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[SCSI] qla4xxx: correct use of cmd->host_scribble
[linux-2.6-block.git] / drivers / scsi / qla4xxx / ql4_fw.h
CommitLineData
afaf5a2d
DS		 1/*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8#ifndef _QLA4X_FW_H
9#define _QLA4X_FW_H
10
11
12#define MAX_PRST_DEV_DB_ENTRIES 64
13#define MIN_DISC_DEV_DB_ENTRY MAX_PRST_DEV_DB_ENTRIES
14#define MAX_DEV_DB_ENTRIES 512
15
16/*************************************************************************
17 *
18 * ISP 4010 I/O Register Set Structure and Definitions
19 *
20 *************************************************************************/
21
22struct port_ctrl_stat_regs {
b2854316
DS		 23 __le32 ext_hw_conf; /* 0x50 R/W */
24 __le32 rsrvd0; /* 0x54 */
25 __le32 port_ctrl; /* 0x58 */
26 __le32 port_status; /* 0x5c */
27 __le32 rsrvd1[32]; /* 0x60-0xdf */
28 __le32 gp_out; /* 0xe0 */
29 __le32 gp_in; /* 0xe4 */
30 __le32 rsrvd2[5]; /* 0xe8-0xfb */
31 __le32 port_err_status; /* 0xfc */
afaf5a2d
DS		 32};
33
34struct host_mem_cfg_regs {
b2854316
DS		 35 __le32 rsrvd0[12]; /* 0x50-0x79 */
36 __le32 req_q_out; /* 0x80 */
37 __le32 rsrvd1[31]; /* 0x84-0xFF */
afaf5a2d
DS		 38};
39
afaf5a2d
DS		 40/* remote register set (access via PCI memory read/write) */
41struct isp_reg {
42#define MBOX_REG_COUNT 8
43 __le32 mailbox[MBOX_REG_COUNT];
44
45 __le32 flash_address; /* 0x20 */
46 __le32 flash_data;
47 __le32 ctrl_status;
48
49 union {
50 struct {
51 __le32 nvram;
52 __le32 reserved1[2]; /* 0x30 */
53 } __attribute__ ((packed)) isp4010;
54 struct {
55 __le32 intr_mask;
56 __le32 nvram; /* 0x30 */
57 __le32 semaphore;
58 } __attribute__ ((packed)) isp4022;
59 } u1;
60
61 __le32 req_q_in; /* SCSI Request Queue Producer Index */
62 __le32 rsp_q_out; /* SCSI Completion Queue Consumer Index */
63
64 __le32 reserved2[4]; /* 0x40 */
65
66 union {
67 struct {
68 __le32 ext_hw_conf; /* 0x50 */
69 __le32 flow_ctrl;
70 __le32 port_ctrl;
71 __le32 port_status;
72
73 __le32 reserved3[8]; /* 0x60 */
74
75 __le32 req_q_out; /* 0x80 */
76
77 __le32 reserved4[23]; /* 0x84 */
78
79 __le32 gp_out; /* 0xe0 */
80 __le32 gp_in;
81
82 __le32 reserved5[5];
83
84 __le32 port_err_status; /* 0xfc */
85 } __attribute__ ((packed)) isp4010;
86 struct {
87 union {
88 struct port_ctrl_stat_regs p0;
89 struct host_mem_cfg_regs p1;
afaf5a2d 90 };
afaf5a2d
DS		 91 } __attribute__ ((packed)) isp4022;
92 } u2;
93}; /* 256 x100 */
94
95
96/* Semaphore Defines for 4010 */
97#define QL4010_DRVR_SEM_BITS 0x00000030
98#define QL4010_GPIO_SEM_BITS 0x000000c0
99#define QL4010_SDRAM_SEM_BITS 0x00000300
100#define QL4010_PHY_SEM_BITS 0x00000c00
101#define QL4010_NVRAM_SEM_BITS 0x00003000
102#define QL4010_FLASH_SEM_BITS 0x0000c000
103
104#define QL4010_DRVR_SEM_MASK 0x00300000
105#define QL4010_GPIO_SEM_MASK 0x00c00000
106#define QL4010_SDRAM_SEM_MASK 0x03000000
107#define QL4010_PHY_SEM_MASK 0x0c000000
108#define QL4010_NVRAM_SEM_MASK 0x30000000
109#define QL4010_FLASH_SEM_MASK 0xc0000000
110
111/* Semaphore Defines for 4022 */
112#define QL4022_RESOURCE_MASK_BASE_CODE 0x7
113#define QL4022_RESOURCE_BITS_BASE_CODE 0x4
114
115
116#define QL4022_DRVR_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (1+16))
117#define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16))
118#define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16))
119#define QL4022_NVRAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (10+16))
120#define QL4022_FLASH_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (13+16))
121
122
123
124/* Page # defines for 4022 */
125#define PORT_CTRL_STAT_PAGE 0 /* 4022 */
126#define HOST_MEM_CFG_PAGE 1 /* 4022 */
127#define LOCAL_RAM_CFG_PAGE 2 /* 4022 */
128#define PROT_STAT_PAGE 3 /* 4022 */
129
130/* Register Mask - sets corresponding mask bits in the upper word */
131static inline uint32_t set_rmask(uint32_t val)
132{
133 return (val & 0xffff) | (val << 16);
134}
135
136
137static inline uint32_t clr_rmask(uint32_t val)
138{
139 return 0 | (val << 16);
140}
141
142/* ctrl_status definitions */
143#define CSR_SCSI_PAGE_SELECT 0x00000003
144#define CSR_SCSI_INTR_ENABLE 0x00000004 /* 4010 */
145#define CSR_SCSI_RESET_INTR 0x00000008
146#define CSR_SCSI_COMPLETION_INTR 0x00000010
147#define CSR_SCSI_PROCESSOR_INTR 0x00000020
148#define CSR_INTR_RISC 0x00000040
149#define CSR_BOOT_ENABLE 0x00000080
150#define CSR_NET_PAGE_SELECT 0x00000300 /* 4010 */
151#define CSR_FUNC_NUM 0x00000700 /* 4022 */
152#define CSR_NET_RESET_INTR 0x00000800 /* 4010 */
153#define CSR_FORCE_SOFT_RESET 0x00002000 /* 4022 */
154#define CSR_FATAL_ERROR 0x00004000
155#define CSR_SOFT_RESET 0x00008000
156#define ISP_CONTROL_FN_MASK CSR_FUNC_NUM
157#define ISP_CONTROL_FN0_SCSI 0x0500
158#define ISP_CONTROL_FN1_SCSI 0x0700
159
160#define INTR_PENDING (CSR_SCSI_COMPLETION_INTR |\
161 CSR_SCSI_PROCESSOR_INTR |\
162 CSR_SCSI_RESET_INTR)
163
164/* ISP InterruptMask definitions */
165#define IMR_SCSI_INTR_ENABLE 0x00000004 /* 4022 */
166
167/* ISP 4022 nvram definitions */
168#define NVR_WRITE_ENABLE 0x00000010 /* 4022 */
169
170/* ISP port_status definitions */
171
172/* ISP Semaphore definitions */
173
174/* ISP General Purpose Output definitions */
b2854316 175#define GPOR_TOPCAT_RESET 0x00000004
afaf5a2d
DS		 176
177/* shadow registers (DMA'd from HA to system memory. read only) */
178struct shadow_regs {
179 /* SCSI Request Queue Consumer Index */
180 __le32 req_q_out; /* 0 x0 R */
181
182 /* SCSI Completion Queue Producer Index */
183 __le32 rsp_q_in; /* 4 x4 R */
184}; /* 8 x8 */
185
186
187/* External hardware configuration register */
188union external_hw_config_reg {
189 struct {
190 /* FIXME: Do we even need this? All values are
191 * referred to by 16 bit quantities. Platform and
192 * endianess issues. */
193 __le32 bReserved0:1;
194 __le32 bSDRAMProtectionMethod:2;
195 __le32 bSDRAMBanks:1;
196 __le32 bSDRAMChipWidth:1;
197 __le32 bSDRAMChipSize:2;
198 __le32 bParityDisable:1;
199 __le32 bExternalMemoryType:1;
200 __le32 bFlashBIOSWriteEnable:1;
201 __le32 bFlashUpperBankSelect:1;
202 __le32 bWriteBurst:2;
203 __le32 bReserved1:3;
204 __le32 bMask:16;
205 };
206 uint32_t Asuint32_t;
207};
208
209/*************************************************************************
210 *
211 * Mailbox Commands Structures and Definitions
212 *
213 *************************************************************************/
214
215/* Mailbox command definitions */
216#define MBOX_CMD_ABOUT_FW 0x0009
b2854316 217#define MBOX_CMD_PING 0x000B
afaf5a2d 218#define MBOX_CMD_LUN_RESET 0x0016
ce545039 219#define MBOX_CMD_TARGET_WARM_RESET 0x0017
d915058f 220#define MBOX_CMD_GET_MANAGEMENT_DATA 0x001E
afaf5a2d
DS		 221#define MBOX_CMD_GET_FW_STATUS 0x001F
222#define MBOX_CMD_SET_ISNS_SERVICE 0x0021
223#define ISNS_DISABLE 0
224#define ISNS_ENABLE 1
d915058f
DS		 225#define MBOX_CMD_COPY_FLASH 0x0024
226#define MBOX_CMD_WRITE_FLASH 0x0025
afaf5a2d
DS		 227#define MBOX_CMD_READ_FLASH 0x0026
228#define MBOX_CMD_CLEAR_DATABASE_ENTRY 0x0031
229#define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT 0x0056
230#define LOGOUT_OPTION_CLOSE_SESSION 0x01
231#define LOGOUT_OPTION_RELOGIN 0x02
232#define MBOX_CMD_EXECUTE_IOCB_A64 0x005A
233#define MBOX_CMD_INITIALIZE_FIRMWARE 0x0060
234#define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK 0x0061
235#define MBOX_CMD_REQUEST_DATABASE_ENTRY 0x0062
236#define MBOX_CMD_SET_DATABASE_ENTRY 0x0063
237#define MBOX_CMD_GET_DATABASE_ENTRY 0x0064
238#define DDB_DS_UNASSIGNED 0x00
239#define DDB_DS_NO_CONNECTION_ACTIVE 0x01
240#define DDB_DS_SESSION_ACTIVE 0x04
241#define DDB_DS_SESSION_FAILED 0x06
242#define DDB_DS_LOGIN_IN_PROCESS 0x07
243#define MBOX_CMD_GET_FW_STATE 0x0069
d915058f
DS		 244#define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A
245#define MBOX_CMD_RESTORE_FACTORY_DEFAULTS 0x0087
b2854316
DS		 246#define MBOX_CMD_SET_ACB 0x0088
247#define MBOX_CMD_GET_ACB 0x0089
248#define MBOX_CMD_DISABLE_ACB 0x008A
249#define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE 0x008B
250#define MBOX_CMD_GET_IPV6_DEST_CACHE 0x008C
251#define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST 0x008D
252#define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST 0x008E
253#define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE 0x0090
254#define MBOX_CMD_GET_IP_ADDR_STATE 0x0091
255#define MBOX_CMD_SEND_IPV6_ROUTER_SOL 0x0092
256#define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR 0x0093
afaf5a2d
DS		 257
258/* Mailbox 1 */
259#define FW_STATE_READY 0x0000
260#define FW_STATE_CONFIG_WAIT 0x0001
2a49a78e 261#define FW_STATE_WAIT_AUTOCONNECT 0x0002
afaf5a2d 262#define FW_STATE_ERROR 0x0004
2a49a78e 263#define FW_STATE_CONFIGURING_IP 0x0008
afaf5a2d
DS		 264
265/* Mailbox 3 */
266#define FW_ADDSTATE_OPTICAL_MEDIA 0x0001
2a49a78e
VC		 267#define FW_ADDSTATE_DHCPv4_ENABLED 0x0002
268#define FW_ADDSTATE_DHCPv4_LEASE_ACQUIRED 0x0004
269#define FW_ADDSTATE_DHCPv4_LEASE_EXPIRED 0x0008
afaf5a2d
DS		 270#define FW_ADDSTATE_LINK_UP 0x0010
271#define FW_ADDSTATE_ISNS_SVC_ENABLED 0x0020
272#define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS 0x006B
273#define MBOX_CMD_CONN_OPEN_SESS_LOGIN 0x0074
274#define MBOX_CMD_GET_CRASH_RECORD 0x0076 /* 4010 only */
275#define MBOX_CMD_GET_CONN_EVENT_LOG 0x0077
276
277/* Mailbox status definitions */
278#define MBOX_COMPLETION_STATUS 4
279#define MBOX_STS_BUSY 0x0007
280#define MBOX_STS_INTERMEDIATE_COMPLETION 0x1000
281#define MBOX_STS_COMMAND_COMPLETE 0x4000
282#define MBOX_STS_COMMAND_ERROR 0x4005
283
284#define MBOX_ASYNC_EVENT_STATUS 8
285#define MBOX_ASTS_SYSTEM_ERROR 0x8002
286#define MBOX_ASTS_REQUEST_TRANSFER_ERROR 0x8003
287#define MBOX_ASTS_RESPONSE_TRANSFER_ERROR 0x8004
288#define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM 0x8005
289#define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED 0x8006
290#define MBOX_ASTS_LINK_UP 0x8010
291#define MBOX_ASTS_LINK_DOWN 0x8011
292#define MBOX_ASTS_DATABASE_CHANGED 0x8014
293#define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED 0x8015
294#define MBOX_ASTS_SELF_TEST_FAILED 0x8016
295#define MBOX_ASTS_LOGIN_FAILED 0x8017
296#define MBOX_ASTS_DNS 0x8018
297#define MBOX_ASTS_HEARTBEAT 0x8019
298#define MBOX_ASTS_NVRAM_INVALID 0x801A
299#define MBOX_ASTS_MAC_ADDRESS_CHANGED 0x801B
300#define MBOX_ASTS_IP_ADDRESS_CHANGED 0x801C
301#define MBOX_ASTS_DHCP_LEASE_EXPIRED 0x801D
302#define MBOX_ASTS_DHCP_LEASE_ACQUIRED 0x801F
303#define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021
b2854316
DS		 304#define MBOX_ASTS_DUPLICATE_IP 0x8025
305#define MBOX_ASTS_ARP_COMPLETE 0x8026
306#define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027
307#define MBOX_ASTS_RESPONSE_QUEUE_FULL 0x8028
308#define MBOX_ASTS_IP_ADDR_STATE_CHANGED 0x8029
309#define MBOX_ASTS_IPV6_PREFIX_EXPIRED 0x802B
310#define MBOX_ASTS_IPV6_ND_PREFIX_IGNORED 0x802C
311#define MBOX_ASTS_IPV6_LCL_PREFIX_IGNORED 0x802D
312#define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD 0x802E
313
afaf5a2d
DS		 314#define ISNS_EVENT_DATA_RECEIVED 0x0000
315#define ISNS_EVENT_CONNECTION_OPENED 0x0001
316#define ISNS_EVENT_CONNECTION_FAILED 0x0002
317#define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR 0x8022
318#define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027
319
320/*************************************************************************/
321
322/* Host Adapter Initialization Control Block (from host) */
b2854316
DS		 323struct addr_ctrl_blk {
324 uint8_t version; /* 00 */
2a49a78e
VC		 325#define IFCB_VER_MIN 0x01
326#define IFCB_VER_MAX 0x02
b2854316 327 uint8_t control; /* 01 */
afaf5a2d 328
b2854316 329 uint16_t fw_options; /* 02-03 */
afaf5a2d
DS		 330#define FWOPT_HEARTBEAT_ENABLE 0x1000
331#define FWOPT_SESSION_MODE 0x0040
332#define FWOPT_INITIATOR_MODE 0x0020
333#define FWOPT_TARGET_MODE 0x0010
334
b2854316
DS		 335 uint16_t exec_throttle; /* 04-05 */
336 uint8_t zio_count; /* 06 */
337 uint8_t res0; /* 07 */
338 uint16_t eth_mtu_size; /* 08-09 */
339 uint16_t add_fw_options; /* 0A-0B */
340
341 uint8_t hb_interval; /* 0C */
342 uint8_t inst_num; /* 0D */
343 uint16_t res1; /* 0E-0F */
344 uint16_t rqq_consumer_idx; /* 10-11 */
345 uint16_t compq_producer_idx; /* 12-13 */
346 uint16_t rqq_len; /* 14-15 */
347 uint16_t compq_len; /* 16-17 */
348 uint32_t rqq_addr_lo; /* 18-1B */
349 uint32_t rqq_addr_hi; /* 1C-1F */
350 uint32_t compq_addr_lo; /* 20-23 */
351 uint32_t compq_addr_hi; /* 24-27 */
352 uint32_t shdwreg_addr_lo; /* 28-2B */
353 uint32_t shdwreg_addr_hi; /* 2C-2F */
354
355 uint16_t iscsi_opts; /* 30-31 */
356 uint16_t ipv4_tcp_opts; /* 32-33 */
357 uint16_t ipv4_ip_opts; /* 34-35 */
2a49a78e 358#define IPOPT_IPv4_PROTOCOL_ENABLE 0x8000
b2854316
DS		 359
360 uint16_t iscsi_max_pdu_size; /* 36-37 */
361 uint8_t ipv4_tos; /* 38 */
362 uint8_t ipv4_ttl; /* 39 */
363 uint8_t acb_version; /* 3A */
2a49a78e
VC		 364#define ACB_NOT_SUPPORTED 0x00
365#define ACB_SUPPORTED 0x02 /* Capable of ACB Version 2
366 Features */
367
b2854316
DS		 368 uint8_t res2; /* 3B */
369 uint16_t def_timeout; /* 3C-3D */
370 uint16_t iscsi_fburst_len; /* 3E-3F */
371 uint16_t iscsi_def_time2wait; /* 40-41 */
372 uint16_t iscsi_def_time2retain; /* 42-43 */
373 uint16_t iscsi_max_outstnd_r2t; /* 44-45 */
374 uint16_t conn_ka_timeout; /* 46-47 */
375 uint16_t ipv4_port; /* 48-49 */
376 uint16_t iscsi_max_burst_len; /* 4A-4B */
377 uint32_t res5; /* 4C-4F */
378 uint8_t ipv4_addr[4]; /* 50-53 */
379 uint16_t ipv4_vlan_tag; /* 54-55 */
380 uint8_t ipv4_addr_state; /* 56 */
381 uint8_t ipv4_cacheid; /* 57 */
382 uint8_t res6[8]; /* 58-5F */
383 uint8_t ipv4_subnet[4]; /* 60-63 */
384 uint8_t res7[12]; /* 64-6F */
385 uint8_t ipv4_gw_addr[4]; /* 70-73 */
386 uint8_t res8[0xc]; /* 74-7F */
387 uint8_t pri_dns_srvr_ip[4];/* 80-83 */
388 uint8_t sec_dns_srvr_ip[4];/* 84-87 */
389 uint16_t min_eph_port; /* 88-89 */
390 uint16_t max_eph_port; /* 8A-8B */
391 uint8_t res9[4]; /* 8C-8F */
392 uint8_t iscsi_alias[32];/* 90-AF */
393 uint8_t res9_1[0x16]; /* B0-C5 */
394 uint16_t tgt_portal_grp;/* C6-C7 */
395 uint8_t abort_timer; /* C8 */
396 uint8_t ipv4_tcp_wsf; /* C9 */
397 uint8_t res10[6]; /* CA-CF */
398 uint8_t ipv4_sec_ip_addr[4]; /* D0-D3 */
399 uint8_t ipv4_dhcp_vid_len; /* D4 */
400 uint8_t ipv4_dhcp_vid[11]; /* D5-DF */
401 uint8_t res11[20]; /* E0-F3 */
402 uint8_t ipv4_dhcp_alt_cid_len; /* F4 */
403 uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */
404 uint8_t iscsi_name[224]; /* 100-1DF */
405 uint8_t res12[32]; /* 1E0-1FF */
406 uint32_t cookie; /* 200-203 */
407 uint16_t ipv6_port; /* 204-205 */
408 uint16_t ipv6_opts; /* 206-207 */
2a49a78e
VC		 409#define IPV6_OPT_IPV6_PROTOCOL_ENABLE 0x8000
410
b2854316 411 uint16_t ipv6_addtl_opts; /* 208-209 */
2a49a78e
VC		 412#define IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE 0x0002 /* Pri ACB
413 Only */
414#define IPV6_ADDOPT_AUTOCONFIG_LINK_LOCAL_ADDR 0x0001
415
b2854316
DS		 416 uint16_t ipv6_tcp_opts; /* 20A-20B */
417 uint8_t ipv6_tcp_wsf; /* 20C */
418 uint16_t ipv6_flow_lbl; /* 20D-20F */
2a49a78e 419 uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */
b2854316
DS		 420 uint16_t ipv6_vlan_tag; /* 220-221 */
421 uint8_t ipv6_lnk_lcl_addr_state;/* 222 */
422 uint8_t ipv6_addr0_state; /* 223 */
423 uint8_t ipv6_addr1_state; /* 224 */
2a49a78e
VC		 424#define IP_ADDRSTATE_UNCONFIGURED 0
425#define IP_ADDRSTATE_INVALID 1
426#define IP_ADDRSTATE_ACQUIRING 2
427#define IP_ADDRSTATE_TENTATIVE 3
428#define IP_ADDRSTATE_DEPRICATED 4
429#define IP_ADDRSTATE_PREFERRED 5
430#define IP_ADDRSTATE_DISABLING 6
431
432 uint8_t ipv6_dflt_rtr_state; /* 225 */
433#define IPV6_RTRSTATE_UNKNOWN 0
434#define IPV6_RTRSTATE_MANUAL 1
435#define IPV6_RTRSTATE_ADVERTISED 3
436#define IPV6_RTRSTATE_STALE 4
437
b2854316
DS		 438 uint8_t ipv6_traffic_class; /* 226 */
439 uint8_t ipv6_hop_limit; /* 227 */
440 uint8_t ipv6_if_id[8]; /* 228-22F */
441 uint8_t ipv6_addr0[16]; /* 230-23F */
442 uint8_t ipv6_addr1[16]; /* 240-24F */
443 uint32_t ipv6_nd_reach_time; /* 250-253 */
444 uint32_t ipv6_nd_rexmit_timer; /* 254-257 */
445 uint32_t ipv6_nd_stale_timeout; /* 258-25B */
446 uint8_t ipv6_dup_addr_detect_count; /* 25C */
447 uint8_t ipv6_cache_id; /* 25D */
448 uint8_t res13[18]; /* 25E-26F */
449 uint32_t ipv6_gw_advrt_mtu; /* 270-273 */
450 uint8_t res14[140]; /* 274-2FF */
451};
452
453struct init_fw_ctrl_blk {
454 struct addr_ctrl_blk pri;
2a49a78e 455/* struct addr_ctrl_blk sec;*/
afaf5a2d
DS		 456};
457
458/*************************************************************************/
459
460struct dev_db_entry {
b2854316 461 uint16_t options; /* 00-01 */
afaf5a2d
DS		 462#define DDB_OPT_DISC_SESSION 0x10
463#define DDB_OPT_TARGET 0x02 /* device is a target */
2a49a78e
VC		 464#define DDB_OPT_IPV6_DEVICE 0x100
465#define DDB_OPT_IPV6_NULL_LINK_LOCAL 0x800 /* post connection */
466#define DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL 0x800 /* pre connection */
afaf5a2d 467
b2854316
DS		 468 uint16_t exec_throttle; /* 02-03 */
469 uint16_t exec_count; /* 04-05 */
470 uint16_t res0; /* 06-07 */
471 uint16_t iscsi_options; /* 08-09 */
472 uint16_t tcp_options; /* 0A-0B */
473 uint16_t ip_options; /* 0C-0D */
474 uint16_t iscsi_max_rcv_data_seg_len; /* 0E-0F */
475 uint32_t res1; /* 10-13 */
476 uint16_t iscsi_max_snd_data_seg_len; /* 14-15 */
477 uint16_t iscsi_first_burst_len; /* 16-17 */
478 uint16_t iscsi_def_time2wait; /* 18-19 */
479 uint16_t iscsi_def_time2retain; /* 1A-1B */
480 uint16_t iscsi_max_outsnd_r2t; /* 1C-1D */
481 uint16_t ka_timeout; /* 1E-1F */
482 uint8_t isid[6]; /* 20-25 big-endian, must be converted
afaf5a2d 483 * to little-endian */
b2854316
DS		 484 uint16_t tsid; /* 26-27 */
485 uint16_t port; /* 28-29 */
486 uint16_t iscsi_max_burst_len; /* 2A-2B */
487 uint16_t def_timeout; /* 2C-2D */
488 uint16_t res2; /* 2E-2F */
489 uint8_t ip_addr[0x10]; /* 30-3F */
490 uint8_t iscsi_alias[0x20]; /* 40-5F */
491 uint8_t tgt_addr[0x20]; /* 60-7F */
492 uint16_t mss; /* 80-81 */
493 uint16_t res3; /* 82-83 */
494 uint16_t lcl_port; /* 84-85 */
495 uint8_t ipv4_tos; /* 86 */
496 uint16_t ipv6_flow_lbl; /* 87-89 */
497 uint8_t res4[0x36]; /* 8A-BF */
498 uint8_t iscsi_name[0xE0]; /* C0-19F : xxzzy Make this a
afaf5a2d
DS		 499 * pointer to a string so we
500 * don't have to reserve soooo
501 * much RAM */
2a49a78e 502 uint8_t link_local_ipv6_addr[0x10]; /* 1A0-1AF */
b2854316
DS		 503 uint8_t res5[0x10]; /* 1B0-1BF */
504 uint16_t ddb_link; /* 1C0-1C1 */
505 uint16_t chap_tbl_idx; /* 1C2-1C3 */
506 uint16_t tgt_portal_grp; /* 1C4-1C5 */
507 uint8_t tcp_xmt_wsf; /* 1C6 */
508 uint8_t tcp_rcv_wsf; /* 1C7 */
509 uint32_t stat_sn; /* 1C8-1CB */
510 uint32_t exp_stat_sn; /* 1CC-1CF */
511 uint8_t res6[0x30]; /* 1D0-1FF */
afaf5a2d
DS		 512};
513
514/*************************************************************************/
515
516/* Flash definitions */
517
518#define FLASH_OFFSET_SYS_INFO 0x02000000
519#define FLASH_DEFAULTBLOCKSIZE 0x20000
520#define FLASH_EOF_OFFSET (FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes
521 * for EOF
522 * signature */
523
524struct sys_info_phys_addr {
525 uint8_t address[6]; /* 00-05 */
526 uint8_t filler[2]; /* 06-07 */
527};
528
529struct flash_sys_info {
530 uint32_t cookie; /* 00-03 */
531 uint32_t physAddrCount; /* 04-07 */
532 struct sys_info_phys_addr physAddr[4]; /* 08-27 */
533 uint8_t vendorId[128]; /* 28-A7 */
534 uint8_t productId[128]; /* A8-127 */
535 uint32_t serialNumber; /* 128-12B */
536
537 /* PCI Configuration values */
538 uint32_t pciDeviceVendor; /* 12C-12F */
539 uint32_t pciDeviceId; /* 130-133 */
540 uint32_t pciSubsysVendor; /* 134-137 */
541 uint32_t pciSubsysId; /* 138-13B */
542
543 /* This validates version 1. */
544 uint32_t crumbs; /* 13C-13F */
545
546 uint32_t enterpriseNumber; /* 140-143 */
547
548 uint32_t mtu; /* 144-147 */
549 uint32_t reserved0; /* 148-14b */
550 uint32_t crumbs2; /* 14c-14f */
551 uint8_t acSerialNumber[16]; /* 150-15f */
552 uint32_t crumbs3; /* 160-16f */
553
554 /* Leave this last in the struct so it is declared invalid if
555 * any new items are added.
556 */
557 uint32_t reserved1[39]; /* 170-1ff */
558}; /* 200 */
559
560struct crash_record {
561 uint16_t fw_major_version; /* 00 - 01 */
562 uint16_t fw_minor_version; /* 02 - 03 */
563 uint16_t fw_patch_version; /* 04 - 05 */
564 uint16_t fw_build_version; /* 06 - 07 */
565
566 uint8_t build_date[16]; /* 08 - 17 */
567 uint8_t build_time[16]; /* 18 - 27 */
568 uint8_t build_user[16]; /* 28 - 37 */
569 uint8_t card_serial_num[16]; /* 38 - 47 */
570
571 uint32_t time_of_crash_in_secs; /* 48 - 4B */
572 uint32_t time_of_crash_in_ms; /* 4C - 4F */
573
574 uint16_t out_RISC_sd_num_frames; /* 50 - 51 */
575 uint16_t OAP_sd_num_words; /* 52 - 53 */
576 uint16_t IAP_sd_num_frames; /* 54 - 55 */
577 uint16_t in_RISC_sd_num_words; /* 56 - 57 */
578
579 uint8_t reserved1[28]; /* 58 - 7F */
580
581 uint8_t out_RISC_reg_dump[256]; /* 80 -17F */
582 uint8_t in_RISC_reg_dump[256]; /*180 -27F */
583 uint8_t in_out_RISC_stack_dump[0]; /*280 - ??? */
584};
585
586struct conn_event_log_entry {
587#define MAX_CONN_EVENT_LOG_ENTRIES 100
588 uint32_t timestamp_sec; /* 00 - 03 seconds since boot */
589 uint32_t timestamp_ms; /* 04 - 07 milliseconds since boot */
590 uint16_t device_index; /* 08 - 09 */
591 uint16_t fw_conn_state; /* 0A - 0B */
592 uint8_t event_type; /* 0C - 0C */
593 uint8_t error_code; /* 0D - 0D */
594 uint16_t error_code_detail; /* 0E - 0F */
595 uint8_t num_consecutive_events; /* 10 - 10 */
596 uint8_t rsvd[3]; /* 11 - 13 */
597};
598
599/*************************************************************************
600 *
601 * IOCB Commands Structures and Definitions
602 *
603 *************************************************************************/
604#define IOCB_MAX_CDB_LEN 16 /* Bytes in a CBD */
605#define IOCB_MAX_SENSEDATA_LEN 32 /* Bytes of sense data */
94bced3c 606#define IOCB_MAX_EXT_SENSEDATA_LEN 60 /* Bytes of extended sense data */
afaf5a2d
DS		 607
608/* IOCB header structure */
609struct qla4_header {
610 uint8_t entryType;
611#define ET_STATUS 0x03
612#define ET_MARKER 0x04
613#define ET_CONT_T1 0x0A
614#define ET_STATUS_CONTINUATION 0x10
615#define ET_CMND_T3 0x19
616#define ET_PASSTHRU0 0x3A
617#define ET_PASSTHRU_STATUS 0x3C
618
619 uint8_t entryStatus;
620 uint8_t systemDefined;
621 uint8_t entryCount;
622
623 /* SyetemDefined definition */
624};
625
626/* Generic queue entry structure*/
627struct queue_entry {
628 uint8_t data[60];
629 uint32_t signature;
630
631};
632
633/* 64 bit addressing segment counts*/
634
635#define COMMAND_SEG_A64 1
636#define CONTINUE_SEG_A64 5
637
638/* 64 bit addressing segment definition*/
639
640struct data_seg_a64 {
641 struct {
642 uint32_t addrLow;
643 uint32_t addrHigh;
644
645 } base;
646
647 uint32_t count;
648
649};
650
651/* Command Type 3 entry structure*/
652
653struct command_t3_entry {
654 struct qla4_header hdr; /* 00-03 */
655
656 uint32_t handle; /* 04-07 */
657 uint16_t target; /* 08-09 */
658 uint16_t connection_id; /* 0A-0B */
659
660 uint8_t control_flags; /* 0C */
661
662 /* data direction (bits 5-6) */
663#define CF_WRITE 0x20
664#define CF_READ 0x40
665#define CF_NO_DATA 0x00
666
667 /* task attributes (bits 2-0) */
668#define CF_HEAD_TAG 0x03
669#define CF_ORDERED_TAG 0x02
670#define CF_SIMPLE_TAG 0x01
671
672 /* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS
673 * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS
674 * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET
675 * PROPERLY.
676 */
677 uint8_t state_flags; /* 0D */
678 uint8_t cmdRefNum; /* 0E */
679 uint8_t reserved1; /* 0F */
680 uint8_t cdb[IOCB_MAX_CDB_LEN]; /* 10-1F */
681 struct scsi_lun lun; /* FCP LUN (BE). */
682 uint32_t cmdSeqNum; /* 28-2B */
683 uint16_t timeout; /* 2C-2D */
684 uint16_t dataSegCnt; /* 2E-2F */
685 uint32_t ttlByteCnt; /* 30-33 */
686 struct data_seg_a64 dataseg[COMMAND_SEG_A64]; /* 34-3F */
687
688};
689
690
691/* Continuation Type 1 entry structure*/
692struct continuation_t1_entry {
693 struct qla4_header hdr;
694
695 struct data_seg_a64 dataseg[CONTINUE_SEG_A64];
696
697};
698
699/* Parameterize for 64 or 32 bits */
700#define COMMAND_SEG COMMAND_SEG_A64
701#define CONTINUE_SEG CONTINUE_SEG_A64
702
703#define ET_COMMAND ET_CMND_T3
704#define ET_CONTINUE ET_CONT_T1
705
706/* Marker entry structure*/
1c3f0b8e 707struct qla4_marker_entry {
afaf5a2d
DS		 708 struct qla4_header hdr; /* 00-03 */
709
710 uint32_t system_defined; /* 04-07 */
711 uint16_t target; /* 08-09 */
712 uint16_t modifier; /* 0A-0B */
9d562913
DS		 713#define MM_LUN_RESET 0
714#define MM_TGT_WARM_RESET 1
afaf5a2d
DS		 715
716 uint16_t flags; /* 0C-0D */
717 uint16_t reserved1; /* 0E-0F */
718 struct scsi_lun lun; /* FCP LUN (BE). */
719 uint64_t reserved2; /* 18-1F */
720 uint64_t reserved3; /* 20-27 */
721 uint64_t reserved4; /* 28-2F */
722 uint64_t reserved5; /* 30-37 */
723 uint64_t reserved6; /* 38-3F */
724};
725
726/* Status entry structure*/
727struct status_entry {
728 struct qla4_header hdr; /* 00-03 */
729
730 uint32_t handle; /* 04-07 */
731
732 uint8_t scsiStatus; /* 08 */
733#define SCSI_CHECK_CONDITION 0x02
734
735 uint8_t iscsiFlags; /* 09 */
736#define ISCSI_FLAG_RESIDUAL_UNDER 0x02
737#define ISCSI_FLAG_RESIDUAL_OVER 0x04
738
739 uint8_t iscsiResponse; /* 0A */
740
741 uint8_t completionStatus; /* 0B */
742#define SCS_COMPLETE 0x00
743#define SCS_INCOMPLETE 0x01
744#define SCS_RESET_OCCURRED 0x04
745#define SCS_ABORTED 0x05
746#define SCS_TIMEOUT 0x06
747#define SCS_DATA_OVERRUN 0x07
748#define SCS_DATA_UNDERRUN 0x15
749#define SCS_QUEUE_FULL 0x1C
750#define SCS_DEVICE_UNAVAILABLE 0x28
751#define SCS_DEVICE_LOGGED_OUT 0x29
752
753 uint8_t reserved1; /* 0C */
754
755 /* state_flags MUST be at the same location as state_flags in
756 * the Command_T3/4_Entry */
757 uint8_t state_flags; /* 0D */
758
759 uint16_t senseDataByteCnt; /* 0E-0F */
760 uint32_t residualByteCnt; /* 10-13 */
761 uint32_t bidiResidualByteCnt; /* 14-17 */
762 uint32_t expSeqNum; /* 18-1B */
763 uint32_t maxCmdSeqNum; /* 1C-1F */
764 uint8_t senseData[IOCB_MAX_SENSEDATA_LEN]; /* 20-3F */
765
766};
767
94bced3c
KH		 768/* Status Continuation entry */
769struct status_cont_entry {
770 struct qla4_header hdr; /* 00-03 */
771 uint8_t ext_sense_data[IOCB_MAX_EXT_SENSEDATA_LEN]; /* 04-63 */
772};
773
afaf5a2d
DS		 774struct passthru0 {
775 struct qla4_header hdr; /* 00-03 */
776 uint32_t handle; /* 04-07 */
777 uint16_t target; /* 08-09 */
778 uint16_t connectionID; /* 0A-0B */
779#define ISNS_DEFAULT_SERVER_CONN_ID ((uint16_t)0x8000)
780
781 uint16_t controlFlags; /* 0C-0D */
782#define PT_FLAG_ETHERNET_FRAME 0x8000
783#define PT_FLAG_ISNS_PDU 0x8000
784#define PT_FLAG_SEND_BUFFER 0x0200
785#define PT_FLAG_WAIT_4_RESPONSE 0x0100
786
787 uint16_t timeout; /* 0E-0F */
788#define PT_DEFAULT_TIMEOUT 30 /* seconds */
789
790 struct data_seg_a64 outDataSeg64; /* 10-1B */
791 uint32_t res1; /* 1C-1F */
792 struct data_seg_a64 inDataSeg64; /* 20-2B */
793 uint8_t res2[20]; /* 2C-3F */
794};
795
796struct passthru_status {
797 struct qla4_header hdr; /* 00-03 */
798 uint32_t handle; /* 04-07 */
799 uint16_t target; /* 08-09 */
800 uint16_t connectionID; /* 0A-0B */
801
802 uint8_t completionStatus; /* 0C */
803#define PASSTHRU_STATUS_COMPLETE 0x01
804
805 uint8_t residualFlags; /* 0D */
806
807 uint16_t timeout; /* 0E-0F */
808 uint16_t portNumber; /* 10-11 */
809 uint8_t res1[10]; /* 12-1B */
810 uint32_t outResidual; /* 1C-1F */
811 uint8_t res2[12]; /* 20-2B */
812 uint32_t inResidual; /* 2C-2F */
813 uint8_t res4[16]; /* 30-3F */
814};
815
816#endif /* _QLA4X_FW_H */
Linux 6.x block layer and io_uring tree(s)