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afaf5a2d DS |
1 | /* |
2 | * QLogic iSCSI HBA Driver | |
7d01d069 | 3 | * Copyright (c) 2003-2010 QLogic Corporation |
afaf5a2d DS |
4 | * |
5 | * See LICENSE.qla4xxx for copyright and licensing details. | |
6 | */ | |
7 | ||
8 | #ifndef _QLA4X_FW_H | |
9 | #define _QLA4X_FW_H | |
10 | ||
11 | ||
12 | #define MAX_PRST_DEV_DB_ENTRIES 64 | |
13 | #define MIN_DISC_DEV_DB_ENTRY MAX_PRST_DEV_DB_ENTRIES | |
f4f5df23 | 14 | #define MAX_DEV_DB_ENTRIES 512 |
13483730 | 15 | #define MAX_DEV_DB_ENTRIES_40XX 256 |
afaf5a2d DS |
16 | |
17 | /************************************************************************* | |
18 | * | |
19 | * ISP 4010 I/O Register Set Structure and Definitions | |
20 | * | |
21 | *************************************************************************/ | |
22 | ||
23 | struct port_ctrl_stat_regs { | |
b2854316 DS |
24 | __le32 ext_hw_conf; /* 0x50 R/W */ |
25 | __le32 rsrvd0; /* 0x54 */ | |
26 | __le32 port_ctrl; /* 0x58 */ | |
27 | __le32 port_status; /* 0x5c */ | |
28 | __le32 rsrvd1[32]; /* 0x60-0xdf */ | |
29 | __le32 gp_out; /* 0xe0 */ | |
30 | __le32 gp_in; /* 0xe4 */ | |
31 | __le32 rsrvd2[5]; /* 0xe8-0xfb */ | |
32 | __le32 port_err_status; /* 0xfc */ | |
afaf5a2d DS |
33 | }; |
34 | ||
35 | struct host_mem_cfg_regs { | |
b2854316 DS |
36 | __le32 rsrvd0[12]; /* 0x50-0x79 */ |
37 | __le32 req_q_out; /* 0x80 */ | |
38 | __le32 rsrvd1[31]; /* 0x84-0xFF */ | |
afaf5a2d DS |
39 | }; |
40 | ||
f4f5df23 VC |
41 | /* |
42 | * ISP 82xx I/O Register Set structure definitions. | |
43 | */ | |
44 | struct device_reg_82xx { | |
45 | __le32 req_q_out; /* 0x0000 (R): Request Queue out-Pointer. */ | |
46 | __le32 reserve1[63]; /* Request Queue out-Pointer. (64 * 4) */ | |
47 | __le32 rsp_q_in; /* 0x0100 (R/W): Response Queue In-Pointer. */ | |
48 | __le32 reserve2[63]; /* Response Queue In-Pointer. */ | |
49 | __le32 rsp_q_out; /* 0x0200 (R/W): Response Queue Out-Pointer. */ | |
50 | __le32 reserve3[63]; /* Response Queue Out-Pointer. */ | |
51 | ||
52 | __le32 mailbox_in[8]; /* 0x0300 (R/W): Mail box In registers */ | |
53 | __le32 reserve4[24]; | |
54 | __le32 hint; /* 0x0380 (R/W): Host interrupt register */ | |
55 | #define HINT_MBX_INT_PENDING BIT_0 | |
56 | __le32 reserve5[31]; | |
57 | __le32 mailbox_out[8]; /* 0x0400 (R): Mail box Out registers */ | |
58 | __le32 reserve6[56]; | |
59 | ||
60 | __le32 host_status; /* Offset 0x500 (R): host status */ | |
61 | #define HSRX_RISC_MB_INT BIT_0 /* RISC to Host Mailbox interrupt */ | |
62 | #define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */ | |
63 | ||
64 | __le32 host_int; /* Offset 0x0504 (R/W): Interrupt status. */ | |
65 | #define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */ | |
66 | }; | |
67 | ||
afaf5a2d DS |
68 | /* remote register set (access via PCI memory read/write) */ |
69 | struct isp_reg { | |
70 | #define MBOX_REG_COUNT 8 | |
71 | __le32 mailbox[MBOX_REG_COUNT]; | |
72 | ||
73 | __le32 flash_address; /* 0x20 */ | |
74 | __le32 flash_data; | |
75 | __le32 ctrl_status; | |
76 | ||
77 | union { | |
78 | struct { | |
79 | __le32 nvram; | |
80 | __le32 reserved1[2]; /* 0x30 */ | |
81 | } __attribute__ ((packed)) isp4010; | |
82 | struct { | |
83 | __le32 intr_mask; | |
84 | __le32 nvram; /* 0x30 */ | |
85 | __le32 semaphore; | |
86 | } __attribute__ ((packed)) isp4022; | |
87 | } u1; | |
88 | ||
89 | __le32 req_q_in; /* SCSI Request Queue Producer Index */ | |
90 | __le32 rsp_q_out; /* SCSI Completion Queue Consumer Index */ | |
91 | ||
92 | __le32 reserved2[4]; /* 0x40 */ | |
93 | ||
94 | union { | |
95 | struct { | |
96 | __le32 ext_hw_conf; /* 0x50 */ | |
97 | __le32 flow_ctrl; | |
98 | __le32 port_ctrl; | |
99 | __le32 port_status; | |
100 | ||
101 | __le32 reserved3[8]; /* 0x60 */ | |
102 | ||
103 | __le32 req_q_out; /* 0x80 */ | |
104 | ||
105 | __le32 reserved4[23]; /* 0x84 */ | |
106 | ||
107 | __le32 gp_out; /* 0xe0 */ | |
108 | __le32 gp_in; | |
109 | ||
110 | __le32 reserved5[5]; | |
111 | ||
112 | __le32 port_err_status; /* 0xfc */ | |
113 | } __attribute__ ((packed)) isp4010; | |
114 | struct { | |
115 | union { | |
116 | struct port_ctrl_stat_regs p0; | |
117 | struct host_mem_cfg_regs p1; | |
afaf5a2d | 118 | }; |
afaf5a2d DS |
119 | } __attribute__ ((packed)) isp4022; |
120 | } u2; | |
121 | }; /* 256 x100 */ | |
122 | ||
123 | ||
124 | /* Semaphore Defines for 4010 */ | |
125 | #define QL4010_DRVR_SEM_BITS 0x00000030 | |
126 | #define QL4010_GPIO_SEM_BITS 0x000000c0 | |
127 | #define QL4010_SDRAM_SEM_BITS 0x00000300 | |
128 | #define QL4010_PHY_SEM_BITS 0x00000c00 | |
129 | #define QL4010_NVRAM_SEM_BITS 0x00003000 | |
130 | #define QL4010_FLASH_SEM_BITS 0x0000c000 | |
131 | ||
132 | #define QL4010_DRVR_SEM_MASK 0x00300000 | |
133 | #define QL4010_GPIO_SEM_MASK 0x00c00000 | |
134 | #define QL4010_SDRAM_SEM_MASK 0x03000000 | |
135 | #define QL4010_PHY_SEM_MASK 0x0c000000 | |
136 | #define QL4010_NVRAM_SEM_MASK 0x30000000 | |
137 | #define QL4010_FLASH_SEM_MASK 0xc0000000 | |
138 | ||
139 | /* Semaphore Defines for 4022 */ | |
140 | #define QL4022_RESOURCE_MASK_BASE_CODE 0x7 | |
141 | #define QL4022_RESOURCE_BITS_BASE_CODE 0x4 | |
142 | ||
143 | ||
144 | #define QL4022_DRVR_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (1+16)) | |
145 | #define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16)) | |
146 | #define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16)) | |
147 | #define QL4022_NVRAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (10+16)) | |
148 | #define QL4022_FLASH_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (13+16)) | |
149 | ||
2a991c21 MR |
150 | /* nvram address for 4032 */ |
151 | #define NVRAM_PORT0_BOOT_MODE 0x03b1 | |
152 | #define NVRAM_PORT0_BOOT_PRI_TGT 0x03b2 | |
153 | #define NVRAM_PORT0_BOOT_SEC_TGT 0x03bb | |
154 | #define NVRAM_PORT1_BOOT_MODE 0x07b1 | |
155 | #define NVRAM_PORT1_BOOT_PRI_TGT 0x07b2 | |
156 | #define NVRAM_PORT1_BOOT_SEC_TGT 0x07bb | |
afaf5a2d DS |
157 | |
158 | ||
159 | /* Page # defines for 4022 */ | |
160 | #define PORT_CTRL_STAT_PAGE 0 /* 4022 */ | |
161 | #define HOST_MEM_CFG_PAGE 1 /* 4022 */ | |
162 | #define LOCAL_RAM_CFG_PAGE 2 /* 4022 */ | |
163 | #define PROT_STAT_PAGE 3 /* 4022 */ | |
164 | ||
165 | /* Register Mask - sets corresponding mask bits in the upper word */ | |
166 | static inline uint32_t set_rmask(uint32_t val) | |
167 | { | |
168 | return (val & 0xffff) | (val << 16); | |
169 | } | |
170 | ||
171 | ||
172 | static inline uint32_t clr_rmask(uint32_t val) | |
173 | { | |
174 | return 0 | (val << 16); | |
175 | } | |
176 | ||
177 | /* ctrl_status definitions */ | |
178 | #define CSR_SCSI_PAGE_SELECT 0x00000003 | |
179 | #define CSR_SCSI_INTR_ENABLE 0x00000004 /* 4010 */ | |
180 | #define CSR_SCSI_RESET_INTR 0x00000008 | |
181 | #define CSR_SCSI_COMPLETION_INTR 0x00000010 | |
182 | #define CSR_SCSI_PROCESSOR_INTR 0x00000020 | |
183 | #define CSR_INTR_RISC 0x00000040 | |
184 | #define CSR_BOOT_ENABLE 0x00000080 | |
185 | #define CSR_NET_PAGE_SELECT 0x00000300 /* 4010 */ | |
186 | #define CSR_FUNC_NUM 0x00000700 /* 4022 */ | |
187 | #define CSR_NET_RESET_INTR 0x00000800 /* 4010 */ | |
188 | #define CSR_FORCE_SOFT_RESET 0x00002000 /* 4022 */ | |
189 | #define CSR_FATAL_ERROR 0x00004000 | |
190 | #define CSR_SOFT_RESET 0x00008000 | |
191 | #define ISP_CONTROL_FN_MASK CSR_FUNC_NUM | |
192 | #define ISP_CONTROL_FN0_SCSI 0x0500 | |
193 | #define ISP_CONTROL_FN1_SCSI 0x0700 | |
194 | ||
195 | #define INTR_PENDING (CSR_SCSI_COMPLETION_INTR |\ | |
196 | CSR_SCSI_PROCESSOR_INTR |\ | |
197 | CSR_SCSI_RESET_INTR) | |
198 | ||
199 | /* ISP InterruptMask definitions */ | |
200 | #define IMR_SCSI_INTR_ENABLE 0x00000004 /* 4022 */ | |
201 | ||
202 | /* ISP 4022 nvram definitions */ | |
203 | #define NVR_WRITE_ENABLE 0x00000010 /* 4022 */ | |
204 | ||
7c07d139 HZ |
205 | #define QL4010_NVRAM_SIZE 0x200 |
206 | #define QL40X2_NVRAM_SIZE 0x800 | |
207 | ||
afaf5a2d DS |
208 | /* ISP port_status definitions */ |
209 | ||
210 | /* ISP Semaphore definitions */ | |
211 | ||
212 | /* ISP General Purpose Output definitions */ | |
b2854316 | 213 | #define GPOR_TOPCAT_RESET 0x00000004 |
afaf5a2d DS |
214 | |
215 | /* shadow registers (DMA'd from HA to system memory. read only) */ | |
216 | struct shadow_regs { | |
217 | /* SCSI Request Queue Consumer Index */ | |
218 | __le32 req_q_out; /* 0 x0 R */ | |
219 | ||
220 | /* SCSI Completion Queue Producer Index */ | |
221 | __le32 rsp_q_in; /* 4 x4 R */ | |
222 | }; /* 8 x8 */ | |
223 | ||
224 | ||
225 | /* External hardware configuration register */ | |
226 | union external_hw_config_reg { | |
227 | struct { | |
228 | /* FIXME: Do we even need this? All values are | |
229 | * referred to by 16 bit quantities. Platform and | |
230 | * endianess issues. */ | |
231 | __le32 bReserved0:1; | |
232 | __le32 bSDRAMProtectionMethod:2; | |
233 | __le32 bSDRAMBanks:1; | |
234 | __le32 bSDRAMChipWidth:1; | |
235 | __le32 bSDRAMChipSize:2; | |
236 | __le32 bParityDisable:1; | |
237 | __le32 bExternalMemoryType:1; | |
238 | __le32 bFlashBIOSWriteEnable:1; | |
239 | __le32 bFlashUpperBankSelect:1; | |
240 | __le32 bWriteBurst:2; | |
241 | __le32 bReserved1:3; | |
242 | __le32 bMask:16; | |
243 | }; | |
244 | uint32_t Asuint32_t; | |
245 | }; | |
246 | ||
f4f5df23 VC |
247 | /* 82XX Support start */ |
248 | /* 82xx Default FLT Addresses */ | |
249 | #define FA_FLASH_LAYOUT_ADDR_82 0xFC400 | |
250 | #define FA_FLASH_DESCR_ADDR_82 0xFC000 | |
251 | #define FA_BOOT_LOAD_ADDR_82 0x04000 | |
252 | #define FA_BOOT_CODE_ADDR_82 0x20000 | |
253 | #define FA_RISC_CODE_ADDR_82 0x40000 | |
254 | #define FA_GOLD_RISC_CODE_ADDR_82 0x80000 | |
4549415a LC |
255 | #define FA_FLASH_ISCSI_CHAP 0x540000 |
256 | #define FA_FLASH_CHAP_SIZE 0xC0000 | |
f4f5df23 VC |
257 | |
258 | /* Flash Description Table */ | |
259 | struct qla_fdt_layout { | |
260 | uint8_t sig[4]; | |
261 | uint16_t version; | |
262 | uint16_t len; | |
263 | uint16_t checksum; | |
264 | uint8_t unused1[2]; | |
265 | uint8_t model[16]; | |
266 | uint16_t man_id; | |
267 | uint16_t id; | |
268 | uint8_t flags; | |
269 | uint8_t erase_cmd; | |
270 | uint8_t alt_erase_cmd; | |
271 | uint8_t wrt_enable_cmd; | |
272 | uint8_t wrt_enable_bits; | |
273 | uint8_t wrt_sts_reg_cmd; | |
274 | uint8_t unprotect_sec_cmd; | |
275 | uint8_t read_man_id_cmd; | |
276 | uint32_t block_size; | |
277 | uint32_t alt_block_size; | |
278 | uint32_t flash_size; | |
279 | uint32_t wrt_enable_data; | |
280 | uint8_t read_id_addr_len; | |
281 | uint8_t wrt_disable_bits; | |
282 | uint8_t read_dev_id_len; | |
283 | uint8_t chip_erase_cmd; | |
284 | uint16_t read_timeout; | |
285 | uint8_t protect_sec_cmd; | |
286 | uint8_t unused2[65]; | |
287 | }; | |
288 | ||
289 | /* Flash Layout Table */ | |
290 | ||
291 | struct qla_flt_location { | |
292 | uint8_t sig[4]; | |
293 | uint16_t start_lo; | |
294 | uint16_t start_hi; | |
295 | uint8_t version; | |
296 | uint8_t unused[5]; | |
297 | uint16_t checksum; | |
298 | }; | |
299 | ||
300 | struct qla_flt_header { | |
301 | uint16_t version; | |
302 | uint16_t length; | |
303 | uint16_t checksum; | |
304 | uint16_t unused; | |
305 | }; | |
306 | ||
307 | /* 82xx FLT Regions */ | |
308 | #define FLT_REG_FDT 0x1a | |
309 | #define FLT_REG_FLT 0x1c | |
310 | #define FLT_REG_BOOTLOAD_82 0x72 | |
311 | #define FLT_REG_FW_82 0x74 | |
93823956 | 312 | #define FLT_REG_FW_82_1 0x97 |
f4f5df23 VC |
313 | #define FLT_REG_GOLD_FW_82 0x75 |
314 | #define FLT_REG_BOOT_CODE_82 0x78 | |
2a991c21 | 315 | #define FLT_REG_ISCSI_PARAM 0x65 |
4549415a | 316 | #define FLT_REG_ISCSI_CHAP 0x63 |
f4f5df23 VC |
317 | |
318 | struct qla_flt_region { | |
319 | uint32_t code; | |
320 | uint32_t size; | |
321 | uint32_t start; | |
322 | uint32_t end; | |
323 | }; | |
324 | ||
afaf5a2d DS |
325 | /************************************************************************* |
326 | * | |
327 | * Mailbox Commands Structures and Definitions | |
328 | * | |
329 | *************************************************************************/ | |
330 | ||
331 | /* Mailbox command definitions */ | |
332 | #define MBOX_CMD_ABOUT_FW 0x0009 | |
b2854316 | 333 | #define MBOX_CMD_PING 0x000B |
c0b9d3f7 VC |
334 | #define PING_IPV6_PROTOCOL_ENABLE 0x1 |
335 | #define PING_IPV6_LINKLOCAL_ADDR 0x4 | |
336 | #define PING_IPV6_ADDR0 0x8 | |
337 | #define PING_IPV6_ADDR1 0xC | |
f4f5df23 VC |
338 | #define MBOX_CMD_ENABLE_INTRS 0x0010 |
339 | #define INTR_DISABLE 0 | |
340 | #define INTR_ENABLE 1 | |
341 | #define MBOX_CMD_STOP_FW 0x0014 | |
09a0f719 | 342 | #define MBOX_CMD_ABORT_TASK 0x0015 |
afaf5a2d | 343 | #define MBOX_CMD_LUN_RESET 0x0016 |
ce545039 | 344 | #define MBOX_CMD_TARGET_WARM_RESET 0x0017 |
d915058f | 345 | #define MBOX_CMD_GET_MANAGEMENT_DATA 0x001E |
afaf5a2d DS |
346 | #define MBOX_CMD_GET_FW_STATUS 0x001F |
347 | #define MBOX_CMD_SET_ISNS_SERVICE 0x0021 | |
348 | #define ISNS_DISABLE 0 | |
349 | #define ISNS_ENABLE 1 | |
d915058f DS |
350 | #define MBOX_CMD_COPY_FLASH 0x0024 |
351 | #define MBOX_CMD_WRITE_FLASH 0x0025 | |
afaf5a2d DS |
352 | #define MBOX_CMD_READ_FLASH 0x0026 |
353 | #define MBOX_CMD_CLEAR_DATABASE_ENTRY 0x0031 | |
b3a271a9 | 354 | #define MBOX_CMD_CONN_OPEN 0x0074 |
afaf5a2d | 355 | #define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT 0x0056 |
b3a271a9 MR |
356 | #define LOGOUT_OPTION_CLOSE_SESSION 0x0002 |
357 | #define LOGOUT_OPTION_RELOGIN 0x0004 | |
358 | #define LOGOUT_OPTION_FREE_DDB 0x0008 | |
afaf5a2d DS |
359 | #define MBOX_CMD_EXECUTE_IOCB_A64 0x005A |
360 | #define MBOX_CMD_INITIALIZE_FIRMWARE 0x0060 | |
361 | #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK 0x0061 | |
362 | #define MBOX_CMD_REQUEST_DATABASE_ENTRY 0x0062 | |
363 | #define MBOX_CMD_SET_DATABASE_ENTRY 0x0063 | |
364 | #define MBOX_CMD_GET_DATABASE_ENTRY 0x0064 | |
365 | #define DDB_DS_UNASSIGNED 0x00 | |
366 | #define DDB_DS_NO_CONNECTION_ACTIVE 0x01 | |
b3a271a9 | 367 | #define DDB_DS_DISCOVERY 0x02 |
afaf5a2d DS |
368 | #define DDB_DS_SESSION_ACTIVE 0x04 |
369 | #define DDB_DS_SESSION_FAILED 0x06 | |
370 | #define DDB_DS_LOGIN_IN_PROCESS 0x07 | |
371 | #define MBOX_CMD_GET_FW_STATE 0x0069 | |
d915058f | 372 | #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A |
f4f5df23 | 373 | #define MBOX_CMD_GET_SYS_INFO 0x0078 |
7c07d139 HZ |
374 | #define MBOX_CMD_GET_NVRAM 0x0078 /* For 40xx */ |
375 | #define MBOX_CMD_SET_NVRAM 0x0079 /* For 40xx */ | |
d915058f | 376 | #define MBOX_CMD_RESTORE_FACTORY_DEFAULTS 0x0087 |
b2854316 DS |
377 | #define MBOX_CMD_SET_ACB 0x0088 |
378 | #define MBOX_CMD_GET_ACB 0x0089 | |
379 | #define MBOX_CMD_DISABLE_ACB 0x008A | |
380 | #define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE 0x008B | |
381 | #define MBOX_CMD_GET_IPV6_DEST_CACHE 0x008C | |
382 | #define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST 0x008D | |
383 | #define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST 0x008E | |
384 | #define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE 0x0090 | |
385 | #define MBOX_CMD_GET_IP_ADDR_STATE 0x0091 | |
386 | #define MBOX_CMD_SEND_IPV6_ROUTER_SOL 0x0092 | |
387 | #define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR 0x0093 | |
068237c8 TP |
388 | #define MBOX_CMD_MINIDUMP 0x0129 |
389 | ||
390 | /* Minidump subcommand */ | |
391 | #define MINIDUMP_GET_SIZE_SUBCOMMAND 0x00 | |
392 | #define MINIDUMP_GET_TMPLT_SUBCOMMAND 0x01 | |
afaf5a2d DS |
393 | |
394 | /* Mailbox 1 */ | |
395 | #define FW_STATE_READY 0x0000 | |
396 | #define FW_STATE_CONFIG_WAIT 0x0001 | |
2a49a78e | 397 | #define FW_STATE_WAIT_AUTOCONNECT 0x0002 |
afaf5a2d | 398 | #define FW_STATE_ERROR 0x0004 |
2a49a78e | 399 | #define FW_STATE_CONFIGURING_IP 0x0008 |
afaf5a2d DS |
400 | |
401 | /* Mailbox 3 */ | |
402 | #define FW_ADDSTATE_OPTICAL_MEDIA 0x0001 | |
2a49a78e VC |
403 | #define FW_ADDSTATE_DHCPv4_ENABLED 0x0002 |
404 | #define FW_ADDSTATE_DHCPv4_LEASE_ACQUIRED 0x0004 | |
405 | #define FW_ADDSTATE_DHCPv4_LEASE_EXPIRED 0x0008 | |
afaf5a2d DS |
406 | #define FW_ADDSTATE_LINK_UP 0x0010 |
407 | #define FW_ADDSTATE_ISNS_SVC_ENABLED 0x0020 | |
3254dbe9 VC |
408 | #define FW_ADDSTATE_LINK_SPEED_10MBPS 0x0100 |
409 | #define FW_ADDSTATE_LINK_SPEED_100MBPS 0x0200 | |
410 | #define FW_ADDSTATE_LINK_SPEED_1GBPS 0x0400 | |
411 | #define FW_ADDSTATE_LINK_SPEED_10GBPS 0x0800 | |
b3a271a9 | 412 | |
afaf5a2d | 413 | #define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS 0x006B |
b3a271a9 MR |
414 | #define IPV6_DEFAULT_DDB_ENTRY 0x0001 |
415 | ||
afaf5a2d DS |
416 | #define MBOX_CMD_CONN_OPEN_SESS_LOGIN 0x0074 |
417 | #define MBOX_CMD_GET_CRASH_RECORD 0x0076 /* 4010 only */ | |
418 | #define MBOX_CMD_GET_CONN_EVENT_LOG 0x0077 | |
419 | ||
420 | /* Mailbox status definitions */ | |
421 | #define MBOX_COMPLETION_STATUS 4 | |
422 | #define MBOX_STS_BUSY 0x0007 | |
423 | #define MBOX_STS_INTERMEDIATE_COMPLETION 0x1000 | |
424 | #define MBOX_STS_COMMAND_COMPLETE 0x4000 | |
425 | #define MBOX_STS_COMMAND_ERROR 0x4005 | |
426 | ||
427 | #define MBOX_ASYNC_EVENT_STATUS 8 | |
428 | #define MBOX_ASTS_SYSTEM_ERROR 0x8002 | |
429 | #define MBOX_ASTS_REQUEST_TRANSFER_ERROR 0x8003 | |
430 | #define MBOX_ASTS_RESPONSE_TRANSFER_ERROR 0x8004 | |
431 | #define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM 0x8005 | |
432 | #define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED 0x8006 | |
433 | #define MBOX_ASTS_LINK_UP 0x8010 | |
434 | #define MBOX_ASTS_LINK_DOWN 0x8011 | |
435 | #define MBOX_ASTS_DATABASE_CHANGED 0x8014 | |
436 | #define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED 0x8015 | |
437 | #define MBOX_ASTS_SELF_TEST_FAILED 0x8016 | |
438 | #define MBOX_ASTS_LOGIN_FAILED 0x8017 | |
439 | #define MBOX_ASTS_DNS 0x8018 | |
440 | #define MBOX_ASTS_HEARTBEAT 0x8019 | |
441 | #define MBOX_ASTS_NVRAM_INVALID 0x801A | |
442 | #define MBOX_ASTS_MAC_ADDRESS_CHANGED 0x801B | |
443 | #define MBOX_ASTS_IP_ADDRESS_CHANGED 0x801C | |
444 | #define MBOX_ASTS_DHCP_LEASE_EXPIRED 0x801D | |
445 | #define MBOX_ASTS_DHCP_LEASE_ACQUIRED 0x801F | |
446 | #define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021 | |
b2854316 DS |
447 | #define MBOX_ASTS_DUPLICATE_IP 0x8025 |
448 | #define MBOX_ASTS_ARP_COMPLETE 0x8026 | |
449 | #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027 | |
450 | #define MBOX_ASTS_RESPONSE_QUEUE_FULL 0x8028 | |
451 | #define MBOX_ASTS_IP_ADDR_STATE_CHANGED 0x8029 | |
452 | #define MBOX_ASTS_IPV6_PREFIX_EXPIRED 0x802B | |
453 | #define MBOX_ASTS_IPV6_ND_PREFIX_IGNORED 0x802C | |
454 | #define MBOX_ASTS_IPV6_LCL_PREFIX_IGNORED 0x802D | |
455 | #define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD 0x802E | |
6434080b SS |
456 | #define MBOX_ASTS_TXSCVR_INSERTED 0x8130 |
457 | #define MBOX_ASTS_TXSCVR_REMOVED 0x8131 | |
b2854316 | 458 | |
afaf5a2d DS |
459 | #define ISNS_EVENT_DATA_RECEIVED 0x0000 |
460 | #define ISNS_EVENT_CONNECTION_OPENED 0x0001 | |
461 | #define ISNS_EVENT_CONNECTION_FAILED 0x0002 | |
462 | #define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR 0x8022 | |
463 | #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027 | |
464 | ||
f4f5df23 VC |
465 | /* ACB State Defines */ |
466 | #define ACB_STATE_UNCONFIGURED 0x00 | |
467 | #define ACB_STATE_INVALID 0x01 | |
468 | #define ACB_STATE_ACQUIRING 0x02 | |
469 | #define ACB_STATE_TENTATIVE 0x03 | |
470 | #define ACB_STATE_DEPRICATED 0x04 | |
471 | #define ACB_STATE_VALID 0x05 | |
472 | #define ACB_STATE_DISABLING 0x06 | |
473 | ||
d00efe3f MC |
474 | /* FLASH offsets */ |
475 | #define FLASH_SEGMENT_IFCB 0x04000000 | |
476 | ||
477 | #define FLASH_OPT_RMW_HOLD 0 | |
478 | #define FLASH_OPT_RMW_INIT 1 | |
479 | #define FLASH_OPT_COMMIT 2 | |
480 | #define FLASH_OPT_RMW_COMMIT 3 | |
481 | ||
afaf5a2d DS |
482 | /*************************************************************************/ |
483 | ||
484 | /* Host Adapter Initialization Control Block (from host) */ | |
b2854316 DS |
485 | struct addr_ctrl_blk { |
486 | uint8_t version; /* 00 */ | |
2a49a78e VC |
487 | #define IFCB_VER_MIN 0x01 |
488 | #define IFCB_VER_MAX 0x02 | |
b2854316 | 489 | uint8_t control; /* 01 */ |
afaf5a2d | 490 | |
b2854316 | 491 | uint16_t fw_options; /* 02-03 */ |
afaf5a2d DS |
492 | #define FWOPT_HEARTBEAT_ENABLE 0x1000 |
493 | #define FWOPT_SESSION_MODE 0x0040 | |
494 | #define FWOPT_INITIATOR_MODE 0x0020 | |
495 | #define FWOPT_TARGET_MODE 0x0010 | |
2657c800 | 496 | #define FWOPT_ENABLE_CRBDB 0x8000 |
afaf5a2d | 497 | |
b2854316 DS |
498 | uint16_t exec_throttle; /* 04-05 */ |
499 | uint8_t zio_count; /* 06 */ | |
500 | uint8_t res0; /* 07 */ | |
501 | uint16_t eth_mtu_size; /* 08-09 */ | |
502 | uint16_t add_fw_options; /* 0A-0B */ | |
b3a271a9 MR |
503 | #define ADFWOPT_SERIALIZE_TASK_MGMT 0x0400 |
504 | #define ADFWOPT_AUTOCONN_DISABLE 0x0002 | |
b2854316 DS |
505 | |
506 | uint8_t hb_interval; /* 0C */ | |
507 | uint8_t inst_num; /* 0D */ | |
508 | uint16_t res1; /* 0E-0F */ | |
509 | uint16_t rqq_consumer_idx; /* 10-11 */ | |
510 | uint16_t compq_producer_idx; /* 12-13 */ | |
511 | uint16_t rqq_len; /* 14-15 */ | |
512 | uint16_t compq_len; /* 16-17 */ | |
513 | uint32_t rqq_addr_lo; /* 18-1B */ | |
514 | uint32_t rqq_addr_hi; /* 1C-1F */ | |
515 | uint32_t compq_addr_lo; /* 20-23 */ | |
516 | uint32_t compq_addr_hi; /* 24-27 */ | |
517 | uint32_t shdwreg_addr_lo; /* 28-2B */ | |
518 | uint32_t shdwreg_addr_hi; /* 2C-2F */ | |
519 | ||
520 | uint16_t iscsi_opts; /* 30-31 */ | |
521 | uint16_t ipv4_tcp_opts; /* 32-33 */ | |
d00efe3f | 522 | #define TCPOPT_DHCP_ENABLE 0x0200 |
b2854316 | 523 | uint16_t ipv4_ip_opts; /* 34-35 */ |
2bab08fc | 524 | #define IPOPT_IPV4_PROTOCOL_ENABLE 0x8000 |
6ac73e8c | 525 | #define IPOPT_VLAN_TAGGING_ENABLE 0x2000 |
b2854316 DS |
526 | |
527 | uint16_t iscsi_max_pdu_size; /* 36-37 */ | |
528 | uint8_t ipv4_tos; /* 38 */ | |
529 | uint8_t ipv4_ttl; /* 39 */ | |
530 | uint8_t acb_version; /* 3A */ | |
2a49a78e VC |
531 | #define ACB_NOT_SUPPORTED 0x00 |
532 | #define ACB_SUPPORTED 0x02 /* Capable of ACB Version 2 | |
533 | Features */ | |
534 | ||
b2854316 DS |
535 | uint8_t res2; /* 3B */ |
536 | uint16_t def_timeout; /* 3C-3D */ | |
537 | uint16_t iscsi_fburst_len; /* 3E-3F */ | |
538 | uint16_t iscsi_def_time2wait; /* 40-41 */ | |
539 | uint16_t iscsi_def_time2retain; /* 42-43 */ | |
540 | uint16_t iscsi_max_outstnd_r2t; /* 44-45 */ | |
541 | uint16_t conn_ka_timeout; /* 46-47 */ | |
542 | uint16_t ipv4_port; /* 48-49 */ | |
543 | uint16_t iscsi_max_burst_len; /* 4A-4B */ | |
544 | uint32_t res5; /* 4C-4F */ | |
545 | uint8_t ipv4_addr[4]; /* 50-53 */ | |
546 | uint16_t ipv4_vlan_tag; /* 54-55 */ | |
547 | uint8_t ipv4_addr_state; /* 56 */ | |
548 | uint8_t ipv4_cacheid; /* 57 */ | |
549 | uint8_t res6[8]; /* 58-5F */ | |
550 | uint8_t ipv4_subnet[4]; /* 60-63 */ | |
551 | uint8_t res7[12]; /* 64-6F */ | |
552 | uint8_t ipv4_gw_addr[4]; /* 70-73 */ | |
553 | uint8_t res8[0xc]; /* 74-7F */ | |
554 | uint8_t pri_dns_srvr_ip[4];/* 80-83 */ | |
555 | uint8_t sec_dns_srvr_ip[4];/* 84-87 */ | |
556 | uint16_t min_eph_port; /* 88-89 */ | |
557 | uint16_t max_eph_port; /* 8A-8B */ | |
558 | uint8_t res9[4]; /* 8C-8F */ | |
559 | uint8_t iscsi_alias[32];/* 90-AF */ | |
560 | uint8_t res9_1[0x16]; /* B0-C5 */ | |
561 | uint16_t tgt_portal_grp;/* C6-C7 */ | |
562 | uint8_t abort_timer; /* C8 */ | |
563 | uint8_t ipv4_tcp_wsf; /* C9 */ | |
564 | uint8_t res10[6]; /* CA-CF */ | |
565 | uint8_t ipv4_sec_ip_addr[4]; /* D0-D3 */ | |
566 | uint8_t ipv4_dhcp_vid_len; /* D4 */ | |
567 | uint8_t ipv4_dhcp_vid[11]; /* D5-DF */ | |
568 | uint8_t res11[20]; /* E0-F3 */ | |
569 | uint8_t ipv4_dhcp_alt_cid_len; /* F4 */ | |
570 | uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */ | |
571 | uint8_t iscsi_name[224]; /* 100-1DF */ | |
572 | uint8_t res12[32]; /* 1E0-1FF */ | |
573 | uint32_t cookie; /* 200-203 */ | |
574 | uint16_t ipv6_port; /* 204-205 */ | |
575 | uint16_t ipv6_opts; /* 206-207 */ | |
2a49a78e | 576 | #define IPV6_OPT_IPV6_PROTOCOL_ENABLE 0x8000 |
6ac73e8c | 577 | #define IPV6_OPT_VLAN_TAGGING_ENABLE 0x2000 |
2a49a78e | 578 | |
b2854316 | 579 | uint16_t ipv6_addtl_opts; /* 208-209 */ |
2a49a78e VC |
580 | #define IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE 0x0002 /* Pri ACB |
581 | Only */ | |
582 | #define IPV6_ADDOPT_AUTOCONFIG_LINK_LOCAL_ADDR 0x0001 | |
583 | ||
b2854316 DS |
584 | uint16_t ipv6_tcp_opts; /* 20A-20B */ |
585 | uint8_t ipv6_tcp_wsf; /* 20C */ | |
586 | uint16_t ipv6_flow_lbl; /* 20D-20F */ | |
2a49a78e | 587 | uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */ |
b2854316 DS |
588 | uint16_t ipv6_vlan_tag; /* 220-221 */ |
589 | uint8_t ipv6_lnk_lcl_addr_state;/* 222 */ | |
590 | uint8_t ipv6_addr0_state; /* 223 */ | |
591 | uint8_t ipv6_addr1_state; /* 224 */ | |
2a49a78e VC |
592 | #define IP_ADDRSTATE_UNCONFIGURED 0 |
593 | #define IP_ADDRSTATE_INVALID 1 | |
594 | #define IP_ADDRSTATE_ACQUIRING 2 | |
595 | #define IP_ADDRSTATE_TENTATIVE 3 | |
596 | #define IP_ADDRSTATE_DEPRICATED 4 | |
597 | #define IP_ADDRSTATE_PREFERRED 5 | |
598 | #define IP_ADDRSTATE_DISABLING 6 | |
599 | ||
600 | uint8_t ipv6_dflt_rtr_state; /* 225 */ | |
601 | #define IPV6_RTRSTATE_UNKNOWN 0 | |
602 | #define IPV6_RTRSTATE_MANUAL 1 | |
603 | #define IPV6_RTRSTATE_ADVERTISED 3 | |
604 | #define IPV6_RTRSTATE_STALE 4 | |
605 | ||
b2854316 DS |
606 | uint8_t ipv6_traffic_class; /* 226 */ |
607 | uint8_t ipv6_hop_limit; /* 227 */ | |
608 | uint8_t ipv6_if_id[8]; /* 228-22F */ | |
609 | uint8_t ipv6_addr0[16]; /* 230-23F */ | |
610 | uint8_t ipv6_addr1[16]; /* 240-24F */ | |
611 | uint32_t ipv6_nd_reach_time; /* 250-253 */ | |
612 | uint32_t ipv6_nd_rexmit_timer; /* 254-257 */ | |
613 | uint32_t ipv6_nd_stale_timeout; /* 258-25B */ | |
614 | uint8_t ipv6_dup_addr_detect_count; /* 25C */ | |
615 | uint8_t ipv6_cache_id; /* 25D */ | |
616 | uint8_t res13[18]; /* 25E-26F */ | |
617 | uint32_t ipv6_gw_advrt_mtu; /* 270-273 */ | |
618 | uint8_t res14[140]; /* 274-2FF */ | |
619 | }; | |
620 | ||
13483730 MC |
621 | #define IP_ADDR_COUNT 4 /* Total 4 IP address supported in one interface |
622 | * One IPv4, one IPv6 link local and 2 IPv6 | |
623 | */ | |
624 | ||
625 | #define IP_STATE_MASK 0x0F000000 | |
626 | #define IP_STATE_SHIFT 24 | |
627 | ||
b2854316 DS |
628 | struct init_fw_ctrl_blk { |
629 | struct addr_ctrl_blk pri; | |
2a49a78e | 630 | /* struct addr_ctrl_blk sec;*/ |
afaf5a2d DS |
631 | }; |
632 | ||
95d31262 VC |
633 | #define PRIMARI_ACB 0 |
634 | #define SECONDARY_ACB 1 | |
635 | ||
d00efe3f MC |
636 | struct addr_ctrl_blk_def { |
637 | uint8_t reserved1[1]; /* 00 */ | |
638 | uint8_t control; /* 01 */ | |
639 | uint8_t reserved2[11]; /* 02-0C */ | |
640 | uint8_t inst_num; /* 0D */ | |
641 | uint8_t reserved3[34]; /* 0E-2F */ | |
642 | uint16_t iscsi_opts; /* 30-31 */ | |
643 | uint16_t ipv4_tcp_opts; /* 32-33 */ | |
644 | uint16_t ipv4_ip_opts; /* 34-35 */ | |
645 | uint16_t iscsi_max_pdu_size; /* 36-37 */ | |
646 | uint8_t ipv4_tos; /* 38 */ | |
647 | uint8_t ipv4_ttl; /* 39 */ | |
648 | uint8_t reserved4[2]; /* 3A-3B */ | |
649 | uint16_t def_timeout; /* 3C-3D */ | |
650 | uint16_t iscsi_fburst_len; /* 3E-3F */ | |
651 | uint8_t reserved5[4]; /* 40-43 */ | |
652 | uint16_t iscsi_max_outstnd_r2t; /* 44-45 */ | |
653 | uint8_t reserved6[2]; /* 46-47 */ | |
654 | uint16_t ipv4_port; /* 48-49 */ | |
655 | uint16_t iscsi_max_burst_len; /* 4A-4B */ | |
656 | uint8_t reserved7[4]; /* 4C-4F */ | |
657 | uint8_t ipv4_addr[4]; /* 50-53 */ | |
658 | uint16_t ipv4_vlan_tag; /* 54-55 */ | |
659 | uint8_t ipv4_addr_state; /* 56 */ | |
660 | uint8_t ipv4_cacheid; /* 57 */ | |
661 | uint8_t reserved8[8]; /* 58-5F */ | |
662 | uint8_t ipv4_subnet[4]; /* 60-63 */ | |
663 | uint8_t reserved9[12]; /* 64-6F */ | |
664 | uint8_t ipv4_gw_addr[4]; /* 70-73 */ | |
665 | uint8_t reserved10[84]; /* 74-C7 */ | |
666 | uint8_t abort_timer; /* C8 */ | |
667 | uint8_t ipv4_tcp_wsf; /* C9 */ | |
668 | uint8_t reserved11[10]; /* CA-D3 */ | |
669 | uint8_t ipv4_dhcp_vid_len; /* D4 */ | |
670 | uint8_t ipv4_dhcp_vid[11]; /* D5-DF */ | |
671 | uint8_t reserved12[20]; /* E0-F3 */ | |
672 | uint8_t ipv4_dhcp_alt_cid_len; /* F4 */ | |
673 | uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */ | |
674 | uint8_t iscsi_name[224]; /* 100-1DF */ | |
675 | uint8_t reserved13[32]; /* 1E0-1FF */ | |
676 | uint32_t cookie; /* 200-203 */ | |
677 | uint16_t ipv6_port; /* 204-205 */ | |
678 | uint16_t ipv6_opts; /* 206-207 */ | |
679 | uint16_t ipv6_addtl_opts; /* 208-209 */ | |
680 | uint16_t ipv6_tcp_opts; /* 20A-20B */ | |
681 | uint8_t ipv6_tcp_wsf; /* 20C */ | |
682 | uint16_t ipv6_flow_lbl; /* 20D-20F */ | |
683 | uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */ | |
684 | uint16_t ipv6_vlan_tag; /* 220-221 */ | |
685 | uint8_t ipv6_lnk_lcl_addr_state; /* 222 */ | |
686 | uint8_t ipv6_addr0_state; /* 223 */ | |
687 | uint8_t ipv6_addr1_state; /* 224 */ | |
688 | uint8_t ipv6_dflt_rtr_state; /* 225 */ | |
689 | uint8_t ipv6_traffic_class; /* 226 */ | |
690 | uint8_t ipv6_hop_limit; /* 227 */ | |
691 | uint8_t ipv6_if_id[8]; /* 228-22F */ | |
692 | uint8_t ipv6_addr0[16]; /* 230-23F */ | |
693 | uint8_t ipv6_addr1[16]; /* 240-24F */ | |
694 | uint32_t ipv6_nd_reach_time; /* 250-253 */ | |
695 | uint32_t ipv6_nd_rexmit_timer; /* 254-257 */ | |
696 | uint32_t ipv6_nd_stale_timeout; /* 258-25B */ | |
697 | uint8_t ipv6_dup_addr_detect_count; /* 25C */ | |
698 | uint8_t ipv6_cache_id; /* 25D */ | |
699 | uint8_t reserved14[18]; /* 25E-26F */ | |
700 | uint32_t ipv6_gw_advrt_mtu; /* 270-273 */ | |
701 | uint8_t reserved15[140]; /* 274-2FF */ | |
702 | }; | |
703 | ||
afaf5a2d DS |
704 | /*************************************************************************/ |
705 | ||
b3a271a9 MR |
706 | #define MAX_CHAP_ENTRIES_40XX 128 |
707 | #define MAX_CHAP_ENTRIES_82XX 1024 | |
4549415a LC |
708 | #define MAX_RESRV_CHAP_IDX 3 |
709 | #define FLASH_CHAP_OFFSET 0x06000000 | |
b3a271a9 MR |
710 | |
711 | struct ql4_chap_table { | |
712 | uint16_t link; | |
713 | uint8_t flags; | |
714 | uint8_t secret_len; | |
715 | #define MIN_CHAP_SECRET_LEN 12 | |
716 | #define MAX_CHAP_SECRET_LEN 100 | |
717 | uint8_t secret[MAX_CHAP_SECRET_LEN]; | |
718 | #define MAX_CHAP_NAME_LEN 256 | |
719 | uint8_t name[MAX_CHAP_NAME_LEN]; | |
720 | uint16_t reserved; | |
721 | #define CHAP_VALID_COOKIE 0x4092 | |
722 | #define CHAP_INVALID_COOKIE 0xFFEE | |
723 | uint16_t cookie; | |
724 | }; | |
725 | ||
afaf5a2d | 726 | struct dev_db_entry { |
b2854316 | 727 | uint16_t options; /* 00-01 */ |
afaf5a2d DS |
728 | #define DDB_OPT_DISC_SESSION 0x10 |
729 | #define DDB_OPT_TARGET 0x02 /* device is a target */ | |
2a49a78e | 730 | #define DDB_OPT_IPV6_DEVICE 0x100 |
b3a271a9 | 731 | #define DDB_OPT_AUTO_SENDTGTS_DISABLE 0x40 |
2a49a78e VC |
732 | #define DDB_OPT_IPV6_NULL_LINK_LOCAL 0x800 /* post connection */ |
733 | #define DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL 0x800 /* pre connection */ | |
afaf5a2d | 734 | |
b2854316 DS |
735 | uint16_t exec_throttle; /* 02-03 */ |
736 | uint16_t exec_count; /* 04-05 */ | |
737 | uint16_t res0; /* 06-07 */ | |
738 | uint16_t iscsi_options; /* 08-09 */ | |
739 | uint16_t tcp_options; /* 0A-0B */ | |
740 | uint16_t ip_options; /* 0C-0D */ | |
741 | uint16_t iscsi_max_rcv_data_seg_len; /* 0E-0F */ | |
b3a271a9 | 742 | #define BYTE_UNITS 512 |
b2854316 DS |
743 | uint32_t res1; /* 10-13 */ |
744 | uint16_t iscsi_max_snd_data_seg_len; /* 14-15 */ | |
745 | uint16_t iscsi_first_burst_len; /* 16-17 */ | |
746 | uint16_t iscsi_def_time2wait; /* 18-19 */ | |
747 | uint16_t iscsi_def_time2retain; /* 1A-1B */ | |
748 | uint16_t iscsi_max_outsnd_r2t; /* 1C-1D */ | |
749 | uint16_t ka_timeout; /* 1E-1F */ | |
750 | uint8_t isid[6]; /* 20-25 big-endian, must be converted | |
afaf5a2d | 751 | * to little-endian */ |
b2854316 DS |
752 | uint16_t tsid; /* 26-27 */ |
753 | uint16_t port; /* 28-29 */ | |
754 | uint16_t iscsi_max_burst_len; /* 2A-2B */ | |
755 | uint16_t def_timeout; /* 2C-2D */ | |
756 | uint16_t res2; /* 2E-2F */ | |
757 | uint8_t ip_addr[0x10]; /* 30-3F */ | |
758 | uint8_t iscsi_alias[0x20]; /* 40-5F */ | |
759 | uint8_t tgt_addr[0x20]; /* 60-7F */ | |
760 | uint16_t mss; /* 80-81 */ | |
761 | uint16_t res3; /* 82-83 */ | |
762 | uint16_t lcl_port; /* 84-85 */ | |
763 | uint8_t ipv4_tos; /* 86 */ | |
764 | uint16_t ipv6_flow_lbl; /* 87-89 */ | |
765 | uint8_t res4[0x36]; /* 8A-BF */ | |
766 | uint8_t iscsi_name[0xE0]; /* C0-19F : xxzzy Make this a | |
afaf5a2d | 767 | * pointer to a string so we |
42b2aa86 | 768 | * don't have to reserve so |
afaf5a2d | 769 | * much RAM */ |
2a49a78e | 770 | uint8_t link_local_ipv6_addr[0x10]; /* 1A0-1AF */ |
b2854316 DS |
771 | uint8_t res5[0x10]; /* 1B0-1BF */ |
772 | uint16_t ddb_link; /* 1C0-1C1 */ | |
773 | uint16_t chap_tbl_idx; /* 1C2-1C3 */ | |
774 | uint16_t tgt_portal_grp; /* 1C4-1C5 */ | |
775 | uint8_t tcp_xmt_wsf; /* 1C6 */ | |
776 | uint8_t tcp_rcv_wsf; /* 1C7 */ | |
777 | uint32_t stat_sn; /* 1C8-1CB */ | |
778 | uint32_t exp_stat_sn; /* 1CC-1CF */ | |
2a991c21 MR |
779 | uint8_t res6[0x2b]; /* 1D0-1FB */ |
780 | #define DDB_VALID_COOKIE 0x9034 | |
781 | uint16_t cookie; /* 1FC-1FD */ | |
782 | uint16_t len; /* 1FE-1FF */ | |
afaf5a2d DS |
783 | }; |
784 | ||
785 | /*************************************************************************/ | |
786 | ||
787 | /* Flash definitions */ | |
788 | ||
789 | #define FLASH_OFFSET_SYS_INFO 0x02000000 | |
790 | #define FLASH_DEFAULTBLOCKSIZE 0x20000 | |
791 | #define FLASH_EOF_OFFSET (FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes | |
792 | * for EOF | |
793 | * signature */ | |
2a991c21 MR |
794 | #define FLASH_RAW_ACCESS_ADDR 0x8e000000 |
795 | ||
796 | #define BOOT_PARAM_OFFSET_PORT0 0x3b0 | |
797 | #define BOOT_PARAM_OFFSET_PORT1 0x7b0 | |
798 | ||
799 | #define FLASH_OFFSET_DB_INFO 0x05000000 | |
800 | #define FLASH_OFFSET_DB_END (FLASH_OFFSET_DB_INFO + 0x7fff) | |
801 | ||
afaf5a2d DS |
802 | |
803 | struct sys_info_phys_addr { | |
804 | uint8_t address[6]; /* 00-05 */ | |
805 | uint8_t filler[2]; /* 06-07 */ | |
806 | }; | |
807 | ||
808 | struct flash_sys_info { | |
809 | uint32_t cookie; /* 00-03 */ | |
810 | uint32_t physAddrCount; /* 04-07 */ | |
811 | struct sys_info_phys_addr physAddr[4]; /* 08-27 */ | |
812 | uint8_t vendorId[128]; /* 28-A7 */ | |
813 | uint8_t productId[128]; /* A8-127 */ | |
814 | uint32_t serialNumber; /* 128-12B */ | |
815 | ||
816 | /* PCI Configuration values */ | |
817 | uint32_t pciDeviceVendor; /* 12C-12F */ | |
818 | uint32_t pciDeviceId; /* 130-133 */ | |
819 | uint32_t pciSubsysVendor; /* 134-137 */ | |
820 | uint32_t pciSubsysId; /* 138-13B */ | |
821 | ||
822 | /* This validates version 1. */ | |
823 | uint32_t crumbs; /* 13C-13F */ | |
824 | ||
825 | uint32_t enterpriseNumber; /* 140-143 */ | |
826 | ||
827 | uint32_t mtu; /* 144-147 */ | |
828 | uint32_t reserved0; /* 148-14b */ | |
829 | uint32_t crumbs2; /* 14c-14f */ | |
830 | uint8_t acSerialNumber[16]; /* 150-15f */ | |
831 | uint32_t crumbs3; /* 160-16f */ | |
832 | ||
833 | /* Leave this last in the struct so it is declared invalid if | |
834 | * any new items are added. | |
835 | */ | |
836 | uint32_t reserved1[39]; /* 170-1ff */ | |
837 | }; /* 200 */ | |
838 | ||
f4f5df23 | 839 | struct mbx_sys_info { |
2ccdf0dc VC |
840 | uint8_t board_id_str[16]; /* 0-f Keep board ID string first */ |
841 | /* in this structure for GUI. */ | |
842 | uint16_t board_id; /* 10-11 board ID code */ | |
843 | uint16_t phys_port_cnt; /* 12-13 number of physical network ports */ | |
844 | uint16_t port_num; /* 14-15 network port for this PCI function */ | |
f4f5df23 | 845 | /* (port 0 is first port) */ |
2ccdf0dc VC |
846 | uint8_t mac_addr[6]; /* 16-1b MAC address for this PCI function */ |
847 | uint32_t iscsi_pci_func_cnt; /* 1c-1f number of iSCSI PCI functions */ | |
848 | uint32_t pci_func; /* 20-23 this PCI function */ | |
849 | unsigned char serial_number[16]; /* 24-33 serial number string */ | |
850 | uint8_t reserved[12]; /* 34-3f */ | |
f4f5df23 VC |
851 | }; |
852 | ||
7ad633c0 HZ |
853 | struct about_fw_info { |
854 | uint16_t fw_major; /* 00 - 01 */ | |
855 | uint16_t fw_minor; /* 02 - 03 */ | |
856 | uint16_t fw_patch; /* 04 - 05 */ | |
857 | uint16_t fw_build; /* 06 - 07 */ | |
858 | uint8_t fw_build_date[16]; /* 08 - 17 ASCII String */ | |
859 | uint8_t fw_build_time[16]; /* 18 - 27 ASCII String */ | |
860 | uint8_t fw_build_user[16]; /* 28 - 37 ASCII String */ | |
861 | uint16_t fw_load_source; /* 38 - 39 */ | |
862 | /* 1 = Flash Primary, | |
863 | 2 = Flash Secondary, | |
864 | 3 = Host Download | |
865 | */ | |
866 | uint8_t reserved1[6]; /* 3A - 3F */ | |
867 | uint16_t iscsi_major; /* 40 - 41 */ | |
868 | uint16_t iscsi_minor; /* 42 - 43 */ | |
869 | uint16_t bootload_major; /* 44 - 45 */ | |
870 | uint16_t bootload_minor; /* 46 - 47 */ | |
871 | uint16_t bootload_patch; /* 48 - 49 */ | |
872 | uint16_t bootload_build; /* 4A - 4B */ | |
873 | uint8_t reserved2[180]; /* 4C - FF */ | |
874 | }; | |
875 | ||
afaf5a2d DS |
876 | struct crash_record { |
877 | uint16_t fw_major_version; /* 00 - 01 */ | |
878 | uint16_t fw_minor_version; /* 02 - 03 */ | |
879 | uint16_t fw_patch_version; /* 04 - 05 */ | |
880 | uint16_t fw_build_version; /* 06 - 07 */ | |
881 | ||
882 | uint8_t build_date[16]; /* 08 - 17 */ | |
883 | uint8_t build_time[16]; /* 18 - 27 */ | |
884 | uint8_t build_user[16]; /* 28 - 37 */ | |
885 | uint8_t card_serial_num[16]; /* 38 - 47 */ | |
886 | ||
887 | uint32_t time_of_crash_in_secs; /* 48 - 4B */ | |
888 | uint32_t time_of_crash_in_ms; /* 4C - 4F */ | |
889 | ||
890 | uint16_t out_RISC_sd_num_frames; /* 50 - 51 */ | |
891 | uint16_t OAP_sd_num_words; /* 52 - 53 */ | |
892 | uint16_t IAP_sd_num_frames; /* 54 - 55 */ | |
893 | uint16_t in_RISC_sd_num_words; /* 56 - 57 */ | |
894 | ||
895 | uint8_t reserved1[28]; /* 58 - 7F */ | |
896 | ||
897 | uint8_t out_RISC_reg_dump[256]; /* 80 -17F */ | |
898 | uint8_t in_RISC_reg_dump[256]; /*180 -27F */ | |
899 | uint8_t in_out_RISC_stack_dump[0]; /*280 - ??? */ | |
900 | }; | |
901 | ||
902 | struct conn_event_log_entry { | |
903 | #define MAX_CONN_EVENT_LOG_ENTRIES 100 | |
904 | uint32_t timestamp_sec; /* 00 - 03 seconds since boot */ | |
905 | uint32_t timestamp_ms; /* 04 - 07 milliseconds since boot */ | |
906 | uint16_t device_index; /* 08 - 09 */ | |
907 | uint16_t fw_conn_state; /* 0A - 0B */ | |
908 | uint8_t event_type; /* 0C - 0C */ | |
909 | uint8_t error_code; /* 0D - 0D */ | |
910 | uint16_t error_code_detail; /* 0E - 0F */ | |
911 | uint8_t num_consecutive_events; /* 10 - 10 */ | |
912 | uint8_t rsvd[3]; /* 11 - 13 */ | |
913 | }; | |
914 | ||
915 | /************************************************************************* | |
916 | * | |
917 | * IOCB Commands Structures and Definitions | |
918 | * | |
919 | *************************************************************************/ | |
920 | #define IOCB_MAX_CDB_LEN 16 /* Bytes in a CBD */ | |
921 | #define IOCB_MAX_SENSEDATA_LEN 32 /* Bytes of sense data */ | |
94bced3c | 922 | #define IOCB_MAX_EXT_SENSEDATA_LEN 60 /* Bytes of extended sense data */ |
afaf5a2d DS |
923 | |
924 | /* IOCB header structure */ | |
925 | struct qla4_header { | |
926 | uint8_t entryType; | |
927 | #define ET_STATUS 0x03 | |
928 | #define ET_MARKER 0x04 | |
929 | #define ET_CONT_T1 0x0A | |
930 | #define ET_STATUS_CONTINUATION 0x10 | |
931 | #define ET_CMND_T3 0x19 | |
932 | #define ET_PASSTHRU0 0x3A | |
933 | #define ET_PASSTHRU_STATUS 0x3C | |
c0b9d3f7 VC |
934 | #define ET_MBOX_CMD 0x38 |
935 | #define ET_MBOX_STATUS 0x39 | |
afaf5a2d DS |
936 | |
937 | uint8_t entryStatus; | |
938 | uint8_t systemDefined; | |
b3a271a9 | 939 | #define SD_ISCSI_PDU 0x01 |
afaf5a2d DS |
940 | uint8_t entryCount; |
941 | ||
942 | /* SyetemDefined definition */ | |
943 | }; | |
944 | ||
945 | /* Generic queue entry structure*/ | |
946 | struct queue_entry { | |
947 | uint8_t data[60]; | |
948 | uint32_t signature; | |
949 | ||
950 | }; | |
951 | ||
952 | /* 64 bit addressing segment counts*/ | |
953 | ||
954 | #define COMMAND_SEG_A64 1 | |
955 | #define CONTINUE_SEG_A64 5 | |
956 | ||
957 | /* 64 bit addressing segment definition*/ | |
958 | ||
959 | struct data_seg_a64 { | |
960 | struct { | |
961 | uint32_t addrLow; | |
962 | uint32_t addrHigh; | |
963 | ||
964 | } base; | |
965 | ||
966 | uint32_t count; | |
967 | ||
968 | }; | |
969 | ||
970 | /* Command Type 3 entry structure*/ | |
971 | ||
972 | struct command_t3_entry { | |
973 | struct qla4_header hdr; /* 00-03 */ | |
974 | ||
975 | uint32_t handle; /* 04-07 */ | |
976 | uint16_t target; /* 08-09 */ | |
977 | uint16_t connection_id; /* 0A-0B */ | |
978 | ||
979 | uint8_t control_flags; /* 0C */ | |
980 | ||
981 | /* data direction (bits 5-6) */ | |
982 | #define CF_WRITE 0x20 | |
983 | #define CF_READ 0x40 | |
984 | #define CF_NO_DATA 0x00 | |
985 | ||
986 | /* task attributes (bits 2-0) */ | |
987 | #define CF_HEAD_TAG 0x03 | |
988 | #define CF_ORDERED_TAG 0x02 | |
989 | #define CF_SIMPLE_TAG 0x01 | |
990 | ||
991 | /* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS | |
992 | * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS | |
993 | * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET | |
994 | * PROPERLY. | |
995 | */ | |
996 | uint8_t state_flags; /* 0D */ | |
997 | uint8_t cmdRefNum; /* 0E */ | |
998 | uint8_t reserved1; /* 0F */ | |
999 | uint8_t cdb[IOCB_MAX_CDB_LEN]; /* 10-1F */ | |
1000 | struct scsi_lun lun; /* FCP LUN (BE). */ | |
1001 | uint32_t cmdSeqNum; /* 28-2B */ | |
1002 | uint16_t timeout; /* 2C-2D */ | |
1003 | uint16_t dataSegCnt; /* 2E-2F */ | |
1004 | uint32_t ttlByteCnt; /* 30-33 */ | |
1005 | struct data_seg_a64 dataseg[COMMAND_SEG_A64]; /* 34-3F */ | |
1006 | ||
1007 | }; | |
1008 | ||
1009 | ||
1010 | /* Continuation Type 1 entry structure*/ | |
1011 | struct continuation_t1_entry { | |
1012 | struct qla4_header hdr; | |
1013 | ||
1014 | struct data_seg_a64 dataseg[CONTINUE_SEG_A64]; | |
1015 | ||
1016 | }; | |
1017 | ||
1018 | /* Parameterize for 64 or 32 bits */ | |
1019 | #define COMMAND_SEG COMMAND_SEG_A64 | |
1020 | #define CONTINUE_SEG CONTINUE_SEG_A64 | |
1021 | ||
1022 | #define ET_COMMAND ET_CMND_T3 | |
1023 | #define ET_CONTINUE ET_CONT_T1 | |
1024 | ||
1025 | /* Marker entry structure*/ | |
1c3f0b8e | 1026 | struct qla4_marker_entry { |
afaf5a2d DS |
1027 | struct qla4_header hdr; /* 00-03 */ |
1028 | ||
1029 | uint32_t system_defined; /* 04-07 */ | |
1030 | uint16_t target; /* 08-09 */ | |
1031 | uint16_t modifier; /* 0A-0B */ | |
9d562913 DS |
1032 | #define MM_LUN_RESET 0 |
1033 | #define MM_TGT_WARM_RESET 1 | |
afaf5a2d DS |
1034 | |
1035 | uint16_t flags; /* 0C-0D */ | |
1036 | uint16_t reserved1; /* 0E-0F */ | |
1037 | struct scsi_lun lun; /* FCP LUN (BE). */ | |
1038 | uint64_t reserved2; /* 18-1F */ | |
1039 | uint64_t reserved3; /* 20-27 */ | |
1040 | uint64_t reserved4; /* 28-2F */ | |
1041 | uint64_t reserved5; /* 30-37 */ | |
1042 | uint64_t reserved6; /* 38-3F */ | |
1043 | }; | |
1044 | ||
1045 | /* Status entry structure*/ | |
1046 | struct status_entry { | |
1047 | struct qla4_header hdr; /* 00-03 */ | |
1048 | ||
1049 | uint32_t handle; /* 04-07 */ | |
1050 | ||
1051 | uint8_t scsiStatus; /* 08 */ | |
1052 | #define SCSI_CHECK_CONDITION 0x02 | |
1053 | ||
1054 | uint8_t iscsiFlags; /* 09 */ | |
1055 | #define ISCSI_FLAG_RESIDUAL_UNDER 0x02 | |
1056 | #define ISCSI_FLAG_RESIDUAL_OVER 0x04 | |
1057 | ||
1058 | uint8_t iscsiResponse; /* 0A */ | |
1059 | ||
1060 | uint8_t completionStatus; /* 0B */ | |
1061 | #define SCS_COMPLETE 0x00 | |
1062 | #define SCS_INCOMPLETE 0x01 | |
1063 | #define SCS_RESET_OCCURRED 0x04 | |
1064 | #define SCS_ABORTED 0x05 | |
1065 | #define SCS_TIMEOUT 0x06 | |
1066 | #define SCS_DATA_OVERRUN 0x07 | |
1067 | #define SCS_DATA_UNDERRUN 0x15 | |
1068 | #define SCS_QUEUE_FULL 0x1C | |
1069 | #define SCS_DEVICE_UNAVAILABLE 0x28 | |
1070 | #define SCS_DEVICE_LOGGED_OUT 0x29 | |
1071 | ||
1072 | uint8_t reserved1; /* 0C */ | |
1073 | ||
1074 | /* state_flags MUST be at the same location as state_flags in | |
1075 | * the Command_T3/4_Entry */ | |
1076 | uint8_t state_flags; /* 0D */ | |
1077 | ||
1078 | uint16_t senseDataByteCnt; /* 0E-0F */ | |
1079 | uint32_t residualByteCnt; /* 10-13 */ | |
1080 | uint32_t bidiResidualByteCnt; /* 14-17 */ | |
1081 | uint32_t expSeqNum; /* 18-1B */ | |
1082 | uint32_t maxCmdSeqNum; /* 1C-1F */ | |
1083 | uint8_t senseData[IOCB_MAX_SENSEDATA_LEN]; /* 20-3F */ | |
1084 | ||
1085 | }; | |
1086 | ||
94bced3c KH |
1087 | /* Status Continuation entry */ |
1088 | struct status_cont_entry { | |
1089 | struct qla4_header hdr; /* 00-03 */ | |
1090 | uint8_t ext_sense_data[IOCB_MAX_EXT_SENSEDATA_LEN]; /* 04-63 */ | |
1091 | }; | |
1092 | ||
afaf5a2d DS |
1093 | struct passthru0 { |
1094 | struct qla4_header hdr; /* 00-03 */ | |
1095 | uint32_t handle; /* 04-07 */ | |
1096 | uint16_t target; /* 08-09 */ | |
b3a271a9 | 1097 | uint16_t connection_id; /* 0A-0B */ |
afaf5a2d DS |
1098 | #define ISNS_DEFAULT_SERVER_CONN_ID ((uint16_t)0x8000) |
1099 | ||
b3a271a9 | 1100 | uint16_t control_flags; /* 0C-0D */ |
afaf5a2d DS |
1101 | #define PT_FLAG_ETHERNET_FRAME 0x8000 |
1102 | #define PT_FLAG_ISNS_PDU 0x8000 | |
1103 | #define PT_FLAG_SEND_BUFFER 0x0200 | |
1104 | #define PT_FLAG_WAIT_4_RESPONSE 0x0100 | |
b3a271a9 | 1105 | #define PT_FLAG_ISCSI_PDU 0x1000 |
afaf5a2d DS |
1106 | |
1107 | uint16_t timeout; /* 0E-0F */ | |
1108 | #define PT_DEFAULT_TIMEOUT 30 /* seconds */ | |
1109 | ||
b3a271a9 | 1110 | struct data_seg_a64 out_dsd; /* 10-1B */ |
afaf5a2d | 1111 | uint32_t res1; /* 1C-1F */ |
b3a271a9 | 1112 | struct data_seg_a64 in_dsd; /* 20-2B */ |
afaf5a2d DS |
1113 | uint8_t res2[20]; /* 2C-3F */ |
1114 | }; | |
1115 | ||
1116 | struct passthru_status { | |
1117 | struct qla4_header hdr; /* 00-03 */ | |
1118 | uint32_t handle; /* 04-07 */ | |
1119 | uint16_t target; /* 08-09 */ | |
1120 | uint16_t connectionID; /* 0A-0B */ | |
1121 | ||
1122 | uint8_t completionStatus; /* 0C */ | |
1123 | #define PASSTHRU_STATUS_COMPLETE 0x01 | |
1124 | ||
1125 | uint8_t residualFlags; /* 0D */ | |
1126 | ||
1127 | uint16_t timeout; /* 0E-0F */ | |
1128 | uint16_t portNumber; /* 10-11 */ | |
1129 | uint8_t res1[10]; /* 12-1B */ | |
1130 | uint32_t outResidual; /* 1C-1F */ | |
1131 | uint8_t res2[12]; /* 20-2B */ | |
1132 | uint32_t inResidual; /* 2C-2F */ | |
1133 | uint8_t res4[16]; /* 30-3F */ | |
1134 | }; | |
1135 | ||
c0b9d3f7 VC |
1136 | struct mbox_cmd_iocb { |
1137 | struct qla4_header hdr; /* 00-03 */ | |
1138 | uint32_t handle; /* 04-07 */ | |
1139 | uint32_t in_mbox[8]; /* 08-25 */ | |
1140 | uint32_t res1[6]; /* 26-3F */ | |
1141 | }; | |
1142 | ||
1143 | struct mbox_status_iocb { | |
1144 | struct qla4_header hdr; /* 00-03 */ | |
1145 | uint32_t handle; /* 04-07 */ | |
1146 | uint32_t out_mbox[8]; /* 08-25 */ | |
1147 | uint32_t res1[6]; /* 26-3F */ | |
1148 | }; | |
1149 | ||
f4f5df23 VC |
1150 | /* |
1151 | * ISP queue - response queue entry definition. | |
1152 | */ | |
1153 | struct response { | |
1154 | uint8_t data[60]; | |
1155 | uint32_t signature; | |
1156 | #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ | |
1157 | }; | |
1158 | ||
b3a271a9 MR |
1159 | struct ql_iscsi_stats { |
1160 | uint8_t reserved1[656]; /* 0000-028F */ | |
1161 | uint32_t tx_cmd_pdu; /* 0290-0293 */ | |
1162 | uint32_t tx_resp_pdu; /* 0294-0297 */ | |
1163 | uint32_t rx_cmd_pdu; /* 0298-029B */ | |
1164 | uint32_t rx_resp_pdu; /* 029C-029F */ | |
1165 | ||
1166 | uint64_t tx_data_octets; /* 02A0-02A7 */ | |
1167 | uint64_t rx_data_octets; /* 02A8-02AF */ | |
1168 | ||
1169 | uint32_t hdr_digest_err; /* 02B0–02B3 */ | |
1170 | uint32_t data_digest_err; /* 02B4–02B7 */ | |
1171 | uint32_t conn_timeout_err; /* 02B8–02BB */ | |
1172 | uint32_t framing_err; /* 02BC–02BF */ | |
1173 | ||
1174 | uint32_t tx_nopout_pdus; /* 02C0–02C3 */ | |
1175 | uint32_t tx_scsi_cmd_pdus; /* 02C4–02C7 */ | |
1176 | uint32_t tx_tmf_cmd_pdus; /* 02C8–02CB */ | |
1177 | uint32_t tx_login_cmd_pdus; /* 02CC–02CF */ | |
1178 | uint32_t tx_text_cmd_pdus; /* 02D0–02D3 */ | |
1179 | uint32_t tx_scsi_write_pdus; /* 02D4–02D7 */ | |
1180 | uint32_t tx_logout_cmd_pdus; /* 02D8–02DB */ | |
1181 | uint32_t tx_snack_req_pdus; /* 02DC–02DF */ | |
1182 | ||
1183 | uint32_t rx_nopin_pdus; /* 02E0–02E3 */ | |
1184 | uint32_t rx_scsi_resp_pdus; /* 02E4–02E7 */ | |
1185 | uint32_t rx_tmf_resp_pdus; /* 02E8–02EB */ | |
1186 | uint32_t rx_login_resp_pdus; /* 02EC–02EF */ | |
1187 | uint32_t rx_text_resp_pdus; /* 02F0–02F3 */ | |
1188 | uint32_t rx_scsi_read_pdus; /* 02F4–02F7 */ | |
1189 | uint32_t rx_logout_resp_pdus; /* 02F8–02FB */ | |
1190 | ||
1191 | uint32_t rx_r2t_pdus; /* 02FC–02FF */ | |
1192 | uint32_t rx_async_pdus; /* 0300–0303 */ | |
1193 | uint32_t rx_reject_pdus; /* 0304–0307 */ | |
1194 | ||
1195 | uint8_t reserved2[264]; /* 0x0308 - 0x040F */ | |
1196 | }; | |
1197 | ||
068237c8 TP |
1198 | #define QLA82XX_DBG_STATE_ARRAY_LEN 16 |
1199 | #define QLA82XX_DBG_CAP_SIZE_ARRAY_LEN 8 | |
1200 | #define QLA82XX_DBG_RSVD_ARRAY_LEN 8 | |
1201 | ||
1202 | struct qla4_8xxx_minidump_template_hdr { | |
1203 | uint32_t entry_type; | |
1204 | uint32_t first_entry_offset; | |
1205 | uint32_t size_of_template; | |
1206 | uint32_t capture_debug_level; | |
1207 | uint32_t num_of_entries; | |
1208 | uint32_t version; | |
1209 | uint32_t driver_timestamp; | |
1210 | uint32_t checksum; | |
1211 | ||
1212 | uint32_t driver_capture_mask; | |
1213 | uint32_t driver_info_word2; | |
1214 | uint32_t driver_info_word3; | |
1215 | uint32_t driver_info_word4; | |
1216 | ||
1217 | uint32_t saved_state_array[QLA82XX_DBG_STATE_ARRAY_LEN]; | |
1218 | uint32_t capture_size_array[QLA82XX_DBG_CAP_SIZE_ARRAY_LEN]; | |
1219 | }; | |
1220 | ||
afaf5a2d | 1221 | #endif /* _QLA4X_FW_H */ |