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afaf5a2d DS |
1 | /* |
2 | * QLogic iSCSI HBA Driver | |
4a4f51e9 | 3 | * Copyright (c) 2003-2013 QLogic Corporation |
afaf5a2d DS |
4 | * |
5 | * See LICENSE.qla4xxx for copyright and licensing details. | |
6 | */ | |
7 | ||
8 | #ifndef _QLA4X_FW_H | |
9 | #define _QLA4X_FW_H | |
10 | ||
11 | ||
12 | #define MAX_PRST_DEV_DB_ENTRIES 64 | |
13 | #define MIN_DISC_DEV_DB_ENTRY MAX_PRST_DEV_DB_ENTRIES | |
f4f5df23 | 14 | #define MAX_DEV_DB_ENTRIES 512 |
13483730 | 15 | #define MAX_DEV_DB_ENTRIES_40XX 256 |
afaf5a2d DS |
16 | |
17 | /************************************************************************* | |
18 | * | |
19 | * ISP 4010 I/O Register Set Structure and Definitions | |
20 | * | |
21 | *************************************************************************/ | |
22 | ||
23 | struct port_ctrl_stat_regs { | |
b2854316 DS |
24 | __le32 ext_hw_conf; /* 0x50 R/W */ |
25 | __le32 rsrvd0; /* 0x54 */ | |
26 | __le32 port_ctrl; /* 0x58 */ | |
27 | __le32 port_status; /* 0x5c */ | |
28 | __le32 rsrvd1[32]; /* 0x60-0xdf */ | |
29 | __le32 gp_out; /* 0xe0 */ | |
30 | __le32 gp_in; /* 0xe4 */ | |
31 | __le32 rsrvd2[5]; /* 0xe8-0xfb */ | |
32 | __le32 port_err_status; /* 0xfc */ | |
afaf5a2d DS |
33 | }; |
34 | ||
35 | struct host_mem_cfg_regs { | |
b2854316 DS |
36 | __le32 rsrvd0[12]; /* 0x50-0x79 */ |
37 | __le32 req_q_out; /* 0x80 */ | |
38 | __le32 rsrvd1[31]; /* 0x84-0xFF */ | |
afaf5a2d DS |
39 | }; |
40 | ||
f4f5df23 VC |
41 | /* |
42 | * ISP 82xx I/O Register Set structure definitions. | |
43 | */ | |
44 | struct device_reg_82xx { | |
45 | __le32 req_q_out; /* 0x0000 (R): Request Queue out-Pointer. */ | |
46 | __le32 reserve1[63]; /* Request Queue out-Pointer. (64 * 4) */ | |
47 | __le32 rsp_q_in; /* 0x0100 (R/W): Response Queue In-Pointer. */ | |
48 | __le32 reserve2[63]; /* Response Queue In-Pointer. */ | |
49 | __le32 rsp_q_out; /* 0x0200 (R/W): Response Queue Out-Pointer. */ | |
50 | __le32 reserve3[63]; /* Response Queue Out-Pointer. */ | |
51 | ||
52 | __le32 mailbox_in[8]; /* 0x0300 (R/W): Mail box In registers */ | |
53 | __le32 reserve4[24]; | |
54 | __le32 hint; /* 0x0380 (R/W): Host interrupt register */ | |
55 | #define HINT_MBX_INT_PENDING BIT_0 | |
56 | __le32 reserve5[31]; | |
57 | __le32 mailbox_out[8]; /* 0x0400 (R): Mail box Out registers */ | |
58 | __le32 reserve6[56]; | |
59 | ||
60 | __le32 host_status; /* Offset 0x500 (R): host status */ | |
61 | #define HSRX_RISC_MB_INT BIT_0 /* RISC to Host Mailbox interrupt */ | |
62 | #define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */ | |
63 | ||
64 | __le32 host_int; /* Offset 0x0504 (R/W): Interrupt status. */ | |
65 | #define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */ | |
66 | }; | |
67 | ||
6e7b4292 VC |
68 | /* ISP 83xx I/O Register Set structure */ |
69 | struct device_reg_83xx { | |
70 | __le32 mailbox_in[16]; /* 0x0000 */ | |
71 | __le32 reserve1[496]; /* 0x0040 */ | |
72 | __le32 mailbox_out[16]; /* 0x0800 */ | |
73 | __le32 reserve2[496]; | |
74 | __le32 mbox_int; /* 0x1000 */ | |
75 | __le32 reserve3[63]; | |
76 | __le32 req_q_out; /* 0x1100 */ | |
77 | __le32 reserve4[63]; | |
78 | ||
79 | __le32 rsp_q_in; /* 0x1200 */ | |
80 | __le32 reserve5[1919]; | |
81 | ||
82 | __le32 req_q_in; /* 0x3000 */ | |
83 | __le32 reserve6[3]; | |
84 | __le32 iocb_int_mask; /* 0x3010 */ | |
85 | __le32 reserve7[3]; | |
86 | __le32 rsp_q_out; /* 0x3020 */ | |
87 | __le32 reserve8[3]; | |
88 | __le32 anonymousbuff; /* 0x3030 */ | |
89 | __le32 mb_int_mask; /* 0x3034 */ | |
90 | ||
91 | __le32 host_intr; /* 0x3038 - Host Interrupt Register */ | |
92 | __le32 risc_intr; /* 0x303C - RISC Interrupt Register */ | |
93 | __le32 reserve9[544]; | |
94 | __le32 leg_int_ptr; /* 0x38C0 - Legacy Interrupt Pointer Register */ | |
95 | __le32 leg_int_trig; /* 0x38C4 - Legacy Interrupt Trigger Control */ | |
96 | __le32 leg_int_mask; /* 0x38C8 - Legacy Interrupt Mask Register */ | |
97 | }; | |
98 | ||
99 | #define INT_ENABLE_FW_MB (1 << 2) | |
100 | #define INT_MASK_FW_MB (1 << 2) | |
101 | ||
afaf5a2d DS |
102 | /* remote register set (access via PCI memory read/write) */ |
103 | struct isp_reg { | |
104 | #define MBOX_REG_COUNT 8 | |
105 | __le32 mailbox[MBOX_REG_COUNT]; | |
106 | ||
107 | __le32 flash_address; /* 0x20 */ | |
108 | __le32 flash_data; | |
109 | __le32 ctrl_status; | |
110 | ||
111 | union { | |
112 | struct { | |
113 | __le32 nvram; | |
114 | __le32 reserved1[2]; /* 0x30 */ | |
115 | } __attribute__ ((packed)) isp4010; | |
116 | struct { | |
117 | __le32 intr_mask; | |
118 | __le32 nvram; /* 0x30 */ | |
119 | __le32 semaphore; | |
120 | } __attribute__ ((packed)) isp4022; | |
121 | } u1; | |
122 | ||
123 | __le32 req_q_in; /* SCSI Request Queue Producer Index */ | |
124 | __le32 rsp_q_out; /* SCSI Completion Queue Consumer Index */ | |
125 | ||
126 | __le32 reserved2[4]; /* 0x40 */ | |
127 | ||
128 | union { | |
129 | struct { | |
130 | __le32 ext_hw_conf; /* 0x50 */ | |
131 | __le32 flow_ctrl; | |
132 | __le32 port_ctrl; | |
133 | __le32 port_status; | |
134 | ||
135 | __le32 reserved3[8]; /* 0x60 */ | |
136 | ||
137 | __le32 req_q_out; /* 0x80 */ | |
138 | ||
139 | __le32 reserved4[23]; /* 0x84 */ | |
140 | ||
141 | __le32 gp_out; /* 0xe0 */ | |
142 | __le32 gp_in; | |
143 | ||
144 | __le32 reserved5[5]; | |
145 | ||
146 | __le32 port_err_status; /* 0xfc */ | |
147 | } __attribute__ ((packed)) isp4010; | |
148 | struct { | |
149 | union { | |
150 | struct port_ctrl_stat_regs p0; | |
151 | struct host_mem_cfg_regs p1; | |
afaf5a2d | 152 | }; |
afaf5a2d DS |
153 | } __attribute__ ((packed)) isp4022; |
154 | } u2; | |
155 | }; /* 256 x100 */ | |
156 | ||
157 | ||
158 | /* Semaphore Defines for 4010 */ | |
159 | #define QL4010_DRVR_SEM_BITS 0x00000030 | |
160 | #define QL4010_GPIO_SEM_BITS 0x000000c0 | |
161 | #define QL4010_SDRAM_SEM_BITS 0x00000300 | |
162 | #define QL4010_PHY_SEM_BITS 0x00000c00 | |
163 | #define QL4010_NVRAM_SEM_BITS 0x00003000 | |
164 | #define QL4010_FLASH_SEM_BITS 0x0000c000 | |
165 | ||
166 | #define QL4010_DRVR_SEM_MASK 0x00300000 | |
167 | #define QL4010_GPIO_SEM_MASK 0x00c00000 | |
168 | #define QL4010_SDRAM_SEM_MASK 0x03000000 | |
169 | #define QL4010_PHY_SEM_MASK 0x0c000000 | |
170 | #define QL4010_NVRAM_SEM_MASK 0x30000000 | |
171 | #define QL4010_FLASH_SEM_MASK 0xc0000000 | |
172 | ||
173 | /* Semaphore Defines for 4022 */ | |
174 | #define QL4022_RESOURCE_MASK_BASE_CODE 0x7 | |
175 | #define QL4022_RESOURCE_BITS_BASE_CODE 0x4 | |
176 | ||
177 | ||
178 | #define QL4022_DRVR_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (1+16)) | |
179 | #define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16)) | |
180 | #define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16)) | |
181 | #define QL4022_NVRAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (10+16)) | |
182 | #define QL4022_FLASH_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (13+16)) | |
183 | ||
2a991c21 MR |
184 | /* nvram address for 4032 */ |
185 | #define NVRAM_PORT0_BOOT_MODE 0x03b1 | |
186 | #define NVRAM_PORT0_BOOT_PRI_TGT 0x03b2 | |
187 | #define NVRAM_PORT0_BOOT_SEC_TGT 0x03bb | |
188 | #define NVRAM_PORT1_BOOT_MODE 0x07b1 | |
189 | #define NVRAM_PORT1_BOOT_PRI_TGT 0x07b2 | |
190 | #define NVRAM_PORT1_BOOT_SEC_TGT 0x07bb | |
afaf5a2d DS |
191 | |
192 | ||
193 | /* Page # defines for 4022 */ | |
194 | #define PORT_CTRL_STAT_PAGE 0 /* 4022 */ | |
195 | #define HOST_MEM_CFG_PAGE 1 /* 4022 */ | |
196 | #define LOCAL_RAM_CFG_PAGE 2 /* 4022 */ | |
197 | #define PROT_STAT_PAGE 3 /* 4022 */ | |
198 | ||
199 | /* Register Mask - sets corresponding mask bits in the upper word */ | |
200 | static inline uint32_t set_rmask(uint32_t val) | |
201 | { | |
202 | return (val & 0xffff) | (val << 16); | |
203 | } | |
204 | ||
205 | ||
206 | static inline uint32_t clr_rmask(uint32_t val) | |
207 | { | |
208 | return 0 | (val << 16); | |
209 | } | |
210 | ||
211 | /* ctrl_status definitions */ | |
212 | #define CSR_SCSI_PAGE_SELECT 0x00000003 | |
213 | #define CSR_SCSI_INTR_ENABLE 0x00000004 /* 4010 */ | |
214 | #define CSR_SCSI_RESET_INTR 0x00000008 | |
215 | #define CSR_SCSI_COMPLETION_INTR 0x00000010 | |
216 | #define CSR_SCSI_PROCESSOR_INTR 0x00000020 | |
217 | #define CSR_INTR_RISC 0x00000040 | |
218 | #define CSR_BOOT_ENABLE 0x00000080 | |
219 | #define CSR_NET_PAGE_SELECT 0x00000300 /* 4010 */ | |
220 | #define CSR_FUNC_NUM 0x00000700 /* 4022 */ | |
221 | #define CSR_NET_RESET_INTR 0x00000800 /* 4010 */ | |
222 | #define CSR_FORCE_SOFT_RESET 0x00002000 /* 4022 */ | |
223 | #define CSR_FATAL_ERROR 0x00004000 | |
224 | #define CSR_SOFT_RESET 0x00008000 | |
225 | #define ISP_CONTROL_FN_MASK CSR_FUNC_NUM | |
226 | #define ISP_CONTROL_FN0_SCSI 0x0500 | |
227 | #define ISP_CONTROL_FN1_SCSI 0x0700 | |
228 | ||
229 | #define INTR_PENDING (CSR_SCSI_COMPLETION_INTR |\ | |
230 | CSR_SCSI_PROCESSOR_INTR |\ | |
231 | CSR_SCSI_RESET_INTR) | |
232 | ||
233 | /* ISP InterruptMask definitions */ | |
234 | #define IMR_SCSI_INTR_ENABLE 0x00000004 /* 4022 */ | |
235 | ||
236 | /* ISP 4022 nvram definitions */ | |
237 | #define NVR_WRITE_ENABLE 0x00000010 /* 4022 */ | |
238 | ||
7c07d139 HZ |
239 | #define QL4010_NVRAM_SIZE 0x200 |
240 | #define QL40X2_NVRAM_SIZE 0x800 | |
241 | ||
afaf5a2d DS |
242 | /* ISP port_status definitions */ |
243 | ||
244 | /* ISP Semaphore definitions */ | |
245 | ||
246 | /* ISP General Purpose Output definitions */ | |
b2854316 | 247 | #define GPOR_TOPCAT_RESET 0x00000004 |
afaf5a2d DS |
248 | |
249 | /* shadow registers (DMA'd from HA to system memory. read only) */ | |
250 | struct shadow_regs { | |
251 | /* SCSI Request Queue Consumer Index */ | |
252 | __le32 req_q_out; /* 0 x0 R */ | |
253 | ||
254 | /* SCSI Completion Queue Producer Index */ | |
255 | __le32 rsp_q_in; /* 4 x4 R */ | |
256 | }; /* 8 x8 */ | |
257 | ||
258 | ||
259 | /* External hardware configuration register */ | |
260 | union external_hw_config_reg { | |
261 | struct { | |
262 | /* FIXME: Do we even need this? All values are | |
263 | * referred to by 16 bit quantities. Platform and | |
264 | * endianess issues. */ | |
265 | __le32 bReserved0:1; | |
266 | __le32 bSDRAMProtectionMethod:2; | |
267 | __le32 bSDRAMBanks:1; | |
268 | __le32 bSDRAMChipWidth:1; | |
269 | __le32 bSDRAMChipSize:2; | |
270 | __le32 bParityDisable:1; | |
271 | __le32 bExternalMemoryType:1; | |
272 | __le32 bFlashBIOSWriteEnable:1; | |
273 | __le32 bFlashUpperBankSelect:1; | |
274 | __le32 bWriteBurst:2; | |
275 | __le32 bReserved1:3; | |
276 | __le32 bMask:16; | |
277 | }; | |
278 | uint32_t Asuint32_t; | |
279 | }; | |
280 | ||
f4f5df23 VC |
281 | /* 82XX Support start */ |
282 | /* 82xx Default FLT Addresses */ | |
283 | #define FA_FLASH_LAYOUT_ADDR_82 0xFC400 | |
284 | #define FA_FLASH_DESCR_ADDR_82 0xFC000 | |
285 | #define FA_BOOT_LOAD_ADDR_82 0x04000 | |
286 | #define FA_BOOT_CODE_ADDR_82 0x20000 | |
287 | #define FA_RISC_CODE_ADDR_82 0x40000 | |
288 | #define FA_GOLD_RISC_CODE_ADDR_82 0x80000 | |
4549415a LC |
289 | #define FA_FLASH_ISCSI_CHAP 0x540000 |
290 | #define FA_FLASH_CHAP_SIZE 0xC0000 | |
1e9e2be3 AC |
291 | #define FA_FLASH_ISCSI_DDB 0x420000 |
292 | #define FA_FLASH_DDB_SIZE 0x080000 | |
f4f5df23 VC |
293 | |
294 | /* Flash Description Table */ | |
295 | struct qla_fdt_layout { | |
296 | uint8_t sig[4]; | |
297 | uint16_t version; | |
298 | uint16_t len; | |
299 | uint16_t checksum; | |
300 | uint8_t unused1[2]; | |
301 | uint8_t model[16]; | |
302 | uint16_t man_id; | |
303 | uint16_t id; | |
304 | uint8_t flags; | |
305 | uint8_t erase_cmd; | |
306 | uint8_t alt_erase_cmd; | |
307 | uint8_t wrt_enable_cmd; | |
308 | uint8_t wrt_enable_bits; | |
309 | uint8_t wrt_sts_reg_cmd; | |
310 | uint8_t unprotect_sec_cmd; | |
311 | uint8_t read_man_id_cmd; | |
312 | uint32_t block_size; | |
313 | uint32_t alt_block_size; | |
314 | uint32_t flash_size; | |
315 | uint32_t wrt_enable_data; | |
316 | uint8_t read_id_addr_len; | |
317 | uint8_t wrt_disable_bits; | |
318 | uint8_t read_dev_id_len; | |
319 | uint8_t chip_erase_cmd; | |
320 | uint16_t read_timeout; | |
321 | uint8_t protect_sec_cmd; | |
322 | uint8_t unused2[65]; | |
323 | }; | |
324 | ||
325 | /* Flash Layout Table */ | |
326 | ||
327 | struct qla_flt_location { | |
328 | uint8_t sig[4]; | |
329 | uint16_t start_lo; | |
330 | uint16_t start_hi; | |
331 | uint8_t version; | |
332 | uint8_t unused[5]; | |
333 | uint16_t checksum; | |
334 | }; | |
335 | ||
336 | struct qla_flt_header { | |
337 | uint16_t version; | |
338 | uint16_t length; | |
339 | uint16_t checksum; | |
340 | uint16_t unused; | |
341 | }; | |
342 | ||
343 | /* 82xx FLT Regions */ | |
344 | #define FLT_REG_FDT 0x1a | |
345 | #define FLT_REG_FLT 0x1c | |
346 | #define FLT_REG_BOOTLOAD_82 0x72 | |
347 | #define FLT_REG_FW_82 0x74 | |
93823956 | 348 | #define FLT_REG_FW_82_1 0x97 |
f4f5df23 VC |
349 | #define FLT_REG_GOLD_FW_82 0x75 |
350 | #define FLT_REG_BOOT_CODE_82 0x78 | |
2a991c21 | 351 | #define FLT_REG_ISCSI_PARAM 0x65 |
4549415a | 352 | #define FLT_REG_ISCSI_CHAP 0x63 |
1e9e2be3 | 353 | #define FLT_REG_ISCSI_DDB 0x6A |
f4f5df23 VC |
354 | |
355 | struct qla_flt_region { | |
356 | uint32_t code; | |
357 | uint32_t size; | |
358 | uint32_t start; | |
359 | uint32_t end; | |
360 | }; | |
361 | ||
afaf5a2d DS |
362 | /************************************************************************* |
363 | * | |
364 | * Mailbox Commands Structures and Definitions | |
365 | * | |
366 | *************************************************************************/ | |
367 | ||
368 | /* Mailbox command definitions */ | |
369 | #define MBOX_CMD_ABOUT_FW 0x0009 | |
b2854316 | 370 | #define MBOX_CMD_PING 0x000B |
c0b9d3f7 VC |
371 | #define PING_IPV6_PROTOCOL_ENABLE 0x1 |
372 | #define PING_IPV6_LINKLOCAL_ADDR 0x4 | |
373 | #define PING_IPV6_ADDR0 0x8 | |
374 | #define PING_IPV6_ADDR1 0xC | |
f4f5df23 VC |
375 | #define MBOX_CMD_ENABLE_INTRS 0x0010 |
376 | #define INTR_DISABLE 0 | |
377 | #define INTR_ENABLE 1 | |
378 | #define MBOX_CMD_STOP_FW 0x0014 | |
09a0f719 | 379 | #define MBOX_CMD_ABORT_TASK 0x0015 |
afaf5a2d | 380 | #define MBOX_CMD_LUN_RESET 0x0016 |
ce545039 | 381 | #define MBOX_CMD_TARGET_WARM_RESET 0x0017 |
d915058f | 382 | #define MBOX_CMD_GET_MANAGEMENT_DATA 0x001E |
afaf5a2d DS |
383 | #define MBOX_CMD_GET_FW_STATUS 0x001F |
384 | #define MBOX_CMD_SET_ISNS_SERVICE 0x0021 | |
385 | #define ISNS_DISABLE 0 | |
386 | #define ISNS_ENABLE 1 | |
d915058f DS |
387 | #define MBOX_CMD_COPY_FLASH 0x0024 |
388 | #define MBOX_CMD_WRITE_FLASH 0x0025 | |
afaf5a2d DS |
389 | #define MBOX_CMD_READ_FLASH 0x0026 |
390 | #define MBOX_CMD_CLEAR_DATABASE_ENTRY 0x0031 | |
b3a271a9 | 391 | #define MBOX_CMD_CONN_OPEN 0x0074 |
afaf5a2d | 392 | #define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT 0x0056 |
de2efea6 | 393 | #define DDB_NOT_LOGGED_IN 0x09 |
b3a271a9 MR |
394 | #define LOGOUT_OPTION_CLOSE_SESSION 0x0002 |
395 | #define LOGOUT_OPTION_RELOGIN 0x0004 | |
396 | #define LOGOUT_OPTION_FREE_DDB 0x0008 | |
cfb27874 MD |
397 | #define MBOX_CMD_SET_PARAM 0x0059 |
398 | #define SET_DRVR_VERSION 0x200 | |
399 | #define MAX_DRVR_VER_LEN 24 | |
afaf5a2d DS |
400 | #define MBOX_CMD_EXECUTE_IOCB_A64 0x005A |
401 | #define MBOX_CMD_INITIALIZE_FIRMWARE 0x0060 | |
402 | #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK 0x0061 | |
403 | #define MBOX_CMD_REQUEST_DATABASE_ENTRY 0x0062 | |
404 | #define MBOX_CMD_SET_DATABASE_ENTRY 0x0063 | |
405 | #define MBOX_CMD_GET_DATABASE_ENTRY 0x0064 | |
406 | #define DDB_DS_UNASSIGNED 0x00 | |
407 | #define DDB_DS_NO_CONNECTION_ACTIVE 0x01 | |
b3a271a9 | 408 | #define DDB_DS_DISCOVERY 0x02 |
afaf5a2d DS |
409 | #define DDB_DS_SESSION_ACTIVE 0x04 |
410 | #define DDB_DS_SESSION_FAILED 0x06 | |
411 | #define DDB_DS_LOGIN_IN_PROCESS 0x07 | |
412 | #define MBOX_CMD_GET_FW_STATE 0x0069 | |
d915058f | 413 | #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A |
df86f771 | 414 | #define MBOX_CMD_DIAG_TEST 0x0075 |
f4f5df23 | 415 | #define MBOX_CMD_GET_SYS_INFO 0x0078 |
7c07d139 HZ |
416 | #define MBOX_CMD_GET_NVRAM 0x0078 /* For 40xx */ |
417 | #define MBOX_CMD_SET_NVRAM 0x0079 /* For 40xx */ | |
d915058f | 418 | #define MBOX_CMD_RESTORE_FACTORY_DEFAULTS 0x0087 |
b2854316 DS |
419 | #define MBOX_CMD_SET_ACB 0x0088 |
420 | #define MBOX_CMD_GET_ACB 0x0089 | |
421 | #define MBOX_CMD_DISABLE_ACB 0x008A | |
422 | #define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE 0x008B | |
423 | #define MBOX_CMD_GET_IPV6_DEST_CACHE 0x008C | |
424 | #define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST 0x008D | |
425 | #define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST 0x008E | |
426 | #define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE 0x0090 | |
427 | #define MBOX_CMD_GET_IP_ADDR_STATE 0x0091 | |
428 | #define MBOX_CMD_SEND_IPV6_ROUTER_SOL 0x0092 | |
429 | #define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR 0x0093 | |
df86f771 VC |
430 | #define MBOX_CMD_SET_PORT_CONFIG 0x0122 |
431 | #define MBOX_CMD_GET_PORT_CONFIG 0x0123 | |
432 | #define MBOX_CMD_SET_LED_CONFIG 0x0125 | |
433 | #define MBOX_CMD_GET_LED_CONFIG 0x0126 | |
068237c8 TP |
434 | #define MBOX_CMD_MINIDUMP 0x0129 |
435 | ||
df86f771 VC |
436 | /* Port Config */ |
437 | #define ENABLE_INTERNAL_LOOPBACK 0x04 | |
438 | #define ENABLE_EXTERNAL_LOOPBACK 0x08 | |
439 | #define ENABLE_DCBX 0x10 | |
440 | ||
068237c8 TP |
441 | /* Minidump subcommand */ |
442 | #define MINIDUMP_GET_SIZE_SUBCOMMAND 0x00 | |
443 | #define MINIDUMP_GET_TMPLT_SUBCOMMAND 0x01 | |
afaf5a2d DS |
444 | |
445 | /* Mailbox 1 */ | |
446 | #define FW_STATE_READY 0x0000 | |
447 | #define FW_STATE_CONFIG_WAIT 0x0001 | |
2a49a78e | 448 | #define FW_STATE_WAIT_AUTOCONNECT 0x0002 |
afaf5a2d | 449 | #define FW_STATE_ERROR 0x0004 |
2a49a78e | 450 | #define FW_STATE_CONFIGURING_IP 0x0008 |
afaf5a2d DS |
451 | |
452 | /* Mailbox 3 */ | |
453 | #define FW_ADDSTATE_OPTICAL_MEDIA 0x0001 | |
2a49a78e VC |
454 | #define FW_ADDSTATE_DHCPv4_ENABLED 0x0002 |
455 | #define FW_ADDSTATE_DHCPv4_LEASE_ACQUIRED 0x0004 | |
456 | #define FW_ADDSTATE_DHCPv4_LEASE_EXPIRED 0x0008 | |
afaf5a2d DS |
457 | #define FW_ADDSTATE_LINK_UP 0x0010 |
458 | #define FW_ADDSTATE_ISNS_SVC_ENABLED 0x0020 | |
3254dbe9 VC |
459 | #define FW_ADDSTATE_LINK_SPEED_10MBPS 0x0100 |
460 | #define FW_ADDSTATE_LINK_SPEED_100MBPS 0x0200 | |
461 | #define FW_ADDSTATE_LINK_SPEED_1GBPS 0x0400 | |
462 | #define FW_ADDSTATE_LINK_SPEED_10GBPS 0x0800 | |
b3a271a9 | 463 | |
afaf5a2d | 464 | #define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS 0x006B |
b3a271a9 MR |
465 | #define IPV6_DEFAULT_DDB_ENTRY 0x0001 |
466 | ||
afaf5a2d DS |
467 | #define MBOX_CMD_CONN_OPEN_SESS_LOGIN 0x0074 |
468 | #define MBOX_CMD_GET_CRASH_RECORD 0x0076 /* 4010 only */ | |
469 | #define MBOX_CMD_GET_CONN_EVENT_LOG 0x0077 | |
470 | ||
320a61de | 471 | #define MBOX_CMD_IDC_ACK 0x0101 |
7ab284c9 | 472 | #define MBOX_CMD_IDC_TIME_EXTEND 0x0102 |
320a61de NJ |
473 | #define MBOX_CMD_PORT_RESET 0x0120 |
474 | #define MBOX_CMD_SET_PORT_CONFIG 0x0122 | |
475 | ||
afaf5a2d DS |
476 | /* Mailbox status definitions */ |
477 | #define MBOX_COMPLETION_STATUS 4 | |
478 | #define MBOX_STS_BUSY 0x0007 | |
479 | #define MBOX_STS_INTERMEDIATE_COMPLETION 0x1000 | |
480 | #define MBOX_STS_COMMAND_COMPLETE 0x4000 | |
481 | #define MBOX_STS_COMMAND_ERROR 0x4005 | |
482 | ||
483 | #define MBOX_ASYNC_EVENT_STATUS 8 | |
484 | #define MBOX_ASTS_SYSTEM_ERROR 0x8002 | |
485 | #define MBOX_ASTS_REQUEST_TRANSFER_ERROR 0x8003 | |
486 | #define MBOX_ASTS_RESPONSE_TRANSFER_ERROR 0x8004 | |
487 | #define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM 0x8005 | |
488 | #define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED 0x8006 | |
489 | #define MBOX_ASTS_LINK_UP 0x8010 | |
490 | #define MBOX_ASTS_LINK_DOWN 0x8011 | |
491 | #define MBOX_ASTS_DATABASE_CHANGED 0x8014 | |
492 | #define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED 0x8015 | |
493 | #define MBOX_ASTS_SELF_TEST_FAILED 0x8016 | |
494 | #define MBOX_ASTS_LOGIN_FAILED 0x8017 | |
495 | #define MBOX_ASTS_DNS 0x8018 | |
496 | #define MBOX_ASTS_HEARTBEAT 0x8019 | |
497 | #define MBOX_ASTS_NVRAM_INVALID 0x801A | |
498 | #define MBOX_ASTS_MAC_ADDRESS_CHANGED 0x801B | |
499 | #define MBOX_ASTS_IP_ADDRESS_CHANGED 0x801C | |
500 | #define MBOX_ASTS_DHCP_LEASE_EXPIRED 0x801D | |
501 | #define MBOX_ASTS_DHCP_LEASE_ACQUIRED 0x801F | |
502 | #define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021 | |
b2854316 DS |
503 | #define MBOX_ASTS_DUPLICATE_IP 0x8025 |
504 | #define MBOX_ASTS_ARP_COMPLETE 0x8026 | |
505 | #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027 | |
506 | #define MBOX_ASTS_RESPONSE_QUEUE_FULL 0x8028 | |
507 | #define MBOX_ASTS_IP_ADDR_STATE_CHANGED 0x8029 | |
78a45448 | 508 | #define MBOX_ASTS_IPV6_DEFAULT_ROUTER_CHANGED 0x802A |
4820002d NJ |
509 | #define MBOX_ASTS_IPV6_LINK_MTU_CHANGE 0x802B |
510 | #define MBOX_ASTS_IPV6_AUTO_PREFIX_IGNORED 0x802C | |
511 | #define MBOX_ASTS_IPV6_ND_LOCAL_PREFIX_IGNORED 0x802D | |
b2854316 | 512 | #define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD 0x802E |
78a45448 VC |
513 | #define MBOX_ASTS_INITIALIZATION_FAILED 0x8031 |
514 | #define MBOX_ASTS_SYSTEM_WARNING_EVENT 0x8036 | |
320a61de | 515 | #define MBOX_ASTS_IDC_COMPLETE 0x8100 |
9cb33f18 | 516 | #define MBOX_ASTS_IDC_REQUEST_NOTIFICATION 0x8101 |
7ab284c9 | 517 | #define MBOX_ASTS_IDC_TIME_EXTEND_NOTIFICATION 0x8102 |
78a45448 | 518 | #define MBOX_ASTS_DCBX_CONF_CHANGE 0x8110 |
6434080b SS |
519 | #define MBOX_ASTS_TXSCVR_INSERTED 0x8130 |
520 | #define MBOX_ASTS_TXSCVR_REMOVED 0x8131 | |
b2854316 | 521 | |
afaf5a2d DS |
522 | #define ISNS_EVENT_DATA_RECEIVED 0x0000 |
523 | #define ISNS_EVENT_CONNECTION_OPENED 0x0001 | |
524 | #define ISNS_EVENT_CONNECTION_FAILED 0x0002 | |
525 | #define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR 0x8022 | |
526 | #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027 | |
527 | ||
7ab284c9 NJ |
528 | /* ACB Configuration Defines */ |
529 | #define ACB_CONFIG_DISABLE 0x00 | |
530 | #define ACB_CONFIG_SET 0x01 | |
531 | ||
7f15ebce NJ |
532 | /* ACB/IP Address State Defines */ |
533 | #define IP_ADDRSTATE_UNCONFIGURED 0 | |
534 | #define IP_ADDRSTATE_INVALID 1 | |
535 | #define IP_ADDRSTATE_ACQUIRING 2 | |
536 | #define IP_ADDRSTATE_TENTATIVE 3 | |
537 | #define IP_ADDRSTATE_DEPRICATED 4 | |
538 | #define IP_ADDRSTATE_PREFERRED 5 | |
539 | #define IP_ADDRSTATE_DISABLING 6 | |
f4f5df23 | 540 | |
d00efe3f MC |
541 | /* FLASH offsets */ |
542 | #define FLASH_SEGMENT_IFCB 0x04000000 | |
543 | ||
544 | #define FLASH_OPT_RMW_HOLD 0 | |
545 | #define FLASH_OPT_RMW_INIT 1 | |
546 | #define FLASH_OPT_COMMIT 2 | |
547 | #define FLASH_OPT_RMW_COMMIT 3 | |
548 | ||
244c079b AC |
549 | /* generic defines to enable/disable params */ |
550 | #define QL4_PARAM_DISABLE 0 | |
551 | #define QL4_PARAM_ENABLE 1 | |
552 | ||
afaf5a2d DS |
553 | /*************************************************************************/ |
554 | ||
555 | /* Host Adapter Initialization Control Block (from host) */ | |
b2854316 DS |
556 | struct addr_ctrl_blk { |
557 | uint8_t version; /* 00 */ | |
2a49a78e VC |
558 | #define IFCB_VER_MIN 0x01 |
559 | #define IFCB_VER_MAX 0x02 | |
b2854316 | 560 | uint8_t control; /* 01 */ |
f8e93412 | 561 | #define CTRLOPT_NEW_CONN_DISABLE 0x0002 |
afaf5a2d | 562 | |
b2854316 | 563 | uint16_t fw_options; /* 02-03 */ |
afaf5a2d DS |
564 | #define FWOPT_HEARTBEAT_ENABLE 0x1000 |
565 | #define FWOPT_SESSION_MODE 0x0040 | |
566 | #define FWOPT_INITIATOR_MODE 0x0020 | |
567 | #define FWOPT_TARGET_MODE 0x0010 | |
2657c800 | 568 | #define FWOPT_ENABLE_CRBDB 0x8000 |
afaf5a2d | 569 | |
b2854316 DS |
570 | uint16_t exec_throttle; /* 04-05 */ |
571 | uint8_t zio_count; /* 06 */ | |
572 | uint8_t res0; /* 07 */ | |
573 | uint16_t eth_mtu_size; /* 08-09 */ | |
574 | uint16_t add_fw_options; /* 0A-0B */ | |
b3a271a9 MR |
575 | #define ADFWOPT_SERIALIZE_TASK_MGMT 0x0400 |
576 | #define ADFWOPT_AUTOCONN_DISABLE 0x0002 | |
b2854316 DS |
577 | |
578 | uint8_t hb_interval; /* 0C */ | |
579 | uint8_t inst_num; /* 0D */ | |
580 | uint16_t res1; /* 0E-0F */ | |
581 | uint16_t rqq_consumer_idx; /* 10-11 */ | |
582 | uint16_t compq_producer_idx; /* 12-13 */ | |
583 | uint16_t rqq_len; /* 14-15 */ | |
584 | uint16_t compq_len; /* 16-17 */ | |
585 | uint32_t rqq_addr_lo; /* 18-1B */ | |
586 | uint32_t rqq_addr_hi; /* 1C-1F */ | |
587 | uint32_t compq_addr_lo; /* 20-23 */ | |
588 | uint32_t compq_addr_hi; /* 24-27 */ | |
589 | uint32_t shdwreg_addr_lo; /* 28-2B */ | |
590 | uint32_t shdwreg_addr_hi; /* 2C-2F */ | |
591 | ||
592 | uint16_t iscsi_opts; /* 30-31 */ | |
f8e93412 HZ |
593 | #define ISCSIOPTS_HEADER_DIGEST_EN 0x2000 |
594 | #define ISCSIOPTS_DATA_DIGEST_EN 0x1000 | |
595 | #define ISCSIOPTS_IMMEDIATE_DATA_EN 0x0800 | |
596 | #define ISCSIOPTS_INITIAL_R2T_EN 0x0400 | |
597 | #define ISCSIOPTS_DATA_SEQ_INORDER_EN 0x0200 | |
598 | #define ISCSIOPTS_DATA_PDU_INORDER_EN 0x0100 | |
599 | #define ISCSIOPTS_CHAP_AUTH_EN 0x0080 | |
600 | #define ISCSIOPTS_SNACK_EN 0x0040 | |
601 | #define ISCSIOPTS_DISCOVERY_LOGOUT_EN 0x0020 | |
602 | #define ISCSIOPTS_BIDI_CHAP_EN 0x0010 | |
603 | #define ISCSIOPTS_DISCOVERY_AUTH_EN 0x0008 | |
604 | #define ISCSIOPTS_STRICT_LOGIN_COMP_EN 0x0004 | |
605 | #define ISCSIOPTS_ERL 0x0003 | |
b2854316 | 606 | uint16_t ipv4_tcp_opts; /* 32-33 */ |
f8e93412 | 607 | #define TCPOPT_DELAYED_ACK_DISABLE 0x8000 |
d00efe3f | 608 | #define TCPOPT_DHCP_ENABLE 0x0200 |
f8e93412 HZ |
609 | #define TCPOPT_DNS_SERVER_IP_EN 0x0100 |
610 | #define TCPOPT_SLP_DA_INFO_EN 0x0080 | |
611 | #define TCPOPT_NAGLE_ALGO_DISABLE 0x0020 | |
612 | #define TCPOPT_WINDOW_SCALE_DISABLE 0x0010 | |
613 | #define TCPOPT_TIMER_SCALE 0x000E | |
614 | #define TCPOPT_TIMESTAMP_ENABLE 0x0001 | |
b2854316 | 615 | uint16_t ipv4_ip_opts; /* 34-35 */ |
2bab08fc | 616 | #define IPOPT_IPV4_PROTOCOL_ENABLE 0x8000 |
f8e93412 | 617 | #define IPOPT_IPV4_TOS_EN 0x4000 |
6ac73e8c | 618 | #define IPOPT_VLAN_TAGGING_ENABLE 0x2000 |
f8e93412 HZ |
619 | #define IPOPT_GRAT_ARP_EN 0x1000 |
620 | #define IPOPT_ALT_CID_EN 0x0800 | |
621 | #define IPOPT_REQ_VID_EN 0x0400 | |
622 | #define IPOPT_USE_VID_EN 0x0200 | |
623 | #define IPOPT_LEARN_IQN_EN 0x0100 | |
624 | #define IPOPT_FRAGMENTATION_DISABLE 0x0010 | |
625 | #define IPOPT_IN_FORWARD_EN 0x0008 | |
626 | #define IPOPT_ARP_REDIRECT_EN 0x0004 | |
b2854316 DS |
627 | |
628 | uint16_t iscsi_max_pdu_size; /* 36-37 */ | |
629 | uint8_t ipv4_tos; /* 38 */ | |
630 | uint8_t ipv4_ttl; /* 39 */ | |
631 | uint8_t acb_version; /* 3A */ | |
2a49a78e VC |
632 | #define ACB_NOT_SUPPORTED 0x00 |
633 | #define ACB_SUPPORTED 0x02 /* Capable of ACB Version 2 | |
634 | Features */ | |
635 | ||
b2854316 DS |
636 | uint8_t res2; /* 3B */ |
637 | uint16_t def_timeout; /* 3C-3D */ | |
638 | uint16_t iscsi_fburst_len; /* 3E-3F */ | |
639 | uint16_t iscsi_def_time2wait; /* 40-41 */ | |
640 | uint16_t iscsi_def_time2retain; /* 42-43 */ | |
641 | uint16_t iscsi_max_outstnd_r2t; /* 44-45 */ | |
642 | uint16_t conn_ka_timeout; /* 46-47 */ | |
643 | uint16_t ipv4_port; /* 48-49 */ | |
644 | uint16_t iscsi_max_burst_len; /* 4A-4B */ | |
645 | uint32_t res5; /* 4C-4F */ | |
646 | uint8_t ipv4_addr[4]; /* 50-53 */ | |
647 | uint16_t ipv4_vlan_tag; /* 54-55 */ | |
648 | uint8_t ipv4_addr_state; /* 56 */ | |
649 | uint8_t ipv4_cacheid; /* 57 */ | |
650 | uint8_t res6[8]; /* 58-5F */ | |
651 | uint8_t ipv4_subnet[4]; /* 60-63 */ | |
652 | uint8_t res7[12]; /* 64-6F */ | |
653 | uint8_t ipv4_gw_addr[4]; /* 70-73 */ | |
654 | uint8_t res8[0xc]; /* 74-7F */ | |
655 | uint8_t pri_dns_srvr_ip[4];/* 80-83 */ | |
656 | uint8_t sec_dns_srvr_ip[4];/* 84-87 */ | |
657 | uint16_t min_eph_port; /* 88-89 */ | |
658 | uint16_t max_eph_port; /* 8A-8B */ | |
659 | uint8_t res9[4]; /* 8C-8F */ | |
660 | uint8_t iscsi_alias[32];/* 90-AF */ | |
661 | uint8_t res9_1[0x16]; /* B0-C5 */ | |
662 | uint16_t tgt_portal_grp;/* C6-C7 */ | |
663 | uint8_t abort_timer; /* C8 */ | |
664 | uint8_t ipv4_tcp_wsf; /* C9 */ | |
665 | uint8_t res10[6]; /* CA-CF */ | |
666 | uint8_t ipv4_sec_ip_addr[4]; /* D0-D3 */ | |
667 | uint8_t ipv4_dhcp_vid_len; /* D4 */ | |
668 | uint8_t ipv4_dhcp_vid[11]; /* D5-DF */ | |
669 | uint8_t res11[20]; /* E0-F3 */ | |
670 | uint8_t ipv4_dhcp_alt_cid_len; /* F4 */ | |
671 | uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */ | |
672 | uint8_t iscsi_name[224]; /* 100-1DF */ | |
673 | uint8_t res12[32]; /* 1E0-1FF */ | |
674 | uint32_t cookie; /* 200-203 */ | |
675 | uint16_t ipv6_port; /* 204-205 */ | |
676 | uint16_t ipv6_opts; /* 206-207 */ | |
f8e93412 HZ |
677 | #define IPV6_OPT_IPV6_PROTOCOL_ENABLE 0x8000 |
678 | #define IPV6_OPT_VLAN_TAGGING_ENABLE 0x2000 | |
679 | #define IPV6_OPT_GRAT_NEIGHBOR_ADV_EN 0x1000 | |
680 | #define IPV6_OPT_REDIRECT_EN 0x0004 | |
2a49a78e | 681 | |
b2854316 | 682 | uint16_t ipv6_addtl_opts; /* 208-209 */ |
f8e93412 HZ |
683 | #define IPV6_ADDOPT_IGNORE_ICMP_ECHO_REQ 0x0040 |
684 | #define IPV6_ADDOPT_MLD_EN 0x0004 | |
2a49a78e VC |
685 | #define IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE 0x0002 /* Pri ACB |
686 | Only */ | |
687 | #define IPV6_ADDOPT_AUTOCONFIG_LINK_LOCAL_ADDR 0x0001 | |
688 | ||
b2854316 | 689 | uint16_t ipv6_tcp_opts; /* 20A-20B */ |
f8e93412 HZ |
690 | #define IPV6_TCPOPT_DELAYED_ACK_DISABLE 0x8000 |
691 | #define IPV6_TCPOPT_NAGLE_ALGO_DISABLE 0x0020 | |
692 | #define IPV6_TCPOPT_WINDOW_SCALE_DISABLE 0x0010 | |
693 | #define IPV6_TCPOPT_TIMER_SCALE 0x000E | |
694 | #define IPV6_TCPOPT_TIMESTAMP_EN 0x0001 | |
b2854316 DS |
695 | uint8_t ipv6_tcp_wsf; /* 20C */ |
696 | uint16_t ipv6_flow_lbl; /* 20D-20F */ | |
2a49a78e | 697 | uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */ |
b2854316 DS |
698 | uint16_t ipv6_vlan_tag; /* 220-221 */ |
699 | uint8_t ipv6_lnk_lcl_addr_state;/* 222 */ | |
700 | uint8_t ipv6_addr0_state; /* 223 */ | |
701 | uint8_t ipv6_addr1_state; /* 224 */ | |
2a49a78e VC |
702 | uint8_t ipv6_dflt_rtr_state; /* 225 */ |
703 | #define IPV6_RTRSTATE_UNKNOWN 0 | |
704 | #define IPV6_RTRSTATE_MANUAL 1 | |
705 | #define IPV6_RTRSTATE_ADVERTISED 3 | |
706 | #define IPV6_RTRSTATE_STALE 4 | |
707 | ||
b2854316 DS |
708 | uint8_t ipv6_traffic_class; /* 226 */ |
709 | uint8_t ipv6_hop_limit; /* 227 */ | |
710 | uint8_t ipv6_if_id[8]; /* 228-22F */ | |
711 | uint8_t ipv6_addr0[16]; /* 230-23F */ | |
712 | uint8_t ipv6_addr1[16]; /* 240-24F */ | |
713 | uint32_t ipv6_nd_reach_time; /* 250-253 */ | |
714 | uint32_t ipv6_nd_rexmit_timer; /* 254-257 */ | |
715 | uint32_t ipv6_nd_stale_timeout; /* 258-25B */ | |
716 | uint8_t ipv6_dup_addr_detect_count; /* 25C */ | |
717 | uint8_t ipv6_cache_id; /* 25D */ | |
718 | uint8_t res13[18]; /* 25E-26F */ | |
719 | uint32_t ipv6_gw_advrt_mtu; /* 270-273 */ | |
720 | uint8_t res14[140]; /* 274-2FF */ | |
721 | }; | |
722 | ||
13483730 MC |
723 | #define IP_ADDR_COUNT 4 /* Total 4 IP address supported in one interface |
724 | * One IPv4, one IPv6 link local and 2 IPv6 | |
725 | */ | |
726 | ||
727 | #define IP_STATE_MASK 0x0F000000 | |
728 | #define IP_STATE_SHIFT 24 | |
729 | ||
b2854316 DS |
730 | struct init_fw_ctrl_blk { |
731 | struct addr_ctrl_blk pri; | |
2a49a78e | 732 | /* struct addr_ctrl_blk sec;*/ |
afaf5a2d DS |
733 | }; |
734 | ||
95d31262 VC |
735 | #define PRIMARI_ACB 0 |
736 | #define SECONDARY_ACB 1 | |
737 | ||
d00efe3f MC |
738 | struct addr_ctrl_blk_def { |
739 | uint8_t reserved1[1]; /* 00 */ | |
740 | uint8_t control; /* 01 */ | |
741 | uint8_t reserved2[11]; /* 02-0C */ | |
742 | uint8_t inst_num; /* 0D */ | |
743 | uint8_t reserved3[34]; /* 0E-2F */ | |
744 | uint16_t iscsi_opts; /* 30-31 */ | |
745 | uint16_t ipv4_tcp_opts; /* 32-33 */ | |
746 | uint16_t ipv4_ip_opts; /* 34-35 */ | |
747 | uint16_t iscsi_max_pdu_size; /* 36-37 */ | |
748 | uint8_t ipv4_tos; /* 38 */ | |
749 | uint8_t ipv4_ttl; /* 39 */ | |
750 | uint8_t reserved4[2]; /* 3A-3B */ | |
751 | uint16_t def_timeout; /* 3C-3D */ | |
752 | uint16_t iscsi_fburst_len; /* 3E-3F */ | |
753 | uint8_t reserved5[4]; /* 40-43 */ | |
754 | uint16_t iscsi_max_outstnd_r2t; /* 44-45 */ | |
755 | uint8_t reserved6[2]; /* 46-47 */ | |
756 | uint16_t ipv4_port; /* 48-49 */ | |
757 | uint16_t iscsi_max_burst_len; /* 4A-4B */ | |
758 | uint8_t reserved7[4]; /* 4C-4F */ | |
759 | uint8_t ipv4_addr[4]; /* 50-53 */ | |
760 | uint16_t ipv4_vlan_tag; /* 54-55 */ | |
761 | uint8_t ipv4_addr_state; /* 56 */ | |
762 | uint8_t ipv4_cacheid; /* 57 */ | |
763 | uint8_t reserved8[8]; /* 58-5F */ | |
764 | uint8_t ipv4_subnet[4]; /* 60-63 */ | |
765 | uint8_t reserved9[12]; /* 64-6F */ | |
766 | uint8_t ipv4_gw_addr[4]; /* 70-73 */ | |
767 | uint8_t reserved10[84]; /* 74-C7 */ | |
768 | uint8_t abort_timer; /* C8 */ | |
769 | uint8_t ipv4_tcp_wsf; /* C9 */ | |
770 | uint8_t reserved11[10]; /* CA-D3 */ | |
771 | uint8_t ipv4_dhcp_vid_len; /* D4 */ | |
772 | uint8_t ipv4_dhcp_vid[11]; /* D5-DF */ | |
773 | uint8_t reserved12[20]; /* E0-F3 */ | |
774 | uint8_t ipv4_dhcp_alt_cid_len; /* F4 */ | |
775 | uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */ | |
776 | uint8_t iscsi_name[224]; /* 100-1DF */ | |
777 | uint8_t reserved13[32]; /* 1E0-1FF */ | |
778 | uint32_t cookie; /* 200-203 */ | |
779 | uint16_t ipv6_port; /* 204-205 */ | |
780 | uint16_t ipv6_opts; /* 206-207 */ | |
781 | uint16_t ipv6_addtl_opts; /* 208-209 */ | |
782 | uint16_t ipv6_tcp_opts; /* 20A-20B */ | |
783 | uint8_t ipv6_tcp_wsf; /* 20C */ | |
784 | uint16_t ipv6_flow_lbl; /* 20D-20F */ | |
785 | uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */ | |
786 | uint16_t ipv6_vlan_tag; /* 220-221 */ | |
787 | uint8_t ipv6_lnk_lcl_addr_state; /* 222 */ | |
788 | uint8_t ipv6_addr0_state; /* 223 */ | |
789 | uint8_t ipv6_addr1_state; /* 224 */ | |
790 | uint8_t ipv6_dflt_rtr_state; /* 225 */ | |
791 | uint8_t ipv6_traffic_class; /* 226 */ | |
792 | uint8_t ipv6_hop_limit; /* 227 */ | |
793 | uint8_t ipv6_if_id[8]; /* 228-22F */ | |
794 | uint8_t ipv6_addr0[16]; /* 230-23F */ | |
795 | uint8_t ipv6_addr1[16]; /* 240-24F */ | |
796 | uint32_t ipv6_nd_reach_time; /* 250-253 */ | |
797 | uint32_t ipv6_nd_rexmit_timer; /* 254-257 */ | |
798 | uint32_t ipv6_nd_stale_timeout; /* 258-25B */ | |
799 | uint8_t ipv6_dup_addr_detect_count; /* 25C */ | |
800 | uint8_t ipv6_cache_id; /* 25D */ | |
801 | uint8_t reserved14[18]; /* 25E-26F */ | |
802 | uint32_t ipv6_gw_advrt_mtu; /* 270-273 */ | |
803 | uint8_t reserved15[140]; /* 274-2FF */ | |
804 | }; | |
805 | ||
afaf5a2d DS |
806 | /*************************************************************************/ |
807 | ||
b3a271a9 MR |
808 | #define MAX_CHAP_ENTRIES_40XX 128 |
809 | #define MAX_CHAP_ENTRIES_82XX 1024 | |
4549415a LC |
810 | #define MAX_RESRV_CHAP_IDX 3 |
811 | #define FLASH_CHAP_OFFSET 0x06000000 | |
b3a271a9 MR |
812 | |
813 | struct ql4_chap_table { | |
814 | uint16_t link; | |
815 | uint8_t flags; | |
816 | uint8_t secret_len; | |
817 | #define MIN_CHAP_SECRET_LEN 12 | |
818 | #define MAX_CHAP_SECRET_LEN 100 | |
819 | uint8_t secret[MAX_CHAP_SECRET_LEN]; | |
820 | #define MAX_CHAP_NAME_LEN 256 | |
821 | uint8_t name[MAX_CHAP_NAME_LEN]; | |
822 | uint16_t reserved; | |
823 | #define CHAP_VALID_COOKIE 0x4092 | |
824 | #define CHAP_INVALID_COOKIE 0xFFEE | |
825 | uint16_t cookie; | |
826 | }; | |
827 | ||
afaf5a2d | 828 | struct dev_db_entry { |
b2854316 | 829 | uint16_t options; /* 00-01 */ |
afaf5a2d DS |
830 | #define DDB_OPT_DISC_SESSION 0x10 |
831 | #define DDB_OPT_TARGET 0x02 /* device is a target */ | |
2a49a78e | 832 | #define DDB_OPT_IPV6_DEVICE 0x100 |
b3a271a9 | 833 | #define DDB_OPT_AUTO_SENDTGTS_DISABLE 0x40 |
2a49a78e VC |
834 | #define DDB_OPT_IPV6_NULL_LINK_LOCAL 0x800 /* post connection */ |
835 | #define DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL 0x800 /* pre connection */ | |
afaf5a2d | 836 | |
1e9e2be3 AC |
837 | #define OPT_IS_FW_ASSIGNED_IPV6 11 |
838 | #define OPT_IPV6_DEVICE 8 | |
839 | #define OPT_AUTO_SENDTGTS_DISABLE 6 | |
840 | #define OPT_DISC_SESSION 4 | |
841 | #define OPT_ENTRY_STATE 3 | |
b2854316 DS |
842 | uint16_t exec_throttle; /* 02-03 */ |
843 | uint16_t exec_count; /* 04-05 */ | |
844 | uint16_t res0; /* 06-07 */ | |
845 | uint16_t iscsi_options; /* 08-09 */ | |
1e9e2be3 AC |
846 | #define ISCSIOPT_HEADER_DIGEST_EN 13 |
847 | #define ISCSIOPT_DATA_DIGEST_EN 12 | |
848 | #define ISCSIOPT_IMMEDIATE_DATA_EN 11 | |
849 | #define ISCSIOPT_INITIAL_R2T_EN 10 | |
850 | #define ISCSIOPT_DATA_SEQ_IN_ORDER 9 | |
851 | #define ISCSIOPT_DATA_PDU_IN_ORDER 8 | |
852 | #define ISCSIOPT_CHAP_AUTH_EN 7 | |
853 | #define ISCSIOPT_SNACK_REQ_EN 6 | |
854 | #define ISCSIOPT_DISCOVERY_LOGOUT_EN 5 | |
855 | #define ISCSIOPT_BIDI_CHAP_EN 4 | |
856 | #define ISCSIOPT_DISCOVERY_AUTH_OPTIONAL 3 | |
857 | #define ISCSIOPT_ERL1 1 | |
858 | #define ISCSIOPT_ERL0 0 | |
859 | ||
b2854316 | 860 | uint16_t tcp_options; /* 0A-0B */ |
1e9e2be3 AC |
861 | #define TCPOPT_TIMESTAMP_STAT 6 |
862 | #define TCPOPT_NAGLE_DISABLE 5 | |
863 | #define TCPOPT_WSF_DISABLE 4 | |
864 | #define TCPOPT_TIMER_SCALE3 3 | |
865 | #define TCPOPT_TIMER_SCALE2 2 | |
866 | #define TCPOPT_TIMER_SCALE1 1 | |
867 | #define TCPOPT_TIMESTAMP_EN 0 | |
868 | ||
b2854316 | 869 | uint16_t ip_options; /* 0C-0D */ |
1e9e2be3 AC |
870 | #define IPOPT_FRAGMENT_DISABLE 4 |
871 | ||
b2854316 | 872 | uint16_t iscsi_max_rcv_data_seg_len; /* 0E-0F */ |
b3a271a9 | 873 | #define BYTE_UNITS 512 |
b2854316 DS |
874 | uint32_t res1; /* 10-13 */ |
875 | uint16_t iscsi_max_snd_data_seg_len; /* 14-15 */ | |
876 | uint16_t iscsi_first_burst_len; /* 16-17 */ | |
877 | uint16_t iscsi_def_time2wait; /* 18-19 */ | |
878 | uint16_t iscsi_def_time2retain; /* 1A-1B */ | |
879 | uint16_t iscsi_max_outsnd_r2t; /* 1C-1D */ | |
880 | uint16_t ka_timeout; /* 1E-1F */ | |
881 | uint8_t isid[6]; /* 20-25 big-endian, must be converted | |
afaf5a2d | 882 | * to little-endian */ |
b2854316 DS |
883 | uint16_t tsid; /* 26-27 */ |
884 | uint16_t port; /* 28-29 */ | |
885 | uint16_t iscsi_max_burst_len; /* 2A-2B */ | |
886 | uint16_t def_timeout; /* 2C-2D */ | |
887 | uint16_t res2; /* 2E-2F */ | |
888 | uint8_t ip_addr[0x10]; /* 30-3F */ | |
889 | uint8_t iscsi_alias[0x20]; /* 40-5F */ | |
890 | uint8_t tgt_addr[0x20]; /* 60-7F */ | |
891 | uint16_t mss; /* 80-81 */ | |
892 | uint16_t res3; /* 82-83 */ | |
893 | uint16_t lcl_port; /* 84-85 */ | |
894 | uint8_t ipv4_tos; /* 86 */ | |
895 | uint16_t ipv6_flow_lbl; /* 87-89 */ | |
896 | uint8_t res4[0x36]; /* 8A-BF */ | |
897 | uint8_t iscsi_name[0xE0]; /* C0-19F : xxzzy Make this a | |
afaf5a2d | 898 | * pointer to a string so we |
42b2aa86 | 899 | * don't have to reserve so |
afaf5a2d | 900 | * much RAM */ |
2a49a78e | 901 | uint8_t link_local_ipv6_addr[0x10]; /* 1A0-1AF */ |
b2854316 | 902 | uint8_t res5[0x10]; /* 1B0-1BF */ |
1e9e2be3 AC |
903 | #define DDB_NO_LINK 0xFFFF |
904 | #define DDB_ISNS 0xFFFD | |
b2854316 DS |
905 | uint16_t ddb_link; /* 1C0-1C1 */ |
906 | uint16_t chap_tbl_idx; /* 1C2-1C3 */ | |
907 | uint16_t tgt_portal_grp; /* 1C4-1C5 */ | |
908 | uint8_t tcp_xmt_wsf; /* 1C6 */ | |
909 | uint8_t tcp_rcv_wsf; /* 1C7 */ | |
910 | uint32_t stat_sn; /* 1C8-1CB */ | |
911 | uint32_t exp_stat_sn; /* 1CC-1CF */ | |
2a991c21 MR |
912 | uint8_t res6[0x2b]; /* 1D0-1FB */ |
913 | #define DDB_VALID_COOKIE 0x9034 | |
914 | uint16_t cookie; /* 1FC-1FD */ | |
915 | uint16_t len; /* 1FE-1FF */ | |
afaf5a2d DS |
916 | }; |
917 | ||
918 | /*************************************************************************/ | |
919 | ||
920 | /* Flash definitions */ | |
921 | ||
922 | #define FLASH_OFFSET_SYS_INFO 0x02000000 | |
923 | #define FLASH_DEFAULTBLOCKSIZE 0x20000 | |
924 | #define FLASH_EOF_OFFSET (FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes | |
925 | * for EOF | |
926 | * signature */ | |
2a991c21 MR |
927 | #define FLASH_RAW_ACCESS_ADDR 0x8e000000 |
928 | ||
929 | #define BOOT_PARAM_OFFSET_PORT0 0x3b0 | |
930 | #define BOOT_PARAM_OFFSET_PORT1 0x7b0 | |
931 | ||
932 | #define FLASH_OFFSET_DB_INFO 0x05000000 | |
933 | #define FLASH_OFFSET_DB_END (FLASH_OFFSET_DB_INFO + 0x7fff) | |
934 | ||
afaf5a2d DS |
935 | |
936 | struct sys_info_phys_addr { | |
937 | uint8_t address[6]; /* 00-05 */ | |
938 | uint8_t filler[2]; /* 06-07 */ | |
939 | }; | |
940 | ||
941 | struct flash_sys_info { | |
942 | uint32_t cookie; /* 00-03 */ | |
943 | uint32_t physAddrCount; /* 04-07 */ | |
944 | struct sys_info_phys_addr physAddr[4]; /* 08-27 */ | |
945 | uint8_t vendorId[128]; /* 28-A7 */ | |
946 | uint8_t productId[128]; /* A8-127 */ | |
947 | uint32_t serialNumber; /* 128-12B */ | |
948 | ||
949 | /* PCI Configuration values */ | |
950 | uint32_t pciDeviceVendor; /* 12C-12F */ | |
951 | uint32_t pciDeviceId; /* 130-133 */ | |
952 | uint32_t pciSubsysVendor; /* 134-137 */ | |
953 | uint32_t pciSubsysId; /* 138-13B */ | |
954 | ||
955 | /* This validates version 1. */ | |
956 | uint32_t crumbs; /* 13C-13F */ | |
957 | ||
958 | uint32_t enterpriseNumber; /* 140-143 */ | |
959 | ||
960 | uint32_t mtu; /* 144-147 */ | |
961 | uint32_t reserved0; /* 148-14b */ | |
962 | uint32_t crumbs2; /* 14c-14f */ | |
963 | uint8_t acSerialNumber[16]; /* 150-15f */ | |
964 | uint32_t crumbs3; /* 160-16f */ | |
965 | ||
966 | /* Leave this last in the struct so it is declared invalid if | |
967 | * any new items are added. | |
968 | */ | |
969 | uint32_t reserved1[39]; /* 170-1ff */ | |
970 | }; /* 200 */ | |
971 | ||
f4f5df23 | 972 | struct mbx_sys_info { |
2ccdf0dc VC |
973 | uint8_t board_id_str[16]; /* 0-f Keep board ID string first */ |
974 | /* in this structure for GUI. */ | |
975 | uint16_t board_id; /* 10-11 board ID code */ | |
976 | uint16_t phys_port_cnt; /* 12-13 number of physical network ports */ | |
977 | uint16_t port_num; /* 14-15 network port for this PCI function */ | |
f4f5df23 | 978 | /* (port 0 is first port) */ |
2ccdf0dc VC |
979 | uint8_t mac_addr[6]; /* 16-1b MAC address for this PCI function */ |
980 | uint32_t iscsi_pci_func_cnt; /* 1c-1f number of iSCSI PCI functions */ | |
981 | uint32_t pci_func; /* 20-23 this PCI function */ | |
982 | unsigned char serial_number[16]; /* 24-33 serial number string */ | |
983 | uint8_t reserved[12]; /* 34-3f */ | |
f4f5df23 VC |
984 | }; |
985 | ||
7ad633c0 HZ |
986 | struct about_fw_info { |
987 | uint16_t fw_major; /* 00 - 01 */ | |
988 | uint16_t fw_minor; /* 02 - 03 */ | |
989 | uint16_t fw_patch; /* 04 - 05 */ | |
990 | uint16_t fw_build; /* 06 - 07 */ | |
991 | uint8_t fw_build_date[16]; /* 08 - 17 ASCII String */ | |
992 | uint8_t fw_build_time[16]; /* 18 - 27 ASCII String */ | |
993 | uint8_t fw_build_user[16]; /* 28 - 37 ASCII String */ | |
994 | uint16_t fw_load_source; /* 38 - 39 */ | |
995 | /* 1 = Flash Primary, | |
996 | 2 = Flash Secondary, | |
997 | 3 = Host Download | |
998 | */ | |
999 | uint8_t reserved1[6]; /* 3A - 3F */ | |
1000 | uint16_t iscsi_major; /* 40 - 41 */ | |
1001 | uint16_t iscsi_minor; /* 42 - 43 */ | |
1002 | uint16_t bootload_major; /* 44 - 45 */ | |
1003 | uint16_t bootload_minor; /* 46 - 47 */ | |
1004 | uint16_t bootload_patch; /* 48 - 49 */ | |
1005 | uint16_t bootload_build; /* 4A - 4B */ | |
eee06a0f | 1006 | uint8_t extended_timestamp[180];/* 4C - FF */ |
7ad633c0 HZ |
1007 | }; |
1008 | ||
afaf5a2d DS |
1009 | struct crash_record { |
1010 | uint16_t fw_major_version; /* 00 - 01 */ | |
1011 | uint16_t fw_minor_version; /* 02 - 03 */ | |
1012 | uint16_t fw_patch_version; /* 04 - 05 */ | |
1013 | uint16_t fw_build_version; /* 06 - 07 */ | |
1014 | ||
1015 | uint8_t build_date[16]; /* 08 - 17 */ | |
1016 | uint8_t build_time[16]; /* 18 - 27 */ | |
1017 | uint8_t build_user[16]; /* 28 - 37 */ | |
1018 | uint8_t card_serial_num[16]; /* 38 - 47 */ | |
1019 | ||
1020 | uint32_t time_of_crash_in_secs; /* 48 - 4B */ | |
1021 | uint32_t time_of_crash_in_ms; /* 4C - 4F */ | |
1022 | ||
1023 | uint16_t out_RISC_sd_num_frames; /* 50 - 51 */ | |
1024 | uint16_t OAP_sd_num_words; /* 52 - 53 */ | |
1025 | uint16_t IAP_sd_num_frames; /* 54 - 55 */ | |
1026 | uint16_t in_RISC_sd_num_words; /* 56 - 57 */ | |
1027 | ||
1028 | uint8_t reserved1[28]; /* 58 - 7F */ | |
1029 | ||
1030 | uint8_t out_RISC_reg_dump[256]; /* 80 -17F */ | |
1031 | uint8_t in_RISC_reg_dump[256]; /*180 -27F */ | |
1032 | uint8_t in_out_RISC_stack_dump[0]; /*280 - ??? */ | |
1033 | }; | |
1034 | ||
1035 | struct conn_event_log_entry { | |
1036 | #define MAX_CONN_EVENT_LOG_ENTRIES 100 | |
1037 | uint32_t timestamp_sec; /* 00 - 03 seconds since boot */ | |
1038 | uint32_t timestamp_ms; /* 04 - 07 milliseconds since boot */ | |
1039 | uint16_t device_index; /* 08 - 09 */ | |
1040 | uint16_t fw_conn_state; /* 0A - 0B */ | |
1041 | uint8_t event_type; /* 0C - 0C */ | |
1042 | uint8_t error_code; /* 0D - 0D */ | |
1043 | uint16_t error_code_detail; /* 0E - 0F */ | |
1044 | uint8_t num_consecutive_events; /* 10 - 10 */ | |
1045 | uint8_t rsvd[3]; /* 11 - 13 */ | |
1046 | }; | |
1047 | ||
1048 | /************************************************************************* | |
1049 | * | |
1050 | * IOCB Commands Structures and Definitions | |
1051 | * | |
1052 | *************************************************************************/ | |
1053 | #define IOCB_MAX_CDB_LEN 16 /* Bytes in a CBD */ | |
1054 | #define IOCB_MAX_SENSEDATA_LEN 32 /* Bytes of sense data */ | |
94bced3c | 1055 | #define IOCB_MAX_EXT_SENSEDATA_LEN 60 /* Bytes of extended sense data */ |
afaf5a2d DS |
1056 | |
1057 | /* IOCB header structure */ | |
1058 | struct qla4_header { | |
1059 | uint8_t entryType; | |
1060 | #define ET_STATUS 0x03 | |
1061 | #define ET_MARKER 0x04 | |
1062 | #define ET_CONT_T1 0x0A | |
1063 | #define ET_STATUS_CONTINUATION 0x10 | |
1064 | #define ET_CMND_T3 0x19 | |
1065 | #define ET_PASSTHRU0 0x3A | |
1066 | #define ET_PASSTHRU_STATUS 0x3C | |
c0b9d3f7 VC |
1067 | #define ET_MBOX_CMD 0x38 |
1068 | #define ET_MBOX_STATUS 0x39 | |
afaf5a2d DS |
1069 | |
1070 | uint8_t entryStatus; | |
1071 | uint8_t systemDefined; | |
b3a271a9 | 1072 | #define SD_ISCSI_PDU 0x01 |
afaf5a2d DS |
1073 | uint8_t entryCount; |
1074 | ||
1075 | /* SyetemDefined definition */ | |
1076 | }; | |
1077 | ||
1078 | /* Generic queue entry structure*/ | |
1079 | struct queue_entry { | |
1080 | uint8_t data[60]; | |
1081 | uint32_t signature; | |
1082 | ||
1083 | }; | |
1084 | ||
1085 | /* 64 bit addressing segment counts*/ | |
1086 | ||
1087 | #define COMMAND_SEG_A64 1 | |
1088 | #define CONTINUE_SEG_A64 5 | |
1089 | ||
1090 | /* 64 bit addressing segment definition*/ | |
1091 | ||
1092 | struct data_seg_a64 { | |
1093 | struct { | |
1094 | uint32_t addrLow; | |
1095 | uint32_t addrHigh; | |
1096 | ||
1097 | } base; | |
1098 | ||
1099 | uint32_t count; | |
1100 | ||
1101 | }; | |
1102 | ||
1103 | /* Command Type 3 entry structure*/ | |
1104 | ||
1105 | struct command_t3_entry { | |
1106 | struct qla4_header hdr; /* 00-03 */ | |
1107 | ||
1108 | uint32_t handle; /* 04-07 */ | |
1109 | uint16_t target; /* 08-09 */ | |
1110 | uint16_t connection_id; /* 0A-0B */ | |
1111 | ||
1112 | uint8_t control_flags; /* 0C */ | |
1113 | ||
1114 | /* data direction (bits 5-6) */ | |
1115 | #define CF_WRITE 0x20 | |
1116 | #define CF_READ 0x40 | |
1117 | #define CF_NO_DATA 0x00 | |
1118 | ||
1119 | /* task attributes (bits 2-0) */ | |
1120 | #define CF_HEAD_TAG 0x03 | |
1121 | #define CF_ORDERED_TAG 0x02 | |
1122 | #define CF_SIMPLE_TAG 0x01 | |
1123 | ||
1124 | /* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS | |
1125 | * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS | |
1126 | * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET | |
1127 | * PROPERLY. | |
1128 | */ | |
1129 | uint8_t state_flags; /* 0D */ | |
1130 | uint8_t cmdRefNum; /* 0E */ | |
1131 | uint8_t reserved1; /* 0F */ | |
1132 | uint8_t cdb[IOCB_MAX_CDB_LEN]; /* 10-1F */ | |
1133 | struct scsi_lun lun; /* FCP LUN (BE). */ | |
1134 | uint32_t cmdSeqNum; /* 28-2B */ | |
1135 | uint16_t timeout; /* 2C-2D */ | |
1136 | uint16_t dataSegCnt; /* 2E-2F */ | |
1137 | uint32_t ttlByteCnt; /* 30-33 */ | |
1138 | struct data_seg_a64 dataseg[COMMAND_SEG_A64]; /* 34-3F */ | |
1139 | ||
1140 | }; | |
1141 | ||
1142 | ||
1143 | /* Continuation Type 1 entry structure*/ | |
1144 | struct continuation_t1_entry { | |
1145 | struct qla4_header hdr; | |
1146 | ||
1147 | struct data_seg_a64 dataseg[CONTINUE_SEG_A64]; | |
1148 | ||
1149 | }; | |
1150 | ||
1151 | /* Parameterize for 64 or 32 bits */ | |
1152 | #define COMMAND_SEG COMMAND_SEG_A64 | |
1153 | #define CONTINUE_SEG CONTINUE_SEG_A64 | |
1154 | ||
1155 | #define ET_COMMAND ET_CMND_T3 | |
1156 | #define ET_CONTINUE ET_CONT_T1 | |
1157 | ||
1158 | /* Marker entry structure*/ | |
1c3f0b8e | 1159 | struct qla4_marker_entry { |
afaf5a2d DS |
1160 | struct qla4_header hdr; /* 00-03 */ |
1161 | ||
1162 | uint32_t system_defined; /* 04-07 */ | |
1163 | uint16_t target; /* 08-09 */ | |
1164 | uint16_t modifier; /* 0A-0B */ | |
9d562913 DS |
1165 | #define MM_LUN_RESET 0 |
1166 | #define MM_TGT_WARM_RESET 1 | |
afaf5a2d DS |
1167 | |
1168 | uint16_t flags; /* 0C-0D */ | |
1169 | uint16_t reserved1; /* 0E-0F */ | |
1170 | struct scsi_lun lun; /* FCP LUN (BE). */ | |
1171 | uint64_t reserved2; /* 18-1F */ | |
1172 | uint64_t reserved3; /* 20-27 */ | |
1173 | uint64_t reserved4; /* 28-2F */ | |
1174 | uint64_t reserved5; /* 30-37 */ | |
1175 | uint64_t reserved6; /* 38-3F */ | |
1176 | }; | |
1177 | ||
1178 | /* Status entry structure*/ | |
1179 | struct status_entry { | |
1180 | struct qla4_header hdr; /* 00-03 */ | |
1181 | ||
1182 | uint32_t handle; /* 04-07 */ | |
1183 | ||
1184 | uint8_t scsiStatus; /* 08 */ | |
1185 | #define SCSI_CHECK_CONDITION 0x02 | |
1186 | ||
1187 | uint8_t iscsiFlags; /* 09 */ | |
1188 | #define ISCSI_FLAG_RESIDUAL_UNDER 0x02 | |
1189 | #define ISCSI_FLAG_RESIDUAL_OVER 0x04 | |
1190 | ||
1191 | uint8_t iscsiResponse; /* 0A */ | |
1192 | ||
1193 | uint8_t completionStatus; /* 0B */ | |
1194 | #define SCS_COMPLETE 0x00 | |
1195 | #define SCS_INCOMPLETE 0x01 | |
1196 | #define SCS_RESET_OCCURRED 0x04 | |
1197 | #define SCS_ABORTED 0x05 | |
1198 | #define SCS_TIMEOUT 0x06 | |
1199 | #define SCS_DATA_OVERRUN 0x07 | |
1200 | #define SCS_DATA_UNDERRUN 0x15 | |
1201 | #define SCS_QUEUE_FULL 0x1C | |
1202 | #define SCS_DEVICE_UNAVAILABLE 0x28 | |
1203 | #define SCS_DEVICE_LOGGED_OUT 0x29 | |
1204 | ||
1205 | uint8_t reserved1; /* 0C */ | |
1206 | ||
1207 | /* state_flags MUST be at the same location as state_flags in | |
1208 | * the Command_T3/4_Entry */ | |
1209 | uint8_t state_flags; /* 0D */ | |
1210 | ||
1211 | uint16_t senseDataByteCnt; /* 0E-0F */ | |
1212 | uint32_t residualByteCnt; /* 10-13 */ | |
1213 | uint32_t bidiResidualByteCnt; /* 14-17 */ | |
1214 | uint32_t expSeqNum; /* 18-1B */ | |
1215 | uint32_t maxCmdSeqNum; /* 1C-1F */ | |
1216 | uint8_t senseData[IOCB_MAX_SENSEDATA_LEN]; /* 20-3F */ | |
1217 | ||
1218 | }; | |
1219 | ||
94bced3c KH |
1220 | /* Status Continuation entry */ |
1221 | struct status_cont_entry { | |
1222 | struct qla4_header hdr; /* 00-03 */ | |
1223 | uint8_t ext_sense_data[IOCB_MAX_EXT_SENSEDATA_LEN]; /* 04-63 */ | |
1224 | }; | |
1225 | ||
afaf5a2d DS |
1226 | struct passthru0 { |
1227 | struct qla4_header hdr; /* 00-03 */ | |
1228 | uint32_t handle; /* 04-07 */ | |
1229 | uint16_t target; /* 08-09 */ | |
b3a271a9 | 1230 | uint16_t connection_id; /* 0A-0B */ |
afaf5a2d DS |
1231 | #define ISNS_DEFAULT_SERVER_CONN_ID ((uint16_t)0x8000) |
1232 | ||
b3a271a9 | 1233 | uint16_t control_flags; /* 0C-0D */ |
afaf5a2d DS |
1234 | #define PT_FLAG_ETHERNET_FRAME 0x8000 |
1235 | #define PT_FLAG_ISNS_PDU 0x8000 | |
1236 | #define PT_FLAG_SEND_BUFFER 0x0200 | |
1237 | #define PT_FLAG_WAIT_4_RESPONSE 0x0100 | |
b3a271a9 | 1238 | #define PT_FLAG_ISCSI_PDU 0x1000 |
afaf5a2d DS |
1239 | |
1240 | uint16_t timeout; /* 0E-0F */ | |
1241 | #define PT_DEFAULT_TIMEOUT 30 /* seconds */ | |
1242 | ||
b3a271a9 | 1243 | struct data_seg_a64 out_dsd; /* 10-1B */ |
afaf5a2d | 1244 | uint32_t res1; /* 1C-1F */ |
b3a271a9 | 1245 | struct data_seg_a64 in_dsd; /* 20-2B */ |
afaf5a2d DS |
1246 | uint8_t res2[20]; /* 2C-3F */ |
1247 | }; | |
1248 | ||
1249 | struct passthru_status { | |
1250 | struct qla4_header hdr; /* 00-03 */ | |
1251 | uint32_t handle; /* 04-07 */ | |
1252 | uint16_t target; /* 08-09 */ | |
1253 | uint16_t connectionID; /* 0A-0B */ | |
1254 | ||
1255 | uint8_t completionStatus; /* 0C */ | |
1256 | #define PASSTHRU_STATUS_COMPLETE 0x01 | |
1257 | ||
1258 | uint8_t residualFlags; /* 0D */ | |
1259 | ||
1260 | uint16_t timeout; /* 0E-0F */ | |
1261 | uint16_t portNumber; /* 10-11 */ | |
1262 | uint8_t res1[10]; /* 12-1B */ | |
1263 | uint32_t outResidual; /* 1C-1F */ | |
1264 | uint8_t res2[12]; /* 20-2B */ | |
1265 | uint32_t inResidual; /* 2C-2F */ | |
1266 | uint8_t res4[16]; /* 30-3F */ | |
1267 | }; | |
1268 | ||
c0b9d3f7 VC |
1269 | struct mbox_cmd_iocb { |
1270 | struct qla4_header hdr; /* 00-03 */ | |
1271 | uint32_t handle; /* 04-07 */ | |
1272 | uint32_t in_mbox[8]; /* 08-25 */ | |
1273 | uint32_t res1[6]; /* 26-3F */ | |
1274 | }; | |
1275 | ||
1276 | struct mbox_status_iocb { | |
1277 | struct qla4_header hdr; /* 00-03 */ | |
1278 | uint32_t handle; /* 04-07 */ | |
1279 | uint32_t out_mbox[8]; /* 08-25 */ | |
1280 | uint32_t res1[6]; /* 26-3F */ | |
1281 | }; | |
1282 | ||
f4f5df23 VC |
1283 | /* |
1284 | * ISP queue - response queue entry definition. | |
1285 | */ | |
1286 | struct response { | |
1287 | uint8_t data[60]; | |
1288 | uint32_t signature; | |
1289 | #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ | |
1290 | }; | |
1291 | ||
b3a271a9 | 1292 | struct ql_iscsi_stats { |
4161cee5 LC |
1293 | uint64_t mac_tx_frames; /* 0000–0007 */ |
1294 | uint64_t mac_tx_bytes; /* 0008–000F */ | |
1295 | uint64_t mac_tx_multicast_frames; /* 0010–0017 */ | |
1296 | uint64_t mac_tx_broadcast_frames; /* 0018–001F */ | |
1297 | uint64_t mac_tx_pause_frames; /* 0020–0027 */ | |
1298 | uint64_t mac_tx_control_frames; /* 0028–002F */ | |
1299 | uint64_t mac_tx_deferral; /* 0030–0037 */ | |
1300 | uint64_t mac_tx_excess_deferral; /* 0038–003F */ | |
1301 | uint64_t mac_tx_late_collision; /* 0040–0047 */ | |
1302 | uint64_t mac_tx_abort; /* 0048–004F */ | |
1303 | uint64_t mac_tx_single_collision; /* 0050–0057 */ | |
1304 | uint64_t mac_tx_multiple_collision; /* 0058–005F */ | |
1305 | uint64_t mac_tx_collision; /* 0060–0067 */ | |
1306 | uint64_t mac_tx_frames_dropped; /* 0068–006F */ | |
1307 | uint64_t mac_tx_jumbo_frames; /* 0070–0077 */ | |
1308 | uint64_t mac_rx_frames; /* 0078–007F */ | |
1309 | uint64_t mac_rx_bytes; /* 0080–0087 */ | |
1310 | uint64_t mac_rx_unknown_control_frames; /* 0088–008F */ | |
1311 | uint64_t mac_rx_pause_frames; /* 0090–0097 */ | |
1312 | uint64_t mac_rx_control_frames; /* 0098–009F */ | |
1313 | uint64_t mac_rx_dribble; /* 00A0–00A7 */ | |
1314 | uint64_t mac_rx_frame_length_error; /* 00A8–00AF */ | |
1315 | uint64_t mac_rx_jabber; /* 00B0–00B7 */ | |
1316 | uint64_t mac_rx_carrier_sense_error; /* 00B8–00BF */ | |
1317 | uint64_t mac_rx_frame_discarded; /* 00C0–00C7 */ | |
1318 | uint64_t mac_rx_frames_dropped; /* 00C8–00CF */ | |
1319 | uint64_t mac_crc_error; /* 00D0–00D7 */ | |
1320 | uint64_t mac_encoding_error; /* 00D8–00DF */ | |
1321 | uint64_t mac_rx_length_error_large; /* 00E0–00E7 */ | |
1322 | uint64_t mac_rx_length_error_small; /* 00E8–00EF */ | |
1323 | uint64_t mac_rx_multicast_frames; /* 00F0–00F7 */ | |
1324 | uint64_t mac_rx_broadcast_frames; /* 00F8–00FF */ | |
1325 | uint64_t ip_tx_packets; /* 0100–0107 */ | |
1326 | uint64_t ip_tx_bytes; /* 0108–010F */ | |
1327 | uint64_t ip_tx_fragments; /* 0110–0117 */ | |
1328 | uint64_t ip_rx_packets; /* 0118–011F */ | |
1329 | uint64_t ip_rx_bytes; /* 0120–0127 */ | |
1330 | uint64_t ip_rx_fragments; /* 0128–012F */ | |
1331 | uint64_t ip_datagram_reassembly; /* 0130–0137 */ | |
1332 | uint64_t ip_invalid_address_error; /* 0138–013F */ | |
1333 | uint64_t ip_error_packets; /* 0140–0147 */ | |
1334 | uint64_t ip_fragrx_overlap; /* 0148–014F */ | |
1335 | uint64_t ip_fragrx_outoforder; /* 0150–0157 */ | |
1336 | uint64_t ip_datagram_reassembly_timeout; /* 0158–015F */ | |
1337 | uint64_t ipv6_tx_packets; /* 0160–0167 */ | |
1338 | uint64_t ipv6_tx_bytes; /* 0168–016F */ | |
1339 | uint64_t ipv6_tx_fragments; /* 0170–0177 */ | |
1340 | uint64_t ipv6_rx_packets; /* 0178–017F */ | |
1341 | uint64_t ipv6_rx_bytes; /* 0180–0187 */ | |
1342 | uint64_t ipv6_rx_fragments; /* 0188–018F */ | |
1343 | uint64_t ipv6_datagram_reassembly; /* 0190–0197 */ | |
1344 | uint64_t ipv6_invalid_address_error; /* 0198–019F */ | |
1345 | uint64_t ipv6_error_packets; /* 01A0–01A7 */ | |
1346 | uint64_t ipv6_fragrx_overlap; /* 01A8–01AF */ | |
1347 | uint64_t ipv6_fragrx_outoforder; /* 01B0–01B7 */ | |
1348 | uint64_t ipv6_datagram_reassembly_timeout; /* 01B8–01BF */ | |
1349 | uint64_t tcp_tx_segments; /* 01C0–01C7 */ | |
1350 | uint64_t tcp_tx_bytes; /* 01C8–01CF */ | |
1351 | uint64_t tcp_rx_segments; /* 01D0–01D7 */ | |
1352 | uint64_t tcp_rx_byte; /* 01D8–01DF */ | |
1353 | uint64_t tcp_duplicate_ack_retx; /* 01E0–01E7 */ | |
1354 | uint64_t tcp_retx_timer_expired; /* 01E8–01EF */ | |
1355 | uint64_t tcp_rx_duplicate_ack; /* 01F0–01F7 */ | |
1356 | uint64_t tcp_rx_pure_ackr; /* 01F8–01FF */ | |
1357 | uint64_t tcp_tx_delayed_ack; /* 0200–0207 */ | |
1358 | uint64_t tcp_tx_pure_ack; /* 0208–020F */ | |
1359 | uint64_t tcp_rx_segment_error; /* 0210–0217 */ | |
1360 | uint64_t tcp_rx_segment_outoforder; /* 0218–021F */ | |
1361 | uint64_t tcp_rx_window_probe; /* 0220–0227 */ | |
1362 | uint64_t tcp_rx_window_update; /* 0228–022F */ | |
1363 | uint64_t tcp_tx_window_probe_persist; /* 0230–0237 */ | |
1364 | uint64_t ecc_error_correction; /* 0238–023F */ | |
1365 | uint64_t iscsi_pdu_tx; /* 0240-0247 */ | |
1366 | uint64_t iscsi_data_bytes_tx; /* 0248-024F */ | |
1367 | uint64_t iscsi_pdu_rx; /* 0250-0257 */ | |
1368 | uint64_t iscsi_data_bytes_rx; /* 0258-025F */ | |
1369 | uint64_t iscsi_io_completed; /* 0260-0267 */ | |
1370 | uint64_t iscsi_unexpected_io_rx; /* 0268-026F */ | |
1371 | uint64_t iscsi_format_error; /* 0270-0277 */ | |
1372 | uint64_t iscsi_hdr_digest_error; /* 0278-027F */ | |
1373 | uint64_t iscsi_data_digest_error; /* 0280-0287 */ | |
1374 | uint64_t iscsi_sequence_error; /* 0288-028F */ | |
b3a271a9 MR |
1375 | uint32_t tx_cmd_pdu; /* 0290-0293 */ |
1376 | uint32_t tx_resp_pdu; /* 0294-0297 */ | |
1377 | uint32_t rx_cmd_pdu; /* 0298-029B */ | |
1378 | uint32_t rx_resp_pdu; /* 029C-029F */ | |
1379 | ||
1380 | uint64_t tx_data_octets; /* 02A0-02A7 */ | |
1381 | uint64_t rx_data_octets; /* 02A8-02AF */ | |
1382 | ||
1383 | uint32_t hdr_digest_err; /* 02B0–02B3 */ | |
1384 | uint32_t data_digest_err; /* 02B4–02B7 */ | |
1385 | uint32_t conn_timeout_err; /* 02B8–02BB */ | |
1386 | uint32_t framing_err; /* 02BC–02BF */ | |
1387 | ||
1388 | uint32_t tx_nopout_pdus; /* 02C0–02C3 */ | |
1389 | uint32_t tx_scsi_cmd_pdus; /* 02C4–02C7 */ | |
1390 | uint32_t tx_tmf_cmd_pdus; /* 02C8–02CB */ | |
1391 | uint32_t tx_login_cmd_pdus; /* 02CC–02CF */ | |
1392 | uint32_t tx_text_cmd_pdus; /* 02D0–02D3 */ | |
1393 | uint32_t tx_scsi_write_pdus; /* 02D4–02D7 */ | |
1394 | uint32_t tx_logout_cmd_pdus; /* 02D8–02DB */ | |
1395 | uint32_t tx_snack_req_pdus; /* 02DC–02DF */ | |
1396 | ||
1397 | uint32_t rx_nopin_pdus; /* 02E0–02E3 */ | |
1398 | uint32_t rx_scsi_resp_pdus; /* 02E4–02E7 */ | |
1399 | uint32_t rx_tmf_resp_pdus; /* 02E8–02EB */ | |
1400 | uint32_t rx_login_resp_pdus; /* 02EC–02EF */ | |
1401 | uint32_t rx_text_resp_pdus; /* 02F0–02F3 */ | |
1402 | uint32_t rx_scsi_read_pdus; /* 02F4–02F7 */ | |
1403 | uint32_t rx_logout_resp_pdus; /* 02F8–02FB */ | |
1404 | ||
1405 | uint32_t rx_r2t_pdus; /* 02FC–02FF */ | |
1406 | uint32_t rx_async_pdus; /* 0300–0303 */ | |
1407 | uint32_t rx_reject_pdus; /* 0304–0307 */ | |
1408 | ||
1409 | uint8_t reserved2[264]; /* 0x0308 - 0x040F */ | |
1410 | }; | |
1411 | ||
de8c72da VC |
1412 | #define QLA8XXX_DBG_STATE_ARRAY_LEN 16 |
1413 | #define QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN 8 | |
1414 | #define QLA8XXX_DBG_RSVD_ARRAY_LEN 8 | |
6e7b4292 VC |
1415 | #define QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN 16 |
1416 | #define QLA83XX_SS_OCM_WNDREG_INDEX 3 | |
1417 | #define QLA83XX_SS_PCI_INDEX 0 | |
b410982c TP |
1418 | #define QLA8022_TEMPLATE_CAP_OFFSET 172 |
1419 | #define QLA83XX_TEMPLATE_CAP_OFFSET 268 | |
1420 | #define QLA80XX_TEMPLATE_RESERVED_BITS 16 | |
068237c8 TP |
1421 | |
1422 | struct qla4_8xxx_minidump_template_hdr { | |
1423 | uint32_t entry_type; | |
1424 | uint32_t first_entry_offset; | |
1425 | uint32_t size_of_template; | |
1426 | uint32_t capture_debug_level; | |
1427 | uint32_t num_of_entries; | |
1428 | uint32_t version; | |
1429 | uint32_t driver_timestamp; | |
1430 | uint32_t checksum; | |
1431 | ||
1432 | uint32_t driver_capture_mask; | |
1433 | uint32_t driver_info_word2; | |
1434 | uint32_t driver_info_word3; | |
1435 | uint32_t driver_info_word4; | |
1436 | ||
de8c72da VC |
1437 | uint32_t saved_state_array[QLA8XXX_DBG_STATE_ARRAY_LEN]; |
1438 | uint32_t capture_size_array[QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN]; | |
6e7b4292 | 1439 | uint32_t ocm_window_reg[QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN]; |
b410982c | 1440 | uint32_t capabilities[QLA80XX_TEMPLATE_RESERVED_BITS]; |
068237c8 TP |
1441 | }; |
1442 | ||
afaf5a2d | 1443 | #endif /* _QLA4X_FW_H */ |