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[SCSI] qla4xxx: Added support for adapter and firmware reset
[linux-2.6-block.git] / drivers / scsi / qla4xxx / ql4_def.h
CommitLineData
afaf5a2d
DS		 1/*
2 * QLogic iSCSI HBA Driver
7d01d069 3 * Copyright (c) 2003-2010 QLogic Corporation
afaf5a2d
DS		 4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8#ifndef __QL4_DEF_H
9#define __QL4_DEF_H
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/types.h>
14#include <linux/module.h>
15#include <linux/list.h>
16#include <linux/pci.h>
17#include <linux/dma-mapping.h>
18#include <linux/sched.h>
19#include <linux/slab.h>
20#include <linux/dmapool.h>
21#include <linux/mempool.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/mutex.h>
7b3595df 27#include <linux/aer.h>
a355943c 28#include <linux/bsg-lib.h>
afaf5a2d
DS		 29
30#include <net/tcp.h>
31#include <scsi/scsi.h>
32#include <scsi/scsi_host.h>
33#include <scsi/scsi_device.h>
34#include <scsi/scsi_cmnd.h>
35#include <scsi/scsi_transport.h>
36#include <scsi/scsi_transport_iscsi.h>
a355943c
VC		 37#include <scsi/scsi_bsg_iscsi.h>
38#include <scsi/scsi_netlink.h>
b3a271a9 39#include <scsi/libiscsi.h>
afaf5a2d 40
f4f5df23
VC		 41#include "ql4_dbg.h"
42#include "ql4_nx.h"
b3a271a9
MR		 43#include "ql4_fw.h"
44#include "ql4_nvram.h"
afaf5a2d
DS		 45
46#ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
47#define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
48#endif
49
50#ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
51#define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
d915058f
DS		 52#endif
53
54#ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
55#define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
56#endif
afaf5a2d 57
f4f5df23
VC		 58#ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
59#define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
60#endif
61
7eece5a0
KH		 62#define ISP4XXX_PCI_FN_1 0x1
63#define ISP4XXX_PCI_FN_2 0x3
64
afaf5a2d
DS		 65#define QLA_SUCCESS 0
66#define QLA_ERROR 1
67
68/*
69 * Data bit definitions
70 */
71#define BIT_0 0x1
72#define BIT_1 0x2
73#define BIT_2 0x4
74#define BIT_3 0x8
75#define BIT_4 0x10
76#define BIT_5 0x20
77#define BIT_6 0x40
78#define BIT_7 0x80
79#define BIT_8 0x100
80#define BIT_9 0x200
81#define BIT_10 0x400
82#define BIT_11 0x800
83#define BIT_12 0x1000
84#define BIT_13 0x2000
85#define BIT_14 0x4000
86#define BIT_15 0x8000
87#define BIT_16 0x10000
88#define BIT_17 0x20000
89#define BIT_18 0x40000
90#define BIT_19 0x80000
91#define BIT_20 0x100000
92#define BIT_21 0x200000
93#define BIT_22 0x400000
94#define BIT_23 0x800000
95#define BIT_24 0x1000000
96#define BIT_25 0x2000000
97#define BIT_26 0x4000000
98#define BIT_27 0x8000000
99#define BIT_28 0x10000000
100#define BIT_29 0x20000000
101#define BIT_30 0x40000000
102#define BIT_31 0x80000000
103
f4f5df23
VC		 104/**
105 * Macros to help code, maintain, etc.
106 **/
107#define ql4_printk(level, ha, format, arg...) \
108 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
109
110
afaf5a2d
DS		 111/*
112 * Host adapter default definitions
113 ***********************************/
114#define MAX_HBAS 16
115#define MAX_BUSES 1
f4f5df23 116#define MAX_TARGETS MAX_DEV_DB_ENTRIES
afaf5a2d 117#define MAX_LUNS 0xffff
b3a271a9 118#define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES
f4f5df23 119#define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
afaf5a2d
DS		 120#define MAX_PDU_ENTRIES 32
121#define INVALID_ENTRY 0xFFFF
122#define MAX_CMDS_TO_RISC 1024
123#define MAX_SRBS MAX_CMDS_TO_RISC
185f107e 124#define MBOX_AEN_REG_COUNT 8
afaf5a2d 125#define MAX_INIT_RETRIES 5
afaf5a2d
DS		 126
127/*
128 * Buffer sizes
129 */
130#define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
131#define RESPONSE_QUEUE_DEPTH 64
132#define QUEUE_SIZE 64
133#define DMA_BUFFER_SIZE 512
134
135/*
136 * Misc
137 */
138#define MAC_ADDR_LEN 6 /* in bytes */
139#define IP_ADDR_LEN 4 /* in bytes */
2a49a78e 140#define IPv6_ADDR_LEN 16 /* IPv6 address size */
afaf5a2d
DS		 141#define DRIVER_NAME "qla4xxx"
142
143#define MAX_LINKED_CMDS_PER_LUN 3
dbaf82ec 144#define MAX_REQS_SERVICED_PER_INTR 1
afaf5a2d
DS		 145
146#define ISCSI_IPADDR_SIZE 4 /* IP address size */
b1c11812 147#define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */
5c8bfc94 148#define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */
afaf5a2d 149
3013cea8
VC		 150#define QL4_SESS_RECOVERY_TMO 30 /* iSCSI session */
151 /* recovery timeout */
152
afaf5a2d
DS		 153#define LSDW(x) ((u32)((u64)(x)))
154#define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
155
156/*
157 * Retry & Timeout Values
158 */
159#define MBOX_TOV 60
160#define SOFT_RESET_TOV 30
161#define RESET_INTR_TOV 3
162#define SEMAPHORE_TOV 10
f4f5df23 163#define ADAPTER_INIT_TOV 30
afaf5a2d
DS		 164#define ADAPTER_RESET_TOV 180
165#define EXTEND_CMD_TOV 60
166#define WAIT_CMD_TOV 30
167#define EH_WAIT_CMD_TOV 120
168#define FIRMWARE_UP_TOV 60
169#define RESET_FIRMWARE_TOV 30
170#define LOGOUT_TOV 10
171#define IOCB_TOV_MARGIN 10
172#define RELOGIN_TOV 18
173#define ISNS_DEREG_TOV 5
f581a3f7 174#define HBA_ONLINE_TOV 30
95d31262 175#define DISABLE_ACB_TOV 30
afaf5a2d
DS		 176
177#define MAX_RESET_HA_RETRIES 2
178
5369887a
VC		 179#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
180
afaf5a2d
DS		 181/*
182 * SCSI Request Block structure (srb) that is placed
183 * on cmd->SCp location of every I/O [We have 22 bytes available]
184 */
185struct srb {
186 struct list_head list; /* (8) */
187 struct scsi_qla_host *ha; /* HA the SP is queued on */
6790d4fe 188 struct ddb_entry *ddb;
afaf5a2d
DS		 189 uint16_t flags; /* (1) Status flags. */
190
191#define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
25985edc 192#define SRB_GOT_SENSE BIT_4 /* sense data received. */
afaf5a2d
DS		 193 uint8_t state; /* (1) Status flags. */
194
195#define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
196#define SRB_FREE_STATE 1
197#define SRB_ACTIVE_STATE 3
198#define SRB_ACTIVE_TIMEOUT_STATE 4
199#define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
200
201 struct scsi_cmnd *cmd; /* (4) SCSI command block */
202 dma_addr_t dma_handle; /* (4) for unmap of single transfers */
09a0f719 203 struct kref srb_ref; /* reference count for this srb */
afaf5a2d
DS		 204 uint8_t err_id; /* error id */
205#define SRB_ERR_PORT 1 /* Request failed because "port down" */
206#define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
207#define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
208#define SRB_ERR_OTHER 4
209
210 uint16_t reserved;
211 uint16_t iocb_tov;
212 uint16_t iocb_cnt; /* Number of used iocbs */
213 uint16_t cc_stat;
94bced3c
KH		 214
215 /* Used for extended sense / status continuation */
216 uint8_t *req_sense_ptr;
217 uint16_t req_sense_len;
218 uint16_t reserved2;
afaf5a2d
DS		 219};
220
5c8bfc94
DS		 221/*
222 * Asynchronous Event Queue structure
223 */
224struct aen {
225 uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
226};
227
228struct ql4_aen_log {
229 int count;
230 struct aen entry[MAX_AEN_ENTRIES];
231};
232
233/*
234 * Device Database (DDB) structure
235 */
afaf5a2d 236struct ddb_entry {
afaf5a2d
DS		 237 struct scsi_qla_host *ha;
238 struct iscsi_cls_session *sess;
239 struct iscsi_cls_conn *conn;
240
afaf5a2d 241 uint16_t fw_ddb_index; /* DDB firmware index */
afaf5a2d 242 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */
afaf5a2d
DS		 243};
244
245/*
246 * DDB states.
247 */
248#define DDB_STATE_DEAD 0 /* We can no longer talk to
249 * this device */
250#define DDB_STATE_ONLINE 1 /* Device ready to accept
251 * commands */
252#define DDB_STATE_MISSING 2 /* Device logged off, trying
253 * to re-login */
254
255/*
256 * DDB flags.
257 */
258#define DF_RELOGIN 0 /* Relogin to device */
afaf5a2d
DS		 259#define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
260#define DF_FO_MASKED 3
261
afaf5a2d 262
afaf5a2d 263
f4f5df23
VC		 264struct ql82xx_hw_data {
265 /* Offsets for flash/nvram access (set to ~0 if not used). */
266 uint32_t flash_conf_off;
267 uint32_t flash_data_off;
268
269 uint32_t fdt_wrt_disable;
270 uint32_t fdt_erase_cmd;
271 uint32_t fdt_block_size;
272 uint32_t fdt_unprotect_sec_cmd;
273 uint32_t fdt_protect_sec_cmd;
274
275 uint32_t flt_region_flt;
276 uint32_t flt_region_fdt;
277 uint32_t flt_region_boot;
278 uint32_t flt_region_bootload;
279 uint32_t flt_region_fw;
2a991c21
MR		 280
281 uint32_t flt_iscsi_param;
f4f5df23
VC		 282 uint32_t reserved;
283};
284
285struct qla4_8xxx_legacy_intr_set {
286 uint32_t int_vec_bit;
287 uint32_t tgt_status_reg;
288 uint32_t tgt_mask_reg;
289 uint32_t pci_int_reg;
290};
291
292/* MSI-X Support */
293
294#define QLA_MSIX_DEFAULT 0x00
295#define QLA_MSIX_RSP_Q 0x01
296
297#define QLA_MSIX_ENTRIES 2
298#define QLA_MIDX_DEFAULT 0
299#define QLA_MIDX_RSP_Q 1
300
301struct ql4_msix_entry {
302 int have_irq;
303 uint16_t msix_vector;
304 uint16_t msix_entry;
305};
306
307/*
308 * ISP Operations
309 */
310struct isp_operations {
311 int (*iospace_config) (struct scsi_qla_host *ha);
312 void (*pci_config) (struct scsi_qla_host *);
313 void (*disable_intrs) (struct scsi_qla_host *);
314 void (*enable_intrs) (struct scsi_qla_host *);
315 int (*start_firmware) (struct scsi_qla_host *);
316 irqreturn_t (*intr_handler) (int , void *);
317 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
318 int (*reset_chip) (struct scsi_qla_host *);
319 int (*reset_firmware) (struct scsi_qla_host *);
320 void (*queue_iocb) (struct scsi_qla_host *);
321 void (*complete_iocb) (struct scsi_qla_host *);
322 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
323 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
324 int (*get_sys_info) (struct scsi_qla_host *);
325};
326
2bab08fc
VC		 327/*qla4xxx ipaddress configuration details */
328struct ipaddress_config {
329 uint16_t ipv4_options;
330 uint16_t tcp_options;
331 uint16_t ipv4_vlan_tag;
332 uint8_t ipv4_addr_state;
333 uint8_t ip_address[IP_ADDR_LEN];
334 uint8_t subnet_mask[IP_ADDR_LEN];
335 uint8_t gateway[IP_ADDR_LEN];
336 uint32_t ipv6_options;
337 uint32_t ipv6_addl_options;
338 uint8_t ipv6_link_local_state;
339 uint8_t ipv6_addr0_state;
340 uint8_t ipv6_addr1_state;
341 uint8_t ipv6_default_router_state;
342 uint16_t ipv6_vlan_tag;
343 struct in6_addr ipv6_link_local_addr;
344 struct in6_addr ipv6_addr0;
345 struct in6_addr ipv6_addr1;
346 struct in6_addr ipv6_default_router_addr;
943c157b 347 uint16_t eth_mtu_size;
2ada7fc5
VC		 348 uint16_t ipv4_port;
349 uint16_t ipv6_port;
2bab08fc
VC		 350};
351
2a991c21
MR		 352#define QL4_CHAP_MAX_NAME_LEN 256
353#define QL4_CHAP_MAX_SECRET_LEN 100
354
355struct ql4_chap_format {
356 u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN];
357 u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN];
358 u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN];
359 u8 target_secret[QL4_CHAP_MAX_SECRET_LEN];
360 u16 intr_chap_name_length;
361 u16 intr_secret_length;
362 u16 target_chap_name_length;
363 u16 target_secret_length;
364};
365
366struct ip_address_format {
367 u8 ip_type;
368 u8 ip_address[16];
369};
370
371struct ql4_conn_info {
372 u16 dest_port;
373 struct ip_address_format dest_ipaddr;
374 struct ql4_chap_format chap;
375};
376
377struct ql4_boot_session_info {
378 u8 target_name[224];
379 struct ql4_conn_info conn_list[1];
380};
381
382struct ql4_boot_tgt_info {
383 struct ql4_boot_session_info boot_pri_sess;
384 struct ql4_boot_session_info boot_sec_sess;
385};
386
afaf5a2d
DS		 387/*
388 * Linux Host Adapter structure
389 */
390struct scsi_qla_host {
391 /* Linux adapter configuration data */
afaf5a2d
DS		 392 unsigned long flags;
393
5c8bfc94
DS		 394#define AF_ONLINE 0 /* 0x00000001 */
395#define AF_INIT_DONE 1 /* 0x00000002 */
396#define AF_MBOX_COMMAND 2 /* 0x00000004 */
397#define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
398#define AF_INTERRUPTS_ON 6 /* 0x00000040 */
399#define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
400#define AF_LINK_UP 8 /* 0x00000100 */
401#define AF_IRQ_ATTACHED 10 /* 0x00000400 */
402#define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */
7eece5a0 403#define AF_HA_REMOVAL 12 /* 0x00001000 */
f4f5df23
VC		 404#define AF_INTx_ENABLED 15 /* 0x00008000 */
405#define AF_MSI_ENABLED 16 /* 0x00010000 */
406#define AF_MSIX_ENABLED 17 /* 0x00020000 */
407#define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */
21033639 408#define AF_FW_RECOVERY 19 /* 0x00080000 */
2232be0d
LC		 409#define AF_EEH_BUSY 20 /* 0x00100000 */
410#define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */
afaf5a2d
DS		 411
412 unsigned long dpc_flags;
413
5c8bfc94
DS		 414#define DPC_RESET_HA 1 /* 0x00000002 */
415#define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
416#define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
f4f5df23 417#define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */
5c8bfc94
DS		 418#define DPC_RESET_HA_INTR 5 /* 0x00000020 */
419#define DPC_ISNS_RESTART 7 /* 0x00000080 */
420#define DPC_AEN 9 /* 0x00000200 */
421#define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
065aa1b4 422#define DPC_LINK_CHANGED 18 /* 0x00040000 */
f4f5df23
VC		 423#define DPC_RESET_ACTIVE 20 /* 0x00040000 */
424#define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/
425#define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/
426
5c8bfc94
DS		 427
428 struct Scsi_Host *host; /* pointer to host data */
429 uint32_t tot_ddbs;
afaf5a2d 430
f4f5df23 431 uint16_t iocb_cnt;
afaf5a2d
DS		 432
433 /* SRB cache. */
434#define SRB_MIN_REQ 128
435 mempool_t *srb_mempool;
436
437 /* pci information */
438 struct pci_dev *pdev;
439
440 struct isp_reg __iomem *reg; /* Base I/O address */
441 unsigned long pio_address;
442 unsigned long pio_length;
443#define MIN_IOBASE_LEN 0x100
444
445 uint16_t req_q_count;
afaf5a2d
DS		 446
447 unsigned long host_no;
448
449 /* NVRAM registers */
450 struct eeprom_data *nvram;
451 spinlock_t hardware_lock ____cacheline_aligned;
f4f5df23 452 uint32_t eeprom_cmd_data;
afaf5a2d
DS		 453
454 /* Counters for general statistics */
d915058f 455 uint64_t isr_count;
afaf5a2d
DS		 456 uint64_t adapter_error_count;
457 uint64_t device_error_count;
458 uint64_t total_io_count;
459 uint64_t total_mbytes_xferred;
460 uint64_t link_failure_count;
461 uint64_t invalid_crc_count;
d915058f 462 uint32_t bytes_xfered;
afaf5a2d
DS		 463 uint32_t spurious_int_count;
464 uint32_t aborted_io_count;
465 uint32_t io_timeout_count;
466 uint32_t mailbox_timeout_count;
467 uint32_t seconds_since_last_intr;
468 uint32_t seconds_since_last_heartbeat;
469 uint32_t mac_index;
470
471 /* Info Needed for Management App */
472 /* --- From GetFwVersion --- */
473 uint32_t firmware_version[2];
474 uint32_t patch_number;
475 uint32_t build_number;
5c8bfc94 476 uint32_t board_id;
afaf5a2d
DS		 477
478 /* --- From Init_FW --- */
479 /* init_cb_t *init_cb; */
480 uint16_t firmware_options;
afaf5a2d
DS		 481 uint8_t alias[32];
482 uint8_t name_string[256];
483 uint8_t heartbeat_interval;
afaf5a2d
DS		 484
485 /* --- From FlashSysInfo --- */
486 uint8_t my_mac[MAC_ADDR_LEN];
487 uint8_t serial_number[16];
2a991c21 488 uint16_t port_num;
afaf5a2d
DS		 489 /* --- From GetFwState --- */
490 uint32_t firmware_state;
afaf5a2d
DS		 491 uint32_t addl_fw_state;
492
493 /* Linux kernel thread */
494 struct workqueue_struct *dpc_thread;
495 struct work_struct dpc_work;
496
497 /* Linux timer thread */
498 struct timer_list timer;
499 uint32_t timer_active;
500
501 /* Recovery Timers */
afaf5a2d
DS		 502 atomic_t check_relogin_timeouts;
503 uint32_t retry_reset_ha_cnt;
504 uint32_t isp_reset_timer; /* reset test timer */
505 uint32_t nic_reset_timer; /* simulated nic reset test timer */
506 int eh_start;
507 struct list_head free_srb_q;
508 uint16_t free_srb_q_count;
509 uint16_t num_srbs_allocated;
510
511 /* DMA Memory Block */
512 void *queues;
513 dma_addr_t queues_dma;
514 unsigned long queues_len;
515
516#define MEM_ALIGN_VALUE \
517 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
518 sizeof(struct queue_entry))
519 /* request and response queue variables */
520 dma_addr_t request_dma;
521 struct queue_entry *request_ring;
522 struct queue_entry *request_ptr;
523 dma_addr_t response_dma;
524 struct queue_entry *response_ring;
525 struct queue_entry *response_ptr;
526 dma_addr_t shadow_regs_dma;
527 struct shadow_regs *shadow_regs;
528 uint16_t request_in; /* Current indexes. */
529 uint16_t request_out;
530 uint16_t response_in;
531 uint16_t response_out;
532
533 /* aen queue variables */
534 uint16_t aen_q_count; /* Number of available aen_q entries */
535 uint16_t aen_in; /* Current indexes */
536 uint16_t aen_out;
537 struct aen aen_q[MAX_AEN_ENTRIES];
538
5c8bfc94
DS		 539 struct ql4_aen_log aen_log;/* tracks all aens */
540
afaf5a2d
DS		 541 /* This mutex protects several threads to do mailbox commands
542 * concurrently.
543 */
544 struct mutex mbox_sem;
afaf5a2d
DS		 545
546 /* temporary mailbox status registers */
547 volatile uint8_t mbox_status_count;
548 volatile uint32_t mbox_status[MBOX_REG_COUNT];
549
0e7e8501 550 /* FW ddb index map */
afaf5a2d
DS		 551 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
552
94bced3c
KH		 553 /* Saved srb for status continuation entry processing */
554 struct srb *status_srb;
2a49a78e 555
2a49a78e 556 uint8_t acb_version;
f4f5df23
VC		 557
558 /* qla82xx specific fields */
559 struct device_reg_82xx __iomem *qla4_8xxx_reg; /* Base I/O address */
560 unsigned long nx_pcibase; /* Base I/O address */
561 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */
562 unsigned long nx_db_wr_ptr; /* Door bell write pointer */
563 unsigned long first_page_group_start;
564 unsigned long first_page_group_end;
565
566 uint32_t crb_win;
567 uint32_t curr_window;
568 uint32_t ddr_mn_window;
569 unsigned long mn_win_crb;
570 unsigned long ms_win_crb;
571 int qdr_sn_window;
572 rwlock_t hw_lock;
573 uint16_t func_num;
574 int link_width;
575
576 struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
577 u32 nx_crb_mask;
578
579 uint8_t revision_id;
580 uint32_t fw_heartbeat_counter;
581
582 struct isp_operations *isp_ops;
583 struct ql82xx_hw_data hw;
584
585 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];
586
587 uint32_t nx_dev_init_timeout;
588 uint32_t nx_reset_timeout;
589
590 struct completion mbx_intr_comp;
7ad633c0 591
2bab08fc 592 struct ipaddress_config ip_config;
ed1086e0
VC		 593 struct iscsi_iface *iface_ipv4;
594 struct iscsi_iface *iface_ipv6_0;
595 struct iscsi_iface *iface_ipv6_1;
2bab08fc 596
7ad633c0
HZ		 597 /* --- From About Firmware --- */
598 uint16_t iscsi_major;
599 uint16_t iscsi_minor;
600 uint16_t bootload_major;
601 uint16_t bootload_minor;
602 uint16_t bootload_patch;
603 uint16_t bootload_build;
a355943c
VC		 604
605 uint32_t flash_state;
606#define QLFLASH_WAITING 0
607#define QLFLASH_READING 1
608#define QLFLASH_WRITING 2
b3a271a9
MR		 609 struct dma_pool *chap_dma_pool;
610#define CHAP_DMA_BLOCK_SIZE 512
611 struct workqueue_struct *task_wq;
612 unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG];
2a991c21
MR		 613#define SYSFS_FLAG_FW_SEL_BOOT 2
614 struct iscsi_boot_kset *boot_kset;
615 struct ql4_boot_tgt_info boot_tgt;
91ec7cec
VC		 616 uint16_t phy_port_num;
617 uint16_t phy_port_cnt;
618 uint16_t iscsi_pci_func_cnt;
619 uint8_t model_name[16];
95d31262 620 struct completion disable_acb_comp;
b3a271a9
MR		 621};
622
623struct ql4_task_data {
624 struct scsi_qla_host *ha;
625 uint8_t iocb_req_cnt;
626 dma_addr_t data_dma;
627 void *req_buffer;
628 dma_addr_t req_dma;
629 void *resp_buffer;
630 dma_addr_t resp_dma;
631 uint32_t resp_len;
632 struct iscsi_task *task;
633 struct passthru_status sts;
634 struct work_struct task_work;
635};
636
637struct qla_endpoint {
638 struct Scsi_Host *host;
639 struct sockaddr dst_addr;
640};
641
642struct qla_conn {
643 struct qla_endpoint *qla_ep;
afaf5a2d
DS		 644};
645
2a49a78e
VC		 646static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
647{
2bab08fc 648 return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0);
2a49a78e
VC		 649}
650
651static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
652{
2bab08fc
VC		 653 return ((ha->ip_config.ipv6_options &
654 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
2a49a78e
VC		 655}
656
afaf5a2d
DS		 657static inline int is_qla4010(struct scsi_qla_host *ha)
658{
659 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
660}
661
662static inline int is_qla4022(struct scsi_qla_host *ha)
663{
664 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
665}
666
d915058f
DS		 667static inline int is_qla4032(struct scsi_qla_host *ha)
668{
669 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
670}
671
f4f5df23
VC		 672static inline int is_qla8022(struct scsi_qla_host *ha)
673{
674 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
675}
676
2232be0d
LC		 677/* Note: Currently AER/EEH is now supported only for 8022 cards
678 * This function needs to be updated when AER/EEH is enabled
679 * for other cards.
680 */
681static inline int is_aer_supported(struct scsi_qla_host *ha)
682{
683 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
684}
685
afaf5a2d
DS		 686static inline int adapter_up(struct scsi_qla_host *ha)
687{
688 return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
689 (test_bit(AF_LINK_UP, &ha->flags) != 0);
690}
691
692static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
693{
b3a271a9 694 return (struct scsi_qla_host *)iscsi_host_priv(shost);
afaf5a2d
DS		 695}
696
697static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
698{
d915058f
DS		 699 return (is_qla4010(ha) ?
700 &ha->reg->u1.isp4010.nvram :
701 &ha->reg->u1.isp4022.semaphore);
afaf5a2d
DS		 702}
703
704static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
705{
d915058f
DS		 706 return (is_qla4010(ha) ?
707 &ha->reg->u1.isp4010.nvram :
708 &ha->reg->u1.isp4022.nvram);
afaf5a2d
DS		 709}
710
711static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
712{
d915058f
DS		 713 return (is_qla4010(ha) ?
714 &ha->reg->u2.isp4010.ext_hw_conf :
715 &ha->reg->u2.isp4022.p0.ext_hw_conf);
afaf5a2d
DS		 716}
717
718static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
719{
d915058f
DS		 720 return (is_qla4010(ha) ?
721 &ha->reg->u2.isp4010.port_status :
722 &ha->reg->u2.isp4022.p0.port_status);
afaf5a2d
DS		 723}
724
725static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
726{
d915058f
DS		 727 return (is_qla4010(ha) ?
728 &ha->reg->u2.isp4010.port_ctrl :
729 &ha->reg->u2.isp4022.p0.port_ctrl);
afaf5a2d
DS		 730}
731
732static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
733{
d915058f
DS		 734 return (is_qla4010(ha) ?
735 &ha->reg->u2.isp4010.port_err_status :
736 &ha->reg->u2.isp4022.p0.port_err_status);
afaf5a2d
DS		 737}
738
739static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
740{
d915058f
DS		 741 return (is_qla4010(ha) ?
742 &ha->reg->u2.isp4010.gp_out :
743 &ha->reg->u2.isp4022.p0.gp_out);
afaf5a2d
DS		 744}
745
746static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
747{
d915058f
DS		 748 return (is_qla4010(ha) ?
749 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
750 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
afaf5a2d
DS		 751}
752
753int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
754void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
755int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
756
757static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
758{
d915058f
DS		 759 if (is_qla4010(a))
760 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
761 QL4010_FLASH_SEM_BITS);
762 else
afaf5a2d
DS		 763 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
764 (QL4022_RESOURCE_BITS_BASE_CODE |
765 (a->mac_index)) << 13);
afaf5a2d
DS		 766}
767
768static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
769{
d915058f 770 if (is_qla4010(a))
afaf5a2d 771 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
d915058f
DS		 772 else
773 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
afaf5a2d
DS		 774}
775
776static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
777{
d915058f
DS		 778 if (is_qla4010(a))
779 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
780 QL4010_NVRAM_SEM_BITS);
781 else
afaf5a2d
DS		 782 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
783 (QL4022_RESOURCE_BITS_BASE_CODE |
784 (a->mac_index)) << 10);
afaf5a2d
DS		 785}
786
787static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
788{
d915058f 789 if (is_qla4010(a))
afaf5a2d 790 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
d915058f
DS		 791 else
792 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
afaf5a2d
DS		 793}
794
795static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
796{
d915058f
DS		 797 if (is_qla4010(a))
798 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
799 QL4010_DRVR_SEM_BITS);
800 else
afaf5a2d
DS		 801 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
802 (QL4022_RESOURCE_BITS_BASE_CODE |
803 (a->mac_index)) << 1);
afaf5a2d
DS		 804}
805
806static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
807{
d915058f 808 if (is_qla4010(a))
afaf5a2d 809 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
d915058f
DS		 810 else
811 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
afaf5a2d
DS		 812}
813
ef7830bb
HZ		 814static inline int ql4xxx_reset_active(struct scsi_qla_host *ha)
815{
816 return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
817 test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
818 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) ||
819 test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) ||
820 test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) ||
821 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
822
823}
afaf5a2d
DS		 824/*---------------------------------------------------------------------------*/
825
826/* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
827#define PRESERVE_DDB_LIST 0
828#define REBUILD_DDB_LIST 1
829
830/* Defines for process_aen() */
831#define PROCESS_ALL_AENS 0
832#define FLUSH_DDB_CHANGED_AENS 1
afaf5a2d 833
afaf5a2d 834#endif /*_QLA4XXX_H */
Linux 6.x block layer and io_uring tree(s)