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[SCSI] qla2xxx: Add scan_[start|finish]() callbacks for ISP24xx HBAs.
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_sup.c
CommitLineData
fa90c54f
AV		 1/*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
1da177e4 4 *
fa90c54f
AV		 5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
1da177e4
LT		 7#include "qla_def.h"
8
9#include <linux/delay.h>
10#include <asm/uaccess.h>
11
12static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
13static void qla2x00_nv_deselect(scsi_qla_host_t *);
14static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
15
16/*
17 * NVRAM support routines
18 */
19
20/**
fa2a1ce5 21 * qla2x00_lock_nvram_access() -
1da177e4
LT		 22 * @ha: HA context
23 */
24void
25qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
26{
27 uint16_t data;
3d71644c 28 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 29
30 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
31 data = RD_REG_WORD(&reg->nvram);
32 while (data & NVR_BUSY) {
33 udelay(100);
34 data = RD_REG_WORD(&reg->nvram);
35 }
36
37 /* Lock resource */
38 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
39 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
40 udelay(5);
41 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
42 while ((data & BIT_0) == 0) {
43 /* Lock failed */
44 udelay(100);
45 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
46 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
47 udelay(5);
48 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
49 }
50 }
51}
52
53/**
fa2a1ce5 54 * qla2x00_unlock_nvram_access() -
1da177e4
LT		 55 * @ha: HA context
56 */
57void
58qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
59{
3d71644c 60 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 61
62 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
63 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
64 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
65 }
66}
67
1da177e4
LT		 68/**
69 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
70 * request routine to get the word from NVRAM.
71 * @ha: HA context
72 * @addr: Address in NVRAM to read
73 *
74 * Returns the word read from nvram @addr.
75 */
76uint16_t
77qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
78{
79 uint16_t data;
80 uint32_t nv_cmd;
81
82 nv_cmd = addr << 16;
83 nv_cmd |= NV_READ_OP;
84 data = qla2x00_nvram_request(ha, nv_cmd);
85
86 return (data);
87}
88
89/**
90 * qla2x00_write_nvram_word() - Write NVRAM data.
91 * @ha: HA context
92 * @addr: Address in NVRAM to write
93 * @data: word to program
94 */
95void
96qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
97{
98 int count;
99 uint16_t word;
45aeaf1e 100 uint32_t nv_cmd, wait_cnt;
3d71644c 101 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 102
103 qla2x00_nv_write(ha, NVR_DATA_OUT);
104 qla2x00_nv_write(ha, 0);
105 qla2x00_nv_write(ha, 0);
106
107 for (word = 0; word < 8; word++)
108 qla2x00_nv_write(ha, NVR_DATA_OUT);
109
110 qla2x00_nv_deselect(ha);
111
112 /* Write data */
113 nv_cmd = (addr << 16) | NV_WRITE_OP;
114 nv_cmd |= data;
115 nv_cmd <<= 5;
116 for (count = 0; count < 27; count++) {
117 if (nv_cmd & BIT_31)
118 qla2x00_nv_write(ha, NVR_DATA_OUT);
119 else
120 qla2x00_nv_write(ha, 0);
121
122 nv_cmd <<= 1;
123 }
124
125 qla2x00_nv_deselect(ha);
126
127 /* Wait for NVRAM to become ready */
128 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 129 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 130 wait_cnt = NVR_WAIT_CNT;
1da177e4 131 do {
45aeaf1e
RA		 132 if (!--wait_cnt) {
133 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
134 __func__, ha->host_no));
135 break;
136 }
1da177e4
LT		 137 NVRAM_DELAY();
138 word = RD_REG_WORD(&reg->nvram);
139 } while ((word & NVR_DATA_IN) == 0);
140
141 qla2x00_nv_deselect(ha);
142
143 /* Disable writes */
144 qla2x00_nv_write(ha, NVR_DATA_OUT);
145 for (count = 0; count < 10; count++)
146 qla2x00_nv_write(ha, 0);
147
148 qla2x00_nv_deselect(ha);
149}
150
459c5378
AV		 151static int
152qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
153 uint32_t tmo)
154{
155 int ret, count;
156 uint16_t word;
157 uint32_t nv_cmd;
158 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
159
160 ret = QLA_SUCCESS;
161
162 qla2x00_nv_write(ha, NVR_DATA_OUT);
163 qla2x00_nv_write(ha, 0);
164 qla2x00_nv_write(ha, 0);
165
166 for (word = 0; word < 8; word++)
167 qla2x00_nv_write(ha, NVR_DATA_OUT);
168
169 qla2x00_nv_deselect(ha);
170
171 /* Write data */
172 nv_cmd = (addr << 16) | NV_WRITE_OP;
173 nv_cmd |= data;
174 nv_cmd <<= 5;
175 for (count = 0; count < 27; count++) {
176 if (nv_cmd & BIT_31)
177 qla2x00_nv_write(ha, NVR_DATA_OUT);
178 else
179 qla2x00_nv_write(ha, 0);
180
181 nv_cmd <<= 1;
182 }
183
184 qla2x00_nv_deselect(ha);
185
186 /* Wait for NVRAM to become ready */
187 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 188 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
459c5378
AV		 189 do {
190 NVRAM_DELAY();
191 word = RD_REG_WORD(&reg->nvram);
192 if (!--tmo) {
193 ret = QLA_FUNCTION_FAILED;
194 break;
195 }
196 } while ((word & NVR_DATA_IN) == 0);
197
198 qla2x00_nv_deselect(ha);
199
200 /* Disable writes */
201 qla2x00_nv_write(ha, NVR_DATA_OUT);
202 for (count = 0; count < 10; count++)
203 qla2x00_nv_write(ha, 0);
204
205 qla2x00_nv_deselect(ha);
206
207 return ret;
208}
209
1da177e4
LT		 210/**
211 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
212 * NVRAM.
213 * @ha: HA context
214 * @nv_cmd: NVRAM command
215 *
216 * Bit definitions for NVRAM command:
217 *
218 * Bit 26 = start bit
219 * Bit 25, 24 = opcode
220 * Bit 23-16 = address
221 * Bit 15-0 = write data
222 *
223 * Returns the word read from nvram @addr.
224 */
225static uint16_t
226qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
227{
228 uint8_t cnt;
3d71644c 229 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 230 uint16_t data = 0;
231 uint16_t reg_data;
232
233 /* Send command to NVRAM. */
234 nv_cmd <<= 5;
235 for (cnt = 0; cnt < 11; cnt++) {
236 if (nv_cmd & BIT_31)
237 qla2x00_nv_write(ha, NVR_DATA_OUT);
238 else
239 qla2x00_nv_write(ha, 0);
240 nv_cmd <<= 1;
241 }
242
243 /* Read data from NVRAM. */
244 for (cnt = 0; cnt < 16; cnt++) {
245 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
dcb36ce9 246 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1da177e4
LT		 247 NVRAM_DELAY();
248 data <<= 1;
249 reg_data = RD_REG_WORD(&reg->nvram);
250 if (reg_data & NVR_DATA_IN)
251 data |= BIT_0;
252 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
253 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
254 NVRAM_DELAY();
255 }
256
257 /* Deselect chip. */
258 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
259 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
260 NVRAM_DELAY();
261
262 return (data);
263}
264
265/**
266 * qla2x00_nv_write() - Clean NVRAM operations.
267 * @ha: HA context
268 */
269static void
270qla2x00_nv_deselect(scsi_qla_host_t *ha)
271{
3d71644c 272 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 273
274 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
275 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
276 NVRAM_DELAY();
277}
278
279/**
280 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
281 * @ha: HA context
282 * @data: Serial interface selector
283 */
284static void
285qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
286{
3d71644c 287 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 288
289 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
290 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
291 NVRAM_DELAY();
292 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT| NVR_CLOCK |
293 NVR_WRT_ENABLE);
294 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
295 NVRAM_DELAY();
296 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
297 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
298 NVRAM_DELAY();
299}
300
459c5378
AV		 301/**
302 * qla2x00_clear_nvram_protection() -
303 * @ha: HA context
304 */
305static int
306qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
307{
308 int ret, stat;
309 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 310 uint32_t word, wait_cnt;
459c5378
AV		 311 uint16_t wprot, wprot_old;
312
313 /* Clear NVRAM write protection. */
314 ret = QLA_FUNCTION_FAILED;
45aeaf1e
RA		 315
316 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
317 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
459c5378 318 __constant_cpu_to_le16(0x1234), 100000);
45aeaf1e
RA		 319 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
320 if (stat != QLA_SUCCESS || wprot != 0x1234) {
459c5378
AV		 321 /* Write enable. */
322 qla2x00_nv_write(ha, NVR_DATA_OUT);
323 qla2x00_nv_write(ha, 0);
324 qla2x00_nv_write(ha, 0);
325 for (word = 0; word < 8; word++)
326 qla2x00_nv_write(ha, NVR_DATA_OUT);
327
328 qla2x00_nv_deselect(ha);
329
330 /* Enable protection register. */
331 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
332 qla2x00_nv_write(ha, NVR_PR_ENABLE);
333 qla2x00_nv_write(ha, NVR_PR_ENABLE);
334 for (word = 0; word < 8; word++)
335 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
336
337 qla2x00_nv_deselect(ha);
338
339 /* Clear protection register (ffff is cleared). */
340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
343 for (word = 0; word < 8; word++)
344 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
345
346 qla2x00_nv_deselect(ha);
347
348 /* Wait for NVRAM to become ready. */
349 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 350 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 351 wait_cnt = NVR_WAIT_CNT;
459c5378 352 do {
45aeaf1e
RA		 353 if (!--wait_cnt) {
354 DEBUG9_10(printk("%s(%ld): NVRAM didn't go "
355 "ready...\n", __func__,
356 ha->host_no));
357 break;
358 }
459c5378
AV		 359 NVRAM_DELAY();
360 word = RD_REG_WORD(&reg->nvram);
361 } while ((word & NVR_DATA_IN) == 0);
362
45aeaf1e
RA		 363 if (wait_cnt)
364 ret = QLA_SUCCESS;
459c5378 365 } else
45aeaf1e 366 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
459c5378
AV		 367
368 return ret;
369}
370
371static void
372qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
373{
374 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 375 uint32_t word, wait_cnt;
459c5378
AV		 376
377 if (stat != QLA_SUCCESS)
378 return;
379
380 /* Set NVRAM write protection. */
381 /* Write enable. */
382 qla2x00_nv_write(ha, NVR_DATA_OUT);
383 qla2x00_nv_write(ha, 0);
384 qla2x00_nv_write(ha, 0);
385 for (word = 0; word < 8; word++)
386 qla2x00_nv_write(ha, NVR_DATA_OUT);
387
388 qla2x00_nv_deselect(ha);
389
390 /* Enable protection register. */
391 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
392 qla2x00_nv_write(ha, NVR_PR_ENABLE);
393 qla2x00_nv_write(ha, NVR_PR_ENABLE);
394 for (word = 0; word < 8; word++)
395 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
396
397 qla2x00_nv_deselect(ha);
398
399 /* Enable protection register. */
400 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
401 qla2x00_nv_write(ha, NVR_PR_ENABLE);
402 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
403 for (word = 0; word < 8; word++)
404 qla2x00_nv_write(ha, NVR_PR_ENABLE);
405
406 qla2x00_nv_deselect(ha);
407
408 /* Wait for NVRAM to become ready. */
409 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 410 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 411 wait_cnt = NVR_WAIT_CNT;
459c5378 412 do {
45aeaf1e
RA		 413 if (!--wait_cnt) {
414 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
415 __func__, ha->host_no));
416 break;
417 }
459c5378
AV		 418 NVRAM_DELAY();
419 word = RD_REG_WORD(&reg->nvram);
420 } while ((word & NVR_DATA_IN) == 0);
421}
422
423
424/*****************************************************************************/
425/* Flash Manipulation Routines */
426/*****************************************************************************/
427
428static inline uint32_t
429flash_conf_to_access_addr(uint32_t faddr)
430{
431 return FARX_ACCESS_FLASH_CONF | faddr;
432}
433
434static inline uint32_t
435flash_data_to_access_addr(uint32_t faddr)
436{
437 return FARX_ACCESS_FLASH_DATA | faddr;
438}
439
440static inline uint32_t
441nvram_conf_to_access_addr(uint32_t naddr)
442{
443 return FARX_ACCESS_NVRAM_CONF | naddr;
444}
445
446static inline uint32_t
447nvram_data_to_access_addr(uint32_t naddr)
448{
449 return FARX_ACCESS_NVRAM_DATA | naddr;
450}
451
e5f82ab8 452static uint32_t
459c5378
AV		 453qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
454{
455 int rval;
456 uint32_t cnt, data;
457 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
458
459 WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
460 /* Wait for READ cycle to complete. */
461 rval = QLA_SUCCESS;
462 for (cnt = 3000;
463 (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
464 rval == QLA_SUCCESS; cnt--) {
465 if (cnt)
466 udelay(10);
467 else
468 rval = QLA_FUNCTION_TIMEOUT;
469 }
470
471 /* TODO: What happens if we time out? */
472 data = 0xDEADDEAD;
473 if (rval == QLA_SUCCESS)
474 data = RD_REG_DWORD(&reg->flash_data);
475
476 return data;
477}
478
479uint32_t *
480qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
481 uint32_t dwords)
482{
483 uint32_t i;
459c5378
AV		 484
485 /* Dword reads to flash. */
486 for (i = 0; i < dwords; i++, faddr++)
487 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
488 flash_data_to_access_addr(faddr)));
489
459c5378
AV		 490 return dwptr;
491}
492
e5f82ab8 493static int
459c5378
AV		 494qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
495{
496 int rval;
497 uint32_t cnt;
498 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
499
500 WRT_REG_DWORD(&reg->flash_data, data);
501 RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
502 WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
503 /* Wait for Write cycle to complete. */
504 rval = QLA_SUCCESS;
505 for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
506 rval == QLA_SUCCESS; cnt--) {
507 if (cnt)
508 udelay(10);
509 else
510 rval = QLA_FUNCTION_TIMEOUT;
511 }
512 return rval;
513}
514
e5f82ab8 515static void
459c5378
AV		 516qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
517 uint8_t *flash_id)
518{
519 uint32_t ids;
520
521 ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
522 *man_id = LSB(ids);
523 *flash_id = MSB(ids);
45aeaf1e
RA		 524
525 /* Check if man_id and flash_id are valid. */
526 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
527 /* Read information using 0x9f opcode
528 * Device ID, Mfg ID would be read in the format:
529 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
530 * Example: ATMEL 0x00 01 45 1F
531 * Extract MFG and Dev ID from last two bytes.
532 */
533 ids = qla24xx_read_flash_dword(ha,
534 flash_data_to_access_addr(0xd009f));
535 *man_id = LSB(ids);
536 *flash_id = MSB(ids);
537 }
459c5378
AV		 538}
539
e5f82ab8 540static int
459c5378
AV		 541qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
542 uint32_t dwords)
543{
544 int ret;
545 uint32_t liter;
45aeaf1e
RA		 546 uint32_t sec_mask, rest_addr, conf_addr, sec_end_mask;
547 uint32_t fdata, findex ;
459c5378
AV		 548 uint8_t man_id, flash_id;
549 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
550
551 ret = QLA_SUCCESS;
552
459c5378
AV		 553 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
554 DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
555 ha->host_no, man_id, flash_id));
556
45aeaf1e 557 sec_end_mask = 0;
459c5378
AV		 558 conf_addr = flash_conf_to_access_addr(0x03d8);
559 switch (man_id) {
fa2a1ce5 560 case 0xbf: /* STT flash. */
459c5378
AV		 561 rest_addr = 0x1fff;
562 sec_mask = 0x3e000;
563 if (flash_id == 0x80)
564 conf_addr = flash_conf_to_access_addr(0x0352);
565 break;
fa2a1ce5 566 case 0x13: /* ST M25P80. */
459c5378
AV		 567 rest_addr = 0x3fff;
568 sec_mask = 0x3c000;
569 break;
45aeaf1e
RA		 570 case 0x1f: // Atmel 26DF081A
571 rest_addr = 0x0fff;
572 sec_mask = 0xff000;
573 sec_end_mask = 0x003ff;
574 conf_addr = flash_conf_to_access_addr(0x0320);
575 break;
459c5378 576 default:
fa2a1ce5 577 /* Default to 64 kb sector size. */
459c5378
AV		 578 rest_addr = 0x3fff;
579 sec_mask = 0x3c000;
580 break;
581 }
582
583 /* Enable flash write. */
584 WRT_REG_DWORD(&reg->ctrl_status,
585 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
586 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
587
588 /* Disable flash write-protection. */
589 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
45aeaf1e
RA		 590 /* Some flash parts need an additional zero-write to clear bits.*/
591 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
459c5378
AV		 592
593 do { /* Loop once to provide quick error exit. */
594 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
45aeaf1e
RA		 595 if (man_id == 0x1f) {
596 findex = faddr << 2;
597 fdata = findex & sec_mask;
598 } else {
599 findex = faddr;
600 fdata = (findex & sec_mask) << 2;
601 }
602
459c5378 603 /* Are we at the beginning of a sector? */
45aeaf1e
RA		 604 if ((findex & rest_addr) == 0) {
605 /*
606 * Do sector unprotect at 4K boundry for Atmel
607 * part.
608 */
609 if (man_id == 0x1f)
610 qla24xx_write_flash_dword(ha,
611 flash_conf_to_access_addr(0x0339),
612 (fdata & 0xff00) | ((fdata << 16) &
613 0xff0000) | ((fdata >> 16) & 0xff));
459c5378
AV		 614 ret = qla24xx_write_flash_dword(ha, conf_addr,
615 (fdata & 0xff00) |((fdata << 16) &
616 0xff0000) | ((fdata >> 16) & 0xff));
617 if (ret != QLA_SUCCESS) {
618 DEBUG9(printk("%s(%ld) Unable to flash "
619 "sector: address=%x.\n", __func__,
620 ha->host_no, faddr));
621 break;
622 }
623 }
624 ret = qla24xx_write_flash_dword(ha,
625 flash_data_to_access_addr(faddr),
626 cpu_to_le32(*dwptr));
627 if (ret != QLA_SUCCESS) {
628 DEBUG9(printk("%s(%ld) Unable to program flash "
629 "address=%x data=%x.\n", __func__,
630 ha->host_no, faddr, *dwptr));
631 break;
632 }
45aeaf1e
RA		 633
634 /* Do sector protect at 4K boundry for Atmel part. */
635 if (man_id == 0x1f &&
636 ((faddr & sec_end_mask) == 0x3ff))
637 qla24xx_write_flash_dword(ha,
638 flash_conf_to_access_addr(0x0336),
639 (fdata & 0xff00) | ((fdata << 16) &
640 0xff0000) | ((fdata >> 16) & 0xff));
459c5378
AV		 641 }
642 } while (0);
643
e978010c 644 /* Enable flash write-protection. */
645 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0x9c);
646
459c5378
AV		 647 /* Disable flash write. */
648 WRT_REG_DWORD(&reg->ctrl_status,
649 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
650 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
651
459c5378
AV		 652 return ret;
653}
654
655uint8_t *
656qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
657 uint32_t bytes)
658{
659 uint32_t i;
660 uint16_t *wptr;
661
662 /* Word reads to NVRAM via registers. */
663 wptr = (uint16_t *)buf;
664 qla2x00_lock_nvram_access(ha);
665 for (i = 0; i < bytes >> 1; i++, naddr++)
666 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
667 naddr));
668 qla2x00_unlock_nvram_access(ha);
669
670 return buf;
671}
672
673uint8_t *
674qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
675 uint32_t bytes)
676{
677 uint32_t i;
678 uint32_t *dwptr;
459c5378
AV		 679
680 /* Dword reads to flash. */
681 dwptr = (uint32_t *)buf;
682 for (i = 0; i < bytes >> 2; i++, naddr++)
683 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
684 nvram_data_to_access_addr(naddr)));
685
459c5378
AV		 686 return buf;
687}
688
689int
690qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
691 uint32_t bytes)
692{
693 int ret, stat;
694 uint32_t i;
695 uint16_t *wptr;
696
697 ret = QLA_SUCCESS;
698
699 qla2x00_lock_nvram_access(ha);
700
701 /* Disable NVRAM write-protection. */
702 stat = qla2x00_clear_nvram_protection(ha);
703
704 wptr = (uint16_t *)buf;
705 for (i = 0; i < bytes >> 1; i++, naddr++) {
706 qla2x00_write_nvram_word(ha, naddr,
707 cpu_to_le16(*wptr));
708 wptr++;
709 }
710
711 /* Enable NVRAM write-protection. */
712 qla2x00_set_nvram_protection(ha, stat);
713
714 qla2x00_unlock_nvram_access(ha);
715
716 return ret;
717}
718
719int
720qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
721 uint32_t bytes)
722{
723 int ret;
724 uint32_t i;
725 uint32_t *dwptr;
726 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
727
728 ret = QLA_SUCCESS;
729
459c5378
AV		 730 /* Enable flash write. */
731 WRT_REG_DWORD(&reg->ctrl_status,
732 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
733 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
734
735 /* Disable NVRAM write-protection. */
736 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
737 0);
738 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
739 0);
740
741 /* Dword writes to flash. */
742 dwptr = (uint32_t *)buf;
743 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
744 ret = qla24xx_write_flash_dword(ha,
745 nvram_data_to_access_addr(naddr),
746 cpu_to_le32(*dwptr));
747 if (ret != QLA_SUCCESS) {
748 DEBUG9(printk("%s(%ld) Unable to program "
749 "nvram address=%x data=%x.\n", __func__,
750 ha->host_no, naddr, *dwptr));
751 break;
752 }
753 }
754
755 /* Enable NVRAM write-protection. */
756 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
757 0x8c);
758
759 /* Disable flash write. */
760 WRT_REG_DWORD(&reg->ctrl_status,
761 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
762 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
763
459c5378
AV		 764 return ret;
765}
f6df144c 766
767
768static inline void
769qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
770{
771 if (IS_QLA2322(ha)) {
772 /* Flip all colors. */
773 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
774 /* Turn off. */
775 ha->beacon_color_state = 0;
776 *pflags = GPIO_LED_ALL_OFF;
777 } else {
778 /* Turn on. */
779 ha->beacon_color_state = QLA_LED_ALL_ON;
780 *pflags = GPIO_LED_RGA_ON;
781 }
782 } else {
783 /* Flip green led only. */
784 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
785 /* Turn off. */
786 ha->beacon_color_state = 0;
787 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
788 } else {
789 /* Turn on. */
790 ha->beacon_color_state = QLA_LED_GRN_ON;
791 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
792 }
793 }
794}
795
796void
797qla2x00_beacon_blink(struct scsi_qla_host *ha)
798{
799 uint16_t gpio_enable;
800 uint16_t gpio_data;
801 uint16_t led_color = 0;
802 unsigned long flags;
803 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
804
805 if (ha->pio_address)
806 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
807
808 spin_lock_irqsave(&ha->hardware_lock, flags);
809
810 /* Save the Original GPIOE. */
811 if (ha->pio_address) {
812 gpio_enable = RD_REG_WORD_PIO(&reg->gpioe);
813 gpio_data = RD_REG_WORD_PIO(&reg->gpiod);
814 } else {
815 gpio_enable = RD_REG_WORD(&reg->gpioe);
816 gpio_data = RD_REG_WORD(&reg->gpiod);
817 }
818
819 /* Set the modified gpio_enable values */
820 gpio_enable |= GPIO_LED_MASK;
821
822 if (ha->pio_address) {
823 WRT_REG_WORD_PIO(&reg->gpioe, gpio_enable);
824 } else {
825 WRT_REG_WORD(&reg->gpioe, gpio_enable);
826 RD_REG_WORD(&reg->gpioe);
827 }
828
829 qla2x00_flip_colors(ha, &led_color);
830
831 /* Clear out any previously set LED color. */
832 gpio_data &= ~GPIO_LED_MASK;
833
834 /* Set the new input LED color to GPIOD. */
835 gpio_data |= led_color;
836
837 /* Set the modified gpio_data values */
838 if (ha->pio_address) {
839 WRT_REG_WORD_PIO(&reg->gpiod, gpio_data);
840 } else {
841 WRT_REG_WORD(&reg->gpiod, gpio_data);
842 RD_REG_WORD(&reg->gpiod);
843 }
844
845 spin_unlock_irqrestore(&ha->hardware_lock, flags);
846}
847
848int
849qla2x00_beacon_on(struct scsi_qla_host *ha)
850{
851 uint16_t gpio_enable;
852 uint16_t gpio_data;
853 unsigned long flags;
854 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
855
856 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
857 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
858
859 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
860 qla_printk(KERN_WARNING, ha,
861 "Unable to update fw options (beacon on).\n");
862 return QLA_FUNCTION_FAILED;
863 }
864
865 if (ha->pio_address)
866 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
867
868 /* Turn off LEDs. */
869 spin_lock_irqsave(&ha->hardware_lock, flags);
870 if (ha->pio_address) {
871 gpio_enable = RD_REG_WORD_PIO(&reg->gpioe);
872 gpio_data = RD_REG_WORD_PIO(&reg->gpiod);
873 } else {
874 gpio_enable = RD_REG_WORD(&reg->gpioe);
875 gpio_data = RD_REG_WORD(&reg->gpiod);
876 }
877 gpio_enable |= GPIO_LED_MASK;
878
879 /* Set the modified gpio_enable values. */
880 if (ha->pio_address) {
881 WRT_REG_WORD_PIO(&reg->gpioe, gpio_enable);
882 } else {
883 WRT_REG_WORD(&reg->gpioe, gpio_enable);
884 RD_REG_WORD(&reg->gpioe);
885 }
886
887 /* Clear out previously set LED colour. */
888 gpio_data &= ~GPIO_LED_MASK;
889 if (ha->pio_address) {
890 WRT_REG_WORD_PIO(&reg->gpiod, gpio_data);
891 } else {
892 WRT_REG_WORD(&reg->gpiod, gpio_data);
893 RD_REG_WORD(&reg->gpiod);
894 }
895 spin_unlock_irqrestore(&ha->hardware_lock, flags);
896
897 /*
898 * Let the per HBA timer kick off the blinking process based on
899 * the following flags. No need to do anything else now.
900 */
901 ha->beacon_blink_led = 1;
902 ha->beacon_color_state = 0;
903
904 return QLA_SUCCESS;
905}
906
907int
908qla2x00_beacon_off(struct scsi_qla_host *ha)
909{
910 int rval = QLA_SUCCESS;
911
912 ha->beacon_blink_led = 0;
913
914 /* Set the on flag so when it gets flipped it will be off. */
915 if (IS_QLA2322(ha))
916 ha->beacon_color_state = QLA_LED_ALL_ON;
917 else
918 ha->beacon_color_state = QLA_LED_GRN_ON;
919
920 ha->isp_ops.beacon_blink(ha); /* This turns green LED off */
921
922 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
923 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
924
925 rval = qla2x00_set_fw_options(ha, ha->fw_options);
926 if (rval != QLA_SUCCESS)
927 qla_printk(KERN_WARNING, ha,
928 "Unable to update fw options (beacon off).\n");
929 return rval;
930}
931
932
933static inline void
934qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
935{
936 /* Flip all colors. */
937 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
938 /* Turn off. */
939 ha->beacon_color_state = 0;
940 *pflags = 0;
941 } else {
942 /* Turn on. */
943 ha->beacon_color_state = QLA_LED_ALL_ON;
944 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
945 }
946}
947
948void
949qla24xx_beacon_blink(struct scsi_qla_host *ha)
950{
951 uint16_t led_color = 0;
952 uint32_t gpio_data;
953 unsigned long flags;
954 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
955
956 /* Save the Original GPIOD. */
957 spin_lock_irqsave(&ha->hardware_lock, flags);
958 gpio_data = RD_REG_DWORD(&reg->gpiod);
959
960 /* Enable the gpio_data reg for update. */
961 gpio_data |= GPDX_LED_UPDATE_MASK;
962
963 WRT_REG_DWORD(&reg->gpiod, gpio_data);
964 gpio_data = RD_REG_DWORD(&reg->gpiod);
965
966 /* Set the color bits. */
967 qla24xx_flip_colors(ha, &led_color);
968
969 /* Clear out any previously set LED color. */
970 gpio_data &= ~GPDX_LED_COLOR_MASK;
971
972 /* Set the new input LED color to GPIOD. */
973 gpio_data |= led_color;
974
975 /* Set the modified gpio_data values. */
976 WRT_REG_DWORD(&reg->gpiod, gpio_data);
977 gpio_data = RD_REG_DWORD(&reg->gpiod);
978 spin_unlock_irqrestore(&ha->hardware_lock, flags);
979}
980
981int
982qla24xx_beacon_on(struct scsi_qla_host *ha)
983{
984 uint32_t gpio_data;
985 unsigned long flags;
986 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
987
988 if (ha->beacon_blink_led == 0) {
989 /* Enable firmware for update */
990 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
991
992 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS)
993 return QLA_FUNCTION_FAILED;
994
995 if (qla2x00_get_fw_options(ha, ha->fw_options) !=
996 QLA_SUCCESS) {
997 qla_printk(KERN_WARNING, ha,
998 "Unable to update fw options (beacon on).\n");
999 return QLA_FUNCTION_FAILED;
1000 }
1001
1002 spin_lock_irqsave(&ha->hardware_lock, flags);
1003 gpio_data = RD_REG_DWORD(&reg->gpiod);
1004
1005 /* Enable the gpio_data reg for update. */
1006 gpio_data |= GPDX_LED_UPDATE_MASK;
1007 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1008 RD_REG_DWORD(&reg->gpiod);
1009
1010 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1011 }
1012
1013 /* So all colors blink together. */
1014 ha->beacon_color_state = 0;
1015
1016 /* Let the per HBA timer kick off the blinking process. */
1017 ha->beacon_blink_led = 1;
1018
1019 return QLA_SUCCESS;
1020}
1021
1022int
1023qla24xx_beacon_off(struct scsi_qla_host *ha)
1024{
1025 uint32_t gpio_data;
1026 unsigned long flags;
1027 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1028
1029 ha->beacon_blink_led = 0;
1030 ha->beacon_color_state = QLA_LED_ALL_ON;
1031
1032 ha->isp_ops.beacon_blink(ha); /* Will flip to all off. */
1033
1034 /* Give control back to firmware. */
1035 spin_lock_irqsave(&ha->hardware_lock, flags);
1036 gpio_data = RD_REG_DWORD(&reg->gpiod);
1037
1038 /* Disable the gpio_data reg for update. */
1039 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1040 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1041 RD_REG_DWORD(&reg->gpiod);
1042 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1043
1044 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1045
1046 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1047 qla_printk(KERN_WARNING, ha,
1048 "Unable to update fw options (beacon off).\n");
1049 return QLA_FUNCTION_FAILED;
1050 }
1051
1052 if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1053 qla_printk(KERN_WARNING, ha,
1054 "Unable to get fw options (beacon off).\n");
1055 return QLA_FUNCTION_FAILED;
1056 }
1057
1058 return QLA_SUCCESS;
1059}
854165f4 1060
1061
1062/*
1063 * Flash support routines
1064 */
1065
1066/**
1067 * qla2x00_flash_enable() - Setup flash for reading and writing.
1068 * @ha: HA context
1069 */
1070static void
1071qla2x00_flash_enable(scsi_qla_host_t *ha)
1072{
1073 uint16_t data;
1074 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1075
1076 data = RD_REG_WORD(&reg->ctrl_status);
1077 data |= CSR_FLASH_ENABLE;
1078 WRT_REG_WORD(&reg->ctrl_status, data);
1079 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1080}
1081
1082/**
1083 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1084 * @ha: HA context
1085 */
1086static void
1087qla2x00_flash_disable(scsi_qla_host_t *ha)
1088{
1089 uint16_t data;
1090 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1091
1092 data = RD_REG_WORD(&reg->ctrl_status);
1093 data &= ~(CSR_FLASH_ENABLE);
1094 WRT_REG_WORD(&reg->ctrl_status, data);
1095 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1096}
1097
1098/**
1099 * qla2x00_read_flash_byte() - Reads a byte from flash
1100 * @ha: HA context
1101 * @addr: Address in flash to read
1102 *
1103 * A word is read from the chip, but, only the lower byte is valid.
1104 *
1105 * Returns the byte read from flash @addr.
1106 */
1107static uint8_t
1108qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr)
1109{
1110 uint16_t data;
1111 uint16_t bank_select;
1112 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1113
1114 bank_select = RD_REG_WORD(&reg->ctrl_status);
1115
1116 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1117 /* Specify 64K address range: */
1118 /* clear out Module Select and Flash Address bits [19:16]. */
1119 bank_select &= ~0xf8;
1120 bank_select |= addr >> 12 & 0xf0;
1121 bank_select |= CSR_FLASH_64K_BANK;
1122 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1123 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1124
1125 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1126 data = RD_REG_WORD(&reg->flash_data);
1127
1128 return (uint8_t)data;
1129 }
1130
1131 /* Setup bit 16 of flash address. */
1132 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1133 bank_select |= CSR_FLASH_64K_BANK;
1134 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1135 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1136 } else if (((addr & BIT_16) == 0) &&
1137 (bank_select & CSR_FLASH_64K_BANK)) {
1138 bank_select &= ~(CSR_FLASH_64K_BANK);
1139 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1140 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1141 }
1142
1143 /* Always perform IO mapped accesses to the FLASH registers. */
1144 if (ha->pio_address) {
1145 uint16_t data2;
1146
1147 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
1148 WRT_REG_WORD_PIO(&reg->flash_address, (uint16_t)addr);
1149 do {
1150 data = RD_REG_WORD_PIO(&reg->flash_data);
1151 barrier();
1152 cpu_relax();
1153 data2 = RD_REG_WORD_PIO(&reg->flash_data);
1154 } while (data != data2);
1155 } else {
1156 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1157 data = qla2x00_debounce_register(&reg->flash_data);
1158 }
1159
1160 return (uint8_t)data;
1161}
1162
1163/**
1164 * qla2x00_write_flash_byte() - Write a byte to flash
1165 * @ha: HA context
1166 * @addr: Address in flash to write
1167 * @data: Data to write
1168 */
1169static void
1170qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data)
1171{
1172 uint16_t bank_select;
1173 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1174
1175 bank_select = RD_REG_WORD(&reg->ctrl_status);
1176 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1177 /* Specify 64K address range: */
1178 /* clear out Module Select and Flash Address bits [19:16]. */
1179 bank_select &= ~0xf8;
1180 bank_select |= addr >> 12 & 0xf0;
1181 bank_select |= CSR_FLASH_64K_BANK;
1182 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1183 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1184
1185 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1186 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1187 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1188 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1189
1190 return;
1191 }
1192
1193 /* Setup bit 16 of flash address. */
1194 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1195 bank_select |= CSR_FLASH_64K_BANK;
1196 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1197 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1198 } else if (((addr & BIT_16) == 0) &&
1199 (bank_select & CSR_FLASH_64K_BANK)) {
1200 bank_select &= ~(CSR_FLASH_64K_BANK);
1201 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1202 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1203 }
1204
1205 /* Always perform IO mapped accesses to the FLASH registers. */
1206 if (ha->pio_address) {
1207 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
1208 WRT_REG_WORD_PIO(&reg->flash_address, (uint16_t)addr);
1209 WRT_REG_WORD_PIO(&reg->flash_data, (uint16_t)data);
1210 } else {
1211 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1212 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1213 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1214 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1215 }
1216}
1217
1218/**
1219 * qla2x00_poll_flash() - Polls flash for completion.
1220 * @ha: HA context
1221 * @addr: Address in flash to poll
1222 * @poll_data: Data to be polled
1223 * @man_id: Flash manufacturer ID
1224 * @flash_id: Flash ID
1225 *
1226 * This function polls the device until bit 7 of what is read matches data
1227 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1228 * out (a fatal error). The flash book recommeds reading bit 7 again after
1229 * reading bit 5 as a 1.
1230 *
1231 * Returns 0 on success, else non-zero.
1232 */
1233static int
1234qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data,
1235 uint8_t man_id, uint8_t flash_id)
1236{
1237 int status;
1238 uint8_t flash_data;
1239 uint32_t cnt;
1240
1241 status = 1;
1242
1243 /* Wait for 30 seconds for command to finish. */
1244 poll_data &= BIT_7;
1245 for (cnt = 3000000; cnt; cnt--) {
1246 flash_data = qla2x00_read_flash_byte(ha, addr);
1247 if ((flash_data & BIT_7) == poll_data) {
1248 status = 0;
1249 break;
1250 }
1251
1252 if (man_id != 0x40 && man_id != 0xda) {
1253 if ((flash_data & BIT_5) && cnt > 2)
1254 cnt = 2;
1255 }
1256 udelay(10);
1257 barrier();
1258 }
1259 return status;
1260}
1261
854165f4 1262/**
1263 * qla2x00_program_flash_address() - Programs a flash address
1264 * @ha: HA context
1265 * @addr: Address in flash to program
1266 * @data: Data to be written in flash
1267 * @man_id: Flash manufacturer ID
1268 * @flash_id: Flash ID
1269 *
1270 * Returns 0 on success, else non-zero.
1271 */
1272static int
1273qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data,
1274 uint8_t man_id, uint8_t flash_id)
1275{
1276 /* Write Program Command Sequence. */
1277 if (IS_OEM_001(ha)) {
1278 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1279 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1280 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1281 qla2x00_write_flash_byte(ha, addr, data);
1282 } else {
1283 if (man_id == 0xda && flash_id == 0xc1) {
1284 qla2x00_write_flash_byte(ha, addr, data);
1285 if (addr & 0x7e)
1286 return 0;
1287 } else {
1288 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1289 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1290 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1291 qla2x00_write_flash_byte(ha, addr, data);
1292 }
1293 }
1294
1295 udelay(150);
1296
1297 /* Wait for write to complete. */
1298 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1299}
1300
1301/**
1302 * qla2x00_erase_flash() - Erase the flash.
1303 * @ha: HA context
1304 * @man_id: Flash manufacturer ID
1305 * @flash_id: Flash ID
1306 *
1307 * Returns 0 on success, else non-zero.
1308 */
1309static int
1310qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id)
1311{
1312 /* Individual Sector Erase Command Sequence */
1313 if (IS_OEM_001(ha)) {
1314 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1315 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1316 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1317 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1318 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1319 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1320 } else {
1321 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1322 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1323 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1324 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1325 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1326 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1327 }
1328
1329 udelay(150);
1330
1331 /* Wait for erase to complete. */
1332 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1333}
1334
1335/**
1336 * qla2x00_erase_flash_sector() - Erase a flash sector.
1337 * @ha: HA context
1338 * @addr: Flash sector to erase
1339 * @sec_mask: Sector address mask
1340 * @man_id: Flash manufacturer ID
1341 * @flash_id: Flash ID
1342 *
1343 * Returns 0 on success, else non-zero.
1344 */
1345static int
1346qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr,
1347 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1348{
1349 /* Individual Sector Erase Command Sequence */
1350 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1351 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1352 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1353 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1354 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1355 if (man_id == 0x1f && flash_id == 0x13)
1356 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1357 else
1358 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1359
1360 udelay(150);
1361
1362 /* Wait for erase to complete. */
1363 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1364}
1365
1366/**
1367 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1368 * @man_id: Flash manufacturer ID
1369 * @flash_id: Flash ID
1370 */
1371static void
1372qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
1373 uint8_t *flash_id)
1374{
1375 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1376 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1377 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1378 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1379 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1380 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1381 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1382 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1383}
1384
30c47662
AV		 1385static void
1386qla2x00_read_flash_data(scsi_qla_host_t *ha, uint8_t *tmp_buf, uint32_t saddr,
1387 uint32_t length)
1388{
1389 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1390 uint32_t midpoint, ilength;
1391 uint8_t data;
1392
1393 midpoint = length / 2;
1394
1395 WRT_REG_WORD(&reg->nvram, 0);
1396 RD_REG_WORD(&reg->nvram);
1397 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1398 if (ilength == midpoint) {
1399 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1400 RD_REG_WORD(&reg->nvram);
1401 }
1402 data = qla2x00_read_flash_byte(ha, saddr);
1403 if (saddr % 100)
1404 udelay(10);
1405 *tmp_buf = data;
1406 }
1407}
854165f4 1408
1409static inline void
1410qla2x00_suspend_hba(struct scsi_qla_host *ha)
1411{
1412 int cnt;
1413 unsigned long flags;
1414 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1415
1416 /* Suspend HBA. */
1417 scsi_block_requests(ha->host);
1418 ha->isp_ops.disable_intrs(ha);
1419 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1420
1421 /* Pause RISC. */
1422 spin_lock_irqsave(&ha->hardware_lock, flags);
1423 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1424 RD_REG_WORD(&reg->hccr);
1425 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1426 for (cnt = 0; cnt < 30000; cnt++) {
1427 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1428 break;
1429 udelay(100);
1430 }
1431 } else {
1432 udelay(10);
1433 }
1434 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1435}
1436
1437static inline void
1438qla2x00_resume_hba(struct scsi_qla_host *ha)
1439{
1440 /* Resume HBA. */
1441 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1442 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
39a11240 1443 qla2xxx_wake_dpc(ha);
854165f4 1444 qla2x00_wait_for_hba_online(ha);
1445 scsi_unblock_requests(ha->host);
1446}
1447
1448uint8_t *
1449qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1450 uint32_t offset, uint32_t length)
1451{
1452 unsigned long flags;
1453 uint32_t addr, midpoint;
1454 uint8_t *data;
1455 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1456
1457 /* Suspend HBA. */
1458 qla2x00_suspend_hba(ha);
1459
1460 /* Go with read. */
1461 spin_lock_irqsave(&ha->hardware_lock, flags);
1462 midpoint = ha->optrom_size / 2;
1463
1464 qla2x00_flash_enable(ha);
1465 WRT_REG_WORD(&reg->nvram, 0);
1466 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1467 for (addr = offset, data = buf; addr < length; addr++, data++) {
1468 if (addr == midpoint) {
1469 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1470 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1471 }
1472
1473 *data = qla2x00_read_flash_byte(ha, addr);
1474 }
1475 qla2x00_flash_disable(ha);
1476 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1477
1478 /* Resume HBA. */
1479 qla2x00_resume_hba(ha);
1480
1481 return buf;
1482}
1483
1484int
1485qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1486 uint32_t offset, uint32_t length)
1487{
1488
1489 int rval;
1490 unsigned long flags;
1491 uint8_t man_id, flash_id, sec_number, data;
1492 uint16_t wd;
1493 uint32_t addr, liter, sec_mask, rest_addr;
1494 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1495
1496 /* Suspend HBA. */
1497 qla2x00_suspend_hba(ha);
1498
1499 rval = QLA_SUCCESS;
1500 sec_number = 0;
1501
1502 /* Reset ISP chip. */
1503 spin_lock_irqsave(&ha->hardware_lock, flags);
1504 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1505 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1506
1507 /* Go with write. */
1508 qla2x00_flash_enable(ha);
1509 do { /* Loop once to provide quick error exit */
1510 /* Structure of flash memory based on manufacturer */
1511 if (IS_OEM_001(ha)) {
1512 /* OEM variant with special flash part. */
1513 man_id = flash_id = 0;
1514 rest_addr = 0xffff;
1515 sec_mask = 0x10000;
1516 goto update_flash;
1517 }
1518 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1519 switch (man_id) {
1520 case 0x20: /* ST flash. */
1521 if (flash_id == 0xd2 || flash_id == 0xe3) {
1522 /*
1523 * ST m29w008at part - 64kb sector size with
1524 * 32kb,8kb,8kb,16kb sectors at memory address
1525 * 0xf0000.
1526 */
1527 rest_addr = 0xffff;
1528 sec_mask = 0x10000;
1529 break;
1530 }
1531 /*
1532 * ST m29w010b part - 16kb sector size
1533 * Default to 16kb sectors
1534 */
1535 rest_addr = 0x3fff;
1536 sec_mask = 0x1c000;
1537 break;
1538 case 0x40: /* Mostel flash. */
1539 /* Mostel v29c51001 part - 512 byte sector size. */
1540 rest_addr = 0x1ff;
1541 sec_mask = 0x1fe00;
1542 break;
1543 case 0xbf: /* SST flash. */
1544 /* SST39sf10 part - 4kb sector size. */
1545 rest_addr = 0xfff;
1546 sec_mask = 0x1f000;
1547 break;
1548 case 0xda: /* Winbond flash. */
1549 /* Winbond W29EE011 part - 256 byte sector size. */
1550 rest_addr = 0x7f;
1551 sec_mask = 0x1ff80;
1552 break;
1553 case 0xc2: /* Macronix flash. */
1554 /* 64k sector size. */
1555 if (flash_id == 0x38 || flash_id == 0x4f) {
1556 rest_addr = 0xffff;
1557 sec_mask = 0x10000;
1558 break;
1559 }
1560 /* Fall through... */
1561
1562 case 0x1f: /* Atmel flash. */
1563 /* 512k sector size. */
1564 if (flash_id == 0x13) {
1565 rest_addr = 0x7fffffff;
1566 sec_mask = 0x80000000;
1567 break;
1568 }
1569 /* Fall through... */
1570
1571 case 0x01: /* AMD flash. */
1572 if (flash_id == 0x38 || flash_id == 0x40 ||
1573 flash_id == 0x4f) {
1574 /* Am29LV081 part - 64kb sector size. */
1575 /* Am29LV002BT part - 64kb sector size. */
1576 rest_addr = 0xffff;
1577 sec_mask = 0x10000;
1578 break;
1579 } else if (flash_id == 0x3e) {
1580 /*
1581 * Am29LV008b part - 64kb sector size with
1582 * 32kb,8kb,8kb,16kb sector at memory address
1583 * h0xf0000.
1584 */
1585 rest_addr = 0xffff;
1586 sec_mask = 0x10000;
1587 break;
1588 } else if (flash_id == 0x20 || flash_id == 0x6e) {
1589 /*
1590 * Am29LV010 part or AM29f010 - 16kb sector
1591 * size.
1592 */
1593 rest_addr = 0x3fff;
1594 sec_mask = 0x1c000;
1595 break;
1596 } else if (flash_id == 0x6d) {
1597 /* Am29LV001 part - 8kb sector size. */
1598 rest_addr = 0x1fff;
1599 sec_mask = 0x1e000;
1600 break;
1601 }
1602 default:
1603 /* Default to 16 kb sector size. */
1604 rest_addr = 0x3fff;
1605 sec_mask = 0x1c000;
1606 break;
1607 }
1608
1609update_flash:
1610 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1611 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
1612 rval = QLA_FUNCTION_FAILED;
1613 break;
1614 }
1615 }
1616
1617 for (addr = offset, liter = 0; liter < length; liter++,
1618 addr++) {
1619 data = buf[liter];
1620 /* Are we at the beginning of a sector? */
1621 if ((addr & rest_addr) == 0) {
1622 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1623 if (addr >= 0x10000UL) {
1624 if (((addr >> 12) & 0xf0) &&
1625 ((man_id == 0x01 &&
1626 flash_id == 0x3e) ||
1627 (man_id == 0x20 &&
1628 flash_id == 0xd2))) {
1629 sec_number++;
1630 if (sec_number == 1) {
1631 rest_addr =
1632 0x7fff;
1633 sec_mask =
1634 0x18000;
1635 } else if (
1636 sec_number == 2 ||
1637 sec_number == 3) {
1638 rest_addr =
1639 0x1fff;
1640 sec_mask =
1641 0x1e000;
1642 } else if (
1643 sec_number == 4) {
1644 rest_addr =
1645 0x3fff;
1646 sec_mask =
1647 0x1c000;
1648 }
1649 }
1650 }
1651 } else if (addr == ha->optrom_size / 2) {
1652 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1653 RD_REG_WORD(&reg->nvram);
1654 }
1655
1656 if (flash_id == 0xda && man_id == 0xc1) {
1657 qla2x00_write_flash_byte(ha, 0x5555,
1658 0xaa);
1659 qla2x00_write_flash_byte(ha, 0x2aaa,
1660 0x55);
1661 qla2x00_write_flash_byte(ha, 0x5555,
1662 0xa0);
1663 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
1664 /* Then erase it */
1665 if (qla2x00_erase_flash_sector(ha,
1666 addr, sec_mask, man_id,
1667 flash_id)) {
1668 rval = QLA_FUNCTION_FAILED;
1669 break;
1670 }
1671 if (man_id == 0x01 && flash_id == 0x6d)
1672 sec_number++;
1673 }
1674 }
1675
1676 if (man_id == 0x01 && flash_id == 0x6d) {
1677 if (sec_number == 1 &&
1678 addr == (rest_addr - 1)) {
1679 rest_addr = 0x0fff;
1680 sec_mask = 0x1f000;
1681 } else if (sec_number == 3 && (addr & 0x7ffe)) {
1682 rest_addr = 0x3fff;
1683 sec_mask = 0x1c000;
1684 }
1685 }
1686
1687 if (qla2x00_program_flash_address(ha, addr, data,
1688 man_id, flash_id)) {
1689 rval = QLA_FUNCTION_FAILED;
1690 break;
1691 }
1692 }
1693 } while (0);
1694 qla2x00_flash_disable(ha);
1695 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1696
1697 /* Resume HBA. */
1698 qla2x00_resume_hba(ha);
1699
1700 return rval;
1701}
1702
1703uint8_t *
1704qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1705 uint32_t offset, uint32_t length)
1706{
1707 /* Suspend HBA. */
1708 scsi_block_requests(ha->host);
1709 ha->isp_ops.disable_intrs(ha);
1710 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1711
1712 /* Go with read. */
1713 qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2);
1714
1715 /* Resume HBA. */
1716 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1717 ha->isp_ops.enable_intrs(ha);
1718 scsi_unblock_requests(ha->host);
1719
1720 return buf;
1721}
1722
1723int
1724qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1725 uint32_t offset, uint32_t length)
1726{
1727 int rval;
1728
1729 /* Suspend HBA. */
1730 scsi_block_requests(ha->host);
1731 ha->isp_ops.disable_intrs(ha);
1732 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1733
1734 /* Go with write. */
1735 rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2,
1736 length >> 2);
1737
1738 /* Resume HBA -- RISC reset needed. */
1739 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1740 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
39a11240 1741 qla2xxx_wake_dpc(ha);
854165f4 1742 qla2x00_wait_for_hba_online(ha);
1743 scsi_unblock_requests(ha->host);
1744
1745 return rval;
1746}
30c47662
AV		 1747
1748/**
1749 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
1750 * @ha: HA context
1751 * @pcids: Pointer to the FCODE PCI data structure
1752 *
1753 * The process of retrieving the FCODE version information is at best
1754 * described as interesting.
1755 *
1756 * Within the first 100h bytes of the image an ASCII string is present
1757 * which contains several pieces of information including the FCODE
1758 * version. Unfortunately it seems the only reliable way to retrieve
1759 * the version is by scanning for another sentinel within the string,
1760 * the FCODE build date:
1761 *
1762 * ... 2.00.02 10/17/02 ...
1763 *
1764 * Returns QLA_SUCCESS on successful retrieval of version.
1765 */
1766static void
1767qla2x00_get_fcode_version(scsi_qla_host_t *ha, uint32_t pcids)
1768{
1769 int ret = QLA_FUNCTION_FAILED;
1770 uint32_t istart, iend, iter, vend;
1771 uint8_t do_next, rbyte, *vbyte;
1772
1773 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
1774
1775 /* Skip the PCI data structure. */
1776 istart = pcids +
1777 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
1778 qla2x00_read_flash_byte(ha, pcids + 0x0A));
1779 iend = istart + 0x100;
1780 do {
1781 /* Scan for the sentinel date string...eeewww. */
1782 do_next = 0;
1783 iter = istart;
1784 while ((iter < iend) && !do_next) {
1785 iter++;
1786 if (qla2x00_read_flash_byte(ha, iter) == '/') {
1787 if (qla2x00_read_flash_byte(ha, iter + 2) ==
1788 '/')
1789 do_next++;
1790 else if (qla2x00_read_flash_byte(ha,
1791 iter + 3) == '/')
1792 do_next++;
1793 }
1794 }
1795 if (!do_next)
1796 break;
1797
1798 /* Backtrack to previous ' ' (space). */
1799 do_next = 0;
1800 while ((iter > istart) && !do_next) {
1801 iter--;
1802 if (qla2x00_read_flash_byte(ha, iter) == ' ')
1803 do_next++;
1804 }
1805 if (!do_next)
1806 break;
1807
1808 /*
1809 * Mark end of version tag, and find previous ' ' (space) or
1810 * string length (recent FCODE images -- major hack ahead!!!).
1811 */
1812 vend = iter - 1;
1813 do_next = 0;
1814 while ((iter > istart) && !do_next) {
1815 iter--;
1816 rbyte = qla2x00_read_flash_byte(ha, iter);
1817 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
1818 do_next++;
1819 }
1820 if (!do_next)
1821 break;
1822
1823 /* Mark beginning of version tag, and copy data. */
1824 iter++;
1825 if ((vend - iter) &&
1826 ((vend - iter) < sizeof(ha->fcode_revision))) {
1827 vbyte = ha->fcode_revision;
1828 while (iter <= vend) {
1829 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
1830 iter++;
1831 }
1832 ret = QLA_SUCCESS;
1833 }
1834 } while (0);
1835
1836 if (ret != QLA_SUCCESS)
1837 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
1838}
1839
1840int
1841qla2x00_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
1842{
1843 int ret = QLA_SUCCESS;
1844 uint8_t code_type, last_image;
1845 uint32_t pcihdr, pcids;
1846 uint8_t *dbyte;
1847 uint16_t *dcode;
1848
1849 if (!ha->pio_address || !mbuf)
1850 return QLA_FUNCTION_FAILED;
1851
1852 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
1853 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
1854 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
1855 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
1856
1857 qla2x00_flash_enable(ha);
1858
1859 /* Begin with first PCI expansion ROM header. */
1860 pcihdr = 0;
1861 last_image = 1;
1862 do {
1863 /* Verify PCI expansion ROM header. */
1864 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
1865 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
1866 /* No signature */
1867 DEBUG2(printk("scsi(%ld): No matching ROM "
1868 "signature.\n", ha->host_no));
1869 ret = QLA_FUNCTION_FAILED;
1870 break;
1871 }
1872
1873 /* Locate PCI data structure. */
1874 pcids = pcihdr +
1875 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
1876 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
1877
1878 /* Validate signature of PCI data structure. */
1879 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
1880 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
1881 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
1882 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
1883 /* Incorrect header. */
1884 DEBUG2(printk("%s(): PCI data struct not found "
1885 "pcir_adr=%x.\n", __func__, pcids));
1886 ret = QLA_FUNCTION_FAILED;
1887 break;
1888 }
1889
1890 /* Read version */
1891 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
1892 switch (code_type) {
1893 case ROM_CODE_TYPE_BIOS:
1894 /* Intel x86, PC-AT compatible. */
1895 ha->bios_revision[0] =
1896 qla2x00_read_flash_byte(ha, pcids + 0x12);
1897 ha->bios_revision[1] =
1898 qla2x00_read_flash_byte(ha, pcids + 0x13);
1899 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
1900 ha->bios_revision[1], ha->bios_revision[0]));
1901 break;
1902 case ROM_CODE_TYPE_FCODE:
1903 /* Open Firmware standard for PCI (FCode). */
1904 /* Eeeewww... */
1905 qla2x00_get_fcode_version(ha, pcids);
1906 break;
1907 case ROM_CODE_TYPE_EFI:
1908 /* Extensible Firmware Interface (EFI). */
1909 ha->efi_revision[0] =
1910 qla2x00_read_flash_byte(ha, pcids + 0x12);
1911 ha->efi_revision[1] =
1912 qla2x00_read_flash_byte(ha, pcids + 0x13);
1913 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
1914 ha->efi_revision[1], ha->efi_revision[0]));
1915 break;
1916 default:
1917 DEBUG2(printk("%s(): Unrecognized code type %x at "
1918 "pcids %x.\n", __func__, code_type, pcids));
1919 break;
1920 }
1921
1922 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
1923
1924 /* Locate next PCI expansion ROM. */
1925 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
1926 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
1927 } while (!last_image);
1928
1929 if (IS_QLA2322(ha)) {
1930 /* Read firmware image information. */
1931 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
1932 dbyte = mbuf;
1933 memset(dbyte, 0, 8);
1934 dcode = (uint16_t *)dbyte;
1935
1936 qla2x00_read_flash_data(ha, dbyte, FA_RISC_CODE_ADDR * 4 + 10,
1937 8);
1938 DEBUG3(printk("%s(%ld): dumping fw ver from flash:\n",
1939 __func__, ha->host_no));
1940 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
1941
1942 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
1943 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
1944 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
1945 dcode[3] == 0)) {
1946 DEBUG2(printk("%s(): Unrecognized fw revision at "
1947 "%x.\n", __func__, FA_RISC_CODE_ADDR * 4));
1948 } else {
1949 /* values are in big endian */
1950 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
1951 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
1952 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
1953 }
1954 }
1955
1956 qla2x00_flash_disable(ha);
1957
1958 return ret;
1959}
1960
1961int
1962qla24xx_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
1963{
1964 int ret = QLA_SUCCESS;
1965 uint32_t pcihdr, pcids;
1966 uint32_t *dcode;
1967 uint8_t *bcode;
1968 uint8_t code_type, last_image;
1969 int i;
1970
1971 if (!mbuf)
1972 return QLA_FUNCTION_FAILED;
1973
1974 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
1975 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
1976 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
1977 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
1978
1979 dcode = mbuf;
1980
1981 /* Begin with first PCI expansion ROM header. */
1982 pcihdr = 0;
1983 last_image = 1;
1984 do {
1985 /* Verify PCI expansion ROM header. */
1986 qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20);
1987 bcode = mbuf + (pcihdr % 4);
1988 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
1989 /* No signature */
1990 DEBUG2(printk("scsi(%ld): No matching ROM "
1991 "signature.\n", ha->host_no));
1992 ret = QLA_FUNCTION_FAILED;
1993 break;
1994 }
1995
1996 /* Locate PCI data structure. */
1997 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
1998
1999 qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20);
2000 bcode = mbuf + (pcihdr % 4);
2001
2002 /* Validate signature of PCI data structure. */
2003 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2004 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2005 /* Incorrect header. */
2006 DEBUG2(printk("%s(): PCI data struct not found "
2007 "pcir_adr=%x.\n", __func__, pcids));
2008 ret = QLA_FUNCTION_FAILED;
2009 break;
2010 }
2011
2012 /* Read version */
2013 code_type = bcode[0x14];
2014 switch (code_type) {
2015 case ROM_CODE_TYPE_BIOS:
2016 /* Intel x86, PC-AT compatible. */
2017 ha->bios_revision[0] = bcode[0x12];
2018 ha->bios_revision[1] = bcode[0x13];
2019 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
2020 ha->bios_revision[1], ha->bios_revision[0]));
2021 break;
2022 case ROM_CODE_TYPE_FCODE:
2023 /* Open Firmware standard for PCI (FCode). */
2024 ha->fcode_revision[0] = bcode[0x12];
2025 ha->fcode_revision[1] = bcode[0x13];
2026 DEBUG3(printk("%s(): read FCODE %d.%d.\n", __func__,
2027 ha->fcode_revision[1], ha->fcode_revision[0]));
2028 break;
2029 case ROM_CODE_TYPE_EFI:
2030 /* Extensible Firmware Interface (EFI). */
2031 ha->efi_revision[0] = bcode[0x12];
2032 ha->efi_revision[1] = bcode[0x13];
2033 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
2034 ha->efi_revision[1], ha->efi_revision[0]));
2035 break;
2036 default:
2037 DEBUG2(printk("%s(): Unrecognized code type %x at "
2038 "pcids %x.\n", __func__, code_type, pcids));
2039 break;
2040 }
2041
2042 last_image = bcode[0x15] & BIT_7;
2043
2044 /* Locate next PCI expansion ROM. */
2045 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2046 } while (!last_image);
2047
2048 /* Read firmware image information. */
2049 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2050 dcode = mbuf;
2051
2052 qla24xx_read_flash_data(ha, dcode, FA_RISC_CODE_ADDR + 4, 4);
2053 for (i = 0; i < 4; i++)
2054 dcode[i] = be32_to_cpu(dcode[i]);
2055
2056 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2057 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2058 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2059 dcode[3] == 0)) {
2060 DEBUG2(printk("%s(): Unrecognized fw version at %x.\n",
2061 __func__, FA_RISC_CODE_ADDR));
2062 } else {
2063 ha->fw_revision[0] = dcode[0];
2064 ha->fw_revision[1] = dcode[1];
2065 ha->fw_revision[2] = dcode[2];
2066 ha->fw_revision[3] = dcode[3];
2067 }
2068
2069 return ret;
2070}
Linux 6.x block layer and io_uring tree(s)