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[SCSI] qla2xxx: Correctly print out/in mailbox registers.
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_sup.c
CommitLineData
fa90c54f
AV		 1/*
2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
1da177e4 4 *
fa90c54f
AV		 5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
1da177e4
LT		 7#include "qla_def.h"
8
9#include <linux/delay.h>
5a0e3ad6 10#include <linux/slab.h>
2c96d8d0 11#include <linux/vmalloc.h>
1da177e4
LT		 12#include <asm/uaccess.h>
13
1da177e4
LT		 14/*
15 * NVRAM support routines
16 */
17
18/**
fa2a1ce5 19 * qla2x00_lock_nvram_access() -
1da177e4
LT		 20 * @ha: HA context
21 */
a824ebb3 22static void
7b867cf7 23qla2x00_lock_nvram_access(struct qla_hw_data *ha)
1da177e4
LT		 24{
25 uint16_t data;
3d71644c 26 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 27
28 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
29 data = RD_REG_WORD(&reg->nvram);
30 while (data & NVR_BUSY) {
31 udelay(100);
32 data = RD_REG_WORD(&reg->nvram);
33 }
34
35 /* Lock resource */
36 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
37 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
38 udelay(5);
39 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
40 while ((data & BIT_0) == 0) {
41 /* Lock failed */
42 udelay(100);
43 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
44 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
45 udelay(5);
46 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
47 }
48 }
49}
50
51/**
fa2a1ce5 52 * qla2x00_unlock_nvram_access() -
1da177e4
LT		 53 * @ha: HA context
54 */
a824ebb3 55static void
7b867cf7 56qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
1da177e4 57{
3d71644c 58 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 59
60 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
61 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
62 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
63 }
64}
65
7b867cf7
AC		 66/**
67 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
68 * @ha: HA context
69 * @data: Serial interface selector
70 */
71static void
72qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
73{
74 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
75
76 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
77 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
78 NVRAM_DELAY();
79 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
80 NVR_WRT_ENABLE);
81 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
82 NVRAM_DELAY();
83 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
84 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
85 NVRAM_DELAY();
86}
87
88/**
89 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
90 * NVRAM.
91 * @ha: HA context
92 * @nv_cmd: NVRAM command
93 *
94 * Bit definitions for NVRAM command:
95 *
96 * Bit 26 = start bit
97 * Bit 25, 24 = opcode
98 * Bit 23-16 = address
99 * Bit 15-0 = write data
100 *
101 * Returns the word read from nvram @addr.
102 */
103static uint16_t
104qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
105{
106 uint8_t cnt;
107 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
108 uint16_t data = 0;
109 uint16_t reg_data;
110
111 /* Send command to NVRAM. */
112 nv_cmd <<= 5;
113 for (cnt = 0; cnt < 11; cnt++) {
114 if (nv_cmd & BIT_31)
115 qla2x00_nv_write(ha, NVR_DATA_OUT);
116 else
117 qla2x00_nv_write(ha, 0);
118 nv_cmd <<= 1;
119 }
120
121 /* Read data from NVRAM. */
122 for (cnt = 0; cnt < 16; cnt++) {
123 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
124 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
125 NVRAM_DELAY();
126 data <<= 1;
127 reg_data = RD_REG_WORD(&reg->nvram);
128 if (reg_data & NVR_DATA_IN)
129 data |= BIT_0;
130 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
131 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
132 NVRAM_DELAY();
133 }
134
135 /* Deselect chip. */
136 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
137 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
138 NVRAM_DELAY();
139
140 return data;
141}
142
143
1da177e4
LT		 144/**
145 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
146 * request routine to get the word from NVRAM.
147 * @ha: HA context
148 * @addr: Address in NVRAM to read
149 *
150 * Returns the word read from nvram @addr.
151 */
a824ebb3 152static uint16_t
7b867cf7 153qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
1da177e4
LT		 154{
155 uint16_t data;
156 uint32_t nv_cmd;
157
158 nv_cmd = addr << 16;
159 nv_cmd |= NV_READ_OP;
160 data = qla2x00_nvram_request(ha, nv_cmd);
161
162 return (data);
163}
164
7b867cf7
AC		 165/**
166 * qla2x00_nv_deselect() - Deselect NVRAM operations.
167 * @ha: HA context
168 */
169static void
170qla2x00_nv_deselect(struct qla_hw_data *ha)
171{
172 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
173
174 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
175 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
176 NVRAM_DELAY();
177}
178
1da177e4
LT		 179/**
180 * qla2x00_write_nvram_word() - Write NVRAM data.
181 * @ha: HA context
182 * @addr: Address in NVRAM to write
183 * @data: word to program
184 */
a824ebb3 185static void
7b867cf7 186qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
1da177e4
LT		 187{
188 int count;
189 uint16_t word;
45aeaf1e 190 uint32_t nv_cmd, wait_cnt;
3d71644c 191 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7c3df132 192 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 193
194 qla2x00_nv_write(ha, NVR_DATA_OUT);
195 qla2x00_nv_write(ha, 0);
196 qla2x00_nv_write(ha, 0);
197
198 for (word = 0; word < 8; word++)
199 qla2x00_nv_write(ha, NVR_DATA_OUT);
200
201 qla2x00_nv_deselect(ha);
202
203 /* Write data */
204 nv_cmd = (addr << 16) | NV_WRITE_OP;
205 nv_cmd |= data;
206 nv_cmd <<= 5;
207 for (count = 0; count < 27; count++) {
208 if (nv_cmd & BIT_31)
209 qla2x00_nv_write(ha, NVR_DATA_OUT);
210 else
211 qla2x00_nv_write(ha, 0);
212
213 nv_cmd <<= 1;
214 }
215
216 qla2x00_nv_deselect(ha);
217
218 /* Wait for NVRAM to become ready */
219 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 220 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 221 wait_cnt = NVR_WAIT_CNT;
1da177e4 222 do {
45aeaf1e 223 if (!--wait_cnt) {
7c3df132
SK		 224 ql_dbg(ql_dbg_user, vha, 0x708d,
225 "NVRAM didn't go ready...\n");
45aeaf1e
RA		 226 break;
227 }
1da177e4
LT		 228 NVRAM_DELAY();
229 word = RD_REG_WORD(&reg->nvram);
230 } while ((word & NVR_DATA_IN) == 0);
231
232 qla2x00_nv_deselect(ha);
233
234 /* Disable writes */
235 qla2x00_nv_write(ha, NVR_DATA_OUT);
236 for (count = 0; count < 10; count++)
237 qla2x00_nv_write(ha, 0);
238
239 qla2x00_nv_deselect(ha);
240}
241
459c5378 242static int
7b867cf7
AC		 243qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
244 uint16_t data, uint32_t tmo)
459c5378
AV		 245{
246 int ret, count;
247 uint16_t word;
248 uint32_t nv_cmd;
249 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
250
251 ret = QLA_SUCCESS;
252
253 qla2x00_nv_write(ha, NVR_DATA_OUT);
254 qla2x00_nv_write(ha, 0);
255 qla2x00_nv_write(ha, 0);
256
257 for (word = 0; word < 8; word++)
258 qla2x00_nv_write(ha, NVR_DATA_OUT);
259
260 qla2x00_nv_deselect(ha);
261
262 /* Write data */
263 nv_cmd = (addr << 16) | NV_WRITE_OP;
264 nv_cmd |= data;
265 nv_cmd <<= 5;
266 for (count = 0; count < 27; count++) {
267 if (nv_cmd & BIT_31)
268 qla2x00_nv_write(ha, NVR_DATA_OUT);
269 else
270 qla2x00_nv_write(ha, 0);
271
272 nv_cmd <<= 1;
273 }
274
275 qla2x00_nv_deselect(ha);
276
277 /* Wait for NVRAM to become ready */
278 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 279 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
459c5378
AV		 280 do {
281 NVRAM_DELAY();
282 word = RD_REG_WORD(&reg->nvram);
283 if (!--tmo) {
284 ret = QLA_FUNCTION_FAILED;
285 break;
286 }
287 } while ((word & NVR_DATA_IN) == 0);
288
289 qla2x00_nv_deselect(ha);
290
291 /* Disable writes */
292 qla2x00_nv_write(ha, NVR_DATA_OUT);
293 for (count = 0; count < 10; count++)
294 qla2x00_nv_write(ha, 0);
295
296 qla2x00_nv_deselect(ha);
297
298 return ret;
299}
300
459c5378
AV		 301/**
302 * qla2x00_clear_nvram_protection() -
303 * @ha: HA context
304 */
305static int
7b867cf7 306qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
459c5378
AV		 307{
308 int ret, stat;
309 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 310 uint32_t word, wait_cnt;
459c5378 311 uint16_t wprot, wprot_old;
7c3df132 312 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
459c5378
AV		 313
314 /* Clear NVRAM write protection. */
315 ret = QLA_FUNCTION_FAILED;
45aeaf1e
RA		 316
317 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
459c5378 319 __constant_cpu_to_le16(0x1234), 100000);
45aeaf1e
RA		 320 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
321 if (stat != QLA_SUCCESS || wprot != 0x1234) {
459c5378
AV		 322 /* Write enable. */
323 qla2x00_nv_write(ha, NVR_DATA_OUT);
324 qla2x00_nv_write(ha, 0);
325 qla2x00_nv_write(ha, 0);
326 for (word = 0; word < 8; word++)
327 qla2x00_nv_write(ha, NVR_DATA_OUT);
328
329 qla2x00_nv_deselect(ha);
330
331 /* Enable protection register. */
332 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
333 qla2x00_nv_write(ha, NVR_PR_ENABLE);
334 qla2x00_nv_write(ha, NVR_PR_ENABLE);
335 for (word = 0; word < 8; word++)
336 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
337
338 qla2x00_nv_deselect(ha);
339
340 /* Clear protection register (ffff is cleared). */
341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
343 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
344 for (word = 0; word < 8; word++)
345 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
346
347 qla2x00_nv_deselect(ha);
348
349 /* Wait for NVRAM to become ready. */
350 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 351 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 352 wait_cnt = NVR_WAIT_CNT;
459c5378 353 do {
45aeaf1e 354 if (!--wait_cnt) {
7c3df132
SK		 355 ql_dbg(ql_dbg_user, vha, 0x708e,
356 "NVRAM didn't go ready...\n");
45aeaf1e
RA		 357 break;
358 }
459c5378
AV		 359 NVRAM_DELAY();
360 word = RD_REG_WORD(&reg->nvram);
361 } while ((word & NVR_DATA_IN) == 0);
362
45aeaf1e
RA		 363 if (wait_cnt)
364 ret = QLA_SUCCESS;
459c5378 365 } else
45aeaf1e 366 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
459c5378
AV		 367
368 return ret;
369}
370
371static void
7b867cf7 372qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
459c5378
AV		 373{
374 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 375 uint32_t word, wait_cnt;
7c3df132 376 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
459c5378
AV		 377
378 if (stat != QLA_SUCCESS)
379 return;
380
381 /* Set NVRAM write protection. */
382 /* Write enable. */
383 qla2x00_nv_write(ha, NVR_DATA_OUT);
384 qla2x00_nv_write(ha, 0);
385 qla2x00_nv_write(ha, 0);
386 for (word = 0; word < 8; word++)
387 qla2x00_nv_write(ha, NVR_DATA_OUT);
388
389 qla2x00_nv_deselect(ha);
390
391 /* Enable protection register. */
392 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
393 qla2x00_nv_write(ha, NVR_PR_ENABLE);
394 qla2x00_nv_write(ha, NVR_PR_ENABLE);
395 for (word = 0; word < 8; word++)
396 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
397
398 qla2x00_nv_deselect(ha);
399
400 /* Enable protection register. */
401 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
402 qla2x00_nv_write(ha, NVR_PR_ENABLE);
403 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
404 for (word = 0; word < 8; word++)
405 qla2x00_nv_write(ha, NVR_PR_ENABLE);
406
407 qla2x00_nv_deselect(ha);
408
409 /* Wait for NVRAM to become ready. */
410 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 411 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 412 wait_cnt = NVR_WAIT_CNT;
459c5378 413 do {
45aeaf1e 414 if (!--wait_cnt) {
7c3df132
SK		 415 ql_dbg(ql_dbg_user, vha, 0x708f,
416 "NVRAM didn't go ready...\n");
45aeaf1e
RA		 417 break;
418 }
459c5378
AV		 419 NVRAM_DELAY();
420 word = RD_REG_WORD(&reg->nvram);
421 } while ((word & NVR_DATA_IN) == 0);
422}
423
424
425/*****************************************************************************/
426/* Flash Manipulation Routines */
427/*****************************************************************************/
428
429static inline uint32_t
3a03eb79 430flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
459c5378 431{
3a03eb79 432 return ha->flash_conf_off | faddr;
459c5378
AV		 433}
434
435static inline uint32_t
3a03eb79 436flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
459c5378 437{
3a03eb79 438 return ha->flash_data_off | faddr;
459c5378
AV		 439}
440
441static inline uint32_t
3a03eb79 442nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
459c5378 443{
3a03eb79 444 return ha->nvram_conf_off | naddr;
459c5378
AV		 445}
446
447static inline uint32_t
3a03eb79 448nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
459c5378 449{
3a03eb79 450 return ha->nvram_data_off | naddr;
459c5378
AV		 451}
452
e5f82ab8 453static uint32_t
7b867cf7 454qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
459c5378
AV		 455{
456 int rval;
457 uint32_t cnt, data;
458 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
459
460 WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
461 /* Wait for READ cycle to complete. */
462 rval = QLA_SUCCESS;
463 for (cnt = 3000;
464 (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
465 rval == QLA_SUCCESS; cnt--) {
466 if (cnt)
467 udelay(10);
468 else
469 rval = QLA_FUNCTION_TIMEOUT;
40a2e34a 470 cond_resched();
459c5378
AV		 471 }
472
473 /* TODO: What happens if we time out? */
474 data = 0xDEADDEAD;
475 if (rval == QLA_SUCCESS)
476 data = RD_REG_DWORD(&reg->flash_data);
477
478 return data;
479}
480
481uint32_t *
7b867cf7 482qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
459c5378
AV		 483 uint32_t dwords)
484{
485 uint32_t i;
3a03eb79
AV		 486 struct qla_hw_data *ha = vha->hw;
487
459c5378
AV		 488 /* Dword reads to flash. */
489 for (i = 0; i < dwords; i++, faddr++)
3a03eb79
AV		 490 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
491 flash_data_addr(ha, faddr)));
459c5378 492
459c5378
AV		 493 return dwptr;
494}
495
e5f82ab8 496static int
7b867cf7 497qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
459c5378
AV		 498{
499 int rval;
500 uint32_t cnt;
501 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
502
503 WRT_REG_DWORD(&reg->flash_data, data);
504 RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
505 WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
506 /* Wait for Write cycle to complete. */
507 rval = QLA_SUCCESS;
508 for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
509 rval == QLA_SUCCESS; cnt--) {
510 if (cnt)
511 udelay(10);
512 else
513 rval = QLA_FUNCTION_TIMEOUT;
40a2e34a 514 cond_resched();
459c5378
AV		 515 }
516 return rval;
517}
518
e5f82ab8 519static void
7b867cf7 520qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
459c5378
AV		 521 uint8_t *flash_id)
522{
523 uint32_t ids;
524
3a03eb79 525 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
459c5378
AV		 526 *man_id = LSB(ids);
527 *flash_id = MSB(ids);
45aeaf1e
RA		 528
529 /* Check if man_id and flash_id are valid. */
530 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
531 /* Read information using 0x9f opcode
532 * Device ID, Mfg ID would be read in the format:
533 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
534 * Example: ATMEL 0x00 01 45 1F
535 * Extract MFG and Dev ID from last two bytes.
536 */
3a03eb79 537 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
45aeaf1e
RA		 538 *man_id = LSB(ids);
539 *flash_id = MSB(ids);
540 }
459c5378
AV		 541}
542
c00d8994 543static int
7b867cf7 544qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
c00d8994
AV		 545{
546 const char *loc, *locations[] = { "DEF", "PCI" };
547 uint32_t pcihdr, pcids;
548 uint32_t *dcode;
549 uint8_t *buf, *bcode, last_image;
550 uint16_t cnt, chksum, *wptr;
551 struct qla_flt_location *fltl;
7b867cf7 552 struct qla_hw_data *ha = vha->hw;
73208dfd 553 struct req_que *req = ha->req_q_map[0];
c00d8994
AV		 554
555 /*
556 * FLT-location structure resides after the last PCI region.
557 */
558
559 /* Begin with sane defaults. */
560 loc = locations[0];
3a03eb79
AV		 561 *start = 0;
562 if (IS_QLA24XX_TYPE(ha))
563 *start = FA_FLASH_LAYOUT_ADDR_24;
564 else if (IS_QLA25XX(ha))
565 *start = FA_FLASH_LAYOUT_ADDR;
566 else if (IS_QLA81XX(ha))
567 *start = FA_FLASH_LAYOUT_ADDR_81;
7ec0effd 568 else if (IS_P3P_TYPE(ha)) {
a9083016
GM		 569 *start = FA_FLASH_LAYOUT_ADDR_82;
570 goto end;
6246b8a1
GM		 571 } else if (IS_QLA83XX(ha)) {
572 *start = FA_FLASH_LAYOUT_ADDR_83;
573 goto end;
a9083016 574 }
c00d8994 575 /* Begin with first PCI expansion ROM header. */
7b867cf7
AC		 576 buf = (uint8_t *)req->ring;
577 dcode = (uint32_t *)req->ring;
c00d8994
AV		 578 pcihdr = 0;
579 last_image = 1;
580 do {
581 /* Verify PCI expansion ROM header. */
7b867cf7 582 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
c00d8994
AV		 583 bcode = buf + (pcihdr % 4);
584 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
585 goto end;
586
587 /* Locate PCI data structure. */
588 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
7b867cf7 589 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
c00d8994
AV		 590 bcode = buf + (pcihdr % 4);
591
592 /* Validate signature of PCI data structure. */
593 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
594 bcode[0x2] != 'I' || bcode[0x3] != 'R')
595 goto end;
596
597 last_image = bcode[0x15] & BIT_7;
598
599 /* Locate next PCI expansion ROM. */
600 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
601 } while (!last_image);
602
603 /* Now verify FLT-location structure. */
7b867cf7
AC		 604 fltl = (struct qla_flt_location *)req->ring;
605 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
c00d8994
AV		 606 sizeof(struct qla_flt_location) >> 2);
607 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
608 fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
609 goto end;
610
7b867cf7 611 wptr = (uint16_t *)req->ring;
c00d8994
AV		 612 cnt = sizeof(struct qla_flt_location) >> 1;
613 for (chksum = 0; cnt; cnt--)
614 chksum += le16_to_cpu(*wptr++);
615 if (chksum) {
7c3df132 616 ql_log(ql_log_fatal, vha, 0x0045,
c00d8994 617 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
7c3df132
SK		 618 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e,
619 buf, sizeof(struct qla_flt_location));
c00d8994
AV		 620 return QLA_FUNCTION_FAILED;
621 }
622
623 /* Good data. Use specified location. */
624 loc = locations[1];
79c13a74
HZ		 625 *start = (le16_to_cpu(fltl->start_hi) << 16 |
626 le16_to_cpu(fltl->start_lo)) >> 2;
c00d8994 627end:
7c3df132
SK		 628 ql_dbg(ql_dbg_init, vha, 0x0046,
629 "FLTL[%s] = 0x%x.\n",
630 loc, *start);
c00d8994
AV		 631 return QLA_SUCCESS;
632}
633
634static void
7b867cf7 635qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
c00d8994
AV		 636{
637 const char *loc, *locations[] = { "DEF", "FLT" };
3a03eb79
AV		 638 const uint32_t def_fw[] =
639 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
640 const uint32_t def_boot[] =
641 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
642 const uint32_t def_vpd_nvram[] =
643 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
3d79038f
AV		 644 const uint32_t def_vpd0[] =
645 { 0, 0, FA_VPD0_ADDR_81 };
646 const uint32_t def_vpd1[] =
647 { 0, 0, FA_VPD1_ADDR_81 };
648 const uint32_t def_nvram0[] =
649 { 0, 0, FA_NVRAM0_ADDR_81 };
650 const uint32_t def_nvram1[] =
651 { 0, 0, FA_NVRAM1_ADDR_81 };
3a03eb79
AV		 652 const uint32_t def_fdt[] =
653 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
654 FA_FLASH_DESCR_ADDR_81 };
655 const uint32_t def_npiv_conf0[] =
656 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
657 FA_NPIV_CONF0_ADDR_81 };
658 const uint32_t def_npiv_conf1[] =
659 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
660 FA_NPIV_CONF1_ADDR_81 };
09ff701a
SR		 661 const uint32_t fcp_prio_cfg0[] =
662 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25,
663 0 };
664 const uint32_t fcp_prio_cfg1[] =
665 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25,
666 0 };
3a03eb79 667 uint32_t def;
c00d8994
AV		 668 uint16_t *wptr;
669 uint16_t cnt, chksum;
670 uint32_t start;
671 struct qla_flt_header *flt;
672 struct qla_flt_region *region;
7b867cf7 673 struct qla_hw_data *ha = vha->hw;
73208dfd 674 struct req_que *req = ha->req_q_map[0];
c00d8994 675
2f0f3f4f
MI		 676 def = 0;
677 if (IS_QLA25XX(ha))
678 def = 1;
679 else if (IS_QLA81XX(ha))
680 def = 2;
ff8073ff
AV		 681
682 /* Assign FCP prio region since older adapters may not have FLT, or
683 FCP prio region in it's FLT.
684 */
685 ha->flt_region_fcp_prio = ha->flags.port0 ?
686 fcp_prio_cfg0[def] : fcp_prio_cfg1[def];
687
c00d8994 688 ha->flt_region_flt = flt_addr;
7b867cf7
AC		 689 wptr = (uint16_t *)req->ring;
690 flt = (struct qla_flt_header *)req->ring;
c00d8994 691 region = (struct qla_flt_region *)&flt[1];
7b867cf7 692 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
c00d8994
AV		 693 flt_addr << 2, OPTROM_BURST_SIZE);
694 if (*wptr == __constant_cpu_to_le16(0xffff))
695 goto no_flash_data;
696 if (flt->version != __constant_cpu_to_le16(1)) {
7c3df132
SK		 697 ql_log(ql_log_warn, vha, 0x0047,
698 "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
c00d8994 699 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
7c3df132 700 le16_to_cpu(flt->checksum));
c00d8994
AV		 701 goto no_flash_data;
702 }
703
704 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
705 for (chksum = 0; cnt; cnt--)
706 chksum += le16_to_cpu(*wptr++);
707 if (chksum) {
7c3df132
SK		 708 ql_log(ql_log_fatal, vha, 0x0048,
709 "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
c00d8994 710 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
7c3df132 711 le16_to_cpu(flt->checksum));
c00d8994
AV		 712 goto no_flash_data;
713 }
714
715 loc = locations[1];
716 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
717 for ( ; cnt; cnt--, region++) {
718 /* Store addresses as DWORD offsets. */
719 start = le32_to_cpu(region->start) >> 2;
7c3df132
SK		 720 ql_dbg(ql_dbg_init, vha, 0x0049,
721 "FLT[%02x]: start=0x%x "
7ec0effd 722 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code) & 0xff,
7c3df132
SK		 723 start, le32_to_cpu(region->end) >> 2,
724 le32_to_cpu(region->size));
c00d8994 725
9088608e 726 switch (le32_to_cpu(region->code) & 0xff) {
6246b8a1
GM		 727 case FLT_REG_FCOE_FW:
728 if (!IS_QLA8031(ha))
729 break;
730 ha->flt_region_fw = start;
731 break;
c00d8994 732 case FLT_REG_FW:
6246b8a1
GM		 733 if (IS_QLA8031(ha))
734 break;
c00d8994
AV		 735 ha->flt_region_fw = start;
736 break;
737 case FLT_REG_BOOT_CODE:
738 ha->flt_region_boot = start;
739 break;
740 case FLT_REG_VPD_0:
6246b8a1
GM		 741 if (IS_QLA8031(ha))
742 break;
c00d8994 743 ha->flt_region_vpd_nvram = start;
7ec0effd 744 if (IS_P3P_TYPE(ha))
a9083016 745 break;
e5b68a61 746 if (ha->flags.port0)
3d79038f
AV		 747 ha->flt_region_vpd = start;
748 break;
749 case FLT_REG_VPD_1:
7ec0effd 750 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
a9083016 751 break;
e5b68a61 752 if (!ha->flags.port0)
3d79038f
AV		 753 ha->flt_region_vpd = start;
754 break;
755 case FLT_REG_NVRAM_0:
6246b8a1
GM		 756 if (IS_QLA8031(ha))
757 break;
e5b68a61 758 if (ha->flags.port0)
3d79038f
AV		 759 ha->flt_region_nvram = start;
760 break;
761 case FLT_REG_NVRAM_1:
6246b8a1
GM		 762 if (IS_QLA8031(ha))
763 break;
e5b68a61 764 if (!ha->flags.port0)
3d79038f 765 ha->flt_region_nvram = start;
c00d8994
AV		 766 break;
767 case FLT_REG_FDT:
768 ha->flt_region_fdt = start;
769 break;
272976ca 770 case FLT_REG_NPIV_CONF_0:
e5b68a61 771 if (ha->flags.port0)
272976ca
AV		 772 ha->flt_region_npiv_conf = start;
773 break;
774 case FLT_REG_NPIV_CONF_1:
e5b68a61 775 if (!ha->flags.port0)
272976ca
AV		 776 ha->flt_region_npiv_conf = start;
777 break;
cbc8eb67
AV		 778 case FLT_REG_GOLD_FW:
779 ha->flt_region_gold_fw = start;
780 break;
09ff701a 781 case FLT_REG_FCP_PRIO_0:
bfdaa761 782 if (ha->flags.port0)
09ff701a
SR		 783 ha->flt_region_fcp_prio = start;
784 break;
785 case FLT_REG_FCP_PRIO_1:
bfdaa761 786 if (!ha->flags.port0)
09ff701a
SR		 787 ha->flt_region_fcp_prio = start;
788 break;
a9083016
GM		 789 case FLT_REG_BOOT_CODE_82XX:
790 ha->flt_region_boot = start;
791 break;
7ec0effd
AD		 792 case FLT_REG_BOOT_CODE_8044:
793 if (IS_QLA8044(ha))
794 ha->flt_region_boot = start;
795 break;
a9083016
GM		 796 case FLT_REG_FW_82XX:
797 ha->flt_region_fw = start;
798 break;
7ec0effd
AD		 799 case FLT_REG_CNA_FW:
800 if (IS_CNA_CAPABLE(ha))
801 ha->flt_region_fw = start;
802 break;
a9083016
GM		 803 case FLT_REG_GOLD_FW_82XX:
804 ha->flt_region_gold_fw = start;
805 break;
806 case FLT_REG_BOOTLOAD_82XX:
807 ha->flt_region_bootload = start;
808 break;
a865c50a
SK		 809 case FLT_REG_VPD_8XXX:
810 if (IS_CNA_CAPABLE(ha))
6246b8a1
GM		 811 ha->flt_region_vpd = start;
812 break;
813 case FLT_REG_FCOE_NVRAM_0:
7ec0effd 814 if (!(IS_QLA8031(ha) || IS_QLA8044(ha)))
6246b8a1
GM		 815 break;
816 if (ha->flags.port0)
817 ha->flt_region_nvram = start;
818 break;
819 case FLT_REG_FCOE_NVRAM_1:
7ec0effd 820 if (!(IS_QLA8031(ha) || IS_QLA8044(ha)))
6246b8a1
GM		 821 break;
822 if (!ha->flags.port0)
823 ha->flt_region_nvram = start;
824 break;
c00d8994
AV		 825 }
826 }
827 goto done;
828
829no_flash_data:
830 /* Use hardcoded defaults. */
831 loc = locations[0];
3a03eb79
AV		 832 ha->flt_region_fw = def_fw[def];
833 ha->flt_region_boot = def_boot[def];
834 ha->flt_region_vpd_nvram = def_vpd_nvram[def];
e5b68a61 835 ha->flt_region_vpd = ha->flags.port0 ?
09ff701a 836 def_vpd0[def] : def_vpd1[def];
e5b68a61 837 ha->flt_region_nvram = ha->flags.port0 ?
09ff701a 838 def_nvram0[def] : def_nvram1[def];
3a03eb79 839 ha->flt_region_fdt = def_fdt[def];
e5b68a61 840 ha->flt_region_npiv_conf = ha->flags.port0 ?
09ff701a 841 def_npiv_conf0[def] : def_npiv_conf1[def];
c00d8994 842done:
7c3df132 843 ql_dbg(ql_dbg_init, vha, 0x004a,
6246b8a1
GM		 844 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x "
845 "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n",
846 loc, ha->flt_region_boot, ha->flt_region_fw,
847 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
848 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf,
849 ha->flt_region_fcp_prio);
c00d8994
AV		 850}
851
852static void
7b867cf7 853qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
7d232c74 854{
821b3996 855#define FLASH_BLK_SIZE_4K 0x1000
7d232c74
AV		 856#define FLASH_BLK_SIZE_32K 0x8000
857#define FLASH_BLK_SIZE_64K 0x10000
c00d8994 858 const char *loc, *locations[] = { "MID", "FDT" };
7d232c74
AV		 859 uint16_t cnt, chksum;
860 uint16_t *wptr;
861 struct qla_fdt_layout *fdt;
862 uint8_t man_id, flash_id;
a9083016 863 uint16_t mid = 0, fid = 0;
7b867cf7 864 struct qla_hw_data *ha = vha->hw;
73208dfd 865 struct req_que *req = ha->req_q_map[0];
7d232c74 866
7b867cf7
AC		 867 wptr = (uint16_t *)req->ring;
868 fdt = (struct qla_fdt_layout *)req->ring;
869 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
c00d8994 870 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
7d232c74
AV		 871 if (*wptr == __constant_cpu_to_le16(0xffff))
872 goto no_flash_data;
873 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
874 fdt->sig[3] != 'D')
875 goto no_flash_data;
876
877 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
878 cnt++)
879 chksum += le16_to_cpu(*wptr++);
880 if (chksum) {
7c3df132
SK		 881 ql_dbg(ql_dbg_init, vha, 0x004c,
882 "Inconsistent FDT detected:"
883 " checksum=0x%x id=%c version0x%x.\n", chksum,
884 fdt->sig[0], le16_to_cpu(fdt->version));
885 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113,
886 (uint8_t *)fdt, sizeof(*fdt));
7d232c74
AV		 887 goto no_flash_data;
888 }
889
c00d8994
AV		 890 loc = locations[1];
891 mid = le16_to_cpu(fdt->man_id);
892 fid = le16_to_cpu(fdt->id);
7d232c74 893 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
7ec0effd
AD		 894 ha->fdt_wrt_enable = fdt->wrt_enable_bits;
895 ha->fdt_wrt_sts_reg_cmd = fdt->wrt_sts_reg_cmd;
896 if (IS_QLA8044(ha))
897 ha->fdt_erase_cmd = fdt->erase_cmd;
898 else
899 ha->fdt_erase_cmd =
900 flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
7d232c74
AV		 901 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
902 if (fdt->unprotect_sec_cmd) {
3a03eb79 903 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
7d232c74
AV		 904 fdt->unprotect_sec_cmd);
905 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
3a03eb79
AV		 906 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
907 flash_conf_addr(ha, 0x0336);
7d232c74 908 }
c00d8994 909 goto done;
7d232c74 910no_flash_data:
c00d8994 911 loc = locations[0];
7ec0effd 912 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 913 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
914 goto done;
915 }
7d232c74 916 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
c00d8994
AV		 917 mid = man_id;
918 fid = flash_id;
7d232c74 919 ha->fdt_wrt_disable = 0x9c;
3a03eb79 920 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
7d232c74
AV		 921 switch (man_id) {
922 case 0xbf: /* STT flash. */
923 if (flash_id == 0x8e)
924 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
925 else
926 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
927
928 if (flash_id == 0x80)
3a03eb79 929 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
7d232c74
AV		 930 break;
931 case 0x13: /* ST M25P80. */
932 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
933 break;
934 case 0x1f: /* Atmel 26DF081A. */
821b3996 935 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
3a03eb79
AV		 936 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
937 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
938 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
7d232c74
AV		 939 break;
940 default:
941 /* Default to 64 kb sector size. */
942 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
943 break;
944 }
c00d8994 945done:
7c3df132 946 ql_dbg(ql_dbg_init, vha, 0x004d,
d8424f68
JP		 947 "FDT[%s]: (0x%x/0x%x) erase=0x%x "
948 "pr=%x wrtd=0x%x blk=0x%x.\n",
949 loc, mid, fid,
7d232c74 950 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
7c3df132
SK		 951 ha->fdt_wrt_disable, ha->fdt_block_size);
952
7d232c74
AV		 953}
954
a9083016
GM		 955static void
956qla2xxx_get_idc_param(scsi_qla_host_t *vha)
957{
958#define QLA82XX_IDC_PARAM_ADDR 0x003e885c
959 uint32_t *wptr;
960 struct qla_hw_data *ha = vha->hw;
961 struct req_que *req = ha->req_q_map[0];
962
7ec0effd 963 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 964 return;
965
966 wptr = (uint32_t *)req->ring;
967 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
968 QLA82XX_IDC_PARAM_ADDR , 8);
969
970 if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
7d613ac6
SV		 971 ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT;
972 ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT;
a9083016 973 } else {
7d613ac6
SV		 974 ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr++);
975 ha->fcoe_reset_timeout = le32_to_cpu(*wptr);
a9083016 976 }
7c3df132 977 ql_dbg(ql_dbg_init, vha, 0x004e,
7d613ac6
SV		 978 "fcoe_dev_init_timeout=%d "
979 "fcoe_reset_timeout=%d.\n", ha->fcoe_dev_init_timeout,
980 ha->fcoe_reset_timeout);
a9083016
GM		 981 return;
982}
983
c00d8994 984int
7b867cf7 985qla2xxx_get_flash_info(scsi_qla_host_t *vha)
c00d8994
AV		 986{
987 int ret;
988 uint32_t flt_addr;
7b867cf7 989 struct qla_hw_data *ha = vha->hw;
c00d8994 990
6246b8a1
GM		 991 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
992 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
c00d8994
AV		 993 return QLA_SUCCESS;
994
7b867cf7 995 ret = qla2xxx_find_flt_start(vha, &flt_addr);
c00d8994
AV		 996 if (ret != QLA_SUCCESS)
997 return ret;
998
7b867cf7
AC		 999 qla2xxx_get_flt_info(vha, flt_addr);
1000 qla2xxx_get_fdt_info(vha);
a9083016 1001 qla2xxx_get_idc_param(vha);
c00d8994
AV		 1002
1003 return QLA_SUCCESS;
1004}
1005
272976ca 1006void
7b867cf7 1007qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
272976ca
AV		 1008{
1009#define NPIV_CONFIG_SIZE (16*1024)
1010 void *data;
1011 uint16_t *wptr;
1012 uint16_t cnt, chksum;
73208dfd 1013 int i;
272976ca
AV		 1014 struct qla_npiv_header hdr;
1015 struct qla_npiv_entry *entry;
7b867cf7 1016 struct qla_hw_data *ha = vha->hw;
272976ca 1017
6246b8a1
GM		 1018 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
1019 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
272976ca
AV		 1020 return;
1021
7d613ac6 1022 if (ha->flags.nic_core_reset_hdlr_active)
a49393f2
GM		 1023 return;
1024
7ec0effd
AD		 1025 if (IS_QLA8044(ha))
1026 return;
1027
7b867cf7 1028 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
272976ca
AV		 1029 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
1030 if (hdr.version == __constant_cpu_to_le16(0xffff))
1031 return;
1032 if (hdr.version != __constant_cpu_to_le16(1)) {
7c3df132
SK		 1033 ql_dbg(ql_dbg_user, vha, 0x7090,
1034 "Unsupported NPIV-Config "
272976ca
AV		 1035 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1036 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
7c3df132 1037 le16_to_cpu(hdr.checksum));
272976ca
AV		 1038 return;
1039 }
1040
1041 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
1042 if (!data) {
7c3df132
SK		 1043 ql_log(ql_log_warn, vha, 0x7091,
1044 "Unable to allocate memory for data.\n");
272976ca
AV		 1045 return;
1046 }
1047
7b867cf7 1048 ha->isp_ops->read_optrom(vha, (uint8_t *)data,
272976ca
AV		 1049 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
1050
1051 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
1052 sizeof(struct qla_npiv_entry)) >> 1;
1053 for (wptr = data, chksum = 0; cnt; cnt--)
1054 chksum += le16_to_cpu(*wptr++);
1055 if (chksum) {
7c3df132
SK		 1056 ql_dbg(ql_dbg_user, vha, 0x7092,
1057 "Inconsistent NPIV-Config "
272976ca
AV		 1058 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1059 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
7c3df132 1060 le16_to_cpu(hdr.checksum));
272976ca
AV		 1061 goto done;
1062 }
1063
1064 entry = data + sizeof(struct qla_npiv_header);
1065 cnt = le16_to_cpu(hdr.entries);
73208dfd 1066 for (i = 0; cnt; cnt--, entry++, i++) {
272976ca
AV		 1067 uint16_t flags;
1068 struct fc_vport_identifiers vid;
1069 struct fc_vport *vport;
1070
40859ae5
AC		 1071 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
1072
272976ca
AV		 1073 flags = le16_to_cpu(entry->flags);
1074 if (flags == 0xffff)
1075 continue;
1076 if ((flags & BIT_0) == 0)
1077 continue;
1078
1079 memset(&vid, 0, sizeof(vid));
1080 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
1081 vid.vport_type = FC_PORTTYPE_NPIV;
1082 vid.disable = false;
1083 vid.port_name = wwn_to_u64(entry->port_name);
1084 vid.node_name = wwn_to_u64(entry->node_name);
1085
7c3df132
SK		 1086 ql_dbg(ql_dbg_user, vha, 0x7093,
1087 "NPIV[%02x]: wwpn=%llx "
1088 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
1089 (unsigned long long)vid.port_name,
1090 (unsigned long long)vid.node_name,
1091 le16_to_cpu(entry->vf_id),
1092 entry->q_qos, entry->f_qos);
73208dfd
AC		 1093
1094 if (i < QLA_PRECONFIG_VPORTS) {
1095 vport = fc_vport_create(vha->host, 0, &vid);
1096 if (!vport)
7c3df132
SK		 1097 ql_log(ql_log_warn, vha, 0x7094,
1098 "NPIV-Config Failed to create vport [%02x]: "
1099 "wwpn=%llx wwnn=%llx.\n", cnt,
1100 (unsigned long long)vid.port_name,
1101 (unsigned long long)vid.node_name);
73208dfd 1102 }
272976ca
AV		 1103 }
1104done:
1105 kfree(data);
1106}
1107
1d2874de
JC		 1108static int
1109qla24xx_unprotect_flash(scsi_qla_host_t *vha)
cb8dacbf 1110{
1d2874de 1111 struct qla_hw_data *ha = vha->hw;
cb8dacbf
AV		 1112 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1113
1d2874de
JC		 1114 if (ha->flags.fac_supported)
1115 return qla81xx_fac_do_write_enable(vha, 1);
1116
cb8dacbf
AV		 1117 /* Enable flash write. */
1118 WRT_REG_DWORD(&reg->ctrl_status,
1119 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1120 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1121
7d232c74 1122 if (!ha->fdt_wrt_disable)
1d2874de 1123 goto done;
7d232c74 1124
b872ca40 1125 /* Disable flash write-protection, first clear SR protection bit */
3a03eb79 1126 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
b872ca40 1127 /* Then write zero again to clear remaining SR bits.*/
3a03eb79 1128 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1d2874de
JC		 1129done:
1130 return QLA_SUCCESS;
cb8dacbf
AV		 1131}
1132
1d2874de
JC		 1133static int
1134qla24xx_protect_flash(scsi_qla_host_t *vha)
cb8dacbf
AV		 1135{
1136 uint32_t cnt;
1d2874de 1137 struct qla_hw_data *ha = vha->hw;
cb8dacbf
AV		 1138 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1139
1d2874de
JC		 1140 if (ha->flags.fac_supported)
1141 return qla81xx_fac_do_write_enable(vha, 0);
1142
7d232c74
AV		 1143 if (!ha->fdt_wrt_disable)
1144 goto skip_wrt_protect;
1145
cb8dacbf 1146 /* Enable flash write-protection and wait for completion. */
3a03eb79 1147 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
7d232c74 1148 ha->fdt_wrt_disable);
cb8dacbf 1149 for (cnt = 300; cnt &&
3a03eb79 1150 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
cb8dacbf
AV		 1151 cnt--) {
1152 udelay(10);
1153 }
1154
7d232c74 1155skip_wrt_protect:
cb8dacbf
AV		 1156 /* Disable flash write. */
1157 WRT_REG_DWORD(&reg->ctrl_status,
1158 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1159 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1d2874de
JC		 1160
1161 return QLA_SUCCESS;
1162}
1163
1164static int
1165qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1166{
1167 struct qla_hw_data *ha = vha->hw;
1168 uint32_t start, finish;
1169
1170 if (ha->flags.fac_supported) {
1171 start = fdata >> 2;
1172 finish = start + (ha->fdt_block_size >> 2) - 1;
1173 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1174 start), flash_data_addr(ha, finish));
1175 }
1176
1177 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1178 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1179 ((fdata >> 16) & 0xff));
cb8dacbf
AV		 1180}
1181
e5f82ab8 1182static int
7b867cf7 1183qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
459c5378
AV		 1184 uint32_t dwords)
1185{
1186 int ret;
7c283177 1187 uint32_t liter;
7d232c74 1188 uint32_t sec_mask, rest_addr;
85d0acbb 1189 uint32_t fdata;
338c9161
AV		 1190 dma_addr_t optrom_dma;
1191 void *optrom = NULL;
7b867cf7 1192 struct qla_hw_data *ha = vha->hw;
459c5378 1193
338c9161 1194 /* Prepare burst-capable write on supported ISPs. */
6246b8a1
GM		 1195 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha)) &&
1196 !(faddr & 0xfff) && dwords > OPTROM_BURST_DWORDS) {
338c9161
AV		 1197 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1198 &optrom_dma, GFP_KERNEL);
1199 if (!optrom) {
7c3df132
SK		 1200 ql_log(ql_log_warn, vha, 0x7095,
1201 "Unable to allocate "
1202 "memory for optrom burst write (%x KB).\n",
1203 OPTROM_BURST_SIZE / 1024);
338c9161
AV		 1204 }
1205 }
1206
7d232c74 1207 rest_addr = (ha->fdt_block_size >> 2) - 1;
85d0acbb 1208 sec_mask = ~rest_addr;
459c5378 1209
1d2874de
JC		 1210 ret = qla24xx_unprotect_flash(vha);
1211 if (ret != QLA_SUCCESS) {
7c3df132 1212 ql_log(ql_log_warn, vha, 0x7096,
1d2874de
JC		 1213 "Unable to unprotect flash for update.\n");
1214 goto done;
1215 }
459c5378 1216
338c9161 1217 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
85d0acbb 1218 fdata = (faddr & sec_mask) << 2;
45aeaf1e 1219
338c9161 1220 /* Are we at the beginning of a sector? */
85d0acbb 1221 if ((faddr & rest_addr) == 0) {
7d232c74
AV		 1222 /* Do sector unprotect. */
1223 if (ha->fdt_unprotect_sec_cmd)
338c9161 1224 qla24xx_write_flash_dword(ha,
7d232c74 1225 ha->fdt_unprotect_sec_cmd,
338c9161 1226 (fdata & 0xff00) | ((fdata << 16) &
459c5378 1227 0xff0000) | ((fdata >> 16) & 0xff));
1d2874de 1228 ret = qla24xx_erase_sector(vha, fdata);
338c9161 1229 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1230 ql_dbg(ql_dbg_user, vha, 0x7007,
1231 "Unable to erase erase sector: address=%x.\n",
1232 faddr);
338c9161 1233 break;
459c5378 1234 }
338c9161
AV		 1235 }
1236
1237 /* Go with burst-write. */
94d6a2b3 1238 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
338c9161 1239 /* Copy data to DMA'ble buffer. */
7c283177 1240 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
338c9161 1241
7b867cf7 1242 ret = qla2x00_load_ram(vha, optrom_dma,
3a03eb79 1243 flash_data_addr(ha, faddr),
338c9161 1244 OPTROM_BURST_DWORDS);
459c5378 1245 if (ret != QLA_SUCCESS) {
7c3df132 1246 ql_log(ql_log_warn, vha, 0x7097,
338c9161
AV		 1247 "Unable to burst-write optrom segment "
1248 "(%x/%x/%llx).\n", ret,
3a03eb79 1249 flash_data_addr(ha, faddr),
875baf3c 1250 (unsigned long long)optrom_dma);
7c3df132 1251 ql_log(ql_log_warn, vha, 0x7098,
338c9161
AV		 1252 "Reverting to slow-write.\n");
1253
1254 dma_free_coherent(&ha->pdev->dev,
1255 OPTROM_BURST_SIZE, optrom, optrom_dma);
1256 optrom = NULL;
1257 } else {
1258 liter += OPTROM_BURST_DWORDS - 1;
1259 faddr += OPTROM_BURST_DWORDS - 1;
1260 dwptr += OPTROM_BURST_DWORDS - 1;
1261 continue;
459c5378 1262 }
338c9161 1263 }
45aeaf1e 1264
338c9161 1265 ret = qla24xx_write_flash_dword(ha,
3a03eb79 1266 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
338c9161 1267 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1268 ql_dbg(ql_dbg_user, vha, 0x7006,
1269 "Unable to program flash address=%x data=%x.\n",
1270 faddr, *dwptr);
338c9161 1271 break;
459c5378 1272 }
338c9161 1273
7d232c74
AV		 1274 /* Do sector protect. */
1275 if (ha->fdt_unprotect_sec_cmd &&
338c9161
AV		 1276 ((faddr & rest_addr) == rest_addr))
1277 qla24xx_write_flash_dword(ha,
7d232c74 1278 ha->fdt_protect_sec_cmd,
338c9161
AV		 1279 (fdata & 0xff00) | ((fdata << 16) &
1280 0xff0000) | ((fdata >> 16) & 0xff));
1281 }
459c5378 1282
1d2874de
JC		 1283 ret = qla24xx_protect_flash(vha);
1284 if (ret != QLA_SUCCESS)
7c3df132 1285 ql_log(ql_log_warn, vha, 0x7099,
1d2874de
JC		 1286 "Unable to protect flash after update.\n");
1287done:
338c9161
AV		 1288 if (optrom)
1289 dma_free_coherent(&ha->pdev->dev,
1290 OPTROM_BURST_SIZE, optrom, optrom_dma);
1291
459c5378
AV		 1292 return ret;
1293}
1294
1295uint8_t *
7b867cf7 1296qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1297 uint32_t bytes)
1298{
1299 uint32_t i;
1300 uint16_t *wptr;
7b867cf7 1301 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1302
1303 /* Word reads to NVRAM via registers. */
1304 wptr = (uint16_t *)buf;
1305 qla2x00_lock_nvram_access(ha);
1306 for (i = 0; i < bytes >> 1; i++, naddr++)
1307 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1308 naddr));
1309 qla2x00_unlock_nvram_access(ha);
1310
1311 return buf;
1312}
1313
1314uint8_t *
7b867cf7 1315qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1316 uint32_t bytes)
1317{
1318 uint32_t i;
1319 uint32_t *dwptr;
3a03eb79 1320 struct qla_hw_data *ha = vha->hw;
459c5378 1321
7ec0effd 1322 if (IS_P3P_TYPE(ha))
a9083016
GM		 1323 return buf;
1324
459c5378
AV		 1325 /* Dword reads to flash. */
1326 dwptr = (uint32_t *)buf;
1327 for (i = 0; i < bytes >> 2; i++, naddr++)
3a03eb79
AV		 1328 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1329 nvram_data_addr(ha, naddr)));
459c5378 1330
459c5378
AV		 1331 return buf;
1332}
1333
1334int
7b867cf7 1335qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1336 uint32_t bytes)
1337{
1338 int ret, stat;
1339 uint32_t i;
1340 uint16_t *wptr;
2c96d8d0 1341 unsigned long flags;
7b867cf7 1342 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1343
1344 ret = QLA_SUCCESS;
1345
2c96d8d0 1346 spin_lock_irqsave(&ha->hardware_lock, flags);
459c5378
AV		 1347 qla2x00_lock_nvram_access(ha);
1348
1349 /* Disable NVRAM write-protection. */
1350 stat = qla2x00_clear_nvram_protection(ha);
1351
1352 wptr = (uint16_t *)buf;
1353 for (i = 0; i < bytes >> 1; i++, naddr++) {
1354 qla2x00_write_nvram_word(ha, naddr,
1355 cpu_to_le16(*wptr));
1356 wptr++;
1357 }
1358
1359 /* Enable NVRAM write-protection. */
1360 qla2x00_set_nvram_protection(ha, stat);
1361
1362 qla2x00_unlock_nvram_access(ha);
2c96d8d0 1363 spin_unlock_irqrestore(&ha->hardware_lock, flags);
459c5378
AV		 1364
1365 return ret;
1366}
1367
1368int
7b867cf7 1369qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1370 uint32_t bytes)
1371{
1372 int ret;
1373 uint32_t i;
1374 uint32_t *dwptr;
7b867cf7 1375 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1376 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1377
1378 ret = QLA_SUCCESS;
1379
7ec0effd 1380 if (IS_P3P_TYPE(ha))
a9083016
GM		 1381 return ret;
1382
459c5378
AV		 1383 /* Enable flash write. */
1384 WRT_REG_DWORD(&reg->ctrl_status,
1385 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1386 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1387
1388 /* Disable NVRAM write-protection. */
3a03eb79
AV		 1389 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1390 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
459c5378
AV		 1391
1392 /* Dword writes to flash. */
1393 dwptr = (uint32_t *)buf;
1394 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1395 ret = qla24xx_write_flash_dword(ha,
3a03eb79 1396 nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
459c5378 1397 if (ret != QLA_SUCCESS) {
7c3df132 1398 ql_dbg(ql_dbg_user, vha, 0x709a,
7640335e 1399 "Unable to program nvram address=%x data=%x.\n",
7c3df132 1400 naddr, *dwptr);
459c5378
AV		 1401 break;
1402 }
1403 }
1404
1405 /* Enable NVRAM write-protection. */
3a03eb79 1406 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
459c5378
AV		 1407
1408 /* Disable flash write. */
1409 WRT_REG_DWORD(&reg->ctrl_status,
1410 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1411 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1412
459c5378
AV		 1413 return ret;
1414}
f6df144c 1415
c3a2f0df 1416uint8_t *
7b867cf7 1417qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
c3a2f0df
AV		 1418 uint32_t bytes)
1419{
1420 uint32_t i;
1421 uint32_t *dwptr;
7b867cf7 1422 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1423
1424 /* Dword reads to flash. */
1425 dwptr = (uint32_t *)buf;
1426 for (i = 0; i < bytes >> 2; i++, naddr++)
1427 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
3a03eb79 1428 flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
c3a2f0df
AV		 1429
1430 return buf;
1431}
1432
1433int
7b867cf7 1434qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
c3a2f0df
AV		 1435 uint32_t bytes)
1436{
7b867cf7 1437 struct qla_hw_data *ha = vha->hw;
2c96d8d0
AV		 1438#define RMW_BUFFER_SIZE (64 * 1024)
1439 uint8_t *dbuf;
1440
1441 dbuf = vmalloc(RMW_BUFFER_SIZE);
1442 if (!dbuf)
1443 return QLA_MEMORY_ALLOC_FAILED;
7b867cf7 1444 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
2c96d8d0
AV		 1445 RMW_BUFFER_SIZE);
1446 memcpy(dbuf + (naddr << 2), buf, bytes);
7b867cf7 1447 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
2c96d8d0
AV		 1448 RMW_BUFFER_SIZE);
1449 vfree(dbuf);
1450
1451 return QLA_SUCCESS;
c3a2f0df 1452}
f6df144c 1453
1454static inline void
7b867cf7 1455qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
f6df144c 1456{
1457 if (IS_QLA2322(ha)) {
1458 /* Flip all colors. */
1459 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1460 /* Turn off. */
1461 ha->beacon_color_state = 0;
1462 *pflags = GPIO_LED_ALL_OFF;
1463 } else {
1464 /* Turn on. */
1465 ha->beacon_color_state = QLA_LED_ALL_ON;
1466 *pflags = GPIO_LED_RGA_ON;
1467 }
1468 } else {
1469 /* Flip green led only. */
1470 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1471 /* Turn off. */
1472 ha->beacon_color_state = 0;
1473 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1474 } else {
1475 /* Turn on. */
1476 ha->beacon_color_state = QLA_LED_GRN_ON;
1477 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1478 }
1479 }
1480}
1481
948882f6
AV		 1482#define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1483
f6df144c 1484void
7b867cf7 1485qla2x00_beacon_blink(struct scsi_qla_host *vha)
f6df144c 1486{
1487 uint16_t gpio_enable;
1488 uint16_t gpio_data;
1489 uint16_t led_color = 0;
1490 unsigned long flags;
7b867cf7 1491 struct qla_hw_data *ha = vha->hw;
f6df144c 1492 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1493
7ec0effd 1494 if (IS_P3P_TYPE(ha))
a9083016
GM		 1495 return;
1496
f6df144c 1497 spin_lock_irqsave(&ha->hardware_lock, flags);
1498
1499 /* Save the Original GPIOE. */
1500 if (ha->pio_address) {
948882f6
AV		 1501 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1502 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
f6df144c 1503 } else {
1504 gpio_enable = RD_REG_WORD(&reg->gpioe);
1505 gpio_data = RD_REG_WORD(&reg->gpiod);
1506 }
1507
1508 /* Set the modified gpio_enable values */
1509 gpio_enable |= GPIO_LED_MASK;
1510
1511 if (ha->pio_address) {
948882f6 1512 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
f6df144c 1513 } else {
1514 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1515 RD_REG_WORD(&reg->gpioe);
1516 }
1517
1518 qla2x00_flip_colors(ha, &led_color);
1519
1520 /* Clear out any previously set LED color. */
1521 gpio_data &= ~GPIO_LED_MASK;
1522
1523 /* Set the new input LED color to GPIOD. */
1524 gpio_data |= led_color;
1525
1526 /* Set the modified gpio_data values */
1527 if (ha->pio_address) {
948882f6 1528 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
f6df144c 1529 } else {
1530 WRT_REG_WORD(&reg->gpiod, gpio_data);
1531 RD_REG_WORD(&reg->gpiod);
1532 }
1533
1534 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1535}
1536
1537int
7b867cf7 1538qla2x00_beacon_on(struct scsi_qla_host *vha)
f6df144c 1539{
1540 uint16_t gpio_enable;
1541 uint16_t gpio_data;
1542 unsigned long flags;
7b867cf7 1543 struct qla_hw_data *ha = vha->hw;
f6df144c 1544 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1545
1546 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1547 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1548
7b867cf7 1549 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
7c3df132 1550 ql_log(ql_log_warn, vha, 0x709b,
f6df144c 1551 "Unable to update fw options (beacon on).\n");
1552 return QLA_FUNCTION_FAILED;
1553 }
1554
f6df144c 1555 /* Turn off LEDs. */
1556 spin_lock_irqsave(&ha->hardware_lock, flags);
1557 if (ha->pio_address) {
948882f6
AV		 1558 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1559 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
f6df144c 1560 } else {
1561 gpio_enable = RD_REG_WORD(&reg->gpioe);
1562 gpio_data = RD_REG_WORD(&reg->gpiod);
1563 }
1564 gpio_enable |= GPIO_LED_MASK;
1565
1566 /* Set the modified gpio_enable values. */
1567 if (ha->pio_address) {
948882f6 1568 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
f6df144c 1569 } else {
1570 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1571 RD_REG_WORD(&reg->gpioe);
1572 }
1573
1574 /* Clear out previously set LED colour. */
1575 gpio_data &= ~GPIO_LED_MASK;
1576 if (ha->pio_address) {
948882f6 1577 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
f6df144c 1578 } else {
1579 WRT_REG_WORD(&reg->gpiod, gpio_data);
1580 RD_REG_WORD(&reg->gpiod);
1581 }
1582 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1583
1584 /*
1585 * Let the per HBA timer kick off the blinking process based on
1586 * the following flags. No need to do anything else now.
1587 */
1588 ha->beacon_blink_led = 1;
1589 ha->beacon_color_state = 0;
1590
1591 return QLA_SUCCESS;
1592}
1593
1594int
7b867cf7 1595qla2x00_beacon_off(struct scsi_qla_host *vha)
f6df144c 1596{
1597 int rval = QLA_SUCCESS;
7b867cf7 1598 struct qla_hw_data *ha = vha->hw;
f6df144c 1599
1600 ha->beacon_blink_led = 0;
1601
1602 /* Set the on flag so when it gets flipped it will be off. */
1603 if (IS_QLA2322(ha))
1604 ha->beacon_color_state = QLA_LED_ALL_ON;
1605 else
1606 ha->beacon_color_state = QLA_LED_GRN_ON;
1607
7b867cf7 1608 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
f6df144c 1609
1610 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1611 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1612
7b867cf7 1613 rval = qla2x00_set_fw_options(vha, ha->fw_options);
f6df144c 1614 if (rval != QLA_SUCCESS)
7c3df132 1615 ql_log(ql_log_warn, vha, 0x709c,
f6df144c 1616 "Unable to update fw options (beacon off).\n");
1617 return rval;
1618}
1619
1620
1621static inline void
7b867cf7 1622qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
f6df144c 1623{
1624 /* Flip all colors. */
1625 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1626 /* Turn off. */
1627 ha->beacon_color_state = 0;
1628 *pflags = 0;
1629 } else {
1630 /* Turn on. */
1631 ha->beacon_color_state = QLA_LED_ALL_ON;
1632 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1633 }
1634}
1635
1636void
7b867cf7 1637qla24xx_beacon_blink(struct scsi_qla_host *vha)
f6df144c 1638{
1639 uint16_t led_color = 0;
1640 uint32_t gpio_data;
1641 unsigned long flags;
7b867cf7 1642 struct qla_hw_data *ha = vha->hw;
f6df144c 1643 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1644
1645 /* Save the Original GPIOD. */
1646 spin_lock_irqsave(&ha->hardware_lock, flags);
1647 gpio_data = RD_REG_DWORD(&reg->gpiod);
1648
1649 /* Enable the gpio_data reg for update. */
1650 gpio_data |= GPDX_LED_UPDATE_MASK;
1651
1652 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1653 gpio_data = RD_REG_DWORD(&reg->gpiod);
1654
1655 /* Set the color bits. */
1656 qla24xx_flip_colors(ha, &led_color);
1657
1658 /* Clear out any previously set LED color. */
1659 gpio_data &= ~GPDX_LED_COLOR_MASK;
1660
1661 /* Set the new input LED color to GPIOD. */
1662 gpio_data |= led_color;
1663
1664 /* Set the modified gpio_data values. */
1665 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1666 gpio_data = RD_REG_DWORD(&reg->gpiod);
1667 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1668}
1669
0143d8b7
CD		 1670static uint32_t
1671qla83xx_select_led_port(struct qla_hw_data *ha)
1672{
1673 uint32_t led_select_value = 0;
1674
1675 if (!IS_QLA83XX(ha))
1676 goto out;
1677
1678 if (ha->flags.port0)
1679 led_select_value = QLA83XX_LED_PORT0;
1680 else
1681 led_select_value = QLA83XX_LED_PORT1;
1682
1683out:
1684 return led_select_value;
1685}
1686
6246b8a1
GM		 1687void
1688qla83xx_beacon_blink(struct scsi_qla_host *vha)
1689{
1690 uint32_t led_select_value;
1691 struct qla_hw_data *ha = vha->hw;
1692 uint16_t led_cfg[6];
1693 uint16_t orig_led_cfg[6];
0143d8b7 1694 uint32_t led_10_value, led_43_value;
6246b8a1
GM		 1695
1696 if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha))
1697 return;
1698
0143d8b7
CD		 1699 if (!ha->beacon_blink_led)
1700 return;
1701
1702 if (IS_QLA2031(ha)) {
1703 led_select_value = qla83xx_select_led_port(ha);
6246b8a1 1704
7d613ac6
SV		 1705 qla83xx_wr_reg(vha, led_select_value, 0x40002000);
1706 qla83xx_wr_reg(vha, led_select_value + 4, 0x40002000);
6246b8a1 1707 msleep(1000);
7d613ac6
SV		 1708 qla83xx_wr_reg(vha, led_select_value, 0x40004000);
1709 qla83xx_wr_reg(vha, led_select_value + 4, 0x40004000);
0143d8b7
CD		 1710 } else if (IS_QLA8031(ha)) {
1711 led_select_value = qla83xx_select_led_port(ha);
1712
1713 qla83xx_rd_reg(vha, led_select_value, &led_10_value);
1714 qla83xx_rd_reg(vha, led_select_value + 0x10, &led_43_value);
1715 qla83xx_wr_reg(vha, led_select_value, 0x01f44000);
1716 msleep(500);
1717 qla83xx_wr_reg(vha, led_select_value, 0x400001f4);
1718 msleep(1000);
1719 qla83xx_wr_reg(vha, led_select_value, led_10_value);
1720 qla83xx_wr_reg(vha, led_select_value + 0x10, led_43_value);
1721 } else if (IS_QLA81XX(ha)) {
6246b8a1
GM		 1722 int rval;
1723
1724 /* Save Current */
1725 rval = qla81xx_get_led_config(vha, orig_led_cfg);
1726 /* Do the blink */
1727 if (rval == QLA_SUCCESS) {
1728 if (IS_QLA81XX(ha)) {
1729 led_cfg[0] = 0x4000;
1730 led_cfg[1] = 0x2000;
1731 led_cfg[2] = 0;
1732 led_cfg[3] = 0;
1733 led_cfg[4] = 0;
1734 led_cfg[5] = 0;
1735 } else {
1736 led_cfg[0] = 0x4000;
1737 led_cfg[1] = 0x4000;
1738 led_cfg[2] = 0x4000;
1739 led_cfg[3] = 0x2000;
1740 led_cfg[4] = 0;
1741 led_cfg[5] = 0x2000;
1742 }
1743 rval = qla81xx_set_led_config(vha, led_cfg);
1744 msleep(1000);
1745 if (IS_QLA81XX(ha)) {
1746 led_cfg[0] = 0x4000;
1747 led_cfg[1] = 0x2000;
1748 led_cfg[2] = 0;
1749 } else {
1750 led_cfg[0] = 0x4000;
1751 led_cfg[1] = 0x2000;
1752 led_cfg[2] = 0x4000;
1753 led_cfg[3] = 0x4000;
1754 led_cfg[4] = 0;
1755 led_cfg[5] = 0x2000;
1756 }
1757 rval = qla81xx_set_led_config(vha, led_cfg);
1758 }
1759 /* On exit, restore original (presumes no status change) */
1760 qla81xx_set_led_config(vha, orig_led_cfg);
1761 }
1762}
1763
f6df144c 1764int
7b867cf7 1765qla24xx_beacon_on(struct scsi_qla_host *vha)
f6df144c 1766{
1767 uint32_t gpio_data;
1768 unsigned long flags;
7b867cf7 1769 struct qla_hw_data *ha = vha->hw;
f6df144c 1770 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1771
7ec0effd 1772 if (IS_P3P_TYPE(ha))
a9083016
GM		 1773 return QLA_SUCCESS;
1774
6246b8a1
GM		 1775 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1776 goto skip_gpio; /* let blink handle it */
1777
f6df144c 1778 if (ha->beacon_blink_led == 0) {
1779 /* Enable firmware for update */
1780 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1781
7b867cf7 1782 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
f6df144c 1783 return QLA_FUNCTION_FAILED;
1784
7b867cf7 1785 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
f6df144c 1786 QLA_SUCCESS) {
7c3df132 1787 ql_log(ql_log_warn, vha, 0x7009,
f6df144c 1788 "Unable to update fw options (beacon on).\n");
1789 return QLA_FUNCTION_FAILED;
1790 }
1791
6246b8a1
GM		 1792 if (IS_QLA2031(ha))
1793 goto skip_gpio;
1794
f6df144c 1795 spin_lock_irqsave(&ha->hardware_lock, flags);
1796 gpio_data = RD_REG_DWORD(&reg->gpiod);
1797
1798 /* Enable the gpio_data reg for update. */
1799 gpio_data |= GPDX_LED_UPDATE_MASK;
1800 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1801 RD_REG_DWORD(&reg->gpiod);
1802
1803 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1804 }
1805
1806 /* So all colors blink together. */
1807 ha->beacon_color_state = 0;
1808
6246b8a1 1809skip_gpio:
f6df144c 1810 /* Let the per HBA timer kick off the blinking process. */
1811 ha->beacon_blink_led = 1;
1812
1813 return QLA_SUCCESS;
1814}
1815
1816int
7b867cf7 1817qla24xx_beacon_off(struct scsi_qla_host *vha)
f6df144c 1818{
1819 uint32_t gpio_data;
1820 unsigned long flags;
7b867cf7 1821 struct qla_hw_data *ha = vha->hw;
f6df144c 1822 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1823
7ec0effd 1824 if (IS_P3P_TYPE(ha))
a9083016
GM		 1825 return QLA_SUCCESS;
1826
f6df144c 1827 ha->beacon_blink_led = 0;
6246b8a1
GM		 1828
1829 if (IS_QLA2031(ha))
1830 goto set_fw_options;
1831
1832 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1833 return QLA_SUCCESS;
1834
f6df144c 1835 ha->beacon_color_state = QLA_LED_ALL_ON;
1836
7b867cf7 1837 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
f6df144c 1838
1839 /* Give control back to firmware. */
1840 spin_lock_irqsave(&ha->hardware_lock, flags);
1841 gpio_data = RD_REG_DWORD(&reg->gpiod);
1842
1843 /* Disable the gpio_data reg for update. */
1844 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1845 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1846 RD_REG_DWORD(&reg->gpiod);
1847 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1848
6246b8a1 1849set_fw_options:
f6df144c 1850 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1851
7b867cf7 1852 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
7c3df132
SK		 1853 ql_log(ql_log_warn, vha, 0x704d,
1854 "Unable to update fw options (beacon on).\n");
f6df144c 1855 return QLA_FUNCTION_FAILED;
1856 }
1857
7b867cf7 1858 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
7c3df132
SK		 1859 ql_log(ql_log_warn, vha, 0x704e,
1860 "Unable to update fw options (beacon on).\n");
f6df144c 1861 return QLA_FUNCTION_FAILED;
1862 }
1863
1864 return QLA_SUCCESS;
1865}
854165f4 1866
1867
1868/*
1869 * Flash support routines
1870 */
1871
1872/**
1873 * qla2x00_flash_enable() - Setup flash for reading and writing.
1874 * @ha: HA context
1875 */
1876static void
7b867cf7 1877qla2x00_flash_enable(struct qla_hw_data *ha)
854165f4 1878{
1879 uint16_t data;
1880 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1881
1882 data = RD_REG_WORD(&reg->ctrl_status);
1883 data |= CSR_FLASH_ENABLE;
1884 WRT_REG_WORD(&reg->ctrl_status, data);
1885 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1886}
1887
1888/**
1889 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1890 * @ha: HA context
1891 */
1892static void
7b867cf7 1893qla2x00_flash_disable(struct qla_hw_data *ha)
854165f4 1894{
1895 uint16_t data;
1896 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1897
1898 data = RD_REG_WORD(&reg->ctrl_status);
1899 data &= ~(CSR_FLASH_ENABLE);
1900 WRT_REG_WORD(&reg->ctrl_status, data);
1901 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1902}
1903
1904/**
1905 * qla2x00_read_flash_byte() - Reads a byte from flash
1906 * @ha: HA context
1907 * @addr: Address in flash to read
1908 *
1909 * A word is read from the chip, but, only the lower byte is valid.
1910 *
1911 * Returns the byte read from flash @addr.
1912 */
1913static uint8_t
7b867cf7 1914qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
854165f4 1915{
1916 uint16_t data;
1917 uint16_t bank_select;
1918 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1919
1920 bank_select = RD_REG_WORD(&reg->ctrl_status);
1921
1922 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1923 /* Specify 64K address range: */
1924 /* clear out Module Select and Flash Address bits [19:16]. */
1925 bank_select &= ~0xf8;
1926 bank_select |= addr >> 12 & 0xf0;
1927 bank_select |= CSR_FLASH_64K_BANK;
1928 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1929 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1930
1931 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1932 data = RD_REG_WORD(&reg->flash_data);
1933
1934 return (uint8_t)data;
1935 }
1936
1937 /* Setup bit 16 of flash address. */
1938 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1939 bank_select |= CSR_FLASH_64K_BANK;
1940 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1941 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1942 } else if (((addr & BIT_16) == 0) &&
1943 (bank_select & CSR_FLASH_64K_BANK)) {
1944 bank_select &= ~(CSR_FLASH_64K_BANK);
1945 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1946 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1947 }
1948
1949 /* Always perform IO mapped accesses to the FLASH registers. */
1950 if (ha->pio_address) {
1951 uint16_t data2;
1952
948882f6 1953 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
854165f4 1954 do {
948882f6 1955 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
854165f4 1956 barrier();
1957 cpu_relax();
948882f6 1958 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
854165f4 1959 } while (data != data2);
1960 } else {
1961 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1962 data = qla2x00_debounce_register(&reg->flash_data);
1963 }
1964
1965 return (uint8_t)data;
1966}
1967
1968/**
1969 * qla2x00_write_flash_byte() - Write a byte to flash
1970 * @ha: HA context
1971 * @addr: Address in flash to write
1972 * @data: Data to write
1973 */
1974static void
7b867cf7 1975qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
854165f4 1976{
1977 uint16_t bank_select;
1978 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1979
1980 bank_select = RD_REG_WORD(&reg->ctrl_status);
1981 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1982 /* Specify 64K address range: */
1983 /* clear out Module Select and Flash Address bits [19:16]. */
1984 bank_select &= ~0xf8;
1985 bank_select |= addr >> 12 & 0xf0;
1986 bank_select |= CSR_FLASH_64K_BANK;
1987 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1988 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1989
1990 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1991 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1992 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1993 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1994
1995 return;
1996 }
1997
1998 /* Setup bit 16 of flash address. */
1999 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
2000 bank_select |= CSR_FLASH_64K_BANK;
2001 WRT_REG_WORD(&reg->ctrl_status, bank_select);
2002 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2003 } else if (((addr & BIT_16) == 0) &&
2004 (bank_select & CSR_FLASH_64K_BANK)) {
2005 bank_select &= ~(CSR_FLASH_64K_BANK);
2006 WRT_REG_WORD(&reg->ctrl_status, bank_select);
2007 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2008 }
2009
2010 /* Always perform IO mapped accesses to the FLASH registers. */
2011 if (ha->pio_address) {
948882f6
AV		 2012 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
2013 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
854165f4 2014 } else {
2015 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
2016 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2017 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
2018 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2019 }
2020}
2021
2022/**
2023 * qla2x00_poll_flash() - Polls flash for completion.
2024 * @ha: HA context
2025 * @addr: Address in flash to poll
2026 * @poll_data: Data to be polled
2027 * @man_id: Flash manufacturer ID
2028 * @flash_id: Flash ID
2029 *
2030 * This function polls the device until bit 7 of what is read matches data
2031 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
2032 * out (a fatal error). The flash book recommeds reading bit 7 again after
2033 * reading bit 5 as a 1.
2034 *
2035 * Returns 0 on success, else non-zero.
2036 */
2037static int
7b867cf7 2038qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
854165f4 2039 uint8_t man_id, uint8_t flash_id)
2040{
2041 int status;
2042 uint8_t flash_data;
2043 uint32_t cnt;
2044
2045 status = 1;
2046
2047 /* Wait for 30 seconds for command to finish. */
2048 poll_data &= BIT_7;
2049 for (cnt = 3000000; cnt; cnt--) {
2050 flash_data = qla2x00_read_flash_byte(ha, addr);
2051 if ((flash_data & BIT_7) == poll_data) {
2052 status = 0;
2053 break;
2054 }
2055
2056 if (man_id != 0x40 && man_id != 0xda) {
2057 if ((flash_data & BIT_5) && cnt > 2)
2058 cnt = 2;
2059 }
2060 udelay(10);
2061 barrier();
40a2e34a 2062 cond_resched();
854165f4 2063 }
2064 return status;
2065}
2066
854165f4 2067/**
2068 * qla2x00_program_flash_address() - Programs a flash address
2069 * @ha: HA context
2070 * @addr: Address in flash to program
2071 * @data: Data to be written in flash
2072 * @man_id: Flash manufacturer ID
2073 * @flash_id: Flash ID
2074 *
2075 * Returns 0 on success, else non-zero.
2076 */
2077static int
7b867cf7
AC		 2078qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
2079 uint8_t data, uint8_t man_id, uint8_t flash_id)
854165f4 2080{
2081 /* Write Program Command Sequence. */
2082 if (IS_OEM_001(ha)) {
2083 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2084 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2085 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
2086 qla2x00_write_flash_byte(ha, addr, data);
2087 } else {
2088 if (man_id == 0xda && flash_id == 0xc1) {
2089 qla2x00_write_flash_byte(ha, addr, data);
2090 if (addr & 0x7e)
2091 return 0;
2092 } else {
2093 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2094 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2095 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
2096 qla2x00_write_flash_byte(ha, addr, data);
2097 }
2098 }
2099
2100 udelay(150);
2101
2102 /* Wait for write to complete. */
2103 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
2104}
2105
2106/**
2107 * qla2x00_erase_flash() - Erase the flash.
2108 * @ha: HA context
2109 * @man_id: Flash manufacturer ID
2110 * @flash_id: Flash ID
2111 *
2112 * Returns 0 on success, else non-zero.
2113 */
2114static int
7b867cf7 2115qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
854165f4 2116{
2117 /* Individual Sector Erase Command Sequence */
2118 if (IS_OEM_001(ha)) {
2119 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2120 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2121 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
2122 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2123 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2124 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
2125 } else {
2126 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2127 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2128 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2129 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2130 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2131 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
2132 }
2133
2134 udelay(150);
2135
2136 /* Wait for erase to complete. */
2137 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
2138}
2139
2140/**
2141 * qla2x00_erase_flash_sector() - Erase a flash sector.
2142 * @ha: HA context
2143 * @addr: Flash sector to erase
2144 * @sec_mask: Sector address mask
2145 * @man_id: Flash manufacturer ID
2146 * @flash_id: Flash ID
2147 *
2148 * Returns 0 on success, else non-zero.
2149 */
2150static int
7b867cf7 2151qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
854165f4 2152 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
2153{
2154 /* Individual Sector Erase Command Sequence */
2155 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2156 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2157 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2158 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2159 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2160 if (man_id == 0x1f && flash_id == 0x13)
2161 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
2162 else
2163 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
2164
2165 udelay(150);
2166
2167 /* Wait for erase to complete. */
2168 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
2169}
2170
2171/**
2172 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
2173 * @man_id: Flash manufacturer ID
2174 * @flash_id: Flash ID
2175 */
2176static void
7b867cf7 2177qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
854165f4 2178 uint8_t *flash_id)
2179{
2180 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2181 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2182 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
2183 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
2184 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
2185 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2186 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2187 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
2188}
2189
30c47662 2190static void
7b867cf7
AC		 2191qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
2192 uint32_t saddr, uint32_t length)
30c47662
AV		 2193{
2194 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2195 uint32_t midpoint, ilength;
2196 uint8_t data;
2197
2198 midpoint = length / 2;
2199
2200 WRT_REG_WORD(&reg->nvram, 0);
2201 RD_REG_WORD(&reg->nvram);
2202 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
2203 if (ilength == midpoint) {
2204 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2205 RD_REG_WORD(&reg->nvram);
2206 }
2207 data = qla2x00_read_flash_byte(ha, saddr);
2208 if (saddr % 100)
2209 udelay(10);
2210 *tmp_buf = data;
40a2e34a 2211 cond_resched();
30c47662
AV		 2212 }
2213}
854165f4 2214
2215static inline void
7b867cf7 2216qla2x00_suspend_hba(struct scsi_qla_host *vha)
854165f4 2217{
2218 int cnt;
2219 unsigned long flags;
7b867cf7 2220 struct qla_hw_data *ha = vha->hw;
854165f4 2221 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2222
2223 /* Suspend HBA. */
7b867cf7 2224 scsi_block_requests(vha->host);
fd34f556 2225 ha->isp_ops->disable_intrs(ha);
854165f4 2226 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2227
2228 /* Pause RISC. */
2229 spin_lock_irqsave(&ha->hardware_lock, flags);
2230 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2231 RD_REG_WORD(&reg->hccr);
2232 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2233 for (cnt = 0; cnt < 30000; cnt++) {
2234 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
2235 break;
2236 udelay(100);
2237 }
2238 } else {
2239 udelay(10);
2240 }
2241 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2242}
2243
2244static inline void
7b867cf7 2245qla2x00_resume_hba(struct scsi_qla_host *vha)
854165f4 2246{
7b867cf7
AC		 2247 struct qla_hw_data *ha = vha->hw;
2248
854165f4 2249 /* Resume HBA. */
2250 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7
AC		 2251 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2252 qla2xxx_wake_dpc(vha);
2533cf67 2253 qla2x00_wait_for_chip_reset(vha);
7b867cf7 2254 scsi_unblock_requests(vha->host);
854165f4 2255}
2256
2257uint8_t *
7b867cf7 2258qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 2259 uint32_t offset, uint32_t length)
2260{
854165f4 2261 uint32_t addr, midpoint;
2262 uint8_t *data;
7b867cf7 2263 struct qla_hw_data *ha = vha->hw;
854165f4 2264 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2265
2266 /* Suspend HBA. */
7b867cf7 2267 qla2x00_suspend_hba(vha);
854165f4 2268
2269 /* Go with read. */
854165f4 2270 midpoint = ha->optrom_size / 2;
2271
2272 qla2x00_flash_enable(ha);
2273 WRT_REG_WORD(&reg->nvram, 0);
2274 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
2275 for (addr = offset, data = buf; addr < length; addr++, data++) {
2276 if (addr == midpoint) {
2277 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2278 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
2279 }
2280
2281 *data = qla2x00_read_flash_byte(ha, addr);
2282 }
2283 qla2x00_flash_disable(ha);
854165f4 2284
2285 /* Resume HBA. */
7b867cf7 2286 qla2x00_resume_hba(vha);
854165f4 2287
2288 return buf;
2289}
2290
2291int
7b867cf7 2292qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 2293 uint32_t offset, uint32_t length)
2294{
2295
2296 int rval;
854165f4 2297 uint8_t man_id, flash_id, sec_number, data;
2298 uint16_t wd;
2299 uint32_t addr, liter, sec_mask, rest_addr;
7b867cf7 2300 struct qla_hw_data *ha = vha->hw;
854165f4 2301 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2302
2303 /* Suspend HBA. */
7b867cf7 2304 qla2x00_suspend_hba(vha);
854165f4 2305
2306 rval = QLA_SUCCESS;
2307 sec_number = 0;
2308
2309 /* Reset ISP chip. */
854165f4 2310 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2311 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2312
2313 /* Go with write. */
2314 qla2x00_flash_enable(ha);
2315 do { /* Loop once to provide quick error exit */
2316 /* Structure of flash memory based on manufacturer */
2317 if (IS_OEM_001(ha)) {
2318 /* OEM variant with special flash part. */
2319 man_id = flash_id = 0;
2320 rest_addr = 0xffff;
2321 sec_mask = 0x10000;
2322 goto update_flash;
2323 }
2324 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2325 switch (man_id) {
2326 case 0x20: /* ST flash. */
2327 if (flash_id == 0xd2 || flash_id == 0xe3) {
2328 /*
2329 * ST m29w008at part - 64kb sector size with
2330 * 32kb,8kb,8kb,16kb sectors at memory address
2331 * 0xf0000.
2332 */
2333 rest_addr = 0xffff;
2334 sec_mask = 0x10000;
2335 break;
2336 }
2337 /*
2338 * ST m29w010b part - 16kb sector size
2339 * Default to 16kb sectors
2340 */
2341 rest_addr = 0x3fff;
2342 sec_mask = 0x1c000;
2343 break;
2344 case 0x40: /* Mostel flash. */
2345 /* Mostel v29c51001 part - 512 byte sector size. */
2346 rest_addr = 0x1ff;
2347 sec_mask = 0x1fe00;
2348 break;
2349 case 0xbf: /* SST flash. */
2350 /* SST39sf10 part - 4kb sector size. */
2351 rest_addr = 0xfff;
2352 sec_mask = 0x1f000;
2353 break;
2354 case 0xda: /* Winbond flash. */
2355 /* Winbond W29EE011 part - 256 byte sector size. */
2356 rest_addr = 0x7f;
2357 sec_mask = 0x1ff80;
2358 break;
2359 case 0xc2: /* Macronix flash. */
2360 /* 64k sector size. */
2361 if (flash_id == 0x38 || flash_id == 0x4f) {
2362 rest_addr = 0xffff;
2363 sec_mask = 0x10000;
2364 break;
2365 }
2366 /* Fall through... */
2367
2368 case 0x1f: /* Atmel flash. */
2369 /* 512k sector size. */
2370 if (flash_id == 0x13) {
2371 rest_addr = 0x7fffffff;
2372 sec_mask = 0x80000000;
2373 break;
2374 }
2375 /* Fall through... */
2376
2377 case 0x01: /* AMD flash. */
2378 if (flash_id == 0x38 || flash_id == 0x40 ||
2379 flash_id == 0x4f) {
2380 /* Am29LV081 part - 64kb sector size. */
2381 /* Am29LV002BT part - 64kb sector size. */
2382 rest_addr = 0xffff;
2383 sec_mask = 0x10000;
2384 break;
2385 } else if (flash_id == 0x3e) {
2386 /*
2387 * Am29LV008b part - 64kb sector size with
2388 * 32kb,8kb,8kb,16kb sector at memory address
2389 * h0xf0000.
2390 */
2391 rest_addr = 0xffff;
2392 sec_mask = 0x10000;
2393 break;
2394 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2395 /*
2396 * Am29LV010 part or AM29f010 - 16kb sector
2397 * size.
2398 */
2399 rest_addr = 0x3fff;
2400 sec_mask = 0x1c000;
2401 break;
2402 } else if (flash_id == 0x6d) {
2403 /* Am29LV001 part - 8kb sector size. */
2404 rest_addr = 0x1fff;
2405 sec_mask = 0x1e000;
2406 break;
2407 }
2408 default:
2409 /* Default to 16 kb sector size. */
2410 rest_addr = 0x3fff;
2411 sec_mask = 0x1c000;
2412 break;
2413 }
2414
2415update_flash:
2416 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2417 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2418 rval = QLA_FUNCTION_FAILED;
2419 break;
2420 }
2421 }
2422
2423 for (addr = offset, liter = 0; liter < length; liter++,
2424 addr++) {
2425 data = buf[liter];
2426 /* Are we at the beginning of a sector? */
2427 if ((addr & rest_addr) == 0) {
2428 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2429 if (addr >= 0x10000UL) {
2430 if (((addr >> 12) & 0xf0) &&
2431 ((man_id == 0x01 &&
2432 flash_id == 0x3e) ||
2433 (man_id == 0x20 &&
2434 flash_id == 0xd2))) {
2435 sec_number++;
2436 if (sec_number == 1) {
2437 rest_addr =
2438 0x7fff;
2439 sec_mask =
2440 0x18000;
2441 } else if (
2442 sec_number == 2 ||
2443 sec_number == 3) {
2444 rest_addr =
2445 0x1fff;
2446 sec_mask =
2447 0x1e000;
2448 } else if (
2449 sec_number == 4) {
2450 rest_addr =
2451 0x3fff;
2452 sec_mask =
2453 0x1c000;
2454 }
2455 }
2456 }
2457 } else if (addr == ha->optrom_size / 2) {
2458 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2459 RD_REG_WORD(&reg->nvram);
2460 }
2461
2462 if (flash_id == 0xda && man_id == 0xc1) {
2463 qla2x00_write_flash_byte(ha, 0x5555,
2464 0xaa);
2465 qla2x00_write_flash_byte(ha, 0x2aaa,
2466 0x55);
2467 qla2x00_write_flash_byte(ha, 0x5555,
2468 0xa0);
2469 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2470 /* Then erase it */
2471 if (qla2x00_erase_flash_sector(ha,
2472 addr, sec_mask, man_id,
2473 flash_id)) {
2474 rval = QLA_FUNCTION_FAILED;
2475 break;
2476 }
2477 if (man_id == 0x01 && flash_id == 0x6d)
2478 sec_number++;
2479 }
2480 }
2481
2482 if (man_id == 0x01 && flash_id == 0x6d) {
2483 if (sec_number == 1 &&
2484 addr == (rest_addr - 1)) {
2485 rest_addr = 0x0fff;
2486 sec_mask = 0x1f000;
2487 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2488 rest_addr = 0x3fff;
2489 sec_mask = 0x1c000;
2490 }
2491 }
2492
2493 if (qla2x00_program_flash_address(ha, addr, data,
2494 man_id, flash_id)) {
2495 rval = QLA_FUNCTION_FAILED;
2496 break;
2497 }
40a2e34a 2498 cond_resched();
854165f4 2499 }
2500 } while (0);
2501 qla2x00_flash_disable(ha);
854165f4 2502
2503 /* Resume HBA. */
7b867cf7 2504 qla2x00_resume_hba(vha);
854165f4 2505
2506 return rval;
2507}
2508
2509uint8_t *
7b867cf7 2510qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 2511 uint32_t offset, uint32_t length)
2512{
7b867cf7
AC		 2513 struct qla_hw_data *ha = vha->hw;
2514
854165f4 2515 /* Suspend HBA. */
7b867cf7 2516 scsi_block_requests(vha->host);
854165f4 2517 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2518
2519 /* Go with read. */
7b867cf7 2520 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
854165f4 2521
2522 /* Resume HBA. */
2523 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7 2524 scsi_unblock_requests(vha->host);
854165f4 2525
2526 return buf;
2527}
2528
2529int
7b867cf7 2530qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4 2531 uint32_t offset, uint32_t length)
2532{
2533 int rval;
7b867cf7 2534 struct qla_hw_data *ha = vha->hw;
854165f4 2535
2536 /* Suspend HBA. */
7b867cf7 2537 scsi_block_requests(vha->host);
854165f4 2538 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2539
2540 /* Go with write. */
7b867cf7 2541 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
854165f4 2542 length >> 2);
2543
854165f4 2544 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7 2545 scsi_unblock_requests(vha->host);
854165f4 2546
2547 return rval;
2548}
30c47662 2549
338c9161 2550uint8_t *
7b867cf7 2551qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
338c9161
AV		 2552 uint32_t offset, uint32_t length)
2553{
2554 int rval;
2555 dma_addr_t optrom_dma;
2556 void *optrom;
2557 uint8_t *pbuf;
2558 uint32_t faddr, left, burst;
7b867cf7 2559 struct qla_hw_data *ha = vha->hw;
338c9161 2560
368bbe07
AV		 2561 if (IS_QLA25XX(ha) || IS_QLA81XX(ha))
2562 goto try_fast;
b7cc176c 2563 if (offset & 0xfff)
338c9161
AV		 2564 goto slow_read;
2565 if (length < OPTROM_BURST_SIZE)
2566 goto slow_read;
2567
368bbe07 2568try_fast:
338c9161
AV		 2569 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2570 &optrom_dma, GFP_KERNEL);
2571 if (!optrom) {
7c3df132
SK		 2572 ql_log(ql_log_warn, vha, 0x00cc,
2573 "Unable to allocate memory for optrom burst read (%x KB).\n",
2574 OPTROM_BURST_SIZE / 1024);
338c9161
AV		 2575 goto slow_read;
2576 }
2577
2578 pbuf = buf;
2579 faddr = offset >> 2;
2580 left = length >> 2;
2581 burst = OPTROM_BURST_DWORDS;
2582 while (left != 0) {
2583 if (burst > left)
2584 burst = left;
2585
7b867cf7 2586 rval = qla2x00_dump_ram(vha, optrom_dma,
3a03eb79 2587 flash_data_addr(ha, faddr), burst);
338c9161 2588 if (rval) {
7c3df132
SK		 2589 ql_log(ql_log_warn, vha, 0x00f5,
2590 "Unable to burst-read optrom segment (%x/%x/%llx).\n",
2591 rval, flash_data_addr(ha, faddr),
875baf3c 2592 (unsigned long long)optrom_dma);
7c3df132 2593 ql_log(ql_log_warn, vha, 0x00f6,
338c9161
AV		 2594 "Reverting to slow-read.\n");
2595
2596 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2597 optrom, optrom_dma);
2598 goto slow_read;
2599 }
2600
2601 memcpy(pbuf, optrom, burst * 4);
2602
2603 left -= burst;
2604 faddr += burst;
2605 pbuf += burst * 4;
2606 }
2607
2608 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2609 optrom_dma);
2610
2611 return buf;
2612
2613slow_read:
7b867cf7 2614 return qla24xx_read_optrom_data(vha, buf, offset, length);
338c9161
AV		 2615}
2616
30c47662
AV		 2617/**
2618 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2619 * @ha: HA context
2620 * @pcids: Pointer to the FCODE PCI data structure
2621 *
2622 * The process of retrieving the FCODE version information is at best
2623 * described as interesting.
2624 *
2625 * Within the first 100h bytes of the image an ASCII string is present
2626 * which contains several pieces of information including the FCODE
2627 * version. Unfortunately it seems the only reliable way to retrieve
2628 * the version is by scanning for another sentinel within the string,
2629 * the FCODE build date:
2630 *
2631 * ... 2.00.02 10/17/02 ...
2632 *
2633 * Returns QLA_SUCCESS on successful retrieval of version.
2634 */
2635static void
7b867cf7 2636qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
30c47662
AV		 2637{
2638 int ret = QLA_FUNCTION_FAILED;
2639 uint32_t istart, iend, iter, vend;
2640 uint8_t do_next, rbyte, *vbyte;
2641
2642 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2643
2644 /* Skip the PCI data structure. */
2645 istart = pcids +
2646 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2647 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2648 iend = istart + 0x100;
2649 do {
2650 /* Scan for the sentinel date string...eeewww. */
2651 do_next = 0;
2652 iter = istart;
2653 while ((iter < iend) && !do_next) {
2654 iter++;
2655 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2656 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2657 '/')
2658 do_next++;
2659 else if (qla2x00_read_flash_byte(ha,
2660 iter + 3) == '/')
2661 do_next++;
2662 }
2663 }
2664 if (!do_next)
2665 break;
2666
2667 /* Backtrack to previous ' ' (space). */
2668 do_next = 0;
2669 while ((iter > istart) && !do_next) {
2670 iter--;
2671 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2672 do_next++;
2673 }
2674 if (!do_next)
2675 break;
2676
2677 /*
2678 * Mark end of version tag, and find previous ' ' (space) or
2679 * string length (recent FCODE images -- major hack ahead!!!).
2680 */
2681 vend = iter - 1;
2682 do_next = 0;
2683 while ((iter > istart) && !do_next) {
2684 iter--;
2685 rbyte = qla2x00_read_flash_byte(ha, iter);
2686 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2687 do_next++;
2688 }
2689 if (!do_next)
2690 break;
2691
2692 /* Mark beginning of version tag, and copy data. */
2693 iter++;
2694 if ((vend - iter) &&
2695 ((vend - iter) < sizeof(ha->fcode_revision))) {
2696 vbyte = ha->fcode_revision;
2697 while (iter <= vend) {
2698 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2699 iter++;
2700 }
2701 ret = QLA_SUCCESS;
2702 }
2703 } while (0);
2704
2705 if (ret != QLA_SUCCESS)
2706 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2707}
2708
2709int
7b867cf7 2710qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
30c47662
AV		 2711{
2712 int ret = QLA_SUCCESS;
2713 uint8_t code_type, last_image;
2714 uint32_t pcihdr, pcids;
2715 uint8_t *dbyte;
2716 uint16_t *dcode;
7b867cf7 2717 struct qla_hw_data *ha = vha->hw;
30c47662
AV		 2718
2719 if (!ha->pio_address || !mbuf)
2720 return QLA_FUNCTION_FAILED;
2721
2722 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2723 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2724 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2725 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2726
2727 qla2x00_flash_enable(ha);
2728
2729 /* Begin with first PCI expansion ROM header. */
2730 pcihdr = 0;
2731 last_image = 1;
2732 do {
2733 /* Verify PCI expansion ROM header. */
2734 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2735 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2736 /* No signature */
7c3df132
SK		 2737 ql_log(ql_log_fatal, vha, 0x0050,
2738 "No matching ROM signature.\n");
30c47662
AV		 2739 ret = QLA_FUNCTION_FAILED;
2740 break;
2741 }
2742
2743 /* Locate PCI data structure. */
2744 pcids = pcihdr +
2745 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2746 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2747
2748 /* Validate signature of PCI data structure. */
2749 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2750 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2751 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2752 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2753 /* Incorrect header. */
7c3df132
SK		 2754 ql_log(ql_log_fatal, vha, 0x0051,
2755 "PCI data struct not found pcir_adr=%x.\n", pcids);
30c47662
AV		 2756 ret = QLA_FUNCTION_FAILED;
2757 break;
2758 }
2759
2760 /* Read version */
2761 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2762 switch (code_type) {
2763 case ROM_CODE_TYPE_BIOS:
2764 /* Intel x86, PC-AT compatible. */
2765 ha->bios_revision[0] =
2766 qla2x00_read_flash_byte(ha, pcids + 0x12);
2767 ha->bios_revision[1] =
2768 qla2x00_read_flash_byte(ha, pcids + 0x13);
7c3df132
SK		 2769 ql_dbg(ql_dbg_init, vha, 0x0052,
2770 "Read BIOS %d.%d.\n",
2771 ha->bios_revision[1], ha->bios_revision[0]);
30c47662
AV		 2772 break;
2773 case ROM_CODE_TYPE_FCODE:
2774 /* Open Firmware standard for PCI (FCode). */
2775 /* Eeeewww... */
2776 qla2x00_get_fcode_version(ha, pcids);
2777 break;
2778 case ROM_CODE_TYPE_EFI:
2779 /* Extensible Firmware Interface (EFI). */
2780 ha->efi_revision[0] =
2781 qla2x00_read_flash_byte(ha, pcids + 0x12);
2782 ha->efi_revision[1] =
2783 qla2x00_read_flash_byte(ha, pcids + 0x13);
7c3df132
SK		 2784 ql_dbg(ql_dbg_init, vha, 0x0053,
2785 "Read EFI %d.%d.\n",
2786 ha->efi_revision[1], ha->efi_revision[0]);
30c47662
AV		 2787 break;
2788 default:
7c3df132
SK		 2789 ql_log(ql_log_warn, vha, 0x0054,
2790 "Unrecognized code type %x at pcids %x.\n",
2791 code_type, pcids);
30c47662
AV		 2792 break;
2793 }
2794
2795 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2796
2797 /* Locate next PCI expansion ROM. */
2798 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2799 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2800 } while (!last_image);
2801
2802 if (IS_QLA2322(ha)) {
2803 /* Read firmware image information. */
2804 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2805 dbyte = mbuf;
2806 memset(dbyte, 0, 8);
2807 dcode = (uint16_t *)dbyte;
2808
c00d8994 2809 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
30c47662 2810 8);
7c3df132
SK		 2811 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a,
2812 "Dumping fw "
2813 "ver from flash:.\n");
2814 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b,
2815 (uint8_t *)dbyte, 8);
30c47662
AV		 2816
2817 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2818 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2819 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2820 dcode[3] == 0)) {
7c3df132
SK		 2821 ql_log(ql_log_warn, vha, 0x0057,
2822 "Unrecognized fw revision at %x.\n",
2823 ha->flt_region_fw * 4);
30c47662
AV		 2824 } else {
2825 /* values are in big endian */
2826 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2827 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2828 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
7c3df132
SK		 2829 ql_dbg(ql_dbg_init, vha, 0x0058,
2830 "FW Version: "
2831 "%d.%d.%d.\n", ha->fw_revision[0],
2832 ha->fw_revision[1], ha->fw_revision[2]);
30c47662
AV		 2833 }
2834 }
2835
2836 qla2x00_flash_disable(ha);
2837
2838 return ret;
2839}
2840
7ec0effd
AD		 2841int
2842qla82xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2843{
2844 int ret = QLA_SUCCESS;
2845 uint32_t pcihdr, pcids;
2846 uint32_t *dcode;
2847 uint8_t *bcode;
2848 uint8_t code_type, last_image;
2849 struct qla_hw_data *ha = vha->hw;
2850
2851 if (!mbuf)
2852 return QLA_FUNCTION_FAILED;
2853
2854 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2855 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2856 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2857 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2858
2859 dcode = mbuf;
2860
2861 /* Begin with first PCI expansion ROM header. */
2862 pcihdr = ha->flt_region_boot << 2;
2863 last_image = 1;
2864 do {
2865 /* Verify PCI expansion ROM header. */
2866 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, pcihdr,
2867 0x20 * 4);
2868 bcode = mbuf + (pcihdr % 4);
2869 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2870 /* No signature */
2871 ql_log(ql_log_fatal, vha, 0x0154,
2872 "No matching ROM signature.\n");
2873 ret = QLA_FUNCTION_FAILED;
2874 break;
2875 }
2876
2877 /* Locate PCI data structure. */
2878 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2879
2880 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, pcids,
2881 0x20 * 4);
2882 bcode = mbuf + (pcihdr % 4);
2883
2884 /* Validate signature of PCI data structure. */
2885 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2886 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2887 /* Incorrect header. */
2888 ql_log(ql_log_fatal, vha, 0x0155,
2889 "PCI data struct not found pcir_adr=%x.\n", pcids);
2890 ret = QLA_FUNCTION_FAILED;
2891 break;
2892 }
2893
2894 /* Read version */
2895 code_type = bcode[0x14];
2896 switch (code_type) {
2897 case ROM_CODE_TYPE_BIOS:
2898 /* Intel x86, PC-AT compatible. */
2899 ha->bios_revision[0] = bcode[0x12];
2900 ha->bios_revision[1] = bcode[0x13];
2901 ql_dbg(ql_dbg_init, vha, 0x0156,
2902 "Read BIOS %d.%d.\n",
2903 ha->bios_revision[1], ha->bios_revision[0]);
2904 break;
2905 case ROM_CODE_TYPE_FCODE:
2906 /* Open Firmware standard for PCI (FCode). */
2907 ha->fcode_revision[0] = bcode[0x12];
2908 ha->fcode_revision[1] = bcode[0x13];
2909 ql_dbg(ql_dbg_init, vha, 0x0157,
2910 "Read FCODE %d.%d.\n",
2911 ha->fcode_revision[1], ha->fcode_revision[0]);
2912 break;
2913 case ROM_CODE_TYPE_EFI:
2914 /* Extensible Firmware Interface (EFI). */
2915 ha->efi_revision[0] = bcode[0x12];
2916 ha->efi_revision[1] = bcode[0x13];
2917 ql_dbg(ql_dbg_init, vha, 0x0158,
2918 "Read EFI %d.%d.\n",
2919 ha->efi_revision[1], ha->efi_revision[0]);
2920 break;
2921 default:
2922 ql_log(ql_log_warn, vha, 0x0159,
2923 "Unrecognized code type %x at pcids %x.\n",
2924 code_type, pcids);
2925 break;
2926 }
2927
2928 last_image = bcode[0x15] & BIT_7;
2929
2930 /* Locate next PCI expansion ROM. */
2931 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2932 } while (!last_image);
2933
2934 /* Read firmware image information. */
2935 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2936 dcode = mbuf;
2937 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, ha->flt_region_fw << 2,
2938 0x20);
2939 bcode = mbuf + (pcihdr % 4);
2940
2941 /* Validate signature of PCI data structure. */
2942 if (bcode[0x0] == 0x3 && bcode[0x1] == 0x0 &&
2943 bcode[0x2] == 0x40 && bcode[0x3] == 0x40) {
2944 ha->fw_revision[0] = bcode[0x4];
2945 ha->fw_revision[1] = bcode[0x5];
2946 ha->fw_revision[2] = bcode[0x6];
2947 ql_dbg(ql_dbg_init, vha, 0x015a,
2948 "Firmware revision %d.%d.%d\n",
2949 ha->fw_revision[0], ha->fw_revision[1],
2950 ha->fw_revision[2]);
2951 }
2952
2953 return ret;
2954}
2955
30c47662 2956int
7b867cf7 2957qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
30c47662
AV		 2958{
2959 int ret = QLA_SUCCESS;
2960 uint32_t pcihdr, pcids;
2961 uint32_t *dcode;
2962 uint8_t *bcode;
2963 uint8_t code_type, last_image;
2964 int i;
7b867cf7 2965 struct qla_hw_data *ha = vha->hw;
30c47662 2966
7ec0effd 2967 if (IS_P3P_TYPE(ha))
a9083016
GM		 2968 return ret;
2969
30c47662
AV		 2970 if (!mbuf)
2971 return QLA_FUNCTION_FAILED;
2972
2973 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2974 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2975 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2976 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2977
2978 dcode = mbuf;
2979
2980 /* Begin with first PCI expansion ROM header. */
6315a5f8 2981 pcihdr = ha->flt_region_boot << 2;
30c47662
AV		 2982 last_image = 1;
2983 do {
2984 /* Verify PCI expansion ROM header. */
7b867cf7 2985 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
30c47662
AV		 2986 bcode = mbuf + (pcihdr % 4);
2987 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2988 /* No signature */
7c3df132
SK		 2989 ql_log(ql_log_fatal, vha, 0x0059,
2990 "No matching ROM signature.\n");
30c47662
AV		 2991 ret = QLA_FUNCTION_FAILED;
2992 break;
2993 }
2994
2995 /* Locate PCI data structure. */
2996 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2997
7b867cf7 2998 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
30c47662
AV		 2999 bcode = mbuf + (pcihdr % 4);
3000
3001 /* Validate signature of PCI data structure. */
3002 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
3003 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
3004 /* Incorrect header. */
7c3df132
SK		 3005 ql_log(ql_log_fatal, vha, 0x005a,
3006 "PCI data struct not found pcir_adr=%x.\n", pcids);
30c47662
AV		 3007 ret = QLA_FUNCTION_FAILED;
3008 break;
3009 }
3010
3011 /* Read version */
3012 code_type = bcode[0x14];
3013 switch (code_type) {
3014 case ROM_CODE_TYPE_BIOS:
3015 /* Intel x86, PC-AT compatible. */
3016 ha->bios_revision[0] = bcode[0x12];
3017 ha->bios_revision[1] = bcode[0x13];
7c3df132
SK		 3018 ql_dbg(ql_dbg_init, vha, 0x005b,
3019 "Read BIOS %d.%d.\n",
3020 ha->bios_revision[1], ha->bios_revision[0]);
30c47662
AV		 3021 break;
3022 case ROM_CODE_TYPE_FCODE:
3023 /* Open Firmware standard for PCI (FCode). */
3024 ha->fcode_revision[0] = bcode[0x12];
3025 ha->fcode_revision[1] = bcode[0x13];
7c3df132
SK		 3026 ql_dbg(ql_dbg_init, vha, 0x005c,
3027 "Read FCODE %d.%d.\n",
3028 ha->fcode_revision[1], ha->fcode_revision[0]);
30c47662
AV		 3029 break;
3030 case ROM_CODE_TYPE_EFI:
3031 /* Extensible Firmware Interface (EFI). */
3032 ha->efi_revision[0] = bcode[0x12];
3033 ha->efi_revision[1] = bcode[0x13];
7c3df132
SK		 3034 ql_dbg(ql_dbg_init, vha, 0x005d,
3035 "Read EFI %d.%d.\n",
3036 ha->efi_revision[1], ha->efi_revision[0]);
30c47662
AV		 3037 break;
3038 default:
7c3df132
SK		 3039 ql_log(ql_log_warn, vha, 0x005e,
3040 "Unrecognized code type %x at pcids %x.\n",
3041 code_type, pcids);
30c47662
AV		 3042 break;
3043 }
3044
3045 last_image = bcode[0x15] & BIT_7;
3046
3047 /* Locate next PCI expansion ROM. */
3048 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
3049 } while (!last_image);
3050
3051 /* Read firmware image information. */
3052 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3053 dcode = mbuf;
3054
7b867cf7 3055 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
30c47662
AV		 3056 for (i = 0; i < 4; i++)
3057 dcode[i] = be32_to_cpu(dcode[i]);
3058
3059 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
3060 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
3061 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
3062 dcode[3] == 0)) {
7c3df132
SK		 3063 ql_log(ql_log_warn, vha, 0x005f,
3064 "Unrecognized fw revision at %x.\n",
3065 ha->flt_region_fw * 4);
30c47662
AV		 3066 } else {
3067 ha->fw_revision[0] = dcode[0];
3068 ha->fw_revision[1] = dcode[1];
3069 ha->fw_revision[2] = dcode[2];
3070 ha->fw_revision[3] = dcode[3];
7c3df132
SK		 3071 ql_dbg(ql_dbg_init, vha, 0x0060,
3072 "Firmware revision %d.%d.%d.%d.\n",
3073 ha->fw_revision[0], ha->fw_revision[1],
3074 ha->fw_revision[2], ha->fw_revision[3]);
30c47662
AV		 3075 }
3076
0f2d962f
MI		 3077 /* Check for golden firmware and get version if available */
3078 if (!IS_QLA81XX(ha)) {
3079 /* Golden firmware is not present in non 81XX adapters */
3080 return ret;
3081 }
3082
3083 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version));
3084 dcode = mbuf;
3085 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode,
3086 ha->flt_region_gold_fw << 2, 32);
3087
3088 if (dcode[4] == 0xFFFFFFFF && dcode[5] == 0xFFFFFFFF &&
3089 dcode[6] == 0xFFFFFFFF && dcode[7] == 0xFFFFFFFF) {
7c3df132
SK		 3090 ql_log(ql_log_warn, vha, 0x0056,
3091 "Unrecognized golden fw at 0x%x.\n",
3092 ha->flt_region_gold_fw * 4);
0f2d962f
MI		 3093 return ret;
3094 }
3095
3096 for (i = 4; i < 8; i++)
3097 ha->gold_fw_version[i-4] = be32_to_cpu(dcode[i]);
3098
30c47662
AV		 3099 return ret;
3100}
cb8dacbf 3101
1ee27146
JC		 3102static int
3103qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
3104{
3105 if (pos >= end || *pos != 0x82)
3106 return 0;
3107
3108 pos += 3 + pos[1];
3109 if (pos >= end || *pos != 0x90)
3110 return 0;
3111
3112 pos += 3 + pos[1];
3113 if (pos >= end || *pos != 0x78)
3114 return 0;
3115
3116 return 1;
3117}
3118
3119int
7b867cf7 3120qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
1ee27146 3121{
7b867cf7 3122 struct qla_hw_data *ha = vha->hw;
1ee27146
JC		 3123 uint8_t *pos = ha->vpd;
3124 uint8_t *end = pos + ha->vpd_size;
3125 int len = 0;
3126
3127 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
3128 return 0;
3129
3130 while (pos < end && *pos != 0x78) {
3131 len = (*pos == 0x82) ? pos[1] : pos[2];
3132
3133 if (!strncmp(pos, key, strlen(key)))
3134 break;
3135
3136 if (*pos != 0x90 && *pos != 0x91)
3137 pos += len;
3138
3139 pos += 3;
3140 }
3141
3142 if (pos < end - len && *pos != 0x78)
3143 return snprintf(str, size, "%.*s", len, pos + 3);
3144
3145 return 0;
3146}
09ff701a
SR		 3147
3148int
3149qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha)
3150{
3151 int len, max_len;
3152 uint32_t fcp_prio_addr;
3153 struct qla_hw_data *ha = vha->hw;
3154
3155 if (!ha->fcp_prio_cfg) {
3156 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE);
3157 if (!ha->fcp_prio_cfg) {
7c3df132
SK		 3158 ql_log(ql_log_warn, vha, 0x00d5,
3159 "Unable to allocate memory for fcp priorty data (%x).\n",
3160 FCP_PRIO_CFG_SIZE);
09ff701a
SR		 3161 return QLA_FUNCTION_FAILED;
3162 }
3163 }
3164 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE);
3165
3166 fcp_prio_addr = ha->flt_region_fcp_prio;
3167
3168 /* first read the fcp priority data header from flash */
3169 ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg,
3170 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE);
3171
7c3df132 3172 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0))
09ff701a
SR		 3173 goto fail;
3174
3175 /* read remaining FCP CMD config data from flash */
3176 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2);
3177 len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE;
3178 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE;
3179
3180 ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0],
3181 fcp_prio_addr << 2, (len < max_len ? len : max_len));
3182
3183 /* revalidate the entire FCP priority config data, including entries */
7c3df132 3184 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1))
09ff701a
SR		 3185 goto fail;
3186
3187 ha->flags.fcp_prio_enabled = 1;
3188 return QLA_SUCCESS;
3189fail:
3190 vfree(ha->fcp_prio_cfg);
3191 ha->fcp_prio_cfg = NULL;
3192 return QLA_FUNCTION_FAILED;
3193}
Linux 6.x block layer and io_uring tree(s)