Commit | Line | Data |
---|---|---|
fa90c54f AV |
1 | /* |
2 | * QLogic Fibre Channel HBA Driver | |
46152ceb | 3 | * Copyright (c) 2003-2012 QLogic Corporation |
1da177e4 | 4 | * |
fa90c54f AV |
5 | * See LICENSE.qla2xxx for copyright and licensing details. |
6 | */ | |
1da177e4 LT |
7 | #include "qla_def.h" |
8 | ||
9 | #include <linux/delay.h> | |
5a0e3ad6 | 10 | #include <linux/slab.h> |
2c96d8d0 | 11 | #include <linux/vmalloc.h> |
1da177e4 LT |
12 | #include <asm/uaccess.h> |
13 | ||
1da177e4 LT |
14 | /* |
15 | * NVRAM support routines | |
16 | */ | |
17 | ||
18 | /** | |
fa2a1ce5 | 19 | * qla2x00_lock_nvram_access() - |
1da177e4 LT |
20 | * @ha: HA context |
21 | */ | |
a824ebb3 | 22 | static void |
7b867cf7 | 23 | qla2x00_lock_nvram_access(struct qla_hw_data *ha) |
1da177e4 LT |
24 | { |
25 | uint16_t data; | |
3d71644c | 26 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
27 | |
28 | if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { | |
29 | data = RD_REG_WORD(®->nvram); | |
30 | while (data & NVR_BUSY) { | |
31 | udelay(100); | |
32 | data = RD_REG_WORD(®->nvram); | |
33 | } | |
34 | ||
35 | /* Lock resource */ | |
36 | WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); | |
37 | RD_REG_WORD(®->u.isp2300.host_semaphore); | |
38 | udelay(5); | |
39 | data = RD_REG_WORD(®->u.isp2300.host_semaphore); | |
40 | while ((data & BIT_0) == 0) { | |
41 | /* Lock failed */ | |
42 | udelay(100); | |
43 | WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); | |
44 | RD_REG_WORD(®->u.isp2300.host_semaphore); | |
45 | udelay(5); | |
46 | data = RD_REG_WORD(®->u.isp2300.host_semaphore); | |
47 | } | |
48 | } | |
49 | } | |
50 | ||
51 | /** | |
fa2a1ce5 | 52 | * qla2x00_unlock_nvram_access() - |
1da177e4 LT |
53 | * @ha: HA context |
54 | */ | |
a824ebb3 | 55 | static void |
7b867cf7 | 56 | qla2x00_unlock_nvram_access(struct qla_hw_data *ha) |
1da177e4 | 57 | { |
3d71644c | 58 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
59 | |
60 | if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { | |
61 | WRT_REG_WORD(®->u.isp2300.host_semaphore, 0); | |
62 | RD_REG_WORD(®->u.isp2300.host_semaphore); | |
63 | } | |
64 | } | |
65 | ||
7b867cf7 AC |
66 | /** |
67 | * qla2x00_nv_write() - Prepare for NVRAM read/write operation. | |
68 | * @ha: HA context | |
69 | * @data: Serial interface selector | |
70 | */ | |
71 | static void | |
72 | qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data) | |
73 | { | |
74 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
75 | ||
76 | WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); | |
77 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
78 | NVRAM_DELAY(); | |
79 | WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_CLOCK | | |
80 | NVR_WRT_ENABLE); | |
81 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
82 | NVRAM_DELAY(); | |
83 | WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); | |
84 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
85 | NVRAM_DELAY(); | |
86 | } | |
87 | ||
88 | /** | |
89 | * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from | |
90 | * NVRAM. | |
91 | * @ha: HA context | |
92 | * @nv_cmd: NVRAM command | |
93 | * | |
94 | * Bit definitions for NVRAM command: | |
95 | * | |
96 | * Bit 26 = start bit | |
97 | * Bit 25, 24 = opcode | |
98 | * Bit 23-16 = address | |
99 | * Bit 15-0 = write data | |
100 | * | |
101 | * Returns the word read from nvram @addr. | |
102 | */ | |
103 | static uint16_t | |
104 | qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd) | |
105 | { | |
106 | uint8_t cnt; | |
107 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
108 | uint16_t data = 0; | |
109 | uint16_t reg_data; | |
110 | ||
111 | /* Send command to NVRAM. */ | |
112 | nv_cmd <<= 5; | |
113 | for (cnt = 0; cnt < 11; cnt++) { | |
114 | if (nv_cmd & BIT_31) | |
115 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
116 | else | |
117 | qla2x00_nv_write(ha, 0); | |
118 | nv_cmd <<= 1; | |
119 | } | |
120 | ||
121 | /* Read data from NVRAM. */ | |
122 | for (cnt = 0; cnt < 16; cnt++) { | |
123 | WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK); | |
124 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
125 | NVRAM_DELAY(); | |
126 | data <<= 1; | |
127 | reg_data = RD_REG_WORD(®->nvram); | |
128 | if (reg_data & NVR_DATA_IN) | |
129 | data |= BIT_0; | |
130 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
131 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
132 | NVRAM_DELAY(); | |
133 | } | |
134 | ||
135 | /* Deselect chip. */ | |
136 | WRT_REG_WORD(®->nvram, NVR_DESELECT); | |
137 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
138 | NVRAM_DELAY(); | |
139 | ||
140 | return data; | |
141 | } | |
142 | ||
143 | ||
1da177e4 LT |
144 | /** |
145 | * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the | |
146 | * request routine to get the word from NVRAM. | |
147 | * @ha: HA context | |
148 | * @addr: Address in NVRAM to read | |
149 | * | |
150 | * Returns the word read from nvram @addr. | |
151 | */ | |
a824ebb3 | 152 | static uint16_t |
7b867cf7 | 153 | qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr) |
1da177e4 LT |
154 | { |
155 | uint16_t data; | |
156 | uint32_t nv_cmd; | |
157 | ||
158 | nv_cmd = addr << 16; | |
159 | nv_cmd |= NV_READ_OP; | |
160 | data = qla2x00_nvram_request(ha, nv_cmd); | |
161 | ||
162 | return (data); | |
163 | } | |
164 | ||
7b867cf7 AC |
165 | /** |
166 | * qla2x00_nv_deselect() - Deselect NVRAM operations. | |
167 | * @ha: HA context | |
168 | */ | |
169 | static void | |
170 | qla2x00_nv_deselect(struct qla_hw_data *ha) | |
171 | { | |
172 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
173 | ||
174 | WRT_REG_WORD(®->nvram, NVR_DESELECT); | |
175 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
176 | NVRAM_DELAY(); | |
177 | } | |
178 | ||
1da177e4 LT |
179 | /** |
180 | * qla2x00_write_nvram_word() - Write NVRAM data. | |
181 | * @ha: HA context | |
182 | * @addr: Address in NVRAM to write | |
183 | * @data: word to program | |
184 | */ | |
a824ebb3 | 185 | static void |
7b867cf7 | 186 | qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data) |
1da177e4 LT |
187 | { |
188 | int count; | |
189 | uint16_t word; | |
45aeaf1e | 190 | uint32_t nv_cmd, wait_cnt; |
3d71644c | 191 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
7c3df132 | 192 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
1da177e4 LT |
193 | |
194 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
195 | qla2x00_nv_write(ha, 0); | |
196 | qla2x00_nv_write(ha, 0); | |
197 | ||
198 | for (word = 0; word < 8; word++) | |
199 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
200 | ||
201 | qla2x00_nv_deselect(ha); | |
202 | ||
203 | /* Write data */ | |
204 | nv_cmd = (addr << 16) | NV_WRITE_OP; | |
205 | nv_cmd |= data; | |
206 | nv_cmd <<= 5; | |
207 | for (count = 0; count < 27; count++) { | |
208 | if (nv_cmd & BIT_31) | |
209 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
210 | else | |
211 | qla2x00_nv_write(ha, 0); | |
212 | ||
213 | nv_cmd <<= 1; | |
214 | } | |
215 | ||
216 | qla2x00_nv_deselect(ha); | |
217 | ||
218 | /* Wait for NVRAM to become ready */ | |
219 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
dcb36ce9 | 220 | RD_REG_WORD(®->nvram); /* PCI Posting. */ |
45aeaf1e | 221 | wait_cnt = NVR_WAIT_CNT; |
1da177e4 | 222 | do { |
45aeaf1e | 223 | if (!--wait_cnt) { |
7c3df132 SK |
224 | ql_dbg(ql_dbg_user, vha, 0x708d, |
225 | "NVRAM didn't go ready...\n"); | |
45aeaf1e RA |
226 | break; |
227 | } | |
1da177e4 LT |
228 | NVRAM_DELAY(); |
229 | word = RD_REG_WORD(®->nvram); | |
230 | } while ((word & NVR_DATA_IN) == 0); | |
231 | ||
232 | qla2x00_nv_deselect(ha); | |
233 | ||
234 | /* Disable writes */ | |
235 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
236 | for (count = 0; count < 10; count++) | |
237 | qla2x00_nv_write(ha, 0); | |
238 | ||
239 | qla2x00_nv_deselect(ha); | |
240 | } | |
241 | ||
459c5378 | 242 | static int |
7b867cf7 AC |
243 | qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr, |
244 | uint16_t data, uint32_t tmo) | |
459c5378 AV |
245 | { |
246 | int ret, count; | |
247 | uint16_t word; | |
248 | uint32_t nv_cmd; | |
249 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
250 | ||
251 | ret = QLA_SUCCESS; | |
252 | ||
253 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
254 | qla2x00_nv_write(ha, 0); | |
255 | qla2x00_nv_write(ha, 0); | |
256 | ||
257 | for (word = 0; word < 8; word++) | |
258 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
259 | ||
260 | qla2x00_nv_deselect(ha); | |
261 | ||
262 | /* Write data */ | |
263 | nv_cmd = (addr << 16) | NV_WRITE_OP; | |
264 | nv_cmd |= data; | |
265 | nv_cmd <<= 5; | |
266 | for (count = 0; count < 27; count++) { | |
267 | if (nv_cmd & BIT_31) | |
268 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
269 | else | |
270 | qla2x00_nv_write(ha, 0); | |
271 | ||
272 | nv_cmd <<= 1; | |
273 | } | |
274 | ||
275 | qla2x00_nv_deselect(ha); | |
276 | ||
277 | /* Wait for NVRAM to become ready */ | |
278 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
dcb36ce9 | 279 | RD_REG_WORD(®->nvram); /* PCI Posting. */ |
459c5378 AV |
280 | do { |
281 | NVRAM_DELAY(); | |
282 | word = RD_REG_WORD(®->nvram); | |
283 | if (!--tmo) { | |
284 | ret = QLA_FUNCTION_FAILED; | |
285 | break; | |
286 | } | |
287 | } while ((word & NVR_DATA_IN) == 0); | |
288 | ||
289 | qla2x00_nv_deselect(ha); | |
290 | ||
291 | /* Disable writes */ | |
292 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
293 | for (count = 0; count < 10; count++) | |
294 | qla2x00_nv_write(ha, 0); | |
295 | ||
296 | qla2x00_nv_deselect(ha); | |
297 | ||
298 | return ret; | |
299 | } | |
300 | ||
459c5378 AV |
301 | /** |
302 | * qla2x00_clear_nvram_protection() - | |
303 | * @ha: HA context | |
304 | */ | |
305 | static int | |
7b867cf7 | 306 | qla2x00_clear_nvram_protection(struct qla_hw_data *ha) |
459c5378 AV |
307 | { |
308 | int ret, stat; | |
309 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
45aeaf1e | 310 | uint32_t word, wait_cnt; |
459c5378 | 311 | uint16_t wprot, wprot_old; |
7c3df132 | 312 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
459c5378 AV |
313 | |
314 | /* Clear NVRAM write protection. */ | |
315 | ret = QLA_FUNCTION_FAILED; | |
45aeaf1e RA |
316 | |
317 | wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); | |
318 | stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base, | |
459c5378 | 319 | __constant_cpu_to_le16(0x1234), 100000); |
45aeaf1e RA |
320 | wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); |
321 | if (stat != QLA_SUCCESS || wprot != 0x1234) { | |
459c5378 AV |
322 | /* Write enable. */ |
323 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
324 | qla2x00_nv_write(ha, 0); | |
325 | qla2x00_nv_write(ha, 0); | |
326 | for (word = 0; word < 8; word++) | |
327 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
328 | ||
329 | qla2x00_nv_deselect(ha); | |
330 | ||
331 | /* Enable protection register. */ | |
332 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
333 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
334 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
335 | for (word = 0; word < 8; word++) | |
336 | qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); | |
337 | ||
338 | qla2x00_nv_deselect(ha); | |
339 | ||
340 | /* Clear protection register (ffff is cleared). */ | |
341 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
342 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
343 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
344 | for (word = 0; word < 8; word++) | |
345 | qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); | |
346 | ||
347 | qla2x00_nv_deselect(ha); | |
348 | ||
349 | /* Wait for NVRAM to become ready. */ | |
350 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
dcb36ce9 | 351 | RD_REG_WORD(®->nvram); /* PCI Posting. */ |
45aeaf1e | 352 | wait_cnt = NVR_WAIT_CNT; |
459c5378 | 353 | do { |
45aeaf1e | 354 | if (!--wait_cnt) { |
7c3df132 SK |
355 | ql_dbg(ql_dbg_user, vha, 0x708e, |
356 | "NVRAM didn't go ready...\n"); | |
45aeaf1e RA |
357 | break; |
358 | } | |
459c5378 AV |
359 | NVRAM_DELAY(); |
360 | word = RD_REG_WORD(®->nvram); | |
361 | } while ((word & NVR_DATA_IN) == 0); | |
362 | ||
45aeaf1e RA |
363 | if (wait_cnt) |
364 | ret = QLA_SUCCESS; | |
459c5378 | 365 | } else |
45aeaf1e | 366 | qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old); |
459c5378 AV |
367 | |
368 | return ret; | |
369 | } | |
370 | ||
371 | static void | |
7b867cf7 | 372 | qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat) |
459c5378 AV |
373 | { |
374 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
45aeaf1e | 375 | uint32_t word, wait_cnt; |
7c3df132 | 376 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
459c5378 AV |
377 | |
378 | if (stat != QLA_SUCCESS) | |
379 | return; | |
380 | ||
381 | /* Set NVRAM write protection. */ | |
382 | /* Write enable. */ | |
383 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
384 | qla2x00_nv_write(ha, 0); | |
385 | qla2x00_nv_write(ha, 0); | |
386 | for (word = 0; word < 8; word++) | |
387 | qla2x00_nv_write(ha, NVR_DATA_OUT); | |
388 | ||
389 | qla2x00_nv_deselect(ha); | |
390 | ||
391 | /* Enable protection register. */ | |
392 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
393 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
394 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
395 | for (word = 0; word < 8; word++) | |
396 | qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); | |
397 | ||
398 | qla2x00_nv_deselect(ha); | |
399 | ||
400 | /* Enable protection register. */ | |
401 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
402 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
403 | qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); | |
404 | for (word = 0; word < 8; word++) | |
405 | qla2x00_nv_write(ha, NVR_PR_ENABLE); | |
406 | ||
407 | qla2x00_nv_deselect(ha); | |
408 | ||
409 | /* Wait for NVRAM to become ready. */ | |
410 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
dcb36ce9 | 411 | RD_REG_WORD(®->nvram); /* PCI Posting. */ |
45aeaf1e | 412 | wait_cnt = NVR_WAIT_CNT; |
459c5378 | 413 | do { |
45aeaf1e | 414 | if (!--wait_cnt) { |
7c3df132 SK |
415 | ql_dbg(ql_dbg_user, vha, 0x708f, |
416 | "NVRAM didn't go ready...\n"); | |
45aeaf1e RA |
417 | break; |
418 | } | |
459c5378 AV |
419 | NVRAM_DELAY(); |
420 | word = RD_REG_WORD(®->nvram); | |
421 | } while ((word & NVR_DATA_IN) == 0); | |
422 | } | |
423 | ||
424 | ||
425 | /*****************************************************************************/ | |
426 | /* Flash Manipulation Routines */ | |
427 | /*****************************************************************************/ | |
428 | ||
429 | static inline uint32_t | |
3a03eb79 | 430 | flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr) |
459c5378 | 431 | { |
3a03eb79 | 432 | return ha->flash_conf_off | faddr; |
459c5378 AV |
433 | } |
434 | ||
435 | static inline uint32_t | |
3a03eb79 | 436 | flash_data_addr(struct qla_hw_data *ha, uint32_t faddr) |
459c5378 | 437 | { |
3a03eb79 | 438 | return ha->flash_data_off | faddr; |
459c5378 AV |
439 | } |
440 | ||
441 | static inline uint32_t | |
3a03eb79 | 442 | nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr) |
459c5378 | 443 | { |
3a03eb79 | 444 | return ha->nvram_conf_off | naddr; |
459c5378 AV |
445 | } |
446 | ||
447 | static inline uint32_t | |
3a03eb79 | 448 | nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr) |
459c5378 | 449 | { |
3a03eb79 | 450 | return ha->nvram_data_off | naddr; |
459c5378 AV |
451 | } |
452 | ||
e5f82ab8 | 453 | static uint32_t |
7b867cf7 | 454 | qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr) |
459c5378 AV |
455 | { |
456 | int rval; | |
457 | uint32_t cnt, data; | |
458 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
459 | ||
460 | WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG); | |
461 | /* Wait for READ cycle to complete. */ | |
462 | rval = QLA_SUCCESS; | |
463 | for (cnt = 3000; | |
464 | (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 && | |
465 | rval == QLA_SUCCESS; cnt--) { | |
466 | if (cnt) | |
467 | udelay(10); | |
468 | else | |
469 | rval = QLA_FUNCTION_TIMEOUT; | |
40a2e34a | 470 | cond_resched(); |
459c5378 AV |
471 | } |
472 | ||
473 | /* TODO: What happens if we time out? */ | |
474 | data = 0xDEADDEAD; | |
475 | if (rval == QLA_SUCCESS) | |
476 | data = RD_REG_DWORD(®->flash_data); | |
477 | ||
478 | return data; | |
479 | } | |
480 | ||
481 | uint32_t * | |
7b867cf7 | 482 | qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, |
459c5378 AV |
483 | uint32_t dwords) |
484 | { | |
485 | uint32_t i; | |
3a03eb79 AV |
486 | struct qla_hw_data *ha = vha->hw; |
487 | ||
459c5378 AV |
488 | /* Dword reads to flash. */ |
489 | for (i = 0; i < dwords; i++, faddr++) | |
3a03eb79 AV |
490 | dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, |
491 | flash_data_addr(ha, faddr))); | |
459c5378 | 492 | |
459c5378 AV |
493 | return dwptr; |
494 | } | |
495 | ||
e5f82ab8 | 496 | static int |
7b867cf7 | 497 | qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data) |
459c5378 AV |
498 | { |
499 | int rval; | |
500 | uint32_t cnt; | |
501 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
502 | ||
503 | WRT_REG_DWORD(®->flash_data, data); | |
504 | RD_REG_DWORD(®->flash_data); /* PCI Posting. */ | |
505 | WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG); | |
506 | /* Wait for Write cycle to complete. */ | |
507 | rval = QLA_SUCCESS; | |
508 | for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) && | |
509 | rval == QLA_SUCCESS; cnt--) { | |
510 | if (cnt) | |
511 | udelay(10); | |
512 | else | |
513 | rval = QLA_FUNCTION_TIMEOUT; | |
40a2e34a | 514 | cond_resched(); |
459c5378 AV |
515 | } |
516 | return rval; | |
517 | } | |
518 | ||
e5f82ab8 | 519 | static void |
7b867cf7 | 520 | qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, |
459c5378 AV |
521 | uint8_t *flash_id) |
522 | { | |
523 | uint32_t ids; | |
524 | ||
3a03eb79 | 525 | ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab)); |
459c5378 AV |
526 | *man_id = LSB(ids); |
527 | *flash_id = MSB(ids); | |
45aeaf1e RA |
528 | |
529 | /* Check if man_id and flash_id are valid. */ | |
530 | if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) { | |
531 | /* Read information using 0x9f opcode | |
532 | * Device ID, Mfg ID would be read in the format: | |
533 | * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID> | |
534 | * Example: ATMEL 0x00 01 45 1F | |
535 | * Extract MFG and Dev ID from last two bytes. | |
536 | */ | |
3a03eb79 | 537 | ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f)); |
45aeaf1e RA |
538 | *man_id = LSB(ids); |
539 | *flash_id = MSB(ids); | |
540 | } | |
459c5378 AV |
541 | } |
542 | ||
c00d8994 | 543 | static int |
7b867cf7 | 544 | qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start) |
c00d8994 AV |
545 | { |
546 | const char *loc, *locations[] = { "DEF", "PCI" }; | |
547 | uint32_t pcihdr, pcids; | |
548 | uint32_t *dcode; | |
549 | uint8_t *buf, *bcode, last_image; | |
550 | uint16_t cnt, chksum, *wptr; | |
551 | struct qla_flt_location *fltl; | |
7b867cf7 | 552 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 553 | struct req_que *req = ha->req_q_map[0]; |
c00d8994 AV |
554 | |
555 | /* | |
556 | * FLT-location structure resides after the last PCI region. | |
557 | */ | |
558 | ||
559 | /* Begin with sane defaults. */ | |
560 | loc = locations[0]; | |
3a03eb79 AV |
561 | *start = 0; |
562 | if (IS_QLA24XX_TYPE(ha)) | |
563 | *start = FA_FLASH_LAYOUT_ADDR_24; | |
564 | else if (IS_QLA25XX(ha)) | |
565 | *start = FA_FLASH_LAYOUT_ADDR; | |
566 | else if (IS_QLA81XX(ha)) | |
567 | *start = FA_FLASH_LAYOUT_ADDR_81; | |
a9083016 GM |
568 | else if (IS_QLA82XX(ha)) { |
569 | *start = FA_FLASH_LAYOUT_ADDR_82; | |
570 | goto end; | |
6246b8a1 GM |
571 | } else if (IS_QLA83XX(ha)) { |
572 | *start = FA_FLASH_LAYOUT_ADDR_83; | |
573 | goto end; | |
a9083016 | 574 | } |
c00d8994 | 575 | /* Begin with first PCI expansion ROM header. */ |
7b867cf7 AC |
576 | buf = (uint8_t *)req->ring; |
577 | dcode = (uint32_t *)req->ring; | |
c00d8994 AV |
578 | pcihdr = 0; |
579 | last_image = 1; | |
580 | do { | |
581 | /* Verify PCI expansion ROM header. */ | |
7b867cf7 | 582 | qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); |
c00d8994 AV |
583 | bcode = buf + (pcihdr % 4); |
584 | if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) | |
585 | goto end; | |
586 | ||
587 | /* Locate PCI data structure. */ | |
588 | pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); | |
7b867cf7 | 589 | qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); |
c00d8994 AV |
590 | bcode = buf + (pcihdr % 4); |
591 | ||
592 | /* Validate signature of PCI data structure. */ | |
593 | if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || | |
594 | bcode[0x2] != 'I' || bcode[0x3] != 'R') | |
595 | goto end; | |
596 | ||
597 | last_image = bcode[0x15] & BIT_7; | |
598 | ||
599 | /* Locate next PCI expansion ROM. */ | |
600 | pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; | |
601 | } while (!last_image); | |
602 | ||
603 | /* Now verify FLT-location structure. */ | |
7b867cf7 AC |
604 | fltl = (struct qla_flt_location *)req->ring; |
605 | qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, | |
c00d8994 AV |
606 | sizeof(struct qla_flt_location) >> 2); |
607 | if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' || | |
608 | fltl->sig[2] != 'L' || fltl->sig[3] != 'T') | |
609 | goto end; | |
610 | ||
7b867cf7 | 611 | wptr = (uint16_t *)req->ring; |
c00d8994 AV |
612 | cnt = sizeof(struct qla_flt_location) >> 1; |
613 | for (chksum = 0; cnt; cnt--) | |
614 | chksum += le16_to_cpu(*wptr++); | |
615 | if (chksum) { | |
7c3df132 | 616 | ql_log(ql_log_fatal, vha, 0x0045, |
c00d8994 | 617 | "Inconsistent FLTL detected: checksum=0x%x.\n", chksum); |
7c3df132 SK |
618 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e, |
619 | buf, sizeof(struct qla_flt_location)); | |
c00d8994 AV |
620 | return QLA_FUNCTION_FAILED; |
621 | } | |
622 | ||
623 | /* Good data. Use specified location. */ | |
624 | loc = locations[1]; | |
79c13a74 HZ |
625 | *start = (le16_to_cpu(fltl->start_hi) << 16 | |
626 | le16_to_cpu(fltl->start_lo)) >> 2; | |
c00d8994 | 627 | end: |
7c3df132 SK |
628 | ql_dbg(ql_dbg_init, vha, 0x0046, |
629 | "FLTL[%s] = 0x%x.\n", | |
630 | loc, *start); | |
c00d8994 AV |
631 | return QLA_SUCCESS; |
632 | } | |
633 | ||
634 | static void | |
7b867cf7 | 635 | qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr) |
c00d8994 AV |
636 | { |
637 | const char *loc, *locations[] = { "DEF", "FLT" }; | |
3a03eb79 AV |
638 | const uint32_t def_fw[] = |
639 | { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 }; | |
640 | const uint32_t def_boot[] = | |
641 | { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 }; | |
642 | const uint32_t def_vpd_nvram[] = | |
643 | { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 }; | |
3d79038f AV |
644 | const uint32_t def_vpd0[] = |
645 | { 0, 0, FA_VPD0_ADDR_81 }; | |
646 | const uint32_t def_vpd1[] = | |
647 | { 0, 0, FA_VPD1_ADDR_81 }; | |
648 | const uint32_t def_nvram0[] = | |
649 | { 0, 0, FA_NVRAM0_ADDR_81 }; | |
650 | const uint32_t def_nvram1[] = | |
651 | { 0, 0, FA_NVRAM1_ADDR_81 }; | |
3a03eb79 AV |
652 | const uint32_t def_fdt[] = |
653 | { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR, | |
654 | FA_FLASH_DESCR_ADDR_81 }; | |
655 | const uint32_t def_npiv_conf0[] = | |
656 | { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR, | |
657 | FA_NPIV_CONF0_ADDR_81 }; | |
658 | const uint32_t def_npiv_conf1[] = | |
659 | { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR, | |
660 | FA_NPIV_CONF1_ADDR_81 }; | |
09ff701a SR |
661 | const uint32_t fcp_prio_cfg0[] = |
662 | { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25, | |
663 | 0 }; | |
664 | const uint32_t fcp_prio_cfg1[] = | |
665 | { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25, | |
666 | 0 }; | |
3a03eb79 | 667 | uint32_t def; |
c00d8994 AV |
668 | uint16_t *wptr; |
669 | uint16_t cnt, chksum; | |
670 | uint32_t start; | |
671 | struct qla_flt_header *flt; | |
672 | struct qla_flt_region *region; | |
7b867cf7 | 673 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 674 | struct req_que *req = ha->req_q_map[0]; |
c00d8994 | 675 | |
2f0f3f4f MI |
676 | def = 0; |
677 | if (IS_QLA25XX(ha)) | |
678 | def = 1; | |
679 | else if (IS_QLA81XX(ha)) | |
680 | def = 2; | |
ff8073ff AV |
681 | |
682 | /* Assign FCP prio region since older adapters may not have FLT, or | |
683 | FCP prio region in it's FLT. | |
684 | */ | |
685 | ha->flt_region_fcp_prio = ha->flags.port0 ? | |
686 | fcp_prio_cfg0[def] : fcp_prio_cfg1[def]; | |
687 | ||
c00d8994 | 688 | ha->flt_region_flt = flt_addr; |
7b867cf7 AC |
689 | wptr = (uint16_t *)req->ring; |
690 | flt = (struct qla_flt_header *)req->ring; | |
c00d8994 | 691 | region = (struct qla_flt_region *)&flt[1]; |
7b867cf7 | 692 | ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring, |
c00d8994 AV |
693 | flt_addr << 2, OPTROM_BURST_SIZE); |
694 | if (*wptr == __constant_cpu_to_le16(0xffff)) | |
695 | goto no_flash_data; | |
696 | if (flt->version != __constant_cpu_to_le16(1)) { | |
7c3df132 SK |
697 | ql_log(ql_log_warn, vha, 0x0047, |
698 | "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n", | |
c00d8994 | 699 | le16_to_cpu(flt->version), le16_to_cpu(flt->length), |
7c3df132 | 700 | le16_to_cpu(flt->checksum)); |
c00d8994 AV |
701 | goto no_flash_data; |
702 | } | |
703 | ||
704 | cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1; | |
705 | for (chksum = 0; cnt; cnt--) | |
706 | chksum += le16_to_cpu(*wptr++); | |
707 | if (chksum) { | |
7c3df132 SK |
708 | ql_log(ql_log_fatal, vha, 0x0048, |
709 | "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n", | |
c00d8994 | 710 | le16_to_cpu(flt->version), le16_to_cpu(flt->length), |
7c3df132 | 711 | le16_to_cpu(flt->checksum)); |
c00d8994 AV |
712 | goto no_flash_data; |
713 | } | |
714 | ||
715 | loc = locations[1]; | |
716 | cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); | |
717 | for ( ; cnt; cnt--, region++) { | |
718 | /* Store addresses as DWORD offsets. */ | |
719 | start = le32_to_cpu(region->start) >> 2; | |
7c3df132 SK |
720 | ql_dbg(ql_dbg_init, vha, 0x0049, |
721 | "FLT[%02x]: start=0x%x " | |
722 | "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), | |
723 | start, le32_to_cpu(region->end) >> 2, | |
724 | le32_to_cpu(region->size)); | |
c00d8994 | 725 | |
9088608e | 726 | switch (le32_to_cpu(region->code) & 0xff) { |
6246b8a1 GM |
727 | case FLT_REG_FCOE_FW: |
728 | if (!IS_QLA8031(ha)) | |
729 | break; | |
730 | ha->flt_region_fw = start; | |
731 | break; | |
c00d8994 | 732 | case FLT_REG_FW: |
6246b8a1 GM |
733 | if (IS_QLA8031(ha)) |
734 | break; | |
c00d8994 AV |
735 | ha->flt_region_fw = start; |
736 | break; | |
737 | case FLT_REG_BOOT_CODE: | |
738 | ha->flt_region_boot = start; | |
739 | break; | |
740 | case FLT_REG_VPD_0: | |
6246b8a1 GM |
741 | if (IS_QLA8031(ha)) |
742 | break; | |
c00d8994 | 743 | ha->flt_region_vpd_nvram = start; |
a9083016 GM |
744 | if (IS_QLA82XX(ha)) |
745 | break; | |
e5b68a61 | 746 | if (ha->flags.port0) |
3d79038f AV |
747 | ha->flt_region_vpd = start; |
748 | break; | |
749 | case FLT_REG_VPD_1: | |
6246b8a1 | 750 | if (IS_QLA82XX(ha) || IS_QLA8031(ha)) |
a9083016 | 751 | break; |
e5b68a61 | 752 | if (!ha->flags.port0) |
3d79038f AV |
753 | ha->flt_region_vpd = start; |
754 | break; | |
755 | case FLT_REG_NVRAM_0: | |
6246b8a1 GM |
756 | if (IS_QLA8031(ha)) |
757 | break; | |
e5b68a61 | 758 | if (ha->flags.port0) |
3d79038f AV |
759 | ha->flt_region_nvram = start; |
760 | break; | |
761 | case FLT_REG_NVRAM_1: | |
6246b8a1 GM |
762 | if (IS_QLA8031(ha)) |
763 | break; | |
e5b68a61 | 764 | if (!ha->flags.port0) |
3d79038f | 765 | ha->flt_region_nvram = start; |
c00d8994 AV |
766 | break; |
767 | case FLT_REG_FDT: | |
768 | ha->flt_region_fdt = start; | |
769 | break; | |
272976ca | 770 | case FLT_REG_NPIV_CONF_0: |
e5b68a61 | 771 | if (ha->flags.port0) |
272976ca AV |
772 | ha->flt_region_npiv_conf = start; |
773 | break; | |
774 | case FLT_REG_NPIV_CONF_1: | |
e5b68a61 | 775 | if (!ha->flags.port0) |
272976ca AV |
776 | ha->flt_region_npiv_conf = start; |
777 | break; | |
cbc8eb67 AV |
778 | case FLT_REG_GOLD_FW: |
779 | ha->flt_region_gold_fw = start; | |
780 | break; | |
09ff701a | 781 | case FLT_REG_FCP_PRIO_0: |
bfdaa761 | 782 | if (ha->flags.port0) |
09ff701a SR |
783 | ha->flt_region_fcp_prio = start; |
784 | break; | |
785 | case FLT_REG_FCP_PRIO_1: | |
bfdaa761 | 786 | if (!ha->flags.port0) |
09ff701a SR |
787 | ha->flt_region_fcp_prio = start; |
788 | break; | |
a9083016 GM |
789 | case FLT_REG_BOOT_CODE_82XX: |
790 | ha->flt_region_boot = start; | |
791 | break; | |
792 | case FLT_REG_FW_82XX: | |
793 | ha->flt_region_fw = start; | |
794 | break; | |
795 | case FLT_REG_GOLD_FW_82XX: | |
796 | ha->flt_region_gold_fw = start; | |
797 | break; | |
798 | case FLT_REG_BOOTLOAD_82XX: | |
799 | ha->flt_region_bootload = start; | |
800 | break; | |
801 | case FLT_REG_VPD_82XX: | |
802 | ha->flt_region_vpd = start; | |
803 | break; | |
6246b8a1 GM |
804 | case FLT_REG_FCOE_VPD_0: |
805 | if (!IS_QLA8031(ha)) | |
806 | break; | |
807 | ha->flt_region_vpd_nvram = start; | |
808 | if (ha->flags.port0) | |
809 | ha->flt_region_vpd = start; | |
810 | break; | |
811 | case FLT_REG_FCOE_VPD_1: | |
812 | if (!IS_QLA8031(ha)) | |
813 | break; | |
814 | if (!ha->flags.port0) | |
815 | ha->flt_region_vpd = start; | |
816 | break; | |
817 | case FLT_REG_FCOE_NVRAM_0: | |
818 | if (!IS_QLA8031(ha)) | |
819 | break; | |
820 | if (ha->flags.port0) | |
821 | ha->flt_region_nvram = start; | |
822 | break; | |
823 | case FLT_REG_FCOE_NVRAM_1: | |
824 | if (!IS_QLA8031(ha)) | |
825 | break; | |
826 | if (!ha->flags.port0) | |
827 | ha->flt_region_nvram = start; | |
828 | break; | |
c00d8994 AV |
829 | } |
830 | } | |
831 | goto done; | |
832 | ||
833 | no_flash_data: | |
834 | /* Use hardcoded defaults. */ | |
835 | loc = locations[0]; | |
3a03eb79 AV |
836 | ha->flt_region_fw = def_fw[def]; |
837 | ha->flt_region_boot = def_boot[def]; | |
838 | ha->flt_region_vpd_nvram = def_vpd_nvram[def]; | |
e5b68a61 | 839 | ha->flt_region_vpd = ha->flags.port0 ? |
09ff701a | 840 | def_vpd0[def] : def_vpd1[def]; |
e5b68a61 | 841 | ha->flt_region_nvram = ha->flags.port0 ? |
09ff701a | 842 | def_nvram0[def] : def_nvram1[def]; |
3a03eb79 | 843 | ha->flt_region_fdt = def_fdt[def]; |
e5b68a61 | 844 | ha->flt_region_npiv_conf = ha->flags.port0 ? |
09ff701a | 845 | def_npiv_conf0[def] : def_npiv_conf1[def]; |
c00d8994 | 846 | done: |
7c3df132 | 847 | ql_dbg(ql_dbg_init, vha, 0x004a, |
6246b8a1 GM |
848 | "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x " |
849 | "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n", | |
850 | loc, ha->flt_region_boot, ha->flt_region_fw, | |
851 | ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram, | |
852 | ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf, | |
853 | ha->flt_region_fcp_prio); | |
c00d8994 AV |
854 | } |
855 | ||
856 | static void | |
7b867cf7 | 857 | qla2xxx_get_fdt_info(scsi_qla_host_t *vha) |
7d232c74 | 858 | { |
821b3996 | 859 | #define FLASH_BLK_SIZE_4K 0x1000 |
7d232c74 AV |
860 | #define FLASH_BLK_SIZE_32K 0x8000 |
861 | #define FLASH_BLK_SIZE_64K 0x10000 | |
c00d8994 | 862 | const char *loc, *locations[] = { "MID", "FDT" }; |
7d232c74 AV |
863 | uint16_t cnt, chksum; |
864 | uint16_t *wptr; | |
865 | struct qla_fdt_layout *fdt; | |
866 | uint8_t man_id, flash_id; | |
a9083016 | 867 | uint16_t mid = 0, fid = 0; |
7b867cf7 | 868 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 869 | struct req_que *req = ha->req_q_map[0]; |
7d232c74 | 870 | |
7b867cf7 AC |
871 | wptr = (uint16_t *)req->ring; |
872 | fdt = (struct qla_fdt_layout *)req->ring; | |
873 | ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring, | |
c00d8994 | 874 | ha->flt_region_fdt << 2, OPTROM_BURST_SIZE); |
7d232c74 AV |
875 | if (*wptr == __constant_cpu_to_le16(0xffff)) |
876 | goto no_flash_data; | |
877 | if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || | |
878 | fdt->sig[3] != 'D') | |
879 | goto no_flash_data; | |
880 | ||
881 | for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1; | |
882 | cnt++) | |
883 | chksum += le16_to_cpu(*wptr++); | |
884 | if (chksum) { | |
7c3df132 SK |
885 | ql_dbg(ql_dbg_init, vha, 0x004c, |
886 | "Inconsistent FDT detected:" | |
887 | " checksum=0x%x id=%c version0x%x.\n", chksum, | |
888 | fdt->sig[0], le16_to_cpu(fdt->version)); | |
889 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113, | |
890 | (uint8_t *)fdt, sizeof(*fdt)); | |
7d232c74 AV |
891 | goto no_flash_data; |
892 | } | |
893 | ||
c00d8994 AV |
894 | loc = locations[1]; |
895 | mid = le16_to_cpu(fdt->man_id); | |
896 | fid = le16_to_cpu(fdt->id); | |
7d232c74 | 897 | ha->fdt_wrt_disable = fdt->wrt_disable_bits; |
3a03eb79 | 898 | ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd); |
7d232c74 AV |
899 | ha->fdt_block_size = le32_to_cpu(fdt->block_size); |
900 | if (fdt->unprotect_sec_cmd) { | |
3a03eb79 | 901 | ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 | |
7d232c74 AV |
902 | fdt->unprotect_sec_cmd); |
903 | ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? | |
3a03eb79 AV |
904 | flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd): |
905 | flash_conf_addr(ha, 0x0336); | |
7d232c74 | 906 | } |
c00d8994 | 907 | goto done; |
7d232c74 | 908 | no_flash_data: |
c00d8994 | 909 | loc = locations[0]; |
a9083016 GM |
910 | if (IS_QLA82XX(ha)) { |
911 | ha->fdt_block_size = FLASH_BLK_SIZE_64K; | |
912 | goto done; | |
913 | } | |
7d232c74 | 914 | qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id); |
c00d8994 AV |
915 | mid = man_id; |
916 | fid = flash_id; | |
7d232c74 | 917 | ha->fdt_wrt_disable = 0x9c; |
3a03eb79 | 918 | ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8); |
7d232c74 AV |
919 | switch (man_id) { |
920 | case 0xbf: /* STT flash. */ | |
921 | if (flash_id == 0x8e) | |
922 | ha->fdt_block_size = FLASH_BLK_SIZE_64K; | |
923 | else | |
924 | ha->fdt_block_size = FLASH_BLK_SIZE_32K; | |
925 | ||
926 | if (flash_id == 0x80) | |
3a03eb79 | 927 | ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352); |
7d232c74 AV |
928 | break; |
929 | case 0x13: /* ST M25P80. */ | |
930 | ha->fdt_block_size = FLASH_BLK_SIZE_64K; | |
931 | break; | |
932 | case 0x1f: /* Atmel 26DF081A. */ | |
821b3996 | 933 | ha->fdt_block_size = FLASH_BLK_SIZE_4K; |
3a03eb79 AV |
934 | ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320); |
935 | ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339); | |
936 | ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336); | |
7d232c74 AV |
937 | break; |
938 | default: | |
939 | /* Default to 64 kb sector size. */ | |
940 | ha->fdt_block_size = FLASH_BLK_SIZE_64K; | |
941 | break; | |
942 | } | |
c00d8994 | 943 | done: |
7c3df132 | 944 | ql_dbg(ql_dbg_init, vha, 0x004d, |
d8424f68 JP |
945 | "FDT[%s]: (0x%x/0x%x) erase=0x%x " |
946 | "pr=%x wrtd=0x%x blk=0x%x.\n", | |
947 | loc, mid, fid, | |
7d232c74 | 948 | ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd, |
7c3df132 SK |
949 | ha->fdt_wrt_disable, ha->fdt_block_size); |
950 | ||
7d232c74 AV |
951 | } |
952 | ||
a9083016 GM |
953 | static void |
954 | qla2xxx_get_idc_param(scsi_qla_host_t *vha) | |
955 | { | |
956 | #define QLA82XX_IDC_PARAM_ADDR 0x003e885c | |
957 | uint32_t *wptr; | |
958 | struct qla_hw_data *ha = vha->hw; | |
959 | struct req_que *req = ha->req_q_map[0]; | |
960 | ||
961 | if (!IS_QLA82XX(ha)) | |
962 | return; | |
963 | ||
964 | wptr = (uint32_t *)req->ring; | |
965 | ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring, | |
966 | QLA82XX_IDC_PARAM_ADDR , 8); | |
967 | ||
968 | if (*wptr == __constant_cpu_to_le32(0xffffffff)) { | |
7d613ac6 SV |
969 | ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT; |
970 | ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT; | |
a9083016 | 971 | } else { |
7d613ac6 SV |
972 | ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr++); |
973 | ha->fcoe_reset_timeout = le32_to_cpu(*wptr); | |
a9083016 | 974 | } |
7c3df132 | 975 | ql_dbg(ql_dbg_init, vha, 0x004e, |
7d613ac6 SV |
976 | "fcoe_dev_init_timeout=%d " |
977 | "fcoe_reset_timeout=%d.\n", ha->fcoe_dev_init_timeout, | |
978 | ha->fcoe_reset_timeout); | |
a9083016 GM |
979 | return; |
980 | } | |
981 | ||
c00d8994 | 982 | int |
7b867cf7 | 983 | qla2xxx_get_flash_info(scsi_qla_host_t *vha) |
c00d8994 AV |
984 | { |
985 | int ret; | |
986 | uint32_t flt_addr; | |
7b867cf7 | 987 | struct qla_hw_data *ha = vha->hw; |
c00d8994 | 988 | |
6246b8a1 GM |
989 | if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && |
990 | !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha)) | |
c00d8994 AV |
991 | return QLA_SUCCESS; |
992 | ||
7b867cf7 | 993 | ret = qla2xxx_find_flt_start(vha, &flt_addr); |
c00d8994 AV |
994 | if (ret != QLA_SUCCESS) |
995 | return ret; | |
996 | ||
7b867cf7 AC |
997 | qla2xxx_get_flt_info(vha, flt_addr); |
998 | qla2xxx_get_fdt_info(vha); | |
a9083016 | 999 | qla2xxx_get_idc_param(vha); |
c00d8994 AV |
1000 | |
1001 | return QLA_SUCCESS; | |
1002 | } | |
1003 | ||
272976ca | 1004 | void |
7b867cf7 | 1005 | qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha) |
272976ca AV |
1006 | { |
1007 | #define NPIV_CONFIG_SIZE (16*1024) | |
1008 | void *data; | |
1009 | uint16_t *wptr; | |
1010 | uint16_t cnt, chksum; | |
73208dfd | 1011 | int i; |
272976ca AV |
1012 | struct qla_npiv_header hdr; |
1013 | struct qla_npiv_entry *entry; | |
7b867cf7 | 1014 | struct qla_hw_data *ha = vha->hw; |
272976ca | 1015 | |
6246b8a1 GM |
1016 | if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && |
1017 | !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha)) | |
272976ca AV |
1018 | return; |
1019 | ||
7d613ac6 | 1020 | if (ha->flags.nic_core_reset_hdlr_active) |
a49393f2 GM |
1021 | return; |
1022 | ||
7b867cf7 | 1023 | ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr, |
272976ca AV |
1024 | ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header)); |
1025 | if (hdr.version == __constant_cpu_to_le16(0xffff)) | |
1026 | return; | |
1027 | if (hdr.version != __constant_cpu_to_le16(1)) { | |
7c3df132 SK |
1028 | ql_dbg(ql_dbg_user, vha, 0x7090, |
1029 | "Unsupported NPIV-Config " | |
272976ca AV |
1030 | "detected: version=0x%x entries=0x%x checksum=0x%x.\n", |
1031 | le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), | |
7c3df132 | 1032 | le16_to_cpu(hdr.checksum)); |
272976ca AV |
1033 | return; |
1034 | } | |
1035 | ||
1036 | data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL); | |
1037 | if (!data) { | |
7c3df132 SK |
1038 | ql_log(ql_log_warn, vha, 0x7091, |
1039 | "Unable to allocate memory for data.\n"); | |
272976ca AV |
1040 | return; |
1041 | } | |
1042 | ||
7b867cf7 | 1043 | ha->isp_ops->read_optrom(vha, (uint8_t *)data, |
272976ca AV |
1044 | ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE); |
1045 | ||
1046 | cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) * | |
1047 | sizeof(struct qla_npiv_entry)) >> 1; | |
1048 | for (wptr = data, chksum = 0; cnt; cnt--) | |
1049 | chksum += le16_to_cpu(*wptr++); | |
1050 | if (chksum) { | |
7c3df132 SK |
1051 | ql_dbg(ql_dbg_user, vha, 0x7092, |
1052 | "Inconsistent NPIV-Config " | |
272976ca AV |
1053 | "detected: version=0x%x entries=0x%x checksum=0x%x.\n", |
1054 | le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), | |
7c3df132 | 1055 | le16_to_cpu(hdr.checksum)); |
272976ca AV |
1056 | goto done; |
1057 | } | |
1058 | ||
1059 | entry = data + sizeof(struct qla_npiv_header); | |
1060 | cnt = le16_to_cpu(hdr.entries); | |
73208dfd | 1061 | for (i = 0; cnt; cnt--, entry++, i++) { |
272976ca AV |
1062 | uint16_t flags; |
1063 | struct fc_vport_identifiers vid; | |
1064 | struct fc_vport *vport; | |
1065 | ||
40859ae5 AC |
1066 | memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry)); |
1067 | ||
272976ca AV |
1068 | flags = le16_to_cpu(entry->flags); |
1069 | if (flags == 0xffff) | |
1070 | continue; | |
1071 | if ((flags & BIT_0) == 0) | |
1072 | continue; | |
1073 | ||
1074 | memset(&vid, 0, sizeof(vid)); | |
1075 | vid.roles = FC_PORT_ROLE_FCP_INITIATOR; | |
1076 | vid.vport_type = FC_PORTTYPE_NPIV; | |
1077 | vid.disable = false; | |
1078 | vid.port_name = wwn_to_u64(entry->port_name); | |
1079 | vid.node_name = wwn_to_u64(entry->node_name); | |
1080 | ||
7c3df132 SK |
1081 | ql_dbg(ql_dbg_user, vha, 0x7093, |
1082 | "NPIV[%02x]: wwpn=%llx " | |
1083 | "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt, | |
1084 | (unsigned long long)vid.port_name, | |
1085 | (unsigned long long)vid.node_name, | |
1086 | le16_to_cpu(entry->vf_id), | |
1087 | entry->q_qos, entry->f_qos); | |
73208dfd AC |
1088 | |
1089 | if (i < QLA_PRECONFIG_VPORTS) { | |
1090 | vport = fc_vport_create(vha->host, 0, &vid); | |
1091 | if (!vport) | |
7c3df132 SK |
1092 | ql_log(ql_log_warn, vha, 0x7094, |
1093 | "NPIV-Config Failed to create vport [%02x]: " | |
1094 | "wwpn=%llx wwnn=%llx.\n", cnt, | |
1095 | (unsigned long long)vid.port_name, | |
1096 | (unsigned long long)vid.node_name); | |
73208dfd | 1097 | } |
272976ca AV |
1098 | } |
1099 | done: | |
1100 | kfree(data); | |
1101 | } | |
1102 | ||
1d2874de JC |
1103 | static int |
1104 | qla24xx_unprotect_flash(scsi_qla_host_t *vha) | |
cb8dacbf | 1105 | { |
1d2874de | 1106 | struct qla_hw_data *ha = vha->hw; |
cb8dacbf AV |
1107 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
1108 | ||
1d2874de JC |
1109 | if (ha->flags.fac_supported) |
1110 | return qla81xx_fac_do_write_enable(vha, 1); | |
1111 | ||
cb8dacbf AV |
1112 | /* Enable flash write. */ |
1113 | WRT_REG_DWORD(®->ctrl_status, | |
1114 | RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); | |
1115 | RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ | |
1116 | ||
7d232c74 | 1117 | if (!ha->fdt_wrt_disable) |
1d2874de | 1118 | goto done; |
7d232c74 | 1119 | |
b872ca40 | 1120 | /* Disable flash write-protection, first clear SR protection bit */ |
3a03eb79 | 1121 | qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); |
b872ca40 | 1122 | /* Then write zero again to clear remaining SR bits.*/ |
3a03eb79 | 1123 | qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); |
1d2874de JC |
1124 | done: |
1125 | return QLA_SUCCESS; | |
cb8dacbf AV |
1126 | } |
1127 | ||
1d2874de JC |
1128 | static int |
1129 | qla24xx_protect_flash(scsi_qla_host_t *vha) | |
cb8dacbf AV |
1130 | { |
1131 | uint32_t cnt; | |
1d2874de | 1132 | struct qla_hw_data *ha = vha->hw; |
cb8dacbf AV |
1133 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
1134 | ||
1d2874de JC |
1135 | if (ha->flags.fac_supported) |
1136 | return qla81xx_fac_do_write_enable(vha, 0); | |
1137 | ||
7d232c74 AV |
1138 | if (!ha->fdt_wrt_disable) |
1139 | goto skip_wrt_protect; | |
1140 | ||
cb8dacbf | 1141 | /* Enable flash write-protection and wait for completion. */ |
3a03eb79 | 1142 | qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), |
7d232c74 | 1143 | ha->fdt_wrt_disable); |
cb8dacbf | 1144 | for (cnt = 300; cnt && |
3a03eb79 | 1145 | qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0; |
cb8dacbf AV |
1146 | cnt--) { |
1147 | udelay(10); | |
1148 | } | |
1149 | ||
7d232c74 | 1150 | skip_wrt_protect: |
cb8dacbf AV |
1151 | /* Disable flash write. */ |
1152 | WRT_REG_DWORD(®->ctrl_status, | |
1153 | RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); | |
1154 | RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ | |
1d2874de JC |
1155 | |
1156 | return QLA_SUCCESS; | |
1157 | } | |
1158 | ||
1159 | static int | |
1160 | qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata) | |
1161 | { | |
1162 | struct qla_hw_data *ha = vha->hw; | |
1163 | uint32_t start, finish; | |
1164 | ||
1165 | if (ha->flags.fac_supported) { | |
1166 | start = fdata >> 2; | |
1167 | finish = start + (ha->fdt_block_size >> 2) - 1; | |
1168 | return qla81xx_fac_erase_sector(vha, flash_data_addr(ha, | |
1169 | start), flash_data_addr(ha, finish)); | |
1170 | } | |
1171 | ||
1172 | return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd, | |
1173 | (fdata & 0xff00) | ((fdata << 16) & 0xff0000) | | |
1174 | ((fdata >> 16) & 0xff)); | |
cb8dacbf AV |
1175 | } |
1176 | ||
e5f82ab8 | 1177 | static int |
7b867cf7 | 1178 | qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, |
459c5378 AV |
1179 | uint32_t dwords) |
1180 | { | |
1181 | int ret; | |
7c283177 | 1182 | uint32_t liter; |
7d232c74 | 1183 | uint32_t sec_mask, rest_addr; |
85d0acbb | 1184 | uint32_t fdata; |
338c9161 AV |
1185 | dma_addr_t optrom_dma; |
1186 | void *optrom = NULL; | |
7b867cf7 | 1187 | struct qla_hw_data *ha = vha->hw; |
459c5378 | 1188 | |
338c9161 | 1189 | /* Prepare burst-capable write on supported ISPs. */ |
6246b8a1 GM |
1190 | if ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha)) && |
1191 | !(faddr & 0xfff) && dwords > OPTROM_BURST_DWORDS) { | |
338c9161 AV |
1192 | optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, |
1193 | &optrom_dma, GFP_KERNEL); | |
1194 | if (!optrom) { | |
7c3df132 SK |
1195 | ql_log(ql_log_warn, vha, 0x7095, |
1196 | "Unable to allocate " | |
1197 | "memory for optrom burst write (%x KB).\n", | |
1198 | OPTROM_BURST_SIZE / 1024); | |
338c9161 AV |
1199 | } |
1200 | } | |
1201 | ||
7d232c74 | 1202 | rest_addr = (ha->fdt_block_size >> 2) - 1; |
85d0acbb | 1203 | sec_mask = ~rest_addr; |
459c5378 | 1204 | |
1d2874de JC |
1205 | ret = qla24xx_unprotect_flash(vha); |
1206 | if (ret != QLA_SUCCESS) { | |
7c3df132 | 1207 | ql_log(ql_log_warn, vha, 0x7096, |
1d2874de JC |
1208 | "Unable to unprotect flash for update.\n"); |
1209 | goto done; | |
1210 | } | |
459c5378 | 1211 | |
338c9161 | 1212 | for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { |
85d0acbb | 1213 | fdata = (faddr & sec_mask) << 2; |
45aeaf1e | 1214 | |
338c9161 | 1215 | /* Are we at the beginning of a sector? */ |
85d0acbb | 1216 | if ((faddr & rest_addr) == 0) { |
7d232c74 AV |
1217 | /* Do sector unprotect. */ |
1218 | if (ha->fdt_unprotect_sec_cmd) | |
338c9161 | 1219 | qla24xx_write_flash_dword(ha, |
7d232c74 | 1220 | ha->fdt_unprotect_sec_cmd, |
338c9161 | 1221 | (fdata & 0xff00) | ((fdata << 16) & |
459c5378 | 1222 | 0xff0000) | ((fdata >> 16) & 0xff)); |
1d2874de | 1223 | ret = qla24xx_erase_sector(vha, fdata); |
338c9161 | 1224 | if (ret != QLA_SUCCESS) { |
7c3df132 SK |
1225 | ql_dbg(ql_dbg_user, vha, 0x7007, |
1226 | "Unable to erase erase sector: address=%x.\n", | |
1227 | faddr); | |
338c9161 | 1228 | break; |
459c5378 | 1229 | } |
338c9161 AV |
1230 | } |
1231 | ||
1232 | /* Go with burst-write. */ | |
94d6a2b3 | 1233 | if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { |
338c9161 | 1234 | /* Copy data to DMA'ble buffer. */ |
7c283177 | 1235 | memcpy(optrom, dwptr, OPTROM_BURST_SIZE); |
338c9161 | 1236 | |
7b867cf7 | 1237 | ret = qla2x00_load_ram(vha, optrom_dma, |
3a03eb79 | 1238 | flash_data_addr(ha, faddr), |
338c9161 | 1239 | OPTROM_BURST_DWORDS); |
459c5378 | 1240 | if (ret != QLA_SUCCESS) { |
7c3df132 | 1241 | ql_log(ql_log_warn, vha, 0x7097, |
338c9161 AV |
1242 | "Unable to burst-write optrom segment " |
1243 | "(%x/%x/%llx).\n", ret, | |
3a03eb79 | 1244 | flash_data_addr(ha, faddr), |
875baf3c | 1245 | (unsigned long long)optrom_dma); |
7c3df132 | 1246 | ql_log(ql_log_warn, vha, 0x7098, |
338c9161 AV |
1247 | "Reverting to slow-write.\n"); |
1248 | ||
1249 | dma_free_coherent(&ha->pdev->dev, | |
1250 | OPTROM_BURST_SIZE, optrom, optrom_dma); | |
1251 | optrom = NULL; | |
1252 | } else { | |
1253 | liter += OPTROM_BURST_DWORDS - 1; | |
1254 | faddr += OPTROM_BURST_DWORDS - 1; | |
1255 | dwptr += OPTROM_BURST_DWORDS - 1; | |
1256 | continue; | |
459c5378 | 1257 | } |
338c9161 | 1258 | } |
45aeaf1e | 1259 | |
338c9161 | 1260 | ret = qla24xx_write_flash_dword(ha, |
3a03eb79 | 1261 | flash_data_addr(ha, faddr), cpu_to_le32(*dwptr)); |
338c9161 | 1262 | if (ret != QLA_SUCCESS) { |
7c3df132 SK |
1263 | ql_dbg(ql_dbg_user, vha, 0x7006, |
1264 | "Unable to program flash address=%x data=%x.\n", | |
1265 | faddr, *dwptr); | |
338c9161 | 1266 | break; |
459c5378 | 1267 | } |
338c9161 | 1268 | |
7d232c74 AV |
1269 | /* Do sector protect. */ |
1270 | if (ha->fdt_unprotect_sec_cmd && | |
338c9161 AV |
1271 | ((faddr & rest_addr) == rest_addr)) |
1272 | qla24xx_write_flash_dword(ha, | |
7d232c74 | 1273 | ha->fdt_protect_sec_cmd, |
338c9161 AV |
1274 | (fdata & 0xff00) | ((fdata << 16) & |
1275 | 0xff0000) | ((fdata >> 16) & 0xff)); | |
1276 | } | |
459c5378 | 1277 | |
1d2874de JC |
1278 | ret = qla24xx_protect_flash(vha); |
1279 | if (ret != QLA_SUCCESS) | |
7c3df132 | 1280 | ql_log(ql_log_warn, vha, 0x7099, |
1d2874de JC |
1281 | "Unable to protect flash after update.\n"); |
1282 | done: | |
338c9161 AV |
1283 | if (optrom) |
1284 | dma_free_coherent(&ha->pdev->dev, | |
1285 | OPTROM_BURST_SIZE, optrom, optrom_dma); | |
1286 | ||
459c5378 AV |
1287 | return ret; |
1288 | } | |
1289 | ||
1290 | uint8_t * | |
7b867cf7 | 1291 | qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, |
459c5378 AV |
1292 | uint32_t bytes) |
1293 | { | |
1294 | uint32_t i; | |
1295 | uint16_t *wptr; | |
7b867cf7 | 1296 | struct qla_hw_data *ha = vha->hw; |
459c5378 AV |
1297 | |
1298 | /* Word reads to NVRAM via registers. */ | |
1299 | wptr = (uint16_t *)buf; | |
1300 | qla2x00_lock_nvram_access(ha); | |
1301 | for (i = 0; i < bytes >> 1; i++, naddr++) | |
1302 | wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha, | |
1303 | naddr)); | |
1304 | qla2x00_unlock_nvram_access(ha); | |
1305 | ||
1306 | return buf; | |
1307 | } | |
1308 | ||
1309 | uint8_t * | |
7b867cf7 | 1310 | qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, |
459c5378 AV |
1311 | uint32_t bytes) |
1312 | { | |
1313 | uint32_t i; | |
1314 | uint32_t *dwptr; | |
3a03eb79 | 1315 | struct qla_hw_data *ha = vha->hw; |
459c5378 | 1316 | |
a9083016 GM |
1317 | if (IS_QLA82XX(ha)) |
1318 | return buf; | |
1319 | ||
459c5378 AV |
1320 | /* Dword reads to flash. */ |
1321 | dwptr = (uint32_t *)buf; | |
1322 | for (i = 0; i < bytes >> 2; i++, naddr++) | |
3a03eb79 AV |
1323 | dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, |
1324 | nvram_data_addr(ha, naddr))); | |
459c5378 | 1325 | |
459c5378 AV |
1326 | return buf; |
1327 | } | |
1328 | ||
1329 | int | |
7b867cf7 | 1330 | qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, |
459c5378 AV |
1331 | uint32_t bytes) |
1332 | { | |
1333 | int ret, stat; | |
1334 | uint32_t i; | |
1335 | uint16_t *wptr; | |
2c96d8d0 | 1336 | unsigned long flags; |
7b867cf7 | 1337 | struct qla_hw_data *ha = vha->hw; |
459c5378 AV |
1338 | |
1339 | ret = QLA_SUCCESS; | |
1340 | ||
2c96d8d0 | 1341 | spin_lock_irqsave(&ha->hardware_lock, flags); |
459c5378 AV |
1342 | qla2x00_lock_nvram_access(ha); |
1343 | ||
1344 | /* Disable NVRAM write-protection. */ | |
1345 | stat = qla2x00_clear_nvram_protection(ha); | |
1346 | ||
1347 | wptr = (uint16_t *)buf; | |
1348 | for (i = 0; i < bytes >> 1; i++, naddr++) { | |
1349 | qla2x00_write_nvram_word(ha, naddr, | |
1350 | cpu_to_le16(*wptr)); | |
1351 | wptr++; | |
1352 | } | |
1353 | ||
1354 | /* Enable NVRAM write-protection. */ | |
1355 | qla2x00_set_nvram_protection(ha, stat); | |
1356 | ||
1357 | qla2x00_unlock_nvram_access(ha); | |
2c96d8d0 | 1358 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
459c5378 AV |
1359 | |
1360 | return ret; | |
1361 | } | |
1362 | ||
1363 | int | |
7b867cf7 | 1364 | qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, |
459c5378 AV |
1365 | uint32_t bytes) |
1366 | { | |
1367 | int ret; | |
1368 | uint32_t i; | |
1369 | uint32_t *dwptr; | |
7b867cf7 | 1370 | struct qla_hw_data *ha = vha->hw; |
459c5378 AV |
1371 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
1372 | ||
1373 | ret = QLA_SUCCESS; | |
1374 | ||
a9083016 GM |
1375 | if (IS_QLA82XX(ha)) |
1376 | return ret; | |
1377 | ||
459c5378 AV |
1378 | /* Enable flash write. */ |
1379 | WRT_REG_DWORD(®->ctrl_status, | |
1380 | RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); | |
1381 | RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ | |
1382 | ||
1383 | /* Disable NVRAM write-protection. */ | |
3a03eb79 AV |
1384 | qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); |
1385 | qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); | |
459c5378 AV |
1386 | |
1387 | /* Dword writes to flash. */ | |
1388 | dwptr = (uint32_t *)buf; | |
1389 | for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) { | |
1390 | ret = qla24xx_write_flash_dword(ha, | |
3a03eb79 | 1391 | nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr)); |
459c5378 | 1392 | if (ret != QLA_SUCCESS) { |
7c3df132 | 1393 | ql_dbg(ql_dbg_user, vha, 0x709a, |
7640335e | 1394 | "Unable to program nvram address=%x data=%x.\n", |
7c3df132 | 1395 | naddr, *dwptr); |
459c5378 AV |
1396 | break; |
1397 | } | |
1398 | } | |
1399 | ||
1400 | /* Enable NVRAM write-protection. */ | |
3a03eb79 | 1401 | qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c); |
459c5378 AV |
1402 | |
1403 | /* Disable flash write. */ | |
1404 | WRT_REG_DWORD(®->ctrl_status, | |
1405 | RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); | |
1406 | RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ | |
1407 | ||
459c5378 AV |
1408 | return ret; |
1409 | } | |
f6df144c | 1410 | |
c3a2f0df | 1411 | uint8_t * |
7b867cf7 | 1412 | qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, |
c3a2f0df AV |
1413 | uint32_t bytes) |
1414 | { | |
1415 | uint32_t i; | |
1416 | uint32_t *dwptr; | |
7b867cf7 | 1417 | struct qla_hw_data *ha = vha->hw; |
c3a2f0df AV |
1418 | |
1419 | /* Dword reads to flash. */ | |
1420 | dwptr = (uint32_t *)buf; | |
1421 | for (i = 0; i < bytes >> 2; i++, naddr++) | |
1422 | dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, | |
3a03eb79 | 1423 | flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr))); |
c3a2f0df AV |
1424 | |
1425 | return buf; | |
1426 | } | |
1427 | ||
1428 | int | |
7b867cf7 | 1429 | qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, |
c3a2f0df AV |
1430 | uint32_t bytes) |
1431 | { | |
7b867cf7 | 1432 | struct qla_hw_data *ha = vha->hw; |
2c96d8d0 AV |
1433 | #define RMW_BUFFER_SIZE (64 * 1024) |
1434 | uint8_t *dbuf; | |
1435 | ||
1436 | dbuf = vmalloc(RMW_BUFFER_SIZE); | |
1437 | if (!dbuf) | |
1438 | return QLA_MEMORY_ALLOC_FAILED; | |
7b867cf7 | 1439 | ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, |
2c96d8d0 AV |
1440 | RMW_BUFFER_SIZE); |
1441 | memcpy(dbuf + (naddr << 2), buf, bytes); | |
7b867cf7 | 1442 | ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, |
2c96d8d0 AV |
1443 | RMW_BUFFER_SIZE); |
1444 | vfree(dbuf); | |
1445 | ||
1446 | return QLA_SUCCESS; | |
c3a2f0df | 1447 | } |
f6df144c | 1448 | |
1449 | static inline void | |
7b867cf7 | 1450 | qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) |
f6df144c | 1451 | { |
1452 | if (IS_QLA2322(ha)) { | |
1453 | /* Flip all colors. */ | |
1454 | if (ha->beacon_color_state == QLA_LED_ALL_ON) { | |
1455 | /* Turn off. */ | |
1456 | ha->beacon_color_state = 0; | |
1457 | *pflags = GPIO_LED_ALL_OFF; | |
1458 | } else { | |
1459 | /* Turn on. */ | |
1460 | ha->beacon_color_state = QLA_LED_ALL_ON; | |
1461 | *pflags = GPIO_LED_RGA_ON; | |
1462 | } | |
1463 | } else { | |
1464 | /* Flip green led only. */ | |
1465 | if (ha->beacon_color_state == QLA_LED_GRN_ON) { | |
1466 | /* Turn off. */ | |
1467 | ha->beacon_color_state = 0; | |
1468 | *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF; | |
1469 | } else { | |
1470 | /* Turn on. */ | |
1471 | ha->beacon_color_state = QLA_LED_GRN_ON; | |
1472 | *pflags = GPIO_LED_GREEN_ON_AMBER_OFF; | |
1473 | } | |
1474 | } | |
1475 | } | |
1476 | ||
948882f6 AV |
1477 | #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r)) |
1478 | ||
f6df144c | 1479 | void |
7b867cf7 | 1480 | qla2x00_beacon_blink(struct scsi_qla_host *vha) |
f6df144c | 1481 | { |
1482 | uint16_t gpio_enable; | |
1483 | uint16_t gpio_data; | |
1484 | uint16_t led_color = 0; | |
1485 | unsigned long flags; | |
7b867cf7 | 1486 | struct qla_hw_data *ha = vha->hw; |
f6df144c | 1487 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1488 | ||
a9083016 GM |
1489 | if (IS_QLA82XX(ha)) |
1490 | return; | |
1491 | ||
f6df144c | 1492 | spin_lock_irqsave(&ha->hardware_lock, flags); |
1493 | ||
1494 | /* Save the Original GPIOE. */ | |
1495 | if (ha->pio_address) { | |
948882f6 AV |
1496 | gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); |
1497 | gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); | |
f6df144c | 1498 | } else { |
1499 | gpio_enable = RD_REG_WORD(®->gpioe); | |
1500 | gpio_data = RD_REG_WORD(®->gpiod); | |
1501 | } | |
1502 | ||
1503 | /* Set the modified gpio_enable values */ | |
1504 | gpio_enable |= GPIO_LED_MASK; | |
1505 | ||
1506 | if (ha->pio_address) { | |
948882f6 | 1507 | WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); |
f6df144c | 1508 | } else { |
1509 | WRT_REG_WORD(®->gpioe, gpio_enable); | |
1510 | RD_REG_WORD(®->gpioe); | |
1511 | } | |
1512 | ||
1513 | qla2x00_flip_colors(ha, &led_color); | |
1514 | ||
1515 | /* Clear out any previously set LED color. */ | |
1516 | gpio_data &= ~GPIO_LED_MASK; | |
1517 | ||
1518 | /* Set the new input LED color to GPIOD. */ | |
1519 | gpio_data |= led_color; | |
1520 | ||
1521 | /* Set the modified gpio_data values */ | |
1522 | if (ha->pio_address) { | |
948882f6 | 1523 | WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); |
f6df144c | 1524 | } else { |
1525 | WRT_REG_WORD(®->gpiod, gpio_data); | |
1526 | RD_REG_WORD(®->gpiod); | |
1527 | } | |
1528 | ||
1529 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1530 | } | |
1531 | ||
1532 | int | |
7b867cf7 | 1533 | qla2x00_beacon_on(struct scsi_qla_host *vha) |
f6df144c | 1534 | { |
1535 | uint16_t gpio_enable; | |
1536 | uint16_t gpio_data; | |
1537 | unsigned long flags; | |
7b867cf7 | 1538 | struct qla_hw_data *ha = vha->hw; |
f6df144c | 1539 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1540 | ||
1541 | ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; | |
1542 | ha->fw_options[1] |= FO1_DISABLE_GPIO6_7; | |
1543 | ||
7b867cf7 | 1544 | if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { |
7c3df132 | 1545 | ql_log(ql_log_warn, vha, 0x709b, |
f6df144c | 1546 | "Unable to update fw options (beacon on).\n"); |
1547 | return QLA_FUNCTION_FAILED; | |
1548 | } | |
1549 | ||
f6df144c | 1550 | /* Turn off LEDs. */ |
1551 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1552 | if (ha->pio_address) { | |
948882f6 AV |
1553 | gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); |
1554 | gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); | |
f6df144c | 1555 | } else { |
1556 | gpio_enable = RD_REG_WORD(®->gpioe); | |
1557 | gpio_data = RD_REG_WORD(®->gpiod); | |
1558 | } | |
1559 | gpio_enable |= GPIO_LED_MASK; | |
1560 | ||
1561 | /* Set the modified gpio_enable values. */ | |
1562 | if (ha->pio_address) { | |
948882f6 | 1563 | WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); |
f6df144c | 1564 | } else { |
1565 | WRT_REG_WORD(®->gpioe, gpio_enable); | |
1566 | RD_REG_WORD(®->gpioe); | |
1567 | } | |
1568 | ||
1569 | /* Clear out previously set LED colour. */ | |
1570 | gpio_data &= ~GPIO_LED_MASK; | |
1571 | if (ha->pio_address) { | |
948882f6 | 1572 | WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); |
f6df144c | 1573 | } else { |
1574 | WRT_REG_WORD(®->gpiod, gpio_data); | |
1575 | RD_REG_WORD(®->gpiod); | |
1576 | } | |
1577 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1578 | ||
1579 | /* | |
1580 | * Let the per HBA timer kick off the blinking process based on | |
1581 | * the following flags. No need to do anything else now. | |
1582 | */ | |
1583 | ha->beacon_blink_led = 1; | |
1584 | ha->beacon_color_state = 0; | |
1585 | ||
1586 | return QLA_SUCCESS; | |
1587 | } | |
1588 | ||
1589 | int | |
7b867cf7 | 1590 | qla2x00_beacon_off(struct scsi_qla_host *vha) |
f6df144c | 1591 | { |
1592 | int rval = QLA_SUCCESS; | |
7b867cf7 | 1593 | struct qla_hw_data *ha = vha->hw; |
f6df144c | 1594 | |
1595 | ha->beacon_blink_led = 0; | |
1596 | ||
1597 | /* Set the on flag so when it gets flipped it will be off. */ | |
1598 | if (IS_QLA2322(ha)) | |
1599 | ha->beacon_color_state = QLA_LED_ALL_ON; | |
1600 | else | |
1601 | ha->beacon_color_state = QLA_LED_GRN_ON; | |
1602 | ||
7b867cf7 | 1603 | ha->isp_ops->beacon_blink(vha); /* This turns green LED off */ |
f6df144c | 1604 | |
1605 | ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; | |
1606 | ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; | |
1607 | ||
7b867cf7 | 1608 | rval = qla2x00_set_fw_options(vha, ha->fw_options); |
f6df144c | 1609 | if (rval != QLA_SUCCESS) |
7c3df132 | 1610 | ql_log(ql_log_warn, vha, 0x709c, |
f6df144c | 1611 | "Unable to update fw options (beacon off).\n"); |
1612 | return rval; | |
1613 | } | |
1614 | ||
1615 | ||
1616 | static inline void | |
7b867cf7 | 1617 | qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) |
f6df144c | 1618 | { |
1619 | /* Flip all colors. */ | |
1620 | if (ha->beacon_color_state == QLA_LED_ALL_ON) { | |
1621 | /* Turn off. */ | |
1622 | ha->beacon_color_state = 0; | |
1623 | *pflags = 0; | |
1624 | } else { | |
1625 | /* Turn on. */ | |
1626 | ha->beacon_color_state = QLA_LED_ALL_ON; | |
1627 | *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON; | |
1628 | } | |
1629 | } | |
1630 | ||
1631 | void | |
7b867cf7 | 1632 | qla24xx_beacon_blink(struct scsi_qla_host *vha) |
f6df144c | 1633 | { |
1634 | uint16_t led_color = 0; | |
1635 | uint32_t gpio_data; | |
1636 | unsigned long flags; | |
7b867cf7 | 1637 | struct qla_hw_data *ha = vha->hw; |
f6df144c | 1638 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
1639 | ||
1640 | /* Save the Original GPIOD. */ | |
1641 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1642 | gpio_data = RD_REG_DWORD(®->gpiod); | |
1643 | ||
1644 | /* Enable the gpio_data reg for update. */ | |
1645 | gpio_data |= GPDX_LED_UPDATE_MASK; | |
1646 | ||
1647 | WRT_REG_DWORD(®->gpiod, gpio_data); | |
1648 | gpio_data = RD_REG_DWORD(®->gpiod); | |
1649 | ||
1650 | /* Set the color bits. */ | |
1651 | qla24xx_flip_colors(ha, &led_color); | |
1652 | ||
1653 | /* Clear out any previously set LED color. */ | |
1654 | gpio_data &= ~GPDX_LED_COLOR_MASK; | |
1655 | ||
1656 | /* Set the new input LED color to GPIOD. */ | |
1657 | gpio_data |= led_color; | |
1658 | ||
1659 | /* Set the modified gpio_data values. */ | |
1660 | WRT_REG_DWORD(®->gpiod, gpio_data); | |
1661 | gpio_data = RD_REG_DWORD(®->gpiod); | |
1662 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1663 | } | |
1664 | ||
0143d8b7 CD |
1665 | static uint32_t |
1666 | qla83xx_select_led_port(struct qla_hw_data *ha) | |
1667 | { | |
1668 | uint32_t led_select_value = 0; | |
1669 | ||
1670 | if (!IS_QLA83XX(ha)) | |
1671 | goto out; | |
1672 | ||
1673 | if (ha->flags.port0) | |
1674 | led_select_value = QLA83XX_LED_PORT0; | |
1675 | else | |
1676 | led_select_value = QLA83XX_LED_PORT1; | |
1677 | ||
1678 | out: | |
1679 | return led_select_value; | |
1680 | } | |
1681 | ||
6246b8a1 GM |
1682 | void |
1683 | qla83xx_beacon_blink(struct scsi_qla_host *vha) | |
1684 | { | |
1685 | uint32_t led_select_value; | |
1686 | struct qla_hw_data *ha = vha->hw; | |
1687 | uint16_t led_cfg[6]; | |
1688 | uint16_t orig_led_cfg[6]; | |
0143d8b7 | 1689 | uint32_t led_10_value, led_43_value; |
6246b8a1 GM |
1690 | |
1691 | if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha)) | |
1692 | return; | |
1693 | ||
0143d8b7 CD |
1694 | if (!ha->beacon_blink_led) |
1695 | return; | |
1696 | ||
1697 | if (IS_QLA2031(ha)) { | |
1698 | led_select_value = qla83xx_select_led_port(ha); | |
6246b8a1 | 1699 | |
7d613ac6 SV |
1700 | qla83xx_wr_reg(vha, led_select_value, 0x40002000); |
1701 | qla83xx_wr_reg(vha, led_select_value + 4, 0x40002000); | |
6246b8a1 | 1702 | msleep(1000); |
7d613ac6 SV |
1703 | qla83xx_wr_reg(vha, led_select_value, 0x40004000); |
1704 | qla83xx_wr_reg(vha, led_select_value + 4, 0x40004000); | |
0143d8b7 CD |
1705 | } else if (IS_QLA8031(ha)) { |
1706 | led_select_value = qla83xx_select_led_port(ha); | |
1707 | ||
1708 | qla83xx_rd_reg(vha, led_select_value, &led_10_value); | |
1709 | qla83xx_rd_reg(vha, led_select_value + 0x10, &led_43_value); | |
1710 | qla83xx_wr_reg(vha, led_select_value, 0x01f44000); | |
1711 | msleep(500); | |
1712 | qla83xx_wr_reg(vha, led_select_value, 0x400001f4); | |
1713 | msleep(1000); | |
1714 | qla83xx_wr_reg(vha, led_select_value, led_10_value); | |
1715 | qla83xx_wr_reg(vha, led_select_value + 0x10, led_43_value); | |
1716 | } else if (IS_QLA81XX(ha)) { | |
6246b8a1 GM |
1717 | int rval; |
1718 | ||
1719 | /* Save Current */ | |
1720 | rval = qla81xx_get_led_config(vha, orig_led_cfg); | |
1721 | /* Do the blink */ | |
1722 | if (rval == QLA_SUCCESS) { | |
1723 | if (IS_QLA81XX(ha)) { | |
1724 | led_cfg[0] = 0x4000; | |
1725 | led_cfg[1] = 0x2000; | |
1726 | led_cfg[2] = 0; | |
1727 | led_cfg[3] = 0; | |
1728 | led_cfg[4] = 0; | |
1729 | led_cfg[5] = 0; | |
1730 | } else { | |
1731 | led_cfg[0] = 0x4000; | |
1732 | led_cfg[1] = 0x4000; | |
1733 | led_cfg[2] = 0x4000; | |
1734 | led_cfg[3] = 0x2000; | |
1735 | led_cfg[4] = 0; | |
1736 | led_cfg[5] = 0x2000; | |
1737 | } | |
1738 | rval = qla81xx_set_led_config(vha, led_cfg); | |
1739 | msleep(1000); | |
1740 | if (IS_QLA81XX(ha)) { | |
1741 | led_cfg[0] = 0x4000; | |
1742 | led_cfg[1] = 0x2000; | |
1743 | led_cfg[2] = 0; | |
1744 | } else { | |
1745 | led_cfg[0] = 0x4000; | |
1746 | led_cfg[1] = 0x2000; | |
1747 | led_cfg[2] = 0x4000; | |
1748 | led_cfg[3] = 0x4000; | |
1749 | led_cfg[4] = 0; | |
1750 | led_cfg[5] = 0x2000; | |
1751 | } | |
1752 | rval = qla81xx_set_led_config(vha, led_cfg); | |
1753 | } | |
1754 | /* On exit, restore original (presumes no status change) */ | |
1755 | qla81xx_set_led_config(vha, orig_led_cfg); | |
1756 | } | |
1757 | } | |
1758 | ||
f6df144c | 1759 | int |
7b867cf7 | 1760 | qla24xx_beacon_on(struct scsi_qla_host *vha) |
f6df144c | 1761 | { |
1762 | uint32_t gpio_data; | |
1763 | unsigned long flags; | |
7b867cf7 | 1764 | struct qla_hw_data *ha = vha->hw; |
f6df144c | 1765 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
1766 | ||
a9083016 GM |
1767 | if (IS_QLA82XX(ha)) |
1768 | return QLA_SUCCESS; | |
1769 | ||
6246b8a1 GM |
1770 | if (IS_QLA8031(ha) || IS_QLA81XX(ha)) |
1771 | goto skip_gpio; /* let blink handle it */ | |
1772 | ||
f6df144c | 1773 | if (ha->beacon_blink_led == 0) { |
1774 | /* Enable firmware for update */ | |
1775 | ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; | |
1776 | ||
7b867cf7 | 1777 | if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) |
f6df144c | 1778 | return QLA_FUNCTION_FAILED; |
1779 | ||
7b867cf7 | 1780 | if (qla2x00_get_fw_options(vha, ha->fw_options) != |
f6df144c | 1781 | QLA_SUCCESS) { |
7c3df132 | 1782 | ql_log(ql_log_warn, vha, 0x7009, |
f6df144c | 1783 | "Unable to update fw options (beacon on).\n"); |
1784 | return QLA_FUNCTION_FAILED; | |
1785 | } | |
1786 | ||
6246b8a1 GM |
1787 | if (IS_QLA2031(ha)) |
1788 | goto skip_gpio; | |
1789 | ||
f6df144c | 1790 | spin_lock_irqsave(&ha->hardware_lock, flags); |
1791 | gpio_data = RD_REG_DWORD(®->gpiod); | |
1792 | ||
1793 | /* Enable the gpio_data reg for update. */ | |
1794 | gpio_data |= GPDX_LED_UPDATE_MASK; | |
1795 | WRT_REG_DWORD(®->gpiod, gpio_data); | |
1796 | RD_REG_DWORD(®->gpiod); | |
1797 | ||
1798 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1799 | } | |
1800 | ||
1801 | /* So all colors blink together. */ | |
1802 | ha->beacon_color_state = 0; | |
1803 | ||
6246b8a1 | 1804 | skip_gpio: |
f6df144c | 1805 | /* Let the per HBA timer kick off the blinking process. */ |
1806 | ha->beacon_blink_led = 1; | |
1807 | ||
1808 | return QLA_SUCCESS; | |
1809 | } | |
1810 | ||
1811 | int | |
7b867cf7 | 1812 | qla24xx_beacon_off(struct scsi_qla_host *vha) |
f6df144c | 1813 | { |
1814 | uint32_t gpio_data; | |
1815 | unsigned long flags; | |
7b867cf7 | 1816 | struct qla_hw_data *ha = vha->hw; |
f6df144c | 1817 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
1818 | ||
a9083016 GM |
1819 | if (IS_QLA82XX(ha)) |
1820 | return QLA_SUCCESS; | |
1821 | ||
f6df144c | 1822 | ha->beacon_blink_led = 0; |
6246b8a1 GM |
1823 | |
1824 | if (IS_QLA2031(ha)) | |
1825 | goto set_fw_options; | |
1826 | ||
1827 | if (IS_QLA8031(ha) || IS_QLA81XX(ha)) | |
1828 | return QLA_SUCCESS; | |
1829 | ||
f6df144c | 1830 | ha->beacon_color_state = QLA_LED_ALL_ON; |
1831 | ||
7b867cf7 | 1832 | ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */ |
f6df144c | 1833 | |
1834 | /* Give control back to firmware. */ | |
1835 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1836 | gpio_data = RD_REG_DWORD(®->gpiod); | |
1837 | ||
1838 | /* Disable the gpio_data reg for update. */ | |
1839 | gpio_data &= ~GPDX_LED_UPDATE_MASK; | |
1840 | WRT_REG_DWORD(®->gpiod, gpio_data); | |
1841 | RD_REG_DWORD(®->gpiod); | |
1842 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1843 | ||
6246b8a1 | 1844 | set_fw_options: |
f6df144c | 1845 | ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL; |
1846 | ||
7b867cf7 | 1847 | if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { |
7c3df132 SK |
1848 | ql_log(ql_log_warn, vha, 0x704d, |
1849 | "Unable to update fw options (beacon on).\n"); | |
f6df144c | 1850 | return QLA_FUNCTION_FAILED; |
1851 | } | |
1852 | ||
7b867cf7 | 1853 | if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { |
7c3df132 SK |
1854 | ql_log(ql_log_warn, vha, 0x704e, |
1855 | "Unable to update fw options (beacon on).\n"); | |
f6df144c | 1856 | return QLA_FUNCTION_FAILED; |
1857 | } | |
1858 | ||
1859 | return QLA_SUCCESS; | |
1860 | } | |
854165f4 | 1861 | |
1862 | ||
1863 | /* | |
1864 | * Flash support routines | |
1865 | */ | |
1866 | ||
1867 | /** | |
1868 | * qla2x00_flash_enable() - Setup flash for reading and writing. | |
1869 | * @ha: HA context | |
1870 | */ | |
1871 | static void | |
7b867cf7 | 1872 | qla2x00_flash_enable(struct qla_hw_data *ha) |
854165f4 | 1873 | { |
1874 | uint16_t data; | |
1875 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1876 | ||
1877 | data = RD_REG_WORD(®->ctrl_status); | |
1878 | data |= CSR_FLASH_ENABLE; | |
1879 | WRT_REG_WORD(®->ctrl_status, data); | |
1880 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1881 | } | |
1882 | ||
1883 | /** | |
1884 | * qla2x00_flash_disable() - Disable flash and allow RISC to run. | |
1885 | * @ha: HA context | |
1886 | */ | |
1887 | static void | |
7b867cf7 | 1888 | qla2x00_flash_disable(struct qla_hw_data *ha) |
854165f4 | 1889 | { |
1890 | uint16_t data; | |
1891 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1892 | ||
1893 | data = RD_REG_WORD(®->ctrl_status); | |
1894 | data &= ~(CSR_FLASH_ENABLE); | |
1895 | WRT_REG_WORD(®->ctrl_status, data); | |
1896 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1897 | } | |
1898 | ||
1899 | /** | |
1900 | * qla2x00_read_flash_byte() - Reads a byte from flash | |
1901 | * @ha: HA context | |
1902 | * @addr: Address in flash to read | |
1903 | * | |
1904 | * A word is read from the chip, but, only the lower byte is valid. | |
1905 | * | |
1906 | * Returns the byte read from flash @addr. | |
1907 | */ | |
1908 | static uint8_t | |
7b867cf7 | 1909 | qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr) |
854165f4 | 1910 | { |
1911 | uint16_t data; | |
1912 | uint16_t bank_select; | |
1913 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1914 | ||
1915 | bank_select = RD_REG_WORD(®->ctrl_status); | |
1916 | ||
1917 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) { | |
1918 | /* Specify 64K address range: */ | |
1919 | /* clear out Module Select and Flash Address bits [19:16]. */ | |
1920 | bank_select &= ~0xf8; | |
1921 | bank_select |= addr >> 12 & 0xf0; | |
1922 | bank_select |= CSR_FLASH_64K_BANK; | |
1923 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
1924 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1925 | ||
1926 | WRT_REG_WORD(®->flash_address, (uint16_t)addr); | |
1927 | data = RD_REG_WORD(®->flash_data); | |
1928 | ||
1929 | return (uint8_t)data; | |
1930 | } | |
1931 | ||
1932 | /* Setup bit 16 of flash address. */ | |
1933 | if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { | |
1934 | bank_select |= CSR_FLASH_64K_BANK; | |
1935 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
1936 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1937 | } else if (((addr & BIT_16) == 0) && | |
1938 | (bank_select & CSR_FLASH_64K_BANK)) { | |
1939 | bank_select &= ~(CSR_FLASH_64K_BANK); | |
1940 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
1941 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1942 | } | |
1943 | ||
1944 | /* Always perform IO mapped accesses to the FLASH registers. */ | |
1945 | if (ha->pio_address) { | |
1946 | uint16_t data2; | |
1947 | ||
948882f6 | 1948 | WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); |
854165f4 | 1949 | do { |
948882f6 | 1950 | data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); |
854165f4 | 1951 | barrier(); |
1952 | cpu_relax(); | |
948882f6 | 1953 | data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); |
854165f4 | 1954 | } while (data != data2); |
1955 | } else { | |
1956 | WRT_REG_WORD(®->flash_address, (uint16_t)addr); | |
1957 | data = qla2x00_debounce_register(®->flash_data); | |
1958 | } | |
1959 | ||
1960 | return (uint8_t)data; | |
1961 | } | |
1962 | ||
1963 | /** | |
1964 | * qla2x00_write_flash_byte() - Write a byte to flash | |
1965 | * @ha: HA context | |
1966 | * @addr: Address in flash to write | |
1967 | * @data: Data to write | |
1968 | */ | |
1969 | static void | |
7b867cf7 | 1970 | qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data) |
854165f4 | 1971 | { |
1972 | uint16_t bank_select; | |
1973 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1974 | ||
1975 | bank_select = RD_REG_WORD(®->ctrl_status); | |
1976 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) { | |
1977 | /* Specify 64K address range: */ | |
1978 | /* clear out Module Select and Flash Address bits [19:16]. */ | |
1979 | bank_select &= ~0xf8; | |
1980 | bank_select |= addr >> 12 & 0xf0; | |
1981 | bank_select |= CSR_FLASH_64K_BANK; | |
1982 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
1983 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1984 | ||
1985 | WRT_REG_WORD(®->flash_address, (uint16_t)addr); | |
1986 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1987 | WRT_REG_WORD(®->flash_data, (uint16_t)data); | |
1988 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1989 | ||
1990 | return; | |
1991 | } | |
1992 | ||
1993 | /* Setup bit 16 of flash address. */ | |
1994 | if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { | |
1995 | bank_select |= CSR_FLASH_64K_BANK; | |
1996 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
1997 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
1998 | } else if (((addr & BIT_16) == 0) && | |
1999 | (bank_select & CSR_FLASH_64K_BANK)) { | |
2000 | bank_select &= ~(CSR_FLASH_64K_BANK); | |
2001 | WRT_REG_WORD(®->ctrl_status, bank_select); | |
2002 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
2003 | } | |
2004 | ||
2005 | /* Always perform IO mapped accesses to the FLASH registers. */ | |
2006 | if (ha->pio_address) { | |
948882f6 AV |
2007 | WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); |
2008 | WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data); | |
854165f4 | 2009 | } else { |
2010 | WRT_REG_WORD(®->flash_address, (uint16_t)addr); | |
2011 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
2012 | WRT_REG_WORD(®->flash_data, (uint16_t)data); | |
2013 | RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ | |
2014 | } | |
2015 | } | |
2016 | ||
2017 | /** | |
2018 | * qla2x00_poll_flash() - Polls flash for completion. | |
2019 | * @ha: HA context | |
2020 | * @addr: Address in flash to poll | |
2021 | * @poll_data: Data to be polled | |
2022 | * @man_id: Flash manufacturer ID | |
2023 | * @flash_id: Flash ID | |
2024 | * | |
2025 | * This function polls the device until bit 7 of what is read matches data | |
2026 | * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed | |
2027 | * out (a fatal error). The flash book recommeds reading bit 7 again after | |
2028 | * reading bit 5 as a 1. | |
2029 | * | |
2030 | * Returns 0 on success, else non-zero. | |
2031 | */ | |
2032 | static int | |
7b867cf7 | 2033 | qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data, |
854165f4 | 2034 | uint8_t man_id, uint8_t flash_id) |
2035 | { | |
2036 | int status; | |
2037 | uint8_t flash_data; | |
2038 | uint32_t cnt; | |
2039 | ||
2040 | status = 1; | |
2041 | ||
2042 | /* Wait for 30 seconds for command to finish. */ | |
2043 | poll_data &= BIT_7; | |
2044 | for (cnt = 3000000; cnt; cnt--) { | |
2045 | flash_data = qla2x00_read_flash_byte(ha, addr); | |
2046 | if ((flash_data & BIT_7) == poll_data) { | |
2047 | status = 0; | |
2048 | break; | |
2049 | } | |
2050 | ||
2051 | if (man_id != 0x40 && man_id != 0xda) { | |
2052 | if ((flash_data & BIT_5) && cnt > 2) | |
2053 | cnt = 2; | |
2054 | } | |
2055 | udelay(10); | |
2056 | barrier(); | |
40a2e34a | 2057 | cond_resched(); |
854165f4 | 2058 | } |
2059 | return status; | |
2060 | } | |
2061 | ||
854165f4 | 2062 | /** |
2063 | * qla2x00_program_flash_address() - Programs a flash address | |
2064 | * @ha: HA context | |
2065 | * @addr: Address in flash to program | |
2066 | * @data: Data to be written in flash | |
2067 | * @man_id: Flash manufacturer ID | |
2068 | * @flash_id: Flash ID | |
2069 | * | |
2070 | * Returns 0 on success, else non-zero. | |
2071 | */ | |
2072 | static int | |
7b867cf7 AC |
2073 | qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr, |
2074 | uint8_t data, uint8_t man_id, uint8_t flash_id) | |
854165f4 | 2075 | { |
2076 | /* Write Program Command Sequence. */ | |
2077 | if (IS_OEM_001(ha)) { | |
2078 | qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); | |
2079 | qla2x00_write_flash_byte(ha, 0x555, 0x55); | |
2080 | qla2x00_write_flash_byte(ha, 0xaaa, 0xa0); | |
2081 | qla2x00_write_flash_byte(ha, addr, data); | |
2082 | } else { | |
2083 | if (man_id == 0xda && flash_id == 0xc1) { | |
2084 | qla2x00_write_flash_byte(ha, addr, data); | |
2085 | if (addr & 0x7e) | |
2086 | return 0; | |
2087 | } else { | |
2088 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
2089 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
2090 | qla2x00_write_flash_byte(ha, 0x5555, 0xa0); | |
2091 | qla2x00_write_flash_byte(ha, addr, data); | |
2092 | } | |
2093 | } | |
2094 | ||
2095 | udelay(150); | |
2096 | ||
2097 | /* Wait for write to complete. */ | |
2098 | return qla2x00_poll_flash(ha, addr, data, man_id, flash_id); | |
2099 | } | |
2100 | ||
2101 | /** | |
2102 | * qla2x00_erase_flash() - Erase the flash. | |
2103 | * @ha: HA context | |
2104 | * @man_id: Flash manufacturer ID | |
2105 | * @flash_id: Flash ID | |
2106 | * | |
2107 | * Returns 0 on success, else non-zero. | |
2108 | */ | |
2109 | static int | |
7b867cf7 | 2110 | qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id) |
854165f4 | 2111 | { |
2112 | /* Individual Sector Erase Command Sequence */ | |
2113 | if (IS_OEM_001(ha)) { | |
2114 | qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); | |
2115 | qla2x00_write_flash_byte(ha, 0x555, 0x55); | |
2116 | qla2x00_write_flash_byte(ha, 0xaaa, 0x80); | |
2117 | qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); | |
2118 | qla2x00_write_flash_byte(ha, 0x555, 0x55); | |
2119 | qla2x00_write_flash_byte(ha, 0xaaa, 0x10); | |
2120 | } else { | |
2121 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
2122 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
2123 | qla2x00_write_flash_byte(ha, 0x5555, 0x80); | |
2124 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
2125 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
2126 | qla2x00_write_flash_byte(ha, 0x5555, 0x10); | |
2127 | } | |
2128 | ||
2129 | udelay(150); | |
2130 | ||
2131 | /* Wait for erase to complete. */ | |
2132 | return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id); | |
2133 | } | |
2134 | ||
2135 | /** | |
2136 | * qla2x00_erase_flash_sector() - Erase a flash sector. | |
2137 | * @ha: HA context | |
2138 | * @addr: Flash sector to erase | |
2139 | * @sec_mask: Sector address mask | |
2140 | * @man_id: Flash manufacturer ID | |
2141 | * @flash_id: Flash ID | |
2142 | * | |
2143 | * Returns 0 on success, else non-zero. | |
2144 | */ | |
2145 | static int | |
7b867cf7 | 2146 | qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr, |
854165f4 | 2147 | uint32_t sec_mask, uint8_t man_id, uint8_t flash_id) |
2148 | { | |
2149 | /* Individual Sector Erase Command Sequence */ | |
2150 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
2151 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
2152 | qla2x00_write_flash_byte(ha, 0x5555, 0x80); | |
2153 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
2154 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
2155 | if (man_id == 0x1f && flash_id == 0x13) | |
2156 | qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10); | |
2157 | else | |
2158 | qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30); | |
2159 | ||
2160 | udelay(150); | |
2161 | ||
2162 | /* Wait for erase to complete. */ | |
2163 | return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id); | |
2164 | } | |
2165 | ||
2166 | /** | |
2167 | * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip. | |
2168 | * @man_id: Flash manufacturer ID | |
2169 | * @flash_id: Flash ID | |
2170 | */ | |
2171 | static void | |
7b867cf7 | 2172 | qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, |
854165f4 | 2173 | uint8_t *flash_id) |
2174 | { | |
2175 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
2176 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
2177 | qla2x00_write_flash_byte(ha, 0x5555, 0x90); | |
2178 | *man_id = qla2x00_read_flash_byte(ha, 0x0000); | |
2179 | *flash_id = qla2x00_read_flash_byte(ha, 0x0001); | |
2180 | qla2x00_write_flash_byte(ha, 0x5555, 0xaa); | |
2181 | qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); | |
2182 | qla2x00_write_flash_byte(ha, 0x5555, 0xf0); | |
2183 | } | |
2184 | ||
30c47662 | 2185 | static void |
7b867cf7 AC |
2186 | qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf, |
2187 | uint32_t saddr, uint32_t length) | |
30c47662 AV |
2188 | { |
2189 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
2190 | uint32_t midpoint, ilength; | |
2191 | uint8_t data; | |
2192 | ||
2193 | midpoint = length / 2; | |
2194 | ||
2195 | WRT_REG_WORD(®->nvram, 0); | |
2196 | RD_REG_WORD(®->nvram); | |
2197 | for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) { | |
2198 | if (ilength == midpoint) { | |
2199 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
2200 | RD_REG_WORD(®->nvram); | |
2201 | } | |
2202 | data = qla2x00_read_flash_byte(ha, saddr); | |
2203 | if (saddr % 100) | |
2204 | udelay(10); | |
2205 | *tmp_buf = data; | |
40a2e34a | 2206 | cond_resched(); |
30c47662 AV |
2207 | } |
2208 | } | |
854165f4 | 2209 | |
2210 | static inline void | |
7b867cf7 | 2211 | qla2x00_suspend_hba(struct scsi_qla_host *vha) |
854165f4 | 2212 | { |
2213 | int cnt; | |
2214 | unsigned long flags; | |
7b867cf7 | 2215 | struct qla_hw_data *ha = vha->hw; |
854165f4 | 2216 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
2217 | ||
2218 | /* Suspend HBA. */ | |
7b867cf7 | 2219 | scsi_block_requests(vha->host); |
fd34f556 | 2220 | ha->isp_ops->disable_intrs(ha); |
854165f4 | 2221 | set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); |
2222 | ||
2223 | /* Pause RISC. */ | |
2224 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
2225 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); | |
2226 | RD_REG_WORD(®->hccr); | |
2227 | if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { | |
2228 | for (cnt = 0; cnt < 30000; cnt++) { | |
2229 | if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) | |
2230 | break; | |
2231 | udelay(100); | |
2232 | } | |
2233 | } else { | |
2234 | udelay(10); | |
2235 | } | |
2236 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
2237 | } | |
2238 | ||
2239 | static inline void | |
7b867cf7 | 2240 | qla2x00_resume_hba(struct scsi_qla_host *vha) |
854165f4 | 2241 | { |
7b867cf7 AC |
2242 | struct qla_hw_data *ha = vha->hw; |
2243 | ||
854165f4 | 2244 | /* Resume HBA. */ |
2245 | clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); | |
7b867cf7 AC |
2246 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); |
2247 | qla2xxx_wake_dpc(vha); | |
2533cf67 | 2248 | qla2x00_wait_for_chip_reset(vha); |
7b867cf7 | 2249 | scsi_unblock_requests(vha->host); |
854165f4 | 2250 | } |
2251 | ||
2252 | uint8_t * | |
7b867cf7 | 2253 | qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, |
854165f4 | 2254 | uint32_t offset, uint32_t length) |
2255 | { | |
854165f4 | 2256 | uint32_t addr, midpoint; |
2257 | uint8_t *data; | |
7b867cf7 | 2258 | struct qla_hw_data *ha = vha->hw; |
854165f4 | 2259 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
2260 | ||
2261 | /* Suspend HBA. */ | |
7b867cf7 | 2262 | qla2x00_suspend_hba(vha); |
854165f4 | 2263 | |
2264 | /* Go with read. */ | |
854165f4 | 2265 | midpoint = ha->optrom_size / 2; |
2266 | ||
2267 | qla2x00_flash_enable(ha); | |
2268 | WRT_REG_WORD(®->nvram, 0); | |
2269 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
2270 | for (addr = offset, data = buf; addr < length; addr++, data++) { | |
2271 | if (addr == midpoint) { | |
2272 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
2273 | RD_REG_WORD(®->nvram); /* PCI Posting. */ | |
2274 | } | |
2275 | ||
2276 | *data = qla2x00_read_flash_byte(ha, addr); | |
2277 | } | |
2278 | qla2x00_flash_disable(ha); | |
854165f4 | 2279 | |
2280 | /* Resume HBA. */ | |
7b867cf7 | 2281 | qla2x00_resume_hba(vha); |
854165f4 | 2282 | |
2283 | return buf; | |
2284 | } | |
2285 | ||
2286 | int | |
7b867cf7 | 2287 | qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, |
854165f4 | 2288 | uint32_t offset, uint32_t length) |
2289 | { | |
2290 | ||
2291 | int rval; | |
854165f4 | 2292 | uint8_t man_id, flash_id, sec_number, data; |
2293 | uint16_t wd; | |
2294 | uint32_t addr, liter, sec_mask, rest_addr; | |
7b867cf7 | 2295 | struct qla_hw_data *ha = vha->hw; |
854165f4 | 2296 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
2297 | ||
2298 | /* Suspend HBA. */ | |
7b867cf7 | 2299 | qla2x00_suspend_hba(vha); |
854165f4 | 2300 | |
2301 | rval = QLA_SUCCESS; | |
2302 | sec_number = 0; | |
2303 | ||
2304 | /* Reset ISP chip. */ | |
854165f4 | 2305 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); |
2306 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); | |
2307 | ||
2308 | /* Go with write. */ | |
2309 | qla2x00_flash_enable(ha); | |
2310 | do { /* Loop once to provide quick error exit */ | |
2311 | /* Structure of flash memory based on manufacturer */ | |
2312 | if (IS_OEM_001(ha)) { | |
2313 | /* OEM variant with special flash part. */ | |
2314 | man_id = flash_id = 0; | |
2315 | rest_addr = 0xffff; | |
2316 | sec_mask = 0x10000; | |
2317 | goto update_flash; | |
2318 | } | |
2319 | qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id); | |
2320 | switch (man_id) { | |
2321 | case 0x20: /* ST flash. */ | |
2322 | if (flash_id == 0xd2 || flash_id == 0xe3) { | |
2323 | /* | |
2324 | * ST m29w008at part - 64kb sector size with | |
2325 | * 32kb,8kb,8kb,16kb sectors at memory address | |
2326 | * 0xf0000. | |
2327 | */ | |
2328 | rest_addr = 0xffff; | |
2329 | sec_mask = 0x10000; | |
2330 | break; | |
2331 | } | |
2332 | /* | |
2333 | * ST m29w010b part - 16kb sector size | |
2334 | * Default to 16kb sectors | |
2335 | */ | |
2336 | rest_addr = 0x3fff; | |
2337 | sec_mask = 0x1c000; | |
2338 | break; | |
2339 | case 0x40: /* Mostel flash. */ | |
2340 | /* Mostel v29c51001 part - 512 byte sector size. */ | |
2341 | rest_addr = 0x1ff; | |
2342 | sec_mask = 0x1fe00; | |
2343 | break; | |
2344 | case 0xbf: /* SST flash. */ | |
2345 | /* SST39sf10 part - 4kb sector size. */ | |
2346 | rest_addr = 0xfff; | |
2347 | sec_mask = 0x1f000; | |
2348 | break; | |
2349 | case 0xda: /* Winbond flash. */ | |
2350 | /* Winbond W29EE011 part - 256 byte sector size. */ | |
2351 | rest_addr = 0x7f; | |
2352 | sec_mask = 0x1ff80; | |
2353 | break; | |
2354 | case 0xc2: /* Macronix flash. */ | |
2355 | /* 64k sector size. */ | |
2356 | if (flash_id == 0x38 || flash_id == 0x4f) { | |
2357 | rest_addr = 0xffff; | |
2358 | sec_mask = 0x10000; | |
2359 | break; | |
2360 | } | |
2361 | /* Fall through... */ | |
2362 | ||
2363 | case 0x1f: /* Atmel flash. */ | |
2364 | /* 512k sector size. */ | |
2365 | if (flash_id == 0x13) { | |
2366 | rest_addr = 0x7fffffff; | |
2367 | sec_mask = 0x80000000; | |
2368 | break; | |
2369 | } | |
2370 | /* Fall through... */ | |
2371 | ||
2372 | case 0x01: /* AMD flash. */ | |
2373 | if (flash_id == 0x38 || flash_id == 0x40 || | |
2374 | flash_id == 0x4f) { | |
2375 | /* Am29LV081 part - 64kb sector size. */ | |
2376 | /* Am29LV002BT part - 64kb sector size. */ | |
2377 | rest_addr = 0xffff; | |
2378 | sec_mask = 0x10000; | |
2379 | break; | |
2380 | } else if (flash_id == 0x3e) { | |
2381 | /* | |
2382 | * Am29LV008b part - 64kb sector size with | |
2383 | * 32kb,8kb,8kb,16kb sector at memory address | |
2384 | * h0xf0000. | |
2385 | */ | |
2386 | rest_addr = 0xffff; | |
2387 | sec_mask = 0x10000; | |
2388 | break; | |
2389 | } else if (flash_id == 0x20 || flash_id == 0x6e) { | |
2390 | /* | |
2391 | * Am29LV010 part or AM29f010 - 16kb sector | |
2392 | * size. | |
2393 | */ | |
2394 | rest_addr = 0x3fff; | |
2395 | sec_mask = 0x1c000; | |
2396 | break; | |
2397 | } else if (flash_id == 0x6d) { | |
2398 | /* Am29LV001 part - 8kb sector size. */ | |
2399 | rest_addr = 0x1fff; | |
2400 | sec_mask = 0x1e000; | |
2401 | break; | |
2402 | } | |
2403 | default: | |
2404 | /* Default to 16 kb sector size. */ | |
2405 | rest_addr = 0x3fff; | |
2406 | sec_mask = 0x1c000; | |
2407 | break; | |
2408 | } | |
2409 | ||
2410 | update_flash: | |
2411 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) { | |
2412 | if (qla2x00_erase_flash(ha, man_id, flash_id)) { | |
2413 | rval = QLA_FUNCTION_FAILED; | |
2414 | break; | |
2415 | } | |
2416 | } | |
2417 | ||
2418 | for (addr = offset, liter = 0; liter < length; liter++, | |
2419 | addr++) { | |
2420 | data = buf[liter]; | |
2421 | /* Are we at the beginning of a sector? */ | |
2422 | if ((addr & rest_addr) == 0) { | |
2423 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) { | |
2424 | if (addr >= 0x10000UL) { | |
2425 | if (((addr >> 12) & 0xf0) && | |
2426 | ((man_id == 0x01 && | |
2427 | flash_id == 0x3e) || | |
2428 | (man_id == 0x20 && | |
2429 | flash_id == 0xd2))) { | |
2430 | sec_number++; | |
2431 | if (sec_number == 1) { | |
2432 | rest_addr = | |
2433 | 0x7fff; | |
2434 | sec_mask = | |
2435 | 0x18000; | |
2436 | } else if ( | |
2437 | sec_number == 2 || | |
2438 | sec_number == 3) { | |
2439 | rest_addr = | |
2440 | 0x1fff; | |
2441 | sec_mask = | |
2442 | 0x1e000; | |
2443 | } else if ( | |
2444 | sec_number == 4) { | |
2445 | rest_addr = | |
2446 | 0x3fff; | |
2447 | sec_mask = | |
2448 | 0x1c000; | |
2449 | } | |
2450 | } | |
2451 | } | |
2452 | } else if (addr == ha->optrom_size / 2) { | |
2453 | WRT_REG_WORD(®->nvram, NVR_SELECT); | |
2454 | RD_REG_WORD(®->nvram); | |
2455 | } | |
2456 | ||
2457 | if (flash_id == 0xda && man_id == 0xc1) { | |
2458 | qla2x00_write_flash_byte(ha, 0x5555, | |
2459 | 0xaa); | |
2460 | qla2x00_write_flash_byte(ha, 0x2aaa, | |
2461 | 0x55); | |
2462 | qla2x00_write_flash_byte(ha, 0x5555, | |
2463 | 0xa0); | |
2464 | } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) { | |
2465 | /* Then erase it */ | |
2466 | if (qla2x00_erase_flash_sector(ha, | |
2467 | addr, sec_mask, man_id, | |
2468 | flash_id)) { | |
2469 | rval = QLA_FUNCTION_FAILED; | |
2470 | break; | |
2471 | } | |
2472 | if (man_id == 0x01 && flash_id == 0x6d) | |
2473 | sec_number++; | |
2474 | } | |
2475 | } | |
2476 | ||
2477 | if (man_id == 0x01 && flash_id == 0x6d) { | |
2478 | if (sec_number == 1 && | |
2479 | addr == (rest_addr - 1)) { | |
2480 | rest_addr = 0x0fff; | |
2481 | sec_mask = 0x1f000; | |
2482 | } else if (sec_number == 3 && (addr & 0x7ffe)) { | |
2483 | rest_addr = 0x3fff; | |
2484 | sec_mask = 0x1c000; | |
2485 | } | |
2486 | } | |
2487 | ||
2488 | if (qla2x00_program_flash_address(ha, addr, data, | |
2489 | man_id, flash_id)) { | |
2490 | rval = QLA_FUNCTION_FAILED; | |
2491 | break; | |
2492 | } | |
40a2e34a | 2493 | cond_resched(); |
854165f4 | 2494 | } |
2495 | } while (0); | |
2496 | qla2x00_flash_disable(ha); | |
854165f4 | 2497 | |
2498 | /* Resume HBA. */ | |
7b867cf7 | 2499 | qla2x00_resume_hba(vha); |
854165f4 | 2500 | |
2501 | return rval; | |
2502 | } | |
2503 | ||
2504 | uint8_t * | |
7b867cf7 | 2505 | qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, |
854165f4 | 2506 | uint32_t offset, uint32_t length) |
2507 | { | |
7b867cf7 AC |
2508 | struct qla_hw_data *ha = vha->hw; |
2509 | ||
854165f4 | 2510 | /* Suspend HBA. */ |
7b867cf7 | 2511 | scsi_block_requests(vha->host); |
854165f4 | 2512 | set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); |
2513 | ||
2514 | /* Go with read. */ | |
7b867cf7 | 2515 | qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2); |
854165f4 | 2516 | |
2517 | /* Resume HBA. */ | |
2518 | clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); | |
7b867cf7 | 2519 | scsi_unblock_requests(vha->host); |
854165f4 | 2520 | |
2521 | return buf; | |
2522 | } | |
2523 | ||
2524 | int | |
7b867cf7 | 2525 | qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, |
854165f4 | 2526 | uint32_t offset, uint32_t length) |
2527 | { | |
2528 | int rval; | |
7b867cf7 | 2529 | struct qla_hw_data *ha = vha->hw; |
854165f4 | 2530 | |
2531 | /* Suspend HBA. */ | |
7b867cf7 | 2532 | scsi_block_requests(vha->host); |
854165f4 | 2533 | set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); |
2534 | ||
2535 | /* Go with write. */ | |
7b867cf7 | 2536 | rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2, |
854165f4 | 2537 | length >> 2); |
2538 | ||
854165f4 | 2539 | clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); |
7b867cf7 | 2540 | scsi_unblock_requests(vha->host); |
854165f4 | 2541 | |
2542 | return rval; | |
2543 | } | |
30c47662 | 2544 | |
338c9161 | 2545 | uint8_t * |
7b867cf7 | 2546 | qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, |
338c9161 AV |
2547 | uint32_t offset, uint32_t length) |
2548 | { | |
2549 | int rval; | |
2550 | dma_addr_t optrom_dma; | |
2551 | void *optrom; | |
2552 | uint8_t *pbuf; | |
2553 | uint32_t faddr, left, burst; | |
7b867cf7 | 2554 | struct qla_hw_data *ha = vha->hw; |
338c9161 | 2555 | |
368bbe07 AV |
2556 | if (IS_QLA25XX(ha) || IS_QLA81XX(ha)) |
2557 | goto try_fast; | |
b7cc176c | 2558 | if (offset & 0xfff) |
338c9161 AV |
2559 | goto slow_read; |
2560 | if (length < OPTROM_BURST_SIZE) | |
2561 | goto slow_read; | |
2562 | ||
368bbe07 | 2563 | try_fast: |
338c9161 AV |
2564 | optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, |
2565 | &optrom_dma, GFP_KERNEL); | |
2566 | if (!optrom) { | |
7c3df132 SK |
2567 | ql_log(ql_log_warn, vha, 0x00cc, |
2568 | "Unable to allocate memory for optrom burst read (%x KB).\n", | |
2569 | OPTROM_BURST_SIZE / 1024); | |
338c9161 AV |
2570 | goto slow_read; |
2571 | } | |
2572 | ||
2573 | pbuf = buf; | |
2574 | faddr = offset >> 2; | |
2575 | left = length >> 2; | |
2576 | burst = OPTROM_BURST_DWORDS; | |
2577 | while (left != 0) { | |
2578 | if (burst > left) | |
2579 | burst = left; | |
2580 | ||
7b867cf7 | 2581 | rval = qla2x00_dump_ram(vha, optrom_dma, |
3a03eb79 | 2582 | flash_data_addr(ha, faddr), burst); |
338c9161 | 2583 | if (rval) { |
7c3df132 SK |
2584 | ql_log(ql_log_warn, vha, 0x00f5, |
2585 | "Unable to burst-read optrom segment (%x/%x/%llx).\n", | |
2586 | rval, flash_data_addr(ha, faddr), | |
875baf3c | 2587 | (unsigned long long)optrom_dma); |
7c3df132 | 2588 | ql_log(ql_log_warn, vha, 0x00f6, |
338c9161 AV |
2589 | "Reverting to slow-read.\n"); |
2590 | ||
2591 | dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, | |
2592 | optrom, optrom_dma); | |
2593 | goto slow_read; | |
2594 | } | |
2595 | ||
2596 | memcpy(pbuf, optrom, burst * 4); | |
2597 | ||
2598 | left -= burst; | |
2599 | faddr += burst; | |
2600 | pbuf += burst * 4; | |
2601 | } | |
2602 | ||
2603 | dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom, | |
2604 | optrom_dma); | |
2605 | ||
2606 | return buf; | |
2607 | ||
2608 | slow_read: | |
7b867cf7 | 2609 | return qla24xx_read_optrom_data(vha, buf, offset, length); |
338c9161 AV |
2610 | } |
2611 | ||
30c47662 AV |
2612 | /** |
2613 | * qla2x00_get_fcode_version() - Determine an FCODE image's version. | |
2614 | * @ha: HA context | |
2615 | * @pcids: Pointer to the FCODE PCI data structure | |
2616 | * | |
2617 | * The process of retrieving the FCODE version information is at best | |
2618 | * described as interesting. | |
2619 | * | |
2620 | * Within the first 100h bytes of the image an ASCII string is present | |
2621 | * which contains several pieces of information including the FCODE | |
2622 | * version. Unfortunately it seems the only reliable way to retrieve | |
2623 | * the version is by scanning for another sentinel within the string, | |
2624 | * the FCODE build date: | |
2625 | * | |
2626 | * ... 2.00.02 10/17/02 ... | |
2627 | * | |
2628 | * Returns QLA_SUCCESS on successful retrieval of version. | |
2629 | */ | |
2630 | static void | |
7b867cf7 | 2631 | qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids) |
30c47662 AV |
2632 | { |
2633 | int ret = QLA_FUNCTION_FAILED; | |
2634 | uint32_t istart, iend, iter, vend; | |
2635 | uint8_t do_next, rbyte, *vbyte; | |
2636 | ||
2637 | memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); | |
2638 | ||
2639 | /* Skip the PCI data structure. */ | |
2640 | istart = pcids + | |
2641 | ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) | | |
2642 | qla2x00_read_flash_byte(ha, pcids + 0x0A)); | |
2643 | iend = istart + 0x100; | |
2644 | do { | |
2645 | /* Scan for the sentinel date string...eeewww. */ | |
2646 | do_next = 0; | |
2647 | iter = istart; | |
2648 | while ((iter < iend) && !do_next) { | |
2649 | iter++; | |
2650 | if (qla2x00_read_flash_byte(ha, iter) == '/') { | |
2651 | if (qla2x00_read_flash_byte(ha, iter + 2) == | |
2652 | '/') | |
2653 | do_next++; | |
2654 | else if (qla2x00_read_flash_byte(ha, | |
2655 | iter + 3) == '/') | |
2656 | do_next++; | |
2657 | } | |
2658 | } | |
2659 | if (!do_next) | |
2660 | break; | |
2661 | ||
2662 | /* Backtrack to previous ' ' (space). */ | |
2663 | do_next = 0; | |
2664 | while ((iter > istart) && !do_next) { | |
2665 | iter--; | |
2666 | if (qla2x00_read_flash_byte(ha, iter) == ' ') | |
2667 | do_next++; | |
2668 | } | |
2669 | if (!do_next) | |
2670 | break; | |
2671 | ||
2672 | /* | |
2673 | * Mark end of version tag, and find previous ' ' (space) or | |
2674 | * string length (recent FCODE images -- major hack ahead!!!). | |
2675 | */ | |
2676 | vend = iter - 1; | |
2677 | do_next = 0; | |
2678 | while ((iter > istart) && !do_next) { | |
2679 | iter--; | |
2680 | rbyte = qla2x00_read_flash_byte(ha, iter); | |
2681 | if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10) | |
2682 | do_next++; | |
2683 | } | |
2684 | if (!do_next) | |
2685 | break; | |
2686 | ||
2687 | /* Mark beginning of version tag, and copy data. */ | |
2688 | iter++; | |
2689 | if ((vend - iter) && | |
2690 | ((vend - iter) < sizeof(ha->fcode_revision))) { | |
2691 | vbyte = ha->fcode_revision; | |
2692 | while (iter <= vend) { | |
2693 | *vbyte++ = qla2x00_read_flash_byte(ha, iter); | |
2694 | iter++; | |
2695 | } | |
2696 | ret = QLA_SUCCESS; | |
2697 | } | |
2698 | } while (0); | |
2699 | ||
2700 | if (ret != QLA_SUCCESS) | |
2701 | memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); | |
2702 | } | |
2703 | ||
2704 | int | |
7b867cf7 | 2705 | qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf) |
30c47662 AV |
2706 | { |
2707 | int ret = QLA_SUCCESS; | |
2708 | uint8_t code_type, last_image; | |
2709 | uint32_t pcihdr, pcids; | |
2710 | uint8_t *dbyte; | |
2711 | uint16_t *dcode; | |
7b867cf7 | 2712 | struct qla_hw_data *ha = vha->hw; |
30c47662 AV |
2713 | |
2714 | if (!ha->pio_address || !mbuf) | |
2715 | return QLA_FUNCTION_FAILED; | |
2716 | ||
2717 | memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); | |
2718 | memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); | |
2719 | memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); | |
2720 | memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); | |
2721 | ||
2722 | qla2x00_flash_enable(ha); | |
2723 | ||
2724 | /* Begin with first PCI expansion ROM header. */ | |
2725 | pcihdr = 0; | |
2726 | last_image = 1; | |
2727 | do { | |
2728 | /* Verify PCI expansion ROM header. */ | |
2729 | if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 || | |
2730 | qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) { | |
2731 | /* No signature */ | |
7c3df132 SK |
2732 | ql_log(ql_log_fatal, vha, 0x0050, |
2733 | "No matching ROM signature.\n"); | |
30c47662 AV |
2734 | ret = QLA_FUNCTION_FAILED; |
2735 | break; | |
2736 | } | |
2737 | ||
2738 | /* Locate PCI data structure. */ | |
2739 | pcids = pcihdr + | |
2740 | ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) | | |
2741 | qla2x00_read_flash_byte(ha, pcihdr + 0x18)); | |
2742 | ||
2743 | /* Validate signature of PCI data structure. */ | |
2744 | if (qla2x00_read_flash_byte(ha, pcids) != 'P' || | |
2745 | qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' || | |
2746 | qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' || | |
2747 | qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') { | |
2748 | /* Incorrect header. */ | |
7c3df132 SK |
2749 | ql_log(ql_log_fatal, vha, 0x0051, |
2750 | "PCI data struct not found pcir_adr=%x.\n", pcids); | |
30c47662 AV |
2751 | ret = QLA_FUNCTION_FAILED; |
2752 | break; | |
2753 | } | |
2754 | ||
2755 | /* Read version */ | |
2756 | code_type = qla2x00_read_flash_byte(ha, pcids + 0x14); | |
2757 | switch (code_type) { | |
2758 | case ROM_CODE_TYPE_BIOS: | |
2759 | /* Intel x86, PC-AT compatible. */ | |
2760 | ha->bios_revision[0] = | |
2761 | qla2x00_read_flash_byte(ha, pcids + 0x12); | |
2762 | ha->bios_revision[1] = | |
2763 | qla2x00_read_flash_byte(ha, pcids + 0x13); | |
7c3df132 SK |
2764 | ql_dbg(ql_dbg_init, vha, 0x0052, |
2765 | "Read BIOS %d.%d.\n", | |
2766 | ha->bios_revision[1], ha->bios_revision[0]); | |
30c47662 AV |
2767 | break; |
2768 | case ROM_CODE_TYPE_FCODE: | |
2769 | /* Open Firmware standard for PCI (FCode). */ | |
2770 | /* Eeeewww... */ | |
2771 | qla2x00_get_fcode_version(ha, pcids); | |
2772 | break; | |
2773 | case ROM_CODE_TYPE_EFI: | |
2774 | /* Extensible Firmware Interface (EFI). */ | |
2775 | ha->efi_revision[0] = | |
2776 | qla2x00_read_flash_byte(ha, pcids + 0x12); | |
2777 | ha->efi_revision[1] = | |
2778 | qla2x00_read_flash_byte(ha, pcids + 0x13); | |
7c3df132 SK |
2779 | ql_dbg(ql_dbg_init, vha, 0x0053, |
2780 | "Read EFI %d.%d.\n", | |
2781 | ha->efi_revision[1], ha->efi_revision[0]); | |
30c47662 AV |
2782 | break; |
2783 | default: | |
7c3df132 SK |
2784 | ql_log(ql_log_warn, vha, 0x0054, |
2785 | "Unrecognized code type %x at pcids %x.\n", | |
2786 | code_type, pcids); | |
30c47662 AV |
2787 | break; |
2788 | } | |
2789 | ||
2790 | last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7; | |
2791 | ||
2792 | /* Locate next PCI expansion ROM. */ | |
2793 | pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) | | |
2794 | qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512; | |
2795 | } while (!last_image); | |
2796 | ||
2797 | if (IS_QLA2322(ha)) { | |
2798 | /* Read firmware image information. */ | |
2799 | memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); | |
2800 | dbyte = mbuf; | |
2801 | memset(dbyte, 0, 8); | |
2802 | dcode = (uint16_t *)dbyte; | |
2803 | ||
c00d8994 | 2804 | qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10, |
30c47662 | 2805 | 8); |
7c3df132 SK |
2806 | ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a, |
2807 | "Dumping fw " | |
2808 | "ver from flash:.\n"); | |
2809 | ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b, | |
2810 | (uint8_t *)dbyte, 8); | |
30c47662 AV |
2811 | |
2812 | if ((dcode[0] == 0xffff && dcode[1] == 0xffff && | |
2813 | dcode[2] == 0xffff && dcode[3] == 0xffff) || | |
2814 | (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && | |
2815 | dcode[3] == 0)) { | |
7c3df132 SK |
2816 | ql_log(ql_log_warn, vha, 0x0057, |
2817 | "Unrecognized fw revision at %x.\n", | |
2818 | ha->flt_region_fw * 4); | |
30c47662 AV |
2819 | } else { |
2820 | /* values are in big endian */ | |
2821 | ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1]; | |
2822 | ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3]; | |
2823 | ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5]; | |
7c3df132 SK |
2824 | ql_dbg(ql_dbg_init, vha, 0x0058, |
2825 | "FW Version: " | |
2826 | "%d.%d.%d.\n", ha->fw_revision[0], | |
2827 | ha->fw_revision[1], ha->fw_revision[2]); | |
30c47662 AV |
2828 | } |
2829 | } | |
2830 | ||
2831 | qla2x00_flash_disable(ha); | |
2832 | ||
2833 | return ret; | |
2834 | } | |
2835 | ||
2836 | int | |
7b867cf7 | 2837 | qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) |
30c47662 AV |
2838 | { |
2839 | int ret = QLA_SUCCESS; | |
2840 | uint32_t pcihdr, pcids; | |
2841 | uint32_t *dcode; | |
2842 | uint8_t *bcode; | |
2843 | uint8_t code_type, last_image; | |
2844 | int i; | |
7b867cf7 | 2845 | struct qla_hw_data *ha = vha->hw; |
30c47662 | 2846 | |
a9083016 GM |
2847 | if (IS_QLA82XX(ha)) |
2848 | return ret; | |
2849 | ||
30c47662 AV |
2850 | if (!mbuf) |
2851 | return QLA_FUNCTION_FAILED; | |
2852 | ||
2853 | memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); | |
2854 | memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); | |
2855 | memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); | |
2856 | memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); | |
2857 | ||
2858 | dcode = mbuf; | |
2859 | ||
2860 | /* Begin with first PCI expansion ROM header. */ | |
6315a5f8 | 2861 | pcihdr = ha->flt_region_boot << 2; |
30c47662 AV |
2862 | last_image = 1; |
2863 | do { | |
2864 | /* Verify PCI expansion ROM header. */ | |
7b867cf7 | 2865 | qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); |
30c47662 AV |
2866 | bcode = mbuf + (pcihdr % 4); |
2867 | if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) { | |
2868 | /* No signature */ | |
7c3df132 SK |
2869 | ql_log(ql_log_fatal, vha, 0x0059, |
2870 | "No matching ROM signature.\n"); | |
30c47662 AV |
2871 | ret = QLA_FUNCTION_FAILED; |
2872 | break; | |
2873 | } | |
2874 | ||
2875 | /* Locate PCI data structure. */ | |
2876 | pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); | |
2877 | ||
7b867cf7 | 2878 | qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); |
30c47662 AV |
2879 | bcode = mbuf + (pcihdr % 4); |
2880 | ||
2881 | /* Validate signature of PCI data structure. */ | |
2882 | if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || | |
2883 | bcode[0x2] != 'I' || bcode[0x3] != 'R') { | |
2884 | /* Incorrect header. */ | |
7c3df132 SK |
2885 | ql_log(ql_log_fatal, vha, 0x005a, |
2886 | "PCI data struct not found pcir_adr=%x.\n", pcids); | |
30c47662 AV |
2887 | ret = QLA_FUNCTION_FAILED; |
2888 | break; | |
2889 | } | |
2890 | ||
2891 | /* Read version */ | |
2892 | code_type = bcode[0x14]; | |
2893 | switch (code_type) { | |
2894 | case ROM_CODE_TYPE_BIOS: | |
2895 | /* Intel x86, PC-AT compatible. */ | |
2896 | ha->bios_revision[0] = bcode[0x12]; | |
2897 | ha->bios_revision[1] = bcode[0x13]; | |
7c3df132 SK |
2898 | ql_dbg(ql_dbg_init, vha, 0x005b, |
2899 | "Read BIOS %d.%d.\n", | |
2900 | ha->bios_revision[1], ha->bios_revision[0]); | |
30c47662 AV |
2901 | break; |
2902 | case ROM_CODE_TYPE_FCODE: | |
2903 | /* Open Firmware standard for PCI (FCode). */ | |
2904 | ha->fcode_revision[0] = bcode[0x12]; | |
2905 | ha->fcode_revision[1] = bcode[0x13]; | |
7c3df132 SK |
2906 | ql_dbg(ql_dbg_init, vha, 0x005c, |
2907 | "Read FCODE %d.%d.\n", | |
2908 | ha->fcode_revision[1], ha->fcode_revision[0]); | |
30c47662 AV |
2909 | break; |
2910 | case ROM_CODE_TYPE_EFI: | |
2911 | /* Extensible Firmware Interface (EFI). */ | |
2912 | ha->efi_revision[0] = bcode[0x12]; | |
2913 | ha->efi_revision[1] = bcode[0x13]; | |
7c3df132 SK |
2914 | ql_dbg(ql_dbg_init, vha, 0x005d, |
2915 | "Read EFI %d.%d.\n", | |
2916 | ha->efi_revision[1], ha->efi_revision[0]); | |
30c47662 AV |
2917 | break; |
2918 | default: | |
7c3df132 SK |
2919 | ql_log(ql_log_warn, vha, 0x005e, |
2920 | "Unrecognized code type %x at pcids %x.\n", | |
2921 | code_type, pcids); | |
30c47662 AV |
2922 | break; |
2923 | } | |
2924 | ||
2925 | last_image = bcode[0x15] & BIT_7; | |
2926 | ||
2927 | /* Locate next PCI expansion ROM. */ | |
2928 | pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; | |
2929 | } while (!last_image); | |
2930 | ||
2931 | /* Read firmware image information. */ | |
2932 | memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); | |
2933 | dcode = mbuf; | |
2934 | ||
7b867cf7 | 2935 | qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4); |
30c47662 AV |
2936 | for (i = 0; i < 4; i++) |
2937 | dcode[i] = be32_to_cpu(dcode[i]); | |
2938 | ||
2939 | if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && | |
2940 | dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || | |
2941 | (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && | |
2942 | dcode[3] == 0)) { | |
7c3df132 SK |
2943 | ql_log(ql_log_warn, vha, 0x005f, |
2944 | "Unrecognized fw revision at %x.\n", | |
2945 | ha->flt_region_fw * 4); | |
30c47662 AV |
2946 | } else { |
2947 | ha->fw_revision[0] = dcode[0]; | |
2948 | ha->fw_revision[1] = dcode[1]; | |
2949 | ha->fw_revision[2] = dcode[2]; | |
2950 | ha->fw_revision[3] = dcode[3]; | |
7c3df132 SK |
2951 | ql_dbg(ql_dbg_init, vha, 0x0060, |
2952 | "Firmware revision %d.%d.%d.%d.\n", | |
2953 | ha->fw_revision[0], ha->fw_revision[1], | |
2954 | ha->fw_revision[2], ha->fw_revision[3]); | |
30c47662 AV |
2955 | } |
2956 | ||
0f2d962f MI |
2957 | /* Check for golden firmware and get version if available */ |
2958 | if (!IS_QLA81XX(ha)) { | |
2959 | /* Golden firmware is not present in non 81XX adapters */ | |
2960 | return ret; | |
2961 | } | |
2962 | ||
2963 | memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version)); | |
2964 | dcode = mbuf; | |
2965 | ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, | |
2966 | ha->flt_region_gold_fw << 2, 32); | |
2967 | ||
2968 | if (dcode[4] == 0xFFFFFFFF && dcode[5] == 0xFFFFFFFF && | |
2969 | dcode[6] == 0xFFFFFFFF && dcode[7] == 0xFFFFFFFF) { | |
7c3df132 SK |
2970 | ql_log(ql_log_warn, vha, 0x0056, |
2971 | "Unrecognized golden fw at 0x%x.\n", | |
2972 | ha->flt_region_gold_fw * 4); | |
0f2d962f MI |
2973 | return ret; |
2974 | } | |
2975 | ||
2976 | for (i = 4; i < 8; i++) | |
2977 | ha->gold_fw_version[i-4] = be32_to_cpu(dcode[i]); | |
2978 | ||
30c47662 AV |
2979 | return ret; |
2980 | } | |
cb8dacbf | 2981 | |
1ee27146 JC |
2982 | static int |
2983 | qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end) | |
2984 | { | |
2985 | if (pos >= end || *pos != 0x82) | |
2986 | return 0; | |
2987 | ||
2988 | pos += 3 + pos[1]; | |
2989 | if (pos >= end || *pos != 0x90) | |
2990 | return 0; | |
2991 | ||
2992 | pos += 3 + pos[1]; | |
2993 | if (pos >= end || *pos != 0x78) | |
2994 | return 0; | |
2995 | ||
2996 | return 1; | |
2997 | } | |
2998 | ||
2999 | int | |
7b867cf7 | 3000 | qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size) |
1ee27146 | 3001 | { |
7b867cf7 | 3002 | struct qla_hw_data *ha = vha->hw; |
1ee27146 JC |
3003 | uint8_t *pos = ha->vpd; |
3004 | uint8_t *end = pos + ha->vpd_size; | |
3005 | int len = 0; | |
3006 | ||
3007 | if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end)) | |
3008 | return 0; | |
3009 | ||
3010 | while (pos < end && *pos != 0x78) { | |
3011 | len = (*pos == 0x82) ? pos[1] : pos[2]; | |
3012 | ||
3013 | if (!strncmp(pos, key, strlen(key))) | |
3014 | break; | |
3015 | ||
3016 | if (*pos != 0x90 && *pos != 0x91) | |
3017 | pos += len; | |
3018 | ||
3019 | pos += 3; | |
3020 | } | |
3021 | ||
3022 | if (pos < end - len && *pos != 0x78) | |
3023 | return snprintf(str, size, "%.*s", len, pos + 3); | |
3024 | ||
3025 | return 0; | |
3026 | } | |
09ff701a SR |
3027 | |
3028 | int | |
3029 | qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha) | |
3030 | { | |
3031 | int len, max_len; | |
3032 | uint32_t fcp_prio_addr; | |
3033 | struct qla_hw_data *ha = vha->hw; | |
3034 | ||
3035 | if (!ha->fcp_prio_cfg) { | |
3036 | ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE); | |
3037 | if (!ha->fcp_prio_cfg) { | |
7c3df132 SK |
3038 | ql_log(ql_log_warn, vha, 0x00d5, |
3039 | "Unable to allocate memory for fcp priorty data (%x).\n", | |
3040 | FCP_PRIO_CFG_SIZE); | |
09ff701a SR |
3041 | return QLA_FUNCTION_FAILED; |
3042 | } | |
3043 | } | |
3044 | memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE); | |
3045 | ||
3046 | fcp_prio_addr = ha->flt_region_fcp_prio; | |
3047 | ||
3048 | /* first read the fcp priority data header from flash */ | |
3049 | ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg, | |
3050 | fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE); | |
3051 | ||
7c3df132 | 3052 | if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0)) |
09ff701a SR |
3053 | goto fail; |
3054 | ||
3055 | /* read remaining FCP CMD config data from flash */ | |
3056 | fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2); | |
3057 | len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE; | |
3058 | max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE; | |
3059 | ||
3060 | ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0], | |
3061 | fcp_prio_addr << 2, (len < max_len ? len : max_len)); | |
3062 | ||
3063 | /* revalidate the entire FCP priority config data, including entries */ | |
7c3df132 | 3064 | if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1)) |
09ff701a SR |
3065 | goto fail; |
3066 | ||
3067 | ha->flags.fcp_prio_enabled = 1; | |
3068 | return QLA_SUCCESS; | |
3069 | fail: | |
3070 | vfree(ha->fcp_prio_cfg); | |
3071 | ha->fcp_prio_cfg = NULL; | |
3072 | return QLA_FUNCTION_FAILED; | |
3073 | } |