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Merge tag 'pci-v6.16-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
[linux-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
77adf3f0 1// SPDX-License-Identifier: GPL-2.0-only
1da177e4 2/*
fa90c54f 3 * QLogic Fibre Channel HBA Driver
bd21eaf9 4 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4
LT		 5 */
6#include "qla_def.h"
7
dc1d7b36 8#include <linux/bitfield.h>
1da177e4
LT		 9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
585def9b 16#include <linux/refcount.h>
62e0dec5 17#include <linux/crash_dump.h>
8bfc149b
AE		 18#include <linux/trace_events.h>
19#include <linux/trace.h>
585def9b 20
1da177e4
LT		 21#include <scsi/scsi_tcq.h>
22#include <scsi/scsicam.h>
23#include <scsi/scsi_transport.h>
24#include <scsi/scsi_transport_fc.h>
25
2d70c103
NB		 26#include "qla_target.h"
27
1da177e4
LT		 28/*
29 * Driver version
30 */
31char qla2x00_version_str[40];
32
6a03b4cd
HZ		 33static int apidev_major;
34
1da177e4
LT		 35/*
36 * SRB allocation cache
37 */
d7459527 38struct kmem_cache *srb_cachep;
1da177e4 39
2c57d0de 40static struct trace_array *qla_trc_array;
8bfc149b 41
cbb01c2f
AE		 42int ql2xfulldump_on_mpifail;
43module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR);
44MODULE_PARM_DESC(ql2xfulldump_on_mpifail,
45 "Set this to take full dump on MPI hang.");
46
e370b64c 47int ql2xenforce_iocb_limit = 2;
89c72f42
QT		 48module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR);
49MODULE_PARM_DESC(ql2xenforce_iocb_limit,
e370b64c
QT		 50 "Enforce IOCB throttling, to avoid FW congestion. (default: 2) "
51 "1: track usage per queue, 2: track usage per adapter");
89c72f42 52
a9083016
GM		 53/*
54 * CT6 CTX allocation cache
55 */
56static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 57/*
58 * error level for logging
59 */
3f006ac3 60uint ql_errlev = 0x8001;
a9083016 61
44d01857
QT		 62int ql2xsecenable;
63module_param(ql2xsecenable, int, S_IRUGO);
64MODULE_PARM_DESC(ql2xsecenable,
65 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled.");
66
fa492630 67static int ql2xenableclass2;
2d70c103
NB		 68module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
69MODULE_PARM_DESC(ql2xenableclass2,
70 "Specify if Class 2 operations are supported from the very "
71 "beginning. Default is 0 - class 2 not supported.");
72
8ae6d9c7 73
1da177e4 74int ql2xlogintimeout = 20;
f2019cb1 75module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 76MODULE_PARM_DESC(ql2xlogintimeout,
77 "Login timeout value in seconds.");
78
a7b61842 79int qlport_down_retry;
f2019cb1 80module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 81MODULE_PARM_DESC(qlport_down_retry,
900d9f98 82 "Maximum number of command retries to a port that returns "
1da177e4
LT		 83 "a PORT-DOWN status.");
84
1da177e4
LT		 85int ql2xplogiabsentdevice;
86module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
87MODULE_PARM_DESC(ql2xplogiabsentdevice,
88 "Option to enable PLOGI to devices that are not present after "
900d9f98 89 "a Fabric scan. This is needed for several broken switches. "
0d52e642 90 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
1da177e4 91
c1c7178c 92int ql2xloginretrycount;
f2019cb1 93module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 94MODULE_PARM_DESC(ql2xloginretrycount,
95 "Specify an alternate value for the NVRAM login retry count.");
96
a7a167bf 97int ql2xallocfwdump = 1;
f2019cb1 98module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 99MODULE_PARM_DESC(ql2xallocfwdump,
100 "Option to enable allocation of memory for a firmware dump "
101 "during HBA initialization. Memory allocation requirements "
102 "vary by ISP type. Default is 1 - allocate memory.");
103
11010fec 104int ql2xextended_error_logging;
27d94035 105module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 106module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 107MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 108 "Option to enable extended error logging,\n"
109 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
110 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
111 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
112 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
113 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
114 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
115 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
116 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 117 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
118 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 119 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 120 "\t\t0x1e400000 - Preferred value for capturing essential "
121 "debug information (equivalent to old "
122 "ql2xextended_error_logging=1).\n"
3ce8866c 123 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 124
8bfc149b
AE		 125int ql2xextended_error_logging_ktrace = 1;
126module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR);
127MODULE_PARM_DESC(ql2xextended_error_logging_ktrace,
efca5274 128 "Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n");
8bfc149b 129
a9083016 130int ql2xshiftctondsd = 6;
f2019cb1 131module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 132MODULE_PARM_DESC(ql2xshiftctondsd,
133 "Set to control shifting of command type processing "
134 "based on total number of SG elements.");
135
58e2753c 136int ql2xfdmienable = 1;
de187df8 137module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 138module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 139MODULE_PARM_DESC(ql2xfdmienable,
7794a5af 140 "Enables FDMI registrations. "
bd7de0b1
JC		 141 "0 - no FDMI registrations. "
142 "1 - provide FDMI registrations (default).");
cca5335c 143
d213a4b7 144#define MAX_Q_DEPTH 64
50280c01 145static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 146module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
147MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 148 "Maximum queue depth to set for each LUN. "
d213a4b7 149 "Default is 64.");
df7baa50 150
9e522cd8
AE		 151int ql2xenabledif = 2;
152module_param(ql2xenabledif, int, S_IRUGO);
bad75002 153MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 154 " Enable T10-CRC-DIF:\n"
155 " Default is 2.\n"
156 " 0 -- No DIF Support\n"
157 " 1 -- Enable DIF for all types\n"
158 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 159
e84067d7
DG		 160#if (IS_ENABLED(CONFIG_NVME_FC))
161int ql2xnvmeenable = 1;
162#else
163int ql2xnvmeenable;
164#endif
165module_param(ql2xnvmeenable, int, 0644);
166MODULE_PARM_DESC(ql2xnvmeenable,
167 "Enables NVME support. "
168 "0 - no NVMe. Default is Y");
169
8cb2049c 170int ql2xenablehba_err_chk = 2;
bad75002
AE		 171module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
172MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 173 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 174 " Default is 2.\n"
8cb2049c
AE		 175 " 0 -- Error isolation disabled\n"
176 " 1 -- Error isolation enabled only for DIX Type 0\n"
177 " 2 -- Error isolation enabled for all Types\n");
bad75002 178
d7459527
MH		 179int ql2xmqsupport = 1;
180module_param(ql2xmqsupport, int, S_IRUGO);
181MODULE_PARM_DESC(ql2xmqsupport,
182 "Enable on demand multiple queue pairs support "
183 "Default is 1 for supported. "
184 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 185
186int ql2xfwloadbin;
86e45bf6 187module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 188module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 189MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 190 "Option to specify location from which to load ISP firmware:.\n"
191 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 192 " interface.\n"
193 " 1 -- load firmware from flash.\n"
194 " 0 -- use default semantics.\n");
195
6907869d 196int ql2xdbwr = 1;
86e45bf6 197module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 198MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 199 "Option to specify scheme for request queue posting.\n"
200 " 0 -- Regular doorbell.\n"
201 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 202
4da26e16 203int ql2xgffidenable;
f2019cb1 204module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 205MODULE_PARM_DESC(ql2xgffidenable,
206 "Enables GFF_ID checks of port type. "
207 "Default is 0 - Do not use GFF_ID information.");
a9083016 208
043dc1d7 209int ql2xasynctmfenable = 1;
f2019cb1 210module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 211MODULE_PARM_DESC(ql2xasynctmfenable,
212 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
84e13c45 213 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 214
215int ql2xdontresethba;
86e45bf6 216module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 217MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 218 "Option to specify reset behaviour.\n"
219 " 0 (Default) -- Reset on failure.\n"
220 " 1 -- Do not reset on failure.\n");
ed0de87c 221
1abf635d
HR		 222uint64_t ql2xmaxlun = MAX_LUNS;
223module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 224MODULE_PARM_DESC(ql2xmaxlun,
225 "Defines the maximum LU number to register with the SCSI "
226 "midlayer. Default is 65535.");
227
08de2844
GM		 228int ql2xmdcapmask = 0x1F;
229module_param(ql2xmdcapmask, int, S_IRUGO);
230MODULE_PARM_DESC(ql2xmdcapmask,
231 "Set the Minidump driver capture mask level. "
6e96fa7b 232 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 233
3aadff35 234int ql2xmdenable = 1;
08de2844
GM		 235module_param(ql2xmdenable, int, S_IRUGO);
236MODULE_PARM_DESC(ql2xmdenable,
237 "Enable/disable MiniDump. "
3aadff35
GM		 238 "0 - MiniDump disabled. "
239 "1 (Default) - MiniDump enabled.");
08de2844 240
c1c7178c 241int ql2xexlogins;
b0d6cabd
HM		 242module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
243MODULE_PARM_DESC(ql2xexlogins,
244 "Number of extended Logins. "
245 "0 (Default)- Disabled.");
246
99e1b683
QT		 247int ql2xexchoffld = 1024;
248module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 249MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 250 "Number of target exchanges.");
251
252int ql2xiniexchg = 1024;
253module_param(ql2xiniexchg, uint, 0644);
254MODULE_PARM_DESC(ql2xiniexchg,
255 "Number of initiator exchanges.");
2f56a7f1 256
c1c7178c 257int ql2xfwholdabts;
f198cafa
HM		 258module_param(ql2xfwholdabts, int, S_IRUGO);
259MODULE_PARM_DESC(ql2xfwholdabts,
260 "Allow FW to hold status IOCB until ABTS rsp received. "
261 "0 (Default) Do not set fw option. "
262 "1 - Set fw option to hold ABTS.");
263
41dc529a
QT		 264int ql2xmvasynctoatio = 1;
265module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
266MODULE_PARM_DESC(ql2xmvasynctoatio,
267 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
268 "0 (Default). Do not move IOCBs"
269 "1 - Move IOCBs.");
270
e4e3a2ce
QT		 271int ql2xautodetectsfp = 1;
272module_param(ql2xautodetectsfp, int, 0444);
273MODULE_PARM_DESC(ql2xautodetectsfp,
274 "Detect SFP range and set appropriate distance.\n"
275 "1 (Default): Enable\n");
276
e7240af5
HM		 277int ql2xenablemsix = 1;
278module_param(ql2xenablemsix, int, 0444);
279MODULE_PARM_DESC(ql2xenablemsix,
280 "Set to enable MSI or MSI-X interrupt mechanism.\n"
281 " Default is 1, enable MSI-X interrupt mechanism.\n"
282 " 0 -- enable traditional pin-based mechanism.\n"
283 " 1 -- enable MSI-X interrupt mechanism.\n"
284 " 2 -- enable MSI interrupt mechanism.\n");
285
9ecf0b0d
QT		 286int qla2xuseresexchforels;
287module_param(qla2xuseresexchforels, int, 0444);
288MODULE_PARM_DESC(qla2xuseresexchforels,
289 "Reserve 1/2 of emergency exchanges for ELS.\n"
290 " 0 (default): disabled");
291
b3ede8ea 292static int ql2xprotmask;
7855d2ba
MP		 293module_param(ql2xprotmask, int, 0644);
294MODULE_PARM_DESC(ql2xprotmask,
295 "Override DIF/DIX protection capabilities mask\n"
296 "Default is 0 which sets protection mask based on "
297 "capabilities reported by HBA firmware.\n");
298
b3ede8ea 299static int ql2xprotguard;
7855d2ba
MP		 300module_param(ql2xprotguard, int, 0644);
301MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
302 " 0 -- Let HBA firmware decide\n"
303 " 1 -- Force T10 CRC\n"
304 " 2 -- Force IP checksum\n");
305
50b81275
GM		 306int ql2xdifbundlinginternalbuffers;
307module_param(ql2xdifbundlinginternalbuffers, int, 0644);
308MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
309 "Force using internal buffers for DIF information\n"
310 "0 (Default). Based on check.\n"
311 "1 Force using internal buffers\n");
312
d83a80ee
JC		 313int ql2xsmartsan;
314module_param(ql2xsmartsan, int, 0444);
315module_param_named(smartsan, ql2xsmartsan, int, 0444);
316MODULE_PARM_DESC(ql2xsmartsan,
317 "Send SmartSAN Management Attributes for FDMI Registration."
318 " Default is 0 - No SmartSAN registration,"
319 " 1 - Register SmartSAN Management Attributes.");
320
bd7de0b1
JC		 321int ql2xrdpenable;
322module_param(ql2xrdpenable, int, 0444);
323module_param_named(rdpenable, ql2xrdpenable, int, 0444);
324MODULE_PARM_DESC(ql2xrdpenable,
325 "Enables RDP responses. "
326 "0 - no RDP responses (default). "
327 "1 - provide RDP responses.");
a0465859
BH		 328int ql2xabts_wait_nvme = 1;
329module_param(ql2xabts_wait_nvme, int, 0444);
330MODULE_PARM_DESC(ql2xabts_wait_nvme,
331 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)");
332
d83a80ee 333
2c57d0de 334static u32 ql2xdelay_before_pci_error_handling = 5;
d3117c83
QT		 335module_param(ql2xdelay_before_pci_error_handling, uint, 0644);
336MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling,
337 "Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n");
338
1a2fbf18 339static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 340static void qla2x00_free_device(scsi_qla_host_t *);
a4e1d0b7 341static void qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 342static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 343
65120de2
SD		 344u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES;
345module_param(ql2xnvme_queues, uint, S_IRUGO);
346MODULE_PARM_DESC(ql2xnvme_queues,
347 "Number of NVMe Queues that can be configured.\n"
348 "Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n"
349 "1 - Minimum number of queues supported\n"
65120de2 350 "8 - Default value");
45235022 351
877b0379
DW		 352int ql2xfc2target = 1;
353module_param(ql2xfc2target, int, 0444);
354MODULE_PARM_DESC(qla2xfc2target,
355 "Enables FC2 Target support. "
356 "0 - FC2 Target support is disabled. "
357 "1 - FC2 Target support is enabled (default).");
358
1da177e4 359static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 360struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 361
1da177e4
LT		 362/* TODO Convert to inlines
363 *
364 * Timer routines
365 */
1da177e4 366
2c3dfe3f 367__inline__ void
8e5f4ba0 368qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 369{
8e5f4ba0 370 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 371 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 372 add_timer(&vha->timer);
373 vha->timer_active = 1;
1da177e4
LT		 374}
375
376static inline void
e315cd28 377qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 378{
a9083016 379 /* Currently used for 82XX only. */
7c3df132
SK		 380 if (vha->device_flags & DFLG_DEV_FAILED) {
381 ql_dbg(ql_dbg_timer, vha, 0x600d,
382 "Device in a failed state, returning.\n");
a9083016 383 return;
7c3df132 384 }
a9083016 385
e315cd28 386 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 387}
388
a824ebb3 389static __inline__ void
e315cd28 390qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 391{
8fa7292f 392 timer_delete_sync(&vha->timer);
e315cd28 393 vha->timer_active = 0;
1da177e4
LT		 394}
395
1da177e4
LT		 396static int qla2x00_do_dpc(void *data);
397
398static void qla2x00_rst_aen(scsi_qla_host_t *);
399
73208dfd
AC		 400static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
401 struct req_que **, struct rsp_que **);
e30d1756 402static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 403static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 404int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
405 struct qla_qpair *qpair);
1da177e4 406
1da177e4 407/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 408static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
409 struct rsp_que *rsp)
410{
411 struct qla_hw_data *ha = vha->hw;
bd432bb5 412
8abfa9e2
QT		 413 rsp->qpair = ha->base_qpair;
414 rsp->req = req;
0691094f 415 ha->base_qpair->hw = ha;
8abfa9e2
QT		 416 ha->base_qpair->req = req;
417 ha->base_qpair->rsp = rsp;
418 ha->base_qpair->vha = vha;
419 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
420 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
421 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
6a629468 422 ha->base_qpair->srb_mempool = ha->srb_mempool;
8abfa9e2 423 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
efeda3bf 424 INIT_LIST_HEAD(&ha->base_qpair->dsd_list);
8abfa9e2
QT		 425 ha->base_qpair->enable_class_2 = ql2xenableclass2;
426 /* init qpair to this cpu. Will adjust at run time. */
86531887 427 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
8abfa9e2
QT		 428 ha->base_qpair->pdev = ha->pdev;
429
ecc89f25 430 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
8abfa9e2
QT		 431 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
432}
433
9a347ff4
CD		 434static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
435 struct rsp_que *rsp)
73208dfd 436{
7c3df132 437 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
bd432bb5 438
6396bb22 439 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
73208dfd
AC		 440 GFP_KERNEL);
441 if (!ha->req_q_map) {
7c3df132
SK		 442 ql_log(ql_log_fatal, vha, 0x003b,
443 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 444 goto fail_req_map;
445 }
446
6396bb22 447 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
73208dfd
AC		 448 GFP_KERNEL);
449 if (!ha->rsp_q_map) {
7c3df132
SK		 450 ql_log(ql_log_fatal, vha, 0x003c,
451 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 452 goto fail_rsp_map;
453 }
d7459527 454
e326d22a
QT		 455 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
456 if (ha->base_qpair == NULL) {
457 ql_log(ql_log_warn, vha, 0x00e0,
458 "Failed to allocate base queue pair memory.\n");
459 goto fail_base_qpair;
460 }
461
8abfa9e2 462 qla_init_base_qpair(vha, req, rsp);
e326d22a 463
c38d1baf 464 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
d7459527
MH		 465 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
466 GFP_KERNEL);
467 if (!ha->queue_pair_map) {
468 ql_log(ql_log_fatal, vha, 0x0180,
469 "Unable to allocate memory for queue pair ptrs.\n");
470 goto fail_qpair_map;
471 }
1d201c81
SD		 472 if (qla_mapq_alloc_qp_cpu_map(ha) != 0) {
473 kfree(ha->queue_pair_map);
474 ha->queue_pair_map = NULL;
475 goto fail_qpair_map;
476 }
d7459527
MH		 477 }
478
9a347ff4
CD		 479 /*
480 * Make sure we record at least the request and response queue zero in
481 * case we need to free them if part of the probe fails.
482 */
483 ha->rsp_q_map[0] = rsp;
484 ha->req_q_map[0] = req;
73208dfd
AC		 485 set_bit(0, ha->rsp_qid_map);
486 set_bit(0, ha->req_qid_map);
6a2cf8d3 487 return 0;
73208dfd 488
d7459527 489fail_qpair_map:
82de802a
QT		 490 kfree(ha->base_qpair);
491 ha->base_qpair = NULL;
492fail_base_qpair:
d7459527
MH		 493 kfree(ha->rsp_q_map);
494 ha->rsp_q_map = NULL;
73208dfd
AC		 495fail_rsp_map:
496 kfree(ha->req_q_map);
497 ha->req_q_map = NULL;
498fail_req_map:
499 return -ENOMEM;
500}
501
2afa19a9 502static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 503{
8ae6d9c7
GM		 504 if (IS_QLAFX00(ha)) {
505 if (req && req->ring_fx00)
506 dma_free_coherent(&ha->pdev->dev,
507 (req->length_fx00 + 1) * sizeof(request_t),
508 req->ring_fx00, req->dma_fx00);
509 } else if (req && req->ring)
73208dfd
AC		 510 dma_free_coherent(&ha->pdev->dev,
511 (req->length + 1) * sizeof(request_t),
512 req->ring, req->dma);
513
6d634067 514 if (req)
8d93f550 515 kfree(req->outstanding_cmds);
6d634067
BK		 516
517 kfree(req);
73208dfd
AC		 518}
519
2afa19a9
AC		 520static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
521{
8ae6d9c7 522 if (IS_QLAFX00(ha)) {
3f6c9be2 523 if (rsp && rsp->ring_fx00)
8ae6d9c7
GM		 524 dma_free_coherent(&ha->pdev->dev,
525 (rsp->length_fx00 + 1) * sizeof(request_t),
526 rsp->ring_fx00, rsp->dma_fx00);
527 } else if (rsp && rsp->ring) {
2afa19a9
AC		 528 dma_free_coherent(&ha->pdev->dev,
529 (rsp->length + 1) * sizeof(response_t),
530 rsp->ring, rsp->dma);
8ae6d9c7 531 }
6d634067 532 kfree(rsp);
2afa19a9
AC		 533}
534
73208dfd
AC		 535static void qla2x00_free_queues(struct qla_hw_data *ha)
536{
537 struct req_que *req;
538 struct rsp_que *rsp;
539 int cnt;
093df737 540 unsigned long flags;
73208dfd 541
82de802a
QT		 542 if (ha->queue_pair_map) {
543 kfree(ha->queue_pair_map);
544 ha->queue_pair_map = NULL;
545 }
546 if (ha->base_qpair) {
547 kfree(ha->base_qpair);
548 ha->base_qpair = NULL;
549 }
550
1d201c81 551 qla_mapq_free_qp_cpu_map(ha);
093df737 552 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 553 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 554 if (!test_bit(cnt, ha->req_qid_map))
555 continue;
556
73208dfd 557 req = ha->req_q_map[cnt];
093df737
QT		 558 clear_bit(cnt, ha->req_qid_map);
559 ha->req_q_map[cnt] = NULL;
560
561 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 562 qla2x00_free_req_que(ha, req);
093df737 563 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 564 }
093df737
QT		 565 spin_unlock_irqrestore(&ha->hardware_lock, flags);
566
73208dfd
AC		 567 kfree(ha->req_q_map);
568 ha->req_q_map = NULL;
2afa19a9 569
093df737
QT		 570
571 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 572 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 573 if (!test_bit(cnt, ha->rsp_qid_map))
574 continue;
575
2afa19a9 576 rsp = ha->rsp_q_map[cnt];
c3c42394 577 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 578 ha->rsp_q_map[cnt] = NULL;
579 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 580 qla2x00_free_rsp_que(ha, rsp);
093df737 581 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 582 }
093df737
QT		 583 spin_unlock_irqrestore(&ha->hardware_lock, flags);
584
2afa19a9
AC		 585 kfree(ha->rsp_q_map);
586 ha->rsp_q_map = NULL;
73208dfd
AC		 587}
588
1da177e4 589static char *
dc6d6d34 590qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
1da177e4 591{
e315cd28 592 struct qla_hw_data *ha = vha->hw;
dc6d6d34 593 static const char *const pci_bus_modes[] = {
1da177e4
LT		 594 "33", "66", "100", "133",
595 };
596 uint16_t pci_bus;
597
1da177e4
LT		 598 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
599 if (pci_bus) {
dc6d6d34
BVA		 600 snprintf(str, str_len, "PCI-X (%s MHz)",
601 pci_bus_modes[pci_bus]);
1da177e4
LT		 602 } else {
603 pci_bus = (ha->pci_attr & BIT_8) >> 8;
dc6d6d34 604 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
1da177e4 605 }
1da177e4 606
dc6d6d34 607 return str;
1da177e4
LT		 608}
609
fca29703 610static char *
dc6d6d34 611qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
fca29703 612{
dc6d6d34
BVA		 613 static const char *const pci_bus_modes[] = {
614 "33", "66", "100", "133",
615 };
e315cd28 616 struct qla_hw_data *ha = vha->hw;
fca29703 617 uint32_t pci_bus;
fca29703 618
62a276f8 619 if (pci_is_pcie(ha->pdev)) {
62a276f8 620 uint32_t lstat, lspeed, lwidth;
dc6d6d34 621 const char *speed_str;
fca29703 622
62a276f8 623 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
dc1d7b36
IJ		 624 lspeed = FIELD_GET(PCI_EXP_LNKCAP_SLS, lstat);
625 lwidth = FIELD_GET(PCI_EXP_LNKCAP_MLW, lstat);
fca29703 626
49300af7
SK		 627 switch (lspeed) {
628 case 1:
dc6d6d34 629 speed_str = "2.5GT/s";
49300af7
SK		 630 break;
631 case 2:
dc6d6d34 632 speed_str = "5.0GT/s";
49300af7
SK		 633 break;
634 case 3:
dc6d6d34 635 speed_str = "8.0GT/s";
49300af7 636 break;
efd39a2a
HM		 637 case 4:
638 speed_str = "16.0GT/s";
639 break;
49300af7 640 default:
dc6d6d34 641 speed_str = "<unknown>";
49300af7
SK		 642 break;
643 }
dc6d6d34 644 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
fca29703
AV		 645
646 return str;
647 }
648
fca29703 649 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
dc6d6d34
BVA		 650 if (pci_bus == 0 || pci_bus == 8)
651 snprintf(str, str_len, "PCI (%s MHz)",
652 pci_bus_modes[pci_bus >> 3]);
653 else
654 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
655 pci_bus & 4 ? 2 : 1,
656 pci_bus_modes[pci_bus & 3]);
fca29703
AV		 657
658 return str;
659}
660
e5f82ab8 661static char *
df57caba 662qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 663{
664 char un_str[10];
e315cd28 665 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 666
df57caba
HM		 667 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
668 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 669
670 if (ha->fw_attributes & BIT_9) {
671 strcat(str, "FLX");
672 return (str);
673 }
674
675 switch (ha->fw_attributes & 0xFF) {
676 case 0x7:
677 strcat(str, "EF");
678 break;
679 case 0x17:
680 strcat(str, "TP");
681 break;
682 case 0x37:
683 strcat(str, "IP");
684 break;
685 case 0x77:
686 strcat(str, "VI");
687 break;
688 default:
689 sprintf(un_str, "(%x)", ha->fw_attributes);
690 strcat(str, un_str);
691 break;
692 }
693 if (ha->fw_attributes & 0x100)
694 strcat(str, "X");
695
696 return (str);
697}
698
e5f82ab8 699static char *
df57caba 700qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 701{
e315cd28 702 struct qla_hw_data *ha = vha->hw;
f0883ac6 703
df57caba 704 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 705 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 706 return str;
fca29703
AV		 707}
708
6c18a43e 709void qla2x00_sp_free_dma(srb_t *sp)
fca29703 710{
25ff6af1 711 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 712 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
fca29703 713
9ba56b95
GM		 714 if (sp->flags & SRB_DMA_VALID) {
715 scsi_dma_unmap(cmd);
716 sp->flags &= ~SRB_DMA_VALID;
7c3df132 717 }
fca29703 718
9ba56b95
GM		 719 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
720 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
721 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
722 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
723 }
724
725 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
726 /* List assured to be having elements */
5ec9f904 727 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
9ba56b95
GM		 728 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
729 }
730
731 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
5ec9f904 732 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
d5ff0eed
JC		 733
734 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 735 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
736 }
737
738 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
82d8dfd2 739 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
fca29703 740
9ba56b95 741 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 742 ctx1->fcp_cmnd_dma);
efeda3bf
QT		 743 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
744 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
745 sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
9ba56b95 746 }
82d8dfd2
QT		 747
748 if (sp->flags & SRB_GOT_BUF)
749 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
9ba56b95
GM		 750}
751
6c18a43e 752void qla2x00_sp_compl(srb_t *sp, int res)
9ba56b95 753{
9ba56b95 754 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
219d27d7 755 struct completion *comp = sp->comp;
9ba56b95 756
31e6cdbe
SK		 757 /* kref: INIT */
758 kref_put(&sp->cmd_kref, qla2x00_sp_release);
740e2935 759 cmd->result = res;
55976163 760 sp->type = 0;
79e30b88 761 scsi_done(cmd);
219d27d7
BVA		 762 if (comp)
763 complete(comp);
fca29703
AV		 764}
765
6c18a43e 766void qla2xxx_qpair_sp_free_dma(srb_t *sp)
d7459527 767{
d7459527
MH		 768 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
769 struct qla_hw_data *ha = sp->fcport->vha->hw;
d7459527
MH		 770
771 if (sp->flags & SRB_DMA_VALID) {
772 scsi_dma_unmap(cmd);
773 sp->flags &= ~SRB_DMA_VALID;
774 }
775
776 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
777 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
778 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
779 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
780 }
781
782 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
783 /* List assured to be having elements */
5ec9f904 784 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
d7459527
MH		 785 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
786 }
787
50b81275 788 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
5ec9f904 789 struct crc_context *difctx = sp->u.scmd.crc_ctx;
50b81275
GM		 790 struct dsd_dma *dif_dsd, *nxt_dsd;
791
792 list_for_each_entry_safe(dif_dsd, nxt_dsd,
793 &difctx->ldif_dma_hndl_list, list) {
794 list_del(&dif_dsd->list);
795 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
796 dif_dsd->dsd_list_dma);
797 kfree(dif_dsd);
798 difctx->no_dif_bundl--;
799 }
800
801 list_for_each_entry_safe(dif_dsd, nxt_dsd,
802 &difctx->ldif_dsd_list, list) {
803 list_del(&dif_dsd->list);
804 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
805 dif_dsd->dsd_list_dma);
806 kfree(dif_dsd);
807 difctx->no_ldif_dsd--;
808 }
809
810 if (difctx->no_ldif_dsd) {
811 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
812 "%s: difctx->no_ldif_dsd=%x\n",
813 __func__, difctx->no_ldif_dsd);
814 }
815
816 if (difctx->no_dif_bundl) {
817 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
818 "%s: difctx->no_dif_bundl=%x\n",
819 __func__, difctx->no_dif_bundl);
820 }
821 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
d7459527 822 }
d8f945bf
BVA		 823
824 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
82d8dfd2 825 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
d8f945bf
BVA		 826
827 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
828 ctx1->fcp_cmnd_dma);
efeda3bf
QT		 829 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
830 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
831 sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
d8f945bf
BVA		 832 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
833 }
834
835 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
5ec9f904 836 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
d8f945bf 837
5ec9f904 838 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
d8f945bf
BVA		 839 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
840 }
82d8dfd2
QT		 841
842 if (sp->flags & SRB_GOT_BUF)
843 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
d7459527
MH		 844}
845
6c18a43e 846void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
d7459527 847{
d7459527 848 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
219d27d7 849 struct completion *comp = sp->comp;
d7459527 850
31e6cdbe
SK		 851 /* ref: INIT */
852 kref_put(&sp->cmd_kref, qla2x00_sp_release);
711a08d7 853 cmd->result = res;
55976163 854 sp->type = 0;
79e30b88 855 scsi_done(cmd);
219d27d7
BVA		 856 if (comp)
857 complete(comp);
d7459527
MH		 858}
859
1da177e4 860static int
f5e3e40b 861qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 862{
134ae078 863 scsi_qla_host_t *vha = shost_priv(host);
fca29703 864 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 865 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 866 struct qla_hw_data *ha = vha->hw;
867 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 868 srb_t *sp;
869 int rval;
870
2dbb02fd
BVA		 871 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
872 WARN_ON_ONCE(!rport)) {
04dfaa53
MFO		 873 cmd->result = DID_NO_CONNECT << 16;
874 goto qc24_fail_command;
875 }
876
5601236b 877 if (ha->mqenable) {
6d58ef05
BVA		 878 uint32_t tag;
879 uint16_t hwq;
880 struct qla_qpair *qpair = NULL;
881
c7d6b2c2 882 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd));
f664a3cc
JA		 883 hwq = blk_mq_unique_tag_to_hwq(tag);
884 qpair = ha->queue_pair_map[hwq];
5601236b
MH		 885
886 if (qpair)
887 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 888 }
889
85880801 890 if (ha->flags.eeh_busy) {
7c3df132 891 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 892 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 893 "PCI Channel IO permanent failure, exiting "
894 "cmd=%p.\n", cmd);
b9b12f73 895 cmd->result = DID_NO_CONNECT << 16;
7c3df132 896 } else {
5f28d2d7 897 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 898 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 899 cmd->result = DID_REQUEUE << 16;
7c3df132 900 }
14e660e6
SJ		 901 goto qc24_fail_command;
902 }
903
19a7b4ae
JSEC		 904 rval = fc_remote_port_chkready(rport);
905 if (rval) {
906 cmd->result = rval;
5f28d2d7 907 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 908 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
909 cmd, rval);
fca29703
AV		 910 goto qc24_fail_command;
911 }
912
bad75002
AE		 913 if (!vha->flags.difdix_supported &&
914 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 915 ql_dbg(ql_dbg_io, vha, 0x3004,
916 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
917 cmd);
bad75002
AE		 918 cmd->result = DID_NO_CONNECT << 16;
919 goto qc24_fail_command;
920 }
aa651be8 921
707531bc
SK		 922 if (!fcport || fcport->deleted) {
923 cmd->result = DID_IMM_RETRY << 16;
aa651be8
CD		 924 goto qc24_fail_command;
925 }
926
78c3e5e6 927 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
fca29703 928 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 929 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 930 ql_dbg(ql_dbg_io, vha, 0x3005,
931 "Returning DNC, fcport_state=%d loop_state=%d.\n",
932 atomic_read(&fcport->state),
933 atomic_read(&base_vha->loop_state));
fca29703
AV		 934 cmd->result = DID_NO_CONNECT << 16;
935 goto qc24_fail_command;
936 }
7b594131 937 goto qc24_target_busy;
fca29703
AV		 938 }
939
e05fe292
CD		 940 /*
941 * Return target busy if we've received a non-zero retry_delay_timer
942 * in a FCP_RSP.
943 */
975f7d46
BP		 944 if (fcport->retry_delay_timestamp == 0) {
945 /* retry delay not set */
946 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 947 fcport->retry_delay_timestamp = 0;
948 else
949 goto qc24_target_busy;
950
85cffefa 951 sp = scsi_cmd_priv(cmd);
31e6cdbe 952 /* ref: INIT */
85cffefa 953 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
fca29703 954
9ba56b95
GM		 955 sp->u.scmd.cmd = cmd;
956 sp->type = SRB_SCSI_CMD;
9ba56b95
GM		 957 sp->free = qla2x00_sp_free_dma;
958 sp->done = qla2x00_sp_compl;
959
e315cd28 960 rval = ha->isp_ops->start_scsi(sp);
7c3df132 961 if (rval != QLA_SUCCESS) {
53016ed3 962 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 963 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 964 goto qc24_host_busy_free_sp;
7c3df132 965 }
fca29703 966
fca29703
AV		 967 return 0;
968
969qc24_host_busy_free_sp:
31e6cdbe
SK		 970 /* ref: INIT */
971 kref_put(&sp->cmd_kref, qla2x00_sp_release);
fca29703 972
7b594131
MC		 973qc24_target_busy:
974 return SCSI_MLQUEUE_TARGET_BUSY;
975
fca29703 976qc24_fail_command:
79e30b88 977 scsi_done(cmd);
fca29703
AV		 978
979 return 0;
980}
981
d7459527
MH		 982/* For MQ supported I/O */
983int
984qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
985 struct qla_qpair *qpair)
986{
987 scsi_qla_host_t *vha = shost_priv(host);
988 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
989 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
990 struct qla_hw_data *ha = vha->hw;
991 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
992 srb_t *sp;
993 int rval;
994
6098c300 995 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16);
d7459527
MH		 996 if (rval) {
997 cmd->result = rval;
998 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
999 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
1000 cmd, rval);
1001 goto qc24_fail_command;
1002 }
1003
f7a0ed47
QT		 1004 if (!qpair->online) {
1005 ql_dbg(ql_dbg_io, vha, 0x3077,
1006 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy);
1007 cmd->result = DID_NO_CONNECT << 16;
1008 goto qc24_fail_command;
1009 }
1010
707531bc
SK		 1011 if (!fcport || fcport->deleted) {
1012 cmd->result = DID_IMM_RETRY << 16;
d7459527
MH		 1013 goto qc24_fail_command;
1014 }
1015
78c3e5e6 1016 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
d7459527
MH		 1017 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
1018 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
1019 ql_dbg(ql_dbg_io, vha, 0x3077,
1020 "Returning DNC, fcport_state=%d loop_state=%d.\n",
1021 atomic_read(&fcport->state),
1022 atomic_read(&base_vha->loop_state));
1023 cmd->result = DID_NO_CONNECT << 16;
1024 goto qc24_fail_command;
1025 }
1026 goto qc24_target_busy;
1027 }
1028
1029 /*
1030 * Return target busy if we've received a non-zero retry_delay_timer
1031 * in a FCP_RSP.
1032 */
1033 if (fcport->retry_delay_timestamp == 0) {
1034 /* retry delay not set */
1035 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1036 fcport->retry_delay_timestamp = 0;
1037 else
1038 goto qc24_target_busy;
1039
85cffefa 1040 sp = scsi_cmd_priv(cmd);
31e6cdbe 1041 /* ref: INIT */
85cffefa 1042 qla2xxx_init_sp(sp, vha, qpair, fcport);
d7459527
MH		 1043
1044 sp->u.scmd.cmd = cmd;
1045 sp->type = SRB_SCSI_CMD;
d7459527
MH		 1046 sp->free = qla2xxx_qpair_sp_free_dma;
1047 sp->done = qla2xxx_qpair_sp_compl;
d7459527
MH		 1048
1049 rval = ha->isp_ops->start_scsi_mq(sp);
1050 if (rval != QLA_SUCCESS) {
1051 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1052 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
d7459527
MH		 1053 goto qc24_host_busy_free_sp;
1054 }
1055
1056 return 0;
1057
1058qc24_host_busy_free_sp:
31e6cdbe
SK		 1059 /* ref: INIT */
1060 kref_put(&sp->cmd_kref, qla2x00_sp_release);
d7459527 1061
d7459527
MH		 1062qc24_target_busy:
1063 return SCSI_MLQUEUE_TARGET_BUSY;
1064
1065qc24_fail_command:
79e30b88 1066 scsi_done(cmd);
d7459527
MH		 1067
1068 return 0;
1069}
1070
1da177e4
LT		 1071/*
1072 * qla2x00_wait_for_hba_online
fa2a1ce5 1073 * Wait till the HBA is online after going through
1da177e4
LT		 1074 * <= MAX_RETRIES_OF_ISP_ABORT or
1075 * finally HBA is disabled ie marked offline
1076 *
1077 * Input:
1078 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1079 *
1080 * Note:
1da177e4
LT		 1081 * Does context switching-Release SPIN_LOCK
1082 * (if any) before calling this routine.
1083 *
1084 * Return:
1085 * Success (Adapter is online) : 0
1086 * Failed (Adapter is offline/disabled) : 1
1087 */
854165f4 1088int
e315cd28 1089qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1090{
fca29703
AV		 1091 int return_status;
1092 unsigned long wait_online;
e315cd28
AC		 1093 struct qla_hw_data *ha = vha->hw;
1094 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1095
fa2a1ce5 1096 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1097 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1098 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1099 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1100 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1101
1102 msleep(1000);
1103 }
e315cd28 1104 if (base_vha->flags.online)
fa2a1ce5 1105 return_status = QLA_SUCCESS;
1da177e4
LT		 1106 else
1107 return_status = QLA_FUNCTION_FAILED;
1108
1da177e4
LT		 1109 return (return_status);
1110}
1111
726b8548
QT		 1112static inline int test_fcport_count(scsi_qla_host_t *vha)
1113{
1114 struct qla_hw_data *ha = vha->hw;
1115 unsigned long flags;
1116 int res;
9efea843 1117 /* Return 0 = sleep, x=wake */
726b8548
QT		 1118
1119 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1120 ql_dbg(ql_dbg_init, vha, 0x00ec,
1121 "tgt %p, fcport_count=%d\n",
1122 vha, vha->fcport_count);
726b8548 1123 res = (vha->fcport_count == 0);
9efea843
QT		 1124 if (res) {
1125 struct fc_port *fcport;
1126
1127 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1128 if (fcport->deleted != QLA_SESS_DELETED) {
1129 /* session(s) may not be fully logged in
1130 * (ie fcport_count=0), but session
1131 * deletion thread(s) may be inflight.
1132 */
1133
1134 res = 0;
1135 break;
1136 }
1137 }
1138 }
726b8548
QT		 1139 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1140
1141 return res;
1142}
1143
1144/*
1145 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1146 * it has dependency on UNLOADING flag to stop device discovery
1147 */
efa93f48 1148void
726b8548
QT		 1149qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1150{
f5187b7d
QT		 1151 u8 i;
1152
3c75ad1d 1153 qla2x00_mark_all_devices_lost(vha);
726b8548 1154
8b1062d5
MW		 1155 for (i = 0; i < 10; i++) {
1156 if (wait_event_timeout(vha->fcport_waitQ,
1157 test_fcport_count(vha), HZ) > 0)
1158 break;
1159 }
f5187b7d 1160
fd5564ba 1161 flush_workqueue(vha->hw->wq);
726b8548
QT		 1162}
1163
86fbee86 1164/*
638a1a01
SC		 1165 * qla2x00_wait_for_hba_ready
1166 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1167 *
1168 * Input:
1169 * ha - pointer to host adapter structure
1170 *
1171 * Note:
1172 * Does context switching-Release SPIN_LOCK
1173 * (if any) before calling this routine.
1174 *
86fbee86 1175 */
638a1a01
SC		 1176static void
1177qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1178{
86fbee86 1179 struct qla_hw_data *ha = vha->hw;
783e0dc4 1180 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1181
1d483901
DC		 1182 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1183 ha->flags.mbox_busy) ||
1184 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1185 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1186 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1187 break;
86fbee86 1188 msleep(1000);
783e0dc4 1189 }
86fbee86
LC		 1190}
1191
2533cf67
LC		 1192int
1193qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1194{
1195 int return_status;
1196 unsigned long wait_reset;
1197 struct qla_hw_data *ha = vha->hw;
1198 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1199
1200 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1201 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1202 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1203 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1204 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1205
1206 msleep(1000);
1207
1208 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1209 ha->flags.chip_reset_done)
1210 break;
1211 }
1212 if (ha->flags.chip_reset_done)
1213 return_status = QLA_SUCCESS;
1214 else
1215 return_status = QLA_FUNCTION_FAILED;
1216
1217 return return_status;
1218}
1219
1da177e4
LT		 1220/**************************************************************************
1221* qla2xxx_eh_abort
1222*
1223* Description:
1224* The abort function will abort the specified command.
1225*
1226* Input:
1227* cmd = Linux SCSI command packet to be aborted.
1228*
1229* Returns:
1230* Either SUCCESS or FAILED.
1231*
1232* Note:
2ea00202 1233* Only return FAILED if command not returned by firmware.
1da177e4 1234**************************************************************************/
e5f82ab8 1235static int
1da177e4
LT		 1236qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1237{
e315cd28 1238 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
8dd9593c 1239 DECLARE_COMPLETION_ONSTACK(comp);
f4f051eb 1240 srb_t *sp;
4e98d3b8 1241 int ret;
9cb78c16
HR		 1242 unsigned int id;
1243 uint64_t lun;
219d27d7 1244 int rval;
e315cd28 1245 struct qla_hw_data *ha = vha->hw;
f45bca8c
QT		 1246 uint32_t ratov_j;
1247 struct qla_qpair *qpair;
1248 unsigned long flags;
3d33b303 1249 int fast_fail_status = SUCCESS;
1da177e4 1250
a465537a
SC		 1251 if (qla2x00_isp_reg_stat(ha)) {
1252 ql_log(ql_log_info, vha, 0x8042,
1253 "PCI/Register disconnect, exiting.\n");
f7a0ed47 1254 qla_pci_set_eeh_busy(vha);
a465537a
SC		 1255 return FAILED;
1256 }
1da177e4 1257
3d33b303 1258 /* Save any FAST_IO_FAIL value to return later if abort succeeds */
4e98d3b8
AV		 1259 ret = fc_block_scsi_eh(cmd);
1260 if (ret != 0)
3d33b303 1261 fast_fail_status = ret;
4e98d3b8 1262
85cffefa 1263 sp = scsi_cmd_priv(cmd);
f45bca8c 1264 qpair = sp->qpair;
585def9b 1265
dbf1f53c
SK		 1266 vha->cmd_timeout_cnt++;
1267
f45bca8c 1268 if ((sp->fcport && sp->fcport->deleted) || !qpair)
3d33b303 1269 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED;
1da177e4 1270
f45bca8c 1271 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
f45bca8c
QT		 1272 sp->comp = &comp;
1273 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1274
585def9b
QT		 1275
1276 id = cmd->device->id;
1277 lun = cmd->device->lun;
1da177e4 1278
7c3df132 1279 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1280 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1281 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1282
f45bca8c
QT		 1283 /*
1284 * Abort will release the original Command/sp from FW. Let the
1285 * original command call scsi_done. In return, he will wakeup
1286 * this sleeping thread.
1287 */
f934c9d0 1288 rval = ha->isp_ops->abort_command(sp);
f45bca8c 1289
219d27d7
BVA		 1290 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1291 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
f934c9d0 1292
f45bca8c
QT		 1293 /* Wait for the command completion. */
1294 ratov_j = ha->r_a_tov/10 * 4 * 1000;
1295 ratov_j = msecs_to_jiffies(ratov_j);
219d27d7
BVA		 1296 switch (rval) {
1297 case QLA_SUCCESS:
8dd9593c
BVA		 1298 if (!wait_for_completion_timeout(&comp, ratov_j)) {
1299 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1300 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
f45bca8c 1301 __func__, ha->r_a_tov/10);
8dd9593c
BVA		 1302 ret = FAILED;
1303 } else {
3d33b303 1304 ret = fast_fail_status;
8dd9593c
BVA		 1305 }
1306 break;
219d27d7 1307 default:
219d27d7
BVA		 1308 ret = FAILED;
1309 break;
1da177e4 1310 }
219d27d7 1311
8dd9593c 1312 sp->comp = NULL;
f45bca8c 1313
7c3df132 1314 ql_log(ql_log_info, vha, 0x801c,
219d27d7
BVA		 1315 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1316 vha->host_no, id, lun, ret);
1da177e4 1317
f4f051eb 1318 return ret;
1319}
1da177e4 1320
b843adde
QT		 1321#define ABORT_POLLING_PERIOD 1000
1322#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
1323
fcef0893
BVA		 1324/*
1325 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1326 */
c39587bc
AE		 1327static int
1328__qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t,
1329 uint64_t l, enum nexus_wait_type type)
f4f051eb 1330{
17d98630 1331 int cnt, match, status;
18e144d3 1332 unsigned long flags;
c39587bc
AE		 1333 scsi_qla_host_t *vha = qpair->vha;
1334 struct req_que *req = qpair->req;
4d78c973 1335 srb_t *sp;
9ba56b95 1336 struct scsi_cmnd *cmd;
b843adde
QT		 1337 unsigned long wait_iter = ABORT_WAIT_ITER;
1338 bool found;
1339 struct qla_hw_data *ha = vha->hw;
1da177e4 1340
523ec773 1341 status = QLA_SUCCESS;
17d98630 1342
b843adde
QT		 1343 while (wait_iter--) {
1344 found = false;
17d98630 1345
c39587bc 1346 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
b843adde
QT		 1347 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1348 sp = req->outstanding_cmds[cnt];
1349 if (!sp)
1350 continue;
1351 if (sp->type != SRB_SCSI_CMD)
1352 continue;
1353 if (vha->vp_idx != sp->vha->vp_idx)
1354 continue;
1355 match = 0;
1356 cmd = GET_CMD_SP(sp);
1357 switch (type) {
1358 case WAIT_HOST:
1359 match = 1;
1360 break;
1361 case WAIT_TARGET:
1362 if (sp->fcport)
1363 match = sp->fcport->d_id.b24 == t;
1364 else
1365 match = 0;
1366 break;
1367 case WAIT_LUN:
1368 if (sp->fcport)
1369 match = (sp->fcport->d_id.b24 == t &&
1370 cmd->device->lun == l);
1371 else
1372 match = 0;
1373 break;
1374 }
1375 if (!match)
1376 continue;
1377
1378 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1379
1380 if (unlikely(pci_channel_offline(ha->pdev)) ||
1381 ha->flags.eeh_busy) {
1382 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1383 "Return:eh_wait.\n");
1384 return status;
1385 }
1386
1387 /*
1388 * SRB_SCSI_CMD is still in the outstanding_cmds array.
1389 * it means scsi_done has not called. Wait for it to
1390 * clear from outstanding_cmds.
1391 */
1392 msleep(ABORT_POLLING_PERIOD);
1393 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1394 found = true;
1395 }
1396 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1397
1398 if (!found)
1399 break;
1da177e4 1400 }
b843adde 1401
33902009 1402 if (wait_iter == -1)
b843adde 1403 status = QLA_FUNCTION_FAILED;
c39587bc
AE		 1404
1405 return status;
1406}
1407
1408int
1409qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1410 uint64_t l, enum nexus_wait_type type)
1411{
1412 struct qla_qpair *qpair;
1413 struct qla_hw_data *ha = vha->hw;
1414 int i, status = QLA_SUCCESS;
523ec773 1415
c39587bc
AE		 1416 status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l,
1417 type);
1418 for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) {
1419 qpair = ha->queue_pair_map[i];
1420 if (!qpair)
1421 continue;
1422 status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l,
1423 type);
1424 }
523ec773 1425 return status;
1da177e4
LT		 1426}
1427
523ec773
AV		 1428static char *reset_errors[] = {
1429 "HBA not online",
1430 "HBA not ready",
1431 "Task management failed",
1432 "Waiting for command completions",
1433};
1da177e4 1434
e5f82ab8 1435static int
cbe1f0d7 1436qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1da177e4 1437{
cbe1f0d7
HR		 1438 struct scsi_device *sdev = cmd->device;
1439 scsi_qla_host_t *vha = shost_priv(sdev->host);
1440 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1441 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1442 struct qla_hw_data *ha = vha->hw;
523ec773 1443 int err;
1da177e4 1444
cbe1f0d7
HR		 1445 if (qla2x00_isp_reg_stat(ha)) {
1446 ql_log(ql_log_info, vha, 0x803e,
1447 "PCI/Register disconnect, exiting.\n");
1448 qla_pci_set_eeh_busy(vha);
1449 return FAILED;
1450 }
1451
7c3df132 1452 if (!fcport) {
523ec773 1453 return FAILED;
7c3df132 1454 }
1da177e4 1455
cbe1f0d7 1456 err = fc_block_rport(rport);
4e98d3b8
AV		 1457 if (err != 0)
1458 return err;
1459
7f4374e6 1460 if (fcport->deleted)
c39587bc 1461 return FAILED;
7f4374e6 1462
7c3df132 1463 ql_log(ql_log_info, vha, 0x8009,
cbe1f0d7
HR		 1464 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no,
1465 sdev->id, sdev->lun, cmd);
1da177e4 1466
523ec773 1467 err = 0;
7c3df132
SK		 1468 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1469 ql_log(ql_log_warn, vha, 0x800a,
1470 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1471 goto eh_reset_failed;
7c3df132 1472 }
523ec773 1473 err = 2;
cbe1f0d7 1474 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1)
7c3df132
SK		 1475 != QLA_SUCCESS) {
1476 ql_log(ql_log_warn, vha, 0x800c,
1477 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1478 goto eh_reset_failed;
7c3df132 1479 }
523ec773 1480 err = 3;
da7c21b7
QT		 1481 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24,
1482 cmd->device->lun,
1483 WAIT_LUN) != QLA_SUCCESS) {
7c3df132 1484 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1485 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1486 goto eh_reset_failed;
7c3df132 1487 }
523ec773 1488
7c3df132 1489 ql_log(ql_log_info, vha, 0x800e,
cbe1f0d7
HR		 1490 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n",
1491 vha->host_no, sdev->id, sdev->lun, cmd);
523ec773
AV		 1492
1493 return SUCCESS;
1494
4d78c973 1495eh_reset_failed:
7c3df132 1496 ql_log(ql_log_info, vha, 0x800f,
cbe1f0d7
HR		 1497 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1498 reset_errors[err], vha->host_no, sdev->id, sdev->lun,
cfb0919c 1499 cmd);
dbf1f53c 1500 vha->reset_cmd_err_cnt++;
523ec773
AV		 1501 return FAILED;
1502}
1da177e4 1503
1da177e4 1504static int
523ec773 1505qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1506{
e56b2234
HR		 1507 struct scsi_device *sdev = cmd->device;
1508 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1509 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport));
e315cd28 1510 struct qla_hw_data *ha = vha->hw;
e56b2234
HR		 1511 fc_port_t *fcport = *(fc_port_t **)rport->dd_data;
1512 int err;
1da177e4 1513
a465537a
SC		 1514 if (qla2x00_isp_reg_stat(ha)) {
1515 ql_log(ql_log_info, vha, 0x803f,
1516 "PCI/Register disconnect, exiting.\n");
f7a0ed47 1517 qla_pci_set_eeh_busy(vha);
a465537a
SC		 1518 return FAILED;
1519 }
1520
e56b2234
HR		 1521 if (!fcport) {
1522 return FAILED;
1523 }
1524
1525 err = fc_block_rport(rport);
1526 if (err != 0)
1527 return err;
1528
1529 if (fcport->deleted)
c39587bc 1530 return FAILED;
e56b2234
HR		 1531
1532 ql_log(ql_log_info, vha, 0x8009,
1533 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no,
1534 sdev->id, cmd);
1535
1536 err = 0;
1537 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1538 ql_log(ql_log_warn, vha, 0x800a,
1539 "Wait for hba online failed for cmd=%p.\n", cmd);
1540 goto eh_reset_failed;
1541 }
1542 err = 2;
1543 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) {
1544 ql_log(ql_log_warn, vha, 0x800c,
1545 "target_reset failed for cmd=%p.\n", cmd);
1546 goto eh_reset_failed;
1547 }
1548 err = 3;
da7c21b7
QT		 1549 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 0,
1550 WAIT_TARGET) != QLA_SUCCESS) {
e56b2234
HR		 1551 ql_log(ql_log_warn, vha, 0x800d,
1552 "wait for pending cmds failed for cmd=%p.\n", cmd);
1553 goto eh_reset_failed;
1554 }
1555
1556 ql_log(ql_log_info, vha, 0x800e,
1557 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n",
1558 vha->host_no, sdev->id, cmd);
1559
1560 return SUCCESS;
1561
1562eh_reset_failed:
1563 ql_log(ql_log_info, vha, 0x800f,
1564 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1565 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1566 cmd);
1567 vha->reset_cmd_err_cnt++;
1568 return FAILED;
1da177e4
LT		 1569}
1570
1da177e4
LT		 1571/**************************************************************************
1572* qla2xxx_eh_bus_reset
1573*
1574* Description:
1575* The bus reset function will reset the bus and abort any executing
1576* commands.
1577*
1578* Input:
1579* cmd = Linux SCSI command packet of the command that cause the
1580* bus reset.
1581*
1582* Returns:
1583* SUCCESS/FAILURE (defined as macro in scsi.h).
1584*
1585**************************************************************************/
e5f82ab8 1586static int
1da177e4
LT		 1587qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1588{
e315cd28 1589 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
2c3dfe3f 1590 int ret = FAILED;
9cb78c16
HR		 1591 unsigned int id;
1592 uint64_t lun;
a465537a
SC		 1593 struct qla_hw_data *ha = vha->hw;
1594
1595 if (qla2x00_isp_reg_stat(ha)) {
1596 ql_log(ql_log_info, vha, 0x8040,
1597 "PCI/Register disconnect, exiting.\n");
f7a0ed47 1598 qla_pci_set_eeh_busy(vha);
a465537a
SC		 1599 return FAILED;
1600 }
f4f051eb 1601
f4f051eb 1602 id = cmd->device->id;
1603 lun = cmd->device->lun;
1da177e4 1604
7f4374e6
QT		 1605 if (qla2x00_chip_is_down(vha))
1606 return ret;
1607
7c3df132 1608 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1609 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1610
e315cd28 1611 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1612 ql_log(ql_log_fatal, vha, 0x8013,
1613 "Wait for hba online failed board disabled.\n");
f4f051eb 1614 goto eh_bus_reset_done;
1da177e4
LT		 1615 }
1616
ad537689
SK		 1617 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1618 ret = SUCCESS;
1619
f4f051eb 1620 if (ret == FAILED)
1621 goto eh_bus_reset_done;
1da177e4 1622
9a41a62b 1623 /* Flush outstanding commands. */
4d78c973 1624 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1625 QLA_SUCCESS) {
1626 ql_log(ql_log_warn, vha, 0x8014,
1627 "Wait for pending commands failed.\n");
9a41a62b 1628 ret = FAILED;
7c3df132 1629 }
1da177e4 1630
f4f051eb 1631eh_bus_reset_done:
7c3df132 1632 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1633 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1634 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1635
f4f051eb 1636 return ret;
1da177e4
LT		 1637}
1638
1639/**************************************************************************
1640* qla2xxx_eh_host_reset
1641*
1642* Description:
1643* The reset function will reset the Adapter.
1644*
1645* Input:
1646* cmd = Linux SCSI command packet of the command that cause the
1647* adapter reset.
1648*
1649* Returns:
1650* Either SUCCESS or FAILED.
1651*
1652* Note:
1653**************************************************************************/
e5f82ab8 1654static int
1da177e4
LT		 1655qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1656{
e315cd28 1657 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1658 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1659 int ret = FAILED;
9cb78c16
HR		 1660 unsigned int id;
1661 uint64_t lun;
e315cd28 1662 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1663
a465537a
SC		 1664 if (qla2x00_isp_reg_stat(ha)) {
1665 ql_log(ql_log_info, vha, 0x8041,
1666 "PCI/Register disconnect, exiting.\n");
f7a0ed47 1667 qla_pci_set_eeh_busy(vha);
a465537a
SC		 1668 return SUCCESS;
1669 }
1670
f4f051eb 1671 id = cmd->device->id;
1672 lun = cmd->device->lun;
f4f051eb 1673
7c3df132 1674 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1675 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1676
63ee7072
CD		 1677 /*
1678 * No point in issuing another reset if one is active. Also do not
1679 * attempt a reset if we are updating flash.
1680 */
1681 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1682 goto eh_host_reset_lock;
1da177e4 1683
e315cd28
AC		 1684 if (vha != base_vha) {
1685 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1686 goto eh_host_reset_lock;
e315cd28 1687 } else {
7ec0effd 1688 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1689 if (!qla82xx_fcoe_ctx_reset(vha)) {
1690 /* Ctx reset success */
1691 ret = SUCCESS;
1692 goto eh_host_reset_lock;
1693 }
1694 /* fall thru if ctx reset failed */
1695 }
68ca949c
AC		 1696 if (ha->wq)
1697 flush_workqueue(ha->wq);
1698
e315cd28 1699 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1700 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1701 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1702 /* failed. schedule dpc to try */
1703 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1704
7c3df132
SK		 1705 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1706 ql_log(ql_log_warn, vha, 0x802a,
1707 "wait for hba online failed.\n");
e315cd28 1708 goto eh_host_reset_lock;
7c3df132 1709 }
e315cd28
AC		 1710 }
1711 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1712 }
1da177e4 1713
e315cd28 1714 /* Waiting for command to be returned to OS.*/
4d78c973 1715 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1716 QLA_SUCCESS)
f4f051eb 1717 ret = SUCCESS;
1da177e4 1718
f4f051eb 1719eh_host_reset_lock:
cfb0919c 1720 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1721 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1722 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1723
f4f051eb 1724 return ret;
1725}
1da177e4
LT		 1726
1727/*
1728* qla2x00_loop_reset
1729* Issue loop reset.
1730*
1731* Input:
1732* ha = adapter block pointer.
1733*
1734* Returns:
1735* 0 = success
1736*/
a4722cf2 1737int
e315cd28 1738qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1739{
0c8c39af 1740 int ret;
e315cd28 1741 struct qla_hw_data *ha = vha->hw;
1da177e4 1742
0b7a9fd9
QT		 1743 if (IS_QLAFX00(ha))
1744 return QLA_SUCCESS;
8ae6d9c7 1745
6246b8a1 1746 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1747 atomic_set(&vha->loop_state, LOOP_DOWN);
1748 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
3c75ad1d 1749 qla2x00_mark_all_devices_lost(vha);
e315cd28 1750 ret = qla2x00_full_login_lip(vha);
0c8c39af 1751 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1752 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1753 "full_login_lip=%d.\n", ret);
749af3d5 1754 }
0c8c39af
AV		 1755 }
1756
0d6e61bc 1757 if (ha->flags.enable_lip_reset) {
e315cd28 1758 ret = qla2x00_lip_reset(vha);
ad537689 1759 if (ret != QLA_SUCCESS)
7c3df132
SK		 1760 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1761 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1762 }
1763
1da177e4 1764 /* Issue marker command only when we are going to start the I/O */
e315cd28 1765 vha->marker_needed = 1;
1da177e4 1766
0c8c39af 1767 return QLA_SUCCESS;
1da177e4
LT		 1768}
1769
c81ef0ed
BVA		 1770/*
1771 * The caller must ensure that no completion interrupts will happen
1772 * while this function is in progress.
1773 */
c4e521b6
BVA		 1774static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1775 unsigned long *flags)
1776 __releases(qp->qp_lock_ptr)
1777 __acquires(qp->qp_lock_ptr)
1778{
219d27d7 1779 DECLARE_COMPLETION_ONSTACK(comp);
c4e521b6
BVA		 1780 scsi_qla_host_t *vha = qp->vha;
1781 struct qla_hw_data *ha = vha->hw;
c81ef0ed 1782 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
219d27d7 1783 int rval;
f45bca8c
QT		 1784 bool ret_cmd;
1785 uint32_t ratov_j;
c4e521b6 1786
2494c286
BVA		 1787 lockdep_assert_held(qp->qp_lock_ptr);
1788
f45bca8c
QT		 1789 if (qla2x00_chip_is_down(vha)) {
1790 sp->done(sp, res);
219d27d7 1791 return;
f45bca8c 1792 }
219d27d7
BVA		 1793
1794 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1795 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1796 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1797 !qla2x00_isp_reg_stat(ha))) {
f45bca8c
QT		 1798 if (sp->comp) {
1799 sp->done(sp, res);
1800 return;
1801 }
1802
219d27d7 1803 sp->comp = &comp;
219d27d7
BVA		 1804 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1805
f45bca8c
QT		 1806 rval = ha->isp_ops->abort_command(sp);
1807 /* Wait for command completion. */
1808 ret_cmd = false;
1809 ratov_j = ha->r_a_tov/10 * 4 * 1000;
1810 ratov_j = msecs_to_jiffies(ratov_j);
219d27d7
BVA		 1811 switch (rval) {
1812 case QLA_SUCCESS:
f45bca8c
QT		 1813 if (wait_for_completion_timeout(&comp, ratov_j)) {
1814 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1815 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1816 __func__, ha->r_a_tov/10);
1817 ret_cmd = true;
1818 }
1819 /* else FW return SP to driver */
219d27d7 1820 break;
f45bca8c
QT		 1821 default:
1822 ret_cmd = true;
219d27d7 1823 break;
c4e521b6 1824 }
219d27d7
BVA		 1825
1826 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
19597cad
QT		 1827 switch (sp->type) {
1828 case SRB_SCSI_CMD:
1829 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd)))
1830 sp->done(sp, res);
1831 break;
1832 default:
1833 if (ret_cmd)
1834 sp->done(sp, res);
1835 break;
1836 }
f45bca8c
QT		 1837 } else {
1838 sp->done(sp, res);
c4e521b6 1839 }
c4e521b6
BVA		 1840}
1841
c81ef0ed
BVA		 1842/*
1843 * The caller must ensure that no completion interrupts will happen
1844 * while this function is in progress.
1845 */
bbead493
QT		 1846static void
1847__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
df4bf0bb 1848{
eb023220 1849 int cnt;
df4bf0bb
AV		 1850 unsigned long flags;
1851 srb_t *sp;
bbead493 1852 scsi_qla_host_t *vha = qp->vha;
e315cd28 1853 struct qla_hw_data *ha = vha->hw;
73208dfd 1854 struct req_que *req;
c5419e26
QT		 1855 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1856 struct qla_tgt_cmd *cmd;
c0cb4496 1857
6a2cf8d3
BK		 1858 if (!ha->req_q_map)
1859 return;
bbead493
QT		 1860 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1861 req = qp->req;
1862 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1863 sp = req->outstanding_cmds[cnt];
1864 if (sp) {
0367076b
NJ		 1865 if (qla2x00_chip_is_down(vha)) {
1866 req->outstanding_cmds[cnt] = NULL;
0367076b 1867 sp->done(sp, res);
0367076b
NJ		 1868 continue;
1869 }
1870
6b0431d6
QT		 1871 switch (sp->cmd_type) {
1872 case TYPE_SRB:
c4e521b6 1873 qla2x00_abort_srb(qp, sp, res, &flags);
585def9b
QT		 1874 break;
1875 case TYPE_TGT_CMD:
bbead493
QT		 1876 if (!vha->hw->tgt.tgt_ops || !tgt ||
1877 qla_ini_mode_enabled(vha)) {
585def9b
QT		 1878 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1879 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1880 vha->dpc_flags);
bbead493 1881 continue;
c733ab35 1882 }
bbead493 1883 cmd = (struct qla_tgt_cmd *)sp;
aefed3e5 1884 cmd->aborted = 1;
585def9b
QT		 1885 break;
1886 case TYPE_TGT_TMCMD:
aefed3e5 1887 /* Skip task management functions. */
585def9b
QT		 1888 break;
1889 default:
1890 break;
73208dfd 1891 }
f45bca8c 1892 req->outstanding_cmds[cnt] = NULL;
df4bf0bb
AV		 1893 }
1894 }
bbead493
QT		 1895 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1896}
1897
c81ef0ed
BVA		 1898/*
1899 * The caller must ensure that no completion interrupts will happen
1900 * while this function is in progress.
1901 */
bbead493
QT		 1902void
1903qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1904{
1905 int que;
1906 struct qla_hw_data *ha = vha->hw;
1907
26a77799
AV		 1908 /* Continue only if initialization complete. */
1909 if (!ha->base_qpair)
1910 return;
bbead493
QT		 1911 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1912
26a77799
AV		 1913 if (!ha->queue_pair_map)
1914 return;
bbead493
QT		 1915 for (que = 0; que < ha->max_qpairs; que++) {
1916 if (!ha->queue_pair_map[que])
1917 continue;
1918
1919 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1920 }
df4bf0bb
AV		 1921}
1922
f4f051eb 1923static int
ed638918 1924qla2xxx_sdev_init(struct scsi_device *sdev)
1da177e4 1925{
bdf79621 1926 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1927
19a7b4ae 1928 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1929 return -ENXIO;
bdf79621 1930
19a7b4ae 1931 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1932
f4f051eb 1933 return 0;
1934}
1da177e4 1935
f4f051eb 1936static int
49515b7f 1937qla2xxx_sdev_configure(struct scsi_device *sdev, struct queue_limits *lim)
f4f051eb 1938{
e315cd28 1939 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1940 struct req_que *req = vha->req;
8482e118 1941
db5ed4df 1942 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1943 return 0;
1944}
1da177e4 1945
f4f051eb 1946static void
ed638918 1947qla2xxx_sdev_destroy(struct scsi_device *sdev)
f4f051eb 1948{
1949 sdev->hostdata = NULL;
1da177e4
LT		 1950}
1951
1952/**
1953 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1954 * @ha: HA context
1955 *
1956 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1957 * supported addressing method.
1958 */
1959static void
53303c42 1960qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1961{
7524f9b9 1962 /* Assume a 32bit DMA mask. */
1da177e4 1963 ha->flags.enable_64bit_addressing = 0;
1da177e4 1964
6a35528a 1965 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1966 /* Any upper-dword bits set? */
1967 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
8d1f1ffa 1968 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9 1969 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1970 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1971 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1972 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1973 return;
1da177e4 1974 }
1da177e4 1975 }
7524f9b9 1976
284901a9 1977 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
8d1f1ffa 1978 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1da177e4
LT		 1979}
1980
fd34f556 1981static void
e315cd28 1982qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1983{
1984 unsigned long flags = 0;
1985 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1986
1987 spin_lock_irqsave(&ha->hardware_lock, flags);
1988 ha->interrupts_on = 1;
1989 /* enable risc and host interrupts */
04474d3a
BVA		 1990 wrt_reg_word(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1991 rd_reg_word(&reg->ictrl);
fd34f556
AV		 1992 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1993
1994}
1995
1996static void
e315cd28 1997qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1998{
1999 unsigned long flags = 0;
2000 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2001
2002 spin_lock_irqsave(&ha->hardware_lock, flags);
2003 ha->interrupts_on = 0;
2004 /* disable risc and host interrupts */
04474d3a
BVA		 2005 wrt_reg_word(&reg->ictrl, 0);
2006 rd_reg_word(&reg->ictrl);
fd34f556
AV		 2007 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2008}
2009
2010static void
e315cd28 2011qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 2012{
2013 unsigned long flags = 0;
2014 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2015
2016 spin_lock_irqsave(&ha->hardware_lock, flags);
2017 ha->interrupts_on = 1;
04474d3a
BVA		 2018 wrt_reg_dword(&reg->ictrl, ICRX_EN_RISC_INT);
2019 rd_reg_dword(&reg->ictrl);
fd34f556
AV		 2020 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2021}
2022
2023static void
e315cd28 2024qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 2025{
2026 unsigned long flags = 0;
2027 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2028
124f85e6
AV		 2029 if (IS_NOPOLLING_TYPE(ha))
2030 return;
fd34f556
AV		 2031 spin_lock_irqsave(&ha->hardware_lock, flags);
2032 ha->interrupts_on = 0;
04474d3a
BVA		 2033 wrt_reg_dword(&reg->ictrl, 0);
2034 rd_reg_dword(&reg->ictrl);
fd34f556
AV		 2035 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2036}
2037
706f457d
GM		 2038static int
2039qla2x00_iospace_config(struct qla_hw_data *ha)
2040{
2041 resource_size_t pio;
2042 uint16_t msix;
706f457d 2043
706f457d
GM		 2044 if (pci_request_selected_regions(ha->pdev, ha->bars,
2045 QLA2XXX_DRIVER_NAME)) {
2046 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
2047 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2048 pci_name(ha->pdev));
2049 goto iospace_error_exit;
2050 }
2051 if (!(ha->bars & 1))
2052 goto skip_pio;
2053
2054 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
2055 pio = pci_resource_start(ha->pdev, 0);
2056 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
2057 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2058 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
2059 "Invalid pci I/O region size (%s).\n",
2060 pci_name(ha->pdev));
2061 pio = 0;
2062 }
2063 } else {
2064 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
2065 "Region #0 no a PIO resource (%s).\n",
2066 pci_name(ha->pdev));
2067 pio = 0;
2068 }
2069 ha->pio_address = pio;
2070 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2071 "PIO address=%llu.\n",
2072 (unsigned long long)ha->pio_address);
2073
2074skip_pio:
2075 /* Use MMIO operations for all accesses. */
2076 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2077 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2078 "Region #1 not an MMIO resource (%s), aborting.\n",
2079 pci_name(ha->pdev));
2080 goto iospace_error_exit;
2081 }
2082 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2083 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2084 "Invalid PCI mem region size (%s), aborting.\n",
2085 pci_name(ha->pdev));
2086 goto iospace_error_exit;
2087 }
2088
2089 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2090 if (!ha->iobase) {
2091 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2092 "Cannot remap MMIO (%s), aborting.\n",
2093 pci_name(ha->pdev));
2094 goto iospace_error_exit;
2095 }
2096
2097 /* Determine queue resources */
2098 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2099 ha->msix_count = QLA_BASE_VECTORS;
dffa1145
SK		 2100
2101 /* Check if FW supports MQ or not */
2102 if (!(ha->fw_attributes & BIT_6))
2103 goto mqiobase_exit;
2104
c38d1baf
HM		 2105 if (!ql2xmqsupport || !ql2xnvmeenable ||
2106 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 2107 goto mqiobase_exit;
2108
2109 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2110 pci_resource_len(ha->pdev, 3));
2111 if (ha->mqiobase) {
2112 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2113 "MQIO Base=%p.\n", ha->mqiobase);
2114 /* Read MSIX vector size of the board */
2115 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 2116 ha->msix_count = msix + 1;
706f457d 2117 /* Max queues are bounded by available msix vectors */
d7459527
MH		 2118 /* MB interrupt uses 1 vector */
2119 ha->max_req_queues = ha->msix_count - 1;
2120 ha->max_rsp_queues = ha->max_req_queues;
2121 /* Queue pairs is the max value minus the base queue pair */
2122 ha->max_qpairs = ha->max_rsp_queues - 1;
2123 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2124 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2125
706f457d 2126 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 2127 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 2128 } else
2129 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2130 "BAR 3 not enabled.\n");
2131
2132mqiobase_exit:
706f457d 2133 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 2134 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 2135 return (0);
2136
2137iospace_error_exit:
2138 return (-ENOMEM);
2139}
2140
2141
6246b8a1
GM		 2142static int
2143qla83xx_iospace_config(struct qla_hw_data *ha)
2144{
2145 uint16_t msix;
6246b8a1
GM		 2146
2147 if (pci_request_selected_regions(ha->pdev, ha->bars,
2148 QLA2XXX_DRIVER_NAME)) {
2149 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2150 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2151 pci_name(ha->pdev));
2152
2153 goto iospace_error_exit;
2154 }
2155
2156 /* Use MMIO operations for all accesses. */
2157 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2158 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2159 "Invalid pci I/O region size (%s).\n",
2160 pci_name(ha->pdev));
2161 goto iospace_error_exit;
2162 }
2163 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2164 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2165 "Invalid PCI mem region size (%s), aborting\n",
2166 pci_name(ha->pdev));
2167 goto iospace_error_exit;
2168 }
2169
2170 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2171 if (!ha->iobase) {
2172 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2173 "Cannot remap MMIO (%s), aborting.\n",
2174 pci_name(ha->pdev));
2175 goto iospace_error_exit;
2176 }
2177
2178 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2179 /* 83XX 26XX always use MQ type access for queues
2180 * - mbar 2, a.k.a region 4 */
2181 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2182 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2183 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2184 pci_resource_len(ha->pdev, 4));
2185
2186 if (!ha->mqiobase) {
2187 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2188 "BAR2/region4 not enabled\n");
2189 goto mqiobase_exit;
2190 }
2191
2192 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2193 pci_resource_len(ha->pdev, 2));
2194 if (ha->msixbase) {
2195 /* Read MSIX vector size of the board */
2196 pci_read_config_word(ha->pdev,
2197 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2198 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2199 /*
2200 * By default, driver uses at least two msix vectors
2201 * (default & rspq)
2202 */
c38d1baf 2203 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 2204 /* MB interrupt uses 1 vector */
2205 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2206
2207 /* ATIOQ needs 1 vector. That's 1 less QPair */
2208 if (QLA_TGT_MODE_ENABLED())
2209 ha->max_req_queues--;
2210
d0d2c68b
MH		 2211 ha->max_rsp_queues = ha->max_req_queues;
2212
d7459527
MH		 2213 /* Queue pairs is the max value minus
2214 * the base queue pair */
2215 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2216 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2217 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2218 }
2219 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2220 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2221 } else
2222 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2223 "BAR 1 not enabled.\n");
2224
2225mqiobase_exit:
6246b8a1 2226 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2227 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2228 return 0;
2229
2230iospace_error_exit:
2231 return -ENOMEM;
2232}
2233
fd34f556
AV		 2234static struct isp_operations qla2100_isp_ops = {
2235 .pci_config = qla2100_pci_config,
2236 .reset_chip = qla2x00_reset_chip,
2237 .chip_diag = qla2x00_chip_diag,
2238 .config_rings = qla2x00_config_rings,
2239 .reset_adapter = qla2x00_reset_adapter,
2240 .nvram_config = qla2x00_nvram_config,
2241 .update_fw_options = qla2x00_update_fw_options,
2242 .load_risc = qla2x00_load_risc,
2243 .pci_info_str = qla2x00_pci_info_str,
2244 .fw_version_str = qla2x00_fw_version_str,
2245 .intr_handler = qla2100_intr_handler,
2246 .enable_intrs = qla2x00_enable_intrs,
2247 .disable_intrs = qla2x00_disable_intrs,
2248 .abort_command = qla2x00_abort_command,
523ec773
AV		 2249 .target_reset = qla2x00_abort_target,
2250 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2251 .fabric_login = qla2x00_login_fabric,
2252 .fabric_logout = qla2x00_fabric_logout,
2253 .calc_req_entries = qla2x00_calc_iocbs_32,
2254 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2255 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2256 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2257 .read_nvram = qla2x00_read_nvram_data,
2258 .write_nvram = qla2x00_write_nvram_data,
2259 .fw_dump = qla2100_fw_dump,
2260 .beacon_on = NULL,
2261 .beacon_off = NULL,
2262 .beacon_blink = NULL,
2263 .read_optrom = qla2x00_read_optrom_data,
2264 .write_optrom = qla2x00_write_optrom_data,
2265 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2266 .start_scsi = qla2x00_start_scsi,
d7459527 2267 .start_scsi_mq = NULL,
a9083016 2268 .abort_isp = qla2x00_abort_isp,
706f457d 2269 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2270 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2271};
2272
2273static struct isp_operations qla2300_isp_ops = {
2274 .pci_config = qla2300_pci_config,
2275 .reset_chip = qla2x00_reset_chip,
2276 .chip_diag = qla2x00_chip_diag,
2277 .config_rings = qla2x00_config_rings,
2278 .reset_adapter = qla2x00_reset_adapter,
2279 .nvram_config = qla2x00_nvram_config,
2280 .update_fw_options = qla2x00_update_fw_options,
2281 .load_risc = qla2x00_load_risc,
2282 .pci_info_str = qla2x00_pci_info_str,
2283 .fw_version_str = qla2x00_fw_version_str,
2284 .intr_handler = qla2300_intr_handler,
2285 .enable_intrs = qla2x00_enable_intrs,
2286 .disable_intrs = qla2x00_disable_intrs,
2287 .abort_command = qla2x00_abort_command,
523ec773
AV		 2288 .target_reset = qla2x00_abort_target,
2289 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2290 .fabric_login = qla2x00_login_fabric,
2291 .fabric_logout = qla2x00_fabric_logout,
2292 .calc_req_entries = qla2x00_calc_iocbs_32,
2293 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2294 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2295 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2296 .read_nvram = qla2x00_read_nvram_data,
2297 .write_nvram = qla2x00_write_nvram_data,
2298 .fw_dump = qla2300_fw_dump,
2299 .beacon_on = qla2x00_beacon_on,
2300 .beacon_off = qla2x00_beacon_off,
2301 .beacon_blink = qla2x00_beacon_blink,
2302 .read_optrom = qla2x00_read_optrom_data,
2303 .write_optrom = qla2x00_write_optrom_data,
2304 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2305 .start_scsi = qla2x00_start_scsi,
d7459527 2306 .start_scsi_mq = NULL,
a9083016 2307 .abort_isp = qla2x00_abort_isp,
7ec0effd 2308 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2309 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2310};
2311
2312static struct isp_operations qla24xx_isp_ops = {
2313 .pci_config = qla24xx_pci_config,
2314 .reset_chip = qla24xx_reset_chip,
2315 .chip_diag = qla24xx_chip_diag,
2316 .config_rings = qla24xx_config_rings,
2317 .reset_adapter = qla24xx_reset_adapter,
2318 .nvram_config = qla24xx_nvram_config,
2319 .update_fw_options = qla24xx_update_fw_options,
2320 .load_risc = qla24xx_load_risc,
2321 .pci_info_str = qla24xx_pci_info_str,
2322 .fw_version_str = qla24xx_fw_version_str,
2323 .intr_handler = qla24xx_intr_handler,
2324 .enable_intrs = qla24xx_enable_intrs,
2325 .disable_intrs = qla24xx_disable_intrs,
2326 .abort_command = qla24xx_abort_command,
523ec773
AV		 2327 .target_reset = qla24xx_abort_target,
2328 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2329 .fabric_login = qla24xx_login_fabric,
2330 .fabric_logout = qla24xx_fabric_logout,
2331 .calc_req_entries = NULL,
2332 .build_iocbs = NULL,
2333 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2334 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2335 .read_nvram = qla24xx_read_nvram_data,
2336 .write_nvram = qla24xx_write_nvram_data,
2337 .fw_dump = qla24xx_fw_dump,
2338 .beacon_on = qla24xx_beacon_on,
2339 .beacon_off = qla24xx_beacon_off,
2340 .beacon_blink = qla24xx_beacon_blink,
2341 .read_optrom = qla24xx_read_optrom_data,
2342 .write_optrom = qla24xx_write_optrom_data,
2343 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2344 .start_scsi = qla24xx_start_scsi,
d7459527 2345 .start_scsi_mq = NULL,
a9083016 2346 .abort_isp = qla2x00_abort_isp,
7ec0effd 2347 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2348 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2349};
2350
c3a2f0df
AV		 2351static struct isp_operations qla25xx_isp_ops = {
2352 .pci_config = qla25xx_pci_config,
2353 .reset_chip = qla24xx_reset_chip,
2354 .chip_diag = qla24xx_chip_diag,
2355 .config_rings = qla24xx_config_rings,
2356 .reset_adapter = qla24xx_reset_adapter,
2357 .nvram_config = qla24xx_nvram_config,
2358 .update_fw_options = qla24xx_update_fw_options,
2359 .load_risc = qla24xx_load_risc,
2360 .pci_info_str = qla24xx_pci_info_str,
2361 .fw_version_str = qla24xx_fw_version_str,
2362 .intr_handler = qla24xx_intr_handler,
2363 .enable_intrs = qla24xx_enable_intrs,
2364 .disable_intrs = qla24xx_disable_intrs,
2365 .abort_command = qla24xx_abort_command,
523ec773
AV		 2366 .target_reset = qla24xx_abort_target,
2367 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2368 .fabric_login = qla24xx_login_fabric,
2369 .fabric_logout = qla24xx_fabric_logout,
2370 .calc_req_entries = NULL,
2371 .build_iocbs = NULL,
2372 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2373 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2374 .read_nvram = qla25xx_read_nvram_data,
2375 .write_nvram = qla25xx_write_nvram_data,
2376 .fw_dump = qla25xx_fw_dump,
2377 .beacon_on = qla24xx_beacon_on,
2378 .beacon_off = qla24xx_beacon_off,
2379 .beacon_blink = qla24xx_beacon_blink,
338c9161 2380 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2381 .write_optrom = qla24xx_write_optrom_data,
2382 .get_flash_version = qla24xx_get_flash_version,
bad75002 2383 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2384 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2385 .abort_isp = qla2x00_abort_isp,
7ec0effd 2386 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2387 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2388};
2389
3a03eb79
AV		 2390static struct isp_operations qla81xx_isp_ops = {
2391 .pci_config = qla25xx_pci_config,
2392 .reset_chip = qla24xx_reset_chip,
2393 .chip_diag = qla24xx_chip_diag,
2394 .config_rings = qla24xx_config_rings,
2395 .reset_adapter = qla24xx_reset_adapter,
2396 .nvram_config = qla81xx_nvram_config,
37efd51f 2397 .update_fw_options = qla24xx_update_fw_options,
eaac30be 2398 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2399 .pci_info_str = qla24xx_pci_info_str,
2400 .fw_version_str = qla24xx_fw_version_str,
2401 .intr_handler = qla24xx_intr_handler,
2402 .enable_intrs = qla24xx_enable_intrs,
2403 .disable_intrs = qla24xx_disable_intrs,
2404 .abort_command = qla24xx_abort_command,
2405 .target_reset = qla24xx_abort_target,
2406 .lun_reset = qla24xx_lun_reset,
2407 .fabric_login = qla24xx_login_fabric,
2408 .fabric_logout = qla24xx_fabric_logout,
2409 .calc_req_entries = NULL,
2410 .build_iocbs = NULL,
2411 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2412 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2413 .read_nvram = NULL,
2414 .write_nvram = NULL,
3a03eb79
AV		 2415 .fw_dump = qla81xx_fw_dump,
2416 .beacon_on = qla24xx_beacon_on,
2417 .beacon_off = qla24xx_beacon_off,
6246b8a1 2418 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2419 .read_optrom = qla25xx_read_optrom_data,
2420 .write_optrom = qla24xx_write_optrom_data,
2421 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2422 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2423 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2424 .abort_isp = qla2x00_abort_isp,
7ec0effd 2425 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2426 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2427};
2428
2429static struct isp_operations qla82xx_isp_ops = {
2430 .pci_config = qla82xx_pci_config,
2431 .reset_chip = qla82xx_reset_chip,
2432 .chip_diag = qla24xx_chip_diag,
2433 .config_rings = qla82xx_config_rings,
2434 .reset_adapter = qla24xx_reset_adapter,
2435 .nvram_config = qla81xx_nvram_config,
2436 .update_fw_options = qla24xx_update_fw_options,
2437 .load_risc = qla82xx_load_risc,
9d55ca66 2438 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2439 .fw_version_str = qla24xx_fw_version_str,
2440 .intr_handler = qla82xx_intr_handler,
2441 .enable_intrs = qla82xx_enable_intrs,
2442 .disable_intrs = qla82xx_disable_intrs,
2443 .abort_command = qla24xx_abort_command,
2444 .target_reset = qla24xx_abort_target,
2445 .lun_reset = qla24xx_lun_reset,
2446 .fabric_login = qla24xx_login_fabric,
2447 .fabric_logout = qla24xx_fabric_logout,
2448 .calc_req_entries = NULL,
2449 .build_iocbs = NULL,
2450 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2451 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2452 .read_nvram = qla24xx_read_nvram_data,
2453 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2454 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2455 .beacon_on = qla82xx_beacon_on,
2456 .beacon_off = qla82xx_beacon_off,
2457 .beacon_blink = NULL,
a9083016
GM		 2458 .read_optrom = qla82xx_read_optrom_data,
2459 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2460 .get_flash_version = qla82xx_get_flash_version,
a9083016 2461 .start_scsi = qla82xx_start_scsi,
d7459527 2462 .start_scsi_mq = NULL,
a9083016 2463 .abort_isp = qla82xx_abort_isp,
706f457d 2464 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2465 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2466};
2467
7ec0effd
AD		 2468static struct isp_operations qla8044_isp_ops = {
2469 .pci_config = qla82xx_pci_config,
2470 .reset_chip = qla82xx_reset_chip,
2471 .chip_diag = qla24xx_chip_diag,
2472 .config_rings = qla82xx_config_rings,
2473 .reset_adapter = qla24xx_reset_adapter,
2474 .nvram_config = qla81xx_nvram_config,
2475 .update_fw_options = qla24xx_update_fw_options,
2476 .load_risc = qla82xx_load_risc,
2477 .pci_info_str = qla24xx_pci_info_str,
2478 .fw_version_str = qla24xx_fw_version_str,
2479 .intr_handler = qla8044_intr_handler,
2480 .enable_intrs = qla82xx_enable_intrs,
2481 .disable_intrs = qla82xx_disable_intrs,
2482 .abort_command = qla24xx_abort_command,
2483 .target_reset = qla24xx_abort_target,
2484 .lun_reset = qla24xx_lun_reset,
2485 .fabric_login = qla24xx_login_fabric,
2486 .fabric_logout = qla24xx_fabric_logout,
2487 .calc_req_entries = NULL,
2488 .build_iocbs = NULL,
2489 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2490 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2491 .read_nvram = NULL,
2492 .write_nvram = NULL,
a1b23c5a 2493 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2494 .beacon_on = qla82xx_beacon_on,
2495 .beacon_off = qla82xx_beacon_off,
2496 .beacon_blink = NULL,
888e639d 2497 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2498 .write_optrom = qla8044_write_optrom_data,
2499 .get_flash_version = qla82xx_get_flash_version,
2500 .start_scsi = qla82xx_start_scsi,
d7459527 2501 .start_scsi_mq = NULL,
7ec0effd
AD		 2502 .abort_isp = qla8044_abort_isp,
2503 .iospace_config = qla82xx_iospace_config,
2504 .initialize_adapter = qla2x00_initialize_adapter,
2505};
2506
6246b8a1
GM		 2507static struct isp_operations qla83xx_isp_ops = {
2508 .pci_config = qla25xx_pci_config,
2509 .reset_chip = qla24xx_reset_chip,
2510 .chip_diag = qla24xx_chip_diag,
2511 .config_rings = qla24xx_config_rings,
2512 .reset_adapter = qla24xx_reset_adapter,
2513 .nvram_config = qla81xx_nvram_config,
37efd51f 2514 .update_fw_options = qla24xx_update_fw_options,
6246b8a1
GM		 2515 .load_risc = qla81xx_load_risc,
2516 .pci_info_str = qla24xx_pci_info_str,
2517 .fw_version_str = qla24xx_fw_version_str,
2518 .intr_handler = qla24xx_intr_handler,
2519 .enable_intrs = qla24xx_enable_intrs,
2520 .disable_intrs = qla24xx_disable_intrs,
2521 .abort_command = qla24xx_abort_command,
2522 .target_reset = qla24xx_abort_target,
2523 .lun_reset = qla24xx_lun_reset,
2524 .fabric_login = qla24xx_login_fabric,
2525 .fabric_logout = qla24xx_fabric_logout,
2526 .calc_req_entries = NULL,
2527 .build_iocbs = NULL,
2528 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2529 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2530 .read_nvram = NULL,
2531 .write_nvram = NULL,
2532 .fw_dump = qla83xx_fw_dump,
2533 .beacon_on = qla24xx_beacon_on,
2534 .beacon_off = qla24xx_beacon_off,
2535 .beacon_blink = qla83xx_beacon_blink,
2536 .read_optrom = qla25xx_read_optrom_data,
2537 .write_optrom = qla24xx_write_optrom_data,
2538 .get_flash_version = qla24xx_get_flash_version,
2539 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2540 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2541 .abort_isp = qla2x00_abort_isp,
2542 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2543 .initialize_adapter = qla2x00_initialize_adapter,
2544};
2545
2546static struct isp_operations qlafx00_isp_ops = {
2547 .pci_config = qlafx00_pci_config,
2548 .reset_chip = qlafx00_soft_reset,
2549 .chip_diag = qlafx00_chip_diag,
2550 .config_rings = qlafx00_config_rings,
2551 .reset_adapter = qlafx00_soft_reset,
2552 .nvram_config = NULL,
2553 .update_fw_options = NULL,
2554 .load_risc = NULL,
2555 .pci_info_str = qlafx00_pci_info_str,
2556 .fw_version_str = qlafx00_fw_version_str,
2557 .intr_handler = qlafx00_intr_handler,
2558 .enable_intrs = qlafx00_enable_intrs,
2559 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2560 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2561 .target_reset = qlafx00_abort_target,
2562 .lun_reset = qlafx00_lun_reset,
2563 .fabric_login = NULL,
2564 .fabric_logout = NULL,
2565 .calc_req_entries = NULL,
2566 .build_iocbs = NULL,
2567 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2568 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2569 .read_nvram = qla24xx_read_nvram_data,
2570 .write_nvram = qla24xx_write_nvram_data,
2571 .fw_dump = NULL,
2572 .beacon_on = qla24xx_beacon_on,
2573 .beacon_off = qla24xx_beacon_off,
2574 .beacon_blink = NULL,
2575 .read_optrom = qla24xx_read_optrom_data,
2576 .write_optrom = qla24xx_write_optrom_data,
2577 .get_flash_version = qla24xx_get_flash_version,
2578 .start_scsi = qlafx00_start_scsi,
d7459527 2579 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2580 .abort_isp = qlafx00_abort_isp,
2581 .iospace_config = qlafx00_iospace_config,
2582 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2583};
2584
f73cb695
CD		 2585static struct isp_operations qla27xx_isp_ops = {
2586 .pci_config = qla25xx_pci_config,
2587 .reset_chip = qla24xx_reset_chip,
2588 .chip_diag = qla24xx_chip_diag,
2589 .config_rings = qla24xx_config_rings,
2590 .reset_adapter = qla24xx_reset_adapter,
2591 .nvram_config = qla81xx_nvram_config,
a36f1443 2592 .update_fw_options = qla24xx_update_fw_options,
f73cb695
CD		 2593 .load_risc = qla81xx_load_risc,
2594 .pci_info_str = qla24xx_pci_info_str,
2595 .fw_version_str = qla24xx_fw_version_str,
2596 .intr_handler = qla24xx_intr_handler,
2597 .enable_intrs = qla24xx_enable_intrs,
2598 .disable_intrs = qla24xx_disable_intrs,
2599 .abort_command = qla24xx_abort_command,
2600 .target_reset = qla24xx_abort_target,
2601 .lun_reset = qla24xx_lun_reset,
2602 .fabric_login = qla24xx_login_fabric,
2603 .fabric_logout = qla24xx_fabric_logout,
2604 .calc_req_entries = NULL,
2605 .build_iocbs = NULL,
2606 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2607 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2608 .read_nvram = NULL,
2609 .write_nvram = NULL,
2610 .fw_dump = qla27xx_fwdump,
cbb01c2f 2611 .mpi_fw_dump = qla27xx_mpi_fwdump,
f73cb695
CD		 2612 .beacon_on = qla24xx_beacon_on,
2613 .beacon_off = qla24xx_beacon_off,
2614 .beacon_blink = qla83xx_beacon_blink,
2615 .read_optrom = qla25xx_read_optrom_data,
2616 .write_optrom = qla24xx_write_optrom_data,
2617 .get_flash_version = qla24xx_get_flash_version,
2618 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2619 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2620 .abort_isp = qla2x00_abort_isp,
2621 .iospace_config = qla83xx_iospace_config,
2622 .initialize_adapter = qla2x00_initialize_adapter,
2623};
2624
ea5b6382 2625static inline void
e315cd28 2626qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2627{
2628 ha->device_type = DT_EXTENDED_IDS;
2629 switch (ha->pdev->device) {
2630 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2631 ha->isp_type |= DT_ISP2100;
ea5b6382 2632 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2633 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2634 break;
2635 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2636 ha->isp_type |= DT_ISP2200;
ea5b6382 2637 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2638 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2639 break;
2640 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2641 ha->isp_type |= DT_ISP2300;
4a59f71d 2642 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2643 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2644 break;
2645 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2646 ha->isp_type |= DT_ISP2312;
4a59f71d 2647 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2648 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2649 break;
2650 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2651 ha->isp_type |= DT_ISP2322;
4a59f71d 2652 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2653 if (ha->pdev->subsystem_vendor == 0x1028 &&
2654 ha->pdev->subsystem_device == 0x0170)
2655 ha->device_type |= DT_OEM_001;
441d1072 2656 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2657 break;
2658 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2659 ha->isp_type |= DT_ISP6312;
441d1072 2660 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2661 break;
2662 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2663 ha->isp_type |= DT_ISP6322;
441d1072 2664 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2665 break;
2666 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2667 ha->isp_type |= DT_ISP2422;
4a59f71d 2668 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2669 ha->device_type |= DT_FWI2;
c76f2c01 2670 ha->device_type |= DT_IIDMA;
441d1072 2671 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2672 break;
2673 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2674 ha->isp_type |= DT_ISP2432;
4a59f71d 2675 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2676 ha->device_type |= DT_FWI2;
c76f2c01 2677 ha->device_type |= DT_IIDMA;
441d1072 2678 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2679 break;
4d4df193 2680 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2681 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2682 ha->device_type |= DT_ZIO_SUPPORTED;
2683 ha->device_type |= DT_FWI2;
2684 ha->device_type |= DT_IIDMA;
2685 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2686 break;
044cc6c8 2687 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2688 ha->isp_type |= DT_ISP5422;
e428924c 2689 ha->device_type |= DT_FWI2;
441d1072 2690 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2691 break;
044cc6c8 2692 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2693 ha->isp_type |= DT_ISP5432;
e428924c 2694 ha->device_type |= DT_FWI2;
441d1072 2695 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2696 break;
c3a2f0df 2697 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2698 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2699 ha->device_type |= DT_ZIO_SUPPORTED;
2700 ha->device_type |= DT_FWI2;
2701 ha->device_type |= DT_IIDMA;
441d1072 2702 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2703 break;
3a03eb79 2704 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2705 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2706 ha->device_type |= DT_ZIO_SUPPORTED;
2707 ha->device_type |= DT_FWI2;
2708 ha->device_type |= DT_IIDMA;
2709 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2710 break;
a9083016 2711 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2712 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2713 ha->device_type |= DT_ZIO_SUPPORTED;
2714 ha->device_type |= DT_FWI2;
2715 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2716 /* Initialize 82XX ISP flags */
2717 qla82xx_init_flags(ha);
2718 break;
7ec0effd 2719 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2720 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2721 ha->device_type |= DT_ZIO_SUPPORTED;
2722 ha->device_type |= DT_FWI2;
2723 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2724 /* Initialize 82XX ISP flags */
2725 qla82xx_init_flags(ha);
2726 break;
6246b8a1 2727 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2728 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2729 ha->device_type |= DT_ZIO_SUPPORTED;
2730 ha->device_type |= DT_FWI2;
2731 ha->device_type |= DT_IIDMA;
2732 ha->device_type |= DT_T10_PI;
2733 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2734 break;
2735 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2736 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2737 ha->device_type |= DT_ZIO_SUPPORTED;
2738 ha->device_type |= DT_FWI2;
2739 ha->device_type |= DT_IIDMA;
2740 ha->device_type |= DT_T10_PI;
2741 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2742 break;
8ae6d9c7 2743 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2744 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2745 break;
f73cb695 2746 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2747 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2748 ha->device_type |= DT_ZIO_SUPPORTED;
2749 ha->device_type |= DT_FWI2;
2750 ha->device_type |= DT_IIDMA;
8ce3f570 2751 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2752 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2753 break;
2c5bbbb2 2754 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2755 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2756 ha->device_type |= DT_ZIO_SUPPORTED;
2757 ha->device_type |= DT_FWI2;
2758 ha->device_type |= DT_IIDMA;
8ce3f570 2759 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2760 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2761 break;
2b48992f 2762 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2763 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2764 ha->device_type |= DT_ZIO_SUPPORTED;
2765 ha->device_type |= DT_FWI2;
2766 ha->device_type |= DT_IIDMA;
8ce3f570 2767 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2768 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2769 break;
ecc89f25
JC		 2770 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2771 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2772 ha->isp_type |= DT_ISP2081;
2773 ha->device_type |= DT_ZIO_SUPPORTED;
2774 ha->device_type |= DT_FWI2;
2775 ha->device_type |= DT_IIDMA;
2776 ha->device_type |= DT_T10_PI;
2777 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2778 break;
2779 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2780 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2781 ha->isp_type |= DT_ISP2281;
2782 ha->device_type |= DT_ZIO_SUPPORTED;
2783 ha->device_type |= DT_FWI2;
2784 ha->device_type |= DT_IIDMA;
2785 ha->device_type |= DT_T10_PI;
2786 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2787 break;
ea5b6382 2788 }
e5b68a61 2789
a9083016 2790 if (IS_QLA82XX(ha))
43a9c38b 2791 ha->port_no = ha->portnum & 1;
f73cb695 2792 else {
a9083016
GM		 2793 /* Get adapter physical port no from interrupt pin register. */
2794 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
ecc89f25
JC		 2795 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2796 IS_QLA27XX(ha) || IS_QLA28XX(ha))
f73cb695
CD		 2797 ha->port_no--;
2798 else
2799 ha->port_no = !(ha->port_no & 1);
2800 }
a9083016 2801
7c3df132 2802 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2803 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2804 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2805}
2806
1e99e33a
AV		 2807static void
2808qla2xxx_scan_start(struct Scsi_Host *shost)
2809{
e315cd28 2810 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2811
cbc8eb67
AV		 2812 if (vha->hw->flags.running_gold_fw)
2813 return;
2814
e315cd28
AC		 2815 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2816 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2817 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2818 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2819}
2820
2821static int
2822qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2823{
e315cd28 2824 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2825
a5dd506e
BK		 2826 if (test_bit(UNLOADING, &vha->dpc_flags))
2827 return 1;
e315cd28 2828 if (!vha->host)
1e99e33a 2829 return 1;
e315cd28 2830 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2831 return 1;
2832
e315cd28 2833 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2834}
2835
3a4e1f3b
MR		 2836static void qla_heartbeat_work_fn(struct work_struct *work)
2837{
2838 struct qla_hw_data *ha = container_of(work,
2839 struct qla_hw_data, heartbeat_work);
2840 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2841
2842 if (!ha->flags.mbox_busy && base_vha->flags.init_done)
2843 qla_no_op_mb(base_vha);
2844}
2845
ec7193e2
QT		 2846static void qla2x00_iocb_work_fn(struct work_struct *work)
2847{
2848 struct scsi_qla_host *vha = container_of(work,
2849 struct scsi_qla_host, iocb_work);
9b3e0f4d
QT		 2850 struct qla_hw_data *ha = vha->hw;
2851 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
0aca7784 2852 int i = 2;
9b3e0f4d
QT		 2853 unsigned long flags;
2854
2855 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2856 return;
ec7193e2 2857
9b3e0f4d 2858 while (!list_empty(&vha->work_list) && i > 0) {
ec7193e2 2859 qla2x00_do_work(vha);
9b3e0f4d 2860 i--;
ec7193e2 2861 }
9b3e0f4d
QT		 2862
2863 spin_lock_irqsave(&vha->work_lock, flags);
2864 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2865 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 2866}
2867
8bfc149b
AE		 2868static void
2869qla_trace_init(void)
2870{
d2356997 2871 qla_trc_array = trace_array_get_by_name("qla2xxx", NULL);
8bfc149b
AE		 2872 if (!qla_trc_array) {
2873 ql_log(ql_log_fatal, NULL, 0x0001,
2874 "Unable to create qla2xxx trace instance, instance logging will be disabled.\n");
2875 return;
2876 }
2877
2878 QLA_TRACE_ENABLE(qla_trc_array);
2879}
2880
2881static void
2882qla_trace_uninit(void)
2883{
2884 if (!qla_trc_array)
2885 return;
2886 trace_array_put(qla_trc_array);
2887}
2888
1da177e4
LT		 2889/*
2890 * PCI driver interface
2891 */
6f039790 2892static int
7ee61397 2893qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2894{
a1541d5a 2895 int ret = -ENODEV;
1da177e4 2896 struct Scsi_Host *host;
e315cd28
AC		 2897 scsi_qla_host_t *base_vha = NULL;
2898 struct qla_hw_data *ha;
29856e28 2899 char pci_info[30];
7d613ac6 2900 char fw_str[30], wq_name[30];
5433383e 2901 struct scsi_host_template *sht;
642ef983 2902 int bars, mem_only = 0;
e315cd28 2903 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2904 struct req_que *req = NULL;
2905 struct rsp_que *rsp = NULL;
5601236b 2906 int i;
d7459527 2907
285d0321 2908 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2909 sht = &qla2xxx_driver_template;
5433383e 2910 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2911 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2912 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2913 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2914 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2915 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2916 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2917 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2918 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2919 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2920 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2921 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2922 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f 2923 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
ecc89f25
JC		 2924 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2925 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2926 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2927 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2928 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
285d0321 2929 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2930 mem_only = 1;
7c3df132
SK		 2931 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2932 "Mem only adapter.\n");
285d0321 2933 }
7c3df132
SK		 2934 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2935 "Bars=%d.\n", bars);
285d0321 2936
09483916
BH		 2937 if (mem_only) {
2938 if (pci_enable_device_mem(pdev))
ddff7ed4 2939 return ret;
09483916
BH		 2940 } else {
2941 if (pci_enable_device(pdev))
ddff7ed4 2942 return ret;
09483916 2943 }
285d0321 2944
62e0dec5
SK		 2945 if (is_kdump_kernel()) {
2946 ql2xmqsupport = 0;
2947 ql2xallocfwdump = 0;
2948 }
2949
e315cd28
AC		 2950 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2951 if (!ha) {
7c3df132
SK		 2952 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2953 "Unable to allocate memory for ha.\n");
ddff7ed4 2954 goto disable_device;
1da177e4 2955 }
7c3df132
SK		 2956 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2957 "Memory allocated for ha=%p.\n", ha);
e315cd28 2958 ha->pdev = pdev;
33e79977
QT		 2959 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2960 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2961 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2962 spin_lock_init(&ha->tgt.atio_lock);
2963
dd30706e
QT		 2964 spin_lock_init(&ha->sadb_lock);
2965 INIT_LIST_HEAD(&ha->sadb_tx_index_list);
2966 INIT_LIST_HEAD(&ha->sadb_rx_index_list);
2967
2968 spin_lock_init(&ha->sadb_fp_lock);
2969
2970 if (qla_edif_sadb_build_free_pool(ha)) {
2971 kfree(ha);
2972 goto disable_device;
2973 }
2974
deeae7a6 2975 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2976
2977 /* Clear our data area */
285d0321 2978 ha->bars = bars;
09483916 2979 ha->mem_only = mem_only;
df4bf0bb 2980 spin_lock_init(&ha->hardware_lock);
339aa70e 2981 spin_lock_init(&ha->vport_slock);
a9b6f722 2982 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2983 mutex_init(&ha->optrom_mutex);
1da177e4 2984
ea5b6382 2985 /* Set ISP-type information. */
2986 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2987
2988 /* Set EEH reset type to fundamental if required by hba */
95676112 2989 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
ecc89f25 2990 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
ca79cf66 2991 pdev->needs_freset = 1;
ca79cf66 2992
cba1e47f
CD		 2993 ha->prev_topology = 0;
2994 ha->init_cb_size = sizeof(init_cb_t);
2995 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2996 ha->optrom_size = OPTROM_SIZE_2300;
d1e3635a 2997 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
b2000805
QT		 2998 atomic_set(&ha->num_pend_mbx_stage1, 0);
2999 atomic_set(&ha->num_pend_mbx_stage2, 0);
8b4673ba
QT		 3000 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
3001 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
a8ec1924
QT		 3002 INIT_LIST_HEAD(&ha->tmf_pending);
3003 INIT_LIST_HEAD(&ha->tmf_active);
cba1e47f 3004
abbd8870 3005 /* Assign ISP specific operations. */
1da177e4 3006 if (IS_QLA2100(ha)) {
642ef983 3007 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 3008 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 3009 req_length = REQUEST_ENTRY_CNT_2100;
3010 rsp_length = RESPONSE_ENTRY_CNT_2100;
3011 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 3012 ha->gid_list_info_size = 4;
3a03eb79
AV		 3013 ha->flash_conf_off = ~0;
3014 ha->flash_data_off = ~0;
3015 ha->nvram_conf_off = ~0;
3016 ha->nvram_data_off = ~0;
fd34f556 3017 ha->isp_ops = &qla2100_isp_ops;
1da177e4 3018 } else if (IS_QLA2200(ha)) {
642ef983 3019 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 3020 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 3021 req_length = REQUEST_ENTRY_CNT_2200;
3022 rsp_length = RESPONSE_ENTRY_CNT_2100;
3023 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 3024 ha->gid_list_info_size = 4;
3a03eb79
AV		 3025 ha->flash_conf_off = ~0;
3026 ha->flash_data_off = ~0;
3027 ha->nvram_conf_off = ~0;
3028 ha->nvram_data_off = ~0;
fd34f556 3029 ha->isp_ops = &qla2100_isp_ops;
fca29703 3030 } else if (IS_QLA23XX(ha)) {
642ef983 3031 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 3032 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 3033 req_length = REQUEST_ENTRY_CNT_2200;
3034 rsp_length = RESPONSE_ENTRY_CNT_2300;
3035 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 3036 ha->gid_list_info_size = 6;
854165f4 3037 if (IS_QLA2322(ha) || IS_QLA6322(ha))
3038 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 3039 ha->flash_conf_off = ~0;
3040 ha->flash_data_off = ~0;
3041 ha->nvram_conf_off = ~0;
3042 ha->nvram_data_off = ~0;
fd34f556 3043 ha->isp_ops = &qla2300_isp_ops;
4d4df193 3044 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 3045 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 3046 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 3047 req_length = REQUEST_ENTRY_CNT_24XX;
3048 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 3049 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 3050 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 3051 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 3052 ha->gid_list_info_size = 8;
854165f4 3053 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 3054 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 3055 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 3056 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3057 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3058 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3059 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 3060 } else if (IS_QLA25XX(ha)) {
642ef983 3061 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 3062 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 3063 req_length = REQUEST_ENTRY_CNT_24XX;
3064 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 3065 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 3066 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 3067 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 3068 ha->gid_list_info_size = 8;
3069 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 3070 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 3071 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 3072 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3073 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3074 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3075 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3076 } else if (IS_QLA81XX(ha)) {
642ef983 3077 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 3078 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3079 req_length = REQUEST_ENTRY_CNT_24XX;
3080 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 3081 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 3082 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3083 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3084 ha->gid_list_info_size = 8;
3085 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 3086 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 3087 ha->isp_ops = &qla81xx_isp_ops;
3088 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3089 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3090 ha->nvram_conf_off = ~0;
3091 ha->nvram_data_off = ~0;
a9083016 3092 } else if (IS_QLA82XX(ha)) {
642ef983 3093 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 3094 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3095 req_length = REQUEST_ENTRY_CNT_82XX;
3096 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3097 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3098 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3099 ha->gid_list_info_size = 8;
3100 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 3101 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 3102 ha->isp_ops = &qla82xx_isp_ops;
3103 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3104 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3105 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3106 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 3107 } else if (IS_QLA8044(ha)) {
3108 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3109 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3110 req_length = REQUEST_ENTRY_CNT_82XX;
3111 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3112 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3113 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3114 ha->gid_list_info_size = 8;
3115 ha->optrom_size = OPTROM_SIZE_83XX;
3116 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3117 ha->isp_ops = &qla8044_isp_ops;
3118 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3119 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3120 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3121 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 3122 } else if (IS_QLA83XX(ha)) {
7d613ac6 3123 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 3124 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 3125 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 3126 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 3127 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 3128 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 3129 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3130 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3131 ha->gid_list_info_size = 8;
3132 ha->optrom_size = OPTROM_SIZE_83XX;
3133 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3134 ha->isp_ops = &qla83xx_isp_ops;
3135 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3136 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3137 ha->nvram_conf_off = ~0;
3138 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 3139 } else if (IS_QLAFX00(ha)) {
3140 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3141 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3142 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3143 req_length = REQUEST_ENTRY_CNT_FX00;
3144 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 3145 ha->isp_ops = &qlafx00_isp_ops;
3146 ha->port_down_retry_count = 30; /* default value */
3147 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3148 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 3149 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 3150 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 3151 ha->mr.host_info_resend = false;
3152 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 3153 } else if (IS_QLA27XX(ha)) {
3154 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3155 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3156 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 3157 req_length = REQUEST_ENTRY_CNT_83XX;
3158 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 3159 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 3160 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3161 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3162 ha->gid_list_info_size = 8;
3163 ha->optrom_size = OPTROM_SIZE_83XX;
3164 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3165 ha->isp_ops = &qla27xx_isp_ops;
3166 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3167 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3168 ha->nvram_conf_off = ~0;
3169 ha->nvram_data_off = ~0;
ecc89f25
JC		 3170 } else if (IS_QLA28XX(ha)) {
3171 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3172 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3173 ha->mbx_count = MAILBOX_REGISTER_COUNT;
ade660d4
QT		 3174 req_length = REQUEST_ENTRY_CNT_83XX;
3175 rsp_length = RESPONSE_ENTRY_CNT_83XX;
ecc89f25
JC		 3176 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3177 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3178 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3179 ha->gid_list_info_size = 8;
3180 ha->optrom_size = OPTROM_SIZE_28XX;
3181 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3182 ha->isp_ops = &qla27xx_isp_ops;
3183 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3184 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3185 ha->nvram_conf_off = ~0;
3186 ha->nvram_data_off = ~0;
1da177e4 3187 }
6246b8a1 3188
7c3df132
SK		 3189 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3190 "mbx_count=%d, req_length=%d, "
3191 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 3192 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3193 "max_fibre_devices=%d.\n",
7c3df132
SK		 3194 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3195 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 3196 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 3197 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3198 "isp_ops=%p, flash_conf_off=%d, "
3199 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3200 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3201 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 3202
3203 /* Configure PCI I/O space */
3204 ret = ha->isp_ops->iospace_config(ha);
3205 if (ret)
0a63ad12 3206 goto iospace_config_failed;
706f457d
GM		 3207
3208 ql_log_pci(ql_log_info, pdev, 0x001d,
3209 "Found an ISP%04X irq %d iobase 0x%p.\n",
3210 pdev->device, pdev->irq, ha->iobase);
6c2f527c 3211 mutex_init(&ha->vport_lock);
d7459527 3212 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 3213 init_completion(&ha->mbx_cmd_comp);
3214 complete(&ha->mbx_cmd_comp);
3215 init_completion(&ha->mbx_intr_comp);
23f2ebd1 3216 init_completion(&ha->dcbx_comp);
f356bef1 3217 init_completion(&ha->lb_portup_comp);
1da177e4 3218
2c3dfe3f 3219 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 3220
53303c42 3221 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 3222 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3223 "64 Bit addressing is %s.\n",
3224 ha->flags.enable_64bit_addressing ? "enable" :
3225 "disable");
73208dfd 3226 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 3227 if (ret) {
7c3df132
SK		 3228 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3229 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 3230
e315cd28
AC		 3231 goto probe_hw_failed;
3232 }
3233
73208dfd 3234 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 3235 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3236 req->max_q_depth = ql2xmaxqdepth;
3237
e315cd28
AC		 3238
3239 base_vha = qla2x00_create_host(sht, ha);
3240 if (!base_vha) {
a1541d5a 3241 ret = -ENOMEM;
e315cd28 3242 goto probe_hw_failed;
1da177e4
LT		 3243 }
3244
e315cd28 3245 pci_set_drvdata(pdev, base_vha);
6b383979 3246 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3247
e315cd28 3248 host = base_vha->host;
2afa19a9 3249 base_vha->req = req;
73208dfd 3250 if (IS_QLA2XXX_MIDTYPE(ha))
f6602f3b
QT		 3251 base_vha->mgmt_svr_loop_id =
3252 qla2x00_reserve_mgmt_server_loop_id(base_vha);
73208dfd 3253 else
e315cd28
AC		 3254 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3255 base_vha->vp_idx;
58548cb5 3256
8ae6d9c7
GM		 3257 /* Setup fcport template structure. */
3258 ha->mr.fcport.vha = base_vha;
3259 ha->mr.fcport.port_type = FCT_UNKNOWN;
3260 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3261 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3262 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3263 ha->mr.fcport.scan_state = 1;
3264
dbf1f53c
SK		 3265 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN |
3266 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT |
3267 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN);
3268
58548cb5
GM		 3269 /* Set the SG table size based on ISP type */
3270 if (!IS_FWI2_CAPABLE(ha)) {
3271 if (IS_QLA2100(ha))
3272 host->sg_tablesize = 32;
3273 } else {
3274 if (!IS_QLA82XX(ha))
3275 host->sg_tablesize = QLA_SG_ALL;
3276 }
642ef983 3277 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3278 host->cmd_per_lun = 3;
3279 host->unique_id = host->host_no;
e9105c4b
MR		 3280
3281 if (ql2xenabledif && ql2xenabledif != 2) {
3282 ql_log(ql_log_warn, base_vha, 0x302d,
3283 "Invalid value for ql2xenabledif, resetting it to default (2)\n");
3284 ql2xenabledif = 2;
3285 }
3286
e02587d7 3287 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3288 host->max_cmd_len = 32;
3289 else
3290 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3291 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3292 /* Older HBAs support only 16-bit LUNs */
3293 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3294 ql2xmaxlun > 0xffff)
3295 host->max_lun = 0xffff;
3296 else
3297 host->max_lun = ql2xmaxlun;
e315cd28 3298 host->transportt = qla2xxx_transport_template;
9a069e19 3299 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3300
7c3df132
SK		 3301 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3302 "max_id=%d this_id=%d "
3303 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3304 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3305 host->this_id, host->cmd_per_lun, host->unique_id,
3306 host->max_cmd_len, host->max_channel, host->max_lun,
3307 host->transportt, sht->vendor_id);
3308
3a4e1f3b 3309 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn);
1010f21e 3310
d7459527
MH		 3311 /* Set up the irqs */
3312 ret = qla2x00_request_irqs(ha, rsp);
3313 if (ret)
6a2cf8d3 3314 goto probe_failed;
d7459527 3315
9a347ff4 3316 /* Alloc arrays of request and response ring ptrs */
6d634067
BK		 3317 ret = qla2x00_alloc_queues(ha, req, rsp);
3318 if (ret) {
9a347ff4
CD		 3319 ql_log(ql_log_fatal, base_vha, 0x003d,
3320 "Failed to allocate memory for queue pointers..."
3321 "aborting.\n");
26a77799 3322 ret = -ENODEV;
6a2cf8d3 3323 goto probe_failed;
9a347ff4
CD		 3324 }
3325
f664a3cc 3326 if (ha->mqenable) {
5601236b
MH		 3327 /* number of hardware queues supported by blk/scsi-mq*/
3328 host->nr_hw_queues = ha->max_qpairs;
3329
3330 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3331 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
c38d1baf
HM		 3332 } else {
3333 if (ql2xnvmeenable) {
3334 host->nr_hw_queues = ha->max_qpairs;
3335 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3336 "FC-NVMe support is enabled, HW queues=%d\n",
3337 host->nr_hw_queues);
3338 } else {
3339 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3340 "blk/scsi-mq disabled.\n");
3341 }
3342 }
5601236b 3343
2d70c103 3344 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3345
90a86fc0
JC		 3346 pci_save_state(pdev);
3347
9a347ff4 3348 /* Assign back pointers */
2afa19a9
AC		 3349 rsp->req = req;
3350 req->rsp = rsp;
9a347ff4 3351
8ae6d9c7
GM		 3352 if (IS_QLAFX00(ha)) {
3353 ha->rsp_q_map[0] = rsp;
3354 ha->req_q_map[0] = req;
3355 set_bit(0, ha->req_qid_map);
3356 set_bit(0, ha->rsp_qid_map);
3357 }
3358
08029990
AV		 3359 /* FWI2-capable only. */
3360 req->req_q_in = &ha->iobase->isp24.req_q_in;
3361 req->req_q_out = &ha->iobase->isp24.req_q_out;
3362 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3363 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
ecc89f25
JC		 3364 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3365 IS_QLA28XX(ha)) {
08029990
AV		 3366 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3367 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3368 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3369 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3370 }
3371
8ae6d9c7
GM		 3372 if (IS_QLAFX00(ha)) {
3373 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3374 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3375 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3376 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3377 }
3378
7ec0effd 3379 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3380 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3381 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3382 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3383 }
3384
7c3df132
SK		 3385 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3386 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3387 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3388 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3389 "req->req_q_in=%p req->req_q_out=%p "
3390 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3391 req->req_q_in, req->req_q_out,
3392 rsp->rsp_q_in, rsp->rsp_q_out);
3393 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3394 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3395 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3396 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3397 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3398 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3399
0a6f4d76 3400 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0);
35a79a63
AP		 3401 if (unlikely(!ha->wq)) {
3402 ret = -ENOMEM;
3403 goto probe_failed;
3404 }
d48cc67c 3405
8ae6d9c7 3406 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3407 ql_log(ql_log_fatal, base_vha, 0x00d6,
3408 "Failed to initialize adapter - Adapter flags %x.\n",
3409 base_vha->device_flags);
1da177e4 3410
a9083016
GM		 3411 if (IS_QLA82XX(ha)) {
3412 qla82xx_idc_lock(ha);
3413 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3414 QLA8XXX_DEV_FAILED);
a9083016 3415 qla82xx_idc_unlock(ha);
7c3df132
SK		 3416 ql_log(ql_log_fatal, base_vha, 0x00d7,
3417 "HW State: FAILED.\n");
7ec0effd
AD		 3418 } else if (IS_QLA8044(ha)) {
3419 qla8044_idc_lock(ha);
3420 qla8044_wr_direct(base_vha,
3421 QLA8044_CRB_DEV_STATE_INDEX,
3422 QLA8XXX_DEV_FAILED);
3423 qla8044_idc_unlock(ha);
3424 ql_log(ql_log_fatal, base_vha, 0x0150,
3425 "HW State: FAILED.\n");
a9083016
GM		 3426 }
3427
a1541d5a 3428 ret = -ENODEV;
1da177e4
LT		 3429 goto probe_failed;
3430 }
3431
3b1bef64
CD		 3432 if (IS_QLAFX00(ha))
3433 host->can_queue = QLAFX00_MAX_CANQUEUE;
3434 else
3435 host->can_queue = req->num_outstanding_cmds - 10;
3436
3437 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3438 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3439 host->can_queue, base_vha->req,
3440 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3441
8192817e
SK		 3442 /* Check if FW supports MQ or not for ISP25xx */
3443 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6))
3444 ha->mqenable = 0;
3445
e326d22a 3446 if (ha->mqenable) {
e326d22a 3447 bool startit = false;
e326d22a 3448
f664a3cc 3449 if (QLA_TGT_MODE_ENABLED())
e326d22a 3450 startit = false;
e326d22a 3451
f664a3cc 3452 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
e326d22a 3453 startit = true;
e326d22a 3454
f664a3cc
JA		 3455 /* Create start of day qpairs for Block MQ */
3456 for (i = 0; i < ha->max_qpairs; i++)
3457 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b 3458 }
89c72f42 3459 qla_init_iocb_limit(base_vha);
68ca949c 3460
cbc8eb67
AV		 3461 if (ha->flags.running_gold_fw)
3462 goto skip_dpc;
3463
1da177e4
LT		 3464 /*
3465 * Startup the kernel thread for this host adapter
3466 */
39a11240 3467 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3468 "%s_dpc", base_vha->host_str);
39a11240 3469 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3470 ql_log(ql_log_fatal, base_vha, 0x00ed,
3471 "Failed to start DPC thread.\n");
39a11240 3472 ret = PTR_ERR(ha->dpc_thread);
e2532b4a 3473 ha->dpc_thread = NULL;
1da177e4
LT		 3474 goto probe_failed;
3475 }
7c3df132
SK		 3476 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3477 "DPC thread started successfully.\n");
1da177e4 3478
2d70c103
NB		 3479 /*
3480 * If we're not coming up in initiator mode, we might sit for
3481 * a while without waking up the dpc thread, which leads to a
3482 * stuck process warning. So just kick the dpc once here and
3483 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3484 */
3485 qla2xxx_wake_dpc(base_vha);
3486
f3ddac19
CD		 3487 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3488
81178772
SK		 3489 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3490 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
b97c0741
BVA		 3491 ha->dpc_lp_wq =
3492 alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, wq_name);
81178772
SK		 3493 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3494
3495 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
b97c0741
BVA		 3496 ha->dpc_hp_wq =
3497 alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, wq_name);
81178772
SK		 3498 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3499 INIT_WORK(&ha->idc_state_handler,
3500 qla83xx_idc_state_handler_work);
3501 INIT_WORK(&ha->nic_core_unrecoverable,
3502 qla83xx_nic_core_unrecoverable_work);
3503 }
3504
cbc8eb67 3505skip_dpc:
e315cd28
AC		 3506 list_add_tail(&base_vha->list, &ha->vp_list);
3507 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3508
3509 /* Initialized the timer */
8e5f4ba0 3510 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3511 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3512 "Started qla2x00_timer with "
3513 "interval=%d.\n", WATCH_INTERVAL);
3514 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3515 "Detected hba at address=%p.\n",
3516 ha);
d19044c3 3517
e02587d7 3518 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3519 if (ha->fw_attributes & BIT_4) {
9e522cd8 3520 int prot = 0, guard;
bd432bb5 3521
bad75002 3522 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3523 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3524 "Registering for DIF/DIX type 1 and 3 protection.\n");
7855d2ba
MP		 3525 if (ql2xprotmask)
3526 scsi_host_set_prot(host, ql2xprotmask);
3527 else
3528 scsi_host_set_prot(host,
3529 prot | SHOST_DIF_TYPE1_PROTECTION
3530 | SHOST_DIF_TYPE2_PROTECTION
3531 | SHOST_DIF_TYPE3_PROTECTION
3532 | SHOST_DIX_TYPE1_PROTECTION
3533 | SHOST_DIX_TYPE2_PROTECTION
3534 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3535
3536 guard = SHOST_DIX_GUARD_CRC;
3537
3538 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3539 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3540 guard |= SHOST_DIX_GUARD_IP;
3541
7855d2ba
MP		 3542 if (ql2xprotguard)
3543 scsi_host_set_guard(host, ql2xprotguard);
3544 else
3545 scsi_host_set_guard(host, guard);
bad75002
AE		 3546 } else
3547 base_vha->flags.difdix_supported = 0;
3548 }
3549
a9083016
GM		 3550 ha->isp_ops->enable_intrs(ha);
3551
1fe19ee4
AB		 3552 if (IS_QLAFX00(ha)) {
3553 ret = qlafx00_fx_disc(base_vha,
3554 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3555 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3556 QLA_SG_ALL : 128;
3557 }
3558
5b7dfbef
CH		 3559 if (IS_T10_PI_CAPABLE(base_vha->hw))
3560 host->dma_alignment = 0x7;
3561
a1541d5a
AV		 3562 ret = scsi_add_host(host, &pdev->dev);
3563 if (ret)
3564 goto probe_failed;
3565
1486400f
MR		 3566 base_vha->flags.init_done = 1;
3567 base_vha->flags.online = 1;
edaa5c74 3568 ha->prev_minidump_failed = 0;
1486400f 3569
7c3df132
SK		 3570 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3571 "Init done and hba is online.\n");
3572
726b8548
QT		 3573 if (qla_ini_mode_enabled(base_vha) ||
3574 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3575 scsi_scan_host(host);
3576 else
eee8bb4a 3577 ql_log(ql_log_info, base_vha, 0x0122,
2d70c103 3578 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3579
e315cd28 3580 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3581
8ae6d9c7 3582 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3583 ret = qlafx00_fx_disc(base_vha,
3584 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3585
3586 /* Register system information */
3587 ret = qlafx00_fx_disc(base_vha,
3588 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3589 }
3590
e315cd28 3591 qla2x00_init_host_attr(base_vha);
a1541d5a 3592
e315cd28 3593 qla2x00_dfs_setup(base_vha);
df613b96 3594
03eb912a
AB		 3595 ql_log(ql_log_info, base_vha, 0x00fb,
3596 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3597 ql_log(ql_log_info, base_vha, 0x00fc,
3598 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
dc6d6d34
BVA		 3599 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3600 sizeof(pci_info)),
7c3df132
SK		 3601 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3602 base_vha->host_no,
df57caba 3603 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3604
2d70c103
NB		 3605 qlt_add_target(ha, base_vha);
3606
6b383979 3607 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3608
3609 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3610 return -ENODEV;
3611
1da177e4
LT		 3612 return 0;
3613
3614probe_failed:
84318a9f 3615 qla_enode_stop(base_vha);
7a09e8d9 3616 qla_edb_stop(base_vha);
85ade401 3617 vfree(base_vha->scan.l);
26fa656e
BK		 3618 if (base_vha->gnl.l) {
3619 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3620 base_vha->gnl.l, base_vha->gnl.ldma);
3621 base_vha->gnl.l = NULL;
3622 }
3623
b9978769
AV		 3624 if (base_vha->timer_active)
3625 qla2x00_stop_timer(base_vha);
3626 base_vha->flags.online = 0;
3627 if (ha->dpc_thread) {
3628 struct task_struct *t = ha->dpc_thread;
3629
3630 ha->dpc_thread = NULL;
3631 kthread_stop(t);
3632 }
3633
e315cd28 3634 qla2x00_free_device(base_vha);
e315cd28 3635 scsi_host_put(base_vha->host);
6d634067
BK		 3636 /*
3637 * Need to NULL out local req/rsp after
3638 * qla2x00_free_device => qla2x00_free_queues frees
3639 * what these are pointing to. Or else we'll
3640 * fall over below in qla2x00_free_req/rsp_que.
3641 */
3642 req = NULL;
3643 rsp = NULL;
1da177e4 3644
e315cd28 3645probe_hw_failed:
d64d6c56 3646 qla2x00_mem_free(ha);
3647 qla2x00_free_req_que(ha, req);
3648 qla2x00_free_rsp_que(ha, rsp);
1a2fbf18
JL		 3649 qla2x00_clear_drv_active(ha);
3650
0a63ad12 3651iospace_config_failed:
7ec0effd 3652 if (IS_P3P_TYPE(ha)) {
0a63ad12 3653 if (!ha->nx_pcibase)
f73cb695 3654 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3655 if (!ql2xdbwr)
f73cb695 3656 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3657 } else {
3658 if (ha->iobase)
3659 iounmap(ha->iobase);
8ae6d9c7
GM		 3660 if (ha->cregbase)
3661 iounmap(ha->cregbase);
a9083016 3662 }
e315cd28
AC		 3663 pci_release_selected_regions(ha->pdev, ha->bars);
3664 kfree(ha);
1da177e4 3665
ddff7ed4 3666disable_device:
e315cd28 3667 pci_disable_device(pdev);
a1541d5a 3668 return ret;
1da177e4 3669}
1da177e4 3670
6997db98
QT		 3671static void __qla_set_remove_flag(scsi_qla_host_t *base_vha)
3672{
3673 scsi_qla_host_t *vp;
3674 unsigned long flags;
3675 struct qla_hw_data *ha;
3676
3677 if (!base_vha)
3678 return;
3679
3680 ha = base_vha->hw;
3681
3682 spin_lock_irqsave(&ha->vport_slock, flags);
3683 list_for_each_entry(vp, &ha->vp_list, list)
3684 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags);
3685
3686 /*
3687 * Indicate device removal to prevent future board_disable
3688 * and wait until any pending board_disable has completed.
3689 */
3690 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3691 spin_unlock_irqrestore(&ha->vport_slock, flags);
3692}
3693
e30d1756
MI		 3694static void
3695qla2x00_shutdown(struct pci_dev *pdev)
3696{
3697 scsi_qla_host_t *vha;
3698 struct qla_hw_data *ha;
3699
3700 vha = pci_get_drvdata(pdev);
3701 ha = vha->hw;
3702
efdb5760
SC		 3703 ql_log(ql_log_info, vha, 0xfffa,
3704 "Adapter shutdown\n");
3705
3706 /*
3707 * Prevent future board_disable and wait
3708 * until any pending board_disable has completed.
3709 */
6997db98 3710 __qla_set_remove_flag(vha);
efdb5760
SC		 3711 cancel_work_sync(&ha->board_disable);
3712
3713 if (!atomic_read(&pdev->enable_cnt))
3714 return;
3715
42479343
AB		 3716 /* Notify ISPFX00 firmware */
3717 if (IS_QLAFX00(ha))
3718 qlafx00_driver_shutdown(vha, 20);
3719
e30d1756
MI		 3720 /* Turn-off FCE trace */
3721 if (ha->flags.fce_enabled) {
3722 qla2x00_disable_fce_trace(vha, NULL, NULL);
3723 ha->flags.fce_enabled = 0;
3724 }
3725
3726 /* Turn-off EFT trace */
3727 if (ha->eft)
3728 qla2x00_disable_eft_trace(vha);
3729
ecc89f25
JC		 3730 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3731 IS_QLA28XX(ha)) {
3407fc37
QT		 3732 if (ha->flags.fw_started)
3733 qla2x00_abort_isp_cleanup(vha);
3734 } else {
3735 /* Stop currently executing firmware. */
3736 qla2x00_try_to_stop_firmware(vha);
3737 }
e30d1756 3738
d3566abb
NP		 3739 /* Disable timer */
3740 if (vha->timer_active)
3741 qla2x00_stop_timer(vha);
3742
e30d1756
MI		 3743 /* Turn adapter off line */
3744 vha->flags.online = 0;
3745
3746 /* turn-off interrupts on the card */
3747 if (ha->interrupts_on) {
3748 vha->flags.init_done = 0;
3749 ha->isp_ops->disable_intrs(ha);
3750 }
3751
3752 qla2x00_free_irqs(vha);
3753
3754 qla2x00_free_fw_dump(ha);
61d41f61 3755
61d41f61 3756 pci_disable_device(pdev);
efdb5760
SC		 3757 ql_log(ql_log_info, vha, 0xfffe,
3758 "Adapter shutdown successfully.\n");
e30d1756
MI		 3759}
3760
fe1b806f 3761/* Deletes all the virtual ports for a given ha */
4c993f76 3762static void
fe1b806f 3763qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3764{
fe1b806f 3765 scsi_qla_host_t *vha;
feafb7b1 3766 unsigned long flags;
e315cd28 3767
43ebf16d
AE		 3768 mutex_lock(&ha->vport_lock);
3769 while (ha->cur_vport_count) {
43ebf16d 3770 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3771
43ebf16d
AE		 3772 BUG_ON(base_vha->list.next == &ha->vp_list);
3773 /* This assumes first entry in ha->vp_list is always base vha */
3774 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3775 scsi_host_get(vha->host);
feafb7b1 3776
43ebf16d
AE		 3777 spin_unlock_irqrestore(&ha->vport_slock, flags);
3778 mutex_unlock(&ha->vport_lock);
3779
5e6803b4
HM		 3780 qla_nvme_delete(vha);
3781
43ebf16d
AE		 3782 fc_vport_terminate(vha->fc_vport);
3783 scsi_host_put(vha->host);
feafb7b1 3784
43ebf16d 3785 mutex_lock(&ha->vport_lock);
e315cd28 3786 }
43ebf16d 3787 mutex_unlock(&ha->vport_lock);
fe1b806f 3788}
1da177e4 3789
fe1b806f
CD		 3790/* Stops all deferred work threads */
3791static void
3792qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3793{
7d613ac6
SV		 3794 /* Cancel all work and destroy DPC workqueues */
3795 if (ha->dpc_lp_wq) {
3796 cancel_work_sync(&ha->idc_aen);
3797 destroy_workqueue(ha->dpc_lp_wq);
3798 ha->dpc_lp_wq = NULL;
3799 }
3800
3801 if (ha->dpc_hp_wq) {
3802 cancel_work_sync(&ha->nic_core_reset);
3803 cancel_work_sync(&ha->idc_state_handler);
3804 cancel_work_sync(&ha->nic_core_unrecoverable);
3805 destroy_workqueue(ha->dpc_hp_wq);
3806 ha->dpc_hp_wq = NULL;
3807 }
3808
b9978769
AV		 3809 /* Kill the kernel thread for this host */
3810 if (ha->dpc_thread) {
3811 struct task_struct *t = ha->dpc_thread;
3812
3813 /*
3814 * qla2xxx_wake_dpc checks for ->dpc_thread
3815 * so we need to zero it out.
3816 */
3817 ha->dpc_thread = NULL;
3818 kthread_stop(t);
3819 }
fe1b806f 3820}
1da177e4 3821
fe1b806f
CD		 3822static void
3823qla2x00_unmap_iobases(struct qla_hw_data *ha)
3824{
a9083016 3825 if (IS_QLA82XX(ha)) {
b963752f 3826
f73cb695 3827 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3828 if (!ql2xdbwr)
f73cb695 3829 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3830 } else {
3831 if (ha->iobase)
3832 iounmap(ha->iobase);
1da177e4 3833
8ae6d9c7
GM		 3834 if (ha->cregbase)
3835 iounmap(ha->cregbase);
3836
a9083016
GM		 3837 if (ha->mqiobase)
3838 iounmap(ha->mqiobase);
6246b8a1 3839
0d6a536c 3840 if (ha->msixbase)
6246b8a1 3841 iounmap(ha->msixbase);
a9083016 3842 }
fe1b806f
CD		 3843}
3844
3845static void
db7157d4 3846qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3847{
fe1b806f
CD		 3848 if (IS_QLA8044(ha)) {
3849 qla8044_idc_lock(ha);
c41afc9a 3850 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3851 qla8044_idc_unlock(ha);
3852 } else if (IS_QLA82XX(ha)) {
3853 qla82xx_idc_lock(ha);
3854 qla82xx_clear_drv_active(ha);
3855 qla82xx_idc_unlock(ha);
3856 }
3857}
3858
3859static void
3860qla2x00_remove_one(struct pci_dev *pdev)
3861{
3862 scsi_qla_host_t *base_vha;
3863 struct qla_hw_data *ha;
3864
beb9e315
JL		 3865 base_vha = pci_get_drvdata(pdev);
3866 ha = base_vha->hw;
45235022
QT		 3867 ql_log(ql_log_info, base_vha, 0xb079,
3868 "Removing driver\n");
6997db98 3869 __qla_set_remove_flag(base_vha);
beb9e315
JL		 3870 cancel_work_sync(&ha->board_disable);
3871
fe1b806f 3872 /*
beb9e315
JL		 3873 * If the PCI device is disabled then there was a PCI-disconnect and
3874 * qla2x00_disable_board_on_pci_error has taken care of most of the
3875 * resources.
fe1b806f 3876 */
beb9e315 3877 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3878 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3879 base_vha->gnl.l, base_vha->gnl.ldma);
26fa656e 3880 base_vha->gnl.l = NULL;
beb9e315
JL		 3881 scsi_host_put(base_vha->host);
3882 kfree(ha);
3883 pci_set_drvdata(pdev, NULL);
fe1b806f 3884 return;
beb9e315 3885 }
638a1a01
SC		 3886 qla2x00_wait_for_hba_ready(base_vha);
3887
856e152a
MW		 3888 /*
3889 * if UNLOADING flag is already set, then continue unload,
3890 * where it was set first.
3891 */
3892 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
3893 return;
3894
ecc89f25
JC		 3895 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3896 IS_QLA28XX(ha)) {
45235022
QT		 3897 if (ha->flags.fw_started)
3898 qla2x00_abort_isp_cleanup(base_vha);
3899 } else if (!IS_QLAFX00(ha)) {
3900 if (IS_QLA8031(ha)) {
3901 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3902 "Clearing fcoe driver presence.\n");
3903 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3904 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3905 "Error while clearing DRV-Presence.\n");
3906 }
3907
3908 qla2x00_try_to_stop_firmware(base_vha);
3909 }
3910
2ce87cc5
QT		 3911 qla2x00_wait_for_sess_deletion(base_vha);
3912
e84067d7
DG		 3913 qla_nvme_delete(base_vha);
3914
726b8548
QT		 3915 dma_free_coherent(&ha->pdev->dev,
3916 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f 3917
26fa656e 3918 base_vha->gnl.l = NULL;
84318a9f 3919 qla_enode_stop(base_vha);
7a09e8d9 3920 qla_edb_stop(base_vha);
26fa656e 3921
a4239945
QT		 3922 vfree(base_vha->scan.l);
3923
fe1b806f
CD		 3924 if (IS_QLAFX00(ha))
3925 qlafx00_driver_shutdown(base_vha, 20);
3926
3927 qla2x00_delete_all_vps(ha, base_vha);
3928
fe1b806f
CD		 3929 qla2x00_dfs_remove(base_vha);
3930
3931 qla84xx_put_chip(base_vha);
3932
3933 /* Disable timer */
3934 if (base_vha->timer_active)
3935 qla2x00_stop_timer(base_vha);
3936
3937 base_vha->flags.online = 0;
3938
b0d6cabd
HM		 3939 /* free DMA memory */
3940 if (ha->exlogin_buf)
3941 qla2x00_free_exlogin_buffer(ha);
3942
2f56a7f1
HM		 3943 /* free DMA memory */
3944 if (ha->exchoffld_buf)
3945 qla2x00_free_exchoffld_buffer(ha);
3946
fe1b806f
CD		 3947 qla2x00_destroy_deferred_work(ha);
3948
3949 qlt_remove_target(ha, base_vha);
3950
3951 qla2x00_free_sysfs_attr(base_vha, true);
3952
3953 fc_remove_host(base_vha->host);
3954
3955 scsi_remove_host(base_vha->host);
3956
3957 qla2x00_free_device(base_vha);
3958
db7157d4 3959 qla2x00_clear_drv_active(ha);
fe1b806f 3960
d2749ffa
AE		 3961 scsi_host_put(base_vha->host);
3962
fe1b806f 3963 qla2x00_unmap_iobases(ha);
73208dfd 3964
e315cd28
AC		 3965 pci_release_selected_regions(ha->pdev, ha->bars);
3966 kfree(ha);
1da177e4 3967
665db93b 3968 pci_disable_device(pdev);
1da177e4 3969}
1da177e4 3970
576bfde8
JC		 3971static inline void
3972qla24xx_free_purex_list(struct purex_list *list)
3973{
8062b742 3974 struct purex_item *item, *next;
576bfde8
JC		 3975 ulong flags;
3976
3977 spin_lock_irqsave(&list->lock, flags);
8062b742
QT		 3978 list_for_each_entry_safe(item, next, &list->head, list) {
3979 list_del(&item->list);
09722524
AE		 3980 if (item == &item->vha->default_item)
3981 continue;
8062b742 3982 kfree(item);
576bfde8
JC		 3983 }
3984 spin_unlock_irqrestore(&list->lock, flags);
3985}
3986
1da177e4 3987static void
e315cd28 3988qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3989{
e315cd28 3990 struct qla_hw_data *ha = vha->hw;
1da177e4 3991
85880801
AV		 3992 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3993
3994 /* Disable timer */
3995 if (vha->timer_active)
3996 qla2x00_stop_timer(vha);
3997
2afa19a9 3998 qla25xx_delete_queues(vha);
85880801
AV		 3999 vha->flags.online = 0;
4000
f6ef3b18 4001 /* turn-off interrupts on the card */
a9083016
GM		 4002 if (ha->interrupts_on) {
4003 vha->flags.init_done = 0;
fd34f556 4004 ha->isp_ops->disable_intrs(ha);
a9083016 4005 }
f6ef3b18 4006
093df737
QT		 4007 qla2x00_free_fcports(vha);
4008
e315cd28 4009 qla2x00_free_irqs(vha);
1da177e4 4010
093df737
QT		 4011 /* Flush the work queue and remove it */
4012 if (ha->wq) {
093df737
QT		 4013 destroy_workqueue(ha->wq);
4014 ha->wq = NULL;
4015 }
4016
8867048b 4017
576bfde8
JC		 4018 qla24xx_free_purex_list(&vha->purex_list);
4019
e315cd28 4020 qla2x00_mem_free(ha);
73208dfd 4021
08de2844
GM		 4022 qla82xx_md_free(vha);
4023
dd30706e
QT		 4024 qla_edif_sadb_release_free_pool(ha);
4025 qla_edif_sadb_release(ha);
4026
73208dfd 4027 qla2x00_free_queues(ha);
1da177e4
LT		 4028}
4029
8867048b
CD		 4030void qla2x00_free_fcports(struct scsi_qla_host *vha)
4031{
4032 fc_port_t *fcport, *tfcport;
4033
ffbc6476
QT		 4034 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
4035 qla2x00_free_fcport(fcport);
8867048b
CD		 4036}
4037
d97994dc 4038static inline void
3c75ad1d 4039qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport)
d97994dc 4040{
3c75ad1d 4041 int now;
d97994dc 4042
4043 if (!fcport->rport)
4044 return;
4045
3c75ad1d
HM		 4046 if (fcport->rport) {
4047 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
4048 "%s %8phN. rport %p roles %x\n",
4049 __func__, fcport->port_name, fcport->rport,
4050 fcport->rport->roles);
4051 fc_remote_port_delete(fcport->rport);
2d70c103 4052 }
3c75ad1d 4053 qlt_do_generation_tick(vha, &now);
d97994dc 4054}
4055
1da177e4
LT		 4056/*
4057 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
4058 *
4059 * Input: ha = adapter block pointer. fcport = port structure pointer.
4060 *
4061 * Return: None.
4062 *
4063 * Context:
4064 */
e315cd28 4065void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3c75ad1d 4066 int do_login)
1da177e4 4067{
8ae6d9c7
GM		 4068 if (IS_QLAFX00(vha->hw)) {
4069 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3c75ad1d 4070 qla2x00_schedule_rport_del(vha, fcport);
8ae6d9c7
GM		 4071 return;
4072 }
4073
2c3dfe3f 4074 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 4075 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 4076 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3c75ad1d 4077 qla2x00_schedule_rport_del(vha, fcport);
e315cd28 4078 }
9efea843 4079
fa2a1ce5 4080 /*
1da177e4
LT		 4081 * We may need to retry the login, so don't change the state of the
4082 * port but do the retries.
4083 */
4084 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 4085 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 4086
4087 if (!do_login)
4088 return;
4089
a1d0285e 4090 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4091}
4092
1da177e4 4093void
3c75ad1d 4094qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha)
1da177e4
LT		 4095{
4096 fc_port_t *fcport;
4097
83548fe2
QT		 4098 ql_dbg(ql_dbg_disc, vha, 0x20f1,
4099 "Mark all dev lost\n");
726b8548 4100
e315cd28 4101 list_for_each_entry(fcport, &vha->vp_fcports, list) {
877b0379
DW		 4102 if (ql2xfc2target &&
4103 fcport->loop_id != FC_NO_LOOP_ID &&
44c57f20
SK		 4104 (fcport->flags & FCF_FCP2_DEVICE) &&
4105 fcport->port_type == FCT_TARGET &&
4106 !qla2x00_reset_active(vha)) {
4107 ql_dbg(ql_dbg_disc, vha, 0x211a,
4108 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC",
4109 fcport->flags, fcport->port_type,
4110 fcport->d_id.b24, fcport->port_name);
4111 continue;
4112 }
726b8548 4113 fcport->scan_state = 0;
d8630bb9 4114 qlt_schedule_sess_for_deletion(fcport);
1da177e4
LT		 4115 }
4116}
4117
0e145a59
BVA		 4118static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
4119{
4120 int i;
4121
4122 if (IS_FWI2_CAPABLE(ha))
4123 return;
4124
4125 for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
4126 set_bit(i, ha->loop_id_map);
4127 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
4128 set_bit(BROADCAST, ha->loop_id_map);
4129}
4130
1da177e4
LT		 4131/*
4132* qla2x00_mem_alloc
4133* Allocates adapter memory.
4134*
4135* Returns:
4136* 0 = success.
e8711085 4137* !0 = failure.
1da177e4 4138*/
e8711085 4139static int
73208dfd
AC		 4140qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
4141 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 4142{
4143 char name[16];
fac28079 4144 int rc;
1da177e4 4145
430eef03
QT		 4146 if (QLA_TGT_MODE_ENABLED() || EDIF_CAP(ha)) {
4147 ha->vp_map = kcalloc(MAX_MULTI_ID_FABRIC, sizeof(struct qla_vp_map), GFP_KERNEL);
4148 if (!ha->vp_map)
4149 goto fail;
4150 }
4151
e8711085 4152 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 4153 &ha->init_cb_dma, GFP_KERNEL);
e8711085 4154 if (!ha->init_cb)
430eef03 4155 goto fail_free_vp_map;
e8711085 4156
fac28079
QT		 4157 rc = btree_init32(&ha->host_map);
4158 if (rc)
2d70c103
NB		 4159 goto fail_free_init_cb;
4160
fac28079
QT		 4161 if (qlt_mem_alloc(ha) < 0)
4162 goto fail_free_btree;
4163
642ef983
CD		 4164 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
4165 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 4166 if (!ha->gid_list)
2d70c103 4167 goto fail_free_tgt_mem;
1da177e4 4168
e8711085
AV		 4169 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4170 if (!ha->srb_mempool)
e315cd28 4171 goto fail_free_gid_list;
e8711085 4172
44d01857 4173 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) {
a9083016
GM		 4174 /* Allocate cache for CT6 Ctx. */
4175 if (!ctx_cachep) {
4176 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4177 sizeof(struct ct6_dsd), 0,
4178 SLAB_HWCACHE_ALIGN, NULL);
4179 if (!ctx_cachep)
fc1ffd6c 4180 goto fail_free_srb_mempool;
a9083016
GM		 4181 }
4182 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4183 ctx_cachep);
4184 if (!ha->ctx_mempool)
4185 goto fail_free_srb_mempool;
7c3df132
SK		 4186 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4187 "ctx_cachep=%p ctx_mempool=%p.\n",
4188 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 4189 }
4190
e8711085
AV		 4191 /* Get memory for cached NVRAM */
4192 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4193 if (!ha->nvram)
a9083016 4194 goto fail_free_ctx_mempool;
e8711085 4195
e315cd28
AC		 4196 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4197 ha->pdev->device);
4198 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4199 DMA_POOL_SIZE, 8, 0);
4200 if (!ha->s_dma_pool)
4201 goto fail_free_nvram;
4202
7c3df132
SK		 4203 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4204 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4205 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4206
44d01857 4207 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) {
a9083016
GM		 4208 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4209 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4210 if (!ha->dl_dma_pool) {
7c3df132
SK		 4211 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4212 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 4213 goto fail_s_dma_pool;
4214 }
4215
4216 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4217 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4218 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 4219 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4220 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 4221 goto fail_dl_dma_pool;
4222 }
50b81275
GM		 4223
4224 if (ql2xenabledif) {
4225 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4226 struct dsd_dma *dsd, *nxt;
4227 uint i;
4228 /* Creata a DMA pool of buffers for DIF bundling */
4229 ha->dif_bundl_pool = dma_pool_create(name,
4230 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4231 if (!ha->dif_bundl_pool) {
4232 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4233 "%s: failed create dif_bundl_pool\n",
4234 __func__);
4235 goto fail_dif_bundl_dma_pool;
4236 }
4237
4238 INIT_LIST_HEAD(&ha->pool.good.head);
4239 INIT_LIST_HEAD(&ha->pool.unusable.head);
4240 ha->pool.good.count = 0;
4241 ha->pool.unusable.count = 0;
4242 for (i = 0; i < 128; i++) {
4243 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4244 if (!dsd) {
4245 ql_dbg_pci(ql_dbg_init, ha->pdev,
4246 0xe0ee, "%s: failed alloc dsd\n",
4247 __func__);
06634d5b 4248 return -ENOMEM;
50b81275
GM		 4249 }
4250 ha->dif_bundle_kallocs++;
4251
4252 dsd->dsd_addr = dma_pool_alloc(
4253 ha->dif_bundl_pool, GFP_ATOMIC,
4254 &dsd->dsd_list_dma);
4255 if (!dsd->dsd_addr) {
4256 ql_dbg_pci(ql_dbg_init, ha->pdev,
4257 0xe0ee,
4258 "%s: failed alloc ->dsd_addr\n",
4259 __func__);
4260 kfree(dsd);
4261 ha->dif_bundle_kallocs--;
4262 continue;
4263 }
4264 ha->dif_bundle_dma_allocs++;
4265
4266 /*
4267 * if DMA buffer crosses 4G boundary,
4268 * put it on bad list
4269 */
4270 if (MSD(dsd->dsd_list_dma) ^
4271 MSD(dsd->dsd_list_dma + bufsize)) {
4272 list_add_tail(&dsd->list,
4273 &ha->pool.unusable.head);
4274 ha->pool.unusable.count++;
4275 } else {
4276 list_add_tail(&dsd->list,
4277 &ha->pool.good.head);
4278 ha->pool.good.count++;
4279 }
4280 }
4281
4282 /* return the good ones back to the pool */
4283 list_for_each_entry_safe(dsd, nxt,
4284 &ha->pool.good.head, list) {
4285 list_del(&dsd->list);
4286 dma_pool_free(ha->dif_bundl_pool,
4287 dsd->dsd_addr, dsd->dsd_list_dma);
4288 ha->dif_bundle_dma_allocs--;
4289 kfree(dsd);
4290 ha->dif_bundle_kallocs--;
4291 }
4292
4293 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4294 "%s: dif dma pool (good=%u unusable=%u)\n",
4295 __func__, ha->pool.good.count,
4296 ha->pool.unusable.count);
4297 }
4298
7c3df132 4299 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
50b81275
GM		 4300 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4301 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4302 ha->dif_bundl_pool);
a9083016
GM		 4303 }
4304
e8711085
AV		 4305 /* Allocate memory for SNS commands */
4306 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 4307 /* Get consistent memory allocated for SNS commands */
e8711085 4308 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4309 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 4310 if (!ha->sns_cmd)
e315cd28 4311 goto fail_dma_pool;
7c3df132 4312 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 4313 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 4314 } else {
e315cd28 4315 /* Get consistent memory allocated for MS IOCB */
e8711085 4316 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 4317 &ha->ms_iocb_dma);
e8711085 4318 if (!ha->ms_iocb)
e315cd28
AC		 4319 goto fail_dma_pool;
4320 /* Get consistent memory allocated for CT SNS commands */
e8711085 4321 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4322 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 4323 if (!ha->ct_sns)
4324 goto fail_free_ms_iocb;
7c3df132
SK		 4325 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4326 "ms_iocb=%p ct_sns=%p.\n",
4327 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 4328 }
4329
e315cd28 4330 /* Allocate memory for request ring */
73208dfd
AC		 4331 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4332 if (!*req) {
7c3df132
SK		 4333 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4334 "Failed to allocate memory for req.\n");
e315cd28
AC		 4335 goto fail_req;
4336 }
73208dfd
AC		 4337 (*req)->length = req_len;
4338 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4339 ((*req)->length + 1) * sizeof(request_t),
4340 &(*req)->dma, GFP_KERNEL);
4341 if (!(*req)->ring) {
7c3df132
SK		 4342 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4343 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 4344 goto fail_req_ring;
4345 }
4346 /* Allocate memory for response ring */
73208dfd
AC		 4347 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4348 if (!*rsp) {
7c3df132
SK		 4349 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4350 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 4351 goto fail_rsp;
4352 }
73208dfd
AC		 4353 (*rsp)->hw = ha;
4354 (*rsp)->length = rsp_len;
4355 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4356 ((*rsp)->length + 1) * sizeof(response_t),
4357 &(*rsp)->dma, GFP_KERNEL);
4358 if (!(*rsp)->ring) {
7c3df132
SK		 4359 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4360 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 4361 goto fail_rsp_ring;
4362 }
73208dfd
AC		 4363 (*req)->rsp = *rsp;
4364 (*rsp)->req = *req;
7c3df132
SK		 4365 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4366 "req=%p req->length=%d req->ring=%p rsp=%p "
4367 "rsp->length=%d rsp->ring=%p.\n",
4368 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4369 (*rsp)->ring);
73208dfd
AC		 4370 /* Allocate memory for NVRAM data for vports */
4371 if (ha->nvram_npiv_size) {
6396bb22
KC		 4372 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4373 sizeof(struct qla_npiv_entry),
4374 GFP_KERNEL);
73208dfd 4375 if (!ha->npiv_info) {
7c3df132
SK		 4376 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4377 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 4378 goto fail_npiv_info;
4379 }
4380 } else
4381 ha->npiv_info = NULL;
e8711085 4382
b64b0e8f 4383 /* Get consistent memory allocated for EX-INIT-CB. */
ecc89f25
JC		 4384 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4385 IS_QLA28XX(ha)) {
b64b0e8f
AV		 4386 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4387 &ha->ex_init_cb_dma);
4388 if (!ha->ex_init_cb)
4389 goto fail_ex_init_cb;
7c3df132
SK		 4390 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4391 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4392 }
4393
9f2475fe
SS		 4394 /* Get consistent memory allocated for Special Features-CB. */
4395 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
720efdd2 4396 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL,
9f2475fe
SS		 4397 &ha->sf_init_cb_dma);
4398 if (!ha->sf_init_cb)
4399 goto fail_sf_init_cb;
4400 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199,
4401 "sf_init_cb=%p.\n", ha->sf_init_cb);
4402 }
4403
a9083016 4404
5ff1d584
AV		 4405 /* Get consistent memory allocated for Async Port-Database. */
4406 if (!IS_FWI2_CAPABLE(ha)) {
4407 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4408 &ha->async_pd_dma);
4409 if (!ha->async_pd)
4410 goto fail_async_pd;
7c3df132
SK		 4411 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4412 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4413 }
4414
e315cd28 4415 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4416
4417 /* Allocate memory for our loop_id bitmap */
6396bb22
KC		 4418 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4419 sizeof(long),
4420 GFP_KERNEL);
5f16b331 4421 if (!ha->loop_id_map)
fc1ffd6c 4422 goto fail_loop_id_map;
5f16b331
CD		 4423 else {
4424 qla2x00_set_reserved_loop_ids(ha);
4425 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4426 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4427 }
4428
e4e3a2ce
QT		 4429 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4430 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4431 if (!ha->sfp_data) {
4432 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4433 "Unable to allocate memory for SFP read-data.\n");
4434 goto fail_sfp_data;
4435 }
4436
3f006ac3
MH		 4437 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4438 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4439 GFP_KERNEL);
4440 if (!ha->flt) {
4441 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4442 "Unable to allocate memory for FLT.\n");
4443 goto fail_flt_buffer;
4444 }
4445
84318a9f
QT		 4446 /* allocate the purex dma pool */
4447 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev,
0f6d600a 4448 ELS_MAX_PAYLOAD, 8, 0);
84318a9f
QT		 4449
4450 if (!ha->purex_dma_pool) {
4451 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4452 "Unable to allocate purex_dma_pool.\n");
4453 goto fail_flt;
4454 }
4455
4456 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16;
4457 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev,
875386b9
MR		 4458 ha->elsrej.size,
4459 &ha->elsrej.cdma,
4460 GFP_KERNEL);
84318a9f
QT		 4461 if (!ha->elsrej.c) {
4462 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4463 "Alloc failed for els reject cmd.\n");
4464 goto fail_elsrej;
4465 }
4466 ha->elsrej.c->er_cmd = ELS_LS_RJT;
22547929 4467 ha->elsrej.c->er_reason = ELS_RJT_LOGIC;
84318a9f 4468 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA;
875386b9
MR		 4469
4470 ha->lsrjt.size = sizeof(struct fcnvme_ls_rjt);
4471 ha->lsrjt.c = dma_alloc_coherent(&ha->pdev->dev, ha->lsrjt.size,
4472 &ha->lsrjt.cdma, GFP_KERNEL);
4473 if (!ha->lsrjt.c) {
4474 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4475 "Alloc failed for nvme fc reject cmd.\n");
4476 goto fail_lsrjt;
4477 }
4478
b2a72ec3 4479 return 0;
e315cd28 4480
875386b9
MR		 4481fail_lsrjt:
4482 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
4483 ha->elsrej.c, ha->elsrej.cdma);
84318a9f
QT		 4484fail_elsrej:
4485 dma_pool_destroy(ha->purex_dma_pool);
4486fail_flt:
4487 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4488 ha->flt, ha->flt_dma);
4489
3f006ac3
MH		 4490fail_flt_buffer:
4491 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4492 ha->sfp_data, ha->sfp_data_dma);
e4e3a2ce
QT		 4493fail_sfp_data:
4494 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4495fail_loop_id_map:
4496 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584 4497fail_async_pd:
9f2475fe
SS		 4498 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma);
4499fail_sf_init_cb:
5ff1d584 4500 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4501fail_ex_init_cb:
4502 kfree(ha->npiv_info);
73208dfd
AC		 4503fail_npiv_info:
4504 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4505 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4506 (*rsp)->ring = NULL;
4507 (*rsp)->dma = 0;
e315cd28 4508fail_rsp_ring:
73208dfd 4509 kfree(*rsp);
6d634067 4510 *rsp = NULL;
e315cd28 4511fail_rsp:
73208dfd
AC		 4512 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4513 sizeof(request_t), (*req)->ring, (*req)->dma);
4514 (*req)->ring = NULL;
4515 (*req)->dma = 0;
e315cd28 4516fail_req_ring:
73208dfd 4517 kfree(*req);
6d634067 4518 *req = NULL;
e315cd28
AC		 4519fail_req:
4520 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4521 ha->ct_sns, ha->ct_sns_dma);
4522 ha->ct_sns = NULL;
4523 ha->ct_sns_dma = 0;
e8711085
AV		 4524fail_free_ms_iocb:
4525 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4526 ha->ms_iocb = NULL;
4527 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4528
4529 if (ha->sns_cmd)
4530 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4531 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4532fail_dma_pool:
50b81275
GM		 4533 if (ql2xenabledif) {
4534 struct dsd_dma *dsd, *nxt;
4535
4536 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4537 list) {
4538 list_del(&dsd->list);
4539 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4540 dsd->dsd_list_dma);
4541 ha->dif_bundle_dma_allocs--;
4542 kfree(dsd);
4543 ha->dif_bundle_kallocs--;
4544 ha->pool.unusable.count--;
4545 }
4546 dma_pool_destroy(ha->dif_bundl_pool);
4547 ha->dif_bundl_pool = NULL;
4548 }
4549
4550fail_dif_bundl_dma_pool:
bad75002 4551 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4552 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4553 ha->fcp_cmnd_dma_pool = NULL;
4554 }
4555fail_dl_dma_pool:
bad75002 4556 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4557 dma_pool_destroy(ha->dl_dma_pool);
4558 ha->dl_dma_pool = NULL;
4559 }
4560fail_s_dma_pool:
e315cd28
AC		 4561 dma_pool_destroy(ha->s_dma_pool);
4562 ha->s_dma_pool = NULL;
e8711085
AV		 4563fail_free_nvram:
4564 kfree(ha->nvram);
4565 ha->nvram = NULL;
a9083016 4566fail_free_ctx_mempool:
75c1d48a 4567 mempool_destroy(ha->ctx_mempool);
a9083016 4568 ha->ctx_mempool = NULL;
e8711085 4569fail_free_srb_mempool:
75c1d48a 4570 mempool_destroy(ha->srb_mempool);
e8711085 4571 ha->srb_mempool = NULL;
e8711085 4572fail_free_gid_list:
642ef983
CD		 4573 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4574 ha->gid_list,
e315cd28 4575 ha->gid_list_dma);
e8711085
AV		 4576 ha->gid_list = NULL;
4577 ha->gid_list_dma = 0;
2d70c103
NB		 4578fail_free_tgt_mem:
4579 qlt_mem_free(ha);
fac28079
QT		 4580fail_free_btree:
4581 btree_destroy32(&ha->host_map);
e315cd28
AC		 4582fail_free_init_cb:
4583 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4584 ha->init_cb_dma);
4585 ha->init_cb = NULL;
4586 ha->init_cb_dma = 0;
430eef03
QT		 4587fail_free_vp_map:
4588 kfree(ha->vp_map);
e288285d 4589 ha->vp_map = NULL;
e8711085 4590fail:
7c3df132
SK		 4591 ql_log(ql_log_fatal, NULL, 0x0030,
4592 "Memory allocation failure.\n");
e8711085 4593 return -ENOMEM;
1da177e4
LT		 4594}
4595
b0d6cabd
HM		 4596int
4597qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4598{
4599 int rval;
d38cb849
QT		 4600 uint16_t size, max_cnt;
4601 uint32_t temp;
b0d6cabd
HM		 4602 struct qla_hw_data *ha = vha->hw;
4603
4604 /* Return if we don't need to alloacate any extended logins */
d38cb849 4605 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400)
b0d6cabd
HM		 4606 return QLA_SUCCESS;
4607
99e1b683
QT		 4608 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4609 return QLA_SUCCESS;
4610
b0d6cabd
HM		 4611 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4612 max_cnt = 0;
4613 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4614 if (rval != QLA_SUCCESS) {
4615 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4616 "Failed to get exlogin status.\n");
4617 return rval;
4618 }
4619
4620 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4621 temp *= size;
4622
4623 if (temp != ha->exlogin_size) {
4624 qla2x00_free_exlogin_buffer(ha);
4625 ha->exlogin_size = temp;
4626
4627 ql_log(ql_log_info, vha, 0xd024,
4628 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4629 max_cnt, size, temp);
4630
4631 ql_log(ql_log_info, vha, 0xd025,
4632 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4633
4634 /* Get consistent memory for extended logins */
4635 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4636 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4637 if (!ha->exlogin_buf) {
4638 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4639 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4640 return -ENOMEM;
4641 }
b0d6cabd
HM		 4642 }
4643
4644 /* Now configure the dma buffer */
4645 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4646 if (rval) {
83548fe2 4647 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4648 "Setup extended login buffer ****FAILED****.\n");
4649 qla2x00_free_exlogin_buffer(ha);
4650 }
4651
4652 return rval;
4653}
4654
4655/*
4656* qla2x00_free_exlogin_buffer
4657*
4658* Input:
4659* ha = adapter block pointer
4660*/
4661void
4662qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4663{
4664 if (ha->exlogin_buf) {
4665 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4666 ha->exlogin_buf, ha->exlogin_buf_dma);
4667 ha->exlogin_buf = NULL;
4668 ha->exlogin_size = 0;
4669 }
4670}
4671
99e1b683
QT		 4672static void
4673qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4674{
4675 u32 temp;
c03d7401 4676 struct init_cb_81xx *icb = (struct init_cb_81xx *)vha->hw->init_cb;
99e1b683
QT		 4677 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4678
d1e3635a
QT		 4679 if (max_cnt > vha->hw->max_exchg)
4680 max_cnt = vha->hw->max_exchg;
4681
99e1b683 4682 if (qla_ini_mode_enabled(vha)) {
0645cb83
QT		 4683 if (vha->ql2xiniexchg > max_cnt)
4684 vha->ql2xiniexchg = max_cnt;
4685
4686 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4687 *ret_cnt = vha->ql2xiniexchg;
99e1b683 4688
99e1b683 4689 } else if (qla_tgt_mode_enabled(vha)) {
0645cb83
QT		 4690 if (vha->ql2xexchoffld > max_cnt) {
4691 vha->ql2xexchoffld = max_cnt;
4692 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4693 }
99e1b683 4694
0645cb83
QT		 4695 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4696 *ret_cnt = vha->ql2xexchoffld;
99e1b683 4697 } else if (qla_dual_mode_enabled(vha)) {
0645cb83 4698 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
99e1b683 4699 if (temp > max_cnt) {
0645cb83
QT		 4700 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4701 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
99e1b683 4702 temp = max_cnt;
0645cb83 4703 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
99e1b683
QT		 4704 }
4705
4706 if (temp > FW_DEF_EXCHANGES_CNT)
4707 *ret_cnt = temp;
4708 }
4709}
4710
2f56a7f1
HM		 4711int
4712qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4713{
4714 int rval;
d1e3635a
QT		 4715 u16 size, max_cnt;
4716 u32 actual_cnt, totsz;
2f56a7f1
HM		 4717 struct qla_hw_data *ha = vha->hw;
4718
99e1b683
QT		 4719 if (!ha->flags.exchoffld_enabled)
4720 return QLA_SUCCESS;
4721
4722 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4723 return QLA_SUCCESS;
4724
2f56a7f1
HM		 4725 max_cnt = 0;
4726 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4727 if (rval != QLA_SUCCESS) {
4728 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4729 "Failed to get exlogin status.\n");
4730 return rval;
4731 }
4732
d1e3635a
QT		 4733 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4734 ql_log(ql_log_info, vha, 0xd014,
4735 "Actual exchange offload count: %d.\n", actual_cnt);
4736
4737 totsz = actual_cnt * size;
2f56a7f1 4738
d1e3635a 4739 if (totsz != ha->exchoffld_size) {
99e1b683 4740 qla2x00_free_exchoffld_buffer(ha);
0645cb83
QT		 4741 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4742 ha->exchoffld_size = 0;
4743 ha->flags.exchoffld_enabled = 0;
4744 return QLA_SUCCESS;
4745 }
4746
d1e3635a 4747 ha->exchoffld_size = totsz;
99e1b683
QT		 4748
4749 ql_log(ql_log_info, vha, 0xd016,
d1e3635a
QT		 4750 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4751 max_cnt, actual_cnt, size, totsz);
99e1b683
QT		 4752
4753 ql_log(ql_log_info, vha, 0xd017,
4754 "Exchange Buffers requested size = 0x%x\n",
4755 ha->exchoffld_size);
4756
4757 /* Get consistent memory for extended logins */
4758 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4759 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4760 if (!ha->exchoffld_buf) {
4761 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
d1e3635a
QT		 4762 "Failed to allocate memory for Exchange Offload.\n");
4763
4764 if (ha->max_exchg >
4765 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4766 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4767 } else if (ha->max_exchg >
4768 (FW_DEF_EXCHANGES_CNT + 512)) {
4769 ha->max_exchg -= 512;
4770 } else {
4771 ha->flags.exchoffld_enabled = 0;
4772 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4773 "Disabling Exchange offload due to lack of memory\n");
4774 }
4775 ha->exchoffld_size = 0;
4776
99e1b683
QT		 4777 return -ENOMEM;
4778 }
0645cb83
QT		 4779 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4780 /* pathological case */
4781 qla2x00_free_exchoffld_buffer(ha);
4782 ha->exchoffld_size = 0;
4783 ha->flags.exchoffld_enabled = 0;
4784 ql_log(ql_log_info, vha, 0xd016,
4785 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4786 ha->exchoffld_size, actual_cnt, size, totsz);
4787 return 0;
2f56a7f1
HM		 4788 }
4789
4790 /* Now configure the dma buffer */
99e1b683 4791 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4792 if (rval) {
4793 ql_log(ql_log_fatal, vha, 0xd02e,
4794 "Setup exchange offload buffer ****FAILED****.\n");
4795 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4796 } else {
4797 /* re-adjust number of target exchange */
4798 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4799
4800 if (qla_ini_mode_enabled(vha))
4801 icb->exchange_count = 0;
4802 else
0645cb83 4803 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
2f56a7f1
HM		 4804 }
4805
4806 return rval;
4807}
4808
4809/*
4810* qla2x00_free_exchoffld_buffer
4811*
4812* Input:
4813* ha = adapter block pointer
4814*/
4815void
4816qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4817{
4818 if (ha->exchoffld_buf) {
4819 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4820 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4821 ha->exchoffld_buf = NULL;
4822 ha->exchoffld_size = 0;
4823 }
4824}
4825
1da177e4 4826/*
e30d1756
MI		 4827* qla2x00_free_fw_dump
4828* Frees fw dump stuff.
1da177e4
LT		 4829*
4830* Input:
7ec0effd 4831* ha = adapter block pointer
1da177e4 4832*/
a824ebb3 4833static void
e30d1756 4834qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4835{
a28d9e4e
JC		 4836 struct fwdt *fwdt = ha->fwdt;
4837 uint j;
4838
df613b96 4839 if (ha->fce)
f73cb695
CD		 4840 dma_free_coherent(&ha->pdev->dev,
4841 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4842
f73cb695
CD		 4843 if (ha->eft)
4844 dma_free_coherent(&ha->pdev->dev,
4845 EFT_SIZE, ha->eft, ha->eft_dma);
4846
efd26171 4847 vfree(ha->fw_dump);
f73cb695 4848
e30d1756
MI		 4849 ha->fce = NULL;
4850 ha->fce_dma = 0;
3cf92f4b 4851 ha->flags.fce_enabled = 0;
e30d1756
MI		 4852 ha->eft = NULL;
4853 ha->eft_dma = 0;
dbe6f492 4854 ha->fw_dumped = false;
61f098dd 4855 ha->fw_dump_cap_flags = 0;
e30d1756 4856 ha->fw_dump_reading = 0;
f73cb695
CD		 4857 ha->fw_dump = NULL;
4858 ha->fw_dump_len = 0;
a28d9e4e
JC		 4859
4860 for (j = 0; j < 2; j++, fwdt++) {
efd26171 4861 vfree(fwdt->template);
a28d9e4e
JC		 4862 fwdt->template = NULL;
4863 fwdt->length = 0;
4864 }
e30d1756
MI		 4865}
4866
4867/*
4868* qla2x00_mem_free
4869* Frees all adapter allocated memory.
4870*
4871* Input:
4872* ha = adapter block pointer.
4873*/
4874static void
4875qla2x00_mem_free(struct qla_hw_data *ha)
4876{
4877 qla2x00_free_fw_dump(ha);
4878
81178772
SK		 4879 if (ha->mctp_dump)
4880 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4881 ha->mctp_dump_dma);
5365bf99 4882 ha->mctp_dump = NULL;
81178772 4883
75c1d48a 4884 mempool_destroy(ha->srb_mempool);
5365bf99 4885 ha->srb_mempool = NULL;
a7a167bf 4886
11bbc1d8
AV		 4887 if (ha->dcbx_tlv)
4888 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4889 ha->dcbx_tlv, ha->dcbx_tlv_dma);
5365bf99 4890 ha->dcbx_tlv = NULL;
11bbc1d8 4891
ce0423f4
AV		 4892 if (ha->xgmac_data)
4893 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4894 ha->xgmac_data, ha->xgmac_data_dma);
5365bf99 4895 ha->xgmac_data = NULL;
ce0423f4 4896
1da177e4
LT		 4897 if (ha->sns_cmd)
4898 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4899 ha->sns_cmd, ha->sns_cmd_dma);
5365bf99
BVA		 4900 ha->sns_cmd = NULL;
4901 ha->sns_cmd_dma = 0;
1da177e4
LT		 4902
4903 if (ha->ct_sns)
4904 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4905 ha->ct_sns, ha->ct_sns_dma);
5365bf99
BVA		 4906 ha->ct_sns = NULL;
4907 ha->ct_sns_dma = 0;
1da177e4 4908
88729e53 4909 if (ha->sfp_data)
e4e3a2ce
QT		 4910 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4911 ha->sfp_data_dma);
5365bf99 4912 ha->sfp_data = NULL;
88729e53 4913
3f006ac3 4914 if (ha->flt)
162b805e
BVA		 4915 dma_free_coherent(&ha->pdev->dev,
4916 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
3f006ac3 4917 ha->flt, ha->flt_dma);
dc035d4e
BVA		 4918 ha->flt = NULL;
4919 ha->flt_dma = 0;
3f006ac3 4920
1da177e4
LT		 4921 if (ha->ms_iocb)
4922 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
5365bf99
BVA		 4923 ha->ms_iocb = NULL;
4924 ha->ms_iocb_dma = 0;
1da177e4 4925
9f2475fe
SS		 4926 if (ha->sf_init_cb)
4927 dma_pool_free(ha->s_dma_pool,
4928 ha->sf_init_cb, ha->sf_init_cb_dma);
4929
b64b0e8f 4930 if (ha->ex_init_cb)
a9083016
GM		 4931 dma_pool_free(ha->s_dma_pool,
4932 ha->ex_init_cb, ha->ex_init_cb_dma);
5365bf99
BVA		 4933 ha->ex_init_cb = NULL;
4934 ha->ex_init_cb_dma = 0;
b64b0e8f 4935
5ff1d584
AV		 4936 if (ha->async_pd)
4937 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5365bf99
BVA		 4938 ha->async_pd = NULL;
4939 ha->async_pd_dma = 0;
5ff1d584 4940
75c1d48a 4941 dma_pool_destroy(ha->s_dma_pool);
5365bf99 4942 ha->s_dma_pool = NULL;
1da177e4 4943
1da177e4 4944 if (ha->gid_list)
642ef983
CD		 4945 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4946 ha->gid_list, ha->gid_list_dma);
5365bf99
BVA		 4947 ha->gid_list = NULL;
4948 ha->gid_list_dma = 0;
1da177e4 4949
097c0639 4950 if (ha->base_qpair && !list_empty(&ha->base_qpair->dsd_list)) {
efeda3bf
QT		 4951 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4952
4953 /* clean up allocated prev pool */
4954 list_for_each_entry_safe(dsd_ptr, tdsd_ptr,
4955 &ha->base_qpair->dsd_list, list) {
4956 dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr,
4957 dsd_ptr->dsd_list_dma);
4958 list_del(&dsd_ptr->list);
4959 kfree(dsd_ptr);
a9083016
GM		 4960 }
4961 }
4962
75c1d48a 4963 dma_pool_destroy(ha->dl_dma_pool);
5365bf99 4964 ha->dl_dma_pool = NULL;
a9083016 4965
75c1d48a 4966 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
5365bf99 4967 ha->fcp_cmnd_dma_pool = NULL;
a9083016 4968
75c1d48a 4969 mempool_destroy(ha->ctx_mempool);
5365bf99 4970 ha->ctx_mempool = NULL;
a9083016 4971
26a77799 4972 if (ql2xenabledif && ha->dif_bundl_pool) {
50b81275
GM		 4973 struct dsd_dma *dsd, *nxt;
4974
4975 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4976 list) {
4977 list_del(&dsd->list);
4978 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4979 dsd->dsd_list_dma);
4980 ha->dif_bundle_dma_allocs--;
4981 kfree(dsd);
4982 ha->dif_bundle_kallocs--;
4983 ha->pool.unusable.count--;
4984 }
4985 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4986 list_del(&dsd->list);
4987 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4988 dsd->dsd_list_dma);
4989 ha->dif_bundle_dma_allocs--;
4990 kfree(dsd);
4991 ha->dif_bundle_kallocs--;
4992 }
4993 }
4994
0b3b6fe2 4995 dma_pool_destroy(ha->dif_bundl_pool);
dc035d4e 4996 ha->dif_bundl_pool = NULL;
50b81275 4997
2d70c103 4998 qlt_mem_free(ha);
fac28079 4999 qla_remove_hostmap(ha);
2d70c103 5000
e315cd28
AC		 5001 if (ha->init_cb)
5002 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 5003 ha->init_cb, ha->init_cb_dma);
84318a9f
QT		 5004
5005 dma_pool_destroy(ha->purex_dma_pool);
5006 ha->purex_dma_pool = NULL;
5007
5008 if (ha->elsrej.c) {
5009 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
5010 ha->elsrej.c, ha->elsrej.cdma);
5011 ha->elsrej.c = NULL;
5012 }
5013
875386b9
MR		 5014 if (ha->lsrjt.c) {
5015 dma_free_coherent(&ha->pdev->dev, ha->lsrjt.size, ha->lsrjt.c,
5016 ha->lsrjt.cdma);
5017 ha->lsrjt.c = NULL;
5018 }
5019
5365bf99
BVA		 5020 ha->init_cb = NULL;
5021 ha->init_cb_dma = 0;
6a2cf8d3 5022
6d634067 5023 vfree(ha->optrom_buffer);
5365bf99 5024 ha->optrom_buffer = NULL;
6d634067 5025 kfree(ha->nvram);
5365bf99 5026 ha->nvram = NULL;
6d634067 5027 kfree(ha->npiv_info);
5365bf99 5028 ha->npiv_info = NULL;
6d634067 5029 kfree(ha->swl);
5365bf99 5030 ha->swl = NULL;
6d634067 5031 kfree(ha->loop_id_map);
9f2475fe
SS		 5032 ha->sf_init_cb = NULL;
5033 ha->sf_init_cb_dma = 0;
6a2cf8d3 5034 ha->loop_id_map = NULL;
430eef03
QT		 5035
5036 kfree(ha->vp_map);
5037 ha->vp_map = NULL;
e315cd28 5038}
1da177e4 5039
421c20b7
BVA		 5040struct scsi_qla_host *qla2x00_create_host(const struct scsi_host_template *sht,
5041 struct qla_hw_data *ha)
e315cd28
AC		 5042{
5043 struct Scsi_Host *host;
5044 struct scsi_qla_host *vha = NULL;
854165f4 5045
e315cd28 5046 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 5047 if (!host) {
7c3df132
SK		 5048 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
5049 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 5050 return NULL;
e315cd28
AC		 5051 }
5052
5053 /* Clear our data area */
5054 vha = shost_priv(host);
5055 memset(vha, 0, sizeof(scsi_qla_host_t));
5056
5057 vha->host = host;
5058 vha->host_no = host->host_no;
5059 vha->hw = ha;
5060
0645cb83
QT		 5061 vha->qlini_mode = ql2x_ini_mode;
5062 vha->ql2xexchoffld = ql2xexchoffld;
5063 vha->ql2xiniexchg = ql2xiniexchg;
5064
e315cd28
AC		 5065 INIT_LIST_HEAD(&vha->vp_fcports);
5066 INIT_LIST_HEAD(&vha->work_list);
5067 INIT_LIST_HEAD(&vha->list);
8b2f5ff3 5068 INIT_LIST_HEAD(&vha->qla_cmd_list);
71cdc079 5069 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 5070 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 5071 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 5072 INIT_LIST_HEAD(&vha->gnl.fcports);
9b3e0f4d 5073 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
e315cd28 5074
576bfde8
JC		 5075 INIT_LIST_HEAD(&vha->purex_list.head);
5076 spin_lock_init(&vha->purex_list.lock);
5077
f999f4c1 5078 spin_lock_init(&vha->work_lock);
8b2f5ff3 5079 spin_lock_init(&vha->cmd_list_lock);
726b8548 5080 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 5081 init_waitqueue_head(&vha->vref_waitq);
84318a9f 5082 qla_enode_init(vha);
7a09e8d9
QT		 5083 qla_edb_init(vha);
5084
f999f4c1 5085
2fdbc65e
BVA		 5086 vha->gnl.size = sizeof(struct get_name_list_extended) *
5087 (ha->max_loop_id + 1);
41dc529a
QT		 5088 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
5089 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
5090 if (!vha->gnl.l) {
83548fe2 5091 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a 5092 "Alloc failed for name list.\n");
26a77799 5093 scsi_host_put(vha->host);
41dc529a
QT		 5094 return NULL;
5095 }
f999f4c1 5096
a4239945
QT		 5097 /* todo: what about ext login? */
5098 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
5099 vha->scan.l = vmalloc(vha->scan.size);
5100 if (!vha->scan.l) {
5101 ql_log(ql_log_fatal, vha, 0xd04a,
5102 "Alloc failed for scan database.\n");
5103 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
5104 vha->gnl.l, vha->gnl.ldma);
26fa656e 5105 vha->gnl.l = NULL;
26a77799 5106 scsi_host_put(vha->host);
a4239945
QT		 5107 return NULL;
5108 }
f352eeb7 5109 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
a4239945 5110
d721b591
NJ		 5111 snprintf(vha->host_str, sizeof(vha->host_str), "%s_%lu",
5112 QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 5113 ql_dbg(ql_dbg_init, vha, 0x0041,
5114 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
5115 vha->host, vha->hw, vha,
5116 dev_name(&(ha->pdev->dev)));
5117
e315cd28 5118 return vha;
1da177e4
LT		 5119}
5120
726b8548 5121struct qla_work_evt *
f999f4c1 5122qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 5123{
5124 struct qla_work_evt *e;
feafb7b1 5125
5a263892
MW		 5126 if (test_bit(UNLOADING, &vha->dpc_flags))
5127 return NULL;
5128
4fb2169d 5129 if (qla_vha_mark_busy(vha))
feafb7b1 5130 return NULL;
0971de7f 5131
f999f4c1 5132 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 5133 if (!e) {
5134 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 5135 return NULL;
feafb7b1 5136 }
0971de7f
AV		 5137
5138 INIT_LIST_HEAD(&e->list);
5139 e->type = type;
5140 e->flags = QLA_EVT_FLAG_FREE;
5141 return e;
5142}
5143
726b8548 5144int
f999f4c1 5145qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 5146{
f999f4c1 5147 unsigned long flags;
9b3e0f4d 5148 bool q = false;
0971de7f 5149
f999f4c1 5150 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 5151 list_add_tail(&e->list, &vha->work_list);
9b3e0f4d
QT		 5152
5153 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
5154 q = true;
5155
f999f4c1 5156 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2 5157
9b3e0f4d
QT		 5158 if (q)
5159 queue_work(vha->hw->wq, &vha->iocb_work);
f999f4c1 5160
0971de7f
AV		 5161 return QLA_SUCCESS;
5162}
5163
5164int
e315cd28 5165qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 5166 u32 data)
5167{
5168 struct qla_work_evt *e;
5169
f999f4c1 5170 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 5171 if (!e)
5172 return QLA_FUNCTION_FAILED;
5173
5174 e->u.aen.code = code;
5175 e->u.aen.data = data;
f999f4c1 5176 return qla2x00_post_work(vha, e);
0971de7f
AV		 5177}
5178
8a659571
AV		 5179int
5180qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
5181{
5182 struct qla_work_evt *e;
5183
f999f4c1 5184 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 5185 if (!e)
5186 return QLA_FUNCTION_FAILED;
5187
5188 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 5189 return qla2x00_post_work(vha, e);
8a659571
AV		 5190}
5191
ac280b67
AV		 5192#define qla2x00_post_async_work(name, type) \
5193int qla2x00_post_async_##name##_work( \
5194 struct scsi_qla_host *vha, \
5195 fc_port_t *fcport, uint16_t *data) \
5196{ \
5197 struct qla_work_evt *e; \
5198 \
5199 e = qla2x00_alloc_work(vha, type); \
5200 if (!e) \
5201 return QLA_FUNCTION_FAILED; \
5202 \
5203 e->u.logio.fcport = fcport; \
5204 if (data) { \
5205 e->u.logio.data[0] = data[0]; \
5206 e->u.logio.data[1] = data[1]; \
5207 } \
6d674927 5208 fcport->flags |= FCF_ASYNC_ACTIVE; \
ac280b67
AV		 5209 return qla2x00_post_work(vha, e); \
5210}
5211
5212qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67 5213qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
5ff1d584 5214qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
11aea16a
QT		 5215qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
5216qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
ac280b67 5217
3420d36c
AV		 5218int
5219qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
5220{
5221 struct qla_work_evt *e;
5222
5223 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
5224 if (!e)
5225 return QLA_FUNCTION_FAILED;
5226
5227 e->u.uevent.code = code;
5228 return qla2x00_post_work(vha, e);
5229}
5230
5231static void
5232qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
5233{
5234 char event_string[40];
5235 char *envp[] = { event_string, NULL };
5236
5237 switch (code) {
5238 case QLA_UEVENT_CODE_FW_DUMP:
250bd009 5239 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
3420d36c
AV		 5240 vha->host_no);
5241 break;
5242 default:
5243 /* do nothing */
5244 break;
5245 }
5246 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5247}
5248
8ae6d9c7
GM		 5249int
5250qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
5251 uint32_t *data, int cnt)
5252{
5253 struct qla_work_evt *e;
5254
5255 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5256 if (!e)
5257 return QLA_FUNCTION_FAILED;
5258
5259 e->u.aenfx.evtcode = evtcode;
5260 e->u.aenfx.count = cnt;
5261 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5262 return qla2x00_post_work(vha, e);
5263}
5264
cd4ed6b4 5265void qla24xx_sched_upd_fcport(fc_port_t *fcport)
726b8548 5266{
cd4ed6b4 5267 unsigned long flags;
726b8548 5268
cd4ed6b4
QT		 5269 if (IS_SW_RESV_ADDR(fcport->d_id))
5270 return;
726b8548 5271
cd4ed6b4
QT		 5272 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5273 if (fcport->disc_state == DSC_UPD_FCPORT) {
5274 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5275 return;
5276 }
5277 fcport->jiffies_at_registration = jiffies;
5278 fcport->sec_since_registration = 0;
5279 fcport->next_disc_state = DSC_DELETED;
27258a57 5280 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
cd4ed6b4
QT		 5281 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5282
5283 queue_work(system_unbound_wq, &fcport->reg_work);
726b8548
QT		 5284}
5285
5286static
5287void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5288{
5289 unsigned long flags;
b5d15312 5290 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 5291 struct qlt_plogi_ack_t *pla =
5292 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 5293 uint8_t free_fcport = 0;
726b8548 5294
9cd883f0
QT		 5295 ql_dbg(ql_dbg_disc, vha, 0xffff,
5296 "%s %d %8phC enter\n",
5297 __func__, __LINE__, e->u.new_sess.port_name);
5298
726b8548
QT		 5299 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5300 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5301 if (fcport) {
5302 fcport->d_id = e->u.new_sess.id;
5303 if (pla) {
5304 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
9b3e0f4d
QT		 5305 memcpy(fcport->node_name,
5306 pla->iocb.u.isp24.u.plogi.node_name,
5307 WWN_SIZE);
726b8548
QT		 5308 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5309 /* we took an extra ref_count to prevent PLOGI ACK when
5310 * fcport/sess has not been created.
5311 */
5312 pla->ref_count--;
5313 }
5314 } else {
b5d15312 5315 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 5316 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5317 if (fcport) {
5318 fcport->d_id = e->u.new_sess.id;
726b8548
QT		 5319 fcport->flags |= FCF_FABRIC_DEVICE;
5320 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
dbf1f53c 5321 fcport->tgt_short_link_down_cnt = 0;
33b28357 5322
726b8548
QT		 5323 memcpy(fcport->port_name, e->u.new_sess.port_name,
5324 WWN_SIZE);
7f2a398d 5325
84ed362a 5326 fcport->fc4_type = e->u.new_sess.fc4_type;
f8844457
QT		 5327 if (NVME_PRIORITY(vha->hw, fcport))
5328 fcport->do_prli_nvme = 1;
5329 else
5330 fcport->do_prli_nvme = 0;
5331
84ed362a 5332 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) {
94eda271
AE		 5333 fcport->dm_login_expire = jiffies +
5334 QLA_N2N_WAIT_TIME * HZ;
84ed362a 5335 fcport->fc4_type = FS_FC4TYPE_FCP;
7f2a398d 5336 fcport->n2n_flag = 1;
84ed362a
MH		 5337 if (vha->flags.nvme_enabled)
5338 fcport->fc4_type |= FS_FC4TYPE_NVME;
5339 }
7f2a398d 5340
b5d15312
QT		 5341 } else {
5342 ql_dbg(ql_dbg_disc, vha, 0xffff,
5343 "%s %8phC mem alloc fail.\n",
5344 __func__, e->u.new_sess.port_name);
5345
1df627b4
BVA		 5346 if (pla) {
5347 list_del(&pla->list);
b5d15312 5348 kmem_cache_free(qla_tgt_plogi_cachep, pla);
1df627b4 5349 }
b5d15312
QT		 5350 return;
5351 }
5352
5353 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a4239945 5354 /* search again to make sure no one else got ahead */
b5d15312
QT		 5355 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5356 e->u.new_sess.port_name, 1);
5357 if (tfcp) {
5358 /* should rarily happen */
5359 ql_dbg(ql_dbg_disc, vha, 0xffff,
5360 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5361 __func__, tfcp->port_name, tfcp->disc_state,
5362 tfcp->fw_login_state);
5363
5364 free_fcport = 1;
5365 } else {
726b8548
QT		 5366 list_add_tail(&fcport->list, &vha->vp_fcports);
5367
19759033
QT		 5368 }
5369 if (pla) {
5370 qlt_plogi_ack_link(vha, pla, fcport,
5371 QLT_PLOGI_LINK_SAME_WWN);
5372 pla->ref_count--;
726b8548
QT		 5373 }
5374 }
5375 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5376
5377 if (fcport) {
a4239945
QT		 5378 fcport->id_changed = 1;
5379 fcport->scan_state = QLA_FCPORT_FOUND;
8b5292bc 5380 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
a4239945
QT		 5381 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5382
5ef696aa 5383 if (pla) {
9cd883f0
QT		 5384 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5385 u16 wd3_lo;
5386
5387 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5388 fcport->local = 0;
5389 fcport->loop_id =
5390 le16_to_cpu(
5391 pla->iocb.u.isp24.nport_handle);
5392 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5393 wd3_lo =
5394 le16_to_cpu(
5395 pla->iocb.u.isp24.u.prli.wd3_lo);
5396
5397 if (wd3_lo & BIT_7)
5398 fcport->conf_compl_supported = 1;
5399
5400 if ((wd3_lo & BIT_4) == 0)
5401 fcport->port_type = FCT_INITIATOR;
5402 else
5403 fcport->port_type = FCT_TARGET;
5404 }
726b8548 5405 qlt_plogi_ack_unref(vha, pla);
5ef696aa 5406 } else {
1c6cacf4
HR		 5407 fc_port_t *dfcp = NULL;
5408
5ef696aa
QT		 5409 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5410 tfcp = qla2x00_find_fcport_by_nportid(vha,
5411 &e->u.new_sess.id, 1);
5412 if (tfcp && (tfcp != fcport)) {
5413 /*
5414 * We have a conflict fcport with same NportID.
5415 */
5416 ql_dbg(ql_dbg_disc, vha, 0xffff,
5417 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5418 __func__, tfcp->port_name, tfcp->disc_state,
5419 tfcp->fw_login_state);
5420
5421 switch (tfcp->disc_state) {
5422 case DSC_DELETED:
5423 break;
5424 case DSC_DELETE_PEND:
5425 fcport->login_pause = 1;
5426 tfcp->conflict = fcport;
5427 break;
5428 default:
5429 fcport->login_pause = 1;
5430 tfcp->conflict = fcport;
1c6cacf4 5431 dfcp = tfcp;
5ef696aa
QT		 5432 break;
5433 }
5434 }
5435 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1c6cacf4
HR		 5436 if (dfcp)
5437 qlt_schedule_sess_for_deletion(tfcp);
a4239945 5438
8777e431 5439 if (N2N_TOPO(vha->hw)) {
f3f1938b
QT		 5440 fcport->flags &= ~FCF_FABRIC_DEVICE;
5441 fcport->keep_nport_handle = 1;
8777e431 5442 if (vha->flags.nvme_enabled) {
84ed362a
MH		 5443 fcport->fc4_type =
5444 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP);
8777e431
QT		 5445 fcport->n2n_flag = 1;
5446 }
5447 fcport->fw_login_state = 0;
11efe875
QT		 5448
5449 schedule_delayed_work(&vha->scan.scan_work, 5);
8777e431
QT		 5450 } else {
5451 qla24xx_fcport_handle_login(vha, fcport);
5452 }
5ef696aa 5453 }
726b8548 5454 }
b5d15312
QT		 5455
5456 if (free_fcport) {
5457 qla2x00_free_fcport(fcport);
1df627b4
BVA		 5458 if (pla) {
5459 list_del(&pla->list);
b5d15312 5460 kmem_cache_free(qla_tgt_plogi_cachep, pla);
1df627b4 5461 }
b5d15312 5462 }
726b8548
QT		 5463}
5464
e374f9f5
QT		 5465static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5466{
5467 struct srb *sp = e->u.iosb.sp;
5468 int rval;
5469
5470 rval = qla2x00_start_sp(sp);
5471 if (rval != QLA_SUCCESS) {
5472 ql_dbg(ql_dbg_disc, vha, 0x2043,
5473 "%s: %s: Re-issue IOCB failed (%d).\n",
5474 __func__, sp->name, rval);
5475 qla24xx_sp_unmap(vha, sp);
5476 }
5477}
5478
ac280b67 5479void
e315cd28 5480qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 5481{
f999f4c1
AV		 5482 struct qla_work_evt *e, *tmp;
5483 unsigned long flags;
5484 LIST_HEAD(work);
80676d05 5485 int rc;
0971de7f 5486
f999f4c1
AV		 5487 spin_lock_irqsave(&vha->work_lock, flags);
5488 list_splice_init(&vha->work_list, &work);
5489 spin_unlock_irqrestore(&vha->work_lock, flags);
5490
5491 list_for_each_entry_safe(e, tmp, &work, list) {
80676d05 5492 rc = QLA_SUCCESS;
0971de7f
AV		 5493 switch (e->type) {
5494 case QLA_EVT_AEN:
e315cd28 5495 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 5496 e->u.aen.code, e->u.aen.data);
5497 break;
8a659571
AV		 5498 case QLA_EVT_IDC_ACK:
5499 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5500 break;
ac280b67
AV		 5501 case QLA_EVT_ASYNC_LOGIN:
5502 qla2x00_async_login(vha, e->u.logio.fcport,
5503 e->u.logio.data);
5504 break;
ac280b67 5505 case QLA_EVT_ASYNC_LOGOUT:
80676d05 5506 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
ac280b67 5507 break;
5ff1d584
AV		 5508 case QLA_EVT_ASYNC_ADISC:
5509 qla2x00_async_adisc(vha, e->u.logio.fcport,
5510 e->u.logio.data);
5511 break;
3420d36c
AV		 5512 case QLA_EVT_UEVENT:
5513 qla2x00_uevent_emit(vha, e->u.uevent.code);
5514 break;
8ae6d9c7
GM		 5515 case QLA_EVT_AENFX:
5516 qlafx00_process_aen(vha, e);
5517 break;
e374f9f5
QT		 5518 case QLA_EVT_UNMAP:
5519 qla24xx_sp_unmap(vha, e->u.iosb.sp);
726b8548 5520 break;
9b3e0f4d
QT		 5521 case QLA_EVT_RELOGIN:
5522 qla2x00_relogin(vha);
5523 break;
726b8548
QT		 5524 case QLA_EVT_NEW_SESS:
5525 qla24xx_create_new_sess(vha, e);
5526 break;
5527 case QLA_EVT_GPDB:
5528 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5529 e->u.fcport.opt);
5530 break;
a5d42f4c
DG		 5531 case QLA_EVT_PRLI:
5532 qla24xx_async_prli(vha, e->u.fcport.fcport);
5533 break;
726b8548
QT		 5534 case QLA_EVT_GPSC:
5535 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5536 break;
726b8548
QT		 5537 case QLA_EVT_GNL:
5538 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5539 break;
5540 case QLA_EVT_NACK:
5541 qla24xx_do_nack_work(vha, e);
5542 break;
11aea16a 5543 case QLA_EVT_ASYNC_PRLO:
80676d05 5544 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
11aea16a
QT		 5545 break;
5546 case QLA_EVT_ASYNC_PRLO_DONE:
5547 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5548 e->u.logio.data);
5549 break;
beafd692
QT		 5550 case QLA_EVT_SCAN_CMD:
5551 qla_fab_async_scan(vha, e->u.iosb.sp);
a4239945 5552 break;
beafd692
QT		 5553 case QLA_EVT_SCAN_FINISH:
5554 qla_fab_scan_finish(vha, e->u.iosb.sp);
a4239945 5555 break;
a4239945
QT		 5556 case QLA_EVT_GFPNID:
5557 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5558 break;
e374f9f5
QT		 5559 case QLA_EVT_SP_RETRY:
5560 qla_sp_retry(vha, e);
cc28e0ac
QT		 5561 break;
5562 case QLA_EVT_IIDMA:
5563 qla_do_iidma_work(vha, e->u.fcport.fcport);
5564 break;
8777e431
QT		 5565 case QLA_EVT_ELS_PLOGI:
5566 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
881eb861 5567 e->u.fcport.fcport);
8777e431 5568 break;
dd30706e 5569 case QLA_EVT_SA_REPLACE:
0b3f3143 5570 rc = qla24xx_issue_sa_replace_iocb(vha, e);
dd30706e 5571 break;
0971de7f 5572 }
80676d05
QT		 5573
5574 if (rc == EAGAIN) {
5575 /* put 'work' at head of 'vha->work_list' */
5576 spin_lock_irqsave(&vha->work_lock, flags);
5577 list_splice(&work, &vha->work_list);
5578 spin_unlock_irqrestore(&vha->work_lock, flags);
5579 break;
5580 }
5581 list_del_init(&e->list);
0971de7f
AV		 5582 if (e->flags & QLA_EVT_FLAG_FREE)
5583 kfree(e);
feafb7b1
AE		 5584
5585 /* For each work completed decrement vha ref count */
5586 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 5587 }
e315cd28 5588}
f999f4c1 5589
9b3e0f4d
QT		 5590int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5591{
5592 struct qla_work_evt *e;
5593
5594 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5595
5596 if (!e) {
5597 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5598 return QLA_FUNCTION_FAILED;
5599 }
5600
5601 return qla2x00_post_work(vha, e);
5602}
5603
e315cd28
AC		 5604/* Relogins all the fcports of a vport
5605 * Context: dpc thread
5606 */
5607void qla2x00_relogin(struct scsi_qla_host *vha)
5608{
5609 fc_port_t *fcport;
23dd98a6 5610 int status, relogin_needed = 0;
726b8548 5611 struct event_arg ea;
e315cd28
AC		 5612
5613 list_for_each_entry(fcport, &vha->vp_fcports, list) {
9cd883f0
QT		 5614 /*
5615 * If the port is not ONLINE then try to login
5616 * to it if we haven't run out of retries.
5617 */
5ff1d584 5618 if (atomic_read(&fcport->state) != FCS_ONLINE &&
23dd98a6
QT		 5619 fcport->login_retry) {
5620 if (fcport->scan_state != QLA_FCPORT_FOUND ||
9efea843 5621 fcport->disc_state == DSC_LOGIN_AUTH_PEND ||
23dd98a6
QT		 5622 fcport->disc_state == DSC_LOGIN_COMPLETE)
5623 continue;
e315cd28 5624
23dd98a6
QT		 5625 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5626 fcport->disc_state == DSC_DELETE_PEND) {
5627 relogin_needed = 1;
5628 } else {
5629 if (vha->hw->current_topology != ISP_CFG_NL) {
5630 memset(&ea, 0, sizeof(ea));
23dd98a6 5631 ea.fcport = fcport;
897def20 5632 qla24xx_handle_relogin_event(vha, &ea);
8ad4be3d
AE		 5633 } else if (vha->hw->current_topology ==
5634 ISP_CFG_NL &&
5635 IS_QLA2XXX_MIDTYPE(vha->hw)) {
5636 (void)qla24xx_fcport_handle_login(vha,
5637 fcport);
23dd98a6
QT		 5638 } else if (vha->hw->current_topology ==
5639 ISP_CFG_NL) {
5640 fcport->login_retry--;
5641 status =
5642 qla2x00_local_device_login(vha,
5643 fcport);
5644 if (status == QLA_SUCCESS) {
5645 fcport->old_loop_id =
5646 fcport->loop_id;
5647 ql_dbg(ql_dbg_disc, vha, 0x2003,
5648 "Port login OK: logged in ID 0x%x.\n",
5649 fcport->loop_id);
5650 qla2x00_update_fcport
5651 (vha, fcport);
5652 } else if (status == 1) {
5653 set_bit(RELOGIN_NEEDED,
5654 &vha->dpc_flags);
5655 /* retry the login again */
5656 ql_dbg(ql_dbg_disc, vha, 0x2007,
5657 "Retrying %d login again loop_id 0x%x.\n",
5658 fcport->login_retry,
5659 fcport->loop_id);
5660 } else {
5661 fcport->login_retry = 0;
5662 }
e315cd28 5663
23dd98a6
QT		 5664 if (fcport->login_retry == 0 &&
5665 status != QLA_SUCCESS)
5666 qla2x00_clear_loop_id(fcport);
5667 }
e315cd28 5668 }
e315cd28
AC		 5669 }
5670 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5671 break;
0971de7f 5672 }
9b3e0f4d 5673
23dd98a6
QT		 5674 if (relogin_needed)
5675 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5676
9b3e0f4d
QT		 5677 ql_dbg(ql_dbg_disc, vha, 0x400e,
5678 "Relogin end.\n");
0971de7f
AV		 5679}
5680
7d613ac6
SV		 5681/* Schedule work on any of the dpc-workqueues */
5682void
5683qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5684{
5685 struct qla_hw_data *ha = base_vha->hw;
5686
5687 switch (work_code) {
5688 case MBA_IDC_AEN: /* 0x8200 */
5689 if (ha->dpc_lp_wq)
5690 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5691 break;
5692
5693 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5694 if (!ha->flags.nic_core_reset_hdlr_active) {
5695 if (ha->dpc_hp_wq)
5696 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5697 } else
5698 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5699 "NIC Core reset is already active. Skip "
5700 "scheduling it again.\n");
5701 break;
5702 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5703 if (ha->dpc_hp_wq)
5704 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5705 break;
5706 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5707 if (ha->dpc_hp_wq)
5708 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5709 break;
5710 default:
5711 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 5712 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 5713 }
5714
5715 return;
5716}
5717
5718/* Work: Perform NIC Core Unrecoverable state handling */
5719void
5720qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5721{
5722 struct qla_hw_data *ha =
2ad1b67c 5723 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 5724 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5725 uint32_t dev_state = 0;
5726
5727 qla83xx_idc_lock(base_vha, 0);
5728 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5729 qla83xx_reset_ownership(base_vha);
5730 if (ha->flags.nic_core_reset_owner) {
5731 ha->flags.nic_core_reset_owner = 0;
5732 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5733 QLA8XXX_DEV_FAILED);
5734 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5735 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5736 }
5737 qla83xx_idc_unlock(base_vha, 0);
5738}
5739
5740/* Work: Execute IDC state handler */
5741void
5742qla83xx_idc_state_handler_work(struct work_struct *work)
5743{
5744 struct qla_hw_data *ha =
2ad1b67c 5745 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 5746 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5747 uint32_t dev_state = 0;
5748
5749 qla83xx_idc_lock(base_vha, 0);
5750 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5751 if (dev_state == QLA8XXX_DEV_FAILED ||
5752 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5753 qla83xx_idc_state_handler(base_vha);
5754 qla83xx_idc_unlock(base_vha, 0);
5755}
5756
fa492630 5757static int
7d613ac6
SV		 5758qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5759{
5760 int rval = QLA_SUCCESS;
5761 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5762 uint32_t heart_beat_counter1, heart_beat_counter2;
5763
5764 do {
5765 if (time_after(jiffies, heart_beat_wait)) {
5766 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5767 "Nic Core f/w is not alive.\n");
5768 rval = QLA_FUNCTION_FAILED;
5769 break;
5770 }
5771
5772 qla83xx_idc_lock(base_vha, 0);
5773 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5774 &heart_beat_counter1);
5775 qla83xx_idc_unlock(base_vha, 0);
5776 msleep(100);
5777 qla83xx_idc_lock(base_vha, 0);
5778 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5779 &heart_beat_counter2);
5780 qla83xx_idc_unlock(base_vha, 0);
5781 } while (heart_beat_counter1 == heart_beat_counter2);
5782
5783 return rval;
5784}
5785
5786/* Work: Perform NIC Core Reset handling */
5787void
5788qla83xx_nic_core_reset_work(struct work_struct *work)
5789{
5790 struct qla_hw_data *ha =
5791 container_of(work, struct qla_hw_data, nic_core_reset);
5792 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5793 uint32_t dev_state = 0;
5794
81178772
SK		 5795 if (IS_QLA2031(ha)) {
5796 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5797 ql_log(ql_log_warn, base_vha, 0xb081,
5798 "Failed to dump mctp\n");
5799 return;
5800 }
5801
7d613ac6
SV		 5802 if (!ha->flags.nic_core_reset_hdlr_active) {
5803 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5804 qla83xx_idc_lock(base_vha, 0);
5805 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5806 &dev_state);
5807 qla83xx_idc_unlock(base_vha, 0);
5808 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5809 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5810 "Nic Core f/w is alive.\n");
5811 return;
5812 }
5813 }
5814
5815 ha->flags.nic_core_reset_hdlr_active = 1;
5816 if (qla83xx_nic_core_reset(base_vha)) {
5817 /* NIC Core reset failed. */
5818 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5819 "NIC Core reset failed.\n");
5820 }
5821 ha->flags.nic_core_reset_hdlr_active = 0;
5822 }
5823}
5824
5825/* Work: Handle 8200 IDC aens */
5826void
5827qla83xx_service_idc_aen(struct work_struct *work)
5828{
5829 struct qla_hw_data *ha =
5830 container_of(work, struct qla_hw_data, idc_aen);
5831 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5832 uint32_t dev_state, idc_control;
5833
5834 qla83xx_idc_lock(base_vha, 0);
5835 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5836 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5837 qla83xx_idc_unlock(base_vha, 0);
5838 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5839 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5840 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5841 "Application requested NIC Core Reset.\n");
5842 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5843 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5844 QLA_SUCCESS) {
5845 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5846 "Other protocol driver requested NIC Core Reset.\n");
5847 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5848 }
5849 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5850 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5851 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5852 }
5853}
5854
4f6a57c2
AD		 5855/*
5856 * Control the frequency of IDC lock retries
5857 */
5858#define QLA83XX_WAIT_LOGIC_MS 100
7d613ac6 5859
fa492630 5860static int
7d613ac6
SV		 5861qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5862{
5863 int rval;
5864 uint32_t data;
5865 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5866 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5867 struct qla_hw_data *ha = base_vha->hw;
bd432bb5 5868
6c315553
SK		 5869 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5870 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5871
5872 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5873 if (rval)
5874 return rval;
5875
5876 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5877 return QLA_SUCCESS;
5878 } else {
5879 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5880 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5881 data);
5882 if (rval)
5883 return rval;
5884
5885 msleep(200);
5886
5887 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5888 &data);
5889 if (rval)
5890 return rval;
5891
5892 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5893 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5894 ~(idc_lck_rcvry_stage_mask));
5895 rval = qla83xx_wr_reg(base_vha,
5896 QLA83XX_IDC_LOCK_RECOVERY, data);
5897 if (rval)
5898 return rval;
5899
5900 /* Forcefully perform IDC UnLock */
5901 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5902 &data);
5903 if (rval)
5904 return rval;
5905 /* Clear lock-id by setting 0xff */
5906 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5907 0xff);
5908 if (rval)
5909 return rval;
5910 /* Clear lock-recovery by setting 0x0 */
5911 rval = qla83xx_wr_reg(base_vha,
5912 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5913 if (rval)
5914 return rval;
5915 } else
5916 return QLA_SUCCESS;
5917 }
5918
5919 return rval;
5920}
5921
fa492630 5922static int
7d613ac6
SV		 5923qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5924{
5925 int rval = QLA_SUCCESS;
5926 uint32_t o_drv_lockid, n_drv_lockid;
5927 unsigned long lock_recovery_timeout;
5928
5929 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5930retry_lockid:
5931 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5932 if (rval)
5933 goto exit;
5934
5935 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5936 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5937 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5938 return QLA_SUCCESS;
5939 else
5940 return QLA_FUNCTION_FAILED;
5941 }
5942
5943 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5944 if (rval)
5945 goto exit;
5946
5947 if (o_drv_lockid == n_drv_lockid) {
4f6a57c2 5948 msleep(QLA83XX_WAIT_LOGIC_MS);
7d613ac6
SV		 5949 goto retry_lockid;
5950 } else
5951 return QLA_SUCCESS;
5952
5953exit:
5954 return rval;
5955}
5956
4f6a57c2
AD		 5957/*
5958 * Context: task, can sleep
5959 */
7d613ac6
SV		 5960void
5961qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5962{
7d613ac6 5963 uint32_t data;
6c315553 5964 uint32_t lock_owner;
7d613ac6
SV		 5965 struct qla_hw_data *ha = base_vha->hw;
5966
4f6a57c2
AD		 5967 might_sleep();
5968
7d613ac6
SV		 5969 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5970retry_lock:
5971 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5972 == QLA_SUCCESS) {
5973 if (data) {
5974 /* Setting lock-id to our function-number */
5975 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5976 ha->portnum);
5977 } else {
6c315553
SK		 5978 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5979 &lock_owner);
7d613ac6 5980 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5981 "Failed to acquire IDC lock, acquired by %d, "
5982 "retrying...\n", lock_owner);
7d613ac6
SV		 5983
5984 /* Retry/Perform IDC-Lock recovery */
5985 if (qla83xx_idc_lock_recovery(base_vha)
5986 == QLA_SUCCESS) {
4f6a57c2 5987 msleep(QLA83XX_WAIT_LOGIC_MS);
7d613ac6
SV		 5988 goto retry_lock;
5989 } else
5990 ql_log(ql_log_warn, base_vha, 0xb075,
5991 "IDC Lock recovery FAILED.\n");
5992 }
5993
5994 }
5995
5996 return;
7d613ac6
SV		 5997}
5998
4879237c
JC		 5999static bool
6000qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha,
6001 struct purex_entry_24xx *purex)
6002{
6003 char fwstr[16];
6004 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0];
84f7d2e7 6005 struct port_database_24xx *pdb;
4879237c
JC		 6006
6007 /* Domain Controller is always logged-out. */
6008 /* if RDP request is not from Domain Controller: */
6009 if (sid != 0xfffc01)
6010 return false;
6011
6012 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid);
6013
84f7d2e7
HM		 6014 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL);
6015 if (!pdb) {
6016 ql_dbg(ql_dbg_init, vha, 0x0181,
6017 "%s: Failed allocate pdb\n", __func__);
7ffa5b93
BVA		 6018 } else if (qla24xx_get_port_database(vha,
6019 le16_to_cpu(purex->nport_handle), pdb)) {
84f7d2e7
HM		 6020 ql_dbg(ql_dbg_init, vha, 0x0181,
6021 "%s: Failed get pdb sid=%x\n", __func__, sid);
6022 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE &&
6023 pdb->current_login_state != PDS_PRLI_COMPLETE) {
6024 ql_dbg(ql_dbg_init, vha, 0x0181,
6025 "%s: Port not logged in sid=%#x\n", __func__, sid);
6026 } else {
6027 /* RDP request is from logged in port */
6028 kfree(pdb);
6029 return false;
6030 }
6031 kfree(pdb);
6032
4879237c
JC		 6033 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr));
6034 fwstr[strcspn(fwstr, " ")] = 0;
6035 /* if FW version allows RDP response length upto 2048 bytes: */
6036 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0)
6037 return false;
6038
6039 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr);
6040
6041 /* RDP response length is to be reduced to maximum 256 bytes */
6042 return true;
6043}
6044
d83a80ee
JC		 6045/*
6046 * Function Name: qla24xx_process_purex_iocb
6047 *
6048 * Description:
6049 * Prepare a RDP response and send to Fabric switch
6050 *
6051 * PARAMETERS:
6052 * vha: SCSI qla host
6053 * purex: RDP request received by HBA
6054 */
62e9dd17
SS		 6055void qla24xx_process_purex_rdp(struct scsi_qla_host *vha,
6056 struct purex_item *item)
d83a80ee
JC		 6057{
6058 struct qla_hw_data *ha = vha->hw;
62e9dd17
SS		 6059 struct purex_entry_24xx *purex =
6060 (struct purex_entry_24xx *)&item->iocb;
d83a80ee
JC		 6061 dma_addr_t rsp_els_dma;
6062 dma_addr_t rsp_payload_dma;
6063 dma_addr_t stat_dma;
d83a80ee
JC		 6064 dma_addr_t sfp_dma;
6065 struct els_entry_24xx *rsp_els = NULL;
6066 struct rdp_rsp_payload *rsp_payload = NULL;
6067 struct link_statistics *stat = NULL;
d83a80ee
JC		 6068 uint8_t *sfp = NULL;
6069 uint16_t sfp_flags = 0;
4879237c 6070 uint rsp_payload_length = sizeof(*rsp_payload);
576bfde8 6071 int rval;
d83a80ee
JC		 6072
6073 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180,
6074 "%s: Enter\n", __func__);
6075
6076 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181,
6077 "-------- ELS REQ -------\n");
6078 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182,
ab053c09 6079 purex, sizeof(*purex));
d83a80ee 6080
4879237c
JC		 6081 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) {
6082 rsp_payload_length =
6083 offsetof(typeof(*rsp_payload), optical_elmt_desc);
6084 ql_dbg(ql_dbg_init, vha, 0x0181,
6085 "Reducing RSP payload length to %u bytes...\n",
6086 rsp_payload_length);
6087 }
6088
d83a80ee
JC		 6089 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6090 &rsp_els_dma, GFP_KERNEL);
09e382bc
JC		 6091 if (!rsp_els) {
6092 ql_log(ql_log_warn, vha, 0x0183,
6093 "Failed allocate dma buffer ELS RSP.\n");
d83a80ee 6094 goto dealloc;
09e382bc 6095 }
d83a80ee
JC		 6096
6097 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6098 &rsp_payload_dma, GFP_KERNEL);
09e382bc
JC		 6099 if (!rsp_payload) {
6100 ql_log(ql_log_warn, vha, 0x0184,
6101 "Failed allocate dma buffer ELS RSP payload.\n");
d83a80ee 6102 goto dealloc;
09e382bc 6103 }
d83a80ee
JC		 6104
6105 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6106 &sfp_dma, GFP_KERNEL);
6107
6108 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat),
6109 &stat_dma, GFP_KERNEL);
6110
d83a80ee 6111 /* Prepare Response IOCB */
d83a80ee
JC		 6112 rsp_els->entry_type = ELS_IOCB_TYPE;
6113 rsp_els->entry_count = 1;
6114 rsp_els->sys_define = 0;
6115 rsp_els->entry_status = 0;
6116 rsp_els->handle = 0;
6117 rsp_els->nport_handle = purex->nport_handle;
7ffa5b93 6118 rsp_els->tx_dsd_count = cpu_to_le16(1);
d83a80ee
JC		 6119 rsp_els->vp_index = purex->vp_idx;
6120 rsp_els->sof_type = EST_SOFI3;
6121 rsp_els->rx_xchg_address = purex->rx_xchg_addr;
6122 rsp_els->rx_dsd_count = 0;
6123 rsp_els->opcode = purex->els_frame_payload[0];
6124
09e382bc
JC		 6125 rsp_els->d_id[0] = purex->s_id[0];
6126 rsp_els->d_id[1] = purex->s_id[1];
6127 rsp_els->d_id[2] = purex->s_id[2];
d83a80ee 6128
7ffa5b93 6129 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC);
d83a80ee 6130 rsp_els->rx_byte_count = 0;
4879237c 6131 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length);
d83a80ee
JC		 6132
6133 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address);
6134 rsp_els->tx_len = rsp_els->tx_byte_count;
6135
6136 rsp_els->rx_address = 0;
6137 rsp_els->rx_len = 0;
6138
d83a80ee
JC		 6139 /* Prepare Response Payload */
6140 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */
7ffa5b93
BVA		 6141 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) -
6142 sizeof(rsp_payload->hdr));
d83a80ee
JC		 6143
6144 /* Link service Request Info Descriptor */
6145 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1);
6146 rsp_payload->ls_req_info_desc.desc_len =
6147 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc));
6148 rsp_payload->ls_req_info_desc.req_payload_word_0 =
6149 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6150
6151 /* Link service Request Info Descriptor 2 */
6152 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1);
6153 rsp_payload->ls_req_info_desc2.desc_len =
6154 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2));
6155 rsp_payload->ls_req_info_desc2.req_payload_word_0 =
6156 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6157
770538c3
QT		 6158
6159 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000);
6160 rsp_payload->sfp_diag_desc.desc_len =
6161 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc));
6162
d83a80ee
JC		 6163 if (sfp) {
6164 /* SFP Flags */
6165 memset(sfp, 0, SFP_RTDI_LEN);
6166 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0);
6167 if (!rval) {
6168 /* SFP Flags bits 3-0: Port Tx Laser Type */
6169 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5))
6170 sfp_flags |= BIT_0; /* short wave */
6171 else if (sfp[0] & BIT_1)
6172 sfp_flags |= BIT_1; /* long wave 1310nm */
6173 else if (sfp[1] & BIT_4)
6174 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */
6175 }
6176
6177 /* SFP Type */
6178 memset(sfp, 0, SFP_RTDI_LEN);
6179 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0);
6180 if (!rval) {
6181 sfp_flags |= BIT_4; /* optical */
6182 if (sfp[0] == 0x3)
6183 sfp_flags |= BIT_6; /* sfp+ */
6184 }
6185
770538c3
QT		 6186 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags);
6187
d83a80ee
JC		 6188 /* SFP Diagnostics */
6189 memset(sfp, 0, SFP_RTDI_LEN);
6190 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0);
770538c3 6191 if (!rval) {
7ffa5b93 6192 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
d83a80ee
JC		 6193 rsp_payload->sfp_diag_desc.temperature = trx[0];
6194 rsp_payload->sfp_diag_desc.vcc = trx[1];
6195 rsp_payload->sfp_diag_desc.tx_bias = trx[2];
6196 rsp_payload->sfp_diag_desc.tx_power = trx[3];
6197 rsp_payload->sfp_diag_desc.rx_power = trx[4];
d83a80ee
JC		 6198 }
6199 }
6200
6201 /* Port Speed Descriptor */
6202 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001);
6203 rsp_payload->port_speed_desc.desc_len =
6204 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc));
6205 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16(
d68930ba 6206 qla25xx_fdmi_port_speed_capability(ha));
d83a80ee 6207 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16(
d68930ba 6208 qla25xx_fdmi_port_speed_currently(ha));
d83a80ee 6209
770538c3
QT		 6210 /* Link Error Status Descriptor */
6211 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002);
6212 rsp_payload->ls_err_desc.desc_len =
6213 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc));
6214
d83a80ee
JC		 6215 if (stat) {
6216 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0);
6217 if (!rval) {
d83a80ee 6218 rsp_payload->ls_err_desc.link_fail_cnt =
7ffa5b93 6219 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt));
d83a80ee 6220 rsp_payload->ls_err_desc.loss_sync_cnt =
7ffa5b93 6221 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt));
d83a80ee 6222 rsp_payload->ls_err_desc.loss_sig_cnt =
7ffa5b93 6223 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt));
d83a80ee 6224 rsp_payload->ls_err_desc.prim_seq_err_cnt =
7ffa5b93 6225 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt));
d83a80ee 6226 rsp_payload->ls_err_desc.inval_xmit_word_cnt =
7ffa5b93 6227 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt));
d83a80ee 6228 rsp_payload->ls_err_desc.inval_crc_cnt =
7ffa5b93 6229 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt));
d83a80ee
JC		 6230 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6;
6231 }
6232 }
6233
6234 /* Portname Descriptor */
6235 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003);
6236 rsp_payload->port_name_diag_desc.desc_len =
6237 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc));
6238 memcpy(rsp_payload->port_name_diag_desc.WWNN,
6239 vha->node_name,
6240 sizeof(rsp_payload->port_name_diag_desc.WWNN));
6241 memcpy(rsp_payload->port_name_diag_desc.WWPN,
6242 vha->port_name,
6243 sizeof(rsp_payload->port_name_diag_desc.WWPN));
6244
6245 /* F-Port Portname Descriptor */
6246 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003);
6247 rsp_payload->port_name_direct_desc.desc_len =
6248 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc));
6249 memcpy(rsp_payload->port_name_direct_desc.WWNN,
6250 vha->fabric_node_name,
6251 sizeof(rsp_payload->port_name_direct_desc.WWNN));
6252 memcpy(rsp_payload->port_name_direct_desc.WWPN,
6253 vha->fabric_port_name,
6254 sizeof(rsp_payload->port_name_direct_desc.WWPN));
6255
770538c3
QT		 6256 /* Bufer Credit Descriptor */
6257 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006);
6258 rsp_payload->buffer_credit_desc.desc_len =
6259 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc));
6260 rsp_payload->buffer_credit_desc.fcport_b2b = 0;
6261 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0);
6262 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0);
6263
44f5a37d
QT		 6264 if (ha->flags.plogi_template_valid) {
6265 uint32_t tmp =
6266 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred);
6267 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp);
d83a80ee
JC		 6268 }
6269
4879237c
JC		 6270 if (rsp_payload_length < sizeof(*rsp_payload))
6271 goto send;
6272
770538c3
QT		 6273 /* Optical Element Descriptor, Temperature */
6274 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007);
6275 rsp_payload->optical_elmt_desc[0].desc_len =
6276 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6277 /* Optical Element Descriptor, Voltage */
6278 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007);
6279 rsp_payload->optical_elmt_desc[1].desc_len =
6280 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6281 /* Optical Element Descriptor, Tx Bias Current */
6282 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007);
6283 rsp_payload->optical_elmt_desc[2].desc_len =
6284 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6285 /* Optical Element Descriptor, Tx Power */
6286 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007);
6287 rsp_payload->optical_elmt_desc[3].desc_len =
6288 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6289 /* Optical Element Descriptor, Rx Power */
6290 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007);
6291 rsp_payload->optical_elmt_desc[4].desc_len =
6292 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6293
d83a80ee
JC		 6294 if (sfp) {
6295 memset(sfp, 0, SFP_RTDI_LEN);
6296 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0);
6297 if (!rval) {
7ffa5b93 6298 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
d83a80ee
JC		 6299
6300 /* Optical Element Descriptor, Temperature */
d83a80ee
JC		 6301 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0];
6302 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1];
6303 rsp_payload->optical_elmt_desc[0].high_warn = trx[2];
6304 rsp_payload->optical_elmt_desc[0].low_warn = trx[3];
6305 rsp_payload->optical_elmt_desc[0].element_flags =
6306 cpu_to_be32(1 << 28);
6307
6308 /* Optical Element Descriptor, Voltage */
d83a80ee
JC		 6309 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4];
6310 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5];
6311 rsp_payload->optical_elmt_desc[1].high_warn = trx[6];
6312 rsp_payload->optical_elmt_desc[1].low_warn = trx[7];
6313 rsp_payload->optical_elmt_desc[1].element_flags =
6314 cpu_to_be32(2 << 28);
6315
6316 /* Optical Element Descriptor, Tx Bias Current */
d83a80ee
JC		 6317 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8];
6318 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9];
6319 rsp_payload->optical_elmt_desc[2].high_warn = trx[10];
6320 rsp_payload->optical_elmt_desc[2].low_warn = trx[11];
6321 rsp_payload->optical_elmt_desc[2].element_flags =
6322 cpu_to_be32(3 << 28);
6323
6324 /* Optical Element Descriptor, Tx Power */
d83a80ee
JC		 6325 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12];
6326 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13];
6327 rsp_payload->optical_elmt_desc[3].high_warn = trx[14];
6328 rsp_payload->optical_elmt_desc[3].low_warn = trx[15];
6329 rsp_payload->optical_elmt_desc[3].element_flags =
6330 cpu_to_be32(4 << 28);
6331
6332 /* Optical Element Descriptor, Rx Power */
d83a80ee
JC		 6333 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16];
6334 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17];
6335 rsp_payload->optical_elmt_desc[4].high_warn = trx[18];
6336 rsp_payload->optical_elmt_desc[4].low_warn = trx[19];
6337 rsp_payload->optical_elmt_desc[4].element_flags =
6338 cpu_to_be32(5 << 28);
6339 }
6340
6341 memset(sfp, 0, SFP_RTDI_LEN);
6342 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0);
6343 if (!rval) {
6344 /* Temperature high/low alarm/warning */
6345 rsp_payload->optical_elmt_desc[0].element_flags |=
6346 cpu_to_be32(
6347 (sfp[0] >> 7 & 1) << 3 |
6348 (sfp[0] >> 6 & 1) << 2 |
6349 (sfp[4] >> 7 & 1) << 1 |
6350 (sfp[4] >> 6 & 1) << 0);
6351
6352 /* Voltage high/low alarm/warning */
6353 rsp_payload->optical_elmt_desc[1].element_flags |=
6354 cpu_to_be32(
6355 (sfp[0] >> 5 & 1) << 3 |
6356 (sfp[0] >> 4 & 1) << 2 |
6357 (sfp[4] >> 5 & 1) << 1 |
6358 (sfp[4] >> 4 & 1) << 0);
6359
6360 /* Tx Bias Current high/low alarm/warning */
6361 rsp_payload->optical_elmt_desc[2].element_flags |=
6362 cpu_to_be32(
6363 (sfp[0] >> 3 & 1) << 3 |
6364 (sfp[0] >> 2 & 1) << 2 |
6365 (sfp[4] >> 3 & 1) << 1 |
6366 (sfp[4] >> 2 & 1) << 0);
6367
6368 /* Tx Power high/low alarm/warning */
6369 rsp_payload->optical_elmt_desc[3].element_flags |=
6370 cpu_to_be32(
6371 (sfp[0] >> 1 & 1) << 3 |
6372 (sfp[0] >> 0 & 1) << 2 |
6373 (sfp[4] >> 1 & 1) << 1 |
6374 (sfp[4] >> 0 & 1) << 0);
6375
6376 /* Rx Power high/low alarm/warning */
6377 rsp_payload->optical_elmt_desc[4].element_flags |=
6378 cpu_to_be32(
6379 (sfp[1] >> 7 & 1) << 3 |
6380 (sfp[1] >> 6 & 1) << 2 |
6381 (sfp[5] >> 7 & 1) << 1 |
6382 (sfp[5] >> 6 & 1) << 0);
6383 }
6384 }
6385
770538c3
QT		 6386 /* Optical Product Data Descriptor */
6387 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008);
6388 rsp_payload->optical_prod_desc.desc_len =
6389 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc));
6390
d83a80ee
JC		 6391 if (sfp) {
6392 memset(sfp, 0, SFP_RTDI_LEN);
6393 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0);
6394 if (!rval) {
d83a80ee
JC		 6395 memcpy(rsp_payload->optical_prod_desc.vendor_name,
6396 sfp + 0,
6397 sizeof(rsp_payload->optical_prod_desc.vendor_name));
6398 memcpy(rsp_payload->optical_prod_desc.part_number,
6399 sfp + 20,
6400 sizeof(rsp_payload->optical_prod_desc.part_number));
6401 memcpy(rsp_payload->optical_prod_desc.revision,
6402 sfp + 36,
6403 sizeof(rsp_payload->optical_prod_desc.revision));
6404 memcpy(rsp_payload->optical_prod_desc.serial_number,
6405 sfp + 48,
6406 sizeof(rsp_payload->optical_prod_desc.serial_number));
6407 }
6408
6409 memset(sfp, 0, SFP_RTDI_LEN);
6410 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0);
6411 if (!rval) {
6412 memcpy(rsp_payload->optical_prod_desc.date,
6413 sfp + 0,
6414 sizeof(rsp_payload->optical_prod_desc.date));
6415 }
6416 }
6417
6418send:
6419 ql_dbg(ql_dbg_init, vha, 0x0183,
6420 "Sending ELS Response to RDP Request...\n");
6421 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184,
6422 "-------- ELS RSP -------\n");
6423 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185,
ab053c09 6424 rsp_els, sizeof(*rsp_els));
d83a80ee
JC		 6425 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186,
6426 "-------- ELS RSP PAYLOAD -------\n");
6427 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187,
ab053c09 6428 rsp_payload, rsp_payload_length);
d83a80ee
JC		 6429
6430 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0);
6431
09e382bc 6432 if (rval) {
d83a80ee 6433 ql_log(ql_log_warn, vha, 0x0188,
09e382bc
JC		 6434 "%s: iocb failed to execute -> %x\n", __func__, rval);
6435 } else if (rsp_els->comp_status) {
d83a80ee 6436 ql_log(ql_log_warn, vha, 0x0189,
09e382bc
JC		 6437 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n",
6438 __func__, rsp_els->comp_status,
6439 rsp_els->error_subcode_1, rsp_els->error_subcode_2);
d83a80ee
JC		 6440 } else {
6441 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__);
6442 }
6443
6444dealloc:
d83a80ee
JC		 6445 if (stat)
6446 dma_free_coherent(&ha->pdev->dev, sizeof(*stat),
6447 stat, stat_dma);
6448 if (sfp)
6449 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6450 sfp, sfp_dma);
6451 if (rsp_payload)
6452 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6453 rsp_payload, rsp_payload_dma);
6454 if (rsp_els)
6455 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6456 rsp_els, rsp_els_dma);
576bfde8 6457}
d83a80ee 6458
62e9dd17
SS		 6459void
6460qla24xx_free_purex_item(struct purex_item *item)
6461{
6462 if (item == &item->vha->default_item)
6463 memset(&item->vha->default_item, 0, sizeof(struct purex_item));
6464 else
6465 kfree(item);
6466}
6467
576bfde8
JC		 6468void qla24xx_process_purex_list(struct purex_list *list)
6469{
6470 struct list_head head = LIST_HEAD_INIT(head);
6471 struct purex_item *item, *next;
6472 ulong flags;
6473
6474 spin_lock_irqsave(&list->lock, flags);
6475 list_splice_init(&list->head, &head);
6476 spin_unlock_irqrestore(&list->lock, flags);
6477
6478 list_for_each_entry_safe(item, next, &head, list) {
6479 list_del(&item->list);
62e9dd17
SS		 6480 item->process_item(item->vha, item);
6481 qla24xx_free_purex_item(item);
576bfde8 6482 }
d83a80ee
JC		 6483}
6484
4f6a57c2
AD		 6485/*
6486 * Context: task, can sleep
6487 */
7d613ac6
SV		 6488void
6489qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
6490{
5897cb2f
BVA		 6491#if 0
6492 uint16_t options = (requester_id << 15) | BIT_7;
6493#endif
6494 uint16_t retry;
7d613ac6
SV		 6495 uint32_t data;
6496 struct qla_hw_data *ha = base_vha->hw;
6497
4f6a57c2
AD		 6498 might_sleep();
6499
7d613ac6
SV		 6500 /* IDC-unlock implementation using driver-unlock/lock-id
6501 * remote registers
6502 */
6503 retry = 0;
6504retry_unlock:
6505 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
6506 == QLA_SUCCESS) {
6507 if (data == ha->portnum) {
6508 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
6509 /* Clearing lock-id by setting 0xff */
6510 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
6511 } else if (retry < 10) {
6512 /* SV: XXX: IDC unlock retrying needed here? */
6513
6514 /* Retry for IDC-unlock */
4f6a57c2 6515 msleep(QLA83XX_WAIT_LOGIC_MS);
7d613ac6
SV		 6516 retry++;
6517 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 6518 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 6519 goto retry_unlock;
6520 }
6521 } else if (retry < 10) {
6522 /* Retry for IDC-unlock */
4f6a57c2 6523 msleep(QLA83XX_WAIT_LOGIC_MS);
7d613ac6
SV		 6524 retry++;
6525 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 6526 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 6527 goto retry_unlock;
6528 }
6529
6530 return;
6531
5897cb2f 6532#if 0
7d613ac6
SV		 6533 /* XXX: IDC-unlock implementation using access-control mbx */
6534 retry = 0;
6535retry_unlock2:
6536 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
6537 if (retry < 10) {
6538 /* Retry for IDC-unlock */
4f6a57c2 6539 msleep(QLA83XX_WAIT_LOGIC_MS);
7d613ac6
SV		 6540 retry++;
6541 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 6542 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 6543 goto retry_unlock2;
6544 }
6545 }
6546
6547 return;
5897cb2f 6548#endif
7d613ac6
SV		 6549}
6550
6551int
6552__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6553{
6554 int rval = QLA_SUCCESS;
6555 struct qla_hw_data *ha = vha->hw;
6556 uint32_t drv_presence;
6557
6558 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6559 if (rval == QLA_SUCCESS) {
6560 drv_presence |= (1 << ha->portnum);
6561 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6562 drv_presence);
6563 }
6564
6565 return rval;
6566}
6567
6568int
6569qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6570{
6571 int rval = QLA_SUCCESS;
6572
6573 qla83xx_idc_lock(vha, 0);
6574 rval = __qla83xx_set_drv_presence(vha);
6575 qla83xx_idc_unlock(vha, 0);
6576
6577 return rval;
6578}
6579
6580int
6581__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6582{
6583 int rval = QLA_SUCCESS;
6584 struct qla_hw_data *ha = vha->hw;
6585 uint32_t drv_presence;
6586
6587 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6588 if (rval == QLA_SUCCESS) {
6589 drv_presence &= ~(1 << ha->portnum);
6590 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6591 drv_presence);
6592 }
6593
6594 return rval;
6595}
6596
6597int
6598qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6599{
6600 int rval = QLA_SUCCESS;
6601
6602 qla83xx_idc_lock(vha, 0);
6603 rval = __qla83xx_clear_drv_presence(vha);
6604 qla83xx_idc_unlock(vha, 0);
6605
6606 return rval;
6607}
6608
fa492630 6609static void
7d613ac6
SV		 6610qla83xx_need_reset_handler(scsi_qla_host_t *vha)
6611{
6612 struct qla_hw_data *ha = vha->hw;
6613 uint32_t drv_ack, drv_presence;
6614 unsigned long ack_timeout;
6615
6616 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
6617 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
6618 while (1) {
6619 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6620 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 6621 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 6622 break;
6623
6624 if (time_after_eq(jiffies, ack_timeout)) {
6625 ql_log(ql_log_warn, vha, 0xb067,
6626 "RESET ACK TIMEOUT! drv_presence=0x%x "
6627 "drv_ack=0x%x\n", drv_presence, drv_ack);
6628 /*
6629 * The function(s) which did not ack in time are forced
6630 * to withdraw any further participation in the IDC
6631 * reset.
6632 */
6633 if (drv_ack != drv_presence)
6634 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6635 drv_ack);
6636 break;
6637 }
6638
6639 qla83xx_idc_unlock(vha, 0);
6640 msleep(1000);
6641 qla83xx_idc_lock(vha, 0);
6642 }
6643
6644 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
6645 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
6646}
6647
fa492630 6648static int
7d613ac6
SV		 6649qla83xx_device_bootstrap(scsi_qla_host_t *vha)
6650{
6651 int rval = QLA_SUCCESS;
6652 uint32_t idc_control;
6653
6654 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
6655 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
6656
6657 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
6658 __qla83xx_get_idc_control(vha, &idc_control);
6659 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
6660 __qla83xx_set_idc_control(vha, 0);
6661
6662 qla83xx_idc_unlock(vha, 0);
6663 rval = qla83xx_restart_nic_firmware(vha);
6664 qla83xx_idc_lock(vha, 0);
6665
6666 if (rval != QLA_SUCCESS) {
6667 ql_log(ql_log_fatal, vha, 0xb06a,
6668 "Failed to restart NIC f/w.\n");
6669 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
6670 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
6671 } else {
6672 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
6673 "Success in restarting nic f/w.\n");
6674 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
6675 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
6676 }
6677
6678 return rval;
6679}
6680
6681/* Assumes idc_lock always held on entry */
6682int
6683qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
6684{
6685 struct qla_hw_data *ha = base_vha->hw;
6686 int rval = QLA_SUCCESS;
6687 unsigned long dev_init_timeout;
6688 uint32_t dev_state;
6689
6690 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
6691 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
6692
6693 while (1) {
6694
6695 if (time_after_eq(jiffies, dev_init_timeout)) {
6696 ql_log(ql_log_warn, base_vha, 0xb06e,
6697 "Initialization TIMEOUT!\n");
6698 /* Init timeout. Disable further NIC Core
6699 * communication.
6700 */
6701 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
6702 QLA8XXX_DEV_FAILED);
6703 ql_log(ql_log_info, base_vha, 0xb06f,
6704 "HW State: FAILED.\n");
6705 }
6706
6707 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6708 switch (dev_state) {
6709 case QLA8XXX_DEV_READY:
6710 if (ha->flags.nic_core_reset_owner)
6711 qla83xx_idc_audit(base_vha,
6712 IDC_AUDIT_COMPLETION);
6713 ha->flags.nic_core_reset_owner = 0;
6714 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
6715 "Reset_owner reset by 0x%x.\n",
6716 ha->portnum);
6717 goto exit;
6718 case QLA8XXX_DEV_COLD:
6719 if (ha->flags.nic_core_reset_owner)
6720 rval = qla83xx_device_bootstrap(base_vha);
6721 else {
6722 /* Wait for AEN to change device-state */
6723 qla83xx_idc_unlock(base_vha, 0);
6724 msleep(1000);
6725 qla83xx_idc_lock(base_vha, 0);
6726 }
6727 break;
6728 case QLA8XXX_DEV_INITIALIZING:
6729 /* Wait for AEN to change device-state */
6730 qla83xx_idc_unlock(base_vha, 0);
6731 msleep(1000);
6732 qla83xx_idc_lock(base_vha, 0);
6733 break;
6734 case QLA8XXX_DEV_NEED_RESET:
6735 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6736 qla83xx_need_reset_handler(base_vha);
6737 else {
6738 /* Wait for AEN to change device-state */
6739 qla83xx_idc_unlock(base_vha, 0);
6740 msleep(1000);
6741 qla83xx_idc_lock(base_vha, 0);
6742 }
6743 /* reset timeout value after need reset handler */
6744 dev_init_timeout = jiffies +
6745 (ha->fcoe_dev_init_timeout * HZ);
6746 break;
6747 case QLA8XXX_DEV_NEED_QUIESCENT:
6748 /* XXX: DEBUG for now */
6749 qla83xx_idc_unlock(base_vha, 0);
6750 msleep(1000);
6751 qla83xx_idc_lock(base_vha, 0);
6752 break;
6753 case QLA8XXX_DEV_QUIESCENT:
6754 /* XXX: DEBUG for now */
6755 if (ha->flags.quiesce_owner)
6756 goto exit;
6757
6758 qla83xx_idc_unlock(base_vha, 0);
6759 msleep(1000);
6760 qla83xx_idc_lock(base_vha, 0);
6761 dev_init_timeout = jiffies +
6762 (ha->fcoe_dev_init_timeout * HZ);
6763 break;
6764 case QLA8XXX_DEV_FAILED:
6765 if (ha->flags.nic_core_reset_owner)
6766 qla83xx_idc_audit(base_vha,
6767 IDC_AUDIT_COMPLETION);
6768 ha->flags.nic_core_reset_owner = 0;
6769 __qla83xx_clear_drv_presence(base_vha);
6770 qla83xx_idc_unlock(base_vha, 0);
6771 qla8xxx_dev_failed_handler(base_vha);
6772 rval = QLA_FUNCTION_FAILED;
6773 qla83xx_idc_lock(base_vha, 0);
6774 goto exit;
6775 case QLA8XXX_BAD_VALUE:
6776 qla83xx_idc_unlock(base_vha, 0);
6777 msleep(1000);
6778 qla83xx_idc_lock(base_vha, 0);
6779 break;
6780 default:
6781 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 6782 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 6783 qla83xx_idc_unlock(base_vha, 0);
6784 qla8xxx_dev_failed_handler(base_vha);
6785 rval = QLA_FUNCTION_FAILED;
6786 qla83xx_idc_lock(base_vha, 0);
6787 goto exit;
6788 }
6789 }
6790
6791exit:
6792 return rval;
6793}
6794
f3ddac19
CD		 6795void
6796qla2x00_disable_board_on_pci_error(struct work_struct *work)
6797{
6798 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6799 board_disable);
6800 struct pci_dev *pdev = ha->pdev;
6801 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6802
6803 ql_log(ql_log_warn, base_vha, 0x015b,
6804 "Disabling adapter.\n");
6805
efdb5760
SC		 6806 if (!atomic_read(&pdev->enable_cnt)) {
6807 ql_log(ql_log_info, base_vha, 0xfffc,
6808 "PCI device disabled, no action req for PCI error=%lx\n",
6809 base_vha->pci_flags);
6810 return;
6811 }
6812
856e152a
MW		 6813 /*
6814 * if UNLOADING flag is already set, then continue unload,
6815 * where it was set first.
6816 */
6817 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
6818 return;
726b8548 6819
856e152a 6820 qla2x00_wait_for_sess_deletion(base_vha);
f3ddac19
CD		 6821
6822 qla2x00_delete_all_vps(ha, base_vha);
6823
6824 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6825
6826 qla2x00_dfs_remove(base_vha);
6827
6828 qla84xx_put_chip(base_vha);
6829
6830 if (base_vha->timer_active)
6831 qla2x00_stop_timer(base_vha);
6832
6833 base_vha->flags.online = 0;
6834
6835 qla2x00_destroy_deferred_work(ha);
6836
6837 /*
6838 * Do not try to stop beacon blink as it will issue a mailbox
6839 * command.
6840 */
6841 qla2x00_free_sysfs_attr(base_vha, false);
6842
6843 fc_remove_host(base_vha->host);
6844
6845 scsi_remove_host(base_vha->host);
6846
6847 base_vha->flags.init_done = 0;
6848 qla25xx_delete_queues(base_vha);
f3ddac19 6849 qla2x00_free_fcports(base_vha);
093df737 6850 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 6851 qla2x00_mem_free(ha);
6852 qla82xx_md_free(base_vha);
6853 qla2x00_free_queues(ha);
6854
f3ddac19
CD		 6855 qla2x00_unmap_iobases(ha);
6856
6857 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19 6858 pci_disable_device(pdev);
f3ddac19 6859
beb9e315
JL		 6860 /*
6861 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6862 */
f3ddac19
CD		 6863}
6864
1da177e4
LT		 6865/**************************************************************************
6866* qla2x00_do_dpc
6867* This kernel thread is a task that is schedule by the interrupt handler
6868* to perform the background processing for interrupts.
6869*
6870* Notes:
6871* This task always run in the context of a kernel thread. It
6872* is kick-off by the driver's detect code and starts up
6873* up one per adapter. It immediately goes to sleep and waits for
6874* some fibre event. When either the interrupt handler or
6875* the timer routine detects a event it will one of the task
6876* bits then wake us up.
6877**************************************************************************/
6878static int
6879qla2x00_do_dpc(void *data)
6880{
e315cd28
AC		 6881 scsi_qla_host_t *base_vha;
6882 struct qla_hw_data *ha;
d7459527
MH		 6883 uint32_t online;
6884 struct qla_qpair *qpair;
1da177e4 6885
e315cd28
AC		 6886 ha = (struct qla_hw_data *)data;
6887 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 6888
8698a745 6889 set_user_nice(current, MIN_NICE);
1da177e4 6890
563585ec 6891 set_current_state(TASK_INTERRUPTIBLE);
07c903db 6892 while (1) {
7c3df132
SK		 6893 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6894 "DPC handler sleeping.\n");
1da177e4 6895
39a11240 6896 schedule();
1da177e4 6897
07c903db
QT		 6898 if (kthread_should_stop())
6899 break;
6900
f7a0ed47
QT		 6901 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags))
6902 qla_pci_set_eeh_busy(base_vha);
6903
c142caf0
AV		 6904 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6905 goto end_loop;
1da177e4 6906
85880801 6907 if (ha->flags.eeh_busy) {
7c3df132
SK		 6908 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6909 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 6910 goto end_loop;
85880801
AV		 6911 }
6912
07c903db
QT		 6913 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6914 /* don't do any work. Wait to be terminated by kthread_stop */
6915 goto end_loop;
6916
1da177e4
LT		 6917 ha->dpc_active = 1;
6918
5f28d2d7
SK		 6919 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6920 "DPC handler waking up, dpc_flags=0x%lx.\n",
6921 base_vha->dpc_flags);
1da177e4 6922
7ec0effd
AD		 6923 if (IS_P3P_TYPE(ha)) {
6924 if (IS_QLA8044(ha)) {
6925 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6926 &base_vha->dpc_flags)) {
6927 qla8044_idc_lock(ha);
6928 qla8044_wr_direct(base_vha,
6929 QLA8044_CRB_DEV_STATE_INDEX,
6930 QLA8XXX_DEV_FAILED);
6931 qla8044_idc_unlock(ha);
6932 ql_log(ql_log_info, base_vha, 0x4004,
6933 "HW State: FAILED.\n");
6934 qla8044_device_state_handler(base_vha);
6935 continue;
6936 }
6937
6938 } else {
6939 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6940 &base_vha->dpc_flags)) {
6941 qla82xx_idc_lock(ha);
6942 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6943 QLA8XXX_DEV_FAILED);
6944 qla82xx_idc_unlock(ha);
6945 ql_log(ql_log_info, base_vha, 0x0151,
6946 "HW State: FAILED.\n");
6947 qla82xx_device_state_handler(base_vha);
6948 continue;
6949 }
a9083016
GM		 6950 }
6951
6952 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6953 &base_vha->dpc_flags)) {
6954
7c3df132
SK		 6955 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6956 "FCoE context reset scheduled.\n");
a9083016
GM		 6957 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6958 &base_vha->dpc_flags))) {
6959 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6960 /* FCoE-ctx reset failed.
6961 * Escalate to chip-reset
6962 */
6963 set_bit(ISP_ABORT_NEEDED,
6964 &base_vha->dpc_flags);
6965 }
6966 clear_bit(ABORT_ISP_ACTIVE,
6967 &base_vha->dpc_flags);
6968 }
6969
7c3df132
SK		 6970 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6971 "FCoE context reset end.\n");
a9083016 6972 }
8ae6d9c7
GM		 6973 } else if (IS_QLAFX00(ha)) {
6974 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6975 &base_vha->dpc_flags)) {
6976 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6977 "Firmware Reset Recovery\n");
6978 if (qlafx00_reset_initialize(base_vha)) {
6979 /* Failed. Abort isp later. */
6980 if (!test_bit(UNLOADING,
f92f82d6 6981 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 6982 set_bit(ISP_UNRECOVERABLE,
6983 &base_vha->dpc_flags);
6984 ql_dbg(ql_dbg_dpc, base_vha,
6985 0x4021,
6986 "Reset Recovery Failed\n");
f92f82d6 6987 }
8ae6d9c7
GM		 6988 }
6989 }
6990
6991 if (test_and_clear_bit(FX00_TARGET_SCAN,
6992 &base_vha->dpc_flags)) {
6993 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6994 "ISPFx00 Target Scan scheduled\n");
6995 if (qlafx00_rescan_isp(base_vha)) {
6996 if (!test_bit(UNLOADING,
6997 &base_vha->dpc_flags))
6998 set_bit(ISP_UNRECOVERABLE,
6999 &base_vha->dpc_flags);
7000 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
7001 "ISPFx00 Target Scan Failed\n");
7002 }
7003 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
7004 "ISPFx00 Target Scan End\n");
7005 }
e8f5e95d
AB		 7006 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
7007 &base_vha->dpc_flags)) {
7008 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
7009 "ISPFx00 Host Info resend scheduled\n");
7010 qlafx00_fx_disc(base_vha,
7011 &base_vha->hw->mr.fcport,
7012 FXDISC_REG_HOST_INFO);
7013 }
a9083016
GM		 7014 }
7015
e4e3a2ce 7016 if (test_and_clear_bit(DETECT_SFP_CHANGE,
b0f18eee
AV		 7017 &base_vha->dpc_flags)) {
7018 /* Semantic:
7019 * - NO-OP -- await next ISP-ABORT. Preferred method
7020 * to minimize disruptions that will occur
7021 * when a forced chip-reset occurs.
7022 * - Force -- ISP-ABORT scheduled.
7023 */
7024 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */
e4e3a2ce
QT		 7025 }
7026
b08abbd9
QT		 7027 if (test_and_clear_bit
7028 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
7029 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
93eca613
QT		 7030 bool do_reset = true;
7031
0645cb83 7032 switch (base_vha->qlini_mode) {
93eca613
QT		 7033 case QLA2XXX_INI_MODE_ENABLED:
7034 break;
7035 case QLA2XXX_INI_MODE_DISABLED:
0645cb83
QT		 7036 if (!qla_tgt_mode_enabled(base_vha) &&
7037 !ha->flags.fw_started)
93eca613
QT		 7038 do_reset = false;
7039 break;
7040 case QLA2XXX_INI_MODE_DUAL:
0645cb83
QT		 7041 if (!qla_dual_mode_enabled(base_vha) &&
7042 !ha->flags.fw_started)
93eca613
QT		 7043 do_reset = false;
7044 break;
7045 default:
7046 break;
7047 }
1da177e4 7048
93eca613 7049 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 7050 &base_vha->dpc_flags))) {
f839544c 7051 base_vha->flags.online = 1;
93eca613
QT		 7052 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
7053 "ISP abort scheduled.\n");
a9083016 7054 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 7055 /* failed. retry later */
7056 set_bit(ISP_ABORT_NEEDED,
e315cd28 7057 &base_vha->dpc_flags);
99363ef8 7058 }
e315cd28
AC		 7059 clear_bit(ABORT_ISP_ACTIVE,
7060 &base_vha->dpc_flags);
93eca613
QT		 7061 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
7062 "ISP abort end.\n");
99363ef8 7063 }
1da177e4
LT		 7064 }
7065
576bfde8
JC		 7066 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) {
7067 if (atomic_read(&base_vha->loop_state) == LOOP_READY) {
7068 qla24xx_process_purex_list
7069 (&base_vha->purex_list);
7070 clear_bit(PROCESS_PUREX_IOCB,
7071 &base_vha->dpc_flags);
7072 }
d83a80ee
JC		 7073 }
7074
8ae6d9c7
GM		 7075 if (IS_QLAFX00(ha))
7076 goto loop_resync_check;
7077
579d12b5 7078 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 7079 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
7080 "Quiescence mode scheduled.\n");
7ec0effd
AD		 7081 if (IS_P3P_TYPE(ha)) {
7082 if (IS_QLA82XX(ha))
7083 qla82xx_device_state_handler(base_vha);
7084 if (IS_QLA8044(ha))
7085 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 7086 clear_bit(ISP_QUIESCE_NEEDED,
7087 &base_vha->dpc_flags);
7088 if (!ha->flags.quiesce_owner) {
7089 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 7090 if (IS_QLA82XX(ha)) {
7091 qla82xx_idc_lock(ha);
7092 qla82xx_clear_qsnt_ready(
7093 base_vha);
7094 qla82xx_idc_unlock(ha);
7095 } else if (IS_QLA8044(ha)) {
7096 qla8044_idc_lock(ha);
7097 qla8044_clear_qsnt_ready(
7098 base_vha);
7099 qla8044_idc_unlock(ha);
7100 }
8fcd6b8b
CD		 7101 }
7102 } else {
7103 clear_bit(ISP_QUIESCE_NEEDED,
7104 &base_vha->dpc_flags);
7105 qla2x00_quiesce_io(base_vha);
579d12b5 7106 }
7c3df132
SK		 7107 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
7108 "Quiescence mode end.\n");
579d12b5
SK		 7109 }
7110
e315cd28 7111 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 7112 &base_vha->dpc_flags) &&
e315cd28 7113 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 7114
7c3df132
SK		 7115 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
7116 "Reset marker scheduled.\n");
e315cd28
AC		 7117 qla2x00_rst_aen(base_vha);
7118 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 7119 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
7120 "Reset marker end.\n");
1da177e4
LT		 7121 }
7122
7123 /* Retry each device up to login retry count */
4005a995 7124 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
e315cd28
AC		 7125 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
7126 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 7127
4005a995
QT		 7128 if (!base_vha->relogin_jif ||
7129 time_after_eq(jiffies, base_vha->relogin_jif)) {
7130 base_vha->relogin_jif = jiffies + HZ;
7131 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
7132
9b3e0f4d 7133 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
4005a995 7134 "Relogin scheduled.\n");
9b3e0f4d 7135 qla24xx_post_relogin_work(base_vha);
4005a995 7136 }
1da177e4 7137 }
8ae6d9c7 7138loop_resync_check:
3fbc74fe
QT		 7139 if (!qla2x00_reset_active(base_vha) &&
7140 test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 7141 &base_vha->dpc_flags)) {
3fbc74fe
QT		 7142 /*
7143 * Allow abort_isp to complete before moving on to scanning.
7144 */
7c3df132
SK		 7145 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
7146 "Loop resync scheduled.\n");
1da177e4
LT		 7147
7148 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 7149 &base_vha->dpc_flags))) {
1da177e4 7150
52c82823 7151 qla2x00_loop_resync(base_vha);
1da177e4 7152
e315cd28
AC		 7153 clear_bit(LOOP_RESYNC_ACTIVE,
7154 &base_vha->dpc_flags);
1da177e4
LT		 7155 }
7156
7c3df132
SK		 7157 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
7158 "Loop resync end.\n");
1da177e4
LT		 7159 }
7160
8ae6d9c7
GM		 7161 if (IS_QLAFX00(ha))
7162 goto intr_on_check;
7163
e315cd28
AC		 7164 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
7165 atomic_read(&base_vha->loop_state) == LOOP_READY) {
7166 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
7167 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 7168 }
7169
8ae6d9c7 7170intr_on_check:
1da177e4 7171 if (!ha->interrupts_on)
fd34f556 7172 ha->isp_ops->enable_intrs(ha);
1da177e4 7173
e315cd28 7174 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 7175 &base_vha->dpc_flags)) {
7176 if (ha->beacon_blink_led == 1)
7177 ha->isp_ops->beacon_blink(base_vha);
7178 }
f6df144c 7179
d7459527
MH		 7180 /* qpair online check */
7181 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
7182 &base_vha->dpc_flags)) {
7183 if (ha->flags.eeh_busy ||
7184 ha->flags.pci_channel_io_perm_failure)
7185 online = 0;
7186 else
7187 online = 1;
7188
7189 mutex_lock(&ha->mq_lock);
7190 list_for_each_entry(qpair, &base_vha->qp_list,
7191 qp_list_elem)
7192 qpair->online = online;
7193 mutex_unlock(&ha->mq_lock);
7194 }
7195
5777fef7
QT		 7196 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
7197 &base_vha->dpc_flags)) {
7198 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold;
7199
7200 if (threshold > ha->orig_fw_xcb_count)
7201 threshold = ha->orig_fw_xcb_count;
7202
deeae7a6 7203 ql_log(ql_log_info, base_vha, 0xffffff,
5777fef7
QT		 7204 "SET ZIO Activity exchange threshold to %d.\n",
7205 threshold);
7206 if (qla27xx_set_zio_threshold(base_vha, threshold)) {
deeae7a6 7207 ql_log(ql_log_info, base_vha, 0xffffff,
5777fef7
QT		 7208 "Unable to SET ZIO Activity exchange threshold to %d.\n",
7209 threshold);
deeae7a6
DG		 7210 }
7211 }
7212
8ae6d9c7
GM		 7213 if (!IS_QLAFX00(ha))
7214 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 7215
48acad09
QT		 7216 if (test_and_clear_bit(N2N_LINK_RESET,
7217 &base_vha->dpc_flags)) {
7218 qla2x00_lip_reset(base_vha);
7219 }
7220
1da177e4 7221 ha->dpc_active = 0;
c142caf0 7222end_loop:
563585ec 7223 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 7224 } /* End of while(1) */
563585ec 7225 __set_current_state(TASK_RUNNING);
1da177e4 7226
7c3df132
SK		 7227 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
7228 "DPC handler exiting.\n");
1da177e4
LT		 7229
7230 /*
7231 * Make sure that nobody tries to wake us up again.
7232 */
1da177e4
LT		 7233 ha->dpc_active = 0;
7234
39a11240
CH		 7235 return 0;
7236}
7237
7238void
e315cd28 7239qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 7240{
e315cd28 7241 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 7242 struct task_struct *t = ha->dpc_thread;
7243
e315cd28 7244 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 7245 wake_up_process(t);
1da177e4
LT		 7246}
7247
1da177e4
LT		 7248/*
7249* qla2x00_rst_aen
7250* Processes asynchronous reset.
7251*
7252* Input:
7253* ha = adapter block pointer.
7254*/
7255static void
e315cd28 7256qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 7257{
e315cd28
AC		 7258 if (vha->flags.online && !vha->flags.reset_active &&
7259 !atomic_read(&vha->loop_down_timer) &&
7260 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 7261 do {
e315cd28 7262 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 7263
7264 /*
7265 * Issue marker command only when we are going to start
7266 * the I/O.
7267 */
e315cd28
AC		 7268 vha->marker_needed = 1;
7269 } while (!atomic_read(&vha->loop_down_timer) &&
7270 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 7271 }
7272}
7273
d94d8158
QT		 7274static bool qla_do_heartbeat(struct scsi_qla_host *vha)
7275{
d94d8158 7276 struct qla_hw_data *ha = vha->hw;
3a4e1f3b
MR		 7277 u32 cmpl_cnt;
7278 u16 i;
7279 bool do_heartbeat = false;
d94d8158 7280
3a4e1f3b
MR		 7281 /*
7282 * Allow do_heartbeat only if we don’t have any active interrupts,
7283 * but there are still IOs outstanding with firmware.
7284 */
7285 cmpl_cnt = ha->base_qpair->cmd_completion_cnt;
7286 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt &&
7287 cmpl_cnt != ha->base_qpair->cmd_cnt) {
7288 do_heartbeat = true;
d94d8158
QT		 7289 goto skip;
7290 }
3a4e1f3b 7291 ha->base_qpair->prev_completion_cnt = cmpl_cnt;
d94d8158
QT		 7292
7293 for (i = 0; i < ha->max_qpairs; i++) {
3a4e1f3b
MR		 7294 if (ha->queue_pair_map[i]) {
7295 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt;
7296 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt &&
7297 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) {
7298 do_heartbeat = true;
7299 break;
7300 }
7301 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt;
d94d8158
QT		 7302 }
7303 }
7304
7305skip:
3a4e1f3b 7306 return do_heartbeat;
d94d8158
QT		 7307}
7308
713b4157 7309static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started)
d94d8158 7310{
3a4e1f3b
MR		 7311 struct qla_hw_data *ha = vha->hw;
7312
d94d8158
QT		 7313 if (vha->vp_idx)
7314 return;
7315
7316 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha))
7317 return;
7318
713b4157
QT		 7319 /*
7320 * dpc thread cannot run if heartbeat is running at the same time.
7321 * We also do not want to starve heartbeat task. Therefore, do
7322 * heartbeat task at least once every 5 seconds.
7323 */
7324 if (dpc_started &&
7325 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ))
7326 return;
7327
7328 if (qla_do_heartbeat(vha)) {
7329 ha->last_heartbeat_run_jiffies = jiffies;
3a4e1f3b 7330 queue_work(ha->wq, &ha->heartbeat_work);
713b4157 7331 }
d94d8158
QT		 7332}
7333
d3117c83
QT		 7334static void qla_wind_down_chip(scsi_qla_host_t *vha)
7335{
7336 struct qla_hw_data *ha = vha->hw;
7337
7338 if (!ha->flags.eeh_busy)
7339 return;
7340 if (ha->pci_error_state)
7341 /* system is trying to recover */
7342 return;
7343
7344 /*
7345 * Current system is not handling PCIE error. At this point, this is
7346 * best effort to wind down the adapter.
7347 */
7348 if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) &&
7349 !ha->flags.eeh_flush) {
7350 ql_log(ql_log_info, vha, 0x9009,
7351 "PCI Error detected, attempting to reset hardware.\n");
7352
7353 ha->isp_ops->reset_chip(vha);
7354 ha->isp_ops->disable_intrs(ha);
7355
7356 ha->flags.eeh_flush = EEH_FLUSH_RDY;
7357 ha->eeh_jif = jiffies;
7358
7359 } else if (ha->flags.eeh_flush == EEH_FLUSH_RDY &&
7360 time_after_eq(jiffies, ha->eeh_jif + 5 * HZ)) {
7361 pci_clear_master(ha->pdev);
7362
7363 /* flush all command */
7364 qla2x00_abort_isp_cleanup(vha);
7365 ha->flags.eeh_flush = EEH_FLUSH_DONE;
7366
7367 ql_log(ql_log_info, vha, 0x900a,
7368 "PCI Error handling complete, all IOs aborted.\n");
7369 }
7370}
7371
1da177e4
LT		 7372/**************************************************************************
7373* qla2x00_timer
7374*
7375* Description:
7376* One second timer
7377*
7378* Context: Interrupt
7379***************************************************************************/
2c3dfe3f 7380void
8e5f4ba0 7381qla2x00_timer(struct timer_list *t)
1da177e4 7382{
41cb0855 7383 scsi_qla_host_t *vha = timer_container_of(vha, t, timer);
1da177e4 7384 unsigned long cpu_flags = 0;
1da177e4
LT		 7385 int start_dpc = 0;
7386 int index;
7387 srb_t *sp;
85880801 7388 uint16_t w;
e315cd28 7389 struct qla_hw_data *ha = vha->hw;
73208dfd 7390 struct req_que *req;
dbf1f53c
SK		 7391 unsigned long flags;
7392 fc_port_t *fcport = NULL;
85880801 7393
a5b36321 7394 if (ha->flags.eeh_busy) {
d3117c83
QT		 7395 qla_wind_down_chip(vha);
7396
7c3df132
SK		 7397 ql_dbg(ql_dbg_timer, vha, 0x6000,
7398 "EEH = %d, restarting timer.\n",
7399 ha->flags.eeh_busy);
a5b36321
LC		 7400 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7401 return;
7402 }
7403
f3ddac19
CD		 7404 /*
7405 * Hardware read to raise pending EEH errors during mailbox waits. If
7406 * the read returns -1 then disable the board.
7407 */
7408 if (!pci_channel_offline(ha->pdev)) {
85880801 7409 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 7410 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 7411 }
1da177e4 7412
cefcaba6 7413 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 7414 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 7415 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
7416 start_dpc++;
7ec0effd
AD		 7417 if (IS_QLA82XX(ha))
7418 qla82xx_watchdog(vha);
7419 else if (IS_QLA8044(ha))
7420 qla8044_watchdog(vha);
579d12b5
SK		 7421 }
7422
8ae6d9c7
GM		 7423 if (!vha->vp_idx && IS_QLAFX00(ha))
7424 qlafx00_timer_routine(vha);
7425
dbf1f53c
SK		 7426 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7427 vha->link_down_time++;
7428
7429 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
7430 list_for_each_entry(fcport, &vha->vp_fcports, list) {
7431 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7432 fcport->tgt_link_down_time++;
7433 }
7434 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
7435
1da177e4 7436 /* Loop down handler. */
e315cd28 7437 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 7438 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
7439 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 7440 && vha->flags.online) {
1da177e4 7441
e315cd28
AC		 7442 if (atomic_read(&vha->loop_down_timer) ==
7443 vha->loop_down_abort_time) {
1da177e4 7444
7c3df132
SK		 7445 ql_log(ql_log_info, vha, 0x6008,
7446 "Loop down - aborting the queues before time expires.\n");
1da177e4 7447
e315cd28
AC		 7448 if (!IS_QLA2100(ha) && vha->link_down_timeout)
7449 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 7450
f08b7251
AV		 7451 /*
7452 * Schedule an ISP abort to return any FCP2-device
7453 * commands.
7454 */
2c3dfe3f 7455 /* NPIV - scan physical port only */
e315cd28 7456 if (!vha->vp_idx) {
2c3dfe3f
SJ		 7457 spin_lock_irqsave(&ha->hardware_lock,
7458 cpu_flags);
73208dfd 7459 req = ha->req_q_map[0];
2c3dfe3f 7460 for (index = 1;
8d93f550 7461 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 7462 index++) {
7463 fc_port_t *sfcp;
7464
e315cd28 7465 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 7466 if (!sp)
7467 continue;
c5419e26
QT		 7468 if (sp->cmd_type != TYPE_SRB)
7469 continue;
9ba56b95 7470 if (sp->type != SRB_SCSI_CMD)
cf53b069 7471 continue;
2c3dfe3f 7472 sfcp = sp->fcport;
f08b7251 7473 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 7474 continue;
bdf79621 7475
8f7daead
GM		 7476 if (IS_QLA82XX(ha))
7477 set_bit(FCOE_CTX_RESET_NEEDED,
7478 &vha->dpc_flags);
7479 else
7480 set_bit(ISP_ABORT_NEEDED,
e315cd28 7481 &vha->dpc_flags);
2c3dfe3f
SJ		 7482 break;
7483 }
7484 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 7485 cpu_flags);
1da177e4 7486 }
1da177e4
LT		 7487 start_dpc++;
7488 }
7489
7490 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 7491 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
b1ae65c0 7492 if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) {
7c3df132 7493 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 7494 "Loop down - aborting ISP.\n");
7495
8f7daead
GM		 7496 if (IS_QLA82XX(ha))
7497 set_bit(FCOE_CTX_RESET_NEEDED,
7498 &vha->dpc_flags);
7499 else
7500 set_bit(ISP_ABORT_NEEDED,
7501 &vha->dpc_flags);
1da177e4
LT		 7502 }
7503 }
7c3df132
SK		 7504 ql_dbg(ql_dbg_timer, vha, 0x600a,
7505 "Loop down - seconds remaining %d.\n",
7506 atomic_read(&vha->loop_down_timer));
1da177e4 7507 }
cefcaba6
SK		 7508 /* Check if beacon LED needs to be blinked for physical host only */
7509 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 7510 /* There is no beacon_blink function for ISP82xx */
7ec0effd 7511 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 7512 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
7513 start_dpc++;
7514 }
f6df144c 7515 }
7516
4de067e5
QT		 7517 /* check if edif running */
7518 if (vha->hw->flags.edif_enabled)
7519 qla_edif_timer(vha);
7520
550bf57d 7521 /* Process any deferred work. */
9b3e0f4d
QT		 7522 if (!list_empty(&vha->work_list)) {
7523 unsigned long flags;
7524 bool q = false;
7525
7526 spin_lock_irqsave(&vha->work_lock, flags);
7527 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
7528 q = true;
7529 spin_unlock_irqrestore(&vha->work_lock, flags);
7530 if (q)
7531 queue_work(vha->hw->wq, &vha->iocb_work);
7532 }
550bf57d 7533
7401bc18
DG		 7534 /*
7535 * FC-NVME
7536 * see if the active AEN count has changed from what was last reported.
7537 */
49db4d4e 7538 index = atomic_read(&ha->nvme_active_aen_cnt);
b2d1453a 7539 if (!vha->vp_idx &&
49db4d4e 7540 (index != ha->nvme_last_rptd_aen) &&
b2d1453a
GM		 7541 ha->zio_mode == QLA_ZIO_MODE_6 &&
7542 !ha->flags.host_shutting_down) {
5777fef7 7543 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
7401bc18 7544 ql_log(ql_log_info, vha, 0x3002,
8b4673ba
QT		 7545 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
7546 ha->nvme_last_rptd_aen);
5777fef7 7547 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
8b4673ba
QT		 7548 start_dpc++;
7549 }
7550
7551 if (!vha->vp_idx &&
49db4d4e
QT		 7552 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold &&
7553 IS_ZIO_THRESHOLD_CAPABLE(ha)) {
8b4673ba
QT		 7554 ql_log(ql_log_info, vha, 0x3002,
7555 "Sched: Set ZIO exchange threshold to %d.\n",
7556 ha->last_zio_threshold);
7557 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
deeae7a6
DG		 7558 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7559 start_dpc++;
7401bc18 7560 }
1f8f9c34 7561 qla_adjust_buf(vha);
7401bc18 7562
713b4157
QT		 7563 /* borrowing w to signify dpc will run */
7564 w = 0;
1da177e4 7565 /* Schedule the DPC routine if needed */
e315cd28
AC		 7566 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
7567 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
1da177e4 7568 start_dpc ||
e315cd28
AC		 7569 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
7570 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 7571 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
7572 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 7573 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
d83a80ee
JC		 7574 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
7575 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) {
7c3df132
SK		 7576 ql_dbg(ql_dbg_timer, vha, 0x600b,
7577 "isp_abort_needed=%d loop_resync_needed=%d "
efd1bd12 7578 "start_dpc=%d reset_marker_needed=%d",
7c3df132
SK		 7579 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
7580 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
efd1bd12 7581 start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
7c3df132
SK		 7582 ql_dbg(ql_dbg_timer, vha, 0x600c,
7583 "beacon_blink_needed=%d isp_unrecoverable=%d "
7584 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
d83a80ee 7585 "relogin_needed=%d, Process_purex_iocb=%d.\n",
7c3df132
SK		 7586 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
7587 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
7588 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
7589 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
d83a80ee
JC		 7590 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
7591 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags));
e315cd28 7592 qla2xxx_wake_dpc(vha);
713b4157 7593 w = 1;
7c3df132 7594 }
1da177e4 7595
713b4157 7596 qla_heart_beat(vha, w);
d94d8158 7597
e315cd28 7598 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 7599}
7600
5433383e
AV		 7601/* Firmware interface routines. */
7602
5433383e
AV		 7603#define FW_ISP21XX 0
7604#define FW_ISP22XX 1
7605#define FW_ISP2300 2
7606#define FW_ISP2322 3
48c02fde 7607#define FW_ISP24XX 4
c3a2f0df 7608#define FW_ISP25XX 5
3a03eb79 7609#define FW_ISP81XX 6
a9083016 7610#define FW_ISP82XX 7
6246b8a1
GM		 7611#define FW_ISP2031 8
7612#define FW_ISP8031 9
2c5bbbb2 7613#define FW_ISP27XX 10
ecc89f25 7614#define FW_ISP28XX 11
5433383e 7615
bb8ee499
AV		 7616#define FW_FILE_ISP21XX "ql2100_fw.bin"
7617#define FW_FILE_ISP22XX "ql2200_fw.bin"
7618#define FW_FILE_ISP2300 "ql2300_fw.bin"
7619#define FW_FILE_ISP2322 "ql2322_fw.bin"
7620#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 7621#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 7622#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 7623#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 7624#define FW_FILE_ISP2031 "ql2600_fw.bin"
7625#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 7626#define FW_FILE_ISP27XX "ql2700_fw.bin"
ecc89f25 7627#define FW_FILE_ISP28XX "ql2800_fw.bin"
f73cb695 7628
bb8ee499 7629
e1e82b6f 7630static DEFINE_MUTEX(qla_fw_lock);
5433383e 7631
ecc89f25 7632static struct fw_blob qla_fw_blobs[] = {
bb8ee499
AV		 7633 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
7634 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
7635 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
7636 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
7637 { .name = FW_FILE_ISP24XX, },
c3a2f0df 7638 { .name = FW_FILE_ISP25XX, },
3a03eb79 7639 { .name = FW_FILE_ISP81XX, },
a9083016 7640 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 7641 { .name = FW_FILE_ISP2031, },
7642 { .name = FW_FILE_ISP8031, },
2c5bbbb2 7643 { .name = FW_FILE_ISP27XX, },
ecc89f25
JC		 7644 { .name = FW_FILE_ISP28XX, },
7645 { .name = NULL, },
5433383e
AV		 7646};
7647
7648struct fw_blob *
e315cd28 7649qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 7650{
e315cd28 7651 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 7652 struct fw_blob *blob;
7653
5433383e
AV		 7654 if (IS_QLA2100(ha)) {
7655 blob = &qla_fw_blobs[FW_ISP21XX];
7656 } else if (IS_QLA2200(ha)) {
7657 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 7658 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 7659 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 7660 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 7661 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 7662 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 7663 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 7664 } else if (IS_QLA25XX(ha)) {
7665 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 7666 } else if (IS_QLA81XX(ha)) {
7667 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 7668 } else if (IS_QLA82XX(ha)) {
7669 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 7670 } else if (IS_QLA2031(ha)) {
7671 blob = &qla_fw_blobs[FW_ISP2031];
7672 } else if (IS_QLA8031(ha)) {
7673 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 7674 } else if (IS_QLA27XX(ha)) {
7675 blob = &qla_fw_blobs[FW_ISP27XX];
ecc89f25
JC		 7676 } else if (IS_QLA28XX(ha)) {
7677 blob = &qla_fw_blobs[FW_ISP28XX];
8a655229
DC		 7678 } else {
7679 return NULL;
5433383e
AV		 7680 }
7681
ecc89f25
JC		 7682 if (!blob->name)
7683 return NULL;
7684
e1e82b6f 7685 mutex_lock(&qla_fw_lock);
5433383e
AV		 7686 if (blob->fw)
7687 goto out;
7688
7689 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 7690 ql_log(ql_log_warn, vha, 0x0063,
7691 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 7692 blob->fw = NULL;
7693 blob = NULL;
5433383e
AV		 7694 }
7695
7696out:
e1e82b6f 7697 mutex_unlock(&qla_fw_lock);
5433383e
AV		 7698 return blob;
7699}
7700
7701static void
7702qla2x00_release_firmware(void)
7703{
ecc89f25 7704 struct fw_blob *blob;
5433383e 7705
e1e82b6f 7706 mutex_lock(&qla_fw_lock);
ecc89f25
JC		 7707 for (blob = qla_fw_blobs; blob->name; blob++)
7708 release_firmware(blob->fw);
e1e82b6f 7709 mutex_unlock(&qla_fw_lock);
5433383e
AV		 7710}
7711
5386a4e6
QT		 7712static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
7713{
7714 struct qla_hw_data *ha = vha->hw;
7715 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
7716 struct qla_qpair *qpair = NULL;
0c9a5f3e 7717 struct scsi_qla_host *vp, *tvp;
5386a4e6
QT		 7718 fc_port_t *fcport;
7719 int i;
7720 unsigned long flags;
7721
f7a0ed47
QT		 7722 ql_dbg(ql_dbg_aer, vha, 0x9000,
7723 "%s\n", __func__);
5386a4e6
QT		 7724 ha->chip_reset++;
7725
7726 ha->base_qpair->chip_reset = ha->chip_reset;
7727 for (i = 0; i < ha->max_qpairs; i++) {
7728 if (ha->queue_pair_map[i])
7729 ha->queue_pair_map[i]->chip_reset =
7730 ha->base_qpair->chip_reset;
7731 }
7732
f7a0ed47
QT		 7733 /*
7734 * purge mailbox might take a while. Slot Reset/chip reset
7735 * will take care of the purge
7736 */
5386a4e6
QT		 7737
7738 mutex_lock(&ha->mq_lock);
f7a0ed47 7739 ha->base_qpair->online = 0;
5386a4e6
QT		 7740 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7741 qpair->online = 0;
f7a0ed47 7742 wmb();
5386a4e6
QT		 7743 mutex_unlock(&ha->mq_lock);
7744
3c75ad1d 7745 qla2x00_mark_all_devices_lost(vha);
5386a4e6
QT		 7746
7747 spin_lock_irqsave(&ha->vport_slock, flags);
0c9a5f3e 7748 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
5386a4e6
QT		 7749 atomic_inc(&vp->vref_count);
7750 spin_unlock_irqrestore(&ha->vport_slock, flags);
3c75ad1d 7751 qla2x00_mark_all_devices_lost(vp);
5386a4e6
QT		 7752 spin_lock_irqsave(&ha->vport_slock, flags);
7753 atomic_dec(&vp->vref_count);
7754 }
7755 spin_unlock_irqrestore(&ha->vport_slock, flags);
7756
7757 /* Clear all async request states across all VPs. */
7758 list_for_each_entry(fcport, &vha->vp_fcports, list)
7759 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7760
7761 spin_lock_irqsave(&ha->vport_slock, flags);
0c9a5f3e 7762 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
5386a4e6
QT		 7763 atomic_inc(&vp->vref_count);
7764 spin_unlock_irqrestore(&ha->vport_slock, flags);
7765 list_for_each_entry(fcport, &vp->vp_fcports, list)
7766 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7767 spin_lock_irqsave(&ha->vport_slock, flags);
7768 atomic_dec(&vp->vref_count);
7769 }
7770 spin_unlock_irqrestore(&ha->vport_slock, flags);
7771}
7772
7773
14e660e6
SJ		 7774static pci_ers_result_t
7775qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
7776{
85880801
AV		 7777 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
7778 struct qla_hw_data *ha = vha->hw;
f7a0ed47 7779 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET;
85880801 7780
f7a0ed47
QT		 7781 ql_log(ql_log_warn, vha, 0x9000,
7782 "PCI error detected, state %x.\n", state);
7783 ha->pci_error_state = QLA_PCI_ERR_DETECTED;
b9b12f73 7784
efdb5760
SC		 7785 if (!atomic_read(&pdev->enable_cnt)) {
7786 ql_log(ql_log_info, vha, 0xffff,
7787 "PCI device is disabled,state %x\n", state);
f7a0ed47
QT		 7788 ret = PCI_ERS_RESULT_NEED_RESET;
7789 goto out;
efdb5760
SC		 7790 }
7791
14e660e6
SJ		 7792 switch (state) {
7793 case pci_channel_io_normal:
e35920ab 7794 qla_pci_set_eeh_busy(vha);
c38d1baf 7795 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 7796 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7797 qla2xxx_wake_dpc(vha);
7798 }
f7a0ed47
QT		 7799 ret = PCI_ERS_RESULT_CAN_RECOVER;
7800 break;
14e660e6 7801 case pci_channel_io_frozen:
f7a0ed47
QT		 7802 qla_pci_set_eeh_busy(vha);
7803 ret = PCI_ERS_RESULT_NEED_RESET;
7804 break;
14e660e6 7805 case pci_channel_io_perm_failure:
85880801
AV		 7806 ha->flags.pci_channel_io_perm_failure = 1;
7807 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
c38d1baf 7808 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 7809 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7810 qla2xxx_wake_dpc(vha);
7811 }
f7a0ed47 7812 ret = PCI_ERS_RESULT_DISCONNECT;
14e660e6 7813 }
f7a0ed47
QT		 7814out:
7815 ql_dbg(ql_dbg_aer, vha, 0x600d,
7816 "PCI error detected returning [%x].\n", ret);
7817 return ret;
14e660e6
SJ		 7818}
7819
7820static pci_ers_result_t
7821qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
7822{
7823 int risc_paused = 0;
7824 uint32_t stat;
7825 unsigned long flags;
e315cd28
AC		 7826 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7827 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 7828 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7829 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
7830
f7a0ed47
QT		 7831 ql_log(ql_log_warn, base_vha, 0x9000,
7832 "mmio enabled\n");
7833
7834 ha->pci_error_state = QLA_PCI_MMIO_ENABLED;
e35920ab 7835
bcc5b6d3
SK		 7836 if (IS_QLA82XX(ha))
7837 return PCI_ERS_RESULT_RECOVERED;
7838
e35920ab
QT		 7839 if (qla2x00_isp_reg_stat(ha)) {
7840 ql_log(ql_log_info, base_vha, 0x803f,
7841 "During mmio enabled, PCI/Register disconnect still detected.\n");
7842 goto out;
7843 }
7844
14e660e6
SJ		 7845 spin_lock_irqsave(&ha->hardware_lock, flags);
7846 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
04474d3a 7847 stat = rd_reg_word(&reg->hccr);
14e660e6
SJ		 7848 if (stat & HCCR_RISC_PAUSE)
7849 risc_paused = 1;
7850 } else if (IS_QLA23XX(ha)) {
04474d3a 7851 stat = rd_reg_dword(&reg->u.isp2300.host_status);
14e660e6
SJ		 7852 if (stat & HSR_RISC_PAUSED)
7853 risc_paused = 1;
7854 } else if (IS_FWI2_CAPABLE(ha)) {
04474d3a 7855 stat = rd_reg_dword(&reg24->host_status);
14e660e6
SJ		 7856 if (stat & HSRX_RISC_PAUSED)
7857 risc_paused = 1;
7858 }
7859 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7860
7861 if (risc_paused) {
7c3df132
SK		 7862 ql_log(ql_log_info, base_vha, 0x9003,
7863 "RISC paused -- mmio_enabled, Dumping firmware.\n");
8ae17876 7864 qla2xxx_dump_fw(base_vha);
f7a0ed47 7865 }
e35920ab 7866out:
f7a0ed47
QT		 7867 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */
7868 ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7869 "mmio enabled returning.\n");
7870 return PCI_ERS_RESULT_NEED_RESET;
14e660e6
SJ		 7871}
7872
7873static pci_ers_result_t
7874qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7875{
7876 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 7877 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7878 struct qla_hw_data *ha = base_vha->hw;
5386a4e6
QT		 7879 int rc;
7880 struct qla_qpair *qpair = NULL;
09483916 7881
f7a0ed47
QT		 7882 ql_log(ql_log_warn, base_vha, 0x9004,
7883 "Slot Reset.\n");
85880801 7884
f7a0ed47 7885 ha->pci_error_state = QLA_PCI_SLOT_RESET;
90a86fc0
JC		 7886 /* Workaround: qla2xxx driver which access hardware earlier
7887 * needs error state to be pci_channel_io_online.
7888 * Otherwise mailbox command timesout.
7889 */
7890 pdev->error_state = pci_channel_io_normal;
7891
7892 pci_restore_state(pdev);
7893
8c1496bd
RL		 7894 /* pci_restore_state() clears the saved_state flag of the device
7895 * save restored state which resets saved_state flag
7896 */
7897 pci_save_state(pdev);
7898
09483916
BH		 7899 if (ha->mem_only)
7900 rc = pci_enable_device_mem(pdev);
7901 else
7902 rc = pci_enable_device(pdev);
14e660e6 7903
09483916 7904 if (rc) {
7c3df132 7905 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 7906 "Can't re-enable PCI device after reset.\n");
a5b36321 7907 goto exit_slot_reset;
14e660e6 7908 }
14e660e6 7909
90a86fc0 7910
e315cd28 7911 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 7912 goto exit_slot_reset;
7913
5386a4e6
QT		 7914 mutex_lock(&ha->mq_lock);
7915 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7916 qpair->online = 1;
7917 mutex_unlock(&ha->mq_lock);
85880801 7918
f7a0ed47 7919 ha->flags.eeh_busy = 0;
5386a4e6 7920 base_vha->flags.online = 1;
e315cd28 7921 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
f7a0ed47 7922 ha->isp_ops->abort_isp(base_vha);
e315cd28 7923 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 7924
f7a0ed47
QT		 7925 if (qla2x00_isp_reg_stat(ha)) {
7926 ha->flags.eeh_busy = 1;
7927 qla_pci_error_cleanup(base_vha);
7928 ql_log(ql_log_warn, base_vha, 0x9005,
7929 "Device unable to recover from PCI error.\n");
7930 } else {
7931 ret = PCI_ERS_RESULT_RECOVERED;
7932 }
90a86fc0 7933
a5b36321 7934exit_slot_reset:
7c3df132 7935 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
f7a0ed47 7936 "Slot Reset returning %x.\n", ret);
85880801 7937
14e660e6
SJ		 7938 return ret;
7939}
7940
7941static void
7942qla2xxx_pci_resume(struct pci_dev *pdev)
7943{
e315cd28
AC		 7944 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7945 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 7946 int ret;
7947
f7a0ed47
QT		 7948 ql_log(ql_log_warn, base_vha, 0x900f,
7949 "Pci Resume.\n");
85880801 7950
5386a4e6 7951
e315cd28 7952 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 7953 if (ret != QLA_SUCCESS) {
7c3df132
SK		 7954 ql_log(ql_log_fatal, base_vha, 0x9002,
7955 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 7956 }
f7a0ed47
QT		 7957 ha->pci_error_state = QLA_PCI_RESUME;
7958 ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7959 "Pci Resume returning.\n");
7960}
7961
7962void qla_pci_set_eeh_busy(struct scsi_qla_host *vha)
7963{
7964 struct qla_hw_data *ha = vha->hw;
7965 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
7966 bool do_cleanup = false;
7967 unsigned long flags;
7968
7969 if (ha->flags.eeh_busy)
7970 return;
7971
7972 spin_lock_irqsave(&base_vha->work_lock, flags);
7973 if (!ha->flags.eeh_busy) {
d3117c83
QT		 7974 ha->eeh_jif = jiffies;
7975 ha->flags.eeh_flush = 0;
7976
f7a0ed47
QT		 7977 ha->flags.eeh_busy = 1;
7978 do_cleanup = true;
7979 }
7980 spin_unlock_irqrestore(&base_vha->work_lock, flags);
7981
7982 if (do_cleanup)
7983 qla_pci_error_cleanup(base_vha);
7984}
7985
7986/*
7987 * this routine will schedule a task to pause IO from interrupt context
7988 * if caller sees a PCIE error event (register read = 0xf's)
7989 */
7990void qla_schedule_eeh_work(struct scsi_qla_host *vha)
7991{
7992 struct qla_hw_data *ha = vha->hw;
7993 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
7994
7995 if (ha->flags.eeh_busy)
7996 return;
7997
7998 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags);
7999 qla2xxx_wake_dpc(base_vha);
14e660e6
SJ		 8000}
8001
590f806d
QT		 8002static void
8003qla_pci_reset_prepare(struct pci_dev *pdev)
8004{
8005 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8006 struct qla_hw_data *ha = base_vha->hw;
8007 struct qla_qpair *qpair;
8008
8009 ql_log(ql_log_warn, base_vha, 0xffff,
8010 "%s.\n", __func__);
8011
8012 /*
8013 * PCI FLR/function reset is about to reset the
8014 * slot. Stop the chip to stop all DMA access.
8015 * It is assumed that pci_reset_done will be called
8016 * after FLR to resume Chip operation.
8017 */
8018 ha->flags.eeh_busy = 1;
8019 mutex_lock(&ha->mq_lock);
8020 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8021 qpair->online = 0;
8022 mutex_unlock(&ha->mq_lock);
8023
8024 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8025 qla2x00_abort_isp_cleanup(base_vha);
8026 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
8027}
8028
8029static void
8030qla_pci_reset_done(struct pci_dev *pdev)
8031{
8032 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8033 struct qla_hw_data *ha = base_vha->hw;
8034 struct qla_qpair *qpair;
8035
8036 ql_log(ql_log_warn, base_vha, 0xffff,
8037 "%s.\n", __func__);
8038
8039 /*
8040 * FLR just completed by PCI layer. Resume adapter
8041 */
8042 ha->flags.eeh_busy = 0;
8043 mutex_lock(&ha->mq_lock);
8044 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8045 qpair->online = 1;
8046 mutex_unlock(&ha->mq_lock);
8047
8048 base_vha->flags.online = 1;
8049 ha->isp_ops->abort_isp(base_vha);
8050 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8051}
8052
a4e1d0b7 8053static void qla2xxx_map_queues(struct Scsi_Host *shost)
5601236b
MH		 8054{
8055 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
485b0eca 8056 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
5601236b 8057
f3e02695 8058 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
a4e1d0b7 8059 blk_mq_map_queues(qmap);
d68b850e 8060 else
bd326a5a
DW		 8061 blk_mq_map_hw_queues(qmap, &vha->hw->pdev->dev,
8062 vha->irq_offset);
5601236b
MH		 8063}
8064
6515ad71
BVA		 8065struct scsi_host_template qla2xxx_driver_template = {
8066 .module = THIS_MODULE,
8067 .name = QLA2XXX_DRIVER_NAME,
8068 .queuecommand = qla2xxx_queuecommand,
8069
8070 .eh_timed_out = fc_eh_timed_out,
8071 .eh_abort_handler = qla2xxx_eh_abort,
000e68fa 8072 .eh_should_retry_cmd = fc_eh_should_retry_cmd,
6515ad71
BVA		 8073 .eh_device_reset_handler = qla2xxx_eh_device_reset,
8074 .eh_target_reset_handler = qla2xxx_eh_target_reset,
8075 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
8076 .eh_host_reset_handler = qla2xxx_eh_host_reset,
8077
49515b7f 8078 .sdev_configure = qla2xxx_sdev_configure,
6515ad71 8079
ed638918
BVA		 8080 .sdev_init = qla2xxx_sdev_init,
8081 .sdev_destroy = qla2xxx_sdev_destroy,
6515ad71
BVA		 8082 .scan_finished = qla2xxx_scan_finished,
8083 .scan_start = qla2xxx_scan_start,
8084 .change_queue_depth = scsi_change_queue_depth,
8085 .map_queues = qla2xxx_map_queues,
8086 .this_id = -1,
8087 .cmd_per_lun = 3,
8088 .sg_tablesize = SG_ALL,
8089
8090 .max_sectors = 0xFFFF,
66df386d 8091 .shost_groups = qla2x00_host_groups,
6515ad71
BVA		 8092
8093 .supported_mode = MODE_INITIATOR,
8094 .track_queue_depth = 1,
85cffefa 8095 .cmd_size = sizeof(srb_t),
6515ad71
BVA		 8096};
8097
a55b2d21 8098static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 8099 .error_detected = qla2xxx_pci_error_detected,
8100 .mmio_enabled = qla2xxx_pci_mmio_enabled,
8101 .slot_reset = qla2xxx_pci_slot_reset,
8102 .resume = qla2xxx_pci_resume,
590f806d
QT		 8103 .reset_prepare = qla_pci_reset_prepare,
8104 .reset_done = qla_pci_reset_done,
14e660e6
SJ		 8105};
8106
c9a71ca1 8107static const struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 8108 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
8109 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
8110 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
8111 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
8112 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
8113 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
8114 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
8115 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
8116 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 8117 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 8118 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
8119 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 8120 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 8121 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 8122 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 8123 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 8124 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 8125 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 8126 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 8127 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 8128 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 8129 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
ecc89f25
JC		 8130 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
8131 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
8132 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
8133 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
8134 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
5433383e
AV		 8135 { 0 },
8136};
8137MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
8138
fca29703 8139static struct pci_driver qla2xxx_pci_driver = {
cb63067a 8140 .name = QLA2XXX_DRIVER_NAME,
fca29703 8141 .id_table = qla2xxx_pci_tbl,
7ee61397 8142 .probe = qla2x00_probe_one,
4c993f76 8143 .remove = qla2x00_remove_one,
e30d1756 8144 .shutdown = qla2x00_shutdown,
14e660e6 8145 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 8146};
8147
75ef9de1 8148static const struct file_operations apidev_fops = {
6a03b4cd 8149 .owner = THIS_MODULE,
6038f373 8150 .llseek = noop_llseek,
6a03b4cd
HZ		 8151};
8152
1da177e4
LT		 8153/**
8154 * qla2x00_module_init - Module initialization.
8155 **/
8156static int __init
8157qla2x00_module_init(void)
8158{
fca29703
AV		 8159 int ret = 0;
8160
8a73a0e0 8161 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64);
bc04459c
BVA		 8162 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
8163 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
8164 BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
8165 BUILD_BUG_ON(sizeof(init_cb_t) != 96);
8a73a0e0 8166 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64);
bc04459c
BVA		 8167 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
8168 BUILD_BUG_ON(sizeof(request_t) != 64);
8a73a0e0
BVA		 8169 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64);
8170 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64);
8171 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64);
bc04459c 8172 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
8a73a0e0 8173 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64);
bc04459c
BVA		 8174 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
8175 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
8176 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
8177 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
8178 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
8179 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
8180 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
137316ba 8181 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604);
8a73a0e0
BVA		 8182 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424);
8183 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164);
8184 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260);
8185 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260);
8186 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16);
bc04459c 8187 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
8a73a0e0
BVA		 8188 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256);
8189 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24);
8190 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256);
8191 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288);
8192 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216);
bc04459c 8193 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
8a73a0e0 8194 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64);
bc04459c 8195 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
8a73a0e0 8196 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64);
bc04459c
BVA		 8197 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
8198 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
8a73a0e0
BVA		 8199 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64);
8200 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64);
8201 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252);
8202 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64);
8203 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512);
8204 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512);
bc04459c 8205 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
8a73a0e0
BVA		 8206 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64);
8207 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64);
8208 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634);
8209 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100);
8210 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976);
8211 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228);
8212 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52);
8213 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172);
8214 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524);
8215 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8);
8216 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12);
8217 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24);
8218 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420);
8219 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28);
8220 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32);
8221 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196);
d9ab5f1f 8222 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE);
8a73a0e0 8223 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128);
59d23cf3
BVA		 8224 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8);
8225 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16);
8a73a0e0
BVA		 8226 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24);
8227 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16);
8228 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336);
bc04459c 8229 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
8a73a0e0
BVA		 8230 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64);
8231 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64);
8232 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64);
bc04459c 8233 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
8a73a0e0 8234 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52);
bc04459c 8235 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
8a73a0e0
BVA		 8236 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64);
8237 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64);
8238 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64);
8239 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64);
8240 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64);
8241 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64);
8242 BUILD_BUG_ON(sizeof(sts_entry_t) != 64);
8243 BUILD_BUG_ON(sizeof(sw_info_t) != 32);
8244 BUILD_BUG_ON(sizeof(target_id_t) != 2);
bc04459c 8245
8bfc149b
AE		 8246 qla_trace_init();
8247
1da177e4 8248 /* Allocate cache for SRBs. */
354d6b21 8249 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 8250 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 8251 if (srb_cachep == NULL) {
7c3df132
SK		 8252 ql_log(ql_log_fatal, NULL, 0x0001,
8253 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 8254 return -ENOMEM;
8255 }
8256
2d70c103
NB		 8257 /* Initialize target kmem_cache and mem_pools */
8258 ret = qlt_init();
8259 if (ret < 0) {
c794d24e 8260 goto destroy_cache;
2d70c103
NB		 8261 } else if (ret > 0) {
8262 /*
8263 * If initiator mode is explictly disabled by qlt_init(),
8264 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
8265 * performing scsi_scan_target() during LOOP UP event.
8266 */
8267 qla2xxx_transport_functions.disable_target_scan = 1;
8268 qla2xxx_transport_vport_functions.disable_target_scan = 1;
8269 }
8270
1da177e4
LT		 8271 /* Derive version string. */
8272 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 8273 if (ql2xextended_error_logging)
0181944f 8274 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 8275 if (ql2xextended_error_logging == 1)
8276 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 8277
1c97a12a
AV		 8278 qla2xxx_transport_template =
8279 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f 8280 if (!qla2xxx_transport_template) {
7c3df132
SK		 8281 ql_log(ql_log_fatal, NULL, 0x0002,
8282 "fc_attach_transport failed...Failing load!.\n");
c794d24e
BVA		 8283 ret = -ENODEV;
8284 goto qlt_exit;
2c3dfe3f 8285 }
6a03b4cd
HZ		 8286
8287 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
8288 if (apidev_major < 0) {
7c3df132
SK		 8289 ql_log(ql_log_fatal, NULL, 0x0003,
8290 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 8291 }
8292
2c3dfe3f
SJ		 8293 qla2xxx_transport_vport_template =
8294 fc_attach_transport(&qla2xxx_transport_vport_functions);
8295 if (!qla2xxx_transport_vport_template) {
7c3df132
SK		 8296 ql_log(ql_log_fatal, NULL, 0x0004,
8297 "fc_attach_transport vport failed...Failing load!.\n");
c794d24e
BVA		 8298 ret = -ENODEV;
8299 goto unreg_chrdev;
2c3dfe3f 8300 }
7c3df132
SK		 8301 ql_log(ql_log_info, NULL, 0x0005,
8302 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 8303 qla2x00_version_str);
7ee61397 8304 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703 8305 if (ret) {
7c3df132
SK		 8306 ql_log(ql_log_fatal, NULL, 0x0006,
8307 "pci_register_driver failed...ret=%d Failing load!.\n",
8308 ret);
c794d24e 8309 goto release_vport_transport;
fca29703
AV		 8310 }
8311 return ret;
c794d24e
BVA		 8312
8313release_vport_transport:
8314 fc_release_transport(qla2xxx_transport_vport_template);
8315
8316unreg_chrdev:
8317 if (apidev_major >= 0)
8318 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8319 fc_release_transport(qla2xxx_transport_template);
8320
8321qlt_exit:
8322 qlt_exit();
8323
8324destroy_cache:
8325 kmem_cache_destroy(srb_cachep);
8bfc149b
AE		 8326
8327 qla_trace_uninit();
c794d24e 8328 return ret;
1da177e4
LT		 8329}
8330
8331/**
8332 * qla2x00_module_exit - Module cleanup.
8333 **/
8334static void __exit
8335qla2x00_module_exit(void)
8336{
7ee61397 8337 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 8338 qla2x00_release_firmware();
75c1d48a 8339 kmem_cache_destroy(ctx_cachep);
2c3dfe3f 8340 fc_release_transport(qla2xxx_transport_vport_template);
59c209a6
BVA		 8341 if (apidev_major >= 0)
8342 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8343 fc_release_transport(qla2xxx_transport_template);
8344 qlt_exit();
8345 kmem_cache_destroy(srb_cachep);
8bfc149b 8346 qla_trace_uninit();
1da177e4
LT		 8347}
8348
8349module_init(qla2x00_module_init);
8350module_exit(qla2x00_module_exit);
8351
8352MODULE_AUTHOR("QLogic Corporation");
8353MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
8354MODULE_LICENSE("GPL");
bb8ee499
AV		 8355MODULE_FIRMWARE(FW_FILE_ISP21XX);
8356MODULE_FIRMWARE(FW_FILE_ISP22XX);
8357MODULE_FIRMWARE(FW_FILE_ISP2300);
8358MODULE_FIRMWARE(FW_FILE_ISP2322);
8359MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 8360MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)