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[SCSI] mpt2sas: _scsih_smart_predicted_fault uses GFP_KERNEL in interrupt context
[linux-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
07e264b7 3 * Copyright (c) 2003-2011 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16
17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
22/*
23 * Driver version
24 */
25char qla2x00_version_str[40];
26
6a03b4cd
HZ		 27static int apidev_major;
28
1da177e4
LT		 29/*
30 * SRB allocation cache
31 */
e18b890b 32static struct kmem_cache *srb_cachep;
1da177e4 33
a9083016
GM		 34/*
35 * CT6 CTX allocation cache
36 */
37static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 38/*
39 * error level for logging
40 */
41int ql_errlev = ql_log_all;
a9083016 42
1da177e4 43int ql2xlogintimeout = 20;
f2019cb1 44module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 45MODULE_PARM_DESC(ql2xlogintimeout,
46 "Login timeout value in seconds.");
47
a7b61842 48int qlport_down_retry;
f2019cb1 49module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 50MODULE_PARM_DESC(qlport_down_retry,
900d9f98 51 "Maximum number of command retries to a port that returns "
1da177e4
LT		 52 "a PORT-DOWN status.");
53
1da177e4
LT		 54int ql2xplogiabsentdevice;
55module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
56MODULE_PARM_DESC(ql2xplogiabsentdevice,
57 "Option to enable PLOGI to devices that are not present after "
900d9f98 58 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 59 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
60
1da177e4 61int ql2xloginretrycount = 0;
f2019cb1 62module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 63MODULE_PARM_DESC(ql2xloginretrycount,
64 "Specify an alternate value for the NVRAM login retry count.");
65
a7a167bf 66int ql2xallocfwdump = 1;
f2019cb1 67module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 68MODULE_PARM_DESC(ql2xallocfwdump,
69 "Option to enable allocation of memory for a firmware dump "
70 "during HBA initialization. Memory allocation requirements "
71 "vary by ISP type. Default is 1 - allocate memory.");
72
11010fec 73int ql2xextended_error_logging;
27d94035 74module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 75MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 76 "Option to enable extended error logging,\n"
77 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
78 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
79 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
80 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
81 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
82 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
83 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
84 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
85 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
86 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 87
a9083016 88int ql2xshiftctondsd = 6;
f2019cb1 89module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 90MODULE_PARM_DESC(ql2xshiftctondsd,
91 "Set to control shifting of command type processing "
92 "based on total number of SG elements.");
93
1da177e4
LT		 94static void qla2x00_free_device(scsi_qla_host_t *);
95
7e47e5ca 96int ql2xfdmienable=1;
f2019cb1 97module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 98MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 99 "Enables FDMI registrations. "
100 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 101
df7baa50
AV		 102#define MAX_Q_DEPTH 32
103static int ql2xmaxqdepth = MAX_Q_DEPTH;
104module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
105MODULE_PARM_DESC(ql2xmaxqdepth,
106 "Maximum queue depth to report for target devices.");
107
bad75002 108/* Do not change the value of this after module load */
8cb2049c 109int ql2xenabledif = 0;
bad75002
AE		 110module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
111MODULE_PARM_DESC(ql2xenabledif,
112 " Enable T10-CRC-DIF "
8cb2049c
AE		 113 " Default is 0 - No DIF Support. 1 - Enable it"
114 ", 2 - Enable DIF for all types, except Type 0.");
bad75002 115
8cb2049c 116int ql2xenablehba_err_chk = 2;
bad75002
AE		 117module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
118MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c
AE		 119 " Enable T10-CRC-DIF Error isolation by HBA:\n"
120 " Default is 1.\n"
121 " 0 -- Error isolation disabled\n"
122 " 1 -- Error isolation enabled only for DIX Type 0\n"
123 " 2 -- Error isolation enabled for all Types\n");
bad75002 124
e5896bd5 125int ql2xiidmaenable=1;
f2019cb1 126module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 127MODULE_PARM_DESC(ql2xiidmaenable,
128 "Enables iIDMA settings "
129 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
130
73208dfd 131int ql2xmaxqueues = 1;
f2019cb1 132module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 133MODULE_PARM_DESC(ql2xmaxqueues,
134 "Enables MQ settings "
ae68230c
JP		 135 "Default is 1 for single queue. Set it to number "
136 "of queues in MQ mode.");
68ca949c
AC		 137
138int ql2xmultique_tag;
f2019cb1 139module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 140MODULE_PARM_DESC(ql2xmultique_tag,
141 "Enables CPU affinity settings for the driver "
142 "Default is 0 for no affinity of request and response IO. "
143 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 144
145int ql2xfwloadbin;
86e45bf6 146module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 147MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 148 "Option to specify location from which to load ISP firmware:.\n"
149 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 150 " interface.\n"
151 " 1 -- load firmware from flash.\n"
152 " 0 -- use default semantics.\n");
153
ae97c91e 154int ql2xetsenable;
f2019cb1 155module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 156MODULE_PARM_DESC(ql2xetsenable,
157 "Enables firmware ETS burst."
158 "Default is 0 - skip ETS enablement.");
159
6907869d 160int ql2xdbwr = 1;
86e45bf6 161module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 162MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 163 "Option to specify scheme for request queue posting.\n"
164 " 0 -- Regular doorbell.\n"
165 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 166
f4c496c1 167int ql2xtargetreset = 1;
f2019cb1 168module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 169MODULE_PARM_DESC(ql2xtargetreset,
170 "Enable target reset."
171 "Default is 1 - use hw defaults.");
172
4da26e16 173int ql2xgffidenable;
f2019cb1 174module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 175MODULE_PARM_DESC(ql2xgffidenable,
176 "Enables GFF_ID checks of port type. "
177 "Default is 0 - Do not use GFF_ID information.");
a9083016 178
3822263e 179int ql2xasynctmfenable;
f2019cb1 180module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 181MODULE_PARM_DESC(ql2xasynctmfenable,
182 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
183 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 184
185int ql2xdontresethba;
86e45bf6 186module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 187MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 188 "Option to specify reset behaviour.\n"
189 " 0 (Default) -- Reset on failure.\n"
190 " 1 -- Do not reset on failure.\n");
ed0de87c 191
82515920
AV		 192uint ql2xmaxlun = MAX_LUNS;
193module_param(ql2xmaxlun, uint, S_IRUGO);
194MODULE_PARM_DESC(ql2xmaxlun,
195 "Defines the maximum LU number to register with the SCSI "
196 "midlayer. Default is 65535.");
197
08de2844
GM		 198int ql2xmdcapmask = 0x1F;
199module_param(ql2xmdcapmask, int, S_IRUGO);
200MODULE_PARM_DESC(ql2xmdcapmask,
201 "Set the Minidump driver capture mask level. "
202 "Default is 0x7F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
203
204int ql2xmdenable;
205module_param(ql2xmdenable, int, S_IRUGO);
206MODULE_PARM_DESC(ql2xmdenable,
207 "Enable/disable MiniDump. "
208 "0 (Default) - MiniDump disabled. "
209 "1 - MiniDump enabled.");
210
1da177e4 211/*
fa2a1ce5 212 * SCSI host template entry points
1da177e4
LT		 213 */
214static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 215static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 216static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
217static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 218static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 219static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 220static int qla2xxx_eh_abort(struct scsi_cmnd *);
221static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 222static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 223static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
224static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 225
e881a172 226static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7
AV		 227static int qla2x00_change_queue_type(struct scsi_device *, int);
228
a5326f86 229struct scsi_host_template qla2xxx_driver_template = {
1da177e4 230 .module = THIS_MODULE,
cb63067a 231 .name = QLA2XXX_DRIVER_NAME,
a5326f86 232 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 233
234 .eh_abort_handler = qla2xxx_eh_abort,
235 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 236 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 237 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
238 .eh_host_reset_handler = qla2xxx_eh_host_reset,
239
240 .slave_configure = qla2xxx_slave_configure,
241
242 .slave_alloc = qla2xxx_slave_alloc,
243 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 244 .scan_finished = qla2xxx_scan_finished,
245 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 246 .change_queue_depth = qla2x00_change_queue_depth,
247 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 248 .this_id = -1,
249 .cmd_per_lun = 3,
250 .use_clustering = ENABLE_CLUSTERING,
251 .sg_tablesize = SG_ALL,
252
253 .max_sectors = 0xFFFF,
afb046e2 254 .shost_attrs = qla2x00_host_attrs,
fca29703
AV		 255};
256
1da177e4 257static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 258struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 259
1da177e4
LT		 260/* TODO Convert to inlines
261 *
262 * Timer routines
263 */
1da177e4 264
2c3dfe3f 265__inline__ void
e315cd28 266qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 267{
e315cd28
AC		 268 init_timer(&vha->timer);
269 vha->timer.expires = jiffies + interval * HZ;
270 vha->timer.data = (unsigned long)vha;
271 vha->timer.function = (void (*)(unsigned long))func;
272 add_timer(&vha->timer);
273 vha->timer_active = 1;
1da177e4
LT		 274}
275
276static inline void
e315cd28 277qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 278{
a9083016 279 /* Currently used for 82XX only. */
7c3df132
SK		 280 if (vha->device_flags & DFLG_DEV_FAILED) {
281 ql_dbg(ql_dbg_timer, vha, 0x600d,
282 "Device in a failed state, returning.\n");
a9083016 283 return;
7c3df132 284 }
a9083016 285
e315cd28 286 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 287}
288
a824ebb3 289static __inline__ void
e315cd28 290qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 291{
e315cd28
AC		 292 del_timer_sync(&vha->timer);
293 vha->timer_active = 0;
1da177e4
LT		 294}
295
1da177e4
LT		 296static int qla2x00_do_dpc(void *data);
297
298static void qla2x00_rst_aen(scsi_qla_host_t *);
299
73208dfd
AC		 300static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
301 struct req_que **, struct rsp_que **);
e30d1756 302static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28
AC		 303static void qla2x00_mem_free(struct qla_hw_data *);
304static void qla2x00_sp_free_dma(srb_t *);
1da177e4 305
1da177e4 306/* -------------------------------------------------------------------------- */
73208dfd
AC		 307static int qla2x00_alloc_queues(struct qla_hw_data *ha)
308{
7c3df132 309 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 310 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 311 GFP_KERNEL);
312 if (!ha->req_q_map) {
7c3df132
SK		 313 ql_log(ql_log_fatal, vha, 0x003b,
314 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 315 goto fail_req_map;
316 }
317
2afa19a9 318 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 319 GFP_KERNEL);
320 if (!ha->rsp_q_map) {
7c3df132
SK		 321 ql_log(ql_log_fatal, vha, 0x003c,
322 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 323 goto fail_rsp_map;
324 }
325 set_bit(0, ha->rsp_qid_map);
326 set_bit(0, ha->req_qid_map);
327 return 1;
328
329fail_rsp_map:
330 kfree(ha->req_q_map);
331 ha->req_q_map = NULL;
332fail_req_map:
333 return -ENOMEM;
334}
335
2afa19a9 336static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 337{
73208dfd
AC		 338 if (req && req->ring)
339 dma_free_coherent(&ha->pdev->dev,
340 (req->length + 1) * sizeof(request_t),
341 req->ring, req->dma);
342
343 kfree(req);
344 req = NULL;
345}
346
2afa19a9
AC		 347static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
348{
349 if (rsp && rsp->ring)
350 dma_free_coherent(&ha->pdev->dev,
351 (rsp->length + 1) * sizeof(response_t),
352 rsp->ring, rsp->dma);
353
354 kfree(rsp);
355 rsp = NULL;
356}
357
73208dfd
AC		 358static void qla2x00_free_queues(struct qla_hw_data *ha)
359{
360 struct req_que *req;
361 struct rsp_que *rsp;
362 int cnt;
363
2afa19a9 364 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 365 req = ha->req_q_map[cnt];
2afa19a9 366 qla2x00_free_req_que(ha, req);
73208dfd 367 }
73208dfd
AC		 368 kfree(ha->req_q_map);
369 ha->req_q_map = NULL;
2afa19a9
AC		 370
371 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
372 rsp = ha->rsp_q_map[cnt];
373 qla2x00_free_rsp_que(ha, rsp);
374 }
375 kfree(ha->rsp_q_map);
376 ha->rsp_q_map = NULL;
73208dfd
AC		 377}
378
68ca949c
AC		 379static int qla25xx_setup_mode(struct scsi_qla_host *vha)
380{
381 uint16_t options = 0;
382 int ques, req, ret;
383 struct qla_hw_data *ha = vha->hw;
384
7163ea81 385 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 386 ql_log(ql_log_warn, vha, 0x00d8,
387 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 388 goto fail;
389 }
68ca949c 390 if (ql2xmultique_tag) {
68ca949c
AC		 391 /* create a request queue for IO */
392 options |= BIT_7;
393 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
394 QLA_DEFAULT_QUE_QOS);
395 if (!req) {
7c3df132
SK		 396 ql_log(ql_log_warn, vha, 0x00e0,
397 "Failed to create request queue.\n");
68ca949c
AC		 398 goto fail;
399 }
278274d5 400 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 401 vha->req = ha->req_q_map[req];
402 options |= BIT_1;
403 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
404 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
405 if (!ret) {
7c3df132
SK		 406 ql_log(ql_log_warn, vha, 0x00e8,
407 "Failed to create response queue.\n");
68ca949c
AC		 408 goto fail2;
409 }
410 }
7163ea81 411 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 412 ql_dbg(ql_dbg_multiq, vha, 0xc007,
413 "CPU affinity mode enalbed, "
414 "no. of response queues:%d no. of request queues:%d.\n",
415 ha->max_rsp_queues, ha->max_req_queues);
416 ql_dbg(ql_dbg_init, vha, 0x00e9,
417 "CPU affinity mode enalbed, "
418 "no. of response queues:%d no. of request queues:%d.\n",
419 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 420 }
421 return 0;
422fail2:
423 qla25xx_delete_queues(vha);
7163ea81
AC		 424 destroy_workqueue(ha->wq);
425 ha->wq = NULL;
68ca949c
AC		 426fail:
427 ha->mqenable = 0;
7163ea81
AC		 428 kfree(ha->req_q_map);
429 kfree(ha->rsp_q_map);
430 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 431 return 1;
432}
433
1da177e4 434static char *
e315cd28 435qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 436{
e315cd28 437 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 438 static char *pci_bus_modes[] = {
439 "33", "66", "100", "133",
440 };
441 uint16_t pci_bus;
442
443 strcpy(str, "PCI");
444 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
445 if (pci_bus) {
446 strcat(str, "-X (");
447 strcat(str, pci_bus_modes[pci_bus]);
448 } else {
449 pci_bus = (ha->pci_attr & BIT_8) >> 8;
450 strcat(str, " (");
451 strcat(str, pci_bus_modes[pci_bus]);
452 }
453 strcat(str, " MHz)");
454
455 return (str);
456}
457
fca29703 458static char *
e315cd28 459qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 460{
461 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 462 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 463 uint32_t pci_bus;
464 int pcie_reg;
465
466 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
467 if (pcie_reg) {
468 char lwstr[6];
469 uint16_t pcie_lstat, lspeed, lwidth;
470
471 pcie_reg += 0x12;
472 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
473 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
474 lwidth = (pcie_lstat &
475 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
476
477 strcpy(str, "PCIe (");
478 if (lspeed == 1)
c87a0d8c 479 strcat(str, "2.5GT/s ");
c3a2f0df 480 else if (lspeed == 2)
c87a0d8c 481 strcat(str, "5.0GT/s ");
fca29703
AV		 482 else
483 strcat(str, "<unknown> ");
484 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
485 strcat(str, lwstr);
486
487 return str;
488 }
489
490 strcpy(str, "PCI");
491 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
492 if (pci_bus == 0 || pci_bus == 8) {
493 strcat(str, " (");
494 strcat(str, pci_bus_modes[pci_bus >> 3]);
495 } else {
496 strcat(str, "-X ");
497 if (pci_bus & BIT_2)
498 strcat(str, "Mode 2");
499 else
500 strcat(str, "Mode 1");
501 strcat(str, " (");
502 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
503 }
504 strcat(str, " MHz)");
505
506 return str;
507}
508
e5f82ab8 509static char *
e315cd28 510qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 511{
512 char un_str[10];
e315cd28 513 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 514
1da177e4
LT		 515 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
516 ha->fw_minor_version,
517 ha->fw_subminor_version);
518
519 if (ha->fw_attributes & BIT_9) {
520 strcat(str, "FLX");
521 return (str);
522 }
523
524 switch (ha->fw_attributes & 0xFF) {
525 case 0x7:
526 strcat(str, "EF");
527 break;
528 case 0x17:
529 strcat(str, "TP");
530 break;
531 case 0x37:
532 strcat(str, "IP");
533 break;
534 case 0x77:
535 strcat(str, "VI");
536 break;
537 default:
538 sprintf(un_str, "(%x)", ha->fw_attributes);
539 strcat(str, un_str);
540 break;
541 }
542 if (ha->fw_attributes & 0x100)
543 strcat(str, "X");
544
545 return (str);
546}
547
e5f82ab8 548static char *
e315cd28 549qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 550{
e315cd28 551 struct qla_hw_data *ha = vha->hw;
f0883ac6 552
3a03eb79
AV		 553 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
554 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 555 return str;
fca29703
AV		 556}
557
558static inline srb_t *
e315cd28 559qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport,
f5e3e40b 560 struct scsi_cmnd *cmd)
fca29703
AV		 561{
562 srb_t *sp;
e315cd28 563 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 564
565 sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC);
7c3df132
SK		 566 if (!sp) {
567 ql_log(ql_log_warn, vha, 0x3006,
568 "Memory allocation failed for sp.\n");
fca29703 569 return sp;
7c3df132 570 }
fca29703 571
083a469d 572 atomic_set(&sp->ref_count, 1);
fca29703
AV		 573 sp->fcport = fcport;
574 sp->cmd = cmd;
575 sp->flags = 0;
576 CMD_SP(cmd) = (void *)sp;
cf53b069 577 sp->ctx = NULL;
fca29703
AV		 578
579 return sp;
580}
581
1da177e4 582static int
f5e3e40b 583qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 584{
134ae078 585 scsi_qla_host_t *vha = shost_priv(host);
fca29703 586 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 587 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 588 struct qla_hw_data *ha = vha->hw;
589 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 590 srb_t *sp;
591 int rval;
592
85880801 593 if (ha->flags.eeh_busy) {
7c3df132
SK		 594 if (ha->flags.pci_channel_io_perm_failure) {
595 ql_dbg(ql_dbg_io, vha, 0x3001,
596 "PCI Channel IO permanent failure, exiting "
597 "cmd=%p.\n", cmd);
b9b12f73 598 cmd->result = DID_NO_CONNECT << 16;
7c3df132
SK		 599 } else {
600 ql_dbg(ql_dbg_io, vha, 0x3002,
601 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 602 cmd->result = DID_REQUEUE << 16;
7c3df132 603 }
14e660e6
SJ		 604 goto qc24_fail_command;
605 }
606
19a7b4ae
JSEC		 607 rval = fc_remote_port_chkready(rport);
608 if (rval) {
609 cmd->result = rval;
7c3df132
SK		 610 ql_dbg(ql_dbg_io, vha, 0x3003,
611 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
612 cmd, rval);
fca29703
AV		 613 goto qc24_fail_command;
614 }
615
bad75002
AE		 616 if (!vha->flags.difdix_supported &&
617 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 618 ql_dbg(ql_dbg_io, vha, 0x3004,
619 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
620 cmd);
bad75002
AE		 621 cmd->result = DID_NO_CONNECT << 16;
622 goto qc24_fail_command;
623 }
fca29703
AV		 624 if (atomic_read(&fcport->state) != FCS_ONLINE) {
625 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 626 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 627 ql_dbg(ql_dbg_io, vha, 0x3005,
628 "Returning DNC, fcport_state=%d loop_state=%d.\n",
629 atomic_read(&fcport->state),
630 atomic_read(&base_vha->loop_state));
fca29703
AV		 631 cmd->result = DID_NO_CONNECT << 16;
632 goto qc24_fail_command;
633 }
7b594131 634 goto qc24_target_busy;
fca29703
AV		 635 }
636
f5e3e40b 637 sp = qla2x00_get_new_sp(base_vha, fcport, cmd);
fca29703 638 if (!sp)
f5e3e40b 639 goto qc24_host_busy;
fca29703 640
e315cd28 641 rval = ha->isp_ops->start_scsi(sp);
7c3df132
SK		 642 if (rval != QLA_SUCCESS) {
643 ql_dbg(ql_dbg_io, vha, 0x3013,
644 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 645 goto qc24_host_busy_free_sp;
7c3df132 646 }
fca29703 647
fca29703
AV		 648 return 0;
649
650qc24_host_busy_free_sp:
e315cd28
AC		 651 qla2x00_sp_free_dma(sp);
652 mempool_free(sp, ha->srb_mempool);
fca29703 653
f5e3e40b 654qc24_host_busy:
fca29703
AV		 655 return SCSI_MLQUEUE_HOST_BUSY;
656
7b594131
MC		 657qc24_target_busy:
658 return SCSI_MLQUEUE_TARGET_BUSY;
659
fca29703 660qc24_fail_command:
f5e3e40b 661 cmd->scsi_done(cmd);
fca29703
AV		 662
663 return 0;
664}
665
1da177e4
LT		 666/*
667 * qla2x00_eh_wait_on_command
668 * Waits for the command to be returned by the Firmware for some
669 * max time.
670 *
671 * Input:
1da177e4 672 * cmd = Scsi Command to wait on.
1da177e4
LT		 673 *
674 * Return:
675 * Not Found : 0
676 * Found : 1
677 */
678static int
e315cd28 679qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 680{
fe74c71f
AV		 681#define ABORT_POLLING_PERIOD 1000
682#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 683 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 684 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
685 struct qla_hw_data *ha = vha->hw;
f4f051eb 686 int ret = QLA_SUCCESS;
1da177e4 687
85880801 688 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 689 ql_dbg(ql_dbg_taskm, vha, 0x8005,
690 "Return:eh_wait.\n");
85880801
AV		 691 return ret;
692 }
693
d970432c 694 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 695 msleep(ABORT_POLLING_PERIOD);
f4f051eb 696 }
697 if (CMD_SP(cmd))
698 ret = QLA_FUNCTION_FAILED;
1da177e4 699
f4f051eb 700 return ret;
1da177e4
LT		 701}
702
703/*
704 * qla2x00_wait_for_hba_online
fa2a1ce5 705 * Wait till the HBA is online after going through
1da177e4
LT		 706 * <= MAX_RETRIES_OF_ISP_ABORT or
707 * finally HBA is disabled ie marked offline
708 *
709 * Input:
710 * ha - pointer to host adapter structure
fa2a1ce5
AV		 711 *
712 * Note:
1da177e4
LT		 713 * Does context switching-Release SPIN_LOCK
714 * (if any) before calling this routine.
715 *
716 * Return:
717 * Success (Adapter is online) : 0
718 * Failed (Adapter is offline/disabled) : 1
719 */
854165f4 720int
e315cd28 721qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 722{
fca29703
AV		 723 int return_status;
724 unsigned long wait_online;
e315cd28
AC		 725 struct qla_hw_data *ha = vha->hw;
726 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 727
fa2a1ce5 728 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 729 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
730 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
731 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
732 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 733
734 msleep(1000);
735 }
e315cd28 736 if (base_vha->flags.online)
fa2a1ce5 737 return_status = QLA_SUCCESS;
1da177e4
LT		 738 else
739 return_status = QLA_FUNCTION_FAILED;
740
1da177e4
LT		 741 return (return_status);
742}
743
86fbee86
LC		 744/*
745 * qla2x00_wait_for_reset_ready
746 * Wait till the HBA is online after going through
747 * <= MAX_RETRIES_OF_ISP_ABORT or
748 * finally HBA is disabled ie marked offline or flash
749 * operations are in progress.
750 *
751 * Input:
752 * ha - pointer to host adapter structure
753 *
754 * Note:
755 * Does context switching-Release SPIN_LOCK
756 * (if any) before calling this routine.
757 *
758 * Return:
759 * Success (Adapter is online/no flash ops) : 0
760 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
761 */
3dbe756a 762static int
86fbee86
LC		 763qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
764{
765 int return_status;
766 unsigned long wait_online;
767 struct qla_hw_data *ha = vha->hw;
768 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
769
770 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
771 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
772 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
773 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
774 ha->optrom_state != QLA_SWAITING ||
775 ha->dpc_active) && time_before(jiffies, wait_online))
776 msleep(1000);
777
778 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
779 return_status = QLA_SUCCESS;
780 else
781 return_status = QLA_FUNCTION_FAILED;
782
7c3df132
SK		 783 ql_dbg(ql_dbg_taskm, vha, 0x8019,
784 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 785
786 return return_status;
787}
788
2533cf67
LC		 789int
790qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
791{
792 int return_status;
793 unsigned long wait_reset;
794 struct qla_hw_data *ha = vha->hw;
795 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
796
797 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
798 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
799 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
800 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
801 ha->dpc_active) && time_before(jiffies, wait_reset)) {
802
803 msleep(1000);
804
805 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
806 ha->flags.chip_reset_done)
807 break;
808 }
809 if (ha->flags.chip_reset_done)
810 return_status = QLA_SUCCESS;
811 else
812 return_status = QLA_FUNCTION_FAILED;
813
814 return return_status;
815}
816
1da177e4
LT		 817/*
818 * qla2x00_wait_for_loop_ready
819 * Wait for MAX_LOOP_TIMEOUT(5 min) value for loop
fa2a1ce5 820 * to be in LOOP_READY state.
1da177e4
LT		 821 * Input:
822 * ha - pointer to host adapter structure
fa2a1ce5
AV		 823 *
824 * Note:
1da177e4
LT		 825 * Does context switching-Release SPIN_LOCK
826 * (if any) before calling this routine.
fa2a1ce5 827 *
1da177e4
LT		 828 *
829 * Return:
830 * Success (LOOP_READY) : 0
831 * Failed (LOOP_NOT_READY) : 1
832 */
fa2a1ce5 833static inline int
e315cd28 834qla2x00_wait_for_loop_ready(scsi_qla_host_t *vha)
1da177e4
LT		 835{
836 int return_status = QLA_SUCCESS;
837 unsigned long loop_timeout ;
e315cd28
AC		 838 struct qla_hw_data *ha = vha->hw;
839 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 840
841 /* wait for 5 min at the max for loop to be ready */
fa2a1ce5 842 loop_timeout = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1da177e4 843
e315cd28
AC		 844 while ((!atomic_read(&base_vha->loop_down_timer) &&
845 atomic_read(&base_vha->loop_state) == LOOP_DOWN) ||
846 atomic_read(&base_vha->loop_state) != LOOP_READY) {
847 if (atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
57680080
RA		 848 return_status = QLA_FUNCTION_FAILED;
849 break;
850 }
1da177e4
LT		 851 msleep(1000);
852 if (time_after_eq(jiffies, loop_timeout)) {
853 return_status = QLA_FUNCTION_FAILED;
854 break;
855 }
856 }
fa2a1ce5 857 return (return_status);
1da177e4
LT		 858}
859
083a469d
GM		 860static void
861sp_get(struct srb *sp)
862{
863 atomic_inc(&sp->ref_count);
864}
865
1da177e4
LT		 866/**************************************************************************
867* qla2xxx_eh_abort
868*
869* Description:
870* The abort function will abort the specified command.
871*
872* Input:
873* cmd = Linux SCSI command packet to be aborted.
874*
875* Returns:
876* Either SUCCESS or FAILED.
877*
878* Note:
2ea00202 879* Only return FAILED if command not returned by firmware.
1da177e4 880**************************************************************************/
e5f82ab8 881static int
1da177e4
LT		 882qla2xxx_eh_abort(struct scsi_cmnd *cmd)
883{
e315cd28 884 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 885 srb_t *sp;
4e98d3b8 886 int ret;
f4f051eb 887 unsigned int id, lun;
18e144d3 888 unsigned long flags;
2ea00202 889 int wait = 0;
e315cd28 890 struct qla_hw_data *ha = vha->hw;
1da177e4 891
7c3df132
SK		 892 ql_dbg(ql_dbg_taskm, vha, 0x8000,
893 "Entered %s for cmd=%p.\n", __func__, cmd);
f4f051eb 894 if (!CMD_SP(cmd))
2ea00202 895 return SUCCESS;
1da177e4 896
4e98d3b8 897 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 898 ql_dbg(ql_dbg_taskm, vha, 0x8001,
899 "Return value of fc_block_scsi_eh=%d.\n", ret);
4e98d3b8
AV		 900 if (ret != 0)
901 return ret;
902 ret = SUCCESS;
903
f4f051eb 904 id = cmd->device->id;
905 lun = cmd->device->lun;
1da177e4 906
e315cd28 907 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 908 sp = (srb_t *) CMD_SP(cmd);
909 if (!sp) {
910 spin_unlock_irqrestore(&ha->hardware_lock, flags);
911 return SUCCESS;
912 }
1da177e4 913
7c3df132
SK		 914 ql_dbg(ql_dbg_taskm, vha, 0x8002,
915 "Aborting sp=%p cmd=%p from RISC ", sp, cmd);
17d98630 916
170babc3
MC		 917 /* Get a reference to the sp and drop the lock.*/
918 sp_get(sp);
083a469d 919
e315cd28 920 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 921 if (ha->isp_ops->abort_command(sp)) {
7c3df132
SK		 922 ql_dbg(ql_dbg_taskm, vha, 0x8003,
923 "Abort command mbx failed for cmd=%p.\n", cmd);
170babc3 924 } else {
7c3df132
SK		 925 ql_dbg(ql_dbg_taskm, vha, 0x8004,
926 "Abort command mbx success.\n");
170babc3
MC		 927 wait = 1;
928 }
75942064
SK		 929
930 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3 931 qla2x00_sp_compl(ha, sp);
75942064 932 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 933
bc91ade9
CD		 934 /* Did the command return during mailbox execution? */
935 if (ret == FAILED && !CMD_SP(cmd))
936 ret = SUCCESS;
937
f4f051eb 938 /* Wait for the command to be returned. */
2ea00202 939 if (wait) {
e315cd28 940 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132
SK		 941 ql_log(ql_log_warn, vha, 0x8006,
942 "Abort handler timed out for cmd=%p.\n", cmd);
2ea00202 943 ret = FAILED;
f4f051eb 944 }
1da177e4 945 }
1da177e4 946
7c3df132
SK		 947 ql_log(ql_log_info, vha, 0x801c,
948 "Abort command issued -- %d %x.\n", wait, ret);
1da177e4 949
f4f051eb 950 return ret;
951}
1da177e4 952
4d78c973 953int
e315cd28 954qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 955 unsigned int l, enum nexus_wait_type type)
f4f051eb 956{
17d98630 957 int cnt, match, status;
18e144d3 958 unsigned long flags;
e315cd28 959 struct qla_hw_data *ha = vha->hw;
73208dfd 960 struct req_que *req;
4d78c973 961 srb_t *sp;
1da177e4 962
523ec773 963 status = QLA_SUCCESS;
17d98630 964
e315cd28 965 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 966 req = vha->req;
17d98630
AC		 967 for (cnt = 1; status == QLA_SUCCESS &&
968 cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
969 sp = req->outstanding_cmds[cnt];
970 if (!sp)
523ec773 971 continue;
bad75002 972 if ((sp->ctx) && !IS_PROT_IO(sp))
cf53b069 973 continue;
17d98630
AC		 974 if (vha->vp_idx != sp->fcport->vha->vp_idx)
975 continue;
976 match = 0;
977 switch (type) {
978 case WAIT_HOST:
979 match = 1;
980 break;
981 case WAIT_TARGET:
982 match = sp->cmd->device->id == t;
983 break;
984 case WAIT_LUN:
985 match = (sp->cmd->device->id == t &&
986 sp->cmd->device->lun == l);
987 break;
73208dfd 988 }
17d98630
AC		 989 if (!match)
990 continue;
991
992 spin_unlock_irqrestore(&ha->hardware_lock, flags);
993 status = qla2x00_eh_wait_on_command(sp->cmd);
994 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 995 }
e315cd28 996 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 997
998 return status;
1da177e4
LT		 999}
1000
523ec773
AV		 1001static char *reset_errors[] = {
1002 "HBA not online",
1003 "HBA not ready",
1004 "Task management failed",
1005 "Waiting for command completions",
1006};
1da177e4 1007
e5f82ab8 1008static int
523ec773 1009__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 1010 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 1011{
e315cd28 1012 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1013 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1014 int err;
1da177e4 1015
7c3df132
SK		 1016 if (!fcport) {
1017 ql_log(ql_log_warn, vha, 0x8007,
1018 "fcport is NULL.\n");
523ec773 1019 return FAILED;
7c3df132 1020 }
1da177e4 1021
4e98d3b8 1022 err = fc_block_scsi_eh(cmd);
7c3df132
SK		 1023 ql_dbg(ql_dbg_taskm, vha, 0x8008,
1024 "fc_block_scsi_eh ret=%d.\n", err);
4e98d3b8
AV		 1025 if (err != 0)
1026 return err;
1027
7c3df132
SK		 1028 ql_log(ql_log_info, vha, 0x8009,
1029 "%s RESET ISSUED for id %d lun %d cmd=%p.\n", name,
1030 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1031
523ec773 1032 err = 0;
7c3df132
SK		 1033 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1034 ql_log(ql_log_warn, vha, 0x800a,
1035 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1036 goto eh_reset_failed;
7c3df132 1037 }
523ec773 1038 err = 1;
7c3df132
SK		 1039 if (qla2x00_wait_for_loop_ready(vha) != QLA_SUCCESS) {
1040 ql_log(ql_log_warn, vha, 0x800b,
1041 "Wait for loop ready failed for cmd=%p.\n", cmd);
523ec773 1042 goto eh_reset_failed;
7c3df132 1043 }
523ec773 1044 err = 2;
2afa19a9 1045 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1046 != QLA_SUCCESS) {
1047 ql_log(ql_log_warn, vha, 0x800c,
1048 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1049 goto eh_reset_failed;
7c3df132 1050 }
523ec773 1051 err = 3;
e315cd28 1052 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1053 cmd->device->lun, type) != QLA_SUCCESS) {
1054 ql_log(ql_log_warn, vha, 0x800d,
1055 "wait for peding cmds failed for cmd=%p.\n", cmd);
523ec773 1056 goto eh_reset_failed;
7c3df132 1057 }
523ec773 1058
7c3df132
SK		 1059 ql_log(ql_log_info, vha, 0x800e,
1060 "%s RESET SUCCEEDED for id %d lun %d cmd=%p.\n", name,
1061 cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1062
1063 return SUCCESS;
1064
4d78c973 1065eh_reset_failed:
7c3df132
SK		 1066 ql_log(ql_log_info, vha, 0x800f,
1067 "%s RESET FAILED: %s for id %d lun %d cmd=%p.\n", name,
1068 reset_errors[err], cmd->device->id, cmd->device->lun);
523ec773
AV		 1069 return FAILED;
1070}
1da177e4 1071
523ec773
AV		 1072static int
1073qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1074{
e315cd28
AC		 1075 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1076 struct qla_hw_data *ha = vha->hw;
1da177e4 1077
523ec773
AV		 1078 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1079 ha->isp_ops->lun_reset);
1da177e4
LT		 1080}
1081
1da177e4 1082static int
523ec773 1083qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1084{
e315cd28
AC		 1085 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1086 struct qla_hw_data *ha = vha->hw;
1da177e4 1087
523ec773
AV		 1088 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1089 ha->isp_ops->target_reset);
1da177e4
LT		 1090}
1091
1da177e4
LT		 1092/**************************************************************************
1093* qla2xxx_eh_bus_reset
1094*
1095* Description:
1096* The bus reset function will reset the bus and abort any executing
1097* commands.
1098*
1099* Input:
1100* cmd = Linux SCSI command packet of the command that cause the
1101* bus reset.
1102*
1103* Returns:
1104* SUCCESS/FAILURE (defined as macro in scsi.h).
1105*
1106**************************************************************************/
e5f82ab8 1107static int
1da177e4
LT		 1108qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1109{
e315cd28 1110 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1111 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1112 int ret = FAILED;
f4f051eb 1113 unsigned int id, lun;
f4f051eb 1114
f4f051eb 1115 id = cmd->device->id;
1116 lun = cmd->device->lun;
1da177e4 1117
7c3df132
SK		 1118 if (!fcport) {
1119 ql_log(ql_log_warn, vha, 0x8010,
1120 "fcport is NULL.\n");
f4f051eb 1121 return ret;
7c3df132 1122 }
1da177e4 1123
4e98d3b8 1124 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 1125 ql_dbg(ql_dbg_taskm, vha, 0x8011,
1126 "fc_block_scsi_eh ret=%d.\n", ret);
4e98d3b8
AV		 1127 if (ret != 0)
1128 return ret;
1129 ret = FAILED;
1130
7c3df132
SK		 1131 ql_log(ql_log_info, vha, 0x8012,
1132 "BUS RESET ISSUED for id %d lun %d.\n", id, lun);
1da177e4 1133
e315cd28 1134 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1135 ql_log(ql_log_fatal, vha, 0x8013,
1136 "Wait for hba online failed board disabled.\n");
f4f051eb 1137 goto eh_bus_reset_done;
1da177e4
LT		 1138 }
1139
e315cd28
AC		 1140 if (qla2x00_wait_for_loop_ready(vha) == QLA_SUCCESS) {
1141 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
f4f051eb 1142 ret = SUCCESS;
1da177e4 1143 }
f4f051eb 1144 if (ret == FAILED)
1145 goto eh_bus_reset_done;
1da177e4 1146
9a41a62b 1147 /* Flush outstanding commands. */
4d78c973 1148 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1149 QLA_SUCCESS) {
1150 ql_log(ql_log_warn, vha, 0x8014,
1151 "Wait for pending commands failed.\n");
9a41a62b 1152 ret = FAILED;
7c3df132 1153 }
1da177e4 1154
f4f051eb 1155eh_bus_reset_done:
7c3df132
SK		 1156 ql_log(ql_log_warn, vha, 0x802b,
1157 "BUS RESET %s.\n", (ret == FAILED) ? "FAILED" : "SUCCEDED");
1da177e4 1158
f4f051eb 1159 return ret;
1da177e4
LT		 1160}
1161
1162/**************************************************************************
1163* qla2xxx_eh_host_reset
1164*
1165* Description:
1166* The reset function will reset the Adapter.
1167*
1168* Input:
1169* cmd = Linux SCSI command packet of the command that cause the
1170* adapter reset.
1171*
1172* Returns:
1173* Either SUCCESS or FAILED.
1174*
1175* Note:
1176**************************************************************************/
e5f82ab8 1177static int
1da177e4
LT		 1178qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1179{
e315cd28 1180 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1181 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
e315cd28 1182 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1183 int ret = FAILED;
f4f051eb 1184 unsigned int id, lun;
e315cd28 1185 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1186
f4f051eb 1187 id = cmd->device->id;
1188 lun = cmd->device->lun;
f4f051eb 1189
7c3df132
SK		 1190 if (!fcport) {
1191 ql_log(ql_log_warn, vha, 0x8016,
1192 "fcport is NULL.\n");
f4f051eb 1193 return ret;
7c3df132 1194 }
1da177e4 1195
4e98d3b8 1196 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 1197 ql_dbg(ql_dbg_taskm, vha, 0x8017,
1198 "fc_block_scsi_eh ret=%d.\n", ret);
4e98d3b8
AV		 1199 if (ret != 0)
1200 return ret;
1201 ret = FAILED;
1202
7c3df132
SK		 1203 ql_log(ql_log_info, vha, 0x8018,
1204 "ADAPTER RESET ISSUED for id %d lun %d.\n", id, lun);
1da177e4 1205
86fbee86 1206 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1207 goto eh_host_reset_lock;
1da177e4
LT		 1208
1209 /*
1210 * Fixme-may be dpc thread is active and processing
fa2a1ce5 1211 * loop_resync,so wait a while for it to
1da177e4
LT		 1212 * be completed and then issue big hammer.Otherwise
1213 * it may cause I/O failure as big hammer marks the
1214 * devices as lost kicking of the port_down_timer
1215 * while dpc is stuck for the mailbox to complete.
1216 */
e315cd28
AC		 1217 qla2x00_wait_for_loop_ready(vha);
1218 if (vha != base_vha) {
1219 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1220 goto eh_host_reset_lock;
e315cd28 1221 } else {
a9083016
GM		 1222 if (IS_QLA82XX(vha->hw)) {
1223 if (!qla82xx_fcoe_ctx_reset(vha)) {
1224 /* Ctx reset success */
1225 ret = SUCCESS;
1226 goto eh_host_reset_lock;
1227 }
1228 /* fall thru if ctx reset failed */
1229 }
68ca949c
AC		 1230 if (ha->wq)
1231 flush_workqueue(ha->wq);
1232
e315cd28 1233 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1234 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1235 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1236 /* failed. schedule dpc to try */
1237 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1238
7c3df132
SK		 1239 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1240 ql_log(ql_log_warn, vha, 0x802a,
1241 "wait for hba online failed.\n");
e315cd28 1242 goto eh_host_reset_lock;
7c3df132 1243 }
e315cd28
AC		 1244 }
1245 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1246 }
1da177e4 1247
e315cd28 1248 /* Waiting for command to be returned to OS.*/
4d78c973 1249 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1250 QLA_SUCCESS)
f4f051eb 1251 ret = SUCCESS;
1da177e4 1252
f4f051eb 1253eh_host_reset_lock:
7c3df132 1254 qla_printk(KERN_INFO, ha, "%s: reset %s.\n", __func__,
25985edc 1255 (ret == FAILED) ? "failed" : "succeeded");
1da177e4 1256
f4f051eb 1257 return ret;
1258}
1da177e4
LT		 1259
1260/*
1261* qla2x00_loop_reset
1262* Issue loop reset.
1263*
1264* Input:
1265* ha = adapter block pointer.
1266*
1267* Returns:
1268* 0 = success
1269*/
a4722cf2 1270int
e315cd28 1271qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1272{
0c8c39af 1273 int ret;
bdf79621 1274 struct fc_port *fcport;
e315cd28 1275 struct qla_hw_data *ha = vha->hw;
1da177e4 1276
f4c496c1 1277 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1278 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1279 if (fcport->port_type != FCT_TARGET)
1280 continue;
1281
1282 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1283 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1284 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1285 "Bus Reset failed: Target Reset=%d "
1286 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1287 }
1288 }
1289 }
1290
a9083016 1291 if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) {
e315cd28 1292 ret = qla2x00_full_login_lip(vha);
0c8c39af 1293 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1294 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1295 "full_login_lip=%d.\n", ret);
749af3d5
AC		 1296 }
1297 atomic_set(&vha->loop_state, LOOP_DOWN);
1298 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1299 qla2x00_mark_all_devices_lost(vha, 0);
1300 qla2x00_wait_for_loop_ready(vha);
0c8c39af
AV		 1301 }
1302
0d6e61bc 1303 if (ha->flags.enable_lip_reset) {
e315cd28 1304 ret = qla2x00_lip_reset(vha);
0c8c39af 1305 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1306 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1307 "lip_reset failed (%d).\n", ret);
e315cd28
AC		 1308 } else
1309 qla2x00_wait_for_loop_ready(vha);
1da177e4
LT		 1310 }
1311
1da177e4 1312 /* Issue marker command only when we are going to start the I/O */
e315cd28 1313 vha->marker_needed = 1;
1da177e4 1314
0c8c39af 1315 return QLA_SUCCESS;
1da177e4
LT		 1316}
1317
df4bf0bb 1318void
e315cd28 1319qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1320{
73208dfd 1321 int que, cnt;
df4bf0bb
AV		 1322 unsigned long flags;
1323 srb_t *sp;
ac280b67 1324 struct srb_ctx *ctx;
e315cd28 1325 struct qla_hw_data *ha = vha->hw;
73208dfd 1326 struct req_que *req;
df4bf0bb
AV		 1327
1328 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1329 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1330 req = ha->req_q_map[que];
73208dfd
AC		 1331 if (!req)
1332 continue;
1333 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
1334 sp = req->outstanding_cmds[cnt];
e612d465 1335 if (sp) {
73208dfd 1336 req->outstanding_cmds[cnt] = NULL;
a9083016 1337 if (!sp->ctx ||
bad75002
AE		 1338 (sp->flags & SRB_FCP_CMND_DMA_VALID) ||
1339 IS_PROT_IO(sp)) {
ac280b67
AV		 1340 sp->cmd->result = res;
1341 qla2x00_sp_compl(ha, sp);
1342 } else {
1343 ctx = sp->ctx;
9bfacd01
RD		 1344 if (ctx->type == SRB_ELS_CMD_RPT ||
1345 ctx->type == SRB_ELS_CMD_HST ||
1346 ctx->type == SRB_CT_CMD) {
6c452a45 1347 struct fc_bsg_job *bsg_job =
4916392b 1348 ctx->u.bsg_job;
6c452a45
AV		 1349 if (bsg_job->request->msgcode
1350 == FC_BSG_HST_CT)
db3ad7f8 1351 kfree(sp->fcport);
6c452a45
AV		 1352 bsg_job->req->errors = 0;
1353 bsg_job->reply->result = res;
4916392b 1354 bsg_job->job_done(bsg_job);
db3ad7f8 1355 kfree(sp->ctx);
6c452a45 1356 mempool_free(sp,
4916392b 1357 ha->srb_mempool);
9bfacd01
RD		 1358 } else {
1359 ctx->u.iocb_cmd->free(sp);
db3ad7f8 1360 }
ac280b67 1361 }
73208dfd 1362 }
df4bf0bb
AV		 1363 }
1364 }
1365 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1366}
1367
f4f051eb 1368static int
1369qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1370{
bdf79621 1371 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1372
19a7b4ae 1373 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1374 return -ENXIO;
bdf79621 1375
19a7b4ae 1376 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1377
f4f051eb 1378 return 0;
1379}
1da177e4 1380
f4f051eb 1381static int
1382qla2xxx_slave_configure(struct scsi_device *sdev)
1383{
e315cd28 1384 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1385 struct req_que *req = vha->req;
8482e118 1386
f4f051eb 1387 if (sdev->tagged_supported)
73208dfd 1388 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1389 else
73208dfd 1390 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb 1391 return 0;
1392}
1da177e4 1393
f4f051eb 1394static void
1395qla2xxx_slave_destroy(struct scsi_device *sdev)
1396{
1397 sdev->hostdata = NULL;
1da177e4
LT		 1398}
1399
c45dd305
GM		 1400static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1401{
1402 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1403
1404 if (!scsi_track_queue_full(sdev, qdepth))
1405 return;
1406
7c3df132
SK		 1407 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
1408 "Queue depth adjusted-down "
1409 "to %d for scsi(%ld:%d:%d:%d).\n",
1410 sdev->queue_depth, fcport->vha->host_no,
1411 sdev->channel, sdev->id, sdev->lun);
c45dd305
GM		 1412}
1413
1414static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1415{
1416 fc_port_t *fcport = sdev->hostdata;
1417 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1418 struct req_que *req = NULL;
1419
1420 req = vha->req;
1421 if (!req)
1422 return;
1423
1424 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1425 return;
1426
1427 if (sdev->ordered_tags)
1428 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1429 else
1430 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1431
7c3df132
SK		 1432 ql_dbg(ql_dbg_io, vha, 0x302a,
1433 "Queue depth adjusted-up to %d for "
1434 "scsi(%ld:%d:%d:%d).\n",
1435 sdev->queue_depth, fcport->vha->host_no,
1436 sdev->channel, sdev->id, sdev->lun);
c45dd305
GM		 1437}
1438
ce7e4af7 1439static int
e881a172 1440qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1441{
c45dd305
GM		 1442 switch (reason) {
1443 case SCSI_QDEPTH_DEFAULT:
1444 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1445 break;
1446 case SCSI_QDEPTH_QFULL:
1447 qla2x00_handle_queue_full(sdev, qdepth);
1448 break;
1449 case SCSI_QDEPTH_RAMP_UP:
1450 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1451 break;
1452 default:
08002af2 1453 return -EOPNOTSUPP;
c45dd305 1454 }
e881a172 1455
ce7e4af7
AV		 1456 return sdev->queue_depth;
1457}
1458
1459static int
1460qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1461{
1462 if (sdev->tagged_supported) {
1463 scsi_set_tag_type(sdev, tag_type);
1464 if (tag_type)
1465 scsi_activate_tcq(sdev, sdev->queue_depth);
1466 else
1467 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1468 } else
1469 tag_type = 0;
1470
1471 return tag_type;
1472}
1473
1da177e4
LT		 1474/**
1475 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1476 * @ha: HA context
1477 *
1478 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1479 * supported addressing method.
1480 */
1481static void
53303c42 1482qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1483{
7524f9b9 1484 /* Assume a 32bit DMA mask. */
1da177e4 1485 ha->flags.enable_64bit_addressing = 0;
1da177e4 1486
6a35528a 1487 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1488 /* Any upper-dword bits set? */
1489 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1490 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1491 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1492 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1493 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1494 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1495 return;
1da177e4 1496 }
1da177e4 1497 }
7524f9b9 1498
284901a9
YH		 1499 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1500 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1501}
1502
fd34f556 1503static void
e315cd28 1504qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1505{
1506 unsigned long flags = 0;
1507 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1508
1509 spin_lock_irqsave(&ha->hardware_lock, flags);
1510 ha->interrupts_on = 1;
1511 /* enable risc and host interrupts */
1512 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1513 RD_REG_WORD(&reg->ictrl);
1514 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1515
1516}
1517
1518static void
e315cd28 1519qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1520{
1521 unsigned long flags = 0;
1522 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1523
1524 spin_lock_irqsave(&ha->hardware_lock, flags);
1525 ha->interrupts_on = 0;
1526 /* disable risc and host interrupts */
1527 WRT_REG_WORD(&reg->ictrl, 0);
1528 RD_REG_WORD(&reg->ictrl);
1529 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1530}
1531
1532static void
e315cd28 1533qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1534{
1535 unsigned long flags = 0;
1536 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1537
1538 spin_lock_irqsave(&ha->hardware_lock, flags);
1539 ha->interrupts_on = 1;
1540 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1541 RD_REG_DWORD(&reg->ictrl);
1542 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1543}
1544
1545static void
e315cd28 1546qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1547{
1548 unsigned long flags = 0;
1549 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1550
124f85e6
AV		 1551 if (IS_NOPOLLING_TYPE(ha))
1552 return;
fd34f556
AV		 1553 spin_lock_irqsave(&ha->hardware_lock, flags);
1554 ha->interrupts_on = 0;
1555 WRT_REG_DWORD(&reg->ictrl, 0);
1556 RD_REG_DWORD(&reg->ictrl);
1557 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1558}
1559
1560static struct isp_operations qla2100_isp_ops = {
1561 .pci_config = qla2100_pci_config,
1562 .reset_chip = qla2x00_reset_chip,
1563 .chip_diag = qla2x00_chip_diag,
1564 .config_rings = qla2x00_config_rings,
1565 .reset_adapter = qla2x00_reset_adapter,
1566 .nvram_config = qla2x00_nvram_config,
1567 .update_fw_options = qla2x00_update_fw_options,
1568 .load_risc = qla2x00_load_risc,
1569 .pci_info_str = qla2x00_pci_info_str,
1570 .fw_version_str = qla2x00_fw_version_str,
1571 .intr_handler = qla2100_intr_handler,
1572 .enable_intrs = qla2x00_enable_intrs,
1573 .disable_intrs = qla2x00_disable_intrs,
1574 .abort_command = qla2x00_abort_command,
523ec773
AV		 1575 .target_reset = qla2x00_abort_target,
1576 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1577 .fabric_login = qla2x00_login_fabric,
1578 .fabric_logout = qla2x00_fabric_logout,
1579 .calc_req_entries = qla2x00_calc_iocbs_32,
1580 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1581 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1582 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1583 .read_nvram = qla2x00_read_nvram_data,
1584 .write_nvram = qla2x00_write_nvram_data,
1585 .fw_dump = qla2100_fw_dump,
1586 .beacon_on = NULL,
1587 .beacon_off = NULL,
1588 .beacon_blink = NULL,
1589 .read_optrom = qla2x00_read_optrom_data,
1590 .write_optrom = qla2x00_write_optrom_data,
1591 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1592 .start_scsi = qla2x00_start_scsi,
a9083016 1593 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1594};
1595
1596static struct isp_operations qla2300_isp_ops = {
1597 .pci_config = qla2300_pci_config,
1598 .reset_chip = qla2x00_reset_chip,
1599 .chip_diag = qla2x00_chip_diag,
1600 .config_rings = qla2x00_config_rings,
1601 .reset_adapter = qla2x00_reset_adapter,
1602 .nvram_config = qla2x00_nvram_config,
1603 .update_fw_options = qla2x00_update_fw_options,
1604 .load_risc = qla2x00_load_risc,
1605 .pci_info_str = qla2x00_pci_info_str,
1606 .fw_version_str = qla2x00_fw_version_str,
1607 .intr_handler = qla2300_intr_handler,
1608 .enable_intrs = qla2x00_enable_intrs,
1609 .disable_intrs = qla2x00_disable_intrs,
1610 .abort_command = qla2x00_abort_command,
523ec773
AV		 1611 .target_reset = qla2x00_abort_target,
1612 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1613 .fabric_login = qla2x00_login_fabric,
1614 .fabric_logout = qla2x00_fabric_logout,
1615 .calc_req_entries = qla2x00_calc_iocbs_32,
1616 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1617 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1618 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1619 .read_nvram = qla2x00_read_nvram_data,
1620 .write_nvram = qla2x00_write_nvram_data,
1621 .fw_dump = qla2300_fw_dump,
1622 .beacon_on = qla2x00_beacon_on,
1623 .beacon_off = qla2x00_beacon_off,
1624 .beacon_blink = qla2x00_beacon_blink,
1625 .read_optrom = qla2x00_read_optrom_data,
1626 .write_optrom = qla2x00_write_optrom_data,
1627 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1628 .start_scsi = qla2x00_start_scsi,
a9083016 1629 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1630};
1631
1632static struct isp_operations qla24xx_isp_ops = {
1633 .pci_config = qla24xx_pci_config,
1634 .reset_chip = qla24xx_reset_chip,
1635 .chip_diag = qla24xx_chip_diag,
1636 .config_rings = qla24xx_config_rings,
1637 .reset_adapter = qla24xx_reset_adapter,
1638 .nvram_config = qla24xx_nvram_config,
1639 .update_fw_options = qla24xx_update_fw_options,
1640 .load_risc = qla24xx_load_risc,
1641 .pci_info_str = qla24xx_pci_info_str,
1642 .fw_version_str = qla24xx_fw_version_str,
1643 .intr_handler = qla24xx_intr_handler,
1644 .enable_intrs = qla24xx_enable_intrs,
1645 .disable_intrs = qla24xx_disable_intrs,
1646 .abort_command = qla24xx_abort_command,
523ec773
AV		 1647 .target_reset = qla24xx_abort_target,
1648 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1649 .fabric_login = qla24xx_login_fabric,
1650 .fabric_logout = qla24xx_fabric_logout,
1651 .calc_req_entries = NULL,
1652 .build_iocbs = NULL,
1653 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1654 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1655 .read_nvram = qla24xx_read_nvram_data,
1656 .write_nvram = qla24xx_write_nvram_data,
1657 .fw_dump = qla24xx_fw_dump,
1658 .beacon_on = qla24xx_beacon_on,
1659 .beacon_off = qla24xx_beacon_off,
1660 .beacon_blink = qla24xx_beacon_blink,
1661 .read_optrom = qla24xx_read_optrom_data,
1662 .write_optrom = qla24xx_write_optrom_data,
1663 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1664 .start_scsi = qla24xx_start_scsi,
a9083016 1665 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1666};
1667
c3a2f0df
AV		 1668static struct isp_operations qla25xx_isp_ops = {
1669 .pci_config = qla25xx_pci_config,
1670 .reset_chip = qla24xx_reset_chip,
1671 .chip_diag = qla24xx_chip_diag,
1672 .config_rings = qla24xx_config_rings,
1673 .reset_adapter = qla24xx_reset_adapter,
1674 .nvram_config = qla24xx_nvram_config,
1675 .update_fw_options = qla24xx_update_fw_options,
1676 .load_risc = qla24xx_load_risc,
1677 .pci_info_str = qla24xx_pci_info_str,
1678 .fw_version_str = qla24xx_fw_version_str,
1679 .intr_handler = qla24xx_intr_handler,
1680 .enable_intrs = qla24xx_enable_intrs,
1681 .disable_intrs = qla24xx_disable_intrs,
1682 .abort_command = qla24xx_abort_command,
523ec773
AV		 1683 .target_reset = qla24xx_abort_target,
1684 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1685 .fabric_login = qla24xx_login_fabric,
1686 .fabric_logout = qla24xx_fabric_logout,
1687 .calc_req_entries = NULL,
1688 .build_iocbs = NULL,
1689 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1690 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1691 .read_nvram = qla25xx_read_nvram_data,
1692 .write_nvram = qla25xx_write_nvram_data,
1693 .fw_dump = qla25xx_fw_dump,
1694 .beacon_on = qla24xx_beacon_on,
1695 .beacon_off = qla24xx_beacon_off,
1696 .beacon_blink = qla24xx_beacon_blink,
338c9161 1697 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1698 .write_optrom = qla24xx_write_optrom_data,
1699 .get_flash_version = qla24xx_get_flash_version,
bad75002 1700 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1701 .abort_isp = qla2x00_abort_isp,
c3a2f0df
AV		 1702};
1703
3a03eb79
AV		 1704static struct isp_operations qla81xx_isp_ops = {
1705 .pci_config = qla25xx_pci_config,
1706 .reset_chip = qla24xx_reset_chip,
1707 .chip_diag = qla24xx_chip_diag,
1708 .config_rings = qla24xx_config_rings,
1709 .reset_adapter = qla24xx_reset_adapter,
1710 .nvram_config = qla81xx_nvram_config,
1711 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1712 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1713 .pci_info_str = qla24xx_pci_info_str,
1714 .fw_version_str = qla24xx_fw_version_str,
1715 .intr_handler = qla24xx_intr_handler,
1716 .enable_intrs = qla24xx_enable_intrs,
1717 .disable_intrs = qla24xx_disable_intrs,
1718 .abort_command = qla24xx_abort_command,
1719 .target_reset = qla24xx_abort_target,
1720 .lun_reset = qla24xx_lun_reset,
1721 .fabric_login = qla24xx_login_fabric,
1722 .fabric_logout = qla24xx_fabric_logout,
1723 .calc_req_entries = NULL,
1724 .build_iocbs = NULL,
1725 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1726 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1727 .read_nvram = NULL,
1728 .write_nvram = NULL,
3a03eb79
AV		 1729 .fw_dump = qla81xx_fw_dump,
1730 .beacon_on = qla24xx_beacon_on,
1731 .beacon_off = qla24xx_beacon_off,
1732 .beacon_blink = qla24xx_beacon_blink,
1733 .read_optrom = qla25xx_read_optrom_data,
1734 .write_optrom = qla24xx_write_optrom_data,
1735 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1736 .start_scsi = qla24xx_dif_start_scsi,
a9083016
GM		 1737 .abort_isp = qla2x00_abort_isp,
1738};
1739
1740static struct isp_operations qla82xx_isp_ops = {
1741 .pci_config = qla82xx_pci_config,
1742 .reset_chip = qla82xx_reset_chip,
1743 .chip_diag = qla24xx_chip_diag,
1744 .config_rings = qla82xx_config_rings,
1745 .reset_adapter = qla24xx_reset_adapter,
1746 .nvram_config = qla81xx_nvram_config,
1747 .update_fw_options = qla24xx_update_fw_options,
1748 .load_risc = qla82xx_load_risc,
1749 .pci_info_str = qla82xx_pci_info_str,
1750 .fw_version_str = qla24xx_fw_version_str,
1751 .intr_handler = qla82xx_intr_handler,
1752 .enable_intrs = qla82xx_enable_intrs,
1753 .disable_intrs = qla82xx_disable_intrs,
1754 .abort_command = qla24xx_abort_command,
1755 .target_reset = qla24xx_abort_target,
1756 .lun_reset = qla24xx_lun_reset,
1757 .fabric_login = qla24xx_login_fabric,
1758 .fabric_logout = qla24xx_fabric_logout,
1759 .calc_req_entries = NULL,
1760 .build_iocbs = NULL,
1761 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1762 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1763 .read_nvram = qla24xx_read_nvram_data,
1764 .write_nvram = qla24xx_write_nvram_data,
1765 .fw_dump = qla24xx_fw_dump,
999916dc
SK		 1766 .beacon_on = qla82xx_beacon_on,
1767 .beacon_off = qla82xx_beacon_off,
1768 .beacon_blink = NULL,
a9083016
GM		 1769 .read_optrom = qla82xx_read_optrom_data,
1770 .write_optrom = qla82xx_write_optrom_data,
1771 .get_flash_version = qla24xx_get_flash_version,
1772 .start_scsi = qla82xx_start_scsi,
1773 .abort_isp = qla82xx_abort_isp,
3a03eb79
AV		 1774};
1775
ea5b6382 1776static inline void
e315cd28 1777qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 1778{
1779 ha->device_type = DT_EXTENDED_IDS;
1780 switch (ha->pdev->device) {
1781 case PCI_DEVICE_ID_QLOGIC_ISP2100:
1782 ha->device_type |= DT_ISP2100;
1783 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 1784 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 1785 break;
1786 case PCI_DEVICE_ID_QLOGIC_ISP2200:
1787 ha->device_type |= DT_ISP2200;
1788 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 1789 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 1790 break;
1791 case PCI_DEVICE_ID_QLOGIC_ISP2300:
1792 ha->device_type |= DT_ISP2300;
4a59f71d 1793 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 1794 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1795 break;
1796 case PCI_DEVICE_ID_QLOGIC_ISP2312:
1797 ha->device_type |= DT_ISP2312;
4a59f71d 1798 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 1799 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1800 break;
1801 case PCI_DEVICE_ID_QLOGIC_ISP2322:
1802 ha->device_type |= DT_ISP2322;
4a59f71d 1803 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 1804 if (ha->pdev->subsystem_vendor == 0x1028 &&
1805 ha->pdev->subsystem_device == 0x0170)
1806 ha->device_type |= DT_OEM_001;
441d1072 1807 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1808 break;
1809 case PCI_DEVICE_ID_QLOGIC_ISP6312:
1810 ha->device_type |= DT_ISP6312;
441d1072 1811 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1812 break;
1813 case PCI_DEVICE_ID_QLOGIC_ISP6322:
1814 ha->device_type |= DT_ISP6322;
441d1072 1815 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1816 break;
1817 case PCI_DEVICE_ID_QLOGIC_ISP2422:
1818 ha->device_type |= DT_ISP2422;
4a59f71d 1819 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 1820 ha->device_type |= DT_FWI2;
c76f2c01 1821 ha->device_type |= DT_IIDMA;
441d1072 1822 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1823 break;
1824 case PCI_DEVICE_ID_QLOGIC_ISP2432:
1825 ha->device_type |= DT_ISP2432;
4a59f71d 1826 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 1827 ha->device_type |= DT_FWI2;
c76f2c01 1828 ha->device_type |= DT_IIDMA;
441d1072 1829 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1830 break;
4d4df193
HK		 1831 case PCI_DEVICE_ID_QLOGIC_ISP8432:
1832 ha->device_type |= DT_ISP8432;
1833 ha->device_type |= DT_ZIO_SUPPORTED;
1834 ha->device_type |= DT_FWI2;
1835 ha->device_type |= DT_IIDMA;
1836 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1837 break;
044cc6c8 1838 case PCI_DEVICE_ID_QLOGIC_ISP5422:
1839 ha->device_type |= DT_ISP5422;
e428924c 1840 ha->device_type |= DT_FWI2;
441d1072 1841 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1842 break;
044cc6c8 1843 case PCI_DEVICE_ID_QLOGIC_ISP5432:
1844 ha->device_type |= DT_ISP5432;
e428924c 1845 ha->device_type |= DT_FWI2;
441d1072 1846 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1847 break;
c3a2f0df
AV		 1848 case PCI_DEVICE_ID_QLOGIC_ISP2532:
1849 ha->device_type |= DT_ISP2532;
1850 ha->device_type |= DT_ZIO_SUPPORTED;
1851 ha->device_type |= DT_FWI2;
1852 ha->device_type |= DT_IIDMA;
441d1072 1853 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1854 break;
3a03eb79
AV		 1855 case PCI_DEVICE_ID_QLOGIC_ISP8001:
1856 ha->device_type |= DT_ISP8001;
1857 ha->device_type |= DT_ZIO_SUPPORTED;
1858 ha->device_type |= DT_FWI2;
1859 ha->device_type |= DT_IIDMA;
1860 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1861 break;
a9083016
GM		 1862 case PCI_DEVICE_ID_QLOGIC_ISP8021:
1863 ha->device_type |= DT_ISP8021;
1864 ha->device_type |= DT_ZIO_SUPPORTED;
1865 ha->device_type |= DT_FWI2;
1866 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1867 /* Initialize 82XX ISP flags */
1868 qla82xx_init_flags(ha);
1869 break;
ea5b6382 1870 }
e5b68a61 1871
a9083016
GM		 1872 if (IS_QLA82XX(ha))
1873 ha->port_no = !(ha->portnum & 1);
1874 else
1875 /* Get adapter physical port no from interrupt pin register. */
1876 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
1877
e5b68a61
AC		 1878 if (ha->port_no & 1)
1879 ha->flags.port0 = 1;
1880 else
1881 ha->flags.port0 = 0;
7c3df132
SK		 1882 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
1883 "device_type=0x%x port=%d fw_srisc_address=%p.\n",
1884 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
ea5b6382 1885}
1886
1da177e4 1887static int
e315cd28 1888qla2x00_iospace_config(struct qla_hw_data *ha)
1da177e4 1889{
3776541d 1890 resource_size_t pio;
73208dfd 1891 uint16_t msix;
68ca949c 1892 int cpus;
1da177e4 1893
a9083016
GM		 1894 if (IS_QLA82XX(ha))
1895 return qla82xx_iospace_config(ha);
1896
285d0321
AV		 1897 if (pci_request_selected_regions(ha->pdev, ha->bars,
1898 QLA2XXX_DRIVER_NAME)) {
7c3df132
SK		 1899 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1900 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
285d0321 1901 pci_name(ha->pdev));
285d0321
AV		 1902 goto iospace_error_exit;
1903 }
1904 if (!(ha->bars & 1))
1905 goto skip_pio;
1906
1da177e4
LT		 1907 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1908 pio = pci_resource_start(ha->pdev, 0);
3776541d
AV		 1909 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1910 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
7c3df132
SK		 1911 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1912 "Invalid pci I/O region size (%s).\n",
1913 pci_name(ha->pdev));
1da177e4
LT		 1914 pio = 0;
1915 }
1916 } else {
7c3df132
SK		 1917 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1918 "Region #0 no a PIO resource (%s).\n",
1da177e4
LT		 1919 pci_name(ha->pdev));
1920 pio = 0;
1921 }
285d0321 1922 ha->pio_address = pio;
7c3df132
SK		 1923 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1924 "PIO address=%p.\n",
1925 ha->pio_address);
1da177e4 1926
285d0321 1927skip_pio:
1da177e4 1928 /* Use MMIO operations for all accesses. */
3776541d 1929 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
7c3df132
SK		 1930 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1931 "Region #1 not an MMIO resource (%s), aborting.\n",
1da177e4
LT		 1932 pci_name(ha->pdev));
1933 goto iospace_error_exit;
1934 }
3776541d 1935 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
7c3df132
SK		 1936 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1937 "Invalid PCI mem region size (%s), aborting.\n",
1938 pci_name(ha->pdev));
1da177e4
LT		 1939 goto iospace_error_exit;
1940 }
1941
3776541d 1942 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1da177e4 1943 if (!ha->iobase) {
7c3df132
SK		 1944 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1945 "Cannot remap MMIO (%s), aborting.\n",
1946 pci_name(ha->pdev));
1da177e4
LT		 1947 goto iospace_error_exit;
1948 }
1949
73208dfd 1950 /* Determine queue resources */
2afa19a9 1951 ha->max_req_queues = ha->max_rsp_queues = 1;
d84a47c2
MH		 1952 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1953 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
2afa19a9 1954 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
17d98630 1955 goto mqiobase_exit;
d84a47c2 1956
17d98630
AC		 1957 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1958 pci_resource_len(ha->pdev, 3));
1959 if (ha->mqiobase) {
7c3df132
SK		 1960 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1961 "MQIO Base=%p.\n", ha->mqiobase);
17d98630
AC		 1962 /* Read MSIX vector size of the board */
1963 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1964 ha->msix_count = msix;
68ca949c
AC		 1965 /* Max queues are bounded by available msix vectors */
1966 /* queue 0 uses two msix vectors */
1967 if (ql2xmultique_tag) {
1968 cpus = num_online_cpus();
27dc9c5a 1969 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
68ca949c
AC		 1970 (cpus + 1) : (ha->msix_count - 1);
1971 ha->max_req_queues = 2;
1972 } else if (ql2xmaxqueues > 1) {
2afa19a9 1973 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
7c3df132
SK		 1974 QLA_MQ_SIZE : ql2xmaxqueues;
1975 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1976 "QoS mode set, max no of request queues:%d.\n",
1977 ha->max_req_queues);
1978 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1979 "QoS mode set, max no of request queues:%d.\n",
1980 ha->max_req_queues);
2afa19a9 1981 }
7c3df132
SK		 1982 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1983 "MSI-X vector count: %d.\n", msix);
2afa19a9 1984 } else
7c3df132
SK		 1985 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1986 "BAR 3 not enabled.\n");
17d98630
AC		 1987
1988mqiobase_exit:
2afa19a9 1989 ha->msix_count = ha->max_rsp_queues + 1;
7c3df132
SK		 1990 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1991 "MSIX Count:%d.\n", ha->msix_count);
1da177e4
LT		 1992 return (0);
1993
1994iospace_error_exit:
1995 return (-ENOMEM);
1996}
1997
1e99e33a
AV		 1998static void
1999qla2xxx_scan_start(struct Scsi_Host *shost)
2000{
e315cd28 2001 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2002
cbc8eb67
AV		 2003 if (vha->hw->flags.running_gold_fw)
2004 return;
2005
e315cd28
AC		 2006 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2007 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2008 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2009 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2010}
2011
2012static int
2013qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2014{
e315cd28 2015 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2016
e315cd28 2017 if (!vha->host)
1e99e33a 2018 return 1;
e315cd28 2019 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2020 return 1;
2021
e315cd28 2022 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2023}
2024
1da177e4
LT		 2025/*
2026 * PCI driver interface
2027 */
7ee61397
AV		 2028static int __devinit
2029qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2030{
a1541d5a 2031 int ret = -ENODEV;
1da177e4 2032 struct Scsi_Host *host;
e315cd28
AC		 2033 scsi_qla_host_t *base_vha = NULL;
2034 struct qla_hw_data *ha;
29856e28 2035 char pci_info[30];
1da177e4 2036 char fw_str[30];
5433383e 2037 struct scsi_host_template *sht;
c51da4ec 2038 int bars, max_id, mem_only = 0;
e315cd28 2039 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2040 struct req_que *req = NULL;
2041 struct rsp_que *rsp = NULL;
1da177e4 2042
285d0321 2043 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2044 sht = &qla2xxx_driver_template;
5433383e 2045 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2046 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2047 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2048 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2049 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2050 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016
GM		 2051 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2052 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) {
285d0321 2053 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2054 mem_only = 1;
7c3df132
SK		 2055 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2056 "Mem only adapter.\n");
285d0321 2057 }
7c3df132
SK		 2058 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2059 "Bars=%d.\n", bars);
285d0321 2060
09483916
BH		 2061 if (mem_only) {
2062 if (pci_enable_device_mem(pdev))
2063 goto probe_out;
2064 } else {
2065 if (pci_enable_device(pdev))
2066 goto probe_out;
2067 }
285d0321 2068
0927678f
JB		 2069 /* This may fail but that's ok */
2070 pci_enable_pcie_error_reporting(pdev);
285d0321 2071
e315cd28
AC		 2072 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2073 if (!ha) {
7c3df132
SK		 2074 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2075 "Unable to allocate memory for ha.\n");
e315cd28 2076 goto probe_out;
1da177e4 2077 }
7c3df132
SK		 2078 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2079 "Memory allocated for ha=%p.\n", ha);
e315cd28 2080 ha->pdev = pdev;
1da177e4
LT		 2081
2082 /* Clear our data area */
285d0321 2083 ha->bars = bars;
09483916 2084 ha->mem_only = mem_only;
df4bf0bb 2085 spin_lock_init(&ha->hardware_lock);
339aa70e 2086 spin_lock_init(&ha->vport_slock);
1da177e4 2087
ea5b6382 2088 /* Set ISP-type information. */
2089 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2090
2091 /* Set EEH reset type to fundamental if required by hba */
2092 if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) {
2093 pdev->needs_freset = 1;
ca79cf66
DG		 2094 }
2095
1da177e4
LT		 2096 /* Configure PCI I/O space */
2097 ret = qla2x00_iospace_config(ha);
a1541d5a 2098 if (ret)
e315cd28 2099 goto probe_hw_failed;
1da177e4 2100
7c3df132
SK		 2101 ql_log_pci(ql_log_info, pdev, 0x001d,
2102 "Found an ISP%04X irq %d iobase 0x%p.\n",
2103 pdev->device, pdev->irq, ha->iobase);
1da177e4 2104 ha->prev_topology = 0;
fca29703 2105 ha->init_cb_size = sizeof(init_cb_t);
d8b45213 2106 ha->link_data_rate = PORT_SPEED_UNKNOWN;
854165f4 2107 ha->optrom_size = OPTROM_SIZE_2300;
1da177e4 2108
abbd8870 2109 /* Assign ISP specific operations. */
e315cd28 2110 max_id = MAX_TARGETS_2200;
1da177e4 2111 if (IS_QLA2100(ha)) {
e315cd28 2112 max_id = MAX_TARGETS_2100;
1da177e4 2113 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2114 req_length = REQUEST_ENTRY_CNT_2100;
2115 rsp_length = RESPONSE_ENTRY_CNT_2100;
2116 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2117 ha->gid_list_info_size = 4;
3a03eb79
AV		 2118 ha->flash_conf_off = ~0;
2119 ha->flash_data_off = ~0;
2120 ha->nvram_conf_off = ~0;
2121 ha->nvram_data_off = ~0;
fd34f556 2122 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2123 } else if (IS_QLA2200(ha)) {
1da177e4 2124 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2125 req_length = REQUEST_ENTRY_CNT_2200;
2126 rsp_length = RESPONSE_ENTRY_CNT_2100;
2127 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2128 ha->gid_list_info_size = 4;
3a03eb79
AV		 2129 ha->flash_conf_off = ~0;
2130 ha->flash_data_off = ~0;
2131 ha->nvram_conf_off = ~0;
2132 ha->nvram_data_off = ~0;
fd34f556 2133 ha->isp_ops = &qla2100_isp_ops;
fca29703 2134 } else if (IS_QLA23XX(ha)) {
1da177e4 2135 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2136 req_length = REQUEST_ENTRY_CNT_2200;
2137 rsp_length = RESPONSE_ENTRY_CNT_2300;
2138 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2139 ha->gid_list_info_size = 6;
854165f4 2140 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2141 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2142 ha->flash_conf_off = ~0;
2143 ha->flash_data_off = ~0;
2144 ha->nvram_conf_off = ~0;
2145 ha->nvram_data_off = ~0;
fd34f556 2146 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2147 } else if (IS_QLA24XX_TYPE(ha)) {
fca29703 2148 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2149 req_length = REQUEST_ENTRY_CNT_24XX;
2150 rsp_length = RESPONSE_ENTRY_CNT_2300;
2151 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2152 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2153 ha->gid_list_info_size = 8;
854165f4 2154 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2155 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2156 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2157 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2158 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2159 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2160 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2161 } else if (IS_QLA25XX(ha)) {
c3a2f0df 2162 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2163 req_length = REQUEST_ENTRY_CNT_24XX;
2164 rsp_length = RESPONSE_ENTRY_CNT_2300;
2165 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2166 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2167 ha->gid_list_info_size = 8;
2168 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2169 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2170 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2171 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2172 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2173 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2174 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2175 } else if (IS_QLA81XX(ha)) {
2176 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2177 req_length = REQUEST_ENTRY_CNT_24XX;
2178 rsp_length = RESPONSE_ENTRY_CNT_2300;
2179 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2180 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2181 ha->gid_list_info_size = 8;
2182 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2183 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2184 ha->isp_ops = &qla81xx_isp_ops;
2185 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2186 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2187 ha->nvram_conf_off = ~0;
2188 ha->nvram_data_off = ~0;
a9083016
GM		 2189 } else if (IS_QLA82XX(ha)) {
2190 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2191 req_length = REQUEST_ENTRY_CNT_82XX;
2192 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2193 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2194 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2195 ha->gid_list_info_size = 8;
2196 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2197 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2198 ha->isp_ops = &qla82xx_isp_ops;
2199 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2200 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2201 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2202 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
1da177e4 2203 }
7c3df132
SK		 2204 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2205 "mbx_count=%d, req_length=%d, "
2206 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2207 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, .\n",
2208 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2209 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2210 ha->nvram_npiv_size);
2211 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2212 "isp_ops=%p, flash_conf_off=%d, "
2213 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2214 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2215 ha->nvram_conf_off, ha->nvram_data_off);
6c2f527c 2216 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2217 init_completion(&ha->mbx_cmd_comp);
2218 complete(&ha->mbx_cmd_comp);
2219 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2220 init_completion(&ha->dcbx_comp);
1da177e4 2221
2c3dfe3f 2222 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2223
53303c42 2224 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2225 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2226 "64 Bit addressing is %s.\n",
2227 ha->flags.enable_64bit_addressing ? "enable" :
2228 "disable");
73208dfd 2229 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
e315cd28 2230 if (!ret) {
7c3df132
SK		 2231 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2232 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2233
e315cd28
AC		 2234 goto probe_hw_failed;
2235 }
2236
73208dfd 2237 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2238 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2239 req->max_q_depth = ql2xmaxqdepth;
2240
e315cd28
AC		 2241
2242 base_vha = qla2x00_create_host(sht, ha);
2243 if (!base_vha) {
a1541d5a 2244 ret = -ENOMEM;
6e9f21f3 2245 qla2x00_mem_free(ha);
2afa19a9
AC		 2246 qla2x00_free_req_que(ha, req);
2247 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2248 goto probe_hw_failed;
1da177e4
LT		 2249 }
2250
e315cd28
AC		 2251 pci_set_drvdata(pdev, base_vha);
2252
e315cd28 2253 host = base_vha->host;
2afa19a9 2254 base_vha->req = req;
73208dfd
AC		 2255 host->can_queue = req->length + 128;
2256 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2257 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2258 else
e315cd28
AC		 2259 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2260 base_vha->vp_idx;
58548cb5
GM		 2261
2262 /* Set the SG table size based on ISP type */
2263 if (!IS_FWI2_CAPABLE(ha)) {
2264 if (IS_QLA2100(ha))
2265 host->sg_tablesize = 32;
2266 } else {
2267 if (!IS_QLA82XX(ha))
2268 host->sg_tablesize = QLA_SG_ALL;
2269 }
7c3df132
SK		 2270 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2271 "can_queue=%d, req=%p, "
2272 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2273 host->can_queue, base_vha->req,
2274 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
e315cd28
AC		 2275 host->max_id = max_id;
2276 host->this_id = 255;
2277 host->cmd_per_lun = 3;
2278 host->unique_id = host->host_no;
e02587d7 2279 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2280 host->max_cmd_len = 32;
2281 else
2282 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2283 host->max_channel = MAX_BUSES - 1;
82515920 2284 host->max_lun = ql2xmaxlun;
e315cd28 2285 host->transportt = qla2xxx_transport_template;
9a069e19 2286 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2287
7c3df132
SK		 2288 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2289 "max_id=%d this_id=%d "
2290 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2291 "max_lun=%d transportt=%p, vendor_id=%d.\n", host->max_id,
2292 host->this_id, host->cmd_per_lun, host->unique_id,
2293 host->max_cmd_len, host->max_channel, host->max_lun,
2294 host->transportt, sht->vendor_id);
2295
73208dfd
AC		 2296 /* Set up the irqs */
2297 ret = qla2x00_request_irqs(ha, rsp);
2298 if (ret)
6e9f21f3 2299 goto probe_init_failed;
90a86fc0
JC		 2300
2301 pci_save_state(pdev);
2302
73208dfd 2303 /* Alloc arrays of request and response ring ptrs */
7163ea81 2304que_init:
73208dfd 2305 if (!qla2x00_alloc_queues(ha)) {
7c3df132
SK		 2306 ql_log(ql_log_fatal, base_vha, 0x003d,
2307 "Failed to allocate memory for queue pointers.. aborting.\n");
6e9f21f3 2308 goto probe_init_failed;
73208dfd 2309 }
a9083016 2310
73208dfd
AC		 2311 ha->rsp_q_map[0] = rsp;
2312 ha->req_q_map[0] = req;
2afa19a9
AC		 2313 rsp->req = req;
2314 req->rsp = rsp;
2315 set_bit(0, ha->req_qid_map);
2316 set_bit(0, ha->rsp_qid_map);
08029990
AV		 2317 /* FWI2-capable only. */
2318 req->req_q_in = &ha->iobase->isp24.req_q_in;
2319 req->req_q_out = &ha->iobase->isp24.req_q_out;
2320 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2321 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
17d98630 2322 if (ha->mqenable) {
08029990
AV		 2323 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2324 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2325 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2326 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2327 }
2328
a9083016
GM		 2329 if (IS_QLA82XX(ha)) {
2330 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2331 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2332 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2333 }
2334
7c3df132
SK		 2335 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2336 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2337 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2338 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2339 "req->req_q_in=%p req->req_q_out=%p "
2340 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2341 req->req_q_in, req->req_q_out,
2342 rsp->rsp_q_in, rsp->rsp_q_out);
2343 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2344 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2345 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2346 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2347 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2348 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2349
7c3df132
SK		 2350 if (qla2x00_initialize_adapter(base_vha)) {
2351 ql_log(ql_log_fatal, base_vha, 0x00d6,
2352 "Failed to initialize adapter - Adapter flags %x.\n",
2353 base_vha->device_flags);
1da177e4 2354
a9083016
GM		 2355 if (IS_QLA82XX(ha)) {
2356 qla82xx_idc_lock(ha);
2357 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2358 QLA82XX_DEV_FAILED);
2359 qla82xx_idc_unlock(ha);
7c3df132
SK		 2360 ql_log(ql_log_fatal, base_vha, 0x00d7,
2361 "HW State: FAILED.\n");
a9083016
GM		 2362 }
2363
a1541d5a 2364 ret = -ENODEV;
1da177e4
LT		 2365 goto probe_failed;
2366 }
2367
7163ea81
AC		 2368 if (ha->mqenable) {
2369 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2370 ql_log(ql_log_warn, base_vha, 0x00ec,
2371 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2372 goto que_init;
2373 }
2374 }
68ca949c 2375
cbc8eb67
AV		 2376 if (ha->flags.running_gold_fw)
2377 goto skip_dpc;
2378
1da177e4
LT		 2379 /*
2380 * Startup the kernel thread for this host adapter
2381 */
39a11240 2382 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2383 "%s_dpc", base_vha->host_str);
39a11240 2384 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2385 ql_log(ql_log_fatal, base_vha, 0x00ed,
2386 "Failed to start DPC thread.\n");
39a11240 2387 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2388 goto probe_failed;
2389 }
7c3df132
SK		 2390 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2391 "DPC thread started successfully.\n");
1da177e4 2392
cbc8eb67 2393skip_dpc:
e315cd28
AC		 2394 list_add_tail(&base_vha->list, &ha->vp_list);
2395 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2396
2397 /* Initialized the timer */
e315cd28 2398 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2399 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2400 "Started qla2x00_timer with "
2401 "interval=%d.\n", WATCH_INTERVAL);
2402 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2403 "Detected hba at address=%p.\n",
2404 ha);
d19044c3 2405
e02587d7 2406 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2407 if (ha->fw_attributes & BIT_4) {
8cb2049c 2408 int prot = 0;
bad75002 2409 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2410 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2411 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2412 if (ql2xenabledif == 1)
2413 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2414 scsi_host_set_prot(host,
8cb2049c 2415 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2416 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2417 | SHOST_DIF_TYPE3_PROTECTION
2418 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2419 | SHOST_DIX_TYPE2_PROTECTION
bad75002
AE		 2420 | SHOST_DIX_TYPE3_PROTECTION);
2421 scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
2422 } else
2423 base_vha->flags.difdix_supported = 0;
2424 }
2425
a9083016
GM		 2426 ha->isp_ops->enable_intrs(ha);
2427
a1541d5a
AV		 2428 ret = scsi_add_host(host, &pdev->dev);
2429 if (ret)
2430 goto probe_failed;
2431
1486400f
MR		 2432 base_vha->flags.init_done = 1;
2433 base_vha->flags.online = 1;
2434
7c3df132
SK		 2435 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2436 "Init done and hba is online.\n");
2437
1e99e33a
AV		 2438 scsi_scan_host(host);
2439
e315cd28 2440 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2441
e315cd28 2442 qla2x00_init_host_attr(base_vha);
a1541d5a 2443
e315cd28 2444 qla2x00_dfs_setup(base_vha);
df613b96 2445
7c3df132
SK		 2446 ql_log(ql_log_info, base_vha, 0x00fa,
2447 "QLogic Fibre Channed HBA Driver: %s.\n",
2448 qla2x00_version_str);
2449 ql_log(ql_log_info, base_vha, 0x00fb,
2450 "QLogic %s - %s.\n",
2451 ha->model_number, ha->model_desc ? ha->model_desc : "");
2452 ql_log(ql_log_info, base_vha, 0x00fc,
2453 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2454 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2455 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2456 base_vha->host_no,
e315cd28 2457 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2458
1da177e4
LT		 2459 return 0;
2460
6e9f21f3 2461probe_init_failed:
2afa19a9
AC		 2462 qla2x00_free_req_que(ha, req);
2463 qla2x00_free_rsp_que(ha, rsp);
2464 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2465
1da177e4 2466probe_failed:
b9978769
AV		 2467 if (base_vha->timer_active)
2468 qla2x00_stop_timer(base_vha);
2469 base_vha->flags.online = 0;
2470 if (ha->dpc_thread) {
2471 struct task_struct *t = ha->dpc_thread;
2472
2473 ha->dpc_thread = NULL;
2474 kthread_stop(t);
2475 }
2476
e315cd28 2477 qla2x00_free_device(base_vha);
1da177e4 2478
e315cd28 2479 scsi_host_put(base_vha->host);
1da177e4 2480
e315cd28 2481probe_hw_failed:
a9083016
GM		 2482 if (IS_QLA82XX(ha)) {
2483 qla82xx_idc_lock(ha);
2484 qla82xx_clear_drv_active(ha);
2485 qla82xx_idc_unlock(ha);
2486 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2487 if (!ql2xdbwr)
2488 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2489 } else {
2490 if (ha->iobase)
2491 iounmap(ha->iobase);
2492 }
e315cd28
AC		 2493 pci_release_selected_regions(ha->pdev, ha->bars);
2494 kfree(ha);
2495 ha = NULL;
1da177e4 2496
a1541d5a 2497probe_out:
e315cd28 2498 pci_disable_device(pdev);
a1541d5a 2499 return ret;
1da177e4 2500}
1da177e4 2501
e30d1756
MI		 2502static void
2503qla2x00_shutdown(struct pci_dev *pdev)
2504{
2505 scsi_qla_host_t *vha;
2506 struct qla_hw_data *ha;
2507
2508 vha = pci_get_drvdata(pdev);
2509 ha = vha->hw;
2510
2511 /* Turn-off FCE trace */
2512 if (ha->flags.fce_enabled) {
2513 qla2x00_disable_fce_trace(vha, NULL, NULL);
2514 ha->flags.fce_enabled = 0;
2515 }
2516
2517 /* Turn-off EFT trace */
2518 if (ha->eft)
2519 qla2x00_disable_eft_trace(vha);
2520
2521 /* Stop currently executing firmware. */
2522 qla2x00_try_to_stop_firmware(vha);
2523
2524 /* Turn adapter off line */
2525 vha->flags.online = 0;
2526
2527 /* turn-off interrupts on the card */
2528 if (ha->interrupts_on) {
2529 vha->flags.init_done = 0;
2530 ha->isp_ops->disable_intrs(ha);
2531 }
2532
2533 qla2x00_free_irqs(vha);
2534
2535 qla2x00_free_fw_dump(ha);
2536}
2537
4c993f76 2538static void
7ee61397 2539qla2x00_remove_one(struct pci_dev *pdev)
1da177e4 2540{
feafb7b1 2541 scsi_qla_host_t *base_vha, *vha;
e315cd28 2542 struct qla_hw_data *ha;
feafb7b1 2543 unsigned long flags;
e315cd28
AC		 2544
2545 base_vha = pci_get_drvdata(pdev);
2546 ha = base_vha->hw;
2547
43ebf16d
AE		 2548 mutex_lock(&ha->vport_lock);
2549 while (ha->cur_vport_count) {
2550 struct Scsi_Host *scsi_host;
feafb7b1 2551
43ebf16d 2552 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2553
43ebf16d
AE		 2554 BUG_ON(base_vha->list.next == &ha->vp_list);
2555 /* This assumes first entry in ha->vp_list is always base vha */
2556 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2557 scsi_host = scsi_host_get(vha->host);
feafb7b1 2558
43ebf16d
AE		 2559 spin_unlock_irqrestore(&ha->vport_slock, flags);
2560 mutex_unlock(&ha->vport_lock);
2561
2562 fc_vport_terminate(vha->fc_vport);
2563 scsi_host_put(vha->host);
feafb7b1 2564
43ebf16d 2565 mutex_lock(&ha->vport_lock);
e315cd28 2566 }
43ebf16d 2567 mutex_unlock(&ha->vport_lock);
1da177e4 2568
e315cd28 2569 set_bit(UNLOADING, &base_vha->dpc_flags);
1da177e4 2570
b9978769
AV		 2571 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
2572
e315cd28 2573 qla2x00_dfs_remove(base_vha);
c795c1e4 2574
e315cd28 2575 qla84xx_put_chip(base_vha);
c795c1e4 2576
b9978769
AV		 2577 /* Disable timer */
2578 if (base_vha->timer_active)
2579 qla2x00_stop_timer(base_vha);
2580
2581 base_vha->flags.online = 0;
2582
68ca949c
AC		 2583 /* Flush the work queue and remove it */
2584 if (ha->wq) {
2585 flush_workqueue(ha->wq);
2586 destroy_workqueue(ha->wq);
2587 ha->wq = NULL;
2588 }
2589
b9978769
AV		 2590 /* Kill the kernel thread for this host */
2591 if (ha->dpc_thread) {
2592 struct task_struct *t = ha->dpc_thread;
2593
2594 /*
2595 * qla2xxx_wake_dpc checks for ->dpc_thread
2596 * so we need to zero it out.
2597 */
2598 ha->dpc_thread = NULL;
2599 kthread_stop(t);
2600 }
2601
e315cd28 2602 qla2x00_free_sysfs_attr(base_vha);
df613b96 2603
e315cd28 2604 fc_remove_host(base_vha->host);
4d4df193 2605
e315cd28 2606 scsi_remove_host(base_vha->host);
1da177e4 2607
e315cd28 2608 qla2x00_free_device(base_vha);
bdf79621 2609
e315cd28 2610 scsi_host_put(base_vha->host);
1da177e4 2611
a9083016 2612 if (IS_QLA82XX(ha)) {
b963752f
GM		 2613 qla82xx_idc_lock(ha);
2614 qla82xx_clear_drv_active(ha);
2615 qla82xx_idc_unlock(ha);
2616
a9083016
GM		 2617 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2618 if (!ql2xdbwr)
2619 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2620 } else {
2621 if (ha->iobase)
2622 iounmap(ha->iobase);
1da177e4 2623
a9083016
GM		 2624 if (ha->mqiobase)
2625 iounmap(ha->mqiobase);
2626 }
73208dfd 2627
e315cd28
AC		 2628 pci_release_selected_regions(ha->pdev, ha->bars);
2629 kfree(ha);
2630 ha = NULL;
1da177e4 2631
90a86fc0
JC		 2632 pci_disable_pcie_error_reporting(pdev);
2633
665db93b 2634 pci_disable_device(pdev);
1da177e4
LT		 2635 pci_set_drvdata(pdev, NULL);
2636}
1da177e4
LT		 2637
2638static void
e315cd28 2639qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 2640{
e315cd28 2641 struct qla_hw_data *ha = vha->hw;
1da177e4 2642
85880801
AV		 2643 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
2644
2645 /* Disable timer */
2646 if (vha->timer_active)
2647 qla2x00_stop_timer(vha);
2648
2649 /* Kill the kernel thread for this host */
2650 if (ha->dpc_thread) {
2651 struct task_struct *t = ha->dpc_thread;
2652
2653 /*
2654 * qla2xxx_wake_dpc checks for ->dpc_thread
2655 * so we need to zero it out.
2656 */
2657 ha->dpc_thread = NULL;
2658 kthread_stop(t);
2659 }
2660
2afa19a9
AC		 2661 qla25xx_delete_queues(vha);
2662
df613b96 2663 if (ha->flags.fce_enabled)
e315cd28 2664 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 2665
a7a167bf 2666 if (ha->eft)
e315cd28 2667 qla2x00_disable_eft_trace(vha);
a7a167bf 2668
f6ef3b18 2669 /* Stop currently executing firmware. */
e315cd28 2670 qla2x00_try_to_stop_firmware(vha);
1da177e4 2671
85880801
AV		 2672 vha->flags.online = 0;
2673
f6ef3b18 2674 /* turn-off interrupts on the card */
a9083016
GM		 2675 if (ha->interrupts_on) {
2676 vha->flags.init_done = 0;
fd34f556 2677 ha->isp_ops->disable_intrs(ha);
a9083016 2678 }
f6ef3b18 2679
e315cd28 2680 qla2x00_free_irqs(vha);
1da177e4 2681
8867048b
CD		 2682 qla2x00_free_fcports(vha);
2683
e315cd28 2684 qla2x00_mem_free(ha);
73208dfd 2685
08de2844
GM		 2686 qla82xx_md_free(vha);
2687
73208dfd 2688 qla2x00_free_queues(ha);
1da177e4
LT		 2689}
2690
8867048b
CD		 2691void qla2x00_free_fcports(struct scsi_qla_host *vha)
2692{
2693 fc_port_t *fcport, *tfcport;
2694
2695 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
2696 list_del(&fcport->list);
2697 kfree(fcport);
2698 fcport = NULL;
2699 }
2700}
2701
d97994dc 2702static inline void
e315cd28 2703qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 2704 int defer)
2705{
d97994dc 2706 struct fc_rport *rport;
67becc00 2707 scsi_qla_host_t *base_vha;
044d78e1 2708 unsigned long flags;
d97994dc 2709
2710 if (!fcport->rport)
2711 return;
2712
2713 rport = fcport->rport;
2714 if (defer) {
67becc00 2715 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 2716 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 2717 fcport->drport = rport;
044d78e1 2718 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 2719 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
2720 qla2xxx_wake_dpc(base_vha);
5f3a9a20 2721 } else
d97994dc 2722 fc_remote_port_delete(rport);
d97994dc 2723}
2724
1da177e4
LT		 2725/*
2726 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
2727 *
2728 * Input: ha = adapter block pointer. fcport = port structure pointer.
2729 *
2730 * Return: None.
2731 *
2732 * Context:
2733 */
e315cd28 2734void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 2735 int do_login, int defer)
1da177e4 2736{
2c3dfe3f 2737 if (atomic_read(&fcport->state) == FCS_ONLINE &&
e315cd28 2738 vha->vp_idx == fcport->vp_idx) {
ec426e10 2739 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 2740 qla2x00_schedule_rport_del(vha, fcport, defer);
2741 }
fa2a1ce5 2742 /*
1da177e4
LT		 2743 * We may need to retry the login, so don't change the state of the
2744 * port but do the retries.
2745 */
2746 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 2747 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2748
2749 if (!do_login)
2750 return;
2751
2752 if (fcport->login_retry == 0) {
e315cd28
AC		 2753 fcport->login_retry = vha->hw->login_retry_count;
2754 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 2755
7c3df132
SK		 2756 ql_dbg(ql_dbg_disc, vha, 0x2067,
2757 "Port login retry "
1da177e4 2758 "%02x%02x%02x%02x%02x%02x%02x%02x, "
7c3df132
SK		 2759 "id = 0x%04x retry cnt=%d.\n",
2760 fcport->port_name[0], fcport->port_name[1],
2761 fcport->port_name[2], fcport->port_name[3],
2762 fcport->port_name[4], fcport->port_name[5],
2763 fcport->port_name[6], fcport->port_name[7],
2764 fcport->loop_id, fcport->login_retry);
1da177e4
LT		 2765 }
2766}
2767
2768/*
2769 * qla2x00_mark_all_devices_lost
2770 * Updates fcport state when device goes offline.
2771 *
2772 * Input:
2773 * ha = adapter block pointer.
2774 * fcport = port structure pointer.
2775 *
2776 * Return:
2777 * None.
2778 *
2779 * Context:
2780 */
2781void
e315cd28 2782qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 2783{
2784 fc_port_t *fcport;
2785
e315cd28 2786 list_for_each_entry(fcport, &vha->vp_fcports, list) {
0d6e61bc 2787 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
1da177e4 2788 continue;
0d6e61bc 2789
1da177e4
LT		 2790 /*
2791 * No point in marking the device as lost, if the device is
2792 * already DEAD.
2793 */
2794 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
2795 continue;
e315cd28 2796 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 2797 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 2798 if (defer)
2799 qla2x00_schedule_rport_del(vha, fcport, defer);
2800 else if (vha->vp_idx == fcport->vp_idx)
2801 qla2x00_schedule_rport_del(vha, fcport, defer);
2802 }
1da177e4
LT		 2803 }
2804}
2805
2806/*
2807* qla2x00_mem_alloc
2808* Allocates adapter memory.
2809*
2810* Returns:
2811* 0 = success.
e8711085 2812* !0 = failure.
1da177e4 2813*/
e8711085 2814static int
73208dfd
AC		 2815qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
2816 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 2817{
2818 char name[16];
1da177e4 2819
e8711085 2820 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 2821 &ha->init_cb_dma, GFP_KERNEL);
e8711085 2822 if (!ha->init_cb)
e315cd28 2823 goto fail;
e8711085 2824
e315cd28
AC		 2825 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE,
2826 &ha->gid_list_dma, GFP_KERNEL);
2827 if (!ha->gid_list)
e8711085 2828 goto fail_free_init_cb;
1da177e4 2829
e8711085
AV		 2830 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
2831 if (!ha->srb_mempool)
e315cd28 2832 goto fail_free_gid_list;
e8711085 2833
a9083016
GM		 2834 if (IS_QLA82XX(ha)) {
2835 /* Allocate cache for CT6 Ctx. */
2836 if (!ctx_cachep) {
2837 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
2838 sizeof(struct ct6_dsd), 0,
2839 SLAB_HWCACHE_ALIGN, NULL);
2840 if (!ctx_cachep)
2841 goto fail_free_gid_list;
2842 }
2843 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
2844 ctx_cachep);
2845 if (!ha->ctx_mempool)
2846 goto fail_free_srb_mempool;
7c3df132
SK		 2847 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
2848 "ctx_cachep=%p ctx_mempool=%p.\n",
2849 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 2850 }
2851
e8711085
AV		 2852 /* Get memory for cached NVRAM */
2853 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
2854 if (!ha->nvram)
a9083016 2855 goto fail_free_ctx_mempool;
e8711085 2856
e315cd28
AC		 2857 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
2858 ha->pdev->device);
2859 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2860 DMA_POOL_SIZE, 8, 0);
2861 if (!ha->s_dma_pool)
2862 goto fail_free_nvram;
2863
7c3df132
SK		 2864 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
2865 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
2866 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
2867
bad75002 2868 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 2869 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2870 DSD_LIST_DMA_POOL_SIZE, 8, 0);
2871 if (!ha->dl_dma_pool) {
7c3df132
SK		 2872 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
2873 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 2874 goto fail_s_dma_pool;
2875 }
2876
2877 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2878 FCP_CMND_DMA_POOL_SIZE, 8, 0);
2879 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 2880 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
2881 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 2882 goto fail_dl_dma_pool;
2883 }
7c3df132
SK		 2884 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
2885 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
2886 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 2887 }
2888
e8711085
AV		 2889 /* Allocate memory for SNS commands */
2890 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 2891 /* Get consistent memory allocated for SNS commands */
e8711085 2892 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 2893 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 2894 if (!ha->sns_cmd)
e315cd28 2895 goto fail_dma_pool;
7c3df132
SK		 2896 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
2897 "sns_cmd.\n", ha->sns_cmd);
e8711085 2898 } else {
e315cd28 2899 /* Get consistent memory allocated for MS IOCB */
e8711085 2900 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 2901 &ha->ms_iocb_dma);
e8711085 2902 if (!ha->ms_iocb)
e315cd28
AC		 2903 goto fail_dma_pool;
2904 /* Get consistent memory allocated for CT SNS commands */
e8711085 2905 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 2906 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 2907 if (!ha->ct_sns)
2908 goto fail_free_ms_iocb;
7c3df132
SK		 2909 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
2910 "ms_iocb=%p ct_sns=%p.\n",
2911 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 2912 }
2913
e315cd28 2914 /* Allocate memory for request ring */
73208dfd
AC		 2915 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
2916 if (!*req) {
7c3df132
SK		 2917 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
2918 "Failed to allocate memory for req.\n");
e315cd28
AC		 2919 goto fail_req;
2920 }
73208dfd
AC		 2921 (*req)->length = req_len;
2922 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
2923 ((*req)->length + 1) * sizeof(request_t),
2924 &(*req)->dma, GFP_KERNEL);
2925 if (!(*req)->ring) {
7c3df132
SK		 2926 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
2927 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 2928 goto fail_req_ring;
2929 }
2930 /* Allocate memory for response ring */
73208dfd
AC		 2931 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
2932 if (!*rsp) {
7c3df132
SK		 2933 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
2934 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 2935 goto fail_rsp;
2936 }
73208dfd
AC		 2937 (*rsp)->hw = ha;
2938 (*rsp)->length = rsp_len;
2939 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
2940 ((*rsp)->length + 1) * sizeof(response_t),
2941 &(*rsp)->dma, GFP_KERNEL);
2942 if (!(*rsp)->ring) {
7c3df132
SK		 2943 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
2944 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 2945 goto fail_rsp_ring;
2946 }
73208dfd
AC		 2947 (*req)->rsp = *rsp;
2948 (*rsp)->req = *req;
7c3df132
SK		 2949 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
2950 "req=%p req->length=%d req->ring=%p rsp=%p "
2951 "rsp->length=%d rsp->ring=%p.\n",
2952 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
2953 (*rsp)->ring);
73208dfd
AC		 2954 /* Allocate memory for NVRAM data for vports */
2955 if (ha->nvram_npiv_size) {
2956 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 2957 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 2958 if (!ha->npiv_info) {
7c3df132
SK		 2959 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
2960 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 2961 goto fail_npiv_info;
2962 }
2963 } else
2964 ha->npiv_info = NULL;
e8711085 2965
b64b0e8f 2966 /* Get consistent memory allocated for EX-INIT-CB. */
a9083016 2967 if (IS_QLA8XXX_TYPE(ha)) {
b64b0e8f
AV		 2968 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2969 &ha->ex_init_cb_dma);
2970 if (!ha->ex_init_cb)
2971 goto fail_ex_init_cb;
7c3df132
SK		 2972 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
2973 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 2974 }
2975
a9083016
GM		 2976 INIT_LIST_HEAD(&ha->gbl_dsd_list);
2977
5ff1d584
AV		 2978 /* Get consistent memory allocated for Async Port-Database. */
2979 if (!IS_FWI2_CAPABLE(ha)) {
2980 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2981 &ha->async_pd_dma);
2982 if (!ha->async_pd)
2983 goto fail_async_pd;
7c3df132
SK		 2984 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
2985 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 2986 }
2987
e315cd28
AC		 2988 INIT_LIST_HEAD(&ha->vp_list);
2989 return 1;
2990
5ff1d584
AV		 2991fail_async_pd:
2992 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 2993fail_ex_init_cb:
2994 kfree(ha->npiv_info);
73208dfd
AC		 2995fail_npiv_info:
2996 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
2997 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
2998 (*rsp)->ring = NULL;
2999 (*rsp)->dma = 0;
e315cd28 3000fail_rsp_ring:
73208dfd 3001 kfree(*rsp);
e315cd28 3002fail_rsp:
73208dfd
AC		 3003 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3004 sizeof(request_t), (*req)->ring, (*req)->dma);
3005 (*req)->ring = NULL;
3006 (*req)->dma = 0;
e315cd28 3007fail_req_ring:
73208dfd 3008 kfree(*req);
e315cd28
AC		 3009fail_req:
3010 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3011 ha->ct_sns, ha->ct_sns_dma);
3012 ha->ct_sns = NULL;
3013 ha->ct_sns_dma = 0;
e8711085
AV		 3014fail_free_ms_iocb:
3015 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3016 ha->ms_iocb = NULL;
3017 ha->ms_iocb_dma = 0;
e315cd28 3018fail_dma_pool:
bad75002 3019 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3020 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3021 ha->fcp_cmnd_dma_pool = NULL;
3022 }
3023fail_dl_dma_pool:
bad75002 3024 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3025 dma_pool_destroy(ha->dl_dma_pool);
3026 ha->dl_dma_pool = NULL;
3027 }
3028fail_s_dma_pool:
e315cd28
AC		 3029 dma_pool_destroy(ha->s_dma_pool);
3030 ha->s_dma_pool = NULL;
e8711085
AV		 3031fail_free_nvram:
3032 kfree(ha->nvram);
3033 ha->nvram = NULL;
a9083016
GM		 3034fail_free_ctx_mempool:
3035 mempool_destroy(ha->ctx_mempool);
3036 ha->ctx_mempool = NULL;
e8711085
AV		 3037fail_free_srb_mempool:
3038 mempool_destroy(ha->srb_mempool);
3039 ha->srb_mempool = NULL;
e8711085
AV		 3040fail_free_gid_list:
3041 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
e315cd28 3042 ha->gid_list_dma);
e8711085
AV		 3043 ha->gid_list = NULL;
3044 ha->gid_list_dma = 0;
e315cd28
AC		 3045fail_free_init_cb:
3046 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3047 ha->init_cb_dma);
3048 ha->init_cb = NULL;
3049 ha->init_cb_dma = 0;
e8711085 3050fail:
7c3df132
SK		 3051 ql_log(ql_log_fatal, NULL, 0x0030,
3052 "Memory allocation failure.\n");
e8711085 3053 return -ENOMEM;
1da177e4
LT		 3054}
3055
3056/*
e30d1756
MI		 3057* qla2x00_free_fw_dump
3058* Frees fw dump stuff.
1da177e4
LT		 3059*
3060* Input:
e30d1756 3061* ha = adapter block pointer.
1da177e4 3062*/
a824ebb3 3063static void
e30d1756 3064qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3065{
df613b96
AV		 3066 if (ha->fce)
3067 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
e30d1756 3068 ha->fce_dma);
df613b96 3069
a7a167bf
AV		 3070 if (ha->fw_dump) {
3071 if (ha->eft)
3072 dma_free_coherent(&ha->pdev->dev,
e30d1756 3073 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
a7a167bf
AV		 3074 vfree(ha->fw_dump);
3075 }
e30d1756
MI		 3076 ha->fce = NULL;
3077 ha->fce_dma = 0;
3078 ha->eft = NULL;
3079 ha->eft_dma = 0;
3080 ha->fw_dump = NULL;
3081 ha->fw_dumped = 0;
3082 ha->fw_dump_reading = 0;
3083}
3084
3085/*
3086* qla2x00_mem_free
3087* Frees all adapter allocated memory.
3088*
3089* Input:
3090* ha = adapter block pointer.
3091*/
3092static void
3093qla2x00_mem_free(struct qla_hw_data *ha)
3094{
3095 qla2x00_free_fw_dump(ha);
3096
3097 if (ha->srb_mempool)
3098 mempool_destroy(ha->srb_mempool);
a7a167bf 3099
11bbc1d8
AV		 3100 if (ha->dcbx_tlv)
3101 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3102 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3103
ce0423f4
AV		 3104 if (ha->xgmac_data)
3105 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3106 ha->xgmac_data, ha->xgmac_data_dma);
3107
1da177e4
LT		 3108 if (ha->sns_cmd)
3109 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3110 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3111
3112 if (ha->ct_sns)
3113 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3114 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3115
88729e53
AV		 3116 if (ha->sfp_data)
3117 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3118
ad0ecd61
JC		 3119 if (ha->edc_data)
3120 dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma);
3121
1da177e4
LT		 3122 if (ha->ms_iocb)
3123 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3124
b64b0e8f 3125 if (ha->ex_init_cb)
a9083016
GM		 3126 dma_pool_free(ha->s_dma_pool,
3127 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3128
5ff1d584
AV		 3129 if (ha->async_pd)
3130 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3131
1da177e4
LT		 3132 if (ha->s_dma_pool)
3133 dma_pool_destroy(ha->s_dma_pool);
3134
1da177e4
LT		 3135 if (ha->gid_list)
3136 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
e315cd28 3137 ha->gid_list_dma);
1da177e4 3138
a9083016
GM		 3139 if (IS_QLA82XX(ha)) {
3140 if (!list_empty(&ha->gbl_dsd_list)) {
3141 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3142
3143 /* clean up allocated prev pool */
3144 list_for_each_entry_safe(dsd_ptr,
3145 tdsd_ptr, &ha->gbl_dsd_list, list) {
3146 dma_pool_free(ha->dl_dma_pool,
3147 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3148 list_del(&dsd_ptr->list);
3149 kfree(dsd_ptr);
3150 }
3151 }
3152 }
3153
3154 if (ha->dl_dma_pool)
3155 dma_pool_destroy(ha->dl_dma_pool);
3156
3157 if (ha->fcp_cmnd_dma_pool)
3158 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3159
3160 if (ha->ctx_mempool)
3161 mempool_destroy(ha->ctx_mempool);
3162
e315cd28
AC		 3163 if (ha->init_cb)
3164 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3165 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3166 vfree(ha->optrom_buffer);
3167 kfree(ha->nvram);
73208dfd 3168 kfree(ha->npiv_info);
1da177e4 3169
e8711085 3170 ha->srb_mempool = NULL;
a9083016 3171 ha->ctx_mempool = NULL;
1da177e4
LT		 3172 ha->sns_cmd = NULL;
3173 ha->sns_cmd_dma = 0;
3174 ha->ct_sns = NULL;
3175 ha->ct_sns_dma = 0;
3176 ha->ms_iocb = NULL;
3177 ha->ms_iocb_dma = 0;
1da177e4
LT		 3178 ha->init_cb = NULL;
3179 ha->init_cb_dma = 0;
b64b0e8f
AV		 3180 ha->ex_init_cb = NULL;
3181 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3182 ha->async_pd = NULL;
3183 ha->async_pd_dma = 0;
1da177e4
LT		 3184
3185 ha->s_dma_pool = NULL;
a9083016
GM		 3186 ha->dl_dma_pool = NULL;
3187 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3188
1da177e4
LT		 3189 ha->gid_list = NULL;
3190 ha->gid_list_dma = 0;
e315cd28 3191}
1da177e4 3192
e315cd28
AC		 3193struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3194 struct qla_hw_data *ha)
3195{
3196 struct Scsi_Host *host;
3197 struct scsi_qla_host *vha = NULL;
854165f4 3198
e315cd28
AC		 3199 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3200 if (host == NULL) {
7c3df132
SK		 3201 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3202 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3203 goto fail;
3204 }
3205
3206 /* Clear our data area */
3207 vha = shost_priv(host);
3208 memset(vha, 0, sizeof(scsi_qla_host_t));
3209
3210 vha->host = host;
3211 vha->host_no = host->host_no;
3212 vha->hw = ha;
3213
3214 INIT_LIST_HEAD(&vha->vp_fcports);
3215 INIT_LIST_HEAD(&vha->work_list);
3216 INIT_LIST_HEAD(&vha->list);
3217
f999f4c1
AV		 3218 spin_lock_init(&vha->work_lock);
3219
e315cd28 3220 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3221 ql_dbg(ql_dbg_init, vha, 0x0041,
3222 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3223 vha->host, vha->hw, vha,
3224 dev_name(&(ha->pdev->dev)));
3225
e315cd28
AC		 3226 return vha;
3227
3228fail:
3229 return vha;
1da177e4
LT		 3230}
3231
01ef66bb 3232static struct qla_work_evt *
f999f4c1 3233qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3234{
3235 struct qla_work_evt *e;
feafb7b1
AE		 3236 uint8_t bail;
3237
3238 QLA_VHA_MARK_BUSY(vha, bail);
3239 if (bail)
3240 return NULL;
0971de7f 3241
f999f4c1 3242 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3243 if (!e) {
3244 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3245 return NULL;
feafb7b1 3246 }
0971de7f
AV		 3247
3248 INIT_LIST_HEAD(&e->list);
3249 e->type = type;
3250 e->flags = QLA_EVT_FLAG_FREE;
3251 return e;
3252}
3253
01ef66bb 3254static int
f999f4c1 3255qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3256{
f999f4c1 3257 unsigned long flags;
0971de7f 3258
f999f4c1 3259 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3260 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3261 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3262 qla2xxx_wake_dpc(vha);
f999f4c1 3263
0971de7f
AV		 3264 return QLA_SUCCESS;
3265}
3266
3267int
e315cd28 3268qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3269 u32 data)
3270{
3271 struct qla_work_evt *e;
3272
f999f4c1 3273 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3274 if (!e)
3275 return QLA_FUNCTION_FAILED;
3276
3277 e->u.aen.code = code;
3278 e->u.aen.data = data;
f999f4c1 3279 return qla2x00_post_work(vha, e);
0971de7f
AV		 3280}
3281
8a659571
AV		 3282int
3283qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3284{
3285 struct qla_work_evt *e;
3286
f999f4c1 3287 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3288 if (!e)
3289 return QLA_FUNCTION_FAILED;
3290
3291 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3292 return qla2x00_post_work(vha, e);
8a659571
AV		 3293}
3294
ac280b67
AV		 3295#define qla2x00_post_async_work(name, type) \
3296int qla2x00_post_async_##name##_work( \
3297 struct scsi_qla_host *vha, \
3298 fc_port_t *fcport, uint16_t *data) \
3299{ \
3300 struct qla_work_evt *e; \
3301 \
3302 e = qla2x00_alloc_work(vha, type); \
3303 if (!e) \
3304 return QLA_FUNCTION_FAILED; \
3305 \
3306 e->u.logio.fcport = fcport; \
3307 if (data) { \
3308 e->u.logio.data[0] = data[0]; \
3309 e->u.logio.data[1] = data[1]; \
3310 } \
3311 return qla2x00_post_work(vha, e); \
3312}
3313
3314qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3315qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3316qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3317qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3318qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3319qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3320
3420d36c
AV		 3321int
3322qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3323{
3324 struct qla_work_evt *e;
3325
3326 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3327 if (!e)
3328 return QLA_FUNCTION_FAILED;
3329
3330 e->u.uevent.code = code;
3331 return qla2x00_post_work(vha, e);
3332}
3333
3334static void
3335qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3336{
3337 char event_string[40];
3338 char *envp[] = { event_string, NULL };
3339
3340 switch (code) {
3341 case QLA_UEVENT_CODE_FW_DUMP:
3342 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3343 vha->host_no);
3344 break;
3345 default:
3346 /* do nothing */
3347 break;
3348 }
3349 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3350}
3351
ac280b67 3352void
e315cd28 3353qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3354{
f999f4c1
AV		 3355 struct qla_work_evt *e, *tmp;
3356 unsigned long flags;
3357 LIST_HEAD(work);
0971de7f 3358
f999f4c1
AV		 3359 spin_lock_irqsave(&vha->work_lock, flags);
3360 list_splice_init(&vha->work_list, &work);
3361 spin_unlock_irqrestore(&vha->work_lock, flags);
3362
3363 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3364 list_del_init(&e->list);
0971de7f
AV		 3365
3366 switch (e->type) {
3367 case QLA_EVT_AEN:
e315cd28 3368 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3369 e->u.aen.code, e->u.aen.data);
3370 break;
8a659571
AV		 3371 case QLA_EVT_IDC_ACK:
3372 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3373 break;
ac280b67
AV		 3374 case QLA_EVT_ASYNC_LOGIN:
3375 qla2x00_async_login(vha, e->u.logio.fcport,
3376 e->u.logio.data);
3377 break;
3378 case QLA_EVT_ASYNC_LOGIN_DONE:
3379 qla2x00_async_login_done(vha, e->u.logio.fcport,
3380 e->u.logio.data);
3381 break;
3382 case QLA_EVT_ASYNC_LOGOUT:
3383 qla2x00_async_logout(vha, e->u.logio.fcport);
3384 break;
3385 case QLA_EVT_ASYNC_LOGOUT_DONE:
3386 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3387 e->u.logio.data);
3388 break;
5ff1d584
AV		 3389 case QLA_EVT_ASYNC_ADISC:
3390 qla2x00_async_adisc(vha, e->u.logio.fcport,
3391 e->u.logio.data);
3392 break;
3393 case QLA_EVT_ASYNC_ADISC_DONE:
3394 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3395 e->u.logio.data);
3396 break;
3420d36c
AV		 3397 case QLA_EVT_UEVENT:
3398 qla2x00_uevent_emit(vha, e->u.uevent.code);
3399 break;
0971de7f
AV		 3400 }
3401 if (e->flags & QLA_EVT_FLAG_FREE)
3402 kfree(e);
feafb7b1
AE		 3403
3404 /* For each work completed decrement vha ref count */
3405 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3406 }
e315cd28 3407}
f999f4c1 3408
e315cd28
AC		 3409/* Relogins all the fcports of a vport
3410 * Context: dpc thread
3411 */
3412void qla2x00_relogin(struct scsi_qla_host *vha)
3413{
3414 fc_port_t *fcport;
c6b2fca8 3415 int status;
e315cd28
AC		 3416 uint16_t next_loopid = 0;
3417 struct qla_hw_data *ha = vha->hw;
ac280b67 3418 uint16_t data[2];
e315cd28
AC		 3419
3420 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3421 /*
3422 * If the port is not ONLINE then try to login
3423 * to it if we haven't run out of retries.
3424 */
5ff1d584
AV		 3425 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3426 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 3427 fcport->login_retry--;
e315cd28 3428 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 3429 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 3430 ha->isp_ops->fabric_logout(vha,
3431 fcport->loop_id,
3432 fcport->d_id.b.domain,
3433 fcport->d_id.b.area,
3434 fcport->d_id.b.al_pa);
3435
03bcfb57
JC		 3436 if (fcport->loop_id == FC_NO_LOOP_ID) {
3437 fcport->loop_id = next_loopid =
3438 ha->min_external_loopid;
3439 status = qla2x00_find_new_loop_id(
3440 vha, fcport);
3441 if (status != QLA_SUCCESS) {
3442 /* Ran out of IDs to use */
3443 break;
3444 }
3445 }
3446
ac280b67 3447 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 3448 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3449 data[0] = 0;
3450 data[1] = QLA_LOGIO_LOGIN_RETRIED;
3451 status = qla2x00_post_async_login_work(
3452 vha, fcport, data);
3453 if (status == QLA_SUCCESS)
3454 continue;
3455 /* Attempt a retry. */
3456 status = 1;
3457 } else
3458 status = qla2x00_fabric_login(vha,
3459 fcport, &next_loopid);
e315cd28
AC		 3460 } else
3461 status = qla2x00_local_device_login(vha,
3462 fcport);
3463
e315cd28
AC		 3464 if (status == QLA_SUCCESS) {
3465 fcport->old_loop_id = fcport->loop_id;
3466
7c3df132
SK		 3467 ql_dbg(ql_dbg_disc, vha, 0x2003,
3468 "Port login OK: logged in ID 0x%x.\n",
3469 fcport->loop_id);
e315cd28
AC		 3470
3471 qla2x00_update_fcport(vha, fcport);
3472
3473 } else if (status == 1) {
3474 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3475 /* retry the login again */
7c3df132
SK		 3476 ql_dbg(ql_dbg_disc, vha, 0x2007,
3477 "Retrying %d login again loop_id 0x%x.\n",
3478 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 3479 } else {
3480 fcport->login_retry = 0;
3481 }
3482
3483 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
3484 fcport->loop_id = FC_NO_LOOP_ID;
3485 }
3486 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3487 break;
0971de7f 3488 }
0971de7f
AV		 3489}
3490
1da177e4
LT		 3491/**************************************************************************
3492* qla2x00_do_dpc
3493* This kernel thread is a task that is schedule by the interrupt handler
3494* to perform the background processing for interrupts.
3495*
3496* Notes:
3497* This task always run in the context of a kernel thread. It
3498* is kick-off by the driver's detect code and starts up
3499* up one per adapter. It immediately goes to sleep and waits for
3500* some fibre event. When either the interrupt handler or
3501* the timer routine detects a event it will one of the task
3502* bits then wake us up.
3503**************************************************************************/
3504static int
3505qla2x00_do_dpc(void *data)
3506{
2c3dfe3f 3507 int rval;
e315cd28
AC		 3508 scsi_qla_host_t *base_vha;
3509 struct qla_hw_data *ha;
1da177e4 3510
e315cd28
AC		 3511 ha = (struct qla_hw_data *)data;
3512 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 3513
1da177e4
LT		 3514 set_user_nice(current, -20);
3515
563585ec 3516 set_current_state(TASK_INTERRUPTIBLE);
39a11240 3517 while (!kthread_should_stop()) {
7c3df132
SK		 3518 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
3519 "DPC handler sleeping.\n");
1da177e4 3520
39a11240
CH		 3521 schedule();
3522 __set_current_state(TASK_RUNNING);
1da177e4 3523
7c3df132
SK		 3524 ql_dbg(ql_dbg_dpc, base_vha, 0x4001,
3525 "DPC handler waking up.\n");
3526 ql_dbg(ql_dbg_dpc, base_vha, 0x4002,
3527 "dpc_flags=0x%lx.\n", base_vha->dpc_flags);
1da177e4
LT		 3528
3529 /* Initialization not yet finished. Don't do anything yet. */
e315cd28 3530 if (!base_vha->flags.init_done)
1da177e4
LT		 3531 continue;
3532
85880801 3533 if (ha->flags.eeh_busy) {
7c3df132
SK		 3534 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
3535 "eeh_busy=%d.\n", ha->flags.eeh_busy);
85880801
AV		 3536 continue;
3537 }
3538
1da177e4
LT		 3539 ha->dpc_active = 1;
3540
1da177e4 3541 if (ha->flags.mbox_busy) {
1da177e4
LT		 3542 ha->dpc_active = 0;
3543 continue;
3544 }
3545
e315cd28 3546 qla2x00_do_work(base_vha);
0971de7f 3547
a9083016
GM		 3548 if (IS_QLA82XX(ha)) {
3549 if (test_and_clear_bit(ISP_UNRECOVERABLE,
3550 &base_vha->dpc_flags)) {
3551 qla82xx_idc_lock(ha);
3552 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3553 QLA82XX_DEV_FAILED);
3554 qla82xx_idc_unlock(ha);
7c3df132
SK		 3555 ql_log(ql_log_info, base_vha, 0x4004,
3556 "HW State: FAILED.\n");
a9083016
GM		 3557 qla82xx_device_state_handler(base_vha);
3558 continue;
3559 }
3560
3561 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
3562 &base_vha->dpc_flags)) {
3563
7c3df132
SK		 3564 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
3565 "FCoE context reset scheduled.\n");
a9083016
GM		 3566 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
3567 &base_vha->dpc_flags))) {
3568 if (qla82xx_fcoe_ctx_reset(base_vha)) {
3569 /* FCoE-ctx reset failed.
3570 * Escalate to chip-reset
3571 */
3572 set_bit(ISP_ABORT_NEEDED,
3573 &base_vha->dpc_flags);
3574 }
3575 clear_bit(ABORT_ISP_ACTIVE,
3576 &base_vha->dpc_flags);
3577 }
3578
7c3df132
SK		 3579 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
3580 "FCoE context reset end.\n");
a9083016
GM		 3581 }
3582 }
3583
e315cd28
AC		 3584 if (test_and_clear_bit(ISP_ABORT_NEEDED,
3585 &base_vha->dpc_flags)) {
1da177e4 3586
7c3df132
SK		 3587 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
3588 "ISP abort scheduled.\n");
1da177e4 3589 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 3590 &base_vha->dpc_flags))) {
1da177e4 3591
a9083016 3592 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 3593 /* failed. retry later */
3594 set_bit(ISP_ABORT_NEEDED,
e315cd28 3595 &base_vha->dpc_flags);
99363ef8 3596 }
e315cd28
AC		 3597 clear_bit(ABORT_ISP_ACTIVE,
3598 &base_vha->dpc_flags);
99363ef8
SJ		 3599 }
3600
7c3df132
SK		 3601 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
3602 "ISP abort end.\n");
1da177e4
LT		 3603 }
3604
e315cd28
AC		 3605 if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
3606 qla2x00_update_fcports(base_vha);
3607 clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
c9c5ced9 3608 }
d97994dc 3609
579d12b5 3610 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 3611 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
3612 "Quiescence mode scheduled.\n");
579d12b5
SK		 3613 qla82xx_device_state_handler(base_vha);
3614 clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags);
3615 if (!ha->flags.quiesce_owner) {
3616 qla2x00_perform_loop_resync(base_vha);
3617
3618 qla82xx_idc_lock(ha);
3619 qla82xx_clear_qsnt_ready(base_vha);
3620 qla82xx_idc_unlock(ha);
3621 }
7c3df132
SK		 3622 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
3623 "Quiescence mode end.\n");
579d12b5
SK		 3624 }
3625
e315cd28
AC		 3626 if (test_and_clear_bit(RESET_MARKER_NEEDED,
3627 &base_vha->dpc_flags) &&
3628 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 3629
7c3df132
SK		 3630 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
3631 "Reset marker scheduled.\n");
e315cd28
AC		 3632 qla2x00_rst_aen(base_vha);
3633 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 3634 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
3635 "Reset marker end.\n");
1da177e4
LT		 3636 }
3637
3638 /* Retry each device up to login retry count */
e315cd28
AC		 3639 if ((test_and_clear_bit(RELOGIN_NEEDED,
3640 &base_vha->dpc_flags)) &&
3641 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
3642 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 3643
7c3df132
SK		 3644 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
3645 "Relogin scheduled.\n");
e315cd28 3646 qla2x00_relogin(base_vha);
7c3df132
SK		 3647 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
3648 "Relogin end.\n");
1da177e4
LT		 3649 }
3650
e315cd28
AC		 3651 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
3652 &base_vha->dpc_flags)) {
1da177e4 3653
7c3df132
SK		 3654 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
3655 "Loop resync scheduled.\n");
1da177e4
LT		 3656
3657 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 3658 &base_vha->dpc_flags))) {
1da177e4 3659
e315cd28 3660 rval = qla2x00_loop_resync(base_vha);
1da177e4 3661
e315cd28
AC		 3662 clear_bit(LOOP_RESYNC_ACTIVE,
3663 &base_vha->dpc_flags);
1da177e4
LT		 3664 }
3665
7c3df132
SK		 3666 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
3667 "Loop resync end.\n");
1da177e4
LT		 3668 }
3669
e315cd28
AC		 3670 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
3671 atomic_read(&base_vha->loop_state) == LOOP_READY) {
3672 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
3673 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 3674 }
3675
1da177e4 3676 if (!ha->interrupts_on)
fd34f556 3677 ha->isp_ops->enable_intrs(ha);
1da177e4 3678
e315cd28
AC		 3679 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
3680 &base_vha->dpc_flags))
3681 ha->isp_ops->beacon_blink(base_vha);
f6df144c 3682
e315cd28 3683 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 3684
1da177e4 3685 ha->dpc_active = 0;
563585ec 3686 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 3687 } /* End of while(1) */
563585ec 3688 __set_current_state(TASK_RUNNING);
1da177e4 3689
7c3df132
SK		 3690 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
3691 "DPC handler exiting.\n");
1da177e4
LT		 3692
3693 /*
3694 * Make sure that nobody tries to wake us up again.
3695 */
1da177e4
LT		 3696 ha->dpc_active = 0;
3697
ac280b67
AV		 3698 /* Cleanup any residual CTX SRBs. */
3699 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3700
39a11240
CH		 3701 return 0;
3702}
3703
3704void
e315cd28 3705qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 3706{
e315cd28 3707 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 3708 struct task_struct *t = ha->dpc_thread;
3709
e315cd28 3710 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 3711 wake_up_process(t);
1da177e4
LT		 3712}
3713
1da177e4
LT		 3714/*
3715* qla2x00_rst_aen
3716* Processes asynchronous reset.
3717*
3718* Input:
3719* ha = adapter block pointer.
3720*/
3721static void
e315cd28 3722qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 3723{
e315cd28
AC		 3724 if (vha->flags.online && !vha->flags.reset_active &&
3725 !atomic_read(&vha->loop_down_timer) &&
3726 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 3727 do {
e315cd28 3728 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3729
3730 /*
3731 * Issue marker command only when we are going to start
3732 * the I/O.
3733 */
e315cd28
AC		 3734 vha->marker_needed = 1;
3735 } while (!atomic_read(&vha->loop_down_timer) &&
3736 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 3737 }
3738}
3739
f4f051eb 3740static void
e315cd28 3741qla2x00_sp_free_dma(srb_t *sp)
f4f051eb 3742{
3743 struct scsi_cmnd *cmd = sp->cmd;
bad75002 3744 struct qla_hw_data *ha = sp->fcport->vha->hw;
f4f051eb 3745
3746 if (sp->flags & SRB_DMA_VALID) {
385d70b4 3747 scsi_dma_unmap(cmd);
f4f051eb 3748 sp->flags &= ~SRB_DMA_VALID;
3749 }
bad75002
AE		 3750
3751 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
3752 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
3753 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
3754 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
3755 }
3756
3757 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
3758 /* List assured to be having elements */
3759 qla2x00_clean_dsd_pool(ha, sp);
3760 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
3761 }
3762
3763 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
3764 dma_pool_free(ha->dl_dma_pool, sp->ctx,
3765 ((struct crc_context *)sp->ctx)->crc_ctx_dma);
3766 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
3767 }
3768
fca29703 3769 CMD_SP(cmd) = NULL;
f4f051eb 3770}
3771
3dbe756a 3772static void
083a469d 3773qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp)
f4f051eb 3774{
3775 struct scsi_cmnd *cmd = sp->cmd;
3776
e315cd28 3777 qla2x00_sp_free_dma(sp);
f4f051eb 3778
a9083016
GM		 3779 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
3780 struct ct6_dsd *ctx = sp->ctx;
3781 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd,
3782 ctx->fcp_cmnd_dma);
3783 list_splice(&ctx->dsd_list, &ha->gbl_dsd_list);
3784 ha->gbl_dsd_inuse -= ctx->dsd_use_cnt;
3785 ha->gbl_dsd_avail += ctx->dsd_use_cnt;
3786 mempool_free(sp->ctx, ha->ctx_mempool);
3787 sp->ctx = NULL;
3788 }
f4f051eb 3789
a9083016 3790 mempool_free(sp, ha->srb_mempool);
f4f051eb 3791 cmd->scsi_done(cmd);
3792}
bdf79621 3793
083a469d
GM		 3794void
3795qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp)
3796{
3797 if (atomic_read(&sp->ref_count) == 0) {
7c3df132
SK		 3798 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
3799 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
3800 sp, sp->cmd);
3801 if (ql2xextended_error_logging & ql_dbg_io)
3802 BUG();
083a469d
GM		 3803 return;
3804 }
3805 if (!atomic_dec_and_test(&sp->ref_count))
3806 return;
3807 qla2x00_sp_final_compl(ha, sp);
3808}
3809
1da177e4
LT		 3810/**************************************************************************
3811* qla2x00_timer
3812*
3813* Description:
3814* One second timer
3815*
3816* Context: Interrupt
3817***************************************************************************/
2c3dfe3f 3818void
e315cd28 3819qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 3820{
1da177e4 3821 unsigned long cpu_flags = 0;
1da177e4
LT		 3822 int start_dpc = 0;
3823 int index;
3824 srb_t *sp;
85880801 3825 uint16_t w;
e315cd28 3826 struct qla_hw_data *ha = vha->hw;
73208dfd 3827 struct req_que *req;
85880801 3828
a5b36321 3829 if (ha->flags.eeh_busy) {
7c3df132
SK		 3830 ql_dbg(ql_dbg_timer, vha, 0x6000,
3831 "EEH = %d, restarting timer.\n",
3832 ha->flags.eeh_busy);
a5b36321
LC		 3833 qla2x00_restart_timer(vha, WATCH_INTERVAL);
3834 return;
3835 }
3836
85880801
AV		 3837 /* Hardware read to raise pending EEH errors during mailbox waits. */
3838 if (!pci_channel_offline(ha->pdev))
3839 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
1da177e4 3840
cefcaba6
SK		 3841 /* Make sure qla82xx_watchdog is run only for physical port */
3842 if (!vha->vp_idx && IS_QLA82XX(ha)) {
579d12b5
SK		 3843 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
3844 start_dpc++;
3845 qla82xx_watchdog(vha);
3846 }
3847
1da177e4 3848 /* Loop down handler. */
e315cd28 3849 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 3850 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
3851 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 3852 && vha->flags.online) {
1da177e4 3853
e315cd28
AC		 3854 if (atomic_read(&vha->loop_down_timer) ==
3855 vha->loop_down_abort_time) {
1da177e4 3856
7c3df132
SK		 3857 ql_log(ql_log_info, vha, 0x6008,
3858 "Loop down - aborting the queues before time expires.\n");
1da177e4 3859
e315cd28
AC		 3860 if (!IS_QLA2100(ha) && vha->link_down_timeout)
3861 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 3862
f08b7251
AV		 3863 /*
3864 * Schedule an ISP abort to return any FCP2-device
3865 * commands.
3866 */
2c3dfe3f 3867 /* NPIV - scan physical port only */
e315cd28 3868 if (!vha->vp_idx) {
2c3dfe3f
SJ		 3869 spin_lock_irqsave(&ha->hardware_lock,
3870 cpu_flags);
73208dfd 3871 req = ha->req_q_map[0];
2c3dfe3f
SJ		 3872 for (index = 1;
3873 index < MAX_OUTSTANDING_COMMANDS;
3874 index++) {
3875 fc_port_t *sfcp;
3876
e315cd28 3877 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 3878 if (!sp)
3879 continue;
bad75002 3880 if (sp->ctx && !IS_PROT_IO(sp))
cf53b069 3881 continue;
2c3dfe3f 3882 sfcp = sp->fcport;
f08b7251 3883 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 3884 continue;
bdf79621 3885
8f7daead
GM		 3886 if (IS_QLA82XX(ha))
3887 set_bit(FCOE_CTX_RESET_NEEDED,
3888 &vha->dpc_flags);
3889 else
3890 set_bit(ISP_ABORT_NEEDED,
e315cd28 3891 &vha->dpc_flags);
2c3dfe3f
SJ		 3892 break;
3893 }
3894 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 3895 cpu_flags);
1da177e4 3896 }
1da177e4
LT		 3897 start_dpc++;
3898 }
3899
3900 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 3901 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 3902 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 3903 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 3904 "Loop down - aborting ISP.\n");
3905
8f7daead
GM		 3906 if (IS_QLA82XX(ha))
3907 set_bit(FCOE_CTX_RESET_NEEDED,
3908 &vha->dpc_flags);
3909 else
3910 set_bit(ISP_ABORT_NEEDED,
3911 &vha->dpc_flags);
1da177e4
LT		 3912 }
3913 }
7c3df132
SK		 3914 ql_dbg(ql_dbg_timer, vha, 0x600a,
3915 "Loop down - seconds remaining %d.\n",
3916 atomic_read(&vha->loop_down_timer));
1da177e4
LT		 3917 }
3918
cefcaba6
SK		 3919 /* Check if beacon LED needs to be blinked for physical host only */
3920 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc
SK		 3921 /* There is no beacon_blink function for ISP82xx */
3922 if (!IS_QLA82XX(ha)) {
3923 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
3924 start_dpc++;
3925 }
f6df144c 3926 }
3927
550bf57d 3928 /* Process any deferred work. */
e315cd28 3929 if (!list_empty(&vha->work_list))
550bf57d
AV		 3930 start_dpc++;
3931
1da177e4 3932 /* Schedule the DPC routine if needed */
e315cd28
AC		 3933 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
3934 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
3935 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 3936 start_dpc ||
e315cd28
AC		 3937 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
3938 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 3939 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
3940 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 3941 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7c3df132
SK		 3942 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
3943 ql_dbg(ql_dbg_timer, vha, 0x600b,
3944 "isp_abort_needed=%d loop_resync_needed=%d "
3945 "fcport_update_needed=%d start_dpc=%d "
3946 "reset_marker_needed=%d",
3947 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
3948 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
3949 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
3950 start_dpc,
3951 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
3952 ql_dbg(ql_dbg_timer, vha, 0x600c,
3953 "beacon_blink_needed=%d isp_unrecoverable=%d "
3954 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
3955 "relogin_needed=%d.\n",
3956 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
3957 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
3958 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
3959 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
3960 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 3961 qla2xxx_wake_dpc(vha);
7c3df132 3962 }
1da177e4 3963
e315cd28 3964 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 3965}
3966
5433383e
AV		 3967/* Firmware interface routines. */
3968
a9083016 3969#define FW_BLOBS 8
5433383e
AV		 3970#define FW_ISP21XX 0
3971#define FW_ISP22XX 1
3972#define FW_ISP2300 2
3973#define FW_ISP2322 3
48c02fde 3974#define FW_ISP24XX 4
c3a2f0df 3975#define FW_ISP25XX 5
3a03eb79 3976#define FW_ISP81XX 6
a9083016 3977#define FW_ISP82XX 7
5433383e 3978
bb8ee499
AV		 3979#define FW_FILE_ISP21XX "ql2100_fw.bin"
3980#define FW_FILE_ISP22XX "ql2200_fw.bin"
3981#define FW_FILE_ISP2300 "ql2300_fw.bin"
3982#define FW_FILE_ISP2322 "ql2322_fw.bin"
3983#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 3984#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 3985#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 3986#define FW_FILE_ISP82XX "ql8200_fw.bin"
bb8ee499 3987
e1e82b6f 3988static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 3989
3990static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 3991 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
3992 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
3993 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
3994 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
3995 { .name = FW_FILE_ISP24XX, },
c3a2f0df 3996 { .name = FW_FILE_ISP25XX, },
3a03eb79 3997 { .name = FW_FILE_ISP81XX, },
a9083016 3998 { .name = FW_FILE_ISP82XX, },
5433383e
AV		 3999};
4000
4001struct fw_blob *
e315cd28 4002qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 4003{
e315cd28 4004 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 4005 struct fw_blob *blob;
4006
4007 blob = NULL;
4008 if (IS_QLA2100(ha)) {
4009 blob = &qla_fw_blobs[FW_ISP21XX];
4010 } else if (IS_QLA2200(ha)) {
4011 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 4012 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 4013 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 4014 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 4015 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 4016 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 4017 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 4018 } else if (IS_QLA25XX(ha)) {
4019 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 4020 } else if (IS_QLA81XX(ha)) {
4021 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 4022 } else if (IS_QLA82XX(ha)) {
4023 blob = &qla_fw_blobs[FW_ISP82XX];
5433383e
AV		 4024 }
4025
e1e82b6f 4026 mutex_lock(&qla_fw_lock);
5433383e
AV		 4027 if (blob->fw)
4028 goto out;
4029
4030 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 4031 ql_log(ql_log_warn, vha, 0x0063,
4032 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 4033 blob->fw = NULL;
4034 blob = NULL;
4035 goto out;
4036 }
4037
4038out:
e1e82b6f 4039 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4040 return blob;
4041}
4042
4043static void
4044qla2x00_release_firmware(void)
4045{
4046 int idx;
4047
e1e82b6f 4048 mutex_lock(&qla_fw_lock);
5433383e
AV		 4049 for (idx = 0; idx < FW_BLOBS; idx++)
4050 if (qla_fw_blobs[idx].fw)
4051 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 4052 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4053}
4054
14e660e6
SJ		 4055static pci_ers_result_t
4056qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4057{
85880801
AV		 4058 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
4059 struct qla_hw_data *ha = vha->hw;
4060
7c3df132
SK		 4061 ql_dbg(ql_dbg_aer, vha, 0x9000,
4062 "PCI error detected, state %x.\n", state);
b9b12f73 4063
14e660e6
SJ		 4064 switch (state) {
4065 case pci_channel_io_normal:
85880801 4066 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4067 return PCI_ERS_RESULT_CAN_RECOVER;
4068 case pci_channel_io_frozen:
85880801 4069 ha->flags.eeh_busy = 1;
a5b36321
LC		 4070 /* For ISP82XX complete any pending mailbox cmd */
4071 if (IS_QLA82XX(ha)) {
7190575f 4072 ha->flags.isp82xx_fw_hung = 1;
a5b36321
LC		 4073 if (ha->flags.mbox_busy) {
4074 ha->flags.mbox_int = 1;
7c3df132
SK		 4075 ql_dbg(ql_dbg_aer, vha, 0x9001,
4076 "Due to pci channel io frozen, doing premature "
4077 "completion of mbx command.\n");
a5b36321
LC		 4078 complete(&ha->mbx_intr_comp);
4079 }
4080 }
90a86fc0 4081 qla2x00_free_irqs(vha);
14e660e6 4082 pci_disable_device(pdev);
bddd2d65
LC		 4083 /* Return back all IOs */
4084 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 4085 return PCI_ERS_RESULT_NEED_RESET;
4086 case pci_channel_io_perm_failure:
85880801
AV		 4087 ha->flags.pci_channel_io_perm_failure = 1;
4088 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 4089 return PCI_ERS_RESULT_DISCONNECT;
4090 }
4091 return PCI_ERS_RESULT_NEED_RESET;
4092}
4093
4094static pci_ers_result_t
4095qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
4096{
4097 int risc_paused = 0;
4098 uint32_t stat;
4099 unsigned long flags;
e315cd28
AC		 4100 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4101 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4102 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4103 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
4104
bcc5b6d3
SK		 4105 if (IS_QLA82XX(ha))
4106 return PCI_ERS_RESULT_RECOVERED;
4107
14e660e6
SJ		 4108 spin_lock_irqsave(&ha->hardware_lock, flags);
4109 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
4110 stat = RD_REG_DWORD(&reg->hccr);
4111 if (stat & HCCR_RISC_PAUSE)
4112 risc_paused = 1;
4113 } else if (IS_QLA23XX(ha)) {
4114 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
4115 if (stat & HSR_RISC_PAUSED)
4116 risc_paused = 1;
4117 } else if (IS_FWI2_CAPABLE(ha)) {
4118 stat = RD_REG_DWORD(&reg24->host_status);
4119 if (stat & HSRX_RISC_PAUSED)
4120 risc_paused = 1;
4121 }
4122 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4123
4124 if (risc_paused) {
7c3df132
SK		 4125 ql_log(ql_log_info, base_vha, 0x9003,
4126 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 4127 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 4128
4129 return PCI_ERS_RESULT_NEED_RESET;
4130 } else
4131 return PCI_ERS_RESULT_RECOVERED;
4132}
4133
a5b36321
LC		 4134uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
4135{
4136 uint32_t rval = QLA_FUNCTION_FAILED;
4137 uint32_t drv_active = 0;
4138 struct qla_hw_data *ha = base_vha->hw;
4139 int fn;
4140 struct pci_dev *other_pdev = NULL;
4141
7c3df132
SK		 4142 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
4143 "Entered %s.\n", __func__);
a5b36321
LC		 4144
4145 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4146
4147 if (base_vha->flags.online) {
4148 /* Abort all outstanding commands,
4149 * so as to be requeued later */
4150 qla2x00_abort_isp_cleanup(base_vha);
4151 }
4152
4153
4154 fn = PCI_FUNC(ha->pdev->devfn);
4155 while (fn > 0) {
4156 fn--;
7c3df132
SK		 4157 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
4158 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 4159 other_pdev =
4160 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
4161 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
4162 fn));
4163
4164 if (!other_pdev)
4165 continue;
4166 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 4167 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
4168 "Found PCI func available and enable at 0x%x.\n",
4169 fn);
a5b36321
LC		 4170 pci_dev_put(other_pdev);
4171 break;
4172 }
4173 pci_dev_put(other_pdev);
4174 }
4175
4176 if (!fn) {
4177 /* Reset owner */
7c3df132
SK		 4178 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
4179 "This devfn is reset owner = 0x%x.\n",
4180 ha->pdev->devfn);
a5b36321
LC		 4181 qla82xx_idc_lock(ha);
4182
4183 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4184 QLA82XX_DEV_INITIALIZING);
4185
4186 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
4187 QLA82XX_IDC_VERSION);
4188
4189 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 4190 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
4191 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 4192
4193 qla82xx_idc_unlock(ha);
4194 /* Reset if device is not already reset
4195 * drv_active would be 0 if a reset has already been done
4196 */
4197 if (drv_active)
4198 rval = qla82xx_start_firmware(base_vha);
4199 else
4200 rval = QLA_SUCCESS;
4201 qla82xx_idc_lock(ha);
4202
4203 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4204 ql_log(ql_log_info, base_vha, 0x900b,
4205 "HW State: FAILED.\n");
a5b36321
LC		 4206 qla82xx_clear_drv_active(ha);
4207 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4208 QLA82XX_DEV_FAILED);
4209 } else {
7c3df132
SK		 4210 ql_log(ql_log_info, base_vha, 0x900c,
4211 "HW State: READY.\n");
a5b36321
LC		 4212 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4213 QLA82XX_DEV_READY);
4214 qla82xx_idc_unlock(ha);
7190575f 4215 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 4216 rval = qla82xx_restart_isp(base_vha);
4217 qla82xx_idc_lock(ha);
4218 /* Clear driver state register */
4219 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
4220 qla82xx_set_drv_active(base_vha);
4221 }
4222 qla82xx_idc_unlock(ha);
4223 } else {
7c3df132
SK		 4224 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
4225 "This devfn is not reset owner = 0x%x.\n",
4226 ha->pdev->devfn);
a5b36321
LC		 4227 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
4228 QLA82XX_DEV_READY)) {
7190575f 4229 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 4230 rval = qla82xx_restart_isp(base_vha);
4231 qla82xx_idc_lock(ha);
4232 qla82xx_set_drv_active(base_vha);
4233 qla82xx_idc_unlock(ha);
4234 }
4235 }
4236 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4237
4238 return rval;
4239}
4240
14e660e6
SJ		 4241static pci_ers_result_t
4242qla2xxx_pci_slot_reset(struct pci_dev *pdev)
4243{
4244 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 4245 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4246 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 4247 struct rsp_que *rsp;
4248 int rc, retries = 10;
09483916 4249
7c3df132
SK		 4250 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
4251 "Slot Reset.\n");
85880801 4252
90a86fc0
JC		 4253 /* Workaround: qla2xxx driver which access hardware earlier
4254 * needs error state to be pci_channel_io_online.
4255 * Otherwise mailbox command timesout.
4256 */
4257 pdev->error_state = pci_channel_io_normal;
4258
4259 pci_restore_state(pdev);
4260
8c1496bd
RL		 4261 /* pci_restore_state() clears the saved_state flag of the device
4262 * save restored state which resets saved_state flag
4263 */
4264 pci_save_state(pdev);
4265
09483916
BH		 4266 if (ha->mem_only)
4267 rc = pci_enable_device_mem(pdev);
4268 else
4269 rc = pci_enable_device(pdev);
14e660e6 4270
09483916 4271 if (rc) {
7c3df132 4272 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 4273 "Can't re-enable PCI device after reset.\n");
a5b36321 4274 goto exit_slot_reset;
14e660e6 4275 }
14e660e6 4276
90a86fc0
JC		 4277 rsp = ha->rsp_q_map[0];
4278 if (qla2x00_request_irqs(ha, rsp))
a5b36321 4279 goto exit_slot_reset;
90a86fc0 4280
e315cd28 4281 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 4282 goto exit_slot_reset;
4283
4284 if (IS_QLA82XX(ha)) {
4285 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
4286 ret = PCI_ERS_RESULT_RECOVERED;
4287 goto exit_slot_reset;
4288 } else
4289 goto exit_slot_reset;
4290 }
14e660e6 4291
90a86fc0
JC		 4292 while (ha->flags.mbox_busy && retries--)
4293 msleep(1000);
85880801 4294
e315cd28 4295 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 4296 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 4297 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 4298 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 4299
90a86fc0 4300
a5b36321 4301exit_slot_reset:
7c3df132
SK		 4302 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
4303 "slot_reset return %x.\n", ret);
85880801 4304
14e660e6
SJ		 4305 return ret;
4306}
4307
4308static void
4309qla2xxx_pci_resume(struct pci_dev *pdev)
4310{
e315cd28
AC		 4311 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4312 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4313 int ret;
4314
7c3df132
SK		 4315 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
4316 "pci_resume.\n");
85880801 4317
e315cd28 4318 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 4319 if (ret != QLA_SUCCESS) {
7c3df132
SK		 4320 ql_log(ql_log_fatal, base_vha, 0x9002,
4321 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 4322 }
85880801 4323
3e46f031
LC		 4324 pci_cleanup_aer_uncorrect_error_status(pdev);
4325
85880801 4326 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4327}
4328
4329static struct pci_error_handlers qla2xxx_err_handler = {
4330 .error_detected = qla2xxx_pci_error_detected,
4331 .mmio_enabled = qla2xxx_pci_mmio_enabled,
4332 .slot_reset = qla2xxx_pci_slot_reset,
4333 .resume = qla2xxx_pci_resume,
4334};
4335
5433383e 4336static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 4337 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
4338 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
4339 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
4340 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
4341 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
4342 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
4343 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
4344 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
4345 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 4346 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 4347 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
4348 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 4349 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
3a03eb79 4350 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 4351 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5433383e
AV		 4352 { 0 },
4353};
4354MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
4355
fca29703 4356static struct pci_driver qla2xxx_pci_driver = {
cb63067a 4357 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 4358 .driver = {
4359 .owner = THIS_MODULE,
4360 },
fca29703 4361 .id_table = qla2xxx_pci_tbl,
7ee61397 4362 .probe = qla2x00_probe_one,
4c993f76 4363 .remove = qla2x00_remove_one,
e30d1756 4364 .shutdown = qla2x00_shutdown,
14e660e6 4365 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 4366};
4367
6a03b4cd
HZ		 4368static struct file_operations apidev_fops = {
4369 .owner = THIS_MODULE,
6038f373 4370 .llseek = noop_llseek,
6a03b4cd
HZ		 4371};
4372
1da177e4
LT		 4373/**
4374 * qla2x00_module_init - Module initialization.
4375 **/
4376static int __init
4377qla2x00_module_init(void)
4378{
fca29703
AV		 4379 int ret = 0;
4380
1da177e4 4381 /* Allocate cache for SRBs. */
354d6b21 4382 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 4383 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 4384 if (srb_cachep == NULL) {
7c3df132
SK		 4385 ql_log(ql_log_fatal, NULL, 0x0001,
4386 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 4387 return -ENOMEM;
4388 }
4389
4390 /* Derive version string. */
4391 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 4392 if (ql2xextended_error_logging)
0181944f
AV		 4393 strcat(qla2x00_version_str, "-debug");
4394
1c97a12a
AV		 4395 qla2xxx_transport_template =
4396 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 4397 if (!qla2xxx_transport_template) {
4398 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 4399 ql_log(ql_log_fatal, NULL, 0x0002,
4400 "fc_attach_transport failed...Failing load!.\n");
1da177e4 4401 return -ENODEV;
2c3dfe3f 4402 }
6a03b4cd
HZ		 4403
4404 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
4405 if (apidev_major < 0) {
7c3df132
SK		 4406 ql_log(ql_log_fatal, NULL, 0x0003,
4407 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 4408 }
4409
2c3dfe3f
SJ		 4410 qla2xxx_transport_vport_template =
4411 fc_attach_transport(&qla2xxx_transport_vport_functions);
4412 if (!qla2xxx_transport_vport_template) {
4413 kmem_cache_destroy(srb_cachep);
4414 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 4415 ql_log(ql_log_fatal, NULL, 0x0004,
4416 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 4417 return -ENODEV;
2c3dfe3f 4418 }
7c3df132
SK		 4419 ql_log(ql_log_info, NULL, 0x0005,
4420 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 4421 qla2x00_version_str);
7ee61397 4422 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 4423 if (ret) {
4424 kmem_cache_destroy(srb_cachep);
4425 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 4426 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 4427 ql_log(ql_log_fatal, NULL, 0x0006,
4428 "pci_register_driver failed...ret=%d Failing load!.\n",
4429 ret);
fca29703
AV		 4430 }
4431 return ret;
1da177e4
LT		 4432}
4433
4434/**
4435 * qla2x00_module_exit - Module cleanup.
4436 **/
4437static void __exit
4438qla2x00_module_exit(void)
4439{
6a03b4cd 4440 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 4441 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 4442 qla2x00_release_firmware();
354d6b21 4443 kmem_cache_destroy(srb_cachep);
a9083016
GM		 4444 if (ctx_cachep)
4445 kmem_cache_destroy(ctx_cachep);
1da177e4 4446 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 4447 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 4448}
4449
4450module_init(qla2x00_module_init);
4451module_exit(qla2x00_module_exit);
4452
4453MODULE_AUTHOR("QLogic Corporation");
4454MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
4455MODULE_LICENSE("GPL");
4456MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 4457MODULE_FIRMWARE(FW_FILE_ISP21XX);
4458MODULE_FIRMWARE(FW_FILE_ISP22XX);
4459MODULE_FIRMWARE(FW_FILE_ISP2300);
4460MODULE_FIRMWARE(FW_FILE_ISP2322);
4461MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 4462MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)