projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
qla2xxx: Enable Extended Logins support
[linux-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 83MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
3ce8866c 99 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 100
a9083016 101int ql2xshiftctondsd = 6;
f2019cb1 102module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 103MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
7e47e5ca 107int ql2xfdmienable=1;
de187df8 108module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 109MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 112
50280c01
CD		 113#define MAX_Q_DEPTH 32
114static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 115module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
df7baa50 119
9e522cd8
AE		 120int ql2xenabledif = 2;
121module_param(ql2xenabledif, int, S_IRUGO);
bad75002 122MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 123 " Enable T10-CRC-DIF:\n"
124 " Default is 2.\n"
125 " 0 -- No DIF Support\n"
126 " 1 -- Enable DIF for all types\n"
127 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 128
8cb2049c 129int ql2xenablehba_err_chk = 2;
bad75002
AE		 130module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
131MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 132 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 133 " Default is 2.\n"
8cb2049c
AE		 134 " 0 -- Error isolation disabled\n"
135 " 1 -- Error isolation enabled only for DIX Type 0\n"
136 " 2 -- Error isolation enabled for all Types\n");
bad75002 137
e5896bd5 138int ql2xiidmaenable=1;
f2019cb1 139module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 140MODULE_PARM_DESC(ql2xiidmaenable,
141 "Enables iIDMA settings "
142 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
143
73208dfd 144int ql2xmaxqueues = 1;
f2019cb1 145module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 146MODULE_PARM_DESC(ql2xmaxqueues,
147 "Enables MQ settings "
ae68230c
JP		 148 "Default is 1 for single queue. Set it to number "
149 "of queues in MQ mode.");
68ca949c
AC		 150
151int ql2xmultique_tag;
f2019cb1 152module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 153MODULE_PARM_DESC(ql2xmultique_tag,
154 "Enables CPU affinity settings for the driver "
155 "Default is 0 for no affinity of request and response IO. "
156 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 157
158int ql2xfwloadbin;
86e45bf6 159module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 160MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 161 "Option to specify location from which to load ISP firmware:.\n"
162 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 163 " interface.\n"
164 " 1 -- load firmware from flash.\n"
165 " 0 -- use default semantics.\n");
166
ae97c91e 167int ql2xetsenable;
f2019cb1 168module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 169MODULE_PARM_DESC(ql2xetsenable,
170 "Enables firmware ETS burst."
171 "Default is 0 - skip ETS enablement.");
172
6907869d 173int ql2xdbwr = 1;
86e45bf6 174module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 175MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 176 "Option to specify scheme for request queue posting.\n"
177 " 0 -- Regular doorbell.\n"
178 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 179
f4c496c1 180int ql2xtargetreset = 1;
f2019cb1 181module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 182MODULE_PARM_DESC(ql2xtargetreset,
183 "Enable target reset."
184 "Default is 1 - use hw defaults.");
185
4da26e16 186int ql2xgffidenable;
f2019cb1 187module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 188MODULE_PARM_DESC(ql2xgffidenable,
189 "Enables GFF_ID checks of port type. "
190 "Default is 0 - Do not use GFF_ID information.");
a9083016 191
3822263e 192int ql2xasynctmfenable;
f2019cb1 193module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 194MODULE_PARM_DESC(ql2xasynctmfenable,
195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
196 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 197
198int ql2xdontresethba;
86e45bf6 199module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 200MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 201 "Option to specify reset behaviour.\n"
202 " 0 (Default) -- Reset on failure.\n"
203 " 1 -- Do not reset on failure.\n");
ed0de87c 204
1abf635d
HR		 205uint64_t ql2xmaxlun = MAX_LUNS;
206module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 207MODULE_PARM_DESC(ql2xmaxlun,
208 "Defines the maximum LU number to register with the SCSI "
209 "midlayer. Default is 65535.");
210
08de2844
GM		 211int ql2xmdcapmask = 0x1F;
212module_param(ql2xmdcapmask, int, S_IRUGO);
213MODULE_PARM_DESC(ql2xmdcapmask,
214 "Set the Minidump driver capture mask level. "
6e96fa7b 215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 216
3aadff35 217int ql2xmdenable = 1;
08de2844
GM		 218module_param(ql2xmdenable, int, S_IRUGO);
219MODULE_PARM_DESC(ql2xmdenable,
220 "Enable/disable MiniDump. "
3aadff35
GM		 221 "0 - MiniDump disabled. "
222 "1 (Default) - MiniDump enabled.");
08de2844 223
b0d6cabd
HM		 224int ql2xexlogins = 0;
225module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
226MODULE_PARM_DESC(ql2xexlogins,
227 "Number of extended Logins. "
228 "0 (Default)- Disabled.");
229
1da177e4 230/*
fa2a1ce5 231 * SCSI host template entry points
1da177e4
LT		 232 */
233static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 234static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 235static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
236static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 237static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 238static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 239static int qla2xxx_eh_abort(struct scsi_cmnd *);
240static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 241static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 242static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
243static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 244
1a2fbf18 245static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 246static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 247static void qla83xx_disable_laser(scsi_qla_host_t *vha);
ce7e4af7 248
a5326f86 249struct scsi_host_template qla2xxx_driver_template = {
1da177e4 250 .module = THIS_MODULE,
cb63067a 251 .name = QLA2XXX_DRIVER_NAME,
a5326f86 252 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 253
254 .eh_abort_handler = qla2xxx_eh_abort,
255 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 256 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 257 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
258 .eh_host_reset_handler = qla2xxx_eh_host_reset,
259
260 .slave_configure = qla2xxx_slave_configure,
261
262 .slave_alloc = qla2xxx_slave_alloc,
263 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 264 .scan_finished = qla2xxx_scan_finished,
265 .scan_start = qla2xxx_scan_start,
db5ed4df 266 .change_queue_depth = scsi_change_queue_depth,
fca29703
AV		 267 .this_id = -1,
268 .cmd_per_lun = 3,
269 .use_clustering = ENABLE_CLUSTERING,
270 .sg_tablesize = SG_ALL,
271
272 .max_sectors = 0xFFFF,
afb046e2 273 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 274
275 .supported_mode = MODE_INITIATOR,
c40ecc12 276 .track_queue_depth = 1,
fca29703
AV		 277};
278
1da177e4 279static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 280struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 281
1da177e4
LT		 282/* TODO Convert to inlines
283 *
284 * Timer routines
285 */
1da177e4 286
2c3dfe3f 287__inline__ void
e315cd28 288qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 289{
e315cd28
AC		 290 init_timer(&vha->timer);
291 vha->timer.expires = jiffies + interval * HZ;
292 vha->timer.data = (unsigned long)vha;
293 vha->timer.function = (void (*)(unsigned long))func;
294 add_timer(&vha->timer);
295 vha->timer_active = 1;
1da177e4
LT		 296}
297
298static inline void
e315cd28 299qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 300{
a9083016 301 /* Currently used for 82XX only. */
7c3df132
SK		 302 if (vha->device_flags & DFLG_DEV_FAILED) {
303 ql_dbg(ql_dbg_timer, vha, 0x600d,
304 "Device in a failed state, returning.\n");
a9083016 305 return;
7c3df132 306 }
a9083016 307
e315cd28 308 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 309}
310
a824ebb3 311static __inline__ void
e315cd28 312qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 313{
e315cd28
AC		 314 del_timer_sync(&vha->timer);
315 vha->timer_active = 0;
1da177e4
LT		 316}
317
1da177e4
LT		 318static int qla2x00_do_dpc(void *data);
319
320static void qla2x00_rst_aen(scsi_qla_host_t *);
321
73208dfd
AC		 322static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
323 struct req_que **, struct rsp_que **);
e30d1756 324static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 325static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 326
1da177e4 327/* -------------------------------------------------------------------------- */
9a347ff4
CD		 328static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
329 struct rsp_que *rsp)
73208dfd 330{
7c3df132 331 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 332 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 333 GFP_KERNEL);
334 if (!ha->req_q_map) {
7c3df132
SK		 335 ql_log(ql_log_fatal, vha, 0x003b,
336 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 337 goto fail_req_map;
338 }
339
2afa19a9 340 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 341 GFP_KERNEL);
342 if (!ha->rsp_q_map) {
7c3df132
SK		 343 ql_log(ql_log_fatal, vha, 0x003c,
344 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 345 goto fail_rsp_map;
346 }
9a347ff4
CD		 347 /*
348 * Make sure we record at least the request and response queue zero in
349 * case we need to free them if part of the probe fails.
350 */
351 ha->rsp_q_map[0] = rsp;
352 ha->req_q_map[0] = req;
73208dfd
AC		 353 set_bit(0, ha->rsp_qid_map);
354 set_bit(0, ha->req_qid_map);
355 return 1;
356
357fail_rsp_map:
358 kfree(ha->req_q_map);
359 ha->req_q_map = NULL;
360fail_req_map:
361 return -ENOMEM;
362}
363
2afa19a9 364static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 365{
8ae6d9c7
GM		 366 if (IS_QLAFX00(ha)) {
367 if (req && req->ring_fx00)
368 dma_free_coherent(&ha->pdev->dev,
369 (req->length_fx00 + 1) * sizeof(request_t),
370 req->ring_fx00, req->dma_fx00);
371 } else if (req && req->ring)
73208dfd
AC		 372 dma_free_coherent(&ha->pdev->dev,
373 (req->length + 1) * sizeof(request_t),
374 req->ring, req->dma);
375
8d93f550
CD		 376 if (req)
377 kfree(req->outstanding_cmds);
378
73208dfd
AC		 379 kfree(req);
380 req = NULL;
381}
382
2afa19a9
AC		 383static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
384{
8ae6d9c7
GM		 385 if (IS_QLAFX00(ha)) {
386 if (rsp && rsp->ring)
387 dma_free_coherent(&ha->pdev->dev,
388 (rsp->length_fx00 + 1) * sizeof(request_t),
389 rsp->ring_fx00, rsp->dma_fx00);
390 } else if (rsp && rsp->ring) {
2afa19a9
AC		 391 dma_free_coherent(&ha->pdev->dev,
392 (rsp->length + 1) * sizeof(response_t),
393 rsp->ring, rsp->dma);
8ae6d9c7 394 }
2afa19a9
AC		 395 kfree(rsp);
396 rsp = NULL;
397}
398
73208dfd
AC		 399static void qla2x00_free_queues(struct qla_hw_data *ha)
400{
401 struct req_que *req;
402 struct rsp_que *rsp;
403 int cnt;
404
2afa19a9 405 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 406 req = ha->req_q_map[cnt];
2afa19a9 407 qla2x00_free_req_que(ha, req);
73208dfd 408 }
73208dfd
AC		 409 kfree(ha->req_q_map);
410 ha->req_q_map = NULL;
2afa19a9
AC		 411
412 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
413 rsp = ha->rsp_q_map[cnt];
414 qla2x00_free_rsp_que(ha, rsp);
415 }
416 kfree(ha->rsp_q_map);
417 ha->rsp_q_map = NULL;
73208dfd
AC		 418}
419
68ca949c
AC		 420static int qla25xx_setup_mode(struct scsi_qla_host *vha)
421{
422 uint16_t options = 0;
423 int ques, req, ret;
424 struct qla_hw_data *ha = vha->hw;
425
7163ea81 426 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 427 ql_log(ql_log_warn, vha, 0x00d8,
428 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 429 goto fail;
430 }
68ca949c 431 if (ql2xmultique_tag) {
68ca949c
AC		 432 /* create a request queue for IO */
433 options |= BIT_7;
434 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
435 QLA_DEFAULT_QUE_QOS);
436 if (!req) {
7c3df132
SK		 437 ql_log(ql_log_warn, vha, 0x00e0,
438 "Failed to create request queue.\n");
68ca949c
AC		 439 goto fail;
440 }
278274d5 441 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 442 vha->req = ha->req_q_map[req];
443 options |= BIT_1;
444 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
445 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
446 if (!ret) {
7c3df132
SK		 447 ql_log(ql_log_warn, vha, 0x00e8,
448 "Failed to create response queue.\n");
68ca949c
AC		 449 goto fail2;
450 }
451 }
7163ea81 452 ha->flags.cpu_affinity_enabled = 1;
7c3df132 453 ql_dbg(ql_dbg_multiq, vha, 0xc007,
6ef68da7 454 "CPU affinity mode enabled, "
7c3df132
SK		 455 "no. of response queues:%d no. of request queues:%d.\n",
456 ha->max_rsp_queues, ha->max_req_queues);
457 ql_dbg(ql_dbg_init, vha, 0x00e9,
6ef68da7 458 "CPU affinity mode enabled, "
7c3df132
SK		 459 "no. of response queues:%d no. of request queues:%d.\n",
460 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 461 }
462 return 0;
463fail2:
464 qla25xx_delete_queues(vha);
7163ea81
AC		 465 destroy_workqueue(ha->wq);
466 ha->wq = NULL;
0cd33fcf 467 vha->req = ha->req_q_map[0];
68ca949c
AC		 468fail:
469 ha->mqenable = 0;
7163ea81
AC		 470 kfree(ha->req_q_map);
471 kfree(ha->rsp_q_map);
472 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 473 return 1;
474}
475
1da177e4 476static char *
e315cd28 477qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 478{
e315cd28 479 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 480 static char *pci_bus_modes[] = {
481 "33", "66", "100", "133",
482 };
483 uint16_t pci_bus;
484
485 strcpy(str, "PCI");
486 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
487 if (pci_bus) {
488 strcat(str, "-X (");
489 strcat(str, pci_bus_modes[pci_bus]);
490 } else {
491 pci_bus = (ha->pci_attr & BIT_8) >> 8;
492 strcat(str, " (");
493 strcat(str, pci_bus_modes[pci_bus]);
494 }
495 strcat(str, " MHz)");
496
497 return (str);
498}
499
fca29703 500static char *
e315cd28 501qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 502{
503 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 504 struct qla_hw_data *ha = vha->hw;
fca29703 505 uint32_t pci_bus;
fca29703 506
62a276f8 507 if (pci_is_pcie(ha->pdev)) {
fca29703 508 char lwstr[6];
62a276f8 509 uint32_t lstat, lspeed, lwidth;
fca29703 510
62a276f8
BH		 511 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
512 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
513 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 514
515 strcpy(str, "PCIe (");
49300af7
SK		 516 switch (lspeed) {
517 case 1:
c87a0d8c 518 strcat(str, "2.5GT/s ");
49300af7
SK		 519 break;
520 case 2:
c87a0d8c 521 strcat(str, "5.0GT/s ");
49300af7
SK		 522 break;
523 case 3:
524 strcat(str, "8.0GT/s ");
525 break;
526 default:
fca29703 527 strcat(str, "<unknown> ");
49300af7
SK		 528 break;
529 }
fca29703
AV		 530 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
531 strcat(str, lwstr);
532
533 return str;
534 }
535
536 strcpy(str, "PCI");
537 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
538 if (pci_bus == 0 || pci_bus == 8) {
539 strcat(str, " (");
540 strcat(str, pci_bus_modes[pci_bus >> 3]);
541 } else {
542 strcat(str, "-X ");
543 if (pci_bus & BIT_2)
544 strcat(str, "Mode 2");
545 else
546 strcat(str, "Mode 1");
547 strcat(str, " (");
548 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
549 }
550 strcat(str, " MHz)");
551
552 return str;
553}
554
e5f82ab8 555static char *
df57caba 556qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 557{
558 char un_str[10];
e315cd28 559 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 560
df57caba
HM		 561 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
562 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 563
564 if (ha->fw_attributes & BIT_9) {
565 strcat(str, "FLX");
566 return (str);
567 }
568
569 switch (ha->fw_attributes & 0xFF) {
570 case 0x7:
571 strcat(str, "EF");
572 break;
573 case 0x17:
574 strcat(str, "TP");
575 break;
576 case 0x37:
577 strcat(str, "IP");
578 break;
579 case 0x77:
580 strcat(str, "VI");
581 break;
582 default:
583 sprintf(un_str, "(%x)", ha->fw_attributes);
584 strcat(str, un_str);
585 break;
586 }
587 if (ha->fw_attributes & 0x100)
588 strcat(str, "X");
589
590 return (str);
591}
592
e5f82ab8 593static char *
df57caba 594qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 595{
e315cd28 596 struct qla_hw_data *ha = vha->hw;
f0883ac6 597
df57caba 598 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 599 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 600 return str;
fca29703
AV		 601}
602
9ba56b95
GM		 603void
604qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 605{
9ba56b95
GM		 606 srb_t *sp = (srb_t *)ptr;
607 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
608 struct qla_hw_data *ha = sp->fcport->vha->hw;
609 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 610
9ba56b95
GM		 611 if (sp->flags & SRB_DMA_VALID) {
612 scsi_dma_unmap(cmd);
613 sp->flags &= ~SRB_DMA_VALID;
7c3df132 614 }
fca29703 615
9ba56b95
GM		 616 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
617 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
618 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
619 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
620 }
621
622 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
623 /* List assured to be having elements */
f83adb61 624 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 625 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
626 }
627
628 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
629 dma_pool_free(ha->dl_dma_pool, ctx,
630 ((struct crc_context *)ctx)->crc_ctx_dma);
631 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
632 }
633
634 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
635 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 636
9ba56b95
GM		 637 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
638 ctx1->fcp_cmnd_dma);
639 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
640 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
641 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
642 mempool_free(ctx1, ha->ctx_mempool);
643 ctx1 = NULL;
644 }
645
646 CMD_SP(cmd) = NULL;
b00ee7d7 647 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 648}
649
14b06808 650static void
9ba56b95
GM		 651qla2x00_sp_compl(void *data, void *ptr, int res)
652{
653 struct qla_hw_data *ha = (struct qla_hw_data *)data;
654 srb_t *sp = (srb_t *)ptr;
655 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
656
657 cmd->result = res;
658
659 if (atomic_read(&sp->ref_count) == 0) {
660 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
661 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
662 sp, GET_CMD_SP(sp));
663 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 664 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 665 return;
666 }
667 if (!atomic_dec_and_test(&sp->ref_count))
668 return;
669
670 qla2x00_sp_free_dma(ha, sp);
671 cmd->scsi_done(cmd);
fca29703
AV		 672}
673
8ae6d9c7
GM		 674/* If we are SP1 here, we need to still take and release the host_lock as SP1
675 * does not have the changes necessary to avoid taking host->host_lock.
676 */
1da177e4 677static int
f5e3e40b 678qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 679{
134ae078 680 scsi_qla_host_t *vha = shost_priv(host);
fca29703 681 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 682 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 683 struct qla_hw_data *ha = vha->hw;
684 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 685 srb_t *sp;
686 int rval;
687
85880801 688 if (ha->flags.eeh_busy) {
7c3df132 689 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 690 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 691 "PCI Channel IO permanent failure, exiting "
692 "cmd=%p.\n", cmd);
b9b12f73 693 cmd->result = DID_NO_CONNECT << 16;
7c3df132 694 } else {
5f28d2d7 695 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 696 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 697 cmd->result = DID_REQUEUE << 16;
7c3df132 698 }
14e660e6
SJ		 699 goto qc24_fail_command;
700 }
701
19a7b4ae
JSEC		 702 rval = fc_remote_port_chkready(rport);
703 if (rval) {
704 cmd->result = rval;
5f28d2d7 705 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 706 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
707 cmd, rval);
fca29703
AV		 708 goto qc24_fail_command;
709 }
710
bad75002
AE		 711 if (!vha->flags.difdix_supported &&
712 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 713 ql_dbg(ql_dbg_io, vha, 0x3004,
714 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
715 cmd);
bad75002
AE		 716 cmd->result = DID_NO_CONNECT << 16;
717 goto qc24_fail_command;
718 }
aa651be8
CD		 719
720 if (!fcport) {
721 cmd->result = DID_NO_CONNECT << 16;
722 goto qc24_fail_command;
723 }
724
fca29703
AV		 725 if (atomic_read(&fcport->state) != FCS_ONLINE) {
726 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 727 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 728 ql_dbg(ql_dbg_io, vha, 0x3005,
729 "Returning DNC, fcport_state=%d loop_state=%d.\n",
730 atomic_read(&fcport->state),
731 atomic_read(&base_vha->loop_state));
fca29703
AV		 732 cmd->result = DID_NO_CONNECT << 16;
733 goto qc24_fail_command;
734 }
7b594131 735 goto qc24_target_busy;
fca29703
AV		 736 }
737
e05fe292
CD		 738 /*
739 * Return target busy if we've received a non-zero retry_delay_timer
740 * in a FCP_RSP.
741 */
975f7d46
BP		 742 if (fcport->retry_delay_timestamp == 0) {
743 /* retry delay not set */
744 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 745 fcport->retry_delay_timestamp = 0;
746 else
747 goto qc24_target_busy;
748
b00ee7d7 749 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 750 if (!sp)
f5e3e40b 751 goto qc24_host_busy;
fca29703 752
9ba56b95
GM		 753 sp->u.scmd.cmd = cmd;
754 sp->type = SRB_SCSI_CMD;
755 atomic_set(&sp->ref_count, 1);
756 CMD_SP(cmd) = (void *)sp;
757 sp->free = qla2x00_sp_free_dma;
758 sp->done = qla2x00_sp_compl;
759
e315cd28 760 rval = ha->isp_ops->start_scsi(sp);
7c3df132 761 if (rval != QLA_SUCCESS) {
53016ed3 762 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 763 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 764 goto qc24_host_busy_free_sp;
7c3df132 765 }
fca29703 766
fca29703
AV		 767 return 0;
768
769qc24_host_busy_free_sp:
9ba56b95 770 qla2x00_sp_free_dma(ha, sp);
fca29703 771
f5e3e40b 772qc24_host_busy:
fca29703
AV		 773 return SCSI_MLQUEUE_HOST_BUSY;
774
7b594131
MC		 775qc24_target_busy:
776 return SCSI_MLQUEUE_TARGET_BUSY;
777
fca29703 778qc24_fail_command:
f5e3e40b 779 cmd->scsi_done(cmd);
fca29703
AV		 780
781 return 0;
782}
783
1da177e4
LT		 784/*
785 * qla2x00_eh_wait_on_command
786 * Waits for the command to be returned by the Firmware for some
787 * max time.
788 *
789 * Input:
1da177e4 790 * cmd = Scsi Command to wait on.
1da177e4
LT		 791 *
792 * Return:
793 * Not Found : 0
794 * Found : 1
795 */
796static int
e315cd28 797qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 798{
fe74c71f 799#define ABORT_POLLING_PERIOD 1000
478c3b03 800#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 801 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 802 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
803 struct qla_hw_data *ha = vha->hw;
f4f051eb 804 int ret = QLA_SUCCESS;
1da177e4 805
85880801 806 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 807 ql_dbg(ql_dbg_taskm, vha, 0x8005,
808 "Return:eh_wait.\n");
85880801
AV		 809 return ret;
810 }
811
d970432c 812 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 813 msleep(ABORT_POLLING_PERIOD);
f4f051eb 814 }
815 if (CMD_SP(cmd))
816 ret = QLA_FUNCTION_FAILED;
1da177e4 817
f4f051eb 818 return ret;
1da177e4
LT		 819}
820
821/*
822 * qla2x00_wait_for_hba_online
fa2a1ce5 823 * Wait till the HBA is online after going through
1da177e4
LT		 824 * <= MAX_RETRIES_OF_ISP_ABORT or
825 * finally HBA is disabled ie marked offline
826 *
827 * Input:
828 * ha - pointer to host adapter structure
fa2a1ce5
AV		 829 *
830 * Note:
1da177e4
LT		 831 * Does context switching-Release SPIN_LOCK
832 * (if any) before calling this routine.
833 *
834 * Return:
835 * Success (Adapter is online) : 0
836 * Failed (Adapter is offline/disabled) : 1
837 */
854165f4 838int
e315cd28 839qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 840{
fca29703
AV		 841 int return_status;
842 unsigned long wait_online;
e315cd28
AC		 843 struct qla_hw_data *ha = vha->hw;
844 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 845
fa2a1ce5 846 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 847 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
848 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
849 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
850 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 851
852 msleep(1000);
853 }
e315cd28 854 if (base_vha->flags.online)
fa2a1ce5 855 return_status = QLA_SUCCESS;
1da177e4
LT		 856 else
857 return_status = QLA_FUNCTION_FAILED;
858
1da177e4
LT		 859 return (return_status);
860}
861
86fbee86 862/*
638a1a01
SC		 863 * qla2x00_wait_for_hba_ready
864 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 865 *
866 * Input:
867 * ha - pointer to host adapter structure
868 *
869 * Note:
870 * Does context switching-Release SPIN_LOCK
871 * (if any) before calling this routine.
872 *
86fbee86 873 */
638a1a01
SC		 874static void
875qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 876{
86fbee86 877 struct qla_hw_data *ha = vha->hw;
86fbee86 878
9d35894d
SC		 879 while (((qla2x00_reset_active(vha)) || ha->dpc_active ||
880 ha->flags.mbox_busy) ||
881 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
882 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags))
86fbee86 883 msleep(1000);
86fbee86
LC		 884}
885
2533cf67
LC		 886int
887qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
888{
889 int return_status;
890 unsigned long wait_reset;
891 struct qla_hw_data *ha = vha->hw;
892 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
893
894 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
895 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
896 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
897 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
898 ha->dpc_active) && time_before(jiffies, wait_reset)) {
899
900 msleep(1000);
901
902 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
903 ha->flags.chip_reset_done)
904 break;
905 }
906 if (ha->flags.chip_reset_done)
907 return_status = QLA_SUCCESS;
908 else
909 return_status = QLA_FUNCTION_FAILED;
910
911 return return_status;
912}
913
083a469d
GM		 914static void
915sp_get(struct srb *sp)
916{
917 atomic_inc(&sp->ref_count);
918}
919
1da177e4
LT		 920/**************************************************************************
921* qla2xxx_eh_abort
922*
923* Description:
924* The abort function will abort the specified command.
925*
926* Input:
927* cmd = Linux SCSI command packet to be aborted.
928*
929* Returns:
930* Either SUCCESS or FAILED.
931*
932* Note:
2ea00202 933* Only return FAILED if command not returned by firmware.
1da177e4 934**************************************************************************/
e5f82ab8 935static int
1da177e4
LT		 936qla2xxx_eh_abort(struct scsi_cmnd *cmd)
937{
e315cd28 938 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 939 srb_t *sp;
4e98d3b8 940 int ret;
9cb78c16
HR		 941 unsigned int id;
942 uint64_t lun;
18e144d3 943 unsigned long flags;
f934c9d0 944 int rval, wait = 0;
e315cd28 945 struct qla_hw_data *ha = vha->hw;
1da177e4 946
f4f051eb 947 if (!CMD_SP(cmd))
2ea00202 948 return SUCCESS;
1da177e4 949
4e98d3b8
AV		 950 ret = fc_block_scsi_eh(cmd);
951 if (ret != 0)
952 return ret;
953 ret = SUCCESS;
954
f4f051eb 955 id = cmd->device->id;
956 lun = cmd->device->lun;
1da177e4 957
e315cd28 958 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 959 sp = (srb_t *) CMD_SP(cmd);
960 if (!sp) {
961 spin_unlock_irqrestore(&ha->hardware_lock, flags);
962 return SUCCESS;
963 }
1da177e4 964
7c3df132 965 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 966 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
967 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 968
170babc3
MC		 969 /* Get a reference to the sp and drop the lock.*/
970 sp_get(sp);
083a469d 971
e315cd28 972 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 973 rval = ha->isp_ops->abort_command(sp);
974 if (rval) {
96219424 975 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 976 ret = SUCCESS;
96219424 977 else
f934c9d0
CD		 978 ret = FAILED;
979
7c3df132 980 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 981 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 982 } else {
7c3df132 983 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 984 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 985 wait = 1;
986 }
75942064
SK		 987
988 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 989 sp->done(ha, sp, 0);
75942064 990 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 991
bc91ade9
CD		 992 /* Did the command return during mailbox execution? */
993 if (ret == FAILED && !CMD_SP(cmd))
994 ret = SUCCESS;
995
f4f051eb 996 /* Wait for the command to be returned. */
2ea00202 997 if (wait) {
e315cd28 998 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 999 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1000 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1001 ret = FAILED;
f4f051eb 1002 }
1da177e4 1003 }
1da177e4 1004
7c3df132 1005 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1006 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1007 vha->host_no, id, lun, wait, ret);
1da177e4 1008
f4f051eb 1009 return ret;
1010}
1da177e4 1011
4d78c973 1012int
e315cd28 1013qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1014 uint64_t l, enum nexus_wait_type type)
f4f051eb 1015{
17d98630 1016 int cnt, match, status;
18e144d3 1017 unsigned long flags;
e315cd28 1018 struct qla_hw_data *ha = vha->hw;
73208dfd 1019 struct req_que *req;
4d78c973 1020 srb_t *sp;
9ba56b95 1021 struct scsi_cmnd *cmd;
1da177e4 1022
523ec773 1023 status = QLA_SUCCESS;
17d98630 1024
e315cd28 1025 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1026 req = vha->req;
17d98630 1027 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1028 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1029 sp = req->outstanding_cmds[cnt];
1030 if (!sp)
523ec773 1031 continue;
9ba56b95 1032 if (sp->type != SRB_SCSI_CMD)
cf53b069 1033 continue;
17d98630
AC		 1034 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1035 continue;
1036 match = 0;
9ba56b95 1037 cmd = GET_CMD_SP(sp);
17d98630
AC		 1038 switch (type) {
1039 case WAIT_HOST:
1040 match = 1;
1041 break;
1042 case WAIT_TARGET:
9ba56b95 1043 match = cmd->device->id == t;
17d98630
AC		 1044 break;
1045 case WAIT_LUN:
9ba56b95
GM		 1046 match = (cmd->device->id == t &&
1047 cmd->device->lun == l);
17d98630 1048 break;
73208dfd 1049 }
17d98630
AC		 1050 if (!match)
1051 continue;
1052
1053 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1054 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1055 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1056 }
e315cd28 1057 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1058
1059 return status;
1da177e4
LT		 1060}
1061
523ec773
AV		 1062static char *reset_errors[] = {
1063 "HBA not online",
1064 "HBA not ready",
1065 "Task management failed",
1066 "Waiting for command completions",
1067};
1da177e4 1068
e5f82ab8 1069static int
523ec773 1070__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1071 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1072{
e315cd28 1073 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1074 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1075 int err;
1da177e4 1076
7c3df132 1077 if (!fcport) {
523ec773 1078 return FAILED;
7c3df132 1079 }
1da177e4 1080
4e98d3b8
AV		 1081 err = fc_block_scsi_eh(cmd);
1082 if (err != 0)
1083 return err;
1084
7c3df132 1085 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1086 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1087 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1088
523ec773 1089 err = 0;
7c3df132
SK		 1090 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1091 ql_log(ql_log_warn, vha, 0x800a,
1092 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1093 goto eh_reset_failed;
7c3df132 1094 }
523ec773 1095 err = 2;
2afa19a9 1096 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1097 != QLA_SUCCESS) {
1098 ql_log(ql_log_warn, vha, 0x800c,
1099 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1100 goto eh_reset_failed;
7c3df132 1101 }
523ec773 1102 err = 3;
e315cd28 1103 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1104 cmd->device->lun, type) != QLA_SUCCESS) {
1105 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1106 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1107 goto eh_reset_failed;
7c3df132 1108 }
523ec773 1109
7c3df132 1110 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1111 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1112 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1113
1114 return SUCCESS;
1115
4d78c973 1116eh_reset_failed:
7c3df132 1117 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1118 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1119 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1120 cmd);
523ec773
AV		 1121 return FAILED;
1122}
1da177e4 1123
523ec773
AV		 1124static int
1125qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1126{
e315cd28
AC		 1127 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1128 struct qla_hw_data *ha = vha->hw;
1da177e4 1129
523ec773
AV		 1130 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1131 ha->isp_ops->lun_reset);
1da177e4
LT		 1132}
1133
1da177e4 1134static int
523ec773 1135qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1136{
e315cd28
AC		 1137 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1138 struct qla_hw_data *ha = vha->hw;
1da177e4 1139
523ec773
AV		 1140 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1141 ha->isp_ops->target_reset);
1da177e4
LT		 1142}
1143
1da177e4
LT		 1144/**************************************************************************
1145* qla2xxx_eh_bus_reset
1146*
1147* Description:
1148* The bus reset function will reset the bus and abort any executing
1149* commands.
1150*
1151* Input:
1152* cmd = Linux SCSI command packet of the command that cause the
1153* bus reset.
1154*
1155* Returns:
1156* SUCCESS/FAILURE (defined as macro in scsi.h).
1157*
1158**************************************************************************/
e5f82ab8 1159static int
1da177e4
LT		 1160qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1161{
e315cd28 1162 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1163 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1164 int ret = FAILED;
9cb78c16
HR		 1165 unsigned int id;
1166 uint64_t lun;
f4f051eb 1167
f4f051eb 1168 id = cmd->device->id;
1169 lun = cmd->device->lun;
1da177e4 1170
7c3df132 1171 if (!fcport) {
f4f051eb 1172 return ret;
7c3df132 1173 }
1da177e4 1174
4e98d3b8
AV		 1175 ret = fc_block_scsi_eh(cmd);
1176 if (ret != 0)
1177 return ret;
1178 ret = FAILED;
1179
7c3df132 1180 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1181 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1182
e315cd28 1183 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1184 ql_log(ql_log_fatal, vha, 0x8013,
1185 "Wait for hba online failed board disabled.\n");
f4f051eb 1186 goto eh_bus_reset_done;
1da177e4
LT		 1187 }
1188
ad537689
SK		 1189 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1190 ret = SUCCESS;
1191
f4f051eb 1192 if (ret == FAILED)
1193 goto eh_bus_reset_done;
1da177e4 1194
9a41a62b 1195 /* Flush outstanding commands. */
4d78c973 1196 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1197 QLA_SUCCESS) {
1198 ql_log(ql_log_warn, vha, 0x8014,
1199 "Wait for pending commands failed.\n");
9a41a62b 1200 ret = FAILED;
7c3df132 1201 }
1da177e4 1202
f4f051eb 1203eh_bus_reset_done:
7c3df132 1204 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1205 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1206 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1207
f4f051eb 1208 return ret;
1da177e4
LT		 1209}
1210
1211/**************************************************************************
1212* qla2xxx_eh_host_reset
1213*
1214* Description:
1215* The reset function will reset the Adapter.
1216*
1217* Input:
1218* cmd = Linux SCSI command packet of the command that cause the
1219* adapter reset.
1220*
1221* Returns:
1222* Either SUCCESS or FAILED.
1223*
1224* Note:
1225**************************************************************************/
e5f82ab8 1226static int
1da177e4
LT		 1227qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1228{
e315cd28 1229 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1230 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1231 int ret = FAILED;
9cb78c16
HR		 1232 unsigned int id;
1233 uint64_t lun;
e315cd28 1234 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1235
f4f051eb 1236 id = cmd->device->id;
1237 lun = cmd->device->lun;
f4f051eb 1238
7c3df132 1239 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1240 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1241
63ee7072
CD		 1242 /*
1243 * No point in issuing another reset if one is active. Also do not
1244 * attempt a reset if we are updating flash.
1245 */
1246 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1247 goto eh_host_reset_lock;
1da177e4 1248
e315cd28
AC		 1249 if (vha != base_vha) {
1250 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1251 goto eh_host_reset_lock;
e315cd28 1252 } else {
7ec0effd 1253 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1254 if (!qla82xx_fcoe_ctx_reset(vha)) {
1255 /* Ctx reset success */
1256 ret = SUCCESS;
1257 goto eh_host_reset_lock;
1258 }
1259 /* fall thru if ctx reset failed */
1260 }
68ca949c
AC		 1261 if (ha->wq)
1262 flush_workqueue(ha->wq);
1263
e315cd28 1264 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1265 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1266 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1267 /* failed. schedule dpc to try */
1268 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1269
7c3df132
SK		 1270 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1271 ql_log(ql_log_warn, vha, 0x802a,
1272 "wait for hba online failed.\n");
e315cd28 1273 goto eh_host_reset_lock;
7c3df132 1274 }
e315cd28
AC		 1275 }
1276 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1277 }
1da177e4 1278
e315cd28 1279 /* Waiting for command to be returned to OS.*/
4d78c973 1280 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1281 QLA_SUCCESS)
f4f051eb 1282 ret = SUCCESS;
1da177e4 1283
f4f051eb 1284eh_host_reset_lock:
cfb0919c 1285 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1286 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1287 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1288
f4f051eb 1289 return ret;
1290}
1da177e4
LT		 1291
1292/*
1293* qla2x00_loop_reset
1294* Issue loop reset.
1295*
1296* Input:
1297* ha = adapter block pointer.
1298*
1299* Returns:
1300* 0 = success
1301*/
a4722cf2 1302int
e315cd28 1303qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1304{
0c8c39af 1305 int ret;
bdf79621 1306 struct fc_port *fcport;
e315cd28 1307 struct qla_hw_data *ha = vha->hw;
1da177e4 1308
5854771e
AB		 1309 if (IS_QLAFX00(ha)) {
1310 return qlafx00_loop_reset(vha);
1311 }
1312
f4c496c1 1313 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1314 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1315 if (fcport->port_type != FCT_TARGET)
1316 continue;
1317
1318 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1319 if (ret != QLA_SUCCESS) {
7c3df132 1320 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1321 "Bus Reset failed: Reset=%d "
7c3df132 1322 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1323 }
1324 }
1325 }
1326
8ae6d9c7 1327
6246b8a1 1328 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1329 atomic_set(&vha->loop_state, LOOP_DOWN);
1330 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1331 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1332 ret = qla2x00_full_login_lip(vha);
0c8c39af 1333 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1334 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1335 "full_login_lip=%d.\n", ret);
749af3d5 1336 }
0c8c39af
AV		 1337 }
1338
0d6e61bc 1339 if (ha->flags.enable_lip_reset) {
e315cd28 1340 ret = qla2x00_lip_reset(vha);
ad537689 1341 if (ret != QLA_SUCCESS)
7c3df132
SK		 1342 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1343 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1344 }
1345
1da177e4 1346 /* Issue marker command only when we are going to start the I/O */
e315cd28 1347 vha->marker_needed = 1;
1da177e4 1348
0c8c39af 1349 return QLA_SUCCESS;
1da177e4
LT		 1350}
1351
df4bf0bb 1352void
e315cd28 1353qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1354{
73208dfd 1355 int que, cnt;
df4bf0bb
AV		 1356 unsigned long flags;
1357 srb_t *sp;
e315cd28 1358 struct qla_hw_data *ha = vha->hw;
73208dfd 1359 struct req_que *req;
df4bf0bb 1360
c0cb4496
AE		 1361 qlt_host_reset_handler(ha);
1362
df4bf0bb 1363 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1364 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1365 req = ha->req_q_map[que];
73208dfd
AC		 1366 if (!req)
1367 continue;
8d93f550
CD		 1368 if (!req->outstanding_cmds)
1369 continue;
1370 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1371 sp = req->outstanding_cmds[cnt];
e612d465 1372 if (sp) {
73208dfd 1373 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1374 sp->done(vha, sp, res);
73208dfd 1375 }
df4bf0bb
AV		 1376 }
1377 }
1378 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1379}
1380
f4f051eb 1381static int
1382qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1383{
bdf79621 1384 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1385
19a7b4ae 1386 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1387 return -ENXIO;
bdf79621 1388
19a7b4ae 1389 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1390
f4f051eb 1391 return 0;
1392}
1da177e4 1393
f4f051eb 1394static int
1395qla2xxx_slave_configure(struct scsi_device *sdev)
1396{
e315cd28 1397 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1398 struct req_que *req = vha->req;
8482e118 1399
9e522cd8
AE		 1400 if (IS_T10_PI_CAPABLE(vha->hw))
1401 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1402
db5ed4df 1403 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1404 return 0;
1405}
1da177e4 1406
f4f051eb 1407static void
1408qla2xxx_slave_destroy(struct scsi_device *sdev)
1409{
1410 sdev->hostdata = NULL;
1da177e4
LT		 1411}
1412
1413/**
1414 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1415 * @ha: HA context
1416 *
1417 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1418 * supported addressing method.
1419 */
1420static void
53303c42 1421qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1422{
7524f9b9 1423 /* Assume a 32bit DMA mask. */
1da177e4 1424 ha->flags.enable_64bit_addressing = 0;
1da177e4 1425
6a35528a 1426 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1427 /* Any upper-dword bits set? */
1428 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1429 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1430 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1431 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1432 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1433 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1434 return;
1da177e4 1435 }
1da177e4 1436 }
7524f9b9 1437
284901a9
YH		 1438 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1439 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1440}
1441
fd34f556 1442static void
e315cd28 1443qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1444{
1445 unsigned long flags = 0;
1446 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1447
1448 spin_lock_irqsave(&ha->hardware_lock, flags);
1449 ha->interrupts_on = 1;
1450 /* enable risc and host interrupts */
1451 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1452 RD_REG_WORD(&reg->ictrl);
1453 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1454
1455}
1456
1457static void
e315cd28 1458qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1459{
1460 unsigned long flags = 0;
1461 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1462
1463 spin_lock_irqsave(&ha->hardware_lock, flags);
1464 ha->interrupts_on = 0;
1465 /* disable risc and host interrupts */
1466 WRT_REG_WORD(&reg->ictrl, 0);
1467 RD_REG_WORD(&reg->ictrl);
1468 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1469}
1470
1471static void
e315cd28 1472qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1473{
1474 unsigned long flags = 0;
1475 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1476
1477 spin_lock_irqsave(&ha->hardware_lock, flags);
1478 ha->interrupts_on = 1;
1479 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1480 RD_REG_DWORD(&reg->ictrl);
1481 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1482}
1483
1484static void
e315cd28 1485qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1486{
1487 unsigned long flags = 0;
1488 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1489
124f85e6
AV		 1490 if (IS_NOPOLLING_TYPE(ha))
1491 return;
fd34f556
AV		 1492 spin_lock_irqsave(&ha->hardware_lock, flags);
1493 ha->interrupts_on = 0;
1494 WRT_REG_DWORD(&reg->ictrl, 0);
1495 RD_REG_DWORD(&reg->ictrl);
1496 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1497}
1498
706f457d
GM		 1499static int
1500qla2x00_iospace_config(struct qla_hw_data *ha)
1501{
1502 resource_size_t pio;
1503 uint16_t msix;
1504 int cpus;
1505
706f457d
GM		 1506 if (pci_request_selected_regions(ha->pdev, ha->bars,
1507 QLA2XXX_DRIVER_NAME)) {
1508 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1509 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1510 pci_name(ha->pdev));
1511 goto iospace_error_exit;
1512 }
1513 if (!(ha->bars & 1))
1514 goto skip_pio;
1515
1516 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1517 pio = pci_resource_start(ha->pdev, 0);
1518 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1519 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1520 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1521 "Invalid pci I/O region size (%s).\n",
1522 pci_name(ha->pdev));
1523 pio = 0;
1524 }
1525 } else {
1526 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1527 "Region #0 no a PIO resource (%s).\n",
1528 pci_name(ha->pdev));
1529 pio = 0;
1530 }
1531 ha->pio_address = pio;
1532 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1533 "PIO address=%llu.\n",
1534 (unsigned long long)ha->pio_address);
1535
1536skip_pio:
1537 /* Use MMIO operations for all accesses. */
1538 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1539 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1540 "Region #1 not an MMIO resource (%s), aborting.\n",
1541 pci_name(ha->pdev));
1542 goto iospace_error_exit;
1543 }
1544 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1545 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1546 "Invalid PCI mem region size (%s), aborting.\n",
1547 pci_name(ha->pdev));
1548 goto iospace_error_exit;
1549 }
1550
1551 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1552 if (!ha->iobase) {
1553 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1554 "Cannot remap MMIO (%s), aborting.\n",
1555 pci_name(ha->pdev));
1556 goto iospace_error_exit;
1557 }
1558
1559 /* Determine queue resources */
1560 ha->max_req_queues = ha->max_rsp_queues = 1;
1561 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1562 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1563 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1564 goto mqiobase_exit;
1565
1566 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1567 pci_resource_len(ha->pdev, 3));
1568 if (ha->mqiobase) {
1569 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1570 "MQIO Base=%p.\n", ha->mqiobase);
1571 /* Read MSIX vector size of the board */
1572 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1573 ha->msix_count = msix;
1574 /* Max queues are bounded by available msix vectors */
1575 /* queue 0 uses two msix vectors */
1576 if (ql2xmultique_tag) {
1577 cpus = num_online_cpus();
1578 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1579 (cpus + 1) : (ha->msix_count - 1);
1580 ha->max_req_queues = 2;
1581 } else if (ql2xmaxqueues > 1) {
1582 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1583 QLA_MQ_SIZE : ql2xmaxqueues;
1584 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1585 "QoS mode set, max no of request queues:%d.\n",
1586 ha->max_req_queues);
1587 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1588 "QoS mode set, max no of request queues:%d.\n",
1589 ha->max_req_queues);
1590 }
1591 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1592 "MSI-X vector count: %d.\n", msix);
1593 } else
1594 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1595 "BAR 3 not enabled.\n");
1596
1597mqiobase_exit:
1598 ha->msix_count = ha->max_rsp_queues + 1;
1599 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1600 "MSIX Count:%d.\n", ha->msix_count);
1601 return (0);
1602
1603iospace_error_exit:
1604 return (-ENOMEM);
1605}
1606
1607
6246b8a1
GM		 1608static int
1609qla83xx_iospace_config(struct qla_hw_data *ha)
1610{
1611 uint16_t msix;
1612 int cpus;
1613
1614 if (pci_request_selected_regions(ha->pdev, ha->bars,
1615 QLA2XXX_DRIVER_NAME)) {
1616 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1617 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1618 pci_name(ha->pdev));
1619
1620 goto iospace_error_exit;
1621 }
1622
1623 /* Use MMIO operations for all accesses. */
1624 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1625 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1626 "Invalid pci I/O region size (%s).\n",
1627 pci_name(ha->pdev));
1628 goto iospace_error_exit;
1629 }
1630 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1631 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1632 "Invalid PCI mem region size (%s), aborting\n",
1633 pci_name(ha->pdev));
1634 goto iospace_error_exit;
1635 }
1636
1637 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1638 if (!ha->iobase) {
1639 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1640 "Cannot remap MMIO (%s), aborting.\n",
1641 pci_name(ha->pdev));
1642 goto iospace_error_exit;
1643 }
1644
1645 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1646 /* 83XX 26XX always use MQ type access for queues
1647 * - mbar 2, a.k.a region 4 */
1648 ha->max_req_queues = ha->max_rsp_queues = 1;
1649 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1650 pci_resource_len(ha->pdev, 4));
1651
1652 if (!ha->mqiobase) {
1653 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1654 "BAR2/region4 not enabled\n");
1655 goto mqiobase_exit;
1656 }
1657
1658 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1659 pci_resource_len(ha->pdev, 2));
1660 if (ha->msixbase) {
1661 /* Read MSIX vector size of the board */
1662 pci_read_config_word(ha->pdev,
1663 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1664 ha->msix_count = msix;
1665 /* Max queues are bounded by available msix vectors */
1666 /* queue 0 uses two msix vectors */
1667 if (ql2xmultique_tag) {
1668 cpus = num_online_cpus();
1669 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1670 (cpus + 1) : (ha->msix_count - 1);
1671 ha->max_req_queues = 2;
1672 } else if (ql2xmaxqueues > 1) {
1673 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1674 QLA_MQ_SIZE : ql2xmaxqueues;
1675 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1676 "QoS mode set, max no of request queues:%d.\n",
1677 ha->max_req_queues);
1678 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1679 "QoS mode set, max no of request queues:%d.\n",
1680 ha->max_req_queues);
1681 }
1682 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1683 "MSI-X vector count: %d.\n", msix);
1684 } else
1685 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1686 "BAR 1 not enabled.\n");
1687
1688mqiobase_exit:
1689 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1690
1691 qlt_83xx_iospace_config(ha);
1692
6246b8a1
GM		 1693 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1694 "MSIX Count:%d.\n", ha->msix_count);
1695 return 0;
1696
1697iospace_error_exit:
1698 return -ENOMEM;
1699}
1700
fd34f556
AV		 1701static struct isp_operations qla2100_isp_ops = {
1702 .pci_config = qla2100_pci_config,
1703 .reset_chip = qla2x00_reset_chip,
1704 .chip_diag = qla2x00_chip_diag,
1705 .config_rings = qla2x00_config_rings,
1706 .reset_adapter = qla2x00_reset_adapter,
1707 .nvram_config = qla2x00_nvram_config,
1708 .update_fw_options = qla2x00_update_fw_options,
1709 .load_risc = qla2x00_load_risc,
1710 .pci_info_str = qla2x00_pci_info_str,
1711 .fw_version_str = qla2x00_fw_version_str,
1712 .intr_handler = qla2100_intr_handler,
1713 .enable_intrs = qla2x00_enable_intrs,
1714 .disable_intrs = qla2x00_disable_intrs,
1715 .abort_command = qla2x00_abort_command,
523ec773
AV		 1716 .target_reset = qla2x00_abort_target,
1717 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1718 .fabric_login = qla2x00_login_fabric,
1719 .fabric_logout = qla2x00_fabric_logout,
1720 .calc_req_entries = qla2x00_calc_iocbs_32,
1721 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1722 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1723 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1724 .read_nvram = qla2x00_read_nvram_data,
1725 .write_nvram = qla2x00_write_nvram_data,
1726 .fw_dump = qla2100_fw_dump,
1727 .beacon_on = NULL,
1728 .beacon_off = NULL,
1729 .beacon_blink = NULL,
1730 .read_optrom = qla2x00_read_optrom_data,
1731 .write_optrom = qla2x00_write_optrom_data,
1732 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1733 .start_scsi = qla2x00_start_scsi,
a9083016 1734 .abort_isp = qla2x00_abort_isp,
706f457d 1735 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1736 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1737};
1738
1739static struct isp_operations qla2300_isp_ops = {
1740 .pci_config = qla2300_pci_config,
1741 .reset_chip = qla2x00_reset_chip,
1742 .chip_diag = qla2x00_chip_diag,
1743 .config_rings = qla2x00_config_rings,
1744 .reset_adapter = qla2x00_reset_adapter,
1745 .nvram_config = qla2x00_nvram_config,
1746 .update_fw_options = qla2x00_update_fw_options,
1747 .load_risc = qla2x00_load_risc,
1748 .pci_info_str = qla2x00_pci_info_str,
1749 .fw_version_str = qla2x00_fw_version_str,
1750 .intr_handler = qla2300_intr_handler,
1751 .enable_intrs = qla2x00_enable_intrs,
1752 .disable_intrs = qla2x00_disable_intrs,
1753 .abort_command = qla2x00_abort_command,
523ec773
AV		 1754 .target_reset = qla2x00_abort_target,
1755 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1756 .fabric_login = qla2x00_login_fabric,
1757 .fabric_logout = qla2x00_fabric_logout,
1758 .calc_req_entries = qla2x00_calc_iocbs_32,
1759 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1760 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1761 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1762 .read_nvram = qla2x00_read_nvram_data,
1763 .write_nvram = qla2x00_write_nvram_data,
1764 .fw_dump = qla2300_fw_dump,
1765 .beacon_on = qla2x00_beacon_on,
1766 .beacon_off = qla2x00_beacon_off,
1767 .beacon_blink = qla2x00_beacon_blink,
1768 .read_optrom = qla2x00_read_optrom_data,
1769 .write_optrom = qla2x00_write_optrom_data,
1770 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1771 .start_scsi = qla2x00_start_scsi,
a9083016 1772 .abort_isp = qla2x00_abort_isp,
7ec0effd 1773 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1774 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1775};
1776
1777static struct isp_operations qla24xx_isp_ops = {
1778 .pci_config = qla24xx_pci_config,
1779 .reset_chip = qla24xx_reset_chip,
1780 .chip_diag = qla24xx_chip_diag,
1781 .config_rings = qla24xx_config_rings,
1782 .reset_adapter = qla24xx_reset_adapter,
1783 .nvram_config = qla24xx_nvram_config,
1784 .update_fw_options = qla24xx_update_fw_options,
1785 .load_risc = qla24xx_load_risc,
1786 .pci_info_str = qla24xx_pci_info_str,
1787 .fw_version_str = qla24xx_fw_version_str,
1788 .intr_handler = qla24xx_intr_handler,
1789 .enable_intrs = qla24xx_enable_intrs,
1790 .disable_intrs = qla24xx_disable_intrs,
1791 .abort_command = qla24xx_abort_command,
523ec773
AV		 1792 .target_reset = qla24xx_abort_target,
1793 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1794 .fabric_login = qla24xx_login_fabric,
1795 .fabric_logout = qla24xx_fabric_logout,
1796 .calc_req_entries = NULL,
1797 .build_iocbs = NULL,
1798 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1799 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1800 .read_nvram = qla24xx_read_nvram_data,
1801 .write_nvram = qla24xx_write_nvram_data,
1802 .fw_dump = qla24xx_fw_dump,
1803 .beacon_on = qla24xx_beacon_on,
1804 .beacon_off = qla24xx_beacon_off,
1805 .beacon_blink = qla24xx_beacon_blink,
1806 .read_optrom = qla24xx_read_optrom_data,
1807 .write_optrom = qla24xx_write_optrom_data,
1808 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1809 .start_scsi = qla24xx_start_scsi,
a9083016 1810 .abort_isp = qla2x00_abort_isp,
7ec0effd 1811 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1812 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1813};
1814
c3a2f0df
AV		 1815static struct isp_operations qla25xx_isp_ops = {
1816 .pci_config = qla25xx_pci_config,
1817 .reset_chip = qla24xx_reset_chip,
1818 .chip_diag = qla24xx_chip_diag,
1819 .config_rings = qla24xx_config_rings,
1820 .reset_adapter = qla24xx_reset_adapter,
1821 .nvram_config = qla24xx_nvram_config,
1822 .update_fw_options = qla24xx_update_fw_options,
1823 .load_risc = qla24xx_load_risc,
1824 .pci_info_str = qla24xx_pci_info_str,
1825 .fw_version_str = qla24xx_fw_version_str,
1826 .intr_handler = qla24xx_intr_handler,
1827 .enable_intrs = qla24xx_enable_intrs,
1828 .disable_intrs = qla24xx_disable_intrs,
1829 .abort_command = qla24xx_abort_command,
523ec773
AV		 1830 .target_reset = qla24xx_abort_target,
1831 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1832 .fabric_login = qla24xx_login_fabric,
1833 .fabric_logout = qla24xx_fabric_logout,
1834 .calc_req_entries = NULL,
1835 .build_iocbs = NULL,
1836 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1837 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1838 .read_nvram = qla25xx_read_nvram_data,
1839 .write_nvram = qla25xx_write_nvram_data,
1840 .fw_dump = qla25xx_fw_dump,
1841 .beacon_on = qla24xx_beacon_on,
1842 .beacon_off = qla24xx_beacon_off,
1843 .beacon_blink = qla24xx_beacon_blink,
338c9161 1844 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1845 .write_optrom = qla24xx_write_optrom_data,
1846 .get_flash_version = qla24xx_get_flash_version,
bad75002 1847 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1848 .abort_isp = qla2x00_abort_isp,
7ec0effd 1849 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1850 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1851};
1852
3a03eb79
AV		 1853static struct isp_operations qla81xx_isp_ops = {
1854 .pci_config = qla25xx_pci_config,
1855 .reset_chip = qla24xx_reset_chip,
1856 .chip_diag = qla24xx_chip_diag,
1857 .config_rings = qla24xx_config_rings,
1858 .reset_adapter = qla24xx_reset_adapter,
1859 .nvram_config = qla81xx_nvram_config,
1860 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1861 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1862 .pci_info_str = qla24xx_pci_info_str,
1863 .fw_version_str = qla24xx_fw_version_str,
1864 .intr_handler = qla24xx_intr_handler,
1865 .enable_intrs = qla24xx_enable_intrs,
1866 .disable_intrs = qla24xx_disable_intrs,
1867 .abort_command = qla24xx_abort_command,
1868 .target_reset = qla24xx_abort_target,
1869 .lun_reset = qla24xx_lun_reset,
1870 .fabric_login = qla24xx_login_fabric,
1871 .fabric_logout = qla24xx_fabric_logout,
1872 .calc_req_entries = NULL,
1873 .build_iocbs = NULL,
1874 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1875 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1876 .read_nvram = NULL,
1877 .write_nvram = NULL,
3a03eb79
AV		 1878 .fw_dump = qla81xx_fw_dump,
1879 .beacon_on = qla24xx_beacon_on,
1880 .beacon_off = qla24xx_beacon_off,
6246b8a1 1881 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1882 .read_optrom = qla25xx_read_optrom_data,
1883 .write_optrom = qla24xx_write_optrom_data,
1884 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1885 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1886 .abort_isp = qla2x00_abort_isp,
7ec0effd 1887 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1888 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 1889};
1890
1891static struct isp_operations qla82xx_isp_ops = {
1892 .pci_config = qla82xx_pci_config,
1893 .reset_chip = qla82xx_reset_chip,
1894 .chip_diag = qla24xx_chip_diag,
1895 .config_rings = qla82xx_config_rings,
1896 .reset_adapter = qla24xx_reset_adapter,
1897 .nvram_config = qla81xx_nvram_config,
1898 .update_fw_options = qla24xx_update_fw_options,
1899 .load_risc = qla82xx_load_risc,
9d55ca66 1900 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 1901 .fw_version_str = qla24xx_fw_version_str,
1902 .intr_handler = qla82xx_intr_handler,
1903 .enable_intrs = qla82xx_enable_intrs,
1904 .disable_intrs = qla82xx_disable_intrs,
1905 .abort_command = qla24xx_abort_command,
1906 .target_reset = qla24xx_abort_target,
1907 .lun_reset = qla24xx_lun_reset,
1908 .fabric_login = qla24xx_login_fabric,
1909 .fabric_logout = qla24xx_fabric_logout,
1910 .calc_req_entries = NULL,
1911 .build_iocbs = NULL,
1912 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1913 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1914 .read_nvram = qla24xx_read_nvram_data,
1915 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 1916 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 1917 .beacon_on = qla82xx_beacon_on,
1918 .beacon_off = qla82xx_beacon_off,
1919 .beacon_blink = NULL,
a9083016
GM		 1920 .read_optrom = qla82xx_read_optrom_data,
1921 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 1922 .get_flash_version = qla82xx_get_flash_version,
a9083016
GM		 1923 .start_scsi = qla82xx_start_scsi,
1924 .abort_isp = qla82xx_abort_isp,
706f457d 1925 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 1926 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 1927};
1928
7ec0effd
AD		 1929static struct isp_operations qla8044_isp_ops = {
1930 .pci_config = qla82xx_pci_config,
1931 .reset_chip = qla82xx_reset_chip,
1932 .chip_diag = qla24xx_chip_diag,
1933 .config_rings = qla82xx_config_rings,
1934 .reset_adapter = qla24xx_reset_adapter,
1935 .nvram_config = qla81xx_nvram_config,
1936 .update_fw_options = qla24xx_update_fw_options,
1937 .load_risc = qla82xx_load_risc,
1938 .pci_info_str = qla24xx_pci_info_str,
1939 .fw_version_str = qla24xx_fw_version_str,
1940 .intr_handler = qla8044_intr_handler,
1941 .enable_intrs = qla82xx_enable_intrs,
1942 .disable_intrs = qla82xx_disable_intrs,
1943 .abort_command = qla24xx_abort_command,
1944 .target_reset = qla24xx_abort_target,
1945 .lun_reset = qla24xx_lun_reset,
1946 .fabric_login = qla24xx_login_fabric,
1947 .fabric_logout = qla24xx_fabric_logout,
1948 .calc_req_entries = NULL,
1949 .build_iocbs = NULL,
1950 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1951 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1952 .read_nvram = NULL,
1953 .write_nvram = NULL,
a1b23c5a 1954 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 1955 .beacon_on = qla82xx_beacon_on,
1956 .beacon_off = qla82xx_beacon_off,
1957 .beacon_blink = NULL,
888e639d 1958 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 1959 .write_optrom = qla8044_write_optrom_data,
1960 .get_flash_version = qla82xx_get_flash_version,
1961 .start_scsi = qla82xx_start_scsi,
1962 .abort_isp = qla8044_abort_isp,
1963 .iospace_config = qla82xx_iospace_config,
1964 .initialize_adapter = qla2x00_initialize_adapter,
1965};
1966
6246b8a1
GM		 1967static struct isp_operations qla83xx_isp_ops = {
1968 .pci_config = qla25xx_pci_config,
1969 .reset_chip = qla24xx_reset_chip,
1970 .chip_diag = qla24xx_chip_diag,
1971 .config_rings = qla24xx_config_rings,
1972 .reset_adapter = qla24xx_reset_adapter,
1973 .nvram_config = qla81xx_nvram_config,
1974 .update_fw_options = qla81xx_update_fw_options,
1975 .load_risc = qla81xx_load_risc,
1976 .pci_info_str = qla24xx_pci_info_str,
1977 .fw_version_str = qla24xx_fw_version_str,
1978 .intr_handler = qla24xx_intr_handler,
1979 .enable_intrs = qla24xx_enable_intrs,
1980 .disable_intrs = qla24xx_disable_intrs,
1981 .abort_command = qla24xx_abort_command,
1982 .target_reset = qla24xx_abort_target,
1983 .lun_reset = qla24xx_lun_reset,
1984 .fabric_login = qla24xx_login_fabric,
1985 .fabric_logout = qla24xx_fabric_logout,
1986 .calc_req_entries = NULL,
1987 .build_iocbs = NULL,
1988 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1989 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1990 .read_nvram = NULL,
1991 .write_nvram = NULL,
1992 .fw_dump = qla83xx_fw_dump,
1993 .beacon_on = qla24xx_beacon_on,
1994 .beacon_off = qla24xx_beacon_off,
1995 .beacon_blink = qla83xx_beacon_blink,
1996 .read_optrom = qla25xx_read_optrom_data,
1997 .write_optrom = qla24xx_write_optrom_data,
1998 .get_flash_version = qla24xx_get_flash_version,
1999 .start_scsi = qla24xx_dif_start_scsi,
2000 .abort_isp = qla2x00_abort_isp,
2001 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2002 .initialize_adapter = qla2x00_initialize_adapter,
2003};
2004
2005static struct isp_operations qlafx00_isp_ops = {
2006 .pci_config = qlafx00_pci_config,
2007 .reset_chip = qlafx00_soft_reset,
2008 .chip_diag = qlafx00_chip_diag,
2009 .config_rings = qlafx00_config_rings,
2010 .reset_adapter = qlafx00_soft_reset,
2011 .nvram_config = NULL,
2012 .update_fw_options = NULL,
2013 .load_risc = NULL,
2014 .pci_info_str = qlafx00_pci_info_str,
2015 .fw_version_str = qlafx00_fw_version_str,
2016 .intr_handler = qlafx00_intr_handler,
2017 .enable_intrs = qlafx00_enable_intrs,
2018 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2019 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2020 .target_reset = qlafx00_abort_target,
2021 .lun_reset = qlafx00_lun_reset,
2022 .fabric_login = NULL,
2023 .fabric_logout = NULL,
2024 .calc_req_entries = NULL,
2025 .build_iocbs = NULL,
2026 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2027 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2028 .read_nvram = qla24xx_read_nvram_data,
2029 .write_nvram = qla24xx_write_nvram_data,
2030 .fw_dump = NULL,
2031 .beacon_on = qla24xx_beacon_on,
2032 .beacon_off = qla24xx_beacon_off,
2033 .beacon_blink = NULL,
2034 .read_optrom = qla24xx_read_optrom_data,
2035 .write_optrom = qla24xx_write_optrom_data,
2036 .get_flash_version = qla24xx_get_flash_version,
2037 .start_scsi = qlafx00_start_scsi,
2038 .abort_isp = qlafx00_abort_isp,
2039 .iospace_config = qlafx00_iospace_config,
2040 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2041};
2042
f73cb695
CD		 2043static struct isp_operations qla27xx_isp_ops = {
2044 .pci_config = qla25xx_pci_config,
2045 .reset_chip = qla24xx_reset_chip,
2046 .chip_diag = qla24xx_chip_diag,
2047 .config_rings = qla24xx_config_rings,
2048 .reset_adapter = qla24xx_reset_adapter,
2049 .nvram_config = qla81xx_nvram_config,
2050 .update_fw_options = qla81xx_update_fw_options,
2051 .load_risc = qla81xx_load_risc,
2052 .pci_info_str = qla24xx_pci_info_str,
2053 .fw_version_str = qla24xx_fw_version_str,
2054 .intr_handler = qla24xx_intr_handler,
2055 .enable_intrs = qla24xx_enable_intrs,
2056 .disable_intrs = qla24xx_disable_intrs,
2057 .abort_command = qla24xx_abort_command,
2058 .target_reset = qla24xx_abort_target,
2059 .lun_reset = qla24xx_lun_reset,
2060 .fabric_login = qla24xx_login_fabric,
2061 .fabric_logout = qla24xx_fabric_logout,
2062 .calc_req_entries = NULL,
2063 .build_iocbs = NULL,
2064 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2065 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2066 .read_nvram = NULL,
2067 .write_nvram = NULL,
2068 .fw_dump = qla27xx_fwdump,
2069 .beacon_on = qla24xx_beacon_on,
2070 .beacon_off = qla24xx_beacon_off,
2071 .beacon_blink = qla83xx_beacon_blink,
2072 .read_optrom = qla25xx_read_optrom_data,
2073 .write_optrom = qla24xx_write_optrom_data,
2074 .get_flash_version = qla24xx_get_flash_version,
2075 .start_scsi = qla24xx_dif_start_scsi,
2076 .abort_isp = qla2x00_abort_isp,
2077 .iospace_config = qla83xx_iospace_config,
2078 .initialize_adapter = qla2x00_initialize_adapter,
2079};
2080
ea5b6382 2081static inline void
e315cd28 2082qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2083{
2084 ha->device_type = DT_EXTENDED_IDS;
2085 switch (ha->pdev->device) {
2086 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2087 ha->device_type |= DT_ISP2100;
2088 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2089 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2090 break;
2091 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2092 ha->device_type |= DT_ISP2200;
2093 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2094 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2095 break;
2096 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2097 ha->device_type |= DT_ISP2300;
4a59f71d 2098 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2099 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2100 break;
2101 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2102 ha->device_type |= DT_ISP2312;
4a59f71d 2103 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2104 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2105 break;
2106 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2107 ha->device_type |= DT_ISP2322;
4a59f71d 2108 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2109 if (ha->pdev->subsystem_vendor == 0x1028 &&
2110 ha->pdev->subsystem_device == 0x0170)
2111 ha->device_type |= DT_OEM_001;
441d1072 2112 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2113 break;
2114 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2115 ha->device_type |= DT_ISP6312;
441d1072 2116 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2117 break;
2118 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2119 ha->device_type |= DT_ISP6322;
441d1072 2120 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2121 break;
2122 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2123 ha->device_type |= DT_ISP2422;
4a59f71d 2124 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2125 ha->device_type |= DT_FWI2;
c76f2c01 2126 ha->device_type |= DT_IIDMA;
441d1072 2127 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2128 break;
2129 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2130 ha->device_type |= DT_ISP2432;
4a59f71d 2131 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2132 ha->device_type |= DT_FWI2;
c76f2c01 2133 ha->device_type |= DT_IIDMA;
441d1072 2134 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2135 break;
4d4df193
HK		 2136 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2137 ha->device_type |= DT_ISP8432;
2138 ha->device_type |= DT_ZIO_SUPPORTED;
2139 ha->device_type |= DT_FWI2;
2140 ha->device_type |= DT_IIDMA;
2141 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2142 break;
044cc6c8 2143 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2144 ha->device_type |= DT_ISP5422;
e428924c 2145 ha->device_type |= DT_FWI2;
441d1072 2146 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2147 break;
044cc6c8 2148 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2149 ha->device_type |= DT_ISP5432;
e428924c 2150 ha->device_type |= DT_FWI2;
441d1072 2151 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2152 break;
c3a2f0df
AV		 2153 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2154 ha->device_type |= DT_ISP2532;
2155 ha->device_type |= DT_ZIO_SUPPORTED;
2156 ha->device_type |= DT_FWI2;
2157 ha->device_type |= DT_IIDMA;
441d1072 2158 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2159 break;
3a03eb79
AV		 2160 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2161 ha->device_type |= DT_ISP8001;
2162 ha->device_type |= DT_ZIO_SUPPORTED;
2163 ha->device_type |= DT_FWI2;
2164 ha->device_type |= DT_IIDMA;
2165 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2166 break;
a9083016
GM		 2167 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2168 ha->device_type |= DT_ISP8021;
2169 ha->device_type |= DT_ZIO_SUPPORTED;
2170 ha->device_type |= DT_FWI2;
2171 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2172 /* Initialize 82XX ISP flags */
2173 qla82xx_init_flags(ha);
2174 break;
7ec0effd
AD		 2175 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2176 ha->device_type |= DT_ISP8044;
2177 ha->device_type |= DT_ZIO_SUPPORTED;
2178 ha->device_type |= DT_FWI2;
2179 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2180 /* Initialize 82XX ISP flags */
2181 qla82xx_init_flags(ha);
2182 break;
6246b8a1
GM		 2183 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2184 ha->device_type |= DT_ISP2031;
2185 ha->device_type |= DT_ZIO_SUPPORTED;
2186 ha->device_type |= DT_FWI2;
2187 ha->device_type |= DT_IIDMA;
2188 ha->device_type |= DT_T10_PI;
2189 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2190 break;
2191 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2192 ha->device_type |= DT_ISP8031;
2193 ha->device_type |= DT_ZIO_SUPPORTED;
2194 ha->device_type |= DT_FWI2;
2195 ha->device_type |= DT_IIDMA;
2196 ha->device_type |= DT_T10_PI;
2197 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2198 break;
8ae6d9c7
GM		 2199 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2200 ha->device_type |= DT_ISPFX00;
2201 break;
f73cb695
CD		 2202 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2203 ha->device_type |= DT_ISP2071;
2204 ha->device_type |= DT_ZIO_SUPPORTED;
2205 ha->device_type |= DT_FWI2;
2206 ha->device_type |= DT_IIDMA;
2207 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2208 break;
2c5bbbb2
JC		 2209 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2210 ha->device_type |= DT_ISP2271;
2211 ha->device_type |= DT_ZIO_SUPPORTED;
2212 ha->device_type |= DT_FWI2;
2213 ha->device_type |= DT_IIDMA;
2214 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2215 break;
2b48992f
SC		 2216 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2217 ha->device_type |= DT_ISP2261;
2218 ha->device_type |= DT_ZIO_SUPPORTED;
2219 ha->device_type |= DT_FWI2;
2220 ha->device_type |= DT_IIDMA;
2221 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2222 break;
ea5b6382 2223 }
e5b68a61 2224
a9083016 2225 if (IS_QLA82XX(ha))
43a9c38b 2226 ha->port_no = ha->portnum & 1;
f73cb695 2227 else {
a9083016
GM		 2228 /* Get adapter physical port no from interrupt pin register. */
2229 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2230 if (IS_QLA27XX(ha))
2231 ha->port_no--;
2232 else
2233 ha->port_no = !(ha->port_no & 1);
2234 }
a9083016 2235
7c3df132 2236 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2237 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2238 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2239}
2240
1e99e33a
AV		 2241static void
2242qla2xxx_scan_start(struct Scsi_Host *shost)
2243{
e315cd28 2244 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2245
cbc8eb67
AV		 2246 if (vha->hw->flags.running_gold_fw)
2247 return;
2248
e315cd28
AC		 2249 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2250 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2251 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2252 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2253}
2254
2255static int
2256qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2257{
e315cd28 2258 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2259
e315cd28 2260 if (!vha->host)
1e99e33a 2261 return 1;
e315cd28 2262 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2263 return 1;
2264
e315cd28 2265 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2266}
2267
1da177e4
LT		 2268/*
2269 * PCI driver interface
2270 */
6f039790 2271static int
7ee61397 2272qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2273{
a1541d5a 2274 int ret = -ENODEV;
1da177e4 2275 struct Scsi_Host *host;
e315cd28
AC		 2276 scsi_qla_host_t *base_vha = NULL;
2277 struct qla_hw_data *ha;
29856e28 2278 char pci_info[30];
7d613ac6 2279 char fw_str[30], wq_name[30];
5433383e 2280 struct scsi_host_template *sht;
642ef983 2281 int bars, mem_only = 0;
e315cd28 2282 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2283 struct req_que *req = NULL;
2284 struct rsp_que *rsp = NULL;
285d0321 2285 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2286 sht = &qla2xxx_driver_template;
5433383e 2287 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2288 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2289 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2290 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2291 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2292 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2293 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2294 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2295 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2296 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2297 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2298 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2299 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2300 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2301 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2302 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2303 mem_only = 1;
7c3df132
SK		 2304 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2305 "Mem only adapter.\n");
285d0321 2306 }
7c3df132
SK		 2307 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2308 "Bars=%d.\n", bars);
285d0321 2309
09483916
BH		 2310 if (mem_only) {
2311 if (pci_enable_device_mem(pdev))
2312 goto probe_out;
2313 } else {
2314 if (pci_enable_device(pdev))
2315 goto probe_out;
2316 }
285d0321 2317
0927678f
JB		 2318 /* This may fail but that's ok */
2319 pci_enable_pcie_error_reporting(pdev);
285d0321 2320
e315cd28
AC		 2321 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2322 if (!ha) {
7c3df132
SK		 2323 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2324 "Unable to allocate memory for ha.\n");
e315cd28 2325 goto probe_out;
1da177e4 2326 }
7c3df132
SK		 2327 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2328 "Memory allocated for ha=%p.\n", ha);
e315cd28 2329 ha->pdev = pdev;
2d70c103 2330 ha->tgt.enable_class_2 = ql2xenableclass2;
33e79977
QT		 2331 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2332 spin_lock_init(&ha->tgt.q_full_lock);
1da177e4
LT		 2333
2334 /* Clear our data area */
285d0321 2335 ha->bars = bars;
09483916 2336 ha->mem_only = mem_only;
df4bf0bb 2337 spin_lock_init(&ha->hardware_lock);
339aa70e 2338 spin_lock_init(&ha->vport_slock);
a9b6f722 2339 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2340 mutex_init(&ha->optrom_mutex);
1da177e4 2341
ea5b6382 2342 /* Set ISP-type information. */
2343 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2344
2345 /* Set EEH reset type to fundamental if required by hba */
95676112 2346 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2347 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2348 pdev->needs_freset = 1;
ca79cf66 2349
cba1e47f
CD		 2350 ha->prev_topology = 0;
2351 ha->init_cb_size = sizeof(init_cb_t);
2352 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2353 ha->optrom_size = OPTROM_SIZE_2300;
2354
abbd8870 2355 /* Assign ISP specific operations. */
1da177e4 2356 if (IS_QLA2100(ha)) {
642ef983 2357 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2358 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2359 req_length = REQUEST_ENTRY_CNT_2100;
2360 rsp_length = RESPONSE_ENTRY_CNT_2100;
2361 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2362 ha->gid_list_info_size = 4;
3a03eb79
AV		 2363 ha->flash_conf_off = ~0;
2364 ha->flash_data_off = ~0;
2365 ha->nvram_conf_off = ~0;
2366 ha->nvram_data_off = ~0;
fd34f556 2367 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2368 } else if (IS_QLA2200(ha)) {
642ef983 2369 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2370 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2371 req_length = REQUEST_ENTRY_CNT_2200;
2372 rsp_length = RESPONSE_ENTRY_CNT_2100;
2373 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2374 ha->gid_list_info_size = 4;
3a03eb79
AV		 2375 ha->flash_conf_off = ~0;
2376 ha->flash_data_off = ~0;
2377 ha->nvram_conf_off = ~0;
2378 ha->nvram_data_off = ~0;
fd34f556 2379 ha->isp_ops = &qla2100_isp_ops;
fca29703 2380 } else if (IS_QLA23XX(ha)) {
642ef983 2381 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2382 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2383 req_length = REQUEST_ENTRY_CNT_2200;
2384 rsp_length = RESPONSE_ENTRY_CNT_2300;
2385 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2386 ha->gid_list_info_size = 6;
854165f4 2387 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2388 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2389 ha->flash_conf_off = ~0;
2390 ha->flash_data_off = ~0;
2391 ha->nvram_conf_off = ~0;
2392 ha->nvram_data_off = ~0;
fd34f556 2393 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2394 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2395 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2396 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2397 req_length = REQUEST_ENTRY_CNT_24XX;
2398 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2399 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2400 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2401 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2402 ha->gid_list_info_size = 8;
854165f4 2403 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2404 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2405 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2406 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2407 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2408 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2409 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2410 } else if (IS_QLA25XX(ha)) {
642ef983 2411 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2412 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2413 req_length = REQUEST_ENTRY_CNT_24XX;
2414 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2415 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2416 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2417 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2418 ha->gid_list_info_size = 8;
2419 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2420 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2421 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2422 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2423 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2424 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2425 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2426 } else if (IS_QLA81XX(ha)) {
642ef983 2427 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2428 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2429 req_length = REQUEST_ENTRY_CNT_24XX;
2430 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2431 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2432 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2433 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2434 ha->gid_list_info_size = 8;
2435 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2436 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2437 ha->isp_ops = &qla81xx_isp_ops;
2438 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2439 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2440 ha->nvram_conf_off = ~0;
2441 ha->nvram_data_off = ~0;
a9083016 2442 } else if (IS_QLA82XX(ha)) {
642ef983 2443 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2444 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2445 req_length = REQUEST_ENTRY_CNT_82XX;
2446 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2447 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2448 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2449 ha->gid_list_info_size = 8;
2450 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2451 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2452 ha->isp_ops = &qla82xx_isp_ops;
2453 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2454 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2455 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2456 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2457 } else if (IS_QLA8044(ha)) {
2458 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2459 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2460 req_length = REQUEST_ENTRY_CNT_82XX;
2461 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2462 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2463 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2464 ha->gid_list_info_size = 8;
2465 ha->optrom_size = OPTROM_SIZE_83XX;
2466 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2467 ha->isp_ops = &qla8044_isp_ops;
2468 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2469 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2470 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2471 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2472 } else if (IS_QLA83XX(ha)) {
7d613ac6 2473 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2474 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2475 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2476 req_length = REQUEST_ENTRY_CNT_83XX;
6246b8a1 2477 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2478 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2479 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2480 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2481 ha->gid_list_info_size = 8;
2482 ha->optrom_size = OPTROM_SIZE_83XX;
2483 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2484 ha->isp_ops = &qla83xx_isp_ops;
2485 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2486 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2487 ha->nvram_conf_off = ~0;
2488 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2489 } else if (IS_QLAFX00(ha)) {
2490 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2491 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2492 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2493 req_length = REQUEST_ENTRY_CNT_FX00;
2494 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2495 ha->isp_ops = &qlafx00_isp_ops;
2496 ha->port_down_retry_count = 30; /* default value */
2497 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2498 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2499 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2500 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2501 ha->mr.host_info_resend = false;
2502 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2503 } else if (IS_QLA27XX(ha)) {
2504 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2505 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2506 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2507 req_length = REQUEST_ENTRY_CNT_24XX;
2508 rsp_length = RESPONSE_ENTRY_CNT_2300;
b20f02e1 2509 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2510 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2511 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2512 ha->gid_list_info_size = 8;
2513 ha->optrom_size = OPTROM_SIZE_83XX;
2514 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2515 ha->isp_ops = &qla27xx_isp_ops;
2516 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2517 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2518 ha->nvram_conf_off = ~0;
2519 ha->nvram_data_off = ~0;
1da177e4 2520 }
6246b8a1 2521
7c3df132
SK		 2522 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2523 "mbx_count=%d, req_length=%d, "
2524 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2525 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2526 "max_fibre_devices=%d.\n",
7c3df132
SK		 2527 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2528 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2529 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2530 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2531 "isp_ops=%p, flash_conf_off=%d, "
2532 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2533 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2534 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2535
2536 /* Configure PCI I/O space */
2537 ret = ha->isp_ops->iospace_config(ha);
2538 if (ret)
0a63ad12 2539 goto iospace_config_failed;
706f457d
GM		 2540
2541 ql_log_pci(ql_log_info, pdev, 0x001d,
2542 "Found an ISP%04X irq %d iobase 0x%p.\n",
2543 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2544 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2545 init_completion(&ha->mbx_cmd_comp);
2546 complete(&ha->mbx_cmd_comp);
2547 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2548 init_completion(&ha->dcbx_comp);
f356bef1 2549 init_completion(&ha->lb_portup_comp);
1da177e4 2550
2c3dfe3f 2551 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2552
53303c42 2553 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2554 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2555 "64 Bit addressing is %s.\n",
2556 ha->flags.enable_64bit_addressing ? "enable" :
2557 "disable");
73208dfd 2558 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2559 if (ret) {
7c3df132
SK		 2560 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2561 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2562
e315cd28
AC		 2563 goto probe_hw_failed;
2564 }
2565
73208dfd 2566 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2567 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2568 req->max_q_depth = ql2xmaxqdepth;
2569
e315cd28
AC		 2570
2571 base_vha = qla2x00_create_host(sht, ha);
2572 if (!base_vha) {
a1541d5a 2573 ret = -ENOMEM;
6e9f21f3 2574 qla2x00_mem_free(ha);
2afa19a9
AC		 2575 qla2x00_free_req_que(ha, req);
2576 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2577 goto probe_hw_failed;
1da177e4
LT		 2578 }
2579
e315cd28 2580 pci_set_drvdata(pdev, base_vha);
6b383979 2581 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2582
e315cd28 2583 host = base_vha->host;
2afa19a9 2584 base_vha->req = req;
73208dfd 2585 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2586 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2587 else
e315cd28
AC		 2588 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2589 base_vha->vp_idx;
58548cb5 2590
8ae6d9c7
GM		 2591 /* Setup fcport template structure. */
2592 ha->mr.fcport.vha = base_vha;
2593 ha->mr.fcport.port_type = FCT_UNKNOWN;
2594 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2595 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2596 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2597 ha->mr.fcport.scan_state = 1;
2598
58548cb5
GM		 2599 /* Set the SG table size based on ISP type */
2600 if (!IS_FWI2_CAPABLE(ha)) {
2601 if (IS_QLA2100(ha))
2602 host->sg_tablesize = 32;
2603 } else {
2604 if (!IS_QLA82XX(ha))
2605 host->sg_tablesize = QLA_SG_ALL;
2606 }
642ef983 2607 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2608 host->cmd_per_lun = 3;
2609 host->unique_id = host->host_no;
e02587d7 2610 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2611 host->max_cmd_len = 32;
2612 else
2613 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2614 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2615 /* Older HBAs support only 16-bit LUNs */
2616 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2617 ql2xmaxlun > 0xffff)
2618 host->max_lun = 0xffff;
2619 else
2620 host->max_lun = ql2xmaxlun;
e315cd28 2621 host->transportt = qla2xxx_transport_template;
9a069e19 2622 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2623
7c3df132
SK		 2624 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2625 "max_id=%d this_id=%d "
2626 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2627 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2628 host->this_id, host->cmd_per_lun, host->unique_id,
2629 host->max_cmd_len, host->max_channel, host->max_lun,
2630 host->transportt, sht->vendor_id);
2631
9a347ff4
CD		 2632que_init:
2633 /* Alloc arrays of request and response ring ptrs */
2634 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2635 ql_log(ql_log_fatal, base_vha, 0x003d,
2636 "Failed to allocate memory for queue pointers..."
2637 "aborting.\n");
2638 goto probe_init_failed;
2639 }
2640
2d70c103 2641 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2642
73208dfd
AC		 2643 /* Set up the irqs */
2644 ret = qla2x00_request_irqs(ha, rsp);
2645 if (ret)
6e9f21f3 2646 goto probe_init_failed;
90a86fc0
JC		 2647
2648 pci_save_state(pdev);
2649
9a347ff4 2650 /* Assign back pointers */
2afa19a9
AC		 2651 rsp->req = req;
2652 req->rsp = rsp;
9a347ff4 2653
8ae6d9c7
GM		 2654 if (IS_QLAFX00(ha)) {
2655 ha->rsp_q_map[0] = rsp;
2656 ha->req_q_map[0] = req;
2657 set_bit(0, ha->req_qid_map);
2658 set_bit(0, ha->rsp_qid_map);
2659 }
2660
08029990
AV		 2661 /* FWI2-capable only. */
2662 req->req_q_in = &ha->iobase->isp24.req_q_in;
2663 req->req_q_out = &ha->iobase->isp24.req_q_out;
2664 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2665 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2666 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2667 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2668 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2669 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2670 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2671 }
2672
8ae6d9c7
GM		 2673 if (IS_QLAFX00(ha)) {
2674 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2675 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2676 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2677 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2678 }
2679
7ec0effd 2680 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2681 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2682 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2683 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2684 }
2685
7c3df132
SK		 2686 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2687 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2688 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2689 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2690 "req->req_q_in=%p req->req_q_out=%p "
2691 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2692 req->req_q_in, req->req_q_out,
2693 rsp->rsp_q_in, rsp->rsp_q_out);
2694 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2695 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2696 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2697 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2698 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2699 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2700
8ae6d9c7 2701 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2702 ql_log(ql_log_fatal, base_vha, 0x00d6,
2703 "Failed to initialize adapter - Adapter flags %x.\n",
2704 base_vha->device_flags);
1da177e4 2705
a9083016
GM		 2706 if (IS_QLA82XX(ha)) {
2707 qla82xx_idc_lock(ha);
2708 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2709 QLA8XXX_DEV_FAILED);
a9083016 2710 qla82xx_idc_unlock(ha);
7c3df132
SK		 2711 ql_log(ql_log_fatal, base_vha, 0x00d7,
2712 "HW State: FAILED.\n");
7ec0effd
AD		 2713 } else if (IS_QLA8044(ha)) {
2714 qla8044_idc_lock(ha);
2715 qla8044_wr_direct(base_vha,
2716 QLA8044_CRB_DEV_STATE_INDEX,
2717 QLA8XXX_DEV_FAILED);
2718 qla8044_idc_unlock(ha);
2719 ql_log(ql_log_fatal, base_vha, 0x0150,
2720 "HW State: FAILED.\n");
a9083016
GM		 2721 }
2722
a1541d5a 2723 ret = -ENODEV;
1da177e4
LT		 2724 goto probe_failed;
2725 }
2726
3b1bef64
CD		 2727 if (IS_QLAFX00(ha))
2728 host->can_queue = QLAFX00_MAX_CANQUEUE;
2729 else
2730 host->can_queue = req->num_outstanding_cmds - 10;
2731
2732 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2733 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2734 host->can_queue, base_vha->req,
2735 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2736
7163ea81
AC		 2737 if (ha->mqenable) {
2738 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2739 ql_log(ql_log_warn, base_vha, 0x00ec,
2740 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2741 goto que_init;
2742 }
2743 }
68ca949c 2744
cbc8eb67
AV		 2745 if (ha->flags.running_gold_fw)
2746 goto skip_dpc;
2747
1da177e4
LT		 2748 /*
2749 * Startup the kernel thread for this host adapter
2750 */
39a11240 2751 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2752 "%s_dpc", base_vha->host_str);
39a11240 2753 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2754 ql_log(ql_log_fatal, base_vha, 0x00ed,
2755 "Failed to start DPC thread.\n");
39a11240 2756 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2757 goto probe_failed;
2758 }
7c3df132
SK		 2759 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2760 "DPC thread started successfully.\n");
1da177e4 2761
2d70c103
NB		 2762 /*
2763 * If we're not coming up in initiator mode, we might sit for
2764 * a while without waking up the dpc thread, which leads to a
2765 * stuck process warning. So just kick the dpc once here and
2766 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2767 */
2768 qla2xxx_wake_dpc(base_vha);
2769
f3ddac19
CD		 2770 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2771
81178772
SK		 2772 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2773 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2774 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2775 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2776
2777 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2778 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2779 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2780 INIT_WORK(&ha->idc_state_handler,
2781 qla83xx_idc_state_handler_work);
2782 INIT_WORK(&ha->nic_core_unrecoverable,
2783 qla83xx_nic_core_unrecoverable_work);
2784 }
2785
cbc8eb67 2786skip_dpc:
e315cd28
AC		 2787 list_add_tail(&base_vha->list, &ha->vp_list);
2788 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2789
2790 /* Initialized the timer */
e315cd28 2791 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2792 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2793 "Started qla2x00_timer with "
2794 "interval=%d.\n", WATCH_INTERVAL);
2795 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2796 "Detected hba at address=%p.\n",
2797 ha);
d19044c3 2798
e02587d7 2799 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2800 if (ha->fw_attributes & BIT_4) {
9e522cd8 2801 int prot = 0, guard;
bad75002 2802 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2803 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2804 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2805 if (ql2xenabledif == 1)
2806 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2807 scsi_host_set_prot(host,
8cb2049c 2808 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2809 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2810 | SHOST_DIF_TYPE3_PROTECTION
2811 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2812 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2813 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2814
2815 guard = SHOST_DIX_GUARD_CRC;
2816
2817 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2818 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2819 guard |= SHOST_DIX_GUARD_IP;
2820
2821 scsi_host_set_guard(host, guard);
bad75002
AE		 2822 } else
2823 base_vha->flags.difdix_supported = 0;
2824 }
2825
a9083016
GM		 2826 ha->isp_ops->enable_intrs(ha);
2827
1fe19ee4
AB		 2828 if (IS_QLAFX00(ha)) {
2829 ret = qlafx00_fx_disc(base_vha,
2830 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2831 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2832 QLA_SG_ALL : 128;
2833 }
2834
a1541d5a
AV		 2835 ret = scsi_add_host(host, &pdev->dev);
2836 if (ret)
2837 goto probe_failed;
2838
1486400f
MR		 2839 base_vha->flags.init_done = 1;
2840 base_vha->flags.online = 1;
edaa5c74 2841 ha->prev_minidump_failed = 0;
1486400f 2842
7c3df132
SK		 2843 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2844 "Init done and hba is online.\n");
2845
2d70c103
NB		 2846 if (qla_ini_mode_enabled(base_vha))
2847 scsi_scan_host(host);
2848 else
2849 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2850 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2851
e315cd28 2852 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2853
8ae6d9c7 2854 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 2855 ret = qlafx00_fx_disc(base_vha,
2856 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2857
2858 /* Register system information */
2859 ret = qlafx00_fx_disc(base_vha,
2860 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2861 }
2862
e315cd28 2863 qla2x00_init_host_attr(base_vha);
a1541d5a 2864
e315cd28 2865 qla2x00_dfs_setup(base_vha);
df613b96 2866
03eb912a
AB		 2867 ql_log(ql_log_info, base_vha, 0x00fb,
2868 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 2869 ql_log(ql_log_info, base_vha, 0x00fc,
2870 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2871 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2872 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2873 base_vha->host_no,
df57caba 2874 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 2875
2d70c103
NB		 2876 qlt_add_target(ha, base_vha);
2877
6b383979 2878 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
1da177e4
LT		 2879 return 0;
2880
6e9f21f3 2881probe_init_failed:
2afa19a9 2882 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2883 ha->req_q_map[0] = NULL;
2884 clear_bit(0, ha->req_qid_map);
2afa19a9 2885 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2886 ha->rsp_q_map[0] = NULL;
2887 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2888 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2889
1da177e4 2890probe_failed:
b9978769
AV		 2891 if (base_vha->timer_active)
2892 qla2x00_stop_timer(base_vha);
2893 base_vha->flags.online = 0;
2894 if (ha->dpc_thread) {
2895 struct task_struct *t = ha->dpc_thread;
2896
2897 ha->dpc_thread = NULL;
2898 kthread_stop(t);
2899 }
2900
e315cd28 2901 qla2x00_free_device(base_vha);
1da177e4 2902
e315cd28 2903 scsi_host_put(base_vha->host);
1da177e4 2904
e315cd28 2905probe_hw_failed:
1a2fbf18
JL		 2906 qla2x00_clear_drv_active(ha);
2907
0a63ad12 2908iospace_config_failed:
7ec0effd 2909 if (IS_P3P_TYPE(ha)) {
0a63ad12 2910 if (!ha->nx_pcibase)
f73cb695 2911 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 2912 if (!ql2xdbwr)
f73cb695 2913 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 2914 } else {
2915 if (ha->iobase)
2916 iounmap(ha->iobase);
8ae6d9c7
GM		 2917 if (ha->cregbase)
2918 iounmap(ha->cregbase);
a9083016 2919 }
e315cd28
AC		 2920 pci_release_selected_regions(ha->pdev, ha->bars);
2921 kfree(ha);
2922 ha = NULL;
1da177e4 2923
a1541d5a 2924probe_out:
e315cd28 2925 pci_disable_device(pdev);
a1541d5a 2926 return ret;
1da177e4 2927}
1da177e4 2928
e30d1756
MI		 2929static void
2930qla2x00_shutdown(struct pci_dev *pdev)
2931{
2932 scsi_qla_host_t *vha;
2933 struct qla_hw_data *ha;
2934
552f3f9a
MI		 2935 if (!atomic_read(&pdev->enable_cnt))
2936 return;
2937
e30d1756
MI		 2938 vha = pci_get_drvdata(pdev);
2939 ha = vha->hw;
2940
42479343
AB		 2941 /* Notify ISPFX00 firmware */
2942 if (IS_QLAFX00(ha))
2943 qlafx00_driver_shutdown(vha, 20);
2944
e30d1756
MI		 2945 /* Turn-off FCE trace */
2946 if (ha->flags.fce_enabled) {
2947 qla2x00_disable_fce_trace(vha, NULL, NULL);
2948 ha->flags.fce_enabled = 0;
2949 }
2950
2951 /* Turn-off EFT trace */
2952 if (ha->eft)
2953 qla2x00_disable_eft_trace(vha);
2954
2955 /* Stop currently executing firmware. */
2956 qla2x00_try_to_stop_firmware(vha);
2957
2958 /* Turn adapter off line */
2959 vha->flags.online = 0;
2960
2961 /* turn-off interrupts on the card */
2962 if (ha->interrupts_on) {
2963 vha->flags.init_done = 0;
2964 ha->isp_ops->disable_intrs(ha);
2965 }
2966
2967 qla2x00_free_irqs(vha);
2968
2969 qla2x00_free_fw_dump(ha);
61d41f61
CD		 2970
2971 pci_disable_pcie_error_reporting(pdev);
2972 pci_disable_device(pdev);
e30d1756
MI		 2973}
2974
fe1b806f 2975/* Deletes all the virtual ports for a given ha */
4c993f76 2976static void
fe1b806f 2977qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 2978{
fe1b806f 2979 scsi_qla_host_t *vha;
feafb7b1 2980 unsigned long flags;
e315cd28 2981
43ebf16d
AE		 2982 mutex_lock(&ha->vport_lock);
2983 while (ha->cur_vport_count) {
43ebf16d 2984 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2985
43ebf16d
AE		 2986 BUG_ON(base_vha->list.next == &ha->vp_list);
2987 /* This assumes first entry in ha->vp_list is always base vha */
2988 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 2989 scsi_host_get(vha->host);
feafb7b1 2990
43ebf16d
AE		 2991 spin_unlock_irqrestore(&ha->vport_slock, flags);
2992 mutex_unlock(&ha->vport_lock);
2993
2994 fc_vport_terminate(vha->fc_vport);
2995 scsi_host_put(vha->host);
feafb7b1 2996
43ebf16d 2997 mutex_lock(&ha->vport_lock);
e315cd28 2998 }
43ebf16d 2999 mutex_unlock(&ha->vport_lock);
fe1b806f 3000}
1da177e4 3001
fe1b806f
CD		 3002/* Stops all deferred work threads */
3003static void
3004qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3005{
68ca949c
AC		 3006 /* Flush the work queue and remove it */
3007 if (ha->wq) {
3008 flush_workqueue(ha->wq);
3009 destroy_workqueue(ha->wq);
3010 ha->wq = NULL;
3011 }
3012
7d613ac6
SV		 3013 /* Cancel all work and destroy DPC workqueues */
3014 if (ha->dpc_lp_wq) {
3015 cancel_work_sync(&ha->idc_aen);
3016 destroy_workqueue(ha->dpc_lp_wq);
3017 ha->dpc_lp_wq = NULL;
3018 }
3019
3020 if (ha->dpc_hp_wq) {
3021 cancel_work_sync(&ha->nic_core_reset);
3022 cancel_work_sync(&ha->idc_state_handler);
3023 cancel_work_sync(&ha->nic_core_unrecoverable);
3024 destroy_workqueue(ha->dpc_hp_wq);
3025 ha->dpc_hp_wq = NULL;
3026 }
3027
b9978769
AV		 3028 /* Kill the kernel thread for this host */
3029 if (ha->dpc_thread) {
3030 struct task_struct *t = ha->dpc_thread;
3031
3032 /*
3033 * qla2xxx_wake_dpc checks for ->dpc_thread
3034 * so we need to zero it out.
3035 */
3036 ha->dpc_thread = NULL;
3037 kthread_stop(t);
3038 }
fe1b806f 3039}
1da177e4 3040
fe1b806f
CD		 3041static void
3042qla2x00_unmap_iobases(struct qla_hw_data *ha)
3043{
a9083016 3044 if (IS_QLA82XX(ha)) {
b963752f 3045
f73cb695 3046 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3047 if (!ql2xdbwr)
f73cb695 3048 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3049 } else {
3050 if (ha->iobase)
3051 iounmap(ha->iobase);
1da177e4 3052
8ae6d9c7
GM		 3053 if (ha->cregbase)
3054 iounmap(ha->cregbase);
3055
a9083016
GM		 3056 if (ha->mqiobase)
3057 iounmap(ha->mqiobase);
6246b8a1 3058
f73cb695 3059 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3060 iounmap(ha->msixbase);
a9083016 3061 }
fe1b806f
CD		 3062}
3063
3064static void
db7157d4 3065qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3066{
fe1b806f
CD		 3067 if (IS_QLA8044(ha)) {
3068 qla8044_idc_lock(ha);
c41afc9a 3069 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3070 qla8044_idc_unlock(ha);
3071 } else if (IS_QLA82XX(ha)) {
3072 qla82xx_idc_lock(ha);
3073 qla82xx_clear_drv_active(ha);
3074 qla82xx_idc_unlock(ha);
3075 }
3076}
3077
3078static void
3079qla2x00_remove_one(struct pci_dev *pdev)
3080{
3081 scsi_qla_host_t *base_vha;
3082 struct qla_hw_data *ha;
3083
beb9e315
JL		 3084 base_vha = pci_get_drvdata(pdev);
3085 ha = base_vha->hw;
3086
3087 /* Indicate device removal to prevent future board_disable and wait
3088 * until any pending board_disable has completed. */
3089 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3090 cancel_work_sync(&ha->board_disable);
3091
fe1b806f 3092 /*
beb9e315
JL		 3093 * If the PCI device is disabled then there was a PCI-disconnect and
3094 * qla2x00_disable_board_on_pci_error has taken care of most of the
3095 * resources.
fe1b806f 3096 */
beb9e315
JL		 3097 if (!atomic_read(&pdev->enable_cnt)) {
3098 scsi_host_put(base_vha->host);
3099 kfree(ha);
3100 pci_set_drvdata(pdev, NULL);
fe1b806f 3101 return;
beb9e315 3102 }
fe1b806f 3103
638a1a01
SC		 3104 qla2x00_wait_for_hba_ready(base_vha);
3105
fe1b806f
CD		 3106 set_bit(UNLOADING, &base_vha->dpc_flags);
3107
3108 if (IS_QLAFX00(ha))
3109 qlafx00_driver_shutdown(base_vha, 20);
3110
3111 qla2x00_delete_all_vps(ha, base_vha);
3112
3113 if (IS_QLA8031(ha)) {
3114 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3115 "Clearing fcoe driver presence.\n");
3116 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3117 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3118 "Error while clearing DRV-Presence.\n");
3119 }
3120
3121 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3122
3123 qla2x00_dfs_remove(base_vha);
3124
3125 qla84xx_put_chip(base_vha);
3126
2d5a4c34
HM		 3127 /* Laser should be disabled only for ISP2031 */
3128 if (IS_QLA2031(ha))
3129 qla83xx_disable_laser(base_vha);
3130
fe1b806f
CD		 3131 /* Disable timer */
3132 if (base_vha->timer_active)
3133 qla2x00_stop_timer(base_vha);
3134
3135 base_vha->flags.online = 0;
3136
b0d6cabd
HM		 3137 /* free DMA memory */
3138 if (ha->exlogin_buf)
3139 qla2x00_free_exlogin_buffer(ha);
3140
fe1b806f
CD		 3141 qla2x00_destroy_deferred_work(ha);
3142
3143 qlt_remove_target(ha, base_vha);
3144
3145 qla2x00_free_sysfs_attr(base_vha, true);
3146
3147 fc_remove_host(base_vha->host);
3148
3149 scsi_remove_host(base_vha->host);
3150
3151 qla2x00_free_device(base_vha);
3152
db7157d4 3153 qla2x00_clear_drv_active(ha);
fe1b806f 3154
d2749ffa
AE		 3155 scsi_host_put(base_vha->host);
3156
fe1b806f 3157 qla2x00_unmap_iobases(ha);
73208dfd 3158
e315cd28
AC		 3159 pci_release_selected_regions(ha->pdev, ha->bars);
3160 kfree(ha);
3161 ha = NULL;
1da177e4 3162
90a86fc0
JC		 3163 pci_disable_pcie_error_reporting(pdev);
3164
665db93b 3165 pci_disable_device(pdev);
1da177e4 3166}
1da177e4
LT		 3167
3168static void
e315cd28 3169qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3170{
e315cd28 3171 struct qla_hw_data *ha = vha->hw;
1da177e4 3172
85880801
AV		 3173 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3174
3175 /* Disable timer */
3176 if (vha->timer_active)
3177 qla2x00_stop_timer(vha);
3178
2afa19a9 3179 qla25xx_delete_queues(vha);
fe1b806f 3180
df613b96 3181 if (ha->flags.fce_enabled)
e315cd28 3182 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3183
a7a167bf 3184 if (ha->eft)
e315cd28 3185 qla2x00_disable_eft_trace(vha);
a7a167bf 3186
f6ef3b18 3187 /* Stop currently executing firmware. */
e315cd28 3188 qla2x00_try_to_stop_firmware(vha);
1da177e4 3189
85880801
AV		 3190 vha->flags.online = 0;
3191
f6ef3b18 3192 /* turn-off interrupts on the card */
a9083016
GM		 3193 if (ha->interrupts_on) {
3194 vha->flags.init_done = 0;
fd34f556 3195 ha->isp_ops->disable_intrs(ha);
a9083016 3196 }
f6ef3b18 3197
e315cd28 3198 qla2x00_free_irqs(vha);
1da177e4 3199
8867048b
CD		 3200 qla2x00_free_fcports(vha);
3201
e315cd28 3202 qla2x00_mem_free(ha);
73208dfd 3203
08de2844
GM		 3204 qla82xx_md_free(vha);
3205
73208dfd 3206 qla2x00_free_queues(ha);
1da177e4
LT		 3207}
3208
8867048b
CD		 3209void qla2x00_free_fcports(struct scsi_qla_host *vha)
3210{
3211 fc_port_t *fcport, *tfcport;
3212
3213 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3214 list_del(&fcport->list);
5f16b331 3215 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3216 kfree(fcport);
3217 fcport = NULL;
3218 }
3219}
3220
d97994dc 3221static inline void
e315cd28 3222qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3223 int defer)
3224{
d97994dc 3225 struct fc_rport *rport;
67becc00 3226 scsi_qla_host_t *base_vha;
044d78e1 3227 unsigned long flags;
d97994dc 3228
3229 if (!fcport->rport)
3230 return;
3231
3232 rport = fcport->rport;
3233 if (defer) {
67becc00 3234 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3235 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3236 fcport->drport = rport;
044d78e1 3237 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3238 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3239 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3240 qla2xxx_wake_dpc(base_vha);
2d70c103 3241 } else {
df673274 3242 int now;
d20ed91b
AP		 3243 if (rport)
3244 fc_remote_port_delete(rport);
df673274
AP		 3245 qlt_do_generation_tick(vha, &now);
3246 qlt_fc_port_deleted(vha, fcport, now);
2d70c103 3247 }
d97994dc 3248}
3249
1da177e4
LT		 3250/*
3251 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3252 *
3253 * Input: ha = adapter block pointer. fcport = port structure pointer.
3254 *
3255 * Return: None.
3256 *
3257 * Context:
3258 */
e315cd28 3259void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3260 int do_login, int defer)
1da177e4 3261{
8ae6d9c7
GM		 3262 if (IS_QLAFX00(vha->hw)) {
3263 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3264 qla2x00_schedule_rport_del(vha, fcport, defer);
3265 return;
3266 }
3267
2c3dfe3f 3268 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3269 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3270 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3271 qla2x00_schedule_rport_del(vha, fcport, defer);
3272 }
fa2a1ce5 3273 /*
1da177e4
LT		 3274 * We may need to retry the login, so don't change the state of the
3275 * port but do the retries.
3276 */
3277 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3278 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3279
3280 if (!do_login)
3281 return;
3282
a1d0285e
AE		 3283 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3284
1da177e4 3285 if (fcport->login_retry == 0) {
e315cd28 3286 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3287
7c3df132 3288 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3289 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3290 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3291 }
3292}
3293
3294/*
3295 * qla2x00_mark_all_devices_lost
3296 * Updates fcport state when device goes offline.
3297 *
3298 * Input:
3299 * ha = adapter block pointer.
3300 * fcport = port structure pointer.
3301 *
3302 * Return:
3303 * None.
3304 *
3305 * Context:
3306 */
3307void
e315cd28 3308qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3309{
3310 fc_port_t *fcport;
3311
e315cd28 3312 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3313 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3314 continue;
0d6e61bc 3315
1da177e4
LT		 3316 /*
3317 * No point in marking the device as lost, if the device is
3318 * already DEAD.
3319 */
3320 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3321 continue;
e315cd28 3322 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3323 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3324 if (defer)
3325 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3326 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3327 qla2x00_schedule_rport_del(vha, fcport, defer);
3328 }
1da177e4
LT		 3329 }
3330}
3331
3332/*
3333* qla2x00_mem_alloc
3334* Allocates adapter memory.
3335*
3336* Returns:
3337* 0 = success.
e8711085 3338* !0 = failure.
1da177e4 3339*/
e8711085 3340static int
73208dfd
AC		 3341qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3342 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3343{
3344 char name[16];
1da177e4 3345
e8711085 3346 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3347 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3348 if (!ha->init_cb)
e315cd28 3349 goto fail;
e8711085 3350
2d70c103
NB		 3351 if (qlt_mem_alloc(ha) < 0)
3352 goto fail_free_init_cb;
3353
642ef983
CD		 3354 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3355 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3356 if (!ha->gid_list)
2d70c103 3357 goto fail_free_tgt_mem;
1da177e4 3358
e8711085
AV		 3359 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3360 if (!ha->srb_mempool)
e315cd28 3361 goto fail_free_gid_list;
e8711085 3362
7ec0effd 3363 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3364 /* Allocate cache for CT6 Ctx. */
3365 if (!ctx_cachep) {
3366 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3367 sizeof(struct ct6_dsd), 0,
3368 SLAB_HWCACHE_ALIGN, NULL);
3369 if (!ctx_cachep)
3370 goto fail_free_gid_list;
3371 }
3372 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3373 ctx_cachep);
3374 if (!ha->ctx_mempool)
3375 goto fail_free_srb_mempool;
7c3df132
SK		 3376 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3377 "ctx_cachep=%p ctx_mempool=%p.\n",
3378 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3379 }
3380
e8711085
AV		 3381 /* Get memory for cached NVRAM */
3382 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3383 if (!ha->nvram)
a9083016 3384 goto fail_free_ctx_mempool;
e8711085 3385
e315cd28
AC		 3386 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3387 ha->pdev->device);
3388 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3389 DMA_POOL_SIZE, 8, 0);
3390 if (!ha->s_dma_pool)
3391 goto fail_free_nvram;
3392
7c3df132
SK		 3393 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3394 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3395 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3396
7ec0effd 3397 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3398 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3399 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3400 if (!ha->dl_dma_pool) {
7c3df132
SK		 3401 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3402 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3403 goto fail_s_dma_pool;
3404 }
3405
3406 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3407 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3408 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3409 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3410 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3411 goto fail_dl_dma_pool;
3412 }
7c3df132
SK		 3413 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3414 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3415 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3416 }
3417
e8711085
AV		 3418 /* Allocate memory for SNS commands */
3419 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3420 /* Get consistent memory allocated for SNS commands */
e8711085 3421 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3422 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3423 if (!ha->sns_cmd)
e315cd28 3424 goto fail_dma_pool;
7c3df132 3425 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3426 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3427 } else {
e315cd28 3428 /* Get consistent memory allocated for MS IOCB */
e8711085 3429 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3430 &ha->ms_iocb_dma);
e8711085 3431 if (!ha->ms_iocb)
e315cd28
AC		 3432 goto fail_dma_pool;
3433 /* Get consistent memory allocated for CT SNS commands */
e8711085 3434 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3435 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3436 if (!ha->ct_sns)
3437 goto fail_free_ms_iocb;
7c3df132
SK		 3438 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3439 "ms_iocb=%p ct_sns=%p.\n",
3440 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3441 }
3442
e315cd28 3443 /* Allocate memory for request ring */
73208dfd
AC		 3444 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3445 if (!*req) {
7c3df132
SK		 3446 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3447 "Failed to allocate memory for req.\n");
e315cd28
AC		 3448 goto fail_req;
3449 }
73208dfd
AC		 3450 (*req)->length = req_len;
3451 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3452 ((*req)->length + 1) * sizeof(request_t),
3453 &(*req)->dma, GFP_KERNEL);
3454 if (!(*req)->ring) {
7c3df132
SK		 3455 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3456 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3457 goto fail_req_ring;
3458 }
3459 /* Allocate memory for response ring */
73208dfd
AC		 3460 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3461 if (!*rsp) {
7c3df132
SK		 3462 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3463 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3464 goto fail_rsp;
3465 }
73208dfd
AC		 3466 (*rsp)->hw = ha;
3467 (*rsp)->length = rsp_len;
3468 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3469 ((*rsp)->length + 1) * sizeof(response_t),
3470 &(*rsp)->dma, GFP_KERNEL);
3471 if (!(*rsp)->ring) {
7c3df132
SK		 3472 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3473 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3474 goto fail_rsp_ring;
3475 }
73208dfd
AC		 3476 (*req)->rsp = *rsp;
3477 (*rsp)->req = *req;
7c3df132
SK		 3478 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3479 "req=%p req->length=%d req->ring=%p rsp=%p "
3480 "rsp->length=%d rsp->ring=%p.\n",
3481 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3482 (*rsp)->ring);
73208dfd
AC		 3483 /* Allocate memory for NVRAM data for vports */
3484 if (ha->nvram_npiv_size) {
3485 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3486 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3487 if (!ha->npiv_info) {
7c3df132
SK		 3488 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3489 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3490 goto fail_npiv_info;
3491 }
3492 } else
3493 ha->npiv_info = NULL;
e8711085 3494
b64b0e8f 3495 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3496 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3497 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3498 &ha->ex_init_cb_dma);
3499 if (!ha->ex_init_cb)
3500 goto fail_ex_init_cb;
7c3df132
SK		 3501 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3502 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3503 }
3504
a9083016
GM		 3505 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3506
5ff1d584
AV		 3507 /* Get consistent memory allocated for Async Port-Database. */
3508 if (!IS_FWI2_CAPABLE(ha)) {
3509 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3510 &ha->async_pd_dma);
3511 if (!ha->async_pd)
3512 goto fail_async_pd;
7c3df132
SK		 3513 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3514 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3515 }
3516
e315cd28 3517 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3518
3519 /* Allocate memory for our loop_id bitmap */
3520 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3521 GFP_KERNEL);
3522 if (!ha->loop_id_map)
3523 goto fail_async_pd;
3524 else {
3525 qla2x00_set_reserved_loop_ids(ha);
3526 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3527 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3528 }
3529
b2a72ec3 3530 return 0;
e315cd28 3531
5ff1d584
AV		 3532fail_async_pd:
3533 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3534fail_ex_init_cb:
3535 kfree(ha->npiv_info);
73208dfd
AC		 3536fail_npiv_info:
3537 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3538 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3539 (*rsp)->ring = NULL;
3540 (*rsp)->dma = 0;
e315cd28 3541fail_rsp_ring:
73208dfd 3542 kfree(*rsp);
e315cd28 3543fail_rsp:
73208dfd
AC		 3544 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3545 sizeof(request_t), (*req)->ring, (*req)->dma);
3546 (*req)->ring = NULL;
3547 (*req)->dma = 0;
e315cd28 3548fail_req_ring:
73208dfd 3549 kfree(*req);
e315cd28
AC		 3550fail_req:
3551 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3552 ha->ct_sns, ha->ct_sns_dma);
3553 ha->ct_sns = NULL;
3554 ha->ct_sns_dma = 0;
e8711085
AV		 3555fail_free_ms_iocb:
3556 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3557 ha->ms_iocb = NULL;
3558 ha->ms_iocb_dma = 0;
e315cd28 3559fail_dma_pool:
bad75002 3560 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3561 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3562 ha->fcp_cmnd_dma_pool = NULL;
3563 }
3564fail_dl_dma_pool:
bad75002 3565 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3566 dma_pool_destroy(ha->dl_dma_pool);
3567 ha->dl_dma_pool = NULL;
3568 }
3569fail_s_dma_pool:
e315cd28
AC		 3570 dma_pool_destroy(ha->s_dma_pool);
3571 ha->s_dma_pool = NULL;
e8711085
AV		 3572fail_free_nvram:
3573 kfree(ha->nvram);
3574 ha->nvram = NULL;
a9083016
GM		 3575fail_free_ctx_mempool:
3576 mempool_destroy(ha->ctx_mempool);
3577 ha->ctx_mempool = NULL;
e8711085
AV		 3578fail_free_srb_mempool:
3579 mempool_destroy(ha->srb_mempool);
3580 ha->srb_mempool = NULL;
e8711085 3581fail_free_gid_list:
642ef983
CD		 3582 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3583 ha->gid_list,
e315cd28 3584 ha->gid_list_dma);
e8711085
AV		 3585 ha->gid_list = NULL;
3586 ha->gid_list_dma = 0;
2d70c103
NB		 3587fail_free_tgt_mem:
3588 qlt_mem_free(ha);
e315cd28
AC		 3589fail_free_init_cb:
3590 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3591 ha->init_cb_dma);
3592 ha->init_cb = NULL;
3593 ha->init_cb_dma = 0;
e8711085 3594fail:
7c3df132
SK		 3595 ql_log(ql_log_fatal, NULL, 0x0030,
3596 "Memory allocation failure.\n");
e8711085 3597 return -ENOMEM;
1da177e4
LT		 3598}
3599
b0d6cabd
HM		 3600int
3601qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
3602{
3603 int rval;
3604 uint16_t size, max_cnt, temp;
3605 struct qla_hw_data *ha = vha->hw;
3606
3607 /* Return if we don't need to alloacate any extended logins */
3608 if (!ql2xexlogins)
3609 return QLA_SUCCESS;
3610
3611 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
3612 max_cnt = 0;
3613 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
3614 if (rval != QLA_SUCCESS) {
3615 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
3616 "Failed to get exlogin status.\n");
3617 return rval;
3618 }
3619
3620 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
3621 ha->exlogin_size = (size * temp);
3622 ql_log(ql_log_info, vha, 0xd024,
3623 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
3624 max_cnt, size, temp);
3625
3626 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n",
3627 ha->exlogin_size);
3628
3629 /* Get consistent memory for extended logins */
3630 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
3631 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
3632 if (!ha->exlogin_buf) {
3633 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
3634 "Failed to allocate memory for exlogin_buf_dma.\n");
3635 return -ENOMEM;
3636 }
3637
3638 /* Now configure the dma buffer */
3639 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
3640 if (rval) {
3641 ql_log(ql_log_fatal, vha, 0x00cf,
3642 "Setup extended login buffer ****FAILED****.\n");
3643 qla2x00_free_exlogin_buffer(ha);
3644 }
3645
3646 return rval;
3647}
3648
3649/*
3650* qla2x00_free_exlogin_buffer
3651*
3652* Input:
3653* ha = adapter block pointer
3654*/
3655void
3656qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
3657{
3658 if (ha->exlogin_buf) {
3659 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
3660 ha->exlogin_buf, ha->exlogin_buf_dma);
3661 ha->exlogin_buf = NULL;
3662 ha->exlogin_size = 0;
3663 }
3664}
3665
1da177e4 3666/*
e30d1756
MI		 3667* qla2x00_free_fw_dump
3668* Frees fw dump stuff.
1da177e4
LT		 3669*
3670* Input:
7ec0effd 3671* ha = adapter block pointer
1da177e4 3672*/
a824ebb3 3673static void
e30d1756 3674qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3675{
df613b96 3676 if (ha->fce)
f73cb695
CD		 3677 dma_free_coherent(&ha->pdev->dev,
3678 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 3679
f73cb695
CD		 3680 if (ha->eft)
3681 dma_free_coherent(&ha->pdev->dev,
3682 EFT_SIZE, ha->eft, ha->eft_dma);
3683
3684 if (ha->fw_dump)
a7a167bf 3685 vfree(ha->fw_dump);
f73cb695
CD		 3686 if (ha->fw_dump_template)
3687 vfree(ha->fw_dump_template);
3688
e30d1756
MI		 3689 ha->fce = NULL;
3690 ha->fce_dma = 0;
3691 ha->eft = NULL;
3692 ha->eft_dma = 0;
e30d1756 3693 ha->fw_dumped = 0;
61f098dd 3694 ha->fw_dump_cap_flags = 0;
e30d1756 3695 ha->fw_dump_reading = 0;
f73cb695
CD		 3696 ha->fw_dump = NULL;
3697 ha->fw_dump_len = 0;
3698 ha->fw_dump_template = NULL;
3699 ha->fw_dump_template_len = 0;
e30d1756
MI		 3700}
3701
3702/*
3703* qla2x00_mem_free
3704* Frees all adapter allocated memory.
3705*
3706* Input:
3707* ha = adapter block pointer.
3708*/
3709static void
3710qla2x00_mem_free(struct qla_hw_data *ha)
3711{
3712 qla2x00_free_fw_dump(ha);
3713
81178772
SK		 3714 if (ha->mctp_dump)
3715 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3716 ha->mctp_dump_dma);
3717
e30d1756
MI		 3718 if (ha->srb_mempool)
3719 mempool_destroy(ha->srb_mempool);
a7a167bf 3720
11bbc1d8
AV		 3721 if (ha->dcbx_tlv)
3722 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3723 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3724
ce0423f4
AV		 3725 if (ha->xgmac_data)
3726 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3727 ha->xgmac_data, ha->xgmac_data_dma);
3728
1da177e4
LT		 3729 if (ha->sns_cmd)
3730 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3731 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3732
3733 if (ha->ct_sns)
3734 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3735 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3736
88729e53
AV		 3737 if (ha->sfp_data)
3738 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3739
1da177e4
LT		 3740 if (ha->ms_iocb)
3741 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3742
b64b0e8f 3743 if (ha->ex_init_cb)
a9083016
GM		 3744 dma_pool_free(ha->s_dma_pool,
3745 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3746
5ff1d584
AV		 3747 if (ha->async_pd)
3748 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3749
1da177e4
LT		 3750 if (ha->s_dma_pool)
3751 dma_pool_destroy(ha->s_dma_pool);
3752
1da177e4 3753 if (ha->gid_list)
642ef983
CD		 3754 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3755 ha->gid_list, ha->gid_list_dma);
1da177e4 3756
a9083016
GM		 3757 if (IS_QLA82XX(ha)) {
3758 if (!list_empty(&ha->gbl_dsd_list)) {
3759 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3760
3761 /* clean up allocated prev pool */
3762 list_for_each_entry_safe(dsd_ptr,
3763 tdsd_ptr, &ha->gbl_dsd_list, list) {
3764 dma_pool_free(ha->dl_dma_pool,
3765 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3766 list_del(&dsd_ptr->list);
3767 kfree(dsd_ptr);
3768 }
3769 }
3770 }
3771
3772 if (ha->dl_dma_pool)
3773 dma_pool_destroy(ha->dl_dma_pool);
3774
3775 if (ha->fcp_cmnd_dma_pool)
3776 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3777
3778 if (ha->ctx_mempool)
3779 mempool_destroy(ha->ctx_mempool);
3780
2d70c103
NB		 3781 qlt_mem_free(ha);
3782
e315cd28
AC		 3783 if (ha->init_cb)
3784 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3785 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3786 vfree(ha->optrom_buffer);
3787 kfree(ha->nvram);
73208dfd 3788 kfree(ha->npiv_info);
7a67735b 3789 kfree(ha->swl);
5f16b331 3790 kfree(ha->loop_id_map);
1da177e4 3791
e8711085 3792 ha->srb_mempool = NULL;
a9083016 3793 ha->ctx_mempool = NULL;
1da177e4
LT		 3794 ha->sns_cmd = NULL;
3795 ha->sns_cmd_dma = 0;
3796 ha->ct_sns = NULL;
3797 ha->ct_sns_dma = 0;
3798 ha->ms_iocb = NULL;
3799 ha->ms_iocb_dma = 0;
1da177e4
LT		 3800 ha->init_cb = NULL;
3801 ha->init_cb_dma = 0;
b64b0e8f
AV		 3802 ha->ex_init_cb = NULL;
3803 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3804 ha->async_pd = NULL;
3805 ha->async_pd_dma = 0;
1da177e4
LT		 3806
3807 ha->s_dma_pool = NULL;
a9083016
GM		 3808 ha->dl_dma_pool = NULL;
3809 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3810
1da177e4
LT		 3811 ha->gid_list = NULL;
3812 ha->gid_list_dma = 0;
2d70c103
NB		 3813
3814 ha->tgt.atio_ring = NULL;
3815 ha->tgt.atio_dma = 0;
3816 ha->tgt.tgt_vp_map = NULL;
e315cd28 3817}
1da177e4 3818
e315cd28
AC		 3819struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3820 struct qla_hw_data *ha)
3821{
3822 struct Scsi_Host *host;
3823 struct scsi_qla_host *vha = NULL;
854165f4 3824
e315cd28
AC		 3825 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3826 if (host == NULL) {
7c3df132
SK		 3827 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3828 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3829 goto fail;
3830 }
3831
3832 /* Clear our data area */
3833 vha = shost_priv(host);
3834 memset(vha, 0, sizeof(scsi_qla_host_t));
3835
3836 vha->host = host;
3837 vha->host_no = host->host_no;
3838 vha->hw = ha;
3839
3840 INIT_LIST_HEAD(&vha->vp_fcports);
3841 INIT_LIST_HEAD(&vha->work_list);
3842 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 3843 INIT_LIST_HEAD(&vha->qla_cmd_list);
3844 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
e315cd28 3845
f999f4c1 3846 spin_lock_init(&vha->work_lock);
8b2f5ff3 3847 spin_lock_init(&vha->cmd_list_lock);
f999f4c1 3848
e315cd28 3849 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3850 ql_dbg(ql_dbg_init, vha, 0x0041,
3851 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3852 vha->host, vha->hw, vha,
3853 dev_name(&(ha->pdev->dev)));
3854
e315cd28
AC		 3855 return vha;
3856
3857fail:
3858 return vha;
1da177e4
LT		 3859}
3860
01ef66bb 3861static struct qla_work_evt *
f999f4c1 3862qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3863{
3864 struct qla_work_evt *e;
feafb7b1
AE		 3865 uint8_t bail;
3866
3867 QLA_VHA_MARK_BUSY(vha, bail);
3868 if (bail)
3869 return NULL;
0971de7f 3870
f999f4c1 3871 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3872 if (!e) {
3873 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3874 return NULL;
feafb7b1 3875 }
0971de7f
AV		 3876
3877 INIT_LIST_HEAD(&e->list);
3878 e->type = type;
3879 e->flags = QLA_EVT_FLAG_FREE;
3880 return e;
3881}
3882
01ef66bb 3883static int
f999f4c1 3884qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3885{
f999f4c1 3886 unsigned long flags;
0971de7f 3887
f999f4c1 3888 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3889 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3890 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3891 qla2xxx_wake_dpc(vha);
f999f4c1 3892
0971de7f
AV		 3893 return QLA_SUCCESS;
3894}
3895
3896int
e315cd28 3897qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3898 u32 data)
3899{
3900 struct qla_work_evt *e;
3901
f999f4c1 3902 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3903 if (!e)
3904 return QLA_FUNCTION_FAILED;
3905
3906 e->u.aen.code = code;
3907 e->u.aen.data = data;
f999f4c1 3908 return qla2x00_post_work(vha, e);
0971de7f
AV		 3909}
3910
8a659571
AV		 3911int
3912qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3913{
3914 struct qla_work_evt *e;
3915
f999f4c1 3916 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3917 if (!e)
3918 return QLA_FUNCTION_FAILED;
3919
3920 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3921 return qla2x00_post_work(vha, e);
8a659571
AV		 3922}
3923
ac280b67
AV		 3924#define qla2x00_post_async_work(name, type) \
3925int qla2x00_post_async_##name##_work( \
3926 struct scsi_qla_host *vha, \
3927 fc_port_t *fcport, uint16_t *data) \
3928{ \
3929 struct qla_work_evt *e; \
3930 \
3931 e = qla2x00_alloc_work(vha, type); \
3932 if (!e) \
3933 return QLA_FUNCTION_FAILED; \
3934 \
3935 e->u.logio.fcport = fcport; \
3936 if (data) { \
3937 e->u.logio.data[0] = data[0]; \
3938 e->u.logio.data[1] = data[1]; \
3939 } \
3940 return qla2x00_post_work(vha, e); \
3941}
3942
3943qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3944qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3945qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3946qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3947qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3948qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3949
3420d36c
AV		 3950int
3951qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3952{
3953 struct qla_work_evt *e;
3954
3955 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3956 if (!e)
3957 return QLA_FUNCTION_FAILED;
3958
3959 e->u.uevent.code = code;
3960 return qla2x00_post_work(vha, e);
3961}
3962
3963static void
3964qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3965{
3966 char event_string[40];
3967 char *envp[] = { event_string, NULL };
3968
3969 switch (code) {
3970 case QLA_UEVENT_CODE_FW_DUMP:
3971 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3972 vha->host_no);
3973 break;
3974 default:
3975 /* do nothing */
3976 break;
3977 }
3978 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3979}
3980
8ae6d9c7
GM		 3981int
3982qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3983 uint32_t *data, int cnt)
3984{
3985 struct qla_work_evt *e;
3986
3987 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3988 if (!e)
3989 return QLA_FUNCTION_FAILED;
3990
3991 e->u.aenfx.evtcode = evtcode;
3992 e->u.aenfx.count = cnt;
3993 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3994 return qla2x00_post_work(vha, e);
3995}
3996
ac280b67 3997void
e315cd28 3998qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3999{
f999f4c1
AV		 4000 struct qla_work_evt *e, *tmp;
4001 unsigned long flags;
4002 LIST_HEAD(work);
0971de7f 4003
f999f4c1
AV		 4004 spin_lock_irqsave(&vha->work_lock, flags);
4005 list_splice_init(&vha->work_list, &work);
4006 spin_unlock_irqrestore(&vha->work_lock, flags);
4007
4008 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4009 list_del_init(&e->list);
0971de7f
AV		 4010
4011 switch (e->type) {
4012 case QLA_EVT_AEN:
e315cd28 4013 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4014 e->u.aen.code, e->u.aen.data);
4015 break;
8a659571
AV		 4016 case QLA_EVT_IDC_ACK:
4017 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4018 break;
ac280b67
AV		 4019 case QLA_EVT_ASYNC_LOGIN:
4020 qla2x00_async_login(vha, e->u.logio.fcport,
4021 e->u.logio.data);
4022 break;
4023 case QLA_EVT_ASYNC_LOGIN_DONE:
4024 qla2x00_async_login_done(vha, e->u.logio.fcport,
4025 e->u.logio.data);
4026 break;
4027 case QLA_EVT_ASYNC_LOGOUT:
4028 qla2x00_async_logout(vha, e->u.logio.fcport);
4029 break;
4030 case QLA_EVT_ASYNC_LOGOUT_DONE:
4031 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4032 e->u.logio.data);
4033 break;
5ff1d584
AV		 4034 case QLA_EVT_ASYNC_ADISC:
4035 qla2x00_async_adisc(vha, e->u.logio.fcport,
4036 e->u.logio.data);
4037 break;
4038 case QLA_EVT_ASYNC_ADISC_DONE:
4039 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4040 e->u.logio.data);
4041 break;
3420d36c
AV		 4042 case QLA_EVT_UEVENT:
4043 qla2x00_uevent_emit(vha, e->u.uevent.code);
4044 break;
8ae6d9c7
GM		 4045 case QLA_EVT_AENFX:
4046 qlafx00_process_aen(vha, e);
4047 break;
0971de7f
AV		 4048 }
4049 if (e->flags & QLA_EVT_FLAG_FREE)
4050 kfree(e);
feafb7b1
AE		 4051
4052 /* For each work completed decrement vha ref count */
4053 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4054 }
e315cd28 4055}
f999f4c1 4056
e315cd28
AC		 4057/* Relogins all the fcports of a vport
4058 * Context: dpc thread
4059 */
4060void qla2x00_relogin(struct scsi_qla_host *vha)
4061{
4062 fc_port_t *fcport;
c6b2fca8 4063 int status;
e315cd28
AC		 4064 uint16_t next_loopid = 0;
4065 struct qla_hw_data *ha = vha->hw;
ac280b67 4066 uint16_t data[2];
e315cd28
AC		 4067
4068 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4069 /*
4070 * If the port is not ONLINE then try to login
4071 * to it if we haven't run out of retries.
4072 */
5ff1d584
AV		 4073 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4074 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4075 fcport->login_retry--;
e315cd28 4076 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4077 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4078 ha->isp_ops->fabric_logout(vha,
4079 fcport->loop_id,
4080 fcport->d_id.b.domain,
4081 fcport->d_id.b.area,
4082 fcport->d_id.b.al_pa);
4083
03bcfb57
JC		 4084 if (fcport->loop_id == FC_NO_LOOP_ID) {
4085 fcport->loop_id = next_loopid =
4086 ha->min_external_loopid;
4087 status = qla2x00_find_new_loop_id(
4088 vha, fcport);
4089 if (status != QLA_SUCCESS) {
4090 /* Ran out of IDs to use */
4091 break;
4092 }
4093 }
4094
ac280b67 4095 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4096 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4097 data[0] = 0;
4098 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4099 status = qla2x00_post_async_login_work(
4100 vha, fcport, data);
4101 if (status == QLA_SUCCESS)
4102 continue;
4103 /* Attempt a retry. */
4104 status = 1;
aaf4d3e2 4105 } else {
ac280b67
AV		 4106 status = qla2x00_fabric_login(vha,
4107 fcport, &next_loopid);
aaf4d3e2
SK		 4108 if (status == QLA_SUCCESS) {
4109 int status2;
4110 uint8_t opts;
4111
4112 opts = 0;
4113 if (fcport->flags &
4114 FCF_FCP2_DEVICE)
4115 opts |= BIT_1;
03003960
SK		 4116 status2 =
4117 qla2x00_get_port_database(
4118 vha, fcport, opts);
aaf4d3e2
SK		 4119 if (status2 != QLA_SUCCESS)
4120 status = 1;
4121 }
4122 }
e315cd28
AC		 4123 } else
4124 status = qla2x00_local_device_login(vha,
4125 fcport);
4126
e315cd28
AC		 4127 if (status == QLA_SUCCESS) {
4128 fcport->old_loop_id = fcport->loop_id;
4129
7c3df132
SK		 4130 ql_dbg(ql_dbg_disc, vha, 0x2003,
4131 "Port login OK: logged in ID 0x%x.\n",
4132 fcport->loop_id);
e315cd28
AC		 4133
4134 qla2x00_update_fcport(vha, fcport);
4135
4136 } else if (status == 1) {
4137 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4138 /* retry the login again */
7c3df132
SK		 4139 ql_dbg(ql_dbg_disc, vha, 0x2007,
4140 "Retrying %d login again loop_id 0x%x.\n",
4141 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4142 } else {
4143 fcport->login_retry = 0;
4144 }
4145
4146 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4147 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4148 }
4149 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4150 break;
0971de7f 4151 }
0971de7f
AV		 4152}
4153
7d613ac6
SV		 4154/* Schedule work on any of the dpc-workqueues */
4155void
4156qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4157{
4158 struct qla_hw_data *ha = base_vha->hw;
4159
4160 switch (work_code) {
4161 case MBA_IDC_AEN: /* 0x8200 */
4162 if (ha->dpc_lp_wq)
4163 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4164 break;
4165
4166 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4167 if (!ha->flags.nic_core_reset_hdlr_active) {
4168 if (ha->dpc_hp_wq)
4169 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4170 } else
4171 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4172 "NIC Core reset is already active. Skip "
4173 "scheduling it again.\n");
4174 break;
4175 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4176 if (ha->dpc_hp_wq)
4177 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4178 break;
4179 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4180 if (ha->dpc_hp_wq)
4181 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4182 break;
4183 default:
4184 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4185 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4186 }
4187
4188 return;
4189}
4190
4191/* Work: Perform NIC Core Unrecoverable state handling */
4192void
4193qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4194{
4195 struct qla_hw_data *ha =
2ad1b67c 4196 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4197 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4198 uint32_t dev_state = 0;
4199
4200 qla83xx_idc_lock(base_vha, 0);
4201 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4202 qla83xx_reset_ownership(base_vha);
4203 if (ha->flags.nic_core_reset_owner) {
4204 ha->flags.nic_core_reset_owner = 0;
4205 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4206 QLA8XXX_DEV_FAILED);
4207 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4208 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4209 }
4210 qla83xx_idc_unlock(base_vha, 0);
4211}
4212
4213/* Work: Execute IDC state handler */
4214void
4215qla83xx_idc_state_handler_work(struct work_struct *work)
4216{
4217 struct qla_hw_data *ha =
2ad1b67c 4218 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4219 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4220 uint32_t dev_state = 0;
4221
4222 qla83xx_idc_lock(base_vha, 0);
4223 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4224 if (dev_state == QLA8XXX_DEV_FAILED ||
4225 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4226 qla83xx_idc_state_handler(base_vha);
4227 qla83xx_idc_unlock(base_vha, 0);
4228}
4229
fa492630 4230static int
7d613ac6
SV		 4231qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4232{
4233 int rval = QLA_SUCCESS;
4234 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4235 uint32_t heart_beat_counter1, heart_beat_counter2;
4236
4237 do {
4238 if (time_after(jiffies, heart_beat_wait)) {
4239 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4240 "Nic Core f/w is not alive.\n");
4241 rval = QLA_FUNCTION_FAILED;
4242 break;
4243 }
4244
4245 qla83xx_idc_lock(base_vha, 0);
4246 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4247 &heart_beat_counter1);
4248 qla83xx_idc_unlock(base_vha, 0);
4249 msleep(100);
4250 qla83xx_idc_lock(base_vha, 0);
4251 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4252 &heart_beat_counter2);
4253 qla83xx_idc_unlock(base_vha, 0);
4254 } while (heart_beat_counter1 == heart_beat_counter2);
4255
4256 return rval;
4257}
4258
4259/* Work: Perform NIC Core Reset handling */
4260void
4261qla83xx_nic_core_reset_work(struct work_struct *work)
4262{
4263 struct qla_hw_data *ha =
4264 container_of(work, struct qla_hw_data, nic_core_reset);
4265 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4266 uint32_t dev_state = 0;
4267
81178772
SK		 4268 if (IS_QLA2031(ha)) {
4269 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4270 ql_log(ql_log_warn, base_vha, 0xb081,
4271 "Failed to dump mctp\n");
4272 return;
4273 }
4274
7d613ac6
SV		 4275 if (!ha->flags.nic_core_reset_hdlr_active) {
4276 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4277 qla83xx_idc_lock(base_vha, 0);
4278 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4279 &dev_state);
4280 qla83xx_idc_unlock(base_vha, 0);
4281 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4282 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4283 "Nic Core f/w is alive.\n");
4284 return;
4285 }
4286 }
4287
4288 ha->flags.nic_core_reset_hdlr_active = 1;
4289 if (qla83xx_nic_core_reset(base_vha)) {
4290 /* NIC Core reset failed. */
4291 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4292 "NIC Core reset failed.\n");
4293 }
4294 ha->flags.nic_core_reset_hdlr_active = 0;
4295 }
4296}
4297
4298/* Work: Handle 8200 IDC aens */
4299void
4300qla83xx_service_idc_aen(struct work_struct *work)
4301{
4302 struct qla_hw_data *ha =
4303 container_of(work, struct qla_hw_data, idc_aen);
4304 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4305 uint32_t dev_state, idc_control;
4306
4307 qla83xx_idc_lock(base_vha, 0);
4308 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4309 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4310 qla83xx_idc_unlock(base_vha, 0);
4311 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4312 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4313 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4314 "Application requested NIC Core Reset.\n");
4315 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4316 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4317 QLA_SUCCESS) {
4318 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4319 "Other protocol driver requested NIC Core Reset.\n");
4320 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4321 }
4322 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4323 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4324 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4325 }
4326}
4327
4328static void
4329qla83xx_wait_logic(void)
4330{
4331 int i;
4332
4333 /* Yield CPU */
4334 if (!in_interrupt()) {
4335 /*
4336 * Wait about 200ms before retrying again.
4337 * This controls the number of retries for single
4338 * lock operation.
4339 */
4340 msleep(100);
4341 schedule();
4342 } else {
4343 for (i = 0; i < 20; i++)
4344 cpu_relax(); /* This a nop instr on i386 */
4345 }
4346}
4347
fa492630 4348static int
7d613ac6
SV		 4349qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4350{
4351 int rval;
4352 uint32_t data;
4353 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4354 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4355 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4356 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4357 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4358
4359 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4360 if (rval)
4361 return rval;
4362
4363 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4364 return QLA_SUCCESS;
4365 } else {
4366 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4367 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4368 data);
4369 if (rval)
4370 return rval;
4371
4372 msleep(200);
4373
4374 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4375 &data);
4376 if (rval)
4377 return rval;
4378
4379 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4380 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4381 ~(idc_lck_rcvry_stage_mask));
4382 rval = qla83xx_wr_reg(base_vha,
4383 QLA83XX_IDC_LOCK_RECOVERY, data);
4384 if (rval)
4385 return rval;
4386
4387 /* Forcefully perform IDC UnLock */
4388 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4389 &data);
4390 if (rval)
4391 return rval;
4392 /* Clear lock-id by setting 0xff */
4393 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4394 0xff);
4395 if (rval)
4396 return rval;
4397 /* Clear lock-recovery by setting 0x0 */
4398 rval = qla83xx_wr_reg(base_vha,
4399 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4400 if (rval)
4401 return rval;
4402 } else
4403 return QLA_SUCCESS;
4404 }
4405
4406 return rval;
4407}
4408
fa492630 4409static int
7d613ac6
SV		 4410qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4411{
4412 int rval = QLA_SUCCESS;
4413 uint32_t o_drv_lockid, n_drv_lockid;
4414 unsigned long lock_recovery_timeout;
4415
4416 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4417retry_lockid:
4418 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4419 if (rval)
4420 goto exit;
4421
4422 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4423 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4424 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4425 return QLA_SUCCESS;
4426 else
4427 return QLA_FUNCTION_FAILED;
4428 }
4429
4430 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4431 if (rval)
4432 goto exit;
4433
4434 if (o_drv_lockid == n_drv_lockid) {
4435 qla83xx_wait_logic();
4436 goto retry_lockid;
4437 } else
4438 return QLA_SUCCESS;
4439
4440exit:
4441 return rval;
4442}
4443
4444void
4445qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4446{
4447 uint16_t options = (requester_id << 15) | BIT_6;
4448 uint32_t data;
6c315553 4449 uint32_t lock_owner;
7d613ac6
SV		 4450 struct qla_hw_data *ha = base_vha->hw;
4451
4452 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4453retry_lock:
4454 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4455 == QLA_SUCCESS) {
4456 if (data) {
4457 /* Setting lock-id to our function-number */
4458 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4459 ha->portnum);
4460 } else {
6c315553
SK		 4461 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4462 &lock_owner);
7d613ac6 4463 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4464 "Failed to acquire IDC lock, acquired by %d, "
4465 "retrying...\n", lock_owner);
7d613ac6
SV		 4466
4467 /* Retry/Perform IDC-Lock recovery */
4468 if (qla83xx_idc_lock_recovery(base_vha)
4469 == QLA_SUCCESS) {
4470 qla83xx_wait_logic();
4471 goto retry_lock;
4472 } else
4473 ql_log(ql_log_warn, base_vha, 0xb075,
4474 "IDC Lock recovery FAILED.\n");
4475 }
4476
4477 }
4478
4479 return;
4480
4481 /* XXX: IDC-lock implementation using access-control mbx */
4482retry_lock2:
4483 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4484 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4485 "Failed to acquire IDC lock. retrying...\n");
4486 /* Retry/Perform IDC-Lock recovery */
4487 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4488 qla83xx_wait_logic();
4489 goto retry_lock2;
4490 } else
4491 ql_log(ql_log_warn, base_vha, 0xb076,
4492 "IDC Lock recovery FAILED.\n");
4493 }
4494
4495 return;
4496}
4497
4498void
4499qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4500{
5897cb2f
BVA		 4501#if 0
4502 uint16_t options = (requester_id << 15) | BIT_7;
4503#endif
4504 uint16_t retry;
7d613ac6
SV		 4505 uint32_t data;
4506 struct qla_hw_data *ha = base_vha->hw;
4507
4508 /* IDC-unlock implementation using driver-unlock/lock-id
4509 * remote registers
4510 */
4511 retry = 0;
4512retry_unlock:
4513 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4514 == QLA_SUCCESS) {
4515 if (data == ha->portnum) {
4516 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4517 /* Clearing lock-id by setting 0xff */
4518 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4519 } else if (retry < 10) {
4520 /* SV: XXX: IDC unlock retrying needed here? */
4521
4522 /* Retry for IDC-unlock */
4523 qla83xx_wait_logic();
4524 retry++;
4525 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4526 "Failed to release IDC lock, retyring=%d\n", retry);
4527 goto retry_unlock;
4528 }
4529 } else if (retry < 10) {
4530 /* Retry for IDC-unlock */
4531 qla83xx_wait_logic();
4532 retry++;
4533 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4534 "Failed to read drv-lockid, retyring=%d\n", retry);
4535 goto retry_unlock;
4536 }
4537
4538 return;
4539
5897cb2f 4540#if 0
7d613ac6
SV		 4541 /* XXX: IDC-unlock implementation using access-control mbx */
4542 retry = 0;
4543retry_unlock2:
4544 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4545 if (retry < 10) {
4546 /* Retry for IDC-unlock */
4547 qla83xx_wait_logic();
4548 retry++;
4549 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4550 "Failed to release IDC lock, retyring=%d\n", retry);
4551 goto retry_unlock2;
4552 }
4553 }
4554
4555 return;
5897cb2f 4556#endif
7d613ac6
SV		 4557}
4558
4559int
4560__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4561{
4562 int rval = QLA_SUCCESS;
4563 struct qla_hw_data *ha = vha->hw;
4564 uint32_t drv_presence;
4565
4566 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4567 if (rval == QLA_SUCCESS) {
4568 drv_presence |= (1 << ha->portnum);
4569 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4570 drv_presence);
4571 }
4572
4573 return rval;
4574}
4575
4576int
4577qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4578{
4579 int rval = QLA_SUCCESS;
4580
4581 qla83xx_idc_lock(vha, 0);
4582 rval = __qla83xx_set_drv_presence(vha);
4583 qla83xx_idc_unlock(vha, 0);
4584
4585 return rval;
4586}
4587
4588int
4589__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4590{
4591 int rval = QLA_SUCCESS;
4592 struct qla_hw_data *ha = vha->hw;
4593 uint32_t drv_presence;
4594
4595 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4596 if (rval == QLA_SUCCESS) {
4597 drv_presence &= ~(1 << ha->portnum);
4598 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4599 drv_presence);
4600 }
4601
4602 return rval;
4603}
4604
4605int
4606qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4607{
4608 int rval = QLA_SUCCESS;
4609
4610 qla83xx_idc_lock(vha, 0);
4611 rval = __qla83xx_clear_drv_presence(vha);
4612 qla83xx_idc_unlock(vha, 0);
4613
4614 return rval;
4615}
4616
fa492630 4617static void
7d613ac6
SV		 4618qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4619{
4620 struct qla_hw_data *ha = vha->hw;
4621 uint32_t drv_ack, drv_presence;
4622 unsigned long ack_timeout;
4623
4624 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4625 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4626 while (1) {
4627 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4628 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4629 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4630 break;
4631
4632 if (time_after_eq(jiffies, ack_timeout)) {
4633 ql_log(ql_log_warn, vha, 0xb067,
4634 "RESET ACK TIMEOUT! drv_presence=0x%x "
4635 "drv_ack=0x%x\n", drv_presence, drv_ack);
4636 /*
4637 * The function(s) which did not ack in time are forced
4638 * to withdraw any further participation in the IDC
4639 * reset.
4640 */
4641 if (drv_ack != drv_presence)
4642 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4643 drv_ack);
4644 break;
4645 }
4646
4647 qla83xx_idc_unlock(vha, 0);
4648 msleep(1000);
4649 qla83xx_idc_lock(vha, 0);
4650 }
4651
4652 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4653 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4654}
4655
fa492630 4656static int
7d613ac6
SV		 4657qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4658{
4659 int rval = QLA_SUCCESS;
4660 uint32_t idc_control;
4661
4662 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4663 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4664
4665 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4666 __qla83xx_get_idc_control(vha, &idc_control);
4667 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4668 __qla83xx_set_idc_control(vha, 0);
4669
4670 qla83xx_idc_unlock(vha, 0);
4671 rval = qla83xx_restart_nic_firmware(vha);
4672 qla83xx_idc_lock(vha, 0);
4673
4674 if (rval != QLA_SUCCESS) {
4675 ql_log(ql_log_fatal, vha, 0xb06a,
4676 "Failed to restart NIC f/w.\n");
4677 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4678 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4679 } else {
4680 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4681 "Success in restarting nic f/w.\n");
4682 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4683 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4684 }
4685
4686 return rval;
4687}
4688
4689/* Assumes idc_lock always held on entry */
4690int
4691qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4692{
4693 struct qla_hw_data *ha = base_vha->hw;
4694 int rval = QLA_SUCCESS;
4695 unsigned long dev_init_timeout;
4696 uint32_t dev_state;
4697
4698 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4699 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4700
4701 while (1) {
4702
4703 if (time_after_eq(jiffies, dev_init_timeout)) {
4704 ql_log(ql_log_warn, base_vha, 0xb06e,
4705 "Initialization TIMEOUT!\n");
4706 /* Init timeout. Disable further NIC Core
4707 * communication.
4708 */
4709 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4710 QLA8XXX_DEV_FAILED);
4711 ql_log(ql_log_info, base_vha, 0xb06f,
4712 "HW State: FAILED.\n");
4713 }
4714
4715 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4716 switch (dev_state) {
4717 case QLA8XXX_DEV_READY:
4718 if (ha->flags.nic_core_reset_owner)
4719 qla83xx_idc_audit(base_vha,
4720 IDC_AUDIT_COMPLETION);
4721 ha->flags.nic_core_reset_owner = 0;
4722 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4723 "Reset_owner reset by 0x%x.\n",
4724 ha->portnum);
4725 goto exit;
4726 case QLA8XXX_DEV_COLD:
4727 if (ha->flags.nic_core_reset_owner)
4728 rval = qla83xx_device_bootstrap(base_vha);
4729 else {
4730 /* Wait for AEN to change device-state */
4731 qla83xx_idc_unlock(base_vha, 0);
4732 msleep(1000);
4733 qla83xx_idc_lock(base_vha, 0);
4734 }
4735 break;
4736 case QLA8XXX_DEV_INITIALIZING:
4737 /* Wait for AEN to change device-state */
4738 qla83xx_idc_unlock(base_vha, 0);
4739 msleep(1000);
4740 qla83xx_idc_lock(base_vha, 0);
4741 break;
4742 case QLA8XXX_DEV_NEED_RESET:
4743 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4744 qla83xx_need_reset_handler(base_vha);
4745 else {
4746 /* Wait for AEN to change device-state */
4747 qla83xx_idc_unlock(base_vha, 0);
4748 msleep(1000);
4749 qla83xx_idc_lock(base_vha, 0);
4750 }
4751 /* reset timeout value after need reset handler */
4752 dev_init_timeout = jiffies +
4753 (ha->fcoe_dev_init_timeout * HZ);
4754 break;
4755 case QLA8XXX_DEV_NEED_QUIESCENT:
4756 /* XXX: DEBUG for now */
4757 qla83xx_idc_unlock(base_vha, 0);
4758 msleep(1000);
4759 qla83xx_idc_lock(base_vha, 0);
4760 break;
4761 case QLA8XXX_DEV_QUIESCENT:
4762 /* XXX: DEBUG for now */
4763 if (ha->flags.quiesce_owner)
4764 goto exit;
4765
4766 qla83xx_idc_unlock(base_vha, 0);
4767 msleep(1000);
4768 qla83xx_idc_lock(base_vha, 0);
4769 dev_init_timeout = jiffies +
4770 (ha->fcoe_dev_init_timeout * HZ);
4771 break;
4772 case QLA8XXX_DEV_FAILED:
4773 if (ha->flags.nic_core_reset_owner)
4774 qla83xx_idc_audit(base_vha,
4775 IDC_AUDIT_COMPLETION);
4776 ha->flags.nic_core_reset_owner = 0;
4777 __qla83xx_clear_drv_presence(base_vha);
4778 qla83xx_idc_unlock(base_vha, 0);
4779 qla8xxx_dev_failed_handler(base_vha);
4780 rval = QLA_FUNCTION_FAILED;
4781 qla83xx_idc_lock(base_vha, 0);
4782 goto exit;
4783 case QLA8XXX_BAD_VALUE:
4784 qla83xx_idc_unlock(base_vha, 0);
4785 msleep(1000);
4786 qla83xx_idc_lock(base_vha, 0);
4787 break;
4788 default:
4789 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 4790 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 4791 qla83xx_idc_unlock(base_vha, 0);
4792 qla8xxx_dev_failed_handler(base_vha);
4793 rval = QLA_FUNCTION_FAILED;
4794 qla83xx_idc_lock(base_vha, 0);
4795 goto exit;
4796 }
4797 }
4798
4799exit:
4800 return rval;
4801}
4802
f3ddac19
CD		 4803void
4804qla2x00_disable_board_on_pci_error(struct work_struct *work)
4805{
4806 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4807 board_disable);
4808 struct pci_dev *pdev = ha->pdev;
4809 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4810
4811 ql_log(ql_log_warn, base_vha, 0x015b,
4812 "Disabling adapter.\n");
4813
4814 set_bit(UNLOADING, &base_vha->dpc_flags);
4815
4816 qla2x00_delete_all_vps(ha, base_vha);
4817
4818 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4819
4820 qla2x00_dfs_remove(base_vha);
4821
4822 qla84xx_put_chip(base_vha);
4823
4824 if (base_vha->timer_active)
4825 qla2x00_stop_timer(base_vha);
4826
4827 base_vha->flags.online = 0;
4828
4829 qla2x00_destroy_deferred_work(ha);
4830
4831 /*
4832 * Do not try to stop beacon blink as it will issue a mailbox
4833 * command.
4834 */
4835 qla2x00_free_sysfs_attr(base_vha, false);
4836
4837 fc_remove_host(base_vha->host);
4838
4839 scsi_remove_host(base_vha->host);
4840
4841 base_vha->flags.init_done = 0;
4842 qla25xx_delete_queues(base_vha);
4843 qla2x00_free_irqs(base_vha);
4844 qla2x00_free_fcports(base_vha);
4845 qla2x00_mem_free(ha);
4846 qla82xx_md_free(base_vha);
4847 qla2x00_free_queues(ha);
4848
f3ddac19
CD		 4849 qla2x00_unmap_iobases(ha);
4850
4851 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 4852 pci_disable_pcie_error_reporting(pdev);
4853 pci_disable_device(pdev);
f3ddac19 4854
beb9e315
JL		 4855 /*
4856 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
4857 */
f3ddac19
CD		 4858}
4859
1da177e4
LT		 4860/**************************************************************************
4861* qla2x00_do_dpc
4862* This kernel thread is a task that is schedule by the interrupt handler
4863* to perform the background processing for interrupts.
4864*
4865* Notes:
4866* This task always run in the context of a kernel thread. It
4867* is kick-off by the driver's detect code and starts up
4868* up one per adapter. It immediately goes to sleep and waits for
4869* some fibre event. When either the interrupt handler or
4870* the timer routine detects a event it will one of the task
4871* bits then wake us up.
4872**************************************************************************/
4873static int
4874qla2x00_do_dpc(void *data)
4875{
e315cd28
AC		 4876 scsi_qla_host_t *base_vha;
4877 struct qla_hw_data *ha;
1da177e4 4878
e315cd28
AC		 4879 ha = (struct qla_hw_data *)data;
4880 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4881
8698a745 4882 set_user_nice(current, MIN_NICE);
1da177e4 4883
563585ec 4884 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4885 while (!kthread_should_stop()) {
7c3df132
SK		 4886 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4887 "DPC handler sleeping.\n");
1da177e4 4888
39a11240 4889 schedule();
1da177e4 4890
c142caf0
AV		 4891 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4892 goto end_loop;
1da177e4 4893
85880801 4894 if (ha->flags.eeh_busy) {
7c3df132
SK		 4895 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4896 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4897 goto end_loop;
85880801
AV		 4898 }
4899
1da177e4
LT		 4900 ha->dpc_active = 1;
4901
5f28d2d7
SK		 4902 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4903 "DPC handler waking up, dpc_flags=0x%lx.\n",
4904 base_vha->dpc_flags);
1da177e4 4905
e315cd28 4906 qla2x00_do_work(base_vha);
0971de7f 4907
7ec0effd
AD		 4908 if (IS_P3P_TYPE(ha)) {
4909 if (IS_QLA8044(ha)) {
4910 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4911 &base_vha->dpc_flags)) {
4912 qla8044_idc_lock(ha);
4913 qla8044_wr_direct(base_vha,
4914 QLA8044_CRB_DEV_STATE_INDEX,
4915 QLA8XXX_DEV_FAILED);
4916 qla8044_idc_unlock(ha);
4917 ql_log(ql_log_info, base_vha, 0x4004,
4918 "HW State: FAILED.\n");
4919 qla8044_device_state_handler(base_vha);
4920 continue;
4921 }
4922
4923 } else {
4924 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4925 &base_vha->dpc_flags)) {
4926 qla82xx_idc_lock(ha);
4927 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4928 QLA8XXX_DEV_FAILED);
4929 qla82xx_idc_unlock(ha);
4930 ql_log(ql_log_info, base_vha, 0x0151,
4931 "HW State: FAILED.\n");
4932 qla82xx_device_state_handler(base_vha);
4933 continue;
4934 }
a9083016
GM		 4935 }
4936
4937 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4938 &base_vha->dpc_flags)) {
4939
7c3df132
SK		 4940 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4941 "FCoE context reset scheduled.\n");
a9083016
GM		 4942 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4943 &base_vha->dpc_flags))) {
4944 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4945 /* FCoE-ctx reset failed.
4946 * Escalate to chip-reset
4947 */
4948 set_bit(ISP_ABORT_NEEDED,
4949 &base_vha->dpc_flags);
4950 }
4951 clear_bit(ABORT_ISP_ACTIVE,
4952 &base_vha->dpc_flags);
4953 }
4954
7c3df132
SK		 4955 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4956 "FCoE context reset end.\n");
a9083016 4957 }
8ae6d9c7
GM		 4958 } else if (IS_QLAFX00(ha)) {
4959 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4960 &base_vha->dpc_flags)) {
4961 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4962 "Firmware Reset Recovery\n");
4963 if (qlafx00_reset_initialize(base_vha)) {
4964 /* Failed. Abort isp later. */
4965 if (!test_bit(UNLOADING,
f92f82d6 4966 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 4967 set_bit(ISP_UNRECOVERABLE,
4968 &base_vha->dpc_flags);
4969 ql_dbg(ql_dbg_dpc, base_vha,
4970 0x4021,
4971 "Reset Recovery Failed\n");
f92f82d6 4972 }
8ae6d9c7
GM		 4973 }
4974 }
4975
4976 if (test_and_clear_bit(FX00_TARGET_SCAN,
4977 &base_vha->dpc_flags)) {
4978 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4979 "ISPFx00 Target Scan scheduled\n");
4980 if (qlafx00_rescan_isp(base_vha)) {
4981 if (!test_bit(UNLOADING,
4982 &base_vha->dpc_flags))
4983 set_bit(ISP_UNRECOVERABLE,
4984 &base_vha->dpc_flags);
4985 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4986 "ISPFx00 Target Scan Failed\n");
4987 }
4988 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4989 "ISPFx00 Target Scan End\n");
4990 }
e8f5e95d
AB		 4991 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4992 &base_vha->dpc_flags)) {
4993 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4994 "ISPFx00 Host Info resend scheduled\n");
4995 qlafx00_fx_disc(base_vha,
4996 &base_vha->hw->mr.fcport,
4997 FXDISC_REG_HOST_INFO);
4998 }
a9083016
GM		 4999 }
5000
e315cd28
AC		 5001 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5002 &base_vha->dpc_flags)) {
1da177e4 5003
7c3df132
SK		 5004 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5005 "ISP abort scheduled.\n");
1da177e4 5006 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5007 &base_vha->dpc_flags))) {
1da177e4 5008
a9083016 5009 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5010 /* failed. retry later */
5011 set_bit(ISP_ABORT_NEEDED,
e315cd28 5012 &base_vha->dpc_flags);
99363ef8 5013 }
e315cd28
AC		 5014 clear_bit(ABORT_ISP_ACTIVE,
5015 &base_vha->dpc_flags);
99363ef8
SJ		 5016 }
5017
7c3df132
SK		 5018 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5019 "ISP abort end.\n");
1da177e4
LT		 5020 }
5021
a394aac8
DJ		 5022 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5023 &base_vha->dpc_flags)) {
e315cd28 5024 qla2x00_update_fcports(base_vha);
c9c5ced9 5025 }
d97994dc 5026
2d70c103
NB		 5027 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
5028 int ret;
5029 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
5030 if (ret != QLA_SUCCESS)
5031 ql_log(ql_log_warn, base_vha, 0x121,
5032 "Failed to enable receiving of RSCN "
5033 "requests: 0x%x.\n", ret);
5034 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
5035 }
5036
8ae6d9c7
GM		 5037 if (IS_QLAFX00(ha))
5038 goto loop_resync_check;
5039
579d12b5 5040 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5041 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5042 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5043 if (IS_P3P_TYPE(ha)) {
5044 if (IS_QLA82XX(ha))
5045 qla82xx_device_state_handler(base_vha);
5046 if (IS_QLA8044(ha))
5047 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5048 clear_bit(ISP_QUIESCE_NEEDED,
5049 &base_vha->dpc_flags);
5050 if (!ha->flags.quiesce_owner) {
5051 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5052 if (IS_QLA82XX(ha)) {
5053 qla82xx_idc_lock(ha);
5054 qla82xx_clear_qsnt_ready(
5055 base_vha);
5056 qla82xx_idc_unlock(ha);
5057 } else if (IS_QLA8044(ha)) {
5058 qla8044_idc_lock(ha);
5059 qla8044_clear_qsnt_ready(
5060 base_vha);
5061 qla8044_idc_unlock(ha);
5062 }
8fcd6b8b
CD		 5063 }
5064 } else {
5065 clear_bit(ISP_QUIESCE_NEEDED,
5066 &base_vha->dpc_flags);
5067 qla2x00_quiesce_io(base_vha);
579d12b5 5068 }
7c3df132
SK		 5069 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5070 "Quiescence mode end.\n");
579d12b5
SK		 5071 }
5072
e315cd28 5073 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5074 &base_vha->dpc_flags) &&
e315cd28 5075 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5076
7c3df132
SK		 5077 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5078 "Reset marker scheduled.\n");
e315cd28
AC		 5079 qla2x00_rst_aen(base_vha);
5080 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5081 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5082 "Reset marker end.\n");
1da177e4
LT		 5083 }
5084
5085 /* Retry each device up to login retry count */
e315cd28
AC		 5086 if ((test_and_clear_bit(RELOGIN_NEEDED,
5087 &base_vha->dpc_flags)) &&
5088 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5089 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5090
7c3df132
SK		 5091 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5092 "Relogin scheduled.\n");
e315cd28 5093 qla2x00_relogin(base_vha);
7c3df132
SK		 5094 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5095 "Relogin end.\n");
1da177e4 5096 }
8ae6d9c7 5097loop_resync_check:
e315cd28 5098 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5099 &base_vha->dpc_flags)) {
1da177e4 5100
7c3df132
SK		 5101 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5102 "Loop resync scheduled.\n");
1da177e4
LT		 5103
5104 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5105 &base_vha->dpc_flags))) {
1da177e4 5106
52c82823 5107 qla2x00_loop_resync(base_vha);
1da177e4 5108
e315cd28
AC		 5109 clear_bit(LOOP_RESYNC_ACTIVE,
5110 &base_vha->dpc_flags);
1da177e4
LT		 5111 }
5112
7c3df132
SK		 5113 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5114 "Loop resync end.\n");
1da177e4
LT		 5115 }
5116
8ae6d9c7
GM		 5117 if (IS_QLAFX00(ha))
5118 goto intr_on_check;
5119
e315cd28
AC		 5120 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5121 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5122 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5123 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5124 }
5125
8ae6d9c7 5126intr_on_check:
1da177e4 5127 if (!ha->interrupts_on)
fd34f556 5128 ha->isp_ops->enable_intrs(ha);
1da177e4 5129
e315cd28 5130 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5131 &base_vha->dpc_flags)) {
5132 if (ha->beacon_blink_led == 1)
5133 ha->isp_ops->beacon_blink(base_vha);
5134 }
f6df144c 5135
8ae6d9c7
GM		 5136 if (!IS_QLAFX00(ha))
5137 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5138
1da177e4 5139 ha->dpc_active = 0;
c142caf0 5140end_loop:
563585ec 5141 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5142 } /* End of while(1) */
563585ec 5143 __set_current_state(TASK_RUNNING);
1da177e4 5144
7c3df132
SK		 5145 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5146 "DPC handler exiting.\n");
1da177e4
LT		 5147
5148 /*
5149 * Make sure that nobody tries to wake us up again.
5150 */
1da177e4
LT		 5151 ha->dpc_active = 0;
5152
ac280b67
AV		 5153 /* Cleanup any residual CTX SRBs. */
5154 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5155
39a11240
CH		 5156 return 0;
5157}
5158
5159void
e315cd28 5160qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5161{
e315cd28 5162 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5163 struct task_struct *t = ha->dpc_thread;
5164
e315cd28 5165 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5166 wake_up_process(t);
1da177e4
LT		 5167}
5168
1da177e4
LT		 5169/*
5170* qla2x00_rst_aen
5171* Processes asynchronous reset.
5172*
5173* Input:
5174* ha = adapter block pointer.
5175*/
5176static void
e315cd28 5177qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5178{
e315cd28
AC		 5179 if (vha->flags.online && !vha->flags.reset_active &&
5180 !atomic_read(&vha->loop_down_timer) &&
5181 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5182 do {
e315cd28 5183 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5184
5185 /*
5186 * Issue marker command only when we are going to start
5187 * the I/O.
5188 */
e315cd28
AC		 5189 vha->marker_needed = 1;
5190 } while (!atomic_read(&vha->loop_down_timer) &&
5191 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5192 }
5193}
5194
1da177e4
LT		 5195/**************************************************************************
5196* qla2x00_timer
5197*
5198* Description:
5199* One second timer
5200*
5201* Context: Interrupt
5202***************************************************************************/
2c3dfe3f 5203void
e315cd28 5204qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5205{
1da177e4 5206 unsigned long cpu_flags = 0;
1da177e4
LT		 5207 int start_dpc = 0;
5208 int index;
5209 srb_t *sp;
85880801 5210 uint16_t w;
e315cd28 5211 struct qla_hw_data *ha = vha->hw;
73208dfd 5212 struct req_que *req;
85880801 5213
a5b36321 5214 if (ha->flags.eeh_busy) {
7c3df132
SK		 5215 ql_dbg(ql_dbg_timer, vha, 0x6000,
5216 "EEH = %d, restarting timer.\n",
5217 ha->flags.eeh_busy);
a5b36321
LC		 5218 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5219 return;
5220 }
5221
f3ddac19
CD		 5222 /*
5223 * Hardware read to raise pending EEH errors during mailbox waits. If
5224 * the read returns -1 then disable the board.
5225 */
5226 if (!pci_channel_offline(ha->pdev)) {
85880801 5227 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5228 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5229 }
1da177e4 5230
cefcaba6 5231 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5232 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5233 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5234 start_dpc++;
7ec0effd
AD		 5235 if (IS_QLA82XX(ha))
5236 qla82xx_watchdog(vha);
5237 else if (IS_QLA8044(ha))
5238 qla8044_watchdog(vha);
579d12b5
SK		 5239 }
5240
8ae6d9c7
GM		 5241 if (!vha->vp_idx && IS_QLAFX00(ha))
5242 qlafx00_timer_routine(vha);
5243
1da177e4 5244 /* Loop down handler. */
e315cd28 5245 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5246 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5247 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5248 && vha->flags.online) {
1da177e4 5249
e315cd28
AC		 5250 if (atomic_read(&vha->loop_down_timer) ==
5251 vha->loop_down_abort_time) {
1da177e4 5252
7c3df132
SK		 5253 ql_log(ql_log_info, vha, 0x6008,
5254 "Loop down - aborting the queues before time expires.\n");
1da177e4 5255
e315cd28
AC		 5256 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5257 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5258
f08b7251
AV		 5259 /*
5260 * Schedule an ISP abort to return any FCP2-device
5261 * commands.
5262 */
2c3dfe3f 5263 /* NPIV - scan physical port only */
e315cd28 5264 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5265 spin_lock_irqsave(&ha->hardware_lock,
5266 cpu_flags);
73208dfd 5267 req = ha->req_q_map[0];
2c3dfe3f 5268 for (index = 1;
8d93f550 5269 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5270 index++) {
5271 fc_port_t *sfcp;
5272
e315cd28 5273 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5274 if (!sp)
5275 continue;
9ba56b95 5276 if (sp->type != SRB_SCSI_CMD)
cf53b069 5277 continue;
2c3dfe3f 5278 sfcp = sp->fcport;
f08b7251 5279 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5280 continue;
bdf79621 5281
8f7daead
GM		 5282 if (IS_QLA82XX(ha))
5283 set_bit(FCOE_CTX_RESET_NEEDED,
5284 &vha->dpc_flags);
5285 else
5286 set_bit(ISP_ABORT_NEEDED,
e315cd28 5287 &vha->dpc_flags);
2c3dfe3f
SJ		 5288 break;
5289 }
5290 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5291 cpu_flags);
1da177e4 5292 }
1da177e4
LT		 5293 start_dpc++;
5294 }
5295
5296 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5297 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5298 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5299 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5300 "Loop down - aborting ISP.\n");
5301
8f7daead
GM		 5302 if (IS_QLA82XX(ha))
5303 set_bit(FCOE_CTX_RESET_NEEDED,
5304 &vha->dpc_flags);
5305 else
5306 set_bit(ISP_ABORT_NEEDED,
5307 &vha->dpc_flags);
1da177e4
LT		 5308 }
5309 }
7c3df132
SK		 5310 ql_dbg(ql_dbg_timer, vha, 0x600a,
5311 "Loop down - seconds remaining %d.\n",
5312 atomic_read(&vha->loop_down_timer));
1da177e4 5313 }
cefcaba6
SK		 5314 /* Check if beacon LED needs to be blinked for physical host only */
5315 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5316 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5317 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5318 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5319 start_dpc++;
5320 }
f6df144c 5321 }
5322
550bf57d 5323 /* Process any deferred work. */
e315cd28 5324 if (!list_empty(&vha->work_list))
550bf57d
AV		 5325 start_dpc++;
5326
1da177e4 5327 /* Schedule the DPC routine if needed */
e315cd28
AC		 5328 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5329 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5330 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5331 start_dpc ||
e315cd28
AC		 5332 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5333 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5334 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5335 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5336 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5337 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5338 ql_dbg(ql_dbg_timer, vha, 0x600b,
5339 "isp_abort_needed=%d loop_resync_needed=%d "
5340 "fcport_update_needed=%d start_dpc=%d "
5341 "reset_marker_needed=%d",
5342 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5343 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5344 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5345 start_dpc,
5346 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5347 ql_dbg(ql_dbg_timer, vha, 0x600c,
5348 "beacon_blink_needed=%d isp_unrecoverable=%d "
5349 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5350 "relogin_needed=%d.\n",
7c3df132
SK		 5351 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5352 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5353 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5354 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5355 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5356 qla2xxx_wake_dpc(vha);
7c3df132 5357 }
1da177e4 5358
e315cd28 5359 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5360}
5361
5433383e
AV		 5362/* Firmware interface routines. */
5363
f73cb695 5364#define FW_BLOBS 11
5433383e
AV		 5365#define FW_ISP21XX 0
5366#define FW_ISP22XX 1
5367#define FW_ISP2300 2
5368#define FW_ISP2322 3
48c02fde 5369#define FW_ISP24XX 4
c3a2f0df 5370#define FW_ISP25XX 5
3a03eb79 5371#define FW_ISP81XX 6
a9083016 5372#define FW_ISP82XX 7
6246b8a1
GM		 5373#define FW_ISP2031 8
5374#define FW_ISP8031 9
2c5bbbb2 5375#define FW_ISP27XX 10
5433383e 5376
bb8ee499
AV		 5377#define FW_FILE_ISP21XX "ql2100_fw.bin"
5378#define FW_FILE_ISP22XX "ql2200_fw.bin"
5379#define FW_FILE_ISP2300 "ql2300_fw.bin"
5380#define FW_FILE_ISP2322 "ql2322_fw.bin"
5381#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5382#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5383#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5384#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5385#define FW_FILE_ISP2031 "ql2600_fw.bin"
5386#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5387#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5388
bb8ee499 5389
e1e82b6f 5390static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5391
5392static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5393 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5394 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5395 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5396 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5397 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5398 { .name = FW_FILE_ISP25XX, },
3a03eb79 5399 { .name = FW_FILE_ISP81XX, },
a9083016 5400 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5401 { .name = FW_FILE_ISP2031, },
5402 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5403 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5404};
5405
5406struct fw_blob *
e315cd28 5407qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5408{
e315cd28 5409 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5410 struct fw_blob *blob;
5411
5433383e
AV		 5412 if (IS_QLA2100(ha)) {
5413 blob = &qla_fw_blobs[FW_ISP21XX];
5414 } else if (IS_QLA2200(ha)) {
5415 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5416 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5417 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5418 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5419 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5420 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5421 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5422 } else if (IS_QLA25XX(ha)) {
5423 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5424 } else if (IS_QLA81XX(ha)) {
5425 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5426 } else if (IS_QLA82XX(ha)) {
5427 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5428 } else if (IS_QLA2031(ha)) {
5429 blob = &qla_fw_blobs[FW_ISP2031];
5430 } else if (IS_QLA8031(ha)) {
5431 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5432 } else if (IS_QLA27XX(ha)) {
5433 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5434 } else {
5435 return NULL;
5433383e
AV		 5436 }
5437
e1e82b6f 5438 mutex_lock(&qla_fw_lock);
5433383e
AV		 5439 if (blob->fw)
5440 goto out;
5441
5442 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5443 ql_log(ql_log_warn, vha, 0x0063,
5444 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5445 blob->fw = NULL;
5446 blob = NULL;
5447 goto out;
5448 }
5449
5450out:
e1e82b6f 5451 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5452 return blob;
5453}
5454
5455static void
5456qla2x00_release_firmware(void)
5457{
5458 int idx;
5459
e1e82b6f 5460 mutex_lock(&qla_fw_lock);
5433383e 5461 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5462 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5463 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5464}
5465
14e660e6
SJ		 5466static pci_ers_result_t
5467qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5468{
85880801
AV		 5469 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5470 struct qla_hw_data *ha = vha->hw;
5471
7c3df132
SK		 5472 ql_dbg(ql_dbg_aer, vha, 0x9000,
5473 "PCI error detected, state %x.\n", state);
b9b12f73 5474
14e660e6
SJ		 5475 switch (state) {
5476 case pci_channel_io_normal:
85880801 5477 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5478 return PCI_ERS_RESULT_CAN_RECOVER;
5479 case pci_channel_io_frozen:
85880801 5480 ha->flags.eeh_busy = 1;
a5b36321
LC		 5481 /* For ISP82XX complete any pending mailbox cmd */
5482 if (IS_QLA82XX(ha)) {
7190575f 5483 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5484 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5485 qla82xx_clear_pending_mbx(vha);
a5b36321 5486 }
90a86fc0 5487 qla2x00_free_irqs(vha);
14e660e6 5488 pci_disable_device(pdev);
bddd2d65
LC		 5489 /* Return back all IOs */
5490 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5491 return PCI_ERS_RESULT_NEED_RESET;
5492 case pci_channel_io_perm_failure:
85880801
AV		 5493 ha->flags.pci_channel_io_perm_failure = 1;
5494 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5495 return PCI_ERS_RESULT_DISCONNECT;
5496 }
5497 return PCI_ERS_RESULT_NEED_RESET;
5498}
5499
5500static pci_ers_result_t
5501qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5502{
5503 int risc_paused = 0;
5504 uint32_t stat;
5505 unsigned long flags;
e315cd28
AC		 5506 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5507 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5508 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5509 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5510
bcc5b6d3
SK		 5511 if (IS_QLA82XX(ha))
5512 return PCI_ERS_RESULT_RECOVERED;
5513
14e660e6
SJ		 5514 spin_lock_irqsave(&ha->hardware_lock, flags);
5515 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5516 stat = RD_REG_DWORD(&reg->hccr);
5517 if (stat & HCCR_RISC_PAUSE)
5518 risc_paused = 1;
5519 } else if (IS_QLA23XX(ha)) {
5520 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5521 if (stat & HSR_RISC_PAUSED)
5522 risc_paused = 1;
5523 } else if (IS_FWI2_CAPABLE(ha)) {
5524 stat = RD_REG_DWORD(&reg24->host_status);
5525 if (stat & HSRX_RISC_PAUSED)
5526 risc_paused = 1;
5527 }
5528 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5529
5530 if (risc_paused) {
7c3df132
SK		 5531 ql_log(ql_log_info, base_vha, 0x9003,
5532 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5533 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5534
5535 return PCI_ERS_RESULT_NEED_RESET;
5536 } else
5537 return PCI_ERS_RESULT_RECOVERED;
5538}
5539
fa492630
SK		 5540static uint32_t
5541qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5542{
5543 uint32_t rval = QLA_FUNCTION_FAILED;
5544 uint32_t drv_active = 0;
5545 struct qla_hw_data *ha = base_vha->hw;
5546 int fn;
5547 struct pci_dev *other_pdev = NULL;
5548
7c3df132
SK		 5549 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5550 "Entered %s.\n", __func__);
a5b36321
LC		 5551
5552 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5553
5554 if (base_vha->flags.online) {
5555 /* Abort all outstanding commands,
5556 * so as to be requeued later */
5557 qla2x00_abort_isp_cleanup(base_vha);
5558 }
5559
5560
5561 fn = PCI_FUNC(ha->pdev->devfn);
5562 while (fn > 0) {
5563 fn--;
7c3df132
SK		 5564 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5565 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5566 other_pdev =
5567 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5568 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5569 fn));
5570
5571 if (!other_pdev)
5572 continue;
5573 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5574 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5575 "Found PCI func available and enable at 0x%x.\n",
5576 fn);
a5b36321
LC		 5577 pci_dev_put(other_pdev);
5578 break;
5579 }
5580 pci_dev_put(other_pdev);
5581 }
5582
5583 if (!fn) {
5584 /* Reset owner */
7c3df132
SK		 5585 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5586 "This devfn is reset owner = 0x%x.\n",
5587 ha->pdev->devfn);
a5b36321
LC		 5588 qla82xx_idc_lock(ha);
5589
5590 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5591 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5592
5593 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5594 QLA82XX_IDC_VERSION);
5595
5596 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5597 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5598 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5599
5600 qla82xx_idc_unlock(ha);
5601 /* Reset if device is not already reset
5602 * drv_active would be 0 if a reset has already been done
5603 */
5604 if (drv_active)
5605 rval = qla82xx_start_firmware(base_vha);
5606 else
5607 rval = QLA_SUCCESS;
5608 qla82xx_idc_lock(ha);
5609
5610 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5611 ql_log(ql_log_info, base_vha, 0x900b,
5612 "HW State: FAILED.\n");
a5b36321
LC		 5613 qla82xx_clear_drv_active(ha);
5614 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5615 QLA8XXX_DEV_FAILED);
a5b36321 5616 } else {
7c3df132
SK		 5617 ql_log(ql_log_info, base_vha, 0x900c,
5618 "HW State: READY.\n");
a5b36321 5619 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5620 QLA8XXX_DEV_READY);
a5b36321 5621 qla82xx_idc_unlock(ha);
7190575f 5622 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5623 rval = qla82xx_restart_isp(base_vha);
5624 qla82xx_idc_lock(ha);
5625 /* Clear driver state register */
5626 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5627 qla82xx_set_drv_active(base_vha);
5628 }
5629 qla82xx_idc_unlock(ha);
5630 } else {
7c3df132
SK		 5631 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5632 "This devfn is not reset owner = 0x%x.\n",
5633 ha->pdev->devfn);
a5b36321 5634 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5635 QLA8XXX_DEV_READY)) {
7190575f 5636 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5637 rval = qla82xx_restart_isp(base_vha);
5638 qla82xx_idc_lock(ha);
5639 qla82xx_set_drv_active(base_vha);
5640 qla82xx_idc_unlock(ha);
5641 }
5642 }
5643 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5644
5645 return rval;
5646}
5647
14e660e6
SJ		 5648static pci_ers_result_t
5649qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5650{
5651 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5652 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5653 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5654 struct rsp_que *rsp;
5655 int rc, retries = 10;
09483916 5656
7c3df132
SK		 5657 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5658 "Slot Reset.\n");
85880801 5659
90a86fc0
JC		 5660 /* Workaround: qla2xxx driver which access hardware earlier
5661 * needs error state to be pci_channel_io_online.
5662 * Otherwise mailbox command timesout.
5663 */
5664 pdev->error_state = pci_channel_io_normal;
5665
5666 pci_restore_state(pdev);
5667
8c1496bd
RL		 5668 /* pci_restore_state() clears the saved_state flag of the device
5669 * save restored state which resets saved_state flag
5670 */
5671 pci_save_state(pdev);
5672
09483916
BH		 5673 if (ha->mem_only)
5674 rc = pci_enable_device_mem(pdev);
5675 else
5676 rc = pci_enable_device(pdev);
14e660e6 5677
09483916 5678 if (rc) {
7c3df132 5679 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5680 "Can't re-enable PCI device after reset.\n");
a5b36321 5681 goto exit_slot_reset;
14e660e6 5682 }
14e660e6 5683
90a86fc0
JC		 5684 rsp = ha->rsp_q_map[0];
5685 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5686 goto exit_slot_reset;
90a86fc0 5687
e315cd28 5688 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5689 goto exit_slot_reset;
5690
5691 if (IS_QLA82XX(ha)) {
5692 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5693 ret = PCI_ERS_RESULT_RECOVERED;
5694 goto exit_slot_reset;
5695 } else
5696 goto exit_slot_reset;
5697 }
14e660e6 5698
90a86fc0
JC		 5699 while (ha->flags.mbox_busy && retries--)
5700 msleep(1000);
85880801 5701
e315cd28 5702 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5703 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5704 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5705 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5706
90a86fc0 5707
a5b36321 5708exit_slot_reset:
7c3df132
SK		 5709 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5710 "slot_reset return %x.\n", ret);
85880801 5711
14e660e6
SJ		 5712 return ret;
5713}
5714
5715static void
5716qla2xxx_pci_resume(struct pci_dev *pdev)
5717{
e315cd28
AC		 5718 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5719 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5720 int ret;
5721
7c3df132
SK		 5722 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5723 "pci_resume.\n");
85880801 5724
e315cd28 5725 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5726 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5727 ql_log(ql_log_fatal, base_vha, 0x9002,
5728 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5729 }
85880801 5730
3e46f031
LC		 5731 pci_cleanup_aer_uncorrect_error_status(pdev);
5732
85880801 5733 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5734}
5735
2d5a4c34
HM		 5736static void
5737qla83xx_disable_laser(scsi_qla_host_t *vha)
5738{
5739 uint32_t reg, data, fn;
5740 struct qla_hw_data *ha = vha->hw;
5741 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
5742
5743 /* pci func #/port # */
5744 ql_dbg(ql_dbg_init, vha, 0x004b,
5745 "Disabling Laser for hba: %p\n", vha);
5746
5747 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
5748 (BIT_15|BIT_14|BIT_13|BIT_12));
5749
5750 fn = (fn >> 12);
5751
5752 if (fn & 1)
5753 reg = PORT_1_2031;
5754 else
5755 reg = PORT_0_2031;
5756
5757 data = LASER_OFF_2031;
5758
5759 qla83xx_wr_reg(vha, reg, data);
5760}
5761
a55b2d21 5762static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5763 .error_detected = qla2xxx_pci_error_detected,
5764 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5765 .slot_reset = qla2xxx_pci_slot_reset,
5766 .resume = qla2xxx_pci_resume,
5767};
5768
5433383e 5769static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5770 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5771 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5772 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5773 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5774 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5775 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5776 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5777 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5778 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5779 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5780 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5781 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5782 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5783 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5784 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5785 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5786 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5787 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 5788 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 5789 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 5790 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 5791 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 5792 { 0 },
5793};
5794MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5795
fca29703 5796static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5797 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5798 .driver = {
5799 .owner = THIS_MODULE,
5800 },
fca29703 5801 .id_table = qla2xxx_pci_tbl,
7ee61397 5802 .probe = qla2x00_probe_one,
4c993f76 5803 .remove = qla2x00_remove_one,
e30d1756 5804 .shutdown = qla2x00_shutdown,
14e660e6 5805 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5806};
5807
75ef9de1 5808static const struct file_operations apidev_fops = {
6a03b4cd 5809 .owner = THIS_MODULE,
6038f373 5810 .llseek = noop_llseek,
6a03b4cd
HZ		 5811};
5812
1da177e4
LT		 5813/**
5814 * qla2x00_module_init - Module initialization.
5815 **/
5816static int __init
5817qla2x00_module_init(void)
5818{
fca29703
AV		 5819 int ret = 0;
5820
1da177e4 5821 /* Allocate cache for SRBs. */
354d6b21 5822 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5823 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5824 if (srb_cachep == NULL) {
7c3df132
SK		 5825 ql_log(ql_log_fatal, NULL, 0x0001,
5826 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5827 return -ENOMEM;
5828 }
5829
2d70c103
NB		 5830 /* Initialize target kmem_cache and mem_pools */
5831 ret = qlt_init();
5832 if (ret < 0) {
5833 kmem_cache_destroy(srb_cachep);
5834 return ret;
5835 } else if (ret > 0) {
5836 /*
5837 * If initiator mode is explictly disabled by qlt_init(),
5838 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5839 * performing scsi_scan_target() during LOOP UP event.
5840 */
5841 qla2xxx_transport_functions.disable_target_scan = 1;
5842 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5843 }
5844
1da177e4
LT		 5845 /* Derive version string. */
5846 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5847 if (ql2xextended_error_logging)
0181944f
AV		 5848 strcat(qla2x00_version_str, "-debug");
5849
1c97a12a
AV		 5850 qla2xxx_transport_template =
5851 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5852 if (!qla2xxx_transport_template) {
5853 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5854 ql_log(ql_log_fatal, NULL, 0x0002,
5855 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5856 qlt_exit();
1da177e4 5857 return -ENODEV;
2c3dfe3f 5858 }
6a03b4cd
HZ		 5859
5860 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5861 if (apidev_major < 0) {
7c3df132
SK		 5862 ql_log(ql_log_fatal, NULL, 0x0003,
5863 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5864 }
5865
2c3dfe3f
SJ		 5866 qla2xxx_transport_vport_template =
5867 fc_attach_transport(&qla2xxx_transport_vport_functions);
5868 if (!qla2xxx_transport_vport_template) {
5869 kmem_cache_destroy(srb_cachep);
2d70c103 5870 qlt_exit();
2c3dfe3f 5871 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5872 ql_log(ql_log_fatal, NULL, 0x0004,
5873 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5874 return -ENODEV;
2c3dfe3f 5875 }
7c3df132
SK		 5876 ql_log(ql_log_info, NULL, 0x0005,
5877 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5878 qla2x00_version_str);
7ee61397 5879 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5880 if (ret) {
5881 kmem_cache_destroy(srb_cachep);
2d70c103 5882 qlt_exit();
fca29703 5883 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5884 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5885 ql_log(ql_log_fatal, NULL, 0x0006,
5886 "pci_register_driver failed...ret=%d Failing load!.\n",
5887 ret);
fca29703
AV		 5888 }
5889 return ret;
1da177e4
LT		 5890}
5891
5892/**
5893 * qla2x00_module_exit - Module cleanup.
5894 **/
5895static void __exit
5896qla2x00_module_exit(void)
5897{
6a03b4cd 5898 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5899 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5900 qla2x00_release_firmware();
354d6b21 5901 kmem_cache_destroy(srb_cachep);
2d70c103 5902 qlt_exit();
a9083016
GM		 5903 if (ctx_cachep)
5904 kmem_cache_destroy(ctx_cachep);
1da177e4 5905 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5906 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5907}
5908
5909module_init(qla2x00_module_init);
5910module_exit(qla2x00_module_exit);
5911
5912MODULE_AUTHOR("QLogic Corporation");
5913MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5914MODULE_LICENSE("GPL");
5915MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5916MODULE_FIRMWARE(FW_FILE_ISP21XX);
5917MODULE_FIRMWARE(FW_FILE_ISP22XX);
5918MODULE_FIRMWARE(FW_FILE_ISP2300);
5919MODULE_FIRMWARE(FW_FILE_ISP2322);
5920MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5921MODULE_FIRMWARE(FW_FILE_ISP25XX);
f1458cda
SC		 5922MODULE_FIRMWARE(FW_FILE_ISP2031);
5923MODULE_FIRMWARE(FW_FILE_ISP8031);
5924MODULE_FIRMWARE(FW_FILE_ISP27XX);
Linux 6.x block layer and io_uring tree(s)