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scsi: lpfc: add missing Kconfig NVME dependencies
[linux-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
50280c01
CD		 116#define MAX_Q_DEPTH 32
117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 120 "Maximum queue depth to set for each LUN. "
121 "Default is 32.");
df7baa50 122
9e522cd8
AE		 123int ql2xenabledif = 2;
124module_param(ql2xenabledif, int, S_IRUGO);
bad75002 125MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 126 " Enable T10-CRC-DIF:\n"
127 " Default is 2.\n"
128 " 0 -- No DIF Support\n"
129 " 1 -- Enable DIF for all types\n"
130 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 131
8cb2049c 132int ql2xenablehba_err_chk = 2;
bad75002
AE		 133module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
134MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 135 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 136 " Default is 2.\n"
8cb2049c
AE		 137 " 0 -- Error isolation disabled\n"
138 " 1 -- Error isolation enabled only for DIX Type 0\n"
139 " 2 -- Error isolation enabled for all Types\n");
bad75002 140
e5896bd5 141int ql2xiidmaenable=1;
f2019cb1 142module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 143MODULE_PARM_DESC(ql2xiidmaenable,
144 "Enables iIDMA settings "
145 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
146
d7459527
MH		 147int ql2xmqsupport = 1;
148module_param(ql2xmqsupport, int, S_IRUGO);
149MODULE_PARM_DESC(ql2xmqsupport,
150 "Enable on demand multiple queue pairs support "
151 "Default is 1 for supported. "
152 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 153
154int ql2xfwloadbin;
86e45bf6 155module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 156module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 157MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
ae97c91e 164int ql2xetsenable;
f2019cb1 165module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 166MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
6907869d 170int ql2xdbwr = 1;
86e45bf6 171module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 172MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 176
f4c496c1 177int ql2xtargetreset = 1;
f2019cb1 178module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 179MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
4da26e16 183int ql2xgffidenable;
f2019cb1 184module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 185MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
a9083016 188
3822263e 189int ql2xasynctmfenable;
f2019cb1 190module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 191MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 194
195int ql2xdontresethba;
86e45bf6 196module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 197MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
ed0de87c 201
1abf635d
HR		 202uint64_t ql2xmaxlun = MAX_LUNS;
203module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 204MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
08de2844
GM		 208int ql2xmdcapmask = 0x1F;
209module_param(ql2xmdcapmask, int, S_IRUGO);
210MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
6e96fa7b 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 213
3aadff35 214int ql2xmdenable = 1;
08de2844
GM		 215module_param(ql2xmdenable, int, S_IRUGO);
216MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
3aadff35
GM		 218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
08de2844 220
b0d6cabd
HM		 221int ql2xexlogins = 0;
222module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
223MODULE_PARM_DESC(ql2xexlogins,
224 "Number of extended Logins. "
225 "0 (Default)- Disabled.");
226
2f56a7f1
HM		 227int ql2xexchoffld = 0;
228module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR);
229MODULE_PARM_DESC(ql2xexchoffld,
230 "Number of exchanges to offload. "
231 "0 (Default)- Disabled.");
232
f198cafa
HM		 233int ql2xfwholdabts = 0;
234module_param(ql2xfwholdabts, int, S_IRUGO);
235MODULE_PARM_DESC(ql2xfwholdabts,
236 "Allow FW to hold status IOCB until ABTS rsp received. "
237 "0 (Default) Do not set fw option. "
238 "1 - Set fw option to hold ABTS.");
239
1da177e4 240/*
fa2a1ce5 241 * SCSI host template entry points
1da177e4
LT		 242 */
243static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 244static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 245static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
246static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 247static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 248static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 249static int qla2xxx_eh_abort(struct scsi_cmnd *);
250static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 251static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 252static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
253static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 254
1a2fbf18 255static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 256static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 257static void qla83xx_disable_laser(scsi_qla_host_t *vha);
5601236b 258static int qla2xxx_map_queues(struct Scsi_Host *shost);
ce7e4af7 259
a5326f86 260struct scsi_host_template qla2xxx_driver_template = {
1da177e4 261 .module = THIS_MODULE,
cb63067a 262 .name = QLA2XXX_DRIVER_NAME,
a5326f86 263 .queuecommand = qla2xxx_queuecommand,
fca29703 264
b6a05c82 265 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 266 .eh_abort_handler = qla2xxx_eh_abort,
267 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 268 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 269 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
270 .eh_host_reset_handler = qla2xxx_eh_host_reset,
271
272 .slave_configure = qla2xxx_slave_configure,
273
274 .slave_alloc = qla2xxx_slave_alloc,
275 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 276 .scan_finished = qla2xxx_scan_finished,
277 .scan_start = qla2xxx_scan_start,
db5ed4df 278 .change_queue_depth = scsi_change_queue_depth,
5601236b 279 .map_queues = qla2xxx_map_queues,
fca29703
AV		 280 .this_id = -1,
281 .cmd_per_lun = 3,
282 .use_clustering = ENABLE_CLUSTERING,
283 .sg_tablesize = SG_ALL,
284
285 .max_sectors = 0xFFFF,
afb046e2 286 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 287
288 .supported_mode = MODE_INITIATOR,
c40ecc12 289 .track_queue_depth = 1,
fca29703
AV		 290};
291
1da177e4 292static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 293struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 294
1da177e4
LT		 295/* TODO Convert to inlines
296 *
297 * Timer routines
298 */
1da177e4 299
2c3dfe3f 300__inline__ void
e315cd28 301qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 302{
e315cd28
AC		 303 init_timer(&vha->timer);
304 vha->timer.expires = jiffies + interval * HZ;
305 vha->timer.data = (unsigned long)vha;
306 vha->timer.function = (void (*)(unsigned long))func;
307 add_timer(&vha->timer);
308 vha->timer_active = 1;
1da177e4
LT		 309}
310
311static inline void
e315cd28 312qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 313{
a9083016 314 /* Currently used for 82XX only. */
7c3df132
SK		 315 if (vha->device_flags & DFLG_DEV_FAILED) {
316 ql_dbg(ql_dbg_timer, vha, 0x600d,
317 "Device in a failed state, returning.\n");
a9083016 318 return;
7c3df132 319 }
a9083016 320
e315cd28 321 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 322}
323
a824ebb3 324static __inline__ void
e315cd28 325qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 326{
e315cd28
AC		 327 del_timer_sync(&vha->timer);
328 vha->timer_active = 0;
1da177e4
LT		 329}
330
1da177e4
LT		 331static int qla2x00_do_dpc(void *data);
332
333static void qla2x00_rst_aen(scsi_qla_host_t *);
334
73208dfd
AC		 335static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
336 struct req_que **, struct rsp_que **);
e30d1756 337static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 338static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 339int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
340 struct qla_qpair *qpair);
1da177e4 341
1da177e4 342/* -------------------------------------------------------------------------- */
9a347ff4
CD		 343static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
344 struct rsp_que *rsp)
73208dfd 345{
7c3df132 346 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 347 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 348 GFP_KERNEL);
349 if (!ha->req_q_map) {
7c3df132
SK		 350 ql_log(ql_log_fatal, vha, 0x003b,
351 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 352 goto fail_req_map;
353 }
354
2afa19a9 355 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 356 GFP_KERNEL);
357 if (!ha->rsp_q_map) {
7c3df132
SK		 358 ql_log(ql_log_fatal, vha, 0x003c,
359 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 360 goto fail_rsp_map;
361 }
d7459527
MH		 362
363 if (ql2xmqsupport && ha->max_qpairs) {
364 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
365 GFP_KERNEL);
366 if (!ha->queue_pair_map) {
367 ql_log(ql_log_fatal, vha, 0x0180,
368 "Unable to allocate memory for queue pair ptrs.\n");
369 goto fail_qpair_map;
370 }
371 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
372 if (ha->base_qpair == NULL) {
373 ql_log(ql_log_warn, vha, 0x0182,
374 "Failed to allocate base queue pair memory.\n");
375 goto fail_base_qpair;
376 }
377 ha->base_qpair->req = req;
378 ha->base_qpair->rsp = rsp;
379 }
380
9a347ff4
CD		 381 /*
382 * Make sure we record at least the request and response queue zero in
383 * case we need to free them if part of the probe fails.
384 */
385 ha->rsp_q_map[0] = rsp;
386 ha->req_q_map[0] = req;
73208dfd
AC		 387 set_bit(0, ha->rsp_qid_map);
388 set_bit(0, ha->req_qid_map);
389 return 1;
390
d7459527
MH		 391fail_base_qpair:
392 kfree(ha->queue_pair_map);
393fail_qpair_map:
394 kfree(ha->rsp_q_map);
395 ha->rsp_q_map = NULL;
73208dfd
AC		 396fail_rsp_map:
397 kfree(ha->req_q_map);
398 ha->req_q_map = NULL;
399fail_req_map:
400 return -ENOMEM;
401}
402
2afa19a9 403static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 404{
8ae6d9c7
GM		 405 if (IS_QLAFX00(ha)) {
406 if (req && req->ring_fx00)
407 dma_free_coherent(&ha->pdev->dev,
408 (req->length_fx00 + 1) * sizeof(request_t),
409 req->ring_fx00, req->dma_fx00);
410 } else if (req && req->ring)
73208dfd
AC		 411 dma_free_coherent(&ha->pdev->dev,
412 (req->length + 1) * sizeof(request_t),
413 req->ring, req->dma);
414
8d93f550
CD		 415 if (req)
416 kfree(req->outstanding_cmds);
417
73208dfd
AC		 418 kfree(req);
419 req = NULL;
420}
421
2afa19a9
AC		 422static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
423{
8ae6d9c7
GM		 424 if (IS_QLAFX00(ha)) {
425 if (rsp && rsp->ring)
426 dma_free_coherent(&ha->pdev->dev,
427 (rsp->length_fx00 + 1) * sizeof(request_t),
428 rsp->ring_fx00, rsp->dma_fx00);
429 } else if (rsp && rsp->ring) {
2afa19a9
AC		 430 dma_free_coherent(&ha->pdev->dev,
431 (rsp->length + 1) * sizeof(response_t),
432 rsp->ring, rsp->dma);
8ae6d9c7 433 }
2afa19a9
AC		 434 kfree(rsp);
435 rsp = NULL;
436}
437
73208dfd
AC		 438static void qla2x00_free_queues(struct qla_hw_data *ha)
439{
440 struct req_que *req;
441 struct rsp_que *rsp;
442 int cnt;
093df737 443 unsigned long flags;
73208dfd 444
093df737 445 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 446 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 447 if (!test_bit(cnt, ha->req_qid_map))
448 continue;
449
73208dfd 450 req = ha->req_q_map[cnt];
093df737
QT		 451 clear_bit(cnt, ha->req_qid_map);
452 ha->req_q_map[cnt] = NULL;
453
454 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 455 qla2x00_free_req_que(ha, req);
093df737 456 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 457 }
093df737
QT		 458 spin_unlock_irqrestore(&ha->hardware_lock, flags);
459
73208dfd
AC		 460 kfree(ha->req_q_map);
461 ha->req_q_map = NULL;
2afa19a9 462
093df737
QT		 463
464 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 465 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 466 if (!test_bit(cnt, ha->rsp_qid_map))
467 continue;
468
2afa19a9 469 rsp = ha->rsp_q_map[cnt];
c3c42394 470 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 471 ha->rsp_q_map[cnt] = NULL;
472 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 473 qla2x00_free_rsp_que(ha, rsp);
093df737 474 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 475 }
093df737
QT		 476 spin_unlock_irqrestore(&ha->hardware_lock, flags);
477
2afa19a9
AC		 478 kfree(ha->rsp_q_map);
479 ha->rsp_q_map = NULL;
73208dfd
AC		 480}
481
1da177e4 482static char *
e315cd28 483qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 484{
e315cd28 485 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 486 static char *pci_bus_modes[] = {
487 "33", "66", "100", "133",
488 };
489 uint16_t pci_bus;
490
491 strcpy(str, "PCI");
492 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
493 if (pci_bus) {
494 strcat(str, "-X (");
495 strcat(str, pci_bus_modes[pci_bus]);
496 } else {
497 pci_bus = (ha->pci_attr & BIT_8) >> 8;
498 strcat(str, " (");
499 strcat(str, pci_bus_modes[pci_bus]);
500 }
501 strcat(str, " MHz)");
502
503 return (str);
504}
505
fca29703 506static char *
e315cd28 507qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 508{
509 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 510 struct qla_hw_data *ha = vha->hw;
fca29703 511 uint32_t pci_bus;
fca29703 512
62a276f8 513 if (pci_is_pcie(ha->pdev)) {
fca29703 514 char lwstr[6];
62a276f8 515 uint32_t lstat, lspeed, lwidth;
fca29703 516
62a276f8
BH		 517 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
518 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
519 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 520
521 strcpy(str, "PCIe (");
49300af7
SK		 522 switch (lspeed) {
523 case 1:
c87a0d8c 524 strcat(str, "2.5GT/s ");
49300af7
SK		 525 break;
526 case 2:
c87a0d8c 527 strcat(str, "5.0GT/s ");
49300af7
SK		 528 break;
529 case 3:
530 strcat(str, "8.0GT/s ");
531 break;
532 default:
fca29703 533 strcat(str, "<unknown> ");
49300af7
SK		 534 break;
535 }
fca29703
AV		 536 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
537 strcat(str, lwstr);
538
539 return str;
540 }
541
542 strcpy(str, "PCI");
543 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
544 if (pci_bus == 0 || pci_bus == 8) {
545 strcat(str, " (");
546 strcat(str, pci_bus_modes[pci_bus >> 3]);
547 } else {
548 strcat(str, "-X ");
549 if (pci_bus & BIT_2)
550 strcat(str, "Mode 2");
551 else
552 strcat(str, "Mode 1");
553 strcat(str, " (");
554 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
555 }
556 strcat(str, " MHz)");
557
558 return str;
559}
560
e5f82ab8 561static char *
df57caba 562qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 563{
564 char un_str[10];
e315cd28 565 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 566
df57caba
HM		 567 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
568 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 569
570 if (ha->fw_attributes & BIT_9) {
571 strcat(str, "FLX");
572 return (str);
573 }
574
575 switch (ha->fw_attributes & 0xFF) {
576 case 0x7:
577 strcat(str, "EF");
578 break;
579 case 0x17:
580 strcat(str, "TP");
581 break;
582 case 0x37:
583 strcat(str, "IP");
584 break;
585 case 0x77:
586 strcat(str, "VI");
587 break;
588 default:
589 sprintf(un_str, "(%x)", ha->fw_attributes);
590 strcat(str, un_str);
591 break;
592 }
593 if (ha->fw_attributes & 0x100)
594 strcat(str, "X");
595
596 return (str);
597}
598
e5f82ab8 599static char *
df57caba 600qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 601{
e315cd28 602 struct qla_hw_data *ha = vha->hw;
f0883ac6 603
df57caba 604 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 605 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 606 return str;
fca29703
AV		 607}
608
9ba56b95
GM		 609void
610qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 611{
9ba56b95
GM		 612 srb_t *sp = (srb_t *)ptr;
613 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
614 struct qla_hw_data *ha = sp->fcport->vha->hw;
615 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 616
9ba56b95
GM		 617 if (sp->flags & SRB_DMA_VALID) {
618 scsi_dma_unmap(cmd);
619 sp->flags &= ~SRB_DMA_VALID;
7c3df132 620 }
fca29703 621
9ba56b95
GM		 622 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
623 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
624 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
625 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
626 }
627
628 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
629 /* List assured to be having elements */
f83adb61 630 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 631 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
632 }
633
634 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
635 dma_pool_free(ha->dl_dma_pool, ctx,
636 ((struct crc_context *)ctx)->crc_ctx_dma);
637 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
638 }
639
640 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
641 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 642
9ba56b95
GM		 643 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
644 ctx1->fcp_cmnd_dma);
645 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
646 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
647 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
648 mempool_free(ctx1, ha->ctx_mempool);
649 ctx1 = NULL;
650 }
651
652 CMD_SP(cmd) = NULL;
b00ee7d7 653 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 654}
655
d7459527 656void
9ba56b95
GM		 657qla2x00_sp_compl(void *data, void *ptr, int res)
658{
659 struct qla_hw_data *ha = (struct qla_hw_data *)data;
660 srb_t *sp = (srb_t *)ptr;
661 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
662
663 cmd->result = res;
664
665 if (atomic_read(&sp->ref_count) == 0) {
666 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
667 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
668 sp, GET_CMD_SP(sp));
669 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 670 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 671 return;
672 }
673 if (!atomic_dec_and_test(&sp->ref_count))
674 return;
675
676 qla2x00_sp_free_dma(ha, sp);
677 cmd->scsi_done(cmd);
fca29703
AV		 678}
679
d7459527
MH		 680void
681qla2xxx_qpair_sp_free_dma(void *vha, void *ptr)
682{
683 srb_t *sp = (srb_t *)ptr;
684 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
685 struct qla_hw_data *ha = sp->fcport->vha->hw;
686 void *ctx = GET_CMD_CTX_SP(sp);
687
688 if (sp->flags & SRB_DMA_VALID) {
689 scsi_dma_unmap(cmd);
690 sp->flags &= ~SRB_DMA_VALID;
691 }
692
693 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
694 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
695 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
696 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
697 }
698
699 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
700 /* List assured to be having elements */
701 qla2x00_clean_dsd_pool(ha, sp, NULL);
702 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
703 }
704
705 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
706 dma_pool_free(ha->dl_dma_pool, ctx,
707 ((struct crc_context *)ctx)->crc_ctx_dma);
708 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
709 }
710
711 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
712 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
713
714 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
715 ctx1->fcp_cmnd_dma);
716 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
717 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
718 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
719 mempool_free(ctx1, ha->ctx_mempool);
720 }
721
722 CMD_SP(cmd) = NULL;
723 qla2xxx_rel_qpair_sp(sp->qpair, sp);
724}
725
726void
727qla2xxx_qpair_sp_compl(void *data, void *ptr, int res)
728{
729 srb_t *sp = (srb_t *)ptr;
730 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
731
732 cmd->result = res;
733
734 if (atomic_read(&sp->ref_count) == 0) {
735 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
736 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
737 sp, GET_CMD_SP(sp));
738 if (ql2xextended_error_logging & ql_dbg_io)
739 WARN_ON(atomic_read(&sp->ref_count) == 0);
740 return;
741 }
742 if (!atomic_dec_and_test(&sp->ref_count))
743 return;
744
745 qla2xxx_qpair_sp_free_dma(sp->fcport->vha, sp);
746 cmd->scsi_done(cmd);
747}
748
8ae6d9c7
GM		 749/* If we are SP1 here, we need to still take and release the host_lock as SP1
750 * does not have the changes necessary to avoid taking host->host_lock.
751 */
1da177e4 752static int
f5e3e40b 753qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 754{
134ae078 755 scsi_qla_host_t *vha = shost_priv(host);
fca29703 756 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 757 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 758 struct qla_hw_data *ha = vha->hw;
759 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 760 srb_t *sp;
761 int rval;
5601236b
MH		 762 struct qla_qpair *qpair = NULL;
763 uint32_t tag;
764 uint16_t hwq;
fca29703 765
04dfaa53
MFO		 766 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
767 cmd->result = DID_NO_CONNECT << 16;
768 goto qc24_fail_command;
769 }
770
5601236b
MH		 771 if (ha->mqenable) {
772 if (shost_use_blk_mq(vha->host)) {
773 tag = blk_mq_unique_tag(cmd->request);
774 hwq = blk_mq_unique_tag_to_hwq(tag);
775 qpair = ha->queue_pair_map[hwq];
776 } else if (vha->vp_idx && vha->qpair) {
777 qpair = vha->qpair;
778 }
779
780 if (qpair)
781 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 782 }
783
85880801 784 if (ha->flags.eeh_busy) {
7c3df132 785 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 786 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 787 "PCI Channel IO permanent failure, exiting "
788 "cmd=%p.\n", cmd);
b9b12f73 789 cmd->result = DID_NO_CONNECT << 16;
7c3df132 790 } else {
5f28d2d7 791 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 792 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 793 cmd->result = DID_REQUEUE << 16;
7c3df132 794 }
14e660e6
SJ		 795 goto qc24_fail_command;
796 }
797
19a7b4ae
JSEC		 798 rval = fc_remote_port_chkready(rport);
799 if (rval) {
800 cmd->result = rval;
5f28d2d7 801 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 802 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
803 cmd, rval);
fca29703
AV		 804 goto qc24_fail_command;
805 }
806
bad75002
AE		 807 if (!vha->flags.difdix_supported &&
808 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 809 ql_dbg(ql_dbg_io, vha, 0x3004,
810 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
811 cmd);
bad75002
AE		 812 cmd->result = DID_NO_CONNECT << 16;
813 goto qc24_fail_command;
814 }
aa651be8
CD		 815
816 if (!fcport) {
817 cmd->result = DID_NO_CONNECT << 16;
818 goto qc24_fail_command;
819 }
820
fca29703
AV		 821 if (atomic_read(&fcport->state) != FCS_ONLINE) {
822 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 823 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 824 ql_dbg(ql_dbg_io, vha, 0x3005,
825 "Returning DNC, fcport_state=%d loop_state=%d.\n",
826 atomic_read(&fcport->state),
827 atomic_read(&base_vha->loop_state));
fca29703
AV		 828 cmd->result = DID_NO_CONNECT << 16;
829 goto qc24_fail_command;
830 }
7b594131 831 goto qc24_target_busy;
fca29703
AV		 832 }
833
e05fe292
CD		 834 /*
835 * Return target busy if we've received a non-zero retry_delay_timer
836 * in a FCP_RSP.
837 */
975f7d46
BP		 838 if (fcport->retry_delay_timestamp == 0) {
839 /* retry delay not set */
840 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 841 fcport->retry_delay_timestamp = 0;
842 else
843 goto qc24_target_busy;
844
b00ee7d7 845 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 846 if (!sp)
f5e3e40b 847 goto qc24_host_busy;
fca29703 848
9ba56b95
GM		 849 sp->u.scmd.cmd = cmd;
850 sp->type = SRB_SCSI_CMD;
851 atomic_set(&sp->ref_count, 1);
852 CMD_SP(cmd) = (void *)sp;
853 sp->free = qla2x00_sp_free_dma;
854 sp->done = qla2x00_sp_compl;
855
e315cd28 856 rval = ha->isp_ops->start_scsi(sp);
7c3df132 857 if (rval != QLA_SUCCESS) {
53016ed3 858 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 859 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 860 goto qc24_host_busy_free_sp;
7c3df132 861 }
fca29703 862
fca29703
AV		 863 return 0;
864
865qc24_host_busy_free_sp:
9ba56b95 866 qla2x00_sp_free_dma(ha, sp);
fca29703 867
f5e3e40b 868qc24_host_busy:
fca29703
AV		 869 return SCSI_MLQUEUE_HOST_BUSY;
870
7b594131
MC		 871qc24_target_busy:
872 return SCSI_MLQUEUE_TARGET_BUSY;
873
fca29703 874qc24_fail_command:
f5e3e40b 875 cmd->scsi_done(cmd);
fca29703
AV		 876
877 return 0;
878}
879
d7459527
MH		 880/* For MQ supported I/O */
881int
882qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
883 struct qla_qpair *qpair)
884{
885 scsi_qla_host_t *vha = shost_priv(host);
886 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
887 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
888 struct qla_hw_data *ha = vha->hw;
889 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
890 srb_t *sp;
891 int rval;
892
893 rval = fc_remote_port_chkready(rport);
894 if (rval) {
895 cmd->result = rval;
896 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
897 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
898 cmd, rval);
899 goto qc24_fail_command;
900 }
901
902 if (!fcport) {
903 cmd->result = DID_NO_CONNECT << 16;
904 goto qc24_fail_command;
905 }
906
907 if (atomic_read(&fcport->state) != FCS_ONLINE) {
908 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
909 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
910 ql_dbg(ql_dbg_io, vha, 0x3077,
911 "Returning DNC, fcport_state=%d loop_state=%d.\n",
912 atomic_read(&fcport->state),
913 atomic_read(&base_vha->loop_state));
914 cmd->result = DID_NO_CONNECT << 16;
915 goto qc24_fail_command;
916 }
917 goto qc24_target_busy;
918 }
919
920 /*
921 * Return target busy if we've received a non-zero retry_delay_timer
922 * in a FCP_RSP.
923 */
924 if (fcport->retry_delay_timestamp == 0) {
925 /* retry delay not set */
926 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
927 fcport->retry_delay_timestamp = 0;
928 else
929 goto qc24_target_busy;
930
931 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
932 if (!sp)
933 goto qc24_host_busy;
934
935 sp->u.scmd.cmd = cmd;
936 sp->type = SRB_SCSI_CMD;
937 atomic_set(&sp->ref_count, 1);
938 CMD_SP(cmd) = (void *)sp;
939 sp->free = qla2xxx_qpair_sp_free_dma;
940 sp->done = qla2xxx_qpair_sp_compl;
941 sp->qpair = qpair;
942
943 rval = ha->isp_ops->start_scsi_mq(sp);
944 if (rval != QLA_SUCCESS) {
945 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
946 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
947 if (rval == QLA_INTERFACE_ERROR)
948 goto qc24_fail_command;
949 goto qc24_host_busy_free_sp;
950 }
951
952 return 0;
953
954qc24_host_busy_free_sp:
955 qla2xxx_qpair_sp_free_dma(vha, sp);
956
957qc24_host_busy:
958 return SCSI_MLQUEUE_HOST_BUSY;
959
960qc24_target_busy:
961 return SCSI_MLQUEUE_TARGET_BUSY;
962
963qc24_fail_command:
964 cmd->scsi_done(cmd);
965
966 return 0;
967}
968
1da177e4
LT		 969/*
970 * qla2x00_eh_wait_on_command
971 * Waits for the command to be returned by the Firmware for some
972 * max time.
973 *
974 * Input:
1da177e4 975 * cmd = Scsi Command to wait on.
1da177e4
LT		 976 *
977 * Return:
978 * Not Found : 0
979 * Found : 1
980 */
981static int
e315cd28 982qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 983{
fe74c71f 984#define ABORT_POLLING_PERIOD 1000
478c3b03 985#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 986 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 987 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
988 struct qla_hw_data *ha = vha->hw;
f4f051eb 989 int ret = QLA_SUCCESS;
1da177e4 990
85880801 991 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 992 ql_dbg(ql_dbg_taskm, vha, 0x8005,
993 "Return:eh_wait.\n");
85880801
AV		 994 return ret;
995 }
996
d970432c 997 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 998 msleep(ABORT_POLLING_PERIOD);
f4f051eb 999 }
1000 if (CMD_SP(cmd))
1001 ret = QLA_FUNCTION_FAILED;
1da177e4 1002
f4f051eb 1003 return ret;
1da177e4
LT		 1004}
1005
1006/*
1007 * qla2x00_wait_for_hba_online
fa2a1ce5 1008 * Wait till the HBA is online after going through
1da177e4
LT		 1009 * <= MAX_RETRIES_OF_ISP_ABORT or
1010 * finally HBA is disabled ie marked offline
1011 *
1012 * Input:
1013 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1014 *
1015 * Note:
1da177e4
LT		 1016 * Does context switching-Release SPIN_LOCK
1017 * (if any) before calling this routine.
1018 *
1019 * Return:
1020 * Success (Adapter is online) : 0
1021 * Failed (Adapter is offline/disabled) : 1
1022 */
854165f4 1023int
e315cd28 1024qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1025{
fca29703
AV		 1026 int return_status;
1027 unsigned long wait_online;
e315cd28
AC		 1028 struct qla_hw_data *ha = vha->hw;
1029 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1030
fa2a1ce5 1031 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1032 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1033 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1034 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1035 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1036
1037 msleep(1000);
1038 }
e315cd28 1039 if (base_vha->flags.online)
fa2a1ce5 1040 return_status = QLA_SUCCESS;
1da177e4
LT		 1041 else
1042 return_status = QLA_FUNCTION_FAILED;
1043
1da177e4
LT		 1044 return (return_status);
1045}
1046
86fbee86 1047/*
638a1a01
SC		 1048 * qla2x00_wait_for_hba_ready
1049 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1050 *
1051 * Input:
1052 * ha - pointer to host adapter structure
1053 *
1054 * Note:
1055 * Does context switching-Release SPIN_LOCK
1056 * (if any) before calling this routine.
1057 *
86fbee86 1058 */
638a1a01
SC		 1059static void
1060qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1061{
86fbee86 1062 struct qla_hw_data *ha = vha->hw;
783e0dc4 1063 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1064
1d483901
DC		 1065 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1066 ha->flags.mbox_busy) ||
1067 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1068 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1069 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1070 break;
86fbee86 1071 msleep(1000);
783e0dc4 1072 }
86fbee86
LC		 1073}
1074
2533cf67
LC		 1075int
1076qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1077{
1078 int return_status;
1079 unsigned long wait_reset;
1080 struct qla_hw_data *ha = vha->hw;
1081 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1082
1083 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1084 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1085 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1086 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1087 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1088
1089 msleep(1000);
1090
1091 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1092 ha->flags.chip_reset_done)
1093 break;
1094 }
1095 if (ha->flags.chip_reset_done)
1096 return_status = QLA_SUCCESS;
1097 else
1098 return_status = QLA_FUNCTION_FAILED;
1099
1100 return return_status;
1101}
1102
083a469d
GM		 1103static void
1104sp_get(struct srb *sp)
1105{
1106 atomic_inc(&sp->ref_count);
1107}
1108
a465537a
SC		 1109#define ISP_REG_DISCONNECT 0xffffffffU
1110/**************************************************************************
1111* qla2x00_isp_reg_stat
1112*
1113* Description:
1114* Read the host status register of ISP before aborting the command.
1115*
1116* Input:
1117* ha = pointer to host adapter structure.
1118*
1119*
1120* Returns:
1121* Either true or false.
1122*
1123* Note: Return true if there is register disconnect.
1124**************************************************************************/
1125static inline
1126uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1127{
1128 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1129
1130 return ((RD_REG_DWORD(&reg->host_status)) == ISP_REG_DISCONNECT);
1131}
1132
1da177e4
LT		 1133/**************************************************************************
1134* qla2xxx_eh_abort
1135*
1136* Description:
1137* The abort function will abort the specified command.
1138*
1139* Input:
1140* cmd = Linux SCSI command packet to be aborted.
1141*
1142* Returns:
1143* Either SUCCESS or FAILED.
1144*
1145* Note:
2ea00202 1146* Only return FAILED if command not returned by firmware.
1da177e4 1147**************************************************************************/
e5f82ab8 1148static int
1da177e4
LT		 1149qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1150{
e315cd28 1151 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1152 srb_t *sp;
4e98d3b8 1153 int ret;
9cb78c16
HR		 1154 unsigned int id;
1155 uint64_t lun;
18e144d3 1156 unsigned long flags;
f934c9d0 1157 int rval, wait = 0;
e315cd28 1158 struct qla_hw_data *ha = vha->hw;
1da177e4 1159
a465537a
SC		 1160 if (qla2x00_isp_reg_stat(ha)) {
1161 ql_log(ql_log_info, vha, 0x8042,
1162 "PCI/Register disconnect, exiting.\n");
1163 return FAILED;
1164 }
f4f051eb 1165 if (!CMD_SP(cmd))
2ea00202 1166 return SUCCESS;
1da177e4 1167
4e98d3b8
AV		 1168 ret = fc_block_scsi_eh(cmd);
1169 if (ret != 0)
1170 return ret;
1171 ret = SUCCESS;
1172
f4f051eb 1173 id = cmd->device->id;
1174 lun = cmd->device->lun;
1da177e4 1175
e315cd28 1176 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1177 sp = (srb_t *) CMD_SP(cmd);
1178 if (!sp) {
1179 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1180 return SUCCESS;
1181 }
1da177e4 1182
7c3df132 1183 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1184 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1185 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1186
170babc3
MC		 1187 /* Get a reference to the sp and drop the lock.*/
1188 sp_get(sp);
083a469d 1189
e315cd28 1190 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1191 rval = ha->isp_ops->abort_command(sp);
1192 if (rval) {
96219424 1193 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1194 ret = SUCCESS;
96219424 1195 else
f934c9d0
CD		 1196 ret = FAILED;
1197
7c3df132 1198 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1199 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1200 } else {
7c3df132 1201 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1202 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1203 wait = 1;
1204 }
75942064
SK		 1205
1206 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 1207 sp->done(ha, sp, 0);
75942064 1208 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1209
bc91ade9
CD		 1210 /* Did the command return during mailbox execution? */
1211 if (ret == FAILED && !CMD_SP(cmd))
1212 ret = SUCCESS;
1213
f4f051eb 1214 /* Wait for the command to be returned. */
2ea00202 1215 if (wait) {
e315cd28 1216 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1217 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1218 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1219 ret = FAILED;
f4f051eb 1220 }
1da177e4 1221 }
1da177e4 1222
7c3df132 1223 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1224 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1225 vha->host_no, id, lun, wait, ret);
1da177e4 1226
f4f051eb 1227 return ret;
1228}
1da177e4 1229
4d78c973 1230int
e315cd28 1231qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1232 uint64_t l, enum nexus_wait_type type)
f4f051eb 1233{
17d98630 1234 int cnt, match, status;
18e144d3 1235 unsigned long flags;
e315cd28 1236 struct qla_hw_data *ha = vha->hw;
73208dfd 1237 struct req_que *req;
4d78c973 1238 srb_t *sp;
9ba56b95 1239 struct scsi_cmnd *cmd;
1da177e4 1240
523ec773 1241 status = QLA_SUCCESS;
17d98630 1242
e315cd28 1243 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1244 req = vha->req;
17d98630 1245 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1246 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1247 sp = req->outstanding_cmds[cnt];
1248 if (!sp)
523ec773 1249 continue;
9ba56b95 1250 if (sp->type != SRB_SCSI_CMD)
cf53b069 1251 continue;
17d98630
AC		 1252 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1253 continue;
1254 match = 0;
9ba56b95 1255 cmd = GET_CMD_SP(sp);
17d98630
AC		 1256 switch (type) {
1257 case WAIT_HOST:
1258 match = 1;
1259 break;
1260 case WAIT_TARGET:
9ba56b95 1261 match = cmd->device->id == t;
17d98630
AC		 1262 break;
1263 case WAIT_LUN:
9ba56b95
GM		 1264 match = (cmd->device->id == t &&
1265 cmd->device->lun == l);
17d98630 1266 break;
73208dfd 1267 }
17d98630
AC		 1268 if (!match)
1269 continue;
1270
1271 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1272 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1273 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1274 }
e315cd28 1275 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1276
1277 return status;
1da177e4
LT		 1278}
1279
523ec773
AV		 1280static char *reset_errors[] = {
1281 "HBA not online",
1282 "HBA not ready",
1283 "Task management failed",
1284 "Waiting for command completions",
1285};
1da177e4 1286
e5f82ab8 1287static int
523ec773 1288__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1289 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1290{
e315cd28 1291 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1292 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1293 int err;
1da177e4 1294
7c3df132 1295 if (!fcport) {
523ec773 1296 return FAILED;
7c3df132 1297 }
1da177e4 1298
4e98d3b8
AV		 1299 err = fc_block_scsi_eh(cmd);
1300 if (err != 0)
1301 return err;
1302
7c3df132 1303 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1304 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1305 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1306
523ec773 1307 err = 0;
7c3df132
SK		 1308 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1309 ql_log(ql_log_warn, vha, 0x800a,
1310 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1311 goto eh_reset_failed;
7c3df132 1312 }
523ec773 1313 err = 2;
2afa19a9 1314 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1315 != QLA_SUCCESS) {
1316 ql_log(ql_log_warn, vha, 0x800c,
1317 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1318 goto eh_reset_failed;
7c3df132 1319 }
523ec773 1320 err = 3;
e315cd28 1321 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1322 cmd->device->lun, type) != QLA_SUCCESS) {
1323 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1324 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1325 goto eh_reset_failed;
7c3df132 1326 }
523ec773 1327
7c3df132 1328 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1329 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1330 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1331
1332 return SUCCESS;
1333
4d78c973 1334eh_reset_failed:
7c3df132 1335 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1336 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1337 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1338 cmd);
523ec773
AV		 1339 return FAILED;
1340}
1da177e4 1341
523ec773
AV		 1342static int
1343qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1344{
e315cd28
AC		 1345 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1346 struct qla_hw_data *ha = vha->hw;
1da177e4 1347
a465537a
SC		 1348 if (qla2x00_isp_reg_stat(ha)) {
1349 ql_log(ql_log_info, vha, 0x803e,
1350 "PCI/Register disconnect, exiting.\n");
1351 return FAILED;
1352 }
1353
523ec773
AV		 1354 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1355 ha->isp_ops->lun_reset);
1da177e4
LT		 1356}
1357
1da177e4 1358static int
523ec773 1359qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1360{
e315cd28
AC		 1361 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1362 struct qla_hw_data *ha = vha->hw;
1da177e4 1363
a465537a
SC		 1364 if (qla2x00_isp_reg_stat(ha)) {
1365 ql_log(ql_log_info, vha, 0x803f,
1366 "PCI/Register disconnect, exiting.\n");
1367 return FAILED;
1368 }
1369
523ec773
AV		 1370 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1371 ha->isp_ops->target_reset);
1da177e4
LT		 1372}
1373
1da177e4
LT		 1374/**************************************************************************
1375* qla2xxx_eh_bus_reset
1376*
1377* Description:
1378* The bus reset function will reset the bus and abort any executing
1379* commands.
1380*
1381* Input:
1382* cmd = Linux SCSI command packet of the command that cause the
1383* bus reset.
1384*
1385* Returns:
1386* SUCCESS/FAILURE (defined as macro in scsi.h).
1387*
1388**************************************************************************/
e5f82ab8 1389static int
1da177e4
LT		 1390qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1391{
e315cd28 1392 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1393 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1394 int ret = FAILED;
9cb78c16
HR		 1395 unsigned int id;
1396 uint64_t lun;
a465537a
SC		 1397 struct qla_hw_data *ha = vha->hw;
1398
1399 if (qla2x00_isp_reg_stat(ha)) {
1400 ql_log(ql_log_info, vha, 0x8040,
1401 "PCI/Register disconnect, exiting.\n");
1402 return FAILED;
1403 }
f4f051eb 1404
f4f051eb 1405 id = cmd->device->id;
1406 lun = cmd->device->lun;
1da177e4 1407
7c3df132 1408 if (!fcport) {
f4f051eb 1409 return ret;
7c3df132 1410 }
1da177e4 1411
4e98d3b8
AV		 1412 ret = fc_block_scsi_eh(cmd);
1413 if (ret != 0)
1414 return ret;
1415 ret = FAILED;
1416
7c3df132 1417 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1418 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1419
e315cd28 1420 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1421 ql_log(ql_log_fatal, vha, 0x8013,
1422 "Wait for hba online failed board disabled.\n");
f4f051eb 1423 goto eh_bus_reset_done;
1da177e4
LT		 1424 }
1425
ad537689
SK		 1426 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1427 ret = SUCCESS;
1428
f4f051eb 1429 if (ret == FAILED)
1430 goto eh_bus_reset_done;
1da177e4 1431
9a41a62b 1432 /* Flush outstanding commands. */
4d78c973 1433 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1434 QLA_SUCCESS) {
1435 ql_log(ql_log_warn, vha, 0x8014,
1436 "Wait for pending commands failed.\n");
9a41a62b 1437 ret = FAILED;
7c3df132 1438 }
1da177e4 1439
f4f051eb 1440eh_bus_reset_done:
7c3df132 1441 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1442 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1443 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1444
f4f051eb 1445 return ret;
1da177e4
LT		 1446}
1447
1448/**************************************************************************
1449* qla2xxx_eh_host_reset
1450*
1451* Description:
1452* The reset function will reset the Adapter.
1453*
1454* Input:
1455* cmd = Linux SCSI command packet of the command that cause the
1456* adapter reset.
1457*
1458* Returns:
1459* Either SUCCESS or FAILED.
1460*
1461* Note:
1462**************************************************************************/
e5f82ab8 1463static int
1da177e4
LT		 1464qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1465{
e315cd28 1466 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1467 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1468 int ret = FAILED;
9cb78c16
HR		 1469 unsigned int id;
1470 uint64_t lun;
e315cd28 1471 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1472
a465537a
SC		 1473 if (qla2x00_isp_reg_stat(ha)) {
1474 ql_log(ql_log_info, vha, 0x8041,
1475 "PCI/Register disconnect, exiting.\n");
1476 schedule_work(&ha->board_disable);
1477 return SUCCESS;
1478 }
1479
f4f051eb 1480 id = cmd->device->id;
1481 lun = cmd->device->lun;
f4f051eb 1482
7c3df132 1483 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1484 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1485
63ee7072
CD		 1486 /*
1487 * No point in issuing another reset if one is active. Also do not
1488 * attempt a reset if we are updating flash.
1489 */
1490 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1491 goto eh_host_reset_lock;
1da177e4 1492
e315cd28
AC		 1493 if (vha != base_vha) {
1494 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1495 goto eh_host_reset_lock;
e315cd28 1496 } else {
7ec0effd 1497 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1498 if (!qla82xx_fcoe_ctx_reset(vha)) {
1499 /* Ctx reset success */
1500 ret = SUCCESS;
1501 goto eh_host_reset_lock;
1502 }
1503 /* fall thru if ctx reset failed */
1504 }
68ca949c
AC		 1505 if (ha->wq)
1506 flush_workqueue(ha->wq);
1507
e315cd28 1508 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1509 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1510 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1511 /* failed. schedule dpc to try */
1512 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1513
7c3df132
SK		 1514 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1515 ql_log(ql_log_warn, vha, 0x802a,
1516 "wait for hba online failed.\n");
e315cd28 1517 goto eh_host_reset_lock;
7c3df132 1518 }
e315cd28
AC		 1519 }
1520 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1521 }
1da177e4 1522
e315cd28 1523 /* Waiting for command to be returned to OS.*/
4d78c973 1524 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1525 QLA_SUCCESS)
f4f051eb 1526 ret = SUCCESS;
1da177e4 1527
f4f051eb 1528eh_host_reset_lock:
cfb0919c 1529 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1530 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1531 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1532
f4f051eb 1533 return ret;
1534}
1da177e4
LT		 1535
1536/*
1537* qla2x00_loop_reset
1538* Issue loop reset.
1539*
1540* Input:
1541* ha = adapter block pointer.
1542*
1543* Returns:
1544* 0 = success
1545*/
a4722cf2 1546int
e315cd28 1547qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1548{
0c8c39af 1549 int ret;
bdf79621 1550 struct fc_port *fcport;
e315cd28 1551 struct qla_hw_data *ha = vha->hw;
1da177e4 1552
5854771e
AB		 1553 if (IS_QLAFX00(ha)) {
1554 return qlafx00_loop_reset(vha);
1555 }
1556
f4c496c1 1557 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1558 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1559 if (fcport->port_type != FCT_TARGET)
1560 continue;
1561
1562 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1563 if (ret != QLA_SUCCESS) {
7c3df132 1564 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1565 "Bus Reset failed: Reset=%d "
7c3df132 1566 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1567 }
1568 }
1569 }
1570
8ae6d9c7 1571
6246b8a1 1572 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1573 atomic_set(&vha->loop_state, LOOP_DOWN);
1574 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1575 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1576 ret = qla2x00_full_login_lip(vha);
0c8c39af 1577 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1578 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1579 "full_login_lip=%d.\n", ret);
749af3d5 1580 }
0c8c39af
AV		 1581 }
1582
0d6e61bc 1583 if (ha->flags.enable_lip_reset) {
e315cd28 1584 ret = qla2x00_lip_reset(vha);
ad537689 1585 if (ret != QLA_SUCCESS)
7c3df132
SK		 1586 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1587 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1588 }
1589
1da177e4 1590 /* Issue marker command only when we are going to start the I/O */
e315cd28 1591 vha->marker_needed = 1;
1da177e4 1592
0c8c39af 1593 return QLA_SUCCESS;
1da177e4
LT		 1594}
1595
df4bf0bb 1596void
e315cd28 1597qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1598{
73208dfd 1599 int que, cnt;
df4bf0bb
AV		 1600 unsigned long flags;
1601 srb_t *sp;
e315cd28 1602 struct qla_hw_data *ha = vha->hw;
73208dfd 1603 struct req_que *req;
df4bf0bb 1604
c0cb4496
AE		 1605 qlt_host_reset_handler(ha);
1606
df4bf0bb 1607 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1608 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1609 req = ha->req_q_map[que];
73208dfd
AC		 1610 if (!req)
1611 continue;
8d93f550
CD		 1612 if (!req->outstanding_cmds)
1613 continue;
1614 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1615 sp = req->outstanding_cmds[cnt];
e612d465 1616 if (sp) {
c733ab35
MFO		 1617 /* Don't abort commands in adapter during EEH
1618 * recovery as it's not accessible/responding.
1535aa75 1619 */
2780f3c8 1620 if (GET_CMD_SP(sp) && !ha->flags.eeh_busy) {
c733ab35
MFO		 1621 /* Get a reference to the sp and drop the lock.
1622 * The reference ensures this sp->done() call
1623 * - and not the call in qla2xxx_eh_abort() -
1624 * ends the SCSI command (with result 'res').
1625 */
1626 sp_get(sp);
1627 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1628 qla2xxx_eh_abort(GET_CMD_SP(sp));
1629 spin_lock_irqsave(&ha->hardware_lock, flags);
1630 }
73208dfd 1631 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1632 sp->done(vha, sp, res);
73208dfd 1633 }
df4bf0bb
AV		 1634 }
1635 }
1636 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1637}
1638
f4f051eb 1639static int
1640qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1641{
bdf79621 1642 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1643
19a7b4ae 1644 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1645 return -ENXIO;
bdf79621 1646
19a7b4ae 1647 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1648
f4f051eb 1649 return 0;
1650}
1da177e4 1651
f4f051eb 1652static int
1653qla2xxx_slave_configure(struct scsi_device *sdev)
1654{
e315cd28 1655 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1656 struct req_que *req = vha->req;
8482e118 1657
9e522cd8
AE		 1658 if (IS_T10_PI_CAPABLE(vha->hw))
1659 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1660
db5ed4df 1661 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1662 return 0;
1663}
1da177e4 1664
f4f051eb 1665static void
1666qla2xxx_slave_destroy(struct scsi_device *sdev)
1667{
1668 sdev->hostdata = NULL;
1da177e4
LT		 1669}
1670
1671/**
1672 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1673 * @ha: HA context
1674 *
1675 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1676 * supported addressing method.
1677 */
1678static void
53303c42 1679qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1680{
7524f9b9 1681 /* Assume a 32bit DMA mask. */
1da177e4 1682 ha->flags.enable_64bit_addressing = 0;
1da177e4 1683
6a35528a 1684 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1685 /* Any upper-dword bits set? */
1686 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1687 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1688 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1689 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1690 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1691 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1692 return;
1da177e4 1693 }
1da177e4 1694 }
7524f9b9 1695
284901a9
YH		 1696 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1697 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1698}
1699
fd34f556 1700static void
e315cd28 1701qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1702{
1703 unsigned long flags = 0;
1704 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1705
1706 spin_lock_irqsave(&ha->hardware_lock, flags);
1707 ha->interrupts_on = 1;
1708 /* enable risc and host interrupts */
1709 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1710 RD_REG_WORD(&reg->ictrl);
1711 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1712
1713}
1714
1715static void
e315cd28 1716qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1717{
1718 unsigned long flags = 0;
1719 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1720
1721 spin_lock_irqsave(&ha->hardware_lock, flags);
1722 ha->interrupts_on = 0;
1723 /* disable risc and host interrupts */
1724 WRT_REG_WORD(&reg->ictrl, 0);
1725 RD_REG_WORD(&reg->ictrl);
1726 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1727}
1728
1729static void
e315cd28 1730qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1731{
1732 unsigned long flags = 0;
1733 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1734
1735 spin_lock_irqsave(&ha->hardware_lock, flags);
1736 ha->interrupts_on = 1;
1737 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1738 RD_REG_DWORD(&reg->ictrl);
1739 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1740}
1741
1742static void
e315cd28 1743qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1744{
1745 unsigned long flags = 0;
1746 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1747
124f85e6
AV		 1748 if (IS_NOPOLLING_TYPE(ha))
1749 return;
fd34f556
AV		 1750 spin_lock_irqsave(&ha->hardware_lock, flags);
1751 ha->interrupts_on = 0;
1752 WRT_REG_DWORD(&reg->ictrl, 0);
1753 RD_REG_DWORD(&reg->ictrl);
1754 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1755}
1756
706f457d
GM		 1757static int
1758qla2x00_iospace_config(struct qla_hw_data *ha)
1759{
1760 resource_size_t pio;
1761 uint16_t msix;
706f457d 1762
706f457d
GM		 1763 if (pci_request_selected_regions(ha->pdev, ha->bars,
1764 QLA2XXX_DRIVER_NAME)) {
1765 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1766 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1767 pci_name(ha->pdev));
1768 goto iospace_error_exit;
1769 }
1770 if (!(ha->bars & 1))
1771 goto skip_pio;
1772
1773 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1774 pio = pci_resource_start(ha->pdev, 0);
1775 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1776 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1777 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1778 "Invalid pci I/O region size (%s).\n",
1779 pci_name(ha->pdev));
1780 pio = 0;
1781 }
1782 } else {
1783 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1784 "Region #0 no a PIO resource (%s).\n",
1785 pci_name(ha->pdev));
1786 pio = 0;
1787 }
1788 ha->pio_address = pio;
1789 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1790 "PIO address=%llu.\n",
1791 (unsigned long long)ha->pio_address);
1792
1793skip_pio:
1794 /* Use MMIO operations for all accesses. */
1795 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1796 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1797 "Region #1 not an MMIO resource (%s), aborting.\n",
1798 pci_name(ha->pdev));
1799 goto iospace_error_exit;
1800 }
1801 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1802 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1803 "Invalid PCI mem region size (%s), aborting.\n",
1804 pci_name(ha->pdev));
1805 goto iospace_error_exit;
1806 }
1807
1808 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1809 if (!ha->iobase) {
1810 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1811 "Cannot remap MMIO (%s), aborting.\n",
1812 pci_name(ha->pdev));
1813 goto iospace_error_exit;
1814 }
1815
1816 /* Determine queue resources */
1817 ha->max_req_queues = ha->max_rsp_queues = 1;
d7459527 1818 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1819 goto mqiobase_exit;
1820
1821 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1822 pci_resource_len(ha->pdev, 3));
1823 if (ha->mqiobase) {
1824 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1825 "MQIO Base=%p.\n", ha->mqiobase);
1826 /* Read MSIX vector size of the board */
1827 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1828 ha->msix_count = msix + 1;
706f457d 1829 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1830 /* MB interrupt uses 1 vector */
1831 ha->max_req_queues = ha->msix_count - 1;
1832 ha->max_rsp_queues = ha->max_req_queues;
1833 /* Queue pairs is the max value minus the base queue pair */
1834 ha->max_qpairs = ha->max_rsp_queues - 1;
1835 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1836 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1837
706f457d 1838 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 1839 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 1840 } else
1841 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1842 "BAR 3 not enabled.\n");
1843
1844mqiobase_exit:
1845 ha->msix_count = ha->max_rsp_queues + 1;
1846 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1847 "MSIX Count:%d.\n", ha->msix_count);
1848 return (0);
1849
1850iospace_error_exit:
1851 return (-ENOMEM);
1852}
1853
1854
6246b8a1
GM		 1855static int
1856qla83xx_iospace_config(struct qla_hw_data *ha)
1857{
1858 uint16_t msix;
6246b8a1
GM		 1859
1860 if (pci_request_selected_regions(ha->pdev, ha->bars,
1861 QLA2XXX_DRIVER_NAME)) {
1862 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1863 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1864 pci_name(ha->pdev));
1865
1866 goto iospace_error_exit;
1867 }
1868
1869 /* Use MMIO operations for all accesses. */
1870 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1871 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1872 "Invalid pci I/O region size (%s).\n",
1873 pci_name(ha->pdev));
1874 goto iospace_error_exit;
1875 }
1876 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1877 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1878 "Invalid PCI mem region size (%s), aborting\n",
1879 pci_name(ha->pdev));
1880 goto iospace_error_exit;
1881 }
1882
1883 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1884 if (!ha->iobase) {
1885 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1886 "Cannot remap MMIO (%s), aborting.\n",
1887 pci_name(ha->pdev));
1888 goto iospace_error_exit;
1889 }
1890
1891 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1892 /* 83XX 26XX always use MQ type access for queues
1893 * - mbar 2, a.k.a region 4 */
1894 ha->max_req_queues = ha->max_rsp_queues = 1;
1895 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1896 pci_resource_len(ha->pdev, 4));
1897
1898 if (!ha->mqiobase) {
1899 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1900 "BAR2/region4 not enabled\n");
1901 goto mqiobase_exit;
1902 }
1903
1904 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1905 pci_resource_len(ha->pdev, 2));
1906 if (ha->msixbase) {
1907 /* Read MSIX vector size of the board */
1908 pci_read_config_word(ha->pdev,
1909 QLA_83XX_PCI_MSIX_CONTROL, &msix);
d7459527 1910 ha->msix_count = msix + 1;
093df737
QT		 1911 /*
1912 * By default, driver uses at least two msix vectors
1913 * (default & rspq)
1914 */
d7459527
MH		 1915 if (ql2xmqsupport) {
1916 /* MB interrupt uses 1 vector */
1917 ha->max_req_queues = ha->msix_count - 1;
1918 ha->max_rsp_queues = ha->max_req_queues;
093df737
QT		 1919
1920 /* ATIOQ needs 1 vector. That's 1 less QPair */
1921 if (QLA_TGT_MODE_ENABLED())
1922 ha->max_req_queues--;
1923
d7459527
MH		 1924 /* Queue pairs is the max value minus
1925 * the base queue pair */
1926 ha->max_qpairs = ha->max_req_queues - 1;
d7459527
MH		 1927 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0190,
1928 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 1929 }
1930 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 1931 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 1932 } else
1933 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1934 "BAR 1 not enabled.\n");
1935
1936mqiobase_exit:
1937 ha->msix_count = ha->max_rsp_queues + 1;
093df737
QT		 1938 if (QLA_TGT_MODE_ENABLED())
1939 ha->msix_count++;
aa230bc5
AE		 1940
1941 qlt_83xx_iospace_config(ha);
1942
6246b8a1
GM		 1943 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1944 "MSIX Count:%d.\n", ha->msix_count);
1945 return 0;
1946
1947iospace_error_exit:
1948 return -ENOMEM;
1949}
1950
fd34f556
AV		 1951static struct isp_operations qla2100_isp_ops = {
1952 .pci_config = qla2100_pci_config,
1953 .reset_chip = qla2x00_reset_chip,
1954 .chip_diag = qla2x00_chip_diag,
1955 .config_rings = qla2x00_config_rings,
1956 .reset_adapter = qla2x00_reset_adapter,
1957 .nvram_config = qla2x00_nvram_config,
1958 .update_fw_options = qla2x00_update_fw_options,
1959 .load_risc = qla2x00_load_risc,
1960 .pci_info_str = qla2x00_pci_info_str,
1961 .fw_version_str = qla2x00_fw_version_str,
1962 .intr_handler = qla2100_intr_handler,
1963 .enable_intrs = qla2x00_enable_intrs,
1964 .disable_intrs = qla2x00_disable_intrs,
1965 .abort_command = qla2x00_abort_command,
523ec773
AV		 1966 .target_reset = qla2x00_abort_target,
1967 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1968 .fabric_login = qla2x00_login_fabric,
1969 .fabric_logout = qla2x00_fabric_logout,
1970 .calc_req_entries = qla2x00_calc_iocbs_32,
1971 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1972 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1973 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1974 .read_nvram = qla2x00_read_nvram_data,
1975 .write_nvram = qla2x00_write_nvram_data,
1976 .fw_dump = qla2100_fw_dump,
1977 .beacon_on = NULL,
1978 .beacon_off = NULL,
1979 .beacon_blink = NULL,
1980 .read_optrom = qla2x00_read_optrom_data,
1981 .write_optrom = qla2x00_write_optrom_data,
1982 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1983 .start_scsi = qla2x00_start_scsi,
d7459527 1984 .start_scsi_mq = NULL,
a9083016 1985 .abort_isp = qla2x00_abort_isp,
706f457d 1986 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1987 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1988};
1989
1990static struct isp_operations qla2300_isp_ops = {
1991 .pci_config = qla2300_pci_config,
1992 .reset_chip = qla2x00_reset_chip,
1993 .chip_diag = qla2x00_chip_diag,
1994 .config_rings = qla2x00_config_rings,
1995 .reset_adapter = qla2x00_reset_adapter,
1996 .nvram_config = qla2x00_nvram_config,
1997 .update_fw_options = qla2x00_update_fw_options,
1998 .load_risc = qla2x00_load_risc,
1999 .pci_info_str = qla2x00_pci_info_str,
2000 .fw_version_str = qla2x00_fw_version_str,
2001 .intr_handler = qla2300_intr_handler,
2002 .enable_intrs = qla2x00_enable_intrs,
2003 .disable_intrs = qla2x00_disable_intrs,
2004 .abort_command = qla2x00_abort_command,
523ec773
AV		 2005 .target_reset = qla2x00_abort_target,
2006 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2007 .fabric_login = qla2x00_login_fabric,
2008 .fabric_logout = qla2x00_fabric_logout,
2009 .calc_req_entries = qla2x00_calc_iocbs_32,
2010 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2011 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2012 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2013 .read_nvram = qla2x00_read_nvram_data,
2014 .write_nvram = qla2x00_write_nvram_data,
2015 .fw_dump = qla2300_fw_dump,
2016 .beacon_on = qla2x00_beacon_on,
2017 .beacon_off = qla2x00_beacon_off,
2018 .beacon_blink = qla2x00_beacon_blink,
2019 .read_optrom = qla2x00_read_optrom_data,
2020 .write_optrom = qla2x00_write_optrom_data,
2021 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2022 .start_scsi = qla2x00_start_scsi,
d7459527 2023 .start_scsi_mq = NULL,
a9083016 2024 .abort_isp = qla2x00_abort_isp,
7ec0effd 2025 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2026 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2027};
2028
2029static struct isp_operations qla24xx_isp_ops = {
2030 .pci_config = qla24xx_pci_config,
2031 .reset_chip = qla24xx_reset_chip,
2032 .chip_diag = qla24xx_chip_diag,
2033 .config_rings = qla24xx_config_rings,
2034 .reset_adapter = qla24xx_reset_adapter,
2035 .nvram_config = qla24xx_nvram_config,
2036 .update_fw_options = qla24xx_update_fw_options,
2037 .load_risc = qla24xx_load_risc,
2038 .pci_info_str = qla24xx_pci_info_str,
2039 .fw_version_str = qla24xx_fw_version_str,
2040 .intr_handler = qla24xx_intr_handler,
2041 .enable_intrs = qla24xx_enable_intrs,
2042 .disable_intrs = qla24xx_disable_intrs,
2043 .abort_command = qla24xx_abort_command,
523ec773
AV		 2044 .target_reset = qla24xx_abort_target,
2045 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2046 .fabric_login = qla24xx_login_fabric,
2047 .fabric_logout = qla24xx_fabric_logout,
2048 .calc_req_entries = NULL,
2049 .build_iocbs = NULL,
2050 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2051 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2052 .read_nvram = qla24xx_read_nvram_data,
2053 .write_nvram = qla24xx_write_nvram_data,
2054 .fw_dump = qla24xx_fw_dump,
2055 .beacon_on = qla24xx_beacon_on,
2056 .beacon_off = qla24xx_beacon_off,
2057 .beacon_blink = qla24xx_beacon_blink,
2058 .read_optrom = qla24xx_read_optrom_data,
2059 .write_optrom = qla24xx_write_optrom_data,
2060 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2061 .start_scsi = qla24xx_start_scsi,
d7459527 2062 .start_scsi_mq = NULL,
a9083016 2063 .abort_isp = qla2x00_abort_isp,
7ec0effd 2064 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2065 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2066};
2067
c3a2f0df
AV		 2068static struct isp_operations qla25xx_isp_ops = {
2069 .pci_config = qla25xx_pci_config,
2070 .reset_chip = qla24xx_reset_chip,
2071 .chip_diag = qla24xx_chip_diag,
2072 .config_rings = qla24xx_config_rings,
2073 .reset_adapter = qla24xx_reset_adapter,
2074 .nvram_config = qla24xx_nvram_config,
2075 .update_fw_options = qla24xx_update_fw_options,
2076 .load_risc = qla24xx_load_risc,
2077 .pci_info_str = qla24xx_pci_info_str,
2078 .fw_version_str = qla24xx_fw_version_str,
2079 .intr_handler = qla24xx_intr_handler,
2080 .enable_intrs = qla24xx_enable_intrs,
2081 .disable_intrs = qla24xx_disable_intrs,
2082 .abort_command = qla24xx_abort_command,
523ec773
AV		 2083 .target_reset = qla24xx_abort_target,
2084 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2085 .fabric_login = qla24xx_login_fabric,
2086 .fabric_logout = qla24xx_fabric_logout,
2087 .calc_req_entries = NULL,
2088 .build_iocbs = NULL,
2089 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2090 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2091 .read_nvram = qla25xx_read_nvram_data,
2092 .write_nvram = qla25xx_write_nvram_data,
2093 .fw_dump = qla25xx_fw_dump,
2094 .beacon_on = qla24xx_beacon_on,
2095 .beacon_off = qla24xx_beacon_off,
2096 .beacon_blink = qla24xx_beacon_blink,
338c9161 2097 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2098 .write_optrom = qla24xx_write_optrom_data,
2099 .get_flash_version = qla24xx_get_flash_version,
bad75002 2100 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2101 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2102 .abort_isp = qla2x00_abort_isp,
7ec0effd 2103 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2104 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2105};
2106
3a03eb79
AV		 2107static struct isp_operations qla81xx_isp_ops = {
2108 .pci_config = qla25xx_pci_config,
2109 .reset_chip = qla24xx_reset_chip,
2110 .chip_diag = qla24xx_chip_diag,
2111 .config_rings = qla24xx_config_rings,
2112 .reset_adapter = qla24xx_reset_adapter,
2113 .nvram_config = qla81xx_nvram_config,
2114 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2115 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2116 .pci_info_str = qla24xx_pci_info_str,
2117 .fw_version_str = qla24xx_fw_version_str,
2118 .intr_handler = qla24xx_intr_handler,
2119 .enable_intrs = qla24xx_enable_intrs,
2120 .disable_intrs = qla24xx_disable_intrs,
2121 .abort_command = qla24xx_abort_command,
2122 .target_reset = qla24xx_abort_target,
2123 .lun_reset = qla24xx_lun_reset,
2124 .fabric_login = qla24xx_login_fabric,
2125 .fabric_logout = qla24xx_fabric_logout,
2126 .calc_req_entries = NULL,
2127 .build_iocbs = NULL,
2128 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2129 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2130 .read_nvram = NULL,
2131 .write_nvram = NULL,
3a03eb79
AV		 2132 .fw_dump = qla81xx_fw_dump,
2133 .beacon_on = qla24xx_beacon_on,
2134 .beacon_off = qla24xx_beacon_off,
6246b8a1 2135 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2136 .read_optrom = qla25xx_read_optrom_data,
2137 .write_optrom = qla24xx_write_optrom_data,
2138 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2139 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2140 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2141 .abort_isp = qla2x00_abort_isp,
7ec0effd 2142 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2143 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2144};
2145
2146static struct isp_operations qla82xx_isp_ops = {
2147 .pci_config = qla82xx_pci_config,
2148 .reset_chip = qla82xx_reset_chip,
2149 .chip_diag = qla24xx_chip_diag,
2150 .config_rings = qla82xx_config_rings,
2151 .reset_adapter = qla24xx_reset_adapter,
2152 .nvram_config = qla81xx_nvram_config,
2153 .update_fw_options = qla24xx_update_fw_options,
2154 .load_risc = qla82xx_load_risc,
9d55ca66 2155 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2156 .fw_version_str = qla24xx_fw_version_str,
2157 .intr_handler = qla82xx_intr_handler,
2158 .enable_intrs = qla82xx_enable_intrs,
2159 .disable_intrs = qla82xx_disable_intrs,
2160 .abort_command = qla24xx_abort_command,
2161 .target_reset = qla24xx_abort_target,
2162 .lun_reset = qla24xx_lun_reset,
2163 .fabric_login = qla24xx_login_fabric,
2164 .fabric_logout = qla24xx_fabric_logout,
2165 .calc_req_entries = NULL,
2166 .build_iocbs = NULL,
2167 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2168 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2169 .read_nvram = qla24xx_read_nvram_data,
2170 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2171 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2172 .beacon_on = qla82xx_beacon_on,
2173 .beacon_off = qla82xx_beacon_off,
2174 .beacon_blink = NULL,
a9083016
GM		 2175 .read_optrom = qla82xx_read_optrom_data,
2176 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2177 .get_flash_version = qla82xx_get_flash_version,
a9083016 2178 .start_scsi = qla82xx_start_scsi,
d7459527 2179 .start_scsi_mq = NULL,
a9083016 2180 .abort_isp = qla82xx_abort_isp,
706f457d 2181 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2182 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2183};
2184
7ec0effd
AD		 2185static struct isp_operations qla8044_isp_ops = {
2186 .pci_config = qla82xx_pci_config,
2187 .reset_chip = qla82xx_reset_chip,
2188 .chip_diag = qla24xx_chip_diag,
2189 .config_rings = qla82xx_config_rings,
2190 .reset_adapter = qla24xx_reset_adapter,
2191 .nvram_config = qla81xx_nvram_config,
2192 .update_fw_options = qla24xx_update_fw_options,
2193 .load_risc = qla82xx_load_risc,
2194 .pci_info_str = qla24xx_pci_info_str,
2195 .fw_version_str = qla24xx_fw_version_str,
2196 .intr_handler = qla8044_intr_handler,
2197 .enable_intrs = qla82xx_enable_intrs,
2198 .disable_intrs = qla82xx_disable_intrs,
2199 .abort_command = qla24xx_abort_command,
2200 .target_reset = qla24xx_abort_target,
2201 .lun_reset = qla24xx_lun_reset,
2202 .fabric_login = qla24xx_login_fabric,
2203 .fabric_logout = qla24xx_fabric_logout,
2204 .calc_req_entries = NULL,
2205 .build_iocbs = NULL,
2206 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2207 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2208 .read_nvram = NULL,
2209 .write_nvram = NULL,
a1b23c5a 2210 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2211 .beacon_on = qla82xx_beacon_on,
2212 .beacon_off = qla82xx_beacon_off,
2213 .beacon_blink = NULL,
888e639d 2214 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2215 .write_optrom = qla8044_write_optrom_data,
2216 .get_flash_version = qla82xx_get_flash_version,
2217 .start_scsi = qla82xx_start_scsi,
d7459527 2218 .start_scsi_mq = NULL,
7ec0effd
AD		 2219 .abort_isp = qla8044_abort_isp,
2220 .iospace_config = qla82xx_iospace_config,
2221 .initialize_adapter = qla2x00_initialize_adapter,
2222};
2223
6246b8a1
GM		 2224static struct isp_operations qla83xx_isp_ops = {
2225 .pci_config = qla25xx_pci_config,
2226 .reset_chip = qla24xx_reset_chip,
2227 .chip_diag = qla24xx_chip_diag,
2228 .config_rings = qla24xx_config_rings,
2229 .reset_adapter = qla24xx_reset_adapter,
2230 .nvram_config = qla81xx_nvram_config,
2231 .update_fw_options = qla81xx_update_fw_options,
2232 .load_risc = qla81xx_load_risc,
2233 .pci_info_str = qla24xx_pci_info_str,
2234 .fw_version_str = qla24xx_fw_version_str,
2235 .intr_handler = qla24xx_intr_handler,
2236 .enable_intrs = qla24xx_enable_intrs,
2237 .disable_intrs = qla24xx_disable_intrs,
2238 .abort_command = qla24xx_abort_command,
2239 .target_reset = qla24xx_abort_target,
2240 .lun_reset = qla24xx_lun_reset,
2241 .fabric_login = qla24xx_login_fabric,
2242 .fabric_logout = qla24xx_fabric_logout,
2243 .calc_req_entries = NULL,
2244 .build_iocbs = NULL,
2245 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2246 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2247 .read_nvram = NULL,
2248 .write_nvram = NULL,
2249 .fw_dump = qla83xx_fw_dump,
2250 .beacon_on = qla24xx_beacon_on,
2251 .beacon_off = qla24xx_beacon_off,
2252 .beacon_blink = qla83xx_beacon_blink,
2253 .read_optrom = qla25xx_read_optrom_data,
2254 .write_optrom = qla24xx_write_optrom_data,
2255 .get_flash_version = qla24xx_get_flash_version,
2256 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2257 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2258 .abort_isp = qla2x00_abort_isp,
2259 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2260 .initialize_adapter = qla2x00_initialize_adapter,
2261};
2262
2263static struct isp_operations qlafx00_isp_ops = {
2264 .pci_config = qlafx00_pci_config,
2265 .reset_chip = qlafx00_soft_reset,
2266 .chip_diag = qlafx00_chip_diag,
2267 .config_rings = qlafx00_config_rings,
2268 .reset_adapter = qlafx00_soft_reset,
2269 .nvram_config = NULL,
2270 .update_fw_options = NULL,
2271 .load_risc = NULL,
2272 .pci_info_str = qlafx00_pci_info_str,
2273 .fw_version_str = qlafx00_fw_version_str,
2274 .intr_handler = qlafx00_intr_handler,
2275 .enable_intrs = qlafx00_enable_intrs,
2276 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2277 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2278 .target_reset = qlafx00_abort_target,
2279 .lun_reset = qlafx00_lun_reset,
2280 .fabric_login = NULL,
2281 .fabric_logout = NULL,
2282 .calc_req_entries = NULL,
2283 .build_iocbs = NULL,
2284 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2285 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2286 .read_nvram = qla24xx_read_nvram_data,
2287 .write_nvram = qla24xx_write_nvram_data,
2288 .fw_dump = NULL,
2289 .beacon_on = qla24xx_beacon_on,
2290 .beacon_off = qla24xx_beacon_off,
2291 .beacon_blink = NULL,
2292 .read_optrom = qla24xx_read_optrom_data,
2293 .write_optrom = qla24xx_write_optrom_data,
2294 .get_flash_version = qla24xx_get_flash_version,
2295 .start_scsi = qlafx00_start_scsi,
d7459527 2296 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2297 .abort_isp = qlafx00_abort_isp,
2298 .iospace_config = qlafx00_iospace_config,
2299 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2300};
2301
f73cb695
CD		 2302static struct isp_operations qla27xx_isp_ops = {
2303 .pci_config = qla25xx_pci_config,
2304 .reset_chip = qla24xx_reset_chip,
2305 .chip_diag = qla24xx_chip_diag,
2306 .config_rings = qla24xx_config_rings,
2307 .reset_adapter = qla24xx_reset_adapter,
2308 .nvram_config = qla81xx_nvram_config,
2309 .update_fw_options = qla81xx_update_fw_options,
2310 .load_risc = qla81xx_load_risc,
2311 .pci_info_str = qla24xx_pci_info_str,
2312 .fw_version_str = qla24xx_fw_version_str,
2313 .intr_handler = qla24xx_intr_handler,
2314 .enable_intrs = qla24xx_enable_intrs,
2315 .disable_intrs = qla24xx_disable_intrs,
2316 .abort_command = qla24xx_abort_command,
2317 .target_reset = qla24xx_abort_target,
2318 .lun_reset = qla24xx_lun_reset,
2319 .fabric_login = qla24xx_login_fabric,
2320 .fabric_logout = qla24xx_fabric_logout,
2321 .calc_req_entries = NULL,
2322 .build_iocbs = NULL,
2323 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2324 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2325 .read_nvram = NULL,
2326 .write_nvram = NULL,
2327 .fw_dump = qla27xx_fwdump,
2328 .beacon_on = qla24xx_beacon_on,
2329 .beacon_off = qla24xx_beacon_off,
2330 .beacon_blink = qla83xx_beacon_blink,
2331 .read_optrom = qla25xx_read_optrom_data,
2332 .write_optrom = qla24xx_write_optrom_data,
2333 .get_flash_version = qla24xx_get_flash_version,
2334 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2335 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2336 .abort_isp = qla2x00_abort_isp,
2337 .iospace_config = qla83xx_iospace_config,
2338 .initialize_adapter = qla2x00_initialize_adapter,
2339};
2340
ea5b6382 2341static inline void
e315cd28 2342qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2343{
2344 ha->device_type = DT_EXTENDED_IDS;
2345 switch (ha->pdev->device) {
2346 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2347 ha->isp_type |= DT_ISP2100;
ea5b6382 2348 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2349 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2350 break;
2351 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2352 ha->isp_type |= DT_ISP2200;
ea5b6382 2353 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2354 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2355 break;
2356 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2357 ha->isp_type |= DT_ISP2300;
4a59f71d 2358 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2359 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2360 break;
2361 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2362 ha->isp_type |= DT_ISP2312;
4a59f71d 2363 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2364 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2365 break;
2366 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2367 ha->isp_type |= DT_ISP2322;
4a59f71d 2368 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2369 if (ha->pdev->subsystem_vendor == 0x1028 &&
2370 ha->pdev->subsystem_device == 0x0170)
2371 ha->device_type |= DT_OEM_001;
441d1072 2372 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2373 break;
2374 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2375 ha->isp_type |= DT_ISP6312;
441d1072 2376 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2377 break;
2378 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2379 ha->isp_type |= DT_ISP6322;
441d1072 2380 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2381 break;
2382 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2383 ha->isp_type |= DT_ISP2422;
4a59f71d 2384 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2385 ha->device_type |= DT_FWI2;
c76f2c01 2386 ha->device_type |= DT_IIDMA;
441d1072 2387 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2388 break;
2389 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2390 ha->isp_type |= DT_ISP2432;
4a59f71d 2391 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2392 ha->device_type |= DT_FWI2;
c76f2c01 2393 ha->device_type |= DT_IIDMA;
441d1072 2394 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2395 break;
4d4df193 2396 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2397 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2398 ha->device_type |= DT_ZIO_SUPPORTED;
2399 ha->device_type |= DT_FWI2;
2400 ha->device_type |= DT_IIDMA;
2401 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2402 break;
044cc6c8 2403 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2404 ha->isp_type |= DT_ISP5422;
e428924c 2405 ha->device_type |= DT_FWI2;
441d1072 2406 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2407 break;
044cc6c8 2408 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2409 ha->isp_type |= DT_ISP5432;
e428924c 2410 ha->device_type |= DT_FWI2;
441d1072 2411 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2412 break;
c3a2f0df 2413 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2414 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2415 ha->device_type |= DT_ZIO_SUPPORTED;
2416 ha->device_type |= DT_FWI2;
2417 ha->device_type |= DT_IIDMA;
441d1072 2418 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2419 break;
3a03eb79 2420 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2421 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2422 ha->device_type |= DT_ZIO_SUPPORTED;
2423 ha->device_type |= DT_FWI2;
2424 ha->device_type |= DT_IIDMA;
2425 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2426 break;
a9083016 2427 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2428 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2429 ha->device_type |= DT_ZIO_SUPPORTED;
2430 ha->device_type |= DT_FWI2;
2431 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2432 /* Initialize 82XX ISP flags */
2433 qla82xx_init_flags(ha);
2434 break;
7ec0effd 2435 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2436 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2437 ha->device_type |= DT_ZIO_SUPPORTED;
2438 ha->device_type |= DT_FWI2;
2439 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2440 /* Initialize 82XX ISP flags */
2441 qla82xx_init_flags(ha);
2442 break;
6246b8a1 2443 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2444 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2445 ha->device_type |= DT_ZIO_SUPPORTED;
2446 ha->device_type |= DT_FWI2;
2447 ha->device_type |= DT_IIDMA;
2448 ha->device_type |= DT_T10_PI;
2449 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2450 break;
2451 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2452 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2453 ha->device_type |= DT_ZIO_SUPPORTED;
2454 ha->device_type |= DT_FWI2;
2455 ha->device_type |= DT_IIDMA;
2456 ha->device_type |= DT_T10_PI;
2457 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2458 break;
8ae6d9c7 2459 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2460 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2461 break;
f73cb695 2462 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2463 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2464 ha->device_type |= DT_ZIO_SUPPORTED;
2465 ha->device_type |= DT_FWI2;
2466 ha->device_type |= DT_IIDMA;
8ce3f570 2467 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2468 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2469 break;
2c5bbbb2 2470 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2471 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2472 ha->device_type |= DT_ZIO_SUPPORTED;
2473 ha->device_type |= DT_FWI2;
2474 ha->device_type |= DT_IIDMA;
8ce3f570 2475 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2476 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2477 break;
2b48992f 2478 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2479 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2480 ha->device_type |= DT_ZIO_SUPPORTED;
2481 ha->device_type |= DT_FWI2;
2482 ha->device_type |= DT_IIDMA;
8ce3f570 2483 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2484 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2485 break;
ea5b6382 2486 }
e5b68a61 2487
a9083016 2488 if (IS_QLA82XX(ha))
43a9c38b 2489 ha->port_no = ha->portnum & 1;
f73cb695 2490 else {
a9083016
GM		 2491 /* Get adapter physical port no from interrupt pin register. */
2492 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2493 if (IS_QLA27XX(ha))
2494 ha->port_no--;
2495 else
2496 ha->port_no = !(ha->port_no & 1);
2497 }
a9083016 2498
7c3df132 2499 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2500 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2501 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2502}
2503
1e99e33a
AV		 2504static void
2505qla2xxx_scan_start(struct Scsi_Host *shost)
2506{
e315cd28 2507 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2508
cbc8eb67
AV		 2509 if (vha->hw->flags.running_gold_fw)
2510 return;
2511
e315cd28
AC		 2512 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2513 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2514 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2515 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2516}
2517
2518static int
2519qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2520{
e315cd28 2521 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2522
a5dd506e
BK		 2523 if (test_bit(UNLOADING, &vha->dpc_flags))
2524 return 1;
e315cd28 2525 if (!vha->host)
1e99e33a 2526 return 1;
e315cd28 2527 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2528 return 1;
2529
e315cd28 2530 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2531}
2532
1da177e4
LT		 2533/*
2534 * PCI driver interface
2535 */
6f039790 2536static int
7ee61397 2537qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2538{
a1541d5a 2539 int ret = -ENODEV;
1da177e4 2540 struct Scsi_Host *host;
e315cd28
AC		 2541 scsi_qla_host_t *base_vha = NULL;
2542 struct qla_hw_data *ha;
29856e28 2543 char pci_info[30];
7d613ac6 2544 char fw_str[30], wq_name[30];
5433383e 2545 struct scsi_host_template *sht;
642ef983 2546 int bars, mem_only = 0;
e315cd28 2547 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2548 struct req_que *req = NULL;
2549 struct rsp_que *rsp = NULL;
5601236b 2550 int i;
d7459527 2551
285d0321 2552 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2553 sht = &qla2xxx_driver_template;
5433383e 2554 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2555 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2556 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2557 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2558 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2559 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2560 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2561 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2562 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2563 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2564 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2565 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2566 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2567 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2568 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2569 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2570 mem_only = 1;
7c3df132
SK		 2571 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2572 "Mem only adapter.\n");
285d0321 2573 }
7c3df132
SK		 2574 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2575 "Bars=%d.\n", bars);
285d0321 2576
09483916
BH		 2577 if (mem_only) {
2578 if (pci_enable_device_mem(pdev))
2579 goto probe_out;
2580 } else {
2581 if (pci_enable_device(pdev))
2582 goto probe_out;
2583 }
285d0321 2584
0927678f
JB		 2585 /* This may fail but that's ok */
2586 pci_enable_pcie_error_reporting(pdev);
285d0321 2587
e315cd28
AC		 2588 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2589 if (!ha) {
7c3df132
SK		 2590 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2591 "Unable to allocate memory for ha.\n");
e315cd28 2592 goto probe_out;
1da177e4 2593 }
7c3df132
SK		 2594 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2595 "Memory allocated for ha=%p.\n", ha);
e315cd28 2596 ha->pdev = pdev;
2d70c103 2597 ha->tgt.enable_class_2 = ql2xenableclass2;
33e79977
QT		 2598 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2599 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2600 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2601 spin_lock_init(&ha->tgt.atio_lock);
2602
1da177e4
LT		 2603
2604 /* Clear our data area */
285d0321 2605 ha->bars = bars;
09483916 2606 ha->mem_only = mem_only;
df4bf0bb 2607 spin_lock_init(&ha->hardware_lock);
339aa70e 2608 spin_lock_init(&ha->vport_slock);
a9b6f722 2609 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2610 mutex_init(&ha->optrom_mutex);
1da177e4 2611
ea5b6382 2612 /* Set ISP-type information. */
2613 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2614
2615 /* Set EEH reset type to fundamental if required by hba */
95676112 2616 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2617 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2618 pdev->needs_freset = 1;
ca79cf66 2619
cba1e47f
CD		 2620 ha->prev_topology = 0;
2621 ha->init_cb_size = sizeof(init_cb_t);
2622 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2623 ha->optrom_size = OPTROM_SIZE_2300;
2624
abbd8870 2625 /* Assign ISP specific operations. */
1da177e4 2626 if (IS_QLA2100(ha)) {
642ef983 2627 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2628 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2629 req_length = REQUEST_ENTRY_CNT_2100;
2630 rsp_length = RESPONSE_ENTRY_CNT_2100;
2631 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2632 ha->gid_list_info_size = 4;
3a03eb79
AV		 2633 ha->flash_conf_off = ~0;
2634 ha->flash_data_off = ~0;
2635 ha->nvram_conf_off = ~0;
2636 ha->nvram_data_off = ~0;
fd34f556 2637 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2638 } else if (IS_QLA2200(ha)) {
642ef983 2639 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2640 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2641 req_length = REQUEST_ENTRY_CNT_2200;
2642 rsp_length = RESPONSE_ENTRY_CNT_2100;
2643 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2644 ha->gid_list_info_size = 4;
3a03eb79
AV		 2645 ha->flash_conf_off = ~0;
2646 ha->flash_data_off = ~0;
2647 ha->nvram_conf_off = ~0;
2648 ha->nvram_data_off = ~0;
fd34f556 2649 ha->isp_ops = &qla2100_isp_ops;
fca29703 2650 } else if (IS_QLA23XX(ha)) {
642ef983 2651 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2652 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2653 req_length = REQUEST_ENTRY_CNT_2200;
2654 rsp_length = RESPONSE_ENTRY_CNT_2300;
2655 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2656 ha->gid_list_info_size = 6;
854165f4 2657 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2658 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2659 ha->flash_conf_off = ~0;
2660 ha->flash_data_off = ~0;
2661 ha->nvram_conf_off = ~0;
2662 ha->nvram_data_off = ~0;
fd34f556 2663 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2664 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2665 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2666 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2667 req_length = REQUEST_ENTRY_CNT_24XX;
2668 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2669 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2670 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2671 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2672 ha->gid_list_info_size = 8;
854165f4 2673 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2674 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2675 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2676 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2677 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2678 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2679 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2680 } else if (IS_QLA25XX(ha)) {
642ef983 2681 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2682 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2683 req_length = REQUEST_ENTRY_CNT_24XX;
2684 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2685 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2686 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2687 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2688 ha->gid_list_info_size = 8;
2689 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2690 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2691 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2692 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2693 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2694 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2695 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2696 } else if (IS_QLA81XX(ha)) {
642ef983 2697 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2698 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2699 req_length = REQUEST_ENTRY_CNT_24XX;
2700 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2701 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2702 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2703 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2704 ha->gid_list_info_size = 8;
2705 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2706 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2707 ha->isp_ops = &qla81xx_isp_ops;
2708 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2709 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2710 ha->nvram_conf_off = ~0;
2711 ha->nvram_data_off = ~0;
a9083016 2712 } else if (IS_QLA82XX(ha)) {
642ef983 2713 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2714 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2715 req_length = REQUEST_ENTRY_CNT_82XX;
2716 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2717 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2718 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2719 ha->gid_list_info_size = 8;
2720 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2721 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2722 ha->isp_ops = &qla82xx_isp_ops;
2723 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2724 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2725 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2726 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2727 } else if (IS_QLA8044(ha)) {
2728 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2729 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2730 req_length = REQUEST_ENTRY_CNT_82XX;
2731 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2732 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2733 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2734 ha->gid_list_info_size = 8;
2735 ha->optrom_size = OPTROM_SIZE_83XX;
2736 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2737 ha->isp_ops = &qla8044_isp_ops;
2738 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2739 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2740 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2741 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2742 } else if (IS_QLA83XX(ha)) {
7d613ac6 2743 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2744 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2745 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2746 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2747 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2748 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2749 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2750 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2751 ha->gid_list_info_size = 8;
2752 ha->optrom_size = OPTROM_SIZE_83XX;
2753 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2754 ha->isp_ops = &qla83xx_isp_ops;
2755 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2756 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2757 ha->nvram_conf_off = ~0;
2758 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2759 } else if (IS_QLAFX00(ha)) {
2760 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2761 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2762 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2763 req_length = REQUEST_ENTRY_CNT_FX00;
2764 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2765 ha->isp_ops = &qlafx00_isp_ops;
2766 ha->port_down_retry_count = 30; /* default value */
2767 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2768 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2769 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2770 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2771 ha->mr.host_info_resend = false;
2772 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2773 } else if (IS_QLA27XX(ha)) {
2774 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2775 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2776 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2777 req_length = REQUEST_ENTRY_CNT_83XX;
2778 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2779 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2780 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2781 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2782 ha->gid_list_info_size = 8;
2783 ha->optrom_size = OPTROM_SIZE_83XX;
2784 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2785 ha->isp_ops = &qla27xx_isp_ops;
2786 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2787 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2788 ha->nvram_conf_off = ~0;
2789 ha->nvram_data_off = ~0;
1da177e4 2790 }
6246b8a1 2791
7c3df132
SK		 2792 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2793 "mbx_count=%d, req_length=%d, "
2794 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2795 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2796 "max_fibre_devices=%d.\n",
7c3df132
SK		 2797 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2798 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2799 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2800 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2801 "isp_ops=%p, flash_conf_off=%d, "
2802 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2803 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2804 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2805
2806 /* Configure PCI I/O space */
2807 ret = ha->isp_ops->iospace_config(ha);
2808 if (ret)
0a63ad12 2809 goto iospace_config_failed;
706f457d
GM		 2810
2811 ql_log_pci(ql_log_info, pdev, 0x001d,
2812 "Found an ISP%04X irq %d iobase 0x%p.\n",
2813 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2814 mutex_init(&ha->vport_lock);
d7459527 2815 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2816 init_completion(&ha->mbx_cmd_comp);
2817 complete(&ha->mbx_cmd_comp);
2818 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2819 init_completion(&ha->dcbx_comp);
f356bef1 2820 init_completion(&ha->lb_portup_comp);
1da177e4 2821
2c3dfe3f 2822 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2823
53303c42 2824 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2825 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2826 "64 Bit addressing is %s.\n",
2827 ha->flags.enable_64bit_addressing ? "enable" :
2828 "disable");
73208dfd 2829 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2830 if (ret) {
7c3df132
SK		 2831 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2832 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2833
e315cd28
AC		 2834 goto probe_hw_failed;
2835 }
2836
73208dfd 2837 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2838 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2839 req->max_q_depth = ql2xmaxqdepth;
2840
e315cd28
AC		 2841
2842 base_vha = qla2x00_create_host(sht, ha);
2843 if (!base_vha) {
a1541d5a 2844 ret = -ENOMEM;
6e9f21f3 2845 qla2x00_mem_free(ha);
2afa19a9
AC		 2846 qla2x00_free_req_que(ha, req);
2847 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2848 goto probe_hw_failed;
1da177e4
LT		 2849 }
2850
e315cd28 2851 pci_set_drvdata(pdev, base_vha);
6b383979 2852 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2853
e315cd28 2854 host = base_vha->host;
2afa19a9 2855 base_vha->req = req;
73208dfd 2856 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2857 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2858 else
e315cd28
AC		 2859 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2860 base_vha->vp_idx;
58548cb5 2861
8ae6d9c7
GM		 2862 /* Setup fcport template structure. */
2863 ha->mr.fcport.vha = base_vha;
2864 ha->mr.fcport.port_type = FCT_UNKNOWN;
2865 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2866 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2867 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2868 ha->mr.fcport.scan_state = 1;
2869
58548cb5
GM		 2870 /* Set the SG table size based on ISP type */
2871 if (!IS_FWI2_CAPABLE(ha)) {
2872 if (IS_QLA2100(ha))
2873 host->sg_tablesize = 32;
2874 } else {
2875 if (!IS_QLA82XX(ha))
2876 host->sg_tablesize = QLA_SG_ALL;
2877 }
642ef983 2878 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2879 host->cmd_per_lun = 3;
2880 host->unique_id = host->host_no;
e02587d7 2881 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2882 host->max_cmd_len = 32;
2883 else
2884 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2885 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2886 /* Older HBAs support only 16-bit LUNs */
2887 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2888 ql2xmaxlun > 0xffff)
2889 host->max_lun = 0xffff;
2890 else
2891 host->max_lun = ql2xmaxlun;
e315cd28 2892 host->transportt = qla2xxx_transport_template;
9a069e19 2893 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2894
7c3df132
SK		 2895 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2896 "max_id=%d this_id=%d "
2897 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2898 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2899 host->this_id, host->cmd_per_lun, host->unique_id,
2900 host->max_cmd_len, host->max_channel, host->max_lun,
2901 host->transportt, sht->vendor_id);
2902
d7459527
MH		 2903 /* Set up the irqs */
2904 ret = qla2x00_request_irqs(ha, rsp);
2905 if (ret)
2906 goto probe_init_failed;
2907
9a347ff4
CD		 2908 /* Alloc arrays of request and response ring ptrs */
2909 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2910 ql_log(ql_log_fatal, base_vha, 0x003d,
2911 "Failed to allocate memory for queue pointers..."
2912 "aborting.\n");
2913 goto probe_init_failed;
2914 }
2915
5601236b
MH		 2916 if (ha->mqenable && shost_use_blk_mq(host)) {
2917 /* number of hardware queues supported by blk/scsi-mq*/
2918 host->nr_hw_queues = ha->max_qpairs;
2919
2920 ql_dbg(ql_dbg_init, base_vha, 0x0192,
2921 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
2922 } else
2923 ql_dbg(ql_dbg_init, base_vha, 0x0193,
2924 "blk/scsi-mq disabled.\n");
2925
2d70c103 2926 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2927
90a86fc0
JC		 2928 pci_save_state(pdev);
2929
9a347ff4 2930 /* Assign back pointers */
2afa19a9
AC		 2931 rsp->req = req;
2932 req->rsp = rsp;
9a347ff4 2933
8ae6d9c7
GM		 2934 if (IS_QLAFX00(ha)) {
2935 ha->rsp_q_map[0] = rsp;
2936 ha->req_q_map[0] = req;
2937 set_bit(0, ha->req_qid_map);
2938 set_bit(0, ha->rsp_qid_map);
2939 }
2940
08029990
AV		 2941 /* FWI2-capable only. */
2942 req->req_q_in = &ha->iobase->isp24.req_q_in;
2943 req->req_q_out = &ha->iobase->isp24.req_q_out;
2944 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2945 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2946 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2947 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2948 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2949 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2950 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2951 }
2952
8ae6d9c7
GM		 2953 if (IS_QLAFX00(ha)) {
2954 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2955 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2956 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2957 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2958 }
2959
7ec0effd 2960 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2961 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2962 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2963 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2964 }
2965
7c3df132
SK		 2966 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2967 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2968 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2969 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2970 "req->req_q_in=%p req->req_q_out=%p "
2971 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2972 req->req_q_in, req->req_q_out,
2973 rsp->rsp_q_in, rsp->rsp_q_out);
2974 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2975 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2976 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2977 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2978 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2979 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2980
8ae6d9c7 2981 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2982 ql_log(ql_log_fatal, base_vha, 0x00d6,
2983 "Failed to initialize adapter - Adapter flags %x.\n",
2984 base_vha->device_flags);
1da177e4 2985
a9083016
GM		 2986 if (IS_QLA82XX(ha)) {
2987 qla82xx_idc_lock(ha);
2988 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2989 QLA8XXX_DEV_FAILED);
a9083016 2990 qla82xx_idc_unlock(ha);
7c3df132
SK		 2991 ql_log(ql_log_fatal, base_vha, 0x00d7,
2992 "HW State: FAILED.\n");
7ec0effd
AD		 2993 } else if (IS_QLA8044(ha)) {
2994 qla8044_idc_lock(ha);
2995 qla8044_wr_direct(base_vha,
2996 QLA8044_CRB_DEV_STATE_INDEX,
2997 QLA8XXX_DEV_FAILED);
2998 qla8044_idc_unlock(ha);
2999 ql_log(ql_log_fatal, base_vha, 0x0150,
3000 "HW State: FAILED.\n");
a9083016
GM		 3001 }
3002
a1541d5a 3003 ret = -ENODEV;
1da177e4
LT		 3004 goto probe_failed;
3005 }
3006
3b1bef64
CD		 3007 if (IS_QLAFX00(ha))
3008 host->can_queue = QLAFX00_MAX_CANQUEUE;
3009 else
3010 host->can_queue = req->num_outstanding_cmds - 10;
3011
3012 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3013 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3014 host->can_queue, base_vha->req,
3015 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3016
093df737 3017 if (ha->mqenable && qla_ini_mode_enabled(base_vha)) {
d7459527 3018 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
5601236b
MH		 3019 /* Create start of day qpairs for Block MQ */
3020 if (shost_use_blk_mq(host)) {
3021 for (i = 0; i < ha->max_qpairs; i++)
3022 qla2xxx_create_qpair(base_vha, 5, 0);
3023 }
3024 }
68ca949c 3025
cbc8eb67
AV		 3026 if (ha->flags.running_gold_fw)
3027 goto skip_dpc;
3028
1da177e4
LT		 3029 /*
3030 * Startup the kernel thread for this host adapter
3031 */
39a11240 3032 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3033 "%s_dpc", base_vha->host_str);
39a11240 3034 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3035 ql_log(ql_log_fatal, base_vha, 0x00ed,
3036 "Failed to start DPC thread.\n");
39a11240 3037 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 3038 goto probe_failed;
3039 }
7c3df132
SK		 3040 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3041 "DPC thread started successfully.\n");
1da177e4 3042
2d70c103
NB		 3043 /*
3044 * If we're not coming up in initiator mode, we might sit for
3045 * a while without waking up the dpc thread, which leads to a
3046 * stuck process warning. So just kick the dpc once here and
3047 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3048 */
3049 qla2xxx_wake_dpc(base_vha);
3050
f3ddac19
CD		 3051 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3052
81178772
SK		 3053 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3054 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3055 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3056 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3057
3058 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3059 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3060 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3061 INIT_WORK(&ha->idc_state_handler,
3062 qla83xx_idc_state_handler_work);
3063 INIT_WORK(&ha->nic_core_unrecoverable,
3064 qla83xx_nic_core_unrecoverable_work);
3065 }
3066
cbc8eb67 3067skip_dpc:
e315cd28
AC		 3068 list_add_tail(&base_vha->list, &ha->vp_list);
3069 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3070
3071 /* Initialized the timer */
e315cd28 3072 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 3073 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3074 "Started qla2x00_timer with "
3075 "interval=%d.\n", WATCH_INTERVAL);
3076 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3077 "Detected hba at address=%p.\n",
3078 ha);
d19044c3 3079
e02587d7 3080 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3081 if (ha->fw_attributes & BIT_4) {
9e522cd8 3082 int prot = 0, guard;
bad75002 3083 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3084 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3085 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3086 if (ql2xenabledif == 1)
3087 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3088 scsi_host_set_prot(host,
8cb2049c 3089 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3090 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3091 | SHOST_DIF_TYPE3_PROTECTION
3092 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3093 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3094 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3095
3096 guard = SHOST_DIX_GUARD_CRC;
3097
3098 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3099 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3100 guard |= SHOST_DIX_GUARD_IP;
3101
3102 scsi_host_set_guard(host, guard);
bad75002
AE		 3103 } else
3104 base_vha->flags.difdix_supported = 0;
3105 }
3106
a9083016
GM		 3107 ha->isp_ops->enable_intrs(ha);
3108
1fe19ee4
AB		 3109 if (IS_QLAFX00(ha)) {
3110 ret = qlafx00_fx_disc(base_vha,
3111 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3112 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3113 QLA_SG_ALL : 128;
3114 }
3115
a1541d5a
AV		 3116 ret = scsi_add_host(host, &pdev->dev);
3117 if (ret)
3118 goto probe_failed;
3119
1486400f
MR		 3120 base_vha->flags.init_done = 1;
3121 base_vha->flags.online = 1;
edaa5c74 3122 ha->prev_minidump_failed = 0;
1486400f 3123
7c3df132
SK		 3124 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3125 "Init done and hba is online.\n");
3126
2d70c103
NB		 3127 if (qla_ini_mode_enabled(base_vha))
3128 scsi_scan_host(host);
3129 else
3130 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3131 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3132
e315cd28 3133 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3134
8ae6d9c7 3135 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3136 ret = qlafx00_fx_disc(base_vha,
3137 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3138
3139 /* Register system information */
3140 ret = qlafx00_fx_disc(base_vha,
3141 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3142 }
3143
e315cd28 3144 qla2x00_init_host_attr(base_vha);
a1541d5a 3145
e315cd28 3146 qla2x00_dfs_setup(base_vha);
df613b96 3147
03eb912a
AB		 3148 ql_log(ql_log_info, base_vha, 0x00fb,
3149 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3150 ql_log(ql_log_info, base_vha, 0x00fc,
3151 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3152 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3153 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3154 base_vha->host_no,
df57caba 3155 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3156
2d70c103
NB		 3157 qlt_add_target(ha, base_vha);
3158
6b383979 3159 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3160
3161 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3162 return -ENODEV;
3163
1da177e4
LT		 3164 return 0;
3165
6e9f21f3 3166probe_init_failed:
2afa19a9 3167 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3168 ha->req_q_map[0] = NULL;
3169 clear_bit(0, ha->req_qid_map);
2afa19a9 3170 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3171 ha->rsp_q_map[0] = NULL;
3172 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3173 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3174
1da177e4 3175probe_failed:
b9978769
AV		 3176 if (base_vha->timer_active)
3177 qla2x00_stop_timer(base_vha);
3178 base_vha->flags.online = 0;
3179 if (ha->dpc_thread) {
3180 struct task_struct *t = ha->dpc_thread;
3181
3182 ha->dpc_thread = NULL;
3183 kthread_stop(t);
3184 }
3185
e315cd28 3186 qla2x00_free_device(base_vha);
1da177e4 3187
e315cd28 3188 scsi_host_put(base_vha->host);
1da177e4 3189
e315cd28 3190probe_hw_failed:
1a2fbf18
JL		 3191 qla2x00_clear_drv_active(ha);
3192
0a63ad12 3193iospace_config_failed:
7ec0effd 3194 if (IS_P3P_TYPE(ha)) {
0a63ad12 3195 if (!ha->nx_pcibase)
f73cb695 3196 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3197 if (!ql2xdbwr)
f73cb695 3198 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3199 } else {
3200 if (ha->iobase)
3201 iounmap(ha->iobase);
8ae6d9c7
GM		 3202 if (ha->cregbase)
3203 iounmap(ha->cregbase);
a9083016 3204 }
e315cd28
AC		 3205 pci_release_selected_regions(ha->pdev, ha->bars);
3206 kfree(ha);
3207 ha = NULL;
1da177e4 3208
a1541d5a 3209probe_out:
e315cd28 3210 pci_disable_device(pdev);
a1541d5a 3211 return ret;
1da177e4 3212}
1da177e4 3213
e30d1756
MI		 3214static void
3215qla2x00_shutdown(struct pci_dev *pdev)
3216{
3217 scsi_qla_host_t *vha;
3218 struct qla_hw_data *ha;
3219
552f3f9a
MI		 3220 if (!atomic_read(&pdev->enable_cnt))
3221 return;
3222
e30d1756
MI		 3223 vha = pci_get_drvdata(pdev);
3224 ha = vha->hw;
3225
42479343
AB		 3226 /* Notify ISPFX00 firmware */
3227 if (IS_QLAFX00(ha))
3228 qlafx00_driver_shutdown(vha, 20);
3229
e30d1756
MI		 3230 /* Turn-off FCE trace */
3231 if (ha->flags.fce_enabled) {
3232 qla2x00_disable_fce_trace(vha, NULL, NULL);
3233 ha->flags.fce_enabled = 0;
3234 }
3235
3236 /* Turn-off EFT trace */
3237 if (ha->eft)
3238 qla2x00_disable_eft_trace(vha);
3239
3240 /* Stop currently executing firmware. */
3241 qla2x00_try_to_stop_firmware(vha);
3242
3243 /* Turn adapter off line */
3244 vha->flags.online = 0;
3245
3246 /* turn-off interrupts on the card */
3247 if (ha->interrupts_on) {
3248 vha->flags.init_done = 0;
3249 ha->isp_ops->disable_intrs(ha);
3250 }
3251
3252 qla2x00_free_irqs(vha);
3253
3254 qla2x00_free_fw_dump(ha);
61d41f61
CD		 3255
3256 pci_disable_pcie_error_reporting(pdev);
3257 pci_disable_device(pdev);
e30d1756
MI		 3258}
3259
fe1b806f 3260/* Deletes all the virtual ports for a given ha */
4c993f76 3261static void
fe1b806f 3262qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3263{
fe1b806f 3264 scsi_qla_host_t *vha;
feafb7b1 3265 unsigned long flags;
e315cd28 3266
43ebf16d
AE		 3267 mutex_lock(&ha->vport_lock);
3268 while (ha->cur_vport_count) {
43ebf16d 3269 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3270
43ebf16d
AE		 3271 BUG_ON(base_vha->list.next == &ha->vp_list);
3272 /* This assumes first entry in ha->vp_list is always base vha */
3273 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3274 scsi_host_get(vha->host);
feafb7b1 3275
43ebf16d
AE		 3276 spin_unlock_irqrestore(&ha->vport_slock, flags);
3277 mutex_unlock(&ha->vport_lock);
3278
3279 fc_vport_terminate(vha->fc_vport);
3280 scsi_host_put(vha->host);
feafb7b1 3281
43ebf16d 3282 mutex_lock(&ha->vport_lock);
e315cd28 3283 }
43ebf16d 3284 mutex_unlock(&ha->vport_lock);
fe1b806f 3285}
1da177e4 3286
fe1b806f
CD		 3287/* Stops all deferred work threads */
3288static void
3289qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3290{
7d613ac6
SV		 3291 /* Cancel all work and destroy DPC workqueues */
3292 if (ha->dpc_lp_wq) {
3293 cancel_work_sync(&ha->idc_aen);
3294 destroy_workqueue(ha->dpc_lp_wq);
3295 ha->dpc_lp_wq = NULL;
3296 }
3297
3298 if (ha->dpc_hp_wq) {
3299 cancel_work_sync(&ha->nic_core_reset);
3300 cancel_work_sync(&ha->idc_state_handler);
3301 cancel_work_sync(&ha->nic_core_unrecoverable);
3302 destroy_workqueue(ha->dpc_hp_wq);
3303 ha->dpc_hp_wq = NULL;
3304 }
3305
b9978769
AV		 3306 /* Kill the kernel thread for this host */
3307 if (ha->dpc_thread) {
3308 struct task_struct *t = ha->dpc_thread;
3309
3310 /*
3311 * qla2xxx_wake_dpc checks for ->dpc_thread
3312 * so we need to zero it out.
3313 */
3314 ha->dpc_thread = NULL;
3315 kthread_stop(t);
3316 }
fe1b806f 3317}
1da177e4 3318
fe1b806f
CD		 3319static void
3320qla2x00_unmap_iobases(struct qla_hw_data *ha)
3321{
a9083016 3322 if (IS_QLA82XX(ha)) {
b963752f 3323
f73cb695 3324 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3325 if (!ql2xdbwr)
f73cb695 3326 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3327 } else {
3328 if (ha->iobase)
3329 iounmap(ha->iobase);
1da177e4 3330
8ae6d9c7
GM		 3331 if (ha->cregbase)
3332 iounmap(ha->cregbase);
3333
a9083016
GM		 3334 if (ha->mqiobase)
3335 iounmap(ha->mqiobase);
6246b8a1 3336
f73cb695 3337 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3338 iounmap(ha->msixbase);
a9083016 3339 }
fe1b806f
CD		 3340}
3341
3342static void
db7157d4 3343qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3344{
fe1b806f
CD		 3345 if (IS_QLA8044(ha)) {
3346 qla8044_idc_lock(ha);
c41afc9a 3347 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3348 qla8044_idc_unlock(ha);
3349 } else if (IS_QLA82XX(ha)) {
3350 qla82xx_idc_lock(ha);
3351 qla82xx_clear_drv_active(ha);
3352 qla82xx_idc_unlock(ha);
3353 }
3354}
3355
3356static void
3357qla2x00_remove_one(struct pci_dev *pdev)
3358{
3359 scsi_qla_host_t *base_vha;
3360 struct qla_hw_data *ha;
3361
beb9e315
JL		 3362 base_vha = pci_get_drvdata(pdev);
3363 ha = base_vha->hw;
3364
3365 /* Indicate device removal to prevent future board_disable and wait
3366 * until any pending board_disable has completed. */
3367 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3368 cancel_work_sync(&ha->board_disable);
3369
fe1b806f 3370 /*
beb9e315
JL		 3371 * If the PCI device is disabled then there was a PCI-disconnect and
3372 * qla2x00_disable_board_on_pci_error has taken care of most of the
3373 * resources.
fe1b806f 3374 */
beb9e315
JL		 3375 if (!atomic_read(&pdev->enable_cnt)) {
3376 scsi_host_put(base_vha->host);
3377 kfree(ha);
3378 pci_set_drvdata(pdev, NULL);
fe1b806f 3379 return;
beb9e315 3380 }
fe1b806f 3381
638a1a01
SC		 3382 qla2x00_wait_for_hba_ready(base_vha);
3383
783e0dc4
SC		 3384 /* if UNLOAD flag is already set, then continue unload,
3385 * where it was set first.
3386 */
3387 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3388 return;
3389
fe1b806f
CD		 3390 set_bit(UNLOADING, &base_vha->dpc_flags);
3391
3392 if (IS_QLAFX00(ha))
3393 qlafx00_driver_shutdown(base_vha, 20);
3394
3395 qla2x00_delete_all_vps(ha, base_vha);
3396
3397 if (IS_QLA8031(ha)) {
3398 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3399 "Clearing fcoe driver presence.\n");
3400 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3401 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3402 "Error while clearing DRV-Presence.\n");
3403 }
3404
3405 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3406
3407 qla2x00_dfs_remove(base_vha);
3408
3409 qla84xx_put_chip(base_vha);
3410
2d5a4c34
HM		 3411 /* Laser should be disabled only for ISP2031 */
3412 if (IS_QLA2031(ha))
3413 qla83xx_disable_laser(base_vha);
3414
fe1b806f
CD		 3415 /* Disable timer */
3416 if (base_vha->timer_active)
3417 qla2x00_stop_timer(base_vha);
3418
3419 base_vha->flags.online = 0;
3420
b0d6cabd
HM		 3421 /* free DMA memory */
3422 if (ha->exlogin_buf)
3423 qla2x00_free_exlogin_buffer(ha);
3424
2f56a7f1
HM		 3425 /* free DMA memory */
3426 if (ha->exchoffld_buf)
3427 qla2x00_free_exchoffld_buffer(ha);
3428
fe1b806f
CD		 3429 qla2x00_destroy_deferred_work(ha);
3430
3431 qlt_remove_target(ha, base_vha);
3432
3433 qla2x00_free_sysfs_attr(base_vha, true);
3434
3435 fc_remove_host(base_vha->host);
3436
3437 scsi_remove_host(base_vha->host);
3438
3439 qla2x00_free_device(base_vha);
3440
db7157d4 3441 qla2x00_clear_drv_active(ha);
fe1b806f 3442
d2749ffa
AE		 3443 scsi_host_put(base_vha->host);
3444
fe1b806f 3445 qla2x00_unmap_iobases(ha);
73208dfd 3446
e315cd28
AC		 3447 pci_release_selected_regions(ha->pdev, ha->bars);
3448 kfree(ha);
3449 ha = NULL;
1da177e4 3450
90a86fc0
JC		 3451 pci_disable_pcie_error_reporting(pdev);
3452
665db93b 3453 pci_disable_device(pdev);
1da177e4 3454}
1da177e4
LT		 3455
3456static void
e315cd28 3457qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3458{
e315cd28 3459 struct qla_hw_data *ha = vha->hw;
1da177e4 3460
85880801
AV		 3461 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3462
3463 /* Disable timer */
3464 if (vha->timer_active)
3465 qla2x00_stop_timer(vha);
3466
2afa19a9 3467 qla25xx_delete_queues(vha);
fe1b806f 3468
df613b96 3469 if (ha->flags.fce_enabled)
e315cd28 3470 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3471
a7a167bf 3472 if (ha->eft)
e315cd28 3473 qla2x00_disable_eft_trace(vha);
a7a167bf 3474
f6ef3b18 3475 /* Stop currently executing firmware. */
e315cd28 3476 qla2x00_try_to_stop_firmware(vha);
1da177e4 3477
85880801
AV		 3478 vha->flags.online = 0;
3479
f6ef3b18 3480 /* turn-off interrupts on the card */
a9083016
GM		 3481 if (ha->interrupts_on) {
3482 vha->flags.init_done = 0;
fd34f556 3483 ha->isp_ops->disable_intrs(ha);
a9083016 3484 }
f6ef3b18 3485
093df737
QT		 3486 qla2x00_free_fcports(vha);
3487
e315cd28 3488 qla2x00_free_irqs(vha);
1da177e4 3489
093df737
QT		 3490 /* Flush the work queue and remove it */
3491 if (ha->wq) {
3492 flush_workqueue(ha->wq);
3493 destroy_workqueue(ha->wq);
3494 ha->wq = NULL;
3495 }
3496
8867048b 3497
e315cd28 3498 qla2x00_mem_free(ha);
73208dfd 3499
08de2844
GM		 3500 qla82xx_md_free(vha);
3501
73208dfd 3502 qla2x00_free_queues(ha);
1da177e4
LT		 3503}
3504
8867048b
CD		 3505void qla2x00_free_fcports(struct scsi_qla_host *vha)
3506{
3507 fc_port_t *fcport, *tfcport;
3508
3509 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3510 list_del(&fcport->list);
5f16b331 3511 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3512 kfree(fcport);
3513 fcport = NULL;
3514 }
3515}
3516
d97994dc 3517static inline void
e315cd28 3518qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3519 int defer)
3520{
d97994dc 3521 struct fc_rport *rport;
67becc00 3522 scsi_qla_host_t *base_vha;
044d78e1 3523 unsigned long flags;
d97994dc 3524
3525 if (!fcport->rport)
3526 return;
3527
3528 rport = fcport->rport;
3529 if (defer) {
67becc00 3530 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3531 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3532 fcport->drport = rport;
044d78e1 3533 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3534 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3535 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3536 qla2xxx_wake_dpc(base_vha);
2d70c103 3537 } else {
df673274 3538 int now;
d20ed91b
AP		 3539 if (rport)
3540 fc_remote_port_delete(rport);
df673274
AP		 3541 qlt_do_generation_tick(vha, &now);
3542 qlt_fc_port_deleted(vha, fcport, now);
2d70c103 3543 }
d97994dc 3544}
3545
1da177e4
LT		 3546/*
3547 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3548 *
3549 * Input: ha = adapter block pointer. fcport = port structure pointer.
3550 *
3551 * Return: None.
3552 *
3553 * Context:
3554 */
e315cd28 3555void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3556 int do_login, int defer)
1da177e4 3557{
8ae6d9c7
GM		 3558 if (IS_QLAFX00(vha->hw)) {
3559 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3560 qla2x00_schedule_rport_del(vha, fcport, defer);
3561 return;
3562 }
3563
2c3dfe3f 3564 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3565 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3566 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3567 qla2x00_schedule_rport_del(vha, fcport, defer);
3568 }
fa2a1ce5 3569 /*
1da177e4
LT		 3570 * We may need to retry the login, so don't change the state of the
3571 * port but do the retries.
3572 */
3573 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3574 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3575
3576 if (!do_login)
3577 return;
3578
a1d0285e
AE		 3579 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3580
1da177e4 3581 if (fcport->login_retry == 0) {
e315cd28 3582 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3583
7c3df132 3584 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3585 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3586 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3587 }
3588}
3589
3590/*
3591 * qla2x00_mark_all_devices_lost
3592 * Updates fcport state when device goes offline.
3593 *
3594 * Input:
3595 * ha = adapter block pointer.
3596 * fcport = port structure pointer.
3597 *
3598 * Return:
3599 * None.
3600 *
3601 * Context:
3602 */
3603void
e315cd28 3604qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3605{
3606 fc_port_t *fcport;
3607
e315cd28 3608 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3609 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3610 continue;
0d6e61bc 3611
1da177e4
LT		 3612 /*
3613 * No point in marking the device as lost, if the device is
3614 * already DEAD.
3615 */
3616 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3617 continue;
e315cd28 3618 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3619 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3620 if (defer)
3621 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3622 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3623 qla2x00_schedule_rport_del(vha, fcport, defer);
3624 }
1da177e4
LT		 3625 }
3626}
3627
3628/*
3629* qla2x00_mem_alloc
3630* Allocates adapter memory.
3631*
3632* Returns:
3633* 0 = success.
e8711085 3634* !0 = failure.
1da177e4 3635*/
e8711085 3636static int
73208dfd
AC		 3637qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3638 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3639{
3640 char name[16];
1da177e4 3641
e8711085 3642 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3643 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3644 if (!ha->init_cb)
e315cd28 3645 goto fail;
e8711085 3646
2d70c103
NB		 3647 if (qlt_mem_alloc(ha) < 0)
3648 goto fail_free_init_cb;
3649
642ef983
CD		 3650 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3651 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3652 if (!ha->gid_list)
2d70c103 3653 goto fail_free_tgt_mem;
1da177e4 3654
e8711085
AV		 3655 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3656 if (!ha->srb_mempool)
e315cd28 3657 goto fail_free_gid_list;
e8711085 3658
7ec0effd 3659 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3660 /* Allocate cache for CT6 Ctx. */
3661 if (!ctx_cachep) {
3662 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3663 sizeof(struct ct6_dsd), 0,
3664 SLAB_HWCACHE_ALIGN, NULL);
3665 if (!ctx_cachep)
fc1ffd6c 3666 goto fail_free_srb_mempool;
a9083016
GM		 3667 }
3668 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3669 ctx_cachep);
3670 if (!ha->ctx_mempool)
3671 goto fail_free_srb_mempool;
7c3df132
SK		 3672 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3673 "ctx_cachep=%p ctx_mempool=%p.\n",
3674 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3675 }
3676
e8711085
AV		 3677 /* Get memory for cached NVRAM */
3678 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3679 if (!ha->nvram)
a9083016 3680 goto fail_free_ctx_mempool;
e8711085 3681
e315cd28
AC		 3682 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3683 ha->pdev->device);
3684 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3685 DMA_POOL_SIZE, 8, 0);
3686 if (!ha->s_dma_pool)
3687 goto fail_free_nvram;
3688
7c3df132
SK		 3689 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3690 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3691 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3692
7ec0effd 3693 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3694 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3695 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3696 if (!ha->dl_dma_pool) {
7c3df132
SK		 3697 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3698 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3699 goto fail_s_dma_pool;
3700 }
3701
3702 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3703 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3704 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3705 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3706 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3707 goto fail_dl_dma_pool;
3708 }
7c3df132
SK		 3709 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3710 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3711 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3712 }
3713
e8711085
AV		 3714 /* Allocate memory for SNS commands */
3715 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3716 /* Get consistent memory allocated for SNS commands */
e8711085 3717 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3718 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3719 if (!ha->sns_cmd)
e315cd28 3720 goto fail_dma_pool;
7c3df132 3721 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3722 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3723 } else {
e315cd28 3724 /* Get consistent memory allocated for MS IOCB */
e8711085 3725 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3726 &ha->ms_iocb_dma);
e8711085 3727 if (!ha->ms_iocb)
e315cd28
AC		 3728 goto fail_dma_pool;
3729 /* Get consistent memory allocated for CT SNS commands */
e8711085 3730 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3731 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3732 if (!ha->ct_sns)
3733 goto fail_free_ms_iocb;
7c3df132
SK		 3734 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3735 "ms_iocb=%p ct_sns=%p.\n",
3736 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3737 }
3738
e315cd28 3739 /* Allocate memory for request ring */
73208dfd
AC		 3740 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3741 if (!*req) {
7c3df132
SK		 3742 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3743 "Failed to allocate memory for req.\n");
e315cd28
AC		 3744 goto fail_req;
3745 }
73208dfd
AC		 3746 (*req)->length = req_len;
3747 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3748 ((*req)->length + 1) * sizeof(request_t),
3749 &(*req)->dma, GFP_KERNEL);
3750 if (!(*req)->ring) {
7c3df132
SK		 3751 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3752 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3753 goto fail_req_ring;
3754 }
3755 /* Allocate memory for response ring */
73208dfd
AC		 3756 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3757 if (!*rsp) {
7c3df132
SK		 3758 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3759 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3760 goto fail_rsp;
3761 }
73208dfd
AC		 3762 (*rsp)->hw = ha;
3763 (*rsp)->length = rsp_len;
3764 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3765 ((*rsp)->length + 1) * sizeof(response_t),
3766 &(*rsp)->dma, GFP_KERNEL);
3767 if (!(*rsp)->ring) {
7c3df132
SK		 3768 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3769 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3770 goto fail_rsp_ring;
3771 }
73208dfd
AC		 3772 (*req)->rsp = *rsp;
3773 (*rsp)->req = *req;
7c3df132
SK		 3774 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3775 "req=%p req->length=%d req->ring=%p rsp=%p "
3776 "rsp->length=%d rsp->ring=%p.\n",
3777 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3778 (*rsp)->ring);
73208dfd
AC		 3779 /* Allocate memory for NVRAM data for vports */
3780 if (ha->nvram_npiv_size) {
3781 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3782 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3783 if (!ha->npiv_info) {
7c3df132
SK		 3784 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3785 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3786 goto fail_npiv_info;
3787 }
3788 } else
3789 ha->npiv_info = NULL;
e8711085 3790
b64b0e8f 3791 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3792 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3793 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3794 &ha->ex_init_cb_dma);
3795 if (!ha->ex_init_cb)
3796 goto fail_ex_init_cb;
7c3df132
SK		 3797 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3798 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3799 }
3800
a9083016
GM		 3801 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3802
5ff1d584
AV		 3803 /* Get consistent memory allocated for Async Port-Database. */
3804 if (!IS_FWI2_CAPABLE(ha)) {
3805 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3806 &ha->async_pd_dma);
3807 if (!ha->async_pd)
3808 goto fail_async_pd;
7c3df132
SK		 3809 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3810 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3811 }
3812
e315cd28 3813 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3814
3815 /* Allocate memory for our loop_id bitmap */
3816 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3817 GFP_KERNEL);
3818 if (!ha->loop_id_map)
fc1ffd6c 3819 goto fail_loop_id_map;
5f16b331
CD		 3820 else {
3821 qla2x00_set_reserved_loop_ids(ha);
3822 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3823 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3824 }
3825
b2a72ec3 3826 return 0;
e315cd28 3827
fc1ffd6c
QT		 3828fail_loop_id_map:
3829 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 3830fail_async_pd:
3831 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3832fail_ex_init_cb:
3833 kfree(ha->npiv_info);
73208dfd
AC		 3834fail_npiv_info:
3835 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3836 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3837 (*rsp)->ring = NULL;
3838 (*rsp)->dma = 0;
e315cd28 3839fail_rsp_ring:
73208dfd 3840 kfree(*rsp);
e315cd28 3841fail_rsp:
73208dfd
AC		 3842 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3843 sizeof(request_t), (*req)->ring, (*req)->dma);
3844 (*req)->ring = NULL;
3845 (*req)->dma = 0;
e315cd28 3846fail_req_ring:
73208dfd 3847 kfree(*req);
e315cd28
AC		 3848fail_req:
3849 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3850 ha->ct_sns, ha->ct_sns_dma);
3851 ha->ct_sns = NULL;
3852 ha->ct_sns_dma = 0;
e8711085
AV		 3853fail_free_ms_iocb:
3854 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3855 ha->ms_iocb = NULL;
3856 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 3857
3858 if (ha->sns_cmd)
3859 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3860 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 3861fail_dma_pool:
bad75002 3862 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3863 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3864 ha->fcp_cmnd_dma_pool = NULL;
3865 }
3866fail_dl_dma_pool:
bad75002 3867 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3868 dma_pool_destroy(ha->dl_dma_pool);
3869 ha->dl_dma_pool = NULL;
3870 }
3871fail_s_dma_pool:
e315cd28
AC		 3872 dma_pool_destroy(ha->s_dma_pool);
3873 ha->s_dma_pool = NULL;
e8711085
AV		 3874fail_free_nvram:
3875 kfree(ha->nvram);
3876 ha->nvram = NULL;
a9083016 3877fail_free_ctx_mempool:
fc1ffd6c
QT		 3878 if (ha->ctx_mempool)
3879 mempool_destroy(ha->ctx_mempool);
a9083016 3880 ha->ctx_mempool = NULL;
e8711085 3881fail_free_srb_mempool:
fc1ffd6c
QT		 3882 if (ha->srb_mempool)
3883 mempool_destroy(ha->srb_mempool);
e8711085 3884 ha->srb_mempool = NULL;
e8711085 3885fail_free_gid_list:
642ef983
CD		 3886 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3887 ha->gid_list,
e315cd28 3888 ha->gid_list_dma);
e8711085
AV		 3889 ha->gid_list = NULL;
3890 ha->gid_list_dma = 0;
2d70c103
NB		 3891fail_free_tgt_mem:
3892 qlt_mem_free(ha);
e315cd28
AC		 3893fail_free_init_cb:
3894 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3895 ha->init_cb_dma);
3896 ha->init_cb = NULL;
3897 ha->init_cb_dma = 0;
e8711085 3898fail:
7c3df132
SK		 3899 ql_log(ql_log_fatal, NULL, 0x0030,
3900 "Memory allocation failure.\n");
e8711085 3901 return -ENOMEM;
1da177e4
LT		 3902}
3903
b0d6cabd
HM		 3904int
3905qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
3906{
3907 int rval;
3908 uint16_t size, max_cnt, temp;
3909 struct qla_hw_data *ha = vha->hw;
3910
3911 /* Return if we don't need to alloacate any extended logins */
3912 if (!ql2xexlogins)
3913 return QLA_SUCCESS;
3914
3915 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
3916 max_cnt = 0;
3917 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
3918 if (rval != QLA_SUCCESS) {
3919 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
3920 "Failed to get exlogin status.\n");
3921 return rval;
3922 }
3923
3924 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
3925 ha->exlogin_size = (size * temp);
3926 ql_log(ql_log_info, vha, 0xd024,
3927 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
3928 max_cnt, size, temp);
3929
3930 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n",
3931 ha->exlogin_size);
3932
3933 /* Get consistent memory for extended logins */
3934 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
3935 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
3936 if (!ha->exlogin_buf) {
3937 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
3938 "Failed to allocate memory for exlogin_buf_dma.\n");
3939 return -ENOMEM;
3940 }
3941
3942 /* Now configure the dma buffer */
3943 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
3944 if (rval) {
3945 ql_log(ql_log_fatal, vha, 0x00cf,
3946 "Setup extended login buffer ****FAILED****.\n");
3947 qla2x00_free_exlogin_buffer(ha);
3948 }
3949
3950 return rval;
3951}
3952
3953/*
3954* qla2x00_free_exlogin_buffer
3955*
3956* Input:
3957* ha = adapter block pointer
3958*/
3959void
3960qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
3961{
3962 if (ha->exlogin_buf) {
3963 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
3964 ha->exlogin_buf, ha->exlogin_buf_dma);
3965 ha->exlogin_buf = NULL;
3966 ha->exlogin_size = 0;
3967 }
3968}
3969
2f56a7f1
HM		 3970int
3971qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
3972{
3973 int rval;
3974 uint16_t size, max_cnt, temp;
3975 struct qla_hw_data *ha = vha->hw;
3976
3977 /* Return if we don't need to alloacate any extended logins */
3978 if (!ql2xexchoffld)
3979 return QLA_SUCCESS;
3980
3981 ql_log(ql_log_info, vha, 0xd014,
3982 "Exchange offload count: %d.\n", ql2xexlogins);
3983
3984 max_cnt = 0;
3985 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
3986 if (rval != QLA_SUCCESS) {
3987 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
3988 "Failed to get exlogin status.\n");
3989 return rval;
3990 }
3991
3992 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld;
3993 ha->exchoffld_size = (size * temp);
3994 ql_log(ql_log_info, vha, 0xd016,
3995 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
3996 max_cnt, size, temp);
3997
3998 ql_log(ql_log_info, vha, 0xd017,
3999 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size);
4000
4001 /* Get consistent memory for extended logins */
4002 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4003 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4004 if (!ha->exchoffld_buf) {
4005 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4006 "Failed to allocate memory for exchoffld_buf_dma.\n");
4007 return -ENOMEM;
4008 }
4009
4010 /* Now configure the dma buffer */
4011 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma);
4012 if (rval) {
4013 ql_log(ql_log_fatal, vha, 0xd02e,
4014 "Setup exchange offload buffer ****FAILED****.\n");
4015 qla2x00_free_exchoffld_buffer(ha);
4016 }
4017
4018 return rval;
4019}
4020
4021/*
4022* qla2x00_free_exchoffld_buffer
4023*
4024* Input:
4025* ha = adapter block pointer
4026*/
4027void
4028qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4029{
4030 if (ha->exchoffld_buf) {
4031 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4032 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4033 ha->exchoffld_buf = NULL;
4034 ha->exchoffld_size = 0;
4035 }
4036}
4037
1da177e4 4038/*
e30d1756
MI		 4039* qla2x00_free_fw_dump
4040* Frees fw dump stuff.
1da177e4
LT		 4041*
4042* Input:
7ec0effd 4043* ha = adapter block pointer
1da177e4 4044*/
a824ebb3 4045static void
e30d1756 4046qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4047{
df613b96 4048 if (ha->fce)
f73cb695
CD		 4049 dma_free_coherent(&ha->pdev->dev,
4050 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4051
f73cb695
CD		 4052 if (ha->eft)
4053 dma_free_coherent(&ha->pdev->dev,
4054 EFT_SIZE, ha->eft, ha->eft_dma);
4055
4056 if (ha->fw_dump)
a7a167bf 4057 vfree(ha->fw_dump);
f73cb695
CD		 4058 if (ha->fw_dump_template)
4059 vfree(ha->fw_dump_template);
4060
e30d1756
MI		 4061 ha->fce = NULL;
4062 ha->fce_dma = 0;
4063 ha->eft = NULL;
4064 ha->eft_dma = 0;
e30d1756 4065 ha->fw_dumped = 0;
61f098dd 4066 ha->fw_dump_cap_flags = 0;
e30d1756 4067 ha->fw_dump_reading = 0;
f73cb695
CD		 4068 ha->fw_dump = NULL;
4069 ha->fw_dump_len = 0;
4070 ha->fw_dump_template = NULL;
4071 ha->fw_dump_template_len = 0;
e30d1756
MI		 4072}
4073
4074/*
4075* qla2x00_mem_free
4076* Frees all adapter allocated memory.
4077*
4078* Input:
4079* ha = adapter block pointer.
4080*/
4081static void
4082qla2x00_mem_free(struct qla_hw_data *ha)
4083{
4084 qla2x00_free_fw_dump(ha);
4085
81178772
SK		 4086 if (ha->mctp_dump)
4087 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4088 ha->mctp_dump_dma);
4089
e30d1756
MI		 4090 if (ha->srb_mempool)
4091 mempool_destroy(ha->srb_mempool);
a7a167bf 4092
11bbc1d8
AV		 4093 if (ha->dcbx_tlv)
4094 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4095 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4096
ce0423f4
AV		 4097 if (ha->xgmac_data)
4098 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4099 ha->xgmac_data, ha->xgmac_data_dma);
4100
1da177e4
LT		 4101 if (ha->sns_cmd)
4102 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4103 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4104
4105 if (ha->ct_sns)
4106 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4107 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4108
88729e53
AV		 4109 if (ha->sfp_data)
4110 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
4111
1da177e4
LT		 4112 if (ha->ms_iocb)
4113 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4114
b64b0e8f 4115 if (ha->ex_init_cb)
a9083016
GM		 4116 dma_pool_free(ha->s_dma_pool,
4117 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4118
5ff1d584
AV		 4119 if (ha->async_pd)
4120 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4121
1da177e4
LT		 4122 if (ha->s_dma_pool)
4123 dma_pool_destroy(ha->s_dma_pool);
4124
1da177e4 4125 if (ha->gid_list)
642ef983
CD		 4126 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4127 ha->gid_list, ha->gid_list_dma);
1da177e4 4128
a9083016
GM		 4129 if (IS_QLA82XX(ha)) {
4130 if (!list_empty(&ha->gbl_dsd_list)) {
4131 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4132
4133 /* clean up allocated prev pool */
4134 list_for_each_entry_safe(dsd_ptr,
4135 tdsd_ptr, &ha->gbl_dsd_list, list) {
4136 dma_pool_free(ha->dl_dma_pool,
4137 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4138 list_del(&dsd_ptr->list);
4139 kfree(dsd_ptr);
4140 }
4141 }
4142 }
4143
4144 if (ha->dl_dma_pool)
4145 dma_pool_destroy(ha->dl_dma_pool);
4146
4147 if (ha->fcp_cmnd_dma_pool)
4148 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4149
4150 if (ha->ctx_mempool)
4151 mempool_destroy(ha->ctx_mempool);
4152
2d70c103
NB		 4153 qlt_mem_free(ha);
4154
e315cd28
AC		 4155 if (ha->init_cb)
4156 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4157 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4158 vfree(ha->optrom_buffer);
4159 kfree(ha->nvram);
73208dfd 4160 kfree(ha->npiv_info);
7a67735b 4161 kfree(ha->swl);
5f16b331 4162 kfree(ha->loop_id_map);
1da177e4 4163
e8711085 4164 ha->srb_mempool = NULL;
a9083016 4165 ha->ctx_mempool = NULL;
1da177e4
LT		 4166 ha->sns_cmd = NULL;
4167 ha->sns_cmd_dma = 0;
4168 ha->ct_sns = NULL;
4169 ha->ct_sns_dma = 0;
4170 ha->ms_iocb = NULL;
4171 ha->ms_iocb_dma = 0;
1da177e4
LT		 4172 ha->init_cb = NULL;
4173 ha->init_cb_dma = 0;
b64b0e8f
AV		 4174 ha->ex_init_cb = NULL;
4175 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4176 ha->async_pd = NULL;
4177 ha->async_pd_dma = 0;
1da177e4
LT		 4178
4179 ha->s_dma_pool = NULL;
a9083016
GM		 4180 ha->dl_dma_pool = NULL;
4181 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4182
1da177e4
LT		 4183 ha->gid_list = NULL;
4184 ha->gid_list_dma = 0;
2d70c103
NB		 4185
4186 ha->tgt.atio_ring = NULL;
4187 ha->tgt.atio_dma = 0;
4188 ha->tgt.tgt_vp_map = NULL;
e315cd28 4189}
1da177e4 4190
e315cd28
AC		 4191struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4192 struct qla_hw_data *ha)
4193{
4194 struct Scsi_Host *host;
4195 struct scsi_qla_host *vha = NULL;
854165f4 4196
e315cd28
AC		 4197 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
4198 if (host == NULL) {
7c3df132
SK		 4199 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4200 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 4201 goto fail;
4202 }
4203
4204 /* Clear our data area */
4205 vha = shost_priv(host);
4206 memset(vha, 0, sizeof(scsi_qla_host_t));
4207
4208 vha->host = host;
4209 vha->host_no = host->host_no;
4210 vha->hw = ha;
4211
4212 INIT_LIST_HEAD(&vha->vp_fcports);
4213 INIT_LIST_HEAD(&vha->work_list);
4214 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4215 INIT_LIST_HEAD(&vha->qla_cmd_list);
4216 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4217 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4218 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4219 INIT_LIST_HEAD(&vha->qp_list);
e315cd28 4220
f999f4c1 4221 spin_lock_init(&vha->work_lock);
8b2f5ff3 4222 spin_lock_init(&vha->cmd_list_lock);
f999f4c1 4223
e315cd28 4224 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4225 ql_dbg(ql_dbg_init, vha, 0x0041,
4226 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4227 vha->host, vha->hw, vha,
4228 dev_name(&(ha->pdev->dev)));
4229
e315cd28
AC		 4230 return vha;
4231
4232fail:
4233 return vha;
1da177e4
LT		 4234}
4235
01ef66bb 4236static struct qla_work_evt *
f999f4c1 4237qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4238{
4239 struct qla_work_evt *e;
feafb7b1
AE		 4240 uint8_t bail;
4241
4242 QLA_VHA_MARK_BUSY(vha, bail);
4243 if (bail)
4244 return NULL;
0971de7f 4245
f999f4c1 4246 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4247 if (!e) {
4248 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4249 return NULL;
feafb7b1 4250 }
0971de7f
AV		 4251
4252 INIT_LIST_HEAD(&e->list);
4253 e->type = type;
4254 e->flags = QLA_EVT_FLAG_FREE;
4255 return e;
4256}
4257
01ef66bb 4258static int
f999f4c1 4259qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4260{
f999f4c1 4261 unsigned long flags;
0971de7f 4262
f999f4c1 4263 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4264 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4265 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 4266 qla2xxx_wake_dpc(vha);
f999f4c1 4267
0971de7f
AV		 4268 return QLA_SUCCESS;
4269}
4270
4271int
e315cd28 4272qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4273 u32 data)
4274{
4275 struct qla_work_evt *e;
4276
f999f4c1 4277 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4278 if (!e)
4279 return QLA_FUNCTION_FAILED;
4280
4281 e->u.aen.code = code;
4282 e->u.aen.data = data;
f999f4c1 4283 return qla2x00_post_work(vha, e);
0971de7f
AV		 4284}
4285
8a659571
AV		 4286int
4287qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4288{
4289 struct qla_work_evt *e;
4290
f999f4c1 4291 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4292 if (!e)
4293 return QLA_FUNCTION_FAILED;
4294
4295 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4296 return qla2x00_post_work(vha, e);
8a659571
AV		 4297}
4298
ac280b67
AV		 4299#define qla2x00_post_async_work(name, type) \
4300int qla2x00_post_async_##name##_work( \
4301 struct scsi_qla_host *vha, \
4302 fc_port_t *fcport, uint16_t *data) \
4303{ \
4304 struct qla_work_evt *e; \
4305 \
4306 e = qla2x00_alloc_work(vha, type); \
4307 if (!e) \
4308 return QLA_FUNCTION_FAILED; \
4309 \
4310 e->u.logio.fcport = fcport; \
4311 if (data) { \
4312 e->u.logio.data[0] = data[0]; \
4313 e->u.logio.data[1] = data[1]; \
4314 } \
4315 return qla2x00_post_work(vha, e); \
4316}
4317
4318qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4319qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
4320qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4321qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4322qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4323qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4324
3420d36c
AV		 4325int
4326qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4327{
4328 struct qla_work_evt *e;
4329
4330 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4331 if (!e)
4332 return QLA_FUNCTION_FAILED;
4333
4334 e->u.uevent.code = code;
4335 return qla2x00_post_work(vha, e);
4336}
4337
4338static void
4339qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4340{
4341 char event_string[40];
4342 char *envp[] = { event_string, NULL };
4343
4344 switch (code) {
4345 case QLA_UEVENT_CODE_FW_DUMP:
4346 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4347 vha->host_no);
4348 break;
4349 default:
4350 /* do nothing */
4351 break;
4352 }
4353 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4354}
4355
8ae6d9c7
GM		 4356int
4357qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4358 uint32_t *data, int cnt)
4359{
4360 struct qla_work_evt *e;
4361
4362 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4363 if (!e)
4364 return QLA_FUNCTION_FAILED;
4365
4366 e->u.aenfx.evtcode = evtcode;
4367 e->u.aenfx.count = cnt;
4368 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4369 return qla2x00_post_work(vha, e);
4370}
4371
ac280b67 4372void
e315cd28 4373qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4374{
f999f4c1
AV		 4375 struct qla_work_evt *e, *tmp;
4376 unsigned long flags;
4377 LIST_HEAD(work);
0971de7f 4378
f999f4c1
AV		 4379 spin_lock_irqsave(&vha->work_lock, flags);
4380 list_splice_init(&vha->work_list, &work);
4381 spin_unlock_irqrestore(&vha->work_lock, flags);
4382
4383 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4384 list_del_init(&e->list);
0971de7f
AV		 4385
4386 switch (e->type) {
4387 case QLA_EVT_AEN:
e315cd28 4388 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4389 e->u.aen.code, e->u.aen.data);
4390 break;
8a659571
AV		 4391 case QLA_EVT_IDC_ACK:
4392 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4393 break;
ac280b67
AV		 4394 case QLA_EVT_ASYNC_LOGIN:
4395 qla2x00_async_login(vha, e->u.logio.fcport,
4396 e->u.logio.data);
4397 break;
4398 case QLA_EVT_ASYNC_LOGIN_DONE:
4399 qla2x00_async_login_done(vha, e->u.logio.fcport,
4400 e->u.logio.data);
4401 break;
4402 case QLA_EVT_ASYNC_LOGOUT:
4403 qla2x00_async_logout(vha, e->u.logio.fcport);
4404 break;
4405 case QLA_EVT_ASYNC_LOGOUT_DONE:
4406 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4407 e->u.logio.data);
4408 break;
5ff1d584
AV		 4409 case QLA_EVT_ASYNC_ADISC:
4410 qla2x00_async_adisc(vha, e->u.logio.fcport,
4411 e->u.logio.data);
4412 break;
4413 case QLA_EVT_ASYNC_ADISC_DONE:
4414 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4415 e->u.logio.data);
4416 break;
3420d36c
AV		 4417 case QLA_EVT_UEVENT:
4418 qla2x00_uevent_emit(vha, e->u.uevent.code);
4419 break;
8ae6d9c7
GM		 4420 case QLA_EVT_AENFX:
4421 qlafx00_process_aen(vha, e);
4422 break;
0971de7f
AV		 4423 }
4424 if (e->flags & QLA_EVT_FLAG_FREE)
4425 kfree(e);
feafb7b1
AE		 4426
4427 /* For each work completed decrement vha ref count */
4428 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4429 }
e315cd28 4430}
f999f4c1 4431
e315cd28
AC		 4432/* Relogins all the fcports of a vport
4433 * Context: dpc thread
4434 */
4435void qla2x00_relogin(struct scsi_qla_host *vha)
4436{
4437 fc_port_t *fcport;
c6b2fca8 4438 int status;
e315cd28
AC		 4439 uint16_t next_loopid = 0;
4440 struct qla_hw_data *ha = vha->hw;
ac280b67 4441 uint16_t data[2];
e315cd28
AC		 4442
4443 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4444 /*
4445 * If the port is not ONLINE then try to login
4446 * to it if we haven't run out of retries.
4447 */
5ff1d584
AV		 4448 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4449 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4450 fcport->login_retry--;
e315cd28 4451 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4452 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4453 ha->isp_ops->fabric_logout(vha,
4454 fcport->loop_id,
4455 fcport->d_id.b.domain,
4456 fcport->d_id.b.area,
4457 fcport->d_id.b.al_pa);
4458
03bcfb57
JC		 4459 if (fcport->loop_id == FC_NO_LOOP_ID) {
4460 fcport->loop_id = next_loopid =
4461 ha->min_external_loopid;
4462 status = qla2x00_find_new_loop_id(
4463 vha, fcport);
4464 if (status != QLA_SUCCESS) {
4465 /* Ran out of IDs to use */
4466 break;
4467 }
4468 }
4469
ac280b67 4470 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4471 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4472 data[0] = 0;
4473 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4474 status = qla2x00_post_async_login_work(
4475 vha, fcport, data);
4476 if (status == QLA_SUCCESS)
4477 continue;
4478 /* Attempt a retry. */
4479 status = 1;
aaf4d3e2 4480 } else {
ac280b67
AV		 4481 status = qla2x00_fabric_login(vha,
4482 fcport, &next_loopid);
aaf4d3e2
SK		 4483 if (status == QLA_SUCCESS) {
4484 int status2;
4485 uint8_t opts;
4486
4487 opts = 0;
4488 if (fcport->flags &
4489 FCF_FCP2_DEVICE)
4490 opts |= BIT_1;
03003960
SK		 4491 status2 =
4492 qla2x00_get_port_database(
4493 vha, fcport, opts);
aaf4d3e2
SK		 4494 if (status2 != QLA_SUCCESS)
4495 status = 1;
4496 }
4497 }
e315cd28
AC		 4498 } else
4499 status = qla2x00_local_device_login(vha,
4500 fcport);
4501
e315cd28
AC		 4502 if (status == QLA_SUCCESS) {
4503 fcport->old_loop_id = fcport->loop_id;
4504
7c3df132
SK		 4505 ql_dbg(ql_dbg_disc, vha, 0x2003,
4506 "Port login OK: logged in ID 0x%x.\n",
4507 fcport->loop_id);
e315cd28
AC		 4508
4509 qla2x00_update_fcport(vha, fcport);
4510
4511 } else if (status == 1) {
4512 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4513 /* retry the login again */
7c3df132
SK		 4514 ql_dbg(ql_dbg_disc, vha, 0x2007,
4515 "Retrying %d login again loop_id 0x%x.\n",
4516 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4517 } else {
4518 fcport->login_retry = 0;
4519 }
4520
4521 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4522 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4523 }
4524 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4525 break;
0971de7f 4526 }
0971de7f
AV		 4527}
4528
7d613ac6
SV		 4529/* Schedule work on any of the dpc-workqueues */
4530void
4531qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4532{
4533 struct qla_hw_data *ha = base_vha->hw;
4534
4535 switch (work_code) {
4536 case MBA_IDC_AEN: /* 0x8200 */
4537 if (ha->dpc_lp_wq)
4538 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4539 break;
4540
4541 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4542 if (!ha->flags.nic_core_reset_hdlr_active) {
4543 if (ha->dpc_hp_wq)
4544 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4545 } else
4546 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4547 "NIC Core reset is already active. Skip "
4548 "scheduling it again.\n");
4549 break;
4550 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4551 if (ha->dpc_hp_wq)
4552 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4553 break;
4554 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4555 if (ha->dpc_hp_wq)
4556 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4557 break;
4558 default:
4559 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4560 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4561 }
4562
4563 return;
4564}
4565
4566/* Work: Perform NIC Core Unrecoverable state handling */
4567void
4568qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4569{
4570 struct qla_hw_data *ha =
2ad1b67c 4571 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4572 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4573 uint32_t dev_state = 0;
4574
4575 qla83xx_idc_lock(base_vha, 0);
4576 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4577 qla83xx_reset_ownership(base_vha);
4578 if (ha->flags.nic_core_reset_owner) {
4579 ha->flags.nic_core_reset_owner = 0;
4580 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4581 QLA8XXX_DEV_FAILED);
4582 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4583 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4584 }
4585 qla83xx_idc_unlock(base_vha, 0);
4586}
4587
4588/* Work: Execute IDC state handler */
4589void
4590qla83xx_idc_state_handler_work(struct work_struct *work)
4591{
4592 struct qla_hw_data *ha =
2ad1b67c 4593 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4594 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4595 uint32_t dev_state = 0;
4596
4597 qla83xx_idc_lock(base_vha, 0);
4598 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4599 if (dev_state == QLA8XXX_DEV_FAILED ||
4600 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4601 qla83xx_idc_state_handler(base_vha);
4602 qla83xx_idc_unlock(base_vha, 0);
4603}
4604
fa492630 4605static int
7d613ac6
SV		 4606qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4607{
4608 int rval = QLA_SUCCESS;
4609 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4610 uint32_t heart_beat_counter1, heart_beat_counter2;
4611
4612 do {
4613 if (time_after(jiffies, heart_beat_wait)) {
4614 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4615 "Nic Core f/w is not alive.\n");
4616 rval = QLA_FUNCTION_FAILED;
4617 break;
4618 }
4619
4620 qla83xx_idc_lock(base_vha, 0);
4621 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4622 &heart_beat_counter1);
4623 qla83xx_idc_unlock(base_vha, 0);
4624 msleep(100);
4625 qla83xx_idc_lock(base_vha, 0);
4626 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4627 &heart_beat_counter2);
4628 qla83xx_idc_unlock(base_vha, 0);
4629 } while (heart_beat_counter1 == heart_beat_counter2);
4630
4631 return rval;
4632}
4633
4634/* Work: Perform NIC Core Reset handling */
4635void
4636qla83xx_nic_core_reset_work(struct work_struct *work)
4637{
4638 struct qla_hw_data *ha =
4639 container_of(work, struct qla_hw_data, nic_core_reset);
4640 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4641 uint32_t dev_state = 0;
4642
81178772
SK		 4643 if (IS_QLA2031(ha)) {
4644 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4645 ql_log(ql_log_warn, base_vha, 0xb081,
4646 "Failed to dump mctp\n");
4647 return;
4648 }
4649
7d613ac6
SV		 4650 if (!ha->flags.nic_core_reset_hdlr_active) {
4651 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4652 qla83xx_idc_lock(base_vha, 0);
4653 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4654 &dev_state);
4655 qla83xx_idc_unlock(base_vha, 0);
4656 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4657 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4658 "Nic Core f/w is alive.\n");
4659 return;
4660 }
4661 }
4662
4663 ha->flags.nic_core_reset_hdlr_active = 1;
4664 if (qla83xx_nic_core_reset(base_vha)) {
4665 /* NIC Core reset failed. */
4666 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4667 "NIC Core reset failed.\n");
4668 }
4669 ha->flags.nic_core_reset_hdlr_active = 0;
4670 }
4671}
4672
4673/* Work: Handle 8200 IDC aens */
4674void
4675qla83xx_service_idc_aen(struct work_struct *work)
4676{
4677 struct qla_hw_data *ha =
4678 container_of(work, struct qla_hw_data, idc_aen);
4679 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4680 uint32_t dev_state, idc_control;
4681
4682 qla83xx_idc_lock(base_vha, 0);
4683 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4684 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4685 qla83xx_idc_unlock(base_vha, 0);
4686 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4687 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4688 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4689 "Application requested NIC Core Reset.\n");
4690 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4691 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4692 QLA_SUCCESS) {
4693 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4694 "Other protocol driver requested NIC Core Reset.\n");
4695 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4696 }
4697 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4698 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4699 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4700 }
4701}
4702
4703static void
4704qla83xx_wait_logic(void)
4705{
4706 int i;
4707
4708 /* Yield CPU */
4709 if (!in_interrupt()) {
4710 /*
4711 * Wait about 200ms before retrying again.
4712 * This controls the number of retries for single
4713 * lock operation.
4714 */
4715 msleep(100);
4716 schedule();
4717 } else {
4718 for (i = 0; i < 20; i++)
4719 cpu_relax(); /* This a nop instr on i386 */
4720 }
4721}
4722
fa492630 4723static int
7d613ac6
SV		 4724qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4725{
4726 int rval;
4727 uint32_t data;
4728 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4729 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4730 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4731 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4732 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4733
4734 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4735 if (rval)
4736 return rval;
4737
4738 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4739 return QLA_SUCCESS;
4740 } else {
4741 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4742 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4743 data);
4744 if (rval)
4745 return rval;
4746
4747 msleep(200);
4748
4749 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4750 &data);
4751 if (rval)
4752 return rval;
4753
4754 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4755 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4756 ~(idc_lck_rcvry_stage_mask));
4757 rval = qla83xx_wr_reg(base_vha,
4758 QLA83XX_IDC_LOCK_RECOVERY, data);
4759 if (rval)
4760 return rval;
4761
4762 /* Forcefully perform IDC UnLock */
4763 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4764 &data);
4765 if (rval)
4766 return rval;
4767 /* Clear lock-id by setting 0xff */
4768 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4769 0xff);
4770 if (rval)
4771 return rval;
4772 /* Clear lock-recovery by setting 0x0 */
4773 rval = qla83xx_wr_reg(base_vha,
4774 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4775 if (rval)
4776 return rval;
4777 } else
4778 return QLA_SUCCESS;
4779 }
4780
4781 return rval;
4782}
4783
fa492630 4784static int
7d613ac6
SV		 4785qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4786{
4787 int rval = QLA_SUCCESS;
4788 uint32_t o_drv_lockid, n_drv_lockid;
4789 unsigned long lock_recovery_timeout;
4790
4791 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4792retry_lockid:
4793 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4794 if (rval)
4795 goto exit;
4796
4797 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4798 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4799 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4800 return QLA_SUCCESS;
4801 else
4802 return QLA_FUNCTION_FAILED;
4803 }
4804
4805 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4806 if (rval)
4807 goto exit;
4808
4809 if (o_drv_lockid == n_drv_lockid) {
4810 qla83xx_wait_logic();
4811 goto retry_lockid;
4812 } else
4813 return QLA_SUCCESS;
4814
4815exit:
4816 return rval;
4817}
4818
4819void
4820qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4821{
4822 uint16_t options = (requester_id << 15) | BIT_6;
4823 uint32_t data;
6c315553 4824 uint32_t lock_owner;
7d613ac6
SV		 4825 struct qla_hw_data *ha = base_vha->hw;
4826
4827 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4828retry_lock:
4829 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4830 == QLA_SUCCESS) {
4831 if (data) {
4832 /* Setting lock-id to our function-number */
4833 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4834 ha->portnum);
4835 } else {
6c315553
SK		 4836 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4837 &lock_owner);
7d613ac6 4838 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4839 "Failed to acquire IDC lock, acquired by %d, "
4840 "retrying...\n", lock_owner);
7d613ac6
SV		 4841
4842 /* Retry/Perform IDC-Lock recovery */
4843 if (qla83xx_idc_lock_recovery(base_vha)
4844 == QLA_SUCCESS) {
4845 qla83xx_wait_logic();
4846 goto retry_lock;
4847 } else
4848 ql_log(ql_log_warn, base_vha, 0xb075,
4849 "IDC Lock recovery FAILED.\n");
4850 }
4851
4852 }
4853
4854 return;
4855
4856 /* XXX: IDC-lock implementation using access-control mbx */
4857retry_lock2:
4858 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4859 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4860 "Failed to acquire IDC lock. retrying...\n");
4861 /* Retry/Perform IDC-Lock recovery */
4862 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4863 qla83xx_wait_logic();
4864 goto retry_lock2;
4865 } else
4866 ql_log(ql_log_warn, base_vha, 0xb076,
4867 "IDC Lock recovery FAILED.\n");
4868 }
4869
4870 return;
4871}
4872
4873void
4874qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4875{
5897cb2f
BVA		 4876#if 0
4877 uint16_t options = (requester_id << 15) | BIT_7;
4878#endif
4879 uint16_t retry;
7d613ac6
SV		 4880 uint32_t data;
4881 struct qla_hw_data *ha = base_vha->hw;
4882
4883 /* IDC-unlock implementation using driver-unlock/lock-id
4884 * remote registers
4885 */
4886 retry = 0;
4887retry_unlock:
4888 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4889 == QLA_SUCCESS) {
4890 if (data == ha->portnum) {
4891 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4892 /* Clearing lock-id by setting 0xff */
4893 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4894 } else if (retry < 10) {
4895 /* SV: XXX: IDC unlock retrying needed here? */
4896
4897 /* Retry for IDC-unlock */
4898 qla83xx_wait_logic();
4899 retry++;
4900 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 4901 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 4902 goto retry_unlock;
4903 }
4904 } else if (retry < 10) {
4905 /* Retry for IDC-unlock */
4906 qla83xx_wait_logic();
4907 retry++;
4908 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 4909 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 4910 goto retry_unlock;
4911 }
4912
4913 return;
4914
5897cb2f 4915#if 0
7d613ac6
SV		 4916 /* XXX: IDC-unlock implementation using access-control mbx */
4917 retry = 0;
4918retry_unlock2:
4919 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4920 if (retry < 10) {
4921 /* Retry for IDC-unlock */
4922 qla83xx_wait_logic();
4923 retry++;
4924 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 4925 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 4926 goto retry_unlock2;
4927 }
4928 }
4929
4930 return;
5897cb2f 4931#endif
7d613ac6
SV		 4932}
4933
4934int
4935__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4936{
4937 int rval = QLA_SUCCESS;
4938 struct qla_hw_data *ha = vha->hw;
4939 uint32_t drv_presence;
4940
4941 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4942 if (rval == QLA_SUCCESS) {
4943 drv_presence |= (1 << ha->portnum);
4944 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4945 drv_presence);
4946 }
4947
4948 return rval;
4949}
4950
4951int
4952qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4953{
4954 int rval = QLA_SUCCESS;
4955
4956 qla83xx_idc_lock(vha, 0);
4957 rval = __qla83xx_set_drv_presence(vha);
4958 qla83xx_idc_unlock(vha, 0);
4959
4960 return rval;
4961}
4962
4963int
4964__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4965{
4966 int rval = QLA_SUCCESS;
4967 struct qla_hw_data *ha = vha->hw;
4968 uint32_t drv_presence;
4969
4970 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4971 if (rval == QLA_SUCCESS) {
4972 drv_presence &= ~(1 << ha->portnum);
4973 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4974 drv_presence);
4975 }
4976
4977 return rval;
4978}
4979
4980int
4981qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4982{
4983 int rval = QLA_SUCCESS;
4984
4985 qla83xx_idc_lock(vha, 0);
4986 rval = __qla83xx_clear_drv_presence(vha);
4987 qla83xx_idc_unlock(vha, 0);
4988
4989 return rval;
4990}
4991
fa492630 4992static void
7d613ac6
SV		 4993qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4994{
4995 struct qla_hw_data *ha = vha->hw;
4996 uint32_t drv_ack, drv_presence;
4997 unsigned long ack_timeout;
4998
4999 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5000 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5001 while (1) {
5002 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5003 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5004 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5005 break;
5006
5007 if (time_after_eq(jiffies, ack_timeout)) {
5008 ql_log(ql_log_warn, vha, 0xb067,
5009 "RESET ACK TIMEOUT! drv_presence=0x%x "
5010 "drv_ack=0x%x\n", drv_presence, drv_ack);
5011 /*
5012 * The function(s) which did not ack in time are forced
5013 * to withdraw any further participation in the IDC
5014 * reset.
5015 */
5016 if (drv_ack != drv_presence)
5017 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5018 drv_ack);
5019 break;
5020 }
5021
5022 qla83xx_idc_unlock(vha, 0);
5023 msleep(1000);
5024 qla83xx_idc_lock(vha, 0);
5025 }
5026
5027 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5028 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5029}
5030
fa492630 5031static int
7d613ac6
SV		 5032qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5033{
5034 int rval = QLA_SUCCESS;
5035 uint32_t idc_control;
5036
5037 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5038 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5039
5040 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5041 __qla83xx_get_idc_control(vha, &idc_control);
5042 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5043 __qla83xx_set_idc_control(vha, 0);
5044
5045 qla83xx_idc_unlock(vha, 0);
5046 rval = qla83xx_restart_nic_firmware(vha);
5047 qla83xx_idc_lock(vha, 0);
5048
5049 if (rval != QLA_SUCCESS) {
5050 ql_log(ql_log_fatal, vha, 0xb06a,
5051 "Failed to restart NIC f/w.\n");
5052 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5053 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5054 } else {
5055 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5056 "Success in restarting nic f/w.\n");
5057 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5058 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5059 }
5060
5061 return rval;
5062}
5063
5064/* Assumes idc_lock always held on entry */
5065int
5066qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5067{
5068 struct qla_hw_data *ha = base_vha->hw;
5069 int rval = QLA_SUCCESS;
5070 unsigned long dev_init_timeout;
5071 uint32_t dev_state;
5072
5073 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5074 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5075
5076 while (1) {
5077
5078 if (time_after_eq(jiffies, dev_init_timeout)) {
5079 ql_log(ql_log_warn, base_vha, 0xb06e,
5080 "Initialization TIMEOUT!\n");
5081 /* Init timeout. Disable further NIC Core
5082 * communication.
5083 */
5084 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5085 QLA8XXX_DEV_FAILED);
5086 ql_log(ql_log_info, base_vha, 0xb06f,
5087 "HW State: FAILED.\n");
5088 }
5089
5090 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5091 switch (dev_state) {
5092 case QLA8XXX_DEV_READY:
5093 if (ha->flags.nic_core_reset_owner)
5094 qla83xx_idc_audit(base_vha,
5095 IDC_AUDIT_COMPLETION);
5096 ha->flags.nic_core_reset_owner = 0;
5097 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5098 "Reset_owner reset by 0x%x.\n",
5099 ha->portnum);
5100 goto exit;
5101 case QLA8XXX_DEV_COLD:
5102 if (ha->flags.nic_core_reset_owner)
5103 rval = qla83xx_device_bootstrap(base_vha);
5104 else {
5105 /* Wait for AEN to change device-state */
5106 qla83xx_idc_unlock(base_vha, 0);
5107 msleep(1000);
5108 qla83xx_idc_lock(base_vha, 0);
5109 }
5110 break;
5111 case QLA8XXX_DEV_INITIALIZING:
5112 /* Wait for AEN to change device-state */
5113 qla83xx_idc_unlock(base_vha, 0);
5114 msleep(1000);
5115 qla83xx_idc_lock(base_vha, 0);
5116 break;
5117 case QLA8XXX_DEV_NEED_RESET:
5118 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5119 qla83xx_need_reset_handler(base_vha);
5120 else {
5121 /* Wait for AEN to change device-state */
5122 qla83xx_idc_unlock(base_vha, 0);
5123 msleep(1000);
5124 qla83xx_idc_lock(base_vha, 0);
5125 }
5126 /* reset timeout value after need reset handler */
5127 dev_init_timeout = jiffies +
5128 (ha->fcoe_dev_init_timeout * HZ);
5129 break;
5130 case QLA8XXX_DEV_NEED_QUIESCENT:
5131 /* XXX: DEBUG for now */
5132 qla83xx_idc_unlock(base_vha, 0);
5133 msleep(1000);
5134 qla83xx_idc_lock(base_vha, 0);
5135 break;
5136 case QLA8XXX_DEV_QUIESCENT:
5137 /* XXX: DEBUG for now */
5138 if (ha->flags.quiesce_owner)
5139 goto exit;
5140
5141 qla83xx_idc_unlock(base_vha, 0);
5142 msleep(1000);
5143 qla83xx_idc_lock(base_vha, 0);
5144 dev_init_timeout = jiffies +
5145 (ha->fcoe_dev_init_timeout * HZ);
5146 break;
5147 case QLA8XXX_DEV_FAILED:
5148 if (ha->flags.nic_core_reset_owner)
5149 qla83xx_idc_audit(base_vha,
5150 IDC_AUDIT_COMPLETION);
5151 ha->flags.nic_core_reset_owner = 0;
5152 __qla83xx_clear_drv_presence(base_vha);
5153 qla83xx_idc_unlock(base_vha, 0);
5154 qla8xxx_dev_failed_handler(base_vha);
5155 rval = QLA_FUNCTION_FAILED;
5156 qla83xx_idc_lock(base_vha, 0);
5157 goto exit;
5158 case QLA8XXX_BAD_VALUE:
5159 qla83xx_idc_unlock(base_vha, 0);
5160 msleep(1000);
5161 qla83xx_idc_lock(base_vha, 0);
5162 break;
5163 default:
5164 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5165 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5166 qla83xx_idc_unlock(base_vha, 0);
5167 qla8xxx_dev_failed_handler(base_vha);
5168 rval = QLA_FUNCTION_FAILED;
5169 qla83xx_idc_lock(base_vha, 0);
5170 goto exit;
5171 }
5172 }
5173
5174exit:
5175 return rval;
5176}
5177
f3ddac19
CD		 5178void
5179qla2x00_disable_board_on_pci_error(struct work_struct *work)
5180{
5181 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5182 board_disable);
5183 struct pci_dev *pdev = ha->pdev;
5184 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5185
783e0dc4
SC		 5186 /* if UNLOAD flag is already set, then continue unload,
5187 * where it was set first.
5188 */
5189 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5190 return;
5191
f3ddac19
CD		 5192 ql_log(ql_log_warn, base_vha, 0x015b,
5193 "Disabling adapter.\n");
5194
5195 set_bit(UNLOADING, &base_vha->dpc_flags);
5196
5197 qla2x00_delete_all_vps(ha, base_vha);
5198
5199 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5200
5201 qla2x00_dfs_remove(base_vha);
5202
5203 qla84xx_put_chip(base_vha);
5204
5205 if (base_vha->timer_active)
5206 qla2x00_stop_timer(base_vha);
5207
5208 base_vha->flags.online = 0;
5209
5210 qla2x00_destroy_deferred_work(ha);
5211
5212 /*
5213 * Do not try to stop beacon blink as it will issue a mailbox
5214 * command.
5215 */
5216 qla2x00_free_sysfs_attr(base_vha, false);
5217
5218 fc_remove_host(base_vha->host);
5219
5220 scsi_remove_host(base_vha->host);
5221
5222 base_vha->flags.init_done = 0;
5223 qla25xx_delete_queues(base_vha);
f3ddac19 5224 qla2x00_free_fcports(base_vha);
093df737 5225 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5226 qla2x00_mem_free(ha);
5227 qla82xx_md_free(base_vha);
5228 qla2x00_free_queues(ha);
5229
f3ddac19
CD		 5230 qla2x00_unmap_iobases(ha);
5231
5232 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5233 pci_disable_pcie_error_reporting(pdev);
5234 pci_disable_device(pdev);
f3ddac19 5235
beb9e315
JL		 5236 /*
5237 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5238 */
f3ddac19
CD		 5239}
5240
1da177e4
LT		 5241/**************************************************************************
5242* qla2x00_do_dpc
5243* This kernel thread is a task that is schedule by the interrupt handler
5244* to perform the background processing for interrupts.
5245*
5246* Notes:
5247* This task always run in the context of a kernel thread. It
5248* is kick-off by the driver's detect code and starts up
5249* up one per adapter. It immediately goes to sleep and waits for
5250* some fibre event. When either the interrupt handler or
5251* the timer routine detects a event it will one of the task
5252* bits then wake us up.
5253**************************************************************************/
5254static int
5255qla2x00_do_dpc(void *data)
5256{
e315cd28
AC		 5257 scsi_qla_host_t *base_vha;
5258 struct qla_hw_data *ha;
d7459527
MH		 5259 uint32_t online;
5260 struct qla_qpair *qpair;
1da177e4 5261
e315cd28
AC		 5262 ha = (struct qla_hw_data *)data;
5263 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5264
8698a745 5265 set_user_nice(current, MIN_NICE);
1da177e4 5266
563585ec 5267 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5268 while (!kthread_should_stop()) {
7c3df132
SK		 5269 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5270 "DPC handler sleeping.\n");
1da177e4 5271
39a11240 5272 schedule();
1da177e4 5273
c142caf0
AV		 5274 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5275 goto end_loop;
1da177e4 5276
85880801 5277 if (ha->flags.eeh_busy) {
7c3df132
SK		 5278 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5279 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5280 goto end_loop;
85880801
AV		 5281 }
5282
1da177e4
LT		 5283 ha->dpc_active = 1;
5284
5f28d2d7
SK		 5285 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5286 "DPC handler waking up, dpc_flags=0x%lx.\n",
5287 base_vha->dpc_flags);
1da177e4 5288
a29b3dd7
JC		 5289 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5290 break;
5291
e315cd28 5292 qla2x00_do_work(base_vha);
0971de7f 5293
7ec0effd
AD		 5294 if (IS_P3P_TYPE(ha)) {
5295 if (IS_QLA8044(ha)) {
5296 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5297 &base_vha->dpc_flags)) {
5298 qla8044_idc_lock(ha);
5299 qla8044_wr_direct(base_vha,
5300 QLA8044_CRB_DEV_STATE_INDEX,
5301 QLA8XXX_DEV_FAILED);
5302 qla8044_idc_unlock(ha);
5303 ql_log(ql_log_info, base_vha, 0x4004,
5304 "HW State: FAILED.\n");
5305 qla8044_device_state_handler(base_vha);
5306 continue;
5307 }
5308
5309 } else {
5310 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5311 &base_vha->dpc_flags)) {
5312 qla82xx_idc_lock(ha);
5313 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5314 QLA8XXX_DEV_FAILED);
5315 qla82xx_idc_unlock(ha);
5316 ql_log(ql_log_info, base_vha, 0x0151,
5317 "HW State: FAILED.\n");
5318 qla82xx_device_state_handler(base_vha);
5319 continue;
5320 }
a9083016
GM		 5321 }
5322
5323 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5324 &base_vha->dpc_flags)) {
5325
7c3df132
SK		 5326 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5327 "FCoE context reset scheduled.\n");
a9083016
GM		 5328 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5329 &base_vha->dpc_flags))) {
5330 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5331 /* FCoE-ctx reset failed.
5332 * Escalate to chip-reset
5333 */
5334 set_bit(ISP_ABORT_NEEDED,
5335 &base_vha->dpc_flags);
5336 }
5337 clear_bit(ABORT_ISP_ACTIVE,
5338 &base_vha->dpc_flags);
5339 }
5340
7c3df132
SK		 5341 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5342 "FCoE context reset end.\n");
a9083016 5343 }
8ae6d9c7
GM		 5344 } else if (IS_QLAFX00(ha)) {
5345 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5346 &base_vha->dpc_flags)) {
5347 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5348 "Firmware Reset Recovery\n");
5349 if (qlafx00_reset_initialize(base_vha)) {
5350 /* Failed. Abort isp later. */
5351 if (!test_bit(UNLOADING,
f92f82d6 5352 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5353 set_bit(ISP_UNRECOVERABLE,
5354 &base_vha->dpc_flags);
5355 ql_dbg(ql_dbg_dpc, base_vha,
5356 0x4021,
5357 "Reset Recovery Failed\n");
f92f82d6 5358 }
8ae6d9c7
GM		 5359 }
5360 }
5361
5362 if (test_and_clear_bit(FX00_TARGET_SCAN,
5363 &base_vha->dpc_flags)) {
5364 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5365 "ISPFx00 Target Scan scheduled\n");
5366 if (qlafx00_rescan_isp(base_vha)) {
5367 if (!test_bit(UNLOADING,
5368 &base_vha->dpc_flags))
5369 set_bit(ISP_UNRECOVERABLE,
5370 &base_vha->dpc_flags);
5371 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5372 "ISPFx00 Target Scan Failed\n");
5373 }
5374 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5375 "ISPFx00 Target Scan End\n");
5376 }
e8f5e95d
AB		 5377 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5378 &base_vha->dpc_flags)) {
5379 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5380 "ISPFx00 Host Info resend scheduled\n");
5381 qlafx00_fx_disc(base_vha,
5382 &base_vha->hw->mr.fcport,
5383 FXDISC_REG_HOST_INFO);
5384 }
a9083016
GM		 5385 }
5386
e315cd28
AC		 5387 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5388 &base_vha->dpc_flags)) {
1da177e4 5389
7c3df132
SK		 5390 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5391 "ISP abort scheduled.\n");
1da177e4 5392 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5393 &base_vha->dpc_flags))) {
1da177e4 5394
a9083016 5395 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5396 /* failed. retry later */
5397 set_bit(ISP_ABORT_NEEDED,
e315cd28 5398 &base_vha->dpc_flags);
99363ef8 5399 }
e315cd28
AC		 5400 clear_bit(ABORT_ISP_ACTIVE,
5401 &base_vha->dpc_flags);
99363ef8
SJ		 5402 }
5403
7c3df132
SK		 5404 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5405 "ISP abort end.\n");
1da177e4
LT		 5406 }
5407
a394aac8
DJ		 5408 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5409 &base_vha->dpc_flags)) {
e315cd28 5410 qla2x00_update_fcports(base_vha);
c9c5ced9 5411 }
d97994dc 5412
2d70c103
NB		 5413 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
5414 int ret;
5415 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
5416 if (ret != QLA_SUCCESS)
5417 ql_log(ql_log_warn, base_vha, 0x121,
5418 "Failed to enable receiving of RSCN "
5419 "requests: 0x%x.\n", ret);
5420 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
5421 }
5422
8ae6d9c7
GM		 5423 if (IS_QLAFX00(ha))
5424 goto loop_resync_check;
5425
579d12b5 5426 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5427 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5428 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5429 if (IS_P3P_TYPE(ha)) {
5430 if (IS_QLA82XX(ha))
5431 qla82xx_device_state_handler(base_vha);
5432 if (IS_QLA8044(ha))
5433 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5434 clear_bit(ISP_QUIESCE_NEEDED,
5435 &base_vha->dpc_flags);
5436 if (!ha->flags.quiesce_owner) {
5437 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5438 if (IS_QLA82XX(ha)) {
5439 qla82xx_idc_lock(ha);
5440 qla82xx_clear_qsnt_ready(
5441 base_vha);
5442 qla82xx_idc_unlock(ha);
5443 } else if (IS_QLA8044(ha)) {
5444 qla8044_idc_lock(ha);
5445 qla8044_clear_qsnt_ready(
5446 base_vha);
5447 qla8044_idc_unlock(ha);
5448 }
8fcd6b8b
CD		 5449 }
5450 } else {
5451 clear_bit(ISP_QUIESCE_NEEDED,
5452 &base_vha->dpc_flags);
5453 qla2x00_quiesce_io(base_vha);
579d12b5 5454 }
7c3df132
SK		 5455 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5456 "Quiescence mode end.\n");
579d12b5
SK		 5457 }
5458
e315cd28 5459 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5460 &base_vha->dpc_flags) &&
e315cd28 5461 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5462
7c3df132
SK		 5463 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5464 "Reset marker scheduled.\n");
e315cd28
AC		 5465 qla2x00_rst_aen(base_vha);
5466 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5467 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5468 "Reset marker end.\n");
1da177e4
LT		 5469 }
5470
5471 /* Retry each device up to login retry count */
e315cd28
AC		 5472 if ((test_and_clear_bit(RELOGIN_NEEDED,
5473 &base_vha->dpc_flags)) &&
5474 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5475 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5476
7c3df132
SK		 5477 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5478 "Relogin scheduled.\n");
e315cd28 5479 qla2x00_relogin(base_vha);
7c3df132
SK		 5480 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5481 "Relogin end.\n");
1da177e4 5482 }
8ae6d9c7 5483loop_resync_check:
e315cd28 5484 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5485 &base_vha->dpc_flags)) {
1da177e4 5486
7c3df132
SK		 5487 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5488 "Loop resync scheduled.\n");
1da177e4
LT		 5489
5490 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5491 &base_vha->dpc_flags))) {
1da177e4 5492
52c82823 5493 qla2x00_loop_resync(base_vha);
1da177e4 5494
e315cd28
AC		 5495 clear_bit(LOOP_RESYNC_ACTIVE,
5496 &base_vha->dpc_flags);
1da177e4
LT		 5497 }
5498
7c3df132
SK		 5499 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5500 "Loop resync end.\n");
1da177e4
LT		 5501 }
5502
8ae6d9c7
GM		 5503 if (IS_QLAFX00(ha))
5504 goto intr_on_check;
5505
e315cd28
AC		 5506 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5507 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5508 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5509 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5510 }
5511
8ae6d9c7 5512intr_on_check:
1da177e4 5513 if (!ha->interrupts_on)
fd34f556 5514 ha->isp_ops->enable_intrs(ha);
1da177e4 5515
e315cd28 5516 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5517 &base_vha->dpc_flags)) {
5518 if (ha->beacon_blink_led == 1)
5519 ha->isp_ops->beacon_blink(base_vha);
5520 }
f6df144c 5521
d7459527
MH		 5522 /* qpair online check */
5523 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5524 &base_vha->dpc_flags)) {
5525 if (ha->flags.eeh_busy ||
5526 ha->flags.pci_channel_io_perm_failure)
5527 online = 0;
5528 else
5529 online = 1;
5530
5531 mutex_lock(&ha->mq_lock);
5532 list_for_each_entry(qpair, &base_vha->qp_list,
5533 qp_list_elem)
5534 qpair->online = online;
5535 mutex_unlock(&ha->mq_lock);
5536 }
5537
8ae6d9c7
GM		 5538 if (!IS_QLAFX00(ha))
5539 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5540
1da177e4 5541 ha->dpc_active = 0;
c142caf0 5542end_loop:
563585ec 5543 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5544 } /* End of while(1) */
563585ec 5545 __set_current_state(TASK_RUNNING);
1da177e4 5546
7c3df132
SK		 5547 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5548 "DPC handler exiting.\n");
1da177e4
LT		 5549
5550 /*
5551 * Make sure that nobody tries to wake us up again.
5552 */
1da177e4
LT		 5553 ha->dpc_active = 0;
5554
ac280b67
AV		 5555 /* Cleanup any residual CTX SRBs. */
5556 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5557
39a11240
CH		 5558 return 0;
5559}
5560
5561void
e315cd28 5562qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5563{
e315cd28 5564 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5565 struct task_struct *t = ha->dpc_thread;
5566
e315cd28 5567 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5568 wake_up_process(t);
1da177e4
LT		 5569}
5570
1da177e4
LT		 5571/*
5572* qla2x00_rst_aen
5573* Processes asynchronous reset.
5574*
5575* Input:
5576* ha = adapter block pointer.
5577*/
5578static void
e315cd28 5579qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5580{
e315cd28
AC		 5581 if (vha->flags.online && !vha->flags.reset_active &&
5582 !atomic_read(&vha->loop_down_timer) &&
5583 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5584 do {
e315cd28 5585 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5586
5587 /*
5588 * Issue marker command only when we are going to start
5589 * the I/O.
5590 */
e315cd28
AC		 5591 vha->marker_needed = 1;
5592 } while (!atomic_read(&vha->loop_down_timer) &&
5593 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5594 }
5595}
5596
1da177e4
LT		 5597/**************************************************************************
5598* qla2x00_timer
5599*
5600* Description:
5601* One second timer
5602*
5603* Context: Interrupt
5604***************************************************************************/
2c3dfe3f 5605void
e315cd28 5606qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5607{
1da177e4 5608 unsigned long cpu_flags = 0;
1da177e4
LT		 5609 int start_dpc = 0;
5610 int index;
5611 srb_t *sp;
85880801 5612 uint16_t w;
e315cd28 5613 struct qla_hw_data *ha = vha->hw;
73208dfd 5614 struct req_que *req;
85880801 5615
a5b36321 5616 if (ha->flags.eeh_busy) {
7c3df132
SK		 5617 ql_dbg(ql_dbg_timer, vha, 0x6000,
5618 "EEH = %d, restarting timer.\n",
5619 ha->flags.eeh_busy);
a5b36321
LC		 5620 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5621 return;
5622 }
5623
f3ddac19
CD		 5624 /*
5625 * Hardware read to raise pending EEH errors during mailbox waits. If
5626 * the read returns -1 then disable the board.
5627 */
5628 if (!pci_channel_offline(ha->pdev)) {
85880801 5629 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5630 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5631 }
1da177e4 5632
cefcaba6 5633 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5634 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5635 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5636 start_dpc++;
7ec0effd
AD		 5637 if (IS_QLA82XX(ha))
5638 qla82xx_watchdog(vha);
5639 else if (IS_QLA8044(ha))
5640 qla8044_watchdog(vha);
579d12b5
SK		 5641 }
5642
8ae6d9c7
GM		 5643 if (!vha->vp_idx && IS_QLAFX00(ha))
5644 qlafx00_timer_routine(vha);
5645
1da177e4 5646 /* Loop down handler. */
e315cd28 5647 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5648 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5649 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5650 && vha->flags.online) {
1da177e4 5651
e315cd28
AC		 5652 if (atomic_read(&vha->loop_down_timer) ==
5653 vha->loop_down_abort_time) {
1da177e4 5654
7c3df132
SK		 5655 ql_log(ql_log_info, vha, 0x6008,
5656 "Loop down - aborting the queues before time expires.\n");
1da177e4 5657
e315cd28
AC		 5658 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5659 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5660
f08b7251
AV		 5661 /*
5662 * Schedule an ISP abort to return any FCP2-device
5663 * commands.
5664 */
2c3dfe3f 5665 /* NPIV - scan physical port only */
e315cd28 5666 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5667 spin_lock_irqsave(&ha->hardware_lock,
5668 cpu_flags);
73208dfd 5669 req = ha->req_q_map[0];
2c3dfe3f 5670 for (index = 1;
8d93f550 5671 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5672 index++) {
5673 fc_port_t *sfcp;
5674
e315cd28 5675 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5676 if (!sp)
5677 continue;
9ba56b95 5678 if (sp->type != SRB_SCSI_CMD)
cf53b069 5679 continue;
2c3dfe3f 5680 sfcp = sp->fcport;
f08b7251 5681 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5682 continue;
bdf79621 5683
8f7daead
GM		 5684 if (IS_QLA82XX(ha))
5685 set_bit(FCOE_CTX_RESET_NEEDED,
5686 &vha->dpc_flags);
5687 else
5688 set_bit(ISP_ABORT_NEEDED,
e315cd28 5689 &vha->dpc_flags);
2c3dfe3f
SJ		 5690 break;
5691 }
5692 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5693 cpu_flags);
1da177e4 5694 }
1da177e4
LT		 5695 start_dpc++;
5696 }
5697
5698 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5699 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5700 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5701 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5702 "Loop down - aborting ISP.\n");
5703
8f7daead
GM		 5704 if (IS_QLA82XX(ha))
5705 set_bit(FCOE_CTX_RESET_NEEDED,
5706 &vha->dpc_flags);
5707 else
5708 set_bit(ISP_ABORT_NEEDED,
5709 &vha->dpc_flags);
1da177e4
LT		 5710 }
5711 }
7c3df132
SK		 5712 ql_dbg(ql_dbg_timer, vha, 0x600a,
5713 "Loop down - seconds remaining %d.\n",
5714 atomic_read(&vha->loop_down_timer));
1da177e4 5715 }
cefcaba6
SK		 5716 /* Check if beacon LED needs to be blinked for physical host only */
5717 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5718 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5719 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5720 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5721 start_dpc++;
5722 }
f6df144c 5723 }
5724
550bf57d 5725 /* Process any deferred work. */
e315cd28 5726 if (!list_empty(&vha->work_list))
550bf57d
AV		 5727 start_dpc++;
5728
1da177e4 5729 /* Schedule the DPC routine if needed */
e315cd28
AC		 5730 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5731 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5732 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5733 start_dpc ||
e315cd28
AC		 5734 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5735 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5736 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5737 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5738 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5739 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5740 ql_dbg(ql_dbg_timer, vha, 0x600b,
5741 "isp_abort_needed=%d loop_resync_needed=%d "
5742 "fcport_update_needed=%d start_dpc=%d "
5743 "reset_marker_needed=%d",
5744 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5745 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5746 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5747 start_dpc,
5748 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5749 ql_dbg(ql_dbg_timer, vha, 0x600c,
5750 "beacon_blink_needed=%d isp_unrecoverable=%d "
5751 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5752 "relogin_needed=%d.\n",
7c3df132
SK		 5753 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5754 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5755 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5756 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5757 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5758 qla2xxx_wake_dpc(vha);
7c3df132 5759 }
1da177e4 5760
e315cd28 5761 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5762}
5763
5433383e
AV		 5764/* Firmware interface routines. */
5765
f73cb695 5766#define FW_BLOBS 11
5433383e
AV		 5767#define FW_ISP21XX 0
5768#define FW_ISP22XX 1
5769#define FW_ISP2300 2
5770#define FW_ISP2322 3
48c02fde 5771#define FW_ISP24XX 4
c3a2f0df 5772#define FW_ISP25XX 5
3a03eb79 5773#define FW_ISP81XX 6
a9083016 5774#define FW_ISP82XX 7
6246b8a1
GM		 5775#define FW_ISP2031 8
5776#define FW_ISP8031 9
2c5bbbb2 5777#define FW_ISP27XX 10
5433383e 5778
bb8ee499
AV		 5779#define FW_FILE_ISP21XX "ql2100_fw.bin"
5780#define FW_FILE_ISP22XX "ql2200_fw.bin"
5781#define FW_FILE_ISP2300 "ql2300_fw.bin"
5782#define FW_FILE_ISP2322 "ql2322_fw.bin"
5783#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5784#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5785#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5786#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5787#define FW_FILE_ISP2031 "ql2600_fw.bin"
5788#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5789#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5790
bb8ee499 5791
e1e82b6f 5792static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5793
5794static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5795 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5796 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5797 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5798 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5799 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5800 { .name = FW_FILE_ISP25XX, },
3a03eb79 5801 { .name = FW_FILE_ISP81XX, },
a9083016 5802 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5803 { .name = FW_FILE_ISP2031, },
5804 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5805 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5806};
5807
5808struct fw_blob *
e315cd28 5809qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5810{
e315cd28 5811 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5812 struct fw_blob *blob;
5813
5433383e
AV		 5814 if (IS_QLA2100(ha)) {
5815 blob = &qla_fw_blobs[FW_ISP21XX];
5816 } else if (IS_QLA2200(ha)) {
5817 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5818 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5819 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5820 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5821 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5822 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5823 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5824 } else if (IS_QLA25XX(ha)) {
5825 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5826 } else if (IS_QLA81XX(ha)) {
5827 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5828 } else if (IS_QLA82XX(ha)) {
5829 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5830 } else if (IS_QLA2031(ha)) {
5831 blob = &qla_fw_blobs[FW_ISP2031];
5832 } else if (IS_QLA8031(ha)) {
5833 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5834 } else if (IS_QLA27XX(ha)) {
5835 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5836 } else {
5837 return NULL;
5433383e
AV		 5838 }
5839
e1e82b6f 5840 mutex_lock(&qla_fw_lock);
5433383e
AV		 5841 if (blob->fw)
5842 goto out;
5843
5844 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5845 ql_log(ql_log_warn, vha, 0x0063,
5846 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5847 blob->fw = NULL;
5848 blob = NULL;
5849 goto out;
5850 }
5851
5852out:
e1e82b6f 5853 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5854 return blob;
5855}
5856
5857static void
5858qla2x00_release_firmware(void)
5859{
5860 int idx;
5861
e1e82b6f 5862 mutex_lock(&qla_fw_lock);
5433383e 5863 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5864 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5865 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5866}
5867
14e660e6
SJ		 5868static pci_ers_result_t
5869qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5870{
85880801
AV		 5871 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5872 struct qla_hw_data *ha = vha->hw;
5873
7c3df132
SK		 5874 ql_dbg(ql_dbg_aer, vha, 0x9000,
5875 "PCI error detected, state %x.\n", state);
b9b12f73 5876
14e660e6
SJ		 5877 switch (state) {
5878 case pci_channel_io_normal:
85880801 5879 ha->flags.eeh_busy = 0;
d7459527
MH		 5880 if (ql2xmqsupport) {
5881 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
5882 qla2xxx_wake_dpc(vha);
5883 }
14e660e6
SJ		 5884 return PCI_ERS_RESULT_CAN_RECOVER;
5885 case pci_channel_io_frozen:
85880801 5886 ha->flags.eeh_busy = 1;
a5b36321
LC		 5887 /* For ISP82XX complete any pending mailbox cmd */
5888 if (IS_QLA82XX(ha)) {
7190575f 5889 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5890 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5891 qla82xx_clear_pending_mbx(vha);
a5b36321 5892 }
90a86fc0 5893 qla2x00_free_irqs(vha);
14e660e6 5894 pci_disable_device(pdev);
bddd2d65
LC		 5895 /* Return back all IOs */
5896 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
d7459527
MH		 5897 if (ql2xmqsupport) {
5898 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
5899 qla2xxx_wake_dpc(vha);
5900 }
14e660e6
SJ		 5901 return PCI_ERS_RESULT_NEED_RESET;
5902 case pci_channel_io_perm_failure:
85880801
AV		 5903 ha->flags.pci_channel_io_perm_failure = 1;
5904 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
d7459527
MH		 5905 if (ql2xmqsupport) {
5906 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
5907 qla2xxx_wake_dpc(vha);
5908 }
14e660e6
SJ		 5909 return PCI_ERS_RESULT_DISCONNECT;
5910 }
5911 return PCI_ERS_RESULT_NEED_RESET;
5912}
5913
5914static pci_ers_result_t
5915qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5916{
5917 int risc_paused = 0;
5918 uint32_t stat;
5919 unsigned long flags;
e315cd28
AC		 5920 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5921 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5922 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5923 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5924
bcc5b6d3
SK		 5925 if (IS_QLA82XX(ha))
5926 return PCI_ERS_RESULT_RECOVERED;
5927
14e660e6
SJ		 5928 spin_lock_irqsave(&ha->hardware_lock, flags);
5929 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5930 stat = RD_REG_DWORD(&reg->hccr);
5931 if (stat & HCCR_RISC_PAUSE)
5932 risc_paused = 1;
5933 } else if (IS_QLA23XX(ha)) {
5934 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5935 if (stat & HSR_RISC_PAUSED)
5936 risc_paused = 1;
5937 } else if (IS_FWI2_CAPABLE(ha)) {
5938 stat = RD_REG_DWORD(&reg24->host_status);
5939 if (stat & HSRX_RISC_PAUSED)
5940 risc_paused = 1;
5941 }
5942 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5943
5944 if (risc_paused) {
7c3df132
SK		 5945 ql_log(ql_log_info, base_vha, 0x9003,
5946 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5947 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5948
5949 return PCI_ERS_RESULT_NEED_RESET;
5950 } else
5951 return PCI_ERS_RESULT_RECOVERED;
5952}
5953
fa492630
SK		 5954static uint32_t
5955qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5956{
5957 uint32_t rval = QLA_FUNCTION_FAILED;
5958 uint32_t drv_active = 0;
5959 struct qla_hw_data *ha = base_vha->hw;
5960 int fn;
5961 struct pci_dev *other_pdev = NULL;
5962
7c3df132
SK		 5963 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5964 "Entered %s.\n", __func__);
a5b36321
LC		 5965
5966 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5967
5968 if (base_vha->flags.online) {
5969 /* Abort all outstanding commands,
5970 * so as to be requeued later */
5971 qla2x00_abort_isp_cleanup(base_vha);
5972 }
5973
5974
5975 fn = PCI_FUNC(ha->pdev->devfn);
5976 while (fn > 0) {
5977 fn--;
7c3df132
SK		 5978 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5979 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5980 other_pdev =
5981 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5982 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5983 fn));
5984
5985 if (!other_pdev)
5986 continue;
5987 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5988 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5989 "Found PCI func available and enable at 0x%x.\n",
5990 fn);
a5b36321
LC		 5991 pci_dev_put(other_pdev);
5992 break;
5993 }
5994 pci_dev_put(other_pdev);
5995 }
5996
5997 if (!fn) {
5998 /* Reset owner */
7c3df132
SK		 5999 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6000 "This devfn is reset owner = 0x%x.\n",
6001 ha->pdev->devfn);
a5b36321
LC		 6002 qla82xx_idc_lock(ha);
6003
6004 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6005 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6006
6007 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6008 QLA82XX_IDC_VERSION);
6009
6010 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6011 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6012 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6013
6014 qla82xx_idc_unlock(ha);
6015 /* Reset if device is not already reset
6016 * drv_active would be 0 if a reset has already been done
6017 */
6018 if (drv_active)
6019 rval = qla82xx_start_firmware(base_vha);
6020 else
6021 rval = QLA_SUCCESS;
6022 qla82xx_idc_lock(ha);
6023
6024 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6025 ql_log(ql_log_info, base_vha, 0x900b,
6026 "HW State: FAILED.\n");
a5b36321
LC		 6027 qla82xx_clear_drv_active(ha);
6028 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6029 QLA8XXX_DEV_FAILED);
a5b36321 6030 } else {
7c3df132
SK		 6031 ql_log(ql_log_info, base_vha, 0x900c,
6032 "HW State: READY.\n");
a5b36321 6033 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6034 QLA8XXX_DEV_READY);
a5b36321 6035 qla82xx_idc_unlock(ha);
7190575f 6036 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6037 rval = qla82xx_restart_isp(base_vha);
6038 qla82xx_idc_lock(ha);
6039 /* Clear driver state register */
6040 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6041 qla82xx_set_drv_active(base_vha);
6042 }
6043 qla82xx_idc_unlock(ha);
6044 } else {
7c3df132
SK		 6045 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6046 "This devfn is not reset owner = 0x%x.\n",
6047 ha->pdev->devfn);
a5b36321 6048 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6049 QLA8XXX_DEV_READY)) {
7190575f 6050 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6051 rval = qla82xx_restart_isp(base_vha);
6052 qla82xx_idc_lock(ha);
6053 qla82xx_set_drv_active(base_vha);
6054 qla82xx_idc_unlock(ha);
6055 }
6056 }
6057 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6058
6059 return rval;
6060}
6061
14e660e6
SJ		 6062static pci_ers_result_t
6063qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6064{
6065 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6066 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6067 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6068 struct rsp_que *rsp;
6069 int rc, retries = 10;
09483916 6070
7c3df132
SK		 6071 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6072 "Slot Reset.\n");
85880801 6073
90a86fc0
JC		 6074 /* Workaround: qla2xxx driver which access hardware earlier
6075 * needs error state to be pci_channel_io_online.
6076 * Otherwise mailbox command timesout.
6077 */
6078 pdev->error_state = pci_channel_io_normal;
6079
6080 pci_restore_state(pdev);
6081
8c1496bd
RL		 6082 /* pci_restore_state() clears the saved_state flag of the device
6083 * save restored state which resets saved_state flag
6084 */
6085 pci_save_state(pdev);
6086
09483916
BH		 6087 if (ha->mem_only)
6088 rc = pci_enable_device_mem(pdev);
6089 else
6090 rc = pci_enable_device(pdev);
14e660e6 6091
09483916 6092 if (rc) {
7c3df132 6093 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6094 "Can't re-enable PCI device after reset.\n");
a5b36321 6095 goto exit_slot_reset;
14e660e6 6096 }
14e660e6 6097
90a86fc0
JC		 6098 rsp = ha->rsp_q_map[0];
6099 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6100 goto exit_slot_reset;
90a86fc0 6101
e315cd28 6102 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6103 goto exit_slot_reset;
6104
6105 if (IS_QLA82XX(ha)) {
6106 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6107 ret = PCI_ERS_RESULT_RECOVERED;
6108 goto exit_slot_reset;
6109 } else
6110 goto exit_slot_reset;
6111 }
14e660e6 6112
90a86fc0
JC		 6113 while (ha->flags.mbox_busy && retries--)
6114 msleep(1000);
85880801 6115
e315cd28 6116 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6117 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6118 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6119 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6120
90a86fc0 6121
a5b36321 6122exit_slot_reset:
7c3df132
SK		 6123 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6124 "slot_reset return %x.\n", ret);
85880801 6125
14e660e6
SJ		 6126 return ret;
6127}
6128
6129static void
6130qla2xxx_pci_resume(struct pci_dev *pdev)
6131{
e315cd28
AC		 6132 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6133 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6134 int ret;
6135
7c3df132
SK		 6136 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6137 "pci_resume.\n");
85880801 6138
e315cd28 6139 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6140 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6141 ql_log(ql_log_fatal, base_vha, 0x9002,
6142 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6143 }
85880801 6144
3e46f031
LC		 6145 pci_cleanup_aer_uncorrect_error_status(pdev);
6146
85880801 6147 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6148}
6149
2d5a4c34
HM		 6150static void
6151qla83xx_disable_laser(scsi_qla_host_t *vha)
6152{
6153 uint32_t reg, data, fn;
6154 struct qla_hw_data *ha = vha->hw;
6155 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6156
6157 /* pci func #/port # */
6158 ql_dbg(ql_dbg_init, vha, 0x004b,
6159 "Disabling Laser for hba: %p\n", vha);
6160
6161 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6162 (BIT_15|BIT_14|BIT_13|BIT_12));
6163
6164 fn = (fn >> 12);
6165
6166 if (fn & 1)
6167 reg = PORT_1_2031;
6168 else
6169 reg = PORT_0_2031;
6170
6171 data = LASER_OFF_2031;
6172
6173 qla83xx_wr_reg(vha, reg, data);
6174}
6175
5601236b
MH		 6176static int qla2xxx_map_queues(struct Scsi_Host *shost)
6177{
6178 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6179
6180 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6181}
6182
a55b2d21 6183static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6184 .error_detected = qla2xxx_pci_error_detected,
6185 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6186 .slot_reset = qla2xxx_pci_slot_reset,
6187 .resume = qla2xxx_pci_resume,
6188};
6189
5433383e 6190static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6191 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6192 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6193 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6194 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6195 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6196 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6197 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6198 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6199 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6200 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6201 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6202 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6203 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6204 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6205 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6206 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6207 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6208 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6209 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6210 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6211 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6212 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6213 { 0 },
6214};
6215MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6216
fca29703 6217static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6218 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6219 .driver = {
6220 .owner = THIS_MODULE,
6221 },
fca29703 6222 .id_table = qla2xxx_pci_tbl,
7ee61397 6223 .probe = qla2x00_probe_one,
4c993f76 6224 .remove = qla2x00_remove_one,
e30d1756 6225 .shutdown = qla2x00_shutdown,
14e660e6 6226 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6227};
6228
75ef9de1 6229static const struct file_operations apidev_fops = {
6a03b4cd 6230 .owner = THIS_MODULE,
6038f373 6231 .llseek = noop_llseek,
6a03b4cd
HZ		 6232};
6233
1da177e4
LT		 6234/**
6235 * qla2x00_module_init - Module initialization.
6236 **/
6237static int __init
6238qla2x00_module_init(void)
6239{
fca29703
AV		 6240 int ret = 0;
6241
1da177e4 6242 /* Allocate cache for SRBs. */
354d6b21 6243 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6244 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6245 if (srb_cachep == NULL) {
7c3df132
SK		 6246 ql_log(ql_log_fatal, NULL, 0x0001,
6247 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6248 return -ENOMEM;
6249 }
6250
2d70c103
NB		 6251 /* Initialize target kmem_cache and mem_pools */
6252 ret = qlt_init();
6253 if (ret < 0) {
6254 kmem_cache_destroy(srb_cachep);
6255 return ret;
6256 } else if (ret > 0) {
6257 /*
6258 * If initiator mode is explictly disabled by qlt_init(),
6259 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6260 * performing scsi_scan_target() during LOOP UP event.
6261 */
6262 qla2xxx_transport_functions.disable_target_scan = 1;
6263 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6264 }
6265
1da177e4
LT		 6266 /* Derive version string. */
6267 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6268 if (ql2xextended_error_logging)
0181944f
AV		 6269 strcat(qla2x00_version_str, "-debug");
6270
1c97a12a
AV		 6271 qla2xxx_transport_template =
6272 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6273 if (!qla2xxx_transport_template) {
6274 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6275 ql_log(ql_log_fatal, NULL, 0x0002,
6276 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6277 qlt_exit();
1da177e4 6278 return -ENODEV;
2c3dfe3f 6279 }
6a03b4cd
HZ		 6280
6281 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6282 if (apidev_major < 0) {
7c3df132
SK		 6283 ql_log(ql_log_fatal, NULL, 0x0003,
6284 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6285 }
6286
2c3dfe3f
SJ		 6287 qla2xxx_transport_vport_template =
6288 fc_attach_transport(&qla2xxx_transport_vport_functions);
6289 if (!qla2xxx_transport_vport_template) {
6290 kmem_cache_destroy(srb_cachep);
2d70c103 6291 qlt_exit();
2c3dfe3f 6292 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6293 ql_log(ql_log_fatal, NULL, 0x0004,
6294 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6295 return -ENODEV;
2c3dfe3f 6296 }
7c3df132
SK		 6297 ql_log(ql_log_info, NULL, 0x0005,
6298 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6299 qla2x00_version_str);
7ee61397 6300 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6301 if (ret) {
6302 kmem_cache_destroy(srb_cachep);
2d70c103 6303 qlt_exit();
fca29703 6304 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6305 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6306 ql_log(ql_log_fatal, NULL, 0x0006,
6307 "pci_register_driver failed...ret=%d Failing load!.\n",
6308 ret);
fca29703
AV		 6309 }
6310 return ret;
1da177e4
LT		 6311}
6312
6313/**
6314 * qla2x00_module_exit - Module cleanup.
6315 **/
6316static void __exit
6317qla2x00_module_exit(void)
6318{
6a03b4cd 6319 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6320 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6321 qla2x00_release_firmware();
354d6b21 6322 kmem_cache_destroy(srb_cachep);
2d70c103 6323 qlt_exit();
a9083016
GM		 6324 if (ctx_cachep)
6325 kmem_cache_destroy(ctx_cachep);
1da177e4 6326 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6327 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6328}
6329
6330module_init(qla2x00_module_init);
6331module_exit(qla2x00_module_exit);
6332
6333MODULE_AUTHOR("QLogic Corporation");
6334MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6335MODULE_LICENSE("GPL");
6336MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6337MODULE_FIRMWARE(FW_FILE_ISP21XX);
6338MODULE_FIRMWARE(FW_FILE_ISP22XX);
6339MODULE_FIRMWARE(FW_FILE_ISP2300);
6340MODULE_FIRMWARE(FW_FILE_ISP2322);
6341MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6342MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)