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scsi: mptsas: remove duplicated assignment to pointer head
[linux-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
d213a4b7 116#define MAX_Q_DEPTH 64
50280c01 117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 120 "Maximum queue depth to set for each LUN. "
d213a4b7 121 "Default is 64.");
df7baa50 122
e84067d7
DG		 123#if (IS_ENABLED(CONFIG_NVME_FC))
124int ql2xenabledif;
125#else
9e522cd8 126int ql2xenabledif = 2;
e84067d7 127#endif
9e522cd8 128module_param(ql2xenabledif, int, S_IRUGO);
bad75002 129MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 130 " Enable T10-CRC-DIF:\n"
131 " Default is 2.\n"
132 " 0 -- No DIF Support\n"
133 " 1 -- Enable DIF for all types\n"
134 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 135
e84067d7
DG		 136#if (IS_ENABLED(CONFIG_NVME_FC))
137int ql2xnvmeenable = 1;
138#else
139int ql2xnvmeenable;
140#endif
141module_param(ql2xnvmeenable, int, 0644);
142MODULE_PARM_DESC(ql2xnvmeenable,
143 "Enables NVME support. "
144 "0 - no NVMe. Default is Y");
145
8cb2049c 146int ql2xenablehba_err_chk = 2;
bad75002
AE		 147module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
148MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 149 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 150 " Default is 2.\n"
8cb2049c
AE		 151 " 0 -- Error isolation disabled\n"
152 " 1 -- Error isolation enabled only for DIX Type 0\n"
153 " 2 -- Error isolation enabled for all Types\n");
bad75002 154
e5896bd5 155int ql2xiidmaenable=1;
f2019cb1 156module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 157MODULE_PARM_DESC(ql2xiidmaenable,
158 "Enables iIDMA settings "
159 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
160
d7459527
MH		 161int ql2xmqsupport = 1;
162module_param(ql2xmqsupport, int, S_IRUGO);
163MODULE_PARM_DESC(ql2xmqsupport,
164 "Enable on demand multiple queue pairs support "
165 "Default is 1 for supported. "
166 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 167
168int ql2xfwloadbin;
86e45bf6 169module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 170module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 171MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 172 "Option to specify location from which to load ISP firmware:.\n"
173 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 174 " interface.\n"
175 " 1 -- load firmware from flash.\n"
176 " 0 -- use default semantics.\n");
177
ae97c91e 178int ql2xetsenable;
f2019cb1 179module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 180MODULE_PARM_DESC(ql2xetsenable,
181 "Enables firmware ETS burst."
182 "Default is 0 - skip ETS enablement.");
183
6907869d 184int ql2xdbwr = 1;
86e45bf6 185module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 186MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 187 "Option to specify scheme for request queue posting.\n"
188 " 0 -- Regular doorbell.\n"
189 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 190
f4c496c1 191int ql2xtargetreset = 1;
f2019cb1 192module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 193MODULE_PARM_DESC(ql2xtargetreset,
194 "Enable target reset."
195 "Default is 1 - use hw defaults.");
196
4da26e16 197int ql2xgffidenable;
f2019cb1 198module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 199MODULE_PARM_DESC(ql2xgffidenable,
200 "Enables GFF_ID checks of port type. "
201 "Default is 0 - Do not use GFF_ID information.");
a9083016 202
043dc1d7 203int ql2xasynctmfenable = 1;
f2019cb1 204module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 205MODULE_PARM_DESC(ql2xasynctmfenable,
206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
207 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 208
209int ql2xdontresethba;
86e45bf6 210module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 211MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 212 "Option to specify reset behaviour.\n"
213 " 0 (Default) -- Reset on failure.\n"
214 " 1 -- Do not reset on failure.\n");
ed0de87c 215
1abf635d
HR		 216uint64_t ql2xmaxlun = MAX_LUNS;
217module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 218MODULE_PARM_DESC(ql2xmaxlun,
219 "Defines the maximum LU number to register with the SCSI "
220 "midlayer. Default is 65535.");
221
08de2844
GM		 222int ql2xmdcapmask = 0x1F;
223module_param(ql2xmdcapmask, int, S_IRUGO);
224MODULE_PARM_DESC(ql2xmdcapmask,
225 "Set the Minidump driver capture mask level. "
6e96fa7b 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 227
3aadff35 228int ql2xmdenable = 1;
08de2844
GM		 229module_param(ql2xmdenable, int, S_IRUGO);
230MODULE_PARM_DESC(ql2xmdenable,
231 "Enable/disable MiniDump. "
3aadff35
GM		 232 "0 - MiniDump disabled. "
233 "1 (Default) - MiniDump enabled.");
08de2844 234
b0d6cabd
HM		 235int ql2xexlogins = 0;
236module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
237MODULE_PARM_DESC(ql2xexlogins,
238 "Number of extended Logins. "
239 "0 (Default)- Disabled.");
240
99e1b683
QT		 241int ql2xexchoffld = 1024;
242module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 243MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 244 "Number of target exchanges.");
245
246int ql2xiniexchg = 1024;
247module_param(ql2xiniexchg, uint, 0644);
248MODULE_PARM_DESC(ql2xiniexchg,
249 "Number of initiator exchanges.");
2f56a7f1 250
f198cafa
HM		 251int ql2xfwholdabts = 0;
252module_param(ql2xfwholdabts, int, S_IRUGO);
253MODULE_PARM_DESC(ql2xfwholdabts,
254 "Allow FW to hold status IOCB until ABTS rsp received. "
255 "0 (Default) Do not set fw option. "
256 "1 - Set fw option to hold ABTS.");
257
41dc529a
QT		 258int ql2xmvasynctoatio = 1;
259module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
260MODULE_PARM_DESC(ql2xmvasynctoatio,
261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
262 "0 (Default). Do not move IOCBs"
263 "1 - Move IOCBs.");
264
e4e3a2ce
QT		 265int ql2xautodetectsfp = 1;
266module_param(ql2xautodetectsfp, int, 0444);
267MODULE_PARM_DESC(ql2xautodetectsfp,
268 "Detect SFP range and set appropriate distance.\n"
269 "1 (Default): Enable\n");
270
e7240af5
HM		 271int ql2xenablemsix = 1;
272module_param(ql2xenablemsix, int, 0444);
273MODULE_PARM_DESC(ql2xenablemsix,
274 "Set to enable MSI or MSI-X interrupt mechanism.\n"
275 " Default is 1, enable MSI-X interrupt mechanism.\n"
276 " 0 -- enable traditional pin-based mechanism.\n"
277 " 1 -- enable MSI-X interrupt mechanism.\n"
278 " 2 -- enable MSI interrupt mechanism.\n");
279
9ecf0b0d
QT		 280int qla2xuseresexchforels;
281module_param(qla2xuseresexchforels, int, 0444);
282MODULE_PARM_DESC(qla2xuseresexchforels,
283 "Reserve 1/2 of emergency exchanges for ELS.\n"
284 " 0 (default): disabled");
285
1da177e4 286/*
fa2a1ce5 287 * SCSI host template entry points
1da177e4
LT		 288 */
289static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 290static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 291static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
292static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 293static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 294static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 295static int qla2xxx_eh_abort(struct scsi_cmnd *);
296static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 297static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 298static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
299static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 300
1a2fbf18 301static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 302static void qla2x00_free_device(scsi_qla_host_t *);
5601236b 303static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 304static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 305
a5326f86 306struct scsi_host_template qla2xxx_driver_template = {
1da177e4 307 .module = THIS_MODULE,
cb63067a 308 .name = QLA2XXX_DRIVER_NAME,
a5326f86 309 .queuecommand = qla2xxx_queuecommand,
fca29703 310
b6a05c82 311 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 312 .eh_abort_handler = qla2xxx_eh_abort,
313 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 314 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 315 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
316 .eh_host_reset_handler = qla2xxx_eh_host_reset,
317
318 .slave_configure = qla2xxx_slave_configure,
319
320 .slave_alloc = qla2xxx_slave_alloc,
321 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 322 .scan_finished = qla2xxx_scan_finished,
323 .scan_start = qla2xxx_scan_start,
db5ed4df 324 .change_queue_depth = scsi_change_queue_depth,
5601236b 325 .map_queues = qla2xxx_map_queues,
fca29703
AV		 326 .this_id = -1,
327 .cmd_per_lun = 3,
328 .use_clustering = ENABLE_CLUSTERING,
329 .sg_tablesize = SG_ALL,
330
331 .max_sectors = 0xFFFF,
afb046e2 332 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 333
334 .supported_mode = MODE_INITIATOR,
c40ecc12 335 .track_queue_depth = 1,
fca29703
AV		 336};
337
1da177e4 338static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 339struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 340
1da177e4
LT		 341/* TODO Convert to inlines
342 *
343 * Timer routines
344 */
1da177e4 345
2c3dfe3f 346__inline__ void
8e5f4ba0 347qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 348{
8e5f4ba0 349 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 350 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 351 add_timer(&vha->timer);
352 vha->timer_active = 1;
1da177e4
LT		 353}
354
355static inline void
e315cd28 356qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 357{
a9083016 358 /* Currently used for 82XX only. */
7c3df132
SK		 359 if (vha->device_flags & DFLG_DEV_FAILED) {
360 ql_dbg(ql_dbg_timer, vha, 0x600d,
361 "Device in a failed state, returning.\n");
a9083016 362 return;
7c3df132 363 }
a9083016 364
e315cd28 365 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 366}
367
a824ebb3 368static __inline__ void
e315cd28 369qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 370{
e315cd28
AC		 371 del_timer_sync(&vha->timer);
372 vha->timer_active = 0;
1da177e4
LT		 373}
374
1da177e4
LT		 375static int qla2x00_do_dpc(void *data);
376
377static void qla2x00_rst_aen(scsi_qla_host_t *);
378
73208dfd
AC		 379static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
380 struct req_que **, struct rsp_que **);
e30d1756 381static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 382static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 383int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
384 struct qla_qpair *qpair);
1da177e4 385
1da177e4 386/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 387static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
388 struct rsp_que *rsp)
389{
390 struct qla_hw_data *ha = vha->hw;
391 rsp->qpair = ha->base_qpair;
392 rsp->req = req;
393 ha->base_qpair->req = req;
394 ha->base_qpair->rsp = rsp;
395 ha->base_qpair->vha = vha;
396 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
397 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
398 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
399 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
cf19c45d 400 INIT_LIST_HEAD(&ha->base_qpair->nvme_done_list);
8abfa9e2
QT		 401 ha->base_qpair->enable_class_2 = ql2xenableclass2;
402 /* init qpair to this cpu. Will adjust at run time. */
86531887 403 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
8abfa9e2
QT		 404 ha->base_qpair->pdev = ha->pdev;
405
406 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
407 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
408}
409
9a347ff4
CD		 410static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
411 struct rsp_que *rsp)
73208dfd 412{
7c3df132 413 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 414 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 415 GFP_KERNEL);
416 if (!ha->req_q_map) {
7c3df132
SK		 417 ql_log(ql_log_fatal, vha, 0x003b,
418 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 419 goto fail_req_map;
420 }
421
2afa19a9 422 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 423 GFP_KERNEL);
424 if (!ha->rsp_q_map) {
7c3df132
SK		 425 ql_log(ql_log_fatal, vha, 0x003c,
426 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 427 goto fail_rsp_map;
428 }
d7459527 429
e326d22a
QT		 430 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
431 if (ha->base_qpair == NULL) {
432 ql_log(ql_log_warn, vha, 0x00e0,
433 "Failed to allocate base queue pair memory.\n");
434 goto fail_base_qpair;
435 }
436
8abfa9e2 437 qla_init_base_qpair(vha, req, rsp);
e326d22a 438
c38d1baf 439 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
d7459527
MH		 440 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
441 GFP_KERNEL);
442 if (!ha->queue_pair_map) {
443 ql_log(ql_log_fatal, vha, 0x0180,
444 "Unable to allocate memory for queue pair ptrs.\n");
445 goto fail_qpair_map;
446 }
d7459527
MH		 447 }
448
9a347ff4
CD		 449 /*
450 * Make sure we record at least the request and response queue zero in
451 * case we need to free them if part of the probe fails.
452 */
453 ha->rsp_q_map[0] = rsp;
454 ha->req_q_map[0] = req;
73208dfd
AC		 455 set_bit(0, ha->rsp_qid_map);
456 set_bit(0, ha->req_qid_map);
457 return 1;
458
d7459527 459fail_qpair_map:
82de802a
QT		 460 kfree(ha->base_qpair);
461 ha->base_qpair = NULL;
462fail_base_qpair:
d7459527
MH		 463 kfree(ha->rsp_q_map);
464 ha->rsp_q_map = NULL;
73208dfd
AC		 465fail_rsp_map:
466 kfree(ha->req_q_map);
467 ha->req_q_map = NULL;
468fail_req_map:
469 return -ENOMEM;
470}
471
2afa19a9 472static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 473{
8ae6d9c7
GM		 474 if (IS_QLAFX00(ha)) {
475 if (req && req->ring_fx00)
476 dma_free_coherent(&ha->pdev->dev,
477 (req->length_fx00 + 1) * sizeof(request_t),
478 req->ring_fx00, req->dma_fx00);
479 } else if (req && req->ring)
73208dfd
AC		 480 dma_free_coherent(&ha->pdev->dev,
481 (req->length + 1) * sizeof(request_t),
482 req->ring, req->dma);
483
8d93f550
CD		 484 if (req)
485 kfree(req->outstanding_cmds);
486
73208dfd 487 kfree(req);
73208dfd
AC		 488}
489
2afa19a9
AC		 490static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
491{
8ae6d9c7
GM		 492 if (IS_QLAFX00(ha)) {
493 if (rsp && rsp->ring)
494 dma_free_coherent(&ha->pdev->dev,
495 (rsp->length_fx00 + 1) * sizeof(request_t),
496 rsp->ring_fx00, rsp->dma_fx00);
497 } else if (rsp && rsp->ring) {
2afa19a9
AC		 498 dma_free_coherent(&ha->pdev->dev,
499 (rsp->length + 1) * sizeof(response_t),
500 rsp->ring, rsp->dma);
8ae6d9c7 501 }
2afa19a9 502 kfree(rsp);
2afa19a9
AC		 503}
504
73208dfd
AC		 505static void qla2x00_free_queues(struct qla_hw_data *ha)
506{
507 struct req_que *req;
508 struct rsp_que *rsp;
509 int cnt;
093df737 510 unsigned long flags;
73208dfd 511
82de802a
QT		 512 if (ha->queue_pair_map) {
513 kfree(ha->queue_pair_map);
514 ha->queue_pair_map = NULL;
515 }
516 if (ha->base_qpair) {
517 kfree(ha->base_qpair);
518 ha->base_qpair = NULL;
519 }
520
093df737 521 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 522 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 523 if (!test_bit(cnt, ha->req_qid_map))
524 continue;
525
73208dfd 526 req = ha->req_q_map[cnt];
093df737
QT		 527 clear_bit(cnt, ha->req_qid_map);
528 ha->req_q_map[cnt] = NULL;
529
530 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 531 qla2x00_free_req_que(ha, req);
093df737 532 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 533 }
093df737
QT		 534 spin_unlock_irqrestore(&ha->hardware_lock, flags);
535
73208dfd
AC		 536 kfree(ha->req_q_map);
537 ha->req_q_map = NULL;
2afa19a9 538
093df737
QT		 539
540 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 541 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 542 if (!test_bit(cnt, ha->rsp_qid_map))
543 continue;
544
2afa19a9 545 rsp = ha->rsp_q_map[cnt];
c3c42394 546 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 547 ha->rsp_q_map[cnt] = NULL;
548 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 549 qla2x00_free_rsp_que(ha, rsp);
093df737 550 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 551 }
093df737
QT		 552 spin_unlock_irqrestore(&ha->hardware_lock, flags);
553
2afa19a9
AC		 554 kfree(ha->rsp_q_map);
555 ha->rsp_q_map = NULL;
73208dfd
AC		 556}
557
1da177e4 558static char *
e315cd28 559qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 560{
e315cd28 561 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 562 static char *pci_bus_modes[] = {
563 "33", "66", "100", "133",
564 };
565 uint16_t pci_bus;
566
567 strcpy(str, "PCI");
568 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
569 if (pci_bus) {
570 strcat(str, "-X (");
571 strcat(str, pci_bus_modes[pci_bus]);
572 } else {
573 pci_bus = (ha->pci_attr & BIT_8) >> 8;
574 strcat(str, " (");
575 strcat(str, pci_bus_modes[pci_bus]);
576 }
577 strcat(str, " MHz)");
578
579 return (str);
580}
581
fca29703 582static char *
e315cd28 583qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 584{
585 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 586 struct qla_hw_data *ha = vha->hw;
fca29703 587 uint32_t pci_bus;
fca29703 588
62a276f8 589 if (pci_is_pcie(ha->pdev)) {
fca29703 590 char lwstr[6];
62a276f8 591 uint32_t lstat, lspeed, lwidth;
fca29703 592
62a276f8
BH		 593 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
594 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
595 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 596
597 strcpy(str, "PCIe (");
49300af7
SK		 598 switch (lspeed) {
599 case 1:
c87a0d8c 600 strcat(str, "2.5GT/s ");
49300af7
SK		 601 break;
602 case 2:
c87a0d8c 603 strcat(str, "5.0GT/s ");
49300af7
SK		 604 break;
605 case 3:
606 strcat(str, "8.0GT/s ");
607 break;
608 default:
fca29703 609 strcat(str, "<unknown> ");
49300af7
SK		 610 break;
611 }
fca29703
AV		 612 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
613 strcat(str, lwstr);
614
615 return str;
616 }
617
618 strcpy(str, "PCI");
619 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
620 if (pci_bus == 0 || pci_bus == 8) {
621 strcat(str, " (");
622 strcat(str, pci_bus_modes[pci_bus >> 3]);
623 } else {
624 strcat(str, "-X ");
625 if (pci_bus & BIT_2)
626 strcat(str, "Mode 2");
627 else
628 strcat(str, "Mode 1");
629 strcat(str, " (");
630 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
631 }
632 strcat(str, " MHz)");
633
634 return str;
635}
636
e5f82ab8 637static char *
df57caba 638qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 639{
640 char un_str[10];
e315cd28 641 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 642
df57caba
HM		 643 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
644 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 645
646 if (ha->fw_attributes & BIT_9) {
647 strcat(str, "FLX");
648 return (str);
649 }
650
651 switch (ha->fw_attributes & 0xFF) {
652 case 0x7:
653 strcat(str, "EF");
654 break;
655 case 0x17:
656 strcat(str, "TP");
657 break;
658 case 0x37:
659 strcat(str, "IP");
660 break;
661 case 0x77:
662 strcat(str, "VI");
663 break;
664 default:
665 sprintf(un_str, "(%x)", ha->fw_attributes);
666 strcat(str, un_str);
667 break;
668 }
669 if (ha->fw_attributes & 0x100)
670 strcat(str, "X");
671
672 return (str);
673}
674
e5f82ab8 675static char *
df57caba 676qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 677{
e315cd28 678 struct qla_hw_data *ha = vha->hw;
f0883ac6 679
df57caba 680 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 681 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 682 return str;
fca29703
AV		 683}
684
9ba56b95 685void
25ff6af1 686qla2x00_sp_free_dma(void *ptr)
fca29703 687{
25ff6af1
JC		 688 srb_t *sp = ptr;
689 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 690 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 691 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 692
9ba56b95
GM		 693 if (sp->flags & SRB_DMA_VALID) {
694 scsi_dma_unmap(cmd);
695 sp->flags &= ~SRB_DMA_VALID;
7c3df132 696 }
fca29703 697
9ba56b95
GM		 698 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
699 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
700 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
701 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
702 }
703
d5ff0eed
JC		 704 if (!ctx)
705 goto end;
706
9ba56b95
GM		 707 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
708 /* List assured to be having elements */
d5ff0eed 709 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 710 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
711 }
712
713 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 714 struct crc_context *ctx0 = ctx;
715
716 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 717 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
718 }
719
720 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 721 struct ct6_dsd *ctx1 = ctx;
fca29703 722
9ba56b95 723 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 724 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 725 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
726 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
727 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
728 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95
GM		 729 }
730
d5ff0eed 731end:
6fcd98fd 732 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) {
7401bc18
DG		 733 CMD_SP(cmd) = NULL;
734 qla2x00_rel_sp(sp);
735 }
9ba56b95
GM		 736}
737
d7459527 738void
25ff6af1 739qla2x00_sp_compl(void *ptr, int res)
9ba56b95 740{
25ff6af1 741 srb_t *sp = ptr;
9ba56b95
GM		 742 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
743
744 cmd->result = res;
745
746 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 747 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 748 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
749 sp, GET_CMD_SP(sp));
750 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 751 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 752 return;
753 }
754 if (!atomic_dec_and_test(&sp->ref_count))
755 return;
756
f3caa990 757 sp->free(sp);
9ba56b95 758 cmd->scsi_done(cmd);
fca29703
AV		 759}
760
d7459527 761void
25ff6af1 762qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 763{
764 srb_t *sp = (srb_t *)ptr;
765 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
766 struct qla_hw_data *ha = sp->fcport->vha->hw;
767 void *ctx = GET_CMD_CTX_SP(sp);
768
769 if (sp->flags & SRB_DMA_VALID) {
770 scsi_dma_unmap(cmd);
771 sp->flags &= ~SRB_DMA_VALID;
772 }
773
774 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
775 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
776 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
777 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
778 }
779
d5ff0eed
JC		 780 if (!ctx)
781 goto end;
782
d7459527
MH		 783 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
784 /* List assured to be having elements */
d5ff0eed 785 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 786 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
787 }
788
789 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 790 struct crc_context *ctx0 = ctx;
791
792 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 793 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
794 }
795
796 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 797 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 798 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
799 ctx1->fcp_cmnd_dma);
800 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
801 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
802 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
803 mempool_free(ctx1, ha->ctx_mempool);
804 }
d5ff0eed 805end:
d7459527
MH		 806 CMD_SP(cmd) = NULL;
807 qla2xxx_rel_qpair_sp(sp->qpair, sp);
808}
809
810void
25ff6af1 811qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 812{
25ff6af1 813 srb_t *sp = ptr;
d7459527
MH		 814 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
815
816 cmd->result = res;
817
818 if (atomic_read(&sp->ref_count) == 0) {
819 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
820 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
821 sp, GET_CMD_SP(sp));
822 if (ql2xextended_error_logging & ql_dbg_io)
823 WARN_ON(atomic_read(&sp->ref_count) == 0);
824 return;
825 }
826 if (!atomic_dec_and_test(&sp->ref_count))
827 return;
828
f3caa990 829 sp->free(sp);
d7459527
MH		 830 cmd->scsi_done(cmd);
831}
832
8ae6d9c7
GM		 833/* If we are SP1 here, we need to still take and release the host_lock as SP1
834 * does not have the changes necessary to avoid taking host->host_lock.
835 */
1da177e4 836static int
f5e3e40b 837qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 838{
134ae078 839 scsi_qla_host_t *vha = shost_priv(host);
fca29703 840 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 841 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 842 struct qla_hw_data *ha = vha->hw;
843 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 844 srb_t *sp;
845 int rval;
5601236b
MH		 846 struct qla_qpair *qpair = NULL;
847 uint32_t tag;
848 uint16_t hwq;
fca29703 849
04dfaa53
MFO		 850 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
851 cmd->result = DID_NO_CONNECT << 16;
852 goto qc24_fail_command;
853 }
854
5601236b
MH		 855 if (ha->mqenable) {
856 if (shost_use_blk_mq(vha->host)) {
857 tag = blk_mq_unique_tag(cmd->request);
858 hwq = blk_mq_unique_tag_to_hwq(tag);
859 qpair = ha->queue_pair_map[hwq];
860 } else if (vha->vp_idx && vha->qpair) {
861 qpair = vha->qpair;
862 }
863
864 if (qpair)
865 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 866 }
867
85880801 868 if (ha->flags.eeh_busy) {
7c3df132 869 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 870 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 871 "PCI Channel IO permanent failure, exiting "
872 "cmd=%p.\n", cmd);
b9b12f73 873 cmd->result = DID_NO_CONNECT << 16;
7c3df132 874 } else {
5f28d2d7 875 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 876 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 877 cmd->result = DID_REQUEUE << 16;
7c3df132 878 }
14e660e6
SJ		 879 goto qc24_fail_command;
880 }
881
19a7b4ae
JSEC		 882 rval = fc_remote_port_chkready(rport);
883 if (rval) {
884 cmd->result = rval;
5f28d2d7 885 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 886 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
887 cmd, rval);
fca29703
AV		 888 goto qc24_fail_command;
889 }
890
bad75002
AE		 891 if (!vha->flags.difdix_supported &&
892 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 893 ql_dbg(ql_dbg_io, vha, 0x3004,
894 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
895 cmd);
bad75002
AE		 896 cmd->result = DID_NO_CONNECT << 16;
897 goto qc24_fail_command;
898 }
aa651be8
CD		 899
900 if (!fcport) {
901 cmd->result = DID_NO_CONNECT << 16;
902 goto qc24_fail_command;
903 }
904
fca29703
AV		 905 if (atomic_read(&fcport->state) != FCS_ONLINE) {
906 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 907 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 908 ql_dbg(ql_dbg_io, vha, 0x3005,
909 "Returning DNC, fcport_state=%d loop_state=%d.\n",
910 atomic_read(&fcport->state),
911 atomic_read(&base_vha->loop_state));
fca29703
AV		 912 cmd->result = DID_NO_CONNECT << 16;
913 goto qc24_fail_command;
914 }
7b594131 915 goto qc24_target_busy;
fca29703
AV		 916 }
917
e05fe292
CD		 918 /*
919 * Return target busy if we've received a non-zero retry_delay_timer
920 * in a FCP_RSP.
921 */
975f7d46
BP		 922 if (fcport->retry_delay_timestamp == 0) {
923 /* retry delay not set */
924 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 925 fcport->retry_delay_timestamp = 0;
926 else
927 goto qc24_target_busy;
928
b00ee7d7 929 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 930 if (!sp)
f5e3e40b 931 goto qc24_host_busy;
fca29703 932
9ba56b95
GM		 933 sp->u.scmd.cmd = cmd;
934 sp->type = SRB_SCSI_CMD;
935 atomic_set(&sp->ref_count, 1);
936 CMD_SP(cmd) = (void *)sp;
937 sp->free = qla2x00_sp_free_dma;
938 sp->done = qla2x00_sp_compl;
939
e315cd28 940 rval = ha->isp_ops->start_scsi(sp);
7c3df132 941 if (rval != QLA_SUCCESS) {
53016ed3 942 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 943 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 944 goto qc24_host_busy_free_sp;
7c3df132 945 }
fca29703 946
fca29703
AV		 947 return 0;
948
949qc24_host_busy_free_sp:
f3caa990 950 sp->free(sp);
fca29703 951
f5e3e40b 952qc24_host_busy:
fca29703
AV		 953 return SCSI_MLQUEUE_HOST_BUSY;
954
7b594131
MC		 955qc24_target_busy:
956 return SCSI_MLQUEUE_TARGET_BUSY;
957
fca29703 958qc24_fail_command:
f5e3e40b 959 cmd->scsi_done(cmd);
fca29703
AV		 960
961 return 0;
962}
963
d7459527
MH		 964/* For MQ supported I/O */
965int
966qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
967 struct qla_qpair *qpair)
968{
969 scsi_qla_host_t *vha = shost_priv(host);
970 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
971 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
972 struct qla_hw_data *ha = vha->hw;
973 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
974 srb_t *sp;
975 int rval;
976
977 rval = fc_remote_port_chkready(rport);
978 if (rval) {
979 cmd->result = rval;
980 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
981 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
982 cmd, rval);
983 goto qc24_fail_command;
984 }
985
986 if (!fcport) {
987 cmd->result = DID_NO_CONNECT << 16;
988 goto qc24_fail_command;
989 }
990
991 if (atomic_read(&fcport->state) != FCS_ONLINE) {
992 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
993 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
994 ql_dbg(ql_dbg_io, vha, 0x3077,
995 "Returning DNC, fcport_state=%d loop_state=%d.\n",
996 atomic_read(&fcport->state),
997 atomic_read(&base_vha->loop_state));
998 cmd->result = DID_NO_CONNECT << 16;
999 goto qc24_fail_command;
1000 }
1001 goto qc24_target_busy;
1002 }
1003
1004 /*
1005 * Return target busy if we've received a non-zero retry_delay_timer
1006 * in a FCP_RSP.
1007 */
1008 if (fcport->retry_delay_timestamp == 0) {
1009 /* retry delay not set */
1010 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1011 fcport->retry_delay_timestamp = 0;
1012 else
1013 goto qc24_target_busy;
1014
1015 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
1016 if (!sp)
1017 goto qc24_host_busy;
1018
1019 sp->u.scmd.cmd = cmd;
1020 sp->type = SRB_SCSI_CMD;
1021 atomic_set(&sp->ref_count, 1);
1022 CMD_SP(cmd) = (void *)sp;
1023 sp->free = qla2xxx_qpair_sp_free_dma;
1024 sp->done = qla2xxx_qpair_sp_compl;
1025 sp->qpair = qpair;
1026
1027 rval = ha->isp_ops->start_scsi_mq(sp);
1028 if (rval != QLA_SUCCESS) {
1029 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1030 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1031 if (rval == QLA_INTERFACE_ERROR)
1032 goto qc24_fail_command;
1033 goto qc24_host_busy_free_sp;
1034 }
1035
1036 return 0;
1037
1038qc24_host_busy_free_sp:
f3caa990 1039 sp->free(sp);
d7459527
MH		 1040
1041qc24_host_busy:
1042 return SCSI_MLQUEUE_HOST_BUSY;
1043
1044qc24_target_busy:
1045 return SCSI_MLQUEUE_TARGET_BUSY;
1046
1047qc24_fail_command:
1048 cmd->scsi_done(cmd);
1049
1050 return 0;
1051}
1052
1da177e4
LT		 1053/*
1054 * qla2x00_eh_wait_on_command
1055 * Waits for the command to be returned by the Firmware for some
1056 * max time.
1057 *
1058 * Input:
1da177e4 1059 * cmd = Scsi Command to wait on.
1da177e4
LT		 1060 *
1061 * Return:
1062 * Not Found : 0
1063 * Found : 1
1064 */
1065static int
e315cd28 1066qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1067{
fe74c71f 1068#define ABORT_POLLING_PERIOD 1000
478c3b03 1069#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1070 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1071 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1072 struct qla_hw_data *ha = vha->hw;
f4f051eb 1073 int ret = QLA_SUCCESS;
1da177e4 1074
85880801 1075 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1076 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1077 "Return:eh_wait.\n");
85880801
AV		 1078 return ret;
1079 }
1080
d970432c 1081 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1082 msleep(ABORT_POLLING_PERIOD);
f4f051eb 1083 }
1084 if (CMD_SP(cmd))
1085 ret = QLA_FUNCTION_FAILED;
1da177e4 1086
f4f051eb 1087 return ret;
1da177e4
LT		 1088}
1089
1090/*
1091 * qla2x00_wait_for_hba_online
fa2a1ce5 1092 * Wait till the HBA is online after going through
1da177e4
LT		 1093 * <= MAX_RETRIES_OF_ISP_ABORT or
1094 * finally HBA is disabled ie marked offline
1095 *
1096 * Input:
1097 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1098 *
1099 * Note:
1da177e4
LT		 1100 * Does context switching-Release SPIN_LOCK
1101 * (if any) before calling this routine.
1102 *
1103 * Return:
1104 * Success (Adapter is online) : 0
1105 * Failed (Adapter is offline/disabled) : 1
1106 */
854165f4 1107int
e315cd28 1108qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1109{
fca29703
AV		 1110 int return_status;
1111 unsigned long wait_online;
e315cd28
AC		 1112 struct qla_hw_data *ha = vha->hw;
1113 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1114
fa2a1ce5 1115 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1116 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1117 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1118 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1119 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1120
1121 msleep(1000);
1122 }
e315cd28 1123 if (base_vha->flags.online)
fa2a1ce5 1124 return_status = QLA_SUCCESS;
1da177e4
LT		 1125 else
1126 return_status = QLA_FUNCTION_FAILED;
1127
1da177e4
LT		 1128 return (return_status);
1129}
1130
726b8548
QT		 1131static inline int test_fcport_count(scsi_qla_host_t *vha)
1132{
1133 struct qla_hw_data *ha = vha->hw;
1134 unsigned long flags;
1135 int res;
1136
1137 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1138 ql_dbg(ql_dbg_init, vha, 0x00ec,
1139 "tgt %p, fcport_count=%d\n",
1140 vha, vha->fcport_count);
726b8548
QT		 1141 res = (vha->fcport_count == 0);
1142 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1143
1144 return res;
1145}
1146
1147/*
1148 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1149 * it has dependency on UNLOADING flag to stop device discovery
1150 */
1151static void
1152qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1153{
1154 qla2x00_mark_all_devices_lost(vha, 0);
1155
b85e0957 1156 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
726b8548
QT		 1157}
1158
86fbee86 1159/*
638a1a01
SC		 1160 * qla2x00_wait_for_hba_ready
1161 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1162 *
1163 * Input:
1164 * ha - pointer to host adapter structure
1165 *
1166 * Note:
1167 * Does context switching-Release SPIN_LOCK
1168 * (if any) before calling this routine.
1169 *
86fbee86 1170 */
638a1a01
SC		 1171static void
1172qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1173{
86fbee86 1174 struct qla_hw_data *ha = vha->hw;
783e0dc4 1175 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1176
1d483901
DC		 1177 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1178 ha->flags.mbox_busy) ||
1179 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1180 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1181 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1182 break;
86fbee86 1183 msleep(1000);
783e0dc4 1184 }
86fbee86
LC		 1185}
1186
2533cf67
LC		 1187int
1188qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1189{
1190 int return_status;
1191 unsigned long wait_reset;
1192 struct qla_hw_data *ha = vha->hw;
1193 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1194
1195 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1196 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1197 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1198 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1199 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1200
1201 msleep(1000);
1202
1203 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1204 ha->flags.chip_reset_done)
1205 break;
1206 }
1207 if (ha->flags.chip_reset_done)
1208 return_status = QLA_SUCCESS;
1209 else
1210 return_status = QLA_FUNCTION_FAILED;
1211
1212 return return_status;
1213}
1214
083a469d
GM		 1215static void
1216sp_get(struct srb *sp)
1217{
1218 atomic_inc(&sp->ref_count);
1219}
1220
a465537a
SC		 1221#define ISP_REG_DISCONNECT 0xffffffffU
1222/**************************************************************************
1223* qla2x00_isp_reg_stat
1224*
1225* Description:
1226* Read the host status register of ISP before aborting the command.
1227*
1228* Input:
1229* ha = pointer to host adapter structure.
1230*
1231*
1232* Returns:
1233* Either true or false.
1234*
1235* Note: Return true if there is register disconnect.
1236**************************************************************************/
1237static inline
1238uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1239{
1240 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1241 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1242
bf6061b1
SC		 1243 if (IS_P3P_TYPE(ha))
1244 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1245 else
1246 return ((RD_REG_DWORD(&reg->host_status)) ==
1247 ISP_REG_DISCONNECT);
a465537a
SC		 1248}
1249
1da177e4
LT		 1250/**************************************************************************
1251* qla2xxx_eh_abort
1252*
1253* Description:
1254* The abort function will abort the specified command.
1255*
1256* Input:
1257* cmd = Linux SCSI command packet to be aborted.
1258*
1259* Returns:
1260* Either SUCCESS or FAILED.
1261*
1262* Note:
2ea00202 1263* Only return FAILED if command not returned by firmware.
1da177e4 1264**************************************************************************/
e5f82ab8 1265static int
1da177e4
LT		 1266qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1267{
e315cd28 1268 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1269 srb_t *sp;
4e98d3b8 1270 int ret;
9cb78c16
HR		 1271 unsigned int id;
1272 uint64_t lun;
18e144d3 1273 unsigned long flags;
f934c9d0 1274 int rval, wait = 0;
e315cd28 1275 struct qla_hw_data *ha = vha->hw;
1da177e4 1276
a465537a
SC		 1277 if (qla2x00_isp_reg_stat(ha)) {
1278 ql_log(ql_log_info, vha, 0x8042,
1279 "PCI/Register disconnect, exiting.\n");
1280 return FAILED;
1281 }
f4f051eb 1282 if (!CMD_SP(cmd))
2ea00202 1283 return SUCCESS;
1da177e4 1284
4e98d3b8
AV		 1285 ret = fc_block_scsi_eh(cmd);
1286 if (ret != 0)
1287 return ret;
1288 ret = SUCCESS;
1289
f4f051eb 1290 id = cmd->device->id;
1291 lun = cmd->device->lun;
1da177e4 1292
e315cd28 1293 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1294 sp = (srb_t *) CMD_SP(cmd);
1295 if (!sp) {
1296 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1297 return SUCCESS;
1298 }
1da177e4 1299
7c3df132 1300 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1301 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1302 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1303
170babc3
MC		 1304 /* Get a reference to the sp and drop the lock.*/
1305 sp_get(sp);
083a469d 1306
e315cd28 1307 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1308 rval = ha->isp_ops->abort_command(sp);
1309 if (rval) {
96219424 1310 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1311 ret = SUCCESS;
96219424 1312 else
f934c9d0
CD		 1313 ret = FAILED;
1314
7c3df132 1315 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1316 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1317 } else {
7c3df132 1318 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1319 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1320 wait = 1;
1321 }
75942064
SK		 1322
1323 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1324 sp->done(sp, 0);
75942064 1325 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1326
bc91ade9
CD		 1327 /* Did the command return during mailbox execution? */
1328 if (ret == FAILED && !CMD_SP(cmd))
1329 ret = SUCCESS;
1330
f4f051eb 1331 /* Wait for the command to be returned. */
2ea00202 1332 if (wait) {
e315cd28 1333 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1334 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1335 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1336 ret = FAILED;
f4f051eb 1337 }
1da177e4 1338 }
1da177e4 1339
7c3df132 1340 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1341 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1342 vha->host_no, id, lun, wait, ret);
1da177e4 1343
f4f051eb 1344 return ret;
1345}
1da177e4 1346
4d78c973 1347int
e315cd28 1348qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1349 uint64_t l, enum nexus_wait_type type)
f4f051eb 1350{
17d98630 1351 int cnt, match, status;
18e144d3 1352 unsigned long flags;
e315cd28 1353 struct qla_hw_data *ha = vha->hw;
73208dfd 1354 struct req_que *req;
4d78c973 1355 srb_t *sp;
9ba56b95 1356 struct scsi_cmnd *cmd;
1da177e4 1357
523ec773 1358 status = QLA_SUCCESS;
17d98630 1359
e315cd28 1360 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1361 req = vha->req;
17d98630 1362 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1363 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1364 sp = req->outstanding_cmds[cnt];
1365 if (!sp)
523ec773 1366 continue;
9ba56b95 1367 if (sp->type != SRB_SCSI_CMD)
cf53b069 1368 continue;
25ff6af1 1369 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1370 continue;
1371 match = 0;
9ba56b95 1372 cmd = GET_CMD_SP(sp);
17d98630
AC		 1373 switch (type) {
1374 case WAIT_HOST:
1375 match = 1;
1376 break;
1377 case WAIT_TARGET:
9ba56b95 1378 match = cmd->device->id == t;
17d98630
AC		 1379 break;
1380 case WAIT_LUN:
9ba56b95
GM		 1381 match = (cmd->device->id == t &&
1382 cmd->device->lun == l);
17d98630 1383 break;
73208dfd 1384 }
17d98630
AC		 1385 if (!match)
1386 continue;
1387
1388 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1389 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1390 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1391 }
e315cd28 1392 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1393
1394 return status;
1da177e4
LT		 1395}
1396
523ec773
AV		 1397static char *reset_errors[] = {
1398 "HBA not online",
1399 "HBA not ready",
1400 "Task management failed",
1401 "Waiting for command completions",
1402};
1da177e4 1403
e5f82ab8 1404static int
523ec773 1405__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1406 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1407{
e315cd28 1408 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1409 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1410 int err;
1da177e4 1411
7c3df132 1412 if (!fcport) {
523ec773 1413 return FAILED;
7c3df132 1414 }
1da177e4 1415
4e98d3b8
AV		 1416 err = fc_block_scsi_eh(cmd);
1417 if (err != 0)
1418 return err;
1419
7c3df132 1420 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1421 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1422 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1423
523ec773 1424 err = 0;
7c3df132
SK		 1425 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1426 ql_log(ql_log_warn, vha, 0x800a,
1427 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1428 goto eh_reset_failed;
7c3df132 1429 }
523ec773 1430 err = 2;
2afa19a9 1431 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1432 != QLA_SUCCESS) {
1433 ql_log(ql_log_warn, vha, 0x800c,
1434 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1435 goto eh_reset_failed;
7c3df132 1436 }
523ec773 1437 err = 3;
e315cd28 1438 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1439 cmd->device->lun, type) != QLA_SUCCESS) {
1440 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1441 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1442 goto eh_reset_failed;
7c3df132 1443 }
523ec773 1444
7c3df132 1445 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1446 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1447 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1448
1449 return SUCCESS;
1450
4d78c973 1451eh_reset_failed:
7c3df132 1452 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1453 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1454 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1455 cmd);
523ec773
AV		 1456 return FAILED;
1457}
1da177e4 1458
523ec773
AV		 1459static int
1460qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1461{
e315cd28
AC		 1462 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1463 struct qla_hw_data *ha = vha->hw;
1da177e4 1464
a465537a
SC		 1465 if (qla2x00_isp_reg_stat(ha)) {
1466 ql_log(ql_log_info, vha, 0x803e,
1467 "PCI/Register disconnect, exiting.\n");
1468 return FAILED;
1469 }
1470
523ec773
AV		 1471 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1472 ha->isp_ops->lun_reset);
1da177e4
LT		 1473}
1474
1da177e4 1475static int
523ec773 1476qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1477{
e315cd28
AC		 1478 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1479 struct qla_hw_data *ha = vha->hw;
1da177e4 1480
a465537a
SC		 1481 if (qla2x00_isp_reg_stat(ha)) {
1482 ql_log(ql_log_info, vha, 0x803f,
1483 "PCI/Register disconnect, exiting.\n");
1484 return FAILED;
1485 }
1486
523ec773
AV		 1487 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1488 ha->isp_ops->target_reset);
1da177e4
LT		 1489}
1490
1da177e4
LT		 1491/**************************************************************************
1492* qla2xxx_eh_bus_reset
1493*
1494* Description:
1495* The bus reset function will reset the bus and abort any executing
1496* commands.
1497*
1498* Input:
1499* cmd = Linux SCSI command packet of the command that cause the
1500* bus reset.
1501*
1502* Returns:
1503* SUCCESS/FAILURE (defined as macro in scsi.h).
1504*
1505**************************************************************************/
e5f82ab8 1506static int
1da177e4
LT		 1507qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1508{
e315cd28 1509 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1510 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1511 int ret = FAILED;
9cb78c16
HR		 1512 unsigned int id;
1513 uint64_t lun;
a465537a
SC		 1514 struct qla_hw_data *ha = vha->hw;
1515
1516 if (qla2x00_isp_reg_stat(ha)) {
1517 ql_log(ql_log_info, vha, 0x8040,
1518 "PCI/Register disconnect, exiting.\n");
1519 return FAILED;
1520 }
f4f051eb 1521
f4f051eb 1522 id = cmd->device->id;
1523 lun = cmd->device->lun;
1da177e4 1524
7c3df132 1525 if (!fcport) {
f4f051eb 1526 return ret;
7c3df132 1527 }
1da177e4 1528
4e98d3b8
AV		 1529 ret = fc_block_scsi_eh(cmd);
1530 if (ret != 0)
1531 return ret;
1532 ret = FAILED;
1533
7c3df132 1534 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1535 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1536
e315cd28 1537 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1538 ql_log(ql_log_fatal, vha, 0x8013,
1539 "Wait for hba online failed board disabled.\n");
f4f051eb 1540 goto eh_bus_reset_done;
1da177e4
LT		 1541 }
1542
ad537689
SK		 1543 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1544 ret = SUCCESS;
1545
f4f051eb 1546 if (ret == FAILED)
1547 goto eh_bus_reset_done;
1da177e4 1548
9a41a62b 1549 /* Flush outstanding commands. */
4d78c973 1550 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1551 QLA_SUCCESS) {
1552 ql_log(ql_log_warn, vha, 0x8014,
1553 "Wait for pending commands failed.\n");
9a41a62b 1554 ret = FAILED;
7c3df132 1555 }
1da177e4 1556
f4f051eb 1557eh_bus_reset_done:
7c3df132 1558 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1559 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1560 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1561
f4f051eb 1562 return ret;
1da177e4
LT		 1563}
1564
1565/**************************************************************************
1566* qla2xxx_eh_host_reset
1567*
1568* Description:
1569* The reset function will reset the Adapter.
1570*
1571* Input:
1572* cmd = Linux SCSI command packet of the command that cause the
1573* adapter reset.
1574*
1575* Returns:
1576* Either SUCCESS or FAILED.
1577*
1578* Note:
1579**************************************************************************/
e5f82ab8 1580static int
1da177e4
LT		 1581qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1582{
e315cd28 1583 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1584 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1585 int ret = FAILED;
9cb78c16
HR		 1586 unsigned int id;
1587 uint64_t lun;
e315cd28 1588 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1589
a465537a
SC		 1590 if (qla2x00_isp_reg_stat(ha)) {
1591 ql_log(ql_log_info, vha, 0x8041,
1592 "PCI/Register disconnect, exiting.\n");
1593 schedule_work(&ha->board_disable);
1594 return SUCCESS;
1595 }
1596
f4f051eb 1597 id = cmd->device->id;
1598 lun = cmd->device->lun;
f4f051eb 1599
7c3df132 1600 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1601 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1602
63ee7072
CD		 1603 /*
1604 * No point in issuing another reset if one is active. Also do not
1605 * attempt a reset if we are updating flash.
1606 */
1607 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1608 goto eh_host_reset_lock;
1da177e4 1609
e315cd28
AC		 1610 if (vha != base_vha) {
1611 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1612 goto eh_host_reset_lock;
e315cd28 1613 } else {
7ec0effd 1614 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1615 if (!qla82xx_fcoe_ctx_reset(vha)) {
1616 /* Ctx reset success */
1617 ret = SUCCESS;
1618 goto eh_host_reset_lock;
1619 }
1620 /* fall thru if ctx reset failed */
1621 }
68ca949c
AC		 1622 if (ha->wq)
1623 flush_workqueue(ha->wq);
1624
e315cd28 1625 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1626 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1627 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1628 /* failed. schedule dpc to try */
1629 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1630
7c3df132
SK		 1631 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1632 ql_log(ql_log_warn, vha, 0x802a,
1633 "wait for hba online failed.\n");
e315cd28 1634 goto eh_host_reset_lock;
7c3df132 1635 }
e315cd28
AC		 1636 }
1637 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1638 }
1da177e4 1639
e315cd28 1640 /* Waiting for command to be returned to OS.*/
4d78c973 1641 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1642 QLA_SUCCESS)
f4f051eb 1643 ret = SUCCESS;
1da177e4 1644
f4f051eb 1645eh_host_reset_lock:
cfb0919c 1646 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1647 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1648 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1649
f4f051eb 1650 return ret;
1651}
1da177e4
LT		 1652
1653/*
1654* qla2x00_loop_reset
1655* Issue loop reset.
1656*
1657* Input:
1658* ha = adapter block pointer.
1659*
1660* Returns:
1661* 0 = success
1662*/
a4722cf2 1663int
e315cd28 1664qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1665{
0c8c39af 1666 int ret;
bdf79621 1667 struct fc_port *fcport;
e315cd28 1668 struct qla_hw_data *ha = vha->hw;
1da177e4 1669
5854771e
AB		 1670 if (IS_QLAFX00(ha)) {
1671 return qlafx00_loop_reset(vha);
1672 }
1673
f4c496c1 1674 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1675 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1676 if (fcport->port_type != FCT_TARGET)
1677 continue;
1678
1679 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1680 if (ret != QLA_SUCCESS) {
7c3df132 1681 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1682 "Bus Reset failed: Reset=%d "
7c3df132 1683 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1684 }
1685 }
1686 }
1687
8ae6d9c7 1688
6246b8a1 1689 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1690 atomic_set(&vha->loop_state, LOOP_DOWN);
1691 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1692 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1693 ret = qla2x00_full_login_lip(vha);
0c8c39af 1694 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1695 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1696 "full_login_lip=%d.\n", ret);
749af3d5 1697 }
0c8c39af
AV		 1698 }
1699
0d6e61bc 1700 if (ha->flags.enable_lip_reset) {
e315cd28 1701 ret = qla2x00_lip_reset(vha);
ad537689 1702 if (ret != QLA_SUCCESS)
7c3df132
SK		 1703 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1704 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1705 }
1706
1da177e4 1707 /* Issue marker command only when we are going to start the I/O */
e315cd28 1708 vha->marker_needed = 1;
1da177e4 1709
0c8c39af 1710 return QLA_SUCCESS;
1da177e4
LT		 1711}
1712
bbead493
QT		 1713static void
1714__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
df4bf0bb 1715{
bbead493 1716 int cnt, status;
df4bf0bb
AV		 1717 unsigned long flags;
1718 srb_t *sp;
bbead493 1719 scsi_qla_host_t *vha = qp->vha;
e315cd28 1720 struct qla_hw_data *ha = vha->hw;
73208dfd 1721 struct req_que *req;
c5419e26
QT		 1722 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1723 struct qla_tgt_cmd *cmd;
1724 uint8_t trace = 0;
c0cb4496 1725
bbead493
QT		 1726 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1727 req = qp->req;
1728 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1729 sp = req->outstanding_cmds[cnt];
1730 if (sp) {
1731 req->outstanding_cmds[cnt] = NULL;
1732 if (sp->cmd_type == TYPE_SRB) {
1733 if (sp->type == SRB_NVME_CMD ||
1734 sp->type == SRB_NVME_LS) {
1735 sp_get(sp);
1736 spin_unlock_irqrestore(qp->qp_lock_ptr,
1737 flags);
1738 qla_nvme_abort(ha, sp);
1739 spin_lock_irqsave(qp->qp_lock_ptr,
1740 flags);
1741 } else if (GET_CMD_SP(sp) &&
1742 !ha->flags.eeh_busy &&
1743 (!test_bit(ABORT_ISP_ACTIVE,
1744 &vha->dpc_flags)) &&
1745 (sp->type == SRB_SCSI_CMD)) {
1746 /*
1747 * Don't abort commands in
1748 * adapter during EEH
1749 * recovery as it's not
1750 * accessible/responding.
1751 *
1752 * Get a reference to the sp
1753 * and drop the lock. The
1754 * reference ensures this
1755 * sp->done() call and not the
1756 * call in qla2xxx_eh_abort()
1757 * ends the SCSI command (with
1758 * result 'res').
1759 */
1760 sp_get(sp);
1761 spin_unlock_irqrestore(qp->qp_lock_ptr,
1762 flags);
1763 status = qla2xxx_eh_abort(
1764 GET_CMD_SP(sp));
1765 spin_lock_irqsave(qp->qp_lock_ptr,
1766 flags);
1767 /*
1768 * Get rid of extra reference
1769 * if immediate exit from
1770 * ql2xxx_eh_abort
1771 */
1772 if (status == FAILED &&
1773 (qla2x00_isp_reg_stat(ha)))
1774 atomic_dec(
1775 &sp->ref_count);
1776 }
1777 sp->done(sp, res);
1778 } else {
1779 if (!vha->hw->tgt.tgt_ops || !tgt ||
1780 qla_ini_mode_enabled(vha)) {
1781 if (!trace)
1782 ql_dbg(ql_dbg_tgt_mgt,
1783 vha, 0xf003,
1784 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1785 vha->dpc_flags);
1786 continue;
c733ab35 1787 }
bbead493
QT		 1788 cmd = (struct qla_tgt_cmd *)sp;
1789 qlt_abort_cmd_on_host_reset(cmd->vha, cmd);
73208dfd 1790 }
df4bf0bb
AV		 1791 }
1792 }
bbead493
QT		 1793 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1794}
1795
1796void
1797qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1798{
1799 int que;
1800 struct qla_hw_data *ha = vha->hw;
1801
1802 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1803
1804 for (que = 0; que < ha->max_qpairs; que++) {
1805 if (!ha->queue_pair_map[que])
1806 continue;
1807
1808 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1809 }
df4bf0bb
AV		 1810}
1811
f4f051eb 1812static int
1813qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1814{
bdf79621 1815 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1816
19a7b4ae 1817 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1818 return -ENXIO;
bdf79621 1819
19a7b4ae 1820 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1821
f4f051eb 1822 return 0;
1823}
1da177e4 1824
f4f051eb 1825static int
1826qla2xxx_slave_configure(struct scsi_device *sdev)
1827{
e315cd28 1828 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1829 struct req_que *req = vha->req;
8482e118 1830
9e522cd8
AE		 1831 if (IS_T10_PI_CAPABLE(vha->hw))
1832 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1833
db5ed4df 1834 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb 1835 return 0;
1836}
1da177e4 1837
f4f051eb 1838static void
1839qla2xxx_slave_destroy(struct scsi_device *sdev)
1840{
1841 sdev->hostdata = NULL;
1da177e4
LT		 1842}
1843
1844/**
1845 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1846 * @ha: HA context
1847 *
1848 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1849 * supported addressing method.
1850 */
1851static void
53303c42 1852qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1853{
7524f9b9 1854 /* Assume a 32bit DMA mask. */
1da177e4 1855 ha->flags.enable_64bit_addressing = 0;
1da177e4 1856
6a35528a 1857 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1858 /* Any upper-dword bits set? */
1859 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1860 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1861 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1862 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1863 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1864 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1865 return;
1da177e4 1866 }
1da177e4 1867 }
7524f9b9 1868
284901a9
YH		 1869 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1870 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1871}
1872
fd34f556 1873static void
e315cd28 1874qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1875{
1876 unsigned long flags = 0;
1877 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1878
1879 spin_lock_irqsave(&ha->hardware_lock, flags);
1880 ha->interrupts_on = 1;
1881 /* enable risc and host interrupts */
1882 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1883 RD_REG_WORD(&reg->ictrl);
1884 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1885
1886}
1887
1888static void
e315cd28 1889qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1890{
1891 unsigned long flags = 0;
1892 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1893
1894 spin_lock_irqsave(&ha->hardware_lock, flags);
1895 ha->interrupts_on = 0;
1896 /* disable risc and host interrupts */
1897 WRT_REG_WORD(&reg->ictrl, 0);
1898 RD_REG_WORD(&reg->ictrl);
1899 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1900}
1901
1902static void
e315cd28 1903qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1904{
1905 unsigned long flags = 0;
1906 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1907
1908 spin_lock_irqsave(&ha->hardware_lock, flags);
1909 ha->interrupts_on = 1;
1910 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1911 RD_REG_DWORD(&reg->ictrl);
1912 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1913}
1914
1915static void
e315cd28 1916qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1917{
1918 unsigned long flags = 0;
1919 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1920
124f85e6
AV		 1921 if (IS_NOPOLLING_TYPE(ha))
1922 return;
fd34f556
AV		 1923 spin_lock_irqsave(&ha->hardware_lock, flags);
1924 ha->interrupts_on = 0;
1925 WRT_REG_DWORD(&reg->ictrl, 0);
1926 RD_REG_DWORD(&reg->ictrl);
1927 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1928}
1929
706f457d
GM		 1930static int
1931qla2x00_iospace_config(struct qla_hw_data *ha)
1932{
1933 resource_size_t pio;
1934 uint16_t msix;
706f457d 1935
706f457d
GM		 1936 if (pci_request_selected_regions(ha->pdev, ha->bars,
1937 QLA2XXX_DRIVER_NAME)) {
1938 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1939 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1940 pci_name(ha->pdev));
1941 goto iospace_error_exit;
1942 }
1943 if (!(ha->bars & 1))
1944 goto skip_pio;
1945
1946 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1947 pio = pci_resource_start(ha->pdev, 0);
1948 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1949 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1950 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1951 "Invalid pci I/O region size (%s).\n",
1952 pci_name(ha->pdev));
1953 pio = 0;
1954 }
1955 } else {
1956 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1957 "Region #0 no a PIO resource (%s).\n",
1958 pci_name(ha->pdev));
1959 pio = 0;
1960 }
1961 ha->pio_address = pio;
1962 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1963 "PIO address=%llu.\n",
1964 (unsigned long long)ha->pio_address);
1965
1966skip_pio:
1967 /* Use MMIO operations for all accesses. */
1968 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1969 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1970 "Region #1 not an MMIO resource (%s), aborting.\n",
1971 pci_name(ha->pdev));
1972 goto iospace_error_exit;
1973 }
1974 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1975 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1976 "Invalid PCI mem region size (%s), aborting.\n",
1977 pci_name(ha->pdev));
1978 goto iospace_error_exit;
1979 }
1980
1981 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1982 if (!ha->iobase) {
1983 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1984 "Cannot remap MMIO (%s), aborting.\n",
1985 pci_name(ha->pdev));
1986 goto iospace_error_exit;
1987 }
1988
1989 /* Determine queue resources */
1990 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1991 ha->msix_count = QLA_BASE_VECTORS;
c38d1baf
HM		 1992 if (!ql2xmqsupport || !ql2xnvmeenable ||
1993 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1994 goto mqiobase_exit;
1995
1996 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1997 pci_resource_len(ha->pdev, 3));
1998 if (ha->mqiobase) {
1999 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2000 "MQIO Base=%p.\n", ha->mqiobase);
2001 /* Read MSIX vector size of the board */
2002 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 2003 ha->msix_count = msix + 1;
706f457d 2004 /* Max queues are bounded by available msix vectors */
d7459527
MH		 2005 /* MB interrupt uses 1 vector */
2006 ha->max_req_queues = ha->msix_count - 1;
2007 ha->max_rsp_queues = ha->max_req_queues;
2008 /* Queue pairs is the max value minus the base queue pair */
2009 ha->max_qpairs = ha->max_rsp_queues - 1;
2010 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2011 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2012
706f457d 2013 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 2014 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 2015 } else
2016 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2017 "BAR 3 not enabled.\n");
2018
2019mqiobase_exit:
706f457d 2020 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 2021 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 2022 return (0);
2023
2024iospace_error_exit:
2025 return (-ENOMEM);
2026}
2027
2028
6246b8a1
GM		 2029static int
2030qla83xx_iospace_config(struct qla_hw_data *ha)
2031{
2032 uint16_t msix;
6246b8a1
GM		 2033
2034 if (pci_request_selected_regions(ha->pdev, ha->bars,
2035 QLA2XXX_DRIVER_NAME)) {
2036 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2037 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2038 pci_name(ha->pdev));
2039
2040 goto iospace_error_exit;
2041 }
2042
2043 /* Use MMIO operations for all accesses. */
2044 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2045 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2046 "Invalid pci I/O region size (%s).\n",
2047 pci_name(ha->pdev));
2048 goto iospace_error_exit;
2049 }
2050 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2051 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2052 "Invalid PCI mem region size (%s), aborting\n",
2053 pci_name(ha->pdev));
2054 goto iospace_error_exit;
2055 }
2056
2057 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2058 if (!ha->iobase) {
2059 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2060 "Cannot remap MMIO (%s), aborting.\n",
2061 pci_name(ha->pdev));
2062 goto iospace_error_exit;
2063 }
2064
2065 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2066 /* 83XX 26XX always use MQ type access for queues
2067 * - mbar 2, a.k.a region 4 */
2068 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2069 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2070 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2071 pci_resource_len(ha->pdev, 4));
2072
2073 if (!ha->mqiobase) {
2074 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2075 "BAR2/region4 not enabled\n");
2076 goto mqiobase_exit;
2077 }
2078
2079 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2080 pci_resource_len(ha->pdev, 2));
2081 if (ha->msixbase) {
2082 /* Read MSIX vector size of the board */
2083 pci_read_config_word(ha->pdev,
2084 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2085 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2086 /*
2087 * By default, driver uses at least two msix vectors
2088 * (default & rspq)
2089 */
c38d1baf 2090 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 2091 /* MB interrupt uses 1 vector */
2092 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2093
2094 /* ATIOQ needs 1 vector. That's 1 less QPair */
2095 if (QLA_TGT_MODE_ENABLED())
2096 ha->max_req_queues--;
2097
d0d2c68b
MH		 2098 ha->max_rsp_queues = ha->max_req_queues;
2099
d7459527
MH		 2100 /* Queue pairs is the max value minus
2101 * the base queue pair */
2102 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2103 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2104 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2105 }
2106 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2107 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2108 } else
2109 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2110 "BAR 1 not enabled.\n");
2111
2112mqiobase_exit:
6246b8a1 2113 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2114 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2115 return 0;
2116
2117iospace_error_exit:
2118 return -ENOMEM;
2119}
2120
fd34f556
AV		 2121static struct isp_operations qla2100_isp_ops = {
2122 .pci_config = qla2100_pci_config,
2123 .reset_chip = qla2x00_reset_chip,
2124 .chip_diag = qla2x00_chip_diag,
2125 .config_rings = qla2x00_config_rings,
2126 .reset_adapter = qla2x00_reset_adapter,
2127 .nvram_config = qla2x00_nvram_config,
2128 .update_fw_options = qla2x00_update_fw_options,
2129 .load_risc = qla2x00_load_risc,
2130 .pci_info_str = qla2x00_pci_info_str,
2131 .fw_version_str = qla2x00_fw_version_str,
2132 .intr_handler = qla2100_intr_handler,
2133 .enable_intrs = qla2x00_enable_intrs,
2134 .disable_intrs = qla2x00_disable_intrs,
2135 .abort_command = qla2x00_abort_command,
523ec773
AV		 2136 .target_reset = qla2x00_abort_target,
2137 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2138 .fabric_login = qla2x00_login_fabric,
2139 .fabric_logout = qla2x00_fabric_logout,
2140 .calc_req_entries = qla2x00_calc_iocbs_32,
2141 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2142 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2143 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2144 .read_nvram = qla2x00_read_nvram_data,
2145 .write_nvram = qla2x00_write_nvram_data,
2146 .fw_dump = qla2100_fw_dump,
2147 .beacon_on = NULL,
2148 .beacon_off = NULL,
2149 .beacon_blink = NULL,
2150 .read_optrom = qla2x00_read_optrom_data,
2151 .write_optrom = qla2x00_write_optrom_data,
2152 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2153 .start_scsi = qla2x00_start_scsi,
d7459527 2154 .start_scsi_mq = NULL,
a9083016 2155 .abort_isp = qla2x00_abort_isp,
706f457d 2156 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2157 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2158};
2159
2160static struct isp_operations qla2300_isp_ops = {
2161 .pci_config = qla2300_pci_config,
2162 .reset_chip = qla2x00_reset_chip,
2163 .chip_diag = qla2x00_chip_diag,
2164 .config_rings = qla2x00_config_rings,
2165 .reset_adapter = qla2x00_reset_adapter,
2166 .nvram_config = qla2x00_nvram_config,
2167 .update_fw_options = qla2x00_update_fw_options,
2168 .load_risc = qla2x00_load_risc,
2169 .pci_info_str = qla2x00_pci_info_str,
2170 .fw_version_str = qla2x00_fw_version_str,
2171 .intr_handler = qla2300_intr_handler,
2172 .enable_intrs = qla2x00_enable_intrs,
2173 .disable_intrs = qla2x00_disable_intrs,
2174 .abort_command = qla2x00_abort_command,
523ec773
AV		 2175 .target_reset = qla2x00_abort_target,
2176 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2177 .fabric_login = qla2x00_login_fabric,
2178 .fabric_logout = qla2x00_fabric_logout,
2179 .calc_req_entries = qla2x00_calc_iocbs_32,
2180 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2181 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2182 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2183 .read_nvram = qla2x00_read_nvram_data,
2184 .write_nvram = qla2x00_write_nvram_data,
2185 .fw_dump = qla2300_fw_dump,
2186 .beacon_on = qla2x00_beacon_on,
2187 .beacon_off = qla2x00_beacon_off,
2188 .beacon_blink = qla2x00_beacon_blink,
2189 .read_optrom = qla2x00_read_optrom_data,
2190 .write_optrom = qla2x00_write_optrom_data,
2191 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2192 .start_scsi = qla2x00_start_scsi,
d7459527 2193 .start_scsi_mq = NULL,
a9083016 2194 .abort_isp = qla2x00_abort_isp,
7ec0effd 2195 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2196 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2197};
2198
2199static struct isp_operations qla24xx_isp_ops = {
2200 .pci_config = qla24xx_pci_config,
2201 .reset_chip = qla24xx_reset_chip,
2202 .chip_diag = qla24xx_chip_diag,
2203 .config_rings = qla24xx_config_rings,
2204 .reset_adapter = qla24xx_reset_adapter,
2205 .nvram_config = qla24xx_nvram_config,
2206 .update_fw_options = qla24xx_update_fw_options,
2207 .load_risc = qla24xx_load_risc,
2208 .pci_info_str = qla24xx_pci_info_str,
2209 .fw_version_str = qla24xx_fw_version_str,
2210 .intr_handler = qla24xx_intr_handler,
2211 .enable_intrs = qla24xx_enable_intrs,
2212 .disable_intrs = qla24xx_disable_intrs,
2213 .abort_command = qla24xx_abort_command,
523ec773
AV		 2214 .target_reset = qla24xx_abort_target,
2215 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2216 .fabric_login = qla24xx_login_fabric,
2217 .fabric_logout = qla24xx_fabric_logout,
2218 .calc_req_entries = NULL,
2219 .build_iocbs = NULL,
2220 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2221 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2222 .read_nvram = qla24xx_read_nvram_data,
2223 .write_nvram = qla24xx_write_nvram_data,
2224 .fw_dump = qla24xx_fw_dump,
2225 .beacon_on = qla24xx_beacon_on,
2226 .beacon_off = qla24xx_beacon_off,
2227 .beacon_blink = qla24xx_beacon_blink,
2228 .read_optrom = qla24xx_read_optrom_data,
2229 .write_optrom = qla24xx_write_optrom_data,
2230 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2231 .start_scsi = qla24xx_start_scsi,
d7459527 2232 .start_scsi_mq = NULL,
a9083016 2233 .abort_isp = qla2x00_abort_isp,
7ec0effd 2234 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2235 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2236};
2237
c3a2f0df
AV		 2238static struct isp_operations qla25xx_isp_ops = {
2239 .pci_config = qla25xx_pci_config,
2240 .reset_chip = qla24xx_reset_chip,
2241 .chip_diag = qla24xx_chip_diag,
2242 .config_rings = qla24xx_config_rings,
2243 .reset_adapter = qla24xx_reset_adapter,
2244 .nvram_config = qla24xx_nvram_config,
2245 .update_fw_options = qla24xx_update_fw_options,
2246 .load_risc = qla24xx_load_risc,
2247 .pci_info_str = qla24xx_pci_info_str,
2248 .fw_version_str = qla24xx_fw_version_str,
2249 .intr_handler = qla24xx_intr_handler,
2250 .enable_intrs = qla24xx_enable_intrs,
2251 .disable_intrs = qla24xx_disable_intrs,
2252 .abort_command = qla24xx_abort_command,
523ec773
AV		 2253 .target_reset = qla24xx_abort_target,
2254 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2255 .fabric_login = qla24xx_login_fabric,
2256 .fabric_logout = qla24xx_fabric_logout,
2257 .calc_req_entries = NULL,
2258 .build_iocbs = NULL,
2259 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2260 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2261 .read_nvram = qla25xx_read_nvram_data,
2262 .write_nvram = qla25xx_write_nvram_data,
2263 .fw_dump = qla25xx_fw_dump,
2264 .beacon_on = qla24xx_beacon_on,
2265 .beacon_off = qla24xx_beacon_off,
2266 .beacon_blink = qla24xx_beacon_blink,
338c9161 2267 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2268 .write_optrom = qla24xx_write_optrom_data,
2269 .get_flash_version = qla24xx_get_flash_version,
bad75002 2270 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2271 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2272 .abort_isp = qla2x00_abort_isp,
7ec0effd 2273 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2274 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2275};
2276
3a03eb79
AV		 2277static struct isp_operations qla81xx_isp_ops = {
2278 .pci_config = qla25xx_pci_config,
2279 .reset_chip = qla24xx_reset_chip,
2280 .chip_diag = qla24xx_chip_diag,
2281 .config_rings = qla24xx_config_rings,
2282 .reset_adapter = qla24xx_reset_adapter,
2283 .nvram_config = qla81xx_nvram_config,
2284 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2285 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2286 .pci_info_str = qla24xx_pci_info_str,
2287 .fw_version_str = qla24xx_fw_version_str,
2288 .intr_handler = qla24xx_intr_handler,
2289 .enable_intrs = qla24xx_enable_intrs,
2290 .disable_intrs = qla24xx_disable_intrs,
2291 .abort_command = qla24xx_abort_command,
2292 .target_reset = qla24xx_abort_target,
2293 .lun_reset = qla24xx_lun_reset,
2294 .fabric_login = qla24xx_login_fabric,
2295 .fabric_logout = qla24xx_fabric_logout,
2296 .calc_req_entries = NULL,
2297 .build_iocbs = NULL,
2298 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2299 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2300 .read_nvram = NULL,
2301 .write_nvram = NULL,
3a03eb79
AV		 2302 .fw_dump = qla81xx_fw_dump,
2303 .beacon_on = qla24xx_beacon_on,
2304 .beacon_off = qla24xx_beacon_off,
6246b8a1 2305 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2306 .read_optrom = qla25xx_read_optrom_data,
2307 .write_optrom = qla24xx_write_optrom_data,
2308 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2309 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2310 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2311 .abort_isp = qla2x00_abort_isp,
7ec0effd 2312 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2313 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2314};
2315
2316static struct isp_operations qla82xx_isp_ops = {
2317 .pci_config = qla82xx_pci_config,
2318 .reset_chip = qla82xx_reset_chip,
2319 .chip_diag = qla24xx_chip_diag,
2320 .config_rings = qla82xx_config_rings,
2321 .reset_adapter = qla24xx_reset_adapter,
2322 .nvram_config = qla81xx_nvram_config,
2323 .update_fw_options = qla24xx_update_fw_options,
2324 .load_risc = qla82xx_load_risc,
9d55ca66 2325 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2326 .fw_version_str = qla24xx_fw_version_str,
2327 .intr_handler = qla82xx_intr_handler,
2328 .enable_intrs = qla82xx_enable_intrs,
2329 .disable_intrs = qla82xx_disable_intrs,
2330 .abort_command = qla24xx_abort_command,
2331 .target_reset = qla24xx_abort_target,
2332 .lun_reset = qla24xx_lun_reset,
2333 .fabric_login = qla24xx_login_fabric,
2334 .fabric_logout = qla24xx_fabric_logout,
2335 .calc_req_entries = NULL,
2336 .build_iocbs = NULL,
2337 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2338 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2339 .read_nvram = qla24xx_read_nvram_data,
2340 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2341 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2342 .beacon_on = qla82xx_beacon_on,
2343 .beacon_off = qla82xx_beacon_off,
2344 .beacon_blink = NULL,
a9083016
GM		 2345 .read_optrom = qla82xx_read_optrom_data,
2346 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2347 .get_flash_version = qla82xx_get_flash_version,
a9083016 2348 .start_scsi = qla82xx_start_scsi,
d7459527 2349 .start_scsi_mq = NULL,
a9083016 2350 .abort_isp = qla82xx_abort_isp,
706f457d 2351 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2352 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2353};
2354
7ec0effd
AD		 2355static struct isp_operations qla8044_isp_ops = {
2356 .pci_config = qla82xx_pci_config,
2357 .reset_chip = qla82xx_reset_chip,
2358 .chip_diag = qla24xx_chip_diag,
2359 .config_rings = qla82xx_config_rings,
2360 .reset_adapter = qla24xx_reset_adapter,
2361 .nvram_config = qla81xx_nvram_config,
2362 .update_fw_options = qla24xx_update_fw_options,
2363 .load_risc = qla82xx_load_risc,
2364 .pci_info_str = qla24xx_pci_info_str,
2365 .fw_version_str = qla24xx_fw_version_str,
2366 .intr_handler = qla8044_intr_handler,
2367 .enable_intrs = qla82xx_enable_intrs,
2368 .disable_intrs = qla82xx_disable_intrs,
2369 .abort_command = qla24xx_abort_command,
2370 .target_reset = qla24xx_abort_target,
2371 .lun_reset = qla24xx_lun_reset,
2372 .fabric_login = qla24xx_login_fabric,
2373 .fabric_logout = qla24xx_fabric_logout,
2374 .calc_req_entries = NULL,
2375 .build_iocbs = NULL,
2376 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2377 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2378 .read_nvram = NULL,
2379 .write_nvram = NULL,
a1b23c5a 2380 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2381 .beacon_on = qla82xx_beacon_on,
2382 .beacon_off = qla82xx_beacon_off,
2383 .beacon_blink = NULL,
888e639d 2384 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2385 .write_optrom = qla8044_write_optrom_data,
2386 .get_flash_version = qla82xx_get_flash_version,
2387 .start_scsi = qla82xx_start_scsi,
d7459527 2388 .start_scsi_mq = NULL,
7ec0effd
AD		 2389 .abort_isp = qla8044_abort_isp,
2390 .iospace_config = qla82xx_iospace_config,
2391 .initialize_adapter = qla2x00_initialize_adapter,
2392};
2393
6246b8a1
GM		 2394static struct isp_operations qla83xx_isp_ops = {
2395 .pci_config = qla25xx_pci_config,
2396 .reset_chip = qla24xx_reset_chip,
2397 .chip_diag = qla24xx_chip_diag,
2398 .config_rings = qla24xx_config_rings,
2399 .reset_adapter = qla24xx_reset_adapter,
2400 .nvram_config = qla81xx_nvram_config,
2401 .update_fw_options = qla81xx_update_fw_options,
2402 .load_risc = qla81xx_load_risc,
2403 .pci_info_str = qla24xx_pci_info_str,
2404 .fw_version_str = qla24xx_fw_version_str,
2405 .intr_handler = qla24xx_intr_handler,
2406 .enable_intrs = qla24xx_enable_intrs,
2407 .disable_intrs = qla24xx_disable_intrs,
2408 .abort_command = qla24xx_abort_command,
2409 .target_reset = qla24xx_abort_target,
2410 .lun_reset = qla24xx_lun_reset,
2411 .fabric_login = qla24xx_login_fabric,
2412 .fabric_logout = qla24xx_fabric_logout,
2413 .calc_req_entries = NULL,
2414 .build_iocbs = NULL,
2415 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2416 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2417 .read_nvram = NULL,
2418 .write_nvram = NULL,
2419 .fw_dump = qla83xx_fw_dump,
2420 .beacon_on = qla24xx_beacon_on,
2421 .beacon_off = qla24xx_beacon_off,
2422 .beacon_blink = qla83xx_beacon_blink,
2423 .read_optrom = qla25xx_read_optrom_data,
2424 .write_optrom = qla24xx_write_optrom_data,
2425 .get_flash_version = qla24xx_get_flash_version,
2426 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2427 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2428 .abort_isp = qla2x00_abort_isp,
2429 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2430 .initialize_adapter = qla2x00_initialize_adapter,
2431};
2432
2433static struct isp_operations qlafx00_isp_ops = {
2434 .pci_config = qlafx00_pci_config,
2435 .reset_chip = qlafx00_soft_reset,
2436 .chip_diag = qlafx00_chip_diag,
2437 .config_rings = qlafx00_config_rings,
2438 .reset_adapter = qlafx00_soft_reset,
2439 .nvram_config = NULL,
2440 .update_fw_options = NULL,
2441 .load_risc = NULL,
2442 .pci_info_str = qlafx00_pci_info_str,
2443 .fw_version_str = qlafx00_fw_version_str,
2444 .intr_handler = qlafx00_intr_handler,
2445 .enable_intrs = qlafx00_enable_intrs,
2446 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2447 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2448 .target_reset = qlafx00_abort_target,
2449 .lun_reset = qlafx00_lun_reset,
2450 .fabric_login = NULL,
2451 .fabric_logout = NULL,
2452 .calc_req_entries = NULL,
2453 .build_iocbs = NULL,
2454 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2455 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2456 .read_nvram = qla24xx_read_nvram_data,
2457 .write_nvram = qla24xx_write_nvram_data,
2458 .fw_dump = NULL,
2459 .beacon_on = qla24xx_beacon_on,
2460 .beacon_off = qla24xx_beacon_off,
2461 .beacon_blink = NULL,
2462 .read_optrom = qla24xx_read_optrom_data,
2463 .write_optrom = qla24xx_write_optrom_data,
2464 .get_flash_version = qla24xx_get_flash_version,
2465 .start_scsi = qlafx00_start_scsi,
d7459527 2466 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2467 .abort_isp = qlafx00_abort_isp,
2468 .iospace_config = qlafx00_iospace_config,
2469 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2470};
2471
f73cb695
CD		 2472static struct isp_operations qla27xx_isp_ops = {
2473 .pci_config = qla25xx_pci_config,
2474 .reset_chip = qla24xx_reset_chip,
2475 .chip_diag = qla24xx_chip_diag,
2476 .config_rings = qla24xx_config_rings,
2477 .reset_adapter = qla24xx_reset_adapter,
2478 .nvram_config = qla81xx_nvram_config,
2479 .update_fw_options = qla81xx_update_fw_options,
2480 .load_risc = qla81xx_load_risc,
2481 .pci_info_str = qla24xx_pci_info_str,
2482 .fw_version_str = qla24xx_fw_version_str,
2483 .intr_handler = qla24xx_intr_handler,
2484 .enable_intrs = qla24xx_enable_intrs,
2485 .disable_intrs = qla24xx_disable_intrs,
2486 .abort_command = qla24xx_abort_command,
2487 .target_reset = qla24xx_abort_target,
2488 .lun_reset = qla24xx_lun_reset,
2489 .fabric_login = qla24xx_login_fabric,
2490 .fabric_logout = qla24xx_fabric_logout,
2491 .calc_req_entries = NULL,
2492 .build_iocbs = NULL,
2493 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2494 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2495 .read_nvram = NULL,
2496 .write_nvram = NULL,
2497 .fw_dump = qla27xx_fwdump,
2498 .beacon_on = qla24xx_beacon_on,
2499 .beacon_off = qla24xx_beacon_off,
2500 .beacon_blink = qla83xx_beacon_blink,
2501 .read_optrom = qla25xx_read_optrom_data,
2502 .write_optrom = qla24xx_write_optrom_data,
2503 .get_flash_version = qla24xx_get_flash_version,
2504 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2505 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2506 .abort_isp = qla2x00_abort_isp,
2507 .iospace_config = qla83xx_iospace_config,
2508 .initialize_adapter = qla2x00_initialize_adapter,
2509};
2510
ea5b6382 2511static inline void
e315cd28 2512qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2513{
2514 ha->device_type = DT_EXTENDED_IDS;
2515 switch (ha->pdev->device) {
2516 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2517 ha->isp_type |= DT_ISP2100;
ea5b6382 2518 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2519 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2520 break;
2521 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2522 ha->isp_type |= DT_ISP2200;
ea5b6382 2523 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2524 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2525 break;
2526 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2527 ha->isp_type |= DT_ISP2300;
4a59f71d 2528 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2529 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2530 break;
2531 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2532 ha->isp_type |= DT_ISP2312;
4a59f71d 2533 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2534 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2535 break;
2536 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2537 ha->isp_type |= DT_ISP2322;
4a59f71d 2538 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2539 if (ha->pdev->subsystem_vendor == 0x1028 &&
2540 ha->pdev->subsystem_device == 0x0170)
2541 ha->device_type |= DT_OEM_001;
441d1072 2542 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2543 break;
2544 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2545 ha->isp_type |= DT_ISP6312;
441d1072 2546 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2547 break;
2548 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2549 ha->isp_type |= DT_ISP6322;
441d1072 2550 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2551 break;
2552 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2553 ha->isp_type |= DT_ISP2422;
4a59f71d 2554 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2555 ha->device_type |= DT_FWI2;
c76f2c01 2556 ha->device_type |= DT_IIDMA;
441d1072 2557 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2558 break;
2559 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2560 ha->isp_type |= DT_ISP2432;
4a59f71d 2561 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2562 ha->device_type |= DT_FWI2;
c76f2c01 2563 ha->device_type |= DT_IIDMA;
441d1072 2564 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2565 break;
4d4df193 2566 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2567 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2568 ha->device_type |= DT_ZIO_SUPPORTED;
2569 ha->device_type |= DT_FWI2;
2570 ha->device_type |= DT_IIDMA;
2571 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2572 break;
044cc6c8 2573 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2574 ha->isp_type |= DT_ISP5422;
e428924c 2575 ha->device_type |= DT_FWI2;
441d1072 2576 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2577 break;
044cc6c8 2578 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2579 ha->isp_type |= DT_ISP5432;
e428924c 2580 ha->device_type |= DT_FWI2;
441d1072 2581 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2582 break;
c3a2f0df 2583 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2584 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2585 ha->device_type |= DT_ZIO_SUPPORTED;
2586 ha->device_type |= DT_FWI2;
2587 ha->device_type |= DT_IIDMA;
441d1072 2588 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2589 break;
3a03eb79 2590 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2591 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2592 ha->device_type |= DT_ZIO_SUPPORTED;
2593 ha->device_type |= DT_FWI2;
2594 ha->device_type |= DT_IIDMA;
2595 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2596 break;
a9083016 2597 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2598 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2599 ha->device_type |= DT_ZIO_SUPPORTED;
2600 ha->device_type |= DT_FWI2;
2601 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2602 /* Initialize 82XX ISP flags */
2603 qla82xx_init_flags(ha);
2604 break;
7ec0effd 2605 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2606 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2607 ha->device_type |= DT_ZIO_SUPPORTED;
2608 ha->device_type |= DT_FWI2;
2609 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2610 /* Initialize 82XX ISP flags */
2611 qla82xx_init_flags(ha);
2612 break;
6246b8a1 2613 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2614 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2615 ha->device_type |= DT_ZIO_SUPPORTED;
2616 ha->device_type |= DT_FWI2;
2617 ha->device_type |= DT_IIDMA;
2618 ha->device_type |= DT_T10_PI;
2619 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2620 break;
2621 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2622 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2623 ha->device_type |= DT_ZIO_SUPPORTED;
2624 ha->device_type |= DT_FWI2;
2625 ha->device_type |= DT_IIDMA;
2626 ha->device_type |= DT_T10_PI;
2627 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2628 break;
8ae6d9c7 2629 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2630 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2631 break;
f73cb695 2632 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2633 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2634 ha->device_type |= DT_ZIO_SUPPORTED;
2635 ha->device_type |= DT_FWI2;
2636 ha->device_type |= DT_IIDMA;
8ce3f570 2637 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2638 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2639 break;
2c5bbbb2 2640 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2641 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2642 ha->device_type |= DT_ZIO_SUPPORTED;
2643 ha->device_type |= DT_FWI2;
2644 ha->device_type |= DT_IIDMA;
8ce3f570 2645 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2646 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2647 break;
2b48992f 2648 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2649 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2650 ha->device_type |= DT_ZIO_SUPPORTED;
2651 ha->device_type |= DT_FWI2;
2652 ha->device_type |= DT_IIDMA;
8ce3f570 2653 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2654 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2655 break;
ea5b6382 2656 }
e5b68a61 2657
a9083016 2658 if (IS_QLA82XX(ha))
43a9c38b 2659 ha->port_no = ha->portnum & 1;
f73cb695 2660 else {
a9083016
GM		 2661 /* Get adapter physical port no from interrupt pin register. */
2662 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2663 if (IS_QLA27XX(ha))
2664 ha->port_no--;
2665 else
2666 ha->port_no = !(ha->port_no & 1);
2667 }
a9083016 2668
7c3df132 2669 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2670 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2671 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2672}
2673
1e99e33a
AV		 2674static void
2675qla2xxx_scan_start(struct Scsi_Host *shost)
2676{
e315cd28 2677 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2678
cbc8eb67
AV		 2679 if (vha->hw->flags.running_gold_fw)
2680 return;
2681
e315cd28
AC		 2682 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2683 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2684 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2685 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2686}
2687
2688static int
2689qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2690{
e315cd28 2691 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2692
a5dd506e
BK		 2693 if (test_bit(UNLOADING, &vha->dpc_flags))
2694 return 1;
e315cd28 2695 if (!vha->host)
1e99e33a 2696 return 1;
e315cd28 2697 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2698 return 1;
2699
e315cd28 2700 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2701}
2702
ec7193e2
QT		 2703static void qla2x00_iocb_work_fn(struct work_struct *work)
2704{
2705 struct scsi_qla_host *vha = container_of(work,
2706 struct scsi_qla_host, iocb_work);
9b3e0f4d
QT		 2707 struct qla_hw_data *ha = vha->hw;
2708 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2709 int i = 20;
2710 unsigned long flags;
2711
2712 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2713 return;
ec7193e2 2714
9b3e0f4d 2715 while (!list_empty(&vha->work_list) && i > 0) {
ec7193e2 2716 qla2x00_do_work(vha);
9b3e0f4d 2717 i--;
ec7193e2 2718 }
9b3e0f4d
QT		 2719
2720 spin_lock_irqsave(&vha->work_lock, flags);
2721 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2722 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 2723}
2724
1da177e4
LT		 2725/*
2726 * PCI driver interface
2727 */
6f039790 2728static int
7ee61397 2729qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2730{
a1541d5a 2731 int ret = -ENODEV;
1da177e4 2732 struct Scsi_Host *host;
e315cd28
AC		 2733 scsi_qla_host_t *base_vha = NULL;
2734 struct qla_hw_data *ha;
29856e28 2735 char pci_info[30];
7d613ac6 2736 char fw_str[30], wq_name[30];
5433383e 2737 struct scsi_host_template *sht;
642ef983 2738 int bars, mem_only = 0;
e315cd28 2739 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2740 struct req_que *req = NULL;
2741 struct rsp_que *rsp = NULL;
5601236b 2742 int i;
d7459527 2743
285d0321 2744 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2745 sht = &qla2xxx_driver_template;
5433383e 2746 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2747 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2748 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2749 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2750 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2751 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2752 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2753 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2754 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2755 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2756 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2757 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2758 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2759 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2760 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2761 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2762 mem_only = 1;
7c3df132
SK		 2763 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2764 "Mem only adapter.\n");
285d0321 2765 }
7c3df132
SK		 2766 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2767 "Bars=%d.\n", bars);
285d0321 2768
09483916
BH		 2769 if (mem_only) {
2770 if (pci_enable_device_mem(pdev))
ddff7ed4 2771 return ret;
09483916
BH		 2772 } else {
2773 if (pci_enable_device(pdev))
ddff7ed4 2774 return ret;
09483916 2775 }
285d0321 2776
0927678f
JB		 2777 /* This may fail but that's ok */
2778 pci_enable_pcie_error_reporting(pdev);
285d0321 2779
e315cd28
AC		 2780 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2781 if (!ha) {
7c3df132
SK		 2782 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2783 "Unable to allocate memory for ha.\n");
ddff7ed4 2784 goto disable_device;
1da177e4 2785 }
7c3df132
SK		 2786 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2787 "Memory allocated for ha=%p.\n", ha);
e315cd28 2788 ha->pdev = pdev;
33e79977
QT		 2789 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2790 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2791 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2792 spin_lock_init(&ha->tgt.atio_lock);
2793
deeae7a6 2794 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2795
2796 /* Clear our data area */
285d0321 2797 ha->bars = bars;
09483916 2798 ha->mem_only = mem_only;
df4bf0bb 2799 spin_lock_init(&ha->hardware_lock);
339aa70e 2800 spin_lock_init(&ha->vport_slock);
a9b6f722 2801 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2802 mutex_init(&ha->optrom_mutex);
1da177e4 2803
ea5b6382 2804 /* Set ISP-type information. */
2805 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2806
2807 /* Set EEH reset type to fundamental if required by hba */
95676112 2808 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2809 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2810 pdev->needs_freset = 1;
ca79cf66 2811
cba1e47f
CD		 2812 ha->prev_topology = 0;
2813 ha->init_cb_size = sizeof(init_cb_t);
2814 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2815 ha->optrom_size = OPTROM_SIZE_2300;
d1e3635a 2816 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
cba1e47f 2817
abbd8870 2818 /* Assign ISP specific operations. */
1da177e4 2819 if (IS_QLA2100(ha)) {
642ef983 2820 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2821 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2822 req_length = REQUEST_ENTRY_CNT_2100;
2823 rsp_length = RESPONSE_ENTRY_CNT_2100;
2824 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2825 ha->gid_list_info_size = 4;
3a03eb79
AV		 2826 ha->flash_conf_off = ~0;
2827 ha->flash_data_off = ~0;
2828 ha->nvram_conf_off = ~0;
2829 ha->nvram_data_off = ~0;
fd34f556 2830 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2831 } else if (IS_QLA2200(ha)) {
642ef983 2832 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2833 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2834 req_length = REQUEST_ENTRY_CNT_2200;
2835 rsp_length = RESPONSE_ENTRY_CNT_2100;
2836 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2837 ha->gid_list_info_size = 4;
3a03eb79
AV		 2838 ha->flash_conf_off = ~0;
2839 ha->flash_data_off = ~0;
2840 ha->nvram_conf_off = ~0;
2841 ha->nvram_data_off = ~0;
fd34f556 2842 ha->isp_ops = &qla2100_isp_ops;
fca29703 2843 } else if (IS_QLA23XX(ha)) {
642ef983 2844 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2845 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2846 req_length = REQUEST_ENTRY_CNT_2200;
2847 rsp_length = RESPONSE_ENTRY_CNT_2300;
2848 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2849 ha->gid_list_info_size = 6;
854165f4 2850 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2851 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2852 ha->flash_conf_off = ~0;
2853 ha->flash_data_off = ~0;
2854 ha->nvram_conf_off = ~0;
2855 ha->nvram_data_off = ~0;
fd34f556 2856 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2857 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2858 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2859 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2860 req_length = REQUEST_ENTRY_CNT_24XX;
2861 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2862 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2863 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2864 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2865 ha->gid_list_info_size = 8;
854165f4 2866 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2867 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2868 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2869 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2870 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2871 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2872 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2873 } else if (IS_QLA25XX(ha)) {
642ef983 2874 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2875 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2876 req_length = REQUEST_ENTRY_CNT_24XX;
2877 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2878 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2879 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2880 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2881 ha->gid_list_info_size = 8;
2882 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2883 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2884 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2885 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2886 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2887 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2888 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2889 } else if (IS_QLA81XX(ha)) {
642ef983 2890 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2891 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2892 req_length = REQUEST_ENTRY_CNT_24XX;
2893 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2894 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2895 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2896 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2897 ha->gid_list_info_size = 8;
2898 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2899 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2900 ha->isp_ops = &qla81xx_isp_ops;
2901 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2902 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2903 ha->nvram_conf_off = ~0;
2904 ha->nvram_data_off = ~0;
a9083016 2905 } else if (IS_QLA82XX(ha)) {
642ef983 2906 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2907 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2908 req_length = REQUEST_ENTRY_CNT_82XX;
2909 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2910 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2911 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2912 ha->gid_list_info_size = 8;
2913 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2914 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2915 ha->isp_ops = &qla82xx_isp_ops;
2916 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2917 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2918 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2919 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2920 } else if (IS_QLA8044(ha)) {
2921 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2922 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2923 req_length = REQUEST_ENTRY_CNT_82XX;
2924 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2925 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2926 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2927 ha->gid_list_info_size = 8;
2928 ha->optrom_size = OPTROM_SIZE_83XX;
2929 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2930 ha->isp_ops = &qla8044_isp_ops;
2931 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2932 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2933 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2934 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2935 } else if (IS_QLA83XX(ha)) {
7d613ac6 2936 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2937 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2938 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2939 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2940 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2941 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2942 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2943 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2944 ha->gid_list_info_size = 8;
2945 ha->optrom_size = OPTROM_SIZE_83XX;
2946 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2947 ha->isp_ops = &qla83xx_isp_ops;
2948 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2949 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2950 ha->nvram_conf_off = ~0;
2951 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2952 } else if (IS_QLAFX00(ha)) {
2953 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2954 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2955 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2956 req_length = REQUEST_ENTRY_CNT_FX00;
2957 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2958 ha->isp_ops = &qlafx00_isp_ops;
2959 ha->port_down_retry_count = 30; /* default value */
2960 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2961 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2962 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2963 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2964 ha->mr.host_info_resend = false;
2965 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2966 } else if (IS_QLA27XX(ha)) {
2967 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2968 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2969 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2970 req_length = REQUEST_ENTRY_CNT_83XX;
2971 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2972 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2973 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2974 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2975 ha->gid_list_info_size = 8;
2976 ha->optrom_size = OPTROM_SIZE_83XX;
2977 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2978 ha->isp_ops = &qla27xx_isp_ops;
2979 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2980 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2981 ha->nvram_conf_off = ~0;
2982 ha->nvram_data_off = ~0;
1da177e4 2983 }
6246b8a1 2984
7c3df132
SK		 2985 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2986 "mbx_count=%d, req_length=%d, "
2987 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2988 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2989 "max_fibre_devices=%d.\n",
7c3df132
SK		 2990 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2991 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2992 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2993 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2994 "isp_ops=%p, flash_conf_off=%d, "
2995 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2996 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2997 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2998
2999 /* Configure PCI I/O space */
3000 ret = ha->isp_ops->iospace_config(ha);
3001 if (ret)
0a63ad12 3002 goto iospace_config_failed;
706f457d
GM		 3003
3004 ql_log_pci(ql_log_info, pdev, 0x001d,
3005 "Found an ISP%04X irq %d iobase 0x%p.\n",
3006 pdev->device, pdev->irq, ha->iobase);
6c2f527c 3007 mutex_init(&ha->vport_lock);
d7459527 3008 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 3009 init_completion(&ha->mbx_cmd_comp);
3010 complete(&ha->mbx_cmd_comp);
3011 init_completion(&ha->mbx_intr_comp);
23f2ebd1 3012 init_completion(&ha->dcbx_comp);
f356bef1 3013 init_completion(&ha->lb_portup_comp);
1da177e4 3014
2c3dfe3f 3015 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 3016
53303c42 3017 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 3018 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3019 "64 Bit addressing is %s.\n",
3020 ha->flags.enable_64bit_addressing ? "enable" :
3021 "disable");
73208dfd 3022 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 3023 if (ret) {
7c3df132
SK		 3024 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3025 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 3026
e315cd28
AC		 3027 goto probe_hw_failed;
3028 }
3029
73208dfd 3030 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 3031 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3032 req->max_q_depth = ql2xmaxqdepth;
3033
e315cd28
AC		 3034
3035 base_vha = qla2x00_create_host(sht, ha);
3036 if (!base_vha) {
a1541d5a 3037 ret = -ENOMEM;
6e9f21f3 3038 qla2x00_mem_free(ha);
2afa19a9
AC		 3039 qla2x00_free_req_que(ha, req);
3040 qla2x00_free_rsp_que(ha, rsp);
e315cd28 3041 goto probe_hw_failed;
1da177e4
LT		 3042 }
3043
e315cd28 3044 pci_set_drvdata(pdev, base_vha);
6b383979 3045 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3046
e315cd28 3047 host = base_vha->host;
2afa19a9 3048 base_vha->req = req;
73208dfd 3049 if (IS_QLA2XXX_MIDTYPE(ha))
1429f044 3050 base_vha->mgmt_svr_loop_id = NPH_MGMT_SERVER;
73208dfd 3051 else
e315cd28
AC		 3052 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3053 base_vha->vp_idx;
58548cb5 3054
8ae6d9c7
GM		 3055 /* Setup fcport template structure. */
3056 ha->mr.fcport.vha = base_vha;
3057 ha->mr.fcport.port_type = FCT_UNKNOWN;
3058 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3059 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3060 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3061 ha->mr.fcport.scan_state = 1;
3062
58548cb5
GM		 3063 /* Set the SG table size based on ISP type */
3064 if (!IS_FWI2_CAPABLE(ha)) {
3065 if (IS_QLA2100(ha))
3066 host->sg_tablesize = 32;
3067 } else {
3068 if (!IS_QLA82XX(ha))
3069 host->sg_tablesize = QLA_SG_ALL;
3070 }
642ef983 3071 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3072 host->cmd_per_lun = 3;
3073 host->unique_id = host->host_no;
e02587d7 3074 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3075 host->max_cmd_len = 32;
3076 else
3077 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3078 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3079 /* Older HBAs support only 16-bit LUNs */
3080 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3081 ql2xmaxlun > 0xffff)
3082 host->max_lun = 0xffff;
3083 else
3084 host->max_lun = ql2xmaxlun;
e315cd28 3085 host->transportt = qla2xxx_transport_template;
9a069e19 3086 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3087
7c3df132
SK		 3088 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3089 "max_id=%d this_id=%d "
3090 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3091 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3092 host->this_id, host->cmd_per_lun, host->unique_id,
3093 host->max_cmd_len, host->max_channel, host->max_lun,
3094 host->transportt, sht->vendor_id);
3095
1010f21e
HM		 3096 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3097
d7459527
MH		 3098 /* Set up the irqs */
3099 ret = qla2x00_request_irqs(ha, rsp);
3100 if (ret)
3101 goto probe_init_failed;
3102
9a347ff4
CD		 3103 /* Alloc arrays of request and response ring ptrs */
3104 if (!qla2x00_alloc_queues(ha, req, rsp)) {
3105 ql_log(ql_log_fatal, base_vha, 0x003d,
3106 "Failed to allocate memory for queue pointers..."
3107 "aborting.\n");
3108 goto probe_init_failed;
3109 }
3110
5601236b
MH		 3111 if (ha->mqenable && shost_use_blk_mq(host)) {
3112 /* number of hardware queues supported by blk/scsi-mq*/
3113 host->nr_hw_queues = ha->max_qpairs;
3114
3115 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3116 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
c38d1baf
HM		 3117 } else {
3118 if (ql2xnvmeenable) {
3119 host->nr_hw_queues = ha->max_qpairs;
3120 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3121 "FC-NVMe support is enabled, HW queues=%d\n",
3122 host->nr_hw_queues);
3123 } else {
3124 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3125 "blk/scsi-mq disabled.\n");
3126 }
3127 }
5601236b 3128
2d70c103 3129 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3130
90a86fc0
JC		 3131 pci_save_state(pdev);
3132
9a347ff4 3133 /* Assign back pointers */
2afa19a9
AC		 3134 rsp->req = req;
3135 req->rsp = rsp;
9a347ff4 3136
8ae6d9c7
GM		 3137 if (IS_QLAFX00(ha)) {
3138 ha->rsp_q_map[0] = rsp;
3139 ha->req_q_map[0] = req;
3140 set_bit(0, ha->req_qid_map);
3141 set_bit(0, ha->rsp_qid_map);
3142 }
3143
08029990
AV		 3144 /* FWI2-capable only. */
3145 req->req_q_in = &ha->iobase->isp24.req_q_in;
3146 req->req_q_out = &ha->iobase->isp24.req_q_out;
3147 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3148 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 3149 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 3150 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3151 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3152 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3153 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3154 }
3155
8ae6d9c7
GM		 3156 if (IS_QLAFX00(ha)) {
3157 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3158 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3159 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3160 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3161 }
3162
7ec0effd 3163 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3164 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3165 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3166 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3167 }
3168
7c3df132
SK		 3169 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3170 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3171 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3172 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3173 "req->req_q_in=%p req->req_q_out=%p "
3174 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3175 req->req_q_in, req->req_q_out,
3176 rsp->rsp_q_in, rsp->rsp_q_out);
3177 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3178 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3179 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3180 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3181 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3182 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3183
8ae6d9c7 3184 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3185 ql_log(ql_log_fatal, base_vha, 0x00d6,
3186 "Failed to initialize adapter - Adapter flags %x.\n",
3187 base_vha->device_flags);
1da177e4 3188
a9083016
GM		 3189 if (IS_QLA82XX(ha)) {
3190 qla82xx_idc_lock(ha);
3191 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3192 QLA8XXX_DEV_FAILED);
a9083016 3193 qla82xx_idc_unlock(ha);
7c3df132
SK		 3194 ql_log(ql_log_fatal, base_vha, 0x00d7,
3195 "HW State: FAILED.\n");
7ec0effd
AD		 3196 } else if (IS_QLA8044(ha)) {
3197 qla8044_idc_lock(ha);
3198 qla8044_wr_direct(base_vha,
3199 QLA8044_CRB_DEV_STATE_INDEX,
3200 QLA8XXX_DEV_FAILED);
3201 qla8044_idc_unlock(ha);
3202 ql_log(ql_log_fatal, base_vha, 0x0150,
3203 "HW State: FAILED.\n");
a9083016
GM		 3204 }
3205
a1541d5a 3206 ret = -ENODEV;
1da177e4
LT		 3207 goto probe_failed;
3208 }
3209
3b1bef64
CD		 3210 if (IS_QLAFX00(ha))
3211 host->can_queue = QLAFX00_MAX_CANQUEUE;
3212 else
3213 host->can_queue = req->num_outstanding_cmds - 10;
3214
3215 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3216 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3217 host->can_queue, base_vha->req,
3218 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3219
9b3e0f4d 3220 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
a01c77d2 3221
e326d22a
QT		 3222 if (ha->mqenable) {
3223 bool mq = false;
3224 bool startit = false;
e326d22a
QT		 3225
3226 if (QLA_TGT_MODE_ENABLED()) {
3227 mq = true;
3228 startit = false;
3229 }
3230
3231 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) &&
3232 shost_use_blk_mq(host)) {
3233 mq = true;
3234 startit = true;
3235 }
3236
3237 if (mq) {
3238 /* Create start of day qpairs for Block MQ */
5601236b 3239 for (i = 0; i < ha->max_qpairs; i++)
e326d22a 3240 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b
MH		 3241 }
3242 }
68ca949c 3243
cbc8eb67
AV		 3244 if (ha->flags.running_gold_fw)
3245 goto skip_dpc;
3246
1da177e4
LT		 3247 /*
3248 * Startup the kernel thread for this host adapter
3249 */
39a11240 3250 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3251 "%s_dpc", base_vha->host_str);
39a11240 3252 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3253 ql_log(ql_log_fatal, base_vha, 0x00ed,
3254 "Failed to start DPC thread.\n");
39a11240 3255 ret = PTR_ERR(ha->dpc_thread);
e2532b4a 3256 ha->dpc_thread = NULL;
1da177e4
LT		 3257 goto probe_failed;
3258 }
7c3df132
SK		 3259 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3260 "DPC thread started successfully.\n");
1da177e4 3261
2d70c103
NB		 3262 /*
3263 * If we're not coming up in initiator mode, we might sit for
3264 * a while without waking up the dpc thread, which leads to a
3265 * stuck process warning. So just kick the dpc once here and
3266 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3267 */
3268 qla2xxx_wake_dpc(base_vha);
3269
f3ddac19
CD		 3270 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3271
81178772
SK		 3272 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3273 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3274 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3275 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3276
3277 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3278 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3279 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3280 INIT_WORK(&ha->idc_state_handler,
3281 qla83xx_idc_state_handler_work);
3282 INIT_WORK(&ha->nic_core_unrecoverable,
3283 qla83xx_nic_core_unrecoverable_work);
3284 }
3285
cbc8eb67 3286skip_dpc:
e315cd28
AC		 3287 list_add_tail(&base_vha->list, &ha->vp_list);
3288 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3289
3290 /* Initialized the timer */
8e5f4ba0 3291 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3292 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3293 "Started qla2x00_timer with "
3294 "interval=%d.\n", WATCH_INTERVAL);
3295 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3296 "Detected hba at address=%p.\n",
3297 ha);
d19044c3 3298
e02587d7 3299 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3300 if (ha->fw_attributes & BIT_4) {
9e522cd8 3301 int prot = 0, guard;
bad75002 3302 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3303 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3304 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3305 if (ql2xenabledif == 1)
3306 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3307 scsi_host_set_prot(host,
8cb2049c 3308 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3309 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3310 | SHOST_DIF_TYPE3_PROTECTION
3311 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3312 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3313 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3314
3315 guard = SHOST_DIX_GUARD_CRC;
3316
3317 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3318 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3319 guard |= SHOST_DIX_GUARD_IP;
3320
3321 scsi_host_set_guard(host, guard);
bad75002
AE		 3322 } else
3323 base_vha->flags.difdix_supported = 0;
3324 }
3325
a9083016
GM		 3326 ha->isp_ops->enable_intrs(ha);
3327
1fe19ee4
AB		 3328 if (IS_QLAFX00(ha)) {
3329 ret = qlafx00_fx_disc(base_vha,
3330 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3331 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3332 QLA_SG_ALL : 128;
3333 }
3334
a1541d5a
AV		 3335 ret = scsi_add_host(host, &pdev->dev);
3336 if (ret)
3337 goto probe_failed;
3338
1486400f
MR		 3339 base_vha->flags.init_done = 1;
3340 base_vha->flags.online = 1;
edaa5c74 3341 ha->prev_minidump_failed = 0;
1486400f 3342
7c3df132
SK		 3343 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3344 "Init done and hba is online.\n");
3345
726b8548
QT		 3346 if (qla_ini_mode_enabled(base_vha) ||
3347 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3348 scsi_scan_host(host);
3349 else
3350 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3351 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3352
e315cd28 3353 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3354
8ae6d9c7 3355 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3356 ret = qlafx00_fx_disc(base_vha,
3357 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3358
3359 /* Register system information */
3360 ret = qlafx00_fx_disc(base_vha,
3361 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3362 }
3363
e315cd28 3364 qla2x00_init_host_attr(base_vha);
a1541d5a 3365
e315cd28 3366 qla2x00_dfs_setup(base_vha);
df613b96 3367
03eb912a
AB		 3368 ql_log(ql_log_info, base_vha, 0x00fb,
3369 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3370 ql_log(ql_log_info, base_vha, 0x00fc,
3371 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3372 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3373 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3374 base_vha->host_no,
df57caba 3375 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3376
2d70c103
NB		 3377 qlt_add_target(ha, base_vha);
3378
6b383979 3379 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3380
3381 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3382 return -ENODEV;
3383
e4e3a2ce
QT		 3384 if (ha->flags.detected_lr_sfp) {
3385 ql_log(ql_log_info, base_vha, 0xffff,
3386 "Reset chip to pick up LR SFP setting\n");
3387 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3388 qla2xxx_wake_dpc(base_vha);
3389 }
3390
1da177e4
LT		 3391 return 0;
3392
6e9f21f3 3393probe_init_failed:
2afa19a9 3394 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3395 ha->req_q_map[0] = NULL;
3396 clear_bit(0, ha->req_qid_map);
2afa19a9 3397 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3398 ha->rsp_q_map[0] = NULL;
3399 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3400 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3401
1da177e4 3402probe_failed:
b9978769
AV		 3403 if (base_vha->timer_active)
3404 qla2x00_stop_timer(base_vha);
3405 base_vha->flags.online = 0;
3406 if (ha->dpc_thread) {
3407 struct task_struct *t = ha->dpc_thread;
3408
3409 ha->dpc_thread = NULL;
3410 kthread_stop(t);
3411 }
3412
e315cd28 3413 qla2x00_free_device(base_vha);
1da177e4 3414
e315cd28 3415 scsi_host_put(base_vha->host);
1da177e4 3416
e315cd28 3417probe_hw_failed:
1a2fbf18
JL		 3418 qla2x00_clear_drv_active(ha);
3419
0a63ad12 3420iospace_config_failed:
7ec0effd 3421 if (IS_P3P_TYPE(ha)) {
0a63ad12 3422 if (!ha->nx_pcibase)
f73cb695 3423 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3424 if (!ql2xdbwr)
f73cb695 3425 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3426 } else {
3427 if (ha->iobase)
3428 iounmap(ha->iobase);
8ae6d9c7
GM		 3429 if (ha->cregbase)
3430 iounmap(ha->cregbase);
a9083016 3431 }
e315cd28
AC		 3432 pci_release_selected_regions(ha->pdev, ha->bars);
3433 kfree(ha);
1da177e4 3434
ddff7ed4 3435disable_device:
e315cd28 3436 pci_disable_device(pdev);
a1541d5a 3437 return ret;
1da177e4 3438}
1da177e4 3439
e30d1756
MI		 3440static void
3441qla2x00_shutdown(struct pci_dev *pdev)
3442{
3443 scsi_qla_host_t *vha;
3444 struct qla_hw_data *ha;
3445
3446 vha = pci_get_drvdata(pdev);
3447 ha = vha->hw;
3448
efdb5760
SC		 3449 ql_log(ql_log_info, vha, 0xfffa,
3450 "Adapter shutdown\n");
3451
3452 /*
3453 * Prevent future board_disable and wait
3454 * until any pending board_disable has completed.
3455 */
3456 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3457 cancel_work_sync(&ha->board_disable);
3458
3459 if (!atomic_read(&pdev->enable_cnt))
3460 return;
3461
42479343
AB		 3462 /* Notify ISPFX00 firmware */
3463 if (IS_QLAFX00(ha))
3464 qlafx00_driver_shutdown(vha, 20);
3465
e30d1756
MI		 3466 /* Turn-off FCE trace */
3467 if (ha->flags.fce_enabled) {
3468 qla2x00_disable_fce_trace(vha, NULL, NULL);
3469 ha->flags.fce_enabled = 0;
3470 }
3471
3472 /* Turn-off EFT trace */
3473 if (ha->eft)
3474 qla2x00_disable_eft_trace(vha);
3475
3407fc37
QT		 3476 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3477 if (ha->flags.fw_started)
3478 qla2x00_abort_isp_cleanup(vha);
3479 } else {
3480 /* Stop currently executing firmware. */
3481 qla2x00_try_to_stop_firmware(vha);
3482 }
e30d1756
MI		 3483
3484 /* Turn adapter off line */
3485 vha->flags.online = 0;
3486
3487 /* turn-off interrupts on the card */
3488 if (ha->interrupts_on) {
3489 vha->flags.init_done = 0;
3490 ha->isp_ops->disable_intrs(ha);
3491 }
3492
3493 qla2x00_free_irqs(vha);
3494
3495 qla2x00_free_fw_dump(ha);
61d41f61 3496
61d41f61 3497 pci_disable_device(pdev);
efdb5760
SC		 3498 ql_log(ql_log_info, vha, 0xfffe,
3499 "Adapter shutdown successfully.\n");
e30d1756
MI		 3500}
3501
fe1b806f 3502/* Deletes all the virtual ports for a given ha */
4c993f76 3503static void
fe1b806f 3504qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3505{
fe1b806f 3506 scsi_qla_host_t *vha;
feafb7b1 3507 unsigned long flags;
e315cd28 3508
43ebf16d
AE		 3509 mutex_lock(&ha->vport_lock);
3510 while (ha->cur_vport_count) {
43ebf16d 3511 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3512
43ebf16d
AE		 3513 BUG_ON(base_vha->list.next == &ha->vp_list);
3514 /* This assumes first entry in ha->vp_list is always base vha */
3515 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3516 scsi_host_get(vha->host);
feafb7b1 3517
43ebf16d
AE		 3518 spin_unlock_irqrestore(&ha->vport_slock, flags);
3519 mutex_unlock(&ha->vport_lock);
3520
3521 fc_vport_terminate(vha->fc_vport);
3522 scsi_host_put(vha->host);
feafb7b1 3523
43ebf16d 3524 mutex_lock(&ha->vport_lock);
e315cd28 3525 }
43ebf16d 3526 mutex_unlock(&ha->vport_lock);
fe1b806f 3527}
1da177e4 3528
fe1b806f
CD		 3529/* Stops all deferred work threads */
3530static void
3531qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3532{
7d613ac6
SV		 3533 /* Cancel all work and destroy DPC workqueues */
3534 if (ha->dpc_lp_wq) {
3535 cancel_work_sync(&ha->idc_aen);
3536 destroy_workqueue(ha->dpc_lp_wq);
3537 ha->dpc_lp_wq = NULL;
3538 }
3539
3540 if (ha->dpc_hp_wq) {
3541 cancel_work_sync(&ha->nic_core_reset);
3542 cancel_work_sync(&ha->idc_state_handler);
3543 cancel_work_sync(&ha->nic_core_unrecoverable);
3544 destroy_workqueue(ha->dpc_hp_wq);
3545 ha->dpc_hp_wq = NULL;
3546 }
3547
b9978769
AV		 3548 /* Kill the kernel thread for this host */
3549 if (ha->dpc_thread) {
3550 struct task_struct *t = ha->dpc_thread;
3551
3552 /*
3553 * qla2xxx_wake_dpc checks for ->dpc_thread
3554 * so we need to zero it out.
3555 */
3556 ha->dpc_thread = NULL;
3557 kthread_stop(t);
3558 }
fe1b806f 3559}
1da177e4 3560
fe1b806f
CD		 3561static void
3562qla2x00_unmap_iobases(struct qla_hw_data *ha)
3563{
a9083016 3564 if (IS_QLA82XX(ha)) {
b963752f 3565
f73cb695 3566 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3567 if (!ql2xdbwr)
f73cb695 3568 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3569 } else {
3570 if (ha->iobase)
3571 iounmap(ha->iobase);
1da177e4 3572
8ae6d9c7
GM		 3573 if (ha->cregbase)
3574 iounmap(ha->cregbase);
3575
a9083016
GM		 3576 if (ha->mqiobase)
3577 iounmap(ha->mqiobase);
6246b8a1 3578
f73cb695 3579 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3580 iounmap(ha->msixbase);
a9083016 3581 }
fe1b806f
CD		 3582}
3583
3584static void
db7157d4 3585qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3586{
fe1b806f
CD		 3587 if (IS_QLA8044(ha)) {
3588 qla8044_idc_lock(ha);
c41afc9a 3589 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3590 qla8044_idc_unlock(ha);
3591 } else if (IS_QLA82XX(ha)) {
3592 qla82xx_idc_lock(ha);
3593 qla82xx_clear_drv_active(ha);
3594 qla82xx_idc_unlock(ha);
3595 }
3596}
3597
3598static void
3599qla2x00_remove_one(struct pci_dev *pdev)
3600{
3601 scsi_qla_host_t *base_vha;
3602 struct qla_hw_data *ha;
3603
beb9e315
JL		 3604 base_vha = pci_get_drvdata(pdev);
3605 ha = base_vha->hw;
3606
3607 /* Indicate device removal to prevent future board_disable and wait
3608 * until any pending board_disable has completed. */
3609 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3610 cancel_work_sync(&ha->board_disable);
3611
fe1b806f 3612 /*
beb9e315
JL		 3613 * If the PCI device is disabled then there was a PCI-disconnect and
3614 * qla2x00_disable_board_on_pci_error has taken care of most of the
3615 * resources.
fe1b806f 3616 */
beb9e315 3617 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3618 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3619 base_vha->gnl.l, base_vha->gnl.ldma);
3620
beb9e315
JL		 3621 scsi_host_put(base_vha->host);
3622 kfree(ha);
3623 pci_set_drvdata(pdev, NULL);
fe1b806f 3624 return;
beb9e315 3625 }
638a1a01
SC		 3626 qla2x00_wait_for_hba_ready(base_vha);
3627
726b8548
QT		 3628 /*
3629 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3630 * where it was set first.
3631 */
3632 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3633 return;
3634
fe1b806f 3635 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3636
3637 qla_nvme_delete(base_vha);
3638
726b8548
QT		 3639 dma_free_coherent(&ha->pdev->dev,
3640 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f 3641
a4239945
QT		 3642 vfree(base_vha->scan.l);
3643
fe1b806f
CD		 3644 if (IS_QLAFX00(ha))
3645 qlafx00_driver_shutdown(base_vha, 20);
3646
3647 qla2x00_delete_all_vps(ha, base_vha);
3648
3649 if (IS_QLA8031(ha)) {
3650 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3651 "Clearing fcoe driver presence.\n");
3652 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3653 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3654 "Error while clearing DRV-Presence.\n");
3655 }
3656
3657 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3658
3659 qla2x00_dfs_remove(base_vha);
3660
3661 qla84xx_put_chip(base_vha);
3662
3663 /* Disable timer */
3664 if (base_vha->timer_active)
3665 qla2x00_stop_timer(base_vha);
3666
3667 base_vha->flags.online = 0;
3668
b0d6cabd
HM		 3669 /* free DMA memory */
3670 if (ha->exlogin_buf)
3671 qla2x00_free_exlogin_buffer(ha);
3672
2f56a7f1
HM		 3673 /* free DMA memory */
3674 if (ha->exchoffld_buf)
3675 qla2x00_free_exchoffld_buffer(ha);
3676
fe1b806f
CD		 3677 qla2x00_destroy_deferred_work(ha);
3678
3679 qlt_remove_target(ha, base_vha);
3680
3681 qla2x00_free_sysfs_attr(base_vha, true);
3682
3683 fc_remove_host(base_vha->host);
482c9dc7 3684 qlt_remove_target_resources(ha);
fe1b806f
CD		 3685
3686 scsi_remove_host(base_vha->host);
3687
3688 qla2x00_free_device(base_vha);
3689
db7157d4 3690 qla2x00_clear_drv_active(ha);
fe1b806f 3691
d2749ffa
AE		 3692 scsi_host_put(base_vha->host);
3693
fe1b806f 3694 qla2x00_unmap_iobases(ha);
73208dfd 3695
e315cd28
AC		 3696 pci_release_selected_regions(ha->pdev, ha->bars);
3697 kfree(ha);
1da177e4 3698
90a86fc0
JC		 3699 pci_disable_pcie_error_reporting(pdev);
3700
665db93b 3701 pci_disable_device(pdev);
1da177e4 3702}
1da177e4
LT		 3703
3704static void
e315cd28 3705qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3706{
e315cd28 3707 struct qla_hw_data *ha = vha->hw;
1da177e4 3708
85880801
AV		 3709 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3710
3711 /* Disable timer */
3712 if (vha->timer_active)
3713 qla2x00_stop_timer(vha);
3714
2afa19a9 3715 qla25xx_delete_queues(vha);
fe1b806f 3716
df613b96 3717 if (ha->flags.fce_enabled)
e315cd28 3718 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3719
a7a167bf 3720 if (ha->eft)
e315cd28 3721 qla2x00_disable_eft_trace(vha);
a7a167bf 3722
3407fc37
QT		 3723 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3724 if (ha->flags.fw_started)
3725 qla2x00_abort_isp_cleanup(vha);
3726 } else {
3727 if (ha->flags.fw_started) {
3728 /* Stop currently executing firmware. */
3729 qla2x00_try_to_stop_firmware(vha);
3730 ha->flags.fw_started = 0;
3731 }
3732 }
1da177e4 3733
85880801
AV		 3734 vha->flags.online = 0;
3735
f6ef3b18 3736 /* turn-off interrupts on the card */
a9083016
GM		 3737 if (ha->interrupts_on) {
3738 vha->flags.init_done = 0;
fd34f556 3739 ha->isp_ops->disable_intrs(ha);
a9083016 3740 }
f6ef3b18 3741
093df737
QT		 3742 qla2x00_free_fcports(vha);
3743
e315cd28 3744 qla2x00_free_irqs(vha);
1da177e4 3745
093df737
QT		 3746 /* Flush the work queue and remove it */
3747 if (ha->wq) {
3748 flush_workqueue(ha->wq);
3749 destroy_workqueue(ha->wq);
3750 ha->wq = NULL;
3751 }
3752
8867048b 3753
e315cd28 3754 qla2x00_mem_free(ha);
73208dfd 3755
08de2844
GM		 3756 qla82xx_md_free(vha);
3757
73208dfd 3758 qla2x00_free_queues(ha);
1da177e4
LT		 3759}
3760
8867048b
CD		 3761void qla2x00_free_fcports(struct scsi_qla_host *vha)
3762{
3763 fc_port_t *fcport, *tfcport;
3764
3765 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3766 list_del(&fcport->list);
5f16b331 3767 qla2x00_clear_loop_id(fcport);
8867048b 3768 kfree(fcport);
8867048b
CD		 3769 }
3770}
3771
d97994dc 3772static inline void
e315cd28 3773qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3774 int defer)
3775{
d97994dc 3776 struct fc_rport *rport;
67becc00 3777 scsi_qla_host_t *base_vha;
044d78e1 3778 unsigned long flags;
d97994dc 3779
3780 if (!fcport->rport)
3781 return;
3782
3783 rport = fcport->rport;
3784 if (defer) {
67becc00 3785 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3786 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3787 fcport->drport = rport;
044d78e1 3788 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3789 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3790 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3791 qla2xxx_wake_dpc(base_vha);
2d70c103 3792 } else {
df673274 3793 int now;
726b8548 3794 if (rport) {
83548fe2
QT		 3795 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3796 "%s %8phN. rport %p roles %x\n",
3797 __func__, fcport->port_name, rport,
3798 rport->roles);
d20ed91b 3799 fc_remote_port_delete(rport);
726b8548 3800 }
df673274 3801 qlt_do_generation_tick(vha, &now);
2d70c103 3802 }
d97994dc 3803}
3804
1da177e4
LT		 3805/*
3806 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3807 *
3808 * Input: ha = adapter block pointer. fcport = port structure pointer.
3809 *
3810 * Return: None.
3811 *
3812 * Context:
3813 */
e315cd28 3814void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3815 int do_login, int defer)
1da177e4 3816{
8ae6d9c7
GM		 3817 if (IS_QLAFX00(vha->hw)) {
3818 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3819 qla2x00_schedule_rport_del(vha, fcport, defer);
3820 return;
3821 }
3822
2c3dfe3f 3823 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3824 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3825 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3826 qla2x00_schedule_rport_del(vha, fcport, defer);
3827 }
fa2a1ce5 3828 /*
1da177e4
LT		 3829 * We may need to retry the login, so don't change the state of the
3830 * port but do the retries.
3831 */
3832 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3833 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3834
3835 if (!do_login)
3836 return;
3837
a1d0285e
AE		 3838 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3839
1da177e4 3840 if (fcport->login_retry == 0) {
e315cd28 3841 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3842
83548fe2 3843 ql_dbg(ql_dbg_disc, vha, 0x20a3,
726b8548 3844 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
7b833558 3845 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3846 }
3847}
3848
3849/*
3850 * qla2x00_mark_all_devices_lost
3851 * Updates fcport state when device goes offline.
3852 *
3853 * Input:
3854 * ha = adapter block pointer.
3855 * fcport = port structure pointer.
3856 *
3857 * Return:
3858 * None.
3859 *
3860 * Context:
3861 */
3862void
e315cd28 3863qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3864{
3865 fc_port_t *fcport;
3866
83548fe2
QT		 3867 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3868 "Mark all dev lost\n");
726b8548 3869
e315cd28 3870 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548 3871 fcport->scan_state = 0;
d8630bb9 3872 qlt_schedule_sess_for_deletion(fcport);
726b8548 3873
c6d39e23 3874 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3875 continue;
0d6e61bc 3876
1da177e4
LT		 3877 /*
3878 * No point in marking the device as lost, if the device is
3879 * already DEAD.
3880 */
3881 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3882 continue;
e315cd28 3883 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3884 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3885 if (defer)
3886 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3887 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3888 qla2x00_schedule_rport_del(vha, fcport, defer);
3889 }
1da177e4
LT		 3890 }
3891}
3892
3893/*
3894* qla2x00_mem_alloc
3895* Allocates adapter memory.
3896*
3897* Returns:
3898* 0 = success.
e8711085 3899* !0 = failure.
1da177e4 3900*/
e8711085 3901static int
73208dfd
AC		 3902qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3903 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3904{
3905 char name[16];
1da177e4 3906
e8711085 3907 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3908 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3909 if (!ha->init_cb)
e315cd28 3910 goto fail;
e8711085 3911
2d70c103
NB		 3912 if (qlt_mem_alloc(ha) < 0)
3913 goto fail_free_init_cb;
3914
642ef983
CD		 3915 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3916 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3917 if (!ha->gid_list)
2d70c103 3918 goto fail_free_tgt_mem;
1da177e4 3919
e8711085
AV		 3920 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3921 if (!ha->srb_mempool)
e315cd28 3922 goto fail_free_gid_list;
e8711085 3923
7ec0effd 3924 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3925 /* Allocate cache for CT6 Ctx. */
3926 if (!ctx_cachep) {
3927 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3928 sizeof(struct ct6_dsd), 0,
3929 SLAB_HWCACHE_ALIGN, NULL);
3930 if (!ctx_cachep)
fc1ffd6c 3931 goto fail_free_srb_mempool;
a9083016
GM		 3932 }
3933 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3934 ctx_cachep);
3935 if (!ha->ctx_mempool)
3936 goto fail_free_srb_mempool;
7c3df132
SK		 3937 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3938 "ctx_cachep=%p ctx_mempool=%p.\n",
3939 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3940 }
3941
e8711085
AV		 3942 /* Get memory for cached NVRAM */
3943 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3944 if (!ha->nvram)
a9083016 3945 goto fail_free_ctx_mempool;
e8711085 3946
e315cd28
AC		 3947 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3948 ha->pdev->device);
3949 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3950 DMA_POOL_SIZE, 8, 0);
3951 if (!ha->s_dma_pool)
3952 goto fail_free_nvram;
3953
7c3df132
SK		 3954 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3955 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3956 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3957
7ec0effd 3958 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3959 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3960 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3961 if (!ha->dl_dma_pool) {
7c3df132
SK		 3962 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3963 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3964 goto fail_s_dma_pool;
3965 }
3966
3967 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3968 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3969 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3970 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3971 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3972 goto fail_dl_dma_pool;
3973 }
7c3df132
SK		 3974 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3975 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3976 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3977 }
3978
e8711085
AV		 3979 /* Allocate memory for SNS commands */
3980 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3981 /* Get consistent memory allocated for SNS commands */
e8711085 3982 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3983 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3984 if (!ha->sns_cmd)
e315cd28 3985 goto fail_dma_pool;
7c3df132 3986 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3987 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3988 } else {
e315cd28 3989 /* Get consistent memory allocated for MS IOCB */
e8711085 3990 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3991 &ha->ms_iocb_dma);
e8711085 3992 if (!ha->ms_iocb)
e315cd28
AC		 3993 goto fail_dma_pool;
3994 /* Get consistent memory allocated for CT SNS commands */
e8711085 3995 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3996 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3997 if (!ha->ct_sns)
3998 goto fail_free_ms_iocb;
7c3df132
SK		 3999 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4000 "ms_iocb=%p ct_sns=%p.\n",
4001 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 4002 }
4003
e315cd28 4004 /* Allocate memory for request ring */
73208dfd
AC		 4005 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4006 if (!*req) {
7c3df132
SK		 4007 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4008 "Failed to allocate memory for req.\n");
e315cd28
AC		 4009 goto fail_req;
4010 }
73208dfd
AC		 4011 (*req)->length = req_len;
4012 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4013 ((*req)->length + 1) * sizeof(request_t),
4014 &(*req)->dma, GFP_KERNEL);
4015 if (!(*req)->ring) {
7c3df132
SK		 4016 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4017 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 4018 goto fail_req_ring;
4019 }
4020 /* Allocate memory for response ring */
73208dfd
AC		 4021 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4022 if (!*rsp) {
7c3df132
SK		 4023 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4024 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 4025 goto fail_rsp;
4026 }
73208dfd
AC		 4027 (*rsp)->hw = ha;
4028 (*rsp)->length = rsp_len;
4029 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4030 ((*rsp)->length + 1) * sizeof(response_t),
4031 &(*rsp)->dma, GFP_KERNEL);
4032 if (!(*rsp)->ring) {
7c3df132
SK		 4033 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4034 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 4035 goto fail_rsp_ring;
4036 }
73208dfd
AC		 4037 (*req)->rsp = *rsp;
4038 (*rsp)->req = *req;
7c3df132
SK		 4039 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4040 "req=%p req->length=%d req->ring=%p rsp=%p "
4041 "rsp->length=%d rsp->ring=%p.\n",
4042 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4043 (*rsp)->ring);
73208dfd
AC		 4044 /* Allocate memory for NVRAM data for vports */
4045 if (ha->nvram_npiv_size) {
4046 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 4047 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 4048 if (!ha->npiv_info) {
7c3df132
SK		 4049 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4050 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 4051 goto fail_npiv_info;
4052 }
4053 } else
4054 ha->npiv_info = NULL;
e8711085 4055
b64b0e8f 4056 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 4057 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 4058 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4059 &ha->ex_init_cb_dma);
4060 if (!ha->ex_init_cb)
4061 goto fail_ex_init_cb;
7c3df132
SK		 4062 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4063 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4064 }
4065
a9083016
GM		 4066 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4067
5ff1d584
AV		 4068 /* Get consistent memory allocated for Async Port-Database. */
4069 if (!IS_FWI2_CAPABLE(ha)) {
4070 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4071 &ha->async_pd_dma);
4072 if (!ha->async_pd)
4073 goto fail_async_pd;
7c3df132
SK		 4074 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4075 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4076 }
4077
e315cd28 4078 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4079
4080 /* Allocate memory for our loop_id bitmap */
4081 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
4082 GFP_KERNEL);
4083 if (!ha->loop_id_map)
fc1ffd6c 4084 goto fail_loop_id_map;
5f16b331
CD		 4085 else {
4086 qla2x00_set_reserved_loop_ids(ha);
4087 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4088 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4089 }
4090
e4e3a2ce
QT		 4091 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4092 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4093 if (!ha->sfp_data) {
4094 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4095 "Unable to allocate memory for SFP read-data.\n");
4096 goto fail_sfp_data;
4097 }
4098
b2a72ec3 4099 return 0;
e315cd28 4100
e4e3a2ce
QT		 4101fail_sfp_data:
4102 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4103fail_loop_id_map:
4104 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4105fail_async_pd:
4106 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4107fail_ex_init_cb:
4108 kfree(ha->npiv_info);
73208dfd
AC		 4109fail_npiv_info:
4110 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4111 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4112 (*rsp)->ring = NULL;
4113 (*rsp)->dma = 0;
e315cd28 4114fail_rsp_ring:
73208dfd 4115 kfree(*rsp);
e315cd28 4116fail_rsp:
73208dfd
AC		 4117 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4118 sizeof(request_t), (*req)->ring, (*req)->dma);
4119 (*req)->ring = NULL;
4120 (*req)->dma = 0;
e315cd28 4121fail_req_ring:
73208dfd 4122 kfree(*req);
e315cd28
AC		 4123fail_req:
4124 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4125 ha->ct_sns, ha->ct_sns_dma);
4126 ha->ct_sns = NULL;
4127 ha->ct_sns_dma = 0;
e8711085
AV		 4128fail_free_ms_iocb:
4129 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4130 ha->ms_iocb = NULL;
4131 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4132
4133 if (ha->sns_cmd)
4134 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4135 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4136fail_dma_pool:
bad75002 4137 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4138 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4139 ha->fcp_cmnd_dma_pool = NULL;
4140 }
4141fail_dl_dma_pool:
bad75002 4142 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4143 dma_pool_destroy(ha->dl_dma_pool);
4144 ha->dl_dma_pool = NULL;
4145 }
4146fail_s_dma_pool:
e315cd28
AC		 4147 dma_pool_destroy(ha->s_dma_pool);
4148 ha->s_dma_pool = NULL;
e8711085
AV		 4149fail_free_nvram:
4150 kfree(ha->nvram);
4151 ha->nvram = NULL;
a9083016 4152fail_free_ctx_mempool:
fc1ffd6c
QT		 4153 if (ha->ctx_mempool)
4154 mempool_destroy(ha->ctx_mempool);
a9083016 4155 ha->ctx_mempool = NULL;
e8711085 4156fail_free_srb_mempool:
fc1ffd6c
QT		 4157 if (ha->srb_mempool)
4158 mempool_destroy(ha->srb_mempool);
e8711085 4159 ha->srb_mempool = NULL;
e8711085 4160fail_free_gid_list:
642ef983
CD		 4161 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4162 ha->gid_list,
e315cd28 4163 ha->gid_list_dma);
e8711085
AV		 4164 ha->gid_list = NULL;
4165 ha->gid_list_dma = 0;
2d70c103
NB		 4166fail_free_tgt_mem:
4167 qlt_mem_free(ha);
e315cd28
AC		 4168fail_free_init_cb:
4169 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4170 ha->init_cb_dma);
4171 ha->init_cb = NULL;
4172 ha->init_cb_dma = 0;
e8711085 4173fail:
7c3df132
SK		 4174 ql_log(ql_log_fatal, NULL, 0x0030,
4175 "Memory allocation failure.\n");
e8711085 4176 return -ENOMEM;
1da177e4
LT		 4177}
4178
b0d6cabd
HM		 4179int
4180qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4181{
4182 int rval;
4183 uint16_t size, max_cnt, temp;
4184 struct qla_hw_data *ha = vha->hw;
4185
4186 /* Return if we don't need to alloacate any extended logins */
4187 if (!ql2xexlogins)
4188 return QLA_SUCCESS;
4189
99e1b683
QT		 4190 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4191 return QLA_SUCCESS;
4192
b0d6cabd
HM		 4193 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4194 max_cnt = 0;
4195 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4196 if (rval != QLA_SUCCESS) {
4197 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4198 "Failed to get exlogin status.\n");
4199 return rval;
4200 }
4201
4202 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4203 temp *= size;
4204
4205 if (temp != ha->exlogin_size) {
4206 qla2x00_free_exlogin_buffer(ha);
4207 ha->exlogin_size = temp;
4208
4209 ql_log(ql_log_info, vha, 0xd024,
4210 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4211 max_cnt, size, temp);
4212
4213 ql_log(ql_log_info, vha, 0xd025,
4214 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4215
4216 /* Get consistent memory for extended logins */
4217 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4218 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4219 if (!ha->exlogin_buf) {
4220 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4221 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4222 return -ENOMEM;
4223 }
b0d6cabd
HM		 4224 }
4225
4226 /* Now configure the dma buffer */
4227 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4228 if (rval) {
83548fe2 4229 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4230 "Setup extended login buffer ****FAILED****.\n");
4231 qla2x00_free_exlogin_buffer(ha);
4232 }
4233
4234 return rval;
4235}
4236
4237/*
4238* qla2x00_free_exlogin_buffer
4239*
4240* Input:
4241* ha = adapter block pointer
4242*/
4243void
4244qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4245{
4246 if (ha->exlogin_buf) {
4247 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4248 ha->exlogin_buf, ha->exlogin_buf_dma);
4249 ha->exlogin_buf = NULL;
4250 ha->exlogin_size = 0;
4251 }
4252}
4253
99e1b683
QT		 4254static void
4255qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4256{
4257 u32 temp;
4258 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4259
d1e3635a
QT		 4260 if (max_cnt > vha->hw->max_exchg)
4261 max_cnt = vha->hw->max_exchg;
4262
99e1b683
QT		 4263 if (qla_ini_mode_enabled(vha)) {
4264 if (ql2xiniexchg > max_cnt)
4265 ql2xiniexchg = max_cnt;
4266
4267 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4268 *ret_cnt = ql2xiniexchg;
4269 } else if (qla_tgt_mode_enabled(vha)) {
4270 if (ql2xexchoffld > max_cnt)
4271 ql2xexchoffld = max_cnt;
4272
4273 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4274 *ret_cnt = ql2xexchoffld;
4275 } else if (qla_dual_mode_enabled(vha)) {
4276 temp = ql2xiniexchg + ql2xexchoffld;
4277 if (temp > max_cnt) {
4278 ql2xiniexchg -= (temp - max_cnt)/2;
4279 ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4280 temp = max_cnt;
4281 }
4282
4283 if (temp > FW_DEF_EXCHANGES_CNT)
4284 *ret_cnt = temp;
4285 }
4286}
4287
2f56a7f1
HM		 4288int
4289qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4290{
4291 int rval;
d1e3635a
QT		 4292 u16 size, max_cnt;
4293 u32 actual_cnt, totsz;
2f56a7f1
HM		 4294 struct qla_hw_data *ha = vha->hw;
4295
99e1b683
QT		 4296 if (!ha->flags.exchoffld_enabled)
4297 return QLA_SUCCESS;
4298
4299 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4300 return QLA_SUCCESS;
4301
2f56a7f1
HM		 4302 max_cnt = 0;
4303 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4304 if (rval != QLA_SUCCESS) {
4305 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4306 "Failed to get exlogin status.\n");
4307 return rval;
4308 }
4309
d1e3635a
QT		 4310 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4311 ql_log(ql_log_info, vha, 0xd014,
4312 "Actual exchange offload count: %d.\n", actual_cnt);
4313
4314 totsz = actual_cnt * size;
2f56a7f1 4315
d1e3635a 4316 if (totsz != ha->exchoffld_size) {
99e1b683 4317 qla2x00_free_exchoffld_buffer(ha);
d1e3635a 4318 ha->exchoffld_size = totsz;
99e1b683
QT		 4319
4320 ql_log(ql_log_info, vha, 0xd016,
d1e3635a
QT		 4321 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4322 max_cnt, actual_cnt, size, totsz);
99e1b683
QT		 4323
4324 ql_log(ql_log_info, vha, 0xd017,
4325 "Exchange Buffers requested size = 0x%x\n",
4326 ha->exchoffld_size);
4327
4328 /* Get consistent memory for extended logins */
4329 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4330 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4331 if (!ha->exchoffld_buf) {
4332 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
d1e3635a
QT		 4333 "Failed to allocate memory for Exchange Offload.\n");
4334
4335 if (ha->max_exchg >
4336 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4337 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4338 } else if (ha->max_exchg >
4339 (FW_DEF_EXCHANGES_CNT + 512)) {
4340 ha->max_exchg -= 512;
4341 } else {
4342 ha->flags.exchoffld_enabled = 0;
4343 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4344 "Disabling Exchange offload due to lack of memory\n");
4345 }
4346 ha->exchoffld_size = 0;
4347
99e1b683
QT		 4348 return -ENOMEM;
4349 }
2f56a7f1
HM		 4350 }
4351
4352 /* Now configure the dma buffer */
99e1b683 4353 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4354 if (rval) {
4355 ql_log(ql_log_fatal, vha, 0xd02e,
4356 "Setup exchange offload buffer ****FAILED****.\n");
4357 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4358 } else {
4359 /* re-adjust number of target exchange */
4360 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4361
4362 if (qla_ini_mode_enabled(vha))
4363 icb->exchange_count = 0;
4364 else
4365 icb->exchange_count = cpu_to_le16(ql2xexchoffld);
2f56a7f1
HM		 4366 }
4367
4368 return rval;
4369}
4370
4371/*
4372* qla2x00_free_exchoffld_buffer
4373*
4374* Input:
4375* ha = adapter block pointer
4376*/
4377void
4378qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4379{
4380 if (ha->exchoffld_buf) {
4381 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4382 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4383 ha->exchoffld_buf = NULL;
4384 ha->exchoffld_size = 0;
4385 }
4386}
4387
1da177e4 4388/*
e30d1756
MI		 4389* qla2x00_free_fw_dump
4390* Frees fw dump stuff.
1da177e4
LT		 4391*
4392* Input:
7ec0effd 4393* ha = adapter block pointer
1da177e4 4394*/
a824ebb3 4395static void
e30d1756 4396qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4397{
df613b96 4398 if (ha->fce)
f73cb695
CD		 4399 dma_free_coherent(&ha->pdev->dev,
4400 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4401
f73cb695
CD		 4402 if (ha->eft)
4403 dma_free_coherent(&ha->pdev->dev,
4404 EFT_SIZE, ha->eft, ha->eft_dma);
4405
4406 if (ha->fw_dump)
a7a167bf 4407 vfree(ha->fw_dump);
f73cb695
CD		 4408 if (ha->fw_dump_template)
4409 vfree(ha->fw_dump_template);
4410
e30d1756
MI		 4411 ha->fce = NULL;
4412 ha->fce_dma = 0;
4413 ha->eft = NULL;
4414 ha->eft_dma = 0;
e30d1756 4415 ha->fw_dumped = 0;
61f098dd 4416 ha->fw_dump_cap_flags = 0;
e30d1756 4417 ha->fw_dump_reading = 0;
f73cb695
CD		 4418 ha->fw_dump = NULL;
4419 ha->fw_dump_len = 0;
4420 ha->fw_dump_template = NULL;
4421 ha->fw_dump_template_len = 0;
e30d1756
MI		 4422}
4423
4424/*
4425* qla2x00_mem_free
4426* Frees all adapter allocated memory.
4427*
4428* Input:
4429* ha = adapter block pointer.
4430*/
4431static void
4432qla2x00_mem_free(struct qla_hw_data *ha)
4433{
4434 qla2x00_free_fw_dump(ha);
4435
81178772
SK		 4436 if (ha->mctp_dump)
4437 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4438 ha->mctp_dump_dma);
4439
e30d1756
MI		 4440 if (ha->srb_mempool)
4441 mempool_destroy(ha->srb_mempool);
a7a167bf 4442
11bbc1d8
AV		 4443 if (ha->dcbx_tlv)
4444 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4445 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4446
ce0423f4
AV		 4447 if (ha->xgmac_data)
4448 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4449 ha->xgmac_data, ha->xgmac_data_dma);
4450
1da177e4
LT		 4451 if (ha->sns_cmd)
4452 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4453 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4454
4455 if (ha->ct_sns)
4456 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4457 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4458
88729e53 4459 if (ha->sfp_data)
e4e3a2ce
QT		 4460 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4461 ha->sfp_data_dma);
88729e53 4462
1da177e4
LT		 4463 if (ha->ms_iocb)
4464 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4465
b64b0e8f 4466 if (ha->ex_init_cb)
a9083016
GM		 4467 dma_pool_free(ha->s_dma_pool,
4468 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4469
5ff1d584
AV		 4470 if (ha->async_pd)
4471 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4472
1da177e4
LT		 4473 if (ha->s_dma_pool)
4474 dma_pool_destroy(ha->s_dma_pool);
4475
1da177e4 4476 if (ha->gid_list)
642ef983
CD		 4477 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4478 ha->gid_list, ha->gid_list_dma);
1da177e4 4479
a9083016
GM		 4480 if (IS_QLA82XX(ha)) {
4481 if (!list_empty(&ha->gbl_dsd_list)) {
4482 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4483
4484 /* clean up allocated prev pool */
4485 list_for_each_entry_safe(dsd_ptr,
4486 tdsd_ptr, &ha->gbl_dsd_list, list) {
4487 dma_pool_free(ha->dl_dma_pool,
4488 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4489 list_del(&dsd_ptr->list);
4490 kfree(dsd_ptr);
4491 }
4492 }
4493 }
4494
4495 if (ha->dl_dma_pool)
4496 dma_pool_destroy(ha->dl_dma_pool);
4497
4498 if (ha->fcp_cmnd_dma_pool)
4499 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4500
4501 if (ha->ctx_mempool)
4502 mempool_destroy(ha->ctx_mempool);
4503
2d70c103
NB		 4504 qlt_mem_free(ha);
4505
e315cd28
AC		 4506 if (ha->init_cb)
4507 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4508 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4509 vfree(ha->optrom_buffer);
4510 kfree(ha->nvram);
73208dfd 4511 kfree(ha->npiv_info);
7a67735b 4512 kfree(ha->swl);
5f16b331 4513 kfree(ha->loop_id_map);
1da177e4 4514
e8711085 4515 ha->srb_mempool = NULL;
a9083016 4516 ha->ctx_mempool = NULL;
1da177e4
LT		 4517 ha->sns_cmd = NULL;
4518 ha->sns_cmd_dma = 0;
4519 ha->ct_sns = NULL;
4520 ha->ct_sns_dma = 0;
4521 ha->ms_iocb = NULL;
4522 ha->ms_iocb_dma = 0;
1da177e4
LT		 4523 ha->init_cb = NULL;
4524 ha->init_cb_dma = 0;
b64b0e8f
AV		 4525 ha->ex_init_cb = NULL;
4526 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4527 ha->async_pd = NULL;
4528 ha->async_pd_dma = 0;
1da177e4
LT		 4529
4530 ha->s_dma_pool = NULL;
a9083016
GM		 4531 ha->dl_dma_pool = NULL;
4532 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4533
1da177e4
LT		 4534 ha->gid_list = NULL;
4535 ha->gid_list_dma = 0;
2d70c103
NB		 4536
4537 ha->tgt.atio_ring = NULL;
4538 ha->tgt.atio_dma = 0;
4539 ha->tgt.tgt_vp_map = NULL;
e315cd28 4540}
1da177e4 4541
e315cd28
AC		 4542struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4543 struct qla_hw_data *ha)
4544{
4545 struct Scsi_Host *host;
4546 struct scsi_qla_host *vha = NULL;
854165f4 4547
e315cd28 4548 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4549 if (!host) {
7c3df132
SK		 4550 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4551 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4552 return NULL;
e315cd28
AC		 4553 }
4554
4555 /* Clear our data area */
4556 vha = shost_priv(host);
4557 memset(vha, 0, sizeof(scsi_qla_host_t));
4558
4559 vha->host = host;
4560 vha->host_no = host->host_no;
4561 vha->hw = ha;
4562
4563 INIT_LIST_HEAD(&vha->vp_fcports);
4564 INIT_LIST_HEAD(&vha->work_list);
4565 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4566 INIT_LIST_HEAD(&vha->qla_cmd_list);
4567 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4568 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4569 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4570 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4571 INIT_LIST_HEAD(&vha->gnl.fcports);
a5d42f4c 4572 INIT_LIST_HEAD(&vha->nvme_rport_list);
2d73ac61 4573 INIT_LIST_HEAD(&vha->gpnid_list);
9b3e0f4d 4574 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
e315cd28 4575
f999f4c1 4576 spin_lock_init(&vha->work_lock);
8b2f5ff3 4577 spin_lock_init(&vha->cmd_list_lock);
726b8548 4578 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4579 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4580
2fdbc65e
BVA		 4581 vha->gnl.size = sizeof(struct get_name_list_extended) *
4582 (ha->max_loop_id + 1);
41dc529a
QT		 4583 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4584 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4585 if (!vha->gnl.l) {
83548fe2 4586 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a
QT		 4587 "Alloc failed for name list.\n");
4588 scsi_remove_host(vha->host);
4589 return NULL;
4590 }
f999f4c1 4591
a4239945
QT		 4592 /* todo: what about ext login? */
4593 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4594 vha->scan.l = vmalloc(vha->scan.size);
4595 if (!vha->scan.l) {
4596 ql_log(ql_log_fatal, vha, 0xd04a,
4597 "Alloc failed for scan database.\n");
4598 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4599 vha->gnl.l, vha->gnl.ldma);
4600 scsi_remove_host(vha->host);
4601 return NULL;
4602 }
f352eeb7 4603 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
a4239945 4604
e315cd28 4605 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4606 ql_dbg(ql_dbg_init, vha, 0x0041,
4607 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4608 vha->host, vha->hw, vha,
4609 dev_name(&(ha->pdev->dev)));
4610
e315cd28 4611 return vha;
1da177e4
LT		 4612}
4613
726b8548 4614struct qla_work_evt *
f999f4c1 4615qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4616{
4617 struct qla_work_evt *e;
feafb7b1
AE		 4618 uint8_t bail;
4619
4620 QLA_VHA_MARK_BUSY(vha, bail);
4621 if (bail)
4622 return NULL;
0971de7f 4623
f999f4c1 4624 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4625 if (!e) {
4626 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4627 return NULL;
feafb7b1 4628 }
0971de7f
AV		 4629
4630 INIT_LIST_HEAD(&e->list);
4631 e->type = type;
4632 e->flags = QLA_EVT_FLAG_FREE;
4633 return e;
4634}
4635
726b8548 4636int
f999f4c1 4637qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4638{
f999f4c1 4639 unsigned long flags;
9b3e0f4d 4640 bool q = false;
0971de7f 4641
f999f4c1 4642 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4643 list_add_tail(&e->list, &vha->work_list);
9b3e0f4d
QT		 4644
4645 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4646 q = true;
4647
f999f4c1 4648 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2 4649
9b3e0f4d
QT		 4650 if (q)
4651 queue_work(vha->hw->wq, &vha->iocb_work);
f999f4c1 4652
0971de7f
AV		 4653 return QLA_SUCCESS;
4654}
4655
4656int
e315cd28 4657qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4658 u32 data)
4659{
4660 struct qla_work_evt *e;
4661
f999f4c1 4662 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4663 if (!e)
4664 return QLA_FUNCTION_FAILED;
4665
4666 e->u.aen.code = code;
4667 e->u.aen.data = data;
f999f4c1 4668 return qla2x00_post_work(vha, e);
0971de7f
AV		 4669}
4670
8a659571
AV		 4671int
4672qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4673{
4674 struct qla_work_evt *e;
4675
f999f4c1 4676 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4677 if (!e)
4678 return QLA_FUNCTION_FAILED;
4679
4680 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4681 return qla2x00_post_work(vha, e);
8a659571
AV		 4682}
4683
ac280b67
AV		 4684#define qla2x00_post_async_work(name, type) \
4685int qla2x00_post_async_##name##_work( \
4686 struct scsi_qla_host *vha, \
4687 fc_port_t *fcport, uint16_t *data) \
4688{ \
4689 struct qla_work_evt *e; \
4690 \
4691 e = qla2x00_alloc_work(vha, type); \
4692 if (!e) \
4693 return QLA_FUNCTION_FAILED; \
4694 \
4695 e->u.logio.fcport = fcport; \
4696 if (data) { \
4697 e->u.logio.data[0] = data[0]; \
4698 e->u.logio.data[1] = data[1]; \
4699 } \
6d674927 4700 fcport->flags |= FCF_ASYNC_ACTIVE; \
ac280b67
AV		 4701 return qla2x00_post_work(vha, e); \
4702}
4703
4704qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4705qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4706qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4707qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4708qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
11aea16a
QT		 4709qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4710qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
ac280b67 4711
3420d36c
AV		 4712int
4713qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4714{
4715 struct qla_work_evt *e;
4716
4717 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4718 if (!e)
4719 return QLA_FUNCTION_FAILED;
4720
4721 e->u.uevent.code = code;
4722 return qla2x00_post_work(vha, e);
4723}
4724
4725static void
4726qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4727{
4728 char event_string[40];
4729 char *envp[] = { event_string, NULL };
4730
4731 switch (code) {
4732 case QLA_UEVENT_CODE_FW_DUMP:
4733 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4734 vha->host_no);
4735 break;
4736 default:
4737 /* do nothing */
4738 break;
4739 }
4740 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4741}
4742
8ae6d9c7
GM		 4743int
4744qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4745 uint32_t *data, int cnt)
4746{
4747 struct qla_work_evt *e;
4748
4749 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4750 if (!e)
4751 return QLA_FUNCTION_FAILED;
4752
4753 e->u.aenfx.evtcode = evtcode;
4754 e->u.aenfx.count = cnt;
4755 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4756 return qla2x00_post_work(vha, e);
4757}
4758
726b8548
QT		 4759int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4760{
4761 struct qla_work_evt *e;
4762
4763 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4764 if (!e)
4765 return QLA_FUNCTION_FAILED;
4766
4767 e->u.fcport.fcport = fcport;
4768 return qla2x00_post_work(vha, e);
4769}
4770
4771static
4772void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4773{
4774 unsigned long flags;
b5d15312 4775 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 4776 struct qlt_plogi_ack_t *pla =
4777 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 4778 uint8_t free_fcport = 0;
a4239945 4779 u64 wwn;
726b8548 4780
9cd883f0
QT		 4781 ql_dbg(ql_dbg_disc, vha, 0xffff,
4782 "%s %d %8phC enter\n",
4783 __func__, __LINE__, e->u.new_sess.port_name);
4784
726b8548
QT		 4785 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4786 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4787 if (fcport) {
4788 fcport->d_id = e->u.new_sess.id;
4789 if (pla) {
4790 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
9b3e0f4d
QT		 4791 memcpy(fcport->node_name,
4792 pla->iocb.u.isp24.u.plogi.node_name,
4793 WWN_SIZE);
726b8548
QT		 4794 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4795 /* we took an extra ref_count to prevent PLOGI ACK when
4796 * fcport/sess has not been created.
4797 */
4798 pla->ref_count--;
4799 }
4800 } else {
b5d15312 4801 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 4802 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4803 if (fcport) {
4804 fcport->d_id = e->u.new_sess.id;
726b8548
QT		 4805 fcport->flags |= FCF_FABRIC_DEVICE;
4806 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
a4239945
QT		 4807 if (e->u.new_sess.fc4_type == FC4_TYPE_FCP_SCSI)
4808 fcport->fc4_type = FC4_TYPE_FCP_SCSI;
726b8548
QT		 4809
4810 memcpy(fcport->port_name, e->u.new_sess.port_name,
4811 WWN_SIZE);
b5d15312
QT		 4812 } else {
4813 ql_dbg(ql_dbg_disc, vha, 0xffff,
4814 "%s %8phC mem alloc fail.\n",
4815 __func__, e->u.new_sess.port_name);
4816
4817 if (pla)
4818 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4819 return;
4820 }
4821
4822 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a4239945 4823 /* search again to make sure no one else got ahead */
b5d15312
QT		 4824 tfcp = qla2x00_find_fcport_by_wwpn(vha,
4825 e->u.new_sess.port_name, 1);
4826 if (tfcp) {
4827 /* should rarily happen */
4828 ql_dbg(ql_dbg_disc, vha, 0xffff,
4829 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
4830 __func__, tfcp->port_name, tfcp->disc_state,
4831 tfcp->fw_login_state);
4832
4833 free_fcport = 1;
4834 } else {
726b8548
QT		 4835 list_add_tail(&fcport->list, &vha->vp_fcports);
4836
19759033
QT		 4837 }
4838 if (pla) {
4839 qlt_plogi_ack_link(vha, pla, fcport,
4840 QLT_PLOGI_LINK_SAME_WWN);
4841 pla->ref_count--;
726b8548
QT		 4842 }
4843 }
4844 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4845
4846 if (fcport) {
9cd883f0
QT		 4847 if (N2N_TOPO(vha->hw))
4848 fcport->flags &= ~FCF_FABRIC_DEVICE;
4849
a4239945
QT		 4850 fcport->id_changed = 1;
4851 fcport->scan_state = QLA_FCPORT_FOUND;
4852 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
4853
5ef696aa 4854 if (pla) {
9cd883f0
QT		 4855 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
4856 u16 wd3_lo;
4857
4858 fcport->fw_login_state = DSC_LS_PRLI_PEND;
4859 fcport->local = 0;
4860 fcport->loop_id =
4861 le16_to_cpu(
4862 pla->iocb.u.isp24.nport_handle);
4863 fcport->fw_login_state = DSC_LS_PRLI_PEND;
4864 wd3_lo =
4865 le16_to_cpu(
4866 pla->iocb.u.isp24.u.prli.wd3_lo);
4867
4868 if (wd3_lo & BIT_7)
4869 fcport->conf_compl_supported = 1;
4870
4871 if ((wd3_lo & BIT_4) == 0)
4872 fcport->port_type = FCT_INITIATOR;
4873 else
4874 fcport->port_type = FCT_TARGET;
4875 }
726b8548 4876 qlt_plogi_ack_unref(vha, pla);
5ef696aa
QT		 4877 } else {
4878 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4879 tfcp = qla2x00_find_fcport_by_nportid(vha,
4880 &e->u.new_sess.id, 1);
4881 if (tfcp && (tfcp != fcport)) {
4882 /*
4883 * We have a conflict fcport with same NportID.
4884 */
4885 ql_dbg(ql_dbg_disc, vha, 0xffff,
4886 "%s %8phC found conflict b4 add. DS %d LS %d\n",
4887 __func__, tfcp->port_name, tfcp->disc_state,
4888 tfcp->fw_login_state);
4889
4890 switch (tfcp->disc_state) {
4891 case DSC_DELETED:
4892 break;
4893 case DSC_DELETE_PEND:
4894 fcport->login_pause = 1;
4895 tfcp->conflict = fcport;
4896 break;
4897 default:
4898 fcport->login_pause = 1;
4899 tfcp->conflict = fcport;
d8630bb9 4900 qlt_schedule_sess_for_deletion(tfcp);
5ef696aa
QT		 4901 break;
4902 }
4903 }
4904 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
a4239945
QT		 4905
4906 wwn = wwn_to_u64(fcport->node_name);
4907
4908 if (!wwn)
4909 qla24xx_async_gnnid(vha, fcport);
4910 else
4911 qla24xx_async_gnl(vha, fcport);
5ef696aa 4912 }
726b8548 4913 }
b5d15312
QT		 4914
4915 if (free_fcport) {
4916 qla2x00_free_fcport(fcport);
4917 if (pla)
4918 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4919 }
726b8548
QT		 4920}
4921
e374f9f5
QT		 4922static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
4923{
4924 struct srb *sp = e->u.iosb.sp;
4925 int rval;
4926
4927 rval = qla2x00_start_sp(sp);
4928 if (rval != QLA_SUCCESS) {
4929 ql_dbg(ql_dbg_disc, vha, 0x2043,
4930 "%s: %s: Re-issue IOCB failed (%d).\n",
4931 __func__, sp->name, rval);
4932 qla24xx_sp_unmap(vha, sp);
4933 }
4934}
4935
ac280b67 4936void
e315cd28 4937qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4938{
f999f4c1
AV		 4939 struct qla_work_evt *e, *tmp;
4940 unsigned long flags;
4941 LIST_HEAD(work);
0971de7f 4942
f999f4c1
AV		 4943 spin_lock_irqsave(&vha->work_lock, flags);
4944 list_splice_init(&vha->work_list, &work);
4945 spin_unlock_irqrestore(&vha->work_lock, flags);
4946
4947 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4948 list_del_init(&e->list);
0971de7f
AV		 4949
4950 switch (e->type) {
4951 case QLA_EVT_AEN:
e315cd28 4952 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4953 e->u.aen.code, e->u.aen.data);
4954 break;
8a659571
AV		 4955 case QLA_EVT_IDC_ACK:
4956 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4957 break;
ac280b67
AV		 4958 case QLA_EVT_ASYNC_LOGIN:
4959 qla2x00_async_login(vha, e->u.logio.fcport,
4960 e->u.logio.data);
4961 break;
ac280b67
AV		 4962 case QLA_EVT_ASYNC_LOGOUT:
4963 qla2x00_async_logout(vha, e->u.logio.fcport);
4964 break;
4965 case QLA_EVT_ASYNC_LOGOUT_DONE:
4966 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4967 e->u.logio.data);
4968 break;
5ff1d584
AV		 4969 case QLA_EVT_ASYNC_ADISC:
4970 qla2x00_async_adisc(vha, e->u.logio.fcport,
4971 e->u.logio.data);
4972 break;
4973 case QLA_EVT_ASYNC_ADISC_DONE:
4974 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4975 e->u.logio.data);
4976 break;
3420d36c
AV		 4977 case QLA_EVT_UEVENT:
4978 qla2x00_uevent_emit(vha, e->u.uevent.code);
4979 break;
8ae6d9c7
GM		 4980 case QLA_EVT_AENFX:
4981 qlafx00_process_aen(vha, e);
4982 break;
726b8548
QT		 4983 case QLA_EVT_GIDPN:
4984 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
4985 break;
4986 case QLA_EVT_GPNID:
4987 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
4988 break;
e374f9f5
QT		 4989 case QLA_EVT_UNMAP:
4990 qla24xx_sp_unmap(vha, e->u.iosb.sp);
726b8548 4991 break;
9b3e0f4d
QT		 4992 case QLA_EVT_RELOGIN:
4993 qla2x00_relogin(vha);
4994 break;
726b8548
QT		 4995 case QLA_EVT_NEW_SESS:
4996 qla24xx_create_new_sess(vha, e);
4997 break;
4998 case QLA_EVT_GPDB:
4999 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5000 e->u.fcport.opt);
5001 break;
a5d42f4c
DG		 5002 case QLA_EVT_PRLI:
5003 qla24xx_async_prli(vha, e->u.fcport.fcport);
5004 break;
726b8548
QT		 5005 case QLA_EVT_GPSC:
5006 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5007 break;
5008 case QLA_EVT_UPD_FCPORT:
5009 qla2x00_update_fcport(vha, e->u.fcport.fcport);
5010 break;
5011 case QLA_EVT_GNL:
5012 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5013 break;
5014 case QLA_EVT_NACK:
5015 qla24xx_do_nack_work(vha, e);
5016 break;
11aea16a
QT		 5017 case QLA_EVT_ASYNC_PRLO:
5018 qla2x00_async_prlo(vha, e->u.logio.fcport);
5019 break;
5020 case QLA_EVT_ASYNC_PRLO_DONE:
5021 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5022 e->u.logio.data);
5023 break;
a4239945
QT		 5024 case QLA_EVT_GPNFT:
5025 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type);
5026 break;
5027 case QLA_EVT_GPNFT_DONE:
5028 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5029 break;
5030 case QLA_EVT_GNNFT_DONE:
5031 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5032 break;
5033 case QLA_EVT_GNNID:
5034 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5035 break;
5036 case QLA_EVT_GFPNID:
5037 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5038 break;
e374f9f5
QT		 5039 case QLA_EVT_SP_RETRY:
5040 qla_sp_retry(vha, e);
0971de7f
AV		 5041 }
5042 if (e->flags & QLA_EVT_FLAG_FREE)
5043 kfree(e);
feafb7b1
AE		 5044
5045 /* For each work completed decrement vha ref count */
5046 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 5047 }
e315cd28 5048}
f999f4c1 5049
9b3e0f4d
QT		 5050int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5051{
5052 struct qla_work_evt *e;
5053
5054 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5055
5056 if (!e) {
5057 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5058 return QLA_FUNCTION_FAILED;
5059 }
5060
5061 return qla2x00_post_work(vha, e);
5062}
5063
e315cd28
AC		 5064/* Relogins all the fcports of a vport
5065 * Context: dpc thread
5066 */
5067void qla2x00_relogin(struct scsi_qla_host *vha)
5068{
5069 fc_port_t *fcport;
c6b2fca8 5070 int status;
726b8548 5071 struct event_arg ea;
e315cd28
AC		 5072
5073 list_for_each_entry(fcport, &vha->vp_fcports, list) {
9cd883f0
QT		 5074 /*
5075 * If the port is not ONLINE then try to login
5076 * to it if we haven't run out of retries.
5077 */
5ff1d584 5078 if (atomic_read(&fcport->state) != FCS_ONLINE &&
6d674927
QT		 5079 fcport->login_retry &&
5080 !(fcport->flags & (FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE))) {
9cd883f0 5081 if (vha->hw->current_topology != ISP_CFG_NL) {
83548fe2 5082 ql_dbg(ql_dbg_disc, fcport->vha, 0x2108,
726b8548
QT		 5083 "%s %8phC DS %d LS %d\n", __func__,
5084 fcport->port_name, fcport->disc_state,
5085 fcport->fw_login_state);
5086 memset(&ea, 0, sizeof(ea));
5087 ea.event = FCME_RELOGIN;
5088 ea.fcport = fcport;
5089 qla2x00_fcport_event_handler(vha, &ea);
9cd883f0 5090 } else if (vha->hw->current_topology == ISP_CFG_NL) {
4005a995 5091 fcport->login_retry--;
e315cd28
AC		 5092 status = qla2x00_local_device_login(vha,
5093 fcport);
726b8548
QT		 5094 if (status == QLA_SUCCESS) {
5095 fcport->old_loop_id = fcport->loop_id;
5096 ql_dbg(ql_dbg_disc, vha, 0x2003,
5097 "Port login OK: logged in ID 0x%x.\n",
5098 fcport->loop_id);
5099 qla2x00_update_fcport(vha, fcport);
5100 } else if (status == 1) {
5101 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5102 /* retry the login again */
5103 ql_dbg(ql_dbg_disc, vha, 0x2007,
5104 "Retrying %d login again loop_id 0x%x.\n",
5105 fcport->login_retry,
5106 fcport->loop_id);
5107 } else {
5108 fcport->login_retry = 0;
5109 }
e315cd28 5110
726b8548
QT		 5111 if (fcport->login_retry == 0 &&
5112 status != QLA_SUCCESS)
5113 qla2x00_clear_loop_id(fcport);
e315cd28 5114 }
e315cd28
AC		 5115 }
5116 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5117 break;
0971de7f 5118 }
9b3e0f4d
QT		 5119
5120 ql_dbg(ql_dbg_disc, vha, 0x400e,
5121 "Relogin end.\n");
0971de7f
AV		 5122}
5123
7d613ac6
SV		 5124/* Schedule work on any of the dpc-workqueues */
5125void
5126qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5127{
5128 struct qla_hw_data *ha = base_vha->hw;
5129
5130 switch (work_code) {
5131 case MBA_IDC_AEN: /* 0x8200 */
5132 if (ha->dpc_lp_wq)
5133 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5134 break;
5135
5136 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5137 if (!ha->flags.nic_core_reset_hdlr_active) {
5138 if (ha->dpc_hp_wq)
5139 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5140 } else
5141 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5142 "NIC Core reset is already active. Skip "
5143 "scheduling it again.\n");
5144 break;
5145 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5146 if (ha->dpc_hp_wq)
5147 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5148 break;
5149 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5150 if (ha->dpc_hp_wq)
5151 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5152 break;
5153 default:
5154 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 5155 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 5156 }
5157
5158 return;
5159}
5160
5161/* Work: Perform NIC Core Unrecoverable state handling */
5162void
5163qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5164{
5165 struct qla_hw_data *ha =
2ad1b67c 5166 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 5167 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5168 uint32_t dev_state = 0;
5169
5170 qla83xx_idc_lock(base_vha, 0);
5171 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5172 qla83xx_reset_ownership(base_vha);
5173 if (ha->flags.nic_core_reset_owner) {
5174 ha->flags.nic_core_reset_owner = 0;
5175 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5176 QLA8XXX_DEV_FAILED);
5177 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5178 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5179 }
5180 qla83xx_idc_unlock(base_vha, 0);
5181}
5182
5183/* Work: Execute IDC state handler */
5184void
5185qla83xx_idc_state_handler_work(struct work_struct *work)
5186{
5187 struct qla_hw_data *ha =
2ad1b67c 5188 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 5189 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5190 uint32_t dev_state = 0;
5191
5192 qla83xx_idc_lock(base_vha, 0);
5193 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5194 if (dev_state == QLA8XXX_DEV_FAILED ||
5195 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5196 qla83xx_idc_state_handler(base_vha);
5197 qla83xx_idc_unlock(base_vha, 0);
5198}
5199
fa492630 5200static int
7d613ac6
SV		 5201qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5202{
5203 int rval = QLA_SUCCESS;
5204 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5205 uint32_t heart_beat_counter1, heart_beat_counter2;
5206
5207 do {
5208 if (time_after(jiffies, heart_beat_wait)) {
5209 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5210 "Nic Core f/w is not alive.\n");
5211 rval = QLA_FUNCTION_FAILED;
5212 break;
5213 }
5214
5215 qla83xx_idc_lock(base_vha, 0);
5216 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5217 &heart_beat_counter1);
5218 qla83xx_idc_unlock(base_vha, 0);
5219 msleep(100);
5220 qla83xx_idc_lock(base_vha, 0);
5221 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5222 &heart_beat_counter2);
5223 qla83xx_idc_unlock(base_vha, 0);
5224 } while (heart_beat_counter1 == heart_beat_counter2);
5225
5226 return rval;
5227}
5228
5229/* Work: Perform NIC Core Reset handling */
5230void
5231qla83xx_nic_core_reset_work(struct work_struct *work)
5232{
5233 struct qla_hw_data *ha =
5234 container_of(work, struct qla_hw_data, nic_core_reset);
5235 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5236 uint32_t dev_state = 0;
5237
81178772
SK		 5238 if (IS_QLA2031(ha)) {
5239 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5240 ql_log(ql_log_warn, base_vha, 0xb081,
5241 "Failed to dump mctp\n");
5242 return;
5243 }
5244
7d613ac6
SV		 5245 if (!ha->flags.nic_core_reset_hdlr_active) {
5246 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5247 qla83xx_idc_lock(base_vha, 0);
5248 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5249 &dev_state);
5250 qla83xx_idc_unlock(base_vha, 0);
5251 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5252 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5253 "Nic Core f/w is alive.\n");
5254 return;
5255 }
5256 }
5257
5258 ha->flags.nic_core_reset_hdlr_active = 1;
5259 if (qla83xx_nic_core_reset(base_vha)) {
5260 /* NIC Core reset failed. */
5261 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5262 "NIC Core reset failed.\n");
5263 }
5264 ha->flags.nic_core_reset_hdlr_active = 0;
5265 }
5266}
5267
5268/* Work: Handle 8200 IDC aens */
5269void
5270qla83xx_service_idc_aen(struct work_struct *work)
5271{
5272 struct qla_hw_data *ha =
5273 container_of(work, struct qla_hw_data, idc_aen);
5274 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5275 uint32_t dev_state, idc_control;
5276
5277 qla83xx_idc_lock(base_vha, 0);
5278 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5279 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5280 qla83xx_idc_unlock(base_vha, 0);
5281 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5282 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5283 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5284 "Application requested NIC Core Reset.\n");
5285 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5286 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5287 QLA_SUCCESS) {
5288 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5289 "Other protocol driver requested NIC Core Reset.\n");
5290 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5291 }
5292 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5293 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5294 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5295 }
5296}
5297
5298static void
5299qla83xx_wait_logic(void)
5300{
5301 int i;
5302
5303 /* Yield CPU */
5304 if (!in_interrupt()) {
5305 /*
5306 * Wait about 200ms before retrying again.
5307 * This controls the number of retries for single
5308 * lock operation.
5309 */
5310 msleep(100);
5311 schedule();
5312 } else {
5313 for (i = 0; i < 20; i++)
5314 cpu_relax(); /* This a nop instr on i386 */
5315 }
5316}
5317
fa492630 5318static int
7d613ac6
SV		 5319qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5320{
5321 int rval;
5322 uint32_t data;
5323 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5324 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5325 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 5326 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5327 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5328
5329 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5330 if (rval)
5331 return rval;
5332
5333 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5334 return QLA_SUCCESS;
5335 } else {
5336 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5337 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5338 data);
5339 if (rval)
5340 return rval;
5341
5342 msleep(200);
5343
5344 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5345 &data);
5346 if (rval)
5347 return rval;
5348
5349 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5350 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5351 ~(idc_lck_rcvry_stage_mask));
5352 rval = qla83xx_wr_reg(base_vha,
5353 QLA83XX_IDC_LOCK_RECOVERY, data);
5354 if (rval)
5355 return rval;
5356
5357 /* Forcefully perform IDC UnLock */
5358 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5359 &data);
5360 if (rval)
5361 return rval;
5362 /* Clear lock-id by setting 0xff */
5363 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5364 0xff);
5365 if (rval)
5366 return rval;
5367 /* Clear lock-recovery by setting 0x0 */
5368 rval = qla83xx_wr_reg(base_vha,
5369 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5370 if (rval)
5371 return rval;
5372 } else
5373 return QLA_SUCCESS;
5374 }
5375
5376 return rval;
5377}
5378
fa492630 5379static int
7d613ac6
SV		 5380qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5381{
5382 int rval = QLA_SUCCESS;
5383 uint32_t o_drv_lockid, n_drv_lockid;
5384 unsigned long lock_recovery_timeout;
5385
5386 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5387retry_lockid:
5388 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5389 if (rval)
5390 goto exit;
5391
5392 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5393 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5394 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5395 return QLA_SUCCESS;
5396 else
5397 return QLA_FUNCTION_FAILED;
5398 }
5399
5400 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5401 if (rval)
5402 goto exit;
5403
5404 if (o_drv_lockid == n_drv_lockid) {
5405 qla83xx_wait_logic();
5406 goto retry_lockid;
5407 } else
5408 return QLA_SUCCESS;
5409
5410exit:
5411 return rval;
5412}
5413
5414void
5415qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5416{
5417 uint16_t options = (requester_id << 15) | BIT_6;
5418 uint32_t data;
6c315553 5419 uint32_t lock_owner;
7d613ac6
SV		 5420 struct qla_hw_data *ha = base_vha->hw;
5421
5422 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5423retry_lock:
5424 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5425 == QLA_SUCCESS) {
5426 if (data) {
5427 /* Setting lock-id to our function-number */
5428 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5429 ha->portnum);
5430 } else {
6c315553
SK		 5431 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5432 &lock_owner);
7d613ac6 5433 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5434 "Failed to acquire IDC lock, acquired by %d, "
5435 "retrying...\n", lock_owner);
7d613ac6
SV		 5436
5437 /* Retry/Perform IDC-Lock recovery */
5438 if (qla83xx_idc_lock_recovery(base_vha)
5439 == QLA_SUCCESS) {
5440 qla83xx_wait_logic();
5441 goto retry_lock;
5442 } else
5443 ql_log(ql_log_warn, base_vha, 0xb075,
5444 "IDC Lock recovery FAILED.\n");
5445 }
5446
5447 }
5448
5449 return;
5450
5451 /* XXX: IDC-lock implementation using access-control mbx */
5452retry_lock2:
5453 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5454 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5455 "Failed to acquire IDC lock. retrying...\n");
5456 /* Retry/Perform IDC-Lock recovery */
5457 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5458 qla83xx_wait_logic();
5459 goto retry_lock2;
5460 } else
5461 ql_log(ql_log_warn, base_vha, 0xb076,
5462 "IDC Lock recovery FAILED.\n");
5463 }
5464
5465 return;
5466}
5467
5468void
5469qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5470{
5897cb2f
BVA		 5471#if 0
5472 uint16_t options = (requester_id << 15) | BIT_7;
5473#endif
5474 uint16_t retry;
7d613ac6
SV		 5475 uint32_t data;
5476 struct qla_hw_data *ha = base_vha->hw;
5477
5478 /* IDC-unlock implementation using driver-unlock/lock-id
5479 * remote registers
5480 */
5481 retry = 0;
5482retry_unlock:
5483 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5484 == QLA_SUCCESS) {
5485 if (data == ha->portnum) {
5486 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5487 /* Clearing lock-id by setting 0xff */
5488 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5489 } else if (retry < 10) {
5490 /* SV: XXX: IDC unlock retrying needed here? */
5491
5492 /* Retry for IDC-unlock */
5493 qla83xx_wait_logic();
5494 retry++;
5495 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5496 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5497 goto retry_unlock;
5498 }
5499 } else if (retry < 10) {
5500 /* Retry for IDC-unlock */
5501 qla83xx_wait_logic();
5502 retry++;
5503 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5504 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5505 goto retry_unlock;
5506 }
5507
5508 return;
5509
5897cb2f 5510#if 0
7d613ac6
SV		 5511 /* XXX: IDC-unlock implementation using access-control mbx */
5512 retry = 0;
5513retry_unlock2:
5514 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5515 if (retry < 10) {
5516 /* Retry for IDC-unlock */
5517 qla83xx_wait_logic();
5518 retry++;
5519 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5520 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5521 goto retry_unlock2;
5522 }
5523 }
5524
5525 return;
5897cb2f 5526#endif
7d613ac6
SV		 5527}
5528
5529int
5530__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5531{
5532 int rval = QLA_SUCCESS;
5533 struct qla_hw_data *ha = vha->hw;
5534 uint32_t drv_presence;
5535
5536 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5537 if (rval == QLA_SUCCESS) {
5538 drv_presence |= (1 << ha->portnum);
5539 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5540 drv_presence);
5541 }
5542
5543 return rval;
5544}
5545
5546int
5547qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5548{
5549 int rval = QLA_SUCCESS;
5550
5551 qla83xx_idc_lock(vha, 0);
5552 rval = __qla83xx_set_drv_presence(vha);
5553 qla83xx_idc_unlock(vha, 0);
5554
5555 return rval;
5556}
5557
5558int
5559__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5560{
5561 int rval = QLA_SUCCESS;
5562 struct qla_hw_data *ha = vha->hw;
5563 uint32_t drv_presence;
5564
5565 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5566 if (rval == QLA_SUCCESS) {
5567 drv_presence &= ~(1 << ha->portnum);
5568 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5569 drv_presence);
5570 }
5571
5572 return rval;
5573}
5574
5575int
5576qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5577{
5578 int rval = QLA_SUCCESS;
5579
5580 qla83xx_idc_lock(vha, 0);
5581 rval = __qla83xx_clear_drv_presence(vha);
5582 qla83xx_idc_unlock(vha, 0);
5583
5584 return rval;
5585}
5586
fa492630 5587static void
7d613ac6
SV		 5588qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5589{
5590 struct qla_hw_data *ha = vha->hw;
5591 uint32_t drv_ack, drv_presence;
5592 unsigned long ack_timeout;
5593
5594 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5595 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5596 while (1) {
5597 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5598 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5599 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5600 break;
5601
5602 if (time_after_eq(jiffies, ack_timeout)) {
5603 ql_log(ql_log_warn, vha, 0xb067,
5604 "RESET ACK TIMEOUT! drv_presence=0x%x "
5605 "drv_ack=0x%x\n", drv_presence, drv_ack);
5606 /*
5607 * The function(s) which did not ack in time are forced
5608 * to withdraw any further participation in the IDC
5609 * reset.
5610 */
5611 if (drv_ack != drv_presence)
5612 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5613 drv_ack);
5614 break;
5615 }
5616
5617 qla83xx_idc_unlock(vha, 0);
5618 msleep(1000);
5619 qla83xx_idc_lock(vha, 0);
5620 }
5621
5622 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5623 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5624}
5625
fa492630 5626static int
7d613ac6
SV		 5627qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5628{
5629 int rval = QLA_SUCCESS;
5630 uint32_t idc_control;
5631
5632 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5633 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5634
5635 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5636 __qla83xx_get_idc_control(vha, &idc_control);
5637 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5638 __qla83xx_set_idc_control(vha, 0);
5639
5640 qla83xx_idc_unlock(vha, 0);
5641 rval = qla83xx_restart_nic_firmware(vha);
5642 qla83xx_idc_lock(vha, 0);
5643
5644 if (rval != QLA_SUCCESS) {
5645 ql_log(ql_log_fatal, vha, 0xb06a,
5646 "Failed to restart NIC f/w.\n");
5647 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5648 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5649 } else {
5650 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5651 "Success in restarting nic f/w.\n");
5652 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5653 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5654 }
5655
5656 return rval;
5657}
5658
5659/* Assumes idc_lock always held on entry */
5660int
5661qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5662{
5663 struct qla_hw_data *ha = base_vha->hw;
5664 int rval = QLA_SUCCESS;
5665 unsigned long dev_init_timeout;
5666 uint32_t dev_state;
5667
5668 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5669 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5670
5671 while (1) {
5672
5673 if (time_after_eq(jiffies, dev_init_timeout)) {
5674 ql_log(ql_log_warn, base_vha, 0xb06e,
5675 "Initialization TIMEOUT!\n");
5676 /* Init timeout. Disable further NIC Core
5677 * communication.
5678 */
5679 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5680 QLA8XXX_DEV_FAILED);
5681 ql_log(ql_log_info, base_vha, 0xb06f,
5682 "HW State: FAILED.\n");
5683 }
5684
5685 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5686 switch (dev_state) {
5687 case QLA8XXX_DEV_READY:
5688 if (ha->flags.nic_core_reset_owner)
5689 qla83xx_idc_audit(base_vha,
5690 IDC_AUDIT_COMPLETION);
5691 ha->flags.nic_core_reset_owner = 0;
5692 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5693 "Reset_owner reset by 0x%x.\n",
5694 ha->portnum);
5695 goto exit;
5696 case QLA8XXX_DEV_COLD:
5697 if (ha->flags.nic_core_reset_owner)
5698 rval = qla83xx_device_bootstrap(base_vha);
5699 else {
5700 /* Wait for AEN to change device-state */
5701 qla83xx_idc_unlock(base_vha, 0);
5702 msleep(1000);
5703 qla83xx_idc_lock(base_vha, 0);
5704 }
5705 break;
5706 case QLA8XXX_DEV_INITIALIZING:
5707 /* Wait for AEN to change device-state */
5708 qla83xx_idc_unlock(base_vha, 0);
5709 msleep(1000);
5710 qla83xx_idc_lock(base_vha, 0);
5711 break;
5712 case QLA8XXX_DEV_NEED_RESET:
5713 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5714 qla83xx_need_reset_handler(base_vha);
5715 else {
5716 /* Wait for AEN to change device-state */
5717 qla83xx_idc_unlock(base_vha, 0);
5718 msleep(1000);
5719 qla83xx_idc_lock(base_vha, 0);
5720 }
5721 /* reset timeout value after need reset handler */
5722 dev_init_timeout = jiffies +
5723 (ha->fcoe_dev_init_timeout * HZ);
5724 break;
5725 case QLA8XXX_DEV_NEED_QUIESCENT:
5726 /* XXX: DEBUG for now */
5727 qla83xx_idc_unlock(base_vha, 0);
5728 msleep(1000);
5729 qla83xx_idc_lock(base_vha, 0);
5730 break;
5731 case QLA8XXX_DEV_QUIESCENT:
5732 /* XXX: DEBUG for now */
5733 if (ha->flags.quiesce_owner)
5734 goto exit;
5735
5736 qla83xx_idc_unlock(base_vha, 0);
5737 msleep(1000);
5738 qla83xx_idc_lock(base_vha, 0);
5739 dev_init_timeout = jiffies +
5740 (ha->fcoe_dev_init_timeout * HZ);
5741 break;
5742 case QLA8XXX_DEV_FAILED:
5743 if (ha->flags.nic_core_reset_owner)
5744 qla83xx_idc_audit(base_vha,
5745 IDC_AUDIT_COMPLETION);
5746 ha->flags.nic_core_reset_owner = 0;
5747 __qla83xx_clear_drv_presence(base_vha);
5748 qla83xx_idc_unlock(base_vha, 0);
5749 qla8xxx_dev_failed_handler(base_vha);
5750 rval = QLA_FUNCTION_FAILED;
5751 qla83xx_idc_lock(base_vha, 0);
5752 goto exit;
5753 case QLA8XXX_BAD_VALUE:
5754 qla83xx_idc_unlock(base_vha, 0);
5755 msleep(1000);
5756 qla83xx_idc_lock(base_vha, 0);
5757 break;
5758 default:
5759 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5760 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5761 qla83xx_idc_unlock(base_vha, 0);
5762 qla8xxx_dev_failed_handler(base_vha);
5763 rval = QLA_FUNCTION_FAILED;
5764 qla83xx_idc_lock(base_vha, 0);
5765 goto exit;
5766 }
5767 }
5768
5769exit:
5770 return rval;
5771}
5772
f3ddac19
CD		 5773void
5774qla2x00_disable_board_on_pci_error(struct work_struct *work)
5775{
5776 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5777 board_disable);
5778 struct pci_dev *pdev = ha->pdev;
5779 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5780
726b8548
QT		 5781 /*
5782 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5783 * where it was set first.
5784 */
5785 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5786 return;
5787
f3ddac19
CD		 5788 ql_log(ql_log_warn, base_vha, 0x015b,
5789 "Disabling adapter.\n");
5790
efdb5760
SC		 5791 if (!atomic_read(&pdev->enable_cnt)) {
5792 ql_log(ql_log_info, base_vha, 0xfffc,
5793 "PCI device disabled, no action req for PCI error=%lx\n",
5794 base_vha->pci_flags);
5795 return;
5796 }
5797
726b8548
QT		 5798 qla2x00_wait_for_sess_deletion(base_vha);
5799
f3ddac19
CD		 5800 set_bit(UNLOADING, &base_vha->dpc_flags);
5801
5802 qla2x00_delete_all_vps(ha, base_vha);
5803
5804 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5805
5806 qla2x00_dfs_remove(base_vha);
5807
5808 qla84xx_put_chip(base_vha);
5809
5810 if (base_vha->timer_active)
5811 qla2x00_stop_timer(base_vha);
5812
5813 base_vha->flags.online = 0;
5814
5815 qla2x00_destroy_deferred_work(ha);
5816
5817 /*
5818 * Do not try to stop beacon blink as it will issue a mailbox
5819 * command.
5820 */
5821 qla2x00_free_sysfs_attr(base_vha, false);
5822
5823 fc_remove_host(base_vha->host);
5824
5825 scsi_remove_host(base_vha->host);
5826
5827 base_vha->flags.init_done = 0;
5828 qla25xx_delete_queues(base_vha);
f3ddac19 5829 qla2x00_free_fcports(base_vha);
093df737 5830 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5831 qla2x00_mem_free(ha);
5832 qla82xx_md_free(base_vha);
5833 qla2x00_free_queues(ha);
5834
f3ddac19
CD		 5835 qla2x00_unmap_iobases(ha);
5836
5837 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5838 pci_disable_pcie_error_reporting(pdev);
5839 pci_disable_device(pdev);
f3ddac19 5840
beb9e315
JL		 5841 /*
5842 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5843 */
f3ddac19
CD		 5844}
5845
1da177e4
LT		 5846/**************************************************************************
5847* qla2x00_do_dpc
5848* This kernel thread is a task that is schedule by the interrupt handler
5849* to perform the background processing for interrupts.
5850*
5851* Notes:
5852* This task always run in the context of a kernel thread. It
5853* is kick-off by the driver's detect code and starts up
5854* up one per adapter. It immediately goes to sleep and waits for
5855* some fibre event. When either the interrupt handler or
5856* the timer routine detects a event it will one of the task
5857* bits then wake us up.
5858**************************************************************************/
5859static int
5860qla2x00_do_dpc(void *data)
5861{
e315cd28
AC		 5862 scsi_qla_host_t *base_vha;
5863 struct qla_hw_data *ha;
d7459527
MH		 5864 uint32_t online;
5865 struct qla_qpair *qpair;
1da177e4 5866
e315cd28
AC		 5867 ha = (struct qla_hw_data *)data;
5868 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5869
8698a745 5870 set_user_nice(current, MIN_NICE);
1da177e4 5871
563585ec 5872 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5873 while (!kthread_should_stop()) {
7c3df132
SK		 5874 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5875 "DPC handler sleeping.\n");
1da177e4 5876
39a11240 5877 schedule();
1da177e4 5878
c142caf0
AV		 5879 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5880 goto end_loop;
1da177e4 5881
85880801 5882 if (ha->flags.eeh_busy) {
7c3df132
SK		 5883 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5884 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5885 goto end_loop;
85880801
AV		 5886 }
5887
1da177e4
LT		 5888 ha->dpc_active = 1;
5889
5f28d2d7
SK		 5890 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5891 "DPC handler waking up, dpc_flags=0x%lx.\n",
5892 base_vha->dpc_flags);
1da177e4 5893
a29b3dd7
JC		 5894 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5895 break;
5896
7ec0effd
AD		 5897 if (IS_P3P_TYPE(ha)) {
5898 if (IS_QLA8044(ha)) {
5899 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5900 &base_vha->dpc_flags)) {
5901 qla8044_idc_lock(ha);
5902 qla8044_wr_direct(base_vha,
5903 QLA8044_CRB_DEV_STATE_INDEX,
5904 QLA8XXX_DEV_FAILED);
5905 qla8044_idc_unlock(ha);
5906 ql_log(ql_log_info, base_vha, 0x4004,
5907 "HW State: FAILED.\n");
5908 qla8044_device_state_handler(base_vha);
5909 continue;
5910 }
5911
5912 } else {
5913 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5914 &base_vha->dpc_flags)) {
5915 qla82xx_idc_lock(ha);
5916 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5917 QLA8XXX_DEV_FAILED);
5918 qla82xx_idc_unlock(ha);
5919 ql_log(ql_log_info, base_vha, 0x0151,
5920 "HW State: FAILED.\n");
5921 qla82xx_device_state_handler(base_vha);
5922 continue;
5923 }
a9083016
GM		 5924 }
5925
5926 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5927 &base_vha->dpc_flags)) {
5928
7c3df132
SK		 5929 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5930 "FCoE context reset scheduled.\n");
a9083016
GM		 5931 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5932 &base_vha->dpc_flags))) {
5933 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5934 /* FCoE-ctx reset failed.
5935 * Escalate to chip-reset
5936 */
5937 set_bit(ISP_ABORT_NEEDED,
5938 &base_vha->dpc_flags);
5939 }
5940 clear_bit(ABORT_ISP_ACTIVE,
5941 &base_vha->dpc_flags);
5942 }
5943
7c3df132
SK		 5944 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5945 "FCoE context reset end.\n");
a9083016 5946 }
8ae6d9c7
GM		 5947 } else if (IS_QLAFX00(ha)) {
5948 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5949 &base_vha->dpc_flags)) {
5950 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5951 "Firmware Reset Recovery\n");
5952 if (qlafx00_reset_initialize(base_vha)) {
5953 /* Failed. Abort isp later. */
5954 if (!test_bit(UNLOADING,
f92f82d6 5955 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5956 set_bit(ISP_UNRECOVERABLE,
5957 &base_vha->dpc_flags);
5958 ql_dbg(ql_dbg_dpc, base_vha,
5959 0x4021,
5960 "Reset Recovery Failed\n");
f92f82d6 5961 }
8ae6d9c7
GM		 5962 }
5963 }
5964
5965 if (test_and_clear_bit(FX00_TARGET_SCAN,
5966 &base_vha->dpc_flags)) {
5967 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5968 "ISPFx00 Target Scan scheduled\n");
5969 if (qlafx00_rescan_isp(base_vha)) {
5970 if (!test_bit(UNLOADING,
5971 &base_vha->dpc_flags))
5972 set_bit(ISP_UNRECOVERABLE,
5973 &base_vha->dpc_flags);
5974 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5975 "ISPFx00 Target Scan Failed\n");
5976 }
5977 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5978 "ISPFx00 Target Scan End\n");
5979 }
e8f5e95d
AB		 5980 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5981 &base_vha->dpc_flags)) {
5982 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5983 "ISPFx00 Host Info resend scheduled\n");
5984 qlafx00_fx_disc(base_vha,
5985 &base_vha->hw->mr.fcport,
5986 FXDISC_REG_HOST_INFO);
5987 }
a9083016
GM		 5988 }
5989
e4e3a2ce
QT		 5990 if (test_and_clear_bit(DETECT_SFP_CHANGE,
5991 &base_vha->dpc_flags) &&
5992 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
5993 qla24xx_detect_sfp(base_vha);
5994
5995 if (ha->flags.detected_lr_sfp !=
5996 ha->flags.using_lr_setting)
5997 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
5998 }
5999
e315cd28
AC		 6000 if (test_and_clear_bit(ISP_ABORT_NEEDED,
6001 &base_vha->dpc_flags)) {
1da177e4 6002
7c3df132
SK		 6003 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6004 "ISP abort scheduled.\n");
1da177e4 6005 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 6006 &base_vha->dpc_flags))) {
1da177e4 6007
a9083016 6008 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 6009 /* failed. retry later */
6010 set_bit(ISP_ABORT_NEEDED,
e315cd28 6011 &base_vha->dpc_flags);
99363ef8 6012 }
e315cd28
AC		 6013 clear_bit(ABORT_ISP_ACTIVE,
6014 &base_vha->dpc_flags);
99363ef8
SJ		 6015 }
6016
7c3df132
SK		 6017 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6018 "ISP abort end.\n");
1da177e4
LT		 6019 }
6020
a394aac8
DJ		 6021 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6022 &base_vha->dpc_flags)) {
e315cd28 6023 qla2x00_update_fcports(base_vha);
c9c5ced9 6024 }
d97994dc 6025
8ae6d9c7
GM		 6026 if (IS_QLAFX00(ha))
6027 goto loop_resync_check;
6028
579d12b5 6029 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 6030 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6031 "Quiescence mode scheduled.\n");
7ec0effd
AD		 6032 if (IS_P3P_TYPE(ha)) {
6033 if (IS_QLA82XX(ha))
6034 qla82xx_device_state_handler(base_vha);
6035 if (IS_QLA8044(ha))
6036 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 6037 clear_bit(ISP_QUIESCE_NEEDED,
6038 &base_vha->dpc_flags);
6039 if (!ha->flags.quiesce_owner) {
6040 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 6041 if (IS_QLA82XX(ha)) {
6042 qla82xx_idc_lock(ha);
6043 qla82xx_clear_qsnt_ready(
6044 base_vha);
6045 qla82xx_idc_unlock(ha);
6046 } else if (IS_QLA8044(ha)) {
6047 qla8044_idc_lock(ha);
6048 qla8044_clear_qsnt_ready(
6049 base_vha);
6050 qla8044_idc_unlock(ha);
6051 }
8fcd6b8b
CD		 6052 }
6053 } else {
6054 clear_bit(ISP_QUIESCE_NEEDED,
6055 &base_vha->dpc_flags);
6056 qla2x00_quiesce_io(base_vha);
579d12b5 6057 }
7c3df132
SK		 6058 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6059 "Quiescence mode end.\n");
579d12b5
SK		 6060 }
6061
e315cd28 6062 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 6063 &base_vha->dpc_flags) &&
e315cd28 6064 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 6065
7c3df132
SK		 6066 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6067 "Reset marker scheduled.\n");
e315cd28
AC		 6068 qla2x00_rst_aen(base_vha);
6069 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 6070 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6071 "Reset marker end.\n");
1da177e4
LT		 6072 }
6073
6074 /* Retry each device up to login retry count */
4005a995 6075 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
e315cd28
AC		 6076 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6077 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 6078
4005a995
QT		 6079 if (!base_vha->relogin_jif ||
6080 time_after_eq(jiffies, base_vha->relogin_jif)) {
6081 base_vha->relogin_jif = jiffies + HZ;
6082 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6083
9b3e0f4d 6084 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
4005a995 6085 "Relogin scheduled.\n");
9b3e0f4d 6086 qla24xx_post_relogin_work(base_vha);
4005a995 6087 }
1da177e4 6088 }
8ae6d9c7 6089loop_resync_check:
e315cd28 6090 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 6091 &base_vha->dpc_flags)) {
1da177e4 6092
7c3df132
SK		 6093 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6094 "Loop resync scheduled.\n");
1da177e4
LT		 6095
6096 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 6097 &base_vha->dpc_flags))) {
1da177e4 6098
52c82823 6099 qla2x00_loop_resync(base_vha);
1da177e4 6100
e315cd28
AC		 6101 clear_bit(LOOP_RESYNC_ACTIVE,
6102 &base_vha->dpc_flags);
1da177e4
LT		 6103 }
6104
7c3df132
SK		 6105 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6106 "Loop resync end.\n");
1da177e4
LT		 6107 }
6108
8ae6d9c7
GM		 6109 if (IS_QLAFX00(ha))
6110 goto intr_on_check;
6111
e315cd28
AC		 6112 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6113 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6114 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6115 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 6116 }
6117
8ae6d9c7 6118intr_on_check:
1da177e4 6119 if (!ha->interrupts_on)
fd34f556 6120 ha->isp_ops->enable_intrs(ha);
1da177e4 6121
e315cd28 6122 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 6123 &base_vha->dpc_flags)) {
6124 if (ha->beacon_blink_led == 1)
6125 ha->isp_ops->beacon_blink(base_vha);
6126 }
f6df144c 6127
d7459527
MH		 6128 /* qpair online check */
6129 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6130 &base_vha->dpc_flags)) {
6131 if (ha->flags.eeh_busy ||
6132 ha->flags.pci_channel_io_perm_failure)
6133 online = 0;
6134 else
6135 online = 1;
6136
6137 mutex_lock(&ha->mq_lock);
6138 list_for_each_entry(qpair, &base_vha->qp_list,
6139 qp_list_elem)
6140 qpair->online = online;
6141 mutex_unlock(&ha->mq_lock);
6142 }
6143
deeae7a6
DG		 6144 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) {
6145 ql_log(ql_log_info, base_vha, 0xffffff,
6146 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6147 ha->nvme_last_rptd_aen);
6148 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) {
6149 ql_log(ql_log_info, base_vha, 0xffffff,
6150 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6151 ha->nvme_last_rptd_aen);
6152 }
6153 }
6154
8ae6d9c7
GM		 6155 if (!IS_QLAFX00(ha))
6156 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 6157
1da177e4 6158 ha->dpc_active = 0;
c142caf0 6159end_loop:
563585ec 6160 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 6161 } /* End of while(1) */
563585ec 6162 __set_current_state(TASK_RUNNING);
1da177e4 6163
7c3df132
SK		 6164 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
6165 "DPC handler exiting.\n");
1da177e4
LT		 6166
6167 /*
6168 * Make sure that nobody tries to wake us up again.
6169 */
1da177e4
LT		 6170 ha->dpc_active = 0;
6171
ac280b67
AV		 6172 /* Cleanup any residual CTX SRBs. */
6173 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6174
39a11240
CH		 6175 return 0;
6176}
6177
6178void
e315cd28 6179qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 6180{
e315cd28 6181 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 6182 struct task_struct *t = ha->dpc_thread;
6183
e315cd28 6184 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 6185 wake_up_process(t);
1da177e4
LT		 6186}
6187
1da177e4
LT		 6188/*
6189* qla2x00_rst_aen
6190* Processes asynchronous reset.
6191*
6192* Input:
6193* ha = adapter block pointer.
6194*/
6195static void
e315cd28 6196qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 6197{
e315cd28
AC		 6198 if (vha->flags.online && !vha->flags.reset_active &&
6199 !atomic_read(&vha->loop_down_timer) &&
6200 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 6201 do {
e315cd28 6202 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6203
6204 /*
6205 * Issue marker command only when we are going to start
6206 * the I/O.
6207 */
e315cd28
AC		 6208 vha->marker_needed = 1;
6209 } while (!atomic_read(&vha->loop_down_timer) &&
6210 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 6211 }
6212}
6213
1da177e4
LT		 6214/**************************************************************************
6215* qla2x00_timer
6216*
6217* Description:
6218* One second timer
6219*
6220* Context: Interrupt
6221***************************************************************************/
2c3dfe3f 6222void
8e5f4ba0 6223qla2x00_timer(struct timer_list *t)
1da177e4 6224{
8e5f4ba0 6225 scsi_qla_host_t *vha = from_timer(vha, t, timer);
1da177e4 6226 unsigned long cpu_flags = 0;
1da177e4
LT		 6227 int start_dpc = 0;
6228 int index;
6229 srb_t *sp;
85880801 6230 uint16_t w;
e315cd28 6231 struct qla_hw_data *ha = vha->hw;
73208dfd 6232 struct req_que *req;
85880801 6233
a5b36321 6234 if (ha->flags.eeh_busy) {
7c3df132
SK		 6235 ql_dbg(ql_dbg_timer, vha, 0x6000,
6236 "EEH = %d, restarting timer.\n",
6237 ha->flags.eeh_busy);
a5b36321
LC		 6238 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6239 return;
6240 }
6241
f3ddac19
CD		 6242 /*
6243 * Hardware read to raise pending EEH errors during mailbox waits. If
6244 * the read returns -1 then disable the board.
6245 */
6246 if (!pci_channel_offline(ha->pdev)) {
85880801 6247 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 6248 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 6249 }
1da177e4 6250
cefcaba6 6251 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 6252 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 6253 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6254 start_dpc++;
7ec0effd
AD		 6255 if (IS_QLA82XX(ha))
6256 qla82xx_watchdog(vha);
6257 else if (IS_QLA8044(ha))
6258 qla8044_watchdog(vha);
579d12b5
SK		 6259 }
6260
8ae6d9c7
GM		 6261 if (!vha->vp_idx && IS_QLAFX00(ha))
6262 qlafx00_timer_routine(vha);
6263
1da177e4 6264 /* Loop down handler. */
e315cd28 6265 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 6266 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6267 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 6268 && vha->flags.online) {
1da177e4 6269
e315cd28
AC		 6270 if (atomic_read(&vha->loop_down_timer) ==
6271 vha->loop_down_abort_time) {
1da177e4 6272
7c3df132
SK		 6273 ql_log(ql_log_info, vha, 0x6008,
6274 "Loop down - aborting the queues before time expires.\n");
1da177e4 6275
e315cd28
AC		 6276 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6277 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 6278
f08b7251
AV		 6279 /*
6280 * Schedule an ISP abort to return any FCP2-device
6281 * commands.
6282 */
2c3dfe3f 6283 /* NPIV - scan physical port only */
e315cd28 6284 if (!vha->vp_idx) {
2c3dfe3f
SJ		 6285 spin_lock_irqsave(&ha->hardware_lock,
6286 cpu_flags);
73208dfd 6287 req = ha->req_q_map[0];
2c3dfe3f 6288 for (index = 1;
8d93f550 6289 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 6290 index++) {
6291 fc_port_t *sfcp;
6292
e315cd28 6293 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6294 if (!sp)
6295 continue;
c5419e26
QT		 6296 if (sp->cmd_type != TYPE_SRB)
6297 continue;
9ba56b95 6298 if (sp->type != SRB_SCSI_CMD)
cf53b069 6299 continue;
2c3dfe3f 6300 sfcp = sp->fcport;
f08b7251 6301 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6302 continue;
bdf79621 6303
8f7daead
GM		 6304 if (IS_QLA82XX(ha))
6305 set_bit(FCOE_CTX_RESET_NEEDED,
6306 &vha->dpc_flags);
6307 else
6308 set_bit(ISP_ABORT_NEEDED,
e315cd28 6309 &vha->dpc_flags);
2c3dfe3f
SJ		 6310 break;
6311 }
6312 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6313 cpu_flags);
1da177e4 6314 }
1da177e4
LT		 6315 start_dpc++;
6316 }
6317
6318 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6319 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6320 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6321 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6322 "Loop down - aborting ISP.\n");
6323
8f7daead
GM		 6324 if (IS_QLA82XX(ha))
6325 set_bit(FCOE_CTX_RESET_NEEDED,
6326 &vha->dpc_flags);
6327 else
6328 set_bit(ISP_ABORT_NEEDED,
6329 &vha->dpc_flags);
1da177e4
LT		 6330 }
6331 }
7c3df132
SK		 6332 ql_dbg(ql_dbg_timer, vha, 0x600a,
6333 "Loop down - seconds remaining %d.\n",
6334 atomic_read(&vha->loop_down_timer));
1da177e4 6335 }
cefcaba6
SK		 6336 /* Check if beacon LED needs to be blinked for physical host only */
6337 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6338 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6339 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6340 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6341 start_dpc++;
6342 }
f6df144c 6343 }
6344
550bf57d 6345 /* Process any deferred work. */
9b3e0f4d
QT		 6346 if (!list_empty(&vha->work_list)) {
6347 unsigned long flags;
6348 bool q = false;
6349
6350 spin_lock_irqsave(&vha->work_lock, flags);
6351 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
6352 q = true;
6353 spin_unlock_irqrestore(&vha->work_lock, flags);
6354 if (q)
6355 queue_work(vha->hw->wq, &vha->iocb_work);
6356 }
550bf57d 6357
7401bc18
DG		 6358 /*
6359 * FC-NVME
6360 * see if the active AEN count has changed from what was last reported.
6361 */
deeae7a6
DG		 6362 if (!vha->vp_idx &&
6363 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen &&
6364 ha->zio_mode == QLA_ZIO_MODE_6) {
7401bc18 6365 ql_log(ql_log_info, vha, 0x3002,
deeae7a6
DG		 6366 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6367 ha->nvme_last_rptd_aen);
6368 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
6369 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6370 start_dpc++;
7401bc18
DG		 6371 }
6372
1da177e4 6373 /* Schedule the DPC routine if needed */
e315cd28
AC		 6374 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6375 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6376 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6377 start_dpc ||
e315cd28
AC		 6378 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6379 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6380 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6381 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6382 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6383 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6384 ql_dbg(ql_dbg_timer, vha, 0x600b,
6385 "isp_abort_needed=%d loop_resync_needed=%d "
6386 "fcport_update_needed=%d start_dpc=%d "
6387 "reset_marker_needed=%d",
6388 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6389 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6390 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6391 start_dpc,
6392 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6393 ql_dbg(ql_dbg_timer, vha, 0x600c,
6394 "beacon_blink_needed=%d isp_unrecoverable=%d "
6395 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6396 "relogin_needed=%d.\n",
7c3df132
SK		 6397 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6398 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6399 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6400 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6401 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6402 qla2xxx_wake_dpc(vha);
7c3df132 6403 }
1da177e4 6404
e315cd28 6405 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6406}
6407
5433383e
AV		 6408/* Firmware interface routines. */
6409
f73cb695 6410#define FW_BLOBS 11
5433383e
AV		 6411#define FW_ISP21XX 0
6412#define FW_ISP22XX 1
6413#define FW_ISP2300 2
6414#define FW_ISP2322 3
48c02fde 6415#define FW_ISP24XX 4
c3a2f0df 6416#define FW_ISP25XX 5
3a03eb79 6417#define FW_ISP81XX 6
a9083016 6418#define FW_ISP82XX 7
6246b8a1
GM		 6419#define FW_ISP2031 8
6420#define FW_ISP8031 9
2c5bbbb2 6421#define FW_ISP27XX 10
5433383e 6422
bb8ee499
AV		 6423#define FW_FILE_ISP21XX "ql2100_fw.bin"
6424#define FW_FILE_ISP22XX "ql2200_fw.bin"
6425#define FW_FILE_ISP2300 "ql2300_fw.bin"
6426#define FW_FILE_ISP2322 "ql2322_fw.bin"
6427#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6428#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6429#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6430#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6431#define FW_FILE_ISP2031 "ql2600_fw.bin"
6432#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6433#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 6434
bb8ee499 6435
e1e82b6f 6436static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 6437
6438static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 6439 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6440 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6441 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6442 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6443 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6444 { .name = FW_FILE_ISP25XX, },
3a03eb79 6445 { .name = FW_FILE_ISP81XX, },
a9083016 6446 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6447 { .name = FW_FILE_ISP2031, },
6448 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6449 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 6450};
6451
6452struct fw_blob *
e315cd28 6453qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6454{
e315cd28 6455 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6456 struct fw_blob *blob;
6457
5433383e
AV		 6458 if (IS_QLA2100(ha)) {
6459 blob = &qla_fw_blobs[FW_ISP21XX];
6460 } else if (IS_QLA2200(ha)) {
6461 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6462 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6463 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6464 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6465 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6466 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6467 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6468 } else if (IS_QLA25XX(ha)) {
6469 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6470 } else if (IS_QLA81XX(ha)) {
6471 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6472 } else if (IS_QLA82XX(ha)) {
6473 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6474 } else if (IS_QLA2031(ha)) {
6475 blob = &qla_fw_blobs[FW_ISP2031];
6476 } else if (IS_QLA8031(ha)) {
6477 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6478 } else if (IS_QLA27XX(ha)) {
6479 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 6480 } else {
6481 return NULL;
5433383e
AV		 6482 }
6483
e1e82b6f 6484 mutex_lock(&qla_fw_lock);
5433383e
AV		 6485 if (blob->fw)
6486 goto out;
6487
6488 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6489 ql_log(ql_log_warn, vha, 0x0063,
6490 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6491 blob->fw = NULL;
6492 blob = NULL;
6493 goto out;
6494 }
6495
6496out:
e1e82b6f 6497 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6498 return blob;
6499}
6500
6501static void
6502qla2x00_release_firmware(void)
6503{
6504 int idx;
6505
e1e82b6f 6506 mutex_lock(&qla_fw_lock);
5433383e 6507 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 6508 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 6509 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6510}
6511
14e660e6
SJ		 6512static pci_ers_result_t
6513qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6514{
85880801
AV		 6515 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6516 struct qla_hw_data *ha = vha->hw;
6517
7c3df132
SK		 6518 ql_dbg(ql_dbg_aer, vha, 0x9000,
6519 "PCI error detected, state %x.\n", state);
b9b12f73 6520
efdb5760
SC		 6521 if (!atomic_read(&pdev->enable_cnt)) {
6522 ql_log(ql_log_info, vha, 0xffff,
6523 "PCI device is disabled,state %x\n", state);
6524 return PCI_ERS_RESULT_NEED_RESET;
6525 }
6526
14e660e6
SJ		 6527 switch (state) {
6528 case pci_channel_io_normal:
85880801 6529 ha->flags.eeh_busy = 0;
c38d1baf 6530 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6531 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6532 qla2xxx_wake_dpc(vha);
6533 }
14e660e6
SJ		 6534 return PCI_ERS_RESULT_CAN_RECOVER;
6535 case pci_channel_io_frozen:
85880801 6536 ha->flags.eeh_busy = 1;
a5b36321
LC		 6537 /* For ISP82XX complete any pending mailbox cmd */
6538 if (IS_QLA82XX(ha)) {
7190575f 6539 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6540 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6541 qla82xx_clear_pending_mbx(vha);
a5b36321 6542 }
90a86fc0 6543 qla2x00_free_irqs(vha);
14e660e6 6544 pci_disable_device(pdev);
bddd2d65
LC		 6545 /* Return back all IOs */
6546 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
c38d1baf 6547 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6548 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6549 qla2xxx_wake_dpc(vha);
6550 }
14e660e6
SJ		 6551 return PCI_ERS_RESULT_NEED_RESET;
6552 case pci_channel_io_perm_failure:
85880801
AV		 6553 ha->flags.pci_channel_io_perm_failure = 1;
6554 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
c38d1baf 6555 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6556 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6557 qla2xxx_wake_dpc(vha);
6558 }
14e660e6
SJ		 6559 return PCI_ERS_RESULT_DISCONNECT;
6560 }
6561 return PCI_ERS_RESULT_NEED_RESET;
6562}
6563
6564static pci_ers_result_t
6565qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6566{
6567 int risc_paused = 0;
6568 uint32_t stat;
6569 unsigned long flags;
e315cd28
AC		 6570 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6571 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6572 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6573 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6574
bcc5b6d3
SK		 6575 if (IS_QLA82XX(ha))
6576 return PCI_ERS_RESULT_RECOVERED;
6577
14e660e6
SJ		 6578 spin_lock_irqsave(&ha->hardware_lock, flags);
6579 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6580 stat = RD_REG_DWORD(&reg->hccr);
6581 if (stat & HCCR_RISC_PAUSE)
6582 risc_paused = 1;
6583 } else if (IS_QLA23XX(ha)) {
6584 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6585 if (stat & HSR_RISC_PAUSED)
6586 risc_paused = 1;
6587 } else if (IS_FWI2_CAPABLE(ha)) {
6588 stat = RD_REG_DWORD(&reg24->host_status);
6589 if (stat & HSRX_RISC_PAUSED)
6590 risc_paused = 1;
6591 }
6592 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6593
6594 if (risc_paused) {
7c3df132
SK		 6595 ql_log(ql_log_info, base_vha, 0x9003,
6596 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6597 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6598
6599 return PCI_ERS_RESULT_NEED_RESET;
6600 } else
6601 return PCI_ERS_RESULT_RECOVERED;
6602}
6603
fa492630
SK		 6604static uint32_t
6605qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6606{
6607 uint32_t rval = QLA_FUNCTION_FAILED;
6608 uint32_t drv_active = 0;
6609 struct qla_hw_data *ha = base_vha->hw;
6610 int fn;
6611 struct pci_dev *other_pdev = NULL;
6612
7c3df132
SK		 6613 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6614 "Entered %s.\n", __func__);
a5b36321
LC		 6615
6616 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6617
6618 if (base_vha->flags.online) {
6619 /* Abort all outstanding commands,
6620 * so as to be requeued later */
6621 qla2x00_abort_isp_cleanup(base_vha);
6622 }
6623
6624
6625 fn = PCI_FUNC(ha->pdev->devfn);
6626 while (fn > 0) {
6627 fn--;
7c3df132
SK		 6628 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6629 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6630 other_pdev =
6631 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6632 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6633 fn));
6634
6635 if (!other_pdev)
6636 continue;
6637 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6638 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6639 "Found PCI func available and enable at 0x%x.\n",
6640 fn);
a5b36321
LC		 6641 pci_dev_put(other_pdev);
6642 break;
6643 }
6644 pci_dev_put(other_pdev);
6645 }
6646
6647 if (!fn) {
6648 /* Reset owner */
7c3df132
SK		 6649 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6650 "This devfn is reset owner = 0x%x.\n",
6651 ha->pdev->devfn);
a5b36321
LC		 6652 qla82xx_idc_lock(ha);
6653
6654 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6655 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6656
6657 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6658 QLA82XX_IDC_VERSION);
6659
6660 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6661 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6662 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6663
6664 qla82xx_idc_unlock(ha);
6665 /* Reset if device is not already reset
6666 * drv_active would be 0 if a reset has already been done
6667 */
6668 if (drv_active)
6669 rval = qla82xx_start_firmware(base_vha);
6670 else
6671 rval = QLA_SUCCESS;
6672 qla82xx_idc_lock(ha);
6673
6674 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6675 ql_log(ql_log_info, base_vha, 0x900b,
6676 "HW State: FAILED.\n");
a5b36321
LC		 6677 qla82xx_clear_drv_active(ha);
6678 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6679 QLA8XXX_DEV_FAILED);
a5b36321 6680 } else {
7c3df132
SK		 6681 ql_log(ql_log_info, base_vha, 0x900c,
6682 "HW State: READY.\n");
a5b36321 6683 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6684 QLA8XXX_DEV_READY);
a5b36321 6685 qla82xx_idc_unlock(ha);
7190575f 6686 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6687 rval = qla82xx_restart_isp(base_vha);
6688 qla82xx_idc_lock(ha);
6689 /* Clear driver state register */
6690 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6691 qla82xx_set_drv_active(base_vha);
6692 }
6693 qla82xx_idc_unlock(ha);
6694 } else {
7c3df132
SK		 6695 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6696 "This devfn is not reset owner = 0x%x.\n",
6697 ha->pdev->devfn);
a5b36321 6698 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6699 QLA8XXX_DEV_READY)) {
7190575f 6700 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6701 rval = qla82xx_restart_isp(base_vha);
6702 qla82xx_idc_lock(ha);
6703 qla82xx_set_drv_active(base_vha);
6704 qla82xx_idc_unlock(ha);
6705 }
6706 }
6707 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6708
6709 return rval;
6710}
6711
14e660e6
SJ		 6712static pci_ers_result_t
6713qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6714{
6715 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6716 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6717 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6718 struct rsp_que *rsp;
6719 int rc, retries = 10;
09483916 6720
7c3df132
SK		 6721 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6722 "Slot Reset.\n");
85880801 6723
90a86fc0
JC		 6724 /* Workaround: qla2xxx driver which access hardware earlier
6725 * needs error state to be pci_channel_io_online.
6726 * Otherwise mailbox command timesout.
6727 */
6728 pdev->error_state = pci_channel_io_normal;
6729
6730 pci_restore_state(pdev);
6731
8c1496bd
RL		 6732 /* pci_restore_state() clears the saved_state flag of the device
6733 * save restored state which resets saved_state flag
6734 */
6735 pci_save_state(pdev);
6736
09483916
BH		 6737 if (ha->mem_only)
6738 rc = pci_enable_device_mem(pdev);
6739 else
6740 rc = pci_enable_device(pdev);
14e660e6 6741
09483916 6742 if (rc) {
7c3df132 6743 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6744 "Can't re-enable PCI device after reset.\n");
a5b36321 6745 goto exit_slot_reset;
14e660e6 6746 }
14e660e6 6747
90a86fc0
JC		 6748 rsp = ha->rsp_q_map[0];
6749 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6750 goto exit_slot_reset;
90a86fc0 6751
e315cd28 6752 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6753 goto exit_slot_reset;
6754
6755 if (IS_QLA82XX(ha)) {
6756 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6757 ret = PCI_ERS_RESULT_RECOVERED;
6758 goto exit_slot_reset;
6759 } else
6760 goto exit_slot_reset;
6761 }
14e660e6 6762
90a86fc0
JC		 6763 while (ha->flags.mbox_busy && retries--)
6764 msleep(1000);
85880801 6765
e315cd28 6766 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6767 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6768 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6769 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6770
90a86fc0 6771
a5b36321 6772exit_slot_reset:
7c3df132
SK		 6773 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6774 "slot_reset return %x.\n", ret);
85880801 6775
14e660e6
SJ		 6776 return ret;
6777}
6778
6779static void
6780qla2xxx_pci_resume(struct pci_dev *pdev)
6781{
e315cd28
AC		 6782 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6783 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6784 int ret;
6785
7c3df132
SK		 6786 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6787 "pci_resume.\n");
85880801 6788
e315cd28 6789 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6790 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6791 ql_log(ql_log_fatal, base_vha, 0x9002,
6792 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6793 }
85880801 6794
3e46f031
LC		 6795 pci_cleanup_aer_uncorrect_error_status(pdev);
6796
85880801 6797 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6798}
6799
5601236b
MH		 6800static int qla2xxx_map_queues(struct Scsi_Host *shost)
6801{
d68b850e 6802 int rc;
5601236b
MH		 6803 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6804
d68b850e
QT		 6805 if (USER_CTRL_IRQ(vha->hw))
6806 rc = blk_mq_map_queues(&shost->tag_set);
6807 else
6808 rc = blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6809 return rc;
5601236b
MH		 6810}
6811
a55b2d21 6812static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6813 .error_detected = qla2xxx_pci_error_detected,
6814 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6815 .slot_reset = qla2xxx_pci_slot_reset,
6816 .resume = qla2xxx_pci_resume,
6817};
6818
5433383e 6819static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6820 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6821 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6822 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6823 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6824 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6825 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6826 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6827 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6828 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6829 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6830 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6831 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6832 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6833 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6834 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6835 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6836 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6837 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6838 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6839 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6840 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6841 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6842 { 0 },
6843};
6844MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6845
fca29703 6846static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6847 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6848 .driver = {
6849 .owner = THIS_MODULE,
6850 },
fca29703 6851 .id_table = qla2xxx_pci_tbl,
7ee61397 6852 .probe = qla2x00_probe_one,
4c993f76 6853 .remove = qla2x00_remove_one,
e30d1756 6854 .shutdown = qla2x00_shutdown,
14e660e6 6855 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6856};
6857
75ef9de1 6858static const struct file_operations apidev_fops = {
6a03b4cd 6859 .owner = THIS_MODULE,
6038f373 6860 .llseek = noop_llseek,
6a03b4cd
HZ		 6861};
6862
1da177e4
LT		 6863/**
6864 * qla2x00_module_init - Module initialization.
6865 **/
6866static int __init
6867qla2x00_module_init(void)
6868{
fca29703
AV		 6869 int ret = 0;
6870
1da177e4 6871 /* Allocate cache for SRBs. */
354d6b21 6872 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6873 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6874 if (srb_cachep == NULL) {
7c3df132
SK		 6875 ql_log(ql_log_fatal, NULL, 0x0001,
6876 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6877 return -ENOMEM;
6878 }
6879
2d70c103
NB		 6880 /* Initialize target kmem_cache and mem_pools */
6881 ret = qlt_init();
6882 if (ret < 0) {
6883 kmem_cache_destroy(srb_cachep);
6884 return ret;
6885 } else if (ret > 0) {
6886 /*
6887 * If initiator mode is explictly disabled by qlt_init(),
6888 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6889 * performing scsi_scan_target() during LOOP UP event.
6890 */
6891 qla2xxx_transport_functions.disable_target_scan = 1;
6892 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6893 }
6894
1da177e4
LT		 6895 /* Derive version string. */
6896 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6897 if (ql2xextended_error_logging)
0181944f 6898 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 6899 if (ql2xextended_error_logging == 1)
6900 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 6901
1c97a12a
AV		 6902 qla2xxx_transport_template =
6903 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6904 if (!qla2xxx_transport_template) {
6905 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6906 ql_log(ql_log_fatal, NULL, 0x0002,
6907 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6908 qlt_exit();
1da177e4 6909 return -ENODEV;
2c3dfe3f 6910 }
6a03b4cd
HZ		 6911
6912 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6913 if (apidev_major < 0) {
7c3df132
SK		 6914 ql_log(ql_log_fatal, NULL, 0x0003,
6915 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6916 }
6917
2c3dfe3f
SJ		 6918 qla2xxx_transport_vport_template =
6919 fc_attach_transport(&qla2xxx_transport_vport_functions);
6920 if (!qla2xxx_transport_vport_template) {
6921 kmem_cache_destroy(srb_cachep);
2d70c103 6922 qlt_exit();
2c3dfe3f 6923 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6924 ql_log(ql_log_fatal, NULL, 0x0004,
6925 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6926 return -ENODEV;
2c3dfe3f 6927 }
7c3df132
SK		 6928 ql_log(ql_log_info, NULL, 0x0005,
6929 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6930 qla2x00_version_str);
7ee61397 6931 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6932 if (ret) {
6933 kmem_cache_destroy(srb_cachep);
2d70c103 6934 qlt_exit();
fca29703 6935 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6936 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6937 ql_log(ql_log_fatal, NULL, 0x0006,
6938 "pci_register_driver failed...ret=%d Failing load!.\n",
6939 ret);
fca29703
AV		 6940 }
6941 return ret;
1da177e4
LT		 6942}
6943
6944/**
6945 * qla2x00_module_exit - Module cleanup.
6946 **/
6947static void __exit
6948qla2x00_module_exit(void)
6949{
6a03b4cd 6950 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6951 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6952 qla2x00_release_firmware();
354d6b21 6953 kmem_cache_destroy(srb_cachep);
2d70c103 6954 qlt_exit();
a9083016
GM		 6955 if (ctx_cachep)
6956 kmem_cache_destroy(ctx_cachep);
1da177e4 6957 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6958 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6959}
6960
6961module_init(qla2x00_module_init);
6962module_exit(qla2x00_module_exit);
6963
6964MODULE_AUTHOR("QLogic Corporation");
6965MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6966MODULE_LICENSE("GPL");
6967MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6968MODULE_FIRMWARE(FW_FILE_ISP21XX);
6969MODULE_FIRMWARE(FW_FILE_ISP22XX);
6970MODULE_FIRMWARE(FW_FILE_ISP2300);
6971MODULE_FIRMWARE(FW_FILE_ISP2322);
6972MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6973MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)