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[SCSI] qla2xxx: Stats should be different from physical and virtual ports
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
07e264b7 3 * Copyright (c) 2003-2011 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16
17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
22/*
23 * Driver version
24 */
25char qla2x00_version_str[40];
26
6a03b4cd
HZ		 27static int apidev_major;
28
1da177e4
LT		 29/*
30 * SRB allocation cache
31 */
e18b890b 32static struct kmem_cache *srb_cachep;
1da177e4 33
a9083016
GM		 34/*
35 * CT6 CTX allocation cache
36 */
37static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 38/*
39 * error level for logging
40 */
41int ql_errlev = ql_log_all;
a9083016 42
1da177e4 43int ql2xlogintimeout = 20;
f2019cb1 44module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 45MODULE_PARM_DESC(ql2xlogintimeout,
46 "Login timeout value in seconds.");
47
a7b61842 48int qlport_down_retry;
f2019cb1 49module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 50MODULE_PARM_DESC(qlport_down_retry,
900d9f98 51 "Maximum number of command retries to a port that returns "
1da177e4
LT		 52 "a PORT-DOWN status.");
53
1da177e4
LT		 54int ql2xplogiabsentdevice;
55module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
56MODULE_PARM_DESC(ql2xplogiabsentdevice,
57 "Option to enable PLOGI to devices that are not present after "
900d9f98 58 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 59 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
60
1da177e4 61int ql2xloginretrycount = 0;
f2019cb1 62module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 63MODULE_PARM_DESC(ql2xloginretrycount,
64 "Specify an alternate value for the NVRAM login retry count.");
65
a7a167bf 66int ql2xallocfwdump = 1;
f2019cb1 67module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 68MODULE_PARM_DESC(ql2xallocfwdump,
69 "Option to enable allocation of memory for a firmware dump "
70 "during HBA initialization. Memory allocation requirements "
71 "vary by ISP type. Default is 1 - allocate memory.");
72
11010fec 73int ql2xextended_error_logging;
27d94035 74module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 75MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 76 "Option to enable extended error logging,\n"
77 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
78 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
79 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
80 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
81 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
82 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
83 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
84 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
85 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 86 "\t\t0x1e400000 - Preferred value for capturing essential "
87 "debug information (equivalent to old "
88 "ql2xextended_error_logging=1).\n"
3ce8866c 89 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 90
a9083016 91int ql2xshiftctondsd = 6;
f2019cb1 92module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 93MODULE_PARM_DESC(ql2xshiftctondsd,
94 "Set to control shifting of command type processing "
95 "based on total number of SG elements.");
96
1da177e4
LT		 97static void qla2x00_free_device(scsi_qla_host_t *);
98
7e47e5ca 99int ql2xfdmienable=1;
f2019cb1 100module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 101MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 102 "Enables FDMI registrations. "
103 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 104
df7baa50
AV		 105#define MAX_Q_DEPTH 32
106static int ql2xmaxqdepth = MAX_Q_DEPTH;
107module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
108MODULE_PARM_DESC(ql2xmaxqdepth,
109 "Maximum queue depth to report for target devices.");
110
bad75002 111/* Do not change the value of this after module load */
8cb2049c 112int ql2xenabledif = 0;
bad75002
AE		 113module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
114MODULE_PARM_DESC(ql2xenabledif,
115 " Enable T10-CRC-DIF "
8cb2049c
AE		 116 " Default is 0 - No DIF Support. 1 - Enable it"
117 ", 2 - Enable DIF for all types, except Type 0.");
bad75002 118
8cb2049c 119int ql2xenablehba_err_chk = 2;
bad75002
AE		 120module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
121MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c
AE		 122 " Enable T10-CRC-DIF Error isolation by HBA:\n"
123 " Default is 1.\n"
124 " 0 -- Error isolation disabled\n"
125 " 1 -- Error isolation enabled only for DIX Type 0\n"
126 " 2 -- Error isolation enabled for all Types\n");
bad75002 127
e5896bd5 128int ql2xiidmaenable=1;
f2019cb1 129module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 130MODULE_PARM_DESC(ql2xiidmaenable,
131 "Enables iIDMA settings "
132 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
133
73208dfd 134int ql2xmaxqueues = 1;
f2019cb1 135module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 136MODULE_PARM_DESC(ql2xmaxqueues,
137 "Enables MQ settings "
ae68230c
JP		 138 "Default is 1 for single queue. Set it to number "
139 "of queues in MQ mode.");
68ca949c
AC		 140
141int ql2xmultique_tag;
f2019cb1 142module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 143MODULE_PARM_DESC(ql2xmultique_tag,
144 "Enables CPU affinity settings for the driver "
145 "Default is 0 for no affinity of request and response IO. "
146 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 147
148int ql2xfwloadbin;
86e45bf6 149module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 150MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 151 "Option to specify location from which to load ISP firmware:.\n"
152 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 153 " interface.\n"
154 " 1 -- load firmware from flash.\n"
155 " 0 -- use default semantics.\n");
156
ae97c91e 157int ql2xetsenable;
f2019cb1 158module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 159MODULE_PARM_DESC(ql2xetsenable,
160 "Enables firmware ETS burst."
161 "Default is 0 - skip ETS enablement.");
162
6907869d 163int ql2xdbwr = 1;
86e45bf6 164module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 165MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 166 "Option to specify scheme for request queue posting.\n"
167 " 0 -- Regular doorbell.\n"
168 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 169
f4c496c1 170int ql2xtargetreset = 1;
f2019cb1 171module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 172MODULE_PARM_DESC(ql2xtargetreset,
173 "Enable target reset."
174 "Default is 1 - use hw defaults.");
175
4da26e16 176int ql2xgffidenable;
f2019cb1 177module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 178MODULE_PARM_DESC(ql2xgffidenable,
179 "Enables GFF_ID checks of port type. "
180 "Default is 0 - Do not use GFF_ID information.");
a9083016 181
3822263e 182int ql2xasynctmfenable;
f2019cb1 183module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 184MODULE_PARM_DESC(ql2xasynctmfenable,
185 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
186 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 187
188int ql2xdontresethba;
86e45bf6 189module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 190MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 191 "Option to specify reset behaviour.\n"
192 " 0 (Default) -- Reset on failure.\n"
193 " 1 -- Do not reset on failure.\n");
ed0de87c 194
82515920
AV		 195uint ql2xmaxlun = MAX_LUNS;
196module_param(ql2xmaxlun, uint, S_IRUGO);
197MODULE_PARM_DESC(ql2xmaxlun,
198 "Defines the maximum LU number to register with the SCSI "
199 "midlayer. Default is 65535.");
200
08de2844
GM		 201int ql2xmdcapmask = 0x1F;
202module_param(ql2xmdcapmask, int, S_IRUGO);
203MODULE_PARM_DESC(ql2xmdcapmask,
204 "Set the Minidump driver capture mask level. "
6e96fa7b 205 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 206
3aadff35 207int ql2xmdenable = 1;
08de2844
GM		 208module_param(ql2xmdenable, int, S_IRUGO);
209MODULE_PARM_DESC(ql2xmdenable,
210 "Enable/disable MiniDump. "
3aadff35
GM		 211 "0 - MiniDump disabled. "
212 "1 (Default) - MiniDump enabled.");
08de2844 213
1da177e4 214/*
fa2a1ce5 215 * SCSI host template entry points
1da177e4
LT		 216 */
217static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 218static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 219static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
220static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 221static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 222static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 223static int qla2xxx_eh_abort(struct scsi_cmnd *);
224static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 225static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 226static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
227static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 228
e881a172 229static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7
AV		 230static int qla2x00_change_queue_type(struct scsi_device *, int);
231
a5326f86 232struct scsi_host_template qla2xxx_driver_template = {
1da177e4 233 .module = THIS_MODULE,
cb63067a 234 .name = QLA2XXX_DRIVER_NAME,
a5326f86 235 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 236
237 .eh_abort_handler = qla2xxx_eh_abort,
238 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 239 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 240 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
241 .eh_host_reset_handler = qla2xxx_eh_host_reset,
242
243 .slave_configure = qla2xxx_slave_configure,
244
245 .slave_alloc = qla2xxx_slave_alloc,
246 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 247 .scan_finished = qla2xxx_scan_finished,
248 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 249 .change_queue_depth = qla2x00_change_queue_depth,
250 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 251 .this_id = -1,
252 .cmd_per_lun = 3,
253 .use_clustering = ENABLE_CLUSTERING,
254 .sg_tablesize = SG_ALL,
255
256 .max_sectors = 0xFFFF,
afb046e2 257 .shost_attrs = qla2x00_host_attrs,
fca29703
AV		 258};
259
1da177e4 260static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 261struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 262
1da177e4
LT		 263/* TODO Convert to inlines
264 *
265 * Timer routines
266 */
1da177e4 267
2c3dfe3f 268__inline__ void
e315cd28 269qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 270{
e315cd28
AC		 271 init_timer(&vha->timer);
272 vha->timer.expires = jiffies + interval * HZ;
273 vha->timer.data = (unsigned long)vha;
274 vha->timer.function = (void (*)(unsigned long))func;
275 add_timer(&vha->timer);
276 vha->timer_active = 1;
1da177e4
LT		 277}
278
279static inline void
e315cd28 280qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 281{
a9083016 282 /* Currently used for 82XX only. */
7c3df132
SK		 283 if (vha->device_flags & DFLG_DEV_FAILED) {
284 ql_dbg(ql_dbg_timer, vha, 0x600d,
285 "Device in a failed state, returning.\n");
a9083016 286 return;
7c3df132 287 }
a9083016 288
e315cd28 289 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 290}
291
a824ebb3 292static __inline__ void
e315cd28 293qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 294{
e315cd28
AC		 295 del_timer_sync(&vha->timer);
296 vha->timer_active = 0;
1da177e4
LT		 297}
298
1da177e4
LT		 299static int qla2x00_do_dpc(void *data);
300
301static void qla2x00_rst_aen(scsi_qla_host_t *);
302
73208dfd
AC		 303static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
304 struct req_que **, struct rsp_que **);
e30d1756 305static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 306static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 307
1da177e4 308/* -------------------------------------------------------------------------- */
9a347ff4
CD		 309static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
310 struct rsp_que *rsp)
73208dfd 311{
7c3df132 312 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 313 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 314 GFP_KERNEL);
315 if (!ha->req_q_map) {
7c3df132
SK		 316 ql_log(ql_log_fatal, vha, 0x003b,
317 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 318 goto fail_req_map;
319 }
320
2afa19a9 321 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 322 GFP_KERNEL);
323 if (!ha->rsp_q_map) {
7c3df132
SK		 324 ql_log(ql_log_fatal, vha, 0x003c,
325 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 326 goto fail_rsp_map;
327 }
9a347ff4
CD		 328 /*
329 * Make sure we record at least the request and response queue zero in
330 * case we need to free them if part of the probe fails.
331 */
332 ha->rsp_q_map[0] = rsp;
333 ha->req_q_map[0] = req;
73208dfd
AC		 334 set_bit(0, ha->rsp_qid_map);
335 set_bit(0, ha->req_qid_map);
336 return 1;
337
338fail_rsp_map:
339 kfree(ha->req_q_map);
340 ha->req_q_map = NULL;
341fail_req_map:
342 return -ENOMEM;
343}
344
2afa19a9 345static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 346{
73208dfd
AC		 347 if (req && req->ring)
348 dma_free_coherent(&ha->pdev->dev,
349 (req->length + 1) * sizeof(request_t),
350 req->ring, req->dma);
351
352 kfree(req);
353 req = NULL;
354}
355
2afa19a9
AC		 356static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
357{
358 if (rsp && rsp->ring)
359 dma_free_coherent(&ha->pdev->dev,
360 (rsp->length + 1) * sizeof(response_t),
361 rsp->ring, rsp->dma);
362
363 kfree(rsp);
364 rsp = NULL;
365}
366
73208dfd
AC		 367static void qla2x00_free_queues(struct qla_hw_data *ha)
368{
369 struct req_que *req;
370 struct rsp_que *rsp;
371 int cnt;
372
2afa19a9 373 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 374 req = ha->req_q_map[cnt];
2afa19a9 375 qla2x00_free_req_que(ha, req);
73208dfd 376 }
73208dfd
AC		 377 kfree(ha->req_q_map);
378 ha->req_q_map = NULL;
2afa19a9
AC		 379
380 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
381 rsp = ha->rsp_q_map[cnt];
382 qla2x00_free_rsp_que(ha, rsp);
383 }
384 kfree(ha->rsp_q_map);
385 ha->rsp_q_map = NULL;
73208dfd
AC		 386}
387
68ca949c
AC		 388static int qla25xx_setup_mode(struct scsi_qla_host *vha)
389{
390 uint16_t options = 0;
391 int ques, req, ret;
392 struct qla_hw_data *ha = vha->hw;
393
7163ea81 394 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 395 ql_log(ql_log_warn, vha, 0x00d8,
396 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 397 goto fail;
398 }
68ca949c 399 if (ql2xmultique_tag) {
68ca949c
AC		 400 /* create a request queue for IO */
401 options |= BIT_7;
402 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
403 QLA_DEFAULT_QUE_QOS);
404 if (!req) {
7c3df132
SK		 405 ql_log(ql_log_warn, vha, 0x00e0,
406 "Failed to create request queue.\n");
68ca949c
AC		 407 goto fail;
408 }
278274d5 409 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 410 vha->req = ha->req_q_map[req];
411 options |= BIT_1;
412 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
413 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
414 if (!ret) {
7c3df132
SK		 415 ql_log(ql_log_warn, vha, 0x00e8,
416 "Failed to create response queue.\n");
68ca949c
AC		 417 goto fail2;
418 }
419 }
7163ea81 420 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 421 ql_dbg(ql_dbg_multiq, vha, 0xc007,
422 "CPU affinity mode enalbed, "
423 "no. of response queues:%d no. of request queues:%d.\n",
424 ha->max_rsp_queues, ha->max_req_queues);
425 ql_dbg(ql_dbg_init, vha, 0x00e9,
426 "CPU affinity mode enalbed, "
427 "no. of response queues:%d no. of request queues:%d.\n",
428 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 429 }
430 return 0;
431fail2:
432 qla25xx_delete_queues(vha);
7163ea81
AC		 433 destroy_workqueue(ha->wq);
434 ha->wq = NULL;
0cd33fcf 435 vha->req = ha->req_q_map[0];
68ca949c
AC		 436fail:
437 ha->mqenable = 0;
7163ea81
AC		 438 kfree(ha->req_q_map);
439 kfree(ha->rsp_q_map);
440 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 441 return 1;
442}
443
1da177e4 444static char *
e315cd28 445qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 446{
e315cd28 447 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 448 static char *pci_bus_modes[] = {
449 "33", "66", "100", "133",
450 };
451 uint16_t pci_bus;
452
453 strcpy(str, "PCI");
454 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
455 if (pci_bus) {
456 strcat(str, "-X (");
457 strcat(str, pci_bus_modes[pci_bus]);
458 } else {
459 pci_bus = (ha->pci_attr & BIT_8) >> 8;
460 strcat(str, " (");
461 strcat(str, pci_bus_modes[pci_bus]);
462 }
463 strcat(str, " MHz)");
464
465 return (str);
466}
467
fca29703 468static char *
e315cd28 469qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 470{
471 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 472 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 473 uint32_t pci_bus;
474 int pcie_reg;
475
476 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
477 if (pcie_reg) {
478 char lwstr[6];
479 uint16_t pcie_lstat, lspeed, lwidth;
480
481 pcie_reg += 0x12;
482 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
483 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
484 lwidth = (pcie_lstat &
485 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
486
487 strcpy(str, "PCIe (");
488 if (lspeed == 1)
c87a0d8c 489 strcat(str, "2.5GT/s ");
c3a2f0df 490 else if (lspeed == 2)
c87a0d8c 491 strcat(str, "5.0GT/s ");
fca29703
AV		 492 else
493 strcat(str, "<unknown> ");
494 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
495 strcat(str, lwstr);
496
497 return str;
498 }
499
500 strcpy(str, "PCI");
501 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
502 if (pci_bus == 0 || pci_bus == 8) {
503 strcat(str, " (");
504 strcat(str, pci_bus_modes[pci_bus >> 3]);
505 } else {
506 strcat(str, "-X ");
507 if (pci_bus & BIT_2)
508 strcat(str, "Mode 2");
509 else
510 strcat(str, "Mode 1");
511 strcat(str, " (");
512 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
513 }
514 strcat(str, " MHz)");
515
516 return str;
517}
518
e5f82ab8 519static char *
e315cd28 520qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 521{
522 char un_str[10];
e315cd28 523 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 524
1da177e4
LT		 525 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
526 ha->fw_minor_version,
527 ha->fw_subminor_version);
528
529 if (ha->fw_attributes & BIT_9) {
530 strcat(str, "FLX");
531 return (str);
532 }
533
534 switch (ha->fw_attributes & 0xFF) {
535 case 0x7:
536 strcat(str, "EF");
537 break;
538 case 0x17:
539 strcat(str, "TP");
540 break;
541 case 0x37:
542 strcat(str, "IP");
543 break;
544 case 0x77:
545 strcat(str, "VI");
546 break;
547 default:
548 sprintf(un_str, "(%x)", ha->fw_attributes);
549 strcat(str, un_str);
550 break;
551 }
552 if (ha->fw_attributes & 0x100)
553 strcat(str, "X");
554
555 return (str);
556}
557
e5f82ab8 558static char *
e315cd28 559qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 560{
e315cd28 561 struct qla_hw_data *ha = vha->hw;
f0883ac6 562
3a03eb79
AV		 563 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
564 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 565 return str;
fca29703
AV		 566}
567
9ba56b95
GM		 568void
569qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 570{
9ba56b95
GM		 571 srb_t *sp = (srb_t *)ptr;
572 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
573 struct qla_hw_data *ha = sp->fcport->vha->hw;
574 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 575
9ba56b95
GM		 576 if (sp->flags & SRB_DMA_VALID) {
577 scsi_dma_unmap(cmd);
578 sp->flags &= ~SRB_DMA_VALID;
7c3df132 579 }
fca29703 580
9ba56b95
GM		 581 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
582 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
583 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
584 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
585 }
586
587 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
588 /* List assured to be having elements */
589 qla2x00_clean_dsd_pool(ha, sp);
590 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
591 }
592
593 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
594 dma_pool_free(ha->dl_dma_pool, ctx,
595 ((struct crc_context *)ctx)->crc_ctx_dma);
596 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
597 }
598
599 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
600 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 601
9ba56b95
GM		 602 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
603 ctx1->fcp_cmnd_dma);
604 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
605 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
606 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
607 mempool_free(ctx1, ha->ctx_mempool);
608 ctx1 = NULL;
609 }
610
611 CMD_SP(cmd) = NULL;
612 mempool_free(sp, ha->srb_mempool);
613}
614
615static void
616qla2x00_sp_compl(void *data, void *ptr, int res)
617{
618 struct qla_hw_data *ha = (struct qla_hw_data *)data;
619 srb_t *sp = (srb_t *)ptr;
620 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
621
622 cmd->result = res;
623
624 if (atomic_read(&sp->ref_count) == 0) {
625 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
626 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
627 sp, GET_CMD_SP(sp));
628 if (ql2xextended_error_logging & ql_dbg_io)
629 BUG();
630 return;
631 }
632 if (!atomic_dec_and_test(&sp->ref_count))
633 return;
634
635 qla2x00_sp_free_dma(ha, sp);
636 cmd->scsi_done(cmd);
fca29703
AV		 637}
638
1da177e4 639static int
f5e3e40b 640qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 641{
134ae078 642 scsi_qla_host_t *vha = shost_priv(host);
fca29703 643 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 644 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 645 struct qla_hw_data *ha = vha->hw;
646 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 647 srb_t *sp;
648 int rval;
649
85880801 650 if (ha->flags.eeh_busy) {
7c3df132 651 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 652 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 653 "PCI Channel IO permanent failure, exiting "
654 "cmd=%p.\n", cmd);
b9b12f73 655 cmd->result = DID_NO_CONNECT << 16;
7c3df132 656 } else {
5f28d2d7 657 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 658 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 659 cmd->result = DID_REQUEUE << 16;
7c3df132 660 }
14e660e6
SJ		 661 goto qc24_fail_command;
662 }
663
19a7b4ae
JSEC		 664 rval = fc_remote_port_chkready(rport);
665 if (rval) {
666 cmd->result = rval;
5f28d2d7 667 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 668 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
669 cmd, rval);
fca29703
AV		 670 goto qc24_fail_command;
671 }
672
bad75002
AE		 673 if (!vha->flags.difdix_supported &&
674 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 675 ql_dbg(ql_dbg_io, vha, 0x3004,
676 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
677 cmd);
bad75002
AE		 678 cmd->result = DID_NO_CONNECT << 16;
679 goto qc24_fail_command;
680 }
aa651be8
CD		 681
682 if (!fcport) {
683 cmd->result = DID_NO_CONNECT << 16;
684 goto qc24_fail_command;
685 }
686
fca29703
AV		 687 if (atomic_read(&fcport->state) != FCS_ONLINE) {
688 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 689 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 690 ql_dbg(ql_dbg_io, vha, 0x3005,
691 "Returning DNC, fcport_state=%d loop_state=%d.\n",
692 atomic_read(&fcport->state),
693 atomic_read(&base_vha->loop_state));
fca29703
AV		 694 cmd->result = DID_NO_CONNECT << 16;
695 goto qc24_fail_command;
696 }
7b594131 697 goto qc24_target_busy;
fca29703
AV		 698 }
699
9ba56b95 700 sp = qla2x00_get_sp(base_vha, fcport, GFP_ATOMIC);
fca29703 701 if (!sp)
f5e3e40b 702 goto qc24_host_busy;
fca29703 703
9ba56b95
GM		 704 sp->u.scmd.cmd = cmd;
705 sp->type = SRB_SCSI_CMD;
706 atomic_set(&sp->ref_count, 1);
707 CMD_SP(cmd) = (void *)sp;
708 sp->free = qla2x00_sp_free_dma;
709 sp->done = qla2x00_sp_compl;
710
e315cd28 711 rval = ha->isp_ops->start_scsi(sp);
7c3df132
SK		 712 if (rval != QLA_SUCCESS) {
713 ql_dbg(ql_dbg_io, vha, 0x3013,
714 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 715 goto qc24_host_busy_free_sp;
7c3df132 716 }
fca29703 717
fca29703
AV		 718 return 0;
719
720qc24_host_busy_free_sp:
9ba56b95 721 qla2x00_sp_free_dma(ha, sp);
fca29703 722
f5e3e40b 723qc24_host_busy:
fca29703
AV		 724 return SCSI_MLQUEUE_HOST_BUSY;
725
7b594131
MC		 726qc24_target_busy:
727 return SCSI_MLQUEUE_TARGET_BUSY;
728
fca29703 729qc24_fail_command:
f5e3e40b 730 cmd->scsi_done(cmd);
fca29703
AV		 731
732 return 0;
733}
734
1da177e4
LT		 735/*
736 * qla2x00_eh_wait_on_command
737 * Waits for the command to be returned by the Firmware for some
738 * max time.
739 *
740 * Input:
1da177e4 741 * cmd = Scsi Command to wait on.
1da177e4
LT		 742 *
743 * Return:
744 * Not Found : 0
745 * Found : 1
746 */
747static int
e315cd28 748qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 749{
fe74c71f
AV		 750#define ABORT_POLLING_PERIOD 1000
751#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 752 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 753 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
754 struct qla_hw_data *ha = vha->hw;
f4f051eb 755 int ret = QLA_SUCCESS;
1da177e4 756
85880801 757 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 758 ql_dbg(ql_dbg_taskm, vha, 0x8005,
759 "Return:eh_wait.\n");
85880801
AV		 760 return ret;
761 }
762
d970432c 763 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 764 msleep(ABORT_POLLING_PERIOD);
f4f051eb 765 }
766 if (CMD_SP(cmd))
767 ret = QLA_FUNCTION_FAILED;
1da177e4 768
f4f051eb 769 return ret;
1da177e4
LT		 770}
771
772/*
773 * qla2x00_wait_for_hba_online
fa2a1ce5 774 * Wait till the HBA is online after going through
1da177e4
LT		 775 * <= MAX_RETRIES_OF_ISP_ABORT or
776 * finally HBA is disabled ie marked offline
777 *
778 * Input:
779 * ha - pointer to host adapter structure
fa2a1ce5
AV		 780 *
781 * Note:
1da177e4
LT		 782 * Does context switching-Release SPIN_LOCK
783 * (if any) before calling this routine.
784 *
785 * Return:
786 * Success (Adapter is online) : 0
787 * Failed (Adapter is offline/disabled) : 1
788 */
854165f4 789int
e315cd28 790qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 791{
fca29703
AV		 792 int return_status;
793 unsigned long wait_online;
e315cd28
AC		 794 struct qla_hw_data *ha = vha->hw;
795 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 796
fa2a1ce5 797 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 798 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
799 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
800 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
801 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 802
803 msleep(1000);
804 }
e315cd28 805 if (base_vha->flags.online)
fa2a1ce5 806 return_status = QLA_SUCCESS;
1da177e4
LT		 807 else
808 return_status = QLA_FUNCTION_FAILED;
809
1da177e4
LT		 810 return (return_status);
811}
812
86fbee86
LC		 813/*
814 * qla2x00_wait_for_reset_ready
815 * Wait till the HBA is online after going through
816 * <= MAX_RETRIES_OF_ISP_ABORT or
817 * finally HBA is disabled ie marked offline or flash
818 * operations are in progress.
819 *
820 * Input:
821 * ha - pointer to host adapter structure
822 *
823 * Note:
824 * Does context switching-Release SPIN_LOCK
825 * (if any) before calling this routine.
826 *
827 * Return:
828 * Success (Adapter is online/no flash ops) : 0
829 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
830 */
3dbe756a 831static int
86fbee86
LC		 832qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
833{
834 int return_status;
835 unsigned long wait_online;
836 struct qla_hw_data *ha = vha->hw;
837 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
838
839 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
840 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
841 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
842 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
843 ha->optrom_state != QLA_SWAITING ||
844 ha->dpc_active) && time_before(jiffies, wait_online))
845 msleep(1000);
846
847 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
848 return_status = QLA_SUCCESS;
849 else
850 return_status = QLA_FUNCTION_FAILED;
851
7c3df132
SK		 852 ql_dbg(ql_dbg_taskm, vha, 0x8019,
853 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 854
855 return return_status;
856}
857
2533cf67
LC		 858int
859qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
860{
861 int return_status;
862 unsigned long wait_reset;
863 struct qla_hw_data *ha = vha->hw;
864 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
865
866 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
867 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
868 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
869 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
870 ha->dpc_active) && time_before(jiffies, wait_reset)) {
871
872 msleep(1000);
873
874 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
875 ha->flags.chip_reset_done)
876 break;
877 }
878 if (ha->flags.chip_reset_done)
879 return_status = QLA_SUCCESS;
880 else
881 return_status = QLA_FUNCTION_FAILED;
882
883 return return_status;
884}
885
083a469d
GM		 886static void
887sp_get(struct srb *sp)
888{
889 atomic_inc(&sp->ref_count);
890}
891
1da177e4
LT		 892/**************************************************************************
893* qla2xxx_eh_abort
894*
895* Description:
896* The abort function will abort the specified command.
897*
898* Input:
899* cmd = Linux SCSI command packet to be aborted.
900*
901* Returns:
902* Either SUCCESS or FAILED.
903*
904* Note:
2ea00202 905* Only return FAILED if command not returned by firmware.
1da177e4 906**************************************************************************/
e5f82ab8 907static int
1da177e4
LT		 908qla2xxx_eh_abort(struct scsi_cmnd *cmd)
909{
e315cd28 910 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 911 srb_t *sp;
4e98d3b8 912 int ret;
f4f051eb 913 unsigned int id, lun;
18e144d3 914 unsigned long flags;
2ea00202 915 int wait = 0;
e315cd28 916 struct qla_hw_data *ha = vha->hw;
1da177e4 917
f4f051eb 918 if (!CMD_SP(cmd))
2ea00202 919 return SUCCESS;
1da177e4 920
4e98d3b8
AV		 921 ret = fc_block_scsi_eh(cmd);
922 if (ret != 0)
923 return ret;
924 ret = SUCCESS;
925
f4f051eb 926 id = cmd->device->id;
927 lun = cmd->device->lun;
1da177e4 928
e315cd28 929 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 930 sp = (srb_t *) CMD_SP(cmd);
931 if (!sp) {
932 spin_unlock_irqrestore(&ha->hardware_lock, flags);
933 return SUCCESS;
934 }
1da177e4 935
7c3df132 936 ql_dbg(ql_dbg_taskm, vha, 0x8002,
cfb0919c
CD		 937 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
938 vha->host_no, id, lun, sp, cmd);
17d98630 939
170babc3
MC		 940 /* Get a reference to the sp and drop the lock.*/
941 sp_get(sp);
083a469d 942
e315cd28 943 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 944 if (ha->isp_ops->abort_command(sp)) {
a55aac79 945 ret = FAILED;
7c3df132 946 ql_dbg(ql_dbg_taskm, vha, 0x8003,
cfb0919c 947 "Abort command mbx failed cmd=%p.\n", cmd);
170babc3 948 } else {
7c3df132 949 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 950 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 951 wait = 1;
952 }
75942064
SK		 953
954 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 955 sp->done(ha, sp, 0);
75942064 956 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 957
bc91ade9
CD		 958 /* Did the command return during mailbox execution? */
959 if (ret == FAILED && !CMD_SP(cmd))
960 ret = SUCCESS;
961
f4f051eb 962 /* Wait for the command to be returned. */
2ea00202 963 if (wait) {
e315cd28 964 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 965 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 966 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 967 ret = FAILED;
f4f051eb 968 }
1da177e4 969 }
1da177e4 970
7c3df132 971 ql_log(ql_log_info, vha, 0x801c,
cfb0919c
CD		 972 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
973 vha->host_no, id, lun, wait, ret);
1da177e4 974
f4f051eb 975 return ret;
976}
1da177e4 977
4d78c973 978int
e315cd28 979qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 980 unsigned int l, enum nexus_wait_type type)
f4f051eb 981{
17d98630 982 int cnt, match, status;
18e144d3 983 unsigned long flags;
e315cd28 984 struct qla_hw_data *ha = vha->hw;
73208dfd 985 struct req_que *req;
4d78c973 986 srb_t *sp;
9ba56b95 987 struct scsi_cmnd *cmd;
1da177e4 988
523ec773 989 status = QLA_SUCCESS;
17d98630 990
e315cd28 991 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 992 req = vha->req;
17d98630
AC		 993 for (cnt = 1; status == QLA_SUCCESS &&
994 cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
995 sp = req->outstanding_cmds[cnt];
996 if (!sp)
523ec773 997 continue;
9ba56b95 998 if (sp->type != SRB_SCSI_CMD)
cf53b069 999 continue;
17d98630
AC		 1000 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1001 continue;
1002 match = 0;
9ba56b95 1003 cmd = GET_CMD_SP(sp);
17d98630
AC		 1004 switch (type) {
1005 case WAIT_HOST:
1006 match = 1;
1007 break;
1008 case WAIT_TARGET:
9ba56b95 1009 match = cmd->device->id == t;
17d98630
AC		 1010 break;
1011 case WAIT_LUN:
9ba56b95
GM		 1012 match = (cmd->device->id == t &&
1013 cmd->device->lun == l);
17d98630 1014 break;
73208dfd 1015 }
17d98630
AC		 1016 if (!match)
1017 continue;
1018
1019 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1020 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1021 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1022 }
e315cd28 1023 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1024
1025 return status;
1da177e4
LT		 1026}
1027
523ec773
AV		 1028static char *reset_errors[] = {
1029 "HBA not online",
1030 "HBA not ready",
1031 "Task management failed",
1032 "Waiting for command completions",
1033};
1da177e4 1034
e5f82ab8 1035static int
523ec773 1036__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 1037 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 1038{
e315cd28 1039 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1040 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1041 int err;
1da177e4 1042
7c3df132 1043 if (!fcport) {
523ec773 1044 return FAILED;
7c3df132 1045 }
1da177e4 1046
4e98d3b8
AV		 1047 err = fc_block_scsi_eh(cmd);
1048 if (err != 0)
1049 return err;
1050
7c3df132 1051 ql_log(ql_log_info, vha, 0x8009,
cfb0919c 1052 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
7c3df132 1053 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1054
523ec773 1055 err = 0;
7c3df132
SK		 1056 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1057 ql_log(ql_log_warn, vha, 0x800a,
1058 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1059 goto eh_reset_failed;
7c3df132 1060 }
523ec773 1061 err = 2;
2afa19a9 1062 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1063 != QLA_SUCCESS) {
1064 ql_log(ql_log_warn, vha, 0x800c,
1065 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1066 goto eh_reset_failed;
7c3df132 1067 }
523ec773 1068 err = 3;
e315cd28 1069 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1070 cmd->device->lun, type) != QLA_SUCCESS) {
1071 ql_log(ql_log_warn, vha, 0x800d,
1072 "wait for peding cmds failed for cmd=%p.\n", cmd);
523ec773 1073 goto eh_reset_failed;
7c3df132 1074 }
523ec773 1075
7c3df132 1076 ql_log(ql_log_info, vha, 0x800e,
cfb0919c
CD		 1077 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1078 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1079
1080 return SUCCESS;
1081
4d78c973 1082eh_reset_failed:
7c3df132 1083 ql_log(ql_log_info, vha, 0x800f,
cfb0919c
CD		 1084 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1085 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1086 cmd);
523ec773
AV		 1087 return FAILED;
1088}
1da177e4 1089
523ec773
AV		 1090static int
1091qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1092{
e315cd28
AC		 1093 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1094 struct qla_hw_data *ha = vha->hw;
1da177e4 1095
523ec773
AV		 1096 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1097 ha->isp_ops->lun_reset);
1da177e4
LT		 1098}
1099
1da177e4 1100static int
523ec773 1101qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1102{
e315cd28
AC		 1103 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1104 struct qla_hw_data *ha = vha->hw;
1da177e4 1105
523ec773
AV		 1106 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1107 ha->isp_ops->target_reset);
1da177e4
LT		 1108}
1109
1da177e4
LT		 1110/**************************************************************************
1111* qla2xxx_eh_bus_reset
1112*
1113* Description:
1114* The bus reset function will reset the bus and abort any executing
1115* commands.
1116*
1117* Input:
1118* cmd = Linux SCSI command packet of the command that cause the
1119* bus reset.
1120*
1121* Returns:
1122* SUCCESS/FAILURE (defined as macro in scsi.h).
1123*
1124**************************************************************************/
e5f82ab8 1125static int
1da177e4
LT		 1126qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1127{
e315cd28 1128 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1129 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1130 int ret = FAILED;
f4f051eb 1131 unsigned int id, lun;
f4f051eb 1132
f4f051eb 1133 id = cmd->device->id;
1134 lun = cmd->device->lun;
1da177e4 1135
7c3df132 1136 if (!fcport) {
f4f051eb 1137 return ret;
7c3df132 1138 }
1da177e4 1139
4e98d3b8
AV		 1140 ret = fc_block_scsi_eh(cmd);
1141 if (ret != 0)
1142 return ret;
1143 ret = FAILED;
1144
7c3df132 1145 ql_log(ql_log_info, vha, 0x8012,
cfb0919c 1146 "BUS RESET ISSUED nexus=%ld:%d%d.\n", vha->host_no, id, lun);
1da177e4 1147
e315cd28 1148 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1149 ql_log(ql_log_fatal, vha, 0x8013,
1150 "Wait for hba online failed board disabled.\n");
f4f051eb 1151 goto eh_bus_reset_done;
1da177e4
LT		 1152 }
1153
ad537689
SK		 1154 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1155 ret = SUCCESS;
1156
f4f051eb 1157 if (ret == FAILED)
1158 goto eh_bus_reset_done;
1da177e4 1159
9a41a62b 1160 /* Flush outstanding commands. */
4d78c973 1161 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1162 QLA_SUCCESS) {
1163 ql_log(ql_log_warn, vha, 0x8014,
1164 "Wait for pending commands failed.\n");
9a41a62b 1165 ret = FAILED;
7c3df132 1166 }
1da177e4 1167
f4f051eb 1168eh_bus_reset_done:
7c3df132 1169 ql_log(ql_log_warn, vha, 0x802b,
cfb0919c
CD		 1170 "BUS RESET %s nexus=%ld:%d:%d.\n",
1171 (ret == FAILED) ? "FAILED" : "SUCCEDED", vha->host_no, id, lun);
1da177e4 1172
f4f051eb 1173 return ret;
1da177e4
LT		 1174}
1175
1176/**************************************************************************
1177* qla2xxx_eh_host_reset
1178*
1179* Description:
1180* The reset function will reset the Adapter.
1181*
1182* Input:
1183* cmd = Linux SCSI command packet of the command that cause the
1184* adapter reset.
1185*
1186* Returns:
1187* Either SUCCESS or FAILED.
1188*
1189* Note:
1190**************************************************************************/
e5f82ab8 1191static int
1da177e4
LT		 1192qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1193{
e315cd28 1194 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1195 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1196 int ret = FAILED;
f4f051eb 1197 unsigned int id, lun;
e315cd28 1198 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1199
f4f051eb 1200 id = cmd->device->id;
1201 lun = cmd->device->lun;
f4f051eb 1202
7c3df132 1203 ql_log(ql_log_info, vha, 0x8018,
cfb0919c 1204 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1205
86fbee86 1206 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1207 goto eh_host_reset_lock;
1da177e4 1208
e315cd28
AC		 1209 if (vha != base_vha) {
1210 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1211 goto eh_host_reset_lock;
e315cd28 1212 } else {
a9083016
GM		 1213 if (IS_QLA82XX(vha->hw)) {
1214 if (!qla82xx_fcoe_ctx_reset(vha)) {
1215 /* Ctx reset success */
1216 ret = SUCCESS;
1217 goto eh_host_reset_lock;
1218 }
1219 /* fall thru if ctx reset failed */
1220 }
68ca949c
AC		 1221 if (ha->wq)
1222 flush_workqueue(ha->wq);
1223
e315cd28 1224 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1225 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1226 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1227 /* failed. schedule dpc to try */
1228 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1229
7c3df132
SK		 1230 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1231 ql_log(ql_log_warn, vha, 0x802a,
1232 "wait for hba online failed.\n");
e315cd28 1233 goto eh_host_reset_lock;
7c3df132 1234 }
e315cd28
AC		 1235 }
1236 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1237 }
1da177e4 1238
e315cd28 1239 /* Waiting for command to be returned to OS.*/
4d78c973 1240 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1241 QLA_SUCCESS)
f4f051eb 1242 ret = SUCCESS;
1da177e4 1243
f4f051eb 1244eh_host_reset_lock:
cfb0919c
CD		 1245 ql_log(ql_log_info, vha, 0x8017,
1246 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1247 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1248
f4f051eb 1249 return ret;
1250}
1da177e4
LT		 1251
1252/*
1253* qla2x00_loop_reset
1254* Issue loop reset.
1255*
1256* Input:
1257* ha = adapter block pointer.
1258*
1259* Returns:
1260* 0 = success
1261*/
a4722cf2 1262int
e315cd28 1263qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1264{
0c8c39af 1265 int ret;
bdf79621 1266 struct fc_port *fcport;
e315cd28 1267 struct qla_hw_data *ha = vha->hw;
1da177e4 1268
f4c496c1 1269 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1270 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1271 if (fcport->port_type != FCT_TARGET)
1272 continue;
1273
1274 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1275 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1276 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1277 "Bus Reset failed: Target Reset=%d "
1278 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1279 }
1280 }
1281 }
1282
6246b8a1 1283 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
e315cd28 1284 ret = qla2x00_full_login_lip(vha);
0c8c39af 1285 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1286 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1287 "full_login_lip=%d.\n", ret);
749af3d5
AC		 1288 }
1289 atomic_set(&vha->loop_state, LOOP_DOWN);
1290 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1291 qla2x00_mark_all_devices_lost(vha, 0);
0c8c39af
AV		 1292 }
1293
0d6e61bc 1294 if (ha->flags.enable_lip_reset) {
e315cd28 1295 ret = qla2x00_lip_reset(vha);
ad537689 1296 if (ret != QLA_SUCCESS)
7c3df132
SK		 1297 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1298 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1299 }
1300
1da177e4 1301 /* Issue marker command only when we are going to start the I/O */
e315cd28 1302 vha->marker_needed = 1;
1da177e4 1303
0c8c39af 1304 return QLA_SUCCESS;
1da177e4
LT		 1305}
1306
df4bf0bb 1307void
e315cd28 1308qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1309{
73208dfd 1310 int que, cnt;
df4bf0bb
AV		 1311 unsigned long flags;
1312 srb_t *sp;
e315cd28 1313 struct qla_hw_data *ha = vha->hw;
73208dfd 1314 struct req_que *req;
df4bf0bb
AV		 1315
1316 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1317 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1318 req = ha->req_q_map[que];
73208dfd
AC		 1319 if (!req)
1320 continue;
1321 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
1322 sp = req->outstanding_cmds[cnt];
e612d465 1323 if (sp) {
73208dfd 1324 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1325 sp->done(vha, sp, res);
73208dfd 1326 }
df4bf0bb
AV		 1327 }
1328 }
1329 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1330}
1331
f4f051eb 1332static int
1333qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1334{
bdf79621 1335 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1336
19a7b4ae 1337 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1338 return -ENXIO;
bdf79621 1339
19a7b4ae 1340 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1341
f4f051eb 1342 return 0;
1343}
1da177e4 1344
f4f051eb 1345static int
1346qla2xxx_slave_configure(struct scsi_device *sdev)
1347{
e315cd28 1348 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1349 struct req_que *req = vha->req;
8482e118 1350
f4f051eb 1351 if (sdev->tagged_supported)
73208dfd 1352 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1353 else
73208dfd 1354 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb 1355 return 0;
1356}
1da177e4 1357
f4f051eb 1358static void
1359qla2xxx_slave_destroy(struct scsi_device *sdev)
1360{
1361 sdev->hostdata = NULL;
1da177e4
LT		 1362}
1363
c45dd305
GM		 1364static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1365{
1366 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1367
1368 if (!scsi_track_queue_full(sdev, qdepth))
1369 return;
1370
7c3df132 1371 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
cfb0919c
CD		 1372 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1373 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1374}
1375
1376static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1377{
1378 fc_port_t *fcport = sdev->hostdata;
1379 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1380 struct req_que *req = NULL;
1381
1382 req = vha->req;
1383 if (!req)
1384 return;
1385
1386 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1387 return;
1388
1389 if (sdev->ordered_tags)
1390 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1391 else
1392 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1393
7c3df132 1394 ql_dbg(ql_dbg_io, vha, 0x302a,
cfb0919c
CD		 1395 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1396 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1397}
1398
ce7e4af7 1399static int
e881a172 1400qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1401{
c45dd305
GM		 1402 switch (reason) {
1403 case SCSI_QDEPTH_DEFAULT:
1404 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1405 break;
1406 case SCSI_QDEPTH_QFULL:
1407 qla2x00_handle_queue_full(sdev, qdepth);
1408 break;
1409 case SCSI_QDEPTH_RAMP_UP:
1410 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1411 break;
1412 default:
08002af2 1413 return -EOPNOTSUPP;
c45dd305 1414 }
e881a172 1415
ce7e4af7
AV		 1416 return sdev->queue_depth;
1417}
1418
1419static int
1420qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1421{
1422 if (sdev->tagged_supported) {
1423 scsi_set_tag_type(sdev, tag_type);
1424 if (tag_type)
1425 scsi_activate_tcq(sdev, sdev->queue_depth);
1426 else
1427 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1428 } else
1429 tag_type = 0;
1430
1431 return tag_type;
1432}
1433
1da177e4
LT		 1434/**
1435 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1436 * @ha: HA context
1437 *
1438 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1439 * supported addressing method.
1440 */
1441static void
53303c42 1442qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1443{
7524f9b9 1444 /* Assume a 32bit DMA mask. */
1da177e4 1445 ha->flags.enable_64bit_addressing = 0;
1da177e4 1446
6a35528a 1447 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1448 /* Any upper-dword bits set? */
1449 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1450 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1451 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1452 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1453 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1454 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1455 return;
1da177e4 1456 }
1da177e4 1457 }
7524f9b9 1458
284901a9
YH		 1459 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1460 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1461}
1462
fd34f556 1463static void
e315cd28 1464qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1465{
1466 unsigned long flags = 0;
1467 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1468
1469 spin_lock_irqsave(&ha->hardware_lock, flags);
1470 ha->interrupts_on = 1;
1471 /* enable risc and host interrupts */
1472 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1473 RD_REG_WORD(&reg->ictrl);
1474 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1475
1476}
1477
1478static void
e315cd28 1479qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1480{
1481 unsigned long flags = 0;
1482 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1483
1484 spin_lock_irqsave(&ha->hardware_lock, flags);
1485 ha->interrupts_on = 0;
1486 /* disable risc and host interrupts */
1487 WRT_REG_WORD(&reg->ictrl, 0);
1488 RD_REG_WORD(&reg->ictrl);
1489 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1490}
1491
1492static void
e315cd28 1493qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1494{
1495 unsigned long flags = 0;
1496 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1497
1498 spin_lock_irqsave(&ha->hardware_lock, flags);
1499 ha->interrupts_on = 1;
1500 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1501 RD_REG_DWORD(&reg->ictrl);
1502 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1503}
1504
1505static void
e315cd28 1506qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1507{
1508 unsigned long flags = 0;
1509 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1510
124f85e6
AV		 1511 if (IS_NOPOLLING_TYPE(ha))
1512 return;
fd34f556
AV		 1513 spin_lock_irqsave(&ha->hardware_lock, flags);
1514 ha->interrupts_on = 0;
1515 WRT_REG_DWORD(&reg->ictrl, 0);
1516 RD_REG_DWORD(&reg->ictrl);
1517 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1518}
1519
706f457d
GM		 1520static int
1521qla2x00_iospace_config(struct qla_hw_data *ha)
1522{
1523 resource_size_t pio;
1524 uint16_t msix;
1525 int cpus;
1526
706f457d
GM		 1527 if (pci_request_selected_regions(ha->pdev, ha->bars,
1528 QLA2XXX_DRIVER_NAME)) {
1529 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1530 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1531 pci_name(ha->pdev));
1532 goto iospace_error_exit;
1533 }
1534 if (!(ha->bars & 1))
1535 goto skip_pio;
1536
1537 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1538 pio = pci_resource_start(ha->pdev, 0);
1539 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1540 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1541 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1542 "Invalid pci I/O region size (%s).\n",
1543 pci_name(ha->pdev));
1544 pio = 0;
1545 }
1546 } else {
1547 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1548 "Region #0 no a PIO resource (%s).\n",
1549 pci_name(ha->pdev));
1550 pio = 0;
1551 }
1552 ha->pio_address = pio;
1553 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1554 "PIO address=%llu.\n",
1555 (unsigned long long)ha->pio_address);
1556
1557skip_pio:
1558 /* Use MMIO operations for all accesses. */
1559 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1560 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1561 "Region #1 not an MMIO resource (%s), aborting.\n",
1562 pci_name(ha->pdev));
1563 goto iospace_error_exit;
1564 }
1565 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1566 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1567 "Invalid PCI mem region size (%s), aborting.\n",
1568 pci_name(ha->pdev));
1569 goto iospace_error_exit;
1570 }
1571
1572 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1573 if (!ha->iobase) {
1574 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1575 "Cannot remap MMIO (%s), aborting.\n",
1576 pci_name(ha->pdev));
1577 goto iospace_error_exit;
1578 }
1579
1580 /* Determine queue resources */
1581 ha->max_req_queues = ha->max_rsp_queues = 1;
1582 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1583 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1584 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1585 goto mqiobase_exit;
1586
1587 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1588 pci_resource_len(ha->pdev, 3));
1589 if (ha->mqiobase) {
1590 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1591 "MQIO Base=%p.\n", ha->mqiobase);
1592 /* Read MSIX vector size of the board */
1593 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1594 ha->msix_count = msix;
1595 /* Max queues are bounded by available msix vectors */
1596 /* queue 0 uses two msix vectors */
1597 if (ql2xmultique_tag) {
1598 cpus = num_online_cpus();
1599 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1600 (cpus + 1) : (ha->msix_count - 1);
1601 ha->max_req_queues = 2;
1602 } else if (ql2xmaxqueues > 1) {
1603 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1604 QLA_MQ_SIZE : ql2xmaxqueues;
1605 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1606 "QoS mode set, max no of request queues:%d.\n",
1607 ha->max_req_queues);
1608 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1609 "QoS mode set, max no of request queues:%d.\n",
1610 ha->max_req_queues);
1611 }
1612 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1613 "MSI-X vector count: %d.\n", msix);
1614 } else
1615 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1616 "BAR 3 not enabled.\n");
1617
1618mqiobase_exit:
1619 ha->msix_count = ha->max_rsp_queues + 1;
1620 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1621 "MSIX Count:%d.\n", ha->msix_count);
1622 return (0);
1623
1624iospace_error_exit:
1625 return (-ENOMEM);
1626}
1627
1628
6246b8a1
GM		 1629static int
1630qla83xx_iospace_config(struct qla_hw_data *ha)
1631{
1632 uint16_t msix;
1633 int cpus;
1634
1635 if (pci_request_selected_regions(ha->pdev, ha->bars,
1636 QLA2XXX_DRIVER_NAME)) {
1637 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1638 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1639 pci_name(ha->pdev));
1640
1641 goto iospace_error_exit;
1642 }
1643
1644 /* Use MMIO operations for all accesses. */
1645 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1646 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1647 "Invalid pci I/O region size (%s).\n",
1648 pci_name(ha->pdev));
1649 goto iospace_error_exit;
1650 }
1651 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1652 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1653 "Invalid PCI mem region size (%s), aborting\n",
1654 pci_name(ha->pdev));
1655 goto iospace_error_exit;
1656 }
1657
1658 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1659 if (!ha->iobase) {
1660 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1661 "Cannot remap MMIO (%s), aborting.\n",
1662 pci_name(ha->pdev));
1663 goto iospace_error_exit;
1664 }
1665
1666 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1667 /* 83XX 26XX always use MQ type access for queues
1668 * - mbar 2, a.k.a region 4 */
1669 ha->max_req_queues = ha->max_rsp_queues = 1;
1670 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1671 pci_resource_len(ha->pdev, 4));
1672
1673 if (!ha->mqiobase) {
1674 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1675 "BAR2/region4 not enabled\n");
1676 goto mqiobase_exit;
1677 }
1678
1679 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1680 pci_resource_len(ha->pdev, 2));
1681 if (ha->msixbase) {
1682 /* Read MSIX vector size of the board */
1683 pci_read_config_word(ha->pdev,
1684 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1685 ha->msix_count = msix;
1686 /* Max queues are bounded by available msix vectors */
1687 /* queue 0 uses two msix vectors */
1688 if (ql2xmultique_tag) {
1689 cpus = num_online_cpus();
1690 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1691 (cpus + 1) : (ha->msix_count - 1);
1692 ha->max_req_queues = 2;
1693 } else if (ql2xmaxqueues > 1) {
1694 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1695 QLA_MQ_SIZE : ql2xmaxqueues;
1696 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1697 "QoS mode set, max no of request queues:%d.\n",
1698 ha->max_req_queues);
1699 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1700 "QoS mode set, max no of request queues:%d.\n",
1701 ha->max_req_queues);
1702 }
1703 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1704 "MSI-X vector count: %d.\n", msix);
1705 } else
1706 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1707 "BAR 1 not enabled.\n");
1708
1709mqiobase_exit:
1710 ha->msix_count = ha->max_rsp_queues + 1;
1711 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1712 "MSIX Count:%d.\n", ha->msix_count);
1713 return 0;
1714
1715iospace_error_exit:
1716 return -ENOMEM;
1717}
1718
fd34f556
AV		 1719static struct isp_operations qla2100_isp_ops = {
1720 .pci_config = qla2100_pci_config,
1721 .reset_chip = qla2x00_reset_chip,
1722 .chip_diag = qla2x00_chip_diag,
1723 .config_rings = qla2x00_config_rings,
1724 .reset_adapter = qla2x00_reset_adapter,
1725 .nvram_config = qla2x00_nvram_config,
1726 .update_fw_options = qla2x00_update_fw_options,
1727 .load_risc = qla2x00_load_risc,
1728 .pci_info_str = qla2x00_pci_info_str,
1729 .fw_version_str = qla2x00_fw_version_str,
1730 .intr_handler = qla2100_intr_handler,
1731 .enable_intrs = qla2x00_enable_intrs,
1732 .disable_intrs = qla2x00_disable_intrs,
1733 .abort_command = qla2x00_abort_command,
523ec773
AV		 1734 .target_reset = qla2x00_abort_target,
1735 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1736 .fabric_login = qla2x00_login_fabric,
1737 .fabric_logout = qla2x00_fabric_logout,
1738 .calc_req_entries = qla2x00_calc_iocbs_32,
1739 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1740 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1741 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1742 .read_nvram = qla2x00_read_nvram_data,
1743 .write_nvram = qla2x00_write_nvram_data,
1744 .fw_dump = qla2100_fw_dump,
1745 .beacon_on = NULL,
1746 .beacon_off = NULL,
1747 .beacon_blink = NULL,
1748 .read_optrom = qla2x00_read_optrom_data,
1749 .write_optrom = qla2x00_write_optrom_data,
1750 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1751 .start_scsi = qla2x00_start_scsi,
a9083016 1752 .abort_isp = qla2x00_abort_isp,
706f457d 1753 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1754};
1755
1756static struct isp_operations qla2300_isp_ops = {
1757 .pci_config = qla2300_pci_config,
1758 .reset_chip = qla2x00_reset_chip,
1759 .chip_diag = qla2x00_chip_diag,
1760 .config_rings = qla2x00_config_rings,
1761 .reset_adapter = qla2x00_reset_adapter,
1762 .nvram_config = qla2x00_nvram_config,
1763 .update_fw_options = qla2x00_update_fw_options,
1764 .load_risc = qla2x00_load_risc,
1765 .pci_info_str = qla2x00_pci_info_str,
1766 .fw_version_str = qla2x00_fw_version_str,
1767 .intr_handler = qla2300_intr_handler,
1768 .enable_intrs = qla2x00_enable_intrs,
1769 .disable_intrs = qla2x00_disable_intrs,
1770 .abort_command = qla2x00_abort_command,
523ec773
AV		 1771 .target_reset = qla2x00_abort_target,
1772 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1773 .fabric_login = qla2x00_login_fabric,
1774 .fabric_logout = qla2x00_fabric_logout,
1775 .calc_req_entries = qla2x00_calc_iocbs_32,
1776 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1777 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1778 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1779 .read_nvram = qla2x00_read_nvram_data,
1780 .write_nvram = qla2x00_write_nvram_data,
1781 .fw_dump = qla2300_fw_dump,
1782 .beacon_on = qla2x00_beacon_on,
1783 .beacon_off = qla2x00_beacon_off,
1784 .beacon_blink = qla2x00_beacon_blink,
1785 .read_optrom = qla2x00_read_optrom_data,
1786 .write_optrom = qla2x00_write_optrom_data,
1787 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1788 .start_scsi = qla2x00_start_scsi,
a9083016 1789 .abort_isp = qla2x00_abort_isp,
706f457d 1790 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1791};
1792
1793static struct isp_operations qla24xx_isp_ops = {
1794 .pci_config = qla24xx_pci_config,
1795 .reset_chip = qla24xx_reset_chip,
1796 .chip_diag = qla24xx_chip_diag,
1797 .config_rings = qla24xx_config_rings,
1798 .reset_adapter = qla24xx_reset_adapter,
1799 .nvram_config = qla24xx_nvram_config,
1800 .update_fw_options = qla24xx_update_fw_options,
1801 .load_risc = qla24xx_load_risc,
1802 .pci_info_str = qla24xx_pci_info_str,
1803 .fw_version_str = qla24xx_fw_version_str,
1804 .intr_handler = qla24xx_intr_handler,
1805 .enable_intrs = qla24xx_enable_intrs,
1806 .disable_intrs = qla24xx_disable_intrs,
1807 .abort_command = qla24xx_abort_command,
523ec773
AV		 1808 .target_reset = qla24xx_abort_target,
1809 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1810 .fabric_login = qla24xx_login_fabric,
1811 .fabric_logout = qla24xx_fabric_logout,
1812 .calc_req_entries = NULL,
1813 .build_iocbs = NULL,
1814 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1815 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1816 .read_nvram = qla24xx_read_nvram_data,
1817 .write_nvram = qla24xx_write_nvram_data,
1818 .fw_dump = qla24xx_fw_dump,
1819 .beacon_on = qla24xx_beacon_on,
1820 .beacon_off = qla24xx_beacon_off,
1821 .beacon_blink = qla24xx_beacon_blink,
1822 .read_optrom = qla24xx_read_optrom_data,
1823 .write_optrom = qla24xx_write_optrom_data,
1824 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1825 .start_scsi = qla24xx_start_scsi,
a9083016 1826 .abort_isp = qla2x00_abort_isp,
706f457d 1827 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1828};
1829
c3a2f0df
AV		 1830static struct isp_operations qla25xx_isp_ops = {
1831 .pci_config = qla25xx_pci_config,
1832 .reset_chip = qla24xx_reset_chip,
1833 .chip_diag = qla24xx_chip_diag,
1834 .config_rings = qla24xx_config_rings,
1835 .reset_adapter = qla24xx_reset_adapter,
1836 .nvram_config = qla24xx_nvram_config,
1837 .update_fw_options = qla24xx_update_fw_options,
1838 .load_risc = qla24xx_load_risc,
1839 .pci_info_str = qla24xx_pci_info_str,
1840 .fw_version_str = qla24xx_fw_version_str,
1841 .intr_handler = qla24xx_intr_handler,
1842 .enable_intrs = qla24xx_enable_intrs,
1843 .disable_intrs = qla24xx_disable_intrs,
1844 .abort_command = qla24xx_abort_command,
523ec773
AV		 1845 .target_reset = qla24xx_abort_target,
1846 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1847 .fabric_login = qla24xx_login_fabric,
1848 .fabric_logout = qla24xx_fabric_logout,
1849 .calc_req_entries = NULL,
1850 .build_iocbs = NULL,
1851 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1852 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1853 .read_nvram = qla25xx_read_nvram_data,
1854 .write_nvram = qla25xx_write_nvram_data,
1855 .fw_dump = qla25xx_fw_dump,
1856 .beacon_on = qla24xx_beacon_on,
1857 .beacon_off = qla24xx_beacon_off,
1858 .beacon_blink = qla24xx_beacon_blink,
338c9161 1859 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1860 .write_optrom = qla24xx_write_optrom_data,
1861 .get_flash_version = qla24xx_get_flash_version,
bad75002 1862 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1863 .abort_isp = qla2x00_abort_isp,
706f457d 1864 .iospace_config = qla2x00_iospace_config,
c3a2f0df
AV		 1865};
1866
3a03eb79
AV		 1867static struct isp_operations qla81xx_isp_ops = {
1868 .pci_config = qla25xx_pci_config,
1869 .reset_chip = qla24xx_reset_chip,
1870 .chip_diag = qla24xx_chip_diag,
1871 .config_rings = qla24xx_config_rings,
1872 .reset_adapter = qla24xx_reset_adapter,
1873 .nvram_config = qla81xx_nvram_config,
1874 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1875 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1876 .pci_info_str = qla24xx_pci_info_str,
1877 .fw_version_str = qla24xx_fw_version_str,
1878 .intr_handler = qla24xx_intr_handler,
1879 .enable_intrs = qla24xx_enable_intrs,
1880 .disable_intrs = qla24xx_disable_intrs,
1881 .abort_command = qla24xx_abort_command,
1882 .target_reset = qla24xx_abort_target,
1883 .lun_reset = qla24xx_lun_reset,
1884 .fabric_login = qla24xx_login_fabric,
1885 .fabric_logout = qla24xx_fabric_logout,
1886 .calc_req_entries = NULL,
1887 .build_iocbs = NULL,
1888 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1889 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1890 .read_nvram = NULL,
1891 .write_nvram = NULL,
3a03eb79
AV		 1892 .fw_dump = qla81xx_fw_dump,
1893 .beacon_on = qla24xx_beacon_on,
1894 .beacon_off = qla24xx_beacon_off,
6246b8a1 1895 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1896 .read_optrom = qla25xx_read_optrom_data,
1897 .write_optrom = qla24xx_write_optrom_data,
1898 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1899 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1900 .abort_isp = qla2x00_abort_isp,
706f457d 1901 .iospace_config = qla2x00_iospace_config,
a9083016
GM		 1902};
1903
1904static struct isp_operations qla82xx_isp_ops = {
1905 .pci_config = qla82xx_pci_config,
1906 .reset_chip = qla82xx_reset_chip,
1907 .chip_diag = qla24xx_chip_diag,
1908 .config_rings = qla82xx_config_rings,
1909 .reset_adapter = qla24xx_reset_adapter,
1910 .nvram_config = qla81xx_nvram_config,
1911 .update_fw_options = qla24xx_update_fw_options,
1912 .load_risc = qla82xx_load_risc,
1913 .pci_info_str = qla82xx_pci_info_str,
1914 .fw_version_str = qla24xx_fw_version_str,
1915 .intr_handler = qla82xx_intr_handler,
1916 .enable_intrs = qla82xx_enable_intrs,
1917 .disable_intrs = qla82xx_disable_intrs,
1918 .abort_command = qla24xx_abort_command,
1919 .target_reset = qla24xx_abort_target,
1920 .lun_reset = qla24xx_lun_reset,
1921 .fabric_login = qla24xx_login_fabric,
1922 .fabric_logout = qla24xx_fabric_logout,
1923 .calc_req_entries = NULL,
1924 .build_iocbs = NULL,
1925 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1926 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1927 .read_nvram = qla24xx_read_nvram_data,
1928 .write_nvram = qla24xx_write_nvram_data,
1929 .fw_dump = qla24xx_fw_dump,
999916dc
SK		 1930 .beacon_on = qla82xx_beacon_on,
1931 .beacon_off = qla82xx_beacon_off,
1932 .beacon_blink = NULL,
a9083016
GM		 1933 .read_optrom = qla82xx_read_optrom_data,
1934 .write_optrom = qla82xx_write_optrom_data,
1935 .get_flash_version = qla24xx_get_flash_version,
1936 .start_scsi = qla82xx_start_scsi,
1937 .abort_isp = qla82xx_abort_isp,
706f457d 1938 .iospace_config = qla82xx_iospace_config,
3a03eb79
AV		 1939};
1940
6246b8a1
GM		 1941static struct isp_operations qla83xx_isp_ops = {
1942 .pci_config = qla25xx_pci_config,
1943 .reset_chip = qla24xx_reset_chip,
1944 .chip_diag = qla24xx_chip_diag,
1945 .config_rings = qla24xx_config_rings,
1946 .reset_adapter = qla24xx_reset_adapter,
1947 .nvram_config = qla81xx_nvram_config,
1948 .update_fw_options = qla81xx_update_fw_options,
1949 .load_risc = qla81xx_load_risc,
1950 .pci_info_str = qla24xx_pci_info_str,
1951 .fw_version_str = qla24xx_fw_version_str,
1952 .intr_handler = qla24xx_intr_handler,
1953 .enable_intrs = qla24xx_enable_intrs,
1954 .disable_intrs = qla24xx_disable_intrs,
1955 .abort_command = qla24xx_abort_command,
1956 .target_reset = qla24xx_abort_target,
1957 .lun_reset = qla24xx_lun_reset,
1958 .fabric_login = qla24xx_login_fabric,
1959 .fabric_logout = qla24xx_fabric_logout,
1960 .calc_req_entries = NULL,
1961 .build_iocbs = NULL,
1962 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1963 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1964 .read_nvram = NULL,
1965 .write_nvram = NULL,
1966 .fw_dump = qla83xx_fw_dump,
1967 .beacon_on = qla24xx_beacon_on,
1968 .beacon_off = qla24xx_beacon_off,
1969 .beacon_blink = qla83xx_beacon_blink,
1970 .read_optrom = qla25xx_read_optrom_data,
1971 .write_optrom = qla24xx_write_optrom_data,
1972 .get_flash_version = qla24xx_get_flash_version,
1973 .start_scsi = qla24xx_dif_start_scsi,
1974 .abort_isp = qla2x00_abort_isp,
1975 .iospace_config = qla83xx_iospace_config,
1976};
1977
ea5b6382 1978static inline void
e315cd28 1979qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 1980{
1981 ha->device_type = DT_EXTENDED_IDS;
1982 switch (ha->pdev->device) {
1983 case PCI_DEVICE_ID_QLOGIC_ISP2100:
1984 ha->device_type |= DT_ISP2100;
1985 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 1986 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 1987 break;
1988 case PCI_DEVICE_ID_QLOGIC_ISP2200:
1989 ha->device_type |= DT_ISP2200;
1990 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 1991 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 1992 break;
1993 case PCI_DEVICE_ID_QLOGIC_ISP2300:
1994 ha->device_type |= DT_ISP2300;
4a59f71d 1995 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 1996 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 1997 break;
1998 case PCI_DEVICE_ID_QLOGIC_ISP2312:
1999 ha->device_type |= DT_ISP2312;
4a59f71d 2000 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2001 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2002 break;
2003 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2004 ha->device_type |= DT_ISP2322;
4a59f71d 2005 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2006 if (ha->pdev->subsystem_vendor == 0x1028 &&
2007 ha->pdev->subsystem_device == 0x0170)
2008 ha->device_type |= DT_OEM_001;
441d1072 2009 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2010 break;
2011 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2012 ha->device_type |= DT_ISP6312;
441d1072 2013 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2014 break;
2015 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2016 ha->device_type |= DT_ISP6322;
441d1072 2017 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2018 break;
2019 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2020 ha->device_type |= DT_ISP2422;
4a59f71d 2021 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2022 ha->device_type |= DT_FWI2;
c76f2c01 2023 ha->device_type |= DT_IIDMA;
441d1072 2024 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2025 break;
2026 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2027 ha->device_type |= DT_ISP2432;
4a59f71d 2028 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2029 ha->device_type |= DT_FWI2;
c76f2c01 2030 ha->device_type |= DT_IIDMA;
441d1072 2031 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2032 break;
4d4df193
HK		 2033 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2034 ha->device_type |= DT_ISP8432;
2035 ha->device_type |= DT_ZIO_SUPPORTED;
2036 ha->device_type |= DT_FWI2;
2037 ha->device_type |= DT_IIDMA;
2038 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2039 break;
044cc6c8 2040 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2041 ha->device_type |= DT_ISP5422;
e428924c 2042 ha->device_type |= DT_FWI2;
441d1072 2043 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2044 break;
044cc6c8 2045 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2046 ha->device_type |= DT_ISP5432;
e428924c 2047 ha->device_type |= DT_FWI2;
441d1072 2048 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2049 break;
c3a2f0df
AV		 2050 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2051 ha->device_type |= DT_ISP2532;
2052 ha->device_type |= DT_ZIO_SUPPORTED;
2053 ha->device_type |= DT_FWI2;
2054 ha->device_type |= DT_IIDMA;
441d1072 2055 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2056 break;
3a03eb79
AV		 2057 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2058 ha->device_type |= DT_ISP8001;
2059 ha->device_type |= DT_ZIO_SUPPORTED;
2060 ha->device_type |= DT_FWI2;
2061 ha->device_type |= DT_IIDMA;
2062 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2063 break;
a9083016
GM		 2064 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2065 ha->device_type |= DT_ISP8021;
2066 ha->device_type |= DT_ZIO_SUPPORTED;
2067 ha->device_type |= DT_FWI2;
2068 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2069 /* Initialize 82XX ISP flags */
2070 qla82xx_init_flags(ha);
2071 break;
6246b8a1
GM		 2072 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2073 ha->device_type |= DT_ISP2031;
2074 ha->device_type |= DT_ZIO_SUPPORTED;
2075 ha->device_type |= DT_FWI2;
2076 ha->device_type |= DT_IIDMA;
2077 ha->device_type |= DT_T10_PI;
2078 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2079 break;
2080 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2081 ha->device_type |= DT_ISP8031;
2082 ha->device_type |= DT_ZIO_SUPPORTED;
2083 ha->device_type |= DT_FWI2;
2084 ha->device_type |= DT_IIDMA;
2085 ha->device_type |= DT_T10_PI;
2086 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2087 break;
ea5b6382 2088 }
e5b68a61 2089
a9083016
GM		 2090 if (IS_QLA82XX(ha))
2091 ha->port_no = !(ha->portnum & 1);
2092 else
2093 /* Get adapter physical port no from interrupt pin register. */
2094 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2095
e5b68a61
AC		 2096 if (ha->port_no & 1)
2097 ha->flags.port0 = 1;
2098 else
2099 ha->flags.port0 = 0;
7c3df132 2100 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2101 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
7c3df132 2102 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
ea5b6382 2103}
2104
1e99e33a
AV		 2105static void
2106qla2xxx_scan_start(struct Scsi_Host *shost)
2107{
e315cd28 2108 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2109
cbc8eb67
AV		 2110 if (vha->hw->flags.running_gold_fw)
2111 return;
2112
e315cd28
AC		 2113 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2114 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2115 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2116 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2117}
2118
2119static int
2120qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2121{
e315cd28 2122 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2123
e315cd28 2124 if (!vha->host)
1e99e33a 2125 return 1;
e315cd28 2126 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2127 return 1;
2128
e315cd28 2129 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2130}
2131
1da177e4
LT		 2132/*
2133 * PCI driver interface
2134 */
7ee61397
AV		 2135static int __devinit
2136qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2137{
a1541d5a 2138 int ret = -ENODEV;
1da177e4 2139 struct Scsi_Host *host;
e315cd28
AC		 2140 scsi_qla_host_t *base_vha = NULL;
2141 struct qla_hw_data *ha;
29856e28 2142 char pci_info[30];
1da177e4 2143 char fw_str[30];
5433383e 2144 struct scsi_host_template *sht;
642ef983 2145 int bars, mem_only = 0;
e315cd28 2146 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2147 struct req_que *req = NULL;
2148 struct rsp_que *rsp = NULL;
1da177e4 2149
285d0321 2150 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2151 sht = &qla2xxx_driver_template;
5433383e 2152 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2153 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2154 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2155 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2156 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2157 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2158 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2159 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2160 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2161 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031) {
285d0321 2162 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2163 mem_only = 1;
7c3df132
SK		 2164 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2165 "Mem only adapter.\n");
285d0321 2166 }
7c3df132
SK		 2167 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2168 "Bars=%d.\n", bars);
285d0321 2169
09483916
BH		 2170 if (mem_only) {
2171 if (pci_enable_device_mem(pdev))
2172 goto probe_out;
2173 } else {
2174 if (pci_enable_device(pdev))
2175 goto probe_out;
2176 }
285d0321 2177
0927678f
JB		 2178 /* This may fail but that's ok */
2179 pci_enable_pcie_error_reporting(pdev);
285d0321 2180
e315cd28
AC		 2181 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2182 if (!ha) {
7c3df132
SK		 2183 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2184 "Unable to allocate memory for ha.\n");
e315cd28 2185 goto probe_out;
1da177e4 2186 }
7c3df132
SK		 2187 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2188 "Memory allocated for ha=%p.\n", ha);
e315cd28 2189 ha->pdev = pdev;
1da177e4
LT		 2190
2191 /* Clear our data area */
285d0321 2192 ha->bars = bars;
09483916 2193 ha->mem_only = mem_only;
df4bf0bb 2194 spin_lock_init(&ha->hardware_lock);
339aa70e 2195 spin_lock_init(&ha->vport_slock);
1da177e4 2196
ea5b6382 2197 /* Set ISP-type information. */
2198 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2199
2200 /* Set EEH reset type to fundamental if required by hba */
6246b8a1 2201 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha))
ca79cf66 2202 pdev->needs_freset = 1;
ca79cf66 2203
cba1e47f
CD		 2204 ha->prev_topology = 0;
2205 ha->init_cb_size = sizeof(init_cb_t);
2206 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2207 ha->optrom_size = OPTROM_SIZE_2300;
2208
abbd8870 2209 /* Assign ISP specific operations. */
1da177e4 2210 if (IS_QLA2100(ha)) {
642ef983 2211 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2212 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2213 req_length = REQUEST_ENTRY_CNT_2100;
2214 rsp_length = RESPONSE_ENTRY_CNT_2100;
2215 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2216 ha->gid_list_info_size = 4;
3a03eb79
AV		 2217 ha->flash_conf_off = ~0;
2218 ha->flash_data_off = ~0;
2219 ha->nvram_conf_off = ~0;
2220 ha->nvram_data_off = ~0;
fd34f556 2221 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2222 } else if (IS_QLA2200(ha)) {
642ef983 2223 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2224 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2225 req_length = REQUEST_ENTRY_CNT_2200;
2226 rsp_length = RESPONSE_ENTRY_CNT_2100;
2227 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2228 ha->gid_list_info_size = 4;
3a03eb79
AV		 2229 ha->flash_conf_off = ~0;
2230 ha->flash_data_off = ~0;
2231 ha->nvram_conf_off = ~0;
2232 ha->nvram_data_off = ~0;
fd34f556 2233 ha->isp_ops = &qla2100_isp_ops;
fca29703 2234 } else if (IS_QLA23XX(ha)) {
642ef983 2235 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2236 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2237 req_length = REQUEST_ENTRY_CNT_2200;
2238 rsp_length = RESPONSE_ENTRY_CNT_2300;
2239 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2240 ha->gid_list_info_size = 6;
854165f4 2241 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2242 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2243 ha->flash_conf_off = ~0;
2244 ha->flash_data_off = ~0;
2245 ha->nvram_conf_off = ~0;
2246 ha->nvram_data_off = ~0;
fd34f556 2247 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2248 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2249 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2250 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2251 req_length = REQUEST_ENTRY_CNT_24XX;
2252 rsp_length = RESPONSE_ENTRY_CNT_2300;
2253 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2254 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2255 ha->gid_list_info_size = 8;
854165f4 2256 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2257 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2258 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2259 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2260 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2261 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2262 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2263 } else if (IS_QLA25XX(ha)) {
642ef983 2264 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2265 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2266 req_length = REQUEST_ENTRY_CNT_24XX;
2267 rsp_length = RESPONSE_ENTRY_CNT_2300;
2268 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2269 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2270 ha->gid_list_info_size = 8;
2271 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2272 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2273 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2274 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2275 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2276 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2277 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2278 } else if (IS_QLA81XX(ha)) {
642ef983 2279 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2280 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2281 req_length = REQUEST_ENTRY_CNT_24XX;
2282 rsp_length = RESPONSE_ENTRY_CNT_2300;
2283 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2284 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2285 ha->gid_list_info_size = 8;
2286 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2287 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2288 ha->isp_ops = &qla81xx_isp_ops;
2289 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2290 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2291 ha->nvram_conf_off = ~0;
2292 ha->nvram_data_off = ~0;
a9083016 2293 } else if (IS_QLA82XX(ha)) {
642ef983 2294 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2295 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2296 req_length = REQUEST_ENTRY_CNT_82XX;
2297 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2298 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2299 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2300 ha->gid_list_info_size = 8;
2301 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2302 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2303 ha->isp_ops = &qla82xx_isp_ops;
2304 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2305 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2306 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2307 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2308 } else if (IS_QLA83XX(ha)) {
642ef983 2309 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1
GM		 2310 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2311 req_length = REQUEST_ENTRY_CNT_24XX;
2312 rsp_length = RESPONSE_ENTRY_CNT_2300;
2313 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2314 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2315 ha->gid_list_info_size = 8;
2316 ha->optrom_size = OPTROM_SIZE_83XX;
2317 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2318 ha->isp_ops = &qla83xx_isp_ops;
2319 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2320 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2321 ha->nvram_conf_off = ~0;
2322 ha->nvram_data_off = ~0;
1da177e4 2323 }
6246b8a1 2324
7c3df132
SK		 2325 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2326 "mbx_count=%d, req_length=%d, "
2327 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2328 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2329 "max_fibre_devices=%d.\n",
7c3df132
SK		 2330 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2331 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2332 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2333 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2334 "isp_ops=%p, flash_conf_off=%d, "
2335 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2336 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2337 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2338
2339 /* Configure PCI I/O space */
2340 ret = ha->isp_ops->iospace_config(ha);
2341 if (ret)
2342 goto probe_hw_failed;
2343
2344 ql_log_pci(ql_log_info, pdev, 0x001d,
2345 "Found an ISP%04X irq %d iobase 0x%p.\n",
2346 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2347 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2348 init_completion(&ha->mbx_cmd_comp);
2349 complete(&ha->mbx_cmd_comp);
2350 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2351 init_completion(&ha->dcbx_comp);
1da177e4 2352
2c3dfe3f 2353 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2354
53303c42 2355 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2356 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2357 "64 Bit addressing is %s.\n",
2358 ha->flags.enable_64bit_addressing ? "enable" :
2359 "disable");
73208dfd 2360 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
e315cd28 2361 if (!ret) {
7c3df132
SK		 2362 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2363 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2364
e315cd28
AC		 2365 goto probe_hw_failed;
2366 }
2367
73208dfd 2368 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2369 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2370 req->max_q_depth = ql2xmaxqdepth;
2371
e315cd28
AC		 2372
2373 base_vha = qla2x00_create_host(sht, ha);
2374 if (!base_vha) {
a1541d5a 2375 ret = -ENOMEM;
6e9f21f3 2376 qla2x00_mem_free(ha);
2afa19a9
AC		 2377 qla2x00_free_req_que(ha, req);
2378 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2379 goto probe_hw_failed;
1da177e4
LT		 2380 }
2381
e315cd28
AC		 2382 pci_set_drvdata(pdev, base_vha);
2383
e315cd28 2384 host = base_vha->host;
2afa19a9 2385 base_vha->req = req;
73208dfd
AC		 2386 host->can_queue = req->length + 128;
2387 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2388 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2389 else
e315cd28
AC		 2390 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2391 base_vha->vp_idx;
58548cb5
GM		 2392
2393 /* Set the SG table size based on ISP type */
2394 if (!IS_FWI2_CAPABLE(ha)) {
2395 if (IS_QLA2100(ha))
2396 host->sg_tablesize = 32;
2397 } else {
2398 if (!IS_QLA82XX(ha))
2399 host->sg_tablesize = QLA_SG_ALL;
2400 }
7c3df132
SK		 2401 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2402 "can_queue=%d, req=%p, "
2403 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2404 host->can_queue, base_vha->req,
2405 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
642ef983 2406 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2407 host->this_id = 255;
2408 host->cmd_per_lun = 3;
2409 host->unique_id = host->host_no;
e02587d7 2410 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2411 host->max_cmd_len = 32;
2412 else
2413 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2414 host->max_channel = MAX_BUSES - 1;
82515920 2415 host->max_lun = ql2xmaxlun;
e315cd28 2416 host->transportt = qla2xxx_transport_template;
9a069e19 2417 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2418
7c3df132
SK		 2419 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2420 "max_id=%d this_id=%d "
2421 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
d8424f68 2422 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2423 host->this_id, host->cmd_per_lun, host->unique_id,
2424 host->max_cmd_len, host->max_channel, host->max_lun,
2425 host->transportt, sht->vendor_id);
2426
9a347ff4
CD		 2427que_init:
2428 /* Alloc arrays of request and response ring ptrs */
2429 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2430 ql_log(ql_log_fatal, base_vha, 0x003d,
2431 "Failed to allocate memory for queue pointers..."
2432 "aborting.\n");
2433 goto probe_init_failed;
2434 }
2435
2436
73208dfd
AC		 2437 /* Set up the irqs */
2438 ret = qla2x00_request_irqs(ha, rsp);
2439 if (ret)
6e9f21f3 2440 goto probe_init_failed;
90a86fc0
JC		 2441
2442 pci_save_state(pdev);
2443
9a347ff4 2444 /* Assign back pointers */
2afa19a9
AC		 2445 rsp->req = req;
2446 req->rsp = rsp;
9a347ff4 2447
08029990
AV		 2448 /* FWI2-capable only. */
2449 req->req_q_in = &ha->iobase->isp24.req_q_in;
2450 req->req_q_out = &ha->iobase->isp24.req_q_out;
2451 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2452 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
6246b8a1 2453 if (ha->mqenable || IS_QLA83XX(ha)) {
08029990
AV		 2454 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2455 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2456 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2457 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2458 }
2459
a9083016
GM		 2460 if (IS_QLA82XX(ha)) {
2461 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2462 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2463 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2464 }
2465
7c3df132
SK		 2466 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2467 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2468 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2469 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2470 "req->req_q_in=%p req->req_q_out=%p "
2471 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2472 req->req_q_in, req->req_q_out,
2473 rsp->rsp_q_in, rsp->rsp_q_out);
2474 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2475 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2476 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2477 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2478 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2479 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2480
7c3df132
SK		 2481 if (qla2x00_initialize_adapter(base_vha)) {
2482 ql_log(ql_log_fatal, base_vha, 0x00d6,
2483 "Failed to initialize adapter - Adapter flags %x.\n",
2484 base_vha->device_flags);
1da177e4 2485
a9083016
GM		 2486 if (IS_QLA82XX(ha)) {
2487 qla82xx_idc_lock(ha);
2488 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2489 QLA82XX_DEV_FAILED);
2490 qla82xx_idc_unlock(ha);
7c3df132
SK		 2491 ql_log(ql_log_fatal, base_vha, 0x00d7,
2492 "HW State: FAILED.\n");
a9083016
GM		 2493 }
2494
a1541d5a 2495 ret = -ENODEV;
1da177e4
LT		 2496 goto probe_failed;
2497 }
2498
7163ea81
AC		 2499 if (ha->mqenable) {
2500 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2501 ql_log(ql_log_warn, base_vha, 0x00ec,
2502 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2503 goto que_init;
2504 }
2505 }
68ca949c 2506
cbc8eb67
AV		 2507 if (ha->flags.running_gold_fw)
2508 goto skip_dpc;
2509
1da177e4
LT		 2510 /*
2511 * Startup the kernel thread for this host adapter
2512 */
39a11240 2513 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2514 "%s_dpc", base_vha->host_str);
39a11240 2515 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2516 ql_log(ql_log_fatal, base_vha, 0x00ed,
2517 "Failed to start DPC thread.\n");
39a11240 2518 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2519 goto probe_failed;
2520 }
7c3df132
SK		 2521 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2522 "DPC thread started successfully.\n");
1da177e4 2523
cbc8eb67 2524skip_dpc:
e315cd28
AC		 2525 list_add_tail(&base_vha->list, &ha->vp_list);
2526 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2527
2528 /* Initialized the timer */
e315cd28 2529 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2530 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2531 "Started qla2x00_timer with "
2532 "interval=%d.\n", WATCH_INTERVAL);
2533 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2534 "Detected hba at address=%p.\n",
2535 ha);
d19044c3 2536
e02587d7 2537 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2538 if (ha->fw_attributes & BIT_4) {
8cb2049c 2539 int prot = 0;
bad75002 2540 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2541 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2542 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2543 if (ql2xenabledif == 1)
2544 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2545 scsi_host_set_prot(host,
8cb2049c 2546 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2547 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2548 | SHOST_DIF_TYPE3_PROTECTION
2549 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2550 | SHOST_DIX_TYPE2_PROTECTION
bad75002
AE		 2551 | SHOST_DIX_TYPE3_PROTECTION);
2552 scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
2553 } else
2554 base_vha->flags.difdix_supported = 0;
2555 }
2556
a9083016
GM		 2557 ha->isp_ops->enable_intrs(ha);
2558
a1541d5a
AV		 2559 ret = scsi_add_host(host, &pdev->dev);
2560 if (ret)
2561 goto probe_failed;
2562
1486400f
MR		 2563 base_vha->flags.init_done = 1;
2564 base_vha->flags.online = 1;
2565
7c3df132
SK		 2566 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2567 "Init done and hba is online.\n");
2568
1e99e33a
AV		 2569 scsi_scan_host(host);
2570
e315cd28 2571 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2572
e315cd28 2573 qla2x00_init_host_attr(base_vha);
a1541d5a 2574
e315cd28 2575 qla2x00_dfs_setup(base_vha);
df613b96 2576
7c3df132
SK		 2577 ql_log(ql_log_info, base_vha, 0x00fb,
2578 "QLogic %s - %s.\n",
2579 ha->model_number, ha->model_desc ? ha->model_desc : "");
2580 ql_log(ql_log_info, base_vha, 0x00fc,
2581 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2582 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2583 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2584 base_vha->host_no,
e315cd28 2585 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2586
1da177e4
LT		 2587 return 0;
2588
6e9f21f3 2589probe_init_failed:
2afa19a9 2590 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2591 ha->req_q_map[0] = NULL;
2592 clear_bit(0, ha->req_qid_map);
2afa19a9 2593 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2594 ha->rsp_q_map[0] = NULL;
2595 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2596 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2597
1da177e4 2598probe_failed:
b9978769
AV		 2599 if (base_vha->timer_active)
2600 qla2x00_stop_timer(base_vha);
2601 base_vha->flags.online = 0;
2602 if (ha->dpc_thread) {
2603 struct task_struct *t = ha->dpc_thread;
2604
2605 ha->dpc_thread = NULL;
2606 kthread_stop(t);
2607 }
2608
e315cd28 2609 qla2x00_free_device(base_vha);
1da177e4 2610
e315cd28 2611 scsi_host_put(base_vha->host);
1da177e4 2612
e315cd28 2613probe_hw_failed:
a9083016
GM		 2614 if (IS_QLA82XX(ha)) {
2615 qla82xx_idc_lock(ha);
2616 qla82xx_clear_drv_active(ha);
2617 qla82xx_idc_unlock(ha);
2618 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2619 if (!ql2xdbwr)
2620 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2621 } else {
2622 if (ha->iobase)
2623 iounmap(ha->iobase);
2624 }
e315cd28
AC		 2625 pci_release_selected_regions(ha->pdev, ha->bars);
2626 kfree(ha);
2627 ha = NULL;
1da177e4 2628
a1541d5a 2629probe_out:
e315cd28 2630 pci_disable_device(pdev);
a1541d5a 2631 return ret;
1da177e4 2632}
1da177e4 2633
e30d1756
MI		 2634static void
2635qla2x00_shutdown(struct pci_dev *pdev)
2636{
2637 scsi_qla_host_t *vha;
2638 struct qla_hw_data *ha;
2639
2640 vha = pci_get_drvdata(pdev);
2641 ha = vha->hw;
2642
2643 /* Turn-off FCE trace */
2644 if (ha->flags.fce_enabled) {
2645 qla2x00_disable_fce_trace(vha, NULL, NULL);
2646 ha->flags.fce_enabled = 0;
2647 }
2648
2649 /* Turn-off EFT trace */
2650 if (ha->eft)
2651 qla2x00_disable_eft_trace(vha);
2652
2653 /* Stop currently executing firmware. */
2654 qla2x00_try_to_stop_firmware(vha);
2655
2656 /* Turn adapter off line */
2657 vha->flags.online = 0;
2658
2659 /* turn-off interrupts on the card */
2660 if (ha->interrupts_on) {
2661 vha->flags.init_done = 0;
2662 ha->isp_ops->disable_intrs(ha);
2663 }
2664
2665 qla2x00_free_irqs(vha);
2666
2667 qla2x00_free_fw_dump(ha);
2668}
2669
4c993f76 2670static void
7ee61397 2671qla2x00_remove_one(struct pci_dev *pdev)
1da177e4 2672{
feafb7b1 2673 scsi_qla_host_t *base_vha, *vha;
e315cd28 2674 struct qla_hw_data *ha;
feafb7b1 2675 unsigned long flags;
e315cd28 2676
9a347ff4
CD		 2677 /*
2678 * If the PCI device is disabled that means that probe failed and any
2679 * resources should be have cleaned up on probe exit.
2680 */
2681 if (!atomic_read(&pdev->enable_cnt))
2682 return;
2683
e315cd28
AC		 2684 base_vha = pci_get_drvdata(pdev);
2685 ha = base_vha->hw;
2686
43ebf16d
AE		 2687 mutex_lock(&ha->vport_lock);
2688 while (ha->cur_vport_count) {
2689 struct Scsi_Host *scsi_host;
feafb7b1 2690
43ebf16d 2691 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2692
43ebf16d
AE		 2693 BUG_ON(base_vha->list.next == &ha->vp_list);
2694 /* This assumes first entry in ha->vp_list is always base vha */
2695 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2696 scsi_host = scsi_host_get(vha->host);
feafb7b1 2697
43ebf16d
AE		 2698 spin_unlock_irqrestore(&ha->vport_slock, flags);
2699 mutex_unlock(&ha->vport_lock);
2700
2701 fc_vport_terminate(vha->fc_vport);
2702 scsi_host_put(vha->host);
feafb7b1 2703
43ebf16d 2704 mutex_lock(&ha->vport_lock);
e315cd28 2705 }
43ebf16d 2706 mutex_unlock(&ha->vport_lock);
1da177e4 2707
e315cd28 2708 set_bit(UNLOADING, &base_vha->dpc_flags);
1da177e4 2709
b9978769
AV		 2710 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
2711
e315cd28 2712 qla2x00_dfs_remove(base_vha);
c795c1e4 2713
e315cd28 2714 qla84xx_put_chip(base_vha);
c795c1e4 2715
b9978769
AV		 2716 /* Disable timer */
2717 if (base_vha->timer_active)
2718 qla2x00_stop_timer(base_vha);
2719
2720 base_vha->flags.online = 0;
2721
68ca949c
AC		 2722 /* Flush the work queue and remove it */
2723 if (ha->wq) {
2724 flush_workqueue(ha->wq);
2725 destroy_workqueue(ha->wq);
2726 ha->wq = NULL;
2727 }
2728
b9978769
AV		 2729 /* Kill the kernel thread for this host */
2730 if (ha->dpc_thread) {
2731 struct task_struct *t = ha->dpc_thread;
2732
2733 /*
2734 * qla2xxx_wake_dpc checks for ->dpc_thread
2735 * so we need to zero it out.
2736 */
2737 ha->dpc_thread = NULL;
2738 kthread_stop(t);
2739 }
2740
e315cd28 2741 qla2x00_free_sysfs_attr(base_vha);
df613b96 2742
e315cd28 2743 fc_remove_host(base_vha->host);
4d4df193 2744
e315cd28 2745 scsi_remove_host(base_vha->host);
1da177e4 2746
e315cd28 2747 qla2x00_free_device(base_vha);
bdf79621 2748
e315cd28 2749 scsi_host_put(base_vha->host);
1da177e4 2750
a9083016 2751 if (IS_QLA82XX(ha)) {
b963752f
GM		 2752 qla82xx_idc_lock(ha);
2753 qla82xx_clear_drv_active(ha);
2754 qla82xx_idc_unlock(ha);
2755
a9083016
GM		 2756 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2757 if (!ql2xdbwr)
2758 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2759 } else {
2760 if (ha->iobase)
2761 iounmap(ha->iobase);
1da177e4 2762
a9083016
GM		 2763 if (ha->mqiobase)
2764 iounmap(ha->mqiobase);
6246b8a1
GM		 2765
2766 if (IS_QLA83XX(ha) && ha->msixbase)
2767 iounmap(ha->msixbase);
a9083016 2768 }
73208dfd 2769
e315cd28
AC		 2770 pci_release_selected_regions(ha->pdev, ha->bars);
2771 kfree(ha);
2772 ha = NULL;
1da177e4 2773
90a86fc0
JC		 2774 pci_disable_pcie_error_reporting(pdev);
2775
665db93b 2776 pci_disable_device(pdev);
1da177e4
LT		 2777 pci_set_drvdata(pdev, NULL);
2778}
1da177e4
LT		 2779
2780static void
e315cd28 2781qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 2782{
e315cd28 2783 struct qla_hw_data *ha = vha->hw;
1da177e4 2784
85880801
AV		 2785 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
2786
2787 /* Disable timer */
2788 if (vha->timer_active)
2789 qla2x00_stop_timer(vha);
2790
2791 /* Kill the kernel thread for this host */
2792 if (ha->dpc_thread) {
2793 struct task_struct *t = ha->dpc_thread;
2794
2795 /*
2796 * qla2xxx_wake_dpc checks for ->dpc_thread
2797 * so we need to zero it out.
2798 */
2799 ha->dpc_thread = NULL;
2800 kthread_stop(t);
2801 }
2802
2afa19a9
AC		 2803 qla25xx_delete_queues(vha);
2804
df613b96 2805 if (ha->flags.fce_enabled)
e315cd28 2806 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 2807
a7a167bf 2808 if (ha->eft)
e315cd28 2809 qla2x00_disable_eft_trace(vha);
a7a167bf 2810
f6ef3b18 2811 /* Stop currently executing firmware. */
e315cd28 2812 qla2x00_try_to_stop_firmware(vha);
1da177e4 2813
85880801
AV		 2814 vha->flags.online = 0;
2815
f6ef3b18 2816 /* turn-off interrupts on the card */
a9083016
GM		 2817 if (ha->interrupts_on) {
2818 vha->flags.init_done = 0;
fd34f556 2819 ha->isp_ops->disable_intrs(ha);
a9083016 2820 }
f6ef3b18 2821
e315cd28 2822 qla2x00_free_irqs(vha);
1da177e4 2823
8867048b
CD		 2824 qla2x00_free_fcports(vha);
2825
e315cd28 2826 qla2x00_mem_free(ha);
73208dfd 2827
08de2844
GM		 2828 qla82xx_md_free(vha);
2829
73208dfd 2830 qla2x00_free_queues(ha);
1da177e4
LT		 2831}
2832
8867048b
CD		 2833void qla2x00_free_fcports(struct scsi_qla_host *vha)
2834{
2835 fc_port_t *fcport, *tfcport;
2836
2837 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
2838 list_del(&fcport->list);
2839 kfree(fcport);
2840 fcport = NULL;
2841 }
2842}
2843
d97994dc 2844static inline void
e315cd28 2845qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 2846 int defer)
2847{
d97994dc 2848 struct fc_rport *rport;
67becc00 2849 scsi_qla_host_t *base_vha;
044d78e1 2850 unsigned long flags;
d97994dc 2851
2852 if (!fcport->rport)
2853 return;
2854
2855 rport = fcport->rport;
2856 if (defer) {
67becc00 2857 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 2858 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 2859 fcport->drport = rport;
044d78e1 2860 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 2861 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
2862 qla2xxx_wake_dpc(base_vha);
5f3a9a20 2863 } else
d97994dc 2864 fc_remote_port_delete(rport);
d97994dc 2865}
2866
1da177e4
LT		 2867/*
2868 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
2869 *
2870 * Input: ha = adapter block pointer. fcport = port structure pointer.
2871 *
2872 * Return: None.
2873 *
2874 * Context:
2875 */
e315cd28 2876void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 2877 int do_login, int defer)
1da177e4 2878{
2c3dfe3f 2879 if (atomic_read(&fcport->state) == FCS_ONLINE &&
e315cd28 2880 vha->vp_idx == fcport->vp_idx) {
ec426e10 2881 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 2882 qla2x00_schedule_rport_del(vha, fcport, defer);
2883 }
fa2a1ce5 2884 /*
1da177e4
LT		 2885 * We may need to retry the login, so don't change the state of the
2886 * port but do the retries.
2887 */
2888 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 2889 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2890
2891 if (!do_login)
2892 return;
2893
2894 if (fcport->login_retry == 0) {
e315cd28
AC		 2895 fcport->login_retry = vha->hw->login_retry_count;
2896 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 2897
7c3df132
SK		 2898 ql_dbg(ql_dbg_disc, vha, 0x2067,
2899 "Port login retry "
1da177e4 2900 "%02x%02x%02x%02x%02x%02x%02x%02x, "
7c3df132
SK		 2901 "id = 0x%04x retry cnt=%d.\n",
2902 fcport->port_name[0], fcport->port_name[1],
2903 fcport->port_name[2], fcport->port_name[3],
2904 fcport->port_name[4], fcport->port_name[5],
2905 fcport->port_name[6], fcport->port_name[7],
2906 fcport->loop_id, fcport->login_retry);
1da177e4
LT		 2907 }
2908}
2909
2910/*
2911 * qla2x00_mark_all_devices_lost
2912 * Updates fcport state when device goes offline.
2913 *
2914 * Input:
2915 * ha = adapter block pointer.
2916 * fcport = port structure pointer.
2917 *
2918 * Return:
2919 * None.
2920 *
2921 * Context:
2922 */
2923void
e315cd28 2924qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 2925{
2926 fc_port_t *fcport;
2927
e315cd28 2928 list_for_each_entry(fcport, &vha->vp_fcports, list) {
0d6e61bc 2929 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
1da177e4 2930 continue;
0d6e61bc 2931
1da177e4
LT		 2932 /*
2933 * No point in marking the device as lost, if the device is
2934 * already DEAD.
2935 */
2936 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
2937 continue;
e315cd28 2938 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 2939 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 2940 if (defer)
2941 qla2x00_schedule_rport_del(vha, fcport, defer);
2942 else if (vha->vp_idx == fcport->vp_idx)
2943 qla2x00_schedule_rport_del(vha, fcport, defer);
2944 }
1da177e4
LT		 2945 }
2946}
2947
2948/*
2949* qla2x00_mem_alloc
2950* Allocates adapter memory.
2951*
2952* Returns:
2953* 0 = success.
e8711085 2954* !0 = failure.
1da177e4 2955*/
e8711085 2956static int
73208dfd
AC		 2957qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
2958 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 2959{
2960 char name[16];
1da177e4 2961
e8711085 2962 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 2963 &ha->init_cb_dma, GFP_KERNEL);
e8711085 2964 if (!ha->init_cb)
e315cd28 2965 goto fail;
e8711085 2966
642ef983
CD		 2967 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
2968 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 2969 if (!ha->gid_list)
e8711085 2970 goto fail_free_init_cb;
1da177e4 2971
e8711085
AV		 2972 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
2973 if (!ha->srb_mempool)
e315cd28 2974 goto fail_free_gid_list;
e8711085 2975
a9083016
GM		 2976 if (IS_QLA82XX(ha)) {
2977 /* Allocate cache for CT6 Ctx. */
2978 if (!ctx_cachep) {
2979 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
2980 sizeof(struct ct6_dsd), 0,
2981 SLAB_HWCACHE_ALIGN, NULL);
2982 if (!ctx_cachep)
2983 goto fail_free_gid_list;
2984 }
2985 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
2986 ctx_cachep);
2987 if (!ha->ctx_mempool)
2988 goto fail_free_srb_mempool;
7c3df132
SK		 2989 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
2990 "ctx_cachep=%p ctx_mempool=%p.\n",
2991 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 2992 }
2993
e8711085
AV		 2994 /* Get memory for cached NVRAM */
2995 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
2996 if (!ha->nvram)
a9083016 2997 goto fail_free_ctx_mempool;
e8711085 2998
e315cd28
AC		 2999 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3000 ha->pdev->device);
3001 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3002 DMA_POOL_SIZE, 8, 0);
3003 if (!ha->s_dma_pool)
3004 goto fail_free_nvram;
3005
7c3df132
SK		 3006 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3007 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3008 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3009
bad75002 3010 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3011 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3012 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3013 if (!ha->dl_dma_pool) {
7c3df132
SK		 3014 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3015 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3016 goto fail_s_dma_pool;
3017 }
3018
3019 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3020 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3021 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3022 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3023 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3024 goto fail_dl_dma_pool;
3025 }
7c3df132
SK		 3026 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3027 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3028 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3029 }
3030
e8711085
AV		 3031 /* Allocate memory for SNS commands */
3032 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3033 /* Get consistent memory allocated for SNS commands */
e8711085 3034 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3035 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3036 if (!ha->sns_cmd)
e315cd28 3037 goto fail_dma_pool;
7c3df132 3038 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3039 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3040 } else {
e315cd28 3041 /* Get consistent memory allocated for MS IOCB */
e8711085 3042 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3043 &ha->ms_iocb_dma);
e8711085 3044 if (!ha->ms_iocb)
e315cd28
AC		 3045 goto fail_dma_pool;
3046 /* Get consistent memory allocated for CT SNS commands */
e8711085 3047 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3048 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3049 if (!ha->ct_sns)
3050 goto fail_free_ms_iocb;
7c3df132
SK		 3051 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3052 "ms_iocb=%p ct_sns=%p.\n",
3053 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3054 }
3055
e315cd28 3056 /* Allocate memory for request ring */
73208dfd
AC		 3057 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3058 if (!*req) {
7c3df132
SK		 3059 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3060 "Failed to allocate memory for req.\n");
e315cd28
AC		 3061 goto fail_req;
3062 }
73208dfd
AC		 3063 (*req)->length = req_len;
3064 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3065 ((*req)->length + 1) * sizeof(request_t),
3066 &(*req)->dma, GFP_KERNEL);
3067 if (!(*req)->ring) {
7c3df132
SK		 3068 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3069 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3070 goto fail_req_ring;
3071 }
3072 /* Allocate memory for response ring */
73208dfd
AC		 3073 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3074 if (!*rsp) {
7c3df132
SK		 3075 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3076 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3077 goto fail_rsp;
3078 }
73208dfd
AC		 3079 (*rsp)->hw = ha;
3080 (*rsp)->length = rsp_len;
3081 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3082 ((*rsp)->length + 1) * sizeof(response_t),
3083 &(*rsp)->dma, GFP_KERNEL);
3084 if (!(*rsp)->ring) {
7c3df132
SK		 3085 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3086 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3087 goto fail_rsp_ring;
3088 }
73208dfd
AC		 3089 (*req)->rsp = *rsp;
3090 (*rsp)->req = *req;
7c3df132
SK		 3091 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3092 "req=%p req->length=%d req->ring=%p rsp=%p "
3093 "rsp->length=%d rsp->ring=%p.\n",
3094 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3095 (*rsp)->ring);
73208dfd
AC		 3096 /* Allocate memory for NVRAM data for vports */
3097 if (ha->nvram_npiv_size) {
3098 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3099 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3100 if (!ha->npiv_info) {
7c3df132
SK		 3101 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3102 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3103 goto fail_npiv_info;
3104 }
3105 } else
3106 ha->npiv_info = NULL;
e8711085 3107
b64b0e8f 3108 /* Get consistent memory allocated for EX-INIT-CB. */
6246b8a1 3109 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) {
b64b0e8f
AV		 3110 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3111 &ha->ex_init_cb_dma);
3112 if (!ha->ex_init_cb)
3113 goto fail_ex_init_cb;
7c3df132
SK		 3114 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3115 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3116 }
3117
a9083016
GM		 3118 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3119
5ff1d584
AV		 3120 /* Get consistent memory allocated for Async Port-Database. */
3121 if (!IS_FWI2_CAPABLE(ha)) {
3122 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3123 &ha->async_pd_dma);
3124 if (!ha->async_pd)
3125 goto fail_async_pd;
7c3df132
SK		 3126 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3127 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3128 }
3129
e315cd28
AC		 3130 INIT_LIST_HEAD(&ha->vp_list);
3131 return 1;
3132
5ff1d584
AV		 3133fail_async_pd:
3134 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3135fail_ex_init_cb:
3136 kfree(ha->npiv_info);
73208dfd
AC		 3137fail_npiv_info:
3138 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3139 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3140 (*rsp)->ring = NULL;
3141 (*rsp)->dma = 0;
e315cd28 3142fail_rsp_ring:
73208dfd 3143 kfree(*rsp);
e315cd28 3144fail_rsp:
73208dfd
AC		 3145 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3146 sizeof(request_t), (*req)->ring, (*req)->dma);
3147 (*req)->ring = NULL;
3148 (*req)->dma = 0;
e315cd28 3149fail_req_ring:
73208dfd 3150 kfree(*req);
e315cd28
AC		 3151fail_req:
3152 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3153 ha->ct_sns, ha->ct_sns_dma);
3154 ha->ct_sns = NULL;
3155 ha->ct_sns_dma = 0;
e8711085
AV		 3156fail_free_ms_iocb:
3157 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3158 ha->ms_iocb = NULL;
3159 ha->ms_iocb_dma = 0;
e315cd28 3160fail_dma_pool:
bad75002 3161 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3162 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3163 ha->fcp_cmnd_dma_pool = NULL;
3164 }
3165fail_dl_dma_pool:
bad75002 3166 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3167 dma_pool_destroy(ha->dl_dma_pool);
3168 ha->dl_dma_pool = NULL;
3169 }
3170fail_s_dma_pool:
e315cd28
AC		 3171 dma_pool_destroy(ha->s_dma_pool);
3172 ha->s_dma_pool = NULL;
e8711085
AV		 3173fail_free_nvram:
3174 kfree(ha->nvram);
3175 ha->nvram = NULL;
a9083016
GM		 3176fail_free_ctx_mempool:
3177 mempool_destroy(ha->ctx_mempool);
3178 ha->ctx_mempool = NULL;
e8711085
AV		 3179fail_free_srb_mempool:
3180 mempool_destroy(ha->srb_mempool);
3181 ha->srb_mempool = NULL;
e8711085 3182fail_free_gid_list:
642ef983
CD		 3183 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3184 ha->gid_list,
e315cd28 3185 ha->gid_list_dma);
e8711085
AV		 3186 ha->gid_list = NULL;
3187 ha->gid_list_dma = 0;
e315cd28
AC		 3188fail_free_init_cb:
3189 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3190 ha->init_cb_dma);
3191 ha->init_cb = NULL;
3192 ha->init_cb_dma = 0;
e8711085 3193fail:
7c3df132
SK		 3194 ql_log(ql_log_fatal, NULL, 0x0030,
3195 "Memory allocation failure.\n");
e8711085 3196 return -ENOMEM;
1da177e4
LT		 3197}
3198
3199/*
e30d1756
MI		 3200* qla2x00_free_fw_dump
3201* Frees fw dump stuff.
1da177e4
LT		 3202*
3203* Input:
e30d1756 3204* ha = adapter block pointer.
1da177e4 3205*/
a824ebb3 3206static void
e30d1756 3207qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3208{
df613b96
AV		 3209 if (ha->fce)
3210 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
e30d1756 3211 ha->fce_dma);
df613b96 3212
a7a167bf
AV		 3213 if (ha->fw_dump) {
3214 if (ha->eft)
3215 dma_free_coherent(&ha->pdev->dev,
e30d1756 3216 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
a7a167bf
AV		 3217 vfree(ha->fw_dump);
3218 }
e30d1756
MI		 3219 ha->fce = NULL;
3220 ha->fce_dma = 0;
3221 ha->eft = NULL;
3222 ha->eft_dma = 0;
3223 ha->fw_dump = NULL;
3224 ha->fw_dumped = 0;
3225 ha->fw_dump_reading = 0;
3226}
3227
3228/*
3229* qla2x00_mem_free
3230* Frees all adapter allocated memory.
3231*
3232* Input:
3233* ha = adapter block pointer.
3234*/
3235static void
3236qla2x00_mem_free(struct qla_hw_data *ha)
3237{
3238 qla2x00_free_fw_dump(ha);
3239
3240 if (ha->srb_mempool)
3241 mempool_destroy(ha->srb_mempool);
a7a167bf 3242
11bbc1d8
AV		 3243 if (ha->dcbx_tlv)
3244 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3245 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3246
ce0423f4
AV		 3247 if (ha->xgmac_data)
3248 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3249 ha->xgmac_data, ha->xgmac_data_dma);
3250
1da177e4
LT		 3251 if (ha->sns_cmd)
3252 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3253 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3254
3255 if (ha->ct_sns)
3256 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3257 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3258
88729e53
AV		 3259 if (ha->sfp_data)
3260 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3261
1da177e4
LT		 3262 if (ha->ms_iocb)
3263 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3264
b64b0e8f 3265 if (ha->ex_init_cb)
a9083016
GM		 3266 dma_pool_free(ha->s_dma_pool,
3267 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3268
5ff1d584
AV		 3269 if (ha->async_pd)
3270 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3271
1da177e4
LT		 3272 if (ha->s_dma_pool)
3273 dma_pool_destroy(ha->s_dma_pool);
3274
1da177e4 3275 if (ha->gid_list)
642ef983
CD		 3276 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3277 ha->gid_list, ha->gid_list_dma);
1da177e4 3278
a9083016
GM		 3279 if (IS_QLA82XX(ha)) {
3280 if (!list_empty(&ha->gbl_dsd_list)) {
3281 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3282
3283 /* clean up allocated prev pool */
3284 list_for_each_entry_safe(dsd_ptr,
3285 tdsd_ptr, &ha->gbl_dsd_list, list) {
3286 dma_pool_free(ha->dl_dma_pool,
3287 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3288 list_del(&dsd_ptr->list);
3289 kfree(dsd_ptr);
3290 }
3291 }
3292 }
3293
3294 if (ha->dl_dma_pool)
3295 dma_pool_destroy(ha->dl_dma_pool);
3296
3297 if (ha->fcp_cmnd_dma_pool)
3298 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3299
3300 if (ha->ctx_mempool)
3301 mempool_destroy(ha->ctx_mempool);
3302
e315cd28
AC		 3303 if (ha->init_cb)
3304 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3305 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3306 vfree(ha->optrom_buffer);
3307 kfree(ha->nvram);
73208dfd 3308 kfree(ha->npiv_info);
7a67735b 3309 kfree(ha->swl);
1da177e4 3310
e8711085 3311 ha->srb_mempool = NULL;
a9083016 3312 ha->ctx_mempool = NULL;
1da177e4
LT		 3313 ha->sns_cmd = NULL;
3314 ha->sns_cmd_dma = 0;
3315 ha->ct_sns = NULL;
3316 ha->ct_sns_dma = 0;
3317 ha->ms_iocb = NULL;
3318 ha->ms_iocb_dma = 0;
1da177e4
LT		 3319 ha->init_cb = NULL;
3320 ha->init_cb_dma = 0;
b64b0e8f
AV		 3321 ha->ex_init_cb = NULL;
3322 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3323 ha->async_pd = NULL;
3324 ha->async_pd_dma = 0;
1da177e4
LT		 3325
3326 ha->s_dma_pool = NULL;
a9083016
GM		 3327 ha->dl_dma_pool = NULL;
3328 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3329
1da177e4
LT		 3330 ha->gid_list = NULL;
3331 ha->gid_list_dma = 0;
e315cd28 3332}
1da177e4 3333
e315cd28
AC		 3334struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3335 struct qla_hw_data *ha)
3336{
3337 struct Scsi_Host *host;
3338 struct scsi_qla_host *vha = NULL;
854165f4 3339
e315cd28
AC		 3340 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3341 if (host == NULL) {
7c3df132
SK		 3342 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3343 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3344 goto fail;
3345 }
3346
3347 /* Clear our data area */
3348 vha = shost_priv(host);
3349 memset(vha, 0, sizeof(scsi_qla_host_t));
3350
3351 vha->host = host;
3352 vha->host_no = host->host_no;
3353 vha->hw = ha;
3354
3355 INIT_LIST_HEAD(&vha->vp_fcports);
3356 INIT_LIST_HEAD(&vha->work_list);
3357 INIT_LIST_HEAD(&vha->list);
3358
f999f4c1
AV		 3359 spin_lock_init(&vha->work_lock);
3360
e315cd28 3361 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3362 ql_dbg(ql_dbg_init, vha, 0x0041,
3363 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3364 vha->host, vha->hw, vha,
3365 dev_name(&(ha->pdev->dev)));
3366
e315cd28
AC		 3367 return vha;
3368
3369fail:
3370 return vha;
1da177e4
LT		 3371}
3372
01ef66bb 3373static struct qla_work_evt *
f999f4c1 3374qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3375{
3376 struct qla_work_evt *e;
feafb7b1
AE		 3377 uint8_t bail;
3378
3379 QLA_VHA_MARK_BUSY(vha, bail);
3380 if (bail)
3381 return NULL;
0971de7f 3382
f999f4c1 3383 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3384 if (!e) {
3385 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3386 return NULL;
feafb7b1 3387 }
0971de7f
AV		 3388
3389 INIT_LIST_HEAD(&e->list);
3390 e->type = type;
3391 e->flags = QLA_EVT_FLAG_FREE;
3392 return e;
3393}
3394
01ef66bb 3395static int
f999f4c1 3396qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3397{
f999f4c1 3398 unsigned long flags;
0971de7f 3399
f999f4c1 3400 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3401 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3402 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3403 qla2xxx_wake_dpc(vha);
f999f4c1 3404
0971de7f
AV		 3405 return QLA_SUCCESS;
3406}
3407
3408int
e315cd28 3409qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3410 u32 data)
3411{
3412 struct qla_work_evt *e;
3413
f999f4c1 3414 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3415 if (!e)
3416 return QLA_FUNCTION_FAILED;
3417
3418 e->u.aen.code = code;
3419 e->u.aen.data = data;
f999f4c1 3420 return qla2x00_post_work(vha, e);
0971de7f
AV		 3421}
3422
8a659571
AV		 3423int
3424qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3425{
3426 struct qla_work_evt *e;
3427
f999f4c1 3428 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3429 if (!e)
3430 return QLA_FUNCTION_FAILED;
3431
3432 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3433 return qla2x00_post_work(vha, e);
8a659571
AV		 3434}
3435
ac280b67
AV		 3436#define qla2x00_post_async_work(name, type) \
3437int qla2x00_post_async_##name##_work( \
3438 struct scsi_qla_host *vha, \
3439 fc_port_t *fcport, uint16_t *data) \
3440{ \
3441 struct qla_work_evt *e; \
3442 \
3443 e = qla2x00_alloc_work(vha, type); \
3444 if (!e) \
3445 return QLA_FUNCTION_FAILED; \
3446 \
3447 e->u.logio.fcport = fcport; \
3448 if (data) { \
3449 e->u.logio.data[0] = data[0]; \
3450 e->u.logio.data[1] = data[1]; \
3451 } \
3452 return qla2x00_post_work(vha, e); \
3453}
3454
3455qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3456qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3457qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3458qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3459qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3460qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3461
3420d36c
AV		 3462int
3463qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3464{
3465 struct qla_work_evt *e;
3466
3467 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3468 if (!e)
3469 return QLA_FUNCTION_FAILED;
3470
3471 e->u.uevent.code = code;
3472 return qla2x00_post_work(vha, e);
3473}
3474
3475static void
3476qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3477{
3478 char event_string[40];
3479 char *envp[] = { event_string, NULL };
3480
3481 switch (code) {
3482 case QLA_UEVENT_CODE_FW_DUMP:
3483 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3484 vha->host_no);
3485 break;
3486 default:
3487 /* do nothing */
3488 break;
3489 }
3490 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3491}
3492
ac280b67 3493void
e315cd28 3494qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3495{
f999f4c1
AV		 3496 struct qla_work_evt *e, *tmp;
3497 unsigned long flags;
3498 LIST_HEAD(work);
0971de7f 3499
f999f4c1
AV		 3500 spin_lock_irqsave(&vha->work_lock, flags);
3501 list_splice_init(&vha->work_list, &work);
3502 spin_unlock_irqrestore(&vha->work_lock, flags);
3503
3504 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3505 list_del_init(&e->list);
0971de7f
AV		 3506
3507 switch (e->type) {
3508 case QLA_EVT_AEN:
e315cd28 3509 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3510 e->u.aen.code, e->u.aen.data);
3511 break;
8a659571
AV		 3512 case QLA_EVT_IDC_ACK:
3513 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3514 break;
ac280b67
AV		 3515 case QLA_EVT_ASYNC_LOGIN:
3516 qla2x00_async_login(vha, e->u.logio.fcport,
3517 e->u.logio.data);
3518 break;
3519 case QLA_EVT_ASYNC_LOGIN_DONE:
3520 qla2x00_async_login_done(vha, e->u.logio.fcport,
3521 e->u.logio.data);
3522 break;
3523 case QLA_EVT_ASYNC_LOGOUT:
3524 qla2x00_async_logout(vha, e->u.logio.fcport);
3525 break;
3526 case QLA_EVT_ASYNC_LOGOUT_DONE:
3527 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3528 e->u.logio.data);
3529 break;
5ff1d584
AV		 3530 case QLA_EVT_ASYNC_ADISC:
3531 qla2x00_async_adisc(vha, e->u.logio.fcport,
3532 e->u.logio.data);
3533 break;
3534 case QLA_EVT_ASYNC_ADISC_DONE:
3535 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3536 e->u.logio.data);
3537 break;
3420d36c
AV		 3538 case QLA_EVT_UEVENT:
3539 qla2x00_uevent_emit(vha, e->u.uevent.code);
3540 break;
0971de7f
AV		 3541 }
3542 if (e->flags & QLA_EVT_FLAG_FREE)
3543 kfree(e);
feafb7b1
AE		 3544
3545 /* For each work completed decrement vha ref count */
3546 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3547 }
e315cd28 3548}
f999f4c1 3549
e315cd28
AC		 3550/* Relogins all the fcports of a vport
3551 * Context: dpc thread
3552 */
3553void qla2x00_relogin(struct scsi_qla_host *vha)
3554{
3555 fc_port_t *fcport;
c6b2fca8 3556 int status;
e315cd28
AC		 3557 uint16_t next_loopid = 0;
3558 struct qla_hw_data *ha = vha->hw;
ac280b67 3559 uint16_t data[2];
e315cd28
AC		 3560
3561 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3562 /*
3563 * If the port is not ONLINE then try to login
3564 * to it if we haven't run out of retries.
3565 */
5ff1d584
AV		 3566 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3567 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 3568 fcport->login_retry--;
e315cd28 3569 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 3570 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 3571 ha->isp_ops->fabric_logout(vha,
3572 fcport->loop_id,
3573 fcport->d_id.b.domain,
3574 fcport->d_id.b.area,
3575 fcport->d_id.b.al_pa);
3576
03bcfb57
JC		 3577 if (fcport->loop_id == FC_NO_LOOP_ID) {
3578 fcport->loop_id = next_loopid =
3579 ha->min_external_loopid;
3580 status = qla2x00_find_new_loop_id(
3581 vha, fcport);
3582 if (status != QLA_SUCCESS) {
3583 /* Ran out of IDs to use */
3584 break;
3585 }
3586 }
3587
ac280b67 3588 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 3589 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3590 data[0] = 0;
3591 data[1] = QLA_LOGIO_LOGIN_RETRIED;
3592 status = qla2x00_post_async_login_work(
3593 vha, fcport, data);
3594 if (status == QLA_SUCCESS)
3595 continue;
3596 /* Attempt a retry. */
3597 status = 1;
aaf4d3e2 3598 } else {
ac280b67
AV		 3599 status = qla2x00_fabric_login(vha,
3600 fcport, &next_loopid);
aaf4d3e2
SK		 3601 if (status == QLA_SUCCESS) {
3602 int status2;
3603 uint8_t opts;
3604
3605 opts = 0;
3606 if (fcport->flags &
3607 FCF_FCP2_DEVICE)
3608 opts |= BIT_1;
3609 status2 =
3610 qla2x00_get_port_database(
3611 vha, fcport,
3612 opts);
3613 if (status2 != QLA_SUCCESS)
3614 status = 1;
3615 }
3616 }
e315cd28
AC		 3617 } else
3618 status = qla2x00_local_device_login(vha,
3619 fcport);
3620
e315cd28
AC		 3621 if (status == QLA_SUCCESS) {
3622 fcport->old_loop_id = fcport->loop_id;
3623
7c3df132
SK		 3624 ql_dbg(ql_dbg_disc, vha, 0x2003,
3625 "Port login OK: logged in ID 0x%x.\n",
3626 fcport->loop_id);
e315cd28
AC		 3627
3628 qla2x00_update_fcport(vha, fcport);
3629
3630 } else if (status == 1) {
3631 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3632 /* retry the login again */
7c3df132
SK		 3633 ql_dbg(ql_dbg_disc, vha, 0x2007,
3634 "Retrying %d login again loop_id 0x%x.\n",
3635 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 3636 } else {
3637 fcport->login_retry = 0;
3638 }
3639
3640 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
3641 fcport->loop_id = FC_NO_LOOP_ID;
3642 }
3643 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3644 break;
0971de7f 3645 }
0971de7f
AV		 3646}
3647
1da177e4
LT		 3648/**************************************************************************
3649* qla2x00_do_dpc
3650* This kernel thread is a task that is schedule by the interrupt handler
3651* to perform the background processing for interrupts.
3652*
3653* Notes:
3654* This task always run in the context of a kernel thread. It
3655* is kick-off by the driver's detect code and starts up
3656* up one per adapter. It immediately goes to sleep and waits for
3657* some fibre event. When either the interrupt handler or
3658* the timer routine detects a event it will one of the task
3659* bits then wake us up.
3660**************************************************************************/
3661static int
3662qla2x00_do_dpc(void *data)
3663{
2c3dfe3f 3664 int rval;
e315cd28
AC		 3665 scsi_qla_host_t *base_vha;
3666 struct qla_hw_data *ha;
1da177e4 3667
e315cd28
AC		 3668 ha = (struct qla_hw_data *)data;
3669 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 3670
1da177e4
LT		 3671 set_user_nice(current, -20);
3672
563585ec 3673 set_current_state(TASK_INTERRUPTIBLE);
39a11240 3674 while (!kthread_should_stop()) {
7c3df132
SK		 3675 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
3676 "DPC handler sleeping.\n");
1da177e4 3677
39a11240
CH		 3678 schedule();
3679 __set_current_state(TASK_RUNNING);
1da177e4 3680
c142caf0
AV		 3681 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
3682 goto end_loop;
1da177e4 3683
85880801 3684 if (ha->flags.eeh_busy) {
7c3df132
SK		 3685 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
3686 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 3687 goto end_loop;
85880801
AV		 3688 }
3689
1da177e4
LT		 3690 ha->dpc_active = 1;
3691
5f28d2d7
SK		 3692 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
3693 "DPC handler waking up, dpc_flags=0x%lx.\n",
3694 base_vha->dpc_flags);
1da177e4 3695
e315cd28 3696 qla2x00_do_work(base_vha);
0971de7f 3697
a9083016
GM		 3698 if (IS_QLA82XX(ha)) {
3699 if (test_and_clear_bit(ISP_UNRECOVERABLE,
3700 &base_vha->dpc_flags)) {
3701 qla82xx_idc_lock(ha);
3702 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3703 QLA82XX_DEV_FAILED);
3704 qla82xx_idc_unlock(ha);
7c3df132
SK		 3705 ql_log(ql_log_info, base_vha, 0x4004,
3706 "HW State: FAILED.\n");
a9083016
GM		 3707 qla82xx_device_state_handler(base_vha);
3708 continue;
3709 }
3710
3711 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
3712 &base_vha->dpc_flags)) {
3713
7c3df132
SK		 3714 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
3715 "FCoE context reset scheduled.\n");
a9083016
GM		 3716 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
3717 &base_vha->dpc_flags))) {
3718 if (qla82xx_fcoe_ctx_reset(base_vha)) {
3719 /* FCoE-ctx reset failed.
3720 * Escalate to chip-reset
3721 */
3722 set_bit(ISP_ABORT_NEEDED,
3723 &base_vha->dpc_flags);
3724 }
3725 clear_bit(ABORT_ISP_ACTIVE,
3726 &base_vha->dpc_flags);
3727 }
3728
7c3df132
SK		 3729 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
3730 "FCoE context reset end.\n");
a9083016
GM		 3731 }
3732 }
3733
e315cd28
AC		 3734 if (test_and_clear_bit(ISP_ABORT_NEEDED,
3735 &base_vha->dpc_flags)) {
1da177e4 3736
7c3df132
SK		 3737 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
3738 "ISP abort scheduled.\n");
1da177e4 3739 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 3740 &base_vha->dpc_flags))) {
1da177e4 3741
a9083016 3742 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 3743 /* failed. retry later */
3744 set_bit(ISP_ABORT_NEEDED,
e315cd28 3745 &base_vha->dpc_flags);
99363ef8 3746 }
e315cd28
AC		 3747 clear_bit(ABORT_ISP_ACTIVE,
3748 &base_vha->dpc_flags);
99363ef8
SJ		 3749 }
3750
7c3df132
SK		 3751 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
3752 "ISP abort end.\n");
1da177e4
LT		 3753 }
3754
e315cd28
AC		 3755 if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
3756 qla2x00_update_fcports(base_vha);
3757 clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
c9c5ced9 3758 }
d97994dc 3759
579d12b5 3760 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 3761 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
3762 "Quiescence mode scheduled.\n");
579d12b5
SK		 3763 qla82xx_device_state_handler(base_vha);
3764 clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags);
3765 if (!ha->flags.quiesce_owner) {
3766 qla2x00_perform_loop_resync(base_vha);
3767
3768 qla82xx_idc_lock(ha);
3769 qla82xx_clear_qsnt_ready(base_vha);
3770 qla82xx_idc_unlock(ha);
3771 }
7c3df132
SK		 3772 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
3773 "Quiescence mode end.\n");
579d12b5
SK		 3774 }
3775
e315cd28
AC		 3776 if (test_and_clear_bit(RESET_MARKER_NEEDED,
3777 &base_vha->dpc_flags) &&
3778 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 3779
7c3df132
SK		 3780 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
3781 "Reset marker scheduled.\n");
e315cd28
AC		 3782 qla2x00_rst_aen(base_vha);
3783 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 3784 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
3785 "Reset marker end.\n");
1da177e4
LT		 3786 }
3787
3788 /* Retry each device up to login retry count */
e315cd28
AC		 3789 if ((test_and_clear_bit(RELOGIN_NEEDED,
3790 &base_vha->dpc_flags)) &&
3791 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
3792 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 3793
7c3df132
SK		 3794 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
3795 "Relogin scheduled.\n");
e315cd28 3796 qla2x00_relogin(base_vha);
7c3df132
SK		 3797 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
3798 "Relogin end.\n");
1da177e4
LT		 3799 }
3800
e315cd28
AC		 3801 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
3802 &base_vha->dpc_flags)) {
1da177e4 3803
7c3df132
SK		 3804 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
3805 "Loop resync scheduled.\n");
1da177e4
LT		 3806
3807 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 3808 &base_vha->dpc_flags))) {
1da177e4 3809
e315cd28 3810 rval = qla2x00_loop_resync(base_vha);
1da177e4 3811
e315cd28
AC		 3812 clear_bit(LOOP_RESYNC_ACTIVE,
3813 &base_vha->dpc_flags);
1da177e4
LT		 3814 }
3815
7c3df132
SK		 3816 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
3817 "Loop resync end.\n");
1da177e4
LT		 3818 }
3819
e315cd28
AC		 3820 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
3821 atomic_read(&base_vha->loop_state) == LOOP_READY) {
3822 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
3823 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 3824 }
3825
1da177e4 3826 if (!ha->interrupts_on)
fd34f556 3827 ha->isp_ops->enable_intrs(ha);
1da177e4 3828
e315cd28
AC		 3829 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
3830 &base_vha->dpc_flags))
3831 ha->isp_ops->beacon_blink(base_vha);
f6df144c 3832
e315cd28 3833 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 3834
1da177e4 3835 ha->dpc_active = 0;
c142caf0 3836end_loop:
563585ec 3837 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 3838 } /* End of while(1) */
563585ec 3839 __set_current_state(TASK_RUNNING);
1da177e4 3840
7c3df132
SK		 3841 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
3842 "DPC handler exiting.\n");
1da177e4
LT		 3843
3844 /*
3845 * Make sure that nobody tries to wake us up again.
3846 */
1da177e4
LT		 3847 ha->dpc_active = 0;
3848
ac280b67
AV		 3849 /* Cleanup any residual CTX SRBs. */
3850 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3851
39a11240
CH		 3852 return 0;
3853}
3854
3855void
e315cd28 3856qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 3857{
e315cd28 3858 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 3859 struct task_struct *t = ha->dpc_thread;
3860
e315cd28 3861 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 3862 wake_up_process(t);
1da177e4
LT		 3863}
3864
1da177e4
LT		 3865/*
3866* qla2x00_rst_aen
3867* Processes asynchronous reset.
3868*
3869* Input:
3870* ha = adapter block pointer.
3871*/
3872static void
e315cd28 3873qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 3874{
e315cd28
AC		 3875 if (vha->flags.online && !vha->flags.reset_active &&
3876 !atomic_read(&vha->loop_down_timer) &&
3877 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 3878 do {
e315cd28 3879 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3880
3881 /*
3882 * Issue marker command only when we are going to start
3883 * the I/O.
3884 */
e315cd28
AC		 3885 vha->marker_needed = 1;
3886 } while (!atomic_read(&vha->loop_down_timer) &&
3887 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 3888 }
3889}
3890
1da177e4
LT		 3891/**************************************************************************
3892* qla2x00_timer
3893*
3894* Description:
3895* One second timer
3896*
3897* Context: Interrupt
3898***************************************************************************/
2c3dfe3f 3899void
e315cd28 3900qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 3901{
1da177e4 3902 unsigned long cpu_flags = 0;
1da177e4
LT		 3903 int start_dpc = 0;
3904 int index;
3905 srb_t *sp;
85880801 3906 uint16_t w;
e315cd28 3907 struct qla_hw_data *ha = vha->hw;
73208dfd 3908 struct req_que *req;
85880801 3909
a5b36321 3910 if (ha->flags.eeh_busy) {
7c3df132
SK		 3911 ql_dbg(ql_dbg_timer, vha, 0x6000,
3912 "EEH = %d, restarting timer.\n",
3913 ha->flags.eeh_busy);
a5b36321
LC		 3914 qla2x00_restart_timer(vha, WATCH_INTERVAL);
3915 return;
3916 }
3917
85880801
AV		 3918 /* Hardware read to raise pending EEH errors during mailbox waits. */
3919 if (!pci_channel_offline(ha->pdev))
3920 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
1da177e4 3921
cefcaba6
SK		 3922 /* Make sure qla82xx_watchdog is run only for physical port */
3923 if (!vha->vp_idx && IS_QLA82XX(ha)) {
579d12b5
SK		 3924 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
3925 start_dpc++;
3926 qla82xx_watchdog(vha);
3927 }
3928
1da177e4 3929 /* Loop down handler. */
e315cd28 3930 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 3931 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
3932 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 3933 && vha->flags.online) {
1da177e4 3934
e315cd28
AC		 3935 if (atomic_read(&vha->loop_down_timer) ==
3936 vha->loop_down_abort_time) {
1da177e4 3937
7c3df132
SK		 3938 ql_log(ql_log_info, vha, 0x6008,
3939 "Loop down - aborting the queues before time expires.\n");
1da177e4 3940
e315cd28
AC		 3941 if (!IS_QLA2100(ha) && vha->link_down_timeout)
3942 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 3943
f08b7251
AV		 3944 /*
3945 * Schedule an ISP abort to return any FCP2-device
3946 * commands.
3947 */
2c3dfe3f 3948 /* NPIV - scan physical port only */
e315cd28 3949 if (!vha->vp_idx) {
2c3dfe3f
SJ		 3950 spin_lock_irqsave(&ha->hardware_lock,
3951 cpu_flags);
73208dfd 3952 req = ha->req_q_map[0];
2c3dfe3f
SJ		 3953 for (index = 1;
3954 index < MAX_OUTSTANDING_COMMANDS;
3955 index++) {
3956 fc_port_t *sfcp;
3957
e315cd28 3958 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 3959 if (!sp)
3960 continue;
9ba56b95 3961 if (sp->type != SRB_SCSI_CMD)
cf53b069 3962 continue;
2c3dfe3f 3963 sfcp = sp->fcport;
f08b7251 3964 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 3965 continue;
bdf79621 3966
8f7daead
GM		 3967 if (IS_QLA82XX(ha))
3968 set_bit(FCOE_CTX_RESET_NEEDED,
3969 &vha->dpc_flags);
3970 else
3971 set_bit(ISP_ABORT_NEEDED,
e315cd28 3972 &vha->dpc_flags);
2c3dfe3f
SJ		 3973 break;
3974 }
3975 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 3976 cpu_flags);
1da177e4 3977 }
1da177e4
LT		 3978 start_dpc++;
3979 }
3980
3981 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 3982 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 3983 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 3984 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 3985 "Loop down - aborting ISP.\n");
3986
8f7daead
GM		 3987 if (IS_QLA82XX(ha))
3988 set_bit(FCOE_CTX_RESET_NEEDED,
3989 &vha->dpc_flags);
3990 else
3991 set_bit(ISP_ABORT_NEEDED,
3992 &vha->dpc_flags);
1da177e4
LT		 3993 }
3994 }
7c3df132
SK		 3995 ql_dbg(ql_dbg_timer, vha, 0x600a,
3996 "Loop down - seconds remaining %d.\n",
3997 atomic_read(&vha->loop_down_timer));
1da177e4
LT		 3998 }
3999
cefcaba6
SK		 4000 /* Check if beacon LED needs to be blinked for physical host only */
4001 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc
SK		 4002 /* There is no beacon_blink function for ISP82xx */
4003 if (!IS_QLA82XX(ha)) {
4004 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
4005 start_dpc++;
4006 }
f6df144c 4007 }
4008
550bf57d 4009 /* Process any deferred work. */
e315cd28 4010 if (!list_empty(&vha->work_list))
550bf57d
AV		 4011 start_dpc++;
4012
1da177e4 4013 /* Schedule the DPC routine if needed */
e315cd28
AC		 4014 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
4015 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
4016 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 4017 start_dpc ||
e315cd28
AC		 4018 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
4019 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 4020 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
4021 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 4022 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7c3df132
SK		 4023 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
4024 ql_dbg(ql_dbg_timer, vha, 0x600b,
4025 "isp_abort_needed=%d loop_resync_needed=%d "
4026 "fcport_update_needed=%d start_dpc=%d "
4027 "reset_marker_needed=%d",
4028 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
4029 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
4030 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
4031 start_dpc,
4032 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
4033 ql_dbg(ql_dbg_timer, vha, 0x600c,
4034 "beacon_blink_needed=%d isp_unrecoverable=%d "
4035 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
4036 "relogin_needed=%d.\n",
4037 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
4038 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
4039 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
4040 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
4041 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 4042 qla2xxx_wake_dpc(vha);
7c3df132 4043 }
1da177e4 4044
e315cd28 4045 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 4046}
4047
5433383e
AV		 4048/* Firmware interface routines. */
4049
6246b8a1 4050#define FW_BLOBS 10
5433383e
AV		 4051#define FW_ISP21XX 0
4052#define FW_ISP22XX 1
4053#define FW_ISP2300 2
4054#define FW_ISP2322 3
48c02fde 4055#define FW_ISP24XX 4
c3a2f0df 4056#define FW_ISP25XX 5
3a03eb79 4057#define FW_ISP81XX 6
a9083016 4058#define FW_ISP82XX 7
6246b8a1
GM		 4059#define FW_ISP2031 8
4060#define FW_ISP8031 9
5433383e 4061
bb8ee499
AV		 4062#define FW_FILE_ISP21XX "ql2100_fw.bin"
4063#define FW_FILE_ISP22XX "ql2200_fw.bin"
4064#define FW_FILE_ISP2300 "ql2300_fw.bin"
4065#define FW_FILE_ISP2322 "ql2322_fw.bin"
4066#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 4067#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 4068#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 4069#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 4070#define FW_FILE_ISP2031 "ql2600_fw.bin"
4071#define FW_FILE_ISP8031 "ql8300_fw.bin"
bb8ee499 4072
e1e82b6f 4073static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 4074
4075static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 4076 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
4077 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
4078 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
4079 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
4080 { .name = FW_FILE_ISP24XX, },
c3a2f0df 4081 { .name = FW_FILE_ISP25XX, },
3a03eb79 4082 { .name = FW_FILE_ISP81XX, },
a9083016 4083 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 4084 { .name = FW_FILE_ISP2031, },
4085 { .name = FW_FILE_ISP8031, },
5433383e
AV		 4086};
4087
4088struct fw_blob *
e315cd28 4089qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 4090{
e315cd28 4091 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 4092 struct fw_blob *blob;
4093
5433383e
AV		 4094 if (IS_QLA2100(ha)) {
4095 blob = &qla_fw_blobs[FW_ISP21XX];
4096 } else if (IS_QLA2200(ha)) {
4097 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 4098 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 4099 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 4100 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 4101 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 4102 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 4103 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 4104 } else if (IS_QLA25XX(ha)) {
4105 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 4106 } else if (IS_QLA81XX(ha)) {
4107 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 4108 } else if (IS_QLA82XX(ha)) {
4109 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 4110 } else if (IS_QLA2031(ha)) {
4111 blob = &qla_fw_blobs[FW_ISP2031];
4112 } else if (IS_QLA8031(ha)) {
4113 blob = &qla_fw_blobs[FW_ISP8031];
8a655229
DC		 4114 } else {
4115 return NULL;
5433383e
AV		 4116 }
4117
e1e82b6f 4118 mutex_lock(&qla_fw_lock);
5433383e
AV		 4119 if (blob->fw)
4120 goto out;
4121
4122 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 4123 ql_log(ql_log_warn, vha, 0x0063,
4124 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 4125 blob->fw = NULL;
4126 blob = NULL;
4127 goto out;
4128 }
4129
4130out:
e1e82b6f 4131 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4132 return blob;
4133}
4134
4135static void
4136qla2x00_release_firmware(void)
4137{
4138 int idx;
4139
e1e82b6f 4140 mutex_lock(&qla_fw_lock);
5433383e
AV		 4141 for (idx = 0; idx < FW_BLOBS; idx++)
4142 if (qla_fw_blobs[idx].fw)
4143 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 4144 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4145}
4146
14e660e6
SJ		 4147static pci_ers_result_t
4148qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4149{
85880801
AV		 4150 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
4151 struct qla_hw_data *ha = vha->hw;
4152
7c3df132
SK		 4153 ql_dbg(ql_dbg_aer, vha, 0x9000,
4154 "PCI error detected, state %x.\n", state);
b9b12f73 4155
14e660e6
SJ		 4156 switch (state) {
4157 case pci_channel_io_normal:
85880801 4158 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4159 return PCI_ERS_RESULT_CAN_RECOVER;
4160 case pci_channel_io_frozen:
85880801 4161 ha->flags.eeh_busy = 1;
a5b36321
LC		 4162 /* For ISP82XX complete any pending mailbox cmd */
4163 if (IS_QLA82XX(ha)) {
7190575f 4164 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 4165 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
4166 qla82xx_clear_pending_mbx(vha);
a5b36321 4167 }
90a86fc0 4168 qla2x00_free_irqs(vha);
14e660e6 4169 pci_disable_device(pdev);
bddd2d65
LC		 4170 /* Return back all IOs */
4171 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 4172 return PCI_ERS_RESULT_NEED_RESET;
4173 case pci_channel_io_perm_failure:
85880801
AV		 4174 ha->flags.pci_channel_io_perm_failure = 1;
4175 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 4176 return PCI_ERS_RESULT_DISCONNECT;
4177 }
4178 return PCI_ERS_RESULT_NEED_RESET;
4179}
4180
4181static pci_ers_result_t
4182qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
4183{
4184 int risc_paused = 0;
4185 uint32_t stat;
4186 unsigned long flags;
e315cd28
AC		 4187 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4188 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4189 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4190 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
4191
bcc5b6d3
SK		 4192 if (IS_QLA82XX(ha))
4193 return PCI_ERS_RESULT_RECOVERED;
4194
14e660e6
SJ		 4195 spin_lock_irqsave(&ha->hardware_lock, flags);
4196 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
4197 stat = RD_REG_DWORD(&reg->hccr);
4198 if (stat & HCCR_RISC_PAUSE)
4199 risc_paused = 1;
4200 } else if (IS_QLA23XX(ha)) {
4201 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
4202 if (stat & HSR_RISC_PAUSED)
4203 risc_paused = 1;
4204 } else if (IS_FWI2_CAPABLE(ha)) {
4205 stat = RD_REG_DWORD(&reg24->host_status);
4206 if (stat & HSRX_RISC_PAUSED)
4207 risc_paused = 1;
4208 }
4209 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4210
4211 if (risc_paused) {
7c3df132
SK		 4212 ql_log(ql_log_info, base_vha, 0x9003,
4213 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 4214 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 4215
4216 return PCI_ERS_RESULT_NEED_RESET;
4217 } else
4218 return PCI_ERS_RESULT_RECOVERED;
4219}
4220
a5b36321
LC		 4221uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
4222{
4223 uint32_t rval = QLA_FUNCTION_FAILED;
4224 uint32_t drv_active = 0;
4225 struct qla_hw_data *ha = base_vha->hw;
4226 int fn;
4227 struct pci_dev *other_pdev = NULL;
4228
7c3df132
SK		 4229 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
4230 "Entered %s.\n", __func__);
a5b36321
LC		 4231
4232 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4233
4234 if (base_vha->flags.online) {
4235 /* Abort all outstanding commands,
4236 * so as to be requeued later */
4237 qla2x00_abort_isp_cleanup(base_vha);
4238 }
4239
4240
4241 fn = PCI_FUNC(ha->pdev->devfn);
4242 while (fn > 0) {
4243 fn--;
7c3df132
SK		 4244 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
4245 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 4246 other_pdev =
4247 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
4248 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
4249 fn));
4250
4251 if (!other_pdev)
4252 continue;
4253 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 4254 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
4255 "Found PCI func available and enable at 0x%x.\n",
4256 fn);
a5b36321
LC		 4257 pci_dev_put(other_pdev);
4258 break;
4259 }
4260 pci_dev_put(other_pdev);
4261 }
4262
4263 if (!fn) {
4264 /* Reset owner */
7c3df132
SK		 4265 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
4266 "This devfn is reset owner = 0x%x.\n",
4267 ha->pdev->devfn);
a5b36321
LC		 4268 qla82xx_idc_lock(ha);
4269
4270 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4271 QLA82XX_DEV_INITIALIZING);
4272
4273 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
4274 QLA82XX_IDC_VERSION);
4275
4276 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 4277 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
4278 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 4279
4280 qla82xx_idc_unlock(ha);
4281 /* Reset if device is not already reset
4282 * drv_active would be 0 if a reset has already been done
4283 */
4284 if (drv_active)
4285 rval = qla82xx_start_firmware(base_vha);
4286 else
4287 rval = QLA_SUCCESS;
4288 qla82xx_idc_lock(ha);
4289
4290 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4291 ql_log(ql_log_info, base_vha, 0x900b,
4292 "HW State: FAILED.\n");
a5b36321
LC		 4293 qla82xx_clear_drv_active(ha);
4294 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4295 QLA82XX_DEV_FAILED);
4296 } else {
7c3df132
SK		 4297 ql_log(ql_log_info, base_vha, 0x900c,
4298 "HW State: READY.\n");
a5b36321
LC		 4299 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4300 QLA82XX_DEV_READY);
4301 qla82xx_idc_unlock(ha);
7190575f 4302 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 4303 rval = qla82xx_restart_isp(base_vha);
4304 qla82xx_idc_lock(ha);
4305 /* Clear driver state register */
4306 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
4307 qla82xx_set_drv_active(base_vha);
4308 }
4309 qla82xx_idc_unlock(ha);
4310 } else {
7c3df132
SK		 4311 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
4312 "This devfn is not reset owner = 0x%x.\n",
4313 ha->pdev->devfn);
a5b36321
LC		 4314 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
4315 QLA82XX_DEV_READY)) {
7190575f 4316 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 4317 rval = qla82xx_restart_isp(base_vha);
4318 qla82xx_idc_lock(ha);
4319 qla82xx_set_drv_active(base_vha);
4320 qla82xx_idc_unlock(ha);
4321 }
4322 }
4323 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4324
4325 return rval;
4326}
4327
14e660e6
SJ		 4328static pci_ers_result_t
4329qla2xxx_pci_slot_reset(struct pci_dev *pdev)
4330{
4331 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 4332 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4333 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 4334 struct rsp_que *rsp;
4335 int rc, retries = 10;
09483916 4336
7c3df132
SK		 4337 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
4338 "Slot Reset.\n");
85880801 4339
90a86fc0
JC		 4340 /* Workaround: qla2xxx driver which access hardware earlier
4341 * needs error state to be pci_channel_io_online.
4342 * Otherwise mailbox command timesout.
4343 */
4344 pdev->error_state = pci_channel_io_normal;
4345
4346 pci_restore_state(pdev);
4347
8c1496bd
RL		 4348 /* pci_restore_state() clears the saved_state flag of the device
4349 * save restored state which resets saved_state flag
4350 */
4351 pci_save_state(pdev);
4352
09483916
BH		 4353 if (ha->mem_only)
4354 rc = pci_enable_device_mem(pdev);
4355 else
4356 rc = pci_enable_device(pdev);
14e660e6 4357
09483916 4358 if (rc) {
7c3df132 4359 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 4360 "Can't re-enable PCI device after reset.\n");
a5b36321 4361 goto exit_slot_reset;
14e660e6 4362 }
14e660e6 4363
90a86fc0
JC		 4364 rsp = ha->rsp_q_map[0];
4365 if (qla2x00_request_irqs(ha, rsp))
a5b36321 4366 goto exit_slot_reset;
90a86fc0 4367
e315cd28 4368 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 4369 goto exit_slot_reset;
4370
4371 if (IS_QLA82XX(ha)) {
4372 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
4373 ret = PCI_ERS_RESULT_RECOVERED;
4374 goto exit_slot_reset;
4375 } else
4376 goto exit_slot_reset;
4377 }
14e660e6 4378
90a86fc0
JC		 4379 while (ha->flags.mbox_busy && retries--)
4380 msleep(1000);
85880801 4381
e315cd28 4382 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 4383 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 4384 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 4385 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 4386
90a86fc0 4387
a5b36321 4388exit_slot_reset:
7c3df132
SK		 4389 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
4390 "slot_reset return %x.\n", ret);
85880801 4391
14e660e6
SJ		 4392 return ret;
4393}
4394
4395static void
4396qla2xxx_pci_resume(struct pci_dev *pdev)
4397{
e315cd28
AC		 4398 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4399 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4400 int ret;
4401
7c3df132
SK		 4402 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
4403 "pci_resume.\n");
85880801 4404
e315cd28 4405 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 4406 if (ret != QLA_SUCCESS) {
7c3df132
SK		 4407 ql_log(ql_log_fatal, base_vha, 0x9002,
4408 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 4409 }
85880801 4410
3e46f031
LC		 4411 pci_cleanup_aer_uncorrect_error_status(pdev);
4412
85880801 4413 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4414}
4415
4416static struct pci_error_handlers qla2xxx_err_handler = {
4417 .error_detected = qla2xxx_pci_error_detected,
4418 .mmio_enabled = qla2xxx_pci_mmio_enabled,
4419 .slot_reset = qla2xxx_pci_slot_reset,
4420 .resume = qla2xxx_pci_resume,
4421};
4422
5433383e 4423static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 4424 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
4425 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
4426 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
4427 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
4428 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
4429 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
4430 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
4431 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
4432 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 4433 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 4434 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
4435 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 4436 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 4437 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 4438 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 4439 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5433383e
AV		 4440 { 0 },
4441};
4442MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
4443
fca29703 4444static struct pci_driver qla2xxx_pci_driver = {
cb63067a 4445 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 4446 .driver = {
4447 .owner = THIS_MODULE,
4448 },
fca29703 4449 .id_table = qla2xxx_pci_tbl,
7ee61397 4450 .probe = qla2x00_probe_one,
4c993f76 4451 .remove = qla2x00_remove_one,
e30d1756 4452 .shutdown = qla2x00_shutdown,
14e660e6 4453 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 4454};
4455
6a03b4cd
HZ		 4456static struct file_operations apidev_fops = {
4457 .owner = THIS_MODULE,
6038f373 4458 .llseek = noop_llseek,
6a03b4cd
HZ		 4459};
4460
1da177e4
LT		 4461/**
4462 * qla2x00_module_init - Module initialization.
4463 **/
4464static int __init
4465qla2x00_module_init(void)
4466{
fca29703
AV		 4467 int ret = 0;
4468
1da177e4 4469 /* Allocate cache for SRBs. */
354d6b21 4470 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 4471 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 4472 if (srb_cachep == NULL) {
7c3df132
SK		 4473 ql_log(ql_log_fatal, NULL, 0x0001,
4474 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 4475 return -ENOMEM;
4476 }
4477
4478 /* Derive version string. */
4479 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 4480 if (ql2xextended_error_logging)
0181944f
AV		 4481 strcat(qla2x00_version_str, "-debug");
4482
1c97a12a
AV		 4483 qla2xxx_transport_template =
4484 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 4485 if (!qla2xxx_transport_template) {
4486 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 4487 ql_log(ql_log_fatal, NULL, 0x0002,
4488 "fc_attach_transport failed...Failing load!.\n");
1da177e4 4489 return -ENODEV;
2c3dfe3f 4490 }
6a03b4cd
HZ		 4491
4492 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
4493 if (apidev_major < 0) {
7c3df132
SK		 4494 ql_log(ql_log_fatal, NULL, 0x0003,
4495 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 4496 }
4497
2c3dfe3f
SJ		 4498 qla2xxx_transport_vport_template =
4499 fc_attach_transport(&qla2xxx_transport_vport_functions);
4500 if (!qla2xxx_transport_vport_template) {
4501 kmem_cache_destroy(srb_cachep);
4502 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 4503 ql_log(ql_log_fatal, NULL, 0x0004,
4504 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 4505 return -ENODEV;
2c3dfe3f 4506 }
7c3df132
SK		 4507 ql_log(ql_log_info, NULL, 0x0005,
4508 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 4509 qla2x00_version_str);
7ee61397 4510 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 4511 if (ret) {
4512 kmem_cache_destroy(srb_cachep);
4513 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 4514 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 4515 ql_log(ql_log_fatal, NULL, 0x0006,
4516 "pci_register_driver failed...ret=%d Failing load!.\n",
4517 ret);
fca29703
AV		 4518 }
4519 return ret;
1da177e4
LT		 4520}
4521
4522/**
4523 * qla2x00_module_exit - Module cleanup.
4524 **/
4525static void __exit
4526qla2x00_module_exit(void)
4527{
6a03b4cd 4528 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 4529 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 4530 qla2x00_release_firmware();
354d6b21 4531 kmem_cache_destroy(srb_cachep);
a9083016
GM		 4532 if (ctx_cachep)
4533 kmem_cache_destroy(ctx_cachep);
1da177e4 4534 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 4535 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 4536}
4537
4538module_init(qla2x00_module_init);
4539module_exit(qla2x00_module_exit);
4540
4541MODULE_AUTHOR("QLogic Corporation");
4542MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
4543MODULE_LICENSE("GPL");
4544MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 4545MODULE_FIRMWARE(FW_FILE_ISP21XX);
4546MODULE_FIRMWARE(FW_FILE_ISP22XX);
4547MODULE_FIRMWARE(FW_FILE_ISP2300);
4548MODULE_FIRMWARE(FW_FILE_ISP2322);
4549MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 4550MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)