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scsi_scan: Restrict sequential scan to 256 LUNs
[linux-block.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 83MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
3ce8866c 99 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 100
a9083016 101int ql2xshiftctondsd = 6;
f2019cb1 102module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 103MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
7e47e5ca 107int ql2xfdmienable=1;
f2019cb1 108module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 109MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 112
50280c01
CD		 113#define MAX_Q_DEPTH 32
114static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 115module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
df7baa50 119
9e522cd8
AE		 120int ql2xenabledif = 2;
121module_param(ql2xenabledif, int, S_IRUGO);
bad75002 122MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 123 " Enable T10-CRC-DIF:\n"
124 " Default is 2.\n"
125 " 0 -- No DIF Support\n"
126 " 1 -- Enable DIF for all types\n"
127 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 128
8cb2049c 129int ql2xenablehba_err_chk = 2;
bad75002
AE		 130module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
131MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 132 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 133 " Default is 2.\n"
8cb2049c
AE		 134 " 0 -- Error isolation disabled\n"
135 " 1 -- Error isolation enabled only for DIX Type 0\n"
136 " 2 -- Error isolation enabled for all Types\n");
bad75002 137
e5896bd5 138int ql2xiidmaenable=1;
f2019cb1 139module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 140MODULE_PARM_DESC(ql2xiidmaenable,
141 "Enables iIDMA settings "
142 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
143
73208dfd 144int ql2xmaxqueues = 1;
f2019cb1 145module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 146MODULE_PARM_DESC(ql2xmaxqueues,
147 "Enables MQ settings "
ae68230c
JP		 148 "Default is 1 for single queue. Set it to number "
149 "of queues in MQ mode.");
68ca949c
AC		 150
151int ql2xmultique_tag;
f2019cb1 152module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 153MODULE_PARM_DESC(ql2xmultique_tag,
154 "Enables CPU affinity settings for the driver "
155 "Default is 0 for no affinity of request and response IO. "
156 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 157
158int ql2xfwloadbin;
86e45bf6 159module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 160MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 161 "Option to specify location from which to load ISP firmware:.\n"
162 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 163 " interface.\n"
164 " 1 -- load firmware from flash.\n"
165 " 0 -- use default semantics.\n");
166
ae97c91e 167int ql2xetsenable;
f2019cb1 168module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 169MODULE_PARM_DESC(ql2xetsenable,
170 "Enables firmware ETS burst."
171 "Default is 0 - skip ETS enablement.");
172
6907869d 173int ql2xdbwr = 1;
86e45bf6 174module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 175MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 176 "Option to specify scheme for request queue posting.\n"
177 " 0 -- Regular doorbell.\n"
178 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 179
f4c496c1 180int ql2xtargetreset = 1;
f2019cb1 181module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 182MODULE_PARM_DESC(ql2xtargetreset,
183 "Enable target reset."
184 "Default is 1 - use hw defaults.");
185
4da26e16 186int ql2xgffidenable;
f2019cb1 187module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 188MODULE_PARM_DESC(ql2xgffidenable,
189 "Enables GFF_ID checks of port type. "
190 "Default is 0 - Do not use GFF_ID information.");
a9083016 191
3822263e 192int ql2xasynctmfenable;
f2019cb1 193module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 194MODULE_PARM_DESC(ql2xasynctmfenable,
195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
196 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 197
198int ql2xdontresethba;
86e45bf6 199module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 200MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 201 "Option to specify reset behaviour.\n"
202 " 0 (Default) -- Reset on failure.\n"
203 " 1 -- Do not reset on failure.\n");
ed0de87c 204
82515920
AV		 205uint ql2xmaxlun = MAX_LUNS;
206module_param(ql2xmaxlun, uint, S_IRUGO);
207MODULE_PARM_DESC(ql2xmaxlun,
208 "Defines the maximum LU number to register with the SCSI "
209 "midlayer. Default is 65535.");
210
08de2844
GM		 211int ql2xmdcapmask = 0x1F;
212module_param(ql2xmdcapmask, int, S_IRUGO);
213MODULE_PARM_DESC(ql2xmdcapmask,
214 "Set the Minidump driver capture mask level. "
6e96fa7b 215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 216
3aadff35 217int ql2xmdenable = 1;
08de2844
GM		 218module_param(ql2xmdenable, int, S_IRUGO);
219MODULE_PARM_DESC(ql2xmdenable,
220 "Enable/disable MiniDump. "
3aadff35
GM		 221 "0 - MiniDump disabled. "
222 "1 (Default) - MiniDump enabled.");
08de2844 223
1da177e4 224/*
fa2a1ce5 225 * SCSI host template entry points
1da177e4
LT		 226 */
227static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 228static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 229static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
230static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 231static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 232static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 233static int qla2xxx_eh_abort(struct scsi_cmnd *);
234static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 235static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 236static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
237static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 238
e881a172 239static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7 240static int qla2x00_change_queue_type(struct scsi_device *, int);
3491255e 241static void qla2x00_free_device(scsi_qla_host_t *);
ce7e4af7 242
a5326f86 243struct scsi_host_template qla2xxx_driver_template = {
1da177e4 244 .module = THIS_MODULE,
cb63067a 245 .name = QLA2XXX_DRIVER_NAME,
a5326f86 246 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 247
248 .eh_abort_handler = qla2xxx_eh_abort,
249 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 250 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 251 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
252 .eh_host_reset_handler = qla2xxx_eh_host_reset,
253
254 .slave_configure = qla2xxx_slave_configure,
255
256 .slave_alloc = qla2xxx_slave_alloc,
257 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 258 .scan_finished = qla2xxx_scan_finished,
259 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 260 .change_queue_depth = qla2x00_change_queue_depth,
261 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 262 .this_id = -1,
263 .cmd_per_lun = 3,
264 .use_clustering = ENABLE_CLUSTERING,
265 .sg_tablesize = SG_ALL,
266
267 .max_sectors = 0xFFFF,
afb046e2 268 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 269
270 .supported_mode = MODE_INITIATOR,
fca29703
AV		 271};
272
1da177e4 273static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 274struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 275
1da177e4
LT		 276/* TODO Convert to inlines
277 *
278 * Timer routines
279 */
1da177e4 280
2c3dfe3f 281__inline__ void
e315cd28 282qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 283{
e315cd28
AC		 284 init_timer(&vha->timer);
285 vha->timer.expires = jiffies + interval * HZ;
286 vha->timer.data = (unsigned long)vha;
287 vha->timer.function = (void (*)(unsigned long))func;
288 add_timer(&vha->timer);
289 vha->timer_active = 1;
1da177e4
LT		 290}
291
292static inline void
e315cd28 293qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 294{
a9083016 295 /* Currently used for 82XX only. */
7c3df132
SK		 296 if (vha->device_flags & DFLG_DEV_FAILED) {
297 ql_dbg(ql_dbg_timer, vha, 0x600d,
298 "Device in a failed state, returning.\n");
a9083016 299 return;
7c3df132 300 }
a9083016 301
e315cd28 302 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 303}
304
a824ebb3 305static __inline__ void
e315cd28 306qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 307{
e315cd28
AC		 308 del_timer_sync(&vha->timer);
309 vha->timer_active = 0;
1da177e4
LT		 310}
311
1da177e4
LT		 312static int qla2x00_do_dpc(void *data);
313
314static void qla2x00_rst_aen(scsi_qla_host_t *);
315
73208dfd
AC		 316static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
317 struct req_que **, struct rsp_que **);
e30d1756 318static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 319static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 320
1da177e4 321/* -------------------------------------------------------------------------- */
9a347ff4
CD		 322static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
323 struct rsp_que *rsp)
73208dfd 324{
7c3df132 325 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 326 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 327 GFP_KERNEL);
328 if (!ha->req_q_map) {
7c3df132
SK		 329 ql_log(ql_log_fatal, vha, 0x003b,
330 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 331 goto fail_req_map;
332 }
333
2afa19a9 334 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 335 GFP_KERNEL);
336 if (!ha->rsp_q_map) {
7c3df132
SK		 337 ql_log(ql_log_fatal, vha, 0x003c,
338 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 339 goto fail_rsp_map;
340 }
9a347ff4
CD		 341 /*
342 * Make sure we record at least the request and response queue zero in
343 * case we need to free them if part of the probe fails.
344 */
345 ha->rsp_q_map[0] = rsp;
346 ha->req_q_map[0] = req;
73208dfd
AC		 347 set_bit(0, ha->rsp_qid_map);
348 set_bit(0, ha->req_qid_map);
349 return 1;
350
351fail_rsp_map:
352 kfree(ha->req_q_map);
353 ha->req_q_map = NULL;
354fail_req_map:
355 return -ENOMEM;
356}
357
2afa19a9 358static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 359{
8ae6d9c7
GM		 360 if (IS_QLAFX00(ha)) {
361 if (req && req->ring_fx00)
362 dma_free_coherent(&ha->pdev->dev,
363 (req->length_fx00 + 1) * sizeof(request_t),
364 req->ring_fx00, req->dma_fx00);
365 } else if (req && req->ring)
73208dfd
AC		 366 dma_free_coherent(&ha->pdev->dev,
367 (req->length + 1) * sizeof(request_t),
368 req->ring, req->dma);
369
8d93f550
CD		 370 if (req)
371 kfree(req->outstanding_cmds);
372
73208dfd
AC		 373 kfree(req);
374 req = NULL;
375}
376
2afa19a9
AC		 377static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
378{
8ae6d9c7
GM		 379 if (IS_QLAFX00(ha)) {
380 if (rsp && rsp->ring)
381 dma_free_coherent(&ha->pdev->dev,
382 (rsp->length_fx00 + 1) * sizeof(request_t),
383 rsp->ring_fx00, rsp->dma_fx00);
384 } else if (rsp && rsp->ring) {
2afa19a9
AC		 385 dma_free_coherent(&ha->pdev->dev,
386 (rsp->length + 1) * sizeof(response_t),
387 rsp->ring, rsp->dma);
8ae6d9c7 388 }
2afa19a9
AC		 389 kfree(rsp);
390 rsp = NULL;
391}
392
73208dfd
AC		 393static void qla2x00_free_queues(struct qla_hw_data *ha)
394{
395 struct req_que *req;
396 struct rsp_que *rsp;
397 int cnt;
398
2afa19a9 399 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 400 req = ha->req_q_map[cnt];
2afa19a9 401 qla2x00_free_req_que(ha, req);
73208dfd 402 }
73208dfd
AC		 403 kfree(ha->req_q_map);
404 ha->req_q_map = NULL;
2afa19a9
AC		 405
406 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
407 rsp = ha->rsp_q_map[cnt];
408 qla2x00_free_rsp_que(ha, rsp);
409 }
410 kfree(ha->rsp_q_map);
411 ha->rsp_q_map = NULL;
73208dfd
AC		 412}
413
68ca949c
AC		 414static int qla25xx_setup_mode(struct scsi_qla_host *vha)
415{
416 uint16_t options = 0;
417 int ques, req, ret;
418 struct qla_hw_data *ha = vha->hw;
419
7163ea81 420 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 421 ql_log(ql_log_warn, vha, 0x00d8,
422 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 423 goto fail;
424 }
68ca949c 425 if (ql2xmultique_tag) {
68ca949c
AC		 426 /* create a request queue for IO */
427 options |= BIT_7;
428 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
429 QLA_DEFAULT_QUE_QOS);
430 if (!req) {
7c3df132
SK		 431 ql_log(ql_log_warn, vha, 0x00e0,
432 "Failed to create request queue.\n");
68ca949c
AC		 433 goto fail;
434 }
278274d5 435 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 436 vha->req = ha->req_q_map[req];
437 options |= BIT_1;
438 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
439 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
440 if (!ret) {
7c3df132
SK		 441 ql_log(ql_log_warn, vha, 0x00e8,
442 "Failed to create response queue.\n");
68ca949c
AC		 443 goto fail2;
444 }
445 }
7163ea81 446 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 447 ql_dbg(ql_dbg_multiq, vha, 0xc007,
448 "CPU affinity mode enalbed, "
449 "no. of response queues:%d no. of request queues:%d.\n",
450 ha->max_rsp_queues, ha->max_req_queues);
451 ql_dbg(ql_dbg_init, vha, 0x00e9,
452 "CPU affinity mode enalbed, "
453 "no. of response queues:%d no. of request queues:%d.\n",
454 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 455 }
456 return 0;
457fail2:
458 qla25xx_delete_queues(vha);
7163ea81
AC		 459 destroy_workqueue(ha->wq);
460 ha->wq = NULL;
0cd33fcf 461 vha->req = ha->req_q_map[0];
68ca949c
AC		 462fail:
463 ha->mqenable = 0;
7163ea81
AC		 464 kfree(ha->req_q_map);
465 kfree(ha->rsp_q_map);
466 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 467 return 1;
468}
469
1da177e4 470static char *
e315cd28 471qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 472{
e315cd28 473 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 474 static char *pci_bus_modes[] = {
475 "33", "66", "100", "133",
476 };
477 uint16_t pci_bus;
478
479 strcpy(str, "PCI");
480 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
481 if (pci_bus) {
482 strcat(str, "-X (");
483 strcat(str, pci_bus_modes[pci_bus]);
484 } else {
485 pci_bus = (ha->pci_attr & BIT_8) >> 8;
486 strcat(str, " (");
487 strcat(str, pci_bus_modes[pci_bus]);
488 }
489 strcat(str, " MHz)");
490
491 return (str);
492}
493
fca29703 494static char *
e315cd28 495qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 496{
497 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 498 struct qla_hw_data *ha = vha->hw;
fca29703 499 uint32_t pci_bus;
fca29703 500
62a276f8 501 if (pci_is_pcie(ha->pdev)) {
fca29703 502 char lwstr[6];
62a276f8 503 uint32_t lstat, lspeed, lwidth;
fca29703 504
62a276f8
BH		 505 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
506 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
507 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 508
509 strcpy(str, "PCIe (");
49300af7
SK		 510 switch (lspeed) {
511 case 1:
c87a0d8c 512 strcat(str, "2.5GT/s ");
49300af7
SK		 513 break;
514 case 2:
c87a0d8c 515 strcat(str, "5.0GT/s ");
49300af7
SK		 516 break;
517 case 3:
518 strcat(str, "8.0GT/s ");
519 break;
520 default:
fca29703 521 strcat(str, "<unknown> ");
49300af7
SK		 522 break;
523 }
fca29703
AV		 524 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
525 strcat(str, lwstr);
526
527 return str;
528 }
529
530 strcpy(str, "PCI");
531 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
532 if (pci_bus == 0 || pci_bus == 8) {
533 strcat(str, " (");
534 strcat(str, pci_bus_modes[pci_bus >> 3]);
535 } else {
536 strcat(str, "-X ");
537 if (pci_bus & BIT_2)
538 strcat(str, "Mode 2");
539 else
540 strcat(str, "Mode 1");
541 strcat(str, " (");
542 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
543 }
544 strcat(str, " MHz)");
545
546 return str;
547}
548
e5f82ab8 549static char *
e315cd28 550qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 551{
552 char un_str[10];
e315cd28 553 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 554
1da177e4
LT		 555 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
556 ha->fw_minor_version,
557 ha->fw_subminor_version);
558
559 if (ha->fw_attributes & BIT_9) {
560 strcat(str, "FLX");
561 return (str);
562 }
563
564 switch (ha->fw_attributes & 0xFF) {
565 case 0x7:
566 strcat(str, "EF");
567 break;
568 case 0x17:
569 strcat(str, "TP");
570 break;
571 case 0x37:
572 strcat(str, "IP");
573 break;
574 case 0x77:
575 strcat(str, "VI");
576 break;
577 default:
578 sprintf(un_str, "(%x)", ha->fw_attributes);
579 strcat(str, un_str);
580 break;
581 }
582 if (ha->fw_attributes & 0x100)
583 strcat(str, "X");
584
585 return (str);
586}
587
e5f82ab8 588static char *
e315cd28 589qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 590{
e315cd28 591 struct qla_hw_data *ha = vha->hw;
f0883ac6 592
3a03eb79
AV		 593 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
594 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 595 return str;
fca29703
AV		 596}
597
9ba56b95
GM		 598void
599qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 600{
9ba56b95
GM		 601 srb_t *sp = (srb_t *)ptr;
602 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
603 struct qla_hw_data *ha = sp->fcport->vha->hw;
604 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 605
9ba56b95
GM		 606 if (sp->flags & SRB_DMA_VALID) {
607 scsi_dma_unmap(cmd);
608 sp->flags &= ~SRB_DMA_VALID;
7c3df132 609 }
fca29703 610
9ba56b95
GM		 611 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
612 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
613 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
614 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
615 }
616
617 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
618 /* List assured to be having elements */
f83adb61 619 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 620 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
621 }
622
623 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
624 dma_pool_free(ha->dl_dma_pool, ctx,
625 ((struct crc_context *)ctx)->crc_ctx_dma);
626 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
627 }
628
629 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
630 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 631
9ba56b95
GM		 632 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
633 ctx1->fcp_cmnd_dma);
634 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
635 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
636 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
637 mempool_free(ctx1, ha->ctx_mempool);
638 ctx1 = NULL;
639 }
640
641 CMD_SP(cmd) = NULL;
b00ee7d7 642 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 643}
644
14b06808 645static void
9ba56b95
GM		 646qla2x00_sp_compl(void *data, void *ptr, int res)
647{
648 struct qla_hw_data *ha = (struct qla_hw_data *)data;
649 srb_t *sp = (srb_t *)ptr;
650 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
651
652 cmd->result = res;
653
654 if (atomic_read(&sp->ref_count) == 0) {
655 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
656 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
657 sp, GET_CMD_SP(sp));
658 if (ql2xextended_error_logging & ql_dbg_io)
659 BUG();
660 return;
661 }
662 if (!atomic_dec_and_test(&sp->ref_count))
663 return;
664
665 qla2x00_sp_free_dma(ha, sp);
666 cmd->scsi_done(cmd);
fca29703
AV		 667}
668
8ae6d9c7
GM		 669/* If we are SP1 here, we need to still take and release the host_lock as SP1
670 * does not have the changes necessary to avoid taking host->host_lock.
671 */
1da177e4 672static int
f5e3e40b 673qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 674{
134ae078 675 scsi_qla_host_t *vha = shost_priv(host);
fca29703 676 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 677 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 678 struct qla_hw_data *ha = vha->hw;
679 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 680 srb_t *sp;
681 int rval;
682
85880801 683 if (ha->flags.eeh_busy) {
7c3df132 684 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 685 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 686 "PCI Channel IO permanent failure, exiting "
687 "cmd=%p.\n", cmd);
b9b12f73 688 cmd->result = DID_NO_CONNECT << 16;
7c3df132 689 } else {
5f28d2d7 690 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 691 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 692 cmd->result = DID_REQUEUE << 16;
7c3df132 693 }
14e660e6
SJ		 694 goto qc24_fail_command;
695 }
696
19a7b4ae
JSEC		 697 rval = fc_remote_port_chkready(rport);
698 if (rval) {
699 cmd->result = rval;
5f28d2d7 700 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 701 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
702 cmd, rval);
fca29703
AV		 703 goto qc24_fail_command;
704 }
705
bad75002
AE		 706 if (!vha->flags.difdix_supported &&
707 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 708 ql_dbg(ql_dbg_io, vha, 0x3004,
709 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
710 cmd);
bad75002
AE		 711 cmd->result = DID_NO_CONNECT << 16;
712 goto qc24_fail_command;
713 }
aa651be8
CD		 714
715 if (!fcport) {
716 cmd->result = DID_NO_CONNECT << 16;
717 goto qc24_fail_command;
718 }
719
fca29703
AV		 720 if (atomic_read(&fcport->state) != FCS_ONLINE) {
721 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 722 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 723 ql_dbg(ql_dbg_io, vha, 0x3005,
724 "Returning DNC, fcport_state=%d loop_state=%d.\n",
725 atomic_read(&fcport->state),
726 atomic_read(&base_vha->loop_state));
fca29703
AV		 727 cmd->result = DID_NO_CONNECT << 16;
728 goto qc24_fail_command;
729 }
7b594131 730 goto qc24_target_busy;
fca29703
AV		 731 }
732
b00ee7d7 733 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 734 if (!sp)
f5e3e40b 735 goto qc24_host_busy;
fca29703 736
9ba56b95
GM		 737 sp->u.scmd.cmd = cmd;
738 sp->type = SRB_SCSI_CMD;
739 atomic_set(&sp->ref_count, 1);
740 CMD_SP(cmd) = (void *)sp;
741 sp->free = qla2x00_sp_free_dma;
742 sp->done = qla2x00_sp_compl;
743
e315cd28 744 rval = ha->isp_ops->start_scsi(sp);
7c3df132 745 if (rval != QLA_SUCCESS) {
53016ed3 746 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 747 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 748 goto qc24_host_busy_free_sp;
7c3df132 749 }
fca29703 750
fca29703
AV		 751 return 0;
752
753qc24_host_busy_free_sp:
9ba56b95 754 qla2x00_sp_free_dma(ha, sp);
fca29703 755
f5e3e40b 756qc24_host_busy:
fca29703
AV		 757 return SCSI_MLQUEUE_HOST_BUSY;
758
7b594131
MC		 759qc24_target_busy:
760 return SCSI_MLQUEUE_TARGET_BUSY;
761
fca29703 762qc24_fail_command:
f5e3e40b 763 cmd->scsi_done(cmd);
fca29703
AV		 764
765 return 0;
766}
767
1da177e4
LT		 768/*
769 * qla2x00_eh_wait_on_command
770 * Waits for the command to be returned by the Firmware for some
771 * max time.
772 *
773 * Input:
1da177e4 774 * cmd = Scsi Command to wait on.
1da177e4
LT		 775 *
776 * Return:
777 * Not Found : 0
778 * Found : 1
779 */
780static int
e315cd28 781qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 782{
fe74c71f 783#define ABORT_POLLING_PERIOD 1000
478c3b03 784#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 785 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 786 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
787 struct qla_hw_data *ha = vha->hw;
f4f051eb 788 int ret = QLA_SUCCESS;
1da177e4 789
85880801 790 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 791 ql_dbg(ql_dbg_taskm, vha, 0x8005,
792 "Return:eh_wait.\n");
85880801
AV		 793 return ret;
794 }
795
d970432c 796 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 797 msleep(ABORT_POLLING_PERIOD);
f4f051eb 798 }
799 if (CMD_SP(cmd))
800 ret = QLA_FUNCTION_FAILED;
1da177e4 801
f4f051eb 802 return ret;
1da177e4
LT		 803}
804
805/*
806 * qla2x00_wait_for_hba_online
fa2a1ce5 807 * Wait till the HBA is online after going through
1da177e4
LT		 808 * <= MAX_RETRIES_OF_ISP_ABORT or
809 * finally HBA is disabled ie marked offline
810 *
811 * Input:
812 * ha - pointer to host adapter structure
fa2a1ce5
AV		 813 *
814 * Note:
1da177e4
LT		 815 * Does context switching-Release SPIN_LOCK
816 * (if any) before calling this routine.
817 *
818 * Return:
819 * Success (Adapter is online) : 0
820 * Failed (Adapter is offline/disabled) : 1
821 */
854165f4 822int
e315cd28 823qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 824{
fca29703
AV		 825 int return_status;
826 unsigned long wait_online;
e315cd28
AC		 827 struct qla_hw_data *ha = vha->hw;
828 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 829
fa2a1ce5 830 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 831 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
832 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
833 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
834 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 835
836 msleep(1000);
837 }
e315cd28 838 if (base_vha->flags.online)
fa2a1ce5 839 return_status = QLA_SUCCESS;
1da177e4
LT		 840 else
841 return_status = QLA_FUNCTION_FAILED;
842
1da177e4
LT		 843 return (return_status);
844}
845
86fbee86 846/*
638a1a01
SC		 847 * qla2x00_wait_for_hba_ready
848 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 849 *
850 * Input:
851 * ha - pointer to host adapter structure
852 *
853 * Note:
854 * Does context switching-Release SPIN_LOCK
855 * (if any) before calling this routine.
856 *
86fbee86 857 */
638a1a01
SC		 858static void
859qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 860{
86fbee86 861 struct qla_hw_data *ha = vha->hw;
86fbee86 862
638a1a01
SC		 863 while ((!(vha->flags.online) || ha->dpc_active ||
864 ha->flags.mbox_busy))
86fbee86 865 msleep(1000);
86fbee86
LC		 866}
867
2533cf67
LC		 868int
869qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
870{
871 int return_status;
872 unsigned long wait_reset;
873 struct qla_hw_data *ha = vha->hw;
874 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
875
876 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
877 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
878 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
879 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
880 ha->dpc_active) && time_before(jiffies, wait_reset)) {
881
882 msleep(1000);
883
884 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
885 ha->flags.chip_reset_done)
886 break;
887 }
888 if (ha->flags.chip_reset_done)
889 return_status = QLA_SUCCESS;
890 else
891 return_status = QLA_FUNCTION_FAILED;
892
893 return return_status;
894}
895
083a469d
GM		 896static void
897sp_get(struct srb *sp)
898{
899 atomic_inc(&sp->ref_count);
900}
901
1da177e4
LT		 902/**************************************************************************
903* qla2xxx_eh_abort
904*
905* Description:
906* The abort function will abort the specified command.
907*
908* Input:
909* cmd = Linux SCSI command packet to be aborted.
910*
911* Returns:
912* Either SUCCESS or FAILED.
913*
914* Note:
2ea00202 915* Only return FAILED if command not returned by firmware.
1da177e4 916**************************************************************************/
e5f82ab8 917static int
1da177e4
LT		 918qla2xxx_eh_abort(struct scsi_cmnd *cmd)
919{
e315cd28 920 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 921 srb_t *sp;
4e98d3b8 922 int ret;
f4f051eb 923 unsigned int id, lun;
18e144d3 924 unsigned long flags;
f934c9d0 925 int rval, wait = 0;
e315cd28 926 struct qla_hw_data *ha = vha->hw;
1da177e4 927
f4f051eb 928 if (!CMD_SP(cmd))
2ea00202 929 return SUCCESS;
1da177e4 930
4e98d3b8
AV		 931 ret = fc_block_scsi_eh(cmd);
932 if (ret != 0)
933 return ret;
934 ret = SUCCESS;
935
f4f051eb 936 id = cmd->device->id;
937 lun = cmd->device->lun;
1da177e4 938
e315cd28 939 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 940 sp = (srb_t *) CMD_SP(cmd);
941 if (!sp) {
942 spin_unlock_irqrestore(&ha->hardware_lock, flags);
943 return SUCCESS;
944 }
1da177e4 945
7c3df132 946 ql_dbg(ql_dbg_taskm, vha, 0x8002,
cfb0919c
CD		 947 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
948 vha->host_no, id, lun, sp, cmd);
17d98630 949
170babc3
MC		 950 /* Get a reference to the sp and drop the lock.*/
951 sp_get(sp);
083a469d 952
e315cd28 953 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 954 rval = ha->isp_ops->abort_command(sp);
955 if (rval) {
956 if (rval == QLA_FUNCTION_PARAMETER_ERROR) {
957 /*
958 * Decrement the ref_count since we can't find the
959 * command
960 */
961 atomic_dec(&sp->ref_count);
962 ret = SUCCESS;
963 } else
964 ret = FAILED;
965
7c3df132 966 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 967 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 968 } else {
7c3df132 969 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 970 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 971 wait = 1;
972 }
75942064
SK		 973
974 spin_lock_irqsave(&ha->hardware_lock, flags);
f934c9d0
CD		 975 /*
976 * Clear the slot in the oustanding_cmds array if we can't find the
977 * command to reclaim the resources.
978 */
979 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
980 vha->req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 981 sp->done(ha, sp, 0);
75942064 982 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 983
bc91ade9
CD		 984 /* Did the command return during mailbox execution? */
985 if (ret == FAILED && !CMD_SP(cmd))
986 ret = SUCCESS;
987
f4f051eb 988 /* Wait for the command to be returned. */
2ea00202 989 if (wait) {
e315cd28 990 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 991 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 992 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 993 ret = FAILED;
f4f051eb 994 }
1da177e4 995 }
1da177e4 996
7c3df132 997 ql_log(ql_log_info, vha, 0x801c,
cfb0919c
CD		 998 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
999 vha->host_no, id, lun, wait, ret);
1da177e4 1000
f4f051eb 1001 return ret;
1002}
1da177e4 1003
4d78c973 1004int
e315cd28 1005qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 1006 unsigned int l, enum nexus_wait_type type)
f4f051eb 1007{
17d98630 1008 int cnt, match, status;
18e144d3 1009 unsigned long flags;
e315cd28 1010 struct qla_hw_data *ha = vha->hw;
73208dfd 1011 struct req_que *req;
4d78c973 1012 srb_t *sp;
9ba56b95 1013 struct scsi_cmnd *cmd;
1da177e4 1014
523ec773 1015 status = QLA_SUCCESS;
17d98630 1016
e315cd28 1017 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1018 req = vha->req;
17d98630 1019 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1020 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1021 sp = req->outstanding_cmds[cnt];
1022 if (!sp)
523ec773 1023 continue;
9ba56b95 1024 if (sp->type != SRB_SCSI_CMD)
cf53b069 1025 continue;
17d98630
AC		 1026 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1027 continue;
1028 match = 0;
9ba56b95 1029 cmd = GET_CMD_SP(sp);
17d98630
AC		 1030 switch (type) {
1031 case WAIT_HOST:
1032 match = 1;
1033 break;
1034 case WAIT_TARGET:
9ba56b95 1035 match = cmd->device->id == t;
17d98630
AC		 1036 break;
1037 case WAIT_LUN:
9ba56b95
GM		 1038 match = (cmd->device->id == t &&
1039 cmd->device->lun == l);
17d98630 1040 break;
73208dfd 1041 }
17d98630
AC		 1042 if (!match)
1043 continue;
1044
1045 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1046 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1047 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1048 }
e315cd28 1049 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1050
1051 return status;
1da177e4
LT		 1052}
1053
523ec773
AV		 1054static char *reset_errors[] = {
1055 "HBA not online",
1056 "HBA not ready",
1057 "Task management failed",
1058 "Waiting for command completions",
1059};
1da177e4 1060
e5f82ab8 1061static int
523ec773 1062__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 1063 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 1064{
e315cd28 1065 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1066 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1067 int err;
1da177e4 1068
7c3df132 1069 if (!fcport) {
523ec773 1070 return FAILED;
7c3df132 1071 }
1da177e4 1072
4e98d3b8
AV		 1073 err = fc_block_scsi_eh(cmd);
1074 if (err != 0)
1075 return err;
1076
7c3df132 1077 ql_log(ql_log_info, vha, 0x8009,
cfb0919c 1078 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
7c3df132 1079 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1080
523ec773 1081 err = 0;
7c3df132
SK		 1082 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1083 ql_log(ql_log_warn, vha, 0x800a,
1084 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1085 goto eh_reset_failed;
7c3df132 1086 }
523ec773 1087 err = 2;
2afa19a9 1088 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1089 != QLA_SUCCESS) {
1090 ql_log(ql_log_warn, vha, 0x800c,
1091 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1092 goto eh_reset_failed;
7c3df132 1093 }
523ec773 1094 err = 3;
e315cd28 1095 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1096 cmd->device->lun, type) != QLA_SUCCESS) {
1097 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1098 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1099 goto eh_reset_failed;
7c3df132 1100 }
523ec773 1101
7c3df132 1102 ql_log(ql_log_info, vha, 0x800e,
cfb0919c
CD		 1103 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1104 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1105
1106 return SUCCESS;
1107
4d78c973 1108eh_reset_failed:
7c3df132 1109 ql_log(ql_log_info, vha, 0x800f,
cfb0919c
CD		 1110 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1111 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1112 cmd);
523ec773
AV		 1113 return FAILED;
1114}
1da177e4 1115
523ec773
AV		 1116static int
1117qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1118{
e315cd28
AC		 1119 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1120 struct qla_hw_data *ha = vha->hw;
1da177e4 1121
523ec773
AV		 1122 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1123 ha->isp_ops->lun_reset);
1da177e4
LT		 1124}
1125
1da177e4 1126static int
523ec773 1127qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1128{
e315cd28
AC		 1129 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1130 struct qla_hw_data *ha = vha->hw;
1da177e4 1131
523ec773
AV		 1132 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1133 ha->isp_ops->target_reset);
1da177e4
LT		 1134}
1135
1da177e4
LT		 1136/**************************************************************************
1137* qla2xxx_eh_bus_reset
1138*
1139* Description:
1140* The bus reset function will reset the bus and abort any executing
1141* commands.
1142*
1143* Input:
1144* cmd = Linux SCSI command packet of the command that cause the
1145* bus reset.
1146*
1147* Returns:
1148* SUCCESS/FAILURE (defined as macro in scsi.h).
1149*
1150**************************************************************************/
e5f82ab8 1151static int
1da177e4
LT		 1152qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1153{
e315cd28 1154 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1155 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1156 int ret = FAILED;
f4f051eb 1157 unsigned int id, lun;
f4f051eb 1158
f4f051eb 1159 id = cmd->device->id;
1160 lun = cmd->device->lun;
1da177e4 1161
7c3df132 1162 if (!fcport) {
f4f051eb 1163 return ret;
7c3df132 1164 }
1da177e4 1165
4e98d3b8
AV		 1166 ret = fc_block_scsi_eh(cmd);
1167 if (ret != 0)
1168 return ret;
1169 ret = FAILED;
1170
7c3df132 1171 ql_log(ql_log_info, vha, 0x8012,
46270afe 1172 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1173
e315cd28 1174 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1175 ql_log(ql_log_fatal, vha, 0x8013,
1176 "Wait for hba online failed board disabled.\n");
f4f051eb 1177 goto eh_bus_reset_done;
1da177e4
LT		 1178 }
1179
ad537689
SK		 1180 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1181 ret = SUCCESS;
1182
f4f051eb 1183 if (ret == FAILED)
1184 goto eh_bus_reset_done;
1da177e4 1185
9a41a62b 1186 /* Flush outstanding commands. */
4d78c973 1187 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1188 QLA_SUCCESS) {
1189 ql_log(ql_log_warn, vha, 0x8014,
1190 "Wait for pending commands failed.\n");
9a41a62b 1191 ret = FAILED;
7c3df132 1192 }
1da177e4 1193
f4f051eb 1194eh_bus_reset_done:
7c3df132 1195 ql_log(ql_log_warn, vha, 0x802b,
cfb0919c 1196 "BUS RESET %s nexus=%ld:%d:%d.\n",
d6a03581 1197 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1198
f4f051eb 1199 return ret;
1da177e4
LT		 1200}
1201
1202/**************************************************************************
1203* qla2xxx_eh_host_reset
1204*
1205* Description:
1206* The reset function will reset the Adapter.
1207*
1208* Input:
1209* cmd = Linux SCSI command packet of the command that cause the
1210* adapter reset.
1211*
1212* Returns:
1213* Either SUCCESS or FAILED.
1214*
1215* Note:
1216**************************************************************************/
e5f82ab8 1217static int
1da177e4
LT		 1218qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1219{
e315cd28 1220 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1221 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1222 int ret = FAILED;
f4f051eb 1223 unsigned int id, lun;
e315cd28 1224 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1225
f4f051eb 1226 id = cmd->device->id;
1227 lun = cmd->device->lun;
f4f051eb 1228
7c3df132 1229 ql_log(ql_log_info, vha, 0x8018,
cfb0919c 1230 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1231
63ee7072
CD		 1232 /*
1233 * No point in issuing another reset if one is active. Also do not
1234 * attempt a reset if we are updating flash.
1235 */
1236 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1237 goto eh_host_reset_lock;
1da177e4 1238
e315cd28
AC		 1239 if (vha != base_vha) {
1240 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1241 goto eh_host_reset_lock;
e315cd28 1242 } else {
7ec0effd 1243 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1244 if (!qla82xx_fcoe_ctx_reset(vha)) {
1245 /* Ctx reset success */
1246 ret = SUCCESS;
1247 goto eh_host_reset_lock;
1248 }
1249 /* fall thru if ctx reset failed */
1250 }
68ca949c
AC		 1251 if (ha->wq)
1252 flush_workqueue(ha->wq);
1253
e315cd28 1254 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1255 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1256 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1257 /* failed. schedule dpc to try */
1258 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1259
7c3df132
SK		 1260 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1261 ql_log(ql_log_warn, vha, 0x802a,
1262 "wait for hba online failed.\n");
e315cd28 1263 goto eh_host_reset_lock;
7c3df132 1264 }
e315cd28
AC		 1265 }
1266 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1267 }
1da177e4 1268
e315cd28 1269 /* Waiting for command to be returned to OS.*/
4d78c973 1270 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1271 QLA_SUCCESS)
f4f051eb 1272 ret = SUCCESS;
1da177e4 1273
f4f051eb 1274eh_host_reset_lock:
cfb0919c
CD		 1275 ql_log(ql_log_info, vha, 0x8017,
1276 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1277 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1278
f4f051eb 1279 return ret;
1280}
1da177e4
LT		 1281
1282/*
1283* qla2x00_loop_reset
1284* Issue loop reset.
1285*
1286* Input:
1287* ha = adapter block pointer.
1288*
1289* Returns:
1290* 0 = success
1291*/
a4722cf2 1292int
e315cd28 1293qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1294{
0c8c39af 1295 int ret;
bdf79621 1296 struct fc_port *fcport;
e315cd28 1297 struct qla_hw_data *ha = vha->hw;
1da177e4 1298
5854771e
AB		 1299 if (IS_QLAFX00(ha)) {
1300 return qlafx00_loop_reset(vha);
1301 }
1302
f4c496c1 1303 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1304 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1305 if (fcport->port_type != FCT_TARGET)
1306 continue;
1307
1308 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1309 if (ret != QLA_SUCCESS) {
7c3df132 1310 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1311 "Bus Reset failed: Reset=%d "
7c3df132 1312 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1313 }
1314 }
1315 }
1316
8ae6d9c7 1317
6246b8a1 1318 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1319 atomic_set(&vha->loop_state, LOOP_DOWN);
1320 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1321 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1322 ret = qla2x00_full_login_lip(vha);
0c8c39af 1323 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1324 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1325 "full_login_lip=%d.\n", ret);
749af3d5 1326 }
0c8c39af
AV		 1327 }
1328
0d6e61bc 1329 if (ha->flags.enable_lip_reset) {
e315cd28 1330 ret = qla2x00_lip_reset(vha);
ad537689 1331 if (ret != QLA_SUCCESS)
7c3df132
SK		 1332 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1333 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1334 }
1335
1da177e4 1336 /* Issue marker command only when we are going to start the I/O */
e315cd28 1337 vha->marker_needed = 1;
1da177e4 1338
0c8c39af 1339 return QLA_SUCCESS;
1da177e4
LT		 1340}
1341
df4bf0bb 1342void
e315cd28 1343qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1344{
73208dfd 1345 int que, cnt;
df4bf0bb
AV		 1346 unsigned long flags;
1347 srb_t *sp;
e315cd28 1348 struct qla_hw_data *ha = vha->hw;
73208dfd 1349 struct req_que *req;
df4bf0bb
AV		 1350
1351 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1352 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1353 req = ha->req_q_map[que];
73208dfd
AC		 1354 if (!req)
1355 continue;
8d93f550
CD		 1356 if (!req->outstanding_cmds)
1357 continue;
1358 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1359 sp = req->outstanding_cmds[cnt];
e612d465 1360 if (sp) {
73208dfd 1361 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1362 sp->done(vha, sp, res);
73208dfd 1363 }
df4bf0bb
AV		 1364 }
1365 }
1366 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1367}
1368
f4f051eb 1369static int
1370qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1371{
bdf79621 1372 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1373
19a7b4ae 1374 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1375 return -ENXIO;
bdf79621 1376
19a7b4ae 1377 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1378
f4f051eb 1379 return 0;
1380}
1da177e4 1381
f4f051eb 1382static int
1383qla2xxx_slave_configure(struct scsi_device *sdev)
1384{
e315cd28 1385 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1386 struct req_que *req = vha->req;
8482e118 1387
9e522cd8
AE		 1388 if (IS_T10_PI_CAPABLE(vha->hw))
1389 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1390
f4f051eb 1391 if (sdev->tagged_supported)
73208dfd 1392 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1393 else
73208dfd 1394 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb 1395 return 0;
1396}
1da177e4 1397
f4f051eb 1398static void
1399qla2xxx_slave_destroy(struct scsi_device *sdev)
1400{
1401 sdev->hostdata = NULL;
1da177e4
LT		 1402}
1403
c45dd305
GM		 1404static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1405{
1406 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1407
1408 if (!scsi_track_queue_full(sdev, qdepth))
1409 return;
1410
7c3df132 1411 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
cfb0919c
CD		 1412 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1413 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1414}
1415
1416static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1417{
1418 fc_port_t *fcport = sdev->hostdata;
1419 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1420 struct req_que *req = NULL;
1421
1422 req = vha->req;
1423 if (!req)
1424 return;
1425
1426 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1427 return;
1428
1429 if (sdev->ordered_tags)
1430 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1431 else
1432 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1433
7c3df132 1434 ql_dbg(ql_dbg_io, vha, 0x302a,
cfb0919c
CD		 1435 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1436 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1437}
1438
ce7e4af7 1439static int
e881a172 1440qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1441{
c45dd305
GM		 1442 switch (reason) {
1443 case SCSI_QDEPTH_DEFAULT:
1444 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1445 break;
1446 case SCSI_QDEPTH_QFULL:
1447 qla2x00_handle_queue_full(sdev, qdepth);
1448 break;
1449 case SCSI_QDEPTH_RAMP_UP:
1450 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1451 break;
1452 default:
08002af2 1453 return -EOPNOTSUPP;
c45dd305 1454 }
e881a172 1455
ce7e4af7
AV		 1456 return sdev->queue_depth;
1457}
1458
1459static int
1460qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1461{
1462 if (sdev->tagged_supported) {
1463 scsi_set_tag_type(sdev, tag_type);
1464 if (tag_type)
1465 scsi_activate_tcq(sdev, sdev->queue_depth);
1466 else
1467 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1468 } else
1469 tag_type = 0;
1470
1471 return tag_type;
1472}
1473
1da177e4
LT		 1474/**
1475 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1476 * @ha: HA context
1477 *
1478 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1479 * supported addressing method.
1480 */
1481static void
53303c42 1482qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1483{
7524f9b9 1484 /* Assume a 32bit DMA mask. */
1da177e4 1485 ha->flags.enable_64bit_addressing = 0;
1da177e4 1486
6a35528a 1487 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1488 /* Any upper-dword bits set? */
1489 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1490 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1491 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1492 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1493 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1494 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1495 return;
1da177e4 1496 }
1da177e4 1497 }
7524f9b9 1498
284901a9
YH		 1499 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1500 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1501}
1502
fd34f556 1503static void
e315cd28 1504qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1505{
1506 unsigned long flags = 0;
1507 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1508
1509 spin_lock_irqsave(&ha->hardware_lock, flags);
1510 ha->interrupts_on = 1;
1511 /* enable risc and host interrupts */
1512 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1513 RD_REG_WORD(&reg->ictrl);
1514 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1515
1516}
1517
1518static void
e315cd28 1519qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1520{
1521 unsigned long flags = 0;
1522 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1523
1524 spin_lock_irqsave(&ha->hardware_lock, flags);
1525 ha->interrupts_on = 0;
1526 /* disable risc and host interrupts */
1527 WRT_REG_WORD(&reg->ictrl, 0);
1528 RD_REG_WORD(&reg->ictrl);
1529 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1530}
1531
1532static void
e315cd28 1533qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1534{
1535 unsigned long flags = 0;
1536 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1537
1538 spin_lock_irqsave(&ha->hardware_lock, flags);
1539 ha->interrupts_on = 1;
1540 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1541 RD_REG_DWORD(&reg->ictrl);
1542 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1543}
1544
1545static void
e315cd28 1546qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1547{
1548 unsigned long flags = 0;
1549 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1550
124f85e6
AV		 1551 if (IS_NOPOLLING_TYPE(ha))
1552 return;
fd34f556
AV		 1553 spin_lock_irqsave(&ha->hardware_lock, flags);
1554 ha->interrupts_on = 0;
1555 WRT_REG_DWORD(&reg->ictrl, 0);
1556 RD_REG_DWORD(&reg->ictrl);
1557 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1558}
1559
706f457d
GM		 1560static int
1561qla2x00_iospace_config(struct qla_hw_data *ha)
1562{
1563 resource_size_t pio;
1564 uint16_t msix;
1565 int cpus;
1566
706f457d
GM		 1567 if (pci_request_selected_regions(ha->pdev, ha->bars,
1568 QLA2XXX_DRIVER_NAME)) {
1569 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1570 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1571 pci_name(ha->pdev));
1572 goto iospace_error_exit;
1573 }
1574 if (!(ha->bars & 1))
1575 goto skip_pio;
1576
1577 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1578 pio = pci_resource_start(ha->pdev, 0);
1579 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1580 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1581 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1582 "Invalid pci I/O region size (%s).\n",
1583 pci_name(ha->pdev));
1584 pio = 0;
1585 }
1586 } else {
1587 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1588 "Region #0 no a PIO resource (%s).\n",
1589 pci_name(ha->pdev));
1590 pio = 0;
1591 }
1592 ha->pio_address = pio;
1593 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1594 "PIO address=%llu.\n",
1595 (unsigned long long)ha->pio_address);
1596
1597skip_pio:
1598 /* Use MMIO operations for all accesses. */
1599 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1600 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1601 "Region #1 not an MMIO resource (%s), aborting.\n",
1602 pci_name(ha->pdev));
1603 goto iospace_error_exit;
1604 }
1605 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1606 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1607 "Invalid PCI mem region size (%s), aborting.\n",
1608 pci_name(ha->pdev));
1609 goto iospace_error_exit;
1610 }
1611
1612 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1613 if (!ha->iobase) {
1614 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1615 "Cannot remap MMIO (%s), aborting.\n",
1616 pci_name(ha->pdev));
1617 goto iospace_error_exit;
1618 }
1619
1620 /* Determine queue resources */
1621 ha->max_req_queues = ha->max_rsp_queues = 1;
1622 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1623 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1624 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1625 goto mqiobase_exit;
1626
1627 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1628 pci_resource_len(ha->pdev, 3));
1629 if (ha->mqiobase) {
1630 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1631 "MQIO Base=%p.\n", ha->mqiobase);
1632 /* Read MSIX vector size of the board */
1633 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1634 ha->msix_count = msix;
1635 /* Max queues are bounded by available msix vectors */
1636 /* queue 0 uses two msix vectors */
1637 if (ql2xmultique_tag) {
1638 cpus = num_online_cpus();
1639 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1640 (cpus + 1) : (ha->msix_count - 1);
1641 ha->max_req_queues = 2;
1642 } else if (ql2xmaxqueues > 1) {
1643 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1644 QLA_MQ_SIZE : ql2xmaxqueues;
1645 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1646 "QoS mode set, max no of request queues:%d.\n",
1647 ha->max_req_queues);
1648 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1649 "QoS mode set, max no of request queues:%d.\n",
1650 ha->max_req_queues);
1651 }
1652 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1653 "MSI-X vector count: %d.\n", msix);
1654 } else
1655 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1656 "BAR 3 not enabled.\n");
1657
1658mqiobase_exit:
1659 ha->msix_count = ha->max_rsp_queues + 1;
1660 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1661 "MSIX Count:%d.\n", ha->msix_count);
1662 return (0);
1663
1664iospace_error_exit:
1665 return (-ENOMEM);
1666}
1667
1668
6246b8a1
GM		 1669static int
1670qla83xx_iospace_config(struct qla_hw_data *ha)
1671{
1672 uint16_t msix;
1673 int cpus;
1674
1675 if (pci_request_selected_regions(ha->pdev, ha->bars,
1676 QLA2XXX_DRIVER_NAME)) {
1677 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1678 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1679 pci_name(ha->pdev));
1680
1681 goto iospace_error_exit;
1682 }
1683
1684 /* Use MMIO operations for all accesses. */
1685 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1686 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1687 "Invalid pci I/O region size (%s).\n",
1688 pci_name(ha->pdev));
1689 goto iospace_error_exit;
1690 }
1691 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1692 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1693 "Invalid PCI mem region size (%s), aborting\n",
1694 pci_name(ha->pdev));
1695 goto iospace_error_exit;
1696 }
1697
1698 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1699 if (!ha->iobase) {
1700 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1701 "Cannot remap MMIO (%s), aborting.\n",
1702 pci_name(ha->pdev));
1703 goto iospace_error_exit;
1704 }
1705
1706 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1707 /* 83XX 26XX always use MQ type access for queues
1708 * - mbar 2, a.k.a region 4 */
1709 ha->max_req_queues = ha->max_rsp_queues = 1;
1710 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1711 pci_resource_len(ha->pdev, 4));
1712
1713 if (!ha->mqiobase) {
1714 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1715 "BAR2/region4 not enabled\n");
1716 goto mqiobase_exit;
1717 }
1718
1719 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1720 pci_resource_len(ha->pdev, 2));
1721 if (ha->msixbase) {
1722 /* Read MSIX vector size of the board */
1723 pci_read_config_word(ha->pdev,
1724 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1725 ha->msix_count = msix;
1726 /* Max queues are bounded by available msix vectors */
1727 /* queue 0 uses two msix vectors */
1728 if (ql2xmultique_tag) {
1729 cpus = num_online_cpus();
1730 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1731 (cpus + 1) : (ha->msix_count - 1);
1732 ha->max_req_queues = 2;
1733 } else if (ql2xmaxqueues > 1) {
1734 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1735 QLA_MQ_SIZE : ql2xmaxqueues;
1736 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1737 "QoS mode set, max no of request queues:%d.\n",
1738 ha->max_req_queues);
1739 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1740 "QoS mode set, max no of request queues:%d.\n",
1741 ha->max_req_queues);
1742 }
1743 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1744 "MSI-X vector count: %d.\n", msix);
1745 } else
1746 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1747 "BAR 1 not enabled.\n");
1748
1749mqiobase_exit:
1750 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1751
1752 qlt_83xx_iospace_config(ha);
1753
6246b8a1
GM		 1754 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1755 "MSIX Count:%d.\n", ha->msix_count);
1756 return 0;
1757
1758iospace_error_exit:
1759 return -ENOMEM;
1760}
1761
fd34f556
AV		 1762static struct isp_operations qla2100_isp_ops = {
1763 .pci_config = qla2100_pci_config,
1764 .reset_chip = qla2x00_reset_chip,
1765 .chip_diag = qla2x00_chip_diag,
1766 .config_rings = qla2x00_config_rings,
1767 .reset_adapter = qla2x00_reset_adapter,
1768 .nvram_config = qla2x00_nvram_config,
1769 .update_fw_options = qla2x00_update_fw_options,
1770 .load_risc = qla2x00_load_risc,
1771 .pci_info_str = qla2x00_pci_info_str,
1772 .fw_version_str = qla2x00_fw_version_str,
1773 .intr_handler = qla2100_intr_handler,
1774 .enable_intrs = qla2x00_enable_intrs,
1775 .disable_intrs = qla2x00_disable_intrs,
1776 .abort_command = qla2x00_abort_command,
523ec773
AV		 1777 .target_reset = qla2x00_abort_target,
1778 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1779 .fabric_login = qla2x00_login_fabric,
1780 .fabric_logout = qla2x00_fabric_logout,
1781 .calc_req_entries = qla2x00_calc_iocbs_32,
1782 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1783 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1784 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1785 .read_nvram = qla2x00_read_nvram_data,
1786 .write_nvram = qla2x00_write_nvram_data,
1787 .fw_dump = qla2100_fw_dump,
1788 .beacon_on = NULL,
1789 .beacon_off = NULL,
1790 .beacon_blink = NULL,
1791 .read_optrom = qla2x00_read_optrom_data,
1792 .write_optrom = qla2x00_write_optrom_data,
1793 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1794 .start_scsi = qla2x00_start_scsi,
a9083016 1795 .abort_isp = qla2x00_abort_isp,
706f457d 1796 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1797 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1798};
1799
1800static struct isp_operations qla2300_isp_ops = {
1801 .pci_config = qla2300_pci_config,
1802 .reset_chip = qla2x00_reset_chip,
1803 .chip_diag = qla2x00_chip_diag,
1804 .config_rings = qla2x00_config_rings,
1805 .reset_adapter = qla2x00_reset_adapter,
1806 .nvram_config = qla2x00_nvram_config,
1807 .update_fw_options = qla2x00_update_fw_options,
1808 .load_risc = qla2x00_load_risc,
1809 .pci_info_str = qla2x00_pci_info_str,
1810 .fw_version_str = qla2x00_fw_version_str,
1811 .intr_handler = qla2300_intr_handler,
1812 .enable_intrs = qla2x00_enable_intrs,
1813 .disable_intrs = qla2x00_disable_intrs,
1814 .abort_command = qla2x00_abort_command,
523ec773
AV		 1815 .target_reset = qla2x00_abort_target,
1816 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1817 .fabric_login = qla2x00_login_fabric,
1818 .fabric_logout = qla2x00_fabric_logout,
1819 .calc_req_entries = qla2x00_calc_iocbs_32,
1820 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1821 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1822 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1823 .read_nvram = qla2x00_read_nvram_data,
1824 .write_nvram = qla2x00_write_nvram_data,
1825 .fw_dump = qla2300_fw_dump,
1826 .beacon_on = qla2x00_beacon_on,
1827 .beacon_off = qla2x00_beacon_off,
1828 .beacon_blink = qla2x00_beacon_blink,
1829 .read_optrom = qla2x00_read_optrom_data,
1830 .write_optrom = qla2x00_write_optrom_data,
1831 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1832 .start_scsi = qla2x00_start_scsi,
a9083016 1833 .abort_isp = qla2x00_abort_isp,
7ec0effd 1834 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1835 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1836};
1837
1838static struct isp_operations qla24xx_isp_ops = {
1839 .pci_config = qla24xx_pci_config,
1840 .reset_chip = qla24xx_reset_chip,
1841 .chip_diag = qla24xx_chip_diag,
1842 .config_rings = qla24xx_config_rings,
1843 .reset_adapter = qla24xx_reset_adapter,
1844 .nvram_config = qla24xx_nvram_config,
1845 .update_fw_options = qla24xx_update_fw_options,
1846 .load_risc = qla24xx_load_risc,
1847 .pci_info_str = qla24xx_pci_info_str,
1848 .fw_version_str = qla24xx_fw_version_str,
1849 .intr_handler = qla24xx_intr_handler,
1850 .enable_intrs = qla24xx_enable_intrs,
1851 .disable_intrs = qla24xx_disable_intrs,
1852 .abort_command = qla24xx_abort_command,
523ec773
AV		 1853 .target_reset = qla24xx_abort_target,
1854 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1855 .fabric_login = qla24xx_login_fabric,
1856 .fabric_logout = qla24xx_fabric_logout,
1857 .calc_req_entries = NULL,
1858 .build_iocbs = NULL,
1859 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1860 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1861 .read_nvram = qla24xx_read_nvram_data,
1862 .write_nvram = qla24xx_write_nvram_data,
1863 .fw_dump = qla24xx_fw_dump,
1864 .beacon_on = qla24xx_beacon_on,
1865 .beacon_off = qla24xx_beacon_off,
1866 .beacon_blink = qla24xx_beacon_blink,
1867 .read_optrom = qla24xx_read_optrom_data,
1868 .write_optrom = qla24xx_write_optrom_data,
1869 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1870 .start_scsi = qla24xx_start_scsi,
a9083016 1871 .abort_isp = qla2x00_abort_isp,
7ec0effd 1872 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1873 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1874};
1875
c3a2f0df
AV		 1876static struct isp_operations qla25xx_isp_ops = {
1877 .pci_config = qla25xx_pci_config,
1878 .reset_chip = qla24xx_reset_chip,
1879 .chip_diag = qla24xx_chip_diag,
1880 .config_rings = qla24xx_config_rings,
1881 .reset_adapter = qla24xx_reset_adapter,
1882 .nvram_config = qla24xx_nvram_config,
1883 .update_fw_options = qla24xx_update_fw_options,
1884 .load_risc = qla24xx_load_risc,
1885 .pci_info_str = qla24xx_pci_info_str,
1886 .fw_version_str = qla24xx_fw_version_str,
1887 .intr_handler = qla24xx_intr_handler,
1888 .enable_intrs = qla24xx_enable_intrs,
1889 .disable_intrs = qla24xx_disable_intrs,
1890 .abort_command = qla24xx_abort_command,
523ec773
AV		 1891 .target_reset = qla24xx_abort_target,
1892 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1893 .fabric_login = qla24xx_login_fabric,
1894 .fabric_logout = qla24xx_fabric_logout,
1895 .calc_req_entries = NULL,
1896 .build_iocbs = NULL,
1897 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1898 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1899 .read_nvram = qla25xx_read_nvram_data,
1900 .write_nvram = qla25xx_write_nvram_data,
1901 .fw_dump = qla25xx_fw_dump,
1902 .beacon_on = qla24xx_beacon_on,
1903 .beacon_off = qla24xx_beacon_off,
1904 .beacon_blink = qla24xx_beacon_blink,
338c9161 1905 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1906 .write_optrom = qla24xx_write_optrom_data,
1907 .get_flash_version = qla24xx_get_flash_version,
bad75002 1908 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1909 .abort_isp = qla2x00_abort_isp,
7ec0effd 1910 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1911 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1912};
1913
3a03eb79
AV		 1914static struct isp_operations qla81xx_isp_ops = {
1915 .pci_config = qla25xx_pci_config,
1916 .reset_chip = qla24xx_reset_chip,
1917 .chip_diag = qla24xx_chip_diag,
1918 .config_rings = qla24xx_config_rings,
1919 .reset_adapter = qla24xx_reset_adapter,
1920 .nvram_config = qla81xx_nvram_config,
1921 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1922 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1923 .pci_info_str = qla24xx_pci_info_str,
1924 .fw_version_str = qla24xx_fw_version_str,
1925 .intr_handler = qla24xx_intr_handler,
1926 .enable_intrs = qla24xx_enable_intrs,
1927 .disable_intrs = qla24xx_disable_intrs,
1928 .abort_command = qla24xx_abort_command,
1929 .target_reset = qla24xx_abort_target,
1930 .lun_reset = qla24xx_lun_reset,
1931 .fabric_login = qla24xx_login_fabric,
1932 .fabric_logout = qla24xx_fabric_logout,
1933 .calc_req_entries = NULL,
1934 .build_iocbs = NULL,
1935 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1936 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1937 .read_nvram = NULL,
1938 .write_nvram = NULL,
3a03eb79
AV		 1939 .fw_dump = qla81xx_fw_dump,
1940 .beacon_on = qla24xx_beacon_on,
1941 .beacon_off = qla24xx_beacon_off,
6246b8a1 1942 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1943 .read_optrom = qla25xx_read_optrom_data,
1944 .write_optrom = qla24xx_write_optrom_data,
1945 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1946 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1947 .abort_isp = qla2x00_abort_isp,
7ec0effd 1948 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1949 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 1950};
1951
1952static struct isp_operations qla82xx_isp_ops = {
1953 .pci_config = qla82xx_pci_config,
1954 .reset_chip = qla82xx_reset_chip,
1955 .chip_diag = qla24xx_chip_diag,
1956 .config_rings = qla82xx_config_rings,
1957 .reset_adapter = qla24xx_reset_adapter,
1958 .nvram_config = qla81xx_nvram_config,
1959 .update_fw_options = qla24xx_update_fw_options,
1960 .load_risc = qla82xx_load_risc,
9d55ca66 1961 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 1962 .fw_version_str = qla24xx_fw_version_str,
1963 .intr_handler = qla82xx_intr_handler,
1964 .enable_intrs = qla82xx_enable_intrs,
1965 .disable_intrs = qla82xx_disable_intrs,
1966 .abort_command = qla24xx_abort_command,
1967 .target_reset = qla24xx_abort_target,
1968 .lun_reset = qla24xx_lun_reset,
1969 .fabric_login = qla24xx_login_fabric,
1970 .fabric_logout = qla24xx_fabric_logout,
1971 .calc_req_entries = NULL,
1972 .build_iocbs = NULL,
1973 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1974 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1975 .read_nvram = qla24xx_read_nvram_data,
1976 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 1977 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 1978 .beacon_on = qla82xx_beacon_on,
1979 .beacon_off = qla82xx_beacon_off,
1980 .beacon_blink = NULL,
a9083016
GM		 1981 .read_optrom = qla82xx_read_optrom_data,
1982 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 1983 .get_flash_version = qla82xx_get_flash_version,
a9083016
GM		 1984 .start_scsi = qla82xx_start_scsi,
1985 .abort_isp = qla82xx_abort_isp,
706f457d 1986 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 1987 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 1988};
1989
7ec0effd
AD		 1990static struct isp_operations qla8044_isp_ops = {
1991 .pci_config = qla82xx_pci_config,
1992 .reset_chip = qla82xx_reset_chip,
1993 .chip_diag = qla24xx_chip_diag,
1994 .config_rings = qla82xx_config_rings,
1995 .reset_adapter = qla24xx_reset_adapter,
1996 .nvram_config = qla81xx_nvram_config,
1997 .update_fw_options = qla24xx_update_fw_options,
1998 .load_risc = qla82xx_load_risc,
1999 .pci_info_str = qla24xx_pci_info_str,
2000 .fw_version_str = qla24xx_fw_version_str,
2001 .intr_handler = qla8044_intr_handler,
2002 .enable_intrs = qla82xx_enable_intrs,
2003 .disable_intrs = qla82xx_disable_intrs,
2004 .abort_command = qla24xx_abort_command,
2005 .target_reset = qla24xx_abort_target,
2006 .lun_reset = qla24xx_lun_reset,
2007 .fabric_login = qla24xx_login_fabric,
2008 .fabric_logout = qla24xx_fabric_logout,
2009 .calc_req_entries = NULL,
2010 .build_iocbs = NULL,
2011 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2012 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2013 .read_nvram = NULL,
2014 .write_nvram = NULL,
a1b23c5a 2015 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2016 .beacon_on = qla82xx_beacon_on,
2017 .beacon_off = qla82xx_beacon_off,
2018 .beacon_blink = NULL,
888e639d 2019 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2020 .write_optrom = qla8044_write_optrom_data,
2021 .get_flash_version = qla82xx_get_flash_version,
2022 .start_scsi = qla82xx_start_scsi,
2023 .abort_isp = qla8044_abort_isp,
2024 .iospace_config = qla82xx_iospace_config,
2025 .initialize_adapter = qla2x00_initialize_adapter,
2026};
2027
6246b8a1
GM		 2028static struct isp_operations qla83xx_isp_ops = {
2029 .pci_config = qla25xx_pci_config,
2030 .reset_chip = qla24xx_reset_chip,
2031 .chip_diag = qla24xx_chip_diag,
2032 .config_rings = qla24xx_config_rings,
2033 .reset_adapter = qla24xx_reset_adapter,
2034 .nvram_config = qla81xx_nvram_config,
2035 .update_fw_options = qla81xx_update_fw_options,
2036 .load_risc = qla81xx_load_risc,
2037 .pci_info_str = qla24xx_pci_info_str,
2038 .fw_version_str = qla24xx_fw_version_str,
2039 .intr_handler = qla24xx_intr_handler,
2040 .enable_intrs = qla24xx_enable_intrs,
2041 .disable_intrs = qla24xx_disable_intrs,
2042 .abort_command = qla24xx_abort_command,
2043 .target_reset = qla24xx_abort_target,
2044 .lun_reset = qla24xx_lun_reset,
2045 .fabric_login = qla24xx_login_fabric,
2046 .fabric_logout = qla24xx_fabric_logout,
2047 .calc_req_entries = NULL,
2048 .build_iocbs = NULL,
2049 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2050 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2051 .read_nvram = NULL,
2052 .write_nvram = NULL,
2053 .fw_dump = qla83xx_fw_dump,
2054 .beacon_on = qla24xx_beacon_on,
2055 .beacon_off = qla24xx_beacon_off,
2056 .beacon_blink = qla83xx_beacon_blink,
2057 .read_optrom = qla25xx_read_optrom_data,
2058 .write_optrom = qla24xx_write_optrom_data,
2059 .get_flash_version = qla24xx_get_flash_version,
2060 .start_scsi = qla24xx_dif_start_scsi,
2061 .abort_isp = qla2x00_abort_isp,
2062 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2063 .initialize_adapter = qla2x00_initialize_adapter,
2064};
2065
2066static struct isp_operations qlafx00_isp_ops = {
2067 .pci_config = qlafx00_pci_config,
2068 .reset_chip = qlafx00_soft_reset,
2069 .chip_diag = qlafx00_chip_diag,
2070 .config_rings = qlafx00_config_rings,
2071 .reset_adapter = qlafx00_soft_reset,
2072 .nvram_config = NULL,
2073 .update_fw_options = NULL,
2074 .load_risc = NULL,
2075 .pci_info_str = qlafx00_pci_info_str,
2076 .fw_version_str = qlafx00_fw_version_str,
2077 .intr_handler = qlafx00_intr_handler,
2078 .enable_intrs = qlafx00_enable_intrs,
2079 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2080 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2081 .target_reset = qlafx00_abort_target,
2082 .lun_reset = qlafx00_lun_reset,
2083 .fabric_login = NULL,
2084 .fabric_logout = NULL,
2085 .calc_req_entries = NULL,
2086 .build_iocbs = NULL,
2087 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2088 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2089 .read_nvram = qla24xx_read_nvram_data,
2090 .write_nvram = qla24xx_write_nvram_data,
2091 .fw_dump = NULL,
2092 .beacon_on = qla24xx_beacon_on,
2093 .beacon_off = qla24xx_beacon_off,
2094 .beacon_blink = NULL,
2095 .read_optrom = qla24xx_read_optrom_data,
2096 .write_optrom = qla24xx_write_optrom_data,
2097 .get_flash_version = qla24xx_get_flash_version,
2098 .start_scsi = qlafx00_start_scsi,
2099 .abort_isp = qlafx00_abort_isp,
2100 .iospace_config = qlafx00_iospace_config,
2101 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2102};
2103
f73cb695
CD		 2104static struct isp_operations qla27xx_isp_ops = {
2105 .pci_config = qla25xx_pci_config,
2106 .reset_chip = qla24xx_reset_chip,
2107 .chip_diag = qla24xx_chip_diag,
2108 .config_rings = qla24xx_config_rings,
2109 .reset_adapter = qla24xx_reset_adapter,
2110 .nvram_config = qla81xx_nvram_config,
2111 .update_fw_options = qla81xx_update_fw_options,
2112 .load_risc = qla81xx_load_risc,
2113 .pci_info_str = qla24xx_pci_info_str,
2114 .fw_version_str = qla24xx_fw_version_str,
2115 .intr_handler = qla24xx_intr_handler,
2116 .enable_intrs = qla24xx_enable_intrs,
2117 .disable_intrs = qla24xx_disable_intrs,
2118 .abort_command = qla24xx_abort_command,
2119 .target_reset = qla24xx_abort_target,
2120 .lun_reset = qla24xx_lun_reset,
2121 .fabric_login = qla24xx_login_fabric,
2122 .fabric_logout = qla24xx_fabric_logout,
2123 .calc_req_entries = NULL,
2124 .build_iocbs = NULL,
2125 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2126 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2127 .read_nvram = NULL,
2128 .write_nvram = NULL,
2129 .fw_dump = qla27xx_fwdump,
2130 .beacon_on = qla24xx_beacon_on,
2131 .beacon_off = qla24xx_beacon_off,
2132 .beacon_blink = qla83xx_beacon_blink,
2133 .read_optrom = qla25xx_read_optrom_data,
2134 .write_optrom = qla24xx_write_optrom_data,
2135 .get_flash_version = qla24xx_get_flash_version,
2136 .start_scsi = qla24xx_dif_start_scsi,
2137 .abort_isp = qla2x00_abort_isp,
2138 .iospace_config = qla83xx_iospace_config,
2139 .initialize_adapter = qla2x00_initialize_adapter,
2140};
2141
ea5b6382 2142static inline void
e315cd28 2143qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382 2144{
2145 ha->device_type = DT_EXTENDED_IDS;
2146 switch (ha->pdev->device) {
2147 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2148 ha->device_type |= DT_ISP2100;
2149 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2150 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2151 break;
2152 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2153 ha->device_type |= DT_ISP2200;
2154 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2155 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382 2156 break;
2157 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2158 ha->device_type |= DT_ISP2300;
4a59f71d 2159 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2160 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2161 break;
2162 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2163 ha->device_type |= DT_ISP2312;
4a59f71d 2164 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2165 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2166 break;
2167 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2168 ha->device_type |= DT_ISP2322;
4a59f71d 2169 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382 2170 if (ha->pdev->subsystem_vendor == 0x1028 &&
2171 ha->pdev->subsystem_device == 0x0170)
2172 ha->device_type |= DT_OEM_001;
441d1072 2173 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2174 break;
2175 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2176 ha->device_type |= DT_ISP6312;
441d1072 2177 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2178 break;
2179 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2180 ha->device_type |= DT_ISP6322;
441d1072 2181 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382 2182 break;
2183 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2184 ha->device_type |= DT_ISP2422;
4a59f71d 2185 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2186 ha->device_type |= DT_FWI2;
c76f2c01 2187 ha->device_type |= DT_IIDMA;
441d1072 2188 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2189 break;
2190 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2191 ha->device_type |= DT_ISP2432;
4a59f71d 2192 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2193 ha->device_type |= DT_FWI2;
c76f2c01 2194 ha->device_type |= DT_IIDMA;
441d1072 2195 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2196 break;
4d4df193
HK		 2197 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2198 ha->device_type |= DT_ISP8432;
2199 ha->device_type |= DT_ZIO_SUPPORTED;
2200 ha->device_type |= DT_FWI2;
2201 ha->device_type |= DT_IIDMA;
2202 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2203 break;
044cc6c8 2204 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2205 ha->device_type |= DT_ISP5422;
e428924c 2206 ha->device_type |= DT_FWI2;
441d1072 2207 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2208 break;
044cc6c8 2209 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2210 ha->device_type |= DT_ISP5432;
e428924c 2211 ha->device_type |= DT_FWI2;
441d1072 2212 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2213 break;
c3a2f0df
AV		 2214 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2215 ha->device_type |= DT_ISP2532;
2216 ha->device_type |= DT_ZIO_SUPPORTED;
2217 ha->device_type |= DT_FWI2;
2218 ha->device_type |= DT_IIDMA;
441d1072 2219 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2220 break;
3a03eb79
AV		 2221 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2222 ha->device_type |= DT_ISP8001;
2223 ha->device_type |= DT_ZIO_SUPPORTED;
2224 ha->device_type |= DT_FWI2;
2225 ha->device_type |= DT_IIDMA;
2226 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2227 break;
a9083016
GM		 2228 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2229 ha->device_type |= DT_ISP8021;
2230 ha->device_type |= DT_ZIO_SUPPORTED;
2231 ha->device_type |= DT_FWI2;
2232 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2233 /* Initialize 82XX ISP flags */
2234 qla82xx_init_flags(ha);
2235 break;
7ec0effd
AD		 2236 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2237 ha->device_type |= DT_ISP8044;
2238 ha->device_type |= DT_ZIO_SUPPORTED;
2239 ha->device_type |= DT_FWI2;
2240 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2241 /* Initialize 82XX ISP flags */
2242 qla82xx_init_flags(ha);
2243 break;
6246b8a1
GM		 2244 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2245 ha->device_type |= DT_ISP2031;
2246 ha->device_type |= DT_ZIO_SUPPORTED;
2247 ha->device_type |= DT_FWI2;
2248 ha->device_type |= DT_IIDMA;
2249 ha->device_type |= DT_T10_PI;
2250 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2251 break;
2252 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2253 ha->device_type |= DT_ISP8031;
2254 ha->device_type |= DT_ZIO_SUPPORTED;
2255 ha->device_type |= DT_FWI2;
2256 ha->device_type |= DT_IIDMA;
2257 ha->device_type |= DT_T10_PI;
2258 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2259 break;
8ae6d9c7
GM		 2260 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2261 ha->device_type |= DT_ISPFX00;
2262 break;
f73cb695
CD		 2263 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2264 ha->device_type |= DT_ISP2071;
2265 ha->device_type |= DT_ZIO_SUPPORTED;
2266 ha->device_type |= DT_FWI2;
2267 ha->device_type |= DT_IIDMA;
2268 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2269 break;
2c5bbbb2
JC		 2270 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2271 ha->device_type |= DT_ISP2271;
2272 ha->device_type |= DT_ZIO_SUPPORTED;
2273 ha->device_type |= DT_FWI2;
2274 ha->device_type |= DT_IIDMA;
2275 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2276 break;
ea5b6382 2277 }
e5b68a61 2278
a9083016 2279 if (IS_QLA82XX(ha))
43a9c38b 2280 ha->port_no = ha->portnum & 1;
f73cb695 2281 else {
a9083016
GM		 2282 /* Get adapter physical port no from interrupt pin register. */
2283 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2284 if (IS_QLA27XX(ha))
2285 ha->port_no--;
2286 else
2287 ha->port_no = !(ha->port_no & 1);
2288 }
a9083016 2289
7c3df132 2290 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2291 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2292 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382 2293}
2294
1e99e33a
AV		 2295static void
2296qla2xxx_scan_start(struct Scsi_Host *shost)
2297{
e315cd28 2298 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2299
cbc8eb67
AV		 2300 if (vha->hw->flags.running_gold_fw)
2301 return;
2302
e315cd28
AC		 2303 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2304 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2305 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2306 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2307}
2308
2309static int
2310qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2311{
e315cd28 2312 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2313
e315cd28 2314 if (!vha->host)
1e99e33a 2315 return 1;
e315cd28 2316 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2317 return 1;
2318
e315cd28 2319 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2320}
2321
1da177e4
LT		 2322/*
2323 * PCI driver interface
2324 */
6f039790 2325static int
7ee61397 2326qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2327{
a1541d5a 2328 int ret = -ENODEV;
1da177e4 2329 struct Scsi_Host *host;
e315cd28
AC		 2330 scsi_qla_host_t *base_vha = NULL;
2331 struct qla_hw_data *ha;
29856e28 2332 char pci_info[30];
7d613ac6 2333 char fw_str[30], wq_name[30];
5433383e 2334 struct scsi_host_template *sht;
642ef983 2335 int bars, mem_only = 0;
e315cd28 2336 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2337 struct req_que *req = NULL;
2338 struct rsp_que *rsp = NULL;
285d0321 2339 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2340 sht = &qla2xxx_driver_template;
5433383e 2341 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2342 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2343 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2344 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2345 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2346 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2347 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2348 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2349 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2350 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2351 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2352 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2
JC		 2353 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2354 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271) {
285d0321 2355 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2356 mem_only = 1;
7c3df132
SK		 2357 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2358 "Mem only adapter.\n");
285d0321 2359 }
7c3df132
SK		 2360 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2361 "Bars=%d.\n", bars);
285d0321 2362
09483916
BH		 2363 if (mem_only) {
2364 if (pci_enable_device_mem(pdev))
2365 goto probe_out;
2366 } else {
2367 if (pci_enable_device(pdev))
2368 goto probe_out;
2369 }
285d0321 2370
0927678f
JB		 2371 /* This may fail but that's ok */
2372 pci_enable_pcie_error_reporting(pdev);
285d0321 2373
e315cd28
AC		 2374 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2375 if (!ha) {
7c3df132
SK		 2376 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2377 "Unable to allocate memory for ha.\n");
e315cd28 2378 goto probe_out;
1da177e4 2379 }
7c3df132
SK		 2380 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2381 "Memory allocated for ha=%p.\n", ha);
e315cd28 2382 ha->pdev = pdev;
2d70c103 2383 ha->tgt.enable_class_2 = ql2xenableclass2;
1da177e4
LT		 2384
2385 /* Clear our data area */
285d0321 2386 ha->bars = bars;
09483916 2387 ha->mem_only = mem_only;
df4bf0bb 2388 spin_lock_init(&ha->hardware_lock);
339aa70e 2389 spin_lock_init(&ha->vport_slock);
a9b6f722 2390 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2391 mutex_init(&ha->optrom_mutex);
1da177e4 2392
ea5b6382 2393 /* Set ISP-type information. */
2394 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2395
2396 /* Set EEH reset type to fundamental if required by hba */
95676112 2397 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2398 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2399 pdev->needs_freset = 1;
ca79cf66 2400
cba1e47f
CD		 2401 ha->prev_topology = 0;
2402 ha->init_cb_size = sizeof(init_cb_t);
2403 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2404 ha->optrom_size = OPTROM_SIZE_2300;
2405
abbd8870 2406 /* Assign ISP specific operations. */
1da177e4 2407 if (IS_QLA2100(ha)) {
642ef983 2408 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2409 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2410 req_length = REQUEST_ENTRY_CNT_2100;
2411 rsp_length = RESPONSE_ENTRY_CNT_2100;
2412 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2413 ha->gid_list_info_size = 4;
3a03eb79
AV		 2414 ha->flash_conf_off = ~0;
2415 ha->flash_data_off = ~0;
2416 ha->nvram_conf_off = ~0;
2417 ha->nvram_data_off = ~0;
fd34f556 2418 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2419 } else if (IS_QLA2200(ha)) {
642ef983 2420 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2421 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2422 req_length = REQUEST_ENTRY_CNT_2200;
2423 rsp_length = RESPONSE_ENTRY_CNT_2100;
2424 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2425 ha->gid_list_info_size = 4;
3a03eb79
AV		 2426 ha->flash_conf_off = ~0;
2427 ha->flash_data_off = ~0;
2428 ha->nvram_conf_off = ~0;
2429 ha->nvram_data_off = ~0;
fd34f556 2430 ha->isp_ops = &qla2100_isp_ops;
fca29703 2431 } else if (IS_QLA23XX(ha)) {
642ef983 2432 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2433 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2434 req_length = REQUEST_ENTRY_CNT_2200;
2435 rsp_length = RESPONSE_ENTRY_CNT_2300;
2436 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2437 ha->gid_list_info_size = 6;
854165f4 2438 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2439 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2440 ha->flash_conf_off = ~0;
2441 ha->flash_data_off = ~0;
2442 ha->nvram_conf_off = ~0;
2443 ha->nvram_data_off = ~0;
fd34f556 2444 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2445 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2446 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2447 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2448 req_length = REQUEST_ENTRY_CNT_24XX;
2449 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2450 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2451 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2452 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2453 ha->gid_list_info_size = 8;
854165f4 2454 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2455 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2456 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2457 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2458 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2459 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2460 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2461 } else if (IS_QLA25XX(ha)) {
642ef983 2462 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2463 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2464 req_length = REQUEST_ENTRY_CNT_24XX;
2465 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2466 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2467 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2468 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2469 ha->gid_list_info_size = 8;
2470 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2471 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2472 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2473 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2474 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2475 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2476 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2477 } else if (IS_QLA81XX(ha)) {
642ef983 2478 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2479 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2480 req_length = REQUEST_ENTRY_CNT_24XX;
2481 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2482 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2483 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2484 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2485 ha->gid_list_info_size = 8;
2486 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2487 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2488 ha->isp_ops = &qla81xx_isp_ops;
2489 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2490 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2491 ha->nvram_conf_off = ~0;
2492 ha->nvram_data_off = ~0;
a9083016 2493 } else if (IS_QLA82XX(ha)) {
642ef983 2494 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2495 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2496 req_length = REQUEST_ENTRY_CNT_82XX;
2497 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2498 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2499 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2500 ha->gid_list_info_size = 8;
2501 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2502 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2503 ha->isp_ops = &qla82xx_isp_ops;
2504 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2505 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2506 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2507 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2508 } else if (IS_QLA8044(ha)) {
2509 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2510 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2511 req_length = REQUEST_ENTRY_CNT_82XX;
2512 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2513 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2514 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2515 ha->gid_list_info_size = 8;
2516 ha->optrom_size = OPTROM_SIZE_83XX;
2517 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2518 ha->isp_ops = &qla8044_isp_ops;
2519 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2520 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2521 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2522 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2523 } else if (IS_QLA83XX(ha)) {
7d613ac6 2524 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2525 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1
GM		 2526 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2527 req_length = REQUEST_ENTRY_CNT_24XX;
2528 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2529 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2530 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2531 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2532 ha->gid_list_info_size = 8;
2533 ha->optrom_size = OPTROM_SIZE_83XX;
2534 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2535 ha->isp_ops = &qla83xx_isp_ops;
2536 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2537 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2538 ha->nvram_conf_off = ~0;
2539 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2540 } else if (IS_QLAFX00(ha)) {
2541 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2542 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2543 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2544 req_length = REQUEST_ENTRY_CNT_FX00;
2545 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2546 ha->isp_ops = &qlafx00_isp_ops;
2547 ha->port_down_retry_count = 30; /* default value */
2548 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2549 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2550 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2551 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2552 ha->mr.host_info_resend = false;
2553 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2554 } else if (IS_QLA27XX(ha)) {
2555 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2556 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2557 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2558 req_length = REQUEST_ENTRY_CNT_24XX;
2559 rsp_length = RESPONSE_ENTRY_CNT_2300;
2560 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2561 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2562 ha->gid_list_info_size = 8;
2563 ha->optrom_size = OPTROM_SIZE_83XX;
2564 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2565 ha->isp_ops = &qla27xx_isp_ops;
2566 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2567 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2568 ha->nvram_conf_off = ~0;
2569 ha->nvram_data_off = ~0;
1da177e4 2570 }
6246b8a1 2571
7c3df132
SK		 2572 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2573 "mbx_count=%d, req_length=%d, "
2574 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2575 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2576 "max_fibre_devices=%d.\n",
7c3df132
SK		 2577 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2578 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2579 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2580 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2581 "isp_ops=%p, flash_conf_off=%d, "
2582 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2583 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2584 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2585
2586 /* Configure PCI I/O space */
2587 ret = ha->isp_ops->iospace_config(ha);
2588 if (ret)
0a63ad12 2589 goto iospace_config_failed;
706f457d
GM		 2590
2591 ql_log_pci(ql_log_info, pdev, 0x001d,
2592 "Found an ISP%04X irq %d iobase 0x%p.\n",
2593 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2594 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2595 init_completion(&ha->mbx_cmd_comp);
2596 complete(&ha->mbx_cmd_comp);
2597 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2598 init_completion(&ha->dcbx_comp);
f356bef1 2599 init_completion(&ha->lb_portup_comp);
1da177e4 2600
2c3dfe3f 2601 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2602
53303c42 2603 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2604 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2605 "64 Bit addressing is %s.\n",
2606 ha->flags.enable_64bit_addressing ? "enable" :
2607 "disable");
73208dfd 2608 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2609 if (ret) {
7c3df132
SK		 2610 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2611 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2612
e315cd28
AC		 2613 goto probe_hw_failed;
2614 }
2615
73208dfd 2616 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2617 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2618 req->max_q_depth = ql2xmaxqdepth;
2619
e315cd28
AC		 2620
2621 base_vha = qla2x00_create_host(sht, ha);
2622 if (!base_vha) {
a1541d5a 2623 ret = -ENOMEM;
6e9f21f3 2624 qla2x00_mem_free(ha);
2afa19a9
AC		 2625 qla2x00_free_req_que(ha, req);
2626 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2627 goto probe_hw_failed;
1da177e4
LT		 2628 }
2629
e315cd28
AC		 2630 pci_set_drvdata(pdev, base_vha);
2631
e315cd28 2632 host = base_vha->host;
2afa19a9 2633 base_vha->req = req;
73208dfd 2634 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2635 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2636 else
e315cd28
AC		 2637 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2638 base_vha->vp_idx;
58548cb5 2639
8ae6d9c7
GM		 2640 /* Setup fcport template structure. */
2641 ha->mr.fcport.vha = base_vha;
2642 ha->mr.fcport.port_type = FCT_UNKNOWN;
2643 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2644 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2645 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2646 ha->mr.fcport.scan_state = 1;
2647
58548cb5
GM		 2648 /* Set the SG table size based on ISP type */
2649 if (!IS_FWI2_CAPABLE(ha)) {
2650 if (IS_QLA2100(ha))
2651 host->sg_tablesize = 32;
2652 } else {
2653 if (!IS_QLA82XX(ha))
2654 host->sg_tablesize = QLA_SG_ALL;
2655 }
642ef983 2656 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2657 host->cmd_per_lun = 3;
2658 host->unique_id = host->host_no;
e02587d7 2659 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2660 host->max_cmd_len = 32;
2661 else
2662 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2663 host->max_channel = MAX_BUSES - 1;
82515920 2664 host->max_lun = ql2xmaxlun;
e315cd28 2665 host->transportt = qla2xxx_transport_template;
9a069e19 2666 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2667
7c3df132
SK		 2668 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2669 "max_id=%d this_id=%d "
2670 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
d8424f68 2671 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2672 host->this_id, host->cmd_per_lun, host->unique_id,
2673 host->max_cmd_len, host->max_channel, host->max_lun,
2674 host->transportt, sht->vendor_id);
2675
9a347ff4
CD		 2676que_init:
2677 /* Alloc arrays of request and response ring ptrs */
2678 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2679 ql_log(ql_log_fatal, base_vha, 0x003d,
2680 "Failed to allocate memory for queue pointers..."
2681 "aborting.\n");
2682 goto probe_init_failed;
2683 }
2684
2d70c103 2685 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2686
73208dfd
AC		 2687 /* Set up the irqs */
2688 ret = qla2x00_request_irqs(ha, rsp);
2689 if (ret)
6e9f21f3 2690 goto probe_init_failed;
90a86fc0
JC		 2691
2692 pci_save_state(pdev);
2693
9a347ff4 2694 /* Assign back pointers */
2afa19a9
AC		 2695 rsp->req = req;
2696 req->rsp = rsp;
9a347ff4 2697
8ae6d9c7
GM		 2698 if (IS_QLAFX00(ha)) {
2699 ha->rsp_q_map[0] = rsp;
2700 ha->req_q_map[0] = req;
2701 set_bit(0, ha->req_qid_map);
2702 set_bit(0, ha->rsp_qid_map);
2703 }
2704
08029990
AV		 2705 /* FWI2-capable only. */
2706 req->req_q_in = &ha->iobase->isp24.req_q_in;
2707 req->req_q_out = &ha->iobase->isp24.req_q_out;
2708 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2709 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2710 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2711 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2712 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2713 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2714 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2715 }
2716
8ae6d9c7
GM		 2717 if (IS_QLAFX00(ha)) {
2718 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2719 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2720 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2721 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2722 }
2723
7ec0effd 2724 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2725 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2726 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2727 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2728 }
2729
7c3df132
SK		 2730 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2731 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2732 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2733 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2734 "req->req_q_in=%p req->req_q_out=%p "
2735 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2736 req->req_q_in, req->req_q_out,
2737 rsp->rsp_q_in, rsp->rsp_q_out);
2738 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2739 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2740 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2741 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2742 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2743 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2744
8ae6d9c7 2745 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2746 ql_log(ql_log_fatal, base_vha, 0x00d6,
2747 "Failed to initialize adapter - Adapter flags %x.\n",
2748 base_vha->device_flags);
1da177e4 2749
a9083016
GM		 2750 if (IS_QLA82XX(ha)) {
2751 qla82xx_idc_lock(ha);
2752 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2753 QLA8XXX_DEV_FAILED);
a9083016 2754 qla82xx_idc_unlock(ha);
7c3df132
SK		 2755 ql_log(ql_log_fatal, base_vha, 0x00d7,
2756 "HW State: FAILED.\n");
7ec0effd
AD		 2757 } else if (IS_QLA8044(ha)) {
2758 qla8044_idc_lock(ha);
2759 qla8044_wr_direct(base_vha,
2760 QLA8044_CRB_DEV_STATE_INDEX,
2761 QLA8XXX_DEV_FAILED);
2762 qla8044_idc_unlock(ha);
2763 ql_log(ql_log_fatal, base_vha, 0x0150,
2764 "HW State: FAILED.\n");
a9083016
GM		 2765 }
2766
a1541d5a 2767 ret = -ENODEV;
1da177e4
LT		 2768 goto probe_failed;
2769 }
2770
3b1bef64
CD		 2771 if (IS_QLAFX00(ha))
2772 host->can_queue = QLAFX00_MAX_CANQUEUE;
2773 else
2774 host->can_queue = req->num_outstanding_cmds - 10;
2775
2776 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2777 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2778 host->can_queue, base_vha->req,
2779 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2780
7163ea81
AC		 2781 if (ha->mqenable) {
2782 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2783 ql_log(ql_log_warn, base_vha, 0x00ec,
2784 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2785 goto que_init;
2786 }
2787 }
68ca949c 2788
cbc8eb67
AV		 2789 if (ha->flags.running_gold_fw)
2790 goto skip_dpc;
2791
1da177e4
LT		 2792 /*
2793 * Startup the kernel thread for this host adapter
2794 */
39a11240 2795 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2796 "%s_dpc", base_vha->host_str);
39a11240 2797 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2798 ql_log(ql_log_fatal, base_vha, 0x00ed,
2799 "Failed to start DPC thread.\n");
39a11240 2800 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2801 goto probe_failed;
2802 }
7c3df132
SK		 2803 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2804 "DPC thread started successfully.\n");
1da177e4 2805
2d70c103
NB		 2806 /*
2807 * If we're not coming up in initiator mode, we might sit for
2808 * a while without waking up the dpc thread, which leads to a
2809 * stuck process warning. So just kick the dpc once here and
2810 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2811 */
2812 qla2xxx_wake_dpc(base_vha);
2813
f3ddac19
CD		 2814 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2815
81178772
SK		 2816 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2817 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2818 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2819 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2820
2821 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2822 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2823 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2824 INIT_WORK(&ha->idc_state_handler,
2825 qla83xx_idc_state_handler_work);
2826 INIT_WORK(&ha->nic_core_unrecoverable,
2827 qla83xx_nic_core_unrecoverable_work);
2828 }
2829
cbc8eb67 2830skip_dpc:
e315cd28
AC		 2831 list_add_tail(&base_vha->list, &ha->vp_list);
2832 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2833
2834 /* Initialized the timer */
e315cd28 2835 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2836 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2837 "Started qla2x00_timer with "
2838 "interval=%d.\n", WATCH_INTERVAL);
2839 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2840 "Detected hba at address=%p.\n",
2841 ha);
d19044c3 2842
e02587d7 2843 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2844 if (ha->fw_attributes & BIT_4) {
9e522cd8 2845 int prot = 0, guard;
bad75002 2846 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2847 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2848 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2849 if (ql2xenabledif == 1)
2850 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2851 scsi_host_set_prot(host,
8cb2049c 2852 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2853 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2854 | SHOST_DIF_TYPE3_PROTECTION
2855 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2856 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2857 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2858
2859 guard = SHOST_DIX_GUARD_CRC;
2860
2861 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2862 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2863 guard |= SHOST_DIX_GUARD_IP;
2864
2865 scsi_host_set_guard(host, guard);
bad75002
AE		 2866 } else
2867 base_vha->flags.difdix_supported = 0;
2868 }
2869
a9083016
GM		 2870 ha->isp_ops->enable_intrs(ha);
2871
1fe19ee4
AB		 2872 if (IS_QLAFX00(ha)) {
2873 ret = qlafx00_fx_disc(base_vha,
2874 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2875 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2876 QLA_SG_ALL : 128;
2877 }
2878
a1541d5a
AV		 2879 ret = scsi_add_host(host, &pdev->dev);
2880 if (ret)
2881 goto probe_failed;
2882
1486400f
MR		 2883 base_vha->flags.init_done = 1;
2884 base_vha->flags.online = 1;
edaa5c74 2885 ha->prev_minidump_failed = 0;
1486400f 2886
7c3df132
SK		 2887 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2888 "Init done and hba is online.\n");
2889
2d70c103
NB		 2890 if (qla_ini_mode_enabled(base_vha))
2891 scsi_scan_host(host);
2892 else
2893 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2894 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2895
e315cd28 2896 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2897
8ae6d9c7 2898 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 2899 ret = qlafx00_fx_disc(base_vha,
2900 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2901
2902 /* Register system information */
2903 ret = qlafx00_fx_disc(base_vha,
2904 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2905 }
2906
e315cd28 2907 qla2x00_init_host_attr(base_vha);
a1541d5a 2908
e315cd28 2909 qla2x00_dfs_setup(base_vha);
df613b96 2910
03eb912a
AB		 2911 ql_log(ql_log_info, base_vha, 0x00fb,
2912 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 2913 ql_log(ql_log_info, base_vha, 0x00fc,
2914 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2915 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2916 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2917 base_vha->host_no,
e315cd28 2918 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2919
2d70c103
NB		 2920 qlt_add_target(ha, base_vha);
2921
1da177e4
LT		 2922 return 0;
2923
6e9f21f3 2924probe_init_failed:
2afa19a9 2925 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2926 ha->req_q_map[0] = NULL;
2927 clear_bit(0, ha->req_qid_map);
2afa19a9 2928 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2929 ha->rsp_q_map[0] = NULL;
2930 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2931 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2932
1da177e4 2933probe_failed:
b9978769
AV		 2934 if (base_vha->timer_active)
2935 qla2x00_stop_timer(base_vha);
2936 base_vha->flags.online = 0;
2937 if (ha->dpc_thread) {
2938 struct task_struct *t = ha->dpc_thread;
2939
2940 ha->dpc_thread = NULL;
2941 kthread_stop(t);
2942 }
2943
e315cd28 2944 qla2x00_free_device(base_vha);
1da177e4 2945
e315cd28 2946 scsi_host_put(base_vha->host);
1da177e4 2947
e315cd28 2948probe_hw_failed:
a9083016
GM		 2949 if (IS_QLA82XX(ha)) {
2950 qla82xx_idc_lock(ha);
2951 qla82xx_clear_drv_active(ha);
2952 qla82xx_idc_unlock(ha);
0a63ad12 2953 }
7ec0effd
AD		 2954 if (IS_QLA8044(ha)) {
2955 qla8044_idc_lock(ha);
c41afc9a 2956 qla8044_clear_drv_active(ha);
7ec0effd
AD		 2957 qla8044_idc_unlock(ha);
2958 }
0a63ad12 2959iospace_config_failed:
7ec0effd 2960 if (IS_P3P_TYPE(ha)) {
0a63ad12 2961 if (!ha->nx_pcibase)
f73cb695 2962 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 2963 if (!ql2xdbwr)
f73cb695 2964 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 2965 } else {
2966 if (ha->iobase)
2967 iounmap(ha->iobase);
8ae6d9c7
GM		 2968 if (ha->cregbase)
2969 iounmap(ha->cregbase);
a9083016 2970 }
e315cd28
AC		 2971 pci_release_selected_regions(ha->pdev, ha->bars);
2972 kfree(ha);
2973 ha = NULL;
1da177e4 2974
a1541d5a 2975probe_out:
e315cd28 2976 pci_disable_device(pdev);
a1541d5a 2977 return ret;
1da177e4 2978}
1da177e4 2979
e30d1756
MI		 2980static void
2981qla2x00_shutdown(struct pci_dev *pdev)
2982{
2983 scsi_qla_host_t *vha;
2984 struct qla_hw_data *ha;
2985
552f3f9a
MI		 2986 if (!atomic_read(&pdev->enable_cnt))
2987 return;
2988
e30d1756
MI		 2989 vha = pci_get_drvdata(pdev);
2990 ha = vha->hw;
2991
42479343
AB		 2992 /* Notify ISPFX00 firmware */
2993 if (IS_QLAFX00(ha))
2994 qlafx00_driver_shutdown(vha, 20);
2995
e30d1756
MI		 2996 /* Turn-off FCE trace */
2997 if (ha->flags.fce_enabled) {
2998 qla2x00_disable_fce_trace(vha, NULL, NULL);
2999 ha->flags.fce_enabled = 0;
3000 }
3001
3002 /* Turn-off EFT trace */
3003 if (ha->eft)
3004 qla2x00_disable_eft_trace(vha);
3005
3006 /* Stop currently executing firmware. */
3007 qla2x00_try_to_stop_firmware(vha);
3008
3009 /* Turn adapter off line */
3010 vha->flags.online = 0;
3011
3012 /* turn-off interrupts on the card */
3013 if (ha->interrupts_on) {
3014 vha->flags.init_done = 0;
3015 ha->isp_ops->disable_intrs(ha);
3016 }
3017
3018 qla2x00_free_irqs(vha);
3019
3020 qla2x00_free_fw_dump(ha);
3021}
3022
fe1b806f 3023/* Deletes all the virtual ports for a given ha */
4c993f76 3024static void
fe1b806f 3025qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3026{
fe1b806f
CD		 3027 struct Scsi_Host *scsi_host;
3028 scsi_qla_host_t *vha;
feafb7b1 3029 unsigned long flags;
e315cd28 3030
43ebf16d
AE		 3031 mutex_lock(&ha->vport_lock);
3032 while (ha->cur_vport_count) {
43ebf16d 3033 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3034
43ebf16d
AE		 3035 BUG_ON(base_vha->list.next == &ha->vp_list);
3036 /* This assumes first entry in ha->vp_list is always base vha */
3037 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
fe1b806f 3038 scsi_host = scsi_host_get(vha->host);
feafb7b1 3039
43ebf16d
AE		 3040 spin_unlock_irqrestore(&ha->vport_slock, flags);
3041 mutex_unlock(&ha->vport_lock);
3042
3043 fc_vport_terminate(vha->fc_vport);
3044 scsi_host_put(vha->host);
feafb7b1 3045
43ebf16d 3046 mutex_lock(&ha->vport_lock);
e315cd28 3047 }
43ebf16d 3048 mutex_unlock(&ha->vport_lock);
fe1b806f 3049}
1da177e4 3050
fe1b806f
CD		 3051/* Stops all deferred work threads */
3052static void
3053qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3054{
68ca949c
AC		 3055 /* Flush the work queue and remove it */
3056 if (ha->wq) {
3057 flush_workqueue(ha->wq);
3058 destroy_workqueue(ha->wq);
3059 ha->wq = NULL;
3060 }
3061
7d613ac6
SV		 3062 /* Cancel all work and destroy DPC workqueues */
3063 if (ha->dpc_lp_wq) {
3064 cancel_work_sync(&ha->idc_aen);
3065 destroy_workqueue(ha->dpc_lp_wq);
3066 ha->dpc_lp_wq = NULL;
3067 }
3068
3069 if (ha->dpc_hp_wq) {
3070 cancel_work_sync(&ha->nic_core_reset);
3071 cancel_work_sync(&ha->idc_state_handler);
3072 cancel_work_sync(&ha->nic_core_unrecoverable);
3073 destroy_workqueue(ha->dpc_hp_wq);
3074 ha->dpc_hp_wq = NULL;
3075 }
3076
b9978769
AV		 3077 /* Kill the kernel thread for this host */
3078 if (ha->dpc_thread) {
3079 struct task_struct *t = ha->dpc_thread;
3080
3081 /*
3082 * qla2xxx_wake_dpc checks for ->dpc_thread
3083 * so we need to zero it out.
3084 */
3085 ha->dpc_thread = NULL;
3086 kthread_stop(t);
3087 }
fe1b806f 3088}
1da177e4 3089
fe1b806f
CD		 3090static void
3091qla2x00_unmap_iobases(struct qla_hw_data *ha)
3092{
a9083016 3093 if (IS_QLA82XX(ha)) {
b963752f 3094
f73cb695 3095 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3096 if (!ql2xdbwr)
f73cb695 3097 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3098 } else {
3099 if (ha->iobase)
3100 iounmap(ha->iobase);
1da177e4 3101
8ae6d9c7
GM		 3102 if (ha->cregbase)
3103 iounmap(ha->cregbase);
3104
a9083016
GM		 3105 if (ha->mqiobase)
3106 iounmap(ha->mqiobase);
6246b8a1 3107
f73cb695 3108 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3109 iounmap(ha->msixbase);
a9083016 3110 }
fe1b806f
CD		 3111}
3112
3113static void
3114qla2x00_clear_drv_active(scsi_qla_host_t *vha)
3115{
3116 struct qla_hw_data *ha = vha->hw;
3117
3118 if (IS_QLA8044(ha)) {
3119 qla8044_idc_lock(ha);
c41afc9a 3120 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3121 qla8044_idc_unlock(ha);
3122 } else if (IS_QLA82XX(ha)) {
3123 qla82xx_idc_lock(ha);
3124 qla82xx_clear_drv_active(ha);
3125 qla82xx_idc_unlock(ha);
3126 }
3127}
3128
3129static void
3130qla2x00_remove_one(struct pci_dev *pdev)
3131{
3132 scsi_qla_host_t *base_vha;
3133 struct qla_hw_data *ha;
3134
3135 /*
3136 * If the PCI device is disabled that means that probe failed and any
3137 * resources should be have cleaned up on probe exit.
3138 */
3139 if (!atomic_read(&pdev->enable_cnt))
3140 return;
3141
3142 base_vha = pci_get_drvdata(pdev);
3143 ha = base_vha->hw;
3144
638a1a01
SC		 3145 qla2x00_wait_for_hba_ready(base_vha);
3146
fe1b806f
CD		 3147 set_bit(UNLOADING, &base_vha->dpc_flags);
3148
3149 if (IS_QLAFX00(ha))
3150 qlafx00_driver_shutdown(base_vha, 20);
3151
3152 qla2x00_delete_all_vps(ha, base_vha);
3153
3154 if (IS_QLA8031(ha)) {
3155 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3156 "Clearing fcoe driver presence.\n");
3157 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3158 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3159 "Error while clearing DRV-Presence.\n");
3160 }
3161
3162 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3163
3164 qla2x00_dfs_remove(base_vha);
3165
3166 qla84xx_put_chip(base_vha);
3167
3168 /* Disable timer */
3169 if (base_vha->timer_active)
3170 qla2x00_stop_timer(base_vha);
3171
3172 base_vha->flags.online = 0;
3173
3174 qla2x00_destroy_deferred_work(ha);
3175
3176 qlt_remove_target(ha, base_vha);
3177
3178 qla2x00_free_sysfs_attr(base_vha, true);
3179
3180 fc_remove_host(base_vha->host);
3181
3182 scsi_remove_host(base_vha->host);
3183
3184 qla2x00_free_device(base_vha);
3185
3186 scsi_host_put(base_vha->host);
3187
3188 qla2x00_clear_drv_active(base_vha);
3189
3190 qla2x00_unmap_iobases(ha);
73208dfd 3191
e315cd28
AC		 3192 pci_release_selected_regions(ha->pdev, ha->bars);
3193 kfree(ha);
3194 ha = NULL;
1da177e4 3195
90a86fc0
JC		 3196 pci_disable_pcie_error_reporting(pdev);
3197
665db93b 3198 pci_disable_device(pdev);
1da177e4 3199}
1da177e4
LT		 3200
3201static void
e315cd28 3202qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3203{
e315cd28 3204 struct qla_hw_data *ha = vha->hw;
1da177e4 3205
85880801
AV		 3206 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3207
3208 /* Disable timer */
3209 if (vha->timer_active)
3210 qla2x00_stop_timer(vha);
3211
2afa19a9 3212 qla25xx_delete_queues(vha);
fe1b806f 3213
df613b96 3214 if (ha->flags.fce_enabled)
e315cd28 3215 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3216
a7a167bf 3217 if (ha->eft)
e315cd28 3218 qla2x00_disable_eft_trace(vha);
a7a167bf 3219
f6ef3b18 3220 /* Stop currently executing firmware. */
e315cd28 3221 qla2x00_try_to_stop_firmware(vha);
1da177e4 3222
85880801
AV		 3223 vha->flags.online = 0;
3224
f6ef3b18 3225 /* turn-off interrupts on the card */
a9083016
GM		 3226 if (ha->interrupts_on) {
3227 vha->flags.init_done = 0;
fd34f556 3228 ha->isp_ops->disable_intrs(ha);
a9083016 3229 }
f6ef3b18 3230
e315cd28 3231 qla2x00_free_irqs(vha);
1da177e4 3232
8867048b
CD		 3233 qla2x00_free_fcports(vha);
3234
e315cd28 3235 qla2x00_mem_free(ha);
73208dfd 3236
08de2844
GM		 3237 qla82xx_md_free(vha);
3238
73208dfd 3239 qla2x00_free_queues(ha);
1da177e4
LT		 3240}
3241
8867048b
CD		 3242void qla2x00_free_fcports(struct scsi_qla_host *vha)
3243{
3244 fc_port_t *fcport, *tfcport;
3245
3246 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3247 list_del(&fcport->list);
5f16b331 3248 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3249 kfree(fcport);
3250 fcport = NULL;
3251 }
3252}
3253
d97994dc 3254static inline void
e315cd28 3255qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc 3256 int defer)
3257{
d97994dc 3258 struct fc_rport *rport;
67becc00 3259 scsi_qla_host_t *base_vha;
044d78e1 3260 unsigned long flags;
d97994dc 3261
3262 if (!fcport->rport)
3263 return;
3264
3265 rport = fcport->rport;
3266 if (defer) {
67becc00 3267 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3268 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3269 fcport->drport = rport;
044d78e1 3270 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 3271 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3272 qla2xxx_wake_dpc(base_vha);
2d70c103 3273 } else {
d97994dc 3274 fc_remote_port_delete(rport);
2d70c103
NB		 3275 qlt_fc_port_deleted(vha, fcport);
3276 }
d97994dc 3277}
3278
1da177e4
LT		 3279/*
3280 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3281 *
3282 * Input: ha = adapter block pointer. fcport = port structure pointer.
3283 *
3284 * Return: None.
3285 *
3286 * Context:
3287 */
e315cd28 3288void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3289 int do_login, int defer)
1da177e4 3290{
8ae6d9c7
GM		 3291 if (IS_QLAFX00(vha->hw)) {
3292 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3293 qla2x00_schedule_rport_del(vha, fcport, defer);
3294 return;
3295 }
3296
2c3dfe3f 3297 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3298 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3299 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3300 qla2x00_schedule_rport_del(vha, fcport, defer);
3301 }
fa2a1ce5 3302 /*
1da177e4
LT		 3303 * We may need to retry the login, so don't change the state of the
3304 * port but do the retries.
3305 */
3306 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3307 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3308
3309 if (!do_login)
3310 return;
3311
3312 if (fcport->login_retry == 0) {
e315cd28
AC		 3313 fcport->login_retry = vha->hw->login_retry_count;
3314 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 3315
7c3df132 3316 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3317 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3318 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3319 }
3320}
3321
3322/*
3323 * qla2x00_mark_all_devices_lost
3324 * Updates fcport state when device goes offline.
3325 *
3326 * Input:
3327 * ha = adapter block pointer.
3328 * fcport = port structure pointer.
3329 *
3330 * Return:
3331 * None.
3332 *
3333 * Context:
3334 */
3335void
e315cd28 3336qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3337{
3338 fc_port_t *fcport;
3339
e315cd28 3340 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3341 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3342 continue;
0d6e61bc 3343
1da177e4
LT		 3344 /*
3345 * No point in marking the device as lost, if the device is
3346 * already DEAD.
3347 */
3348 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3349 continue;
e315cd28 3350 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3351 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3352 if (defer)
3353 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3354 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3355 qla2x00_schedule_rport_del(vha, fcport, defer);
3356 }
1da177e4
LT		 3357 }
3358}
3359
3360/*
3361* qla2x00_mem_alloc
3362* Allocates adapter memory.
3363*
3364* Returns:
3365* 0 = success.
e8711085 3366* !0 = failure.
1da177e4 3367*/
e8711085 3368static int
73208dfd
AC		 3369qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3370 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3371{
3372 char name[16];
1da177e4 3373
e8711085 3374 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3375 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3376 if (!ha->init_cb)
e315cd28 3377 goto fail;
e8711085 3378
2d70c103
NB		 3379 if (qlt_mem_alloc(ha) < 0)
3380 goto fail_free_init_cb;
3381
642ef983
CD		 3382 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3383 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3384 if (!ha->gid_list)
2d70c103 3385 goto fail_free_tgt_mem;
1da177e4 3386
e8711085
AV		 3387 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3388 if (!ha->srb_mempool)
e315cd28 3389 goto fail_free_gid_list;
e8711085 3390
7ec0effd 3391 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3392 /* Allocate cache for CT6 Ctx. */
3393 if (!ctx_cachep) {
3394 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3395 sizeof(struct ct6_dsd), 0,
3396 SLAB_HWCACHE_ALIGN, NULL);
3397 if (!ctx_cachep)
3398 goto fail_free_gid_list;
3399 }
3400 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3401 ctx_cachep);
3402 if (!ha->ctx_mempool)
3403 goto fail_free_srb_mempool;
7c3df132
SK		 3404 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3405 "ctx_cachep=%p ctx_mempool=%p.\n",
3406 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3407 }
3408
e8711085
AV		 3409 /* Get memory for cached NVRAM */
3410 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3411 if (!ha->nvram)
a9083016 3412 goto fail_free_ctx_mempool;
e8711085 3413
e315cd28
AC		 3414 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3415 ha->pdev->device);
3416 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3417 DMA_POOL_SIZE, 8, 0);
3418 if (!ha->s_dma_pool)
3419 goto fail_free_nvram;
3420
7c3df132
SK		 3421 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3422 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3423 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3424
7ec0effd 3425 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3426 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3427 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3428 if (!ha->dl_dma_pool) {
7c3df132
SK		 3429 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3430 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3431 goto fail_s_dma_pool;
3432 }
3433
3434 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3435 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3436 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3437 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3438 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3439 goto fail_dl_dma_pool;
3440 }
7c3df132
SK		 3441 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3442 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3443 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3444 }
3445
e8711085
AV		 3446 /* Allocate memory for SNS commands */
3447 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3448 /* Get consistent memory allocated for SNS commands */
e8711085 3449 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3450 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3451 if (!ha->sns_cmd)
e315cd28 3452 goto fail_dma_pool;
7c3df132 3453 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3454 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3455 } else {
e315cd28 3456 /* Get consistent memory allocated for MS IOCB */
e8711085 3457 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3458 &ha->ms_iocb_dma);
e8711085 3459 if (!ha->ms_iocb)
e315cd28
AC		 3460 goto fail_dma_pool;
3461 /* Get consistent memory allocated for CT SNS commands */
e8711085 3462 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3463 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3464 if (!ha->ct_sns)
3465 goto fail_free_ms_iocb;
7c3df132
SK		 3466 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3467 "ms_iocb=%p ct_sns=%p.\n",
3468 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3469 }
3470
e315cd28 3471 /* Allocate memory for request ring */
73208dfd
AC		 3472 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3473 if (!*req) {
7c3df132
SK		 3474 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3475 "Failed to allocate memory for req.\n");
e315cd28
AC		 3476 goto fail_req;
3477 }
73208dfd
AC		 3478 (*req)->length = req_len;
3479 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3480 ((*req)->length + 1) * sizeof(request_t),
3481 &(*req)->dma, GFP_KERNEL);
3482 if (!(*req)->ring) {
7c3df132
SK		 3483 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3484 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3485 goto fail_req_ring;
3486 }
3487 /* Allocate memory for response ring */
73208dfd
AC		 3488 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3489 if (!*rsp) {
7c3df132
SK		 3490 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3491 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3492 goto fail_rsp;
3493 }
73208dfd
AC		 3494 (*rsp)->hw = ha;
3495 (*rsp)->length = rsp_len;
3496 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3497 ((*rsp)->length + 1) * sizeof(response_t),
3498 &(*rsp)->dma, GFP_KERNEL);
3499 if (!(*rsp)->ring) {
7c3df132
SK		 3500 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3501 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3502 goto fail_rsp_ring;
3503 }
73208dfd
AC		 3504 (*req)->rsp = *rsp;
3505 (*rsp)->req = *req;
7c3df132
SK		 3506 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3507 "req=%p req->length=%d req->ring=%p rsp=%p "
3508 "rsp->length=%d rsp->ring=%p.\n",
3509 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3510 (*rsp)->ring);
73208dfd
AC		 3511 /* Allocate memory for NVRAM data for vports */
3512 if (ha->nvram_npiv_size) {
3513 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3514 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3515 if (!ha->npiv_info) {
7c3df132
SK		 3516 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3517 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3518 goto fail_npiv_info;
3519 }
3520 } else
3521 ha->npiv_info = NULL;
e8711085 3522
b64b0e8f 3523 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3524 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3525 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3526 &ha->ex_init_cb_dma);
3527 if (!ha->ex_init_cb)
3528 goto fail_ex_init_cb;
7c3df132
SK		 3529 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3530 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3531 }
3532
a9083016
GM		 3533 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3534
5ff1d584
AV		 3535 /* Get consistent memory allocated for Async Port-Database. */
3536 if (!IS_FWI2_CAPABLE(ha)) {
3537 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3538 &ha->async_pd_dma);
3539 if (!ha->async_pd)
3540 goto fail_async_pd;
7c3df132
SK		 3541 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3542 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3543 }
3544
e315cd28 3545 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3546
3547 /* Allocate memory for our loop_id bitmap */
3548 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3549 GFP_KERNEL);
3550 if (!ha->loop_id_map)
3551 goto fail_async_pd;
3552 else {
3553 qla2x00_set_reserved_loop_ids(ha);
3554 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3555 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3556 }
3557
b2a72ec3 3558 return 0;
e315cd28 3559
5ff1d584
AV		 3560fail_async_pd:
3561 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3562fail_ex_init_cb:
3563 kfree(ha->npiv_info);
73208dfd
AC		 3564fail_npiv_info:
3565 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3566 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3567 (*rsp)->ring = NULL;
3568 (*rsp)->dma = 0;
e315cd28 3569fail_rsp_ring:
73208dfd 3570 kfree(*rsp);
e315cd28 3571fail_rsp:
73208dfd
AC		 3572 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3573 sizeof(request_t), (*req)->ring, (*req)->dma);
3574 (*req)->ring = NULL;
3575 (*req)->dma = 0;
e315cd28 3576fail_req_ring:
73208dfd 3577 kfree(*req);
e315cd28
AC		 3578fail_req:
3579 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3580 ha->ct_sns, ha->ct_sns_dma);
3581 ha->ct_sns = NULL;
3582 ha->ct_sns_dma = 0;
e8711085
AV		 3583fail_free_ms_iocb:
3584 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3585 ha->ms_iocb = NULL;
3586 ha->ms_iocb_dma = 0;
e315cd28 3587fail_dma_pool:
bad75002 3588 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3589 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3590 ha->fcp_cmnd_dma_pool = NULL;
3591 }
3592fail_dl_dma_pool:
bad75002 3593 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3594 dma_pool_destroy(ha->dl_dma_pool);
3595 ha->dl_dma_pool = NULL;
3596 }
3597fail_s_dma_pool:
e315cd28
AC		 3598 dma_pool_destroy(ha->s_dma_pool);
3599 ha->s_dma_pool = NULL;
e8711085
AV		 3600fail_free_nvram:
3601 kfree(ha->nvram);
3602 ha->nvram = NULL;
a9083016
GM		 3603fail_free_ctx_mempool:
3604 mempool_destroy(ha->ctx_mempool);
3605 ha->ctx_mempool = NULL;
e8711085
AV		 3606fail_free_srb_mempool:
3607 mempool_destroy(ha->srb_mempool);
3608 ha->srb_mempool = NULL;
e8711085 3609fail_free_gid_list:
642ef983
CD		 3610 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3611 ha->gid_list,
e315cd28 3612 ha->gid_list_dma);
e8711085
AV		 3613 ha->gid_list = NULL;
3614 ha->gid_list_dma = 0;
2d70c103
NB		 3615fail_free_tgt_mem:
3616 qlt_mem_free(ha);
e315cd28
AC		 3617fail_free_init_cb:
3618 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3619 ha->init_cb_dma);
3620 ha->init_cb = NULL;
3621 ha->init_cb_dma = 0;
e8711085 3622fail:
7c3df132
SK		 3623 ql_log(ql_log_fatal, NULL, 0x0030,
3624 "Memory allocation failure.\n");
e8711085 3625 return -ENOMEM;
1da177e4
LT		 3626}
3627
3628/*
e30d1756
MI		 3629* qla2x00_free_fw_dump
3630* Frees fw dump stuff.
1da177e4
LT		 3631*
3632* Input:
7ec0effd 3633* ha = adapter block pointer
1da177e4 3634*/
a824ebb3 3635static void
e30d1756 3636qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3637{
df613b96 3638 if (ha->fce)
f73cb695
CD		 3639 dma_free_coherent(&ha->pdev->dev,
3640 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 3641
f73cb695
CD		 3642 if (ha->eft)
3643 dma_free_coherent(&ha->pdev->dev,
3644 EFT_SIZE, ha->eft, ha->eft_dma);
3645
3646 if (ha->fw_dump)
a7a167bf 3647 vfree(ha->fw_dump);
f73cb695
CD		 3648 if (ha->fw_dump_template)
3649 vfree(ha->fw_dump_template);
3650
e30d1756
MI		 3651 ha->fce = NULL;
3652 ha->fce_dma = 0;
3653 ha->eft = NULL;
3654 ha->eft_dma = 0;
e30d1756 3655 ha->fw_dumped = 0;
61f098dd 3656 ha->fw_dump_cap_flags = 0;
e30d1756 3657 ha->fw_dump_reading = 0;
f73cb695
CD		 3658 ha->fw_dump = NULL;
3659 ha->fw_dump_len = 0;
3660 ha->fw_dump_template = NULL;
3661 ha->fw_dump_template_len = 0;
e30d1756
MI		 3662}
3663
3664/*
3665* qla2x00_mem_free
3666* Frees all adapter allocated memory.
3667*
3668* Input:
3669* ha = adapter block pointer.
3670*/
3671static void
3672qla2x00_mem_free(struct qla_hw_data *ha)
3673{
3674 qla2x00_free_fw_dump(ha);
3675
81178772
SK		 3676 if (ha->mctp_dump)
3677 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3678 ha->mctp_dump_dma);
3679
e30d1756
MI		 3680 if (ha->srb_mempool)
3681 mempool_destroy(ha->srb_mempool);
a7a167bf 3682
11bbc1d8
AV		 3683 if (ha->dcbx_tlv)
3684 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3685 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3686
ce0423f4
AV		 3687 if (ha->xgmac_data)
3688 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3689 ha->xgmac_data, ha->xgmac_data_dma);
3690
1da177e4
LT		 3691 if (ha->sns_cmd)
3692 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3693 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3694
3695 if (ha->ct_sns)
3696 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3697 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3698
88729e53
AV		 3699 if (ha->sfp_data)
3700 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3701
1da177e4
LT		 3702 if (ha->ms_iocb)
3703 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3704
b64b0e8f 3705 if (ha->ex_init_cb)
a9083016
GM		 3706 dma_pool_free(ha->s_dma_pool,
3707 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3708
5ff1d584
AV		 3709 if (ha->async_pd)
3710 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3711
1da177e4
LT		 3712 if (ha->s_dma_pool)
3713 dma_pool_destroy(ha->s_dma_pool);
3714
1da177e4 3715 if (ha->gid_list)
642ef983
CD		 3716 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3717 ha->gid_list, ha->gid_list_dma);
1da177e4 3718
a9083016
GM		 3719 if (IS_QLA82XX(ha)) {
3720 if (!list_empty(&ha->gbl_dsd_list)) {
3721 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3722
3723 /* clean up allocated prev pool */
3724 list_for_each_entry_safe(dsd_ptr,
3725 tdsd_ptr, &ha->gbl_dsd_list, list) {
3726 dma_pool_free(ha->dl_dma_pool,
3727 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3728 list_del(&dsd_ptr->list);
3729 kfree(dsd_ptr);
3730 }
3731 }
3732 }
3733
3734 if (ha->dl_dma_pool)
3735 dma_pool_destroy(ha->dl_dma_pool);
3736
3737 if (ha->fcp_cmnd_dma_pool)
3738 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3739
3740 if (ha->ctx_mempool)
3741 mempool_destroy(ha->ctx_mempool);
3742
2d70c103
NB		 3743 qlt_mem_free(ha);
3744
e315cd28
AC		 3745 if (ha->init_cb)
3746 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3747 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3748 vfree(ha->optrom_buffer);
3749 kfree(ha->nvram);
73208dfd 3750 kfree(ha->npiv_info);
7a67735b 3751 kfree(ha->swl);
5f16b331 3752 kfree(ha->loop_id_map);
1da177e4 3753
e8711085 3754 ha->srb_mempool = NULL;
a9083016 3755 ha->ctx_mempool = NULL;
1da177e4
LT		 3756 ha->sns_cmd = NULL;
3757 ha->sns_cmd_dma = 0;
3758 ha->ct_sns = NULL;
3759 ha->ct_sns_dma = 0;
3760 ha->ms_iocb = NULL;
3761 ha->ms_iocb_dma = 0;
1da177e4
LT		 3762 ha->init_cb = NULL;
3763 ha->init_cb_dma = 0;
b64b0e8f
AV		 3764 ha->ex_init_cb = NULL;
3765 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3766 ha->async_pd = NULL;
3767 ha->async_pd_dma = 0;
1da177e4
LT		 3768
3769 ha->s_dma_pool = NULL;
a9083016
GM		 3770 ha->dl_dma_pool = NULL;
3771 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3772
1da177e4
LT		 3773 ha->gid_list = NULL;
3774 ha->gid_list_dma = 0;
2d70c103
NB		 3775
3776 ha->tgt.atio_ring = NULL;
3777 ha->tgt.atio_dma = 0;
3778 ha->tgt.tgt_vp_map = NULL;
e315cd28 3779}
1da177e4 3780
e315cd28
AC		 3781struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3782 struct qla_hw_data *ha)
3783{
3784 struct Scsi_Host *host;
3785 struct scsi_qla_host *vha = NULL;
854165f4 3786
e315cd28
AC		 3787 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3788 if (host == NULL) {
7c3df132
SK		 3789 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3790 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3791 goto fail;
3792 }
3793
3794 /* Clear our data area */
3795 vha = shost_priv(host);
3796 memset(vha, 0, sizeof(scsi_qla_host_t));
3797
3798 vha->host = host;
3799 vha->host_no = host->host_no;
3800 vha->hw = ha;
3801
3802 INIT_LIST_HEAD(&vha->vp_fcports);
3803 INIT_LIST_HEAD(&vha->work_list);
3804 INIT_LIST_HEAD(&vha->list);
3805
f999f4c1
AV		 3806 spin_lock_init(&vha->work_lock);
3807
e315cd28 3808 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3809 ql_dbg(ql_dbg_init, vha, 0x0041,
3810 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3811 vha->host, vha->hw, vha,
3812 dev_name(&(ha->pdev->dev)));
3813
e315cd28
AC		 3814 return vha;
3815
3816fail:
3817 return vha;
1da177e4
LT		 3818}
3819
01ef66bb 3820static struct qla_work_evt *
f999f4c1 3821qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3822{
3823 struct qla_work_evt *e;
feafb7b1
AE		 3824 uint8_t bail;
3825
3826 QLA_VHA_MARK_BUSY(vha, bail);
3827 if (bail)
3828 return NULL;
0971de7f 3829
f999f4c1 3830 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3831 if (!e) {
3832 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3833 return NULL;
feafb7b1 3834 }
0971de7f
AV		 3835
3836 INIT_LIST_HEAD(&e->list);
3837 e->type = type;
3838 e->flags = QLA_EVT_FLAG_FREE;
3839 return e;
3840}
3841
01ef66bb 3842static int
f999f4c1 3843qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3844{
f999f4c1 3845 unsigned long flags;
0971de7f 3846
f999f4c1 3847 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3848 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3849 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3850 qla2xxx_wake_dpc(vha);
f999f4c1 3851
0971de7f
AV		 3852 return QLA_SUCCESS;
3853}
3854
3855int
e315cd28 3856qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3857 u32 data)
3858{
3859 struct qla_work_evt *e;
3860
f999f4c1 3861 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3862 if (!e)
3863 return QLA_FUNCTION_FAILED;
3864
3865 e->u.aen.code = code;
3866 e->u.aen.data = data;
f999f4c1 3867 return qla2x00_post_work(vha, e);
0971de7f
AV		 3868}
3869
8a659571
AV		 3870int
3871qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3872{
3873 struct qla_work_evt *e;
3874
f999f4c1 3875 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3876 if (!e)
3877 return QLA_FUNCTION_FAILED;
3878
3879 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3880 return qla2x00_post_work(vha, e);
8a659571
AV		 3881}
3882
ac280b67
AV		 3883#define qla2x00_post_async_work(name, type) \
3884int qla2x00_post_async_##name##_work( \
3885 struct scsi_qla_host *vha, \
3886 fc_port_t *fcport, uint16_t *data) \
3887{ \
3888 struct qla_work_evt *e; \
3889 \
3890 e = qla2x00_alloc_work(vha, type); \
3891 if (!e) \
3892 return QLA_FUNCTION_FAILED; \
3893 \
3894 e->u.logio.fcport = fcport; \
3895 if (data) { \
3896 e->u.logio.data[0] = data[0]; \
3897 e->u.logio.data[1] = data[1]; \
3898 } \
3899 return qla2x00_post_work(vha, e); \
3900}
3901
3902qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3903qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3904qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3905qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3906qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3907qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3908
3420d36c
AV		 3909int
3910qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3911{
3912 struct qla_work_evt *e;
3913
3914 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3915 if (!e)
3916 return QLA_FUNCTION_FAILED;
3917
3918 e->u.uevent.code = code;
3919 return qla2x00_post_work(vha, e);
3920}
3921
3922static void
3923qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3924{
3925 char event_string[40];
3926 char *envp[] = { event_string, NULL };
3927
3928 switch (code) {
3929 case QLA_UEVENT_CODE_FW_DUMP:
3930 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3931 vha->host_no);
3932 break;
3933 default:
3934 /* do nothing */
3935 break;
3936 }
3937 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3938}
3939
8ae6d9c7
GM		 3940int
3941qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3942 uint32_t *data, int cnt)
3943{
3944 struct qla_work_evt *e;
3945
3946 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3947 if (!e)
3948 return QLA_FUNCTION_FAILED;
3949
3950 e->u.aenfx.evtcode = evtcode;
3951 e->u.aenfx.count = cnt;
3952 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3953 return qla2x00_post_work(vha, e);
3954}
3955
ac280b67 3956void
e315cd28 3957qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3958{
f999f4c1
AV		 3959 struct qla_work_evt *e, *tmp;
3960 unsigned long flags;
3961 LIST_HEAD(work);
0971de7f 3962
f999f4c1
AV		 3963 spin_lock_irqsave(&vha->work_lock, flags);
3964 list_splice_init(&vha->work_list, &work);
3965 spin_unlock_irqrestore(&vha->work_lock, flags);
3966
3967 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3968 list_del_init(&e->list);
0971de7f
AV		 3969
3970 switch (e->type) {
3971 case QLA_EVT_AEN:
e315cd28 3972 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3973 e->u.aen.code, e->u.aen.data);
3974 break;
8a659571
AV		 3975 case QLA_EVT_IDC_ACK:
3976 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3977 break;
ac280b67
AV		 3978 case QLA_EVT_ASYNC_LOGIN:
3979 qla2x00_async_login(vha, e->u.logio.fcport,
3980 e->u.logio.data);
3981 break;
3982 case QLA_EVT_ASYNC_LOGIN_DONE:
3983 qla2x00_async_login_done(vha, e->u.logio.fcport,
3984 e->u.logio.data);
3985 break;
3986 case QLA_EVT_ASYNC_LOGOUT:
3987 qla2x00_async_logout(vha, e->u.logio.fcport);
3988 break;
3989 case QLA_EVT_ASYNC_LOGOUT_DONE:
3990 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3991 e->u.logio.data);
3992 break;
5ff1d584
AV		 3993 case QLA_EVT_ASYNC_ADISC:
3994 qla2x00_async_adisc(vha, e->u.logio.fcport,
3995 e->u.logio.data);
3996 break;
3997 case QLA_EVT_ASYNC_ADISC_DONE:
3998 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3999 e->u.logio.data);
4000 break;
3420d36c
AV		 4001 case QLA_EVT_UEVENT:
4002 qla2x00_uevent_emit(vha, e->u.uevent.code);
4003 break;
8ae6d9c7
GM		 4004 case QLA_EVT_AENFX:
4005 qlafx00_process_aen(vha, e);
4006 break;
0971de7f
AV		 4007 }
4008 if (e->flags & QLA_EVT_FLAG_FREE)
4009 kfree(e);
feafb7b1
AE		 4010
4011 /* For each work completed decrement vha ref count */
4012 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4013 }
e315cd28 4014}
f999f4c1 4015
e315cd28
AC		 4016/* Relogins all the fcports of a vport
4017 * Context: dpc thread
4018 */
4019void qla2x00_relogin(struct scsi_qla_host *vha)
4020{
4021 fc_port_t *fcport;
c6b2fca8 4022 int status;
e315cd28
AC		 4023 uint16_t next_loopid = 0;
4024 struct qla_hw_data *ha = vha->hw;
ac280b67 4025 uint16_t data[2];
e315cd28
AC		 4026
4027 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4028 /*
4029 * If the port is not ONLINE then try to login
4030 * to it if we haven't run out of retries.
4031 */
5ff1d584
AV		 4032 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4033 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4034 fcport->login_retry--;
e315cd28 4035 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4036 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4037 ha->isp_ops->fabric_logout(vha,
4038 fcport->loop_id,
4039 fcport->d_id.b.domain,
4040 fcport->d_id.b.area,
4041 fcport->d_id.b.al_pa);
4042
03bcfb57
JC		 4043 if (fcport->loop_id == FC_NO_LOOP_ID) {
4044 fcport->loop_id = next_loopid =
4045 ha->min_external_loopid;
4046 status = qla2x00_find_new_loop_id(
4047 vha, fcport);
4048 if (status != QLA_SUCCESS) {
4049 /* Ran out of IDs to use */
4050 break;
4051 }
4052 }
4053
ac280b67 4054 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4055 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4056 data[0] = 0;
4057 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4058 status = qla2x00_post_async_login_work(
4059 vha, fcport, data);
4060 if (status == QLA_SUCCESS)
4061 continue;
4062 /* Attempt a retry. */
4063 status = 1;
aaf4d3e2 4064 } else {
ac280b67
AV		 4065 status = qla2x00_fabric_login(vha,
4066 fcport, &next_loopid);
aaf4d3e2
SK		 4067 if (status == QLA_SUCCESS) {
4068 int status2;
4069 uint8_t opts;
4070
4071 opts = 0;
4072 if (fcport->flags &
4073 FCF_FCP2_DEVICE)
4074 opts |= BIT_1;
03003960
SK		 4075 status2 =
4076 qla2x00_get_port_database(
4077 vha, fcport, opts);
aaf4d3e2
SK		 4078 if (status2 != QLA_SUCCESS)
4079 status = 1;
4080 }
4081 }
e315cd28
AC		 4082 } else
4083 status = qla2x00_local_device_login(vha,
4084 fcport);
4085
e315cd28
AC		 4086 if (status == QLA_SUCCESS) {
4087 fcport->old_loop_id = fcport->loop_id;
4088
7c3df132
SK		 4089 ql_dbg(ql_dbg_disc, vha, 0x2003,
4090 "Port login OK: logged in ID 0x%x.\n",
4091 fcport->loop_id);
e315cd28
AC		 4092
4093 qla2x00_update_fcport(vha, fcport);
4094
4095 } else if (status == 1) {
4096 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4097 /* retry the login again */
7c3df132
SK		 4098 ql_dbg(ql_dbg_disc, vha, 0x2007,
4099 "Retrying %d login again loop_id 0x%x.\n",
4100 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4101 } else {
4102 fcport->login_retry = 0;
4103 }
4104
4105 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4106 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4107 }
4108 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4109 break;
0971de7f 4110 }
0971de7f
AV		 4111}
4112
7d613ac6
SV		 4113/* Schedule work on any of the dpc-workqueues */
4114void
4115qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4116{
4117 struct qla_hw_data *ha = base_vha->hw;
4118
4119 switch (work_code) {
4120 case MBA_IDC_AEN: /* 0x8200 */
4121 if (ha->dpc_lp_wq)
4122 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4123 break;
4124
4125 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4126 if (!ha->flags.nic_core_reset_hdlr_active) {
4127 if (ha->dpc_hp_wq)
4128 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4129 } else
4130 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4131 "NIC Core reset is already active. Skip "
4132 "scheduling it again.\n");
4133 break;
4134 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4135 if (ha->dpc_hp_wq)
4136 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4137 break;
4138 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4139 if (ha->dpc_hp_wq)
4140 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4141 break;
4142 default:
4143 ql_log(ql_log_warn, base_vha, 0xb05f,
4144 "Unknow work-code=0x%x.\n", work_code);
4145 }
4146
4147 return;
4148}
4149
4150/* Work: Perform NIC Core Unrecoverable state handling */
4151void
4152qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4153{
4154 struct qla_hw_data *ha =
2ad1b67c 4155 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4156 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4157 uint32_t dev_state = 0;
4158
4159 qla83xx_idc_lock(base_vha, 0);
4160 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4161 qla83xx_reset_ownership(base_vha);
4162 if (ha->flags.nic_core_reset_owner) {
4163 ha->flags.nic_core_reset_owner = 0;
4164 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4165 QLA8XXX_DEV_FAILED);
4166 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4167 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4168 }
4169 qla83xx_idc_unlock(base_vha, 0);
4170}
4171
4172/* Work: Execute IDC state handler */
4173void
4174qla83xx_idc_state_handler_work(struct work_struct *work)
4175{
4176 struct qla_hw_data *ha =
2ad1b67c 4177 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4178 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4179 uint32_t dev_state = 0;
4180
4181 qla83xx_idc_lock(base_vha, 0);
4182 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4183 if (dev_state == QLA8XXX_DEV_FAILED ||
4184 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4185 qla83xx_idc_state_handler(base_vha);
4186 qla83xx_idc_unlock(base_vha, 0);
4187}
4188
fa492630 4189static int
7d613ac6
SV		 4190qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4191{
4192 int rval = QLA_SUCCESS;
4193 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4194 uint32_t heart_beat_counter1, heart_beat_counter2;
4195
4196 do {
4197 if (time_after(jiffies, heart_beat_wait)) {
4198 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4199 "Nic Core f/w is not alive.\n");
4200 rval = QLA_FUNCTION_FAILED;
4201 break;
4202 }
4203
4204 qla83xx_idc_lock(base_vha, 0);
4205 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4206 &heart_beat_counter1);
4207 qla83xx_idc_unlock(base_vha, 0);
4208 msleep(100);
4209 qla83xx_idc_lock(base_vha, 0);
4210 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4211 &heart_beat_counter2);
4212 qla83xx_idc_unlock(base_vha, 0);
4213 } while (heart_beat_counter1 == heart_beat_counter2);
4214
4215 return rval;
4216}
4217
4218/* Work: Perform NIC Core Reset handling */
4219void
4220qla83xx_nic_core_reset_work(struct work_struct *work)
4221{
4222 struct qla_hw_data *ha =
4223 container_of(work, struct qla_hw_data, nic_core_reset);
4224 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4225 uint32_t dev_state = 0;
4226
81178772
SK		 4227 if (IS_QLA2031(ha)) {
4228 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4229 ql_log(ql_log_warn, base_vha, 0xb081,
4230 "Failed to dump mctp\n");
4231 return;
4232 }
4233
7d613ac6
SV		 4234 if (!ha->flags.nic_core_reset_hdlr_active) {
4235 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4236 qla83xx_idc_lock(base_vha, 0);
4237 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4238 &dev_state);
4239 qla83xx_idc_unlock(base_vha, 0);
4240 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4241 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4242 "Nic Core f/w is alive.\n");
4243 return;
4244 }
4245 }
4246
4247 ha->flags.nic_core_reset_hdlr_active = 1;
4248 if (qla83xx_nic_core_reset(base_vha)) {
4249 /* NIC Core reset failed. */
4250 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4251 "NIC Core reset failed.\n");
4252 }
4253 ha->flags.nic_core_reset_hdlr_active = 0;
4254 }
4255}
4256
4257/* Work: Handle 8200 IDC aens */
4258void
4259qla83xx_service_idc_aen(struct work_struct *work)
4260{
4261 struct qla_hw_data *ha =
4262 container_of(work, struct qla_hw_data, idc_aen);
4263 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4264 uint32_t dev_state, idc_control;
4265
4266 qla83xx_idc_lock(base_vha, 0);
4267 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4268 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4269 qla83xx_idc_unlock(base_vha, 0);
4270 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4271 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4272 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4273 "Application requested NIC Core Reset.\n");
4274 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4275 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4276 QLA_SUCCESS) {
4277 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4278 "Other protocol driver requested NIC Core Reset.\n");
4279 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4280 }
4281 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4282 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4283 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4284 }
4285}
4286
4287static void
4288qla83xx_wait_logic(void)
4289{
4290 int i;
4291
4292 /* Yield CPU */
4293 if (!in_interrupt()) {
4294 /*
4295 * Wait about 200ms before retrying again.
4296 * This controls the number of retries for single
4297 * lock operation.
4298 */
4299 msleep(100);
4300 schedule();
4301 } else {
4302 for (i = 0; i < 20; i++)
4303 cpu_relax(); /* This a nop instr on i386 */
4304 }
4305}
4306
fa492630 4307static int
7d613ac6
SV		 4308qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4309{
4310 int rval;
4311 uint32_t data;
4312 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4313 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4314 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4315 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4316 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4317
4318 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4319 if (rval)
4320 return rval;
4321
4322 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4323 return QLA_SUCCESS;
4324 } else {
4325 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4326 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4327 data);
4328 if (rval)
4329 return rval;
4330
4331 msleep(200);
4332
4333 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4334 &data);
4335 if (rval)
4336 return rval;
4337
4338 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4339 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4340 ~(idc_lck_rcvry_stage_mask));
4341 rval = qla83xx_wr_reg(base_vha,
4342 QLA83XX_IDC_LOCK_RECOVERY, data);
4343 if (rval)
4344 return rval;
4345
4346 /* Forcefully perform IDC UnLock */
4347 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4348 &data);
4349 if (rval)
4350 return rval;
4351 /* Clear lock-id by setting 0xff */
4352 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4353 0xff);
4354 if (rval)
4355 return rval;
4356 /* Clear lock-recovery by setting 0x0 */
4357 rval = qla83xx_wr_reg(base_vha,
4358 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4359 if (rval)
4360 return rval;
4361 } else
4362 return QLA_SUCCESS;
4363 }
4364
4365 return rval;
4366}
4367
fa492630 4368static int
7d613ac6
SV		 4369qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4370{
4371 int rval = QLA_SUCCESS;
4372 uint32_t o_drv_lockid, n_drv_lockid;
4373 unsigned long lock_recovery_timeout;
4374
4375 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4376retry_lockid:
4377 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4378 if (rval)
4379 goto exit;
4380
4381 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4382 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4383 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4384 return QLA_SUCCESS;
4385 else
4386 return QLA_FUNCTION_FAILED;
4387 }
4388
4389 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4390 if (rval)
4391 goto exit;
4392
4393 if (o_drv_lockid == n_drv_lockid) {
4394 qla83xx_wait_logic();
4395 goto retry_lockid;
4396 } else
4397 return QLA_SUCCESS;
4398
4399exit:
4400 return rval;
4401}
4402
4403void
4404qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4405{
4406 uint16_t options = (requester_id << 15) | BIT_6;
4407 uint32_t data;
6c315553 4408 uint32_t lock_owner;
7d613ac6
SV		 4409 struct qla_hw_data *ha = base_vha->hw;
4410
4411 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4412retry_lock:
4413 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4414 == QLA_SUCCESS) {
4415 if (data) {
4416 /* Setting lock-id to our function-number */
4417 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4418 ha->portnum);
4419 } else {
6c315553
SK		 4420 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4421 &lock_owner);
7d613ac6 4422 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4423 "Failed to acquire IDC lock, acquired by %d, "
4424 "retrying...\n", lock_owner);
7d613ac6
SV		 4425
4426 /* Retry/Perform IDC-Lock recovery */
4427 if (qla83xx_idc_lock_recovery(base_vha)
4428 == QLA_SUCCESS) {
4429 qla83xx_wait_logic();
4430 goto retry_lock;
4431 } else
4432 ql_log(ql_log_warn, base_vha, 0xb075,
4433 "IDC Lock recovery FAILED.\n");
4434 }
4435
4436 }
4437
4438 return;
4439
4440 /* XXX: IDC-lock implementation using access-control mbx */
4441retry_lock2:
4442 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4443 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4444 "Failed to acquire IDC lock. retrying...\n");
4445 /* Retry/Perform IDC-Lock recovery */
4446 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4447 qla83xx_wait_logic();
4448 goto retry_lock2;
4449 } else
4450 ql_log(ql_log_warn, base_vha, 0xb076,
4451 "IDC Lock recovery FAILED.\n");
4452 }
4453
4454 return;
4455}
4456
4457void
4458qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4459{
4460 uint16_t options = (requester_id << 15) | BIT_7, retry;
4461 uint32_t data;
4462 struct qla_hw_data *ha = base_vha->hw;
4463
4464 /* IDC-unlock implementation using driver-unlock/lock-id
4465 * remote registers
4466 */
4467 retry = 0;
4468retry_unlock:
4469 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4470 == QLA_SUCCESS) {
4471 if (data == ha->portnum) {
4472 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4473 /* Clearing lock-id by setting 0xff */
4474 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4475 } else if (retry < 10) {
4476 /* SV: XXX: IDC unlock retrying needed here? */
4477
4478 /* Retry for IDC-unlock */
4479 qla83xx_wait_logic();
4480 retry++;
4481 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4482 "Failed to release IDC lock, retyring=%d\n", retry);
4483 goto retry_unlock;
4484 }
4485 } else if (retry < 10) {
4486 /* Retry for IDC-unlock */
4487 qla83xx_wait_logic();
4488 retry++;
4489 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4490 "Failed to read drv-lockid, retyring=%d\n", retry);
4491 goto retry_unlock;
4492 }
4493
4494 return;
4495
4496 /* XXX: IDC-unlock implementation using access-control mbx */
4497 retry = 0;
4498retry_unlock2:
4499 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4500 if (retry < 10) {
4501 /* Retry for IDC-unlock */
4502 qla83xx_wait_logic();
4503 retry++;
4504 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4505 "Failed to release IDC lock, retyring=%d\n", retry);
4506 goto retry_unlock2;
4507 }
4508 }
4509
4510 return;
4511}
4512
4513int
4514__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4515{
4516 int rval = QLA_SUCCESS;
4517 struct qla_hw_data *ha = vha->hw;
4518 uint32_t drv_presence;
4519
4520 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4521 if (rval == QLA_SUCCESS) {
4522 drv_presence |= (1 << ha->portnum);
4523 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4524 drv_presence);
4525 }
4526
4527 return rval;
4528}
4529
4530int
4531qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4532{
4533 int rval = QLA_SUCCESS;
4534
4535 qla83xx_idc_lock(vha, 0);
4536 rval = __qla83xx_set_drv_presence(vha);
4537 qla83xx_idc_unlock(vha, 0);
4538
4539 return rval;
4540}
4541
4542int
4543__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4544{
4545 int rval = QLA_SUCCESS;
4546 struct qla_hw_data *ha = vha->hw;
4547 uint32_t drv_presence;
4548
4549 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4550 if (rval == QLA_SUCCESS) {
4551 drv_presence &= ~(1 << ha->portnum);
4552 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4553 drv_presence);
4554 }
4555
4556 return rval;
4557}
4558
4559int
4560qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4561{
4562 int rval = QLA_SUCCESS;
4563
4564 qla83xx_idc_lock(vha, 0);
4565 rval = __qla83xx_clear_drv_presence(vha);
4566 qla83xx_idc_unlock(vha, 0);
4567
4568 return rval;
4569}
4570
fa492630 4571static void
7d613ac6
SV		 4572qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4573{
4574 struct qla_hw_data *ha = vha->hw;
4575 uint32_t drv_ack, drv_presence;
4576 unsigned long ack_timeout;
4577
4578 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4579 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4580 while (1) {
4581 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4582 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4583 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4584 break;
4585
4586 if (time_after_eq(jiffies, ack_timeout)) {
4587 ql_log(ql_log_warn, vha, 0xb067,
4588 "RESET ACK TIMEOUT! drv_presence=0x%x "
4589 "drv_ack=0x%x\n", drv_presence, drv_ack);
4590 /*
4591 * The function(s) which did not ack in time are forced
4592 * to withdraw any further participation in the IDC
4593 * reset.
4594 */
4595 if (drv_ack != drv_presence)
4596 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4597 drv_ack);
4598 break;
4599 }
4600
4601 qla83xx_idc_unlock(vha, 0);
4602 msleep(1000);
4603 qla83xx_idc_lock(vha, 0);
4604 }
4605
4606 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4607 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4608}
4609
fa492630 4610static int
7d613ac6
SV		 4611qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4612{
4613 int rval = QLA_SUCCESS;
4614 uint32_t idc_control;
4615
4616 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4617 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4618
4619 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4620 __qla83xx_get_idc_control(vha, &idc_control);
4621 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4622 __qla83xx_set_idc_control(vha, 0);
4623
4624 qla83xx_idc_unlock(vha, 0);
4625 rval = qla83xx_restart_nic_firmware(vha);
4626 qla83xx_idc_lock(vha, 0);
4627
4628 if (rval != QLA_SUCCESS) {
4629 ql_log(ql_log_fatal, vha, 0xb06a,
4630 "Failed to restart NIC f/w.\n");
4631 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4632 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4633 } else {
4634 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4635 "Success in restarting nic f/w.\n");
4636 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4637 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4638 }
4639
4640 return rval;
4641}
4642
4643/* Assumes idc_lock always held on entry */
4644int
4645qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4646{
4647 struct qla_hw_data *ha = base_vha->hw;
4648 int rval = QLA_SUCCESS;
4649 unsigned long dev_init_timeout;
4650 uint32_t dev_state;
4651
4652 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4653 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4654
4655 while (1) {
4656
4657 if (time_after_eq(jiffies, dev_init_timeout)) {
4658 ql_log(ql_log_warn, base_vha, 0xb06e,
4659 "Initialization TIMEOUT!\n");
4660 /* Init timeout. Disable further NIC Core
4661 * communication.
4662 */
4663 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4664 QLA8XXX_DEV_FAILED);
4665 ql_log(ql_log_info, base_vha, 0xb06f,
4666 "HW State: FAILED.\n");
4667 }
4668
4669 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4670 switch (dev_state) {
4671 case QLA8XXX_DEV_READY:
4672 if (ha->flags.nic_core_reset_owner)
4673 qla83xx_idc_audit(base_vha,
4674 IDC_AUDIT_COMPLETION);
4675 ha->flags.nic_core_reset_owner = 0;
4676 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4677 "Reset_owner reset by 0x%x.\n",
4678 ha->portnum);
4679 goto exit;
4680 case QLA8XXX_DEV_COLD:
4681 if (ha->flags.nic_core_reset_owner)
4682 rval = qla83xx_device_bootstrap(base_vha);
4683 else {
4684 /* Wait for AEN to change device-state */
4685 qla83xx_idc_unlock(base_vha, 0);
4686 msleep(1000);
4687 qla83xx_idc_lock(base_vha, 0);
4688 }
4689 break;
4690 case QLA8XXX_DEV_INITIALIZING:
4691 /* Wait for AEN to change device-state */
4692 qla83xx_idc_unlock(base_vha, 0);
4693 msleep(1000);
4694 qla83xx_idc_lock(base_vha, 0);
4695 break;
4696 case QLA8XXX_DEV_NEED_RESET:
4697 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4698 qla83xx_need_reset_handler(base_vha);
4699 else {
4700 /* Wait for AEN to change device-state */
4701 qla83xx_idc_unlock(base_vha, 0);
4702 msleep(1000);
4703 qla83xx_idc_lock(base_vha, 0);
4704 }
4705 /* reset timeout value after need reset handler */
4706 dev_init_timeout = jiffies +
4707 (ha->fcoe_dev_init_timeout * HZ);
4708 break;
4709 case QLA8XXX_DEV_NEED_QUIESCENT:
4710 /* XXX: DEBUG for now */
4711 qla83xx_idc_unlock(base_vha, 0);
4712 msleep(1000);
4713 qla83xx_idc_lock(base_vha, 0);
4714 break;
4715 case QLA8XXX_DEV_QUIESCENT:
4716 /* XXX: DEBUG for now */
4717 if (ha->flags.quiesce_owner)
4718 goto exit;
4719
4720 qla83xx_idc_unlock(base_vha, 0);
4721 msleep(1000);
4722 qla83xx_idc_lock(base_vha, 0);
4723 dev_init_timeout = jiffies +
4724 (ha->fcoe_dev_init_timeout * HZ);
4725 break;
4726 case QLA8XXX_DEV_FAILED:
4727 if (ha->flags.nic_core_reset_owner)
4728 qla83xx_idc_audit(base_vha,
4729 IDC_AUDIT_COMPLETION);
4730 ha->flags.nic_core_reset_owner = 0;
4731 __qla83xx_clear_drv_presence(base_vha);
4732 qla83xx_idc_unlock(base_vha, 0);
4733 qla8xxx_dev_failed_handler(base_vha);
4734 rval = QLA_FUNCTION_FAILED;
4735 qla83xx_idc_lock(base_vha, 0);
4736 goto exit;
4737 case QLA8XXX_BAD_VALUE:
4738 qla83xx_idc_unlock(base_vha, 0);
4739 msleep(1000);
4740 qla83xx_idc_lock(base_vha, 0);
4741 break;
4742 default:
4743 ql_log(ql_log_warn, base_vha, 0xb071,
4744 "Unknow Device State: %x.\n", dev_state);
4745 qla83xx_idc_unlock(base_vha, 0);
4746 qla8xxx_dev_failed_handler(base_vha);
4747 rval = QLA_FUNCTION_FAILED;
4748 qla83xx_idc_lock(base_vha, 0);
4749 goto exit;
4750 }
4751 }
4752
4753exit:
4754 return rval;
4755}
4756
f3ddac19
CD		 4757void
4758qla2x00_disable_board_on_pci_error(struct work_struct *work)
4759{
4760 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4761 board_disable);
4762 struct pci_dev *pdev = ha->pdev;
4763 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4764
4765 ql_log(ql_log_warn, base_vha, 0x015b,
4766 "Disabling adapter.\n");
4767
4768 set_bit(UNLOADING, &base_vha->dpc_flags);
4769
4770 qla2x00_delete_all_vps(ha, base_vha);
4771
4772 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4773
4774 qla2x00_dfs_remove(base_vha);
4775
4776 qla84xx_put_chip(base_vha);
4777
4778 if (base_vha->timer_active)
4779 qla2x00_stop_timer(base_vha);
4780
4781 base_vha->flags.online = 0;
4782
4783 qla2x00_destroy_deferred_work(ha);
4784
4785 /*
4786 * Do not try to stop beacon blink as it will issue a mailbox
4787 * command.
4788 */
4789 qla2x00_free_sysfs_attr(base_vha, false);
4790
4791 fc_remove_host(base_vha->host);
4792
4793 scsi_remove_host(base_vha->host);
4794
4795 base_vha->flags.init_done = 0;
4796 qla25xx_delete_queues(base_vha);
4797 qla2x00_free_irqs(base_vha);
4798 qla2x00_free_fcports(base_vha);
4799 qla2x00_mem_free(ha);
4800 qla82xx_md_free(base_vha);
4801 qla2x00_free_queues(ha);
4802
4803 scsi_host_put(base_vha->host);
4804
4805 qla2x00_unmap_iobases(ha);
4806
4807 pci_release_selected_regions(ha->pdev, ha->bars);
4808 kfree(ha);
4809 ha = NULL;
4810
4811 pci_disable_pcie_error_reporting(pdev);
4812 pci_disable_device(pdev);
4813 pci_set_drvdata(pdev, NULL);
4814
4815}
4816
1da177e4
LT		 4817/**************************************************************************
4818* qla2x00_do_dpc
4819* This kernel thread is a task that is schedule by the interrupt handler
4820* to perform the background processing for interrupts.
4821*
4822* Notes:
4823* This task always run in the context of a kernel thread. It
4824* is kick-off by the driver's detect code and starts up
4825* up one per adapter. It immediately goes to sleep and waits for
4826* some fibre event. When either the interrupt handler or
4827* the timer routine detects a event it will one of the task
4828* bits then wake us up.
4829**************************************************************************/
4830static int
4831qla2x00_do_dpc(void *data)
4832{
2c3dfe3f 4833 int rval;
e315cd28
AC		 4834 scsi_qla_host_t *base_vha;
4835 struct qla_hw_data *ha;
1da177e4 4836
e315cd28
AC		 4837 ha = (struct qla_hw_data *)data;
4838 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4839
8698a745 4840 set_user_nice(current, MIN_NICE);
1da177e4 4841
563585ec 4842 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4843 while (!kthread_should_stop()) {
7c3df132
SK		 4844 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4845 "DPC handler sleeping.\n");
1da177e4 4846
39a11240
CH		 4847 schedule();
4848 __set_current_state(TASK_RUNNING);
1da177e4 4849
c142caf0
AV		 4850 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4851 goto end_loop;
1da177e4 4852
85880801 4853 if (ha->flags.eeh_busy) {
7c3df132
SK		 4854 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4855 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4856 goto end_loop;
85880801
AV		 4857 }
4858
1da177e4
LT		 4859 ha->dpc_active = 1;
4860
5f28d2d7
SK		 4861 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4862 "DPC handler waking up, dpc_flags=0x%lx.\n",
4863 base_vha->dpc_flags);
1da177e4 4864
e315cd28 4865 qla2x00_do_work(base_vha);
0971de7f 4866
7ec0effd
AD		 4867 if (IS_P3P_TYPE(ha)) {
4868 if (IS_QLA8044(ha)) {
4869 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4870 &base_vha->dpc_flags)) {
4871 qla8044_idc_lock(ha);
4872 qla8044_wr_direct(base_vha,
4873 QLA8044_CRB_DEV_STATE_INDEX,
4874 QLA8XXX_DEV_FAILED);
4875 qla8044_idc_unlock(ha);
4876 ql_log(ql_log_info, base_vha, 0x4004,
4877 "HW State: FAILED.\n");
4878 qla8044_device_state_handler(base_vha);
4879 continue;
4880 }
4881
4882 } else {
4883 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4884 &base_vha->dpc_flags)) {
4885 qla82xx_idc_lock(ha);
4886 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4887 QLA8XXX_DEV_FAILED);
4888 qla82xx_idc_unlock(ha);
4889 ql_log(ql_log_info, base_vha, 0x0151,
4890 "HW State: FAILED.\n");
4891 qla82xx_device_state_handler(base_vha);
4892 continue;
4893 }
a9083016
GM		 4894 }
4895
4896 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4897 &base_vha->dpc_flags)) {
4898
7c3df132
SK		 4899 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4900 "FCoE context reset scheduled.\n");
a9083016
GM		 4901 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4902 &base_vha->dpc_flags))) {
4903 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4904 /* FCoE-ctx reset failed.
4905 * Escalate to chip-reset
4906 */
4907 set_bit(ISP_ABORT_NEEDED,
4908 &base_vha->dpc_flags);
4909 }
4910 clear_bit(ABORT_ISP_ACTIVE,
4911 &base_vha->dpc_flags);
4912 }
4913
7c3df132
SK		 4914 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4915 "FCoE context reset end.\n");
a9083016 4916 }
8ae6d9c7
GM		 4917 } else if (IS_QLAFX00(ha)) {
4918 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4919 &base_vha->dpc_flags)) {
4920 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4921 "Firmware Reset Recovery\n");
4922 if (qlafx00_reset_initialize(base_vha)) {
4923 /* Failed. Abort isp later. */
4924 if (!test_bit(UNLOADING,
f92f82d6 4925 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 4926 set_bit(ISP_UNRECOVERABLE,
4927 &base_vha->dpc_flags);
4928 ql_dbg(ql_dbg_dpc, base_vha,
4929 0x4021,
4930 "Reset Recovery Failed\n");
f92f82d6 4931 }
8ae6d9c7
GM		 4932 }
4933 }
4934
4935 if (test_and_clear_bit(FX00_TARGET_SCAN,
4936 &base_vha->dpc_flags)) {
4937 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4938 "ISPFx00 Target Scan scheduled\n");
4939 if (qlafx00_rescan_isp(base_vha)) {
4940 if (!test_bit(UNLOADING,
4941 &base_vha->dpc_flags))
4942 set_bit(ISP_UNRECOVERABLE,
4943 &base_vha->dpc_flags);
4944 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4945 "ISPFx00 Target Scan Failed\n");
4946 }
4947 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4948 "ISPFx00 Target Scan End\n");
4949 }
e8f5e95d
AB		 4950 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4951 &base_vha->dpc_flags)) {
4952 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4953 "ISPFx00 Host Info resend scheduled\n");
4954 qlafx00_fx_disc(base_vha,
4955 &base_vha->hw->mr.fcport,
4956 FXDISC_REG_HOST_INFO);
4957 }
a9083016
GM		 4958 }
4959
e315cd28
AC		 4960 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4961 &base_vha->dpc_flags)) {
1da177e4 4962
7c3df132
SK		 4963 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4964 "ISP abort scheduled.\n");
1da177e4 4965 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4966 &base_vha->dpc_flags))) {
1da177e4 4967
a9083016 4968 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4969 /* failed. retry later */
4970 set_bit(ISP_ABORT_NEEDED,
e315cd28 4971 &base_vha->dpc_flags);
99363ef8 4972 }
e315cd28
AC		 4973 clear_bit(ABORT_ISP_ACTIVE,
4974 &base_vha->dpc_flags);
99363ef8
SJ		 4975 }
4976
7c3df132
SK		 4977 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4978 "ISP abort end.\n");
1da177e4
LT		 4979 }
4980
a394aac8
DJ		 4981 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4982 &base_vha->dpc_flags)) {
e315cd28 4983 qla2x00_update_fcports(base_vha);
c9c5ced9 4984 }
d97994dc 4985
2d70c103
NB		 4986 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4987 int ret;
4988 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4989 if (ret != QLA_SUCCESS)
4990 ql_log(ql_log_warn, base_vha, 0x121,
4991 "Failed to enable receiving of RSCN "
4992 "requests: 0x%x.\n", ret);
4993 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4994 }
4995
8ae6d9c7
GM		 4996 if (IS_QLAFX00(ha))
4997 goto loop_resync_check;
4998
579d12b5 4999 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5000 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5001 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5002 if (IS_P3P_TYPE(ha)) {
5003 if (IS_QLA82XX(ha))
5004 qla82xx_device_state_handler(base_vha);
5005 if (IS_QLA8044(ha))
5006 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5007 clear_bit(ISP_QUIESCE_NEEDED,
5008 &base_vha->dpc_flags);
5009 if (!ha->flags.quiesce_owner) {
5010 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5011 if (IS_QLA82XX(ha)) {
5012 qla82xx_idc_lock(ha);
5013 qla82xx_clear_qsnt_ready(
5014 base_vha);
5015 qla82xx_idc_unlock(ha);
5016 } else if (IS_QLA8044(ha)) {
5017 qla8044_idc_lock(ha);
5018 qla8044_clear_qsnt_ready(
5019 base_vha);
5020 qla8044_idc_unlock(ha);
5021 }
8fcd6b8b
CD		 5022 }
5023 } else {
5024 clear_bit(ISP_QUIESCE_NEEDED,
5025 &base_vha->dpc_flags);
5026 qla2x00_quiesce_io(base_vha);
579d12b5 5027 }
7c3df132
SK		 5028 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5029 "Quiescence mode end.\n");
579d12b5
SK		 5030 }
5031
e315cd28 5032 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5033 &base_vha->dpc_flags) &&
e315cd28 5034 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5035
7c3df132
SK		 5036 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5037 "Reset marker scheduled.\n");
e315cd28
AC		 5038 qla2x00_rst_aen(base_vha);
5039 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5040 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5041 "Reset marker end.\n");
1da177e4
LT		 5042 }
5043
5044 /* Retry each device up to login retry count */
e315cd28
AC		 5045 if ((test_and_clear_bit(RELOGIN_NEEDED,
5046 &base_vha->dpc_flags)) &&
5047 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5048 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5049
7c3df132
SK		 5050 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5051 "Relogin scheduled.\n");
e315cd28 5052 qla2x00_relogin(base_vha);
7c3df132
SK		 5053 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5054 "Relogin end.\n");
1da177e4 5055 }
8ae6d9c7 5056loop_resync_check:
e315cd28 5057 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5058 &base_vha->dpc_flags)) {
1da177e4 5059
7c3df132
SK		 5060 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5061 "Loop resync scheduled.\n");
1da177e4
LT		 5062
5063 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5064 &base_vha->dpc_flags))) {
1da177e4 5065
e315cd28 5066 rval = qla2x00_loop_resync(base_vha);
1da177e4 5067
e315cd28
AC		 5068 clear_bit(LOOP_RESYNC_ACTIVE,
5069 &base_vha->dpc_flags);
1da177e4
LT		 5070 }
5071
7c3df132
SK		 5072 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5073 "Loop resync end.\n");
1da177e4
LT		 5074 }
5075
8ae6d9c7
GM		 5076 if (IS_QLAFX00(ha))
5077 goto intr_on_check;
5078
e315cd28
AC		 5079 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5080 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5081 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5082 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5083 }
5084
8ae6d9c7 5085intr_on_check:
1da177e4 5086 if (!ha->interrupts_on)
fd34f556 5087 ha->isp_ops->enable_intrs(ha);
1da177e4 5088
e315cd28 5089 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5090 &base_vha->dpc_flags)) {
5091 if (ha->beacon_blink_led == 1)
5092 ha->isp_ops->beacon_blink(base_vha);
5093 }
f6df144c 5094
8ae6d9c7
GM		 5095 if (!IS_QLAFX00(ha))
5096 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5097
1da177e4 5098 ha->dpc_active = 0;
c142caf0 5099end_loop:
563585ec 5100 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5101 } /* End of while(1) */
563585ec 5102 __set_current_state(TASK_RUNNING);
1da177e4 5103
7c3df132
SK		 5104 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5105 "DPC handler exiting.\n");
1da177e4
LT		 5106
5107 /*
5108 * Make sure that nobody tries to wake us up again.
5109 */
1da177e4
LT		 5110 ha->dpc_active = 0;
5111
ac280b67
AV		 5112 /* Cleanup any residual CTX SRBs. */
5113 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5114
39a11240
CH		 5115 return 0;
5116}
5117
5118void
e315cd28 5119qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5120{
e315cd28 5121 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5122 struct task_struct *t = ha->dpc_thread;
5123
e315cd28 5124 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5125 wake_up_process(t);
1da177e4
LT		 5126}
5127
1da177e4
LT		 5128/*
5129* qla2x00_rst_aen
5130* Processes asynchronous reset.
5131*
5132* Input:
5133* ha = adapter block pointer.
5134*/
5135static void
e315cd28 5136qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5137{
e315cd28
AC		 5138 if (vha->flags.online && !vha->flags.reset_active &&
5139 !atomic_read(&vha->loop_down_timer) &&
5140 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5141 do {
e315cd28 5142 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5143
5144 /*
5145 * Issue marker command only when we are going to start
5146 * the I/O.
5147 */
e315cd28
AC		 5148 vha->marker_needed = 1;
5149 } while (!atomic_read(&vha->loop_down_timer) &&
5150 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5151 }
5152}
5153
1da177e4
LT		 5154/**************************************************************************
5155* qla2x00_timer
5156*
5157* Description:
5158* One second timer
5159*
5160* Context: Interrupt
5161***************************************************************************/
2c3dfe3f 5162void
e315cd28 5163qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5164{
1da177e4 5165 unsigned long cpu_flags = 0;
1da177e4
LT		 5166 int start_dpc = 0;
5167 int index;
5168 srb_t *sp;
85880801 5169 uint16_t w;
e315cd28 5170 struct qla_hw_data *ha = vha->hw;
73208dfd 5171 struct req_que *req;
85880801 5172
a5b36321 5173 if (ha->flags.eeh_busy) {
7c3df132
SK		 5174 ql_dbg(ql_dbg_timer, vha, 0x6000,
5175 "EEH = %d, restarting timer.\n",
5176 ha->flags.eeh_busy);
a5b36321
LC		 5177 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5178 return;
5179 }
5180
f3ddac19
CD		 5181 /*
5182 * Hardware read to raise pending EEH errors during mailbox waits. If
5183 * the read returns -1 then disable the board.
5184 */
5185 if (!pci_channel_offline(ha->pdev)) {
85880801 5186 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
f3ddac19
CD		 5187 if (w == 0xffff)
5188 /*
5189 * Schedule this on the default system workqueue so that
5190 * all the adapter workqueues and the DPC thread can be
5191 * shutdown cleanly.
5192 */
5193 schedule_work(&ha->board_disable);
5194 }
1da177e4 5195
cefcaba6 5196 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5197 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5198 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5199 start_dpc++;
7ec0effd
AD		 5200 if (IS_QLA82XX(ha))
5201 qla82xx_watchdog(vha);
5202 else if (IS_QLA8044(ha))
5203 qla8044_watchdog(vha);
579d12b5
SK		 5204 }
5205
8ae6d9c7
GM		 5206 if (!vha->vp_idx && IS_QLAFX00(ha))
5207 qlafx00_timer_routine(vha);
5208
1da177e4 5209 /* Loop down handler. */
e315cd28 5210 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5211 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5212 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5213 && vha->flags.online) {
1da177e4 5214
e315cd28
AC		 5215 if (atomic_read(&vha->loop_down_timer) ==
5216 vha->loop_down_abort_time) {
1da177e4 5217
7c3df132
SK		 5218 ql_log(ql_log_info, vha, 0x6008,
5219 "Loop down - aborting the queues before time expires.\n");
1da177e4 5220
e315cd28
AC		 5221 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5222 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5223
f08b7251
AV		 5224 /*
5225 * Schedule an ISP abort to return any FCP2-device
5226 * commands.
5227 */
2c3dfe3f 5228 /* NPIV - scan physical port only */
e315cd28 5229 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5230 spin_lock_irqsave(&ha->hardware_lock,
5231 cpu_flags);
73208dfd 5232 req = ha->req_q_map[0];
2c3dfe3f 5233 for (index = 1;
8d93f550 5234 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5235 index++) {
5236 fc_port_t *sfcp;
5237
e315cd28 5238 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5239 if (!sp)
5240 continue;
9ba56b95 5241 if (sp->type != SRB_SCSI_CMD)
cf53b069 5242 continue;
2c3dfe3f 5243 sfcp = sp->fcport;
f08b7251 5244 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5245 continue;
bdf79621 5246
8f7daead
GM		 5247 if (IS_QLA82XX(ha))
5248 set_bit(FCOE_CTX_RESET_NEEDED,
5249 &vha->dpc_flags);
5250 else
5251 set_bit(ISP_ABORT_NEEDED,
e315cd28 5252 &vha->dpc_flags);
2c3dfe3f
SJ		 5253 break;
5254 }
5255 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5256 cpu_flags);
1da177e4 5257 }
1da177e4
LT		 5258 start_dpc++;
5259 }
5260
5261 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5262 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5263 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5264 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5265 "Loop down - aborting ISP.\n");
5266
8f7daead
GM		 5267 if (IS_QLA82XX(ha))
5268 set_bit(FCOE_CTX_RESET_NEEDED,
5269 &vha->dpc_flags);
5270 else
5271 set_bit(ISP_ABORT_NEEDED,
5272 &vha->dpc_flags);
1da177e4
LT		 5273 }
5274 }
7c3df132
SK		 5275 ql_dbg(ql_dbg_timer, vha, 0x600a,
5276 "Loop down - seconds remaining %d.\n",
5277 atomic_read(&vha->loop_down_timer));
1da177e4 5278 }
cefcaba6
SK		 5279 /* Check if beacon LED needs to be blinked for physical host only */
5280 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5281 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5282 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5283 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5284 start_dpc++;
5285 }
f6df144c 5286 }
5287
550bf57d 5288 /* Process any deferred work. */
e315cd28 5289 if (!list_empty(&vha->work_list))
550bf57d
AV		 5290 start_dpc++;
5291
1da177e4 5292 /* Schedule the DPC routine if needed */
e315cd28
AC		 5293 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5294 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5295 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5296 start_dpc ||
e315cd28
AC		 5297 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5298 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5299 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5300 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5301 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5302 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5303 ql_dbg(ql_dbg_timer, vha, 0x600b,
5304 "isp_abort_needed=%d loop_resync_needed=%d "
5305 "fcport_update_needed=%d start_dpc=%d "
5306 "reset_marker_needed=%d",
5307 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5308 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5309 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5310 start_dpc,
5311 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5312 ql_dbg(ql_dbg_timer, vha, 0x600c,
5313 "beacon_blink_needed=%d isp_unrecoverable=%d "
5314 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5315 "relogin_needed=%d.\n",
7c3df132
SK		 5316 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5317 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5318 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5319 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5320 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5321 qla2xxx_wake_dpc(vha);
7c3df132 5322 }
1da177e4 5323
e315cd28 5324 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5325}
5326
5433383e
AV		 5327/* Firmware interface routines. */
5328
f73cb695 5329#define FW_BLOBS 11
5433383e
AV		 5330#define FW_ISP21XX 0
5331#define FW_ISP22XX 1
5332#define FW_ISP2300 2
5333#define FW_ISP2322 3
48c02fde 5334#define FW_ISP24XX 4
c3a2f0df 5335#define FW_ISP25XX 5
3a03eb79 5336#define FW_ISP81XX 6
a9083016 5337#define FW_ISP82XX 7
6246b8a1
GM		 5338#define FW_ISP2031 8
5339#define FW_ISP8031 9
2c5bbbb2 5340#define FW_ISP27XX 10
5433383e 5341
bb8ee499
AV		 5342#define FW_FILE_ISP21XX "ql2100_fw.bin"
5343#define FW_FILE_ISP22XX "ql2200_fw.bin"
5344#define FW_FILE_ISP2300 "ql2300_fw.bin"
5345#define FW_FILE_ISP2322 "ql2322_fw.bin"
5346#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5347#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5348#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5349#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5350#define FW_FILE_ISP2031 "ql2600_fw.bin"
5351#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5352#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5353
bb8ee499 5354
e1e82b6f 5355static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5356
5357static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5358 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5359 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5360 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5361 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5362 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5363 { .name = FW_FILE_ISP25XX, },
3a03eb79 5364 { .name = FW_FILE_ISP81XX, },
a9083016 5365 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5366 { .name = FW_FILE_ISP2031, },
5367 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5368 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5369};
5370
5371struct fw_blob *
e315cd28 5372qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5373{
e315cd28 5374 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5375 struct fw_blob *blob;
5376
5433383e
AV		 5377 if (IS_QLA2100(ha)) {
5378 blob = &qla_fw_blobs[FW_ISP21XX];
5379 } else if (IS_QLA2200(ha)) {
5380 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5381 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5382 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5383 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5384 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5385 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5386 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5387 } else if (IS_QLA25XX(ha)) {
5388 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5389 } else if (IS_QLA81XX(ha)) {
5390 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5391 } else if (IS_QLA82XX(ha)) {
5392 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5393 } else if (IS_QLA2031(ha)) {
5394 blob = &qla_fw_blobs[FW_ISP2031];
5395 } else if (IS_QLA8031(ha)) {
5396 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5397 } else if (IS_QLA27XX(ha)) {
5398 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5399 } else {
5400 return NULL;
5433383e
AV		 5401 }
5402
e1e82b6f 5403 mutex_lock(&qla_fw_lock);
5433383e
AV		 5404 if (blob->fw)
5405 goto out;
5406
5407 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5408 ql_log(ql_log_warn, vha, 0x0063,
5409 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5410 blob->fw = NULL;
5411 blob = NULL;
5412 goto out;
5413 }
5414
5415out:
e1e82b6f 5416 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5417 return blob;
5418}
5419
5420static void
5421qla2x00_release_firmware(void)
5422{
5423 int idx;
5424
e1e82b6f 5425 mutex_lock(&qla_fw_lock);
5433383e 5426 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5427 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5428 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5429}
5430
14e660e6
SJ		 5431static pci_ers_result_t
5432qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5433{
85880801
AV		 5434 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5435 struct qla_hw_data *ha = vha->hw;
5436
7c3df132
SK		 5437 ql_dbg(ql_dbg_aer, vha, 0x9000,
5438 "PCI error detected, state %x.\n", state);
b9b12f73 5439
14e660e6
SJ		 5440 switch (state) {
5441 case pci_channel_io_normal:
85880801 5442 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5443 return PCI_ERS_RESULT_CAN_RECOVER;
5444 case pci_channel_io_frozen:
85880801 5445 ha->flags.eeh_busy = 1;
a5b36321
LC		 5446 /* For ISP82XX complete any pending mailbox cmd */
5447 if (IS_QLA82XX(ha)) {
7190575f 5448 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5449 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5450 qla82xx_clear_pending_mbx(vha);
a5b36321 5451 }
90a86fc0 5452 qla2x00_free_irqs(vha);
14e660e6 5453 pci_disable_device(pdev);
bddd2d65
LC		 5454 /* Return back all IOs */
5455 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5456 return PCI_ERS_RESULT_NEED_RESET;
5457 case pci_channel_io_perm_failure:
85880801
AV		 5458 ha->flags.pci_channel_io_perm_failure = 1;
5459 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5460 return PCI_ERS_RESULT_DISCONNECT;
5461 }
5462 return PCI_ERS_RESULT_NEED_RESET;
5463}
5464
5465static pci_ers_result_t
5466qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5467{
5468 int risc_paused = 0;
5469 uint32_t stat;
5470 unsigned long flags;
e315cd28
AC		 5471 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5472 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5473 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5474 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5475
bcc5b6d3
SK		 5476 if (IS_QLA82XX(ha))
5477 return PCI_ERS_RESULT_RECOVERED;
5478
14e660e6
SJ		 5479 spin_lock_irqsave(&ha->hardware_lock, flags);
5480 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5481 stat = RD_REG_DWORD(&reg->hccr);
5482 if (stat & HCCR_RISC_PAUSE)
5483 risc_paused = 1;
5484 } else if (IS_QLA23XX(ha)) {
5485 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5486 if (stat & HSR_RISC_PAUSED)
5487 risc_paused = 1;
5488 } else if (IS_FWI2_CAPABLE(ha)) {
5489 stat = RD_REG_DWORD(&reg24->host_status);
5490 if (stat & HSRX_RISC_PAUSED)
5491 risc_paused = 1;
5492 }
5493 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5494
5495 if (risc_paused) {
7c3df132
SK		 5496 ql_log(ql_log_info, base_vha, 0x9003,
5497 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5498 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5499
5500 return PCI_ERS_RESULT_NEED_RESET;
5501 } else
5502 return PCI_ERS_RESULT_RECOVERED;
5503}
5504
fa492630
SK		 5505static uint32_t
5506qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5507{
5508 uint32_t rval = QLA_FUNCTION_FAILED;
5509 uint32_t drv_active = 0;
5510 struct qla_hw_data *ha = base_vha->hw;
5511 int fn;
5512 struct pci_dev *other_pdev = NULL;
5513
7c3df132
SK		 5514 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5515 "Entered %s.\n", __func__);
a5b36321
LC		 5516
5517 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5518
5519 if (base_vha->flags.online) {
5520 /* Abort all outstanding commands,
5521 * so as to be requeued later */
5522 qla2x00_abort_isp_cleanup(base_vha);
5523 }
5524
5525
5526 fn = PCI_FUNC(ha->pdev->devfn);
5527 while (fn > 0) {
5528 fn--;
7c3df132
SK		 5529 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5530 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5531 other_pdev =
5532 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5533 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5534 fn));
5535
5536 if (!other_pdev)
5537 continue;
5538 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5539 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5540 "Found PCI func available and enable at 0x%x.\n",
5541 fn);
a5b36321
LC		 5542 pci_dev_put(other_pdev);
5543 break;
5544 }
5545 pci_dev_put(other_pdev);
5546 }
5547
5548 if (!fn) {
5549 /* Reset owner */
7c3df132
SK		 5550 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5551 "This devfn is reset owner = 0x%x.\n",
5552 ha->pdev->devfn);
a5b36321
LC		 5553 qla82xx_idc_lock(ha);
5554
5555 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5556 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5557
5558 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5559 QLA82XX_IDC_VERSION);
5560
5561 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5562 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5563 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5564
5565 qla82xx_idc_unlock(ha);
5566 /* Reset if device is not already reset
5567 * drv_active would be 0 if a reset has already been done
5568 */
5569 if (drv_active)
5570 rval = qla82xx_start_firmware(base_vha);
5571 else
5572 rval = QLA_SUCCESS;
5573 qla82xx_idc_lock(ha);
5574
5575 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5576 ql_log(ql_log_info, base_vha, 0x900b,
5577 "HW State: FAILED.\n");
a5b36321
LC		 5578 qla82xx_clear_drv_active(ha);
5579 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5580 QLA8XXX_DEV_FAILED);
a5b36321 5581 } else {
7c3df132
SK		 5582 ql_log(ql_log_info, base_vha, 0x900c,
5583 "HW State: READY.\n");
a5b36321 5584 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5585 QLA8XXX_DEV_READY);
a5b36321 5586 qla82xx_idc_unlock(ha);
7190575f 5587 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5588 rval = qla82xx_restart_isp(base_vha);
5589 qla82xx_idc_lock(ha);
5590 /* Clear driver state register */
5591 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5592 qla82xx_set_drv_active(base_vha);
5593 }
5594 qla82xx_idc_unlock(ha);
5595 } else {
7c3df132
SK		 5596 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5597 "This devfn is not reset owner = 0x%x.\n",
5598 ha->pdev->devfn);
a5b36321 5599 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5600 QLA8XXX_DEV_READY)) {
7190575f 5601 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5602 rval = qla82xx_restart_isp(base_vha);
5603 qla82xx_idc_lock(ha);
5604 qla82xx_set_drv_active(base_vha);
5605 qla82xx_idc_unlock(ha);
5606 }
5607 }
5608 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5609
5610 return rval;
5611}
5612
14e660e6
SJ		 5613static pci_ers_result_t
5614qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5615{
5616 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5617 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5618 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5619 struct rsp_que *rsp;
5620 int rc, retries = 10;
09483916 5621
7c3df132
SK		 5622 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5623 "Slot Reset.\n");
85880801 5624
90a86fc0
JC		 5625 /* Workaround: qla2xxx driver which access hardware earlier
5626 * needs error state to be pci_channel_io_online.
5627 * Otherwise mailbox command timesout.
5628 */
5629 pdev->error_state = pci_channel_io_normal;
5630
5631 pci_restore_state(pdev);
5632
8c1496bd
RL		 5633 /* pci_restore_state() clears the saved_state flag of the device
5634 * save restored state which resets saved_state flag
5635 */
5636 pci_save_state(pdev);
5637
09483916
BH		 5638 if (ha->mem_only)
5639 rc = pci_enable_device_mem(pdev);
5640 else
5641 rc = pci_enable_device(pdev);
14e660e6 5642
09483916 5643 if (rc) {
7c3df132 5644 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5645 "Can't re-enable PCI device after reset.\n");
a5b36321 5646 goto exit_slot_reset;
14e660e6 5647 }
14e660e6 5648
90a86fc0
JC		 5649 rsp = ha->rsp_q_map[0];
5650 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5651 goto exit_slot_reset;
90a86fc0 5652
e315cd28 5653 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5654 goto exit_slot_reset;
5655
5656 if (IS_QLA82XX(ha)) {
5657 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5658 ret = PCI_ERS_RESULT_RECOVERED;
5659 goto exit_slot_reset;
5660 } else
5661 goto exit_slot_reset;
5662 }
14e660e6 5663
90a86fc0
JC		 5664 while (ha->flags.mbox_busy && retries--)
5665 msleep(1000);
85880801 5666
e315cd28 5667 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5668 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5669 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5670 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5671
90a86fc0 5672
a5b36321 5673exit_slot_reset:
7c3df132
SK		 5674 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5675 "slot_reset return %x.\n", ret);
85880801 5676
14e660e6
SJ		 5677 return ret;
5678}
5679
5680static void
5681qla2xxx_pci_resume(struct pci_dev *pdev)
5682{
e315cd28
AC		 5683 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5684 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5685 int ret;
5686
7c3df132
SK		 5687 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5688 "pci_resume.\n");
85880801 5689
e315cd28 5690 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5691 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5692 ql_log(ql_log_fatal, base_vha, 0x9002,
5693 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5694 }
85880801 5695
3e46f031
LC		 5696 pci_cleanup_aer_uncorrect_error_status(pdev);
5697
85880801 5698 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5699}
5700
a55b2d21 5701static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5702 .error_detected = qla2xxx_pci_error_detected,
5703 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5704 .slot_reset = qla2xxx_pci_slot_reset,
5705 .resume = qla2xxx_pci_resume,
5706};
5707
5433383e 5708static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5709 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5710 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5711 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5712 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5713 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5714 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5715 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5716 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5717 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5718 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5719 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5720 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5721 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5722 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5723 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5724 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5725 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5726 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 5727 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 5728 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 5729 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
5433383e
AV		 5730 { 0 },
5731};
5732MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5733
fca29703 5734static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5735 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5736 .driver = {
5737 .owner = THIS_MODULE,
5738 },
fca29703 5739 .id_table = qla2xxx_pci_tbl,
7ee61397 5740 .probe = qla2x00_probe_one,
4c993f76 5741 .remove = qla2x00_remove_one,
e30d1756 5742 .shutdown = qla2x00_shutdown,
14e660e6 5743 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5744};
5745
75ef9de1 5746static const struct file_operations apidev_fops = {
6a03b4cd 5747 .owner = THIS_MODULE,
6038f373 5748 .llseek = noop_llseek,
6a03b4cd
HZ		 5749};
5750
1da177e4
LT		 5751/**
5752 * qla2x00_module_init - Module initialization.
5753 **/
5754static int __init
5755qla2x00_module_init(void)
5756{
fca29703
AV		 5757 int ret = 0;
5758
1da177e4 5759 /* Allocate cache for SRBs. */
354d6b21 5760 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5761 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5762 if (srb_cachep == NULL) {
7c3df132
SK		 5763 ql_log(ql_log_fatal, NULL, 0x0001,
5764 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5765 return -ENOMEM;
5766 }
5767
2d70c103
NB		 5768 /* Initialize target kmem_cache and mem_pools */
5769 ret = qlt_init();
5770 if (ret < 0) {
5771 kmem_cache_destroy(srb_cachep);
5772 return ret;
5773 } else if (ret > 0) {
5774 /*
5775 * If initiator mode is explictly disabled by qlt_init(),
5776 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5777 * performing scsi_scan_target() during LOOP UP event.
5778 */
5779 qla2xxx_transport_functions.disable_target_scan = 1;
5780 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5781 }
5782
1da177e4
LT		 5783 /* Derive version string. */
5784 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5785 if (ql2xextended_error_logging)
0181944f
AV		 5786 strcat(qla2x00_version_str, "-debug");
5787
1c97a12a
AV		 5788 qla2xxx_transport_template =
5789 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5790 if (!qla2xxx_transport_template) {
5791 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5792 ql_log(ql_log_fatal, NULL, 0x0002,
5793 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5794 qlt_exit();
1da177e4 5795 return -ENODEV;
2c3dfe3f 5796 }
6a03b4cd
HZ		 5797
5798 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5799 if (apidev_major < 0) {
7c3df132
SK		 5800 ql_log(ql_log_fatal, NULL, 0x0003,
5801 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5802 }
5803
2c3dfe3f
SJ		 5804 qla2xxx_transport_vport_template =
5805 fc_attach_transport(&qla2xxx_transport_vport_functions);
5806 if (!qla2xxx_transport_vport_template) {
5807 kmem_cache_destroy(srb_cachep);
2d70c103 5808 qlt_exit();
2c3dfe3f 5809 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5810 ql_log(ql_log_fatal, NULL, 0x0004,
5811 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5812 return -ENODEV;
2c3dfe3f 5813 }
7c3df132
SK		 5814 ql_log(ql_log_info, NULL, 0x0005,
5815 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5816 qla2x00_version_str);
7ee61397 5817 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5818 if (ret) {
5819 kmem_cache_destroy(srb_cachep);
2d70c103 5820 qlt_exit();
fca29703 5821 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5822 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5823 ql_log(ql_log_fatal, NULL, 0x0006,
5824 "pci_register_driver failed...ret=%d Failing load!.\n",
5825 ret);
fca29703
AV		 5826 }
5827 return ret;
1da177e4
LT		 5828}
5829
5830/**
5831 * qla2x00_module_exit - Module cleanup.
5832 **/
5833static void __exit
5834qla2x00_module_exit(void)
5835{
6a03b4cd 5836 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5837 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5838 qla2x00_release_firmware();
354d6b21 5839 kmem_cache_destroy(srb_cachep);
2d70c103 5840 qlt_exit();
a9083016
GM		 5841 if (ctx_cachep)
5842 kmem_cache_destroy(ctx_cachep);
1da177e4 5843 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5844 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5845}
5846
5847module_init(qla2x00_module_init);
5848module_exit(qla2x00_module_exit);
5849
5850MODULE_AUTHOR("QLogic Corporation");
5851MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5852MODULE_LICENSE("GPL");
5853MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5854MODULE_FIRMWARE(FW_FILE_ISP21XX);
5855MODULE_FIRMWARE(FW_FILE_ISP22XX);
5856MODULE_FIRMWARE(FW_FILE_ISP2300);
5857MODULE_FIRMWARE(FW_FILE_ISP2322);
5858MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5859MODULE_FIRMWARE(FW_FILE_ISP25XX);
Linux 6.x block layer and io_uring tree(s)