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a9083016 GM |
1 | /* |
2 | * QLogic Fibre Channel HBA Driver | |
3 | * Copyright (c) 2003-2008 QLogic Corporation | |
4 | * | |
5 | * See LICENSE.qla2xxx for copyright and licensing details. | |
6 | */ | |
7 | #include "qla_def.h" | |
8 | #include <linux/delay.h> | |
9 | #include <linux/pci.h> | |
10 | ||
11 | #define MASK(n) ((1ULL<<(n))-1) | |
12 | #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ | |
13 | ((addr >> 25) & 0x3ff)) | |
14 | #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ | |
15 | ((addr >> 25) & 0x3ff)) | |
16 | #define MS_WIN(addr) (addr & 0x0ffc0000) | |
17 | #define QLA82XX_PCI_MN_2M (0) | |
18 | #define QLA82XX_PCI_MS_2M (0x80000) | |
19 | #define QLA82XX_PCI_OCM0_2M (0xc0000) | |
20 | #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) | |
21 | #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) | |
22 | ||
23 | /* CRB window related */ | |
24 | #define CRB_BLK(off) ((off >> 20) & 0x3f) | |
25 | #define CRB_SUBBLK(off) ((off >> 16) & 0xf) | |
26 | #define CRB_WINDOW_2M (0x130060) | |
27 | #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) | |
28 | #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ | |
29 | ((off) & 0xf0000)) | |
30 | #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) | |
31 | #define CRB_INDIRECT_2M (0x1e0000UL) | |
32 | ||
33 | static inline void *qla82xx_pci_base_offsetfset(struct qla_hw_data *ha, | |
34 | unsigned long off) | |
35 | { | |
36 | if ((off < ha->first_page_group_end) && | |
37 | (off >= ha->first_page_group_start)) | |
38 | return (void *)(ha->nx_pcibase + off); | |
39 | ||
40 | return NULL; | |
41 | } | |
42 | ||
43 | #define MAX_CRB_XFORM 60 | |
44 | static unsigned long crb_addr_xform[MAX_CRB_XFORM]; | |
45 | int qla82xx_crb_table_initialized; | |
46 | ||
47 | #define qla82xx_crb_addr_transform(name) \ | |
48 | (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ | |
49 | QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) | |
50 | ||
51 | static void qla82xx_crb_addr_transform_setup(void) | |
52 | { | |
53 | qla82xx_crb_addr_transform(XDMA); | |
54 | qla82xx_crb_addr_transform(TIMR); | |
55 | qla82xx_crb_addr_transform(SRE); | |
56 | qla82xx_crb_addr_transform(SQN3); | |
57 | qla82xx_crb_addr_transform(SQN2); | |
58 | qla82xx_crb_addr_transform(SQN1); | |
59 | qla82xx_crb_addr_transform(SQN0); | |
60 | qla82xx_crb_addr_transform(SQS3); | |
61 | qla82xx_crb_addr_transform(SQS2); | |
62 | qla82xx_crb_addr_transform(SQS1); | |
63 | qla82xx_crb_addr_transform(SQS0); | |
64 | qla82xx_crb_addr_transform(RPMX7); | |
65 | qla82xx_crb_addr_transform(RPMX6); | |
66 | qla82xx_crb_addr_transform(RPMX5); | |
67 | qla82xx_crb_addr_transform(RPMX4); | |
68 | qla82xx_crb_addr_transform(RPMX3); | |
69 | qla82xx_crb_addr_transform(RPMX2); | |
70 | qla82xx_crb_addr_transform(RPMX1); | |
71 | qla82xx_crb_addr_transform(RPMX0); | |
72 | qla82xx_crb_addr_transform(ROMUSB); | |
73 | qla82xx_crb_addr_transform(SN); | |
74 | qla82xx_crb_addr_transform(QMN); | |
75 | qla82xx_crb_addr_transform(QMS); | |
76 | qla82xx_crb_addr_transform(PGNI); | |
77 | qla82xx_crb_addr_transform(PGND); | |
78 | qla82xx_crb_addr_transform(PGN3); | |
79 | qla82xx_crb_addr_transform(PGN2); | |
80 | qla82xx_crb_addr_transform(PGN1); | |
81 | qla82xx_crb_addr_transform(PGN0); | |
82 | qla82xx_crb_addr_transform(PGSI); | |
83 | qla82xx_crb_addr_transform(PGSD); | |
84 | qla82xx_crb_addr_transform(PGS3); | |
85 | qla82xx_crb_addr_transform(PGS2); | |
86 | qla82xx_crb_addr_transform(PGS1); | |
87 | qla82xx_crb_addr_transform(PGS0); | |
88 | qla82xx_crb_addr_transform(PS); | |
89 | qla82xx_crb_addr_transform(PH); | |
90 | qla82xx_crb_addr_transform(NIU); | |
91 | qla82xx_crb_addr_transform(I2Q); | |
92 | qla82xx_crb_addr_transform(EG); | |
93 | qla82xx_crb_addr_transform(MN); | |
94 | qla82xx_crb_addr_transform(MS); | |
95 | qla82xx_crb_addr_transform(CAS2); | |
96 | qla82xx_crb_addr_transform(CAS1); | |
97 | qla82xx_crb_addr_transform(CAS0); | |
98 | qla82xx_crb_addr_transform(CAM); | |
99 | qla82xx_crb_addr_transform(C2C1); | |
100 | qla82xx_crb_addr_transform(C2C0); | |
101 | qla82xx_crb_addr_transform(SMB); | |
102 | qla82xx_crb_addr_transform(OCM0); | |
103 | /* | |
104 | * Used only in P3 just define it for P2 also. | |
105 | */ | |
106 | qla82xx_crb_addr_transform(I2C0); | |
107 | ||
108 | qla82xx_crb_table_initialized = 1; | |
109 | } | |
110 | ||
111 | struct crb_128M_2M_block_map crb_128M_2M_map[64] = { | |
112 | {{{0, 0, 0, 0} } }, | |
113 | {{{1, 0x0100000, 0x0102000, 0x120000}, | |
114 | {1, 0x0110000, 0x0120000, 0x130000}, | |
115 | {1, 0x0120000, 0x0122000, 0x124000}, | |
116 | {1, 0x0130000, 0x0132000, 0x126000}, | |
117 | {1, 0x0140000, 0x0142000, 0x128000}, | |
118 | {1, 0x0150000, 0x0152000, 0x12a000}, | |
119 | {1, 0x0160000, 0x0170000, 0x110000}, | |
120 | {1, 0x0170000, 0x0172000, 0x12e000}, | |
121 | {0, 0x0000000, 0x0000000, 0x000000}, | |
122 | {0, 0x0000000, 0x0000000, 0x000000}, | |
123 | {0, 0x0000000, 0x0000000, 0x000000}, | |
124 | {0, 0x0000000, 0x0000000, 0x000000}, | |
125 | {0, 0x0000000, 0x0000000, 0x000000}, | |
126 | {0, 0x0000000, 0x0000000, 0x000000}, | |
127 | {1, 0x01e0000, 0x01e0800, 0x122000}, | |
128 | {0, 0x0000000, 0x0000000, 0x000000} } } , | |
129 | {{{1, 0x0200000, 0x0210000, 0x180000} } }, | |
130 | {{{0, 0, 0, 0} } }, | |
131 | {{{1, 0x0400000, 0x0401000, 0x169000} } }, | |
132 | {{{1, 0x0500000, 0x0510000, 0x140000} } }, | |
133 | {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, | |
134 | {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, | |
135 | {{{1, 0x0800000, 0x0802000, 0x170000}, | |
136 | {0, 0x0000000, 0x0000000, 0x000000}, | |
137 | {0, 0x0000000, 0x0000000, 0x000000}, | |
138 | {0, 0x0000000, 0x0000000, 0x000000}, | |
139 | {0, 0x0000000, 0x0000000, 0x000000}, | |
140 | {0, 0x0000000, 0x0000000, 0x000000}, | |
141 | {0, 0x0000000, 0x0000000, 0x000000}, | |
142 | {0, 0x0000000, 0x0000000, 0x000000}, | |
143 | {0, 0x0000000, 0x0000000, 0x000000}, | |
144 | {0, 0x0000000, 0x0000000, 0x000000}, | |
145 | {0, 0x0000000, 0x0000000, 0x000000}, | |
146 | {0, 0x0000000, 0x0000000, 0x000000}, | |
147 | {0, 0x0000000, 0x0000000, 0x000000}, | |
148 | {0, 0x0000000, 0x0000000, 0x000000}, | |
149 | {0, 0x0000000, 0x0000000, 0x000000}, | |
150 | {1, 0x08f0000, 0x08f2000, 0x172000} } }, | |
151 | {{{1, 0x0900000, 0x0902000, 0x174000}, | |
152 | {0, 0x0000000, 0x0000000, 0x000000}, | |
153 | {0, 0x0000000, 0x0000000, 0x000000}, | |
154 | {0, 0x0000000, 0x0000000, 0x000000}, | |
155 | {0, 0x0000000, 0x0000000, 0x000000}, | |
156 | {0, 0x0000000, 0x0000000, 0x000000}, | |
157 | {0, 0x0000000, 0x0000000, 0x000000}, | |
158 | {0, 0x0000000, 0x0000000, 0x000000}, | |
159 | {0, 0x0000000, 0x0000000, 0x000000}, | |
160 | {0, 0x0000000, 0x0000000, 0x000000}, | |
161 | {0, 0x0000000, 0x0000000, 0x000000}, | |
162 | {0, 0x0000000, 0x0000000, 0x000000}, | |
163 | {0, 0x0000000, 0x0000000, 0x000000}, | |
164 | {0, 0x0000000, 0x0000000, 0x000000}, | |
165 | {0, 0x0000000, 0x0000000, 0x000000}, | |
166 | {1, 0x09f0000, 0x09f2000, 0x176000} } }, | |
167 | {{{0, 0x0a00000, 0x0a02000, 0x178000}, | |
168 | {0, 0x0000000, 0x0000000, 0x000000}, | |
169 | {0, 0x0000000, 0x0000000, 0x000000}, | |
170 | {0, 0x0000000, 0x0000000, 0x000000}, | |
171 | {0, 0x0000000, 0x0000000, 0x000000}, | |
172 | {0, 0x0000000, 0x0000000, 0x000000}, | |
173 | {0, 0x0000000, 0x0000000, 0x000000}, | |
174 | {0, 0x0000000, 0x0000000, 0x000000}, | |
175 | {0, 0x0000000, 0x0000000, 0x000000}, | |
176 | {0, 0x0000000, 0x0000000, 0x000000}, | |
177 | {0, 0x0000000, 0x0000000, 0x000000}, | |
178 | {0, 0x0000000, 0x0000000, 0x000000}, | |
179 | {0, 0x0000000, 0x0000000, 0x000000}, | |
180 | {0, 0x0000000, 0x0000000, 0x000000}, | |
181 | {0, 0x0000000, 0x0000000, 0x000000}, | |
182 | {1, 0x0af0000, 0x0af2000, 0x17a000} } }, | |
183 | {{{0, 0x0b00000, 0x0b02000, 0x17c000}, | |
184 | {0, 0x0000000, 0x0000000, 0x000000}, | |
185 | {0, 0x0000000, 0x0000000, 0x000000}, | |
186 | {0, 0x0000000, 0x0000000, 0x000000}, | |
187 | {0, 0x0000000, 0x0000000, 0x000000}, | |
188 | {0, 0x0000000, 0x0000000, 0x000000}, | |
189 | {0, 0x0000000, 0x0000000, 0x000000}, | |
190 | {0, 0x0000000, 0x0000000, 0x000000}, | |
191 | {0, 0x0000000, 0x0000000, 0x000000}, | |
192 | {0, 0x0000000, 0x0000000, 0x000000}, | |
193 | {0, 0x0000000, 0x0000000, 0x000000}, | |
194 | {0, 0x0000000, 0x0000000, 0x000000}, | |
195 | {0, 0x0000000, 0x0000000, 0x000000}, | |
196 | {0, 0x0000000, 0x0000000, 0x000000}, | |
197 | {0, 0x0000000, 0x0000000, 0x000000}, | |
198 | {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, | |
199 | {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, | |
200 | {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, | |
201 | {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, | |
202 | {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, | |
203 | {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, | |
204 | {{{1, 0x1100000, 0x1101000, 0x160000} } }, | |
205 | {{{1, 0x1200000, 0x1201000, 0x161000} } }, | |
206 | {{{1, 0x1300000, 0x1301000, 0x162000} } }, | |
207 | {{{1, 0x1400000, 0x1401000, 0x163000} } }, | |
208 | {{{1, 0x1500000, 0x1501000, 0x165000} } }, | |
209 | {{{1, 0x1600000, 0x1601000, 0x166000} } }, | |
210 | {{{0, 0, 0, 0} } }, | |
211 | {{{0, 0, 0, 0} } }, | |
212 | {{{0, 0, 0, 0} } }, | |
213 | {{{0, 0, 0, 0} } }, | |
214 | {{{0, 0, 0, 0} } }, | |
215 | {{{0, 0, 0, 0} } }, | |
216 | {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, | |
217 | {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, | |
218 | {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, | |
219 | {{{0} } }, | |
220 | {{{1, 0x2100000, 0x2102000, 0x120000}, | |
221 | {1, 0x2110000, 0x2120000, 0x130000}, | |
222 | {1, 0x2120000, 0x2122000, 0x124000}, | |
223 | {1, 0x2130000, 0x2132000, 0x126000}, | |
224 | {1, 0x2140000, 0x2142000, 0x128000}, | |
225 | {1, 0x2150000, 0x2152000, 0x12a000}, | |
226 | {1, 0x2160000, 0x2170000, 0x110000}, | |
227 | {1, 0x2170000, 0x2172000, 0x12e000}, | |
228 | {0, 0x0000000, 0x0000000, 0x000000}, | |
229 | {0, 0x0000000, 0x0000000, 0x000000}, | |
230 | {0, 0x0000000, 0x0000000, 0x000000}, | |
231 | {0, 0x0000000, 0x0000000, 0x000000}, | |
232 | {0, 0x0000000, 0x0000000, 0x000000}, | |
233 | {0, 0x0000000, 0x0000000, 0x000000}, | |
234 | {0, 0x0000000, 0x0000000, 0x000000}, | |
235 | {0, 0x0000000, 0x0000000, 0x000000} } }, | |
236 | {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, | |
237 | {{{0} } }, | |
238 | {{{0} } }, | |
239 | {{{0} } }, | |
240 | {{{0} } }, | |
241 | {{{0} } }, | |
242 | {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, | |
243 | {{{1, 0x2900000, 0x2901000, 0x16b000} } }, | |
244 | {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, | |
245 | {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, | |
246 | {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, | |
247 | {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, | |
248 | {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, | |
249 | {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, | |
250 | {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, | |
251 | {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, | |
252 | {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, | |
253 | {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, | |
254 | {{{0} } }, | |
255 | {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, | |
256 | {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, | |
257 | {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, | |
258 | {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, | |
259 | {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, | |
260 | {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, | |
261 | {{{0} } }, | |
262 | {{{0} } }, | |
263 | {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, | |
264 | {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, | |
265 | {{{1, 0x3f00000, 0x3f01000, 0x168000} } } | |
266 | }; | |
267 | ||
268 | /* | |
269 | * top 12 bits of crb internal address (hub, agent) | |
270 | */ | |
271 | unsigned qla82xx_crb_hub_agt[64] = { | |
272 | 0, | |
273 | QLA82XX_HW_CRB_HUB_AGT_ADR_PS, | |
274 | QLA82XX_HW_CRB_HUB_AGT_ADR_MN, | |
275 | QLA82XX_HW_CRB_HUB_AGT_ADR_MS, | |
276 | 0, | |
277 | QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, | |
278 | QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, | |
279 | QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, | |
280 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, | |
281 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, | |
282 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, | |
283 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, | |
284 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, | |
285 | QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, | |
286 | QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, | |
287 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, | |
288 | QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, | |
289 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, | |
290 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, | |
291 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, | |
292 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, | |
293 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, | |
294 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, | |
295 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, | |
296 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, | |
297 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, | |
298 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, | |
299 | 0, | |
300 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, | |
301 | QLA82XX_HW_CRB_HUB_AGT_ADR_SN, | |
302 | 0, | |
303 | QLA82XX_HW_CRB_HUB_AGT_ADR_EG, | |
304 | 0, | |
305 | QLA82XX_HW_CRB_HUB_AGT_ADR_PS, | |
306 | QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, | |
307 | 0, | |
308 | 0, | |
309 | 0, | |
310 | 0, | |
311 | 0, | |
312 | QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, | |
313 | 0, | |
314 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, | |
315 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, | |
316 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, | |
317 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, | |
318 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, | |
319 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, | |
320 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, | |
321 | QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, | |
322 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, | |
323 | QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, | |
324 | 0, | |
325 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, | |
326 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, | |
327 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, | |
328 | QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, | |
329 | 0, | |
330 | QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, | |
331 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, | |
332 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, | |
333 | 0, | |
334 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, | |
335 | 0, | |
336 | }; | |
337 | ||
338 | /* | |
339 | * In: 'off' is offset from CRB space in 128M pci map | |
340 | * Out: 'off' is 2M pci map addr | |
341 | * side effect: lock crb window | |
342 | */ | |
343 | static void | |
344 | qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) | |
345 | { | |
346 | u32 win_read; | |
347 | ||
348 | ha->crb_win = CRB_HI(*off); | |
349 | writel(ha->crb_win, | |
350 | (void *)(CRB_WINDOW_2M + ha->nx_pcibase)); | |
351 | ||
352 | /* Read back value to make sure write has gone through before trying | |
353 | * to use it. | |
354 | */ | |
355 | win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); | |
356 | if (win_read != ha->crb_win) { | |
357 | DEBUG2(qla_printk(KERN_INFO, ha, | |
358 | "%s: Written crbwin (0x%x) != Read crbwin (0x%x), " | |
359 | "off=0x%lx\n", __func__, ha->crb_win, win_read, *off)); | |
360 | } | |
361 | *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; | |
362 | } | |
363 | ||
364 | static inline unsigned long | |
365 | qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) | |
366 | { | |
367 | /* See if we are currently pointing to the region we want to use next */ | |
368 | if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { | |
369 | /* No need to change window. PCIX and PCIEregs are in both | |
370 | * regs are in both windows. | |
371 | */ | |
372 | return off; | |
373 | } | |
374 | ||
375 | if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { | |
376 | /* We are in first CRB window */ | |
377 | if (ha->curr_window != 0) | |
378 | WARN_ON(1); | |
379 | return off; | |
380 | } | |
381 | ||
382 | if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { | |
383 | /* We are in second CRB window */ | |
384 | off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; | |
385 | ||
386 | if (ha->curr_window != 1) | |
387 | return off; | |
388 | ||
389 | /* We are in the QM or direct access | |
390 | * register region - do nothing | |
391 | */ | |
392 | if ((off >= QLA82XX_PCI_DIRECT_CRB) && | |
393 | (off < QLA82XX_PCI_CAMQM_MAX)) | |
394 | return off; | |
395 | } | |
396 | /* strange address given */ | |
397 | qla_printk(KERN_WARNING, ha, | |
398 | "%s: Warning: unm_nic_pci_set_crbwindow called with" | |
399 | " an unknown address(%llx)\n", QLA2XXX_DRIVER_NAME, off); | |
400 | return off; | |
401 | } | |
402 | ||
403 | int | |
404 | qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) | |
405 | { | |
406 | unsigned long flags = 0; | |
407 | int rv; | |
408 | ||
409 | rv = qla82xx_pci_get_crb_addr_2M(ha, &off); | |
410 | ||
411 | BUG_ON(rv == -1); | |
412 | ||
413 | if (rv == 1) { | |
414 | write_lock_irqsave(&ha->hw_lock, flags); | |
415 | qla82xx_crb_win_lock(ha); | |
416 | qla82xx_pci_set_crbwindow_2M(ha, &off); | |
417 | } | |
418 | ||
419 | writel(data, (void __iomem *)off); | |
420 | ||
421 | if (rv == 1) { | |
422 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); | |
423 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
424 | } | |
425 | return 0; | |
426 | } | |
427 | ||
428 | int | |
429 | qla82xx_rd_32(struct qla_hw_data *ha, ulong off) | |
430 | { | |
431 | unsigned long flags = 0; | |
432 | int rv; | |
433 | u32 data; | |
434 | ||
435 | rv = qla82xx_pci_get_crb_addr_2M(ha, &off); | |
436 | ||
437 | BUG_ON(rv == -1); | |
438 | ||
439 | if (rv == 1) { | |
440 | write_lock_irqsave(&ha->hw_lock, flags); | |
441 | qla82xx_crb_win_lock(ha); | |
442 | qla82xx_pci_set_crbwindow_2M(ha, &off); | |
443 | } | |
444 | data = RD_REG_DWORD((void __iomem *)off); | |
445 | ||
446 | if (rv == 1) { | |
447 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); | |
448 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
449 | } | |
450 | return data; | |
451 | } | |
452 | ||
453 | #define CRB_WIN_LOCK_TIMEOUT 100000000 | |
454 | int qla82xx_crb_win_lock(struct qla_hw_data *ha) | |
455 | { | |
456 | int done = 0, timeout = 0; | |
457 | ||
458 | while (!done) { | |
459 | /* acquire semaphore3 from PCI HW block */ | |
460 | done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); | |
461 | if (done == 1) | |
462 | break; | |
463 | if (timeout >= CRB_WIN_LOCK_TIMEOUT) | |
464 | return -1; | |
465 | timeout++; | |
466 | } | |
467 | qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); | |
468 | return 0; | |
469 | } | |
470 | ||
471 | #define IDC_LOCK_TIMEOUT 100000000 | |
472 | int qla82xx_idc_lock(struct qla_hw_data *ha) | |
473 | { | |
474 | int i; | |
475 | int done = 0, timeout = 0; | |
476 | ||
477 | while (!done) { | |
478 | /* acquire semaphore5 from PCI HW block */ | |
479 | done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); | |
480 | if (done == 1) | |
481 | break; | |
482 | if (timeout >= IDC_LOCK_TIMEOUT) | |
483 | return -1; | |
484 | ||
485 | timeout++; | |
486 | ||
487 | /* Yield CPU */ | |
488 | if (!in_interrupt()) | |
489 | schedule(); | |
490 | else { | |
491 | for (i = 0; i < 20; i++) | |
492 | cpu_relax(); | |
493 | } | |
494 | } | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
499 | void qla82xx_idc_unlock(struct qla_hw_data *ha) | |
500 | { | |
501 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); | |
502 | } | |
503 | ||
504 | int | |
505 | qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) | |
506 | { | |
507 | struct crb_128M_2M_sub_block_map *m; | |
508 | ||
509 | if (*off >= QLA82XX_CRB_MAX) | |
510 | return -1; | |
511 | ||
512 | if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { | |
513 | *off = (*off - QLA82XX_PCI_CAMQM) + | |
514 | QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; | |
515 | return 0; | |
516 | } | |
517 | ||
518 | if (*off < QLA82XX_PCI_CRBSPACE) | |
519 | return -1; | |
520 | ||
521 | *off -= QLA82XX_PCI_CRBSPACE; | |
522 | ||
523 | /* Try direct map */ | |
524 | m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; | |
525 | ||
526 | if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { | |
527 | *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; | |
528 | return 0; | |
529 | } | |
530 | /* Not in direct map, use crb window */ | |
531 | return 1; | |
532 | } | |
533 | ||
534 | /* PCI Windowing for DDR regions. */ | |
535 | #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ | |
536 | (((addr) <= (high)) && ((addr) >= (low))) | |
537 | /* | |
538 | * check memory access boundary. | |
539 | * used by test agent. support ddr access only for now | |
540 | */ | |
541 | static unsigned long | |
542 | qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, | |
543 | unsigned long long addr, int size) | |
544 | { | |
545 | if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, | |
546 | QLA82XX_ADDR_DDR_NET_MAX) || | |
547 | !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, | |
548 | QLA82XX_ADDR_DDR_NET_MAX) || | |
549 | ((size != 1) && (size != 2) && (size != 4) && (size != 8))) | |
550 | return 0; | |
551 | else | |
552 | return 1; | |
553 | } | |
554 | ||
555 | int qla82xx_pci_set_window_warning_count; | |
556 | ||
557 | unsigned long | |
558 | qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) | |
559 | { | |
560 | int window; | |
561 | u32 win_read; | |
562 | ||
563 | if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, | |
564 | QLA82XX_ADDR_DDR_NET_MAX)) { | |
565 | /* DDR network side */ | |
566 | window = MN_WIN(addr); | |
567 | ha->ddr_mn_window = window; | |
568 | qla82xx_wr_32(ha, | |
569 | ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); | |
570 | win_read = qla82xx_rd_32(ha, | |
571 | ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); | |
572 | if ((win_read << 17) != window) { | |
573 | qla_printk(KERN_WARNING, ha, | |
574 | "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n", | |
575 | __func__, window, win_read); | |
576 | } | |
577 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; | |
578 | } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, | |
579 | QLA82XX_ADDR_OCM0_MAX)) { | |
580 | unsigned int temp1; | |
581 | if ((addr & 0x00ff800) == 0xff800) { | |
582 | qla_printk(KERN_WARNING, ha, | |
583 | "%s: QM access not handled.\n", __func__); | |
584 | addr = -1UL; | |
585 | } | |
586 | window = OCM_WIN(addr); | |
587 | ha->ddr_mn_window = window; | |
588 | qla82xx_wr_32(ha, | |
589 | ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); | |
590 | win_read = qla82xx_rd_32(ha, | |
591 | ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); | |
592 | temp1 = ((window & 0x1FF) << 7) | | |
593 | ((window & 0x0FFFE0000) >> 17); | |
594 | if (win_read != temp1) { | |
595 | qla_printk(KERN_WARNING, ha, | |
596 | "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x)\n", | |
597 | __func__, temp1, win_read); | |
598 | } | |
599 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; | |
600 | ||
601 | } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, | |
602 | QLA82XX_P3_ADDR_QDR_NET_MAX)) { | |
603 | /* QDR network side */ | |
604 | window = MS_WIN(addr); | |
605 | ha->qdr_sn_window = window; | |
606 | qla82xx_wr_32(ha, | |
607 | ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); | |
608 | win_read = qla82xx_rd_32(ha, | |
609 | ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); | |
610 | if (win_read != window) { | |
611 | qla_printk(KERN_WARNING, ha, | |
612 | "%s: Written MSwin (0x%x) != Read MSwin (0x%x)\n", | |
613 | __func__, window, win_read); | |
614 | } | |
615 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; | |
616 | } else { | |
617 | /* | |
618 | * peg gdb frequently accesses memory that doesn't exist, | |
619 | * this limits the chit chat so debugging isn't slowed down. | |
620 | */ | |
621 | if ((qla82xx_pci_set_window_warning_count++ < 8) || | |
622 | (qla82xx_pci_set_window_warning_count%64 == 0)) { | |
623 | qla_printk(KERN_WARNING, ha, | |
624 | "%s: Warning:%s Unknown address range!\n", __func__, | |
625 | QLA2XXX_DRIVER_NAME); | |
626 | } | |
627 | addr = -1UL; | |
628 | } | |
629 | return addr; | |
630 | } | |
631 | ||
632 | /* check if address is in the same windows as the previous access */ | |
633 | static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, | |
634 | unsigned long long addr) | |
635 | { | |
636 | int window; | |
637 | unsigned long long qdr_max; | |
638 | ||
639 | qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; | |
640 | ||
641 | /* DDR network side */ | |
642 | if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, | |
643 | QLA82XX_ADDR_DDR_NET_MAX)) | |
644 | BUG(); | |
645 | else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, | |
646 | QLA82XX_ADDR_OCM0_MAX)) | |
647 | return 1; | |
648 | else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, | |
649 | QLA82XX_ADDR_OCM1_MAX)) | |
650 | return 1; | |
651 | else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { | |
652 | /* QDR network side */ | |
653 | window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; | |
654 | if (ha->qdr_sn_window == window) | |
655 | return 1; | |
656 | } | |
657 | return 0; | |
658 | } | |
659 | ||
660 | static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, | |
661 | u64 off, void *data, int size) | |
662 | { | |
663 | unsigned long flags; | |
664 | void *addr; | |
665 | int ret = 0; | |
666 | u64 start; | |
667 | uint8_t *mem_ptr = NULL; | |
668 | unsigned long mem_base; | |
669 | unsigned long mem_page; | |
670 | ||
671 | write_lock_irqsave(&ha->hw_lock, flags); | |
672 | ||
673 | /* | |
674 | * If attempting to access unknown address or straddle hw windows, | |
675 | * do not access. | |
676 | */ | |
677 | start = qla82xx_pci_set_window(ha, off); | |
678 | if ((start == -1UL) || | |
679 | (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { | |
680 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
681 | qla_printk(KERN_ERR, ha, | |
682 | "%s out of bound pci memory access. " | |
683 | "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME, off); | |
684 | return -1; | |
685 | } | |
686 | ||
687 | addr = qla82xx_pci_base_offsetfset(ha, start); | |
688 | if (!addr) { | |
689 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
690 | mem_base = pci_resource_start(ha->pdev, 0); | |
691 | mem_page = start & PAGE_MASK; | |
692 | /* Map two pages whenever user tries to access addresses in two | |
693 | * consecutive pages. | |
694 | */ | |
695 | if (mem_page != ((start + size - 1) & PAGE_MASK)) | |
696 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); | |
697 | else | |
698 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); | |
699 | if (mem_ptr == 0UL) { | |
700 | *(u8 *)data = 0; | |
701 | return -1; | |
702 | } | |
703 | addr = mem_ptr; | |
704 | addr += start & (PAGE_SIZE - 1); | |
705 | write_lock_irqsave(&ha->hw_lock, flags); | |
706 | } | |
707 | ||
708 | switch (size) { | |
709 | case 1: | |
710 | *(u8 *)data = readb(addr); | |
711 | break; | |
712 | case 2: | |
713 | *(u16 *)data = readw(addr); | |
714 | break; | |
715 | case 4: | |
716 | *(u32 *)data = readl(addr); | |
717 | break; | |
718 | case 8: | |
719 | *(u64 *)data = readq(addr); | |
720 | break; | |
721 | default: | |
722 | ret = -1; | |
723 | break; | |
724 | } | |
725 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
726 | ||
727 | if (mem_ptr) | |
728 | iounmap(mem_ptr); | |
729 | return ret; | |
730 | } | |
731 | ||
732 | static int | |
733 | qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, | |
734 | u64 off, void *data, int size) | |
735 | { | |
736 | unsigned long flags; | |
737 | void *addr; | |
738 | int ret = 0; | |
739 | u64 start; | |
740 | uint8_t *mem_ptr = NULL; | |
741 | unsigned long mem_base; | |
742 | unsigned long mem_page; | |
743 | ||
744 | write_lock_irqsave(&ha->hw_lock, flags); | |
745 | ||
746 | /* | |
747 | * If attempting to access unknown address or straddle hw windows, | |
748 | * do not access. | |
749 | */ | |
750 | start = qla82xx_pci_set_window(ha, off); | |
751 | if ((start == -1UL) || | |
752 | (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { | |
753 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
754 | qla_printk(KERN_ERR, ha, | |
755 | "%s out of bound pci memory access. " | |
756 | "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME, off); | |
757 | return -1; | |
758 | } | |
759 | ||
760 | addr = qla82xx_pci_base_offsetfset(ha, start); | |
761 | if (!addr) { | |
762 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
763 | mem_base = pci_resource_start(ha->pdev, 0); | |
764 | mem_page = start & PAGE_MASK; | |
765 | /* Map two pages whenever user tries to access addresses in two | |
766 | * consecutive pages. | |
767 | */ | |
768 | if (mem_page != ((start + size - 1) & PAGE_MASK)) | |
769 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); | |
770 | else | |
771 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); | |
772 | if (mem_ptr == 0UL) | |
773 | return -1; | |
774 | ||
775 | addr = mem_ptr; | |
776 | addr += start & (PAGE_SIZE - 1); | |
777 | write_lock_irqsave(&ha->hw_lock, flags); | |
778 | } | |
779 | ||
780 | switch (size) { | |
781 | case 1: | |
782 | writeb(*(u8 *)data, addr); | |
783 | break; | |
784 | case 2: | |
785 | writew(*(u16 *)data, addr); | |
786 | break; | |
787 | case 4: | |
788 | writel(*(u32 *)data, addr); | |
789 | break; | |
790 | case 8: | |
791 | writeq(*(u64 *)data, addr); | |
792 | break; | |
793 | default: | |
794 | ret = -1; | |
795 | break; | |
796 | } | |
797 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
798 | if (mem_ptr) | |
799 | iounmap(mem_ptr); | |
800 | return ret; | |
801 | } | |
802 | ||
803 | int | |
804 | qla82xx_wrmem(struct qla_hw_data *ha, u64 off, void *data, int size) | |
805 | { | |
806 | int i, j, ret = 0, loop, sz[2], off0; | |
807 | u32 temp; | |
808 | u64 off8, mem_crb, tmpw, word[2] = {0, 0}; | |
809 | #define MAX_CTL_CHECK 1000 | |
810 | /* | |
811 | * If not MN, go check for MS or invalid. | |
812 | */ | |
813 | if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) { | |
814 | mem_crb = QLA82XX_CRB_QDR_NET; | |
815 | } else { | |
816 | mem_crb = QLA82XX_CRB_DDR_NET; | |
817 | if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) | |
818 | return qla82xx_pci_mem_write_direct(ha, off, | |
819 | data, size); | |
820 | } | |
821 | ||
822 | off8 = off & 0xfffffff8; | |
823 | off0 = off & 0x7; | |
824 | sz[0] = (size < (8 - off0)) ? size : (8 - off0); | |
825 | sz[1] = size - sz[0]; | |
826 | loop = ((off0 + size - 1) >> 3) + 1; | |
827 | ||
828 | if ((size != 8) || (off0 != 0)) { | |
829 | for (i = 0; i < loop; i++) { | |
830 | if (qla82xx_rdmem(ha, off8 + (i << 3), &word[i], 8)) | |
831 | return -1; | |
832 | } | |
833 | } | |
834 | ||
835 | switch (size) { | |
836 | case 1: | |
837 | tmpw = *((u8 *)data); | |
838 | break; | |
839 | case 2: | |
840 | tmpw = *((u16 *)data); | |
841 | break; | |
842 | case 4: | |
843 | tmpw = *((u32 *)data); | |
844 | break; | |
845 | case 8: | |
846 | default: | |
847 | tmpw = *((u64 *)data); | |
848 | break; | |
849 | } | |
850 | ||
851 | word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); | |
852 | word[0] |= tmpw << (off0 * 8); | |
853 | ||
854 | if (loop == 2) { | |
855 | word[1] &= ~(~0ULL << (sz[1] * 8)); | |
856 | word[1] |= tmpw >> (sz[0] * 8); | |
857 | } | |
858 | ||
859 | for (i = 0; i < loop; i++) { | |
860 | temp = off8 + (i << 3); | |
861 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); | |
862 | temp = 0; | |
863 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); | |
864 | temp = word[i] & 0xffffffff; | |
865 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); | |
866 | temp = (word[i] >> 32) & 0xffffffff; | |
867 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); | |
868 | temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; | |
869 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); | |
870 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; | |
871 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); | |
872 | ||
873 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
874 | temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); | |
875 | if ((temp & MIU_TA_CTL_BUSY) == 0) | |
876 | break; | |
877 | } | |
878 | ||
879 | if (j >= MAX_CTL_CHECK) { | |
880 | qla_printk(KERN_WARNING, ha, | |
881 | "%s: Fail to write through agent\n", | |
882 | QLA2XXX_DRIVER_NAME); | |
883 | ret = -1; | |
884 | break; | |
885 | } | |
886 | } | |
887 | return ret; | |
888 | } | |
889 | ||
890 | int | |
891 | qla82xx_rdmem(struct qla_hw_data *ha, u64 off, void *data, int size) | |
892 | { | |
893 | int i, j = 0, k, start, end, loop, sz[2], off0[2]; | |
894 | u32 temp; | |
895 | u64 off8, val, mem_crb, word[2] = {0, 0}; | |
896 | #define MAX_CTL_CHECK 1000 | |
897 | ||
898 | /* | |
899 | * If not MN, go check for MS or invalid. | |
900 | */ | |
901 | if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) | |
902 | mem_crb = QLA82XX_CRB_QDR_NET; | |
903 | else { | |
904 | mem_crb = QLA82XX_CRB_DDR_NET; | |
905 | if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) | |
906 | return qla82xx_pci_mem_read_direct(ha, off, | |
907 | data, size); | |
908 | } | |
909 | ||
910 | off8 = off & 0xfffffff8; | |
911 | off0[0] = off & 0x7; | |
912 | off0[1] = 0; | |
913 | sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); | |
914 | sz[1] = size - sz[0]; | |
915 | loop = ((off0[0] + size - 1) >> 3) + 1; | |
916 | ||
917 | for (i = 0; i < loop; i++) { | |
918 | temp = off8 + (i << 3); | |
919 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); | |
920 | temp = 0; | |
921 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); | |
922 | temp = MIU_TA_CTL_ENABLE; | |
923 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); | |
924 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; | |
925 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); | |
926 | ||
927 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
928 | temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); | |
929 | if ((temp & MIU_TA_CTL_BUSY) == 0) | |
930 | break; | |
931 | } | |
932 | ||
933 | if (j >= MAX_CTL_CHECK) { | |
934 | qla_printk(KERN_INFO, ha, | |
935 | "%s: Fail to read through agent\n", | |
936 | QLA2XXX_DRIVER_NAME); | |
937 | break; | |
938 | } | |
939 | ||
940 | start = off0[i] >> 2; | |
941 | end = (off0[i] + sz[i] - 1) >> 2; | |
942 | for (k = start; k <= end; k++) { | |
943 | temp = qla82xx_rd_32(ha, | |
944 | mem_crb + MIU_TEST_AGT_RDDATA(k)); | |
945 | word[i] |= ((u64)temp << (32 * k)); | |
946 | } | |
947 | } | |
948 | ||
949 | if (j >= MAX_CTL_CHECK) | |
950 | return -1; | |
951 | ||
952 | if (sz[0] == 8) { | |
953 | val = word[0]; | |
954 | } else { | |
955 | val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | | |
956 | ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); | |
957 | } | |
958 | ||
959 | switch (size) { | |
960 | case 1: | |
961 | *(u8 *)data = val; | |
962 | break; | |
963 | case 2: | |
964 | *(u16 *)data = val; | |
965 | break; | |
966 | case 4: | |
967 | *(u32 *)data = val; | |
968 | break; | |
969 | case 8: | |
970 | *(u64 *)data = val; | |
971 | break; | |
972 | } | |
973 | return 0; | |
974 | } | |
975 | ||
976 | #define MTU_FUDGE_FACTOR 100 | |
977 | unsigned long qla82xx_decode_crb_addr(unsigned long addr) | |
978 | { | |
979 | int i; | |
980 | unsigned long base_addr, offset, pci_base; | |
981 | ||
982 | if (!qla82xx_crb_table_initialized) | |
983 | qla82xx_crb_addr_transform_setup(); | |
984 | ||
985 | pci_base = ADDR_ERROR; | |
986 | base_addr = addr & 0xfff00000; | |
987 | offset = addr & 0x000fffff; | |
988 | ||
989 | for (i = 0; i < MAX_CRB_XFORM; i++) { | |
990 | if (crb_addr_xform[i] == base_addr) { | |
991 | pci_base = i << 20; | |
992 | break; | |
993 | } | |
994 | } | |
995 | if (pci_base == ADDR_ERROR) | |
996 | return pci_base; | |
997 | return pci_base + offset; | |
998 | } | |
999 | ||
1000 | static long rom_max_timeout = 100; | |
1001 | static long qla82xx_rom_lock_timeout = 100; | |
1002 | ||
1003 | int | |
1004 | qla82xx_rom_lock(struct qla_hw_data *ha) | |
1005 | { | |
1006 | int done = 0, timeout = 0; | |
1007 | ||
1008 | while (!done) { | |
1009 | /* acquire semaphore2 from PCI HW block */ | |
1010 | done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); | |
1011 | if (done == 1) | |
1012 | break; | |
1013 | if (timeout >= qla82xx_rom_lock_timeout) | |
1014 | return -1; | |
1015 | timeout++; | |
1016 | } | |
1017 | qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); | |
1018 | return 0; | |
1019 | } | |
1020 | ||
1021 | int | |
1022 | qla82xx_wait_rom_busy(struct qla_hw_data *ha) | |
1023 | { | |
1024 | long timeout = 0; | |
1025 | long done = 0 ; | |
1026 | ||
1027 | while (done == 0) { | |
1028 | done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); | |
1029 | done &= 4; | |
1030 | timeout++; | |
1031 | if (timeout >= rom_max_timeout) { | |
1032 | DEBUG(qla_printk(KERN_INFO, ha, | |
1033 | "%s: Timeout reached waiting for rom busy", | |
1034 | QLA2XXX_DRIVER_NAME)); | |
1035 | return -1; | |
1036 | } | |
1037 | } | |
1038 | return 0; | |
1039 | } | |
1040 | ||
1041 | int | |
1042 | qla82xx_wait_rom_done(struct qla_hw_data *ha) | |
1043 | { | |
1044 | long timeout = 0; | |
1045 | long done = 0 ; | |
1046 | ||
1047 | while (done == 0) { | |
1048 | done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); | |
1049 | done &= 2; | |
1050 | timeout++; | |
1051 | if (timeout >= rom_max_timeout) { | |
1052 | DEBUG(qla_printk(KERN_INFO, ha, | |
1053 | "%s: Timeout reached waiting for rom done", | |
1054 | QLA2XXX_DRIVER_NAME)); | |
1055 | return -1; | |
1056 | } | |
1057 | } | |
1058 | return 0; | |
1059 | } | |
1060 | ||
1061 | int | |
1062 | qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) | |
1063 | { | |
1064 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); | |
1065 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); | |
1066 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); | |
1067 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); | |
1068 | qla82xx_wait_rom_busy(ha); | |
1069 | if (qla82xx_wait_rom_done(ha)) { | |
1070 | qla_printk(KERN_WARNING, ha, | |
1071 | "%s: Error waiting for rom done\n", | |
1072 | QLA2XXX_DRIVER_NAME); | |
1073 | return -1; | |
1074 | } | |
1075 | /* Reset abyte_cnt and dummy_byte_cnt */ | |
1076 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); | |
1077 | udelay(10); | |
1078 | cond_resched(); | |
1079 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); | |
1080 | *valp = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); | |
1081 | return 0; | |
1082 | } | |
1083 | ||
1084 | int | |
1085 | qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) | |
1086 | { | |
1087 | int ret, loops = 0; | |
1088 | ||
1089 | while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { | |
1090 | udelay(100); | |
1091 | schedule(); | |
1092 | loops++; | |
1093 | } | |
1094 | if (loops >= 50000) { | |
1095 | qla_printk(KERN_INFO, ha, | |
1096 | "%s: qla82xx_rom_lock failed\n", | |
1097 | QLA2XXX_DRIVER_NAME); | |
1098 | return -1; | |
1099 | } | |
1100 | ret = qla82xx_do_rom_fast_read(ha, addr, valp); | |
1101 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); | |
1102 | return ret; | |
1103 | } | |
1104 | ||
1105 | int | |
1106 | qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) | |
1107 | { | |
1108 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); | |
1109 | qla82xx_wait_rom_busy(ha); | |
1110 | if (qla82xx_wait_rom_done(ha)) { | |
1111 | qla_printk(KERN_WARNING, ha, | |
1112 | "Error waiting for rom done\n"); | |
1113 | return -1; | |
1114 | } | |
1115 | *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); | |
1116 | return 0; | |
1117 | } | |
1118 | ||
1119 | int | |
1120 | qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) | |
1121 | { | |
1122 | long timeout = 0; | |
1123 | uint32_t done = 1 ; | |
1124 | uint32_t val; | |
1125 | int ret = 0; | |
1126 | ||
1127 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); | |
1128 | while ((done != 0) && (ret == 0)) { | |
1129 | ret = qla82xx_read_status_reg(ha, &val); | |
1130 | done = val & 1; | |
1131 | timeout++; | |
1132 | udelay(10); | |
1133 | cond_resched(); | |
1134 | if (timeout >= 50000) { | |
1135 | qla_printk(KERN_WARNING, ha, | |
1136 | "Timeout reached waiting for write finish"); | |
1137 | return -1; | |
1138 | } | |
1139 | } | |
1140 | return ret; | |
1141 | } | |
1142 | ||
1143 | int | |
1144 | qla82xx_flash_set_write_enable(struct qla_hw_data *ha) | |
1145 | { | |
1146 | uint32_t val; | |
1147 | qla82xx_wait_rom_busy(ha); | |
1148 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); | |
1149 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); | |
1150 | qla82xx_wait_rom_busy(ha); | |
1151 | if (qla82xx_wait_rom_done(ha)) | |
1152 | return -1; | |
1153 | if (qla82xx_read_status_reg(ha, &val) != 0) | |
1154 | return -1; | |
1155 | if ((val & 2) != 2) | |
1156 | return -1; | |
1157 | return 0; | |
1158 | } | |
1159 | ||
1160 | int | |
1161 | qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) | |
1162 | { | |
1163 | if (qla82xx_flash_set_write_enable(ha)) | |
1164 | return -1; | |
1165 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); | |
1166 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); | |
1167 | if (qla82xx_wait_rom_done(ha)) { | |
1168 | qla_printk(KERN_WARNING, ha, | |
1169 | "Error waiting for rom done\n"); | |
1170 | return -1; | |
1171 | } | |
1172 | return qla82xx_flash_wait_write_finish(ha); | |
1173 | } | |
1174 | ||
1175 | int | |
1176 | qla82xx_write_disable_flash(struct qla_hw_data *ha) | |
1177 | { | |
1178 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); | |
1179 | if (qla82xx_wait_rom_done(ha)) { | |
1180 | qla_printk(KERN_WARNING, ha, | |
1181 | "Error waiting for rom done\n"); | |
1182 | return -1; | |
1183 | } | |
1184 | return 0; | |
1185 | } | |
1186 | ||
1187 | int | |
1188 | ql82xx_rom_lock_d(struct qla_hw_data *ha) | |
1189 | { | |
1190 | int loops = 0; | |
1191 | while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { | |
1192 | udelay(100); | |
1193 | cond_resched(); | |
1194 | loops++; | |
1195 | } | |
1196 | if (loops >= 50000) { | |
1197 | qla_printk(KERN_WARNING, ha, "ROM lock failed\n"); | |
1198 | return -1; | |
1199 | } | |
1200 | return 0;; | |
1201 | } | |
1202 | ||
1203 | int | |
1204 | qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, | |
1205 | uint32_t data) | |
1206 | { | |
1207 | int ret = 0; | |
1208 | ||
1209 | ret = ql82xx_rom_lock_d(ha); | |
1210 | if (ret < 0) { | |
1211 | qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); | |
1212 | return ret; | |
1213 | } | |
1214 | ||
1215 | if (qla82xx_flash_set_write_enable(ha)) | |
1216 | goto done_write; | |
1217 | ||
1218 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); | |
1219 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); | |
1220 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); | |
1221 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); | |
1222 | qla82xx_wait_rom_busy(ha); | |
1223 | if (qla82xx_wait_rom_done(ha)) { | |
1224 | qla_printk(KERN_WARNING, ha, | |
1225 | "Error waiting for rom done\n"); | |
1226 | ret = -1; | |
1227 | goto done_write; | |
1228 | } | |
1229 | ||
1230 | ret = qla82xx_flash_wait_write_finish(ha); | |
1231 | ||
1232 | done_write: | |
1233 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); | |
1234 | return ret; | |
1235 | } | |
1236 | ||
1237 | /* This routine does CRB initialize sequence | |
1238 | * to put the ISP into operational state | |
1239 | */ | |
1240 | int qla82xx_pinit_from_rom(scsi_qla_host_t *vha) | |
1241 | { | |
1242 | int addr, val; | |
1243 | int i ; | |
1244 | struct crb_addr_pair *buf; | |
1245 | unsigned long off; | |
1246 | unsigned offset, n; | |
1247 | struct qla_hw_data *ha = vha->hw; | |
1248 | ||
1249 | struct crb_addr_pair { | |
1250 | long addr; | |
1251 | long data; | |
1252 | }; | |
1253 | ||
1254 | /* Halt all the indiviual PEGs and other blocks of the ISP */ | |
1255 | qla82xx_rom_lock(ha); | |
1256 | if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) | |
1257 | /* don't reset CAM block on reset */ | |
1258 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); | |
1259 | else | |
1260 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); | |
1261 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); | |
1262 | ||
1263 | /* Read the signature value from the flash. | |
1264 | * Offset 0: Contain signature (0xcafecafe) | |
1265 | * Offset 4: Offset and number of addr/value pairs | |
1266 | * that present in CRB initialize sequence | |
1267 | */ | |
1268 | if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || | |
1269 | qla82xx_rom_fast_read(ha, 4, &n) != 0) { | |
1270 | qla_printk(KERN_WARNING, ha, | |
1271 | "[ERROR] Reading crb_init area: n: %08x\n", n); | |
1272 | return -1; | |
1273 | } | |
1274 | ||
1275 | /* Offset in flash = lower 16 bits | |
1276 | * Number of enteries = upper 16 bits | |
1277 | */ | |
1278 | offset = n & 0xffffU; | |
1279 | n = (n >> 16) & 0xffffU; | |
1280 | ||
1281 | /* number of addr/value pair should not exceed 1024 enteries */ | |
1282 | if (n >= 1024) { | |
1283 | qla_printk(KERN_WARNING, ha, | |
1284 | "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n", | |
1285 | QLA2XXX_DRIVER_NAME, __func__, n); | |
1286 | return -1; | |
1287 | } | |
1288 | ||
1289 | qla_printk(KERN_INFO, ha, | |
1290 | "%s: %d CRB init values found in ROM.\n", QLA2XXX_DRIVER_NAME, n); | |
1291 | ||
1292 | buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); | |
1293 | if (buf == NULL) { | |
1294 | qla_printk(KERN_WARNING, ha, | |
1295 | "%s: [ERROR] Unable to malloc memory.\n", | |
1296 | QLA2XXX_DRIVER_NAME); | |
1297 | return -1; | |
1298 | } | |
1299 | ||
1300 | for (i = 0; i < n; i++) { | |
1301 | if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || | |
1302 | qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { | |
1303 | kfree(buf); | |
1304 | return -1; | |
1305 | } | |
1306 | ||
1307 | buf[i].addr = addr; | |
1308 | buf[i].data = val; | |
1309 | } | |
1310 | ||
1311 | for (i = 0; i < n; i++) { | |
1312 | /* Translate internal CRB initialization | |
1313 | * address to PCI bus address | |
1314 | */ | |
1315 | off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + | |
1316 | QLA82XX_PCI_CRBSPACE; | |
1317 | /* Not all CRB addr/value pair to be written, | |
1318 | * some of them are skipped | |
1319 | */ | |
1320 | ||
1321 | /* skipping cold reboot MAGIC */ | |
1322 | if (off == QLA82XX_CAM_RAM(0x1fc)) | |
1323 | continue; | |
1324 | ||
1325 | /* do not reset PCI */ | |
1326 | if (off == (ROMUSB_GLB + 0xbc)) | |
1327 | continue; | |
1328 | ||
1329 | /* skip core clock, so that firmware can increase the clock */ | |
1330 | if (off == (ROMUSB_GLB + 0xc8)) | |
1331 | continue; | |
1332 | ||
1333 | /* skip the function enable register */ | |
1334 | if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) | |
1335 | continue; | |
1336 | ||
1337 | if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) | |
1338 | continue; | |
1339 | ||
1340 | if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) | |
1341 | continue; | |
1342 | ||
1343 | if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) | |
1344 | continue; | |
1345 | ||
1346 | if (off == ADDR_ERROR) { | |
1347 | qla_printk(KERN_WARNING, ha, | |
1348 | "%s: [ERROR] Unknown addr: 0x%08lx\n", | |
1349 | QLA2XXX_DRIVER_NAME, buf[i].addr); | |
1350 | continue; | |
1351 | } | |
1352 | ||
1353 | if (off == (QLA82XX_CRB_PEG_NET_1 + 0x18)) { | |
1354 | if (!QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) | |
1355 | buf[i].data = 0x1020; | |
1356 | } | |
1357 | ||
1358 | qla82xx_wr_32(ha, off, buf[i].data); | |
1359 | ||
1360 | /* ISP requires much bigger delay to settle down, | |
1361 | * else crb_window returns 0xffffffff | |
1362 | */ | |
1363 | if (off == QLA82XX_ROMUSB_GLB_SW_RESET) | |
1364 | msleep(1000); | |
1365 | ||
1366 | /* ISP requires millisec delay between | |
1367 | * successive CRB register updation | |
1368 | */ | |
1369 | msleep(1); | |
1370 | } | |
1371 | ||
1372 | kfree(buf); | |
1373 | ||
1374 | /* Resetting the data and instruction cache */ | |
1375 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); | |
1376 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); | |
1377 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); | |
1378 | ||
1379 | /* Clear all protocol processing engines */ | |
1380 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); | |
1381 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); | |
1382 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); | |
1383 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); | |
1384 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); | |
1385 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); | |
1386 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); | |
1387 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); | |
1388 | return 0; | |
1389 | } | |
1390 | ||
1391 | int qla82xx_check_for_bad_spd(struct qla_hw_data *ha) | |
1392 | { | |
1393 | u32 val = 0; | |
1394 | val = qla82xx_rd_32(ha, BOOT_LOADER_DIMM_STATUS); | |
1395 | val &= QLA82XX_BOOT_LOADER_MN_ISSUE; | |
1396 | if (val & QLA82XX_PEG_TUNE_MN_SPD_ZEROED) { | |
1397 | qla_printk(KERN_INFO, ha, | |
1398 | "Memory DIMM SPD not programmed. " | |
1399 | " Assumed valid.\n"); | |
1400 | return 1; | |
1401 | } else if (val) { | |
1402 | qla_printk(KERN_INFO, ha, | |
1403 | "Memory DIMM type incorrect.Info:%08X.\n", val); | |
1404 | return 2; | |
1405 | } | |
1406 | return 0; | |
1407 | } | |
1408 | ||
1409 | int | |
1410 | qla82xx_fw_load_from_flash(struct qla_hw_data *ha) | |
1411 | { | |
1412 | int i; | |
1413 | long size = 0; | |
1414 | long flashaddr = BOOTLD_START, memaddr = BOOTLD_START; | |
1415 | u64 data; | |
1416 | u32 high, low; | |
1417 | size = (IMAGE_START - BOOTLD_START) / 8; | |
1418 | ||
1419 | for (i = 0; i < size; i++) { | |
1420 | if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || | |
1421 | (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { | |
1422 | return -1; | |
1423 | } | |
1424 | data = ((u64)high << 32) | low ; | |
1425 | qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); | |
1426 | flashaddr += 8; | |
1427 | memaddr += 8; | |
1428 | ||
1429 | if (i % 0x1000 == 0) | |
1430 | msleep(1); | |
1431 | } | |
1432 | udelay(100); | |
1433 | read_lock(&ha->hw_lock); | |
1434 | if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { | |
1435 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); | |
1436 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); | |
1437 | } else { | |
1438 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001d); | |
1439 | } | |
1440 | read_unlock(&ha->hw_lock); | |
1441 | return 0; | |
1442 | } | |
1443 | ||
1444 | int | |
1445 | qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, | |
1446 | u64 off, void *data, int size) | |
1447 | { | |
1448 | int i, j = 0, k, start, end, loop, sz[2], off0[2]; | |
1449 | int shift_amount; | |
1450 | uint32_t temp; | |
1451 | uint64_t off8, val, mem_crb, word[2] = {0, 0}; | |
1452 | ||
1453 | /* | |
1454 | * If not MN, go check for MS or invalid. | |
1455 | */ | |
1456 | ||
1457 | if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) | |
1458 | mem_crb = QLA82XX_CRB_QDR_NET; | |
1459 | else { | |
1460 | mem_crb = QLA82XX_CRB_DDR_NET; | |
1461 | if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) | |
1462 | return qla82xx_pci_mem_read_direct(ha, | |
1463 | off, data, size); | |
1464 | } | |
1465 | ||
1466 | if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { | |
1467 | off8 = off & 0xfffffff0; | |
1468 | off0[0] = off & 0xf; | |
1469 | sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); | |
1470 | shift_amount = 4; | |
1471 | } else { | |
1472 | off8 = off & 0xfffffff8; | |
1473 | off0[0] = off & 0x7; | |
1474 | sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); | |
1475 | shift_amount = 4; | |
1476 | } | |
1477 | loop = ((off0[0] + size - 1) >> shift_amount) + 1; | |
1478 | off0[1] = 0; | |
1479 | sz[1] = size - sz[0]; | |
1480 | ||
1481 | /* | |
1482 | * don't lock here - write_wx gets the lock if each time | |
1483 | * write_lock_irqsave(&adapter->adapter_lock, flags); | |
1484 | * netxen_nic_pci_change_crbwindow_128M(adapter, 0); | |
1485 | */ | |
1486 | ||
1487 | for (i = 0; i < loop; i++) { | |
1488 | temp = off8 + (i << shift_amount); | |
1489 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); | |
1490 | temp = 0; | |
1491 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); | |
1492 | temp = MIU_TA_CTL_ENABLE; | |
1493 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); | |
1494 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; | |
1495 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); | |
1496 | ||
1497 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
1498 | temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); | |
1499 | if ((temp & MIU_TA_CTL_BUSY) == 0) | |
1500 | break; | |
1501 | } | |
1502 | ||
1503 | if (j >= MAX_CTL_CHECK) { | |
1504 | if (printk_ratelimit()) | |
1505 | dev_err(&ha->pdev->dev, | |
1506 | "failed to read through agent\n"); | |
1507 | break; | |
1508 | } | |
1509 | ||
1510 | start = off0[i] >> 2; | |
1511 | end = (off0[i] + sz[i] - 1) >> 2; | |
1512 | for (k = start; k <= end; k++) { | |
1513 | temp = qla82xx_rd_32(ha, | |
1514 | mem_crb + MIU_TEST_AGT_RDDATA(k)); | |
1515 | word[i] |= ((uint64_t)temp << (32 * (k & 1))); | |
1516 | } | |
1517 | } | |
1518 | ||
1519 | /* | |
1520 | * netxen_nic_pci_change_crbwindow_128M(adapter, 1); | |
1521 | * write_unlock_irqrestore(&adapter->adapter_lock, flags); | |
1522 | */ | |
1523 | ||
1524 | if (j >= MAX_CTL_CHECK) | |
1525 | return -1; | |
1526 | ||
1527 | if ((off0[0] & 7) == 0) { | |
1528 | val = word[0]; | |
1529 | } else { | |
1530 | val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | | |
1531 | ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); | |
1532 | } | |
1533 | ||
1534 | switch (size) { | |
1535 | case 1: | |
1536 | *(uint8_t *)data = val; | |
1537 | break; | |
1538 | case 2: | |
1539 | *(uint16_t *)data = val; | |
1540 | break; | |
1541 | case 4: | |
1542 | *(uint32_t *)data = val; | |
1543 | break; | |
1544 | case 8: | |
1545 | *(uint64_t *)data = val; | |
1546 | break; | |
1547 | } | |
1548 | return 0; | |
1549 | } | |
1550 | ||
1551 | int | |
1552 | qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, | |
1553 | u64 off, void *data, int size) | |
1554 | { | |
1555 | int i, j, ret = 0, loop, sz[2], off0; | |
1556 | int scale, shift_amount, p3p, startword; | |
1557 | uint32_t temp; | |
1558 | uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; | |
1559 | ||
1560 | /* | |
1561 | * If not MN, go check for MS or invalid. | |
1562 | */ | |
1563 | if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) | |
1564 | mem_crb = QLA82XX_CRB_QDR_NET; | |
1565 | else { | |
1566 | mem_crb = QLA82XX_CRB_DDR_NET; | |
1567 | if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) | |
1568 | return qla82xx_pci_mem_write_direct(ha, | |
1569 | off, data, size); | |
1570 | } | |
1571 | ||
1572 | off0 = off & 0x7; | |
1573 | sz[0] = (size < (8 - off0)) ? size : (8 - off0); | |
1574 | sz[1] = size - sz[0]; | |
1575 | ||
1576 | if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { | |
1577 | off8 = off & 0xfffffff0; | |
1578 | loop = (((off & 0xf) + size - 1) >> 4) + 1; | |
1579 | shift_amount = 4; | |
1580 | scale = 2; | |
1581 | p3p = 1; | |
1582 | startword = (off & 0xf)/8; | |
1583 | } else { | |
1584 | off8 = off & 0xfffffff8; | |
1585 | loop = ((off0 + size - 1) >> 3) + 1; | |
1586 | shift_amount = 3; | |
1587 | scale = 1; | |
1588 | p3p = 0; | |
1589 | startword = 0; | |
1590 | } | |
1591 | ||
1592 | if (p3p || (size != 8) || (off0 != 0)) { | |
1593 | for (i = 0; i < loop; i++) { | |
1594 | if (qla82xx_pci_mem_read_2M(ha, off8 + | |
1595 | (i << shift_amount), &word[i * scale], 8)) | |
1596 | return -1; | |
1597 | } | |
1598 | } | |
1599 | ||
1600 | switch (size) { | |
1601 | case 1: | |
1602 | tmpw = *((uint8_t *)data); | |
1603 | break; | |
1604 | case 2: | |
1605 | tmpw = *((uint16_t *)data); | |
1606 | break; | |
1607 | case 4: | |
1608 | tmpw = *((uint32_t *)data); | |
1609 | break; | |
1610 | case 8: | |
1611 | default: | |
1612 | tmpw = *((uint64_t *)data); | |
1613 | break; | |
1614 | } | |
1615 | ||
1616 | if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { | |
1617 | if (sz[0] == 8) { | |
1618 | word[startword] = tmpw; | |
1619 | } else { | |
1620 | word[startword] &= | |
1621 | ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); | |
1622 | word[startword] |= tmpw << (off0 * 8); | |
1623 | } | |
1624 | if (sz[1] != 0) { | |
1625 | word[startword+1] &= ~(~0ULL << (sz[1] * 8)); | |
1626 | word[startword+1] |= tmpw >> (sz[0] * 8); | |
1627 | } | |
1628 | } else { | |
1629 | word[startword] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); | |
1630 | word[startword] |= tmpw << (off0 * 8); | |
1631 | ||
1632 | if (loop == 2) { | |
1633 | word[1] &= ~(~0ULL << (sz[1] * 8)); | |
1634 | word[1] |= tmpw >> (sz[0] * 8); | |
1635 | } | |
1636 | } | |
1637 | ||
1638 | /* | |
1639 | * don't lock here - write_wx gets the lock if each time | |
1640 | * write_lock_irqsave(&adapter->adapter_lock, flags); | |
1641 | * netxen_nic_pci_change_crbwindow_128M(adapter, 0); | |
1642 | */ | |
1643 | for (i = 0; i < loop; i++) { | |
1644 | temp = off8 + (i << shift_amount); | |
1645 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); | |
1646 | temp = 0; | |
1647 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); | |
1648 | temp = word[i * scale] & 0xffffffff; | |
1649 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); | |
1650 | temp = (word[i * scale] >> 32) & 0xffffffff; | |
1651 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); | |
1652 | if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { | |
1653 | temp = word[i*scale + 1] & 0xffffffff; | |
1654 | qla82xx_wr_32(ha, mem_crb + | |
1655 | MIU_TEST_AGT_WRDATA_UPPER_LO, temp); | |
1656 | temp = (word[i*scale + 1] >> 32) & 0xffffffff; | |
1657 | qla82xx_wr_32(ha, mem_crb + | |
1658 | MIU_TEST_AGT_WRDATA_UPPER_HI, temp); | |
1659 | } | |
1660 | ||
1661 | temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; | |
1662 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); | |
1663 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; | |
1664 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); | |
1665 | ||
1666 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
1667 | temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); | |
1668 | if ((temp & MIU_TA_CTL_BUSY) == 0) | |
1669 | break; | |
1670 | } | |
1671 | ||
1672 | if (j >= MAX_CTL_CHECK) { | |
1673 | if (printk_ratelimit()) | |
1674 | dev_err(&ha->pdev->dev, | |
1675 | "failed to write through agent\n"); | |
1676 | ret = -1; | |
1677 | break; | |
1678 | } | |
1679 | } | |
1680 | ||
1681 | return ret; | |
1682 | } | |
1683 | ||
1684 | /* PCI related functions */ | |
1685 | char * | |
1686 | qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str) | |
1687 | { | |
1688 | int pcie_reg; | |
1689 | struct qla_hw_data *ha = vha->hw; | |
1690 | char lwstr[6]; | |
1691 | uint16_t lnk; | |
1692 | ||
1693 | pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); | |
1694 | pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk); | |
1695 | ha->link_width = (lnk >> 4) & 0x3f; | |
1696 | ||
1697 | strcpy(str, "PCIe ("); | |
1698 | strcat(str, "2.5Gb/s "); | |
1699 | snprintf(lwstr, sizeof(lwstr), "x%d)", ha->link_width); | |
1700 | strcat(str, lwstr); | |
1701 | return str; | |
1702 | } | |
1703 | ||
1704 | int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) | |
1705 | { | |
1706 | unsigned long val = 0; | |
1707 | u32 control; | |
1708 | ||
1709 | switch (region) { | |
1710 | case 0: | |
1711 | val = 0; | |
1712 | break; | |
1713 | case 1: | |
1714 | pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); | |
1715 | val = control + QLA82XX_MSIX_TBL_SPACE; | |
1716 | break; | |
1717 | } | |
1718 | return val; | |
1719 | } | |
1720 | ||
1721 | int qla82xx_pci_region_len(struct pci_dev *pdev, int region) | |
1722 | { | |
1723 | unsigned long val = 0; | |
1724 | u32 control; | |
1725 | switch (region) { | |
1726 | case 0: | |
1727 | pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); | |
1728 | val = control; | |
1729 | break; | |
1730 | case 1: | |
1731 | val = pci_resource_len(pdev, 0) - | |
1732 | qla82xx_pci_region_offset(pdev, 1); | |
1733 | break; | |
1734 | } | |
1735 | return val; | |
1736 | } | |
1737 | ||
1738 | int | |
1739 | qla82xx_iospace_config(struct qla_hw_data *ha) | |
1740 | { | |
1741 | uint32_t len = 0; | |
1742 | ||
1743 | if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { | |
1744 | qla_printk(KERN_WARNING, ha, | |
1745 | "Failed to reserve selected regions (%s)\n", | |
1746 | pci_name(ha->pdev)); | |
1747 | goto iospace_error_exit; | |
1748 | } | |
1749 | ||
1750 | /* Use MMIO operations for all accesses. */ | |
1751 | if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { | |
1752 | qla_printk(KERN_ERR, ha, | |
1753 | "region #0 not an MMIO resource (%s), aborting\n", | |
1754 | pci_name(ha->pdev)); | |
1755 | goto iospace_error_exit; | |
1756 | } | |
1757 | ||
1758 | len = pci_resource_len(ha->pdev, 0); | |
1759 | ha->nx_pcibase = | |
1760 | (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); | |
1761 | if (!ha->nx_pcibase) { | |
1762 | qla_printk(KERN_ERR, ha, | |
1763 | "cannot remap pcibase MMIO (%s), aborting\n", | |
1764 | pci_name(ha->pdev)); | |
1765 | pci_release_regions(ha->pdev); | |
1766 | goto iospace_error_exit; | |
1767 | } | |
1768 | ||
1769 | /* Mapping of IO base pointer */ | |
1770 | ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase + | |
1771 | 0xbc000 + (ha->pdev->devfn << 11)); | |
1772 | ||
1773 | if (!ql2xdbwr) { | |
1774 | ha->nxdb_wr_ptr = | |
1775 | (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + | |
1776 | (ha->pdev->devfn << 12)), 4); | |
1777 | if (!ha->nxdb_wr_ptr) { | |
1778 | qla_printk(KERN_ERR, ha, | |
1779 | "cannot remap MMIO (%s), aborting\n", | |
1780 | pci_name(ha->pdev)); | |
1781 | pci_release_regions(ha->pdev); | |
1782 | goto iospace_error_exit; | |
1783 | } | |
1784 | ||
1785 | /* Mapping of IO base pointer, | |
1786 | * door bell read and write pointer | |
1787 | */ | |
1788 | ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + | |
1789 | (ha->pdev->devfn * 8); | |
1790 | } else { | |
1791 | ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? | |
1792 | QLA82XX_CAMRAM_DB1 : | |
1793 | QLA82XX_CAMRAM_DB2); | |
1794 | } | |
1795 | ||
1796 | ha->max_req_queues = ha->max_rsp_queues = 1; | |
1797 | ha->msix_count = ha->max_rsp_queues + 1; | |
1798 | return 0; | |
1799 | ||
1800 | iospace_error_exit: | |
1801 | return -ENOMEM; | |
1802 | } | |
1803 | ||
1804 | /* GS related functions */ | |
1805 | ||
1806 | /* Initialization related functions */ | |
1807 | ||
1808 | /** | |
1809 | * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. | |
1810 | * @ha: HA context | |
1811 | * | |
1812 | * Returns 0 on success. | |
1813 | */ | |
1814 | int | |
1815 | qla82xx_pci_config(scsi_qla_host_t *vha) | |
1816 | { | |
1817 | struct qla_hw_data *ha = vha->hw; | |
1818 | int ret; | |
1819 | ||
1820 | pci_set_master(ha->pdev); | |
1821 | ret = pci_set_mwi(ha->pdev); | |
1822 | ha->chip_revision = ha->pdev->revision; | |
1823 | return 0; | |
1824 | } | |
1825 | ||
1826 | /** | |
1827 | * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. | |
1828 | * @ha: HA context | |
1829 | * | |
1830 | * Returns 0 on success. | |
1831 | */ | |
1832 | void | |
1833 | qla82xx_reset_chip(scsi_qla_host_t *vha) | |
1834 | { | |
1835 | struct qla_hw_data *ha = vha->hw; | |
1836 | ha->isp_ops->disable_intrs(ha); | |
1837 | } | |
1838 | ||
1839 | void qla82xx_config_rings(struct scsi_qla_host *vha) | |
1840 | { | |
1841 | struct qla_hw_data *ha = vha->hw; | |
1842 | struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; | |
1843 | struct init_cb_81xx *icb; | |
1844 | struct req_que *req = ha->req_q_map[0]; | |
1845 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
1846 | ||
1847 | /* Setup ring parameters in initialization control block. */ | |
1848 | icb = (struct init_cb_81xx *)ha->init_cb; | |
1849 | icb->request_q_outpointer = __constant_cpu_to_le16(0); | |
1850 | icb->response_q_inpointer = __constant_cpu_to_le16(0); | |
1851 | icb->request_q_length = cpu_to_le16(req->length); | |
1852 | icb->response_q_length = cpu_to_le16(rsp->length); | |
1853 | icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); | |
1854 | icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); | |
1855 | icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); | |
1856 | icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); | |
1857 | ||
1858 | icb->version = 1; | |
1859 | icb->frame_payload_size = 2112; | |
1860 | icb->execution_throttle = 8; | |
1861 | icb->exchange_count = 128; | |
1862 | icb->login_retry_count = 8; | |
1863 | ||
1864 | WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); | |
1865 | WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); | |
1866 | WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); | |
1867 | } | |
1868 | ||
1869 | int qla82xx_fw_load_from_blob(struct qla_hw_data *ha) | |
1870 | { | |
1871 | u64 *ptr64; | |
1872 | u32 i, flashaddr, size; | |
1873 | __le64 data; | |
1874 | ||
1875 | size = (IMAGE_START - BOOTLD_START) / 8; | |
1876 | ||
1877 | ptr64 = (u64 *)&ha->hablob->fw->data[BOOTLD_START]; | |
1878 | flashaddr = BOOTLD_START; | |
1879 | ||
1880 | for (i = 0; i < size; i++) { | |
1881 | data = cpu_to_le64(ptr64[i]); | |
1882 | qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8); | |
1883 | flashaddr += 8; | |
1884 | } | |
1885 | ||
1886 | size = *(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]; | |
1887 | size = (__force u32)cpu_to_le32(size) / 8; | |
1888 | ptr64 = (u64 *)&ha->hablob->fw->data[IMAGE_START]; | |
1889 | flashaddr = FLASH_ADDR_START; | |
1890 | ||
1891 | for (i = 0; i < size; i++) { | |
1892 | data = cpu_to_le64(ptr64[i]); | |
1893 | ||
1894 | if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) | |
1895 | return -EIO; | |
1896 | flashaddr += 8; | |
1897 | } | |
1898 | ||
1899 | /* Write a magic value to CAMRAM register | |
1900 | * at a specified offset to indicate | |
1901 | * that all data is written and | |
1902 | * ready for firmware to initialize. | |
1903 | */ | |
1904 | qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), 0x12345678); | |
1905 | ||
1906 | if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { | |
1907 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); | |
1908 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); | |
1909 | } else | |
1910 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001d); | |
1911 | return 0; | |
1912 | } | |
1913 | ||
1914 | int qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) | |
1915 | { | |
1916 | u32 val = 0; | |
1917 | int retries = 60; | |
1918 | ||
1919 | do { | |
1920 | read_lock(&ha->hw_lock); | |
1921 | val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); | |
1922 | read_unlock(&ha->hw_lock); | |
1923 | ||
1924 | switch (val) { | |
1925 | case PHAN_INITIALIZE_COMPLETE: | |
1926 | case PHAN_INITIALIZE_ACK: | |
1927 | return QLA_SUCCESS; | |
1928 | case PHAN_INITIALIZE_FAILED: | |
1929 | break; | |
1930 | default: | |
1931 | break; | |
1932 | } | |
1933 | qla_printk(KERN_WARNING, ha, | |
1934 | "CRB_CMDPEG_STATE: 0x%x and retries: 0x%x\n", | |
1935 | val, retries); | |
1936 | ||
1937 | msleep(500); | |
1938 | ||
1939 | } while (--retries); | |
1940 | ||
1941 | qla_printk(KERN_INFO, ha, | |
1942 | "Cmd Peg initialization failed: 0x%x.\n", val); | |
1943 | ||
1944 | qla82xx_check_for_bad_spd(ha); | |
1945 | val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); | |
1946 | read_lock(&ha->hw_lock); | |
1947 | qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); | |
1948 | read_unlock(&ha->hw_lock); | |
1949 | return QLA_FUNCTION_FAILED; | |
1950 | } | |
1951 | ||
1952 | int qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) | |
1953 | { | |
1954 | u32 val = 0; | |
1955 | int retries = 60; | |
1956 | ||
1957 | do { | |
1958 | read_lock(&ha->hw_lock); | |
1959 | val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); | |
1960 | read_unlock(&ha->hw_lock); | |
1961 | ||
1962 | switch (val) { | |
1963 | case PHAN_INITIALIZE_COMPLETE: | |
1964 | case PHAN_INITIALIZE_ACK: | |
1965 | return QLA_SUCCESS; | |
1966 | case PHAN_INITIALIZE_FAILED: | |
1967 | break; | |
1968 | default: | |
1969 | break; | |
1970 | } | |
1971 | ||
1972 | qla_printk(KERN_WARNING, ha, | |
1973 | "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x\n", | |
1974 | val, retries); | |
1975 | ||
1976 | msleep(500); | |
1977 | ||
1978 | } while (--retries); | |
1979 | ||
1980 | qla_printk(KERN_INFO, ha, | |
1981 | "Rcv Peg initialization failed: 0x%x.\n", val); | |
1982 | read_lock(&ha->hw_lock); | |
1983 | qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); | |
1984 | read_unlock(&ha->hw_lock); | |
1985 | return QLA_FUNCTION_FAILED; | |
1986 | } | |
1987 | ||
1988 | /* ISR related functions */ | |
1989 | uint32_t qla82xx_isr_int_target_mask_enable[8] = { | |
1990 | ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1, | |
1991 | ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3, | |
1992 | ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5, | |
1993 | ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7 | |
1994 | }; | |
1995 | ||
1996 | uint32_t qla82xx_isr_int_target_status[8] = { | |
1997 | ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1, | |
1998 | ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3, | |
1999 | ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5, | |
2000 | ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7 | |
2001 | }; | |
2002 | ||
2003 | static struct qla82xx_legacy_intr_set legacy_intr[] = \ | |
2004 | QLA82XX_LEGACY_INTR_CONFIG; | |
2005 | ||
2006 | /* | |
2007 | * qla82xx_mbx_completion() - Process mailbox command completions. | |
2008 | * @ha: SCSI driver HA context | |
2009 | * @mb0: Mailbox0 register | |
2010 | */ | |
2011 | void | |
2012 | qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) | |
2013 | { | |
2014 | uint16_t cnt; | |
2015 | uint16_t __iomem *wptr; | |
2016 | struct qla_hw_data *ha = vha->hw; | |
2017 | struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; | |
2018 | wptr = (uint16_t __iomem *)®->mailbox_out[1]; | |
2019 | ||
2020 | /* Load return mailbox registers. */ | |
2021 | ha->flags.mbox_int = 1; | |
2022 | ha->mailbox_out[0] = mb0; | |
2023 | ||
2024 | for (cnt = 1; cnt < ha->mbx_count; cnt++) { | |
2025 | ha->mailbox_out[cnt] = RD_REG_WORD(wptr); | |
2026 | wptr++; | |
2027 | } | |
2028 | ||
2029 | if (ha->mcp) { | |
2030 | DEBUG3_11(printk(KERN_INFO "%s(%ld): " | |
2031 | "Got mailbox completion. cmd=%x.\n", | |
2032 | __func__, vha->host_no, ha->mcp->mb[0])); | |
2033 | } else { | |
2034 | qla_printk(KERN_INFO, ha, | |
2035 | "%s(%ld): MBX pointer ERROR!\n", | |
2036 | __func__, vha->host_no); | |
2037 | } | |
2038 | } | |
2039 | ||
2040 | /* | |
2041 | * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. | |
2042 | * @irq: | |
2043 | * @dev_id: SCSI driver HA context | |
2044 | * @regs: | |
2045 | * | |
2046 | * Called by system whenever the host adapter generates an interrupt. | |
2047 | * | |
2048 | * Returns handled flag. | |
2049 | */ | |
2050 | irqreturn_t | |
2051 | qla82xx_intr_handler(int irq, void *dev_id) | |
2052 | { | |
2053 | scsi_qla_host_t *vha; | |
2054 | struct qla_hw_data *ha; | |
2055 | struct rsp_que *rsp; | |
2056 | struct device_reg_82xx __iomem *reg; | |
2057 | int status = 0, status1 = 0; | |
2058 | unsigned long flags; | |
2059 | unsigned long iter; | |
2060 | uint32_t stat; | |
2061 | uint16_t mb[4]; | |
2062 | ||
2063 | rsp = (struct rsp_que *) dev_id; | |
2064 | if (!rsp) { | |
2065 | printk(KERN_INFO | |
2066 | "%s(): NULL response queue pointer\n", __func__); | |
2067 | return IRQ_NONE; | |
2068 | } | |
2069 | ha = rsp->hw; | |
2070 | ||
2071 | if (!ha->flags.msi_enabled) { | |
2072 | status = qla82xx_rd_32(ha, ISR_INT_VECTOR); | |
2073 | if (!(status & ha->nx_legacy_intr.int_vec_bit)) | |
2074 | return IRQ_NONE; | |
2075 | ||
2076 | status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); | |
2077 | if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) | |
2078 | return IRQ_NONE; | |
2079 | } | |
2080 | ||
2081 | /* clear the interrupt */ | |
2082 | qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); | |
2083 | ||
2084 | /* read twice to ensure write is flushed */ | |
2085 | qla82xx_rd_32(ha, ISR_INT_VECTOR); | |
2086 | qla82xx_rd_32(ha, ISR_INT_VECTOR); | |
2087 | ||
2088 | reg = &ha->iobase->isp82; | |
2089 | ||
2090 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
2091 | vha = pci_get_drvdata(ha->pdev); | |
2092 | for (iter = 1; iter--; ) { | |
2093 | ||
2094 | if (RD_REG_DWORD(®->host_int)) { | |
2095 | stat = RD_REG_DWORD(®->host_status); | |
2096 | if (stat & HSRX_RISC_PAUSED) { | |
2097 | if (pci_channel_offline(ha->pdev)) | |
2098 | break; | |
2099 | ||
2100 | qla_printk(KERN_INFO, ha, "RISC paused\n"); | |
2101 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
2102 | qla2xxx_wake_dpc(vha); | |
2103 | break; | |
2104 | } else if ((stat & HSRX_RISC_INT) == 0) | |
2105 | break; | |
2106 | ||
2107 | switch (stat & 0xff) { | |
2108 | case 0x1: | |
2109 | case 0x2: | |
2110 | case 0x10: | |
2111 | case 0x11: | |
2112 | qla82xx_mbx_completion(vha, MSW(stat)); | |
2113 | status |= MBX_INTERRUPT; | |
2114 | break; | |
2115 | case 0x12: | |
2116 | mb[0] = MSW(stat); | |
2117 | mb[1] = RD_REG_WORD(®->mailbox_out[1]); | |
2118 | mb[2] = RD_REG_WORD(®->mailbox_out[2]); | |
2119 | mb[3] = RD_REG_WORD(®->mailbox_out[3]); | |
2120 | qla2x00_async_event(vha, rsp, mb); | |
2121 | break; | |
2122 | case 0x13: | |
2123 | qla24xx_process_response_queue(vha, rsp); | |
2124 | break; | |
2125 | default: | |
2126 | DEBUG2(printk("scsi(%ld): " | |
2127 | " Unrecognized interrupt type (%d).\n", | |
2128 | vha->host_no, stat & 0xff)); | |
2129 | break; | |
2130 | } | |
2131 | } | |
2132 | WRT_REG_DWORD(®->host_int, 0); | |
2133 | } | |
2134 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
2135 | if (!ha->flags.msi_enabled) | |
2136 | qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); | |
2137 | ||
2138 | #ifdef QL_DEBUG_LEVEL_17 | |
2139 | if (!irq && ha->flags.eeh_busy) | |
2140 | qla_printk(KERN_WARNING, ha, | |
2141 | "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n", | |
2142 | status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); | |
2143 | #endif | |
2144 | ||
2145 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && | |
2146 | (status & MBX_INTERRUPT) && ha->flags.mbox_int) { | |
2147 | set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
2148 | complete(&ha->mbx_intr_comp); | |
2149 | } | |
2150 | return IRQ_HANDLED; | |
2151 | } | |
2152 | ||
2153 | irqreturn_t | |
2154 | qla82xx_msix_default(int irq, void *dev_id) | |
2155 | { | |
2156 | scsi_qla_host_t *vha; | |
2157 | struct qla_hw_data *ha; | |
2158 | struct rsp_que *rsp; | |
2159 | struct device_reg_82xx __iomem *reg; | |
2160 | int status = 0; | |
2161 | unsigned long flags; | |
2162 | uint32_t stat; | |
2163 | uint16_t mb[4]; | |
2164 | ||
2165 | rsp = (struct rsp_que *) dev_id; | |
2166 | if (!rsp) { | |
2167 | printk(KERN_INFO | |
2168 | "%s(): NULL response queue pointer\n", __func__); | |
2169 | return IRQ_NONE; | |
2170 | } | |
2171 | ha = rsp->hw; | |
2172 | ||
2173 | reg = &ha->iobase->isp82; | |
2174 | ||
2175 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
2176 | vha = pci_get_drvdata(ha->pdev); | |
2177 | do { | |
2178 | if (RD_REG_DWORD(®->host_int)) { | |
2179 | stat = RD_REG_DWORD(®->host_status); | |
2180 | if (stat & HSRX_RISC_PAUSED) { | |
2181 | if (pci_channel_offline(ha->pdev)) | |
2182 | break; | |
2183 | ||
2184 | qla_printk(KERN_INFO, ha, "RISC paused\n"); | |
2185 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
2186 | qla2xxx_wake_dpc(vha); | |
2187 | break; | |
2188 | } else if ((stat & HSRX_RISC_INT) == 0) | |
2189 | break; | |
2190 | ||
2191 | switch (stat & 0xff) { | |
2192 | case 0x1: | |
2193 | case 0x2: | |
2194 | case 0x10: | |
2195 | case 0x11: | |
2196 | qla82xx_mbx_completion(vha, MSW(stat)); | |
2197 | status |= MBX_INTERRUPT; | |
2198 | break; | |
2199 | case 0x12: | |
2200 | mb[0] = MSW(stat); | |
2201 | mb[1] = RD_REG_WORD(®->mailbox_out[1]); | |
2202 | mb[2] = RD_REG_WORD(®->mailbox_out[2]); | |
2203 | mb[3] = RD_REG_WORD(®->mailbox_out[3]); | |
2204 | qla2x00_async_event(vha, rsp, mb); | |
2205 | break; | |
2206 | case 0x13: | |
2207 | qla24xx_process_response_queue(vha, rsp); | |
2208 | break; | |
2209 | default: | |
2210 | DEBUG2(printk("scsi(%ld): " | |
2211 | " Unrecognized interrupt type (%d).\n", | |
2212 | vha->host_no, stat & 0xff)); | |
2213 | break; | |
2214 | } | |
2215 | } | |
2216 | WRT_REG_DWORD(®->host_int, 0); | |
2217 | } while (0); | |
2218 | ||
2219 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
2220 | ||
2221 | #ifdef QL_DEBUG_LEVEL_17 | |
2222 | if (!irq && ha->flags.eeh_busy) | |
2223 | qla_printk(KERN_WARNING, ha, | |
2224 | "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n", | |
2225 | status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); | |
2226 | #endif | |
2227 | ||
2228 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && | |
2229 | (status & MBX_INTERRUPT) && ha->flags.mbox_int) { | |
2230 | set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
2231 | complete(&ha->mbx_intr_comp); | |
2232 | } | |
2233 | return IRQ_HANDLED; | |
2234 | } | |
2235 | ||
2236 | irqreturn_t | |
2237 | qla82xx_msix_rsp_q(int irq, void *dev_id) | |
2238 | { | |
2239 | scsi_qla_host_t *vha; | |
2240 | struct qla_hw_data *ha; | |
2241 | struct rsp_que *rsp; | |
2242 | struct device_reg_82xx __iomem *reg; | |
2243 | ||
2244 | rsp = (struct rsp_que *) dev_id; | |
2245 | if (!rsp) { | |
2246 | printk(KERN_INFO | |
2247 | "%s(): NULL response queue pointer\n", __func__); | |
2248 | return IRQ_NONE; | |
2249 | } | |
2250 | ||
2251 | ha = rsp->hw; | |
2252 | reg = &ha->iobase->isp82; | |
2253 | spin_lock_irq(&ha->hardware_lock); | |
2254 | vha = pci_get_drvdata(ha->pdev); | |
2255 | qla24xx_process_response_queue(vha, rsp); | |
2256 | WRT_REG_DWORD(®->host_int, 0); | |
2257 | spin_unlock_irq(&ha->hardware_lock); | |
2258 | return IRQ_HANDLED; | |
2259 | } | |
2260 | ||
2261 | void | |
2262 | qla82xx_poll(int irq, void *dev_id) | |
2263 | { | |
2264 | scsi_qla_host_t *vha; | |
2265 | struct qla_hw_data *ha; | |
2266 | struct rsp_que *rsp; | |
2267 | struct device_reg_82xx __iomem *reg; | |
2268 | int status = 0; | |
2269 | uint32_t stat; | |
2270 | uint16_t mb[4]; | |
2271 | unsigned long flags; | |
2272 | ||
2273 | rsp = (struct rsp_que *) dev_id; | |
2274 | if (!rsp) { | |
2275 | printk(KERN_INFO | |
2276 | "%s(): NULL response queue pointer\n", __func__); | |
2277 | return; | |
2278 | } | |
2279 | ha = rsp->hw; | |
2280 | ||
2281 | reg = &ha->iobase->isp82; | |
2282 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
2283 | vha = pci_get_drvdata(ha->pdev); | |
2284 | ||
2285 | if (RD_REG_DWORD(®->host_int)) { | |
2286 | stat = RD_REG_DWORD(®->host_status); | |
2287 | switch (stat & 0xff) { | |
2288 | case 0x1: | |
2289 | case 0x2: | |
2290 | case 0x10: | |
2291 | case 0x11: | |
2292 | qla82xx_mbx_completion(vha, MSW(stat)); | |
2293 | status |= MBX_INTERRUPT; | |
2294 | break; | |
2295 | case 0x12: | |
2296 | mb[0] = MSW(stat); | |
2297 | mb[1] = RD_REG_WORD(®->mailbox_out[1]); | |
2298 | mb[2] = RD_REG_WORD(®->mailbox_out[2]); | |
2299 | mb[3] = RD_REG_WORD(®->mailbox_out[3]); | |
2300 | qla2x00_async_event(vha, rsp, mb); | |
2301 | break; | |
2302 | case 0x13: | |
2303 | qla24xx_process_response_queue(vha, rsp); | |
2304 | break; | |
2305 | default: | |
2306 | DEBUG2(printk("scsi(%ld): Unrecognized interrupt type " | |
2307 | "(%d).\n", | |
2308 | vha->host_no, stat & 0xff)); | |
2309 | break; | |
2310 | } | |
2311 | } | |
2312 | WRT_REG_DWORD(®->host_int, 0); | |
2313 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
2314 | } | |
2315 | ||
2316 | void | |
2317 | qla82xx_enable_intrs(struct qla_hw_data *ha) | |
2318 | { | |
2319 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); | |
2320 | qla82xx_mbx_intr_enable(vha); | |
2321 | spin_lock_irq(&ha->hardware_lock); | |
2322 | qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); | |
2323 | spin_unlock_irq(&ha->hardware_lock); | |
2324 | ha->interrupts_on = 1; | |
2325 | } | |
2326 | ||
2327 | void | |
2328 | qla82xx_disable_intrs(struct qla_hw_data *ha) | |
2329 | { | |
2330 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); | |
2331 | qla82xx_mbx_intr_disable(vha); | |
2332 | spin_lock_irq(&ha->hardware_lock); | |
2333 | qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); | |
2334 | spin_unlock_irq(&ha->hardware_lock); | |
2335 | ha->interrupts_on = 0; | |
2336 | } | |
2337 | ||
2338 | void qla82xx_init_flags(struct qla_hw_data *ha) | |
2339 | { | |
2340 | struct qla82xx_legacy_intr_set *nx_legacy_intr; | |
2341 | ||
2342 | /* ISP 8021 initializations */ | |
2343 | rwlock_init(&ha->hw_lock); | |
2344 | ha->qdr_sn_window = -1; | |
2345 | ha->ddr_mn_window = -1; | |
2346 | ha->curr_window = 255; | |
2347 | ha->portnum = PCI_FUNC(ha->pdev->devfn); | |
2348 | nx_legacy_intr = &legacy_intr[ha->portnum]; | |
2349 | ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; | |
2350 | ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; | |
2351 | ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; | |
2352 | ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; | |
2353 | } | |
2354 | ||
2355 | static inline void | |
2356 | qla82xx_set_drv_active(scsi_qla_host_t *vha) | |
2357 | { | |
2358 | uint32_t drv_active; | |
2359 | struct qla_hw_data *ha = vha->hw; | |
2360 | ||
2361 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
2362 | ||
2363 | /* If reset value is all FF's, initialize DRV_ACTIVE */ | |
2364 | if (drv_active == 0xffffffff) { | |
2365 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 0); | |
2366 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
2367 | } | |
2368 | drv_active |= (1 << (ha->portnum * 4)); | |
2369 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); | |
2370 | } | |
2371 | ||
2372 | inline void | |
2373 | qla82xx_clear_drv_active(struct qla_hw_data *ha) | |
2374 | { | |
2375 | uint32_t drv_active; | |
2376 | ||
2377 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
2378 | drv_active &= ~(1 << (ha->portnum * 4)); | |
2379 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); | |
2380 | } | |
2381 | ||
2382 | static inline int | |
2383 | qla82xx_need_reset(struct qla_hw_data *ha) | |
2384 | { | |
2385 | uint32_t drv_state; | |
2386 | int rval; | |
2387 | ||
2388 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | |
2389 | rval = drv_state & (1 << (ha->portnum * 4)); | |
2390 | return rval; | |
2391 | } | |
2392 | ||
2393 | static inline void | |
2394 | qla82xx_set_rst_ready(struct qla_hw_data *ha) | |
2395 | { | |
2396 | uint32_t drv_state; | |
2397 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); | |
2398 | ||
2399 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | |
2400 | ||
2401 | /* If reset value is all FF's, initialize DRV_STATE */ | |
2402 | if (drv_state == 0xffffffff) { | |
2403 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); | |
2404 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | |
2405 | } | |
2406 | drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); | |
2407 | qla_printk(KERN_INFO, ha, | |
2408 | "%s(%ld):drv_state = 0x%x\n", | |
2409 | __func__, vha->host_no, drv_state); | |
2410 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); | |
2411 | } | |
2412 | ||
2413 | static inline void | |
2414 | qla82xx_clear_rst_ready(struct qla_hw_data *ha) | |
2415 | { | |
2416 | uint32_t drv_state; | |
2417 | ||
2418 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | |
2419 | drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); | |
2420 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); | |
2421 | } | |
2422 | ||
2423 | static inline void | |
2424 | qla82xx_set_qsnt_ready(struct qla_hw_data *ha) | |
2425 | { | |
2426 | uint32_t qsnt_state; | |
2427 | ||
2428 | qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | |
2429 | qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); | |
2430 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); | |
2431 | } | |
2432 | ||
2433 | int qla82xx_load_fw(scsi_qla_host_t *vha) | |
2434 | { | |
2435 | int rst; | |
2436 | struct fw_blob *blob; | |
2437 | struct qla_hw_data *ha = vha->hw; | |
2438 | ||
2439 | /* Put both the PEG CMD and RCV PEG to default state | |
2440 | * of 0 before resetting the hardware | |
2441 | */ | |
2442 | qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); | |
2443 | qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); | |
2444 | ||
2445 | if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { | |
2446 | qla_printk(KERN_ERR, ha, | |
2447 | "%s: Error during CRB Initialization\n", __func__); | |
2448 | return QLA_FUNCTION_FAILED; | |
2449 | } | |
2450 | udelay(500); | |
2451 | ||
2452 | /* Bring QM and CAMRAM out of reset */ | |
2453 | rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); | |
2454 | rst &= ~((1 << 28) | (1 << 24)); | |
2455 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); | |
2456 | ||
2457 | /* | |
2458 | * FW Load priority: | |
2459 | * 1) Operational firmware residing in flash. | |
2460 | * 2) Firmware via request-firmware interface (.bin file). | |
2461 | */ | |
2462 | if (ql2xfwloadbin == 2) | |
2463 | goto try_blob_fw; | |
2464 | ||
2465 | qla_printk(KERN_INFO, ha, | |
2466 | "Attempting to load firmware from flash\n"); | |
2467 | ||
2468 | if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { | |
2469 | qla_printk(KERN_ERR, ha, | |
2470 | "Firmware loaded successfully from flash\n"); | |
2471 | return QLA_SUCCESS; | |
2472 | } | |
2473 | try_blob_fw: | |
2474 | qla_printk(KERN_INFO, ha, | |
2475 | "Attempting to load firmware from blob\n"); | |
2476 | ||
2477 | /* Load firmware blob. */ | |
2478 | blob = ha->hablob = qla2x00_request_firmware(vha); | |
2479 | if (!blob) { | |
2480 | qla_printk(KERN_ERR, ha, | |
2481 | "Firmware image not present.\n"); | |
2482 | goto fw_load_failed; | |
2483 | } | |
2484 | ||
2485 | if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { | |
2486 | qla_printk(KERN_ERR, ha, | |
2487 | "%s: Firmware loaded successfully " | |
2488 | " from binary blob\n", __func__); | |
2489 | return QLA_SUCCESS; | |
2490 | } else { | |
2491 | qla_printk(KERN_ERR, ha, | |
2492 | "Firmware load failed from binary blob\n"); | |
2493 | blob->fw = NULL; | |
2494 | blob = NULL; | |
2495 | goto fw_load_failed; | |
2496 | } | |
2497 | return QLA_SUCCESS; | |
2498 | ||
2499 | fw_load_failed: | |
2500 | return QLA_FUNCTION_FAILED; | |
2501 | } | |
2502 | ||
2503 | static int | |
2504 | qla82xx_start_firmware(scsi_qla_host_t *vha) | |
2505 | { | |
2506 | int pcie_cap; | |
2507 | uint16_t lnk; | |
2508 | struct qla_hw_data *ha = vha->hw; | |
2509 | ||
2510 | /* scrub dma mask expansion register */ | |
2511 | qla82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555); | |
2512 | ||
2513 | /* Overwrite stale initialization register values */ | |
2514 | qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); | |
2515 | qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); | |
2516 | ||
2517 | if (qla82xx_load_fw(vha) != QLA_SUCCESS) { | |
2518 | qla_printk(KERN_INFO, ha, | |
2519 | "%s: Error trying to start fw!\n", __func__); | |
2520 | return QLA_FUNCTION_FAILED; | |
2521 | } | |
2522 | ||
2523 | /* Handshake with the card before we register the devices. */ | |
2524 | if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { | |
2525 | qla_printk(KERN_INFO, ha, | |
2526 | "%s: Error during card handshake!\n", __func__); | |
2527 | return QLA_FUNCTION_FAILED; | |
2528 | } | |
2529 | ||
2530 | /* Negotiated Link width */ | |
2531 | pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); | |
2532 | pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); | |
2533 | ha->link_width = (lnk >> 4) & 0x3f; | |
2534 | ||
2535 | /* Synchronize with Receive peg */ | |
2536 | return qla82xx_check_rcvpeg_state(ha); | |
2537 | } | |
2538 | ||
2539 | static inline int | |
2540 | qla2xx_build_scsi_type_6_iocbs(srb_t *sp, struct cmd_type_6 *cmd_pkt, | |
2541 | uint16_t tot_dsds) | |
2542 | { | |
2543 | uint32_t *cur_dsd = NULL; | |
2544 | scsi_qla_host_t *vha; | |
2545 | struct qla_hw_data *ha; | |
2546 | struct scsi_cmnd *cmd; | |
2547 | struct scatterlist *cur_seg; | |
2548 | uint32_t *dsd_seg; | |
2549 | void *next_dsd; | |
2550 | uint8_t avail_dsds; | |
2551 | uint8_t first_iocb = 1; | |
2552 | uint32_t dsd_list_len; | |
2553 | struct dsd_dma *dsd_ptr; | |
2554 | struct ct6_dsd *ctx; | |
2555 | ||
2556 | cmd = sp->cmd; | |
2557 | ||
2558 | /* Update entry type to indicate Command Type 3 IOCB */ | |
2559 | *((uint32_t *)(&cmd_pkt->entry_type)) = | |
2560 | __constant_cpu_to_le32(COMMAND_TYPE_6); | |
2561 | ||
2562 | /* No data transfer */ | |
2563 | if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) { | |
2564 | cmd_pkt->byte_count = __constant_cpu_to_le32(0); | |
2565 | return 0; | |
2566 | } | |
2567 | ||
2568 | vha = sp->fcport->vha; | |
2569 | ha = vha->hw; | |
2570 | ||
2571 | /* Set transfer direction */ | |
2572 | if (cmd->sc_data_direction == DMA_TO_DEVICE) { | |
2573 | cmd_pkt->control_flags = | |
2574 | __constant_cpu_to_le16(CF_WRITE_DATA); | |
2575 | ha->qla_stats.output_bytes += scsi_bufflen(cmd); | |
2576 | } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) { | |
2577 | cmd_pkt->control_flags = | |
2578 | __constant_cpu_to_le16(CF_READ_DATA); | |
2579 | ha->qla_stats.input_bytes += scsi_bufflen(cmd); | |
2580 | } | |
2581 | ||
2582 | cur_seg = scsi_sglist(cmd); | |
2583 | ctx = sp->ctx; | |
2584 | ||
2585 | while (tot_dsds) { | |
2586 | avail_dsds = (tot_dsds > QLA_DSDS_PER_IOCB) ? | |
2587 | QLA_DSDS_PER_IOCB : tot_dsds; | |
2588 | tot_dsds -= avail_dsds; | |
2589 | dsd_list_len = (avail_dsds + 1) * QLA_DSD_SIZE; | |
2590 | ||
2591 | dsd_ptr = list_first_entry(&ha->gbl_dsd_list, | |
2592 | struct dsd_dma, list); | |
2593 | next_dsd = dsd_ptr->dsd_addr; | |
2594 | list_del(&dsd_ptr->list); | |
2595 | ha->gbl_dsd_avail--; | |
2596 | list_add_tail(&dsd_ptr->list, &ctx->dsd_list); | |
2597 | ctx->dsd_use_cnt++; | |
2598 | ha->gbl_dsd_inuse++; | |
2599 | ||
2600 | if (first_iocb) { | |
2601 | first_iocb = 0; | |
2602 | dsd_seg = (uint32_t *)&cmd_pkt->fcp_data_dseg_address; | |
2603 | *dsd_seg++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); | |
2604 | *dsd_seg++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); | |
2605 | *dsd_seg++ = dsd_list_len; | |
2606 | } else { | |
2607 | *cur_dsd++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); | |
2608 | *cur_dsd++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); | |
2609 | *cur_dsd++ = dsd_list_len; | |
2610 | } | |
2611 | cur_dsd = (uint32_t *)next_dsd; | |
2612 | while (avail_dsds) { | |
2613 | dma_addr_t sle_dma; | |
2614 | ||
2615 | sle_dma = sg_dma_address(cur_seg); | |
2616 | *cur_dsd++ = cpu_to_le32(LSD(sle_dma)); | |
2617 | *cur_dsd++ = cpu_to_le32(MSD(sle_dma)); | |
2618 | *cur_dsd++ = cpu_to_le32(sg_dma_len(cur_seg)); | |
2619 | cur_seg++; | |
2620 | avail_dsds--; | |
2621 | } | |
2622 | } | |
2623 | ||
2624 | /* Null termination */ | |
2625 | *cur_dsd++ = 0; | |
2626 | *cur_dsd++ = 0; | |
2627 | *cur_dsd++ = 0; | |
2628 | cmd_pkt->control_flags |= CF_DATA_SEG_DESCR_ENABLE; | |
2629 | return 0; | |
2630 | } | |
2631 | ||
2632 | /* | |
2633 | * qla82xx_calc_dsd_lists() - Determine number of DSD list required | |
2634 | * for Command Type 6. | |
2635 | * | |
2636 | * @dsds: number of data segment decriptors needed | |
2637 | * | |
2638 | * Returns the number of dsd list needed to store @dsds. | |
2639 | */ | |
2640 | inline uint16_t | |
2641 | qla82xx_calc_dsd_lists(uint16_t dsds) | |
2642 | { | |
2643 | uint16_t dsd_lists = 0; | |
2644 | ||
2645 | dsd_lists = (dsds/QLA_DSDS_PER_IOCB); | |
2646 | if (dsds % QLA_DSDS_PER_IOCB) | |
2647 | dsd_lists++; | |
2648 | return dsd_lists; | |
2649 | } | |
2650 | ||
2651 | /* | |
2652 | * qla82xx_start_scsi() - Send a SCSI command to the ISP | |
2653 | * @sp: command to send to the ISP | |
2654 | * | |
2655 | * Returns non-zero if a failure occured, else zero. | |
2656 | */ | |
2657 | int | |
2658 | qla82xx_start_scsi(srb_t *sp) | |
2659 | { | |
2660 | int ret, nseg; | |
2661 | unsigned long flags; | |
2662 | struct scsi_cmnd *cmd; | |
2663 | uint32_t *clr_ptr; | |
2664 | uint32_t index; | |
2665 | uint32_t handle; | |
2666 | uint16_t cnt; | |
2667 | uint16_t req_cnt; | |
2668 | uint16_t tot_dsds; | |
2669 | struct device_reg_82xx __iomem *reg; | |
2670 | uint32_t dbval; | |
2671 | uint32_t *fcp_dl; | |
2672 | uint8_t additional_cdb_len; | |
2673 | struct ct6_dsd *ctx; | |
2674 | struct scsi_qla_host *vha = sp->fcport->vha; | |
2675 | struct qla_hw_data *ha = vha->hw; | |
2676 | struct req_que *req = NULL; | |
2677 | struct rsp_que *rsp = NULL; | |
2678 | ||
2679 | /* Setup device pointers. */ | |
2680 | ret = 0; | |
2681 | reg = &ha->iobase->isp82; | |
2682 | cmd = sp->cmd; | |
2683 | req = vha->req; | |
2684 | rsp = ha->rsp_q_map[0]; | |
2685 | ||
2686 | /* So we know we haven't pci_map'ed anything yet */ | |
2687 | tot_dsds = 0; | |
2688 | ||
2689 | dbval = 0x04 | (ha->portnum << 5); | |
2690 | ||
2691 | /* Send marker if required */ | |
2692 | if (vha->marker_needed != 0) { | |
2693 | if (qla2x00_marker(vha, req, | |
2694 | rsp, 0, 0, MK_SYNC_ALL) != QLA_SUCCESS) | |
2695 | return QLA_FUNCTION_FAILED; | |
2696 | vha->marker_needed = 0; | |
2697 | } | |
2698 | ||
2699 | /* Acquire ring specific lock */ | |
2700 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
2701 | ||
2702 | /* Check for room in outstanding command list. */ | |
2703 | handle = req->current_outstanding_cmd; | |
2704 | for (index = 1; index < MAX_OUTSTANDING_COMMANDS; index++) { | |
2705 | handle++; | |
2706 | if (handle == MAX_OUTSTANDING_COMMANDS) | |
2707 | handle = 1; | |
2708 | if (!req->outstanding_cmds[handle]) | |
2709 | break; | |
2710 | } | |
2711 | if (index == MAX_OUTSTANDING_COMMANDS) | |
2712 | goto queuing_error; | |
2713 | ||
2714 | /* Map the sg table so we have an accurate count of sg entries needed */ | |
2715 | if (scsi_sg_count(cmd)) { | |
2716 | nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd), | |
2717 | scsi_sg_count(cmd), cmd->sc_data_direction); | |
2718 | if (unlikely(!nseg)) | |
2719 | goto queuing_error; | |
2720 | } else | |
2721 | nseg = 0; | |
2722 | ||
2723 | tot_dsds = nseg; | |
2724 | ||
2725 | if (tot_dsds > ql2xshiftctondsd) { | |
2726 | struct cmd_type_6 *cmd_pkt; | |
2727 | uint16_t more_dsd_lists = 0; | |
2728 | struct dsd_dma *dsd_ptr; | |
2729 | uint16_t i; | |
2730 | ||
2731 | more_dsd_lists = qla82xx_calc_dsd_lists(tot_dsds); | |
2732 | if ((more_dsd_lists + ha->gbl_dsd_inuse) >= NUM_DSD_CHAIN) | |
2733 | goto queuing_error; | |
2734 | ||
2735 | if (more_dsd_lists <= ha->gbl_dsd_avail) | |
2736 | goto sufficient_dsds; | |
2737 | else | |
2738 | more_dsd_lists -= ha->gbl_dsd_avail; | |
2739 | ||
2740 | for (i = 0; i < more_dsd_lists; i++) { | |
2741 | dsd_ptr = kzalloc(sizeof(struct dsd_dma), GFP_ATOMIC); | |
2742 | if (!dsd_ptr) | |
2743 | goto queuing_error; | |
2744 | ||
2745 | dsd_ptr->dsd_addr = dma_pool_alloc(ha->dl_dma_pool, | |
2746 | GFP_ATOMIC, &dsd_ptr->dsd_list_dma); | |
2747 | if (!dsd_ptr->dsd_addr) { | |
2748 | kfree(dsd_ptr); | |
2749 | goto queuing_error; | |
2750 | } | |
2751 | list_add_tail(&dsd_ptr->list, &ha->gbl_dsd_list); | |
2752 | ha->gbl_dsd_avail++; | |
2753 | } | |
2754 | ||
2755 | sufficient_dsds: | |
2756 | req_cnt = 1; | |
2757 | ||
2758 | ctx = sp->ctx = mempool_alloc(ha->ctx_mempool, GFP_ATOMIC); | |
2759 | if (!sp->ctx) { | |
2760 | DEBUG(printk(KERN_INFO | |
2761 | "%s(%ld): failed to allocate" | |
2762 | " ctx.\n", __func__, vha->host_no)); | |
2763 | goto queuing_error; | |
2764 | } | |
2765 | memset(ctx, 0, sizeof(struct ct6_dsd)); | |
2766 | ctx->fcp_cmnd = dma_pool_alloc(ha->fcp_cmnd_dma_pool, | |
2767 | GFP_ATOMIC, &ctx->fcp_cmnd_dma); | |
2768 | if (!ctx->fcp_cmnd) { | |
2769 | DEBUG2_3(printk("%s(%ld): failed to allocate" | |
2770 | " fcp_cmnd.\n", __func__, vha->host_no)); | |
2771 | goto queuing_error_fcp_cmnd; | |
2772 | } | |
2773 | ||
2774 | /* Initialize the DSD list and dma handle */ | |
2775 | INIT_LIST_HEAD(&ctx->dsd_list); | |
2776 | ctx->dsd_use_cnt = 0; | |
2777 | ||
2778 | if (cmd->cmd_len > 16) { | |
2779 | additional_cdb_len = cmd->cmd_len - 16; | |
2780 | if ((cmd->cmd_len % 4) != 0) { | |
2781 | /* SCSI command bigger than 16 bytes must be | |
2782 | * multiple of 4 | |
2783 | */ | |
2784 | goto queuing_error_fcp_cmnd; | |
2785 | } | |
2786 | ctx->fcp_cmnd_len = 12 + cmd->cmd_len + 4; | |
2787 | } else { | |
2788 | additional_cdb_len = 0; | |
2789 | ctx->fcp_cmnd_len = 12 + 16 + 4; | |
2790 | } | |
2791 | ||
2792 | cmd_pkt = (struct cmd_type_6 *)req->ring_ptr; | |
2793 | cmd_pkt->handle = MAKE_HANDLE(req->id, handle); | |
2794 | ||
2795 | /* Zero out remaining portion of packet. */ | |
2796 | /* tagged queuing modifier -- default is TSK_SIMPLE (0). */ | |
2797 | clr_ptr = (uint32_t *)cmd_pkt + 2; | |
2798 | memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); | |
2799 | cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); | |
2800 | ||
2801 | /* Set NPORT-ID and LUN number*/ | |
2802 | cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); | |
2803 | cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; | |
2804 | cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; | |
2805 | cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; | |
2806 | cmd_pkt->vp_index = sp->fcport->vp_idx; | |
2807 | ||
2808 | /* Build IOCB segments */ | |
2809 | if (qla2xx_build_scsi_type_6_iocbs(sp, cmd_pkt, tot_dsds)) | |
2810 | goto queuing_error_fcp_cmnd; | |
2811 | ||
2812 | int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); | |
2813 | ||
2814 | /* build FCP_CMND IU */ | |
2815 | memset(ctx->fcp_cmnd, 0, sizeof(struct fcp_cmnd)); | |
2816 | int_to_scsilun(sp->cmd->device->lun, &ctx->fcp_cmnd->lun); | |
2817 | ctx->fcp_cmnd->additional_cdb_len = additional_cdb_len; | |
2818 | ||
2819 | if (cmd->sc_data_direction == DMA_TO_DEVICE) | |
2820 | ctx->fcp_cmnd->additional_cdb_len |= 1; | |
2821 | else if (cmd->sc_data_direction == DMA_FROM_DEVICE) | |
2822 | ctx->fcp_cmnd->additional_cdb_len |= 2; | |
2823 | ||
2824 | memcpy(ctx->fcp_cmnd->cdb, cmd->cmnd, cmd->cmd_len); | |
2825 | ||
2826 | fcp_dl = (uint32_t *)(ctx->fcp_cmnd->cdb + 16 + | |
2827 | additional_cdb_len); | |
2828 | *fcp_dl = htonl((uint32_t)scsi_bufflen(cmd)); | |
2829 | ||
2830 | cmd_pkt->fcp_cmnd_dseg_len = cpu_to_le16(ctx->fcp_cmnd_len); | |
2831 | cmd_pkt->fcp_cmnd_dseg_address[0] = | |
2832 | cpu_to_le32(LSD(ctx->fcp_cmnd_dma)); | |
2833 | cmd_pkt->fcp_cmnd_dseg_address[1] = | |
2834 | cpu_to_le32(MSD(ctx->fcp_cmnd_dma)); | |
2835 | ||
2836 | sp->flags |= SRB_FCP_CMND_DMA_VALID; | |
2837 | cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); | |
2838 | /* Set total data segment count. */ | |
2839 | cmd_pkt->entry_count = (uint8_t)req_cnt; | |
2840 | /* Specify response queue number where | |
2841 | * completion should happen | |
2842 | */ | |
2843 | cmd_pkt->entry_status = (uint8_t) rsp->id; | |
2844 | } else { | |
2845 | struct cmd_type_7 *cmd_pkt; | |
2846 | req_cnt = qla24xx_calc_iocbs(tot_dsds); | |
2847 | if (req->cnt < (req_cnt + 2)) { | |
2848 | cnt = (uint16_t)RD_REG_DWORD_RELAXED( | |
2849 | ®->req_q_out[0]); | |
2850 | if (req->ring_index < cnt) | |
2851 | req->cnt = cnt - req->ring_index; | |
2852 | else | |
2853 | req->cnt = req->length - | |
2854 | (req->ring_index - cnt); | |
2855 | } | |
2856 | if (req->cnt < (req_cnt + 2)) | |
2857 | goto queuing_error; | |
2858 | ||
2859 | cmd_pkt = (struct cmd_type_7 *)req->ring_ptr; | |
2860 | cmd_pkt->handle = MAKE_HANDLE(req->id, handle); | |
2861 | ||
2862 | /* Zero out remaining portion of packet. */ | |
2863 | /* tagged queuing modifier -- default is TSK_SIMPLE (0).*/ | |
2864 | clr_ptr = (uint32_t *)cmd_pkt + 2; | |
2865 | memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); | |
2866 | cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); | |
2867 | ||
2868 | /* Set NPORT-ID and LUN number*/ | |
2869 | cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); | |
2870 | cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; | |
2871 | cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; | |
2872 | cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; | |
2873 | cmd_pkt->vp_index = sp->fcport->vp_idx; | |
2874 | ||
2875 | int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); | |
2876 | host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, | |
2877 | sizeof(cmd_pkt->lun)); | |
2878 | ||
2879 | /* Load SCSI command packet. */ | |
2880 | memcpy(cmd_pkt->fcp_cdb, cmd->cmnd, cmd->cmd_len); | |
2881 | host_to_fcp_swap(cmd_pkt->fcp_cdb, sizeof(cmd_pkt->fcp_cdb)); | |
2882 | ||
2883 | cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); | |
2884 | ||
2885 | /* Build IOCB segments */ | |
2886 | qla24xx_build_scsi_iocbs(sp, cmd_pkt, tot_dsds); | |
2887 | ||
2888 | /* Set total data segment count. */ | |
2889 | cmd_pkt->entry_count = (uint8_t)req_cnt; | |
2890 | /* Specify response queue number where | |
2891 | * completion should happen. | |
2892 | */ | |
2893 | cmd_pkt->entry_status = (uint8_t) rsp->id; | |
2894 | ||
2895 | } | |
2896 | /* Build command packet. */ | |
2897 | req->current_outstanding_cmd = handle; | |
2898 | req->outstanding_cmds[handle] = sp; | |
2899 | sp->handle = handle; | |
2900 | sp->cmd->host_scribble = (unsigned char *)(unsigned long)handle; | |
2901 | req->cnt -= req_cnt; | |
2902 | wmb(); | |
2903 | ||
2904 | /* Adjust ring index. */ | |
2905 | req->ring_index++; | |
2906 | if (req->ring_index == req->length) { | |
2907 | req->ring_index = 0; | |
2908 | req->ring_ptr = req->ring; | |
2909 | } else | |
2910 | req->ring_ptr++; | |
2911 | ||
2912 | sp->flags |= SRB_DMA_VALID; | |
2913 | ||
2914 | /* Set chip new ring index. */ | |
2915 | /* write, read and verify logic */ | |
2916 | dbval = dbval | (req->id << 8) | (req->ring_index << 16); | |
2917 | if (ql2xdbwr) | |
2918 | qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); | |
2919 | else { | |
2920 | WRT_REG_DWORD( | |
2921 | (unsigned long __iomem *)ha->nxdb_wr_ptr, | |
2922 | dbval); | |
2923 | wmb(); | |
2924 | while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { | |
2925 | WRT_REG_DWORD( | |
2926 | (unsigned long __iomem *)ha->nxdb_wr_ptr, | |
2927 | dbval); | |
2928 | wmb(); | |
2929 | } | |
2930 | } | |
2931 | ||
2932 | /* Manage unprocessed RIO/ZIO commands in response queue. */ | |
2933 | if (vha->flags.process_response_queue && | |
2934 | rsp->ring_ptr->signature != RESPONSE_PROCESSED) | |
2935 | qla24xx_process_response_queue(vha, rsp); | |
2936 | ||
2937 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
2938 | return QLA_SUCCESS; | |
2939 | ||
2940 | queuing_error_fcp_cmnd: | |
2941 | dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd, ctx->fcp_cmnd_dma); | |
2942 | queuing_error: | |
2943 | if (tot_dsds) | |
2944 | scsi_dma_unmap(cmd); | |
2945 | ||
2946 | if (sp->ctx) { | |
2947 | mempool_free(sp->ctx, ha->ctx_mempool); | |
2948 | sp->ctx = NULL; | |
2949 | } | |
2950 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
2951 | ||
2952 | return QLA_FUNCTION_FAILED; | |
2953 | } | |
2954 | ||
2955 | uint32_t * | |
2956 | qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, | |
2957 | uint32_t length) | |
2958 | { | |
2959 | uint32_t i; | |
2960 | uint32_t val; | |
2961 | struct qla_hw_data *ha = vha->hw; | |
2962 | ||
2963 | /* Dword reads to flash. */ | |
2964 | for (i = 0; i < length/4; i++, faddr += 4) { | |
2965 | if (qla82xx_rom_fast_read(ha, faddr, &val)) { | |
2966 | qla_printk(KERN_WARNING, ha, | |
2967 | "Do ROM fast read failed\n"); | |
2968 | goto done_read; | |
2969 | } | |
2970 | dwptr[i] = __constant_cpu_to_le32(val); | |
2971 | } | |
2972 | done_read: | |
2973 | return dwptr; | |
2974 | } | |
2975 | ||
2976 | int | |
2977 | qla82xx_unprotect_flash(struct qla_hw_data *ha) | |
2978 | { | |
2979 | int ret; | |
2980 | uint32_t val; | |
2981 | ||
2982 | ret = ql82xx_rom_lock_d(ha); | |
2983 | if (ret < 0) { | |
2984 | qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); | |
2985 | return ret; | |
2986 | } | |
2987 | ||
2988 | ret = qla82xx_read_status_reg(ha, &val); | |
2989 | if (ret < 0) | |
2990 | goto done_unprotect; | |
2991 | ||
2992 | val &= ~(0x7 << 2); | |
2993 | ret = qla82xx_write_status_reg(ha, val); | |
2994 | if (ret < 0) { | |
2995 | val |= (0x7 << 2); | |
2996 | qla82xx_write_status_reg(ha, val); | |
2997 | } | |
2998 | ||
2999 | if (qla82xx_write_disable_flash(ha) != 0) | |
3000 | qla_printk(KERN_WARNING, ha, "Write disable failed\n"); | |
3001 | ||
3002 | done_unprotect: | |
3003 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); | |
3004 | return ret; | |
3005 | } | |
3006 | ||
3007 | int | |
3008 | qla82xx_protect_flash(struct qla_hw_data *ha) | |
3009 | { | |
3010 | int ret; | |
3011 | uint32_t val; | |
3012 | ||
3013 | ret = ql82xx_rom_lock_d(ha); | |
3014 | if (ret < 0) { | |
3015 | qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); | |
3016 | return ret; | |
3017 | } | |
3018 | ||
3019 | ret = qla82xx_read_status_reg(ha, &val); | |
3020 | if (ret < 0) | |
3021 | goto done_protect; | |
3022 | ||
3023 | val |= (0x7 << 2); | |
3024 | /* LOCK all sectors */ | |
3025 | ret = qla82xx_write_status_reg(ha, val); | |
3026 | if (ret < 0) | |
3027 | qla_printk(KERN_WARNING, ha, "Write status register failed\n"); | |
3028 | ||
3029 | if (qla82xx_write_disable_flash(ha) != 0) | |
3030 | qla_printk(KERN_WARNING, ha, "Write disable failed\n"); | |
3031 | done_protect: | |
3032 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); | |
3033 | return ret; | |
3034 | } | |
3035 | ||
3036 | int | |
3037 | qla82xx_erase_sector(struct qla_hw_data *ha, int addr) | |
3038 | { | |
3039 | int ret = 0; | |
3040 | ||
3041 | ret = ql82xx_rom_lock_d(ha); | |
3042 | if (ret < 0) { | |
3043 | qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); | |
3044 | return ret; | |
3045 | } | |
3046 | ||
3047 | qla82xx_flash_set_write_enable(ha); | |
3048 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); | |
3049 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); | |
3050 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); | |
3051 | ||
3052 | if (qla82xx_wait_rom_done(ha)) { | |
3053 | qla_printk(KERN_WARNING, ha, | |
3054 | "Error waiting for rom done\n"); | |
3055 | ret = -1; | |
3056 | goto done; | |
3057 | } | |
3058 | ret = qla82xx_flash_wait_write_finish(ha); | |
3059 | done: | |
3060 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); | |
3061 | return ret; | |
3062 | } | |
3063 | ||
3064 | /* | |
3065 | * Address and length are byte address | |
3066 | */ | |
3067 | uint8_t * | |
3068 | qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, | |
3069 | uint32_t offset, uint32_t length) | |
3070 | { | |
3071 | scsi_block_requests(vha->host); | |
3072 | qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); | |
3073 | scsi_unblock_requests(vha->host); | |
3074 | return buf; | |
3075 | } | |
3076 | ||
3077 | static int | |
3078 | qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, | |
3079 | uint32_t faddr, uint32_t dwords) | |
3080 | { | |
3081 | int ret; | |
3082 | uint32_t liter; | |
3083 | uint32_t sec_mask, rest_addr; | |
3084 | dma_addr_t optrom_dma; | |
3085 | void *optrom = NULL; | |
3086 | int page_mode = 0; | |
3087 | struct qla_hw_data *ha = vha->hw; | |
3088 | ||
3089 | ret = -1; | |
3090 | ||
3091 | /* Prepare burst-capable write on supported ISPs. */ | |
3092 | if (page_mode && !(faddr & 0xfff) && | |
3093 | dwords > OPTROM_BURST_DWORDS) { | |
3094 | optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, | |
3095 | &optrom_dma, GFP_KERNEL); | |
3096 | if (!optrom) { | |
3097 | qla_printk(KERN_DEBUG, ha, | |
3098 | "Unable to allocate memory for optrom " | |
3099 | "burst write (%x KB).\n", | |
3100 | OPTROM_BURST_SIZE / 1024); | |
3101 | } | |
3102 | } | |
3103 | ||
3104 | rest_addr = ha->fdt_block_size - 1; | |
3105 | sec_mask = ~rest_addr; | |
3106 | ||
3107 | ret = qla82xx_unprotect_flash(ha); | |
3108 | if (ret) { | |
3109 | qla_printk(KERN_WARNING, ha, | |
3110 | "Unable to unprotect flash for update.\n"); | |
3111 | goto write_done; | |
3112 | } | |
3113 | ||
3114 | for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { | |
3115 | /* Are we at the beginning of a sector? */ | |
3116 | if ((faddr & rest_addr) == 0) { | |
3117 | ||
3118 | ret = qla82xx_erase_sector(ha, faddr); | |
3119 | if (ret) { | |
3120 | DEBUG9(qla_printk(KERN_ERR, ha, | |
3121 | "Unable to erase sector: " | |
3122 | "address=%x.\n", faddr)); | |
3123 | break; | |
3124 | } | |
3125 | } | |
3126 | ||
3127 | /* Go with burst-write. */ | |
3128 | if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { | |
3129 | /* Copy data to DMA'ble buffer. */ | |
3130 | memcpy(optrom, dwptr, OPTROM_BURST_SIZE); | |
3131 | ||
3132 | ret = qla2x00_load_ram(vha, optrom_dma, | |
3133 | (ha->flash_data_off | faddr), | |
3134 | OPTROM_BURST_DWORDS); | |
3135 | if (ret != QLA_SUCCESS) { | |
3136 | qla_printk(KERN_WARNING, ha, | |
3137 | "Unable to burst-write optrom segment " | |
3138 | "(%x/%x/%llx).\n", ret, | |
3139 | (ha->flash_data_off | faddr), | |
3140 | (unsigned long long)optrom_dma); | |
3141 | qla_printk(KERN_WARNING, ha, | |
3142 | "Reverting to slow-write.\n"); | |
3143 | ||
3144 | dma_free_coherent(&ha->pdev->dev, | |
3145 | OPTROM_BURST_SIZE, optrom, optrom_dma); | |
3146 | optrom = NULL; | |
3147 | } else { | |
3148 | liter += OPTROM_BURST_DWORDS - 1; | |
3149 | faddr += OPTROM_BURST_DWORDS - 1; | |
3150 | dwptr += OPTROM_BURST_DWORDS - 1; | |
3151 | continue; | |
3152 | } | |
3153 | } | |
3154 | ||
3155 | ret = qla82xx_write_flash_dword(ha, faddr, | |
3156 | cpu_to_le32(*dwptr)); | |
3157 | if (ret) { | |
3158 | DEBUG9(printk(KERN_DEBUG "%s(%ld) Unable to program" | |
3159 | "flash address=%x data=%x.\n", __func__, | |
3160 | ha->host_no, faddr, *dwptr)); | |
3161 | break; | |
3162 | } | |
3163 | } | |
3164 | ||
3165 | ret = qla82xx_protect_flash(ha); | |
3166 | if (ret) | |
3167 | qla_printk(KERN_WARNING, ha, | |
3168 | "Unable to protect flash after update.\n"); | |
3169 | write_done: | |
3170 | if (optrom) | |
3171 | dma_free_coherent(&ha->pdev->dev, | |
3172 | OPTROM_BURST_SIZE, optrom, optrom_dma); | |
3173 | return ret; | |
3174 | } | |
3175 | ||
3176 | int | |
3177 | qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, | |
3178 | uint32_t offset, uint32_t length) | |
3179 | { | |
3180 | int rval; | |
3181 | ||
3182 | /* Suspend HBA. */ | |
3183 | scsi_block_requests(vha->host); | |
3184 | rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, | |
3185 | length >> 2); | |
3186 | scsi_unblock_requests(vha->host); | |
3187 | ||
3188 | /* Convert return ISP82xx to generic */ | |
3189 | if (rval) | |
3190 | rval = QLA_FUNCTION_FAILED; | |
3191 | else | |
3192 | rval = QLA_SUCCESS; | |
3193 | return rval; | |
3194 | } | |
3195 | ||
3196 | void | |
3197 | qla82xx_start_iocbs(srb_t *sp) | |
3198 | { | |
3199 | struct qla_hw_data *ha = sp->fcport->vha->hw; | |
3200 | struct req_que *req = ha->req_q_map[0]; | |
3201 | struct device_reg_82xx __iomem *reg; | |
3202 | uint32_t dbval; | |
3203 | ||
3204 | /* Adjust ring index. */ | |
3205 | req->ring_index++; | |
3206 | if (req->ring_index == req->length) { | |
3207 | req->ring_index = 0; | |
3208 | req->ring_ptr = req->ring; | |
3209 | } else | |
3210 | req->ring_ptr++; | |
3211 | ||
3212 | reg = &ha->iobase->isp82; | |
3213 | dbval = 0x04 | (ha->portnum << 5); | |
3214 | ||
3215 | dbval = dbval | (req->id << 8) | (req->ring_index << 16); | |
3216 | WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); | |
3217 | wmb(); | |
3218 | while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { | |
3219 | WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); | |
3220 | wmb(); | |
3221 | } | |
3222 | } | |
3223 | ||
3224 | /* | |
3225 | * qla82xx_device_bootstrap | |
3226 | * Initialize device, set DEV_READY, start fw | |
3227 | * | |
3228 | * Note: | |
3229 | * IDC lock must be held upon entry | |
3230 | * | |
3231 | * Return: | |
3232 | * Success : 0 | |
3233 | * Failed : 1 | |
3234 | */ | |
3235 | static int | |
3236 | qla82xx_device_bootstrap(scsi_qla_host_t *vha) | |
3237 | { | |
3238 | int rval, i, timeout; | |
3239 | uint32_t old_count, count; | |
3240 | struct qla_hw_data *ha = vha->hw; | |
3241 | ||
3242 | if (qla82xx_need_reset(ha)) | |
3243 | goto dev_initialize; | |
3244 | ||
3245 | old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); | |
3246 | ||
3247 | for (i = 0; i < 10; i++) { | |
3248 | timeout = msleep_interruptible(200); | |
3249 | if (timeout) { | |
3250 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
3251 | QLA82XX_DEV_FAILED); | |
3252 | return QLA_FUNCTION_FAILED; | |
3253 | } | |
3254 | ||
3255 | count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); | |
3256 | if (count != old_count) | |
3257 | goto dev_ready; | |
3258 | } | |
3259 | ||
3260 | dev_initialize: | |
3261 | /* set to DEV_INITIALIZING */ | |
3262 | qla_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); | |
3263 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); | |
3264 | ||
3265 | /* Driver that sets device state to initializating sets IDC version */ | |
3266 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); | |
3267 | ||
3268 | qla82xx_idc_unlock(ha); | |
3269 | rval = qla82xx_start_firmware(vha); | |
3270 | qla82xx_idc_lock(ha); | |
3271 | ||
3272 | if (rval != QLA_SUCCESS) { | |
3273 | qla_printk(KERN_INFO, ha, "HW State: FAILED\n"); | |
3274 | qla82xx_clear_drv_active(ha); | |
3275 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); | |
3276 | return rval; | |
3277 | } | |
3278 | ||
3279 | dev_ready: | |
3280 | qla_printk(KERN_INFO, ha, "HW State: READY\n"); | |
3281 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); | |
3282 | ||
3283 | return QLA_SUCCESS; | |
3284 | } | |
3285 | ||
3286 | static void | |
3287 | qla82xx_dev_failed_handler(scsi_qla_host_t *vha) | |
3288 | { | |
3289 | struct qla_hw_data *ha = vha->hw; | |
3290 | ||
3291 | /* Disable the board */ | |
3292 | qla_printk(KERN_INFO, ha, "Disabling the board\n"); | |
3293 | ||
3294 | /* Set DEV_FAILED flag to disable timer */ | |
3295 | vha->device_flags |= DFLG_DEV_FAILED; | |
3296 | qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); | |
3297 | qla2x00_mark_all_devices_lost(vha, 0); | |
3298 | vha->flags.online = 0; | |
3299 | vha->flags.init_done = 0; | |
3300 | } | |
3301 | ||
3302 | /* | |
3303 | * qla82xx_need_reset_handler | |
3304 | * Code to start reset sequence | |
3305 | * | |
3306 | * Note: | |
3307 | * IDC lock must be held upon entry | |
3308 | * | |
3309 | * Return: | |
3310 | * Success : 0 | |
3311 | * Failed : 1 | |
3312 | */ | |
3313 | static void | |
3314 | qla82xx_need_reset_handler(scsi_qla_host_t *vha) | |
3315 | { | |
3316 | uint32_t dev_state, drv_state, drv_active; | |
3317 | unsigned long reset_timeout; | |
3318 | struct qla_hw_data *ha = vha->hw; | |
3319 | struct req_que *req = ha->req_q_map[0]; | |
3320 | ||
3321 | if (vha->flags.online) { | |
3322 | qla82xx_idc_unlock(ha); | |
3323 | qla2x00_abort_isp_cleanup(vha); | |
3324 | ha->isp_ops->get_flash_version(vha, req->ring); | |
3325 | ha->isp_ops->nvram_config(vha); | |
3326 | qla82xx_idc_lock(ha); | |
3327 | } | |
3328 | ||
3329 | qla82xx_set_rst_ready(ha); | |
3330 | ||
3331 | /* wait for 10 seconds for reset ack from all functions */ | |
3332 | reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); | |
3333 | ||
3334 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | |
3335 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
3336 | ||
3337 | while (drv_state != drv_active) { | |
3338 | if (time_after_eq(jiffies, reset_timeout)) { | |
3339 | qla_printk(KERN_INFO, ha, | |
3340 | "%s: RESET TIMEOUT!\n", QLA2XXX_DRIVER_NAME); | |
3341 | break; | |
3342 | } | |
3343 | qla82xx_idc_unlock(ha); | |
3344 | msleep(1000); | |
3345 | qla82xx_idc_lock(ha); | |
3346 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | |
3347 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
3348 | } | |
3349 | ||
3350 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | |
3351 | /* Force to DEV_COLD unless someone else is starting a reset */ | |
3352 | if (dev_state != QLA82XX_DEV_INITIALIZING) { | |
3353 | qla_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); | |
3354 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); | |
3355 | } | |
3356 | } | |
3357 | ||
3358 | static void | |
3359 | qla82xx_check_fw_alive(scsi_qla_host_t *vha) | |
3360 | { | |
3361 | uint32_t fw_heartbeat_counter, halt_status; | |
3362 | struct qla_hw_data *ha = vha->hw; | |
3363 | ||
3364 | fw_heartbeat_counter = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); | |
3365 | if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { | |
3366 | vha->seconds_since_last_heartbeat++; | |
3367 | /* FW not alive after 2 seconds */ | |
3368 | if (vha->seconds_since_last_heartbeat == 2) { | |
3369 | vha->seconds_since_last_heartbeat = 0; | |
3370 | halt_status = qla82xx_rd_32(ha, | |
3371 | QLA82XX_PEG_HALT_STATUS1); | |
3372 | if (halt_status & HALT_STATUS_UNRECOVERABLE) { | |
3373 | set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); | |
3374 | } else { | |
3375 | qla_printk(KERN_INFO, ha, | |
3376 | "scsi(%ld): %s - detect abort needed\n", | |
3377 | vha->host_no, __func__); | |
3378 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
3379 | } | |
3380 | qla2xxx_wake_dpc(vha); | |
3381 | } | |
3382 | } | |
3383 | vha->fw_heartbeat_counter = fw_heartbeat_counter; | |
3384 | } | |
3385 | ||
3386 | /* | |
3387 | * qla82xx_device_state_handler | |
3388 | * Main state handler | |
3389 | * | |
3390 | * Note: | |
3391 | * IDC lock must be held upon entry | |
3392 | * | |
3393 | * Return: | |
3394 | * Success : 0 | |
3395 | * Failed : 1 | |
3396 | */ | |
3397 | int | |
3398 | qla82xx_device_state_handler(scsi_qla_host_t *vha) | |
3399 | { | |
3400 | uint32_t dev_state; | |
3401 | uint32_t drv_active; | |
3402 | int rval = QLA_SUCCESS; | |
3403 | unsigned long dev_init_timeout; | |
3404 | struct qla_hw_data *ha = vha->hw; | |
3405 | ||
3406 | qla82xx_idc_lock(ha); | |
3407 | if (!vha->flags.init_done) | |
3408 | qla82xx_set_drv_active(vha); | |
3409 | ||
3410 | /* Set cold state*/ | |
3411 | if (!PCI_FUNC(ha->pdev->devfn & 1)) { | |
3412 | ||
3413 | /* Check if other functions alive, else set dev state | |
3414 | * to cold | |
3415 | */ | |
3416 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
3417 | drv_active &= ~(1 << (ha->portnum * 4)); | |
3418 | drv_active &= ~(1 << ((ha->portnum + 1) * 4)); | |
3419 | ||
3420 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | |
3421 | if (!drv_active) { | |
3422 | ||
3423 | switch (dev_state) { | |
3424 | case QLA82XX_DEV_COLD: | |
3425 | case QLA82XX_DEV_READY: | |
3426 | case QLA82XX_DEV_INITIALIZING: | |
3427 | case QLA82XX_DEV_NEED_RESET: | |
3428 | case QLA82XX_DEV_NEED_QUIESCENT: | |
3429 | case QLA82XX_DEV_QUIESCENT: | |
3430 | case QLA82XX_DEV_FAILED: | |
3431 | break; | |
3432 | default: | |
3433 | qla_printk(KERN_INFO, ha, | |
3434 | "No other function exist," | |
3435 | " resetting dev state to COLD\n"); | |
3436 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
3437 | QLA82XX_DEV_COLD); | |
3438 | break; | |
3439 | } | |
3440 | } | |
3441 | } | |
3442 | ||
3443 | /* wait for 30 seconds for device to go ready */ | |
3444 | dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); | |
3445 | ||
3446 | while (1) { | |
3447 | ||
3448 | if (time_after_eq(jiffies, dev_init_timeout)) { | |
3449 | DEBUG(qla_printk(KERN_INFO, ha, | |
3450 | "%s: device init failed!\n", | |
3451 | QLA2XXX_DRIVER_NAME)); | |
3452 | rval = QLA_FUNCTION_FAILED; | |
3453 | break; | |
3454 | } | |
3455 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | |
3456 | switch (dev_state) { | |
3457 | case QLA82XX_DEV_READY: | |
3458 | goto exit; | |
3459 | case QLA82XX_DEV_COLD: | |
3460 | rval = qla82xx_device_bootstrap(vha); | |
3461 | goto exit; | |
3462 | case QLA82XX_DEV_INITIALIZING: | |
3463 | qla82xx_idc_unlock(ha); | |
3464 | msleep(1000); | |
3465 | qla82xx_idc_lock(ha); | |
3466 | break; | |
3467 | case QLA82XX_DEV_NEED_RESET: | |
3468 | if (!ql2xdontresethba) | |
3469 | qla82xx_need_reset_handler(vha); | |
3470 | break; | |
3471 | case QLA82XX_DEV_NEED_QUIESCENT: | |
3472 | qla82xx_set_qsnt_ready(ha); | |
3473 | case QLA82XX_DEV_QUIESCENT: | |
3474 | qla82xx_idc_unlock(ha); | |
3475 | msleep(1000); | |
3476 | qla82xx_idc_lock(ha); | |
3477 | break; | |
3478 | case QLA82XX_DEV_FAILED: | |
3479 | qla82xx_dev_failed_handler(vha); | |
3480 | rval = QLA_FUNCTION_FAILED; | |
3481 | goto exit; | |
3482 | default: | |
3483 | qla82xx_idc_unlock(ha); | |
3484 | msleep(1000); | |
3485 | qla82xx_idc_lock(ha); | |
3486 | } | |
3487 | } | |
3488 | exit: | |
3489 | qla82xx_idc_unlock(ha); | |
3490 | return rval; | |
3491 | } | |
3492 | ||
3493 | void qla82xx_watchdog(scsi_qla_host_t *vha) | |
3494 | { | |
3495 | uint32_t dev_state; | |
3496 | struct qla_hw_data *ha = vha->hw; | |
3497 | ||
3498 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | |
3499 | ||
3500 | /* don't poll if reset is going on */ | |
3501 | if (!(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || | |
3502 | test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) || | |
3503 | test_bit(ISP_ABORT_RETRY, &vha->dpc_flags))) { | |
3504 | if (dev_state == QLA82XX_DEV_NEED_RESET) { | |
3505 | qla_printk(KERN_WARNING, ha, | |
3506 | "%s(): Adapter reset needed!\n", __func__); | |
3507 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | |
3508 | qla2xxx_wake_dpc(vha); | |
3509 | } else { | |
3510 | qla82xx_check_fw_alive(vha); | |
3511 | } | |
3512 | } | |
3513 | } | |
3514 | ||
3515 | int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) | |
3516 | { | |
3517 | int rval; | |
3518 | rval = qla82xx_device_state_handler(vha); | |
3519 | return rval; | |
3520 | } | |
3521 | ||
3522 | /* | |
3523 | * qla82xx_abort_isp | |
3524 | * Resets ISP and aborts all outstanding commands. | |
3525 | * | |
3526 | * Input: | |
3527 | * ha = adapter block pointer. | |
3528 | * | |
3529 | * Returns: | |
3530 | * 0 = success | |
3531 | */ | |
3532 | int | |
3533 | qla82xx_abort_isp(scsi_qla_host_t *vha) | |
3534 | { | |
3535 | int rval; | |
3536 | struct qla_hw_data *ha = vha->hw; | |
3537 | uint32_t dev_state; | |
3538 | ||
3539 | if (vha->device_flags & DFLG_DEV_FAILED) { | |
3540 | qla_printk(KERN_WARNING, ha, | |
3541 | "%s(%ld): Device in failed state, " | |
3542 | "Exiting.\n", __func__, vha->host_no); | |
3543 | return QLA_SUCCESS; | |
3544 | } | |
3545 | ||
3546 | qla82xx_idc_lock(ha); | |
3547 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | |
3548 | if (dev_state != QLA82XX_DEV_INITIALIZING) { | |
3549 | qla_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); | |
3550 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
3551 | QLA82XX_DEV_NEED_RESET); | |
3552 | } else | |
3553 | qla_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n"); | |
3554 | qla82xx_idc_unlock(ha); | |
3555 | ||
3556 | rval = qla82xx_device_state_handler(vha); | |
3557 | ||
3558 | qla82xx_idc_lock(ha); | |
3559 | qla82xx_clear_rst_ready(ha); | |
3560 | qla82xx_idc_unlock(ha); | |
3561 | ||
3562 | if (rval == QLA_SUCCESS) | |
3563 | qla82xx_restart_isp(vha); | |
3564 | return rval; | |
3565 | } | |
3566 | ||
3567 | /* | |
3568 | * qla82xx_fcoe_ctx_reset | |
3569 | * Perform a quick reset and aborts all outstanding commands. | |
3570 | * This will only perform an FCoE context reset and avoids a full blown | |
3571 | * chip reset. | |
3572 | * | |
3573 | * Input: | |
3574 | * ha = adapter block pointer. | |
3575 | * is_reset_path = flag for identifying the reset path. | |
3576 | * | |
3577 | * Returns: | |
3578 | * 0 = success | |
3579 | */ | |
3580 | int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) | |
3581 | { | |
3582 | int rval = QLA_FUNCTION_FAILED; | |
3583 | ||
3584 | if (vha->flags.online) { | |
3585 | /* Abort all outstanding commands, so as to be requeued later */ | |
3586 | qla2x00_abort_isp_cleanup(vha); | |
3587 | } | |
3588 | ||
3589 | /* Stop currently executing firmware. | |
3590 | * This will destroy existing FCoE context at the F/W end. | |
3591 | */ | |
3592 | qla2x00_try_to_stop_firmware(vha); | |
3593 | ||
3594 | /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ | |
3595 | rval = qla82xx_restart_isp(vha); | |
3596 | ||
3597 | return rval; | |
3598 | } | |
3599 | ||
3600 | /* | |
3601 | * qla2x00_wait_for_fcoe_ctx_reset | |
3602 | * Wait till the FCoE context is reset. | |
3603 | * | |
3604 | * Note: | |
3605 | * Does context switching here. | |
3606 | * Release SPIN_LOCK (if any) before calling this routine. | |
3607 | * | |
3608 | * Return: | |
3609 | * Success (fcoe_ctx reset is done) : 0 | |
3610 | * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 | |
3611 | */ | |
3612 | int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) | |
3613 | { | |
3614 | int status = QLA_FUNCTION_FAILED; | |
3615 | unsigned long wait_reset; | |
3616 | ||
3617 | wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); | |
3618 | while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || | |
3619 | test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) | |
3620 | && time_before(jiffies, wait_reset)) { | |
3621 | ||
3622 | set_current_state(TASK_UNINTERRUPTIBLE); | |
3623 | schedule_timeout(HZ); | |
3624 | ||
3625 | if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && | |
3626 | !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { | |
3627 | status = QLA_SUCCESS; | |
3628 | break; | |
3629 | } | |
3630 | } | |
3631 | DEBUG2(printk(KERN_INFO | |
3632 | "%s status=%d\n", __func__, status)); | |
3633 | ||
3634 | return status; | |
3635 | } |