Commit | Line | Data |
---|---|---|
a9083016 GM |
1 | /* |
2 | * QLogic Fibre Channel HBA Driver | |
07e264b7 | 3 | * Copyright (c) 2003-2011 QLogic Corporation |
a9083016 GM |
4 | * |
5 | * See LICENSE.qla2xxx for copyright and licensing details. | |
6 | */ | |
7 | #include "qla_def.h" | |
8 | #include <linux/delay.h> | |
9 | #include <linux/pci.h> | |
08de2844 GM |
10 | #include <linux/ratelimit.h> |
11 | #include <linux/vmalloc.h> | |
ff2fc42e | 12 | #include <scsi/scsi_tcq.h> |
a9083016 GM |
13 | |
14 | #define MASK(n) ((1ULL<<(n))-1) | |
15 | #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ | |
16 | ((addr >> 25) & 0x3ff)) | |
17 | #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ | |
18 | ((addr >> 25) & 0x3ff)) | |
19 | #define MS_WIN(addr) (addr & 0x0ffc0000) | |
20 | #define QLA82XX_PCI_MN_2M (0) | |
21 | #define QLA82XX_PCI_MS_2M (0x80000) | |
22 | #define QLA82XX_PCI_OCM0_2M (0xc0000) | |
23 | #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) | |
24 | #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) | |
0547fb37 | 25 | #define BLOCK_PROTECT_BITS 0x0F |
a9083016 GM |
26 | |
27 | /* CRB window related */ | |
28 | #define CRB_BLK(off) ((off >> 20) & 0x3f) | |
29 | #define CRB_SUBBLK(off) ((off >> 16) & 0xf) | |
30 | #define CRB_WINDOW_2M (0x130060) | |
31 | #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) | |
32 | #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ | |
33 | ((off) & 0xf0000)) | |
34 | #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) | |
35 | #define CRB_INDIRECT_2M (0x1e0000UL) | |
36 | ||
a9083016 GM |
37 | #define MAX_CRB_XFORM 60 |
38 | static unsigned long crb_addr_xform[MAX_CRB_XFORM]; | |
39 | int qla82xx_crb_table_initialized; | |
40 | ||
41 | #define qla82xx_crb_addr_transform(name) \ | |
42 | (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ | |
43 | QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) | |
44 | ||
45 | static void qla82xx_crb_addr_transform_setup(void) | |
46 | { | |
47 | qla82xx_crb_addr_transform(XDMA); | |
48 | qla82xx_crb_addr_transform(TIMR); | |
49 | qla82xx_crb_addr_transform(SRE); | |
50 | qla82xx_crb_addr_transform(SQN3); | |
51 | qla82xx_crb_addr_transform(SQN2); | |
52 | qla82xx_crb_addr_transform(SQN1); | |
53 | qla82xx_crb_addr_transform(SQN0); | |
54 | qla82xx_crb_addr_transform(SQS3); | |
55 | qla82xx_crb_addr_transform(SQS2); | |
56 | qla82xx_crb_addr_transform(SQS1); | |
57 | qla82xx_crb_addr_transform(SQS0); | |
58 | qla82xx_crb_addr_transform(RPMX7); | |
59 | qla82xx_crb_addr_transform(RPMX6); | |
60 | qla82xx_crb_addr_transform(RPMX5); | |
61 | qla82xx_crb_addr_transform(RPMX4); | |
62 | qla82xx_crb_addr_transform(RPMX3); | |
63 | qla82xx_crb_addr_transform(RPMX2); | |
64 | qla82xx_crb_addr_transform(RPMX1); | |
65 | qla82xx_crb_addr_transform(RPMX0); | |
66 | qla82xx_crb_addr_transform(ROMUSB); | |
67 | qla82xx_crb_addr_transform(SN); | |
68 | qla82xx_crb_addr_transform(QMN); | |
69 | qla82xx_crb_addr_transform(QMS); | |
70 | qla82xx_crb_addr_transform(PGNI); | |
71 | qla82xx_crb_addr_transform(PGND); | |
72 | qla82xx_crb_addr_transform(PGN3); | |
73 | qla82xx_crb_addr_transform(PGN2); | |
74 | qla82xx_crb_addr_transform(PGN1); | |
75 | qla82xx_crb_addr_transform(PGN0); | |
76 | qla82xx_crb_addr_transform(PGSI); | |
77 | qla82xx_crb_addr_transform(PGSD); | |
78 | qla82xx_crb_addr_transform(PGS3); | |
79 | qla82xx_crb_addr_transform(PGS2); | |
80 | qla82xx_crb_addr_transform(PGS1); | |
81 | qla82xx_crb_addr_transform(PGS0); | |
82 | qla82xx_crb_addr_transform(PS); | |
83 | qla82xx_crb_addr_transform(PH); | |
84 | qla82xx_crb_addr_transform(NIU); | |
85 | qla82xx_crb_addr_transform(I2Q); | |
86 | qla82xx_crb_addr_transform(EG); | |
87 | qla82xx_crb_addr_transform(MN); | |
88 | qla82xx_crb_addr_transform(MS); | |
89 | qla82xx_crb_addr_transform(CAS2); | |
90 | qla82xx_crb_addr_transform(CAS1); | |
91 | qla82xx_crb_addr_transform(CAS0); | |
92 | qla82xx_crb_addr_transform(CAM); | |
93 | qla82xx_crb_addr_transform(C2C1); | |
94 | qla82xx_crb_addr_transform(C2C0); | |
95 | qla82xx_crb_addr_transform(SMB); | |
96 | qla82xx_crb_addr_transform(OCM0); | |
97 | /* | |
98 | * Used only in P3 just define it for P2 also. | |
99 | */ | |
100 | qla82xx_crb_addr_transform(I2C0); | |
101 | ||
102 | qla82xx_crb_table_initialized = 1; | |
103 | } | |
104 | ||
105 | struct crb_128M_2M_block_map crb_128M_2M_map[64] = { | |
106 | {{{0, 0, 0, 0} } }, | |
107 | {{{1, 0x0100000, 0x0102000, 0x120000}, | |
108 | {1, 0x0110000, 0x0120000, 0x130000}, | |
109 | {1, 0x0120000, 0x0122000, 0x124000}, | |
110 | {1, 0x0130000, 0x0132000, 0x126000}, | |
111 | {1, 0x0140000, 0x0142000, 0x128000}, | |
112 | {1, 0x0150000, 0x0152000, 0x12a000}, | |
113 | {1, 0x0160000, 0x0170000, 0x110000}, | |
114 | {1, 0x0170000, 0x0172000, 0x12e000}, | |
115 | {0, 0x0000000, 0x0000000, 0x000000}, | |
116 | {0, 0x0000000, 0x0000000, 0x000000}, | |
117 | {0, 0x0000000, 0x0000000, 0x000000}, | |
118 | {0, 0x0000000, 0x0000000, 0x000000}, | |
119 | {0, 0x0000000, 0x0000000, 0x000000}, | |
120 | {0, 0x0000000, 0x0000000, 0x000000}, | |
121 | {1, 0x01e0000, 0x01e0800, 0x122000}, | |
122 | {0, 0x0000000, 0x0000000, 0x000000} } } , | |
123 | {{{1, 0x0200000, 0x0210000, 0x180000} } }, | |
124 | {{{0, 0, 0, 0} } }, | |
125 | {{{1, 0x0400000, 0x0401000, 0x169000} } }, | |
126 | {{{1, 0x0500000, 0x0510000, 0x140000} } }, | |
127 | {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, | |
128 | {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, | |
129 | {{{1, 0x0800000, 0x0802000, 0x170000}, | |
130 | {0, 0x0000000, 0x0000000, 0x000000}, | |
131 | {0, 0x0000000, 0x0000000, 0x000000}, | |
132 | {0, 0x0000000, 0x0000000, 0x000000}, | |
133 | {0, 0x0000000, 0x0000000, 0x000000}, | |
134 | {0, 0x0000000, 0x0000000, 0x000000}, | |
135 | {0, 0x0000000, 0x0000000, 0x000000}, | |
136 | {0, 0x0000000, 0x0000000, 0x000000}, | |
137 | {0, 0x0000000, 0x0000000, 0x000000}, | |
138 | {0, 0x0000000, 0x0000000, 0x000000}, | |
139 | {0, 0x0000000, 0x0000000, 0x000000}, | |
140 | {0, 0x0000000, 0x0000000, 0x000000}, | |
141 | {0, 0x0000000, 0x0000000, 0x000000}, | |
142 | {0, 0x0000000, 0x0000000, 0x000000}, | |
143 | {0, 0x0000000, 0x0000000, 0x000000}, | |
144 | {1, 0x08f0000, 0x08f2000, 0x172000} } }, | |
145 | {{{1, 0x0900000, 0x0902000, 0x174000}, | |
146 | {0, 0x0000000, 0x0000000, 0x000000}, | |
147 | {0, 0x0000000, 0x0000000, 0x000000}, | |
148 | {0, 0x0000000, 0x0000000, 0x000000}, | |
149 | {0, 0x0000000, 0x0000000, 0x000000}, | |
150 | {0, 0x0000000, 0x0000000, 0x000000}, | |
151 | {0, 0x0000000, 0x0000000, 0x000000}, | |
152 | {0, 0x0000000, 0x0000000, 0x000000}, | |
153 | {0, 0x0000000, 0x0000000, 0x000000}, | |
154 | {0, 0x0000000, 0x0000000, 0x000000}, | |
155 | {0, 0x0000000, 0x0000000, 0x000000}, | |
156 | {0, 0x0000000, 0x0000000, 0x000000}, | |
157 | {0, 0x0000000, 0x0000000, 0x000000}, | |
158 | {0, 0x0000000, 0x0000000, 0x000000}, | |
159 | {0, 0x0000000, 0x0000000, 0x000000}, | |
160 | {1, 0x09f0000, 0x09f2000, 0x176000} } }, | |
161 | {{{0, 0x0a00000, 0x0a02000, 0x178000}, | |
162 | {0, 0x0000000, 0x0000000, 0x000000}, | |
163 | {0, 0x0000000, 0x0000000, 0x000000}, | |
164 | {0, 0x0000000, 0x0000000, 0x000000}, | |
165 | {0, 0x0000000, 0x0000000, 0x000000}, | |
166 | {0, 0x0000000, 0x0000000, 0x000000}, | |
167 | {0, 0x0000000, 0x0000000, 0x000000}, | |
168 | {0, 0x0000000, 0x0000000, 0x000000}, | |
169 | {0, 0x0000000, 0x0000000, 0x000000}, | |
170 | {0, 0x0000000, 0x0000000, 0x000000}, | |
171 | {0, 0x0000000, 0x0000000, 0x000000}, | |
172 | {0, 0x0000000, 0x0000000, 0x000000}, | |
173 | {0, 0x0000000, 0x0000000, 0x000000}, | |
174 | {0, 0x0000000, 0x0000000, 0x000000}, | |
175 | {0, 0x0000000, 0x0000000, 0x000000}, | |
176 | {1, 0x0af0000, 0x0af2000, 0x17a000} } }, | |
177 | {{{0, 0x0b00000, 0x0b02000, 0x17c000}, | |
178 | {0, 0x0000000, 0x0000000, 0x000000}, | |
179 | {0, 0x0000000, 0x0000000, 0x000000}, | |
180 | {0, 0x0000000, 0x0000000, 0x000000}, | |
181 | {0, 0x0000000, 0x0000000, 0x000000}, | |
182 | {0, 0x0000000, 0x0000000, 0x000000}, | |
183 | {0, 0x0000000, 0x0000000, 0x000000}, | |
184 | {0, 0x0000000, 0x0000000, 0x000000}, | |
185 | {0, 0x0000000, 0x0000000, 0x000000}, | |
186 | {0, 0x0000000, 0x0000000, 0x000000}, | |
187 | {0, 0x0000000, 0x0000000, 0x000000}, | |
188 | {0, 0x0000000, 0x0000000, 0x000000}, | |
189 | {0, 0x0000000, 0x0000000, 0x000000}, | |
190 | {0, 0x0000000, 0x0000000, 0x000000}, | |
191 | {0, 0x0000000, 0x0000000, 0x000000}, | |
192 | {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, | |
193 | {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, | |
194 | {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, | |
195 | {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, | |
196 | {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, | |
197 | {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, | |
198 | {{{1, 0x1100000, 0x1101000, 0x160000} } }, | |
199 | {{{1, 0x1200000, 0x1201000, 0x161000} } }, | |
200 | {{{1, 0x1300000, 0x1301000, 0x162000} } }, | |
201 | {{{1, 0x1400000, 0x1401000, 0x163000} } }, | |
202 | {{{1, 0x1500000, 0x1501000, 0x165000} } }, | |
203 | {{{1, 0x1600000, 0x1601000, 0x166000} } }, | |
204 | {{{0, 0, 0, 0} } }, | |
205 | {{{0, 0, 0, 0} } }, | |
206 | {{{0, 0, 0, 0} } }, | |
207 | {{{0, 0, 0, 0} } }, | |
208 | {{{0, 0, 0, 0} } }, | |
209 | {{{0, 0, 0, 0} } }, | |
210 | {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, | |
211 | {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, | |
212 | {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, | |
213 | {{{0} } }, | |
214 | {{{1, 0x2100000, 0x2102000, 0x120000}, | |
215 | {1, 0x2110000, 0x2120000, 0x130000}, | |
216 | {1, 0x2120000, 0x2122000, 0x124000}, | |
217 | {1, 0x2130000, 0x2132000, 0x126000}, | |
218 | {1, 0x2140000, 0x2142000, 0x128000}, | |
219 | {1, 0x2150000, 0x2152000, 0x12a000}, | |
220 | {1, 0x2160000, 0x2170000, 0x110000}, | |
221 | {1, 0x2170000, 0x2172000, 0x12e000}, | |
222 | {0, 0x0000000, 0x0000000, 0x000000}, | |
223 | {0, 0x0000000, 0x0000000, 0x000000}, | |
224 | {0, 0x0000000, 0x0000000, 0x000000}, | |
225 | {0, 0x0000000, 0x0000000, 0x000000}, | |
226 | {0, 0x0000000, 0x0000000, 0x000000}, | |
227 | {0, 0x0000000, 0x0000000, 0x000000}, | |
228 | {0, 0x0000000, 0x0000000, 0x000000}, | |
229 | {0, 0x0000000, 0x0000000, 0x000000} } }, | |
230 | {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, | |
231 | {{{0} } }, | |
232 | {{{0} } }, | |
233 | {{{0} } }, | |
234 | {{{0} } }, | |
235 | {{{0} } }, | |
236 | {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, | |
237 | {{{1, 0x2900000, 0x2901000, 0x16b000} } }, | |
238 | {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, | |
239 | {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, | |
240 | {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, | |
241 | {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, | |
242 | {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, | |
243 | {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, | |
244 | {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, | |
245 | {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, | |
246 | {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, | |
247 | {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, | |
248 | {{{0} } }, | |
249 | {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, | |
250 | {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, | |
251 | {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, | |
252 | {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, | |
253 | {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, | |
254 | {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, | |
255 | {{{0} } }, | |
256 | {{{0} } }, | |
257 | {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, | |
258 | {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, | |
259 | {{{1, 0x3f00000, 0x3f01000, 0x168000} } } | |
260 | }; | |
261 | ||
262 | /* | |
263 | * top 12 bits of crb internal address (hub, agent) | |
264 | */ | |
265 | unsigned qla82xx_crb_hub_agt[64] = { | |
266 | 0, | |
267 | QLA82XX_HW_CRB_HUB_AGT_ADR_PS, | |
268 | QLA82XX_HW_CRB_HUB_AGT_ADR_MN, | |
269 | QLA82XX_HW_CRB_HUB_AGT_ADR_MS, | |
270 | 0, | |
271 | QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, | |
272 | QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, | |
273 | QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, | |
274 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, | |
275 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, | |
276 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, | |
277 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, | |
278 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, | |
279 | QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, | |
280 | QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, | |
281 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, | |
282 | QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, | |
283 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, | |
284 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, | |
285 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, | |
286 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, | |
287 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, | |
288 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, | |
289 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, | |
290 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, | |
291 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, | |
292 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, | |
293 | 0, | |
294 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, | |
295 | QLA82XX_HW_CRB_HUB_AGT_ADR_SN, | |
296 | 0, | |
297 | QLA82XX_HW_CRB_HUB_AGT_ADR_EG, | |
298 | 0, | |
299 | QLA82XX_HW_CRB_HUB_AGT_ADR_PS, | |
300 | QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, | |
301 | 0, | |
302 | 0, | |
303 | 0, | |
304 | 0, | |
305 | 0, | |
306 | QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, | |
307 | 0, | |
308 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, | |
309 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, | |
310 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, | |
311 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, | |
312 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, | |
313 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, | |
314 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, | |
315 | QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, | |
316 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, | |
317 | QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, | |
318 | 0, | |
319 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, | |
320 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, | |
321 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, | |
322 | QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, | |
323 | 0, | |
324 | QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, | |
325 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, | |
326 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, | |
327 | 0, | |
328 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, | |
329 | 0, | |
330 | }; | |
331 | ||
f1af6208 | 332 | /* Device states */ |
08de2844 | 333 | char *q_dev_state[] = { |
f1af6208 GM |
334 | "Unknown", |
335 | "Cold", | |
336 | "Initializing", | |
337 | "Ready", | |
338 | "Need Reset", | |
339 | "Need Quiescent", | |
340 | "Failed", | |
341 | "Quiescent", | |
342 | }; | |
343 | ||
08de2844 GM |
344 | char *qdev_state(uint32_t dev_state) |
345 | { | |
346 | return q_dev_state[dev_state]; | |
347 | } | |
348 | ||
a9083016 GM |
349 | /* |
350 | * In: 'off' is offset from CRB space in 128M pci map | |
351 | * Out: 'off' is 2M pci map addr | |
352 | * side effect: lock crb window | |
353 | */ | |
354 | static void | |
355 | qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) | |
356 | { | |
357 | u32 win_read; | |
7c3df132 | 358 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
359 | |
360 | ha->crb_win = CRB_HI(*off); | |
361 | writel(ha->crb_win, | |
362 | (void *)(CRB_WINDOW_2M + ha->nx_pcibase)); | |
363 | ||
364 | /* Read back value to make sure write has gone through before trying | |
365 | * to use it. | |
366 | */ | |
367 | win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); | |
368 | if (win_read != ha->crb_win) { | |
7c3df132 SK |
369 | ql_dbg(ql_dbg_p3p, vha, 0xb000, |
370 | "%s: Written crbwin (0x%x) " | |
371 | "!= Read crbwin (0x%x), off=0x%lx.\n", | |
372 | ha->crb_win, win_read, *off); | |
a9083016 GM |
373 | } |
374 | *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; | |
375 | } | |
376 | ||
377 | static inline unsigned long | |
378 | qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) | |
379 | { | |
7c3df132 | 380 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
381 | /* See if we are currently pointing to the region we want to use next */ |
382 | if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { | |
383 | /* No need to change window. PCIX and PCIEregs are in both | |
384 | * regs are in both windows. | |
385 | */ | |
386 | return off; | |
387 | } | |
388 | ||
389 | if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { | |
390 | /* We are in first CRB window */ | |
391 | if (ha->curr_window != 0) | |
392 | WARN_ON(1); | |
393 | return off; | |
394 | } | |
395 | ||
396 | if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { | |
397 | /* We are in second CRB window */ | |
398 | off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; | |
399 | ||
400 | if (ha->curr_window != 1) | |
401 | return off; | |
402 | ||
403 | /* We are in the QM or direct access | |
404 | * register region - do nothing | |
405 | */ | |
406 | if ((off >= QLA82XX_PCI_DIRECT_CRB) && | |
407 | (off < QLA82XX_PCI_CAMQM_MAX)) | |
408 | return off; | |
409 | } | |
410 | /* strange address given */ | |
7c3df132 SK |
411 | ql_dbg(ql_dbg_p3p, vha, 0xb001, |
412 | "%x: Warning: unm_nic_pci_set_crbwindow " | |
413 | "called with an unknown address(%llx).\n", | |
414 | QLA2XXX_DRIVER_NAME, off); | |
a9083016 GM |
415 | return off; |
416 | } | |
417 | ||
77e334d2 GM |
418 | static int |
419 | qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) | |
420 | { | |
421 | struct crb_128M_2M_sub_block_map *m; | |
422 | ||
423 | if (*off >= QLA82XX_CRB_MAX) | |
424 | return -1; | |
425 | ||
426 | if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { | |
427 | *off = (*off - QLA82XX_PCI_CAMQM) + | |
428 | QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; | |
429 | return 0; | |
430 | } | |
431 | ||
432 | if (*off < QLA82XX_PCI_CRBSPACE) | |
433 | return -1; | |
434 | ||
435 | *off -= QLA82XX_PCI_CRBSPACE; | |
436 | ||
437 | /* Try direct map */ | |
438 | m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; | |
439 | ||
440 | if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { | |
441 | *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; | |
442 | return 0; | |
443 | } | |
444 | /* Not in direct map, use crb window */ | |
445 | return 1; | |
446 | } | |
447 | ||
448 | #define CRB_WIN_LOCK_TIMEOUT 100000000 | |
449 | static int qla82xx_crb_win_lock(struct qla_hw_data *ha) | |
450 | { | |
451 | int done = 0, timeout = 0; | |
452 | ||
453 | while (!done) { | |
454 | /* acquire semaphore3 from PCI HW block */ | |
455 | done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); | |
456 | if (done == 1) | |
457 | break; | |
458 | if (timeout >= CRB_WIN_LOCK_TIMEOUT) | |
459 | return -1; | |
460 | timeout++; | |
461 | } | |
462 | qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); | |
463 | return 0; | |
464 | } | |
465 | ||
a9083016 GM |
466 | int |
467 | qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) | |
468 | { | |
469 | unsigned long flags = 0; | |
470 | int rv; | |
471 | ||
472 | rv = qla82xx_pci_get_crb_addr_2M(ha, &off); | |
473 | ||
474 | BUG_ON(rv == -1); | |
475 | ||
476 | if (rv == 1) { | |
477 | write_lock_irqsave(&ha->hw_lock, flags); | |
478 | qla82xx_crb_win_lock(ha); | |
479 | qla82xx_pci_set_crbwindow_2M(ha, &off); | |
480 | } | |
481 | ||
482 | writel(data, (void __iomem *)off); | |
483 | ||
484 | if (rv == 1) { | |
485 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); | |
486 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
487 | } | |
488 | return 0; | |
489 | } | |
490 | ||
491 | int | |
492 | qla82xx_rd_32(struct qla_hw_data *ha, ulong off) | |
493 | { | |
494 | unsigned long flags = 0; | |
495 | int rv; | |
496 | u32 data; | |
497 | ||
498 | rv = qla82xx_pci_get_crb_addr_2M(ha, &off); | |
499 | ||
500 | BUG_ON(rv == -1); | |
501 | ||
502 | if (rv == 1) { | |
503 | write_lock_irqsave(&ha->hw_lock, flags); | |
504 | qla82xx_crb_win_lock(ha); | |
505 | qla82xx_pci_set_crbwindow_2M(ha, &off); | |
506 | } | |
507 | data = RD_REG_DWORD((void __iomem *)off); | |
508 | ||
509 | if (rv == 1) { | |
510 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); | |
511 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
512 | } | |
513 | return data; | |
514 | } | |
515 | ||
a9083016 GM |
516 | #define IDC_LOCK_TIMEOUT 100000000 |
517 | int qla82xx_idc_lock(struct qla_hw_data *ha) | |
518 | { | |
519 | int i; | |
520 | int done = 0, timeout = 0; | |
521 | ||
522 | while (!done) { | |
523 | /* acquire semaphore5 from PCI HW block */ | |
524 | done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); | |
525 | if (done == 1) | |
526 | break; | |
527 | if (timeout >= IDC_LOCK_TIMEOUT) | |
528 | return -1; | |
529 | ||
530 | timeout++; | |
531 | ||
532 | /* Yield CPU */ | |
533 | if (!in_interrupt()) | |
534 | schedule(); | |
535 | else { | |
536 | for (i = 0; i < 20; i++) | |
537 | cpu_relax(); | |
538 | } | |
539 | } | |
540 | ||
541 | return 0; | |
542 | } | |
543 | ||
544 | void qla82xx_idc_unlock(struct qla_hw_data *ha) | |
545 | { | |
546 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); | |
547 | } | |
548 | ||
a9083016 GM |
549 | /* PCI Windowing for DDR regions. */ |
550 | #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ | |
551 | (((addr) <= (high)) && ((addr) >= (low))) | |
552 | /* | |
553 | * check memory access boundary. | |
554 | * used by test agent. support ddr access only for now | |
555 | */ | |
556 | static unsigned long | |
557 | qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, | |
558 | unsigned long long addr, int size) | |
559 | { | |
560 | if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, | |
561 | QLA82XX_ADDR_DDR_NET_MAX) || | |
562 | !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, | |
563 | QLA82XX_ADDR_DDR_NET_MAX) || | |
564 | ((size != 1) && (size != 2) && (size != 4) && (size != 8))) | |
565 | return 0; | |
566 | else | |
567 | return 1; | |
568 | } | |
569 | ||
570 | int qla82xx_pci_set_window_warning_count; | |
571 | ||
77e334d2 | 572 | static unsigned long |
a9083016 GM |
573 | qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) |
574 | { | |
575 | int window; | |
576 | u32 win_read; | |
7c3df132 | 577 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
578 | |
579 | if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, | |
580 | QLA82XX_ADDR_DDR_NET_MAX)) { | |
581 | /* DDR network side */ | |
582 | window = MN_WIN(addr); | |
583 | ha->ddr_mn_window = window; | |
584 | qla82xx_wr_32(ha, | |
585 | ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); | |
586 | win_read = qla82xx_rd_32(ha, | |
587 | ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); | |
588 | if ((win_read << 17) != window) { | |
7c3df132 SK |
589 | ql_dbg(ql_dbg_p3p, vha, 0xb003, |
590 | "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", | |
a9083016 GM |
591 | __func__, window, win_read); |
592 | } | |
593 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; | |
594 | } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, | |
595 | QLA82XX_ADDR_OCM0_MAX)) { | |
596 | unsigned int temp1; | |
597 | if ((addr & 0x00ff800) == 0xff800) { | |
7c3df132 | 598 | ql_log(ql_log_warn, vha, 0xb004, |
a9083016 GM |
599 | "%s: QM access not handled.\n", __func__); |
600 | addr = -1UL; | |
601 | } | |
602 | window = OCM_WIN(addr); | |
603 | ha->ddr_mn_window = window; | |
604 | qla82xx_wr_32(ha, | |
605 | ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); | |
606 | win_read = qla82xx_rd_32(ha, | |
607 | ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); | |
608 | temp1 = ((window & 0x1FF) << 7) | | |
609 | ((window & 0x0FFFE0000) >> 17); | |
610 | if (win_read != temp1) { | |
7c3df132 SK |
611 | ql_log(ql_log_warn, vha, 0xb005, |
612 | "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", | |
a9083016 GM |
613 | __func__, temp1, win_read); |
614 | } | |
615 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; | |
616 | ||
617 | } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, | |
618 | QLA82XX_P3_ADDR_QDR_NET_MAX)) { | |
619 | /* QDR network side */ | |
620 | window = MS_WIN(addr); | |
621 | ha->qdr_sn_window = window; | |
622 | qla82xx_wr_32(ha, | |
623 | ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); | |
624 | win_read = qla82xx_rd_32(ha, | |
625 | ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); | |
626 | if (win_read != window) { | |
7c3df132 SK |
627 | ql_log(ql_log_warn, vha, 0xb006, |
628 | "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", | |
a9083016 GM |
629 | __func__, window, win_read); |
630 | } | |
631 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; | |
632 | } else { | |
633 | /* | |
634 | * peg gdb frequently accesses memory that doesn't exist, | |
635 | * this limits the chit chat so debugging isn't slowed down. | |
636 | */ | |
637 | if ((qla82xx_pci_set_window_warning_count++ < 8) || | |
638 | (qla82xx_pci_set_window_warning_count%64 == 0)) { | |
7c3df132 SK |
639 | ql_log(ql_log_warn, vha, 0xb007, |
640 | "%s: Warning:%s Unknown address range!.\n", | |
641 | __func__, QLA2XXX_DRIVER_NAME); | |
a9083016 GM |
642 | } |
643 | addr = -1UL; | |
644 | } | |
645 | return addr; | |
646 | } | |
647 | ||
648 | /* check if address is in the same windows as the previous access */ | |
649 | static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, | |
650 | unsigned long long addr) | |
651 | { | |
652 | int window; | |
653 | unsigned long long qdr_max; | |
654 | ||
655 | qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; | |
656 | ||
657 | /* DDR network side */ | |
658 | if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, | |
659 | QLA82XX_ADDR_DDR_NET_MAX)) | |
660 | BUG(); | |
661 | else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, | |
662 | QLA82XX_ADDR_OCM0_MAX)) | |
663 | return 1; | |
664 | else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, | |
665 | QLA82XX_ADDR_OCM1_MAX)) | |
666 | return 1; | |
667 | else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { | |
668 | /* QDR network side */ | |
669 | window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; | |
670 | if (ha->qdr_sn_window == window) | |
671 | return 1; | |
672 | } | |
673 | return 0; | |
674 | } | |
675 | ||
676 | static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, | |
677 | u64 off, void *data, int size) | |
678 | { | |
679 | unsigned long flags; | |
f1af6208 | 680 | void *addr = NULL; |
a9083016 GM |
681 | int ret = 0; |
682 | u64 start; | |
683 | uint8_t *mem_ptr = NULL; | |
684 | unsigned long mem_base; | |
685 | unsigned long mem_page; | |
7c3df132 | 686 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
687 | |
688 | write_lock_irqsave(&ha->hw_lock, flags); | |
689 | ||
690 | /* | |
691 | * If attempting to access unknown address or straddle hw windows, | |
692 | * do not access. | |
693 | */ | |
694 | start = qla82xx_pci_set_window(ha, off); | |
695 | if ((start == -1UL) || | |
696 | (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { | |
697 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
7c3df132 SK |
698 | ql_log(ql_log_fatal, vha, 0xb008, |
699 | "%s out of bound pci memory " | |
700 | "access, offset is 0x%llx.\n", | |
701 | QLA2XXX_DRIVER_NAME, off); | |
a9083016 GM |
702 | return -1; |
703 | } | |
704 | ||
f1af6208 GM |
705 | write_unlock_irqrestore(&ha->hw_lock, flags); |
706 | mem_base = pci_resource_start(ha->pdev, 0); | |
707 | mem_page = start & PAGE_MASK; | |
708 | /* Map two pages whenever user tries to access addresses in two | |
709 | * consecutive pages. | |
710 | */ | |
711 | if (mem_page != ((start + size - 1) & PAGE_MASK)) | |
712 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); | |
713 | else | |
714 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); | |
715 | if (mem_ptr == 0UL) { | |
716 | *(u8 *)data = 0; | |
717 | return -1; | |
a9083016 | 718 | } |
f1af6208 GM |
719 | addr = mem_ptr; |
720 | addr += start & (PAGE_SIZE - 1); | |
721 | write_lock_irqsave(&ha->hw_lock, flags); | |
a9083016 GM |
722 | |
723 | switch (size) { | |
724 | case 1: | |
725 | *(u8 *)data = readb(addr); | |
726 | break; | |
727 | case 2: | |
728 | *(u16 *)data = readw(addr); | |
729 | break; | |
730 | case 4: | |
731 | *(u32 *)data = readl(addr); | |
732 | break; | |
733 | case 8: | |
734 | *(u64 *)data = readq(addr); | |
735 | break; | |
736 | default: | |
737 | ret = -1; | |
738 | break; | |
739 | } | |
740 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
741 | ||
742 | if (mem_ptr) | |
743 | iounmap(mem_ptr); | |
744 | return ret; | |
745 | } | |
746 | ||
747 | static int | |
748 | qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, | |
749 | u64 off, void *data, int size) | |
750 | { | |
751 | unsigned long flags; | |
f1af6208 | 752 | void *addr = NULL; |
a9083016 GM |
753 | int ret = 0; |
754 | u64 start; | |
755 | uint8_t *mem_ptr = NULL; | |
756 | unsigned long mem_base; | |
757 | unsigned long mem_page; | |
7c3df132 | 758 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
759 | |
760 | write_lock_irqsave(&ha->hw_lock, flags); | |
761 | ||
762 | /* | |
763 | * If attempting to access unknown address or straddle hw windows, | |
764 | * do not access. | |
765 | */ | |
766 | start = qla82xx_pci_set_window(ha, off); | |
767 | if ((start == -1UL) || | |
768 | (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { | |
769 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
7c3df132 SK |
770 | ql_log(ql_log_fatal, vha, 0xb009, |
771 | "%s out of bount memory " | |
772 | "access, offset is 0x%llx.\n", | |
773 | QLA2XXX_DRIVER_NAME, off); | |
a9083016 GM |
774 | return -1; |
775 | } | |
776 | ||
f1af6208 GM |
777 | write_unlock_irqrestore(&ha->hw_lock, flags); |
778 | mem_base = pci_resource_start(ha->pdev, 0); | |
779 | mem_page = start & PAGE_MASK; | |
780 | /* Map two pages whenever user tries to access addresses in two | |
781 | * consecutive pages. | |
782 | */ | |
783 | if (mem_page != ((start + size - 1) & PAGE_MASK)) | |
784 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); | |
785 | else | |
786 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); | |
787 | if (mem_ptr == 0UL) | |
788 | return -1; | |
a9083016 | 789 | |
f1af6208 GM |
790 | addr = mem_ptr; |
791 | addr += start & (PAGE_SIZE - 1); | |
792 | write_lock_irqsave(&ha->hw_lock, flags); | |
a9083016 GM |
793 | |
794 | switch (size) { | |
795 | case 1: | |
796 | writeb(*(u8 *)data, addr); | |
797 | break; | |
798 | case 2: | |
799 | writew(*(u16 *)data, addr); | |
800 | break; | |
801 | case 4: | |
802 | writel(*(u32 *)data, addr); | |
803 | break; | |
804 | case 8: | |
805 | writeq(*(u64 *)data, addr); | |
806 | break; | |
807 | default: | |
808 | ret = -1; | |
809 | break; | |
810 | } | |
811 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
812 | if (mem_ptr) | |
813 | iounmap(mem_ptr); | |
814 | return ret; | |
815 | } | |
816 | ||
a9083016 | 817 | #define MTU_FUDGE_FACTOR 100 |
77e334d2 GM |
818 | static unsigned long |
819 | qla82xx_decode_crb_addr(unsigned long addr) | |
a9083016 GM |
820 | { |
821 | int i; | |
822 | unsigned long base_addr, offset, pci_base; | |
823 | ||
824 | if (!qla82xx_crb_table_initialized) | |
825 | qla82xx_crb_addr_transform_setup(); | |
826 | ||
827 | pci_base = ADDR_ERROR; | |
828 | base_addr = addr & 0xfff00000; | |
829 | offset = addr & 0x000fffff; | |
830 | ||
831 | for (i = 0; i < MAX_CRB_XFORM; i++) { | |
832 | if (crb_addr_xform[i] == base_addr) { | |
833 | pci_base = i << 20; | |
834 | break; | |
835 | } | |
836 | } | |
837 | if (pci_base == ADDR_ERROR) | |
838 | return pci_base; | |
839 | return pci_base + offset; | |
840 | } | |
841 | ||
842 | static long rom_max_timeout = 100; | |
843 | static long qla82xx_rom_lock_timeout = 100; | |
844 | ||
77e334d2 | 845 | static int |
a9083016 GM |
846 | qla82xx_rom_lock(struct qla_hw_data *ha) |
847 | { | |
848 | int done = 0, timeout = 0; | |
849 | ||
850 | while (!done) { | |
851 | /* acquire semaphore2 from PCI HW block */ | |
852 | done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); | |
853 | if (done == 1) | |
854 | break; | |
855 | if (timeout >= qla82xx_rom_lock_timeout) | |
856 | return -1; | |
857 | timeout++; | |
858 | } | |
859 | qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); | |
860 | return 0; | |
861 | } | |
862 | ||
d652e093 CD |
863 | static void |
864 | qla82xx_rom_unlock(struct qla_hw_data *ha) | |
865 | { | |
866 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); | |
867 | } | |
868 | ||
77e334d2 | 869 | static int |
a9083016 GM |
870 | qla82xx_wait_rom_busy(struct qla_hw_data *ha) |
871 | { | |
872 | long timeout = 0; | |
873 | long done = 0 ; | |
7c3df132 | 874 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
875 | |
876 | while (done == 0) { | |
877 | done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); | |
878 | done &= 4; | |
879 | timeout++; | |
880 | if (timeout >= rom_max_timeout) { | |
7c3df132 SK |
881 | ql_dbg(ql_dbg_p3p, vha, 0xb00a, |
882 | "%s: Timeout reached waiting for rom busy.\n", | |
883 | QLA2XXX_DRIVER_NAME); | |
a9083016 GM |
884 | return -1; |
885 | } | |
886 | } | |
887 | return 0; | |
888 | } | |
889 | ||
77e334d2 | 890 | static int |
a9083016 GM |
891 | qla82xx_wait_rom_done(struct qla_hw_data *ha) |
892 | { | |
893 | long timeout = 0; | |
894 | long done = 0 ; | |
7c3df132 | 895 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
896 | |
897 | while (done == 0) { | |
898 | done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); | |
899 | done &= 2; | |
900 | timeout++; | |
901 | if (timeout >= rom_max_timeout) { | |
7c3df132 SK |
902 | ql_dbg(ql_dbg_p3p, vha, 0xb00b, |
903 | "%s: Timeout reached waiting for rom done.\n", | |
904 | QLA2XXX_DRIVER_NAME); | |
a9083016 GM |
905 | return -1; |
906 | } | |
907 | } | |
908 | return 0; | |
909 | } | |
910 | ||
77e334d2 | 911 | static int |
a9083016 GM |
912 | qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) |
913 | { | |
7c3df132 SK |
914 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
915 | ||
a9083016 GM |
916 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); |
917 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); | |
918 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); | |
919 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); | |
920 | qla82xx_wait_rom_busy(ha); | |
921 | if (qla82xx_wait_rom_done(ha)) { | |
7c3df132 SK |
922 | ql_log(ql_log_fatal, vha, 0x00ba, |
923 | "Error waiting for rom done.\n"); | |
a9083016 GM |
924 | return -1; |
925 | } | |
926 | /* Reset abyte_cnt and dummy_byte_cnt */ | |
927 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); | |
928 | udelay(10); | |
929 | cond_resched(); | |
930 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); | |
931 | *valp = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); | |
932 | return 0; | |
933 | } | |
934 | ||
77e334d2 | 935 | static int |
a9083016 GM |
936 | qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) |
937 | { | |
938 | int ret, loops = 0; | |
7c3df132 | 939 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
940 | |
941 | while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { | |
942 | udelay(100); | |
943 | schedule(); | |
944 | loops++; | |
945 | } | |
946 | if (loops >= 50000) { | |
7c3df132 SK |
947 | ql_log(ql_log_fatal, vha, 0x00b9, |
948 | "Failed to aquire SEM2 lock.\n"); | |
a9083016 GM |
949 | return -1; |
950 | } | |
951 | ret = qla82xx_do_rom_fast_read(ha, addr, valp); | |
d652e093 | 952 | qla82xx_rom_unlock(ha); |
a9083016 GM |
953 | return ret; |
954 | } | |
955 | ||
77e334d2 | 956 | static int |
a9083016 GM |
957 | qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) |
958 | { | |
7c3df132 | 959 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
960 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); |
961 | qla82xx_wait_rom_busy(ha); | |
962 | if (qla82xx_wait_rom_done(ha)) { | |
7c3df132 SK |
963 | ql_log(ql_log_warn, vha, 0xb00c, |
964 | "Error waiting for rom done.\n"); | |
a9083016 GM |
965 | return -1; |
966 | } | |
967 | *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); | |
968 | return 0; | |
969 | } | |
970 | ||
77e334d2 | 971 | static int |
a9083016 GM |
972 | qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) |
973 | { | |
974 | long timeout = 0; | |
975 | uint32_t done = 1 ; | |
976 | uint32_t val; | |
977 | int ret = 0; | |
7c3df132 | 978 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
979 | |
980 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); | |
981 | while ((done != 0) && (ret == 0)) { | |
982 | ret = qla82xx_read_status_reg(ha, &val); | |
983 | done = val & 1; | |
984 | timeout++; | |
985 | udelay(10); | |
986 | cond_resched(); | |
987 | if (timeout >= 50000) { | |
7c3df132 SK |
988 | ql_log(ql_log_warn, vha, 0xb00d, |
989 | "Timeout reached waiting for write finish.\n"); | |
a9083016 GM |
990 | return -1; |
991 | } | |
992 | } | |
993 | return ret; | |
994 | } | |
995 | ||
77e334d2 | 996 | static int |
a9083016 GM |
997 | qla82xx_flash_set_write_enable(struct qla_hw_data *ha) |
998 | { | |
999 | uint32_t val; | |
1000 | qla82xx_wait_rom_busy(ha); | |
1001 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); | |
1002 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); | |
1003 | qla82xx_wait_rom_busy(ha); | |
1004 | if (qla82xx_wait_rom_done(ha)) | |
1005 | return -1; | |
1006 | if (qla82xx_read_status_reg(ha, &val) != 0) | |
1007 | return -1; | |
1008 | if ((val & 2) != 2) | |
1009 | return -1; | |
1010 | return 0; | |
1011 | } | |
1012 | ||
77e334d2 | 1013 | static int |
a9083016 GM |
1014 | qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) |
1015 | { | |
7c3df132 | 1016 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
1017 | if (qla82xx_flash_set_write_enable(ha)) |
1018 | return -1; | |
1019 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); | |
1020 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); | |
1021 | if (qla82xx_wait_rom_done(ha)) { | |
7c3df132 SK |
1022 | ql_log(ql_log_warn, vha, 0xb00e, |
1023 | "Error waiting for rom done.\n"); | |
a9083016 GM |
1024 | return -1; |
1025 | } | |
1026 | return qla82xx_flash_wait_write_finish(ha); | |
1027 | } | |
1028 | ||
77e334d2 | 1029 | static int |
a9083016 GM |
1030 | qla82xx_write_disable_flash(struct qla_hw_data *ha) |
1031 | { | |
7c3df132 | 1032 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
1033 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); |
1034 | if (qla82xx_wait_rom_done(ha)) { | |
7c3df132 SK |
1035 | ql_log(ql_log_warn, vha, 0xb00f, |
1036 | "Error waiting for rom done.\n"); | |
a9083016 GM |
1037 | return -1; |
1038 | } | |
1039 | return 0; | |
1040 | } | |
1041 | ||
77e334d2 | 1042 | static int |
a9083016 GM |
1043 | ql82xx_rom_lock_d(struct qla_hw_data *ha) |
1044 | { | |
1045 | int loops = 0; | |
7c3df132 SK |
1046 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
1047 | ||
a9083016 GM |
1048 | while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { |
1049 | udelay(100); | |
1050 | cond_resched(); | |
1051 | loops++; | |
1052 | } | |
1053 | if (loops >= 50000) { | |
7c3df132 SK |
1054 | ql_log(ql_log_warn, vha, 0xb010, |
1055 | "ROM lock failed.\n"); | |
a9083016 GM |
1056 | return -1; |
1057 | } | |
1058 | return 0;; | |
1059 | } | |
1060 | ||
77e334d2 | 1061 | static int |
a9083016 GM |
1062 | qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, |
1063 | uint32_t data) | |
1064 | { | |
1065 | int ret = 0; | |
7c3df132 | 1066 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
1067 | |
1068 | ret = ql82xx_rom_lock_d(ha); | |
1069 | if (ret < 0) { | |
7c3df132 SK |
1070 | ql_log(ql_log_warn, vha, 0xb011, |
1071 | "ROM lock failed.\n"); | |
a9083016 GM |
1072 | return ret; |
1073 | } | |
1074 | ||
1075 | if (qla82xx_flash_set_write_enable(ha)) | |
1076 | goto done_write; | |
1077 | ||
1078 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); | |
1079 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); | |
1080 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); | |
1081 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); | |
1082 | qla82xx_wait_rom_busy(ha); | |
1083 | if (qla82xx_wait_rom_done(ha)) { | |
7c3df132 SK |
1084 | ql_log(ql_log_warn, vha, 0xb012, |
1085 | "Error waiting for rom done.\n"); | |
a9083016 GM |
1086 | ret = -1; |
1087 | goto done_write; | |
1088 | } | |
1089 | ||
1090 | ret = qla82xx_flash_wait_write_finish(ha); | |
1091 | ||
1092 | done_write: | |
d652e093 | 1093 | qla82xx_rom_unlock(ha); |
a9083016 GM |
1094 | return ret; |
1095 | } | |
1096 | ||
1097 | /* This routine does CRB initialize sequence | |
1098 | * to put the ISP into operational state | |
1099 | */ | |
77e334d2 GM |
1100 | static int |
1101 | qla82xx_pinit_from_rom(scsi_qla_host_t *vha) | |
a9083016 GM |
1102 | { |
1103 | int addr, val; | |
1104 | int i ; | |
1105 | struct crb_addr_pair *buf; | |
1106 | unsigned long off; | |
1107 | unsigned offset, n; | |
1108 | struct qla_hw_data *ha = vha->hw; | |
1109 | ||
1110 | struct crb_addr_pair { | |
1111 | long addr; | |
1112 | long data; | |
1113 | }; | |
1114 | ||
1115 | /* Halt all the indiviual PEGs and other blocks of the ISP */ | |
1116 | qla82xx_rom_lock(ha); | |
c9e8fd5c | 1117 | |
02be2215 GM |
1118 | /* disable all I2Q */ |
1119 | qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); | |
1120 | qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); | |
1121 | qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); | |
1122 | qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); | |
1123 | qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); | |
1124 | qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); | |
1125 | ||
1126 | /* disable all niu interrupts */ | |
c9e8fd5c MI |
1127 | qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); |
1128 | /* disable xge rx/tx */ | |
1129 | qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); | |
1130 | /* disable xg1 rx/tx */ | |
1131 | qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); | |
02be2215 GM |
1132 | /* disable sideband mac */ |
1133 | qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); | |
1134 | /* disable ap0 mac */ | |
1135 | qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); | |
1136 | /* disable ap1 mac */ | |
1137 | qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); | |
c9e8fd5c MI |
1138 | |
1139 | /* halt sre */ | |
1140 | val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); | |
1141 | qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); | |
1142 | ||
1143 | /* halt epg */ | |
1144 | qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); | |
1145 | ||
1146 | /* halt timers */ | |
1147 | qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); | |
1148 | qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); | |
1149 | qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); | |
1150 | qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); | |
1151 | qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); | |
02be2215 | 1152 | qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); |
c9e8fd5c MI |
1153 | |
1154 | /* halt pegs */ | |
1155 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); | |
1156 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); | |
1157 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); | |
1158 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); | |
1159 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); | |
02be2215 | 1160 | msleep(20); |
c9e8fd5c MI |
1161 | |
1162 | /* big hammer */ | |
a9083016 GM |
1163 | if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) |
1164 | /* don't reset CAM block on reset */ | |
1165 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); | |
1166 | else | |
1167 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); | |
c9e8fd5c MI |
1168 | |
1169 | /* reset ms */ | |
1170 | val = qla82xx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4); | |
1171 | val |= (1 << 1); | |
1172 | qla82xx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val); | |
1173 | msleep(20); | |
1174 | ||
1175 | /* unreset ms */ | |
1176 | val = qla82xx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4); | |
1177 | val &= ~(1 << 1); | |
1178 | qla82xx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val); | |
1179 | msleep(20); | |
1180 | ||
d652e093 | 1181 | qla82xx_rom_unlock(ha); |
a9083016 GM |
1182 | |
1183 | /* Read the signature value from the flash. | |
1184 | * Offset 0: Contain signature (0xcafecafe) | |
1185 | * Offset 4: Offset and number of addr/value pairs | |
1186 | * that present in CRB initialize sequence | |
1187 | */ | |
1188 | if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || | |
1189 | qla82xx_rom_fast_read(ha, 4, &n) != 0) { | |
7c3df132 SK |
1190 | ql_log(ql_log_fatal, vha, 0x006e, |
1191 | "Error Reading crb_init area: n: %08x.\n", n); | |
a9083016 GM |
1192 | return -1; |
1193 | } | |
1194 | ||
1195 | /* Offset in flash = lower 16 bits | |
1196 | * Number of enteries = upper 16 bits | |
1197 | */ | |
1198 | offset = n & 0xffffU; | |
1199 | n = (n >> 16) & 0xffffU; | |
1200 | ||
1201 | /* number of addr/value pair should not exceed 1024 enteries */ | |
1202 | if (n >= 1024) { | |
7c3df132 SK |
1203 | ql_log(ql_log_fatal, vha, 0x0071, |
1204 | "Card flash not initialized:n=0x%x.\n", n); | |
a9083016 GM |
1205 | return -1; |
1206 | } | |
1207 | ||
7c3df132 SK |
1208 | ql_log(ql_log_info, vha, 0x0072, |
1209 | "%d CRB init values found in ROM.\n", n); | |
a9083016 GM |
1210 | |
1211 | buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); | |
1212 | if (buf == NULL) { | |
7c3df132 SK |
1213 | ql_log(ql_log_fatal, vha, 0x010c, |
1214 | "Unable to allocate memory.\n"); | |
a9083016 GM |
1215 | return -1; |
1216 | } | |
1217 | ||
1218 | for (i = 0; i < n; i++) { | |
1219 | if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || | |
1220 | qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { | |
1221 | kfree(buf); | |
1222 | return -1; | |
1223 | } | |
1224 | ||
1225 | buf[i].addr = addr; | |
1226 | buf[i].data = val; | |
1227 | } | |
1228 | ||
1229 | for (i = 0; i < n; i++) { | |
1230 | /* Translate internal CRB initialization | |
1231 | * address to PCI bus address | |
1232 | */ | |
1233 | off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + | |
1234 | QLA82XX_PCI_CRBSPACE; | |
1235 | /* Not all CRB addr/value pair to be written, | |
1236 | * some of them are skipped | |
1237 | */ | |
1238 | ||
1239 | /* skipping cold reboot MAGIC */ | |
1240 | if (off == QLA82XX_CAM_RAM(0x1fc)) | |
1241 | continue; | |
1242 | ||
1243 | /* do not reset PCI */ | |
1244 | if (off == (ROMUSB_GLB + 0xbc)) | |
1245 | continue; | |
1246 | ||
1247 | /* skip core clock, so that firmware can increase the clock */ | |
1248 | if (off == (ROMUSB_GLB + 0xc8)) | |
1249 | continue; | |
1250 | ||
1251 | /* skip the function enable register */ | |
1252 | if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) | |
1253 | continue; | |
1254 | ||
1255 | if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) | |
1256 | continue; | |
1257 | ||
1258 | if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) | |
1259 | continue; | |
1260 | ||
1261 | if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) | |
1262 | continue; | |
1263 | ||
1264 | if (off == ADDR_ERROR) { | |
7c3df132 SK |
1265 | ql_log(ql_log_fatal, vha, 0x0116, |
1266 | "Unknow addr: 0x%08lx.\n", buf[i].addr); | |
a9083016 GM |
1267 | continue; |
1268 | } | |
1269 | ||
a9083016 GM |
1270 | qla82xx_wr_32(ha, off, buf[i].data); |
1271 | ||
1272 | /* ISP requires much bigger delay to settle down, | |
1273 | * else crb_window returns 0xffffffff | |
1274 | */ | |
1275 | if (off == QLA82XX_ROMUSB_GLB_SW_RESET) | |
1276 | msleep(1000); | |
1277 | ||
1278 | /* ISP requires millisec delay between | |
1279 | * successive CRB register updation | |
1280 | */ | |
1281 | msleep(1); | |
1282 | } | |
1283 | ||
1284 | kfree(buf); | |
1285 | ||
1286 | /* Resetting the data and instruction cache */ | |
1287 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); | |
1288 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); | |
1289 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); | |
1290 | ||
1291 | /* Clear all protocol processing engines */ | |
1292 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); | |
1293 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); | |
1294 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); | |
1295 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); | |
1296 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); | |
1297 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); | |
1298 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); | |
1299 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); | |
1300 | return 0; | |
1301 | } | |
1302 | ||
77e334d2 GM |
1303 | static int |
1304 | qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, | |
1305 | u64 off, void *data, int size) | |
1306 | { | |
1307 | int i, j, ret = 0, loop, sz[2], off0; | |
1308 | int scale, shift_amount, startword; | |
1309 | uint32_t temp; | |
1310 | uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; | |
1311 | ||
1312 | /* | |
1313 | * If not MN, go check for MS or invalid. | |
1314 | */ | |
1315 | if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) | |
1316 | mem_crb = QLA82XX_CRB_QDR_NET; | |
1317 | else { | |
1318 | mem_crb = QLA82XX_CRB_DDR_NET; | |
1319 | if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) | |
1320 | return qla82xx_pci_mem_write_direct(ha, | |
1321 | off, data, size); | |
1322 | } | |
1323 | ||
1324 | off0 = off & 0x7; | |
1325 | sz[0] = (size < (8 - off0)) ? size : (8 - off0); | |
1326 | sz[1] = size - sz[0]; | |
1327 | ||
1328 | off8 = off & 0xfffffff0; | |
1329 | loop = (((off & 0xf) + size - 1) >> 4) + 1; | |
1330 | shift_amount = 4; | |
1331 | scale = 2; | |
1332 | startword = (off & 0xf)/8; | |
1333 | ||
1334 | for (i = 0; i < loop; i++) { | |
1335 | if (qla82xx_pci_mem_read_2M(ha, off8 + | |
1336 | (i << shift_amount), &word[i * scale], 8)) | |
1337 | return -1; | |
1338 | } | |
1339 | ||
1340 | switch (size) { | |
1341 | case 1: | |
1342 | tmpw = *((uint8_t *)data); | |
1343 | break; | |
1344 | case 2: | |
1345 | tmpw = *((uint16_t *)data); | |
1346 | break; | |
1347 | case 4: | |
1348 | tmpw = *((uint32_t *)data); | |
1349 | break; | |
1350 | case 8: | |
1351 | default: | |
1352 | tmpw = *((uint64_t *)data); | |
1353 | break; | |
1354 | } | |
1355 | ||
1356 | if (sz[0] == 8) { | |
1357 | word[startword] = tmpw; | |
1358 | } else { | |
1359 | word[startword] &= | |
1360 | ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); | |
1361 | word[startword] |= tmpw << (off0 * 8); | |
1362 | } | |
1363 | if (sz[1] != 0) { | |
1364 | word[startword+1] &= ~(~0ULL << (sz[1] * 8)); | |
1365 | word[startword+1] |= tmpw >> (sz[0] * 8); | |
1366 | } | |
1367 | ||
77e334d2 GM |
1368 | for (i = 0; i < loop; i++) { |
1369 | temp = off8 + (i << shift_amount); | |
1370 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); | |
1371 | temp = 0; | |
1372 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); | |
1373 | temp = word[i * scale] & 0xffffffff; | |
1374 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); | |
1375 | temp = (word[i * scale] >> 32) & 0xffffffff; | |
1376 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); | |
1377 | temp = word[i*scale + 1] & 0xffffffff; | |
1378 | qla82xx_wr_32(ha, mem_crb + | |
1379 | MIU_TEST_AGT_WRDATA_UPPER_LO, temp); | |
1380 | temp = (word[i*scale + 1] >> 32) & 0xffffffff; | |
1381 | qla82xx_wr_32(ha, mem_crb + | |
1382 | MIU_TEST_AGT_WRDATA_UPPER_HI, temp); | |
1383 | ||
1384 | temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; | |
1385 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); | |
1386 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; | |
1387 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); | |
1388 | ||
1389 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
1390 | temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); | |
1391 | if ((temp & MIU_TA_CTL_BUSY) == 0) | |
1392 | break; | |
1393 | } | |
1394 | ||
1395 | if (j >= MAX_CTL_CHECK) { | |
1396 | if (printk_ratelimit()) | |
1397 | dev_err(&ha->pdev->dev, | |
7c3df132 | 1398 | "failed to write through agent.\n"); |
77e334d2 GM |
1399 | ret = -1; |
1400 | break; | |
1401 | } | |
1402 | } | |
1403 | ||
1404 | return ret; | |
1405 | } | |
1406 | ||
1407 | static int | |
a9083016 GM |
1408 | qla82xx_fw_load_from_flash(struct qla_hw_data *ha) |
1409 | { | |
1410 | int i; | |
1411 | long size = 0; | |
9c2b2975 HZ |
1412 | long flashaddr = ha->flt_region_bootload << 2; |
1413 | long memaddr = BOOTLD_START; | |
a9083016 GM |
1414 | u64 data; |
1415 | u32 high, low; | |
1416 | size = (IMAGE_START - BOOTLD_START) / 8; | |
1417 | ||
1418 | for (i = 0; i < size; i++) { | |
1419 | if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || | |
1420 | (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { | |
1421 | return -1; | |
1422 | } | |
1423 | data = ((u64)high << 32) | low ; | |
1424 | qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); | |
1425 | flashaddr += 8; | |
1426 | memaddr += 8; | |
1427 | ||
1428 | if (i % 0x1000 == 0) | |
1429 | msleep(1); | |
1430 | } | |
1431 | udelay(100); | |
1432 | read_lock(&ha->hw_lock); | |
3711333d GM |
1433 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); |
1434 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); | |
a9083016 GM |
1435 | read_unlock(&ha->hw_lock); |
1436 | return 0; | |
1437 | } | |
1438 | ||
1439 | int | |
1440 | qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, | |
1441 | u64 off, void *data, int size) | |
1442 | { | |
1443 | int i, j = 0, k, start, end, loop, sz[2], off0[2]; | |
1444 | int shift_amount; | |
1445 | uint32_t temp; | |
1446 | uint64_t off8, val, mem_crb, word[2] = {0, 0}; | |
1447 | ||
1448 | /* | |
1449 | * If not MN, go check for MS or invalid. | |
1450 | */ | |
1451 | ||
1452 | if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) | |
1453 | mem_crb = QLA82XX_CRB_QDR_NET; | |
1454 | else { | |
1455 | mem_crb = QLA82XX_CRB_DDR_NET; | |
1456 | if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) | |
1457 | return qla82xx_pci_mem_read_direct(ha, | |
1458 | off, data, size); | |
1459 | } | |
1460 | ||
3711333d GM |
1461 | off8 = off & 0xfffffff0; |
1462 | off0[0] = off & 0xf; | |
1463 | sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); | |
1464 | shift_amount = 4; | |
a9083016 GM |
1465 | loop = ((off0[0] + size - 1) >> shift_amount) + 1; |
1466 | off0[1] = 0; | |
1467 | sz[1] = size - sz[0]; | |
1468 | ||
a9083016 GM |
1469 | for (i = 0; i < loop; i++) { |
1470 | temp = off8 + (i << shift_amount); | |
1471 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); | |
1472 | temp = 0; | |
1473 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); | |
1474 | temp = MIU_TA_CTL_ENABLE; | |
1475 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); | |
1476 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; | |
1477 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); | |
1478 | ||
1479 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
1480 | temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); | |
1481 | if ((temp & MIU_TA_CTL_BUSY) == 0) | |
1482 | break; | |
1483 | } | |
1484 | ||
1485 | if (j >= MAX_CTL_CHECK) { | |
1486 | if (printk_ratelimit()) | |
1487 | dev_err(&ha->pdev->dev, | |
7c3df132 | 1488 | "failed to read through agent.\n"); |
a9083016 GM |
1489 | break; |
1490 | } | |
1491 | ||
1492 | start = off0[i] >> 2; | |
1493 | end = (off0[i] + sz[i] - 1) >> 2; | |
1494 | for (k = start; k <= end; k++) { | |
1495 | temp = qla82xx_rd_32(ha, | |
1496 | mem_crb + MIU_TEST_AGT_RDDATA(k)); | |
1497 | word[i] |= ((uint64_t)temp << (32 * (k & 1))); | |
1498 | } | |
1499 | } | |
1500 | ||
a9083016 GM |
1501 | if (j >= MAX_CTL_CHECK) |
1502 | return -1; | |
1503 | ||
1504 | if ((off0[0] & 7) == 0) { | |
1505 | val = word[0]; | |
1506 | } else { | |
1507 | val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | | |
1508 | ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); | |
1509 | } | |
1510 | ||
1511 | switch (size) { | |
1512 | case 1: | |
1513 | *(uint8_t *)data = val; | |
1514 | break; | |
1515 | case 2: | |
1516 | *(uint16_t *)data = val; | |
1517 | break; | |
1518 | case 4: | |
1519 | *(uint32_t *)data = val; | |
1520 | break; | |
1521 | case 8: | |
1522 | *(uint64_t *)data = val; | |
1523 | break; | |
1524 | } | |
1525 | return 0; | |
1526 | } | |
1527 | ||
a9083016 | 1528 | |
9c2b2975 HZ |
1529 | static struct qla82xx_uri_table_desc * |
1530 | qla82xx_get_table_desc(const u8 *unirom, int section) | |
1531 | { | |
1532 | uint32_t i; | |
1533 | struct qla82xx_uri_table_desc *directory = | |
1534 | (struct qla82xx_uri_table_desc *)&unirom[0]; | |
1535 | __le32 offset; | |
1536 | __le32 tab_type; | |
1537 | __le32 entries = cpu_to_le32(directory->num_entries); | |
1538 | ||
1539 | for (i = 0; i < entries; i++) { | |
1540 | offset = cpu_to_le32(directory->findex) + | |
1541 | (i * cpu_to_le32(directory->entry_size)); | |
1542 | tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8)); | |
1543 | ||
1544 | if (tab_type == section) | |
1545 | return (struct qla82xx_uri_table_desc *)&unirom[offset]; | |
1546 | } | |
1547 | ||
1548 | return NULL; | |
1549 | } | |
1550 | ||
1551 | static struct qla82xx_uri_data_desc * | |
1552 | qla82xx_get_data_desc(struct qla_hw_data *ha, | |
1553 | u32 section, u32 idx_offset) | |
1554 | { | |
1555 | const u8 *unirom = ha->hablob->fw->data; | |
1556 | int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset)); | |
1557 | struct qla82xx_uri_table_desc *tab_desc = NULL; | |
1558 | __le32 offset; | |
1559 | ||
1560 | tab_desc = qla82xx_get_table_desc(unirom, section); | |
1561 | if (!tab_desc) | |
1562 | return NULL; | |
1563 | ||
1564 | offset = cpu_to_le32(tab_desc->findex) + | |
1565 | (cpu_to_le32(tab_desc->entry_size) * idx); | |
1566 | ||
1567 | return (struct qla82xx_uri_data_desc *)&unirom[offset]; | |
1568 | } | |
1569 | ||
1570 | static u8 * | |
1571 | qla82xx_get_bootld_offset(struct qla_hw_data *ha) | |
1572 | { | |
1573 | u32 offset = BOOTLD_START; | |
1574 | struct qla82xx_uri_data_desc *uri_desc = NULL; | |
1575 | ||
1576 | if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { | |
1577 | uri_desc = qla82xx_get_data_desc(ha, | |
1578 | QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF); | |
1579 | if (uri_desc) | |
1580 | offset = cpu_to_le32(uri_desc->findex); | |
1581 | } | |
1582 | ||
1583 | return (u8 *)&ha->hablob->fw->data[offset]; | |
1584 | } | |
1585 | ||
1586 | static __le32 | |
1587 | qla82xx_get_fw_size(struct qla_hw_data *ha) | |
1588 | { | |
1589 | struct qla82xx_uri_data_desc *uri_desc = NULL; | |
1590 | ||
1591 | if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { | |
1592 | uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, | |
1593 | QLA82XX_URI_FIRMWARE_IDX_OFF); | |
1594 | if (uri_desc) | |
1595 | return cpu_to_le32(uri_desc->size); | |
1596 | } | |
1597 | ||
1598 | return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]); | |
1599 | } | |
1600 | ||
1601 | static u8 * | |
1602 | qla82xx_get_fw_offs(struct qla_hw_data *ha) | |
1603 | { | |
1604 | u32 offset = IMAGE_START; | |
1605 | struct qla82xx_uri_data_desc *uri_desc = NULL; | |
1606 | ||
1607 | if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) { | |
1608 | uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW, | |
1609 | QLA82XX_URI_FIRMWARE_IDX_OFF); | |
1610 | if (uri_desc) | |
1611 | offset = cpu_to_le32(uri_desc->findex); | |
1612 | } | |
1613 | ||
1614 | return (u8 *)&ha->hablob->fw->data[offset]; | |
1615 | } | |
1616 | ||
a9083016 GM |
1617 | /* PCI related functions */ |
1618 | char * | |
1619 | qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str) | |
1620 | { | |
1621 | int pcie_reg; | |
1622 | struct qla_hw_data *ha = vha->hw; | |
1623 | char lwstr[6]; | |
1624 | uint16_t lnk; | |
1625 | ||
1626 | pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); | |
1627 | pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk); | |
1628 | ha->link_width = (lnk >> 4) & 0x3f; | |
1629 | ||
1630 | strcpy(str, "PCIe ("); | |
1631 | strcat(str, "2.5Gb/s "); | |
1632 | snprintf(lwstr, sizeof(lwstr), "x%d)", ha->link_width); | |
1633 | strcat(str, lwstr); | |
1634 | return str; | |
1635 | } | |
1636 | ||
1637 | int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) | |
1638 | { | |
1639 | unsigned long val = 0; | |
1640 | u32 control; | |
1641 | ||
1642 | switch (region) { | |
1643 | case 0: | |
1644 | val = 0; | |
1645 | break; | |
1646 | case 1: | |
1647 | pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); | |
1648 | val = control + QLA82XX_MSIX_TBL_SPACE; | |
1649 | break; | |
1650 | } | |
1651 | return val; | |
1652 | } | |
1653 | ||
a9083016 GM |
1654 | |
1655 | int | |
1656 | qla82xx_iospace_config(struct qla_hw_data *ha) | |
1657 | { | |
1658 | uint32_t len = 0; | |
1659 | ||
1660 | if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { | |
7c3df132 SK |
1661 | ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, |
1662 | "Failed to reserver selected regions.\n"); | |
a9083016 GM |
1663 | goto iospace_error_exit; |
1664 | } | |
1665 | ||
1666 | /* Use MMIO operations for all accesses. */ | |
1667 | if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { | |
7c3df132 SK |
1668 | ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, |
1669 | "Region #0 not an MMIO resource, aborting.\n"); | |
a9083016 GM |
1670 | goto iospace_error_exit; |
1671 | } | |
1672 | ||
1673 | len = pci_resource_len(ha->pdev, 0); | |
1674 | ha->nx_pcibase = | |
1675 | (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); | |
1676 | if (!ha->nx_pcibase) { | |
7c3df132 SK |
1677 | ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, |
1678 | "Cannot remap pcibase MMIO, aborting.\n"); | |
a9083016 GM |
1679 | pci_release_regions(ha->pdev); |
1680 | goto iospace_error_exit; | |
1681 | } | |
1682 | ||
1683 | /* Mapping of IO base pointer */ | |
1684 | ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase + | |
1685 | 0xbc000 + (ha->pdev->devfn << 11)); | |
1686 | ||
1687 | if (!ql2xdbwr) { | |
1688 | ha->nxdb_wr_ptr = | |
1689 | (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + | |
1690 | (ha->pdev->devfn << 12)), 4); | |
1691 | if (!ha->nxdb_wr_ptr) { | |
7c3df132 SK |
1692 | ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, |
1693 | "Cannot remap MMIO, aborting.\n"); | |
a9083016 GM |
1694 | pci_release_regions(ha->pdev); |
1695 | goto iospace_error_exit; | |
1696 | } | |
1697 | ||
1698 | /* Mapping of IO base pointer, | |
1699 | * door bell read and write pointer | |
1700 | */ | |
1701 | ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + | |
1702 | (ha->pdev->devfn * 8); | |
1703 | } else { | |
1704 | ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? | |
1705 | QLA82XX_CAMRAM_DB1 : | |
1706 | QLA82XX_CAMRAM_DB2); | |
1707 | } | |
1708 | ||
1709 | ha->max_req_queues = ha->max_rsp_queues = 1; | |
1710 | ha->msix_count = ha->max_rsp_queues + 1; | |
7c3df132 SK |
1711 | ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, |
1712 | "nx_pci_base=%p iobase=%p " | |
1713 | "max_req_queues=%d msix_count=%d.\n", | |
1714 | ha->nx_pcibase, ha->iobase, | |
1715 | ha->max_req_queues, ha->msix_count); | |
1716 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, | |
1717 | "nx_pci_base=%p iobase=%p " | |
1718 | "max_req_queues=%d msix_count=%d.\n", | |
1719 | ha->nx_pcibase, ha->iobase, | |
1720 | ha->max_req_queues, ha->msix_count); | |
a9083016 GM |
1721 | return 0; |
1722 | ||
1723 | iospace_error_exit: | |
1724 | return -ENOMEM; | |
1725 | } | |
1726 | ||
1727 | /* GS related functions */ | |
1728 | ||
1729 | /* Initialization related functions */ | |
1730 | ||
1731 | /** | |
1732 | * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. | |
1733 | * @ha: HA context | |
1734 | * | |
1735 | * Returns 0 on success. | |
1736 | */ | |
1737 | int | |
1738 | qla82xx_pci_config(scsi_qla_host_t *vha) | |
1739 | { | |
1740 | struct qla_hw_data *ha = vha->hw; | |
1741 | int ret; | |
1742 | ||
1743 | pci_set_master(ha->pdev); | |
1744 | ret = pci_set_mwi(ha->pdev); | |
1745 | ha->chip_revision = ha->pdev->revision; | |
7c3df132 SK |
1746 | ql_dbg(ql_dbg_init, vha, 0x0043, |
1747 | "Chip revision:%ld.\n", | |
1748 | ha->chip_revision); | |
a9083016 GM |
1749 | return 0; |
1750 | } | |
1751 | ||
1752 | /** | |
1753 | * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. | |
1754 | * @ha: HA context | |
1755 | * | |
1756 | * Returns 0 on success. | |
1757 | */ | |
1758 | void | |
1759 | qla82xx_reset_chip(scsi_qla_host_t *vha) | |
1760 | { | |
1761 | struct qla_hw_data *ha = vha->hw; | |
1762 | ha->isp_ops->disable_intrs(ha); | |
1763 | } | |
1764 | ||
1765 | void qla82xx_config_rings(struct scsi_qla_host *vha) | |
1766 | { | |
1767 | struct qla_hw_data *ha = vha->hw; | |
1768 | struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; | |
1769 | struct init_cb_81xx *icb; | |
1770 | struct req_que *req = ha->req_q_map[0]; | |
1771 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
1772 | ||
1773 | /* Setup ring parameters in initialization control block. */ | |
1774 | icb = (struct init_cb_81xx *)ha->init_cb; | |
1775 | icb->request_q_outpointer = __constant_cpu_to_le16(0); | |
1776 | icb->response_q_inpointer = __constant_cpu_to_le16(0); | |
1777 | icb->request_q_length = cpu_to_le16(req->length); | |
1778 | icb->response_q_length = cpu_to_le16(rsp->length); | |
1779 | icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); | |
1780 | icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); | |
1781 | icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); | |
1782 | icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); | |
1783 | ||
a9083016 GM |
1784 | WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); |
1785 | WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); | |
1786 | WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); | |
1787 | } | |
1788 | ||
f1af6208 GM |
1789 | void qla82xx_reset_adapter(struct scsi_qla_host *vha) |
1790 | { | |
1791 | struct qla_hw_data *ha = vha->hw; | |
1792 | vha->flags.online = 0; | |
1793 | qla2x00_try_to_stop_firmware(vha); | |
1794 | ha->isp_ops->disable_intrs(ha); | |
1795 | } | |
1796 | ||
77e334d2 GM |
1797 | static int |
1798 | qla82xx_fw_load_from_blob(struct qla_hw_data *ha) | |
a9083016 GM |
1799 | { |
1800 | u64 *ptr64; | |
1801 | u32 i, flashaddr, size; | |
1802 | __le64 data; | |
1803 | ||
1804 | size = (IMAGE_START - BOOTLD_START) / 8; | |
1805 | ||
9c2b2975 | 1806 | ptr64 = (u64 *)qla82xx_get_bootld_offset(ha); |
a9083016 GM |
1807 | flashaddr = BOOTLD_START; |
1808 | ||
1809 | for (i = 0; i < size; i++) { | |
1810 | data = cpu_to_le64(ptr64[i]); | |
9c2b2975 HZ |
1811 | if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) |
1812 | return -EIO; | |
a9083016 GM |
1813 | flashaddr += 8; |
1814 | } | |
1815 | ||
a9083016 | 1816 | flashaddr = FLASH_ADDR_START; |
9c2b2975 HZ |
1817 | size = (__force u32)qla82xx_get_fw_size(ha) / 8; |
1818 | ptr64 = (u64 *)qla82xx_get_fw_offs(ha); | |
a9083016 GM |
1819 | |
1820 | for (i = 0; i < size; i++) { | |
1821 | data = cpu_to_le64(ptr64[i]); | |
1822 | ||
1823 | if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) | |
1824 | return -EIO; | |
1825 | flashaddr += 8; | |
1826 | } | |
9c2b2975 | 1827 | udelay(100); |
a9083016 GM |
1828 | |
1829 | /* Write a magic value to CAMRAM register | |
1830 | * at a specified offset to indicate | |
1831 | * that all data is written and | |
1832 | * ready for firmware to initialize. | |
1833 | */ | |
9c2b2975 | 1834 | qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); |
a9083016 | 1835 | |
9c2b2975 | 1836 | read_lock(&ha->hw_lock); |
3711333d GM |
1837 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); |
1838 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); | |
9c2b2975 HZ |
1839 | read_unlock(&ha->hw_lock); |
1840 | return 0; | |
1841 | } | |
1842 | ||
1843 | static int | |
1844 | qla82xx_set_product_offset(struct qla_hw_data *ha) | |
1845 | { | |
1846 | struct qla82xx_uri_table_desc *ptab_desc = NULL; | |
1847 | const uint8_t *unirom = ha->hablob->fw->data; | |
1848 | uint32_t i; | |
1849 | __le32 entries; | |
1850 | __le32 flags, file_chiprev, offset; | |
1851 | uint8_t chiprev = ha->chip_revision; | |
1852 | /* Hardcoding mn_present flag for P3P */ | |
1853 | int mn_present = 0; | |
1854 | uint32_t flagbit; | |
1855 | ||
1856 | ptab_desc = qla82xx_get_table_desc(unirom, | |
1857 | QLA82XX_URI_DIR_SECT_PRODUCT_TBL); | |
1858 | if (!ptab_desc) | |
1859 | return -1; | |
1860 | ||
1861 | entries = cpu_to_le32(ptab_desc->num_entries); | |
1862 | ||
1863 | for (i = 0; i < entries; i++) { | |
1864 | offset = cpu_to_le32(ptab_desc->findex) + | |
1865 | (i * cpu_to_le32(ptab_desc->entry_size)); | |
1866 | flags = cpu_to_le32(*((int *)&unirom[offset] + | |
1867 | QLA82XX_URI_FLAGS_OFF)); | |
1868 | file_chiprev = cpu_to_le32(*((int *)&unirom[offset] + | |
1869 | QLA82XX_URI_CHIP_REV_OFF)); | |
1870 | ||
1871 | flagbit = mn_present ? 1 : 2; | |
1872 | ||
1873 | if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) { | |
1874 | ha->file_prd_off = offset; | |
1875 | return 0; | |
1876 | } | |
1877 | } | |
1878 | return -1; | |
1879 | } | |
1880 | ||
1881 | int | |
1882 | qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type) | |
1883 | { | |
1884 | __le32 val; | |
1885 | uint32_t min_size; | |
1886 | struct qla_hw_data *ha = vha->hw; | |
1887 | const struct firmware *fw = ha->hablob->fw; | |
1888 | ||
1889 | ha->fw_type = fw_type; | |
1890 | ||
1891 | if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) { | |
1892 | if (qla82xx_set_product_offset(ha)) | |
1893 | return -EINVAL; | |
1894 | ||
1895 | min_size = QLA82XX_URI_FW_MIN_SIZE; | |
1896 | } else { | |
1897 | val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]); | |
1898 | if ((__force u32)val != QLA82XX_BDINFO_MAGIC) | |
1899 | return -EINVAL; | |
1900 | ||
1901 | min_size = QLA82XX_FW_MIN_SIZE; | |
1902 | } | |
1903 | ||
1904 | if (fw->size < min_size) | |
1905 | return -EINVAL; | |
a9083016 GM |
1906 | return 0; |
1907 | } | |
1908 | ||
77e334d2 GM |
1909 | static int |
1910 | qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) | |
a9083016 GM |
1911 | { |
1912 | u32 val = 0; | |
1913 | int retries = 60; | |
7c3df132 | 1914 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
1915 | |
1916 | do { | |
1917 | read_lock(&ha->hw_lock); | |
1918 | val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); | |
1919 | read_unlock(&ha->hw_lock); | |
1920 | ||
1921 | switch (val) { | |
1922 | case PHAN_INITIALIZE_COMPLETE: | |
1923 | case PHAN_INITIALIZE_ACK: | |
1924 | return QLA_SUCCESS; | |
1925 | case PHAN_INITIALIZE_FAILED: | |
1926 | break; | |
1927 | default: | |
1928 | break; | |
1929 | } | |
7c3df132 SK |
1930 | ql_log(ql_log_info, vha, 0x00a8, |
1931 | "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", | |
1932 | val, retries); | |
a9083016 GM |
1933 | |
1934 | msleep(500); | |
1935 | ||
1936 | } while (--retries); | |
1937 | ||
7c3df132 | 1938 | ql_log(ql_log_fatal, vha, 0x00a9, |
a9083016 GM |
1939 | "Cmd Peg initialization failed: 0x%x.\n", val); |
1940 | ||
a9083016 GM |
1941 | val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); |
1942 | read_lock(&ha->hw_lock); | |
1943 | qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); | |
1944 | read_unlock(&ha->hw_lock); | |
1945 | return QLA_FUNCTION_FAILED; | |
1946 | } | |
1947 | ||
77e334d2 GM |
1948 | static int |
1949 | qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) | |
a9083016 GM |
1950 | { |
1951 | u32 val = 0; | |
1952 | int retries = 60; | |
7c3df132 | 1953 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
1954 | |
1955 | do { | |
1956 | read_lock(&ha->hw_lock); | |
1957 | val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); | |
1958 | read_unlock(&ha->hw_lock); | |
1959 | ||
1960 | switch (val) { | |
1961 | case PHAN_INITIALIZE_COMPLETE: | |
1962 | case PHAN_INITIALIZE_ACK: | |
1963 | return QLA_SUCCESS; | |
1964 | case PHAN_INITIALIZE_FAILED: | |
1965 | break; | |
1966 | default: | |
1967 | break; | |
1968 | } | |
7c3df132 SK |
1969 | ql_log(ql_log_info, vha, 0x00ab, |
1970 | "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", | |
1971 | val, retries); | |
a9083016 GM |
1972 | |
1973 | msleep(500); | |
1974 | ||
1975 | } while (--retries); | |
1976 | ||
7c3df132 SK |
1977 | ql_log(ql_log_fatal, vha, 0x00ac, |
1978 | "Rcv Peg initializatin failed: 0x%x.\n", val); | |
a9083016 GM |
1979 | read_lock(&ha->hw_lock); |
1980 | qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); | |
1981 | read_unlock(&ha->hw_lock); | |
1982 | return QLA_FUNCTION_FAILED; | |
1983 | } | |
1984 | ||
1985 | /* ISR related functions */ | |
1986 | uint32_t qla82xx_isr_int_target_mask_enable[8] = { | |
1987 | ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1, | |
1988 | ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3, | |
1989 | ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5, | |
1990 | ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7 | |
1991 | }; | |
1992 | ||
1993 | uint32_t qla82xx_isr_int_target_status[8] = { | |
1994 | ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1, | |
1995 | ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3, | |
1996 | ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5, | |
1997 | ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7 | |
1998 | }; | |
1999 | ||
2000 | static struct qla82xx_legacy_intr_set legacy_intr[] = \ | |
2001 | QLA82XX_LEGACY_INTR_CONFIG; | |
2002 | ||
2003 | /* | |
2004 | * qla82xx_mbx_completion() - Process mailbox command completions. | |
2005 | * @ha: SCSI driver HA context | |
2006 | * @mb0: Mailbox0 register | |
2007 | */ | |
77e334d2 | 2008 | static void |
a9083016 GM |
2009 | qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) |
2010 | { | |
2011 | uint16_t cnt; | |
2012 | uint16_t __iomem *wptr; | |
2013 | struct qla_hw_data *ha = vha->hw; | |
2014 | struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; | |
2015 | wptr = (uint16_t __iomem *)®->mailbox_out[1]; | |
2016 | ||
2017 | /* Load return mailbox registers. */ | |
2018 | ha->flags.mbox_int = 1; | |
2019 | ha->mailbox_out[0] = mb0; | |
2020 | ||
2021 | for (cnt = 1; cnt < ha->mbx_count; cnt++) { | |
2022 | ha->mailbox_out[cnt] = RD_REG_WORD(wptr); | |
2023 | wptr++; | |
2024 | } | |
2025 | ||
2026 | if (ha->mcp) { | |
7c3df132 SK |
2027 | ql_dbg(ql_dbg_async, vha, 0x5052, |
2028 | "Got mailbox completion. cmd=%x.\n", ha->mcp->mb[0]); | |
a9083016 | 2029 | } else { |
7c3df132 SK |
2030 | ql_dbg(ql_dbg_async, vha, 0x5053, |
2031 | "MBX pointer ERROR.\n"); | |
a9083016 GM |
2032 | } |
2033 | } | |
2034 | ||
2035 | /* | |
2036 | * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. | |
2037 | * @irq: | |
2038 | * @dev_id: SCSI driver HA context | |
2039 | * @regs: | |
2040 | * | |
2041 | * Called by system whenever the host adapter generates an interrupt. | |
2042 | * | |
2043 | * Returns handled flag. | |
2044 | */ | |
2045 | irqreturn_t | |
2046 | qla82xx_intr_handler(int irq, void *dev_id) | |
2047 | { | |
2048 | scsi_qla_host_t *vha; | |
2049 | struct qla_hw_data *ha; | |
2050 | struct rsp_que *rsp; | |
2051 | struct device_reg_82xx __iomem *reg; | |
2052 | int status = 0, status1 = 0; | |
2053 | unsigned long flags; | |
2054 | unsigned long iter; | |
7c3df132 | 2055 | uint32_t stat = 0; |
a9083016 GM |
2056 | uint16_t mb[4]; |
2057 | ||
2058 | rsp = (struct rsp_que *) dev_id; | |
2059 | if (!rsp) { | |
2060 | printk(KERN_INFO | |
7c3df132 | 2061 | "%s(): NULL response queue pointer.\n", __func__); |
a9083016 GM |
2062 | return IRQ_NONE; |
2063 | } | |
2064 | ha = rsp->hw; | |
2065 | ||
2066 | if (!ha->flags.msi_enabled) { | |
2067 | status = qla82xx_rd_32(ha, ISR_INT_VECTOR); | |
2068 | if (!(status & ha->nx_legacy_intr.int_vec_bit)) | |
2069 | return IRQ_NONE; | |
2070 | ||
2071 | status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); | |
2072 | if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) | |
2073 | return IRQ_NONE; | |
2074 | } | |
2075 | ||
2076 | /* clear the interrupt */ | |
2077 | qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); | |
2078 | ||
2079 | /* read twice to ensure write is flushed */ | |
2080 | qla82xx_rd_32(ha, ISR_INT_VECTOR); | |
2081 | qla82xx_rd_32(ha, ISR_INT_VECTOR); | |
2082 | ||
2083 | reg = &ha->iobase->isp82; | |
2084 | ||
2085 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
2086 | vha = pci_get_drvdata(ha->pdev); | |
2087 | for (iter = 1; iter--; ) { | |
2088 | ||
2089 | if (RD_REG_DWORD(®->host_int)) { | |
2090 | stat = RD_REG_DWORD(®->host_status); | |
a9083016 GM |
2091 | |
2092 | switch (stat & 0xff) { | |
2093 | case 0x1: | |
2094 | case 0x2: | |
2095 | case 0x10: | |
2096 | case 0x11: | |
2097 | qla82xx_mbx_completion(vha, MSW(stat)); | |
2098 | status |= MBX_INTERRUPT; | |
2099 | break; | |
2100 | case 0x12: | |
2101 | mb[0] = MSW(stat); | |
2102 | mb[1] = RD_REG_WORD(®->mailbox_out[1]); | |
2103 | mb[2] = RD_REG_WORD(®->mailbox_out[2]); | |
2104 | mb[3] = RD_REG_WORD(®->mailbox_out[3]); | |
2105 | qla2x00_async_event(vha, rsp, mb); | |
2106 | break; | |
2107 | case 0x13: | |
2108 | qla24xx_process_response_queue(vha, rsp); | |
2109 | break; | |
2110 | default: | |
7c3df132 SK |
2111 | ql_dbg(ql_dbg_async, vha, 0x5054, |
2112 | "Unrecognized interrupt type (%d).\n", | |
2113 | stat & 0xff); | |
a9083016 GM |
2114 | break; |
2115 | } | |
2116 | } | |
2117 | WRT_REG_DWORD(®->host_int, 0); | |
2118 | } | |
2119 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
2120 | if (!ha->flags.msi_enabled) | |
2121 | qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); | |
2122 | ||
2123 | #ifdef QL_DEBUG_LEVEL_17 | |
2124 | if (!irq && ha->flags.eeh_busy) | |
7c3df132 SK |
2125 | ql_log(ql_log_warn, vha, 0x503d, |
2126 | "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", | |
a9083016 GM |
2127 | status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); |
2128 | #endif | |
2129 | ||
2130 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && | |
2131 | (status & MBX_INTERRUPT) && ha->flags.mbox_int) { | |
2132 | set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
2133 | complete(&ha->mbx_intr_comp); | |
2134 | } | |
2135 | return IRQ_HANDLED; | |
2136 | } | |
2137 | ||
2138 | irqreturn_t | |
2139 | qla82xx_msix_default(int irq, void *dev_id) | |
2140 | { | |
2141 | scsi_qla_host_t *vha; | |
2142 | struct qla_hw_data *ha; | |
2143 | struct rsp_que *rsp; | |
2144 | struct device_reg_82xx __iomem *reg; | |
2145 | int status = 0; | |
2146 | unsigned long flags; | |
7c3df132 | 2147 | uint32_t stat = 0; |
a9083016 GM |
2148 | uint16_t mb[4]; |
2149 | ||
2150 | rsp = (struct rsp_que *) dev_id; | |
2151 | if (!rsp) { | |
2152 | printk(KERN_INFO | |
7c3df132 | 2153 | "%s(): NULL response queue pointer.\n", __func__); |
a9083016 GM |
2154 | return IRQ_NONE; |
2155 | } | |
2156 | ha = rsp->hw; | |
2157 | ||
2158 | reg = &ha->iobase->isp82; | |
2159 | ||
2160 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
2161 | vha = pci_get_drvdata(ha->pdev); | |
2162 | do { | |
2163 | if (RD_REG_DWORD(®->host_int)) { | |
2164 | stat = RD_REG_DWORD(®->host_status); | |
a9083016 GM |
2165 | |
2166 | switch (stat & 0xff) { | |
2167 | case 0x1: | |
2168 | case 0x2: | |
2169 | case 0x10: | |
2170 | case 0x11: | |
2171 | qla82xx_mbx_completion(vha, MSW(stat)); | |
2172 | status |= MBX_INTERRUPT; | |
2173 | break; | |
2174 | case 0x12: | |
2175 | mb[0] = MSW(stat); | |
2176 | mb[1] = RD_REG_WORD(®->mailbox_out[1]); | |
2177 | mb[2] = RD_REG_WORD(®->mailbox_out[2]); | |
2178 | mb[3] = RD_REG_WORD(®->mailbox_out[3]); | |
2179 | qla2x00_async_event(vha, rsp, mb); | |
2180 | break; | |
2181 | case 0x13: | |
2182 | qla24xx_process_response_queue(vha, rsp); | |
2183 | break; | |
2184 | default: | |
7c3df132 SK |
2185 | ql_dbg(ql_dbg_async, vha, 0x5041, |
2186 | "Unrecognized interrupt type (%d).\n", | |
2187 | stat & 0xff); | |
a9083016 GM |
2188 | break; |
2189 | } | |
2190 | } | |
2191 | WRT_REG_DWORD(®->host_int, 0); | |
2192 | } while (0); | |
2193 | ||
2194 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
2195 | ||
2196 | #ifdef QL_DEBUG_LEVEL_17 | |
2197 | if (!irq && ha->flags.eeh_busy) | |
7c3df132 SK |
2198 | ql_log(ql_log_warn, vha, 0x5044, |
2199 | "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n", | |
2200 | status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); | |
a9083016 GM |
2201 | #endif |
2202 | ||
2203 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && | |
2204 | (status & MBX_INTERRUPT) && ha->flags.mbox_int) { | |
2205 | set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
2206 | complete(&ha->mbx_intr_comp); | |
2207 | } | |
2208 | return IRQ_HANDLED; | |
2209 | } | |
2210 | ||
2211 | irqreturn_t | |
2212 | qla82xx_msix_rsp_q(int irq, void *dev_id) | |
2213 | { | |
2214 | scsi_qla_host_t *vha; | |
2215 | struct qla_hw_data *ha; | |
2216 | struct rsp_que *rsp; | |
2217 | struct device_reg_82xx __iomem *reg; | |
3553d343 | 2218 | unsigned long flags; |
a9083016 GM |
2219 | |
2220 | rsp = (struct rsp_que *) dev_id; | |
2221 | if (!rsp) { | |
2222 | printk(KERN_INFO | |
7c3df132 | 2223 | "%s(): NULL response queue pointer.\n", __func__); |
a9083016 GM |
2224 | return IRQ_NONE; |
2225 | } | |
2226 | ||
2227 | ha = rsp->hw; | |
2228 | reg = &ha->iobase->isp82; | |
3553d343 | 2229 | spin_lock_irqsave(&ha->hardware_lock, flags); |
a9083016 GM |
2230 | vha = pci_get_drvdata(ha->pdev); |
2231 | qla24xx_process_response_queue(vha, rsp); | |
2232 | WRT_REG_DWORD(®->host_int, 0); | |
3553d343 | 2233 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
a9083016 GM |
2234 | return IRQ_HANDLED; |
2235 | } | |
2236 | ||
2237 | void | |
2238 | qla82xx_poll(int irq, void *dev_id) | |
2239 | { | |
2240 | scsi_qla_host_t *vha; | |
2241 | struct qla_hw_data *ha; | |
2242 | struct rsp_que *rsp; | |
2243 | struct device_reg_82xx __iomem *reg; | |
2244 | int status = 0; | |
2245 | uint32_t stat; | |
2246 | uint16_t mb[4]; | |
2247 | unsigned long flags; | |
2248 | ||
2249 | rsp = (struct rsp_que *) dev_id; | |
2250 | if (!rsp) { | |
2251 | printk(KERN_INFO | |
7c3df132 | 2252 | "%s(): NULL response queue pointer.\n", __func__); |
a9083016 GM |
2253 | return; |
2254 | } | |
2255 | ha = rsp->hw; | |
2256 | ||
2257 | reg = &ha->iobase->isp82; | |
2258 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
2259 | vha = pci_get_drvdata(ha->pdev); | |
2260 | ||
2261 | if (RD_REG_DWORD(®->host_int)) { | |
2262 | stat = RD_REG_DWORD(®->host_status); | |
2263 | switch (stat & 0xff) { | |
2264 | case 0x1: | |
2265 | case 0x2: | |
2266 | case 0x10: | |
2267 | case 0x11: | |
2268 | qla82xx_mbx_completion(vha, MSW(stat)); | |
2269 | status |= MBX_INTERRUPT; | |
2270 | break; | |
2271 | case 0x12: | |
2272 | mb[0] = MSW(stat); | |
2273 | mb[1] = RD_REG_WORD(®->mailbox_out[1]); | |
2274 | mb[2] = RD_REG_WORD(®->mailbox_out[2]); | |
2275 | mb[3] = RD_REG_WORD(®->mailbox_out[3]); | |
2276 | qla2x00_async_event(vha, rsp, mb); | |
2277 | break; | |
2278 | case 0x13: | |
2279 | qla24xx_process_response_queue(vha, rsp); | |
2280 | break; | |
2281 | default: | |
7c3df132 SK |
2282 | ql_dbg(ql_dbg_p3p, vha, 0xb013, |
2283 | "Unrecognized interrupt type (%d).\n", | |
2284 | stat * 0xff); | |
a9083016 GM |
2285 | break; |
2286 | } | |
2287 | } | |
2288 | WRT_REG_DWORD(®->host_int, 0); | |
2289 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
2290 | } | |
2291 | ||
2292 | void | |
2293 | qla82xx_enable_intrs(struct qla_hw_data *ha) | |
2294 | { | |
2295 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); | |
2296 | qla82xx_mbx_intr_enable(vha); | |
2297 | spin_lock_irq(&ha->hardware_lock); | |
2298 | qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); | |
2299 | spin_unlock_irq(&ha->hardware_lock); | |
2300 | ha->interrupts_on = 1; | |
2301 | } | |
2302 | ||
2303 | void | |
2304 | qla82xx_disable_intrs(struct qla_hw_data *ha) | |
2305 | { | |
2306 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); | |
2307 | qla82xx_mbx_intr_disable(vha); | |
2308 | spin_lock_irq(&ha->hardware_lock); | |
2309 | qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); | |
2310 | spin_unlock_irq(&ha->hardware_lock); | |
2311 | ha->interrupts_on = 0; | |
2312 | } | |
2313 | ||
2314 | void qla82xx_init_flags(struct qla_hw_data *ha) | |
2315 | { | |
2316 | struct qla82xx_legacy_intr_set *nx_legacy_intr; | |
2317 | ||
2318 | /* ISP 8021 initializations */ | |
2319 | rwlock_init(&ha->hw_lock); | |
2320 | ha->qdr_sn_window = -1; | |
2321 | ha->ddr_mn_window = -1; | |
2322 | ha->curr_window = 255; | |
2323 | ha->portnum = PCI_FUNC(ha->pdev->devfn); | |
2324 | nx_legacy_intr = &legacy_intr[ha->portnum]; | |
2325 | ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; | |
2326 | ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; | |
2327 | ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; | |
2328 | ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; | |
2329 | } | |
2330 | ||
a5b36321 | 2331 | inline void |
a9083016 GM |
2332 | qla82xx_set_drv_active(scsi_qla_host_t *vha) |
2333 | { | |
2334 | uint32_t drv_active; | |
2335 | struct qla_hw_data *ha = vha->hw; | |
2336 | ||
2337 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
2338 | ||
2339 | /* If reset value is all FF's, initialize DRV_ACTIVE */ | |
2340 | if (drv_active == 0xffffffff) { | |
77e334d2 GM |
2341 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, |
2342 | QLA82XX_DRV_NOT_ACTIVE); | |
a9083016 GM |
2343 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); |
2344 | } | |
77e334d2 | 2345 | drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); |
a9083016 GM |
2346 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); |
2347 | } | |
2348 | ||
2349 | inline void | |
2350 | qla82xx_clear_drv_active(struct qla_hw_data *ha) | |
2351 | { | |
2352 | uint32_t drv_active; | |
2353 | ||
2354 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
77e334d2 | 2355 | drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); |
a9083016 GM |
2356 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); |
2357 | } | |
2358 | ||
2359 | static inline int | |
2360 | qla82xx_need_reset(struct qla_hw_data *ha) | |
2361 | { | |
2362 | uint32_t drv_state; | |
2363 | int rval; | |
2364 | ||
08de2844 GM |
2365 | if (ha->flags.isp82xx_reset_owner) |
2366 | return 1; | |
2367 | else { | |
2368 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | |
2369 | rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); | |
2370 | return rval; | |
2371 | } | |
a9083016 GM |
2372 | } |
2373 | ||
2374 | static inline void | |
2375 | qla82xx_set_rst_ready(struct qla_hw_data *ha) | |
2376 | { | |
2377 | uint32_t drv_state; | |
2378 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); | |
2379 | ||
2380 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | |
2381 | ||
2382 | /* If reset value is all FF's, initialize DRV_STATE */ | |
2383 | if (drv_state == 0xffffffff) { | |
77e334d2 | 2384 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY); |
a9083016 GM |
2385 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); |
2386 | } | |
2387 | drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); | |
08de2844 GM |
2388 | ql_dbg(ql_dbg_init, vha, 0x00bb, |
2389 | "drv_state = 0x%08x.\n", drv_state); | |
a9083016 GM |
2390 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); |
2391 | } | |
2392 | ||
2393 | static inline void | |
2394 | qla82xx_clear_rst_ready(struct qla_hw_data *ha) | |
2395 | { | |
2396 | uint32_t drv_state; | |
2397 | ||
2398 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | |
2399 | drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); | |
2400 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); | |
2401 | } | |
2402 | ||
2403 | static inline void | |
2404 | qla82xx_set_qsnt_ready(struct qla_hw_data *ha) | |
2405 | { | |
2406 | uint32_t qsnt_state; | |
2407 | ||
2408 | qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | |
2409 | qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); | |
2410 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); | |
2411 | } | |
2412 | ||
579d12b5 SK |
2413 | void |
2414 | qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha) | |
2415 | { | |
2416 | struct qla_hw_data *ha = vha->hw; | |
2417 | uint32_t qsnt_state; | |
2418 | ||
2419 | qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | |
2420 | qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); | |
2421 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); | |
2422 | } | |
2423 | ||
77e334d2 GM |
2424 | static int |
2425 | qla82xx_load_fw(scsi_qla_host_t *vha) | |
a9083016 GM |
2426 | { |
2427 | int rst; | |
2428 | struct fw_blob *blob; | |
2429 | struct qla_hw_data *ha = vha->hw; | |
2430 | ||
a9083016 | 2431 | if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { |
7c3df132 SK |
2432 | ql_log(ql_log_fatal, vha, 0x009f, |
2433 | "Error during CRB initialization.\n"); | |
a9083016 GM |
2434 | return QLA_FUNCTION_FAILED; |
2435 | } | |
2436 | udelay(500); | |
2437 | ||
2438 | /* Bring QM and CAMRAM out of reset */ | |
2439 | rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); | |
2440 | rst &= ~((1 << 28) | (1 << 24)); | |
2441 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); | |
2442 | ||
2443 | /* | |
2444 | * FW Load priority: | |
2445 | * 1) Operational firmware residing in flash. | |
2446 | * 2) Firmware via request-firmware interface (.bin file). | |
2447 | */ | |
2448 | if (ql2xfwloadbin == 2) | |
2449 | goto try_blob_fw; | |
2450 | ||
7c3df132 SK |
2451 | ql_log(ql_log_info, vha, 0x00a0, |
2452 | "Attempting to load firmware from flash.\n"); | |
a9083016 GM |
2453 | |
2454 | if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { | |
7c3df132 SK |
2455 | ql_log(ql_log_info, vha, 0x00a1, |
2456 | "Firmware loaded successully from flash.\n"); | |
a9083016 | 2457 | return QLA_SUCCESS; |
875efad7 | 2458 | } else { |
7c3df132 SK |
2459 | ql_log(ql_log_warn, vha, 0x0108, |
2460 | "Firmware load from flash failed.\n"); | |
a9083016 | 2461 | } |
875efad7 | 2462 | |
a9083016 | 2463 | try_blob_fw: |
7c3df132 SK |
2464 | ql_log(ql_log_info, vha, 0x00a2, |
2465 | "Attempting to load firmware from blob.\n"); | |
a9083016 GM |
2466 | |
2467 | /* Load firmware blob. */ | |
2468 | blob = ha->hablob = qla2x00_request_firmware(vha); | |
2469 | if (!blob) { | |
7c3df132 SK |
2470 | ql_log(ql_log_fatal, vha, 0x00a3, |
2471 | "Firmware image not preset.\n"); | |
a9083016 GM |
2472 | goto fw_load_failed; |
2473 | } | |
2474 | ||
9c2b2975 HZ |
2475 | /* Validating firmware blob */ |
2476 | if (qla82xx_validate_firmware_blob(vha, | |
2477 | QLA82XX_FLASH_ROMIMAGE)) { | |
2478 | /* Fallback to URI format */ | |
2479 | if (qla82xx_validate_firmware_blob(vha, | |
2480 | QLA82XX_UNIFIED_ROMIMAGE)) { | |
7c3df132 SK |
2481 | ql_log(ql_log_fatal, vha, 0x00a4, |
2482 | "No valid firmware image found.\n"); | |
9c2b2975 HZ |
2483 | return QLA_FUNCTION_FAILED; |
2484 | } | |
2485 | } | |
2486 | ||
a9083016 | 2487 | if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { |
7c3df132 SK |
2488 | ql_log(ql_log_info, vha, 0x00a5, |
2489 | "Firmware loaded successfully from binary blob.\n"); | |
a9083016 GM |
2490 | return QLA_SUCCESS; |
2491 | } else { | |
7c3df132 SK |
2492 | ql_log(ql_log_fatal, vha, 0x00a6, |
2493 | "Firmware load failed for binary blob.\n"); | |
a9083016 GM |
2494 | blob->fw = NULL; |
2495 | blob = NULL; | |
2496 | goto fw_load_failed; | |
2497 | } | |
2498 | return QLA_SUCCESS; | |
2499 | ||
2500 | fw_load_failed: | |
2501 | return QLA_FUNCTION_FAILED; | |
2502 | } | |
2503 | ||
a5b36321 | 2504 | int |
a9083016 GM |
2505 | qla82xx_start_firmware(scsi_qla_host_t *vha) |
2506 | { | |
2507 | int pcie_cap; | |
2508 | uint16_t lnk; | |
2509 | struct qla_hw_data *ha = vha->hw; | |
2510 | ||
2511 | /* scrub dma mask expansion register */ | |
77e334d2 | 2512 | qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE); |
a9083016 | 2513 | |
3711333d GM |
2514 | /* Put both the PEG CMD and RCV PEG to default state |
2515 | * of 0 before resetting the hardware | |
2516 | */ | |
2517 | qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); | |
2518 | qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); | |
2519 | ||
a9083016 GM |
2520 | /* Overwrite stale initialization register values */ |
2521 | qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); | |
2522 | qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); | |
2523 | ||
2524 | if (qla82xx_load_fw(vha) != QLA_SUCCESS) { | |
7c3df132 SK |
2525 | ql_log(ql_log_fatal, vha, 0x00a7, |
2526 | "Error trying to start fw.\n"); | |
a9083016 GM |
2527 | return QLA_FUNCTION_FAILED; |
2528 | } | |
2529 | ||
2530 | /* Handshake with the card before we register the devices. */ | |
2531 | if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { | |
7c3df132 SK |
2532 | ql_log(ql_log_fatal, vha, 0x00aa, |
2533 | "Error during card handshake.\n"); | |
a9083016 GM |
2534 | return QLA_FUNCTION_FAILED; |
2535 | } | |
2536 | ||
2537 | /* Negotiated Link width */ | |
2538 | pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); | |
2539 | pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); | |
2540 | ha->link_width = (lnk >> 4) & 0x3f; | |
2541 | ||
2542 | /* Synchronize with Receive peg */ | |
2543 | return qla82xx_check_rcvpeg_state(ha); | |
2544 | } | |
2545 | ||
2546 | static inline int | |
2547 | qla2xx_build_scsi_type_6_iocbs(srb_t *sp, struct cmd_type_6 *cmd_pkt, | |
2548 | uint16_t tot_dsds) | |
2549 | { | |
2550 | uint32_t *cur_dsd = NULL; | |
2551 | scsi_qla_host_t *vha; | |
2552 | struct qla_hw_data *ha; | |
2553 | struct scsi_cmnd *cmd; | |
2554 | struct scatterlist *cur_seg; | |
2555 | uint32_t *dsd_seg; | |
2556 | void *next_dsd; | |
2557 | uint8_t avail_dsds; | |
2558 | uint8_t first_iocb = 1; | |
2559 | uint32_t dsd_list_len; | |
2560 | struct dsd_dma *dsd_ptr; | |
2561 | struct ct6_dsd *ctx; | |
2562 | ||
2563 | cmd = sp->cmd; | |
2564 | ||
2565 | /* Update entry type to indicate Command Type 3 IOCB */ | |
2566 | *((uint32_t *)(&cmd_pkt->entry_type)) = | |
2567 | __constant_cpu_to_le32(COMMAND_TYPE_6); | |
2568 | ||
2569 | /* No data transfer */ | |
2570 | if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) { | |
2571 | cmd_pkt->byte_count = __constant_cpu_to_le32(0); | |
2572 | return 0; | |
2573 | } | |
2574 | ||
2575 | vha = sp->fcport->vha; | |
2576 | ha = vha->hw; | |
2577 | ||
2578 | /* Set transfer direction */ | |
2579 | if (cmd->sc_data_direction == DMA_TO_DEVICE) { | |
2580 | cmd_pkt->control_flags = | |
2581 | __constant_cpu_to_le16(CF_WRITE_DATA); | |
2582 | ha->qla_stats.output_bytes += scsi_bufflen(cmd); | |
2583 | } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) { | |
2584 | cmd_pkt->control_flags = | |
2585 | __constant_cpu_to_le16(CF_READ_DATA); | |
2586 | ha->qla_stats.input_bytes += scsi_bufflen(cmd); | |
2587 | } | |
2588 | ||
2589 | cur_seg = scsi_sglist(cmd); | |
2590 | ctx = sp->ctx; | |
2591 | ||
2592 | while (tot_dsds) { | |
2593 | avail_dsds = (tot_dsds > QLA_DSDS_PER_IOCB) ? | |
2594 | QLA_DSDS_PER_IOCB : tot_dsds; | |
2595 | tot_dsds -= avail_dsds; | |
2596 | dsd_list_len = (avail_dsds + 1) * QLA_DSD_SIZE; | |
2597 | ||
2598 | dsd_ptr = list_first_entry(&ha->gbl_dsd_list, | |
2599 | struct dsd_dma, list); | |
2600 | next_dsd = dsd_ptr->dsd_addr; | |
2601 | list_del(&dsd_ptr->list); | |
2602 | ha->gbl_dsd_avail--; | |
2603 | list_add_tail(&dsd_ptr->list, &ctx->dsd_list); | |
2604 | ctx->dsd_use_cnt++; | |
2605 | ha->gbl_dsd_inuse++; | |
2606 | ||
2607 | if (first_iocb) { | |
2608 | first_iocb = 0; | |
2609 | dsd_seg = (uint32_t *)&cmd_pkt->fcp_data_dseg_address; | |
2610 | *dsd_seg++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); | |
2611 | *dsd_seg++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); | |
63d92d3e | 2612 | cmd_pkt->fcp_data_dseg_len = cpu_to_le32(dsd_list_len); |
a9083016 GM |
2613 | } else { |
2614 | *cur_dsd++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); | |
2615 | *cur_dsd++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); | |
fa96d927 | 2616 | *cur_dsd++ = cpu_to_le32(dsd_list_len); |
a9083016 GM |
2617 | } |
2618 | cur_dsd = (uint32_t *)next_dsd; | |
2619 | while (avail_dsds) { | |
2620 | dma_addr_t sle_dma; | |
2621 | ||
2622 | sle_dma = sg_dma_address(cur_seg); | |
2623 | *cur_dsd++ = cpu_to_le32(LSD(sle_dma)); | |
2624 | *cur_dsd++ = cpu_to_le32(MSD(sle_dma)); | |
2625 | *cur_dsd++ = cpu_to_le32(sg_dma_len(cur_seg)); | |
aa5cbf8a | 2626 | cur_seg = sg_next(cur_seg); |
a9083016 GM |
2627 | avail_dsds--; |
2628 | } | |
2629 | } | |
2630 | ||
2631 | /* Null termination */ | |
2632 | *cur_dsd++ = 0; | |
2633 | *cur_dsd++ = 0; | |
2634 | *cur_dsd++ = 0; | |
2635 | cmd_pkt->control_flags |= CF_DATA_SEG_DESCR_ENABLE; | |
2636 | return 0; | |
2637 | } | |
2638 | ||
2639 | /* | |
2640 | * qla82xx_calc_dsd_lists() - Determine number of DSD list required | |
2641 | * for Command Type 6. | |
2642 | * | |
2643 | * @dsds: number of data segment decriptors needed | |
2644 | * | |
2645 | * Returns the number of dsd list needed to store @dsds. | |
2646 | */ | |
2647 | inline uint16_t | |
2648 | qla82xx_calc_dsd_lists(uint16_t dsds) | |
2649 | { | |
2650 | uint16_t dsd_lists = 0; | |
2651 | ||
2652 | dsd_lists = (dsds/QLA_DSDS_PER_IOCB); | |
2653 | if (dsds % QLA_DSDS_PER_IOCB) | |
2654 | dsd_lists++; | |
2655 | return dsd_lists; | |
2656 | } | |
2657 | ||
2658 | /* | |
2659 | * qla82xx_start_scsi() - Send a SCSI command to the ISP | |
2660 | * @sp: command to send to the ISP | |
2661 | * | |
25985edc | 2662 | * Returns non-zero if a failure occurred, else zero. |
a9083016 GM |
2663 | */ |
2664 | int | |
2665 | qla82xx_start_scsi(srb_t *sp) | |
2666 | { | |
2667 | int ret, nseg; | |
2668 | unsigned long flags; | |
2669 | struct scsi_cmnd *cmd; | |
2670 | uint32_t *clr_ptr; | |
2671 | uint32_t index; | |
2672 | uint32_t handle; | |
2673 | uint16_t cnt; | |
2674 | uint16_t req_cnt; | |
2675 | uint16_t tot_dsds; | |
2676 | struct device_reg_82xx __iomem *reg; | |
2677 | uint32_t dbval; | |
2678 | uint32_t *fcp_dl; | |
2679 | uint8_t additional_cdb_len; | |
2680 | struct ct6_dsd *ctx; | |
2681 | struct scsi_qla_host *vha = sp->fcport->vha; | |
2682 | struct qla_hw_data *ha = vha->hw; | |
2683 | struct req_que *req = NULL; | |
2684 | struct rsp_que *rsp = NULL; | |
ff2fc42e | 2685 | char tag[2]; |
a9083016 GM |
2686 | |
2687 | /* Setup device pointers. */ | |
2688 | ret = 0; | |
2689 | reg = &ha->iobase->isp82; | |
2690 | cmd = sp->cmd; | |
2691 | req = vha->req; | |
2692 | rsp = ha->rsp_q_map[0]; | |
2693 | ||
2694 | /* So we know we haven't pci_map'ed anything yet */ | |
2695 | tot_dsds = 0; | |
2696 | ||
2697 | dbval = 0x04 | (ha->portnum << 5); | |
2698 | ||
2699 | /* Send marker if required */ | |
2700 | if (vha->marker_needed != 0) { | |
2701 | if (qla2x00_marker(vha, req, | |
7c3df132 SK |
2702 | rsp, 0, 0, MK_SYNC_ALL) != QLA_SUCCESS) { |
2703 | ql_log(ql_log_warn, vha, 0x300c, | |
2704 | "qla2x00_marker failed for cmd=%p.\n", cmd); | |
a9083016 | 2705 | return QLA_FUNCTION_FAILED; |
7c3df132 | 2706 | } |
a9083016 GM |
2707 | vha->marker_needed = 0; |
2708 | } | |
2709 | ||
2710 | /* Acquire ring specific lock */ | |
2711 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
2712 | ||
2713 | /* Check for room in outstanding command list. */ | |
2714 | handle = req->current_outstanding_cmd; | |
2715 | for (index = 1; index < MAX_OUTSTANDING_COMMANDS; index++) { | |
2716 | handle++; | |
2717 | if (handle == MAX_OUTSTANDING_COMMANDS) | |
2718 | handle = 1; | |
2719 | if (!req->outstanding_cmds[handle]) | |
2720 | break; | |
2721 | } | |
2722 | if (index == MAX_OUTSTANDING_COMMANDS) | |
2723 | goto queuing_error; | |
2724 | ||
2725 | /* Map the sg table so we have an accurate count of sg entries needed */ | |
2726 | if (scsi_sg_count(cmd)) { | |
2727 | nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd), | |
2728 | scsi_sg_count(cmd), cmd->sc_data_direction); | |
2729 | if (unlikely(!nseg)) | |
2730 | goto queuing_error; | |
2731 | } else | |
2732 | nseg = 0; | |
2733 | ||
2734 | tot_dsds = nseg; | |
2735 | ||
2736 | if (tot_dsds > ql2xshiftctondsd) { | |
2737 | struct cmd_type_6 *cmd_pkt; | |
2738 | uint16_t more_dsd_lists = 0; | |
2739 | struct dsd_dma *dsd_ptr; | |
2740 | uint16_t i; | |
2741 | ||
2742 | more_dsd_lists = qla82xx_calc_dsd_lists(tot_dsds); | |
7c3df132 SK |
2743 | if ((more_dsd_lists + ha->gbl_dsd_inuse) >= NUM_DSD_CHAIN) { |
2744 | ql_dbg(ql_dbg_io, vha, 0x300d, | |
2745 | "Num of DSD list %d is than %d for cmd=%p.\n", | |
2746 | more_dsd_lists + ha->gbl_dsd_inuse, NUM_DSD_CHAIN, | |
2747 | cmd); | |
a9083016 | 2748 | goto queuing_error; |
7c3df132 | 2749 | } |
a9083016 GM |
2750 | |
2751 | if (more_dsd_lists <= ha->gbl_dsd_avail) | |
2752 | goto sufficient_dsds; | |
2753 | else | |
2754 | more_dsd_lists -= ha->gbl_dsd_avail; | |
2755 | ||
2756 | for (i = 0; i < more_dsd_lists; i++) { | |
2757 | dsd_ptr = kzalloc(sizeof(struct dsd_dma), GFP_ATOMIC); | |
7c3df132 SK |
2758 | if (!dsd_ptr) { |
2759 | ql_log(ql_log_fatal, vha, 0x300e, | |
2760 | "Failed to allocate memory for dsd_dma " | |
2761 | "for cmd=%p.\n", cmd); | |
a9083016 | 2762 | goto queuing_error; |
7c3df132 | 2763 | } |
a9083016 GM |
2764 | |
2765 | dsd_ptr->dsd_addr = dma_pool_alloc(ha->dl_dma_pool, | |
2766 | GFP_ATOMIC, &dsd_ptr->dsd_list_dma); | |
2767 | if (!dsd_ptr->dsd_addr) { | |
2768 | kfree(dsd_ptr); | |
7c3df132 SK |
2769 | ql_log(ql_log_fatal, vha, 0x300f, |
2770 | "Failed to allocate memory for dsd_addr " | |
2771 | "for cmd=%p.\n", cmd); | |
a9083016 GM |
2772 | goto queuing_error; |
2773 | } | |
2774 | list_add_tail(&dsd_ptr->list, &ha->gbl_dsd_list); | |
2775 | ha->gbl_dsd_avail++; | |
2776 | } | |
2777 | ||
2778 | sufficient_dsds: | |
2779 | req_cnt = 1; | |
2780 | ||
1bd58b89 GM |
2781 | if (req->cnt < (req_cnt + 2)) { |
2782 | cnt = (uint16_t)RD_REG_DWORD_RELAXED( | |
2783 | ®->req_q_out[0]); | |
2784 | if (req->ring_index < cnt) | |
2785 | req->cnt = cnt - req->ring_index; | |
2786 | else | |
2787 | req->cnt = req->length - | |
2788 | (req->ring_index - cnt); | |
2789 | } | |
2790 | ||
2791 | if (req->cnt < (req_cnt + 2)) | |
2792 | goto queuing_error; | |
2793 | ||
a9083016 GM |
2794 | ctx = sp->ctx = mempool_alloc(ha->ctx_mempool, GFP_ATOMIC); |
2795 | if (!sp->ctx) { | |
7c3df132 SK |
2796 | ql_log(ql_log_fatal, vha, 0x3010, |
2797 | "Failed to allocate ctx for cmd=%p.\n", cmd); | |
a9083016 GM |
2798 | goto queuing_error; |
2799 | } | |
2800 | memset(ctx, 0, sizeof(struct ct6_dsd)); | |
2801 | ctx->fcp_cmnd = dma_pool_alloc(ha->fcp_cmnd_dma_pool, | |
2802 | GFP_ATOMIC, &ctx->fcp_cmnd_dma); | |
2803 | if (!ctx->fcp_cmnd) { | |
7c3df132 SK |
2804 | ql_log(ql_log_fatal, vha, 0x3011, |
2805 | "Failed to allocate fcp_cmnd for cmd=%p.\n", cmd); | |
a9083016 GM |
2806 | goto queuing_error_fcp_cmnd; |
2807 | } | |
2808 | ||
2809 | /* Initialize the DSD list and dma handle */ | |
2810 | INIT_LIST_HEAD(&ctx->dsd_list); | |
2811 | ctx->dsd_use_cnt = 0; | |
2812 | ||
2813 | if (cmd->cmd_len > 16) { | |
2814 | additional_cdb_len = cmd->cmd_len - 16; | |
2815 | if ((cmd->cmd_len % 4) != 0) { | |
2816 | /* SCSI command bigger than 16 bytes must be | |
2817 | * multiple of 4 | |
2818 | */ | |
7c3df132 SK |
2819 | ql_log(ql_log_warn, vha, 0x3012, |
2820 | "scsi cmd len %d not multiple of 4 " | |
2821 | "for cmd=%p.\n", cmd->cmd_len, cmd); | |
a9083016 GM |
2822 | goto queuing_error_fcp_cmnd; |
2823 | } | |
2824 | ctx->fcp_cmnd_len = 12 + cmd->cmd_len + 4; | |
2825 | } else { | |
2826 | additional_cdb_len = 0; | |
2827 | ctx->fcp_cmnd_len = 12 + 16 + 4; | |
2828 | } | |
2829 | ||
2830 | cmd_pkt = (struct cmd_type_6 *)req->ring_ptr; | |
2831 | cmd_pkt->handle = MAKE_HANDLE(req->id, handle); | |
2832 | ||
2833 | /* Zero out remaining portion of packet. */ | |
2834 | /* tagged queuing modifier -- default is TSK_SIMPLE (0). */ | |
2835 | clr_ptr = (uint32_t *)cmd_pkt + 2; | |
2836 | memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); | |
2837 | cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); | |
2838 | ||
2839 | /* Set NPORT-ID and LUN number*/ | |
2840 | cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); | |
2841 | cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; | |
2842 | cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; | |
2843 | cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; | |
2844 | cmd_pkt->vp_index = sp->fcport->vp_idx; | |
2845 | ||
2846 | /* Build IOCB segments */ | |
2847 | if (qla2xx_build_scsi_type_6_iocbs(sp, cmd_pkt, tot_dsds)) | |
2848 | goto queuing_error_fcp_cmnd; | |
2849 | ||
2850 | int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); | |
85727e1f | 2851 | host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, sizeof(cmd_pkt->lun)); |
a9083016 | 2852 | |
51cc9a8e SK |
2853 | /* build FCP_CMND IU */ |
2854 | memset(ctx->fcp_cmnd, 0, sizeof(struct fcp_cmnd)); | |
2855 | int_to_scsilun(sp->cmd->device->lun, &ctx->fcp_cmnd->lun); | |
2856 | ctx->fcp_cmnd->additional_cdb_len = additional_cdb_len; | |
2857 | ||
2858 | if (cmd->sc_data_direction == DMA_TO_DEVICE) | |
2859 | ctx->fcp_cmnd->additional_cdb_len |= 1; | |
2860 | else if (cmd->sc_data_direction == DMA_FROM_DEVICE) | |
2861 | ctx->fcp_cmnd->additional_cdb_len |= 2; | |
2862 | ||
ff2fc42e AV |
2863 | /* |
2864 | * Update tagged queuing modifier -- default is TSK_SIMPLE (0). | |
2865 | */ | |
2866 | if (scsi_populate_tag_msg(cmd, tag)) { | |
2867 | switch (tag[0]) { | |
2868 | case HEAD_OF_QUEUE_TAG: | |
2869 | ctx->fcp_cmnd->task_attribute = | |
2870 | TSK_HEAD_OF_QUEUE; | |
2871 | break; | |
2872 | case ORDERED_QUEUE_TAG: | |
2873 | ctx->fcp_cmnd->task_attribute = | |
2874 | TSK_ORDERED; | |
2875 | break; | |
2876 | } | |
2877 | } | |
2878 | ||
a9083016 GM |
2879 | memcpy(ctx->fcp_cmnd->cdb, cmd->cmnd, cmd->cmd_len); |
2880 | ||
2881 | fcp_dl = (uint32_t *)(ctx->fcp_cmnd->cdb + 16 + | |
2882 | additional_cdb_len); | |
2883 | *fcp_dl = htonl((uint32_t)scsi_bufflen(cmd)); | |
2884 | ||
2885 | cmd_pkt->fcp_cmnd_dseg_len = cpu_to_le16(ctx->fcp_cmnd_len); | |
2886 | cmd_pkt->fcp_cmnd_dseg_address[0] = | |
2887 | cpu_to_le32(LSD(ctx->fcp_cmnd_dma)); | |
2888 | cmd_pkt->fcp_cmnd_dseg_address[1] = | |
2889 | cpu_to_le32(MSD(ctx->fcp_cmnd_dma)); | |
2890 | ||
2891 | sp->flags |= SRB_FCP_CMND_DMA_VALID; | |
2892 | cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); | |
2893 | /* Set total data segment count. */ | |
2894 | cmd_pkt->entry_count = (uint8_t)req_cnt; | |
2895 | /* Specify response queue number where | |
2896 | * completion should happen | |
2897 | */ | |
2898 | cmd_pkt->entry_status = (uint8_t) rsp->id; | |
2899 | } else { | |
2900 | struct cmd_type_7 *cmd_pkt; | |
7c3df132 | 2901 | req_cnt = qla24xx_calc_iocbs(vha, tot_dsds); |
a9083016 GM |
2902 | if (req->cnt < (req_cnt + 2)) { |
2903 | cnt = (uint16_t)RD_REG_DWORD_RELAXED( | |
2904 | ®->req_q_out[0]); | |
2905 | if (req->ring_index < cnt) | |
2906 | req->cnt = cnt - req->ring_index; | |
2907 | else | |
2908 | req->cnt = req->length - | |
2909 | (req->ring_index - cnt); | |
2910 | } | |
2911 | if (req->cnt < (req_cnt + 2)) | |
2912 | goto queuing_error; | |
2913 | ||
2914 | cmd_pkt = (struct cmd_type_7 *)req->ring_ptr; | |
2915 | cmd_pkt->handle = MAKE_HANDLE(req->id, handle); | |
2916 | ||
2917 | /* Zero out remaining portion of packet. */ | |
2918 | /* tagged queuing modifier -- default is TSK_SIMPLE (0).*/ | |
2919 | clr_ptr = (uint32_t *)cmd_pkt + 2; | |
2920 | memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); | |
2921 | cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); | |
2922 | ||
2923 | /* Set NPORT-ID and LUN number*/ | |
2924 | cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); | |
2925 | cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; | |
2926 | cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; | |
2927 | cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; | |
2928 | cmd_pkt->vp_index = sp->fcport->vp_idx; | |
2929 | ||
2930 | int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); | |
2931 | host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, | |
2932 | sizeof(cmd_pkt->lun)); | |
2933 | ||
ff2fc42e AV |
2934 | /* |
2935 | * Update tagged queuing modifier -- default is TSK_SIMPLE (0). | |
2936 | */ | |
2937 | if (scsi_populate_tag_msg(cmd, tag)) { | |
2938 | switch (tag[0]) { | |
2939 | case HEAD_OF_QUEUE_TAG: | |
2940 | cmd_pkt->task = TSK_HEAD_OF_QUEUE; | |
2941 | break; | |
2942 | case ORDERED_QUEUE_TAG: | |
2943 | cmd_pkt->task = TSK_ORDERED; | |
2944 | break; | |
2945 | } | |
2946 | } | |
2947 | ||
a9083016 GM |
2948 | /* Load SCSI command packet. */ |
2949 | memcpy(cmd_pkt->fcp_cdb, cmd->cmnd, cmd->cmd_len); | |
2950 | host_to_fcp_swap(cmd_pkt->fcp_cdb, sizeof(cmd_pkt->fcp_cdb)); | |
2951 | ||
2952 | cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); | |
2953 | ||
2954 | /* Build IOCB segments */ | |
2955 | qla24xx_build_scsi_iocbs(sp, cmd_pkt, tot_dsds); | |
2956 | ||
2957 | /* Set total data segment count. */ | |
2958 | cmd_pkt->entry_count = (uint8_t)req_cnt; | |
2959 | /* Specify response queue number where | |
2960 | * completion should happen. | |
2961 | */ | |
2962 | cmd_pkt->entry_status = (uint8_t) rsp->id; | |
2963 | ||
2964 | } | |
2965 | /* Build command packet. */ | |
2966 | req->current_outstanding_cmd = handle; | |
2967 | req->outstanding_cmds[handle] = sp; | |
2968 | sp->handle = handle; | |
2969 | sp->cmd->host_scribble = (unsigned char *)(unsigned long)handle; | |
2970 | req->cnt -= req_cnt; | |
2971 | wmb(); | |
2972 | ||
2973 | /* Adjust ring index. */ | |
2974 | req->ring_index++; | |
2975 | if (req->ring_index == req->length) { | |
2976 | req->ring_index = 0; | |
2977 | req->ring_ptr = req->ring; | |
2978 | } else | |
2979 | req->ring_ptr++; | |
2980 | ||
2981 | sp->flags |= SRB_DMA_VALID; | |
2982 | ||
2983 | /* Set chip new ring index. */ | |
2984 | /* write, read and verify logic */ | |
2985 | dbval = dbval | (req->id << 8) | (req->ring_index << 16); | |
2986 | if (ql2xdbwr) | |
2987 | qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); | |
2988 | else { | |
2989 | WRT_REG_DWORD( | |
2990 | (unsigned long __iomem *)ha->nxdb_wr_ptr, | |
2991 | dbval); | |
2992 | wmb(); | |
2993 | while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { | |
2994 | WRT_REG_DWORD( | |
2995 | (unsigned long __iomem *)ha->nxdb_wr_ptr, | |
2996 | dbval); | |
2997 | wmb(); | |
2998 | } | |
2999 | } | |
3000 | ||
3001 | /* Manage unprocessed RIO/ZIO commands in response queue. */ | |
3002 | if (vha->flags.process_response_queue && | |
3003 | rsp->ring_ptr->signature != RESPONSE_PROCESSED) | |
3004 | qla24xx_process_response_queue(vha, rsp); | |
3005 | ||
3006 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
3007 | return QLA_SUCCESS; | |
3008 | ||
3009 | queuing_error_fcp_cmnd: | |
3010 | dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd, ctx->fcp_cmnd_dma); | |
3011 | queuing_error: | |
3012 | if (tot_dsds) | |
3013 | scsi_dma_unmap(cmd); | |
3014 | ||
3015 | if (sp->ctx) { | |
3016 | mempool_free(sp->ctx, ha->ctx_mempool); | |
3017 | sp->ctx = NULL; | |
3018 | } | |
3019 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
3020 | ||
3021 | return QLA_FUNCTION_FAILED; | |
3022 | } | |
3023 | ||
77e334d2 | 3024 | static uint32_t * |
a9083016 GM |
3025 | qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, |
3026 | uint32_t length) | |
3027 | { | |
3028 | uint32_t i; | |
3029 | uint32_t val; | |
3030 | struct qla_hw_data *ha = vha->hw; | |
3031 | ||
3032 | /* Dword reads to flash. */ | |
3033 | for (i = 0; i < length/4; i++, faddr += 4) { | |
3034 | if (qla82xx_rom_fast_read(ha, faddr, &val)) { | |
7c3df132 SK |
3035 | ql_log(ql_log_warn, vha, 0x0106, |
3036 | "Do ROM fast read failed.\n"); | |
a9083016 GM |
3037 | goto done_read; |
3038 | } | |
3039 | dwptr[i] = __constant_cpu_to_le32(val); | |
3040 | } | |
3041 | done_read: | |
3042 | return dwptr; | |
3043 | } | |
3044 | ||
77e334d2 | 3045 | static int |
a9083016 GM |
3046 | qla82xx_unprotect_flash(struct qla_hw_data *ha) |
3047 | { | |
3048 | int ret; | |
3049 | uint32_t val; | |
7c3df132 | 3050 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
3051 | |
3052 | ret = ql82xx_rom_lock_d(ha); | |
3053 | if (ret < 0) { | |
7c3df132 SK |
3054 | ql_log(ql_log_warn, vha, 0xb014, |
3055 | "ROM Lock failed.\n"); | |
a9083016 GM |
3056 | return ret; |
3057 | } | |
3058 | ||
3059 | ret = qla82xx_read_status_reg(ha, &val); | |
3060 | if (ret < 0) | |
3061 | goto done_unprotect; | |
3062 | ||
0547fb37 | 3063 | val &= ~(BLOCK_PROTECT_BITS << 2); |
a9083016 GM |
3064 | ret = qla82xx_write_status_reg(ha, val); |
3065 | if (ret < 0) { | |
0547fb37 | 3066 | val |= (BLOCK_PROTECT_BITS << 2); |
a9083016 GM |
3067 | qla82xx_write_status_reg(ha, val); |
3068 | } | |
3069 | ||
3070 | if (qla82xx_write_disable_flash(ha) != 0) | |
7c3df132 SK |
3071 | ql_log(ql_log_warn, vha, 0xb015, |
3072 | "Write disable failed.\n"); | |
a9083016 GM |
3073 | |
3074 | done_unprotect: | |
d652e093 | 3075 | qla82xx_rom_unlock(ha); |
a9083016 GM |
3076 | return ret; |
3077 | } | |
3078 | ||
77e334d2 | 3079 | static int |
a9083016 GM |
3080 | qla82xx_protect_flash(struct qla_hw_data *ha) |
3081 | { | |
3082 | int ret; | |
3083 | uint32_t val; | |
7c3df132 | 3084 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
3085 | |
3086 | ret = ql82xx_rom_lock_d(ha); | |
3087 | if (ret < 0) { | |
7c3df132 SK |
3088 | ql_log(ql_log_warn, vha, 0xb016, |
3089 | "ROM Lock failed.\n"); | |
a9083016 GM |
3090 | return ret; |
3091 | } | |
3092 | ||
3093 | ret = qla82xx_read_status_reg(ha, &val); | |
3094 | if (ret < 0) | |
3095 | goto done_protect; | |
3096 | ||
0547fb37 | 3097 | val |= (BLOCK_PROTECT_BITS << 2); |
a9083016 GM |
3098 | /* LOCK all sectors */ |
3099 | ret = qla82xx_write_status_reg(ha, val); | |
3100 | if (ret < 0) | |
7c3df132 SK |
3101 | ql_log(ql_log_warn, vha, 0xb017, |
3102 | "Write status register failed.\n"); | |
a9083016 GM |
3103 | |
3104 | if (qla82xx_write_disable_flash(ha) != 0) | |
7c3df132 SK |
3105 | ql_log(ql_log_warn, vha, 0xb018, |
3106 | "Write disable failed.\n"); | |
a9083016 | 3107 | done_protect: |
d652e093 | 3108 | qla82xx_rom_unlock(ha); |
a9083016 GM |
3109 | return ret; |
3110 | } | |
3111 | ||
77e334d2 | 3112 | static int |
a9083016 GM |
3113 | qla82xx_erase_sector(struct qla_hw_data *ha, int addr) |
3114 | { | |
3115 | int ret = 0; | |
7c3df132 | 3116 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
a9083016 GM |
3117 | |
3118 | ret = ql82xx_rom_lock_d(ha); | |
3119 | if (ret < 0) { | |
7c3df132 SK |
3120 | ql_log(ql_log_warn, vha, 0xb019, |
3121 | "ROM Lock failed.\n"); | |
a9083016 GM |
3122 | return ret; |
3123 | } | |
3124 | ||
3125 | qla82xx_flash_set_write_enable(ha); | |
3126 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); | |
3127 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); | |
3128 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); | |
3129 | ||
3130 | if (qla82xx_wait_rom_done(ha)) { | |
7c3df132 SK |
3131 | ql_log(ql_log_warn, vha, 0xb01a, |
3132 | "Error waiting for rom done.\n"); | |
a9083016 GM |
3133 | ret = -1; |
3134 | goto done; | |
3135 | } | |
3136 | ret = qla82xx_flash_wait_write_finish(ha); | |
3137 | done: | |
d652e093 | 3138 | qla82xx_rom_unlock(ha); |
a9083016 GM |
3139 | return ret; |
3140 | } | |
3141 | ||
3142 | /* | |
3143 | * Address and length are byte address | |
3144 | */ | |
3145 | uint8_t * | |
3146 | qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, | |
3147 | uint32_t offset, uint32_t length) | |
3148 | { | |
3149 | scsi_block_requests(vha->host); | |
3150 | qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); | |
3151 | scsi_unblock_requests(vha->host); | |
3152 | return buf; | |
3153 | } | |
3154 | ||
3155 | static int | |
3156 | qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, | |
3157 | uint32_t faddr, uint32_t dwords) | |
3158 | { | |
3159 | int ret; | |
3160 | uint32_t liter; | |
3161 | uint32_t sec_mask, rest_addr; | |
3162 | dma_addr_t optrom_dma; | |
3163 | void *optrom = NULL; | |
3164 | int page_mode = 0; | |
3165 | struct qla_hw_data *ha = vha->hw; | |
3166 | ||
3167 | ret = -1; | |
3168 | ||
3169 | /* Prepare burst-capable write on supported ISPs. */ | |
3170 | if (page_mode && !(faddr & 0xfff) && | |
3171 | dwords > OPTROM_BURST_DWORDS) { | |
3172 | optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, | |
3173 | &optrom_dma, GFP_KERNEL); | |
3174 | if (!optrom) { | |
7c3df132 SK |
3175 | ql_log(ql_log_warn, vha, 0xb01b, |
3176 | "Unable to allocate memory " | |
3177 | "for optron burst write (%x KB).\n", | |
3178 | OPTROM_BURST_SIZE / 1024); | |
a9083016 GM |
3179 | } |
3180 | } | |
3181 | ||
3182 | rest_addr = ha->fdt_block_size - 1; | |
3183 | sec_mask = ~rest_addr; | |
3184 | ||
3185 | ret = qla82xx_unprotect_flash(ha); | |
3186 | if (ret) { | |
7c3df132 SK |
3187 | ql_log(ql_log_warn, vha, 0xb01c, |
3188 | "Unable to unprotect flash for update.\n"); | |
a9083016 GM |
3189 | goto write_done; |
3190 | } | |
3191 | ||
3192 | for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { | |
3193 | /* Are we at the beginning of a sector? */ | |
3194 | if ((faddr & rest_addr) == 0) { | |
3195 | ||
3196 | ret = qla82xx_erase_sector(ha, faddr); | |
3197 | if (ret) { | |
7c3df132 SK |
3198 | ql_log(ql_log_warn, vha, 0xb01d, |
3199 | "Unable to erase sector: address=%x.\n", | |
3200 | faddr); | |
a9083016 GM |
3201 | break; |
3202 | } | |
3203 | } | |
3204 | ||
3205 | /* Go with burst-write. */ | |
3206 | if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { | |
3207 | /* Copy data to DMA'ble buffer. */ | |
3208 | memcpy(optrom, dwptr, OPTROM_BURST_SIZE); | |
3209 | ||
3210 | ret = qla2x00_load_ram(vha, optrom_dma, | |
3211 | (ha->flash_data_off | faddr), | |
3212 | OPTROM_BURST_DWORDS); | |
3213 | if (ret != QLA_SUCCESS) { | |
7c3df132 | 3214 | ql_log(ql_log_warn, vha, 0xb01e, |
a9083016 GM |
3215 | "Unable to burst-write optrom segment " |
3216 | "(%x/%x/%llx).\n", ret, | |
3217 | (ha->flash_data_off | faddr), | |
3218 | (unsigned long long)optrom_dma); | |
7c3df132 | 3219 | ql_log(ql_log_warn, vha, 0xb01f, |
a9083016 GM |
3220 | "Reverting to slow-write.\n"); |
3221 | ||
3222 | dma_free_coherent(&ha->pdev->dev, | |
3223 | OPTROM_BURST_SIZE, optrom, optrom_dma); | |
3224 | optrom = NULL; | |
3225 | } else { | |
3226 | liter += OPTROM_BURST_DWORDS - 1; | |
3227 | faddr += OPTROM_BURST_DWORDS - 1; | |
3228 | dwptr += OPTROM_BURST_DWORDS - 1; | |
3229 | continue; | |
3230 | } | |
3231 | } | |
3232 | ||
3233 | ret = qla82xx_write_flash_dword(ha, faddr, | |
3234 | cpu_to_le32(*dwptr)); | |
3235 | if (ret) { | |
7c3df132 SK |
3236 | ql_dbg(ql_dbg_p3p, vha, 0xb020, |
3237 | "Unable to program flash address=%x data=%x.\n", | |
3238 | faddr, *dwptr); | |
a9083016 GM |
3239 | break; |
3240 | } | |
3241 | } | |
3242 | ||
3243 | ret = qla82xx_protect_flash(ha); | |
3244 | if (ret) | |
7c3df132 | 3245 | ql_log(ql_log_warn, vha, 0xb021, |
a9083016 GM |
3246 | "Unable to protect flash after update.\n"); |
3247 | write_done: | |
3248 | if (optrom) | |
3249 | dma_free_coherent(&ha->pdev->dev, | |
3250 | OPTROM_BURST_SIZE, optrom, optrom_dma); | |
3251 | return ret; | |
3252 | } | |
3253 | ||
3254 | int | |
3255 | qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, | |
3256 | uint32_t offset, uint32_t length) | |
3257 | { | |
3258 | int rval; | |
3259 | ||
3260 | /* Suspend HBA. */ | |
3261 | scsi_block_requests(vha->host); | |
3262 | rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, | |
3263 | length >> 2); | |
3264 | scsi_unblock_requests(vha->host); | |
3265 | ||
3266 | /* Convert return ISP82xx to generic */ | |
3267 | if (rval) | |
3268 | rval = QLA_FUNCTION_FAILED; | |
3269 | else | |
3270 | rval = QLA_SUCCESS; | |
3271 | return rval; | |
3272 | } | |
3273 | ||
3274 | void | |
3275 | qla82xx_start_iocbs(srb_t *sp) | |
3276 | { | |
3277 | struct qla_hw_data *ha = sp->fcport->vha->hw; | |
3278 | struct req_que *req = ha->req_q_map[0]; | |
3279 | struct device_reg_82xx __iomem *reg; | |
3280 | uint32_t dbval; | |
3281 | ||
3282 | /* Adjust ring index. */ | |
3283 | req->ring_index++; | |
3284 | if (req->ring_index == req->length) { | |
3285 | req->ring_index = 0; | |
3286 | req->ring_ptr = req->ring; | |
3287 | } else | |
3288 | req->ring_ptr++; | |
3289 | ||
3290 | reg = &ha->iobase->isp82; | |
3291 | dbval = 0x04 | (ha->portnum << 5); | |
3292 | ||
3293 | dbval = dbval | (req->id << 8) | (req->ring_index << 16); | |
6907869d GM |
3294 | if (ql2xdbwr) |
3295 | qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); | |
3296 | else { | |
3297 | WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); | |
a9083016 | 3298 | wmb(); |
6907869d GM |
3299 | while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { |
3300 | WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, | |
3301 | dbval); | |
3302 | wmb(); | |
3303 | } | |
a9083016 GM |
3304 | } |
3305 | } | |
3306 | ||
e6a4202a SS |
3307 | void qla82xx_rom_lock_recovery(struct qla_hw_data *ha) |
3308 | { | |
7c3df132 SK |
3309 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
3310 | ||
e6a4202a SS |
3311 | if (qla82xx_rom_lock(ha)) |
3312 | /* Someone else is holding the lock. */ | |
7c3df132 SK |
3313 | ql_log(ql_log_info, vha, 0xb022, |
3314 | "Resetting rom_lock.\n"); | |
e6a4202a SS |
3315 | |
3316 | /* | |
3317 | * Either we got the lock, or someone | |
3318 | * else died while holding it. | |
3319 | * In either case, unlock. | |
3320 | */ | |
d652e093 | 3321 | qla82xx_rom_unlock(ha); |
e6a4202a SS |
3322 | } |
3323 | ||
a9083016 GM |
3324 | /* |
3325 | * qla82xx_device_bootstrap | |
3326 | * Initialize device, set DEV_READY, start fw | |
3327 | * | |
3328 | * Note: | |
3329 | * IDC lock must be held upon entry | |
3330 | * | |
3331 | * Return: | |
3332 | * Success : 0 | |
3333 | * Failed : 1 | |
3334 | */ | |
3335 | static int | |
3336 | qla82xx_device_bootstrap(scsi_qla_host_t *vha) | |
3337 | { | |
e6a4202a SS |
3338 | int rval = QLA_SUCCESS; |
3339 | int i, timeout; | |
a9083016 GM |
3340 | uint32_t old_count, count; |
3341 | struct qla_hw_data *ha = vha->hw; | |
e6a4202a | 3342 | int need_reset = 0, peg_stuck = 1; |
a9083016 | 3343 | |
e6a4202a | 3344 | need_reset = qla82xx_need_reset(ha); |
a9083016 GM |
3345 | |
3346 | old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); | |
3347 | ||
3348 | for (i = 0; i < 10; i++) { | |
3349 | timeout = msleep_interruptible(200); | |
3350 | if (timeout) { | |
3351 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
3352 | QLA82XX_DEV_FAILED); | |
3353 | return QLA_FUNCTION_FAILED; | |
3354 | } | |
3355 | ||
3356 | count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); | |
3357 | if (count != old_count) | |
e6a4202a SS |
3358 | peg_stuck = 0; |
3359 | } | |
3360 | ||
3361 | if (need_reset) { | |
3362 | /* We are trying to perform a recovery here. */ | |
3363 | if (peg_stuck) | |
3364 | qla82xx_rom_lock_recovery(ha); | |
3365 | goto dev_initialize; | |
3366 | } else { | |
3367 | /* Start of day for this ha context. */ | |
3368 | if (peg_stuck) { | |
3369 | /* Either we are the first or recovery in progress. */ | |
3370 | qla82xx_rom_lock_recovery(ha); | |
3371 | goto dev_initialize; | |
3372 | } else | |
3373 | /* Firmware already running. */ | |
a9083016 GM |
3374 | goto dev_ready; |
3375 | } | |
3376 | ||
e6a4202a SS |
3377 | return rval; |
3378 | ||
a9083016 GM |
3379 | dev_initialize: |
3380 | /* set to DEV_INITIALIZING */ | |
7c3df132 SK |
3381 | ql_log(ql_log_info, vha, 0x009e, |
3382 | "HW State: INITIALIZING.\n"); | |
a9083016 GM |
3383 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); |
3384 | ||
3385 | /* Driver that sets device state to initializating sets IDC version */ | |
3386 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); | |
3387 | ||
3388 | qla82xx_idc_unlock(ha); | |
3389 | rval = qla82xx_start_firmware(vha); | |
3390 | qla82xx_idc_lock(ha); | |
3391 | ||
3392 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
3393 | ql_log(ql_log_fatal, vha, 0x00ad, |
3394 | "HW State: FAILED.\n"); | |
a9083016 GM |
3395 | qla82xx_clear_drv_active(ha); |
3396 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); | |
3397 | return rval; | |
3398 | } | |
3399 | ||
3400 | dev_ready: | |
7c3df132 SK |
3401 | ql_log(ql_log_info, vha, 0x00ae, |
3402 | "HW State: READY.\n"); | |
a9083016 GM |
3403 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); |
3404 | ||
3405 | return QLA_SUCCESS; | |
3406 | } | |
3407 | ||
579d12b5 SK |
3408 | /* |
3409 | * qla82xx_need_qsnt_handler | |
3410 | * Code to start quiescence sequence | |
3411 | * | |
3412 | * Note: | |
3413 | * IDC lock must be held upon entry | |
3414 | * | |
3415 | * Return: void | |
3416 | */ | |
3417 | ||
3418 | static void | |
3419 | qla82xx_need_qsnt_handler(scsi_qla_host_t *vha) | |
3420 | { | |
3421 | struct qla_hw_data *ha = vha->hw; | |
3422 | uint32_t dev_state, drv_state, drv_active; | |
3423 | unsigned long reset_timeout; | |
3424 | ||
3425 | if (vha->flags.online) { | |
3426 | /*Block any further I/O and wait for pending cmnds to complete*/ | |
3427 | qla82xx_quiescent_state_cleanup(vha); | |
3428 | } | |
3429 | ||
3430 | /* Set the quiescence ready bit */ | |
3431 | qla82xx_set_qsnt_ready(ha); | |
3432 | ||
3433 | /*wait for 30 secs for other functions to ack */ | |
3434 | reset_timeout = jiffies + (30 * HZ); | |
3435 | ||
3436 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | |
3437 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
3438 | /* Its 2 that is written when qsnt is acked, moving one bit */ | |
3439 | drv_active = drv_active << 0x01; | |
3440 | ||
3441 | while (drv_state != drv_active) { | |
3442 | ||
3443 | if (time_after_eq(jiffies, reset_timeout)) { | |
3444 | /* quiescence timeout, other functions didn't ack | |
3445 | * changing the state to DEV_READY | |
3446 | */ | |
7c3df132 SK |
3447 | ql_log(ql_log_info, vha, 0xb023, |
3448 | "%s : QUIESCENT TIMEOUT.\n", QLA2XXX_DRIVER_NAME); | |
3449 | ql_log(ql_log_info, vha, 0xb024, | |
3450 | "DRV_ACTIVE:%d DRV_STATE:%d.\n", | |
3451 | drv_active, drv_state); | |
579d12b5 | 3452 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
7c3df132 SK |
3453 | QLA82XX_DEV_READY); |
3454 | ql_log(ql_log_info, vha, 0xb025, | |
3455 | "HW State: DEV_READY.\n"); | |
579d12b5 SK |
3456 | qla82xx_idc_unlock(ha); |
3457 | qla2x00_perform_loop_resync(vha); | |
3458 | qla82xx_idc_lock(ha); | |
3459 | ||
3460 | qla82xx_clear_qsnt_ready(vha); | |
3461 | return; | |
3462 | } | |
3463 | ||
3464 | qla82xx_idc_unlock(ha); | |
3465 | msleep(1000); | |
3466 | qla82xx_idc_lock(ha); | |
3467 | ||
3468 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | |
3469 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
3470 | drv_active = drv_active << 0x01; | |
3471 | } | |
3472 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | |
3473 | /* everyone acked so set the state to DEV_QUIESCENCE */ | |
3474 | if (dev_state == QLA82XX_DEV_NEED_QUIESCENT) { | |
7c3df132 SK |
3475 | ql_log(ql_log_info, vha, 0xb026, |
3476 | "HW State: DEV_QUIESCENT.\n"); | |
579d12b5 SK |
3477 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_QUIESCENT); |
3478 | } | |
3479 | } | |
3480 | ||
3481 | /* | |
3482 | * qla82xx_wait_for_state_change | |
3483 | * Wait for device state to change from given current state | |
3484 | * | |
3485 | * Note: | |
3486 | * IDC lock must not be held upon entry | |
3487 | * | |
3488 | * Return: | |
3489 | * Changed device state. | |
3490 | */ | |
3491 | uint32_t | |
3492 | qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state) | |
3493 | { | |
3494 | struct qla_hw_data *ha = vha->hw; | |
3495 | uint32_t dev_state; | |
3496 | ||
3497 | do { | |
3498 | msleep(1000); | |
3499 | qla82xx_idc_lock(ha); | |
3500 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | |
3501 | qla82xx_idc_unlock(ha); | |
3502 | } while (dev_state == curr_state); | |
3503 | ||
3504 | return dev_state; | |
3505 | } | |
3506 | ||
a9083016 GM |
3507 | static void |
3508 | qla82xx_dev_failed_handler(scsi_qla_host_t *vha) | |
3509 | { | |
3510 | struct qla_hw_data *ha = vha->hw; | |
3511 | ||
3512 | /* Disable the board */ | |
7c3df132 SK |
3513 | ql_log(ql_log_fatal, vha, 0x00b8, |
3514 | "Disabling the board.\n"); | |
a9083016 | 3515 | |
b963752f GM |
3516 | qla82xx_idc_lock(ha); |
3517 | qla82xx_clear_drv_active(ha); | |
3518 | qla82xx_idc_unlock(ha); | |
3519 | ||
a9083016 GM |
3520 | /* Set DEV_FAILED flag to disable timer */ |
3521 | vha->device_flags |= DFLG_DEV_FAILED; | |
3522 | qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); | |
3523 | qla2x00_mark_all_devices_lost(vha, 0); | |
3524 | vha->flags.online = 0; | |
3525 | vha->flags.init_done = 0; | |
3526 | } | |
3527 | ||
3528 | /* | |
3529 | * qla82xx_need_reset_handler | |
3530 | * Code to start reset sequence | |
3531 | * | |
3532 | * Note: | |
3533 | * IDC lock must be held upon entry | |
3534 | * | |
3535 | * Return: | |
3536 | * Success : 0 | |
3537 | * Failed : 1 | |
3538 | */ | |
3539 | static void | |
3540 | qla82xx_need_reset_handler(scsi_qla_host_t *vha) | |
3541 | { | |
e5fdae55 CD |
3542 | uint32_t dev_state, drv_state, drv_active; |
3543 | uint32_t active_mask = 0; | |
a9083016 GM |
3544 | unsigned long reset_timeout; |
3545 | struct qla_hw_data *ha = vha->hw; | |
3546 | struct req_que *req = ha->req_q_map[0]; | |
3547 | ||
3548 | if (vha->flags.online) { | |
3549 | qla82xx_idc_unlock(ha); | |
3550 | qla2x00_abort_isp_cleanup(vha); | |
3551 | ha->isp_ops->get_flash_version(vha, req->ring); | |
3552 | ha->isp_ops->nvram_config(vha); | |
3553 | qla82xx_idc_lock(ha); | |
3554 | } | |
3555 | ||
08de2844 GM |
3556 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); |
3557 | if (!ha->flags.isp82xx_reset_owner) { | |
3558 | ql_dbg(ql_dbg_p3p, vha, 0xb028, | |
3559 | "reset_acknowledged by 0x%x\n", ha->portnum); | |
3560 | qla82xx_set_rst_ready(ha); | |
3561 | } else { | |
3562 | active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4)); | |
3563 | drv_active &= active_mask; | |
3564 | ql_dbg(ql_dbg_p3p, vha, 0xb029, | |
3565 | "active_mask: 0x%08x\n", active_mask); | |
3566 | } | |
a9083016 GM |
3567 | |
3568 | /* wait for 10 seconds for reset ack from all functions */ | |
3569 | reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); | |
3570 | ||
3571 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | |
3572 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
08de2844 | 3573 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); |
a9083016 | 3574 | |
08de2844 GM |
3575 | ql_dbg(ql_dbg_p3p, vha, 0xb02a, |
3576 | "drv_state: 0x%08x, drv_active: 0x%08x, " | |
3577 | "dev_state: 0x%08x, active_mask: 0x%08x\n", | |
3578 | drv_state, drv_active, dev_state, active_mask); | |
3579 | ||
3580 | while (drv_state != drv_active && | |
3581 | dev_state != QLA82XX_DEV_INITIALIZING) { | |
a9083016 | 3582 | if (time_after_eq(jiffies, reset_timeout)) { |
7c3df132 SK |
3583 | ql_log(ql_log_warn, vha, 0x00b5, |
3584 | "Reset timeout.\n"); | |
a9083016 GM |
3585 | break; |
3586 | } | |
3587 | qla82xx_idc_unlock(ha); | |
3588 | msleep(1000); | |
3589 | qla82xx_idc_lock(ha); | |
3590 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | |
3591 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
08de2844 GM |
3592 | if (ha->flags.isp82xx_reset_owner) |
3593 | drv_active &= active_mask; | |
3594 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | |
a9083016 GM |
3595 | } |
3596 | ||
08de2844 GM |
3597 | ql_dbg(ql_dbg_p3p, vha, 0xb02b, |
3598 | "drv_state: 0x%08x, drv_active: 0x%08x, " | |
3599 | "dev_state: 0x%08x, active_mask: 0x%08x\n", | |
3600 | drv_state, drv_active, dev_state, active_mask); | |
3601 | ||
7c3df132 SK |
3602 | ql_log(ql_log_info, vha, 0x00b6, |
3603 | "Device state is 0x%x = %s.\n", | |
3604 | dev_state, | |
08de2844 | 3605 | dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); |
f1af6208 | 3606 | |
a9083016 | 3607 | /* Force to DEV_COLD unless someone else is starting a reset */ |
08de2844 GM |
3608 | if (dev_state != QLA82XX_DEV_INITIALIZING && |
3609 | dev_state != QLA82XX_DEV_COLD) { | |
7c3df132 SK |
3610 | ql_log(ql_log_info, vha, 0x00b7, |
3611 | "HW State: COLD/RE-INIT.\n"); | |
a9083016 | 3612 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); |
08de2844 GM |
3613 | if (ql2xmdenable) { |
3614 | if (qla82xx_md_collect(vha)) | |
3615 | ql_log(ql_log_warn, vha, 0xb02c, | |
3616 | "Not able to collect minidump.\n"); | |
3617 | } else | |
3618 | ql_log(ql_log_warn, vha, 0xb04f, | |
3619 | "Minidump disabled.\n"); | |
a9083016 GM |
3620 | } |
3621 | } | |
3622 | ||
3173167f | 3623 | int |
08de2844 GM |
3624 | qla82xx_check_md_needed(scsi_qla_host_t *vha) |
3625 | { | |
3626 | struct qla_hw_data *ha = vha->hw; | |
3627 | uint16_t fw_major_version, fw_minor_version, fw_subminor_version; | |
3173167f GM |
3628 | int rval = QLA_SUCCESS; |
3629 | ||
3630 | fw_major_version = ha->fw_major_version; | |
3631 | fw_minor_version = ha->fw_minor_version; | |
3632 | fw_subminor_version = ha->fw_subminor_version; | |
3633 | ||
3634 | rval = qla2x00_get_fw_version(vha, &ha->fw_major_version, | |
3635 | &ha->fw_minor_version, &ha->fw_subminor_version, | |
3636 | &ha->fw_attributes, &ha->fw_memory_size, | |
3637 | ha->mpi_version, &ha->mpi_capabilities, | |
3638 | ha->phy_version); | |
3639 | ||
3640 | if (rval != QLA_SUCCESS) | |
3641 | return rval; | |
3642 | ||
3643 | if (ql2xmdenable) { | |
3644 | if (!ha->fw_dumped) { | |
3645 | if (fw_major_version != ha->fw_major_version || | |
3646 | fw_minor_version != ha->fw_minor_version || | |
3647 | fw_subminor_version != ha->fw_subminor_version) { | |
3648 | ||
3649 | ql_log(ql_log_info, vha, 0xb02d, | |
3650 | "Firmware version differs " | |
3651 | "Previous version: %d:%d:%d - " | |
3652 | "New version: %d:%d:%d\n", | |
3653 | ha->fw_major_version, | |
3654 | ha->fw_minor_version, | |
3655 | ha->fw_subminor_version, | |
3656 | fw_major_version, fw_minor_version, | |
3657 | fw_subminor_version); | |
3658 | /* Release MiniDump resources */ | |
3659 | qla82xx_md_free(vha); | |
3660 | /* ALlocate MiniDump resources */ | |
3661 | qla82xx_md_prep(vha); | |
3662 | } else | |
3663 | ql_log(ql_log_info, vha, 0xb02e, | |
3664 | "Firmware dump available to retrieve\n", | |
3665 | vha->host_no); | |
08de2844 | 3666 | } |
3173167f GM |
3667 | } |
3668 | return rval; | |
08de2844 GM |
3669 | } |
3670 | ||
3671 | ||
7190575f | 3672 | int |
a9083016 GM |
3673 | qla82xx_check_fw_alive(scsi_qla_host_t *vha) |
3674 | { | |
7190575f GM |
3675 | uint32_t fw_heartbeat_counter; |
3676 | int status = 0; | |
a9083016 | 3677 | |
7190575f GM |
3678 | fw_heartbeat_counter = qla82xx_rd_32(vha->hw, |
3679 | QLA82XX_PEG_ALIVE_COUNTER); | |
a5b36321 | 3680 | /* all 0xff, assume AER/EEH in progress, ignore */ |
7c3df132 SK |
3681 | if (fw_heartbeat_counter == 0xffffffff) { |
3682 | ql_dbg(ql_dbg_timer, vha, 0x6003, | |
3683 | "FW heartbeat counter is 0xffffffff, " | |
3684 | "returning status=%d.\n", status); | |
7190575f | 3685 | return status; |
7c3df132 | 3686 | } |
a9083016 GM |
3687 | if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { |
3688 | vha->seconds_since_last_heartbeat++; | |
3689 | /* FW not alive after 2 seconds */ | |
3690 | if (vha->seconds_since_last_heartbeat == 2) { | |
3691 | vha->seconds_since_last_heartbeat = 0; | |
7190575f | 3692 | status = 1; |
a9083016 | 3693 | } |
efa786cc LC |
3694 | } else |
3695 | vha->seconds_since_last_heartbeat = 0; | |
a9083016 | 3696 | vha->fw_heartbeat_counter = fw_heartbeat_counter; |
7c3df132 SK |
3697 | if (status) |
3698 | ql_dbg(ql_dbg_timer, vha, 0x6004, | |
3699 | "Returning status=%d.\n", status); | |
7190575f | 3700 | return status; |
a9083016 GM |
3701 | } |
3702 | ||
3703 | /* | |
3704 | * qla82xx_device_state_handler | |
3705 | * Main state handler | |
3706 | * | |
3707 | * Note: | |
3708 | * IDC lock must be held upon entry | |
3709 | * | |
3710 | * Return: | |
3711 | * Success : 0 | |
3712 | * Failed : 1 | |
3713 | */ | |
3714 | int | |
3715 | qla82xx_device_state_handler(scsi_qla_host_t *vha) | |
3716 | { | |
3717 | uint32_t dev_state; | |
92dbf273 | 3718 | uint32_t old_dev_state; |
a9083016 GM |
3719 | int rval = QLA_SUCCESS; |
3720 | unsigned long dev_init_timeout; | |
3721 | struct qla_hw_data *ha = vha->hw; | |
92dbf273 | 3722 | int loopcount = 0; |
a9083016 GM |
3723 | |
3724 | qla82xx_idc_lock(ha); | |
3725 | if (!vha->flags.init_done) | |
3726 | qla82xx_set_drv_active(vha); | |
3727 | ||
f1af6208 | 3728 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); |
92dbf273 | 3729 | old_dev_state = dev_state; |
7c3df132 SK |
3730 | ql_log(ql_log_info, vha, 0x009b, |
3731 | "Device state is 0x%x = %s.\n", | |
3732 | dev_state, | |
08de2844 | 3733 | dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); |
a9083016 GM |
3734 | |
3735 | /* wait for 30 seconds for device to go ready */ | |
3736 | dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); | |
3737 | ||
3738 | while (1) { | |
3739 | ||
3740 | if (time_after_eq(jiffies, dev_init_timeout)) { | |
7c3df132 SK |
3741 | ql_log(ql_log_fatal, vha, 0x009c, |
3742 | "Device init failed.\n"); | |
a9083016 GM |
3743 | rval = QLA_FUNCTION_FAILED; |
3744 | break; | |
3745 | } | |
3746 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | |
92dbf273 GM |
3747 | if (old_dev_state != dev_state) { |
3748 | loopcount = 0; | |
3749 | old_dev_state = dev_state; | |
3750 | } | |
3751 | if (loopcount < 5) { | |
7c3df132 SK |
3752 | ql_log(ql_log_info, vha, 0x009d, |
3753 | "Device state is 0x%x = %s.\n", | |
3754 | dev_state, | |
08de2844 | 3755 | dev_state < MAX_STATES ? qdev_state(dev_state) : |
7c3df132 | 3756 | "Unknown"); |
92dbf273 | 3757 | } |
f1af6208 | 3758 | |
a9083016 GM |
3759 | switch (dev_state) { |
3760 | case QLA82XX_DEV_READY: | |
08de2844 GM |
3761 | qla82xx_check_md_needed(vha); |
3762 | ha->flags.isp82xx_reset_owner = 0; | |
a9083016 GM |
3763 | goto exit; |
3764 | case QLA82XX_DEV_COLD: | |
3765 | rval = qla82xx_device_bootstrap(vha); | |
08de2844 | 3766 | break; |
a9083016 GM |
3767 | case QLA82XX_DEV_INITIALIZING: |
3768 | qla82xx_idc_unlock(ha); | |
3769 | msleep(1000); | |
3770 | qla82xx_idc_lock(ha); | |
3771 | break; | |
3772 | case QLA82XX_DEV_NEED_RESET: | |
c8582ad9 SK |
3773 | if (!ql2xdontresethba) |
3774 | qla82xx_need_reset_handler(vha); | |
3775 | else { | |
3776 | qla82xx_idc_unlock(ha); | |
3777 | msleep(1000); | |
3778 | qla82xx_idc_lock(ha); | |
3779 | } | |
0060ddf8 | 3780 | dev_init_timeout = jiffies + |
c8582ad9 | 3781 | (ha->nx_dev_init_timeout * HZ); |
a9083016 GM |
3782 | break; |
3783 | case QLA82XX_DEV_NEED_QUIESCENT: | |
579d12b5 SK |
3784 | qla82xx_need_qsnt_handler(vha); |
3785 | /* Reset timeout value after quiescence handler */ | |
3786 | dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ | |
3787 | * HZ); | |
3788 | break; | |
a9083016 | 3789 | case QLA82XX_DEV_QUIESCENT: |
579d12b5 SK |
3790 | /* Owner will exit and other will wait for the state |
3791 | * to get changed | |
3792 | */ | |
3793 | if (ha->flags.quiesce_owner) | |
3794 | goto exit; | |
3795 | ||
a9083016 GM |
3796 | qla82xx_idc_unlock(ha); |
3797 | msleep(1000); | |
3798 | qla82xx_idc_lock(ha); | |
579d12b5 SK |
3799 | |
3800 | /* Reset timeout value after quiescence handler */ | |
3801 | dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\ | |
3802 | * HZ); | |
a9083016 GM |
3803 | break; |
3804 | case QLA82XX_DEV_FAILED: | |
3805 | qla82xx_dev_failed_handler(vha); | |
3806 | rval = QLA_FUNCTION_FAILED; | |
3807 | goto exit; | |
3808 | default: | |
3809 | qla82xx_idc_unlock(ha); | |
3810 | msleep(1000); | |
3811 | qla82xx_idc_lock(ha); | |
3812 | } | |
92dbf273 | 3813 | loopcount++; |
a9083016 GM |
3814 | } |
3815 | exit: | |
3816 | qla82xx_idc_unlock(ha); | |
3817 | return rval; | |
3818 | } | |
3819 | ||
c8f6544e CD |
3820 | void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha) |
3821 | { | |
3822 | struct qla_hw_data *ha = vha->hw; | |
3823 | ||
3824 | if (ha->flags.mbox_busy) { | |
3825 | ha->flags.mbox_int = 1; | |
8937f2f1 | 3826 | ha->flags.mbox_busy = 0; |
c8f6544e CD |
3827 | ql_log(ql_log_warn, vha, 0x6010, |
3828 | "Doing premature completion of mbx command.\n"); | |
3829 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) | |
3830 | complete(&ha->mbx_intr_comp); | |
3831 | } | |
3832 | } | |
3833 | ||
a9083016 GM |
3834 | void qla82xx_watchdog(scsi_qla_host_t *vha) |
3835 | { | |
7190575f | 3836 | uint32_t dev_state, halt_status; |
a9083016 GM |
3837 | struct qla_hw_data *ha = vha->hw; |
3838 | ||
a9083016 | 3839 | /* don't poll if reset is going on */ |
7190575f GM |
3840 | if (!ha->flags.isp82xx_reset_hdlr_active) { |
3841 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | |
3842 | if (dev_state == QLA82XX_DEV_NEED_RESET && | |
3843 | !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { | |
7c3df132 SK |
3844 | ql_log(ql_log_warn, vha, 0x6001, |
3845 | "Adapter reset needed.\n"); | |
a9083016 GM |
3846 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); |
3847 | qla2xxx_wake_dpc(vha); | |
579d12b5 SK |
3848 | } else if (dev_state == QLA82XX_DEV_NEED_QUIESCENT && |
3849 | !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { | |
7c3df132 SK |
3850 | ql_log(ql_log_warn, vha, 0x6002, |
3851 | "Quiescent needed.\n"); | |
579d12b5 SK |
3852 | set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); |
3853 | qla2xxx_wake_dpc(vha); | |
a9083016 | 3854 | } else { |
7190575f GM |
3855 | if (qla82xx_check_fw_alive(vha)) { |
3856 | halt_status = qla82xx_rd_32(ha, | |
3857 | QLA82XX_PEG_HALT_STATUS1); | |
7c3df132 SK |
3858 | ql_dbg(ql_dbg_timer, vha, 0x6005, |
3859 | "dumping hw/fw registers:.\n " | |
3860 | " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " | |
3861 | " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " | |
3862 | " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " | |
3863 | " PEG_NET_4_PC: 0x%x.\n", halt_status, | |
0e8edb03 GM |
3864 | qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2), |
3865 | qla82xx_rd_32(ha, | |
3866 | QLA82XX_CRB_PEG_NET_0 + 0x3c), | |
3867 | qla82xx_rd_32(ha, | |
3868 | QLA82XX_CRB_PEG_NET_1 + 0x3c), | |
3869 | qla82xx_rd_32(ha, | |
3870 | QLA82XX_CRB_PEG_NET_2 + 0x3c), | |
3871 | qla82xx_rd_32(ha, | |
3872 | QLA82XX_CRB_PEG_NET_3 + 0x3c), | |
3873 | qla82xx_rd_32(ha, | |
3874 | QLA82XX_CRB_PEG_NET_4 + 0x3c)); | |
10a340e6 CD |
3875 | if (LSW(MSB(halt_status)) == 0x67) |
3876 | ql_log(ql_log_warn, vha, 0xb052, | |
3877 | "Firmware aborted with " | |
3878 | "error code 0x00006700. Device is " | |
3879 | "being reset.\n"); | |
7190575f GM |
3880 | if (halt_status & HALT_STATUS_UNRECOVERABLE) { |
3881 | set_bit(ISP_UNRECOVERABLE, | |
3882 | &vha->dpc_flags); | |
3883 | } else { | |
7c3df132 SK |
3884 | ql_log(ql_log_info, vha, 0x6006, |
3885 | "Detect abort needed.\n"); | |
7190575f GM |
3886 | set_bit(ISP_ABORT_NEEDED, |
3887 | &vha->dpc_flags); | |
3888 | } | |
3889 | qla2xxx_wake_dpc(vha); | |
3890 | ha->flags.isp82xx_fw_hung = 1; | |
c8f6544e CD |
3891 | ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); |
3892 | qla82xx_clear_pending_mbx(vha); | |
7190575f | 3893 | } |
a9083016 GM |
3894 | } |
3895 | } | |
3896 | } | |
3897 | ||
3898 | int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) | |
3899 | { | |
3900 | int rval; | |
3901 | rval = qla82xx_device_state_handler(vha); | |
3902 | return rval; | |
3903 | } | |
3904 | ||
08de2844 GM |
3905 | void |
3906 | qla82xx_set_reset_owner(scsi_qla_host_t *vha) | |
3907 | { | |
3908 | struct qla_hw_data *ha = vha->hw; | |
3909 | uint32_t dev_state; | |
3910 | ||
3911 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | |
3912 | if (dev_state == QLA82XX_DEV_READY) { | |
3913 | ql_log(ql_log_info, vha, 0xb02f, | |
3914 | "HW State: NEED RESET\n"); | |
3915 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
3916 | QLA82XX_DEV_NEED_RESET); | |
3917 | ha->flags.isp82xx_reset_owner = 1; | |
3918 | ql_dbg(ql_dbg_p3p, vha, 0xb030, | |
3919 | "reset_owner is 0x%x\n", ha->portnum); | |
3920 | } else | |
3921 | ql_log(ql_log_info, vha, 0xb031, | |
3922 | "Device state is 0x%x = %s.\n", | |
3923 | dev_state, | |
3924 | dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown"); | |
3925 | } | |
3926 | ||
a9083016 GM |
3927 | /* |
3928 | * qla82xx_abort_isp | |
3929 | * Resets ISP and aborts all outstanding commands. | |
3930 | * | |
3931 | * Input: | |
3932 | * ha = adapter block pointer. | |
3933 | * | |
3934 | * Returns: | |
3935 | * 0 = success | |
3936 | */ | |
3937 | int | |
3938 | qla82xx_abort_isp(scsi_qla_host_t *vha) | |
3939 | { | |
3940 | int rval; | |
3941 | struct qla_hw_data *ha = vha->hw; | |
a9083016 GM |
3942 | |
3943 | if (vha->device_flags & DFLG_DEV_FAILED) { | |
7c3df132 SK |
3944 | ql_log(ql_log_warn, vha, 0x8024, |
3945 | "Device in failed state, exiting.\n"); | |
a9083016 GM |
3946 | return QLA_SUCCESS; |
3947 | } | |
7190575f | 3948 | ha->flags.isp82xx_reset_hdlr_active = 1; |
a9083016 GM |
3949 | |
3950 | qla82xx_idc_lock(ha); | |
08de2844 | 3951 | qla82xx_set_reset_owner(vha); |
a9083016 GM |
3952 | qla82xx_idc_unlock(ha); |
3953 | ||
3954 | rval = qla82xx_device_state_handler(vha); | |
3955 | ||
3956 | qla82xx_idc_lock(ha); | |
3957 | qla82xx_clear_rst_ready(ha); | |
3958 | qla82xx_idc_unlock(ha); | |
3959 | ||
cdbb0a4f | 3960 | if (rval == QLA_SUCCESS) { |
7190575f GM |
3961 | ha->flags.isp82xx_fw_hung = 0; |
3962 | ha->flags.isp82xx_reset_hdlr_active = 0; | |
a9083016 | 3963 | qla82xx_restart_isp(vha); |
cdbb0a4f | 3964 | } |
f1af6208 GM |
3965 | |
3966 | if (rval) { | |
3967 | vha->flags.online = 1; | |
3968 | if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { | |
3969 | if (ha->isp_abort_cnt == 0) { | |
7c3df132 SK |
3970 | ql_log(ql_log_warn, vha, 0x8027, |
3971 | "ISP error recover failed - board " | |
3972 | "disabled.\n"); | |
f1af6208 GM |
3973 | /* |
3974 | * The next call disables the board | |
3975 | * completely. | |
3976 | */ | |
3977 | ha->isp_ops->reset_adapter(vha); | |
3978 | vha->flags.online = 0; | |
3979 | clear_bit(ISP_ABORT_RETRY, | |
3980 | &vha->dpc_flags); | |
3981 | rval = QLA_SUCCESS; | |
3982 | } else { /* schedule another ISP abort */ | |
3983 | ha->isp_abort_cnt--; | |
7c3df132 SK |
3984 | ql_log(ql_log_warn, vha, 0x8036, |
3985 | "ISP abort - retry remaining %d.\n", | |
3986 | ha->isp_abort_cnt); | |
f1af6208 GM |
3987 | rval = QLA_FUNCTION_FAILED; |
3988 | } | |
3989 | } else { | |
3990 | ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; | |
7c3df132 SK |
3991 | ql_dbg(ql_dbg_taskm, vha, 0x8029, |
3992 | "ISP error recovery - retrying (%d) more times.\n", | |
3993 | ha->isp_abort_cnt); | |
f1af6208 GM |
3994 | set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); |
3995 | rval = QLA_FUNCTION_FAILED; | |
3996 | } | |
3997 | } | |
a9083016 GM |
3998 | return rval; |
3999 | } | |
4000 | ||
4001 | /* | |
4002 | * qla82xx_fcoe_ctx_reset | |
4003 | * Perform a quick reset and aborts all outstanding commands. | |
4004 | * This will only perform an FCoE context reset and avoids a full blown | |
4005 | * chip reset. | |
4006 | * | |
4007 | * Input: | |
4008 | * ha = adapter block pointer. | |
4009 | * is_reset_path = flag for identifying the reset path. | |
4010 | * | |
4011 | * Returns: | |
4012 | * 0 = success | |
4013 | */ | |
4014 | int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) | |
4015 | { | |
4016 | int rval = QLA_FUNCTION_FAILED; | |
4017 | ||
4018 | if (vha->flags.online) { | |
4019 | /* Abort all outstanding commands, so as to be requeued later */ | |
4020 | qla2x00_abort_isp_cleanup(vha); | |
4021 | } | |
4022 | ||
4023 | /* Stop currently executing firmware. | |
4024 | * This will destroy existing FCoE context at the F/W end. | |
4025 | */ | |
4026 | qla2x00_try_to_stop_firmware(vha); | |
4027 | ||
4028 | /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ | |
4029 | rval = qla82xx_restart_isp(vha); | |
4030 | ||
4031 | return rval; | |
4032 | } | |
4033 | ||
4034 | /* | |
4035 | * qla2x00_wait_for_fcoe_ctx_reset | |
4036 | * Wait till the FCoE context is reset. | |
4037 | * | |
4038 | * Note: | |
4039 | * Does context switching here. | |
4040 | * Release SPIN_LOCK (if any) before calling this routine. | |
4041 | * | |
4042 | * Return: | |
4043 | * Success (fcoe_ctx reset is done) : 0 | |
4044 | * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 | |
4045 | */ | |
4046 | int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) | |
4047 | { | |
4048 | int status = QLA_FUNCTION_FAILED; | |
4049 | unsigned long wait_reset; | |
4050 | ||
4051 | wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); | |
4052 | while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || | |
4053 | test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) | |
4054 | && time_before(jiffies, wait_reset)) { | |
4055 | ||
4056 | set_current_state(TASK_UNINTERRUPTIBLE); | |
4057 | schedule_timeout(HZ); | |
4058 | ||
4059 | if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && | |
4060 | !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { | |
4061 | status = QLA_SUCCESS; | |
4062 | break; | |
4063 | } | |
4064 | } | |
7c3df132 SK |
4065 | ql_dbg(ql_dbg_p3p, vha, 0xb027, |
4066 | "%s status=%d.\n", status); | |
a9083016 GM |
4067 | |
4068 | return status; | |
4069 | } | |
7190575f GM |
4070 | |
4071 | void | |
4072 | qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha) | |
4073 | { | |
4074 | int i; | |
4075 | unsigned long flags; | |
4076 | struct qla_hw_data *ha = vha->hw; | |
4077 | ||
4078 | /* Check if 82XX firmware is alive or not | |
4079 | * We may have arrived here from NEED_RESET | |
4080 | * detection only | |
4081 | */ | |
4082 | if (!ha->flags.isp82xx_fw_hung) { | |
4083 | for (i = 0; i < 2; i++) { | |
4084 | msleep(1000); | |
4085 | if (qla82xx_check_fw_alive(vha)) { | |
4086 | ha->flags.isp82xx_fw_hung = 1; | |
c8f6544e | 4087 | qla82xx_clear_pending_mbx(vha); |
7190575f GM |
4088 | break; |
4089 | } | |
4090 | } | |
4091 | } | |
7c3df132 SK |
4092 | ql_dbg(ql_dbg_init, vha, 0x00b0, |
4093 | "Entered %s fw_hung=%d.\n", | |
4094 | __func__, ha->flags.isp82xx_fw_hung); | |
7190575f GM |
4095 | |
4096 | /* Abort all commands gracefully if fw NOT hung */ | |
4097 | if (!ha->flags.isp82xx_fw_hung) { | |
4098 | int cnt, que; | |
4099 | srb_t *sp; | |
4100 | struct req_que *req; | |
4101 | ||
4102 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
4103 | for (que = 0; que < ha->max_req_queues; que++) { | |
4104 | req = ha->req_q_map[que]; | |
4105 | if (!req) | |
4106 | continue; | |
4107 | for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { | |
4108 | sp = req->outstanding_cmds[cnt]; | |
4109 | if (sp) { | |
4110 | if (!sp->ctx || | |
4111 | (sp->flags & SRB_FCP_CMND_DMA_VALID)) { | |
4112 | spin_unlock_irqrestore( | |
4113 | &ha->hardware_lock, flags); | |
4114 | if (ha->isp_ops->abort_command(sp)) { | |
7c3df132 SK |
4115 | ql_log(ql_log_info, vha, |
4116 | 0x00b1, | |
4117 | "mbx abort failed.\n"); | |
7190575f | 4118 | } else { |
7c3df132 SK |
4119 | ql_log(ql_log_info, vha, |
4120 | 0x00b2, | |
4121 | "mbx abort success.\n"); | |
7190575f GM |
4122 | } |
4123 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
4124 | } | |
4125 | } | |
4126 | } | |
4127 | } | |
4128 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
4129 | ||
4130 | /* Wait for pending cmds (physical and virtual) to complete */ | |
4131 | if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0, | |
4132 | WAIT_HOST) == QLA_SUCCESS) { | |
7c3df132 SK |
4133 | ql_dbg(ql_dbg_init, vha, 0x00b3, |
4134 | "Done wait for " | |
4135 | "pending commands.\n"); | |
7190575f GM |
4136 | } |
4137 | } | |
4138 | } | |
08de2844 GM |
4139 | |
4140 | /* Minidump related functions */ | |
4141 | int | |
4142 | qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag) | |
4143 | { | |
4144 | uint32_t off_value, rval = 0; | |
4145 | ||
4146 | WRT_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase), | |
4147 | (off & 0xFFFF0000)); | |
4148 | ||
4149 | /* Read back value to make sure write has gone through */ | |
4150 | RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); | |
4151 | off_value = (off & 0x0000FFFF); | |
4152 | ||
4153 | if (flag) | |
4154 | WRT_REG_DWORD((void *) | |
4155 | (off_value + CRB_INDIRECT_2M + ha->nx_pcibase), | |
4156 | data); | |
4157 | else | |
4158 | rval = RD_REG_DWORD((void *) | |
4159 | (off_value + CRB_INDIRECT_2M + ha->nx_pcibase)); | |
4160 | ||
4161 | return rval; | |
4162 | } | |
4163 | ||
4164 | static int | |
4165 | qla82xx_minidump_process_control(scsi_qla_host_t *vha, | |
4166 | qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) | |
4167 | { | |
4168 | struct qla_hw_data *ha = vha->hw; | |
4169 | struct qla82xx_md_entry_crb *crb_entry; | |
4170 | uint32_t read_value, opcode, poll_time; | |
4171 | uint32_t addr, index, crb_addr; | |
4172 | unsigned long wtime; | |
4173 | struct qla82xx_md_template_hdr *tmplt_hdr; | |
4174 | uint32_t rval = QLA_SUCCESS; | |
4175 | int i; | |
4176 | ||
4177 | tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; | |
4178 | crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr; | |
4179 | crb_addr = crb_entry->addr; | |
4180 | ||
4181 | for (i = 0; i < crb_entry->op_count; i++) { | |
4182 | opcode = crb_entry->crb_ctrl.opcode; | |
4183 | if (opcode & QLA82XX_DBG_OPCODE_WR) { | |
4184 | qla82xx_md_rw_32(ha, crb_addr, | |
4185 | crb_entry->value_1, 1); | |
4186 | opcode &= ~QLA82XX_DBG_OPCODE_WR; | |
4187 | } | |
4188 | ||
4189 | if (opcode & QLA82XX_DBG_OPCODE_RW) { | |
4190 | read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); | |
4191 | qla82xx_md_rw_32(ha, crb_addr, read_value, 1); | |
4192 | opcode &= ~QLA82XX_DBG_OPCODE_RW; | |
4193 | } | |
4194 | ||
4195 | if (opcode & QLA82XX_DBG_OPCODE_AND) { | |
4196 | read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); | |
4197 | read_value &= crb_entry->value_2; | |
4198 | opcode &= ~QLA82XX_DBG_OPCODE_AND; | |
4199 | if (opcode & QLA82XX_DBG_OPCODE_OR) { | |
4200 | read_value |= crb_entry->value_3; | |
4201 | opcode &= ~QLA82XX_DBG_OPCODE_OR; | |
4202 | } | |
4203 | qla82xx_md_rw_32(ha, crb_addr, read_value, 1); | |
4204 | } | |
4205 | ||
4206 | if (opcode & QLA82XX_DBG_OPCODE_OR) { | |
4207 | read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); | |
4208 | read_value |= crb_entry->value_3; | |
4209 | qla82xx_md_rw_32(ha, crb_addr, read_value, 1); | |
4210 | opcode &= ~QLA82XX_DBG_OPCODE_OR; | |
4211 | } | |
4212 | ||
4213 | if (opcode & QLA82XX_DBG_OPCODE_POLL) { | |
4214 | poll_time = crb_entry->crb_strd.poll_timeout; | |
4215 | wtime = jiffies + poll_time; | |
4216 | read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); | |
4217 | ||
4218 | do { | |
4219 | if ((read_value & crb_entry->value_2) | |
4220 | == crb_entry->value_1) | |
4221 | break; | |
4222 | else if (time_after_eq(jiffies, wtime)) { | |
4223 | /* capturing dump failed */ | |
4224 | rval = QLA_FUNCTION_FAILED; | |
4225 | break; | |
4226 | } else | |
4227 | read_value = qla82xx_md_rw_32(ha, | |
4228 | crb_addr, 0, 0); | |
4229 | } while (1); | |
4230 | opcode &= ~QLA82XX_DBG_OPCODE_POLL; | |
4231 | } | |
4232 | ||
4233 | if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { | |
4234 | if (crb_entry->crb_strd.state_index_a) { | |
4235 | index = crb_entry->crb_strd.state_index_a; | |
4236 | addr = tmplt_hdr->saved_state_array[index]; | |
4237 | } else | |
4238 | addr = crb_addr; | |
4239 | ||
4240 | read_value = qla82xx_md_rw_32(ha, addr, 0, 0); | |
4241 | index = crb_entry->crb_ctrl.state_index_v; | |
4242 | tmplt_hdr->saved_state_array[index] = read_value; | |
4243 | opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; | |
4244 | } | |
4245 | ||
4246 | if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { | |
4247 | if (crb_entry->crb_strd.state_index_a) { | |
4248 | index = crb_entry->crb_strd.state_index_a; | |
4249 | addr = tmplt_hdr->saved_state_array[index]; | |
4250 | } else | |
4251 | addr = crb_addr; | |
4252 | ||
4253 | if (crb_entry->crb_ctrl.state_index_v) { | |
4254 | index = crb_entry->crb_ctrl.state_index_v; | |
4255 | read_value = | |
4256 | tmplt_hdr->saved_state_array[index]; | |
4257 | } else | |
4258 | read_value = crb_entry->value_1; | |
4259 | ||
4260 | qla82xx_md_rw_32(ha, addr, read_value, 1); | |
4261 | opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; | |
4262 | } | |
4263 | ||
4264 | if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { | |
4265 | index = crb_entry->crb_ctrl.state_index_v; | |
4266 | read_value = tmplt_hdr->saved_state_array[index]; | |
4267 | read_value <<= crb_entry->crb_ctrl.shl; | |
4268 | read_value >>= crb_entry->crb_ctrl.shr; | |
4269 | if (crb_entry->value_2) | |
4270 | read_value &= crb_entry->value_2; | |
4271 | read_value |= crb_entry->value_3; | |
4272 | read_value += crb_entry->value_1; | |
4273 | tmplt_hdr->saved_state_array[index] = read_value; | |
4274 | opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; | |
4275 | } | |
4276 | crb_addr += crb_entry->crb_strd.addr_stride; | |
4277 | } | |
4278 | return rval; | |
4279 | } | |
4280 | ||
4281 | static void | |
4282 | qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha, | |
4283 | qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) | |
4284 | { | |
4285 | struct qla_hw_data *ha = vha->hw; | |
4286 | uint32_t r_addr, r_stride, loop_cnt, i, r_value; | |
4287 | struct qla82xx_md_entry_rdocm *ocm_hdr; | |
4288 | uint32_t *data_ptr = *d_ptr; | |
4289 | ||
4290 | ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr; | |
4291 | r_addr = ocm_hdr->read_addr; | |
4292 | r_stride = ocm_hdr->read_addr_stride; | |
4293 | loop_cnt = ocm_hdr->op_count; | |
4294 | ||
4295 | for (i = 0; i < loop_cnt; i++) { | |
4296 | r_value = RD_REG_DWORD((void *)(r_addr + ha->nx_pcibase)); | |
4297 | *data_ptr++ = cpu_to_le32(r_value); | |
4298 | r_addr += r_stride; | |
4299 | } | |
4300 | *d_ptr = data_ptr; | |
4301 | } | |
4302 | ||
4303 | static void | |
4304 | qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha, | |
4305 | qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) | |
4306 | { | |
4307 | struct qla_hw_data *ha = vha->hw; | |
4308 | uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; | |
4309 | struct qla82xx_md_entry_mux *mux_hdr; | |
4310 | uint32_t *data_ptr = *d_ptr; | |
4311 | ||
4312 | mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr; | |
4313 | r_addr = mux_hdr->read_addr; | |
4314 | s_addr = mux_hdr->select_addr; | |
4315 | s_stride = mux_hdr->select_value_stride; | |
4316 | s_value = mux_hdr->select_value; | |
4317 | loop_cnt = mux_hdr->op_count; | |
4318 | ||
4319 | for (i = 0; i < loop_cnt; i++) { | |
4320 | qla82xx_md_rw_32(ha, s_addr, s_value, 1); | |
4321 | r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); | |
4322 | *data_ptr++ = cpu_to_le32(s_value); | |
4323 | *data_ptr++ = cpu_to_le32(r_value); | |
4324 | s_value += s_stride; | |
4325 | } | |
4326 | *d_ptr = data_ptr; | |
4327 | } | |
4328 | ||
4329 | static void | |
4330 | qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha, | |
4331 | qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) | |
4332 | { | |
4333 | struct qla_hw_data *ha = vha->hw; | |
4334 | uint32_t r_addr, r_stride, loop_cnt, i, r_value; | |
4335 | struct qla82xx_md_entry_crb *crb_hdr; | |
4336 | uint32_t *data_ptr = *d_ptr; | |
4337 | ||
4338 | crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr; | |
4339 | r_addr = crb_hdr->addr; | |
4340 | r_stride = crb_hdr->crb_strd.addr_stride; | |
4341 | loop_cnt = crb_hdr->op_count; | |
4342 | ||
4343 | for (i = 0; i < loop_cnt; i++) { | |
4344 | r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); | |
4345 | *data_ptr++ = cpu_to_le32(r_addr); | |
4346 | *data_ptr++ = cpu_to_le32(r_value); | |
4347 | r_addr += r_stride; | |
4348 | } | |
4349 | *d_ptr = data_ptr; | |
4350 | } | |
4351 | ||
4352 | static int | |
4353 | qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha, | |
4354 | qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) | |
4355 | { | |
4356 | struct qla_hw_data *ha = vha->hw; | |
4357 | uint32_t addr, r_addr, c_addr, t_r_addr; | |
4358 | uint32_t i, k, loop_count, t_value, r_cnt, r_value; | |
4359 | unsigned long p_wait, w_time, p_mask; | |
4360 | uint32_t c_value_w, c_value_r; | |
4361 | struct qla82xx_md_entry_cache *cache_hdr; | |
4362 | int rval = QLA_FUNCTION_FAILED; | |
4363 | uint32_t *data_ptr = *d_ptr; | |
4364 | ||
4365 | cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; | |
4366 | loop_count = cache_hdr->op_count; | |
4367 | r_addr = cache_hdr->read_addr; | |
4368 | c_addr = cache_hdr->control_addr; | |
4369 | c_value_w = cache_hdr->cache_ctrl.write_value; | |
4370 | ||
4371 | t_r_addr = cache_hdr->tag_reg_addr; | |
4372 | t_value = cache_hdr->addr_ctrl.init_tag_value; | |
4373 | r_cnt = cache_hdr->read_ctrl.read_addr_cnt; | |
4374 | p_wait = cache_hdr->cache_ctrl.poll_wait; | |
4375 | p_mask = cache_hdr->cache_ctrl.poll_mask; | |
4376 | ||
4377 | for (i = 0; i < loop_count; i++) { | |
4378 | qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); | |
4379 | if (c_value_w) | |
4380 | qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); | |
4381 | ||
4382 | if (p_mask) { | |
4383 | w_time = jiffies + p_wait; | |
4384 | do { | |
4385 | c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); | |
4386 | if ((c_value_r & p_mask) == 0) | |
4387 | break; | |
4388 | else if (time_after_eq(jiffies, w_time)) { | |
4389 | /* capturing dump failed */ | |
4390 | ql_dbg(ql_dbg_p3p, vha, 0xb032, | |
4391 | "c_value_r: 0x%x, poll_mask: 0x%lx, " | |
4392 | "w_time: 0x%lx\n", | |
4393 | c_value_r, p_mask, w_time); | |
4394 | return rval; | |
4395 | } | |
4396 | } while (1); | |
4397 | } | |
4398 | ||
4399 | addr = r_addr; | |
4400 | for (k = 0; k < r_cnt; k++) { | |
4401 | r_value = qla82xx_md_rw_32(ha, addr, 0, 0); | |
4402 | *data_ptr++ = cpu_to_le32(r_value); | |
4403 | addr += cache_hdr->read_ctrl.read_addr_stride; | |
4404 | } | |
4405 | t_value += cache_hdr->addr_ctrl.tag_value_stride; | |
4406 | } | |
4407 | *d_ptr = data_ptr; | |
4408 | return QLA_SUCCESS; | |
4409 | } | |
4410 | ||
4411 | static void | |
4412 | qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha, | |
4413 | qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) | |
4414 | { | |
4415 | struct qla_hw_data *ha = vha->hw; | |
4416 | uint32_t addr, r_addr, c_addr, t_r_addr; | |
4417 | uint32_t i, k, loop_count, t_value, r_cnt, r_value; | |
4418 | uint32_t c_value_w; | |
4419 | struct qla82xx_md_entry_cache *cache_hdr; | |
4420 | uint32_t *data_ptr = *d_ptr; | |
4421 | ||
4422 | cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr; | |
4423 | loop_count = cache_hdr->op_count; | |
4424 | r_addr = cache_hdr->read_addr; | |
4425 | c_addr = cache_hdr->control_addr; | |
4426 | c_value_w = cache_hdr->cache_ctrl.write_value; | |
4427 | ||
4428 | t_r_addr = cache_hdr->tag_reg_addr; | |
4429 | t_value = cache_hdr->addr_ctrl.init_tag_value; | |
4430 | r_cnt = cache_hdr->read_ctrl.read_addr_cnt; | |
4431 | ||
4432 | for (i = 0; i < loop_count; i++) { | |
4433 | qla82xx_md_rw_32(ha, t_r_addr, t_value, 1); | |
4434 | qla82xx_md_rw_32(ha, c_addr, c_value_w, 1); | |
4435 | addr = r_addr; | |
4436 | for (k = 0; k < r_cnt; k++) { | |
4437 | r_value = qla82xx_md_rw_32(ha, addr, 0, 0); | |
4438 | *data_ptr++ = cpu_to_le32(r_value); | |
4439 | addr += cache_hdr->read_ctrl.read_addr_stride; | |
4440 | } | |
4441 | t_value += cache_hdr->addr_ctrl.tag_value_stride; | |
4442 | } | |
4443 | *d_ptr = data_ptr; | |
4444 | } | |
4445 | ||
4446 | static void | |
4447 | qla82xx_minidump_process_queue(scsi_qla_host_t *vha, | |
4448 | qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) | |
4449 | { | |
4450 | struct qla_hw_data *ha = vha->hw; | |
4451 | uint32_t s_addr, r_addr; | |
4452 | uint32_t r_stride, r_value, r_cnt, qid = 0; | |
4453 | uint32_t i, k, loop_cnt; | |
4454 | struct qla82xx_md_entry_queue *q_hdr; | |
4455 | uint32_t *data_ptr = *d_ptr; | |
4456 | ||
4457 | q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr; | |
4458 | s_addr = q_hdr->select_addr; | |
4459 | r_cnt = q_hdr->rd_strd.read_addr_cnt; | |
4460 | r_stride = q_hdr->rd_strd.read_addr_stride; | |
4461 | loop_cnt = q_hdr->op_count; | |
4462 | ||
4463 | for (i = 0; i < loop_cnt; i++) { | |
4464 | qla82xx_md_rw_32(ha, s_addr, qid, 1); | |
4465 | r_addr = q_hdr->read_addr; | |
4466 | for (k = 0; k < r_cnt; k++) { | |
4467 | r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); | |
4468 | *data_ptr++ = cpu_to_le32(r_value); | |
4469 | r_addr += r_stride; | |
4470 | } | |
4471 | qid += q_hdr->q_strd.queue_id_stride; | |
4472 | } | |
4473 | *d_ptr = data_ptr; | |
4474 | } | |
4475 | ||
4476 | static void | |
4477 | qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha, | |
4478 | qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) | |
4479 | { | |
4480 | struct qla_hw_data *ha = vha->hw; | |
4481 | uint32_t r_addr, r_value; | |
4482 | uint32_t i, loop_cnt; | |
4483 | struct qla82xx_md_entry_rdrom *rom_hdr; | |
4484 | uint32_t *data_ptr = *d_ptr; | |
4485 | ||
4486 | rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr; | |
4487 | r_addr = rom_hdr->read_addr; | |
4488 | loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); | |
4489 | ||
4490 | for (i = 0; i < loop_cnt; i++) { | |
4491 | qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, | |
4492 | (r_addr & 0xFFFF0000), 1); | |
4493 | r_value = qla82xx_md_rw_32(ha, | |
4494 | MD_DIRECT_ROM_READ_BASE + | |
4495 | (r_addr & 0x0000FFFF), 0, 0); | |
4496 | *data_ptr++ = cpu_to_le32(r_value); | |
4497 | r_addr += sizeof(uint32_t); | |
4498 | } | |
4499 | *d_ptr = data_ptr; | |
4500 | } | |
4501 | ||
4502 | static int | |
4503 | qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha, | |
4504 | qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr) | |
4505 | { | |
4506 | struct qla_hw_data *ha = vha->hw; | |
4507 | uint32_t r_addr, r_value, r_data; | |
4508 | uint32_t i, j, loop_cnt; | |
4509 | struct qla82xx_md_entry_rdmem *m_hdr; | |
4510 | unsigned long flags; | |
4511 | int rval = QLA_FUNCTION_FAILED; | |
4512 | uint32_t *data_ptr = *d_ptr; | |
4513 | ||
4514 | m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr; | |
4515 | r_addr = m_hdr->read_addr; | |
4516 | loop_cnt = m_hdr->read_data_size/16; | |
4517 | ||
4518 | if (r_addr & 0xf) { | |
4519 | ql_log(ql_log_warn, vha, 0xb033, | |
4520 | "Read addr 0x%x not 16 bytes alligned\n", r_addr); | |
4521 | return rval; | |
4522 | } | |
4523 | ||
4524 | if (m_hdr->read_data_size % 16) { | |
4525 | ql_log(ql_log_warn, vha, 0xb034, | |
4526 | "Read data[0x%x] not multiple of 16 bytes\n", | |
4527 | m_hdr->read_data_size); | |
4528 | return rval; | |
4529 | } | |
4530 | ||
4531 | ql_dbg(ql_dbg_p3p, vha, 0xb035, | |
4532 | "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", | |
4533 | __func__, r_addr, m_hdr->read_data_size, loop_cnt); | |
4534 | ||
4535 | write_lock_irqsave(&ha->hw_lock, flags); | |
4536 | for (i = 0; i < loop_cnt; i++) { | |
4537 | qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); | |
4538 | r_value = 0; | |
4539 | qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); | |
4540 | r_value = MIU_TA_CTL_ENABLE; | |
4541 | qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); | |
4542 | r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; | |
4543 | qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); | |
4544 | ||
4545 | for (j = 0; j < MAX_CTL_CHECK; j++) { | |
4546 | r_value = qla82xx_md_rw_32(ha, | |
4547 | MD_MIU_TEST_AGT_CTRL, 0, 0); | |
4548 | if ((r_value & MIU_TA_CTL_BUSY) == 0) | |
4549 | break; | |
4550 | } | |
4551 | ||
4552 | if (j >= MAX_CTL_CHECK) { | |
4553 | printk_ratelimited(KERN_ERR | |
4554 | "failed to read through agent\n"); | |
4555 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
4556 | return rval; | |
4557 | } | |
4558 | ||
4559 | for (j = 0; j < 4; j++) { | |
4560 | r_data = qla82xx_md_rw_32(ha, | |
4561 | MD_MIU_TEST_AGT_RDDATA[j], 0, 0); | |
4562 | *data_ptr++ = cpu_to_le32(r_data); | |
4563 | } | |
4564 | r_addr += 16; | |
4565 | } | |
4566 | write_unlock_irqrestore(&ha->hw_lock, flags); | |
4567 | *d_ptr = data_ptr; | |
4568 | return QLA_SUCCESS; | |
4569 | } | |
4570 | ||
4571 | static int | |
4572 | qla82xx_validate_template_chksum(scsi_qla_host_t *vha) | |
4573 | { | |
4574 | struct qla_hw_data *ha = vha->hw; | |
4575 | uint64_t chksum = 0; | |
4576 | uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr; | |
4577 | int count = ha->md_template_size/sizeof(uint32_t); | |
4578 | ||
4579 | while (count-- > 0) | |
4580 | chksum += *d_ptr++; | |
4581 | while (chksum >> 32) | |
4582 | chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); | |
4583 | return ~chksum; | |
4584 | } | |
4585 | ||
4586 | static void | |
4587 | qla82xx_mark_entry_skipped(scsi_qla_host_t *vha, | |
4588 | qla82xx_md_entry_hdr_t *entry_hdr, int index) | |
4589 | { | |
4590 | entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; | |
4591 | ql_dbg(ql_dbg_p3p, vha, 0xb036, | |
4592 | "Skipping entry[%d]: " | |
4593 | "ETYPE[0x%x]-ELEVEL[0x%x]\n", | |
4594 | index, entry_hdr->entry_type, | |
4595 | entry_hdr->d_ctrl.entry_capture_mask); | |
4596 | } | |
4597 | ||
4598 | int | |
4599 | qla82xx_md_collect(scsi_qla_host_t *vha) | |
4600 | { | |
4601 | struct qla_hw_data *ha = vha->hw; | |
4602 | int no_entry_hdr = 0; | |
4603 | qla82xx_md_entry_hdr_t *entry_hdr; | |
4604 | struct qla82xx_md_template_hdr *tmplt_hdr; | |
4605 | uint32_t *data_ptr; | |
4606 | uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; | |
4607 | int i = 0, rval = QLA_FUNCTION_FAILED; | |
4608 | ||
4609 | tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; | |
4610 | data_ptr = (uint32_t *)ha->md_dump; | |
4611 | ||
4612 | if (ha->fw_dumped) { | |
4613 | ql_log(ql_log_info, vha, 0xb037, | |
4614 | "Firmware dump available to retrive\n"); | |
4615 | goto md_failed; | |
4616 | } | |
4617 | ||
4618 | ha->fw_dumped = 0; | |
4619 | ||
4620 | if (!ha->md_tmplt_hdr || !ha->md_dump) { | |
4621 | ql_log(ql_log_warn, vha, 0xb038, | |
4622 | "Memory not allocated for minidump capture\n"); | |
4623 | goto md_failed; | |
4624 | } | |
4625 | ||
4626 | if (qla82xx_validate_template_chksum(vha)) { | |
4627 | ql_log(ql_log_info, vha, 0xb039, | |
4628 | "Template checksum validation error\n"); | |
4629 | goto md_failed; | |
4630 | } | |
4631 | ||
4632 | no_entry_hdr = tmplt_hdr->num_of_entries; | |
4633 | ql_dbg(ql_dbg_p3p, vha, 0xb03a, | |
4634 | "No of entry headers in Template: 0x%x\n", no_entry_hdr); | |
4635 | ||
4636 | ql_dbg(ql_dbg_p3p, vha, 0xb03b, | |
4637 | "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); | |
4638 | ||
4639 | f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; | |
4640 | ||
4641 | /* Validate whether required debug level is set */ | |
4642 | if ((f_capture_mask & 0x3) != 0x3) { | |
4643 | ql_log(ql_log_warn, vha, 0xb03c, | |
4644 | "Minimum required capture mask[0x%x] level not set\n", | |
4645 | f_capture_mask); | |
4646 | goto md_failed; | |
4647 | } | |
4648 | tmplt_hdr->driver_capture_mask = ql2xmdcapmask; | |
4649 | ||
4650 | tmplt_hdr->driver_info[0] = vha->host_no; | |
4651 | tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) | | |
4652 | (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) | | |
4653 | QLA_DRIVER_BETA_VER; | |
4654 | ||
4655 | total_data_size = ha->md_dump_size; | |
4656 | ||
4657 | ql_dbg(ql_log_info, vha, 0xb03d, | |
4658 | "Total minidump data_size 0x%x to be captured\n", total_data_size); | |
4659 | ||
4660 | /* Check whether template obtained is valid */ | |
4661 | if (tmplt_hdr->entry_type != QLA82XX_TLHDR) { | |
4662 | ql_log(ql_log_warn, vha, 0xb04e, | |
4663 | "Bad template header entry type: 0x%x obtained\n", | |
4664 | tmplt_hdr->entry_type); | |
4665 | goto md_failed; | |
4666 | } | |
4667 | ||
4668 | entry_hdr = (qla82xx_md_entry_hdr_t *) \ | |
4669 | (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); | |
4670 | ||
4671 | /* Walk through the entry headers */ | |
4672 | for (i = 0; i < no_entry_hdr; i++) { | |
4673 | ||
4674 | if (data_collected > total_data_size) { | |
4675 | ql_log(ql_log_warn, vha, 0xb03e, | |
4676 | "More MiniDump data collected: [0x%x]\n", | |
4677 | data_collected); | |
4678 | goto md_failed; | |
4679 | } | |
4680 | ||
4681 | if (!(entry_hdr->d_ctrl.entry_capture_mask & | |
4682 | ql2xmdcapmask)) { | |
4683 | entry_hdr->d_ctrl.driver_flags |= | |
4684 | QLA82XX_DBG_SKIPPED_FLAG; | |
4685 | ql_dbg(ql_dbg_p3p, vha, 0xb03f, | |
4686 | "Skipping entry[%d]: " | |
4687 | "ETYPE[0x%x]-ELEVEL[0x%x]\n", | |
4688 | i, entry_hdr->entry_type, | |
4689 | entry_hdr->d_ctrl.entry_capture_mask); | |
4690 | goto skip_nxt_entry; | |
4691 | } | |
4692 | ||
4693 | ql_dbg(ql_dbg_p3p, vha, 0xb040, | |
4694 | "[%s]: data ptr[%d]: %p, entry_hdr: %p\n" | |
4695 | "entry_type: 0x%x, captrue_mask: 0x%x\n", | |
4696 | __func__, i, data_ptr, entry_hdr, | |
4697 | entry_hdr->entry_type, | |
4698 | entry_hdr->d_ctrl.entry_capture_mask); | |
4699 | ||
4700 | ql_dbg(ql_dbg_p3p, vha, 0xb041, | |
4701 | "Data collected: [0x%x], Dump size left:[0x%x]\n", | |
4702 | data_collected, (ha->md_dump_size - data_collected)); | |
4703 | ||
4704 | /* Decode the entry type and take | |
4705 | * required action to capture debug data */ | |
4706 | switch (entry_hdr->entry_type) { | |
4707 | case QLA82XX_RDEND: | |
4708 | qla82xx_mark_entry_skipped(vha, entry_hdr, i); | |
4709 | break; | |
4710 | case QLA82XX_CNTRL: | |
4711 | rval = qla82xx_minidump_process_control(vha, | |
4712 | entry_hdr, &data_ptr); | |
4713 | if (rval != QLA_SUCCESS) { | |
4714 | qla82xx_mark_entry_skipped(vha, entry_hdr, i); | |
4715 | goto md_failed; | |
4716 | } | |
4717 | break; | |
4718 | case QLA82XX_RDCRB: | |
4719 | qla82xx_minidump_process_rdcrb(vha, | |
4720 | entry_hdr, &data_ptr); | |
4721 | break; | |
4722 | case QLA82XX_RDMEM: | |
4723 | rval = qla82xx_minidump_process_rdmem(vha, | |
4724 | entry_hdr, &data_ptr); | |
4725 | if (rval != QLA_SUCCESS) { | |
4726 | qla82xx_mark_entry_skipped(vha, entry_hdr, i); | |
4727 | goto md_failed; | |
4728 | } | |
4729 | break; | |
4730 | case QLA82XX_BOARD: | |
4731 | case QLA82XX_RDROM: | |
4732 | qla82xx_minidump_process_rdrom(vha, | |
4733 | entry_hdr, &data_ptr); | |
4734 | break; | |
4735 | case QLA82XX_L2DTG: | |
4736 | case QLA82XX_L2ITG: | |
4737 | case QLA82XX_L2DAT: | |
4738 | case QLA82XX_L2INS: | |
4739 | rval = qla82xx_minidump_process_l2tag(vha, | |
4740 | entry_hdr, &data_ptr); | |
4741 | if (rval != QLA_SUCCESS) { | |
4742 | qla82xx_mark_entry_skipped(vha, entry_hdr, i); | |
4743 | goto md_failed; | |
4744 | } | |
4745 | break; | |
4746 | case QLA82XX_L1DAT: | |
4747 | case QLA82XX_L1INS: | |
4748 | qla82xx_minidump_process_l1cache(vha, | |
4749 | entry_hdr, &data_ptr); | |
4750 | break; | |
4751 | case QLA82XX_RDOCM: | |
4752 | qla82xx_minidump_process_rdocm(vha, | |
4753 | entry_hdr, &data_ptr); | |
4754 | break; | |
4755 | case QLA82XX_RDMUX: | |
4756 | qla82xx_minidump_process_rdmux(vha, | |
4757 | entry_hdr, &data_ptr); | |
4758 | break; | |
4759 | case QLA82XX_QUEUE: | |
4760 | qla82xx_minidump_process_queue(vha, | |
4761 | entry_hdr, &data_ptr); | |
4762 | break; | |
4763 | case QLA82XX_RDNOP: | |
4764 | default: | |
4765 | qla82xx_mark_entry_skipped(vha, entry_hdr, i); | |
4766 | break; | |
4767 | } | |
4768 | ||
4769 | ql_dbg(ql_dbg_p3p, vha, 0xb042, | |
4770 | "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr); | |
4771 | ||
4772 | data_collected = (uint8_t *)data_ptr - | |
4773 | (uint8_t *)ha->md_dump; | |
4774 | skip_nxt_entry: | |
4775 | entry_hdr = (qla82xx_md_entry_hdr_t *) \ | |
4776 | (((uint8_t *)entry_hdr) + entry_hdr->entry_size); | |
4777 | } | |
4778 | ||
4779 | if (data_collected != total_data_size) { | |
4780 | ql_dbg(ql_log_warn, vha, 0xb043, | |
4781 | "MiniDump data mismatch: Data collected: [0x%x]," | |
4782 | "total_data_size:[0x%x]\n", | |
4783 | data_collected, total_data_size); | |
4784 | goto md_failed; | |
4785 | } | |
4786 | ||
4787 | ql_log(ql_log_info, vha, 0xb044, | |
4788 | "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", | |
4789 | vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); | |
4790 | ha->fw_dumped = 1; | |
4791 | qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); | |
4792 | ||
4793 | md_failed: | |
4794 | return rval; | |
4795 | } | |
4796 | ||
4797 | int | |
4798 | qla82xx_md_alloc(scsi_qla_host_t *vha) | |
4799 | { | |
4800 | struct qla_hw_data *ha = vha->hw; | |
4801 | int i, k; | |
4802 | struct qla82xx_md_template_hdr *tmplt_hdr; | |
4803 | ||
4804 | tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr; | |
4805 | ||
4806 | if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { | |
4807 | ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; | |
4808 | ql_log(ql_log_info, vha, 0xb045, | |
4809 | "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", | |
4810 | ql2xmdcapmask); | |
4811 | } | |
4812 | ||
4813 | for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { | |
4814 | if (i & ql2xmdcapmask) | |
4815 | ha->md_dump_size += tmplt_hdr->capture_size_array[k]; | |
4816 | } | |
4817 | ||
4818 | if (ha->md_dump) { | |
4819 | ql_log(ql_log_warn, vha, 0xb046, | |
4820 | "Firmware dump previously allocated.\n"); | |
4821 | return 1; | |
4822 | } | |
4823 | ||
4824 | ha->md_dump = vmalloc(ha->md_dump_size); | |
4825 | if (ha->md_dump == NULL) { | |
4826 | ql_log(ql_log_warn, vha, 0xb047, | |
4827 | "Unable to allocate memory for Minidump size " | |
4828 | "(0x%x).\n", ha->md_dump_size); | |
4829 | return 1; | |
4830 | } | |
4831 | return 0; | |
4832 | } | |
4833 | ||
4834 | void | |
4835 | qla82xx_md_free(scsi_qla_host_t *vha) | |
4836 | { | |
4837 | struct qla_hw_data *ha = vha->hw; | |
4838 | ||
4839 | /* Release the template header allocated */ | |
4840 | if (ha->md_tmplt_hdr) { | |
4841 | ql_log(ql_log_info, vha, 0xb048, | |
4842 | "Free MiniDump template: %p, size (%d KB)\n", | |
4843 | ha->md_tmplt_hdr, ha->md_template_size / 1024); | |
4844 | dma_free_coherent(&ha->pdev->dev, ha->md_template_size, | |
4845 | ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); | |
4846 | ha->md_tmplt_hdr = 0; | |
4847 | } | |
4848 | ||
4849 | /* Release the template data buffer allocated */ | |
4850 | if (ha->md_dump) { | |
4851 | ql_log(ql_log_info, vha, 0xb049, | |
4852 | "Free MiniDump memory: %p, size (%d KB)\n", | |
4853 | ha->md_dump, ha->md_dump_size / 1024); | |
4854 | vfree(ha->md_dump); | |
4855 | ha->md_dump_size = 0; | |
4856 | ha->md_dump = 0; | |
4857 | } | |
4858 | } | |
4859 | ||
4860 | void | |
4861 | qla82xx_md_prep(scsi_qla_host_t *vha) | |
4862 | { | |
4863 | struct qla_hw_data *ha = vha->hw; | |
4864 | int rval; | |
4865 | ||
4866 | /* Get Minidump template size */ | |
4867 | rval = qla82xx_md_get_template_size(vha); | |
4868 | if (rval == QLA_SUCCESS) { | |
4869 | ql_log(ql_log_info, vha, 0xb04a, | |
4870 | "MiniDump Template size obtained (%d KB)\n", | |
4871 | ha->md_template_size / 1024); | |
4872 | ||
4873 | /* Get Minidump template */ | |
4874 | rval = qla82xx_md_get_template(vha); | |
4875 | if (rval == QLA_SUCCESS) { | |
4876 | ql_dbg(ql_dbg_p3p, vha, 0xb04b, | |
4877 | "MiniDump Template obtained\n"); | |
4878 | ||
4879 | /* Allocate memory for minidump */ | |
4880 | rval = qla82xx_md_alloc(vha); | |
4881 | if (rval == QLA_SUCCESS) | |
4882 | ql_log(ql_log_info, vha, 0xb04c, | |
4883 | "MiniDump memory allocated (%d KB)\n", | |
4884 | ha->md_dump_size / 1024); | |
4885 | else { | |
4886 | ql_log(ql_log_info, vha, 0xb04d, | |
4887 | "Free MiniDump template: %p, size: (%d KB)\n", | |
4888 | ha->md_tmplt_hdr, | |
4889 | ha->md_template_size / 1024); | |
4890 | dma_free_coherent(&ha->pdev->dev, | |
4891 | ha->md_template_size, | |
4892 | ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma); | |
4893 | ha->md_tmplt_hdr = 0; | |
4894 | } | |
4895 | ||
4896 | } | |
4897 | } | |
4898 | } | |
999916dc SK |
4899 | |
4900 | int | |
4901 | qla82xx_beacon_on(struct scsi_qla_host *vha) | |
4902 | { | |
4903 | ||
4904 | int rval; | |
4905 | struct qla_hw_data *ha = vha->hw; | |
4906 | qla82xx_idc_lock(ha); | |
4907 | rval = qla82xx_mbx_beacon_ctl(vha, 1); | |
4908 | ||
4909 | if (rval) { | |
4910 | ql_log(ql_log_warn, vha, 0xb050, | |
4911 | "mbx set led config failed in %s\n", __func__); | |
4912 | goto exit; | |
4913 | } | |
4914 | ha->beacon_blink_led = 1; | |
4915 | exit: | |
4916 | qla82xx_idc_unlock(ha); | |
4917 | return rval; | |
4918 | } | |
4919 | ||
4920 | int | |
4921 | qla82xx_beacon_off(struct scsi_qla_host *vha) | |
4922 | { | |
4923 | ||
4924 | int rval; | |
4925 | struct qla_hw_data *ha = vha->hw; | |
4926 | qla82xx_idc_lock(ha); | |
4927 | rval = qla82xx_mbx_beacon_ctl(vha, 0); | |
4928 | ||
4929 | if (rval) { | |
4930 | ql_log(ql_log_warn, vha, 0xb051, | |
4931 | "mbx set led config failed in %s\n", __func__); | |
4932 | goto exit; | |
4933 | } | |
4934 | ha->beacon_blink_led = 0; | |
4935 | exit: | |
4936 | qla82xx_idc_unlock(ha); | |
4937 | return rval; | |
4938 | } |