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scsi: use 64-bit LUNs
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_mr.c
CommitLineData
8ae6d9c7
GM		 1/*
2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
8ae6d9c7
GM		 4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7#include "qla_def.h"
8#include <linux/delay.h>
9#include <linux/pci.h>
10#include <linux/ratelimit.h>
11#include <linux/vmalloc.h>
12#include <scsi/scsi_tcq.h>
13#include <linux/utsname.h>
14
15
16/* QLAFX00 specific Mailbox implementation functions */
17
18/*
19 * qlafx00_mailbox_command
20 * Issue mailbox command and waits for completion.
21 *
22 * Input:
23 * ha = adapter block pointer.
24 * mcp = driver internal mbx struct pointer.
25 *
26 * Output:
27 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
28 *
29 * Returns:
30 * 0 : QLA_SUCCESS = cmd performed success
31 * 1 : QLA_FUNCTION_FAILED (error encountered)
32 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
33 *
34 * Context:
35 * Kernel context.
36 */
37static int
38qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp)
39
40{
41 int rval;
42 unsigned long flags = 0;
f73cb695 43 device_reg_t *reg;
8ae6d9c7
GM		 44 uint8_t abort_active;
45 uint8_t io_lock_on;
46 uint16_t command = 0;
47 uint32_t *iptr;
48 uint32_t __iomem *optr;
49 uint32_t cnt;
50 uint32_t mboxes;
51 unsigned long wait_time;
52 struct qla_hw_data *ha = vha->hw;
53 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
54
55 if (ha->pdev->error_state > pci_channel_io_frozen) {
56 ql_log(ql_log_warn, vha, 0x115c,
57 "error_state is greater than pci_channel_io_frozen, "
58 "exiting.\n");
59 return QLA_FUNCTION_TIMEOUT;
60 }
61
62 if (vha->device_flags & DFLG_DEV_FAILED) {
63 ql_log(ql_log_warn, vha, 0x115f,
64 "Device in failed state, exiting.\n");
65 return QLA_FUNCTION_TIMEOUT;
66 }
67
68 reg = ha->iobase;
69 io_lock_on = base_vha->flags.init_done;
70
71 rval = QLA_SUCCESS;
72 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
73
74 if (ha->flags.pci_channel_io_perm_failure) {
75 ql_log(ql_log_warn, vha, 0x1175,
76 "Perm failure on EEH timeout MBX, exiting.\n");
77 return QLA_FUNCTION_TIMEOUT;
78 }
79
80 if (ha->flags.isp82xx_fw_hung) {
81 /* Setting Link-Down error */
82 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
83 ql_log(ql_log_warn, vha, 0x1176,
84 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
85 rval = QLA_FUNCTION_FAILED;
86 goto premature_exit;
87 }
88
89 /*
90 * Wait for active mailbox commands to finish by waiting at most tov
91 * seconds. This is to serialize actual issuing of mailbox cmds during
92 * non ISP abort time.
93 */
94 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
95 /* Timeout occurred. Return error. */
96 ql_log(ql_log_warn, vha, 0x1177,
97 "Cmd access timeout, cmd=0x%x, Exiting.\n",
98 mcp->mb[0]);
99 return QLA_FUNCTION_TIMEOUT;
100 }
101
102 ha->flags.mbox_busy = 1;
103 /* Save mailbox command for debug */
104 ha->mcp32 = mcp;
105
106 ql_dbg(ql_dbg_mbx, vha, 0x1178,
107 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
108
109 spin_lock_irqsave(&ha->hardware_lock, flags);
110
111 /* Load mailbox registers. */
112 optr = (uint32_t __iomem *)&reg->ispfx00.mailbox0;
113
114 iptr = mcp->mb;
115 command = mcp->mb[0];
116 mboxes = mcp->out_mb;
117
118 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
119 if (mboxes & BIT_0)
120 WRT_REG_DWORD(optr, *iptr);
121
122 mboxes >>= 1;
123 optr++;
124 iptr++;
125 }
126
127 /* Issue set host interrupt command to send cmd out. */
128 ha->flags.mbox_int = 0;
129 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
130
131 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172,
132 (uint8_t *)mcp->mb, 16);
133 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173,
134 ((uint8_t *)mcp->mb + 0x10), 16);
135 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174,
136 ((uint8_t *)mcp->mb + 0x20), 8);
137
138 /* Unlock mbx registers and wait for interrupt */
139 ql_dbg(ql_dbg_mbx, vha, 0x1179,
140 "Going to unlock irq & waiting for interrupts. "
141 "jiffies=%lx.\n", jiffies);
142
143 /* Wait for mbx cmd completion until timeout */
144 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
145 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
146
147 QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
148 spin_unlock_irqrestore(&ha->hardware_lock, flags);
149
150 wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
8ae6d9c7
GM		 151 } else {
152 ql_dbg(ql_dbg_mbx, vha, 0x112c,
153 "Cmd=%x Polling Mode.\n", command);
154
155 QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
156 spin_unlock_irqrestore(&ha->hardware_lock, flags);
157
158 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
159 while (!ha->flags.mbox_int) {
160 if (time_after(jiffies, wait_time))
161 break;
162
163 /* Check for pending interrupts. */
164 qla2x00_poll(ha->rsp_q_map[0]);
165
166 if (!ha->flags.mbox_int &&
167 !(IS_QLA2200(ha) &&
168 command == MBC_LOAD_RISC_RAM_EXTENDED))
169 usleep_range(10000, 11000);
170 } /* while */
171 ql_dbg(ql_dbg_mbx, vha, 0x112d,
172 "Waited %d sec.\n",
173 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
174 }
175
176 /* Check whether we timed out */
177 if (ha->flags.mbox_int) {
178 uint32_t *iptr2;
179
180 ql_dbg(ql_dbg_mbx, vha, 0x112e,
181 "Cmd=%x completed.\n", command);
182
183 /* Got interrupt. Clear the flag. */
184 ha->flags.mbox_int = 0;
185 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
186
187 if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE)
188 rval = QLA_FUNCTION_FAILED;
189
190 /* Load return mailbox registers. */
191 iptr2 = mcp->mb;
192 iptr = (uint32_t *)&ha->mailbox_out32[0];
193 mboxes = mcp->in_mb;
194 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
195 if (mboxes & BIT_0)
196 *iptr2 = *iptr;
197
198 mboxes >>= 1;
199 iptr2++;
200 iptr++;
201 }
202 } else {
203
204 rval = QLA_FUNCTION_TIMEOUT;
205 }
206
207 ha->flags.mbox_busy = 0;
208
209 /* Clean up */
210 ha->mcp32 = NULL;
211
212 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
213 ql_dbg(ql_dbg_mbx, vha, 0x113a,
214 "checking for additional resp interrupt.\n");
215
216 /* polling mode for non isp_abort commands. */
217 qla2x00_poll(ha->rsp_q_map[0]);
218 }
219
220 if (rval == QLA_FUNCTION_TIMEOUT &&
221 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
222 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
223 ha->flags.eeh_busy) {
224 /* not in dpc. schedule it for dpc to take over. */
225 ql_dbg(ql_dbg_mbx, vha, 0x115d,
226 "Timeout, schedule isp_abort_needed.\n");
227
228 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
229 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
230 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
231
232 ql_log(ql_log_info, base_vha, 0x115e,
233 "Mailbox cmd timeout occurred, cmd=0x%x, "
234 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
235 "abort.\n", command, mcp->mb[0],
236 ha->flags.eeh_busy);
237 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
238 qla2xxx_wake_dpc(vha);
239 }
240 } else if (!abort_active) {
241 /* call abort directly since we are in the DPC thread */
242 ql_dbg(ql_dbg_mbx, vha, 0x1160,
243 "Timeout, calling abort_isp.\n");
244
245 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
246 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
247 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
248
249 ql_log(ql_log_info, base_vha, 0x1161,
250 "Mailbox cmd timeout occurred, cmd=0x%x, "
251 "mb[0]=0x%x. Scheduling ISP abort ",
252 command, mcp->mb[0]);
253
254 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
255 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
256 if (ha->isp_ops->abort_isp(vha)) {
257 /* Failed. retry later. */
258 set_bit(ISP_ABORT_NEEDED,
259 &vha->dpc_flags);
260 }
261 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
262 ql_dbg(ql_dbg_mbx, vha, 0x1162,
263 "Finished abort_isp.\n");
264 }
265 }
266 }
267
268premature_exit:
269 /* Allow next mbx cmd to come in. */
270 complete(&ha->mbx_cmd_comp);
271
272 if (rval) {
273 ql_log(ql_log_warn, base_vha, 0x1163,
274 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, "
275 "mb[3]=%x, cmd=%x ****.\n",
276 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
277 } else {
278 ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__);
279 }
280
281 return rval;
282}
283
284/*
285 * qlafx00_driver_shutdown
286 * Indicate a driver shutdown to firmware.
287 *
288 * Input:
289 * ha = adapter block pointer.
290 *
291 * Returns:
292 * local function return status code.
293 *
294 * Context:
295 * Kernel context.
296 */
42479343 297int
8ae6d9c7
GM		 298qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo)
299{
300 int rval;
301 struct mbx_cmd_32 mc;
302 struct mbx_cmd_32 *mcp = &mc;
303
304 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166,
305 "Entered %s.\n", __func__);
306
307 mcp->mb[0] = MBC_MR_DRV_SHUTDOWN;
308 mcp->out_mb = MBX_0;
309 mcp->in_mb = MBX_0;
310 if (tmo)
311 mcp->tov = tmo;
312 else
313 mcp->tov = MBX_TOV_SECONDS;
314 mcp->flags = 0;
315 rval = qlafx00_mailbox_command(vha, mcp);
316
317 if (rval != QLA_SUCCESS) {
318 ql_dbg(ql_dbg_mbx, vha, 0x1167,
319 "Failed=%x.\n", rval);
320 } else {
321 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168,
322 "Done %s.\n", __func__);
323 }
324
325 return rval;
326}
327
328/*
329 * qlafx00_get_firmware_state
330 * Get adapter firmware state.
331 *
332 * Input:
333 * ha = adapter block pointer.
334 * TARGET_QUEUE_LOCK must be released.
335 * ADAPTER_STATE_LOCK must be released.
336 *
337 * Returns:
338 * qla7xxx local function return status code.
339 *
340 * Context:
341 * Kernel context.
342 */
343static int
344qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states)
345{
346 int rval;
347 struct mbx_cmd_32 mc;
348 struct mbx_cmd_32 *mcp = &mc;
349
350 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169,
351 "Entered %s.\n", __func__);
352
353 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
354 mcp->out_mb = MBX_0;
355 mcp->in_mb = MBX_1|MBX_0;
356 mcp->tov = MBX_TOV_SECONDS;
357 mcp->flags = 0;
358 rval = qlafx00_mailbox_command(vha, mcp);
359
360 /* Return firmware states. */
361 states[0] = mcp->mb[1];
362
363 if (rval != QLA_SUCCESS) {
364 ql_dbg(ql_dbg_mbx, vha, 0x116a,
365 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
366 } else {
367 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b,
368 "Done %s.\n", __func__);
369 }
370 return rval;
371}
372
373/*
374 * qlafx00_init_firmware
375 * Initialize adapter firmware.
376 *
377 * Input:
378 * ha = adapter block pointer.
379 * dptr = Initialization control block pointer.
380 * size = size of initialization control block.
381 * TARGET_QUEUE_LOCK must be released.
382 * ADAPTER_STATE_LOCK must be released.
383 *
384 * Returns:
385 * qlafx00 local function return status code.
386 *
387 * Context:
388 * Kernel context.
389 */
390int
391qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
392{
393 int rval;
394 struct mbx_cmd_32 mc;
395 struct mbx_cmd_32 *mcp = &mc;
396 struct qla_hw_data *ha = vha->hw;
397
398 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c,
399 "Entered %s.\n", __func__);
400
401 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
402
403 mcp->mb[1] = 0;
404 mcp->mb[2] = MSD(ha->init_cb_dma);
405 mcp->mb[3] = LSD(ha->init_cb_dma);
406
407 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
408 mcp->in_mb = MBX_0;
409 mcp->buf_size = size;
410 mcp->flags = MBX_DMA_OUT;
411 mcp->tov = MBX_TOV_SECONDS;
412 rval = qlafx00_mailbox_command(vha, mcp);
413
414 if (rval != QLA_SUCCESS) {
415 ql_dbg(ql_dbg_mbx, vha, 0x116d,
416 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
417 } else {
418 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e,
419 "Done %s.\n", __func__);
420 }
421 return rval;
422}
423
424/*
425 * qlafx00_mbx_reg_test
426 */
427static int
428qlafx00_mbx_reg_test(scsi_qla_host_t *vha)
429{
430 int rval;
431 struct mbx_cmd_32 mc;
432 struct mbx_cmd_32 *mcp = &mc;
433
434 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f,
435 "Entered %s.\n", __func__);
436
437
438 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
439 mcp->mb[1] = 0xAAAA;
440 mcp->mb[2] = 0x5555;
441 mcp->mb[3] = 0xAA55;
442 mcp->mb[4] = 0x55AA;
443 mcp->mb[5] = 0xA5A5;
444 mcp->mb[6] = 0x5A5A;
445 mcp->mb[7] = 0x2525;
446 mcp->mb[8] = 0xBBBB;
447 mcp->mb[9] = 0x6666;
448 mcp->mb[10] = 0xBB66;
449 mcp->mb[11] = 0x66BB;
450 mcp->mb[12] = 0xB6B6;
451 mcp->mb[13] = 0x6B6B;
452 mcp->mb[14] = 0x3636;
453 mcp->mb[15] = 0xCCCC;
454
455
456 mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
457 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
458 mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
459 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
460 mcp->buf_size = 0;
461 mcp->flags = MBX_DMA_OUT;
462 mcp->tov = MBX_TOV_SECONDS;
463 rval = qlafx00_mailbox_command(vha, mcp);
464 if (rval == QLA_SUCCESS) {
465 if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 ||
466 mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA)
467 rval = QLA_FUNCTION_FAILED;
468 if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A ||
469 mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB)
470 rval = QLA_FUNCTION_FAILED;
471 if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 ||
472 mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6)
473 rval = QLA_FUNCTION_FAILED;
474 if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 ||
475 mcp->mb[31] != 0xCCCC)
476 rval = QLA_FUNCTION_FAILED;
477 }
478
479 if (rval != QLA_SUCCESS) {
480 ql_dbg(ql_dbg_mbx, vha, 0x1170,
481 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
482 } else {
483 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171,
484 "Done %s.\n", __func__);
485 }
486 return rval;
487}
488
489/**
490 * qlafx00_pci_config() - Setup ISPFx00 PCI configuration registers.
491 * @ha: HA context
492 *
493 * Returns 0 on success.
494 */
495int
496qlafx00_pci_config(scsi_qla_host_t *vha)
497{
498 uint16_t w;
499 struct qla_hw_data *ha = vha->hw;
500
501 pci_set_master(ha->pdev);
502 pci_try_set_mwi(ha->pdev);
503
504 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
505 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
506 w &= ~PCI_COMMAND_INTX_DISABLE;
507 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
508
509 /* PCIe -- adjust Maximum Read Request Size (2048). */
ce9f7ed9 510 if (pci_is_pcie(ha->pdev))
8ae6d9c7
GM		 511 pcie_set_readrq(ha->pdev, 2048);
512
513 ha->chip_revision = ha->pdev->revision;
514
515 return QLA_SUCCESS;
516}
517
518/**
519 * qlafx00_warm_reset() - Perform warm reset of iSA(CPUs being reset on SOC).
520 * @ha: HA context
521 *
522 */
523static inline void
524qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
525{
526 unsigned long flags = 0;
527 struct qla_hw_data *ha = vha->hw;
528 int i, core;
529 uint32_t cnt;
42543fb9
AB		 530 uint32_t reg_val;
531
532 spin_lock_irqsave(&ha->hardware_lock, flags);
533
534 QLAFX00_SET_HBA_SOC_REG(ha, 0x80004, 0);
535 QLAFX00_SET_HBA_SOC_REG(ha, 0x82004, 0);
536
537 /* stop the XOR DMA engines */
538 QLAFX00_SET_HBA_SOC_REG(ha, 0x60920, 0x02);
539 QLAFX00_SET_HBA_SOC_REG(ha, 0x60924, 0x02);
540 QLAFX00_SET_HBA_SOC_REG(ha, 0xf0920, 0x02);
541 QLAFX00_SET_HBA_SOC_REG(ha, 0xf0924, 0x02);
542
543 /* stop the IDMA engines */
544 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60840);
545 reg_val &= ~(1<<12);
546 QLAFX00_SET_HBA_SOC_REG(ha, 0x60840, reg_val);
547
548 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60844);
549 reg_val &= ~(1<<12);
550 QLAFX00_SET_HBA_SOC_REG(ha, 0x60844, reg_val);
551
552 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60848);
553 reg_val &= ~(1<<12);
554 QLAFX00_SET_HBA_SOC_REG(ha, 0x60848, reg_val);
555
556 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x6084C);
557 reg_val &= ~(1<<12);
558 QLAFX00_SET_HBA_SOC_REG(ha, 0x6084C, reg_val);
559
560 for (i = 0; i < 100000; i++) {
561 if ((QLAFX00_GET_HBA_SOC_REG(ha, 0xd0000) & 0x10000000) == 0 &&
562 (QLAFX00_GET_HBA_SOC_REG(ha, 0x10600) & 0x1) == 0)
563 break;
564 udelay(100);
565 }
8ae6d9c7
GM		 566
567 /* Set all 4 cores in reset */
568 for (i = 0; i < 4; i++) {
569 QLAFX00_SET_HBA_SOC_REG(ha,
570 (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01));
8ae6d9c7
GM		 571 QLAFX00_SET_HBA_SOC_REG(ha,
572 (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101));
573 }
574
575 /* Reset all units in Fabric */
42543fb9
AB		 576 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x011f0101));
577
578 /* */
579 QLAFX00_SET_HBA_SOC_REG(ha, 0x10610, 1);
580 QLAFX00_SET_HBA_SOC_REG(ha, 0x10600, 0);
581
582 /* Set all 4 core Memory Power Down Registers */
583 for (i = 0; i < 5; i++) {
584 QLAFX00_SET_HBA_SOC_REG(ha,
585 (SOC_PWR_MANAGEMENT_PWR_DOWN_REG + 4*i), (0x0));
586 }
8ae6d9c7
GM		 587
588 /* Reset all interrupt control registers */
589 for (i = 0; i < 115; i++) {
590 QLAFX00_SET_HBA_SOC_REG(ha,
591 (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0));
592 }
593
594 /* Reset Timers control registers. per core */
595 for (core = 0; core < 4; core++)
596 for (i = 0; i < 8; i++)
597 QLAFX00_SET_HBA_SOC_REG(ha,
598 (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0));
599
600 /* Reset per core IRQ ack register */
601 for (core = 0; core < 4; core++)
602 QLAFX00_SET_HBA_SOC_REG(ha,
603 (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF));
604
605 /* Set Fabric control and config to defaults */
606 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2));
607 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3));
608
8ae6d9c7
GM		 609 /* Kick in Fabric units */
610 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0));
611
612 /* Kick in Core0 to start boot process */
613 QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00));
614
ec1937a2
SK		 615 spin_unlock_irqrestore(&ha->hardware_lock, flags);
616
8ae6d9c7
GM		 617 /* Wait 10secs for soft-reset to complete. */
618 for (cnt = 10; cnt; cnt--) {
619 msleep(1000);
620 barrier();
621 }
8ae6d9c7
GM		 622}
623
624/**
625 * qlafx00_soft_reset() - Soft Reset ISPFx00.
626 * @ha: HA context
627 *
628 * Returns 0 on success.
629 */
630void
631qlafx00_soft_reset(scsi_qla_host_t *vha)
632{
633 struct qla_hw_data *ha = vha->hw;
634
635 if (unlikely(pci_channel_offline(ha->pdev) &&
636 ha->flags.pci_channel_io_perm_failure))
637 return;
638
639 ha->isp_ops->disable_intrs(ha);
640 qlafx00_soc_cpu_reset(vha);
8ae6d9c7
GM		 641}
642
643/**
644 * qlafx00_chip_diag() - Test ISPFx00 for proper operation.
645 * @ha: HA context
646 *
647 * Returns 0 on success.
648 */
649int
650qlafx00_chip_diag(scsi_qla_host_t *vha)
651{
652 int rval = 0;
653 struct qla_hw_data *ha = vha->hw;
654 struct req_que *req = ha->req_q_map[0];
655
656 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
657
658 rval = qlafx00_mbx_reg_test(vha);
659 if (rval) {
660 ql_log(ql_log_warn, vha, 0x1165,
661 "Failed mailbox send register test\n");
662 } else {
663 /* Flag a successful rval */
664 rval = QLA_SUCCESS;
665 }
666 return rval;
667}
668
669void
670qlafx00_config_rings(struct scsi_qla_host *vha)
671{
672 struct qla_hw_data *ha = vha->hw;
673 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
8ae6d9c7
GM		 674
675 WRT_REG_DWORD(&reg->req_q_in, 0);
676 WRT_REG_DWORD(&reg->req_q_out, 0);
677
678 WRT_REG_DWORD(&reg->rsp_q_in, 0);
679 WRT_REG_DWORD(&reg->rsp_q_out, 0);
680
681 /* PCI posting */
682 RD_REG_DWORD(&reg->rsp_q_out);
683}
684
685char *
686qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str)
687{
688 struct qla_hw_data *ha = vha->hw;
8ae6d9c7 689
ce9f7ed9 690 if (pci_is_pcie(ha->pdev)) {
8ae6d9c7
GM		 691 strcpy(str, "PCIe iSA");
692 return str;
693 }
694 return str;
695}
696
697char *
698qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str)
699{
700 struct qla_hw_data *ha = vha->hw;
701
702 sprintf(str, "%s", ha->mr.fw_version);
703 return str;
704}
705
706void
707qlafx00_enable_intrs(struct qla_hw_data *ha)
708{
709 unsigned long flags = 0;
710
711 spin_lock_irqsave(&ha->hardware_lock, flags);
712 ha->interrupts_on = 1;
713 QLAFX00_ENABLE_ICNTRL_REG(ha);
714 spin_unlock_irqrestore(&ha->hardware_lock, flags);
715}
716
717void
718qlafx00_disable_intrs(struct qla_hw_data *ha)
719{
720 unsigned long flags = 0;
721
722 spin_lock_irqsave(&ha->hardware_lock, flags);
723 ha->interrupts_on = 0;
724 QLAFX00_DISABLE_ICNTRL_REG(ha);
725 spin_unlock_irqrestore(&ha->hardware_lock, flags);
726}
727
8ae6d9c7 728int
9cb78c16 729qlafx00_abort_target(fc_port_t *fcport, uint64_t l, int tag)
8ae6d9c7 730{
faef62d1 731 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
8ae6d9c7
GM		 732}
733
734int
9cb78c16 735qlafx00_lun_reset(fc_port_t *fcport, uint64_t l, int tag)
8ae6d9c7 736{
faef62d1 737 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
8ae6d9c7
GM		 738}
739
5854771e
AB		 740int
741qlafx00_loop_reset(scsi_qla_host_t *vha)
742{
743 int ret;
744 struct fc_port *fcport;
745 struct qla_hw_data *ha = vha->hw;
746
747 if (ql2xtargetreset) {
748 list_for_each_entry(fcport, &vha->vp_fcports, list) {
749 if (fcport->port_type != FCT_TARGET)
750 continue;
751
752 ret = ha->isp_ops->target_reset(fcport, 0, 0);
753 if (ret != QLA_SUCCESS) {
754 ql_dbg(ql_dbg_taskm, vha, 0x803d,
755 "Bus Reset failed: Reset=%d "
756 "d_id=%x.\n", ret, fcport->d_id.b24);
757 }
758 }
759 }
760 return QLA_SUCCESS;
761}
762
8ae6d9c7
GM		 763int
764qlafx00_iospace_config(struct qla_hw_data *ha)
765{
766 if (pci_request_selected_regions(ha->pdev, ha->bars,
767 QLA2XXX_DRIVER_NAME)) {
768 ql_log_pci(ql_log_fatal, ha->pdev, 0x014e,
769 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
770 pci_name(ha->pdev));
771 goto iospace_error_exit;
772 }
773
774 /* Use MMIO operations for all accesses. */
775 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
776 ql_log_pci(ql_log_warn, ha->pdev, 0x014f,
777 "Invalid pci I/O region size (%s).\n",
778 pci_name(ha->pdev));
779 goto iospace_error_exit;
780 }
781 if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) {
782 ql_log_pci(ql_log_warn, ha->pdev, 0x0127,
783 "Invalid PCI mem BAR0 region size (%s), aborting\n",
784 pci_name(ha->pdev));
785 goto iospace_error_exit;
786 }
787
788 ha->cregbase =
789 ioremap_nocache(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00);
790 if (!ha->cregbase) {
791 ql_log_pci(ql_log_fatal, ha->pdev, 0x0128,
792 "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
793 goto iospace_error_exit;
794 }
795
796 if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) {
797 ql_log_pci(ql_log_warn, ha->pdev, 0x0129,
798 "region #2 not an MMIO resource (%s), aborting\n",
799 pci_name(ha->pdev));
800 goto iospace_error_exit;
801 }
802 if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) {
803 ql_log_pci(ql_log_warn, ha->pdev, 0x012a,
804 "Invalid PCI mem BAR2 region size (%s), aborting\n",
805 pci_name(ha->pdev));
806 goto iospace_error_exit;
807 }
808
809 ha->iobase =
810 ioremap_nocache(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00);
811 if (!ha->iobase) {
812 ql_log_pci(ql_log_fatal, ha->pdev, 0x012b,
813 "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
814 goto iospace_error_exit;
815 }
816
817 /* Determine queue resources */
818 ha->max_req_queues = ha->max_rsp_queues = 1;
819
820 ql_log_pci(ql_log_info, ha->pdev, 0x012c,
821 "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n",
822 ha->bars, ha->cregbase, ha->iobase);
823
824 return 0;
825
826iospace_error_exit:
827 return -ENOMEM;
828}
829
830static void
831qlafx00_save_queue_ptrs(struct scsi_qla_host *vha)
832{
833 struct qla_hw_data *ha = vha->hw;
834 struct req_que *req = ha->req_q_map[0];
835 struct rsp_que *rsp = ha->rsp_q_map[0];
836
837 req->length_fx00 = req->length;
838 req->ring_fx00 = req->ring;
839 req->dma_fx00 = req->dma;
840
841 rsp->length_fx00 = rsp->length;
842 rsp->ring_fx00 = rsp->ring;
843 rsp->dma_fx00 = rsp->dma;
844
845 ql_dbg(ql_dbg_init, vha, 0x012d,
846 "req: %p, ring_fx00: %p, length_fx00: 0x%x,"
847 "req->dma_fx00: 0x%llx\n", req, req->ring_fx00,
848 req->length_fx00, (u64)req->dma_fx00);
849
850 ql_dbg(ql_dbg_init, vha, 0x012e,
851 "rsp: %p, ring_fx00: %p, length_fx00: 0x%x,"
852 "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00,
853 rsp->length_fx00, (u64)rsp->dma_fx00);
854}
855
856static int
857qlafx00_config_queues(struct scsi_qla_host *vha)
858{
859 struct qla_hw_data *ha = vha->hw;
860 struct req_que *req = ha->req_q_map[0];
861 struct rsp_que *rsp = ha->rsp_q_map[0];
862 dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
863
864 req->length = ha->req_que_len;
865 req->ring = (void *)ha->iobase + ha->req_que_off;
866 req->dma = bar2_hdl + ha->req_que_off;
867 if ((!req->ring) || (req->length == 0)) {
868 ql_log_pci(ql_log_info, ha->pdev, 0x012f,
869 "Unable to allocate memory for req_ring\n");
870 return QLA_FUNCTION_FAILED;
871 }
872
873 ql_dbg(ql_dbg_init, vha, 0x0130,
874 "req: %p req_ring pointer %p req len 0x%x "
875 "req off 0x%x\n, req->dma: 0x%llx",
876 req, req->ring, req->length,
877 ha->req_que_off, (u64)req->dma);
878
879 rsp->length = ha->rsp_que_len;
880 rsp->ring = (void *)ha->iobase + ha->rsp_que_off;
881 rsp->dma = bar2_hdl + ha->rsp_que_off;
882 if ((!rsp->ring) || (rsp->length == 0)) {
883 ql_log_pci(ql_log_info, ha->pdev, 0x0131,
884 "Unable to allocate memory for rsp_ring\n");
885 return QLA_FUNCTION_FAILED;
886 }
887
888 ql_dbg(ql_dbg_init, vha, 0x0132,
889 "rsp: %p rsp_ring pointer %p rsp len 0x%x "
890 "rsp off 0x%x, rsp->dma: 0x%llx\n",
891 rsp, rsp->ring, rsp->length,
892 ha->rsp_que_off, (u64)rsp->dma);
893
894 return QLA_SUCCESS;
895}
896
897static int
898qlafx00_init_fw_ready(scsi_qla_host_t *vha)
899{
900 int rval = 0;
901 unsigned long wtime;
902 uint16_t wait_time; /* Wait time */
903 struct qla_hw_data *ha = vha->hw;
904 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
905 uint32_t aenmbx, aenmbx7 = 0;
f9a2a543 906 uint32_t pseudo_aen;
8ae6d9c7
GM		 907 uint32_t state[5];
908 bool done = false;
909
910 /* 30 seconds wait - Adjust if required */
911 wait_time = 30;
912
f9a2a543
AB		 913 pseudo_aen = RD_REG_DWORD(&reg->pseudoaen);
914 if (pseudo_aen == 1) {
915 aenmbx7 = RD_REG_DWORD(&reg->initval7);
916 ha->mbx_intr_code = MSW(aenmbx7);
917 ha->rqstq_intr_code = LSW(aenmbx7);
918 rval = qlafx00_driver_shutdown(vha, 10);
919 if (rval != QLA_SUCCESS)
920 qlafx00_soft_reset(vha);
921 }
922
8ae6d9c7
GM		 923 /* wait time before firmware ready */
924 wtime = jiffies + (wait_time * HZ);
925 do {
926 aenmbx = RD_REG_DWORD(&reg->aenmailbox0);
927 barrier();
928 ql_dbg(ql_dbg_mbx, vha, 0x0133,
929 "aenmbx: 0x%x\n", aenmbx);
930
931 switch (aenmbx) {
932 case MBA_FW_NOT_STARTED:
933 case MBA_FW_STARTING:
934 break;
935
936 case MBA_SYSTEM_ERR:
937 case MBA_REQ_TRANSFER_ERR:
938 case MBA_RSP_TRANSFER_ERR:
939 case MBA_FW_INIT_FAILURE:
940 qlafx00_soft_reset(vha);
941 break;
942
943 case MBA_FW_RESTART_CMPLT:
944 /* Set the mbx and rqstq intr code */
945 aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
946 ha->mbx_intr_code = MSW(aenmbx7);
947 ha->rqstq_intr_code = LSW(aenmbx7);
948 ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
949 ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
950 ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
951 ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
952 WRT_REG_DWORD(&reg->aenmailbox0, 0);
953 RD_REG_DWORD_RELAXED(&reg->aenmailbox0);
954 ql_dbg(ql_dbg_init, vha, 0x0134,
955 "f/w returned mbx_intr_code: 0x%x, "
956 "rqstq_intr_code: 0x%x\n",
957 ha->mbx_intr_code, ha->rqstq_intr_code);
958 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
959 rval = QLA_SUCCESS;
960 done = true;
961 break;
962
963 default:
0f8cdff5
AB		 964 if ((aenmbx & 0xFF00) == MBA_FW_INIT_INPROGRESS)
965 break;
966
8ae6d9c7
GM		 967 /* If fw is apparently not ready. In order to continue,
968 * we might need to issue Mbox cmd, but the problem is
969 * that the DoorBell vector values that come with the
970 * 8060 AEN are most likely gone by now (and thus no
971 * bell would be rung on the fw side when mbox cmd is
972 * issued). We have to therefore grab the 8060 AEN
973 * shadow regs (filled in by FW when the last 8060
974 * AEN was being posted).
975 * Do the following to determine what is needed in
976 * order to get the FW ready:
977 * 1. reload the 8060 AEN values from the shadow regs
978 * 2. clear int status to get rid of possible pending
979 * interrupts
980 * 3. issue Get FW State Mbox cmd to determine fw state
981 * Set the mbx and rqstq intr code from Shadow Regs
982 */
983 aenmbx7 = RD_REG_DWORD(&reg->initval7);
984 ha->mbx_intr_code = MSW(aenmbx7);
985 ha->rqstq_intr_code = LSW(aenmbx7);
986 ha->req_que_off = RD_REG_DWORD(&reg->initval1);
987 ha->rsp_que_off = RD_REG_DWORD(&reg->initval3);
988 ha->req_que_len = RD_REG_DWORD(&reg->initval5);
989 ha->rsp_que_len = RD_REG_DWORD(&reg->initval6);
990 ql_dbg(ql_dbg_init, vha, 0x0135,
991 "f/w returned mbx_intr_code: 0x%x, "
992 "rqstq_intr_code: 0x%x\n",
993 ha->mbx_intr_code, ha->rqstq_intr_code);
994 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
995
996 /* Get the FW state */
997 rval = qlafx00_get_firmware_state(vha, state);
998 if (rval != QLA_SUCCESS) {
999 /* Retry if timer has not expired */
1000 break;
1001 }
1002
1003 if (state[0] == FSTATE_FX00_CONFIG_WAIT) {
1004 /* Firmware is waiting to be
1005 * initialized by driver
1006 */
1007 rval = QLA_SUCCESS;
1008 done = true;
1009 break;
1010 }
1011
1012 /* Issue driver shutdown and wait until f/w recovers.
1013 * Driver should continue to poll until 8060 AEN is
1014 * received indicating firmware recovery.
1015 */
1016 ql_dbg(ql_dbg_init, vha, 0x0136,
1017 "Sending Driver shutdown fw_state 0x%x\n",
1018 state[0]);
1019
1020 rval = qlafx00_driver_shutdown(vha, 10);
1021 if (rval != QLA_SUCCESS) {
1022 rval = QLA_FUNCTION_FAILED;
1023 break;
1024 }
1025 msleep(500);
1026
1027 wtime = jiffies + (wait_time * HZ);
1028 break;
1029 }
1030
1031 if (!done) {
1032 if (time_after_eq(jiffies, wtime)) {
1033 ql_dbg(ql_dbg_init, vha, 0x0137,
1034 "Init f/w failed: aen[7]: 0x%x\n",
1035 RD_REG_DWORD(&reg->aenmailbox7));
1036 rval = QLA_FUNCTION_FAILED;
1037 done = true;
1038 break;
1039 }
1040 /* Delay for a while */
1041 msleep(500);
1042 }
1043 } while (!done);
1044
1045 if (rval)
1046 ql_dbg(ql_dbg_init, vha, 0x0138,
1047 "%s **** FAILED ****.\n", __func__);
1048 else
1049 ql_dbg(ql_dbg_init, vha, 0x0139,
1050 "%s **** SUCCESS ****.\n", __func__);
1051
1052 return rval;
1053}
1054
1055/*
1056 * qlafx00_fw_ready() - Waits for firmware ready.
1057 * @ha: HA context
1058 *
1059 * Returns 0 on success.
1060 */
1061int
1062qlafx00_fw_ready(scsi_qla_host_t *vha)
1063{
1064 int rval;
1065 unsigned long wtime;
1066 uint16_t wait_time; /* Wait time if loop is coming ready */
1067 uint32_t state[5];
1068
1069 rval = QLA_SUCCESS;
1070
1071 wait_time = 10;
1072
1073 /* wait time before firmware ready */
1074 wtime = jiffies + (wait_time * HZ);
1075
1076 /* Wait for ISP to finish init */
1077 if (!vha->flags.init_done)
1078 ql_dbg(ql_dbg_init, vha, 0x013a,
1079 "Waiting for init to complete...\n");
1080
1081 do {
1082 rval = qlafx00_get_firmware_state(vha, state);
1083
1084 if (rval == QLA_SUCCESS) {
1085 if (state[0] == FSTATE_FX00_INITIALIZED) {
1086 ql_dbg(ql_dbg_init, vha, 0x013b,
1087 "fw_state=%x\n", state[0]);
1088 rval = QLA_SUCCESS;
1089 break;
1090 }
1091 }
1092 rval = QLA_FUNCTION_FAILED;
1093
1094 if (time_after_eq(jiffies, wtime))
1095 break;
1096
1097 /* Delay for a while */
1098 msleep(500);
1099
1100 ql_dbg(ql_dbg_init, vha, 0x013c,
1101 "fw_state=%x curr time=%lx.\n", state[0], jiffies);
1102 } while (1);
1103
1104
1105 if (rval)
1106 ql_dbg(ql_dbg_init, vha, 0x013d,
1107 "Firmware ready **** FAILED ****.\n");
1108 else
1109 ql_dbg(ql_dbg_init, vha, 0x013e,
1110 "Firmware ready **** SUCCESS ****.\n");
1111
1112 return rval;
1113}
1114
1115static int
1116qlafx00_find_all_targets(scsi_qla_host_t *vha,
1117 struct list_head *new_fcports)
1118{
1119 int rval;
1120 uint16_t tgt_id;
1121 fc_port_t *fcport, *new_fcport;
1122 int found;
1123 struct qla_hw_data *ha = vha->hw;
1124
1125 rval = QLA_SUCCESS;
1126
1127 if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
1128 return QLA_FUNCTION_FAILED;
1129
1130 if ((atomic_read(&vha->loop_down_timer) ||
1131 STATE_TRANSITION(vha))) {
1132 atomic_set(&vha->loop_down_timer, 0);
1133 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1134 return QLA_FUNCTION_FAILED;
1135 }
1136
1137 ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
1138 "Listing Target bit map...\n");
1139 ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha,
1140 0x2089, (uint8_t *)ha->gid_list, 32);
1141
1142 /* Allocate temporary rmtport for any new rmtports discovered. */
1143 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1144 if (new_fcport == NULL)
1145 return QLA_MEMORY_ALLOC_FAILED;
1146
1147 for_each_set_bit(tgt_id, (void *)ha->gid_list,
1148 QLAFX00_TGT_NODE_LIST_SIZE) {
1149
1150 /* Send get target node info */
1151 new_fcport->tgt_id = tgt_id;
1152 rval = qlafx00_fx_disc(vha, new_fcport,
1153 FXDISC_GET_TGT_NODE_INFO);
1154 if (rval != QLA_SUCCESS) {
1155 ql_log(ql_log_warn, vha, 0x208a,
1156 "Target info scan failed -- assuming zero-entry "
1157 "result...\n");
1158 continue;
1159 }
1160
1161 /* Locate matching device in database. */
1162 found = 0;
1163 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1164 if (memcmp(new_fcport->port_name,
1165 fcport->port_name, WWN_SIZE))
1166 continue;
1167
1168 found++;
1169
1170 /*
1171 * If tgt_id is same and state FCS_ONLINE, nothing
1172 * changed.
1173 */
1174 if (fcport->tgt_id == new_fcport->tgt_id &&
1175 atomic_read(&fcport->state) == FCS_ONLINE)
1176 break;
1177
1178 /*
1179 * Tgt ID changed or device was marked to be updated.
1180 */
1181 ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b,
1182 "TGT-ID Change(%s): Present tgt id: "
1183 "0x%x state: 0x%x "
1184 "wwnn = %llx wwpn = %llx.\n",
1185 __func__, fcport->tgt_id,
1186 atomic_read(&fcport->state),
1187 (unsigned long long)wwn_to_u64(fcport->node_name),
1188 (unsigned long long)wwn_to_u64(fcport->port_name));
1189
1190 ql_log(ql_log_info, vha, 0x208c,
1191 "TGT-ID Announce(%s): Discovered tgt "
1192 "id 0x%x wwnn = %llx "
1193 "wwpn = %llx.\n", __func__, new_fcport->tgt_id,
1194 (unsigned long long)
1195 wwn_to_u64(new_fcport->node_name),
1196 (unsigned long long)
1197 wwn_to_u64(new_fcport->port_name));
1198
1199 if (atomic_read(&fcport->state) != FCS_ONLINE) {
1200 fcport->old_tgt_id = fcport->tgt_id;
1201 fcport->tgt_id = new_fcport->tgt_id;
1202 ql_log(ql_log_info, vha, 0x208d,
1203 "TGT-ID: New fcport Added: %p\n", fcport);
1204 qla2x00_update_fcport(vha, fcport);
1205 } else {
1206 ql_log(ql_log_info, vha, 0x208e,
1207 " Existing TGT-ID %x did not get "
1208 " offline event from firmware.\n",
1209 fcport->old_tgt_id);
1210 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1211 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1212 kfree(new_fcport);
1213 return rval;
1214 }
1215 break;
1216 }
1217
1218 if (found)
1219 continue;
1220
1221 /* If device was not in our fcports list, then add it. */
1222 list_add_tail(&new_fcport->list, new_fcports);
1223
1224 /* Allocate a new replacement fcport. */
1225 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1226 if (new_fcport == NULL)
1227 return QLA_MEMORY_ALLOC_FAILED;
1228 }
1229
1230 kfree(new_fcport);
1231 return rval;
1232}
1233
1234/*
1235 * qlafx00_configure_all_targets
1236 * Setup target devices with node ID's.
1237 *
1238 * Input:
1239 * ha = adapter block pointer.
1240 *
1241 * Returns:
1242 * 0 = success.
1243 * BIT_0 = error
1244 */
1245static int
1246qlafx00_configure_all_targets(scsi_qla_host_t *vha)
1247{
1248 int rval;
1249 fc_port_t *fcport, *rmptemp;
1250 LIST_HEAD(new_fcports);
1251
1252 rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1253 FXDISC_GET_TGT_NODE_LIST);
1254 if (rval != QLA_SUCCESS) {
1255 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1256 return rval;
1257 }
1258
1259 rval = qlafx00_find_all_targets(vha, &new_fcports);
1260 if (rval != QLA_SUCCESS) {
1261 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1262 return rval;
1263 }
1264
1265 /*
1266 * Delete all previous devices marked lost.
1267 */
1268 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1269 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1270 break;
1271
1272 if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
1273 if (fcport->port_type != FCT_INITIATOR)
1274 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1275 }
1276 }
1277
1278 /*
1279 * Add the new devices to our devices list.
1280 */
1281 list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
1282 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1283 break;
1284
1285 qla2x00_update_fcport(vha, fcport);
1286 list_move_tail(&fcport->list, &vha->vp_fcports);
1287 ql_log(ql_log_info, vha, 0x208f,
1288 "Attach new target id 0x%x wwnn = %llx "
1289 "wwpn = %llx.\n",
1290 fcport->tgt_id,
1291 (unsigned long long)wwn_to_u64(fcport->node_name),
1292 (unsigned long long)wwn_to_u64(fcport->port_name));
1293 }
1294
1295 /* Free all new device structures not processed. */
1296 list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
1297 list_del(&fcport->list);
1298 kfree(fcport);
1299 }
1300
1301 return rval;
1302}
1303
1304/*
1305 * qlafx00_configure_devices
1306 * Updates Fibre Channel Device Database with what is actually on loop.
1307 *
1308 * Input:
1309 * ha = adapter block pointer.
1310 *
1311 * Returns:
1312 * 0 = success.
1313 * 1 = error.
1314 * 2 = database was full and device was not configured.
1315 */
1316int
1317qlafx00_configure_devices(scsi_qla_host_t *vha)
1318{
1319 int rval;
1320 unsigned long flags, save_flags;
1321 rval = QLA_SUCCESS;
1322
1323 save_flags = flags = vha->dpc_flags;
1324
1325 ql_dbg(ql_dbg_disc, vha, 0x2090,
1326 "Configure devices -- dpc flags =0x%lx\n", flags);
1327
1328 rval = qlafx00_configure_all_targets(vha);
1329
1330 if (rval == QLA_SUCCESS) {
1331 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1332 rval = QLA_FUNCTION_FAILED;
1333 } else {
1334 atomic_set(&vha->loop_state, LOOP_READY);
1335 ql_log(ql_log_info, vha, 0x2091,
1336 "Device Ready\n");
1337 }
1338 }
1339
1340 if (rval) {
1341 ql_dbg(ql_dbg_disc, vha, 0x2092,
1342 "%s *** FAILED ***.\n", __func__);
1343 } else {
1344 ql_dbg(ql_dbg_disc, vha, 0x2093,
1345 "%s: exiting normally.\n", __func__);
1346 }
1347 return rval;
1348}
1349
1350static void
71e56003 1351qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha, bool critemp)
8ae6d9c7
GM		 1352{
1353 struct qla_hw_data *ha = vha->hw;
1354 fc_port_t *fcport;
1355
1356 vha->flags.online = 0;
8ae6d9c7 1357 ha->mr.fw_hbt_en = 0;
8ae6d9c7 1358
71e56003
AB		 1359 if (!critemp) {
1360 ha->flags.chip_reset_done = 0;
1361 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1362 vha->qla_stats.total_isp_aborts++;
1363 ql_log(ql_log_info, vha, 0x013f,
1364 "Performing ISP error recovery - ha = %p.\n", ha);
1365 ha->isp_ops->reset_chip(vha);
1366 }
8ae6d9c7
GM		 1367
1368 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
1369 atomic_set(&vha->loop_state, LOOP_DOWN);
1370 atomic_set(&vha->loop_down_timer,
1371 QLAFX00_LOOP_DOWN_TIME);
1372 } else {
1373 if (!atomic_read(&vha->loop_down_timer))
1374 atomic_set(&vha->loop_down_timer,
1375 QLAFX00_LOOP_DOWN_TIME);
1376 }
1377
1378 /* Clear all async request states across all VPs. */
1379 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1380 fcport->flags = 0;
1381 if (atomic_read(&fcport->state) == FCS_ONLINE)
1382 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1383 }
1384
1385 if (!ha->flags.eeh_busy) {
71e56003
AB		 1386 if (critemp) {
1387 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
1388 } else {
1389 /* Requeue all commands in outstanding command list. */
1390 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
1391 }
8ae6d9c7
GM		 1392 }
1393
1394 qla2x00_free_irqs(vha);
71e56003
AB		 1395 if (critemp)
1396 set_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags);
1397 else
1398 set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
8ae6d9c7
GM		 1399
1400 /* Clear the Interrupts */
1401 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1402
1403 ql_log(ql_log_info, vha, 0x0140,
1404 "%s Done done - ha=%p.\n", __func__, ha);
1405}
1406
1407/**
1408 * qlafx00_init_response_q_entries() - Initializes response queue entries.
1409 * @ha: HA context
1410 *
1411 * Beginning of request ring has initialization control block already built
1412 * by nvram config routine.
1413 *
1414 * Returns 0 on success.
1415 */
1416void
1417qlafx00_init_response_q_entries(struct rsp_que *rsp)
1418{
1419 uint16_t cnt;
1420 response_t *pkt;
1421
1422 rsp->ring_ptr = rsp->ring;
1423 rsp->ring_index = 0;
1424 rsp->status_srb = NULL;
1425 pkt = rsp->ring_ptr;
1426 for (cnt = 0; cnt < rsp->length; cnt++) {
1427 pkt->signature = RESPONSE_PROCESSED;
1f8deefe
SK		 1428 WRT_REG_DWORD((void __iomem *)&pkt->signature,
1429 RESPONSE_PROCESSED);
8ae6d9c7
GM		 1430 pkt++;
1431 }
1432}
1433
1434int
1435qlafx00_rescan_isp(scsi_qla_host_t *vha)
1436{
1437 uint32_t status = QLA_FUNCTION_FAILED;
1438 struct qla_hw_data *ha = vha->hw;
1439 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
1440 uint32_t aenmbx7;
1441
1442 qla2x00_request_irqs(ha, ha->rsp_q_map[0]);
1443
1444 aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
1445 ha->mbx_intr_code = MSW(aenmbx7);
1446 ha->rqstq_intr_code = LSW(aenmbx7);
1447 ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
1448 ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
1449 ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
1450 ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
1451
1452 ql_dbg(ql_dbg_disc, vha, 0x2094,
1453 "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x "
1454 " Req que offset 0x%x Rsp que offset 0x%x\n",
1455 ha->mbx_intr_code, ha->rqstq_intr_code,
1456 ha->req_que_off, ha->rsp_que_len);
1457
1458 /* Clear the Interrupts */
1459 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1460
1461 status = qla2x00_init_rings(vha);
1462 if (!status) {
1463 vha->flags.online = 1;
1464
1465 /* if no cable then assume it's good */
1466 if ((vha->device_flags & DFLG_NO_CABLE))
1467 status = 0;
1468 /* Register system information */
1469 if (qlafx00_fx_disc(vha,
1470 &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO))
1471 ql_dbg(ql_dbg_disc, vha, 0x2095,
1472 "failed to register host info\n");
1473 }
1474 scsi_unblock_requests(vha->host);
1475 return status;
1476}
1477
1478void
1479qlafx00_timer_routine(scsi_qla_host_t *vha)
1480{
1481 struct qla_hw_data *ha = vha->hw;
1482 uint32_t fw_heart_beat;
1483 uint32_t aenmbx0;
1484 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
71e56003 1485 uint32_t tempc;
8ae6d9c7
GM		 1486
1487 /* Check firmware health */
1488 if (ha->mr.fw_hbt_cnt)
1489 ha->mr.fw_hbt_cnt--;
1490 else {
1491 if ((!ha->flags.mr_reset_hdlr_active) &&
1492 (!test_bit(UNLOADING, &vha->dpc_flags)) &&
1493 (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
1494 (ha->mr.fw_hbt_en)) {
1495 fw_heart_beat = RD_REG_DWORD(&reg->fwheartbeat);
1496 if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) {
1497 ha->mr.old_fw_hbt_cnt = fw_heart_beat;
1498 ha->mr.fw_hbt_miss_cnt = 0;
1499 } else {
1500 ha->mr.fw_hbt_miss_cnt++;
1501 if (ha->mr.fw_hbt_miss_cnt ==
1502 QLAFX00_HEARTBEAT_MISS_CNT) {
1503 set_bit(ISP_ABORT_NEEDED,
1504 &vha->dpc_flags);
1505 qla2xxx_wake_dpc(vha);
1506 ha->mr.fw_hbt_miss_cnt = 0;
1507 }
1508 }
1509 }
1510 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
1511 }
1512
1513 if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) {
1514 /* Reset recovery to be performed in timer routine */
1515 aenmbx0 = RD_REG_DWORD(&reg->aenmailbox0);
1516 if (ha->mr.fw_reset_timer_exp) {
1517 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1518 qla2xxx_wake_dpc(vha);
1519 ha->mr.fw_reset_timer_exp = 0;
1520 } else if (aenmbx0 == MBA_FW_RESTART_CMPLT) {
1521 /* Wake up DPC to rescan the targets */
1522 set_bit(FX00_TARGET_SCAN, &vha->dpc_flags);
1523 clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1524 qla2xxx_wake_dpc(vha);
1525 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1526 } else if ((aenmbx0 == MBA_FW_STARTING) &&
1527 (!ha->mr.fw_hbt_en)) {
1528 ha->mr.fw_hbt_en = 1;
1529 } else if (!ha->mr.fw_reset_timer_tick) {
1530 if (aenmbx0 == ha->mr.old_aenmbx0_state)
1531 ha->mr.fw_reset_timer_exp = 1;
1532 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1533 } else if (aenmbx0 == 0xFFFFFFFF) {
1534 uint32_t data0, data1;
1535
1536 data0 = QLAFX00_RD_REG(ha,
1537 QLAFX00_BAR1_BASE_ADDR_REG);
1538 data1 = QLAFX00_RD_REG(ha,
1539 QLAFX00_PEX0_WIN0_BASE_ADDR_REG);
1540
1541 data0 &= 0xffff0000;
1542 data1 &= 0x0000ffff;
1543
1544 QLAFX00_WR_REG(ha,
1545 QLAFX00_PEX0_WIN0_BASE_ADDR_REG,
1546 (data0 | data1));
1547 } else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) {
1548 ha->mr.fw_reset_timer_tick =
1549 QLAFX00_MAX_RESET_INTERVAL;
b6511d99
AB		 1550 } else if (aenmbx0 == MBA_FW_RESET_FCT) {
1551 ha->mr.fw_reset_timer_tick =
1552 QLAFX00_MAX_RESET_INTERVAL;
8ae6d9c7
GM		 1553 }
1554 ha->mr.old_aenmbx0_state = aenmbx0;
1555 ha->mr.fw_reset_timer_tick--;
1556 }
71e56003
AB		 1557 if (test_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags)) {
1558 /*
1559 * Critical temperature recovery to be
1560 * performed in timer routine
1561 */
1562 if (ha->mr.fw_critemp_timer_tick == 0) {
1563 tempc = QLAFX00_GET_TEMPERATURE(ha);
6ddcfef7 1564 ql_dbg(ql_dbg_timer, vha, 0x6012,
71e56003
AB		 1565 "ISPFx00(%s): Critical temp timer, "
1566 "current SOC temperature: %d\n",
1567 __func__, tempc);
1568 if (tempc < ha->mr.critical_temperature) {
1569 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1570 clear_bit(FX00_CRITEMP_RECOVERY,
1571 &vha->dpc_flags);
1572 qla2xxx_wake_dpc(vha);
1573 }
1574 ha->mr.fw_critemp_timer_tick =
1575 QLAFX00_CRITEMP_INTERVAL;
1576 } else {
1577 ha->mr.fw_critemp_timer_tick--;
1578 }
1579 }
e8f5e95d
AB		 1580 if (ha->mr.host_info_resend) {
1581 /*
1582 * Incomplete host info might be sent to firmware
1583 * durinng system boot - info should be resend
1584 */
1585 if (ha->mr.hinfo_resend_timer_tick == 0) {
1586 ha->mr.host_info_resend = false;
1587 set_bit(FX00_HOST_INFO_RESEND, &vha->dpc_flags);
1588 ha->mr.hinfo_resend_timer_tick =
1589 QLAFX00_HINFO_RESEND_INTERVAL;
1590 qla2xxx_wake_dpc(vha);
1591 } else {
1592 ha->mr.hinfo_resend_timer_tick--;
1593 }
1594 }
1595
8ae6d9c7
GM		 1596}
1597
1598/*
1599 * qlfx00a_reset_initialize
1600 * Re-initialize after a iSA device reset.
1601 *
1602 * Input:
1603 * ha = adapter block pointer.
1604 *
1605 * Returns:
1606 * 0 = success
1607 */
1608int
1609qlafx00_reset_initialize(scsi_qla_host_t *vha)
1610{
1611 struct qla_hw_data *ha = vha->hw;
1612
1613 if (vha->device_flags & DFLG_DEV_FAILED) {
1614 ql_dbg(ql_dbg_init, vha, 0x0142,
1615 "Device in failed state\n");
1616 return QLA_SUCCESS;
1617 }
1618
1619 ha->flags.mr_reset_hdlr_active = 1;
1620
1621 if (vha->flags.online) {
1622 scsi_block_requests(vha->host);
71e56003 1623 qlafx00_abort_isp_cleanup(vha, false);
8ae6d9c7
GM		 1624 }
1625
1626 ql_log(ql_log_info, vha, 0x0143,
1627 "(%s): succeeded.\n", __func__);
1628 ha->flags.mr_reset_hdlr_active = 0;
1629 return QLA_SUCCESS;
1630}
1631
1632/*
1633 * qlafx00_abort_isp
1634 * Resets ISP and aborts all outstanding commands.
1635 *
1636 * Input:
1637 * ha = adapter block pointer.
1638 *
1639 * Returns:
1640 * 0 = success
1641 */
1642int
1643qlafx00_abort_isp(scsi_qla_host_t *vha)
1644{
1645 struct qla_hw_data *ha = vha->hw;
1646
1647 if (vha->flags.online) {
1648 if (unlikely(pci_channel_offline(ha->pdev) &&
1649 ha->flags.pci_channel_io_perm_failure)) {
1650 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1651 return QLA_SUCCESS;
1652 }
1653
1654 scsi_block_requests(vha->host);
71e56003 1655 qlafx00_abort_isp_cleanup(vha, false);
e601d778
AB		 1656 } else {
1657 scsi_block_requests(vha->host);
1658 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1659 vha->qla_stats.total_isp_aborts++;
1660 ha->isp_ops->reset_chip(vha);
1661 set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1662 /* Clear the Interrupts */
1663 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
8ae6d9c7
GM		 1664 }
1665
1666 ql_log(ql_log_info, vha, 0x0145,
1667 "(%s): succeeded.\n", __func__);
1668
1669 return QLA_SUCCESS;
1670}
1671
1672static inline fc_port_t*
1673qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id)
1674{
1675 fc_port_t *fcport;
1676
1677 /* Check for matching device in remote port list. */
1678 fcport = NULL;
1679 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1680 if (fcport->tgt_id == tgt_id) {
1681 ql_dbg(ql_dbg_async, vha, 0x5072,
1682 "Matching fcport(%p) found with TGT-ID: 0x%x "
1683 "and Remote TGT_ID: 0x%x\n",
1684 fcport, fcport->tgt_id, tgt_id);
1685 break;
1686 }
1687 }
1688 return fcport;
1689}
1690
1691static void
1692qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id)
1693{
1694 fc_port_t *fcport;
1695
1696 ql_log(ql_log_info, vha, 0x5073,
1697 "Detach TGT-ID: 0x%x\n", tgt_id);
1698
1699 fcport = qlafx00_get_fcport(vha, tgt_id);
1700 if (!fcport)
1701 return;
1702
1703 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1704
1705 return;
1706}
1707
1708int
1709qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt)
1710{
1711 int rval = 0;
1712 uint32_t aen_code, aen_data;
1713
1714 aen_code = FCH_EVT_VENDOR_UNIQUE;
1715 aen_data = evt->u.aenfx.evtcode;
1716
1717 switch (evt->u.aenfx.evtcode) {
1718 case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
1719 if (evt->u.aenfx.mbx[1] == 0) {
1720 if (evt->u.aenfx.mbx[2] == 1) {
1721 if (!vha->flags.fw_tgt_reported)
1722 vha->flags.fw_tgt_reported = 1;
1723 atomic_set(&vha->loop_down_timer, 0);
1724 atomic_set(&vha->loop_state, LOOP_UP);
1725 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1726 qla2xxx_wake_dpc(vha);
1727 } else if (evt->u.aenfx.mbx[2] == 2) {
1728 qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]);
1729 }
1730 } else if (evt->u.aenfx.mbx[1] == 0xffff) {
1731 if (evt->u.aenfx.mbx[2] == 1) {
1732 if (!vha->flags.fw_tgt_reported)
1733 vha->flags.fw_tgt_reported = 1;
1734 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1735 } else if (evt->u.aenfx.mbx[2] == 2) {
1736 vha->device_flags |= DFLG_NO_CABLE;
1737 qla2x00_mark_all_devices_lost(vha, 1);
1738 }
1739 }
1740 break;
1741 case QLAFX00_MBA_LINK_UP:
1742 aen_code = FCH_EVT_LINKUP;
1743 aen_data = 0;
1744 break;
1745 case QLAFX00_MBA_LINK_DOWN:
1746 aen_code = FCH_EVT_LINKDOWN;
1747 aen_data = 0;
1748 break;
71e56003
AB		 1749 case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
1750 ql_log(ql_log_info, vha, 0x5082,
1751 "Process critical temperature event "
1752 "aenmb[0]: %x\n",
1753 evt->u.aenfx.evtcode);
1754 scsi_block_requests(vha->host);
1755 qlafx00_abort_isp_cleanup(vha, true);
1756 scsi_unblock_requests(vha->host);
1757 break;
8ae6d9c7
GM		 1758 }
1759
1760 fc_host_post_event(vha->host, fc_get_event_number(),
1761 aen_code, aen_data);
1762
1763 return rval;
1764}
1765
1766static void
1767qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo)
1768{
1769 u64 port_name = 0, node_name = 0;
1770
1771 port_name = (unsigned long long)wwn_to_u64(pinfo->port_name);
1772 node_name = (unsigned long long)wwn_to_u64(pinfo->node_name);
1773
1774 fc_host_node_name(vha->host) = node_name;
1775 fc_host_port_name(vha->host) = port_name;
1776 if (!pinfo->port_type)
1777 vha->hw->current_topology = ISP_CFG_F;
1778 if (pinfo->link_status == QLAFX00_LINK_STATUS_UP)
1779 atomic_set(&vha->loop_state, LOOP_READY);
1780 else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN)
1781 atomic_set(&vha->loop_state, LOOP_DOWN);
1782 vha->hw->link_data_rate = (uint16_t)pinfo->link_config;
1783}
1784
1785static void
1786qla2x00_fxdisc_iocb_timeout(void *data)
1787{
1788 srb_t *sp = (srb_t *)data;
1789 struct srb_iocb *lio = &sp->u.iocb_cmd;
1790
1791 complete(&lio->u.fxiocb.fxiocb_comp);
1792}
1793
1794static void
1795qla2x00_fxdisc_sp_done(void *data, void *ptr, int res)
1796{
1797 srb_t *sp = (srb_t *)ptr;
1798 struct srb_iocb *lio = &sp->u.iocb_cmd;
1799
1800 complete(&lio->u.fxiocb.fxiocb_comp);
1801}
1802
1803int
1f8deefe 1804qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
8ae6d9c7
GM		 1805{
1806 srb_t *sp;
1807 struct srb_iocb *fdisc;
1808 int rval = QLA_FUNCTION_FAILED;
1809 struct qla_hw_data *ha = vha->hw;
1810 struct host_system_info *phost_info;
1811 struct register_host_info *preg_hsi;
1812 struct new_utsname *p_sysid = NULL;
1813 struct timeval tv;
1814
1815 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1816 if (!sp)
1817 goto done;
1818
1819 fdisc = &sp->u.iocb_cmd;
1820 switch (fx_type) {
1821 case FXDISC_GET_CONFIG_INFO:
1822 fdisc->u.fxiocb.flags =
1823 SRB_FXDISC_RESP_DMA_VALID;
1824 fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data);
1825 break;
1826 case FXDISC_GET_PORT_INFO:
1827 fdisc->u.fxiocb.flags =
1828 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1829 fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO;
1f8deefe 1830 fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->port_id);
8ae6d9c7
GM		 1831 break;
1832 case FXDISC_GET_TGT_NODE_INFO:
1833 fdisc->u.fxiocb.flags =
1834 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1835 fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO;
1f8deefe 1836 fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->tgt_id);
8ae6d9c7
GM		 1837 break;
1838 case FXDISC_GET_TGT_NODE_LIST:
1839 fdisc->u.fxiocb.flags =
1840 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1841 fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE;
1842 break;
1843 case FXDISC_REG_HOST_INFO:
1844 fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID;
1845 fdisc->u.fxiocb.req_len = sizeof(struct register_host_info);
1846 p_sysid = utsname();
1847 if (!p_sysid) {
1848 ql_log(ql_log_warn, vha, 0x303c,
0b1587b1 1849 "Not able to get the system information\n");
8ae6d9c7
GM		 1850 goto done_free_sp;
1851 }
1852 break;
767157c5 1853 case FXDISC_ABORT_IOCTL:
8ae6d9c7
GM		 1854 default:
1855 break;
1856 }
1857
1858 if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
1859 fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev,
1860 fdisc->u.fxiocb.req_len,
1861 &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL);
1862 if (!fdisc->u.fxiocb.req_addr)
1863 goto done_free_sp;
1864
1865 if (fx_type == FXDISC_REG_HOST_INFO) {
1866 preg_hsi = (struct register_host_info *)
1867 fdisc->u.fxiocb.req_addr;
1868 phost_info = &preg_hsi->hsi;
1869 memset(preg_hsi, 0, sizeof(struct register_host_info));
1870 phost_info->os_type = OS_TYPE_LINUX;
1871 strncpy(phost_info->sysname,
1872 p_sysid->sysname, SYSNAME_LENGTH);
1873 strncpy(phost_info->nodename,
1874 p_sysid->nodename, NODENAME_LENGTH);
e8f5e95d
AB		 1875 if (!strcmp(phost_info->nodename, "(none)"))
1876 ha->mr.host_info_resend = true;
8ae6d9c7
GM		 1877 strncpy(phost_info->release,
1878 p_sysid->release, RELEASE_LENGTH);
1879 strncpy(phost_info->version,
1880 p_sysid->version, VERSION_LENGTH);
1881 strncpy(phost_info->machine,
1882 p_sysid->machine, MACHINE_LENGTH);
1883 strncpy(phost_info->domainname,
1884 p_sysid->domainname, DOMNAME_LENGTH);
1885 strncpy(phost_info->hostdriver,
1886 QLA2XXX_VERSION, VERSION_LENGTH);
1887 do_gettimeofday(&tv);
1888 preg_hsi->utc = (uint64_t)tv.tv_sec;
1889 ql_dbg(ql_dbg_init, vha, 0x0149,
1890 "ISP%04X: Host registration with firmware\n",
1891 ha->pdev->device);
1892 ql_dbg(ql_dbg_init, vha, 0x014a,
1893 "os_type = '%d', sysname = '%s', nodname = '%s'\n",
1894 phost_info->os_type,
1895 phost_info->sysname,
1896 phost_info->nodename);
1897 ql_dbg(ql_dbg_init, vha, 0x014b,
1898 "release = '%s', version = '%s'\n",
1899 phost_info->release,
1900 phost_info->version);
1901 ql_dbg(ql_dbg_init, vha, 0x014c,
1902 "machine = '%s' "
1903 "domainname = '%s', hostdriver = '%s'\n",
1904 phost_info->machine,
1905 phost_info->domainname,
1906 phost_info->hostdriver);
1907 ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
1908 (uint8_t *)phost_info,
1909 sizeof(struct host_system_info));
1910 }
1911 }
1912
1913 if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
1914 fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev,
1915 fdisc->u.fxiocb.rsp_len,
1916 &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL);
1917 if (!fdisc->u.fxiocb.rsp_addr)
1918 goto done_unmap_req;
1919 }
1920
1921 sp->type = SRB_FXIOCB_DCMD;
1922 sp->name = "fxdisc";
1923 qla2x00_init_timer(sp, FXDISC_TIMEOUT);
1924 fdisc->timeout = qla2x00_fxdisc_iocb_timeout;
1f8deefe 1925 fdisc->u.fxiocb.req_func_type = cpu_to_le16(fx_type);
8ae6d9c7
GM		 1926 sp->done = qla2x00_fxdisc_sp_done;
1927
1928 rval = qla2x00_start_sp(sp);
1929 if (rval != QLA_SUCCESS)
1930 goto done_unmap_dma;
1931
1932 wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp);
1933
1934 if (fx_type == FXDISC_GET_CONFIG_INFO) {
1935 struct config_info_data *pinfo =
1936 (struct config_info_data *) fdisc->u.fxiocb.rsp_addr;
03eb912a
AB		 1937 strcpy(vha->hw->model_number, pinfo->model_num);
1938 strcpy(vha->hw->model_desc, pinfo->model_description);
8ae6d9c7
GM		 1939 memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name,
1940 sizeof(vha->hw->mr.symbolic_name));
1941 memcpy(&vha->hw->mr.serial_num, pinfo->serial_num,
1942 sizeof(vha->hw->mr.serial_num));
1943 memcpy(&vha->hw->mr.hw_version, pinfo->hw_version,
1944 sizeof(vha->hw->mr.hw_version));
1945 memcpy(&vha->hw->mr.fw_version, pinfo->fw_version,
1946 sizeof(vha->hw->mr.fw_version));
1947 strim(vha->hw->mr.fw_version);
1948 memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version,
1949 sizeof(vha->hw->mr.uboot_version));
1950 memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num,
1951 sizeof(vha->hw->mr.fru_serial_num));
f875cd4c
AB		 1952 vha->hw->mr.critical_temperature =
1953 (pinfo->nominal_temp_value) ?
1954 pinfo->nominal_temp_value : QLAFX00_CRITEMP_THRSHLD;
1fe19ee4
AB		 1955 ha->mr.extended_io_enabled = (pinfo->enabled_capabilities &
1956 QLAFX00_EXTENDED_IO_EN_MASK) != 0;
8ae6d9c7
GM		 1957 } else if (fx_type == FXDISC_GET_PORT_INFO) {
1958 struct port_info_data *pinfo =
1959 (struct port_info_data *) fdisc->u.fxiocb.rsp_addr;
1960 memcpy(vha->node_name, pinfo->node_name, WWN_SIZE);
1961 memcpy(vha->port_name, pinfo->port_name, WWN_SIZE);
1962 vha->d_id.b.domain = pinfo->port_id[0];
1963 vha->d_id.b.area = pinfo->port_id[1];
1964 vha->d_id.b.al_pa = pinfo->port_id[2];
1965 qlafx00_update_host_attr(vha, pinfo);
1966 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
1967 (uint8_t *)pinfo, 16);
1968 } else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
1969 struct qlafx00_tgt_node_info *pinfo =
1970 (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
1971 memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE);
1972 memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
1973 fcport->port_type = FCT_TARGET;
1974 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
1975 (uint8_t *)pinfo, 16);
1976 } else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
1977 struct qlafx00_tgt_node_info *pinfo =
1978 (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
1979 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
1980 (uint8_t *)pinfo, 16);
1981 memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
767157c5
AB		 1982 } else if (fx_type == FXDISC_ABORT_IOCTL)
1983 fdisc->u.fxiocb.result =
b593931d
AB		 1984 (fdisc->u.fxiocb.result ==
1985 cpu_to_le32(QLAFX00_IOCTL_ICOB_ABORT_SUCCESS)) ?
767157c5
AB		 1986 cpu_to_le32(QLA_SUCCESS) : cpu_to_le32(QLA_FUNCTION_FAILED);
1987
1f8deefe 1988 rval = le32_to_cpu(fdisc->u.fxiocb.result);
8ae6d9c7
GM		 1989
1990done_unmap_dma:
1991 if (fdisc->u.fxiocb.rsp_addr)
1992 dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len,
1993 fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle);
1994
1995done_unmap_req:
1996 if (fdisc->u.fxiocb.req_addr)
1997 dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len,
1998 fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle);
1999done_free_sp:
2000 sp->free(vha, sp);
2001done:
2002 return rval;
2003}
2004
8ae6d9c7
GM		 2005/*
2006 * qlafx00_initialize_adapter
2007 * Initialize board.
2008 *
2009 * Input:
2010 * ha = adapter block pointer.
2011 *
2012 * Returns:
2013 * 0 = success
2014 */
2015int
2016qlafx00_initialize_adapter(scsi_qla_host_t *vha)
2017{
2018 int rval;
2019 struct qla_hw_data *ha = vha->hw;
71e56003 2020 uint32_t tempc;
8ae6d9c7
GM		 2021
2022 /* Clear adapter flags. */
2023 vha->flags.online = 0;
2024 ha->flags.chip_reset_done = 0;
2025 vha->flags.reset_active = 0;
2026 ha->flags.pci_channel_io_perm_failure = 0;
2027 ha->flags.eeh_busy = 0;
8ae6d9c7
GM		 2028 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
2029 atomic_set(&vha->loop_state, LOOP_DOWN);
2030 vha->device_flags = DFLG_NO_CABLE;
2031 vha->dpc_flags = 0;
2032 vha->flags.management_server_logged_in = 0;
8ae6d9c7
GM		 2033 ha->isp_abort_cnt = 0;
2034 ha->beacon_blink_led = 0;
2035
2036 set_bit(0, ha->req_qid_map);
2037 set_bit(0, ha->rsp_qid_map);
2038
2039 ql_dbg(ql_dbg_init, vha, 0x0147,
2040 "Configuring PCI space...\n");
2041
2042 rval = ha->isp_ops->pci_config(vha);
2043 if (rval) {
2044 ql_log(ql_log_warn, vha, 0x0148,
2045 "Unable to configure PCI space.\n");
2046 return rval;
2047 }
2048
2049 rval = qlafx00_init_fw_ready(vha);
2050 if (rval != QLA_SUCCESS)
2051 return rval;
2052
2053 qlafx00_save_queue_ptrs(vha);
2054
2055 rval = qlafx00_config_queues(vha);
2056 if (rval != QLA_SUCCESS)
2057 return rval;
2058
2059 /*
2060 * Allocate the array of outstanding commands
2061 * now that we know the firmware resources.
2062 */
2063 rval = qla2x00_alloc_outstanding_cmds(ha, vha->req);
2064 if (rval != QLA_SUCCESS)
2065 return rval;
2066
2067 rval = qla2x00_init_rings(vha);
2068 ha->flags.chip_reset_done = 1;
2069
71e56003
AB		 2070 tempc = QLAFX00_GET_TEMPERATURE(ha);
2071 ql_dbg(ql_dbg_init, vha, 0x0152,
2072 "ISPFx00(%s): Critical temp timer, current SOC temperature: 0x%x\n",
2073 __func__, tempc);
2074
8ae6d9c7
GM		 2075 return rval;
2076}
2077
2078uint32_t
2079qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr,
2080 char *buf)
2081{
2082 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
2083 int rval = QLA_FUNCTION_FAILED;
2084 uint32_t state[1];
2085
2086 if (qla2x00_reset_active(vha))
2087 ql_log(ql_log_warn, vha, 0x70ce,
2088 "ISP reset active.\n");
2089 else if (!vha->hw->flags.eeh_busy) {
2090 rval = qlafx00_get_firmware_state(vha, state);
2091 }
2092 if (rval != QLA_SUCCESS)
2093 memset(state, -1, sizeof(state));
2094
2095 return state[0];
2096}
2097
2098void
2099qlafx00_get_host_speed(struct Scsi_Host *shost)
2100{
2101 struct qla_hw_data *ha = ((struct scsi_qla_host *)
2102 (shost_priv(shost)))->hw;
2103 u32 speed = FC_PORTSPEED_UNKNOWN;
2104
2105 switch (ha->link_data_rate) {
2106 case QLAFX00_PORT_SPEED_2G:
2107 speed = FC_PORTSPEED_2GBIT;
2108 break;
2109 case QLAFX00_PORT_SPEED_4G:
2110 speed = FC_PORTSPEED_4GBIT;
2111 break;
2112 case QLAFX00_PORT_SPEED_8G:
2113 speed = FC_PORTSPEED_8GBIT;
2114 break;
2115 case QLAFX00_PORT_SPEED_10G:
2116 speed = FC_PORTSPEED_10GBIT;
2117 break;
2118 }
2119 fc_host_speed(shost) = speed;
2120}
2121
2122/** QLAFX00 specific ISR implementation functions */
2123
2124static inline void
2125qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
2126 uint32_t sense_len, struct rsp_que *rsp, int res)
2127{
2128 struct scsi_qla_host *vha = sp->fcport->vha;
2129 struct scsi_cmnd *cp = GET_CMD_SP(sp);
2130 uint32_t track_sense_len;
2131
2132 SET_FW_SENSE_LEN(sp, sense_len);
2133
2134 if (sense_len >= SCSI_SENSE_BUFFERSIZE)
2135 sense_len = SCSI_SENSE_BUFFERSIZE;
2136
2137 SET_CMD_SENSE_LEN(sp, sense_len);
2138 SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
2139 track_sense_len = sense_len;
2140
2141 if (sense_len > par_sense_len)
2142 sense_len = par_sense_len;
2143
2144 memcpy(cp->sense_buffer, sense_data, sense_len);
2145
2146 SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len);
2147
2148 SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
2149 track_sense_len -= sense_len;
2150 SET_CMD_SENSE_LEN(sp, track_sense_len);
2151
2152 ql_dbg(ql_dbg_io, vha, 0x304d,
2153 "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n",
2154 sense_len, par_sense_len, track_sense_len);
2155 if (GET_FW_SENSE_LEN(sp) > 0) {
2156 rsp->status_srb = sp;
2157 cp->result = res;
2158 }
2159
2160 if (sense_len) {
2161 ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039,
9cb78c16 2162 "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n",
8ae6d9c7
GM		 2163 sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
2164 cp);
2165 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049,
2166 cp->sense_buffer, sense_len);
2167 }
2168}
2169
2170static void
2171qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
2172 struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp,
1f8deefe 2173 __le16 sstatus, __le16 cpstatus)
8ae6d9c7
GM		 2174{
2175 struct srb_iocb *tmf;
2176
2177 tmf = &sp->u.iocb_cmd;
1f8deefe
SK		 2178 if (cpstatus != cpu_to_le16((uint16_t)CS_COMPLETE) ||
2179 (sstatus & cpu_to_le16((uint16_t)SS_RESPONSE_INFO_LEN_VALID)))
2180 cpstatus = cpu_to_le16((uint16_t)CS_INCOMPLETE);
8ae6d9c7
GM		 2181 tmf->u.tmf.comp_status = cpstatus;
2182 sp->done(vha, sp, 0);
2183}
2184
2185static void
2186qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
2187 struct abort_iocb_entry_fx00 *pkt)
2188{
2189 const char func[] = "ABT_IOCB";
2190 srb_t *sp;
2191 struct srb_iocb *abt;
2192
2193 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2194 if (!sp)
2195 return;
2196
2197 abt = &sp->u.iocb_cmd;
1f8deefe 2198 abt->u.abt.comp_status = pkt->tgt_id_sts;
8ae6d9c7
GM		 2199 sp->done(vha, sp, 0);
2200}
2201
2202static void
2203qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
2204 struct ioctl_iocb_entry_fx00 *pkt)
2205{
2206 const char func[] = "IOSB_IOCB";
2207 srb_t *sp;
2208 struct fc_bsg_job *bsg_job;
2209 struct srb_iocb *iocb_job;
2210 int res;
2211 struct qla_mt_iocb_rsp_fx00 fstatus;
2212 uint8_t *fw_sts_ptr;
2213
2214 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2215 if (!sp)
2216 return;
2217
2218 if (sp->type == SRB_FXIOCB_DCMD) {
2219 iocb_job = &sp->u.iocb_cmd;
1f8deefe
SK		 2220 iocb_job->u.fxiocb.seq_number = pkt->seq_no;
2221 iocb_job->u.fxiocb.fw_flags = pkt->fw_iotcl_flags;
2222 iocb_job->u.fxiocb.result = pkt->status;
8ae6d9c7
GM		 2223 if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID)
2224 iocb_job->u.fxiocb.req_data =
1f8deefe 2225 pkt->dataword_r;
8ae6d9c7
GM		 2226 } else {
2227 bsg_job = sp->u.bsg_job;
2228
2229 memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00));
2230
2231 fstatus.reserved_1 = pkt->reserved_0;
2232 fstatus.func_type = pkt->comp_func_num;
2233 fstatus.ioctl_flags = pkt->fw_iotcl_flags;
2234 fstatus.ioctl_data = pkt->dataword_r;
2235 fstatus.adapid = pkt->adapid;
d68b3e01 2236 fstatus.reserved_2 = pkt->dataword_r_extra;
8ae6d9c7
GM		 2237 fstatus.res_count = pkt->residuallen;
2238 fstatus.status = pkt->status;
2239 fstatus.seq_number = pkt->seq_no;
2240 memcpy(fstatus.reserved_3,
2241 pkt->reserved_2, 20 * sizeof(uint8_t));
2242
2243 fw_sts_ptr = ((uint8_t *)bsg_job->req->sense) +
2244 sizeof(struct fc_bsg_reply);
2245
2246 memcpy(fw_sts_ptr, (uint8_t *)&fstatus,
2247 sizeof(struct qla_mt_iocb_rsp_fx00));
2248 bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
2249 sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
2250
2251 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
2252 sp->fcport->vha, 0x5080,
2253 (uint8_t *)pkt, sizeof(struct ioctl_iocb_entry_fx00));
2254
2255 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
2256 sp->fcport->vha, 0x5074,
2257 (uint8_t *)fw_sts_ptr, sizeof(struct qla_mt_iocb_rsp_fx00));
2258
2259 res = bsg_job->reply->result = DID_OK << 16;
2260 bsg_job->reply->reply_payload_rcv_len =
2261 bsg_job->reply_payload.payload_len;
2262 }
2263 sp->done(vha, sp, res);
2264}
2265
2266/**
2267 * qlafx00_status_entry() - Process a Status IOCB entry.
2268 * @ha: SCSI driver HA context
2269 * @pkt: Entry pointer
2270 */
2271static void
2272qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
2273{
2274 srb_t *sp;
2275 fc_port_t *fcport;
2276 struct scsi_cmnd *cp;
2277 struct sts_entry_fx00 *sts;
1f8deefe
SK		 2278 __le16 comp_status;
2279 __le16 scsi_status;
8ae6d9c7 2280 uint16_t ox_id;
1f8deefe 2281 __le16 lscsi_status;
8ae6d9c7
GM		 2282 int32_t resid;
2283 uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
2284 fw_resid_len;
2285 uint8_t *rsp_info = NULL, *sense_data = NULL;
2286 struct qla_hw_data *ha = vha->hw;
2287 uint32_t hindex, handle;
2288 uint16_t que;
2289 struct req_que *req;
2290 int logit = 1;
2291 int res = 0;
2292
2293 sts = (struct sts_entry_fx00 *) pkt;
2294
1f8deefe
SK		 2295 comp_status = sts->comp_status;
2296 scsi_status = sts->scsi_status & cpu_to_le16((uint16_t)SS_MASK);
8ae6d9c7
GM		 2297 hindex = sts->handle;
2298 handle = LSW(hindex);
2299
2300 que = MSW(hindex);
2301 req = ha->req_q_map[que];
2302
2303 /* Validate handle. */
2304 if (handle < req->num_outstanding_cmds)
2305 sp = req->outstanding_cmds[handle];
2306 else
2307 sp = NULL;
2308
2309 if (sp == NULL) {
2310 ql_dbg(ql_dbg_io, vha, 0x3034,
2311 "Invalid status handle (0x%x).\n", handle);
2312
2313 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2314 qla2xxx_wake_dpc(vha);
2315 return;
2316 }
2317
2318 if (sp->type == SRB_TM_CMD) {
2319 req->outstanding_cmds[handle] = NULL;
2320 qlafx00_tm_iocb_entry(vha, req, pkt, sp,
2321 scsi_status, comp_status);
2322 return;
2323 }
2324
2325 /* Fast path completion. */
2326 if (comp_status == CS_COMPLETE && scsi_status == 0) {
8ae6d9c7
GM		 2327 qla2x00_process_completed_request(vha, req, handle);
2328 return;
2329 }
2330
2331 req->outstanding_cmds[handle] = NULL;
2332 cp = GET_CMD_SP(sp);
2333 if (cp == NULL) {
2334 ql_dbg(ql_dbg_io, vha, 0x3048,
2335 "Command already returned (0x%x/%p).\n",
2336 handle, sp);
2337
2338 return;
2339 }
2340
1f8deefe 2341 lscsi_status = scsi_status & cpu_to_le16((uint16_t)STATUS_MASK);
8ae6d9c7
GM		 2342
2343 fcport = sp->fcport;
2344
2345 ox_id = 0;
2346 sense_len = par_sense_len = rsp_info_len = resid_len =
2347 fw_resid_len = 0;
1f8deefe
SK		 2348 if (scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))
2349 sense_len = sts->sense_len;
2350 if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
2351 | (uint16_t)SS_RESIDUAL_OVER)))
8ae6d9c7 2352 resid_len = le32_to_cpu(sts->residual_len);
1f8deefe 2353 if (comp_status == cpu_to_le16((uint16_t)CS_DATA_UNDERRUN))
8ae6d9c7
GM		 2354 fw_resid_len = le32_to_cpu(sts->residual_len);
2355 rsp_info = sense_data = sts->data;
2356 par_sense_len = sizeof(sts->data);
2357
2358 /* Check for overrun. */
2359 if (comp_status == CS_COMPLETE &&
1f8deefe
SK		 2360 scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_OVER))
2361 comp_status = cpu_to_le16((uint16_t)CS_DATA_OVERRUN);
8ae6d9c7
GM		 2362
2363 /*
2364 * Based on Host and scsi status generate status code for Linux
2365 */
1f8deefe 2366 switch (le16_to_cpu(comp_status)) {
8ae6d9c7
GM		 2367 case CS_COMPLETE:
2368 case CS_QUEUE_FULL:
2369 if (scsi_status == 0) {
2370 res = DID_OK << 16;
2371 break;
2372 }
1f8deefe
SK		 2373 if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
2374 | (uint16_t)SS_RESIDUAL_OVER))) {
8ae6d9c7
GM		 2375 resid = resid_len;
2376 scsi_set_resid(cp, resid);
2377
2378 if (!lscsi_status &&
2379 ((unsigned)(scsi_bufflen(cp) - resid) <
2380 cp->underflow)) {
2381 ql_dbg(ql_dbg_io, fcport->vha, 0x3050,
2382 "Mid-layer underflow "
2383 "detected (0x%x of 0x%x bytes).\n",
2384 resid, scsi_bufflen(cp));
2385
2386 res = DID_ERROR << 16;
2387 break;
2388 }
2389 }
1f8deefe 2390 res = DID_OK << 16 | le16_to_cpu(lscsi_status);
8ae6d9c7 2391
1f8deefe
SK		 2392 if (lscsi_status ==
2393 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
8ae6d9c7
GM		 2394 ql_dbg(ql_dbg_io, fcport->vha, 0x3051,
2395 "QUEUE FULL detected.\n");
2396 break;
2397 }
2398 logit = 0;
1f8deefe 2399 if (lscsi_status != cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
8ae6d9c7
GM		 2400 break;
2401
2402 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
1f8deefe 2403 if (!(scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
8ae6d9c7
GM		 2404 break;
2405
2406 qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len,
2407 rsp, res);
2408 break;
2409
2410 case CS_DATA_UNDERRUN:
2411 /* Use F/W calculated residual length. */
2412 if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
2413 resid = fw_resid_len;
2414 else
2415 resid = resid_len;
2416 scsi_set_resid(cp, resid);
1f8deefe 2417 if (scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_UNDER)) {
8ae6d9c7
GM		 2418 if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
2419 && fw_resid_len != resid_len) {
2420 ql_dbg(ql_dbg_io, fcport->vha, 0x3052,
2421 "Dropped frame(s) detected "
2422 "(0x%x of 0x%x bytes).\n",
2423 resid, scsi_bufflen(cp));
2424
1f8deefe
SK		 2425 res = DID_ERROR << 16 |
2426 le16_to_cpu(lscsi_status);
8ae6d9c7
GM		 2427 goto check_scsi_status;
2428 }
2429
2430 if (!lscsi_status &&
2431 ((unsigned)(scsi_bufflen(cp) - resid) <
2432 cp->underflow)) {
2433 ql_dbg(ql_dbg_io, fcport->vha, 0x3053,
2434 "Mid-layer underflow "
2435 "detected (0x%x of 0x%x bytes, "
2436 "cp->underflow: 0x%x).\n",
2437 resid, scsi_bufflen(cp), cp->underflow);
2438
2439 res = DID_ERROR << 16;
2440 break;
2441 }
1f8deefe
SK		 2442 } else if (lscsi_status !=
2443 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL) &&
2444 lscsi_status != cpu_to_le16((uint16_t)SAM_STAT_BUSY)) {
8ae6d9c7
GM		 2445 /*
2446 * scsi status of task set and busy are considered
2447 * to be task not completed.
2448 */
2449
2450 ql_dbg(ql_dbg_io, fcport->vha, 0x3054,
2451 "Dropped frame(s) detected (0x%x "
2452 "of 0x%x bytes).\n", resid,
2453 scsi_bufflen(cp));
2454
1f8deefe 2455 res = DID_ERROR << 16 | le16_to_cpu(lscsi_status);
8ae6d9c7
GM		 2456 goto check_scsi_status;
2457 } else {
2458 ql_dbg(ql_dbg_io, fcport->vha, 0x3055,
2459 "scsi_status: 0x%x, lscsi_status: 0x%x\n",
2460 scsi_status, lscsi_status);
2461 }
2462
1f8deefe 2463 res = DID_OK << 16 | le16_to_cpu(lscsi_status);
8ae6d9c7
GM		 2464 logit = 0;
2465
2466check_scsi_status:
2467 /*
2468 * Check to see if SCSI Status is non zero. If so report SCSI
2469 * Status.
2470 */
2471 if (lscsi_status != 0) {
1f8deefe
SK		 2472 if (lscsi_status ==
2473 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
8ae6d9c7
GM		 2474 ql_dbg(ql_dbg_io, fcport->vha, 0x3056,
2475 "QUEUE FULL detected.\n");
2476 logit = 1;
2477 break;
2478 }
1f8deefe
SK		 2479 if (lscsi_status !=
2480 cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
8ae6d9c7
GM		 2481 break;
2482
2483 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
1f8deefe
SK		 2484 if (!(scsi_status &
2485 cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
8ae6d9c7
GM		 2486 break;
2487
2488 qlafx00_handle_sense(sp, sense_data, par_sense_len,
2489 sense_len, rsp, res);
2490 }
2491 break;
2492
2493 case CS_PORT_LOGGED_OUT:
2494 case CS_PORT_CONFIG_CHG:
2495 case CS_PORT_BUSY:
2496 case CS_INCOMPLETE:
2497 case CS_PORT_UNAVAILABLE:
2498 case CS_TIMEOUT:
2499 case CS_RESET:
2500
2501 /*
2502 * We are going to have the fc class block the rport
2503 * while we try to recover so instruct the mid layer
2504 * to requeue until the class decides how to handle this.
2505 */
2506 res = DID_TRANSPORT_DISRUPTED << 16;
2507
2508 ql_dbg(ql_dbg_io, fcport->vha, 0x3057,
2509 "Port down status: port-state=0x%x.\n",
2510 atomic_read(&fcport->state));
2511
2512 if (atomic_read(&fcport->state) == FCS_ONLINE)
2513 qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
2514 break;
2515
2516 case CS_ABORTED:
2517 res = DID_RESET << 16;
2518 break;
2519
2520 default:
2521 res = DID_ERROR << 16;
2522 break;
2523 }
2524
2525 if (logit)
2526 ql_dbg(ql_dbg_io, fcport->vha, 0x3058,
9cb78c16 2527 "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu "
7b833558
OK		 2528 "tgt_id: 0x%x lscsi_status: 0x%x cdb=%10phN len=0x%x "
2529 "rsp_info=0x%x resid=0x%x fw_resid=0x%x sense_len=0x%x, "
2530 "par_sense_len=0x%x, rsp_info_len=0x%x\n",
8ae6d9c7
GM		 2531 comp_status, scsi_status, res, vha->host_no,
2532 cp->device->id, cp->device->lun, fcport->tgt_id,
7b833558 2533 lscsi_status, cp->cmnd, scsi_bufflen(cp),
8ae6d9c7
GM		 2534 rsp_info_len, resid_len, fw_resid_len, sense_len,
2535 par_sense_len, rsp_info_len);
2536
8ae6d9c7
GM		 2537 if (rsp->status_srb == NULL)
2538 sp->done(ha, sp, res);
2539}
2540
2541/**
2542 * qlafx00_status_cont_entry() - Process a Status Continuations entry.
2543 * @ha: SCSI driver HA context
2544 * @pkt: Entry pointer
2545 *
2546 * Extended sense data.
2547 */
2548static void
2549qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
2550{
2551 uint8_t sense_sz = 0;
2552 struct qla_hw_data *ha = rsp->hw;
2553 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
2554 srb_t *sp = rsp->status_srb;
2555 struct scsi_cmnd *cp;
2556 uint32_t sense_len;
2557 uint8_t *sense_ptr;
2558
2559 if (!sp) {
2560 ql_dbg(ql_dbg_io, vha, 0x3037,
2561 "no SP, sp = %p\n", sp);
2562 return;
2563 }
2564
2565 if (!GET_FW_SENSE_LEN(sp)) {
2566 ql_dbg(ql_dbg_io, vha, 0x304b,
2567 "no fw sense data, sp = %p\n", sp);
2568 return;
2569 }
2570 cp = GET_CMD_SP(sp);
2571 if (cp == NULL) {
2572 ql_log(ql_log_warn, vha, 0x303b,
2573 "cmd is NULL: already returned to OS (sp=%p).\n", sp);
2574
2575 rsp->status_srb = NULL;
2576 return;
2577 }
2578
2579 if (!GET_CMD_SENSE_LEN(sp)) {
2580 ql_dbg(ql_dbg_io, vha, 0x304c,
2581 "no sense data, sp = %p\n", sp);
2582 } else {
2583 sense_len = GET_CMD_SENSE_LEN(sp);
2584 sense_ptr = GET_CMD_SENSE_PTR(sp);
2585 ql_dbg(ql_dbg_io, vha, 0x304f,
2586 "sp=%p sense_len=0x%x sense_ptr=%p.\n",
2587 sp, sense_len, sense_ptr);
2588
2589 if (sense_len > sizeof(pkt->data))
2590 sense_sz = sizeof(pkt->data);
2591 else
2592 sense_sz = sense_len;
2593
2594 /* Move sense data. */
2595 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
2596 (uint8_t *)pkt, sizeof(sts_cont_entry_t));
2597 memcpy(sense_ptr, pkt->data, sense_sz);
2598 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
2599 sense_ptr, sense_sz);
2600
2601 sense_len -= sense_sz;
2602 sense_ptr += sense_sz;
2603
2604 SET_CMD_SENSE_PTR(sp, sense_ptr);
2605 SET_CMD_SENSE_LEN(sp, sense_len);
2606 }
2607 sense_len = GET_FW_SENSE_LEN(sp);
2608 sense_len = (sense_len > sizeof(pkt->data)) ?
2609 (sense_len - sizeof(pkt->data)) : 0;
2610 SET_FW_SENSE_LEN(sp, sense_len);
2611
2612 /* Place command on done queue. */
2613 if (sense_len == 0) {
2614 rsp->status_srb = NULL;
2615 sp->done(ha, sp, cp->result);
2616 }
2617}
2618
2619/**
2620 * qlafx00_multistatus_entry() - Process Multi response queue entries.
2621 * @ha: SCSI driver HA context
2622 */
2623static void
2624qlafx00_multistatus_entry(struct scsi_qla_host *vha,
2625 struct rsp_que *rsp, void *pkt)
2626{
2627 srb_t *sp;
2628 struct multi_sts_entry_fx00 *stsmfx;
2629 struct qla_hw_data *ha = vha->hw;
2630 uint32_t handle, hindex, handle_count, i;
2631 uint16_t que;
2632 struct req_que *req;
1f8deefe 2633 __le32 *handle_ptr;
8ae6d9c7
GM		 2634
2635 stsmfx = (struct multi_sts_entry_fx00 *) pkt;
2636
2637 handle_count = stsmfx->handle_count;
2638
2639 if (handle_count > MAX_HANDLE_COUNT) {
2640 ql_dbg(ql_dbg_io, vha, 0x3035,
2641 "Invalid handle count (0x%x).\n", handle_count);
2642 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2643 qla2xxx_wake_dpc(vha);
2644 return;
2645 }
2646
1f8deefe 2647 handle_ptr = &stsmfx->handles[0];
8ae6d9c7
GM		 2648
2649 for (i = 0; i < handle_count; i++) {
2650 hindex = le32_to_cpu(*handle_ptr);
2651 handle = LSW(hindex);
2652 que = MSW(hindex);
2653 req = ha->req_q_map[que];
2654
2655 /* Validate handle. */
2656 if (handle < req->num_outstanding_cmds)
2657 sp = req->outstanding_cmds[handle];
2658 else
2659 sp = NULL;
2660
2661 if (sp == NULL) {
2662 ql_dbg(ql_dbg_io, vha, 0x3044,
2663 "Invalid status handle (0x%x).\n", handle);
2664 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2665 qla2xxx_wake_dpc(vha);
2666 return;
2667 }
2668 qla2x00_process_completed_request(vha, req, handle);
2669 handle_ptr++;
2670 }
2671}
2672
2673/**
2674 * qlafx00_error_entry() - Process an error entry.
2675 * @ha: SCSI driver HA context
2676 * @pkt: Entry pointer
2677 */
2678static void
2679qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp,
2680 struct sts_entry_fx00 *pkt, uint8_t estatus, uint8_t etype)
2681{
2682 srb_t *sp;
2683 struct qla_hw_data *ha = vha->hw;
2684 const char func[] = "ERROR-IOCB";
d550dd27 2685 uint16_t que = 0;
8ae6d9c7
GM		 2686 struct req_que *req = NULL;
2687 int res = DID_ERROR << 16;
2688
2689 ql_dbg(ql_dbg_async, vha, 0x507f,
2690 "type of error status in response: 0x%x\n", estatus);
2691
2692 req = ha->req_q_map[que];
2693
2694 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2695 if (sp) {
2696 sp->done(ha, sp, res);
2697 return;
2698 }
2699
2700 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2701 qla2xxx_wake_dpc(vha);
2702}
2703
2704/**
2705 * qlafx00_process_response_queue() - Process response queue entries.
2706 * @ha: SCSI driver HA context
2707 */
2708static void
2709qlafx00_process_response_queue(struct scsi_qla_host *vha,
2710 struct rsp_que *rsp)
2711{
2712 struct sts_entry_fx00 *pkt;
2713 response_t *lptr;
6ac1f3b5
SK		 2714 uint16_t lreq_q_in = 0;
2715 uint16_t lreq_q_out = 0;
8ae6d9c7 2716
6ac1f3b5 2717 lreq_q_in = RD_REG_DWORD(rsp->rsp_q_in);
9929c478 2718 lreq_q_out = rsp->ring_index;
6ac1f3b5
SK		 2719
2720 while (lreq_q_in != lreq_q_out) {
8ae6d9c7 2721 lptr = rsp->ring_ptr;
1f8deefe
SK		 2722 memcpy_fromio(rsp->rsp_pkt, (void __iomem *)lptr,
2723 sizeof(rsp->rsp_pkt));
8ae6d9c7
GM		 2724 pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt;
2725
2726 rsp->ring_index++;
6ac1f3b5 2727 lreq_q_out++;
8ae6d9c7 2728 if (rsp->ring_index == rsp->length) {
6ac1f3b5 2729 lreq_q_out = 0;
8ae6d9c7
GM		 2730 rsp->ring_index = 0;
2731 rsp->ring_ptr = rsp->ring;
2732 } else {
2733 rsp->ring_ptr++;
2734 }
2735
2736 if (pkt->entry_status != 0 &&
2737 pkt->entry_type != IOCTL_IOSB_TYPE_FX00) {
2738 qlafx00_error_entry(vha, rsp,
2739 (struct sts_entry_fx00 *)pkt, pkt->entry_status,
2740 pkt->entry_type);
8ae6d9c7
GM		 2741 continue;
2742 }
2743
2744 switch (pkt->entry_type) {
2745 case STATUS_TYPE_FX00:
2746 qlafx00_status_entry(vha, rsp, pkt);
2747 break;
2748
2749 case STATUS_CONT_TYPE_FX00:
2750 qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
2751 break;
2752
2753 case MULTI_STATUS_TYPE_FX00:
2754 qlafx00_multistatus_entry(vha, rsp, pkt);
2755 break;
2756
2757 case ABORT_IOCB_TYPE_FX00:
2758 qlafx00_abort_iocb_entry(vha, rsp->req,
2759 (struct abort_iocb_entry_fx00 *)pkt);
2760 break;
2761
2762 case IOCTL_IOSB_TYPE_FX00:
2763 qlafx00_ioctl_iosb_entry(vha, rsp->req,
2764 (struct ioctl_iocb_entry_fx00 *)pkt);
2765 break;
2766 default:
2767 /* Type Not Supported. */
2768 ql_dbg(ql_dbg_async, vha, 0x5081,
2769 "Received unknown response pkt type %x "
2770 "entry status=%x.\n",
2771 pkt->entry_type, pkt->entry_status);
2772 break;
2773 }
8ae6d9c7
GM		 2774 }
2775
2776 /* Adjust ring index */
2777 WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
2778}
2779
2780/**
2781 * qlafx00_async_event() - Process aynchronous events.
2782 * @ha: SCSI driver HA context
2783 */
2784static void
2785qlafx00_async_event(scsi_qla_host_t *vha)
2786{
2787 struct qla_hw_data *ha = vha->hw;
2788 struct device_reg_fx00 __iomem *reg;
2789 int data_size = 1;
2790
2791 reg = &ha->iobase->ispfx00;
2792 /* Setup to process RIO completion. */
2793 switch (ha->aenmb[0]) {
2794 case QLAFX00_MBA_SYSTEM_ERR: /* System Error */
2795 ql_log(ql_log_warn, vha, 0x5079,
2796 "ISP System Error - mbx1=%x\n", ha->aenmb[0]);
2797 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2798 break;
2799
2800 case QLAFX00_MBA_SHUTDOWN_RQSTD: /* Shutdown requested */
2801 ql_dbg(ql_dbg_async, vha, 0x5076,
2802 "Asynchronous FW shutdown requested.\n");
2803 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2804 qla2xxx_wake_dpc(vha);
2805 break;
2806
2807 case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
965c77a6
SK		 2808 ha->aenmb[1] = RD_REG_DWORD(&reg->aenmailbox1);
2809 ha->aenmb[2] = RD_REG_DWORD(&reg->aenmailbox2);
2810 ha->aenmb[3] = RD_REG_DWORD(&reg->aenmailbox3);
8ae6d9c7
GM		 2811 ql_dbg(ql_dbg_async, vha, 0x5077,
2812 "Asynchronous port Update received "
2813 "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n",
2814 ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]);
2815 data_size = 4;
2816 break;
71e56003
AB		 2817
2818 case QLAFX00_MBA_TEMP_OVER: /* Over temperature event */
4881d095
AB		 2819 ql_log(ql_log_info, vha, 0x5085,
2820 "Asynchronous over temperature event received "
2821 "aenmb[0]: %x\n",
2822 ha->aenmb[0]);
2823 break;
2824
2825 case QLAFX00_MBA_TEMP_NORM: /* Normal temperature event */
2826 ql_log(ql_log_info, vha, 0x5086,
2827 "Asynchronous normal temperature event received "
2828 "aenmb[0]: %x\n",
2829 ha->aenmb[0]);
2830 break;
2831
71e56003
AB		 2832 case QLAFX00_MBA_TEMP_CRIT: /* Critical temperature event */
2833 ql_log(ql_log_info, vha, 0x5083,
2834 "Asynchronous critical temperature event received "
2835 "aenmb[0]: %x\n",
2836 ha->aenmb[0]);
71e56003
AB		 2837 break;
2838
8ae6d9c7
GM		 2839 default:
2840 ha->aenmb[1] = RD_REG_WORD(&reg->aenmailbox1);
2841 ha->aenmb[2] = RD_REG_WORD(&reg->aenmailbox2);
2842 ha->aenmb[3] = RD_REG_WORD(&reg->aenmailbox3);
2843 ha->aenmb[4] = RD_REG_WORD(&reg->aenmailbox4);
2844 ha->aenmb[5] = RD_REG_WORD(&reg->aenmailbox5);
2845 ha->aenmb[6] = RD_REG_WORD(&reg->aenmailbox6);
2846 ha->aenmb[7] = RD_REG_WORD(&reg->aenmailbox7);
2847 ql_dbg(ql_dbg_async, vha, 0x5078,
2848 "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n",
2849 ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3],
2850 ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]);
2851 break;
2852 }
2853 qlafx00_post_aenfx_work(vha, ha->aenmb[0],
2854 (uint32_t *)ha->aenmb, data_size);
2855}
2856
2857/**
2858 *
2859 * qlafx00x_mbx_completion() - Process mailbox command completions.
2860 * @ha: SCSI driver HA context
2861 * @mb16: Mailbox16 register
2862 */
2863static void
2864qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0)
2865{
2866 uint16_t cnt;
965c77a6 2867 uint32_t __iomem *wptr;
8ae6d9c7
GM		 2868 struct qla_hw_data *ha = vha->hw;
2869 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
2870
2871 if (!ha->mcp32)
2872 ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n");
2873
2874 /* Load return mailbox registers. */
2875 ha->flags.mbox_int = 1;
2876 ha->mailbox_out32[0] = mb0;
965c77a6 2877 wptr = (uint32_t __iomem *)&reg->mailbox17;
8ae6d9c7
GM		 2878
2879 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
965c77a6 2880 ha->mailbox_out32[cnt] = RD_REG_DWORD(wptr);
8ae6d9c7
GM		 2881 wptr++;
2882 }
2883}
2884
2885/**
2886 * qlafx00_intr_handler() - Process interrupts for the ISPFX00.
2887 * @irq:
2888 * @dev_id: SCSI driver HA context
2889 *
2890 * Called by system whenever the host adapter generates an interrupt.
2891 *
2892 * Returns handled flag.
2893 */
2894irqreturn_t
2895qlafx00_intr_handler(int irq, void *dev_id)
2896{
2897 scsi_qla_host_t *vha;
2898 struct qla_hw_data *ha;
2899 struct device_reg_fx00 __iomem *reg;
2900 int status;
2901 unsigned long iter;
2902 uint32_t stat;
2903 uint32_t mb[8];
2904 struct rsp_que *rsp;
2905 unsigned long flags;
2906 uint32_t clr_intr = 0;
fbe9c54b 2907 uint32_t intr_stat = 0;
8ae6d9c7
GM		 2908
2909 rsp = (struct rsp_que *) dev_id;
2910 if (!rsp) {
2911 ql_log(ql_log_info, NULL, 0x507d,
2912 "%s: NULL response queue pointer.\n", __func__);
2913 return IRQ_NONE;
2914 }
2915
2916 ha = rsp->hw;
2917 reg = &ha->iobase->ispfx00;
2918 status = 0;
2919
2920 if (unlikely(pci_channel_offline(ha->pdev)))
2921 return IRQ_HANDLED;
2922
2923 spin_lock_irqsave(&ha->hardware_lock, flags);
2924 vha = pci_get_drvdata(ha->pdev);
2925 for (iter = 50; iter--; clr_intr = 0) {
2926 stat = QLAFX00_RD_INTR_REG(ha);
f3ddac19
CD		 2927 if (qla2x00_check_reg_for_disconnect(vha, stat))
2928 break;
fbe9c54b
SK		 2929 intr_stat = stat & QLAFX00_HST_INT_STS_BITS;
2930 if (!intr_stat)
8ae6d9c7
GM		 2931 break;
2932
fbe9c54b 2933 if (stat & QLAFX00_INTR_MB_CMPLT) {
8ae6d9c7
GM		 2934 mb[0] = RD_REG_WORD(&reg->mailbox16);
2935 qlafx00_mbx_completion(vha, mb[0]);
2936 status |= MBX_INTERRUPT;
2937 clr_intr |= QLAFX00_INTR_MB_CMPLT;
fbe9c54b
SK		 2938 }
2939 if (intr_stat & QLAFX00_INTR_ASYNC_CMPLT) {
8ae6d9c7
GM		 2940 ha->aenmb[0] = RD_REG_WORD(&reg->aenmailbox0);
2941 qlafx00_async_event(vha);
2942 clr_intr |= QLAFX00_INTR_ASYNC_CMPLT;
fbe9c54b
SK		 2943 }
2944 if (intr_stat & QLAFX00_INTR_RSP_CMPLT) {
8ae6d9c7
GM		 2945 qlafx00_process_response_queue(vha, rsp);
2946 clr_intr |= QLAFX00_INTR_RSP_CMPLT;
8ae6d9c7 2947 }
fbe9c54b 2948
8ae6d9c7
GM		 2949 QLAFX00_CLR_INTR_REG(ha, clr_intr);
2950 QLAFX00_RD_INTR_REG(ha);
2951 }
36439832 2952
2953 qla2x00_handle_mbx_completion(ha, status);
8ae6d9c7
GM		 2954 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2955
8ae6d9c7
GM		 2956 return IRQ_HANDLED;
2957}
2958
2959/** QLAFX00 specific IOCB implementation functions */
2960
2961static inline cont_a64_entry_t *
2962qlafx00_prep_cont_type1_iocb(struct req_que *req,
2963 cont_a64_entry_t *lcont_pkt)
2964{
2965 cont_a64_entry_t *cont_pkt;
2966
2967 /* Adjust ring index. */
2968 req->ring_index++;
2969 if (req->ring_index == req->length) {
2970 req->ring_index = 0;
2971 req->ring_ptr = req->ring;
2972 } else {
2973 req->ring_ptr++;
2974 }
2975
2976 cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
2977
2978 /* Load packet defaults. */
1f8deefe 2979 lcont_pkt->entry_type = CONTINUE_A64_TYPE_FX00;
8ae6d9c7
GM		 2980
2981 return cont_pkt;
2982}
2983
2984static inline void
2985qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
2986 uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt)
2987{
2988 uint16_t avail_dsds;
1f8deefe 2989 __le32 *cur_dsd;
8ae6d9c7
GM		 2990 scsi_qla_host_t *vha;
2991 struct scsi_cmnd *cmd;
2992 struct scatterlist *sg;
2993 int i, cont;
2994 struct req_que *req;
2995 cont_a64_entry_t lcont_pkt;
2996 cont_a64_entry_t *cont_pkt;
2997
2998 vha = sp->fcport->vha;
2999 req = vha->req;
3000
3001 cmd = GET_CMD_SP(sp);
3002 cont = 0;
3003 cont_pkt = NULL;
3004
3005 /* Update entry type to indicate Command Type 3 IOCB */
1f8deefe 3006 lcmd_pkt->entry_type = FX00_COMMAND_TYPE_7;
8ae6d9c7
GM		 3007
3008 /* No data transfer */
3009 if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
3010 lcmd_pkt->byte_count = __constant_cpu_to_le32(0);
3011 return;
3012 }
3013
3014 /* Set transfer direction */
3015 if (cmd->sc_data_direction == DMA_TO_DEVICE) {
378c538d 3016 lcmd_pkt->cntrl_flags = TMF_WRITE_DATA;
8ae6d9c7
GM		 3017 vha->qla_stats.output_bytes += scsi_bufflen(cmd);
3018 } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
378c538d 3019 lcmd_pkt->cntrl_flags = TMF_READ_DATA;
8ae6d9c7
GM		 3020 vha->qla_stats.input_bytes += scsi_bufflen(cmd);
3021 }
3022
3023 /* One DSD is available in the Command Type 3 IOCB */
3024 avail_dsds = 1;
1f8deefe 3025 cur_dsd = (__le32 *)&lcmd_pkt->dseg_0_address;
8ae6d9c7
GM		 3026
3027 /* Load data segments */
3028 scsi_for_each_sg(cmd, sg, tot_dsds, i) {
3029 dma_addr_t sle_dma;
3030
3031 /* Allocate additional continuation packets? */
3032 if (avail_dsds == 0) {
3033 /*
3034 * Five DSDs are available in the Continuation
3035 * Type 1 IOCB.
3036 */
3037 memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE);
3038 cont_pkt =
3039 qlafx00_prep_cont_type1_iocb(req, &lcont_pkt);
1f8deefe 3040 cur_dsd = (__le32 *)lcont_pkt.dseg_0_address;
8ae6d9c7
GM		 3041 avail_dsds = 5;
3042 cont = 1;
3043 }
3044
3045 sle_dma = sg_dma_address(sg);
3046 *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
3047 *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
3048 *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
3049 avail_dsds--;
3050 if (avail_dsds == 0 && cont == 1) {
3051 cont = 0;
3052 memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
3053 REQUEST_ENTRY_SIZE);
3054 }
3055
3056 }
3057 if (avail_dsds != 0 && cont == 1) {
3058 memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
3059 REQUEST_ENTRY_SIZE);
3060 }
3061}
3062
3063/**
3064 * qlafx00_start_scsi() - Send a SCSI command to the ISP
3065 * @sp: command to send to the ISP
3066 *
3067 * Returns non-zero if a failure occurred, else zero.
3068 */
3069int
3070qlafx00_start_scsi(srb_t *sp)
3071{
3072 int ret, nseg;
3073 unsigned long flags;
3074 uint32_t index;
3075 uint32_t handle;
3076 uint16_t cnt;
3077 uint16_t req_cnt;
3078 uint16_t tot_dsds;
3079 struct req_que *req = NULL;
3080 struct rsp_que *rsp = NULL;
3081 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
3082 struct scsi_qla_host *vha = sp->fcport->vha;
3083 struct qla_hw_data *ha = vha->hw;
3084 struct cmd_type_7_fx00 *cmd_pkt;
3085 struct cmd_type_7_fx00 lcmd_pkt;
3086 struct scsi_lun llun;
3087 char tag[2];
3088
3089 /* Setup device pointers. */
3090 ret = 0;
3091
3092 rsp = ha->rsp_q_map[0];
3093 req = vha->req;
3094
3095 /* So we know we haven't pci_map'ed anything yet */
3096 tot_dsds = 0;
3097
8ae6d9c7
GM		 3098 /* Acquire ring specific lock */
3099 spin_lock_irqsave(&ha->hardware_lock, flags);
3100
3101 /* Check for room in outstanding command list. */
3102 handle = req->current_outstanding_cmd;
3103 for (index = 1; index < req->num_outstanding_cmds; index++) {
3104 handle++;
3105 if (handle == req->num_outstanding_cmds)
3106 handle = 1;
3107 if (!req->outstanding_cmds[handle])
3108 break;
3109 }
3110 if (index == req->num_outstanding_cmds)
3111 goto queuing_error;
3112
3113 /* Map the sg table so we have an accurate count of sg entries needed */
3114 if (scsi_sg_count(cmd)) {
3115 nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
3116 scsi_sg_count(cmd), cmd->sc_data_direction);
3117 if (unlikely(!nseg))
3118 goto queuing_error;
3119 } else
3120 nseg = 0;
3121
3122 tot_dsds = nseg;
3123 req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);
3124 if (req->cnt < (req_cnt + 2)) {
3125 cnt = RD_REG_DWORD_RELAXED(req->req_q_out);
3126
3127 if (req->ring_index < cnt)
3128 req->cnt = cnt - req->ring_index;
3129 else
3130 req->cnt = req->length -
3131 (req->ring_index - cnt);
3132 if (req->cnt < (req_cnt + 2))
3133 goto queuing_error;
3134 }
3135
3136 /* Build command packet. */
3137 req->current_outstanding_cmd = handle;
3138 req->outstanding_cmds[handle] = sp;
3139 sp->handle = handle;
3140 cmd->host_scribble = (unsigned char *)(unsigned long)handle;
3141 req->cnt -= req_cnt;
3142
3143 cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr;
3144
3145 memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE);
3146
3147 lcmd_pkt.handle = MAKE_HANDLE(req->id, sp->handle);
d68b3e01
AB		 3148 lcmd_pkt.reserved_0 = 0;
3149 lcmd_pkt.port_path_ctrl = 0;
3150 lcmd_pkt.reserved_1 = 0;
8ae6d9c7
GM		 3151 lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds);
3152 lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id);
3153
3154 int_to_scsilun(cmd->device->lun, &llun);
3155 host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun,
3156 sizeof(lcmd_pkt.lun));
3157
3158 /* Update tagged queuing modifier -- default is TSK_SIMPLE (0). */
3159 if (scsi_populate_tag_msg(cmd, tag)) {
3160 switch (tag[0]) {
3161 case HEAD_OF_QUEUE_TAG:
3162 lcmd_pkt.task = TSK_HEAD_OF_QUEUE;
3163 break;
3164 case ORDERED_QUEUE_TAG:
3165 lcmd_pkt.task = TSK_ORDERED;
3166 break;
3167 }
3168 }
3169
3170 /* Load SCSI command packet. */
3171 host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb));
3172 lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
3173
3174 /* Build IOCB segments */
3175 qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt);
3176
3177 /* Set total data segment count. */
3178 lcmd_pkt.entry_count = (uint8_t)req_cnt;
3179
3180 /* Specify response queue number where completion should happen */
3181 lcmd_pkt.entry_status = (uint8_t) rsp->id;
3182
3183 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
3184 (uint8_t *)cmd->cmnd, cmd->cmd_len);
3185 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
3186 (uint8_t *)&lcmd_pkt, REQUEST_ENTRY_SIZE);
3187
3188 memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
3189 wmb();
3190
3191 /* Adjust ring index. */
3192 req->ring_index++;
3193 if (req->ring_index == req->length) {
3194 req->ring_index = 0;
3195 req->ring_ptr = req->ring;
3196 } else
3197 req->ring_ptr++;
3198
3199 sp->flags |= SRB_DMA_VALID;
3200
3201 /* Set chip new ring index. */
3202 WRT_REG_DWORD(req->req_q_in, req->ring_index);
3203 QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code);
3204
3205 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3206 return QLA_SUCCESS;
3207
3208queuing_error:
3209 if (tot_dsds)
3210 scsi_dma_unmap(cmd);
3211
3212 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3213
3214 return QLA_FUNCTION_FAILED;
3215}
3216
3217void
3218qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb)
3219{
3220 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3221 scsi_qla_host_t *vha = sp->fcport->vha;
3222 struct req_que *req = vha->req;
3223 struct tsk_mgmt_entry_fx00 tm_iocb;
3224 struct scsi_lun llun;
3225
3226 memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00));
3227 tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00;
3228 tm_iocb.entry_count = 1;
3229 tm_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
d68b3e01 3230 tm_iocb.reserved_0 = 0;
8ae6d9c7
GM		 3231 tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id);
3232 tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags);
1f8deefe 3233 if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) {
8ae6d9c7
GM		 3234 int_to_scsilun(fxio->u.tmf.lun, &llun);
3235 host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun,
3236 sizeof(struct scsi_lun));
3237 }
3238
1f8deefe 3239 memcpy((void *)ptm_iocb, &tm_iocb,
8ae6d9c7
GM		 3240 sizeof(struct tsk_mgmt_entry_fx00));
3241 wmb();
3242}
3243
3244void
3245qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb)
3246{
3247 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3248 scsi_qla_host_t *vha = sp->fcport->vha;
3249 struct req_que *req = vha->req;
3250 struct abort_iocb_entry_fx00 abt_iocb;
3251
3252 memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00));
3253 abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00;
3254 abt_iocb.entry_count = 1;
3255 abt_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
3256 abt_iocb.abort_handle =
3257 cpu_to_le32(MAKE_HANDLE(req->id, fxio->u.abt.cmd_hndl));
3258 abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id);
3259 abt_iocb.req_que_no = cpu_to_le16(req->id);
3260
1f8deefe 3261 memcpy((void *)pabt_iocb, &abt_iocb,
8ae6d9c7
GM		 3262 sizeof(struct abort_iocb_entry_fx00));
3263 wmb();
3264}
3265
3266void
3267qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
3268{
3269 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3270 struct qla_mt_iocb_rqst_fx00 *piocb_rqst;
3271 struct fc_bsg_job *bsg_job;
3272 struct fxdisc_entry_fx00 fx_iocb;
3273 uint8_t entry_cnt = 1;
3274
3275 memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00));
3276 fx_iocb.entry_type = FX00_IOCB_TYPE;
3277 fx_iocb.handle = cpu_to_le32(sp->handle);
3278 fx_iocb.entry_count = entry_cnt;
3279
3280 if (sp->type == SRB_FXIOCB_DCMD) {
3281 fx_iocb.func_num =
1f8deefe
SK		 3282 sp->u.iocb_cmd.u.fxiocb.req_func_type;
3283 fx_iocb.adapid = fxio->u.fxiocb.adapter_id;
3284 fx_iocb.adapid_hi = fxio->u.fxiocb.adapter_id_hi;
3285 fx_iocb.reserved_0 = fxio->u.fxiocb.reserved_0;
3286 fx_iocb.reserved_1 = fxio->u.fxiocb.reserved_1;
3287 fx_iocb.dataword_extra = fxio->u.fxiocb.req_data_extra;
8ae6d9c7
GM		 3288
3289 if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
3290 fx_iocb.req_dsdcnt = cpu_to_le16(1);
3291 fx_iocb.req_xfrcnt =
3292 cpu_to_le16(fxio->u.fxiocb.req_len);
3293 fx_iocb.dseg_rq_address[0] =
3294 cpu_to_le32(LSD(fxio->u.fxiocb.req_dma_handle));
3295 fx_iocb.dseg_rq_address[1] =
3296 cpu_to_le32(MSD(fxio->u.fxiocb.req_dma_handle));
3297 fx_iocb.dseg_rq_len =
3298 cpu_to_le32(fxio->u.fxiocb.req_len);
3299 }
3300
3301 if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
3302 fx_iocb.rsp_dsdcnt = cpu_to_le16(1);
3303 fx_iocb.rsp_xfrcnt =
3304 cpu_to_le16(fxio->u.fxiocb.rsp_len);
3305 fx_iocb.dseg_rsp_address[0] =
3306 cpu_to_le32(LSD(fxio->u.fxiocb.rsp_dma_handle));
3307 fx_iocb.dseg_rsp_address[1] =
3308 cpu_to_le32(MSD(fxio->u.fxiocb.rsp_dma_handle));
3309 fx_iocb.dseg_rsp_len =
3310 cpu_to_le32(fxio->u.fxiocb.rsp_len);
3311 }
3312
3313 if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) {
1f8deefe 3314 fx_iocb.dataword = fxio->u.fxiocb.req_data;
8ae6d9c7
GM		 3315 }
3316 fx_iocb.flags = fxio->u.fxiocb.flags;
3317 } else {
3318 struct scatterlist *sg;
3319 bsg_job = sp->u.bsg_job;
3320 piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *)
3321 &bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
3322
3323 fx_iocb.func_num = piocb_rqst->func_type;
3324 fx_iocb.adapid = piocb_rqst->adapid;
3325 fx_iocb.adapid_hi = piocb_rqst->adapid_hi;
3326 fx_iocb.reserved_0 = piocb_rqst->reserved_0;
3327 fx_iocb.reserved_1 = piocb_rqst->reserved_1;
3328 fx_iocb.dataword_extra = piocb_rqst->dataword_extra;
3329 fx_iocb.dataword = piocb_rqst->dataword;
1f8deefe
SK		 3330 fx_iocb.req_xfrcnt = piocb_rqst->req_len;
3331 fx_iocb.rsp_xfrcnt = piocb_rqst->rsp_len;
8ae6d9c7
GM		 3332
3333 if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) {
3334 int avail_dsds, tot_dsds;
3335 cont_a64_entry_t lcont_pkt;
3336 cont_a64_entry_t *cont_pkt = NULL;
1f8deefe 3337 __le32 *cur_dsd;
8ae6d9c7
GM		 3338 int index = 0, cont = 0;
3339
3340 fx_iocb.req_dsdcnt =
3341 cpu_to_le16(bsg_job->request_payload.sg_cnt);
3342 tot_dsds =
1f8deefe
SK		 3343 bsg_job->request_payload.sg_cnt;
3344 cur_dsd = (__le32 *)&fx_iocb.dseg_rq_address[0];
8ae6d9c7
GM		 3345 avail_dsds = 1;
3346 for_each_sg(bsg_job->request_payload.sg_list, sg,
3347 tot_dsds, index) {
3348 dma_addr_t sle_dma;
3349
3350 /* Allocate additional continuation packets? */
3351 if (avail_dsds == 0) {
3352 /*
3353 * Five DSDs are available in the Cont.
3354 * Type 1 IOCB.
3355 */
3356 memset(&lcont_pkt, 0,
3357 REQUEST_ENTRY_SIZE);
3358 cont_pkt =
3359 qlafx00_prep_cont_type1_iocb(
3360 sp->fcport->vha->req,
3361 &lcont_pkt);
1f8deefe 3362 cur_dsd = (__le32 *)
8ae6d9c7
GM		 3363 lcont_pkt.dseg_0_address;
3364 avail_dsds = 5;
3365 cont = 1;
3366 entry_cnt++;
3367 }
3368
3369 sle_dma = sg_dma_address(sg);
3370 *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
3371 *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
3372 *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
3373 avail_dsds--;
3374
3375 if (avail_dsds == 0 && cont == 1) {
3376 cont = 0;
3377 memcpy_toio(
3378 (void __iomem *)cont_pkt,
3379 &lcont_pkt, REQUEST_ENTRY_SIZE);
3380 ql_dump_buffer(
3381 ql_dbg_user + ql_dbg_verbose,
3382 sp->fcport->vha, 0x3042,
3383 (uint8_t *)&lcont_pkt,
3384 REQUEST_ENTRY_SIZE);
3385 }
3386 }
3387 if (avail_dsds != 0 && cont == 1) {
3388 memcpy_toio((void __iomem *)cont_pkt,
3389 &lcont_pkt, REQUEST_ENTRY_SIZE);
3390 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3391 sp->fcport->vha, 0x3043,
3392 (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
3393 }
3394 }
3395
3396 if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) {
3397 int avail_dsds, tot_dsds;
3398 cont_a64_entry_t lcont_pkt;
3399 cont_a64_entry_t *cont_pkt = NULL;
1f8deefe 3400 __le32 *cur_dsd;
8ae6d9c7
GM		 3401 int index = 0, cont = 0;
3402
3403 fx_iocb.rsp_dsdcnt =
3404 cpu_to_le16(bsg_job->reply_payload.sg_cnt);
1f8deefe
SK		 3405 tot_dsds = bsg_job->reply_payload.sg_cnt;
3406 cur_dsd = (__le32 *)&fx_iocb.dseg_rsp_address[0];
8ae6d9c7
GM		 3407 avail_dsds = 1;
3408
3409 for_each_sg(bsg_job->reply_payload.sg_list, sg,
3410 tot_dsds, index) {
3411 dma_addr_t sle_dma;
3412
3413 /* Allocate additional continuation packets? */
3414 if (avail_dsds == 0) {
3415 /*
3416 * Five DSDs are available in the Cont.
3417 * Type 1 IOCB.
3418 */
3419 memset(&lcont_pkt, 0,
3420 REQUEST_ENTRY_SIZE);
3421 cont_pkt =
3422 qlafx00_prep_cont_type1_iocb(
3423 sp->fcport->vha->req,
3424 &lcont_pkt);
1f8deefe 3425 cur_dsd = (__le32 *)
8ae6d9c7
GM		 3426 lcont_pkt.dseg_0_address;
3427 avail_dsds = 5;
3428 cont = 1;
3429 entry_cnt++;
3430 }
3431
3432 sle_dma = sg_dma_address(sg);
3433 *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
3434 *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
3435 *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
3436 avail_dsds--;
3437
3438 if (avail_dsds == 0 && cont == 1) {
3439 cont = 0;
3440 memcpy_toio((void __iomem *)cont_pkt,
3441 &lcont_pkt,
3442 REQUEST_ENTRY_SIZE);
3443 ql_dump_buffer(
3444 ql_dbg_user + ql_dbg_verbose,
3445 sp->fcport->vha, 0x3045,
3446 (uint8_t *)&lcont_pkt,
3447 REQUEST_ENTRY_SIZE);
3448 }
3449 }
3450 if (avail_dsds != 0 && cont == 1) {
3451 memcpy_toio((void __iomem *)cont_pkt,
3452 &lcont_pkt, REQUEST_ENTRY_SIZE);
3453 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3454 sp->fcport->vha, 0x3046,
3455 (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
3456 }
3457 }
3458
3459 if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID)
1f8deefe 3460 fx_iocb.dataword = piocb_rqst->dataword;
8ae6d9c7
GM		 3461 fx_iocb.flags = piocb_rqst->flags;
3462 fx_iocb.entry_count = entry_cnt;
3463 }
3464
3465 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3466 sp->fcport->vha, 0x3047,
3467 (uint8_t *)&fx_iocb, sizeof(struct fxdisc_entry_fx00));
3468
f79a84bf 3469 memcpy_toio((void __iomem *)pfxiocb, &fx_iocb,
8ae6d9c7
GM		 3470 sizeof(struct fxdisc_entry_fx00));
3471 wmb();
3472}
Linux 6.x block layer and io_uring tree(s)