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[SCSI] qla2xxx: Do link initialization on get loop id failure.
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_mbx.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
46152ceb 3 * Copyright (c) 2003-2012 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
2d70c103 8#include "qla_target.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/gfp.h>
1da177e4 12
1da177e4
LT		 13
14/*
15 * qla2x00_mailbox_command
16 * Issue mailbox command and waits for completion.
17 *
18 * Input:
19 * ha = adapter block pointer.
20 * mcp = driver internal mbx struct pointer.
21 *
22 * Output:
23 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
24 *
25 * Returns:
26 * 0 : QLA_SUCCESS = cmd performed success
27 * 1 : QLA_FUNCTION_FAILED (error encountered)
28 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
29 *
30 * Context:
31 * Kernel context.
32 */
33static int
7b867cf7 34qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
1da177e4
LT		 35{
36 int rval;
37 unsigned long flags = 0;
2c3dfe3f 38 device_reg_t __iomem *reg;
1c7c6357 39 uint8_t abort_active;
2c3dfe3f 40 uint8_t io_lock_on;
cdbb0a4f 41 uint16_t command = 0;
1da177e4
LT		 42 uint16_t *iptr;
43 uint16_t __iomem *optr;
44 uint32_t cnt;
45 uint32_t mboxes;
1da177e4 46 unsigned long wait_time;
7b867cf7
AC		 47 struct qla_hw_data *ha = vha->hw;
48 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f 49
5e19ed90 50 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
7c3df132
SK		 51
52 if (ha->pdev->error_state > pci_channel_io_frozen) {
5e19ed90 53 ql_log(ql_log_warn, vha, 0x1001,
7c3df132
SK		 54 "error_state is greater than pci_channel_io_frozen, "
55 "exiting.\n");
b9b12f73 56 return QLA_FUNCTION_TIMEOUT;
7c3df132 57 }
b9b12f73 58
a9083016 59 if (vha->device_flags & DFLG_DEV_FAILED) {
5e19ed90 60 ql_log(ql_log_warn, vha, 0x1002,
7c3df132 61 "Device in failed state, exiting.\n");
a9083016
GM		 62 return QLA_FUNCTION_TIMEOUT;
63 }
64
2c3dfe3f 65 reg = ha->iobase;
7b867cf7 66 io_lock_on = base_vha->flags.init_done;
1da177e4
LT		 67
68 rval = QLA_SUCCESS;
7b867cf7 69 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1c7c6357 70
1da177e4 71
85880801 72 if (ha->flags.pci_channel_io_perm_failure) {
5e19ed90 73 ql_log(ql_log_warn, vha, 0x1003,
7c3df132 74 "Perm failure on EEH timeout MBX, exiting.\n");
85880801
AV		 75 return QLA_FUNCTION_TIMEOUT;
76 }
77
7d613ac6 78 if (IS_QLA82XX(ha) && ha->flags.isp82xx_fw_hung) {
862cd01e
GM		 79 /* Setting Link-Down error */
80 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
5e19ed90 81 ql_log(ql_log_warn, vha, 0x1004,
7c3df132 82 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
1806fcd5 83 return QLA_FUNCTION_TIMEOUT;
862cd01e
GM		 84 }
85
1da177e4 86 /*
1c7c6357
AV		 87 * Wait for active mailbox commands to finish by waiting at most tov
88 * seconds. This is to serialize actual issuing of mailbox cmds during
89 * non ISP abort time.
1da177e4 90 */
8eca3f39
AV		 91 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
92 /* Timeout occurred. Return error. */
5e19ed90 93 ql_log(ql_log_warn, vha, 0x1005,
d8c0d546
CD		 94 "Cmd access timeout, cmd=0x%x, Exiting.\n",
95 mcp->mb[0]);
8eca3f39 96 return QLA_FUNCTION_TIMEOUT;
1da177e4
LT		 97 }
98
99 ha->flags.mbox_busy = 1;
100 /* Save mailbox command for debug */
101 ha->mcp = mcp;
102
5e19ed90 103 ql_dbg(ql_dbg_mbx, vha, 0x1006,
7c3df132 104 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
1da177e4
LT		 105
106 spin_lock_irqsave(&ha->hardware_lock, flags);
107
108 /* Load mailbox registers. */
a9083016
GM		 109 if (IS_QLA82XX(ha))
110 optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
111 else if (IS_FWI2_CAPABLE(ha) && !IS_QLA82XX(ha))
1c7c6357
AV		 112 optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
113 else
114 optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
1da177e4
LT		 115
116 iptr = mcp->mb;
117 command = mcp->mb[0];
118 mboxes = mcp->out_mb;
119
120 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
121 if (IS_QLA2200(ha) && cnt == 8)
1c7c6357
AV		 122 optr =
123 (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
1da177e4
LT		 124 if (mboxes & BIT_0)
125 WRT_REG_WORD(optr, *iptr);
126
127 mboxes >>= 1;
128 optr++;
129 iptr++;
130 }
131
5e19ed90 132 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1111,
7c3df132 133 "Loaded MBX registers (displayed in bytes) =.\n");
5e19ed90 134 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1112,
7c3df132 135 (uint8_t *)mcp->mb, 16);
5e19ed90 136 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1113,
7c3df132 137 ".\n");
5e19ed90 138 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1114,
7c3df132 139 ((uint8_t *)mcp->mb + 0x10), 16);
5e19ed90 140 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1115,
7c3df132 141 ".\n");
5e19ed90 142 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1116,
7c3df132 143 ((uint8_t *)mcp->mb + 0x20), 8);
5e19ed90 144 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
7c3df132 145 "I/O Address = %p.\n", optr);
5e19ed90 146 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x100e);
1da177e4
LT		 147
148 /* Issue set host interrupt command to send cmd out. */
149 ha->flags.mbox_int = 0;
150 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
151
152 /* Unlock mbx registers and wait for interrupt */
5e19ed90 153 ql_dbg(ql_dbg_mbx, vha, 0x100f,
7c3df132
SK		 154 "Going to unlock irq & waiting for interrupts. "
155 "jiffies=%lx.\n", jiffies);
1da177e4
LT		 156
157 /* Wait for mbx cmd completion until timeout */
158
124f85e6 159 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
1da177e4
LT		 160 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
161
a9083016
GM		 162 if (IS_QLA82XX(ha)) {
163 if (RD_REG_DWORD(&reg->isp82.hint) &
164 HINT_MBX_INT_PENDING) {
165 spin_unlock_irqrestore(&ha->hardware_lock,
166 flags);
8937f2f1 167 ha->flags.mbox_busy = 0;
5e19ed90 168 ql_dbg(ql_dbg_mbx, vha, 0x1010,
7c3df132 169 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 170 rval = QLA_FUNCTION_TIMEOUT;
171 goto premature_exit;
a9083016
GM		 172 }
173 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
174 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 175 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
176 else
177 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4
LT		 178 spin_unlock_irqrestore(&ha->hardware_lock, flags);
179
0b05a1f0 180 wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
1da177e4 181
1da177e4
LT		 182 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
183
1da177e4 184 } else {
5e19ed90 185 ql_dbg(ql_dbg_mbx, vha, 0x1011,
7c3df132 186 "Cmd=%x Polling Mode.\n", command);
1da177e4 187
a9083016
GM		 188 if (IS_QLA82XX(ha)) {
189 if (RD_REG_DWORD(&reg->isp82.hint) &
190 HINT_MBX_INT_PENDING) {
191 spin_unlock_irqrestore(&ha->hardware_lock,
192 flags);
8937f2f1 193 ha->flags.mbox_busy = 0;
5e19ed90 194 ql_dbg(ql_dbg_mbx, vha, 0x1012,
7c3df132 195 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 196 rval = QLA_FUNCTION_TIMEOUT;
197 goto premature_exit;
a9083016
GM		 198 }
199 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
200 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 201 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
202 else
203 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4 204 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4
LT		 205
206 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
207 while (!ha->flags.mbox_int) {
208 if (time_after(jiffies, wait_time))
209 break;
210
211 /* Check for pending interrupts. */
73208dfd 212 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4 213
85880801
AV		 214 if (!ha->flags.mbox_int &&
215 !(IS_QLA2200(ha) &&
216 command == MBC_LOAD_RISC_RAM_EXTENDED))
59989831 217 msleep(10);
1da177e4 218 } /* while */
5e19ed90 219 ql_dbg(ql_dbg_mbx, vha, 0x1013,
7c3df132
SK		 220 "Waited %d sec.\n",
221 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
1da177e4
LT		 222 }
223
1da177e4
LT		 224 /* Check whether we timed out */
225 if (ha->flags.mbox_int) {
226 uint16_t *iptr2;
227
5e19ed90 228 ql_dbg(ql_dbg_mbx, vha, 0x1014,
7c3df132 229 "Cmd=%x completed.\n", command);
1da177e4
LT		 230
231 /* Got interrupt. Clear the flag. */
232 ha->flags.mbox_int = 0;
233 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
234
7d613ac6 235 if ((IS_QLA82XX(ha) && ha->flags.isp82xx_fw_hung)) {
cdbb0a4f
SV		 236 ha->flags.mbox_busy = 0;
237 /* Setting Link-Down error */
238 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
239 ha->mcp = NULL;
240 rval = QLA_FUNCTION_FAILED;
5e19ed90 241 ql_log(ql_log_warn, vha, 0x1015,
7c3df132 242 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
cdbb0a4f
SV		 243 goto premature_exit;
244 }
245
354d6b21 246 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
1da177e4 247 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 248
249 /* Load return mailbox registers. */
250 iptr2 = mcp->mb;
251 iptr = (uint16_t *)&ha->mailbox_out[0];
252 mboxes = mcp->in_mb;
253 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
254 if (mboxes & BIT_0)
255 *iptr2 = *iptr;
256
257 mboxes >>= 1;
258 iptr2++;
259 iptr++;
260 }
261 } else {
262
1c7c6357
AV		 263 uint16_t mb0;
264 uint32_t ictrl;
265
e428924c 266 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 267 mb0 = RD_REG_WORD(&reg->isp24.mailbox0);
268 ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
269 } else {
cca5335c 270 mb0 = RD_MAILBOX_REG(ha, &reg->isp, 0);
1c7c6357
AV		 271 ictrl = RD_REG_WORD(&reg->isp.ictrl);
272 }
5e19ed90 273 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
5f28d2d7
SK		 274 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
275 "mb[0]=0x%x\n", command, ictrl, jiffies, mb0);
5e19ed90 276 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
1da177e4 277
f55bfc88
CD		 278 /*
279 * Attempt to capture a firmware dump for further analysis
280 * of the current firmware state
281 */
282 ha->isp_ops->fw_dump(vha, 0);
283
1da177e4
LT		 284 rval = QLA_FUNCTION_TIMEOUT;
285 }
286
1da177e4
LT		 287 ha->flags.mbox_busy = 0;
288
289 /* Clean up */
290 ha->mcp = NULL;
291
124f85e6 292 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
5e19ed90 293 ql_dbg(ql_dbg_mbx, vha, 0x101a,
7c3df132 294 "Checking for additional resp interrupt.\n");
1da177e4
LT		 295
296 /* polling mode for non isp_abort commands. */
73208dfd 297 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4
LT		 298 }
299
1c7c6357
AV		 300 if (rval == QLA_FUNCTION_TIMEOUT &&
301 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
85880801
AV		 302 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
303 ha->flags.eeh_busy) {
1da177e4 304 /* not in dpc. schedule it for dpc to take over. */
5e19ed90 305 ql_dbg(ql_dbg_mbx, vha, 0x101b,
7c3df132 306 "Timeout, schedule isp_abort_needed.\n");
cdbb0a4f
SV		 307
308 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
309 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
310 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 311 if (IS_QLA82XX(ha)) {
312 ql_dbg(ql_dbg_mbx, vha, 0x112a,
313 "disabling pause transmit on port "
314 "0 & 1.\n");
315 qla82xx_wr_32(ha,
316 QLA82XX_CRB_NIU + 0x98,
317 CRB_NIU_XG_PAUSE_CTL_P0|
318 CRB_NIU_XG_PAUSE_CTL_P1);
319 }
7c3df132 320 ql_log(ql_log_info, base_vha, 0x101c,
24d9ee85 321 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 322 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
323 "abort.\n", command, mcp->mb[0],
324 ha->flags.eeh_busy);
cdbb0a4f
SV		 325 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
326 qla2xxx_wake_dpc(vha);
327 }
1da177e4 328 } else if (!abort_active) {
1da177e4 329 /* call abort directly since we are in the DPC thread */
5e19ed90 330 ql_dbg(ql_dbg_mbx, vha, 0x101d,
7c3df132 331 "Timeout, calling abort_isp.\n");
cdbb0a4f
SV		 332
333 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
334 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
335 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 336 if (IS_QLA82XX(ha)) {
337 ql_dbg(ql_dbg_mbx, vha, 0x112b,
338 "disabling pause transmit on port "
339 "0 & 1.\n");
340 qla82xx_wr_32(ha,
341 QLA82XX_CRB_NIU + 0x98,
342 CRB_NIU_XG_PAUSE_CTL_P0|
343 CRB_NIU_XG_PAUSE_CTL_P1);
344 }
7c3df132 345 ql_log(ql_log_info, base_vha, 0x101e,
24d9ee85 346 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 347 "mb[0]=0x%x. Scheduling ISP abort ",
348 command, mcp->mb[0]);
cdbb0a4f
SV		 349 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
350 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
d3360960
GM		 351 /* Allow next mbx cmd to come in. */
352 complete(&ha->mbx_cmd_comp);
cdbb0a4f
SV		 353 if (ha->isp_ops->abort_isp(vha)) {
354 /* Failed. retry later. */
355 set_bit(ISP_ABORT_NEEDED,
356 &vha->dpc_flags);
357 }
358 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
5e19ed90 359 ql_dbg(ql_dbg_mbx, vha, 0x101f,
7c3df132 360 "Finished abort_isp.\n");
d3360960 361 goto mbx_done;
1da177e4 362 }
1da177e4
LT		 363 }
364 }
365
cdbb0a4f 366premature_exit:
1da177e4 367 /* Allow next mbx cmd to come in. */
8eca3f39 368 complete(&ha->mbx_cmd_comp);
1da177e4 369
d3360960 370mbx_done:
1da177e4 371 if (rval) {
09543c09 372 ql_log(ql_log_warn, base_vha, 0x1020,
6246b8a1
GM		 373 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
374 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
1da177e4 375 } else {
7c3df132 376 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
1da177e4
LT		 377 }
378
1da177e4
LT		 379 return rval;
380}
381
1da177e4 382int
7b867cf7 383qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
590f98e5 384 uint32_t risc_code_size)
1da177e4
LT		 385{
386 int rval;
7b867cf7 387 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 388 mbx_cmd_t mc;
389 mbx_cmd_t *mcp = &mc;
1da177e4 390
5f28d2d7
SK		 391 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
392 "Entered %s.\n", __func__);
1da177e4 393
e428924c 394 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
590f98e5 395 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
396 mcp->mb[8] = MSW(risc_addr);
397 mcp->out_mb = MBX_8|MBX_0;
1da177e4 398 } else {
590f98e5 399 mcp->mb[0] = MBC_LOAD_RISC_RAM;
400 mcp->out_mb = MBX_0;
1da177e4 401 }
1da177e4
LT		 402 mcp->mb[1] = LSW(risc_addr);
403 mcp->mb[2] = MSW(req_dma);
404 mcp->mb[3] = LSW(req_dma);
1da177e4
LT		 405 mcp->mb[6] = MSW(MSD(req_dma));
406 mcp->mb[7] = LSW(MSD(req_dma));
590f98e5 407 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
e428924c 408 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 409 mcp->mb[4] = MSW(risc_code_size);
410 mcp->mb[5] = LSW(risc_code_size);
411 mcp->out_mb |= MBX_5|MBX_4;
412 } else {
413 mcp->mb[4] = LSW(risc_code_size);
414 mcp->out_mb |= MBX_4;
415 }
416
1da177e4 417 mcp->in_mb = MBX_0;
b93480e3 418 mcp->tov = MBX_TOV_SECONDS;
1da177e4 419 mcp->flags = 0;
7b867cf7 420 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 421
1da177e4 422 if (rval != QLA_SUCCESS) {
7c3df132
SK		 423 ql_dbg(ql_dbg_mbx, vha, 0x1023,
424 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4 425 } else {
5f28d2d7
SK		 426 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
427 "Done %s.\n", __func__);
1da177e4
LT		 428 }
429
430 return rval;
431}
432
cad454b1 433#define EXTENDED_BB_CREDITS BIT_0
1da177e4
LT		 434/*
435 * qla2x00_execute_fw
1c7c6357 436 * Start adapter firmware.
1da177e4
LT		 437 *
438 * Input:
1c7c6357
AV		 439 * ha = adapter block pointer.
440 * TARGET_QUEUE_LOCK must be released.
441 * ADAPTER_STATE_LOCK must be released.
1da177e4
LT		 442 *
443 * Returns:
1c7c6357 444 * qla2x00 local function return status code.
1da177e4
LT		 445 *
446 * Context:
1c7c6357 447 * Kernel context.
1da177e4
LT		 448 */
449int
7b867cf7 450qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 451{
452 int rval;
7b867cf7 453 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 454 mbx_cmd_t mc;
455 mbx_cmd_t *mcp = &mc;
456
5f28d2d7
SK		 457 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
458 "Entered %s.\n", __func__);
1da177e4
LT		 459
460 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
1c7c6357
AV		 461 mcp->out_mb = MBX_0;
462 mcp->in_mb = MBX_0;
e428924c 463 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 464 mcp->mb[1] = MSW(risc_addr);
465 mcp->mb[2] = LSW(risc_addr);
466 mcp->mb[3] = 0;
6246b8a1 467 if (IS_QLA81XX(ha) || IS_QLA83XX(ha)) {
cad454b1
SV		 468 struct nvram_81xx *nv = ha->nvram;
469 mcp->mb[4] = (nv->enhanced_features &
470 EXTENDED_BB_CREDITS);
471 } else
472 mcp->mb[4] = 0;
8b3253d1 473 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
1c7c6357
AV		 474 mcp->in_mb |= MBX_1;
475 } else {
476 mcp->mb[1] = LSW(risc_addr);
477 mcp->out_mb |= MBX_1;
478 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
479 mcp->mb[2] = 0;
480 mcp->out_mb |= MBX_2;
481 }
1da177e4
LT		 482 }
483
b93480e3 484 mcp->tov = MBX_TOV_SECONDS;
1da177e4 485 mcp->flags = 0;
7b867cf7 486 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 487
1c7c6357 488 if (rval != QLA_SUCCESS) {
7c3df132
SK		 489 ql_dbg(ql_dbg_mbx, vha, 0x1026,
490 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357 491 } else {
e428924c 492 if (IS_FWI2_CAPABLE(ha)) {
5f28d2d7 493 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027,
7c3df132 494 "Done exchanges=%x.\n", mcp->mb[1]);
1c7c6357 495 } else {
5f28d2d7
SK		 496 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
497 "Done %s.\n", __func__);
1c7c6357
AV		 498 }
499 }
1da177e4
LT		 500
501 return rval;
502}
503
504/*
505 * qla2x00_get_fw_version
506 * Get firmware version.
507 *
508 * Input:
509 * ha: adapter state pointer.
510 * major: pointer for major number.
511 * minor: pointer for minor number.
512 * subminor: pointer for subminor number.
513 *
514 * Returns:
515 * qla2x00 local function return status code.
516 *
517 * Context:
518 * Kernel context.
519 */
ca9e9c3e 520int
6246b8a1 521qla2x00_get_fw_version(scsi_qla_host_t *vha)
1da177e4
LT		 522{
523 int rval;
524 mbx_cmd_t mc;
525 mbx_cmd_t *mcp = &mc;
6246b8a1 526 struct qla_hw_data *ha = vha->hw;
1da177e4 527
5f28d2d7
SK		 528 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
529 "Entered %s.\n", __func__);
1da177e4
LT		 530
531 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
532 mcp->out_mb = MBX_0;
533 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
6246b8a1 534 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha))
55a96158 535 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
fb0effee 536 if (IS_FWI2_CAPABLE(ha))
6246b8a1 537 mcp->in_mb |= MBX_17|MBX_16|MBX_15;
1da177e4 538 mcp->flags = 0;
b93480e3 539 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 540 rval = qla2x00_mailbox_command(vha, mcp);
ca9e9c3e
AV		 541 if (rval != QLA_SUCCESS)
542 goto failed;
1da177e4
LT		 543
544 /* Return mailbox data. */
6246b8a1
GM		 545 ha->fw_major_version = mcp->mb[1];
546 ha->fw_minor_version = mcp->mb[2];
547 ha->fw_subminor_version = mcp->mb[3];
548 ha->fw_attributes = mcp->mb[6];
7b867cf7 549 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
6246b8a1 550 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
1da177e4 551 else
6246b8a1
GM		 552 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
553 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw)) {
554 ha->mpi_version[0] = mcp->mb[10] & 0xff;
555 ha->mpi_version[1] = mcp->mb[11] >> 8;
556 ha->mpi_version[2] = mcp->mb[11] & 0xff;
557 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
558 ha->phy_version[0] = mcp->mb[8] & 0xff;
559 ha->phy_version[1] = mcp->mb[9] >> 8;
560 ha->phy_version[2] = mcp->mb[9] & 0xff;
561 }
81178772
SK		 562 if (IS_FWI2_CAPABLE(ha)) {
563 ha->fw_attributes_h = mcp->mb[15];
564 ha->fw_attributes_ext[0] = mcp->mb[16];
565 ha->fw_attributes_ext[1] = mcp->mb[17];
566 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
567 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
568 __func__, mcp->mb[15], mcp->mb[6]);
569 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
570 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
571 __func__, mcp->mb[17], mcp->mb[16]);
3a03eb79 572 }
6246b8a1 573
ca9e9c3e 574failed:
1da177e4
LT		 575 if (rval != QLA_SUCCESS) {
576 /*EMPTY*/
7c3df132 577 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
1da177e4
LT		 578 } else {
579 /*EMPTY*/
5f28d2d7
SK		 580 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
581 "Done %s.\n", __func__);
1da177e4 582 }
ca9e9c3e 583 return rval;
1da177e4
LT		 584}
585
586/*
587 * qla2x00_get_fw_options
588 * Set firmware options.
589 *
590 * Input:
591 * ha = adapter block pointer.
592 * fwopt = pointer for firmware options.
593 *
594 * Returns:
595 * qla2x00 local function return status code.
596 *
597 * Context:
598 * Kernel context.
599 */
600int
7b867cf7 601qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 602{
603 int rval;
604 mbx_cmd_t mc;
605 mbx_cmd_t *mcp = &mc;
606
5f28d2d7
SK		 607 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
608 "Entered %s.\n", __func__);
1da177e4
LT		 609
610 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
611 mcp->out_mb = MBX_0;
612 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 613 mcp->tov = MBX_TOV_SECONDS;
1da177e4 614 mcp->flags = 0;
7b867cf7 615 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 616
617 if (rval != QLA_SUCCESS) {
618 /*EMPTY*/
7c3df132 619 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
1da177e4 620 } else {
1c7c6357 621 fwopts[0] = mcp->mb[0];
1da177e4
LT		 622 fwopts[1] = mcp->mb[1];
623 fwopts[2] = mcp->mb[2];
624 fwopts[3] = mcp->mb[3];
625
5f28d2d7
SK		 626 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
627 "Done %s.\n", __func__);
1da177e4
LT		 628 }
629
630 return rval;
631}
632
633
634/*
635 * qla2x00_set_fw_options
636 * Set firmware options.
637 *
638 * Input:
639 * ha = adapter block pointer.
640 * fwopt = pointer for firmware options.
641 *
642 * Returns:
643 * qla2x00 local function return status code.
644 *
645 * Context:
646 * Kernel context.
647 */
648int
7b867cf7 649qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 650{
651 int rval;
652 mbx_cmd_t mc;
653 mbx_cmd_t *mcp = &mc;
654
5f28d2d7
SK		 655 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
656 "Entered %s.\n", __func__);
1da177e4
LT		 657
658 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
659 mcp->mb[1] = fwopts[1];
660 mcp->mb[2] = fwopts[2];
661 mcp->mb[3] = fwopts[3];
1c7c6357 662 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 663 mcp->in_mb = MBX_0;
7b867cf7 664 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 665 mcp->in_mb |= MBX_1;
666 } else {
667 mcp->mb[10] = fwopts[10];
668 mcp->mb[11] = fwopts[11];
669 mcp->mb[12] = 0; /* Undocumented, but used */
670 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
671 }
b93480e3 672 mcp->tov = MBX_TOV_SECONDS;
1da177e4 673 mcp->flags = 0;
7b867cf7 674 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 675
1c7c6357
AV		 676 fwopts[0] = mcp->mb[0];
677
1da177e4
LT		 678 if (rval != QLA_SUCCESS) {
679 /*EMPTY*/
7c3df132
SK		 680 ql_dbg(ql_dbg_mbx, vha, 0x1030,
681 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 682 } else {
683 /*EMPTY*/
5f28d2d7
SK		 684 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
685 "Done %s.\n", __func__);
1da177e4
LT		 686 }
687
688 return rval;
689}
690
691/*
692 * qla2x00_mbx_reg_test
693 * Mailbox register wrap test.
694 *
695 * Input:
696 * ha = adapter block pointer.
697 * TARGET_QUEUE_LOCK must be released.
698 * ADAPTER_STATE_LOCK must be released.
699 *
700 * Returns:
701 * qla2x00 local function return status code.
702 *
703 * Context:
704 * Kernel context.
705 */
706int
7b867cf7 707qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
1da177e4
LT		 708{
709 int rval;
710 mbx_cmd_t mc;
711 mbx_cmd_t *mcp = &mc;
712
5f28d2d7
SK		 713 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
714 "Entered %s.\n", __func__);
1da177e4
LT		 715
716 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
717 mcp->mb[1] = 0xAAAA;
718 mcp->mb[2] = 0x5555;
719 mcp->mb[3] = 0xAA55;
720 mcp->mb[4] = 0x55AA;
721 mcp->mb[5] = 0xA5A5;
722 mcp->mb[6] = 0x5A5A;
723 mcp->mb[7] = 0x2525;
724 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
725 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 726 mcp->tov = MBX_TOV_SECONDS;
1da177e4 727 mcp->flags = 0;
7b867cf7 728 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 729
730 if (rval == QLA_SUCCESS) {
731 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
732 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
733 rval = QLA_FUNCTION_FAILED;
734 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
735 mcp->mb[7] != 0x2525)
736 rval = QLA_FUNCTION_FAILED;
737 }
738
739 if (rval != QLA_SUCCESS) {
740 /*EMPTY*/
7c3df132 741 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
1da177e4
LT		 742 } else {
743 /*EMPTY*/
5f28d2d7
SK		 744 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
745 "Done %s.\n", __func__);
1da177e4
LT		 746 }
747
748 return rval;
749}
750
751/*
752 * qla2x00_verify_checksum
753 * Verify firmware checksum.
754 *
755 * Input:
756 * ha = adapter block pointer.
757 * TARGET_QUEUE_LOCK must be released.
758 * ADAPTER_STATE_LOCK must be released.
759 *
760 * Returns:
761 * qla2x00 local function return status code.
762 *
763 * Context:
764 * Kernel context.
765 */
766int
7b867cf7 767qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 768{
769 int rval;
770 mbx_cmd_t mc;
771 mbx_cmd_t *mcp = &mc;
772
5f28d2d7
SK		 773 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
774 "Entered %s.\n", __func__);
1da177e4
LT		 775
776 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
1c7c6357
AV		 777 mcp->out_mb = MBX_0;
778 mcp->in_mb = MBX_0;
7b867cf7 779 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 780 mcp->mb[1] = MSW(risc_addr);
781 mcp->mb[2] = LSW(risc_addr);
782 mcp->out_mb |= MBX_2|MBX_1;
783 mcp->in_mb |= MBX_2|MBX_1;
784 } else {
785 mcp->mb[1] = LSW(risc_addr);
786 mcp->out_mb |= MBX_1;
787 mcp->in_mb |= MBX_1;
788 }
789
b93480e3 790 mcp->tov = MBX_TOV_SECONDS;
1da177e4 791 mcp->flags = 0;
7b867cf7 792 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 793
794 if (rval != QLA_SUCCESS) {
7c3df132
SK		 795 ql_dbg(ql_dbg_mbx, vha, 0x1036,
796 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
797 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
1da177e4 798 } else {
5f28d2d7
SK		 799 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
800 "Done %s.\n", __func__);
1da177e4
LT		 801 }
802
803 return rval;
804}
805
806/*
807 * qla2x00_issue_iocb
808 * Issue IOCB using mailbox command
809 *
810 * Input:
811 * ha = adapter state pointer.
812 * buffer = buffer pointer.
813 * phys_addr = physical address of buffer.
814 * size = size of buffer.
815 * TARGET_QUEUE_LOCK must be released.
816 * ADAPTER_STATE_LOCK must be released.
817 *
818 * Returns:
819 * qla2x00 local function return status code.
820 *
821 * Context:
822 * Kernel context.
823 */
6e98016c 824int
7b867cf7 825qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
4d4df193 826 dma_addr_t phys_addr, size_t size, uint32_t tov)
1da177e4
LT		 827{
828 int rval;
829 mbx_cmd_t mc;
830 mbx_cmd_t *mcp = &mc;
831
5f28d2d7
SK		 832 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
833 "Entered %s.\n", __func__);
7c3df132 834
1da177e4
LT		 835 mcp->mb[0] = MBC_IOCB_COMMAND_A64;
836 mcp->mb[1] = 0;
837 mcp->mb[2] = MSW(phys_addr);
838 mcp->mb[3] = LSW(phys_addr);
839 mcp->mb[6] = MSW(MSD(phys_addr));
840 mcp->mb[7] = LSW(MSD(phys_addr));
841 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
842 mcp->in_mb = MBX_2|MBX_0;
4d4df193 843 mcp->tov = tov;
1da177e4 844 mcp->flags = 0;
7b867cf7 845 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 846
847 if (rval != QLA_SUCCESS) {
848 /*EMPTY*/
7c3df132 849 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
1da177e4 850 } else {
8c958a99
AV		 851 sts_entry_t *sts_entry = (sts_entry_t *) buffer;
852
853 /* Mask reserved bits. */
854 sts_entry->entry_status &=
7b867cf7 855 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
5f28d2d7
SK		 856 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
857 "Done %s.\n", __func__);
1da177e4
LT		 858 }
859
860 return rval;
861}
862
4d4df193 863int
7b867cf7 864qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
4d4df193
HK		 865 size_t size)
866{
7b867cf7 867 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
4d4df193
HK		 868 MBX_TOV_SECONDS);
869}
870
1da177e4
LT		 871/*
872 * qla2x00_abort_command
873 * Abort command aborts a specified IOCB.
874 *
875 * Input:
876 * ha = adapter block pointer.
877 * sp = SB structure pointer.
878 *
879 * Returns:
880 * qla2x00 local function return status code.
881 *
882 * Context:
883 * Kernel context.
884 */
885int
2afa19a9 886qla2x00_abort_command(srb_t *sp)
1da177e4
LT		 887{
888 unsigned long flags = 0;
1da177e4 889 int rval;
73208dfd 890 uint32_t handle = 0;
1da177e4
LT		 891 mbx_cmd_t mc;
892 mbx_cmd_t *mcp = &mc;
2afa19a9
AC		 893 fc_port_t *fcport = sp->fcport;
894 scsi_qla_host_t *vha = fcport->vha;
7b867cf7 895 struct qla_hw_data *ha = vha->hw;
2afa19a9 896 struct req_que *req = vha->req;
9ba56b95 897 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1da177e4 898
5f28d2d7
SK		 899 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
900 "Entered %s.\n", __func__);
1da177e4 901
c9c5ced9 902 spin_lock_irqsave(&ha->hardware_lock, flags);
8d93f550 903 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 904 if (req->outstanding_cmds[handle] == sp)
1da177e4
LT		 905 break;
906 }
c9c5ced9 907 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 908
8d93f550 909 if (handle == req->num_outstanding_cmds) {
1da177e4
LT		 910 /* command not found */
911 return QLA_FUNCTION_FAILED;
912 }
913
914 mcp->mb[0] = MBC_ABORT_COMMAND;
915 if (HAS_EXTENDED_IDS(ha))
916 mcp->mb[1] = fcport->loop_id;
917 else
918 mcp->mb[1] = fcport->loop_id << 8;
919 mcp->mb[2] = (uint16_t)handle;
920 mcp->mb[3] = (uint16_t)(handle >> 16);
9ba56b95 921 mcp->mb[6] = (uint16_t)cmd->device->lun;
1da177e4
LT		 922 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
923 mcp->in_mb = MBX_0;
b93480e3 924 mcp->tov = MBX_TOV_SECONDS;
1da177e4 925 mcp->flags = 0;
7b867cf7 926 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 927
928 if (rval != QLA_SUCCESS) {
7c3df132 929 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
1da177e4 930 } else {
5f28d2d7
SK		 931 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
932 "Done %s.\n", __func__);
1da177e4
LT		 933 }
934
935 return rval;
936}
937
1da177e4 938int
2afa19a9 939qla2x00_abort_target(struct fc_port *fcport, unsigned int l, int tag)
1da177e4 940{
523ec773 941 int rval, rval2;
1da177e4
LT		 942 mbx_cmd_t mc;
943 mbx_cmd_t *mcp = &mc;
7b867cf7 944 scsi_qla_host_t *vha;
73208dfd
AC		 945 struct req_que *req;
946 struct rsp_que *rsp;
1da177e4 947
523ec773 948 l = l;
7b867cf7 949 vha = fcport->vha;
7c3df132 950
5f28d2d7
SK		 951 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
952 "Entered %s.\n", __func__);
7c3df132 953
7e2b895b
GM		 954 req = vha->hw->req_q_map[0];
955 rsp = req->rsp;
1da177e4 956 mcp->mb[0] = MBC_ABORT_TARGET;
523ec773 957 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
7b867cf7 958 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 959 mcp->mb[1] = fcport->loop_id;
960 mcp->mb[10] = 0;
961 mcp->out_mb |= MBX_10;
962 } else {
963 mcp->mb[1] = fcport->loop_id << 8;
964 }
7b867cf7
AC		 965 mcp->mb[2] = vha->hw->loop_reset_delay;
966 mcp->mb[9] = vha->vp_idx;
1da177e4
LT		 967
968 mcp->in_mb = MBX_0;
b93480e3 969 mcp->tov = MBX_TOV_SECONDS;
1da177e4 970 mcp->flags = 0;
7b867cf7 971 rval = qla2x00_mailbox_command(vha, mcp);
523ec773 972 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 973 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
974 "Failed=%x.\n", rval);
523ec773
AV		 975 }
976
977 /* Issue marker IOCB. */
73208dfd
AC		 978 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
979 MK_SYNC_ID);
523ec773 980 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 981 ql_dbg(ql_dbg_mbx, vha, 0x1040,
982 "Failed to issue marker IOCB (%x).\n", rval2);
523ec773 983 } else {
5f28d2d7
SK		 984 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
985 "Done %s.\n", __func__);
523ec773
AV		 986 }
987
988 return rval;
989}
990
991int
2afa19a9 992qla2x00_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
523ec773
AV		 993{
994 int rval, rval2;
995 mbx_cmd_t mc;
996 mbx_cmd_t *mcp = &mc;
7b867cf7 997 scsi_qla_host_t *vha;
73208dfd
AC		 998 struct req_que *req;
999 struct rsp_que *rsp;
523ec773 1000
7b867cf7 1001 vha = fcport->vha;
7c3df132 1002
5f28d2d7
SK		 1003 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
1004 "Entered %s.\n", __func__);
7c3df132 1005
7e2b895b
GM		 1006 req = vha->hw->req_q_map[0];
1007 rsp = req->rsp;
523ec773
AV		 1008 mcp->mb[0] = MBC_LUN_RESET;
1009 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 1010 if (HAS_EXTENDED_IDS(vha->hw))
523ec773
AV		 1011 mcp->mb[1] = fcport->loop_id;
1012 else
1013 mcp->mb[1] = fcport->loop_id << 8;
1014 mcp->mb[2] = l;
1015 mcp->mb[3] = 0;
7b867cf7 1016 mcp->mb[9] = vha->vp_idx;
1da177e4 1017
523ec773 1018 mcp->in_mb = MBX_0;
b93480e3 1019 mcp->tov = MBX_TOV_SECONDS;
523ec773 1020 mcp->flags = 0;
7b867cf7 1021 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1022 if (rval != QLA_SUCCESS) {
7c3df132 1023 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
523ec773
AV		 1024 }
1025
1026 /* Issue marker IOCB. */
73208dfd
AC		 1027 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
1028 MK_SYNC_ID_LUN);
523ec773 1029 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 1030 ql_dbg(ql_dbg_mbx, vha, 0x1044,
1031 "Failed to issue marker IOCB (%x).\n", rval2);
1da177e4 1032 } else {
5f28d2d7
SK		 1033 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
1034 "Done %s.\n", __func__);
1da177e4
LT		 1035 }
1036
1037 return rval;
1038}
1da177e4 1039
1da177e4
LT		 1040/*
1041 * qla2x00_get_adapter_id
1042 * Get adapter ID and topology.
1043 *
1044 * Input:
1045 * ha = adapter block pointer.
1046 * id = pointer for loop ID.
1047 * al_pa = pointer for AL_PA.
1048 * area = pointer for area.
1049 * domain = pointer for domain.
1050 * top = pointer for topology.
1051 * TARGET_QUEUE_LOCK must be released.
1052 * ADAPTER_STATE_LOCK must be released.
1053 *
1054 * Returns:
1055 * qla2x00 local function return status code.
1056 *
1057 * Context:
1058 * Kernel context.
1059 */
1060int
7b867cf7 1061qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
2c3dfe3f 1062 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
1da177e4
LT		 1063{
1064 int rval;
1065 mbx_cmd_t mc;
1066 mbx_cmd_t *mcp = &mc;
1067
5f28d2d7
SK		 1068 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
1069 "Entered %s.\n", __func__);
1da177e4
LT		 1070
1071 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
7b867cf7 1072 mcp->mb[9] = vha->vp_idx;
eb66dc60 1073 mcp->out_mb = MBX_9|MBX_0;
2c3dfe3f 1074 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6246b8a1 1075 if (IS_CNA_CAPABLE(vha->hw))
bad7001c 1076 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
b93480e3 1077 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1078 mcp->flags = 0;
7b867cf7 1079 rval = qla2x00_mailbox_command(vha, mcp);
33135aa2
RA		 1080 if (mcp->mb[0] == MBS_COMMAND_ERROR)
1081 rval = QLA_COMMAND_ERROR;
42e421b1
AV		 1082 else if (mcp->mb[0] == MBS_INVALID_COMMAND)
1083 rval = QLA_INVALID_COMMAND;
1da177e4
LT		 1084
1085 /* Return data. */
1086 *id = mcp->mb[1];
1087 *al_pa = LSB(mcp->mb[2]);
1088 *area = MSB(mcp->mb[2]);
1089 *domain = LSB(mcp->mb[3]);
1090 *top = mcp->mb[6];
2c3dfe3f 1091 *sw_cap = mcp->mb[7];
1da177e4
LT		 1092
1093 if (rval != QLA_SUCCESS) {
1094 /*EMPTY*/
7c3df132 1095 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
1da177e4 1096 } else {
5f28d2d7
SK		 1097 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
1098 "Done %s.\n", __func__);
bad7001c 1099
6246b8a1 1100 if (IS_CNA_CAPABLE(vha->hw)) {
bad7001c
AV		 1101 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1102 vha->fcoe_fcf_idx = mcp->mb[10];
1103 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
1104 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
1105 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
1106 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
1107 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
1108 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
1109 }
1da177e4
LT		 1110 }
1111
1112 return rval;
1113}
1114
1115/*
1116 * qla2x00_get_retry_cnt
1117 * Get current firmware login retry count and delay.
1118 *
1119 * Input:
1120 * ha = adapter block pointer.
1121 * retry_cnt = pointer to login retry count.
1122 * tov = pointer to login timeout value.
1123 *
1124 * Returns:
1125 * qla2x00 local function return status code.
1126 *
1127 * Context:
1128 * Kernel context.
1129 */
1130int
7b867cf7 1131qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
1da177e4
LT		 1132 uint16_t *r_a_tov)
1133{
1134 int rval;
1135 uint16_t ratov;
1136 mbx_cmd_t mc;
1137 mbx_cmd_t *mcp = &mc;
1138
5f28d2d7
SK		 1139 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
1140 "Entered %s.\n", __func__);
1da177e4
LT		 1141
1142 mcp->mb[0] = MBC_GET_RETRY_COUNT;
1143 mcp->out_mb = MBX_0;
1144 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1145 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1146 mcp->flags = 0;
7b867cf7 1147 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1148
1149 if (rval != QLA_SUCCESS) {
1150 /*EMPTY*/
7c3df132
SK		 1151 ql_dbg(ql_dbg_mbx, vha, 0x104a,
1152 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4
LT		 1153 } else {
1154 /* Convert returned data and check our values. */
1155 *r_a_tov = mcp->mb[3] / 2;
1156 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
1157 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
1158 /* Update to the larger values */
1159 *retry_cnt = (uint8_t)mcp->mb[1];
1160 *tov = ratov;
1161 }
1162
5f28d2d7 1163 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
7c3df132 1164 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
1da177e4
LT		 1165 }
1166
1167 return rval;
1168}
1169
1170/*
1171 * qla2x00_init_firmware
1172 * Initialize adapter firmware.
1173 *
1174 * Input:
1175 * ha = adapter block pointer.
1176 * dptr = Initialization control block pointer.
1177 * size = size of initialization control block.
1178 * TARGET_QUEUE_LOCK must be released.
1179 * ADAPTER_STATE_LOCK must be released.
1180 *
1181 * Returns:
1182 * qla2x00 local function return status code.
1183 *
1184 * Context:
1185 * Kernel context.
1186 */
1187int
7b867cf7 1188qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1da177e4
LT		 1189{
1190 int rval;
1191 mbx_cmd_t mc;
1192 mbx_cmd_t *mcp = &mc;
7b867cf7 1193 struct qla_hw_data *ha = vha->hw;
1da177e4 1194
5f28d2d7
SK		 1195 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
1196 "Entered %s.\n", __func__);
1da177e4 1197
a9083016
GM		 1198 if (IS_QLA82XX(ha) && ql2xdbwr)
1199 qla82xx_wr_32(ha, ha->nxdb_wr_ptr,
1200 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1201
e6e074f1 1202 if (ha->flags.npiv_supported)
2c3dfe3f
SJ		 1203 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
1204 else
1205 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1206
b64b0e8f 1207 mcp->mb[1] = 0;
1da177e4
LT		 1208 mcp->mb[2] = MSW(ha->init_cb_dma);
1209 mcp->mb[3] = LSW(ha->init_cb_dma);
1da177e4
LT		 1210 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1211 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
b64b0e8f 1212 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6246b8a1 1213 if ((IS_QLA81XX(ha) || IS_QLA83XX(ha)) && ha->ex_init_cb->ex_version) {
b64b0e8f
AV		 1214 mcp->mb[1] = BIT_0;
1215 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1216 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
1217 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
1218 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
1219 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1220 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1221 }
6246b8a1
GM		 1222 /* 1 and 2 should normally be captured. */
1223 mcp->in_mb = MBX_2|MBX_1|MBX_0;
1224 if (IS_QLA83XX(ha))
1225 /* mb3 is additional info about the installed SFP. */
1226 mcp->in_mb |= MBX_3;
1da177e4
LT		 1227 mcp->buf_size = size;
1228 mcp->flags = MBX_DMA_OUT;
b93480e3 1229 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 1230 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1231
1232 if (rval != QLA_SUCCESS) {
1233 /*EMPTY*/
7c3df132 1234 ql_dbg(ql_dbg_mbx, vha, 0x104d,
6246b8a1
GM		 1235 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
1236 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
1da177e4
LT		 1237 } else {
1238 /*EMPTY*/
5f28d2d7
SK		 1239 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
1240 "Done %s.\n", __func__);
1da177e4
LT		 1241 }
1242
1243 return rval;
1244}
1245
2d70c103
NB		 1246/*
1247 * qla2x00_get_node_name_list
1248 * Issue get node name list mailbox command, kmalloc()
1249 * and return the resulting list. Caller must kfree() it!
1250 *
1251 * Input:
1252 * ha = adapter state pointer.
1253 * out_data = resulting list
1254 * out_len = length of the resulting list
1255 *
1256 * Returns:
1257 * qla2x00 local function return status code.
1258 *
1259 * Context:
1260 * Kernel context.
1261 */
1262int
1263qla2x00_get_node_name_list(scsi_qla_host_t *vha, void **out_data, int *out_len)
1264{
1265 struct qla_hw_data *ha = vha->hw;
1266 struct qla_port_24xx_data *list = NULL;
1267 void *pmap;
1268 mbx_cmd_t mc;
1269 dma_addr_t pmap_dma;
1270 ulong dma_size;
1271 int rval, left;
1272
1273 left = 1;
1274 while (left > 0) {
1275 dma_size = left * sizeof(*list);
1276 pmap = dma_alloc_coherent(&ha->pdev->dev, dma_size,
1277 &pmap_dma, GFP_KERNEL);
1278 if (!pmap) {
1279 ql_log(ql_log_warn, vha, 0x113f,
1280 "%s(%ld): DMA Alloc failed of %ld\n",
1281 __func__, vha->host_no, dma_size);
1282 rval = QLA_MEMORY_ALLOC_FAILED;
1283 goto out;
1284 }
1285
1286 mc.mb[0] = MBC_PORT_NODE_NAME_LIST;
1287 mc.mb[1] = BIT_1 | BIT_3;
1288 mc.mb[2] = MSW(pmap_dma);
1289 mc.mb[3] = LSW(pmap_dma);
1290 mc.mb[6] = MSW(MSD(pmap_dma));
1291 mc.mb[7] = LSW(MSD(pmap_dma));
1292 mc.mb[8] = dma_size;
1293 mc.out_mb = MBX_0|MBX_1|MBX_2|MBX_3|MBX_6|MBX_7|MBX_8;
1294 mc.in_mb = MBX_0|MBX_1;
1295 mc.tov = 30;
1296 mc.flags = MBX_DMA_IN;
1297
1298 rval = qla2x00_mailbox_command(vha, &mc);
1299 if (rval != QLA_SUCCESS) {
1300 if ((mc.mb[0] == MBS_COMMAND_ERROR) &&
1301 (mc.mb[1] == 0xA)) {
1302 left += le16_to_cpu(mc.mb[2]) /
1303 sizeof(struct qla_port_24xx_data);
1304 goto restart;
1305 }
1306 goto out_free;
1307 }
1308
1309 left = 0;
1310
1311 list = kzalloc(dma_size, GFP_KERNEL);
1312 if (!list) {
1313 ql_log(ql_log_warn, vha, 0x1140,
1314 "%s(%ld): failed to allocate node names list "
1315 "structure.\n", __func__, vha->host_no);
1316 rval = QLA_MEMORY_ALLOC_FAILED;
1317 goto out_free;
1318 }
1319
1320 memcpy(list, pmap, dma_size);
1321restart:
1322 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
1323 }
1324
1325 *out_data = list;
1326 *out_len = dma_size;
1327
1328out:
1329 return rval;
1330
1331out_free:
1332 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
1333 return rval;
1334}
1335
1da177e4
LT		 1336/*
1337 * qla2x00_get_port_database
1338 * Issue normal/enhanced get port database mailbox command
1339 * and copy device name as necessary.
1340 *
1341 * Input:
1342 * ha = adapter state pointer.
1343 * dev = structure pointer.
1344 * opt = enhanced cmd option byte.
1345 *
1346 * Returns:
1347 * qla2x00 local function return status code.
1348 *
1349 * Context:
1350 * Kernel context.
1351 */
1352int
7b867cf7 1353qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
1da177e4
LT		 1354{
1355 int rval;
1356 mbx_cmd_t mc;
1357 mbx_cmd_t *mcp = &mc;
1358 port_database_t *pd;
1c7c6357 1359 struct port_database_24xx *pd24;
1da177e4 1360 dma_addr_t pd_dma;
7b867cf7 1361 struct qla_hw_data *ha = vha->hw;
1da177e4 1362
5f28d2d7
SK		 1363 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
1364 "Entered %s.\n", __func__);
1da177e4 1365
1c7c6357
AV		 1366 pd24 = NULL;
1367 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1da177e4 1368 if (pd == NULL) {
7c3df132
SK		 1369 ql_log(ql_log_warn, vha, 0x1050,
1370 "Failed to allocate port database structure.\n");
1da177e4
LT		 1371 return QLA_MEMORY_ALLOC_FAILED;
1372 }
1c7c6357 1373 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
1da177e4 1374
1c7c6357 1375 mcp->mb[0] = MBC_GET_PORT_DATABASE;
e428924c 1376 if (opt != 0 && !IS_FWI2_CAPABLE(ha))
1da177e4 1377 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
1da177e4
LT		 1378 mcp->mb[2] = MSW(pd_dma);
1379 mcp->mb[3] = LSW(pd_dma);
1380 mcp->mb[6] = MSW(MSD(pd_dma));
1381 mcp->mb[7] = LSW(MSD(pd_dma));
7b867cf7 1382 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 1383 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1da177e4 1384 mcp->in_mb = MBX_0;
e428924c 1385 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 1386 mcp->mb[1] = fcport->loop_id;
1387 mcp->mb[10] = opt;
1388 mcp->out_mb |= MBX_10|MBX_1;
1389 mcp->in_mb |= MBX_1;
1390 } else if (HAS_EXTENDED_IDS(ha)) {
1391 mcp->mb[1] = fcport->loop_id;
1392 mcp->mb[10] = opt;
1393 mcp->out_mb |= MBX_10|MBX_1;
1394 } else {
1395 mcp->mb[1] = fcport->loop_id << 8 | opt;
1396 mcp->out_mb |= MBX_1;
1397 }
e428924c
AV		 1398 mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
1399 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
1da177e4
LT		 1400 mcp->flags = MBX_DMA_IN;
1401 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 1402 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1403 if (rval != QLA_SUCCESS)
1404 goto gpd_error_out;
1405
e428924c 1406 if (IS_FWI2_CAPABLE(ha)) {
0eba25df 1407 uint64_t zero = 0;
1c7c6357
AV		 1408 pd24 = (struct port_database_24xx *) pd;
1409
1410 /* Check for logged in state. */
1411 if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
1412 pd24->last_login_state != PDS_PRLI_COMPLETE) {
7c3df132
SK		 1413 ql_dbg(ql_dbg_mbx, vha, 0x1051,
1414 "Unable to verify login-state (%x/%x) for "
1415 "loop_id %x.\n", pd24->current_login_state,
1416 pd24->last_login_state, fcport->loop_id);
1c7c6357
AV		 1417 rval = QLA_FUNCTION_FAILED;
1418 goto gpd_error_out;
1419 }
1da177e4 1420
0eba25df
AE		 1421 if (fcport->loop_id == FC_NO_LOOP_ID ||
1422 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1423 memcmp(fcport->port_name, pd24->port_name, 8))) {
1424 /* We lost the device mid way. */
1425 rval = QLA_NOT_LOGGED_IN;
1426 goto gpd_error_out;
1427 }
1428
1c7c6357
AV		 1429 /* Names are little-endian. */
1430 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
1431 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
1432
1433 /* Get port_id of device. */
1434 fcport->d_id.b.domain = pd24->port_id[0];
1435 fcport->d_id.b.area = pd24->port_id[1];
1436 fcport->d_id.b.al_pa = pd24->port_id[2];
1437 fcport->d_id.b.rsvd_1 = 0;
1438
1439 /* If not target must be initiator or unknown type. */
1440 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
1441 fcport->port_type = FCT_INITIATOR;
1442 else
1443 fcport->port_type = FCT_TARGET;
2d70c103
NB		 1444
1445 /* Passback COS information. */
1446 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
1447 FC_COS_CLASS2 : FC_COS_CLASS3;
1448
1449 if (pd24->prli_svc_param_word_3[0] & BIT_7)
1450 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
1c7c6357 1451 } else {
0eba25df
AE		 1452 uint64_t zero = 0;
1453
1c7c6357
AV		 1454 /* Check for logged in state. */
1455 if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
1456 pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
7c3df132
SK		 1457 ql_dbg(ql_dbg_mbx, vha, 0x100a,
1458 "Unable to verify login-state (%x/%x) - "
1459 "portid=%02x%02x%02x.\n", pd->master_state,
1460 pd->slave_state, fcport->d_id.b.domain,
1461 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1c7c6357
AV		 1462 rval = QLA_FUNCTION_FAILED;
1463 goto gpd_error_out;
1464 }
1da177e4 1465
0eba25df
AE		 1466 if (fcport->loop_id == FC_NO_LOOP_ID ||
1467 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1468 memcmp(fcport->port_name, pd->port_name, 8))) {
1469 /* We lost the device mid way. */
1470 rval = QLA_NOT_LOGGED_IN;
1471 goto gpd_error_out;
1472 }
1473
1c7c6357
AV		 1474 /* Names are little-endian. */
1475 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
1476 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
1477
1478 /* Get port_id of device. */
1479 fcport->d_id.b.domain = pd->port_id[0];
1480 fcport->d_id.b.area = pd->port_id[3];
1481 fcport->d_id.b.al_pa = pd->port_id[2];
1482 fcport->d_id.b.rsvd_1 = 0;
1483
1c7c6357
AV		 1484 /* If not target must be initiator or unknown type. */
1485 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
1486 fcport->port_type = FCT_INITIATOR;
1487 else
1488 fcport->port_type = FCT_TARGET;
ad3e0eda
AV		 1489
1490 /* Passback COS information. */
1491 fcport->supported_classes = (pd->options & BIT_4) ?
1492 FC_COS_CLASS2: FC_COS_CLASS3;
1c7c6357 1493 }
1da177e4
LT		 1494
1495gpd_error_out:
1496 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1497
1498 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1499 ql_dbg(ql_dbg_mbx, vha, 0x1052,
1500 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
1501 mcp->mb[0], mcp->mb[1]);
1da177e4 1502 } else {
5f28d2d7
SK		 1503 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
1504 "Done %s.\n", __func__);
1da177e4
LT		 1505 }
1506
1507 return rval;
1508}
1509
1510/*
1511 * qla2x00_get_firmware_state
1512 * Get adapter firmware state.
1513 *
1514 * Input:
1515 * ha = adapter block pointer.
1516 * dptr = pointer for firmware state.
1517 * TARGET_QUEUE_LOCK must be released.
1518 * ADAPTER_STATE_LOCK must be released.
1519 *
1520 * Returns:
1521 * qla2x00 local function return status code.
1522 *
1523 * Context:
1524 * Kernel context.
1525 */
1526int
7b867cf7 1527qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
1da177e4
LT		 1528{
1529 int rval;
1530 mbx_cmd_t mc;
1531 mbx_cmd_t *mcp = &mc;
1532
5f28d2d7
SK		 1533 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
1534 "Entered %s.\n", __func__);
1da177e4
LT		 1535
1536 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
1537 mcp->out_mb = MBX_0;
9d2683c0
AV		 1538 if (IS_FWI2_CAPABLE(vha->hw))
1539 mcp->in_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1540 else
1541 mcp->in_mb = MBX_1|MBX_0;
b93480e3 1542 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1543 mcp->flags = 0;
7b867cf7 1544 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1545
4d4df193
HK		 1546 /* Return firmware states. */
1547 states[0] = mcp->mb[1];
9d2683c0
AV		 1548 if (IS_FWI2_CAPABLE(vha->hw)) {
1549 states[1] = mcp->mb[2];
1550 states[2] = mcp->mb[3];
1551 states[3] = mcp->mb[4];
1552 states[4] = mcp->mb[5];
1553 }
1da177e4
LT		 1554
1555 if (rval != QLA_SUCCESS) {
1556 /*EMPTY*/
7c3df132 1557 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
1da177e4
LT		 1558 } else {
1559 /*EMPTY*/
5f28d2d7
SK		 1560 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
1561 "Done %s.\n", __func__);
1da177e4
LT		 1562 }
1563
1564 return rval;
1565}
1566
1567/*
1568 * qla2x00_get_port_name
1569 * Issue get port name mailbox command.
1570 * Returned name is in big endian format.
1571 *
1572 * Input:
1573 * ha = adapter block pointer.
1574 * loop_id = loop ID of device.
1575 * name = pointer for name.
1576 * TARGET_QUEUE_LOCK must be released.
1577 * ADAPTER_STATE_LOCK must be released.
1578 *
1579 * Returns:
1580 * qla2x00 local function return status code.
1581 *
1582 * Context:
1583 * Kernel context.
1584 */
1585int
7b867cf7 1586qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
1da177e4
LT		 1587 uint8_t opt)
1588{
1589 int rval;
1590 mbx_cmd_t mc;
1591 mbx_cmd_t *mcp = &mc;
1592
5f28d2d7
SK		 1593 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
1594 "Entered %s.\n", __func__);
1da177e4
LT		 1595
1596 mcp->mb[0] = MBC_GET_PORT_NAME;
7b867cf7 1597 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 1598 mcp->out_mb = MBX_9|MBX_1|MBX_0;
7b867cf7 1599 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 1600 mcp->mb[1] = loop_id;
1601 mcp->mb[10] = opt;
1602 mcp->out_mb |= MBX_10;
1603 } else {
1604 mcp->mb[1] = loop_id << 8 | opt;
1605 }
1606
1607 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1608 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1609 mcp->flags = 0;
7b867cf7 1610 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1611
1612 if (rval != QLA_SUCCESS) {
1613 /*EMPTY*/
7c3df132 1614 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
1da177e4
LT		 1615 } else {
1616 if (name != NULL) {
1617 /* This function returns name in big endian. */
1196ae02
RL		 1618 name[0] = MSB(mcp->mb[2]);
1619 name[1] = LSB(mcp->mb[2]);
1620 name[2] = MSB(mcp->mb[3]);
1621 name[3] = LSB(mcp->mb[3]);
1622 name[4] = MSB(mcp->mb[6]);
1623 name[5] = LSB(mcp->mb[6]);
1624 name[6] = MSB(mcp->mb[7]);
1625 name[7] = LSB(mcp->mb[7]);
1da177e4
LT		 1626 }
1627
5f28d2d7
SK		 1628 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
1629 "Done %s.\n", __func__);
1da177e4
LT		 1630 }
1631
1632 return rval;
1633}
1634
61e1b269
JC		 1635/*
1636 * qla24xx_link_initialization
1637 * Issue link initialization mailbox command.
1638 *
1639 * Input:
1640 * ha = adapter block pointer.
1641 * TARGET_QUEUE_LOCK must be released.
1642 * ADAPTER_STATE_LOCK must be released.
1643 *
1644 * Returns:
1645 * qla2x00 local function return status code.
1646 *
1647 * Context:
1648 * Kernel context.
1649 */
1650int
1651qla24xx_link_initialize(scsi_qla_host_t *vha)
1652{
1653 int rval;
1654 mbx_cmd_t mc;
1655 mbx_cmd_t *mcp = &mc;
1656
1657 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
1658 "Entered %s.\n", __func__);
1659
1660 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
1661 return QLA_FUNCTION_FAILED;
1662
1663 mcp->mb[0] = MBC_LINK_INITIALIZATION;
1664 mcp->mb[1] = BIT_6|BIT_4;
1665 mcp->mb[2] = 0;
1666 mcp->mb[3] = 0;
1667 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1668 mcp->in_mb = MBX_0;
1669 mcp->tov = MBX_TOV_SECONDS;
1670 mcp->flags = 0;
1671 rval = qla2x00_mailbox_command(vha, mcp);
1672
1673 if (rval != QLA_SUCCESS) {
1674 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
1675 } else {
1676 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
1677 "Done %s.\n", __func__);
1678 }
1679
1680 return rval;
1681}
1682
1da177e4
LT		 1683/*
1684 * qla2x00_lip_reset
1685 * Issue LIP reset mailbox command.
1686 *
1687 * Input:
1688 * ha = adapter block pointer.
1689 * TARGET_QUEUE_LOCK must be released.
1690 * ADAPTER_STATE_LOCK must be released.
1691 *
1692 * Returns:
1693 * qla2x00 local function return status code.
1694 *
1695 * Context:
1696 * Kernel context.
1697 */
1698int
7b867cf7 1699qla2x00_lip_reset(scsi_qla_host_t *vha)
1da177e4
LT		 1700{
1701 int rval;
1702 mbx_cmd_t mc;
1703 mbx_cmd_t *mcp = &mc;
1704
5f28d2d7
SK		 1705 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
1706 "Entered %s.\n", __func__);
1da177e4 1707
6246b8a1 1708 if (IS_CNA_CAPABLE(vha->hw)) {
3a03eb79
AV		 1709 /* Logout across all FCFs. */
1710 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
1711 mcp->mb[1] = BIT_1;
1712 mcp->mb[2] = 0;
1713 mcp->out_mb = MBX_2|MBX_1|MBX_0;
1714 } else if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357 1715 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
0c8c39af
AV		 1716 mcp->mb[1] = BIT_6;
1717 mcp->mb[2] = 0;
7b867cf7 1718 mcp->mb[3] = vha->hw->loop_reset_delay;
1c7c6357 1719 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 1720 } else {
1c7c6357
AV		 1721 mcp->mb[0] = MBC_LIP_RESET;
1722 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 1723 if (HAS_EXTENDED_IDS(vha->hw)) {
1c7c6357
AV		 1724 mcp->mb[1] = 0x00ff;
1725 mcp->mb[10] = 0;
1726 mcp->out_mb |= MBX_10;
1727 } else {
1728 mcp->mb[1] = 0xff00;
1729 }
7b867cf7 1730 mcp->mb[2] = vha->hw->loop_reset_delay;
1c7c6357 1731 mcp->mb[3] = 0;
1da177e4 1732 }
1da177e4 1733 mcp->in_mb = MBX_0;
b93480e3 1734 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1735 mcp->flags = 0;
7b867cf7 1736 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1737
1738 if (rval != QLA_SUCCESS) {
1739 /*EMPTY*/
7c3df132 1740 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
1da177e4
LT		 1741 } else {
1742 /*EMPTY*/
5f28d2d7
SK		 1743 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
1744 "Done %s.\n", __func__);
1da177e4
LT		 1745 }
1746
1747 return rval;
1748}
1749
1750/*
1751 * qla2x00_send_sns
1752 * Send SNS command.
1753 *
1754 * Input:
1755 * ha = adapter block pointer.
1756 * sns = pointer for command.
1757 * cmd_size = command size.
1758 * buf_size = response/command size.
1759 * TARGET_QUEUE_LOCK must be released.
1760 * ADAPTER_STATE_LOCK must be released.
1761 *
1762 * Returns:
1763 * qla2x00 local function return status code.
1764 *
1765 * Context:
1766 * Kernel context.
1767 */
1768int
7b867cf7 1769qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
1da177e4
LT		 1770 uint16_t cmd_size, size_t buf_size)
1771{
1772 int rval;
1773 mbx_cmd_t mc;
1774 mbx_cmd_t *mcp = &mc;
1775
5f28d2d7
SK		 1776 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
1777 "Entered %s.\n", __func__);
1da177e4 1778
5f28d2d7 1779 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
7c3df132
SK		 1780 "Retry cnt=%d ratov=%d total tov=%d.\n",
1781 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
1da177e4
LT		 1782
1783 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
1784 mcp->mb[1] = cmd_size;
1785 mcp->mb[2] = MSW(sns_phys_address);
1786 mcp->mb[3] = LSW(sns_phys_address);
1787 mcp->mb[6] = MSW(MSD(sns_phys_address));
1788 mcp->mb[7] = LSW(MSD(sns_phys_address));
1789 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1790 mcp->in_mb = MBX_0|MBX_1;
1791 mcp->buf_size = buf_size;
1792 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
7b867cf7
AC		 1793 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
1794 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1795
1796 if (rval != QLA_SUCCESS) {
1797 /*EMPTY*/
7c3df132
SK		 1798 ql_dbg(ql_dbg_mbx, vha, 0x105f,
1799 "Failed=%x mb[0]=%x mb[1]=%x.\n",
1800 rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 1801 } else {
1802 /*EMPTY*/
5f28d2d7
SK		 1803 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
1804 "Done %s.\n", __func__);
1da177e4
LT		 1805 }
1806
1807 return rval;
1808}
1809
1c7c6357 1810int
7b867cf7 1811qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 1812 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
1813{
1814 int rval;
1815
1816 struct logio_entry_24xx *lg;
1817 dma_addr_t lg_dma;
1818 uint32_t iop[2];
7b867cf7 1819 struct qla_hw_data *ha = vha->hw;
2afa19a9
AC		 1820 struct req_que *req;
1821 struct rsp_que *rsp;
1c7c6357 1822
5f28d2d7
SK		 1823 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
1824 "Entered %s.\n", __func__);
1c7c6357 1825
7163ea81 1826 if (ha->flags.cpu_affinity_enabled)
68ca949c
AC		 1827 req = ha->req_q_map[0];
1828 else
1829 req = vha->req;
2afa19a9
AC		 1830 rsp = req->rsp;
1831
1c7c6357
AV		 1832 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1833 if (lg == NULL) {
7c3df132
SK		 1834 ql_log(ql_log_warn, vha, 0x1062,
1835 "Failed to allocate login IOCB.\n");
1c7c6357
AV		 1836 return QLA_MEMORY_ALLOC_FAILED;
1837 }
1838 memset(lg, 0, sizeof(struct logio_entry_24xx));
1839
1840 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
1841 lg->entry_count = 1;
2afa19a9 1842 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357
AV		 1843 lg->nport_handle = cpu_to_le16(loop_id);
1844 lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI);
1845 if (opt & BIT_0)
1846 lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI);
8baa51a6
AV		 1847 if (opt & BIT_1)
1848 lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI);
1c7c6357
AV		 1849 lg->port_id[0] = al_pa;
1850 lg->port_id[1] = area;
1851 lg->port_id[2] = domain;
7b867cf7 1852 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 1853 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
1854 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 1855 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1856 ql_dbg(ql_dbg_mbx, vha, 0x1063,
1857 "Failed to issue login IOCB (%x).\n", rval);
1c7c6357 1858 } else if (lg->entry_status != 0) {
7c3df132
SK		 1859 ql_dbg(ql_dbg_mbx, vha, 0x1064,
1860 "Failed to complete IOCB -- error status (%x).\n",
1861 lg->entry_status);
1c7c6357
AV		 1862 rval = QLA_FUNCTION_FAILED;
1863 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
1864 iop[0] = le32_to_cpu(lg->io_parameter[0]);
1865 iop[1] = le32_to_cpu(lg->io_parameter[1]);
1866
7c3df132
SK		 1867 ql_dbg(ql_dbg_mbx, vha, 0x1065,
1868 "Failed to complete IOCB -- completion status (%x) "
1869 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1870 iop[0], iop[1]);
1c7c6357
AV		 1871
1872 switch (iop[0]) {
1873 case LSC_SCODE_PORTID_USED:
1874 mb[0] = MBS_PORT_ID_USED;
1875 mb[1] = LSW(iop[1]);
1876 break;
1877 case LSC_SCODE_NPORT_USED:
1878 mb[0] = MBS_LOOP_ID_USED;
1879 break;
1880 case LSC_SCODE_NOLINK:
1881 case LSC_SCODE_NOIOCB:
1882 case LSC_SCODE_NOXCB:
1883 case LSC_SCODE_CMD_FAILED:
1884 case LSC_SCODE_NOFABRIC:
1885 case LSC_SCODE_FW_NOT_READY:
1886 case LSC_SCODE_NOT_LOGGED_IN:
1887 case LSC_SCODE_NOPCB:
1888 case LSC_SCODE_ELS_REJECT:
1889 case LSC_SCODE_CMD_PARAM_ERR:
1890 case LSC_SCODE_NONPORT:
1891 case LSC_SCODE_LOGGED_IN:
1892 case LSC_SCODE_NOFLOGI_ACC:
1893 default:
1894 mb[0] = MBS_COMMAND_ERROR;
1895 break;
1896 }
1897 } else {
5f28d2d7
SK		 1898 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
1899 "Done %s.\n", __func__);
1c7c6357
AV		 1900
1901 iop[0] = le32_to_cpu(lg->io_parameter[0]);
1902
1903 mb[0] = MBS_COMMAND_COMPLETE;
1904 mb[1] = 0;
1905 if (iop[0] & BIT_4) {
1906 if (iop[0] & BIT_8)
1907 mb[1] |= BIT_1;
1908 } else
1909 mb[1] = BIT_0;
ad3e0eda
AV		 1910
1911 /* Passback COS information. */
1912 mb[10] = 0;
1913 if (lg->io_parameter[7] || lg->io_parameter[8])
1914 mb[10] |= BIT_0; /* Class 2. */
1915 if (lg->io_parameter[9] || lg->io_parameter[10])
1916 mb[10] |= BIT_1; /* Class 3. */
2d70c103
NB		 1917 if (lg->io_parameter[0] & __constant_cpu_to_le32(BIT_7))
1918 mb[10] |= BIT_7; /* Confirmed Completion
1919 * Allowed
1920 */
1c7c6357
AV		 1921 }
1922
1923 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
1924
1925 return rval;
1926}
1927
1da177e4
LT		 1928/*
1929 * qla2x00_login_fabric
1930 * Issue login fabric port mailbox command.
1931 *
1932 * Input:
1933 * ha = adapter block pointer.
1934 * loop_id = device loop ID.
1935 * domain = device domain.
1936 * area = device area.
1937 * al_pa = device AL_PA.
1938 * status = pointer for return status.
1939 * opt = command options.
1940 * TARGET_QUEUE_LOCK must be released.
1941 * ADAPTER_STATE_LOCK must be released.
1942 *
1943 * Returns:
1944 * qla2x00 local function return status code.
1945 *
1946 * Context:
1947 * Kernel context.
1948 */
1949int
7b867cf7 1950qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1da177e4
LT		 1951 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
1952{
1953 int rval;
1954 mbx_cmd_t mc;
1955 mbx_cmd_t *mcp = &mc;
7b867cf7 1956 struct qla_hw_data *ha = vha->hw;
1da177e4 1957
5f28d2d7
SK		 1958 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
1959 "Entered %s.\n", __func__);
1da177e4
LT		 1960
1961 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
1962 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1963 if (HAS_EXTENDED_IDS(ha)) {
1964 mcp->mb[1] = loop_id;
1965 mcp->mb[10] = opt;
1966 mcp->out_mb |= MBX_10;
1967 } else {
1968 mcp->mb[1] = (loop_id << 8) | opt;
1969 }
1970 mcp->mb[2] = domain;
1971 mcp->mb[3] = area << 8 | al_pa;
1972
1973 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
1974 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
1975 mcp->flags = 0;
7b867cf7 1976 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1977
1978 /* Return mailbox statuses. */
1979 if (mb != NULL) {
1980 mb[0] = mcp->mb[0];
1981 mb[1] = mcp->mb[1];
1982 mb[2] = mcp->mb[2];
1983 mb[6] = mcp->mb[6];
1984 mb[7] = mcp->mb[7];
ad3e0eda
AV		 1985 /* COS retrieved from Get-Port-Database mailbox command. */
1986 mb[10] = 0;
1da177e4
LT		 1987 }
1988
1989 if (rval != QLA_SUCCESS) {
1990 /* RLU tmp code: need to change main mailbox_command function to
1991 * return ok even when the mailbox completion value is not
1992 * SUCCESS. The caller needs to be responsible to interpret
1993 * the return values of this mailbox command if we're not
1994 * to change too much of the existing code.
1995 */
1996 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
1997 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
1998 mcp->mb[0] == 0x4006)
1999 rval = QLA_SUCCESS;
2000
2001 /*EMPTY*/
7c3df132
SK		 2002 ql_dbg(ql_dbg_mbx, vha, 0x1068,
2003 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
2004 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1da177e4
LT		 2005 } else {
2006 /*EMPTY*/
5f28d2d7
SK		 2007 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
2008 "Done %s.\n", __func__);
1da177e4
LT		 2009 }
2010
2011 return rval;
2012}
2013
2014/*
2015 * qla2x00_login_local_device
2016 * Issue login loop port mailbox command.
fa2a1ce5 2017 *
1da177e4
LT		 2018 * Input:
2019 * ha = adapter block pointer.
2020 * loop_id = device loop ID.
2021 * opt = command options.
fa2a1ce5 2022 *
1da177e4
LT		 2023 * Returns:
2024 * Return status code.
fa2a1ce5 2025 *
1da177e4
LT		 2026 * Context:
2027 * Kernel context.
fa2a1ce5 2028 *
1da177e4
LT		 2029 */
2030int
7b867cf7 2031qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 2032 uint16_t *mb_ret, uint8_t opt)
2033{
2034 int rval;
2035 mbx_cmd_t mc;
2036 mbx_cmd_t *mcp = &mc;
7b867cf7 2037 struct qla_hw_data *ha = vha->hw;
1da177e4 2038
5f28d2d7
SK		 2039 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
2040 "Entered %s.\n", __func__);
7c3df132 2041
e428924c 2042 if (IS_FWI2_CAPABLE(ha))
7b867cf7 2043 return qla24xx_login_fabric(vha, fcport->loop_id,
9a52a57c 2044 fcport->d_id.b.domain, fcport->d_id.b.area,
2045 fcport->d_id.b.al_pa, mb_ret, opt);
2046
1da177e4
LT		 2047 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
2048 if (HAS_EXTENDED_IDS(ha))
9a52a57c 2049 mcp->mb[1] = fcport->loop_id;
1da177e4 2050 else
9a52a57c 2051 mcp->mb[1] = fcport->loop_id << 8;
1da177e4
LT		 2052 mcp->mb[2] = opt;
2053 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2054 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
2055 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2056 mcp->flags = 0;
7b867cf7 2057 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2058
2059 /* Return mailbox statuses. */
2060 if (mb_ret != NULL) {
2061 mb_ret[0] = mcp->mb[0];
2062 mb_ret[1] = mcp->mb[1];
2063 mb_ret[6] = mcp->mb[6];
2064 mb_ret[7] = mcp->mb[7];
2065 }
2066
2067 if (rval != QLA_SUCCESS) {
2068 /* AV tmp code: need to change main mailbox_command function to
2069 * return ok even when the mailbox completion value is not
2070 * SUCCESS. The caller needs to be responsible to interpret
2071 * the return values of this mailbox command if we're not
2072 * to change too much of the existing code.
2073 */
2074 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
2075 rval = QLA_SUCCESS;
2076
7c3df132
SK		 2077 ql_dbg(ql_dbg_mbx, vha, 0x106b,
2078 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
2079 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
1da177e4
LT		 2080 } else {
2081 /*EMPTY*/
5f28d2d7
SK		 2082 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
2083 "Done %s.\n", __func__);
1da177e4
LT		 2084 }
2085
2086 return (rval);
2087}
2088
1c7c6357 2089int
7b867cf7 2090qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 2091 uint8_t area, uint8_t al_pa)
2092{
2093 int rval;
2094 struct logio_entry_24xx *lg;
2095 dma_addr_t lg_dma;
7b867cf7 2096 struct qla_hw_data *ha = vha->hw;
2afa19a9
AC		 2097 struct req_que *req;
2098 struct rsp_que *rsp;
1c7c6357 2099
5f28d2d7
SK		 2100 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
2101 "Entered %s.\n", __func__);
1c7c6357
AV		 2102
2103 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
2104 if (lg == NULL) {
7c3df132
SK		 2105 ql_log(ql_log_warn, vha, 0x106e,
2106 "Failed to allocate logout IOCB.\n");
1c7c6357
AV		 2107 return QLA_MEMORY_ALLOC_FAILED;
2108 }
2109 memset(lg, 0, sizeof(struct logio_entry_24xx));
2110
2afa19a9
AC		 2111 if (ql2xmaxqueues > 1)
2112 req = ha->req_q_map[0];
2113 else
2114 req = vha->req;
2115 rsp = req->rsp;
1c7c6357
AV		 2116 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2117 lg->entry_count = 1;
2afa19a9 2118 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357
AV		 2119 lg->nport_handle = cpu_to_le16(loop_id);
2120 lg->control_flags =
c8d6691b
AV		 2121 __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
2122 LCF_FREE_NPORT);
1c7c6357
AV		 2123 lg->port_id[0] = al_pa;
2124 lg->port_id[1] = area;
2125 lg->port_id[2] = domain;
7b867cf7 2126 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 2127 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2128 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 2129 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2130 ql_dbg(ql_dbg_mbx, vha, 0x106f,
2131 "Failed to issue logout IOCB (%x).\n", rval);
1c7c6357 2132 } else if (lg->entry_status != 0) {
7c3df132
SK		 2133 ql_dbg(ql_dbg_mbx, vha, 0x1070,
2134 "Failed to complete IOCB -- error status (%x).\n",
2135 lg->entry_status);
1c7c6357
AV		 2136 rval = QLA_FUNCTION_FAILED;
2137 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 2138 ql_dbg(ql_dbg_mbx, vha, 0x1071,
2139 "Failed to complete IOCB -- completion status (%x) "
2140 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1c7c6357 2141 le32_to_cpu(lg->io_parameter[0]),
7c3df132 2142 le32_to_cpu(lg->io_parameter[1]));
1c7c6357
AV		 2143 } else {
2144 /*EMPTY*/
5f28d2d7
SK		 2145 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
2146 "Done %s.\n", __func__);
1c7c6357
AV		 2147 }
2148
2149 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2150
2151 return rval;
2152}
2153
1da177e4
LT		 2154/*
2155 * qla2x00_fabric_logout
2156 * Issue logout fabric port mailbox command.
2157 *
2158 * Input:
2159 * ha = adapter block pointer.
2160 * loop_id = device loop ID.
2161 * TARGET_QUEUE_LOCK must be released.
2162 * ADAPTER_STATE_LOCK must be released.
2163 *
2164 * Returns:
2165 * qla2x00 local function return status code.
2166 *
2167 * Context:
2168 * Kernel context.
2169 */
2170int
7b867cf7 2171qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357 2172 uint8_t area, uint8_t al_pa)
1da177e4
LT		 2173{
2174 int rval;
2175 mbx_cmd_t mc;
2176 mbx_cmd_t *mcp = &mc;
2177
5f28d2d7
SK		 2178 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
2179 "Entered %s.\n", __func__);
1da177e4
LT		 2180
2181 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
2182 mcp->out_mb = MBX_1|MBX_0;
7b867cf7 2183 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 2184 mcp->mb[1] = loop_id;
2185 mcp->mb[10] = 0;
2186 mcp->out_mb |= MBX_10;
2187 } else {
2188 mcp->mb[1] = loop_id << 8;
2189 }
2190
2191 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2192 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2193 mcp->flags = 0;
7b867cf7 2194 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2195
2196 if (rval != QLA_SUCCESS) {
2197 /*EMPTY*/
7c3df132
SK		 2198 ql_dbg(ql_dbg_mbx, vha, 0x1074,
2199 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
1da177e4
LT		 2200 } else {
2201 /*EMPTY*/
5f28d2d7
SK		 2202 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
2203 "Done %s.\n", __func__);
1da177e4
LT		 2204 }
2205
2206 return rval;
2207}
2208
2209/*
2210 * qla2x00_full_login_lip
2211 * Issue full login LIP mailbox command.
2212 *
2213 * Input:
2214 * ha = adapter block pointer.
2215 * TARGET_QUEUE_LOCK must be released.
2216 * ADAPTER_STATE_LOCK must be released.
2217 *
2218 * Returns:
2219 * qla2x00 local function return status code.
2220 *
2221 * Context:
2222 * Kernel context.
2223 */
2224int
7b867cf7 2225qla2x00_full_login_lip(scsi_qla_host_t *vha)
1da177e4
LT		 2226{
2227 int rval;
2228 mbx_cmd_t mc;
2229 mbx_cmd_t *mcp = &mc;
2230
5f28d2d7
SK		 2231 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
2232 "Entered %s.\n", __func__);
1da177e4
LT		 2233
2234 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
7b867cf7 2235 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
0c8c39af 2236 mcp->mb[2] = 0;
1da177e4
LT		 2237 mcp->mb[3] = 0;
2238 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2239 mcp->in_mb = MBX_0;
b93480e3 2240 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2241 mcp->flags = 0;
7b867cf7 2242 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2243
2244 if (rval != QLA_SUCCESS) {
2245 /*EMPTY*/
7c3df132 2246 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
1da177e4
LT		 2247 } else {
2248 /*EMPTY*/
5f28d2d7
SK		 2249 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
2250 "Done %s.\n", __func__);
1da177e4
LT		 2251 }
2252
2253 return rval;
2254}
2255
2256/*
2257 * qla2x00_get_id_list
2258 *
2259 * Input:
2260 * ha = adapter block pointer.
2261 *
2262 * Returns:
2263 * qla2x00 local function return status code.
2264 *
2265 * Context:
2266 * Kernel context.
2267 */
2268int
7b867cf7 2269qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
1da177e4
LT		 2270 uint16_t *entries)
2271{
2272 int rval;
2273 mbx_cmd_t mc;
2274 mbx_cmd_t *mcp = &mc;
2275
5f28d2d7
SK		 2276 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
2277 "Entered %s.\n", __func__);
1da177e4
LT		 2278
2279 if (id_list == NULL)
2280 return QLA_FUNCTION_FAILED;
2281
2282 mcp->mb[0] = MBC_GET_ID_LIST;
1c7c6357 2283 mcp->out_mb = MBX_0;
7b867cf7 2284 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 2285 mcp->mb[2] = MSW(id_list_dma);
2286 mcp->mb[3] = LSW(id_list_dma);
2287 mcp->mb[6] = MSW(MSD(id_list_dma));
2288 mcp->mb[7] = LSW(MSD(id_list_dma));
247ec457 2289 mcp->mb[8] = 0;
7b867cf7 2290 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 2291 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
1c7c6357
AV		 2292 } else {
2293 mcp->mb[1] = MSW(id_list_dma);
2294 mcp->mb[2] = LSW(id_list_dma);
2295 mcp->mb[3] = MSW(MSD(id_list_dma));
2296 mcp->mb[6] = LSW(MSD(id_list_dma));
2297 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
2298 }
1da177e4 2299 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2300 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2301 mcp->flags = 0;
7b867cf7 2302 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2303
2304 if (rval != QLA_SUCCESS) {
2305 /*EMPTY*/
7c3df132 2306 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
1da177e4
LT		 2307 } else {
2308 *entries = mcp->mb[1];
5f28d2d7
SK		 2309 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
2310 "Done %s.\n", __func__);
1da177e4
LT		 2311 }
2312
2313 return rval;
2314}
2315
2316/*
2317 * qla2x00_get_resource_cnts
2318 * Get current firmware resource counts.
2319 *
2320 * Input:
2321 * ha = adapter block pointer.
2322 *
2323 * Returns:
2324 * qla2x00 local function return status code.
2325 *
2326 * Context:
2327 * Kernel context.
2328 */
2329int
7b867cf7 2330qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
4d0ea247 2331 uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt,
f3a0a77e 2332 uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs)
1da177e4
LT		 2333{
2334 int rval;
2335 mbx_cmd_t mc;
2336 mbx_cmd_t *mcp = &mc;
2337
5f28d2d7
SK		 2338 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
2339 "Entered %s.\n", __func__);
1da177e4
LT		 2340
2341 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2342 mcp->out_mb = MBX_0;
4d0ea247 2343 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6246b8a1 2344 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw))
f3a0a77e 2345 mcp->in_mb |= MBX_12;
b93480e3 2346 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2347 mcp->flags = 0;
7b867cf7 2348 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2349
2350 if (rval != QLA_SUCCESS) {
2351 /*EMPTY*/
7c3df132
SK		 2352 ql_dbg(ql_dbg_mbx, vha, 0x107d,
2353 "Failed mb[0]=%x.\n", mcp->mb[0]);
1da177e4 2354 } else {
5f28d2d7 2355 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
7c3df132
SK		 2356 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
2357 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
2358 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
2359 mcp->mb[11], mcp->mb[12]);
1da177e4
LT		 2360
2361 if (cur_xchg_cnt)
2362 *cur_xchg_cnt = mcp->mb[3];
2363 if (orig_xchg_cnt)
2364 *orig_xchg_cnt = mcp->mb[6];
2365 if (cur_iocb_cnt)
2366 *cur_iocb_cnt = mcp->mb[7];
2367 if (orig_iocb_cnt)
2368 *orig_iocb_cnt = mcp->mb[10];
7b867cf7 2369 if (vha->hw->flags.npiv_supported && max_npiv_vports)
4d0ea247 2370 *max_npiv_vports = mcp->mb[11];
6246b8a1 2371 if ((IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw)) && max_fcfs)
f3a0a77e 2372 *max_fcfs = mcp->mb[12];
1da177e4
LT		 2373 }
2374
2375 return (rval);
2376}
2377
1da177e4
LT		 2378/*
2379 * qla2x00_get_fcal_position_map
2380 * Get FCAL (LILP) position map using mailbox command
2381 *
2382 * Input:
2383 * ha = adapter state pointer.
2384 * pos_map = buffer pointer (can be NULL).
2385 *
2386 * Returns:
2387 * qla2x00 local function return status code.
2388 *
2389 * Context:
2390 * Kernel context.
2391 */
2392int
7b867cf7 2393qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
1da177e4
LT		 2394{
2395 int rval;
2396 mbx_cmd_t mc;
2397 mbx_cmd_t *mcp = &mc;
2398 char *pmap;
2399 dma_addr_t pmap_dma;
7b867cf7 2400 struct qla_hw_data *ha = vha->hw;
1da177e4 2401
5f28d2d7
SK		 2402 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
2403 "Entered %s.\n", __func__);
7c3df132 2404
4b89258c 2405 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
1da177e4 2406 if (pmap == NULL) {
7c3df132
SK		 2407 ql_log(ql_log_warn, vha, 0x1080,
2408 "Memory alloc failed.\n");
1da177e4
LT		 2409 return QLA_MEMORY_ALLOC_FAILED;
2410 }
2411 memset(pmap, 0, FCAL_MAP_SIZE);
2412
2413 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
2414 mcp->mb[2] = MSW(pmap_dma);
2415 mcp->mb[3] = LSW(pmap_dma);
2416 mcp->mb[6] = MSW(MSD(pmap_dma));
2417 mcp->mb[7] = LSW(MSD(pmap_dma));
2418 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2419 mcp->in_mb = MBX_1|MBX_0;
2420 mcp->buf_size = FCAL_MAP_SIZE;
2421 mcp->flags = MBX_DMA_IN;
2422 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 2423 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2424
2425 if (rval == QLA_SUCCESS) {
5f28d2d7 2426 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
7c3df132
SK		 2427 "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
2428 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
2429 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
2430 pmap, pmap[0] + 1);
1da177e4
LT		 2431
2432 if (pos_map)
2433 memcpy(pos_map, pmap, FCAL_MAP_SIZE);
2434 }
2435 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
2436
2437 if (rval != QLA_SUCCESS) {
7c3df132 2438 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
1da177e4 2439 } else {
5f28d2d7
SK		 2440 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
2441 "Done %s.\n", __func__);
1da177e4
LT		 2442 }
2443
2444 return rval;
2445}
392e2f65 2446
2447/*
2448 * qla2x00_get_link_status
2449 *
2450 * Input:
2451 * ha = adapter block pointer.
2452 * loop_id = device loop ID.
2453 * ret_buf = pointer to link status return buffer.
2454 *
2455 * Returns:
2456 * 0 = success.
2457 * BIT_0 = mem alloc error.
2458 * BIT_1 = mailbox error.
2459 */
2460int
7b867cf7 2461qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
43ef0580 2462 struct link_statistics *stats, dma_addr_t stats_dma)
392e2f65 2463{
2464 int rval;
2465 mbx_cmd_t mc;
2466 mbx_cmd_t *mcp = &mc;
43ef0580 2467 uint32_t *siter, *diter, dwords;
7b867cf7 2468 struct qla_hw_data *ha = vha->hw;
392e2f65 2469
5f28d2d7
SK		 2470 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
2471 "Entered %s.\n", __func__);
392e2f65 2472
392e2f65 2473 mcp->mb[0] = MBC_GET_LINK_STATUS;
43ef0580
AV		 2474 mcp->mb[2] = MSW(stats_dma);
2475 mcp->mb[3] = LSW(stats_dma);
2476 mcp->mb[6] = MSW(MSD(stats_dma));
2477 mcp->mb[7] = LSW(MSD(stats_dma));
392e2f65 2478 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2479 mcp->in_mb = MBX_0;
e428924c 2480 if (IS_FWI2_CAPABLE(ha)) {
392e2f65 2481 mcp->mb[1] = loop_id;
2482 mcp->mb[4] = 0;
2483 mcp->mb[10] = 0;
2484 mcp->out_mb |= MBX_10|MBX_4|MBX_1;
2485 mcp->in_mb |= MBX_1;
2486 } else if (HAS_EXTENDED_IDS(ha)) {
2487 mcp->mb[1] = loop_id;
2488 mcp->mb[10] = 0;
2489 mcp->out_mb |= MBX_10|MBX_1;
2490 } else {
2491 mcp->mb[1] = loop_id << 8;
2492 mcp->out_mb |= MBX_1;
2493 }
b93480e3 2494 mcp->tov = MBX_TOV_SECONDS;
392e2f65 2495 mcp->flags = IOCTL_CMD;
7b867cf7 2496 rval = qla2x00_mailbox_command(vha, mcp);
392e2f65 2497
2498 if (rval == QLA_SUCCESS) {
2499 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 2500 ql_dbg(ql_dbg_mbx, vha, 0x1085,
2501 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
43ef0580 2502 rval = QLA_FUNCTION_FAILED;
392e2f65 2503 } else {
43ef0580 2504 /* Copy over data -- firmware data is LE. */
5f28d2d7
SK		 2505 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
2506 "Done %s.\n", __func__);
43ef0580
AV		 2507 dwords = offsetof(struct link_statistics, unused1) / 4;
2508 siter = diter = &stats->link_fail_cnt;
2509 while (dwords--)
2510 *diter++ = le32_to_cpu(*siter++);
392e2f65 2511 }
2512 } else {
2513 /* Failed. */
7c3df132 2514 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
392e2f65 2515 }
2516
392e2f65 2517 return rval;
2518}
2519
2520int
7b867cf7 2521qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
43ef0580 2522 dma_addr_t stats_dma)
1c7c6357
AV		 2523{
2524 int rval;
2525 mbx_cmd_t mc;
2526 mbx_cmd_t *mcp = &mc;
43ef0580 2527 uint32_t *siter, *diter, dwords;
1c7c6357 2528
5f28d2d7
SK		 2529 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
2530 "Entered %s.\n", __func__);
1c7c6357 2531
1c7c6357 2532 mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;
43ef0580
AV		 2533 mcp->mb[2] = MSW(stats_dma);
2534 mcp->mb[3] = LSW(stats_dma);
2535 mcp->mb[6] = MSW(MSD(stats_dma));
2536 mcp->mb[7] = LSW(MSD(stats_dma));
2537 mcp->mb[8] = sizeof(struct link_statistics) / 4;
7b867cf7 2538 mcp->mb[9] = vha->vp_idx;
1c7c6357 2539 mcp->mb[10] = 0;
43ef0580 2540 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1c7c6357 2541 mcp->in_mb = MBX_2|MBX_1|MBX_0;
b93480e3 2542 mcp->tov = MBX_TOV_SECONDS;
1c7c6357 2543 mcp->flags = IOCTL_CMD;
7b867cf7 2544 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 2545
2546 if (rval == QLA_SUCCESS) {
2547 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 2548 ql_dbg(ql_dbg_mbx, vha, 0x1089,
2549 "Failed mb[0]=%x.\n", mcp->mb[0]);
43ef0580 2550 rval = QLA_FUNCTION_FAILED;
1c7c6357 2551 } else {
5f28d2d7
SK		 2552 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
2553 "Done %s.\n", __func__);
1c7c6357 2554 /* Copy over data -- firmware data is LE. */
43ef0580
AV		 2555 dwords = sizeof(struct link_statistics) / 4;
2556 siter = diter = &stats->link_fail_cnt;
1c7c6357 2557 while (dwords--)
43ef0580 2558 *diter++ = le32_to_cpu(*siter++);
1c7c6357
AV		 2559 }
2560 } else {
2561 /* Failed. */
7c3df132 2562 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
1c7c6357
AV		 2563 }
2564
1c7c6357
AV		 2565 return rval;
2566}
1c7c6357
AV		 2567
2568int
2afa19a9 2569qla24xx_abort_command(srb_t *sp)
1c7c6357
AV		 2570{
2571 int rval;
1c7c6357
AV		 2572 unsigned long flags = 0;
2573
2574 struct abort_entry_24xx *abt;
2575 dma_addr_t abt_dma;
2576 uint32_t handle;
2afa19a9
AC		 2577 fc_port_t *fcport = sp->fcport;
2578 struct scsi_qla_host *vha = fcport->vha;
7b867cf7 2579 struct qla_hw_data *ha = vha->hw;
67c2e93a 2580 struct req_que *req = vha->req;
1c7c6357 2581
5f28d2d7
SK		 2582 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
2583 "Entered %s.\n", __func__);
1c7c6357 2584
7b867cf7 2585 spin_lock_irqsave(&ha->hardware_lock, flags);
8d93f550 2586 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 2587 if (req->outstanding_cmds[handle] == sp)
1c7c6357
AV		 2588 break;
2589 }
7b867cf7 2590 spin_unlock_irqrestore(&ha->hardware_lock, flags);
8d93f550 2591 if (handle == req->num_outstanding_cmds) {
1c7c6357
AV		 2592 /* Command not found. */
2593 return QLA_FUNCTION_FAILED;
2594 }
2595
2596 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
2597 if (abt == NULL) {
7c3df132
SK		 2598 ql_log(ql_log_warn, vha, 0x108d,
2599 "Failed to allocate abort IOCB.\n");
1c7c6357
AV		 2600 return QLA_MEMORY_ALLOC_FAILED;
2601 }
2602 memset(abt, 0, sizeof(struct abort_entry_24xx));
2603
2604 abt->entry_type = ABORT_IOCB_TYPE;
2605 abt->entry_count = 1;
2afa19a9 2606 abt->handle = MAKE_HANDLE(req->id, abt->handle);
1c7c6357 2607 abt->nport_handle = cpu_to_le16(fcport->loop_id);
a74ec14f 2608 abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
1c7c6357
AV		 2609 abt->port_id[0] = fcport->d_id.b.al_pa;
2610 abt->port_id[1] = fcport->d_id.b.area;
2611 abt->port_id[2] = fcport->d_id.b.domain;
c6d39e23 2612 abt->vp_index = fcport->vha->vp_idx;
73208dfd
AC		 2613
2614 abt->req_que_no = cpu_to_le16(req->id);
2615
7b867cf7 2616 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
1c7c6357 2617 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2618 ql_dbg(ql_dbg_mbx, vha, 0x108e,
2619 "Failed to issue IOCB (%x).\n", rval);
1c7c6357 2620 } else if (abt->entry_status != 0) {
7c3df132
SK		 2621 ql_dbg(ql_dbg_mbx, vha, 0x108f,
2622 "Failed to complete IOCB -- error status (%x).\n",
2623 abt->entry_status);
1c7c6357
AV		 2624 rval = QLA_FUNCTION_FAILED;
2625 } else if (abt->nport_handle != __constant_cpu_to_le16(0)) {
7c3df132
SK		 2626 ql_dbg(ql_dbg_mbx, vha, 0x1090,
2627 "Failed to complete IOCB -- completion status (%x).\n",
2628 le16_to_cpu(abt->nport_handle));
1c7c6357
AV		 2629 rval = QLA_FUNCTION_FAILED;
2630 } else {
5f28d2d7
SK		 2631 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
2632 "Done %s.\n", __func__);
1c7c6357
AV		 2633 }
2634
2635 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
2636
2637 return rval;
2638}
2639
2640struct tsk_mgmt_cmd {
2641 union {
2642 struct tsk_mgmt_entry tsk;
2643 struct sts_entry_24xx sts;
2644 } p;
2645};
2646
523ec773
AV		 2647static int
2648__qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
2afa19a9 2649 unsigned int l, int tag)
1c7c6357 2650{
523ec773 2651 int rval, rval2;
1c7c6357 2652 struct tsk_mgmt_cmd *tsk;
9ca1d01f 2653 struct sts_entry_24xx *sts;
1c7c6357 2654 dma_addr_t tsk_dma;
7b867cf7
AC		 2655 scsi_qla_host_t *vha;
2656 struct qla_hw_data *ha;
73208dfd
AC		 2657 struct req_que *req;
2658 struct rsp_que *rsp;
1c7c6357 2659
7b867cf7
AC		 2660 vha = fcport->vha;
2661 ha = vha->hw;
2afa19a9 2662 req = vha->req;
7c3df132 2663
5f28d2d7
SK		 2664 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
2665 "Entered %s.\n", __func__);
7c3df132 2666
7163ea81 2667 if (ha->flags.cpu_affinity_enabled)
68ca949c
AC		 2668 rsp = ha->rsp_q_map[tag + 1];
2669 else
2670 rsp = req->rsp;
7b867cf7 2671 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
1c7c6357 2672 if (tsk == NULL) {
7c3df132
SK		 2673 ql_log(ql_log_warn, vha, 0x1093,
2674 "Failed to allocate task management IOCB.\n");
1c7c6357
AV		 2675 return QLA_MEMORY_ALLOC_FAILED;
2676 }
2677 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
2678
2679 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
2680 tsk->p.tsk.entry_count = 1;
2afa19a9 2681 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
1c7c6357 2682 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
00a537b8 2683 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
523ec773 2684 tsk->p.tsk.control_flags = cpu_to_le32(type);
1c7c6357
AV		 2685 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
2686 tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
2687 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
c6d39e23 2688 tsk->p.tsk.vp_index = fcport->vha->vp_idx;
523ec773
AV		 2689 if (type == TCF_LUN_RESET) {
2690 int_to_scsilun(l, &tsk->p.tsk.lun);
2691 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
2692 sizeof(tsk->p.tsk.lun));
2693 }
2c3dfe3f 2694
9ca1d01f 2695 sts = &tsk->p.sts;
7b867cf7 2696 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
1c7c6357 2697 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2698 ql_dbg(ql_dbg_mbx, vha, 0x1094,
2699 "Failed to issue %s reset IOCB (%x).\n", name, rval);
9ca1d01f 2700 } else if (sts->entry_status != 0) {
7c3df132
SK		 2701 ql_dbg(ql_dbg_mbx, vha, 0x1095,
2702 "Failed to complete IOCB -- error status (%x).\n",
2703 sts->entry_status);
1c7c6357 2704 rval = QLA_FUNCTION_FAILED;
9ca1d01f 2705 } else if (sts->comp_status !=
1c7c6357 2706 __constant_cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 2707 ql_dbg(ql_dbg_mbx, vha, 0x1096,
2708 "Failed to complete IOCB -- completion status (%x).\n",
2709 le16_to_cpu(sts->comp_status));
9ca1d01f 2710 rval = QLA_FUNCTION_FAILED;
97dec564
AV		 2711 } else if (le16_to_cpu(sts->scsi_status) &
2712 SS_RESPONSE_INFO_LEN_VALID) {
2713 if (le32_to_cpu(sts->rsp_data_len) < 4) {
5f28d2d7 2714 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
7c3df132
SK		 2715 "Ignoring inconsistent data length -- not enough "
2716 "response info (%d).\n",
2717 le32_to_cpu(sts->rsp_data_len));
97dec564 2718 } else if (sts->data[3]) {
7c3df132
SK		 2719 ql_dbg(ql_dbg_mbx, vha, 0x1098,
2720 "Failed to complete IOCB -- response (%x).\n",
2721 sts->data[3]);
97dec564
AV		 2722 rval = QLA_FUNCTION_FAILED;
2723 }
1c7c6357
AV		 2724 }
2725
2726 /* Issue marker IOCB. */
73208dfd 2727 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
523ec773
AV		 2728 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
2729 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 2730 ql_dbg(ql_dbg_mbx, vha, 0x1099,
2731 "Failed to issue marker IOCB (%x).\n", rval2);
1c7c6357 2732 } else {
5f28d2d7
SK		 2733 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
2734 "Done %s.\n", __func__);
1c7c6357
AV		 2735 }
2736
7b867cf7 2737 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
1c7c6357
AV		 2738
2739 return rval;
2740}
2741
523ec773 2742int
2afa19a9 2743qla24xx_abort_target(struct fc_port *fcport, unsigned int l, int tag)
523ec773 2744{
3822263e
MI		 2745 struct qla_hw_data *ha = fcport->vha->hw;
2746
2747 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
2748 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
2749
2afa19a9 2750 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
523ec773
AV		 2751}
2752
2753int
2afa19a9 2754qla24xx_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
523ec773 2755{
3822263e
MI		 2756 struct qla_hw_data *ha = fcport->vha->hw;
2757
2758 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
2759 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
2760
2afa19a9 2761 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
523ec773
AV		 2762}
2763
1c7c6357 2764int
7b867cf7 2765qla2x00_system_error(scsi_qla_host_t *vha)
1c7c6357
AV		 2766{
2767 int rval;
2768 mbx_cmd_t mc;
2769 mbx_cmd_t *mcp = &mc;
7b867cf7 2770 struct qla_hw_data *ha = vha->hw;
1c7c6357 2771
68af0811 2772 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 2773 return QLA_FUNCTION_FAILED;
2774
5f28d2d7
SK		 2775 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
2776 "Entered %s.\n", __func__);
1c7c6357
AV		 2777
2778 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
2779 mcp->out_mb = MBX_0;
2780 mcp->in_mb = MBX_0;
2781 mcp->tov = 5;
2782 mcp->flags = 0;
7b867cf7 2783 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 2784
2785 if (rval != QLA_SUCCESS) {
7c3df132 2786 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
1c7c6357 2787 } else {
5f28d2d7
SK		 2788 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
2789 "Done %s.\n", __func__);
1c7c6357
AV		 2790 }
2791
2792 return rval;
2793}
2794
1c7c6357
AV		 2795/**
2796 * qla2x00_set_serdes_params() -
2797 * @ha: HA context
2798 *
2799 * Returns
2800 */
2801int
7b867cf7 2802qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
1c7c6357
AV		 2803 uint16_t sw_em_2g, uint16_t sw_em_4g)
2804{
2805 int rval;
2806 mbx_cmd_t mc;
2807 mbx_cmd_t *mcp = &mc;
2808
5f28d2d7
SK		 2809 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
2810 "Entered %s.\n", __func__);
1c7c6357
AV		 2811
2812 mcp->mb[0] = MBC_SERDES_PARAMS;
2813 mcp->mb[1] = BIT_0;
fdbc6833 2814 mcp->mb[2] = sw_em_1g | BIT_15;
2815 mcp->mb[3] = sw_em_2g | BIT_15;
2816 mcp->mb[4] = sw_em_4g | BIT_15;
1c7c6357
AV		 2817 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
2818 mcp->in_mb = MBX_0;
b93480e3 2819 mcp->tov = MBX_TOV_SECONDS;
1c7c6357 2820 mcp->flags = 0;
7b867cf7 2821 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 2822
2823 if (rval != QLA_SUCCESS) {
2824 /*EMPTY*/
7c3df132
SK		 2825 ql_dbg(ql_dbg_mbx, vha, 0x109f,
2826 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357
AV		 2827 } else {
2828 /*EMPTY*/
5f28d2d7
SK		 2829 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
2830 "Done %s.\n", __func__);
1c7c6357
AV		 2831 }
2832
2833 return rval;
2834}
f6ef3b18
AV		 2835
2836int
7b867cf7 2837qla2x00_stop_firmware(scsi_qla_host_t *vha)
f6ef3b18
AV		 2838{
2839 int rval;
2840 mbx_cmd_t mc;
2841 mbx_cmd_t *mcp = &mc;
2842
7b867cf7 2843 if (!IS_FWI2_CAPABLE(vha->hw))
f6ef3b18
AV		 2844 return QLA_FUNCTION_FAILED;
2845
5f28d2d7
SK		 2846 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
2847 "Entered %s.\n", __func__);
f6ef3b18
AV		 2848
2849 mcp->mb[0] = MBC_STOP_FIRMWARE;
4ba988db
AV		 2850 mcp->mb[1] = 0;
2851 mcp->out_mb = MBX_1|MBX_0;
f6ef3b18
AV		 2852 mcp->in_mb = MBX_0;
2853 mcp->tov = 5;
2854 mcp->flags = 0;
7b867cf7 2855 rval = qla2x00_mailbox_command(vha, mcp);
f6ef3b18
AV		 2856
2857 if (rval != QLA_SUCCESS) {
7c3df132 2858 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
b469a7cb
AV		 2859 if (mcp->mb[0] == MBS_INVALID_COMMAND)
2860 rval = QLA_INVALID_COMMAND;
f6ef3b18 2861 } else {
5f28d2d7
SK		 2862 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
2863 "Done %s.\n", __func__);
f6ef3b18
AV		 2864 }
2865
2866 return rval;
2867}
a7a167bf
AV		 2868
2869int
7b867cf7 2870qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
a7a167bf
AV		 2871 uint16_t buffers)
2872{
2873 int rval;
2874 mbx_cmd_t mc;
2875 mbx_cmd_t *mcp = &mc;
2876
5f28d2d7
SK		 2877 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
2878 "Entered %s.\n", __func__);
7c3df132 2879
7b867cf7 2880 if (!IS_FWI2_CAPABLE(vha->hw))
a7a167bf
AV		 2881 return QLA_FUNCTION_FAILED;
2882
85880801
AV		 2883 if (unlikely(pci_channel_offline(vha->hw->pdev)))
2884 return QLA_FUNCTION_FAILED;
2885
a7a167bf 2886 mcp->mb[0] = MBC_TRACE_CONTROL;
00b6bd25
AV		 2887 mcp->mb[1] = TC_EFT_ENABLE;
2888 mcp->mb[2] = LSW(eft_dma);
2889 mcp->mb[3] = MSW(eft_dma);
2890 mcp->mb[4] = LSW(MSD(eft_dma));
2891 mcp->mb[5] = MSW(MSD(eft_dma));
2892 mcp->mb[6] = buffers;
2893 mcp->mb[7] = TC_AEN_DISABLE;
2894 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
a7a167bf 2895 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2896 mcp->tov = MBX_TOV_SECONDS;
a7a167bf 2897 mcp->flags = 0;
7b867cf7 2898 rval = qla2x00_mailbox_command(vha, mcp);
00b6bd25 2899 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2900 ql_dbg(ql_dbg_mbx, vha, 0x10a5,
2901 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2902 rval, mcp->mb[0], mcp->mb[1]);
00b6bd25 2903 } else {
5f28d2d7
SK		 2904 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
2905 "Done %s.\n", __func__);
00b6bd25
AV		 2906 }
2907
2908 return rval;
2909}
a7a167bf 2910
00b6bd25 2911int
7b867cf7 2912qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
00b6bd25
AV		 2913{
2914 int rval;
2915 mbx_cmd_t mc;
2916 mbx_cmd_t *mcp = &mc;
2917
5f28d2d7
SK		 2918 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
2919 "Entered %s.\n", __func__);
7c3df132 2920
7b867cf7 2921 if (!IS_FWI2_CAPABLE(vha->hw))
00b6bd25
AV		 2922 return QLA_FUNCTION_FAILED;
2923
85880801
AV		 2924 if (unlikely(pci_channel_offline(vha->hw->pdev)))
2925 return QLA_FUNCTION_FAILED;
2926
00b6bd25
AV		 2927 mcp->mb[0] = MBC_TRACE_CONTROL;
2928 mcp->mb[1] = TC_EFT_DISABLE;
2929 mcp->out_mb = MBX_1|MBX_0;
2930 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2931 mcp->tov = MBX_TOV_SECONDS;
00b6bd25 2932 mcp->flags = 0;
7b867cf7 2933 rval = qla2x00_mailbox_command(vha, mcp);
a7a167bf 2934 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2935 ql_dbg(ql_dbg_mbx, vha, 0x10a8,
2936 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2937 rval, mcp->mb[0], mcp->mb[1]);
a7a167bf 2938 } else {
5f28d2d7
SK		 2939 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
2940 "Done %s.\n", __func__);
a7a167bf
AV		 2941 }
2942
2943 return rval;
2944}
2945
df613b96 2946int
7b867cf7 2947qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
df613b96
AV		 2948 uint16_t buffers, uint16_t *mb, uint32_t *dwords)
2949{
2950 int rval;
2951 mbx_cmd_t mc;
2952 mbx_cmd_t *mcp = &mc;
2953
5f28d2d7
SK		 2954 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
2955 "Entered %s.\n", __func__);
7c3df132 2956
6246b8a1
GM		 2957 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
2958 !IS_QLA83XX(vha->hw))
df613b96
AV		 2959 return QLA_FUNCTION_FAILED;
2960
85880801
AV		 2961 if (unlikely(pci_channel_offline(vha->hw->pdev)))
2962 return QLA_FUNCTION_FAILED;
2963
df613b96
AV		 2964 mcp->mb[0] = MBC_TRACE_CONTROL;
2965 mcp->mb[1] = TC_FCE_ENABLE;
2966 mcp->mb[2] = LSW(fce_dma);
2967 mcp->mb[3] = MSW(fce_dma);
2968 mcp->mb[4] = LSW(MSD(fce_dma));
2969 mcp->mb[5] = MSW(MSD(fce_dma));
2970 mcp->mb[6] = buffers;
2971 mcp->mb[7] = TC_AEN_DISABLE;
2972 mcp->mb[8] = 0;
2973 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
2974 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
2975 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
2976 MBX_1|MBX_0;
2977 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 2978 mcp->tov = MBX_TOV_SECONDS;
df613b96 2979 mcp->flags = 0;
7b867cf7 2980 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 2981 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2982 ql_dbg(ql_dbg_mbx, vha, 0x10ab,
2983 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2984 rval, mcp->mb[0], mcp->mb[1]);
df613b96 2985 } else {
5f28d2d7
SK		 2986 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
2987 "Done %s.\n", __func__);
df613b96
AV		 2988
2989 if (mb)
2990 memcpy(mb, mcp->mb, 8 * sizeof(*mb));
2991 if (dwords)
fa0926df 2992 *dwords = buffers;
df613b96
AV		 2993 }
2994
2995 return rval;
2996}
2997
2998int
7b867cf7 2999qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
df613b96
AV		 3000{
3001 int rval;
3002 mbx_cmd_t mc;
3003 mbx_cmd_t *mcp = &mc;
3004
5f28d2d7
SK		 3005 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
3006 "Entered %s.\n", __func__);
7c3df132 3007
7b867cf7 3008 if (!IS_FWI2_CAPABLE(vha->hw))
df613b96
AV		 3009 return QLA_FUNCTION_FAILED;
3010
85880801
AV		 3011 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3012 return QLA_FUNCTION_FAILED;
3013
df613b96
AV		 3014 mcp->mb[0] = MBC_TRACE_CONTROL;
3015 mcp->mb[1] = TC_FCE_DISABLE;
3016 mcp->mb[2] = TC_FCE_DISABLE_TRACE;
3017 mcp->out_mb = MBX_2|MBX_1|MBX_0;
3018 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3019 MBX_1|MBX_0;
b93480e3 3020 mcp->tov = MBX_TOV_SECONDS;
df613b96 3021 mcp->flags = 0;
7b867cf7 3022 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 3023 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3024 ql_dbg(ql_dbg_mbx, vha, 0x10ae,
3025 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3026 rval, mcp->mb[0], mcp->mb[1]);
df613b96 3027 } else {
5f28d2d7
SK		 3028 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
3029 "Done %s.\n", __func__);
df613b96
AV		 3030
3031 if (wr)
3032 *wr = (uint64_t) mcp->mb[5] << 48 |
3033 (uint64_t) mcp->mb[4] << 32 |
3034 (uint64_t) mcp->mb[3] << 16 |
3035 (uint64_t) mcp->mb[2];
3036 if (rd)
3037 *rd = (uint64_t) mcp->mb[9] << 48 |
3038 (uint64_t) mcp->mb[8] << 32 |
3039 (uint64_t) mcp->mb[7] << 16 |
3040 (uint64_t) mcp->mb[6];
3041 }
3042
3043 return rval;
3044}
3045
6e98016c
GM		 3046int
3047qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3048 uint16_t *port_speed, uint16_t *mb)
3049{
3050 int rval;
3051 mbx_cmd_t mc;
3052 mbx_cmd_t *mcp = &mc;
3053
5f28d2d7
SK		 3054 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
3055 "Entered %s.\n", __func__);
7c3df132 3056
6e98016c
GM		 3057 if (!IS_IIDMA_CAPABLE(vha->hw))
3058 return QLA_FUNCTION_FAILED;
3059
6e98016c
GM		 3060 mcp->mb[0] = MBC_PORT_PARAMS;
3061 mcp->mb[1] = loop_id;
3062 mcp->mb[2] = mcp->mb[3] = 0;
3063 mcp->mb[9] = vha->vp_idx;
3064 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3065 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3066 mcp->tov = MBX_TOV_SECONDS;
3067 mcp->flags = 0;
3068 rval = qla2x00_mailbox_command(vha, mcp);
3069
3070 /* Return mailbox statuses. */
3071 if (mb != NULL) {
3072 mb[0] = mcp->mb[0];
3073 mb[1] = mcp->mb[1];
3074 mb[3] = mcp->mb[3];
3075 }
3076
3077 if (rval != QLA_SUCCESS) {
7c3df132 3078 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
6e98016c 3079 } else {
5f28d2d7
SK		 3080 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
3081 "Done %s.\n", __func__);
6e98016c
GM		 3082 if (port_speed)
3083 *port_speed = mcp->mb[3];
3084 }
3085
3086 return rval;
3087}
3088
d8b45213 3089int
7b867cf7 3090qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
d8b45213
AV		 3091 uint16_t port_speed, uint16_t *mb)
3092{
3093 int rval;
3094 mbx_cmd_t mc;
3095 mbx_cmd_t *mcp = &mc;
3096
5f28d2d7
SK		 3097 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
3098 "Entered %s.\n", __func__);
7c3df132 3099
7b867cf7 3100 if (!IS_IIDMA_CAPABLE(vha->hw))
d8b45213
AV		 3101 return QLA_FUNCTION_FAILED;
3102
d8b45213
AV		 3103 mcp->mb[0] = MBC_PORT_PARAMS;
3104 mcp->mb[1] = loop_id;
3105 mcp->mb[2] = BIT_0;
6246b8a1 3106 if (IS_CNA_CAPABLE(vha->hw))
1bb39548
HZ		 3107 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
3108 else
3109 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
3110 mcp->mb[9] = vha->vp_idx;
3111 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3112 mcp->in_mb = MBX_3|MBX_1|MBX_0;
b93480e3 3113 mcp->tov = MBX_TOV_SECONDS;
d8b45213 3114 mcp->flags = 0;
7b867cf7 3115 rval = qla2x00_mailbox_command(vha, mcp);
d8b45213
AV		 3116
3117 /* Return mailbox statuses. */
3118 if (mb != NULL) {
3119 mb[0] = mcp->mb[0];
3120 mb[1] = mcp->mb[1];
3121 mb[3] = mcp->mb[3];
d8b45213
AV		 3122 }
3123
3124 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 3125 ql_dbg(ql_dbg_mbx, vha, 0x10b4,
3126 "Failed=%x.\n", rval);
d8b45213 3127 } else {
5f28d2d7
SK		 3128 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
3129 "Done %s.\n", __func__);
d8b45213
AV		 3130 }
3131
3132 return rval;
3133}
2c3dfe3f 3134
2c3dfe3f 3135void
7b867cf7 3136qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
2c3dfe3f
SJ		 3137 struct vp_rpt_id_entry_24xx *rptid_entry)
3138{
3139 uint8_t vp_idx;
c6852c4c 3140 uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
7b867cf7
AC		 3141 struct qla_hw_data *ha = vha->hw;
3142 scsi_qla_host_t *vp;
feafb7b1 3143 unsigned long flags;
2c3dfe3f 3144
5f28d2d7
SK		 3145 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
3146 "Entered %s.\n", __func__);
7c3df132 3147
2c3dfe3f
SJ		 3148 if (rptid_entry->entry_status != 0)
3149 return;
2c3dfe3f
SJ		 3150
3151 if (rptid_entry->format == 0) {
5f28d2d7 3152 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7,
7c3df132
SK		 3153 "Format 0 : Number of VPs setup %d, number of "
3154 "VPs acquired %d.\n",
3155 MSB(le16_to_cpu(rptid_entry->vp_count)),
3156 LSB(le16_to_cpu(rptid_entry->vp_count)));
5f28d2d7 3157 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8,
7c3df132
SK		 3158 "Primary port id %02x%02x%02x.\n",
3159 rptid_entry->port_id[2], rptid_entry->port_id[1],
3160 rptid_entry->port_id[0]);
2c3dfe3f 3161 } else if (rptid_entry->format == 1) {
c6852c4c 3162 vp_idx = LSB(stat);
5f28d2d7 3163 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9,
7c3df132
SK		 3164 "Format 1: VP[%d] enabled - status %d - with "
3165 "port id %02x%02x%02x.\n", vp_idx, MSB(stat),
2c3dfe3f 3166 rptid_entry->port_id[2], rptid_entry->port_id[1],
7c3df132 3167 rptid_entry->port_id[0]);
531a82d1
AV		 3168
3169 vp = vha;
3170 if (vp_idx == 0 && (MSB(stat) != 1))
3171 goto reg_needed;
2c3dfe3f 3172
681e014b 3173 if (MSB(stat) != 0 && MSB(stat) != 2) {
7c3df132
SK		 3174 ql_dbg(ql_dbg_mbx, vha, 0x10ba,
3175 "Could not acquire ID for VP[%d].\n", vp_idx);
2c3dfe3f 3176 return;
81eb9b49 3177 }
2c3dfe3f 3178
feafb7b1
AE		 3179 spin_lock_irqsave(&ha->vport_slock, flags);
3180 list_for_each_entry(vp, &ha->vp_list, list)
7b867cf7 3181 if (vp_idx == vp->vp_idx)
2c3dfe3f 3182 break;
feafb7b1
AE		 3183 spin_unlock_irqrestore(&ha->vport_slock, flags);
3184
7b867cf7 3185 if (!vp)
2c3dfe3f
SJ		 3186 return;
3187
7b867cf7
AC		 3188 vp->d_id.b.domain = rptid_entry->port_id[2];
3189 vp->d_id.b.area = rptid_entry->port_id[1];
3190 vp->d_id.b.al_pa = rptid_entry->port_id[0];
2c3dfe3f
SJ		 3191
3192 /*
3193 * Cannot configure here as we are still sitting on the
3194 * response queue. Handle it in dpc context.
3195 */
7b867cf7 3196 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
2c3dfe3f 3197
531a82d1
AV		 3198reg_needed:
3199 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
3200 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
3201 set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
7b867cf7 3202 qla2xxx_wake_dpc(vha);
2c3dfe3f
SJ		 3203 }
3204}
3205
3206/*
3207 * qla24xx_modify_vp_config
3208 * Change VP configuration for vha
3209 *
3210 * Input:
3211 * vha = adapter block pointer.
3212 *
3213 * Returns:
3214 * qla2xxx local function return status code.
3215 *
3216 * Context:
3217 * Kernel context.
3218 */
3219int
3220qla24xx_modify_vp_config(scsi_qla_host_t *vha)
3221{
3222 int rval;
3223 struct vp_config_entry_24xx *vpmod;
3224 dma_addr_t vpmod_dma;
7b867cf7
AC		 3225 struct qla_hw_data *ha = vha->hw;
3226 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f
SJ		 3227
3228 /* This can be called by the parent */
2c3dfe3f 3229
5f28d2d7
SK		 3230 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
3231 "Entered %s.\n", __func__);
7c3df132 3232
7b867cf7 3233 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
2c3dfe3f 3234 if (!vpmod) {
7c3df132
SK		 3235 ql_log(ql_log_warn, vha, 0x10bc,
3236 "Failed to allocate modify VP IOCB.\n");
2c3dfe3f
SJ		 3237 return QLA_MEMORY_ALLOC_FAILED;
3238 }
3239
3240 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
3241 vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
3242 vpmod->entry_count = 1;
3243 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
3244 vpmod->vp_count = 1;
3245 vpmod->vp_index1 = vha->vp_idx;
3246 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
2d70c103
NB		 3247
3248 qlt_modify_vp_config(vha, vpmod);
3249
2c3dfe3f
SJ		 3250 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
3251 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
3252 vpmod->entry_count = 1;
3253
7b867cf7 3254 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
2c3dfe3f 3255 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3256 ql_dbg(ql_dbg_mbx, vha, 0x10bd,
3257 "Failed to issue VP config IOCB (%x).\n", rval);
2c3dfe3f 3258 } else if (vpmod->comp_status != 0) {
7c3df132
SK		 3259 ql_dbg(ql_dbg_mbx, vha, 0x10be,
3260 "Failed to complete IOCB -- error status (%x).\n",
3261 vpmod->comp_status);
2c3dfe3f
SJ		 3262 rval = QLA_FUNCTION_FAILED;
3263 } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3264 ql_dbg(ql_dbg_mbx, vha, 0x10bf,
3265 "Failed to complete IOCB -- completion status (%x).\n",
3266 le16_to_cpu(vpmod->comp_status));
2c3dfe3f
SJ		 3267 rval = QLA_FUNCTION_FAILED;
3268 } else {
3269 /* EMPTY */
5f28d2d7
SK		 3270 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
3271 "Done %s.\n", __func__);
2c3dfe3f
SJ		 3272 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
3273 }
7b867cf7 3274 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
2c3dfe3f
SJ		 3275
3276 return rval;
3277}
3278
3279/*
3280 * qla24xx_control_vp
3281 * Enable a virtual port for given host
3282 *
3283 * Input:
3284 * ha = adapter block pointer.
3285 * vhba = virtual adapter (unused)
3286 * index = index number for enabled VP
3287 *
3288 * Returns:
3289 * qla2xxx local function return status code.
3290 *
3291 * Context:
3292 * Kernel context.
3293 */
3294int
3295qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
3296{
3297 int rval;
3298 int map, pos;
3299 struct vp_ctrl_entry_24xx *vce;
3300 dma_addr_t vce_dma;
7b867cf7 3301 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 3302 int vp_index = vha->vp_idx;
7b867cf7 3303 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f 3304
5f28d2d7 3305 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1,
7c3df132 3306 "Entered %s enabling index %d.\n", __func__, vp_index);
2c3dfe3f 3307
eb66dc60 3308 if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
2c3dfe3f
SJ		 3309 return QLA_PARAMETER_ERROR;
3310
3311 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
3312 if (!vce) {
7c3df132
SK		 3313 ql_log(ql_log_warn, vha, 0x10c2,
3314 "Failed to allocate VP control IOCB.\n");
2c3dfe3f
SJ		 3315 return QLA_MEMORY_ALLOC_FAILED;
3316 }
3317 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
3318
3319 vce->entry_type = VP_CTRL_IOCB_TYPE;
3320 vce->entry_count = 1;
3321 vce->command = cpu_to_le16(cmd);
3322 vce->vp_count = __constant_cpu_to_le16(1);
3323
3324 /* index map in firmware starts with 1; decrement index
3325 * this is ok as we never use index 0
3326 */
3327 map = (vp_index - 1) / 8;
3328 pos = (vp_index - 1) & 7;
6c2f527c 3329 mutex_lock(&ha->vport_lock);
2c3dfe3f 3330 vce->vp_idx_map[map] |= 1 << pos;
6c2f527c 3331 mutex_unlock(&ha->vport_lock);
2c3dfe3f 3332
7b867cf7 3333 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
2c3dfe3f 3334 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3335 ql_dbg(ql_dbg_mbx, vha, 0x10c3,
3336 "Failed to issue VP control IOCB (%x).\n", rval);
2c3dfe3f 3337 } else if (vce->entry_status != 0) {
7c3df132
SK		 3338 ql_dbg(ql_dbg_mbx, vha, 0x10c4,
3339 "Failed to complete IOCB -- error status (%x).\n",
2c3dfe3f
SJ		 3340 vce->entry_status);
3341 rval = QLA_FUNCTION_FAILED;
3342 } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3343 ql_dbg(ql_dbg_mbx, vha, 0x10c5,
3344 "Failed to complet IOCB -- completion status (%x).\n",
2c3dfe3f
SJ		 3345 le16_to_cpu(vce->comp_status));
3346 rval = QLA_FUNCTION_FAILED;
3347 } else {
5f28d2d7
SK		 3348 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6,
3349 "Done %s.\n", __func__);
2c3dfe3f
SJ		 3350 }
3351
3352 dma_pool_free(ha->s_dma_pool, vce, vce_dma);
3353
3354 return rval;
3355}
3356
3357/*
3358 * qla2x00_send_change_request
3359 * Receive or disable RSCN request from fabric controller
3360 *
3361 * Input:
3362 * ha = adapter block pointer
3363 * format = registration format:
3364 * 0 - Reserved
3365 * 1 - Fabric detected registration
3366 * 2 - N_port detected registration
3367 * 3 - Full registration
3368 * FF - clear registration
3369 * vp_idx = Virtual port index
3370 *
3371 * Returns:
3372 * qla2x00 local function return status code.
3373 *
3374 * Context:
3375 * Kernel Context
3376 */
3377
3378int
7b867cf7 3379qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
2c3dfe3f
SJ		 3380 uint16_t vp_idx)
3381{
3382 int rval;
3383 mbx_cmd_t mc;
3384 mbx_cmd_t *mcp = &mc;
3385
5f28d2d7
SK		 3386 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
3387 "Entered %s.\n", __func__);
7c3df132 3388
2c3dfe3f
SJ		 3389 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
3390 mcp->mb[1] = format;
3391 mcp->mb[9] = vp_idx;
3392 mcp->out_mb = MBX_9|MBX_1|MBX_0;
3393 mcp->in_mb = MBX_0|MBX_1;
3394 mcp->tov = MBX_TOV_SECONDS;
3395 mcp->flags = 0;
7b867cf7 3396 rval = qla2x00_mailbox_command(vha, mcp);
2c3dfe3f
SJ		 3397
3398 if (rval == QLA_SUCCESS) {
3399 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
3400 rval = BIT_1;
3401 }
3402 } else
3403 rval = BIT_1;
3404
3405 return rval;
3406}
338c9161
AV		 3407
3408int
7b867cf7 3409qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
338c9161
AV		 3410 uint32_t size)
3411{
3412 int rval;
3413 mbx_cmd_t mc;
3414 mbx_cmd_t *mcp = &mc;
3415
5f28d2d7
SK		 3416 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
3417 "Entered %s.\n", __func__);
338c9161 3418
7b867cf7 3419 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 3420 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
3421 mcp->mb[8] = MSW(addr);
3422 mcp->out_mb = MBX_8|MBX_0;
3423 } else {
3424 mcp->mb[0] = MBC_DUMP_RISC_RAM;
3425 mcp->out_mb = MBX_0;
3426 }
3427 mcp->mb[1] = LSW(addr);
3428 mcp->mb[2] = MSW(req_dma);
3429 mcp->mb[3] = LSW(req_dma);
3430 mcp->mb[6] = MSW(MSD(req_dma));
3431 mcp->mb[7] = LSW(MSD(req_dma));
3432 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
7b867cf7 3433 if (IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 3434 mcp->mb[4] = MSW(size);
3435 mcp->mb[5] = LSW(size);
3436 mcp->out_mb |= MBX_5|MBX_4;
3437 } else {
3438 mcp->mb[4] = LSW(size);
3439 mcp->out_mb |= MBX_4;
3440 }
3441
3442 mcp->in_mb = MBX_0;
b93480e3 3443 mcp->tov = MBX_TOV_SECONDS;
338c9161 3444 mcp->flags = 0;
7b867cf7 3445 rval = qla2x00_mailbox_command(vha, mcp);
338c9161
AV		 3446
3447 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3448 ql_dbg(ql_dbg_mbx, vha, 0x1008,
3449 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
338c9161 3450 } else {
5f28d2d7
SK		 3451 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
3452 "Done %s.\n", __func__);
338c9161
AV		 3453 }
3454
3455 return rval;
3456}
4d4df193
HK		 3457/* 84XX Support **************************************************************/
3458
3459struct cs84xx_mgmt_cmd {
3460 union {
3461 struct verify_chip_entry_84xx req;
3462 struct verify_chip_rsp_84xx rsp;
3463 } p;
3464};
3465
3466int
7b867cf7 3467qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
4d4df193
HK		 3468{
3469 int rval, retry;
3470 struct cs84xx_mgmt_cmd *mn;
3471 dma_addr_t mn_dma;
3472 uint16_t options;
3473 unsigned long flags;
7b867cf7 3474 struct qla_hw_data *ha = vha->hw;
4d4df193 3475
5f28d2d7
SK		 3476 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
3477 "Entered %s.\n", __func__);
4d4df193
HK		 3478
3479 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
3480 if (mn == NULL) {
4d4df193
HK		 3481 return QLA_MEMORY_ALLOC_FAILED;
3482 }
3483
3484 /* Force Update? */
3485 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
3486 /* Diagnostic firmware? */
3487 /* options |= MENLO_DIAG_FW; */
3488 /* We update the firmware with only one data sequence. */
3489 options |= VCO_END_OF_DATA;
3490
4d4df193 3491 do {
c1ec1f1b 3492 retry = 0;
4d4df193
HK		 3493 memset(mn, 0, sizeof(*mn));
3494 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
3495 mn->p.req.entry_count = 1;
3496 mn->p.req.options = cpu_to_le16(options);
3497
7c3df132
SK		 3498 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
3499 "Dump of Verify Request.\n");
3500 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
3501 (uint8_t *)mn, sizeof(*mn));
4d4df193 3502
7b867cf7 3503 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
4d4df193 3504 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3505 ql_dbg(ql_dbg_mbx, vha, 0x10cb,
3506 "Failed to issue verify IOCB (%x).\n", rval);
4d4df193
HK		 3507 goto verify_done;
3508 }
3509
7c3df132
SK		 3510 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
3511 "Dump of Verify Response.\n");
3512 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
3513 (uint8_t *)mn, sizeof(*mn));
4d4df193
HK		 3514
3515 status[0] = le16_to_cpu(mn->p.rsp.comp_status);
3516 status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
3517 le16_to_cpu(mn->p.rsp.failure_code) : 0;
5f28d2d7 3518 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
7c3df132 3519 "cs=%x fc=%x.\n", status[0], status[1]);
4d4df193
HK		 3520
3521 if (status[0] != CS_COMPLETE) {
3522 rval = QLA_FUNCTION_FAILED;
3523 if (!(options & VCO_DONT_UPDATE_FW)) {
7c3df132
SK		 3524 ql_dbg(ql_dbg_mbx, vha, 0x10cf,
3525 "Firmware update failed. Retrying "
3526 "without update firmware.\n");
4d4df193
HK		 3527 options |= VCO_DONT_UPDATE_FW;
3528 options &= ~VCO_FORCE_UPDATE;
3529 retry = 1;
3530 }
3531 } else {
5f28d2d7 3532 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
7c3df132
SK		 3533 "Firmware updated to %x.\n",
3534 le32_to_cpu(mn->p.rsp.fw_ver));
4d4df193
HK		 3535
3536 /* NOTE: we only update OP firmware. */
3537 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
3538 ha->cs84xx->op_fw_version =
3539 le32_to_cpu(mn->p.rsp.fw_ver);
3540 spin_unlock_irqrestore(&ha->cs84xx->access_lock,
3541 flags);
3542 }
3543 } while (retry);
3544
3545verify_done:
3546 dma_pool_free(ha->s_dma_pool, mn, mn_dma);
3547
3548 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 3549 ql_dbg(ql_dbg_mbx, vha, 0x10d1,
3550 "Failed=%x.\n", rval);
4d4df193 3551 } else {
5f28d2d7
SK		 3552 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
3553 "Done %s.\n", __func__);
4d4df193
HK		 3554 }
3555
3556 return rval;
3557}
73208dfd
AC		 3558
3559int
618a7523 3560qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
73208dfd
AC		 3561{
3562 int rval;
3563 unsigned long flags;
3564 mbx_cmd_t mc;
3565 mbx_cmd_t *mcp = &mc;
3566 struct device_reg_25xxmq __iomem *reg;
3567 struct qla_hw_data *ha = vha->hw;
3568
5f28d2d7
SK		 3569 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
3570 "Entered %s.\n", __func__);
7c3df132 3571
73208dfd 3572 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 3573 mcp->mb[1] = req->options;
73208dfd
AC		 3574 mcp->mb[2] = MSW(LSD(req->dma));
3575 mcp->mb[3] = LSW(LSD(req->dma));
3576 mcp->mb[6] = MSW(MSD(req->dma));
3577 mcp->mb[7] = LSW(MSD(req->dma));
3578 mcp->mb[5] = req->length;
3579 if (req->rsp)
3580 mcp->mb[10] = req->rsp->id;
3581 mcp->mb[12] = req->qos;
3582 mcp->mb[11] = req->vp_idx;
3583 mcp->mb[13] = req->rid;
6246b8a1
GM		 3584 if (IS_QLA83XX(ha))
3585 mcp->mb[15] = 0;
73208dfd 3586
fa492630 3587 reg = (struct device_reg_25xxmq __iomem *)((ha->mqiobase) +
73208dfd
AC		 3588 QLA_QUE_PAGE * req->id);
3589
3590 mcp->mb[4] = req->id;
3591 /* que in ptr index */
3592 mcp->mb[8] = 0;
3593 /* que out ptr index */
3594 mcp->mb[9] = 0;
3595 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
3596 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3597 mcp->in_mb = MBX_0;
3598 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 3599 mcp->tov = MBX_TOV_SECONDS * 2;
3600
3601 if (IS_QLA81XX(ha) || IS_QLA83XX(ha))
3602 mcp->in_mb |= MBX_1;
3603 if (IS_QLA83XX(ha)) {
3604 mcp->out_mb |= MBX_15;
3605 /* debug q create issue in SR-IOV */
3606 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
3607 }
73208dfd
AC		 3608
3609 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 3610 if (!(req->options & BIT_0)) {
73208dfd 3611 WRT_REG_DWORD(&reg->req_q_in, 0);
6246b8a1
GM		 3612 if (!IS_QLA83XX(ha))
3613 WRT_REG_DWORD(&reg->req_q_out, 0);
73208dfd 3614 }
2afa19a9
AC		 3615 req->req_q_in = &reg->req_q_in;
3616 req->req_q_out = &reg->req_q_out;
73208dfd
AC		 3617 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3618
17d98630 3619 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 3620 if (rval != QLA_SUCCESS) {
3621 ql_dbg(ql_dbg_mbx, vha, 0x10d4,
3622 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3623 } else {
5f28d2d7
SK		 3624 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
3625 "Done %s.\n", __func__);
7c3df132
SK		 3626 }
3627
73208dfd
AC		 3628 return rval;
3629}
3630
3631int
618a7523 3632qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
73208dfd
AC		 3633{
3634 int rval;
3635 unsigned long flags;
3636 mbx_cmd_t mc;
3637 mbx_cmd_t *mcp = &mc;
3638 struct device_reg_25xxmq __iomem *reg;
3639 struct qla_hw_data *ha = vha->hw;
3640
5f28d2d7
SK		 3641 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
3642 "Entered %s.\n", __func__);
7c3df132 3643
73208dfd 3644 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 3645 mcp->mb[1] = rsp->options;
73208dfd
AC		 3646 mcp->mb[2] = MSW(LSD(rsp->dma));
3647 mcp->mb[3] = LSW(LSD(rsp->dma));
3648 mcp->mb[6] = MSW(MSD(rsp->dma));
3649 mcp->mb[7] = LSW(MSD(rsp->dma));
3650 mcp->mb[5] = rsp->length;
444786d7 3651 mcp->mb[14] = rsp->msix->entry;
73208dfd 3652 mcp->mb[13] = rsp->rid;
6246b8a1
GM		 3653 if (IS_QLA83XX(ha))
3654 mcp->mb[15] = 0;
73208dfd 3655
fa492630 3656 reg = (struct device_reg_25xxmq __iomem *)((ha->mqiobase) +
73208dfd
AC		 3657 QLA_QUE_PAGE * rsp->id);
3658
3659 mcp->mb[4] = rsp->id;
3660 /* que in ptr index */
3661 mcp->mb[8] = 0;
3662 /* que out ptr index */
3663 mcp->mb[9] = 0;
2afa19a9 3664 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
73208dfd
AC		 3665 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3666 mcp->in_mb = MBX_0;
3667 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 3668 mcp->tov = MBX_TOV_SECONDS * 2;
3669
3670 if (IS_QLA81XX(ha)) {
3671 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
3672 mcp->in_mb |= MBX_1;
3673 } else if (IS_QLA83XX(ha)) {
3674 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
3675 mcp->in_mb |= MBX_1;
3676 /* debug q create issue in SR-IOV */
3677 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
3678 }
73208dfd
AC		 3679
3680 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 3681 if (!(rsp->options & BIT_0)) {
73208dfd 3682 WRT_REG_DWORD(&reg->rsp_q_out, 0);
6246b8a1
GM		 3683 if (!IS_QLA83XX(ha))
3684 WRT_REG_DWORD(&reg->rsp_q_in, 0);
73208dfd
AC		 3685 }
3686
3687 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3688
17d98630 3689 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 3690 if (rval != QLA_SUCCESS) {
3691 ql_dbg(ql_dbg_mbx, vha, 0x10d7,
3692 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3693 } else {
5f28d2d7
SK		 3694 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
3695 "Done %s.\n", __func__);
7c3df132
SK		 3696 }
3697
73208dfd
AC		 3698 return rval;
3699}
3700
8a659571
AV		 3701int
3702qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
3703{
3704 int rval;
3705 mbx_cmd_t mc;
3706 mbx_cmd_t *mcp = &mc;
3707
5f28d2d7
SK		 3708 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
3709 "Entered %s.\n", __func__);
8a659571
AV		 3710
3711 mcp->mb[0] = MBC_IDC_ACK;
3712 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3713 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3714 mcp->in_mb = MBX_0;
3715 mcp->tov = MBX_TOV_SECONDS;
3716 mcp->flags = 0;
3717 rval = qla2x00_mailbox_command(vha, mcp);
3718
3719 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3720 ql_dbg(ql_dbg_mbx, vha, 0x10da,
3721 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
8a659571 3722 } else {
5f28d2d7
SK		 3723 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
3724 "Done %s.\n", __func__);
8a659571
AV		 3725 }
3726
3727 return rval;
3728}
1d2874de
JC		 3729
3730int
3731qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
3732{
3733 int rval;
3734 mbx_cmd_t mc;
3735 mbx_cmd_t *mcp = &mc;
3736
5f28d2d7
SK		 3737 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
3738 "Entered %s.\n", __func__);
7c3df132 3739
6246b8a1 3740 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
1d2874de
JC		 3741 return QLA_FUNCTION_FAILED;
3742
1d2874de
JC		 3743 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3744 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
3745 mcp->out_mb = MBX_1|MBX_0;
3746 mcp->in_mb = MBX_1|MBX_0;
3747 mcp->tov = MBX_TOV_SECONDS;
3748 mcp->flags = 0;
3749 rval = qla2x00_mailbox_command(vha, mcp);
3750
3751 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3752 ql_dbg(ql_dbg_mbx, vha, 0x10dd,
3753 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3754 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 3755 } else {
5f28d2d7
SK		 3756 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
3757 "Done %s.\n", __func__);
1d2874de
JC		 3758 *sector_size = mcp->mb[1];
3759 }
3760
3761 return rval;
3762}
3763
3764int
3765qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
3766{
3767 int rval;
3768 mbx_cmd_t mc;
3769 mbx_cmd_t *mcp = &mc;
3770
6246b8a1 3771 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
1d2874de
JC		 3772 return QLA_FUNCTION_FAILED;
3773
5f28d2d7
SK		 3774 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
3775 "Entered %s.\n", __func__);
1d2874de
JC		 3776
3777 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3778 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
3779 FAC_OPT_CMD_WRITE_PROTECT;
3780 mcp->out_mb = MBX_1|MBX_0;
3781 mcp->in_mb = MBX_1|MBX_0;
3782 mcp->tov = MBX_TOV_SECONDS;
3783 mcp->flags = 0;
3784 rval = qla2x00_mailbox_command(vha, mcp);
3785
3786 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3787 ql_dbg(ql_dbg_mbx, vha, 0x10e0,
3788 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3789 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 3790 } else {
5f28d2d7
SK		 3791 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
3792 "Done %s.\n", __func__);
1d2874de
JC		 3793 }
3794
3795 return rval;
3796}
3797
3798int
3799qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
3800{
3801 int rval;
3802 mbx_cmd_t mc;
3803 mbx_cmd_t *mcp = &mc;
3804
6246b8a1 3805 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw))
1d2874de
JC		 3806 return QLA_FUNCTION_FAILED;
3807
5f28d2d7
SK		 3808 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
3809 "Entered %s.\n", __func__);
1d2874de
JC		 3810
3811 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3812 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
3813 mcp->mb[2] = LSW(start);
3814 mcp->mb[3] = MSW(start);
3815 mcp->mb[4] = LSW(finish);
3816 mcp->mb[5] = MSW(finish);
3817 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3818 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3819 mcp->tov = MBX_TOV_SECONDS;
3820 mcp->flags = 0;
3821 rval = qla2x00_mailbox_command(vha, mcp);
3822
3823 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3824 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
3825 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
3826 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1d2874de 3827 } else {
5f28d2d7
SK		 3828 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
3829 "Done %s.\n", __func__);
1d2874de
JC		 3830 }
3831
3832 return rval;
3833}
6e181be5
LC		 3834
3835int
3836qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
3837{
3838 int rval = 0;
3839 mbx_cmd_t mc;
3840 mbx_cmd_t *mcp = &mc;
3841
5f28d2d7
SK		 3842 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
3843 "Entered %s.\n", __func__);
6e181be5
LC		 3844
3845 mcp->mb[0] = MBC_RESTART_MPI_FW;
3846 mcp->out_mb = MBX_0;
3847 mcp->in_mb = MBX_0|MBX_1;
3848 mcp->tov = MBX_TOV_SECONDS;
3849 mcp->flags = 0;
3850 rval = qla2x00_mailbox_command(vha, mcp);
3851
3852 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3853 ql_dbg(ql_dbg_mbx, vha, 0x10e6,
3854 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3855 rval, mcp->mb[0], mcp->mb[1]);
6e181be5 3856 } else {
5f28d2d7
SK		 3857 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
3858 "Done %s.\n", __func__);
6e181be5
LC		 3859 }
3860
3861 return rval;
3862}
ad0ecd61
JC		 3863
3864int
6766df9e
JC		 3865qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
3866 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 3867{
3868 int rval;
3869 mbx_cmd_t mc;
3870 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 3871 struct qla_hw_data *ha = vha->hw;
3872
5f28d2d7
SK		 3873 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
3874 "Entered %s.\n", __func__);
7c3df132 3875
6766df9e
JC		 3876 if (!IS_FWI2_CAPABLE(ha))
3877 return QLA_FUNCTION_FAILED;
ad0ecd61 3878
6766df9e
JC		 3879 if (len == 1)
3880 opt |= BIT_0;
3881
ad0ecd61
JC		 3882 mcp->mb[0] = MBC_READ_SFP;
3883 mcp->mb[1] = dev;
3884 mcp->mb[2] = MSW(sfp_dma);
3885 mcp->mb[3] = LSW(sfp_dma);
3886 mcp->mb[6] = MSW(MSD(sfp_dma));
3887 mcp->mb[7] = LSW(MSD(sfp_dma));
3888 mcp->mb[8] = len;
6766df9e 3889 mcp->mb[9] = off;
ad0ecd61
JC		 3890 mcp->mb[10] = opt;
3891 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1bff6cc8 3892 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 3893 mcp->tov = MBX_TOV_SECONDS;
3894 mcp->flags = 0;
3895 rval = qla2x00_mailbox_command(vha, mcp);
3896
3897 if (opt & BIT_0)
6766df9e 3898 *sfp = mcp->mb[1];
ad0ecd61
JC		 3899
3900 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3901 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
3902 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
ad0ecd61 3903 } else {
5f28d2d7
SK		 3904 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
3905 "Done %s.\n", __func__);
ad0ecd61
JC		 3906 }
3907
3908 return rval;
3909}
3910
3911int
6766df9e
JC		 3912qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
3913 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 3914{
3915 int rval;
3916 mbx_cmd_t mc;
3917 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 3918 struct qla_hw_data *ha = vha->hw;
3919
5f28d2d7
SK		 3920 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
3921 "Entered %s.\n", __func__);
7c3df132 3922
6766df9e
JC		 3923 if (!IS_FWI2_CAPABLE(ha))
3924 return QLA_FUNCTION_FAILED;
ad0ecd61 3925
6766df9e
JC		 3926 if (len == 1)
3927 opt |= BIT_0;
3928
ad0ecd61 3929 if (opt & BIT_0)
6766df9e 3930 len = *sfp;
ad0ecd61
JC		 3931
3932 mcp->mb[0] = MBC_WRITE_SFP;
3933 mcp->mb[1] = dev;
3934 mcp->mb[2] = MSW(sfp_dma);
3935 mcp->mb[3] = LSW(sfp_dma);
3936 mcp->mb[6] = MSW(MSD(sfp_dma));
3937 mcp->mb[7] = LSW(MSD(sfp_dma));
3938 mcp->mb[8] = len;
6766df9e 3939 mcp->mb[9] = off;
ad0ecd61
JC		 3940 mcp->mb[10] = opt;
3941 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6766df9e 3942 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 3943 mcp->tov = MBX_TOV_SECONDS;
3944 mcp->flags = 0;
3945 rval = qla2x00_mailbox_command(vha, mcp);
3946
3947 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3948 ql_dbg(ql_dbg_mbx, vha, 0x10ec,
3949 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
ad0ecd61 3950 } else {
5f28d2d7
SK		 3951 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
3952 "Done %s.\n", __func__);
ad0ecd61
JC		 3953 }
3954
3955 return rval;
3956}
ce0423f4
AV		 3957
3958int
3959qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
3960 uint16_t size_in_bytes, uint16_t *actual_size)
3961{
3962 int rval;
3963 mbx_cmd_t mc;
3964 mbx_cmd_t *mcp = &mc;
3965
5f28d2d7
SK		 3966 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
3967 "Entered %s.\n", __func__);
7c3df132 3968
6246b8a1 3969 if (!IS_CNA_CAPABLE(vha->hw))
ce0423f4
AV		 3970 return QLA_FUNCTION_FAILED;
3971
ce0423f4
AV		 3972 mcp->mb[0] = MBC_GET_XGMAC_STATS;
3973 mcp->mb[2] = MSW(stats_dma);
3974 mcp->mb[3] = LSW(stats_dma);
3975 mcp->mb[6] = MSW(MSD(stats_dma));
3976 mcp->mb[7] = LSW(MSD(stats_dma));
3977 mcp->mb[8] = size_in_bytes >> 2;
3978 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
3979 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3980 mcp->tov = MBX_TOV_SECONDS;
3981 mcp->flags = 0;
3982 rval = qla2x00_mailbox_command(vha, mcp);
3983
3984 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3985 ql_dbg(ql_dbg_mbx, vha, 0x10ef,
3986 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
3987 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
ce0423f4 3988 } else {
5f28d2d7
SK		 3989 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
3990 "Done %s.\n", __func__);
7c3df132 3991
ce0423f4
AV		 3992
3993 *actual_size = mcp->mb[2] << 2;
3994 }
3995
3996 return rval;
3997}
11bbc1d8
AV		 3998
3999int
4000qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
4001 uint16_t size)
4002{
4003 int rval;
4004 mbx_cmd_t mc;
4005 mbx_cmd_t *mcp = &mc;
4006
5f28d2d7
SK		 4007 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
4008 "Entered %s.\n", __func__);
7c3df132 4009
6246b8a1 4010 if (!IS_CNA_CAPABLE(vha->hw))
11bbc1d8
AV		 4011 return QLA_FUNCTION_FAILED;
4012
11bbc1d8
AV		 4013 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
4014 mcp->mb[1] = 0;
4015 mcp->mb[2] = MSW(tlv_dma);
4016 mcp->mb[3] = LSW(tlv_dma);
4017 mcp->mb[6] = MSW(MSD(tlv_dma));
4018 mcp->mb[7] = LSW(MSD(tlv_dma));
4019 mcp->mb[8] = size;
4020 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4021 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4022 mcp->tov = MBX_TOV_SECONDS;
4023 mcp->flags = 0;
4024 rval = qla2x00_mailbox_command(vha, mcp);
4025
4026 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4027 ql_dbg(ql_dbg_mbx, vha, 0x10f2,
4028 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4029 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
11bbc1d8 4030 } else {
5f28d2d7
SK		 4031 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
4032 "Done %s.\n", __func__);
11bbc1d8
AV		 4033 }
4034
4035 return rval;
4036}
18e7555a
AV		 4037
4038int
4039qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
4040{
4041 int rval;
4042 mbx_cmd_t mc;
4043 mbx_cmd_t *mcp = &mc;
4044
5f28d2d7
SK		 4045 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
4046 "Entered %s.\n", __func__);
7c3df132 4047
18e7555a
AV		 4048 if (!IS_FWI2_CAPABLE(vha->hw))
4049 return QLA_FUNCTION_FAILED;
4050
18e7555a
AV		 4051 mcp->mb[0] = MBC_READ_RAM_EXTENDED;
4052 mcp->mb[1] = LSW(risc_addr);
4053 mcp->mb[8] = MSW(risc_addr);
4054 mcp->out_mb = MBX_8|MBX_1|MBX_0;
4055 mcp->in_mb = MBX_3|MBX_2|MBX_0;
4056 mcp->tov = 30;
4057 mcp->flags = 0;
4058 rval = qla2x00_mailbox_command(vha, mcp);
4059 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4060 ql_dbg(ql_dbg_mbx, vha, 0x10f5,
4061 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 4062 } else {
5f28d2d7
SK		 4063 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
4064 "Done %s.\n", __func__);
18e7555a
AV		 4065 *data = mcp->mb[3] << 16 | mcp->mb[2];
4066 }
4067
4068 return rval;
4069}
4070
9a069e19 4071int
a9083016
GM		 4072qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4073 uint16_t *mresp)
9a069e19
GM		 4074{
4075 int rval;
4076 mbx_cmd_t mc;
4077 mbx_cmd_t *mcp = &mc;
4078 uint32_t iter_cnt = 0x1;
4079
5f28d2d7
SK		 4080 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
4081 "Entered %s.\n", __func__);
9a069e19
GM		 4082
4083 memset(mcp->mb, 0 , sizeof(mcp->mb));
4084 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
4085 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
4086
4087 /* transfer count */
4088 mcp->mb[10] = LSW(mreq->transfer_size);
4089 mcp->mb[11] = MSW(mreq->transfer_size);
4090
4091 /* send data address */
4092 mcp->mb[14] = LSW(mreq->send_dma);
4093 mcp->mb[15] = MSW(mreq->send_dma);
4094 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4095 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4096
25985edc 4097 /* receive data address */
9a069e19
GM		 4098 mcp->mb[16] = LSW(mreq->rcv_dma);
4099 mcp->mb[17] = MSW(mreq->rcv_dma);
4100 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4101 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4102
4103 /* Iteration count */
4104 mcp->mb[18] = LSW(iter_cnt);
4105 mcp->mb[19] = MSW(iter_cnt);
4106
4107 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
4108 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 4109 if (IS_CNA_CAPABLE(vha->hw))
9a069e19
GM		 4110 mcp->out_mb |= MBX_2;
4111 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
4112
4113 mcp->buf_size = mreq->transfer_size;
4114 mcp->tov = MBX_TOV_SECONDS;
4115 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4116
4117 rval = qla2x00_mailbox_command(vha, mcp);
4118
4119 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4120 ql_dbg(ql_dbg_mbx, vha, 0x10f8,
4121 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
4122 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
4123 mcp->mb[3], mcp->mb[18], mcp->mb[19]);
9a069e19 4124 } else {
5f28d2d7
SK		 4125 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
4126 "Done %s.\n", __func__);
9a069e19
GM		 4127 }
4128
4129 /* Copy mailbox information */
4130 memcpy( mresp, mcp->mb, 64);
9a069e19
GM		 4131 return rval;
4132}
4133
4134int
a9083016
GM		 4135qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4136 uint16_t *mresp)
9a069e19
GM		 4137{
4138 int rval;
4139 mbx_cmd_t mc;
4140 mbx_cmd_t *mcp = &mc;
4141 struct qla_hw_data *ha = vha->hw;
4142
5f28d2d7
SK		 4143 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
4144 "Entered %s.\n", __func__);
9a069e19
GM		 4145
4146 memset(mcp->mb, 0 , sizeof(mcp->mb));
4147 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
4148 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
6246b8a1 4149 if (IS_CNA_CAPABLE(ha)) {
9a069e19 4150 mcp->mb[1] |= BIT_15;
a9083016
GM		 4151 mcp->mb[2] = vha->fcoe_fcf_idx;
4152 }
9a069e19
GM		 4153 mcp->mb[16] = LSW(mreq->rcv_dma);
4154 mcp->mb[17] = MSW(mreq->rcv_dma);
4155 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4156 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4157
4158 mcp->mb[10] = LSW(mreq->transfer_size);
4159
4160 mcp->mb[14] = LSW(mreq->send_dma);
4161 mcp->mb[15] = MSW(mreq->send_dma);
4162 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4163 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4164
4165 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
4166 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 4167 if (IS_CNA_CAPABLE(ha))
9a069e19
GM		 4168 mcp->out_mb |= MBX_2;
4169
4170 mcp->in_mb = MBX_0;
6246b8a1
GM		 4171 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
4172 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
9a069e19 4173 mcp->in_mb |= MBX_1;
6246b8a1 4174 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
9a069e19
GM		 4175 mcp->in_mb |= MBX_3;
4176
4177 mcp->tov = MBX_TOV_SECONDS;
4178 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4179 mcp->buf_size = mreq->transfer_size;
4180
4181 rval = qla2x00_mailbox_command(vha, mcp);
4182
4183 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4184 ql_dbg(ql_dbg_mbx, vha, 0x10fb,
4185 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4186 rval, mcp->mb[0], mcp->mb[1]);
9a069e19 4187 } else {
5f28d2d7
SK		 4188 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
4189 "Done %s.\n", __func__);
9a069e19
GM		 4190 }
4191
4192 /* Copy mailbox information */
6dbdda4d 4193 memcpy(mresp, mcp->mb, 64);
9a069e19
GM		 4194 return rval;
4195}
6dbdda4d 4196
9a069e19 4197int
7c3df132 4198qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
9a069e19
GM		 4199{
4200 int rval;
4201 mbx_cmd_t mc;
4202 mbx_cmd_t *mcp = &mc;
4203
5f28d2d7 4204 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
7c3df132 4205 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
9a069e19
GM		 4206
4207 mcp->mb[0] = MBC_ISP84XX_RESET;
4208 mcp->mb[1] = enable_diagnostic;
4209 mcp->out_mb = MBX_1|MBX_0;
4210 mcp->in_mb = MBX_1|MBX_0;
4211 mcp->tov = MBX_TOV_SECONDS;
4212 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
7c3df132 4213 rval = qla2x00_mailbox_command(vha, mcp);
9a069e19 4214
9a069e19 4215 if (rval != QLA_SUCCESS)
7c3df132 4216 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
9a069e19 4217 else
5f28d2d7
SK		 4218 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
4219 "Done %s.\n", __func__);
9a069e19
GM		 4220
4221 return rval;
4222}
4223
18e7555a
AV		 4224int
4225qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
4226{
4227 int rval;
4228 mbx_cmd_t mc;
4229 mbx_cmd_t *mcp = &mc;
4230
5f28d2d7
SK		 4231 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
4232 "Entered %s.\n", __func__);
7c3df132 4233
18e7555a 4234 if (!IS_FWI2_CAPABLE(vha->hw))
6c452a45 4235 return QLA_FUNCTION_FAILED;
18e7555a 4236
18e7555a
AV		 4237 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
4238 mcp->mb[1] = LSW(risc_addr);
4239 mcp->mb[2] = LSW(data);
4240 mcp->mb[3] = MSW(data);
4241 mcp->mb[8] = MSW(risc_addr);
4242 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
4243 mcp->in_mb = MBX_0;
4244 mcp->tov = 30;
4245 mcp->flags = 0;
4246 rval = qla2x00_mailbox_command(vha, mcp);
4247 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4248 ql_dbg(ql_dbg_mbx, vha, 0x1101,
4249 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 4250 } else {
5f28d2d7
SK		 4251 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
4252 "Done %s.\n", __func__);
18e7555a
AV		 4253 }
4254
4255 return rval;
4256}
3064ff39 4257
b1d46989
MI		 4258int
4259qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
4260{
4261 int rval;
4262 uint32_t stat, timer;
4263 uint16_t mb0 = 0;
4264 struct qla_hw_data *ha = vha->hw;
4265 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4266
4267 rval = QLA_SUCCESS;
4268
5f28d2d7
SK		 4269 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
4270 "Entered %s.\n", __func__);
b1d46989
MI		 4271
4272 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
4273
4274 /* Write the MBC data to the registers */
4275 WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
4276 WRT_REG_WORD(&reg->mailbox1, mb[0]);
4277 WRT_REG_WORD(&reg->mailbox2, mb[1]);
4278 WRT_REG_WORD(&reg->mailbox3, mb[2]);
4279 WRT_REG_WORD(&reg->mailbox4, mb[3]);
4280
4281 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
4282
4283 /* Poll for MBC interrupt */
4284 for (timer = 6000000; timer; timer--) {
4285 /* Check for pending interrupts. */
4286 stat = RD_REG_DWORD(&reg->host_status);
4287 if (stat & HSRX_RISC_INT) {
4288 stat &= 0xff;
4289
4290 if (stat == 0x1 || stat == 0x2 ||
4291 stat == 0x10 || stat == 0x11) {
4292 set_bit(MBX_INTERRUPT,
4293 &ha->mbx_cmd_flags);
4294 mb0 = RD_REG_WORD(&reg->mailbox0);
4295 WRT_REG_DWORD(&reg->hccr,
4296 HCCRX_CLR_RISC_INT);
4297 RD_REG_DWORD(&reg->hccr);
4298 break;
4299 }
4300 }
4301 udelay(5);
4302 }
4303
4304 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
4305 rval = mb0 & MBS_MASK;
4306 else
4307 rval = QLA_FUNCTION_FAILED;
4308
4309 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4310 ql_dbg(ql_dbg_mbx, vha, 0x1104,
4311 "Failed=%x mb[0]=%x.\n", rval, mb[0]);
b1d46989 4312 } else {
5f28d2d7
SK		 4313 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
4314 "Done %s.\n", __func__);
b1d46989
MI		 4315 }
4316
4317 return rval;
4318}
6246b8a1 4319
3064ff39
MH		 4320int
4321qla2x00_get_data_rate(scsi_qla_host_t *vha)
4322{
4323 int rval;
4324 mbx_cmd_t mc;
4325 mbx_cmd_t *mcp = &mc;
4326 struct qla_hw_data *ha = vha->hw;
4327
5f28d2d7
SK		 4328 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
4329 "Entered %s.\n", __func__);
7c3df132 4330
3064ff39
MH		 4331 if (!IS_FWI2_CAPABLE(ha))
4332 return QLA_FUNCTION_FAILED;
4333
3064ff39
MH		 4334 mcp->mb[0] = MBC_DATA_RATE;
4335 mcp->mb[1] = 0;
4336 mcp->out_mb = MBX_1|MBX_0;
4337 mcp->in_mb = MBX_2|MBX_1|MBX_0;
6246b8a1
GM		 4338 if (IS_QLA83XX(ha))
4339 mcp->in_mb |= MBX_3;
3064ff39
MH		 4340 mcp->tov = MBX_TOV_SECONDS;
4341 mcp->flags = 0;
4342 rval = qla2x00_mailbox_command(vha, mcp);
4343 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4344 ql_dbg(ql_dbg_mbx, vha, 0x1107,
4345 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3064ff39 4346 } else {
5f28d2d7
SK		 4347 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
4348 "Done %s.\n", __func__);
3064ff39
MH		 4349 if (mcp->mb[1] != 0x7)
4350 ha->link_data_rate = mcp->mb[1];
4351 }
4352
4353 return rval;
4354}
09ff701a 4355
23f2ebd1
SR		 4356int
4357qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
4358{
4359 int rval;
4360 mbx_cmd_t mc;
4361 mbx_cmd_t *mcp = &mc;
4362 struct qla_hw_data *ha = vha->hw;
4363
5f28d2d7
SK		 4364 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
4365 "Entered %s.\n", __func__);
23f2ebd1 4366
6246b8a1 4367 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha))
23f2ebd1
SR		 4368 return QLA_FUNCTION_FAILED;
4369 mcp->mb[0] = MBC_GET_PORT_CONFIG;
4370 mcp->out_mb = MBX_0;
4371 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4372 mcp->tov = MBX_TOV_SECONDS;
4373 mcp->flags = 0;
4374
4375 rval = qla2x00_mailbox_command(vha, mcp);
4376
4377 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4378 ql_dbg(ql_dbg_mbx, vha, 0x110a,
4379 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1
SR		 4380 } else {
4381 /* Copy all bits to preserve original value */
4382 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
4383
5f28d2d7
SK		 4384 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
4385 "Done %s.\n", __func__);
23f2ebd1
SR		 4386 }
4387 return rval;
4388}
4389
4390int
4391qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
4392{
4393 int rval;
4394 mbx_cmd_t mc;
4395 mbx_cmd_t *mcp = &mc;
4396
5f28d2d7
SK		 4397 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
4398 "Entered %s.\n", __func__);
23f2ebd1
SR		 4399
4400 mcp->mb[0] = MBC_SET_PORT_CONFIG;
4401 /* Copy all bits to preserve original setting */
4402 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
4403 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4404 mcp->in_mb = MBX_0;
4405 mcp->tov = MBX_TOV_SECONDS;
4406 mcp->flags = 0;
4407 rval = qla2x00_mailbox_command(vha, mcp);
4408
4409 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4410 ql_dbg(ql_dbg_mbx, vha, 0x110d,
4411 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1 4412 } else
5f28d2d7
SK		 4413 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
4414 "Done %s.\n", __func__);
23f2ebd1
SR		 4415
4416 return rval;
4417}
4418
4419
09ff701a
SR		 4420int
4421qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
4422 uint16_t *mb)
4423{
4424 int rval;
4425 mbx_cmd_t mc;
4426 mbx_cmd_t *mcp = &mc;
4427 struct qla_hw_data *ha = vha->hw;
4428
5f28d2d7
SK		 4429 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
4430 "Entered %s.\n", __func__);
7c3df132 4431
09ff701a
SR		 4432 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
4433 return QLA_FUNCTION_FAILED;
4434
09ff701a
SR		 4435 mcp->mb[0] = MBC_PORT_PARAMS;
4436 mcp->mb[1] = loop_id;
4437 if (ha->flags.fcp_prio_enabled)
4438 mcp->mb[2] = BIT_1;
4439 else
4440 mcp->mb[2] = BIT_2;
4441 mcp->mb[4] = priority & 0xf;
4442 mcp->mb[9] = vha->vp_idx;
4443 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4444 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
4445 mcp->tov = 30;
4446 mcp->flags = 0;
4447 rval = qla2x00_mailbox_command(vha, mcp);
4448 if (mb != NULL) {
4449 mb[0] = mcp->mb[0];
4450 mb[1] = mcp->mb[1];
4451 mb[3] = mcp->mb[3];
4452 mb[4] = mcp->mb[4];
4453 }
4454
4455 if (rval != QLA_SUCCESS) {
7c3df132 4456 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
09ff701a 4457 } else {
5f28d2d7
SK		 4458 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
4459 "Done %s.\n", __func__);
09ff701a
SR		 4460 }
4461
4462 return rval;
4463}
a9083016 4464
794a5691
AV		 4465int
4466qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp, uint16_t *frac)
4467{
4468 int rval;
6ad11eaa 4469 uint8_t byte;
794a5691
AV		 4470 struct qla_hw_data *ha = vha->hw;
4471
5f28d2d7
SK		 4472 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ca,
4473 "Entered %s.\n", __func__);
794a5691 4474
6ad11eaa 4475 /* Integer part */
f9322eec
JC		 4476 rval = qla2x00_read_sfp(vha, 0, &byte, 0x98, 0x01, 1,
4477 BIT_13|BIT_12|BIT_0);
794a5691 4478 if (rval != QLA_SUCCESS) {
7c3df132 4479 ql_dbg(ql_dbg_mbx, vha, 0x10c9, "Failed=%x.\n", rval);
794a5691
AV		 4480 ha->flags.thermal_supported = 0;
4481 goto fail;
4482 }
6ad11eaa 4483 *temp = byte;
794a5691 4484
6ad11eaa 4485 /* Fraction part */
f9322eec
JC		 4486 rval = qla2x00_read_sfp(vha, 0, &byte, 0x98, 0x10, 1,
4487 BIT_13|BIT_12|BIT_0);
794a5691 4488 if (rval != QLA_SUCCESS) {
7c3df132 4489 ql_dbg(ql_dbg_mbx, vha, 0x1019, "Failed=%x.\n", rval);
794a5691
AV		 4490 ha->flags.thermal_supported = 0;
4491 goto fail;
4492 }
6ad11eaa 4493 *frac = (byte >> 6) * 25;
794a5691 4494
5f28d2d7
SK		 4495 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1018,
4496 "Done %s.\n", __func__);
37f489b5 4497 return rval;
794a5691 4498fail:
37f489b5
JC		 4499 ql_log(ql_log_warn, vha, 0x1150,
4500 "Thermal not supported by this card "
4501 "(ignoring further requests).\n");
794a5691
AV		 4502 return rval;
4503}
4504
a9083016
GM		 4505int
4506qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
4507{
4508 int rval;
4509 struct qla_hw_data *ha = vha->hw;
4510 mbx_cmd_t mc;
4511 mbx_cmd_t *mcp = &mc;
4512
5f28d2d7
SK		 4513 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
4514 "Entered %s.\n", __func__);
7c3df132 4515
a9083016
GM		 4516 if (!IS_FWI2_CAPABLE(ha))
4517 return QLA_FUNCTION_FAILED;
4518
a9083016 4519 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 4520 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 4521 mcp->mb[1] = 1;
4522
4523 mcp->out_mb = MBX_1|MBX_0;
4524 mcp->in_mb = MBX_0;
4525 mcp->tov = 30;
4526 mcp->flags = 0;
4527
4528 rval = qla2x00_mailbox_command(vha, mcp);
4529 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4530 ql_dbg(ql_dbg_mbx, vha, 0x1016,
4531 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 4532 } else {
5f28d2d7
SK		 4533 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
4534 "Done %s.\n", __func__);
a9083016
GM		 4535 }
4536
4537 return rval;
4538}
4539
4540int
4541qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
4542{
4543 int rval;
4544 struct qla_hw_data *ha = vha->hw;
4545 mbx_cmd_t mc;
4546 mbx_cmd_t *mcp = &mc;
4547
5f28d2d7
SK		 4548 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
4549 "Entered %s.\n", __func__);
7c3df132 4550
a9083016
GM		 4551 if (!IS_QLA82XX(ha))
4552 return QLA_FUNCTION_FAILED;
4553
a9083016 4554 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 4555 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 4556 mcp->mb[1] = 0;
4557
4558 mcp->out_mb = MBX_1|MBX_0;
4559 mcp->in_mb = MBX_0;
4560 mcp->tov = 30;
4561 mcp->flags = 0;
4562
4563 rval = qla2x00_mailbox_command(vha, mcp);
4564 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4565 ql_dbg(ql_dbg_mbx, vha, 0x100c,
4566 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 4567 } else {
5f28d2d7
SK		 4568 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
4569 "Done %s.\n", __func__);
a9083016
GM		 4570 }
4571
4572 return rval;
4573}
08de2844
GM		 4574
4575int
4576qla82xx_md_get_template_size(scsi_qla_host_t *vha)
4577{
4578 struct qla_hw_data *ha = vha->hw;
4579 mbx_cmd_t mc;
4580 mbx_cmd_t *mcp = &mc;
4581 int rval = QLA_FUNCTION_FAILED;
4582
5f28d2d7
SK		 4583 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
4584 "Entered %s.\n", __func__);
08de2844
GM		 4585
4586 memset(mcp->mb, 0 , sizeof(mcp->mb));
4587 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4588 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4589 mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
4590 mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
4591
4592 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
4593 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
4594 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4595
4596 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4597 mcp->tov = MBX_TOV_SECONDS;
4598 rval = qla2x00_mailbox_command(vha, mcp);
4599
4600 /* Always copy back return mailbox values. */
4601 if (rval != QLA_SUCCESS) {
4602 ql_dbg(ql_dbg_mbx, vha, 0x1120,
4603 "mailbox command FAILED=0x%x, subcode=%x.\n",
4604 (mcp->mb[1] << 16) | mcp->mb[0],
4605 (mcp->mb[3] << 16) | mcp->mb[2]);
4606 } else {
5f28d2d7
SK		 4607 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
4608 "Done %s.\n", __func__);
08de2844
GM		 4609 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
4610 if (!ha->md_template_size) {
4611 ql_dbg(ql_dbg_mbx, vha, 0x1122,
4612 "Null template size obtained.\n");
4613 rval = QLA_FUNCTION_FAILED;
4614 }
4615 }
4616 return rval;
4617}
4618
4619int
4620qla82xx_md_get_template(scsi_qla_host_t *vha)
4621{
4622 struct qla_hw_data *ha = vha->hw;
4623 mbx_cmd_t mc;
4624 mbx_cmd_t *mcp = &mc;
4625 int rval = QLA_FUNCTION_FAILED;
4626
5f28d2d7
SK		 4627 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
4628 "Entered %s.\n", __func__);
08de2844
GM		 4629
4630 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
4631 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
4632 if (!ha->md_tmplt_hdr) {
4633 ql_log(ql_log_warn, vha, 0x1124,
4634 "Unable to allocate memory for Minidump template.\n");
4635 return rval;
4636 }
4637
4638 memset(mcp->mb, 0 , sizeof(mcp->mb));
4639 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4640 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4641 mcp->mb[2] = LSW(RQST_TMPLT);
4642 mcp->mb[3] = MSW(RQST_TMPLT);
4643 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
4644 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
4645 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
4646 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
4647 mcp->mb[8] = LSW(ha->md_template_size);
4648 mcp->mb[9] = MSW(ha->md_template_size);
4649
4650 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4651 mcp->tov = MBX_TOV_SECONDS;
4652 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
4653 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4654 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
4655 rval = qla2x00_mailbox_command(vha, mcp);
4656
4657 if (rval != QLA_SUCCESS) {
4658 ql_dbg(ql_dbg_mbx, vha, 0x1125,
4659 "mailbox command FAILED=0x%x, subcode=%x.\n",
4660 ((mcp->mb[1] << 16) | mcp->mb[0]),
4661 ((mcp->mb[3] << 16) | mcp->mb[2]));
4662 } else
5f28d2d7
SK		 4663 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
4664 "Done %s.\n", __func__);
08de2844
GM		 4665 return rval;
4666}
999916dc 4667
6246b8a1
GM		 4668int
4669qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
4670{
4671 int rval;
4672 struct qla_hw_data *ha = vha->hw;
4673 mbx_cmd_t mc;
4674 mbx_cmd_t *mcp = &mc;
4675
4676 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
4677 return QLA_FUNCTION_FAILED;
4678
5f28d2d7
SK		 4679 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
4680 "Entered %s.\n", __func__);
6246b8a1
GM		 4681
4682 memset(mcp, 0, sizeof(mbx_cmd_t));
4683 mcp->mb[0] = MBC_SET_LED_CONFIG;
4684 mcp->mb[1] = led_cfg[0];
4685 mcp->mb[2] = led_cfg[1];
4686 if (IS_QLA8031(ha)) {
4687 mcp->mb[3] = led_cfg[2];
4688 mcp->mb[4] = led_cfg[3];
4689 mcp->mb[5] = led_cfg[4];
4690 mcp->mb[6] = led_cfg[5];
4691 }
4692
4693 mcp->out_mb = MBX_2|MBX_1|MBX_0;
4694 if (IS_QLA8031(ha))
4695 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
4696 mcp->in_mb = MBX_0;
4697 mcp->tov = 30;
4698 mcp->flags = 0;
4699
4700 rval = qla2x00_mailbox_command(vha, mcp);
4701 if (rval != QLA_SUCCESS) {
4702 ql_dbg(ql_dbg_mbx, vha, 0x1134,
4703 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4704 } else {
5f28d2d7
SK		 4705 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
4706 "Done %s.\n", __func__);
6246b8a1
GM		 4707 }
4708
4709 return rval;
4710}
4711
4712int
4713qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
4714{
4715 int rval;
4716 struct qla_hw_data *ha = vha->hw;
4717 mbx_cmd_t mc;
4718 mbx_cmd_t *mcp = &mc;
4719
4720 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
4721 return QLA_FUNCTION_FAILED;
4722
5f28d2d7
SK		 4723 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
4724 "Entered %s.\n", __func__);
6246b8a1
GM		 4725
4726 memset(mcp, 0, sizeof(mbx_cmd_t));
4727 mcp->mb[0] = MBC_GET_LED_CONFIG;
4728
4729 mcp->out_mb = MBX_0;
4730 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4731 if (IS_QLA8031(ha))
4732 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
4733 mcp->tov = 30;
4734 mcp->flags = 0;
4735
4736 rval = qla2x00_mailbox_command(vha, mcp);
4737 if (rval != QLA_SUCCESS) {
4738 ql_dbg(ql_dbg_mbx, vha, 0x1137,
4739 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4740 } else {
4741 led_cfg[0] = mcp->mb[1];
4742 led_cfg[1] = mcp->mb[2];
4743 if (IS_QLA8031(ha)) {
4744 led_cfg[2] = mcp->mb[3];
4745 led_cfg[3] = mcp->mb[4];
4746 led_cfg[4] = mcp->mb[5];
4747 led_cfg[5] = mcp->mb[6];
4748 }
5f28d2d7
SK		 4749 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
4750 "Done %s.\n", __func__);
6246b8a1
GM		 4751 }
4752
4753 return rval;
4754}
4755
999916dc
SK		 4756int
4757qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
4758{
4759 int rval;
4760 struct qla_hw_data *ha = vha->hw;
4761 mbx_cmd_t mc;
4762 mbx_cmd_t *mcp = &mc;
4763
4764 if (!IS_QLA82XX(ha))
4765 return QLA_FUNCTION_FAILED;
4766
5f28d2d7 4767 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
999916dc
SK		 4768 "Entered %s.\n", __func__);
4769
4770 memset(mcp, 0, sizeof(mbx_cmd_t));
4771 mcp->mb[0] = MBC_SET_LED_CONFIG;
4772 if (enable)
4773 mcp->mb[7] = 0xE;
4774 else
4775 mcp->mb[7] = 0xD;
4776
4777 mcp->out_mb = MBX_7|MBX_0;
4778 mcp->in_mb = MBX_0;
6246b8a1 4779 mcp->tov = MBX_TOV_SECONDS;
999916dc
SK		 4780 mcp->flags = 0;
4781
4782 rval = qla2x00_mailbox_command(vha, mcp);
4783 if (rval != QLA_SUCCESS) {
4784 ql_dbg(ql_dbg_mbx, vha, 0x1128,
4785 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4786 } else {
5f28d2d7 4787 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
999916dc
SK		 4788 "Done %s.\n", __func__);
4789 }
4790
4791 return rval;
4792}
6246b8a1
GM		 4793
4794int
7d613ac6 4795qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
6246b8a1
GM		 4796{
4797 int rval;
4798 struct qla_hw_data *ha = vha->hw;
4799 mbx_cmd_t mc;
4800 mbx_cmd_t *mcp = &mc;
4801
4802 if (!IS_QLA83XX(ha))
4803 return QLA_FUNCTION_FAILED;
4804
5f28d2d7
SK		 4805 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
4806 "Entered %s.\n", __func__);
6246b8a1
GM		 4807
4808 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
4809 mcp->mb[1] = LSW(reg);
4810 mcp->mb[2] = MSW(reg);
4811 mcp->mb[3] = LSW(data);
4812 mcp->mb[4] = MSW(data);
4813 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4814
4815 mcp->in_mb = MBX_1|MBX_0;
4816 mcp->tov = MBX_TOV_SECONDS;
4817 mcp->flags = 0;
4818 rval = qla2x00_mailbox_command(vha, mcp);
4819
4820 if (rval != QLA_SUCCESS) {
4821 ql_dbg(ql_dbg_mbx, vha, 0x1131,
4822 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4823 } else {
5f28d2d7 4824 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
6246b8a1
GM		 4825 "Done %s.\n", __func__);
4826 }
af11f64d 4827
6246b8a1
GM		 4828 return rval;
4829}
af11f64d
AV		 4830
4831int
4832qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
4833{
4834 int rval;
4835 struct qla_hw_data *ha = vha->hw;
4836 mbx_cmd_t mc;
4837 mbx_cmd_t *mcp = &mc;
4838
4839 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
5f28d2d7 4840 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
af11f64d
AV		 4841 "Implicit LOGO Unsupported.\n");
4842 return QLA_FUNCTION_FAILED;
4843 }
4844
4845
5f28d2d7
SK		 4846 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
4847 "Entering %s.\n", __func__);
af11f64d
AV		 4848
4849 /* Perform Implicit LOGO. */
4850 mcp->mb[0] = MBC_PORT_LOGOUT;
4851 mcp->mb[1] = fcport->loop_id;
4852 mcp->mb[10] = BIT_15;
4853 mcp->out_mb = MBX_10|MBX_1|MBX_0;
4854 mcp->in_mb = MBX_0;
4855 mcp->tov = MBX_TOV_SECONDS;
4856 mcp->flags = 0;
4857 rval = qla2x00_mailbox_command(vha, mcp);
4858 if (rval != QLA_SUCCESS)
4859 ql_dbg(ql_dbg_mbx, vha, 0x113d,
4860 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4861 else
5f28d2d7
SK		 4862 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
4863 "Done %s.\n", __func__);
af11f64d
AV		 4864
4865 return rval;
4866}
4867
7d613ac6
SV		 4868int
4869qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
4870{
4871 int rval;
4872 mbx_cmd_t mc;
4873 mbx_cmd_t *mcp = &mc;
4874 struct qla_hw_data *ha = vha->hw;
4875 unsigned long retry_max_time = jiffies + (2 * HZ);
4876
4877 if (!IS_QLA83XX(ha))
4878 return QLA_FUNCTION_FAILED;
4879
4880 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
4881
4882retry_rd_reg:
4883 mcp->mb[0] = MBC_READ_REMOTE_REG;
4884 mcp->mb[1] = LSW(reg);
4885 mcp->mb[2] = MSW(reg);
4886 mcp->out_mb = MBX_2|MBX_1|MBX_0;
4887 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
4888 mcp->tov = MBX_TOV_SECONDS;
4889 mcp->flags = 0;
4890 rval = qla2x00_mailbox_command(vha, mcp);
4891
4892 if (rval != QLA_SUCCESS) {
4893 ql_dbg(ql_dbg_mbx, vha, 0x114c,
4894 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4895 rval, mcp->mb[0], mcp->mb[1]);
4896 } else {
4897 *data = (mcp->mb[3] | (mcp->mb[4] << 16));
4898 if (*data == QLA8XXX_BAD_VALUE) {
4899 /*
4900 * During soft-reset CAMRAM register reads might
4901 * return 0xbad0bad0. So retry for MAX of 2 sec
4902 * while reading camram registers.
4903 */
4904 if (time_after(jiffies, retry_max_time)) {
4905 ql_dbg(ql_dbg_mbx, vha, 0x1141,
4906 "Failure to read CAMRAM register. "
4907 "data=0x%x.\n", *data);
4908 return QLA_FUNCTION_FAILED;
4909 }
4910 msleep(100);
4911 goto retry_rd_reg;
4912 }
4913 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
4914 }
4915
4916 return rval;
4917}
4918
4919int
4920qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
4921{
4922 int rval;
4923 mbx_cmd_t mc;
4924 mbx_cmd_t *mcp = &mc;
4925 struct qla_hw_data *ha = vha->hw;
4926
4927 if (!IS_QLA83XX(ha))
4928 return QLA_FUNCTION_FAILED;
4929
4930 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
4931
4932 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
4933 mcp->out_mb = MBX_0;
4934 mcp->in_mb = MBX_1|MBX_0;
4935 mcp->tov = MBX_TOV_SECONDS;
4936 mcp->flags = 0;
4937 rval = qla2x00_mailbox_command(vha, mcp);
4938
4939 if (rval != QLA_SUCCESS) {
4940 ql_dbg(ql_dbg_mbx, vha, 0x1144,
4941 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4942 rval, mcp->mb[0], mcp->mb[1]);
4943 ha->isp_ops->fw_dump(vha, 0);
4944 } else {
4945 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
4946 }
4947
4948 return rval;
4949}
4950
4951int
4952qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
4953 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
4954{
4955 int rval;
4956 mbx_cmd_t mc;
4957 mbx_cmd_t *mcp = &mc;
4958 uint8_t subcode = (uint8_t)options;
4959 struct qla_hw_data *ha = vha->hw;
4960
4961 if (!IS_QLA8031(ha))
4962 return QLA_FUNCTION_FAILED;
4963
4964 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
4965
4966 mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
4967 mcp->mb[1] = options;
4968 mcp->out_mb = MBX_1|MBX_0;
4969 if (subcode & BIT_2) {
4970 mcp->mb[2] = LSW(start_addr);
4971 mcp->mb[3] = MSW(start_addr);
4972 mcp->mb[4] = LSW(end_addr);
4973 mcp->mb[5] = MSW(end_addr);
4974 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
4975 }
4976 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4977 if (!(subcode & (BIT_2 | BIT_5)))
4978 mcp->in_mb |= MBX_4|MBX_3;
4979 mcp->tov = MBX_TOV_SECONDS;
4980 mcp->flags = 0;
4981 rval = qla2x00_mailbox_command(vha, mcp);
4982
4983 if (rval != QLA_SUCCESS) {
4984 ql_dbg(ql_dbg_mbx, vha, 0x1147,
4985 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
4986 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
4987 mcp->mb[4]);
4988 ha->isp_ops->fw_dump(vha, 0);
4989 } else {
4990 if (subcode & BIT_5)
4991 *sector_size = mcp->mb[1];
4992 else if (subcode & (BIT_6 | BIT_7)) {
4993 ql_dbg(ql_dbg_mbx, vha, 0x1148,
4994 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
4995 } else if (subcode & (BIT_3 | BIT_4)) {
4996 ql_dbg(ql_dbg_mbx, vha, 0x1149,
4997 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
4998 }
4999 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
5000 }
5001
5002 return rval;
5003}
81178772
SK		 5004
5005int
5006qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
5007 uint32_t size)
5008{
5009 int rval;
5010 mbx_cmd_t mc;
5011 mbx_cmd_t *mcp = &mc;
5012
5013 if (!IS_MCTP_CAPABLE(vha->hw))
5014 return QLA_FUNCTION_FAILED;
5015
5016 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
5017 "Entered %s.\n", __func__);
5018
5019 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
5020 mcp->mb[1] = LSW(addr);
5021 mcp->mb[2] = MSW(req_dma);
5022 mcp->mb[3] = LSW(req_dma);
5023 mcp->mb[4] = MSW(size);
5024 mcp->mb[5] = LSW(size);
5025 mcp->mb[6] = MSW(MSD(req_dma));
5026 mcp->mb[7] = LSW(MSD(req_dma));
5027 mcp->mb[8] = MSW(addr);
5028 /* Setting RAM ID to valid */
5029 mcp->mb[10] |= BIT_7;
5030 /* For MCTP RAM ID is 0x40 */
5031 mcp->mb[10] |= 0x40;
5032
5033 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
5034 MBX_0;
5035
5036 mcp->in_mb = MBX_0;
5037 mcp->tov = MBX_TOV_SECONDS;
5038 mcp->flags = 0;
5039 rval = qla2x00_mailbox_command(vha, mcp);
5040
5041 if (rval != QLA_SUCCESS) {
5042 ql_dbg(ql_dbg_mbx, vha, 0x114e,
5043 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5044 } else {
5045 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
5046 "Done %s.\n", __func__);
5047 }
5048
5049 return rval;
5050}
Linux 6.x block layer and io_uring tree(s)