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kbuild: descend into scripts/gcc-plugins/ via scripts/Makefile
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_mbx.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
2d70c103 8#include "qla_target.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/gfp.h>
1da177e4 12
15f30a57
QT		 13static struct mb_cmd_name {
14 uint16_t cmd;
15 const char *str;
16} mb_str[] = {
17 {MBC_GET_PORT_DATABASE, "GPDB"},
18 {MBC_GET_ID_LIST, "GIDList"},
19 {MBC_GET_LINK_PRIV_STATS, "Stats"},
94d83e36 20 {MBC_GET_RESOURCE_COUNTS, "ResCnt"},
15f30a57
QT		 21};
22
23static const char *mb_to_str(uint16_t cmd)
24{
25 int i;
26 struct mb_cmd_name *e;
27
28 for (i = 0; i < ARRAY_SIZE(mb_str); i++) {
29 e = mb_str + i;
30 if (cmd == e->cmd)
31 return e->str;
32 }
33 return "unknown";
34}
35
ca825828 36static struct rom_cmd {
77ddb94a 37 uint16_t cmd;
38} rom_cmds[] = {
39 { MBC_LOAD_RAM },
40 { MBC_EXECUTE_FIRMWARE },
41 { MBC_READ_RAM_WORD },
42 { MBC_MAILBOX_REGISTER_TEST },
43 { MBC_VERIFY_CHECKSUM },
44 { MBC_GET_FIRMWARE_VERSION },
45 { MBC_LOAD_RISC_RAM },
46 { MBC_DUMP_RISC_RAM },
47 { MBC_LOAD_RISC_RAM_EXTENDED },
48 { MBC_DUMP_RISC_RAM_EXTENDED },
49 { MBC_WRITE_RAM_WORD_EXTENDED },
50 { MBC_READ_RAM_EXTENDED },
51 { MBC_GET_RESOURCE_COUNTS },
52 { MBC_SET_FIRMWARE_OPTION },
53 { MBC_MID_INITIALIZE_FIRMWARE },
54 { MBC_GET_FIRMWARE_STATE },
55 { MBC_GET_MEM_OFFLOAD_CNTRL_STAT },
56 { MBC_GET_RETRY_COUNT },
57 { MBC_TRACE_CONTROL },
b7edfa23 58 { MBC_INITIALIZE_MULTIQ },
1608cc4a
QT		 59 { MBC_IOCB_COMMAND_A64 },
60 { MBC_GET_ADAPTER_LOOP_ID },
e4e3a2ce 61 { MBC_READ_SFP },
8777e431 62 { MBC_GET_RNID_PARAMS },
8b4673ba 63 { MBC_GET_SET_ZIO_THRESHOLD },
77ddb94a 64};
65
66static int is_rom_cmd(uint16_t cmd)
67{
68 int i;
69 struct rom_cmd *wc;
70
71 for (i = 0; i < ARRAY_SIZE(rom_cmds); i++) {
72 wc = rom_cmds + i;
73 if (wc->cmd == cmd)
74 return 1;
75 }
76
77 return 0;
78}
1da177e4
LT		 79
80/*
81 * qla2x00_mailbox_command
82 * Issue mailbox command and waits for completion.
83 *
84 * Input:
85 * ha = adapter block pointer.
86 * mcp = driver internal mbx struct pointer.
87 *
88 * Output:
89 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
90 *
91 * Returns:
92 * 0 : QLA_SUCCESS = cmd performed success
93 * 1 : QLA_FUNCTION_FAILED (error encountered)
94 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
95 *
96 * Context:
97 * Kernel context.
98 */
99static int
7b867cf7 100qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
1da177e4 101{
d14e72fb 102 int rval, i;
1da177e4 103 unsigned long flags = 0;
f73cb695 104 device_reg_t *reg;
1c7c6357 105 uint8_t abort_active;
2c3dfe3f 106 uint8_t io_lock_on;
cdbb0a4f 107 uint16_t command = 0;
1da177e4
LT		 108 uint16_t *iptr;
109 uint16_t __iomem *optr;
110 uint32_t cnt;
111 uint32_t mboxes;
1da177e4 112 unsigned long wait_time;
7b867cf7
AC		 113 struct qla_hw_data *ha = vha->hw;
114 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
b2000805 115 u32 chip_reset;
2c3dfe3f 116
d14e72fb 117
5e19ed90 118 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
7c3df132
SK		 119
120 if (ha->pdev->error_state > pci_channel_io_frozen) {
5e19ed90 121 ql_log(ql_log_warn, vha, 0x1001,
7c3df132
SK		 122 "error_state is greater than pci_channel_io_frozen, "
123 "exiting.\n");
b9b12f73 124 return QLA_FUNCTION_TIMEOUT;
7c3df132 125 }
b9b12f73 126
a9083016 127 if (vha->device_flags & DFLG_DEV_FAILED) {
5e19ed90 128 ql_log(ql_log_warn, vha, 0x1002,
7c3df132 129 "Device in failed state, exiting.\n");
a9083016
GM		 130 return QLA_FUNCTION_TIMEOUT;
131 }
132
c2a5d94f 133 /* if PCI error, then avoid mbx processing.*/
ba175891
SC		 134 if (test_bit(PFLG_DISCONNECTED, &base_vha->dpc_flags) &&
135 test_bit(UNLOADING, &base_vha->dpc_flags)) {
83548fe2 136 ql_log(ql_log_warn, vha, 0xd04e,
783e0dc4
SC		 137 "PCI error, exiting.\n");
138 return QLA_FUNCTION_TIMEOUT;
c2a5d94f 139 }
783e0dc4 140
2c3dfe3f 141 reg = ha->iobase;
7b867cf7 142 io_lock_on = base_vha->flags.init_done;
1da177e4
LT		 143
144 rval = QLA_SUCCESS;
7b867cf7 145 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
b2000805 146 chip_reset = ha->chip_reset;
1da177e4 147
85880801 148 if (ha->flags.pci_channel_io_perm_failure) {
5e19ed90 149 ql_log(ql_log_warn, vha, 0x1003,
7c3df132 150 "Perm failure on EEH timeout MBX, exiting.\n");
85880801
AV		 151 return QLA_FUNCTION_TIMEOUT;
152 }
153
7ec0effd 154 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
862cd01e
GM		 155 /* Setting Link-Down error */
156 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
5e19ed90 157 ql_log(ql_log_warn, vha, 0x1004,
7c3df132 158 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
1806fcd5 159 return QLA_FUNCTION_TIMEOUT;
862cd01e
GM		 160 }
161
77ddb94a 162 /* check if ISP abort is active and return cmd with timeout */
163 if ((test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
164 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
165 test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) &&
166 !is_rom_cmd(mcp->mb[0])) {
167 ql_log(ql_log_info, vha, 0x1005,
168 "Cmd 0x%x aborted with timeout since ISP Abort is pending\n",
169 mcp->mb[0]);
170 return QLA_FUNCTION_TIMEOUT;
171 }
172
b2000805 173 atomic_inc(&ha->num_pend_mbx_stage1);
1da177e4 174 /*
1c7c6357
AV		 175 * Wait for active mailbox commands to finish by waiting at most tov
176 * seconds. This is to serialize actual issuing of mailbox cmds during
177 * non ISP abort time.
1da177e4 178 */
8eca3f39
AV		 179 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
180 /* Timeout occurred. Return error. */
83548fe2 181 ql_log(ql_log_warn, vha, 0xd035,
d8c0d546
CD		 182 "Cmd access timeout, cmd=0x%x, Exiting.\n",
183 mcp->mb[0]);
b2000805 184 atomic_dec(&ha->num_pend_mbx_stage1);
8eca3f39 185 return QLA_FUNCTION_TIMEOUT;
1da177e4 186 }
b2000805
QT		 187 atomic_dec(&ha->num_pend_mbx_stage1);
188 if (ha->flags.purge_mbox || chip_reset != ha->chip_reset) {
189 rval = QLA_ABORTED;
190 goto premature_exit;
191 }
1da177e4 192
b6faaaf7 193
1da177e4
LT		 194 /* Save mailbox command for debug */
195 ha->mcp = mcp;
196
5e19ed90 197 ql_dbg(ql_dbg_mbx, vha, 0x1006,
7c3df132 198 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
1da177e4
LT		 199
200 spin_lock_irqsave(&ha->hardware_lock, flags);
201
b6faaaf7
QT		 202 if (ha->flags.purge_mbox || chip_reset != ha->chip_reset ||
203 ha->flags.mbox_busy) {
b2000805 204 rval = QLA_ABORTED;
b2000805
QT		 205 spin_unlock_irqrestore(&ha->hardware_lock, flags);
206 goto premature_exit;
207 }
b6faaaf7 208 ha->flags.mbox_busy = 1;
b2000805 209
1da177e4 210 /* Load mailbox registers. */
7ec0effd 211 if (IS_P3P_TYPE(ha))
a9083016 212 optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
7ec0effd 213 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
1c7c6357
AV		 214 optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
215 else
216 optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
1da177e4
LT		 217
218 iptr = mcp->mb;
219 command = mcp->mb[0];
220 mboxes = mcp->out_mb;
221
7b711623 222 ql_dbg(ql_dbg_mbx, vha, 0x1111,
0e31a2c8 223 "Mailbox registers (OUT):\n");
1da177e4
LT		 224 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
225 if (IS_QLA2200(ha) && cnt == 8)
1c7c6357
AV		 226 optr =
227 (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
0e31a2c8
JC		 228 if (mboxes & BIT_0) {
229 ql_dbg(ql_dbg_mbx, vha, 0x1112,
230 "mbox[%d]<-0x%04x\n", cnt, *iptr);
1da177e4 231 WRT_REG_WORD(optr, *iptr);
0e31a2c8 232 }
1da177e4
LT		 233
234 mboxes >>= 1;
235 optr++;
236 iptr++;
237 }
238
5e19ed90 239 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
7c3df132 240 "I/O Address = %p.\n", optr);
1da177e4
LT		 241
242 /* Issue set host interrupt command to send cmd out. */
243 ha->flags.mbox_int = 0;
244 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
245
246 /* Unlock mbx registers and wait for interrupt */
5e19ed90 247 ql_dbg(ql_dbg_mbx, vha, 0x100f,
7c3df132
SK		 248 "Going to unlock irq & waiting for interrupts. "
249 "jiffies=%lx.\n", jiffies);
1da177e4
LT		 250
251 /* Wait for mbx cmd completion until timeout */
b2000805 252 atomic_inc(&ha->num_pend_mbx_stage2);
124f85e6 253 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
1da177e4
LT		 254 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
255
7ec0effd 256 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 257 if (RD_REG_DWORD(&reg->isp82.hint) &
258 HINT_MBX_INT_PENDING) {
b6faaaf7 259 ha->flags.mbox_busy = 0;
a9083016
GM		 260 spin_unlock_irqrestore(&ha->hardware_lock,
261 flags);
b6faaaf7 262
b2000805 263 atomic_dec(&ha->num_pend_mbx_stage2);
5e19ed90 264 ql_dbg(ql_dbg_mbx, vha, 0x1010,
7c3df132 265 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 266 rval = QLA_FUNCTION_TIMEOUT;
267 goto premature_exit;
a9083016
GM		 268 }
269 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
270 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 271 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
272 else
273 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4
LT		 274 spin_unlock_irqrestore(&ha->hardware_lock, flags);
275
77ddb94a 276 wait_time = jiffies;
b2000805 277 atomic_inc(&ha->num_pend_mbx_stage3);
754d1243
GM		 278 if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
279 mcp->tov * HZ)) {
b6faaaf7
QT		 280 if (chip_reset != ha->chip_reset) {
281 spin_lock_irqsave(&ha->hardware_lock, flags);
282 ha->flags.mbox_busy = 0;
283 spin_unlock_irqrestore(&ha->hardware_lock,
284 flags);
285 atomic_dec(&ha->num_pend_mbx_stage2);
286 atomic_dec(&ha->num_pend_mbx_stage3);
287 rval = QLA_ABORTED;
288 goto premature_exit;
289 }
754d1243
GM		 290 ql_dbg(ql_dbg_mbx, vha, 0x117a,
291 "cmd=%x Timeout.\n", command);
292 spin_lock_irqsave(&ha->hardware_lock, flags);
293 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
294 spin_unlock_irqrestore(&ha->hardware_lock, flags);
b2000805
QT		 295
296 } else if (ha->flags.purge_mbox ||
297 chip_reset != ha->chip_reset) {
b6faaaf7 298 spin_lock_irqsave(&ha->hardware_lock, flags);
b2000805 299 ha->flags.mbox_busy = 0;
b6faaaf7 300 spin_unlock_irqrestore(&ha->hardware_lock, flags);
b2000805
QT		 301 atomic_dec(&ha->num_pend_mbx_stage2);
302 atomic_dec(&ha->num_pend_mbx_stage3);
303 rval = QLA_ABORTED;
304 goto premature_exit;
754d1243 305 }
b2000805
QT		 306 atomic_dec(&ha->num_pend_mbx_stage3);
307
77ddb94a 308 if (time_after(jiffies, wait_time + 5 * HZ))
309 ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n",
310 command, jiffies_to_msecs(jiffies - wait_time));
1da177e4 311 } else {
5e19ed90 312 ql_dbg(ql_dbg_mbx, vha, 0x1011,
7c3df132 313 "Cmd=%x Polling Mode.\n", command);
1da177e4 314
7ec0effd 315 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 316 if (RD_REG_DWORD(&reg->isp82.hint) &
317 HINT_MBX_INT_PENDING) {
b6faaaf7 318 ha->flags.mbox_busy = 0;
a9083016
GM		 319 spin_unlock_irqrestore(&ha->hardware_lock,
320 flags);
b2000805 321 atomic_dec(&ha->num_pend_mbx_stage2);
5e19ed90 322 ql_dbg(ql_dbg_mbx, vha, 0x1012,
7c3df132 323 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 324 rval = QLA_FUNCTION_TIMEOUT;
325 goto premature_exit;
a9083016
GM		 326 }
327 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
328 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 329 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
330 else
331 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4 332 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4
LT		 333
334 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
335 while (!ha->flags.mbox_int) {
b2000805
QT		 336 if (ha->flags.purge_mbox ||
337 chip_reset != ha->chip_reset) {
b6faaaf7 338 spin_lock_irqsave(&ha->hardware_lock, flags);
b2000805 339 ha->flags.mbox_busy = 0;
b6faaaf7
QT		 340 spin_unlock_irqrestore(&ha->hardware_lock,
341 flags);
b2000805
QT		 342 atomic_dec(&ha->num_pend_mbx_stage2);
343 rval = QLA_ABORTED;
344 goto premature_exit;
345 }
346
1da177e4
LT		 347 if (time_after(jiffies, wait_time))
348 break;
349
3cb182b3
RG		 350 /*
351 * Check if it's UNLOADING, cause we cannot poll in
352 * this case, or else a NULL pointer dereference
353 * is triggered.
354 */
355 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)))
356 return QLA_FUNCTION_TIMEOUT;
357
1da177e4 358 /* Check for pending interrupts. */
73208dfd 359 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4 360
85880801
AV		 361 if (!ha->flags.mbox_int &&
362 !(IS_QLA2200(ha) &&
363 command == MBC_LOAD_RISC_RAM_EXTENDED))
59989831 364 msleep(10);
1da177e4 365 } /* while */
5e19ed90 366 ql_dbg(ql_dbg_mbx, vha, 0x1013,
7c3df132
SK		 367 "Waited %d sec.\n",
368 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
1da177e4 369 }
b2000805 370 atomic_dec(&ha->num_pend_mbx_stage2);
1da177e4 371
1da177e4
LT		 372 /* Check whether we timed out */
373 if (ha->flags.mbox_int) {
374 uint16_t *iptr2;
375
5e19ed90 376 ql_dbg(ql_dbg_mbx, vha, 0x1014,
7c3df132 377 "Cmd=%x completed.\n", command);
1da177e4
LT		 378
379 /* Got interrupt. Clear the flag. */
380 ha->flags.mbox_int = 0;
381 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
382
7ec0effd 383 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
b6faaaf7 384 spin_lock_irqsave(&ha->hardware_lock, flags);
cdbb0a4f 385 ha->flags.mbox_busy = 0;
b6faaaf7
QT		 386 spin_unlock_irqrestore(&ha->hardware_lock, flags);
387
cdbb0a4f
SV		 388 /* Setting Link-Down error */
389 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
390 ha->mcp = NULL;
391 rval = QLA_FUNCTION_FAILED;
83548fe2 392 ql_log(ql_log_warn, vha, 0xd048,
7c3df132 393 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
cdbb0a4f
SV		 394 goto premature_exit;
395 }
396
354d6b21 397 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
1da177e4 398 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 399
400 /* Load return mailbox registers. */
401 iptr2 = mcp->mb;
402 iptr = (uint16_t *)&ha->mailbox_out[0];
403 mboxes = mcp->in_mb;
0e31a2c8
JC		 404
405 ql_dbg(ql_dbg_mbx, vha, 0x1113,
406 "Mailbox registers (IN):\n");
1da177e4 407 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
0e31a2c8 408 if (mboxes & BIT_0) {
1da177e4 409 *iptr2 = *iptr;
0e31a2c8
JC		 410 ql_dbg(ql_dbg_mbx, vha, 0x1114,
411 "mbox[%d]->0x%04x\n", cnt, *iptr2);
412 }
1da177e4
LT		 413
414 mboxes >>= 1;
415 iptr2++;
416 iptr++;
417 }
418 } else {
419
8d3c9c23
QT		 420 uint16_t mb[8];
421 uint32_t ictrl, host_status, hccr;
783e0dc4 422 uint16_t w;
1c7c6357 423
e428924c 424 if (IS_FWI2_CAPABLE(ha)) {
8d3c9c23
QT		 425 mb[0] = RD_REG_WORD(&reg->isp24.mailbox0);
426 mb[1] = RD_REG_WORD(&reg->isp24.mailbox1);
427 mb[2] = RD_REG_WORD(&reg->isp24.mailbox2);
428 mb[3] = RD_REG_WORD(&reg->isp24.mailbox3);
429 mb[7] = RD_REG_WORD(&reg->isp24.mailbox7);
1c7c6357 430 ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
8d3c9c23
QT		 431 host_status = RD_REG_DWORD(&reg->isp24.host_status);
432 hccr = RD_REG_DWORD(&reg->isp24.hccr);
433
83548fe2 434 ql_log(ql_log_warn, vha, 0xd04c,
8d3c9c23
QT		 435 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
436 "mb[0-3]=[0x%x 0x%x 0x%x 0x%x] mb7 0x%x host_status 0x%x hccr 0x%x\n",
437 command, ictrl, jiffies, mb[0], mb[1], mb[2], mb[3],
438 mb[7], host_status, hccr);
439
1c7c6357 440 } else {
8d3c9c23 441 mb[0] = RD_MAILBOX_REG(ha, &reg->isp, 0);
1c7c6357 442 ictrl = RD_REG_WORD(&reg->isp.ictrl);
8d3c9c23
QT		 443 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
444 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
445 "mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]);
1c7c6357 446 }
5e19ed90 447 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
1da177e4 448
783e0dc4
SC		 449 /* Capture FW dump only, if PCI device active */
450 if (!pci_channel_offline(vha->hw->pdev)) {
451 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
b2000805
QT		 452 if (w == 0xffff || ictrl == 0xffffffff ||
453 (chip_reset != ha->chip_reset)) {
783e0dc4
SC		 454 /* This is special case if there is unload
455 * of driver happening and if PCI device go
456 * into bad state due to PCI error condition
457 * then only PCI ERR flag would be set.
458 * we will do premature exit for above case.
459 */
b6faaaf7 460 spin_lock_irqsave(&ha->hardware_lock, flags);
783e0dc4 461 ha->flags.mbox_busy = 0;
b6faaaf7
QT		 462 spin_unlock_irqrestore(&ha->hardware_lock,
463 flags);
783e0dc4
SC		 464 rval = QLA_FUNCTION_TIMEOUT;
465 goto premature_exit;
466 }
f55bfc88 467
783e0dc4
SC		 468 /* Attempt to capture firmware dump for further
469 * anallysis of the current formware state. we do not
470 * need to do this if we are intentionally generating
471 * a dump
472 */
473 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
474 ha->isp_ops->fw_dump(vha, 0);
475 rval = QLA_FUNCTION_TIMEOUT;
476 }
1da177e4 477 }
b6faaaf7 478 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 479 ha->flags.mbox_busy = 0;
b6faaaf7 480 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4
LT		 481
482 /* Clean up */
483 ha->mcp = NULL;
484
124f85e6 485 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
5e19ed90 486 ql_dbg(ql_dbg_mbx, vha, 0x101a,
7c3df132 487 "Checking for additional resp interrupt.\n");
1da177e4
LT		 488
489 /* polling mode for non isp_abort commands. */
73208dfd 490 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4
LT		 491 }
492
1c7c6357
AV		 493 if (rval == QLA_FUNCTION_TIMEOUT &&
494 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
85880801
AV		 495 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
496 ha->flags.eeh_busy) {
1da177e4 497 /* not in dpc. schedule it for dpc to take over. */
5e19ed90 498 ql_dbg(ql_dbg_mbx, vha, 0x101b,
7c3df132 499 "Timeout, schedule isp_abort_needed.\n");
cdbb0a4f
SV		 500
501 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
502 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
503 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 504 if (IS_QLA82XX(ha)) {
505 ql_dbg(ql_dbg_mbx, vha, 0x112a,
506 "disabling pause transmit on port "
507 "0 & 1.\n");
508 qla82xx_wr_32(ha,
509 QLA82XX_CRB_NIU + 0x98,
510 CRB_NIU_XG_PAUSE_CTL_P0|
511 CRB_NIU_XG_PAUSE_CTL_P1);
512 }
7c3df132 513 ql_log(ql_log_info, base_vha, 0x101c,
24d9ee85 514 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 515 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
516 "abort.\n", command, mcp->mb[0],
517 ha->flags.eeh_busy);
cdbb0a4f
SV		 518 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
519 qla2xxx_wake_dpc(vha);
520 }
710bc78f 521 } else if (current == ha->dpc_thread) {
1da177e4 522 /* call abort directly since we are in the DPC thread */
5e19ed90 523 ql_dbg(ql_dbg_mbx, vha, 0x101d,
7c3df132 524 "Timeout, calling abort_isp.\n");
cdbb0a4f
SV		 525
526 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
527 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
528 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 529 if (IS_QLA82XX(ha)) {
530 ql_dbg(ql_dbg_mbx, vha, 0x112b,
531 "disabling pause transmit on port "
532 "0 & 1.\n");
533 qla82xx_wr_32(ha,
534 QLA82XX_CRB_NIU + 0x98,
535 CRB_NIU_XG_PAUSE_CTL_P0|
536 CRB_NIU_XG_PAUSE_CTL_P1);
537 }
7c3df132 538 ql_log(ql_log_info, base_vha, 0x101e,
24d9ee85 539 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 540 "mb[0]=0x%x. Scheduling ISP abort ",
541 command, mcp->mb[0]);
cdbb0a4f
SV		 542 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
543 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
d3360960
GM		 544 /* Allow next mbx cmd to come in. */
545 complete(&ha->mbx_cmd_comp);
cdbb0a4f
SV		 546 if (ha->isp_ops->abort_isp(vha)) {
547 /* Failed. retry later. */
548 set_bit(ISP_ABORT_NEEDED,
549 &vha->dpc_flags);
550 }
551 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
5e19ed90 552 ql_dbg(ql_dbg_mbx, vha, 0x101f,
7c3df132 553 "Finished abort_isp.\n");
d3360960 554 goto mbx_done;
1da177e4 555 }
1da177e4
LT		 556 }
557 }
558
cdbb0a4f 559premature_exit:
1da177e4 560 /* Allow next mbx cmd to come in. */
8eca3f39 561 complete(&ha->mbx_cmd_comp);
1da177e4 562
d3360960 563mbx_done:
b2000805
QT		 564 if (rval == QLA_ABORTED) {
565 ql_log(ql_log_info, vha, 0xd035,
566 "Chip Reset in progress. Purging Mbox cmd=0x%x.\n",
567 mcp->mb[0]);
568 } else if (rval) {
050dc76a
JC		 569 if (ql2xextended_error_logging & (ql_dbg_disc|ql_dbg_mbx)) {
570 pr_warn("%s [%s]-%04x:%ld: **** Failed", QL_MSGHDR,
571 dev_name(&ha->pdev->dev), 0x1020+0x800,
572 vha->host_no);
573 mboxes = mcp->in_mb;
574 cnt = 4;
575 for (i = 0; i < ha->mbx_count && cnt; i++, mboxes >>= 1)
576 if (mboxes & BIT_0) {
577 printk(" mb[%u]=%x", i, mcp->mb[i]);
578 cnt--;
579 }
580 pr_warn(" cmd=%x ****\n", command);
581 }
f7e59e99
MR		 582 if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) {
583 ql_dbg(ql_dbg_mbx, vha, 0x1198,
584 "host_status=%#x intr_ctrl=%#x intr_status=%#x\n",
585 RD_REG_DWORD(&reg->isp24.host_status),
586 RD_REG_DWORD(&reg->isp24.ictrl),
587 RD_REG_DWORD(&reg->isp24.istatus));
588 } else {
589 ql_dbg(ql_dbg_mbx, vha, 0x1206,
590 "ctrl_status=%#x ictrl=%#x istatus=%#x\n",
591 RD_REG_WORD(&reg->isp.ctrl_status),
592 RD_REG_WORD(&reg->isp.ictrl),
593 RD_REG_WORD(&reg->isp.istatus));
594 }
1da177e4 595 } else {
7c3df132 596 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
1da177e4
LT		 597 }
598
1da177e4
LT		 599 return rval;
600}
601
1da177e4 602int
7b867cf7 603qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
590f98e5 604 uint32_t risc_code_size)
1da177e4
LT		 605{
606 int rval;
7b867cf7 607 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 608 mbx_cmd_t mc;
609 mbx_cmd_t *mcp = &mc;
1da177e4 610
5f28d2d7
SK		 611 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
612 "Entered %s.\n", __func__);
1da177e4 613
e428924c 614 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
590f98e5 615 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
616 mcp->mb[8] = MSW(risc_addr);
617 mcp->out_mb = MBX_8|MBX_0;
1da177e4 618 } else {
590f98e5 619 mcp->mb[0] = MBC_LOAD_RISC_RAM;
620 mcp->out_mb = MBX_0;
1da177e4 621 }
1da177e4
LT		 622 mcp->mb[1] = LSW(risc_addr);
623 mcp->mb[2] = MSW(req_dma);
624 mcp->mb[3] = LSW(req_dma);
1da177e4
LT		 625 mcp->mb[6] = MSW(MSD(req_dma));
626 mcp->mb[7] = LSW(MSD(req_dma));
590f98e5 627 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
e428924c 628 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 629 mcp->mb[4] = MSW(risc_code_size);
630 mcp->mb[5] = LSW(risc_code_size);
631 mcp->out_mb |= MBX_5|MBX_4;
632 } else {
633 mcp->mb[4] = LSW(risc_code_size);
634 mcp->out_mb |= MBX_4;
635 }
636
1da177e4 637 mcp->in_mb = MBX_0;
b93480e3 638 mcp->tov = MBX_TOV_SECONDS;
1da177e4 639 mcp->flags = 0;
7b867cf7 640 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 641
1da177e4 642 if (rval != QLA_SUCCESS) {
7c3df132
SK		 643 ql_dbg(ql_dbg_mbx, vha, 0x1023,
644 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4 645 } else {
5f28d2d7
SK		 646 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
647 "Done %s.\n", __func__);
1da177e4
LT		 648 }
649
650 return rval;
651}
652
cad454b1 653#define EXTENDED_BB_CREDITS BIT_0
e84067d7 654#define NVME_ENABLE_FLAG BIT_3
1f4c7c38
JC		 655static inline uint16_t qla25xx_set_sfp_lr_dist(struct qla_hw_data *ha)
656{
657 uint16_t mb4 = BIT_0;
658
659 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
660 mb4 |= ha->long_range_distance << LR_DIST_FW_POS;
661
662 return mb4;
663}
664
665static inline uint16_t qla25xx_set_nvr_lr_dist(struct qla_hw_data *ha)
666{
667 uint16_t mb4 = BIT_0;
668
669 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
670 struct nvram_81xx *nv = ha->nvram;
671
672 mb4 |= LR_DIST_FW_FIELD(nv->enhanced_features);
673 }
674
675 return mb4;
676}
e84067d7 677
1da177e4
LT		 678/*
679 * qla2x00_execute_fw
1c7c6357 680 * Start adapter firmware.
1da177e4
LT		 681 *
682 * Input:
1c7c6357
AV		 683 * ha = adapter block pointer.
684 * TARGET_QUEUE_LOCK must be released.
685 * ADAPTER_STATE_LOCK must be released.
1da177e4
LT		 686 *
687 * Returns:
1c7c6357 688 * qla2x00 local function return status code.
1da177e4
LT		 689 *
690 * Context:
1c7c6357 691 * Kernel context.
1da177e4
LT		 692 */
693int
7b867cf7 694qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 695{
696 int rval;
7b867cf7 697 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 698 mbx_cmd_t mc;
699 mbx_cmd_t *mcp = &mc;
700
5f28d2d7
SK		 701 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
702 "Entered %s.\n", __func__);
1da177e4
LT		 703
704 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
1c7c6357
AV		 705 mcp->out_mb = MBX_0;
706 mcp->in_mb = MBX_0;
e428924c 707 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 708 mcp->mb[1] = MSW(risc_addr);
709 mcp->mb[2] = LSW(risc_addr);
710 mcp->mb[3] = 0;
e4e3a2ce 711 mcp->mb[4] = 0;
1f4c7c38 712 ha->flags.using_lr_setting = 0;
f73cb695
CD		 713 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
714 IS_QLA27XX(ha)) {
e4e3a2ce
QT		 715 if (ql2xautodetectsfp) {
716 if (ha->flags.detected_lr_sfp) {
1f4c7c38
JC		 717 mcp->mb[4] |=
718 qla25xx_set_sfp_lr_dist(ha);
e4e3a2ce
QT		 719 ha->flags.using_lr_setting = 1;
720 }
721 } else {
722 struct nvram_81xx *nv = ha->nvram;
1f4c7c38 723 /* set LR distance if specified in nvram */
e4e3a2ce 724 if (nv->enhanced_features &
1f4c7c38
JC		 725 NEF_LR_DIST_ENABLE) {
726 mcp->mb[4] |=
727 qla25xx_set_nvr_lr_dist(ha);
e4e3a2ce
QT		 728 ha->flags.using_lr_setting = 1;
729 }
730 }
e4e3a2ce 731 }
b0d6cabd 732
e84067d7
DG		 733 if (ql2xnvmeenable && IS_QLA27XX(ha))
734 mcp->mb[4] |= NVME_ENABLE_FLAG;
735
92d4408e
SC		 736 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
737 struct nvram_81xx *nv = ha->nvram;
738 /* set minimum speed if specified in nvram */
739 if (nv->min_link_speed >= 2 &&
740 nv->min_link_speed <= 5) {
741 mcp->mb[4] |= BIT_4;
742 mcp->mb[11] = nv->min_link_speed;
743 mcp->out_mb |= MBX_11;
744 mcp->in_mb |= BIT_5;
745 vha->min_link_speed_feat = nv->min_link_speed;
746 }
747 }
748
b0d6cabd
HM		 749 if (ha->flags.exlogins_enabled)
750 mcp->mb[4] |= ENABLE_EXTENDED_LOGIN;
751
2f56a7f1
HM		 752 if (ha->flags.exchoffld_enabled)
753 mcp->mb[4] |= ENABLE_EXCHANGE_OFFLD;
754
8b3253d1 755 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
1f4c7c38 756 mcp->in_mb |= MBX_3 | MBX_2 | MBX_1;
1c7c6357
AV		 757 } else {
758 mcp->mb[1] = LSW(risc_addr);
759 mcp->out_mb |= MBX_1;
760 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
761 mcp->mb[2] = 0;
762 mcp->out_mb |= MBX_2;
763 }
1da177e4
LT		 764 }
765
b93480e3 766 mcp->tov = MBX_TOV_SECONDS;
1da177e4 767 mcp->flags = 0;
7b867cf7 768 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 769
1c7c6357 770 if (rval != QLA_SUCCESS) {
7c3df132
SK		 771 ql_dbg(ql_dbg_mbx, vha, 0x1026,
772 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357 773 } else {
e428924c 774 if (IS_FWI2_CAPABLE(ha)) {
1f4c7c38
JC		 775 ha->fw_ability_mask = mcp->mb[3] << 16 | mcp->mb[2];
776 ql_dbg(ql_dbg_mbx, vha, 0x119a,
777 "fw_ability_mask=%x.\n", ha->fw_ability_mask);
92d4408e
SC		 778 ql_dbg(ql_dbg_mbx, vha, 0x1027,
779 "exchanges=%x.\n", mcp->mb[1]);
1f4c7c38
JC		 780 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
781 ha->max_speed_sup = mcp->mb[2] & BIT_0;
92d4408e
SC		 782 ql_dbg(ql_dbg_mbx, vha, 0x119b,
783 "Maximum speed supported=%s.\n",
784 ha->max_speed_sup ? "32Gps" : "16Gps");
785 if (vha->min_link_speed_feat) {
786 ha->min_link_speed = mcp->mb[5];
787 ql_dbg(ql_dbg_mbx, vha, 0x119c,
788 "Minimum speed set=%s.\n",
789 mcp->mb[5] == 5 ? "32Gps" :
790 mcp->mb[5] == 4 ? "16Gps" :
791 mcp->mb[5] == 3 ? "8Gps" :
792 mcp->mb[5] == 2 ? "4Gps" :
1f4c7c38 793 "unknown");
92d4408e
SC		 794 }
795 }
1c7c6357 796 }
1f4c7c38
JC		 797 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
798 "Done.\n");
1c7c6357 799 }
1da177e4
LT		 800
801 return rval;
802}
803
b0d6cabd
HM		 804/*
805 * qla_get_exlogin_status
806 * Get extended login status
807 * uses the memory offload control/status Mailbox
808 *
809 * Input:
810 * ha: adapter state pointer.
811 * fwopt: firmware options
812 *
813 * Returns:
814 * qla2x00 local function status
815 *
816 * Context:
817 * Kernel context.
818 */
819#define FETCH_XLOGINS_STAT 0x8
820int
821qla_get_exlogin_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
822 uint16_t *ex_logins_cnt)
823{
824 int rval;
825 mbx_cmd_t mc;
826 mbx_cmd_t *mcp = &mc;
827
828 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118f,
829 "Entered %s\n", __func__);
830
831 memset(mcp->mb, 0 , sizeof(mcp->mb));
832 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
833 mcp->mb[1] = FETCH_XLOGINS_STAT;
834 mcp->out_mb = MBX_1|MBX_0;
835 mcp->in_mb = MBX_10|MBX_4|MBX_0;
836 mcp->tov = MBX_TOV_SECONDS;
837 mcp->flags = 0;
838
839 rval = qla2x00_mailbox_command(vha, mcp);
840 if (rval != QLA_SUCCESS) {
841 ql_dbg(ql_dbg_mbx, vha, 0x1115, "Failed=%x.\n", rval);
842 } else {
843 *buf_sz = mcp->mb[4];
844 *ex_logins_cnt = mcp->mb[10];
845
846 ql_log(ql_log_info, vha, 0x1190,
847 "buffer size 0x%x, exchange login count=%d\n",
848 mcp->mb[4], mcp->mb[10]);
849
850 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1116,
851 "Done %s.\n", __func__);
852 }
853
854 return rval;
855}
856
857/*
858 * qla_set_exlogin_mem_cfg
859 * set extended login memory configuration
860 * Mbx needs to be issues before init_cb is set
861 *
862 * Input:
863 * ha: adapter state pointer.
864 * buffer: buffer pointer
865 * phys_addr: physical address of buffer
866 * size: size of buffer
867 * TARGET_QUEUE_LOCK must be released
868 * ADAPTER_STATE_LOCK must be release
869 *
870 * Returns:
871 * qla2x00 local funxtion status code.
872 *
873 * Context:
874 * Kernel context.
875 */
876#define CONFIG_XLOGINS_MEM 0x3
877int
878qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr)
879{
880 int rval;
881 mbx_cmd_t mc;
882 mbx_cmd_t *mcp = &mc;
883 struct qla_hw_data *ha = vha->hw;
b0d6cabd
HM		 884
885 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111a,
886 "Entered %s.\n", __func__);
887
888 memset(mcp->mb, 0 , sizeof(mcp->mb));
889 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
890 mcp->mb[1] = CONFIG_XLOGINS_MEM;
891 mcp->mb[2] = MSW(phys_addr);
892 mcp->mb[3] = LSW(phys_addr);
893 mcp->mb[6] = MSW(MSD(phys_addr));
894 mcp->mb[7] = LSW(MSD(phys_addr));
895 mcp->mb[8] = MSW(ha->exlogin_size);
896 mcp->mb[9] = LSW(ha->exlogin_size);
897 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
898 mcp->in_mb = MBX_11|MBX_0;
899 mcp->tov = MBX_TOV_SECONDS;
900 mcp->flags = 0;
901 rval = qla2x00_mailbox_command(vha, mcp);
902 if (rval != QLA_SUCCESS) {
903 /*EMPTY*/
904 ql_dbg(ql_dbg_mbx, vha, 0x111b, "Failed=%x.\n", rval);
905 } else {
b0d6cabd
HM		 906 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
907 "Done %s.\n", __func__);
908 }
909
910 return rval;
911}
912
2f56a7f1
HM		 913/*
914 * qla_get_exchoffld_status
915 * Get exchange offload status
916 * uses the memory offload control/status Mailbox
917 *
918 * Input:
919 * ha: adapter state pointer.
920 * fwopt: firmware options
921 *
922 * Returns:
923 * qla2x00 local function status
924 *
925 * Context:
926 * Kernel context.
927 */
928#define FETCH_XCHOFFLD_STAT 0x2
929int
930qla_get_exchoffld_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
931 uint16_t *ex_logins_cnt)
932{
933 int rval;
934 mbx_cmd_t mc;
935 mbx_cmd_t *mcp = &mc;
936
937 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1019,
938 "Entered %s\n", __func__);
939
940 memset(mcp->mb, 0 , sizeof(mcp->mb));
941 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
942 mcp->mb[1] = FETCH_XCHOFFLD_STAT;
943 mcp->out_mb = MBX_1|MBX_0;
944 mcp->in_mb = MBX_10|MBX_4|MBX_0;
945 mcp->tov = MBX_TOV_SECONDS;
946 mcp->flags = 0;
947
948 rval = qla2x00_mailbox_command(vha, mcp);
949 if (rval != QLA_SUCCESS) {
950 ql_dbg(ql_dbg_mbx, vha, 0x1155, "Failed=%x.\n", rval);
951 } else {
952 *buf_sz = mcp->mb[4];
953 *ex_logins_cnt = mcp->mb[10];
954
955 ql_log(ql_log_info, vha, 0x118e,
956 "buffer size 0x%x, exchange offload count=%d\n",
957 mcp->mb[4], mcp->mb[10]);
958
959 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1156,
960 "Done %s.\n", __func__);
961 }
962
963 return rval;
964}
965
966/*
967 * qla_set_exchoffld_mem_cfg
968 * Set exchange offload memory configuration
969 * Mbx needs to be issues before init_cb is set
970 *
971 * Input:
972 * ha: adapter state pointer.
973 * buffer: buffer pointer
974 * phys_addr: physical address of buffer
975 * size: size of buffer
976 * TARGET_QUEUE_LOCK must be released
977 * ADAPTER_STATE_LOCK must be release
978 *
979 * Returns:
980 * qla2x00 local funxtion status code.
981 *
982 * Context:
983 * Kernel context.
984 */
985#define CONFIG_XCHOFFLD_MEM 0x3
986int
99e1b683 987qla_set_exchoffld_mem_cfg(scsi_qla_host_t *vha)
2f56a7f1
HM		 988{
989 int rval;
990 mbx_cmd_t mc;
991 mbx_cmd_t *mcp = &mc;
992 struct qla_hw_data *ha = vha->hw;
993
994 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1157,
995 "Entered %s.\n", __func__);
996
997 memset(mcp->mb, 0 , sizeof(mcp->mb));
998 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
999 mcp->mb[1] = CONFIG_XCHOFFLD_MEM;
99e1b683
QT		 1000 mcp->mb[2] = MSW(ha->exchoffld_buf_dma);
1001 mcp->mb[3] = LSW(ha->exchoffld_buf_dma);
1002 mcp->mb[6] = MSW(MSD(ha->exchoffld_buf_dma));
1003 mcp->mb[7] = LSW(MSD(ha->exchoffld_buf_dma));
1004 mcp->mb[8] = MSW(ha->exchoffld_size);
1005 mcp->mb[9] = LSW(ha->exchoffld_size);
2f56a7f1
HM		 1006 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1007 mcp->in_mb = MBX_11|MBX_0;
1008 mcp->tov = MBX_TOV_SECONDS;
1009 mcp->flags = 0;
1010 rval = qla2x00_mailbox_command(vha, mcp);
1011 if (rval != QLA_SUCCESS) {
1012 /*EMPTY*/
1013 ql_dbg(ql_dbg_mbx, vha, 0x1158, "Failed=%x.\n", rval);
1014 } else {
1015 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192,
1016 "Done %s.\n", __func__);
1017 }
1018
1019 return rval;
1020}
1021
1da177e4
LT		 1022/*
1023 * qla2x00_get_fw_version
1024 * Get firmware version.
1025 *
1026 * Input:
1027 * ha: adapter state pointer.
1028 * major: pointer for major number.
1029 * minor: pointer for minor number.
1030 * subminor: pointer for subminor number.
1031 *
1032 * Returns:
1033 * qla2x00 local function return status code.
1034 *
1035 * Context:
1036 * Kernel context.
1037 */
ca9e9c3e 1038int
6246b8a1 1039qla2x00_get_fw_version(scsi_qla_host_t *vha)
1da177e4
LT		 1040{
1041 int rval;
1042 mbx_cmd_t mc;
1043 mbx_cmd_t *mcp = &mc;
6246b8a1 1044 struct qla_hw_data *ha = vha->hw;
1da177e4 1045
5f28d2d7
SK		 1046 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
1047 "Entered %s.\n", __func__);
1da177e4
LT		 1048
1049 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
1050 mcp->out_mb = MBX_0;
1051 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
7ec0effd 1052 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
55a96158 1053 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
fb0effee 1054 if (IS_FWI2_CAPABLE(ha))
6246b8a1 1055 mcp->in_mb |= MBX_17|MBX_16|MBX_15;
f73cb695 1056 if (IS_QLA27XX(ha))
ad1ef177
JC		 1057 mcp->in_mb |=
1058 MBX_25|MBX_24|MBX_23|MBX_22|MBX_21|MBX_20|MBX_19|MBX_18|
1059 MBX_14|MBX_13|MBX_11|MBX_10|MBX_9|MBX_8;
03aa868c 1060
1da177e4 1061 mcp->flags = 0;
b93480e3 1062 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 1063 rval = qla2x00_mailbox_command(vha, mcp);
ca9e9c3e
AV		 1064 if (rval != QLA_SUCCESS)
1065 goto failed;
1da177e4
LT		 1066
1067 /* Return mailbox data. */
6246b8a1
GM		 1068 ha->fw_major_version = mcp->mb[1];
1069 ha->fw_minor_version = mcp->mb[2];
1070 ha->fw_subminor_version = mcp->mb[3];
1071 ha->fw_attributes = mcp->mb[6];
7b867cf7 1072 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
6246b8a1 1073 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
1da177e4 1074 else
6246b8a1 1075 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
03aa868c 1076
7ec0effd 1077 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
6246b8a1
GM		 1078 ha->mpi_version[0] = mcp->mb[10] & 0xff;
1079 ha->mpi_version[1] = mcp->mb[11] >> 8;
1080 ha->mpi_version[2] = mcp->mb[11] & 0xff;
1081 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
1082 ha->phy_version[0] = mcp->mb[8] & 0xff;
1083 ha->phy_version[1] = mcp->mb[9] >> 8;
1084 ha->phy_version[2] = mcp->mb[9] & 0xff;
1085 }
03aa868c 1086
81178772
SK		 1087 if (IS_FWI2_CAPABLE(ha)) {
1088 ha->fw_attributes_h = mcp->mb[15];
1089 ha->fw_attributes_ext[0] = mcp->mb[16];
1090 ha->fw_attributes_ext[1] = mcp->mb[17];
1091 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
1092 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
1093 __func__, mcp->mb[15], mcp->mb[6]);
1094 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
1095 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
1096 __func__, mcp->mb[17], mcp->mb[16]);
2f56a7f1 1097
b0d6cabd
HM		 1098 if (ha->fw_attributes_h & 0x4)
1099 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118d,
1100 "%s: Firmware supports Extended Login 0x%x\n",
1101 __func__, ha->fw_attributes_h);
2f56a7f1
HM		 1102
1103 if (ha->fw_attributes_h & 0x8)
1104 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1191,
1105 "%s: Firmware supports Exchange Offload 0x%x\n",
1106 __func__, ha->fw_attributes_h);
e84067d7 1107
deeae7a6
DG		 1108 /*
1109 * FW supports nvme and driver load parameter requested nvme.
1110 * BIT 26 of fw_attributes indicates NVMe support.
1111 */
1cbc0efc 1112 if ((ha->fw_attributes_h & 0x400) && ql2xnvmeenable) {
e84067d7 1113 vha->flags.nvme_enabled = 1;
1cbc0efc
DT		 1114 ql_log(ql_log_info, vha, 0xd302,
1115 "%s: FC-NVMe is Enabled (0x%x)\n",
1116 __func__, ha->fw_attributes_h);
1117 }
3a03eb79 1118 }
03aa868c 1119
f73cb695 1120 if (IS_QLA27XX(ha)) {
03aa868c
SC		 1121 ha->mpi_version[0] = mcp->mb[10] & 0xff;
1122 ha->mpi_version[1] = mcp->mb[11] >> 8;
1123 ha->mpi_version[2] = mcp->mb[11] & 0xff;
1124 ha->pep_version[0] = mcp->mb[13] & 0xff;
1125 ha->pep_version[1] = mcp->mb[14] >> 8;
1126 ha->pep_version[2] = mcp->mb[14] & 0xff;
f73cb695
CD		 1127 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18];
1128 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20];
ad1ef177
JC		 1129 ha->fw_ddr_ram_start = (mcp->mb[23] << 16) | mcp->mb[22];
1130 ha->fw_ddr_ram_end = (mcp->mb[25] << 16) | mcp->mb[24];
f73cb695 1131 }
6246b8a1 1132
ca9e9c3e 1133failed:
1da177e4
LT		 1134 if (rval != QLA_SUCCESS) {
1135 /*EMPTY*/
7c3df132 1136 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
1da177e4
LT		 1137 } else {
1138 /*EMPTY*/
5f28d2d7
SK		 1139 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
1140 "Done %s.\n", __func__);
1da177e4 1141 }
ca9e9c3e 1142 return rval;
1da177e4
LT		 1143}
1144
1145/*
1146 * qla2x00_get_fw_options
1147 * Set firmware options.
1148 *
1149 * Input:
1150 * ha = adapter block pointer.
1151 * fwopt = pointer for firmware options.
1152 *
1153 * Returns:
1154 * qla2x00 local function return status code.
1155 *
1156 * Context:
1157 * Kernel context.
1158 */
1159int
7b867cf7 1160qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 1161{
1162 int rval;
1163 mbx_cmd_t mc;
1164 mbx_cmd_t *mcp = &mc;
1165
5f28d2d7
SK		 1166 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
1167 "Entered %s.\n", __func__);
1da177e4
LT		 1168
1169 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
1170 mcp->out_mb = MBX_0;
1171 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1172 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1173 mcp->flags = 0;
7b867cf7 1174 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1175
1176 if (rval != QLA_SUCCESS) {
1177 /*EMPTY*/
7c3df132 1178 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
1da177e4 1179 } else {
1c7c6357 1180 fwopts[0] = mcp->mb[0];
1da177e4
LT		 1181 fwopts[1] = mcp->mb[1];
1182 fwopts[2] = mcp->mb[2];
1183 fwopts[3] = mcp->mb[3];
1184
5f28d2d7
SK		 1185 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
1186 "Done %s.\n", __func__);
1da177e4
LT		 1187 }
1188
1189 return rval;
1190}
1191
1192
1193/*
1194 * qla2x00_set_fw_options
1195 * Set firmware options.
1196 *
1197 * Input:
1198 * ha = adapter block pointer.
1199 * fwopt = pointer for firmware options.
1200 *
1201 * Returns:
1202 * qla2x00 local function return status code.
1203 *
1204 * Context:
1205 * Kernel context.
1206 */
1207int
7b867cf7 1208qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 1209{
1210 int rval;
1211 mbx_cmd_t mc;
1212 mbx_cmd_t *mcp = &mc;
1213
5f28d2d7
SK		 1214 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
1215 "Entered %s.\n", __func__);
1da177e4
LT		 1216
1217 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
1218 mcp->mb[1] = fwopts[1];
1219 mcp->mb[2] = fwopts[2];
1220 mcp->mb[3] = fwopts[3];
1c7c6357 1221 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 1222 mcp->in_mb = MBX_0;
7b867cf7 1223 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357 1224 mcp->in_mb |= MBX_1;
2da52737
QT		 1225 mcp->mb[10] = fwopts[10];
1226 mcp->out_mb |= MBX_10;
1c7c6357
AV		 1227 } else {
1228 mcp->mb[10] = fwopts[10];
1229 mcp->mb[11] = fwopts[11];
1230 mcp->mb[12] = 0; /* Undocumented, but used */
1231 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
1232 }
b93480e3 1233 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1234 mcp->flags = 0;
7b867cf7 1235 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1236
1c7c6357
AV		 1237 fwopts[0] = mcp->mb[0];
1238
1da177e4
LT		 1239 if (rval != QLA_SUCCESS) {
1240 /*EMPTY*/
7c3df132
SK		 1241 ql_dbg(ql_dbg_mbx, vha, 0x1030,
1242 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 1243 } else {
1244 /*EMPTY*/
5f28d2d7
SK		 1245 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
1246 "Done %s.\n", __func__);
1da177e4
LT		 1247 }
1248
1249 return rval;
1250}
1251
1252/*
1253 * qla2x00_mbx_reg_test
1254 * Mailbox register wrap test.
1255 *
1256 * Input:
1257 * ha = adapter block pointer.
1258 * TARGET_QUEUE_LOCK must be released.
1259 * ADAPTER_STATE_LOCK must be released.
1260 *
1261 * Returns:
1262 * qla2x00 local function return status code.
1263 *
1264 * Context:
1265 * Kernel context.
1266 */
1267int
7b867cf7 1268qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
1da177e4
LT		 1269{
1270 int rval;
1271 mbx_cmd_t mc;
1272 mbx_cmd_t *mcp = &mc;
1273
5f28d2d7
SK		 1274 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
1275 "Entered %s.\n", __func__);
1da177e4
LT		 1276
1277 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
1278 mcp->mb[1] = 0xAAAA;
1279 mcp->mb[2] = 0x5555;
1280 mcp->mb[3] = 0xAA55;
1281 mcp->mb[4] = 0x55AA;
1282 mcp->mb[5] = 0xA5A5;
1283 mcp->mb[6] = 0x5A5A;
1284 mcp->mb[7] = 0x2525;
1285 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1286 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1287 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1288 mcp->flags = 0;
7b867cf7 1289 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1290
1291 if (rval == QLA_SUCCESS) {
1292 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
1293 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
1294 rval = QLA_FUNCTION_FAILED;
1295 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
1296 mcp->mb[7] != 0x2525)
1297 rval = QLA_FUNCTION_FAILED;
1298 }
1299
1300 if (rval != QLA_SUCCESS) {
1301 /*EMPTY*/
7c3df132 1302 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
1da177e4
LT		 1303 } else {
1304 /*EMPTY*/
5f28d2d7
SK		 1305 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
1306 "Done %s.\n", __func__);
1da177e4
LT		 1307 }
1308
1309 return rval;
1310}
1311
1312/*
1313 * qla2x00_verify_checksum
1314 * Verify firmware checksum.
1315 *
1316 * Input:
1317 * ha = adapter block pointer.
1318 * TARGET_QUEUE_LOCK must be released.
1319 * ADAPTER_STATE_LOCK must be released.
1320 *
1321 * Returns:
1322 * qla2x00 local function return status code.
1323 *
1324 * Context:
1325 * Kernel context.
1326 */
1327int
7b867cf7 1328qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 1329{
1330 int rval;
1331 mbx_cmd_t mc;
1332 mbx_cmd_t *mcp = &mc;
1333
5f28d2d7
SK		 1334 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
1335 "Entered %s.\n", __func__);
1da177e4
LT		 1336
1337 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
1c7c6357
AV		 1338 mcp->out_mb = MBX_0;
1339 mcp->in_mb = MBX_0;
7b867cf7 1340 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 1341 mcp->mb[1] = MSW(risc_addr);
1342 mcp->mb[2] = LSW(risc_addr);
1343 mcp->out_mb |= MBX_2|MBX_1;
1344 mcp->in_mb |= MBX_2|MBX_1;
1345 } else {
1346 mcp->mb[1] = LSW(risc_addr);
1347 mcp->out_mb |= MBX_1;
1348 mcp->in_mb |= MBX_1;
1349 }
1350
b93480e3 1351 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1352 mcp->flags = 0;
7b867cf7 1353 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1354
1355 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1356 ql_dbg(ql_dbg_mbx, vha, 0x1036,
1357 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
1358 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
1da177e4 1359 } else {
5f28d2d7
SK		 1360 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
1361 "Done %s.\n", __func__);
1da177e4
LT		 1362 }
1363
1364 return rval;
1365}
1366
1367/*
1368 * qla2x00_issue_iocb
1369 * Issue IOCB using mailbox command
1370 *
1371 * Input:
1372 * ha = adapter state pointer.
1373 * buffer = buffer pointer.
1374 * phys_addr = physical address of buffer.
1375 * size = size of buffer.
1376 * TARGET_QUEUE_LOCK must be released.
1377 * ADAPTER_STATE_LOCK must be released.
1378 *
1379 * Returns:
1380 * qla2x00 local function return status code.
1381 *
1382 * Context:
1383 * Kernel context.
1384 */
6e98016c 1385int
7b867cf7 1386qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
4d4df193 1387 dma_addr_t phys_addr, size_t size, uint32_t tov)
1da177e4
LT		 1388{
1389 int rval;
1390 mbx_cmd_t mc;
1391 mbx_cmd_t *mcp = &mc;
1392
5f28d2d7
SK		 1393 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
1394 "Entered %s.\n", __func__);
7c3df132 1395
1da177e4
LT		 1396 mcp->mb[0] = MBC_IOCB_COMMAND_A64;
1397 mcp->mb[1] = 0;
1398 mcp->mb[2] = MSW(phys_addr);
1399 mcp->mb[3] = LSW(phys_addr);
1400 mcp->mb[6] = MSW(MSD(phys_addr));
1401 mcp->mb[7] = LSW(MSD(phys_addr));
1402 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1403 mcp->in_mb = MBX_2|MBX_0;
4d4df193 1404 mcp->tov = tov;
1da177e4 1405 mcp->flags = 0;
7b867cf7 1406 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1407
1408 if (rval != QLA_SUCCESS) {
1409 /*EMPTY*/
7c3df132 1410 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
1da177e4 1411 } else {
8c958a99
AV		 1412 sts_entry_t *sts_entry = (sts_entry_t *) buffer;
1413
1414 /* Mask reserved bits. */
1415 sts_entry->entry_status &=
7b867cf7 1416 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
5f28d2d7
SK		 1417 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
1418 "Done %s.\n", __func__);
1da177e4
LT		 1419 }
1420
1421 return rval;
1422}
1423
4d4df193 1424int
7b867cf7 1425qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
4d4df193
HK		 1426 size_t size)
1427{
7b867cf7 1428 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
4d4df193
HK		 1429 MBX_TOV_SECONDS);
1430}
1431
1da177e4
LT		 1432/*
1433 * qla2x00_abort_command
1434 * Abort command aborts a specified IOCB.
1435 *
1436 * Input:
1437 * ha = adapter block pointer.
1438 * sp = SB structure pointer.
1439 *
1440 * Returns:
1441 * qla2x00 local function return status code.
1442 *
1443 * Context:
1444 * Kernel context.
1445 */
1446int
2afa19a9 1447qla2x00_abort_command(srb_t *sp)
1da177e4
LT		 1448{
1449 unsigned long flags = 0;
1da177e4 1450 int rval;
73208dfd 1451 uint32_t handle = 0;
1da177e4
LT		 1452 mbx_cmd_t mc;
1453 mbx_cmd_t *mcp = &mc;
2afa19a9
AC		 1454 fc_port_t *fcport = sp->fcport;
1455 scsi_qla_host_t *vha = fcport->vha;
7b867cf7 1456 struct qla_hw_data *ha = vha->hw;
d7459527 1457 struct req_que *req;
9ba56b95 1458 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1da177e4 1459
5f28d2d7
SK		 1460 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
1461 "Entered %s.\n", __func__);
1da177e4 1462
d7459527
MH		 1463 if (vha->flags.qpairs_available && sp->qpair)
1464 req = sp->qpair->req;
1465 else
1466 req = vha->req;
1467
c9c5ced9 1468 spin_lock_irqsave(&ha->hardware_lock, flags);
8d93f550 1469 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 1470 if (req->outstanding_cmds[handle] == sp)
1da177e4
LT		 1471 break;
1472 }
c9c5ced9 1473 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1474
8d93f550 1475 if (handle == req->num_outstanding_cmds) {
1da177e4
LT		 1476 /* command not found */
1477 return QLA_FUNCTION_FAILED;
1478 }
1479
1480 mcp->mb[0] = MBC_ABORT_COMMAND;
1481 if (HAS_EXTENDED_IDS(ha))
1482 mcp->mb[1] = fcport->loop_id;
1483 else
1484 mcp->mb[1] = fcport->loop_id << 8;
1485 mcp->mb[2] = (uint16_t)handle;
1486 mcp->mb[3] = (uint16_t)(handle >> 16);
9ba56b95 1487 mcp->mb[6] = (uint16_t)cmd->device->lun;
1da177e4
LT		 1488 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1489 mcp->in_mb = MBX_0;
b93480e3 1490 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1491 mcp->flags = 0;
7b867cf7 1492 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1493
1494 if (rval != QLA_SUCCESS) {
7c3df132 1495 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
1da177e4 1496 } else {
5f28d2d7
SK		 1497 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
1498 "Done %s.\n", __func__);
1da177e4
LT		 1499 }
1500
1501 return rval;
1502}
1503
1da177e4 1504int
9cb78c16 1505qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag)
1da177e4 1506{
523ec773 1507 int rval, rval2;
1da177e4
LT		 1508 mbx_cmd_t mc;
1509 mbx_cmd_t *mcp = &mc;
7b867cf7 1510 scsi_qla_host_t *vha;
73208dfd
AC		 1511 struct req_que *req;
1512 struct rsp_que *rsp;
1da177e4 1513
7b867cf7 1514 vha = fcport->vha;
7c3df132 1515
5f28d2d7
SK		 1516 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
1517 "Entered %s.\n", __func__);
7c3df132 1518
7e2b895b
GM		 1519 req = vha->hw->req_q_map[0];
1520 rsp = req->rsp;
1da177e4 1521 mcp->mb[0] = MBC_ABORT_TARGET;
523ec773 1522 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
7b867cf7 1523 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 1524 mcp->mb[1] = fcport->loop_id;
1525 mcp->mb[10] = 0;
1526 mcp->out_mb |= MBX_10;
1527 } else {
1528 mcp->mb[1] = fcport->loop_id << 8;
1529 }
7b867cf7
AC		 1530 mcp->mb[2] = vha->hw->loop_reset_delay;
1531 mcp->mb[9] = vha->vp_idx;
1da177e4
LT		 1532
1533 mcp->in_mb = MBX_0;
b93480e3 1534 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1535 mcp->flags = 0;
7b867cf7 1536 rval = qla2x00_mailbox_command(vha, mcp);
523ec773 1537 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 1538 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
1539 "Failed=%x.\n", rval);
523ec773
AV		 1540 }
1541
1542 /* Issue marker IOCB. */
73208dfd
AC		 1543 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
1544 MK_SYNC_ID);
523ec773 1545 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 1546 ql_dbg(ql_dbg_mbx, vha, 0x1040,
1547 "Failed to issue marker IOCB (%x).\n", rval2);
523ec773 1548 } else {
5f28d2d7
SK		 1549 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
1550 "Done %s.\n", __func__);
523ec773
AV		 1551 }
1552
1553 return rval;
1554}
1555
1556int
9cb78c16 1557qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
523ec773
AV		 1558{
1559 int rval, rval2;
1560 mbx_cmd_t mc;
1561 mbx_cmd_t *mcp = &mc;
7b867cf7 1562 scsi_qla_host_t *vha;
73208dfd
AC		 1563 struct req_que *req;
1564 struct rsp_que *rsp;
523ec773 1565
7b867cf7 1566 vha = fcport->vha;
7c3df132 1567
5f28d2d7
SK		 1568 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
1569 "Entered %s.\n", __func__);
7c3df132 1570
7e2b895b
GM		 1571 req = vha->hw->req_q_map[0];
1572 rsp = req->rsp;
523ec773
AV		 1573 mcp->mb[0] = MBC_LUN_RESET;
1574 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 1575 if (HAS_EXTENDED_IDS(vha->hw))
523ec773
AV		 1576 mcp->mb[1] = fcport->loop_id;
1577 else
1578 mcp->mb[1] = fcport->loop_id << 8;
9cb78c16 1579 mcp->mb[2] = (u32)l;
523ec773 1580 mcp->mb[3] = 0;
7b867cf7 1581 mcp->mb[9] = vha->vp_idx;
1da177e4 1582
523ec773 1583 mcp->in_mb = MBX_0;
b93480e3 1584 mcp->tov = MBX_TOV_SECONDS;
523ec773 1585 mcp->flags = 0;
7b867cf7 1586 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1587 if (rval != QLA_SUCCESS) {
7c3df132 1588 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
523ec773
AV		 1589 }
1590
1591 /* Issue marker IOCB. */
73208dfd
AC		 1592 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
1593 MK_SYNC_ID_LUN);
523ec773 1594 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 1595 ql_dbg(ql_dbg_mbx, vha, 0x1044,
1596 "Failed to issue marker IOCB (%x).\n", rval2);
1da177e4 1597 } else {
5f28d2d7
SK		 1598 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
1599 "Done %s.\n", __func__);
1da177e4
LT		 1600 }
1601
1602 return rval;
1603}
1da177e4 1604
1da177e4
LT		 1605/*
1606 * qla2x00_get_adapter_id
1607 * Get adapter ID and topology.
1608 *
1609 * Input:
1610 * ha = adapter block pointer.
1611 * id = pointer for loop ID.
1612 * al_pa = pointer for AL_PA.
1613 * area = pointer for area.
1614 * domain = pointer for domain.
1615 * top = pointer for topology.
1616 * TARGET_QUEUE_LOCK must be released.
1617 * ADAPTER_STATE_LOCK must be released.
1618 *
1619 * Returns:
1620 * qla2x00 local function return status code.
1621 *
1622 * Context:
1623 * Kernel context.
1624 */
1625int
7b867cf7 1626qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
2c3dfe3f 1627 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
1da177e4
LT		 1628{
1629 int rval;
1630 mbx_cmd_t mc;
1631 mbx_cmd_t *mcp = &mc;
1632
5f28d2d7
SK		 1633 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
1634 "Entered %s.\n", __func__);
1da177e4
LT		 1635
1636 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
7b867cf7 1637 mcp->mb[9] = vha->vp_idx;
eb66dc60 1638 mcp->out_mb = MBX_9|MBX_0;
2c3dfe3f 1639 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6246b8a1 1640 if (IS_CNA_CAPABLE(vha->hw))
bad7001c 1641 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
7c9c4766
JC		 1642 if (IS_FWI2_CAPABLE(vha->hw))
1643 mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16;
969a6199
SC		 1644 if (IS_QLA27XX(vha->hw))
1645 mcp->in_mb |= MBX_15;
b93480e3 1646 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1647 mcp->flags = 0;
7b867cf7 1648 rval = qla2x00_mailbox_command(vha, mcp);
33135aa2
RA		 1649 if (mcp->mb[0] == MBS_COMMAND_ERROR)
1650 rval = QLA_COMMAND_ERROR;
42e421b1
AV		 1651 else if (mcp->mb[0] == MBS_INVALID_COMMAND)
1652 rval = QLA_INVALID_COMMAND;
1da177e4
LT		 1653
1654 /* Return data. */
1655 *id = mcp->mb[1];
1656 *al_pa = LSB(mcp->mb[2]);
1657 *area = MSB(mcp->mb[2]);
1658 *domain = LSB(mcp->mb[3]);
1659 *top = mcp->mb[6];
2c3dfe3f 1660 *sw_cap = mcp->mb[7];
1da177e4
LT		 1661
1662 if (rval != QLA_SUCCESS) {
1663 /*EMPTY*/
7c3df132 1664 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
1da177e4 1665 } else {
5f28d2d7
SK		 1666 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
1667 "Done %s.\n", __func__);
bad7001c 1668
6246b8a1 1669 if (IS_CNA_CAPABLE(vha->hw)) {
bad7001c
AV		 1670 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1671 vha->fcoe_fcf_idx = mcp->mb[10];
1672 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
1673 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
1674 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
1675 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
1676 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
1677 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
1678 }
7c9c4766 1679 /* If FA-WWN supported */
d6b9b42b
SK		 1680 if (IS_FAWWN_CAPABLE(vha->hw)) {
1681 if (mcp->mb[7] & BIT_14) {
1682 vha->port_name[0] = MSB(mcp->mb[16]);
1683 vha->port_name[1] = LSB(mcp->mb[16]);
1684 vha->port_name[2] = MSB(mcp->mb[17]);
1685 vha->port_name[3] = LSB(mcp->mb[17]);
1686 vha->port_name[4] = MSB(mcp->mb[18]);
1687 vha->port_name[5] = LSB(mcp->mb[18]);
1688 vha->port_name[6] = MSB(mcp->mb[19]);
1689 vha->port_name[7] = LSB(mcp->mb[19]);
1690 fc_host_port_name(vha->host) =
1691 wwn_to_u64(vha->port_name);
1692 ql_dbg(ql_dbg_mbx, vha, 0x10ca,
1693 "FA-WWN acquired %016llx\n",
1694 wwn_to_u64(vha->port_name));
1695 }
7c9c4766 1696 }
969a6199
SC		 1697
1698 if (IS_QLA27XX(vha->hw))
1699 vha->bbcr = mcp->mb[15];
1da177e4
LT		 1700 }
1701
1702 return rval;
1703}
1704
1705/*
1706 * qla2x00_get_retry_cnt
1707 * Get current firmware login retry count and delay.
1708 *
1709 * Input:
1710 * ha = adapter block pointer.
1711 * retry_cnt = pointer to login retry count.
1712 * tov = pointer to login timeout value.
1713 *
1714 * Returns:
1715 * qla2x00 local function return status code.
1716 *
1717 * Context:
1718 * Kernel context.
1719 */
1720int
7b867cf7 1721qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
1da177e4
LT		 1722 uint16_t *r_a_tov)
1723{
1724 int rval;
1725 uint16_t ratov;
1726 mbx_cmd_t mc;
1727 mbx_cmd_t *mcp = &mc;
1728
5f28d2d7
SK		 1729 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
1730 "Entered %s.\n", __func__);
1da177e4
LT		 1731
1732 mcp->mb[0] = MBC_GET_RETRY_COUNT;
1733 mcp->out_mb = MBX_0;
1734 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1735 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1736 mcp->flags = 0;
7b867cf7 1737 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1738
1739 if (rval != QLA_SUCCESS) {
1740 /*EMPTY*/
7c3df132
SK		 1741 ql_dbg(ql_dbg_mbx, vha, 0x104a,
1742 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4
LT		 1743 } else {
1744 /* Convert returned data and check our values. */
1745 *r_a_tov = mcp->mb[3] / 2;
1746 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
1747 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
1748 /* Update to the larger values */
1749 *retry_cnt = (uint8_t)mcp->mb[1];
1750 *tov = ratov;
1751 }
1752
5f28d2d7 1753 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
7c3df132 1754 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
1da177e4
LT		 1755 }
1756
1757 return rval;
1758}
1759
1760/*
1761 * qla2x00_init_firmware
1762 * Initialize adapter firmware.
1763 *
1764 * Input:
1765 * ha = adapter block pointer.
1766 * dptr = Initialization control block pointer.
1767 * size = size of initialization control block.
1768 * TARGET_QUEUE_LOCK must be released.
1769 * ADAPTER_STATE_LOCK must be released.
1770 *
1771 * Returns:
1772 * qla2x00 local function return status code.
1773 *
1774 * Context:
1775 * Kernel context.
1776 */
1777int
7b867cf7 1778qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1da177e4
LT		 1779{
1780 int rval;
1781 mbx_cmd_t mc;
1782 mbx_cmd_t *mcp = &mc;
7b867cf7 1783 struct qla_hw_data *ha = vha->hw;
1da177e4 1784
5f28d2d7
SK		 1785 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
1786 "Entered %s.\n", __func__);
1da177e4 1787
7ec0effd 1788 if (IS_P3P_TYPE(ha) && ql2xdbwr)
8dfa4b5a 1789 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr,
a9083016
GM		 1790 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1791
e6e074f1 1792 if (ha->flags.npiv_supported)
2c3dfe3f
SJ		 1793 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
1794 else
1795 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1796
b64b0e8f 1797 mcp->mb[1] = 0;
1da177e4
LT		 1798 mcp->mb[2] = MSW(ha->init_cb_dma);
1799 mcp->mb[3] = LSW(ha->init_cb_dma);
1da177e4
LT		 1800 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1801 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
b64b0e8f 1802 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4ef21bd4 1803 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
b64b0e8f
AV		 1804 mcp->mb[1] = BIT_0;
1805 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1806 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
1807 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
1808 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
1809 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1810 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1811 }
6246b8a1
GM		 1812 /* 1 and 2 should normally be captured. */
1813 mcp->in_mb = MBX_2|MBX_1|MBX_0;
f73cb695 1814 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1
GM		 1815 /* mb3 is additional info about the installed SFP. */
1816 mcp->in_mb |= MBX_3;
1da177e4
LT		 1817 mcp->buf_size = size;
1818 mcp->flags = MBX_DMA_OUT;
b93480e3 1819 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 1820 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1821
1822 if (rval != QLA_SUCCESS) {
1823 /*EMPTY*/
7c3df132 1824 ql_dbg(ql_dbg_mbx, vha, 0x104d,
6246b8a1
GM		 1825 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
1826 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
1da177e4 1827 } else {
92d4408e
SC		 1828 if (IS_QLA27XX(ha)) {
1829 if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
1830 ql_dbg(ql_dbg_mbx, vha, 0x119d,
1831 "Invalid SFP/Validation Failed\n");
1832 }
5f28d2d7
SK		 1833 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
1834 "Done %s.\n", __func__);
1da177e4
LT		 1835 }
1836
1837 return rval;
1838}
1839
2d70c103 1840
1da177e4
LT		 1841/*
1842 * qla2x00_get_port_database
1843 * Issue normal/enhanced get port database mailbox command
1844 * and copy device name as necessary.
1845 *
1846 * Input:
1847 * ha = adapter state pointer.
1848 * dev = structure pointer.
1849 * opt = enhanced cmd option byte.
1850 *
1851 * Returns:
1852 * qla2x00 local function return status code.
1853 *
1854 * Context:
1855 * Kernel context.
1856 */
1857int
7b867cf7 1858qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
1da177e4
LT		 1859{
1860 int rval;
1861 mbx_cmd_t mc;
1862 mbx_cmd_t *mcp = &mc;
1863 port_database_t *pd;
1c7c6357 1864 struct port_database_24xx *pd24;
1da177e4 1865 dma_addr_t pd_dma;
7b867cf7 1866 struct qla_hw_data *ha = vha->hw;
1da177e4 1867
5f28d2d7
SK		 1868 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
1869 "Entered %s.\n", __func__);
1da177e4 1870
1c7c6357 1871 pd24 = NULL;
08eb7f45 1872 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1da177e4 1873 if (pd == NULL) {
7c3df132
SK		 1874 ql_log(ql_log_warn, vha, 0x1050,
1875 "Failed to allocate port database structure.\n");
edd05de1 1876 fcport->query = 0;
1da177e4
LT		 1877 return QLA_MEMORY_ALLOC_FAILED;
1878 }
1da177e4 1879
1c7c6357 1880 mcp->mb[0] = MBC_GET_PORT_DATABASE;
e428924c 1881 if (opt != 0 && !IS_FWI2_CAPABLE(ha))
1da177e4 1882 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
1da177e4
LT		 1883 mcp->mb[2] = MSW(pd_dma);
1884 mcp->mb[3] = LSW(pd_dma);
1885 mcp->mb[6] = MSW(MSD(pd_dma));
1886 mcp->mb[7] = LSW(MSD(pd_dma));
7b867cf7 1887 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 1888 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1da177e4 1889 mcp->in_mb = MBX_0;
e428924c 1890 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 1891 mcp->mb[1] = fcport->loop_id;
1892 mcp->mb[10] = opt;
1893 mcp->out_mb |= MBX_10|MBX_1;
1894 mcp->in_mb |= MBX_1;
1895 } else if (HAS_EXTENDED_IDS(ha)) {
1896 mcp->mb[1] = fcport->loop_id;
1897 mcp->mb[10] = opt;
1898 mcp->out_mb |= MBX_10|MBX_1;
1899 } else {
1900 mcp->mb[1] = fcport->loop_id << 8 | opt;
1901 mcp->out_mb |= MBX_1;
1902 }
e428924c
AV		 1903 mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
1904 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
1da177e4
LT		 1905 mcp->flags = MBX_DMA_IN;
1906 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 1907 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1908 if (rval != QLA_SUCCESS)
1909 goto gpd_error_out;
1910
e428924c 1911 if (IS_FWI2_CAPABLE(ha)) {
0eba25df 1912 uint64_t zero = 0;
c0c462c8
DG		 1913 u8 current_login_state, last_login_state;
1914
1c7c6357
AV		 1915 pd24 = (struct port_database_24xx *) pd;
1916
1917 /* Check for logged in state. */
c0c462c8
DG		 1918 if (fcport->fc4f_nvme) {
1919 current_login_state = pd24->current_login_state >> 4;
1920 last_login_state = pd24->last_login_state >> 4;
1921 } else {
1922 current_login_state = pd24->current_login_state & 0xf;
1923 last_login_state = pd24->last_login_state & 0xf;
1924 }
1925 fcport->current_login_state = pd24->current_login_state;
1926 fcport->last_login_state = pd24->last_login_state;
1927
1928 /* Check for logged in state. */
1929 if (current_login_state != PDS_PRLI_COMPLETE &&
1930 last_login_state != PDS_PRLI_COMPLETE) {
1931 ql_dbg(ql_dbg_mbx, vha, 0x119a,
1932 "Unable to verify login-state (%x/%x) for loop_id %x.\n",
1933 current_login_state, last_login_state,
1934 fcport->loop_id);
1c7c6357 1935 rval = QLA_FUNCTION_FAILED;
c0c462c8
DG		 1936
1937 if (!fcport->query)
1938 goto gpd_error_out;
1c7c6357 1939 }
1da177e4 1940
0eba25df
AE		 1941 if (fcport->loop_id == FC_NO_LOOP_ID ||
1942 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1943 memcmp(fcport->port_name, pd24->port_name, 8))) {
1944 /* We lost the device mid way. */
1945 rval = QLA_NOT_LOGGED_IN;
1946 goto gpd_error_out;
1947 }
1948
1c7c6357
AV		 1949 /* Names are little-endian. */
1950 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
1951 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
1952
1953 /* Get port_id of device. */
1954 fcport->d_id.b.domain = pd24->port_id[0];
1955 fcport->d_id.b.area = pd24->port_id[1];
1956 fcport->d_id.b.al_pa = pd24->port_id[2];
1957 fcport->d_id.b.rsvd_1 = 0;
1958
1959 /* If not target must be initiator or unknown type. */
1960 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
1961 fcport->port_type = FCT_INITIATOR;
1962 else
1963 fcport->port_type = FCT_TARGET;
2d70c103
NB		 1964
1965 /* Passback COS information. */
1966 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
1967 FC_COS_CLASS2 : FC_COS_CLASS3;
1968
1969 if (pd24->prli_svc_param_word_3[0] & BIT_7)
1970 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
1c7c6357 1971 } else {
0eba25df
AE		 1972 uint64_t zero = 0;
1973
1c7c6357
AV		 1974 /* Check for logged in state. */
1975 if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
1976 pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
7c3df132
SK		 1977 ql_dbg(ql_dbg_mbx, vha, 0x100a,
1978 "Unable to verify login-state (%x/%x) - "
1979 "portid=%02x%02x%02x.\n", pd->master_state,
1980 pd->slave_state, fcport->d_id.b.domain,
1981 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1c7c6357
AV		 1982 rval = QLA_FUNCTION_FAILED;
1983 goto gpd_error_out;
1984 }
1da177e4 1985
0eba25df
AE		 1986 if (fcport->loop_id == FC_NO_LOOP_ID ||
1987 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1988 memcmp(fcport->port_name, pd->port_name, 8))) {
1989 /* We lost the device mid way. */
1990 rval = QLA_NOT_LOGGED_IN;
1991 goto gpd_error_out;
1992 }
1993
1c7c6357
AV		 1994 /* Names are little-endian. */
1995 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
1996 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
1997
1998 /* Get port_id of device. */
1999 fcport->d_id.b.domain = pd->port_id[0];
2000 fcport->d_id.b.area = pd->port_id[3];
2001 fcport->d_id.b.al_pa = pd->port_id[2];
2002 fcport->d_id.b.rsvd_1 = 0;
2003
1c7c6357
AV		 2004 /* If not target must be initiator or unknown type. */
2005 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
2006 fcport->port_type = FCT_INITIATOR;
2007 else
2008 fcport->port_type = FCT_TARGET;
ad3e0eda
AV		 2009
2010 /* Passback COS information. */
2011 fcport->supported_classes = (pd->options & BIT_4) ?
2012 FC_COS_CLASS2: FC_COS_CLASS3;
1c7c6357 2013 }
1da177e4
LT		 2014
2015gpd_error_out:
2016 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
edd05de1 2017 fcport->query = 0;
1da177e4
LT		 2018
2019 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2020 ql_dbg(ql_dbg_mbx, vha, 0x1052,
2021 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
2022 mcp->mb[0], mcp->mb[1]);
1da177e4 2023 } else {
5f28d2d7
SK		 2024 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
2025 "Done %s.\n", __func__);
1da177e4
LT		 2026 }
2027
2028 return rval;
2029}
2030
2031/*
2032 * qla2x00_get_firmware_state
2033 * Get adapter firmware state.
2034 *
2035 * Input:
2036 * ha = adapter block pointer.
2037 * dptr = pointer for firmware state.
2038 * TARGET_QUEUE_LOCK must be released.
2039 * ADAPTER_STATE_LOCK must be released.
2040 *
2041 * Returns:
2042 * qla2x00 local function return status code.
2043 *
2044 * Context:
2045 * Kernel context.
2046 */
2047int
7b867cf7 2048qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
1da177e4
LT		 2049{
2050 int rval;
2051 mbx_cmd_t mc;
2052 mbx_cmd_t *mcp = &mc;
92d4408e 2053 struct qla_hw_data *ha = vha->hw;
1da177e4 2054
5f28d2d7
SK		 2055 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
2056 "Entered %s.\n", __func__);
1da177e4
LT		 2057
2058 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
2059 mcp->out_mb = MBX_0;
9d2683c0 2060 if (IS_FWI2_CAPABLE(vha->hw))
b5a340dd 2061 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
9d2683c0
AV		 2062 else
2063 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2064 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2065 mcp->flags = 0;
7b867cf7 2066 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 2067
4d4df193
HK		 2068 /* Return firmware states. */
2069 states[0] = mcp->mb[1];
9d2683c0
AV		 2070 if (IS_FWI2_CAPABLE(vha->hw)) {
2071 states[1] = mcp->mb[2];
ec891462 2072 states[2] = mcp->mb[3]; /* SFP info */
9d2683c0
AV		 2073 states[3] = mcp->mb[4];
2074 states[4] = mcp->mb[5];
b5a340dd 2075 states[5] = mcp->mb[6]; /* DPORT status */
9d2683c0 2076 }
1da177e4
LT		 2077
2078 if (rval != QLA_SUCCESS) {
2079 /*EMPTY*/
7c3df132 2080 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
1da177e4 2081 } else {
92d4408e
SC		 2082 if (IS_QLA27XX(ha)) {
2083 if (mcp->mb[2] == 6 || mcp->mb[3] == 2)
2084 ql_dbg(ql_dbg_mbx, vha, 0x119e,
2085 "Invalid SFP/Validation Failed\n");
2086 }
5f28d2d7
SK		 2087 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
2088 "Done %s.\n", __func__);
1da177e4
LT		 2089 }
2090
2091 return rval;
2092}
2093
2094/*
2095 * qla2x00_get_port_name
2096 * Issue get port name mailbox command.
2097 * Returned name is in big endian format.
2098 *
2099 * Input:
2100 * ha = adapter block pointer.
2101 * loop_id = loop ID of device.
2102 * name = pointer for name.
2103 * TARGET_QUEUE_LOCK must be released.
2104 * ADAPTER_STATE_LOCK must be released.
2105 *
2106 * Returns:
2107 * qla2x00 local function return status code.
2108 *
2109 * Context:
2110 * Kernel context.
2111 */
2112int
7b867cf7 2113qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
1da177e4
LT		 2114 uint8_t opt)
2115{
2116 int rval;
2117 mbx_cmd_t mc;
2118 mbx_cmd_t *mcp = &mc;
2119
5f28d2d7
SK		 2120 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
2121 "Entered %s.\n", __func__);
1da177e4
LT		 2122
2123 mcp->mb[0] = MBC_GET_PORT_NAME;
7b867cf7 2124 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 2125 mcp->out_mb = MBX_9|MBX_1|MBX_0;
7b867cf7 2126 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 2127 mcp->mb[1] = loop_id;
2128 mcp->mb[10] = opt;
2129 mcp->out_mb |= MBX_10;
2130 } else {
2131 mcp->mb[1] = loop_id << 8 | opt;
2132 }
2133
2134 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 2135 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2136 mcp->flags = 0;
7b867cf7 2137 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2138
2139 if (rval != QLA_SUCCESS) {
2140 /*EMPTY*/
7c3df132 2141 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
1da177e4
LT		 2142 } else {
2143 if (name != NULL) {
2144 /* This function returns name in big endian. */
1196ae02
RL		 2145 name[0] = MSB(mcp->mb[2]);
2146 name[1] = LSB(mcp->mb[2]);
2147 name[2] = MSB(mcp->mb[3]);
2148 name[3] = LSB(mcp->mb[3]);
2149 name[4] = MSB(mcp->mb[6]);
2150 name[5] = LSB(mcp->mb[6]);
2151 name[6] = MSB(mcp->mb[7]);
2152 name[7] = LSB(mcp->mb[7]);
1da177e4
LT		 2153 }
2154
5f28d2d7
SK		 2155 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
2156 "Done %s.\n", __func__);
1da177e4
LT		 2157 }
2158
2159 return rval;
2160}
2161
61e1b269
JC		 2162/*
2163 * qla24xx_link_initialization
2164 * Issue link initialization mailbox command.
2165 *
2166 * Input:
2167 * ha = adapter block pointer.
2168 * TARGET_QUEUE_LOCK must be released.
2169 * ADAPTER_STATE_LOCK must be released.
2170 *
2171 * Returns:
2172 * qla2x00 local function return status code.
2173 *
2174 * Context:
2175 * Kernel context.
2176 */
2177int
2178qla24xx_link_initialize(scsi_qla_host_t *vha)
2179{
2180 int rval;
2181 mbx_cmd_t mc;
2182 mbx_cmd_t *mcp = &mc;
2183
2184 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
2185 "Entered %s.\n", __func__);
2186
2187 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
2188 return QLA_FUNCTION_FAILED;
2189
2190 mcp->mb[0] = MBC_LINK_INITIALIZATION;
5a5c27b6
JC		 2191 mcp->mb[1] = BIT_4;
2192 if (vha->hw->operating_mode == LOOP)
2193 mcp->mb[1] |= BIT_6;
2194 else
2195 mcp->mb[1] |= BIT_5;
61e1b269
JC		 2196 mcp->mb[2] = 0;
2197 mcp->mb[3] = 0;
2198 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2199 mcp->in_mb = MBX_0;
2200 mcp->tov = MBX_TOV_SECONDS;
2201 mcp->flags = 0;
2202 rval = qla2x00_mailbox_command(vha, mcp);
2203
2204 if (rval != QLA_SUCCESS) {
2205 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
2206 } else {
2207 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
2208 "Done %s.\n", __func__);
2209 }
2210
2211 return rval;
2212}
2213
1da177e4
LT		 2214/*
2215 * qla2x00_lip_reset
2216 * Issue LIP reset mailbox command.
2217 *
2218 * Input:
2219 * ha = adapter block pointer.
2220 * TARGET_QUEUE_LOCK must be released.
2221 * ADAPTER_STATE_LOCK must be released.
2222 *
2223 * Returns:
2224 * qla2x00 local function return status code.
2225 *
2226 * Context:
2227 * Kernel context.
2228 */
2229int
7b867cf7 2230qla2x00_lip_reset(scsi_qla_host_t *vha)
1da177e4
LT		 2231{
2232 int rval;
2233 mbx_cmd_t mc;
2234 mbx_cmd_t *mcp = &mc;
2235
5f28d2d7
SK		 2236 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
2237 "Entered %s.\n", __func__);
1da177e4 2238
6246b8a1 2239 if (IS_CNA_CAPABLE(vha->hw)) {
3a03eb79
AV		 2240 /* Logout across all FCFs. */
2241 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2242 mcp->mb[1] = BIT_1;
2243 mcp->mb[2] = 0;
2244 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2245 } else if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357 2246 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
48acad09
QT		 2247 if (N2N_TOPO(vha->hw))
2248 mcp->mb[1] = BIT_4; /* re-init */
2249 else
2250 mcp->mb[1] = BIT_6; /* LIP */
0c8c39af 2251 mcp->mb[2] = 0;
7b867cf7 2252 mcp->mb[3] = vha->hw->loop_reset_delay;
1c7c6357 2253 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 2254 } else {
1c7c6357
AV		 2255 mcp->mb[0] = MBC_LIP_RESET;
2256 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 2257 if (HAS_EXTENDED_IDS(vha->hw)) {
1c7c6357
AV		 2258 mcp->mb[1] = 0x00ff;
2259 mcp->mb[10] = 0;
2260 mcp->out_mb |= MBX_10;
2261 } else {
2262 mcp->mb[1] = 0xff00;
2263 }
7b867cf7 2264 mcp->mb[2] = vha->hw->loop_reset_delay;
1c7c6357 2265 mcp->mb[3] = 0;
1da177e4 2266 }
1da177e4 2267 mcp->in_mb = MBX_0;
b93480e3 2268 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2269 mcp->flags = 0;
7b867cf7 2270 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2271
2272 if (rval != QLA_SUCCESS) {
2273 /*EMPTY*/
7c3df132 2274 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
1da177e4
LT		 2275 } else {
2276 /*EMPTY*/
5f28d2d7
SK		 2277 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
2278 "Done %s.\n", __func__);
1da177e4
LT		 2279 }
2280
2281 return rval;
2282}
2283
2284/*
2285 * qla2x00_send_sns
2286 * Send SNS command.
2287 *
2288 * Input:
2289 * ha = adapter block pointer.
2290 * sns = pointer for command.
2291 * cmd_size = command size.
2292 * buf_size = response/command size.
2293 * TARGET_QUEUE_LOCK must be released.
2294 * ADAPTER_STATE_LOCK must be released.
2295 *
2296 * Returns:
2297 * qla2x00 local function return status code.
2298 *
2299 * Context:
2300 * Kernel context.
2301 */
2302int
7b867cf7 2303qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
1da177e4
LT		 2304 uint16_t cmd_size, size_t buf_size)
2305{
2306 int rval;
2307 mbx_cmd_t mc;
2308 mbx_cmd_t *mcp = &mc;
2309
5f28d2d7
SK		 2310 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
2311 "Entered %s.\n", __func__);
1da177e4 2312
5f28d2d7 2313 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
7c3df132
SK		 2314 "Retry cnt=%d ratov=%d total tov=%d.\n",
2315 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
1da177e4
LT		 2316
2317 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
2318 mcp->mb[1] = cmd_size;
2319 mcp->mb[2] = MSW(sns_phys_address);
2320 mcp->mb[3] = LSW(sns_phys_address);
2321 mcp->mb[6] = MSW(MSD(sns_phys_address));
2322 mcp->mb[7] = LSW(MSD(sns_phys_address));
2323 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2324 mcp->in_mb = MBX_0|MBX_1;
2325 mcp->buf_size = buf_size;
2326 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
7b867cf7
AC		 2327 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
2328 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2329
2330 if (rval != QLA_SUCCESS) {
2331 /*EMPTY*/
7c3df132
SK		 2332 ql_dbg(ql_dbg_mbx, vha, 0x105f,
2333 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2334 rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 2335 } else {
2336 /*EMPTY*/
5f28d2d7
SK		 2337 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
2338 "Done %s.\n", __func__);
1da177e4
LT		 2339 }
2340
2341 return rval;
2342}
2343
1c7c6357 2344int
7b867cf7 2345qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 2346 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2347{
2348 int rval;
2349
2350 struct logio_entry_24xx *lg;
2351 dma_addr_t lg_dma;
2352 uint32_t iop[2];
7b867cf7 2353 struct qla_hw_data *ha = vha->hw;
2afa19a9 2354 struct req_que *req;
1c7c6357 2355
5f28d2d7
SK		 2356 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
2357 "Entered %s.\n", __func__);
1c7c6357 2358
d7459527
MH		 2359 if (vha->vp_idx && vha->qpair)
2360 req = vha->qpair->req;
68ca949c 2361 else
d7459527 2362 req = ha->req_q_map[0];
2afa19a9 2363
08eb7f45 2364 lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1c7c6357 2365 if (lg == NULL) {
7c3df132
SK		 2366 ql_log(ql_log_warn, vha, 0x1062,
2367 "Failed to allocate login IOCB.\n");
1c7c6357
AV		 2368 return QLA_MEMORY_ALLOC_FAILED;
2369 }
1c7c6357
AV		 2370
2371 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2372 lg->entry_count = 1;
2afa19a9 2373 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357 2374 lg->nport_handle = cpu_to_le16(loop_id);
ad950360 2375 lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI);
1c7c6357 2376 if (opt & BIT_0)
ad950360 2377 lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI);
8baa51a6 2378 if (opt & BIT_1)
ad950360 2379 lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI);
1c7c6357
AV		 2380 lg->port_id[0] = al_pa;
2381 lg->port_id[1] = area;
2382 lg->port_id[2] = domain;
7b867cf7 2383 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 2384 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2385 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 2386 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2387 ql_dbg(ql_dbg_mbx, vha, 0x1063,
2388 "Failed to issue login IOCB (%x).\n", rval);
1c7c6357 2389 } else if (lg->entry_status != 0) {
7c3df132
SK		 2390 ql_dbg(ql_dbg_mbx, vha, 0x1064,
2391 "Failed to complete IOCB -- error status (%x).\n",
2392 lg->entry_status);
1c7c6357 2393 rval = QLA_FUNCTION_FAILED;
ad950360 2394 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
1c7c6357
AV		 2395 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2396 iop[1] = le32_to_cpu(lg->io_parameter[1]);
2397
7c3df132
SK		 2398 ql_dbg(ql_dbg_mbx, vha, 0x1065,
2399 "Failed to complete IOCB -- completion status (%x) "
2400 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
2401 iop[0], iop[1]);
1c7c6357
AV		 2402
2403 switch (iop[0]) {
2404 case LSC_SCODE_PORTID_USED:
2405 mb[0] = MBS_PORT_ID_USED;
2406 mb[1] = LSW(iop[1]);
2407 break;
2408 case LSC_SCODE_NPORT_USED:
2409 mb[0] = MBS_LOOP_ID_USED;
2410 break;
2411 case LSC_SCODE_NOLINK:
2412 case LSC_SCODE_NOIOCB:
2413 case LSC_SCODE_NOXCB:
2414 case LSC_SCODE_CMD_FAILED:
2415 case LSC_SCODE_NOFABRIC:
2416 case LSC_SCODE_FW_NOT_READY:
2417 case LSC_SCODE_NOT_LOGGED_IN:
2418 case LSC_SCODE_NOPCB:
2419 case LSC_SCODE_ELS_REJECT:
2420 case LSC_SCODE_CMD_PARAM_ERR:
2421 case LSC_SCODE_NONPORT:
2422 case LSC_SCODE_LOGGED_IN:
2423 case LSC_SCODE_NOFLOGI_ACC:
2424 default:
2425 mb[0] = MBS_COMMAND_ERROR;
2426 break;
2427 }
2428 } else {
5f28d2d7
SK		 2429 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
2430 "Done %s.\n", __func__);
1c7c6357
AV		 2431
2432 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2433
2434 mb[0] = MBS_COMMAND_COMPLETE;
2435 mb[1] = 0;
2436 if (iop[0] & BIT_4) {
2437 if (iop[0] & BIT_8)
2438 mb[1] |= BIT_1;
2439 } else
2440 mb[1] = BIT_0;
ad3e0eda
AV		 2441
2442 /* Passback COS information. */
2443 mb[10] = 0;
2444 if (lg->io_parameter[7] || lg->io_parameter[8])
2445 mb[10] |= BIT_0; /* Class 2. */
2446 if (lg->io_parameter[9] || lg->io_parameter[10])
2447 mb[10] |= BIT_1; /* Class 3. */
ad950360 2448 if (lg->io_parameter[0] & cpu_to_le32(BIT_7))
2d70c103
NB		 2449 mb[10] |= BIT_7; /* Confirmed Completion
2450 * Allowed
2451 */
1c7c6357
AV		 2452 }
2453
2454 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2455
2456 return rval;
2457}
2458
1da177e4
LT		 2459/*
2460 * qla2x00_login_fabric
2461 * Issue login fabric port mailbox command.
2462 *
2463 * Input:
2464 * ha = adapter block pointer.
2465 * loop_id = device loop ID.
2466 * domain = device domain.
2467 * area = device area.
2468 * al_pa = device AL_PA.
2469 * status = pointer for return status.
2470 * opt = command options.
2471 * TARGET_QUEUE_LOCK must be released.
2472 * ADAPTER_STATE_LOCK must be released.
2473 *
2474 * Returns:
2475 * qla2x00 local function return status code.
2476 *
2477 * Context:
2478 * Kernel context.
2479 */
2480int
7b867cf7 2481qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1da177e4
LT		 2482 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2483{
2484 int rval;
2485 mbx_cmd_t mc;
2486 mbx_cmd_t *mcp = &mc;
7b867cf7 2487 struct qla_hw_data *ha = vha->hw;
1da177e4 2488
5f28d2d7
SK		 2489 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
2490 "Entered %s.\n", __func__);
1da177e4
LT		 2491
2492 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
2493 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2494 if (HAS_EXTENDED_IDS(ha)) {
2495 mcp->mb[1] = loop_id;
2496 mcp->mb[10] = opt;
2497 mcp->out_mb |= MBX_10;
2498 } else {
2499 mcp->mb[1] = (loop_id << 8) | opt;
2500 }
2501 mcp->mb[2] = domain;
2502 mcp->mb[3] = area << 8 | al_pa;
2503
2504 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
2505 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2506 mcp->flags = 0;
7b867cf7 2507 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2508
2509 /* Return mailbox statuses. */
2510 if (mb != NULL) {
2511 mb[0] = mcp->mb[0];
2512 mb[1] = mcp->mb[1];
2513 mb[2] = mcp->mb[2];
2514 mb[6] = mcp->mb[6];
2515 mb[7] = mcp->mb[7];
ad3e0eda
AV		 2516 /* COS retrieved from Get-Port-Database mailbox command. */
2517 mb[10] = 0;
1da177e4
LT		 2518 }
2519
2520 if (rval != QLA_SUCCESS) {
2521 /* RLU tmp code: need to change main mailbox_command function to
2522 * return ok even when the mailbox completion value is not
2523 * SUCCESS. The caller needs to be responsible to interpret
2524 * the return values of this mailbox command if we're not
2525 * to change too much of the existing code.
2526 */
2527 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
2528 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
2529 mcp->mb[0] == 0x4006)
2530 rval = QLA_SUCCESS;
2531
2532 /*EMPTY*/
7c3df132
SK		 2533 ql_dbg(ql_dbg_mbx, vha, 0x1068,
2534 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
2535 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1da177e4
LT		 2536 } else {
2537 /*EMPTY*/
5f28d2d7
SK		 2538 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
2539 "Done %s.\n", __func__);
1da177e4
LT		 2540 }
2541
2542 return rval;
2543}
2544
2545/*
2546 * qla2x00_login_local_device
2547 * Issue login loop port mailbox command.
fa2a1ce5 2548 *
1da177e4
LT		 2549 * Input:
2550 * ha = adapter block pointer.
2551 * loop_id = device loop ID.
2552 * opt = command options.
fa2a1ce5 2553 *
1da177e4
LT		 2554 * Returns:
2555 * Return status code.
fa2a1ce5 2556 *
1da177e4
LT		 2557 * Context:
2558 * Kernel context.
fa2a1ce5 2559 *
1da177e4
LT		 2560 */
2561int
7b867cf7 2562qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 2563 uint16_t *mb_ret, uint8_t opt)
2564{
2565 int rval;
2566 mbx_cmd_t mc;
2567 mbx_cmd_t *mcp = &mc;
7b867cf7 2568 struct qla_hw_data *ha = vha->hw;
1da177e4 2569
5f28d2d7
SK		 2570 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
2571 "Entered %s.\n", __func__);
7c3df132 2572
e428924c 2573 if (IS_FWI2_CAPABLE(ha))
7b867cf7 2574 return qla24xx_login_fabric(vha, fcport->loop_id,
9a52a57c 2575 fcport->d_id.b.domain, fcport->d_id.b.area,
2576 fcport->d_id.b.al_pa, mb_ret, opt);
2577
1da177e4
LT		 2578 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
2579 if (HAS_EXTENDED_IDS(ha))
9a52a57c 2580 mcp->mb[1] = fcport->loop_id;
1da177e4 2581 else
9a52a57c 2582 mcp->mb[1] = fcport->loop_id << 8;
1da177e4
LT		 2583 mcp->mb[2] = opt;
2584 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2585 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
2586 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2587 mcp->flags = 0;
7b867cf7 2588 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2589
2590 /* Return mailbox statuses. */
2591 if (mb_ret != NULL) {
2592 mb_ret[0] = mcp->mb[0];
2593 mb_ret[1] = mcp->mb[1];
2594 mb_ret[6] = mcp->mb[6];
2595 mb_ret[7] = mcp->mb[7];
2596 }
2597
2598 if (rval != QLA_SUCCESS) {
2599 /* AV tmp code: need to change main mailbox_command function to
2600 * return ok even when the mailbox completion value is not
2601 * SUCCESS. The caller needs to be responsible to interpret
2602 * the return values of this mailbox command if we're not
2603 * to change too much of the existing code.
2604 */
2605 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
2606 rval = QLA_SUCCESS;
2607
7c3df132
SK		 2608 ql_dbg(ql_dbg_mbx, vha, 0x106b,
2609 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
2610 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
1da177e4
LT		 2611 } else {
2612 /*EMPTY*/
5f28d2d7
SK		 2613 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
2614 "Done %s.\n", __func__);
1da177e4
LT		 2615 }
2616
2617 return (rval);
2618}
2619
1c7c6357 2620int
7b867cf7 2621qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 2622 uint8_t area, uint8_t al_pa)
2623{
2624 int rval;
2625 struct logio_entry_24xx *lg;
2626 dma_addr_t lg_dma;
7b867cf7 2627 struct qla_hw_data *ha = vha->hw;
2afa19a9 2628 struct req_que *req;
1c7c6357 2629
5f28d2d7
SK		 2630 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
2631 "Entered %s.\n", __func__);
1c7c6357 2632
08eb7f45 2633 lg = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1c7c6357 2634 if (lg == NULL) {
7c3df132
SK		 2635 ql_log(ql_log_warn, vha, 0x106e,
2636 "Failed to allocate logout IOCB.\n");
1c7c6357
AV		 2637 return QLA_MEMORY_ALLOC_FAILED;
2638 }
1c7c6357 2639
d7459527 2640 req = vha->req;
1c7c6357
AV		 2641 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2642 lg->entry_count = 1;
2afa19a9 2643 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357
AV		 2644 lg->nport_handle = cpu_to_le16(loop_id);
2645 lg->control_flags =
ad950360 2646 cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
c8d6691b 2647 LCF_FREE_NPORT);
1c7c6357
AV		 2648 lg->port_id[0] = al_pa;
2649 lg->port_id[1] = area;
2650 lg->port_id[2] = domain;
7b867cf7 2651 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 2652 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2653 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 2654 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2655 ql_dbg(ql_dbg_mbx, vha, 0x106f,
2656 "Failed to issue logout IOCB (%x).\n", rval);
1c7c6357 2657 } else if (lg->entry_status != 0) {
7c3df132
SK		 2658 ql_dbg(ql_dbg_mbx, vha, 0x1070,
2659 "Failed to complete IOCB -- error status (%x).\n",
2660 lg->entry_status);
1c7c6357 2661 rval = QLA_FUNCTION_FAILED;
ad950360 2662 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 2663 ql_dbg(ql_dbg_mbx, vha, 0x1071,
2664 "Failed to complete IOCB -- completion status (%x) "
2665 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1c7c6357 2666 le32_to_cpu(lg->io_parameter[0]),
7c3df132 2667 le32_to_cpu(lg->io_parameter[1]));
1c7c6357
AV		 2668 } else {
2669 /*EMPTY*/
5f28d2d7
SK		 2670 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
2671 "Done %s.\n", __func__);
1c7c6357
AV		 2672 }
2673
2674 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2675
2676 return rval;
2677}
2678
1da177e4
LT		 2679/*
2680 * qla2x00_fabric_logout
2681 * Issue logout fabric port mailbox command.
2682 *
2683 * Input:
2684 * ha = adapter block pointer.
2685 * loop_id = device loop ID.
2686 * TARGET_QUEUE_LOCK must be released.
2687 * ADAPTER_STATE_LOCK must be released.
2688 *
2689 * Returns:
2690 * qla2x00 local function return status code.
2691 *
2692 * Context:
2693 * Kernel context.
2694 */
2695int
7b867cf7 2696qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357 2697 uint8_t area, uint8_t al_pa)
1da177e4
LT		 2698{
2699 int rval;
2700 mbx_cmd_t mc;
2701 mbx_cmd_t *mcp = &mc;
2702
5f28d2d7
SK		 2703 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
2704 "Entered %s.\n", __func__);
1da177e4
LT		 2705
2706 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
2707 mcp->out_mb = MBX_1|MBX_0;
7b867cf7 2708 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 2709 mcp->mb[1] = loop_id;
2710 mcp->mb[10] = 0;
2711 mcp->out_mb |= MBX_10;
2712 } else {
2713 mcp->mb[1] = loop_id << 8;
2714 }
2715
2716 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2717 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2718 mcp->flags = 0;
7b867cf7 2719 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2720
2721 if (rval != QLA_SUCCESS) {
2722 /*EMPTY*/
7c3df132
SK		 2723 ql_dbg(ql_dbg_mbx, vha, 0x1074,
2724 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
1da177e4
LT		 2725 } else {
2726 /*EMPTY*/
5f28d2d7
SK		 2727 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
2728 "Done %s.\n", __func__);
1da177e4
LT		 2729 }
2730
2731 return rval;
2732}
2733
2734/*
2735 * qla2x00_full_login_lip
2736 * Issue full login LIP mailbox command.
2737 *
2738 * Input:
2739 * ha = adapter block pointer.
2740 * TARGET_QUEUE_LOCK must be released.
2741 * ADAPTER_STATE_LOCK must be released.
2742 *
2743 * Returns:
2744 * qla2x00 local function return status code.
2745 *
2746 * Context:
2747 * Kernel context.
2748 */
2749int
7b867cf7 2750qla2x00_full_login_lip(scsi_qla_host_t *vha)
1da177e4
LT		 2751{
2752 int rval;
2753 mbx_cmd_t mc;
2754 mbx_cmd_t *mcp = &mc;
2755
5f28d2d7
SK		 2756 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
2757 "Entered %s.\n", __func__);
1da177e4
LT		 2758
2759 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
7b867cf7 2760 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
0c8c39af 2761 mcp->mb[2] = 0;
1da177e4
LT		 2762 mcp->mb[3] = 0;
2763 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2764 mcp->in_mb = MBX_0;
b93480e3 2765 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2766 mcp->flags = 0;
7b867cf7 2767 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2768
2769 if (rval != QLA_SUCCESS) {
2770 /*EMPTY*/
7c3df132 2771 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
1da177e4
LT		 2772 } else {
2773 /*EMPTY*/
5f28d2d7
SK		 2774 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
2775 "Done %s.\n", __func__);
1da177e4
LT		 2776 }
2777
2778 return rval;
2779}
2780
2781/*
2782 * qla2x00_get_id_list
2783 *
2784 * Input:
2785 * ha = adapter block pointer.
2786 *
2787 * Returns:
2788 * qla2x00 local function return status code.
2789 *
2790 * Context:
2791 * Kernel context.
2792 */
2793int
7b867cf7 2794qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
1da177e4
LT		 2795 uint16_t *entries)
2796{
2797 int rval;
2798 mbx_cmd_t mc;
2799 mbx_cmd_t *mcp = &mc;
2800
5f28d2d7
SK		 2801 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
2802 "Entered %s.\n", __func__);
1da177e4
LT		 2803
2804 if (id_list == NULL)
2805 return QLA_FUNCTION_FAILED;
2806
2807 mcp->mb[0] = MBC_GET_ID_LIST;
1c7c6357 2808 mcp->out_mb = MBX_0;
7b867cf7 2809 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 2810 mcp->mb[2] = MSW(id_list_dma);
2811 mcp->mb[3] = LSW(id_list_dma);
2812 mcp->mb[6] = MSW(MSD(id_list_dma));
2813 mcp->mb[7] = LSW(MSD(id_list_dma));
247ec457 2814 mcp->mb[8] = 0;
7b867cf7 2815 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 2816 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
1c7c6357
AV		 2817 } else {
2818 mcp->mb[1] = MSW(id_list_dma);
2819 mcp->mb[2] = LSW(id_list_dma);
2820 mcp->mb[3] = MSW(MSD(id_list_dma));
2821 mcp->mb[6] = LSW(MSD(id_list_dma));
2822 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
2823 }
1da177e4 2824 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2825 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2826 mcp->flags = 0;
7b867cf7 2827 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2828
2829 if (rval != QLA_SUCCESS) {
2830 /*EMPTY*/
7c3df132 2831 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
1da177e4
LT		 2832 } else {
2833 *entries = mcp->mb[1];
5f28d2d7
SK		 2834 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
2835 "Done %s.\n", __func__);
1da177e4
LT		 2836 }
2837
2838 return rval;
2839}
2840
2841/*
2842 * qla2x00_get_resource_cnts
2843 * Get current firmware resource counts.
2844 *
2845 * Input:
2846 * ha = adapter block pointer.
2847 *
2848 * Returns:
2849 * qla2x00 local function return status code.
2850 *
2851 * Context:
2852 * Kernel context.
2853 */
2854int
03e8c680 2855qla2x00_get_resource_cnts(scsi_qla_host_t *vha)
1da177e4 2856{
03e8c680 2857 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2858 int rval;
2859 mbx_cmd_t mc;
2860 mbx_cmd_t *mcp = &mc;
2861
5f28d2d7
SK		 2862 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
2863 "Entered %s.\n", __func__);
1da177e4
LT		 2864
2865 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2866 mcp->out_mb = MBX_0;
4d0ea247 2867 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
f73cb695 2868 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw))
f3a0a77e 2869 mcp->in_mb |= MBX_12;
b93480e3 2870 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2871 mcp->flags = 0;
7b867cf7 2872 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2873
2874 if (rval != QLA_SUCCESS) {
2875 /*EMPTY*/
7c3df132
SK		 2876 ql_dbg(ql_dbg_mbx, vha, 0x107d,
2877 "Failed mb[0]=%x.\n", mcp->mb[0]);
1da177e4 2878 } else {
5f28d2d7 2879 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
7c3df132
SK		 2880 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
2881 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
2882 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
2883 mcp->mb[11], mcp->mb[12]);
1da177e4 2884
03e8c680
QT		 2885 ha->orig_fw_tgt_xcb_count = mcp->mb[1];
2886 ha->cur_fw_tgt_xcb_count = mcp->mb[2];
2887 ha->cur_fw_xcb_count = mcp->mb[3];
2888 ha->orig_fw_xcb_count = mcp->mb[6];
2889 ha->cur_fw_iocb_count = mcp->mb[7];
2890 ha->orig_fw_iocb_count = mcp->mb[10];
2891 if (ha->flags.npiv_supported)
2892 ha->max_npiv_vports = mcp->mb[11];
2893 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
2894 ha->fw_max_fcf_count = mcp->mb[12];
1da177e4
LT		 2895 }
2896
2897 return (rval);
2898}
2899
1da177e4
LT		 2900/*
2901 * qla2x00_get_fcal_position_map
2902 * Get FCAL (LILP) position map using mailbox command
2903 *
2904 * Input:
2905 * ha = adapter state pointer.
2906 * pos_map = buffer pointer (can be NULL).
2907 *
2908 * Returns:
2909 * qla2x00 local function return status code.
2910 *
2911 * Context:
2912 * Kernel context.
2913 */
2914int
7b867cf7 2915qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
1da177e4
LT		 2916{
2917 int rval;
2918 mbx_cmd_t mc;
2919 mbx_cmd_t *mcp = &mc;
2920 char *pmap;
2921 dma_addr_t pmap_dma;
7b867cf7 2922 struct qla_hw_data *ha = vha->hw;
1da177e4 2923
5f28d2d7
SK		 2924 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
2925 "Entered %s.\n", __func__);
7c3df132 2926
08eb7f45 2927 pmap = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
1da177e4 2928 if (pmap == NULL) {
7c3df132
SK		 2929 ql_log(ql_log_warn, vha, 0x1080,
2930 "Memory alloc failed.\n");
1da177e4
LT		 2931 return QLA_MEMORY_ALLOC_FAILED;
2932 }
1da177e4
LT		 2933
2934 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
2935 mcp->mb[2] = MSW(pmap_dma);
2936 mcp->mb[3] = LSW(pmap_dma);
2937 mcp->mb[6] = MSW(MSD(pmap_dma));
2938 mcp->mb[7] = LSW(MSD(pmap_dma));
2939 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2940 mcp->in_mb = MBX_1|MBX_0;
2941 mcp->buf_size = FCAL_MAP_SIZE;
2942 mcp->flags = MBX_DMA_IN;
2943 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 2944 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2945
2946 if (rval == QLA_SUCCESS) {
5f28d2d7 2947 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
7c3df132
SK		 2948 "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
2949 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
2950 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
2951 pmap, pmap[0] + 1);
1da177e4
LT		 2952
2953 if (pos_map)
2954 memcpy(pos_map, pmap, FCAL_MAP_SIZE);
2955 }
2956 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
2957
2958 if (rval != QLA_SUCCESS) {
7c3df132 2959 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
1da177e4 2960 } else {
5f28d2d7
SK		 2961 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
2962 "Done %s.\n", __func__);
1da177e4
LT		 2963 }
2964
2965 return rval;
2966}
392e2f65 2967
2968/*
2969 * qla2x00_get_link_status
2970 *
2971 * Input:
2972 * ha = adapter block pointer.
2973 * loop_id = device loop ID.
2974 * ret_buf = pointer to link status return buffer.
2975 *
2976 * Returns:
2977 * 0 = success.
2978 * BIT_0 = mem alloc error.
2979 * BIT_1 = mailbox error.
2980 */
2981int
7b867cf7 2982qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
43ef0580 2983 struct link_statistics *stats, dma_addr_t stats_dma)
392e2f65 2984{
2985 int rval;
2986 mbx_cmd_t mc;
2987 mbx_cmd_t *mcp = &mc;
c6dc9905
JC		 2988 uint32_t *iter = (void *)stats;
2989 ushort dwords = offsetof(typeof(*stats), link_up_cnt)/sizeof(*iter);
7b867cf7 2990 struct qla_hw_data *ha = vha->hw;
392e2f65 2991
5f28d2d7
SK		 2992 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
2993 "Entered %s.\n", __func__);
392e2f65 2994
392e2f65 2995 mcp->mb[0] = MBC_GET_LINK_STATUS;
c6dc9905
JC		 2996 mcp->mb[2] = MSW(LSD(stats_dma));
2997 mcp->mb[3] = LSW(LSD(stats_dma));
43ef0580
AV		 2998 mcp->mb[6] = MSW(MSD(stats_dma));
2999 mcp->mb[7] = LSW(MSD(stats_dma));
392e2f65 3000 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
3001 mcp->in_mb = MBX_0;
e428924c 3002 if (IS_FWI2_CAPABLE(ha)) {
392e2f65 3003 mcp->mb[1] = loop_id;
3004 mcp->mb[4] = 0;
3005 mcp->mb[10] = 0;
3006 mcp->out_mb |= MBX_10|MBX_4|MBX_1;
3007 mcp->in_mb |= MBX_1;
3008 } else if (HAS_EXTENDED_IDS(ha)) {
3009 mcp->mb[1] = loop_id;
3010 mcp->mb[10] = 0;
3011 mcp->out_mb |= MBX_10|MBX_1;
3012 } else {
3013 mcp->mb[1] = loop_id << 8;
3014 mcp->out_mb |= MBX_1;
3015 }
b93480e3 3016 mcp->tov = MBX_TOV_SECONDS;
392e2f65 3017 mcp->flags = IOCTL_CMD;
7b867cf7 3018 rval = qla2x00_mailbox_command(vha, mcp);
392e2f65 3019
3020 if (rval == QLA_SUCCESS) {
3021 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3022 ql_dbg(ql_dbg_mbx, vha, 0x1085,
3023 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
43ef0580 3024 rval = QLA_FUNCTION_FAILED;
392e2f65 3025 } else {
c6dc9905 3026 /* Re-endianize - firmware data is le32. */
5f28d2d7
SK		 3027 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
3028 "Done %s.\n", __func__);
da08ef5c
JC		 3029 for ( ; dwords--; iter++)
3030 le32_to_cpus(iter);
392e2f65 3031 }
3032 } else {
3033 /* Failed. */
7c3df132 3034 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
392e2f65 3035 }
3036
392e2f65 3037 return rval;
3038}
3039
3040int
7b867cf7 3041qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
15f30a57 3042 dma_addr_t stats_dma, uint16_t options)
1c7c6357
AV		 3043{
3044 int rval;
3045 mbx_cmd_t mc;
3046 mbx_cmd_t *mcp = &mc;
da08ef5c 3047 uint32_t *iter, dwords;
1c7c6357 3048
5f28d2d7
SK		 3049 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
3050 "Entered %s.\n", __func__);
1c7c6357 3051
15f30a57
QT		 3052 memset(&mc, 0, sizeof(mc));
3053 mc.mb[0] = MBC_GET_LINK_PRIV_STATS;
3054 mc.mb[2] = MSW(stats_dma);
3055 mc.mb[3] = LSW(stats_dma);
3056 mc.mb[6] = MSW(MSD(stats_dma));
3057 mc.mb[7] = LSW(MSD(stats_dma));
3058 mc.mb[8] = sizeof(struct link_statistics) / 4;
3059 mc.mb[9] = cpu_to_le16(vha->vp_idx);
3060 mc.mb[10] = cpu_to_le16(options);
3061
3062 rval = qla24xx_send_mb_cmd(vha, &mc);
1c7c6357
AV		 3063
3064 if (rval == QLA_SUCCESS) {
3065 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3066 ql_dbg(ql_dbg_mbx, vha, 0x1089,
3067 "Failed mb[0]=%x.\n", mcp->mb[0]);
43ef0580 3068 rval = QLA_FUNCTION_FAILED;
1c7c6357 3069 } else {
5f28d2d7
SK		 3070 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
3071 "Done %s.\n", __func__);
c6dc9905 3072 /* Re-endianize - firmware data is le32. */
43ef0580 3073 dwords = sizeof(struct link_statistics) / 4;
da08ef5c
JC		 3074 iter = &stats->link_fail_cnt;
3075 for ( ; dwords--; iter++)
3076 le32_to_cpus(iter);
1c7c6357
AV		 3077 }
3078 } else {
3079 /* Failed. */
7c3df132 3080 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
1c7c6357
AV		 3081 }
3082
1c7c6357
AV		 3083 return rval;
3084}
1c7c6357
AV		 3085
3086int
2afa19a9 3087qla24xx_abort_command(srb_t *sp)
1c7c6357
AV		 3088{
3089 int rval;
1c7c6357
AV		 3090 unsigned long flags = 0;
3091
3092 struct abort_entry_24xx *abt;
3093 dma_addr_t abt_dma;
3094 uint32_t handle;
2afa19a9
AC		 3095 fc_port_t *fcport = sp->fcport;
3096 struct scsi_qla_host *vha = fcport->vha;
7b867cf7 3097 struct qla_hw_data *ha = vha->hw;
67c2e93a 3098 struct req_que *req = vha->req;
585def9b 3099 struct qla_qpair *qpair = sp->qpair;
1c7c6357 3100
5f28d2d7
SK		 3101 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
3102 "Entered %s.\n", __func__);
1c7c6357 3103
d7459527
MH		 3104 if (vha->flags.qpairs_available && sp->qpair)
3105 req = sp->qpair->req;
585def9b
QT		 3106 else
3107 return QLA_FUNCTION_FAILED;
d7459527 3108
4440e46d
AB		 3109 if (ql2xasynctmfenable)
3110 return qla24xx_async_abort_command(sp);
3111
585def9b 3112 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
8d93f550 3113 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 3114 if (req->outstanding_cmds[handle] == sp)
1c7c6357
AV		 3115 break;
3116 }
585def9b 3117 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
8d93f550 3118 if (handle == req->num_outstanding_cmds) {
1c7c6357
AV		 3119 /* Command not found. */
3120 return QLA_FUNCTION_FAILED;
3121 }
3122
08eb7f45 3123 abt = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
1c7c6357 3124 if (abt == NULL) {
7c3df132
SK		 3125 ql_log(ql_log_warn, vha, 0x108d,
3126 "Failed to allocate abort IOCB.\n");
1c7c6357
AV		 3127 return QLA_MEMORY_ALLOC_FAILED;
3128 }
1c7c6357
AV		 3129
3130 abt->entry_type = ABORT_IOCB_TYPE;
3131 abt->entry_count = 1;
2afa19a9 3132 abt->handle = MAKE_HANDLE(req->id, abt->handle);
1c7c6357 3133 abt->nport_handle = cpu_to_le16(fcport->loop_id);
a74ec14f 3134 abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
1c7c6357
AV		 3135 abt->port_id[0] = fcport->d_id.b.al_pa;
3136 abt->port_id[1] = fcport->d_id.b.area;
3137 abt->port_id[2] = fcport->d_id.b.domain;
c6d39e23 3138 abt->vp_index = fcport->vha->vp_idx;
73208dfd
AC		 3139
3140 abt->req_que_no = cpu_to_le16(req->id);
3141
7b867cf7 3142 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
1c7c6357 3143 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3144 ql_dbg(ql_dbg_mbx, vha, 0x108e,
3145 "Failed to issue IOCB (%x).\n", rval);
1c7c6357 3146 } else if (abt->entry_status != 0) {
7c3df132
SK		 3147 ql_dbg(ql_dbg_mbx, vha, 0x108f,
3148 "Failed to complete IOCB -- error status (%x).\n",
3149 abt->entry_status);
1c7c6357 3150 rval = QLA_FUNCTION_FAILED;
ad950360 3151 } else if (abt->nport_handle != cpu_to_le16(0)) {
7c3df132
SK		 3152 ql_dbg(ql_dbg_mbx, vha, 0x1090,
3153 "Failed to complete IOCB -- completion status (%x).\n",
3154 le16_to_cpu(abt->nport_handle));
f934c9d0
CD		 3155 if (abt->nport_handle == CS_IOCB_ERROR)
3156 rval = QLA_FUNCTION_PARAMETER_ERROR;
3157 else
3158 rval = QLA_FUNCTION_FAILED;
1c7c6357 3159 } else {
5f28d2d7
SK		 3160 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
3161 "Done %s.\n", __func__);
1c7c6357
AV		 3162 }
3163
3164 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
3165
3166 return rval;
3167}
3168
3169struct tsk_mgmt_cmd {
3170 union {
3171 struct tsk_mgmt_entry tsk;
3172 struct sts_entry_24xx sts;
3173 } p;
3174};
3175
523ec773
AV		 3176static int
3177__qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
9cb78c16 3178 uint64_t l, int tag)
1c7c6357 3179{
523ec773 3180 int rval, rval2;
1c7c6357 3181 struct tsk_mgmt_cmd *tsk;
9ca1d01f 3182 struct sts_entry_24xx *sts;
1c7c6357 3183 dma_addr_t tsk_dma;
7b867cf7
AC		 3184 scsi_qla_host_t *vha;
3185 struct qla_hw_data *ha;
73208dfd
AC		 3186 struct req_que *req;
3187 struct rsp_que *rsp;
d7459527 3188 struct qla_qpair *qpair;
1c7c6357 3189
7b867cf7
AC		 3190 vha = fcport->vha;
3191 ha = vha->hw;
2afa19a9 3192 req = vha->req;
7c3df132 3193
5f28d2d7
SK		 3194 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
3195 "Entered %s.\n", __func__);
7c3df132 3196
d7459527
MH		 3197 if (vha->vp_idx && vha->qpair) {
3198 /* NPIV port */
3199 qpair = vha->qpair;
3200 rsp = qpair->rsp;
3201 req = qpair->req;
3202 } else {
68ca949c 3203 rsp = req->rsp;
d7459527
MH		 3204 }
3205
08eb7f45 3206 tsk = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
1c7c6357 3207 if (tsk == NULL) {
7c3df132
SK		 3208 ql_log(ql_log_warn, vha, 0x1093,
3209 "Failed to allocate task management IOCB.\n");
1c7c6357
AV		 3210 return QLA_MEMORY_ALLOC_FAILED;
3211 }
1c7c6357
AV		 3212
3213 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
3214 tsk->p.tsk.entry_count = 1;
2afa19a9 3215 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
1c7c6357 3216 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
00a537b8 3217 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
523ec773 3218 tsk->p.tsk.control_flags = cpu_to_le32(type);
1c7c6357
AV		 3219 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
3220 tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
3221 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
c6d39e23 3222 tsk->p.tsk.vp_index = fcport->vha->vp_idx;
523ec773
AV		 3223 if (type == TCF_LUN_RESET) {
3224 int_to_scsilun(l, &tsk->p.tsk.lun);
3225 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
3226 sizeof(tsk->p.tsk.lun));
3227 }
2c3dfe3f 3228
9ca1d01f 3229 sts = &tsk->p.sts;
7b867cf7 3230 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
1c7c6357 3231 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3232 ql_dbg(ql_dbg_mbx, vha, 0x1094,
3233 "Failed to issue %s reset IOCB (%x).\n", name, rval);
9ca1d01f 3234 } else if (sts->entry_status != 0) {
7c3df132
SK		 3235 ql_dbg(ql_dbg_mbx, vha, 0x1095,
3236 "Failed to complete IOCB -- error status (%x).\n",
3237 sts->entry_status);
1c7c6357 3238 rval = QLA_FUNCTION_FAILED;
ad950360 3239 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3240 ql_dbg(ql_dbg_mbx, vha, 0x1096,
3241 "Failed to complete IOCB -- completion status (%x).\n",
3242 le16_to_cpu(sts->comp_status));
9ca1d01f 3243 rval = QLA_FUNCTION_FAILED;
97dec564
AV		 3244 } else if (le16_to_cpu(sts->scsi_status) &
3245 SS_RESPONSE_INFO_LEN_VALID) {
3246 if (le32_to_cpu(sts->rsp_data_len) < 4) {
5f28d2d7 3247 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
7c3df132
SK		 3248 "Ignoring inconsistent data length -- not enough "
3249 "response info (%d).\n",
3250 le32_to_cpu(sts->rsp_data_len));
97dec564 3251 } else if (sts->data[3]) {
7c3df132
SK		 3252 ql_dbg(ql_dbg_mbx, vha, 0x1098,
3253 "Failed to complete IOCB -- response (%x).\n",
3254 sts->data[3]);
97dec564
AV		 3255 rval = QLA_FUNCTION_FAILED;
3256 }
1c7c6357
AV		 3257 }
3258
3259 /* Issue marker IOCB. */
73208dfd 3260 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
523ec773
AV		 3261 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
3262 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3263 ql_dbg(ql_dbg_mbx, vha, 0x1099,
3264 "Failed to issue marker IOCB (%x).\n", rval2);
1c7c6357 3265 } else {
5f28d2d7
SK		 3266 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
3267 "Done %s.\n", __func__);
1c7c6357
AV		 3268 }
3269
7b867cf7 3270 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
1c7c6357
AV		 3271
3272 return rval;
3273}
3274
523ec773 3275int
9cb78c16 3276qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag)
523ec773 3277{
3822263e
MI		 3278 struct qla_hw_data *ha = fcport->vha->hw;
3279
3280 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3281 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
3282
2afa19a9 3283 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
523ec773
AV		 3284}
3285
3286int
9cb78c16 3287qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
523ec773 3288{
3822263e
MI		 3289 struct qla_hw_data *ha = fcport->vha->hw;
3290
3291 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3292 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
3293
2afa19a9 3294 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
523ec773
AV		 3295}
3296
1c7c6357 3297int
7b867cf7 3298qla2x00_system_error(scsi_qla_host_t *vha)
1c7c6357
AV		 3299{
3300 int rval;
3301 mbx_cmd_t mc;
3302 mbx_cmd_t *mcp = &mc;
7b867cf7 3303 struct qla_hw_data *ha = vha->hw;
1c7c6357 3304
68af0811 3305 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 3306 return QLA_FUNCTION_FAILED;
3307
5f28d2d7
SK		 3308 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
3309 "Entered %s.\n", __func__);
1c7c6357
AV		 3310
3311 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
3312 mcp->out_mb = MBX_0;
3313 mcp->in_mb = MBX_0;
3314 mcp->tov = 5;
3315 mcp->flags = 0;
7b867cf7 3316 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 3317
3318 if (rval != QLA_SUCCESS) {
7c3df132 3319 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
1c7c6357 3320 } else {
5f28d2d7
SK		 3321 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
3322 "Done %s.\n", __func__);
1c7c6357
AV		 3323 }
3324
3325 return rval;
3326}
3327
db64e930
JC		 3328int
3329qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data)
3330{
3331 int rval;
3332 mbx_cmd_t mc;
3333 mbx_cmd_t *mcp = &mc;
3334
f299c7c2
JC		 3335 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3336 !IS_QLA27XX(vha->hw))
db64e930
JC		 3337 return QLA_FUNCTION_FAILED;
3338
3339 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
3340 "Entered %s.\n", __func__);
3341
3342 mcp->mb[0] = MBC_WRITE_SERDES;
3343 mcp->mb[1] = addr;
064135e0
AV		 3344 if (IS_QLA2031(vha->hw))
3345 mcp->mb[2] = data & 0xff;
3346 else
3347 mcp->mb[2] = data;
3348
db64e930
JC		 3349 mcp->mb[3] = 0;
3350 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
3351 mcp->in_mb = MBX_0;
3352 mcp->tov = MBX_TOV_SECONDS;
3353 mcp->flags = 0;
3354 rval = qla2x00_mailbox_command(vha, mcp);
3355
3356 if (rval != QLA_SUCCESS) {
3357 ql_dbg(ql_dbg_mbx, vha, 0x1183,
3358 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3359 } else {
3360 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184,
3361 "Done %s.\n", __func__);
3362 }
3363
3364 return rval;
3365}
3366
3367int
3368qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data)
3369{
3370 int rval;
3371 mbx_cmd_t mc;
3372 mbx_cmd_t *mcp = &mc;
3373
f299c7c2
JC		 3374 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3375 !IS_QLA27XX(vha->hw))
db64e930
JC		 3376 return QLA_FUNCTION_FAILED;
3377
3378 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
3379 "Entered %s.\n", __func__);
3380
3381 mcp->mb[0] = MBC_READ_SERDES;
3382 mcp->mb[1] = addr;
3383 mcp->mb[3] = 0;
3384 mcp->out_mb = MBX_3|MBX_1|MBX_0;
3385 mcp->in_mb = MBX_1|MBX_0;
3386 mcp->tov = MBX_TOV_SECONDS;
3387 mcp->flags = 0;
3388 rval = qla2x00_mailbox_command(vha, mcp);
3389
064135e0
AV		 3390 if (IS_QLA2031(vha->hw))
3391 *data = mcp->mb[1] & 0xff;
3392 else
3393 *data = mcp->mb[1];
db64e930
JC		 3394
3395 if (rval != QLA_SUCCESS) {
3396 ql_dbg(ql_dbg_mbx, vha, 0x1186,
3397 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3398 } else {
3399 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187,
3400 "Done %s.\n", __func__);
3401 }
3402
3403 return rval;
3404}
3405
e8887c51
JC		 3406int
3407qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
3408{
3409 int rval;
3410 mbx_cmd_t mc;
3411 mbx_cmd_t *mcp = &mc;
3412
3413 if (!IS_QLA8044(vha->hw))
3414 return QLA_FUNCTION_FAILED;
3415
83548fe2 3416 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x11a0,
e8887c51
JC		 3417 "Entered %s.\n", __func__);
3418
3419 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3420 mcp->mb[1] = HCS_WRITE_SERDES;
3421 mcp->mb[3] = LSW(addr);
3422 mcp->mb[4] = MSW(addr);
3423 mcp->mb[5] = LSW(data);
3424 mcp->mb[6] = MSW(data);
3425 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0;
3426 mcp->in_mb = MBX_0;
3427 mcp->tov = MBX_TOV_SECONDS;
3428 mcp->flags = 0;
3429 rval = qla2x00_mailbox_command(vha, mcp);
3430
3431 if (rval != QLA_SUCCESS) {
83548fe2 3432 ql_dbg(ql_dbg_mbx, vha, 0x11a1,
e8887c51
JC		 3433 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3434 } else {
3435 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188,
3436 "Done %s.\n", __func__);
3437 }
3438
3439 return rval;
3440}
3441
3442int
3443qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
3444{
3445 int rval;
3446 mbx_cmd_t mc;
3447 mbx_cmd_t *mcp = &mc;
3448
3449 if (!IS_QLA8044(vha->hw))
3450 return QLA_FUNCTION_FAILED;
3451
3452 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189,
3453 "Entered %s.\n", __func__);
3454
3455 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3456 mcp->mb[1] = HCS_READ_SERDES;
3457 mcp->mb[3] = LSW(addr);
3458 mcp->mb[4] = MSW(addr);
3459 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0;
3460 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3461 mcp->tov = MBX_TOV_SECONDS;
3462 mcp->flags = 0;
3463 rval = qla2x00_mailbox_command(vha, mcp);
3464
3465 *data = mcp->mb[2] << 16 | mcp->mb[1];
3466
3467 if (rval != QLA_SUCCESS) {
3468 ql_dbg(ql_dbg_mbx, vha, 0x118a,
3469 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3470 } else {
3471 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b,
3472 "Done %s.\n", __func__);
3473 }
3474
3475 return rval;
3476}
3477
1c7c6357
AV		 3478/**
3479 * qla2x00_set_serdes_params() -
2db6228d 3480 * @vha: HA context
807eb907
BVA		 3481 * @sw_em_1g: serial link options
3482 * @sw_em_2g: serial link options
3483 * @sw_em_4g: serial link options
1c7c6357
AV		 3484 *
3485 * Returns
3486 */
3487int
7b867cf7 3488qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
1c7c6357
AV		 3489 uint16_t sw_em_2g, uint16_t sw_em_4g)
3490{
3491 int rval;
3492 mbx_cmd_t mc;
3493 mbx_cmd_t *mcp = &mc;
3494
5f28d2d7
SK		 3495 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
3496 "Entered %s.\n", __func__);
1c7c6357
AV		 3497
3498 mcp->mb[0] = MBC_SERDES_PARAMS;
3499 mcp->mb[1] = BIT_0;
fdbc6833 3500 mcp->mb[2] = sw_em_1g | BIT_15;
3501 mcp->mb[3] = sw_em_2g | BIT_15;
3502 mcp->mb[4] = sw_em_4g | BIT_15;
1c7c6357
AV		 3503 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3504 mcp->in_mb = MBX_0;
b93480e3 3505 mcp->tov = MBX_TOV_SECONDS;
1c7c6357 3506 mcp->flags = 0;
7b867cf7 3507 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 3508
3509 if (rval != QLA_SUCCESS) {
3510 /*EMPTY*/
7c3df132
SK		 3511 ql_dbg(ql_dbg_mbx, vha, 0x109f,
3512 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357
AV		 3513 } else {
3514 /*EMPTY*/
5f28d2d7
SK		 3515 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
3516 "Done %s.\n", __func__);
1c7c6357
AV		 3517 }
3518
3519 return rval;
3520}
f6ef3b18
AV		 3521
3522int
7b867cf7 3523qla2x00_stop_firmware(scsi_qla_host_t *vha)
f6ef3b18
AV		 3524{
3525 int rval;
3526 mbx_cmd_t mc;
3527 mbx_cmd_t *mcp = &mc;
3528
7b867cf7 3529 if (!IS_FWI2_CAPABLE(vha->hw))
f6ef3b18
AV		 3530 return QLA_FUNCTION_FAILED;
3531
5f28d2d7
SK		 3532 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
3533 "Entered %s.\n", __func__);
f6ef3b18
AV		 3534
3535 mcp->mb[0] = MBC_STOP_FIRMWARE;
4ba988db
AV		 3536 mcp->mb[1] = 0;
3537 mcp->out_mb = MBX_1|MBX_0;
f6ef3b18
AV		 3538 mcp->in_mb = MBX_0;
3539 mcp->tov = 5;
3540 mcp->flags = 0;
7b867cf7 3541 rval = qla2x00_mailbox_command(vha, mcp);
f6ef3b18
AV		 3542
3543 if (rval != QLA_SUCCESS) {
7c3df132 3544 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
b469a7cb
AV		 3545 if (mcp->mb[0] == MBS_INVALID_COMMAND)
3546 rval = QLA_INVALID_COMMAND;
f6ef3b18 3547 } else {
5f28d2d7
SK		 3548 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
3549 "Done %s.\n", __func__);
f6ef3b18
AV		 3550 }
3551
3552 return rval;
3553}
a7a167bf
AV		 3554
3555int
7b867cf7 3556qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
a7a167bf
AV		 3557 uint16_t buffers)
3558{
3559 int rval;
3560 mbx_cmd_t mc;
3561 mbx_cmd_t *mcp = &mc;
3562
5f28d2d7
SK		 3563 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
3564 "Entered %s.\n", __func__);
7c3df132 3565
7b867cf7 3566 if (!IS_FWI2_CAPABLE(vha->hw))
a7a167bf
AV		 3567 return QLA_FUNCTION_FAILED;
3568
85880801
AV		 3569 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3570 return QLA_FUNCTION_FAILED;
3571
a7a167bf 3572 mcp->mb[0] = MBC_TRACE_CONTROL;
00b6bd25
AV		 3573 mcp->mb[1] = TC_EFT_ENABLE;
3574 mcp->mb[2] = LSW(eft_dma);
3575 mcp->mb[3] = MSW(eft_dma);
3576 mcp->mb[4] = LSW(MSD(eft_dma));
3577 mcp->mb[5] = MSW(MSD(eft_dma));
3578 mcp->mb[6] = buffers;
3579 mcp->mb[7] = TC_AEN_DISABLE;
3580 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
a7a167bf 3581 mcp->in_mb = MBX_1|MBX_0;
b93480e3 3582 mcp->tov = MBX_TOV_SECONDS;
a7a167bf 3583 mcp->flags = 0;
7b867cf7 3584 rval = qla2x00_mailbox_command(vha, mcp);
00b6bd25 3585 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3586 ql_dbg(ql_dbg_mbx, vha, 0x10a5,
3587 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3588 rval, mcp->mb[0], mcp->mb[1]);
00b6bd25 3589 } else {
5f28d2d7
SK		 3590 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
3591 "Done %s.\n", __func__);
00b6bd25
AV		 3592 }
3593
3594 return rval;
3595}
a7a167bf 3596
00b6bd25 3597int
7b867cf7 3598qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
00b6bd25
AV		 3599{
3600 int rval;
3601 mbx_cmd_t mc;
3602 mbx_cmd_t *mcp = &mc;
3603
5f28d2d7
SK		 3604 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
3605 "Entered %s.\n", __func__);
7c3df132 3606
7b867cf7 3607 if (!IS_FWI2_CAPABLE(vha->hw))
00b6bd25
AV		 3608 return QLA_FUNCTION_FAILED;
3609
85880801
AV		 3610 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3611 return QLA_FUNCTION_FAILED;
3612
00b6bd25
AV		 3613 mcp->mb[0] = MBC_TRACE_CONTROL;
3614 mcp->mb[1] = TC_EFT_DISABLE;
3615 mcp->out_mb = MBX_1|MBX_0;
3616 mcp->in_mb = MBX_1|MBX_0;
b93480e3 3617 mcp->tov = MBX_TOV_SECONDS;
00b6bd25 3618 mcp->flags = 0;
7b867cf7 3619 rval = qla2x00_mailbox_command(vha, mcp);
a7a167bf 3620 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3621 ql_dbg(ql_dbg_mbx, vha, 0x10a8,
3622 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3623 rval, mcp->mb[0], mcp->mb[1]);
a7a167bf 3624 } else {
5f28d2d7
SK		 3625 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
3626 "Done %s.\n", __func__);
a7a167bf
AV		 3627 }
3628
3629 return rval;
3630}
3631
df613b96 3632int
7b867cf7 3633qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
df613b96
AV		 3634 uint16_t buffers, uint16_t *mb, uint32_t *dwords)
3635{
3636 int rval;
3637 mbx_cmd_t mc;
3638 mbx_cmd_t *mcp = &mc;
3639
5f28d2d7
SK		 3640 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
3641 "Entered %s.\n", __func__);
7c3df132 3642
6246b8a1 3643 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
f73cb695 3644 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
df613b96
AV		 3645 return QLA_FUNCTION_FAILED;
3646
85880801
AV		 3647 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3648 return QLA_FUNCTION_FAILED;
3649
df613b96
AV		 3650 mcp->mb[0] = MBC_TRACE_CONTROL;
3651 mcp->mb[1] = TC_FCE_ENABLE;
3652 mcp->mb[2] = LSW(fce_dma);
3653 mcp->mb[3] = MSW(fce_dma);
3654 mcp->mb[4] = LSW(MSD(fce_dma));
3655 mcp->mb[5] = MSW(MSD(fce_dma));
3656 mcp->mb[6] = buffers;
3657 mcp->mb[7] = TC_AEN_DISABLE;
3658 mcp->mb[8] = 0;
3659 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
3660 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
3661 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3662 MBX_1|MBX_0;
3663 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 3664 mcp->tov = MBX_TOV_SECONDS;
df613b96 3665 mcp->flags = 0;
7b867cf7 3666 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 3667 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3668 ql_dbg(ql_dbg_mbx, vha, 0x10ab,
3669 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3670 rval, mcp->mb[0], mcp->mb[1]);
df613b96 3671 } else {
5f28d2d7
SK		 3672 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
3673 "Done %s.\n", __func__);
df613b96
AV		 3674
3675 if (mb)
3676 memcpy(mb, mcp->mb, 8 * sizeof(*mb));
3677 if (dwords)
fa0926df 3678 *dwords = buffers;
df613b96
AV		 3679 }
3680
3681 return rval;
3682}
3683
3684int
7b867cf7 3685qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
df613b96
AV		 3686{
3687 int rval;
3688 mbx_cmd_t mc;
3689 mbx_cmd_t *mcp = &mc;
3690
5f28d2d7
SK		 3691 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
3692 "Entered %s.\n", __func__);
7c3df132 3693
7b867cf7 3694 if (!IS_FWI2_CAPABLE(vha->hw))
df613b96
AV		 3695 return QLA_FUNCTION_FAILED;
3696
85880801
AV		 3697 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3698 return QLA_FUNCTION_FAILED;
3699
df613b96
AV		 3700 mcp->mb[0] = MBC_TRACE_CONTROL;
3701 mcp->mb[1] = TC_FCE_DISABLE;
3702 mcp->mb[2] = TC_FCE_DISABLE_TRACE;
3703 mcp->out_mb = MBX_2|MBX_1|MBX_0;
3704 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3705 MBX_1|MBX_0;
b93480e3 3706 mcp->tov = MBX_TOV_SECONDS;
df613b96 3707 mcp->flags = 0;
7b867cf7 3708 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 3709 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3710 ql_dbg(ql_dbg_mbx, vha, 0x10ae,
3711 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3712 rval, mcp->mb[0], mcp->mb[1]);
df613b96 3713 } else {
5f28d2d7
SK		 3714 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
3715 "Done %s.\n", __func__);
df613b96
AV		 3716
3717 if (wr)
3718 *wr = (uint64_t) mcp->mb[5] << 48 |
3719 (uint64_t) mcp->mb[4] << 32 |
3720 (uint64_t) mcp->mb[3] << 16 |
3721 (uint64_t) mcp->mb[2];
3722 if (rd)
3723 *rd = (uint64_t) mcp->mb[9] << 48 |
3724 (uint64_t) mcp->mb[8] << 32 |
3725 (uint64_t) mcp->mb[7] << 16 |
3726 (uint64_t) mcp->mb[6];
3727 }
3728
3729 return rval;
3730}
3731
6e98016c
GM		 3732int
3733qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3734 uint16_t *port_speed, uint16_t *mb)
3735{
3736 int rval;
3737 mbx_cmd_t mc;
3738 mbx_cmd_t *mcp = &mc;
3739
5f28d2d7
SK		 3740 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
3741 "Entered %s.\n", __func__);
7c3df132 3742
6e98016c
GM		 3743 if (!IS_IIDMA_CAPABLE(vha->hw))
3744 return QLA_FUNCTION_FAILED;
3745
6e98016c
GM		 3746 mcp->mb[0] = MBC_PORT_PARAMS;
3747 mcp->mb[1] = loop_id;
3748 mcp->mb[2] = mcp->mb[3] = 0;
3749 mcp->mb[9] = vha->vp_idx;
3750 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3751 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3752 mcp->tov = MBX_TOV_SECONDS;
3753 mcp->flags = 0;
3754 rval = qla2x00_mailbox_command(vha, mcp);
3755
3756 /* Return mailbox statuses. */
3757 if (mb != NULL) {
3758 mb[0] = mcp->mb[0];
3759 mb[1] = mcp->mb[1];
3760 mb[3] = mcp->mb[3];
3761 }
3762
3763 if (rval != QLA_SUCCESS) {
7c3df132 3764 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
6e98016c 3765 } else {
5f28d2d7
SK		 3766 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
3767 "Done %s.\n", __func__);
6e98016c
GM		 3768 if (port_speed)
3769 *port_speed = mcp->mb[3];
3770 }
3771
3772 return rval;
3773}
3774
d8b45213 3775int
7b867cf7 3776qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
d8b45213
AV		 3777 uint16_t port_speed, uint16_t *mb)
3778{
3779 int rval;
3780 mbx_cmd_t mc;
3781 mbx_cmd_t *mcp = &mc;
3782
5f28d2d7
SK		 3783 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
3784 "Entered %s.\n", __func__);
7c3df132 3785
7b867cf7 3786 if (!IS_IIDMA_CAPABLE(vha->hw))
d8b45213
AV		 3787 return QLA_FUNCTION_FAILED;
3788
d8b45213
AV		 3789 mcp->mb[0] = MBC_PORT_PARAMS;
3790 mcp->mb[1] = loop_id;
3791 mcp->mb[2] = BIT_0;
4c1458df 3792 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
1bb39548
HZ		 3793 mcp->mb[9] = vha->vp_idx;
3794 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3795 mcp->in_mb = MBX_3|MBX_1|MBX_0;
b93480e3 3796 mcp->tov = MBX_TOV_SECONDS;
d8b45213 3797 mcp->flags = 0;
7b867cf7 3798 rval = qla2x00_mailbox_command(vha, mcp);
d8b45213
AV		 3799
3800 /* Return mailbox statuses. */
3801 if (mb != NULL) {
3802 mb[0] = mcp->mb[0];
3803 mb[1] = mcp->mb[1];
3804 mb[3] = mcp->mb[3];
d8b45213
AV		 3805 }
3806
3807 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 3808 ql_dbg(ql_dbg_mbx, vha, 0x10b4,
3809 "Failed=%x.\n", rval);
d8b45213 3810 } else {
5f28d2d7
SK		 3811 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
3812 "Done %s.\n", __func__);
d8b45213
AV		 3813 }
3814
3815 return rval;
3816}
2c3dfe3f 3817
2c3dfe3f 3818void
7b867cf7 3819qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
2c3dfe3f
SJ		 3820 struct vp_rpt_id_entry_24xx *rptid_entry)
3821{
7b867cf7 3822 struct qla_hw_data *ha = vha->hw;
41dc529a 3823 scsi_qla_host_t *vp = NULL;
feafb7b1 3824 unsigned long flags;
4ac8d4ca 3825 int found;
482c9dc7 3826 port_id_t id;
9cd883f0 3827 struct fc_port *fcport;
2c3dfe3f 3828
5f28d2d7
SK		 3829 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
3830 "Entered %s.\n", __func__);
7c3df132 3831
2c3dfe3f
SJ		 3832 if (rptid_entry->entry_status != 0)
3833 return;
2c3dfe3f 3834
482c9dc7
QT		 3835 id.b.domain = rptid_entry->port_id[2];
3836 id.b.area = rptid_entry->port_id[1];
3837 id.b.al_pa = rptid_entry->port_id[0];
3838 id.b.rsvd_1 = 0;
1763c1fd 3839 ha->flags.n2n_ae = 0;
482c9dc7 3840
2c3dfe3f 3841 if (rptid_entry->format == 0) {
41dc529a 3842 /* loop */
ec7193e2 3843 ql_dbg(ql_dbg_async, vha, 0x10b7,
7c3df132 3844 "Format 0 : Number of VPs setup %d, number of "
41dc529a
QT		 3845 "VPs acquired %d.\n", rptid_entry->vp_setup,
3846 rptid_entry->vp_acquired);
ec7193e2 3847 ql_dbg(ql_dbg_async, vha, 0x10b8,
7c3df132
SK		 3848 "Primary port id %02x%02x%02x.\n",
3849 rptid_entry->port_id[2], rptid_entry->port_id[1],
3850 rptid_entry->port_id[0]);
9cd883f0 3851 ha->current_topology = ISP_CFG_NL;
482c9dc7 3852 qlt_update_host_map(vha, id);
41dc529a 3853
2c3dfe3f 3854 } else if (rptid_entry->format == 1) {
41dc529a 3855 /* fabric */
ec7193e2 3856 ql_dbg(ql_dbg_async, vha, 0x10b9,
7c3df132 3857 "Format 1: VP[%d] enabled - status %d - with "
41dc529a
QT		 3858 "port id %02x%02x%02x.\n", rptid_entry->vp_idx,
3859 rptid_entry->vp_status,
2c3dfe3f 3860 rptid_entry->port_id[2], rptid_entry->port_id[1],
7c3df132 3861 rptid_entry->port_id[0]);
edd05de1
DG		 3862 ql_dbg(ql_dbg_async, vha, 0x5075,
3863 "Format 1: Remote WWPN %8phC.\n",
3864 rptid_entry->u.f1.port_name);
3865
3866 ql_dbg(ql_dbg_async, vha, 0x5075,
3867 "Format 1: WWPN %8phC.\n",
3868 vha->port_name);
3869
8777e431
QT		 3870 switch (rptid_entry->u.f1.flags & TOPO_MASK) {
3871 case TOPO_N2N:
3872 ha->current_topology = ISP_CFG_N;
3873 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
3874 fcport = qla2x00_find_fcport_by_wwpn(vha,
3875 rptid_entry->u.f1.port_name, 1);
3876 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
3877
3878 if (fcport) {
3879 fcport->plogi_nack_done_deadline = jiffies + HZ;
3880 fcport->dm_login_expire = jiffies + 3*HZ;
3881 fcport->scan_state = QLA_FCPORT_FOUND;
3882 switch (fcport->disc_state) {
3883 case DSC_DELETED:
3884 set_bit(RELOGIN_NEEDED,
3885 &vha->dpc_flags);
3886 break;
3887 case DSC_DELETE_PEND:
3888 break;
3889 default:
3890 qlt_schedule_sess_for_deletion(fcport);
3891 break;
3892 }
edd05de1 3893 } else {
8777e431
QT		 3894 id.b24 = 0;
3895 if (wwn_to_u64(vha->port_name) >
3896 wwn_to_u64(rptid_entry->u.f1.port_name)) {
3897 vha->d_id.b24 = 0;
3898 vha->d_id.b.al_pa = 1;
3899 ha->flags.n2n_bigger = 1;
3900
3901 id.b.al_pa = 2;
3902 ql_dbg(ql_dbg_async, vha, 0x5075,
3903 "Format 1: assign local id %x remote id %x\n",
3904 vha->d_id.b24, id.b24);
3905 } else {
3906 ql_dbg(ql_dbg_async, vha, 0x5075,
3907 "Format 1: Remote login - Waiting for WWPN %8phC.\n",
3908 rptid_entry->u.f1.port_name);
3909 ha->flags.n2n_bigger = 0;
3910 }
3911 qla24xx_post_newsess_work(vha, &id,
3912 rptid_entry->u.f1.port_name,
3913 rptid_entry->u.f1.node_name,
3914 NULL,
3915 FC4_TYPE_UNKNOWN);
edd05de1
DG		 3916 }
3917
8777e431
QT		 3918 /* if our portname is higher then initiate N2N login */
3919
edd05de1 3920 set_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags);
1763c1fd 3921 ha->flags.n2n_ae = 1;
edd05de1 3922 return;
8777e431
QT		 3923 break;
3924 case TOPO_FL:
3925 ha->current_topology = ISP_CFG_FL;
3926 break;
3927 case TOPO_F:
3928 ha->current_topology = ISP_CFG_F;
3929 break;
3930 default:
3931 break;
edd05de1 3932 }
531a82d1 3933
9cd883f0
QT		 3934 ha->flags.gpsc_supported = 1;
3935 ha->current_topology = ISP_CFG_F;
969a6199 3936 /* buffer to buffer credit flag */
41dc529a
QT		 3937 vha->flags.bbcr_enable = (rptid_entry->u.f1.bbcr & 0xf) != 0;
3938
3939 if (rptid_entry->vp_idx == 0) {
3940 if (rptid_entry->vp_status == VP_STAT_COMPL) {
3941 /* FA-WWN is only for physical port */
3942 if (qla_ini_mode_enabled(vha) &&
3943 ha->flags.fawwpn_enabled &&
3944 (rptid_entry->u.f1.flags &
fcc5b5cd 3945 BIT_6)) {
41dc529a
QT		 3946 memcpy(vha->port_name,
3947 rptid_entry->u.f1.port_name,
3948 WWN_SIZE);
3949 }
7c9c4766 3950
482c9dc7 3951 qlt_update_host_map(vha, id);
7c9c4766 3952 }
41dc529a 3953
41dc529a
QT		 3954 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
3955 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
3956 } else {
3957 if (rptid_entry->vp_status != VP_STAT_COMPL &&
3958 rptid_entry->vp_status != VP_STAT_ID_CHG) {
3959 ql_dbg(ql_dbg_mbx, vha, 0x10ba,
3960 "Could not acquire ID for VP[%d].\n",
3961 rptid_entry->vp_idx);
3962 return;
4ac8d4ca 3963 }
feafb7b1 3964
41dc529a
QT		 3965 found = 0;
3966 spin_lock_irqsave(&ha->vport_slock, flags);
3967 list_for_each_entry(vp, &ha->vp_list, list) {
3968 if (rptid_entry->vp_idx == vp->vp_idx) {
3969 found = 1;
3970 break;
3971 }
3972 }
3973 spin_unlock_irqrestore(&ha->vport_slock, flags);
2c3dfe3f 3974
41dc529a
QT		 3975 if (!found)
3976 return;
2c3dfe3f 3977
482c9dc7 3978 qlt_update_host_map(vp, id);
2c3dfe3f 3979
41dc529a
QT		 3980 /*
3981 * Cannot configure here as we are still sitting on the
3982 * response queue. Handle it in dpc context.
3983 */
3984 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
3985 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
3986 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
3987 }
531a82d1 3988 set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
7b867cf7 3989 qla2xxx_wake_dpc(vha);
41dc529a 3990 } else if (rptid_entry->format == 2) {
83548fe2 3991 ql_dbg(ql_dbg_async, vha, 0x505f,
41dc529a
QT		 3992 "RIDA: format 2/N2N Primary port id %02x%02x%02x.\n",
3993 rptid_entry->port_id[2], rptid_entry->port_id[1],
3994 rptid_entry->port_id[0]);
3995
83548fe2 3996 ql_dbg(ql_dbg_async, vha, 0x5075,
41dc529a
QT		 3997 "N2N: Remote WWPN %8phC.\n",
3998 rptid_entry->u.f2.port_name);
3999
4000 /* N2N. direct connect */
9cd883f0
QT		 4001 ha->current_topology = ISP_CFG_N;
4002 ha->flags.rida_fmt2 = 1;
41dc529a
QT		 4003 vha->d_id.b.domain = rptid_entry->port_id[2];
4004 vha->d_id.b.area = rptid_entry->port_id[1];
4005 vha->d_id.b.al_pa = rptid_entry->port_id[0];
4006
1763c1fd 4007 ha->flags.n2n_ae = 1;
41dc529a
QT		 4008 spin_lock_irqsave(&ha->vport_slock, flags);
4009 qlt_update_vp_map(vha, SET_AL_PA);
4010 spin_unlock_irqrestore(&ha->vport_slock, flags);
9cd883f0
QT		 4011
4012 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4013 fcport->scan_state = QLA_FCPORT_SCAN;
4014 }
4015
4016 fcport = qla2x00_find_fcport_by_wwpn(vha,
4017 rptid_entry->u.f2.port_name, 1);
4018
4019 if (fcport) {
23dd98a6 4020 fcport->login_retry = vha->hw->login_retry_count;
9cd883f0
QT		 4021 fcport->plogi_nack_done_deadline = jiffies + HZ;
4022 fcport->scan_state = QLA_FCPORT_FOUND;
9cd883f0 4023 }
2c3dfe3f
SJ		 4024 }
4025}
4026
4027/*
4028 * qla24xx_modify_vp_config
4029 * Change VP configuration for vha
4030 *
4031 * Input:
4032 * vha = adapter block pointer.
4033 *
4034 * Returns:
4035 * qla2xxx local function return status code.
4036 *
4037 * Context:
4038 * Kernel context.
4039 */
4040int
4041qla24xx_modify_vp_config(scsi_qla_host_t *vha)
4042{
4043 int rval;
4044 struct vp_config_entry_24xx *vpmod;
4045 dma_addr_t vpmod_dma;
7b867cf7
AC		 4046 struct qla_hw_data *ha = vha->hw;
4047 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f
SJ		 4048
4049 /* This can be called by the parent */
2c3dfe3f 4050
5f28d2d7
SK		 4051 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
4052 "Entered %s.\n", __func__);
7c3df132 4053
08eb7f45 4054 vpmod = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
2c3dfe3f 4055 if (!vpmod) {
7c3df132
SK		 4056 ql_log(ql_log_warn, vha, 0x10bc,
4057 "Failed to allocate modify VP IOCB.\n");
2c3dfe3f
SJ		 4058 return QLA_MEMORY_ALLOC_FAILED;
4059 }
4060
2c3dfe3f
SJ		 4061 vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
4062 vpmod->entry_count = 1;
4063 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
4064 vpmod->vp_count = 1;
4065 vpmod->vp_index1 = vha->vp_idx;
4066 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
2d70c103
NB		 4067
4068 qlt_modify_vp_config(vha, vpmod);
4069
2c3dfe3f
SJ		 4070 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
4071 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
4072 vpmod->entry_count = 1;
4073
7b867cf7 4074 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
2c3dfe3f 4075 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4076 ql_dbg(ql_dbg_mbx, vha, 0x10bd,
4077 "Failed to issue VP config IOCB (%x).\n", rval);
2c3dfe3f 4078 } else if (vpmod->comp_status != 0) {
7c3df132
SK		 4079 ql_dbg(ql_dbg_mbx, vha, 0x10be,
4080 "Failed to complete IOCB -- error status (%x).\n",
4081 vpmod->comp_status);
2c3dfe3f 4082 rval = QLA_FUNCTION_FAILED;
ad950360 4083 } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 4084 ql_dbg(ql_dbg_mbx, vha, 0x10bf,
4085 "Failed to complete IOCB -- completion status (%x).\n",
4086 le16_to_cpu(vpmod->comp_status));
2c3dfe3f
SJ		 4087 rval = QLA_FUNCTION_FAILED;
4088 } else {
4089 /* EMPTY */
5f28d2d7
SK		 4090 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
4091 "Done %s.\n", __func__);
2c3dfe3f
SJ		 4092 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
4093 }
7b867cf7 4094 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
2c3dfe3f
SJ		 4095
4096 return rval;
4097}
4098
2c3dfe3f
SJ		 4099/*
4100 * qla2x00_send_change_request
4101 * Receive or disable RSCN request from fabric controller
4102 *
4103 * Input:
4104 * ha = adapter block pointer
4105 * format = registration format:
4106 * 0 - Reserved
4107 * 1 - Fabric detected registration
4108 * 2 - N_port detected registration
4109 * 3 - Full registration
4110 * FF - clear registration
4111 * vp_idx = Virtual port index
4112 *
4113 * Returns:
4114 * qla2x00 local function return status code.
4115 *
4116 * Context:
4117 * Kernel Context
4118 */
4119
4120int
7b867cf7 4121qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
2c3dfe3f
SJ		 4122 uint16_t vp_idx)
4123{
4124 int rval;
4125 mbx_cmd_t mc;
4126 mbx_cmd_t *mcp = &mc;
4127
5f28d2d7
SK		 4128 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
4129 "Entered %s.\n", __func__);
7c3df132 4130
2c3dfe3f
SJ		 4131 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
4132 mcp->mb[1] = format;
4133 mcp->mb[9] = vp_idx;
4134 mcp->out_mb = MBX_9|MBX_1|MBX_0;
4135 mcp->in_mb = MBX_0|MBX_1;
4136 mcp->tov = MBX_TOV_SECONDS;
4137 mcp->flags = 0;
7b867cf7 4138 rval = qla2x00_mailbox_command(vha, mcp);
2c3dfe3f
SJ		 4139
4140 if (rval == QLA_SUCCESS) {
4141 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
4142 rval = BIT_1;
4143 }
4144 } else
4145 rval = BIT_1;
4146
4147 return rval;
4148}
338c9161
AV		 4149
4150int
7b867cf7 4151qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
338c9161
AV		 4152 uint32_t size)
4153{
4154 int rval;
4155 mbx_cmd_t mc;
4156 mbx_cmd_t *mcp = &mc;
4157
5f28d2d7
SK		 4158 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
4159 "Entered %s.\n", __func__);
338c9161 4160
7b867cf7 4161 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 4162 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
4163 mcp->mb[8] = MSW(addr);
4164 mcp->out_mb = MBX_8|MBX_0;
4165 } else {
4166 mcp->mb[0] = MBC_DUMP_RISC_RAM;
4167 mcp->out_mb = MBX_0;
4168 }
4169 mcp->mb[1] = LSW(addr);
4170 mcp->mb[2] = MSW(req_dma);
4171 mcp->mb[3] = LSW(req_dma);
4172 mcp->mb[6] = MSW(MSD(req_dma));
4173 mcp->mb[7] = LSW(MSD(req_dma));
4174 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
7b867cf7 4175 if (IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 4176 mcp->mb[4] = MSW(size);
4177 mcp->mb[5] = LSW(size);
4178 mcp->out_mb |= MBX_5|MBX_4;
4179 } else {
4180 mcp->mb[4] = LSW(size);
4181 mcp->out_mb |= MBX_4;
4182 }
4183
4184 mcp->in_mb = MBX_0;
b93480e3 4185 mcp->tov = MBX_TOV_SECONDS;
338c9161 4186 mcp->flags = 0;
7b867cf7 4187 rval = qla2x00_mailbox_command(vha, mcp);
338c9161
AV		 4188
4189 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4190 ql_dbg(ql_dbg_mbx, vha, 0x1008,
4191 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
338c9161 4192 } else {
5f28d2d7
SK		 4193 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
4194 "Done %s.\n", __func__);
338c9161
AV		 4195 }
4196
4197 return rval;
4198}
4d4df193
HK		 4199/* 84XX Support **************************************************************/
4200
4201struct cs84xx_mgmt_cmd {
4202 union {
4203 struct verify_chip_entry_84xx req;
4204 struct verify_chip_rsp_84xx rsp;
4205 } p;
4206};
4207
4208int
7b867cf7 4209qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
4d4df193
HK		 4210{
4211 int rval, retry;
4212 struct cs84xx_mgmt_cmd *mn;
4213 dma_addr_t mn_dma;
4214 uint16_t options;
4215 unsigned long flags;
7b867cf7 4216 struct qla_hw_data *ha = vha->hw;
4d4df193 4217
5f28d2d7
SK		 4218 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
4219 "Entered %s.\n", __func__);
4d4df193
HK		 4220
4221 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
4222 if (mn == NULL) {
4d4df193
HK		 4223 return QLA_MEMORY_ALLOC_FAILED;
4224 }
4225
4226 /* Force Update? */
4227 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
4228 /* Diagnostic firmware? */
4229 /* options |= MENLO_DIAG_FW; */
4230 /* We update the firmware with only one data sequence. */
4231 options |= VCO_END_OF_DATA;
4232
4d4df193 4233 do {
c1ec1f1b 4234 retry = 0;
4d4df193
HK		 4235 memset(mn, 0, sizeof(*mn));
4236 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
4237 mn->p.req.entry_count = 1;
4238 mn->p.req.options = cpu_to_le16(options);
4239
7c3df132
SK		 4240 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
4241 "Dump of Verify Request.\n");
4242 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
4243 (uint8_t *)mn, sizeof(*mn));
4d4df193 4244
7b867cf7 4245 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
4d4df193 4246 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4247 ql_dbg(ql_dbg_mbx, vha, 0x10cb,
4248 "Failed to issue verify IOCB (%x).\n", rval);
4d4df193
HK		 4249 goto verify_done;
4250 }
4251
7c3df132
SK		 4252 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
4253 "Dump of Verify Response.\n");
4254 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
4255 (uint8_t *)mn, sizeof(*mn));
4d4df193
HK		 4256
4257 status[0] = le16_to_cpu(mn->p.rsp.comp_status);
4258 status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
4259 le16_to_cpu(mn->p.rsp.failure_code) : 0;
5f28d2d7 4260 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
7c3df132 4261 "cs=%x fc=%x.\n", status[0], status[1]);
4d4df193
HK		 4262
4263 if (status[0] != CS_COMPLETE) {
4264 rval = QLA_FUNCTION_FAILED;
4265 if (!(options & VCO_DONT_UPDATE_FW)) {
7c3df132
SK		 4266 ql_dbg(ql_dbg_mbx, vha, 0x10cf,
4267 "Firmware update failed. Retrying "
4268 "without update firmware.\n");
4d4df193
HK		 4269 options |= VCO_DONT_UPDATE_FW;
4270 options &= ~VCO_FORCE_UPDATE;
4271 retry = 1;
4272 }
4273 } else {
5f28d2d7 4274 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
7c3df132
SK		 4275 "Firmware updated to %x.\n",
4276 le32_to_cpu(mn->p.rsp.fw_ver));
4d4df193
HK		 4277
4278 /* NOTE: we only update OP firmware. */
4279 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
4280 ha->cs84xx->op_fw_version =
4281 le32_to_cpu(mn->p.rsp.fw_ver);
4282 spin_unlock_irqrestore(&ha->cs84xx->access_lock,
4283 flags);
4284 }
4285 } while (retry);
4286
4287verify_done:
4288 dma_pool_free(ha->s_dma_pool, mn, mn_dma);
4289
4290 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 4291 ql_dbg(ql_dbg_mbx, vha, 0x10d1,
4292 "Failed=%x.\n", rval);
4d4df193 4293 } else {
5f28d2d7
SK		 4294 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
4295 "Done %s.\n", __func__);
4d4df193
HK		 4296 }
4297
4298 return rval;
4299}
73208dfd
AC		 4300
4301int
618a7523 4302qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
73208dfd
AC		 4303{
4304 int rval;
4305 unsigned long flags;
4306 mbx_cmd_t mc;
4307 mbx_cmd_t *mcp = &mc;
73208dfd
AC		 4308 struct qla_hw_data *ha = vha->hw;
4309
45235022
QT		 4310 if (!ha->flags.fw_started)
4311 return QLA_SUCCESS;
4312
5f28d2d7
SK		 4313 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
4314 "Entered %s.\n", __func__);
7c3df132 4315
7c6300e3
JC		 4316 if (IS_SHADOW_REG_CAPABLE(ha))
4317 req->options |= BIT_13;
4318
73208dfd 4319 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 4320 mcp->mb[1] = req->options;
73208dfd
AC		 4321 mcp->mb[2] = MSW(LSD(req->dma));
4322 mcp->mb[3] = LSW(LSD(req->dma));
4323 mcp->mb[6] = MSW(MSD(req->dma));
4324 mcp->mb[7] = LSW(MSD(req->dma));
4325 mcp->mb[5] = req->length;
4326 if (req->rsp)
4327 mcp->mb[10] = req->rsp->id;
4328 mcp->mb[12] = req->qos;
4329 mcp->mb[11] = req->vp_idx;
4330 mcp->mb[13] = req->rid;
f73cb695 4331 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 4332 mcp->mb[15] = 0;
73208dfd 4333
73208dfd
AC		 4334 mcp->mb[4] = req->id;
4335 /* que in ptr index */
4336 mcp->mb[8] = 0;
4337 /* que out ptr index */
7c6300e3 4338 mcp->mb[9] = *req->out_ptr = 0;
73208dfd
AC		 4339 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
4340 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4341 mcp->in_mb = MBX_0;
4342 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 4343 mcp->tov = MBX_TOV_SECONDS * 2;
4344
f73cb695 4345 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 4346 mcp->in_mb |= MBX_1;
ba4828b7 4347 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 4348 mcp->out_mb |= MBX_15;
4349 /* debug q create issue in SR-IOV */
4350 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4351 }
73208dfd
AC		 4352
4353 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 4354 if (!(req->options & BIT_0)) {
da9b1d5c 4355 WRT_REG_DWORD(req->req_q_in, 0);
29db41c3 4356 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
da9b1d5c 4357 WRT_REG_DWORD(req->req_q_out, 0);
73208dfd
AC		 4358 }
4359 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4360
17d98630 4361 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 4362 if (rval != QLA_SUCCESS) {
4363 ql_dbg(ql_dbg_mbx, vha, 0x10d4,
4364 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4365 } else {
5f28d2d7
SK		 4366 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
4367 "Done %s.\n", __func__);
7c3df132
SK		 4368 }
4369
73208dfd
AC		 4370 return rval;
4371}
4372
4373int
618a7523 4374qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
73208dfd
AC		 4375{
4376 int rval;
4377 unsigned long flags;
4378 mbx_cmd_t mc;
4379 mbx_cmd_t *mcp = &mc;
73208dfd
AC		 4380 struct qla_hw_data *ha = vha->hw;
4381
45235022
QT		 4382 if (!ha->flags.fw_started)
4383 return QLA_SUCCESS;
4384
5f28d2d7
SK		 4385 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
4386 "Entered %s.\n", __func__);
7c3df132 4387
7c6300e3
JC		 4388 if (IS_SHADOW_REG_CAPABLE(ha))
4389 rsp->options |= BIT_13;
4390
73208dfd 4391 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 4392 mcp->mb[1] = rsp->options;
73208dfd
AC		 4393 mcp->mb[2] = MSW(LSD(rsp->dma));
4394 mcp->mb[3] = LSW(LSD(rsp->dma));
4395 mcp->mb[6] = MSW(MSD(rsp->dma));
4396 mcp->mb[7] = LSW(MSD(rsp->dma));
4397 mcp->mb[5] = rsp->length;
444786d7 4398 mcp->mb[14] = rsp->msix->entry;
73208dfd 4399 mcp->mb[13] = rsp->rid;
f73cb695 4400 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 4401 mcp->mb[15] = 0;
73208dfd 4402
73208dfd
AC		 4403 mcp->mb[4] = rsp->id;
4404 /* que in ptr index */
7c6300e3 4405 mcp->mb[8] = *rsp->in_ptr = 0;
73208dfd
AC		 4406 /* que out ptr index */
4407 mcp->mb[9] = 0;
2afa19a9 4408 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
73208dfd
AC		 4409 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4410 mcp->in_mb = MBX_0;
4411 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 4412 mcp->tov = MBX_TOV_SECONDS * 2;
4413
4414 if (IS_QLA81XX(ha)) {
4415 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
4416 mcp->in_mb |= MBX_1;
f73cb695 4417 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 4418 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
4419 mcp->in_mb |= MBX_1;
4420 /* debug q create issue in SR-IOV */
4421 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4422 }
73208dfd
AC		 4423
4424 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 4425 if (!(rsp->options & BIT_0)) {
da9b1d5c 4426 WRT_REG_DWORD(rsp->rsp_q_out, 0);
b20f02e1 4427 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
da9b1d5c 4428 WRT_REG_DWORD(rsp->rsp_q_in, 0);
73208dfd
AC		 4429 }
4430
4431 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4432
17d98630 4433 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 4434 if (rval != QLA_SUCCESS) {
4435 ql_dbg(ql_dbg_mbx, vha, 0x10d7,
4436 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4437 } else {
5f28d2d7
SK		 4438 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
4439 "Done %s.\n", __func__);
7c3df132
SK		 4440 }
4441
73208dfd
AC		 4442 return rval;
4443}
4444
8a659571
AV		 4445int
4446qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
4447{
4448 int rval;
4449 mbx_cmd_t mc;
4450 mbx_cmd_t *mcp = &mc;
4451
5f28d2d7
SK		 4452 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
4453 "Entered %s.\n", __func__);
8a659571
AV		 4454
4455 mcp->mb[0] = MBC_IDC_ACK;
4456 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4457 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4458 mcp->in_mb = MBX_0;
4459 mcp->tov = MBX_TOV_SECONDS;
4460 mcp->flags = 0;
4461 rval = qla2x00_mailbox_command(vha, mcp);
4462
4463 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4464 ql_dbg(ql_dbg_mbx, vha, 0x10da,
4465 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
8a659571 4466 } else {
5f28d2d7
SK		 4467 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
4468 "Done %s.\n", __func__);
8a659571
AV		 4469 }
4470
4471 return rval;
4472}
1d2874de
JC		 4473
4474int
4475qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
4476{
4477 int rval;
4478 mbx_cmd_t mc;
4479 mbx_cmd_t *mcp = &mc;
4480
5f28d2d7
SK		 4481 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
4482 "Entered %s.\n", __func__);
7c3df132 4483
f73cb695
CD		 4484 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4485 !IS_QLA27XX(vha->hw))
1d2874de
JC		 4486 return QLA_FUNCTION_FAILED;
4487
1d2874de
JC		 4488 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4489 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
4490 mcp->out_mb = MBX_1|MBX_0;
4491 mcp->in_mb = MBX_1|MBX_0;
4492 mcp->tov = MBX_TOV_SECONDS;
4493 mcp->flags = 0;
4494 rval = qla2x00_mailbox_command(vha, mcp);
4495
4496 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4497 ql_dbg(ql_dbg_mbx, vha, 0x10dd,
4498 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4499 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 4500 } else {
5f28d2d7
SK		 4501 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
4502 "Done %s.\n", __func__);
1d2874de
JC		 4503 *sector_size = mcp->mb[1];
4504 }
4505
4506 return rval;
4507}
4508
4509int
4510qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
4511{
4512 int rval;
4513 mbx_cmd_t mc;
4514 mbx_cmd_t *mcp = &mc;
4515
f73cb695
CD		 4516 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4517 !IS_QLA27XX(vha->hw))
1d2874de
JC		 4518 return QLA_FUNCTION_FAILED;
4519
5f28d2d7
SK		 4520 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
4521 "Entered %s.\n", __func__);
1d2874de
JC		 4522
4523 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4524 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
4525 FAC_OPT_CMD_WRITE_PROTECT;
4526 mcp->out_mb = MBX_1|MBX_0;
4527 mcp->in_mb = MBX_1|MBX_0;
4528 mcp->tov = MBX_TOV_SECONDS;
4529 mcp->flags = 0;
4530 rval = qla2x00_mailbox_command(vha, mcp);
4531
4532 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4533 ql_dbg(ql_dbg_mbx, vha, 0x10e0,
4534 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4535 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 4536 } else {
5f28d2d7
SK		 4537 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
4538 "Done %s.\n", __func__);
1d2874de
JC		 4539 }
4540
4541 return rval;
4542}
4543
4544int
4545qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
4546{
4547 int rval;
4548 mbx_cmd_t mc;
4549 mbx_cmd_t *mcp = &mc;
4550
f73cb695
CD		 4551 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4552 !IS_QLA27XX(vha->hw))
1d2874de
JC		 4553 return QLA_FUNCTION_FAILED;
4554
5f28d2d7
SK		 4555 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
4556 "Entered %s.\n", __func__);
1d2874de
JC		 4557
4558 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4559 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
4560 mcp->mb[2] = LSW(start);
4561 mcp->mb[3] = MSW(start);
4562 mcp->mb[4] = LSW(finish);
4563 mcp->mb[5] = MSW(finish);
4564 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4565 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4566 mcp->tov = MBX_TOV_SECONDS;
4567 mcp->flags = 0;
4568 rval = qla2x00_mailbox_command(vha, mcp);
4569
4570 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4571 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
4572 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4573 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1d2874de 4574 } else {
5f28d2d7
SK		 4575 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
4576 "Done %s.\n", __func__);
1d2874de
JC		 4577 }
4578
4579 return rval;
4580}
6e181be5
LC		 4581
4582int
4583qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
4584{
4585 int rval = 0;
4586 mbx_cmd_t mc;
4587 mbx_cmd_t *mcp = &mc;
4588
5f28d2d7
SK		 4589 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
4590 "Entered %s.\n", __func__);
6e181be5
LC		 4591
4592 mcp->mb[0] = MBC_RESTART_MPI_FW;
4593 mcp->out_mb = MBX_0;
4594 mcp->in_mb = MBX_0|MBX_1;
4595 mcp->tov = MBX_TOV_SECONDS;
4596 mcp->flags = 0;
4597 rval = qla2x00_mailbox_command(vha, mcp);
4598
4599 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4600 ql_dbg(ql_dbg_mbx, vha, 0x10e6,
4601 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4602 rval, mcp->mb[0], mcp->mb[1]);
6e181be5 4603 } else {
5f28d2d7
SK		 4604 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
4605 "Done %s.\n", __func__);
6e181be5
LC		 4606 }
4607
4608 return rval;
4609}
ad0ecd61 4610
c46e65c7
JC		 4611int
4612qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4613{
4614 int rval;
4615 mbx_cmd_t mc;
4616 mbx_cmd_t *mcp = &mc;
4617 int i;
4618 int len;
4619 uint16_t *str;
4620 struct qla_hw_data *ha = vha->hw;
4621
4622 if (!IS_P3P_TYPE(ha))
4623 return QLA_FUNCTION_FAILED;
4624
4625 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
4626 "Entered %s.\n", __func__);
4627
4628 str = (void *)version;
4629 len = strlen(version);
4630
4631 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4632 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
4633 mcp->out_mb = MBX_1|MBX_0;
4634 for (i = 4; i < 16 && len; i++, str++, len -= 2) {
4635 mcp->mb[i] = cpu_to_le16p(str);
4636 mcp->out_mb |= 1<<i;
4637 }
4638 for (; i < 16; i++) {
4639 mcp->mb[i] = 0;
4640 mcp->out_mb |= 1<<i;
4641 }
4642 mcp->in_mb = MBX_1|MBX_0;
4643 mcp->tov = MBX_TOV_SECONDS;
4644 mcp->flags = 0;
4645 rval = qla2x00_mailbox_command(vha, mcp);
4646
4647 if (rval != QLA_SUCCESS) {
4648 ql_dbg(ql_dbg_mbx, vha, 0x117c,
4649 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4650 } else {
4651 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d,
4652 "Done %s.\n", __func__);
4653 }
4654
4655 return rval;
4656}
4657
4658int
4659qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4660{
4661 int rval;
4662 mbx_cmd_t mc;
4663 mbx_cmd_t *mcp = &mc;
4664 int len;
4665 uint16_t dwlen;
4666 uint8_t *str;
4667 dma_addr_t str_dma;
4668 struct qla_hw_data *ha = vha->hw;
4669
4670 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) ||
4671 IS_P3P_TYPE(ha))
4672 return QLA_FUNCTION_FAILED;
4673
4674 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e,
4675 "Entered %s.\n", __func__);
4676
4677 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
4678 if (!str) {
4679 ql_log(ql_log_warn, vha, 0x117f,
4680 "Failed to allocate driver version param.\n");
4681 return QLA_MEMORY_ALLOC_FAILED;
4682 }
4683
4684 memcpy(str, "\x7\x3\x11\x0", 4);
4685 dwlen = str[0];
4686 len = dwlen * 4 - 4;
4687 memset(str + 4, 0, len);
4688 if (len > strlen(version))
4689 len = strlen(version);
4690 memcpy(str + 4, version, len);
4691
4692 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4693 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
4694 mcp->mb[2] = MSW(LSD(str_dma));
4695 mcp->mb[3] = LSW(LSD(str_dma));
4696 mcp->mb[6] = MSW(MSD(str_dma));
4697 mcp->mb[7] = LSW(MSD(str_dma));
4698 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4699 mcp->in_mb = MBX_1|MBX_0;
4700 mcp->tov = MBX_TOV_SECONDS;
4701 mcp->flags = 0;
4702 rval = qla2x00_mailbox_command(vha, mcp);
4703
4704 if (rval != QLA_SUCCESS) {
4705 ql_dbg(ql_dbg_mbx, vha, 0x1180,
4706 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4707 } else {
4708 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181,
4709 "Done %s.\n", __func__);
4710 }
4711
4712 dma_pool_free(ha->s_dma_pool, str, str_dma);
4713
4714 return rval;
4715}
4716
edd05de1
DG		 4717int
4718qla24xx_get_port_login_templ(scsi_qla_host_t *vha, dma_addr_t buf_dma,
4719 void *buf, uint16_t bufsiz)
4720{
4721 int rval, i;
4722 mbx_cmd_t mc;
4723 mbx_cmd_t *mcp = &mc;
4724 uint32_t *bp;
4725
4726 if (!IS_FWI2_CAPABLE(vha->hw))
4727 return QLA_FUNCTION_FAILED;
4728
4729 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4730 "Entered %s.\n", __func__);
4731
4732 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4733 mcp->mb[1] = RNID_TYPE_PORT_LOGIN << 8;
4734 mcp->mb[2] = MSW(buf_dma);
4735 mcp->mb[3] = LSW(buf_dma);
4736 mcp->mb[6] = MSW(MSD(buf_dma));
4737 mcp->mb[7] = LSW(MSD(buf_dma));
4738 mcp->mb[8] = bufsiz/4;
4739 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4740 mcp->in_mb = MBX_1|MBX_0;
4741 mcp->tov = MBX_TOV_SECONDS;
4742 mcp->flags = 0;
4743 rval = qla2x00_mailbox_command(vha, mcp);
4744
4745 if (rval != QLA_SUCCESS) {
4746 ql_dbg(ql_dbg_mbx, vha, 0x115a,
4747 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4748 } else {
4749 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
4750 "Done %s.\n", __func__);
4751 bp = (uint32_t *) buf;
4752 for (i = 0; i < (bufsiz-4)/4; i++, bp++)
8777e431 4753 *bp = le32_to_cpu(*bp);
edd05de1
DG		 4754 }
4755
4756 return rval;
4757}
4758
fe52f6e1
JC		 4759static int
4760qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
4761{
4762 int rval;
4763 mbx_cmd_t mc;
4764 mbx_cmd_t *mcp = &mc;
4765
4766 if (!IS_FWI2_CAPABLE(vha->hw))
4767 return QLA_FUNCTION_FAILED;
4768
4769 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4770 "Entered %s.\n", __func__);
4771
4772 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4773 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
4774 mcp->out_mb = MBX_1|MBX_0;
4775 mcp->in_mb = MBX_1|MBX_0;
4776 mcp->tov = MBX_TOV_SECONDS;
4777 mcp->flags = 0;
4778 rval = qla2x00_mailbox_command(vha, mcp);
4779 *temp = mcp->mb[1];
4780
4781 if (rval != QLA_SUCCESS) {
4782 ql_dbg(ql_dbg_mbx, vha, 0x115a,
4783 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4784 } else {
4785 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
4786 "Done %s.\n", __func__);
4787 }
4788
4789 return rval;
4790}
4791
ad0ecd61 4792int
6766df9e
JC		 4793qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4794 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 4795{
4796 int rval;
4797 mbx_cmd_t mc;
4798 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 4799 struct qla_hw_data *ha = vha->hw;
4800
5f28d2d7
SK		 4801 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
4802 "Entered %s.\n", __func__);
7c3df132 4803
6766df9e
JC		 4804 if (!IS_FWI2_CAPABLE(ha))
4805 return QLA_FUNCTION_FAILED;
ad0ecd61 4806
6766df9e
JC		 4807 if (len == 1)
4808 opt |= BIT_0;
4809
ad0ecd61
JC		 4810 mcp->mb[0] = MBC_READ_SFP;
4811 mcp->mb[1] = dev;
4812 mcp->mb[2] = MSW(sfp_dma);
4813 mcp->mb[3] = LSW(sfp_dma);
4814 mcp->mb[6] = MSW(MSD(sfp_dma));
4815 mcp->mb[7] = LSW(MSD(sfp_dma));
4816 mcp->mb[8] = len;
6766df9e 4817 mcp->mb[9] = off;
ad0ecd61
JC		 4818 mcp->mb[10] = opt;
4819 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1bff6cc8 4820 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 4821 mcp->tov = MBX_TOV_SECONDS;
4822 mcp->flags = 0;
4823 rval = qla2x00_mailbox_command(vha, mcp);
4824
4825 if (opt & BIT_0)
6766df9e 4826 *sfp = mcp->mb[1];
ad0ecd61
JC		 4827
4828 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4829 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
4830 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
e4e3a2ce
QT		 4831 if (mcp->mb[0] == MBS_COMMAND_ERROR &&
4832 mcp->mb[1] == 0x22)
4833 /* sfp is not there */
4834 rval = QLA_INTERFACE_ERROR;
ad0ecd61 4835 } else {
5f28d2d7
SK		 4836 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
4837 "Done %s.\n", __func__);
ad0ecd61
JC		 4838 }
4839
4840 return rval;
4841}
4842
4843int
6766df9e
JC		 4844qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4845 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 4846{
4847 int rval;
4848 mbx_cmd_t mc;
4849 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 4850 struct qla_hw_data *ha = vha->hw;
4851
5f28d2d7
SK		 4852 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
4853 "Entered %s.\n", __func__);
7c3df132 4854
6766df9e
JC		 4855 if (!IS_FWI2_CAPABLE(ha))
4856 return QLA_FUNCTION_FAILED;
ad0ecd61 4857
6766df9e
JC		 4858 if (len == 1)
4859 opt |= BIT_0;
4860
ad0ecd61 4861 if (opt & BIT_0)
6766df9e 4862 len = *sfp;
ad0ecd61
JC		 4863
4864 mcp->mb[0] = MBC_WRITE_SFP;
4865 mcp->mb[1] = dev;
4866 mcp->mb[2] = MSW(sfp_dma);
4867 mcp->mb[3] = LSW(sfp_dma);
4868 mcp->mb[6] = MSW(MSD(sfp_dma));
4869 mcp->mb[7] = LSW(MSD(sfp_dma));
4870 mcp->mb[8] = len;
6766df9e 4871 mcp->mb[9] = off;
ad0ecd61
JC		 4872 mcp->mb[10] = opt;
4873 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6766df9e 4874 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 4875 mcp->tov = MBX_TOV_SECONDS;
4876 mcp->flags = 0;
4877 rval = qla2x00_mailbox_command(vha, mcp);
4878
4879 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4880 ql_dbg(ql_dbg_mbx, vha, 0x10ec,
4881 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
ad0ecd61 4882 } else {
5f28d2d7
SK		 4883 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
4884 "Done %s.\n", __func__);
ad0ecd61
JC		 4885 }
4886
4887 return rval;
4888}
ce0423f4
AV		 4889
4890int
4891qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
4892 uint16_t size_in_bytes, uint16_t *actual_size)
4893{
4894 int rval;
4895 mbx_cmd_t mc;
4896 mbx_cmd_t *mcp = &mc;
4897
5f28d2d7
SK		 4898 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
4899 "Entered %s.\n", __func__);
7c3df132 4900
6246b8a1 4901 if (!IS_CNA_CAPABLE(vha->hw))
ce0423f4
AV		 4902 return QLA_FUNCTION_FAILED;
4903
ce0423f4
AV		 4904 mcp->mb[0] = MBC_GET_XGMAC_STATS;
4905 mcp->mb[2] = MSW(stats_dma);
4906 mcp->mb[3] = LSW(stats_dma);
4907 mcp->mb[6] = MSW(MSD(stats_dma));
4908 mcp->mb[7] = LSW(MSD(stats_dma));
4909 mcp->mb[8] = size_in_bytes >> 2;
4910 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
4911 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4912 mcp->tov = MBX_TOV_SECONDS;
4913 mcp->flags = 0;
4914 rval = qla2x00_mailbox_command(vha, mcp);
4915
4916 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4917 ql_dbg(ql_dbg_mbx, vha, 0x10ef,
4918 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4919 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
ce0423f4 4920 } else {
5f28d2d7
SK		 4921 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
4922 "Done %s.\n", __func__);
7c3df132 4923
ce0423f4
AV		 4924
4925 *actual_size = mcp->mb[2] << 2;
4926 }
4927
4928 return rval;
4929}
11bbc1d8
AV		 4930
4931int
4932qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
4933 uint16_t size)
4934{
4935 int rval;
4936 mbx_cmd_t mc;
4937 mbx_cmd_t *mcp = &mc;
4938
5f28d2d7
SK		 4939 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
4940 "Entered %s.\n", __func__);
7c3df132 4941
6246b8a1 4942 if (!IS_CNA_CAPABLE(vha->hw))
11bbc1d8
AV		 4943 return QLA_FUNCTION_FAILED;
4944
11bbc1d8
AV		 4945 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
4946 mcp->mb[1] = 0;
4947 mcp->mb[2] = MSW(tlv_dma);
4948 mcp->mb[3] = LSW(tlv_dma);
4949 mcp->mb[6] = MSW(MSD(tlv_dma));
4950 mcp->mb[7] = LSW(MSD(tlv_dma));
4951 mcp->mb[8] = size;
4952 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4953 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4954 mcp->tov = MBX_TOV_SECONDS;
4955 mcp->flags = 0;
4956 rval = qla2x00_mailbox_command(vha, mcp);
4957
4958 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4959 ql_dbg(ql_dbg_mbx, vha, 0x10f2,
4960 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4961 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
11bbc1d8 4962 } else {
5f28d2d7
SK		 4963 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
4964 "Done %s.\n", __func__);
11bbc1d8
AV		 4965 }
4966
4967 return rval;
4968}
18e7555a
AV		 4969
4970int
4971qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
4972{
4973 int rval;
4974 mbx_cmd_t mc;
4975 mbx_cmd_t *mcp = &mc;
4976
5f28d2d7
SK		 4977 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
4978 "Entered %s.\n", __func__);
7c3df132 4979
18e7555a
AV		 4980 if (!IS_FWI2_CAPABLE(vha->hw))
4981 return QLA_FUNCTION_FAILED;
4982
18e7555a
AV		 4983 mcp->mb[0] = MBC_READ_RAM_EXTENDED;
4984 mcp->mb[1] = LSW(risc_addr);
4985 mcp->mb[8] = MSW(risc_addr);
4986 mcp->out_mb = MBX_8|MBX_1|MBX_0;
4987 mcp->in_mb = MBX_3|MBX_2|MBX_0;
4988 mcp->tov = 30;
4989 mcp->flags = 0;
4990 rval = qla2x00_mailbox_command(vha, mcp);
4991 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4992 ql_dbg(ql_dbg_mbx, vha, 0x10f5,
4993 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 4994 } else {
5f28d2d7
SK		 4995 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
4996 "Done %s.\n", __func__);
18e7555a
AV		 4997 *data = mcp->mb[3] << 16 | mcp->mb[2];
4998 }
4999
5000 return rval;
5001}
5002
9a069e19 5003int
a9083016
GM		 5004qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
5005 uint16_t *mresp)
9a069e19
GM		 5006{
5007 int rval;
5008 mbx_cmd_t mc;
5009 mbx_cmd_t *mcp = &mc;
9a069e19 5010
5f28d2d7
SK		 5011 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
5012 "Entered %s.\n", __func__);
9a069e19
GM		 5013
5014 memset(mcp->mb, 0 , sizeof(mcp->mb));
5015 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
5016 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
5017
5018 /* transfer count */
5019 mcp->mb[10] = LSW(mreq->transfer_size);
5020 mcp->mb[11] = MSW(mreq->transfer_size);
5021
5022 /* send data address */
5023 mcp->mb[14] = LSW(mreq->send_dma);
5024 mcp->mb[15] = MSW(mreq->send_dma);
5025 mcp->mb[20] = LSW(MSD(mreq->send_dma));
5026 mcp->mb[21] = MSW(MSD(mreq->send_dma));
5027
25985edc 5028 /* receive data address */
9a069e19
GM		 5029 mcp->mb[16] = LSW(mreq->rcv_dma);
5030 mcp->mb[17] = MSW(mreq->rcv_dma);
5031 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
5032 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
5033
5034 /* Iteration count */
1b98b421
JC		 5035 mcp->mb[18] = LSW(mreq->iteration_count);
5036 mcp->mb[19] = MSW(mreq->iteration_count);
9a069e19
GM		 5037
5038 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
5039 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 5040 if (IS_CNA_CAPABLE(vha->hw))
9a069e19
GM		 5041 mcp->out_mb |= MBX_2;
5042 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
5043
5044 mcp->buf_size = mreq->transfer_size;
5045 mcp->tov = MBX_TOV_SECONDS;
5046 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5047
5048 rval = qla2x00_mailbox_command(vha, mcp);
5049
5050 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5051 ql_dbg(ql_dbg_mbx, vha, 0x10f8,
5052 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
5053 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
5054 mcp->mb[3], mcp->mb[18], mcp->mb[19]);
9a069e19 5055 } else {
5f28d2d7
SK		 5056 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
5057 "Done %s.\n", __func__);
9a069e19
GM		 5058 }
5059
5060 /* Copy mailbox information */
5061 memcpy( mresp, mcp->mb, 64);
9a069e19
GM		 5062 return rval;
5063}
5064
5065int
a9083016
GM		 5066qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
5067 uint16_t *mresp)
9a069e19
GM		 5068{
5069 int rval;
5070 mbx_cmd_t mc;
5071 mbx_cmd_t *mcp = &mc;
5072 struct qla_hw_data *ha = vha->hw;
5073
5f28d2d7
SK		 5074 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
5075 "Entered %s.\n", __func__);
9a069e19
GM		 5076
5077 memset(mcp->mb, 0 , sizeof(mcp->mb));
5078 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
1d634965
JC		 5079 /* BIT_6 specifies 64bit address */
5080 mcp->mb[1] = mreq->options | BIT_15 | BIT_6;
6246b8a1 5081 if (IS_CNA_CAPABLE(ha)) {
a9083016
GM		 5082 mcp->mb[2] = vha->fcoe_fcf_idx;
5083 }
9a069e19
GM		 5084 mcp->mb[16] = LSW(mreq->rcv_dma);
5085 mcp->mb[17] = MSW(mreq->rcv_dma);
5086 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
5087 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
5088
5089 mcp->mb[10] = LSW(mreq->transfer_size);
5090
5091 mcp->mb[14] = LSW(mreq->send_dma);
5092 mcp->mb[15] = MSW(mreq->send_dma);
5093 mcp->mb[20] = LSW(MSD(mreq->send_dma));
5094 mcp->mb[21] = MSW(MSD(mreq->send_dma));
5095
5096 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
5097 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 5098 if (IS_CNA_CAPABLE(ha))
9a069e19
GM		 5099 mcp->out_mb |= MBX_2;
5100
5101 mcp->in_mb = MBX_0;
6246b8a1
GM		 5102 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
5103 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
9a069e19 5104 mcp->in_mb |= MBX_1;
6246b8a1 5105 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
9a069e19
GM		 5106 mcp->in_mb |= MBX_3;
5107
5108 mcp->tov = MBX_TOV_SECONDS;
5109 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5110 mcp->buf_size = mreq->transfer_size;
5111
5112 rval = qla2x00_mailbox_command(vha, mcp);
5113
5114 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5115 ql_dbg(ql_dbg_mbx, vha, 0x10fb,
5116 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5117 rval, mcp->mb[0], mcp->mb[1]);
9a069e19 5118 } else {
5f28d2d7
SK		 5119 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
5120 "Done %s.\n", __func__);
9a069e19
GM		 5121 }
5122
5123 /* Copy mailbox information */
6dbdda4d 5124 memcpy(mresp, mcp->mb, 64);
9a069e19
GM		 5125 return rval;
5126}
6dbdda4d 5127
9a069e19 5128int
7c3df132 5129qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
9a069e19
GM		 5130{
5131 int rval;
5132 mbx_cmd_t mc;
5133 mbx_cmd_t *mcp = &mc;
5134
5f28d2d7 5135 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
7c3df132 5136 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
9a069e19
GM		 5137
5138 mcp->mb[0] = MBC_ISP84XX_RESET;
5139 mcp->mb[1] = enable_diagnostic;
5140 mcp->out_mb = MBX_1|MBX_0;
5141 mcp->in_mb = MBX_1|MBX_0;
5142 mcp->tov = MBX_TOV_SECONDS;
5143 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
7c3df132 5144 rval = qla2x00_mailbox_command(vha, mcp);
9a069e19 5145
9a069e19 5146 if (rval != QLA_SUCCESS)
7c3df132 5147 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
9a069e19 5148 else
5f28d2d7
SK		 5149 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
5150 "Done %s.\n", __func__);
9a069e19
GM		 5151
5152 return rval;
5153}
5154
18e7555a
AV		 5155int
5156qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
5157{
5158 int rval;
5159 mbx_cmd_t mc;
5160 mbx_cmd_t *mcp = &mc;
5161
5f28d2d7
SK		 5162 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
5163 "Entered %s.\n", __func__);
7c3df132 5164
18e7555a 5165 if (!IS_FWI2_CAPABLE(vha->hw))
6c452a45 5166 return QLA_FUNCTION_FAILED;
18e7555a 5167
18e7555a
AV		 5168 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
5169 mcp->mb[1] = LSW(risc_addr);
5170 mcp->mb[2] = LSW(data);
5171 mcp->mb[3] = MSW(data);
5172 mcp->mb[8] = MSW(risc_addr);
5173 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
5174 mcp->in_mb = MBX_0;
5175 mcp->tov = 30;
5176 mcp->flags = 0;
5177 rval = qla2x00_mailbox_command(vha, mcp);
5178 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5179 ql_dbg(ql_dbg_mbx, vha, 0x1101,
5180 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 5181 } else {
5f28d2d7
SK		 5182 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
5183 "Done %s.\n", __func__);
18e7555a
AV		 5184 }
5185
5186 return rval;
5187}
3064ff39 5188
b1d46989
MI		 5189int
5190qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
5191{
5192 int rval;
5193 uint32_t stat, timer;
5194 uint16_t mb0 = 0;
5195 struct qla_hw_data *ha = vha->hw;
5196 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
5197
5198 rval = QLA_SUCCESS;
5199
5f28d2d7
SK		 5200 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
5201 "Entered %s.\n", __func__);
b1d46989
MI		 5202
5203 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
5204
5205 /* Write the MBC data to the registers */
5206 WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
5207 WRT_REG_WORD(&reg->mailbox1, mb[0]);
5208 WRT_REG_WORD(&reg->mailbox2, mb[1]);
5209 WRT_REG_WORD(&reg->mailbox3, mb[2]);
5210 WRT_REG_WORD(&reg->mailbox4, mb[3]);
5211
5212 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
5213
5214 /* Poll for MBC interrupt */
5215 for (timer = 6000000; timer; timer--) {
5216 /* Check for pending interrupts. */
5217 stat = RD_REG_DWORD(&reg->host_status);
5218 if (stat & HSRX_RISC_INT) {
5219 stat &= 0xff;
5220
5221 if (stat == 0x1 || stat == 0x2 ||
5222 stat == 0x10 || stat == 0x11) {
5223 set_bit(MBX_INTERRUPT,
5224 &ha->mbx_cmd_flags);
5225 mb0 = RD_REG_WORD(&reg->mailbox0);
5226 WRT_REG_DWORD(&reg->hccr,
5227 HCCRX_CLR_RISC_INT);
5228 RD_REG_DWORD(&reg->hccr);
5229 break;
5230 }
5231 }
5232 udelay(5);
5233 }
5234
5235 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
5236 rval = mb0 & MBS_MASK;
5237 else
5238 rval = QLA_FUNCTION_FAILED;
5239
5240 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5241 ql_dbg(ql_dbg_mbx, vha, 0x1104,
5242 "Failed=%x mb[0]=%x.\n", rval, mb[0]);
b1d46989 5243 } else {
5f28d2d7
SK		 5244 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
5245 "Done %s.\n", __func__);
b1d46989
MI		 5246 }
5247
5248 return rval;
5249}
6246b8a1 5250
3064ff39
MH		 5251int
5252qla2x00_get_data_rate(scsi_qla_host_t *vha)
5253{
5254 int rval;
5255 mbx_cmd_t mc;
5256 mbx_cmd_t *mcp = &mc;
5257 struct qla_hw_data *ha = vha->hw;
5258
5f28d2d7
SK		 5259 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
5260 "Entered %s.\n", __func__);
7c3df132 5261
3064ff39
MH		 5262 if (!IS_FWI2_CAPABLE(ha))
5263 return QLA_FUNCTION_FAILED;
5264
3064ff39
MH		 5265 mcp->mb[0] = MBC_DATA_RATE;
5266 mcp->mb[1] = 0;
5267 mcp->out_mb = MBX_1|MBX_0;
5268 mcp->in_mb = MBX_2|MBX_1|MBX_0;
f73cb695 5269 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 5270 mcp->in_mb |= MBX_3;
3064ff39
MH		 5271 mcp->tov = MBX_TOV_SECONDS;
5272 mcp->flags = 0;
5273 rval = qla2x00_mailbox_command(vha, mcp);
5274 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5275 ql_dbg(ql_dbg_mbx, vha, 0x1107,
5276 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3064ff39 5277 } else {
5f28d2d7
SK		 5278 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
5279 "Done %s.\n", __func__);
3064ff39
MH		 5280 if (mcp->mb[1] != 0x7)
5281 ha->link_data_rate = mcp->mb[1];
5282 }
5283
5284 return rval;
5285}
09ff701a 5286
23f2ebd1
SR		 5287int
5288qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5289{
5290 int rval;
5291 mbx_cmd_t mc;
5292 mbx_cmd_t *mcp = &mc;
5293 struct qla_hw_data *ha = vha->hw;
5294
5f28d2d7
SK		 5295 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
5296 "Entered %s.\n", __func__);
23f2ebd1 5297
f73cb695
CD		 5298 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
5299 !IS_QLA27XX(ha))
23f2ebd1
SR		 5300 return QLA_FUNCTION_FAILED;
5301 mcp->mb[0] = MBC_GET_PORT_CONFIG;
5302 mcp->out_mb = MBX_0;
5303 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5304 mcp->tov = MBX_TOV_SECONDS;
5305 mcp->flags = 0;
5306
5307 rval = qla2x00_mailbox_command(vha, mcp);
5308
5309 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5310 ql_dbg(ql_dbg_mbx, vha, 0x110a,
5311 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1
SR		 5312 } else {
5313 /* Copy all bits to preserve original value */
5314 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
5315
5f28d2d7
SK		 5316 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
5317 "Done %s.\n", __func__);
23f2ebd1
SR		 5318 }
5319 return rval;
5320}
5321
5322int
5323qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5324{
5325 int rval;
5326 mbx_cmd_t mc;
5327 mbx_cmd_t *mcp = &mc;
5328
5f28d2d7
SK		 5329 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
5330 "Entered %s.\n", __func__);
23f2ebd1
SR		 5331
5332 mcp->mb[0] = MBC_SET_PORT_CONFIG;
5333 /* Copy all bits to preserve original setting */
5334 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
5335 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5336 mcp->in_mb = MBX_0;
5337 mcp->tov = MBX_TOV_SECONDS;
5338 mcp->flags = 0;
5339 rval = qla2x00_mailbox_command(vha, mcp);
5340
5341 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5342 ql_dbg(ql_dbg_mbx, vha, 0x110d,
5343 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1 5344 } else
5f28d2d7
SK		 5345 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
5346 "Done %s.\n", __func__);
23f2ebd1
SR		 5347
5348 return rval;
5349}
5350
5351
09ff701a
SR		 5352int
5353qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
5354 uint16_t *mb)
5355{
5356 int rval;
5357 mbx_cmd_t mc;
5358 mbx_cmd_t *mcp = &mc;
5359 struct qla_hw_data *ha = vha->hw;
5360
5f28d2d7
SK		 5361 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
5362 "Entered %s.\n", __func__);
7c3df132 5363
09ff701a
SR		 5364 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
5365 return QLA_FUNCTION_FAILED;
5366
09ff701a
SR		 5367 mcp->mb[0] = MBC_PORT_PARAMS;
5368 mcp->mb[1] = loop_id;
5369 if (ha->flags.fcp_prio_enabled)
5370 mcp->mb[2] = BIT_1;
5371 else
5372 mcp->mb[2] = BIT_2;
5373 mcp->mb[4] = priority & 0xf;
5374 mcp->mb[9] = vha->vp_idx;
5375 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5376 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5377 mcp->tov = 30;
5378 mcp->flags = 0;
5379 rval = qla2x00_mailbox_command(vha, mcp);
5380 if (mb != NULL) {
5381 mb[0] = mcp->mb[0];
5382 mb[1] = mcp->mb[1];
5383 mb[3] = mcp->mb[3];
5384 mb[4] = mcp->mb[4];
5385 }
5386
5387 if (rval != QLA_SUCCESS) {
7c3df132 5388 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
09ff701a 5389 } else {
5f28d2d7
SK		 5390 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
5391 "Done %s.\n", __func__);
09ff701a
SR		 5392 }
5393
5394 return rval;
5395}
a9083016 5396
794a5691 5397int
fe52f6e1 5398qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
794a5691 5399{
fe52f6e1 5400 int rval = QLA_FUNCTION_FAILED;
794a5691 5401 struct qla_hw_data *ha = vha->hw;
fe52f6e1 5402 uint8_t byte;
794a5691 5403
1ae47cf3
JC		 5404 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) {
5405 ql_dbg(ql_dbg_mbx, vha, 0x1150,
5406 "Thermal not supported by this card.\n");
5407 return rval;
5408 }
5409
5410 if (IS_QLA25XX(ha)) {
5411 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
5412 ha->pdev->subsystem_device == 0x0175) {
5413 rval = qla2x00_read_sfp(vha, 0, &byte,
5414 0x98, 0x1, 1, BIT_13|BIT_0);
5415 *temp = byte;
5416 return rval;
5417 }
5418 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
5419 ha->pdev->subsystem_device == 0x338e) {
5420 rval = qla2x00_read_sfp(vha, 0, &byte,
5421 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
5422 *temp = byte;
5423 return rval;
5424 }
5425 ql_dbg(ql_dbg_mbx, vha, 0x10c9,
5426 "Thermal not supported by this card.\n");
5427 return rval;
794a5691 5428 }
794a5691 5429
1ae47cf3
JC		 5430 if (IS_QLA82XX(ha)) {
5431 *temp = qla82xx_read_temperature(vha);
5432 rval = QLA_SUCCESS;
5433 return rval;
5434 } else if (IS_QLA8044(ha)) {
5435 *temp = qla8044_read_temperature(vha);
5436 rval = QLA_SUCCESS;
5437 return rval;
794a5691 5438 }
794a5691 5439
1ae47cf3 5440 rval = qla2x00_read_asic_temperature(vha, temp);
794a5691
AV		 5441 return rval;
5442}
5443
a9083016
GM		 5444int
5445qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
5446{
5447 int rval;
5448 struct qla_hw_data *ha = vha->hw;
5449 mbx_cmd_t mc;
5450 mbx_cmd_t *mcp = &mc;
5451
5f28d2d7
SK		 5452 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
5453 "Entered %s.\n", __func__);
7c3df132 5454
a9083016
GM		 5455 if (!IS_FWI2_CAPABLE(ha))
5456 return QLA_FUNCTION_FAILED;
5457
a9083016 5458 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 5459 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 5460 mcp->mb[1] = 1;
5461
5462 mcp->out_mb = MBX_1|MBX_0;
5463 mcp->in_mb = MBX_0;
5464 mcp->tov = 30;
5465 mcp->flags = 0;
5466
5467 rval = qla2x00_mailbox_command(vha, mcp);
5468 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5469 ql_dbg(ql_dbg_mbx, vha, 0x1016,
5470 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 5471 } else {
5f28d2d7
SK		 5472 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
5473 "Done %s.\n", __func__);
a9083016
GM		 5474 }
5475
5476 return rval;
5477}
5478
5479int
5480qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
5481{
5482 int rval;
5483 struct qla_hw_data *ha = vha->hw;
5484 mbx_cmd_t mc;
5485 mbx_cmd_t *mcp = &mc;
5486
5f28d2d7
SK		 5487 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
5488 "Entered %s.\n", __func__);
7c3df132 5489
7ec0effd 5490 if (!IS_P3P_TYPE(ha))
a9083016
GM		 5491 return QLA_FUNCTION_FAILED;
5492
a9083016 5493 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 5494 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 5495 mcp->mb[1] = 0;
5496
5497 mcp->out_mb = MBX_1|MBX_0;
5498 mcp->in_mb = MBX_0;
5499 mcp->tov = 30;
5500 mcp->flags = 0;
5501
5502 rval = qla2x00_mailbox_command(vha, mcp);
5503 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5504 ql_dbg(ql_dbg_mbx, vha, 0x100c,
5505 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 5506 } else {
5f28d2d7
SK		 5507 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
5508 "Done %s.\n", __func__);
a9083016
GM		 5509 }
5510
5511 return rval;
5512}
08de2844
GM		 5513
5514int
5515qla82xx_md_get_template_size(scsi_qla_host_t *vha)
5516{
5517 struct qla_hw_data *ha = vha->hw;
5518 mbx_cmd_t mc;
5519 mbx_cmd_t *mcp = &mc;
5520 int rval = QLA_FUNCTION_FAILED;
5521
5f28d2d7
SK		 5522 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
5523 "Entered %s.\n", __func__);
08de2844
GM		 5524
5525 memset(mcp->mb, 0 , sizeof(mcp->mb));
5526 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5527 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5528 mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
5529 mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
5530
5531 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5532 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
5533 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5534
5535 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5536 mcp->tov = MBX_TOV_SECONDS;
5537 rval = qla2x00_mailbox_command(vha, mcp);
5538
5539 /* Always copy back return mailbox values. */
5540 if (rval != QLA_SUCCESS) {
5541 ql_dbg(ql_dbg_mbx, vha, 0x1120,
5542 "mailbox command FAILED=0x%x, subcode=%x.\n",
5543 (mcp->mb[1] << 16) | mcp->mb[0],
5544 (mcp->mb[3] << 16) | mcp->mb[2]);
5545 } else {
5f28d2d7
SK		 5546 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
5547 "Done %s.\n", __func__);
08de2844
GM		 5548 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
5549 if (!ha->md_template_size) {
5550 ql_dbg(ql_dbg_mbx, vha, 0x1122,
5551 "Null template size obtained.\n");
5552 rval = QLA_FUNCTION_FAILED;
5553 }
5554 }
5555 return rval;
5556}
5557
5558int
5559qla82xx_md_get_template(scsi_qla_host_t *vha)
5560{
5561 struct qla_hw_data *ha = vha->hw;
5562 mbx_cmd_t mc;
5563 mbx_cmd_t *mcp = &mc;
5564 int rval = QLA_FUNCTION_FAILED;
5565
5f28d2d7
SK		 5566 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
5567 "Entered %s.\n", __func__);
08de2844
GM		 5568
5569 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5570 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5571 if (!ha->md_tmplt_hdr) {
5572 ql_log(ql_log_warn, vha, 0x1124,
5573 "Unable to allocate memory for Minidump template.\n");
5574 return rval;
5575 }
5576
5577 memset(mcp->mb, 0 , sizeof(mcp->mb));
5578 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5579 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5580 mcp->mb[2] = LSW(RQST_TMPLT);
5581 mcp->mb[3] = MSW(RQST_TMPLT);
5582 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
5583 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
5584 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
5585 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
5586 mcp->mb[8] = LSW(ha->md_template_size);
5587 mcp->mb[9] = MSW(ha->md_template_size);
5588
5589 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5590 mcp->tov = MBX_TOV_SECONDS;
5591 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5592 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5593 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5594 rval = qla2x00_mailbox_command(vha, mcp);
5595
5596 if (rval != QLA_SUCCESS) {
5597 ql_dbg(ql_dbg_mbx, vha, 0x1125,
5598 "mailbox command FAILED=0x%x, subcode=%x.\n",
5599 ((mcp->mb[1] << 16) | mcp->mb[0]),
5600 ((mcp->mb[3] << 16) | mcp->mb[2]));
5601 } else
5f28d2d7
SK		 5602 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
5603 "Done %s.\n", __func__);
08de2844
GM		 5604 return rval;
5605}
999916dc 5606
7ec0effd
AD		 5607int
5608qla8044_md_get_template(scsi_qla_host_t *vha)
5609{
5610 struct qla_hw_data *ha = vha->hw;
5611 mbx_cmd_t mc;
5612 mbx_cmd_t *mcp = &mc;
5613 int rval = QLA_FUNCTION_FAILED;
5614 int offset = 0, size = MINIDUMP_SIZE_36K;
5615 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
5616 "Entered %s.\n", __func__);
5617
5618 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5619 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5620 if (!ha->md_tmplt_hdr) {
5621 ql_log(ql_log_warn, vha, 0xb11b,
5622 "Unable to allocate memory for Minidump template.\n");
5623 return rval;
5624 }
5625
5626 memset(mcp->mb, 0 , sizeof(mcp->mb));
5627 while (offset < ha->md_template_size) {
5628 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5629 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5630 mcp->mb[2] = LSW(RQST_TMPLT);
5631 mcp->mb[3] = MSW(RQST_TMPLT);
5632 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
5633 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
5634 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
5635 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
5636 mcp->mb[8] = LSW(size);
5637 mcp->mb[9] = MSW(size);
5638 mcp->mb[10] = offset & 0x0000FFFF;
5639 mcp->mb[11] = offset & 0xFFFF0000;
5640 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5641 mcp->tov = MBX_TOV_SECONDS;
5642 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5643 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5644 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5645 rval = qla2x00_mailbox_command(vha, mcp);
5646
5647 if (rval != QLA_SUCCESS) {
5648 ql_dbg(ql_dbg_mbx, vha, 0xb11c,
5649 "mailbox command FAILED=0x%x, subcode=%x.\n",
5650 ((mcp->mb[1] << 16) | mcp->mb[0]),
5651 ((mcp->mb[3] << 16) | mcp->mb[2]));
5652 return rval;
5653 } else
5654 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
5655 "Done %s.\n", __func__);
5656 offset = offset + size;
5657 }
5658 return rval;
5659}
5660
6246b8a1
GM		 5661int
5662qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5663{
5664 int rval;
5665 struct qla_hw_data *ha = vha->hw;
5666 mbx_cmd_t mc;
5667 mbx_cmd_t *mcp = &mc;
5668
5669 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5670 return QLA_FUNCTION_FAILED;
5671
5f28d2d7
SK		 5672 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
5673 "Entered %s.\n", __func__);
6246b8a1
GM		 5674
5675 memset(mcp, 0, sizeof(mbx_cmd_t));
5676 mcp->mb[0] = MBC_SET_LED_CONFIG;
5677 mcp->mb[1] = led_cfg[0];
5678 mcp->mb[2] = led_cfg[1];
5679 if (IS_QLA8031(ha)) {
5680 mcp->mb[3] = led_cfg[2];
5681 mcp->mb[4] = led_cfg[3];
5682 mcp->mb[5] = led_cfg[4];
5683 mcp->mb[6] = led_cfg[5];
5684 }
5685
5686 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5687 if (IS_QLA8031(ha))
5688 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5689 mcp->in_mb = MBX_0;
5690 mcp->tov = 30;
5691 mcp->flags = 0;
5692
5693 rval = qla2x00_mailbox_command(vha, mcp);
5694 if (rval != QLA_SUCCESS) {
5695 ql_dbg(ql_dbg_mbx, vha, 0x1134,
5696 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5697 } else {
5f28d2d7
SK		 5698 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
5699 "Done %s.\n", __func__);
6246b8a1
GM		 5700 }
5701
5702 return rval;
5703}
5704
5705int
5706qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5707{
5708 int rval;
5709 struct qla_hw_data *ha = vha->hw;
5710 mbx_cmd_t mc;
5711 mbx_cmd_t *mcp = &mc;
5712
5713 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5714 return QLA_FUNCTION_FAILED;
5715
5f28d2d7
SK		 5716 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
5717 "Entered %s.\n", __func__);
6246b8a1
GM		 5718
5719 memset(mcp, 0, sizeof(mbx_cmd_t));
5720 mcp->mb[0] = MBC_GET_LED_CONFIG;
5721
5722 mcp->out_mb = MBX_0;
5723 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5724 if (IS_QLA8031(ha))
5725 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5726 mcp->tov = 30;
5727 mcp->flags = 0;
5728
5729 rval = qla2x00_mailbox_command(vha, mcp);
5730 if (rval != QLA_SUCCESS) {
5731 ql_dbg(ql_dbg_mbx, vha, 0x1137,
5732 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5733 } else {
5734 led_cfg[0] = mcp->mb[1];
5735 led_cfg[1] = mcp->mb[2];
5736 if (IS_QLA8031(ha)) {
5737 led_cfg[2] = mcp->mb[3];
5738 led_cfg[3] = mcp->mb[4];
5739 led_cfg[4] = mcp->mb[5];
5740 led_cfg[5] = mcp->mb[6];
5741 }
5f28d2d7
SK		 5742 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
5743 "Done %s.\n", __func__);
6246b8a1
GM		 5744 }
5745
5746 return rval;
5747}
5748
999916dc
SK		 5749int
5750qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
5751{
5752 int rval;
5753 struct qla_hw_data *ha = vha->hw;
5754 mbx_cmd_t mc;
5755 mbx_cmd_t *mcp = &mc;
5756
7ec0effd 5757 if (!IS_P3P_TYPE(ha))
999916dc
SK		 5758 return QLA_FUNCTION_FAILED;
5759
5f28d2d7 5760 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
999916dc
SK		 5761 "Entered %s.\n", __func__);
5762
5763 memset(mcp, 0, sizeof(mbx_cmd_t));
5764 mcp->mb[0] = MBC_SET_LED_CONFIG;
5765 if (enable)
5766 mcp->mb[7] = 0xE;
5767 else
5768 mcp->mb[7] = 0xD;
5769
5770 mcp->out_mb = MBX_7|MBX_0;
5771 mcp->in_mb = MBX_0;
6246b8a1 5772 mcp->tov = MBX_TOV_SECONDS;
999916dc
SK		 5773 mcp->flags = 0;
5774
5775 rval = qla2x00_mailbox_command(vha, mcp);
5776 if (rval != QLA_SUCCESS) {
5777 ql_dbg(ql_dbg_mbx, vha, 0x1128,
5778 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5779 } else {
5f28d2d7 5780 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
999916dc
SK		 5781 "Done %s.\n", __func__);
5782 }
5783
5784 return rval;
5785}
6246b8a1
GM		 5786
5787int
7d613ac6 5788qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
6246b8a1
GM		 5789{
5790 int rval;
5791 struct qla_hw_data *ha = vha->hw;
5792 mbx_cmd_t mc;
5793 mbx_cmd_t *mcp = &mc;
5794
f73cb695 5795 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
6246b8a1
GM		 5796 return QLA_FUNCTION_FAILED;
5797
5f28d2d7
SK		 5798 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
5799 "Entered %s.\n", __func__);
6246b8a1
GM		 5800
5801 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
5802 mcp->mb[1] = LSW(reg);
5803 mcp->mb[2] = MSW(reg);
5804 mcp->mb[3] = LSW(data);
5805 mcp->mb[4] = MSW(data);
5806 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5807
5808 mcp->in_mb = MBX_1|MBX_0;
5809 mcp->tov = MBX_TOV_SECONDS;
5810 mcp->flags = 0;
5811 rval = qla2x00_mailbox_command(vha, mcp);
5812
5813 if (rval != QLA_SUCCESS) {
5814 ql_dbg(ql_dbg_mbx, vha, 0x1131,
5815 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5816 } else {
5f28d2d7 5817 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
6246b8a1
GM		 5818 "Done %s.\n", __func__);
5819 }
af11f64d 5820
6246b8a1
GM		 5821 return rval;
5822}
af11f64d
AV		 5823
5824int
5825qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
5826{
5827 int rval;
5828 struct qla_hw_data *ha = vha->hw;
5829 mbx_cmd_t mc;
5830 mbx_cmd_t *mcp = &mc;
5831
5832 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
5f28d2d7 5833 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
af11f64d
AV		 5834 "Implicit LOGO Unsupported.\n");
5835 return QLA_FUNCTION_FAILED;
5836 }
5837
5838
5f28d2d7
SK		 5839 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
5840 "Entering %s.\n", __func__);
af11f64d
AV		 5841
5842 /* Perform Implicit LOGO. */
5843 mcp->mb[0] = MBC_PORT_LOGOUT;
5844 mcp->mb[1] = fcport->loop_id;
5845 mcp->mb[10] = BIT_15;
5846 mcp->out_mb = MBX_10|MBX_1|MBX_0;
5847 mcp->in_mb = MBX_0;
5848 mcp->tov = MBX_TOV_SECONDS;
5849 mcp->flags = 0;
5850 rval = qla2x00_mailbox_command(vha, mcp);
5851 if (rval != QLA_SUCCESS)
5852 ql_dbg(ql_dbg_mbx, vha, 0x113d,
5853 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5854 else
5f28d2d7
SK		 5855 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
5856 "Done %s.\n", __func__);
af11f64d
AV		 5857
5858 return rval;
5859}
5860
7d613ac6
SV		 5861int
5862qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
5863{
5864 int rval;
5865 mbx_cmd_t mc;
5866 mbx_cmd_t *mcp = &mc;
5867 struct qla_hw_data *ha = vha->hw;
5868 unsigned long retry_max_time = jiffies + (2 * HZ);
5869
f73cb695 5870 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
7d613ac6
SV		 5871 return QLA_FUNCTION_FAILED;
5872
5873 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
5874
5875retry_rd_reg:
5876 mcp->mb[0] = MBC_READ_REMOTE_REG;
5877 mcp->mb[1] = LSW(reg);
5878 mcp->mb[2] = MSW(reg);
5879 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5880 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5881 mcp->tov = MBX_TOV_SECONDS;
5882 mcp->flags = 0;
5883 rval = qla2x00_mailbox_command(vha, mcp);
5884
5885 if (rval != QLA_SUCCESS) {
5886 ql_dbg(ql_dbg_mbx, vha, 0x114c,
5887 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5888 rval, mcp->mb[0], mcp->mb[1]);
5889 } else {
5890 *data = (mcp->mb[3] | (mcp->mb[4] << 16));
5891 if (*data == QLA8XXX_BAD_VALUE) {
5892 /*
5893 * During soft-reset CAMRAM register reads might
5894 * return 0xbad0bad0. So retry for MAX of 2 sec
5895 * while reading camram registers.
5896 */
5897 if (time_after(jiffies, retry_max_time)) {
5898 ql_dbg(ql_dbg_mbx, vha, 0x1141,
5899 "Failure to read CAMRAM register. "
5900 "data=0x%x.\n", *data);
5901 return QLA_FUNCTION_FAILED;
5902 }
5903 msleep(100);
5904 goto retry_rd_reg;
5905 }
5906 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
5907 }
5908
5909 return rval;
5910}
5911
5912int
5913qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
5914{
5915 int rval;
5916 mbx_cmd_t mc;
5917 mbx_cmd_t *mcp = &mc;
5918 struct qla_hw_data *ha = vha->hw;
5919
b20f02e1 5920 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
7d613ac6
SV		 5921 return QLA_FUNCTION_FAILED;
5922
5923 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
5924
5925 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
5926 mcp->out_mb = MBX_0;
5927 mcp->in_mb = MBX_1|MBX_0;
5928 mcp->tov = MBX_TOV_SECONDS;
5929 mcp->flags = 0;
5930 rval = qla2x00_mailbox_command(vha, mcp);
5931
5932 if (rval != QLA_SUCCESS) {
5933 ql_dbg(ql_dbg_mbx, vha, 0x1144,
5934 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5935 rval, mcp->mb[0], mcp->mb[1]);
5936 ha->isp_ops->fw_dump(vha, 0);
5937 } else {
5938 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
5939 }
5940
5941 return rval;
5942}
5943
5944int
5945qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
5946 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
5947{
5948 int rval;
5949 mbx_cmd_t mc;
5950 mbx_cmd_t *mcp = &mc;
5951 uint8_t subcode = (uint8_t)options;
5952 struct qla_hw_data *ha = vha->hw;
5953
5954 if (!IS_QLA8031(ha))
5955 return QLA_FUNCTION_FAILED;
5956
5957 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
5958
5959 mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
5960 mcp->mb[1] = options;
5961 mcp->out_mb = MBX_1|MBX_0;
5962 if (subcode & BIT_2) {
5963 mcp->mb[2] = LSW(start_addr);
5964 mcp->mb[3] = MSW(start_addr);
5965 mcp->mb[4] = LSW(end_addr);
5966 mcp->mb[5] = MSW(end_addr);
5967 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
5968 }
5969 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5970 if (!(subcode & (BIT_2 | BIT_5)))
5971 mcp->in_mb |= MBX_4|MBX_3;
5972 mcp->tov = MBX_TOV_SECONDS;
5973 mcp->flags = 0;
5974 rval = qla2x00_mailbox_command(vha, mcp);
5975
5976 if (rval != QLA_SUCCESS) {
5977 ql_dbg(ql_dbg_mbx, vha, 0x1147,
5978 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
5979 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
5980 mcp->mb[4]);
5981 ha->isp_ops->fw_dump(vha, 0);
5982 } else {
5983 if (subcode & BIT_5)
5984 *sector_size = mcp->mb[1];
5985 else if (subcode & (BIT_6 | BIT_7)) {
5986 ql_dbg(ql_dbg_mbx, vha, 0x1148,
5987 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5988 } else if (subcode & (BIT_3 | BIT_4)) {
5989 ql_dbg(ql_dbg_mbx, vha, 0x1149,
5990 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5991 }
5992 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
5993 }
5994
5995 return rval;
5996}
81178772
SK		 5997
5998int
5999qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
6000 uint32_t size)
6001{
6002 int rval;
6003 mbx_cmd_t mc;
6004 mbx_cmd_t *mcp = &mc;
6005
6006 if (!IS_MCTP_CAPABLE(vha->hw))
6007 return QLA_FUNCTION_FAILED;
6008
6009 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
6010 "Entered %s.\n", __func__);
6011
6012 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
6013 mcp->mb[1] = LSW(addr);
6014 mcp->mb[2] = MSW(req_dma);
6015 mcp->mb[3] = LSW(req_dma);
6016 mcp->mb[4] = MSW(size);
6017 mcp->mb[5] = LSW(size);
6018 mcp->mb[6] = MSW(MSD(req_dma));
6019 mcp->mb[7] = LSW(MSD(req_dma));
6020 mcp->mb[8] = MSW(addr);
6021 /* Setting RAM ID to valid */
6022 mcp->mb[10] |= BIT_7;
6023 /* For MCTP RAM ID is 0x40 */
6024 mcp->mb[10] |= 0x40;
6025
6026 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
6027 MBX_0;
6028
6029 mcp->in_mb = MBX_0;
6030 mcp->tov = MBX_TOV_SECONDS;
6031 mcp->flags = 0;
6032 rval = qla2x00_mailbox_command(vha, mcp);
6033
6034 if (rval != QLA_SUCCESS) {
6035 ql_dbg(ql_dbg_mbx, vha, 0x114e,
6036 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
6037 } else {
6038 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
6039 "Done %s.\n", __func__);
6040 }
6041
6042 return rval;
6043}
ec891462
JC		 6044
6045int
6046qla26xx_dport_diagnostics(scsi_qla_host_t *vha,
6047 void *dd_buf, uint size, uint options)
6048{
6049 int rval;
6050 mbx_cmd_t mc;
6051 mbx_cmd_t *mcp = &mc;
6052 dma_addr_t dd_dma;
6053
6054 if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
6055 return QLA_FUNCTION_FAILED;
6056
83548fe2 6057 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x119f,
ec891462
JC		 6058 "Entered %s.\n", __func__);
6059
ec891462
JC		 6060 dd_dma = dma_map_single(&vha->hw->pdev->dev,
6061 dd_buf, size, DMA_FROM_DEVICE);
0b2ce198 6062 if (dma_mapping_error(&vha->hw->pdev->dev, dd_dma)) {
ec891462
JC		 6063 ql_log(ql_log_warn, vha, 0x1194, "Failed to map dma buffer.\n");
6064 return QLA_MEMORY_ALLOC_FAILED;
6065 }
6066
6067 memset(dd_buf, 0, size);
6068
6069 mcp->mb[0] = MBC_DPORT_DIAGNOSTICS;
6070 mcp->mb[1] = options;
6071 mcp->mb[2] = MSW(LSD(dd_dma));
6072 mcp->mb[3] = LSW(LSD(dd_dma));
6073 mcp->mb[6] = MSW(MSD(dd_dma));
6074 mcp->mb[7] = LSW(MSD(dd_dma));
6075 mcp->mb[8] = size;
6076 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6077 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
6078 mcp->buf_size = size;
6079 mcp->flags = MBX_DMA_IN;
6080 mcp->tov = MBX_TOV_SECONDS * 4;
6081 rval = qla2x00_mailbox_command(vha, mcp);
6082
6083 if (rval != QLA_SUCCESS) {
6084 ql_dbg(ql_dbg_mbx, vha, 0x1195, "Failed=%x.\n", rval);
6085 } else {
6086 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1196,
6087 "Done %s.\n", __func__);
6088 }
6089
6090 dma_unmap_single(&vha->hw->pdev->dev, dd_dma,
6091 size, DMA_FROM_DEVICE);
6092
6093 return rval;
6094}
15f30a57
QT		 6095
6096static void qla2x00_async_mb_sp_done(void *s, int res)
6097{
6098 struct srb *sp = s;
6099
6100 sp->u.iocb_cmd.u.mbx.rc = res;
6101
6102 complete(&sp->u.iocb_cmd.u.mbx.comp);
6103 /* don't free sp here. Let the caller do the free */
6104}
6105
6106/*
6107 * This mailbox uses the iocb interface to send MB command.
6108 * This allows non-critial (non chip setup) command to go
6109 * out in parrallel.
6110 */
6111int qla24xx_send_mb_cmd(struct scsi_qla_host *vha, mbx_cmd_t *mcp)
6112{
6113 int rval = QLA_FUNCTION_FAILED;
6114 srb_t *sp;
6115 struct srb_iocb *c;
6116
6117 if (!vha->hw->flags.fw_started)
6118 goto done;
6119
6120 sp = qla2x00_get_sp(vha, NULL, GFP_KERNEL);
6121 if (!sp)
6122 goto done;
6123
6124 sp->type = SRB_MB_IOCB;
6125 sp->name = mb_to_str(mcp->mb[0]);
6126
15f30a57
QT		 6127 c = &sp->u.iocb_cmd;
6128 c->timeout = qla2x00_async_iocb_timeout;
6129 init_completion(&c->u.mbx.comp);
6130
e74e7d95
BH		 6131 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
6132
6133 memcpy(sp->u.iocb_cmd.u.mbx.out_mb, mcp->mb, SIZEOF_IOCB_MB_REG);
6134
15f30a57
QT		 6135 sp->done = qla2x00_async_mb_sp_done;
6136
6137 rval = qla2x00_start_sp(sp);
6138 if (rval != QLA_SUCCESS) {
83548fe2 6139 ql_dbg(ql_dbg_mbx, vha, 0x1018,
15f30a57
QT		 6140 "%s: %s Failed submission. %x.\n",
6141 __func__, sp->name, rval);
6142 goto done_free_sp;
6143 }
6144
83548fe2 6145 ql_dbg(ql_dbg_mbx, vha, 0x113f, "MB:%s hndl %x submitted\n",
15f30a57
QT		 6146 sp->name, sp->handle);
6147
6148 wait_for_completion(&c->u.mbx.comp);
6149 memcpy(mcp->mb, sp->u.iocb_cmd.u.mbx.in_mb, SIZEOF_IOCB_MB_REG);
6150
6151 rval = c->u.mbx.rc;
6152 switch (rval) {
6153 case QLA_FUNCTION_TIMEOUT:
83548fe2 6154 ql_dbg(ql_dbg_mbx, vha, 0x1140, "%s: %s Timeout. %x.\n",
15f30a57
QT		 6155 __func__, sp->name, rval);
6156 break;
6157 case QLA_SUCCESS:
83548fe2 6158 ql_dbg(ql_dbg_mbx, vha, 0x119d, "%s: %s done.\n",
15f30a57
QT		 6159 __func__, sp->name);
6160 sp->free(sp);
6161 break;
6162 default:
83548fe2 6163 ql_dbg(ql_dbg_mbx, vha, 0x119e, "%s: %s Failed. %x.\n",
15f30a57
QT		 6164 __func__, sp->name, rval);
6165 sp->free(sp);
6166 break;
6167 }
6168
6169 return rval;
6170
6171done_free_sp:
6172 sp->free(sp);
6173done:
6174 return rval;
6175}
6176
6177/*
6178 * qla24xx_gpdb_wait
6179 * NOTE: Do not call this routine from DPC thread
6180 */
6181int qla24xx_gpdb_wait(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
6182{
6183 int rval = QLA_FUNCTION_FAILED;
6184 dma_addr_t pd_dma;
6185 struct port_database_24xx *pd;
6186 struct qla_hw_data *ha = vha->hw;
6187 mbx_cmd_t mc;
6188
6189 if (!vha->hw->flags.fw_started)
6190 goto done;
6191
08eb7f45 6192 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
15f30a57 6193 if (pd == NULL) {
83548fe2
QT		 6194 ql_log(ql_log_warn, vha, 0xd047,
6195 "Failed to allocate port database structure.\n");
15f30a57
QT		 6196 goto done_free_sp;
6197 }
15f30a57
QT		 6198
6199 memset(&mc, 0, sizeof(mc));
6200 mc.mb[0] = MBC_GET_PORT_DATABASE;
6201 mc.mb[1] = cpu_to_le16(fcport->loop_id);
6202 mc.mb[2] = MSW(pd_dma);
6203 mc.mb[3] = LSW(pd_dma);
6204 mc.mb[6] = MSW(MSD(pd_dma));
6205 mc.mb[7] = LSW(MSD(pd_dma));
6206 mc.mb[9] = cpu_to_le16(vha->vp_idx);
6207 mc.mb[10] = cpu_to_le16((uint16_t)opt);
6208
6209 rval = qla24xx_send_mb_cmd(vha, &mc);
6210 if (rval != QLA_SUCCESS) {
83548fe2 6211 ql_dbg(ql_dbg_mbx, vha, 0x1193,
15f30a57
QT		 6212 "%s: %8phC fail\n", __func__, fcport->port_name);
6213 goto done_free_sp;
6214 }
6215
6216 rval = __qla24xx_parse_gpdb(vha, fcport, pd);
6217
83548fe2 6218 ql_dbg(ql_dbg_mbx, vha, 0x1197, "%s: %8phC done\n",
15f30a57
QT		 6219 __func__, fcport->port_name);
6220
6221done_free_sp:
6222 if (pd)
6223 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
6224done:
6225 return rval;
6226}
6227
6228int __qla24xx_parse_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport,
6229 struct port_database_24xx *pd)
6230{
6231 int rval = QLA_SUCCESS;
6232 uint64_t zero = 0;
a5d42f4c
DG		 6233 u8 current_login_state, last_login_state;
6234
6235 if (fcport->fc4f_nvme) {
6236 current_login_state = pd->current_login_state >> 4;
6237 last_login_state = pd->last_login_state >> 4;
6238 } else {
6239 current_login_state = pd->current_login_state & 0xf;
6240 last_login_state = pd->last_login_state & 0xf;
6241 }
15f30a57
QT		 6242
6243 /* Check for logged in state. */
23c64559 6244 if (current_login_state != PDS_PRLI_COMPLETE) {
83548fe2
QT		 6245 ql_dbg(ql_dbg_mbx, vha, 0x119a,
6246 "Unable to verify login-state (%x/%x) for loop_id %x.\n",
a5d42f4c 6247 current_login_state, last_login_state, fcport->loop_id);
15f30a57
QT		 6248 rval = QLA_FUNCTION_FAILED;
6249 goto gpd_error_out;
6250 }
6251
6252 if (fcport->loop_id == FC_NO_LOOP_ID ||
6253 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
6254 memcmp(fcport->port_name, pd->port_name, 8))) {
6255 /* We lost the device mid way. */
6256 rval = QLA_NOT_LOGGED_IN;
6257 goto gpd_error_out;
6258 }
6259
6260 /* Names are little-endian. */
6261 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
6262 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
6263
6264 /* Get port_id of device. */
6265 fcport->d_id.b.domain = pd->port_id[0];
6266 fcport->d_id.b.area = pd->port_id[1];
6267 fcport->d_id.b.al_pa = pd->port_id[2];
6268 fcport->d_id.b.rsvd_1 = 0;
6269
a5d42f4c
DG		 6270 if (fcport->fc4f_nvme) {
6271 fcport->nvme_prli_service_param =
6272 pd->prli_nvme_svc_param_word_3;
6273 fcport->port_type = FCT_NVME;
6274 } else {
6275 /* If not target must be initiator or unknown type. */
6276 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
6277 fcport->port_type = FCT_INITIATOR;
6278 else
6279 fcport->port_type = FCT_TARGET;
6280 }
15f30a57
QT		 6281 /* Passback COS information. */
6282 fcport->supported_classes = (pd->flags & PDF_CLASS_2) ?
6283 FC_COS_CLASS2 : FC_COS_CLASS3;
6284
6285 if (pd->prli_svc_param_word_3[0] & BIT_7) {
6286 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
6287 fcport->conf_compl_supported = 1;
6288 }
6289
6290gpd_error_out:
6291 return rval;
6292}
6293
6294/*
6295 * qla24xx_gidlist__wait
6296 * NOTE: don't call this routine from DPC thread.
6297 */
6298int qla24xx_gidlist_wait(struct scsi_qla_host *vha,
6299 void *id_list, dma_addr_t id_list_dma, uint16_t *entries)
6300{
6301 int rval = QLA_FUNCTION_FAILED;
6302 mbx_cmd_t mc;
6303
6304 if (!vha->hw->flags.fw_started)
6305 goto done;
6306
6307 memset(&mc, 0, sizeof(mc));
6308 mc.mb[0] = MBC_GET_ID_LIST;
6309 mc.mb[2] = MSW(id_list_dma);
6310 mc.mb[3] = LSW(id_list_dma);
6311 mc.mb[6] = MSW(MSD(id_list_dma));
6312 mc.mb[7] = LSW(MSD(id_list_dma));
6313 mc.mb[8] = 0;
6314 mc.mb[9] = cpu_to_le16(vha->vp_idx);
6315
6316 rval = qla24xx_send_mb_cmd(vha, &mc);
6317 if (rval != QLA_SUCCESS) {
83548fe2
QT		 6318 ql_dbg(ql_dbg_mbx, vha, 0x119b,
6319 "%s: fail\n", __func__);
15f30a57
QT		 6320 } else {
6321 *entries = mc.mb[1];
83548fe2
QT		 6322 ql_dbg(ql_dbg_mbx, vha, 0x119c,
6323 "%s: done\n", __func__);
15f30a57
QT		 6324 }
6325done:
6326 return rval;
6327}
deeae7a6
DG		 6328
6329int qla27xx_set_zio_threshold(scsi_qla_host_t *vha, uint16_t value)
6330{
6331 int rval;
6332 mbx_cmd_t mc;
6333 mbx_cmd_t *mcp = &mc;
6334
6335 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1200,
6336 "Entered %s\n", __func__);
6337
6338 memset(mcp->mb, 0 , sizeof(mcp->mb));
6339 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
6340 mcp->mb[1] = cpu_to_le16(1);
6341 mcp->mb[2] = cpu_to_le16(value);
6342 mcp->out_mb = MBX_2 | MBX_1 | MBX_0;
6343 mcp->in_mb = MBX_2 | MBX_0;
6344 mcp->tov = MBX_TOV_SECONDS;
6345 mcp->flags = 0;
6346
6347 rval = qla2x00_mailbox_command(vha, mcp);
6348
6349 ql_dbg(ql_dbg_mbx, vha, 0x1201, "%s %x\n",
6350 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
6351
6352 return rval;
6353}
6354
6355int qla27xx_get_zio_threshold(scsi_qla_host_t *vha, uint16_t *value)
6356{
6357 int rval;
6358 mbx_cmd_t mc;
6359 mbx_cmd_t *mcp = &mc;
6360
6361 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1203,
6362 "Entered %s\n", __func__);
6363
6364 memset(mcp->mb, 0, sizeof(mcp->mb));
6365 mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
6366 mcp->mb[1] = cpu_to_le16(0);
6367 mcp->out_mb = MBX_1 | MBX_0;
6368 mcp->in_mb = MBX_2 | MBX_0;
6369 mcp->tov = MBX_TOV_SECONDS;
6370 mcp->flags = 0;
6371
6372 rval = qla2x00_mailbox_command(vha, mcp);
6373 if (rval == QLA_SUCCESS)
6374 *value = mc.mb[2];
6375
6376 ql_dbg(ql_dbg_mbx, vha, 0x1205, "%s %x\n",
6377 (rval != QLA_SUCCESS) ? "Failed" : "Done", rval);
6378
6379 return rval;
6380}
e4e3a2ce
QT		 6381
6382int
6383qla2x00_read_sfp_dev(struct scsi_qla_host *vha, char *buf, int count)
6384{
6385 struct qla_hw_data *ha = vha->hw;
6386 uint16_t iter, addr, offset;
6387 dma_addr_t phys_addr;
6388 int rval, c;
6389 u8 *sfp_data;
6390
6391 memset(ha->sfp_data, 0, SFP_DEV_SIZE);
6392 addr = 0xa0;
6393 phys_addr = ha->sfp_data_dma;
6394 sfp_data = ha->sfp_data;
6395 offset = c = 0;
6396
6397 for (iter = 0; iter < SFP_DEV_SIZE / SFP_BLOCK_SIZE; iter++) {
6398 if (iter == 4) {
6399 /* Skip to next device address. */
6400 addr = 0xa2;
6401 offset = 0;
6402 }
6403
6404 rval = qla2x00_read_sfp(vha, phys_addr, sfp_data,
6405 addr, offset, SFP_BLOCK_SIZE, BIT_1);
6406 if (rval != QLA_SUCCESS) {
6407 ql_log(ql_log_warn, vha, 0x706d,
6408 "Unable to read SFP data (%x/%x/%x).\n", rval,
6409 addr, offset);
6410
6411 return rval;
6412 }
6413
6414 if (buf && (c < count)) {
6415 u16 sz;
6416
6417 if ((count - c) >= SFP_BLOCK_SIZE)
6418 sz = SFP_BLOCK_SIZE;
6419 else
6420 sz = count - c;
6421
6422 memcpy(buf, sfp_data, sz);
6423 buf += SFP_BLOCK_SIZE;
6424 c += sz;
6425 }
6426 phys_addr += SFP_BLOCK_SIZE;
6427 sfp_data += SFP_BLOCK_SIZE;
6428 offset += SFP_BLOCK_SIZE;
6429 }
6430
6431 return rval;
6432}
94d83e36
QT		 6433
6434int qla24xx_res_count_wait(struct scsi_qla_host *vha,
6435 uint16_t *out_mb, int out_mb_sz)
6436{
6437 int rval = QLA_FUNCTION_FAILED;
6438 mbx_cmd_t mc;
6439
6440 if (!vha->hw->flags.fw_started)
6441 goto done;
6442
6443 memset(&mc, 0, sizeof(mc));
6444 mc.mb[0] = MBC_GET_RESOURCE_COUNTS;
6445
6446 rval = qla24xx_send_mb_cmd(vha, &mc);
6447 if (rval != QLA_SUCCESS) {
6448 ql_dbg(ql_dbg_mbx, vha, 0xffff,
6449 "%s: fail\n", __func__);
6450 } else {
6451 if (out_mb_sz <= SIZEOF_IOCB_MB_REG)
6452 memcpy(out_mb, mc.mb, out_mb_sz);
6453 else
6454 memcpy(out_mb, mc.mb, SIZEOF_IOCB_MB_REG);
6455
6456 ql_dbg(ql_dbg_mbx, vha, 0xffff,
6457 "%s: done\n", __func__);
6458 }
6459done:
6460 return rval;
6461}
Linux 6.x block layer and io_uring tree(s)