Commit | Line | Data |
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fa90c54f AV |
1 | /* |
2 | * QLogic Fibre Channel HBA Driver | |
07e264b7 | 3 | * Copyright (c) 2003-2011 QLogic Corporation |
fa90c54f AV |
4 | * |
5 | * See LICENSE.qla2xxx for copyright and licensing details. | |
6 | */ | |
3d71644c AV |
7 | #ifndef __QLA_FW_H |
8 | #define __QLA_FW_H | |
9 | ||
3d71644c | 10 | #define MBS_CHECKSUM_ERROR 0x4010 |
c3a2f0df | 11 | #define MBS_INVALID_PRODUCT_KEY 0x4020 |
3d71644c AV |
12 | |
13 | /* | |
14 | * Firmware Options. | |
15 | */ | |
16 | #define FO1_ENABLE_PUREX BIT_10 | |
17 | #define FO1_DISABLE_LED_CTRL BIT_6 | |
c3a2f0df | 18 | #define FO1_ENABLE_8016 BIT_0 |
3d71644c AV |
19 | #define FO2_ENABLE_SEL_CLASS2 BIT_5 |
20 | #define FO3_NO_ABTS_ON_LINKDOWN BIT_14 | |
c3a2f0df | 21 | #define FO3_HOLD_STS_IOCB BIT_12 |
3d71644c AV |
22 | |
23 | /* | |
24 | * Port Database structure definition for ISP 24xx. | |
25 | */ | |
26 | #define PDO_FORCE_ADISC BIT_1 | |
27 | #define PDO_FORCE_PLOGI BIT_0 | |
28 | ||
29 | ||
30 | #define PORT_DATABASE_24XX_SIZE 64 | |
31 | struct port_database_24xx { | |
32 | uint16_t flags; | |
33 | #define PDF_TASK_RETRY_ID BIT_14 | |
34 | #define PDF_FC_TAPE BIT_7 | |
35 | #define PDF_ACK0_CAPABLE BIT_6 | |
36 | #define PDF_FCP2_CONF BIT_5 | |
37 | #define PDF_CLASS_2 BIT_4 | |
38 | #define PDF_HARD_ADDR BIT_1 | |
39 | ||
40 | uint8_t current_login_state; | |
41 | uint8_t last_login_state; | |
42 | #define PDS_PLOGI_PENDING 0x03 | |
43 | #define PDS_PLOGI_COMPLETE 0x04 | |
44 | #define PDS_PRLI_PENDING 0x05 | |
45 | #define PDS_PRLI_COMPLETE 0x06 | |
46 | #define PDS_PORT_UNAVAILABLE 0x07 | |
47 | #define PDS_PRLO_PENDING 0x09 | |
48 | #define PDS_LOGO_PENDING 0x11 | |
3d71644c AV |
49 | #define PDS_PRLI2_PENDING 0x12 |
50 | ||
51 | uint8_t hard_address[3]; | |
52 | uint8_t reserved_1; | |
53 | ||
54 | uint8_t port_id[3]; | |
55 | uint8_t sequence_id; | |
56 | ||
57 | uint16_t port_timer; | |
58 | ||
59 | uint16_t nport_handle; /* N_PORT handle. */ | |
60 | ||
61 | uint16_t receive_data_size; | |
62 | uint16_t reserved_2; | |
63 | ||
64 | uint8_t prli_svc_param_word_0[2]; /* Big endian */ | |
65 | /* Bits 15-0 of word 0 */ | |
66 | uint8_t prli_svc_param_word_3[2]; /* Big endian */ | |
67 | /* Bits 15-0 of word 3 */ | |
68 | ||
69 | uint8_t port_name[WWN_SIZE]; | |
70 | uint8_t node_name[WWN_SIZE]; | |
71 | ||
72 | uint8_t reserved_3[24]; | |
73 | }; | |
74 | ||
2c3dfe3f SJ |
75 | struct vp_database_24xx { |
76 | uint16_t vp_status; | |
77 | uint8_t options; | |
78 | uint8_t id; | |
79 | uint8_t port_name[WWN_SIZE]; | |
80 | uint8_t node_name[WWN_SIZE]; | |
81 | uint16_t port_id_low; | |
82 | uint16_t port_id_high; | |
83 | }; | |
84 | ||
3d71644c AV |
85 | struct nvram_24xx { |
86 | /* NVRAM header. */ | |
87 | uint8_t id[4]; | |
88 | uint16_t nvram_version; | |
89 | uint16_t reserved_0; | |
90 | ||
91 | /* Firmware Initialization Control Block. */ | |
92 | uint16_t version; | |
93 | uint16_t reserved_1; | |
94 | uint16_t frame_payload_size; | |
95 | uint16_t execution_throttle; | |
96 | uint16_t exchange_count; | |
97 | uint16_t hard_address; | |
98 | ||
99 | uint8_t port_name[WWN_SIZE]; | |
100 | uint8_t node_name[WWN_SIZE]; | |
101 | ||
102 | uint16_t login_retry_count; | |
103 | uint16_t link_down_on_nos; | |
104 | uint16_t interrupt_delay_timer; | |
105 | uint16_t login_timeout; | |
106 | ||
107 | uint32_t firmware_options_1; | |
108 | uint32_t firmware_options_2; | |
109 | uint32_t firmware_options_3; | |
110 | ||
111 | /* Offset 56. */ | |
112 | ||
113 | /* | |
114 | * BIT 0 = Control Enable | |
115 | * BIT 1-15 = | |
116 | * | |
117 | * BIT 0-7 = Reserved | |
118 | * BIT 8-10 = Output Swing 1G | |
119 | * BIT 11-13 = Output Emphasis 1G | |
120 | * BIT 14-15 = Reserved | |
121 | * | |
122 | * BIT 0-7 = Reserved | |
123 | * BIT 8-10 = Output Swing 2G | |
124 | * BIT 11-13 = Output Emphasis 2G | |
125 | * BIT 14-15 = Reserved | |
126 | * | |
127 | * BIT 0-7 = Reserved | |
128 | * BIT 8-10 = Output Swing 4G | |
129 | * BIT 11-13 = Output Emphasis 4G | |
130 | * BIT 14-15 = Reserved | |
131 | */ | |
132 | uint16_t seriallink_options[4]; | |
133 | ||
134 | uint16_t reserved_2[16]; | |
135 | ||
136 | /* Offset 96. */ | |
137 | uint16_t reserved_3[16]; | |
138 | ||
139 | /* PCIe table entries. */ | |
140 | uint16_t reserved_4[16]; | |
141 | ||
142 | /* Offset 160. */ | |
143 | uint16_t reserved_5[16]; | |
144 | ||
145 | /* Offset 192. */ | |
146 | uint16_t reserved_6[16]; | |
147 | ||
148 | /* Offset 224. */ | |
149 | uint16_t reserved_7[16]; | |
150 | ||
151 | /* | |
152 | * BIT 0 = Enable spinup delay | |
153 | * BIT 1 = Disable BIOS | |
154 | * BIT 2 = Enable Memory Map BIOS | |
155 | * BIT 3 = Enable Selectable Boot | |
156 | * BIT 4 = Disable RISC code load | |
d4c760c2 | 157 | * BIT 5 = Disable Serdes |
3d71644c AV |
158 | * BIT 6 = |
159 | * BIT 7 = | |
160 | * | |
161 | * BIT 8 = | |
162 | * BIT 9 = | |
163 | * BIT 10 = Enable lip full login | |
164 | * BIT 11 = Enable target reset | |
165 | * BIT 12 = | |
166 | * BIT 13 = | |
167 | * BIT 14 = | |
168 | * BIT 15 = Enable alternate WWN | |
169 | * | |
170 | * BIT 16-31 = | |
171 | */ | |
172 | uint32_t host_p; | |
173 | ||
174 | uint8_t alternate_port_name[WWN_SIZE]; | |
175 | uint8_t alternate_node_name[WWN_SIZE]; | |
176 | ||
177 | uint8_t boot_port_name[WWN_SIZE]; | |
178 | uint16_t boot_lun_number; | |
179 | uint16_t reserved_8; | |
180 | ||
181 | uint8_t alt1_boot_port_name[WWN_SIZE]; | |
182 | uint16_t alt1_boot_lun_number; | |
183 | uint16_t reserved_9; | |
184 | ||
185 | uint8_t alt2_boot_port_name[WWN_SIZE]; | |
186 | uint16_t alt2_boot_lun_number; | |
187 | uint16_t reserved_10; | |
188 | ||
189 | uint8_t alt3_boot_port_name[WWN_SIZE]; | |
190 | uint16_t alt3_boot_lun_number; | |
191 | uint16_t reserved_11; | |
192 | ||
193 | /* | |
194 | * BIT 0 = Selective Login | |
195 | * BIT 1 = Alt-Boot Enable | |
196 | * BIT 2 = Reserved | |
197 | * BIT 3 = Boot Order List | |
198 | * BIT 4 = Reserved | |
199 | * BIT 5 = Selective LUN | |
200 | * BIT 6 = Reserved | |
201 | * BIT 7-31 = | |
202 | */ | |
203 | uint32_t efi_parameters; | |
204 | ||
205 | uint8_t reset_delay; | |
206 | uint8_t reserved_12; | |
207 | uint16_t reserved_13; | |
208 | ||
209 | uint16_t boot_id_number; | |
210 | uint16_t reserved_14; | |
211 | ||
212 | uint16_t max_luns_per_target; | |
213 | uint16_t reserved_15; | |
214 | ||
215 | uint16_t port_down_retry_count; | |
216 | uint16_t link_down_timeout; | |
217 | ||
218 | /* FCode parameters. */ | |
219 | uint16_t fcode_parameter; | |
220 | ||
221 | uint16_t reserved_16[3]; | |
222 | ||
223 | /* Offset 352. */ | |
224 | uint8_t prev_drv_ver_major; | |
225 | uint8_t prev_drv_ver_submajob; | |
226 | uint8_t prev_drv_ver_minor; | |
227 | uint8_t prev_drv_ver_subminor; | |
228 | ||
229 | uint16_t prev_bios_ver_major; | |
230 | uint16_t prev_bios_ver_minor; | |
231 | ||
232 | uint16_t prev_efi_ver_major; | |
233 | uint16_t prev_efi_ver_minor; | |
234 | ||
235 | uint16_t prev_fw_ver_major; | |
236 | uint8_t prev_fw_ver_minor; | |
237 | uint8_t prev_fw_ver_subminor; | |
238 | ||
239 | uint16_t reserved_17[8]; | |
240 | ||
241 | /* Offset 384. */ | |
242 | uint16_t reserved_18[16]; | |
243 | ||
244 | /* Offset 416. */ | |
245 | uint16_t reserved_19[16]; | |
246 | ||
247 | /* Offset 448. */ | |
248 | uint16_t reserved_20[16]; | |
249 | ||
250 | /* Offset 480. */ | |
251 | uint8_t model_name[16]; | |
252 | ||
253 | uint16_t reserved_21[2]; | |
254 | ||
255 | /* Offset 500. */ | |
256 | /* HW Parameter Block. */ | |
257 | uint16_t pcie_table_sig; | |
258 | uint16_t pcie_table_offset; | |
259 | ||
260 | uint16_t subsystem_vendor_id; | |
261 | uint16_t subsystem_device_id; | |
262 | ||
263 | uint32_t checksum; | |
264 | }; | |
265 | ||
266 | /* | |
267 | * ISP Initialization Control Block. | |
268 | * Little endian except where noted. | |
269 | */ | |
270 | #define ICB_VERSION 1 | |
271 | struct init_cb_24xx { | |
272 | uint16_t version; | |
273 | uint16_t reserved_1; | |
274 | ||
275 | uint16_t frame_payload_size; | |
276 | uint16_t execution_throttle; | |
277 | uint16_t exchange_count; | |
278 | ||
279 | uint16_t hard_address; | |
280 | ||
281 | uint8_t port_name[WWN_SIZE]; /* Big endian. */ | |
282 | uint8_t node_name[WWN_SIZE]; /* Big endian. */ | |
283 | ||
284 | uint16_t response_q_inpointer; | |
285 | uint16_t request_q_outpointer; | |
286 | ||
287 | uint16_t login_retry_count; | |
288 | ||
289 | uint16_t prio_request_q_outpointer; | |
290 | ||
291 | uint16_t response_q_length; | |
292 | uint16_t request_q_length; | |
293 | ||
3ea66e28 | 294 | uint16_t link_down_on_nos; /* Milliseconds. */ |
3d71644c AV |
295 | |
296 | uint16_t prio_request_q_length; | |
297 | ||
298 | uint32_t request_q_address[2]; | |
299 | uint32_t response_q_address[2]; | |
300 | uint32_t prio_request_q_address[2]; | |
301 | ||
73208dfd AC |
302 | uint16_t msix; |
303 | uint8_t reserved_2[6]; | |
3d71644c AV |
304 | |
305 | uint16_t atio_q_inpointer; | |
306 | uint16_t atio_q_length; | |
307 | uint32_t atio_q_address[2]; | |
308 | ||
309 | uint16_t interrupt_delay_timer; /* 100us increments. */ | |
310 | uint16_t login_timeout; | |
311 | ||
312 | /* | |
313 | * BIT 0 = Enable Hard Loop Id | |
314 | * BIT 1 = Enable Fairness | |
315 | * BIT 2 = Enable Full-Duplex | |
316 | * BIT 3 = Reserved | |
317 | * BIT 4 = Enable Target Mode | |
318 | * BIT 5 = Disable Initiator Mode | |
319 | * BIT 6 = Reserved | |
320 | * BIT 7 = Reserved | |
321 | * | |
322 | * BIT 8 = Reserved | |
323 | * BIT 9 = Non Participating LIP | |
324 | * BIT 10 = Descending Loop ID Search | |
325 | * BIT 11 = Acquire Loop ID in LIPA | |
326 | * BIT 12 = Reserved | |
327 | * BIT 13 = Full Login after LIP | |
328 | * BIT 14 = Node Name Option | |
329 | * BIT 15-31 = Reserved | |
330 | */ | |
331 | uint32_t firmware_options_1; | |
332 | ||
333 | /* | |
334 | * BIT 0 = Operation Mode bit 0 | |
335 | * BIT 1 = Operation Mode bit 1 | |
336 | * BIT 2 = Operation Mode bit 2 | |
337 | * BIT 3 = Operation Mode bit 3 | |
338 | * BIT 4 = Connection Options bit 0 | |
339 | * BIT 5 = Connection Options bit 1 | |
340 | * BIT 6 = Connection Options bit 2 | |
341 | * BIT 7 = Enable Non part on LIHA failure | |
342 | * | |
343 | * BIT 8 = Enable Class 2 | |
344 | * BIT 9 = Enable ACK0 | |
345 | * BIT 10 = Reserved | |
346 | * BIT 11 = Enable FC-SP Security | |
347 | * BIT 12 = FC Tape Enable | |
c3a2f0df AV |
348 | * BIT 13 = Reserved |
349 | * BIT 14 = Enable Target PRLI Control | |
350 | * BIT 15-31 = Reserved | |
3d71644c AV |
351 | */ |
352 | uint32_t firmware_options_2; | |
353 | ||
354 | /* | |
355 | * BIT 0 = Reserved | |
356 | * BIT 1 = Soft ID only | |
357 | * BIT 2 = Reserved | |
358 | * BIT 3 = Reserved | |
359 | * BIT 4 = FCP RSP Payload bit 0 | |
360 | * BIT 5 = FCP RSP Payload bit 1 | |
361 | * BIT 6 = Enable Receive Out-of-Order data frame handling | |
362 | * BIT 7 = Disable Automatic PLOGI on Local Loop | |
363 | * | |
364 | * BIT 8 = Reserved | |
365 | * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling | |
366 | * BIT 10 = Reserved | |
367 | * BIT 11 = Reserved | |
368 | * BIT 12 = Reserved | |
369 | * BIT 13 = Data Rate bit 0 | |
370 | * BIT 14 = Data Rate bit 1 | |
371 | * BIT 15 = Data Rate bit 2 | |
c3a2f0df AV |
372 | * BIT 16 = Enable 75 ohm Termination Select |
373 | * BIT 17-31 = Reserved | |
3d71644c AV |
374 | */ |
375 | uint32_t firmware_options_3; | |
73208dfd AC |
376 | uint16_t qos; |
377 | uint16_t rid; | |
378 | uint8_t reserved_3[20]; | |
3d71644c AV |
379 | }; |
380 | ||
381 | /* | |
382 | * ISP queue - command entry structure definition. | |
383 | */ | |
384 | #define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */ | |
385 | struct cmd_type_6 { | |
386 | uint8_t entry_type; /* Entry type. */ | |
387 | uint8_t entry_count; /* Entry count. */ | |
388 | uint8_t sys_define; /* System defined. */ | |
389 | uint8_t entry_status; /* Entry Status. */ | |
390 | ||
391 | uint32_t handle; /* System handle. */ | |
392 | ||
393 | uint16_t nport_handle; /* N_PORT handle. */ | |
394 | uint16_t timeout; /* Command timeout. */ | |
395 | ||
396 | uint16_t dseg_count; /* Data segment count. */ | |
397 | ||
398 | uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */ | |
399 | ||
661c3f6c | 400 | struct scsi_lun lun; /* FCP LUN (BE). */ |
3d71644c AV |
401 | |
402 | uint16_t control_flags; /* Control flags. */ | |
bad75002 | 403 | #define CF_DIF_SEG_DESCR_ENABLE BIT_3 |
3d71644c AV |
404 | #define CF_DATA_SEG_DESCR_ENABLE BIT_2 |
405 | #define CF_READ_DATA BIT_1 | |
406 | #define CF_WRITE_DATA BIT_0 | |
407 | ||
408 | uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ | |
409 | uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ | |
410 | ||
411 | uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */ | |
412 | ||
413 | uint32_t byte_count; /* Total byte count. */ | |
414 | ||
415 | uint8_t port_id[3]; /* PortID of destination port. */ | |
416 | uint8_t vp_index; | |
417 | ||
418 | uint32_t fcp_data_dseg_address[2]; /* Data segment address. */ | |
fa96d927 | 419 | uint32_t fcp_data_dseg_len; /* Data segment length. */ |
3d71644c AV |
420 | }; |
421 | ||
422 | #define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */ | |
423 | struct cmd_type_7 { | |
424 | uint8_t entry_type; /* Entry type. */ | |
425 | uint8_t entry_count; /* Entry count. */ | |
426 | uint8_t sys_define; /* System defined. */ | |
427 | uint8_t entry_status; /* Entry Status. */ | |
428 | ||
429 | uint32_t handle; /* System handle. */ | |
430 | ||
431 | uint16_t nport_handle; /* N_PORT handle. */ | |
432 | uint16_t timeout; /* Command timeout. */ | |
433 | #define FW_MAX_TIMEOUT 0x1999 | |
434 | ||
435 | uint16_t dseg_count; /* Data segment count. */ | |
436 | uint16_t reserved_1; | |
437 | ||
661c3f6c | 438 | struct scsi_lun lun; /* FCP LUN (BE). */ |
3d71644c AV |
439 | |
440 | uint16_t task_mgmt_flags; /* Task management flags. */ | |
441 | #define TMF_CLEAR_ACA BIT_14 | |
442 | #define TMF_TARGET_RESET BIT_13 | |
443 | #define TMF_LUN_RESET BIT_12 | |
444 | #define TMF_CLEAR_TASK_SET BIT_10 | |
445 | #define TMF_ABORT_TASK_SET BIT_9 | |
c3a2f0df | 446 | #define TMF_DSD_LIST_ENABLE BIT_2 |
3d71644c AV |
447 | #define TMF_READ_DATA BIT_1 |
448 | #define TMF_WRITE_DATA BIT_0 | |
449 | ||
450 | uint8_t task; | |
451 | #define TSK_SIMPLE 0 | |
452 | #define TSK_HEAD_OF_QUEUE 1 | |
453 | #define TSK_ORDERED 2 | |
454 | #define TSK_ACA 4 | |
455 | #define TSK_UNTAGGED 5 | |
456 | ||
457 | uint8_t crn; | |
458 | ||
459 | uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */ | |
460 | uint32_t byte_count; /* Total byte count. */ | |
461 | ||
462 | uint8_t port_id[3]; /* PortID of destination port. */ | |
463 | uint8_t vp_index; | |
464 | ||
465 | uint32_t dseg_0_address[2]; /* Data segment 0 address. */ | |
466 | uint32_t dseg_0_len; /* Data segment 0 length. */ | |
467 | }; | |
468 | ||
bad75002 AE |
469 | #define COMMAND_TYPE_CRC_2 0x6A /* Command Type CRC_2 (Type 6) |
470 | * (T10-DIF) */ | |
471 | struct cmd_type_crc_2 { | |
472 | uint8_t entry_type; /* Entry type. */ | |
473 | uint8_t entry_count; /* Entry count. */ | |
474 | uint8_t sys_define; /* System defined. */ | |
475 | uint8_t entry_status; /* Entry Status. */ | |
476 | ||
477 | uint32_t handle; /* System handle. */ | |
478 | ||
479 | uint16_t nport_handle; /* N_PORT handle. */ | |
480 | uint16_t timeout; /* Command timeout. */ | |
481 | ||
482 | uint16_t dseg_count; /* Data segment count. */ | |
483 | ||
484 | uint16_t fcp_rsp_dseg_len; /* FCP_RSP DSD length. */ | |
485 | ||
486 | struct scsi_lun lun; /* FCP LUN (BE). */ | |
487 | ||
488 | uint16_t control_flags; /* Control flags. */ | |
489 | ||
490 | uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ | |
491 | uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ | |
492 | ||
493 | uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */ | |
494 | ||
495 | uint32_t byte_count; /* Total byte count. */ | |
496 | ||
497 | uint8_t port_id[3]; /* PortID of destination port. */ | |
498 | uint8_t vp_index; | |
499 | ||
500 | uint32_t crc_context_address[2]; /* Data segment address. */ | |
501 | uint16_t crc_context_len; /* Data segment length. */ | |
502 | uint16_t reserved_1; /* MUST be set to 0. */ | |
503 | }; | |
504 | ||
505 | ||
3d71644c AV |
506 | /* |
507 | * ISP queue - status entry structure definition. | |
508 | */ | |
509 | #define STATUS_TYPE 0x03 /* Status entry. */ | |
510 | struct sts_entry_24xx { | |
511 | uint8_t entry_type; /* Entry type. */ | |
512 | uint8_t entry_count; /* Entry count. */ | |
513 | uint8_t sys_define; /* System defined. */ | |
514 | uint8_t entry_status; /* Entry Status. */ | |
515 | ||
516 | uint32_t handle; /* System handle. */ | |
517 | ||
518 | uint16_t comp_status; /* Completion status. */ | |
519 | uint16_t ox_id; /* OX_ID used by the firmware. */ | |
520 | ||
ed17c71b | 521 | uint32_t residual_len; /* FW calc residual transfer length. */ |
3d71644c AV |
522 | |
523 | uint16_t reserved_1; | |
524 | uint16_t state_flags; /* State flags. */ | |
525 | #define SF_TRANSFERRED_DATA BIT_11 | |
526 | #define SF_FCP_RSP_DMA BIT_0 | |
527 | ||
528 | uint16_t reserved_2; | |
529 | uint16_t scsi_status; /* SCSI status. */ | |
530 | #define SS_CONFIRMATION_REQ BIT_12 | |
531 | ||
532 | uint32_t rsp_residual_count; /* FCP RSP residual count. */ | |
533 | ||
534 | uint32_t sense_len; /* FCP SENSE length. */ | |
535 | uint32_t rsp_data_len; /* FCP response data length. */ | |
3d71644c | 536 | uint8_t data[28]; /* FCP response/sense information. */ |
bad75002 AE |
537 | /* |
538 | * If DIF Error is set in comp_status, these additional fields are | |
539 | * defined: | |
540 | * &data[10] : uint8_t report_runt_bg[2]; - computed guard | |
25985edc | 541 | * &data[12] : uint8_t actual_dif[8]; - DIF Data received |
bad75002 AE |
542 | * &data[20] : uint8_t expected_dif[8]; - DIF Data computed |
543 | */ | |
3d71644c AV |
544 | }; |
545 | ||
bad75002 | 546 | |
3d71644c AV |
547 | /* |
548 | * Status entry completion status | |
549 | */ | |
550 | #define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */ | |
551 | #define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */ | |
552 | #define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */ | |
553 | #define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */ | |
554 | #define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */ | |
555 | ||
556 | /* | |
557 | * ISP queue - marker entry structure definition. | |
558 | */ | |
559 | #define MARKER_TYPE 0x04 /* Marker entry. */ | |
560 | struct mrk_entry_24xx { | |
561 | uint8_t entry_type; /* Entry type. */ | |
562 | uint8_t entry_count; /* Entry count. */ | |
563 | uint8_t handle_count; /* Handle count. */ | |
564 | uint8_t entry_status; /* Entry Status. */ | |
565 | ||
566 | uint32_t handle; /* System handle. */ | |
567 | ||
568 | uint16_t nport_handle; /* N_PORT handle. */ | |
569 | ||
570 | uint8_t modifier; /* Modifier (7-0). */ | |
571 | #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ | |
572 | #define MK_SYNC_ID 1 /* Synchronize ID */ | |
573 | #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ | |
574 | uint8_t reserved_1; | |
575 | ||
576 | uint8_t reserved_2; | |
577 | uint8_t vp_index; | |
578 | ||
579 | uint16_t reserved_3; | |
580 | ||
581 | uint8_t lun[8]; /* FCP LUN (BE). */ | |
582 | uint8_t reserved_4[40]; | |
583 | }; | |
584 | ||
585 | /* | |
586 | * ISP queue - CT Pass-Through entry structure definition. | |
587 | */ | |
588 | #define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */ | |
589 | struct ct_entry_24xx { | |
590 | uint8_t entry_type; /* Entry type. */ | |
591 | uint8_t entry_count; /* Entry count. */ | |
592 | uint8_t sys_define; /* System Defined. */ | |
593 | uint8_t entry_status; /* Entry Status. */ | |
594 | ||
595 | uint32_t handle; /* System handle. */ | |
596 | ||
597 | uint16_t comp_status; /* Completion status. */ | |
598 | ||
599 | uint16_t nport_handle; /* N_PORT handle. */ | |
600 | ||
601 | uint16_t cmd_dsd_count; | |
602 | ||
603 | uint8_t vp_index; | |
604 | uint8_t reserved_1; | |
605 | ||
606 | uint16_t timeout; /* Command timeout. */ | |
607 | uint16_t reserved_2; | |
608 | ||
609 | uint16_t rsp_dsd_count; | |
610 | ||
611 | uint8_t reserved_3[10]; | |
612 | ||
613 | uint32_t rsp_byte_count; | |
614 | uint32_t cmd_byte_count; | |
615 | ||
616 | uint32_t dseg_0_address[2]; /* Data segment 0 address. */ | |
617 | uint32_t dseg_0_len; /* Data segment 0 length. */ | |
618 | uint32_t dseg_1_address[2]; /* Data segment 1 address. */ | |
619 | uint32_t dseg_1_len; /* Data segment 1 length. */ | |
620 | }; | |
621 | ||
622 | /* | |
623 | * ISP queue - ELS Pass-Through entry structure definition. | |
624 | */ | |
625 | #define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */ | |
626 | struct els_entry_24xx { | |
627 | uint8_t entry_type; /* Entry type. */ | |
628 | uint8_t entry_count; /* Entry count. */ | |
629 | uint8_t sys_define; /* System Defined. */ | |
630 | uint8_t entry_status; /* Entry Status. */ | |
631 | ||
632 | uint32_t handle; /* System handle. */ | |
633 | ||
634 | uint16_t reserved_1; | |
635 | ||
636 | uint16_t nport_handle; /* N_PORT handle. */ | |
637 | ||
638 | uint16_t tx_dsd_count; | |
639 | ||
640 | uint8_t vp_index; | |
641 | uint8_t sof_type; | |
642 | #define EST_SOFI3 (1 << 4) | |
643 | #define EST_SOFI2 (3 << 4) | |
644 | ||
c3a2f0df | 645 | uint32_t rx_xchg_address; /* Receive exchange address. */ |
3d71644c AV |
646 | uint16_t rx_dsd_count; |
647 | ||
648 | uint8_t opcode; | |
649 | uint8_t reserved_2; | |
650 | ||
651 | uint8_t port_id[3]; | |
652 | uint8_t reserved_3; | |
653 | ||
654 | uint16_t reserved_4; | |
655 | ||
656 | uint16_t control_flags; /* Control flags. */ | |
657 | #define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13) | |
658 | #define EPD_ELS_COMMAND (0 << 13) | |
659 | #define EPD_ELS_ACC (1 << 13) | |
660 | #define EPD_ELS_RJT (2 << 13) | |
661 | #define EPD_RX_XCHG (3 << 13) | |
662 | #define ECF_CLR_PASSTHRU_PEND BIT_12 | |
663 | #define ECF_INCL_FRAME_HDR BIT_11 | |
664 | ||
665 | uint32_t rx_byte_count; | |
666 | uint32_t tx_byte_count; | |
667 | ||
668 | uint32_t tx_address[2]; /* Data segment 0 address. */ | |
669 | uint32_t tx_len; /* Data segment 0 length. */ | |
670 | uint32_t rx_address[2]; /* Data segment 1 address. */ | |
671 | uint32_t rx_len; /* Data segment 1 length. */ | |
672 | }; | |
673 | ||
9a069e19 GM |
674 | struct els_sts_entry_24xx { |
675 | uint8_t entry_type; /* Entry type. */ | |
676 | uint8_t entry_count; /* Entry count. */ | |
677 | uint8_t sys_define; /* System Defined. */ | |
678 | uint8_t entry_status; /* Entry Status. */ | |
679 | ||
680 | uint32_t handle; /* System handle. */ | |
681 | ||
682 | uint16_t comp_status; | |
683 | ||
684 | uint16_t nport_handle; /* N_PORT handle. */ | |
685 | ||
686 | uint16_t reserved_1; | |
687 | ||
688 | uint8_t vp_index; | |
689 | uint8_t sof_type; | |
690 | ||
691 | uint32_t rx_xchg_address; /* Receive exchange address. */ | |
692 | uint16_t reserved_2; | |
693 | ||
694 | uint8_t opcode; | |
695 | uint8_t reserved_3; | |
696 | ||
697 | uint8_t port_id[3]; | |
698 | uint8_t reserved_4; | |
699 | ||
700 | uint16_t reserved_5; | |
701 | ||
702 | uint16_t control_flags; /* Control flags. */ | |
703 | uint32_t total_byte_count; | |
704 | uint32_t error_subcode_1; | |
705 | uint32_t error_subcode_2; | |
706 | }; | |
3d71644c AV |
707 | /* |
708 | * ISP queue - Mailbox Command entry structure definition. | |
709 | */ | |
710 | #define MBX_IOCB_TYPE 0x39 | |
711 | struct mbx_entry_24xx { | |
712 | uint8_t entry_type; /* Entry type. */ | |
713 | uint8_t entry_count; /* Entry count. */ | |
714 | uint8_t handle_count; /* Handle count. */ | |
715 | uint8_t entry_status; /* Entry Status. */ | |
716 | ||
717 | uint32_t handle; /* System handle. */ | |
718 | ||
719 | uint16_t mbx[28]; | |
720 | }; | |
721 | ||
722 | ||
723 | #define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */ | |
724 | struct logio_entry_24xx { | |
725 | uint8_t entry_type; /* Entry type. */ | |
726 | uint8_t entry_count; /* Entry count. */ | |
727 | uint8_t sys_define; /* System defined. */ | |
728 | uint8_t entry_status; /* Entry Status. */ | |
729 | ||
730 | uint32_t handle; /* System handle. */ | |
731 | ||
732 | uint16_t comp_status; /* Completion status. */ | |
733 | #define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */ | |
734 | ||
735 | uint16_t nport_handle; /* N_PORT handle. */ | |
736 | ||
737 | uint16_t control_flags; /* Control flags. */ | |
738 | /* Modifiers. */ | |
c3a2f0df | 739 | #define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */ |
3d71644c AV |
740 | #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */ |
741 | #define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */ | |
742 | #define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */ | |
743 | #define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */ | |
744 | #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */ | |
745 | #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */ | |
746 | #define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */ | |
747 | #define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */ | |
748 | #define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */ | |
749 | /* Commands. */ | |
750 | #define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */ | |
751 | #define LCF_COMMAND_PRLI 0x01 /* PRLI. */ | |
752 | #define LCF_COMMAND_PDISC 0x02 /* PDISC. */ | |
753 | #define LCF_COMMAND_ADISC 0x03 /* ADISC. */ | |
754 | #define LCF_COMMAND_LOGO 0x08 /* LOGO. */ | |
755 | #define LCF_COMMAND_PRLO 0x09 /* PRLO. */ | |
756 | #define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */ | |
757 | ||
758 | uint8_t vp_index; | |
759 | uint8_t reserved_1; | |
760 | ||
761 | uint8_t port_id[3]; /* PortID of destination port. */ | |
762 | ||
763 | uint8_t rsp_size; /* Response size in 32bit words. */ | |
764 | ||
765 | uint32_t io_parameter[11]; /* General I/O parameters. */ | |
766 | #define LSC_SCODE_NOLINK 0x01 | |
767 | #define LSC_SCODE_NOIOCB 0x02 | |
768 | #define LSC_SCODE_NOXCB 0x03 | |
769 | #define LSC_SCODE_CMD_FAILED 0x04 | |
770 | #define LSC_SCODE_NOFABRIC 0x05 | |
771 | #define LSC_SCODE_FW_NOT_READY 0x07 | |
772 | #define LSC_SCODE_NOT_LOGGED_IN 0x09 | |
773 | #define LSC_SCODE_NOPCB 0x0A | |
774 | ||
775 | #define LSC_SCODE_ELS_REJECT 0x18 | |
776 | #define LSC_SCODE_CMD_PARAM_ERR 0x19 | |
777 | #define LSC_SCODE_PORTID_USED 0x1A | |
778 | #define LSC_SCODE_NPORT_USED 0x1B | |
779 | #define LSC_SCODE_NONPORT 0x1C | |
780 | #define LSC_SCODE_LOGGED_IN 0x1D | |
781 | #define LSC_SCODE_NOFLOGI_ACC 0x1F | |
782 | }; | |
783 | ||
784 | #define TSK_MGMT_IOCB_TYPE 0x14 | |
785 | struct tsk_mgmt_entry { | |
786 | uint8_t entry_type; /* Entry type. */ | |
787 | uint8_t entry_count; /* Entry count. */ | |
788 | uint8_t handle_count; /* Handle count. */ | |
789 | uint8_t entry_status; /* Entry Status. */ | |
790 | ||
791 | uint32_t handle; /* System handle. */ | |
792 | ||
793 | uint16_t nport_handle; /* N_PORT handle. */ | |
794 | ||
795 | uint16_t reserved_1; | |
796 | ||
797 | uint16_t delay; /* Activity delay in seconds. */ | |
798 | ||
799 | uint16_t timeout; /* Command timeout. */ | |
800 | ||
523ec773 | 801 | struct scsi_lun lun; /* FCP LUN (BE). */ |
3d71644c AV |
802 | |
803 | uint32_t control_flags; /* Control Flags. */ | |
804 | #define TCF_NOTMCMD_TO_TARGET BIT_31 | |
805 | #define TCF_LUN_RESET BIT_4 | |
806 | #define TCF_ABORT_TASK_SET BIT_3 | |
807 | #define TCF_CLEAR_TASK_SET BIT_2 | |
808 | #define TCF_TARGET_RESET BIT_1 | |
809 | #define TCF_CLEAR_ACA BIT_0 | |
810 | ||
811 | uint8_t reserved_2[20]; | |
812 | ||
813 | uint8_t port_id[3]; /* PortID of destination port. */ | |
814 | uint8_t vp_index; | |
815 | ||
816 | uint8_t reserved_3[12]; | |
817 | }; | |
818 | ||
819 | #define ABORT_IOCB_TYPE 0x33 | |
820 | struct abort_entry_24xx { | |
821 | uint8_t entry_type; /* Entry type. */ | |
822 | uint8_t entry_count; /* Entry count. */ | |
823 | uint8_t handle_count; /* Handle count. */ | |
824 | uint8_t entry_status; /* Entry Status. */ | |
825 | ||
826 | uint32_t handle; /* System handle. */ | |
827 | ||
828 | uint16_t nport_handle; /* N_PORT handle. */ | |
829 | /* or Completion status. */ | |
830 | ||
831 | uint16_t options; /* Options. */ | |
832 | #define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */ | |
833 | ||
834 | uint32_t handle_to_abort; /* System handle to abort. */ | |
835 | ||
73208dfd AC |
836 | uint16_t req_que_no; |
837 | uint8_t reserved_1[30]; | |
3d71644c AV |
838 | |
839 | uint8_t port_id[3]; /* PortID of destination port. */ | |
840 | uint8_t vp_index; | |
841 | ||
842 | uint8_t reserved_2[12]; | |
843 | }; | |
844 | ||
845 | /* | |
846 | * ISP I/O Register Set structure definitions. | |
847 | */ | |
848 | struct device_reg_24xx { | |
849 | uint32_t flash_addr; /* Flash/NVRAM BIOS address. */ | |
850 | #define FARX_DATA_FLAG BIT_31 | |
851 | #define FARX_ACCESS_FLASH_CONF 0x7FFD0000 | |
852 | #define FARX_ACCESS_FLASH_DATA 0x7FF00000 | |
853 | #define FARX_ACCESS_NVRAM_CONF 0x7FFF0000 | |
854 | #define FARX_ACCESS_NVRAM_DATA 0x7FFE0000 | |
855 | ||
856 | #define FA_NVRAM_FUNC0_ADDR 0x80 | |
857 | #define FA_NVRAM_FUNC1_ADDR 0x180 | |
858 | ||
6f641790 | 859 | #define FA_NVRAM_VPD_SIZE 0x200 |
3d71644c AV |
860 | #define FA_NVRAM_VPD0_ADDR 0x00 |
861 | #define FA_NVRAM_VPD1_ADDR 0x100 | |
b7cc176c JC |
862 | |
863 | #define FA_BOOT_CODE_ADDR 0x00000 | |
3d71644c AV |
864 | /* |
865 | * RISC code begins at offset 512KB | |
866 | * within flash. Consisting of two | |
867 | * contiguous RISC code segments. | |
868 | */ | |
869 | #define FA_RISC_CODE_ADDR 0x20000 | |
870 | #define FA_RISC_CODE_SEGMENTS 2 | |
871 | ||
c00d8994 AV |
872 | #define FA_FLASH_DESCR_ADDR_24 0x11000 |
873 | #define FA_FLASH_LAYOUT_ADDR_24 0x11400 | |
272976ca AV |
874 | #define FA_NPIV_CONF0_ADDR_24 0x16000 |
875 | #define FA_NPIV_CONF1_ADDR_24 0x17000 | |
c00d8994 | 876 | |
c3a2f0df AV |
877 | #define FA_FW_AREA_ADDR 0x40000 |
878 | #define FA_VPD_NVRAM_ADDR 0x48000 | |
879 | #define FA_FEATURE_ADDR 0x4C000 | |
880 | #define FA_FLASH_DESCR_ADDR 0x50000 | |
c00d8994 | 881 | #define FA_FLASH_LAYOUT_ADDR 0x50400 |
cb8dacbf | 882 | #define FA_HW_EVENT0_ADDR 0x54000 |
c00d8994 | 883 | #define FA_HW_EVENT1_ADDR 0x54400 |
cb8dacbf AV |
884 | #define FA_HW_EVENT_SIZE 0x200 |
885 | #define FA_HW_EVENT_ENTRY_SIZE 4 | |
272976ca AV |
886 | #define FA_NPIV_CONF0_ADDR 0x5C000 |
887 | #define FA_NPIV_CONF1_ADDR 0x5D000 | |
09ff701a SR |
888 | #define FA_FCP_PRIO0_ADDR 0x10000 |
889 | #define FA_FCP_PRIO1_ADDR 0x12000 | |
272976ca | 890 | |
cb8dacbf AV |
891 | /* |
892 | * Flash Error Log Event Codes. | |
893 | */ | |
894 | #define HW_EVENT_RESET_ERR 0xF00B | |
895 | #define HW_EVENT_ISP_ERR 0xF020 | |
896 | #define HW_EVENT_PARITY_ERR 0xF022 | |
897 | #define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023 | |
898 | #define HW_EVENT_FLASH_FW_ERR 0xF024 | |
899 | ||
3d71644c AV |
900 | uint32_t flash_data; /* Flash/NVRAM BIOS data. */ |
901 | ||
902 | uint32_t ctrl_status; /* Control/Status. */ | |
903 | #define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */ | |
904 | #define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */ | |
905 | #define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */ | |
906 | #define CSRX_FUNCTION BIT_15 /* Function number. */ | |
907 | /* PCI-X Bus Mode. */ | |
908 | #define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8) | |
909 | #define PBM_PCI_33MHZ (0 << 8) | |
910 | #define PBM_PCIX_M1_66MHZ (1 << 8) | |
911 | #define PBM_PCIX_M1_100MHZ (2 << 8) | |
912 | #define PBM_PCIX_M1_133MHZ (3 << 8) | |
913 | #define PBM_PCIX_M2_66MHZ (5 << 8) | |
914 | #define PBM_PCIX_M2_100MHZ (6 << 8) | |
915 | #define PBM_PCIX_M2_133MHZ (7 << 8) | |
916 | #define PBM_PCI_66MHZ (8 << 8) | |
917 | /* Max Write Burst byte count. */ | |
918 | #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4) | |
919 | #define MWB_512_BYTES (0 << 4) | |
920 | #define MWB_1024_BYTES (1 << 4) | |
921 | #define MWB_2048_BYTES (2 << 4) | |
922 | #define MWB_4096_BYTES (3 << 4) | |
923 | ||
924 | #define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */ | |
925 | #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */ | |
926 | #define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */ | |
927 | ||
928 | uint32_t ictrl; /* Interrupt control. */ | |
929 | #define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */ | |
930 | ||
931 | uint32_t istatus; /* Interrupt status. */ | |
932 | #define ISRX_RISC_INT BIT_3 /* RISC interrupt. */ | |
933 | ||
934 | uint32_t unused_1[2]; /* Gap. */ | |
935 | ||
936 | /* Request Queue. */ | |
937 | uint32_t req_q_in; /* In-Pointer. */ | |
938 | uint32_t req_q_out; /* Out-Pointer. */ | |
939 | /* Response Queue. */ | |
940 | uint32_t rsp_q_in; /* In-Pointer. */ | |
941 | uint32_t rsp_q_out; /* Out-Pointer. */ | |
942 | /* Priority Request Queue. */ | |
943 | uint32_t preq_q_in; /* In-Pointer. */ | |
944 | uint32_t preq_q_out; /* Out-Pointer. */ | |
945 | ||
946 | uint32_t unused_2[2]; /* Gap. */ | |
947 | ||
948 | /* ATIO Queue. */ | |
949 | uint32_t atio_q_in; /* In-Pointer. */ | |
950 | uint32_t atio_q_out; /* Out-Pointer. */ | |
951 | ||
952 | uint32_t host_status; | |
953 | #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */ | |
954 | #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */ | |
955 | ||
956 | uint32_t hccr; /* Host command & control register. */ | |
957 | /* HCCR statuses. */ | |
958 | #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */ | |
959 | #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */ | |
3d71644c AV |
960 | /* HCCR commands. */ |
961 | /* NOOP. */ | |
962 | #define HCCRX_NOOP 0x00000000 | |
963 | /* Set RISC Reset. */ | |
964 | #define HCCRX_SET_RISC_RESET 0x10000000 | |
965 | /* Clear RISC Reset. */ | |
966 | #define HCCRX_CLR_RISC_RESET 0x20000000 | |
967 | /* Set RISC Pause. */ | |
968 | #define HCCRX_SET_RISC_PAUSE 0x30000000 | |
969 | /* Releases RISC Pause. */ | |
970 | #define HCCRX_REL_RISC_PAUSE 0x40000000 | |
971 | /* Set HOST to RISC interrupt. */ | |
972 | #define HCCRX_SET_HOST_INT 0x50000000 | |
973 | /* Clear HOST to RISC interrupt. */ | |
974 | #define HCCRX_CLR_HOST_INT 0x60000000 | |
975 | /* Clear RISC to PCI interrupt. */ | |
976 | #define HCCRX_CLR_RISC_INT 0xA0000000 | |
977 | ||
978 | uint32_t gpiod; /* GPIO Data register. */ | |
c3a2f0df | 979 | |
3d71644c AV |
980 | /* LED update mask. */ |
981 | #define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18) | |
982 | /* Data update mask. */ | |
983 | #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16) | |
c3a2f0df AV |
984 | /* Data update mask. */ |
985 | #define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) | |
3d71644c AV |
986 | /* LED control mask. */ |
987 | #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2) | |
988 | /* LED bit values. Color names as | |
989 | * referenced in fw spec. | |
990 | */ | |
991 | #define GPDX_LED_YELLOW_ON BIT_2 | |
992 | #define GPDX_LED_GREEN_ON BIT_3 | |
993 | #define GPDX_LED_AMBER_ON BIT_4 | |
994 | /* Data in/out. */ | |
995 | #define GPDX_DATA_INOUT (BIT_1|BIT_0) | |
996 | ||
997 | uint32_t gpioe; /* GPIO Enable register. */ | |
998 | /* Enable update mask. */ | |
999 | #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16) | |
c3a2f0df AV |
1000 | /* Enable update mask. */ |
1001 | #define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) | |
3d71644c AV |
1002 | /* Enable. */ |
1003 | #define GPEX_ENABLE (BIT_1|BIT_0) | |
1004 | ||
1005 | uint32_t iobase_addr; /* I/O Bus Base Address register. */ | |
1006 | ||
1007 | uint32_t unused_3[10]; /* Gap. */ | |
1008 | ||
1009 | uint16_t mailbox0; | |
1010 | uint16_t mailbox1; | |
1011 | uint16_t mailbox2; | |
1012 | uint16_t mailbox3; | |
1013 | uint16_t mailbox4; | |
1014 | uint16_t mailbox5; | |
1015 | uint16_t mailbox6; | |
1016 | uint16_t mailbox7; | |
1017 | uint16_t mailbox8; | |
1018 | uint16_t mailbox9; | |
1019 | uint16_t mailbox10; | |
1020 | uint16_t mailbox11; | |
1021 | uint16_t mailbox12; | |
1022 | uint16_t mailbox13; | |
1023 | uint16_t mailbox14; | |
1024 | uint16_t mailbox15; | |
1025 | uint16_t mailbox16; | |
1026 | uint16_t mailbox17; | |
1027 | uint16_t mailbox18; | |
1028 | uint16_t mailbox19; | |
1029 | uint16_t mailbox20; | |
1030 | uint16_t mailbox21; | |
1031 | uint16_t mailbox22; | |
1032 | uint16_t mailbox23; | |
1033 | uint16_t mailbox24; | |
1034 | uint16_t mailbox25; | |
1035 | uint16_t mailbox26; | |
1036 | uint16_t mailbox27; | |
1037 | uint16_t mailbox28; | |
1038 | uint16_t mailbox29; | |
1039 | uint16_t mailbox30; | |
1040 | uint16_t mailbox31; | |
c3a2f0df AV |
1041 | |
1042 | uint32_t iobase_window; | |
b5836927 | 1043 | uint32_t iobase_c4; |
05236a05 AV |
1044 | uint32_t iobase_c8; |
1045 | uint32_t unused_4_1[6]; /* Gap. */ | |
c3a2f0df AV |
1046 | uint32_t iobase_q; |
1047 | uint32_t unused_5[2]; /* Gap. */ | |
1048 | uint32_t iobase_select; | |
1049 | uint32_t unused_6[2]; /* Gap. */ | |
1050 | uint32_t iobase_sdata; | |
3d71644c AV |
1051 | }; |
1052 | ||
00b6bd25 AV |
1053 | /* Trace Control *************************************************************/ |
1054 | ||
1055 | #define TC_AEN_DISABLE 0 | |
1056 | ||
1057 | #define TC_EFT_ENABLE 4 | |
1058 | #define TC_EFT_DISABLE 5 | |
1059 | ||
df613b96 AV |
1060 | #define TC_FCE_ENABLE 8 |
1061 | #define TC_FCE_OPTIONS 0 | |
1062 | #define TC_FCE_DEFAULT_RX_SIZE 2112 | |
1063 | #define TC_FCE_DEFAULT_TX_SIZE 2112 | |
1064 | #define TC_FCE_DISABLE 9 | |
1065 | #define TC_FCE_DISABLE_TRACE BIT_0 | |
1066 | ||
3d71644c AV |
1067 | /* MID Support ***************************************************************/ |
1068 | ||
eb66dc60 AV |
1069 | #define MIN_MULTI_ID_FABRIC 64 /* Must be power-of-2. */ |
1070 | #define MAX_MULTI_ID_FABRIC 256 /* ... */ | |
1071 | ||
1072 | #define for_each_mapped_vp_idx(_ha, _idx) \ | |
1073 | for (_idx = find_next_bit((_ha)->vp_idx_map, \ | |
1074 | (_ha)->max_npiv_vports + 1, 1); \ | |
1075 | _idx <= (_ha)->max_npiv_vports; \ | |
1076 | _idx = find_next_bit((_ha)->vp_idx_map, \ | |
1077 | (_ha)->max_npiv_vports + 1, _idx + 1)) \ | |
3d71644c AV |
1078 | |
1079 | struct mid_conf_entry_24xx { | |
1080 | uint16_t reserved_1; | |
1081 | ||
1082 | /* | |
1083 | * BIT 0 = Enable Hard Loop Id | |
1084 | * BIT 1 = Acquire Loop ID in LIPA | |
1085 | * BIT 2 = ID not Acquired | |
1086 | * BIT 3 = Enable VP | |
1087 | * BIT 4 = Enable Initiator Mode | |
1088 | * BIT 5 = Disable Target Mode | |
1089 | * BIT 6-7 = Reserved | |
1090 | */ | |
1091 | uint8_t options; | |
1092 | ||
1093 | uint8_t hard_address; | |
1094 | ||
1095 | uint8_t port_name[WWN_SIZE]; | |
1096 | uint8_t node_name[WWN_SIZE]; | |
1097 | }; | |
1098 | ||
1099 | struct mid_init_cb_24xx { | |
1100 | struct init_cb_24xx init_cb; | |
1101 | ||
1102 | uint16_t count; | |
1103 | uint16_t options; | |
1104 | ||
eb66dc60 | 1105 | struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC]; |
3d71644c AV |
1106 | }; |
1107 | ||
1108 | ||
1109 | struct mid_db_entry_24xx { | |
1110 | uint16_t status; | |
1111 | #define MDBS_NON_PARTIC BIT_3 | |
1112 | #define MDBS_ID_ACQUIRED BIT_1 | |
1113 | #define MDBS_ENABLED BIT_0 | |
1114 | ||
1115 | uint8_t options; | |
1116 | uint8_t hard_address; | |
1117 | ||
1118 | uint8_t port_name[WWN_SIZE]; | |
1119 | uint8_t node_name[WWN_SIZE]; | |
1120 | ||
1121 | uint8_t port_id[3]; | |
1122 | uint8_t reserved_1; | |
1123 | }; | |
1124 | ||
2c3dfe3f SJ |
1125 | /* |
1126 | * Virtual Port Control IOCB | |
1127 | */ | |
3d71644c AV |
1128 | #define VP_CTRL_IOCB_TYPE 0x30 /* Vitual Port Control entry. */ |
1129 | struct vp_ctrl_entry_24xx { | |
1130 | uint8_t entry_type; /* Entry type. */ | |
1131 | uint8_t entry_count; /* Entry count. */ | |
1132 | uint8_t sys_define; /* System defined. */ | |
1133 | uint8_t entry_status; /* Entry Status. */ | |
1134 | ||
1135 | uint32_t handle; /* System handle. */ | |
1136 | ||
1137 | uint16_t vp_idx_failed; | |
1138 | ||
1139 | uint16_t comp_status; /* Completion status. */ | |
2c3dfe3f | 1140 | #define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */ |
3d71644c AV |
1141 | #define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */ |
1142 | #define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */ | |
1143 | ||
1144 | uint16_t command; | |
1145 | #define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */ | |
1146 | #define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */ | |
1147 | #define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */ | |
1148 | #define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */ | |
2c3dfe3f | 1149 | #define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */ |
3d71644c AV |
1150 | |
1151 | uint16_t vp_count; | |
1152 | ||
1153 | uint8_t vp_idx_map[16]; | |
2c3dfe3f | 1154 | uint16_t flags; |
c6852c4c | 1155 | uint16_t id; |
2c3dfe3f | 1156 | uint16_t reserved_4; |
c6852c4c SJ |
1157 | uint16_t hopct; |
1158 | uint8_t reserved_5[24]; | |
3d71644c AV |
1159 | }; |
1160 | ||
2c3dfe3f SJ |
1161 | /* |
1162 | * Modify Virtual Port Configuration IOCB | |
1163 | */ | |
3d71644c AV |
1164 | #define VP_CONFIG_IOCB_TYPE 0x31 /* Vitual Port Config entry. */ |
1165 | struct vp_config_entry_24xx { | |
1166 | uint8_t entry_type; /* Entry type. */ | |
1167 | uint8_t entry_count; /* Entry count. */ | |
2c3dfe3f | 1168 | uint8_t handle_count; |
3d71644c AV |
1169 | uint8_t entry_status; /* Entry Status. */ |
1170 | ||
1171 | uint32_t handle; /* System handle. */ | |
1172 | ||
2c3dfe3f SJ |
1173 | uint16_t flags; |
1174 | #define CS_VF_BIND_VPORTS_TO_VF BIT_0 | |
1175 | #define CS_VF_SET_QOS_OF_VPORTS BIT_1 | |
1176 | #define CS_VF_SET_HOPS_OF_VPORTS BIT_2 | |
3d71644c AV |
1177 | |
1178 | uint16_t comp_status; /* Completion status. */ | |
1179 | #define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */ | |
1180 | #define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */ | |
1181 | #define CS_VCT_ERROR 0x03 /* Unknown error. */ | |
1182 | #define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */ | |
1183 | #define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */ | |
1184 | ||
1185 | uint8_t command; | |
2c3dfe3f SJ |
1186 | #define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */ |
1187 | #define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */ | |
3d71644c AV |
1188 | |
1189 | uint8_t vp_count; | |
1190 | ||
2c3dfe3f SJ |
1191 | uint8_t vp_index1; |
1192 | uint8_t vp_index2; | |
3d71644c AV |
1193 | |
1194 | uint8_t options_idx1; | |
1195 | uint8_t hard_address_idx1; | |
2c3dfe3f | 1196 | uint16_t reserved_vp1; |
3d71644c AV |
1197 | uint8_t port_name_idx1[WWN_SIZE]; |
1198 | uint8_t node_name_idx1[WWN_SIZE]; | |
1199 | ||
1200 | uint8_t options_idx2; | |
1201 | uint8_t hard_address_idx2; | |
2c3dfe3f | 1202 | uint16_t reserved_vp2; |
3d71644c AV |
1203 | uint8_t port_name_idx2[WWN_SIZE]; |
1204 | uint8_t node_name_idx2[WWN_SIZE]; | |
c6852c4c | 1205 | uint16_t id; |
2c3dfe3f | 1206 | uint16_t reserved_4; |
c6852c4c | 1207 | uint16_t hopct; |
f9e899eb | 1208 | uint8_t reserved_5[2]; |
3d71644c AV |
1209 | }; |
1210 | ||
1211 | #define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */ | |
1212 | struct vp_rpt_id_entry_24xx { | |
1213 | uint8_t entry_type; /* Entry type. */ | |
1214 | uint8_t entry_count; /* Entry count. */ | |
1215 | uint8_t sys_define; /* System defined. */ | |
1216 | uint8_t entry_status; /* Entry Status. */ | |
1217 | ||
1218 | uint32_t handle; /* System handle. */ | |
1219 | ||
1220 | uint16_t vp_count; /* Format 0 -- | VP setup | VP acq |. */ | |
1221 | /* Format 1 -- | VP count |. */ | |
1222 | uint16_t vp_idx; /* Format 0 -- Reserved. */ | |
1223 | /* Format 1 -- VP status and index. */ | |
1224 | ||
1225 | uint8_t port_id[3]; | |
1226 | uint8_t format; | |
1227 | ||
1228 | uint8_t vp_idx_map[16]; | |
1229 | ||
1230 | uint8_t reserved_4[32]; | |
1231 | }; | |
1232 | ||
2c3dfe3f SJ |
1233 | #define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */ |
1234 | struct vf_evfp_entry_24xx { | |
1235 | uint8_t entry_type; /* Entry type. */ | |
1236 | uint8_t entry_count; /* Entry count. */ | |
1237 | uint8_t sys_define; /* System defined. */ | |
1238 | uint8_t entry_status; /* Entry Status. */ | |
1239 | ||
1240 | uint32_t handle; /* System handle. */ | |
1241 | uint16_t comp_status; /* Completion status. */ | |
1242 | uint16_t timeout; /* timeout */ | |
1243 | uint16_t adim_tagging_mode; | |
1244 | ||
1245 | uint16_t vfport_id; | |
1246 | uint32_t exch_addr; | |
1247 | ||
1248 | uint16_t nport_handle; /* N_PORT handle. */ | |
1249 | uint16_t control_flags; | |
1250 | uint32_t io_parameter_0; | |
1251 | uint32_t io_parameter_1; | |
1252 | uint32_t tx_address[2]; /* Data segment 0 address. */ | |
1253 | uint32_t tx_len; /* Data segment 0 length. */ | |
1254 | uint32_t rx_address[2]; /* Data segment 1 address. */ | |
1255 | uint32_t rx_len; /* Data segment 1 length. */ | |
1256 | }; | |
1257 | ||
3d71644c | 1258 | /* END MID Support ***********************************************************/ |
7d232c74 AV |
1259 | |
1260 | /* Flash Description Table ***************************************************/ | |
1261 | ||
1262 | struct qla_fdt_layout { | |
1263 | uint8_t sig[4]; | |
1264 | uint16_t version; | |
1265 | uint16_t len; | |
1266 | uint16_t checksum; | |
1267 | uint8_t unused1[2]; | |
1268 | uint8_t model[16]; | |
1269 | uint16_t man_id; | |
1270 | uint16_t id; | |
1271 | uint8_t flags; | |
1272 | uint8_t erase_cmd; | |
1273 | uint8_t alt_erase_cmd; | |
1274 | uint8_t wrt_enable_cmd; | |
1275 | uint8_t wrt_enable_bits; | |
1276 | uint8_t wrt_sts_reg_cmd; | |
1277 | uint8_t unprotect_sec_cmd; | |
1278 | uint8_t read_man_id_cmd; | |
1279 | uint32_t block_size; | |
1280 | uint32_t alt_block_size; | |
1281 | uint32_t flash_size; | |
1282 | uint32_t wrt_enable_data; | |
1283 | uint8_t read_id_addr_len; | |
1284 | uint8_t wrt_disable_bits; | |
1285 | uint8_t read_dev_id_len; | |
1286 | uint8_t chip_erase_cmd; | |
1287 | uint16_t read_timeout; | |
1288 | uint8_t protect_sec_cmd; | |
1289 | uint8_t unused2[65]; | |
1290 | }; | |
4d4df193 | 1291 | |
c00d8994 AV |
1292 | /* Flash Layout Table ********************************************************/ |
1293 | ||
1294 | struct qla_flt_location { | |
1295 | uint8_t sig[4]; | |
3a03eb79 AV |
1296 | uint16_t start_lo; |
1297 | uint16_t start_hi; | |
1298 | uint8_t version; | |
1299 | uint8_t unused[5]; | |
c00d8994 AV |
1300 | uint16_t checksum; |
1301 | }; | |
1302 | ||
1303 | struct qla_flt_header { | |
1304 | uint16_t version; | |
1305 | uint16_t length; | |
1306 | uint16_t checksum; | |
1307 | uint16_t unused; | |
1308 | }; | |
1309 | ||
1310 | #define FLT_REG_FW 0x01 | |
1311 | #define FLT_REG_BOOT_CODE 0x07 | |
1312 | #define FLT_REG_VPD_0 0x14 | |
1313 | #define FLT_REG_NVRAM_0 0x15 | |
1314 | #define FLT_REG_VPD_1 0x16 | |
1315 | #define FLT_REG_NVRAM_1 0x17 | |
1316 | #define FLT_REG_FDT 0x1a | |
1317 | #define FLT_REG_FLT 0x1c | |
1318 | #define FLT_REG_HW_EVENT_0 0x1d | |
1319 | #define FLT_REG_HW_EVENT_1 0x1f | |
272976ca AV |
1320 | #define FLT_REG_NPIV_CONF_0 0x29 |
1321 | #define FLT_REG_NPIV_CONF_1 0x2a | |
cbc8eb67 | 1322 | #define FLT_REG_GOLD_FW 0x2f |
09ff701a SR |
1323 | #define FLT_REG_FCP_PRIO_0 0x87 |
1324 | #define FLT_REG_FCP_PRIO_1 0x88 | |
c00d8994 AV |
1325 | |
1326 | struct qla_flt_region { | |
1327 | uint32_t code; | |
1328 | uint32_t size; | |
1329 | uint32_t start; | |
1330 | uint32_t end; | |
1331 | }; | |
1332 | ||
272976ca AV |
1333 | /* Flash NPIV Configuration Table ********************************************/ |
1334 | ||
1335 | struct qla_npiv_header { | |
1336 | uint8_t sig[2]; | |
1337 | uint16_t version; | |
1338 | uint16_t entries; | |
1339 | uint16_t unused[4]; | |
1340 | uint16_t checksum; | |
1341 | }; | |
1342 | ||
1343 | struct qla_npiv_entry { | |
1344 | uint16_t flags; | |
1345 | uint16_t vf_id; | |
73208dfd AC |
1346 | uint8_t q_qos; |
1347 | uint8_t f_qos; | |
272976ca AV |
1348 | uint16_t unused1; |
1349 | uint8_t port_name[WWN_SIZE]; | |
1350 | uint8_t node_name[WWN_SIZE]; | |
1351 | }; | |
1352 | ||
4d4df193 HK |
1353 | /* 84XX Support **************************************************************/ |
1354 | ||
1355 | #define MBA_ISP84XX_ALERT 0x800f /* Alert Notification. */ | |
1356 | #define A84_PANIC_RECOVERY 0x1 | |
1357 | #define A84_OP_LOGIN_COMPLETE 0x2 | |
1358 | #define A84_DIAG_LOGIN_COMPLETE 0x3 | |
1359 | #define A84_GOLD_LOGIN_COMPLETE 0x4 | |
1360 | ||
1361 | #define MBC_ISP84XX_RESET 0x3a /* Reset. */ | |
1362 | ||
1363 | #define FSTATE_REMOTE_FC_DOWN BIT_0 | |
1364 | #define FSTATE_NSL_LINK_DOWN BIT_1 | |
1365 | #define FSTATE_IS_DIAG_FW BIT_2 | |
1366 | #define FSTATE_LOGGED_IN BIT_3 | |
1367 | #define FSTATE_WAITING_FOR_VERIFY BIT_4 | |
1368 | ||
1369 | #define VERIFY_CHIP_IOCB_TYPE 0x1B | |
1370 | struct verify_chip_entry_84xx { | |
1371 | uint8_t entry_type; | |
1372 | uint8_t entry_count; | |
1373 | uint8_t sys_defined; | |
1374 | uint8_t entry_status; | |
1375 | ||
1376 | uint32_t handle; | |
1377 | ||
1378 | uint16_t options; | |
1379 | #define VCO_DONT_UPDATE_FW BIT_0 | |
1380 | #define VCO_FORCE_UPDATE BIT_1 | |
1381 | #define VCO_DONT_RESET_UPDATE BIT_2 | |
1382 | #define VCO_DIAG_FW BIT_3 | |
1383 | #define VCO_END_OF_DATA BIT_14 | |
1384 | #define VCO_ENABLE_DSD BIT_15 | |
1385 | ||
1386 | uint16_t reserved_1; | |
1387 | ||
1388 | uint16_t data_seg_cnt; | |
1389 | uint16_t reserved_2[3]; | |
1390 | ||
1391 | uint32_t fw_ver; | |
1392 | uint32_t exchange_address; | |
1393 | ||
1394 | uint32_t reserved_3[3]; | |
1395 | uint32_t fw_size; | |
1396 | uint32_t fw_seq_size; | |
1397 | uint32_t relative_offset; | |
1398 | ||
1399 | uint32_t dseg_address[2]; | |
1400 | uint32_t dseg_length; | |
1401 | }; | |
1402 | ||
1403 | struct verify_chip_rsp_84xx { | |
1404 | uint8_t entry_type; | |
1405 | uint8_t entry_count; | |
1406 | uint8_t sys_defined; | |
1407 | uint8_t entry_status; | |
1408 | ||
1409 | uint32_t handle; | |
1410 | ||
1411 | uint16_t comp_status; | |
1412 | #define CS_VCS_CHIP_FAILURE 0x3 | |
1413 | #define CS_VCS_BAD_EXCHANGE 0x8 | |
1414 | #define CS_VCS_SEQ_COMPLETEi 0x40 | |
1415 | ||
1416 | uint16_t failure_code; | |
1417 | #define VFC_CHECKSUM_ERROR 0x1 | |
1418 | #define VFC_INVALID_LEN 0x2 | |
1419 | #define VFC_ALREADY_IN_PROGRESS 0x8 | |
1420 | ||
1421 | uint16_t reserved_1[4]; | |
1422 | ||
1423 | uint32_t fw_ver; | |
1424 | uint32_t exchange_address; | |
1425 | ||
1426 | uint32_t reserved_2[6]; | |
1427 | }; | |
1428 | ||
1429 | #define ACCESS_CHIP_IOCB_TYPE 0x2B | |
1430 | struct access_chip_84xx { | |
1431 | uint8_t entry_type; | |
1432 | uint8_t entry_count; | |
1433 | uint8_t sys_defined; | |
1434 | uint8_t entry_status; | |
1435 | ||
1436 | uint32_t handle; | |
1437 | ||
1438 | uint16_t options; | |
1439 | #define ACO_DUMP_MEMORY 0x0 | |
1440 | #define ACO_LOAD_MEMORY 0x1 | |
1441 | #define ACO_CHANGE_CONFIG_PARAM 0x2 | |
1442 | #define ACO_REQUEST_INFO 0x3 | |
1443 | ||
1444 | uint16_t reserved1; | |
1445 | ||
1446 | uint16_t dseg_count; | |
1447 | uint16_t reserved2[3]; | |
1448 | ||
1449 | uint32_t parameter1; | |
1450 | uint32_t parameter2; | |
1451 | uint32_t parameter3; | |
1452 | ||
1453 | uint32_t reserved3[3]; | |
1454 | uint32_t total_byte_cnt; | |
1455 | uint32_t reserved4; | |
1456 | ||
1457 | uint32_t dseg_address[2]; | |
1458 | uint32_t dseg_length; | |
1459 | }; | |
1460 | ||
1461 | struct access_chip_rsp_84xx { | |
1462 | uint8_t entry_type; | |
1463 | uint8_t entry_count; | |
1464 | uint8_t sys_defined; | |
1465 | uint8_t entry_status; | |
1466 | ||
1467 | uint32_t handle; | |
1468 | ||
1469 | uint16_t comp_status; | |
1470 | uint16_t failure_code; | |
1471 | uint32_t residual_count; | |
1472 | ||
1473 | uint32_t reserved[12]; | |
1474 | }; | |
3a03eb79 AV |
1475 | |
1476 | /* 81XX Support **************************************************************/ | |
1477 | ||
1478 | #define MBA_DCBX_START 0x8016 | |
1479 | #define MBA_DCBX_COMPLETE 0x8030 | |
1480 | #define MBA_FCF_CONF_ERR 0x8031 | |
1481 | #define MBA_DCBX_PARAM_UPDATE 0x8032 | |
1482 | #define MBA_IDC_COMPLETE 0x8100 | |
1483 | #define MBA_IDC_NOTIFY 0x8101 | |
1484 | #define MBA_IDC_TIME_EXT 0x8102 | |
1485 | ||
8a659571 | 1486 | #define MBC_IDC_ACK 0x101 |
6e181be5 | 1487 | #define MBC_RESTART_MPI_FW 0x3d |
1d2874de | 1488 | #define MBC_FLASH_ACCESS_CTRL 0x3e /* Control flash access. */ |
ce0423f4 | 1489 | #define MBC_GET_XGMAC_STATS 0x7a |
11bbc1d8 | 1490 | #define MBC_GET_DCBX_PARAMS 0x51 |
1d2874de JC |
1491 | |
1492 | /* Flash access control option field bit definitions */ | |
1493 | #define FAC_OPT_FORCE_SEMAPHORE BIT_15 | |
1494 | #define FAC_OPT_REQUESTOR_ID BIT_14 | |
1495 | #define FAC_OPT_CMD_SUBCODE 0xff | |
1496 | ||
1497 | /* Flash access control command subcodes */ | |
1498 | #define FAC_OPT_CMD_WRITE_PROTECT 0x00 | |
1499 | #define FAC_OPT_CMD_WRITE_ENABLE 0x01 | |
1500 | #define FAC_OPT_CMD_ERASE_SECTOR 0x02 | |
1501 | #define FAC_OPT_CMD_LOCK_SEMAPHORE 0x03 | |
1502 | #define FAC_OPT_CMD_UNLOCK_SEMAPHORE 0x04 | |
1503 | #define FAC_OPT_CMD_GET_SECTOR_SIZE 0x05 | |
8a659571 | 1504 | |
3a03eb79 AV |
1505 | struct nvram_81xx { |
1506 | /* NVRAM header. */ | |
1507 | uint8_t id[4]; | |
1508 | uint16_t nvram_version; | |
1509 | uint16_t reserved_0; | |
1510 | ||
1511 | /* Firmware Initialization Control Block. */ | |
1512 | uint16_t version; | |
1513 | uint16_t reserved_1; | |
1514 | uint16_t frame_payload_size; | |
1515 | uint16_t execution_throttle; | |
1516 | uint16_t exchange_count; | |
1517 | uint16_t reserved_2; | |
1518 | ||
1519 | uint8_t port_name[WWN_SIZE]; | |
1520 | uint8_t node_name[WWN_SIZE]; | |
1521 | ||
1522 | uint16_t login_retry_count; | |
1523 | uint16_t reserved_3; | |
1524 | uint16_t interrupt_delay_timer; | |
1525 | uint16_t login_timeout; | |
1526 | ||
1527 | uint32_t firmware_options_1; | |
1528 | uint32_t firmware_options_2; | |
1529 | uint32_t firmware_options_3; | |
1530 | ||
1531 | uint16_t reserved_4[4]; | |
1532 | ||
1533 | /* Offset 64. */ | |
1534 | uint8_t enode_mac[6]; | |
1535 | uint16_t reserved_5[5]; | |
1536 | ||
1537 | /* Offset 80. */ | |
1538 | uint16_t reserved_6[24]; | |
1539 | ||
1540 | /* Offset 128. */ | |
b64b0e8f AV |
1541 | uint16_t ex_version; |
1542 | uint8_t prio_fcf_matching_flags; | |
1543 | uint8_t reserved_6_1[3]; | |
1544 | uint16_t pri_fcf_vlan_id; | |
1545 | uint8_t pri_fcf_fabric_name[8]; | |
1546 | uint16_t reserved_6_2[7]; | |
1547 | uint8_t spma_mac_addr[6]; | |
1548 | uint16_t reserved_6_3[14]; | |
1549 | ||
1550 | /* Offset 192. */ | |
1551 | uint16_t reserved_7[32]; | |
3a03eb79 AV |
1552 | |
1553 | /* | |
1554 | * BIT 0 = Enable spinup delay | |
1555 | * BIT 1 = Disable BIOS | |
1556 | * BIT 2 = Enable Memory Map BIOS | |
1557 | * BIT 3 = Enable Selectable Boot | |
1558 | * BIT 4 = Disable RISC code load | |
1559 | * BIT 5 = Disable Serdes | |
1560 | * BIT 6 = Opt boot mode | |
1561 | * BIT 7 = Interrupt enable | |
1562 | * | |
1563 | * BIT 8 = EV Control enable | |
1564 | * BIT 9 = Enable lip reset | |
1565 | * BIT 10 = Enable lip full login | |
1566 | * BIT 11 = Enable target reset | |
1567 | * BIT 12 = Stop firmware | |
1568 | * BIT 13 = Enable nodename option | |
1569 | * BIT 14 = Default WWPN valid | |
1570 | * BIT 15 = Enable alternate WWN | |
1571 | * | |
1572 | * BIT 16 = CLP LUN string | |
1573 | * BIT 17 = CLP Target string | |
1574 | * BIT 18 = CLP BIOS enable string | |
1575 | * BIT 19 = CLP Serdes string | |
1576 | * BIT 20 = CLP WWPN string | |
1577 | * BIT 21 = CLP WWNN string | |
1578 | * BIT 22 = | |
1579 | * BIT 23 = | |
1580 | * BIT 24 = Keep WWPN | |
1581 | * BIT 25 = Temp WWPN | |
1582 | * BIT 26-31 = | |
1583 | */ | |
1584 | uint32_t host_p; | |
1585 | ||
1586 | uint8_t alternate_port_name[WWN_SIZE]; | |
1587 | uint8_t alternate_node_name[WWN_SIZE]; | |
1588 | ||
1589 | uint8_t boot_port_name[WWN_SIZE]; | |
1590 | uint16_t boot_lun_number; | |
1591 | uint16_t reserved_8; | |
1592 | ||
1593 | uint8_t alt1_boot_port_name[WWN_SIZE]; | |
1594 | uint16_t alt1_boot_lun_number; | |
1595 | uint16_t reserved_9; | |
1596 | ||
1597 | uint8_t alt2_boot_port_name[WWN_SIZE]; | |
1598 | uint16_t alt2_boot_lun_number; | |
1599 | uint16_t reserved_10; | |
1600 | ||
1601 | uint8_t alt3_boot_port_name[WWN_SIZE]; | |
1602 | uint16_t alt3_boot_lun_number; | |
1603 | uint16_t reserved_11; | |
1604 | ||
1605 | /* | |
1606 | * BIT 0 = Selective Login | |
1607 | * BIT 1 = Alt-Boot Enable | |
1608 | * BIT 2 = Reserved | |
1609 | * BIT 3 = Boot Order List | |
1610 | * BIT 4 = Reserved | |
1611 | * BIT 5 = Selective LUN | |
1612 | * BIT 6 = Reserved | |
1613 | * BIT 7-31 = | |
1614 | */ | |
1615 | uint32_t efi_parameters; | |
1616 | ||
1617 | uint8_t reset_delay; | |
1618 | uint8_t reserved_12; | |
1619 | uint16_t reserved_13; | |
1620 | ||
1621 | uint16_t boot_id_number; | |
1622 | uint16_t reserved_14; | |
1623 | ||
1624 | uint16_t max_luns_per_target; | |
1625 | uint16_t reserved_15; | |
1626 | ||
1627 | uint16_t port_down_retry_count; | |
1628 | uint16_t link_down_timeout; | |
1629 | ||
1630 | /* FCode parameters. */ | |
1631 | uint16_t fcode_parameter; | |
1632 | ||
1633 | uint16_t reserved_16[3]; | |
1634 | ||
1635 | /* Offset 352. */ | |
1636 | uint8_t reserved_17[4]; | |
1637 | uint16_t reserved_18[5]; | |
1638 | uint8_t reserved_19[2]; | |
1639 | uint16_t reserved_20[8]; | |
1640 | ||
1641 | /* Offset 384. */ | |
1642 | uint8_t reserved_21[16]; | |
cad454b1 SV |
1643 | uint16_t reserved_22[3]; |
1644 | ||
1645 | /* | |
1646 | * BIT 0 = Extended BB credits for LR | |
1647 | * BIT 1 = Virtual Fabric Enable | |
1648 | * BIT 2 = Enhanced Features Unused | |
1649 | * BIT 3-7 = Enhanced Features Reserved | |
1650 | */ | |
1651 | /* Enhanced Features */ | |
1652 | uint8_t enhanced_features; | |
1653 | ||
1654 | uint8_t reserved_23; | |
1655 | uint16_t reserved_24[4]; | |
3a03eb79 AV |
1656 | |
1657 | /* Offset 416. */ | |
cad454b1 | 1658 | uint16_t reserved_25[32]; |
3a03eb79 AV |
1659 | |
1660 | /* Offset 480. */ | |
1661 | uint8_t model_name[16]; | |
1662 | ||
1663 | /* Offset 496. */ | |
1664 | uint16_t feature_mask_l; | |
1665 | uint16_t feature_mask_h; | |
cad454b1 | 1666 | uint16_t reserved_26[2]; |
3a03eb79 AV |
1667 | |
1668 | uint16_t subsystem_vendor_id; | |
1669 | uint16_t subsystem_device_id; | |
1670 | ||
1671 | uint32_t checksum; | |
1672 | }; | |
1673 | ||
1674 | /* | |
1675 | * ISP Initialization Control Block. | |
1676 | * Little endian except where noted. | |
1677 | */ | |
1678 | #define ICB_VERSION 1 | |
1679 | struct init_cb_81xx { | |
1680 | uint16_t version; | |
1681 | uint16_t reserved_1; | |
1682 | ||
1683 | uint16_t frame_payload_size; | |
1684 | uint16_t execution_throttle; | |
1685 | uint16_t exchange_count; | |
1686 | ||
1687 | uint16_t reserved_2; | |
1688 | ||
1689 | uint8_t port_name[WWN_SIZE]; /* Big endian. */ | |
1690 | uint8_t node_name[WWN_SIZE]; /* Big endian. */ | |
1691 | ||
1692 | uint16_t response_q_inpointer; | |
1693 | uint16_t request_q_outpointer; | |
1694 | ||
1695 | uint16_t login_retry_count; | |
1696 | ||
1697 | uint16_t prio_request_q_outpointer; | |
1698 | ||
1699 | uint16_t response_q_length; | |
1700 | uint16_t request_q_length; | |
1701 | ||
1702 | uint16_t reserved_3; | |
1703 | ||
1704 | uint16_t prio_request_q_length; | |
1705 | ||
1706 | uint32_t request_q_address[2]; | |
1707 | uint32_t response_q_address[2]; | |
1708 | uint32_t prio_request_q_address[2]; | |
1709 | ||
1710 | uint8_t reserved_4[8]; | |
1711 | ||
1712 | uint16_t atio_q_inpointer; | |
1713 | uint16_t atio_q_length; | |
1714 | uint32_t atio_q_address[2]; | |
1715 | ||
1716 | uint16_t interrupt_delay_timer; /* 100us increments. */ | |
1717 | uint16_t login_timeout; | |
1718 | ||
1719 | /* | |
1720 | * BIT 0-3 = Reserved | |
1721 | * BIT 4 = Enable Target Mode | |
1722 | * BIT 5 = Disable Initiator Mode | |
1723 | * BIT 6 = Reserved | |
1724 | * BIT 7 = Reserved | |
1725 | * | |
1726 | * BIT 8-13 = Reserved | |
1727 | * BIT 14 = Node Name Option | |
1728 | * BIT 15-31 = Reserved | |
1729 | */ | |
1730 | uint32_t firmware_options_1; | |
1731 | ||
1732 | /* | |
1733 | * BIT 0 = Operation Mode bit 0 | |
1734 | * BIT 1 = Operation Mode bit 1 | |
1735 | * BIT 2 = Operation Mode bit 2 | |
1736 | * BIT 3 = Operation Mode bit 3 | |
1737 | * BIT 4-7 = Reserved | |
1738 | * | |
1739 | * BIT 8 = Enable Class 2 | |
1740 | * BIT 9 = Enable ACK0 | |
1741 | * BIT 10 = Reserved | |
1742 | * BIT 11 = Enable FC-SP Security | |
1743 | * BIT 12 = FC Tape Enable | |
1744 | * BIT 13 = Reserved | |
1745 | * BIT 14 = Enable Target PRLI Control | |
1746 | * BIT 15-31 = Reserved | |
1747 | */ | |
1748 | uint32_t firmware_options_2; | |
1749 | ||
1750 | /* | |
1751 | * BIT 0-3 = Reserved | |
1752 | * BIT 4 = FCP RSP Payload bit 0 | |
1753 | * BIT 5 = FCP RSP Payload bit 1 | |
1754 | * BIT 6 = Enable Receive Out-of-Order data frame handling | |
1755 | * BIT 7 = Reserved | |
1756 | * | |
1757 | * BIT 8 = Reserved | |
1758 | * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling | |
1759 | * BIT 10-16 = Reserved | |
1760 | * BIT 17 = Enable multiple FCFs | |
1761 | * BIT 18-20 = MAC addressing mode | |
1762 | * BIT 21-25 = Ethernet data rate | |
1763 | * BIT 26 = Enable ethernet header rx IOCB for ATIO q | |
1764 | * BIT 27 = Enable ethernet header rx IOCB for response q | |
1765 | * BIT 28 = SPMA selection bit 0 | |
1766 | * BIT 28 = SPMA selection bit 1 | |
1767 | * BIT 30-31 = Reserved | |
1768 | */ | |
1769 | uint32_t firmware_options_3; | |
1770 | ||
1771 | uint8_t reserved_5[8]; | |
1772 | ||
1773 | uint8_t enode_mac[6]; | |
1774 | ||
1775 | uint8_t reserved_6[10]; | |
1776 | }; | |
1777 | ||
1778 | struct mid_init_cb_81xx { | |
1779 | struct init_cb_81xx init_cb; | |
1780 | ||
1781 | uint16_t count; | |
1782 | uint16_t options; | |
1783 | ||
1784 | struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC]; | |
1785 | }; | |
1786 | ||
b64b0e8f AV |
1787 | struct ex_init_cb_81xx { |
1788 | uint16_t ex_version; | |
1789 | uint8_t prio_fcf_matching_flags; | |
1790 | uint8_t reserved_1[3]; | |
1791 | uint16_t pri_fcf_vlan_id; | |
1792 | uint8_t pri_fcf_fabric_name[8]; | |
1793 | uint16_t reserved_2[7]; | |
1794 | uint8_t spma_mac_addr[6]; | |
1795 | uint16_t reserved_3[14]; | |
1796 | }; | |
1797 | ||
3a03eb79 AV |
1798 | #define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000 |
1799 | #define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000 | |
1800 | ||
09ff701a SR |
1801 | /* FCP priority config defines *************************************/ |
1802 | /* operations */ | |
1803 | #define QLFC_FCP_PRIO_DISABLE 0x0 | |
1804 | #define QLFC_FCP_PRIO_ENABLE 0x1 | |
1805 | #define QLFC_FCP_PRIO_GET_CONFIG 0x2 | |
1806 | #define QLFC_FCP_PRIO_SET_CONFIG 0x3 | |
1807 | ||
1808 | struct qla_fcp_prio_entry { | |
1809 | uint16_t flags; /* Describes parameter(s) in FCP */ | |
1810 | /* priority entry that are valid */ | |
1811 | #define FCP_PRIO_ENTRY_VALID 0x1 | |
1812 | #define FCP_PRIO_ENTRY_TAG_VALID 0x2 | |
1813 | #define FCP_PRIO_ENTRY_SPID_VALID 0x4 | |
1814 | #define FCP_PRIO_ENTRY_DPID_VALID 0x8 | |
1815 | #define FCP_PRIO_ENTRY_LUNB_VALID 0x10 | |
1816 | #define FCP_PRIO_ENTRY_LUNE_VALID 0x20 | |
1817 | #define FCP_PRIO_ENTRY_SWWN_VALID 0x40 | |
1818 | #define FCP_PRIO_ENTRY_DWWN_VALID 0x80 | |
1819 | uint8_t tag; /* Priority value */ | |
1820 | uint8_t reserved; /* Reserved for future use */ | |
1821 | uint32_t src_pid; /* Src port id. high order byte */ | |
1822 | /* unused; -1 (wild card) */ | |
1823 | uint32_t dst_pid; /* Src port id. high order byte */ | |
1824 | /* unused; -1 (wild card) */ | |
1825 | uint16_t lun_beg; /* 1st lun num of lun range. */ | |
1826 | /* -1 (wild card) */ | |
1827 | uint16_t lun_end; /* 2nd lun num of lun range. */ | |
1828 | /* -1 (wild card) */ | |
1829 | uint8_t src_wwpn[8]; /* Source WWPN: -1 (wild card) */ | |
1830 | uint8_t dst_wwpn[8]; /* Destination WWPN: -1 (wild card) */ | |
1831 | }; | |
1832 | ||
1833 | struct qla_fcp_prio_cfg { | |
1834 | uint8_t signature[4]; /* "HQOS" signature of config data */ | |
1835 | uint16_t version; /* 1: Initial version */ | |
1836 | uint16_t length; /* config data size in num bytes */ | |
1837 | uint16_t checksum; /* config data bytes checksum */ | |
1838 | uint16_t num_entries; /* Number of entries */ | |
1839 | uint16_t size_of_entry; /* Size of each entry in num bytes */ | |
1840 | uint8_t attributes; /* enable/disable, persistence */ | |
1841 | #define FCP_PRIO_ATTR_DISABLE 0x0 | |
1842 | #define FCP_PRIO_ATTR_ENABLE 0x1 | |
1843 | #define FCP_PRIO_ATTR_PERSIST 0x2 | |
1844 | uint8_t reserved; /* Reserved for future use */ | |
1845 | #define FCP_PRIO_CFG_HDR_SIZE 0x10 | |
1846 | struct qla_fcp_prio_entry entry[1]; /* fcp priority entries */ | |
1847 | #define FCP_PRIO_CFG_ENTRY_SIZE 0x20 | |
1848 | }; | |
1849 | ||
1850 | #define FCP_PRIO_CFG_SIZE (32*1024) /* fcp prio data per port*/ | |
1851 | ||
1852 | /* 25XX Support ****************************************************/ | |
1853 | #define FA_FCP_PRIO0_ADDR_25 0x3C000 | |
1854 | #define FA_FCP_PRIO1_ADDR_25 0x3E000 | |
1855 | ||
3a03eb79 AV |
1856 | /* 81XX Flash locations -- occupies second 2MB region. */ |
1857 | #define FA_BOOT_CODE_ADDR_81 0x80000 | |
1858 | #define FA_RISC_CODE_ADDR_81 0xA0000 | |
1859 | #define FA_FW_AREA_ADDR_81 0xC0000 | |
1860 | #define FA_VPD_NVRAM_ADDR_81 0xD0000 | |
3d79038f AV |
1861 | #define FA_VPD0_ADDR_81 0xD0000 |
1862 | #define FA_VPD1_ADDR_81 0xD0400 | |
1863 | #define FA_NVRAM0_ADDR_81 0xD0080 | |
fc3ea9bc | 1864 | #define FA_NVRAM1_ADDR_81 0xD0180 |
3a03eb79 AV |
1865 | #define FA_FEATURE_ADDR_81 0xD4000 |
1866 | #define FA_FLASH_DESCR_ADDR_81 0xD8000 | |
1867 | #define FA_FLASH_LAYOUT_ADDR_81 0xD8400 | |
1868 | #define FA_HW_EVENT0_ADDR_81 0xDC000 | |
1869 | #define FA_HW_EVENT1_ADDR_81 0xDC400 | |
1870 | #define FA_NPIV_CONF0_ADDR_81 0xD1000 | |
1871 | #define FA_NPIV_CONF1_ADDR_81 0xD2000 | |
1872 | ||
3d71644c | 1873 | #endif |