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[SCSI] qla2xxx: use kthread_ API
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_def.h
CommitLineData
fa90c54f
AV		 1/*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
1da177e4
LT		 7#ifndef __QLA_DEF_H
8#define __QLA_DEF_H
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/completion.h>
abbd8870 23#include <linux/interrupt.h>
19a7b4ae 24#include <linux/workqueue.h>
5433383e 25#include <linux/firmware.h>
1da177e4
LT		 26#include <asm/semaphore.h>
27
28#include <scsi/scsi.h>
29#include <scsi/scsi_host.h>
30#include <scsi/scsi_device.h>
31#include <scsi/scsi_cmnd.h>
392e2f65 32#include <scsi/scsi_transport_fc.h>
1da177e4 33
5433383e 34#if defined(CONFIG_SCSI_QLA2XXX_EMBEDDED_FIRMWARE)
1da177e4
LT		 35#if defined(CONFIG_SCSI_QLA21XX) || defined(CONFIG_SCSI_QLA21XX_MODULE)
36#define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
37#else
38#define IS_QLA2100(ha) 0
39#endif
40
41#if defined(CONFIG_SCSI_QLA22XX) || defined(CONFIG_SCSI_QLA22XX_MODULE)
42#define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
43#else
44#define IS_QLA2200(ha) 0
45#endif
46
47#if defined(CONFIG_SCSI_QLA2300) || defined(CONFIG_SCSI_QLA2300_MODULE)
48#define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
49#define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
50#else
51#define IS_QLA2300(ha) 0
52#define IS_QLA2312(ha) 0
53#endif
54
55#if defined(CONFIG_SCSI_QLA2322) || defined(CONFIG_SCSI_QLA2322_MODULE)
56#define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
57#else
58#define IS_QLA2322(ha) 0
59#endif
60
61#if defined(CONFIG_SCSI_QLA6312) || defined(CONFIG_SCSI_QLA6312_MODULE)
62#define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
63#define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
64#else
65#define IS_QLA6312(ha) 0
66#define IS_QLA6322(ha) 0
67#endif
68
3d71644c
AV		 69#if defined(CONFIG_SCSI_QLA24XX) || defined(CONFIG_SCSI_QLA24XX_MODULE)
70#define IS_QLA2422(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422)
71#define IS_QLA2432(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432)
72#else
73#define IS_QLA2422(ha) 0
74#define IS_QLA2432(ha) 0
75#endif
76
77#if defined(CONFIG_SCSI_QLA25XX) || defined(CONFIG_SCSI_QLA25XX_MODULE)
78#define IS_QLA2512(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2512)
79#define IS_QLA2522(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2522)
80#else
81#define IS_QLA2512(ha) 0
82#define IS_QLA2522(ha) 0
83#endif
84
5433383e
AV		 85#else /* !defined(CONFIG_SCSI_QLA2XXX_EMBEDDED_FIRMWARE) */
86
87#define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
88#define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
89#define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
90#define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
91#define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
92#define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
93#define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
94#define IS_QLA2422(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422)
95#define IS_QLA2432(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432)
96#define IS_QLA2512(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2512)
97#define IS_QLA2522(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2522)
98#endif
99
1da177e4
LT		 100#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
101 IS_QLA6312(ha) || IS_QLA6322(ha))
3d71644c
AV		 102#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
103#define IS_QLA25XX(ha) (IS_QLA2512(ha) || IS_QLA2522(ha))
104
1da177e4
LT		 105/*
106 * Only non-ISP2[12]00 have extended addressing support in the firmware.
107 */
108#define HAS_EXTENDED_IDS(ha) (!IS_QLA2100(ha) && !IS_QLA2200(ha))
109
110/*
111 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
112 * but that's fine as we don't look at the last 24 ones for
113 * ISP2100 HBAs.
114 */
115#define MAILBOX_REGISTER_COUNT_2100 8
116#define MAILBOX_REGISTER_COUNT 32
117
118#define QLA2200A_RISC_ROM_VER 4
119#define FPM_2300 6
120#define FPM_2310 7
121
122#include "qla_settings.h"
123
fa2a1ce5 124/*
1da177e4
LT		 125 * Data bit definitions
126 */
127#define BIT_0 0x1
128#define BIT_1 0x2
129#define BIT_2 0x4
130#define BIT_3 0x8
131#define BIT_4 0x10
132#define BIT_5 0x20
133#define BIT_6 0x40
134#define BIT_7 0x80
135#define BIT_8 0x100
136#define BIT_9 0x200
137#define BIT_10 0x400
138#define BIT_11 0x800
139#define BIT_12 0x1000
140#define BIT_13 0x2000
141#define BIT_14 0x4000
142#define BIT_15 0x8000
143#define BIT_16 0x10000
144#define BIT_17 0x20000
145#define BIT_18 0x40000
146#define BIT_19 0x80000
147#define BIT_20 0x100000
148#define BIT_21 0x200000
149#define BIT_22 0x400000
150#define BIT_23 0x800000
151#define BIT_24 0x1000000
152#define BIT_25 0x2000000
153#define BIT_26 0x4000000
154#define BIT_27 0x8000000
155#define BIT_28 0x10000000
156#define BIT_29 0x20000000
157#define BIT_30 0x40000000
158#define BIT_31 0x80000000
159
160#define LSB(x) ((uint8_t)(x))
161#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
162
163#define LSW(x) ((uint16_t)(x))
164#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
165
166#define LSD(x) ((uint32_t)((uint64_t)(x)))
167#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
168
169
170/*
171 * I/O register
172*/
173
174#define RD_REG_BYTE(addr) readb(addr)
175#define RD_REG_WORD(addr) readw(addr)
176#define RD_REG_DWORD(addr) readl(addr)
177#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
178#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
179#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
180#define WRT_REG_BYTE(addr, data) writeb(data,addr)
181#define WRT_REG_WORD(addr, data) writew(data,addr)
182#define WRT_REG_DWORD(addr, data) writel(data,addr)
183
f6df144c 184/*
185 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
186 * 133Mhz slot.
187 */
188#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
189#define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
190
1da177e4
LT		 191/*
192 * Fibre Channel device definitions.
193 */
194#define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
195#define MAX_FIBRE_DEVICES 512
cc4731f5 196#define MAX_FIBRE_LUNS 0xFFFF
1da177e4
LT		 197#define MAX_RSCN_COUNT 32
198#define MAX_HOST_COUNT 16
199
200/*
201 * Host adapter default definitions.
202 */
203#define MAX_BUSES 1 /* We only have one bus today */
204#define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
205#define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
1da177e4
LT		 206#define MIN_LUNS 8
207#define MAX_LUNS MAX_FIBRE_LUNS
fa2a1ce5
AV		 208#define MAX_CMDS_PER_LUN 255
209
1da177e4
LT		 210/*
211 * Fibre Channel device definitions.
212 */
213#define SNS_LAST_LOOP_ID_2100 0xfe
214#define SNS_LAST_LOOP_ID_2300 0x7ff
215
216#define LAST_LOCAL_LOOP_ID 0x7d
217#define SNS_FL_PORT 0x7e
218#define FABRIC_CONTROLLER 0x7f
219#define SIMPLE_NAME_SERVER 0x80
220#define SNS_FIRST_LOOP_ID 0x81
221#define MANAGEMENT_SERVER 0xfe
222#define BROADCAST 0xff
223
3d71644c
AV		 224/*
225 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
226 * valid range of an N-PORT id is 0 through 0x7ef.
227 */
228#define NPH_LAST_HANDLE 0x7ef
cca5335c 229#define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
3d71644c
AV		 230#define NPH_SNS 0x7fc /* FFFFFC */
231#define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
232#define NPH_F_PORT 0x7fe /* FFFFFE */
233#define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
234
235#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
236#include "qla_fw.h"
1da177e4
LT		 237
238/*
239 * Timeout timer counts in seconds
240 */
8482e118 241#define PORT_RETRY_TIME 1
1da177e4
LT		 242#define LOOP_DOWN_TIMEOUT 60
243#define LOOP_DOWN_TIME 255 /* 240 */
244#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
245
246/* Maximum outstanding commands in ISP queues (1-65535) */
247#define MAX_OUTSTANDING_COMMANDS 1024
248
249/* ISP request and response entry counts (37-65535) */
250#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
251#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
252#define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
3d71644c 253#define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
1da177e4
LT		 254#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
255#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
256
257/*
fa2a1ce5 258 * SCSI Request Block
1da177e4
LT		 259 */
260typedef struct srb {
261 struct list_head list;
262
263 struct scsi_qla_host *ha; /* HA the SP is queued on */
bdf79621 264 struct fc_port *fcport;
1da177e4
LT		 265
266 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
267
268 struct timer_list timer; /* Command timer */
fa2a1ce5 269 atomic_t ref_count; /* Reference count for this structure */
1da177e4
LT		 270 uint16_t flags;
271
272 /* Request state */
273 uint16_t state;
274
1da177e4
LT		 275 /* Single transfer DMA context */
276 dma_addr_t dma_handle;
277
278 uint32_t request_sense_length;
279 uint8_t *request_sense_ptr;
280
1da177e4
LT		 281 /* SRB magic number */
282 uint16_t magic;
283#define SRB_MAGIC 0x10CB
284} srb_t;
285
286/*
287 * SRB flag definitions
288 */
289#define SRB_TIMEOUT BIT_0 /* Command timed out */
290#define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
291#define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
292#define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
293
294#define SRB_ABORTED BIT_4 /* Command aborted command already */
295#define SRB_RETRY BIT_5 /* Command needs retrying */
296#define SRB_GOT_SENSE BIT_6 /* Command has sense data */
297#define SRB_FAILOVER BIT_7 /* Command in failover state */
298
299#define SRB_BUSY BIT_8 /* Command is in busy retry state */
300#define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
301#define SRB_IOCTL BIT_10 /* IOCTL command. */
302#define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
303
304/*
305 * SRB state definitions
306 */
307#define SRB_FREE_STATE 0 /* returned back */
308#define SRB_PENDING_STATE 1 /* queued in LUN Q */
309#define SRB_ACTIVE_STATE 2 /* in Active Array */
310#define SRB_DONE_STATE 3 /* queued in Done Queue */
311#define SRB_RETRY_STATE 4 /* in Retry Queue */
312#define SRB_SUSPENDED_STATE 5 /* in suspended state */
313#define SRB_NO_QUEUE_STATE 6 /* is in between states */
314#define SRB_ACTIVE_TIMEOUT_STATE 7 /* in Active Array but timed out */
315#define SRB_FAILOVER_STATE 8 /* in Failover Queue */
316#define SRB_SCSI_RETRY_STATE 9 /* in Scsi Retry Queue */
317
318
319/*
320 * ISP I/O Register Set structure definitions.
321 */
3d71644c
AV		 322struct device_reg_2xxx {
323 uint16_t flash_address; /* Flash BIOS address */
324 uint16_t flash_data; /* Flash BIOS data */
1da177e4 325 uint16_t unused_1[1]; /* Gap */
3d71644c 326 uint16_t ctrl_status; /* Control/Status */
fa2a1ce5 327#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
1da177e4
LT		 328#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
329#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
330
3d71644c 331 uint16_t ictrl; /* Interrupt control */
1da177e4
LT		 332#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
333#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
334
3d71644c 335 uint16_t istatus; /* Interrupt status */
1da177e4
LT		 336#define ISR_RISC_INT BIT_3 /* RISC interrupt */
337
3d71644c
AV		 338 uint16_t semaphore; /* Semaphore */
339 uint16_t nvram; /* NVRAM register. */
1da177e4
LT		 340#define NVR_DESELECT 0
341#define NVR_BUSY BIT_15
342#define NVR_WRT_ENABLE BIT_14 /* Write enable */
343#define NVR_PR_ENABLE BIT_13 /* Protection register enable */
344#define NVR_DATA_IN BIT_3
345#define NVR_DATA_OUT BIT_2
346#define NVR_SELECT BIT_1
347#define NVR_CLOCK BIT_0
348
349 union {
350 struct {
3d71644c
AV		 351 uint16_t mailbox0;
352 uint16_t mailbox1;
353 uint16_t mailbox2;
354 uint16_t mailbox3;
355 uint16_t mailbox4;
356 uint16_t mailbox5;
357 uint16_t mailbox6;
358 uint16_t mailbox7;
359 uint16_t unused_2[59]; /* Gap */
1da177e4
LT		 360 } __attribute__((packed)) isp2100;
361 struct {
3d71644c
AV		 362 /* Request Queue */
363 uint16_t req_q_in; /* In-Pointer */
364 uint16_t req_q_out; /* Out-Pointer */
365 /* Response Queue */
366 uint16_t rsp_q_in; /* In-Pointer */
367 uint16_t rsp_q_out; /* Out-Pointer */
1da177e4
LT		 368
369 /* RISC to Host Status */
fa2a1ce5 370 uint32_t host_status;
1da177e4
LT		 371#define HSR_RISC_INT BIT_15 /* RISC interrupt */
372#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
373
374 /* Host to Host Semaphore */
fa2a1ce5 375 uint16_t host_semaphore;
3d71644c
AV		 376 uint16_t unused_3[17]; /* Gap */
377 uint16_t mailbox0;
378 uint16_t mailbox1;
379 uint16_t mailbox2;
380 uint16_t mailbox3;
381 uint16_t mailbox4;
382 uint16_t mailbox5;
383 uint16_t mailbox6;
384 uint16_t mailbox7;
385 uint16_t mailbox8;
386 uint16_t mailbox9;
387 uint16_t mailbox10;
388 uint16_t mailbox11;
389 uint16_t mailbox12;
390 uint16_t mailbox13;
391 uint16_t mailbox14;
392 uint16_t mailbox15;
393 uint16_t mailbox16;
394 uint16_t mailbox17;
395 uint16_t mailbox18;
396 uint16_t mailbox19;
397 uint16_t mailbox20;
398 uint16_t mailbox21;
399 uint16_t mailbox22;
400 uint16_t mailbox23;
401 uint16_t mailbox24;
402 uint16_t mailbox25;
403 uint16_t mailbox26;
404 uint16_t mailbox27;
405 uint16_t mailbox28;
406 uint16_t mailbox29;
407 uint16_t mailbox30;
408 uint16_t mailbox31;
409 uint16_t fb_cmd;
410 uint16_t unused_4[10]; /* Gap */
1da177e4
LT		 411 } __attribute__((packed)) isp2300;
412 } u;
413
3d71644c 414 uint16_t fpm_diag_config;
1da177e4 415 uint16_t unused_5[0x6]; /* Gap */
3d71644c 416 uint16_t pcr; /* Processor Control Register. */
1da177e4 417 uint16_t unused_6[0x5]; /* Gap */
3d71644c 418 uint16_t mctr; /* Memory Configuration and Timing. */
1da177e4 419 uint16_t unused_7[0x3]; /* Gap */
3d71644c 420 uint16_t fb_cmd_2100; /* Unused on 23XX */
1da177e4 421 uint16_t unused_8[0x3]; /* Gap */
3d71644c 422 uint16_t hccr; /* Host command & control register. */
1da177e4
LT		 423#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
424#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
425 /* HCCR commands */
426#define HCCR_RESET_RISC 0x1000 /* Reset RISC */
427#define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
428#define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
429#define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
430#define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
431#define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
432#define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
433#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
434
435 uint16_t unused_9[5]; /* Gap */
3d71644c
AV		 436 uint16_t gpiod; /* GPIO Data register. */
437 uint16_t gpioe; /* GPIO Enable register. */
1da177e4
LT		 438#define GPIO_LED_MASK 0x00C0
439#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
440#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
441#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
442#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
f6df144c 443#define GPIO_LED_ALL_OFF 0x0000
444#define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
445#define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
1da177e4
LT		 446
447 union {
448 struct {
3d71644c
AV		 449 uint16_t unused_10[8]; /* Gap */
450 uint16_t mailbox8;
451 uint16_t mailbox9;
452 uint16_t mailbox10;
453 uint16_t mailbox11;
454 uint16_t mailbox12;
455 uint16_t mailbox13;
456 uint16_t mailbox14;
457 uint16_t mailbox15;
458 uint16_t mailbox16;
459 uint16_t mailbox17;
460 uint16_t mailbox18;
461 uint16_t mailbox19;
462 uint16_t mailbox20;
463 uint16_t mailbox21;
464 uint16_t mailbox22;
465 uint16_t mailbox23; /* Also probe reg. */
1da177e4
LT		 466 } __attribute__((packed)) isp2200;
467 } u_end;
3d71644c
AV		 468};
469
9a168bdd 470typedef union {
3d71644c
AV		 471 struct device_reg_2xxx isp;
472 struct device_reg_24xx isp24;
1da177e4
LT		 473} device_reg_t;
474
475#define ISP_REQ_Q_IN(ha, reg) \
476 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
477 &(reg)->u.isp2100.mailbox4 : \
478 &(reg)->u.isp2300.req_q_in)
479#define ISP_REQ_Q_OUT(ha, reg) \
480 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
481 &(reg)->u.isp2100.mailbox4 : \
482 &(reg)->u.isp2300.req_q_out)
483#define ISP_RSP_Q_IN(ha, reg) \
484 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
485 &(reg)->u.isp2100.mailbox5 : \
486 &(reg)->u.isp2300.rsp_q_in)
487#define ISP_RSP_Q_OUT(ha, reg) \
488 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
489 &(reg)->u.isp2100.mailbox5 : \
490 &(reg)->u.isp2300.rsp_q_out)
491
492#define MAILBOX_REG(ha, reg, num) \
493 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
494 (num < 8 ? \
495 &(reg)->u.isp2100.mailbox0 + (num) : \
496 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
497 &(reg)->u.isp2300.mailbox0 + (num))
498#define RD_MAILBOX_REG(ha, reg, num) \
499 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
500#define WRT_MAILBOX_REG(ha, reg, num, data) \
501 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
502
503#define FB_CMD_REG(ha, reg) \
504 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
505 &(reg)->fb_cmd_2100 : \
506 &(reg)->u.isp2300.fb_cmd)
507#define RD_FB_CMD_REG(ha, reg) \
508 RD_REG_WORD(FB_CMD_REG(ha, reg))
509#define WRT_FB_CMD_REG(ha, reg, data) \
510 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
511
512typedef struct {
513 uint32_t out_mb; /* outbound from driver */
514 uint32_t in_mb; /* Incoming from RISC */
515 uint16_t mb[MAILBOX_REGISTER_COUNT];
516 long buf_size;
517 void *bufp;
518 uint32_t tov;
519 uint8_t flags;
520#define MBX_DMA_IN BIT_0
521#define MBX_DMA_OUT BIT_1
522#define IOCTL_CMD BIT_2
523} mbx_cmd_t;
524
525#define MBX_TOV_SECONDS 30
526
527/*
528 * ISP product identification definitions in mailboxes after reset.
529 */
530#define PROD_ID_1 0x4953
531#define PROD_ID_2 0x0000
532#define PROD_ID_2a 0x5020
533#define PROD_ID_3 0x2020
534
535/*
536 * ISP mailbox Self-Test status codes
537 */
538#define MBS_FRM_ALIVE 0 /* Firmware Alive. */
539#define MBS_CHKSUM_ERR 1 /* Checksum Error. */
540#define MBS_BUSY 4 /* Busy. */
541
542/*
543 * ISP mailbox command complete status codes
544 */
545#define MBS_COMMAND_COMPLETE 0x4000
546#define MBS_INVALID_COMMAND 0x4001
547#define MBS_HOST_INTERFACE_ERROR 0x4002
548#define MBS_TEST_FAILED 0x4003
549#define MBS_COMMAND_ERROR 0x4005
550#define MBS_COMMAND_PARAMETER_ERROR 0x4006
551#define MBS_PORT_ID_USED 0x4007
552#define MBS_LOOP_ID_USED 0x4008
553#define MBS_ALL_IDS_IN_USE 0x4009
554#define MBS_NOT_LOGGED_IN 0x400A
3d71644c
AV		 555#define MBS_LINK_DOWN_ERROR 0x400B
556#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
1da177e4
LT		 557
558/*
559 * ISP mailbox asynchronous event status codes
560 */
561#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
562#define MBA_RESET 0x8001 /* Reset Detected. */
563#define MBA_SYSTEM_ERR 0x8002 /* System Error. */
564#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
565#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
566#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
567#define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
568 /* occurred. */
569#define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
570#define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
571#define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
572#define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
573#define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
574#define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
575#define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
576#define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
577#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
578#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
579#define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
580#define MBA_IP_RECEIVE 0x8023 /* IP Received. */
581#define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
582#define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
583#define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
584#define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
585 /* used. */
586#define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
587#define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
588#define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
589#define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
590#define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
591#define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
592#define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
593#define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
594#define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
595#define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
596#define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
597#define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
598#define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
599
600/*
601 * Firmware options 1, 2, 3.
602 */
603#define FO1_AE_ON_LIPF8 BIT_0
604#define FO1_AE_ALL_LIP_RESET BIT_1
605#define FO1_CTIO_RETRY BIT_3
606#define FO1_DISABLE_LIP_F7_SW BIT_4
607#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
3d71644c 608#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
1da177e4
LT		 609#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
610#define FO1_SET_EMPHASIS_SWING BIT_8
611#define FO1_AE_AUTO_BYPASS BIT_9
612#define FO1_ENABLE_PURE_IOCB BIT_10
613#define FO1_AE_PLOGI_RJT BIT_11
614#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
615#define FO1_AE_QUEUE_FULL BIT_13
616
617#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
618#define FO2_REV_LOOPBACK BIT_1
619
620#define FO3_ENABLE_EMERG_IOCB BIT_0
621#define FO3_AE_RND_ERROR BIT_1
622
3d71644c
AV		 623/* 24XX additional firmware options */
624#define ADD_FO_COUNT 3
625#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
626#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
627
628#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
629
630#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
631
1da177e4
LT		 632/*
633 * ISP mailbox commands
634 */
635#define MBC_LOAD_RAM 1 /* Load RAM. */
636#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
637#define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
638#define MBC_READ_RAM_WORD 5 /* Read RAM word. */
639#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
640#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
641#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
642#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
643#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
644#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
645#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
646#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
647#define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
648#define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
f6ef3b18 649#define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
1da177e4
LT		 650#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
651#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
652#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
653#define MBC_RESET 0x18 /* Reset. */
654#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
655#define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
656#define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
657#define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
658#define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
659#define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
660#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
661#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
662#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
663#define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
664#define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
665#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
666#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
667#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
668#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
669#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
670#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
671#define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
672#define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
673#define MBC_DATA_RATE 0x5d /* Get RNID parameters */
674#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
675#define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
676 /* Initialization Procedure */
677#define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
678#define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
679#define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
680#define MBC_TARGET_RESET 0x66 /* Target Reset. */
681#define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
682#define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
683#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
684#define MBC_GET_PORT_NAME 0x6a /* Get port name. */
685#define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
686#define MBC_LIP_RESET 0x6c /* LIP reset. */
687#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
688 /* commandd. */
689#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
690#define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
691#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
692#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
693#define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
694#define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
695#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
696#define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
697#define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
698#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
699#define MBC_LUN_RESET 0x7E /* Send LUN reset */
700
3d71644c
AV		 701/*
702 * ISP24xx mailbox commands
703 */
704#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
705#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
706#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
707#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
708#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
709#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
710#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
711#define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
712#define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
713#define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
714#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
715#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
716
1da177e4
LT		 717/* Firmware return data sizes */
718#define FCAL_MAP_SIZE 128
719
720/* Mailbox bit definitions for out_mb and in_mb */
721#define MBX_31 BIT_31
722#define MBX_30 BIT_30
723#define MBX_29 BIT_29
724#define MBX_28 BIT_28
725#define MBX_27 BIT_27
726#define MBX_26 BIT_26
727#define MBX_25 BIT_25
728#define MBX_24 BIT_24
729#define MBX_23 BIT_23
730#define MBX_22 BIT_22
731#define MBX_21 BIT_21
732#define MBX_20 BIT_20
733#define MBX_19 BIT_19
734#define MBX_18 BIT_18
735#define MBX_17 BIT_17
736#define MBX_16 BIT_16
737#define MBX_15 BIT_15
738#define MBX_14 BIT_14
739#define MBX_13 BIT_13
740#define MBX_12 BIT_12
741#define MBX_11 BIT_11
742#define MBX_10 BIT_10
743#define MBX_9 BIT_9
744#define MBX_8 BIT_8
745#define MBX_7 BIT_7
746#define MBX_6 BIT_6
747#define MBX_5 BIT_5
748#define MBX_4 BIT_4
749#define MBX_3 BIT_3
750#define MBX_2 BIT_2
751#define MBX_1 BIT_1
752#define MBX_0 BIT_0
753
754/*
755 * Firmware state codes from get firmware state mailbox command
756 */
757#define FSTATE_CONFIG_WAIT 0
758#define FSTATE_WAIT_AL_PA 1
759#define FSTATE_WAIT_LOGIN 2
760#define FSTATE_READY 3
761#define FSTATE_LOSS_OF_SYNC 4
762#define FSTATE_ERROR 5
763#define FSTATE_REINIT 6
764#define FSTATE_NON_PART 7
765
766#define FSTATE_CONFIG_CORRECT 0
767#define FSTATE_P2P_RCV_LIP 1
768#define FSTATE_P2P_CHOOSE_LOOP 2
769#define FSTATE_P2P_RCV_UNIDEN_LIP 3
770#define FSTATE_FATAL_ERROR 4
771#define FSTATE_LOOP_BACK_CONN 5
772
773/*
774 * Port Database structure definition
775 * Little endian except where noted.
776 */
777#define PORT_DATABASE_SIZE 128 /* bytes */
778typedef struct {
779 uint8_t options;
780 uint8_t control;
781 uint8_t master_state;
782 uint8_t slave_state;
783 uint8_t reserved[2];
784 uint8_t hard_address;
785 uint8_t reserved_1;
786 uint8_t port_id[4];
787 uint8_t node_name[WWN_SIZE];
788 uint8_t port_name[WWN_SIZE];
789 uint16_t execution_throttle;
790 uint16_t execution_count;
791 uint8_t reset_count;
792 uint8_t reserved_2;
793 uint16_t resource_allocation;
794 uint16_t current_allocation;
795 uint16_t queue_head;
796 uint16_t queue_tail;
797 uint16_t transmit_execution_list_next;
798 uint16_t transmit_execution_list_previous;
799 uint16_t common_features;
800 uint16_t total_concurrent_sequences;
801 uint16_t RO_by_information_category;
802 uint8_t recipient;
803 uint8_t initiator;
804 uint16_t receive_data_size;
805 uint16_t concurrent_sequences;
806 uint16_t open_sequences_per_exchange;
807 uint16_t lun_abort_flags;
808 uint16_t lun_stop_flags;
809 uint16_t stop_queue_head;
810 uint16_t stop_queue_tail;
811 uint16_t port_retry_timer;
812 uint16_t next_sequence_id;
813 uint16_t frame_count;
814 uint16_t PRLI_payload_length;
815 uint8_t prli_svc_param_word_0[2]; /* Big endian */
816 /* Bits 15-0 of word 0 */
817 uint8_t prli_svc_param_word_3[2]; /* Big endian */
818 /* Bits 15-0 of word 3 */
819 uint16_t loop_id;
820 uint16_t extended_lun_info_list_pointer;
821 uint16_t extended_lun_stop_list_pointer;
822} port_database_t;
823
824/*
825 * Port database slave/master states
826 */
827#define PD_STATE_DISCOVERY 0
828#define PD_STATE_WAIT_DISCOVERY_ACK 1
829#define PD_STATE_PORT_LOGIN 2
830#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
831#define PD_STATE_PROCESS_LOGIN 4
832#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
833#define PD_STATE_PORT_LOGGED_IN 6
834#define PD_STATE_PORT_UNAVAILABLE 7
835#define PD_STATE_PROCESS_LOGOUT 8
836#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
837#define PD_STATE_PORT_LOGOUT 10
838#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
839
840
4fdfefe5
AV		 841#define QLA_ZIO_MODE_5 (BIT_2 | BIT_0)
842#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
843#define QLA_ZIO_DISABLED 0
844#define QLA_ZIO_DEFAULT_TIMER 2
845
1da177e4
LT		 846/*
847 * ISP Initialization Control Block.
848 * Little endian except where noted.
849 */
850#define ICB_VERSION 1
851typedef struct {
852 uint8_t version;
853 uint8_t reserved_1;
854
855 /*
856 * LSB BIT 0 = Enable Hard Loop Id
857 * LSB BIT 1 = Enable Fairness
858 * LSB BIT 2 = Enable Full-Duplex
859 * LSB BIT 3 = Enable Fast Posting
860 * LSB BIT 4 = Enable Target Mode
861 * LSB BIT 5 = Disable Initiator Mode
862 * LSB BIT 6 = Enable ADISC
863 * LSB BIT 7 = Enable Target Inquiry Data
864 *
865 * MSB BIT 0 = Enable PDBC Notify
866 * MSB BIT 1 = Non Participating LIP
867 * MSB BIT 2 = Descending Loop ID Search
868 * MSB BIT 3 = Acquire Loop ID in LIPA
869 * MSB BIT 4 = Stop PortQ on Full Status
870 * MSB BIT 5 = Full Login after LIP
871 * MSB BIT 6 = Node Name Option
872 * MSB BIT 7 = Ext IFWCB enable bit
873 */
874 uint8_t firmware_options[2];
875
876 uint16_t frame_payload_size;
877 uint16_t max_iocb_allocation;
878 uint16_t execution_throttle;
879 uint8_t retry_count;
880 uint8_t retry_delay; /* unused */
881 uint8_t port_name[WWN_SIZE]; /* Big endian. */
882 uint16_t hard_address;
883 uint8_t inquiry_data;
884 uint8_t login_timeout;
885 uint8_t node_name[WWN_SIZE]; /* Big endian. */
886
887 uint16_t request_q_outpointer;
888 uint16_t response_q_inpointer;
889 uint16_t request_q_length;
890 uint16_t response_q_length;
891 uint32_t request_q_address[2];
892 uint32_t response_q_address[2];
893
894 uint16_t lun_enables;
895 uint8_t command_resource_count;
896 uint8_t immediate_notify_resource_count;
897 uint16_t timeout;
898 uint8_t reserved_2[2];
899
900 /*
901 * LSB BIT 0 = Timer Operation mode bit 0
902 * LSB BIT 1 = Timer Operation mode bit 1
903 * LSB BIT 2 = Timer Operation mode bit 2
904 * LSB BIT 3 = Timer Operation mode bit 3
905 * LSB BIT 4 = Init Config Mode bit 0
906 * LSB BIT 5 = Init Config Mode bit 1
907 * LSB BIT 6 = Init Config Mode bit 2
908 * LSB BIT 7 = Enable Non part on LIHA failure
909 *
910 * MSB BIT 0 = Enable class 2
911 * MSB BIT 1 = Enable ACK0
912 * MSB BIT 2 =
913 * MSB BIT 3 =
914 * MSB BIT 4 = FC Tape Enable
915 * MSB BIT 5 = Enable FC Confirm
916 * MSB BIT 6 = Enable command queuing in target mode
917 * MSB BIT 7 = No Logo On Link Down
918 */
919 uint8_t add_firmware_options[2];
920
921 uint8_t response_accumulation_timer;
922 uint8_t interrupt_delay_timer;
923
924 /*
925 * LSB BIT 0 = Enable Read xfr_rdy
926 * LSB BIT 1 = Soft ID only
927 * LSB BIT 2 =
928 * LSB BIT 3 =
929 * LSB BIT 4 = FCP RSP Payload [0]
930 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
931 * LSB BIT 6 = Enable Out-of-Order frame handling
932 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
933 *
934 * MSB BIT 0 = Sbus enable - 2300
935 * MSB BIT 1 =
936 * MSB BIT 2 =
937 * MSB BIT 3 =
06c22bd1 938 * MSB BIT 4 = LED mode
1da177e4
LT		 939 * MSB BIT 5 = enable 50 ohm termination
940 * MSB BIT 6 = Data Rate (2300 only)
941 * MSB BIT 7 = Data Rate (2300 only)
942 */
943 uint8_t special_options[2];
944
945 uint8_t reserved_3[26];
946} init_cb_t;
947
948/*
949 * Get Link Status mailbox command return buffer.
950 */
3d71644c
AV		 951#define GLSO_SEND_RPS BIT_0
952#define GLSO_USE_DID BIT_3
953
1da177e4
LT		 954typedef struct {
955 uint32_t link_fail_cnt;
956 uint32_t loss_sync_cnt;
957 uint32_t loss_sig_cnt;
958 uint32_t prim_seq_err_cnt;
959 uint32_t inval_xmit_word_cnt;
960 uint32_t inval_crc_cnt;
961} link_stat_t;
962
963/*
964 * NVRAM Command values.
965 */
966#define NV_START_BIT BIT_2
967#define NV_WRITE_OP (BIT_26+BIT_24)
968#define NV_READ_OP (BIT_26+BIT_25)
969#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
970#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
971#define NV_DELAY_COUNT 10
972
973/*
974 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
975 */
976typedef struct {
977 /*
978 * NVRAM header
979 */
980 uint8_t id[4];
981 uint8_t nvram_version;
982 uint8_t reserved_0;
983
984 /*
985 * NVRAM RISC parameter block
986 */
987 uint8_t parameter_block_version;
988 uint8_t reserved_1;
989
990 /*
991 * LSB BIT 0 = Enable Hard Loop Id
992 * LSB BIT 1 = Enable Fairness
993 * LSB BIT 2 = Enable Full-Duplex
994 * LSB BIT 3 = Enable Fast Posting
995 * LSB BIT 4 = Enable Target Mode
996 * LSB BIT 5 = Disable Initiator Mode
997 * LSB BIT 6 = Enable ADISC
998 * LSB BIT 7 = Enable Target Inquiry Data
999 *
1000 * MSB BIT 0 = Enable PDBC Notify
1001 * MSB BIT 1 = Non Participating LIP
1002 * MSB BIT 2 = Descending Loop ID Search
1003 * MSB BIT 3 = Acquire Loop ID in LIPA
1004 * MSB BIT 4 = Stop PortQ on Full Status
1005 * MSB BIT 5 = Full Login after LIP
1006 * MSB BIT 6 = Node Name Option
1007 * MSB BIT 7 = Ext IFWCB enable bit
1008 */
1009 uint8_t firmware_options[2];
1010
1011 uint16_t frame_payload_size;
1012 uint16_t max_iocb_allocation;
1013 uint16_t execution_throttle;
1014 uint8_t retry_count;
1015 uint8_t retry_delay; /* unused */
1016 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1017 uint16_t hard_address;
1018 uint8_t inquiry_data;
1019 uint8_t login_timeout;
1020 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1021
1022 /*
1023 * LSB BIT 0 = Timer Operation mode bit 0
1024 * LSB BIT 1 = Timer Operation mode bit 1
1025 * LSB BIT 2 = Timer Operation mode bit 2
1026 * LSB BIT 3 = Timer Operation mode bit 3
1027 * LSB BIT 4 = Init Config Mode bit 0
1028 * LSB BIT 5 = Init Config Mode bit 1
1029 * LSB BIT 6 = Init Config Mode bit 2
1030 * LSB BIT 7 = Enable Non part on LIHA failure
1031 *
1032 * MSB BIT 0 = Enable class 2
1033 * MSB BIT 1 = Enable ACK0
1034 * MSB BIT 2 =
1035 * MSB BIT 3 =
1036 * MSB BIT 4 = FC Tape Enable
1037 * MSB BIT 5 = Enable FC Confirm
1038 * MSB BIT 6 = Enable command queuing in target mode
1039 * MSB BIT 7 = No Logo On Link Down
1040 */
1041 uint8_t add_firmware_options[2];
1042
1043 uint8_t response_accumulation_timer;
1044 uint8_t interrupt_delay_timer;
1045
1046 /*
1047 * LSB BIT 0 = Enable Read xfr_rdy
1048 * LSB BIT 1 = Soft ID only
1049 * LSB BIT 2 =
1050 * LSB BIT 3 =
1051 * LSB BIT 4 = FCP RSP Payload [0]
1052 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1053 * LSB BIT 6 = Enable Out-of-Order frame handling
1054 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1055 *
1056 * MSB BIT 0 = Sbus enable - 2300
1057 * MSB BIT 1 =
1058 * MSB BIT 2 =
1059 * MSB BIT 3 =
06c22bd1 1060 * MSB BIT 4 = LED mode
1da177e4
LT		 1061 * MSB BIT 5 = enable 50 ohm termination
1062 * MSB BIT 6 = Data Rate (2300 only)
1063 * MSB BIT 7 = Data Rate (2300 only)
1064 */
1065 uint8_t special_options[2];
1066
1067 /* Reserved for expanded RISC parameter block */
1068 uint8_t reserved_2[22];
1069
1070 /*
1071 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1072 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1073 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1074 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1075 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1076 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1077 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1078 * LSB BIT 7 = Rx Sensitivity 1G bit 3
fa2a1ce5 1079 *
1da177e4
LT		 1080 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1081 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1082 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1083 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1084 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1085 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1086 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1087 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1088 *
1089 * LSB BIT 0 = Output Swing 1G bit 0
1090 * LSB BIT 1 = Output Swing 1G bit 1
1091 * LSB BIT 2 = Output Swing 1G bit 2
1092 * LSB BIT 3 = Output Emphasis 1G bit 0
1093 * LSB BIT 4 = Output Emphasis 1G bit 1
1094 * LSB BIT 5 = Output Swing 2G bit 0
1095 * LSB BIT 6 = Output Swing 2G bit 1
1096 * LSB BIT 7 = Output Swing 2G bit 2
fa2a1ce5 1097 *
1da177e4
LT		 1098 * MSB BIT 0 = Output Emphasis 2G bit 0
1099 * MSB BIT 1 = Output Emphasis 2G bit 1
1100 * MSB BIT 2 = Output Enable
1101 * MSB BIT 3 =
1102 * MSB BIT 4 =
1103 * MSB BIT 5 =
1104 * MSB BIT 6 =
1105 * MSB BIT 7 =
1106 */
1107 uint8_t seriallink_options[4];
1108
1109 /*
1110 * NVRAM host parameter block
1111 *
1112 * LSB BIT 0 = Enable spinup delay
1113 * LSB BIT 1 = Disable BIOS
1114 * LSB BIT 2 = Enable Memory Map BIOS
1115 * LSB BIT 3 = Enable Selectable Boot
1116 * LSB BIT 4 = Disable RISC code load
1117 * LSB BIT 5 = Set cache line size 1
1118 * LSB BIT 6 = PCI Parity Disable
1119 * LSB BIT 7 = Enable extended logging
1120 *
1121 * MSB BIT 0 = Enable 64bit addressing
1122 * MSB BIT 1 = Enable lip reset
1123 * MSB BIT 2 = Enable lip full login
1124 * MSB BIT 3 = Enable target reset
1125 * MSB BIT 4 = Enable database storage
1126 * MSB BIT 5 = Enable cache flush read
1127 * MSB BIT 6 = Enable database load
1128 * MSB BIT 7 = Enable alternate WWN
1129 */
1130 uint8_t host_p[2];
1131
1132 uint8_t boot_node_name[WWN_SIZE];
1133 uint8_t boot_lun_number;
1134 uint8_t reset_delay;
1135 uint8_t port_down_retry_count;
1136 uint8_t boot_id_number;
1137 uint16_t max_luns_per_target;
1138 uint8_t fcode_boot_port_name[WWN_SIZE];
1139 uint8_t alternate_port_name[WWN_SIZE];
1140 uint8_t alternate_node_name[WWN_SIZE];
1141
1142 /*
1143 * BIT 0 = Selective Login
1144 * BIT 1 = Alt-Boot Enable
1145 * BIT 2 =
1146 * BIT 3 = Boot Order List
1147 * BIT 4 =
1148 * BIT 5 = Selective LUN
1149 * BIT 6 =
1150 * BIT 7 = unused
1151 */
1152 uint8_t efi_parameters;
1153
1154 uint8_t link_down_timeout;
1155
cca5335c 1156 uint8_t adapter_id[16];
1da177e4
LT		 1157
1158 uint8_t alt1_boot_node_name[WWN_SIZE];
1159 uint16_t alt1_boot_lun_number;
1160 uint8_t alt2_boot_node_name[WWN_SIZE];
1161 uint16_t alt2_boot_lun_number;
1162 uint8_t alt3_boot_node_name[WWN_SIZE];
1163 uint16_t alt3_boot_lun_number;
1164 uint8_t alt4_boot_node_name[WWN_SIZE];
1165 uint16_t alt4_boot_lun_number;
1166 uint8_t alt5_boot_node_name[WWN_SIZE];
1167 uint16_t alt5_boot_lun_number;
1168 uint8_t alt6_boot_node_name[WWN_SIZE];
1169 uint16_t alt6_boot_lun_number;
1170 uint8_t alt7_boot_node_name[WWN_SIZE];
1171 uint16_t alt7_boot_lun_number;
1172
1173 uint8_t reserved_3[2];
1174
1175 /* Offset 200-215 : Model Number */
1176 uint8_t model_number[16];
1177
1178 /* OEM related items */
1179 uint8_t oem_specific[16];
1180
1181 /*
1182 * NVRAM Adapter Features offset 232-239
1183 *
1184 * LSB BIT 0 = External GBIC
1185 * LSB BIT 1 = Risc RAM parity
1186 * LSB BIT 2 = Buffer Plus Module
1187 * LSB BIT 3 = Multi Chip Adapter
1188 * LSB BIT 4 = Internal connector
1189 * LSB BIT 5 =
1190 * LSB BIT 6 =
1191 * LSB BIT 7 =
1192 *
1193 * MSB BIT 0 =
1194 * MSB BIT 1 =
1195 * MSB BIT 2 =
1196 * MSB BIT 3 =
1197 * MSB BIT 4 =
1198 * MSB BIT 5 =
1199 * MSB BIT 6 =
1200 * MSB BIT 7 =
1201 */
1202 uint8_t adapter_features[2];
1203
1204 uint8_t reserved_4[16];
1205
1206 /* Subsystem vendor ID for ISP2200 */
1207 uint16_t subsystem_vendor_id_2200;
1208
1209 /* Subsystem device ID for ISP2200 */
1210 uint16_t subsystem_device_id_2200;
1211
1212 uint8_t reserved_5;
1213 uint8_t checksum;
1214} nvram_t;
1215
1216/*
1217 * ISP queue - response queue entry definition.
1218 */
1219typedef struct {
1220 uint8_t data[60];
1221 uint32_t signature;
1222#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1223} response_t;
1224
1225typedef union {
1226 uint16_t extended;
1227 struct {
1228 uint8_t reserved;
1229 uint8_t standard;
1230 } id;
1231} target_id_t;
1232
1233#define SET_TARGET_ID(ha, to, from) \
1234do { \
1235 if (HAS_EXTENDED_IDS(ha)) \
1236 to.extended = cpu_to_le16(from); \
1237 else \
1238 to.id.standard = (uint8_t)from; \
1239} while (0)
1240
1241/*
1242 * ISP queue - command entry structure definition.
1243 */
1244#define COMMAND_TYPE 0x11 /* Command entry */
1da177e4
LT		 1245typedef struct {
1246 uint8_t entry_type; /* Entry type. */
1247 uint8_t entry_count; /* Entry count. */
1248 uint8_t sys_define; /* System defined. */
1249 uint8_t entry_status; /* Entry Status. */
1250 uint32_t handle; /* System handle. */
1251 target_id_t target; /* SCSI ID */
1252 uint16_t lun; /* SCSI LUN */
1253 uint16_t control_flags; /* Control flags. */
1254#define CF_WRITE BIT_6
1255#define CF_READ BIT_5
1256#define CF_SIMPLE_TAG BIT_3
1257#define CF_ORDERED_TAG BIT_2
1258#define CF_HEAD_TAG BIT_1
1259 uint16_t reserved_1;
1260 uint16_t timeout; /* Command timeout. */
1261 uint16_t dseg_count; /* Data segment count. */
1262 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1263 uint32_t byte_count; /* Total byte count. */
1264 uint32_t dseg_0_address; /* Data segment 0 address. */
1265 uint32_t dseg_0_length; /* Data segment 0 length. */
1266 uint32_t dseg_1_address; /* Data segment 1 address. */
1267 uint32_t dseg_1_length; /* Data segment 1 length. */
1268 uint32_t dseg_2_address; /* Data segment 2 address. */
1269 uint32_t dseg_2_length; /* Data segment 2 length. */
1270} cmd_entry_t;
1271
1272/*
1273 * ISP queue - 64-Bit addressing, command entry structure definition.
1274 */
1275#define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1276typedef struct {
1277 uint8_t entry_type; /* Entry type. */
1278 uint8_t entry_count; /* Entry count. */
1279 uint8_t sys_define; /* System defined. */
1280 uint8_t entry_status; /* Entry Status. */
1281 uint32_t handle; /* System handle. */
1282 target_id_t target; /* SCSI ID */
1283 uint16_t lun; /* SCSI LUN */
1284 uint16_t control_flags; /* Control flags. */
1285 uint16_t reserved_1;
1286 uint16_t timeout; /* Command timeout. */
1287 uint16_t dseg_count; /* Data segment count. */
1288 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1289 uint32_t byte_count; /* Total byte count. */
1290 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1291 uint32_t dseg_0_length; /* Data segment 0 length. */
1292 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1293 uint32_t dseg_1_length; /* Data segment 1 length. */
1294} cmd_a64_entry_t, request_t;
1295
1296/*
1297 * ISP queue - continuation entry structure definition.
1298 */
1299#define CONTINUE_TYPE 0x02 /* Continuation entry. */
1300typedef struct {
1301 uint8_t entry_type; /* Entry type. */
1302 uint8_t entry_count; /* Entry count. */
1303 uint8_t sys_define; /* System defined. */
1304 uint8_t entry_status; /* Entry Status. */
1305 uint32_t reserved;
1306 uint32_t dseg_0_address; /* Data segment 0 address. */
1307 uint32_t dseg_0_length; /* Data segment 0 length. */
1308 uint32_t dseg_1_address; /* Data segment 1 address. */
1309 uint32_t dseg_1_length; /* Data segment 1 length. */
1310 uint32_t dseg_2_address; /* Data segment 2 address. */
1311 uint32_t dseg_2_length; /* Data segment 2 length. */
1312 uint32_t dseg_3_address; /* Data segment 3 address. */
1313 uint32_t dseg_3_length; /* Data segment 3 length. */
1314 uint32_t dseg_4_address; /* Data segment 4 address. */
1315 uint32_t dseg_4_length; /* Data segment 4 length. */
1316 uint32_t dseg_5_address; /* Data segment 5 address. */
1317 uint32_t dseg_5_length; /* Data segment 5 length. */
1318 uint32_t dseg_6_address; /* Data segment 6 address. */
1319 uint32_t dseg_6_length; /* Data segment 6 length. */
1320} cont_entry_t;
1321
1322/*
1323 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1324 */
1325#define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1326typedef struct {
1327 uint8_t entry_type; /* Entry type. */
1328 uint8_t entry_count; /* Entry count. */
1329 uint8_t sys_define; /* System defined. */
1330 uint8_t entry_status; /* Entry Status. */
1331 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1332 uint32_t dseg_0_length; /* Data segment 0 length. */
1333 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1334 uint32_t dseg_1_length; /* Data segment 1 length. */
1335 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1336 uint32_t dseg_2_length; /* Data segment 2 length. */
1337 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1338 uint32_t dseg_3_length; /* Data segment 3 length. */
1339 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1340 uint32_t dseg_4_length; /* Data segment 4 length. */
1341} cont_a64_entry_t;
1342
1343/*
1344 * ISP queue - status entry structure definition.
1345 */
1346#define STATUS_TYPE 0x03 /* Status entry. */
1347typedef struct {
1348 uint8_t entry_type; /* Entry type. */
1349 uint8_t entry_count; /* Entry count. */
1350 uint8_t sys_define; /* System defined. */
1351 uint8_t entry_status; /* Entry Status. */
1352 uint32_t handle; /* System handle. */
1353 uint16_t scsi_status; /* SCSI status. */
1354 uint16_t comp_status; /* Completion status. */
1355 uint16_t state_flags; /* State flags. */
1356 uint16_t status_flags; /* Status flags. */
1357 uint16_t rsp_info_len; /* Response Info Length. */
1358 uint16_t req_sense_length; /* Request sense data length. */
1359 uint32_t residual_length; /* Residual transfer length. */
1360 uint8_t rsp_info[8]; /* FCP response information. */
1361 uint8_t req_sense_data[32]; /* Request sense data. */
1362} sts_entry_t;
1363
1364/*
1365 * Status entry entry status
1366 */
3d71644c 1367#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1da177e4
LT		 1368#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1369#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1370#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1371#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1372#define RF_BUSY BIT_1 /* Busy */
3d71644c
AV		 1373#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1374 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1375#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1376 RF_INV_E_TYPE)
1da177e4
LT		 1377
1378/*
1379 * Status entry SCSI status bit definitions.
1380 */
1381#define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1382#define SS_RESIDUAL_UNDER BIT_11
1383#define SS_RESIDUAL_OVER BIT_10
1384#define SS_SENSE_LEN_VALID BIT_9
1385#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1386
1387#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1388#define SS_BUSY_CONDITION BIT_3
1389#define SS_CONDITION_MET BIT_2
1390#define SS_CHECK_CONDITION BIT_1
1391
1392/*
1393 * Status entry completion status
1394 */
1395#define CS_COMPLETE 0x0 /* No errors */
1396#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1397#define CS_DMA 0x2 /* A DMA direction error. */
1398#define CS_TRANSPORT 0x3 /* Transport error. */
1399#define CS_RESET 0x4 /* SCSI bus reset occurred */
1400#define CS_ABORTED 0x5 /* System aborted command. */
1401#define CS_TIMEOUT 0x6 /* Timeout error. */
1402#define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1403
1404#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1405#define CS_QUEUE_FULL 0x1C /* Queue Full. */
1406#define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1407 /* (selection timeout) */
1408#define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1409#define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1410#define CS_PORT_BUSY 0x2B /* Port Busy */
1411#define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1412#define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1413#define CS_UNKNOWN 0x81 /* Driver defined */
1414#define CS_RETRY 0x82 /* Driver defined */
1415#define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1416
1417/*
1418 * Status entry status flags
1419 */
1420#define SF_ABTS_TERMINATED BIT_10
1421#define SF_LOGOUT_SENT BIT_13
1422
1423/*
1424 * ISP queue - status continuation entry structure definition.
1425 */
1426#define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1427typedef struct {
1428 uint8_t entry_type; /* Entry type. */
1429 uint8_t entry_count; /* Entry count. */
1430 uint8_t sys_define; /* System defined. */
1431 uint8_t entry_status; /* Entry Status. */
1432 uint8_t data[60]; /* data */
1433} sts_cont_entry_t;
1434
1435/*
1436 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1437 * structure definition.
1438 */
1439#define STATUS_TYPE_21 0x21 /* Status entry. */
1440typedef struct {
1441 uint8_t entry_type; /* Entry type. */
1442 uint8_t entry_count; /* Entry count. */
1443 uint8_t handle_count; /* Handle count. */
1444 uint8_t entry_status; /* Entry Status. */
1445 uint32_t handle[15]; /* System handles. */
1446} sts21_entry_t;
1447
1448/*
1449 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1450 * structure definition.
1451 */
1452#define STATUS_TYPE_22 0x22 /* Status entry. */
1453typedef struct {
1454 uint8_t entry_type; /* Entry type. */
1455 uint8_t entry_count; /* Entry count. */
1456 uint8_t handle_count; /* Handle count. */
1457 uint8_t entry_status; /* Entry Status. */
1458 uint16_t handle[30]; /* System handles. */
1459} sts22_entry_t;
1460
1461/*
1462 * ISP queue - marker entry structure definition.
1463 */
1464#define MARKER_TYPE 0x04 /* Marker entry. */
1465typedef struct {
1466 uint8_t entry_type; /* Entry type. */
1467 uint8_t entry_count; /* Entry count. */
1468 uint8_t handle_count; /* Handle count. */
1469 uint8_t entry_status; /* Entry Status. */
1470 uint32_t sys_define_2; /* System defined. */
1471 target_id_t target; /* SCSI ID */
1472 uint8_t modifier; /* Modifier (7-0). */
1473#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1474#define MK_SYNC_ID 1 /* Synchronize ID */
1475#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1476#define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1477 /* clear port changed, */
1478 /* use sequence number. */
1479 uint8_t reserved_1;
1480 uint16_t sequence_number; /* Sequence number of event */
1481 uint16_t lun; /* SCSI LUN */
1482 uint8_t reserved_2[48];
1483} mrk_entry_t;
1484
1485/*
1486 * ISP queue - Management Server entry structure definition.
1487 */
1488#define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1489typedef struct {
1490 uint8_t entry_type; /* Entry type. */
1491 uint8_t entry_count; /* Entry count. */
1492 uint8_t handle_count; /* Handle count. */
1493 uint8_t entry_status; /* Entry Status. */
1494 uint32_t handle1; /* System handle. */
1495 target_id_t loop_id;
1496 uint16_t status;
1497 uint16_t control_flags; /* Control flags. */
1498 uint16_t reserved2;
1499 uint16_t timeout;
1500 uint16_t cmd_dsd_count;
1501 uint16_t total_dsd_count;
1502 uint8_t type;
1503 uint8_t r_ctl;
1504 uint16_t rx_id;
1505 uint16_t reserved3;
1506 uint32_t handle2;
1507 uint32_t rsp_bytecount;
1508 uint32_t req_bytecount;
1509 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1510 uint32_t dseg_req_length; /* Data segment 0 length. */
1511 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1512 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1513} ms_iocb_entry_t;
1514
1515
1516/*
1517 * ISP queue - Mailbox Command entry structure definition.
1518 */
1519#define MBX_IOCB_TYPE 0x39
1520struct mbx_entry {
1521 uint8_t entry_type;
1522 uint8_t entry_count;
1523 uint8_t sys_define1;
1524 /* Use sys_define1 for source type */
1525#define SOURCE_SCSI 0x00
1526#define SOURCE_IP 0x01
1527#define SOURCE_VI 0x02
1528#define SOURCE_SCTP 0x03
1529#define SOURCE_MP 0x04
1530#define SOURCE_MPIOCTL 0x05
1531#define SOURCE_ASYNC_IOCB 0x07
1532
1533 uint8_t entry_status;
1534
1535 uint32_t handle;
1536 target_id_t loop_id;
1537
1538 uint16_t status;
1539 uint16_t state_flags;
1540 uint16_t status_flags;
1541
1542 uint32_t sys_define2[2];
1543
1544 uint16_t mb0;
1545 uint16_t mb1;
1546 uint16_t mb2;
1547 uint16_t mb3;
1548 uint16_t mb6;
1549 uint16_t mb7;
1550 uint16_t mb9;
1551 uint16_t mb10;
1552 uint32_t reserved_2[2];
1553 uint8_t node_name[WWN_SIZE];
1554 uint8_t port_name[WWN_SIZE];
1555};
1556
1557/*
1558 * ISP request and response queue entry sizes
1559 */
1560#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1561#define REQUEST_ENTRY_SIZE (sizeof(request_t))
1562
1563
1564/*
1565 * 24 bit port ID type definition.
1566 */
1567typedef union {
1568 uint32_t b24 : 24;
1569
1570 struct {
1571 uint8_t d_id[3];
1572 uint8_t rsvd_1;
1573 } r;
1574
1575 struct {
1576 uint8_t al_pa;
1577 uint8_t area;
1578 uint8_t domain;
1579 uint8_t rsvd_1;
1580 } b;
1581} port_id_t;
1582#define INVALID_PORT_ID 0xFFFFFF
1583
1584/*
1585 * Switch info gathering structure.
1586 */
1587typedef struct {
1588 port_id_t d_id;
1589 uint8_t node_name[WWN_SIZE];
1590 uint8_t port_name[WWN_SIZE];
1da177e4
LT		 1591} sw_info_t;
1592
1593/*
1594 * Inquiry command structure.
1595 */
1596#define INQ_DATA_SIZE 36
1597
1598/*
1599 * Inquiry mailbox IOCB packet definition.
1600 */
1601typedef struct {
1602 union {
1603 cmd_a64_entry_t cmd;
1604 sts_entry_t rsp;
3d71644c
AV		 1605 struct cmd_type_7 cmd24;
1606 struct sts_entry_24xx rsp24;
1da177e4
LT		 1607 } p;
1608 uint8_t inq[INQ_DATA_SIZE];
1609} inq_cmd_rsp_t;
1610
1611/*
1612 * Report LUN command structure.
1613 */
1614#define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a)
1615
1616typedef struct {
1617 uint32_t len;
1618 uint32_t rsrv;
1619} rpt_hdr_t;
1620
1621typedef struct {
1622 struct {
1623 uint8_t b : 6;
1624 uint8_t address_method : 2;
1625 } msb;
1626 uint8_t lsb;
1627 uint8_t unused[6];
1628} rpt_lun_t;
1629
1630typedef struct {
1631 rpt_hdr_t hdr;
1632 rpt_lun_t lst[MAX_LUNS];
1633} rpt_lun_lst_t;
1634
1635/*
1636 * Report Lun mailbox IOCB packet definition.
1637 */
1638typedef struct {
1639 union {
1640 cmd_a64_entry_t cmd;
1641 sts_entry_t rsp;
3d71644c
AV		 1642 struct cmd_type_7 cmd24;
1643 struct sts_entry_24xx rsp24;
1da177e4
LT		 1644 } p;
1645 rpt_lun_lst_t list;
1646} rpt_lun_cmd_rsp_t;
1647
3d71644c 1648
1da177e4
LT		 1649/*
1650 * Fibre channel port type.
1651 */
1652 typedef enum {
1653 FCT_UNKNOWN,
1654 FCT_RSCN,
1655 FCT_SWITCH,
1656 FCT_BROADCAST,
1657 FCT_INITIATOR,
1658 FCT_TARGET
1659} fc_port_type_t;
1660
1661/*
1662 * Fibre channel port structure.
1663 */
1664typedef struct fc_port {
1665 struct list_head list;
1da177e4
LT		 1666 struct scsi_qla_host *ha;
1667 struct scsi_qla_host *vis_ha; /* only used when suspending lun */
1668
1669 uint8_t node_name[WWN_SIZE];
1670 uint8_t port_name[WWN_SIZE];
1671 port_id_t d_id;
1672 uint16_t loop_id;
1673 uint16_t old_loop_id;
1674
1675 fc_port_type_t port_type;
1676
1677 atomic_t state;
1678 uint32_t flags;
1679
bdf79621 1680 unsigned int os_target_id;
1da177e4
LT		 1681
1682 uint16_t iodesc_idx_sent;
1683
1684 int port_login_retry_count;
1685 int login_retry;
1686 atomic_t port_down_timer;
1687
1688 uint8_t device_type;
1689 uint8_t unused;
1690
1691 uint8_t mp_byte; /* multi-path byte (not used) */
1692 uint8_t cur_path; /* current path id */
1693
d97994dc 1694 spinlock_t rport_lock;
1695 struct fc_rport *rport, *drport;
ad3e0eda 1696 u32 supported_classes;
19a7b4ae
JSEC		 1697 struct work_struct rport_add_work;
1698 struct work_struct rport_del_work;
1da177e4
LT		 1699} fc_port_t;
1700
1701/*
1702 * Fibre channel port/lun states.
1703 */
1704#define FCS_UNCONFIGURED 1
1705#define FCS_DEVICE_DEAD 2
1706#define FCS_DEVICE_LOST 3
1707#define FCS_ONLINE 4
1708#define FCS_NOT_SUPPORTED 5
1709#define FCS_FAILOVER 6
1710#define FCS_FAILOVER_FAILED 7
1711
1712/*
1713 * FC port flags.
1714 */
1715#define FCF_FABRIC_DEVICE BIT_0
1716#define FCF_LOGIN_NEEDED BIT_1
1717#define FCF_FO_MASKED BIT_2
1718#define FCF_FAILOVER_NEEDED BIT_3
1719#define FCF_RESET_NEEDED BIT_4
1720#define FCF_PERSISTENT_BOUND BIT_5
1721#define FCF_TAPE_PRESENT BIT_6
1722#define FCF_FARP_DONE BIT_7
1723#define FCF_FARP_FAILED BIT_8
1724#define FCF_FARP_REPLY_NEEDED BIT_9
1725#define FCF_AUTH_REQ BIT_10
1726#define FCF_SEND_AUTH_REQ BIT_11
1727#define FCF_RECEIVE_AUTH_REQ BIT_12
1728#define FCF_AUTH_SUCCESS BIT_13
1729#define FCF_RLC_SUPPORT BIT_14
1730#define FCF_CONFIG BIT_15 /* Needed? */
1731#define FCF_RESCAN_NEEDED BIT_16
1732#define FCF_XP_DEVICE BIT_17
1733#define FCF_MSA_DEVICE BIT_18
1734#define FCF_EVA_DEVICE BIT_19
1735#define FCF_MSA_PORT_ACTIVE BIT_20
1736#define FCF_FAILBACK_DISABLE BIT_21
1737#define FCF_FAILOVER_DISABLE BIT_22
1738#define FCF_DSXXX_DEVICE BIT_23
1739#define FCF_AA_EVA_DEVICE BIT_24
3d71644c 1740#define FCF_AA_MSA_DEVICE BIT_25
1da177e4
LT		 1741
1742/* No loop ID flag. */
1743#define FC_NO_LOOP_ID 0x1000
1744
1da177e4
LT		 1745/*
1746 * FC-CT interface
1747 *
1748 * NOTE: All structures are big-endian in form.
1749 */
1750
1751#define CT_REJECT_RESPONSE 0x8001
1752#define CT_ACCEPT_RESPONSE 0x8002
cca5335c
AV		 1753#define CT_REASON_CANNOT_PERFORM 0x09
1754#define CT_EXPL_ALREADY_REGISTERED 0x10
1da177e4
LT		 1755
1756#define NS_N_PORT_TYPE 0x01
1757#define NS_NL_PORT_TYPE 0x02
1758#define NS_NX_PORT_TYPE 0x7F
1759
1760#define GA_NXT_CMD 0x100
1761#define GA_NXT_REQ_SIZE (16 + 4)
1762#define GA_NXT_RSP_SIZE (16 + 620)
1763
1764#define GID_PT_CMD 0x1A1
1765#define GID_PT_REQ_SIZE (16 + 4)
1766#define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1767
1768#define GPN_ID_CMD 0x112
1769#define GPN_ID_REQ_SIZE (16 + 4)
1770#define GPN_ID_RSP_SIZE (16 + 8)
1771
1772#define GNN_ID_CMD 0x113
1773#define GNN_ID_REQ_SIZE (16 + 4)
1774#define GNN_ID_RSP_SIZE (16 + 8)
1775
1776#define GFT_ID_CMD 0x117
1777#define GFT_ID_REQ_SIZE (16 + 4)
1778#define GFT_ID_RSP_SIZE (16 + 32)
1779
1780#define RFT_ID_CMD 0x217
1781#define RFT_ID_REQ_SIZE (16 + 4 + 32)
1782#define RFT_ID_RSP_SIZE 16
1783
1784#define RFF_ID_CMD 0x21F
1785#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1786#define RFF_ID_RSP_SIZE 16
1787
1788#define RNN_ID_CMD 0x213
1789#define RNN_ID_REQ_SIZE (16 + 4 + 8)
1790#define RNN_ID_RSP_SIZE 16
1791
1792#define RSNN_NN_CMD 0x239
1793#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1794#define RSNN_NN_RSP_SIZE 16
1795
cca5335c
AV		 1796/*
1797 * HBA attribute types.
1798 */
1799#define FDMI_HBA_ATTR_COUNT 9
1800#define FDMI_HBA_NODE_NAME 1
1801#define FDMI_HBA_MANUFACTURER 2
1802#define FDMI_HBA_SERIAL_NUMBER 3
1803#define FDMI_HBA_MODEL 4
1804#define FDMI_HBA_MODEL_DESCRIPTION 5
1805#define FDMI_HBA_HARDWARE_VERSION 6
1806#define FDMI_HBA_DRIVER_VERSION 7
1807#define FDMI_HBA_OPTION_ROM_VERSION 8
1808#define FDMI_HBA_FIRMWARE_VERSION 9
1809#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1810#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1811
1812struct ct_fdmi_hba_attr {
1813 uint16_t type;
1814 uint16_t len;
1815 union {
1816 uint8_t node_name[WWN_SIZE];
1817 uint8_t manufacturer[32];
1818 uint8_t serial_num[8];
1819 uint8_t model[16];
1820 uint8_t model_desc[80];
1821 uint8_t hw_version[16];
1822 uint8_t driver_version[32];
1823 uint8_t orom_version[16];
1824 uint8_t fw_version[16];
1825 uint8_t os_version[128];
1826 uint8_t max_ct_len[4];
1827 } a;
1828};
1829
1830struct ct_fdmi_hba_attributes {
1831 uint32_t count;
1832 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1833};
1834
1835/*
1836 * Port attribute types.
1837 */
1838#define FDMI_PORT_ATTR_COUNT 5
1839#define FDMI_PORT_FC4_TYPES 1
1840#define FDMI_PORT_SUPPORT_SPEED 2
1841#define FDMI_PORT_CURRENT_SPEED 3
1842#define FDMI_PORT_MAX_FRAME_SIZE 4
1843#define FDMI_PORT_OS_DEVICE_NAME 5
1844#define FDMI_PORT_HOST_NAME 6
1845
1846struct ct_fdmi_port_attr {
1847 uint16_t type;
1848 uint16_t len;
1849 union {
1850 uint8_t fc4_types[32];
1851 uint32_t sup_speed;
1852 uint32_t cur_speed;
1853 uint32_t max_frame_size;
1854 uint8_t os_dev_name[32];
1855 uint8_t host_name[32];
1856 } a;
1857};
1858
1859/*
1860 * Port Attribute Block.
1861 */
1862struct ct_fdmi_port_attributes {
1863 uint32_t count;
1864 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1865};
1866
1867/* FDMI definitions. */
1868#define GRHL_CMD 0x100
1869#define GHAT_CMD 0x101
1870#define GRPL_CMD 0x102
1871#define GPAT_CMD 0x110
1872
1873#define RHBA_CMD 0x200
1874#define RHBA_RSP_SIZE 16
1875
1876#define RHAT_CMD 0x201
1877#define RPRT_CMD 0x210
1878
1879#define RPA_CMD 0x211
1880#define RPA_RSP_SIZE 16
1881
1882#define DHBA_CMD 0x300
1883#define DHBA_REQ_SIZE (16 + 8)
1884#define DHBA_RSP_SIZE 16
1885
1886#define DHAT_CMD 0x301
1887#define DPRT_CMD 0x310
1888#define DPA_CMD 0x311
1889
1da177e4
LT		 1890/* CT command header -- request/response common fields */
1891struct ct_cmd_hdr {
1892 uint8_t revision;
1893 uint8_t in_id[3];
1894 uint8_t gs_type;
1895 uint8_t gs_subtype;
1896 uint8_t options;
1897 uint8_t reserved;
1898};
1899
1900/* CT command request */
1901struct ct_sns_req {
1902 struct ct_cmd_hdr header;
1903 uint16_t command;
1904 uint16_t max_rsp_size;
1905 uint8_t fragment_id;
1906 uint8_t reserved[3];
1907
1908 union {
1909 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */
1910 struct {
1911 uint8_t reserved;
1912 uint8_t port_id[3];
1913 } port_id;
1914
1915 struct {
1916 uint8_t port_type;
1917 uint8_t domain;
1918 uint8_t area;
1919 uint8_t reserved;
1920 } gid_pt;
1921
1922 struct {
1923 uint8_t reserved;
1924 uint8_t port_id[3];
1925 uint8_t fc4_types[32];
1926 } rft_id;
1927
1928 struct {
1929 uint8_t reserved;
1930 uint8_t port_id[3];
1931 uint16_t reserved2;
1932 uint8_t fc4_feature;
1933 uint8_t fc4_type;
1934 } rff_id;
1935
1936 struct {
1937 uint8_t reserved;
1938 uint8_t port_id[3];
1939 uint8_t node_name[8];
1940 } rnn_id;
1941
1942 struct {
1943 uint8_t node_name[8];
1944 uint8_t name_len;
1945 uint8_t sym_node_name[255];
1946 } rsnn_nn;
cca5335c
AV		 1947
1948 struct {
1949 uint8_t hba_indentifier[8];
1950 } ghat;
1951
1952 struct {
1953 uint8_t hba_identifier[8];
1954 uint32_t entry_count;
1955 uint8_t port_name[8];
1956 struct ct_fdmi_hba_attributes attrs;
1957 } rhba;
1958
1959 struct {
1960 uint8_t hba_identifier[8];
1961 struct ct_fdmi_hba_attributes attrs;
1962 } rhat;
1963
1964 struct {
1965 uint8_t port_name[8];
1966 struct ct_fdmi_port_attributes attrs;
1967 } rpa;
1968
1969 struct {
1970 uint8_t port_name[8];
1971 } dhba;
1972
1973 struct {
1974 uint8_t port_name[8];
1975 } dhat;
1976
1977 struct {
1978 uint8_t port_name[8];
1979 } dprt;
1980
1981 struct {
1982 uint8_t port_name[8];
1983 } dpa;
1da177e4
LT		 1984 } req;
1985};
1986
1987/* CT command response header */
1988struct ct_rsp_hdr {
1989 struct ct_cmd_hdr header;
1990 uint16_t response;
1991 uint16_t residual;
1992 uint8_t fragment_id;
1993 uint8_t reason_code;
1994 uint8_t explanation_code;
1995 uint8_t vendor_unique;
1996};
1997
1998struct ct_sns_gid_pt_data {
1999 uint8_t control_byte;
2000 uint8_t port_id[3];
2001};
2002
2003struct ct_sns_rsp {
2004 struct ct_rsp_hdr header;
2005
2006 union {
2007 struct {
2008 uint8_t port_type;
2009 uint8_t port_id[3];
2010 uint8_t port_name[8];
2011 uint8_t sym_port_name_len;
2012 uint8_t sym_port_name[255];
2013 uint8_t node_name[8];
2014 uint8_t sym_node_name_len;
2015 uint8_t sym_node_name[255];
2016 uint8_t init_proc_assoc[8];
2017 uint8_t node_ip_addr[16];
2018 uint8_t class_of_service[4];
2019 uint8_t fc4_types[32];
2020 uint8_t ip_address[16];
2021 uint8_t fabric_port_name[8];
2022 uint8_t reserved;
2023 uint8_t hard_address[3];
2024 } ga_nxt;
2025
2026 struct {
2027 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
2028 } gid_pt;
2029
2030 struct {
2031 uint8_t port_name[8];
2032 } gpn_id;
2033
2034 struct {
2035 uint8_t node_name[8];
2036 } gnn_id;
2037
2038 struct {
2039 uint8_t fc4_types[32];
2040 } gft_id;
cca5335c
AV		 2041
2042 struct {
2043 uint32_t entry_count;
2044 uint8_t port_name[8];
2045 struct ct_fdmi_hba_attributes attrs;
2046 } ghat;
1da177e4
LT		 2047 } rsp;
2048};
2049
2050struct ct_sns_pkt {
2051 union {
2052 struct ct_sns_req req;
2053 struct ct_sns_rsp rsp;
2054 } p;
2055};
2056
2057/*
2058 * SNS command structures -- for 2200 compatability.
2059 */
2060#define RFT_ID_SNS_SCMD_LEN 22
2061#define RFT_ID_SNS_CMD_SIZE 60
2062#define RFT_ID_SNS_DATA_SIZE 16
2063
2064#define RNN_ID_SNS_SCMD_LEN 10
2065#define RNN_ID_SNS_CMD_SIZE 36
2066#define RNN_ID_SNS_DATA_SIZE 16
2067
2068#define GA_NXT_SNS_SCMD_LEN 6
2069#define GA_NXT_SNS_CMD_SIZE 28
2070#define GA_NXT_SNS_DATA_SIZE (620 + 16)
2071
2072#define GID_PT_SNS_SCMD_LEN 6
2073#define GID_PT_SNS_CMD_SIZE 28
2074#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
2075
2076#define GPN_ID_SNS_SCMD_LEN 6
2077#define GPN_ID_SNS_CMD_SIZE 28
2078#define GPN_ID_SNS_DATA_SIZE (8 + 16)
2079
2080#define GNN_ID_SNS_SCMD_LEN 6
2081#define GNN_ID_SNS_CMD_SIZE 28
2082#define GNN_ID_SNS_DATA_SIZE (8 + 16)
2083
2084struct sns_cmd_pkt {
2085 union {
2086 struct {
2087 uint16_t buffer_length;
2088 uint16_t reserved_1;
2089 uint32_t buffer_address[2];
2090 uint16_t subcommand_length;
2091 uint16_t reserved_2;
2092 uint16_t subcommand;
2093 uint16_t size;
2094 uint32_t reserved_3;
2095 uint8_t param[36];
2096 } cmd;
2097
2098 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2099 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2100 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2101 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2102 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2103 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2104 } p;
2105};
2106
2107/* IO descriptors */
2108#define MAX_IO_DESCRIPTORS 32
2109
2110#define ABORT_IOCB_CB 0
2111#define ADISC_PORT_IOCB_CB 1
2112#define LOGOUT_PORT_IOCB_CB 2
2113#define LOGIN_PORT_IOCB_CB 3
2114#define LAST_IOCB_CB 4
2115
2116#define IODESC_INVALID_INDEX 0xFFFF
2117#define IODESC_ADISC_NEEDED 0xFFFE
2118#define IODESC_LOGIN_NEEDED 0xFFFD
2119
2120struct io_descriptor {
2121 uint16_t used:1;
2122 uint16_t idx:11;
2123 uint16_t cb_idx:4;
2124
2125 struct timer_list timer;
2126
2127 struct scsi_qla_host *ha;
2128
2129 port_id_t d_id;
2130 fc_port_t *remote_fcport;
2131
2132 uint32_t signature;
2133};
2134
2135struct qla_fw_info {
2136 unsigned short addressing; /* addressing method used to load fw */
2137#define FW_INFO_ADDR_NORMAL 0
2138#define FW_INFO_ADDR_EXTENDED 1
2139#define FW_INFO_ADDR_NOMORE 0xffff
2140 unsigned short *fwcode; /* pointer to FW array */
2141 unsigned short *fwlen; /* number of words in array */
2142 unsigned short *fwstart; /* start address for F/W */
2143 unsigned long *lfwstart; /* start address (long) for F/W */
2144};
2145
2146struct qla_board_info {
2147 char *drv_name;
2148
2149 char isp_name[8];
2150 struct qla_fw_info *fw_info;
fca29703
AV		 2151 char *fw_fname;
2152 struct scsi_host_template *sht;
1da177e4
LT		 2153};
2154
5433383e
AV		 2155struct fw_blob {
2156 char *name;
2157 uint32_t segs[4];
2158 const struct firmware *fw;
2159};
2160
1da177e4
LT		 2161/* Return data from MBC_GET_ID_LIST call. */
2162struct gid_list_info {
2163 uint8_t al_pa;
2164 uint8_t area;
fa2a1ce5 2165 uint8_t domain;
1da177e4
LT		 2166 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2167 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
3d71644c 2168 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
1da177e4
LT		 2169};
2170#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2171
abbd8870
AV		 2172/*
2173 * ISP operations
2174 */
2175struct isp_operations {
2176
2177 int (*pci_config) (struct scsi_qla_host *);
2178 void (*reset_chip) (struct scsi_qla_host *);
2179 int (*chip_diag) (struct scsi_qla_host *);
2180 void (*config_rings) (struct scsi_qla_host *);
2181 void (*reset_adapter) (struct scsi_qla_host *);
2182 int (*nvram_config) (struct scsi_qla_host *);
2183 void (*update_fw_options) (struct scsi_qla_host *);
2184 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2185
2186 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2187 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2188
2189 irqreturn_t (*intr_handler) (int, void *, struct pt_regs *);
2190 void (*enable_intrs) (struct scsi_qla_host *);
2191 void (*disable_intrs) (struct scsi_qla_host *);
2192
2193 int (*abort_command) (struct scsi_qla_host *, srb_t *);
2194 int (*abort_target) (struct fc_port *);
2195 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2196 uint8_t, uint8_t, uint16_t *, uint8_t);
1c7c6357
AV		 2197 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2198 uint8_t, uint8_t);
abbd8870
AV		 2199
2200 uint16_t (*calc_req_entries) (uint16_t);
2201 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
8c958a99 2202 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
cca5335c
AV		 2203 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2204 uint32_t);
abbd8870
AV		 2205
2206 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2207 uint32_t, uint32_t);
2208 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2209 uint32_t);
2210
2211 void (*fw_dump) (struct scsi_qla_host *, int);
2212 void (*ascii_fw_dump) (struct scsi_qla_host *);
f6df144c 2213
2214 int (*beacon_on) (struct scsi_qla_host *);
2215 int (*beacon_off) (struct scsi_qla_host *);
2216 void (*beacon_blink) (struct scsi_qla_host *);
854165f4 2217
2218 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2219 uint32_t, uint32_t);
2220 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2221 uint32_t);
abbd8870
AV		 2222};
2223
1da177e4
LT		 2224/*
2225 * Linux Host Adapter structure
2226 */
2227typedef struct scsi_qla_host {
2228 struct list_head list;
2229
2230 /* Commonly used flags and state information. */
2231 struct Scsi_Host *host;
2232 struct pci_dev *pdev;
2233
2234 unsigned long host_no;
2235 unsigned long instance;
2236
2237 volatile struct {
2238 uint32_t init_done :1;
2239 uint32_t online :1;
2240 uint32_t mbox_int :1;
2241 uint32_t mbox_busy :1;
2242 uint32_t rscn_queue_overflow :1;
2243 uint32_t reset_active :1;
2244
2245 uint32_t management_server_logged_in :1;
2246 uint32_t process_response_queue :1;
2247
2248 uint32_t disable_risc_code_load :1;
2249 uint32_t enable_64bit_addressing :1;
2250 uint32_t enable_lip_reset :1;
2251 uint32_t enable_lip_full_login :1;
2252 uint32_t enable_target_reset :1;
2253 uint32_t enable_led_scheme :1;
3d71644c
AV		 2254 uint32_t msi_enabled :1;
2255 uint32_t msix_enabled :1;
1da177e4
LT		 2256 } flags;
2257
2258 atomic_t loop_state;
2259#define LOOP_TIMEOUT 1
2260#define LOOP_DOWN 2
2261#define LOOP_UP 3
2262#define LOOP_UPDATE 4
2263#define LOOP_READY 5
2264#define LOOP_DEAD 6
2265
2266 unsigned long dpc_flags;
2267#define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2268#define RESET_ACTIVE 1
2269#define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2270#define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2271#define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2272#define LOOP_RESYNC_ACTIVE 5
2273#define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2274#define RSCN_UPDATE 7 /* Perform an RSCN update. */
2275#define MAILBOX_RETRY 8
2276#define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2277#define FAILOVER_EVENT_NEEDED 10
2278#define FAILOVER_EVENT 11
2279#define FAILOVER_NEEDED 12
2280#define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2281#define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2282#define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2283#define ABORT_QUEUES_NEEDED 16
2284#define RELOGIN_NEEDED 17
2285#define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2286#define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2287#define ISP_ABORT_RETRY 20 /* ISP aborted. */
2288#define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2289#define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
fa2a1ce5 2290#define IOCTL_ERROR_RECOVERY 23
1da177e4 2291#define LOOP_RESET_NEEDED 24
3d71644c 2292#define BEACON_BLINK_NEEDED 25
cca5335c 2293#define REGISTER_FDMI_NEEDED 26
d97994dc 2294#define FCPORT_UPDATE_NEEDED 27
1da177e4
LT		 2295
2296 uint32_t device_flags;
2297#define DFLG_LOCAL_DEVICES BIT_0
2298#define DFLG_RETRY_LOCAL_DEVICES BIT_1
2299#define DFLG_FABRIC_DEVICES BIT_2
2300#define SWITCH_FOUND BIT_3
2301#define DFLG_NO_CABLE BIT_4
2302
2303 /* SRB cache. */
2304#define SRB_MIN_REQ 128
2305 mempool_t *srb_mempool;
2306
fa2a1ce5 2307 /* This spinlock is used to protect "io transactions", you must
1da177e4
LT		 2308 * aquire it before doing any IO to the card, eg with RD_REG*() and
2309 * WRT_REG*() for the duration of your entire commandtransaction.
2310 *
2311 * This spinlock is of lower priority than the io request lock.
2312 */
2313
2314 spinlock_t hardware_lock ____cacheline_aligned;
2315
2316 device_reg_t __iomem *iobase; /* Base I/O address */
2317 unsigned long pio_address;
2318 unsigned long pio_length;
2319#define MIN_IOBASE_LEN 0x100
2320
2321 /* ISP ring lock, rings, and indexes */
2322 dma_addr_t request_dma; /* Physical address. */
2323 request_t *request_ring; /* Base virtual address */
2324 request_t *request_ring_ptr; /* Current address. */
2325 uint16_t req_ring_index; /* Current index. */
2326 uint16_t req_q_cnt; /* Number of available entries. */
2327 uint16_t request_q_length;
2328
2329 dma_addr_t response_dma; /* Physical address. */
2330 response_t *response_ring; /* Base virtual address */
2331 response_t *response_ring_ptr; /* Current address. */
2332 uint16_t rsp_ring_index; /* Current index. */
2333 uint16_t response_q_length;
fa2a1ce5 2334
abbd8870 2335 struct isp_operations isp_ops;
1da177e4
LT		 2336
2337 /* Outstandings ISP commands. */
2338 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
fa2a1ce5 2339 uint32_t current_outstanding_cmd;
1da177e4
LT		 2340 srb_t *status_srb; /* Status continuation entry. */
2341
1da177e4
LT		 2342 uint16_t revision;
2343 uint8_t ports;
1da177e4
LT		 2344
2345 /* ISP configuration data. */
2346 uint16_t loop_id; /* Host adapter loop id */
2347 uint16_t fb_rev;
2348
2349 port_id_t d_id; /* Host adapter port id */
2350 uint16_t max_public_loop_ids;
2351 uint16_t min_external_loopid; /* First external loop Id */
2352
2353 uint16_t link_data_rate; /* F/W operating speed */
04414013 2354#define LDR_1GB 0
2355#define LDR_2GB 1
2356#define LDR_4GB 3
2357#define LDR_UNKNOWN 0xFFFF
1da177e4
LT		 2358
2359 uint8_t current_topology;
2360 uint8_t prev_topology;
2361#define ISP_CFG_NL 1
2362#define ISP_CFG_N 2
2363#define ISP_CFG_FL 4
2364#define ISP_CFG_F 8
2365
2366 uint8_t operating_mode; /* F/W operating mode */
2367#define LOOP 0
2368#define P2P 1
2369#define LOOP_P2P 2
2370#define P2P_LOOP 3
2371
fa2a1ce5 2372 uint8_t marker_needed;
1da177e4
LT		 2373
2374 uint8_t interrupts_on;
2375
2376 /* HBA serial number */
2377 uint8_t serial0;
2378 uint8_t serial1;
2379 uint8_t serial2;
2380
2381 /* NVRAM configuration data */
3d71644c 2382 uint16_t nvram_size;
1da177e4
LT		 2383 uint16_t nvram_base;
2384
2385 uint16_t loop_reset_delay;
1da177e4
LT		 2386 uint8_t retry_count;
2387 uint8_t login_timeout;
2388 uint16_t r_a_tov;
2389 int port_down_retry_count;
1da177e4 2390 uint8_t mbx_count;
1da177e4 2391 uint16_t last_loop_id;
cca5335c 2392 uint16_t mgmt_svr_loop_id;
1da177e4 2393
fa2a1ce5 2394 uint32_t login_retry_count;
1da177e4
LT		 2395
2396 /* Fibre Channel Device List. */
2397 struct list_head fcports;
2398 struct list_head rscn_fcports;
2399
2400 struct io_descriptor io_descriptors[MAX_IO_DESCRIPTORS];
2401 uint16_t iodesc_signature;
2402
1da177e4
LT		 2403 /* RSCN queue. */
2404 uint32_t rscn_queue[MAX_RSCN_COUNT];
2405 uint8_t rscn_in_ptr;
2406 uint8_t rscn_out_ptr;
2407
2408 /* SNS command interfaces. */
2409 ms_iocb_entry_t *ms_iocb;
2410 dma_addr_t ms_iocb_dma;
2411 struct ct_sns_pkt *ct_sns;
2412 dma_addr_t ct_sns_dma;
2413 /* SNS command interfaces for 2200. */
2414 struct sns_cmd_pkt *sns_cmd;
2415 dma_addr_t sns_cmd_dma;
2416
39a11240 2417 struct task_struct *dpc_thread;
1da177e4
LT		 2418 uint8_t dpc_active; /* DPC routine is active */
2419
2420 /* Timeout timers. */
1da177e4
LT		 2421 uint8_t loop_down_abort_time; /* port down timer */
2422 atomic_t loop_down_timer; /* loop down timer */
2423 uint8_t link_down_timeout; /* link down timeout */
2424
2425 uint32_t timer_active;
2426 struct timer_list timer;
2427
2428 dma_addr_t gid_list_dma;
2429 struct gid_list_info *gid_list;
abbd8870 2430 int gid_list_info_size;
1da177e4
LT		 2431
2432 dma_addr_t rlc_rsp_dma;
2433 rpt_lun_cmd_rsp_t *rlc_rsp;
2434
fa2a1ce5 2435 /* Small DMA pool allocations -- maximum 256 bytes in length. */
1da177e4
LT		 2436#define DMA_POOL_SIZE 256
2437 struct dma_pool *s_dma_pool;
2438
2439 dma_addr_t init_cb_dma;
3d71644c
AV		 2440 init_cb_t *init_cb;
2441 int init_cb_size;
1da177e4
LT		 2442
2443 dma_addr_t iodesc_pd_dma;
2444 port_database_t *iodesc_pd;
2445
2446 /* These are used by mailbox operations. */
2447 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2448
2449 mbx_cmd_t *mcp;
2450 unsigned long mbx_cmd_flags;
2451#define MBX_INTERRUPT 1
2452#define MBX_INTR_WAIT 2
2453#define MBX_UPDATE_FLASH_ACTIVE 3
2454
2455 spinlock_t mbx_reg_lock; /* Mbx Cmd Register Lock */
2456
2457 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */
2458 struct semaphore mbx_intr_sem; /* Used for completion notification */
2459
2460 uint32_t mbx_flags;
2461#define MBX_IN_PROGRESS BIT_0
2462#define MBX_BUSY BIT_1 /* Got the Access */
fa2a1ce5 2463#define MBX_SLEEPING_ON_SEM BIT_2
1da177e4
LT		 2464#define MBX_POLLING_FOR_COMP BIT_3
2465#define MBX_COMPLETED BIT_4
fa2a1ce5 2466#define MBX_TIMEDOUT BIT_5
1da177e4
LT		 2467#define MBX_ACCESS_TIMEDOUT BIT_6
2468
2469 mbx_cmd_t mc;
2470
1da177e4
LT		 2471 /* Basic firmware related information. */
2472 struct qla_board_info *brd_info;
2473 uint16_t fw_major_version;
2474 uint16_t fw_minor_version;
2475 uint16_t fw_subminor_version;
2476 uint16_t fw_attributes;
2477 uint32_t fw_memory_size;
2478 uint32_t fw_transfer_size;
2479
2480 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2481 uint8_t fw_seriallink_options[4];
3d71644c 2482 uint16_t fw_seriallink_options24[4];
1da177e4
LT		 2483
2484 /* Firmware dump information. */
2485 void *fw_dump;
2486 int fw_dump_order;
2487 int fw_dump_reading;
2488 char *fw_dump_buffer;
2489 int fw_dump_buffer_len;
2490
3d71644c
AV		 2491 int fw_dumped;
2492 void *fw_dump24;
2493 int fw_dump24_len;
2494
1da177e4 2495 uint8_t host_str[16];
3d71644c 2496 uint32_t pci_attr;
1da177e4
LT		 2497
2498 uint16_t product_id[4];
2499
2500 uint8_t model_number[16+1];
2501#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2502 char *model_desc;
cca5335c 2503 uint8_t adapter_id[16+1];
1da177e4 2504
3d71644c
AV		 2505 uint8_t *node_name;
2506 uint8_t *port_name;
1da177e4
LT		 2507 uint32_t isp_abort_cnt;
2508
854165f4 2509 /* Option ROM information. */
2510 char *optrom_buffer;
2511 uint32_t optrom_size;
2512 int optrom_state;
2513#define QLA_SWAITING 0
2514#define QLA_SREADING 1
2515#define QLA_SWRITING 2
2516
1da177e4
LT		 2517 /* Needed for BEACON */
2518 uint16_t beacon_blink_led;
f6df144c 2519 uint8_t beacon_color_state;
2520#define QLA_LED_GRN_ON 0x01
2521#define QLA_LED_YLW_ON 0x02
2522#define QLA_LED_ABR_ON 0x04
2523#define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2524 /* ISP2322: red, green, amber. */
4fdfefe5
AV		 2525
2526 uint16_t zio_mode;
2527 uint16_t zio_timer;
392e2f65 2528 struct fc_host_statistics fc_host_stat;
1da177e4
LT		 2529} scsi_qla_host_t;
2530
2531
2532/*
2533 * Macros to help code, maintain, etc.
2534 */
2535#define LOOP_TRANSITION(ha) \
2536 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
23443b1d 2537 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
1da177e4 2538 atomic_read(&ha->loop_state) == LOOP_DOWN)
fa2a1ce5 2539
1da177e4 2540#define TGT_Q(ha, t) (ha->otgt[t])
1da177e4
LT		 2541
2542#define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2543
2544#define qla_printk(level, ha, format, arg...) \
2545 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2546
2547/*
2548 * qla2x00 local function return status codes
2549 */
2550#define MBS_MASK 0x3fff
2551
2552#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2553#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2554#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2555#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2556#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2557#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2558#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2559#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2560#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2561#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2562
2563#define QLA_FUNCTION_TIMEOUT 0x100
2564#define QLA_FUNCTION_PARAMETER_ERROR 0x101
2565#define QLA_FUNCTION_FAILED 0x102
2566#define QLA_MEMORY_ALLOC_FAILED 0x103
2567#define QLA_LOCK_TIMEOUT 0x104
2568#define QLA_ABORTED 0x105
2569#define QLA_SUSPENDED 0x106
2570#define QLA_BUSY 0x107
2571#define QLA_RSCNS_HANDLED 0x108
cca5335c 2572#define QLA_ALREADY_REGISTERED 0x109
1da177e4
LT		 2573
2574/*
2575* Stat info for all adpaters
2576*/
2577struct _qla2x00stats {
2578 unsigned long mboxtout; /* mailbox timeouts */
2579 unsigned long mboxerr; /* mailbox errors */
2580 unsigned long ispAbort; /* ISP aborts */
2581 unsigned long debugNo;
2582 unsigned long loop_resync;
2583 unsigned long outarray_full;
2584 unsigned long retry_q_cnt;
2585};
2586
2587#define NVRAM_DELAY() udelay(10)
2588
2589#define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2590
2591/*
2592 * Flash support definitions
2593 */
854165f4 2594#define OPTROM_SIZE_2300 0x20000
2595#define OPTROM_SIZE_2322 0x100000
2596#define OPTROM_SIZE_24XX 0x100000
1da177e4
LT		 2597
2598#include "qla_gbl.h"
2599#include "qla_dbg.h"
2600#include "qla_inline.h"
1da177e4
LT		 2601
2602/*
2603* String arrays
2604*/
2605#define LINESIZE 256
2606#define MAXARGS 26
2607
2608#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2609#define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2610#define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2611#define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2612#define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2613#define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2614
2615#endif
Linux 6.x block layer and io_uring tree(s)