[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_dbg.h

/*
 * QLogic Fibre Channel HBA Driver
 * Copyright (c)  2003-2008 QLogic Corporation
 *
 * See LICENSE.qla2xxx for copyright and licensing details.
 */

#include "qla_def.h"

/*
 * Driver debug definitions.
 */
/* #define QL_DEBUG_LEVEL_1  */ /* Output register accesses to COM1 */
/* #define QL_DEBUG_LEVEL_2  */ /* Output error msgs to COM1 */
/* #define QL_DEBUG_LEVEL_3  */ /* Output function trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_4  */ /* Output NVRAM trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_5  */ /* Output ring trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_6  */ /* Output WATCHDOG timer trace to COM1 */
/* #define QL_DEBUG_LEVEL_7  */ /* Output RISC load trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_8  */ /* Output ring saturation msgs to COM1 */
/* #define QL_DEBUG_LEVEL_9  */ /* Output IOCTL trace msgs */
/* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */
/* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */
/* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */
/* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */
/* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */
/* #define QL_DEBUG_LEVEL_15 */ /* Output NPIV trace msgs */
/* #define QL_DEBUG_LEVEL_16 */ /* Output ISP84XX trace msgs */
/* #define QL_DEBUG_LEVEL_17 */ /* Output EEH trace messages */

/*
* Macros use for debugging the driver.
*/

#define DEBUG(x)	do { if (ql2xextended_error_logging) { x; } } while (0)

#if defined(QL_DEBUG_LEVEL_1)
#define DEBUG1(x)	do {x;} while (0)
#else
#define DEBUG1(x)	do {} while (0)
#endif

#define DEBUG2(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_3(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_3_11(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_9_10(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_11(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_13(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_16(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_17(x) 	do { if (ql2xextended_error_logging) { x; } } while (0)

#if defined(QL_DEBUG_LEVEL_3)
#define DEBUG3(x)	do {x;} while (0)
#define DEBUG3_11(x)	do {x;} while (0)
#else
#define DEBUG3(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_4)
#define DEBUG4(x)	do {x;} while (0)
#else
#define DEBUG4(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_5)
#define DEBUG5(x)          do {x;} while (0)
#else
#define DEBUG5(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_7)
#define DEBUG7(x)          do {x;} while (0)
#else
#define DEBUG7(x)	   do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_9)
#define DEBUG9(x)       do {x;} while (0)
#define DEBUG9_10(x)    do {x;} while (0)
#else
#define DEBUG9(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_10)
#define DEBUG10(x)      do {x;} while (0)
#define DEBUG9_10(x)	do {x;} while (0)
#else
#define DEBUG10(x)	do {} while (0)
  #if !defined(DEBUG9_10)
  #define DEBUG9_10(x)	do {} while (0)
  #endif
#endif

#if defined(QL_DEBUG_LEVEL_11)
#define DEBUG11(x)      do{x;} while(0)
#if !defined(DEBUG3_11)
#define DEBUG3_11(x)    do{x;} while(0)
#endif
#else
#define DEBUG11(x)	do{} while(0)
  #if !defined(QL_DEBUG_LEVEL_3)
  #define DEBUG3_11(x)	do{} while(0)
  #endif
#endif

#if defined(QL_DEBUG_LEVEL_12)
#define DEBUG12(x)      do {x;} while (0)
#else
#define DEBUG12(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_13)
#define DEBUG13(x)      do {x;} while (0)
#else
#define DEBUG13(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_14)
#define DEBUG14(x)      do {x;} while (0)
#else
#define DEBUG14(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_15)
#define DEBUG15(x)      do {x;} while (0)
#else
#define DEBUG15(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_16)
#define DEBUG16(x)	do {x;} while (0)
#else
#define DEBUG16(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_17)
#define DEBUG17(x)	do {x;} while (0)
#else
#define DEBUG17(x)	do {} while (0)
#endif

/*
 * Firmware Dump structure definition
 */

struct qla2300_fw_dump {
	uint16_t hccr;
	uint16_t pbiu_reg[8];
	uint16_t risc_host_reg[8];
	uint16_t mailbox_reg[32];
	uint16_t resp_dma_reg[32];
	uint16_t dma_reg[48];
	uint16_t risc_hdw_reg[16];
	uint16_t risc_gp0_reg[16];
	uint16_t risc_gp1_reg[16];
	uint16_t risc_gp2_reg[16];
	uint16_t risc_gp3_reg[16];
	uint16_t risc_gp4_reg[16];
	uint16_t risc_gp5_reg[16];
	uint16_t risc_gp6_reg[16];
	uint16_t risc_gp7_reg[16];
	uint16_t frame_buf_hdw_reg[64];
	uint16_t fpm_b0_reg[64];
	uint16_t fpm_b1_reg[64];
	uint16_t risc_ram[0xf800];
	uint16_t stack_ram[0x1000];
	uint16_t data_ram[1];
};

struct qla2100_fw_dump {
	uint16_t hccr;
	uint16_t pbiu_reg[8];
	uint16_t mailbox_reg[32];
	uint16_t dma_reg[48];
	uint16_t risc_hdw_reg[16];
	uint16_t risc_gp0_reg[16];
	uint16_t risc_gp1_reg[16];
	uint16_t risc_gp2_reg[16];
	uint16_t risc_gp3_reg[16];
	uint16_t risc_gp4_reg[16];
	uint16_t risc_gp5_reg[16];
	uint16_t risc_gp6_reg[16];
	uint16_t risc_gp7_reg[16];
	uint16_t frame_buf_hdw_reg[16];
	uint16_t fpm_b0_reg[64];
	uint16_t fpm_b1_reg[64];
	uint16_t risc_ram[0xf000];
};

struct qla24xx_fw_dump {
	uint32_t host_status;
	uint32_t host_reg[32];
	uint32_t shadow_reg[7];
	uint16_t mailbox_reg[32];
	uint32_t xseq_gp_reg[128];
	uint32_t xseq_0_reg[16];
	uint32_t xseq_1_reg[16];
	uint32_t rseq_gp_reg[128];
	uint32_t rseq_0_reg[16];
	uint32_t rseq_1_reg[16];
	uint32_t rseq_2_reg[16];
	uint32_t cmd_dma_reg[16];
	uint32_t req0_dma_reg[15];
	uint32_t resp0_dma_reg[15];
	uint32_t req1_dma_reg[15];
	uint32_t xmt0_dma_reg[32];
	uint32_t xmt1_dma_reg[32];
	uint32_t xmt2_dma_reg[32];
	uint32_t xmt3_dma_reg[32];
	uint32_t xmt4_dma_reg[32];
	uint32_t xmt_data_dma_reg[16];
	uint32_t rcvt0_data_dma_reg[32];
	uint32_t rcvt1_data_dma_reg[32];
	uint32_t risc_gp_reg[128];
	uint32_t lmc_reg[112];
	uint32_t fpm_hdw_reg[192];
	uint32_t fb_hdw_reg[176];
	uint32_t code_ram[0x2000];
	uint32_t ext_mem[1];
};

struct qla25xx_fw_dump {
	uint32_t host_status;
	uint32_t host_risc_reg[32];
	uint32_t pcie_regs[4];
	uint32_t host_reg[32];
	uint32_t shadow_reg[11];
	uint32_t risc_io_reg;
	uint16_t mailbox_reg[32];
	uint32_t xseq_gp_reg[128];
	uint32_t xseq_0_reg[48];
	uint32_t xseq_1_reg[16];
	uint32_t rseq_gp_reg[128];
	uint32_t rseq_0_reg[32];
	uint32_t rseq_1_reg[16];
	uint32_t rseq_2_reg[16];
	uint32_t aseq_gp_reg[128];
	uint32_t aseq_0_reg[32];
	uint32_t aseq_1_reg[16];
	uint32_t aseq_2_reg[16];
	uint32_t cmd_dma_reg[16];
	uint32_t req0_dma_reg[15];
	uint32_t resp0_dma_reg[15];
	uint32_t req1_dma_reg[15];
	uint32_t xmt0_dma_reg[32];
	uint32_t xmt1_dma_reg[32];
	uint32_t xmt2_dma_reg[32];
	uint32_t xmt3_dma_reg[32];
	uint32_t xmt4_dma_reg[32];
	uint32_t xmt_data_dma_reg[16];
	uint32_t rcvt0_data_dma_reg[32];
	uint32_t rcvt1_data_dma_reg[32];
	uint32_t risc_gp_reg[128];
	uint32_t lmc_reg[128];
	uint32_t fpm_hdw_reg[192];
	uint32_t fb_hdw_reg[192];
	uint32_t code_ram[0x2000];
	uint32_t ext_mem[1];
};

struct qla81xx_fw_dump {
	uint32_t host_status;
	uint32_t host_risc_reg[32];
	uint32_t pcie_regs[4];
	uint32_t host_reg[32];
	uint32_t shadow_reg[11];
	uint32_t risc_io_reg;
	uint16_t mailbox_reg[32];
	uint32_t xseq_gp_reg[128];
	uint32_t xseq_0_reg[48];
	uint32_t xseq_1_reg[16];
	uint32_t rseq_gp_reg[128];
	uint32_t rseq_0_reg[32];
	uint32_t rseq_1_reg[16];
	uint32_t rseq_2_reg[16];
	uint32_t aseq_gp_reg[128];
	uint32_t aseq_0_reg[32];
	uint32_t aseq_1_reg[16];
	uint32_t aseq_2_reg[16];
	uint32_t cmd_dma_reg[16];
	uint32_t req0_dma_reg[15];
	uint32_t resp0_dma_reg[15];
	uint32_t req1_dma_reg[15];
	uint32_t xmt0_dma_reg[32];
	uint32_t xmt1_dma_reg[32];
	uint32_t xmt2_dma_reg[32];
	uint32_t xmt3_dma_reg[32];
	uint32_t xmt4_dma_reg[32];
	uint32_t xmt_data_dma_reg[16];
	uint32_t rcvt0_data_dma_reg[32];
	uint32_t rcvt1_data_dma_reg[32];
	uint32_t risc_gp_reg[128];
	uint32_t lmc_reg[128];
	uint32_t fpm_hdw_reg[224];
	uint32_t fb_hdw_reg[208];
	uint32_t code_ram[0x2000];
	uint32_t ext_mem[1];
};

#define EFT_NUM_BUFFERS		4
#define EFT_BYTES_PER_BUFFER	0x4000
#define EFT_SIZE		((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))

#define FCE_NUM_BUFFERS		64
#define FCE_BYTES_PER_BUFFER	0x400
#define FCE_SIZE		((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS))
#define fce_calc_size(b)	((FCE_BYTES_PER_BUFFER) * (b))

struct qla2xxx_fce_chain {
	uint32_t type;
	uint32_t chain_size;

	uint32_t size;
	uint32_t addr_l;
	uint32_t addr_h;
	uint32_t eregs[8];
};

struct qla2xxx_mq_chain {
	uint32_t type;
	uint32_t chain_size;

	uint32_t count;
	uint32_t qregs[4 * QLA_MQ_SIZE];
};

#define DUMP_CHAIN_VARIANT	0x80000000
#define DUMP_CHAIN_FCE		0x7FFFFAF0
#define DUMP_CHAIN_MQ		0x7FFFFAF1
#define DUMP_CHAIN_LAST		0x80000000

struct qla2xxx_fw_dump {
	uint8_t signature[4];
	uint32_t version;

	uint32_t fw_major_version;
	uint32_t fw_minor_version;
	uint32_t fw_subminor_version;
	uint32_t fw_attributes;

	uint32_t vendor;
	uint32_t device;
	uint32_t subsystem_vendor;
	uint32_t subsystem_device;

	uint32_t fixed_size;
	uint32_t mem_size;
	uint32_t req_q_size;
	uint32_t rsp_q_size;

	uint32_t eft_size;
	uint32_t eft_addr_l;
	uint32_t eft_addr_h;

	uint32_t header_size;

	union {
		struct qla2100_fw_dump isp21;
		struct qla2300_fw_dump isp23;
		struct qla24xx_fw_dump isp24;
		struct qla25xx_fw_dump isp25;
		struct qla81xx_fw_dump isp81;
	} isp;
};
Commit	Line	Data
fa90c54f AV	1	/*
fa90c54f AV	2	* QLogic Fibre Channel HBA Driver
01e58d8e	3	* Copyright (c) 2003-2008 QLogic Corporation
1da177e4	4	*
fa90c54f AV	5	* See LICENSE.qla2xxx for copyright and licensing details.
fa90c54f AV	6	*/
73208dfd AC	7
	8	#include "qla_def.h"
	9
1da177e4 LT	10	/*
	11	* Driver debug definitions.
	12	*/
	13	/* #define QL_DEBUG_LEVEL_1 / / Output register accesses to COM1 */
	14	/* #define QL_DEBUG_LEVEL_2 / / Output error msgs to COM1 */
	15	/* #define QL_DEBUG_LEVEL_3 / / Output function trace msgs to COM1 */
	16	/* #define QL_DEBUG_LEVEL_4 / / Output NVRAM trace msgs to COM1 */
	17	/* #define QL_DEBUG_LEVEL_5 / / Output ring trace msgs to COM1 */
	18	/* #define QL_DEBUG_LEVEL_6 / / Output WATCHDOG timer trace to COM1 */
	19	/* #define QL_DEBUG_LEVEL_7 / / Output RISC load trace msgs to COM1 */
	20	/* #define QL_DEBUG_LEVEL_8 / / Output ring saturation msgs to COM1 */
	21	/* #define QL_DEBUG_LEVEL_9 / / Output IOCTL trace msgs */
	22	/* #define QL_DEBUG_LEVEL_10 / / Output IOCTL error msgs */
	23	/* #define QL_DEBUG_LEVEL_11 / / Output Mbx Cmd trace msgs */
	24	/* #define QL_DEBUG_LEVEL_12 / / Output IP trace msgs */
	25	/* #define QL_DEBUG_LEVEL_13 / / Output fdmi function trace msgs */
	26	/* #define QL_DEBUG_LEVEL_14 / / Output RSCN trace msgs */
2c3dfe3f	27	/* #define QL_DEBUG_LEVEL_15 / / Output NPIV trace msgs */
4d4df193	28	/* #define QL_DEBUG_LEVEL_16 / / Output ISP84XX trace msgs */
85880801	29	/* #define QL_DEBUG_LEVEL_17 / / Output EEH trace messages */
1da177e4 LT	30
	31	/*
	32	* Macros use for debugging the driver.
	33	*/
1da177e4	34
11010fec	35	#define DEBUG(x) do { if (ql2xextended_error_logging) { x; } } while (0)
1da177e4 LT	36
1da177e4 LT	37	#if defined(QL_DEBUG_LEVEL_1)
744f11fd	38	#define DEBUG1(x) do {x;} while (0)
1da177e4	39	#else
744f11fd	40	#define DEBUG1(x) do {} while (0)
1da177e4 LT	41	#endif
1da177e4 LT	42
11010fec AV	43	#define DEBUG2(x) do { if (ql2xextended_error_logging) { x; } } while (0)
	44	#define DEBUG2_3(x) do { if (ql2xextended_error_logging) { x; } } while (0)
	45	#define DEBUG2_3_11(x) do { if (ql2xextended_error_logging) { x; } } while (0)
	46	#define DEBUG2_9_10(x) do { if (ql2xextended_error_logging) { x; } } while (0)
	47	#define DEBUG2_11(x) do { if (ql2xextended_error_logging) { x; } } while (0)
	48	#define DEBUG2_13(x) do { if (ql2xextended_error_logging) { x; } } while (0)
4d4df193	49	#define DEBUG2_16(x) do { if (ql2xextended_error_logging) { x; } } while (0)
73208dfd	50	#define DEBUG2_17(x) do { if (ql2xextended_error_logging) { x; } } while (0)
1da177e4 LT	51
1da177e4 LT	52	#if defined(QL_DEBUG_LEVEL_3)
744f11fd	53	#define DEBUG3(x) do {x;} while (0)
744f11fd	54	#define DEBUG3_11(x) do {x;} while (0)
1da177e4	55	#else
744f11fd	56	#define DEBUG3(x) do {} while (0)
1da177e4 LT	57	#endif
	58
	59	#if defined(QL_DEBUG_LEVEL_4)
744f11fd	60	#define DEBUG4(x) do {x;} while (0)
1da177e4	61	#else
744f11fd	62	#define DEBUG4(x) do {} while (0)
1da177e4 LT	63	#endif
	64
	65	#if defined(QL_DEBUG_LEVEL_5)
744f11fd	66	#define DEBUG5(x) do {x;} while (0)
1da177e4	67	#else
744f11fd	68	#define DEBUG5(x) do {} while (0)
1da177e4 LT	69	#endif
	70
	71	#if defined(QL_DEBUG_LEVEL_7)
744f11fd	72	#define DEBUG7(x) do {x;} while (0)
1da177e4	73	#else
744f11fd	74	#define DEBUG7(x) do {} while (0)
1da177e4 LT	75	#endif
	76
	77	#if defined(QL_DEBUG_LEVEL_9)
744f11fd AV	78	#define DEBUG9(x) do {x;} while (0)
744f11fd AV	79	#define DEBUG9_10(x) do {x;} while (0)
1da177e4	80	#else
744f11fd	81	#define DEBUG9(x) do {} while (0)
1da177e4 LT	82	#endif
	83
	84	#if defined(QL_DEBUG_LEVEL_10)
744f11fd	85	#define DEBUG10(x) do {x;} while (0)
744f11fd	86	#define DEBUG9_10(x) do {x;} while (0)
1da177e4	87	#else
744f11fd	88	#define DEBUG10(x) do {} while (0)
1da177e4	89	#if !defined(DEBUG9_10)
744f11fd	90	#define DEBUG9_10(x) do {} while (0)
1da177e4 LT	91	#endif
	92	#endif
	93
	94	#if defined(QL_DEBUG_LEVEL_11)
744f11fd	95	#define DEBUG11(x) do{x;} while(0)
1da177e4	96	#if !defined(DEBUG3_11)
744f11fd	97	#define DEBUG3_11(x) do{x;} while(0)
1da177e4 LT	98	#endif
1da177e4 LT	99	#else
744f11fd	100	#define DEBUG11(x) do{} while(0)
1da177e4	101	#if !defined(QL_DEBUG_LEVEL_3)
744f11fd	102	#define DEBUG3_11(x) do{} while(0)
1da177e4 LT	103	#endif
	104	#endif
	105
	106	#if defined(QL_DEBUG_LEVEL_12)
744f11fd	107	#define DEBUG12(x) do {x;} while (0)
1da177e4	108	#else
744f11fd	109	#define DEBUG12(x) do {} while (0)
1da177e4 LT	110	#endif
	111
	112	#if defined(QL_DEBUG_LEVEL_13)
	113	#define DEBUG13(x) do {x;} while (0)
	114	#else
	115	#define DEBUG13(x) do {} while (0)
	116	#endif
	117
	118	#if defined(QL_DEBUG_LEVEL_14)
	119	#define DEBUG14(x) do {x;} while (0)
	120	#else
	121	#define DEBUG14(x) do {} while (0)
	122	#endif
	123
2c3dfe3f SJ	124	#if defined(QL_DEBUG_LEVEL_15)
	125	#define DEBUG15(x) do {x;} while (0)
	126	#else
	127	#define DEBUG15(x) do {} while (0)
	128	#endif
	129
4d4df193 HK	130	#if defined(QL_DEBUG_LEVEL_16)
	131	#define DEBUG16(x) do {x;} while (0)
	132	#else
	133	#define DEBUG16(x) do {} while (0)
	134	#endif
85880801 AV	135
	136	#if defined(QL_DEBUG_LEVEL_17)
	137	#define DEBUG17(x) do {x;} while (0)
	138	#else
	139	#define DEBUG17(x) do {} while (0)
	140	#endif
	141
1da177e4 LT	142	/*
	143	* Firmware Dump structure definition
	144	*/
1da177e4 LT	145
	146	struct qla2300_fw_dump {
	147	uint16_t hccr;
	148	uint16_t pbiu_reg[8];
	149	uint16_t risc_host_reg[8];
	150	uint16_t mailbox_reg[32];
	151	uint16_t resp_dma_reg[32];
	152	uint16_t dma_reg[48];
	153	uint16_t risc_hdw_reg[16];
	154	uint16_t risc_gp0_reg[16];
	155	uint16_t risc_gp1_reg[16];
	156	uint16_t risc_gp2_reg[16];
	157	uint16_t risc_gp3_reg[16];
	158	uint16_t risc_gp4_reg[16];
	159	uint16_t risc_gp5_reg[16];
	160	uint16_t risc_gp6_reg[16];
	161	uint16_t risc_gp7_reg[16];
	162	uint16_t frame_buf_hdw_reg[64];
	163	uint16_t fpm_b0_reg[64];
	164	uint16_t fpm_b1_reg[64];
	165	uint16_t risc_ram[0xf800];
	166	uint16_t stack_ram[0x1000];
	167	uint16_t data_ram[1];
	168	};
	169
	170	struct qla2100_fw_dump {
	171	uint16_t hccr;
	172	uint16_t pbiu_reg[8];
	173	uint16_t mailbox_reg[32];
	174	uint16_t dma_reg[48];
	175	uint16_t risc_hdw_reg[16];
	176	uint16_t risc_gp0_reg[16];
	177	uint16_t risc_gp1_reg[16];
	178	uint16_t risc_gp2_reg[16];
	179	uint16_t risc_gp3_reg[16];
	180	uint16_t risc_gp4_reg[16];
	181	uint16_t risc_gp5_reg[16];
	182	uint16_t risc_gp6_reg[16];
	183	uint16_t risc_gp7_reg[16];
	184	uint16_t frame_buf_hdw_reg[16];
	185	uint16_t fpm_b0_reg[64];
	186	uint16_t fpm_b1_reg[64];
	187	uint16_t risc_ram[0xf000];
	188	};
	189
6d9b61ed	190	struct qla24xx_fw_dump {
210d5350	191	uint32_t host_status;
6d9b61ed	192	uint32_t host_reg[32];
210d5350	193	uint32_t shadow_reg[7];
6d9b61ed AV	194	uint16_t mailbox_reg[32];
	195	uint32_t xseq_gp_reg[128];
	196	uint32_t xseq_0_reg[16];
	197	uint32_t xseq_1_reg[16];
	198	uint32_t rseq_gp_reg[128];
	199	uint32_t rseq_0_reg[16];
	200	uint32_t rseq_1_reg[16];
	201	uint32_t rseq_2_reg[16];
	202	uint32_t cmd_dma_reg[16];
	203	uint32_t req0_dma_reg[15];
	204	uint32_t resp0_dma_reg[15];
	205	uint32_t req1_dma_reg[15];
	206	uint32_t xmt0_dma_reg[32];
	207	uint32_t xmt1_dma_reg[32];
	208	uint32_t xmt2_dma_reg[32];
	209	uint32_t xmt3_dma_reg[32];
	210	uint32_t xmt4_dma_reg[32];
	211	uint32_t xmt_data_dma_reg[16];
	212	uint32_t rcvt0_data_dma_reg[32];
	213	uint32_t rcvt1_data_dma_reg[32];
	214	uint32_t risc_gp_reg[128];
6d9b61ed AV	215	uint32_t lmc_reg[112];
	216	uint32_t fpm_hdw_reg[192];
	217	uint32_t fb_hdw_reg[176];
	218	uint32_t code_ram[0x2000];
	219	uint32_t ext_mem[1];
	220	};
a7a167bf	221
c3a2f0df AV	222	struct qla25xx_fw_dump {
c3a2f0df AV	223	uint32_t host_status;
b5836927 AV	224	uint32_t host_risc_reg[32];
b5836927 AV	225	uint32_t pcie_regs[4];
c3a2f0df AV	226	uint32_t host_reg[32];
	227	uint32_t shadow_reg[11];
	228	uint32_t risc_io_reg;
	229	uint16_t mailbox_reg[32];
	230	uint32_t xseq_gp_reg[128];
	231	uint32_t xseq_0_reg[48];
	232	uint32_t xseq_1_reg[16];
	233	uint32_t rseq_gp_reg[128];
	234	uint32_t rseq_0_reg[32];
	235	uint32_t rseq_1_reg[16];
	236	uint32_t rseq_2_reg[16];
	237	uint32_t aseq_gp_reg[128];
	238	uint32_t aseq_0_reg[32];
	239	uint32_t aseq_1_reg[16];
	240	uint32_t aseq_2_reg[16];
	241	uint32_t cmd_dma_reg[16];
	242	uint32_t req0_dma_reg[15];
	243	uint32_t resp0_dma_reg[15];
	244	uint32_t req1_dma_reg[15];
	245	uint32_t xmt0_dma_reg[32];
	246	uint32_t xmt1_dma_reg[32];
	247	uint32_t xmt2_dma_reg[32];
	248	uint32_t xmt3_dma_reg[32];
	249	uint32_t xmt4_dma_reg[32];
	250	uint32_t xmt_data_dma_reg[16];
	251	uint32_t rcvt0_data_dma_reg[32];
	252	uint32_t rcvt1_data_dma_reg[32];
	253	uint32_t risc_gp_reg[128];
	254	uint32_t lmc_reg[128];
	255	uint32_t fpm_hdw_reg[192];
	256	uint32_t fb_hdw_reg[192];
	257	uint32_t code_ram[0x2000];
	258	uint32_t ext_mem[1];
	259	};
	260
3a03eb79 AV	261	struct qla81xx_fw_dump {
	262	uint32_t host_status;
	263	uint32_t host_risc_reg[32];
	264	uint32_t pcie_regs[4];
	265	uint32_t host_reg[32];
	266	uint32_t shadow_reg[11];
	267	uint32_t risc_io_reg;
	268	uint16_t mailbox_reg[32];
	269	uint32_t xseq_gp_reg[128];
	270	uint32_t xseq_0_reg[48];
	271	uint32_t xseq_1_reg[16];
	272	uint32_t rseq_gp_reg[128];
	273	uint32_t rseq_0_reg[32];
	274	uint32_t rseq_1_reg[16];
	275	uint32_t rseq_2_reg[16];
	276	uint32_t aseq_gp_reg[128];
	277	uint32_t aseq_0_reg[32];
	278	uint32_t aseq_1_reg[16];
	279	uint32_t aseq_2_reg[16];
	280	uint32_t cmd_dma_reg[16];
	281	uint32_t req0_dma_reg[15];
	282	uint32_t resp0_dma_reg[15];
	283	uint32_t req1_dma_reg[15];
	284	uint32_t xmt0_dma_reg[32];
	285	uint32_t xmt1_dma_reg[32];
	286	uint32_t xmt2_dma_reg[32];
	287	uint32_t xmt3_dma_reg[32];
	288	uint32_t xmt4_dma_reg[32];
	289	uint32_t xmt_data_dma_reg[16];
	290	uint32_t rcvt0_data_dma_reg[32];
	291	uint32_t rcvt1_data_dma_reg[32];
	292	uint32_t risc_gp_reg[128];
	293	uint32_t lmc_reg[128];
	294	uint32_t fpm_hdw_reg[224];
	295	uint32_t fb_hdw_reg[208];
	296	uint32_t code_ram[0x2000];
	297	uint32_t ext_mem[1];
	298	};
	299
a7a167bf AV	300	#define EFT_NUM_BUFFERS 4
	301	#define EFT_BYTES_PER_BUFFER 0x4000
	302	#define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
	303
df613b96 AV	304	#define FCE_NUM_BUFFERS 64
	305	#define FCE_BYTES_PER_BUFFER 0x400
	306	#define FCE_SIZE ((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS))
	307	#define fce_calc_size(b) ((FCE_BYTES_PER_BUFFER) * (b))
	308
	309	struct qla2xxx_fce_chain {
	310	uint32_t type;
	311	uint32_t chain_size;
	312
	313	uint32_t size;
	314	uint32_t addr_l;
	315	uint32_t addr_h;
	316	uint32_t eregs[8];
	317	};
	318
73208dfd AC	319	struct qla2xxx_mq_chain {
	320	uint32_t type;
	321	uint32_t chain_size;
	322
	323	uint32_t count;
	324	uint32_t qregs[4 * QLA_MQ_SIZE];
	325	};
	326
df613b96 AV	327	#define DUMP_CHAIN_VARIANT 0x80000000
df613b96 AV	328	#define DUMP_CHAIN_FCE 0x7FFFFAF0
73208dfd	329	#define DUMP_CHAIN_MQ 0x7FFFFAF1
df613b96 AV	330	#define DUMP_CHAIN_LAST 0x80000000
df613b96 AV	331
a7a167bf AV	332	struct qla2xxx_fw_dump {
	333	uint8_t signature[4];
	334	uint32_t version;
	335
	336	uint32_t fw_major_version;
	337	uint32_t fw_minor_version;
	338	uint32_t fw_subminor_version;
	339	uint32_t fw_attributes;
	340
	341	uint32_t vendor;
	342	uint32_t device;
	343	uint32_t subsystem_vendor;
	344	uint32_t subsystem_device;
	345
	346	uint32_t fixed_size;
	347	uint32_t mem_size;
	348	uint32_t req_q_size;
	349	uint32_t rsp_q_size;
	350
	351	uint32_t eft_size;
	352	uint32_t eft_addr_l;
	353	uint32_t eft_addr_h;
	354
	355	uint32_t header_size;
	356
	357	union {
	358	struct qla2100_fw_dump isp21;
	359	struct qla2300_fw_dump isp23;
	360	struct qla24xx_fw_dump isp24;
c3a2f0df	361	struct qla25xx_fw_dump isp25;
3a03eb79	362	struct qla81xx_fw_dump isp81;
a7a167bf AV	363	} isp;
a7a167bf AV	364	};