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[SCSI] qla2xxx: Limit excessive DPC cycles.
[linux-2.6-block.git] / drivers / scsi / qla2xxx / qla_dbg.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
07e264b7 3 * Copyright (c) 2003-2011 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4 6 */
3ce8866c
SK		 7
8/*
9 * Table for showing the current message id in use for particular level
10 * Change this table for addition of log/debug messages.
e02587d7
AE		 11 * ----------------------------------------------------------------------
12 * | Level | Last Value Used | Holes |
13 * ----------------------------------------------------------------------
cfb0919c 14 * | Module Init and Probe | 0x0116 | 0xfa |
63154916 15 * | Mailbox commands | 0x112b | |
cfb0919c
CD		 16 * | Device Discovery | 0x2084 | |
17 * | Queue Command and IO tracing | 0x302f | 0x3008 |
e02587d7 18 * | DPC Thread | 0x401c | |
cfb0919c
CD		 19 * | Async Events | 0x5057 | 0x5052 |
20 * | Timer Routines | 0x6011 | 0x600e,0x600f |
21 * | User Space Interactions | 0x709e | |
22 * | Task Management | 0x803c | 0x8025-0x8026 |
23 * | | | 0x800b,0x8039 |
e02587d7
AE		 24 * | AER/EEH | 0x900f | |
25 * | Virtual Port | 0xa007 | |
c8f6544e 26 * | ISP82XX Specific | 0xb052 | |
e02587d7
AE		 27 * | MultiQ | 0xc00b | |
28 * | Misc | 0xd00b | |
29 * ----------------------------------------------------------------------
3ce8866c
SK		 30 */
31
1da177e4
LT		 32#include "qla_def.h"
33
34#include <linux/delay.h>
35
3ce8866c
SK		 36static uint32_t ql_dbg_offset = 0x800;
37
a7a167bf 38static inline void
7b867cf7 39qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
a7a167bf
AV		 40{
41 fw_dump->fw_major_version = htonl(ha->fw_major_version);
42 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
43 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
44 fw_dump->fw_attributes = htonl(ha->fw_attributes);
45
46 fw_dump->vendor = htonl(ha->pdev->vendor);
47 fw_dump->device = htonl(ha->pdev->device);
48 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
49 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
50}
51
52static inline void *
73208dfd 53qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
a7a167bf 54{
73208dfd
AC		 55 struct req_que *req = ha->req_q_map[0];
56 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf 57 /* Request queue. */
7b867cf7 58 memcpy(ptr, req->ring, req->length *
a7a167bf
AV		 59 sizeof(request_t));
60
61 /* Response queue. */
7b867cf7
AC		 62 ptr += req->length * sizeof(request_t);
63 memcpy(ptr, rsp->ring, rsp->length *
a7a167bf
AV		 64 sizeof(response_t));
65
7b867cf7 66 return ptr + (rsp->length * sizeof(response_t));
a7a167bf 67}
1da177e4 68
c3a2f0df 69static int
7b867cf7 70qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
c5722708 71 uint32_t ram_dwords, void **nxt)
c3a2f0df
AV		 72{
73 int rval;
c5722708
AV		 74 uint32_t cnt, stat, timer, dwords, idx;
75 uint16_t mb0;
c3a2f0df 76 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
c5722708
AV		 77 dma_addr_t dump_dma = ha->gid_list_dma;
78 uint32_t *dump = (uint32_t *)ha->gid_list;
c3a2f0df
AV		 79
80 rval = QLA_SUCCESS;
c5722708 81 mb0 = 0;
c3a2f0df 82
c5722708 83 WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
c3a2f0df
AV		 84 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
85
c5722708
AV		 86 dwords = GID_LIST_SIZE / 4;
87 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
88 cnt += dwords, addr += dwords) {
89 if (cnt + dwords > ram_dwords)
90 dwords = ram_dwords - cnt;
c3a2f0df 91
c5722708
AV		 92 WRT_REG_WORD(&reg->mailbox1, LSW(addr));
93 WRT_REG_WORD(&reg->mailbox8, MSW(addr));
c3a2f0df 94
c5722708
AV		 95 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
96 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
97 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
98 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
c3a2f0df 99
c5722708
AV		 100 WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
101 WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
c3a2f0df
AV		 102 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
103
104 for (timer = 6000000; timer; timer--) {
105 /* Check for pending interrupts. */
106 stat = RD_REG_DWORD(&reg->host_status);
107 if (stat & HSRX_RISC_INT) {
108 stat &= 0xff;
109
110 if (stat == 0x1 || stat == 0x2 ||
111 stat == 0x10 || stat == 0x11) {
112 set_bit(MBX_INTERRUPT,
113 &ha->mbx_cmd_flags);
114
c5722708 115 mb0 = RD_REG_WORD(&reg->mailbox0);
c3a2f0df
AV		 116
117 WRT_REG_DWORD(&reg->hccr,
118 HCCRX_CLR_RISC_INT);
119 RD_REG_DWORD(&reg->hccr);
120 break;
121 }
122
123 /* Clear this intr; it wasn't a mailbox intr */
124 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
125 RD_REG_DWORD(&reg->hccr);
126 }
127 udelay(5);
128 }
129
130 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
c5722708
AV		 131 rval = mb0 & MBS_MASK;
132 for (idx = 0; idx < dwords; idx++)
133 ram[cnt + idx] = swab32(dump[idx]);
c3a2f0df
AV		 134 } else {
135 rval = QLA_FUNCTION_FAILED;
136 }
137 }
138
c5722708 139 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
c3a2f0df
AV		 140 return rval;
141}
142
c5722708 143static int
7b867cf7 144qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
c5722708
AV		 145 uint32_t cram_size, void **nxt)
146{
147 int rval;
148
149 /* Code RAM. */
150 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
151 if (rval != QLA_SUCCESS)
152 return rval;
153
154 /* External Memory. */
155 return qla24xx_dump_ram(ha, 0x100000, *nxt,
156 ha->fw_memory_size - 0x100000 + 1, nxt);
157}
158
c81d04c9
AV		 159static uint32_t *
160qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
161 uint32_t count, uint32_t *buf)
162{
163 uint32_t __iomem *dmp_reg;
164
165 WRT_REG_DWORD(&reg->iobase_addr, iobase);
166 dmp_reg = &reg->iobase_window;
167 while (count--)
168 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
169
170 return buf;
171}
172
173static inline int
174qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
175{
176 int rval = QLA_SUCCESS;
177 uint32_t cnt;
178
c3b058af 179 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
aed10881
AV		 180 for (cnt = 30000;
181 ((RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED) == 0) &&
c3b058af
AV		 182 rval == QLA_SUCCESS; cnt--) {
183 if (cnt)
184 udelay(100);
185 else
186 rval = QLA_FUNCTION_TIMEOUT;
c81d04c9
AV		 187 }
188
189 return rval;
190}
191
192static int
7b867cf7 193qla24xx_soft_reset(struct qla_hw_data *ha)
c81d04c9
AV		 194{
195 int rval = QLA_SUCCESS;
196 uint32_t cnt;
197 uint16_t mb0, wd;
198 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
199
200 /* Reset RISC. */
201 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
202 for (cnt = 0; cnt < 30000; cnt++) {
203 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
204 break;
205
206 udelay(10);
207 }
208
209 WRT_REG_DWORD(&reg->ctrl_status,
210 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
211 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
212
213 udelay(100);
214 /* Wait for firmware to complete NVRAM accesses. */
215 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
216 for (cnt = 10000 ; cnt && mb0; cnt--) {
217 udelay(5);
218 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
219 barrier();
220 }
221
222 /* Wait for soft-reset to complete. */
223 for (cnt = 0; cnt < 30000; cnt++) {
224 if ((RD_REG_DWORD(&reg->ctrl_status) &
225 CSRX_ISP_SOFT_RESET) == 0)
226 break;
227
228 udelay(10);
229 }
230 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
231 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
232
233 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
234 rval == QLA_SUCCESS; cnt--) {
235 if (cnt)
236 udelay(100);
237 else
238 rval = QLA_FUNCTION_TIMEOUT;
239 }
240
241 return rval;
242}
243
c5722708 244static int
7b867cf7 245qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
e18e963b 246 uint32_t ram_words, void **nxt)
c5722708
AV		 247{
248 int rval;
249 uint32_t cnt, stat, timer, words, idx;
250 uint16_t mb0;
251 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
252 dma_addr_t dump_dma = ha->gid_list_dma;
253 uint16_t *dump = (uint16_t *)ha->gid_list;
254
255 rval = QLA_SUCCESS;
256 mb0 = 0;
257
258 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
259 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
260
261 words = GID_LIST_SIZE / 2;
262 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
263 cnt += words, addr += words) {
264 if (cnt + words > ram_words)
265 words = ram_words - cnt;
266
267 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
268 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
269
270 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
271 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
272 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
273 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
274
275 WRT_MAILBOX_REG(ha, reg, 4, words);
276 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
277
278 for (timer = 6000000; timer; timer--) {
279 /* Check for pending interrupts. */
280 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
281 if (stat & HSR_RISC_INT) {
282 stat &= 0xff;
283
284 if (stat == 0x1 || stat == 0x2) {
285 set_bit(MBX_INTERRUPT,
286 &ha->mbx_cmd_flags);
287
288 mb0 = RD_MAILBOX_REG(ha, reg, 0);
289
290 /* Release mailbox registers. */
291 WRT_REG_WORD(&reg->semaphore, 0);
292 WRT_REG_WORD(&reg->hccr,
293 HCCR_CLR_RISC_INT);
294 RD_REG_WORD(&reg->hccr);
295 break;
296 } else if (stat == 0x10 || stat == 0x11) {
297 set_bit(MBX_INTERRUPT,
298 &ha->mbx_cmd_flags);
299
300 mb0 = RD_MAILBOX_REG(ha, reg, 0);
301
302 WRT_REG_WORD(&reg->hccr,
303 HCCR_CLR_RISC_INT);
304 RD_REG_WORD(&reg->hccr);
305 break;
306 }
307
308 /* clear this intr; it wasn't a mailbox intr */
309 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
310 RD_REG_WORD(&reg->hccr);
311 }
312 udelay(5);
313 }
314
315 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
316 rval = mb0 & MBS_MASK;
317 for (idx = 0; idx < words; idx++)
318 ram[cnt + idx] = swab16(dump[idx]);
319 } else {
320 rval = QLA_FUNCTION_FAILED;
321 }
322 }
323
324 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
325 return rval;
326}
327
c81d04c9
AV		 328static inline void
329qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
330 uint16_t *buf)
331{
332 uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
333
334 while (count--)
335 *buf++ = htons(RD_REG_WORD(dmp_reg++));
336}
337
bb99de67
AV		 338static inline void *
339qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
340{
341 if (!ha->eft)
342 return ptr;
343
344 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
345 return ptr + ntohl(ha->fw_dump->eft_size);
346}
347
348static inline void *
349qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
350{
351 uint32_t cnt;
352 uint32_t *iter_reg;
353 struct qla2xxx_fce_chain *fcec = ptr;
354
355 if (!ha->fce)
356 return ptr;
357
358 *last_chain = &fcec->type;
359 fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
360 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
361 fce_calc_size(ha->fce_bufs));
362 fcec->size = htonl(fce_calc_size(ha->fce_bufs));
363 fcec->addr_l = htonl(LSD(ha->fce_dma));
364 fcec->addr_h = htonl(MSD(ha->fce_dma));
365
366 iter_reg = fcec->eregs;
367 for (cnt = 0; cnt < 8; cnt++)
368 *iter_reg++ = htonl(ha->fce_mb[cnt]);
369
370 memcpy(iter_reg, ha->fce, ntohl(fcec->size));
371
372 return iter_reg;
373}
374
d63ab533
AV		 375static inline void *
376qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
377{
378 uint32_t cnt, que_idx;
2afa19a9 379 uint8_t que_cnt;
d63ab533
AV		 380 struct qla2xxx_mq_chain *mq = ptr;
381 struct device_reg_25xxmq __iomem *reg;
382
383 if (!ha->mqenable)
384 return ptr;
385
386 mq = ptr;
387 *last_chain = &mq->type;
388 mq->type = __constant_htonl(DUMP_CHAIN_MQ);
389 mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
390
2afa19a9
AC		 391 que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
392 ha->max_req_queues : ha->max_rsp_queues;
d63ab533
AV		 393 mq->count = htonl(que_cnt);
394 for (cnt = 0; cnt < que_cnt; cnt++) {
395 reg = (struct device_reg_25xxmq *) ((void *)
396 ha->mqiobase + cnt * QLA_QUE_PAGE);
397 que_idx = cnt * 4;
398 mq->qregs[que_idx] = htonl(RD_REG_DWORD(&reg->req_q_in));
399 mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(&reg->req_q_out));
400 mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(&reg->rsp_q_in));
401 mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(&reg->rsp_q_out));
402 }
403
404 return ptr + sizeof(struct qla2xxx_mq_chain);
405}
406
08de2844 407void
3420d36c
AV		 408qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
409{
410 struct qla_hw_data *ha = vha->hw;
411
412 if (rval != QLA_SUCCESS) {
7c3df132
SK		 413 ql_log(ql_log_warn, vha, 0xd000,
414 "Failed to dump firmware (%x).\n", rval);
3420d36c
AV		 415 ha->fw_dumped = 0;
416 } else {
7c3df132 417 ql_log(ql_log_info, vha, 0xd001,
3420d36c
AV		 418 "Firmware dump saved to temp buffer (%ld/%p).\n",
419 vha->host_no, ha->fw_dump);
420 ha->fw_dumped = 1;
421 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
422 }
423}
424
1da177e4
LT		 425/**
426 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
427 * @ha: HA context
428 * @hardware_locked: Called with the hardware_lock
429 */
430void
7b867cf7 431qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1da177e4
LT		 432{
433 int rval;
c5722708 434 uint32_t cnt;
7b867cf7 435 struct qla_hw_data *ha = vha->hw;
3d71644c 436 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 437 uint16_t __iomem *dmp_reg;
438 unsigned long flags;
439 struct qla2300_fw_dump *fw;
c5722708 440 void *nxt;
73208dfd 441 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 442
1da177e4
LT		 443 flags = 0;
444
445 if (!hardware_locked)
446 spin_lock_irqsave(&ha->hardware_lock, flags);
447
d4e3e04d 448 if (!ha->fw_dump) {
7c3df132
SK		 449 ql_log(ql_log_warn, vha, 0xd002,
450 "No buffer available for dump.\n");
1da177e4
LT		 451 goto qla2300_fw_dump_failed;
452 }
453
d4e3e04d 454 if (ha->fw_dumped) {
7c3df132
SK		 455 ql_log(ql_log_warn, vha, 0xd003,
456 "Firmware has been previously dumped (%p) "
457 "-- ignoring request.\n",
458 ha->fw_dump);
1da177e4
LT		 459 goto qla2300_fw_dump_failed;
460 }
a7a167bf
AV		 461 fw = &ha->fw_dump->isp.isp23;
462 qla2xxx_prep_dump(ha, ha->fw_dump);
1da177e4
LT		 463
464 rval = QLA_SUCCESS;
a7a167bf 465 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
1da177e4
LT		 466
467 /* Pause RISC. */
fa2a1ce5 468 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 469 if (IS_QLA2300(ha)) {
470 for (cnt = 30000;
471 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
472 rval == QLA_SUCCESS; cnt--) {
473 if (cnt)
474 udelay(100);
475 else
476 rval = QLA_FUNCTION_TIMEOUT;
477 }
478 } else {
479 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
480 udelay(10);
481 }
482
483 if (rval == QLA_SUCCESS) {
c81d04c9 484 dmp_reg = &reg->flash_address;
fa2a1ce5 485 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
a7a167bf 486 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 487
c81d04c9 488 dmp_reg = &reg->u.isp2300.req_q_in;
fa2a1ce5 489 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
a7a167bf 490 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 491
c81d04c9 492 dmp_reg = &reg->u.isp2300.mailbox0;
fa2a1ce5 493 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
a7a167bf 494 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 495
496 WRT_REG_WORD(&reg->ctrl_status, 0x40);
c81d04c9 497 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
1da177e4
LT		 498
499 WRT_REG_WORD(&reg->ctrl_status, 0x50);
c81d04c9 500 qla2xxx_read_window(reg, 48, fw->dma_reg);
1da177e4
LT		 501
502 WRT_REG_WORD(&reg->ctrl_status, 0x00);
c81d04c9 503 dmp_reg = &reg->risc_hw;
fa2a1ce5 504 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
a7a167bf 505 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 506
fa2a1ce5 507 WRT_REG_WORD(&reg->pcr, 0x2000);
c81d04c9 508 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
1da177e4 509
fa2a1ce5 510 WRT_REG_WORD(&reg->pcr, 0x2200);
c81d04c9 511 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
1da177e4 512
fa2a1ce5 513 WRT_REG_WORD(&reg->pcr, 0x2400);
c81d04c9 514 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
1da177e4 515
fa2a1ce5 516 WRT_REG_WORD(&reg->pcr, 0x2600);
c81d04c9 517 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
1da177e4 518
fa2a1ce5 519 WRT_REG_WORD(&reg->pcr, 0x2800);
c81d04c9 520 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
1da177e4 521
fa2a1ce5 522 WRT_REG_WORD(&reg->pcr, 0x2A00);
c81d04c9 523 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
1da177e4 524
fa2a1ce5 525 WRT_REG_WORD(&reg->pcr, 0x2C00);
c81d04c9 526 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
1da177e4 527
fa2a1ce5 528 WRT_REG_WORD(&reg->pcr, 0x2E00);
c81d04c9 529 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
1da177e4 530
fa2a1ce5 531 WRT_REG_WORD(&reg->ctrl_status, 0x10);
c81d04c9 532 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
1da177e4 533
fa2a1ce5 534 WRT_REG_WORD(&reg->ctrl_status, 0x20);
c81d04c9 535 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
1da177e4 536
fa2a1ce5 537 WRT_REG_WORD(&reg->ctrl_status, 0x30);
c81d04c9 538 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
1da177e4
LT		 539
540 /* Reset RISC. */
541 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
542 for (cnt = 0; cnt < 30000; cnt++) {
543 if ((RD_REG_WORD(&reg->ctrl_status) &
544 CSR_ISP_SOFT_RESET) == 0)
545 break;
546
547 udelay(10);
548 }
549 }
550
551 if (!IS_QLA2300(ha)) {
552 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
553 rval == QLA_SUCCESS; cnt--) {
554 if (cnt)
555 udelay(100);
556 else
557 rval = QLA_FUNCTION_TIMEOUT;
558 }
559 }
560
c5722708
AV		 561 /* Get RISC SRAM. */
562 if (rval == QLA_SUCCESS)
563 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
564 sizeof(fw->risc_ram) / 2, &nxt);
1da177e4 565
c5722708
AV		 566 /* Get stack SRAM. */
567 if (rval == QLA_SUCCESS)
568 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
569 sizeof(fw->stack_ram) / 2, &nxt);
1da177e4 570
c5722708
AV		 571 /* Get data SRAM. */
572 if (rval == QLA_SUCCESS)
573 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
574 ha->fw_memory_size - 0x11000 + 1, &nxt);
1da177e4 575
a7a167bf 576 if (rval == QLA_SUCCESS)
73208dfd 577 qla2xxx_copy_queues(ha, nxt);
a7a167bf 578
3420d36c 579 qla2xxx_dump_post_process(base_vha, rval);
1da177e4
LT		 580
581qla2300_fw_dump_failed:
582 if (!hardware_locked)
583 spin_unlock_irqrestore(&ha->hardware_lock, flags);
584}
585
1da177e4
LT		 586/**
587 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
588 * @ha: HA context
589 * @hardware_locked: Called with the hardware_lock
590 */
591void
7b867cf7 592qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1da177e4
LT		 593{
594 int rval;
595 uint32_t cnt, timer;
596 uint16_t risc_address;
597 uint16_t mb0, mb2;
7b867cf7 598 struct qla_hw_data *ha = vha->hw;
3d71644c 599 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 600 uint16_t __iomem *dmp_reg;
601 unsigned long flags;
602 struct qla2100_fw_dump *fw;
73208dfd 603 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 604
605 risc_address = 0;
606 mb0 = mb2 = 0;
607 flags = 0;
608
609 if (!hardware_locked)
610 spin_lock_irqsave(&ha->hardware_lock, flags);
611
d4e3e04d 612 if (!ha->fw_dump) {
7c3df132
SK		 613 ql_log(ql_log_warn, vha, 0xd004,
614 "No buffer available for dump.\n");
1da177e4
LT		 615 goto qla2100_fw_dump_failed;
616 }
617
d4e3e04d 618 if (ha->fw_dumped) {
7c3df132
SK		 619 ql_log(ql_log_warn, vha, 0xd005,
620 "Firmware has been previously dumped (%p) "
621 "-- ignoring request.\n",
622 ha->fw_dump);
1da177e4
LT		 623 goto qla2100_fw_dump_failed;
624 }
a7a167bf
AV		 625 fw = &ha->fw_dump->isp.isp21;
626 qla2xxx_prep_dump(ha, ha->fw_dump);
1da177e4
LT		 627
628 rval = QLA_SUCCESS;
a7a167bf 629 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
1da177e4
LT		 630
631 /* Pause RISC. */
fa2a1ce5 632 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 633 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
634 rval == QLA_SUCCESS; cnt--) {
635 if (cnt)
636 udelay(100);
637 else
638 rval = QLA_FUNCTION_TIMEOUT;
639 }
640 if (rval == QLA_SUCCESS) {
c81d04c9 641 dmp_reg = &reg->flash_address;
fa2a1ce5 642 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
a7a167bf 643 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 644
c81d04c9 645 dmp_reg = &reg->u.isp2100.mailbox0;
1da177e4 646 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
c81d04c9
AV		 647 if (cnt == 8)
648 dmp_reg = &reg->u_end.isp2200.mailbox8;
649
a7a167bf 650 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 651 }
652
c81d04c9 653 dmp_reg = &reg->u.isp2100.unused_2[0];
fa2a1ce5 654 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
a7a167bf 655 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4
LT		 656
657 WRT_REG_WORD(&reg->ctrl_status, 0x00);
c81d04c9 658 dmp_reg = &reg->risc_hw;
fa2a1ce5 659 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
a7a167bf 660 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
1da177e4 661
fa2a1ce5 662 WRT_REG_WORD(&reg->pcr, 0x2000);
c81d04c9 663 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
1da177e4 664
fa2a1ce5 665 WRT_REG_WORD(&reg->pcr, 0x2100);
c81d04c9 666 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
1da177e4 667
fa2a1ce5 668 WRT_REG_WORD(&reg->pcr, 0x2200);
c81d04c9 669 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
1da177e4 670
fa2a1ce5 671 WRT_REG_WORD(&reg->pcr, 0x2300);
c81d04c9 672 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
1da177e4 673
fa2a1ce5 674 WRT_REG_WORD(&reg->pcr, 0x2400);
c81d04c9 675 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
1da177e4 676
fa2a1ce5 677 WRT_REG_WORD(&reg->pcr, 0x2500);
c81d04c9 678 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
1da177e4 679
fa2a1ce5 680 WRT_REG_WORD(&reg->pcr, 0x2600);
c81d04c9 681 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
1da177e4 682
fa2a1ce5 683 WRT_REG_WORD(&reg->pcr, 0x2700);
c81d04c9 684 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
1da177e4 685
fa2a1ce5 686 WRT_REG_WORD(&reg->ctrl_status, 0x10);
c81d04c9 687 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
1da177e4 688
fa2a1ce5 689 WRT_REG_WORD(&reg->ctrl_status, 0x20);
c81d04c9 690 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
1da177e4 691
fa2a1ce5 692 WRT_REG_WORD(&reg->ctrl_status, 0x30);
c81d04c9 693 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
1da177e4
LT		 694
695 /* Reset the ISP. */
696 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
697 }
698
699 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
700 rval == QLA_SUCCESS; cnt--) {
701 if (cnt)
702 udelay(100);
703 else
704 rval = QLA_FUNCTION_TIMEOUT;
705 }
706
707 /* Pause RISC. */
708 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
709 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
710
fa2a1ce5 711 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 712 for (cnt = 30000;
713 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
714 rval == QLA_SUCCESS; cnt--) {
715 if (cnt)
716 udelay(100);
717 else
718 rval = QLA_FUNCTION_TIMEOUT;
719 }
720 if (rval == QLA_SUCCESS) {
721 /* Set memory configuration and timing. */
722 if (IS_QLA2100(ha))
723 WRT_REG_WORD(&reg->mctr, 0xf1);
724 else
725 WRT_REG_WORD(&reg->mctr, 0xf2);
726 RD_REG_WORD(&reg->mctr); /* PCI Posting. */
727
728 /* Release RISC. */
729 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
730 }
731 }
732
733 if (rval == QLA_SUCCESS) {
734 /* Get RISC SRAM. */
735 risc_address = 0x1000;
736 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
737 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
738 }
739 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
740 cnt++, risc_address++) {
741 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
742 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
743
744 for (timer = 6000000; timer != 0; timer--) {
745 /* Check for pending interrupts. */
746 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
747 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
748 set_bit(MBX_INTERRUPT,
749 &ha->mbx_cmd_flags);
750
751 mb0 = RD_MAILBOX_REG(ha, reg, 0);
752 mb2 = RD_MAILBOX_REG(ha, reg, 2);
753
754 WRT_REG_WORD(&reg->semaphore, 0);
755 WRT_REG_WORD(&reg->hccr,
756 HCCR_CLR_RISC_INT);
757 RD_REG_WORD(&reg->hccr);
758 break;
759 }
760 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
761 RD_REG_WORD(&reg->hccr);
762 }
763 udelay(5);
764 }
765
766 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
767 rval = mb0 & MBS_MASK;
a7a167bf 768 fw->risc_ram[cnt] = htons(mb2);
1da177e4
LT		 769 } else {
770 rval = QLA_FUNCTION_FAILED;
771 }
772 }
773
a7a167bf 774 if (rval == QLA_SUCCESS)
73208dfd 775 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
a7a167bf 776
3420d36c 777 qla2xxx_dump_post_process(base_vha, rval);
1da177e4
LT		 778
779qla2100_fw_dump_failed:
780 if (!hardware_locked)
781 spin_unlock_irqrestore(&ha->hardware_lock, flags);
782}
783
6d9b61ed 784void
7b867cf7 785qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
6d9b61ed
AV		 786{
787 int rval;
c3a2f0df 788 uint32_t cnt;
6d9b61ed 789 uint32_t risc_address;
7b867cf7 790 struct qla_hw_data *ha = vha->hw;
6d9b61ed
AV		 791 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
792 uint32_t __iomem *dmp_reg;
793 uint32_t *iter_reg;
794 uint16_t __iomem *mbx_reg;
795 unsigned long flags;
796 struct qla24xx_fw_dump *fw;
797 uint32_t ext_mem_cnt;
c3a2f0df 798 void *nxt;
73208dfd 799 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6d9b61ed 800
a9083016
GM		 801 if (IS_QLA82XX(ha))
802 return;
803
6d9b61ed 804 risc_address = ext_mem_cnt = 0;
6d9b61ed
AV		 805 flags = 0;
806
807 if (!hardware_locked)
808 spin_lock_irqsave(&ha->hardware_lock, flags);
809
d4e3e04d 810 if (!ha->fw_dump) {
7c3df132
SK		 811 ql_log(ql_log_warn, vha, 0xd006,
812 "No buffer available for dump.\n");
6d9b61ed
AV		 813 goto qla24xx_fw_dump_failed;
814 }
815
816 if (ha->fw_dumped) {
7c3df132
SK		 817 ql_log(ql_log_warn, vha, 0xd007,
818 "Firmware has been previously dumped (%p) "
819 "-- ignoring request.\n",
820 ha->fw_dump);
6d9b61ed
AV		 821 goto qla24xx_fw_dump_failed;
822 }
a7a167bf
AV		 823 fw = &ha->fw_dump->isp.isp24;
824 qla2xxx_prep_dump(ha, ha->fw_dump);
6d9b61ed 825
a7a167bf 826 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
6d9b61ed
AV		 827
828 /* Pause RISC. */
c81d04c9
AV		 829 rval = qla24xx_pause_risc(reg);
830 if (rval != QLA_SUCCESS)
831 goto qla24xx_fw_dump_failed_0;
832
833 /* Host interface registers. */
834 dmp_reg = &reg->flash_addr;
835 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
836 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
837
838 /* Disable interrupts. */
839 WRT_REG_DWORD(&reg->ictrl, 0);
840 RD_REG_DWORD(&reg->ictrl);
841
842 /* Shadow registers. */
843 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
844 RD_REG_DWORD(&reg->iobase_addr);
845 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
846 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
847
848 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
849 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
850
851 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
852 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
853
854 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
855 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
856
857 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
858 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
859
860 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
861 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
862
863 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
864 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
865
866 /* Mailbox registers. */
867 mbx_reg = &reg->mailbox0;
868 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
869 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
870
871 /* Transfer sequence registers. */
872 iter_reg = fw->xseq_gp_reg;
873 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
874 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
875 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
876 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
877 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
878 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
879 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
880 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
881
882 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
883 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
884
885 /* Receive sequence registers. */
886 iter_reg = fw->rseq_gp_reg;
887 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
888 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
889 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
890 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
891 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
892 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
893 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
894 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
895
896 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
897 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
898 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
899
900 /* Command DMA registers. */
901 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
902
903 /* Queues. */
904 iter_reg = fw->req0_dma_reg;
905 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
906 dmp_reg = &reg->iobase_q;
907 for (cnt = 0; cnt < 7; cnt++)
908 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
909
910 iter_reg = fw->resp0_dma_reg;
911 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
912 dmp_reg = &reg->iobase_q;
913 for (cnt = 0; cnt < 7; cnt++)
914 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
915
916 iter_reg = fw->req1_dma_reg;
917 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
918 dmp_reg = &reg->iobase_q;
919 for (cnt = 0; cnt < 7; cnt++)
920 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
921
922 /* Transmit DMA registers. */
923 iter_reg = fw->xmt0_dma_reg;
924 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
925 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
926
927 iter_reg = fw->xmt1_dma_reg;
928 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
929 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
930
931 iter_reg = fw->xmt2_dma_reg;
932 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
933 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
934
935 iter_reg = fw->xmt3_dma_reg;
936 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
937 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
938
939 iter_reg = fw->xmt4_dma_reg;
940 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
941 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
942
943 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
944
945 /* Receive DMA registers. */
946 iter_reg = fw->rcvt0_data_dma_reg;
947 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
948 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
949
950 iter_reg = fw->rcvt1_data_dma_reg;
951 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
952 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
953
954 /* RISC registers. */
955 iter_reg = fw->risc_gp_reg;
956 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
957 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
958 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
959 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
960 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
961 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
962 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
963 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
964
965 /* Local memory controller registers. */
966 iter_reg = fw->lmc_reg;
967 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
968 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
969 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
970 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
971 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
972 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
973 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
974
975 /* Fibre Protocol Module registers. */
976 iter_reg = fw->fpm_hdw_reg;
977 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
978 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
979 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
980 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
981 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
982 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
983 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
984 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
985 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
986 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
987 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
988 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
989
990 /* Frame Buffer registers. */
991 iter_reg = fw->fb_hdw_reg;
992 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
993 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
994 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
995 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
996 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
997 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
998 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
999 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1000 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1001 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1002 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1003
1004 rval = qla24xx_soft_reset(ha);
1005 if (rval != QLA_SUCCESS)
1006 goto qla24xx_fw_dump_failed_0;
1007
1008 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
c5722708 1009 &nxt);
c81d04c9
AV		 1010 if (rval != QLA_SUCCESS)
1011 goto qla24xx_fw_dump_failed_0;
1012
73208dfd 1013 nxt = qla2xxx_copy_queues(ha, nxt);
bb99de67
AV		 1014
1015 qla24xx_copy_eft(ha, nxt);
c81d04c9
AV		 1016
1017qla24xx_fw_dump_failed_0:
3420d36c 1018 qla2xxx_dump_post_process(base_vha, rval);
6d9b61ed 1019
c3a2f0df
AV		 1020qla24xx_fw_dump_failed:
1021 if (!hardware_locked)
1022 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1023}
6d9b61ed 1024
c3a2f0df 1025void
7b867cf7 1026qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
c3a2f0df
AV		 1027{
1028 int rval;
1029 uint32_t cnt;
1030 uint32_t risc_address;
7b867cf7 1031 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1032 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1033 uint32_t __iomem *dmp_reg;
1034 uint32_t *iter_reg;
1035 uint16_t __iomem *mbx_reg;
1036 unsigned long flags;
1037 struct qla25xx_fw_dump *fw;
1038 uint32_t ext_mem_cnt;
d63ab533 1039 void *nxt, *nxt_chain;
bb99de67 1040 uint32_t *last_chain = NULL;
73208dfd 1041 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6d9b61ed 1042
c3a2f0df
AV		 1043 risc_address = ext_mem_cnt = 0;
1044 flags = 0;
6d9b61ed 1045
c3a2f0df
AV		 1046 if (!hardware_locked)
1047 spin_lock_irqsave(&ha->hardware_lock, flags);
6d9b61ed 1048
c3a2f0df 1049 if (!ha->fw_dump) {
7c3df132
SK		 1050 ql_log(ql_log_warn, vha, 0xd008,
1051 "No buffer available for dump.\n");
c3a2f0df
AV		 1052 goto qla25xx_fw_dump_failed;
1053 }
6d9b61ed 1054
c3a2f0df 1055 if (ha->fw_dumped) {
7c3df132
SK		 1056 ql_log(ql_log_warn, vha, 0xd009,
1057 "Firmware has been previously dumped (%p) "
1058 "-- ignoring request.\n",
1059 ha->fw_dump);
c3a2f0df
AV		 1060 goto qla25xx_fw_dump_failed;
1061 }
1062 fw = &ha->fw_dump->isp.isp25;
1063 qla2xxx_prep_dump(ha, ha->fw_dump);
b5836927 1064 ha->fw_dump->version = __constant_htonl(2);
6d9b61ed 1065
c3a2f0df 1066 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
6d9b61ed 1067
c3a2f0df 1068 /* Pause RISC. */
c81d04c9
AV		 1069 rval = qla24xx_pause_risc(reg);
1070 if (rval != QLA_SUCCESS)
1071 goto qla25xx_fw_dump_failed_0;
1072
b5836927
AV		 1073 /* Host/Risc registers. */
1074 iter_reg = fw->host_risc_reg;
1075 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1076 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1077
1078 /* PCIe registers. */
1079 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1080 RD_REG_DWORD(&reg->iobase_addr);
1081 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1082 dmp_reg = &reg->iobase_c4;
1083 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1084 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1085 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1086 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
73208dfd 1087
b5836927
AV		 1088 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1089 RD_REG_DWORD(&reg->iobase_window);
1090
c81d04c9
AV		 1091 /* Host interface registers. */
1092 dmp_reg = &reg->flash_addr;
1093 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1094 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1095
1096 /* Disable interrupts. */
1097 WRT_REG_DWORD(&reg->ictrl, 0);
1098 RD_REG_DWORD(&reg->ictrl);
1099
1100 /* Shadow registers. */
1101 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1102 RD_REG_DWORD(&reg->iobase_addr);
1103 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1104 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1105
1106 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1107 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1108
1109 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1110 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1111
1112 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1113 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1114
1115 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1116 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1117
1118 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1119 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1120
1121 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1122 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1123
1124 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1125 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1126
1127 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1128 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1129
1130 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1131 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1132
1133 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1134 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1135
1136 /* RISC I/O register. */
1137 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1138 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1139
1140 /* Mailbox registers. */
1141 mbx_reg = &reg->mailbox0;
1142 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1143 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1144
1145 /* Transfer sequence registers. */
1146 iter_reg = fw->xseq_gp_reg;
1147 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1148 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1149 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1150 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1151 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1152 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1153 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1154 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1155
1156 iter_reg = fw->xseq_0_reg;
1157 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1158 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1159 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1160
1161 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1162
1163 /* Receive sequence registers. */
1164 iter_reg = fw->rseq_gp_reg;
1165 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1166 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1167 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1168 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1169 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1170 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1171 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1172 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1173
1174 iter_reg = fw->rseq_0_reg;
1175 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1176 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1177
1178 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1179 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1180
1181 /* Auxiliary sequence registers. */
1182 iter_reg = fw->aseq_gp_reg;
1183 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1184 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1185 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1186 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1187 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1188 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1189 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1190 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1191
1192 iter_reg = fw->aseq_0_reg;
1193 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1194 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1195
1196 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1197 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1198
1199 /* Command DMA registers. */
1200 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1201
1202 /* Queues. */
1203 iter_reg = fw->req0_dma_reg;
1204 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1205 dmp_reg = &reg->iobase_q;
1206 for (cnt = 0; cnt < 7; cnt++)
1207 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1208
1209 iter_reg = fw->resp0_dma_reg;
1210 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1211 dmp_reg = &reg->iobase_q;
1212 for (cnt = 0; cnt < 7; cnt++)
1213 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1214
1215 iter_reg = fw->req1_dma_reg;
1216 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1217 dmp_reg = &reg->iobase_q;
1218 for (cnt = 0; cnt < 7; cnt++)
1219 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1220
1221 /* Transmit DMA registers. */
1222 iter_reg = fw->xmt0_dma_reg;
1223 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1224 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1225
1226 iter_reg = fw->xmt1_dma_reg;
1227 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1228 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1229
1230 iter_reg = fw->xmt2_dma_reg;
1231 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1232 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1233
1234 iter_reg = fw->xmt3_dma_reg;
1235 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1236 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1237
1238 iter_reg = fw->xmt4_dma_reg;
1239 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1240 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1241
1242 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1243
1244 /* Receive DMA registers. */
1245 iter_reg = fw->rcvt0_data_dma_reg;
1246 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1247 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1248
1249 iter_reg = fw->rcvt1_data_dma_reg;
1250 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1251 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1252
1253 /* RISC registers. */
1254 iter_reg = fw->risc_gp_reg;
1255 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1256 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1257 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1258 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1259 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1260 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1261 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1262 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1263
1264 /* Local memory controller registers. */
1265 iter_reg = fw->lmc_reg;
1266 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1267 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1268 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1269 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1270 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1271 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1272 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1273 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1274
1275 /* Fibre Protocol Module registers. */
1276 iter_reg = fw->fpm_hdw_reg;
1277 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1278 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1279 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1280 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1281 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1282 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1283 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1284 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1285 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1286 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1287 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1288 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1289
1290 /* Frame Buffer registers. */
1291 iter_reg = fw->fb_hdw_reg;
1292 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1293 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1294 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1295 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1296 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1297 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1298 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1299 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1300 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1301 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1302 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1303 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1304
d63ab533
AV		 1305 /* Multi queue registers */
1306 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1307 &last_chain);
1308
c81d04c9
AV		 1309 rval = qla24xx_soft_reset(ha);
1310 if (rval != QLA_SUCCESS)
1311 goto qla25xx_fw_dump_failed_0;
1312
1313 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
c5722708 1314 &nxt);
c81d04c9
AV		 1315 if (rval != QLA_SUCCESS)
1316 goto qla25xx_fw_dump_failed_0;
1317
73208dfd 1318 nxt = qla2xxx_copy_queues(ha, nxt);
c81d04c9 1319
bb99de67 1320 nxt = qla24xx_copy_eft(ha, nxt);
df613b96 1321
d63ab533
AV		 1322 /* Chain entries -- started with MQ. */
1323 qla25xx_copy_fce(ha, nxt_chain, &last_chain);
bb99de67
AV		 1324 if (last_chain) {
1325 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1326 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1327 }
df613b96 1328
c81d04c9 1329qla25xx_fw_dump_failed_0:
3420d36c 1330 qla2xxx_dump_post_process(base_vha, rval);
6d9b61ed 1331
c3a2f0df 1332qla25xx_fw_dump_failed:
6d9b61ed
AV		 1333 if (!hardware_locked)
1334 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1335}
3a03eb79
AV		 1336
1337void
1338qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1339{
1340 int rval;
1341 uint32_t cnt;
1342 uint32_t risc_address;
1343 struct qla_hw_data *ha = vha->hw;
1344 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1345 uint32_t __iomem *dmp_reg;
1346 uint32_t *iter_reg;
1347 uint16_t __iomem *mbx_reg;
1348 unsigned long flags;
1349 struct qla81xx_fw_dump *fw;
1350 uint32_t ext_mem_cnt;
1351 void *nxt, *nxt_chain;
1352 uint32_t *last_chain = NULL;
1353 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1354
1355 risc_address = ext_mem_cnt = 0;
1356 flags = 0;
1357
1358 if (!hardware_locked)
1359 spin_lock_irqsave(&ha->hardware_lock, flags);
1360
1361 if (!ha->fw_dump) {
7c3df132
SK		 1362 ql_log(ql_log_warn, vha, 0xd00a,
1363 "No buffer available for dump.\n");
3a03eb79
AV		 1364 goto qla81xx_fw_dump_failed;
1365 }
1366
1367 if (ha->fw_dumped) {
7c3df132
SK		 1368 ql_log(ql_log_warn, vha, 0xd00b,
1369 "Firmware has been previously dumped (%p) "
1370 "-- ignoring request.\n",
1371 ha->fw_dump);
3a03eb79
AV		 1372 goto qla81xx_fw_dump_failed;
1373 }
1374 fw = &ha->fw_dump->isp.isp81;
1375 qla2xxx_prep_dump(ha, ha->fw_dump);
1376
1377 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1378
1379 /* Pause RISC. */
1380 rval = qla24xx_pause_risc(reg);
1381 if (rval != QLA_SUCCESS)
1382 goto qla81xx_fw_dump_failed_0;
1383
1384 /* Host/Risc registers. */
1385 iter_reg = fw->host_risc_reg;
1386 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1387 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1388
1389 /* PCIe registers. */
1390 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1391 RD_REG_DWORD(&reg->iobase_addr);
1392 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1393 dmp_reg = &reg->iobase_c4;
1394 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1395 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1396 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1397 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1398
1399 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1400 RD_REG_DWORD(&reg->iobase_window);
1401
1402 /* Host interface registers. */
1403 dmp_reg = &reg->flash_addr;
1404 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1405 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1406
1407 /* Disable interrupts. */
1408 WRT_REG_DWORD(&reg->ictrl, 0);
1409 RD_REG_DWORD(&reg->ictrl);
1410
1411 /* Shadow registers. */
1412 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1413 RD_REG_DWORD(&reg->iobase_addr);
1414 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1415 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1416
1417 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1418 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1419
1420 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1421 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1422
1423 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1424 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1425
1426 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1427 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1428
1429 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1430 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1431
1432 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1433 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1434
1435 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1436 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1437
1438 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1439 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1440
1441 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1442 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1443
1444 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1445 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1446
1447 /* RISC I/O register. */
1448 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1449 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1450
1451 /* Mailbox registers. */
1452 mbx_reg = &reg->mailbox0;
1453 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1454 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1455
1456 /* Transfer sequence registers. */
1457 iter_reg = fw->xseq_gp_reg;
1458 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1459 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1460 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1461 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1462 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1463 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1464 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1465 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1466
1467 iter_reg = fw->xseq_0_reg;
1468 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1469 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1470 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1471
1472 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1473
1474 /* Receive sequence registers. */
1475 iter_reg = fw->rseq_gp_reg;
1476 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1477 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1478 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1479 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1480 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1481 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1482 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1483 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1484
1485 iter_reg = fw->rseq_0_reg;
1486 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1487 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1488
1489 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1490 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1491
1492 /* Auxiliary sequence registers. */
1493 iter_reg = fw->aseq_gp_reg;
1494 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1495 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1496 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1497 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1498 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1499 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1500 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1501 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1502
1503 iter_reg = fw->aseq_0_reg;
1504 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1505 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1506
1507 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1508 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1509
1510 /* Command DMA registers. */
1511 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1512
1513 /* Queues. */
1514 iter_reg = fw->req0_dma_reg;
1515 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1516 dmp_reg = &reg->iobase_q;
1517 for (cnt = 0; cnt < 7; cnt++)
1518 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1519
1520 iter_reg = fw->resp0_dma_reg;
1521 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1522 dmp_reg = &reg->iobase_q;
1523 for (cnt = 0; cnt < 7; cnt++)
1524 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1525
1526 iter_reg = fw->req1_dma_reg;
1527 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1528 dmp_reg = &reg->iobase_q;
1529 for (cnt = 0; cnt < 7; cnt++)
1530 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1531
1532 /* Transmit DMA registers. */
1533 iter_reg = fw->xmt0_dma_reg;
1534 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1535 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1536
1537 iter_reg = fw->xmt1_dma_reg;
1538 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1539 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1540
1541 iter_reg = fw->xmt2_dma_reg;
1542 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1543 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1544
1545 iter_reg = fw->xmt3_dma_reg;
1546 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1547 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1548
1549 iter_reg = fw->xmt4_dma_reg;
1550 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1551 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1552
1553 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1554
1555 /* Receive DMA registers. */
1556 iter_reg = fw->rcvt0_data_dma_reg;
1557 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1558 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1559
1560 iter_reg = fw->rcvt1_data_dma_reg;
1561 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1562 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1563
1564 /* RISC registers. */
1565 iter_reg = fw->risc_gp_reg;
1566 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1567 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1568 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1569 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1570 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1571 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1572 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1573 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1574
1575 /* Local memory controller registers. */
1576 iter_reg = fw->lmc_reg;
1577 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1578 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1579 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1580 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1581 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1582 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1583 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1584 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1585
1586 /* Fibre Protocol Module registers. */
1587 iter_reg = fw->fpm_hdw_reg;
1588 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1589 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1590 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1591 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1592 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1593 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1594 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1595 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1596 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1597 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1598 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1599 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1600 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
1601 qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
1602
1603 /* Frame Buffer registers. */
1604 iter_reg = fw->fb_hdw_reg;
1605 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1606 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1607 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1608 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1609 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1610 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1611 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1612 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1613 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1614 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1615 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1616 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
1617 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1618
1619 /* Multi queue registers */
1620 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1621 &last_chain);
1622
1623 rval = qla24xx_soft_reset(ha);
1624 if (rval != QLA_SUCCESS)
1625 goto qla81xx_fw_dump_failed_0;
1626
1627 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1628 &nxt);
1629 if (rval != QLA_SUCCESS)
1630 goto qla81xx_fw_dump_failed_0;
1631
1632 nxt = qla2xxx_copy_queues(ha, nxt);
1633
1634 nxt = qla24xx_copy_eft(ha, nxt);
1635
1636 /* Chain entries -- started with MQ. */
1637 qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1638 if (last_chain) {
1639 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1640 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1641 }
1642
1643qla81xx_fw_dump_failed_0:
3420d36c 1644 qla2xxx_dump_post_process(base_vha, rval);
3a03eb79
AV		 1645
1646qla81xx_fw_dump_failed:
1647 if (!hardware_locked)
1648 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1649}
1650
1da177e4
LT		 1651/****************************************************************************/
1652/* Driver Debug Functions. */
1653/****************************************************************************/
cfb0919c
CD		 1654
1655static inline int
1656ql_mask_match(uint32_t level)
1657{
1658 if (ql2xextended_error_logging == 1)
1659 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1660 return (level & ql2xextended_error_logging) == level;
1661}
1662
3ce8866c
SK		 1663/*
1664 * This function is for formatting and logging debug information.
1665 * It is to be used when vha is available. It formats the message
1666 * and logs it to the messages file.
1667 * parameters:
1668 * level: The level of the debug messages to be printed.
1669 * If ql2xextended_error_logging value is correctly set,
1670 * this message will appear in the messages file.
1671 * vha: Pointer to the scsi_qla_host_t.
1672 * id: This is a unique identifier for the level. It identifies the
1673 * part of the code from where the message originated.
1674 * msg: The message to be displayed.
1675 */
1676void
086b3e8a
JP		 1677ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
1678{
1679 va_list va;
1680 struct va_format vaf;
3ce8866c 1681
cfb0919c 1682 if (!ql_mask_match(level))
086b3e8a 1683 return;
3ce8866c 1684
086b3e8a 1685 va_start(va, fmt);
3ce8866c 1686
086b3e8a
JP		 1687 vaf.fmt = fmt;
1688 vaf.va = &va;
3ce8866c 1689
086b3e8a
JP		 1690 if (vha != NULL) {
1691 const struct pci_dev *pdev = vha->hw->pdev;
1692 /* <module-name> <pci-name> <msg-id>:<host> Message */
1693 pr_warn("%s [%s]-%04x:%ld: %pV",
1694 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
1695 vha->host_no, &vaf);
1696 } else {
1697 pr_warn("%s [%s]-%04x: : %pV",
1698 QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
3ce8866c
SK		 1699 }
1700
086b3e8a 1701 va_end(va);
3ce8866c
SK		 1702
1703}
1704
1705/*
1706 * This function is for formatting and logging debug information.
1707 * It is to be used when vha is not available and pci is availble,
1708 * i.e., before host allocation. It formats the message and logs it
1709 * to the messages file.
1710 * parameters:
1711 * level: The level of the debug messages to be printed.
1712 * If ql2xextended_error_logging value is correctly set,
1713 * this message will appear in the messages file.
1714 * pdev: Pointer to the struct pci_dev.
1715 * id: This is a unique id for the level. It identifies the part
1716 * of the code from where the message originated.
1717 * msg: The message to be displayed.
1718 */
1719void
086b3e8a
JP		 1720ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
1721 const char *fmt, ...)
1722{
1723 va_list va;
1724 struct va_format vaf;
3ce8866c
SK		 1725
1726 if (pdev == NULL)
1727 return;
cfb0919c 1728 if (!ql_mask_match(level))
086b3e8a 1729 return;
3ce8866c 1730
086b3e8a 1731 va_start(va, fmt);
3ce8866c 1732
086b3e8a
JP		 1733 vaf.fmt = fmt;
1734 vaf.va = &va;
3ce8866c 1735
086b3e8a
JP		 1736 /* <module-name> <dev-name>:<msg-id> Message */
1737 pr_warn("%s [%s]-%04x: : %pV",
1738 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
3ce8866c 1739
086b3e8a 1740 va_end(va);
3ce8866c
SK		 1741}
1742
1743/*
1744 * This function is for formatting and logging log messages.
1745 * It is to be used when vha is available. It formats the message
1746 * and logs it to the messages file. All the messages will be logged
1747 * irrespective of value of ql2xextended_error_logging.
1748 * parameters:
1749 * level: The level of the log messages to be printed in the
1750 * messages file.
1751 * vha: Pointer to the scsi_qla_host_t
1752 * id: This is a unique id for the level. It identifies the
1753 * part of the code from where the message originated.
1754 * msg: The message to be displayed.
1755 */
1756void
086b3e8a
JP		 1757ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
1758{
1759 va_list va;
1760 struct va_format vaf;
1761 char pbuf[128];
3ce8866c 1762
086b3e8a
JP		 1763 if (level > ql_errlev)
1764 return;
3ce8866c 1765
086b3e8a
JP		 1766 if (vha != NULL) {
1767 const struct pci_dev *pdev = vha->hw->pdev;
1768 /* <module-name> <msg-id>:<host> Message */
1769 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
1770 QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
1771 } else {
1772 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
1773 QL_MSGHDR, "0000:00:00.0", id);
1774 }
1775 pbuf[sizeof(pbuf) - 1] = 0;
1776
1777 va_start(va, fmt);
1778
1779 vaf.fmt = fmt;
1780 vaf.va = &va;
1781
1782 switch (level) {
1783 case 0: /* FATAL LOG */
1784 pr_crit("%s%pV", pbuf, &vaf);
1785 break;
1786 case 1:
1787 pr_err("%s%pV", pbuf, &vaf);
1788 break;
1789 case 2:
1790 pr_warn("%s%pV", pbuf, &vaf);
1791 break;
1792 default:
1793 pr_info("%s%pV", pbuf, &vaf);
1794 break;
3ce8866c
SK		 1795 }
1796
086b3e8a 1797 va_end(va);
3ce8866c
SK		 1798}
1799
1800/*
1801 * This function is for formatting and logging log messages.
1802 * It is to be used when vha is not available and pci is availble,
1803 * i.e., before host allocation. It formats the message and logs
1804 * it to the messages file. All the messages are logged irrespective
1805 * of the value of ql2xextended_error_logging.
1806 * parameters:
1807 * level: The level of the log messages to be printed in the
1808 * messages file.
1809 * pdev: Pointer to the struct pci_dev.
1810 * id: This is a unique id for the level. It identifies the
1811 * part of the code from where the message originated.
1812 * msg: The message to be displayed.
1813 */
1814void
086b3e8a
JP		 1815ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
1816 const char *fmt, ...)
1817{
1818 va_list va;
1819 struct va_format vaf;
1820 char pbuf[128];
3ce8866c
SK		 1821
1822 if (pdev == NULL)
1823 return;
086b3e8a
JP		 1824 if (level > ql_errlev)
1825 return;
3ce8866c 1826
086b3e8a
JP		 1827 /* <module-name> <dev-name>:<msg-id> Message */
1828 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
1829 QL_MSGHDR, dev_name(&(pdev->dev)), id);
1830 pbuf[sizeof(pbuf) - 1] = 0;
1831
1832 va_start(va, fmt);
1833
1834 vaf.fmt = fmt;
1835 vaf.va = &va;
1836
1837 switch (level) {
1838 case 0: /* FATAL LOG */
1839 pr_crit("%s%pV", pbuf, &vaf);
1840 break;
1841 case 1:
1842 pr_err("%s%pV", pbuf, &vaf);
1843 break;
1844 case 2:
1845 pr_warn("%s%pV", pbuf, &vaf);
1846 break;
1847 default:
1848 pr_info("%s%pV", pbuf, &vaf);
1849 break;
3ce8866c
SK		 1850 }
1851
086b3e8a 1852 va_end(va);
3ce8866c
SK		 1853}
1854
1855void
1856ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
1857{
1858 int i;
1859 struct qla_hw_data *ha = vha->hw;
1860 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1861 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
1862 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
1863 uint16_t __iomem *mbx_reg;
1864
cfb0919c
CD		 1865 if (!ql_mask_match(level))
1866 return;
3ce8866c 1867
cfb0919c
CD		 1868 if (IS_QLA82XX(ha))
1869 mbx_reg = &reg82->mailbox_in[0];
1870 else if (IS_FWI2_CAPABLE(ha))
1871 mbx_reg = &reg24->mailbox0;
1872 else
1873 mbx_reg = MAILBOX_REG(ha, reg, 0);
1874
1875 ql_dbg(level, vha, id, "Mailbox registers:\n");
1876 for (i = 0; i < 6; i++)
1877 ql_dbg(level, vha, id,
1878 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
3ce8866c
SK		 1879}
1880
1881
1882void
1883ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
1884 uint8_t *b, uint32_t size)
1885{
1886 uint32_t cnt;
1887 uint8_t c;
cfb0919c
CD		 1888
1889 if (!ql_mask_match(level))
1890 return;
1891
1892 ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
1893 "9 Ah Bh Ch Dh Eh Fh\n");
1894 ql_dbg(level, vha, id, "----------------------------------"
1895 "----------------------------\n");
1896
1897 ql_dbg(level, vha, id, " ");
1898 for (cnt = 0; cnt < size;) {
1899 c = *b++;
1900 printk("%02x", (uint32_t) c);
1901 cnt++;
1902 if (!(cnt % 16))
1903 printk("\n");
1904 else
1905 printk(" ");
3ce8866c 1906 }
cfb0919c
CD		 1907 if (cnt % 16)
1908 ql_dbg(level, vha, id, "\n");
3ce8866c 1909}
Linux 6.x block layer and io_uring tree(s)