Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
fa90c54f | 2 | * QLogic Fibre Channel HBA Driver |
1e63395c | 3 | * Copyright (c) 2003-2013 QLogic Corporation |
1da177e4 | 4 | * |
fa90c54f | 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
1da177e4 | 6 | */ |
3ce8866c SK |
7 | |
8 | /* | |
9 | * Table for showing the current message id in use for particular level | |
10 | * Change this table for addition of log/debug messages. | |
e02587d7 AE |
11 | * ---------------------------------------------------------------------- |
12 | * | Level | Last Value Used | Holes | | |
13 | * ---------------------------------------------------------------------- | |
7ec0effd | 14 | * | Module Init and Probe | 0x0151 | 0x4b,0xba,0xfa | |
754d1243 | 15 | * | Mailbox commands | 0x117a | 0x111a-0x111b | |
e9f4f418 | 16 | * | | | 0x1155-0x1158 | |
8ae6d9c7 | 17 | * | Device Discovery | 0x2095 | 0x2020-0x2022, | |
6593d5bd | 18 | * | | | 0x2011-0x2012, | |
2a8593f8 | 19 | * | | | 0x2016 | |
8ae6d9c7 | 20 | * | Queue Command and IO tracing | 0x3058 | 0x3006-0x300b | |
9e522cd8 | 21 | * | | | 0x3027-0x3028 | |
8ae6d9c7 GM |
22 | * | | | 0x303d-0x3041 | |
23 | * | | | 0x302d,0x3033 | | |
24 | * | | | 0x3036,0x3038 | | |
25 | * | | | 0x303a | | |
26 | * | DPC Thread | 0x4022 | 0x4002,0x4013 | | |
27 | * | Async Events | 0x5081 | 0x502b-0x502f | | |
9ba56b95 | 28 | * | | | 0x5047,0x5052 | |
8ae6d9c7 | 29 | * | | | 0x5040,0x5075 | |
5988aeb2 | 30 | * | Timer Routines | 0x6011 | | |
8ae6d9c7 | 31 | * | User Space Interactions | 0x70dd | 0x7018,0x702e, | |
78d56df6 | 32 | * | | | 0x7020,0x7024, | |
733a95bd JC |
33 | * | | | 0x7039,0x7045, | |
34 | * | | | 0x7073-0x7075, | | |
8ae6d9c7 | 35 | * | | | 0x707b,0x708c, | |
a9b6f722 SK |
36 | * | | | 0x70a5,0x70a6, | |
37 | * | | | 0x70a8,0x70ab, | | |
8ae6d9c7 | 38 | * | | | 0x70ad-0x70ae, | |
090fc2e2 | 39 | * | | | 0x70d1-0x70da, | |
a44c72f3 | 40 | * | | | 0x7047,0x703b | |
5854771e | 41 | * | Task Management | 0x803d | 0x8025-0x8026 | |
cfb0919c | 42 | * | | | 0x800b,0x8039 | |
5f28d2d7 | 43 | * | AER/EEH | 0x9011 | | |
e02587d7 | 44 | * | Virtual Port | 0xa007 | | |
7ec0effd AD |
45 | * | ISP82XX Specific | 0xb14c | 0xb002,0xb024 | |
46 | * | | | 0xb09e,0xb0ae | | |
47 | * | | | 0xb0e0-0xb0ef | | |
48 | * | | | 0xb085,0xb0dc | | |
49 | * | | | 0xb107,0xb108 | | |
50 | * | | | 0xb111,0xb11e | | |
51 | * | | | 0xb12c,0xb12d | | |
52 | * | | | 0xb13a,0xb142 | | |
53 | * | | | 0xb13c-0xb140 | | |
6246b8a1 GM |
54 | * | MultiQ | 0xc00c | | |
55 | * | Misc | 0xd010 | | | |
33c36c0a | 56 | * | Target Mode | 0xe070 | | |
aa230bc5 | 57 | * | Target Mode Management | 0xf072 | | |
2d70c103 | 58 | * | Target Mode Task Management | 0x1000b | | |
e02587d7 | 59 | * ---------------------------------------------------------------------- |
3ce8866c SK |
60 | */ |
61 | ||
1da177e4 LT |
62 | #include "qla_def.h" |
63 | ||
64 | #include <linux/delay.h> | |
65 | ||
3ce8866c SK |
66 | static uint32_t ql_dbg_offset = 0x800; |
67 | ||
a7a167bf | 68 | static inline void |
7b867cf7 | 69 | qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump) |
a7a167bf AV |
70 | { |
71 | fw_dump->fw_major_version = htonl(ha->fw_major_version); | |
72 | fw_dump->fw_minor_version = htonl(ha->fw_minor_version); | |
73 | fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version); | |
74 | fw_dump->fw_attributes = htonl(ha->fw_attributes); | |
75 | ||
76 | fw_dump->vendor = htonl(ha->pdev->vendor); | |
77 | fw_dump->device = htonl(ha->pdev->device); | |
78 | fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor); | |
79 | fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device); | |
80 | } | |
81 | ||
82 | static inline void * | |
73208dfd | 83 | qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr) |
a7a167bf | 84 | { |
73208dfd AC |
85 | struct req_que *req = ha->req_q_map[0]; |
86 | struct rsp_que *rsp = ha->rsp_q_map[0]; | |
a7a167bf | 87 | /* Request queue. */ |
7b867cf7 | 88 | memcpy(ptr, req->ring, req->length * |
a7a167bf AV |
89 | sizeof(request_t)); |
90 | ||
91 | /* Response queue. */ | |
7b867cf7 AC |
92 | ptr += req->length * sizeof(request_t); |
93 | memcpy(ptr, rsp->ring, rsp->length * | |
a7a167bf AV |
94 | sizeof(response_t)); |
95 | ||
7b867cf7 | 96 | return ptr + (rsp->length * sizeof(response_t)); |
a7a167bf | 97 | } |
1da177e4 | 98 | |
c3a2f0df | 99 | static int |
7b867cf7 | 100 | qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, |
c5722708 | 101 | uint32_t ram_dwords, void **nxt) |
c3a2f0df AV |
102 | { |
103 | int rval; | |
c5722708 AV |
104 | uint32_t cnt, stat, timer, dwords, idx; |
105 | uint16_t mb0; | |
c3a2f0df | 106 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
c5722708 AV |
107 | dma_addr_t dump_dma = ha->gid_list_dma; |
108 | uint32_t *dump = (uint32_t *)ha->gid_list; | |
c3a2f0df AV |
109 | |
110 | rval = QLA_SUCCESS; | |
c5722708 | 111 | mb0 = 0; |
c3a2f0df | 112 | |
c5722708 | 113 | WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED); |
c3a2f0df AV |
114 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); |
115 | ||
642ef983 | 116 | dwords = qla2x00_gid_list_size(ha) / 4; |
c5722708 AV |
117 | for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS; |
118 | cnt += dwords, addr += dwords) { | |
119 | if (cnt + dwords > ram_dwords) | |
120 | dwords = ram_dwords - cnt; | |
c3a2f0df | 121 | |
c5722708 AV |
122 | WRT_REG_WORD(®->mailbox1, LSW(addr)); |
123 | WRT_REG_WORD(®->mailbox8, MSW(addr)); | |
c3a2f0df | 124 | |
c5722708 AV |
125 | WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); |
126 | WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); | |
127 | WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); | |
128 | WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); | |
c3a2f0df | 129 | |
c5722708 AV |
130 | WRT_REG_WORD(®->mailbox4, MSW(dwords)); |
131 | WRT_REG_WORD(®->mailbox5, LSW(dwords)); | |
c3a2f0df AV |
132 | WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); |
133 | ||
134 | for (timer = 6000000; timer; timer--) { | |
135 | /* Check for pending interrupts. */ | |
136 | stat = RD_REG_DWORD(®->host_status); | |
137 | if (stat & HSRX_RISC_INT) { | |
138 | stat &= 0xff; | |
139 | ||
140 | if (stat == 0x1 || stat == 0x2 || | |
141 | stat == 0x10 || stat == 0x11) { | |
142 | set_bit(MBX_INTERRUPT, | |
143 | &ha->mbx_cmd_flags); | |
144 | ||
c5722708 | 145 | mb0 = RD_REG_WORD(®->mailbox0); |
c3a2f0df AV |
146 | |
147 | WRT_REG_DWORD(®->hccr, | |
148 | HCCRX_CLR_RISC_INT); | |
149 | RD_REG_DWORD(®->hccr); | |
150 | break; | |
151 | } | |
152 | ||
153 | /* Clear this intr; it wasn't a mailbox intr */ | |
154 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); | |
155 | RD_REG_DWORD(®->hccr); | |
156 | } | |
157 | udelay(5); | |
158 | } | |
159 | ||
160 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
c5722708 AV |
161 | rval = mb0 & MBS_MASK; |
162 | for (idx = 0; idx < dwords; idx++) | |
163 | ram[cnt + idx] = swab32(dump[idx]); | |
c3a2f0df AV |
164 | } else { |
165 | rval = QLA_FUNCTION_FAILED; | |
166 | } | |
167 | } | |
168 | ||
c5722708 | 169 | *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; |
c3a2f0df AV |
170 | return rval; |
171 | } | |
172 | ||
c5722708 | 173 | static int |
7b867cf7 | 174 | qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram, |
c5722708 AV |
175 | uint32_t cram_size, void **nxt) |
176 | { | |
177 | int rval; | |
178 | ||
179 | /* Code RAM. */ | |
180 | rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt); | |
181 | if (rval != QLA_SUCCESS) | |
182 | return rval; | |
183 | ||
184 | /* External Memory. */ | |
185 | return qla24xx_dump_ram(ha, 0x100000, *nxt, | |
186 | ha->fw_memory_size - 0x100000 + 1, nxt); | |
187 | } | |
188 | ||
c81d04c9 AV |
189 | static uint32_t * |
190 | qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, | |
191 | uint32_t count, uint32_t *buf) | |
192 | { | |
193 | uint32_t __iomem *dmp_reg; | |
194 | ||
195 | WRT_REG_DWORD(®->iobase_addr, iobase); | |
196 | dmp_reg = ®->iobase_window; | |
197 | while (count--) | |
198 | *buf++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
199 | ||
200 | return buf; | |
201 | } | |
202 | ||
203 | static inline int | |
204 | qla24xx_pause_risc(struct device_reg_24xx __iomem *reg) | |
205 | { | |
206 | int rval = QLA_SUCCESS; | |
207 | uint32_t cnt; | |
208 | ||
c3b058af | 209 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); |
aed10881 AV |
210 | for (cnt = 30000; |
211 | ((RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) == 0) && | |
c3b058af AV |
212 | rval == QLA_SUCCESS; cnt--) { |
213 | if (cnt) | |
214 | udelay(100); | |
215 | else | |
216 | rval = QLA_FUNCTION_TIMEOUT; | |
c81d04c9 AV |
217 | } |
218 | ||
219 | return rval; | |
220 | } | |
221 | ||
222 | static int | |
7b867cf7 | 223 | qla24xx_soft_reset(struct qla_hw_data *ha) |
c81d04c9 AV |
224 | { |
225 | int rval = QLA_SUCCESS; | |
226 | uint32_t cnt; | |
227 | uint16_t mb0, wd; | |
228 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
229 | ||
230 | /* Reset RISC. */ | |
231 | WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
232 | for (cnt = 0; cnt < 30000; cnt++) { | |
233 | if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) | |
234 | break; | |
235 | ||
236 | udelay(10); | |
237 | } | |
238 | ||
239 | WRT_REG_DWORD(®->ctrl_status, | |
240 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); | |
241 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); | |
242 | ||
243 | udelay(100); | |
244 | /* Wait for firmware to complete NVRAM accesses. */ | |
245 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
246 | for (cnt = 10000 ; cnt && mb0; cnt--) { | |
247 | udelay(5); | |
248 | mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); | |
249 | barrier(); | |
250 | } | |
251 | ||
252 | /* Wait for soft-reset to complete. */ | |
253 | for (cnt = 0; cnt < 30000; cnt++) { | |
254 | if ((RD_REG_DWORD(®->ctrl_status) & | |
255 | CSRX_ISP_SOFT_RESET) == 0) | |
256 | break; | |
257 | ||
258 | udelay(10); | |
259 | } | |
260 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | |
261 | RD_REG_DWORD(®->hccr); /* PCI Posting. */ | |
262 | ||
263 | for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 && | |
264 | rval == QLA_SUCCESS; cnt--) { | |
265 | if (cnt) | |
266 | udelay(100); | |
267 | else | |
268 | rval = QLA_FUNCTION_TIMEOUT; | |
269 | } | |
270 | ||
271 | return rval; | |
272 | } | |
273 | ||
c5722708 | 274 | static int |
7b867cf7 | 275 | qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram, |
e18e963b | 276 | uint32_t ram_words, void **nxt) |
c5722708 AV |
277 | { |
278 | int rval; | |
279 | uint32_t cnt, stat, timer, words, idx; | |
280 | uint16_t mb0; | |
281 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
282 | dma_addr_t dump_dma = ha->gid_list_dma; | |
283 | uint16_t *dump = (uint16_t *)ha->gid_list; | |
284 | ||
285 | rval = QLA_SUCCESS; | |
286 | mb0 = 0; | |
287 | ||
288 | WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED); | |
289 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
290 | ||
642ef983 | 291 | words = qla2x00_gid_list_size(ha) / 2; |
c5722708 AV |
292 | for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS; |
293 | cnt += words, addr += words) { | |
294 | if (cnt + words > ram_words) | |
295 | words = ram_words - cnt; | |
296 | ||
297 | WRT_MAILBOX_REG(ha, reg, 1, LSW(addr)); | |
298 | WRT_MAILBOX_REG(ha, reg, 8, MSW(addr)); | |
299 | ||
300 | WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma)); | |
301 | WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma)); | |
302 | WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma))); | |
303 | WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma))); | |
304 | ||
305 | WRT_MAILBOX_REG(ha, reg, 4, words); | |
306 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
307 | ||
308 | for (timer = 6000000; timer; timer--) { | |
309 | /* Check for pending interrupts. */ | |
310 | stat = RD_REG_DWORD(®->u.isp2300.host_status); | |
311 | if (stat & HSR_RISC_INT) { | |
312 | stat &= 0xff; | |
313 | ||
314 | if (stat == 0x1 || stat == 0x2) { | |
315 | set_bit(MBX_INTERRUPT, | |
316 | &ha->mbx_cmd_flags); | |
317 | ||
318 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
319 | ||
320 | /* Release mailbox registers. */ | |
321 | WRT_REG_WORD(®->semaphore, 0); | |
322 | WRT_REG_WORD(®->hccr, | |
323 | HCCR_CLR_RISC_INT); | |
324 | RD_REG_WORD(®->hccr); | |
325 | break; | |
326 | } else if (stat == 0x10 || stat == 0x11) { | |
327 | set_bit(MBX_INTERRUPT, | |
328 | &ha->mbx_cmd_flags); | |
329 | ||
330 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
331 | ||
332 | WRT_REG_WORD(®->hccr, | |
333 | HCCR_CLR_RISC_INT); | |
334 | RD_REG_WORD(®->hccr); | |
335 | break; | |
336 | } | |
337 | ||
338 | /* clear this intr; it wasn't a mailbox intr */ | |
339 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
340 | RD_REG_WORD(®->hccr); | |
341 | } | |
342 | udelay(5); | |
343 | } | |
344 | ||
345 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
346 | rval = mb0 & MBS_MASK; | |
347 | for (idx = 0; idx < words; idx++) | |
348 | ram[cnt + idx] = swab16(dump[idx]); | |
349 | } else { | |
350 | rval = QLA_FUNCTION_FAILED; | |
351 | } | |
352 | } | |
353 | ||
354 | *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; | |
355 | return rval; | |
356 | } | |
357 | ||
c81d04c9 AV |
358 | static inline void |
359 | qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, | |
360 | uint16_t *buf) | |
361 | { | |
362 | uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd; | |
363 | ||
364 | while (count--) | |
365 | *buf++ = htons(RD_REG_WORD(dmp_reg++)); | |
366 | } | |
367 | ||
bb99de67 AV |
368 | static inline void * |
369 | qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr) | |
370 | { | |
371 | if (!ha->eft) | |
372 | return ptr; | |
373 | ||
374 | memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size)); | |
375 | return ptr + ntohl(ha->fw_dump->eft_size); | |
376 | } | |
377 | ||
378 | static inline void * | |
379 | qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) | |
380 | { | |
381 | uint32_t cnt; | |
382 | uint32_t *iter_reg; | |
383 | struct qla2xxx_fce_chain *fcec = ptr; | |
384 | ||
385 | if (!ha->fce) | |
386 | return ptr; | |
387 | ||
388 | *last_chain = &fcec->type; | |
389 | fcec->type = __constant_htonl(DUMP_CHAIN_FCE); | |
390 | fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) + | |
391 | fce_calc_size(ha->fce_bufs)); | |
392 | fcec->size = htonl(fce_calc_size(ha->fce_bufs)); | |
393 | fcec->addr_l = htonl(LSD(ha->fce_dma)); | |
394 | fcec->addr_h = htonl(MSD(ha->fce_dma)); | |
395 | ||
396 | iter_reg = fcec->eregs; | |
397 | for (cnt = 0; cnt < 8; cnt++) | |
398 | *iter_reg++ = htonl(ha->fce_mb[cnt]); | |
399 | ||
400 | memcpy(iter_reg, ha->fce, ntohl(fcec->size)); | |
401 | ||
3cb0a67d | 402 | return (char *)iter_reg + ntohl(fcec->size); |
bb99de67 AV |
403 | } |
404 | ||
2d70c103 NB |
405 | static inline void * |
406 | qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr, | |
407 | uint32_t **last_chain) | |
408 | { | |
409 | struct qla2xxx_mqueue_chain *q; | |
410 | struct qla2xxx_mqueue_header *qh; | |
411 | uint32_t num_queues; | |
412 | int que; | |
413 | struct { | |
414 | int length; | |
415 | void *ring; | |
416 | } aq, *aqp; | |
417 | ||
00876ae8 | 418 | if (!ha->tgt.atio_ring) |
2d70c103 NB |
419 | return ptr; |
420 | ||
421 | num_queues = 1; | |
422 | aqp = &aq; | |
423 | aqp->length = ha->tgt.atio_q_length; | |
424 | aqp->ring = ha->tgt.atio_ring; | |
425 | ||
426 | for (que = 0; que < num_queues; que++) { | |
427 | /* aqp = ha->atio_q_map[que]; */ | |
428 | q = ptr; | |
429 | *last_chain = &q->type; | |
430 | q->type = __constant_htonl(DUMP_CHAIN_QUEUE); | |
431 | q->chain_size = htonl( | |
432 | sizeof(struct qla2xxx_mqueue_chain) + | |
433 | sizeof(struct qla2xxx_mqueue_header) + | |
434 | (aqp->length * sizeof(request_t))); | |
435 | ptr += sizeof(struct qla2xxx_mqueue_chain); | |
436 | ||
437 | /* Add header. */ | |
438 | qh = ptr; | |
439 | qh->queue = __constant_htonl(TYPE_ATIO_QUEUE); | |
440 | qh->number = htonl(que); | |
441 | qh->size = htonl(aqp->length * sizeof(request_t)); | |
442 | ptr += sizeof(struct qla2xxx_mqueue_header); | |
443 | ||
444 | /* Add data. */ | |
445 | memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t)); | |
446 | ||
447 | ptr += aqp->length * sizeof(request_t); | |
448 | } | |
449 | ||
450 | return ptr; | |
451 | } | |
452 | ||
050c9bb1 GM |
453 | static inline void * |
454 | qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) | |
455 | { | |
456 | struct qla2xxx_mqueue_chain *q; | |
457 | struct qla2xxx_mqueue_header *qh; | |
458 | struct req_que *req; | |
459 | struct rsp_que *rsp; | |
460 | int que; | |
461 | ||
462 | if (!ha->mqenable) | |
463 | return ptr; | |
464 | ||
465 | /* Request queues */ | |
466 | for (que = 1; que < ha->max_req_queues; que++) { | |
467 | req = ha->req_q_map[que]; | |
468 | if (!req) | |
469 | break; | |
470 | ||
471 | /* Add chain. */ | |
472 | q = ptr; | |
473 | *last_chain = &q->type; | |
474 | q->type = __constant_htonl(DUMP_CHAIN_QUEUE); | |
475 | q->chain_size = htonl( | |
476 | sizeof(struct qla2xxx_mqueue_chain) + | |
477 | sizeof(struct qla2xxx_mqueue_header) + | |
478 | (req->length * sizeof(request_t))); | |
479 | ptr += sizeof(struct qla2xxx_mqueue_chain); | |
480 | ||
481 | /* Add header. */ | |
482 | qh = ptr; | |
483 | qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE); | |
484 | qh->number = htonl(que); | |
485 | qh->size = htonl(req->length * sizeof(request_t)); | |
486 | ptr += sizeof(struct qla2xxx_mqueue_header); | |
487 | ||
488 | /* Add data. */ | |
489 | memcpy(ptr, req->ring, req->length * sizeof(request_t)); | |
490 | ptr += req->length * sizeof(request_t); | |
491 | } | |
492 | ||
493 | /* Response queues */ | |
494 | for (que = 1; que < ha->max_rsp_queues; que++) { | |
495 | rsp = ha->rsp_q_map[que]; | |
496 | if (!rsp) | |
497 | break; | |
498 | ||
499 | /* Add chain. */ | |
500 | q = ptr; | |
501 | *last_chain = &q->type; | |
502 | q->type = __constant_htonl(DUMP_CHAIN_QUEUE); | |
503 | q->chain_size = htonl( | |
504 | sizeof(struct qla2xxx_mqueue_chain) + | |
505 | sizeof(struct qla2xxx_mqueue_header) + | |
506 | (rsp->length * sizeof(response_t))); | |
507 | ptr += sizeof(struct qla2xxx_mqueue_chain); | |
508 | ||
509 | /* Add header. */ | |
510 | qh = ptr; | |
511 | qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE); | |
512 | qh->number = htonl(que); | |
513 | qh->size = htonl(rsp->length * sizeof(response_t)); | |
514 | ptr += sizeof(struct qla2xxx_mqueue_header); | |
515 | ||
516 | /* Add data. */ | |
517 | memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t)); | |
518 | ptr += rsp->length * sizeof(response_t); | |
519 | } | |
520 | ||
521 | return ptr; | |
522 | } | |
523 | ||
d63ab533 AV |
524 | static inline void * |
525 | qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) | |
526 | { | |
527 | uint32_t cnt, que_idx; | |
2afa19a9 | 528 | uint8_t que_cnt; |
d63ab533 | 529 | struct qla2xxx_mq_chain *mq = ptr; |
da9b1d5c | 530 | device_reg_t __iomem *reg; |
d63ab533 | 531 | |
6246b8a1 | 532 | if (!ha->mqenable || IS_QLA83XX(ha)) |
d63ab533 AV |
533 | return ptr; |
534 | ||
535 | mq = ptr; | |
536 | *last_chain = &mq->type; | |
537 | mq->type = __constant_htonl(DUMP_CHAIN_MQ); | |
538 | mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain)); | |
539 | ||
2afa19a9 AC |
540 | que_cnt = ha->max_req_queues > ha->max_rsp_queues ? |
541 | ha->max_req_queues : ha->max_rsp_queues; | |
d63ab533 AV |
542 | mq->count = htonl(que_cnt); |
543 | for (cnt = 0; cnt < que_cnt; cnt++) { | |
da9b1d5c | 544 | reg = ISP_QUE_REG(ha, cnt); |
d63ab533 | 545 | que_idx = cnt * 4; |
da9b1d5c AV |
546 | mq->qregs[que_idx] = |
547 | htonl(RD_REG_DWORD(®->isp25mq.req_q_in)); | |
548 | mq->qregs[que_idx+1] = | |
549 | htonl(RD_REG_DWORD(®->isp25mq.req_q_out)); | |
550 | mq->qregs[que_idx+2] = | |
551 | htonl(RD_REG_DWORD(®->isp25mq.rsp_q_in)); | |
552 | mq->qregs[que_idx+3] = | |
553 | htonl(RD_REG_DWORD(®->isp25mq.rsp_q_out)); | |
d63ab533 AV |
554 | } |
555 | ||
556 | return ptr + sizeof(struct qla2xxx_mq_chain); | |
557 | } | |
558 | ||
08de2844 | 559 | void |
3420d36c AV |
560 | qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval) |
561 | { | |
562 | struct qla_hw_data *ha = vha->hw; | |
563 | ||
564 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
565 | ql_log(ql_log_warn, vha, 0xd000, |
566 | "Failed to dump firmware (%x).\n", rval); | |
3420d36c AV |
567 | ha->fw_dumped = 0; |
568 | } else { | |
7c3df132 | 569 | ql_log(ql_log_info, vha, 0xd001, |
3420d36c AV |
570 | "Firmware dump saved to temp buffer (%ld/%p).\n", |
571 | vha->host_no, ha->fw_dump); | |
572 | ha->fw_dumped = 1; | |
573 | qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); | |
574 | } | |
575 | } | |
576 | ||
1da177e4 LT |
577 | /** |
578 | * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. | |
579 | * @ha: HA context | |
580 | * @hardware_locked: Called with the hardware_lock | |
581 | */ | |
582 | void | |
7b867cf7 | 583 | qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
1da177e4 LT |
584 | { |
585 | int rval; | |
c5722708 | 586 | uint32_t cnt; |
7b867cf7 | 587 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 588 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
589 | uint16_t __iomem *dmp_reg; |
590 | unsigned long flags; | |
591 | struct qla2300_fw_dump *fw; | |
c5722708 | 592 | void *nxt; |
73208dfd | 593 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 | 594 | |
1da177e4 LT |
595 | flags = 0; |
596 | ||
597 | if (!hardware_locked) | |
598 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
599 | ||
d4e3e04d | 600 | if (!ha->fw_dump) { |
7c3df132 SK |
601 | ql_log(ql_log_warn, vha, 0xd002, |
602 | "No buffer available for dump.\n"); | |
1da177e4 LT |
603 | goto qla2300_fw_dump_failed; |
604 | } | |
605 | ||
d4e3e04d | 606 | if (ha->fw_dumped) { |
7c3df132 SK |
607 | ql_log(ql_log_warn, vha, 0xd003, |
608 | "Firmware has been previously dumped (%p) " | |
609 | "-- ignoring request.\n", | |
610 | ha->fw_dump); | |
1da177e4 LT |
611 | goto qla2300_fw_dump_failed; |
612 | } | |
a7a167bf AV |
613 | fw = &ha->fw_dump->isp.isp23; |
614 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1da177e4 LT |
615 | |
616 | rval = QLA_SUCCESS; | |
a7a167bf | 617 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
1da177e4 LT |
618 | |
619 | /* Pause RISC. */ | |
fa2a1ce5 | 620 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
621 | if (IS_QLA2300(ha)) { |
622 | for (cnt = 30000; | |
623 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && | |
624 | rval == QLA_SUCCESS; cnt--) { | |
625 | if (cnt) | |
626 | udelay(100); | |
627 | else | |
628 | rval = QLA_FUNCTION_TIMEOUT; | |
629 | } | |
630 | } else { | |
631 | RD_REG_WORD(®->hccr); /* PCI Posting. */ | |
632 | udelay(10); | |
633 | } | |
634 | ||
635 | if (rval == QLA_SUCCESS) { | |
c81d04c9 | 636 | dmp_reg = ®->flash_address; |
fa2a1ce5 | 637 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) |
a7a167bf | 638 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 639 | |
c81d04c9 | 640 | dmp_reg = ®->u.isp2300.req_q_in; |
fa2a1ce5 | 641 | for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++) |
a7a167bf | 642 | fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 643 | |
c81d04c9 | 644 | dmp_reg = ®->u.isp2300.mailbox0; |
fa2a1ce5 | 645 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) |
a7a167bf | 646 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
647 | |
648 | WRT_REG_WORD(®->ctrl_status, 0x40); | |
c81d04c9 | 649 | qla2xxx_read_window(reg, 32, fw->resp_dma_reg); |
1da177e4 LT |
650 | |
651 | WRT_REG_WORD(®->ctrl_status, 0x50); | |
c81d04c9 | 652 | qla2xxx_read_window(reg, 48, fw->dma_reg); |
1da177e4 LT |
653 | |
654 | WRT_REG_WORD(®->ctrl_status, 0x00); | |
c81d04c9 | 655 | dmp_reg = ®->risc_hw; |
fa2a1ce5 | 656 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) |
a7a167bf | 657 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 658 | |
fa2a1ce5 | 659 | WRT_REG_WORD(®->pcr, 0x2000); |
c81d04c9 | 660 | qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); |
1da177e4 | 661 | |
fa2a1ce5 | 662 | WRT_REG_WORD(®->pcr, 0x2200); |
c81d04c9 | 663 | qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); |
1da177e4 | 664 | |
fa2a1ce5 | 665 | WRT_REG_WORD(®->pcr, 0x2400); |
c81d04c9 | 666 | qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); |
1da177e4 | 667 | |
fa2a1ce5 | 668 | WRT_REG_WORD(®->pcr, 0x2600); |
c81d04c9 | 669 | qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); |
1da177e4 | 670 | |
fa2a1ce5 | 671 | WRT_REG_WORD(®->pcr, 0x2800); |
c81d04c9 | 672 | qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); |
1da177e4 | 673 | |
fa2a1ce5 | 674 | WRT_REG_WORD(®->pcr, 0x2A00); |
c81d04c9 | 675 | qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); |
1da177e4 | 676 | |
fa2a1ce5 | 677 | WRT_REG_WORD(®->pcr, 0x2C00); |
c81d04c9 | 678 | qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); |
1da177e4 | 679 | |
fa2a1ce5 | 680 | WRT_REG_WORD(®->pcr, 0x2E00); |
c81d04c9 | 681 | qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); |
1da177e4 | 682 | |
fa2a1ce5 | 683 | WRT_REG_WORD(®->ctrl_status, 0x10); |
c81d04c9 | 684 | qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg); |
1da177e4 | 685 | |
fa2a1ce5 | 686 | WRT_REG_WORD(®->ctrl_status, 0x20); |
c81d04c9 | 687 | qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); |
1da177e4 | 688 | |
fa2a1ce5 | 689 | WRT_REG_WORD(®->ctrl_status, 0x30); |
c81d04c9 | 690 | qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); |
1da177e4 LT |
691 | |
692 | /* Reset RISC. */ | |
693 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
694 | for (cnt = 0; cnt < 30000; cnt++) { | |
695 | if ((RD_REG_WORD(®->ctrl_status) & | |
696 | CSR_ISP_SOFT_RESET) == 0) | |
697 | break; | |
698 | ||
699 | udelay(10); | |
700 | } | |
701 | } | |
702 | ||
703 | if (!IS_QLA2300(ha)) { | |
704 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && | |
705 | rval == QLA_SUCCESS; cnt--) { | |
706 | if (cnt) | |
707 | udelay(100); | |
708 | else | |
709 | rval = QLA_FUNCTION_TIMEOUT; | |
710 | } | |
711 | } | |
712 | ||
c5722708 AV |
713 | /* Get RISC SRAM. */ |
714 | if (rval == QLA_SUCCESS) | |
715 | rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram, | |
716 | sizeof(fw->risc_ram) / 2, &nxt); | |
1da177e4 | 717 | |
c5722708 AV |
718 | /* Get stack SRAM. */ |
719 | if (rval == QLA_SUCCESS) | |
720 | rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram, | |
721 | sizeof(fw->stack_ram) / 2, &nxt); | |
1da177e4 | 722 | |
c5722708 AV |
723 | /* Get data SRAM. */ |
724 | if (rval == QLA_SUCCESS) | |
725 | rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram, | |
726 | ha->fw_memory_size - 0x11000 + 1, &nxt); | |
1da177e4 | 727 | |
a7a167bf | 728 | if (rval == QLA_SUCCESS) |
73208dfd | 729 | qla2xxx_copy_queues(ha, nxt); |
a7a167bf | 730 | |
3420d36c | 731 | qla2xxx_dump_post_process(base_vha, rval); |
1da177e4 LT |
732 | |
733 | qla2300_fw_dump_failed: | |
734 | if (!hardware_locked) | |
735 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
736 | } | |
737 | ||
1da177e4 LT |
738 | /** |
739 | * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. | |
740 | * @ha: HA context | |
741 | * @hardware_locked: Called with the hardware_lock | |
742 | */ | |
743 | void | |
7b867cf7 | 744 | qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
1da177e4 LT |
745 | { |
746 | int rval; | |
747 | uint32_t cnt, timer; | |
748 | uint16_t risc_address; | |
749 | uint16_t mb0, mb2; | |
7b867cf7 | 750 | struct qla_hw_data *ha = vha->hw; |
3d71644c | 751 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1da177e4 LT |
752 | uint16_t __iomem *dmp_reg; |
753 | unsigned long flags; | |
754 | struct qla2100_fw_dump *fw; | |
73208dfd | 755 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 LT |
756 | |
757 | risc_address = 0; | |
758 | mb0 = mb2 = 0; | |
759 | flags = 0; | |
760 | ||
761 | if (!hardware_locked) | |
762 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
763 | ||
d4e3e04d | 764 | if (!ha->fw_dump) { |
7c3df132 SK |
765 | ql_log(ql_log_warn, vha, 0xd004, |
766 | "No buffer available for dump.\n"); | |
1da177e4 LT |
767 | goto qla2100_fw_dump_failed; |
768 | } | |
769 | ||
d4e3e04d | 770 | if (ha->fw_dumped) { |
7c3df132 SK |
771 | ql_log(ql_log_warn, vha, 0xd005, |
772 | "Firmware has been previously dumped (%p) " | |
773 | "-- ignoring request.\n", | |
774 | ha->fw_dump); | |
1da177e4 LT |
775 | goto qla2100_fw_dump_failed; |
776 | } | |
a7a167bf AV |
777 | fw = &ha->fw_dump->isp.isp21; |
778 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1da177e4 LT |
779 | |
780 | rval = QLA_SUCCESS; | |
a7a167bf | 781 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
1da177e4 LT |
782 | |
783 | /* Pause RISC. */ | |
fa2a1ce5 | 784 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
785 | for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && |
786 | rval == QLA_SUCCESS; cnt--) { | |
787 | if (cnt) | |
788 | udelay(100); | |
789 | else | |
790 | rval = QLA_FUNCTION_TIMEOUT; | |
791 | } | |
792 | if (rval == QLA_SUCCESS) { | |
c81d04c9 | 793 | dmp_reg = ®->flash_address; |
fa2a1ce5 | 794 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++) |
a7a167bf | 795 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 796 | |
c81d04c9 | 797 | dmp_reg = ®->u.isp2100.mailbox0; |
1da177e4 | 798 | for (cnt = 0; cnt < ha->mbx_count; cnt++) { |
c81d04c9 AV |
799 | if (cnt == 8) |
800 | dmp_reg = ®->u_end.isp2200.mailbox8; | |
801 | ||
a7a167bf | 802 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
803 | } |
804 | ||
c81d04c9 | 805 | dmp_reg = ®->u.isp2100.unused_2[0]; |
fa2a1ce5 | 806 | for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++) |
a7a167bf | 807 | fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 LT |
808 | |
809 | WRT_REG_WORD(®->ctrl_status, 0x00); | |
c81d04c9 | 810 | dmp_reg = ®->risc_hw; |
fa2a1ce5 | 811 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++) |
a7a167bf | 812 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++)); |
1da177e4 | 813 | |
fa2a1ce5 | 814 | WRT_REG_WORD(®->pcr, 0x2000); |
c81d04c9 | 815 | qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); |
1da177e4 | 816 | |
fa2a1ce5 | 817 | WRT_REG_WORD(®->pcr, 0x2100); |
c81d04c9 | 818 | qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); |
1da177e4 | 819 | |
fa2a1ce5 | 820 | WRT_REG_WORD(®->pcr, 0x2200); |
c81d04c9 | 821 | qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); |
1da177e4 | 822 | |
fa2a1ce5 | 823 | WRT_REG_WORD(®->pcr, 0x2300); |
c81d04c9 | 824 | qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); |
1da177e4 | 825 | |
fa2a1ce5 | 826 | WRT_REG_WORD(®->pcr, 0x2400); |
c81d04c9 | 827 | qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); |
1da177e4 | 828 | |
fa2a1ce5 | 829 | WRT_REG_WORD(®->pcr, 0x2500); |
c81d04c9 | 830 | qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); |
1da177e4 | 831 | |
fa2a1ce5 | 832 | WRT_REG_WORD(®->pcr, 0x2600); |
c81d04c9 | 833 | qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); |
1da177e4 | 834 | |
fa2a1ce5 | 835 | WRT_REG_WORD(®->pcr, 0x2700); |
c81d04c9 | 836 | qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); |
1da177e4 | 837 | |
fa2a1ce5 | 838 | WRT_REG_WORD(®->ctrl_status, 0x10); |
c81d04c9 | 839 | qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg); |
1da177e4 | 840 | |
fa2a1ce5 | 841 | WRT_REG_WORD(®->ctrl_status, 0x20); |
c81d04c9 | 842 | qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); |
1da177e4 | 843 | |
fa2a1ce5 | 844 | WRT_REG_WORD(®->ctrl_status, 0x30); |
c81d04c9 | 845 | qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); |
1da177e4 LT |
846 | |
847 | /* Reset the ISP. */ | |
848 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); | |
849 | } | |
850 | ||
851 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && | |
852 | rval == QLA_SUCCESS; cnt--) { | |
853 | if (cnt) | |
854 | udelay(100); | |
855 | else | |
856 | rval = QLA_FUNCTION_TIMEOUT; | |
857 | } | |
858 | ||
859 | /* Pause RISC. */ | |
860 | if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && | |
861 | (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { | |
862 | ||
fa2a1ce5 | 863 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
1da177e4 LT |
864 | for (cnt = 30000; |
865 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && | |
866 | rval == QLA_SUCCESS; cnt--) { | |
867 | if (cnt) | |
868 | udelay(100); | |
869 | else | |
870 | rval = QLA_FUNCTION_TIMEOUT; | |
871 | } | |
872 | if (rval == QLA_SUCCESS) { | |
873 | /* Set memory configuration and timing. */ | |
874 | if (IS_QLA2100(ha)) | |
875 | WRT_REG_WORD(®->mctr, 0xf1); | |
876 | else | |
877 | WRT_REG_WORD(®->mctr, 0xf2); | |
878 | RD_REG_WORD(®->mctr); /* PCI Posting. */ | |
879 | ||
880 | /* Release RISC. */ | |
881 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); | |
882 | } | |
883 | } | |
884 | ||
885 | if (rval == QLA_SUCCESS) { | |
886 | /* Get RISC SRAM. */ | |
887 | risc_address = 0x1000; | |
888 | WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); | |
889 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | |
890 | } | |
891 | for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS; | |
892 | cnt++, risc_address++) { | |
893 | WRT_MAILBOX_REG(ha, reg, 1, risc_address); | |
894 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); | |
895 | ||
896 | for (timer = 6000000; timer != 0; timer--) { | |
897 | /* Check for pending interrupts. */ | |
898 | if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) { | |
899 | if (RD_REG_WORD(®->semaphore) & BIT_0) { | |
900 | set_bit(MBX_INTERRUPT, | |
901 | &ha->mbx_cmd_flags); | |
902 | ||
903 | mb0 = RD_MAILBOX_REG(ha, reg, 0); | |
904 | mb2 = RD_MAILBOX_REG(ha, reg, 2); | |
905 | ||
906 | WRT_REG_WORD(®->semaphore, 0); | |
907 | WRT_REG_WORD(®->hccr, | |
908 | HCCR_CLR_RISC_INT); | |
909 | RD_REG_WORD(®->hccr); | |
910 | break; | |
911 | } | |
912 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); | |
913 | RD_REG_WORD(®->hccr); | |
914 | } | |
915 | udelay(5); | |
916 | } | |
917 | ||
918 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { | |
919 | rval = mb0 & MBS_MASK; | |
a7a167bf | 920 | fw->risc_ram[cnt] = htons(mb2); |
1da177e4 LT |
921 | } else { |
922 | rval = QLA_FUNCTION_FAILED; | |
923 | } | |
924 | } | |
925 | ||
a7a167bf | 926 | if (rval == QLA_SUCCESS) |
73208dfd | 927 | qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]); |
a7a167bf | 928 | |
3420d36c | 929 | qla2xxx_dump_post_process(base_vha, rval); |
1da177e4 LT |
930 | |
931 | qla2100_fw_dump_failed: | |
932 | if (!hardware_locked) | |
933 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
934 | } | |
935 | ||
6d9b61ed | 936 | void |
7b867cf7 | 937 | qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
6d9b61ed AV |
938 | { |
939 | int rval; | |
c3a2f0df | 940 | uint32_t cnt; |
6d9b61ed | 941 | uint32_t risc_address; |
7b867cf7 | 942 | struct qla_hw_data *ha = vha->hw; |
6d9b61ed AV |
943 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
944 | uint32_t __iomem *dmp_reg; | |
945 | uint32_t *iter_reg; | |
946 | uint16_t __iomem *mbx_reg; | |
947 | unsigned long flags; | |
948 | struct qla24xx_fw_dump *fw; | |
949 | uint32_t ext_mem_cnt; | |
c3a2f0df | 950 | void *nxt; |
2d70c103 NB |
951 | void *nxt_chain; |
952 | uint32_t *last_chain = NULL; | |
73208dfd | 953 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
6d9b61ed | 954 | |
7ec0effd | 955 | if (IS_P3P_TYPE(ha)) |
a9083016 GM |
956 | return; |
957 | ||
6d9b61ed | 958 | risc_address = ext_mem_cnt = 0; |
6d9b61ed AV |
959 | flags = 0; |
960 | ||
961 | if (!hardware_locked) | |
962 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
963 | ||
d4e3e04d | 964 | if (!ha->fw_dump) { |
7c3df132 SK |
965 | ql_log(ql_log_warn, vha, 0xd006, |
966 | "No buffer available for dump.\n"); | |
6d9b61ed AV |
967 | goto qla24xx_fw_dump_failed; |
968 | } | |
969 | ||
970 | if (ha->fw_dumped) { | |
7c3df132 SK |
971 | ql_log(ql_log_warn, vha, 0xd007, |
972 | "Firmware has been previously dumped (%p) " | |
973 | "-- ignoring request.\n", | |
974 | ha->fw_dump); | |
6d9b61ed AV |
975 | goto qla24xx_fw_dump_failed; |
976 | } | |
a7a167bf AV |
977 | fw = &ha->fw_dump->isp.isp24; |
978 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
6d9b61ed | 979 | |
a7a167bf | 980 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
6d9b61ed AV |
981 | |
982 | /* Pause RISC. */ | |
c81d04c9 AV |
983 | rval = qla24xx_pause_risc(reg); |
984 | if (rval != QLA_SUCCESS) | |
985 | goto qla24xx_fw_dump_failed_0; | |
986 | ||
987 | /* Host interface registers. */ | |
988 | dmp_reg = ®->flash_addr; | |
989 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
990 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
991 | ||
992 | /* Disable interrupts. */ | |
993 | WRT_REG_DWORD(®->ictrl, 0); | |
994 | RD_REG_DWORD(®->ictrl); | |
995 | ||
996 | /* Shadow registers. */ | |
997 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
998 | RD_REG_DWORD(®->iobase_addr); | |
999 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
1000 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1001 | ||
1002 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
1003 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1004 | ||
1005 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
1006 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1007 | ||
1008 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
1009 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1010 | ||
1011 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
1012 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1013 | ||
1014 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
1015 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1016 | ||
1017 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
1018 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1019 | ||
1020 | /* Mailbox registers. */ | |
1021 | mbx_reg = ®->mailbox0; | |
1022 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
1023 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
1024 | ||
1025 | /* Transfer sequence registers. */ | |
1026 | iter_reg = fw->xseq_gp_reg; | |
1027 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
1028 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
1029 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
1030 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
1031 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
1032 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
1033 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
1034 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
1035 | ||
1036 | qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg); | |
1037 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
1038 | ||
1039 | /* Receive sequence registers. */ | |
1040 | iter_reg = fw->rseq_gp_reg; | |
1041 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
1042 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
1043 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
1044 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
1045 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
1046 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
1047 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
1048 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
1049 | ||
1050 | qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg); | |
1051 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
1052 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
1053 | ||
1054 | /* Command DMA registers. */ | |
1055 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
1056 | ||
1057 | /* Queues. */ | |
1058 | iter_reg = fw->req0_dma_reg; | |
1059 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
1060 | dmp_reg = ®->iobase_q; | |
1061 | for (cnt = 0; cnt < 7; cnt++) | |
1062 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1063 | ||
1064 | iter_reg = fw->resp0_dma_reg; | |
1065 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
1066 | dmp_reg = ®->iobase_q; | |
1067 | for (cnt = 0; cnt < 7; cnt++) | |
1068 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1069 | ||
1070 | iter_reg = fw->req1_dma_reg; | |
1071 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
1072 | dmp_reg = ®->iobase_q; | |
1073 | for (cnt = 0; cnt < 7; cnt++) | |
1074 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1075 | ||
1076 | /* Transmit DMA registers. */ | |
1077 | iter_reg = fw->xmt0_dma_reg; | |
1078 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
1079 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
1080 | ||
1081 | iter_reg = fw->xmt1_dma_reg; | |
1082 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
1083 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
1084 | ||
1085 | iter_reg = fw->xmt2_dma_reg; | |
1086 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
1087 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
1088 | ||
1089 | iter_reg = fw->xmt3_dma_reg; | |
1090 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
1091 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
1092 | ||
1093 | iter_reg = fw->xmt4_dma_reg; | |
1094 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
1095 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
1096 | ||
1097 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
1098 | ||
1099 | /* Receive DMA registers. */ | |
1100 | iter_reg = fw->rcvt0_data_dma_reg; | |
1101 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
1102 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
1103 | ||
1104 | iter_reg = fw->rcvt1_data_dma_reg; | |
1105 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
1106 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
1107 | ||
1108 | /* RISC registers. */ | |
1109 | iter_reg = fw->risc_gp_reg; | |
1110 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
1111 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
1112 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
1113 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
1114 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
1115 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
1116 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
1117 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
1118 | ||
1119 | /* Local memory controller registers. */ | |
1120 | iter_reg = fw->lmc_reg; | |
1121 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
1122 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
1123 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
1124 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
1125 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
1126 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
1127 | qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
1128 | ||
1129 | /* Fibre Protocol Module registers. */ | |
1130 | iter_reg = fw->fpm_hdw_reg; | |
1131 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
1132 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
1133 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
1134 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
1135 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
1136 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
1137 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
1138 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
1139 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
1140 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
1141 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
1142 | qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
1143 | ||
1144 | /* Frame Buffer registers. */ | |
1145 | iter_reg = fw->fb_hdw_reg; | |
1146 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
1147 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
1148 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
1149 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
1150 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
1151 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
1152 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
1153 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
1154 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
1155 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
1156 | qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
1157 | ||
1158 | rval = qla24xx_soft_reset(ha); | |
1159 | if (rval != QLA_SUCCESS) | |
1160 | goto qla24xx_fw_dump_failed_0; | |
1161 | ||
1162 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
c5722708 | 1163 | &nxt); |
c81d04c9 AV |
1164 | if (rval != QLA_SUCCESS) |
1165 | goto qla24xx_fw_dump_failed_0; | |
1166 | ||
73208dfd | 1167 | nxt = qla2xxx_copy_queues(ha, nxt); |
bb99de67 AV |
1168 | |
1169 | qla24xx_copy_eft(ha, nxt); | |
c81d04c9 | 1170 | |
2d70c103 NB |
1171 | nxt_chain = (void *)ha->fw_dump + ha->chain_offset; |
1172 | nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); | |
1173 | if (last_chain) { | |
1174 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
1175 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
1176 | } | |
1177 | ||
1178 | /* Adjust valid length. */ | |
1179 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); | |
1180 | ||
c81d04c9 | 1181 | qla24xx_fw_dump_failed_0: |
3420d36c | 1182 | qla2xxx_dump_post_process(base_vha, rval); |
6d9b61ed | 1183 | |
c3a2f0df AV |
1184 | qla24xx_fw_dump_failed: |
1185 | if (!hardware_locked) | |
1186 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1187 | } | |
6d9b61ed | 1188 | |
c3a2f0df | 1189 | void |
7b867cf7 | 1190 | qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
c3a2f0df AV |
1191 | { |
1192 | int rval; | |
1193 | uint32_t cnt; | |
1194 | uint32_t risc_address; | |
7b867cf7 | 1195 | struct qla_hw_data *ha = vha->hw; |
c3a2f0df AV |
1196 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
1197 | uint32_t __iomem *dmp_reg; | |
1198 | uint32_t *iter_reg; | |
1199 | uint16_t __iomem *mbx_reg; | |
1200 | unsigned long flags; | |
1201 | struct qla25xx_fw_dump *fw; | |
1202 | uint32_t ext_mem_cnt; | |
d63ab533 | 1203 | void *nxt, *nxt_chain; |
bb99de67 | 1204 | uint32_t *last_chain = NULL; |
73208dfd | 1205 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
6d9b61ed | 1206 | |
c3a2f0df AV |
1207 | risc_address = ext_mem_cnt = 0; |
1208 | flags = 0; | |
6d9b61ed | 1209 | |
c3a2f0df AV |
1210 | if (!hardware_locked) |
1211 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
6d9b61ed | 1212 | |
c3a2f0df | 1213 | if (!ha->fw_dump) { |
7c3df132 SK |
1214 | ql_log(ql_log_warn, vha, 0xd008, |
1215 | "No buffer available for dump.\n"); | |
c3a2f0df AV |
1216 | goto qla25xx_fw_dump_failed; |
1217 | } | |
6d9b61ed | 1218 | |
c3a2f0df | 1219 | if (ha->fw_dumped) { |
7c3df132 SK |
1220 | ql_log(ql_log_warn, vha, 0xd009, |
1221 | "Firmware has been previously dumped (%p) " | |
1222 | "-- ignoring request.\n", | |
1223 | ha->fw_dump); | |
c3a2f0df AV |
1224 | goto qla25xx_fw_dump_failed; |
1225 | } | |
1226 | fw = &ha->fw_dump->isp.isp25; | |
1227 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
b5836927 | 1228 | ha->fw_dump->version = __constant_htonl(2); |
6d9b61ed | 1229 | |
c3a2f0df | 1230 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
6d9b61ed | 1231 | |
c3a2f0df | 1232 | /* Pause RISC. */ |
c81d04c9 AV |
1233 | rval = qla24xx_pause_risc(reg); |
1234 | if (rval != QLA_SUCCESS) | |
1235 | goto qla25xx_fw_dump_failed_0; | |
1236 | ||
b5836927 AV |
1237 | /* Host/Risc registers. */ |
1238 | iter_reg = fw->host_risc_reg; | |
1239 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
1240 | qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
1241 | ||
1242 | /* PCIe registers. */ | |
1243 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
1244 | RD_REG_DWORD(®->iobase_addr); | |
1245 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
1246 | dmp_reg = ®->iobase_c4; | |
1247 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1248 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1249 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
1250 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
73208dfd | 1251 | |
b5836927 AV |
1252 | WRT_REG_DWORD(®->iobase_window, 0x00); |
1253 | RD_REG_DWORD(®->iobase_window); | |
1254 | ||
c81d04c9 AV |
1255 | /* Host interface registers. */ |
1256 | dmp_reg = ®->flash_addr; | |
1257 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
1258 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1259 | ||
1260 | /* Disable interrupts. */ | |
1261 | WRT_REG_DWORD(®->ictrl, 0); | |
1262 | RD_REG_DWORD(®->ictrl); | |
1263 | ||
1264 | /* Shadow registers. */ | |
1265 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1266 | RD_REG_DWORD(®->iobase_addr); | |
1267 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
1268 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1269 | ||
1270 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
1271 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1272 | ||
1273 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
1274 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1275 | ||
1276 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
1277 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1278 | ||
1279 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
1280 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1281 | ||
1282 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
1283 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1284 | ||
1285 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
1286 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1287 | ||
1288 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
1289 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1290 | ||
1291 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
1292 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1293 | ||
1294 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
1295 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1296 | ||
1297 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
1298 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1299 | ||
1300 | /* RISC I/O register. */ | |
1301 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
1302 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
1303 | ||
1304 | /* Mailbox registers. */ | |
1305 | mbx_reg = ®->mailbox0; | |
1306 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
1307 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
1308 | ||
1309 | /* Transfer sequence registers. */ | |
1310 | iter_reg = fw->xseq_gp_reg; | |
1311 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
1312 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
1313 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
1314 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
1315 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
1316 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
1317 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
1318 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
1319 | ||
1320 | iter_reg = fw->xseq_0_reg; | |
1321 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
1322 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
1323 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
1324 | ||
1325 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
1326 | ||
1327 | /* Receive sequence registers. */ | |
1328 | iter_reg = fw->rseq_gp_reg; | |
1329 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
1330 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
1331 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
1332 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
1333 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
1334 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
1335 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
1336 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
1337 | ||
1338 | iter_reg = fw->rseq_0_reg; | |
1339 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
1340 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
1341 | ||
1342 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
1343 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
1344 | ||
1345 | /* Auxiliary sequence registers. */ | |
1346 | iter_reg = fw->aseq_gp_reg; | |
1347 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
1348 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
1349 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
1350 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
1351 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
1352 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
1353 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
1354 | qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
1355 | ||
1356 | iter_reg = fw->aseq_0_reg; | |
1357 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
1358 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
1359 | ||
1360 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
1361 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
1362 | ||
1363 | /* Command DMA registers. */ | |
1364 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
1365 | ||
1366 | /* Queues. */ | |
1367 | iter_reg = fw->req0_dma_reg; | |
1368 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
1369 | dmp_reg = ®->iobase_q; | |
1370 | for (cnt = 0; cnt < 7; cnt++) | |
1371 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1372 | ||
1373 | iter_reg = fw->resp0_dma_reg; | |
1374 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
1375 | dmp_reg = ®->iobase_q; | |
1376 | for (cnt = 0; cnt < 7; cnt++) | |
1377 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1378 | ||
1379 | iter_reg = fw->req1_dma_reg; | |
1380 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
1381 | dmp_reg = ®->iobase_q; | |
1382 | for (cnt = 0; cnt < 7; cnt++) | |
1383 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1384 | ||
1385 | /* Transmit DMA registers. */ | |
1386 | iter_reg = fw->xmt0_dma_reg; | |
1387 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
1388 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
1389 | ||
1390 | iter_reg = fw->xmt1_dma_reg; | |
1391 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
1392 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
1393 | ||
1394 | iter_reg = fw->xmt2_dma_reg; | |
1395 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
1396 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
1397 | ||
1398 | iter_reg = fw->xmt3_dma_reg; | |
1399 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
1400 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
1401 | ||
1402 | iter_reg = fw->xmt4_dma_reg; | |
1403 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
1404 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
1405 | ||
1406 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
1407 | ||
1408 | /* Receive DMA registers. */ | |
1409 | iter_reg = fw->rcvt0_data_dma_reg; | |
1410 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
1411 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
1412 | ||
1413 | iter_reg = fw->rcvt1_data_dma_reg; | |
1414 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
1415 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
1416 | ||
1417 | /* RISC registers. */ | |
1418 | iter_reg = fw->risc_gp_reg; | |
1419 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
1420 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
1421 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
1422 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
1423 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
1424 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
1425 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
1426 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
1427 | ||
1428 | /* Local memory controller registers. */ | |
1429 | iter_reg = fw->lmc_reg; | |
1430 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
1431 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
1432 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
1433 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
1434 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
1435 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
1436 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
1437 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
1438 | ||
1439 | /* Fibre Protocol Module registers. */ | |
1440 | iter_reg = fw->fpm_hdw_reg; | |
1441 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
1442 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
1443 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
1444 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
1445 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
1446 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
1447 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
1448 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
1449 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
1450 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
1451 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
1452 | qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
1453 | ||
1454 | /* Frame Buffer registers. */ | |
1455 | iter_reg = fw->fb_hdw_reg; | |
1456 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
1457 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
1458 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
1459 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
1460 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
1461 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
1462 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
1463 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
1464 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
1465 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
1466 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
1467 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
1468 | ||
d63ab533 AV |
1469 | /* Multi queue registers */ |
1470 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, | |
1471 | &last_chain); | |
1472 | ||
c81d04c9 AV |
1473 | rval = qla24xx_soft_reset(ha); |
1474 | if (rval != QLA_SUCCESS) | |
1475 | goto qla25xx_fw_dump_failed_0; | |
1476 | ||
1477 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
c5722708 | 1478 | &nxt); |
c81d04c9 AV |
1479 | if (rval != QLA_SUCCESS) |
1480 | goto qla25xx_fw_dump_failed_0; | |
1481 | ||
73208dfd | 1482 | nxt = qla2xxx_copy_queues(ha, nxt); |
c81d04c9 | 1483 | |
7f544d00 | 1484 | qla24xx_copy_eft(ha, nxt); |
df613b96 | 1485 | |
d63ab533 | 1486 | /* Chain entries -- started with MQ. */ |
050c9bb1 GM |
1487 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); |
1488 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); | |
2d70c103 | 1489 | nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); |
bb99de67 AV |
1490 | if (last_chain) { |
1491 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
1492 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
1493 | } | |
df613b96 | 1494 | |
050c9bb1 GM |
1495 | /* Adjust valid length. */ |
1496 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); | |
1497 | ||
c81d04c9 | 1498 | qla25xx_fw_dump_failed_0: |
3420d36c | 1499 | qla2xxx_dump_post_process(base_vha, rval); |
6d9b61ed | 1500 | |
c3a2f0df | 1501 | qla25xx_fw_dump_failed: |
6d9b61ed AV |
1502 | if (!hardware_locked) |
1503 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1504 | } | |
3a03eb79 AV |
1505 | |
1506 | void | |
1507 | qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) | |
1508 | { | |
1509 | int rval; | |
1510 | uint32_t cnt; | |
1511 | uint32_t risc_address; | |
1512 | struct qla_hw_data *ha = vha->hw; | |
1513 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1514 | uint32_t __iomem *dmp_reg; | |
1515 | uint32_t *iter_reg; | |
1516 | uint16_t __iomem *mbx_reg; | |
1517 | unsigned long flags; | |
1518 | struct qla81xx_fw_dump *fw; | |
1519 | uint32_t ext_mem_cnt; | |
1520 | void *nxt, *nxt_chain; | |
1521 | uint32_t *last_chain = NULL; | |
1522 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
1523 | ||
1524 | risc_address = ext_mem_cnt = 0; | |
1525 | flags = 0; | |
1526 | ||
1527 | if (!hardware_locked) | |
1528 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1529 | ||
1530 | if (!ha->fw_dump) { | |
7c3df132 SK |
1531 | ql_log(ql_log_warn, vha, 0xd00a, |
1532 | "No buffer available for dump.\n"); | |
3a03eb79 AV |
1533 | goto qla81xx_fw_dump_failed; |
1534 | } | |
1535 | ||
1536 | if (ha->fw_dumped) { | |
7c3df132 SK |
1537 | ql_log(ql_log_warn, vha, 0xd00b, |
1538 | "Firmware has been previously dumped (%p) " | |
1539 | "-- ignoring request.\n", | |
1540 | ha->fw_dump); | |
3a03eb79 AV |
1541 | goto qla81xx_fw_dump_failed; |
1542 | } | |
1543 | fw = &ha->fw_dump->isp.isp81; | |
1544 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1545 | ||
1546 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); | |
1547 | ||
1548 | /* Pause RISC. */ | |
1549 | rval = qla24xx_pause_risc(reg); | |
1550 | if (rval != QLA_SUCCESS) | |
1551 | goto qla81xx_fw_dump_failed_0; | |
1552 | ||
1553 | /* Host/Risc registers. */ | |
1554 | iter_reg = fw->host_risc_reg; | |
1555 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
1556 | qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
1557 | ||
1558 | /* PCIe registers. */ | |
1559 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
1560 | RD_REG_DWORD(®->iobase_addr); | |
1561 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
1562 | dmp_reg = ®->iobase_c4; | |
1563 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1564 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1565 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
1566 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
1567 | ||
1568 | WRT_REG_DWORD(®->iobase_window, 0x00); | |
1569 | RD_REG_DWORD(®->iobase_window); | |
1570 | ||
1571 | /* Host interface registers. */ | |
1572 | dmp_reg = ®->flash_addr; | |
1573 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
1574 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1575 | ||
1576 | /* Disable interrupts. */ | |
1577 | WRT_REG_DWORD(®->ictrl, 0); | |
1578 | RD_REG_DWORD(®->ictrl); | |
1579 | ||
1580 | /* Shadow registers. */ | |
1581 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1582 | RD_REG_DWORD(®->iobase_addr); | |
1583 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
1584 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1585 | ||
1586 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
1587 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1588 | ||
1589 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
1590 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1591 | ||
1592 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
1593 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1594 | ||
1595 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
1596 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1597 | ||
1598 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
1599 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1600 | ||
1601 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
1602 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1603 | ||
1604 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
1605 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1606 | ||
1607 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
1608 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1609 | ||
1610 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
1611 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1612 | ||
1613 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
1614 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1615 | ||
1616 | /* RISC I/O register. */ | |
1617 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
1618 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
1619 | ||
1620 | /* Mailbox registers. */ | |
1621 | mbx_reg = ®->mailbox0; | |
1622 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
1623 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
1624 | ||
1625 | /* Transfer sequence registers. */ | |
1626 | iter_reg = fw->xseq_gp_reg; | |
1627 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
1628 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
1629 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
1630 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
1631 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
1632 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
1633 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
1634 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
1635 | ||
1636 | iter_reg = fw->xseq_0_reg; | |
1637 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
1638 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
1639 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
1640 | ||
1641 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
1642 | ||
1643 | /* Receive sequence registers. */ | |
1644 | iter_reg = fw->rseq_gp_reg; | |
1645 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
1646 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
1647 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
1648 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
1649 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
1650 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
1651 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
1652 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
1653 | ||
1654 | iter_reg = fw->rseq_0_reg; | |
1655 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
1656 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
1657 | ||
1658 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
1659 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
1660 | ||
1661 | /* Auxiliary sequence registers. */ | |
1662 | iter_reg = fw->aseq_gp_reg; | |
1663 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
1664 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
1665 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
1666 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
1667 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
1668 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
1669 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
1670 | qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
1671 | ||
1672 | iter_reg = fw->aseq_0_reg; | |
1673 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
1674 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
1675 | ||
1676 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
1677 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
1678 | ||
1679 | /* Command DMA registers. */ | |
1680 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); | |
1681 | ||
1682 | /* Queues. */ | |
1683 | iter_reg = fw->req0_dma_reg; | |
1684 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
1685 | dmp_reg = ®->iobase_q; | |
1686 | for (cnt = 0; cnt < 7; cnt++) | |
1687 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1688 | ||
1689 | iter_reg = fw->resp0_dma_reg; | |
1690 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
1691 | dmp_reg = ®->iobase_q; | |
1692 | for (cnt = 0; cnt < 7; cnt++) | |
1693 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1694 | ||
1695 | iter_reg = fw->req1_dma_reg; | |
1696 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
1697 | dmp_reg = ®->iobase_q; | |
1698 | for (cnt = 0; cnt < 7; cnt++) | |
1699 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
1700 | ||
1701 | /* Transmit DMA registers. */ | |
1702 | iter_reg = fw->xmt0_dma_reg; | |
1703 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
1704 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
1705 | ||
1706 | iter_reg = fw->xmt1_dma_reg; | |
1707 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
1708 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
1709 | ||
1710 | iter_reg = fw->xmt2_dma_reg; | |
1711 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
1712 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
1713 | ||
1714 | iter_reg = fw->xmt3_dma_reg; | |
1715 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
1716 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
1717 | ||
1718 | iter_reg = fw->xmt4_dma_reg; | |
1719 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
1720 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
1721 | ||
1722 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
1723 | ||
1724 | /* Receive DMA registers. */ | |
1725 | iter_reg = fw->rcvt0_data_dma_reg; | |
1726 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
1727 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
1728 | ||
1729 | iter_reg = fw->rcvt1_data_dma_reg; | |
1730 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
1731 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
1732 | ||
1733 | /* RISC registers. */ | |
1734 | iter_reg = fw->risc_gp_reg; | |
1735 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
1736 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
1737 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
1738 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
1739 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
1740 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
1741 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
1742 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
1743 | ||
1744 | /* Local memory controller registers. */ | |
1745 | iter_reg = fw->lmc_reg; | |
1746 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
1747 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
1748 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
1749 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
1750 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
1751 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
1752 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
1753 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
1754 | ||
1755 | /* Fibre Protocol Module registers. */ | |
1756 | iter_reg = fw->fpm_hdw_reg; | |
1757 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
1758 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
1759 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
1760 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
1761 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
1762 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
1763 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
1764 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
1765 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
1766 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
1767 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
1768 | iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
1769 | iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); | |
1770 | qla24xx_read_window(reg, 0x40D0, 16, iter_reg); | |
1771 | ||
1772 | /* Frame Buffer registers. */ | |
1773 | iter_reg = fw->fb_hdw_reg; | |
1774 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
1775 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
1776 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
1777 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
1778 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
1779 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
1780 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
1781 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
1782 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
1783 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
1784 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
1785 | iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); | |
1786 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
1787 | ||
1788 | /* Multi queue registers */ | |
1789 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, | |
1790 | &last_chain); | |
1791 | ||
1792 | rval = qla24xx_soft_reset(ha); | |
1793 | if (rval != QLA_SUCCESS) | |
1794 | goto qla81xx_fw_dump_failed_0; | |
1795 | ||
1796 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
1797 | &nxt); | |
1798 | if (rval != QLA_SUCCESS) | |
1799 | goto qla81xx_fw_dump_failed_0; | |
1800 | ||
1801 | nxt = qla2xxx_copy_queues(ha, nxt); | |
1802 | ||
7f544d00 | 1803 | qla24xx_copy_eft(ha, nxt); |
3a03eb79 AV |
1804 | |
1805 | /* Chain entries -- started with MQ. */ | |
050c9bb1 GM |
1806 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); |
1807 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); | |
2d70c103 | 1808 | nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); |
3a03eb79 AV |
1809 | if (last_chain) { |
1810 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
1811 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
1812 | } | |
1813 | ||
050c9bb1 GM |
1814 | /* Adjust valid length. */ |
1815 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); | |
1816 | ||
3a03eb79 | 1817 | qla81xx_fw_dump_failed_0: |
3420d36c | 1818 | qla2xxx_dump_post_process(base_vha, rval); |
3a03eb79 AV |
1819 | |
1820 | qla81xx_fw_dump_failed: | |
1821 | if (!hardware_locked) | |
1822 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1823 | } | |
1824 | ||
6246b8a1 GM |
1825 | void |
1826 | qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) | |
1827 | { | |
1828 | int rval; | |
1829 | uint32_t cnt, reg_data; | |
1830 | uint32_t risc_address; | |
1831 | struct qla_hw_data *ha = vha->hw; | |
1832 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1833 | uint32_t __iomem *dmp_reg; | |
1834 | uint32_t *iter_reg; | |
1835 | uint16_t __iomem *mbx_reg; | |
1836 | unsigned long flags; | |
1837 | struct qla83xx_fw_dump *fw; | |
1838 | uint32_t ext_mem_cnt; | |
1839 | void *nxt, *nxt_chain; | |
1840 | uint32_t *last_chain = NULL; | |
1841 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
1842 | ||
1843 | risc_address = ext_mem_cnt = 0; | |
1844 | flags = 0; | |
1845 | ||
1846 | if (!hardware_locked) | |
1847 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1848 | ||
1849 | if (!ha->fw_dump) { | |
1850 | ql_log(ql_log_warn, vha, 0xd00c, | |
1851 | "No buffer available for dump!!!\n"); | |
1852 | goto qla83xx_fw_dump_failed; | |
1853 | } | |
1854 | ||
1855 | if (ha->fw_dumped) { | |
1856 | ql_log(ql_log_warn, vha, 0xd00d, | |
1857 | "Firmware has been previously dumped (%p) -- ignoring " | |
1858 | "request...\n", ha->fw_dump); | |
1859 | goto qla83xx_fw_dump_failed; | |
1860 | } | |
1861 | fw = &ha->fw_dump->isp.isp83; | |
1862 | qla2xxx_prep_dump(ha, ha->fw_dump); | |
1863 | ||
1864 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); | |
1865 | ||
1866 | /* Pause RISC. */ | |
1867 | rval = qla24xx_pause_risc(reg); | |
1868 | if (rval != QLA_SUCCESS) | |
1869 | goto qla83xx_fw_dump_failed_0; | |
1870 | ||
1871 | WRT_REG_DWORD(®->iobase_addr, 0x6000); | |
1872 | dmp_reg = ®->iobase_window; | |
1873 | reg_data = RD_REG_DWORD(dmp_reg); | |
1874 | WRT_REG_DWORD(dmp_reg, 0); | |
1875 | ||
1876 | dmp_reg = ®->unused_4_1[0]; | |
1877 | reg_data = RD_REG_DWORD(dmp_reg); | |
1878 | WRT_REG_DWORD(dmp_reg, 0); | |
1879 | ||
1880 | WRT_REG_DWORD(®->iobase_addr, 0x6010); | |
1881 | dmp_reg = ®->unused_4_1[2]; | |
1882 | reg_data = RD_REG_DWORD(dmp_reg); | |
1883 | WRT_REG_DWORD(dmp_reg, 0); | |
1884 | ||
1885 | /* select PCR and disable ecc checking and correction */ | |
1886 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1887 | RD_REG_DWORD(®->iobase_addr); | |
1888 | WRT_REG_DWORD(®->iobase_select, 0x60000000); /* write to F0h = PCR */ | |
1889 | ||
1890 | /* Host/Risc registers. */ | |
1891 | iter_reg = fw->host_risc_reg; | |
1892 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); | |
1893 | iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg); | |
1894 | qla24xx_read_window(reg, 0x7040, 16, iter_reg); | |
1895 | ||
1896 | /* PCIe registers. */ | |
1897 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); | |
1898 | RD_REG_DWORD(®->iobase_addr); | |
1899 | WRT_REG_DWORD(®->iobase_window, 0x01); | |
1900 | dmp_reg = ®->iobase_c4; | |
1901 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1902 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1903 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); | |
1904 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); | |
1905 | ||
1906 | WRT_REG_DWORD(®->iobase_window, 0x00); | |
1907 | RD_REG_DWORD(®->iobase_window); | |
1908 | ||
1909 | /* Host interface registers. */ | |
1910 | dmp_reg = ®->flash_addr; | |
1911 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) | |
1912 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++)); | |
1913 | ||
1914 | /* Disable interrupts. */ | |
1915 | WRT_REG_DWORD(®->ictrl, 0); | |
1916 | RD_REG_DWORD(®->ictrl); | |
1917 | ||
1918 | /* Shadow registers. */ | |
1919 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); | |
1920 | RD_REG_DWORD(®->iobase_addr); | |
1921 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); | |
1922 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1923 | ||
1924 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); | |
1925 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1926 | ||
1927 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); | |
1928 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1929 | ||
1930 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); | |
1931 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1932 | ||
1933 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); | |
1934 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1935 | ||
1936 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); | |
1937 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1938 | ||
1939 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); | |
1940 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1941 | ||
1942 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); | |
1943 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1944 | ||
1945 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); | |
1946 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1947 | ||
1948 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); | |
1949 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1950 | ||
1951 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); | |
1952 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); | |
1953 | ||
1954 | /* RISC I/O register. */ | |
1955 | WRT_REG_DWORD(®->iobase_addr, 0x0010); | |
1956 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); | |
1957 | ||
1958 | /* Mailbox registers. */ | |
1959 | mbx_reg = ®->mailbox0; | |
1960 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) | |
1961 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++)); | |
1962 | ||
1963 | /* Transfer sequence registers. */ | |
1964 | iter_reg = fw->xseq_gp_reg; | |
1965 | iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg); | |
1966 | iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg); | |
1967 | iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg); | |
1968 | iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg); | |
1969 | iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg); | |
1970 | iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg); | |
1971 | iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg); | |
1972 | iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg); | |
1973 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); | |
1974 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); | |
1975 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); | |
1976 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); | |
1977 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); | |
1978 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); | |
1979 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); | |
1980 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); | |
1981 | ||
1982 | iter_reg = fw->xseq_0_reg; | |
1983 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); | |
1984 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); | |
1985 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); | |
1986 | ||
1987 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); | |
1988 | ||
1989 | qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg); | |
1990 | ||
1991 | /* Receive sequence registers. */ | |
1992 | iter_reg = fw->rseq_gp_reg; | |
1993 | iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg); | |
1994 | iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg); | |
1995 | iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg); | |
1996 | iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg); | |
1997 | iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg); | |
1998 | iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg); | |
1999 | iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg); | |
2000 | iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg); | |
2001 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); | |
2002 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); | |
2003 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); | |
2004 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); | |
2005 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); | |
2006 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); | |
2007 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); | |
2008 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); | |
2009 | ||
2010 | iter_reg = fw->rseq_0_reg; | |
2011 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); | |
2012 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); | |
2013 | ||
2014 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); | |
2015 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); | |
2016 | qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg); | |
2017 | ||
2018 | /* Auxiliary sequence registers. */ | |
2019 | iter_reg = fw->aseq_gp_reg; | |
2020 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); | |
2021 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); | |
2022 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); | |
2023 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); | |
2024 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); | |
2025 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); | |
2026 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); | |
2027 | iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg); | |
2028 | iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg); | |
2029 | iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg); | |
2030 | iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg); | |
2031 | iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg); | |
2032 | iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg); | |
2033 | iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg); | |
2034 | iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg); | |
2035 | qla24xx_read_window(reg, 0xB170, 16, iter_reg); | |
2036 | ||
2037 | iter_reg = fw->aseq_0_reg; | |
2038 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); | |
2039 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); | |
2040 | ||
2041 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); | |
2042 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); | |
2043 | qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg); | |
2044 | ||
2045 | /* Command DMA registers. */ | |
2046 | iter_reg = fw->cmd_dma_reg; | |
2047 | iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg); | |
2048 | iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg); | |
2049 | iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg); | |
2050 | qla24xx_read_window(reg, 0x71F0, 16, iter_reg); | |
2051 | ||
2052 | /* Queues. */ | |
2053 | iter_reg = fw->req0_dma_reg; | |
2054 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); | |
2055 | dmp_reg = ®->iobase_q; | |
2056 | for (cnt = 0; cnt < 7; cnt++) | |
2057 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
2058 | ||
2059 | iter_reg = fw->resp0_dma_reg; | |
2060 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); | |
2061 | dmp_reg = ®->iobase_q; | |
2062 | for (cnt = 0; cnt < 7; cnt++) | |
2063 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
2064 | ||
2065 | iter_reg = fw->req1_dma_reg; | |
2066 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); | |
2067 | dmp_reg = ®->iobase_q; | |
2068 | for (cnt = 0; cnt < 7; cnt++) | |
2069 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++)); | |
2070 | ||
2071 | /* Transmit DMA registers. */ | |
2072 | iter_reg = fw->xmt0_dma_reg; | |
2073 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); | |
2074 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); | |
2075 | ||
2076 | iter_reg = fw->xmt1_dma_reg; | |
2077 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); | |
2078 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); | |
2079 | ||
2080 | iter_reg = fw->xmt2_dma_reg; | |
2081 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); | |
2082 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); | |
2083 | ||
2084 | iter_reg = fw->xmt3_dma_reg; | |
2085 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); | |
2086 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); | |
2087 | ||
2088 | iter_reg = fw->xmt4_dma_reg; | |
2089 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); | |
2090 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); | |
2091 | ||
2092 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); | |
2093 | ||
2094 | /* Receive DMA registers. */ | |
2095 | iter_reg = fw->rcvt0_data_dma_reg; | |
2096 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); | |
2097 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); | |
2098 | ||
2099 | iter_reg = fw->rcvt1_data_dma_reg; | |
2100 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); | |
2101 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); | |
2102 | ||
2103 | /* RISC registers. */ | |
2104 | iter_reg = fw->risc_gp_reg; | |
2105 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); | |
2106 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); | |
2107 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); | |
2108 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); | |
2109 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); | |
2110 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); | |
2111 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); | |
2112 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); | |
2113 | ||
2114 | /* Local memory controller registers. */ | |
2115 | iter_reg = fw->lmc_reg; | |
2116 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); | |
2117 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); | |
2118 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); | |
2119 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); | |
2120 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); | |
2121 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); | |
2122 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); | |
2123 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); | |
2124 | ||
2125 | /* Fibre Protocol Module registers. */ | |
2126 | iter_reg = fw->fpm_hdw_reg; | |
2127 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); | |
2128 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); | |
2129 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); | |
2130 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); | |
2131 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); | |
2132 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); | |
2133 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); | |
2134 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); | |
2135 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); | |
2136 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); | |
2137 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); | |
2138 | iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); | |
2139 | iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); | |
2140 | iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg); | |
2141 | iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg); | |
2142 | qla24xx_read_window(reg, 0x40F0, 16, iter_reg); | |
2143 | ||
2144 | /* RQ0 Array registers. */ | |
2145 | iter_reg = fw->rq0_array_reg; | |
2146 | iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg); | |
2147 | iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg); | |
2148 | iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg); | |
2149 | iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg); | |
2150 | iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg); | |
2151 | iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg); | |
2152 | iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg); | |
2153 | iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg); | |
2154 | iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg); | |
2155 | iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg); | |
2156 | iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg); | |
2157 | iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg); | |
2158 | iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg); | |
2159 | iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg); | |
2160 | iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg); | |
2161 | qla24xx_read_window(reg, 0x5CF0, 16, iter_reg); | |
2162 | ||
2163 | /* RQ1 Array registers. */ | |
2164 | iter_reg = fw->rq1_array_reg; | |
2165 | iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg); | |
2166 | iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg); | |
2167 | iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg); | |
2168 | iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg); | |
2169 | iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg); | |
2170 | iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg); | |
2171 | iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg); | |
2172 | iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg); | |
2173 | iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg); | |
2174 | iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg); | |
2175 | iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg); | |
2176 | iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg); | |
2177 | iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg); | |
2178 | iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg); | |
2179 | iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg); | |
2180 | qla24xx_read_window(reg, 0x5DF0, 16, iter_reg); | |
2181 | ||
2182 | /* RP0 Array registers. */ | |
2183 | iter_reg = fw->rp0_array_reg; | |
2184 | iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg); | |
2185 | iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg); | |
2186 | iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg); | |
2187 | iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg); | |
2188 | iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg); | |
2189 | iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg); | |
2190 | iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg); | |
2191 | iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg); | |
2192 | iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg); | |
2193 | iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg); | |
2194 | iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg); | |
2195 | iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg); | |
2196 | iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg); | |
2197 | iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg); | |
2198 | iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg); | |
2199 | qla24xx_read_window(reg, 0x5EF0, 16, iter_reg); | |
2200 | ||
2201 | /* RP1 Array registers. */ | |
2202 | iter_reg = fw->rp1_array_reg; | |
2203 | iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg); | |
2204 | iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg); | |
2205 | iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg); | |
2206 | iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg); | |
2207 | iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg); | |
2208 | iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg); | |
2209 | iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg); | |
2210 | iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg); | |
2211 | iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg); | |
2212 | iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg); | |
2213 | iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg); | |
2214 | iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg); | |
2215 | iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg); | |
2216 | iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg); | |
2217 | iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg); | |
2218 | qla24xx_read_window(reg, 0x5FF0, 16, iter_reg); | |
2219 | ||
2220 | iter_reg = fw->at0_array_reg; | |
2221 | iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg); | |
2222 | iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg); | |
2223 | iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg); | |
2224 | iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg); | |
2225 | iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg); | |
2226 | iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg); | |
2227 | iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg); | |
2228 | qla24xx_read_window(reg, 0x70F0, 16, iter_reg); | |
2229 | ||
2230 | /* I/O Queue Control registers. */ | |
2231 | qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg); | |
2232 | ||
2233 | /* Frame Buffer registers. */ | |
2234 | iter_reg = fw->fb_hdw_reg; | |
2235 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); | |
2236 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); | |
2237 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); | |
2238 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); | |
2239 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); | |
2240 | iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg); | |
2241 | iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg); | |
2242 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); | |
2243 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); | |
2244 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); | |
2245 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); | |
2246 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); | |
2247 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); | |
2248 | iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); | |
2249 | iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg); | |
2250 | iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg); | |
2251 | iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg); | |
2252 | iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg); | |
2253 | iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg); | |
2254 | iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg); | |
2255 | iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg); | |
2256 | iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg); | |
2257 | iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg); | |
2258 | iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg); | |
2259 | iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg); | |
2260 | iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg); | |
2261 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); | |
2262 | ||
2263 | /* Multi queue registers */ | |
2264 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, | |
2265 | &last_chain); | |
2266 | ||
2267 | rval = qla24xx_soft_reset(ha); | |
2268 | if (rval != QLA_SUCCESS) { | |
2269 | ql_log(ql_log_warn, vha, 0xd00e, | |
2270 | "SOFT RESET FAILED, forcing continuation of dump!!!\n"); | |
2271 | rval = QLA_SUCCESS; | |
2272 | ||
2273 | ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n"); | |
2274 | ||
2275 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); | |
2276 | RD_REG_DWORD(®->hccr); | |
2277 | ||
2278 | WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); | |
2279 | RD_REG_DWORD(®->hccr); | |
2280 | ||
2281 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); | |
2282 | RD_REG_DWORD(®->hccr); | |
2283 | ||
2284 | for (cnt = 30000; cnt && (RD_REG_WORD(®->mailbox0)); cnt--) | |
2285 | udelay(5); | |
2286 | ||
2287 | if (!cnt) { | |
2288 | nxt = fw->code_ram; | |
8c0bc701 | 2289 | nxt += sizeof(fw->code_ram); |
6246b8a1 GM |
2290 | nxt += (ha->fw_memory_size - 0x100000 + 1); |
2291 | goto copy_queue; | |
2292 | } else | |
2293 | ql_log(ql_log_warn, vha, 0xd010, | |
2294 | "bigger hammer success?\n"); | |
2295 | } | |
2296 | ||
2297 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), | |
2298 | &nxt); | |
2299 | if (rval != QLA_SUCCESS) | |
2300 | goto qla83xx_fw_dump_failed_0; | |
2301 | ||
2302 | copy_queue: | |
2303 | nxt = qla2xxx_copy_queues(ha, nxt); | |
2304 | ||
7f544d00 | 2305 | qla24xx_copy_eft(ha, nxt); |
6246b8a1 GM |
2306 | |
2307 | /* Chain entries -- started with MQ. */ | |
2308 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); | |
2309 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); | |
2d70c103 | 2310 | nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); |
6246b8a1 GM |
2311 | if (last_chain) { |
2312 | ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT); | |
2313 | *last_chain |= __constant_htonl(DUMP_CHAIN_LAST); | |
2314 | } | |
2315 | ||
2316 | /* Adjust valid length. */ | |
2317 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); | |
2318 | ||
2319 | qla83xx_fw_dump_failed_0: | |
2320 | qla2xxx_dump_post_process(base_vha, rval); | |
2321 | ||
2322 | qla83xx_fw_dump_failed: | |
2323 | if (!hardware_locked) | |
2324 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
2325 | } | |
2326 | ||
1da177e4 LT |
2327 | /****************************************************************************/ |
2328 | /* Driver Debug Functions. */ | |
2329 | /****************************************************************************/ | |
cfb0919c CD |
2330 | |
2331 | static inline int | |
2332 | ql_mask_match(uint32_t level) | |
2333 | { | |
2334 | if (ql2xextended_error_logging == 1) | |
2335 | ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; | |
2336 | return (level & ql2xextended_error_logging) == level; | |
2337 | } | |
2338 | ||
3ce8866c SK |
2339 | /* |
2340 | * This function is for formatting and logging debug information. | |
2341 | * It is to be used when vha is available. It formats the message | |
2342 | * and logs it to the messages file. | |
2343 | * parameters: | |
2344 | * level: The level of the debug messages to be printed. | |
2345 | * If ql2xextended_error_logging value is correctly set, | |
2346 | * this message will appear in the messages file. | |
2347 | * vha: Pointer to the scsi_qla_host_t. | |
2348 | * id: This is a unique identifier for the level. It identifies the | |
2349 | * part of the code from where the message originated. | |
2350 | * msg: The message to be displayed. | |
2351 | */ | |
2352 | void | |
086b3e8a JP |
2353 | ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) |
2354 | { | |
2355 | va_list va; | |
2356 | struct va_format vaf; | |
3ce8866c | 2357 | |
cfb0919c | 2358 | if (!ql_mask_match(level)) |
086b3e8a | 2359 | return; |
3ce8866c | 2360 | |
086b3e8a | 2361 | va_start(va, fmt); |
3ce8866c | 2362 | |
086b3e8a JP |
2363 | vaf.fmt = fmt; |
2364 | vaf.va = &va; | |
3ce8866c | 2365 | |
086b3e8a JP |
2366 | if (vha != NULL) { |
2367 | const struct pci_dev *pdev = vha->hw->pdev; | |
2368 | /* <module-name> <pci-name> <msg-id>:<host> Message */ | |
2369 | pr_warn("%s [%s]-%04x:%ld: %pV", | |
2370 | QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, | |
2371 | vha->host_no, &vaf); | |
2372 | } else { | |
2373 | pr_warn("%s [%s]-%04x: : %pV", | |
2374 | QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf); | |
3ce8866c SK |
2375 | } |
2376 | ||
086b3e8a | 2377 | va_end(va); |
3ce8866c SK |
2378 | |
2379 | } | |
2380 | ||
2381 | /* | |
2382 | * This function is for formatting and logging debug information. | |
d6a03581 | 2383 | * It is to be used when vha is not available and pci is available, |
3ce8866c SK |
2384 | * i.e., before host allocation. It formats the message and logs it |
2385 | * to the messages file. | |
2386 | * parameters: | |
2387 | * level: The level of the debug messages to be printed. | |
2388 | * If ql2xextended_error_logging value is correctly set, | |
2389 | * this message will appear in the messages file. | |
2390 | * pdev: Pointer to the struct pci_dev. | |
2391 | * id: This is a unique id for the level. It identifies the part | |
2392 | * of the code from where the message originated. | |
2393 | * msg: The message to be displayed. | |
2394 | */ | |
2395 | void | |
086b3e8a JP |
2396 | ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id, |
2397 | const char *fmt, ...) | |
2398 | { | |
2399 | va_list va; | |
2400 | struct va_format vaf; | |
3ce8866c SK |
2401 | |
2402 | if (pdev == NULL) | |
2403 | return; | |
cfb0919c | 2404 | if (!ql_mask_match(level)) |
086b3e8a | 2405 | return; |
3ce8866c | 2406 | |
086b3e8a | 2407 | va_start(va, fmt); |
3ce8866c | 2408 | |
086b3e8a JP |
2409 | vaf.fmt = fmt; |
2410 | vaf.va = &va; | |
3ce8866c | 2411 | |
086b3e8a JP |
2412 | /* <module-name> <dev-name>:<msg-id> Message */ |
2413 | pr_warn("%s [%s]-%04x: : %pV", | |
2414 | QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf); | |
3ce8866c | 2415 | |
086b3e8a | 2416 | va_end(va); |
3ce8866c SK |
2417 | } |
2418 | ||
2419 | /* | |
2420 | * This function is for formatting and logging log messages. | |
2421 | * It is to be used when vha is available. It formats the message | |
2422 | * and logs it to the messages file. All the messages will be logged | |
2423 | * irrespective of value of ql2xextended_error_logging. | |
2424 | * parameters: | |
2425 | * level: The level of the log messages to be printed in the | |
2426 | * messages file. | |
2427 | * vha: Pointer to the scsi_qla_host_t | |
2428 | * id: This is a unique id for the level. It identifies the | |
2429 | * part of the code from where the message originated. | |
2430 | * msg: The message to be displayed. | |
2431 | */ | |
2432 | void | |
086b3e8a JP |
2433 | ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) |
2434 | { | |
2435 | va_list va; | |
2436 | struct va_format vaf; | |
2437 | char pbuf[128]; | |
3ce8866c | 2438 | |
086b3e8a JP |
2439 | if (level > ql_errlev) |
2440 | return; | |
3ce8866c | 2441 | |
086b3e8a JP |
2442 | if (vha != NULL) { |
2443 | const struct pci_dev *pdev = vha->hw->pdev; | |
2444 | /* <module-name> <msg-id>:<host> Message */ | |
2445 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ", | |
2446 | QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no); | |
2447 | } else { | |
2448 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", | |
2449 | QL_MSGHDR, "0000:00:00.0", id); | |
2450 | } | |
2451 | pbuf[sizeof(pbuf) - 1] = 0; | |
2452 | ||
2453 | va_start(va, fmt); | |
2454 | ||
2455 | vaf.fmt = fmt; | |
2456 | vaf.va = &va; | |
2457 | ||
2458 | switch (level) { | |
70a3fc76 | 2459 | case ql_log_fatal: /* FATAL LOG */ |
086b3e8a JP |
2460 | pr_crit("%s%pV", pbuf, &vaf); |
2461 | break; | |
70a3fc76 | 2462 | case ql_log_warn: |
086b3e8a JP |
2463 | pr_err("%s%pV", pbuf, &vaf); |
2464 | break; | |
70a3fc76 | 2465 | case ql_log_info: |
086b3e8a JP |
2466 | pr_warn("%s%pV", pbuf, &vaf); |
2467 | break; | |
2468 | default: | |
2469 | pr_info("%s%pV", pbuf, &vaf); | |
2470 | break; | |
3ce8866c SK |
2471 | } |
2472 | ||
086b3e8a | 2473 | va_end(va); |
3ce8866c SK |
2474 | } |
2475 | ||
2476 | /* | |
2477 | * This function is for formatting and logging log messages. | |
d6a03581 | 2478 | * It is to be used when vha is not available and pci is available, |
3ce8866c SK |
2479 | * i.e., before host allocation. It formats the message and logs |
2480 | * it to the messages file. All the messages are logged irrespective | |
2481 | * of the value of ql2xextended_error_logging. | |
2482 | * parameters: | |
2483 | * level: The level of the log messages to be printed in the | |
2484 | * messages file. | |
2485 | * pdev: Pointer to the struct pci_dev. | |
2486 | * id: This is a unique id for the level. It identifies the | |
2487 | * part of the code from where the message originated. | |
2488 | * msg: The message to be displayed. | |
2489 | */ | |
2490 | void | |
086b3e8a JP |
2491 | ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id, |
2492 | const char *fmt, ...) | |
2493 | { | |
2494 | va_list va; | |
2495 | struct va_format vaf; | |
2496 | char pbuf[128]; | |
3ce8866c SK |
2497 | |
2498 | if (pdev == NULL) | |
2499 | return; | |
086b3e8a JP |
2500 | if (level > ql_errlev) |
2501 | return; | |
3ce8866c | 2502 | |
086b3e8a JP |
2503 | /* <module-name> <dev-name>:<msg-id> Message */ |
2504 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", | |
2505 | QL_MSGHDR, dev_name(&(pdev->dev)), id); | |
2506 | pbuf[sizeof(pbuf) - 1] = 0; | |
2507 | ||
2508 | va_start(va, fmt); | |
2509 | ||
2510 | vaf.fmt = fmt; | |
2511 | vaf.va = &va; | |
2512 | ||
2513 | switch (level) { | |
70a3fc76 | 2514 | case ql_log_fatal: /* FATAL LOG */ |
086b3e8a JP |
2515 | pr_crit("%s%pV", pbuf, &vaf); |
2516 | break; | |
70a3fc76 | 2517 | case ql_log_warn: |
086b3e8a JP |
2518 | pr_err("%s%pV", pbuf, &vaf); |
2519 | break; | |
70a3fc76 | 2520 | case ql_log_info: |
086b3e8a JP |
2521 | pr_warn("%s%pV", pbuf, &vaf); |
2522 | break; | |
2523 | default: | |
2524 | pr_info("%s%pV", pbuf, &vaf); | |
2525 | break; | |
3ce8866c SK |
2526 | } |
2527 | ||
086b3e8a | 2528 | va_end(va); |
3ce8866c SK |
2529 | } |
2530 | ||
2531 | void | |
2532 | ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id) | |
2533 | { | |
2534 | int i; | |
2535 | struct qla_hw_data *ha = vha->hw; | |
2536 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
2537 | struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; | |
2538 | struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; | |
2539 | uint16_t __iomem *mbx_reg; | |
2540 | ||
cfb0919c CD |
2541 | if (!ql_mask_match(level)) |
2542 | return; | |
3ce8866c | 2543 | |
7ec0effd | 2544 | if (IS_P3P_TYPE(ha)) |
cfb0919c CD |
2545 | mbx_reg = ®82->mailbox_in[0]; |
2546 | else if (IS_FWI2_CAPABLE(ha)) | |
2547 | mbx_reg = ®24->mailbox0; | |
2548 | else | |
2549 | mbx_reg = MAILBOX_REG(ha, reg, 0); | |
2550 | ||
2551 | ql_dbg(level, vha, id, "Mailbox registers:\n"); | |
2552 | for (i = 0; i < 6; i++) | |
2553 | ql_dbg(level, vha, id, | |
2554 | "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++)); | |
3ce8866c SK |
2555 | } |
2556 | ||
2557 | ||
2558 | void | |
2559 | ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id, | |
2560 | uint8_t *b, uint32_t size) | |
2561 | { | |
2562 | uint32_t cnt; | |
2563 | uint8_t c; | |
cfb0919c CD |
2564 | |
2565 | if (!ql_mask_match(level)) | |
2566 | return; | |
2567 | ||
2568 | ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 " | |
2569 | "9 Ah Bh Ch Dh Eh Fh\n"); | |
2570 | ql_dbg(level, vha, id, "----------------------------------" | |
2571 | "----------------------------\n"); | |
2572 | ||
2573 | ql_dbg(level, vha, id, " "); | |
2574 | for (cnt = 0; cnt < size;) { | |
2575 | c = *b++; | |
2576 | printk("%02x", (uint32_t) c); | |
2577 | cnt++; | |
2578 | if (!(cnt % 16)) | |
2579 | printk("\n"); | |
2580 | else | |
2581 | printk(" "); | |
3ce8866c | 2582 | } |
cfb0919c CD |
2583 | if (cnt % 16) |
2584 | ql_dbg(level, vha, id, "\n"); | |
3ce8866c | 2585 | } |