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f5860992 S |
1 | /* |
2 | * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver | |
3 | * | |
4 | * Copyright (c) 2008-2009 PMC-Sierra, Inc., | |
5 | * All rights reserved. | |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | |
10 | * 1. Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions, and the following disclaimer, | |
12 | * without modification. | |
13 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer | |
14 | * substantially similar to the "NO WARRANTY" disclaimer below | |
15 | * ("Disclaimer") and any redistribution must be conditioned upon | |
16 | * including a substantially similar Disclaimer requirement for further | |
17 | * binary redistribution. | |
18 | * 3. Neither the names of the above-listed copyright holders nor the names | |
19 | * of any contributors may be used to endorse or promote products derived | |
20 | * from this software without specific prior written permission. | |
21 | * | |
22 | * Alternatively, this software may be distributed under the terms of the | |
23 | * GNU General Public License ("GPL") version 2 as published by the Free | |
24 | * Software Foundation. | |
25 | * | |
26 | * NO WARRANTY | |
27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
28 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
29 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR | |
30 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
31 | * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
32 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
33 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
34 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
35 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING | |
36 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
37 | * POSSIBILITY OF SUCH DAMAGES. | |
38 | * | |
39 | */ | |
40 | #include <linux/slab.h> | |
41 | #include "pm8001_sas.h" | |
42 | #include "pm80xx_hwi.h" | |
43 | #include "pm8001_chips.h" | |
44 | #include "pm8001_ctl.h" | |
45 | ||
46 | #define SMP_DIRECT 1 | |
47 | #define SMP_INDIRECT 2 | |
d078b511 AKS |
48 | |
49 | ||
50 | int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value) | |
51 | { | |
52 | u32 reg_val; | |
53 | unsigned long start; | |
54 | pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value); | |
55 | /* confirm the setting is written */ | |
56 | start = jiffies + HZ; /* 1 sec */ | |
57 | do { | |
58 | reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER); | |
59 | } while ((reg_val != shift_value) && time_before(jiffies, start)); | |
60 | if (reg_val != shift_value) { | |
61 | PM8001_FAIL_DBG(pm8001_ha, | |
62 | pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER" | |
63 | " = 0x%x\n", reg_val)); | |
64 | return -1; | |
65 | } | |
66 | return 0; | |
67 | } | |
68 | ||
69 | void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset, | |
70 | const void *destination, | |
71 | u32 dw_count, u32 bus_base_number) | |
72 | { | |
73 | u32 index, value, offset; | |
74 | u32 *destination1; | |
75 | destination1 = (u32 *)destination; | |
76 | ||
77 | for (index = 0; index < dw_count; index += 4, destination1++) { | |
78 | offset = (soffset + index / 4); | |
79 | if (offset < (64 * 1024)) { | |
80 | value = pm8001_cr32(pm8001_ha, bus_base_number, offset); | |
81 | *destination1 = cpu_to_le32(value); | |
82 | } | |
83 | } | |
84 | return; | |
85 | } | |
86 | ||
87 | ssize_t pm80xx_get_fatal_dump(struct device *cdev, | |
88 | struct device_attribute *attr, char *buf) | |
89 | { | |
90 | struct Scsi_Host *shost = class_to_shost(cdev); | |
91 | struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); | |
92 | struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; | |
93 | void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr; | |
d078b511 AKS |
94 | u32 accum_len , reg_val, index, *temp; |
95 | unsigned long start; | |
96 | u8 *direct_data; | |
97 | char *fatal_error_data = buf; | |
98 | ||
99 | pm8001_ha->forensic_info.data_buf.direct_data = buf; | |
100 | if (pm8001_ha->chip_id == chip_8001) { | |
101 | pm8001_ha->forensic_info.data_buf.direct_data += | |
102 | sprintf(pm8001_ha->forensic_info.data_buf.direct_data, | |
103 | "Not supported for SPC controller"); | |
104 | return (char *)pm8001_ha->forensic_info.data_buf.direct_data - | |
105 | (char *)buf; | |
106 | } | |
107 | if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { | |
108 | PM8001_IO_DBG(pm8001_ha, | |
109 | pm8001_printk("forensic_info TYPE_NON_FATAL..............\n")); | |
110 | direct_data = (u8 *)fatal_error_data; | |
111 | pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL; | |
112 | pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET; | |
d078b511 AKS |
113 | pm8001_ha->forensic_info.data_buf.read_len = 0; |
114 | ||
115 | pm8001_ha->forensic_info.data_buf.direct_data = direct_data; | |
d078b511 | 116 | |
d078b511 AKS |
117 | /* start to get data */ |
118 | /* Program the MEMBASE II Shifting Register with 0x00.*/ | |
119 | pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, | |
120 | pm8001_ha->fatal_forensic_shift_offset); | |
121 | pm8001_ha->forensic_last_offset = 0; | |
122 | pm8001_ha->forensic_fatal_step = 0; | |
123 | pm8001_ha->fatal_bar_loc = 0; | |
124 | } | |
cf370066 | 125 | |
d078b511 AKS |
126 | /* Read until accum_len is retrived */ |
127 | accum_len = pm8001_mr32(fatal_table_address, | |
128 | MPI_FATAL_EDUMP_TABLE_ACCUM_LEN); | |
129 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("accum_len 0x%x\n", | |
130 | accum_len)); | |
131 | if (accum_len == 0xFFFFFFFF) { | |
132 | PM8001_IO_DBG(pm8001_ha, | |
133 | pm8001_printk("Possible PCI issue 0x%x not expected\n", | |
134 | accum_len)); | |
cf370066 | 135 | return -EIO; |
d078b511 AKS |
136 | } |
137 | if (accum_len == 0 || accum_len >= 0x100000) { | |
138 | pm8001_ha->forensic_info.data_buf.direct_data += | |
139 | sprintf(pm8001_ha->forensic_info.data_buf.direct_data, | |
140 | "%08x ", 0xFFFFFFFF); | |
141 | return (char *)pm8001_ha->forensic_info.data_buf.direct_data - | |
142 | (char *)buf; | |
143 | } | |
144 | temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; | |
145 | if (pm8001_ha->forensic_fatal_step == 0) { | |
146 | moreData: | |
147 | if (pm8001_ha->forensic_info.data_buf.direct_data) { | |
148 | /* Data is in bar, copy to host memory */ | |
149 | pm80xx_pci_mem_copy(pm8001_ha, pm8001_ha->fatal_bar_loc, | |
150 | pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr, | |
151 | pm8001_ha->forensic_info.data_buf.direct_len , | |
152 | 1); | |
153 | } | |
154 | pm8001_ha->fatal_bar_loc += | |
155 | pm8001_ha->forensic_info.data_buf.direct_len; | |
156 | pm8001_ha->forensic_info.data_buf.direct_offset += | |
157 | pm8001_ha->forensic_info.data_buf.direct_len; | |
158 | pm8001_ha->forensic_last_offset += | |
159 | pm8001_ha->forensic_info.data_buf.direct_len; | |
160 | pm8001_ha->forensic_info.data_buf.read_len = | |
161 | pm8001_ha->forensic_info.data_buf.direct_len; | |
162 | ||
163 | if (pm8001_ha->forensic_last_offset >= accum_len) { | |
164 | pm8001_ha->forensic_info.data_buf.direct_data += | |
165 | sprintf(pm8001_ha->forensic_info.data_buf.direct_data, | |
166 | "%08x ", 3); | |
167 | for (index = 0; index < (SYSFS_OFFSET / 4); index++) { | |
168 | pm8001_ha->forensic_info.data_buf.direct_data += | |
169 | sprintf(pm8001_ha-> | |
170 | forensic_info.data_buf.direct_data, | |
171 | "%08x ", *(temp + index)); | |
172 | } | |
173 | ||
174 | pm8001_ha->fatal_bar_loc = 0; | |
175 | pm8001_ha->forensic_fatal_step = 1; | |
176 | pm8001_ha->fatal_forensic_shift_offset = 0; | |
177 | pm8001_ha->forensic_last_offset = 0; | |
d078b511 AKS |
178 | return (char *)pm8001_ha-> |
179 | forensic_info.data_buf.direct_data - | |
180 | (char *)buf; | |
181 | } | |
182 | if (pm8001_ha->fatal_bar_loc < (64 * 1024)) { | |
183 | pm8001_ha->forensic_info.data_buf.direct_data += | |
184 | sprintf(pm8001_ha-> | |
185 | forensic_info.data_buf.direct_data, | |
186 | "%08x ", 2); | |
187 | for (index = 0; index < (SYSFS_OFFSET / 4); index++) { | |
188 | pm8001_ha->forensic_info.data_buf.direct_data += | |
189 | sprintf(pm8001_ha-> | |
190 | forensic_info.data_buf.direct_data, | |
191 | "%08x ", *(temp + index)); | |
192 | } | |
d078b511 AKS |
193 | return (char *)pm8001_ha-> |
194 | forensic_info.data_buf.direct_data - | |
195 | (char *)buf; | |
196 | } | |
197 | ||
198 | /* Increment the MEMBASE II Shifting Register value by 0x100.*/ | |
199 | pm8001_ha->forensic_info.data_buf.direct_data += | |
200 | sprintf(pm8001_ha->forensic_info.data_buf.direct_data, | |
201 | "%08x ", 2); | |
202 | for (index = 0; index < 256; index++) { | |
203 | pm8001_ha->forensic_info.data_buf.direct_data += | |
204 | sprintf(pm8001_ha-> | |
205 | forensic_info.data_buf.direct_data, | |
206 | "%08x ", *(temp + index)); | |
207 | } | |
208 | pm8001_ha->fatal_forensic_shift_offset += 0x100; | |
209 | pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, | |
210 | pm8001_ha->fatal_forensic_shift_offset); | |
211 | pm8001_ha->fatal_bar_loc = 0; | |
d078b511 AKS |
212 | return (char *)pm8001_ha->forensic_info.data_buf.direct_data - |
213 | (char *)buf; | |
214 | } | |
215 | if (pm8001_ha->forensic_fatal_step == 1) { | |
216 | pm8001_ha->fatal_forensic_shift_offset = 0; | |
217 | /* Read 64K of the debug data. */ | |
218 | pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, | |
219 | pm8001_ha->fatal_forensic_shift_offset); | |
220 | pm8001_mw32(fatal_table_address, | |
221 | MPI_FATAL_EDUMP_TABLE_HANDSHAKE, | |
222 | MPI_FATAL_EDUMP_HANDSHAKE_RDY); | |
223 | ||
224 | /* Poll FDDHSHK until clear */ | |
225 | start = jiffies + (2 * HZ); /* 2 sec */ | |
226 | ||
227 | do { | |
228 | reg_val = pm8001_mr32(fatal_table_address, | |
229 | MPI_FATAL_EDUMP_TABLE_HANDSHAKE); | |
230 | } while ((reg_val) && time_before(jiffies, start)); | |
231 | ||
232 | if (reg_val != 0) { | |
233 | PM8001_FAIL_DBG(pm8001_ha, | |
234 | pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER" | |
235 | " = 0x%x\n", reg_val)); | |
cf370066 | 236 | return -EIO; |
d078b511 AKS |
237 | } |
238 | ||
239 | /* Read the next 64K of the debug data. */ | |
240 | pm8001_ha->forensic_fatal_step = 0; | |
241 | if (pm8001_mr32(fatal_table_address, | |
242 | MPI_FATAL_EDUMP_TABLE_STATUS) != | |
243 | MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) { | |
244 | pm8001_mw32(fatal_table_address, | |
245 | MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 0); | |
246 | goto moreData; | |
247 | } else { | |
248 | pm8001_ha->forensic_info.data_buf.direct_data += | |
249 | sprintf(pm8001_ha-> | |
250 | forensic_info.data_buf.direct_data, | |
251 | "%08x ", 4); | |
252 | pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF; | |
253 | pm8001_ha->forensic_info.data_buf.direct_len = 0; | |
254 | pm8001_ha->forensic_info.data_buf.direct_offset = 0; | |
255 | pm8001_ha->forensic_info.data_buf.read_len = 0; | |
d078b511 AKS |
256 | } |
257 | } | |
258 | ||
259 | return (char *)pm8001_ha->forensic_info.data_buf.direct_data - | |
260 | (char *)buf; | |
261 | } | |
262 | ||
f5860992 S |
263 | /** |
264 | * read_main_config_table - read the configure table and save it. | |
265 | * @pm8001_ha: our hba card information | |
266 | */ | |
267 | static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) | |
268 | { | |
269 | void __iomem *address = pm8001_ha->main_cfg_tbl_addr; | |
270 | ||
271 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature = | |
272 | pm8001_mr32(address, MAIN_SIGNATURE_OFFSET); | |
273 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev = | |
274 | pm8001_mr32(address, MAIN_INTERFACE_REVISION); | |
275 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev = | |
276 | pm8001_mr32(address, MAIN_FW_REVISION); | |
277 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io = | |
278 | pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET); | |
279 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl = | |
280 | pm8001_mr32(address, MAIN_MAX_SGL_OFFSET); | |
281 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag = | |
282 | pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET); | |
283 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset = | |
284 | pm8001_mr32(address, MAIN_GST_OFFSET); | |
285 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset = | |
286 | pm8001_mr32(address, MAIN_IBQ_OFFSET); | |
287 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset = | |
288 | pm8001_mr32(address, MAIN_OBQ_OFFSET); | |
289 | ||
290 | /* read Error Dump Offset and Length */ | |
291 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 = | |
292 | pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET); | |
293 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 = | |
294 | pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH); | |
295 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 = | |
296 | pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET); | |
297 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 = | |
298 | pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH); | |
299 | ||
300 | /* read GPIO LED settings from the configuration table */ | |
301 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping = | |
302 | pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET); | |
303 | ||
304 | /* read analog Setting offset from the configuration table */ | |
305 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset = | |
306 | pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET); | |
307 | ||
308 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset = | |
309 | pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET); | |
310 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset = | |
311 | pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET); | |
312 | } | |
313 | ||
314 | /** | |
315 | * read_general_status_table - read the general status table and save it. | |
316 | * @pm8001_ha: our hba card information | |
317 | */ | |
318 | static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) | |
319 | { | |
320 | void __iomem *address = pm8001_ha->general_stat_tbl_addr; | |
321 | pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate = | |
322 | pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET); | |
323 | pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 = | |
324 | pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET); | |
325 | pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 = | |
326 | pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET); | |
327 | pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt = | |
328 | pm8001_mr32(address, GST_MSGUTCNT_OFFSET); | |
329 | pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt = | |
330 | pm8001_mr32(address, GST_IOPTCNT_OFFSET); | |
331 | pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val = | |
332 | pm8001_mr32(address, GST_GPIO_INPUT_VAL); | |
333 | pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] = | |
334 | pm8001_mr32(address, GST_RERRINFO_OFFSET0); | |
335 | pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] = | |
336 | pm8001_mr32(address, GST_RERRINFO_OFFSET1); | |
337 | pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] = | |
338 | pm8001_mr32(address, GST_RERRINFO_OFFSET2); | |
339 | pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] = | |
340 | pm8001_mr32(address, GST_RERRINFO_OFFSET3); | |
341 | pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] = | |
342 | pm8001_mr32(address, GST_RERRINFO_OFFSET4); | |
343 | pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] = | |
344 | pm8001_mr32(address, GST_RERRINFO_OFFSET5); | |
345 | pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] = | |
346 | pm8001_mr32(address, GST_RERRINFO_OFFSET6); | |
347 | pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] = | |
348 | pm8001_mr32(address, GST_RERRINFO_OFFSET7); | |
349 | } | |
350 | /** | |
351 | * read_phy_attr_table - read the phy attribute table and save it. | |
352 | * @pm8001_ha: our hba card information | |
353 | */ | |
354 | static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha) | |
355 | { | |
356 | void __iomem *address = pm8001_ha->pspa_q_tbl_addr; | |
357 | pm8001_ha->phy_attr_table.phystart1_16[0] = | |
358 | pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET); | |
359 | pm8001_ha->phy_attr_table.phystart1_16[1] = | |
360 | pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET); | |
361 | pm8001_ha->phy_attr_table.phystart1_16[2] = | |
362 | pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET); | |
363 | pm8001_ha->phy_attr_table.phystart1_16[3] = | |
364 | pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET); | |
365 | pm8001_ha->phy_attr_table.phystart1_16[4] = | |
366 | pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET); | |
367 | pm8001_ha->phy_attr_table.phystart1_16[5] = | |
368 | pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET); | |
369 | pm8001_ha->phy_attr_table.phystart1_16[6] = | |
370 | pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET); | |
371 | pm8001_ha->phy_attr_table.phystart1_16[7] = | |
372 | pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET); | |
373 | pm8001_ha->phy_attr_table.phystart1_16[8] = | |
374 | pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET); | |
375 | pm8001_ha->phy_attr_table.phystart1_16[9] = | |
376 | pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET); | |
377 | pm8001_ha->phy_attr_table.phystart1_16[10] = | |
378 | pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET); | |
379 | pm8001_ha->phy_attr_table.phystart1_16[11] = | |
380 | pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET); | |
381 | pm8001_ha->phy_attr_table.phystart1_16[12] = | |
382 | pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET); | |
383 | pm8001_ha->phy_attr_table.phystart1_16[13] = | |
384 | pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET); | |
385 | pm8001_ha->phy_attr_table.phystart1_16[14] = | |
386 | pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET); | |
387 | pm8001_ha->phy_attr_table.phystart1_16[15] = | |
388 | pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET); | |
389 | ||
390 | pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] = | |
391 | pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET); | |
392 | pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] = | |
393 | pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET); | |
394 | pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] = | |
395 | pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET); | |
396 | pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] = | |
397 | pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET); | |
398 | pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] = | |
399 | pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET); | |
400 | pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] = | |
401 | pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET); | |
402 | pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] = | |
403 | pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET); | |
404 | pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] = | |
405 | pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET); | |
406 | pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] = | |
407 | pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET); | |
408 | pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] = | |
409 | pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET); | |
410 | pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] = | |
411 | pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET); | |
412 | pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] = | |
413 | pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET); | |
414 | pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] = | |
415 | pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET); | |
416 | pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] = | |
417 | pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET); | |
418 | pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] = | |
419 | pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET); | |
420 | pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] = | |
421 | pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET); | |
422 | ||
423 | } | |
424 | ||
425 | /** | |
426 | * read_inbnd_queue_table - read the inbound queue table and save it. | |
427 | * @pm8001_ha: our hba card information | |
428 | */ | |
429 | static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) | |
430 | { | |
431 | int i; | |
432 | void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; | |
433 | for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) { | |
434 | u32 offset = i * 0x20; | |
435 | pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = | |
436 | get_pci_bar_index(pm8001_mr32(address, | |
437 | (offset + IB_PIPCI_BAR))); | |
438 | pm8001_ha->inbnd_q_tbl[i].pi_offset = | |
439 | pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET)); | |
440 | } | |
441 | } | |
442 | ||
443 | /** | |
444 | * read_outbnd_queue_table - read the outbound queue table and save it. | |
445 | * @pm8001_ha: our hba card information | |
446 | */ | |
447 | static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) | |
448 | { | |
449 | int i; | |
450 | void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; | |
451 | for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) { | |
452 | u32 offset = i * 0x24; | |
453 | pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = | |
454 | get_pci_bar_index(pm8001_mr32(address, | |
455 | (offset + OB_CIPCI_BAR))); | |
456 | pm8001_ha->outbnd_q_tbl[i].ci_offset = | |
457 | pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET)); | |
458 | } | |
459 | } | |
460 | ||
461 | /** | |
462 | * init_default_table_values - init the default table. | |
463 | * @pm8001_ha: our hba card information | |
464 | */ | |
465 | static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) | |
466 | { | |
467 | int i; | |
468 | u32 offsetib, offsetob; | |
469 | void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; | |
470 | void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; | |
471 | ||
472 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr = | |
473 | pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; | |
474 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr = | |
475 | pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; | |
476 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size = | |
477 | PM8001_EVENT_LOG_SIZE; | |
478 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01; | |
479 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr = | |
480 | pm8001_ha->memoryMap.region[IOP].phys_addr_hi; | |
481 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr = | |
482 | pm8001_ha->memoryMap.region[IOP].phys_addr_lo; | |
483 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size = | |
484 | PM8001_EVENT_LOG_SIZE; | |
485 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01; | |
486 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01; | |
487 | ||
c6b9ef57 S |
488 | /* Disable end to end CRC checking */ |
489 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16); | |
490 | ||
f5860992 S |
491 | for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) { |
492 | pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = | |
9504a923 | 493 | PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); |
f5860992 S |
494 | pm8001_ha->inbnd_q_tbl[i].upper_base_addr = |
495 | pm8001_ha->memoryMap.region[IB + i].phys_addr_hi; | |
496 | pm8001_ha->inbnd_q_tbl[i].lower_base_addr = | |
497 | pm8001_ha->memoryMap.region[IB + i].phys_addr_lo; | |
498 | pm8001_ha->inbnd_q_tbl[i].base_virt = | |
499 | (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr; | |
500 | pm8001_ha->inbnd_q_tbl[i].total_length = | |
501 | pm8001_ha->memoryMap.region[IB + i].total_len; | |
502 | pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = | |
503 | pm8001_ha->memoryMap.region[CI + i].phys_addr_hi; | |
504 | pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = | |
505 | pm8001_ha->memoryMap.region[CI + i].phys_addr_lo; | |
506 | pm8001_ha->inbnd_q_tbl[i].ci_virt = | |
507 | pm8001_ha->memoryMap.region[CI + i].virt_ptr; | |
508 | offsetib = i * 0x20; | |
509 | pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = | |
510 | get_pci_bar_index(pm8001_mr32(addressib, | |
511 | (offsetib + 0x14))); | |
512 | pm8001_ha->inbnd_q_tbl[i].pi_offset = | |
513 | pm8001_mr32(addressib, (offsetib + 0x18)); | |
514 | pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; | |
515 | pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; | |
516 | } | |
517 | for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) { | |
518 | pm8001_ha->outbnd_q_tbl[i].element_size_cnt = | |
9504a923 | 519 | PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); |
f5860992 S |
520 | pm8001_ha->outbnd_q_tbl[i].upper_base_addr = |
521 | pm8001_ha->memoryMap.region[OB + i].phys_addr_hi; | |
522 | pm8001_ha->outbnd_q_tbl[i].lower_base_addr = | |
523 | pm8001_ha->memoryMap.region[OB + i].phys_addr_lo; | |
524 | pm8001_ha->outbnd_q_tbl[i].base_virt = | |
525 | (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr; | |
526 | pm8001_ha->outbnd_q_tbl[i].total_length = | |
527 | pm8001_ha->memoryMap.region[OB + i].total_len; | |
528 | pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = | |
529 | pm8001_ha->memoryMap.region[PI + i].phys_addr_hi; | |
530 | pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = | |
531 | pm8001_ha->memoryMap.region[PI + i].phys_addr_lo; | |
532 | /* interrupt vector based on oq */ | |
533 | pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24); | |
534 | pm8001_ha->outbnd_q_tbl[i].pi_virt = | |
535 | pm8001_ha->memoryMap.region[PI + i].virt_ptr; | |
536 | offsetob = i * 0x24; | |
537 | pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = | |
538 | get_pci_bar_index(pm8001_mr32(addressob, | |
539 | offsetob + 0x14)); | |
540 | pm8001_ha->outbnd_q_tbl[i].ci_offset = | |
541 | pm8001_mr32(addressob, (offsetob + 0x18)); | |
542 | pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; | |
543 | pm8001_ha->outbnd_q_tbl[i].producer_index = 0; | |
544 | } | |
545 | } | |
546 | ||
547 | /** | |
548 | * update_main_config_table - update the main default table to the HBA. | |
549 | * @pm8001_ha: our hba card information | |
550 | */ | |
551 | static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) | |
552 | { | |
553 | void __iomem *address = pm8001_ha->main_cfg_tbl_addr; | |
554 | pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET, | |
555 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd); | |
556 | pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI, | |
557 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr); | |
558 | pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO, | |
559 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr); | |
560 | pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE, | |
561 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size); | |
562 | pm8001_mw32(address, MAIN_EVENT_LOG_OPTION, | |
563 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity); | |
564 | pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI, | |
565 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr); | |
566 | pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO, | |
567 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr); | |
568 | pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE, | |
569 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size); | |
570 | pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION, | |
571 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity); | |
572 | pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT, | |
573 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt); | |
c6b9ef57 S |
574 | pm8001_mw32(address, MAIN_EVENT_CRC_CHECK, |
575 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump); | |
f5860992 S |
576 | |
577 | /* SPCv specific */ | |
578 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF; | |
579 | /* Set GPIOLED to 0x2 for LED indicator */ | |
580 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000; | |
581 | pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET, | |
582 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping); | |
583 | ||
584 | pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER, | |
585 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); | |
586 | pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY, | |
587 | pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay); | |
588 | } | |
589 | ||
590 | /** | |
591 | * update_inbnd_queue_table - update the inbound queue table to the HBA. | |
592 | * @pm8001_ha: our hba card information | |
593 | */ | |
594 | static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, | |
595 | int number) | |
596 | { | |
597 | void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; | |
598 | u16 offset = number * 0x20; | |
599 | pm8001_mw32(address, offset + IB_PROPERITY_OFFSET, | |
600 | pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); | |
601 | pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET, | |
602 | pm8001_ha->inbnd_q_tbl[number].upper_base_addr); | |
603 | pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET, | |
604 | pm8001_ha->inbnd_q_tbl[number].lower_base_addr); | |
605 | pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET, | |
606 | pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); | |
607 | pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET, | |
608 | pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); | |
609 | } | |
610 | ||
611 | /** | |
612 | * update_outbnd_queue_table - update the outbound queue table to the HBA. | |
613 | * @pm8001_ha: our hba card information | |
614 | */ | |
615 | static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, | |
616 | int number) | |
617 | { | |
618 | void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; | |
619 | u16 offset = number * 0x24; | |
620 | pm8001_mw32(address, offset + OB_PROPERITY_OFFSET, | |
621 | pm8001_ha->outbnd_q_tbl[number].element_size_cnt); | |
622 | pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET, | |
623 | pm8001_ha->outbnd_q_tbl[number].upper_base_addr); | |
624 | pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET, | |
625 | pm8001_ha->outbnd_q_tbl[number].lower_base_addr); | |
626 | pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET, | |
627 | pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); | |
628 | pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET, | |
629 | pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); | |
630 | pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET, | |
631 | pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); | |
632 | } | |
633 | ||
634 | /** | |
635 | * mpi_init_check - check firmware initialization status. | |
636 | * @pm8001_ha: our hba card information | |
637 | */ | |
638 | static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) | |
639 | { | |
640 | u32 max_wait_count; | |
641 | u32 value; | |
642 | u32 gst_len_mpistate; | |
643 | ||
644 | /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the | |
645 | table is updated */ | |
646 | pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE); | |
647 | /* wait until Inbound DoorBell Clear Register toggled */ | |
a9a923e5 AKS |
648 | if (IS_SPCV_12G(pm8001_ha->pdev)) { |
649 | max_wait_count = 4 * 1000 * 1000;/* 4 sec */ | |
650 | } else { | |
651 | max_wait_count = 2 * 1000 * 1000;/* 2 sec */ | |
652 | } | |
f5860992 S |
653 | do { |
654 | udelay(1); | |
655 | value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); | |
656 | value &= SPCv_MSGU_CFG_TABLE_UPDATE; | |
657 | } while ((value != 0) && (--max_wait_count)); | |
658 | ||
659 | if (!max_wait_count) | |
660 | return -1; | |
661 | /* check the MPI-State for initialization upto 100ms*/ | |
662 | max_wait_count = 100 * 1000;/* 100 msec */ | |
663 | do { | |
664 | udelay(1); | |
665 | gst_len_mpistate = | |
666 | pm8001_mr32(pm8001_ha->general_stat_tbl_addr, | |
667 | GST_GSTLEN_MPIS_OFFSET); | |
668 | } while ((GST_MPI_STATE_INIT != | |
669 | (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count)); | |
670 | if (!max_wait_count) | |
671 | return -1; | |
672 | ||
673 | /* check MPI Initialization error */ | |
674 | gst_len_mpistate = gst_len_mpistate >> 16; | |
675 | if (0x0000 != gst_len_mpistate) | |
676 | return -1; | |
677 | ||
678 | return 0; | |
679 | } | |
680 | ||
681 | /** | |
682 | * check_fw_ready - The LLDD check if the FW is ready, if not, return error. | |
683 | * @pm8001_ha: our hba card information | |
684 | */ | |
685 | static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) | |
686 | { | |
687 | u32 value; | |
688 | u32 max_wait_count; | |
689 | u32 max_wait_time; | |
690 | int ret = 0; | |
691 | ||
692 | /* reset / PCIe ready */ | |
693 | max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */ | |
694 | do { | |
695 | udelay(1); | |
696 | value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); | |
697 | } while ((value == 0xFFFFFFFF) && (--max_wait_count)); | |
698 | ||
699 | /* check ila status */ | |
700 | max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */ | |
701 | do { | |
702 | udelay(1); | |
703 | value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); | |
704 | } while (((value & SCRATCH_PAD_ILA_READY) != | |
705 | SCRATCH_PAD_ILA_READY) && (--max_wait_count)); | |
706 | if (!max_wait_count) | |
707 | ret = -1; | |
708 | else { | |
709 | PM8001_MSG_DBG(pm8001_ha, | |
710 | pm8001_printk(" ila ready status in %d millisec\n", | |
711 | (max_wait_time - max_wait_count))); | |
712 | } | |
713 | ||
714 | /* check RAAE status */ | |
715 | max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */ | |
716 | do { | |
717 | udelay(1); | |
718 | value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); | |
719 | } while (((value & SCRATCH_PAD_RAAE_READY) != | |
720 | SCRATCH_PAD_RAAE_READY) && (--max_wait_count)); | |
721 | if (!max_wait_count) | |
722 | ret = -1; | |
723 | else { | |
724 | PM8001_MSG_DBG(pm8001_ha, | |
725 | pm8001_printk(" raae ready status in %d millisec\n", | |
726 | (max_wait_time - max_wait_count))); | |
727 | } | |
728 | ||
729 | /* check iop0 status */ | |
730 | max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */ | |
731 | do { | |
732 | udelay(1); | |
733 | value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); | |
734 | } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) && | |
735 | (--max_wait_count)); | |
736 | if (!max_wait_count) | |
737 | ret = -1; | |
738 | else { | |
739 | PM8001_MSG_DBG(pm8001_ha, | |
740 | pm8001_printk(" iop0 ready status in %d millisec\n", | |
741 | (max_wait_time - max_wait_count))); | |
742 | } | |
743 | ||
744 | /* check iop1 status only for 16 port controllers */ | |
745 | if ((pm8001_ha->chip_id != chip_8008) && | |
746 | (pm8001_ha->chip_id != chip_8009)) { | |
747 | /* 200 milli sec */ | |
748 | max_wait_time = max_wait_count = 200 * 1000; | |
749 | do { | |
750 | udelay(1); | |
751 | value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); | |
752 | } while (((value & SCRATCH_PAD_IOP1_READY) != | |
753 | SCRATCH_PAD_IOP1_READY) && (--max_wait_count)); | |
754 | if (!max_wait_count) | |
755 | ret = -1; | |
756 | else { | |
757 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
758 | "iop1 ready status in %d millisec\n", | |
759 | (max_wait_time - max_wait_count))); | |
760 | } | |
761 | } | |
762 | ||
763 | return ret; | |
764 | } | |
765 | ||
766 | static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) | |
767 | { | |
768 | void __iomem *base_addr; | |
769 | u32 value; | |
770 | u32 offset; | |
771 | u32 pcibar; | |
772 | u32 pcilogic; | |
773 | ||
774 | value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); | |
775 | offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */ | |
776 | ||
777 | PM8001_INIT_DBG(pm8001_ha, | |
778 | pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n", | |
779 | offset, value)); | |
780 | pcilogic = (value & 0xFC000000) >> 26; | |
781 | pcibar = get_pci_bar_index(pcilogic); | |
782 | PM8001_INIT_DBG(pm8001_ha, | |
783 | pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar)); | |
784 | pm8001_ha->main_cfg_tbl_addr = base_addr = | |
785 | pm8001_ha->io_mem[pcibar].memvirtaddr + offset; | |
786 | pm8001_ha->general_stat_tbl_addr = | |
787 | base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) & | |
788 | 0xFFFFFF); | |
789 | pm8001_ha->inbnd_q_tbl_addr = | |
790 | base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) & | |
791 | 0xFFFFFF); | |
792 | pm8001_ha->outbnd_q_tbl_addr = | |
793 | base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) & | |
794 | 0xFFFFFF); | |
795 | pm8001_ha->ivt_tbl_addr = | |
796 | base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) & | |
797 | 0xFFFFFF); | |
798 | pm8001_ha->pspa_q_tbl_addr = | |
799 | base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) & | |
800 | 0xFFFFFF); | |
d078b511 AKS |
801 | pm8001_ha->fatal_tbl_addr = |
802 | base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) & | |
803 | 0xFFFFFF); | |
f5860992 S |
804 | |
805 | PM8001_INIT_DBG(pm8001_ha, | |
806 | pm8001_printk("GST OFFSET 0x%x\n", | |
807 | pm8001_cr32(pm8001_ha, pcibar, offset + 0x18))); | |
808 | PM8001_INIT_DBG(pm8001_ha, | |
809 | pm8001_printk("INBND OFFSET 0x%x\n", | |
810 | pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C))); | |
811 | PM8001_INIT_DBG(pm8001_ha, | |
812 | pm8001_printk("OBND OFFSET 0x%x\n", | |
813 | pm8001_cr32(pm8001_ha, pcibar, offset + 0x20))); | |
814 | PM8001_INIT_DBG(pm8001_ha, | |
815 | pm8001_printk("IVT OFFSET 0x%x\n", | |
816 | pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C))); | |
817 | PM8001_INIT_DBG(pm8001_ha, | |
818 | pm8001_printk("PSPA OFFSET 0x%x\n", | |
819 | pm8001_cr32(pm8001_ha, pcibar, offset + 0x90))); | |
820 | PM8001_INIT_DBG(pm8001_ha, | |
821 | pm8001_printk("addr - main cfg %p general status %p\n", | |
822 | pm8001_ha->main_cfg_tbl_addr, | |
823 | pm8001_ha->general_stat_tbl_addr)); | |
824 | PM8001_INIT_DBG(pm8001_ha, | |
825 | pm8001_printk("addr - inbnd %p obnd %p\n", | |
826 | pm8001_ha->inbnd_q_tbl_addr, | |
827 | pm8001_ha->outbnd_q_tbl_addr)); | |
828 | PM8001_INIT_DBG(pm8001_ha, | |
829 | pm8001_printk("addr - pspa %p ivt %p\n", | |
830 | pm8001_ha->pspa_q_tbl_addr, | |
831 | pm8001_ha->ivt_tbl_addr)); | |
832 | } | |
833 | ||
834 | /** | |
835 | * pm80xx_set_thermal_config - support the thermal configuration | |
836 | * @pm8001_ha: our hba card information. | |
837 | */ | |
a6cb3d01 | 838 | int |
f5860992 S |
839 | pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha) |
840 | { | |
841 | struct set_ctrl_cfg_req payload; | |
842 | struct inbound_queue_table *circularQ; | |
843 | int rc; | |
844 | u32 tag; | |
845 | u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; | |
846 | ||
847 | memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); | |
848 | rc = pm8001_tag_alloc(pm8001_ha, &tag); | |
849 | if (rc) | |
850 | return -1; | |
851 | ||
852 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; | |
853 | payload.tag = cpu_to_le32(tag); | |
854 | payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) | | |
855 | (THERMAL_ENABLE << 8) | THERMAL_OP_CODE; | |
856 | payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8); | |
857 | ||
858 | rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); | |
5533abca TH |
859 | if (rc) |
860 | pm8001_tag_free(pm8001_ha, tag); | |
f5860992 S |
861 | return rc; |
862 | ||
863 | } | |
864 | ||
a6cb3d01 S |
865 | /** |
866 | * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol | |
867 | * Timer configuration page | |
868 | * @pm8001_ha: our hba card information. | |
869 | */ | |
870 | static int | |
871 | pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha) | |
872 | { | |
873 | struct set_ctrl_cfg_req payload; | |
874 | struct inbound_queue_table *circularQ; | |
875 | SASProtocolTimerConfig_t SASConfigPage; | |
876 | int rc; | |
877 | u32 tag; | |
878 | u32 opc = OPC_INB_SET_CONTROLLER_CONFIG; | |
879 | ||
880 | memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); | |
881 | memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t)); | |
882 | ||
883 | rc = pm8001_tag_alloc(pm8001_ha, &tag); | |
884 | ||
885 | if (rc) | |
886 | return -1; | |
887 | ||
888 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; | |
889 | payload.tag = cpu_to_le32(tag); | |
890 | ||
891 | SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE; | |
892 | SASConfigPage.MST_MSI = 3 << 15; | |
893 | SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO; | |
894 | SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) | | |
895 | (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER; | |
896 | SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME; | |
897 | ||
898 | if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF) | |
899 | SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF; | |
900 | ||
901 | ||
902 | SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) | | |
903 | SAS_OPNRJT_RTRY_INTVL; | |
904 | SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16) | |
905 | | SAS_COPNRJT_RTRY_TMO; | |
906 | SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16) | |
907 | | SAS_COPNRJT_RTRY_THR; | |
908 | SASConfigPage.MAX_AIP = SAS_MAX_AIP; | |
909 | ||
910 | PM8001_INIT_DBG(pm8001_ha, | |
911 | pm8001_printk("SASConfigPage.pageCode " | |
912 | "0x%08x\n", SASConfigPage.pageCode)); | |
913 | PM8001_INIT_DBG(pm8001_ha, | |
914 | pm8001_printk("SASConfigPage.MST_MSI " | |
915 | " 0x%08x\n", SASConfigPage.MST_MSI)); | |
916 | PM8001_INIT_DBG(pm8001_ha, | |
917 | pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO " | |
918 | " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO)); | |
919 | PM8001_INIT_DBG(pm8001_ha, | |
920 | pm8001_printk("SASConfigPage.STP_FRM_TMO " | |
921 | " 0x%08x\n", SASConfigPage.STP_FRM_TMO)); | |
922 | PM8001_INIT_DBG(pm8001_ha, | |
923 | pm8001_printk("SASConfigPage.STP_IDLE_TMO " | |
924 | " 0x%08x\n", SASConfigPage.STP_IDLE_TMO)); | |
925 | PM8001_INIT_DBG(pm8001_ha, | |
926 | pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL " | |
927 | " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL)); | |
928 | PM8001_INIT_DBG(pm8001_ha, | |
929 | pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO " | |
930 | " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO)); | |
931 | PM8001_INIT_DBG(pm8001_ha, | |
932 | pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR " | |
933 | " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR)); | |
934 | PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP " | |
935 | " 0x%08x\n", SASConfigPage.MAX_AIP)); | |
936 | ||
937 | memcpy(&payload.cfg_pg, &SASConfigPage, | |
938 | sizeof(SASProtocolTimerConfig_t)); | |
939 | ||
940 | rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); | |
5533abca TH |
941 | if (rc) |
942 | pm8001_tag_free(pm8001_ha, tag); | |
a6cb3d01 S |
943 | |
944 | return rc; | |
945 | } | |
946 | ||
f5860992 S |
947 | /** |
948 | * pm80xx_get_encrypt_info - Check for encryption | |
949 | * @pm8001_ha: our hba card information. | |
950 | */ | |
951 | static int | |
952 | pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha) | |
953 | { | |
954 | u32 scratch3_value; | |
da225498 | 955 | int ret = -1; |
f5860992 S |
956 | |
957 | /* Read encryption status from SCRATCH PAD 3 */ | |
958 | scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); | |
959 | ||
960 | if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == | |
961 | SCRATCH_PAD3_ENC_READY) { | |
962 | if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) | |
963 | pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; | |
964 | if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == | |
965 | SCRATCH_PAD3_SMF_ENABLED) | |
966 | pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; | |
967 | if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == | |
968 | SCRATCH_PAD3_SMA_ENABLED) | |
969 | pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; | |
970 | if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == | |
971 | SCRATCH_PAD3_SMB_ENABLED) | |
972 | pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; | |
973 | pm8001_ha->encrypt_info.status = 0; | |
974 | PM8001_INIT_DBG(pm8001_ha, pm8001_printk( | |
975 | "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X." | |
976 | "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n", | |
977 | scratch3_value, pm8001_ha->encrypt_info.cipher_mode, | |
978 | pm8001_ha->encrypt_info.sec_mode, | |
979 | pm8001_ha->encrypt_info.status)); | |
980 | ret = 0; | |
981 | } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) == | |
982 | SCRATCH_PAD3_ENC_DISABLED) { | |
983 | PM8001_INIT_DBG(pm8001_ha, pm8001_printk( | |
984 | "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n", | |
985 | scratch3_value)); | |
986 | pm8001_ha->encrypt_info.status = 0xFFFFFFFF; | |
987 | pm8001_ha->encrypt_info.cipher_mode = 0; | |
988 | pm8001_ha->encrypt_info.sec_mode = 0; | |
da225498 | 989 | ret = 0; |
f5860992 S |
990 | } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == |
991 | SCRATCH_PAD3_ENC_DIS_ERR) { | |
992 | pm8001_ha->encrypt_info.status = | |
993 | (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; | |
994 | if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) | |
995 | pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; | |
996 | if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == | |
997 | SCRATCH_PAD3_SMF_ENABLED) | |
998 | pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; | |
999 | if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == | |
1000 | SCRATCH_PAD3_SMA_ENABLED) | |
1001 | pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; | |
1002 | if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == | |
1003 | SCRATCH_PAD3_SMB_ENABLED) | |
1004 | pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; | |
1005 | PM8001_INIT_DBG(pm8001_ha, pm8001_printk( | |
1006 | "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X." | |
1007 | "Cipher mode 0x%x sec mode 0x%x status 0x%x\n", | |
1008 | scratch3_value, pm8001_ha->encrypt_info.cipher_mode, | |
1009 | pm8001_ha->encrypt_info.sec_mode, | |
1010 | pm8001_ha->encrypt_info.status)); | |
f5860992 S |
1011 | } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) == |
1012 | SCRATCH_PAD3_ENC_ENA_ERR) { | |
1013 | ||
1014 | pm8001_ha->encrypt_info.status = | |
1015 | (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16; | |
1016 | if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED) | |
1017 | pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; | |
1018 | if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == | |
1019 | SCRATCH_PAD3_SMF_ENABLED) | |
1020 | pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; | |
1021 | if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == | |
1022 | SCRATCH_PAD3_SMA_ENABLED) | |
1023 | pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; | |
1024 | if ((scratch3_value & SCRATCH_PAD3_SM_MASK) == | |
1025 | SCRATCH_PAD3_SMB_ENABLED) | |
1026 | pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; | |
1027 | ||
1028 | PM8001_INIT_DBG(pm8001_ha, pm8001_printk( | |
1029 | "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X." | |
1030 | "Cipher mode 0x%x sec mode 0x%x status 0x%x\n", | |
1031 | scratch3_value, pm8001_ha->encrypt_info.cipher_mode, | |
1032 | pm8001_ha->encrypt_info.sec_mode, | |
1033 | pm8001_ha->encrypt_info.status)); | |
f5860992 S |
1034 | } |
1035 | return ret; | |
1036 | } | |
1037 | ||
1038 | /** | |
1039 | * pm80xx_encrypt_update - update flash with encryption informtion | |
1040 | * @pm8001_ha: our hba card information. | |
1041 | */ | |
1042 | static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha) | |
1043 | { | |
1044 | struct kek_mgmt_req payload; | |
1045 | struct inbound_queue_table *circularQ; | |
1046 | int rc; | |
1047 | u32 tag; | |
1048 | u32 opc = OPC_INB_KEK_MANAGEMENT; | |
1049 | ||
1050 | memset(&payload, 0, sizeof(struct kek_mgmt_req)); | |
1051 | rc = pm8001_tag_alloc(pm8001_ha, &tag); | |
1052 | if (rc) | |
1053 | return -1; | |
1054 | ||
1055 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; | |
1056 | payload.tag = cpu_to_le32(tag); | |
1057 | /* Currently only one key is used. New KEK index is 1. | |
1058 | * Current KEK index is 1. Store KEK to NVRAM is 1. | |
1059 | */ | |
1060 | payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) | | |
1061 | KEK_MGMT_SUBOP_KEYCARDUPDATE); | |
1062 | ||
1063 | rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); | |
5533abca TH |
1064 | if (rc) |
1065 | pm8001_tag_free(pm8001_ha, tag); | |
f5860992 S |
1066 | |
1067 | return rc; | |
1068 | } | |
1069 | ||
1070 | /** | |
1071 | * pm8001_chip_init - the main init function that initialize whole PM8001 chip. | |
1072 | * @pm8001_ha: our hba card information | |
1073 | */ | |
1074 | static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha) | |
1075 | { | |
1076 | int ret; | |
1077 | u8 i = 0; | |
1078 | ||
1079 | /* check the firmware status */ | |
1080 | if (-1 == check_fw_ready(pm8001_ha)) { | |
1081 | PM8001_FAIL_DBG(pm8001_ha, | |
1082 | pm8001_printk("Firmware is not ready!\n")); | |
1083 | return -EBUSY; | |
1084 | } | |
1085 | ||
1086 | /* Initialize pci space address eg: mpi offset */ | |
1087 | init_pci_device_addresses(pm8001_ha); | |
1088 | init_default_table_values(pm8001_ha); | |
1089 | read_main_config_table(pm8001_ha); | |
1090 | read_general_status_table(pm8001_ha); | |
1091 | read_inbnd_queue_table(pm8001_ha); | |
1092 | read_outbnd_queue_table(pm8001_ha); | |
1093 | read_phy_attr_table(pm8001_ha); | |
1094 | ||
1095 | /* update main config table ,inbound table and outbound table */ | |
1096 | update_main_config_table(pm8001_ha); | |
1097 | for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) | |
1098 | update_inbnd_queue_table(pm8001_ha, i); | |
1099 | for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) | |
1100 | update_outbnd_queue_table(pm8001_ha, i); | |
1101 | ||
1102 | /* notify firmware update finished and check initialization status */ | |
1103 | if (0 == mpi_init_check(pm8001_ha)) { | |
1104 | PM8001_INIT_DBG(pm8001_ha, | |
1105 | pm8001_printk("MPI initialize successful!\n")); | |
1106 | } else | |
1107 | return -EBUSY; | |
1108 | ||
a6cb3d01 S |
1109 | /* send SAS protocol timer configuration page to FW */ |
1110 | ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha); | |
f5860992 S |
1111 | |
1112 | /* Check for encryption */ | |
1113 | if (pm8001_ha->chip->encrypt) { | |
1114 | PM8001_INIT_DBG(pm8001_ha, | |
1115 | pm8001_printk("Checking for encryption\n")); | |
1116 | ret = pm80xx_get_encrypt_info(pm8001_ha); | |
1117 | if (ret == -1) { | |
1118 | PM8001_INIT_DBG(pm8001_ha, | |
1119 | pm8001_printk("Encryption error !!\n")); | |
1120 | if (pm8001_ha->encrypt_info.status == 0x81) { | |
1121 | PM8001_INIT_DBG(pm8001_ha, pm8001_printk( | |
1122 | "Encryption enabled with error." | |
1123 | "Saving encryption key to flash\n")); | |
1124 | pm80xx_encrypt_update(pm8001_ha); | |
1125 | } | |
1126 | } | |
1127 | } | |
1128 | return 0; | |
1129 | } | |
1130 | ||
1131 | static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) | |
1132 | { | |
1133 | u32 max_wait_count; | |
1134 | u32 value; | |
1135 | u32 gst_len_mpistate; | |
1136 | init_pci_device_addresses(pm8001_ha); | |
1137 | /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the | |
1138 | table is stop */ | |
1139 | pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET); | |
1140 | ||
1141 | /* wait until Inbound DoorBell Clear Register toggled */ | |
a9a923e5 AKS |
1142 | if (IS_SPCV_12G(pm8001_ha->pdev)) { |
1143 | max_wait_count = 4 * 1000 * 1000;/* 4 sec */ | |
1144 | } else { | |
1145 | max_wait_count = 2 * 1000 * 1000;/* 2 sec */ | |
1146 | } | |
f5860992 S |
1147 | do { |
1148 | udelay(1); | |
1149 | value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); | |
1150 | value &= SPCv_MSGU_CFG_TABLE_RESET; | |
1151 | } while ((value != 0) && (--max_wait_count)); | |
1152 | ||
1153 | if (!max_wait_count) { | |
1154 | PM8001_FAIL_DBG(pm8001_ha, | |
1155 | pm8001_printk("TIMEOUT:IBDB value/=%x\n", value)); | |
1156 | return -1; | |
1157 | } | |
1158 | ||
1159 | /* check the MPI-State for termination in progress */ | |
1160 | /* wait until Inbound DoorBell Clear Register toggled */ | |
1161 | max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */ | |
1162 | do { | |
1163 | udelay(1); | |
1164 | gst_len_mpistate = | |
1165 | pm8001_mr32(pm8001_ha->general_stat_tbl_addr, | |
1166 | GST_GSTLEN_MPIS_OFFSET); | |
1167 | if (GST_MPI_STATE_UNINIT == | |
1168 | (gst_len_mpistate & GST_MPI_STATE_MASK)) | |
1169 | break; | |
1170 | } while (--max_wait_count); | |
1171 | if (!max_wait_count) { | |
1172 | PM8001_FAIL_DBG(pm8001_ha, | |
1173 | pm8001_printk(" TIME OUT MPI State = 0x%x\n", | |
1174 | gst_len_mpistate & GST_MPI_STATE_MASK)); | |
1175 | return -1; | |
1176 | } | |
1177 | ||
1178 | return 0; | |
1179 | } | |
1180 | ||
1181 | /** | |
1182 | * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all | |
1183 | * the FW register status to the originated status. | |
1184 | * @pm8001_ha: our hba card information | |
1185 | */ | |
1186 | ||
1187 | static int | |
1188 | pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) | |
1189 | { | |
1190 | u32 regval; | |
1191 | u32 bootloader_state; | |
06f12f22 | 1192 | u32 ibutton0, ibutton1; |
f5860992 S |
1193 | |
1194 | /* Check if MPI is in ready state to reset */ | |
1195 | if (mpi_uninit_check(pm8001_ha) != 0) { | |
1196 | PM8001_FAIL_DBG(pm8001_ha, | |
1197 | pm8001_printk("MPI state is not ready\n")); | |
1198 | return -1; | |
1199 | } | |
1200 | ||
1201 | /* checked for reset register normal state; 0x0 */ | |
1202 | regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); | |
1203 | PM8001_INIT_DBG(pm8001_ha, | |
1204 | pm8001_printk("reset register before write : 0x%x\n", regval)); | |
1205 | ||
1206 | pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE); | |
1207 | mdelay(500); | |
1208 | ||
1209 | regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); | |
1210 | PM8001_INIT_DBG(pm8001_ha, | |
1211 | pm8001_printk("reset register after write 0x%x\n", regval)); | |
1212 | ||
1213 | if ((regval & SPCv_SOFT_RESET_READ_MASK) == | |
1214 | SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) { | |
1215 | PM8001_MSG_DBG(pm8001_ha, | |
1216 | pm8001_printk(" soft reset successful [regval: 0x%x]\n", | |
1217 | regval)); | |
1218 | } else { | |
1219 | PM8001_MSG_DBG(pm8001_ha, | |
1220 | pm8001_printk(" soft reset failed [regval: 0x%x]\n", | |
1221 | regval)); | |
1222 | ||
1223 | /* check bootloader is successfully executed or in HDA mode */ | |
1224 | bootloader_state = | |
1225 | pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & | |
1226 | SCRATCH_PAD1_BOOTSTATE_MASK; | |
1227 | ||
1228 | if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) { | |
1229 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
1230 | "Bootloader state - HDA mode SEEPROM\n")); | |
1231 | } else if (bootloader_state == | |
1232 | SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) { | |
1233 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
1234 | "Bootloader state - HDA mode Bootstrap Pin\n")); | |
1235 | } else if (bootloader_state == | |
1236 | SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) { | |
1237 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
1238 | "Bootloader state - HDA mode soft reset\n")); | |
1239 | } else if (bootloader_state == | |
1240 | SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) { | |
1241 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
1242 | "Bootloader state-HDA mode critical error\n")); | |
1243 | } | |
1244 | return -EBUSY; | |
1245 | } | |
1246 | ||
1247 | /* check the firmware status after reset */ | |
1248 | if (-1 == check_fw_ready(pm8001_ha)) { | |
1249 | PM8001_FAIL_DBG(pm8001_ha, | |
1250 | pm8001_printk("Firmware is not ready!\n")); | |
06f12f22 AKS |
1251 | /* check iButton feature support for motherboard controller */ |
1252 | if (pm8001_ha->pdev->subsystem_vendor != | |
1253 | PCI_VENDOR_ID_ADAPTEC2 && | |
1254 | pm8001_ha->pdev->subsystem_vendor != 0) { | |
1255 | ibutton0 = pm8001_cr32(pm8001_ha, 0, | |
1256 | MSGU_HOST_SCRATCH_PAD_6); | |
1257 | ibutton1 = pm8001_cr32(pm8001_ha, 0, | |
1258 | MSGU_HOST_SCRATCH_PAD_7); | |
1259 | if (!ibutton0 && !ibutton1) { | |
1260 | PM8001_FAIL_DBG(pm8001_ha, | |
1261 | pm8001_printk("iButton Feature is" | |
1262 | " not Available!!!\n")); | |
1263 | return -EBUSY; | |
1264 | } | |
1265 | if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) { | |
1266 | PM8001_FAIL_DBG(pm8001_ha, | |
1267 | pm8001_printk("CRC Check for iButton" | |
1268 | " Feature Failed!!!\n")); | |
1269 | return -EBUSY; | |
1270 | } | |
1271 | } | |
f5860992 S |
1272 | } |
1273 | PM8001_INIT_DBG(pm8001_ha, | |
1274 | pm8001_printk("SPCv soft reset Complete\n")); | |
1275 | return 0; | |
1276 | } | |
1277 | ||
1278 | static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) | |
1279 | { | |
1280 | u32 i; | |
1281 | ||
1282 | PM8001_INIT_DBG(pm8001_ha, | |
1283 | pm8001_printk("chip reset start\n")); | |
1284 | ||
1285 | /* do SPCv chip reset. */ | |
1286 | pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11); | |
1287 | PM8001_INIT_DBG(pm8001_ha, | |
1288 | pm8001_printk("SPC soft reset Complete\n")); | |
1289 | ||
1290 | /* Check this ..whether delay is required or no */ | |
1291 | /* delay 10 usec */ | |
1292 | udelay(10); | |
1293 | ||
1294 | /* wait for 20 msec until the firmware gets reloaded */ | |
1295 | i = 20; | |
1296 | do { | |
1297 | mdelay(1); | |
1298 | } while ((--i) != 0); | |
1299 | ||
1300 | PM8001_INIT_DBG(pm8001_ha, | |
1301 | pm8001_printk("chip reset finished\n")); | |
1302 | } | |
1303 | ||
1304 | /** | |
1305 | * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt | |
1306 | * @pm8001_ha: our hba card information | |
1307 | */ | |
1308 | static void | |
1309 | pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) | |
1310 | { | |
1311 | pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); | |
1312 | pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); | |
1313 | } | |
1314 | ||
1315 | /** | |
1316 | * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt | |
1317 | * @pm8001_ha: our hba card information | |
1318 | */ | |
1319 | static void | |
1320 | pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) | |
1321 | { | |
1322 | pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL); | |
1323 | } | |
1324 | ||
1325 | /** | |
1326 | * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt | |
1327 | * @pm8001_ha: our hba card information | |
1328 | */ | |
1329 | static void | |
1330 | pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) | |
1331 | { | |
1332 | #ifdef PM8001_USE_MSIX | |
1333 | u32 mask; | |
1334 | mask = (u32)(1 << vec); | |
1335 | ||
1336 | pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF)); | |
1337 | return; | |
1338 | #endif | |
1339 | pm80xx_chip_intx_interrupt_enable(pm8001_ha); | |
1340 | ||
1341 | } | |
1342 | ||
1343 | /** | |
1344 | * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt | |
1345 | * @pm8001_ha: our hba card information | |
1346 | */ | |
1347 | static void | |
1348 | pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) | |
1349 | { | |
1350 | #ifdef PM8001_USE_MSIX | |
1351 | u32 mask; | |
1352 | if (vec == 0xFF) | |
1353 | mask = 0xFFFFFFFF; | |
1354 | else | |
1355 | mask = (u32)(1 << vec); | |
1356 | pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF)); | |
1357 | return; | |
1358 | #endif | |
1359 | pm80xx_chip_intx_interrupt_disable(pm8001_ha); | |
1360 | } | |
1361 | ||
c6b9ef57 S |
1362 | static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha, |
1363 | struct pm8001_device *pm8001_ha_dev) | |
1364 | { | |
1365 | int res; | |
1366 | u32 ccb_tag; | |
1367 | struct pm8001_ccb_info *ccb; | |
1368 | struct sas_task *task = NULL; | |
1369 | struct task_abort_req task_abort; | |
1370 | struct inbound_queue_table *circularQ; | |
1371 | u32 opc = OPC_INB_SATA_ABORT; | |
1372 | int ret; | |
1373 | ||
1374 | if (!pm8001_ha_dev) { | |
1375 | PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n")); | |
1376 | return; | |
1377 | } | |
1378 | ||
1379 | task = sas_alloc_slow_task(GFP_ATOMIC); | |
1380 | ||
1381 | if (!task) { | |
1382 | PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot " | |
1383 | "allocate task\n")); | |
1384 | return; | |
1385 | } | |
1386 | ||
1387 | task->task_done = pm8001_task_done; | |
1388 | ||
1389 | res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); | |
5533abca TH |
1390 | if (res) { |
1391 | sas_free_task(task); | |
c6b9ef57 | 1392 | return; |
5533abca | 1393 | } |
c6b9ef57 S |
1394 | |
1395 | ccb = &pm8001_ha->ccb_info[ccb_tag]; | |
1396 | ccb->device = pm8001_ha_dev; | |
1397 | ccb->ccb_tag = ccb_tag; | |
1398 | ccb->task = task; | |
1399 | ||
1400 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; | |
1401 | ||
1402 | memset(&task_abort, 0, sizeof(task_abort)); | |
1403 | task_abort.abort_all = cpu_to_le32(1); | |
1404 | task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id); | |
1405 | task_abort.tag = cpu_to_le32(ccb_tag); | |
1406 | ||
1407 | ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0); | |
5533abca TH |
1408 | if (ret) { |
1409 | sas_free_task(task); | |
1410 | pm8001_tag_free(pm8001_ha, ccb_tag); | |
1411 | } | |
c6b9ef57 S |
1412 | } |
1413 | ||
1414 | static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha, | |
1415 | struct pm8001_device *pm8001_ha_dev) | |
1416 | { | |
1417 | struct sata_start_req sata_cmd; | |
1418 | int res; | |
1419 | u32 ccb_tag; | |
1420 | struct pm8001_ccb_info *ccb; | |
1421 | struct sas_task *task = NULL; | |
1422 | struct host_to_dev_fis fis; | |
1423 | struct domain_device *dev; | |
1424 | struct inbound_queue_table *circularQ; | |
1425 | u32 opc = OPC_INB_SATA_HOST_OPSTART; | |
1426 | ||
1427 | task = sas_alloc_slow_task(GFP_ATOMIC); | |
1428 | ||
1429 | if (!task) { | |
1430 | PM8001_FAIL_DBG(pm8001_ha, | |
1431 | pm8001_printk("cannot allocate task !!!\n")); | |
1432 | return; | |
1433 | } | |
1434 | task->task_done = pm8001_task_done; | |
1435 | ||
1436 | res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); | |
1437 | if (res) { | |
5533abca | 1438 | sas_free_task(task); |
c6b9ef57 S |
1439 | PM8001_FAIL_DBG(pm8001_ha, |
1440 | pm8001_printk("cannot allocate tag !!!\n")); | |
1441 | return; | |
1442 | } | |
1443 | ||
1444 | /* allocate domain device by ourselves as libsas | |
1445 | * is not going to provide any | |
1446 | */ | |
1447 | dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC); | |
1448 | if (!dev) { | |
5533abca TH |
1449 | sas_free_task(task); |
1450 | pm8001_tag_free(pm8001_ha, ccb_tag); | |
c6b9ef57 S |
1451 | PM8001_FAIL_DBG(pm8001_ha, |
1452 | pm8001_printk("Domain device cannot be allocated\n")); | |
c6b9ef57 | 1453 | return; |
c6b9ef57 S |
1454 | } |
1455 | ||
5533abca TH |
1456 | task->dev = dev; |
1457 | task->dev->lldd_dev = pm8001_ha_dev; | |
1458 | ||
c6b9ef57 S |
1459 | ccb = &pm8001_ha->ccb_info[ccb_tag]; |
1460 | ccb->device = pm8001_ha_dev; | |
1461 | ccb->ccb_tag = ccb_tag; | |
1462 | ccb->task = task; | |
1463 | pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG; | |
1464 | pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG; | |
1465 | ||
1466 | memset(&sata_cmd, 0, sizeof(sata_cmd)); | |
1467 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; | |
1468 | ||
1469 | /* construct read log FIS */ | |
1470 | memset(&fis, 0, sizeof(struct host_to_dev_fis)); | |
1471 | fis.fis_type = 0x27; | |
1472 | fis.flags = 0x80; | |
1473 | fis.command = ATA_CMD_READ_LOG_EXT; | |
1474 | fis.lbal = 0x10; | |
1475 | fis.sector_count = 0x1; | |
1476 | ||
1477 | sata_cmd.tag = cpu_to_le32(ccb_tag); | |
1478 | sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); | |
1479 | sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9)); | |
1480 | memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis)); | |
1481 | ||
1482 | res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0); | |
5533abca TH |
1483 | if (res) { |
1484 | sas_free_task(task); | |
1485 | pm8001_tag_free(pm8001_ha, ccb_tag); | |
1486 | kfree(dev); | |
1487 | } | |
c6b9ef57 S |
1488 | } |
1489 | ||
f5860992 S |
1490 | /** |
1491 | * mpi_ssp_completion- process the event that FW response to the SSP request. | |
1492 | * @pm8001_ha: our hba card information | |
1493 | * @piomb: the message contents of this outbound message. | |
1494 | * | |
1495 | * When FW has completed a ssp request for example a IO request, after it has | |
1496 | * filled the SG data with the data, it will trigger this event represent | |
1497 | * that he has finished the job,please check the coresponding buffer. | |
1498 | * So we will tell the caller who maybe waiting the result to tell upper layer | |
1499 | * that the task has been finished. | |
1500 | */ | |
1501 | static void | |
1502 | mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb) | |
1503 | { | |
1504 | struct sas_task *t; | |
1505 | struct pm8001_ccb_info *ccb; | |
1506 | unsigned long flags; | |
1507 | u32 status; | |
1508 | u32 param; | |
1509 | u32 tag; | |
1510 | struct ssp_completion_resp *psspPayload; | |
1511 | struct task_status_struct *ts; | |
1512 | struct ssp_response_iu *iu; | |
1513 | struct pm8001_device *pm8001_dev; | |
1514 | psspPayload = (struct ssp_completion_resp *)(piomb + 4); | |
1515 | status = le32_to_cpu(psspPayload->status); | |
1516 | tag = le32_to_cpu(psspPayload->tag); | |
1517 | ccb = &pm8001_ha->ccb_info[tag]; | |
1518 | if ((status == IO_ABORTED) && ccb->open_retry) { | |
1519 | /* Being completed by another */ | |
1520 | ccb->open_retry = 0; | |
1521 | return; | |
1522 | } | |
1523 | pm8001_dev = ccb->device; | |
1524 | param = le32_to_cpu(psspPayload->param); | |
1525 | t = ccb->task; | |
1526 | ||
1527 | if (status && status != IO_UNDERFLOW) | |
1528 | PM8001_FAIL_DBG(pm8001_ha, | |
1529 | pm8001_printk("sas IO status 0x%x\n", status)); | |
1530 | if (unlikely(!t || !t->lldd_task || !t->dev)) | |
1531 | return; | |
1532 | ts = &t->task_status; | |
cb269c26 AKS |
1533 | /* Print sas address of IO failed device */ |
1534 | if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && | |
1535 | (status != IO_UNDERFLOW)) | |
1536 | PM8001_FAIL_DBG(pm8001_ha, | |
1537 | pm8001_printk("SAS Address of IO Failure Drive" | |
1538 | ":%016llx", SAS_ADDR(t->dev->sas_addr))); | |
1539 | ||
f5860992 S |
1540 | switch (status) { |
1541 | case IO_SUCCESS: | |
1542 | PM8001_IO_DBG(pm8001_ha, | |
1543 | pm8001_printk("IO_SUCCESS ,param = 0x%x\n", | |
1544 | param)); | |
1545 | if (param == 0) { | |
1546 | ts->resp = SAS_TASK_COMPLETE; | |
1547 | ts->stat = SAM_STAT_GOOD; | |
1548 | } else { | |
1549 | ts->resp = SAS_TASK_COMPLETE; | |
1550 | ts->stat = SAS_PROTO_RESPONSE; | |
1551 | ts->residual = param; | |
1552 | iu = &psspPayload->ssp_resp_iu; | |
1553 | sas_ssp_task_response(pm8001_ha->dev, t, iu); | |
1554 | } | |
1555 | if (pm8001_dev) | |
1556 | pm8001_dev->running_req--; | |
1557 | break; | |
1558 | case IO_ABORTED: | |
1559 | PM8001_IO_DBG(pm8001_ha, | |
1560 | pm8001_printk("IO_ABORTED IOMB Tag\n")); | |
1561 | ts->resp = SAS_TASK_COMPLETE; | |
1562 | ts->stat = SAS_ABORTED_TASK; | |
1563 | break; | |
1564 | case IO_UNDERFLOW: | |
1565 | /* SSP Completion with error */ | |
1566 | PM8001_IO_DBG(pm8001_ha, | |
1567 | pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n", | |
1568 | param)); | |
1569 | ts->resp = SAS_TASK_COMPLETE; | |
1570 | ts->stat = SAS_DATA_UNDERRUN; | |
1571 | ts->residual = param; | |
1572 | if (pm8001_dev) | |
1573 | pm8001_dev->running_req--; | |
1574 | break; | |
1575 | case IO_NO_DEVICE: | |
1576 | PM8001_IO_DBG(pm8001_ha, | |
1577 | pm8001_printk("IO_NO_DEVICE\n")); | |
1578 | ts->resp = SAS_TASK_UNDELIVERED; | |
1579 | ts->stat = SAS_PHY_DOWN; | |
1580 | break; | |
1581 | case IO_XFER_ERROR_BREAK: | |
1582 | PM8001_IO_DBG(pm8001_ha, | |
1583 | pm8001_printk("IO_XFER_ERROR_BREAK\n")); | |
1584 | ts->resp = SAS_TASK_COMPLETE; | |
1585 | ts->stat = SAS_OPEN_REJECT; | |
1586 | /* Force the midlayer to retry */ | |
1587 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
1588 | break; | |
1589 | case IO_XFER_ERROR_PHY_NOT_READY: | |
1590 | PM8001_IO_DBG(pm8001_ha, | |
1591 | pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); | |
1592 | ts->resp = SAS_TASK_COMPLETE; | |
1593 | ts->stat = SAS_OPEN_REJECT; | |
1594 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
1595 | break; | |
1596 | case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: | |
1597 | PM8001_IO_DBG(pm8001_ha, | |
1598 | pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); | |
1599 | ts->resp = SAS_TASK_COMPLETE; | |
1600 | ts->stat = SAS_OPEN_REJECT; | |
1601 | ts->open_rej_reason = SAS_OREJ_EPROTO; | |
1602 | break; | |
1603 | case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: | |
1604 | PM8001_IO_DBG(pm8001_ha, | |
1605 | pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); | |
1606 | ts->resp = SAS_TASK_COMPLETE; | |
1607 | ts->stat = SAS_OPEN_REJECT; | |
1608 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; | |
1609 | break; | |
1610 | case IO_OPEN_CNX_ERROR_BREAK: | |
1611 | PM8001_IO_DBG(pm8001_ha, | |
1612 | pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); | |
1613 | ts->resp = SAS_TASK_COMPLETE; | |
1614 | ts->stat = SAS_OPEN_REJECT; | |
1615 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
1616 | break; | |
1617 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: | |
a6cb3d01 S |
1618 | case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: |
1619 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: | |
1620 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: | |
1621 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: | |
1622 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: | |
f5860992 S |
1623 | PM8001_IO_DBG(pm8001_ha, |
1624 | pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); | |
1625 | ts->resp = SAS_TASK_COMPLETE; | |
1626 | ts->stat = SAS_OPEN_REJECT; | |
1627 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; | |
1628 | if (!t->uldd_task) | |
1629 | pm8001_handle_event(pm8001_ha, | |
1630 | pm8001_dev, | |
1631 | IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); | |
1632 | break; | |
1633 | case IO_OPEN_CNX_ERROR_BAD_DESTINATION: | |
1634 | PM8001_IO_DBG(pm8001_ha, | |
1635 | pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); | |
1636 | ts->resp = SAS_TASK_COMPLETE; | |
1637 | ts->stat = SAS_OPEN_REJECT; | |
1638 | ts->open_rej_reason = SAS_OREJ_BAD_DEST; | |
1639 | break; | |
1640 | case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: | |
1641 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
1642 | "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); | |
1643 | ts->resp = SAS_TASK_COMPLETE; | |
1644 | ts->stat = SAS_OPEN_REJECT; | |
1645 | ts->open_rej_reason = SAS_OREJ_CONN_RATE; | |
1646 | break; | |
1647 | case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: | |
1648 | PM8001_IO_DBG(pm8001_ha, | |
1649 | pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); | |
1650 | ts->resp = SAS_TASK_UNDELIVERED; | |
1651 | ts->stat = SAS_OPEN_REJECT; | |
1652 | ts->open_rej_reason = SAS_OREJ_WRONG_DEST; | |
1653 | break; | |
1654 | case IO_XFER_ERROR_NAK_RECEIVED: | |
1655 | PM8001_IO_DBG(pm8001_ha, | |
1656 | pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); | |
1657 | ts->resp = SAS_TASK_COMPLETE; | |
1658 | ts->stat = SAS_OPEN_REJECT; | |
1659 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
1660 | break; | |
1661 | case IO_XFER_ERROR_ACK_NAK_TIMEOUT: | |
1662 | PM8001_IO_DBG(pm8001_ha, | |
1663 | pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); | |
1664 | ts->resp = SAS_TASK_COMPLETE; | |
1665 | ts->stat = SAS_NAK_R_ERR; | |
1666 | break; | |
1667 | case IO_XFER_ERROR_DMA: | |
1668 | PM8001_IO_DBG(pm8001_ha, | |
1669 | pm8001_printk("IO_XFER_ERROR_DMA\n")); | |
1670 | ts->resp = SAS_TASK_COMPLETE; | |
1671 | ts->stat = SAS_OPEN_REJECT; | |
1672 | break; | |
1673 | case IO_XFER_OPEN_RETRY_TIMEOUT: | |
1674 | PM8001_IO_DBG(pm8001_ha, | |
1675 | pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); | |
1676 | ts->resp = SAS_TASK_COMPLETE; | |
1677 | ts->stat = SAS_OPEN_REJECT; | |
1678 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
1679 | break; | |
1680 | case IO_XFER_ERROR_OFFSET_MISMATCH: | |
1681 | PM8001_IO_DBG(pm8001_ha, | |
1682 | pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); | |
1683 | ts->resp = SAS_TASK_COMPLETE; | |
1684 | ts->stat = SAS_OPEN_REJECT; | |
1685 | break; | |
1686 | case IO_PORT_IN_RESET: | |
1687 | PM8001_IO_DBG(pm8001_ha, | |
1688 | pm8001_printk("IO_PORT_IN_RESET\n")); | |
1689 | ts->resp = SAS_TASK_COMPLETE; | |
1690 | ts->stat = SAS_OPEN_REJECT; | |
1691 | break; | |
1692 | case IO_DS_NON_OPERATIONAL: | |
1693 | PM8001_IO_DBG(pm8001_ha, | |
1694 | pm8001_printk("IO_DS_NON_OPERATIONAL\n")); | |
1695 | ts->resp = SAS_TASK_COMPLETE; | |
1696 | ts->stat = SAS_OPEN_REJECT; | |
1697 | if (!t->uldd_task) | |
1698 | pm8001_handle_event(pm8001_ha, | |
1699 | pm8001_dev, | |
1700 | IO_DS_NON_OPERATIONAL); | |
1701 | break; | |
1702 | case IO_DS_IN_RECOVERY: | |
1703 | PM8001_IO_DBG(pm8001_ha, | |
1704 | pm8001_printk("IO_DS_IN_RECOVERY\n")); | |
1705 | ts->resp = SAS_TASK_COMPLETE; | |
1706 | ts->stat = SAS_OPEN_REJECT; | |
1707 | break; | |
1708 | case IO_TM_TAG_NOT_FOUND: | |
1709 | PM8001_IO_DBG(pm8001_ha, | |
1710 | pm8001_printk("IO_TM_TAG_NOT_FOUND\n")); | |
1711 | ts->resp = SAS_TASK_COMPLETE; | |
1712 | ts->stat = SAS_OPEN_REJECT; | |
1713 | break; | |
1714 | case IO_SSP_EXT_IU_ZERO_LEN_ERROR: | |
1715 | PM8001_IO_DBG(pm8001_ha, | |
1716 | pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n")); | |
1717 | ts->resp = SAS_TASK_COMPLETE; | |
1718 | ts->stat = SAS_OPEN_REJECT; | |
1719 | break; | |
1720 | case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: | |
1721 | PM8001_IO_DBG(pm8001_ha, | |
1722 | pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); | |
1723 | ts->resp = SAS_TASK_COMPLETE; | |
1724 | ts->stat = SAS_OPEN_REJECT; | |
1725 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
1726 | break; | |
1727 | default: | |
1728 | PM8001_IO_DBG(pm8001_ha, | |
1729 | pm8001_printk("Unknown status 0x%x\n", status)); | |
1730 | /* not allowed case. Therefore, return failed status */ | |
1731 | ts->resp = SAS_TASK_COMPLETE; | |
1732 | ts->stat = SAS_OPEN_REJECT; | |
1733 | break; | |
1734 | } | |
1735 | PM8001_IO_DBG(pm8001_ha, | |
1736 | pm8001_printk("scsi_status = 0x%x\n ", | |
1737 | psspPayload->ssp_resp_iu.status)); | |
1738 | spin_lock_irqsave(&t->task_state_lock, flags); | |
1739 | t->task_state_flags &= ~SAS_TASK_STATE_PENDING; | |
1740 | t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; | |
1741 | t->task_state_flags |= SAS_TASK_STATE_DONE; | |
1742 | if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { | |
1743 | spin_unlock_irqrestore(&t->task_state_lock, flags); | |
1744 | PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( | |
1745 | "task 0x%p done with io_status 0x%x resp 0x%x " | |
1746 | "stat 0x%x but aborted by upper layer!\n", | |
1747 | t, status, ts->resp, ts->stat)); | |
1748 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); | |
1749 | } else { | |
1750 | spin_unlock_irqrestore(&t->task_state_lock, flags); | |
1751 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); | |
1752 | mb();/* in order to force CPU ordering */ | |
1753 | t->task_done(t); | |
1754 | } | |
1755 | } | |
1756 | ||
1757 | /*See the comments for mpi_ssp_completion */ | |
1758 | static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb) | |
1759 | { | |
1760 | struct sas_task *t; | |
1761 | unsigned long flags; | |
1762 | struct task_status_struct *ts; | |
1763 | struct pm8001_ccb_info *ccb; | |
1764 | struct pm8001_device *pm8001_dev; | |
1765 | struct ssp_event_resp *psspPayload = | |
1766 | (struct ssp_event_resp *)(piomb + 4); | |
1767 | u32 event = le32_to_cpu(psspPayload->event); | |
1768 | u32 tag = le32_to_cpu(psspPayload->tag); | |
1769 | u32 port_id = le32_to_cpu(psspPayload->port_id); | |
1770 | ||
1771 | ccb = &pm8001_ha->ccb_info[tag]; | |
1772 | t = ccb->task; | |
1773 | pm8001_dev = ccb->device; | |
1774 | if (event) | |
1775 | PM8001_FAIL_DBG(pm8001_ha, | |
1776 | pm8001_printk("sas IO status 0x%x\n", event)); | |
1777 | if (unlikely(!t || !t->lldd_task || !t->dev)) | |
1778 | return; | |
1779 | ts = &t->task_status; | |
1780 | PM8001_IO_DBG(pm8001_ha, | |
1781 | pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n", | |
1782 | port_id, tag, event)); | |
1783 | switch (event) { | |
1784 | case IO_OVERFLOW: | |
1785 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");) | |
1786 | ts->resp = SAS_TASK_COMPLETE; | |
1787 | ts->stat = SAS_DATA_OVERRUN; | |
1788 | ts->residual = 0; | |
1789 | if (pm8001_dev) | |
1790 | pm8001_dev->running_req--; | |
1791 | break; | |
1792 | case IO_XFER_ERROR_BREAK: | |
1793 | PM8001_IO_DBG(pm8001_ha, | |
1794 | pm8001_printk("IO_XFER_ERROR_BREAK\n")); | |
1795 | pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); | |
1796 | return; | |
1797 | case IO_XFER_ERROR_PHY_NOT_READY: | |
1798 | PM8001_IO_DBG(pm8001_ha, | |
1799 | pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); | |
1800 | ts->resp = SAS_TASK_COMPLETE; | |
1801 | ts->stat = SAS_OPEN_REJECT; | |
1802 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
1803 | break; | |
1804 | case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: | |
1805 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
1806 | "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); | |
1807 | ts->resp = SAS_TASK_COMPLETE; | |
1808 | ts->stat = SAS_OPEN_REJECT; | |
1809 | ts->open_rej_reason = SAS_OREJ_EPROTO; | |
1810 | break; | |
1811 | case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: | |
1812 | PM8001_IO_DBG(pm8001_ha, | |
1813 | pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); | |
1814 | ts->resp = SAS_TASK_COMPLETE; | |
1815 | ts->stat = SAS_OPEN_REJECT; | |
1816 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; | |
1817 | break; | |
1818 | case IO_OPEN_CNX_ERROR_BREAK: | |
1819 | PM8001_IO_DBG(pm8001_ha, | |
1820 | pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); | |
1821 | ts->resp = SAS_TASK_COMPLETE; | |
1822 | ts->stat = SAS_OPEN_REJECT; | |
1823 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
1824 | break; | |
1825 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: | |
a6cb3d01 S |
1826 | case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: |
1827 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: | |
1828 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: | |
1829 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: | |
1830 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: | |
f5860992 S |
1831 | PM8001_IO_DBG(pm8001_ha, |
1832 | pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); | |
1833 | ts->resp = SAS_TASK_COMPLETE; | |
1834 | ts->stat = SAS_OPEN_REJECT; | |
1835 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; | |
1836 | if (!t->uldd_task) | |
1837 | pm8001_handle_event(pm8001_ha, | |
1838 | pm8001_dev, | |
1839 | IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); | |
1840 | break; | |
1841 | case IO_OPEN_CNX_ERROR_BAD_DESTINATION: | |
1842 | PM8001_IO_DBG(pm8001_ha, | |
1843 | pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); | |
1844 | ts->resp = SAS_TASK_COMPLETE; | |
1845 | ts->stat = SAS_OPEN_REJECT; | |
1846 | ts->open_rej_reason = SAS_OREJ_BAD_DEST; | |
1847 | break; | |
1848 | case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: | |
1849 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
1850 | "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); | |
1851 | ts->resp = SAS_TASK_COMPLETE; | |
1852 | ts->stat = SAS_OPEN_REJECT; | |
1853 | ts->open_rej_reason = SAS_OREJ_CONN_RATE; | |
1854 | break; | |
1855 | case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: | |
1856 | PM8001_IO_DBG(pm8001_ha, | |
1857 | pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); | |
1858 | ts->resp = SAS_TASK_COMPLETE; | |
1859 | ts->stat = SAS_OPEN_REJECT; | |
1860 | ts->open_rej_reason = SAS_OREJ_WRONG_DEST; | |
1861 | break; | |
1862 | case IO_XFER_ERROR_NAK_RECEIVED: | |
1863 | PM8001_IO_DBG(pm8001_ha, | |
1864 | pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); | |
1865 | ts->resp = SAS_TASK_COMPLETE; | |
1866 | ts->stat = SAS_OPEN_REJECT; | |
1867 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
1868 | break; | |
1869 | case IO_XFER_ERROR_ACK_NAK_TIMEOUT: | |
1870 | PM8001_IO_DBG(pm8001_ha, | |
1871 | pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); | |
1872 | ts->resp = SAS_TASK_COMPLETE; | |
1873 | ts->stat = SAS_NAK_R_ERR; | |
1874 | break; | |
1875 | case IO_XFER_OPEN_RETRY_TIMEOUT: | |
1876 | PM8001_IO_DBG(pm8001_ha, | |
1877 | pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); | |
1878 | pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); | |
1879 | return; | |
1880 | case IO_XFER_ERROR_UNEXPECTED_PHASE: | |
1881 | PM8001_IO_DBG(pm8001_ha, | |
1882 | pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); | |
1883 | ts->resp = SAS_TASK_COMPLETE; | |
1884 | ts->stat = SAS_DATA_OVERRUN; | |
1885 | break; | |
1886 | case IO_XFER_ERROR_XFER_RDY_OVERRUN: | |
1887 | PM8001_IO_DBG(pm8001_ha, | |
1888 | pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); | |
1889 | ts->resp = SAS_TASK_COMPLETE; | |
1890 | ts->stat = SAS_DATA_OVERRUN; | |
1891 | break; | |
1892 | case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: | |
1893 | PM8001_IO_DBG(pm8001_ha, | |
1894 | pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); | |
1895 | ts->resp = SAS_TASK_COMPLETE; | |
1896 | ts->stat = SAS_DATA_OVERRUN; | |
1897 | break; | |
1898 | case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: | |
1899 | PM8001_IO_DBG(pm8001_ha, | |
1900 | pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n")); | |
1901 | ts->resp = SAS_TASK_COMPLETE; | |
1902 | ts->stat = SAS_DATA_OVERRUN; | |
1903 | break; | |
1904 | case IO_XFER_ERROR_OFFSET_MISMATCH: | |
1905 | PM8001_IO_DBG(pm8001_ha, | |
1906 | pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); | |
1907 | ts->resp = SAS_TASK_COMPLETE; | |
1908 | ts->stat = SAS_DATA_OVERRUN; | |
1909 | break; | |
1910 | case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: | |
1911 | PM8001_IO_DBG(pm8001_ha, | |
1912 | pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); | |
1913 | ts->resp = SAS_TASK_COMPLETE; | |
1914 | ts->stat = SAS_DATA_OVERRUN; | |
1915 | break; | |
a6cb3d01 S |
1916 | case IO_XFER_ERROR_INTERNAL_CRC_ERROR: |
1917 | PM8001_IO_DBG(pm8001_ha, | |
1918 | pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n")); | |
1919 | /* TBC: used default set values */ | |
1920 | ts->resp = SAS_TASK_COMPLETE; | |
1921 | ts->stat = SAS_DATA_OVERRUN; | |
1922 | break; | |
f5860992 S |
1923 | case IO_XFER_CMD_FRAME_ISSUED: |
1924 | PM8001_IO_DBG(pm8001_ha, | |
1925 | pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n")); | |
1926 | return; | |
1927 | default: | |
1928 | PM8001_IO_DBG(pm8001_ha, | |
1929 | pm8001_printk("Unknown status 0x%x\n", event)); | |
1930 | /* not allowed case. Therefore, return failed status */ | |
1931 | ts->resp = SAS_TASK_COMPLETE; | |
1932 | ts->stat = SAS_DATA_OVERRUN; | |
1933 | break; | |
1934 | } | |
1935 | spin_lock_irqsave(&t->task_state_lock, flags); | |
1936 | t->task_state_flags &= ~SAS_TASK_STATE_PENDING; | |
1937 | t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; | |
1938 | t->task_state_flags |= SAS_TASK_STATE_DONE; | |
1939 | if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { | |
1940 | spin_unlock_irqrestore(&t->task_state_lock, flags); | |
1941 | PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( | |
1942 | "task 0x%p done with event 0x%x resp 0x%x " | |
1943 | "stat 0x%x but aborted by upper layer!\n", | |
1944 | t, event, ts->resp, ts->stat)); | |
1945 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); | |
1946 | } else { | |
1947 | spin_unlock_irqrestore(&t->task_state_lock, flags); | |
1948 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); | |
1949 | mb();/* in order to force CPU ordering */ | |
1950 | t->task_done(t); | |
1951 | } | |
1952 | } | |
1953 | ||
1954 | /*See the comments for mpi_ssp_completion */ | |
1955 | static void | |
1956 | mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) | |
1957 | { | |
1958 | struct sas_task *t; | |
1959 | struct pm8001_ccb_info *ccb; | |
1960 | u32 param; | |
1961 | u32 status; | |
1962 | u32 tag; | |
cb269c26 AKS |
1963 | int i, j; |
1964 | u8 sata_addr_low[4]; | |
1965 | u32 temp_sata_addr_low, temp_sata_addr_hi; | |
1966 | u8 sata_addr_hi[4]; | |
f5860992 S |
1967 | struct sata_completion_resp *psataPayload; |
1968 | struct task_status_struct *ts; | |
1969 | struct ata_task_resp *resp ; | |
1970 | u32 *sata_resp; | |
1971 | struct pm8001_device *pm8001_dev; | |
c6b9ef57 | 1972 | unsigned long flags; |
f5860992 S |
1973 | |
1974 | psataPayload = (struct sata_completion_resp *)(piomb + 4); | |
1975 | status = le32_to_cpu(psataPayload->status); | |
1976 | tag = le32_to_cpu(psataPayload->tag); | |
1977 | ||
c6b9ef57 S |
1978 | if (!tag) { |
1979 | PM8001_FAIL_DBG(pm8001_ha, | |
1980 | pm8001_printk("tag null\n")); | |
1981 | return; | |
1982 | } | |
f5860992 S |
1983 | ccb = &pm8001_ha->ccb_info[tag]; |
1984 | param = le32_to_cpu(psataPayload->param); | |
c6b9ef57 S |
1985 | if (ccb) { |
1986 | t = ccb->task; | |
1987 | pm8001_dev = ccb->device; | |
1988 | } else { | |
1989 | PM8001_FAIL_DBG(pm8001_ha, | |
1990 | pm8001_printk("ccb null\n")); | |
1991 | return; | |
1992 | } | |
1993 | ||
1994 | if (t) { | |
1995 | if (t->dev && (t->dev->lldd_dev)) | |
1996 | pm8001_dev = t->dev->lldd_dev; | |
1997 | } else { | |
1998 | PM8001_FAIL_DBG(pm8001_ha, | |
1999 | pm8001_printk("task null\n")); | |
2000 | return; | |
2001 | } | |
2002 | ||
2003 | if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG)) | |
2004 | && unlikely(!t || !t->lldd_task || !t->dev)) { | |
2005 | PM8001_FAIL_DBG(pm8001_ha, | |
2006 | pm8001_printk("task or dev null\n")); | |
2007 | return; | |
2008 | } | |
2009 | ||
f5860992 | 2010 | ts = &t->task_status; |
c6b9ef57 | 2011 | if (!ts) { |
f5860992 | 2012 | PM8001_FAIL_DBG(pm8001_ha, |
c6b9ef57 | 2013 | pm8001_printk("ts null\n")); |
f5860992 | 2014 | return; |
c6b9ef57 | 2015 | } |
cb269c26 AKS |
2016 | /* Print sas address of IO failed device */ |
2017 | if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) && | |
2018 | (status != IO_UNDERFLOW)) { | |
2019 | if (!((t->dev->parent) && | |
2020 | (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) { | |
2021 | for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++) | |
2022 | sata_addr_low[i] = pm8001_ha->sas_addr[j]; | |
2023 | for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++) | |
2024 | sata_addr_hi[i] = pm8001_ha->sas_addr[j]; | |
2025 | memcpy(&temp_sata_addr_low, sata_addr_low, | |
2026 | sizeof(sata_addr_low)); | |
2027 | memcpy(&temp_sata_addr_hi, sata_addr_hi, | |
2028 | sizeof(sata_addr_hi)); | |
2029 | temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) | |
2030 | |((temp_sata_addr_hi << 8) & | |
2031 | 0xff0000) | | |
2032 | ((temp_sata_addr_hi >> 8) | |
2033 | & 0xff00) | | |
2034 | ((temp_sata_addr_hi << 24) & | |
2035 | 0xff000000)); | |
2036 | temp_sata_addr_low = ((((temp_sata_addr_low >> 24) | |
2037 | & 0xff) | | |
2038 | ((temp_sata_addr_low << 8) | |
2039 | & 0xff0000) | | |
2040 | ((temp_sata_addr_low >> 8) | |
2041 | & 0xff00) | | |
2042 | ((temp_sata_addr_low << 24) | |
2043 | & 0xff000000)) + | |
2044 | pm8001_dev->attached_phy + | |
2045 | 0x10); | |
2046 | PM8001_FAIL_DBG(pm8001_ha, | |
2047 | pm8001_printk("SAS Address of IO Failure Drive:" | |
2048 | "%08x%08x", temp_sata_addr_hi, | |
2049 | temp_sata_addr_low)); | |
f5860992 | 2050 | |
cb269c26 AKS |
2051 | } else { |
2052 | PM8001_FAIL_DBG(pm8001_ha, | |
2053 | pm8001_printk("SAS Address of IO Failure Drive:" | |
2054 | "%016llx", SAS_ADDR(t->dev->sas_addr))); | |
2055 | } | |
2056 | } | |
f5860992 S |
2057 | switch (status) { |
2058 | case IO_SUCCESS: | |
2059 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); | |
2060 | if (param == 0) { | |
2061 | ts->resp = SAS_TASK_COMPLETE; | |
2062 | ts->stat = SAM_STAT_GOOD; | |
c6b9ef57 S |
2063 | /* check if response is for SEND READ LOG */ |
2064 | if (pm8001_dev && | |
2065 | (pm8001_dev->id & NCQ_READ_LOG_FLAG)) { | |
2066 | /* set new bit for abort_all */ | |
2067 | pm8001_dev->id |= NCQ_ABORT_ALL_FLAG; | |
2068 | /* clear bit for read log */ | |
2069 | pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF; | |
2070 | pm80xx_send_abort_all(pm8001_ha, pm8001_dev); | |
2071 | /* Free the tag */ | |
2072 | pm8001_tag_free(pm8001_ha, tag); | |
2073 | sas_free_task(t); | |
2074 | return; | |
2075 | } | |
f5860992 S |
2076 | } else { |
2077 | u8 len; | |
2078 | ts->resp = SAS_TASK_COMPLETE; | |
2079 | ts->stat = SAS_PROTO_RESPONSE; | |
2080 | ts->residual = param; | |
2081 | PM8001_IO_DBG(pm8001_ha, | |
2082 | pm8001_printk("SAS_PROTO_RESPONSE len = %d\n", | |
2083 | param)); | |
2084 | sata_resp = &psataPayload->sata_resp[0]; | |
2085 | resp = (struct ata_task_resp *)ts->buf; | |
2086 | if (t->ata_task.dma_xfer == 0 && | |
2087 | t->data_dir == PCI_DMA_FROMDEVICE) { | |
2088 | len = sizeof(struct pio_setup_fis); | |
2089 | PM8001_IO_DBG(pm8001_ha, | |
2090 | pm8001_printk("PIO read len = %d\n", len)); | |
2091 | } else if (t->ata_task.use_ncq) { | |
2092 | len = sizeof(struct set_dev_bits_fis); | |
2093 | PM8001_IO_DBG(pm8001_ha, | |
2094 | pm8001_printk("FPDMA len = %d\n", len)); | |
2095 | } else { | |
2096 | len = sizeof(struct dev_to_host_fis); | |
2097 | PM8001_IO_DBG(pm8001_ha, | |
2098 | pm8001_printk("other len = %d\n", len)); | |
2099 | } | |
2100 | if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) { | |
2101 | resp->frame_len = len; | |
2102 | memcpy(&resp->ending_fis[0], sata_resp, len); | |
2103 | ts->buf_valid_size = sizeof(*resp); | |
2104 | } else | |
2105 | PM8001_IO_DBG(pm8001_ha, | |
2106 | pm8001_printk("response to large\n")); | |
2107 | } | |
2108 | if (pm8001_dev) | |
2109 | pm8001_dev->running_req--; | |
2110 | break; | |
2111 | case IO_ABORTED: | |
2112 | PM8001_IO_DBG(pm8001_ha, | |
2113 | pm8001_printk("IO_ABORTED IOMB Tag\n")); | |
2114 | ts->resp = SAS_TASK_COMPLETE; | |
2115 | ts->stat = SAS_ABORTED_TASK; | |
2116 | if (pm8001_dev) | |
2117 | pm8001_dev->running_req--; | |
2118 | break; | |
2119 | /* following cases are to do cases */ | |
2120 | case IO_UNDERFLOW: | |
2121 | /* SATA Completion with error */ | |
2122 | PM8001_IO_DBG(pm8001_ha, | |
2123 | pm8001_printk("IO_UNDERFLOW param = %d\n", param)); | |
2124 | ts->resp = SAS_TASK_COMPLETE; | |
2125 | ts->stat = SAS_DATA_UNDERRUN; | |
2126 | ts->residual = param; | |
2127 | if (pm8001_dev) | |
2128 | pm8001_dev->running_req--; | |
2129 | break; | |
2130 | case IO_NO_DEVICE: | |
2131 | PM8001_IO_DBG(pm8001_ha, | |
2132 | pm8001_printk("IO_NO_DEVICE\n")); | |
2133 | ts->resp = SAS_TASK_UNDELIVERED; | |
2134 | ts->stat = SAS_PHY_DOWN; | |
2135 | break; | |
2136 | case IO_XFER_ERROR_BREAK: | |
2137 | PM8001_IO_DBG(pm8001_ha, | |
2138 | pm8001_printk("IO_XFER_ERROR_BREAK\n")); | |
2139 | ts->resp = SAS_TASK_COMPLETE; | |
2140 | ts->stat = SAS_INTERRUPTED; | |
2141 | break; | |
2142 | case IO_XFER_ERROR_PHY_NOT_READY: | |
2143 | PM8001_IO_DBG(pm8001_ha, | |
2144 | pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); | |
2145 | ts->resp = SAS_TASK_COMPLETE; | |
2146 | ts->stat = SAS_OPEN_REJECT; | |
2147 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
2148 | break; | |
2149 | case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: | |
2150 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
2151 | "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); | |
2152 | ts->resp = SAS_TASK_COMPLETE; | |
2153 | ts->stat = SAS_OPEN_REJECT; | |
2154 | ts->open_rej_reason = SAS_OREJ_EPROTO; | |
2155 | break; | |
2156 | case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: | |
2157 | PM8001_IO_DBG(pm8001_ha, | |
2158 | pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); | |
2159 | ts->resp = SAS_TASK_COMPLETE; | |
2160 | ts->stat = SAS_OPEN_REJECT; | |
2161 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; | |
2162 | break; | |
2163 | case IO_OPEN_CNX_ERROR_BREAK: | |
2164 | PM8001_IO_DBG(pm8001_ha, | |
2165 | pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); | |
2166 | ts->resp = SAS_TASK_COMPLETE; | |
2167 | ts->stat = SAS_OPEN_REJECT; | |
2168 | ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; | |
2169 | break; | |
2170 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: | |
a6cb3d01 S |
2171 | case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: |
2172 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: | |
2173 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: | |
2174 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: | |
2175 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: | |
f5860992 S |
2176 | PM8001_IO_DBG(pm8001_ha, |
2177 | pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); | |
2178 | ts->resp = SAS_TASK_COMPLETE; | |
2179 | ts->stat = SAS_DEV_NO_RESPONSE; | |
2180 | if (!t->uldd_task) { | |
2181 | pm8001_handle_event(pm8001_ha, | |
2182 | pm8001_dev, | |
2183 | IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); | |
2184 | ts->resp = SAS_TASK_UNDELIVERED; | |
2185 | ts->stat = SAS_QUEUE_FULL; | |
2b01d816 | 2186 | pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); |
f5860992 S |
2187 | return; |
2188 | } | |
2189 | break; | |
2190 | case IO_OPEN_CNX_ERROR_BAD_DESTINATION: | |
2191 | PM8001_IO_DBG(pm8001_ha, | |
2192 | pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); | |
2193 | ts->resp = SAS_TASK_UNDELIVERED; | |
2194 | ts->stat = SAS_OPEN_REJECT; | |
2195 | ts->open_rej_reason = SAS_OREJ_BAD_DEST; | |
2196 | if (!t->uldd_task) { | |
2197 | pm8001_handle_event(pm8001_ha, | |
2198 | pm8001_dev, | |
2199 | IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); | |
2200 | ts->resp = SAS_TASK_UNDELIVERED; | |
2201 | ts->stat = SAS_QUEUE_FULL; | |
2b01d816 | 2202 | pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); |
f5860992 S |
2203 | return; |
2204 | } | |
2205 | break; | |
2206 | case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: | |
2207 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
2208 | "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); | |
2209 | ts->resp = SAS_TASK_COMPLETE; | |
2210 | ts->stat = SAS_OPEN_REJECT; | |
2211 | ts->open_rej_reason = SAS_OREJ_CONN_RATE; | |
2212 | break; | |
2213 | case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: | |
2214 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
2215 | "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n")); | |
2216 | ts->resp = SAS_TASK_COMPLETE; | |
2217 | ts->stat = SAS_DEV_NO_RESPONSE; | |
2218 | if (!t->uldd_task) { | |
2219 | pm8001_handle_event(pm8001_ha, | |
2220 | pm8001_dev, | |
2221 | IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY); | |
2222 | ts->resp = SAS_TASK_UNDELIVERED; | |
2223 | ts->stat = SAS_QUEUE_FULL; | |
2b01d816 | 2224 | pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); |
f5860992 S |
2225 | return; |
2226 | } | |
2227 | break; | |
2228 | case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: | |
2229 | PM8001_IO_DBG(pm8001_ha, | |
2230 | pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); | |
2231 | ts->resp = SAS_TASK_COMPLETE; | |
2232 | ts->stat = SAS_OPEN_REJECT; | |
2233 | ts->open_rej_reason = SAS_OREJ_WRONG_DEST; | |
2234 | break; | |
2235 | case IO_XFER_ERROR_NAK_RECEIVED: | |
2236 | PM8001_IO_DBG(pm8001_ha, | |
2237 | pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); | |
2238 | ts->resp = SAS_TASK_COMPLETE; | |
2239 | ts->stat = SAS_NAK_R_ERR; | |
2240 | break; | |
2241 | case IO_XFER_ERROR_ACK_NAK_TIMEOUT: | |
2242 | PM8001_IO_DBG(pm8001_ha, | |
2243 | pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n")); | |
2244 | ts->resp = SAS_TASK_COMPLETE; | |
2245 | ts->stat = SAS_NAK_R_ERR; | |
2246 | break; | |
2247 | case IO_XFER_ERROR_DMA: | |
2248 | PM8001_IO_DBG(pm8001_ha, | |
2249 | pm8001_printk("IO_XFER_ERROR_DMA\n")); | |
2250 | ts->resp = SAS_TASK_COMPLETE; | |
2251 | ts->stat = SAS_ABORTED_TASK; | |
2252 | break; | |
2253 | case IO_XFER_ERROR_SATA_LINK_TIMEOUT: | |
2254 | PM8001_IO_DBG(pm8001_ha, | |
2255 | pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n")); | |
2256 | ts->resp = SAS_TASK_UNDELIVERED; | |
2257 | ts->stat = SAS_DEV_NO_RESPONSE; | |
2258 | break; | |
2259 | case IO_XFER_ERROR_REJECTED_NCQ_MODE: | |
2260 | PM8001_IO_DBG(pm8001_ha, | |
2261 | pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); | |
2262 | ts->resp = SAS_TASK_COMPLETE; | |
2263 | ts->stat = SAS_DATA_UNDERRUN; | |
2264 | break; | |
2265 | case IO_XFER_OPEN_RETRY_TIMEOUT: | |
2266 | PM8001_IO_DBG(pm8001_ha, | |
2267 | pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); | |
2268 | ts->resp = SAS_TASK_COMPLETE; | |
2269 | ts->stat = SAS_OPEN_TO; | |
2270 | break; | |
2271 | case IO_PORT_IN_RESET: | |
2272 | PM8001_IO_DBG(pm8001_ha, | |
2273 | pm8001_printk("IO_PORT_IN_RESET\n")); | |
2274 | ts->resp = SAS_TASK_COMPLETE; | |
2275 | ts->stat = SAS_DEV_NO_RESPONSE; | |
2276 | break; | |
2277 | case IO_DS_NON_OPERATIONAL: | |
2278 | PM8001_IO_DBG(pm8001_ha, | |
2279 | pm8001_printk("IO_DS_NON_OPERATIONAL\n")); | |
2280 | ts->resp = SAS_TASK_COMPLETE; | |
2281 | ts->stat = SAS_DEV_NO_RESPONSE; | |
2282 | if (!t->uldd_task) { | |
2283 | pm8001_handle_event(pm8001_ha, pm8001_dev, | |
2284 | IO_DS_NON_OPERATIONAL); | |
2285 | ts->resp = SAS_TASK_UNDELIVERED; | |
2286 | ts->stat = SAS_QUEUE_FULL; | |
2b01d816 | 2287 | pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); |
f5860992 S |
2288 | return; |
2289 | } | |
2290 | break; | |
2291 | case IO_DS_IN_RECOVERY: | |
2292 | PM8001_IO_DBG(pm8001_ha, | |
2293 | pm8001_printk("IO_DS_IN_RECOVERY\n")); | |
2294 | ts->resp = SAS_TASK_COMPLETE; | |
2295 | ts->stat = SAS_DEV_NO_RESPONSE; | |
2296 | break; | |
2297 | case IO_DS_IN_ERROR: | |
2298 | PM8001_IO_DBG(pm8001_ha, | |
2299 | pm8001_printk("IO_DS_IN_ERROR\n")); | |
2300 | ts->resp = SAS_TASK_COMPLETE; | |
2301 | ts->stat = SAS_DEV_NO_RESPONSE; | |
2302 | if (!t->uldd_task) { | |
2303 | pm8001_handle_event(pm8001_ha, pm8001_dev, | |
2304 | IO_DS_IN_ERROR); | |
2305 | ts->resp = SAS_TASK_UNDELIVERED; | |
2306 | ts->stat = SAS_QUEUE_FULL; | |
2b01d816 | 2307 | pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); |
f5860992 S |
2308 | return; |
2309 | } | |
2310 | break; | |
2311 | case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: | |
2312 | PM8001_IO_DBG(pm8001_ha, | |
2313 | pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); | |
2314 | ts->resp = SAS_TASK_COMPLETE; | |
2315 | ts->stat = SAS_OPEN_REJECT; | |
2316 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
2317 | default: | |
2318 | PM8001_IO_DBG(pm8001_ha, | |
2319 | pm8001_printk("Unknown status 0x%x\n", status)); | |
2320 | /* not allowed case. Therefore, return failed status */ | |
2321 | ts->resp = SAS_TASK_COMPLETE; | |
2322 | ts->stat = SAS_DEV_NO_RESPONSE; | |
2323 | break; | |
2324 | } | |
2325 | spin_lock_irqsave(&t->task_state_lock, flags); | |
2326 | t->task_state_flags &= ~SAS_TASK_STATE_PENDING; | |
2327 | t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; | |
2328 | t->task_state_flags |= SAS_TASK_STATE_DONE; | |
2329 | if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { | |
2330 | spin_unlock_irqrestore(&t->task_state_lock, flags); | |
2331 | PM8001_FAIL_DBG(pm8001_ha, | |
2332 | pm8001_printk("task 0x%p done with io_status 0x%x" | |
2333 | " resp 0x%x stat 0x%x but aborted by upper layer!\n", | |
2334 | t, status, ts->resp, ts->stat)); | |
2335 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); | |
2b01d816 | 2336 | } else { |
f5860992 | 2337 | spin_unlock_irqrestore(&t->task_state_lock, flags); |
2b01d816 | 2338 | pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); |
f5860992 S |
2339 | } |
2340 | } | |
2341 | ||
2342 | /*See the comments for mpi_ssp_completion */ | |
2343 | static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb) | |
2344 | { | |
2345 | struct sas_task *t; | |
2346 | struct task_status_struct *ts; | |
2347 | struct pm8001_ccb_info *ccb; | |
2348 | struct pm8001_device *pm8001_dev; | |
2349 | struct sata_event_resp *psataPayload = | |
2350 | (struct sata_event_resp *)(piomb + 4); | |
2351 | u32 event = le32_to_cpu(psataPayload->event); | |
2352 | u32 tag = le32_to_cpu(psataPayload->tag); | |
2353 | u32 port_id = le32_to_cpu(psataPayload->port_id); | |
c6b9ef57 S |
2354 | u32 dev_id = le32_to_cpu(psataPayload->device_id); |
2355 | unsigned long flags; | |
f5860992 S |
2356 | |
2357 | ccb = &pm8001_ha->ccb_info[tag]; | |
c6b9ef57 S |
2358 | |
2359 | if (ccb) { | |
2360 | t = ccb->task; | |
2361 | pm8001_dev = ccb->device; | |
2362 | } else { | |
2363 | PM8001_FAIL_DBG(pm8001_ha, | |
2364 | pm8001_printk("No CCB !!!. returning\n")); | |
2365 | return; | |
2366 | } | |
f5860992 S |
2367 | if (event) |
2368 | PM8001_FAIL_DBG(pm8001_ha, | |
c6b9ef57 S |
2369 | pm8001_printk("SATA EVENT 0x%x\n", event)); |
2370 | ||
2371 | /* Check if this is NCQ error */ | |
2372 | if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) { | |
2373 | /* find device using device id */ | |
2374 | pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); | |
2375 | /* send read log extension */ | |
2376 | if (pm8001_dev) | |
2377 | pm80xx_send_read_log(pm8001_ha, pm8001_dev); | |
2378 | return; | |
2379 | } | |
2380 | ||
2381 | if (unlikely(!t || !t->lldd_task || !t->dev)) { | |
2382 | PM8001_FAIL_DBG(pm8001_ha, | |
2383 | pm8001_printk("task or dev null\n")); | |
f5860992 | 2384 | return; |
c6b9ef57 S |
2385 | } |
2386 | ||
f5860992 S |
2387 | ts = &t->task_status; |
2388 | PM8001_IO_DBG(pm8001_ha, | |
2389 | pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n", | |
2390 | port_id, tag, event)); | |
2391 | switch (event) { | |
2392 | case IO_OVERFLOW: | |
2393 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); | |
2394 | ts->resp = SAS_TASK_COMPLETE; | |
2395 | ts->stat = SAS_DATA_OVERRUN; | |
2396 | ts->residual = 0; | |
2397 | if (pm8001_dev) | |
2398 | pm8001_dev->running_req--; | |
2399 | break; | |
2400 | case IO_XFER_ERROR_BREAK: | |
2401 | PM8001_IO_DBG(pm8001_ha, | |
2402 | pm8001_printk("IO_XFER_ERROR_BREAK\n")); | |
2403 | ts->resp = SAS_TASK_COMPLETE; | |
2404 | ts->stat = SAS_INTERRUPTED; | |
2405 | break; | |
2406 | case IO_XFER_ERROR_PHY_NOT_READY: | |
2407 | PM8001_IO_DBG(pm8001_ha, | |
2408 | pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); | |
2409 | ts->resp = SAS_TASK_COMPLETE; | |
2410 | ts->stat = SAS_OPEN_REJECT; | |
2411 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
2412 | break; | |
2413 | case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: | |
2414 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
2415 | "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); | |
2416 | ts->resp = SAS_TASK_COMPLETE; | |
2417 | ts->stat = SAS_OPEN_REJECT; | |
2418 | ts->open_rej_reason = SAS_OREJ_EPROTO; | |
2419 | break; | |
2420 | case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: | |
2421 | PM8001_IO_DBG(pm8001_ha, | |
2422 | pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); | |
2423 | ts->resp = SAS_TASK_COMPLETE; | |
2424 | ts->stat = SAS_OPEN_REJECT; | |
2425 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; | |
2426 | break; | |
2427 | case IO_OPEN_CNX_ERROR_BREAK: | |
2428 | PM8001_IO_DBG(pm8001_ha, | |
2429 | pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); | |
2430 | ts->resp = SAS_TASK_COMPLETE; | |
2431 | ts->stat = SAS_OPEN_REJECT; | |
2432 | ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; | |
2433 | break; | |
2434 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: | |
a6cb3d01 S |
2435 | case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: |
2436 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: | |
2437 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: | |
2438 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: | |
2439 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: | |
2440 | PM8001_FAIL_DBG(pm8001_ha, | |
f5860992 S |
2441 | pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); |
2442 | ts->resp = SAS_TASK_UNDELIVERED; | |
2443 | ts->stat = SAS_DEV_NO_RESPONSE; | |
2444 | if (!t->uldd_task) { | |
2445 | pm8001_handle_event(pm8001_ha, | |
2446 | pm8001_dev, | |
2447 | IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); | |
2448 | ts->resp = SAS_TASK_COMPLETE; | |
2449 | ts->stat = SAS_QUEUE_FULL; | |
2b01d816 | 2450 | pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); |
f5860992 S |
2451 | return; |
2452 | } | |
2453 | break; | |
2454 | case IO_OPEN_CNX_ERROR_BAD_DESTINATION: | |
2455 | PM8001_IO_DBG(pm8001_ha, | |
2456 | pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); | |
2457 | ts->resp = SAS_TASK_UNDELIVERED; | |
2458 | ts->stat = SAS_OPEN_REJECT; | |
2459 | ts->open_rej_reason = SAS_OREJ_BAD_DEST; | |
2460 | break; | |
2461 | case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: | |
2462 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
2463 | "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); | |
2464 | ts->resp = SAS_TASK_COMPLETE; | |
2465 | ts->stat = SAS_OPEN_REJECT; | |
2466 | ts->open_rej_reason = SAS_OREJ_CONN_RATE; | |
2467 | break; | |
2468 | case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: | |
2469 | PM8001_IO_DBG(pm8001_ha, | |
2470 | pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); | |
2471 | ts->resp = SAS_TASK_COMPLETE; | |
2472 | ts->stat = SAS_OPEN_REJECT; | |
2473 | ts->open_rej_reason = SAS_OREJ_WRONG_DEST; | |
2474 | break; | |
2475 | case IO_XFER_ERROR_NAK_RECEIVED: | |
2476 | PM8001_IO_DBG(pm8001_ha, | |
2477 | pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n")); | |
2478 | ts->resp = SAS_TASK_COMPLETE; | |
2479 | ts->stat = SAS_NAK_R_ERR; | |
2480 | break; | |
2481 | case IO_XFER_ERROR_PEER_ABORTED: | |
2482 | PM8001_IO_DBG(pm8001_ha, | |
2483 | pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n")); | |
2484 | ts->resp = SAS_TASK_COMPLETE; | |
2485 | ts->stat = SAS_NAK_R_ERR; | |
2486 | break; | |
2487 | case IO_XFER_ERROR_REJECTED_NCQ_MODE: | |
2488 | PM8001_IO_DBG(pm8001_ha, | |
2489 | pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n")); | |
2490 | ts->resp = SAS_TASK_COMPLETE; | |
2491 | ts->stat = SAS_DATA_UNDERRUN; | |
2492 | break; | |
2493 | case IO_XFER_OPEN_RETRY_TIMEOUT: | |
2494 | PM8001_IO_DBG(pm8001_ha, | |
2495 | pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); | |
2496 | ts->resp = SAS_TASK_COMPLETE; | |
2497 | ts->stat = SAS_OPEN_TO; | |
2498 | break; | |
2499 | case IO_XFER_ERROR_UNEXPECTED_PHASE: | |
2500 | PM8001_IO_DBG(pm8001_ha, | |
2501 | pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n")); | |
2502 | ts->resp = SAS_TASK_COMPLETE; | |
2503 | ts->stat = SAS_OPEN_TO; | |
2504 | break; | |
2505 | case IO_XFER_ERROR_XFER_RDY_OVERRUN: | |
2506 | PM8001_IO_DBG(pm8001_ha, | |
2507 | pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n")); | |
2508 | ts->resp = SAS_TASK_COMPLETE; | |
2509 | ts->stat = SAS_OPEN_TO; | |
2510 | break; | |
2511 | case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED: | |
2512 | PM8001_IO_DBG(pm8001_ha, | |
2513 | pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n")); | |
2514 | ts->resp = SAS_TASK_COMPLETE; | |
2515 | ts->stat = SAS_OPEN_TO; | |
2516 | break; | |
2517 | case IO_XFER_ERROR_OFFSET_MISMATCH: | |
2518 | PM8001_IO_DBG(pm8001_ha, | |
2519 | pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n")); | |
2520 | ts->resp = SAS_TASK_COMPLETE; | |
2521 | ts->stat = SAS_OPEN_TO; | |
2522 | break; | |
2523 | case IO_XFER_ERROR_XFER_ZERO_DATA_LEN: | |
2524 | PM8001_IO_DBG(pm8001_ha, | |
2525 | pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n")); | |
2526 | ts->resp = SAS_TASK_COMPLETE; | |
2527 | ts->stat = SAS_OPEN_TO; | |
2528 | break; | |
2529 | case IO_XFER_CMD_FRAME_ISSUED: | |
2530 | PM8001_IO_DBG(pm8001_ha, | |
2531 | pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n")); | |
2532 | break; | |
2533 | case IO_XFER_PIO_SETUP_ERROR: | |
2534 | PM8001_IO_DBG(pm8001_ha, | |
2535 | pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n")); | |
2536 | ts->resp = SAS_TASK_COMPLETE; | |
2537 | ts->stat = SAS_OPEN_TO; | |
2538 | break; | |
a6cb3d01 S |
2539 | case IO_XFER_ERROR_INTERNAL_CRC_ERROR: |
2540 | PM8001_FAIL_DBG(pm8001_ha, | |
2541 | pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n")); | |
2542 | /* TBC: used default set values */ | |
2543 | ts->resp = SAS_TASK_COMPLETE; | |
2544 | ts->stat = SAS_OPEN_TO; | |
2545 | break; | |
2546 | case IO_XFER_DMA_ACTIVATE_TIMEOUT: | |
2547 | PM8001_FAIL_DBG(pm8001_ha, | |
2548 | pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n")); | |
2549 | /* TBC: used default set values */ | |
2550 | ts->resp = SAS_TASK_COMPLETE; | |
2551 | ts->stat = SAS_OPEN_TO; | |
2552 | break; | |
f5860992 S |
2553 | default: |
2554 | PM8001_IO_DBG(pm8001_ha, | |
2555 | pm8001_printk("Unknown status 0x%x\n", event)); | |
2556 | /* not allowed case. Therefore, return failed status */ | |
2557 | ts->resp = SAS_TASK_COMPLETE; | |
2558 | ts->stat = SAS_OPEN_TO; | |
2559 | break; | |
2560 | } | |
2561 | spin_lock_irqsave(&t->task_state_lock, flags); | |
2562 | t->task_state_flags &= ~SAS_TASK_STATE_PENDING; | |
2563 | t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; | |
2564 | t->task_state_flags |= SAS_TASK_STATE_DONE; | |
2565 | if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { | |
2566 | spin_unlock_irqrestore(&t->task_state_lock, flags); | |
2567 | PM8001_FAIL_DBG(pm8001_ha, | |
2568 | pm8001_printk("task 0x%p done with io_status 0x%x" | |
2569 | " resp 0x%x stat 0x%x but aborted by upper layer!\n", | |
2570 | t, event, ts->resp, ts->stat)); | |
2571 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); | |
2b01d816 | 2572 | } else { |
f5860992 | 2573 | spin_unlock_irqrestore(&t->task_state_lock, flags); |
2b01d816 | 2574 | pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); |
f5860992 S |
2575 | } |
2576 | } | |
2577 | ||
2578 | /*See the comments for mpi_ssp_completion */ | |
2579 | static void | |
2580 | mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) | |
2581 | { | |
2582 | u32 param, i; | |
2583 | struct sas_task *t; | |
2584 | struct pm8001_ccb_info *ccb; | |
2585 | unsigned long flags; | |
2586 | u32 status; | |
2587 | u32 tag; | |
2588 | struct smp_completion_resp *psmpPayload; | |
2589 | struct task_status_struct *ts; | |
2590 | struct pm8001_device *pm8001_dev; | |
2591 | char *pdma_respaddr = NULL; | |
2592 | ||
2593 | psmpPayload = (struct smp_completion_resp *)(piomb + 4); | |
2594 | status = le32_to_cpu(psmpPayload->status); | |
2595 | tag = le32_to_cpu(psmpPayload->tag); | |
2596 | ||
2597 | ccb = &pm8001_ha->ccb_info[tag]; | |
2598 | param = le32_to_cpu(psmpPayload->param); | |
2599 | t = ccb->task; | |
2600 | ts = &t->task_status; | |
2601 | pm8001_dev = ccb->device; | |
2602 | if (status) | |
2603 | PM8001_FAIL_DBG(pm8001_ha, | |
2604 | pm8001_printk("smp IO status 0x%x\n", status)); | |
2605 | if (unlikely(!t || !t->lldd_task || !t->dev)) | |
2606 | return; | |
2607 | ||
2608 | switch (status) { | |
2609 | ||
2610 | case IO_SUCCESS: | |
2611 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n")); | |
2612 | ts->resp = SAS_TASK_COMPLETE; | |
2613 | ts->stat = SAM_STAT_GOOD; | |
2614 | if (pm8001_dev) | |
2615 | pm8001_dev->running_req--; | |
2616 | if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { | |
2617 | PM8001_IO_DBG(pm8001_ha, | |
2618 | pm8001_printk("DIRECT RESPONSE Length:%d\n", | |
2619 | param)); | |
2620 | pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64 | |
2621 | ((u64)sg_dma_address | |
2622 | (&t->smp_task.smp_resp)))); | |
2623 | for (i = 0; i < param; i++) { | |
2624 | *(pdma_respaddr+i) = psmpPayload->_r_a[i]; | |
2625 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
2626 | "SMP Byte%d DMA data 0x%x psmp 0x%x\n", | |
2627 | i, *(pdma_respaddr+i), | |
2628 | psmpPayload->_r_a[i])); | |
2629 | } | |
2630 | } | |
2631 | break; | |
2632 | case IO_ABORTED: | |
2633 | PM8001_IO_DBG(pm8001_ha, | |
2634 | pm8001_printk("IO_ABORTED IOMB\n")); | |
2635 | ts->resp = SAS_TASK_COMPLETE; | |
2636 | ts->stat = SAS_ABORTED_TASK; | |
2637 | if (pm8001_dev) | |
2638 | pm8001_dev->running_req--; | |
2639 | break; | |
2640 | case IO_OVERFLOW: | |
2641 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n")); | |
2642 | ts->resp = SAS_TASK_COMPLETE; | |
2643 | ts->stat = SAS_DATA_OVERRUN; | |
2644 | ts->residual = 0; | |
2645 | if (pm8001_dev) | |
2646 | pm8001_dev->running_req--; | |
2647 | break; | |
2648 | case IO_NO_DEVICE: | |
2649 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n")); | |
2650 | ts->resp = SAS_TASK_COMPLETE; | |
2651 | ts->stat = SAS_PHY_DOWN; | |
2652 | break; | |
2653 | case IO_ERROR_HW_TIMEOUT: | |
2654 | PM8001_IO_DBG(pm8001_ha, | |
2655 | pm8001_printk("IO_ERROR_HW_TIMEOUT\n")); | |
2656 | ts->resp = SAS_TASK_COMPLETE; | |
2657 | ts->stat = SAM_STAT_BUSY; | |
2658 | break; | |
2659 | case IO_XFER_ERROR_BREAK: | |
2660 | PM8001_IO_DBG(pm8001_ha, | |
2661 | pm8001_printk("IO_XFER_ERROR_BREAK\n")); | |
2662 | ts->resp = SAS_TASK_COMPLETE; | |
2663 | ts->stat = SAM_STAT_BUSY; | |
2664 | break; | |
2665 | case IO_XFER_ERROR_PHY_NOT_READY: | |
2666 | PM8001_IO_DBG(pm8001_ha, | |
2667 | pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n")); | |
2668 | ts->resp = SAS_TASK_COMPLETE; | |
2669 | ts->stat = SAM_STAT_BUSY; | |
2670 | break; | |
2671 | case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED: | |
2672 | PM8001_IO_DBG(pm8001_ha, | |
2673 | pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n")); | |
2674 | ts->resp = SAS_TASK_COMPLETE; | |
2675 | ts->stat = SAS_OPEN_REJECT; | |
2676 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; | |
2677 | break; | |
2678 | case IO_OPEN_CNX_ERROR_ZONE_VIOLATION: | |
2679 | PM8001_IO_DBG(pm8001_ha, | |
2680 | pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n")); | |
2681 | ts->resp = SAS_TASK_COMPLETE; | |
2682 | ts->stat = SAS_OPEN_REJECT; | |
2683 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; | |
2684 | break; | |
2685 | case IO_OPEN_CNX_ERROR_BREAK: | |
2686 | PM8001_IO_DBG(pm8001_ha, | |
2687 | pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n")); | |
2688 | ts->resp = SAS_TASK_COMPLETE; | |
2689 | ts->stat = SAS_OPEN_REJECT; | |
2690 | ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; | |
2691 | break; | |
2692 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS: | |
a6cb3d01 S |
2693 | case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED: |
2694 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO: | |
2695 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST: | |
2696 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE: | |
2697 | case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED: | |
f5860992 S |
2698 | PM8001_IO_DBG(pm8001_ha, |
2699 | pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n")); | |
2700 | ts->resp = SAS_TASK_COMPLETE; | |
2701 | ts->stat = SAS_OPEN_REJECT; | |
2702 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; | |
2703 | pm8001_handle_event(pm8001_ha, | |
2704 | pm8001_dev, | |
2705 | IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS); | |
2706 | break; | |
2707 | case IO_OPEN_CNX_ERROR_BAD_DESTINATION: | |
2708 | PM8001_IO_DBG(pm8001_ha, | |
2709 | pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n")); | |
2710 | ts->resp = SAS_TASK_COMPLETE; | |
2711 | ts->stat = SAS_OPEN_REJECT; | |
2712 | ts->open_rej_reason = SAS_OREJ_BAD_DEST; | |
2713 | break; | |
2714 | case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: | |
2715 | PM8001_IO_DBG(pm8001_ha, pm8001_printk(\ | |
2716 | "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n")); | |
2717 | ts->resp = SAS_TASK_COMPLETE; | |
2718 | ts->stat = SAS_OPEN_REJECT; | |
2719 | ts->open_rej_reason = SAS_OREJ_CONN_RATE; | |
2720 | break; | |
2721 | case IO_OPEN_CNX_ERROR_WRONG_DESTINATION: | |
2722 | PM8001_IO_DBG(pm8001_ha, | |
2723 | pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n")); | |
2724 | ts->resp = SAS_TASK_COMPLETE; | |
2725 | ts->stat = SAS_OPEN_REJECT; | |
2726 | ts->open_rej_reason = SAS_OREJ_WRONG_DEST; | |
2727 | break; | |
2728 | case IO_XFER_ERROR_RX_FRAME: | |
2729 | PM8001_IO_DBG(pm8001_ha, | |
2730 | pm8001_printk("IO_XFER_ERROR_RX_FRAME\n")); | |
2731 | ts->resp = SAS_TASK_COMPLETE; | |
2732 | ts->stat = SAS_DEV_NO_RESPONSE; | |
2733 | break; | |
2734 | case IO_XFER_OPEN_RETRY_TIMEOUT: | |
2735 | PM8001_IO_DBG(pm8001_ha, | |
2736 | pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n")); | |
2737 | ts->resp = SAS_TASK_COMPLETE; | |
2738 | ts->stat = SAS_OPEN_REJECT; | |
2739 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
2740 | break; | |
2741 | case IO_ERROR_INTERNAL_SMP_RESOURCE: | |
2742 | PM8001_IO_DBG(pm8001_ha, | |
2743 | pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n")); | |
2744 | ts->resp = SAS_TASK_COMPLETE; | |
2745 | ts->stat = SAS_QUEUE_FULL; | |
2746 | break; | |
2747 | case IO_PORT_IN_RESET: | |
2748 | PM8001_IO_DBG(pm8001_ha, | |
2749 | pm8001_printk("IO_PORT_IN_RESET\n")); | |
2750 | ts->resp = SAS_TASK_COMPLETE; | |
2751 | ts->stat = SAS_OPEN_REJECT; | |
2752 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
2753 | break; | |
2754 | case IO_DS_NON_OPERATIONAL: | |
2755 | PM8001_IO_DBG(pm8001_ha, | |
2756 | pm8001_printk("IO_DS_NON_OPERATIONAL\n")); | |
2757 | ts->resp = SAS_TASK_COMPLETE; | |
2758 | ts->stat = SAS_DEV_NO_RESPONSE; | |
2759 | break; | |
2760 | case IO_DS_IN_RECOVERY: | |
2761 | PM8001_IO_DBG(pm8001_ha, | |
2762 | pm8001_printk("IO_DS_IN_RECOVERY\n")); | |
2763 | ts->resp = SAS_TASK_COMPLETE; | |
2764 | ts->stat = SAS_OPEN_REJECT; | |
2765 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
2766 | break; | |
2767 | case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: | |
2768 | PM8001_IO_DBG(pm8001_ha, | |
2769 | pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n")); | |
2770 | ts->resp = SAS_TASK_COMPLETE; | |
2771 | ts->stat = SAS_OPEN_REJECT; | |
2772 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
2773 | break; | |
2774 | default: | |
2775 | PM8001_IO_DBG(pm8001_ha, | |
2776 | pm8001_printk("Unknown status 0x%x\n", status)); | |
2777 | ts->resp = SAS_TASK_COMPLETE; | |
2778 | ts->stat = SAS_DEV_NO_RESPONSE; | |
2779 | /* not allowed case. Therefore, return failed status */ | |
2780 | break; | |
2781 | } | |
2782 | spin_lock_irqsave(&t->task_state_lock, flags); | |
2783 | t->task_state_flags &= ~SAS_TASK_STATE_PENDING; | |
2784 | t->task_state_flags &= ~SAS_TASK_AT_INITIATOR; | |
2785 | t->task_state_flags |= SAS_TASK_STATE_DONE; | |
2786 | if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { | |
2787 | spin_unlock_irqrestore(&t->task_state_lock, flags); | |
2788 | PM8001_FAIL_DBG(pm8001_ha, pm8001_printk( | |
2789 | "task 0x%p done with io_status 0x%x resp 0x%x" | |
2790 | "stat 0x%x but aborted by upper layer!\n", | |
2791 | t, status, ts->resp, ts->stat)); | |
2792 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); | |
2793 | } else { | |
2794 | spin_unlock_irqrestore(&t->task_state_lock, flags); | |
2795 | pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); | |
2796 | mb();/* in order to force CPU ordering */ | |
2797 | t->task_done(t); | |
2798 | } | |
2799 | } | |
2800 | ||
2801 | /** | |
2802 | * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW. | |
2803 | * @pm8001_ha: our hba card information | |
2804 | * @Qnum: the outbound queue message number. | |
2805 | * @SEA: source of event to ack | |
2806 | * @port_id: port id. | |
2807 | * @phyId: phy id. | |
2808 | * @param0: parameter 0. | |
2809 | * @param1: parameter 1. | |
2810 | */ | |
2811 | static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, | |
2812 | u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1) | |
2813 | { | |
2814 | struct hw_event_ack_req payload; | |
2815 | u32 opc = OPC_INB_SAS_HW_EVENT_ACK; | |
2816 | ||
2817 | struct inbound_queue_table *circularQ; | |
2818 | ||
2819 | memset((u8 *)&payload, 0, sizeof(payload)); | |
2820 | circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; | |
2821 | payload.tag = cpu_to_le32(1); | |
2822 | payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | | |
2823 | ((phyId & 0xFF) << 24) | (port_id & 0xFF)); | |
2824 | payload.param0 = cpu_to_le32(param0); | |
2825 | payload.param1 = cpu_to_le32(param1); | |
2826 | pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); | |
2827 | } | |
2828 | ||
2829 | static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, | |
2830 | u32 phyId, u32 phy_op); | |
2831 | ||
2832 | /** | |
2833 | * hw_event_sas_phy_up -FW tells me a SAS phy up event. | |
2834 | * @pm8001_ha: our hba card information | |
2835 | * @piomb: IO message buffer | |
2836 | */ | |
2837 | static void | |
2838 | hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) | |
2839 | { | |
2840 | struct hw_event_resp *pPayload = | |
2841 | (struct hw_event_resp *)(piomb + 4); | |
2842 | u32 lr_status_evt_portid = | |
2843 | le32_to_cpu(pPayload->lr_status_evt_portid); | |
2844 | u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); | |
2845 | ||
2846 | u8 link_rate = | |
2847 | (u8)((lr_status_evt_portid & 0xF0000000) >> 28); | |
2848 | u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); | |
2849 | u8 phy_id = | |
2850 | (u8)((phyid_npip_portstate & 0xFF0000) >> 16); | |
2851 | u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); | |
2852 | ||
2853 | struct pm8001_port *port = &pm8001_ha->port[port_id]; | |
2854 | struct sas_ha_struct *sas_ha = pm8001_ha->sas; | |
2855 | struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; | |
2856 | unsigned long flags; | |
2857 | u8 deviceType = pPayload->sas_identify.dev_type; | |
2858 | port->port_state = portstate; | |
7d029005 | 2859 | phy->phy_state = PHY_STATE_LINK_UP_SPCV; |
f5860992 S |
2860 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( |
2861 | "portid:%d; phyid:%d; linkrate:%d; " | |
2862 | "portstate:%x; devicetype:%x\n", | |
2863 | port_id, phy_id, link_rate, portstate, deviceType)); | |
2864 | ||
2865 | switch (deviceType) { | |
2866 | case SAS_PHY_UNUSED: | |
2867 | PM8001_MSG_DBG(pm8001_ha, | |
2868 | pm8001_printk("device type no device.\n")); | |
2869 | break; | |
2870 | case SAS_END_DEVICE: | |
2871 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n")); | |
2872 | pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id, | |
2873 | PHY_NOTIFY_ENABLE_SPINUP); | |
2874 | port->port_attached = 1; | |
2875 | pm8001_get_lrate_mode(phy, link_rate); | |
2876 | break; | |
2877 | case SAS_EDGE_EXPANDER_DEVICE: | |
2878 | PM8001_MSG_DBG(pm8001_ha, | |
2879 | pm8001_printk("expander device.\n")); | |
2880 | port->port_attached = 1; | |
2881 | pm8001_get_lrate_mode(phy, link_rate); | |
2882 | break; | |
2883 | case SAS_FANOUT_EXPANDER_DEVICE: | |
2884 | PM8001_MSG_DBG(pm8001_ha, | |
2885 | pm8001_printk("fanout expander device.\n")); | |
2886 | port->port_attached = 1; | |
2887 | pm8001_get_lrate_mode(phy, link_rate); | |
2888 | break; | |
2889 | default: | |
2890 | PM8001_MSG_DBG(pm8001_ha, | |
2891 | pm8001_printk("unknown device type(%x)\n", deviceType)); | |
2892 | break; | |
2893 | } | |
2894 | phy->phy_type |= PORT_TYPE_SAS; | |
2895 | phy->identify.device_type = deviceType; | |
2896 | phy->phy_attached = 1; | |
2897 | if (phy->identify.device_type == SAS_END_DEVICE) | |
2898 | phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; | |
2899 | else if (phy->identify.device_type != SAS_PHY_UNUSED) | |
2900 | phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; | |
2901 | phy->sas_phy.oob_mode = SAS_OOB_MODE; | |
2902 | sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); | |
2903 | spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); | |
2904 | memcpy(phy->frame_rcvd, &pPayload->sas_identify, | |
2905 | sizeof(struct sas_identify_frame)-4); | |
2906 | phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; | |
2907 | pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); | |
2908 | spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); | |
2909 | if (pm8001_ha->flags == PM8001F_RUN_TIME) | |
2910 | mdelay(200);/*delay a moment to wait disk to spinup*/ | |
2911 | pm8001_bytes_dmaed(pm8001_ha, phy_id); | |
2912 | } | |
2913 | ||
2914 | /** | |
2915 | * hw_event_sata_phy_up -FW tells me a SATA phy up event. | |
2916 | * @pm8001_ha: our hba card information | |
2917 | * @piomb: IO message buffer | |
2918 | */ | |
2919 | static void | |
2920 | hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) | |
2921 | { | |
2922 | struct hw_event_resp *pPayload = | |
2923 | (struct hw_event_resp *)(piomb + 4); | |
2924 | u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); | |
2925 | u32 lr_status_evt_portid = | |
2926 | le32_to_cpu(pPayload->lr_status_evt_portid); | |
2927 | u8 link_rate = | |
2928 | (u8)((lr_status_evt_portid & 0xF0000000) >> 28); | |
2929 | u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); | |
2930 | u8 phy_id = | |
2931 | (u8)((phyid_npip_portstate & 0xFF0000) >> 16); | |
2932 | ||
2933 | u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); | |
2934 | ||
2935 | struct pm8001_port *port = &pm8001_ha->port[port_id]; | |
2936 | struct sas_ha_struct *sas_ha = pm8001_ha->sas; | |
2937 | struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; | |
2938 | unsigned long flags; | |
2939 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
2940 | "port id %d, phy id %d link_rate %d portstate 0x%x\n", | |
2941 | port_id, phy_id, link_rate, portstate)); | |
2942 | ||
2943 | port->port_state = portstate; | |
7d029005 | 2944 | phy->phy_state = PHY_STATE_LINK_UP_SPCV; |
f5860992 S |
2945 | port->port_attached = 1; |
2946 | pm8001_get_lrate_mode(phy, link_rate); | |
2947 | phy->phy_type |= PORT_TYPE_SATA; | |
2948 | phy->phy_attached = 1; | |
2949 | phy->sas_phy.oob_mode = SATA_OOB_MODE; | |
2950 | sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE); | |
2951 | spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); | |
2952 | memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), | |
2953 | sizeof(struct dev_to_host_fis)); | |
2954 | phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); | |
2955 | phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; | |
aa9f8328 | 2956 | phy->identify.device_type = SAS_SATA_DEV; |
f5860992 S |
2957 | pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); |
2958 | spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); | |
2959 | pm8001_bytes_dmaed(pm8001_ha, phy_id); | |
2960 | } | |
2961 | ||
2962 | /** | |
2963 | * hw_event_phy_down -we should notify the libsas the phy is down. | |
2964 | * @pm8001_ha: our hba card information | |
2965 | * @piomb: IO message buffer | |
2966 | */ | |
2967 | static void | |
2968 | hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) | |
2969 | { | |
2970 | struct hw_event_resp *pPayload = | |
2971 | (struct hw_event_resp *)(piomb + 4); | |
2972 | ||
2973 | u32 lr_status_evt_portid = | |
2974 | le32_to_cpu(pPayload->lr_status_evt_portid); | |
2975 | u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); | |
2976 | u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); | |
2977 | u8 phy_id = | |
2978 | (u8)((phyid_npip_portstate & 0xFF0000) >> 16); | |
2979 | u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); | |
2980 | ||
2981 | struct pm8001_port *port = &pm8001_ha->port[port_id]; | |
2982 | struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; | |
2983 | port->port_state = portstate; | |
2984 | phy->phy_type = 0; | |
2985 | phy->identify.device_type = 0; | |
2986 | phy->phy_attached = 0; | |
2987 | memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE); | |
2988 | switch (portstate) { | |
2989 | case PORT_VALID: | |
2990 | break; | |
2991 | case PORT_INVALID: | |
2992 | PM8001_MSG_DBG(pm8001_ha, | |
2993 | pm8001_printk(" PortInvalid portID %d\n", port_id)); | |
2994 | PM8001_MSG_DBG(pm8001_ha, | |
2995 | pm8001_printk(" Last phy Down and port invalid\n")); | |
2996 | port->port_attached = 0; | |
2997 | pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, | |
2998 | port_id, phy_id, 0, 0); | |
2999 | break; | |
3000 | case PORT_IN_RESET: | |
3001 | PM8001_MSG_DBG(pm8001_ha, | |
3002 | pm8001_printk(" Port In Reset portID %d\n", port_id)); | |
3003 | break; | |
3004 | case PORT_NOT_ESTABLISHED: | |
3005 | PM8001_MSG_DBG(pm8001_ha, | |
3006 | pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n")); | |
3007 | port->port_attached = 0; | |
3008 | break; | |
3009 | case PORT_LOSTCOMM: | |
3010 | PM8001_MSG_DBG(pm8001_ha, | |
3011 | pm8001_printk(" phy Down and PORT_LOSTCOMM\n")); | |
3012 | PM8001_MSG_DBG(pm8001_ha, | |
3013 | pm8001_printk(" Last phy Down and port invalid\n")); | |
3014 | port->port_attached = 0; | |
3015 | pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, | |
3016 | port_id, phy_id, 0, 0); | |
3017 | break; | |
3018 | default: | |
3019 | port->port_attached = 0; | |
3020 | PM8001_MSG_DBG(pm8001_ha, | |
3021 | pm8001_printk(" phy Down and(default) = 0x%x\n", | |
3022 | portstate)); | |
3023 | break; | |
3024 | ||
3025 | } | |
3026 | } | |
3027 | ||
3028 | static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) | |
3029 | { | |
3030 | struct phy_start_resp *pPayload = | |
3031 | (struct phy_start_resp *)(piomb + 4); | |
3032 | u32 status = | |
3033 | le32_to_cpu(pPayload->status); | |
3034 | u32 phy_id = | |
3035 | le32_to_cpu(pPayload->phyid); | |
3036 | struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; | |
3037 | ||
3038 | PM8001_INIT_DBG(pm8001_ha, | |
3039 | pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n", | |
3040 | status, phy_id)); | |
3041 | if (status == 0) { | |
3042 | phy->phy_state = 1; | |
3043 | if (pm8001_ha->flags == PM8001F_RUN_TIME) | |
3044 | complete(phy->enable_completion); | |
3045 | } | |
3046 | return 0; | |
3047 | ||
3048 | } | |
3049 | ||
3050 | /** | |
3051 | * mpi_thermal_hw_event -The hw event has come. | |
3052 | * @pm8001_ha: our hba card information | |
3053 | * @piomb: IO message buffer | |
3054 | */ | |
3055 | static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) | |
3056 | { | |
3057 | struct thermal_hw_event *pPayload = | |
3058 | (struct thermal_hw_event *)(piomb + 4); | |
3059 | ||
3060 | u32 thermal_event = le32_to_cpu(pPayload->thermal_event); | |
3061 | u32 rht_lht = le32_to_cpu(pPayload->rht_lht); | |
3062 | ||
3063 | if (thermal_event & 0x40) { | |
3064 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
3065 | "Thermal Event: Local high temperature violated!\n")); | |
3066 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
3067 | "Thermal Event: Measured local high temperature %d\n", | |
3068 | ((rht_lht & 0xFF00) >> 8))); | |
3069 | } | |
3070 | if (thermal_event & 0x10) { | |
3071 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
3072 | "Thermal Event: Remote high temperature violated!\n")); | |
3073 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
3074 | "Thermal Event: Measured remote high temperature %d\n", | |
3075 | ((rht_lht & 0xFF000000) >> 24))); | |
3076 | } | |
3077 | return 0; | |
3078 | } | |
3079 | ||
3080 | /** | |
3081 | * mpi_hw_event -The hw event has come. | |
3082 | * @pm8001_ha: our hba card information | |
3083 | * @piomb: IO message buffer | |
3084 | */ | |
3085 | static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb) | |
3086 | { | |
3087 | unsigned long flags; | |
3088 | struct hw_event_resp *pPayload = | |
3089 | (struct hw_event_resp *)(piomb + 4); | |
3090 | u32 lr_status_evt_portid = | |
3091 | le32_to_cpu(pPayload->lr_status_evt_portid); | |
3092 | u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); | |
3093 | u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); | |
3094 | u8 phy_id = | |
3095 | (u8)((phyid_npip_portstate & 0xFF0000) >> 16); | |
3096 | u16 eventType = | |
3097 | (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8); | |
3098 | u8 status = | |
3099 | (u8)((lr_status_evt_portid & 0x0F000000) >> 24); | |
3100 | ||
3101 | struct sas_ha_struct *sas_ha = pm8001_ha->sas; | |
3102 | struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; | |
3103 | struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; | |
3104 | PM8001_MSG_DBG(pm8001_ha, | |
3105 | pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n", | |
3106 | port_id, phy_id, eventType, status)); | |
3107 | ||
3108 | switch (eventType) { | |
3109 | ||
3110 | case HW_EVENT_SAS_PHY_UP: | |
3111 | PM8001_MSG_DBG(pm8001_ha, | |
3112 | pm8001_printk("HW_EVENT_PHY_START_STATUS\n")); | |
3113 | hw_event_sas_phy_up(pm8001_ha, piomb); | |
3114 | break; | |
3115 | case HW_EVENT_SATA_PHY_UP: | |
3116 | PM8001_MSG_DBG(pm8001_ha, | |
3117 | pm8001_printk("HW_EVENT_SATA_PHY_UP\n")); | |
3118 | hw_event_sata_phy_up(pm8001_ha, piomb); | |
3119 | break; | |
3120 | case HW_EVENT_SATA_SPINUP_HOLD: | |
3121 | PM8001_MSG_DBG(pm8001_ha, | |
3122 | pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n")); | |
3123 | sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD); | |
3124 | break; | |
3125 | case HW_EVENT_PHY_DOWN: | |
3126 | PM8001_MSG_DBG(pm8001_ha, | |
3127 | pm8001_printk("HW_EVENT_PHY_DOWN\n")); | |
3128 | sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL); | |
3129 | phy->phy_attached = 0; | |
3130 | phy->phy_state = 0; | |
3131 | hw_event_phy_down(pm8001_ha, piomb); | |
3132 | break; | |
3133 | case HW_EVENT_PORT_INVALID: | |
3134 | PM8001_MSG_DBG(pm8001_ha, | |
3135 | pm8001_printk("HW_EVENT_PORT_INVALID\n")); | |
3136 | sas_phy_disconnected(sas_phy); | |
3137 | phy->phy_attached = 0; | |
3138 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); | |
3139 | break; | |
3140 | /* the broadcast change primitive received, tell the LIBSAS this event | |
3141 | to revalidate the sas domain*/ | |
3142 | case HW_EVENT_BROADCAST_CHANGE: | |
3143 | PM8001_MSG_DBG(pm8001_ha, | |
3144 | pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n")); | |
3145 | pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, | |
3146 | port_id, phy_id, 1, 0); | |
3147 | spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); | |
3148 | sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; | |
3149 | spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); | |
3150 | sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); | |
3151 | break; | |
3152 | case HW_EVENT_PHY_ERROR: | |
3153 | PM8001_MSG_DBG(pm8001_ha, | |
3154 | pm8001_printk("HW_EVENT_PHY_ERROR\n")); | |
3155 | sas_phy_disconnected(&phy->sas_phy); | |
3156 | phy->phy_attached = 0; | |
3157 | sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR); | |
3158 | break; | |
3159 | case HW_EVENT_BROADCAST_EXP: | |
3160 | PM8001_MSG_DBG(pm8001_ha, | |
3161 | pm8001_printk("HW_EVENT_BROADCAST_EXP\n")); | |
3162 | spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); | |
3163 | sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; | |
3164 | spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); | |
3165 | sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); | |
3166 | break; | |
3167 | case HW_EVENT_LINK_ERR_INVALID_DWORD: | |
3168 | PM8001_MSG_DBG(pm8001_ha, | |
3169 | pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n")); | |
3170 | pm80xx_hw_event_ack_req(pm8001_ha, 0, | |
3171 | HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); | |
3172 | sas_phy_disconnected(sas_phy); | |
3173 | phy->phy_attached = 0; | |
3174 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); | |
3175 | break; | |
3176 | case HW_EVENT_LINK_ERR_DISPARITY_ERROR: | |
3177 | PM8001_MSG_DBG(pm8001_ha, | |
3178 | pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n")); | |
3179 | pm80xx_hw_event_ack_req(pm8001_ha, 0, | |
3180 | HW_EVENT_LINK_ERR_DISPARITY_ERROR, | |
3181 | port_id, phy_id, 0, 0); | |
3182 | sas_phy_disconnected(sas_phy); | |
3183 | phy->phy_attached = 0; | |
3184 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); | |
3185 | break; | |
3186 | case HW_EVENT_LINK_ERR_CODE_VIOLATION: | |
3187 | PM8001_MSG_DBG(pm8001_ha, | |
3188 | pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n")); | |
3189 | pm80xx_hw_event_ack_req(pm8001_ha, 0, | |
3190 | HW_EVENT_LINK_ERR_CODE_VIOLATION, | |
3191 | port_id, phy_id, 0, 0); | |
3192 | sas_phy_disconnected(sas_phy); | |
3193 | phy->phy_attached = 0; | |
3194 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); | |
3195 | break; | |
3196 | case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH: | |
3197 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
3198 | "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n")); | |
3199 | pm80xx_hw_event_ack_req(pm8001_ha, 0, | |
3200 | HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH, | |
3201 | port_id, phy_id, 0, 0); | |
3202 | sas_phy_disconnected(sas_phy); | |
3203 | phy->phy_attached = 0; | |
3204 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); | |
3205 | break; | |
3206 | case HW_EVENT_MALFUNCTION: | |
3207 | PM8001_MSG_DBG(pm8001_ha, | |
3208 | pm8001_printk("HW_EVENT_MALFUNCTION\n")); | |
3209 | break; | |
3210 | case HW_EVENT_BROADCAST_SES: | |
3211 | PM8001_MSG_DBG(pm8001_ha, | |
3212 | pm8001_printk("HW_EVENT_BROADCAST_SES\n")); | |
3213 | spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); | |
3214 | sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; | |
3215 | spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); | |
3216 | sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); | |
3217 | break; | |
3218 | case HW_EVENT_INBOUND_CRC_ERROR: | |
3219 | PM8001_MSG_DBG(pm8001_ha, | |
3220 | pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n")); | |
3221 | pm80xx_hw_event_ack_req(pm8001_ha, 0, | |
3222 | HW_EVENT_INBOUND_CRC_ERROR, | |
3223 | port_id, phy_id, 0, 0); | |
3224 | break; | |
3225 | case HW_EVENT_HARD_RESET_RECEIVED: | |
3226 | PM8001_MSG_DBG(pm8001_ha, | |
3227 | pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n")); | |
3228 | sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET); | |
3229 | break; | |
3230 | case HW_EVENT_ID_FRAME_TIMEOUT: | |
3231 | PM8001_MSG_DBG(pm8001_ha, | |
3232 | pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n")); | |
3233 | sas_phy_disconnected(sas_phy); | |
3234 | phy->phy_attached = 0; | |
3235 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); | |
3236 | break; | |
3237 | case HW_EVENT_LINK_ERR_PHY_RESET_FAILED: | |
3238 | PM8001_MSG_DBG(pm8001_ha, | |
3239 | pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n")); | |
3240 | pm80xx_hw_event_ack_req(pm8001_ha, 0, | |
3241 | HW_EVENT_LINK_ERR_PHY_RESET_FAILED, | |
3242 | port_id, phy_id, 0, 0); | |
3243 | sas_phy_disconnected(sas_phy); | |
3244 | phy->phy_attached = 0; | |
3245 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); | |
3246 | break; | |
3247 | case HW_EVENT_PORT_RESET_TIMER_TMO: | |
3248 | PM8001_MSG_DBG(pm8001_ha, | |
3249 | pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n")); | |
3250 | sas_phy_disconnected(sas_phy); | |
3251 | phy->phy_attached = 0; | |
3252 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); | |
3253 | break; | |
3254 | case HW_EVENT_PORT_RECOVERY_TIMER_TMO: | |
3255 | PM8001_MSG_DBG(pm8001_ha, | |
3256 | pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n")); | |
a6cb3d01 S |
3257 | pm80xx_hw_event_ack_req(pm8001_ha, 0, |
3258 | HW_EVENT_PORT_RECOVERY_TIMER_TMO, | |
3259 | port_id, phy_id, 0, 0); | |
f5860992 S |
3260 | sas_phy_disconnected(sas_phy); |
3261 | phy->phy_attached = 0; | |
3262 | sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR); | |
3263 | break; | |
3264 | case HW_EVENT_PORT_RECOVER: | |
3265 | PM8001_MSG_DBG(pm8001_ha, | |
3266 | pm8001_printk("HW_EVENT_PORT_RECOVER\n")); | |
3267 | break; | |
3268 | case HW_EVENT_PORT_RESET_COMPLETE: | |
3269 | PM8001_MSG_DBG(pm8001_ha, | |
3270 | pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n")); | |
3271 | break; | |
3272 | case EVENT_BROADCAST_ASYNCH_EVENT: | |
3273 | PM8001_MSG_DBG(pm8001_ha, | |
3274 | pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n")); | |
3275 | break; | |
3276 | default: | |
3277 | PM8001_MSG_DBG(pm8001_ha, | |
3278 | pm8001_printk("Unknown event type 0x%x\n", eventType)); | |
3279 | break; | |
3280 | } | |
3281 | return 0; | |
3282 | } | |
3283 | ||
3284 | /** | |
3285 | * mpi_phy_stop_resp - SPCv specific | |
3286 | * @pm8001_ha: our hba card information | |
3287 | * @piomb: IO message buffer | |
3288 | */ | |
3289 | static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) | |
3290 | { | |
3291 | struct phy_stop_resp *pPayload = | |
3292 | (struct phy_stop_resp *)(piomb + 4); | |
3293 | u32 status = | |
3294 | le32_to_cpu(pPayload->status); | |
3295 | u32 phyid = | |
3296 | le32_to_cpu(pPayload->phyid); | |
3297 | struct pm8001_phy *phy = &pm8001_ha->phy[phyid]; | |
3298 | PM8001_MSG_DBG(pm8001_ha, | |
3299 | pm8001_printk("phy:0x%x status:0x%x\n", | |
3300 | phyid, status)); | |
3301 | if (status == 0) | |
3302 | phy->phy_state = 0; | |
3303 | return 0; | |
3304 | } | |
3305 | ||
3306 | /** | |
3307 | * mpi_set_controller_config_resp - SPCv specific | |
3308 | * @pm8001_ha: our hba card information | |
3309 | * @piomb: IO message buffer | |
3310 | */ | |
3311 | static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha, | |
3312 | void *piomb) | |
3313 | { | |
3314 | struct set_ctrl_cfg_resp *pPayload = | |
3315 | (struct set_ctrl_cfg_resp *)(piomb + 4); | |
3316 | u32 status = le32_to_cpu(pPayload->status); | |
3317 | u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd); | |
3318 | ||
3319 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
3320 | "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n", | |
3321 | status, err_qlfr_pgcd)); | |
3322 | ||
3323 | return 0; | |
3324 | } | |
3325 | ||
3326 | /** | |
3327 | * mpi_get_controller_config_resp - SPCv specific | |
3328 | * @pm8001_ha: our hba card information | |
3329 | * @piomb: IO message buffer | |
3330 | */ | |
3331 | static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha, | |
3332 | void *piomb) | |
3333 | { | |
3334 | PM8001_MSG_DBG(pm8001_ha, | |
3335 | pm8001_printk(" pm80xx_addition_functionality\n")); | |
3336 | ||
3337 | return 0; | |
3338 | } | |
3339 | ||
3340 | /** | |
3341 | * mpi_get_phy_profile_resp - SPCv specific | |
3342 | * @pm8001_ha: our hba card information | |
3343 | * @piomb: IO message buffer | |
3344 | */ | |
3345 | static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, | |
3346 | void *piomb) | |
3347 | { | |
3348 | PM8001_MSG_DBG(pm8001_ha, | |
3349 | pm8001_printk(" pm80xx_addition_functionality\n")); | |
3350 | ||
3351 | return 0; | |
3352 | } | |
3353 | ||
3354 | /** | |
3355 | * mpi_flash_op_ext_resp - SPCv specific | |
3356 | * @pm8001_ha: our hba card information | |
3357 | * @piomb: IO message buffer | |
3358 | */ | |
3359 | static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) | |
3360 | { | |
3361 | PM8001_MSG_DBG(pm8001_ha, | |
3362 | pm8001_printk(" pm80xx_addition_functionality\n")); | |
3363 | ||
3364 | return 0; | |
3365 | } | |
3366 | ||
3367 | /** | |
3368 | * mpi_set_phy_profile_resp - SPCv specific | |
3369 | * @pm8001_ha: our hba card information | |
3370 | * @piomb: IO message buffer | |
3371 | */ | |
3372 | static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha, | |
3373 | void *piomb) | |
3374 | { | |
27909407 AKS |
3375 | u8 page_code; |
3376 | struct set_phy_profile_resp *pPayload = | |
3377 | (struct set_phy_profile_resp *)(piomb + 4); | |
3378 | u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid); | |
3379 | u32 status = le32_to_cpu(pPayload->status); | |
f5860992 | 3380 | |
27909407 AKS |
3381 | page_code = (u8)((ppc_phyid & 0xFF00) >> 8); |
3382 | if (status) { | |
3383 | /* status is FAILED */ | |
3384 | PM8001_FAIL_DBG(pm8001_ha, | |
3385 | pm8001_printk("PhyProfile command failed with status " | |
3386 | "0x%08X \n", status)); | |
3387 | return -1; | |
3388 | } else { | |
3389 | if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) { | |
3390 | PM8001_FAIL_DBG(pm8001_ha, | |
3391 | pm8001_printk("Invalid page code 0x%X\n", | |
3392 | page_code)); | |
3393 | return -1; | |
3394 | } | |
3395 | } | |
f5860992 S |
3396 | return 0; |
3397 | } | |
3398 | ||
3399 | /** | |
3400 | * mpi_kek_management_resp - SPCv specific | |
3401 | * @pm8001_ha: our hba card information | |
3402 | * @piomb: IO message buffer | |
3403 | */ | |
3404 | static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha, | |
3405 | void *piomb) | |
3406 | { | |
3407 | struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4); | |
3408 | ||
3409 | u32 status = le32_to_cpu(pPayload->status); | |
3410 | u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop); | |
3411 | u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr); | |
3412 | ||
3413 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
3414 | "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n", | |
3415 | status, kidx_new_curr_ksop, err_qlfr)); | |
3416 | ||
3417 | return 0; | |
3418 | } | |
3419 | ||
3420 | /** | |
3421 | * mpi_dek_management_resp - SPCv specific | |
3422 | * @pm8001_ha: our hba card information | |
3423 | * @piomb: IO message buffer | |
3424 | */ | |
3425 | static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha, | |
3426 | void *piomb) | |
3427 | { | |
3428 | PM8001_MSG_DBG(pm8001_ha, | |
3429 | pm8001_printk(" pm80xx_addition_functionality\n")); | |
3430 | ||
3431 | return 0; | |
3432 | } | |
3433 | ||
3434 | /** | |
3435 | * ssp_coalesced_comp_resp - SPCv specific | |
3436 | * @pm8001_ha: our hba card information | |
3437 | * @piomb: IO message buffer | |
3438 | */ | |
3439 | static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha, | |
3440 | void *piomb) | |
3441 | { | |
3442 | PM8001_MSG_DBG(pm8001_ha, | |
3443 | pm8001_printk(" pm80xx_addition_functionality\n")); | |
3444 | ||
3445 | return 0; | |
3446 | } | |
3447 | ||
3448 | /** | |
3449 | * process_one_iomb - process one outbound Queue memory block | |
3450 | * @pm8001_ha: our hba card information | |
3451 | * @piomb: IO message buffer | |
3452 | */ | |
3453 | static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) | |
3454 | { | |
3455 | __le32 pHeader = *(__le32 *)piomb; | |
3456 | u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF); | |
3457 | ||
3458 | switch (opc) { | |
3459 | case OPC_OUB_ECHO: | |
3460 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n")); | |
3461 | break; | |
3462 | case OPC_OUB_HW_EVENT: | |
3463 | PM8001_MSG_DBG(pm8001_ha, | |
3464 | pm8001_printk("OPC_OUB_HW_EVENT\n")); | |
3465 | mpi_hw_event(pm8001_ha, piomb); | |
3466 | break; | |
3467 | case OPC_OUB_THERM_HW_EVENT: | |
3468 | PM8001_MSG_DBG(pm8001_ha, | |
3469 | pm8001_printk("OPC_OUB_THERMAL_EVENT\n")); | |
3470 | mpi_thermal_hw_event(pm8001_ha, piomb); | |
3471 | break; | |
3472 | case OPC_OUB_SSP_COMP: | |
3473 | PM8001_MSG_DBG(pm8001_ha, | |
3474 | pm8001_printk("OPC_OUB_SSP_COMP\n")); | |
3475 | mpi_ssp_completion(pm8001_ha, piomb); | |
3476 | break; | |
3477 | case OPC_OUB_SMP_COMP: | |
3478 | PM8001_MSG_DBG(pm8001_ha, | |
3479 | pm8001_printk("OPC_OUB_SMP_COMP\n")); | |
3480 | mpi_smp_completion(pm8001_ha, piomb); | |
3481 | break; | |
3482 | case OPC_OUB_LOCAL_PHY_CNTRL: | |
3483 | PM8001_MSG_DBG(pm8001_ha, | |
3484 | pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n")); | |
3485 | pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); | |
3486 | break; | |
3487 | case OPC_OUB_DEV_REGIST: | |
3488 | PM8001_MSG_DBG(pm8001_ha, | |
3489 | pm8001_printk("OPC_OUB_DEV_REGIST\n")); | |
3490 | pm8001_mpi_reg_resp(pm8001_ha, piomb); | |
3491 | break; | |
3492 | case OPC_OUB_DEREG_DEV: | |
3493 | PM8001_MSG_DBG(pm8001_ha, | |
8b513d0c | 3494 | pm8001_printk("unregister the device\n")); |
f5860992 S |
3495 | pm8001_mpi_dereg_resp(pm8001_ha, piomb); |
3496 | break; | |
3497 | case OPC_OUB_GET_DEV_HANDLE: | |
3498 | PM8001_MSG_DBG(pm8001_ha, | |
3499 | pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n")); | |
3500 | break; | |
3501 | case OPC_OUB_SATA_COMP: | |
3502 | PM8001_MSG_DBG(pm8001_ha, | |
3503 | pm8001_printk("OPC_OUB_SATA_COMP\n")); | |
3504 | mpi_sata_completion(pm8001_ha, piomb); | |
3505 | break; | |
3506 | case OPC_OUB_SATA_EVENT: | |
3507 | PM8001_MSG_DBG(pm8001_ha, | |
3508 | pm8001_printk("OPC_OUB_SATA_EVENT\n")); | |
3509 | mpi_sata_event(pm8001_ha, piomb); | |
3510 | break; | |
3511 | case OPC_OUB_SSP_EVENT: | |
3512 | PM8001_MSG_DBG(pm8001_ha, | |
3513 | pm8001_printk("OPC_OUB_SSP_EVENT\n")); | |
3514 | mpi_ssp_event(pm8001_ha, piomb); | |
3515 | break; | |
3516 | case OPC_OUB_DEV_HANDLE_ARRIV: | |
3517 | PM8001_MSG_DBG(pm8001_ha, | |
3518 | pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n")); | |
3519 | /*This is for target*/ | |
3520 | break; | |
3521 | case OPC_OUB_SSP_RECV_EVENT: | |
3522 | PM8001_MSG_DBG(pm8001_ha, | |
3523 | pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n")); | |
3524 | /*This is for target*/ | |
3525 | break; | |
3526 | case OPC_OUB_FW_FLASH_UPDATE: | |
3527 | PM8001_MSG_DBG(pm8001_ha, | |
3528 | pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n")); | |
3529 | pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); | |
3530 | break; | |
3531 | case OPC_OUB_GPIO_RESPONSE: | |
3532 | PM8001_MSG_DBG(pm8001_ha, | |
3533 | pm8001_printk("OPC_OUB_GPIO_RESPONSE\n")); | |
3534 | break; | |
3535 | case OPC_OUB_GPIO_EVENT: | |
3536 | PM8001_MSG_DBG(pm8001_ha, | |
3537 | pm8001_printk("OPC_OUB_GPIO_EVENT\n")); | |
3538 | break; | |
3539 | case OPC_OUB_GENERAL_EVENT: | |
3540 | PM8001_MSG_DBG(pm8001_ha, | |
3541 | pm8001_printk("OPC_OUB_GENERAL_EVENT\n")); | |
3542 | pm8001_mpi_general_event(pm8001_ha, piomb); | |
3543 | break; | |
3544 | case OPC_OUB_SSP_ABORT_RSP: | |
3545 | PM8001_MSG_DBG(pm8001_ha, | |
3546 | pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n")); | |
3547 | pm8001_mpi_task_abort_resp(pm8001_ha, piomb); | |
3548 | break; | |
3549 | case OPC_OUB_SATA_ABORT_RSP: | |
3550 | PM8001_MSG_DBG(pm8001_ha, | |
3551 | pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n")); | |
3552 | pm8001_mpi_task_abort_resp(pm8001_ha, piomb); | |
3553 | break; | |
3554 | case OPC_OUB_SAS_DIAG_MODE_START_END: | |
3555 | PM8001_MSG_DBG(pm8001_ha, | |
3556 | pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n")); | |
3557 | break; | |
3558 | case OPC_OUB_SAS_DIAG_EXECUTE: | |
3559 | PM8001_MSG_DBG(pm8001_ha, | |
3560 | pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n")); | |
3561 | break; | |
3562 | case OPC_OUB_GET_TIME_STAMP: | |
3563 | PM8001_MSG_DBG(pm8001_ha, | |
3564 | pm8001_printk("OPC_OUB_GET_TIME_STAMP\n")); | |
3565 | break; | |
3566 | case OPC_OUB_SAS_HW_EVENT_ACK: | |
3567 | PM8001_MSG_DBG(pm8001_ha, | |
3568 | pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n")); | |
3569 | break; | |
3570 | case OPC_OUB_PORT_CONTROL: | |
3571 | PM8001_MSG_DBG(pm8001_ha, | |
3572 | pm8001_printk("OPC_OUB_PORT_CONTROL\n")); | |
3573 | break; | |
3574 | case OPC_OUB_SMP_ABORT_RSP: | |
3575 | PM8001_MSG_DBG(pm8001_ha, | |
3576 | pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n")); | |
3577 | pm8001_mpi_task_abort_resp(pm8001_ha, piomb); | |
3578 | break; | |
3579 | case OPC_OUB_GET_NVMD_DATA: | |
3580 | PM8001_MSG_DBG(pm8001_ha, | |
3581 | pm8001_printk("OPC_OUB_GET_NVMD_DATA\n")); | |
3582 | pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); | |
3583 | break; | |
3584 | case OPC_OUB_SET_NVMD_DATA: | |
3585 | PM8001_MSG_DBG(pm8001_ha, | |
3586 | pm8001_printk("OPC_OUB_SET_NVMD_DATA\n")); | |
3587 | pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); | |
3588 | break; | |
3589 | case OPC_OUB_DEVICE_HANDLE_REMOVAL: | |
3590 | PM8001_MSG_DBG(pm8001_ha, | |
3591 | pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n")); | |
3592 | break; | |
3593 | case OPC_OUB_SET_DEVICE_STATE: | |
3594 | PM8001_MSG_DBG(pm8001_ha, | |
3595 | pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n")); | |
3596 | pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); | |
3597 | break; | |
3598 | case OPC_OUB_GET_DEVICE_STATE: | |
3599 | PM8001_MSG_DBG(pm8001_ha, | |
3600 | pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n")); | |
3601 | break; | |
3602 | case OPC_OUB_SET_DEV_INFO: | |
3603 | PM8001_MSG_DBG(pm8001_ha, | |
3604 | pm8001_printk("OPC_OUB_SET_DEV_INFO\n")); | |
3605 | break; | |
3606 | /* spcv specifc commands */ | |
3607 | case OPC_OUB_PHY_START_RESP: | |
3608 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
3609 | "OPC_OUB_PHY_START_RESP opcode:%x\n", opc)); | |
3610 | mpi_phy_start_resp(pm8001_ha, piomb); | |
3611 | break; | |
3612 | case OPC_OUB_PHY_STOP_RESP: | |
3613 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
3614 | "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc)); | |
3615 | mpi_phy_stop_resp(pm8001_ha, piomb); | |
3616 | break; | |
3617 | case OPC_OUB_SET_CONTROLLER_CONFIG: | |
3618 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
3619 | "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc)); | |
3620 | mpi_set_controller_config_resp(pm8001_ha, piomb); | |
3621 | break; | |
3622 | case OPC_OUB_GET_CONTROLLER_CONFIG: | |
3623 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
3624 | "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc)); | |
3625 | mpi_get_controller_config_resp(pm8001_ha, piomb); | |
3626 | break; | |
3627 | case OPC_OUB_GET_PHY_PROFILE: | |
3628 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
3629 | "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc)); | |
3630 | mpi_get_phy_profile_resp(pm8001_ha, piomb); | |
3631 | break; | |
3632 | case OPC_OUB_FLASH_OP_EXT: | |
3633 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
3634 | "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc)); | |
3635 | mpi_flash_op_ext_resp(pm8001_ha, piomb); | |
3636 | break; | |
3637 | case OPC_OUB_SET_PHY_PROFILE: | |
3638 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
3639 | "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc)); | |
3640 | mpi_set_phy_profile_resp(pm8001_ha, piomb); | |
3641 | break; | |
3642 | case OPC_OUB_KEK_MANAGEMENT_RESP: | |
3643 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
3644 | "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc)); | |
3645 | mpi_kek_management_resp(pm8001_ha, piomb); | |
3646 | break; | |
3647 | case OPC_OUB_DEK_MANAGEMENT_RESP: | |
3648 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
3649 | "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc)); | |
3650 | mpi_dek_management_resp(pm8001_ha, piomb); | |
3651 | break; | |
3652 | case OPC_OUB_SSP_COALESCED_COMP_RESP: | |
3653 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
3654 | "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc)); | |
3655 | ssp_coalesced_comp_resp(pm8001_ha, piomb); | |
3656 | break; | |
3657 | default: | |
3658 | PM8001_MSG_DBG(pm8001_ha, pm8001_printk( | |
3659 | "Unknown outbound Queue IOMB OPC = 0x%x\n", opc)); | |
3660 | break; | |
3661 | } | |
3662 | } | |
3663 | ||
3664 | static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) | |
3665 | { | |
3666 | struct outbound_queue_table *circularQ; | |
3667 | void *pMsg1 = NULL; | |
3668 | u8 uninitialized_var(bc); | |
3669 | u32 ret = MPI_IO_STATUS_FAIL; | |
3670 | unsigned long flags; | |
3671 | ||
3672 | spin_lock_irqsave(&pm8001_ha->lock, flags); | |
3673 | circularQ = &pm8001_ha->outbnd_q_tbl[vec]; | |
3674 | do { | |
3675 | ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); | |
3676 | if (MPI_IO_STATUS_SUCCESS == ret) { | |
3677 | /* process the outbound message */ | |
3678 | process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); | |
3679 | /* free the message from the outbound circular buffer */ | |
3680 | pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, | |
3681 | circularQ, bc); | |
3682 | } | |
3683 | if (MPI_IO_STATUS_BUSY == ret) { | |
3684 | /* Update the producer index from SPC */ | |
3685 | circularQ->producer_index = | |
3686 | cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); | |
3687 | if (le32_to_cpu(circularQ->producer_index) == | |
3688 | circularQ->consumer_idx) | |
3689 | /* OQ is empty */ | |
3690 | break; | |
3691 | } | |
3692 | } while (1); | |
3693 | spin_unlock_irqrestore(&pm8001_ha->lock, flags); | |
3694 | return ret; | |
3695 | } | |
3696 | ||
3697 | /* PCI_DMA_... to our direction translation. */ | |
3698 | static const u8 data_dir_flags[] = { | |
3699 | [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */ | |
3700 | [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */ | |
3701 | [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */ | |
3702 | [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */ | |
3703 | }; | |
3704 | ||
3705 | static void build_smp_cmd(u32 deviceID, __le32 hTag, | |
3706 | struct smp_req *psmp_cmd, int mode, int length) | |
3707 | { | |
3708 | psmp_cmd->tag = hTag; | |
3709 | psmp_cmd->device_id = cpu_to_le32(deviceID); | |
3710 | if (mode == SMP_DIRECT) { | |
3711 | length = length - 4; /* subtract crc */ | |
3712 | psmp_cmd->len_ip_ir = cpu_to_le32(length << 16); | |
3713 | } else { | |
3714 | psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); | |
3715 | } | |
3716 | } | |
3717 | ||
3718 | /** | |
3719 | * pm8001_chip_smp_req - send a SMP task to FW | |
3720 | * @pm8001_ha: our hba card information. | |
3721 | * @ccb: the ccb information this request used. | |
3722 | */ | |
3723 | static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha, | |
3724 | struct pm8001_ccb_info *ccb) | |
3725 | { | |
3726 | int elem, rc; | |
3727 | struct sas_task *task = ccb->task; | |
3728 | struct domain_device *dev = task->dev; | |
3729 | struct pm8001_device *pm8001_dev = dev->lldd_dev; | |
3730 | struct scatterlist *sg_req, *sg_resp; | |
3731 | u32 req_len, resp_len; | |
3732 | struct smp_req smp_cmd; | |
3733 | u32 opc; | |
3734 | struct inbound_queue_table *circularQ; | |
3735 | char *preq_dma_addr = NULL; | |
3736 | __le64 tmp_addr; | |
3737 | u32 i, length; | |
3738 | ||
3739 | memset(&smp_cmd, 0, sizeof(smp_cmd)); | |
3740 | /* | |
3741 | * DMA-map SMP request, response buffers | |
3742 | */ | |
3743 | sg_req = &task->smp_task.smp_req; | |
3744 | elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE); | |
3745 | if (!elem) | |
3746 | return -ENOMEM; | |
3747 | req_len = sg_dma_len(sg_req); | |
3748 | ||
3749 | sg_resp = &task->smp_task.smp_resp; | |
3750 | elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE); | |
3751 | if (!elem) { | |
3752 | rc = -ENOMEM; | |
3753 | goto err_out; | |
3754 | } | |
3755 | resp_len = sg_dma_len(sg_resp); | |
3756 | /* must be in dwords */ | |
3757 | if ((req_len & 0x3) || (resp_len & 0x3)) { | |
3758 | rc = -EINVAL; | |
3759 | goto err_out_2; | |
3760 | } | |
3761 | ||
3762 | opc = OPC_INB_SMP_REQUEST; | |
3763 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; | |
3764 | smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); | |
3765 | ||
3766 | length = sg_req->length; | |
3767 | PM8001_IO_DBG(pm8001_ha, | |
3768 | pm8001_printk("SMP Frame Length %d\n", sg_req->length)); | |
3769 | if (!(length - 8)) | |
3770 | pm8001_ha->smp_exp_mode = SMP_DIRECT; | |
3771 | else | |
3772 | pm8001_ha->smp_exp_mode = SMP_INDIRECT; | |
3773 | ||
f5860992 S |
3774 | |
3775 | tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req)); | |
3776 | preq_dma_addr = (char *)phys_to_virt(tmp_addr); | |
3777 | ||
3778 | /* INDIRECT MODE command settings. Use DMA */ | |
3779 | if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) { | |
3780 | PM8001_IO_DBG(pm8001_ha, | |
3781 | pm8001_printk("SMP REQUEST INDIRECT MODE\n")); | |
3782 | /* for SPCv indirect mode. Place the top 4 bytes of | |
3783 | * SMP Request header here. */ | |
3784 | for (i = 0; i < 4; i++) | |
3785 | smp_cmd.smp_req16[i] = *(preq_dma_addr + i); | |
3786 | /* exclude top 4 bytes for SMP req header */ | |
3787 | smp_cmd.long_smp_req.long_req_addr = | |
3788 | cpu_to_le64((u64)sg_dma_address | |
cb993e5d | 3789 | (&task->smp_task.smp_req) + 4); |
f5860992 S |
3790 | /* exclude 4 bytes for SMP req header and CRC */ |
3791 | smp_cmd.long_smp_req.long_req_size = | |
3792 | cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8); | |
3793 | smp_cmd.long_smp_req.long_resp_addr = | |
3794 | cpu_to_le64((u64)sg_dma_address | |
3795 | (&task->smp_task.smp_resp)); | |
3796 | smp_cmd.long_smp_req.long_resp_size = | |
3797 | cpu_to_le32((u32)sg_dma_len | |
3798 | (&task->smp_task.smp_resp)-4); | |
3799 | } else { /* DIRECT MODE */ | |
3800 | smp_cmd.long_smp_req.long_req_addr = | |
3801 | cpu_to_le64((u64)sg_dma_address | |
3802 | (&task->smp_task.smp_req)); | |
3803 | smp_cmd.long_smp_req.long_req_size = | |
3804 | cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); | |
3805 | smp_cmd.long_smp_req.long_resp_addr = | |
3806 | cpu_to_le64((u64)sg_dma_address | |
3807 | (&task->smp_task.smp_resp)); | |
3808 | smp_cmd.long_smp_req.long_resp_size = | |
3809 | cpu_to_le32 | |
3810 | ((u32)sg_dma_len(&task->smp_task.smp_resp)-4); | |
3811 | } | |
3812 | if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { | |
3813 | PM8001_IO_DBG(pm8001_ha, | |
3814 | pm8001_printk("SMP REQUEST DIRECT MODE\n")); | |
3815 | for (i = 0; i < length; i++) | |
3816 | if (i < 16) { | |
3817 | smp_cmd.smp_req16[i] = *(preq_dma_addr+i); | |
3818 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
3819 | "Byte[%d]:%x (DMA data:%x)\n", | |
3820 | i, smp_cmd.smp_req16[i], | |
3821 | *(preq_dma_addr))); | |
3822 | } else { | |
3823 | smp_cmd.smp_req[i] = *(preq_dma_addr+i); | |
3824 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
3825 | "Byte[%d]:%x (DMA data:%x)\n", | |
3826 | i, smp_cmd.smp_req[i], | |
3827 | *(preq_dma_addr))); | |
3828 | } | |
3829 | } | |
3830 | ||
3831 | build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, | |
3832 | &smp_cmd, pm8001_ha->smp_exp_mode, length); | |
5533abca TH |
3833 | rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, |
3834 | (u32 *)&smp_cmd, 0); | |
3835 | if (rc) | |
3836 | goto err_out_2; | |
f5860992 S |
3837 | return 0; |
3838 | ||
3839 | err_out_2: | |
3840 | dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, | |
3841 | PCI_DMA_FROMDEVICE); | |
3842 | err_out: | |
3843 | dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, | |
3844 | PCI_DMA_TODEVICE); | |
3845 | return rc; | |
3846 | } | |
3847 | ||
3848 | static int check_enc_sas_cmd(struct sas_task *task) | |
3849 | { | |
e73823f7 JB |
3850 | u8 cmd = task->ssp_task.cmd->cmnd[0]; |
3851 | ||
3852 | if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY) | |
f5860992 S |
3853 | return 1; |
3854 | else | |
3855 | return 0; | |
3856 | } | |
3857 | ||
3858 | static int check_enc_sat_cmd(struct sas_task *task) | |
3859 | { | |
3860 | int ret = 0; | |
3861 | switch (task->ata_task.fis.command) { | |
3862 | case ATA_CMD_FPDMA_READ: | |
3863 | case ATA_CMD_READ_EXT: | |
3864 | case ATA_CMD_READ: | |
3865 | case ATA_CMD_FPDMA_WRITE: | |
3866 | case ATA_CMD_WRITE_EXT: | |
3867 | case ATA_CMD_WRITE: | |
3868 | case ATA_CMD_PIO_READ: | |
3869 | case ATA_CMD_PIO_READ_EXT: | |
3870 | case ATA_CMD_PIO_WRITE: | |
3871 | case ATA_CMD_PIO_WRITE_EXT: | |
3872 | ret = 1; | |
3873 | break; | |
3874 | default: | |
3875 | ret = 0; | |
3876 | break; | |
3877 | } | |
3878 | return ret; | |
3879 | } | |
3880 | ||
3881 | /** | |
3882 | * pm80xx_chip_ssp_io_req - send a SSP task to FW | |
3883 | * @pm8001_ha: our hba card information. | |
3884 | * @ccb: the ccb information this request used. | |
3885 | */ | |
3886 | static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, | |
3887 | struct pm8001_ccb_info *ccb) | |
3888 | { | |
3889 | struct sas_task *task = ccb->task; | |
3890 | struct domain_device *dev = task->dev; | |
3891 | struct pm8001_device *pm8001_dev = dev->lldd_dev; | |
3892 | struct ssp_ini_io_start_req ssp_cmd; | |
3893 | u32 tag = ccb->ccb_tag; | |
3894 | int ret; | |
0ecdf00b AKS |
3895 | u64 phys_addr, start_addr, end_addr; |
3896 | u32 end_addr_high, end_addr_low; | |
f5860992 | 3897 | struct inbound_queue_table *circularQ; |
f9cd6cbd | 3898 | u32 q_index; |
f5860992 S |
3899 | u32 opc = OPC_INB_SSPINIIOSTART; |
3900 | memset(&ssp_cmd, 0, sizeof(ssp_cmd)); | |
3901 | memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); | |
3902 | /* data address domain added for spcv; set to 0 by host, | |
3903 | * used internally by controller | |
3904 | * 0 for SAS 1.1 and SAS 2.0 compatible TLR | |
3905 | */ | |
3906 | ssp_cmd.dad_dir_m_tlr = | |
3907 | cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0); | |
3908 | ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); | |
3909 | ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); | |
3910 | ssp_cmd.tag = cpu_to_le32(tag); | |
3911 | if (task->ssp_task.enable_first_burst) | |
3912 | ssp_cmd.ssp_iu.efb_prio_attr |= 0x80; | |
3913 | ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); | |
3914 | ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); | |
e73823f7 JB |
3915 | memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, |
3916 | task->ssp_task.cmd->cmd_len); | |
f9cd6cbd AKS |
3917 | q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM; |
3918 | circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; | |
f5860992 S |
3919 | |
3920 | /* Check if encryption is set */ | |
3921 | if (pm8001_ha->chip->encrypt && | |
3922 | !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) { | |
3923 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
3924 | "Encryption enabled.Sending Encrypt SAS command 0x%x\n", | |
e73823f7 | 3925 | task->ssp_task.cmd->cmnd[0])); |
f5860992 S |
3926 | opc = OPC_INB_SSP_INI_DIF_ENC_IO; |
3927 | /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/ | |
3928 | ssp_cmd.dad_dir_m_tlr = cpu_to_le32 | |
3929 | ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0); | |
3930 | ||
3931 | /* fill in PRD (scatter/gather) table, if any */ | |
3932 | if (task->num_scatter > 1) { | |
3933 | pm8001_chip_make_sg(task->scatter, | |
3934 | ccb->n_elem, ccb->buf_prd); | |
3935 | phys_addr = ccb->ccb_dma_handle + | |
3936 | offsetof(struct pm8001_ccb_info, buf_prd[0]); | |
3937 | ssp_cmd.enc_addr_low = | |
3938 | cpu_to_le32(lower_32_bits(phys_addr)); | |
3939 | ssp_cmd.enc_addr_high = | |
3940 | cpu_to_le32(upper_32_bits(phys_addr)); | |
3941 | ssp_cmd.enc_esgl = cpu_to_le32(1<<31); | |
3942 | } else if (task->num_scatter == 1) { | |
3943 | u64 dma_addr = sg_dma_address(task->scatter); | |
3944 | ssp_cmd.enc_addr_low = | |
3945 | cpu_to_le32(lower_32_bits(dma_addr)); | |
3946 | ssp_cmd.enc_addr_high = | |
3947 | cpu_to_le32(upper_32_bits(dma_addr)); | |
3948 | ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); | |
3949 | ssp_cmd.enc_esgl = 0; | |
0ecdf00b AKS |
3950 | /* Check 4G Boundary */ |
3951 | start_addr = cpu_to_le64(dma_addr); | |
3952 | end_addr = (start_addr + ssp_cmd.enc_len) - 1; | |
3953 | end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); | |
3954 | end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); | |
3955 | if (end_addr_high != ssp_cmd.enc_addr_high) { | |
3956 | PM8001_FAIL_DBG(pm8001_ha, | |
3957 | pm8001_printk("The sg list address " | |
3958 | "start_addr=0x%016llx data_len=0x%x " | |
3959 | "end_addr_high=0x%08x end_addr_low=" | |
3960 | "0x%08x has crossed 4G boundary\n", | |
3961 | start_addr, ssp_cmd.enc_len, | |
3962 | end_addr_high, end_addr_low)); | |
3963 | pm8001_chip_make_sg(task->scatter, 1, | |
3964 | ccb->buf_prd); | |
3965 | phys_addr = ccb->ccb_dma_handle + | |
3966 | offsetof(struct pm8001_ccb_info, | |
3967 | buf_prd[0]); | |
3968 | ssp_cmd.enc_addr_low = | |
3969 | cpu_to_le32(lower_32_bits(phys_addr)); | |
3970 | ssp_cmd.enc_addr_high = | |
3971 | cpu_to_le32(upper_32_bits(phys_addr)); | |
3972 | ssp_cmd.enc_esgl = cpu_to_le32(1<<31); | |
3973 | } | |
f5860992 S |
3974 | } else if (task->num_scatter == 0) { |
3975 | ssp_cmd.enc_addr_low = 0; | |
3976 | ssp_cmd.enc_addr_high = 0; | |
3977 | ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); | |
3978 | ssp_cmd.enc_esgl = 0; | |
3979 | } | |
3980 | /* XTS mode. All other fields are 0 */ | |
3981 | ssp_cmd.key_cmode = 0x6 << 4; | |
3982 | /* set tweak values. Should be the start lba */ | |
e73823f7 JB |
3983 | ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) | |
3984 | (task->ssp_task.cmd->cmnd[3] << 16) | | |
3985 | (task->ssp_task.cmd->cmnd[4] << 8) | | |
3986 | (task->ssp_task.cmd->cmnd[5])); | |
f5860992 S |
3987 | } else { |
3988 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
3989 | "Sending Normal SAS command 0x%x inb q %x\n", | |
f9cd6cbd | 3990 | task->ssp_task.cmd->cmnd[0], q_index)); |
f5860992 S |
3991 | /* fill in PRD (scatter/gather) table, if any */ |
3992 | if (task->num_scatter > 1) { | |
3993 | pm8001_chip_make_sg(task->scatter, ccb->n_elem, | |
3994 | ccb->buf_prd); | |
3995 | phys_addr = ccb->ccb_dma_handle + | |
3996 | offsetof(struct pm8001_ccb_info, buf_prd[0]); | |
3997 | ssp_cmd.addr_low = | |
3998 | cpu_to_le32(lower_32_bits(phys_addr)); | |
3999 | ssp_cmd.addr_high = | |
4000 | cpu_to_le32(upper_32_bits(phys_addr)); | |
4001 | ssp_cmd.esgl = cpu_to_le32(1<<31); | |
4002 | } else if (task->num_scatter == 1) { | |
4003 | u64 dma_addr = sg_dma_address(task->scatter); | |
4004 | ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr)); | |
4005 | ssp_cmd.addr_high = | |
4006 | cpu_to_le32(upper_32_bits(dma_addr)); | |
4007 | ssp_cmd.len = cpu_to_le32(task->total_xfer_len); | |
4008 | ssp_cmd.esgl = 0; | |
0ecdf00b AKS |
4009 | /* Check 4G Boundary */ |
4010 | start_addr = cpu_to_le64(dma_addr); | |
4011 | end_addr = (start_addr + ssp_cmd.len) - 1; | |
4012 | end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); | |
4013 | end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); | |
4014 | if (end_addr_high != ssp_cmd.addr_high) { | |
4015 | PM8001_FAIL_DBG(pm8001_ha, | |
4016 | pm8001_printk("The sg list address " | |
4017 | "start_addr=0x%016llx data_len=0x%x " | |
4018 | "end_addr_high=0x%08x end_addr_low=" | |
4019 | "0x%08x has crossed 4G boundary\n", | |
4020 | start_addr, ssp_cmd.len, | |
4021 | end_addr_high, end_addr_low)); | |
4022 | pm8001_chip_make_sg(task->scatter, 1, | |
4023 | ccb->buf_prd); | |
4024 | phys_addr = ccb->ccb_dma_handle + | |
4025 | offsetof(struct pm8001_ccb_info, | |
4026 | buf_prd[0]); | |
4027 | ssp_cmd.addr_low = | |
4028 | cpu_to_le32(lower_32_bits(phys_addr)); | |
4029 | ssp_cmd.addr_high = | |
4030 | cpu_to_le32(upper_32_bits(phys_addr)); | |
4031 | ssp_cmd.esgl = cpu_to_le32(1<<31); | |
4032 | } | |
f5860992 S |
4033 | } else if (task->num_scatter == 0) { |
4034 | ssp_cmd.addr_low = 0; | |
4035 | ssp_cmd.addr_high = 0; | |
4036 | ssp_cmd.len = cpu_to_le32(task->total_xfer_len); | |
4037 | ssp_cmd.esgl = 0; | |
4038 | } | |
4039 | } | |
f9cd6cbd AKS |
4040 | q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM; |
4041 | ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, | |
4042 | &ssp_cmd, q_index); | |
f5860992 S |
4043 | return ret; |
4044 | } | |
4045 | ||
4046 | static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha, | |
4047 | struct pm8001_ccb_info *ccb) | |
4048 | { | |
4049 | struct sas_task *task = ccb->task; | |
4050 | struct domain_device *dev = task->dev; | |
4051 | struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; | |
4052 | u32 tag = ccb->ccb_tag; | |
4053 | int ret; | |
f9cd6cbd | 4054 | u32 q_index; |
f5860992 S |
4055 | struct sata_start_req sata_cmd; |
4056 | u32 hdr_tag, ncg_tag = 0; | |
0ecdf00b AKS |
4057 | u64 phys_addr, start_addr, end_addr; |
4058 | u32 end_addr_high, end_addr_low; | |
f5860992 S |
4059 | u32 ATAP = 0x0; |
4060 | u32 dir; | |
4061 | struct inbound_queue_table *circularQ; | |
c6b9ef57 | 4062 | unsigned long flags; |
f5860992 S |
4063 | u32 opc = OPC_INB_SATA_HOST_OPSTART; |
4064 | memset(&sata_cmd, 0, sizeof(sata_cmd)); | |
f9cd6cbd AKS |
4065 | q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM; |
4066 | circularQ = &pm8001_ha->inbnd_q_tbl[q_index]; | |
f5860992 S |
4067 | |
4068 | if (task->data_dir == PCI_DMA_NONE) { | |
4069 | ATAP = 0x04; /* no data*/ | |
4070 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n")); | |
4071 | } else if (likely(!task->ata_task.device_control_reg_update)) { | |
4072 | if (task->ata_task.dma_xfer) { | |
4073 | ATAP = 0x06; /* DMA */ | |
4074 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n")); | |
4075 | } else { | |
4076 | ATAP = 0x05; /* PIO*/ | |
4077 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n")); | |
4078 | } | |
4079 | if (task->ata_task.use_ncq && | |
1cbd772d | 4080 | dev->sata_dev.class != ATA_DEV_ATAPI) { |
f5860992 S |
4081 | ATAP = 0x07; /* FPDMA */ |
4082 | PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n")); | |
4083 | } | |
4084 | } | |
c6b9ef57 S |
4085 | if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { |
4086 | task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); | |
f5860992 | 4087 | ncg_tag = hdr_tag; |
c6b9ef57 | 4088 | } |
f5860992 S |
4089 | dir = data_dir_flags[task->data_dir] << 8; |
4090 | sata_cmd.tag = cpu_to_le32(tag); | |
4091 | sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); | |
4092 | sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); | |
4093 | ||
4094 | sata_cmd.sata_fis = task->ata_task.fis; | |
4095 | if (likely(!task->ata_task.device_control_reg_update)) | |
4096 | sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ | |
4097 | sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ | |
4098 | ||
4099 | /* Check if encryption is set */ | |
4100 | if (pm8001_ha->chip->encrypt && | |
4101 | !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) { | |
4102 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
4103 | "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n", | |
4104 | sata_cmd.sata_fis.command)); | |
4105 | opc = OPC_INB_SATA_DIF_ENC_IO; | |
4106 | ||
4107 | /* set encryption bit */ | |
4108 | sata_cmd.ncqtag_atap_dir_m_dad = | |
4109 | cpu_to_le32(((ncg_tag & 0xff)<<16)| | |
4110 | ((ATAP & 0x3f) << 10) | 0x20 | dir); | |
4111 | /* dad (bit 0-1) is 0 */ | |
4112 | /* fill in PRD (scatter/gather) table, if any */ | |
4113 | if (task->num_scatter > 1) { | |
4114 | pm8001_chip_make_sg(task->scatter, | |
4115 | ccb->n_elem, ccb->buf_prd); | |
4116 | phys_addr = ccb->ccb_dma_handle + | |
4117 | offsetof(struct pm8001_ccb_info, buf_prd[0]); | |
4118 | sata_cmd.enc_addr_low = lower_32_bits(phys_addr); | |
4119 | sata_cmd.enc_addr_high = upper_32_bits(phys_addr); | |
4120 | sata_cmd.enc_esgl = cpu_to_le32(1 << 31); | |
4121 | } else if (task->num_scatter == 1) { | |
4122 | u64 dma_addr = sg_dma_address(task->scatter); | |
4123 | sata_cmd.enc_addr_low = lower_32_bits(dma_addr); | |
4124 | sata_cmd.enc_addr_high = upper_32_bits(dma_addr); | |
4125 | sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); | |
4126 | sata_cmd.enc_esgl = 0; | |
0ecdf00b AKS |
4127 | /* Check 4G Boundary */ |
4128 | start_addr = cpu_to_le64(dma_addr); | |
4129 | end_addr = (start_addr + sata_cmd.enc_len) - 1; | |
4130 | end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); | |
4131 | end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); | |
4132 | if (end_addr_high != sata_cmd.enc_addr_high) { | |
4133 | PM8001_FAIL_DBG(pm8001_ha, | |
4134 | pm8001_printk("The sg list address " | |
4135 | "start_addr=0x%016llx data_len=0x%x " | |
4136 | "end_addr_high=0x%08x end_addr_low" | |
4137 | "=0x%08x has crossed 4G boundary\n", | |
4138 | start_addr, sata_cmd.enc_len, | |
4139 | end_addr_high, end_addr_low)); | |
4140 | pm8001_chip_make_sg(task->scatter, 1, | |
4141 | ccb->buf_prd); | |
4142 | phys_addr = ccb->ccb_dma_handle + | |
4143 | offsetof(struct pm8001_ccb_info, | |
4144 | buf_prd[0]); | |
4145 | sata_cmd.enc_addr_low = | |
4146 | lower_32_bits(phys_addr); | |
4147 | sata_cmd.enc_addr_high = | |
4148 | upper_32_bits(phys_addr); | |
4149 | sata_cmd.enc_esgl = | |
4150 | cpu_to_le32(1 << 31); | |
4151 | } | |
f5860992 S |
4152 | } else if (task->num_scatter == 0) { |
4153 | sata_cmd.enc_addr_low = 0; | |
4154 | sata_cmd.enc_addr_high = 0; | |
4155 | sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); | |
4156 | sata_cmd.enc_esgl = 0; | |
4157 | } | |
4158 | /* XTS mode. All other fields are 0 */ | |
4159 | sata_cmd.key_index_mode = 0x6 << 4; | |
4160 | /* set tweak values. Should be the start lba */ | |
4161 | sata_cmd.twk_val0 = | |
4162 | cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) | | |
4163 | (sata_cmd.sata_fis.lbah << 16) | | |
4164 | (sata_cmd.sata_fis.lbam << 8) | | |
4165 | (sata_cmd.sata_fis.lbal)); | |
4166 | sata_cmd.twk_val1 = | |
4167 | cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) | | |
4168 | (sata_cmd.sata_fis.lbam_exp)); | |
4169 | } else { | |
4170 | PM8001_IO_DBG(pm8001_ha, pm8001_printk( | |
4171 | "Sending Normal SATA command 0x%x inb %x\n", | |
f9cd6cbd | 4172 | sata_cmd.sata_fis.command, q_index)); |
f5860992 S |
4173 | /* dad (bit 0-1) is 0 */ |
4174 | sata_cmd.ncqtag_atap_dir_m_dad = | |
4175 | cpu_to_le32(((ncg_tag & 0xff)<<16) | | |
4176 | ((ATAP & 0x3f) << 10) | dir); | |
4177 | ||
4178 | /* fill in PRD (scatter/gather) table, if any */ | |
4179 | if (task->num_scatter > 1) { | |
4180 | pm8001_chip_make_sg(task->scatter, | |
4181 | ccb->n_elem, ccb->buf_prd); | |
4182 | phys_addr = ccb->ccb_dma_handle + | |
4183 | offsetof(struct pm8001_ccb_info, buf_prd[0]); | |
4184 | sata_cmd.addr_low = lower_32_bits(phys_addr); | |
4185 | sata_cmd.addr_high = upper_32_bits(phys_addr); | |
4186 | sata_cmd.esgl = cpu_to_le32(1 << 31); | |
4187 | } else if (task->num_scatter == 1) { | |
4188 | u64 dma_addr = sg_dma_address(task->scatter); | |
4189 | sata_cmd.addr_low = lower_32_bits(dma_addr); | |
4190 | sata_cmd.addr_high = upper_32_bits(dma_addr); | |
4191 | sata_cmd.len = cpu_to_le32(task->total_xfer_len); | |
4192 | sata_cmd.esgl = 0; | |
0ecdf00b AKS |
4193 | /* Check 4G Boundary */ |
4194 | start_addr = cpu_to_le64(dma_addr); | |
4195 | end_addr = (start_addr + sata_cmd.len) - 1; | |
4196 | end_addr_low = cpu_to_le32(lower_32_bits(end_addr)); | |
4197 | end_addr_high = cpu_to_le32(upper_32_bits(end_addr)); | |
4198 | if (end_addr_high != sata_cmd.addr_high) { | |
4199 | PM8001_FAIL_DBG(pm8001_ha, | |
4200 | pm8001_printk("The sg list address " | |
4201 | "start_addr=0x%016llx data_len=0x%x" | |
4202 | "end_addr_high=0x%08x end_addr_low=" | |
4203 | "0x%08x has crossed 4G boundary\n", | |
4204 | start_addr, sata_cmd.len, | |
4205 | end_addr_high, end_addr_low)); | |
4206 | pm8001_chip_make_sg(task->scatter, 1, | |
4207 | ccb->buf_prd); | |
4208 | phys_addr = ccb->ccb_dma_handle + | |
4209 | offsetof(struct pm8001_ccb_info, | |
4210 | buf_prd[0]); | |
4211 | sata_cmd.addr_low = | |
4212 | lower_32_bits(phys_addr); | |
4213 | sata_cmd.addr_high = | |
4214 | upper_32_bits(phys_addr); | |
4215 | sata_cmd.esgl = cpu_to_le32(1 << 31); | |
4216 | } | |
f5860992 S |
4217 | } else if (task->num_scatter == 0) { |
4218 | sata_cmd.addr_low = 0; | |
4219 | sata_cmd.addr_high = 0; | |
4220 | sata_cmd.len = cpu_to_le32(task->total_xfer_len); | |
4221 | sata_cmd.esgl = 0; | |
4222 | } | |
4223 | /* scsi cdb */ | |
4224 | sata_cmd.atapi_scsi_cdb[0] = | |
4225 | cpu_to_le32(((task->ata_task.atapi_packet[0]) | | |
4226 | (task->ata_task.atapi_packet[1] << 8) | | |
4227 | (task->ata_task.atapi_packet[2] << 16) | | |
4228 | (task->ata_task.atapi_packet[3] << 24))); | |
4229 | sata_cmd.atapi_scsi_cdb[1] = | |
4230 | cpu_to_le32(((task->ata_task.atapi_packet[4]) | | |
4231 | (task->ata_task.atapi_packet[5] << 8) | | |
4232 | (task->ata_task.atapi_packet[6] << 16) | | |
4233 | (task->ata_task.atapi_packet[7] << 24))); | |
4234 | sata_cmd.atapi_scsi_cdb[2] = | |
4235 | cpu_to_le32(((task->ata_task.atapi_packet[8]) | | |
4236 | (task->ata_task.atapi_packet[9] << 8) | | |
4237 | (task->ata_task.atapi_packet[10] << 16) | | |
4238 | (task->ata_task.atapi_packet[11] << 24))); | |
4239 | sata_cmd.atapi_scsi_cdb[3] = | |
4240 | cpu_to_le32(((task->ata_task.atapi_packet[12]) | | |
4241 | (task->ata_task.atapi_packet[13] << 8) | | |
4242 | (task->ata_task.atapi_packet[14] << 16) | | |
4243 | (task->ata_task.atapi_packet[15] << 24))); | |
4244 | } | |
c6b9ef57 S |
4245 | |
4246 | /* Check for read log for failed drive and return */ | |
4247 | if (sata_cmd.sata_fis.command == 0x2f) { | |
4248 | if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) || | |
4249 | (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) || | |
4250 | (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) { | |
4251 | struct task_status_struct *ts; | |
4252 | ||
4253 | pm8001_ha_dev->id &= 0xDFFFFFFF; | |
4254 | ts = &task->task_status; | |
4255 | ||
4256 | spin_lock_irqsave(&task->task_state_lock, flags); | |
4257 | ts->resp = SAS_TASK_COMPLETE; | |
4258 | ts->stat = SAM_STAT_GOOD; | |
4259 | task->task_state_flags &= ~SAS_TASK_STATE_PENDING; | |
4260 | task->task_state_flags &= ~SAS_TASK_AT_INITIATOR; | |
4261 | task->task_state_flags |= SAS_TASK_STATE_DONE; | |
4262 | if (unlikely((task->task_state_flags & | |
4263 | SAS_TASK_STATE_ABORTED))) { | |
4264 | spin_unlock_irqrestore(&task->task_state_lock, | |
4265 | flags); | |
4266 | PM8001_FAIL_DBG(pm8001_ha, | |
4267 | pm8001_printk("task 0x%p resp 0x%x " | |
4268 | " stat 0x%x but aborted by upper layer " | |
4269 | "\n", task, ts->resp, ts->stat)); | |
4270 | pm8001_ccb_task_free(pm8001_ha, task, ccb, tag); | |
4271 | return 0; | |
2b01d816 | 4272 | } else { |
c6b9ef57 S |
4273 | spin_unlock_irqrestore(&task->task_state_lock, |
4274 | flags); | |
2b01d816 ST |
4275 | pm8001_ccb_task_free_done(pm8001_ha, task, |
4276 | ccb, tag); | |
c6b9ef57 S |
4277 | return 0; |
4278 | } | |
4279 | } | |
4280 | } | |
f9cd6cbd | 4281 | q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM; |
f5860992 | 4282 | ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, |
f9cd6cbd | 4283 | &sata_cmd, q_index); |
f5860992 S |
4284 | return ret; |
4285 | } | |
4286 | ||
4287 | /** | |
4288 | * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND | |
4289 | * @pm8001_ha: our hba card information. | |
4290 | * @num: the inbound queue number | |
4291 | * @phy_id: the phy id which we wanted to start up. | |
4292 | */ | |
4293 | static int | |
4294 | pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) | |
4295 | { | |
4296 | struct phy_start_req payload; | |
4297 | struct inbound_queue_table *circularQ; | |
4298 | int ret; | |
4299 | u32 tag = 0x01; | |
4300 | u32 opcode = OPC_INB_PHYSTART; | |
4301 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; | |
4302 | memset(&payload, 0, sizeof(payload)); | |
4303 | payload.tag = cpu_to_le32(tag); | |
4304 | ||
4305 | PM8001_INIT_DBG(pm8001_ha, | |
4306 | pm8001_printk("PHY START REQ for phy_id %d\n", phy_id)); | |
4307 | /* | |
4308 | ** [0:7] PHY Identifier | |
4309 | ** [8:11] link rate 1.5G, 3G, 6G | |
4310 | ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode | |
4311 | ** [14] 0b disable spin up hold; 1b enable spin up hold | |
4312 | ** [15] ob no change in current PHY analig setup 1b enable using SPAST | |
4313 | */ | |
a9a923e5 AKS |
4314 | if (!IS_SPCV_12G(pm8001_ha->pdev)) |
4315 | payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | | |
4316 | LINKMODE_AUTO | LINKRATE_15 | | |
4317 | LINKRATE_30 | LINKRATE_60 | phy_id); | |
4318 | else | |
4319 | payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE | | |
4320 | LINKMODE_AUTO | LINKRATE_15 | | |
4321 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120 | | |
4322 | phy_id); | |
4323 | ||
f5860992 S |
4324 | /* SSC Disable and SAS Analog ST configuration */ |
4325 | /** | |
4326 | payload.ase_sh_lm_slr_phyid = | |
4327 | cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE | | |
4328 | LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | | |
4329 | phy_id); | |
4330 | Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need | |
4331 | **/ | |
4332 | ||
aa9f8328 | 4333 | payload.sas_identify.dev_type = SAS_END_DEVICE; |
f5860992 S |
4334 | payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL; |
4335 | memcpy(payload.sas_identify.sas_addr, | |
4336 | pm8001_ha->sas_addr, SAS_ADDR_SIZE); | |
4337 | payload.sas_identify.phy_id = phy_id; | |
4338 | ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0); | |
4339 | return ret; | |
4340 | } | |
4341 | ||
4342 | /** | |
4343 | * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND | |
4344 | * @pm8001_ha: our hba card information. | |
4345 | * @num: the inbound queue number | |
4346 | * @phy_id: the phy id which we wanted to start up. | |
4347 | */ | |
4348 | static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, | |
4349 | u8 phy_id) | |
4350 | { | |
4351 | struct phy_stop_req payload; | |
4352 | struct inbound_queue_table *circularQ; | |
4353 | int ret; | |
4354 | u32 tag = 0x01; | |
4355 | u32 opcode = OPC_INB_PHYSTOP; | |
4356 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; | |
4357 | memset(&payload, 0, sizeof(payload)); | |
4358 | payload.tag = cpu_to_le32(tag); | |
4359 | payload.phy_id = cpu_to_le32(phy_id); | |
4360 | ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0); | |
4361 | return ret; | |
4362 | } | |
4363 | ||
4364 | /** | |
4365 | * see comments on pm8001_mpi_reg_resp. | |
4366 | */ | |
4367 | static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, | |
4368 | struct pm8001_device *pm8001_dev, u32 flag) | |
4369 | { | |
4370 | struct reg_dev_req payload; | |
4371 | u32 opc; | |
4372 | u32 stp_sspsmp_sata = 0x4; | |
4373 | struct inbound_queue_table *circularQ; | |
4374 | u32 linkrate, phy_id; | |
4375 | int rc, tag = 0xdeadbeef; | |
4376 | struct pm8001_ccb_info *ccb; | |
4377 | u8 retryFlag = 0x1; | |
4378 | u16 firstBurstSize = 0; | |
4379 | u16 ITNT = 2000; | |
4380 | struct domain_device *dev = pm8001_dev->sas_device; | |
4381 | struct domain_device *parent_dev = dev->parent; | |
4382 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; | |
4383 | ||
4384 | memset(&payload, 0, sizeof(payload)); | |
4385 | rc = pm8001_tag_alloc(pm8001_ha, &tag); | |
4386 | if (rc) | |
4387 | return rc; | |
4388 | ccb = &pm8001_ha->ccb_info[tag]; | |
4389 | ccb->device = pm8001_dev; | |
4390 | ccb->ccb_tag = tag; | |
4391 | payload.tag = cpu_to_le32(tag); | |
4392 | ||
4393 | if (flag == 1) { | |
4394 | stp_sspsmp_sata = 0x02; /*direct attached sata */ | |
4395 | } else { | |
aa9f8328 | 4396 | if (pm8001_dev->dev_type == SAS_SATA_DEV) |
f5860992 | 4397 | stp_sspsmp_sata = 0x00; /* stp*/ |
aa9f8328 JB |
4398 | else if (pm8001_dev->dev_type == SAS_END_DEVICE || |
4399 | pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE || | |
4400 | pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE) | |
f5860992 S |
4401 | stp_sspsmp_sata = 0x01; /*ssp or smp*/ |
4402 | } | |
4403 | if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) | |
4404 | phy_id = parent_dev->ex_dev.ex_phy->phy_id; | |
4405 | else | |
4406 | phy_id = pm8001_dev->attached_phy; | |
4407 | ||
4408 | opc = OPC_INB_REG_DEV; | |
4409 | ||
4410 | linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? | |
4411 | pm8001_dev->sas_device->linkrate : dev->port->linkrate; | |
4412 | ||
4413 | payload.phyid_portid = | |
4414 | cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) | | |
4415 | ((phy_id & 0xFF) << 8)); | |
4416 | ||
4417 | payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) | | |
4418 | ((linkrate & 0x0F) << 24) | | |
4419 | ((stp_sspsmp_sata & 0x03) << 28)); | |
4420 | payload.firstburstsize_ITNexustimeout = | |
4421 | cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); | |
4422 | ||
4423 | memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, | |
4424 | SAS_ADDR_SIZE); | |
4425 | ||
4426 | rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); | |
5533abca TH |
4427 | if (rc) |
4428 | pm8001_tag_free(pm8001_ha, tag); | |
f5860992 S |
4429 | |
4430 | return rc; | |
4431 | } | |
4432 | ||
4433 | /** | |
4434 | * pm80xx_chip_phy_ctl_req - support the local phy operation | |
4435 | * @pm8001_ha: our hba card information. | |
4436 | * @num: the inbound queue number | |
4437 | * @phy_id: the phy id which we wanted to operate | |
4438 | * @phy_op: | |
4439 | */ | |
4440 | static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, | |
4441 | u32 phyId, u32 phy_op) | |
4442 | { | |
4443 | struct local_phy_ctl_req payload; | |
4444 | struct inbound_queue_table *circularQ; | |
4445 | int ret; | |
4446 | u32 opc = OPC_INB_LOCAL_PHY_CONTROL; | |
4447 | memset(&payload, 0, sizeof(payload)); | |
4448 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; | |
4449 | payload.tag = cpu_to_le32(1); | |
4450 | payload.phyop_phyid = | |
4451 | cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF)); | |
4452 | ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); | |
4453 | return ret; | |
4454 | } | |
4455 | ||
4456 | static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha) | |
4457 | { | |
4458 | u32 value; | |
4459 | #ifdef PM8001_USE_MSIX | |
4460 | return 1; | |
4461 | #endif | |
4462 | value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); | |
4463 | if (value) | |
4464 | return 1; | |
4465 | return 0; | |
4466 | ||
4467 | } | |
4468 | ||
4469 | /** | |
4470 | * pm8001_chip_isr - PM8001 isr handler. | |
4471 | * @pm8001_ha: our hba card information. | |
4472 | * @irq: irq number. | |
4473 | * @stat: stat. | |
4474 | */ | |
4475 | static irqreturn_t | |
4476 | pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) | |
4477 | { | |
4478 | pm80xx_chip_interrupt_disable(pm8001_ha, vec); | |
4479 | process_oq(pm8001_ha, vec); | |
4480 | pm80xx_chip_interrupt_enable(pm8001_ha, vec); | |
4481 | return IRQ_HANDLED; | |
4482 | } | |
4483 | ||
27909407 AKS |
4484 | void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha, |
4485 | u32 operation, u32 phyid, u32 length, u32 *buf) | |
4486 | { | |
4487 | u32 tag , i, j = 0; | |
4488 | int rc; | |
4489 | struct set_phy_profile_req payload; | |
4490 | struct inbound_queue_table *circularQ; | |
4491 | u32 opc = OPC_INB_SET_PHY_PROFILE; | |
4492 | ||
4493 | memset(&payload, 0, sizeof(payload)); | |
4494 | rc = pm8001_tag_alloc(pm8001_ha, &tag); | |
4495 | if (rc) | |
4496 | PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n")); | |
4497 | circularQ = &pm8001_ha->inbnd_q_tbl[0]; | |
4498 | payload.tag = cpu_to_le32(tag); | |
4499 | payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF)); | |
4500 | PM8001_INIT_DBG(pm8001_ha, | |
4501 | pm8001_printk(" phy profile command for phy %x ,length is %d\n", | |
4502 | payload.ppc_phyid, length)); | |
4503 | for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) { | |
4504 | payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i)); | |
4505 | j++; | |
4506 | } | |
5533abca TH |
4507 | rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0); |
4508 | if (rc) | |
4509 | pm8001_tag_free(pm8001_ha, tag); | |
27909407 AKS |
4510 | } |
4511 | ||
4512 | void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha, | |
4513 | u32 length, u8 *buf) | |
4514 | { | |
4515 | u32 page_code, i; | |
4516 | ||
4517 | page_code = SAS_PHY_ANALOG_SETTINGS_PAGE; | |
4518 | for (i = 0; i < pm8001_ha->chip->n_phy; i++) { | |
4519 | mpi_set_phy_profile_req(pm8001_ha, | |
4520 | SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf); | |
4521 | length = length + PHY_DWORD_LENGTH; | |
4522 | } | |
4523 | PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n")); | |
4524 | } | |
f5860992 S |
4525 | const struct pm8001_dispatch pm8001_80xx_dispatch = { |
4526 | .name = "pmc80xx", | |
4527 | .chip_init = pm80xx_chip_init, | |
4528 | .chip_soft_rst = pm80xx_chip_soft_rst, | |
4529 | .chip_rst = pm80xx_hw_chip_rst, | |
4530 | .chip_iounmap = pm8001_chip_iounmap, | |
4531 | .isr = pm80xx_chip_isr, | |
4532 | .is_our_interupt = pm80xx_chip_is_our_interupt, | |
4533 | .isr_process_oq = process_oq, | |
4534 | .interrupt_enable = pm80xx_chip_interrupt_enable, | |
4535 | .interrupt_disable = pm80xx_chip_interrupt_disable, | |
4536 | .make_prd = pm8001_chip_make_sg, | |
4537 | .smp_req = pm80xx_chip_smp_req, | |
4538 | .ssp_io_req = pm80xx_chip_ssp_io_req, | |
4539 | .sata_req = pm80xx_chip_sata_req, | |
4540 | .phy_start_req = pm80xx_chip_phy_start_req, | |
4541 | .phy_stop_req = pm80xx_chip_phy_stop_req, | |
4542 | .reg_dev_req = pm80xx_chip_reg_dev_req, | |
4543 | .dereg_dev_req = pm8001_chip_dereg_dev_req, | |
4544 | .phy_ctl_req = pm80xx_chip_phy_ctl_req, | |
4545 | .task_abort = pm8001_chip_abort_task, | |
4546 | .ssp_tm_req = pm8001_chip_ssp_tm_req, | |
4547 | .get_nvmd_req = pm8001_chip_get_nvmd_req, | |
4548 | .set_nvmd_req = pm8001_chip_set_nvmd_req, | |
4549 | .fw_flash_update_req = pm8001_chip_fw_flash_update_req, | |
4550 | .set_dev_state_req = pm8001_chip_set_dev_state_req, | |
4551 | }; |