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[SCSI] pm80xx: Firmware flash memory free fix, with addition of new memory region...
[linux-block.git] / drivers / scsi / pm8001 / pm8001_hwi.c
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dbf9bfe6 1/*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
5a0e3ad6 40 #include <linux/slab.h>
dbf9bfe6 41 #include "pm8001_sas.h"
42 #include "pm8001_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46/**
47 * read_main_config_table - read the configure table and save it.
48 * @pm8001_ha: our hba card information
49 */
6f039790 50static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
dbf9bfe6 51{
52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
e5742101
S		 53 pm8001_ha->main_cfg_tbl.pm8001_tbl.signature =
54 pm8001_mr32(address, 0x00);
55 pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
56 pm8001_mr32(address, 0x04);
57 pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
58 pm8001_mr32(address, 0x08);
59 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io =
60 pm8001_mr32(address, 0x0C);
61 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl =
62 pm8001_mr32(address, 0x10);
63 pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
64 pm8001_mr32(address, 0x14);
65 pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset =
66 pm8001_mr32(address, 0x18);
67 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
d0b68041 68 pm8001_mr32(address, MAIN_IBQ_OFFSET);
e5742101 69 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
d0b68041 70 pm8001_mr32(address, MAIN_OBQ_OFFSET);
e5742101 71 pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag =
dbf9bfe6 72 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
73
74 /* read analog Setting offset from the configuration table */
e5742101 75 pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
dbf9bfe6 76 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
77
78 /* read Error Dump Offset and Length */
e5742101 79 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
dbf9bfe6 80 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
e5742101 81 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
dbf9bfe6 82 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
e5742101 83 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
dbf9bfe6 84 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
e5742101 85 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
dbf9bfe6 86 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
87}
88
89/**
90 * read_general_status_table - read the general status table and save it.
91 * @pm8001_ha: our hba card information
92 */
6f039790 93static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
dbf9bfe6 94{
95 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
e5742101
S		 96 pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate =
97 pm8001_mr32(address, 0x00);
98 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 =
99 pm8001_mr32(address, 0x04);
100 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 =
101 pm8001_mr32(address, 0x08);
102 pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt =
103 pm8001_mr32(address, 0x0C);
104 pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt =
105 pm8001_mr32(address, 0x10);
106 pm8001_ha->gs_tbl.pm8001_tbl.rsvd =
107 pm8001_mr32(address, 0x14);
108 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] =
109 pm8001_mr32(address, 0x18);
110 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] =
111 pm8001_mr32(address, 0x1C);
112 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] =
113 pm8001_mr32(address, 0x20);
114 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] =
115 pm8001_mr32(address, 0x24);
116 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] =
117 pm8001_mr32(address, 0x28);
118 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] =
119 pm8001_mr32(address, 0x2C);
120 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] =
121 pm8001_mr32(address, 0x30);
122 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] =
123 pm8001_mr32(address, 0x34);
124 pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val =
125 pm8001_mr32(address, 0x38);
126 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] =
127 pm8001_mr32(address, 0x3C);
128 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] =
129 pm8001_mr32(address, 0x40);
130 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] =
131 pm8001_mr32(address, 0x44);
132 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] =
133 pm8001_mr32(address, 0x48);
134 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] =
135 pm8001_mr32(address, 0x4C);
136 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] =
137 pm8001_mr32(address, 0x50);
138 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] =
139 pm8001_mr32(address, 0x54);
140 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] =
141 pm8001_mr32(address, 0x58);
142 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] =
143 pm8001_mr32(address, 0x5C);
144 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] =
145 pm8001_mr32(address, 0x60);
dbf9bfe6 146}
147
148/**
149 * read_inbnd_queue_table - read the inbound queue table and save it.
150 * @pm8001_ha: our hba card information
151 */
6f039790 152static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
dbf9bfe6 153{
dbf9bfe6 154 int i;
155 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
e590adfd 156 for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
d0b68041 157 u32 offset = i * 0x20;
dbf9bfe6 158 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
159 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
160 pm8001_ha->inbnd_q_tbl[i].pi_offset =
161 pm8001_mr32(address, (offset + 0x18));
162 }
163}
164
165/**
166 * read_outbnd_queue_table - read the outbound queue table and save it.
167 * @pm8001_ha: our hba card information
168 */
6f039790 169static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
dbf9bfe6 170{
dbf9bfe6 171 int i;
172 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
e590adfd 173 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
dbf9bfe6 174 u32 offset = i * 0x24;
175 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
176 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
177 pm8001_ha->outbnd_q_tbl[i].ci_offset =
178 pm8001_mr32(address, (offset + 0x18));
179 }
180}
181
182/**
183 * init_default_table_values - init the default table.
184 * @pm8001_ha: our hba card information
185 */
6f039790 186static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
dbf9bfe6 187{
dbf9bfe6 188 int i;
189 u32 offsetib, offsetob;
190 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
191 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
192
e5742101
S		 193 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0;
194 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0;
195 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0;
196 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0;
197 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0;
198 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
199 0;
200 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
201 0;
202 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
203 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
204 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
205 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
206
207 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr =
dbf9bfe6 208 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
e5742101 209 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr =
dbf9bfe6 210 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
e5742101
S		 211 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size =
212 PM8001_EVENT_LOG_SIZE;
213 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01;
214 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr =
dbf9bfe6 215 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
e5742101 216 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr =
dbf9bfe6 217 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
e5742101
S		 218 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size =
219 PM8001_EVENT_LOG_SIZE;
220 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01;
221 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01;
222 for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
dbf9bfe6 223 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
99c72ebc 224 PM8001_MPI_QUEUE | (64 << 16) | (0x00<<30);
dbf9bfe6 225 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
e590adfd 226 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
dbf9bfe6 227 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
e590adfd 228 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
dbf9bfe6 229 pm8001_ha->inbnd_q_tbl[i].base_virt =
e590adfd 230 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
dbf9bfe6 231 pm8001_ha->inbnd_q_tbl[i].total_length =
e590adfd 232 pm8001_ha->memoryMap.region[IB + i].total_len;
dbf9bfe6 233 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
e590adfd 234 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
dbf9bfe6 235 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
e590adfd 236 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
dbf9bfe6 237 pm8001_ha->inbnd_q_tbl[i].ci_virt =
e590adfd 238 pm8001_ha->memoryMap.region[CI + i].virt_ptr;
dbf9bfe6 239 offsetib = i * 0x20;
240 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
241 get_pci_bar_index(pm8001_mr32(addressib,
242 (offsetib + 0x14)));
243 pm8001_ha->inbnd_q_tbl[i].pi_offset =
244 pm8001_mr32(addressib, (offsetib + 0x18));
245 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
246 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
247 }
e5742101 248 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
dbf9bfe6 249 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
99c72ebc 250 PM8001_MPI_QUEUE | (64 << 16) | (0x01<<30);
dbf9bfe6 251 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
e590adfd 252 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
dbf9bfe6 253 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
e590adfd 254 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
dbf9bfe6 255 pm8001_ha->outbnd_q_tbl[i].base_virt =
e590adfd 256 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
dbf9bfe6 257 pm8001_ha->outbnd_q_tbl[i].total_length =
e590adfd 258 pm8001_ha->memoryMap.region[OB + i].total_len;
dbf9bfe6 259 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
e590adfd 260 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
dbf9bfe6 261 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
e590adfd 262 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
dbf9bfe6 263 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay =
e590adfd 264 0 | (10 << 16) | (i << 24);
dbf9bfe6 265 pm8001_ha->outbnd_q_tbl[i].pi_virt =
e590adfd 266 pm8001_ha->memoryMap.region[PI + i].virt_ptr;
dbf9bfe6 267 offsetob = i * 0x24;
268 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
269 get_pci_bar_index(pm8001_mr32(addressob,
270 offsetob + 0x14));
271 pm8001_ha->outbnd_q_tbl[i].ci_offset =
272 pm8001_mr32(addressob, (offsetob + 0x18));
273 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
274 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
275 }
276}
277
278/**
279 * update_main_config_table - update the main default table to the HBA.
280 * @pm8001_ha: our hba card information
281 */
6f039790 282static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
dbf9bfe6 283{
284 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
285 pm8001_mw32(address, 0x24,
e5742101 286 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
dbf9bfe6 287 pm8001_mw32(address, 0x28,
e5742101 288 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
dbf9bfe6 289 pm8001_mw32(address, 0x2C,
e5742101 290 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
dbf9bfe6 291 pm8001_mw32(address, 0x30,
e5742101 292 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
dbf9bfe6 293 pm8001_mw32(address, 0x34,
e5742101 294 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
dbf9bfe6 295 pm8001_mw32(address, 0x38,
e5742101
S		 296 pm8001_ha->main_cfg_tbl.pm8001_tbl.
297 outbound_tgt_ITNexus_event_pid0_3);
dbf9bfe6 298 pm8001_mw32(address, 0x3C,
e5742101
S		 299 pm8001_ha->main_cfg_tbl.pm8001_tbl.
300 outbound_tgt_ITNexus_event_pid4_7);
dbf9bfe6 301 pm8001_mw32(address, 0x40,
e5742101
S		 302 pm8001_ha->main_cfg_tbl.pm8001_tbl.
303 outbound_tgt_ssp_event_pid0_3);
dbf9bfe6 304 pm8001_mw32(address, 0x44,
e5742101
S		 305 pm8001_ha->main_cfg_tbl.pm8001_tbl.
306 outbound_tgt_ssp_event_pid4_7);
dbf9bfe6 307 pm8001_mw32(address, 0x48,
e5742101
S		 308 pm8001_ha->main_cfg_tbl.pm8001_tbl.
309 outbound_tgt_smp_event_pid0_3);
dbf9bfe6 310 pm8001_mw32(address, 0x4C,
e5742101
S		 311 pm8001_ha->main_cfg_tbl.pm8001_tbl.
312 outbound_tgt_smp_event_pid4_7);
dbf9bfe6 313 pm8001_mw32(address, 0x50,
e5742101 314 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
dbf9bfe6 315 pm8001_mw32(address, 0x54,
e5742101
S		 316 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
317 pm8001_mw32(address, 0x58,
318 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
319 pm8001_mw32(address, 0x5C,
320 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
dbf9bfe6 321 pm8001_mw32(address, 0x60,
e5742101 322 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
dbf9bfe6 323 pm8001_mw32(address, 0x64,
e5742101
S		 324 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
325 pm8001_mw32(address, 0x68,
326 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
dbf9bfe6 327 pm8001_mw32(address, 0x6C,
e5742101 328 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
dbf9bfe6 329 pm8001_mw32(address, 0x70,
e5742101 330 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
dbf9bfe6 331}
332
333/**
334 * update_inbnd_queue_table - update the inbound queue table to the HBA.
335 * @pm8001_ha: our hba card information
336 */
6f039790
GKH		 337static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
338 int number)
dbf9bfe6 339{
340 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
341 u16 offset = number * 0x20;
342 pm8001_mw32(address, offset + 0x00,
343 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
344 pm8001_mw32(address, offset + 0x04,
345 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
346 pm8001_mw32(address, offset + 0x08,
347 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
348 pm8001_mw32(address, offset + 0x0C,
349 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
350 pm8001_mw32(address, offset + 0x10,
351 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
352}
353
354/**
355 * update_outbnd_queue_table - update the outbound queue table to the HBA.
356 * @pm8001_ha: our hba card information
357 */
6f039790
GKH		 358static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
359 int number)
dbf9bfe6 360{
361 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
362 u16 offset = number * 0x24;
363 pm8001_mw32(address, offset + 0x00,
364 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
365 pm8001_mw32(address, offset + 0x04,
366 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
367 pm8001_mw32(address, offset + 0x08,
368 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
369 pm8001_mw32(address, offset + 0x0C,
370 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
371 pm8001_mw32(address, offset + 0x10,
372 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
373 pm8001_mw32(address, offset + 0x1C,
374 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
375}
376
377/**
d95d0001
MS		 378 * pm8001_bar4_shift - function is called to shift BAR base address
379 * @pm8001_ha : our hba card infomation
dbf9bfe6 380 * @shiftValue : shifting value in memory bar.
381 */
d95d0001 382int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
dbf9bfe6 383{
384 u32 regVal;
d95d0001 385 unsigned long start;
dbf9bfe6 386
387 /* program the inbound AXI translation Lower Address */
388 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
389
390 /* confirm the setting is written */
d95d0001 391 start = jiffies + HZ; /* 1 sec */
dbf9bfe6 392 do {
dbf9bfe6 393 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
d95d0001 394 } while ((regVal != shiftValue) && time_before(jiffies, start));
dbf9bfe6 395
d95d0001 396 if (regVal != shiftValue) {
dbf9bfe6 397 PM8001_INIT_DBG(pm8001_ha,
398 pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
399 " = 0x%x\n", regVal));
400 return -1;
401 }
402 return 0;
403}
404
405/**
406 * mpi_set_phys_g3_with_ssc
407 * @pm8001_ha: our hba card information
408 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
409 */
6f039790
GKH		 410static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
411 u32 SSCbit)
dbf9bfe6 412{
0330dba3 413 u32 value, offset, i;
d95d0001 414 unsigned long flags;
dbf9bfe6 415
416#define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
417#define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
418#define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
419#define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
d0b68041 420#define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
421#define PHY_G3_WITH_SSC_BIT_SHIFT 13
422#define SNW3_PHY_CAPABILITIES_PARITY 31
dbf9bfe6 423
424 /*
425 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
426 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
427 */
d95d0001
MS		 428 spin_lock_irqsave(&pm8001_ha->lock, flags);
429 if (-1 == pm8001_bar4_shift(pm8001_ha,
430 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
431 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 432 return;
d95d0001 433 }
0330dba3 434
dbf9bfe6 435 for (i = 0; i < 4; i++) {
436 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
0330dba3 437 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
dbf9bfe6 438 }
dbf9bfe6 439 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
d95d0001
MS		 440 if (-1 == pm8001_bar4_shift(pm8001_ha,
441 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
442 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 443 return;
d95d0001 444 }
dbf9bfe6 445 for (i = 4; i < 8; i++) {
446 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
0330dba3 447 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
dbf9bfe6 448 }
0330dba3 449 /*************************************************************
450 Change the SSC upspreading value to 0x0 so that upspreading is disabled.
451 Device MABC SMOD0 Controls
452 Address: (via MEMBASE-III):
453 Using shifted destination address 0x0_0000: with Offset 0xD8
454
455 31:28 R/W Reserved Do not change
456 27:24 R/W SAS_SMOD_SPRDUP 0000
457 23:20 R/W SAS_SMOD_SPRDDN 0000
458 19:0 R/W Reserved Do not change
459 Upon power-up this register will read as 0x8990c016,
460 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
461 so that the written value will be 0x8090c016.
462 This will ensure only down-spreading SSC is enabled on the SPC.
463 *************************************************************/
464 value = pm8001_cr32(pm8001_ha, 2, 0xd8);
465 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
dbf9bfe6 466
467 /*set the shifted destination address to 0x0 to avoid error operation */
d95d0001
MS		 468 pm8001_bar4_shift(pm8001_ha, 0x0);
469 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 470 return;
471}
472
473/**
474 * mpi_set_open_retry_interval_reg
475 * @pm8001_ha: our hba card information
476 * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
477 */
6f039790
GKH		 478static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
479 u32 interval)
dbf9bfe6 480{
481 u32 offset;
482 u32 value;
483 u32 i;
d95d0001 484 unsigned long flags;
dbf9bfe6 485
486#define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
487#define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
488#define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
489#define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
490#define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
491
492 value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
d95d0001 493 spin_lock_irqsave(&pm8001_ha->lock, flags);
dbf9bfe6 494 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
d95d0001
MS		 495 if (-1 == pm8001_bar4_shift(pm8001_ha,
496 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
497 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 498 return;
d95d0001 499 }
dbf9bfe6 500 for (i = 0; i < 4; i++) {
501 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
502 pm8001_cw32(pm8001_ha, 2, offset, value);
503 }
504
d95d0001
MS		 505 if (-1 == pm8001_bar4_shift(pm8001_ha,
506 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
507 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 508 return;
d95d0001 509 }
dbf9bfe6 510 for (i = 4; i < 8; i++) {
511 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
512 pm8001_cw32(pm8001_ha, 2, offset, value);
513 }
514 /*set the shifted destination address to 0x0 to avoid error operation */
d95d0001
MS		 515 pm8001_bar4_shift(pm8001_ha, 0x0);
516 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 517 return;
518}
519
520/**
521 * mpi_init_check - check firmware initialization status.
522 * @pm8001_ha: our hba card information
523 */
524static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
525{
526 u32 max_wait_count;
527 u32 value;
528 u32 gst_len_mpistate;
529 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
530 table is updated */
531 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
532 /* wait until Inbound DoorBell Clear Register toggled */
533 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
534 do {
535 udelay(1);
536 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
537 value &= SPC_MSGU_CFG_TABLE_UPDATE;
538 } while ((value != 0) && (--max_wait_count));
539
540 if (!max_wait_count)
541 return -1;
542 /* check the MPI-State for initialization */
543 gst_len_mpistate =
544 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
545 GST_GSTLEN_MPIS_OFFSET);
546 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
547 return -1;
548 /* check MPI Initialization error */
549 gst_len_mpistate = gst_len_mpistate >> 16;
550 if (0x0000 != gst_len_mpistate)
551 return -1;
552 return 0;
553}
554
555/**
556 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
557 * @pm8001_ha: our hba card information
558 */
559static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
560{
561 u32 value, value1;
562 u32 max_wait_count;
563 /* check error state */
564 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
565 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
566 /* check AAP error */
567 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
568 /* error state */
569 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
570 return -1;
571 }
572
573 /* check IOP error */
574 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
575 /* error state */
576 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
577 return -1;
578 }
579
580 /* bit 4-31 of scratch pad1 should be zeros if it is not
581 in error state*/
582 if (value & SCRATCH_PAD1_STATE_MASK) {
583 /* error case */
584 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
585 return -1;
586 }
587
588 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
589 in error state */
590 if (value1 & SCRATCH_PAD2_STATE_MASK) {
591 /* error case */
592 return -1;
593 }
594
595 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
596
597 /* wait until scratch pad 1 and 2 registers in ready state */
598 do {
599 udelay(1);
600 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
601 & SCRATCH_PAD1_RDY;
602 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
603 & SCRATCH_PAD2_RDY;
604 if ((--max_wait_count) == 0)
605 return -1;
606 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
607 return 0;
608}
609
610static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
611{
612 void __iomem *base_addr;
613 u32 value;
614 u32 offset;
615 u32 pcibar;
616 u32 pcilogic;
617
618 value = pm8001_cr32(pm8001_ha, 0, 0x44);
619 offset = value & 0x03FFFFFF;
620 PM8001_INIT_DBG(pm8001_ha,
6fbc7692 621 pm8001_printk("Scratchpad 0 Offset: %x\n", offset));
dbf9bfe6 622 pcilogic = (value & 0xFC000000) >> 26;
623 pcibar = get_pci_bar_index(pcilogic);
624 PM8001_INIT_DBG(pm8001_ha,
6fbc7692 625 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
dbf9bfe6 626 pm8001_ha->main_cfg_tbl_addr = base_addr =
627 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
628 pm8001_ha->general_stat_tbl_addr =
629 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
630 pm8001_ha->inbnd_q_tbl_addr =
631 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
632 pm8001_ha->outbnd_q_tbl_addr =
633 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
634}
635
636/**
637 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
638 * @pm8001_ha: our hba card information
639 */
6f039790 640static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
dbf9bfe6 641{
e590adfd 642 u8 i = 0;
54792dc2
S		 643 u16 deviceid;
644 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
645 /* 8081 controllers need BAR shift to access MPI space
646 * as this is shared with BIOS data */
647 if (deviceid == 0x8081) {
648 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
649 PM8001_FAIL_DBG(pm8001_ha,
650 pm8001_printk("Shift Bar4 to 0x%x failed\n",
651 GSM_SM_BASE));
652 return -1;
653 }
654 }
dbf9bfe6 655 /* check the firmware status */
656 if (-1 == check_fw_ready(pm8001_ha)) {
657 PM8001_FAIL_DBG(pm8001_ha,
658 pm8001_printk("Firmware is not ready!\n"));
659 return -EBUSY;
660 }
661
662 /* Initialize pci space address eg: mpi offset */
663 init_pci_device_addresses(pm8001_ha);
664 init_default_table_values(pm8001_ha);
665 read_main_config_table(pm8001_ha);
666 read_general_status_table(pm8001_ha);
667 read_inbnd_queue_table(pm8001_ha);
668 read_outbnd_queue_table(pm8001_ha);
669 /* update main config table ,inbound table and outbound table */
670 update_main_config_table(pm8001_ha);
e590adfd
S		 671 for (i = 0; i < PM8001_MAX_INB_NUM; i++)
672 update_inbnd_queue_table(pm8001_ha, i);
673 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++)
674 update_outbnd_queue_table(pm8001_ha, i);
54792dc2
S		 675 /* 8081 controller donot require these operations */
676 if (deviceid != 0x8081) {
677 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
678 /* 7->130ms, 34->500ms, 119->1.5s */
679 mpi_set_open_retry_interval_reg(pm8001_ha, 119);
680 }
dbf9bfe6 681 /* notify firmware update finished and check initialization status */
682 if (0 == mpi_init_check(pm8001_ha)) {
683 PM8001_INIT_DBG(pm8001_ha,
684 pm8001_printk("MPI initialize successful!\n"));
685 } else
686 return -EBUSY;
687 /*This register is a 16-bit timer with a resolution of 1us. This is the
688 timer used for interrupt delay/coalescing in the PCIe Application Layer.
689 Zero is not a valid value. A value of 1 in the register will cause the
690 interrupts to be normal. A value greater than 1 will cause coalescing
691 delays.*/
692 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
693 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
694 return 0;
695}
696
697static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
698{
699 u32 max_wait_count;
700 u32 value;
701 u32 gst_len_mpistate;
54792dc2
S		 702 u16 deviceid;
703 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
704 if (deviceid == 0x8081) {
705 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
706 PM8001_FAIL_DBG(pm8001_ha,
707 pm8001_printk("Shift Bar4 to 0x%x failed\n",
708 GSM_SM_BASE));
709 return -1;
710 }
711 }
dbf9bfe6 712 init_pci_device_addresses(pm8001_ha);
713 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
714 table is stop */
715 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
716
717 /* wait until Inbound DoorBell Clear Register toggled */
718 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
719 do {
720 udelay(1);
721 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
722 value &= SPC_MSGU_CFG_TABLE_RESET;
723 } while ((value != 0) && (--max_wait_count));
724
725 if (!max_wait_count) {
726 PM8001_FAIL_DBG(pm8001_ha,
727 pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
728 return -1;
729 }
730
731 /* check the MPI-State for termination in progress */
732 /* wait until Inbound DoorBell Clear Register toggled */
733 max_wait_count = 1 * 1000 * 1000; /* 1 sec */
734 do {
735 udelay(1);
736 gst_len_mpistate =
737 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
738 GST_GSTLEN_MPIS_OFFSET);
739 if (GST_MPI_STATE_UNINIT ==
740 (gst_len_mpistate & GST_MPI_STATE_MASK))
741 break;
742 } while (--max_wait_count);
743 if (!max_wait_count) {
744 PM8001_FAIL_DBG(pm8001_ha,
745 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
746 gst_len_mpistate & GST_MPI_STATE_MASK));
747 return -1;
748 }
749 return 0;
750}
751
752/**
753 * soft_reset_ready_check - Function to check FW is ready for soft reset.
754 * @pm8001_ha: our hba card information
755 */
756static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
757{
758 u32 regVal, regVal1, regVal2;
759 if (mpi_uninit_check(pm8001_ha) != 0) {
760 PM8001_FAIL_DBG(pm8001_ha,
761 pm8001_printk("MPI state is not ready\n"));
762 return -1;
763 }
764 /* read the scratch pad 2 register bit 2 */
765 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
766 & SCRATCH_PAD2_FWRDY_RST;
767 if (regVal == SCRATCH_PAD2_FWRDY_RST) {
768 PM8001_INIT_DBG(pm8001_ha,
769 pm8001_printk("Firmware is ready for reset .\n"));
770 } else {
d95d0001
MS		 771 unsigned long flags;
772 /* Trigger NMI twice via RB6 */
773 spin_lock_irqsave(&pm8001_ha->lock, flags);
774 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
775 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 776 PM8001_FAIL_DBG(pm8001_ha,
777 pm8001_printk("Shift Bar4 to 0x%x failed\n",
778 RB6_ACCESS_REG));
779 return -1;
780 }
781 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
782 RB6_MAGIC_NUMBER_RST);
783 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
784 /* wait for 100 ms */
785 mdelay(100);
786 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
787 SCRATCH_PAD2_FWRDY_RST;
788 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
789 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
790 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
791 PM8001_FAIL_DBG(pm8001_ha,
792 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
793 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
794 regVal1, regVal2));
795 PM8001_FAIL_DBG(pm8001_ha,
796 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
797 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
798 PM8001_FAIL_DBG(pm8001_ha,
799 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
800 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
d95d0001 801 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 802 return -1;
803 }
d95d0001 804 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 805 }
806 return 0;
807}
808
809/**
810 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
811 * the FW register status to the originated status.
812 * @pm8001_ha: our hba card information
dbf9bfe6 813 */
814static int
f5860992 815pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
dbf9bfe6 816{
817 u32 regVal, toggleVal;
818 u32 max_wait_count;
819 u32 regVal1, regVal2, regVal3;
f5860992 820 u32 signature = 0x252acbcd; /* for host scratch pad0 */
d95d0001 821 unsigned long flags;
dbf9bfe6 822
823 /* step1: Check FW is ready for soft reset */
824 if (soft_reset_ready_check(pm8001_ha) != 0) {
825 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
826 return -1;
827 }
828
829 /* step 2: clear NMI status register on AAP1 and IOP, write the same
830 value to clear */
831 /* map 0x60000 to BAR4(0x20), BAR2(win) */
d95d0001
MS		 832 spin_lock_irqsave(&pm8001_ha->lock, flags);
833 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
834 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 835 PM8001_FAIL_DBG(pm8001_ha,
836 pm8001_printk("Shift Bar4 to 0x%x failed\n",
837 MBIC_AAP1_ADDR_BASE));
838 return -1;
839 }
840 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
841 PM8001_INIT_DBG(pm8001_ha,
842 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
843 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
844 /* map 0x70000 to BAR4(0x20), BAR2(win) */
d95d0001
MS		 845 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
846 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 847 PM8001_FAIL_DBG(pm8001_ha,
848 pm8001_printk("Shift Bar4 to 0x%x failed\n",
849 MBIC_IOP_ADDR_BASE));
850 return -1;
851 }
852 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
853 PM8001_INIT_DBG(pm8001_ha,
854 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
855 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
856
857 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
858 PM8001_INIT_DBG(pm8001_ha,
859 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
860 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
861
862 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
863 PM8001_INIT_DBG(pm8001_ha,
864 pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal));
865 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
866
867 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
868 PM8001_INIT_DBG(pm8001_ha,
869 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
870 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
871
872 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
873 PM8001_INIT_DBG(pm8001_ha,
874 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
875 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
876
877 /* read the scratch pad 1 register bit 2 */
878 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
879 & SCRATCH_PAD1_RST;
880 toggleVal = regVal ^ SCRATCH_PAD1_RST;
881
882 /* set signature in host scratch pad0 register to tell SPC that the
883 host performs the soft reset */
884 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
885
886 /* read required registers for confirmming */
887 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
d95d0001
MS		 888 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
889 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 890 PM8001_FAIL_DBG(pm8001_ha,
891 pm8001_printk("Shift Bar4 to 0x%x failed\n",
892 GSM_ADDR_BASE));
893 return -1;
894 }
895 PM8001_INIT_DBG(pm8001_ha,
896 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
897 " Reset = 0x%x\n",
898 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
899
900 /* step 3: host read GSM Configuration and Reset register */
901 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
902 /* Put those bits to low */
903 /* GSM XCBI offset = 0x70 0000
904 0x00 Bit 13 COM_SLV_SW_RSTB 1
905 0x00 Bit 12 QSSP_SW_RSTB 1
906 0x00 Bit 11 RAAE_SW_RSTB 1
907 0x00 Bit 9 RB_1_SW_RSTB 1
908 0x00 Bit 8 SM_SW_RSTB 1
909 */
910 regVal &= ~(0x00003b00);
911 /* host write GSM Configuration and Reset register */
912 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
913 PM8001_INIT_DBG(pm8001_ha,
914 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
915 "Configuration and Reset is set to = 0x%x\n",
916 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
917
918 /* step 4: */
919 /* disable GSM - Read Address Parity Check */
920 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
921 PM8001_INIT_DBG(pm8001_ha,
922 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
923 "Enable = 0x%x\n", regVal1));
924 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
925 PM8001_INIT_DBG(pm8001_ha,
926 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
927 "is set to = 0x%x\n",
928 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
929
930 /* disable GSM - Write Address Parity Check */
931 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
932 PM8001_INIT_DBG(pm8001_ha,
933 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
934 " Enable = 0x%x\n", regVal2));
935 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
936 PM8001_INIT_DBG(pm8001_ha,
937 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
938 "Enable is set to = 0x%x\n",
939 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
940
941 /* disable GSM - Write Data Parity Check */
942 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
943 PM8001_INIT_DBG(pm8001_ha,
944 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
945 " Enable = 0x%x\n", regVal3));
946 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
947 PM8001_INIT_DBG(pm8001_ha,
948 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
949 "is set to = 0x%x\n",
950 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
951
952 /* step 5: delay 10 usec */
953 udelay(10);
954 /* step 5-b: set GPIO-0 output control to tristate anyway */
d95d0001
MS		 955 if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
956 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 957 PM8001_INIT_DBG(pm8001_ha,
958 pm8001_printk("Shift Bar4 to 0x%x failed\n",
959 GPIO_ADDR_BASE));
960 return -1;
961 }
962 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
963 PM8001_INIT_DBG(pm8001_ha,
964 pm8001_printk("GPIO Output Control Register:"
965 " = 0x%x\n", regVal));
966 /* set GPIO-0 output control to tri-state */
967 regVal &= 0xFFFFFFFC;
968 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
969
970 /* Step 6: Reset the IOP and AAP1 */
971 /* map 0x00000 to BAR4(0x20), BAR2(win) */
d95d0001
MS		 972 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
973 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 974 PM8001_FAIL_DBG(pm8001_ha,
975 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
976 SPC_TOP_LEVEL_ADDR_BASE));
977 return -1;
978 }
979 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
980 PM8001_INIT_DBG(pm8001_ha,
981 pm8001_printk("Top Register before resetting IOP/AAP1"
982 ":= 0x%x\n", regVal));
983 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
984 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
985
986 /* step 7: Reset the BDMA/OSSP */
987 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
988 PM8001_INIT_DBG(pm8001_ha,
989 pm8001_printk("Top Register before resetting BDMA/OSSP"
990 ": = 0x%x\n", regVal));
991 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
992 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
993
994 /* step 8: delay 10 usec */
995 udelay(10);
996
997 /* step 9: bring the BDMA and OSSP out of reset */
998 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
999 PM8001_INIT_DBG(pm8001_ha,
1000 pm8001_printk("Top Register before bringing up BDMA/OSSP"
1001 ":= 0x%x\n", regVal));
1002 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
1003 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1004
1005 /* step 10: delay 10 usec */
1006 udelay(10);
1007
1008 /* step 11: reads and sets the GSM Configuration and Reset Register */
1009 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
d95d0001
MS		 1010 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
1011 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 1012 PM8001_FAIL_DBG(pm8001_ha,
1013 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
1014 GSM_ADDR_BASE));
1015 return -1;
1016 }
1017 PM8001_INIT_DBG(pm8001_ha,
1018 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
1019 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
1020 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
1021 /* Put those bits to high */
1022 /* GSM XCBI offset = 0x70 0000
1023 0x00 Bit 13 COM_SLV_SW_RSTB 1
1024 0x00 Bit 12 QSSP_SW_RSTB 1
1025 0x00 Bit 11 RAAE_SW_RSTB 1
1026 0x00 Bit 9 RB_1_SW_RSTB 1
1027 0x00 Bit 8 SM_SW_RSTB 1
1028 */
1029 regVal |= (GSM_CONFIG_RESET_VALUE);
1030 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1031 PM8001_INIT_DBG(pm8001_ha,
1032 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
1033 " Configuration and Reset is set to = 0x%x\n",
1034 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
1035
1036 /* step 12: Restore GSM - Read Address Parity Check */
1037 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1038 /* just for debugging */
1039 PM8001_INIT_DBG(pm8001_ha,
1040 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
1041 " = 0x%x\n", regVal));
1042 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
1043 PM8001_INIT_DBG(pm8001_ha,
1044 pm8001_printk("GSM 0x700038 - Read Address Parity"
1045 " Check Enable is set to = 0x%x\n",
1046 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
1047 /* Restore GSM - Write Address Parity Check */
1048 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1049 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
1050 PM8001_INIT_DBG(pm8001_ha,
1051 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
1052 " Enable is set to = 0x%x\n",
1053 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
1054 /* Restore GSM - Write Data Parity Check */
1055 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1056 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
1057 PM8001_INIT_DBG(pm8001_ha,
1058 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
1059 "is set to = 0x%x\n",
1060 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
1061
1062 /* step 13: bring the IOP and AAP1 out of reset */
1063 /* map 0x00000 to BAR4(0x20), BAR2(win) */
d95d0001
MS		 1064 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1065 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 1066 PM8001_FAIL_DBG(pm8001_ha,
1067 pm8001_printk("Shift Bar4 to 0x%x failed\n",
1068 SPC_TOP_LEVEL_ADDR_BASE));
1069 return -1;
1070 }
1071 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1072 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1073 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1074
1075 /* step 14: delay 10 usec - Normal Mode */
1076 udelay(10);
1077 /* check Soft Reset Normal mode or Soft Reset HDA mode */
1078 if (signature == SPC_SOFT_RESET_SIGNATURE) {
1079 /* step 15 (Normal Mode): wait until scratch pad1 register
1080 bit 2 toggled */
1081 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1082 do {
1083 udelay(1);
1084 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1085 SCRATCH_PAD1_RST;
1086 } while ((regVal != toggleVal) && (--max_wait_count));
1087
1088 if (!max_wait_count) {
1089 regVal = pm8001_cr32(pm8001_ha, 0,
1090 MSGU_SCRATCH_PAD_1);
1091 PM8001_FAIL_DBG(pm8001_ha,
1092 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
1093 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1094 toggleVal, regVal));
1095 PM8001_FAIL_DBG(pm8001_ha,
1096 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1097 pm8001_cr32(pm8001_ha, 0,
1098 MSGU_SCRATCH_PAD_0)));
1099 PM8001_FAIL_DBG(pm8001_ha,
1100 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1101 pm8001_cr32(pm8001_ha, 0,
1102 MSGU_SCRATCH_PAD_2)));
1103 PM8001_FAIL_DBG(pm8001_ha,
1104 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1105 pm8001_cr32(pm8001_ha, 0,
1106 MSGU_SCRATCH_PAD_3)));
d95d0001 1107 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 1108 return -1;
1109 }
1110
1111 /* step 16 (Normal) - Clear ODMR and ODCR */
1112 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1113 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1114
1115 /* step 17 (Normal Mode): wait for the FW and IOP to get
1116 ready - 1 sec timeout */
1117 /* Wait for the SPC Configuration Table to be ready */
1118 if (check_fw_ready(pm8001_ha) == -1) {
1119 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1120 /* return error if MPI Configuration Table not ready */
1121 PM8001_INIT_DBG(pm8001_ha,
1122 pm8001_printk("FW not ready SCRATCH_PAD1"
1123 " = 0x%x\n", regVal));
1124 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1125 /* return error if MPI Configuration Table not ready */
1126 PM8001_INIT_DBG(pm8001_ha,
1127 pm8001_printk("FW not ready SCRATCH_PAD2"
1128 " = 0x%x\n", regVal));
1129 PM8001_INIT_DBG(pm8001_ha,
1130 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1131 pm8001_cr32(pm8001_ha, 0,
1132 MSGU_SCRATCH_PAD_0)));
1133 PM8001_INIT_DBG(pm8001_ha,
1134 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1135 pm8001_cr32(pm8001_ha, 0,
1136 MSGU_SCRATCH_PAD_3)));
d95d0001 1137 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 1138 return -1;
1139 }
1140 }
d95d0001
MS		 1141 pm8001_bar4_shift(pm8001_ha, 0);
1142 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 1143
1144 PM8001_INIT_DBG(pm8001_ha,
1145 pm8001_printk("SPC soft reset Complete\n"));
1146 return 0;
1147}
1148
1149static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1150{
1151 u32 i;
1152 u32 regVal;
1153 PM8001_INIT_DBG(pm8001_ha,
1154 pm8001_printk("chip reset start\n"));
1155
1156 /* do SPC chip reset. */
1157 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1158 regVal &= ~(SPC_REG_RESET_DEVICE);
1159 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1160
1161 /* delay 10 usec */
1162 udelay(10);
1163
1164 /* bring chip reset out of reset */
1165 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1166 regVal |= SPC_REG_RESET_DEVICE;
1167 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1168
1169 /* delay 10 usec */
1170 udelay(10);
1171
1172 /* wait for 20 msec until the firmware gets reloaded */
1173 i = 20;
1174 do {
1175 mdelay(1);
1176 } while ((--i) != 0);
1177
1178 PM8001_INIT_DBG(pm8001_ha,
1179 pm8001_printk("chip reset finished\n"));
1180}
1181
1182/**
421f91d2 1183 * pm8001_chip_iounmap - which maped when initialized.
dbf9bfe6 1184 * @pm8001_ha: our hba card information
1185 */
f74cf271 1186void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
dbf9bfe6 1187{
1188 s8 bar, logical = 0;
1189 for (bar = 0; bar < 6; bar++) {
1190 /*
1191 ** logical BARs for SPC:
1192 ** bar 0 and 1 - logical BAR0
1193 ** bar 2 and 3 - logical BAR1
1194 ** bar4 - logical BAR2
1195 ** bar5 - logical BAR3
1196 ** Skip the appropriate assignments:
1197 */
1198 if ((bar == 1) || (bar == 3))
1199 continue;
1200 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1201 iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1202 logical++;
1203 }
1204 }
1205}
1206
1207/**
1208 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1209 * @pm8001_ha: our hba card information
1210 */
1211static void
1212pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1213{
1214 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1215 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1216}
1217
1218 /**
1219 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1220 * @pm8001_ha: our hba card information
1221 */
1222static void
1223pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1224{
1225 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1226}
1227
1228/**
1229 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1230 * @pm8001_ha: our hba card information
1231 */
1232static void
1233pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1234 u32 int_vec_idx)
1235{
1236 u32 msi_index;
1237 u32 value;
1238 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1239 msi_index += MSIX_TABLE_BASE;
1240 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1241 value = (1 << int_vec_idx);
1242 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value);
1243
1244}
1245
1246/**
1247 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1248 * @pm8001_ha: our hba card information
1249 */
1250static void
1251pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1252 u32 int_vec_idx)
1253{
1254 u32 msi_index;
1255 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1256 msi_index += MSIX_TABLE_BASE;
1257 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE);
dbf9bfe6 1258}
d95d0001 1259
dbf9bfe6 1260/**
1261 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1262 * @pm8001_ha: our hba card information
1263 */
1264static void
f74cf271 1265pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
dbf9bfe6 1266{
1267#ifdef PM8001_USE_MSIX
1268 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1269 return;
1270#endif
1271 pm8001_chip_intx_interrupt_enable(pm8001_ha);
1272
1273}
1274
1275/**
1276 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1277 * @pm8001_ha: our hba card information
1278 */
1279static void
f74cf271 1280pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
dbf9bfe6 1281{
1282#ifdef PM8001_USE_MSIX
1283 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1284 return;
1285#endif
1286 pm8001_chip_intx_interrupt_disable(pm8001_ha);
1287
1288}
1289
1290/**
f74cf271
S		 1291 * pm8001_mpi_msg_free_get - get the free message buffer for transfer
1292 * inbound queue.
dbf9bfe6 1293 * @circularQ: the inbound queue we want to transfer to HBA.
1294 * @messageSize: the message size of this transfer, normally it is 64 bytes
1295 * @messagePtr: the pointer to message.
1296 */
f74cf271 1297int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
dbf9bfe6 1298 u16 messageSize, void **messagePtr)
1299{
1300 u32 offset, consumer_index;
1301 struct mpi_msg_hdr *msgHeader;
1302 u8 bcCount = 1; /* only support single buffer */
1303
1304 /* Checks is the requested message size can be allocated in this queue*/
f74cf271 1305 if (messageSize > IOMB_SIZE_SPCV) {
dbf9bfe6 1306 *messagePtr = NULL;
1307 return -1;
1308 }
1309
1310 /* Stores the new consumer index */
1311 consumer_index = pm8001_read_32(circularQ->ci_virt);
1312 circularQ->consumer_index = cpu_to_le32(consumer_index);
99c72ebc 1313 if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
8270ee2a 1314 le32_to_cpu(circularQ->consumer_index)) {
dbf9bfe6 1315 *messagePtr = NULL;
1316 return -1;
1317 }
1318 /* get memory IOMB buffer address */
f74cf271 1319 offset = circularQ->producer_idx * messageSize;
dbf9bfe6 1320 /* increment to next bcCount element */
99c72ebc
MS		 1321 circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1322 % PM8001_MPI_QUEUE;
dbf9bfe6 1323 /* Adds that distance to the base of the region virtual address plus
1324 the message header size*/
1325 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1326 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1327 return 0;
1328}
1329
1330/**
f74cf271
S		 1331 * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
1332 * FW to tell the fw to get this message from IOMB.
dbf9bfe6 1333 * @pm8001_ha: our hba card information
1334 * @circularQ: the inbound queue we want to transfer to HBA.
1335 * @opCode: the operation code represents commands which LLDD and fw recognized.
1336 * @payload: the command payload of each operation command.
1337 */
f74cf271 1338int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
dbf9bfe6 1339 struct inbound_queue_table *circularQ,
f74cf271 1340 u32 opCode, void *payload, u32 responseQueue)
dbf9bfe6 1341{
1342 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
dbf9bfe6 1343 void *pMessage;
1344
f74cf271
S		 1345 if (pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
1346 &pMessage) < 0) {
dbf9bfe6 1347 PM8001_IO_DBG(pm8001_ha,
6fbc7692 1348 pm8001_printk("No free mpi buffer\n"));
dbf9bfe6 1349 return -1;
1350 }
72d0baa0 1351 BUG_ON(!payload);
dbf9bfe6 1352 /*Copy to the payload*/
f74cf271
S		 1353 memcpy(pMessage, payload, (pm8001_ha->iomb_size -
1354 sizeof(struct mpi_msg_hdr)));
dbf9bfe6 1355
1356 /*Build the header*/
1357 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1358 | ((responseQueue & 0x3F) << 16)
1359 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1360
1361 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1362 /*Update the PI to the firmware*/
1363 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1364 circularQ->pi_offset, circularQ->producer_idx);
1365 PM8001_IO_DBG(pm8001_ha,
f74cf271
S		 1366 pm8001_printk("INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
1367 responseQueue, opCode, circularQ->producer_idx,
1368 circularQ->consumer_index));
dbf9bfe6 1369 return 0;
1370}
1371
f74cf271 1372u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
dbf9bfe6 1373 struct outbound_queue_table *circularQ, u8 bc)
1374{
1375 u32 producer_index;
72d0baa0 1376 struct mpi_msg_hdr *msgHeader;
1377 struct mpi_msg_hdr *pOutBoundMsgHeader;
1378
1379 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1380 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
f74cf271 1381 circularQ->consumer_idx * pm8001_ha->iomb_size);
72d0baa0 1382 if (pOutBoundMsgHeader != msgHeader) {
1383 PM8001_FAIL_DBG(pm8001_ha,
1384 pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1385 circularQ->consumer_idx, msgHeader));
1386
1387 /* Update the producer index from SPC */
1388 producer_index = pm8001_read_32(circularQ->pi_virt);
1389 circularQ->producer_index = cpu_to_le32(producer_index);
1390 PM8001_FAIL_DBG(pm8001_ha,
1391 pm8001_printk("consumer_idx = %d producer_index = %d"
1392 "msgHeader = %p\n", circularQ->consumer_idx,
1393 circularQ->producer_index, msgHeader));
1394 return 0;
1395 }
dbf9bfe6 1396 /* free the circular queue buffer elements associated with the message*/
99c72ebc
MS		 1397 circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1398 % PM8001_MPI_QUEUE;
dbf9bfe6 1399 /* update the CI of outbound queue */
1400 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1401 circularQ->consumer_idx);
1402 /* Update the producer index from SPC*/
1403 producer_index = pm8001_read_32(circularQ->pi_virt);
1404 circularQ->producer_index = cpu_to_le32(producer_index);
1405 PM8001_IO_DBG(pm8001_ha,
1406 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1407 circularQ->producer_index));
1408 return 0;
1409}
1410
1411/**
f74cf271
S		 1412 * pm8001_mpi_msg_consume- get the MPI message from outbound queue
1413 * message table.
dbf9bfe6 1414 * @pm8001_ha: our hba card information
1415 * @circularQ: the outbound queue table.
1416 * @messagePtr1: the message contents of this outbound message.
1417 * @pBC: the message size.
1418 */
f74cf271 1419u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
dbf9bfe6 1420 struct outbound_queue_table *circularQ,
1421 void **messagePtr1, u8 *pBC)
1422{
1423 struct mpi_msg_hdr *msgHeader;
1424 __le32 msgHeader_tmp;
1425 u32 header_tmp;
1426 do {
1427 /* If there are not-yet-delivered messages ... */
8270ee2a
SN		 1428 if (le32_to_cpu(circularQ->producer_index)
1429 != circularQ->consumer_idx) {
dbf9bfe6 1430 /*Get the pointer to the circular queue buffer element*/
1431 msgHeader = (struct mpi_msg_hdr *)
1432 (circularQ->base_virt +
f74cf271 1433 circularQ->consumer_idx * pm8001_ha->iomb_size);
dbf9bfe6 1434 /* read header */
1435 header_tmp = pm8001_read_32(msgHeader);
1436 msgHeader_tmp = cpu_to_le32(header_tmp);
8270ee2a 1437 if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
dbf9bfe6 1438 if (OPC_OUB_SKIP_ENTRY !=
8270ee2a 1439 (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
dbf9bfe6 1440 *messagePtr1 =
1441 ((u8 *)msgHeader) +
1442 sizeof(struct mpi_msg_hdr);
8270ee2a
SN		 1443 *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1444 >> 24) & 0x1f);
dbf9bfe6 1445 PM8001_IO_DBG(pm8001_ha,
72d0baa0 1446 pm8001_printk(": CI=%d PI=%d "
1447 "msgHeader=%x\n",
dbf9bfe6 1448 circularQ->consumer_idx,
1449 circularQ->producer_index,
1450 msgHeader_tmp));
1451 return MPI_IO_STATUS_SUCCESS;
1452 } else {
dbf9bfe6 1453 circularQ->consumer_idx =
1454 (circularQ->consumer_idx +
8270ee2a 1455 ((le32_to_cpu(msgHeader_tmp)
99c72ebc
MS		 1456 >> 24) & 0x1f))
1457 % PM8001_MPI_QUEUE;
72d0baa0 1458 msgHeader_tmp = 0;
1459 pm8001_write_32(msgHeader, 0, 0);
dbf9bfe6 1460 /* update the CI of outbound queue */
1461 pm8001_cw32(pm8001_ha,
1462 circularQ->ci_pci_bar,
1463 circularQ->ci_offset,
1464 circularQ->consumer_idx);
dbf9bfe6 1465 }
72d0baa0 1466 } else {
1467 circularQ->consumer_idx =
1468 (circularQ->consumer_idx +
8270ee2a 1469 ((le32_to_cpu(msgHeader_tmp) >> 24) &
99c72ebc 1470 0x1f)) % PM8001_MPI_QUEUE;
72d0baa0 1471 msgHeader_tmp = 0;
1472 pm8001_write_32(msgHeader, 0, 0);
1473 /* update the CI of outbound queue */
1474 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1475 circularQ->ci_offset,
1476 circularQ->consumer_idx);
dbf9bfe6 1477 return MPI_IO_STATUS_FAIL;
72d0baa0 1478 }
1479 } else {
1480 u32 producer_index;
1481 void *pi_virt = circularQ->pi_virt;
1482 /* Update the producer index from SPC */
1483 producer_index = pm8001_read_32(pi_virt);
1484 circularQ->producer_index = cpu_to_le32(producer_index);
dbf9bfe6 1485 }
8270ee2a
SN		 1486 } while (le32_to_cpu(circularQ->producer_index) !=
1487 circularQ->consumer_idx);
dbf9bfe6 1488 /* while we don't have any more not-yet-delivered message */
1489 /* report empty */
1490 return MPI_IO_STATUS_BUSY;
1491}
1492
f74cf271 1493void pm8001_work_fn(struct work_struct *work)
dbf9bfe6 1494{
429305e4 1495 struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
dbf9bfe6 1496 struct pm8001_device *pm8001_dev;
429305e4 1497 struct domain_device *dev;
dbf9bfe6 1498
5954d738
MS		 1499 /*
1500 * So far, all users of this stash an associated structure here.
1501 * If we get here, and this pointer is null, then the action
1502 * was cancelled. This nullification happens when the device
1503 * goes away.
1504 */
1505 pm8001_dev = pw->data; /* Most stash device structure */
1506 if ((pm8001_dev == NULL)
1507 || ((pw->handler != IO_XFER_ERROR_BREAK)
1508 && (pm8001_dev->dev_type == NO_DEVICE))) {
1509 kfree(pw);
1510 return;
1511 }
1512
429305e4 1513 switch (pw->handler) {
5954d738
MS		 1514 case IO_XFER_ERROR_BREAK:
1515 { /* This one stashes the sas_task instead */
1516 struct sas_task *t = (struct sas_task *)pm8001_dev;
1517 u32 tag;
1518 struct pm8001_ccb_info *ccb;
1519 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1520 unsigned long flags, flags1;
1521 struct task_status_struct *ts;
1522 int i;
1523
1524 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1525 break; /* Task still on lu */
1526 spin_lock_irqsave(&pm8001_ha->lock, flags);
1527
1528 spin_lock_irqsave(&t->task_state_lock, flags1);
1529 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1530 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1531 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1532 break; /* Task got completed by another */
1533 }
1534 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1535
1536 /* Search for a possible ccb that matches the task */
1537 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1538 ccb = &pm8001_ha->ccb_info[i];
1539 tag = ccb->ccb_tag;
1540 if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1541 break;
1542 }
1543 if (!ccb) {
1544 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1545 break; /* Task got freed by another */
1546 }
1547 ts = &t->task_status;
1548 ts->resp = SAS_TASK_COMPLETE;
1549 /* Force the midlayer to retry */
1550 ts->stat = SAS_QUEUE_FULL;
1551 pm8001_dev = ccb->device;
1552 if (pm8001_dev)
1553 pm8001_dev->running_req--;
1554 spin_lock_irqsave(&t->task_state_lock, flags1);
1555 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1556 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1557 t->task_state_flags |= SAS_TASK_STATE_DONE;
1558 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1559 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1560 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p"
1561 " done with event 0x%x resp 0x%x stat 0x%x but"
1562 " aborted by upper layer!\n",
1563 t, pw->handler, ts->resp, ts->stat));
1564 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1565 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1566 } else {
1567 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1568 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1569 mb();/* in order to force CPU ordering */
1570 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1571 t->task_done(t);
1572 }
1573 } break;
1574 case IO_XFER_OPEN_RETRY_TIMEOUT:
1575 { /* This one stashes the sas_task instead */
1576 struct sas_task *t = (struct sas_task *)pm8001_dev;
1577 u32 tag;
1578 struct pm8001_ccb_info *ccb;
1579 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1580 unsigned long flags, flags1;
1581 int i, ret = 0;
1582
1583 PM8001_IO_DBG(pm8001_ha,
1584 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1585
1586 ret = pm8001_query_task(t);
1587
1588 PM8001_IO_DBG(pm8001_ha,
1589 switch (ret) {
1590 case TMF_RESP_FUNC_SUCC:
1591 pm8001_printk("...Task on lu\n");
1592 break;
1593
1594 case TMF_RESP_FUNC_COMPLETE:
1595 pm8001_printk("...Task NOT on lu\n");
1596 break;
1597
1598 default:
1599 pm8001_printk("...query task failed!!!\n");
1600 break;
1601 });
1602
1603 spin_lock_irqsave(&pm8001_ha->lock, flags);
1604
1605 spin_lock_irqsave(&t->task_state_lock, flags1);
1606
1607 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1608 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1609 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1610 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1611 (void)pm8001_abort_task(t);
1612 break; /* Task got completed by another */
1613 }
1614
1615 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1616
1617 /* Search for a possible ccb that matches the task */
1618 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1619 ccb = &pm8001_ha->ccb_info[i];
1620 tag = ccb->ccb_tag;
1621 if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1622 break;
1623 }
1624 if (!ccb) {
1625 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1626 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1627 (void)pm8001_abort_task(t);
1628 break; /* Task got freed by another */
1629 }
1630
1631 pm8001_dev = ccb->device;
1632 dev = pm8001_dev->sas_device;
1633
1634 switch (ret) {
1635 case TMF_RESP_FUNC_SUCC: /* task on lu */
1636 ccb->open_retry = 1; /* Snub completion */
1637 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1638 ret = pm8001_abort_task(t);
1639 ccb->open_retry = 0;
1640 switch (ret) {
1641 case TMF_RESP_FUNC_SUCC:
1642 case TMF_RESP_FUNC_COMPLETE:
1643 break;
1644 default: /* device misbehavior */
1645 ret = TMF_RESP_FUNC_FAILED;
1646 PM8001_IO_DBG(pm8001_ha,
1647 pm8001_printk("...Reset phy\n"));
1648 pm8001_I_T_nexus_reset(dev);
1649 break;
1650 }
1651 break;
1652
1653 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1654 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1655 /* Do we need to abort the task locally? */
1656 break;
1657
1658 default: /* device misbehavior */
1659 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1660 ret = TMF_RESP_FUNC_FAILED;
1661 PM8001_IO_DBG(pm8001_ha,
1662 pm8001_printk("...Reset phy\n"));
1663 pm8001_I_T_nexus_reset(dev);
1664 }
1665
1666 if (ret == TMF_RESP_FUNC_FAILED)
1667 t = NULL;
1668 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1669 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n"));
1670 } break;
dbf9bfe6 1671 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
dbf9bfe6 1672 dev = pm8001_dev->sas_device;
1673 pm8001_I_T_nexus_reset(dev);
1674 break;
1675 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
dbf9bfe6 1676 dev = pm8001_dev->sas_device;
1677 pm8001_I_T_nexus_reset(dev);
1678 break;
1679 case IO_DS_IN_ERROR:
dbf9bfe6 1680 dev = pm8001_dev->sas_device;
1681 pm8001_I_T_nexus_reset(dev);
1682 break;
1683 case IO_DS_NON_OPERATIONAL:
dbf9bfe6 1684 dev = pm8001_dev->sas_device;
1685 pm8001_I_T_nexus_reset(dev);
1686 break;
1687 }
429305e4 1688 kfree(pw);
dbf9bfe6 1689}
1690
f74cf271 1691int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
dbf9bfe6 1692 int handler)
1693{
429305e4 1694 struct pm8001_work *pw;
dbf9bfe6 1695 int ret = 0;
1696
429305e4
TH		 1697 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1698 if (pw) {
1699 pw->pm8001_ha = pm8001_ha;
1700 pw->data = data;
1701 pw->handler = handler;
1702 INIT_WORK(&pw->work, pm8001_work_fn);
1703 queue_work(pm8001_wq, &pw->work);
dbf9bfe6 1704 } else
1705 ret = -ENOMEM;
1706
1707 return ret;
1708}
1709
1710/**
1711 * mpi_ssp_completion- process the event that FW response to the SSP request.
1712 * @pm8001_ha: our hba card information
1713 * @piomb: the message contents of this outbound message.
1714 *
1715 * When FW has completed a ssp request for example a IO request, after it has
1716 * filled the SG data with the data, it will trigger this event represent
1717 * that he has finished the job,please check the coresponding buffer.
1718 * So we will tell the caller who maybe waiting the result to tell upper layer
1719 * that the task has been finished.
1720 */
72d0baa0 1721static void
dbf9bfe6 1722mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1723{
1724 struct sas_task *t;
1725 struct pm8001_ccb_info *ccb;
1726 unsigned long flags;
1727 u32 status;
1728 u32 param;
1729 u32 tag;
1730 struct ssp_completion_resp *psspPayload;
1731 struct task_status_struct *ts;
1732 struct ssp_response_iu *iu;
1733 struct pm8001_device *pm8001_dev;
1734 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1735 status = le32_to_cpu(psspPayload->status);
1736 tag = le32_to_cpu(psspPayload->tag);
1737 ccb = &pm8001_ha->ccb_info[tag];
5954d738
MS		 1738 if ((status == IO_ABORTED) && ccb->open_retry) {
1739 /* Being completed by another */
1740 ccb->open_retry = 0;
1741 return;
1742 }
dbf9bfe6 1743 pm8001_dev = ccb->device;
1744 param = le32_to_cpu(psspPayload->param);
1745
dbf9bfe6 1746 t = ccb->task;
1747
72d0baa0 1748 if (status && status != IO_UNDERFLOW)
dbf9bfe6 1749 PM8001_FAIL_DBG(pm8001_ha,
1750 pm8001_printk("sas IO status 0x%x\n", status));
1751 if (unlikely(!t || !t->lldd_task || !t->dev))
72d0baa0 1752 return;
dbf9bfe6 1753 ts = &t->task_status;
1754 switch (status) {
1755 case IO_SUCCESS:
1756 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
6fbc7692 1757 ",param = %d\n", param));
dbf9bfe6 1758 if (param == 0) {
1759 ts->resp = SAS_TASK_COMPLETE;
df64d3ca 1760 ts->stat = SAM_STAT_GOOD;
dbf9bfe6 1761 } else {
1762 ts->resp = SAS_TASK_COMPLETE;
1763 ts->stat = SAS_PROTO_RESPONSE;
1764 ts->residual = param;
1765 iu = &psspPayload->ssp_resp_iu;
1766 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1767 }
1768 if (pm8001_dev)
1769 pm8001_dev->running_req--;
1770 break;
1771 case IO_ABORTED:
1772 PM8001_IO_DBG(pm8001_ha,
6fbc7692 1773 pm8001_printk("IO_ABORTED IOMB Tag\n"));
dbf9bfe6 1774 ts->resp = SAS_TASK_COMPLETE;
1775 ts->stat = SAS_ABORTED_TASK;
1776 break;
1777 case IO_UNDERFLOW:
1778 /* SSP Completion with error */
1779 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
6fbc7692 1780 ",param = %d\n", param));
dbf9bfe6 1781 ts->resp = SAS_TASK_COMPLETE;
1782 ts->stat = SAS_DATA_UNDERRUN;
1783 ts->residual = param;
1784 if (pm8001_dev)
1785 pm8001_dev->running_req--;
1786 break;
1787 case IO_NO_DEVICE:
1788 PM8001_IO_DBG(pm8001_ha,
1789 pm8001_printk("IO_NO_DEVICE\n"));
1790 ts->resp = SAS_TASK_UNDELIVERED;
1791 ts->stat = SAS_PHY_DOWN;
1792 break;
1793 case IO_XFER_ERROR_BREAK:
1794 PM8001_IO_DBG(pm8001_ha,
1795 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1796 ts->resp = SAS_TASK_COMPLETE;
1797 ts->stat = SAS_OPEN_REJECT;
5954d738
MS		 1798 /* Force the midlayer to retry */
1799 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
dbf9bfe6 1800 break;
1801 case IO_XFER_ERROR_PHY_NOT_READY:
1802 PM8001_IO_DBG(pm8001_ha,
1803 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1804 ts->resp = SAS_TASK_COMPLETE;
1805 ts->stat = SAS_OPEN_REJECT;
1806 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1807 break;
1808 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1809 PM8001_IO_DBG(pm8001_ha,
1810 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1811 ts->resp = SAS_TASK_COMPLETE;
1812 ts->stat = SAS_OPEN_REJECT;
1813 ts->open_rej_reason = SAS_OREJ_EPROTO;
1814 break;
1815 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1816 PM8001_IO_DBG(pm8001_ha,
1817 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1818 ts->resp = SAS_TASK_COMPLETE;
1819 ts->stat = SAS_OPEN_REJECT;
1820 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1821 break;
1822 case IO_OPEN_CNX_ERROR_BREAK:
1823 PM8001_IO_DBG(pm8001_ha,
1824 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1825 ts->resp = SAS_TASK_COMPLETE;
1826 ts->stat = SAS_OPEN_REJECT;
72d0baa0 1827 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
dbf9bfe6 1828 break;
1829 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1830 PM8001_IO_DBG(pm8001_ha,
1831 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1832 ts->resp = SAS_TASK_COMPLETE;
1833 ts->stat = SAS_OPEN_REJECT;
1834 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1835 if (!t->uldd_task)
1836 pm8001_handle_event(pm8001_ha,
1837 pm8001_dev,
1838 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1839 break;
1840 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1841 PM8001_IO_DBG(pm8001_ha,
1842 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1843 ts->resp = SAS_TASK_COMPLETE;
1844 ts->stat = SAS_OPEN_REJECT;
1845 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1846 break;
1847 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1848 PM8001_IO_DBG(pm8001_ha,
1849 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1850 "NOT_SUPPORTED\n"));
1851 ts->resp = SAS_TASK_COMPLETE;
1852 ts->stat = SAS_OPEN_REJECT;
1853 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1854 break;
1855 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1856 PM8001_IO_DBG(pm8001_ha,
1857 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1858 ts->resp = SAS_TASK_UNDELIVERED;
1859 ts->stat = SAS_OPEN_REJECT;
1860 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1861 break;
1862 case IO_XFER_ERROR_NAK_RECEIVED:
1863 PM8001_IO_DBG(pm8001_ha,
1864 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1865 ts->resp = SAS_TASK_COMPLETE;
1866 ts->stat = SAS_OPEN_REJECT;
72d0baa0 1867 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
dbf9bfe6 1868 break;
1869 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1870 PM8001_IO_DBG(pm8001_ha,
1871 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1872 ts->resp = SAS_TASK_COMPLETE;
1873 ts->stat = SAS_NAK_R_ERR;
1874 break;
1875 case IO_XFER_ERROR_DMA:
1876 PM8001_IO_DBG(pm8001_ha,
1877 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1878 ts->resp = SAS_TASK_COMPLETE;
1879 ts->stat = SAS_OPEN_REJECT;
1880 break;
1881 case IO_XFER_OPEN_RETRY_TIMEOUT:
1882 PM8001_IO_DBG(pm8001_ha,
1883 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1884 ts->resp = SAS_TASK_COMPLETE;
1885 ts->stat = SAS_OPEN_REJECT;
1886 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1887 break;
1888 case IO_XFER_ERROR_OFFSET_MISMATCH:
1889 PM8001_IO_DBG(pm8001_ha,
1890 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1891 ts->resp = SAS_TASK_COMPLETE;
1892 ts->stat = SAS_OPEN_REJECT;
1893 break;
1894 case IO_PORT_IN_RESET:
1895 PM8001_IO_DBG(pm8001_ha,
1896 pm8001_printk("IO_PORT_IN_RESET\n"));
1897 ts->resp = SAS_TASK_COMPLETE;
1898 ts->stat = SAS_OPEN_REJECT;
1899 break;
1900 case IO_DS_NON_OPERATIONAL:
1901 PM8001_IO_DBG(pm8001_ha,
1902 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1903 ts->resp = SAS_TASK_COMPLETE;
1904 ts->stat = SAS_OPEN_REJECT;
1905 if (!t->uldd_task)
1906 pm8001_handle_event(pm8001_ha,
1907 pm8001_dev,
1908 IO_DS_NON_OPERATIONAL);
1909 break;
1910 case IO_DS_IN_RECOVERY:
1911 PM8001_IO_DBG(pm8001_ha,
1912 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1913 ts->resp = SAS_TASK_COMPLETE;
1914 ts->stat = SAS_OPEN_REJECT;
1915 break;
1916 case IO_TM_TAG_NOT_FOUND:
1917 PM8001_IO_DBG(pm8001_ha,
1918 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1919 ts->resp = SAS_TASK_COMPLETE;
1920 ts->stat = SAS_OPEN_REJECT;
1921 break;
1922 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1923 PM8001_IO_DBG(pm8001_ha,
1924 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1925 ts->resp = SAS_TASK_COMPLETE;
1926 ts->stat = SAS_OPEN_REJECT;
1927 break;
1928 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1929 PM8001_IO_DBG(pm8001_ha,
1930 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1931 ts->resp = SAS_TASK_COMPLETE;
1932 ts->stat = SAS_OPEN_REJECT;
1933 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
6fbc7692 1934 break;
dbf9bfe6 1935 default:
1936 PM8001_IO_DBG(pm8001_ha,
1937 pm8001_printk("Unknown status 0x%x\n", status));
1938 /* not allowed case. Therefore, return failed status */
1939 ts->resp = SAS_TASK_COMPLETE;
1940 ts->stat = SAS_OPEN_REJECT;
1941 break;
1942 }
1943 PM8001_IO_DBG(pm8001_ha,
72d0baa0 1944 pm8001_printk("scsi_status = %x \n ",
dbf9bfe6 1945 psspPayload->ssp_resp_iu.status));
1946 spin_lock_irqsave(&t->task_state_lock, flags);
1947 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1948 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1949 t->task_state_flags |= SAS_TASK_STATE_DONE;
1950 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1951 spin_unlock_irqrestore(&t->task_state_lock, flags);
1952 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1953 " io_status 0x%x resp 0x%x "
1954 "stat 0x%x but aborted by upper layer!\n",
1955 t, status, ts->resp, ts->stat));
1956 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1957 } else {
1958 spin_unlock_irqrestore(&t->task_state_lock, flags);
1959 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1960 mb();/* in order to force CPU ordering */
1961 t->task_done(t);
1962 }
dbf9bfe6 1963}
1964
1965/*See the comments for mpi_ssp_completion */
72d0baa0 1966static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
dbf9bfe6 1967{
1968 struct sas_task *t;
1969 unsigned long flags;
1970 struct task_status_struct *ts;
1971 struct pm8001_ccb_info *ccb;
1972 struct pm8001_device *pm8001_dev;
1973 struct ssp_event_resp *psspPayload =
1974 (struct ssp_event_resp *)(piomb + 4);
1975 u32 event = le32_to_cpu(psspPayload->event);
1976 u32 tag = le32_to_cpu(psspPayload->tag);
1977 u32 port_id = le32_to_cpu(psspPayload->port_id);
1978 u32 dev_id = le32_to_cpu(psspPayload->device_id);
1979
1980 ccb = &pm8001_ha->ccb_info[tag];
1981 t = ccb->task;
1982 pm8001_dev = ccb->device;
1983 if (event)
1984 PM8001_FAIL_DBG(pm8001_ha,
1985 pm8001_printk("sas IO status 0x%x\n", event));
1986 if (unlikely(!t || !t->lldd_task || !t->dev))
72d0baa0 1987 return;
dbf9bfe6 1988 ts = &t->task_status;
1989 PM8001_IO_DBG(pm8001_ha,
1990 pm8001_printk("port_id = %x,device_id = %x\n",
1991 port_id, dev_id));
1992 switch (event) {
1993 case IO_OVERFLOW:
1994 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1995 ts->resp = SAS_TASK_COMPLETE;
1996 ts->stat = SAS_DATA_OVERRUN;
1997 ts->residual = 0;
1998 if (pm8001_dev)
1999 pm8001_dev->running_req--;
2000 break;
2001 case IO_XFER_ERROR_BREAK:
2002 PM8001_IO_DBG(pm8001_ha,
2003 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
5954d738
MS		 2004 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2005 return;
dbf9bfe6 2006 case IO_XFER_ERROR_PHY_NOT_READY:
2007 PM8001_IO_DBG(pm8001_ha,
2008 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2009 ts->resp = SAS_TASK_COMPLETE;
2010 ts->stat = SAS_OPEN_REJECT;
2011 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2012 break;
2013 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2014 PM8001_IO_DBG(pm8001_ha,
2015 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2016 "_SUPPORTED\n"));
2017 ts->resp = SAS_TASK_COMPLETE;
2018 ts->stat = SAS_OPEN_REJECT;
2019 ts->open_rej_reason = SAS_OREJ_EPROTO;
2020 break;
2021 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2022 PM8001_IO_DBG(pm8001_ha,
2023 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2024 ts->resp = SAS_TASK_COMPLETE;
2025 ts->stat = SAS_OPEN_REJECT;
2026 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2027 break;
2028 case IO_OPEN_CNX_ERROR_BREAK:
2029 PM8001_IO_DBG(pm8001_ha,
2030 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2031 ts->resp = SAS_TASK_COMPLETE;
2032 ts->stat = SAS_OPEN_REJECT;
72d0baa0 2033 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
dbf9bfe6 2034 break;
2035 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2036 PM8001_IO_DBG(pm8001_ha,
2037 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2038 ts->resp = SAS_TASK_COMPLETE;
2039 ts->stat = SAS_OPEN_REJECT;
2040 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2041 if (!t->uldd_task)
2042 pm8001_handle_event(pm8001_ha,
2043 pm8001_dev,
2044 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2045 break;
2046 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2047 PM8001_IO_DBG(pm8001_ha,
2048 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2049 ts->resp = SAS_TASK_COMPLETE;
2050 ts->stat = SAS_OPEN_REJECT;
2051 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2052 break;
2053 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2054 PM8001_IO_DBG(pm8001_ha,
2055 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2056 "NOT_SUPPORTED\n"));
2057 ts->resp = SAS_TASK_COMPLETE;
2058 ts->stat = SAS_OPEN_REJECT;
2059 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2060 break;
2061 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2062 PM8001_IO_DBG(pm8001_ha,
2063 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2064 ts->resp = SAS_TASK_COMPLETE;
2065 ts->stat = SAS_OPEN_REJECT;
2066 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2067 break;
2068 case IO_XFER_ERROR_NAK_RECEIVED:
2069 PM8001_IO_DBG(pm8001_ha,
2070 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2071 ts->resp = SAS_TASK_COMPLETE;
2072 ts->stat = SAS_OPEN_REJECT;
72d0baa0 2073 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
dbf9bfe6 2074 break;
2075 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2076 PM8001_IO_DBG(pm8001_ha,
2077 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2078 ts->resp = SAS_TASK_COMPLETE;
2079 ts->stat = SAS_NAK_R_ERR;
2080 break;
2081 case IO_XFER_OPEN_RETRY_TIMEOUT:
2082 PM8001_IO_DBG(pm8001_ha,
2083 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
5954d738
MS		 2084 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2085 return;
dbf9bfe6 2086 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2087 PM8001_IO_DBG(pm8001_ha,
2088 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2089 ts->resp = SAS_TASK_COMPLETE;
2090 ts->stat = SAS_DATA_OVERRUN;
2091 break;
2092 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2093 PM8001_IO_DBG(pm8001_ha,
2094 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2095 ts->resp = SAS_TASK_COMPLETE;
2096 ts->stat = SAS_DATA_OVERRUN;
2097 break;
2098 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2099 PM8001_IO_DBG(pm8001_ha,
2100 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2101 ts->resp = SAS_TASK_COMPLETE;
2102 ts->stat = SAS_DATA_OVERRUN;
2103 break;
2104 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2105 PM8001_IO_DBG(pm8001_ha,
2106 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2107 ts->resp = SAS_TASK_COMPLETE;
2108 ts->stat = SAS_DATA_OVERRUN;
2109 break;
2110 case IO_XFER_ERROR_OFFSET_MISMATCH:
2111 PM8001_IO_DBG(pm8001_ha,
2112 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2113 ts->resp = SAS_TASK_COMPLETE;
2114 ts->stat = SAS_DATA_OVERRUN;
2115 break;
2116 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2117 PM8001_IO_DBG(pm8001_ha,
2118 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2119 ts->resp = SAS_TASK_COMPLETE;
2120 ts->stat = SAS_DATA_OVERRUN;
2121 break;
2122 case IO_XFER_CMD_FRAME_ISSUED:
2123 PM8001_IO_DBG(pm8001_ha,
2124 pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n"));
72d0baa0 2125 return;
dbf9bfe6 2126 default:
2127 PM8001_IO_DBG(pm8001_ha,
2128 pm8001_printk("Unknown status 0x%x\n", event));
2129 /* not allowed case. Therefore, return failed status */
2130 ts->resp = SAS_TASK_COMPLETE;
2131 ts->stat = SAS_DATA_OVERRUN;
2132 break;
2133 }
2134 spin_lock_irqsave(&t->task_state_lock, flags);
2135 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2136 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2137 t->task_state_flags |= SAS_TASK_STATE_DONE;
2138 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2139 spin_unlock_irqrestore(&t->task_state_lock, flags);
2140 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2141 " event 0x%x resp 0x%x "
2142 "stat 0x%x but aborted by upper layer!\n",
2143 t, event, ts->resp, ts->stat));
2144 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2145 } else {
2146 spin_unlock_irqrestore(&t->task_state_lock, flags);
2147 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2148 mb();/* in order to force CPU ordering */
2149 t->task_done(t);
2150 }
dbf9bfe6 2151}
2152
2153/*See the comments for mpi_ssp_completion */
72d0baa0 2154static void
dbf9bfe6 2155mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2156{
2157 struct sas_task *t;
2158 struct pm8001_ccb_info *ccb;
dbf9bfe6 2159 u32 param;
2160 u32 status;
2161 u32 tag;
2162 struct sata_completion_resp *psataPayload;
2163 struct task_status_struct *ts;
2164 struct ata_task_resp *resp ;
2165 u32 *sata_resp;
2166 struct pm8001_device *pm8001_dev;
b08c1856 2167 unsigned long flags;
dbf9bfe6 2168
2169 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2170 status = le32_to_cpu(psataPayload->status);
2171 tag = le32_to_cpu(psataPayload->tag);
2172
2173 ccb = &pm8001_ha->ccb_info[tag];
2174 param = le32_to_cpu(psataPayload->param);
2175 t = ccb->task;
2176 ts = &t->task_status;
2177 pm8001_dev = ccb->device;
2178 if (status)
2179 PM8001_FAIL_DBG(pm8001_ha,
2180 pm8001_printk("sata IO status 0x%x\n", status));
2181 if (unlikely(!t || !t->lldd_task || !t->dev))
72d0baa0 2182 return;
dbf9bfe6 2183
2184 switch (status) {
2185 case IO_SUCCESS:
2186 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2187 if (param == 0) {
2188 ts->resp = SAS_TASK_COMPLETE;
df64d3ca 2189 ts->stat = SAM_STAT_GOOD;
dbf9bfe6 2190 } else {
2191 u8 len;
2192 ts->resp = SAS_TASK_COMPLETE;
2193 ts->stat = SAS_PROTO_RESPONSE;
2194 ts->residual = param;
2195 PM8001_IO_DBG(pm8001_ha,
2196 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2197 param));
2198 sata_resp = &psataPayload->sata_resp[0];
2199 resp = (struct ata_task_resp *)ts->buf;
2200 if (t->ata_task.dma_xfer == 0 &&
2201 t->data_dir == PCI_DMA_FROMDEVICE) {
2202 len = sizeof(struct pio_setup_fis);
2203 PM8001_IO_DBG(pm8001_ha,
2204 pm8001_printk("PIO read len = %d\n", len));
2205 } else if (t->ata_task.use_ncq) {
2206 len = sizeof(struct set_dev_bits_fis);
2207 PM8001_IO_DBG(pm8001_ha,
2208 pm8001_printk("FPDMA len = %d\n", len));
2209 } else {
2210 len = sizeof(struct dev_to_host_fis);
2211 PM8001_IO_DBG(pm8001_ha,
2212 pm8001_printk("other len = %d\n", len));
2213 }
2214 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2215 resp->frame_len = len;
2216 memcpy(&resp->ending_fis[0], sata_resp, len);
2217 ts->buf_valid_size = sizeof(*resp);
2218 } else
2219 PM8001_IO_DBG(pm8001_ha,
6fbc7692 2220 pm8001_printk("response to large\n"));
dbf9bfe6 2221 }
2222 if (pm8001_dev)
2223 pm8001_dev->running_req--;
2224 break;
2225 case IO_ABORTED:
2226 PM8001_IO_DBG(pm8001_ha,
6fbc7692 2227 pm8001_printk("IO_ABORTED IOMB Tag\n"));
dbf9bfe6 2228 ts->resp = SAS_TASK_COMPLETE;
2229 ts->stat = SAS_ABORTED_TASK;
2230 if (pm8001_dev)
2231 pm8001_dev->running_req--;
2232 break;
2233 /* following cases are to do cases */
2234 case IO_UNDERFLOW:
2235 /* SATA Completion with error */
2236 PM8001_IO_DBG(pm8001_ha,
2237 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2238 ts->resp = SAS_TASK_COMPLETE;
2239 ts->stat = SAS_DATA_UNDERRUN;
2240 ts->residual = param;
2241 if (pm8001_dev)
2242 pm8001_dev->running_req--;
2243 break;
2244 case IO_NO_DEVICE:
2245 PM8001_IO_DBG(pm8001_ha,
2246 pm8001_printk("IO_NO_DEVICE\n"));
2247 ts->resp = SAS_TASK_UNDELIVERED;
2248 ts->stat = SAS_PHY_DOWN;
2249 break;
2250 case IO_XFER_ERROR_BREAK:
2251 PM8001_IO_DBG(pm8001_ha,
2252 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2253 ts->resp = SAS_TASK_COMPLETE;
2254 ts->stat = SAS_INTERRUPTED;
2255 break;
2256 case IO_XFER_ERROR_PHY_NOT_READY:
2257 PM8001_IO_DBG(pm8001_ha,
2258 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2259 ts->resp = SAS_TASK_COMPLETE;
2260 ts->stat = SAS_OPEN_REJECT;
2261 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2262 break;
2263 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2264 PM8001_IO_DBG(pm8001_ha,
2265 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2266 "_SUPPORTED\n"));
2267 ts->resp = SAS_TASK_COMPLETE;
2268 ts->stat = SAS_OPEN_REJECT;
2269 ts->open_rej_reason = SAS_OREJ_EPROTO;
2270 break;
2271 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2272 PM8001_IO_DBG(pm8001_ha,
2273 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2274 ts->resp = SAS_TASK_COMPLETE;
2275 ts->stat = SAS_OPEN_REJECT;
2276 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2277 break;
2278 case IO_OPEN_CNX_ERROR_BREAK:
2279 PM8001_IO_DBG(pm8001_ha,
2280 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2281 ts->resp = SAS_TASK_COMPLETE;
2282 ts->stat = SAS_OPEN_REJECT;
2283 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2284 break;
2285 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2286 PM8001_IO_DBG(pm8001_ha,
2287 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2288 ts->resp = SAS_TASK_COMPLETE;
2289 ts->stat = SAS_DEV_NO_RESPONSE;
2290 if (!t->uldd_task) {
2291 pm8001_handle_event(pm8001_ha,
2292 pm8001_dev,
2293 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2294 ts->resp = SAS_TASK_UNDELIVERED;
2295 ts->stat = SAS_QUEUE_FULL;
2296 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2297 mb();/*in order to force CPU ordering*/
bdaefbf5 2298 spin_unlock_irq(&pm8001_ha->lock);
dbf9bfe6 2299 t->task_done(t);
bdaefbf5 2300 spin_lock_irq(&pm8001_ha->lock);
72d0baa0 2301 return;
dbf9bfe6 2302 }
2303 break;
2304 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2305 PM8001_IO_DBG(pm8001_ha,
2306 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2307 ts->resp = SAS_TASK_UNDELIVERED;
2308 ts->stat = SAS_OPEN_REJECT;
2309 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2310 if (!t->uldd_task) {
2311 pm8001_handle_event(pm8001_ha,
2312 pm8001_dev,
2313 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2314 ts->resp = SAS_TASK_UNDELIVERED;
2315 ts->stat = SAS_QUEUE_FULL;
2316 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2317 mb();/*ditto*/
bdaefbf5 2318 spin_unlock_irq(&pm8001_ha->lock);
dbf9bfe6 2319 t->task_done(t);
bdaefbf5 2320 spin_lock_irq(&pm8001_ha->lock);
72d0baa0 2321 return;
dbf9bfe6 2322 }
2323 break;
2324 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2325 PM8001_IO_DBG(pm8001_ha,
2326 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2327 "NOT_SUPPORTED\n"));
2328 ts->resp = SAS_TASK_COMPLETE;
2329 ts->stat = SAS_OPEN_REJECT;
2330 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2331 break;
2332 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2333 PM8001_IO_DBG(pm8001_ha,
2334 pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2335 "_BUSY\n"));
2336 ts->resp = SAS_TASK_COMPLETE;
2337 ts->stat = SAS_DEV_NO_RESPONSE;
2338 if (!t->uldd_task) {
2339 pm8001_handle_event(pm8001_ha,
2340 pm8001_dev,
2341 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2342 ts->resp = SAS_TASK_UNDELIVERED;
2343 ts->stat = SAS_QUEUE_FULL;
2344 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2345 mb();/* ditto*/
bdaefbf5 2346 spin_unlock_irq(&pm8001_ha->lock);
dbf9bfe6 2347 t->task_done(t);
bdaefbf5 2348 spin_lock_irq(&pm8001_ha->lock);
72d0baa0 2349 return;
dbf9bfe6 2350 }
2351 break;
2352 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2353 PM8001_IO_DBG(pm8001_ha,
2354 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2355 ts->resp = SAS_TASK_COMPLETE;
2356 ts->stat = SAS_OPEN_REJECT;
2357 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2358 break;
2359 case IO_XFER_ERROR_NAK_RECEIVED:
2360 PM8001_IO_DBG(pm8001_ha,
2361 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2362 ts->resp = SAS_TASK_COMPLETE;
2363 ts->stat = SAS_NAK_R_ERR;
2364 break;
2365 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2366 PM8001_IO_DBG(pm8001_ha,
2367 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2368 ts->resp = SAS_TASK_COMPLETE;
2369 ts->stat = SAS_NAK_R_ERR;
2370 break;
2371 case IO_XFER_ERROR_DMA:
2372 PM8001_IO_DBG(pm8001_ha,
2373 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2374 ts->resp = SAS_TASK_COMPLETE;
2375 ts->stat = SAS_ABORTED_TASK;
2376 break;
2377 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2378 PM8001_IO_DBG(pm8001_ha,
2379 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2380 ts->resp = SAS_TASK_UNDELIVERED;
2381 ts->stat = SAS_DEV_NO_RESPONSE;
2382 break;
2383 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2384 PM8001_IO_DBG(pm8001_ha,
2385 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2386 ts->resp = SAS_TASK_COMPLETE;
2387 ts->stat = SAS_DATA_UNDERRUN;
2388 break;
2389 case IO_XFER_OPEN_RETRY_TIMEOUT:
2390 PM8001_IO_DBG(pm8001_ha,
2391 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2392 ts->resp = SAS_TASK_COMPLETE;
2393 ts->stat = SAS_OPEN_TO;
2394 break;
2395 case IO_PORT_IN_RESET:
2396 PM8001_IO_DBG(pm8001_ha,
2397 pm8001_printk("IO_PORT_IN_RESET\n"));
2398 ts->resp = SAS_TASK_COMPLETE;
2399 ts->stat = SAS_DEV_NO_RESPONSE;
2400 break;
2401 case IO_DS_NON_OPERATIONAL:
2402 PM8001_IO_DBG(pm8001_ha,
2403 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2404 ts->resp = SAS_TASK_COMPLETE;
2405 ts->stat = SAS_DEV_NO_RESPONSE;
2406 if (!t->uldd_task) {
2407 pm8001_handle_event(pm8001_ha, pm8001_dev,
2408 IO_DS_NON_OPERATIONAL);
2409 ts->resp = SAS_TASK_UNDELIVERED;
2410 ts->stat = SAS_QUEUE_FULL;
2411 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2412 mb();/*ditto*/
bdaefbf5 2413 spin_unlock_irq(&pm8001_ha->lock);
dbf9bfe6 2414 t->task_done(t);
bdaefbf5 2415 spin_lock_irq(&pm8001_ha->lock);
72d0baa0 2416 return;
dbf9bfe6 2417 }
2418 break;
2419 case IO_DS_IN_RECOVERY:
2420 PM8001_IO_DBG(pm8001_ha,
2421 pm8001_printk(" IO_DS_IN_RECOVERY\n"));
2422 ts->resp = SAS_TASK_COMPLETE;
2423 ts->stat = SAS_DEV_NO_RESPONSE;
2424 break;
2425 case IO_DS_IN_ERROR:
2426 PM8001_IO_DBG(pm8001_ha,
2427 pm8001_printk("IO_DS_IN_ERROR\n"));
2428 ts->resp = SAS_TASK_COMPLETE;
2429 ts->stat = SAS_DEV_NO_RESPONSE;
2430 if (!t->uldd_task) {
2431 pm8001_handle_event(pm8001_ha, pm8001_dev,
2432 IO_DS_IN_ERROR);
2433 ts->resp = SAS_TASK_UNDELIVERED;
2434 ts->stat = SAS_QUEUE_FULL;
2435 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2436 mb();/*ditto*/
bdaefbf5 2437 spin_unlock_irq(&pm8001_ha->lock);
dbf9bfe6 2438 t->task_done(t);
bdaefbf5 2439 spin_lock_irq(&pm8001_ha->lock);
72d0baa0 2440 return;
dbf9bfe6 2441 }
2442 break;
2443 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2444 PM8001_IO_DBG(pm8001_ha,
2445 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2446 ts->resp = SAS_TASK_COMPLETE;
2447 ts->stat = SAS_OPEN_REJECT;
2448 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2449 default:
2450 PM8001_IO_DBG(pm8001_ha,
2451 pm8001_printk("Unknown status 0x%x\n", status));
2452 /* not allowed case. Therefore, return failed status */
2453 ts->resp = SAS_TASK_COMPLETE;
2454 ts->stat = SAS_DEV_NO_RESPONSE;
2455 break;
2456 }
b08c1856 2457 spin_lock_irqsave(&t->task_state_lock, flags);
dbf9bfe6 2458 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2459 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2460 t->task_state_flags |= SAS_TASK_STATE_DONE;
2461 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
b08c1856 2462 spin_unlock_irqrestore(&t->task_state_lock, flags);
dbf9bfe6 2463 PM8001_FAIL_DBG(pm8001_ha,
2464 pm8001_printk("task 0x%p done with io_status 0x%x"
2465 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2466 t, status, ts->resp, ts->stat));
2467 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
9e79e125 2468 } else if (t->uldd_task) {
b08c1856 2469 spin_unlock_irqrestore(&t->task_state_lock, flags);
dbf9bfe6 2470 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2471 mb();/* ditto */
bdaefbf5 2472 spin_unlock_irq(&pm8001_ha->lock);
9e79e125 2473 t->task_done(t);
bdaefbf5 2474 spin_lock_irq(&pm8001_ha->lock);
9e79e125 2475 } else if (!t->uldd_task) {
b08c1856 2476 spin_unlock_irqrestore(&t->task_state_lock, flags);
9e79e125 2477 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2478 mb();/*ditto*/
bdaefbf5 2479 spin_unlock_irq(&pm8001_ha->lock);
dbf9bfe6 2480 t->task_done(t);
bdaefbf5 2481 spin_lock_irq(&pm8001_ha->lock);
dbf9bfe6 2482 }
dbf9bfe6 2483}
2484
2485/*See the comments for mpi_ssp_completion */
72d0baa0 2486static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
dbf9bfe6 2487{
2488 struct sas_task *t;
dbf9bfe6 2489 struct task_status_struct *ts;
2490 struct pm8001_ccb_info *ccb;
2491 struct pm8001_device *pm8001_dev;
2492 struct sata_event_resp *psataPayload =
2493 (struct sata_event_resp *)(piomb + 4);
2494 u32 event = le32_to_cpu(psataPayload->event);
2495 u32 tag = le32_to_cpu(psataPayload->tag);
2496 u32 port_id = le32_to_cpu(psataPayload->port_id);
2497 u32 dev_id = le32_to_cpu(psataPayload->device_id);
b08c1856 2498 unsigned long flags;
dbf9bfe6 2499
2500 ccb = &pm8001_ha->ccb_info[tag];
2501 t = ccb->task;
2502 pm8001_dev = ccb->device;
2503 if (event)
2504 PM8001_FAIL_DBG(pm8001_ha,
2505 pm8001_printk("sata IO status 0x%x\n", event));
2506 if (unlikely(!t || !t->lldd_task || !t->dev))
72d0baa0 2507 return;
dbf9bfe6 2508 ts = &t->task_status;
2509 PM8001_IO_DBG(pm8001_ha,
2510 pm8001_printk("port_id = %x,device_id = %x\n",
2511 port_id, dev_id));
2512 switch (event) {
2513 case IO_OVERFLOW:
2514 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2515 ts->resp = SAS_TASK_COMPLETE;
2516 ts->stat = SAS_DATA_OVERRUN;
2517 ts->residual = 0;
2518 if (pm8001_dev)
2519 pm8001_dev->running_req--;
2520 break;
2521 case IO_XFER_ERROR_BREAK:
2522 PM8001_IO_DBG(pm8001_ha,
2523 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2524 ts->resp = SAS_TASK_COMPLETE;
2525 ts->stat = SAS_INTERRUPTED;
2526 break;
2527 case IO_XFER_ERROR_PHY_NOT_READY:
2528 PM8001_IO_DBG(pm8001_ha,
2529 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2530 ts->resp = SAS_TASK_COMPLETE;
2531 ts->stat = SAS_OPEN_REJECT;
2532 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2533 break;
2534 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2535 PM8001_IO_DBG(pm8001_ha,
2536 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2537 "_SUPPORTED\n"));
2538 ts->resp = SAS_TASK_COMPLETE;
2539 ts->stat = SAS_OPEN_REJECT;
2540 ts->open_rej_reason = SAS_OREJ_EPROTO;
2541 break;
2542 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2543 PM8001_IO_DBG(pm8001_ha,
2544 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2545 ts->resp = SAS_TASK_COMPLETE;
2546 ts->stat = SAS_OPEN_REJECT;
2547 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2548 break;
2549 case IO_OPEN_CNX_ERROR_BREAK:
2550 PM8001_IO_DBG(pm8001_ha,
2551 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2552 ts->resp = SAS_TASK_COMPLETE;
2553 ts->stat = SAS_OPEN_REJECT;
2554 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2555 break;
2556 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2557 PM8001_IO_DBG(pm8001_ha,
2558 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2559 ts->resp = SAS_TASK_UNDELIVERED;
2560 ts->stat = SAS_DEV_NO_RESPONSE;
2561 if (!t->uldd_task) {
2562 pm8001_handle_event(pm8001_ha,
2563 pm8001_dev,
2564 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2565 ts->resp = SAS_TASK_COMPLETE;
2566 ts->stat = SAS_QUEUE_FULL;
2567 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2568 mb();/*ditto*/
bdaefbf5 2569 spin_unlock_irq(&pm8001_ha->lock);
dbf9bfe6 2570 t->task_done(t);
bdaefbf5 2571 spin_lock_irq(&pm8001_ha->lock);
72d0baa0 2572 return;
dbf9bfe6 2573 }
2574 break;
2575 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2576 PM8001_IO_DBG(pm8001_ha,
2577 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2578 ts->resp = SAS_TASK_UNDELIVERED;
2579 ts->stat = SAS_OPEN_REJECT;
2580 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2581 break;
2582 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2583 PM8001_IO_DBG(pm8001_ha,
2584 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2585 "NOT_SUPPORTED\n"));
2586 ts->resp = SAS_TASK_COMPLETE;
2587 ts->stat = SAS_OPEN_REJECT;
2588 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2589 break;
2590 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2591 PM8001_IO_DBG(pm8001_ha,
2592 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2593 ts->resp = SAS_TASK_COMPLETE;
2594 ts->stat = SAS_OPEN_REJECT;
2595 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2596 break;
2597 case IO_XFER_ERROR_NAK_RECEIVED:
2598 PM8001_IO_DBG(pm8001_ha,
2599 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2600 ts->resp = SAS_TASK_COMPLETE;
2601 ts->stat = SAS_NAK_R_ERR;
2602 break;
2603 case IO_XFER_ERROR_PEER_ABORTED:
2604 PM8001_IO_DBG(pm8001_ha,
2605 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2606 ts->resp = SAS_TASK_COMPLETE;
2607 ts->stat = SAS_NAK_R_ERR;
2608 break;
2609 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2610 PM8001_IO_DBG(pm8001_ha,
2611 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2612 ts->resp = SAS_TASK_COMPLETE;
2613 ts->stat = SAS_DATA_UNDERRUN;
2614 break;
2615 case IO_XFER_OPEN_RETRY_TIMEOUT:
2616 PM8001_IO_DBG(pm8001_ha,
2617 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2618 ts->resp = SAS_TASK_COMPLETE;
2619 ts->stat = SAS_OPEN_TO;
2620 break;
2621 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2622 PM8001_IO_DBG(pm8001_ha,
2623 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2624 ts->resp = SAS_TASK_COMPLETE;
2625 ts->stat = SAS_OPEN_TO;
2626 break;
2627 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2628 PM8001_IO_DBG(pm8001_ha,
2629 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2630 ts->resp = SAS_TASK_COMPLETE;
2631 ts->stat = SAS_OPEN_TO;
2632 break;
2633 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2634 PM8001_IO_DBG(pm8001_ha,
2635 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2636 ts->resp = SAS_TASK_COMPLETE;
2637 ts->stat = SAS_OPEN_TO;
2638 break;
2639 case IO_XFER_ERROR_OFFSET_MISMATCH:
2640 PM8001_IO_DBG(pm8001_ha,
2641 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2642 ts->resp = SAS_TASK_COMPLETE;
2643 ts->stat = SAS_OPEN_TO;
2644 break;
2645 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2646 PM8001_IO_DBG(pm8001_ha,
2647 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2648 ts->resp = SAS_TASK_COMPLETE;
2649 ts->stat = SAS_OPEN_TO;
2650 break;
2651 case IO_XFER_CMD_FRAME_ISSUED:
2652 PM8001_IO_DBG(pm8001_ha,
2653 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2654 break;
2655 case IO_XFER_PIO_SETUP_ERROR:
2656 PM8001_IO_DBG(pm8001_ha,
2657 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2658 ts->resp = SAS_TASK_COMPLETE;
2659 ts->stat = SAS_OPEN_TO;
2660 break;
2661 default:
2662 PM8001_IO_DBG(pm8001_ha,
2663 pm8001_printk("Unknown status 0x%x\n", event));
2664 /* not allowed case. Therefore, return failed status */
2665 ts->resp = SAS_TASK_COMPLETE;
2666 ts->stat = SAS_OPEN_TO;
2667 break;
2668 }
b08c1856 2669 spin_lock_irqsave(&t->task_state_lock, flags);
dbf9bfe6 2670 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2671 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2672 t->task_state_flags |= SAS_TASK_STATE_DONE;
2673 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
b08c1856 2674 spin_unlock_irqrestore(&t->task_state_lock, flags);
dbf9bfe6 2675 PM8001_FAIL_DBG(pm8001_ha,
2676 pm8001_printk("task 0x%p done with io_status 0x%x"
2677 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2678 t, event, ts->resp, ts->stat));
2679 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
9e79e125 2680 } else if (t->uldd_task) {
b08c1856 2681 spin_unlock_irqrestore(&t->task_state_lock, flags);
dbf9bfe6 2682 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
9e79e125 2683 mb();/* ditto */
bdaefbf5 2684 spin_unlock_irq(&pm8001_ha->lock);
9e79e125 2685 t->task_done(t);
bdaefbf5 2686 spin_lock_irq(&pm8001_ha->lock);
9e79e125 2687 } else if (!t->uldd_task) {
b08c1856 2688 spin_unlock_irqrestore(&t->task_state_lock, flags);
9e79e125 2689 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2690 mb();/*ditto*/
bdaefbf5 2691 spin_unlock_irq(&pm8001_ha->lock);
dbf9bfe6 2692 t->task_done(t);
bdaefbf5 2693 spin_lock_irq(&pm8001_ha->lock);
dbf9bfe6 2694 }
dbf9bfe6 2695}
2696
2697/*See the comments for mpi_ssp_completion */
72d0baa0 2698static void
dbf9bfe6 2699mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2700{
2701 u32 param;
2702 struct sas_task *t;
2703 struct pm8001_ccb_info *ccb;
2704 unsigned long flags;
2705 u32 status;
2706 u32 tag;
2707 struct smp_completion_resp *psmpPayload;
2708 struct task_status_struct *ts;
2709 struct pm8001_device *pm8001_dev;
2710
2711 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2712 status = le32_to_cpu(psmpPayload->status);
2713 tag = le32_to_cpu(psmpPayload->tag);
2714
2715 ccb = &pm8001_ha->ccb_info[tag];
2716 param = le32_to_cpu(psmpPayload->param);
2717 t = ccb->task;
2718 ts = &t->task_status;
2719 pm8001_dev = ccb->device;
2720 if (status)
2721 PM8001_FAIL_DBG(pm8001_ha,
2722 pm8001_printk("smp IO status 0x%x\n", status));
2723 if (unlikely(!t || !t->lldd_task || !t->dev))
72d0baa0 2724 return;
dbf9bfe6 2725
2726 switch (status) {
2727 case IO_SUCCESS:
2728 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2729 ts->resp = SAS_TASK_COMPLETE;
df64d3ca 2730 ts->stat = SAM_STAT_GOOD;
dbf9bfe6 2731 if (pm8001_dev)
2732 pm8001_dev->running_req--;
2733 break;
2734 case IO_ABORTED:
2735 PM8001_IO_DBG(pm8001_ha,
2736 pm8001_printk("IO_ABORTED IOMB\n"));
2737 ts->resp = SAS_TASK_COMPLETE;
2738 ts->stat = SAS_ABORTED_TASK;
2739 if (pm8001_dev)
2740 pm8001_dev->running_req--;
2741 break;
2742 case IO_OVERFLOW:
2743 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2744 ts->resp = SAS_TASK_COMPLETE;
2745 ts->stat = SAS_DATA_OVERRUN;
2746 ts->residual = 0;
2747 if (pm8001_dev)
2748 pm8001_dev->running_req--;
2749 break;
2750 case IO_NO_DEVICE:
2751 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2752 ts->resp = SAS_TASK_COMPLETE;
2753 ts->stat = SAS_PHY_DOWN;
2754 break;
2755 case IO_ERROR_HW_TIMEOUT:
2756 PM8001_IO_DBG(pm8001_ha,
2757 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2758 ts->resp = SAS_TASK_COMPLETE;
df64d3ca 2759 ts->stat = SAM_STAT_BUSY;
dbf9bfe6 2760 break;
2761 case IO_XFER_ERROR_BREAK:
2762 PM8001_IO_DBG(pm8001_ha,
2763 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2764 ts->resp = SAS_TASK_COMPLETE;
df64d3ca 2765 ts->stat = SAM_STAT_BUSY;
dbf9bfe6 2766 break;
2767 case IO_XFER_ERROR_PHY_NOT_READY:
2768 PM8001_IO_DBG(pm8001_ha,
2769 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2770 ts->resp = SAS_TASK_COMPLETE;
df64d3ca 2771 ts->stat = SAM_STAT_BUSY;
dbf9bfe6 2772 break;
2773 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2774 PM8001_IO_DBG(pm8001_ha,
2775 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2776 ts->resp = SAS_TASK_COMPLETE;
2777 ts->stat = SAS_OPEN_REJECT;
2778 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2779 break;
2780 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2781 PM8001_IO_DBG(pm8001_ha,
2782 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2783 ts->resp = SAS_TASK_COMPLETE;
2784 ts->stat = SAS_OPEN_REJECT;
2785 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2786 break;
2787 case IO_OPEN_CNX_ERROR_BREAK:
2788 PM8001_IO_DBG(pm8001_ha,
2789 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2790 ts->resp = SAS_TASK_COMPLETE;
2791 ts->stat = SAS_OPEN_REJECT;
2792 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2793 break;
2794 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2795 PM8001_IO_DBG(pm8001_ha,
2796 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2797 ts->resp = SAS_TASK_COMPLETE;
2798 ts->stat = SAS_OPEN_REJECT;
2799 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2800 pm8001_handle_event(pm8001_ha,
2801 pm8001_dev,
2802 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2803 break;
2804 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2805 PM8001_IO_DBG(pm8001_ha,
2806 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2807 ts->resp = SAS_TASK_COMPLETE;
2808 ts->stat = SAS_OPEN_REJECT;
2809 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2810 break;
2811 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2812 PM8001_IO_DBG(pm8001_ha,
2813 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2814 "NOT_SUPPORTED\n"));
2815 ts->resp = SAS_TASK_COMPLETE;
2816 ts->stat = SAS_OPEN_REJECT;
2817 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2818 break;
2819 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2820 PM8001_IO_DBG(pm8001_ha,
2821 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2822 ts->resp = SAS_TASK_COMPLETE;
2823 ts->stat = SAS_OPEN_REJECT;
2824 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2825 break;
2826 case IO_XFER_ERROR_RX_FRAME:
2827 PM8001_IO_DBG(pm8001_ha,
2828 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2829 ts->resp = SAS_TASK_COMPLETE;
2830 ts->stat = SAS_DEV_NO_RESPONSE;
2831 break;
2832 case IO_XFER_OPEN_RETRY_TIMEOUT:
2833 PM8001_IO_DBG(pm8001_ha,
2834 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2835 ts->resp = SAS_TASK_COMPLETE;
2836 ts->stat = SAS_OPEN_REJECT;
2837 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2838 break;
2839 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2840 PM8001_IO_DBG(pm8001_ha,
2841 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2842 ts->resp = SAS_TASK_COMPLETE;
2843 ts->stat = SAS_QUEUE_FULL;
2844 break;
2845 case IO_PORT_IN_RESET:
2846 PM8001_IO_DBG(pm8001_ha,
2847 pm8001_printk("IO_PORT_IN_RESET\n"));
2848 ts->resp = SAS_TASK_COMPLETE;
2849 ts->stat = SAS_OPEN_REJECT;
2850 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2851 break;
2852 case IO_DS_NON_OPERATIONAL:
2853 PM8001_IO_DBG(pm8001_ha,
2854 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2855 ts->resp = SAS_TASK_COMPLETE;
2856 ts->stat = SAS_DEV_NO_RESPONSE;
2857 break;
2858 case IO_DS_IN_RECOVERY:
2859 PM8001_IO_DBG(pm8001_ha,
2860 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2861 ts->resp = SAS_TASK_COMPLETE;
2862 ts->stat = SAS_OPEN_REJECT;
2863 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2864 break;
2865 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2866 PM8001_IO_DBG(pm8001_ha,
2867 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2868 ts->resp = SAS_TASK_COMPLETE;
2869 ts->stat = SAS_OPEN_REJECT;
2870 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2871 break;
2872 default:
2873 PM8001_IO_DBG(pm8001_ha,
2874 pm8001_printk("Unknown status 0x%x\n", status));
2875 ts->resp = SAS_TASK_COMPLETE;
2876 ts->stat = SAS_DEV_NO_RESPONSE;
2877 /* not allowed case. Therefore, return failed status */
2878 break;
2879 }
2880 spin_lock_irqsave(&t->task_state_lock, flags);
2881 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2882 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2883 t->task_state_flags |= SAS_TASK_STATE_DONE;
2884 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2885 spin_unlock_irqrestore(&t->task_state_lock, flags);
2886 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2887 " io_status 0x%x resp 0x%x "
2888 "stat 0x%x but aborted by upper layer!\n",
2889 t, status, ts->resp, ts->stat));
2890 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2891 } else {
2892 spin_unlock_irqrestore(&t->task_state_lock, flags);
2893 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2894 mb();/* in order to force CPU ordering */
2895 t->task_done(t);
2896 }
dbf9bfe6 2897}
2898
f74cf271
S		 2899void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
2900 void *piomb)
dbf9bfe6 2901{
2902 struct set_dev_state_resp *pPayload =
2903 (struct set_dev_state_resp *)(piomb + 4);
2904 u32 tag = le32_to_cpu(pPayload->tag);
2905 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2906 struct pm8001_device *pm8001_dev = ccb->device;
2907 u32 status = le32_to_cpu(pPayload->status);
2908 u32 device_id = le32_to_cpu(pPayload->device_id);
2909 u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS;
2910 u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS;
2911 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
2912 "from 0x%x to 0x%x status = 0x%x!\n",
2913 device_id, pds, nds, status));
2914 complete(pm8001_dev->setds_completion);
2915 ccb->task = NULL;
2916 ccb->ccb_tag = 0xFFFFFFFF;
2917 pm8001_ccb_free(pm8001_ha, tag);
2918}
2919
f74cf271 2920void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
dbf9bfe6 2921{
2922 struct get_nvm_data_resp *pPayload =
2923 (struct get_nvm_data_resp *)(piomb + 4);
2924 u32 tag = le32_to_cpu(pPayload->tag);
2925 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2926 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2927 complete(pm8001_ha->nvmd_completion);
2928 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
2929 if ((dlen_status & NVMD_STAT) != 0) {
2930 PM8001_FAIL_DBG(pm8001_ha,
2931 pm8001_printk("Set nvm data error!\n"));
2932 return;
2933 }
2934 ccb->task = NULL;
2935 ccb->ccb_tag = 0xFFFFFFFF;
2936 pm8001_ccb_free(pm8001_ha, tag);
2937}
2938
f74cf271
S		 2939void
2940pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
dbf9bfe6 2941{
2942 struct fw_control_ex *fw_control_context;
2943 struct get_nvm_data_resp *pPayload =
2944 (struct get_nvm_data_resp *)(piomb + 4);
2945 u32 tag = le32_to_cpu(pPayload->tag);
2946 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2947 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2948 u32 ir_tds_bn_dps_das_nvm =
2949 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
2950 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
2951 fw_control_context = ccb->fw_control_context;
2952
2953 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
2954 if ((dlen_status & NVMD_STAT) != 0) {
2955 PM8001_FAIL_DBG(pm8001_ha,
2956 pm8001_printk("Get nvm data error!\n"));
2957 complete(pm8001_ha->nvmd_completion);
2958 return;
2959 }
2960
2961 if (ir_tds_bn_dps_das_nvm & IPMode) {
2962 /* indirect mode - IR bit set */
2963 PM8001_MSG_DBG(pm8001_ha,
2964 pm8001_printk("Get NVMD success, IR=1\n"));
2965 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
2966 if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
2967 memcpy(pm8001_ha->sas_addr,
2968 ((u8 *)virt_addr + 4),
2969 SAS_ADDR_SIZE);
2970 PM8001_MSG_DBG(pm8001_ha,
2971 pm8001_printk("Get SAS address"
2972 " from VPD successfully!\n"));
2973 }
2974 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
2975 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
2976 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
2977 ;
2978 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
2979 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
2980 ;
2981 } else {
2982 /* Should not be happened*/
2983 PM8001_MSG_DBG(pm8001_ha,
2984 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
2985 ir_tds_bn_dps_das_nvm));
2986 }
2987 } else /* direct mode */{
2988 PM8001_MSG_DBG(pm8001_ha,
2989 pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
2990 (dlen_status & NVMD_LEN) >> 24));
2991 }
72d0baa0 2992 memcpy(fw_control_context->usrAddr,
2993 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
dbf9bfe6 2994 fw_control_context->len);
2995 complete(pm8001_ha->nvmd_completion);
2996 ccb->task = NULL;
2997 ccb->ccb_tag = 0xFFFFFFFF;
2998 pm8001_ccb_free(pm8001_ha, tag);
2999}
3000
f74cf271 3001int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
dbf9bfe6 3002{
3003 struct local_phy_ctl_resp *pPayload =
3004 (struct local_phy_ctl_resp *)(piomb + 4);
3005 u32 status = le32_to_cpu(pPayload->status);
3006 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
3007 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
3008 if (status != 0) {
3009 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3010 pm8001_printk("%x phy execute %x phy op failed!\n",
dbf9bfe6 3011 phy_id, phy_op));
3012 } else
3013 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3014 pm8001_printk("%x phy execute %x phy op success!\n",
dbf9bfe6 3015 phy_id, phy_op));
3016 return 0;
3017}
3018
3019/**
3020 * pm8001_bytes_dmaed - one of the interface function communication with libsas
3021 * @pm8001_ha: our hba card information
3022 * @i: which phy that received the event.
3023 *
3024 * when HBA driver received the identify done event or initiate FIS received
3025 * event(for SATA), it will invoke this function to notify the sas layer that
3026 * the sas toplogy has formed, please discover the the whole sas domain,
3027 * while receive a broadcast(change) primitive just tell the sas
3028 * layer to discover the changed domain rather than the whole domain.
3029 */
f74cf271 3030void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
dbf9bfe6 3031{
3032 struct pm8001_phy *phy = &pm8001_ha->phy[i];
3033 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3034 struct sas_ha_struct *sas_ha;
3035 if (!phy->phy_attached)
3036 return;
3037
3038 sas_ha = pm8001_ha->sas;
3039 if (sas_phy->phy) {
3040 struct sas_phy *sphy = sas_phy->phy;
3041 sphy->negotiated_linkrate = sas_phy->linkrate;
3042 sphy->minimum_linkrate = phy->minimum_linkrate;
3043 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3044 sphy->maximum_linkrate = phy->maximum_linkrate;
3045 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
3046 }
3047
3048 if (phy->phy_type & PORT_TYPE_SAS) {
3049 struct sas_identify_frame *id;
3050 id = (struct sas_identify_frame *)phy->frame_rcvd;
3051 id->dev_type = phy->identify.device_type;
3052 id->initiator_bits = SAS_PROTOCOL_ALL;
3053 id->target_bits = phy->identify.target_port_protocols;
3054 } else if (phy->phy_type & PORT_TYPE_SATA) {
3055 /*Nothing*/
3056 }
3057 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
3058
3059 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
3060 pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
3061}
3062
3063/* Get the link rate speed */
f74cf271 3064void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
dbf9bfe6 3065{
3066 struct sas_phy *sas_phy = phy->sas_phy.phy;
3067
3068 switch (link_rate) {
3069 case PHY_SPEED_60:
3070 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3071 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
3072 break;
3073 case PHY_SPEED_30:
3074 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3075 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3076 break;
3077 case PHY_SPEED_15:
3078 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3079 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3080 break;
3081 }
3082 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3083 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3084 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3085 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3086 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3087}
3088
3089/**
3090 * asd_get_attached_sas_addr -- extract/generate attached SAS address
3091 * @phy: pointer to asd_phy
3092 * @sas_addr: pointer to buffer where the SAS address is to be written
3093 *
3094 * This function extracts the SAS address from an IDENTIFY frame
3095 * received. If OOB is SATA, then a SAS address is generated from the
3096 * HA tables.
3097 *
3098 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3099 * buffer.
3100 */
f74cf271 3101void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
dbf9bfe6 3102 u8 *sas_addr)
3103{
3104 if (phy->sas_phy.frame_rcvd[0] == 0x34
3105 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3106 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3107 /* FIS device-to-host */
3108 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3109 addr += phy->sas_phy.id;
3110 *(__be64 *)sas_addr = cpu_to_be64(addr);
3111 } else {
3112 struct sas_identify_frame *idframe =
3113 (void *) phy->sas_phy.frame_rcvd;
3114 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3115 }
3116}
3117
3118/**
3119 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3120 * @pm8001_ha: our hba card information
3121 * @Qnum: the outbound queue message number.
3122 * @SEA: source of event to ack
3123 * @port_id: port id.
3124 * @phyId: phy id.
3125 * @param0: parameter 0.
3126 * @param1: parameter 1.
3127 */
3128static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3129 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3130{
3131 struct hw_event_ack_req payload;
3132 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3133
3134 struct inbound_queue_table *circularQ;
3135
3136 memset((u8 *)&payload, 0, sizeof(payload));
3137 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
8270ee2a 3138 payload.tag = cpu_to_le32(1);
dbf9bfe6 3139 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3140 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3141 payload.param0 = cpu_to_le32(param0);
3142 payload.param1 = cpu_to_le32(param1);
f74cf271 3143 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
dbf9bfe6 3144}
3145
3146static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3147 u32 phyId, u32 phy_op);
3148
3149/**
3150 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3151 * @pm8001_ha: our hba card information
3152 * @piomb: IO message buffer
3153 */
3154static void
3155hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3156{
3157 struct hw_event_resp *pPayload =
3158 (struct hw_event_resp *)(piomb + 4);
3159 u32 lr_evt_status_phyid_portid =
3160 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3161 u8 link_rate =
3162 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
1cc943ae 3163 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
dbf9bfe6 3164 u8 phy_id =
3165 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
1cc943ae 3166 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3167 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3168 struct pm8001_port *port = &pm8001_ha->port[port_id];
dbf9bfe6 3169 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3170 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3171 unsigned long flags;
3172 u8 deviceType = pPayload->sas_identify.dev_type;
1cc943ae 3173 port->port_state = portstate;
dbf9bfe6 3174 PM8001_MSG_DBG(pm8001_ha,
83e73329 3175 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3176 port_id, phy_id));
dbf9bfe6 3177
3178 switch (deviceType) {
3179 case SAS_PHY_UNUSED:
3180 PM8001_MSG_DBG(pm8001_ha,
3181 pm8001_printk("device type no device.\n"));
3182 break;
3183 case SAS_END_DEVICE:
3184 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3185 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3186 PHY_NOTIFY_ENABLE_SPINUP);
1cc943ae 3187 port->port_attached = 1;
f74cf271 3188 pm8001_get_lrate_mode(phy, link_rate);
dbf9bfe6 3189 break;
3190 case SAS_EDGE_EXPANDER_DEVICE:
3191 PM8001_MSG_DBG(pm8001_ha,
3192 pm8001_printk("expander device.\n"));
1cc943ae 3193 port->port_attached = 1;
f74cf271 3194 pm8001_get_lrate_mode(phy, link_rate);
dbf9bfe6 3195 break;
3196 case SAS_FANOUT_EXPANDER_DEVICE:
3197 PM8001_MSG_DBG(pm8001_ha,
3198 pm8001_printk("fanout expander device.\n"));
1cc943ae 3199 port->port_attached = 1;
f74cf271 3200 pm8001_get_lrate_mode(phy, link_rate);
dbf9bfe6 3201 break;
3202 default:
3203 PM8001_MSG_DBG(pm8001_ha,
3ad2f3fb 3204 pm8001_printk("unknown device type(%x)\n", deviceType));
dbf9bfe6 3205 break;
3206 }
3207 phy->phy_type |= PORT_TYPE_SAS;
3208 phy->identify.device_type = deviceType;
3209 phy->phy_attached = 1;
8270ee2a 3210 if (phy->identify.device_type == SAS_END_DEVICE)
dbf9bfe6 3211 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
8270ee2a 3212 else if (phy->identify.device_type != SAS_PHY_UNUSED)
dbf9bfe6 3213 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3214 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3215 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3216 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3217 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3218 sizeof(struct sas_identify_frame)-4);
3219 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3220 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3221 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3222 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3223 mdelay(200);/*delay a moment to wait disk to spinup*/
3224 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3225}
3226
3227/**
3228 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3229 * @pm8001_ha: our hba card information
3230 * @piomb: IO message buffer
3231 */
3232static void
3233hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3234{
3235 struct hw_event_resp *pPayload =
3236 (struct hw_event_resp *)(piomb + 4);
3237 u32 lr_evt_status_phyid_portid =
3238 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3239 u8 link_rate =
3240 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
1cc943ae 3241 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
dbf9bfe6 3242 u8 phy_id =
3243 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
1cc943ae 3244 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3245 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3246 struct pm8001_port *port = &pm8001_ha->port[port_id];
dbf9bfe6 3247 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3248 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3249 unsigned long flags;
83e73329 3250 PM8001_MSG_DBG(pm8001_ha,
3251 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
3252 " phy id = %d\n", port_id, phy_id));
1cc943ae 3253 port->port_state = portstate;
3254 port->port_attached = 1;
f74cf271 3255 pm8001_get_lrate_mode(phy, link_rate);
dbf9bfe6 3256 phy->phy_type |= PORT_TYPE_SATA;
3257 phy->phy_attached = 1;
3258 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3259 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3260 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3261 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3262 sizeof(struct dev_to_host_fis));
3263 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3264 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3265 phy->identify.device_type = SATA_DEV;
3266 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3267 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3268 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3269}
3270
3271/**
3272 * hw_event_phy_down -we should notify the libsas the phy is down.
3273 * @pm8001_ha: our hba card information
3274 * @piomb: IO message buffer
3275 */
3276static void
3277hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3278{
3279 struct hw_event_resp *pPayload =
3280 (struct hw_event_resp *)(piomb + 4);
3281 u32 lr_evt_status_phyid_portid =
3282 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3283 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3284 u8 phy_id =
3285 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3286 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3287 u8 portstate = (u8)(npip_portstate & 0x0000000F);
1cc943ae 3288 struct pm8001_port *port = &pm8001_ha->port[port_id];
3289 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3290 port->port_state = portstate;
3291 phy->phy_type = 0;
3292 phy->identify.device_type = 0;
3293 phy->phy_attached = 0;
3294 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
dbf9bfe6 3295 switch (portstate) {
3296 case PORT_VALID:
3297 break;
3298 case PORT_INVALID:
3299 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3300 pm8001_printk(" PortInvalid portID %d\n", port_id));
dbf9bfe6 3301 PM8001_MSG_DBG(pm8001_ha,
3302 pm8001_printk(" Last phy Down and port invalid\n"));
1cc943ae 3303 port->port_attached = 0;
dbf9bfe6 3304 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3305 port_id, phy_id, 0, 0);
3306 break;
3307 case PORT_IN_RESET:
3308 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3309 pm8001_printk(" Port In Reset portID %d\n", port_id));
dbf9bfe6 3310 break;
3311 case PORT_NOT_ESTABLISHED:
3312 PM8001_MSG_DBG(pm8001_ha,
3313 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
1cc943ae 3314 port->port_attached = 0;
dbf9bfe6 3315 break;
3316 case PORT_LOSTCOMM:
3317 PM8001_MSG_DBG(pm8001_ha,
3318 pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3319 PM8001_MSG_DBG(pm8001_ha,
3320 pm8001_printk(" Last phy Down and port invalid\n"));
1cc943ae 3321 port->port_attached = 0;
dbf9bfe6 3322 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3323 port_id, phy_id, 0, 0);
3324 break;
3325 default:
1cc943ae 3326 port->port_attached = 0;
dbf9bfe6 3327 PM8001_MSG_DBG(pm8001_ha,
3328 pm8001_printk(" phy Down and(default) = %x\n",
3329 portstate));
3330 break;
3331
3332 }
3333}
3334
3335/**
f74cf271 3336 * pm8001_mpi_reg_resp -process register device ID response.
dbf9bfe6 3337 * @pm8001_ha: our hba card information
3338 * @piomb: IO message buffer
3339 *
3340 * when sas layer find a device it will notify LLDD, then the driver register
3341 * the domain device to FW, this event is the return device ID which the FW
3342 * has assigned, from now,inter-communication with FW is no longer using the
3343 * SAS address, use device ID which FW assigned.
3344 */
f74cf271 3345int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
dbf9bfe6 3346{
3347 u32 status;
3348 u32 device_id;
3349 u32 htag;
3350 struct pm8001_ccb_info *ccb;
3351 struct pm8001_device *pm8001_dev;
3352 struct dev_reg_resp *registerRespPayload =
3353 (struct dev_reg_resp *)(piomb + 4);
3354
3355 htag = le32_to_cpu(registerRespPayload->tag);
8270ee2a 3356 ccb = &pm8001_ha->ccb_info[htag];
dbf9bfe6 3357 pm8001_dev = ccb->device;
3358 status = le32_to_cpu(registerRespPayload->status);
3359 device_id = le32_to_cpu(registerRespPayload->device_id);
3360 PM8001_MSG_DBG(pm8001_ha,
3361 pm8001_printk(" register device is status = %d\n", status));
3362 switch (status) {
3363 case DEVREG_SUCCESS:
3364 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3365 pm8001_dev->device_id = device_id;
3366 break;
3367 case DEVREG_FAILURE_OUT_OF_RESOURCE:
3368 PM8001_MSG_DBG(pm8001_ha,
3369 pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3370 break;
3371 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3372 PM8001_MSG_DBG(pm8001_ha,
3373 pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3374 break;
3375 case DEVREG_FAILURE_INVALID_PHY_ID:
3376 PM8001_MSG_DBG(pm8001_ha,
3377 pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3378 break;
3379 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3380 PM8001_MSG_DBG(pm8001_ha,
3381 pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3382 break;
3383 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3384 PM8001_MSG_DBG(pm8001_ha,
3385 pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3386 break;
3387 case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3388 PM8001_MSG_DBG(pm8001_ha,
3389 pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3390 break;
3391 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3392 PM8001_MSG_DBG(pm8001_ha,
3393 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3394 break;
3395 default:
3396 PM8001_MSG_DBG(pm8001_ha,
3397 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
3398 break;
3399 }
3400 complete(pm8001_dev->dcompletion);
3401 ccb->task = NULL;
3402 ccb->ccb_tag = 0xFFFFFFFF;
3403 pm8001_ccb_free(pm8001_ha, htag);
3404 return 0;
3405}
3406
f74cf271 3407int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
dbf9bfe6 3408{
3409 u32 status;
3410 u32 device_id;
3411 struct dev_reg_resp *registerRespPayload =
3412 (struct dev_reg_resp *)(piomb + 4);
3413
3414 status = le32_to_cpu(registerRespPayload->status);
3415 device_id = le32_to_cpu(registerRespPayload->device_id);
3416 if (status != 0)
3417 PM8001_MSG_DBG(pm8001_ha,
3418 pm8001_printk(" deregister device failed ,status = %x"
3419 ", device_id = %x\n", status, device_id));
3420 return 0;
3421}
3422
f74cf271
S		 3423/**
3424 * fw_flash_update_resp - Response from FW for flash update command.
3425 * @pm8001_ha: our hba card information
3426 * @piomb: IO message buffer
3427 */
3428int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
3429 void *piomb)
dbf9bfe6 3430{
3431 u32 status;
3432 struct fw_control_ex fw_control_context;
3433 struct fw_flash_Update_resp *ppayload =
3434 (struct fw_flash_Update_resp *)(piomb + 4);
fd00f7c1 3435 u32 tag = le32_to_cpu(ppayload->tag);
dbf9bfe6 3436 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3437 status = le32_to_cpu(ppayload->status);
3438 memcpy(&fw_control_context,
3439 ccb->fw_control_context,
3440 sizeof(fw_control_context));
3441 switch (status) {
3442 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3443 PM8001_MSG_DBG(pm8001_ha,
3444 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3445 break;
3446 case FLASH_UPDATE_IN_PROGRESS:
3447 PM8001_MSG_DBG(pm8001_ha,
3448 pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3449 break;
3450 case FLASH_UPDATE_HDR_ERR:
3451 PM8001_MSG_DBG(pm8001_ha,
3452 pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3453 break;
3454 case FLASH_UPDATE_OFFSET_ERR:
3455 PM8001_MSG_DBG(pm8001_ha,
3456 pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3457 break;
3458 case FLASH_UPDATE_CRC_ERR:
3459 PM8001_MSG_DBG(pm8001_ha,
3460 pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3461 break;
3462 case FLASH_UPDATE_LENGTH_ERR:
3463 PM8001_MSG_DBG(pm8001_ha,
3464 pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3465 break;
3466 case FLASH_UPDATE_HW_ERR:
3467 PM8001_MSG_DBG(pm8001_ha,
3468 pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3469 break;
3470 case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3471 PM8001_MSG_DBG(pm8001_ha,
3472 pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3473 break;
3474 case FLASH_UPDATE_DISABLED:
3475 PM8001_MSG_DBG(pm8001_ha,
3476 pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3477 break;
3478 default:
3479 PM8001_MSG_DBG(pm8001_ha,
3480 pm8001_printk("No matched status = %d\n", status));
3481 break;
3482 }
3483 ccb->fw_control_context->fw_control->retcode = status;
dbf9bfe6 3484 complete(pm8001_ha->nvmd_completion);
3485 ccb->task = NULL;
3486 ccb->ccb_tag = 0xFFFFFFFF;
3487 pm8001_ccb_free(pm8001_ha, tag);
3488 return 0;
3489}
3490
f74cf271 3491int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
dbf9bfe6 3492{
3493 u32 status;
3494 int i;
3495 struct general_event_resp *pPayload =
3496 (struct general_event_resp *)(piomb + 4);
3497 status = le32_to_cpu(pPayload->status);
3498 PM8001_MSG_DBG(pm8001_ha,
3499 pm8001_printk(" status = 0x%x\n", status));
3500 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3501 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3502 pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i,
dbf9bfe6 3503 pPayload->inb_IOMB_payload[i]));
3504 return 0;
3505}
3506
f74cf271 3507int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
dbf9bfe6 3508{
3509 struct sas_task *t;
3510 struct pm8001_ccb_info *ccb;
3511 unsigned long flags;
3512 u32 status ;
3513 u32 tag, scp;
3514 struct task_status_struct *ts;
3515
3516 struct task_abort_resp *pPayload =
3517 (struct task_abort_resp *)(piomb + 4);
dbf9bfe6 3518
3519 status = le32_to_cpu(pPayload->status);
3520 tag = le32_to_cpu(pPayload->tag);
3521 scp = le32_to_cpu(pPayload->scp);
8270ee2a
SN		 3522 ccb = &pm8001_ha->ccb_info[tag];
3523 t = ccb->task;
dbf9bfe6 3524 PM8001_IO_DBG(pm8001_ha,
3525 pm8001_printk(" status = 0x%x\n", status));
72d0baa0 3526 if (t == NULL)
3527 return -1;
3528 ts = &t->task_status;
dbf9bfe6 3529 if (status != 0)
3530 PM8001_FAIL_DBG(pm8001_ha,
72d0baa0 3531 pm8001_printk("task abort failed status 0x%x ,"
3532 "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
dbf9bfe6 3533 switch (status) {
3534 case IO_SUCCESS:
72d0baa0 3535 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
dbf9bfe6 3536 ts->resp = SAS_TASK_COMPLETE;
df64d3ca 3537 ts->stat = SAM_STAT_GOOD;
dbf9bfe6 3538 break;
3539 case IO_NOT_VALID:
72d0baa0 3540 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
dbf9bfe6 3541 ts->resp = TMF_RESP_FUNC_FAILED;
3542 break;
3543 }
3544 spin_lock_irqsave(&t->task_state_lock, flags);
3545 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3546 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3547 t->task_state_flags |= SAS_TASK_STATE_DONE;
3548 spin_unlock_irqrestore(&t->task_state_lock, flags);
8270ee2a 3549 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
dbf9bfe6 3550 mb();
3551 t->task_done(t);
3552 return 0;
3553}
3554
3555/**
3556 * mpi_hw_event -The hw event has come.
3557 * @pm8001_ha: our hba card information
3558 * @piomb: IO message buffer
3559 */
3560static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3561{
3562 unsigned long flags;
3563 struct hw_event_resp *pPayload =
3564 (struct hw_event_resp *)(piomb + 4);
3565 u32 lr_evt_status_phyid_portid =
3566 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3567 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3568 u8 phy_id =
3569 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3570 u16 eventType =
3571 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3572 u8 status =
3573 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3574 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3575 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3576 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3577 PM8001_MSG_DBG(pm8001_ha,
3578 pm8001_printk("outbound queue HW event & event type : "));
3579 switch (eventType) {
3580 case HW_EVENT_PHY_START_STATUS:
3581 PM8001_MSG_DBG(pm8001_ha,
3582 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3583 " status = %x\n", status));
3584 if (status == 0) {
3585 phy->phy_state = 1;
3586 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3587 complete(phy->enable_completion);
3588 }
3589 break;
3590 case HW_EVENT_SAS_PHY_UP:
3591 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3592 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
dbf9bfe6 3593 hw_event_sas_phy_up(pm8001_ha, piomb);
3594 break;
3595 case HW_EVENT_SATA_PHY_UP:
3596 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3597 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
dbf9bfe6 3598 hw_event_sata_phy_up(pm8001_ha, piomb);
3599 break;
3600 case HW_EVENT_PHY_STOP_STATUS:
3601 PM8001_MSG_DBG(pm8001_ha,
3602 pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3603 "status = %x\n", status));
3604 if (status == 0)
3605 phy->phy_state = 0;
3606 break;
3607 case HW_EVENT_SATA_SPINUP_HOLD:
3608 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3609 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
dbf9bfe6 3610 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3611 break;
3612 case HW_EVENT_PHY_DOWN:
3613 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3614 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
dbf9bfe6 3615 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3616 phy->phy_attached = 0;
3617 phy->phy_state = 0;
3618 hw_event_phy_down(pm8001_ha, piomb);
3619 break;
3620 case HW_EVENT_PORT_INVALID:
3621 PM8001_MSG_DBG(pm8001_ha,
3622 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3623 sas_phy_disconnected(sas_phy);
3624 phy->phy_attached = 0;
3625 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3626 break;
3627 /* the broadcast change primitive received, tell the LIBSAS this event
3628 to revalidate the sas domain*/
3629 case HW_EVENT_BROADCAST_CHANGE:
3630 PM8001_MSG_DBG(pm8001_ha,
3631 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3632 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3633 port_id, phy_id, 1, 0);
3634 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3635 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3636 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3637 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3638 break;
3639 case HW_EVENT_PHY_ERROR:
3640 PM8001_MSG_DBG(pm8001_ha,
3641 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3642 sas_phy_disconnected(&phy->sas_phy);
3643 phy->phy_attached = 0;
3644 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3645 break;
3646 case HW_EVENT_BROADCAST_EXP:
3647 PM8001_MSG_DBG(pm8001_ha,
3648 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3649 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3650 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3651 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3652 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3653 break;
3654 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3655 PM8001_MSG_DBG(pm8001_ha,
3656 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3657 pm8001_hw_event_ack_req(pm8001_ha, 0,
3658 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3659 sas_phy_disconnected(sas_phy);
3660 phy->phy_attached = 0;
3661 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3662 break;
3663 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3664 PM8001_MSG_DBG(pm8001_ha,
3665 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3666 pm8001_hw_event_ack_req(pm8001_ha, 0,
3667 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3668 port_id, phy_id, 0, 0);
3669 sas_phy_disconnected(sas_phy);
3670 phy->phy_attached = 0;
3671 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3672 break;
3673 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3674 PM8001_MSG_DBG(pm8001_ha,
3675 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3676 pm8001_hw_event_ack_req(pm8001_ha, 0,
3677 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3678 port_id, phy_id, 0, 0);
3679 sas_phy_disconnected(sas_phy);
3680 phy->phy_attached = 0;
3681 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3682 break;
3683 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3684 PM8001_MSG_DBG(pm8001_ha,
3685 pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3686 pm8001_hw_event_ack_req(pm8001_ha, 0,
3687 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3688 port_id, phy_id, 0, 0);
3689 sas_phy_disconnected(sas_phy);
3690 phy->phy_attached = 0;
3691 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3692 break;
3693 case HW_EVENT_MALFUNCTION:
3694 PM8001_MSG_DBG(pm8001_ha,
3695 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3696 break;
3697 case HW_EVENT_BROADCAST_SES:
3698 PM8001_MSG_DBG(pm8001_ha,
3699 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3700 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3701 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3702 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3703 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3704 break;
3705 case HW_EVENT_INBOUND_CRC_ERROR:
3706 PM8001_MSG_DBG(pm8001_ha,
3707 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3708 pm8001_hw_event_ack_req(pm8001_ha, 0,
3709 HW_EVENT_INBOUND_CRC_ERROR,
3710 port_id, phy_id, 0, 0);
3711 break;
3712 case HW_EVENT_HARD_RESET_RECEIVED:
3713 PM8001_MSG_DBG(pm8001_ha,
3714 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3715 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3716 break;
3717 case HW_EVENT_ID_FRAME_TIMEOUT:
3718 PM8001_MSG_DBG(pm8001_ha,
3719 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3720 sas_phy_disconnected(sas_phy);
3721 phy->phy_attached = 0;
3722 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3723 break;
3724 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3725 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3726 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
dbf9bfe6 3727 pm8001_hw_event_ack_req(pm8001_ha, 0,
3728 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3729 port_id, phy_id, 0, 0);
3730 sas_phy_disconnected(sas_phy);
3731 phy->phy_attached = 0;
3732 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3733 break;
3734 case HW_EVENT_PORT_RESET_TIMER_TMO:
3735 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3736 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
dbf9bfe6 3737 sas_phy_disconnected(sas_phy);
3738 phy->phy_attached = 0;
3739 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3740 break;
3741 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3742 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3743 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
dbf9bfe6 3744 sas_phy_disconnected(sas_phy);
3745 phy->phy_attached = 0;
3746 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3747 break;
3748 case HW_EVENT_PORT_RECOVER:
3749 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3750 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
dbf9bfe6 3751 break;
3752 case HW_EVENT_PORT_RESET_COMPLETE:
3753 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3754 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
dbf9bfe6 3755 break;
3756 case EVENT_BROADCAST_ASYNCH_EVENT:
3757 PM8001_MSG_DBG(pm8001_ha,
3758 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3759 break;
3760 default:
3761 PM8001_MSG_DBG(pm8001_ha,
3762 pm8001_printk("Unknown event type = %x\n", eventType));
3763 break;
3764 }
3765 return 0;
3766}
3767
3768/**
3769 * process_one_iomb - process one outbound Queue memory block
3770 * @pm8001_ha: our hba card information
3771 * @piomb: IO message buffer
3772 */
3773static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3774{
fd00f7c1
SN		 3775 __le32 pHeader = *(__le32 *)piomb;
3776 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
dbf9bfe6 3777
72d0baa0 3778 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
dbf9bfe6 3779
3780 switch (opc) {
3781 case OPC_OUB_ECHO:
6fbc7692 3782 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
dbf9bfe6 3783 break;
3784 case OPC_OUB_HW_EVENT:
3785 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3786 pm8001_printk("OPC_OUB_HW_EVENT\n"));
dbf9bfe6 3787 mpi_hw_event(pm8001_ha, piomb);
3788 break;
3789 case OPC_OUB_SSP_COMP:
3790 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3791 pm8001_printk("OPC_OUB_SSP_COMP\n"));
dbf9bfe6 3792 mpi_ssp_completion(pm8001_ha, piomb);
3793 break;
3794 case OPC_OUB_SMP_COMP:
3795 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3796 pm8001_printk("OPC_OUB_SMP_COMP\n"));
dbf9bfe6 3797 mpi_smp_completion(pm8001_ha, piomb);
3798 break;
3799 case OPC_OUB_LOCAL_PHY_CNTRL:
3800 PM8001_MSG_DBG(pm8001_ha,
3801 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
f74cf271 3802 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
dbf9bfe6 3803 break;
3804 case OPC_OUB_DEV_REGIST:
3805 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3806 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
f74cf271 3807 pm8001_mpi_reg_resp(pm8001_ha, piomb);
dbf9bfe6 3808 break;
3809 case OPC_OUB_DEREG_DEV:
3810 PM8001_MSG_DBG(pm8001_ha,
44ebf89e 3811 pm8001_printk("unregister the device\n"));
f74cf271 3812 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
dbf9bfe6 3813 break;
3814 case OPC_OUB_GET_DEV_HANDLE:
3815 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3816 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
dbf9bfe6 3817 break;
3818 case OPC_OUB_SATA_COMP:
3819 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3820 pm8001_printk("OPC_OUB_SATA_COMP\n"));
dbf9bfe6 3821 mpi_sata_completion(pm8001_ha, piomb);
3822 break;
3823 case OPC_OUB_SATA_EVENT:
3824 PM8001_MSG_DBG(pm8001_ha,
6fbc7692 3825 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
dbf9bfe6 3826 mpi_sata_event(pm8001_ha, piomb);
3827 break;
3828 case OPC_OUB_SSP_EVENT:
3829 PM8001_MSG_DBG(pm8001_ha,
3830 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3831 mpi_ssp_event(pm8001_ha, piomb);
3832 break;
3833 case OPC_OUB_DEV_HANDLE_ARRIV:
3834 PM8001_MSG_DBG(pm8001_ha,
3835 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3836 /*This is for target*/
3837 break;
3838 case OPC_OUB_SSP_RECV_EVENT:
3839 PM8001_MSG_DBG(pm8001_ha,
3840 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3841 /*This is for target*/
3842 break;
3843 case OPC_OUB_DEV_INFO:
3844 PM8001_MSG_DBG(pm8001_ha,
3845 pm8001_printk("OPC_OUB_DEV_INFO\n"));
3846 break;
3847 case OPC_OUB_FW_FLASH_UPDATE:
3848 PM8001_MSG_DBG(pm8001_ha,
3849 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
f74cf271 3850 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
dbf9bfe6 3851 break;
3852 case OPC_OUB_GPIO_RESPONSE:
3853 PM8001_MSG_DBG(pm8001_ha,
3854 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3855 break;
3856 case OPC_OUB_GPIO_EVENT:
3857 PM8001_MSG_DBG(pm8001_ha,
3858 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3859 break;
3860 case OPC_OUB_GENERAL_EVENT:
3861 PM8001_MSG_DBG(pm8001_ha,
3862 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
f74cf271 3863 pm8001_mpi_general_event(pm8001_ha, piomb);
dbf9bfe6 3864 break;
3865 case OPC_OUB_SSP_ABORT_RSP:
3866 PM8001_MSG_DBG(pm8001_ha,
3867 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
f74cf271 3868 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
dbf9bfe6 3869 break;
3870 case OPC_OUB_SATA_ABORT_RSP:
3871 PM8001_MSG_DBG(pm8001_ha,
3872 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
f74cf271 3873 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
dbf9bfe6 3874 break;
3875 case OPC_OUB_SAS_DIAG_MODE_START_END:
3876 PM8001_MSG_DBG(pm8001_ha,
3877 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3878 break;
3879 case OPC_OUB_SAS_DIAG_EXECUTE:
3880 PM8001_MSG_DBG(pm8001_ha,
3881 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3882 break;
3883 case OPC_OUB_GET_TIME_STAMP:
3884 PM8001_MSG_DBG(pm8001_ha,
3885 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3886 break;
3887 case OPC_OUB_SAS_HW_EVENT_ACK:
3888 PM8001_MSG_DBG(pm8001_ha,
3889 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3890 break;
3891 case OPC_OUB_PORT_CONTROL:
3892 PM8001_MSG_DBG(pm8001_ha,
3893 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3894 break;
3895 case OPC_OUB_SMP_ABORT_RSP:
3896 PM8001_MSG_DBG(pm8001_ha,
3897 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
f74cf271 3898 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
dbf9bfe6 3899 break;
3900 case OPC_OUB_GET_NVMD_DATA:
3901 PM8001_MSG_DBG(pm8001_ha,
3902 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
f74cf271 3903 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
dbf9bfe6 3904 break;
3905 case OPC_OUB_SET_NVMD_DATA:
3906 PM8001_MSG_DBG(pm8001_ha,
3907 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
f74cf271 3908 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
dbf9bfe6 3909 break;
3910 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3911 PM8001_MSG_DBG(pm8001_ha,
3912 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3913 break;
3914 case OPC_OUB_SET_DEVICE_STATE:
3915 PM8001_MSG_DBG(pm8001_ha,
3916 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
f74cf271 3917 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
dbf9bfe6 3918 break;
3919 case OPC_OUB_GET_DEVICE_STATE:
3920 PM8001_MSG_DBG(pm8001_ha,
3921 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3922 break;
3923 case OPC_OUB_SET_DEV_INFO:
3924 PM8001_MSG_DBG(pm8001_ha,
3925 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3926 break;
3927 case OPC_OUB_SAS_RE_INITIALIZE:
3928 PM8001_MSG_DBG(pm8001_ha,
3929 pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
3930 break;
3931 default:
3932 PM8001_MSG_DBG(pm8001_ha,
3933 pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
3934 opc));
3935 break;
3936 }
3937}
3938
f74cf271 3939static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
dbf9bfe6 3940{
3941 struct outbound_queue_table *circularQ;
3942 void *pMsg1 = NULL;
8270ee2a 3943 u8 uninitialized_var(bc);
72d0baa0 3944 u32 ret = MPI_IO_STATUS_FAIL;
50ec5bab 3945 unsigned long flags;
dbf9bfe6 3946
50ec5bab 3947 spin_lock_irqsave(&pm8001_ha->lock, flags);
f74cf271 3948 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
dbf9bfe6 3949 do {
f74cf271 3950 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
dbf9bfe6 3951 if (MPI_IO_STATUS_SUCCESS == ret) {
3952 /* process the outbound message */
72d0baa0 3953 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
dbf9bfe6 3954 /* free the message from the outbound circular buffer */
f74cf271
S		 3955 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3956 circularQ, bc);
dbf9bfe6 3957 }
3958 if (MPI_IO_STATUS_BUSY == ret) {
dbf9bfe6 3959 /* Update the producer index from SPC */
8270ee2a
SN		 3960 circularQ->producer_index =
3961 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3962 if (le32_to_cpu(circularQ->producer_index) ==
dbf9bfe6 3963 circularQ->consumer_idx)
3964 /* OQ is empty */
3965 break;
3966 }
72d0baa0 3967 } while (1);
50ec5bab 3968 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
dbf9bfe6 3969 return ret;
3970}
3971
3972/* PCI_DMA_... to our direction translation. */
3973static const u8 data_dir_flags[] = {
3974 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3975 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
3976 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
3977 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
3978};
f74cf271 3979void
dbf9bfe6 3980pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
3981{
3982 int i;
3983 struct scatterlist *sg;
3984 struct pm8001_prd *buf_prd = prd;
3985
3986 for_each_sg(scatter, sg, nr, i) {
3987 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
3988 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
3989 buf_prd->im_len.e = 0;
3990 buf_prd++;
3991 }
3992}
3993
8270ee2a 3994static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
dbf9bfe6 3995{
8270ee2a 3996 psmp_cmd->tag = hTag;
dbf9bfe6 3997 psmp_cmd->device_id = cpu_to_le32(deviceID);
3998 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3999}
4000
4001/**
4002 * pm8001_chip_smp_req - send a SMP task to FW
4003 * @pm8001_ha: our hba card information.
4004 * @ccb: the ccb information this request used.
4005 */
4006static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4007 struct pm8001_ccb_info *ccb)
4008{
4009 int elem, rc;
4010 struct sas_task *task = ccb->task;
4011 struct domain_device *dev = task->dev;
4012 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4013 struct scatterlist *sg_req, *sg_resp;
4014 u32 req_len, resp_len;
4015 struct smp_req smp_cmd;
4016 u32 opc;
4017 struct inbound_queue_table *circularQ;
4018
4019 memset(&smp_cmd, 0, sizeof(smp_cmd));
4020 /*
4021 * DMA-map SMP request, response buffers
4022 */
4023 sg_req = &task->smp_task.smp_req;
4024 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
4025 if (!elem)
4026 return -ENOMEM;
4027 req_len = sg_dma_len(sg_req);
4028
4029 sg_resp = &task->smp_task.smp_resp;
4030 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
4031 if (!elem) {
4032 rc = -ENOMEM;
4033 goto err_out;
4034 }
4035 resp_len = sg_dma_len(sg_resp);
4036 /* must be in dwords */
4037 if ((req_len & 0x3) || (resp_len & 0x3)) {
4038 rc = -EINVAL;
4039 goto err_out_2;
4040 }
4041
4042 opc = OPC_INB_SMP_REQUEST;
4043 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4044 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4045 smp_cmd.long_smp_req.long_req_addr =
4046 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4047 smp_cmd.long_smp_req.long_req_size =
4048 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4049 smp_cmd.long_smp_req.long_resp_addr =
4050 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
4051 smp_cmd.long_smp_req.long_resp_size =
4052 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4053 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
f74cf271 4054 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd, 0);
dbf9bfe6 4055 return 0;
4056
4057err_out_2:
4058 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4059 PCI_DMA_FROMDEVICE);
4060err_out:
4061 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4062 PCI_DMA_TODEVICE);
4063 return rc;
4064}
4065
4066/**
4067 * pm8001_chip_ssp_io_req - send a SSP task to FW
4068 * @pm8001_ha: our hba card information.
4069 * @ccb: the ccb information this request used.
4070 */
4071static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4072 struct pm8001_ccb_info *ccb)
4073{
4074 struct sas_task *task = ccb->task;
4075 struct domain_device *dev = task->dev;
4076 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4077 struct ssp_ini_io_start_req ssp_cmd;
4078 u32 tag = ccb->ccb_tag;
72d0baa0 4079 int ret;
8270ee2a 4080 u64 phys_addr;
dbf9bfe6 4081 struct inbound_queue_table *circularQ;
4082 u32 opc = OPC_INB_SSPINIIOSTART;
4083 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4084 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
afc5ca9d 4085 ssp_cmd.dir_m_tlr =
4086 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
dbf9bfe6 4087 SAS 1.1 compatible TLR*/
4088 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4089 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4090 ssp_cmd.tag = cpu_to_le32(tag);
4091 if (task->ssp_task.enable_first_burst)
4092 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4093 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4094 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4095 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16);
4096 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4097
4098 /* fill in PRD (scatter/gather) table, if any */
4099 if (task->num_scatter > 1) {
4100 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
8270ee2a
SN		 4101 phys_addr = ccb->ccb_dma_handle +
4102 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4103 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4104 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
dbf9bfe6 4105 ssp_cmd.esgl = cpu_to_le32(1<<31);
4106 } else if (task->num_scatter == 1) {
8270ee2a
SN		 4107 u64 dma_addr = sg_dma_address(task->scatter);
4108 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4109 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
dbf9bfe6 4110 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4111 ssp_cmd.esgl = 0;
4112 } else if (task->num_scatter == 0) {
4113 ssp_cmd.addr_low = 0;
4114 ssp_cmd.addr_high = 0;
4115 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4116 ssp_cmd.esgl = 0;
4117 }
f74cf271 4118 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd, 0);
72d0baa0 4119 return ret;
dbf9bfe6 4120}
4121
4122static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4123 struct pm8001_ccb_info *ccb)
4124{
4125 struct sas_task *task = ccb->task;
4126 struct domain_device *dev = task->dev;
4127 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4128 u32 tag = ccb->ccb_tag;
72d0baa0 4129 int ret;
dbf9bfe6 4130 struct sata_start_req sata_cmd;
4131 u32 hdr_tag, ncg_tag = 0;
8270ee2a 4132 u64 phys_addr;
dbf9bfe6 4133 u32 ATAP = 0x0;
4134 u32 dir;
4135 struct inbound_queue_table *circularQ;
4136 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4137 memset(&sata_cmd, 0, sizeof(sata_cmd));
4138 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4139 if (task->data_dir == PCI_DMA_NONE) {
4140 ATAP = 0x04; /* no data*/
6fbc7692 4141 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
dbf9bfe6 4142 } else if (likely(!task->ata_task.device_control_reg_update)) {
4143 if (task->ata_task.dma_xfer) {
4144 ATAP = 0x06; /* DMA */
6fbc7692 4145 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
dbf9bfe6 4146 } else {
4147 ATAP = 0x05; /* PIO*/
6fbc7692 4148 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
dbf9bfe6 4149 }
4150 if (task->ata_task.use_ncq &&
4151 dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
4152 ATAP = 0x07; /* FPDMA */
6fbc7692 4153 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
dbf9bfe6 4154 }
4155 }
4156 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag))
afc5ca9d 4157 ncg_tag = hdr_tag;
dbf9bfe6 4158 dir = data_dir_flags[task->data_dir] << 8;
4159 sata_cmd.tag = cpu_to_le32(tag);
4160 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4161 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4162 sata_cmd.ncqtag_atap_dir_m =
4163 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4164 sata_cmd.sata_fis = task->ata_task.fis;
4165 if (likely(!task->ata_task.device_control_reg_update))
4166 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4167 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4168 /* fill in PRD (scatter/gather) table, if any */
4169 if (task->num_scatter > 1) {
4170 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
8270ee2a
SN		 4171 phys_addr = ccb->ccb_dma_handle +
4172 offsetof(struct pm8001_ccb_info, buf_prd[0]);
dbf9bfe6 4173 sata_cmd.addr_low = lower_32_bits(phys_addr);
4174 sata_cmd.addr_high = upper_32_bits(phys_addr);
4175 sata_cmd.esgl = cpu_to_le32(1 << 31);
4176 } else if (task->num_scatter == 1) {
8270ee2a 4177 u64 dma_addr = sg_dma_address(task->scatter);
dbf9bfe6 4178 sata_cmd.addr_low = lower_32_bits(dma_addr);
4179 sata_cmd.addr_high = upper_32_bits(dma_addr);
4180 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4181 sata_cmd.esgl = 0;
4182 } else if (task->num_scatter == 0) {
4183 sata_cmd.addr_low = 0;
4184 sata_cmd.addr_high = 0;
4185 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4186 sata_cmd.esgl = 0;
4187 }
f74cf271 4188 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
72d0baa0 4189 return ret;
dbf9bfe6 4190}
4191
4192/**
4193 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4194 * @pm8001_ha: our hba card information.
4195 * @num: the inbound queue number
4196 * @phy_id: the phy id which we wanted to start up.
4197 */
4198static int
4199pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4200{
4201 struct phy_start_req payload;
4202 struct inbound_queue_table *circularQ;
72d0baa0 4203 int ret;
dbf9bfe6 4204 u32 tag = 0x01;
4205 u32 opcode = OPC_INB_PHYSTART;
4206 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4207 memset(&payload, 0, sizeof(payload));
4208 payload.tag = cpu_to_le32(tag);
4209 /*
4210 ** [0:7] PHY Identifier
4211 ** [8:11] link rate 1.5G, 3G, 6G
4212 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4213 ** [14] 0b disable spin up hold; 1b enable spin up hold
4214 */
4215 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4216 LINKMODE_AUTO | LINKRATE_15 |
4217 LINKRATE_30 | LINKRATE_60 | phy_id);
4218 payload.sas_identify.dev_type = SAS_END_DEV;
4219 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4220 memcpy(payload.sas_identify.sas_addr,
4221 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4222 payload.sas_identify.phy_id = phy_id;
f74cf271 4223 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
72d0baa0 4224 return ret;
dbf9bfe6 4225}
4226
4227/**
4228 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4229 * @pm8001_ha: our hba card information.
4230 * @num: the inbound queue number
4231 * @phy_id: the phy id which we wanted to start up.
4232 */
f74cf271 4233int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
dbf9bfe6 4234 u8 phy_id)
4235{
4236 struct phy_stop_req payload;
4237 struct inbound_queue_table *circularQ;
72d0baa0 4238 int ret;
dbf9bfe6 4239 u32 tag = 0x01;
4240 u32 opcode = OPC_INB_PHYSTOP;
4241 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4242 memset(&payload, 0, sizeof(payload));
4243 payload.tag = cpu_to_le32(tag);
4244 payload.phy_id = cpu_to_le32(phy_id);
f74cf271 4245 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
72d0baa0 4246 return ret;
dbf9bfe6 4247}
4248
4249/**
f74cf271 4250 * see comments on pm8001_mpi_reg_resp.
dbf9bfe6 4251 */
4252static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4253 struct pm8001_device *pm8001_dev, u32 flag)
4254{
4255 struct reg_dev_req payload;
4256 u32 opc;
4257 u32 stp_sspsmp_sata = 0x4;
4258 struct inbound_queue_table *circularQ;
4259 u32 linkrate, phy_id;
72d0baa0 4260 int rc, tag = 0xdeadbeef;
dbf9bfe6 4261 struct pm8001_ccb_info *ccb;
4262 u8 retryFlag = 0x1;
4263 u16 firstBurstSize = 0;
4264 u16 ITNT = 2000;
4265 struct domain_device *dev = pm8001_dev->sas_device;
4266 struct domain_device *parent_dev = dev->parent;
4267 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4268
4269 memset(&payload, 0, sizeof(payload));
4270 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4271 if (rc)
4272 return rc;
4273 ccb = &pm8001_ha->ccb_info[tag];
4274 ccb->device = pm8001_dev;
4275 ccb->ccb_tag = tag;
4276 payload.tag = cpu_to_le32(tag);
4277 if (flag == 1)
4278 stp_sspsmp_sata = 0x02; /*direct attached sata */
4279 else {
4280 if (pm8001_dev->dev_type == SATA_DEV)
4281 stp_sspsmp_sata = 0x00; /* stp*/
4282 else if (pm8001_dev->dev_type == SAS_END_DEV ||
4283 pm8001_dev->dev_type == EDGE_DEV ||
4284 pm8001_dev->dev_type == FANOUT_DEV)
4285 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4286 }
4287 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4288 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4289 else
4290 phy_id = pm8001_dev->attached_phy;
4291 opc = OPC_INB_REG_DEV;
4292 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4293 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4294 payload.phyid_portid =
4295 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4296 ((phy_id & 0x0F) << 4));
4297 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4298 ((linkrate & 0x0F) * 0x1000000) |
4299 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4300 payload.firstburstsize_ITNexustimeout =
4301 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
afc5ca9d 4302 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
dbf9bfe6 4303 SAS_ADDR_SIZE);
f74cf271 4304 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
72d0baa0 4305 return rc;
dbf9bfe6 4306}
4307
4308/**
f74cf271 4309 * see comments on pm8001_mpi_reg_resp.
dbf9bfe6 4310 */
f74cf271 4311int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
dbf9bfe6 4312 u32 device_id)
4313{
4314 struct dereg_dev_req payload;
4315 u32 opc = OPC_INB_DEREG_DEV_HANDLE;
72d0baa0 4316 int ret;
dbf9bfe6 4317 struct inbound_queue_table *circularQ;
4318
4319 circularQ = &pm8001_ha->inbnd_q_tbl[0];
72d0baa0 4320 memset(&payload, 0, sizeof(payload));
8270ee2a 4321 payload.tag = cpu_to_le32(1);
dbf9bfe6 4322 payload.device_id = cpu_to_le32(device_id);
4323 PM8001_MSG_DBG(pm8001_ha,
4324 pm8001_printk("unregister device device_id = %d\n", device_id));
f74cf271 4325 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
72d0baa0 4326 return ret;
dbf9bfe6 4327}
4328
4329/**
4330 * pm8001_chip_phy_ctl_req - support the local phy operation
4331 * @pm8001_ha: our hba card information.
4332 * @num: the inbound queue number
4333 * @phy_id: the phy id which we wanted to operate
4334 * @phy_op:
4335 */
4336static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4337 u32 phyId, u32 phy_op)
4338{
4339 struct local_phy_ctl_req payload;
4340 struct inbound_queue_table *circularQ;
72d0baa0 4341 int ret;
dbf9bfe6 4342 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
83e73329 4343 memset(&payload, 0, sizeof(payload));
dbf9bfe6 4344 circularQ = &pm8001_ha->inbnd_q_tbl[0];
8270ee2a 4345 payload.tag = cpu_to_le32(1);
dbf9bfe6 4346 payload.phyop_phyid =
4347 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
f74cf271 4348 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
72d0baa0 4349 return ret;
dbf9bfe6 4350}
4351
4352static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4353{
4354 u32 value;
4355#ifdef PM8001_USE_MSIX
4356 return 1;
4357#endif
4358 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4359 if (value)
4360 return 1;
4361 return 0;
4362
4363}
4364
4365/**
4366 * pm8001_chip_isr - PM8001 isr handler.
4367 * @pm8001_ha: our hba card information.
4368 * @irq: irq number.
4369 * @stat: stat.
4370 */
72d0baa0 4371static irqreturn_t
f74cf271 4372pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
dbf9bfe6 4373{
f74cf271
S		 4374 pm8001_chip_interrupt_disable(pm8001_ha, vec);
4375 process_oq(pm8001_ha, vec);
4376 pm8001_chip_interrupt_enable(pm8001_ha, vec);
72d0baa0 4377 return IRQ_HANDLED;
dbf9bfe6 4378}
4379
4380static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4381 u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4382{
4383 struct task_abort_req task_abort;
4384 struct inbound_queue_table *circularQ;
72d0baa0 4385 int ret;
dbf9bfe6 4386 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4387 memset(&task_abort, 0, sizeof(task_abort));
4388 if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4389 task_abort.abort_all = 0;
4390 task_abort.device_id = cpu_to_le32(dev_id);
4391 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4392 task_abort.tag = cpu_to_le32(cmd_tag);
4393 } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4394 task_abort.abort_all = cpu_to_le32(1);
4395 task_abort.device_id = cpu_to_le32(dev_id);
4396 task_abort.tag = cpu_to_le32(cmd_tag);
4397 }
f74cf271 4398 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
72d0baa0 4399 return ret;
dbf9bfe6 4400}
4401
4402/**
4403 * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4404 * @task: the task we wanted to aborted.
4405 * @flag: the abort flag.
4406 */
f74cf271 4407int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
dbf9bfe6 4408 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4409{
4410 u32 opc, device_id;
4411 int rc = TMF_RESP_FUNC_FAILED;
72d0baa0 4412 PM8001_EH_DBG(pm8001_ha, pm8001_printk("cmd_tag = %x, abort task tag"
4413 " = %x", cmd_tag, task_tag));
dbf9bfe6 4414 if (pm8001_dev->dev_type == SAS_END_DEV)
4415 opc = OPC_INB_SSP_ABORT;
4416 else if (pm8001_dev->dev_type == SATA_DEV)
4417 opc = OPC_INB_SATA_ABORT;
4418 else
4419 opc = OPC_INB_SMP_ABORT;/* SMP */
4420 device_id = pm8001_dev->device_id;
4421 rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4422 task_tag, cmd_tag);
4423 if (rc != TMF_RESP_FUNC_COMPLETE)
72d0baa0 4424 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
dbf9bfe6 4425 return rc;
4426}
4427
4428/**
65155b37 4429 * pm8001_chip_ssp_tm_req - built the task management command.
dbf9bfe6 4430 * @pm8001_ha: our hba card information.
4431 * @ccb: the ccb information.
4432 * @tmf: task management function.
4433 */
f74cf271 4434int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
dbf9bfe6 4435 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4436{
4437 struct sas_task *task = ccb->task;
4438 struct domain_device *dev = task->dev;
4439 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4440 u32 opc = OPC_INB_SSPINITMSTART;
4441 struct inbound_queue_table *circularQ;
4442 struct ssp_ini_tm_start_req sspTMCmd;
72d0baa0 4443 int ret;
dbf9bfe6 4444
4445 memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4446 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4447 sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4448 sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
dbf9bfe6 4449 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4450 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4451 circularQ = &pm8001_ha->inbnd_q_tbl[0];
f74cf271 4452 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd, 0);
72d0baa0 4453 return ret;
dbf9bfe6 4454}
4455
f74cf271 4456int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
dbf9bfe6 4457 void *payload)
4458{
4459 u32 opc = OPC_INB_GET_NVMD_DATA;
4460 u32 nvmd_type;
72d0baa0 4461 int rc;
dbf9bfe6 4462 u32 tag;
4463 struct pm8001_ccb_info *ccb;
4464 struct inbound_queue_table *circularQ;
4465 struct get_nvm_data_req nvmd_req;
4466 struct fw_control_ex *fw_control_context;
4467 struct pm8001_ioctl_payload *ioctl_payload = payload;
4468
4469 nvmd_type = ioctl_payload->minor_function;
4470 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
0caeb91c
DC		 4471 if (!fw_control_context)
4472 return -ENOMEM;
1c75a679 4473 fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific;
dbf9bfe6 4474 fw_control_context->len = ioctl_payload->length;
4475 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4476 memset(&nvmd_req, 0, sizeof(nvmd_req));
4477 rc = pm8001_tag_alloc(pm8001_ha, &tag);
823d219f
JL		 4478 if (rc) {
4479 kfree(fw_control_context);
dbf9bfe6 4480 return rc;
823d219f 4481 }
dbf9bfe6 4482 ccb = &pm8001_ha->ccb_info[tag];
4483 ccb->ccb_tag = tag;
4484 ccb->fw_control_context = fw_control_context;
4485 nvmd_req.tag = cpu_to_le32(tag);
4486
4487 switch (nvmd_type) {
4488 case TWI_DEVICE: {
4489 u32 twi_addr, twi_page_size;
4490 twi_addr = 0xa8;
4491 twi_page_size = 2;
4492
4493 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4494 twi_page_size << 8 | TWI_DEVICE);
4495 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4496 nvmd_req.resp_addr_hi =
4497 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4498 nvmd_req.resp_addr_lo =
4499 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4500 break;
4501 }
4502 case C_SEEPROM: {
4503 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4504 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4505 nvmd_req.resp_addr_hi =
4506 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4507 nvmd_req.resp_addr_lo =
4508 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4509 break;
4510 }
4511 case VPD_FLASH: {
4512 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4513 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4514 nvmd_req.resp_addr_hi =
4515 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4516 nvmd_req.resp_addr_lo =
4517 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4518 break;
4519 }
4520 case EXPAN_ROM: {
4521 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4522 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4523 nvmd_req.resp_addr_hi =
4524 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4525 nvmd_req.resp_addr_lo =
4526 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4527 break;
4528 }
4529 default:
4530 break;
4531 }
f74cf271 4532 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0);
72d0baa0 4533 return rc;
dbf9bfe6 4534}
4535
f74cf271 4536int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
dbf9bfe6 4537 void *payload)
4538{
4539 u32 opc = OPC_INB_SET_NVMD_DATA;
4540 u32 nvmd_type;
72d0baa0 4541 int rc;
dbf9bfe6 4542 u32 tag;
4543 struct pm8001_ccb_info *ccb;
4544 struct inbound_queue_table *circularQ;
4545 struct set_nvm_data_req nvmd_req;
4546 struct fw_control_ex *fw_control_context;
4547 struct pm8001_ioctl_payload *ioctl_payload = payload;
4548
4549 nvmd_type = ioctl_payload->minor_function;
4550 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
0caeb91c
DC		 4551 if (!fw_control_context)
4552 return -ENOMEM;
dbf9bfe6 4553 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4554 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
1c75a679 4555 &ioctl_payload->func_specific,
dbf9bfe6 4556 ioctl_payload->length);
4557 memset(&nvmd_req, 0, sizeof(nvmd_req));
4558 rc = pm8001_tag_alloc(pm8001_ha, &tag);
823d219f
JL		 4559 if (rc) {
4560 kfree(fw_control_context);
dbf9bfe6 4561 return rc;
823d219f 4562 }
dbf9bfe6 4563 ccb = &pm8001_ha->ccb_info[tag];
4564 ccb->fw_control_context = fw_control_context;
4565 ccb->ccb_tag = tag;
4566 nvmd_req.tag = cpu_to_le32(tag);
4567 switch (nvmd_type) {
4568 case TWI_DEVICE: {
4569 u32 twi_addr, twi_page_size;
4570 twi_addr = 0xa8;
4571 twi_page_size = 2;
4572 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4573 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4574 twi_page_size << 8 | TWI_DEVICE);
4575 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4576 nvmd_req.resp_addr_hi =
4577 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4578 nvmd_req.resp_addr_lo =
4579 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4580 break;
4581 }
4582 case C_SEEPROM:
4583 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4584 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4585 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4586 nvmd_req.resp_addr_hi =
4587 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4588 nvmd_req.resp_addr_lo =
4589 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4590 break;
4591 case VPD_FLASH:
4592 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4593 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4594 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4595 nvmd_req.resp_addr_hi =
4596 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4597 nvmd_req.resp_addr_lo =
4598 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4599 break;
4600 case EXPAN_ROM:
4601 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4602 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4603 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4604 nvmd_req.resp_addr_hi =
4605 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4606 nvmd_req.resp_addr_lo =
4607 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4608 break;
4609 default:
4610 break;
4611 }
f74cf271 4612 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0);
72d0baa0 4613 return rc;
dbf9bfe6 4614}
4615
4616/**
4617 * pm8001_chip_fw_flash_update_build - support the firmware update operation
4618 * @pm8001_ha: our hba card information.
4619 * @fw_flash_updata_info: firmware flash update param
4620 */
f74cf271 4621int
dbf9bfe6 4622pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4623 void *fw_flash_updata_info, u32 tag)
4624{
4625 struct fw_flash_Update_req payload;
4626 struct fw_flash_updata_info *info;
4627 struct inbound_queue_table *circularQ;
72d0baa0 4628 int ret;
dbf9bfe6 4629 u32 opc = OPC_INB_FW_FLASH_UPDATE;
4630
72d0baa0 4631 memset(&payload, 0, sizeof(struct fw_flash_Update_req));
dbf9bfe6 4632 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4633 info = fw_flash_updata_info;
4634 payload.tag = cpu_to_le32(tag);
4635 payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4636 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4637 payload.total_image_len = cpu_to_le32(info->total_image_len);
4638 payload.len = info->sgl.im_len.len ;
8270ee2a
SN		 4639 payload.sgl_addr_lo =
4640 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4641 payload.sgl_addr_hi =
4642 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
f74cf271 4643 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
72d0baa0 4644 return ret;
dbf9bfe6 4645}
4646
f74cf271 4647int
dbf9bfe6 4648pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4649 void *payload)
4650{
4651 struct fw_flash_updata_info flash_update_info;
4652 struct fw_control_info *fw_control;
4653 struct fw_control_ex *fw_control_context;
72d0baa0 4654 int rc;
dbf9bfe6 4655 u32 tag;
4656 struct pm8001_ccb_info *ccb;
1c75a679
S		 4657 void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr;
4658 dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr;
dbf9bfe6 4659 struct pm8001_ioctl_payload *ioctl_payload = payload;
4660
4661 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
0caeb91c
DC		 4662 if (!fw_control_context)
4663 return -ENOMEM;
1c75a679 4664 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific;
72d0baa0 4665 memcpy(buffer, fw_control->buffer, fw_control->len);
dbf9bfe6 4666 flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4667 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4668 flash_update_info.sgl.im_len.e = 0;
4669 flash_update_info.cur_image_offset = fw_control->offset;
4670 flash_update_info.cur_image_len = fw_control->len;
4671 flash_update_info.total_image_len = fw_control->size;
4672 fw_control_context->fw_control = fw_control;
4673 fw_control_context->virtAddr = buffer;
1c75a679 4674 fw_control_context->phys_addr = phys_addr;
dbf9bfe6 4675 fw_control_context->len = fw_control->len;
4676 rc = pm8001_tag_alloc(pm8001_ha, &tag);
823d219f
JL		 4677 if (rc) {
4678 kfree(fw_control_context);
dbf9bfe6 4679 return rc;
823d219f 4680 }
dbf9bfe6 4681 ccb = &pm8001_ha->ccb_info[tag];
4682 ccb->fw_control_context = fw_control_context;
4683 ccb->ccb_tag = tag;
72d0baa0 4684 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4685 tag);
4686 return rc;
dbf9bfe6 4687}
4688
f74cf271 4689int
dbf9bfe6 4690pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4691 struct pm8001_device *pm8001_dev, u32 state)
4692{
4693 struct set_dev_state_req payload;
4694 struct inbound_queue_table *circularQ;
4695 struct pm8001_ccb_info *ccb;
72d0baa0 4696 int rc;
dbf9bfe6 4697 u32 tag;
4698 u32 opc = OPC_INB_SET_DEVICE_STATE;
72d0baa0 4699 memset(&payload, 0, sizeof(payload));
dbf9bfe6 4700 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4701 if (rc)
4702 return -1;
4703 ccb = &pm8001_ha->ccb_info[tag];
4704 ccb->ccb_tag = tag;
4705 ccb->device = pm8001_dev;
4706 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4707 payload.tag = cpu_to_le32(tag);
4708 payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4709 payload.nds = cpu_to_le32(state);
f74cf271 4710 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
72d0baa0 4711 return rc;
4712
d0b68041 4713}
4714
4715static int
4716pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4717{
4718 struct sas_re_initialization_req payload;
4719 struct inbound_queue_table *circularQ;
4720 struct pm8001_ccb_info *ccb;
4721 int rc;
4722 u32 tag;
4723 u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4724 memset(&payload, 0, sizeof(payload));
4725 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4726 if (rc)
4727 return -1;
4728 ccb = &pm8001_ha->ccb_info[tag];
4729 ccb->ccb_tag = tag;
4730 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4731 payload.tag = cpu_to_le32(tag);
4732 payload.SSAHOLT = cpu_to_le32(0xd << 25);
4733 payload.sata_hol_tmo = cpu_to_le32(80);
4734 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
f74cf271 4735 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
d0b68041 4736 return rc;
dbf9bfe6 4737
4738}
4739
4740const struct pm8001_dispatch pm8001_8001_dispatch = {
4741 .name = "pmc8001",
4742 .chip_init = pm8001_chip_init,
4743 .chip_soft_rst = pm8001_chip_soft_rst,
4744 .chip_rst = pm8001_hw_chip_rst,
4745 .chip_iounmap = pm8001_chip_iounmap,
4746 .isr = pm8001_chip_isr,
4747 .is_our_interupt = pm8001_chip_is_our_interupt,
4748 .isr_process_oq = process_oq,
4749 .interrupt_enable = pm8001_chip_interrupt_enable,
4750 .interrupt_disable = pm8001_chip_interrupt_disable,
4751 .make_prd = pm8001_chip_make_sg,
4752 .smp_req = pm8001_chip_smp_req,
4753 .ssp_io_req = pm8001_chip_ssp_io_req,
4754 .sata_req = pm8001_chip_sata_req,
4755 .phy_start_req = pm8001_chip_phy_start_req,
4756 .phy_stop_req = pm8001_chip_phy_stop_req,
4757 .reg_dev_req = pm8001_chip_reg_dev_req,
4758 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4759 .phy_ctl_req = pm8001_chip_phy_ctl_req,
4760 .task_abort = pm8001_chip_abort_task,
4761 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4762 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4763 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4764 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4765 .set_dev_state_req = pm8001_chip_set_dev_state_req,
d0b68041 4766 .sas_re_init_req = pm8001_chip_sas_re_initialization,
dbf9bfe6 4767};
Linux 6.x block layer and io_uring tree(s)