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Merge tag 's390-5.3-4' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux
[linux-2.6-block.git] / drivers / scsi / ncr53c8xx.c
CommitLineData
74ba9207 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/******************************************************************************
3** Device driver for the PCI-SCSI NCR538XX controller family.
4**
5** Copyright (C) 1994 Wolfgang Stanglmeier
6**
1da177e4
LT		 7**
8**-----------------------------------------------------------------------------
9**
10** This driver has been ported to Linux from the FreeBSD NCR53C8XX driver
11** and is currently maintained by
12**
13** Gerard Roudier <groudier@free.fr>
14**
15** Being given that this driver originates from the FreeBSD version, and
16** in order to keep synergy on both, any suggested enhancements and corrections
17** received on Linux are automatically a potential candidate for the FreeBSD
18** version.
19**
20** The original driver has been written for 386bsd and FreeBSD by
21** Wolfgang Stanglmeier <wolf@cologne.de>
22** Stefan Esser <se@mi.Uni-Koeln.de>
23**
24** And has been ported to NetBSD by
25** Charles M. Hannum <mycroft@gnu.ai.mit.edu>
26**
27**-----------------------------------------------------------------------------
28**
29** Brief history
30**
31** December 10 1995 by Gerard Roudier:
32** Initial port to Linux.
33**
34** June 23 1996 by Gerard Roudier:
35** Support for 64 bits architectures (Alpha).
36**
37** November 30 1996 by Gerard Roudier:
38** Support for Fast-20 scsi.
39** Support for large DMA fifo and 128 dwords bursting.
40**
41** February 27 1997 by Gerard Roudier:
42** Support for Fast-40 scsi.
43** Support for on-Board RAM.
44**
45** May 3 1997 by Gerard Roudier:
46** Full support for scsi scripts instructions pre-fetching.
47**
48** May 19 1997 by Richard Waltham <dormouse@farsrobt.demon.co.uk>:
49** Support for NvRAM detection and reading.
50**
51** August 18 1997 by Cort <cort@cs.nmt.edu>:
52** Support for Power/PC (Big Endian).
53**
54** June 20 1998 by Gerard Roudier
55** Support for up to 64 tags per lun.
56** O(1) everywhere (C and SCRIPTS) for normal cases.
57** Low PCI traffic for command handling when on-chip RAM is present.
58** Aggressive SCSI SCRIPTS optimizations.
59**
b0dc1db1
MW		 60** 2005 by Matthew Wilcox and James Bottomley
61** PCI-ectomy. This driver now supports only the 720 chip (see the
62** NCR_Q720 and zalon drivers for the bus probe logic).
63**
1da177e4
LT		 64*******************************************************************************
65*/
66
67/*
68** Supported SCSI-II features:
69** Synchronous negotiation
70** Wide negotiation (depends on the NCR Chip)
71** Enable disconnection
72** Tagged command queuing
73** Parity checking
74** Etc...
75**
76** Supported NCR/SYMBIOS chips:
77** 53C720 (Wide, Fast SCSI-2, intfly problems)
78*/
79
80/* Name and version of the driver */
81#define SCSI_NCR_DRIVER_NAME "ncr53c8xx-3.4.3g"
82
83#define SCSI_NCR_DEBUG_FLAGS (0)
84
1da177e4
LT		 85#include <linux/blkdev.h>
86#include <linux/delay.h>
87#include <linux/dma-mapping.h>
88#include <linux/errno.h>
5a0e3ad6 89#include <linux/gfp.h>
1da177e4
LT		 90#include <linux/init.h>
91#include <linux/interrupt.h>
92#include <linux/ioport.h>
93#include <linux/mm.h>
94#include <linux/module.h>
95#include <linux/sched.h>
96#include <linux/signal.h>
97#include <linux/spinlock.h>
98#include <linux/stat.h>
99#include <linux/string.h>
100#include <linux/time.h>
101#include <linux/timer.h>
102#include <linux/types.h>
103
104#include <asm/dma.h>
105#include <asm/io.h>
1da177e4
LT		 106
107#include <scsi/scsi.h>
108#include <scsi/scsi_cmnd.h>
b0dc1db1 109#include <scsi/scsi_dbg.h>
1da177e4
LT		 110#include <scsi/scsi_device.h>
111#include <scsi/scsi_tcq.h>
112#include <scsi/scsi_transport.h>
113#include <scsi/scsi_transport_spi.h>
114
115#include "ncr53c8xx.h"
116
1da177e4
LT		 117#define NAME53C8XX "ncr53c8xx"
118
19c65091
MW		 119/*==========================================================
120**
121** Debugging tags
122**
123**==========================================================
124*/
125
126#define DEBUG_ALLOC (0x0001)
127#define DEBUG_PHASE (0x0002)
128#define DEBUG_QUEUE (0x0008)
129#define DEBUG_RESULT (0x0010)
130#define DEBUG_POINTER (0x0020)
131#define DEBUG_SCRIPT (0x0040)
132#define DEBUG_TINY (0x0080)
133#define DEBUG_TIMING (0x0100)
134#define DEBUG_NEGO (0x0200)
135#define DEBUG_TAGS (0x0400)
136#define DEBUG_SCATTER (0x0800)
137#define DEBUG_IC (0x1000)
138
139/*
140** Enable/Disable debug messages.
141** Can be changed at runtime too.
142*/
143
144#ifdef SCSI_NCR_DEBUG_INFO_SUPPORT
145static int ncr_debug = SCSI_NCR_DEBUG_FLAGS;
146 #define DEBUG_FLAGS ncr_debug
147#else
148 #define DEBUG_FLAGS SCSI_NCR_DEBUG_FLAGS
149#endif
150
151static inline struct list_head *ncr_list_pop(struct list_head *head)
152{
153 if (!list_empty(head)) {
154 struct list_head *elem = head->next;
155
156 list_del(elem);
157 return elem;
158 }
159
160 return NULL;
161}
162
163/*==========================================================
164**
165** Simple power of two buddy-like allocator.
166**
167** This simple code is not intended to be fast, but to
168** provide power of 2 aligned memory allocations.
169** Since the SCRIPTS processor only supplies 8 bit
170** arithmetic, this allocator allows simple and fast
171** address calculations from the SCRIPTS code.
172** In addition, cache line alignment is guaranteed for
173** power of 2 cache line size.
174** Enhanced in linux-2.3.44 to provide a memory pool
175** per pcidev to support dynamic dma mapping. (I would
0779bf2d 176** have preferred a real bus abstraction, btw).
19c65091
MW		 177**
178**==========================================================
179*/
180
181#define MEMO_SHIFT 4 /* 16 bytes minimum memory chunk */
182#if PAGE_SIZE >= 8192
183#define MEMO_PAGE_ORDER 0 /* 1 PAGE maximum */
184#else
185#define MEMO_PAGE_ORDER 1 /* 2 PAGES maximum */
186#endif
187#define MEMO_FREE_UNUSED /* Free unused pages immediately */
188#define MEMO_WARN 1
189#define MEMO_GFP_FLAGS GFP_ATOMIC
190#define MEMO_CLUSTER_SHIFT (PAGE_SHIFT+MEMO_PAGE_ORDER)
191#define MEMO_CLUSTER_SIZE (1UL << MEMO_CLUSTER_SHIFT)
192#define MEMO_CLUSTER_MASK (MEMO_CLUSTER_SIZE-1)
193
194typedef u_long m_addr_t; /* Enough bits to bit-hack addresses */
195typedef struct device *m_bush_t; /* Something that addresses DMAable */
196
197typedef struct m_link { /* Link between free memory chunks */
198 struct m_link *next;
199} m_link_s;
200
201typedef struct m_vtob { /* Virtual to Bus address translation */
202 struct m_vtob *next;
203 m_addr_t vaddr;
204 m_addr_t baddr;
205} m_vtob_s;
206#define VTOB_HASH_SHIFT 5
207#define VTOB_HASH_SIZE (1UL << VTOB_HASH_SHIFT)
208#define VTOB_HASH_MASK (VTOB_HASH_SIZE-1)
209#define VTOB_HASH_CODE(m) \
210 ((((m_addr_t) (m)) >> MEMO_CLUSTER_SHIFT) & VTOB_HASH_MASK)
211
212typedef struct m_pool { /* Memory pool of a given kind */
213 m_bush_t bush;
214 m_addr_t (*getp)(struct m_pool *);
215 void (*freep)(struct m_pool *, m_addr_t);
216 int nump;
217 m_vtob_s *(vtob[VTOB_HASH_SIZE]);
218 struct m_pool *next;
219 struct m_link h[PAGE_SHIFT-MEMO_SHIFT+MEMO_PAGE_ORDER+1];
220} m_pool_s;
221
222static void *___m_alloc(m_pool_s *mp, int size)
223{
224 int i = 0;
225 int s = (1 << MEMO_SHIFT);
226 int j;
227 m_addr_t a;
228 m_link_s *h = mp->h;
229
230 if (size > (PAGE_SIZE << MEMO_PAGE_ORDER))
231 return NULL;
232
233 while (size > s) {
234 s <<= 1;
235 ++i;
236 }
237
238 j = i;
239 while (!h[j].next) {
240 if (s == (PAGE_SIZE << MEMO_PAGE_ORDER)) {
241 h[j].next = (m_link_s *)mp->getp(mp);
242 if (h[j].next)
243 h[j].next->next = NULL;
244 break;
245 }
246 ++j;
247 s <<= 1;
248 }
249 a = (m_addr_t) h[j].next;
250 if (a) {
251 h[j].next = h[j].next->next;
252 while (j > i) {
253 j -= 1;
254 s >>= 1;
255 h[j].next = (m_link_s *) (a+s);
256 h[j].next->next = NULL;
257 }
258 }
259#ifdef DEBUG
260 printk("___m_alloc(%d) = %p\n", size, (void *) a);
261#endif
262 return (void *) a;
263}
264
265static void ___m_free(m_pool_s *mp, void *ptr, int size)
266{
267 int i = 0;
268 int s = (1 << MEMO_SHIFT);
269 m_link_s *q;
270 m_addr_t a, b;
271 m_link_s *h = mp->h;
272
273#ifdef DEBUG
274 printk("___m_free(%p, %d)\n", ptr, size);
275#endif
276
277 if (size > (PAGE_SIZE << MEMO_PAGE_ORDER))
278 return;
279
280 while (size > s) {
281 s <<= 1;
282 ++i;
283 }
284
285 a = (m_addr_t) ptr;
286
287 while (1) {
288#ifdef MEMO_FREE_UNUSED
289 if (s == (PAGE_SIZE << MEMO_PAGE_ORDER)) {
290 mp->freep(mp, a);
291 break;
292 }
293#endif
294 b = a ^ s;
295 q = &h[i];
296 while (q->next && q->next != (m_link_s *) b) {
297 q = q->next;
298 }
299 if (!q->next) {
300 ((m_link_s *) a)->next = h[i].next;
301 h[i].next = (m_link_s *) a;
302 break;
303 }
304 q->next = q->next->next;
305 a = a & b;
306 s <<= 1;
307 ++i;
308 }
309}
310
311static DEFINE_SPINLOCK(ncr53c8xx_lock);
312
313static void *__m_calloc2(m_pool_s *mp, int size, char *name, int uflags)
314{
315 void *p;
316
317 p = ___m_alloc(mp, size);
318
319 if (DEBUG_FLAGS & DEBUG_ALLOC)
320 printk ("new %-10s[%4d] @%p.\n", name, size, p);
321
322 if (p)
323 memset(p, 0, size);
324 else if (uflags & MEMO_WARN)
325 printk (NAME53C8XX ": failed to allocate %s[%d]\n", name, size);
326
327 return p;
328}
329
330#define __m_calloc(mp, s, n) __m_calloc2(mp, s, n, MEMO_WARN)
331
332static void __m_free(m_pool_s *mp, void *ptr, int size, char *name)
333{
334 if (DEBUG_FLAGS & DEBUG_ALLOC)
335 printk ("freeing %-10s[%4d] @%p.\n", name, size, ptr);
336
337 ___m_free(mp, ptr, size);
338
339}
340
341/*
342 * With pci bus iommu support, we use a default pool of unmapped memory
343 * for memory we donnot need to DMA from/to and one pool per pcidev for
344 * memory accessed by the PCI chip. `mp0' is the default not DMAable pool.
345 */
346
347static m_addr_t ___mp0_getp(m_pool_s *mp)
348{
349 m_addr_t m = __get_free_pages(MEMO_GFP_FLAGS, MEMO_PAGE_ORDER);
350 if (m)
351 ++mp->nump;
352 return m;
353}
354
355static void ___mp0_freep(m_pool_s *mp, m_addr_t m)
356{
357 free_pages(m, MEMO_PAGE_ORDER);
358 --mp->nump;
359}
360
361static m_pool_s mp0 = {NULL, ___mp0_getp, ___mp0_freep};
362
363/*
364 * DMAable pools.
365 */
366
367/*
368 * With pci bus iommu support, we maintain one pool per pcidev and a
369 * hashed reverse table for virtual to bus physical address translations.
370 */
371static m_addr_t ___dma_getp(m_pool_s *mp)
372{
373 m_addr_t vp;
374 m_vtob_s *vbp;
375
376 vbp = __m_calloc(&mp0, sizeof(*vbp), "VTOB");
377 if (vbp) {
378 dma_addr_t daddr;
379 vp = (m_addr_t) dma_alloc_coherent(mp->bush,
380 PAGE_SIZE<<MEMO_PAGE_ORDER,
381 &daddr, GFP_ATOMIC);
382 if (vp) {
383 int hc = VTOB_HASH_CODE(vp);
384 vbp->vaddr = vp;
385 vbp->baddr = daddr;
386 vbp->next = mp->vtob[hc];
387 mp->vtob[hc] = vbp;
388 ++mp->nump;
389 return vp;
390 }
391 }
392 if (vbp)
393 __m_free(&mp0, vbp, sizeof(*vbp), "VTOB");
394 return 0;
395}
396
397static void ___dma_freep(m_pool_s *mp, m_addr_t m)
398{
399 m_vtob_s **vbpp, *vbp;
400 int hc = VTOB_HASH_CODE(m);
401
402 vbpp = &mp->vtob[hc];
403 while (*vbpp && (*vbpp)->vaddr != m)
404 vbpp = &(*vbpp)->next;
405 if (*vbpp) {
406 vbp = *vbpp;
407 *vbpp = (*vbpp)->next;
408 dma_free_coherent(mp->bush, PAGE_SIZE<<MEMO_PAGE_ORDER,
409 (void *)vbp->vaddr, (dma_addr_t)vbp->baddr);
410 __m_free(&mp0, vbp, sizeof(*vbp), "VTOB");
411 --mp->nump;
412 }
413}
414
415static inline m_pool_s *___get_dma_pool(m_bush_t bush)
416{
417 m_pool_s *mp;
418 for (mp = mp0.next; mp && mp->bush != bush; mp = mp->next);
419 return mp;
420}
421
422static m_pool_s *___cre_dma_pool(m_bush_t bush)
423{
424 m_pool_s *mp;
425 mp = __m_calloc(&mp0, sizeof(*mp), "MPOOL");
426 if (mp) {
427 memset(mp, 0, sizeof(*mp));
428 mp->bush = bush;
429 mp->getp = ___dma_getp;
430 mp->freep = ___dma_freep;
431 mp->next = mp0.next;
432 mp0.next = mp;
433 }
434 return mp;
435}
436
437static void ___del_dma_pool(m_pool_s *p)
438{
439 struct m_pool **pp = &mp0.next;
440
441 while (*pp && *pp != p)
442 pp = &(*pp)->next;
443 if (*pp) {
444 *pp = (*pp)->next;
445 __m_free(&mp0, p, sizeof(*p), "MPOOL");
446 }
447}
448
449static void *__m_calloc_dma(m_bush_t bush, int size, char *name)
450{
451 u_long flags;
452 struct m_pool *mp;
453 void *m = NULL;
454
455 spin_lock_irqsave(&ncr53c8xx_lock, flags);
456 mp = ___get_dma_pool(bush);
457 if (!mp)
458 mp = ___cre_dma_pool(bush);
459 if (mp)
460 m = __m_calloc(mp, size, name);
461 if (mp && !mp->nump)
462 ___del_dma_pool(mp);
463 spin_unlock_irqrestore(&ncr53c8xx_lock, flags);
464
465 return m;
466}
467
468static void __m_free_dma(m_bush_t bush, void *m, int size, char *name)
469{
470 u_long flags;
471 struct m_pool *mp;
472
473 spin_lock_irqsave(&ncr53c8xx_lock, flags);
474 mp = ___get_dma_pool(bush);
475 if (mp)
476 __m_free(mp, m, size, name);
477 if (mp && !mp->nump)
478 ___del_dma_pool(mp);
479 spin_unlock_irqrestore(&ncr53c8xx_lock, flags);
480}
481
482static m_addr_t __vtobus(m_bush_t bush, void *m)
483{
484 u_long flags;
485 m_pool_s *mp;
486 int hc = VTOB_HASH_CODE(m);
487 m_vtob_s *vp = NULL;
488 m_addr_t a = ((m_addr_t) m) & ~MEMO_CLUSTER_MASK;
489
490 spin_lock_irqsave(&ncr53c8xx_lock, flags);
491 mp = ___get_dma_pool(bush);
492 if (mp) {
493 vp = mp->vtob[hc];
494 while (vp && (m_addr_t) vp->vaddr != a)
495 vp = vp->next;
496 }
497 spin_unlock_irqrestore(&ncr53c8xx_lock, flags);
498 return vp ? vp->baddr + (((m_addr_t) m) - a) : 0;
499}
500
501#define _m_calloc_dma(np, s, n) __m_calloc_dma(np->dev, s, n)
502#define _m_free_dma(np, p, s, n) __m_free_dma(np->dev, p, s, n)
503#define m_calloc_dma(s, n) _m_calloc_dma(np, s, n)
504#define m_free_dma(p, s, n) _m_free_dma(np, p, s, n)
505#define _vtobus(np, p) __vtobus(np->dev, p)
506#define vtobus(p) _vtobus(np, p)
507
508/*
509 * Deal with DMA mapping/unmapping.
510 */
511
512/* To keep track of the dma mapping (sg/single) that has been set */
513#define __data_mapped SCp.phase
514#define __data_mapping SCp.have_data_in
515
516static void __unmap_scsi_data(struct device *dev, struct scsi_cmnd *cmd)
517{
518 switch(cmd->__data_mapped) {
519 case 2:
69eca4f5 520 scsi_dma_unmap(cmd);
19c65091
MW		 521 break;
522 }
523 cmd->__data_mapped = 0;
524}
525
19c65091
MW		 526static int __map_scsi_sg_data(struct device *dev, struct scsi_cmnd *cmd)
527{
528 int use_sg;
529
69eca4f5
FT		 530 use_sg = scsi_dma_map(cmd);
531 if (!use_sg)
19c65091
MW		 532 return 0;
533
19c65091
MW		 534 cmd->__data_mapped = 2;
535 cmd->__data_mapping = use_sg;
536
537 return use_sg;
538}
539
540#define unmap_scsi_data(np, cmd) __unmap_scsi_data(np->dev, cmd)
19c65091
MW		 541#define map_scsi_sg_data(np, cmd) __map_scsi_sg_data(np->dev, cmd)
542
543/*==========================================================
544**
545** Driver setup.
546**
547** This structure is initialized from linux config
548** options. It can be overridden at boot-up by the boot
549** command line.
550**
551**==========================================================
552*/
553static struct ncr_driver_setup
554 driver_setup = SCSI_NCR_DRIVER_SETUP;
555
db3a8815 556#ifndef MODULE
19c65091
MW		 557#ifdef SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
558static struct ncr_driver_setup
559 driver_safe_setup __initdata = SCSI_NCR_DRIVER_SAFE_SETUP;
560#endif
db3a8815 561#endif /* !MODULE */
19c65091
MW		 562
563#define initverbose (driver_setup.verbose)
564#define bootverbose (np->verbose)
565
566
567/*===================================================================
568**
569** Driver setup from the boot command line
570**
571**===================================================================
572*/
573
574#ifdef MODULE
575#define ARG_SEP ' '
576#else
577#define ARG_SEP ','
578#endif
579
580#define OPT_TAGS 1
581#define OPT_MASTER_PARITY 2
582#define OPT_SCSI_PARITY 3
583#define OPT_DISCONNECTION 4
584#define OPT_SPECIAL_FEATURES 5
585#define OPT_UNUSED_1 6
586#define OPT_FORCE_SYNC_NEGO 7
587#define OPT_REVERSE_PROBE 8
588#define OPT_DEFAULT_SYNC 9
589#define OPT_VERBOSE 10
590#define OPT_DEBUG 11
591#define OPT_BURST_MAX 12
592#define OPT_LED_PIN 13
593#define OPT_MAX_WIDE 14
594#define OPT_SETTLE_DELAY 15
595#define OPT_DIFF_SUPPORT 16
596#define OPT_IRQM 17
597#define OPT_PCI_FIX_UP 18
598#define OPT_BUS_CHECK 19
599#define OPT_OPTIMIZE 20
600#define OPT_RECOVERY 21
601#define OPT_SAFE_SETUP 22
602#define OPT_USE_NVRAM 23
603#define OPT_EXCLUDE 24
604#define OPT_HOST_ID 25
605
606#ifdef SCSI_NCR_IARB_SUPPORT
607#define OPT_IARB 26
608#endif
609
db3a8815
JG		 610#ifdef MODULE
611#define ARG_SEP ' '
612#else
613#define ARG_SEP ','
614#endif
615
616#ifndef MODULE
19c65091
MW		 617static char setup_token[] __initdata =
618 "tags:" "mpar:"
619 "spar:" "disc:"
620 "specf:" "ultra:"
621 "fsn:" "revprob:"
622 "sync:" "verb:"
623 "debug:" "burst:"
624 "led:" "wide:"
625 "settle:" "diff:"
626 "irqm:" "pcifix:"
627 "buschk:" "optim:"
628 "recovery:"
629 "safe:" "nvram:"
630 "excl:" "hostid:"
631#ifdef SCSI_NCR_IARB_SUPPORT
632 "iarb:"
633#endif
634 ; /* DONNOT REMOVE THIS ';' */
635
19c65091
MW		 636static int __init get_setup_token(char *p)
637{
638 char *cur = setup_token;
639 char *pc;
640 int i = 0;
641
642 while (cur != NULL && (pc = strchr(cur, ':')) != NULL) {
643 ++pc;
644 ++i;
645 if (!strncmp(p, cur, pc - cur))
646 return i;
647 cur = pc;
648 }
649 return 0;
650}
651
19c65091
MW		 652static int __init sym53c8xx__setup(char *str)
653{
654#ifdef SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
655 char *cur = str;
656 char *pc, *pv;
657 int i, val, c;
658 int xi = 0;
659
660 while (cur != NULL && (pc = strchr(cur, ':')) != NULL) {
661 char *pe;
662
663 val = 0;
664 pv = pc;
665 c = *++pv;
666
667 if (c == 'n')
668 val = 0;
669 else if (c == 'y')
670 val = 1;
671 else
672 val = (int) simple_strtoul(pv, &pe, 0);
673
674 switch (get_setup_token(cur)) {
675 case OPT_TAGS:
676 driver_setup.default_tags = val;
677 if (pe && *pe == '/') {
678 i = 0;
679 while (*pe && *pe != ARG_SEP &&
680 i < sizeof(driver_setup.tag_ctrl)-1) {
681 driver_setup.tag_ctrl[i++] = *pe++;
682 }
683 driver_setup.tag_ctrl[i] = '\0';
684 }
685 break;
686 case OPT_MASTER_PARITY:
687 driver_setup.master_parity = val;
688 break;
689 case OPT_SCSI_PARITY:
690 driver_setup.scsi_parity = val;
691 break;
692 case OPT_DISCONNECTION:
693 driver_setup.disconnection = val;
694 break;
695 case OPT_SPECIAL_FEATURES:
696 driver_setup.special_features = val;
697 break;
698 case OPT_FORCE_SYNC_NEGO:
699 driver_setup.force_sync_nego = val;
700 break;
701 case OPT_REVERSE_PROBE:
702 driver_setup.reverse_probe = val;
703 break;
704 case OPT_DEFAULT_SYNC:
705 driver_setup.default_sync = val;
706 break;
707 case OPT_VERBOSE:
708 driver_setup.verbose = val;
709 break;
710 case OPT_DEBUG:
711 driver_setup.debug = val;
712 break;
713 case OPT_BURST_MAX:
714 driver_setup.burst_max = val;
715 break;
716 case OPT_LED_PIN:
717 driver_setup.led_pin = val;
718 break;
719 case OPT_MAX_WIDE:
720 driver_setup.max_wide = val? 1:0;
721 break;
722 case OPT_SETTLE_DELAY:
723 driver_setup.settle_delay = val;
724 break;
725 case OPT_DIFF_SUPPORT:
726 driver_setup.diff_support = val;
727 break;
728 case OPT_IRQM:
729 driver_setup.irqm = val;
730 break;
731 case OPT_PCI_FIX_UP:
732 driver_setup.pci_fix_up = val;
733 break;
734 case OPT_BUS_CHECK:
735 driver_setup.bus_check = val;
736 break;
737 case OPT_OPTIMIZE:
738 driver_setup.optimize = val;
739 break;
740 case OPT_RECOVERY:
741 driver_setup.recovery = val;
742 break;
743 case OPT_USE_NVRAM:
744 driver_setup.use_nvram = val;
745 break;
746 case OPT_SAFE_SETUP:
747 memcpy(&driver_setup, &driver_safe_setup,
748 sizeof(driver_setup));
749 break;
750 case OPT_EXCLUDE:
751 if (xi < SCSI_NCR_MAX_EXCLUDES)
752 driver_setup.excludes[xi++] = val;
753 break;
754 case OPT_HOST_ID:
755 driver_setup.host_id = val;
756 break;
757#ifdef SCSI_NCR_IARB_SUPPORT
758 case OPT_IARB:
759 driver_setup.iarb = val;
760 break;
761#endif
762 default:
763 printk("sym53c8xx_setup: unexpected boot option '%.*s' ignored\n", (int)(pc-cur+1), cur);
764 break;
765 }
766
767 if ((cur = strchr(cur, ARG_SEP)) != NULL)
768 ++cur;
769 }
770#endif /* SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT */
771 return 1;
772}
db3a8815 773#endif /* !MODULE */
19c65091
MW		 774
775/*===================================================================
776**
777** Get device queue depth from boot command line.
778**
779**===================================================================
780*/
781#define DEF_DEPTH (driver_setup.default_tags)
782#define ALL_TARGETS -2
783#define NO_TARGET -1
784#define ALL_LUNS -2
785#define NO_LUN -1
786
787static int device_queue_depth(int unit, int target, int lun)
788{
789 int c, h, t, u, v;
790 char *p = driver_setup.tag_ctrl;
791 char *ep;
792
793 h = -1;
794 t = NO_TARGET;
795 u = NO_LUN;
796 while ((c = *p++) != 0) {
797 v = simple_strtoul(p, &ep, 0);
798 switch(c) {
799 case '/':
800 ++h;
801 t = ALL_TARGETS;
802 u = ALL_LUNS;
803 break;
804 case 't':
805 if (t != target)
806 t = (target == v) ? v : NO_TARGET;
807 u = ALL_LUNS;
808 break;
809 case 'u':
810 if (u != lun)
811 u = (lun == v) ? v : NO_LUN;
812 break;
813 case 'q':
814 if (h == unit &&
815 (t == ALL_TARGETS || t == target) &&
816 (u == ALL_LUNS || u == lun))
817 return v;
818 break;
819 case '-':
820 t = ALL_TARGETS;
821 u = ALL_LUNS;
822 break;
823 default:
824 break;
825 }
826 p = ep;
827 }
828 return DEF_DEPTH;
829}
1da177e4
LT		 830
831
832/*==========================================================
833**
834** The CCB done queue uses an array of CCB virtual
835** addresses. Empty entries are flagged using the bogus
836** virtual address 0xffffffff.
837**
838** Since PCI ensures that only aligned DWORDs are accessed
839** atomically, 64 bit little-endian architecture requires
840** to test the high order DWORD of the entry to determine
841** if it is empty or valid.
842**
843** BTW, I will make things differently as soon as I will
844** have a better idea, but this is simple and should work.
845**
846**==========================================================
847*/
848
849#define SCSI_NCR_CCB_DONE_SUPPORT
850#ifdef SCSI_NCR_CCB_DONE_SUPPORT
851
852#define MAX_DONE 24
853#define CCB_DONE_EMPTY 0xffffffffUL
854
855/* All 32 bit architectures */
856#if BITS_PER_LONG == 32
857#define CCB_DONE_VALID(cp) (((u_long) cp) != CCB_DONE_EMPTY)
858
859/* All > 32 bit (64 bit) architectures regardless endian-ness */
860#else
861#define CCB_DONE_VALID(cp) \
862 ((((u_long) cp) & 0xffffffff00000000ul) && \
863 (((u_long) cp) & 0xfffffffful) != CCB_DONE_EMPTY)
864#endif
865
866#endif /* SCSI_NCR_CCB_DONE_SUPPORT */
867
868/*==========================================================
869**
870** Configuration and Debugging
871**
872**==========================================================
873*/
874
875/*
876** SCSI address of this device.
877** The boot routines should have set it.
878** If not, use this.
879*/
880
881#ifndef SCSI_NCR_MYADDR
882#define SCSI_NCR_MYADDR (7)
883#endif
884
885/*
886** The maximum number of tags per logic unit.
887** Used only for disk devices that support tags.
888*/
889
890#ifndef SCSI_NCR_MAX_TAGS
891#define SCSI_NCR_MAX_TAGS (8)
892#endif
893
894/*
895** TAGS are actually limited to 64 tags/lun.
896** We need to deal with power of 2, for alignment constraints.
897*/
898#if SCSI_NCR_MAX_TAGS > 64
899#define MAX_TAGS (64)
900#else
901#define MAX_TAGS SCSI_NCR_MAX_TAGS
902#endif
903
904#define NO_TAG (255)
905
906/*
907** Choose appropriate type for tag bitmap.
908*/
909#if MAX_TAGS > 32
910typedef u64 tagmap_t;
911#else
912typedef u32 tagmap_t;
913#endif
914
915/*
916** Number of targets supported by the driver.
917** n permits target numbers 0..n-1.
918** Default is 16, meaning targets #0..#15.
919** #7 .. is myself.
920*/
921
922#ifdef SCSI_NCR_MAX_TARGET
923#define MAX_TARGET (SCSI_NCR_MAX_TARGET)
924#else
925#define MAX_TARGET (16)
926#endif
927
928/*
929** Number of logic units supported by the driver.
930** n enables logic unit numbers 0..n-1.
931** The common SCSI devices require only
932** one lun, so take 1 as the default.
933*/
934
935#ifdef SCSI_NCR_MAX_LUN
936#define MAX_LUN SCSI_NCR_MAX_LUN
937#else
938#define MAX_LUN (1)
939#endif
940
941/*
942** Asynchronous pre-scaler (ns). Shall be 40
943*/
944
945#ifndef SCSI_NCR_MIN_ASYNC
946#define SCSI_NCR_MIN_ASYNC (40)
947#endif
948
949/*
950** The maximum number of jobs scheduled for starting.
951** There should be one slot per target, and one slot
952** for each tag of each target in use.
953** The calculation below is actually quite silly ...
954*/
955
956#ifdef SCSI_NCR_CAN_QUEUE
957#define MAX_START (SCSI_NCR_CAN_QUEUE + 4)
958#else
959#define MAX_START (MAX_TARGET + 7 * MAX_TAGS)
960#endif
961
962/*
963** We limit the max number of pending IO to 250.
964** since we donnot want to allocate more than 1
965** PAGE for 'scripth'.
966*/
967#if MAX_START > 250
968#undef MAX_START
969#define MAX_START 250
970#endif
971
972/*
973** The maximum number of segments a transfer is split into.
974** We support up to 127 segments for both read and write.
975** The data scripts are broken into 2 sub-scripts.
976** 80 (MAX_SCATTERL) segments are moved from a sub-script
977** in on-chip RAM. This makes data transfers shorter than
978** 80k (assuming 1k fs) as fast as possible.
979*/
980
981#define MAX_SCATTER (SCSI_NCR_MAX_SCATTER)
982
983#if (MAX_SCATTER > 80)
984#define MAX_SCATTERL 80
985#define MAX_SCATTERH (MAX_SCATTER - MAX_SCATTERL)
986#else
987#define MAX_SCATTERL (MAX_SCATTER-1)
988#define MAX_SCATTERH 1
989#endif
990
991/*
992** other
993*/
994
995#define NCR_SNOOP_TIMEOUT (1000000)
996
997/*
998** Other definitions
999*/
1000
1001#define ScsiResult(host_code, scsi_code) (((host_code) << 16) + ((scsi_code) & 0x7f))
1002
1003#define initverbose (driver_setup.verbose)
1004#define bootverbose (np->verbose)
1005
1006/*==========================================================
1007**
1008** Command control block states.
1009**
1010**==========================================================
1011*/
1012
1013#define HS_IDLE (0)
1014#define HS_BUSY (1)
1015#define HS_NEGOTIATE (2) /* sync/wide data transfer*/
1016#define HS_DISCONNECT (3) /* Disconnected by target */
1017
1018#define HS_DONEMASK (0x80)
1019#define HS_COMPLETE (4|HS_DONEMASK)
1020#define HS_SEL_TIMEOUT (5|HS_DONEMASK) /* Selection timeout */
1021#define HS_RESET (6|HS_DONEMASK) /* SCSI reset */
1022#define HS_ABORTED (7|HS_DONEMASK) /* Transfer aborted */
1023#define HS_TIMEOUT (8|HS_DONEMASK) /* Software timeout */
1024#define HS_FAIL (9|HS_DONEMASK) /* SCSI or PCI bus errors */
1025#define HS_UNEXPECTED (10|HS_DONEMASK)/* Unexpected disconnect */
1026
1027/*
1028** Invalid host status values used by the SCRIPTS processor
1029** when the nexus is not fully identified.
1030** Shall never appear in a CCB.
1031*/
1032
1033#define HS_INVALMASK (0x40)
1034#define HS_SELECTING (0|HS_INVALMASK)
1035#define HS_IN_RESELECT (1|HS_INVALMASK)
1036#define HS_STARTING (2|HS_INVALMASK)
1037
1038/*
1039** Flags set by the SCRIPT processor for commands
1040** that have been skipped.
1041*/
1042#define HS_SKIPMASK (0x20)
1043
1044/*==========================================================
1045**
1046** Software Interrupt Codes
1047**
1048**==========================================================
1049*/
1050
1051#define SIR_BAD_STATUS (1)
1052#define SIR_XXXXXXXXXX (2)
1053#define SIR_NEGO_SYNC (3)
1054#define SIR_NEGO_WIDE (4)
1055#define SIR_NEGO_FAILED (5)
1056#define SIR_NEGO_PROTO (6)
1057#define SIR_REJECT_RECEIVED (7)
1058#define SIR_REJECT_SENT (8)
1059#define SIR_IGN_RESIDUE (9)
1060#define SIR_MISSING_SAVE (10)
1061#define SIR_RESEL_NO_MSG_IN (11)
1062#define SIR_RESEL_NO_IDENTIFY (12)
1063#define SIR_RESEL_BAD_LUN (13)
1064#define SIR_RESEL_BAD_TARGET (14)
1065#define SIR_RESEL_BAD_I_T_L (15)
1066#define SIR_RESEL_BAD_I_T_L_Q (16)
1067#define SIR_DONE_OVERFLOW (17)
1068#define SIR_INTFLY (18)
1069#define SIR_MAX (18)
1070
1071/*==========================================================
1072**
1073** Extended error codes.
1074** xerr_status field of struct ccb.
1075**
1076**==========================================================
1077*/
1078
1079#define XE_OK (0)
1080#define XE_EXTRA_DATA (1) /* unexpected data phase */
1081#define XE_BAD_PHASE (2) /* illegal phase (4/5) */
1082
1083/*==========================================================
1084**
1085** Negotiation status.
1086** nego_status field of struct ccb.
1087**
1088**==========================================================
1089*/
1090
1091#define NS_NOCHANGE (0)
1092#define NS_SYNC (1)
1093#define NS_WIDE (2)
1094#define NS_PPR (4)
1095
1096/*==========================================================
1097**
1098** Misc.
1099**
1100**==========================================================
1101*/
1102
1103#define CCB_MAGIC (0xf2691ad2)
1104
1105/*==========================================================
1106**
1107** Declaration of structs.
1108**
1109**==========================================================
1110*/
1111
1112static struct scsi_transport_template *ncr53c8xx_transport_template = NULL;
1113
1114struct tcb;
1115struct lcb;
1116struct ccb;
1117struct ncb;
1118struct script;
1119
1120struct link {
1121 ncrcmd l_cmd;
1122 ncrcmd l_paddr;
1123};
1124
1125struct usrcmd {
1126 u_long target;
1127 u_long lun;
1128 u_long data;
1129 u_long cmd;
1130};
1131
1132#define UC_SETSYNC 10
1133#define UC_SETTAGS 11
1134#define UC_SETDEBUG 12
1135#define UC_SETORDER 13
1136#define UC_SETWIDE 14
1137#define UC_SETFLAG 15
1138#define UC_SETVERBOSE 17
1139
1140#define UF_TRACE (0x01)
1141#define UF_NODISC (0x02)
1142#define UF_NOSCAN (0x04)
1143
1144/*========================================================================
1145**
1146** Declaration of structs: target control block
1147**
1148**========================================================================
1149*/
1150struct tcb {
1151 /*----------------------------------------------------------------
1152 ** During reselection the ncr jumps to this point with SFBR
1153 ** set to the encoded target number with bit 7 set.
1154 ** if it's not this target, jump to the next.
1155 **
1156 ** JUMP IF (SFBR != #target#), @(next tcb)
1157 **----------------------------------------------------------------
1158 */
1159 struct link jump_tcb;
1160
1161 /*----------------------------------------------------------------
1162 ** Load the actual values for the sxfer and the scntl3
1163 ** register (sync/wide mode).
1164 **
1165 ** SCR_COPY (1), @(sval field of this tcb), @(sxfer register)
1166 ** SCR_COPY (1), @(wval field of this tcb), @(scntl3 register)
1167 **----------------------------------------------------------------
1168 */
1169 ncrcmd getscr[6];
1170
1171 /*----------------------------------------------------------------
1172 ** Get the IDENTIFY message and load the LUN to SFBR.
1173 **
1174 ** CALL, <RESEL_LUN>
1175 **----------------------------------------------------------------
1176 */
1177 struct link call_lun;
1178
1179 /*----------------------------------------------------------------
1180 ** Now look for the right lun.
1181 **
1182 ** For i = 0 to 3
1183 ** SCR_JUMP ^ IFTRUE(MASK(i, 3)), @(first lcb mod. i)
1184 **
1185 ** Recent chips will prefetch the 4 JUMPS using only 1 burst.
1186 ** It is kind of hashcoding.
1187 **----------------------------------------------------------------
1188 */
1189 struct link jump_lcb[4]; /* JUMPs for reselection */
1190 struct lcb * lp[MAX_LUN]; /* The lcb's of this tcb */
1191
1192 /*----------------------------------------------------------------
1193 ** Pointer to the ccb used for negotiation.
1194 ** Prevent from starting a negotiation for all queued commands
1195 ** when tagged command queuing is enabled.
1196 **----------------------------------------------------------------
1197 */
1198 struct ccb * nego_cp;
1199
1200 /*----------------------------------------------------------------
1201 ** statistical data
1202 **----------------------------------------------------------------
1203 */
1204 u_long transfers;
1205 u_long bytes;
1206
1207 /*----------------------------------------------------------------
1208 ** negotiation of wide and synch transfer and device quirks.
1209 **----------------------------------------------------------------
1210 */
1211#ifdef SCSI_NCR_BIG_ENDIAN
1212/*0*/ u16 period;
1213/*2*/ u_char sval;
1214/*3*/ u_char minsync;
1215/*0*/ u_char wval;
1216/*1*/ u_char widedone;
1217/*2*/ u_char quirks;
1218/*3*/ u_char maxoffs;
1219#else
1220/*0*/ u_char minsync;
1221/*1*/ u_char sval;
1222/*2*/ u16 period;
1223/*0*/ u_char maxoffs;
1224/*1*/ u_char quirks;
1225/*2*/ u_char widedone;
1226/*3*/ u_char wval;
1227#endif
1228
1229 /* User settable limits and options. */
1230 u_char usrsync;
1231 u_char usrwide;
1232 u_char usrtags;
1233 u_char usrflag;
1234 struct scsi_target *starget;
1235};
1236
1237/*========================================================================
1238**
1239** Declaration of structs: lun control block
1240**
1241**========================================================================
1242*/
1243struct lcb {
1244 /*----------------------------------------------------------------
1245 ** During reselection the ncr jumps to this point
1246 ** with SFBR set to the "Identify" message.
1247 ** if it's not this lun, jump to the next.
1248 **
1249 ** JUMP IF (SFBR != #lun#), @(next lcb of this target)
1250 **
1251 ** It is this lun. Load TEMP with the nexus jumps table
1252 ** address and jump to RESEL_TAG (or RESEL_NOTAG).
1253 **
1254 ** SCR_COPY (4), p_jump_ccb, TEMP,
1255 ** SCR_JUMP, <RESEL_TAG>
1256 **----------------------------------------------------------------
1257 */
1258 struct link jump_lcb;
1259 ncrcmd load_jump_ccb[3];
1260 struct link jump_tag;
1261 ncrcmd p_jump_ccb; /* Jump table bus address */
1262
1263 /*----------------------------------------------------------------
1264 ** Jump table used by the script processor to directly jump
1265 ** to the CCB corresponding to the reselected nexus.
1266 ** Address is allocated on 256 bytes boundary in order to
1267 ** allow 8 bit calculation of the tag jump entry for up to
1268 ** 64 possible tags.
1269 **----------------------------------------------------------------
1270 */
1271 u32 jump_ccb_0; /* Default table if no tags */
1272 u32 *jump_ccb; /* Virtual address */
1273
1274 /*----------------------------------------------------------------
1275 ** CCB queue management.
1276 **----------------------------------------------------------------
1277 */
1278 struct list_head free_ccbq; /* Queue of available CCBs */
1279 struct list_head busy_ccbq; /* Queue of busy CCBs */
1280 struct list_head wait_ccbq; /* Queue of waiting for IO CCBs */
1281 struct list_head skip_ccbq; /* Queue of skipped CCBs */
1282 u_char actccbs; /* Number of allocated CCBs */
1283 u_char busyccbs; /* CCBs busy for this lun */
1284 u_char queuedccbs; /* CCBs queued to the controller*/
1285 u_char queuedepth; /* Queue depth for this lun */
1286 u_char scdev_depth; /* SCSI device queue depth */
1287 u_char maxnxs; /* Max possible nexuses */
1288
1289 /*----------------------------------------------------------------
1290 ** Control of tagged command queuing.
1291 ** Tags allocation is performed using a circular buffer.
1292 ** This avoids using a loop for tag allocation.
1293 **----------------------------------------------------------------
1294 */
1295 u_char ia_tag; /* Allocation index */
1296 u_char if_tag; /* Freeing index */
1297 u_char cb_tags[MAX_TAGS]; /* Circular tags buffer */
1298 u_char usetags; /* Command queuing is active */
1299 u_char maxtags; /* Max nr of tags asked by user */
1300 u_char numtags; /* Current number of tags */
1301
1302 /*----------------------------------------------------------------
1303 ** QUEUE FULL control and ORDERED tag control.
1304 **----------------------------------------------------------------
1305 */
1306 /*----------------------------------------------------------------
1307 ** QUEUE FULL and ORDERED tag control.
1308 **----------------------------------------------------------------
1309 */
1310 u16 num_good; /* Nr of GOOD since QUEUE FULL */
1311 tagmap_t tags_umap; /* Used tags bitmap */
1312 tagmap_t tags_smap; /* Tags in use at 'tag_stime' */
1313 u_long tags_stime; /* Last time we set smap=umap */
1314 struct ccb * held_ccb; /* CCB held for QUEUE FULL */
1315};
1316
1317/*========================================================================
1318**
1319** Declaration of structs: the launch script.
1320**
1321**========================================================================
1322**
1323** It is part of the CCB and is called by the scripts processor to
1324** start or restart the data structure (nexus).
1325** This 6 DWORDs mini script makes use of prefetching.
1326**
1327**------------------------------------------------------------------------
1328*/
1329struct launch {
1330 /*----------------------------------------------------------------
1331 ** SCR_COPY(4), @(p_phys), @(dsa register)
1332 ** SCR_JUMP, @(scheduler_point)
1333 **----------------------------------------------------------------
1334 */
1335 ncrcmd setup_dsa[3]; /* Copy 'phys' address to dsa */
1336 struct link schedule; /* Jump to scheduler point */
1337 ncrcmd p_phys; /* 'phys' header bus address */
1338};
1339
1340/*========================================================================
1341**
1342** Declaration of structs: global HEADER.
1343**
1344**========================================================================
1345**
1346** This substructure is copied from the ccb to a global address after
1347** selection (or reselection) and copied back before disconnect.
1348**
1349** These fields are accessible to the script processor.
1350**
1351**------------------------------------------------------------------------
1352*/
1353
1354struct head {
1355 /*----------------------------------------------------------------
1356 ** Saved data pointer.
1357 ** Points to the position in the script responsible for the
1358 ** actual transfer transfer of data.
1359 ** It's written after reception of a SAVE_DATA_POINTER message.
1360 ** The goalpointer points after the last transfer command.
1361 **----------------------------------------------------------------
1362 */
1363 u32 savep;
1364 u32 lastp;
1365 u32 goalp;
1366
1367 /*----------------------------------------------------------------
1368 ** Alternate data pointer.
1369 ** They are copied back to savep/lastp/goalp by the SCRIPTS
1370 ** when the direction is unknown and the device claims data out.
1371 **----------------------------------------------------------------
1372 */
1373 u32 wlastp;
1374 u32 wgoalp;
1375
1376 /*----------------------------------------------------------------
1377 ** The virtual address of the ccb containing this header.
1378 **----------------------------------------------------------------
1379 */
1380 struct ccb * cp;
1381
1382 /*----------------------------------------------------------------
1383 ** Status fields.
1384 **----------------------------------------------------------------
1385 */
1386 u_char scr_st[4]; /* script status */
1387 u_char status[4]; /* host status. must be the */
1388 /* last DWORD of the header. */
1389};
1390
1391/*
1392** The status bytes are used by the host and the script processor.
1393**
1394** The byte corresponding to the host_status must be stored in the
1395** last DWORD of the CCB header since it is used for command
1396** completion (ncr_wakeup()). Doing so, we are sure that the header
1397** has been entirely copied back to the CCB when the host_status is
1398** seen complete by the CPU.
1399**
1400** The last four bytes (status[4]) are copied to the scratchb register
1401** (declared as scr0..scr3 in ncr_reg.h) just after the select/reselect,
1402** and copied back just after disconnecting.
1403** Inside the script the XX_REG are used.
1404**
1405** The first four bytes (scr_st[4]) are used inside the script by
1406** "COPY" commands.
1407** Because source and destination must have the same alignment
0779bf2d 1408** in a DWORD, the fields HAVE to be at the chosen offsets.
1da177e4
LT		 1409** xerr_st 0 (0x34) scratcha
1410** sync_st 1 (0x05) sxfer
1411** wide_st 3 (0x03) scntl3
1412*/
1413
1414/*
1415** Last four bytes (script)
1416*/
1417#define QU_REG scr0
1418#define HS_REG scr1
1419#define HS_PRT nc_scr1
1420#define SS_REG scr2
1421#define SS_PRT nc_scr2
1422#define PS_REG scr3
1423
1424/*
1425** Last four bytes (host)
1426*/
1427#ifdef SCSI_NCR_BIG_ENDIAN
1428#define actualquirks phys.header.status[3]
1429#define host_status phys.header.status[2]
1430#define scsi_status phys.header.status[1]
1431#define parity_status phys.header.status[0]
1432#else
1433#define actualquirks phys.header.status[0]
1434#define host_status phys.header.status[1]
1435#define scsi_status phys.header.status[2]
1436#define parity_status phys.header.status[3]
1437#endif
1438
1439/*
1440** First four bytes (script)
1441*/
1442#define xerr_st header.scr_st[0]
1443#define sync_st header.scr_st[1]
1444#define nego_st header.scr_st[2]
1445#define wide_st header.scr_st[3]
1446
1447/*
1448** First four bytes (host)
1449*/
1450#define xerr_status phys.xerr_st
1451#define nego_status phys.nego_st
1452
1453#if 0
1454#define sync_status phys.sync_st
1455#define wide_status phys.wide_st
1456#endif
1457
1458/*==========================================================
1459**
1460** Declaration of structs: Data structure block
1461**
1462**==========================================================
1463**
1464** During execution of a ccb by the script processor,
1465** the DSA (data structure address) register points
1466** to this substructure of the ccb.
1467** This substructure contains the header with
0779bf2d 1468** the script-processor-changeable data and
1da177e4
LT		 1469** data blocks for the indirect move commands.
1470**
1471**----------------------------------------------------------
1472*/
1473
1474struct dsb {
1475
1476 /*
1477 ** Header.
1478 */
1479
1480 struct head header;
1481
1482 /*
1483 ** Table data for Script
1484 */
1485
1486 struct scr_tblsel select;
1487 struct scr_tblmove smsg ;
1488 struct scr_tblmove cmd ;
1489 struct scr_tblmove sense ;
1490 struct scr_tblmove data[MAX_SCATTER];
1491};
1492
1493
1494/*========================================================================
1495**
1496** Declaration of structs: Command control block.
1497**
1498**========================================================================
1499*/
1500struct ccb {
1501 /*----------------------------------------------------------------
1502 ** This is the data structure which is pointed by the DSA
1503 ** register when it is executed by the script processor.
1504 ** It must be the first entry because it contains the header
1505 ** as first entry that must be cache line aligned.
1506 **----------------------------------------------------------------
1507 */
1508 struct dsb phys;
1509
1510 /*----------------------------------------------------------------
1511 ** Mini-script used at CCB execution start-up.
1512 ** Load the DSA with the data structure address (phys) and
1513 ** jump to SELECT. Jump to CANCEL if CCB is to be canceled.
1514 **----------------------------------------------------------------
1515 */
1516 struct launch start;
1517
1518 /*----------------------------------------------------------------
1519 ** Mini-script used at CCB relection to restart the nexus.
1520 ** Load the DSA with the data structure address (phys) and
1521 ** jump to RESEL_DSA. Jump to ABORT if CCB is to be aborted.
1522 **----------------------------------------------------------------
1523 */
1524 struct launch restart;
1525
1526 /*----------------------------------------------------------------
1527 ** If a data transfer phase is terminated too early
1528 ** (after reception of a message (i.e. DISCONNECT)),
1529 ** we have to prepare a mini script to transfer
1530 ** the rest of the data.
1531 **----------------------------------------------------------------
1532 */
1533 ncrcmd patch[8];
1534
1535 /*----------------------------------------------------------------
1536 ** The general SCSI driver provides a
1537 ** pointer to a control block.
1538 **----------------------------------------------------------------
1539 */
1540 struct scsi_cmnd *cmd; /* SCSI command */
1541 u_char cdb_buf[16]; /* Copy of CDB */
1542 u_char sense_buf[64];
1543 int data_len; /* Total data length */
1544
1545 /*----------------------------------------------------------------
1546 ** Message areas.
1547 ** We prepare a message to be sent after selection.
1548 ** We may use a second one if the command is rescheduled
1549 ** due to GETCC or QFULL.
1550 ** Contents are IDENTIFY and SIMPLE_TAG.
1551 ** While negotiating sync or wide transfer,
1552 ** a SDTR or WDTR message is appended.
1553 **----------------------------------------------------------------
1554 */
1555 u_char scsi_smsg [8];
1556 u_char scsi_smsg2[8];
1557
1558 /*----------------------------------------------------------------
1559 ** Other fields.
1560 **----------------------------------------------------------------
1561 */
1562 u_long p_ccb; /* BUS address of this CCB */
1563 u_char sensecmd[6]; /* Sense command */
1564 u_char tag; /* Tag for this transfer */
1565 /* 255 means no tag */
1566 u_char target;
1567 u_char lun;
1568 u_char queued;
1569 u_char auto_sense;
1570 struct ccb * link_ccb; /* Host adapter CCB chain */
1571 struct list_head link_ccbq; /* Link to unit CCB queue */
1572 u32 startp; /* Initial data pointer */
1573 u_long magic; /* Free / busy CCB flag */
1574};
1575
1576#define CCB_PHYS(cp,lbl) (cp->p_ccb + offsetof(struct ccb, lbl))
1577
1578
1579/*========================================================================
1580**
1581** Declaration of structs: NCR device descriptor
1582**
1583**========================================================================
1584*/
1585struct ncb {
1586 /*----------------------------------------------------------------
1587 ** The global header.
1588 ** It is accessible to both the host and the script processor.
1589 ** Must be cache line size aligned (32 for x86) in order to
1590 ** allow cache line bursting when it is copied to/from CCB.
1591 **----------------------------------------------------------------
1592 */
1593 struct head header;
1594
1595 /*----------------------------------------------------------------
1596 ** CCBs management queues.
1597 **----------------------------------------------------------------
1598 */
1599 struct scsi_cmnd *waiting_list; /* Commands waiting for a CCB */
1600 /* when lcb is not allocated. */
1601 struct scsi_cmnd *done_list; /* Commands waiting for done() */
1602 /* callback to be invoked. */
1603 spinlock_t smp_lock; /* Lock for SMP threading */
1604
1605 /*----------------------------------------------------------------
3f79410c 1606 ** Chip and controller identification.
1da177e4
LT		 1607 **----------------------------------------------------------------
1608 */
1609 int unit; /* Unit number */
1610 char inst_name[16]; /* ncb instance name */
1611
1612 /*----------------------------------------------------------------
1613 ** Initial value of some IO register bits.
1614 ** These values are assumed to have been set by BIOS, and may
1615 ** be used for probing adapter implementation differences.
1616 **----------------------------------------------------------------
1617 */
1618 u_char sv_scntl0, sv_scntl3, sv_dmode, sv_dcntl, sv_ctest0, sv_ctest3,
1619 sv_ctest4, sv_ctest5, sv_gpcntl, sv_stest2, sv_stest4;
1620
1621 /*----------------------------------------------------------------
1622 ** Actual initial value of IO register bits used by the
1623 ** driver. They are loaded at initialisation according to
1624 ** features that are to be enabled.
1625 **----------------------------------------------------------------
1626 */
1627 u_char rv_scntl0, rv_scntl3, rv_dmode, rv_dcntl, rv_ctest0, rv_ctest3,
1628 rv_ctest4, rv_ctest5, rv_stest2;
1629
1630 /*----------------------------------------------------------------
1631 ** Targets management.
1632 ** During reselection the ncr jumps to jump_tcb.
1633 ** The SFBR register is loaded with the encoded target id.
1634 ** For i = 0 to 3
1635 ** SCR_JUMP ^ IFTRUE(MASK(i, 3)), @(next tcb mod. i)
1636 **
1637 ** Recent chips will prefetch the 4 JUMPS using only 1 burst.
1638 ** It is kind of hashcoding.
1639 **----------------------------------------------------------------
1640 */
1641 struct link jump_tcb[4]; /* JUMPs for reselection */
1642 struct tcb target[MAX_TARGET]; /* Target data */
1643
1644 /*----------------------------------------------------------------
1645 ** Virtual and physical bus addresses of the chip.
1646 **----------------------------------------------------------------
1647 */
1648 void __iomem *vaddr; /* Virtual and bus address of */
1649 unsigned long paddr; /* chip's IO registers. */
1650 unsigned long paddr2; /* On-chip RAM bus address. */
1651 volatile /* Pointer to volatile for */
1652 struct ncr_reg __iomem *reg; /* memory mapped IO. */
1653
1654 /*----------------------------------------------------------------
1655 ** SCRIPTS virtual and physical bus addresses.
1656 ** 'script' is loaded in the on-chip RAM if present.
1657 ** 'scripth' stays in main memory.
1658 **----------------------------------------------------------------
1659 */
1660 struct script *script0; /* Copies of script and scripth */
1661 struct scripth *scripth0; /* relocated for this ncb. */
1662 struct scripth *scripth; /* Actual scripth virt. address */
1663 u_long p_script; /* Actual script and scripth */
1664 u_long p_scripth; /* bus addresses. */
1665
1666 /*----------------------------------------------------------------
1667 ** General controller parameters and configuration.
1668 **----------------------------------------------------------------
1669 */
1670 struct device *dev;
1671 u_char revision_id; /* PCI device revision id */
1672 u32 irq; /* IRQ level */
1673 u32 features; /* Chip features map */
1674 u_char myaddr; /* SCSI id of the adapter */
1675 u_char maxburst; /* log base 2 of dwords burst */
1676 u_char maxwide; /* Maximum transfer width */
1677 u_char minsync; /* Minimum sync period factor */
1678 u_char maxsync; /* Maximum sync period factor */
1679 u_char maxoffs; /* Max scsi offset */
1680 u_char multiplier; /* Clock multiplier (1,2,4) */
1681 u_char clock_divn; /* Number of clock divisors */
1682 u_long clock_khz; /* SCSI clock frequency in KHz */
1683
1684 /*----------------------------------------------------------------
1685 ** Start queue management.
1686 ** It is filled up by the host processor and accessed by the
1687 ** SCRIPTS processor in order to start SCSI commands.
1688 **----------------------------------------------------------------
1689 */
1690 u16 squeueput; /* Next free slot of the queue */
1691 u16 actccbs; /* Number of allocated CCBs */
1692 u16 queuedccbs; /* Number of CCBs in start queue*/
1693 u16 queuedepth; /* Start queue depth */
1694
1695 /*----------------------------------------------------------------
1696 ** Timeout handler.
1697 **----------------------------------------------------------------
1698 */
1699 struct timer_list timer; /* Timer handler link header */
1700 u_long lasttime;
1701 u_long settle_time; /* Resetting the SCSI BUS */
1702
1703 /*----------------------------------------------------------------
1704 ** Debugging and profiling.
1705 **----------------------------------------------------------------
1706 */
1707 struct ncr_reg regdump; /* Register dump */
1708 u_long regtime; /* Time it has been done */
1709
1710 /*----------------------------------------------------------------
1711 ** Miscellaneous buffers accessed by the scripts-processor.
1712 ** They shall be DWORD aligned, because they may be read or
1713 ** written with a SCR_COPY script command.
1714 **----------------------------------------------------------------
1715 */
1716 u_char msgout[8]; /* Buffer for MESSAGE OUT */
1717 u_char msgin [8]; /* Buffer for MESSAGE IN */
1718 u32 lastmsg; /* Last SCSI message sent */
1719 u_char scratch; /* Scratch for SCSI receive */
1720
1721 /*----------------------------------------------------------------
1722 ** Miscellaneous configuration and status parameters.
1723 **----------------------------------------------------------------
1724 */
1725 u_char disc; /* Diconnection allowed */
1726 u_char scsi_mode; /* Current SCSI BUS mode */
1727 u_char order; /* Tag order to use */
1728 u_char verbose; /* Verbosity for this controller*/
1729 int ncr_cache; /* Used for cache test at init. */
1730 u_long p_ncb; /* BUS address of this NCB */
1731
1732 /*----------------------------------------------------------------
1733 ** Command completion handling.
1734 **----------------------------------------------------------------
1735 */
1736#ifdef SCSI_NCR_CCB_DONE_SUPPORT
1737 struct ccb *(ccb_done[MAX_DONE]);
1738 int ccb_done_ic;
1739#endif
1740 /*----------------------------------------------------------------
1741 ** Fields that should be removed or changed.
1742 **----------------------------------------------------------------
1743 */
1744 struct ccb *ccb; /* Global CCB */
1745 struct usrcmd user; /* Command from user */
1746 volatile u_char release_stage; /* Synchronisation stage on release */
1747};
1748
1749#define NCB_SCRIPT_PHYS(np,lbl) (np->p_script + offsetof (struct script, lbl))
1750#define NCB_SCRIPTH_PHYS(np,lbl) (np->p_scripth + offsetof (struct scripth,lbl))
1751
1752/*==========================================================
1753**
1754**
1755** Script for NCR-Processor.
1756**
1757** Use ncr_script_fill() to create the variable parts.
1758** Use ncr_script_copy_and_bind() to make a copy and
1759** bind to physical addresses.
1760**
1761**
1762**==========================================================
1763**
1764** We have to know the offsets of all labels before
1765** we reach them (for forward jumps).
1766** Therefore we declare a struct here.
1767** If you make changes inside the script,
1768** DONT FORGET TO CHANGE THE LENGTHS HERE!
1769**
1770**----------------------------------------------------------
1771*/
1772
1773/*
1774** For HP Zalon/53c720 systems, the Zalon interface
1775** between CPU and 53c720 does prefetches, which causes
1776** problems with self modifying scripts. The problem
1777** is overcome by calling a dummy subroutine after each
1778** modification, to force a refetch of the script on
1779** return from the subroutine.
1780*/
1781
1782#ifdef CONFIG_NCR53C8XX_PREFETCH
1783#define PREFETCH_FLUSH_CNT 2
1784#define PREFETCH_FLUSH SCR_CALL, PADDRH (wait_dma),
1785#else
1786#define PREFETCH_FLUSH_CNT 0
1787#define PREFETCH_FLUSH
1788#endif
1789
1790/*
1791** Script fragments which are loaded into the on-chip RAM
1792** of 825A, 875 and 895 chips.
1793*/
1794struct script {
1795 ncrcmd start [ 5];
1796 ncrcmd startpos [ 1];
1797 ncrcmd select [ 6];
1798 ncrcmd select2 [ 9 + PREFETCH_FLUSH_CNT];
1799 ncrcmd loadpos [ 4];
1800 ncrcmd send_ident [ 9];
1801 ncrcmd prepare [ 6];
1802 ncrcmd prepare2 [ 7];
1803 ncrcmd command [ 6];
1804 ncrcmd dispatch [ 32];
1805 ncrcmd clrack [ 4];
1806 ncrcmd no_data [ 17];
1807 ncrcmd status [ 8];
1808 ncrcmd msg_in [ 2];
1809 ncrcmd msg_in2 [ 16];
1810 ncrcmd msg_bad [ 4];
1811 ncrcmd setmsg [ 7];
1812 ncrcmd cleanup [ 6];
1813 ncrcmd complete [ 9];
1814 ncrcmd cleanup_ok [ 8 + PREFETCH_FLUSH_CNT];
1815 ncrcmd cleanup0 [ 1];
1816#ifndef SCSI_NCR_CCB_DONE_SUPPORT
1817 ncrcmd signal [ 12];
1818#else
1819 ncrcmd signal [ 9];
1820 ncrcmd done_pos [ 1];
1821 ncrcmd done_plug [ 2];
1822 ncrcmd done_end [ 7];
1823#endif
1824 ncrcmd save_dp [ 7];
1825 ncrcmd restore_dp [ 5];
1826 ncrcmd disconnect [ 10];
1827 ncrcmd msg_out [ 9];
1828 ncrcmd msg_out_done [ 7];
1829 ncrcmd idle [ 2];
1830 ncrcmd reselect [ 8];
1831 ncrcmd reselected [ 8];
1832 ncrcmd resel_dsa [ 6 + PREFETCH_FLUSH_CNT];
1833 ncrcmd loadpos1 [ 4];
1834 ncrcmd resel_lun [ 6];
1835 ncrcmd resel_tag [ 6];
1836 ncrcmd jump_to_nexus [ 4 + PREFETCH_FLUSH_CNT];
1837 ncrcmd nexus_indirect [ 4];
1838 ncrcmd resel_notag [ 4];
1839 ncrcmd data_in [MAX_SCATTERL * 4];
1840 ncrcmd data_in2 [ 4];
1841 ncrcmd data_out [MAX_SCATTERL * 4];
1842 ncrcmd data_out2 [ 4];
1843};
1844
1845/*
1846** Script fragments which stay in main memory for all chips.
1847*/
1848struct scripth {
1849 ncrcmd tryloop [MAX_START*2];
1850 ncrcmd tryloop2 [ 2];
1851#ifdef SCSI_NCR_CCB_DONE_SUPPORT
1852 ncrcmd done_queue [MAX_DONE*5];
1853 ncrcmd done_queue2 [ 2];
1854#endif
1855 ncrcmd select_no_atn [ 8];
1856 ncrcmd cancel [ 4];
1857 ncrcmd skip [ 9 + PREFETCH_FLUSH_CNT];
1858 ncrcmd skip2 [ 19];
1859 ncrcmd par_err_data_in [ 6];
1860 ncrcmd par_err_other [ 4];
1861 ncrcmd msg_reject [ 8];
1862 ncrcmd msg_ign_residue [ 24];
1863 ncrcmd msg_extended [ 10];
1864 ncrcmd msg_ext_2 [ 10];
1865 ncrcmd msg_wdtr [ 14];
1866 ncrcmd send_wdtr [ 7];
1867 ncrcmd msg_ext_3 [ 10];
1868 ncrcmd msg_sdtr [ 14];
1869 ncrcmd send_sdtr [ 7];
1870 ncrcmd nego_bad_phase [ 4];
1871 ncrcmd msg_out_abort [ 10];
1872 ncrcmd hdata_in [MAX_SCATTERH * 4];
1873 ncrcmd hdata_in2 [ 2];
1874 ncrcmd hdata_out [MAX_SCATTERH * 4];
1875 ncrcmd hdata_out2 [ 2];
1876 ncrcmd reset [ 4];
1877 ncrcmd aborttag [ 4];
1878 ncrcmd abort [ 2];
1879 ncrcmd abort_resel [ 20];
1880 ncrcmd resend_ident [ 4];
1881 ncrcmd clratn_go_on [ 3];
1882 ncrcmd nxtdsp_go_on [ 1];
1883 ncrcmd sdata_in [ 8];
1884 ncrcmd data_io [ 18];
1885 ncrcmd bad_identify [ 12];
1886 ncrcmd bad_i_t_l [ 4];
1887 ncrcmd bad_i_t_l_q [ 4];
1888 ncrcmd bad_target [ 8];
1889 ncrcmd bad_status [ 8];
1890 ncrcmd start_ram [ 4 + PREFETCH_FLUSH_CNT];
1891 ncrcmd start_ram0 [ 4];
1892 ncrcmd sto_restart [ 5];
1893 ncrcmd wait_dma [ 2];
1894 ncrcmd snooptest [ 9];
1895 ncrcmd snoopend [ 2];
1896};
1897
1898/*==========================================================
1899**
1900**
1901** Function headers.
1902**
1903**
1904**==========================================================
1905*/
1906
1907static void ncr_alloc_ccb (struct ncb *np, u_char tn, u_char ln);
1908static void ncr_complete (struct ncb *np, struct ccb *cp);
1909static void ncr_exception (struct ncb *np);
1910static void ncr_free_ccb (struct ncb *np, struct ccb *cp);
1911static void ncr_init_ccb (struct ncb *np, struct ccb *cp);
1912static void ncr_init_tcb (struct ncb *np, u_char tn);
1913static struct lcb * ncr_alloc_lcb (struct ncb *np, u_char tn, u_char ln);
1914static struct lcb * ncr_setup_lcb (struct ncb *np, struct scsi_device *sdev);
1915static void ncr_getclock (struct ncb *np, int mult);
1916static void ncr_selectclock (struct ncb *np, u_char scntl3);
1917static struct ccb *ncr_get_ccb (struct ncb *np, struct scsi_cmnd *cmd);
1918static void ncr_chip_reset (struct ncb *np, int delay);
1919static void ncr_init (struct ncb *np, int reset, char * msg, u_long code);
1920static int ncr_int_sbmc (struct ncb *np);
1921static int ncr_int_par (struct ncb *np);
1922static void ncr_int_ma (struct ncb *np);
1923static void ncr_int_sir (struct ncb *np);
1924static void ncr_int_sto (struct ncb *np);
1925static void ncr_negotiate (struct ncb* np, struct tcb* tp);
1926static int ncr_prepare_nego(struct ncb *np, struct ccb *cp, u_char *msgptr);
1927
1928static void ncr_script_copy_and_bind
1929 (struct ncb *np, ncrcmd *src, ncrcmd *dst, int len);
1930static void ncr_script_fill (struct script * scr, struct scripth * scripth);
1931static int ncr_scatter (struct ncb *np, struct ccb *cp, struct scsi_cmnd *cmd);
1932static void ncr_getsync (struct ncb *np, u_char sfac, u_char *fakp, u_char *scntl3p);
1933static void ncr_setsync (struct ncb *np, struct ccb *cp, u_char scntl3, u_char sxfer);
1934static void ncr_setup_tags (struct ncb *np, struct scsi_device *sdev);
1935static void ncr_setwide (struct ncb *np, struct ccb *cp, u_char wide, u_char ack);
1936static int ncr_snooptest (struct ncb *np);
1937static void ncr_timeout (struct ncb *np);
1938static void ncr_wakeup (struct ncb *np, u_long code);
1939static void ncr_wakeup_done (struct ncb *np);
1940static void ncr_start_next_ccb (struct ncb *np, struct lcb * lp, int maxn);
1941static void ncr_put_start_queue(struct ncb *np, struct ccb *cp);
1942
1943static void insert_into_waiting_list(struct ncb *np, struct scsi_cmnd *cmd);
1944static struct scsi_cmnd *retrieve_from_waiting_list(int to_remove, struct ncb *np, struct scsi_cmnd *cmd);
1945static void process_waiting_list(struct ncb *np, int sts);
1946
1947#define remove_from_waiting_list(np, cmd) \
1948 retrieve_from_waiting_list(1, (np), (cmd))
1949#define requeue_waiting_list(np) process_waiting_list((np), DID_OK)
1950#define reset_waiting_list(np) process_waiting_list((np), DID_RESET)
1951
1952static inline char *ncr_name (struct ncb *np)
1953{
1954 return np->inst_name;
1955}
1956
1957
1958/*==========================================================
1959**
1960**
1961** Scripts for NCR-Processor.
1962**
1963** Use ncr_script_bind for binding to physical addresses.
1964**
1965**
1966**==========================================================
1967**
1968** NADDR generates a reference to a field of the controller data.
1969** PADDR generates a reference to another part of the script.
1970** RADDR generates a reference to a script processor register.
1971** FADDR generates a reference to a script processor register
1972** with offset.
1973**
1974**----------------------------------------------------------
1975*/
1976
1977#define RELOC_SOFTC 0x40000000
1978#define RELOC_LABEL 0x50000000
1979#define RELOC_REGISTER 0x60000000
1980#if 0
1981#define RELOC_KVAR 0x70000000
1982#endif
1983#define RELOC_LABELH 0x80000000
1984#define RELOC_MASK 0xf0000000
1985
1986#define NADDR(label) (RELOC_SOFTC | offsetof(struct ncb, label))
1987#define PADDR(label) (RELOC_LABEL | offsetof(struct script, label))
1988#define PADDRH(label) (RELOC_LABELH | offsetof(struct scripth, label))
1989#define RADDR(label) (RELOC_REGISTER | REG(label))
1990#define FADDR(label,ofs)(RELOC_REGISTER | ((REG(label))+(ofs)))
1991#if 0
1992#define KVAR(which) (RELOC_KVAR | (which))
1993#endif
1994
1995#if 0
1996#define SCRIPT_KVAR_JIFFIES (0)
1997#define SCRIPT_KVAR_FIRST SCRIPT_KVAR_JIFFIES
1998#define SCRIPT_KVAR_LAST SCRIPT_KVAR_JIFFIES
1999/*
2000 * Kernel variables referenced in the scripts.
2001 * THESE MUST ALL BE ALIGNED TO A 4-BYTE BOUNDARY.
2002 */
2003static void *script_kvars[] __initdata =
2004 { (void *)&jiffies };
2005#endif
2006
2007static struct script script0 __initdata = {
2008/*--------------------------< START >-----------------------*/ {
2009 /*
2010 ** This NOP will be patched with LED ON
2011 ** SCR_REG_REG (gpreg, SCR_AND, 0xfe)
2012 */
2013 SCR_NO_OP,
2014 0,
2015 /*
2016 ** Clear SIGP.
2017 */
2018 SCR_FROM_REG (ctest2),
2019 0,
2020 /*
2021 ** Then jump to a certain point in tryloop.
2022 ** Due to the lack of indirect addressing the code
2023 ** is self modifying here.
2024 */
2025 SCR_JUMP,
2026}/*-------------------------< STARTPOS >--------------------*/,{
2027 PADDRH(tryloop),
2028
2029}/*-------------------------< SELECT >----------------------*/,{
2030 /*
2031 ** DSA contains the address of a scheduled
2032 ** data structure.
2033 **
2034 ** SCRATCHA contains the address of the script,
2035 ** which starts the next entry.
2036 **
2037 ** Set Initiator mode.
2038 **
2039 ** (Target mode is left as an exercise for the reader)
2040 */
2041
2042 SCR_CLR (SCR_TRG),
2043 0,
2044 SCR_LOAD_REG (HS_REG, HS_SELECTING),
2045 0,
2046
2047 /*
2048 ** And try to select this target.
2049 */
2050 SCR_SEL_TBL_ATN ^ offsetof (struct dsb, select),
2051 PADDR (reselect),
2052
2053}/*-------------------------< SELECT2 >----------------------*/,{
2054 /*
2055 ** Now there are 4 possibilities:
2056 **
2057 ** (1) The ncr loses arbitration.
2058 ** This is ok, because it will try again,
2059 ** when the bus becomes idle.
2060 ** (But beware of the timeout function!)
2061 **
2062 ** (2) The ncr is reselected.
2063 ** Then the script processor takes the jump
2064 ** to the RESELECT label.
2065 **
2066 ** (3) The ncr wins arbitration.
2067 ** Then it will execute SCRIPTS instruction until
2068 ** the next instruction that checks SCSI phase.
2069 ** Then will stop and wait for selection to be
2070 ** complete or selection time-out to occur.
2071 ** As a result the SCRIPTS instructions until
2072 ** LOADPOS + 2 should be executed in parallel with
2073 ** the SCSI core performing selection.
2074 */
2075
2076 /*
b0dc1db1 2077 ** The MESSAGE_REJECT problem seems to be due to a selection
1da177e4
LT		 2078 ** timing problem.
2079 ** Wait immediately for the selection to complete.
2080 ** (2.5x behaves so)
2081 */
2082 SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)),
2083 0,
2084
2085 /*
2086 ** Next time use the next slot.
2087 */
2088 SCR_COPY (4),
2089 RADDR (temp),
2090 PADDR (startpos),
2091 /*
2092 ** The ncr doesn't have an indirect load
2093 ** or store command. So we have to
2094 ** copy part of the control block to a
2095 ** fixed place, where we can access it.
2096 **
2097 ** We patch the address part of a
2098 ** COPY command with the DSA-register.
2099 */
2100 SCR_COPY_F (4),
2101 RADDR (dsa),
2102 PADDR (loadpos),
2103 /*
2104 ** Flush script prefetch if required
2105 */
2106 PREFETCH_FLUSH
2107 /*
2108 ** then we do the actual copy.
2109 */
2110 SCR_COPY (sizeof (struct head)),
2111 /*
2112 ** continued after the next label ...
2113 */
2114}/*-------------------------< LOADPOS >---------------------*/,{
2115 0,
2116 NADDR (header),
2117 /*
2118 ** Wait for the next phase or the selection
2119 ** to complete or time-out.
2120 */
2121 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
2122 PADDR (prepare),
2123
2124}/*-------------------------< SEND_IDENT >----------------------*/,{
2125 /*
2126 ** Selection complete.
2127 ** Send the IDENTIFY and SIMPLE_TAG messages
b0dc1db1 2128 ** (and the EXTENDED_SDTR message)
1da177e4
LT		 2129 */
2130 SCR_MOVE_TBL ^ SCR_MSG_OUT,
2131 offsetof (struct dsb, smsg),
2132 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
2133 PADDRH (resend_ident),
2134 SCR_LOAD_REG (scratcha, 0x80),
2135 0,
2136 SCR_COPY (1),
2137 RADDR (scratcha),
2138 NADDR (lastmsg),
2139}/*-------------------------< PREPARE >----------------------*/,{
2140 /*
2141 ** load the savep (saved pointer) into
2142 ** the TEMP register (actual pointer)
2143 */
2144 SCR_COPY (4),
2145 NADDR (header.savep),
2146 RADDR (temp),
2147 /*
2148 ** Initialize the status registers
2149 */
2150 SCR_COPY (4),
2151 NADDR (header.status),
2152 RADDR (scr0),
2153}/*-------------------------< PREPARE2 >---------------------*/,{
2154 /*
2155 ** Initialize the msgout buffer with a NOOP message.
2156 */
b0dc1db1 2157 SCR_LOAD_REG (scratcha, NOP),
1da177e4
LT		 2158 0,
2159 SCR_COPY (1),
2160 RADDR (scratcha),
2161 NADDR (msgout),
2162#if 0
2163 SCR_COPY (1),
2164 RADDR (scratcha),
2165 NADDR (msgin),
2166#endif
2167 /*
2168 ** Anticipate the COMMAND phase.
2169 ** This is the normal case for initial selection.
2170 */
2171 SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)),
2172 PADDR (dispatch),
2173
2174}/*-------------------------< COMMAND >--------------------*/,{
2175 /*
2176 ** ... and send the command
2177 */
2178 SCR_MOVE_TBL ^ SCR_COMMAND,
2179 offsetof (struct dsb, cmd),
2180 /*
2181 ** If status is still HS_NEGOTIATE, negotiation failed.
2182 ** We check this here, since we want to do that
2183 ** only once.
2184 */
2185 SCR_FROM_REG (HS_REG),
2186 0,
2187 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)),
2188 SIR_NEGO_FAILED,
2189
2190}/*-----------------------< DISPATCH >----------------------*/,{
2191 /*
2192 ** MSG_IN is the only phase that shall be
2193 ** entered at least once for each (re)selection.
2194 ** So we test it first.
2195 */
2196 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
2197 PADDR (msg_in),
2198
2199 SCR_RETURN ^ IFTRUE (IF (SCR_DATA_OUT)),
2200 0,
2201 /*
2202 ** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 4.
2203 ** Possible data corruption during Memory Write and Invalidate.
2204 ** This work-around resets the addressing logic prior to the
2205 ** start of the first MOVE of a DATA IN phase.
2206 ** (See Documentation/scsi/ncr53c8xx.txt for more information)
2207 */
2208 SCR_JUMPR ^ IFFALSE (IF (SCR_DATA_IN)),
2209 20,
2210 SCR_COPY (4),
2211 RADDR (scratcha),
2212 RADDR (scratcha),
2213 SCR_RETURN,
2214 0,
2215 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)),
2216 PADDR (status),
2217 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)),
2218 PADDR (command),
2219 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)),
2220 PADDR (msg_out),
2221 /*
2222 ** Discard one illegal phase byte, if required.
2223 */
2224 SCR_LOAD_REG (scratcha, XE_BAD_PHASE),
2225 0,
2226 SCR_COPY (1),
2227 RADDR (scratcha),
2228 NADDR (xerr_st),
2229 SCR_JUMPR ^ IFFALSE (IF (SCR_ILG_OUT)),
2230 8,
2231 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT,
2232 NADDR (scratch),
2233 SCR_JUMPR ^ IFFALSE (IF (SCR_ILG_IN)),
2234 8,
2235 SCR_MOVE_ABS (1) ^ SCR_ILG_IN,
2236 NADDR (scratch),
2237 SCR_JUMP,
2238 PADDR (dispatch),
2239
2240}/*-------------------------< CLRACK >----------------------*/,{
2241 /*
2242 ** Terminate possible pending message phase.
2243 */
2244 SCR_CLR (SCR_ACK),
2245 0,
2246 SCR_JUMP,
2247 PADDR (dispatch),
2248
2249}/*-------------------------< NO_DATA >--------------------*/,{
2250 /*
2251 ** The target wants to tranfer too much data
2252 ** or in the wrong direction.
2253 ** Remember that in extended error.
2254 */
2255 SCR_LOAD_REG (scratcha, XE_EXTRA_DATA),
2256 0,
2257 SCR_COPY (1),
2258 RADDR (scratcha),
2259 NADDR (xerr_st),
2260 /*
2261 ** Discard one data byte, if required.
2262 */
2263 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)),
2264 8,
2265 SCR_MOVE_ABS (1) ^ SCR_DATA_OUT,
2266 NADDR (scratch),
2267 SCR_JUMPR ^ IFFALSE (IF (SCR_DATA_IN)),
2268 8,
2269 SCR_MOVE_ABS (1) ^ SCR_DATA_IN,
2270 NADDR (scratch),
2271 /*
2272 ** .. and repeat as required.
2273 */
2274 SCR_CALL,
2275 PADDR (dispatch),
2276 SCR_JUMP,
2277 PADDR (no_data),
2278
2279}/*-------------------------< STATUS >--------------------*/,{
2280 /*
2281 ** get the status
2282 */
2283 SCR_MOVE_ABS (1) ^ SCR_STATUS,
2284 NADDR (scratch),
2285 /*
2286 ** save status to scsi_status.
2287 ** mark as complete.
2288 */
2289 SCR_TO_REG (SS_REG),
2290 0,
2291 SCR_LOAD_REG (HS_REG, HS_COMPLETE),
2292 0,
2293 SCR_JUMP,
2294 PADDR (dispatch),
2295}/*-------------------------< MSG_IN >--------------------*/,{
2296 /*
2297 ** Get the first byte of the message
2298 ** and save it to SCRATCHA.
2299 **
2300 ** The script processor doesn't negate the
2301 ** ACK signal after this transfer.
2302 */
2303 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2304 NADDR (msgin[0]),
2305}/*-------------------------< MSG_IN2 >--------------------*/,{
2306 /*
2307 ** Handle this message.
2308 */
b0dc1db1 2309 SCR_JUMP ^ IFTRUE (DATA (COMMAND_COMPLETE)),
1da177e4 2310 PADDR (complete),
b0dc1db1 2311 SCR_JUMP ^ IFTRUE (DATA (DISCONNECT)),
1da177e4 2312 PADDR (disconnect),
b0dc1db1 2313 SCR_JUMP ^ IFTRUE (DATA (SAVE_POINTERS)),
1da177e4 2314 PADDR (save_dp),
b0dc1db1 2315 SCR_JUMP ^ IFTRUE (DATA (RESTORE_POINTERS)),
1da177e4 2316 PADDR (restore_dp),
b0dc1db1 2317 SCR_JUMP ^ IFTRUE (DATA (EXTENDED_MESSAGE)),
1da177e4 2318 PADDRH (msg_extended),
b0dc1db1 2319 SCR_JUMP ^ IFTRUE (DATA (NOP)),
1da177e4 2320 PADDR (clrack),
b0dc1db1 2321 SCR_JUMP ^ IFTRUE (DATA (MESSAGE_REJECT)),
1da177e4 2322 PADDRH (msg_reject),
b0dc1db1 2323 SCR_JUMP ^ IFTRUE (DATA (IGNORE_WIDE_RESIDUE)),
1da177e4
LT		 2324 PADDRH (msg_ign_residue),
2325 /*
2326 ** Rest of the messages left as
2327 ** an exercise ...
2328 **
2329 ** Unimplemented messages:
2330 ** fall through to MSG_BAD.
2331 */
2332}/*-------------------------< MSG_BAD >------------------*/,{
2333 /*
2334 ** unimplemented message - reject it.
2335 */
2336 SCR_INT,
2337 SIR_REJECT_SENT,
b0dc1db1 2338 SCR_LOAD_REG (scratcha, MESSAGE_REJECT),
1da177e4
LT		 2339 0,
2340}/*-------------------------< SETMSG >----------------------*/,{
2341 SCR_COPY (1),
2342 RADDR (scratcha),
2343 NADDR (msgout),
2344 SCR_SET (SCR_ATN),
2345 0,
2346 SCR_JUMP,
2347 PADDR (clrack),
2348}/*-------------------------< CLEANUP >-------------------*/,{
2349 /*
2350 ** dsa: Pointer to ccb
2351 ** or xxxxxxFF (no ccb)
2352 **
2353 ** HS_REG: Host-Status (<>0!)
2354 */
2355 SCR_FROM_REG (dsa),
2356 0,
2357 SCR_JUMP ^ IFTRUE (DATA (0xff)),
2358 PADDR (start),
2359 /*
2360 ** dsa is valid.
2361 ** complete the cleanup.
2362 */
2363 SCR_JUMP,
2364 PADDR (cleanup_ok),
2365
2366}/*-------------------------< COMPLETE >-----------------*/,{
2367 /*
2368 ** Complete message.
2369 **
2370 ** Copy TEMP register to LASTP in header.
2371 */
2372 SCR_COPY (4),
2373 RADDR (temp),
2374 NADDR (header.lastp),
2375 /*
2376 ** When we terminate the cycle by clearing ACK,
2377 ** the target may disconnect immediately.
2378 **
2379 ** We don't want to be told of an
2380 ** "unexpected disconnect",
2381 ** so we disable this feature.
2382 */
2383 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
2384 0,
2385 /*
2386 ** Terminate cycle ...
2387 */
2388 SCR_CLR (SCR_ACK|SCR_ATN),
2389 0,
2390 /*
2391 ** ... and wait for the disconnect.
2392 */
2393 SCR_WAIT_DISC,
2394 0,
2395}/*-------------------------< CLEANUP_OK >----------------*/,{
2396 /*
2397 ** Save host status to header.
2398 */
2399 SCR_COPY (4),
2400 RADDR (scr0),
2401 NADDR (header.status),
2402 /*
2403 ** and copy back the header to the ccb.
2404 */
2405 SCR_COPY_F (4),
2406 RADDR (dsa),
2407 PADDR (cleanup0),
2408 /*
2409 ** Flush script prefetch if required
2410 */
2411 PREFETCH_FLUSH
2412 SCR_COPY (sizeof (struct head)),
2413 NADDR (header),
2414}/*-------------------------< CLEANUP0 >--------------------*/,{
2415 0,
2416}/*-------------------------< SIGNAL >----------------------*/,{
2417 /*
2418 ** if job not completed ...
2419 */
2420 SCR_FROM_REG (HS_REG),
2421 0,
2422 /*
2423 ** ... start the next command.
2424 */
2425 SCR_JUMP ^ IFTRUE (MASK (0, (HS_DONEMASK|HS_SKIPMASK))),
2426 PADDR(start),
2427 /*
2428 ** If command resulted in not GOOD status,
2429 ** call the C code if needed.
2430 */
2431 SCR_FROM_REG (SS_REG),
2432 0,
2433 SCR_CALL ^ IFFALSE (DATA (S_GOOD)),
2434 PADDRH (bad_status),
2435
2436#ifndef SCSI_NCR_CCB_DONE_SUPPORT
2437
2438 /*
2439 ** ... signal completion to the host
2440 */
2441 SCR_INT,
2442 SIR_INTFLY,
2443 /*
2444 ** Auf zu neuen Schandtaten!
2445 */
2446 SCR_JUMP,
2447 PADDR(start),
2448
2449#else /* defined SCSI_NCR_CCB_DONE_SUPPORT */
2450
2451 /*
2452 ** ... signal completion to the host
2453 */
2454 SCR_JUMP,
2455}/*------------------------< DONE_POS >---------------------*/,{
2456 PADDRH (done_queue),
2457}/*------------------------< DONE_PLUG >--------------------*/,{
2458 SCR_INT,
2459 SIR_DONE_OVERFLOW,
2460}/*------------------------< DONE_END >---------------------*/,{
2461 SCR_INT,
2462 SIR_INTFLY,
2463 SCR_COPY (4),
2464 RADDR (temp),
2465 PADDR (done_pos),
2466 SCR_JUMP,
2467 PADDR (start),
2468
2469#endif /* SCSI_NCR_CCB_DONE_SUPPORT */
2470
2471}/*-------------------------< SAVE_DP >------------------*/,{
2472 /*
2473 ** SAVE_DP message:
2474 ** Copy TEMP register to SAVEP in header.
2475 */
2476 SCR_COPY (4),
2477 RADDR (temp),
2478 NADDR (header.savep),
2479 SCR_CLR (SCR_ACK),
2480 0,
2481 SCR_JUMP,
2482 PADDR (dispatch),
2483}/*-------------------------< RESTORE_DP >---------------*/,{
2484 /*
2485 ** RESTORE_DP message:
2486 ** Copy SAVEP in header to TEMP register.
2487 */
2488 SCR_COPY (4),
2489 NADDR (header.savep),
2490 RADDR (temp),
2491 SCR_JUMP,
2492 PADDR (clrack),
2493
2494}/*-------------------------< DISCONNECT >---------------*/,{
2495 /*
2496 ** DISCONNECTing ...
2497 **
2498 ** disable the "unexpected disconnect" feature,
2499 ** and remove the ACK signal.
2500 */
2501 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
2502 0,
2503 SCR_CLR (SCR_ACK|SCR_ATN),
2504 0,
2505 /*
2506 ** Wait for the disconnect.
2507 */
2508 SCR_WAIT_DISC,
2509 0,
2510 /*
2511 ** Status is: DISCONNECTED.
2512 */
2513 SCR_LOAD_REG (HS_REG, HS_DISCONNECT),
2514 0,
2515 SCR_JUMP,
2516 PADDR (cleanup_ok),
2517
2518}/*-------------------------< MSG_OUT >-------------------*/,{
2519 /*
2520 ** The target requests a message.
2521 */
2522 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
2523 NADDR (msgout),
2524 SCR_COPY (1),
2525 NADDR (msgout),
2526 NADDR (lastmsg),
2527 /*
2528 ** If it was no ABORT message ...
2529 */
b0dc1db1 2530 SCR_JUMP ^ IFTRUE (DATA (ABORT_TASK_SET)),
1da177e4
LT		 2531 PADDRH (msg_out_abort),
2532 /*
2533 ** ... wait for the next phase
2534 ** if it's a message out, send it again, ...
2535 */
2536 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
2537 PADDR (msg_out),
2538}/*-------------------------< MSG_OUT_DONE >--------------*/,{
2539 /*
2540 ** ... else clear the message ...
2541 */
b0dc1db1 2542 SCR_LOAD_REG (scratcha, NOP),
1da177e4
LT		 2543 0,
2544 SCR_COPY (4),
2545 RADDR (scratcha),
2546 NADDR (msgout),
2547 /*
2548 ** ... and process the next phase
2549 */
2550 SCR_JUMP,
2551 PADDR (dispatch),
2552}/*-------------------------< IDLE >------------------------*/,{
2553 /*
2554 ** Nothing to do?
2555 ** Wait for reselect.
2556 ** This NOP will be patched with LED OFF
2557 ** SCR_REG_REG (gpreg, SCR_OR, 0x01)
2558 */
2559 SCR_NO_OP,
2560 0,
2561}/*-------------------------< RESELECT >--------------------*/,{
2562 /*
2563 ** make the DSA invalid.
2564 */
2565 SCR_LOAD_REG (dsa, 0xff),
2566 0,
2567 SCR_CLR (SCR_TRG),
2568 0,
2569 SCR_LOAD_REG (HS_REG, HS_IN_RESELECT),
2570 0,
2571 /*
2572 ** Sleep waiting for a reselection.
2573 ** If SIGP is set, special treatment.
2574 **
2575 ** Zu allem bereit ..
2576 */
2577 SCR_WAIT_RESEL,
2578 PADDR(start),
2579}/*-------------------------< RESELECTED >------------------*/,{
2580 /*
2581 ** This NOP will be patched with LED ON
2582 ** SCR_REG_REG (gpreg, SCR_AND, 0xfe)
2583 */
2584 SCR_NO_OP,
2585 0,
2586 /*
2587 ** ... zu nichts zu gebrauchen ?
2588 **
2589 ** load the target id into the SFBR
2590 ** and jump to the control block.
2591 **
2592 ** Look at the declarations of
2593 ** - struct ncb
2594 ** - struct tcb
2595 ** - struct lcb
2596 ** - struct ccb
2597 ** to understand what's going on.
2598 */
2599 SCR_REG_SFBR (ssid, SCR_AND, 0x8F),
2600 0,
2601 SCR_TO_REG (sdid),
2602 0,
2603 SCR_JUMP,
2604 NADDR (jump_tcb),
2605
2606}/*-------------------------< RESEL_DSA >-------------------*/,{
2607 /*
2608 ** Ack the IDENTIFY or TAG previously received.
2609 */
2610 SCR_CLR (SCR_ACK),
2611 0,
2612 /*
2613 ** The ncr doesn't have an indirect load
2614 ** or store command. So we have to
2615 ** copy part of the control block to a
2616 ** fixed place, where we can access it.
2617 **
2618 ** We patch the address part of a
2619 ** COPY command with the DSA-register.
2620 */
2621 SCR_COPY_F (4),
2622 RADDR (dsa),
2623 PADDR (loadpos1),
2624 /*
2625 ** Flush script prefetch if required
2626 */
2627 PREFETCH_FLUSH
2628 /*
2629 ** then we do the actual copy.
2630 */
2631 SCR_COPY (sizeof (struct head)),
2632 /*
2633 ** continued after the next label ...
2634 */
2635
2636}/*-------------------------< LOADPOS1 >-------------------*/,{
2637 0,
2638 NADDR (header),
2639 /*
2640 ** The DSA contains the data structure address.
2641 */
2642 SCR_JUMP,
2643 PADDR (prepare),
2644
2645}/*-------------------------< RESEL_LUN >-------------------*/,{
2646 /*
2647 ** come back to this point
2648 ** to get an IDENTIFY message
2649 ** Wait for a msg_in phase.
2650 */
2651 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
2652 SIR_RESEL_NO_MSG_IN,
2653 /*
2654 ** message phase.
2655 ** Read the data directly from the BUS DATA lines.
2656 ** This helps to support very old SCSI devices that
2657 ** may reselect without sending an IDENTIFY.
2658 */
2659 SCR_FROM_REG (sbdl),
2660 0,
2661 /*
2662 ** It should be an Identify message.
2663 */
2664 SCR_RETURN,
2665 0,
2666}/*-------------------------< RESEL_TAG >-------------------*/,{
2667 /*
2668 ** Read IDENTIFY + SIMPLE + TAG using a single MOVE.
25985edc 2669 ** Aggressive optimization, is'nt it?
1da177e4
LT		 2670 ** No need to test the SIMPLE TAG message, since the
2671 ** driver only supports conformant devices for tags. ;-)
2672 */
2673 SCR_MOVE_ABS (3) ^ SCR_MSG_IN,
2674 NADDR (msgin),
2675 /*
2676 ** Read the TAG from the SIDL.
2677 ** Still an aggressive optimization. ;-)
2678 ** Compute the CCB indirect jump address which
2679 ** is (#TAG*2 & 0xfc) due to tag numbering using
2680 ** 1,3,5..MAXTAGS*2+1 actual values.
2681 */
2682 SCR_REG_SFBR (sidl, SCR_SHL, 0),
2683 0,
2684 SCR_SFBR_REG (temp, SCR_AND, 0xfc),
2685 0,
2686}/*-------------------------< JUMP_TO_NEXUS >-------------------*/,{
2687 SCR_COPY_F (4),
2688 RADDR (temp),
2689 PADDR (nexus_indirect),
2690 /*
2691 ** Flush script prefetch if required
2692 */
2693 PREFETCH_FLUSH
2694 SCR_COPY (4),
2695}/*-------------------------< NEXUS_INDIRECT >-------------------*/,{
2696 0,
2697 RADDR (temp),
2698 SCR_RETURN,
2699 0,
2700}/*-------------------------< RESEL_NOTAG >-------------------*/,{
2701 /*
2702 ** No tag expected.
2703 ** Read an throw away the IDENTIFY.
2704 */
2705 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2706 NADDR (msgin),
2707 SCR_JUMP,
2708 PADDR (jump_to_nexus),
2709}/*-------------------------< DATA_IN >--------------------*/,{
2710/*
2711** Because the size depends on the
2712** #define MAX_SCATTERL parameter,
2713** it is filled in at runtime.
2714**
2715** ##===========< i=0; i<MAX_SCATTERL >=========
2716** || SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN)),
2717** || PADDR (dispatch),
2718** || SCR_MOVE_TBL ^ SCR_DATA_IN,
2719** || offsetof (struct dsb, data[ i]),
2720** ##==========================================
2721**
2722**---------------------------------------------------------
2723*/
27240
2725}/*-------------------------< DATA_IN2 >-------------------*/,{
2726 SCR_CALL,
2727 PADDR (dispatch),
2728 SCR_JUMP,
2729 PADDR (no_data),
2730}/*-------------------------< DATA_OUT >--------------------*/,{
2731/*
2732** Because the size depends on the
2733** #define MAX_SCATTERL parameter,
2734** it is filled in at runtime.
2735**
2736** ##===========< i=0; i<MAX_SCATTERL >=========
2737** || SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_OUT)),
2738** || PADDR (dispatch),
2739** || SCR_MOVE_TBL ^ SCR_DATA_OUT,
2740** || offsetof (struct dsb, data[ i]),
2741** ##==========================================
2742**
2743**---------------------------------------------------------
2744*/
27450
2746}/*-------------------------< DATA_OUT2 >-------------------*/,{
2747 SCR_CALL,
2748 PADDR (dispatch),
2749 SCR_JUMP,
2750 PADDR (no_data),
2751}/*--------------------------------------------------------*/
2752};
2753
2754static struct scripth scripth0 __initdata = {
2755/*-------------------------< TRYLOOP >---------------------*/{
2756/*
2757** Start the next entry.
2758** Called addresses point to the launch script in the CCB.
2759** They are patched by the main processor.
2760**
2761** Because the size depends on the
2762** #define MAX_START parameter, it is filled
2763** in at runtime.
2764**
2765**-----------------------------------------------------------
2766**
2767** ##===========< I=0; i<MAX_START >===========
2768** || SCR_CALL,
2769** || PADDR (idle),
2770** ##==========================================
2771**
2772**-----------------------------------------------------------
2773*/
27740
2775}/*------------------------< TRYLOOP2 >---------------------*/,{
2776 SCR_JUMP,
2777 PADDRH(tryloop),
2778
2779#ifdef SCSI_NCR_CCB_DONE_SUPPORT
2780
2781}/*------------------------< DONE_QUEUE >-------------------*/,{
2782/*
2783** Copy the CCB address to the next done entry.
2784** Because the size depends on the
2785** #define MAX_DONE parameter, it is filled
2786** in at runtime.
2787**
2788**-----------------------------------------------------------
2789**
2790** ##===========< I=0; i<MAX_DONE >===========
2791** || SCR_COPY (sizeof(struct ccb *),
2792** || NADDR (header.cp),
2793** || NADDR (ccb_done[i]),
2794** || SCR_CALL,
2795** || PADDR (done_end),
2796** ##==========================================
2797**
2798**-----------------------------------------------------------
2799*/
28000
2801}/*------------------------< DONE_QUEUE2 >------------------*/,{
2802 SCR_JUMP,
2803 PADDRH (done_queue),
2804
2805#endif /* SCSI_NCR_CCB_DONE_SUPPORT */
2806}/*------------------------< SELECT_NO_ATN >-----------------*/,{
2807 /*
2808 ** Set Initiator mode.
2809 ** And try to select this target without ATN.
2810 */
2811
2812 SCR_CLR (SCR_TRG),
2813 0,
2814 SCR_LOAD_REG (HS_REG, HS_SELECTING),
2815 0,
2816 SCR_SEL_TBL ^ offsetof (struct dsb, select),
2817 PADDR (reselect),
2818 SCR_JUMP,
2819 PADDR (select2),
2820
2821}/*-------------------------< CANCEL >------------------------*/,{
2822
2823 SCR_LOAD_REG (scratcha, HS_ABORTED),
2824 0,
2825 SCR_JUMPR,
2826 8,
2827}/*-------------------------< SKIP >------------------------*/,{
2828 SCR_LOAD_REG (scratcha, 0),
2829 0,
2830 /*
2831 ** This entry has been canceled.
2832 ** Next time use the next slot.
2833 */
2834 SCR_COPY (4),
2835 RADDR (temp),
2836 PADDR (startpos),
2837 /*
2838 ** The ncr doesn't have an indirect load
2839 ** or store command. So we have to
2840 ** copy part of the control block to a
2841 ** fixed place, where we can access it.
2842 **
2843 ** We patch the address part of a
2844 ** COPY command with the DSA-register.
2845 */
2846 SCR_COPY_F (4),
2847 RADDR (dsa),
2848 PADDRH (skip2),
2849 /*
2850 ** Flush script prefetch if required
2851 */
2852 PREFETCH_FLUSH
2853 /*
2854 ** then we do the actual copy.
2855 */
2856 SCR_COPY (sizeof (struct head)),
2857 /*
2858 ** continued after the next label ...
2859 */
2860}/*-------------------------< SKIP2 >---------------------*/,{
2861 0,
2862 NADDR (header),
2863 /*
2864 ** Initialize the status registers
2865 */
2866 SCR_COPY (4),
2867 NADDR (header.status),
2868 RADDR (scr0),
2869 /*
2870 ** Force host status.
2871 */
2872 SCR_FROM_REG (scratcha),
2873 0,
2874 SCR_JUMPR ^ IFFALSE (MASK (0, HS_DONEMASK)),
2875 16,
2876 SCR_REG_REG (HS_REG, SCR_OR, HS_SKIPMASK),
2877 0,
2878 SCR_JUMPR,
2879 8,
2880 SCR_TO_REG (HS_REG),
2881 0,
2882 SCR_LOAD_REG (SS_REG, S_GOOD),
2883 0,
2884 SCR_JUMP,
2885 PADDR (cleanup_ok),
2886
2887},/*-------------------------< PAR_ERR_DATA_IN >---------------*/{
2888 /*
2889 ** Ignore all data in byte, until next phase
2890 */
2891 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
2892 PADDRH (par_err_other),
2893 SCR_MOVE_ABS (1) ^ SCR_DATA_IN,
2894 NADDR (scratch),
2895 SCR_JUMPR,
2896 -24,
2897},/*-------------------------< PAR_ERR_OTHER >------------------*/{
2898 /*
2899 ** count it.
2900 */
2901 SCR_REG_REG (PS_REG, SCR_ADD, 0x01),
2902 0,
2903 /*
2904 ** jump to dispatcher.
2905 */
2906 SCR_JUMP,
2907 PADDR (dispatch),
2908}/*-------------------------< MSG_REJECT >---------------*/,{
2909 /*
2910 ** If a negotiation was in progress,
2911 ** negotiation failed.
2912 ** Otherwise, let the C code print
2913 ** some message.
2914 */
2915 SCR_FROM_REG (HS_REG),
2916 0,
2917 SCR_INT ^ IFFALSE (DATA (HS_NEGOTIATE)),
2918 SIR_REJECT_RECEIVED,
2919 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)),
2920 SIR_NEGO_FAILED,
2921 SCR_JUMP,
2922 PADDR (clrack),
2923
2924}/*-------------------------< MSG_IGN_RESIDUE >----------*/,{
2925 /*
2926 ** Terminate cycle
2927 */
2928 SCR_CLR (SCR_ACK),
2929 0,
2930 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
2931 PADDR (dispatch),
2932 /*
2933 ** get residue size.
2934 */
2935 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2936 NADDR (msgin[1]),
2937 /*
2938 ** Size is 0 .. ignore message.
2939 */
2940 SCR_JUMP ^ IFTRUE (DATA (0)),
2941 PADDR (clrack),
2942 /*
2943 ** Size is not 1 .. have to interrupt.
2944 */
2945 SCR_JUMPR ^ IFFALSE (DATA (1)),
2946 40,
2947 /*
2948 ** Check for residue byte in swide register
2949 */
2950 SCR_FROM_REG (scntl2),
2951 0,
2952 SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)),
2953 16,
2954 /*
2955 ** There IS data in the swide register.
2956 ** Discard it.
2957 */
2958 SCR_REG_REG (scntl2, SCR_OR, WSR),
2959 0,
2960 SCR_JUMP,
2961 PADDR (clrack),
2962 /*
2963 ** Load again the size to the sfbr register.
2964 */
2965 SCR_FROM_REG (scratcha),
2966 0,
2967 SCR_INT,
2968 SIR_IGN_RESIDUE,
2969 SCR_JUMP,
2970 PADDR (clrack),
2971
2972}/*-------------------------< MSG_EXTENDED >-------------*/,{
2973 /*
2974 ** Terminate cycle
2975 */
2976 SCR_CLR (SCR_ACK),
2977 0,
2978 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
2979 PADDR (dispatch),
2980 /*
2981 ** get length.
2982 */
2983 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
2984 NADDR (msgin[1]),
2985 /*
2986 */
2987 SCR_JUMP ^ IFTRUE (DATA (3)),
2988 PADDRH (msg_ext_3),
2989 SCR_JUMP ^ IFFALSE (DATA (2)),
2990 PADDR (msg_bad),
2991}/*-------------------------< MSG_EXT_2 >----------------*/,{
2992 SCR_CLR (SCR_ACK),
2993 0,
2994 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
2995 PADDR (dispatch),
2996 /*
2997 ** get extended message code.
2998 */
2999 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
3000 NADDR (msgin[2]),
b0dc1db1 3001 SCR_JUMP ^ IFTRUE (DATA (EXTENDED_WDTR)),
1da177e4
LT		 3002 PADDRH (msg_wdtr),
3003 /*
3004 ** unknown extended message
3005 */
3006 SCR_JUMP,
3007 PADDR (msg_bad)
3008}/*-------------------------< MSG_WDTR >-----------------*/,{
3009 SCR_CLR (SCR_ACK),
3010 0,
3011 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
3012 PADDR (dispatch),
3013 /*
3014 ** get data bus width
3015 */
3016 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
3017 NADDR (msgin[3]),
3018 /*
3019 ** let the host do the real work.
3020 */
3021 SCR_INT,
3022 SIR_NEGO_WIDE,
3023 /*
3024 ** let the target fetch our answer.
3025 */
3026 SCR_SET (SCR_ATN),
3027 0,
3028 SCR_CLR (SCR_ACK),
3029 0,
3030 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
3031 PADDRH (nego_bad_phase),
3032
3033}/*-------------------------< SEND_WDTR >----------------*/,{
3034 /*
b0dc1db1 3035 ** Send the EXTENDED_WDTR
1da177e4
LT		 3036 */
3037 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT,
3038 NADDR (msgout),
3039 SCR_COPY (1),
3040 NADDR (msgout),
3041 NADDR (lastmsg),
3042 SCR_JUMP,
3043 PADDR (msg_out_done),
3044
3045}/*-------------------------< MSG_EXT_3 >----------------*/,{
3046 SCR_CLR (SCR_ACK),
3047 0,
3048 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
3049 PADDR (dispatch),
3050 /*
3051 ** get extended message code.
3052 */
3053 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
3054 NADDR (msgin[2]),
b0dc1db1 3055 SCR_JUMP ^ IFTRUE (DATA (EXTENDED_SDTR)),
1da177e4
LT		 3056 PADDRH (msg_sdtr),
3057 /*
3058 ** unknown extended message
3059 */
3060 SCR_JUMP,
3061 PADDR (msg_bad)
3062
3063}/*-------------------------< MSG_SDTR >-----------------*/,{
3064 SCR_CLR (SCR_ACK),
3065 0,
3066 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
3067 PADDR (dispatch),
3068 /*
3069 ** get period and offset
3070 */
3071 SCR_MOVE_ABS (2) ^ SCR_MSG_IN,
3072 NADDR (msgin[3]),
3073 /*
3074 ** let the host do the real work.
3075 */
3076 SCR_INT,
3077 SIR_NEGO_SYNC,
3078 /*
3079 ** let the target fetch our answer.
3080 */
3081 SCR_SET (SCR_ATN),
3082 0,
3083 SCR_CLR (SCR_ACK),
3084 0,
3085 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
3086 PADDRH (nego_bad_phase),
3087
3088}/*-------------------------< SEND_SDTR >-------------*/,{
3089 /*
b0dc1db1 3090 ** Send the EXTENDED_SDTR
1da177e4
LT		 3091 */
3092 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT,
3093 NADDR (msgout),
3094 SCR_COPY (1),
3095 NADDR (msgout),
3096 NADDR (lastmsg),
3097 SCR_JUMP,
3098 PADDR (msg_out_done),
3099
3100}/*-------------------------< NEGO_BAD_PHASE >------------*/,{
3101 SCR_INT,
3102 SIR_NEGO_PROTO,
3103 SCR_JUMP,
3104 PADDR (dispatch),
3105
3106}/*-------------------------< MSG_OUT_ABORT >-------------*/,{
3107 /*
3108 ** After ABORT message,
3109 **
3110 ** expect an immediate disconnect, ...
3111 */
3112 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
3113 0,
3114 SCR_CLR (SCR_ACK|SCR_ATN),
3115 0,
3116 SCR_WAIT_DISC,
3117 0,
3118 /*
3119 ** ... and set the status to "ABORTED"
3120 */
3121 SCR_LOAD_REG (HS_REG, HS_ABORTED),
3122 0,
3123 SCR_JUMP,
3124 PADDR (cleanup),
3125
3126}/*-------------------------< HDATA_IN >-------------------*/,{
3127/*
3128** Because the size depends on the
3129** #define MAX_SCATTERH parameter,
3130** it is filled in at runtime.
3131**
3132** ##==< i=MAX_SCATTERL; i<MAX_SCATTERL+MAX_SCATTERH >==
3133** || SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN)),
3134** || PADDR (dispatch),
3135** || SCR_MOVE_TBL ^ SCR_DATA_IN,
3136** || offsetof (struct dsb, data[ i]),
3137** ##===================================================
3138**
3139**---------------------------------------------------------
3140*/
31410
3142}/*-------------------------< HDATA_IN2 >------------------*/,{
3143 SCR_JUMP,
3144 PADDR (data_in),
3145
3146}/*-------------------------< HDATA_OUT >-------------------*/,{
3147/*
3148** Because the size depends on the
3149** #define MAX_SCATTERH parameter,
3150** it is filled in at runtime.
3151**
3152** ##==< i=MAX_SCATTERL; i<MAX_SCATTERL+MAX_SCATTERH >==
3153** || SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_OUT)),
3154** || PADDR (dispatch),
3155** || SCR_MOVE_TBL ^ SCR_DATA_OUT,
3156** || offsetof (struct dsb, data[ i]),
3157** ##===================================================
3158**
3159**---------------------------------------------------------
3160*/
31610
3162}/*-------------------------< HDATA_OUT2 >------------------*/,{
3163 SCR_JUMP,
3164 PADDR (data_out),
3165
3166}/*-------------------------< RESET >----------------------*/,{
3167 /*
b0dc1db1 3168 ** Send a TARGET_RESET message if bad IDENTIFY
1da177e4
LT		 3169 ** received on reselection.
3170 */
b0dc1db1 3171 SCR_LOAD_REG (scratcha, ABORT_TASK),
1da177e4
LT		 3172 0,
3173 SCR_JUMP,
3174 PADDRH (abort_resel),
3175}/*-------------------------< ABORTTAG >-------------------*/,{
3176 /*
3177 ** Abort a wrong tag received on reselection.
3178 */
b0dc1db1 3179 SCR_LOAD_REG (scratcha, ABORT_TASK),
1da177e4
LT		 3180 0,
3181 SCR_JUMP,
3182 PADDRH (abort_resel),
3183}/*-------------------------< ABORT >----------------------*/,{
3184 /*
3185 ** Abort a reselection when no active CCB.
3186 */
b0dc1db1 3187 SCR_LOAD_REG (scratcha, ABORT_TASK_SET),
1da177e4
LT		 3188 0,
3189}/*-------------------------< ABORT_RESEL >----------------*/,{
3190 SCR_COPY (1),
3191 RADDR (scratcha),
3192 NADDR (msgout),
3193 SCR_SET (SCR_ATN),
3194 0,
3195 SCR_CLR (SCR_ACK),
3196 0,
3197 /*
3198 ** and send it.
3199 ** we expect an immediate disconnect
3200 */
3201 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
3202 0,
3203 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
3204 NADDR (msgout),
3205 SCR_COPY (1),
3206 NADDR (msgout),
3207 NADDR (lastmsg),
3208 SCR_CLR (SCR_ACK|SCR_ATN),
3209 0,
3210 SCR_WAIT_DISC,
3211 0,
3212 SCR_JUMP,
3213 PADDR (start),
3214}/*-------------------------< RESEND_IDENT >-------------------*/,{
3215 /*
3216 ** The target stays in MSG OUT phase after having acked
3217 ** Identify [+ Tag [+ Extended message ]]. Targets shall
3218 ** behave this way on parity error.
3219 ** We must send it again all the messages.
3220 */
3221 SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the */
3222 0, /* 1rst ACK = 90 ns. Hope the NCR is'nt too fast */
3223 SCR_JUMP,
3224 PADDR (send_ident),
3225}/*-------------------------< CLRATN_GO_ON >-------------------*/,{
3226 SCR_CLR (SCR_ATN),
3227 0,
3228 SCR_JUMP,
3229}/*-------------------------< NXTDSP_GO_ON >-------------------*/,{
3230 0,
3231}/*-------------------------< SDATA_IN >-------------------*/,{
3232 SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN)),
3233 PADDR (dispatch),
3234 SCR_MOVE_TBL ^ SCR_DATA_IN,
3235 offsetof (struct dsb, sense),
3236 SCR_CALL,
3237 PADDR (dispatch),
3238 SCR_JUMP,
3239 PADDR (no_data),
3240}/*-------------------------< DATA_IO >--------------------*/,{
3241 /*
3242 ** We jump here if the data direction was unknown at the
3243 ** time we had to queue the command to the scripts processor.
3244 ** Pointers had been set as follow in this situation:
3245 ** savep --> DATA_IO
3246 ** lastp --> start pointer when DATA_IN
3247 ** goalp --> goal pointer when DATA_IN
3248 ** wlastp --> start pointer when DATA_OUT
3249 ** wgoalp --> goal pointer when DATA_OUT
3250 ** This script sets savep/lastp/goalp according to the
3251 ** direction chosen by the target.
3252 */
3253 SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_OUT)),
3254 32,
3255 /*
3256 ** Direction is DATA IN.
3257 ** Warning: we jump here, even when phase is DATA OUT.
3258 */
3259 SCR_COPY (4),
3260 NADDR (header.lastp),
3261 NADDR (header.savep),
3262
3263 /*
3264 ** Jump to the SCRIPTS according to actual direction.
3265 */
3266 SCR_COPY (4),
3267 NADDR (header.savep),
3268 RADDR (temp),
3269 SCR_RETURN,
3270 0,
3271 /*
3272 ** Direction is DATA OUT.
3273 */
3274 SCR_COPY (4),
3275 NADDR (header.wlastp),
3276 NADDR (header.lastp),
3277 SCR_COPY (4),
3278 NADDR (header.wgoalp),
3279 NADDR (header.goalp),
3280 SCR_JUMPR,
3281 -64,
3282}/*-------------------------< BAD_IDENTIFY >---------------*/,{
3283 /*
3284 ** If message phase but not an IDENTIFY,
3285 ** get some help from the C code.
3286 ** Old SCSI device may behave so.
3287 */
3288 SCR_JUMPR ^ IFTRUE (MASK (0x80, 0x80)),
3289 16,
3290 SCR_INT,
3291 SIR_RESEL_NO_IDENTIFY,
3292 SCR_JUMP,
3293 PADDRH (reset),
3294 /*
3295 ** Message is an IDENTIFY, but lun is unknown.
3296 ** Read the message, since we got it directly
3297 ** from the SCSI BUS data lines.
3298 ** Signal problem to C code for logging the event.
b0dc1db1 3299 ** Send an ABORT_TASK_SET to clear all pending tasks.
1da177e4
LT		 3300 */
3301 SCR_INT,
3302 SIR_RESEL_BAD_LUN,
3303 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
3304 NADDR (msgin),
3305 SCR_JUMP,
3306 PADDRH (abort),
3307}/*-------------------------< BAD_I_T_L >------------------*/,{
3308 /*
3309 ** We donnot have a task for that I_T_L.
3310 ** Signal problem to C code for logging the event.
b0dc1db1 3311 ** Send an ABORT_TASK_SET message.
1da177e4
LT		 3312 */
3313 SCR_INT,
3314 SIR_RESEL_BAD_I_T_L,
3315 SCR_JUMP,
3316 PADDRH (abort),
3317}/*-------------------------< BAD_I_T_L_Q >----------------*/,{
3318 /*
3319 ** We donnot have a task that matches the tag.
3320 ** Signal problem to C code for logging the event.
b0dc1db1 3321 ** Send an ABORT_TASK message.
1da177e4
LT		 3322 */
3323 SCR_INT,
3324 SIR_RESEL_BAD_I_T_L_Q,
3325 SCR_JUMP,
3326 PADDRH (aborttag),
3327}/*-------------------------< BAD_TARGET >-----------------*/,{
3328 /*
3329 ** We donnot know the target that reselected us.
3330 ** Grab the first message if any (IDENTIFY).
3331 ** Signal problem to C code for logging the event.
b0dc1db1 3332 ** TARGET_RESET message.
1da177e4
LT		 3333 */
3334 SCR_INT,
3335 SIR_RESEL_BAD_TARGET,
3336 SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_IN)),
3337 8,
3338 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
3339 NADDR (msgin),
3340 SCR_JUMP,
3341 PADDRH (reset),
3342}/*-------------------------< BAD_STATUS >-----------------*/,{
3343 /*
3344 ** If command resulted in either QUEUE FULL,
3345 ** CHECK CONDITION or COMMAND TERMINATED,
3346 ** call the C code.
3347 */
3348 SCR_INT ^ IFTRUE (DATA (S_QUEUE_FULL)),
3349 SIR_BAD_STATUS,
3350 SCR_INT ^ IFTRUE (DATA (S_CHECK_COND)),
3351 SIR_BAD_STATUS,
3352 SCR_INT ^ IFTRUE (DATA (S_TERMINATED)),
3353 SIR_BAD_STATUS,
3354 SCR_RETURN,
3355 0,
3356}/*-------------------------< START_RAM >-------------------*/,{
3357 /*
3358 ** Load the script into on-chip RAM,
3359 ** and jump to start point.
3360 */
3361 SCR_COPY_F (4),
3362 RADDR (scratcha),
3363 PADDRH (start_ram0),
3364 /*
3365 ** Flush script prefetch if required
3366 */
3367 PREFETCH_FLUSH
3368 SCR_COPY (sizeof (struct script)),
3369}/*-------------------------< START_RAM0 >--------------------*/,{
3370 0,
3371 PADDR (start),
3372 SCR_JUMP,
3373 PADDR (start),
3374}/*-------------------------< STO_RESTART >-------------------*/,{
3375 /*
3376 **
3377 ** Repair start queue (e.g. next time use the next slot)
3378 ** and jump to start point.
3379 */
3380 SCR_COPY (4),
3381 RADDR (temp),
3382 PADDR (startpos),
3383 SCR_JUMP,
3384 PADDR (start),
3385}/*-------------------------< WAIT_DMA >-------------------*/,{
3386 /*
3387 ** For HP Zalon/53c720 systems, the Zalon interface
3388 ** between CPU and 53c720 does prefetches, which causes
3389 ** problems with self modifying scripts. The problem
3390 ** is overcome by calling a dummy subroutine after each
3391 ** modification, to force a refetch of the script on
3392 ** return from the subroutine.
3393 */
3394 SCR_RETURN,
3395 0,
3396}/*-------------------------< SNOOPTEST >-------------------*/,{
3397 /*
3398 ** Read the variable.
3399 */
3400 SCR_COPY (4),
3401 NADDR(ncr_cache),
3402 RADDR (scratcha),
3403 /*
3404 ** Write the variable.
3405 */
3406 SCR_COPY (4),
3407 RADDR (temp),
3408 NADDR(ncr_cache),
3409 /*
3410 ** Read back the variable.
3411 */
3412 SCR_COPY (4),
3413 NADDR(ncr_cache),
3414 RADDR (temp),
3415}/*-------------------------< SNOOPEND >-------------------*/,{
3416 /*
3417 ** And stop.
3418 */
3419 SCR_INT,
3420 99,
3421}/*--------------------------------------------------------*/
3422};
3423
3424/*==========================================================
3425**
3426**
3427** Fill in #define dependent parts of the script
3428**
3429**
3430**==========================================================
3431*/
3432
3433void __init ncr_script_fill (struct script * scr, struct scripth * scrh)
3434{
3435 int i;
3436 ncrcmd *p;
3437
3438 p = scrh->tryloop;
3439 for (i=0; i<MAX_START; i++) {
3440 *p++ =SCR_CALL;
3441 *p++ =PADDR (idle);
3442 }
3443
3444 BUG_ON((u_long)p != (u_long)&scrh->tryloop + sizeof (scrh->tryloop));
3445
3446#ifdef SCSI_NCR_CCB_DONE_SUPPORT
3447
3448 p = scrh->done_queue;
3449 for (i = 0; i<MAX_DONE; i++) {
3450 *p++ =SCR_COPY (sizeof(struct ccb *));
3451 *p++ =NADDR (header.cp);
3452 *p++ =NADDR (ccb_done[i]);
3453 *p++ =SCR_CALL;
3454 *p++ =PADDR (done_end);
3455 }
3456
3457 BUG_ON((u_long)p != (u_long)&scrh->done_queue+sizeof(scrh->done_queue));
3458
3459#endif /* SCSI_NCR_CCB_DONE_SUPPORT */
3460
3461 p = scrh->hdata_in;
3462 for (i=0; i<MAX_SCATTERH; i++) {
3463 *p++ =SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN));
3464 *p++ =PADDR (dispatch);
3465 *p++ =SCR_MOVE_TBL ^ SCR_DATA_IN;
3466 *p++ =offsetof (struct dsb, data[i]);
3467 }
3468
3469 BUG_ON((u_long)p != (u_long)&scrh->hdata_in + sizeof (scrh->hdata_in));
3470
3471 p = scr->data_in;
3472 for (i=MAX_SCATTERH; i<MAX_SCATTERH+MAX_SCATTERL; i++) {
3473 *p++ =SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_IN));
3474 *p++ =PADDR (dispatch);
3475 *p++ =SCR_MOVE_TBL ^ SCR_DATA_IN;
3476 *p++ =offsetof (struct dsb, data[i]);
3477 }
3478
3479 BUG_ON((u_long)p != (u_long)&scr->data_in + sizeof (scr->data_in));
3480
3481 p = scrh->hdata_out;
3482 for (i=0; i<MAX_SCATTERH; i++) {
3483 *p++ =SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_OUT));
3484 *p++ =PADDR (dispatch);
3485 *p++ =SCR_MOVE_TBL ^ SCR_DATA_OUT;
3486 *p++ =offsetof (struct dsb, data[i]);
3487 }
3488
3489 BUG_ON((u_long)p != (u_long)&scrh->hdata_out + sizeof (scrh->hdata_out));
3490
3491 p = scr->data_out;
3492 for (i=MAX_SCATTERH; i<MAX_SCATTERH+MAX_SCATTERL; i++) {
3493 *p++ =SCR_CALL ^ IFFALSE (WHEN (SCR_DATA_OUT));
3494 *p++ =PADDR (dispatch);
3495 *p++ =SCR_MOVE_TBL ^ SCR_DATA_OUT;
3496 *p++ =offsetof (struct dsb, data[i]);
3497 }
3498
3499 BUG_ON((u_long) p != (u_long)&scr->data_out + sizeof (scr->data_out));
3500}
3501
3502/*==========================================================
3503**
3504**
3505** Copy and rebind a script.
3506**
3507**
3508**==========================================================
3509*/
3510
3511static void __init
3512ncr_script_copy_and_bind (struct ncb *np, ncrcmd *src, ncrcmd *dst, int len)
3513{
3514 ncrcmd opcode, new, old, tmp1, tmp2;
3515 ncrcmd *start, *end;
3516 int relocs;
3517 int opchanged = 0;
3518
3519 start = src;
3520 end = src + len/4;
3521
3522 while (src < end) {
3523
3524 opcode = *src++;
3525 *dst++ = cpu_to_scr(opcode);
3526
3527 /*
3528 ** If we forget to change the length
3529 ** in struct script, a field will be
3530 ** padded with 0. This is an illegal
3531 ** command.
3532 */
3533
3534 if (opcode == 0) {
3535 printk (KERN_ERR "%s: ERROR0 IN SCRIPT at %d.\n",
3536 ncr_name(np), (int) (src-start-1));
3537 mdelay(1000);
3538 }
3539
3540 if (DEBUG_FLAGS & DEBUG_SCRIPT)
3541 printk (KERN_DEBUG "%p: <%x>\n",
3542 (src-1), (unsigned)opcode);
3543
3544 /*
3545 ** We don't have to decode ALL commands
3546 */
3547 switch (opcode >> 28) {
3548
3549 case 0xc:
3550 /*
3551 ** COPY has TWO arguments.
3552 */
3553 relocs = 2;
3554 tmp1 = src[0];
3555#ifdef RELOC_KVAR
3556 if ((tmp1 & RELOC_MASK) == RELOC_KVAR)
3557 tmp1 = 0;
3558#endif
3559 tmp2 = src[1];
3560#ifdef RELOC_KVAR
3561 if ((tmp2 & RELOC_MASK) == RELOC_KVAR)
3562 tmp2 = 0;
3563#endif
3564 if ((tmp1 ^ tmp2) & 3) {
3565 printk (KERN_ERR"%s: ERROR1 IN SCRIPT at %d.\n",
3566 ncr_name(np), (int) (src-start-1));
3567 mdelay(1000);
3568 }
3569 /*
3570 ** If PREFETCH feature not enabled, remove
3571 ** the NO FLUSH bit if present.
3572 */
3573 if ((opcode & SCR_NO_FLUSH) && !(np->features & FE_PFEN)) {
3574 dst[-1] = cpu_to_scr(opcode & ~SCR_NO_FLUSH);
3575 ++opchanged;
3576 }
3577 break;
3578
3579 case 0x0:
3580 /*
3581 ** MOVE (absolute address)
3582 */
3583 relocs = 1;
3584 break;
3585
3586 case 0x8:
3587 /*
3588 ** JUMP / CALL
3589 ** don't relocate if relative :-)
3590 */
3591 if (opcode & 0x00800000)
3592 relocs = 0;
3593 else
3594 relocs = 1;
3595 break;
3596
3597 case 0x4:
3598 case 0x5:
3599 case 0x6:
3600 case 0x7:
3601 relocs = 1;
3602 break;
3603
3604 default:
3605 relocs = 0;
3606 break;
3607 }
3608
3609 if (relocs) {
3610 while (relocs--) {
3611 old = *src++;
3612
3613 switch (old & RELOC_MASK) {
3614 case RELOC_REGISTER:
3615 new = (old & ~RELOC_MASK) + np->paddr;
3616 break;
3617 case RELOC_LABEL:
3618 new = (old & ~RELOC_MASK) + np->p_script;
3619 break;
3620 case RELOC_LABELH:
3621 new = (old & ~RELOC_MASK) + np->p_scripth;
3622 break;
3623 case RELOC_SOFTC:
3624 new = (old & ~RELOC_MASK) + np->p_ncb;
3625 break;
3626#ifdef RELOC_KVAR
3627 case RELOC_KVAR:
3628 if (((old & ~RELOC_MASK) <
3629 SCRIPT_KVAR_FIRST) ||
3630 ((old & ~RELOC_MASK) >
3631 SCRIPT_KVAR_LAST))
3632 panic("ncr KVAR out of range");
3633 new = vtophys(script_kvars[old &
3634 ~RELOC_MASK]);
3635 break;
3636#endif
3637 case 0:
3638 /* Don't relocate a 0 address. */
3639 if (old == 0) {
3640 new = old;
3641 break;
3642 }
3643 /* fall through */
3644 default:
3645 panic("ncr_script_copy_and_bind: weird relocation %x\n", old);
3646 break;
3647 }
3648
3649 *dst++ = cpu_to_scr(new);
3650 }
3651 } else
3652 *dst++ = cpu_to_scr(*src++);
3653
3654 }
3655}
3656
3657/*
3658** Linux host data structure
3659*/
3660
3661struct host_data {
3662 struct ncb *ncb;
3663};
3664
3665#define PRINT_ADDR(cmd, arg...) dev_info(&cmd->device->sdev_gendev , ## arg)
3666
3667static void ncr_print_msg(struct ccb *cp, char *label, u_char *msg)
3668{
1da177e4
LT		 3669 PRINT_ADDR(cp->cmd, "%s: ", label);
3670
cd453c63
MW		 3671 spi_print_msg(msg);
3672 printk("\n");
1da177e4
LT		 3673}
3674
3675/*==========================================================
3676**
3677** NCR chip clock divisor table.
3678** Divisors are multiplied by 10,000,000 in order to make
3679** calculations more simple.
3680**
3681**==========================================================
3682*/
3683
3684#define _5M 5000000
3685static u_long div_10M[] =
3686 {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M};
3687
3688
3689/*===============================================================
3690**
3691** Prepare io register values used by ncr_init() according
3692** to selected and supported features.
3693**
3694** NCR chips allow burst lengths of 2, 4, 8, 16, 32, 64, 128
3695** transfers. 32,64,128 are only supported by 875 and 895 chips.
3696** We use log base 2 (burst length) as internal code, with
3697** value 0 meaning "burst disabled".
3698**
3699**===============================================================
3700*/
3701
3702/*
3703 * Burst length from burst code.
3704 */
3705#define burst_length(bc) (!(bc))? 0 : 1 << (bc)
3706
3707/*
3708 * Burst code from io register bits. Burst enable is ctest0 for c720
3709 */
3710#define burst_code(dmode, ctest0) \
3711 (ctest0) & 0x80 ? 0 : (((dmode) & 0xc0) >> 6) + 1
3712
3713/*
3714 * Set initial io register bits from burst code.
3715 */
3716static inline void ncr_init_burst(struct ncb *np, u_char bc)
3717{
3718 u_char *be = &np->rv_ctest0;
3719 *be &= ~0x80;
3720 np->rv_dmode &= ~(0x3 << 6);
3721 np->rv_ctest5 &= ~0x4;
3722
3723 if (!bc) {
3724 *be |= 0x80;
3725 } else {
3726 --bc;
3727 np->rv_dmode |= ((bc & 0x3) << 6);
3728 np->rv_ctest5 |= (bc & 0x4);
3729 }
3730}
3731
3732static void __init ncr_prepare_setting(struct ncb *np)
3733{
3734 u_char burst_max;
3735 u_long period;
3736 int i;
3737
3738 /*
3739 ** Save assumed BIOS setting
3740 */
3741
3742 np->sv_scntl0 = INB(nc_scntl0) & 0x0a;
3743 np->sv_scntl3 = INB(nc_scntl3) & 0x07;
3744 np->sv_dmode = INB(nc_dmode) & 0xce;
3745 np->sv_dcntl = INB(nc_dcntl) & 0xa8;
3746 np->sv_ctest0 = INB(nc_ctest0) & 0x84;
3747 np->sv_ctest3 = INB(nc_ctest3) & 0x01;
3748 np->sv_ctest4 = INB(nc_ctest4) & 0x80;
3749 np->sv_ctest5 = INB(nc_ctest5) & 0x24;
3750 np->sv_gpcntl = INB(nc_gpcntl);
3751 np->sv_stest2 = INB(nc_stest2) & 0x20;
3752 np->sv_stest4 = INB(nc_stest4);
3753
3754 /*
3755 ** Wide ?
3756 */
3757
3758 np->maxwide = (np->features & FE_WIDE)? 1 : 0;
3759
3760 /*
3761 * Guess the frequency of the chip's clock.
3762 */
3763 if (np->features & FE_ULTRA)
3764 np->clock_khz = 80000;
3765 else
3766 np->clock_khz = 40000;
3767
3768 /*
3769 * Get the clock multiplier factor.
3770 */
3771 if (np->features & FE_QUAD)
3772 np->multiplier = 4;
3773 else if (np->features & FE_DBLR)
3774 np->multiplier = 2;
3775 else
3776 np->multiplier = 1;
3777
3778 /*
3779 * Measure SCSI clock frequency for chips
3780 * it may vary from assumed one.
3781 */
3782 if (np->features & FE_VARCLK)
3783 ncr_getclock(np, np->multiplier);
3784
3785 /*
3786 * Divisor to be used for async (timer pre-scaler).
3787 */
3788 i = np->clock_divn - 1;
3789 while (--i >= 0) {
3790 if (10ul * SCSI_NCR_MIN_ASYNC * np->clock_khz > div_10M[i]) {
3791 ++i;
3792 break;
3793 }
3794 }
3795 np->rv_scntl3 = i+1;
3796
3797 /*
3798 * Minimum synchronous period factor supported by the chip.
3799 * Btw, 'period' is in tenths of nanoseconds.
3800 */
3801
3802 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz;
3803 if (period <= 250) np->minsync = 10;
3804 else if (period <= 303) np->minsync = 11;
3805 else if (period <= 500) np->minsync = 12;
3806 else np->minsync = (period + 40 - 1) / 40;
3807
3808 /*
3809 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2).
3810 */
3811
3812 if (np->minsync < 25 && !(np->features & FE_ULTRA))
3813 np->minsync = 25;
3814
3815 /*
3816 * Maximum synchronous period factor supported by the chip.
3817 */
3818
3819 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz);
3820 np->maxsync = period > 2540 ? 254 : period / 10;
3821
3822 /*
3823 ** Prepare initial value of other IO registers
3824 */
3825#if defined SCSI_NCR_TRUST_BIOS_SETTING
3826 np->rv_scntl0 = np->sv_scntl0;
3827 np->rv_dmode = np->sv_dmode;
3828 np->rv_dcntl = np->sv_dcntl;
3829 np->rv_ctest0 = np->sv_ctest0;
3830 np->rv_ctest3 = np->sv_ctest3;
3831 np->rv_ctest4 = np->sv_ctest4;
3832 np->rv_ctest5 = np->sv_ctest5;
3833 burst_max = burst_code(np->sv_dmode, np->sv_ctest0);
3834#else
3835
3836 /*
3837 ** Select burst length (dwords)
3838 */
3839 burst_max = driver_setup.burst_max;
3840 if (burst_max == 255)
3841 burst_max = burst_code(np->sv_dmode, np->sv_ctest0);
3842 if (burst_max > 7)
3843 burst_max = 7;
3844 if (burst_max > np->maxburst)
3845 burst_max = np->maxburst;
3846
3847 /*
3848 ** Select all supported special features
3849 */
3850 if (np->features & FE_ERL)
3851 np->rv_dmode |= ERL; /* Enable Read Line */
3852 if (np->features & FE_BOF)
3853 np->rv_dmode |= BOF; /* Burst Opcode Fetch */
3854 if (np->features & FE_ERMP)
3855 np->rv_dmode |= ERMP; /* Enable Read Multiple */
3856 if (np->features & FE_PFEN)
3857 np->rv_dcntl |= PFEN; /* Prefetch Enable */
3858 if (np->features & FE_CLSE)
3859 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */
3860 if (np->features & FE_WRIE)
3861 np->rv_ctest3 |= WRIE; /* Write and Invalidate */
3862 if (np->features & FE_DFS)
3863 np->rv_ctest5 |= DFS; /* Dma Fifo Size */
3864 if (np->features & FE_MUX)
3865 np->rv_ctest4 |= MUX; /* Host bus multiplex mode */
3866 if (np->features & FE_EA)
3867 np->rv_dcntl |= EA; /* Enable ACK */
3868 if (np->features & FE_EHP)
3869 np->rv_ctest0 |= EHP; /* Even host parity */
3870
3871 /*
3872 ** Select some other
3873 */
3874 if (driver_setup.master_parity)
3875 np->rv_ctest4 |= MPEE; /* Master parity checking */
3876 if (driver_setup.scsi_parity)
3877 np->rv_scntl0 |= 0x0a; /* full arb., ena parity, par->ATN */
3878
3879 /*
3880 ** Get SCSI addr of host adapter (set by bios?).
3881 */
3882 if (np->myaddr == 255) {
3883 np->myaddr = INB(nc_scid) & 0x07;
3884 if (!np->myaddr)
3885 np->myaddr = SCSI_NCR_MYADDR;
3886 }
3887
3888#endif /* SCSI_NCR_TRUST_BIOS_SETTING */
3889
3890 /*
3891 * Prepare initial io register bits for burst length
3892 */
3893 ncr_init_burst(np, burst_max);
3894
3895 /*
3896 ** Set SCSI BUS mode.
3897 **
3898 ** - ULTRA2 chips (895/895A/896) report the current
3899 ** BUS mode through the STEST4 IO register.
3900 ** - For previous generation chips (825/825A/875),
3901 ** user has to tell us how to check against HVD,
3902 ** since a 100% safe algorithm is not possible.
3903 */
3904 np->scsi_mode = SMODE_SE;
3905 if (np->features & FE_DIFF) {
3906 switch(driver_setup.diff_support) {
3907 case 4: /* Trust previous settings if present, then GPIO3 */
3908 if (np->sv_scntl3) {
3909 if (np->sv_stest2 & 0x20)
3910 np->scsi_mode = SMODE_HVD;
3911 break;
3912 }
3913 case 3: /* SYMBIOS controllers report HVD through GPIO3 */
3914 if (INB(nc_gpreg) & 0x08)
3915 break;
3916 case 2: /* Set HVD unconditionally */
3917 np->scsi_mode = SMODE_HVD;
3918 case 1: /* Trust previous settings for HVD */
3919 if (np->sv_stest2 & 0x20)
3920 np->scsi_mode = SMODE_HVD;
3921 break;
3922 default:/* Don't care about HVD */
3923 break;
3924 }
3925 }
3926 if (np->scsi_mode == SMODE_HVD)
3927 np->rv_stest2 |= 0x20;
3928
3929 /*
3930 ** Set LED support from SCRIPTS.
3931 ** Ignore this feature for boards known to use a
3932 ** specific GPIO wiring and for the 895A or 896
3933 ** that drive the LED directly.
3934 ** Also probe initial setting of GPIO0 as output.
3935 */
3936 if ((driver_setup.led_pin) &&
3937 !(np->features & FE_LEDC) && !(np->sv_gpcntl & 0x01))
3938 np->features |= FE_LED0;
3939
3940 /*
3941 ** Set irq mode.
3942 */
3943 switch(driver_setup.irqm & 3) {
3944 case 2:
3945 np->rv_dcntl |= IRQM;
3946 break;
3947 case 1:
3948 np->rv_dcntl |= (np->sv_dcntl & IRQM);
3949 break;
3950 default:
3951 break;
3952 }
3953
3954 /*
3955 ** Configure targets according to driver setup.
3956 ** Allow to override sync, wide and NOSCAN from
3957 ** boot command line.
3958 */
3959 for (i = 0 ; i < MAX_TARGET ; i++) {
3960 struct tcb *tp = &np->target[i];
3961
3962 tp->usrsync = driver_setup.default_sync;
3963 tp->usrwide = driver_setup.max_wide;
3964 tp->usrtags = MAX_TAGS;
3965 tp->period = 0xffff;
3966 if (!driver_setup.disconnection)
3967 np->target[i].usrflag = UF_NODISC;
3968 }
3969
3970 /*
3971 ** Announce all that stuff to user.
3972 */
3973
3974 printk(KERN_INFO "%s: ID %d, Fast-%d%s%s\n", ncr_name(np),
3975 np->myaddr,
3976 np->minsync < 12 ? 40 : (np->minsync < 25 ? 20 : 10),
3977 (np->rv_scntl0 & 0xa) ? ", Parity Checking" : ", NO Parity",
3978 (np->rv_stest2 & 0x20) ? ", Differential" : "");
3979
3980 if (bootverbose > 1) {
3981 printk (KERN_INFO "%s: initial SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
3982 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
3983 ncr_name(np), np->sv_scntl3, np->sv_dmode, np->sv_dcntl,
3984 np->sv_ctest3, np->sv_ctest4, np->sv_ctest5);
3985
3986 printk (KERN_INFO "%s: final SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
3987 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
3988 ncr_name(np), np->rv_scntl3, np->rv_dmode, np->rv_dcntl,
3989 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5);
3990 }
3991
3992 if (bootverbose && np->paddr2)
3993 printk (KERN_INFO "%s: on-chip RAM at 0x%lx\n",
3994 ncr_name(np), np->paddr2);
3995}
3996
3997/*==========================================================
3998**
3999**
4000** Done SCSI commands list management.
4001**
4002** We donnot enter the scsi_done() callback immediately
4003** after a command has been seen as completed but we
4004** insert it into a list which is flushed outside any kind
4005** of driver critical section.
4006** This allows to do minimal stuff under interrupt and
4007** inside critical sections and to also avoid locking up
4008** on recursive calls to driver entry points under SMP.
4009** In fact, the only kernel point which is entered by the
4010** driver with a driver lock set is kmalloc(GFP_ATOMIC)
4011** that shall not reenter the driver under any circumstances,
4012** AFAIK.
4013**
4014**==========================================================
4015*/
4016static inline void ncr_queue_done_cmd(struct ncb *np, struct scsi_cmnd *cmd)
4017{
4018 unmap_scsi_data(np, cmd);
4019 cmd->host_scribble = (char *) np->done_list;
4020 np->done_list = cmd;
4021}
4022
4023static inline void ncr_flush_done_cmds(struct scsi_cmnd *lcmd)
4024{
4025 struct scsi_cmnd *cmd;
4026
4027 while (lcmd) {
4028 cmd = lcmd;
4029 lcmd = (struct scsi_cmnd *) cmd->host_scribble;
4030 cmd->scsi_done(cmd);
4031 }
4032}
4033
4034/*==========================================================
4035**
4036**
4037** Prepare the next negotiation message if needed.
4038**
4039** Fill in the part of message buffer that contains the
4040** negotiation and the nego_status field of the CCB.
4041** Returns the size of the message in bytes.
4042**
4043**
4044**==========================================================
4045*/
4046
4047
4048static int ncr_prepare_nego(struct ncb *np, struct ccb *cp, u_char *msgptr)
4049{
4050 struct tcb *tp = &np->target[cp->target];
4051 int msglen = 0;
4052 int nego = 0;
4053 struct scsi_target *starget = tp->starget;
4054
4055 /* negotiate wide transfers ? */
4056 if (!tp->widedone) {
4057 if (spi_support_wide(starget)) {
4058 nego = NS_WIDE;
4059 } else
4060 tp->widedone=1;
4061 }
4062
4063 /* negotiate synchronous transfers? */
4064 if (!nego && !tp->period) {
4065 if (spi_support_sync(starget)) {
4066 nego = NS_SYNC;
4067 } else {
4068 tp->period =0xffff;
4069 dev_info(&starget->dev, "target did not report SYNC.\n");
4070 }
4071 }
4072
4073 switch (nego) {
4074 case NS_SYNC:
6ea3c0b2
MW		 4075 msglen += spi_populate_sync_msg(msgptr + msglen,
4076 tp->maxoffs ? tp->minsync : 0, tp->maxoffs);
1da177e4
LT		 4077 break;
4078 case NS_WIDE:
6ea3c0b2 4079 msglen += spi_populate_width_msg(msgptr + msglen, tp->usrwide);
1da177e4
LT		 4080 break;
4081 }
4082
4083 cp->nego_status = nego;
4084
4085 if (nego) {
4086 tp->nego_cp = cp;
4087 if (DEBUG_FLAGS & DEBUG_NEGO) {
4088 ncr_print_msg(cp, nego == NS_WIDE ?
4089 "wide msgout":"sync_msgout", msgptr);
4090 }
4091 }
4092
4093 return msglen;
4094}
4095
4096
4097
4098/*==========================================================
4099**
4100**
4101** Start execution of a SCSI command.
4102** This is called from the generic SCSI driver.
4103**
4104**
4105**==========================================================
4106*/
4107static int ncr_queue_command (struct ncb *np, struct scsi_cmnd *cmd)
4108{
4109 struct scsi_device *sdev = cmd->device;
4110 struct tcb *tp = &np->target[sdev->id];
4111 struct lcb *lp = tp->lp[sdev->lun];
4112 struct ccb *cp;
4113
4114 int segments;
4115 u_char idmsg, *msgptr;
4116 u32 msglen;
4117 int direction;
4118 u32 lastp, goalp;
4119
4120 /*---------------------------------------------
4121 **
4122 ** Some shortcuts ...
4123 **
4124 **---------------------------------------------
4125 */
4126 if ((sdev->id == np->myaddr ) ||
4127 (sdev->id >= MAX_TARGET) ||
4128 (sdev->lun >= MAX_LUN )) {
4129 return(DID_BAD_TARGET);
4130 }
4131
4132 /*---------------------------------------------
4133 **
4134 ** Complete the 1st TEST UNIT READY command
4135 ** with error condition if the device is
4136 ** flagged NOSCAN, in order to speed up
4137 ** the boot.
4138 **
4139 **---------------------------------------------
4140 */
4141 if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12) &&
4142 (tp->usrflag & UF_NOSCAN)) {
4143 tp->usrflag &= ~UF_NOSCAN;
4144 return DID_BAD_TARGET;
4145 }
4146
4147 if (DEBUG_FLAGS & DEBUG_TINY) {
4148 PRINT_ADDR(cmd, "CMD=%x ", cmd->cmnd[0]);
4149 }
4150
4151 /*---------------------------------------------------
4152 **
4153 ** Assign a ccb / bind cmd.
4154 ** If resetting, shorten settle_time if necessary
4155 ** in order to avoid spurious timeouts.
4156 ** If resetting or no free ccb,
4157 ** insert cmd into the waiting list.
4158 **
4159 **----------------------------------------------------
4160 */
242f9dcb
JA		 4161 if (np->settle_time && cmd->request->timeout >= HZ) {
4162 u_long tlimit = jiffies + cmd->request->timeout - HZ;
f2be34a3 4163 if (time_after(np->settle_time, tlimit))
1da177e4
LT		 4164 np->settle_time = tlimit;
4165 }
4166
4167 if (np->settle_time || !(cp=ncr_get_ccb (np, cmd))) {
4168 insert_into_waiting_list(np, cmd);
4169 return(DID_OK);
4170 }
4171 cp->cmd = cmd;
4172
4173 /*----------------------------------------------------
4174 **
4175 ** Build the identify / tag / sdtr message
4176 **
4177 **----------------------------------------------------
4178 */
4179
b0dc1db1 4180 idmsg = IDENTIFY(0, sdev->lun);
1da177e4
LT		 4181
4182 if (cp ->tag != NO_TAG ||
4183 (cp != np->ccb && np->disc && !(tp->usrflag & UF_NODISC)))
4184 idmsg |= 0x40;
4185
4186 msgptr = cp->scsi_smsg;
4187 msglen = 0;
4188 msgptr[msglen++] = idmsg;
4189
4190 if (cp->tag != NO_TAG) {
4191 char order = np->order;
4192
4193 /*
4194 ** Force ordered tag if necessary to avoid timeouts
4195 ** and to preserve interactivity.
4196 */
f2be34a3 4197 if (lp && time_after(jiffies, lp->tags_stime)) {
1da177e4 4198 if (lp->tags_smap) {
b0dc1db1 4199 order = ORDERED_QUEUE_TAG;
1da177e4
LT		 4200 if ((DEBUG_FLAGS & DEBUG_TAGS)||bootverbose>2){
4201 PRINT_ADDR(cmd,
4202 "ordered tag forced.\n");
4203 }
4204 }
f2be34a3 4205 lp->tags_stime = jiffies + 3*HZ;
1da177e4
LT		 4206 lp->tags_smap = lp->tags_umap;
4207 }
4208
4209 if (order == 0) {
4210 /*
4211 ** Ordered write ops, unordered read ops.
4212 */
4213 switch (cmd->cmnd[0]) {
4214 case 0x08: /* READ_SMALL (6) */
4215 case 0x28: /* READ_BIG (10) */
4216 case 0xa8: /* READ_HUGE (12) */
b0dc1db1 4217 order = SIMPLE_QUEUE_TAG;
1da177e4
LT		 4218 break;
4219 default:
b0dc1db1 4220 order = ORDERED_QUEUE_TAG;
1da177e4
LT		 4221 }
4222 }
4223 msgptr[msglen++] = order;
4224 /*
4225 ** Actual tags are numbered 1,3,5,..2*MAXTAGS+1,
4226 ** since we may have to deal with devices that have
4227 ** problems with #TAG 0 or too great #TAG numbers.
4228 */
4229 msgptr[msglen++] = (cp->tag << 1) + 1;
4230 }
4231
4232 /*----------------------------------------------------
4233 **
4234 ** Build the data descriptors
4235 **
4236 **----------------------------------------------------
4237 */
4238
4239 direction = cmd->sc_data_direction;
4240 if (direction != DMA_NONE) {
4241 segments = ncr_scatter(np, cp, cp->cmd);
4242 if (segments < 0) {
4243 ncr_free_ccb(np, cp);
4244 return(DID_ERROR);
4245 }
4246 }
4247 else {
4248 cp->data_len = 0;
4249 segments = 0;
4250 }
4251
4252 /*---------------------------------------------------
4253 **
4254 ** negotiation required?
4255 **
4256 ** (nego_status is filled by ncr_prepare_nego())
4257 **
4258 **---------------------------------------------------
4259 */
4260
4261 cp->nego_status = 0;
4262
4263 if ((!tp->widedone || !tp->period) && !tp->nego_cp && lp) {
4264 msglen += ncr_prepare_nego (np, cp, msgptr + msglen);
4265 }
4266
4267 /*----------------------------------------------------
4268 **
4269 ** Determine xfer direction.
4270 **
4271 **----------------------------------------------------
4272 */
4273 if (!cp->data_len)
4274 direction = DMA_NONE;
4275
4276 /*
4277 ** If data direction is BIDIRECTIONAL, speculate FROM_DEVICE
4278 ** but prepare alternate pointers for TO_DEVICE in case
4279 ** of our speculation will be just wrong.
4280 ** SCRIPTS will swap values if needed.
4281 */
4282 switch(direction) {
4283 case DMA_BIDIRECTIONAL:
4284 case DMA_TO_DEVICE:
4285 goalp = NCB_SCRIPT_PHYS (np, data_out2) + 8;
4286 if (segments <= MAX_SCATTERL)
4287 lastp = goalp - 8 - (segments * 16);
4288 else {
4289 lastp = NCB_SCRIPTH_PHYS (np, hdata_out2);
4290 lastp -= (segments - MAX_SCATTERL) * 16;
4291 }
4292 if (direction != DMA_BIDIRECTIONAL)
4293 break;
4294 cp->phys.header.wgoalp = cpu_to_scr(goalp);
4295 cp->phys.header.wlastp = cpu_to_scr(lastp);
4296 /* fall through */
4297 case DMA_FROM_DEVICE:
4298 goalp = NCB_SCRIPT_PHYS (np, data_in2) + 8;
4299 if (segments <= MAX_SCATTERL)
4300 lastp = goalp - 8 - (segments * 16);
4301 else {
4302 lastp = NCB_SCRIPTH_PHYS (np, hdata_in2);
4303 lastp -= (segments - MAX_SCATTERL) * 16;
4304 }
4305 break;
4306 default:
4307 case DMA_NONE:
4308 lastp = goalp = NCB_SCRIPT_PHYS (np, no_data);
4309 break;
4310 }
4311
4312 /*
4313 ** Set all pointers values needed by SCRIPTS.
4314 ** If direction is unknown, start at data_io.
4315 */
4316 cp->phys.header.lastp = cpu_to_scr(lastp);
4317 cp->phys.header.goalp = cpu_to_scr(goalp);
4318
4319 if (direction == DMA_BIDIRECTIONAL)
4320 cp->phys.header.savep =
4321 cpu_to_scr(NCB_SCRIPTH_PHYS (np, data_io));
4322 else
4323 cp->phys.header.savep= cpu_to_scr(lastp);
4324
4325 /*
4326 ** Save the initial data pointer in order to be able
4327 ** to redo the command.
4328 */
4329 cp->startp = cp->phys.header.savep;
4330
4331 /*----------------------------------------------------
4332 **
4333 ** fill in ccb
4334 **
4335 **----------------------------------------------------
4336 **
4337 **
4338 ** physical -> virtual backlink
4339 ** Generic SCSI command
4340 */
4341
4342 /*
4343 ** Startqueue
4344 */
4345 cp->start.schedule.l_paddr = cpu_to_scr(NCB_SCRIPT_PHYS (np, select));
4346 cp->restart.schedule.l_paddr = cpu_to_scr(NCB_SCRIPT_PHYS (np, resel_dsa));
4347 /*
4348 ** select
4349 */
422c0d61 4350 cp->phys.select.sel_id = sdev_id(sdev);
1da177e4
LT		 4351 cp->phys.select.sel_scntl3 = tp->wval;
4352 cp->phys.select.sel_sxfer = tp->sval;
4353 /*
4354 ** message
4355 */
4356 cp->phys.smsg.addr = cpu_to_scr(CCB_PHYS (cp, scsi_smsg));
4357 cp->phys.smsg.size = cpu_to_scr(msglen);
4358
4359 /*
4360 ** command
4361 */
4362 memcpy(cp->cdb_buf, cmd->cmnd, min_t(int, cmd->cmd_len, sizeof(cp->cdb_buf)));
4363 cp->phys.cmd.addr = cpu_to_scr(CCB_PHYS (cp, cdb_buf[0]));
4364 cp->phys.cmd.size = cpu_to_scr(cmd->cmd_len);
4365
4366 /*
4367 ** status
4368 */
4369 cp->actualquirks = 0;
4370 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY;
4371 cp->scsi_status = S_ILLEGAL;
4372 cp->parity_status = 0;
4373
4374 cp->xerr_status = XE_OK;
4375#if 0
4376 cp->sync_status = tp->sval;
4377 cp->wide_status = tp->wval;
4378#endif
4379
4380 /*----------------------------------------------------
4381 **
4382 ** Critical region: start this job.
4383 **
4384 **----------------------------------------------------
4385 */
4386
4387 /* activate this job. */
4388 cp->magic = CCB_MAGIC;
4389
4390 /*
4391 ** insert next CCBs into start queue.
4392 ** 2 max at a time is enough to flush the CCB wait queue.
4393 */
4394 cp->auto_sense = 0;
4395 if (lp)
4396 ncr_start_next_ccb(np, lp, 2);
4397 else
4398 ncr_put_start_queue(np, cp);
4399
4400 /* Command is successfully queued. */
4401
4402 return DID_OK;
4403}
4404
4405
4406/*==========================================================
4407**
4408**
4409** Insert a CCB into the start queue and wake up the
4410** SCRIPTS processor.
4411**
4412**
4413**==========================================================
4414*/
4415
4416static void ncr_start_next_ccb(struct ncb *np, struct lcb *lp, int maxn)
4417{
4418 struct list_head *qp;
4419 struct ccb *cp;
4420
4421 if (lp->held_ccb)
4422 return;
4423
4424 while (maxn-- && lp->queuedccbs < lp->queuedepth) {
4425 qp = ncr_list_pop(&lp->wait_ccbq);
4426 if (!qp)
4427 break;
4428 ++lp->queuedccbs;
4429 cp = list_entry(qp, struct ccb, link_ccbq);
4430 list_add_tail(qp, &lp->busy_ccbq);
4431 lp->jump_ccb[cp->tag == NO_TAG ? 0 : cp->tag] =
4432 cpu_to_scr(CCB_PHYS (cp, restart));
4433 ncr_put_start_queue(np, cp);
4434 }
4435}
4436
4437static void ncr_put_start_queue(struct ncb *np, struct ccb *cp)
4438{
4439 u16 qidx;
4440
4441 /*
4442 ** insert into start queue.
4443 */
4444 if (!np->squeueput) np->squeueput = 1;
4445 qidx = np->squeueput + 2;
4446 if (qidx >= MAX_START + MAX_START) qidx = 1;
4447
4448 np->scripth->tryloop [qidx] = cpu_to_scr(NCB_SCRIPT_PHYS (np, idle));
4449 MEMORY_BARRIER();
4450 np->scripth->tryloop [np->squeueput] = cpu_to_scr(CCB_PHYS (cp, start));
4451
4452 np->squeueput = qidx;
4453 ++np->queuedccbs;
4454 cp->queued = 1;
4455
4456 if (DEBUG_FLAGS & DEBUG_QUEUE)
4457 printk ("%s: queuepos=%d.\n", ncr_name (np), np->squeueput);
4458
4459 /*
4460 ** Script processor may be waiting for reselect.
4461 ** Wake it up.
4462 */
4463 MEMORY_BARRIER();
4464 OUTB (nc_istat, SIGP);
4465}
4466
4467
4468static int ncr_reset_scsi_bus(struct ncb *np, int enab_int, int settle_delay)
4469{
4470 u32 term;
4471 int retv = 0;
4472
f2be34a3 4473 np->settle_time = jiffies + settle_delay * HZ;
1da177e4
LT		 4474
4475 if (bootverbose > 1)
4476 printk("%s: resetting, "
4477 "command processing suspended for %d seconds\n",
4478 ncr_name(np), settle_delay);
4479
4480 ncr_chip_reset(np, 100);
4481 udelay(2000); /* The 895 needs time for the bus mode to settle */
4482 if (enab_int)
4483 OUTW (nc_sien, RST);
4484 /*
4485 ** Enable Tolerant, reset IRQD if present and
4486 ** properly set IRQ mode, prior to resetting the bus.
4487 */
4488 OUTB (nc_stest3, TE);
4489 OUTB (nc_scntl1, CRST);
4490 udelay(200);
4491
4492 if (!driver_setup.bus_check)
4493 goto out;
4494 /*
4495 ** Check for no terminators or SCSI bus shorts to ground.
4496 ** Read SCSI data bus, data parity bits and control signals.
4497 ** We are expecting RESET to be TRUE and other signals to be
4498 ** FALSE.
4499 */
4500
4501 term = INB(nc_sstat0);
4502 term = ((term & 2) << 7) + ((term & 1) << 17); /* rst sdp0 */
4503 term |= ((INB(nc_sstat2) & 0x01) << 26) | /* sdp1 */
4504 ((INW(nc_sbdl) & 0xff) << 9) | /* d7-0 */
4505 ((INW(nc_sbdl) & 0xff00) << 10) | /* d15-8 */
4506 INB(nc_sbcl); /* req ack bsy sel atn msg cd io */
4507
4508 if (!(np->features & FE_WIDE))
4509 term &= 0x3ffff;
4510
4511 if (term != (2<<7)) {
4512 printk("%s: suspicious SCSI data while resetting the BUS.\n",
4513 ncr_name(np));
4514 printk("%s: %sdp0,d7-0,rst,req,ack,bsy,sel,atn,msg,c/d,i/o = "
4515 "0x%lx, expecting 0x%lx\n",
4516 ncr_name(np),
4517 (np->features & FE_WIDE) ? "dp1,d15-8," : "",
4518 (u_long)term, (u_long)(2<<7));
4519 if (driver_setup.bus_check == 1)
4520 retv = 1;
4521 }
4522out:
4523 OUTB (nc_scntl1, 0);
4524 return retv;
4525}
4526
4527/*
4528 * Start reset process.
4529 * If reset in progress do nothing.
4530 * The interrupt handler will reinitialize the chip.
4531 * The timeout handler will wait for settle_time before
4532 * clearing it and so resuming command processing.
4533 */
4534static void ncr_start_reset(struct ncb *np)
4535{
4536 if (!np->settle_time) {
4537 ncr_reset_scsi_bus(np, 1, driver_setup.settle_delay);
4538 }
4539}
4540
4541/*==========================================================
4542**
4543**
4544** Reset the SCSI BUS.
4545** This is called from the generic SCSI driver.
4546**
4547**
4548**==========================================================
4549*/
4550static int ncr_reset_bus (struct ncb *np, struct scsi_cmnd *cmd, int sync_reset)
4551{
4552/* struct scsi_device *device = cmd->device; */
4553 struct ccb *cp;
4554 int found;
4555
4556/*
4557 * Return immediately if reset is in progress.
4558 */
4559 if (np->settle_time) {
4560 return FAILED;
4561 }
4562/*
4563 * Start the reset process.
4564 * The script processor is then assumed to be stopped.
4565 * Commands will now be queued in the waiting list until a settle
4566 * delay of 2 seconds will be completed.
4567 */
4568 ncr_start_reset(np);
4569/*
4570 * First, look in the wakeup list
4571 */
4572 for (found=0, cp=np->ccb; cp; cp=cp->link_ccb) {
4573 /*
4574 ** look for the ccb of this command.
4575 */
4576 if (cp->host_status == HS_IDLE) continue;
4577 if (cp->cmd == cmd) {
4578 found = 1;
4579 break;
4580 }
4581 }
4582/*
4583 * Then, look in the waiting list
4584 */
4585 if (!found && retrieve_from_waiting_list(0, np, cmd))
4586 found = 1;
4587/*
4588 * Wake-up all awaiting commands with DID_RESET.
4589 */
4590 reset_waiting_list(np);
4591/*
4592 * Wake-up all pending commands with HS_RESET -> DID_RESET.
4593 */
4594 ncr_wakeup(np, HS_RESET);
4595/*
4596 * If the involved command was not in a driver queue, and the
4597 * scsi driver told us reset is synchronous, and the command is not
4598 * currently in the waiting list, complete it with DID_RESET status,
4599 * in order to keep it alive.
4600 */
4601 if (!found && sync_reset && !retrieve_from_waiting_list(0, np, cmd)) {
78adb2bc 4602 cmd->result = DID_RESET << 16;
1da177e4
LT		 4603 ncr_queue_done_cmd(np, cmd);
4604 }
4605
4606 return SUCCESS;
4607}
4608
4609#if 0 /* unused and broken.. */
4610/*==========================================================
4611**
4612**
4613** Abort an SCSI command.
4614** This is called from the generic SCSI driver.
4615**
4616**
4617**==========================================================
4618*/
4619static int ncr_abort_command (struct ncb *np, struct scsi_cmnd *cmd)
4620{
4621/* struct scsi_device *device = cmd->device; */
4622 struct ccb *cp;
4623 int found;
4624 int retv;
4625
4626/*
4627 * First, look for the scsi command in the waiting list
4628 */
4629 if (remove_from_waiting_list(np, cmd)) {
4630 cmd->result = ScsiResult(DID_ABORT, 0);
4631 ncr_queue_done_cmd(np, cmd);
4632 return SCSI_ABORT_SUCCESS;
4633 }
4634
4635/*
4636 * Then, look in the wakeup list
4637 */
4638 for (found=0, cp=np->ccb; cp; cp=cp->link_ccb) {
4639 /*
4640 ** look for the ccb of this command.
4641 */
4642 if (cp->host_status == HS_IDLE) continue;
4643 if (cp->cmd == cmd) {
4644 found = 1;
4645 break;
4646 }
4647 }
4648
4649 if (!found) {
4650 return SCSI_ABORT_NOT_RUNNING;
4651 }
4652
4653 if (np->settle_time) {
4654 return SCSI_ABORT_SNOOZE;
4655 }
4656
4657 /*
4658 ** If the CCB is active, patch schedule jumps for the
4659 ** script to abort the command.
4660 */
4661
4662 switch(cp->host_status) {
4663 case HS_BUSY:
4664 case HS_NEGOTIATE:
4665 printk ("%s: abort ccb=%p (cancel)\n", ncr_name (np), cp);
4666 cp->start.schedule.l_paddr =
4667 cpu_to_scr(NCB_SCRIPTH_PHYS (np, cancel));
4668 retv = SCSI_ABORT_PENDING;
4669 break;
4670 case HS_DISCONNECT:
4671 cp->restart.schedule.l_paddr =
4672 cpu_to_scr(NCB_SCRIPTH_PHYS (np, abort));
4673 retv = SCSI_ABORT_PENDING;
4674 break;
4675 default:
4676 retv = SCSI_ABORT_NOT_RUNNING;
4677 break;
4678
4679 }
4680
4681 /*
4682 ** If there are no requests, the script
4683 ** processor will sleep on SEL_WAIT_RESEL.
4684 ** Let's wake it up, since it may have to work.
4685 */
4686 OUTB (nc_istat, SIGP);
4687
4688 return retv;
4689}
4690#endif
4691
4692static void ncr_detach(struct ncb *np)
4693{
4694 struct ccb *cp;
4695 struct tcb *tp;
4696 struct lcb *lp;
4697 int target, lun;
4698 int i;
4699 char inst_name[16];
4700
4701 /* Local copy so we don't access np after freeing it! */
4702 strlcpy(inst_name, ncr_name(np), sizeof(inst_name));
4703
4704 printk("%s: releasing host resources\n", ncr_name(np));
4705
4706/*
4707** Stop the ncr_timeout process
4708** Set release_stage to 1 and wait that ncr_timeout() set it to 2.
4709*/
4710
4711#ifdef DEBUG_NCR53C8XX
4712 printk("%s: stopping the timer\n", ncr_name(np));
4713#endif
4714 np->release_stage = 1;
4715 for (i = 50 ; i && np->release_stage != 2 ; i--)
4716 mdelay(100);
4717 if (np->release_stage != 2)
4718 printk("%s: the timer seems to be already stopped\n", ncr_name(np));
4719 else np->release_stage = 2;
4720
4721/*
4722** Disable chip interrupts
4723*/
4724
4725#ifdef DEBUG_NCR53C8XX
4726 printk("%s: disabling chip interrupts\n", ncr_name(np));
4727#endif
4728 OUTW (nc_sien , 0);
4729 OUTB (nc_dien , 0);
4730
4731 /*
4732 ** Reset NCR chip
4733 ** Restore bios setting for automatic clock detection.
4734 */
4735
4736 printk("%s: resetting chip\n", ncr_name(np));
4737 ncr_chip_reset(np, 100);
4738
4739 OUTB(nc_dmode, np->sv_dmode);
4740 OUTB(nc_dcntl, np->sv_dcntl);
4741 OUTB(nc_ctest0, np->sv_ctest0);
4742 OUTB(nc_ctest3, np->sv_ctest3);
4743 OUTB(nc_ctest4, np->sv_ctest4);
4744 OUTB(nc_ctest5, np->sv_ctest5);
4745 OUTB(nc_gpcntl, np->sv_gpcntl);
4746 OUTB(nc_stest2, np->sv_stest2);
4747
4748 ncr_selectclock(np, np->sv_scntl3);
4749
4750 /*
4751 ** Free allocated ccb(s)
4752 */
4753
4754 while ((cp=np->ccb->link_ccb) != NULL) {
4755 np->ccb->link_ccb = cp->link_ccb;
4756 if (cp->host_status) {
4757 printk("%s: shall free an active ccb (host_status=%d)\n",
4758 ncr_name(np), cp->host_status);
4759 }
4760#ifdef DEBUG_NCR53C8XX
4761 printk("%s: freeing ccb (%lx)\n", ncr_name(np), (u_long) cp);
4762#endif
4763 m_free_dma(cp, sizeof(*cp), "CCB");
4764 }
4765
4766 /* Free allocated tp(s) */
4767
4768 for (target = 0; target < MAX_TARGET ; target++) {
4769 tp=&np->target[target];
4770 for (lun = 0 ; lun < MAX_LUN ; lun++) {
4771 lp = tp->lp[lun];
4772 if (lp) {
4773#ifdef DEBUG_NCR53C8XX
4774 printk("%s: freeing lp (%lx)\n", ncr_name(np), (u_long) lp);
4775#endif
4776 if (lp->jump_ccb != &lp->jump_ccb_0)
4777 m_free_dma(lp->jump_ccb,256,"JUMP_CCB");
4778 m_free_dma(lp, sizeof(*lp), "LCB");
4779 }
4780 }
4781 }
4782
4783 if (np->scripth0)
4784 m_free_dma(np->scripth0, sizeof(struct scripth), "SCRIPTH");
4785 if (np->script0)
4786 m_free_dma(np->script0, sizeof(struct script), "SCRIPT");
4787 if (np->ccb)
4788 m_free_dma(np->ccb, sizeof(struct ccb), "CCB");
4789 m_free_dma(np, sizeof(struct ncb), "NCB");
4790
4791 printk("%s: host resources successfully released\n", inst_name);
4792}
4793
4794/*==========================================================
4795**
4796**
4797** Complete execution of a SCSI command.
4798** Signal completion to the generic SCSI driver.
4799**
4800**
4801**==========================================================
4802*/
4803
4804void ncr_complete (struct ncb *np, struct ccb *cp)
4805{
4806 struct scsi_cmnd *cmd;
4807 struct tcb *tp;
4808 struct lcb *lp;
4809
4810 /*
4811 ** Sanity check
4812 */
4813
4814 if (!cp || cp->magic != CCB_MAGIC || !cp->cmd)
4815 return;
4816
4817 /*
4818 ** Print minimal debug information.
4819 */
4820
4821 if (DEBUG_FLAGS & DEBUG_TINY)
4822 printk ("CCB=%lx STAT=%x/%x\n", (unsigned long)cp,
4823 cp->host_status,cp->scsi_status);
4824
4825 /*
4826 ** Get command, target and lun pointers.
4827 */
4828
4829 cmd = cp->cmd;
4830 cp->cmd = NULL;
4831 tp = &np->target[cmd->device->id];
4832 lp = tp->lp[cmd->device->lun];
4833
4834 /*
4835 ** We donnot queue more than 1 ccb per target
4836 ** with negotiation at any time. If this ccb was
4837 ** used for negotiation, clear this info in the tcb.
4838 */
4839
4840 if (cp == tp->nego_cp)
4841 tp->nego_cp = NULL;
4842
4843 /*
4844 ** If auto-sense performed, change scsi status.
4845 */
4846 if (cp->auto_sense) {
4847 cp->scsi_status = cp->auto_sense;
4848 }
4849
4850 /*
4851 ** If we were recovering from queue full or performing
4852 ** auto-sense, requeue skipped CCBs to the wait queue.
4853 */
4854
4855 if (lp && lp->held_ccb) {
4856 if (cp == lp->held_ccb) {
4857 list_splice_init(&lp->skip_ccbq, &lp->wait_ccbq);
4858 lp->held_ccb = NULL;
4859 }
4860 }
4861
4862 /*
4863 ** Check for parity errors.
4864 */
4865
4866 if (cp->parity_status > 1) {
4867 PRINT_ADDR(cmd, "%d parity error(s).\n",cp->parity_status);
4868 }
4869
4870 /*
4871 ** Check for extended errors.
4872 */
4873
4874 if (cp->xerr_status != XE_OK) {
4875 switch (cp->xerr_status) {
4876 case XE_EXTRA_DATA:
4877 PRINT_ADDR(cmd, "extraneous data discarded.\n");
4878 break;
4879 case XE_BAD_PHASE:
4880 PRINT_ADDR(cmd, "invalid scsi phase (4/5).\n");
4881 break;
4882 default:
4883 PRINT_ADDR(cmd, "extended error %d.\n",
4884 cp->xerr_status);
4885 break;
4886 }
4887 if (cp->host_status==HS_COMPLETE)
4888 cp->host_status = HS_FAIL;
4889 }
4890
4891 /*
4892 ** Print out any error for debugging purpose.
4893 */
4894 if (DEBUG_FLAGS & (DEBUG_RESULT|DEBUG_TINY)) {
4895 if (cp->host_status!=HS_COMPLETE || cp->scsi_status!=S_GOOD) {
4896 PRINT_ADDR(cmd, "ERROR: cmd=%x host_status=%x "
4897 "scsi_status=%x\n", cmd->cmnd[0],
4898 cp->host_status, cp->scsi_status);
4899 }
4900 }
4901
4902 /*
4903 ** Check the status.
4904 */
4905 if ( (cp->host_status == HS_COMPLETE)
4906 && (cp->scsi_status == S_GOOD ||
4907 cp->scsi_status == S_COND_MET)) {
4908 /*
4909 * All went well (GOOD status).
4910 * CONDITION MET status is returned on
4911 * `Pre-Fetch' or `Search data' success.
4912 */
4913 cmd->result = ScsiResult(DID_OK, cp->scsi_status);
4914
4915 /*
4916 ** @RESID@
4917 ** Could dig out the correct value for resid,
4918 ** but it would be quite complicated.
4919 */
4920 /* if (cp->phys.header.lastp != cp->phys.header.goalp) */
4921
4922 /*
4923 ** Allocate the lcb if not yet.
4924 */
4925 if (!lp)
4926 ncr_alloc_lcb (np, cmd->device->id, cmd->device->lun);
4927
4928 tp->bytes += cp->data_len;
4929 tp->transfers ++;
4930
4931 /*
4932 ** If tags was reduced due to queue full,
4933 ** increase tags if 1000 good status received.
4934 */
4935 if (lp && lp->usetags && lp->numtags < lp->maxtags) {
4936 ++lp->num_good;
4937 if (lp->num_good >= 1000) {
4938 lp->num_good = 0;
4939 ++lp->numtags;
4940 ncr_setup_tags (np, cmd->device);
4941 }
4942 }
4943 } else if ((cp->host_status == HS_COMPLETE)
4944 && (cp->scsi_status == S_CHECK_COND)) {
4945 /*
4946 ** Check condition code
4947 */
78adb2bc 4948 cmd->result = DID_OK << 16 | S_CHECK_COND;
1da177e4
LT		 4949
4950 /*
4951 ** Copy back sense data to caller's buffer.
4952 */
4953 memcpy(cmd->sense_buffer, cp->sense_buf,
b80ca4f7
FT		 4954 min_t(size_t, SCSI_SENSE_BUFFERSIZE,
4955 sizeof(cp->sense_buf)));
1da177e4
LT		 4956
4957 if (DEBUG_FLAGS & (DEBUG_RESULT|DEBUG_TINY)) {
149d6baf 4958 u_char *p = cmd->sense_buffer;
1da177e4
LT		 4959 int i;
4960 PRINT_ADDR(cmd, "sense data:");
4961 for (i=0; i<14; i++) printk (" %x", *p++);
4962 printk (".\n");
4963 }
4964 } else if ((cp->host_status == HS_COMPLETE)
4965 && (cp->scsi_status == S_CONFLICT)) {
4966 /*
4967 ** Reservation Conflict condition code
4968 */
78adb2bc 4969 cmd->result = DID_OK << 16 | S_CONFLICT;
1da177e4
LT		 4970
4971 } else if ((cp->host_status == HS_COMPLETE)
4972 && (cp->scsi_status == S_BUSY ||
4973 cp->scsi_status == S_QUEUE_FULL)) {
4974
4975 /*
4976 ** Target is busy.
4977 */
4978 cmd->result = ScsiResult(DID_OK, cp->scsi_status);
4979
4980 } else if ((cp->host_status == HS_SEL_TIMEOUT)
4981 || (cp->host_status == HS_TIMEOUT)) {
4982
4983 /*
4984 ** No response
4985 */
4986 cmd->result = ScsiResult(DID_TIME_OUT, cp->scsi_status);
4987
4988 } else if (cp->host_status == HS_RESET) {
4989
4990 /*
4991 ** SCSI bus reset
4992 */
4993 cmd->result = ScsiResult(DID_RESET, cp->scsi_status);
4994
4995 } else if (cp->host_status == HS_ABORTED) {
4996
4997 /*
4998 ** Transfer aborted
4999 */
5000 cmd->result = ScsiResult(DID_ABORT, cp->scsi_status);
5001
5002 } else {
5003
5004 /*
5005 ** Other protocol messes
5006 */
5007 PRINT_ADDR(cmd, "COMMAND FAILED (%x %x) @%p.\n",
5008 cp->host_status, cp->scsi_status, cp);
5009
5010 cmd->result = ScsiResult(DID_ERROR, cp->scsi_status);
5011 }
5012
5013 /*
5014 ** trace output
5015 */
5016
5017 if (tp->usrflag & UF_TRACE) {
5018 u_char * p;
5019 int i;
5020 PRINT_ADDR(cmd, " CMD:");
5021 p = (u_char*) &cmd->cmnd[0];
5022 for (i=0; i<cmd->cmd_len; i++) printk (" %x", *p++);
5023
5024 if (cp->host_status==HS_COMPLETE) {
5025 switch (cp->scsi_status) {
5026 case S_GOOD:
5027 printk (" GOOD");
5028 break;
5029 case S_CHECK_COND:
5030 printk (" SENSE:");
5031 p = (u_char*) &cmd->sense_buffer;
5032 for (i=0; i<14; i++)
5033 printk (" %x", *p++);
5034 break;
5035 default:
5036 printk (" STAT: %x\n", cp->scsi_status);
5037 break;
5038 }
5039 } else printk (" HOSTERROR: %x", cp->host_status);
5040 printk ("\n");
5041 }
5042
5043 /*
5044 ** Free this ccb
5045 */
5046 ncr_free_ccb (np, cp);
5047
5048 /*
5049 ** requeue awaiting scsi commands for this lun.
5050 */
5051 if (lp && lp->queuedccbs < lp->queuedepth &&
5052 !list_empty(&lp->wait_ccbq))
5053 ncr_start_next_ccb(np, lp, 2);
5054
5055 /*
5056 ** requeue awaiting scsi commands for this controller.
5057 */
5058 if (np->waiting_list)
5059 requeue_waiting_list(np);
5060
5061 /*
5062 ** signal completion to generic driver.
5063 */
5064 ncr_queue_done_cmd(np, cmd);
5065}
5066
5067/*==========================================================
5068**
5069**
5070** Signal all (or one) control block done.
5071**
5072**
5073**==========================================================
5074*/
5075
5076/*
5077** This CCB has been skipped by the NCR.
0779bf2d 5078** Queue it in the corresponding unit queue.
1da177e4
LT		 5079*/
5080static void ncr_ccb_skipped(struct ncb *np, struct ccb *cp)
5081{
5082 struct tcb *tp = &np->target[cp->target];
5083 struct lcb *lp = tp->lp[cp->lun];
5084
5085 if (lp && cp != np->ccb) {
5086 cp->host_status &= ~HS_SKIPMASK;
5087 cp->start.schedule.l_paddr =
5088 cpu_to_scr(NCB_SCRIPT_PHYS (np, select));
179e0917 5089 list_move_tail(&cp->link_ccbq, &lp->skip_ccbq);
1da177e4
LT		 5090 if (cp->queued) {
5091 --lp->queuedccbs;
5092 }
5093 }
5094 if (cp->queued) {
5095 --np->queuedccbs;
5096 cp->queued = 0;
5097 }
5098}
5099
5100/*
5101** The NCR has completed CCBs.
5102** Look at the DONE QUEUE if enabled, otherwise scan all CCBs
5103*/
5104void ncr_wakeup_done (struct ncb *np)
5105{
5106 struct ccb *cp;
5107#ifdef SCSI_NCR_CCB_DONE_SUPPORT
5108 int i, j;
5109
5110 i = np->ccb_done_ic;
5111 while (1) {
5112 j = i+1;
5113 if (j >= MAX_DONE)
5114 j = 0;
5115
5116 cp = np->ccb_done[j];
5117 if (!CCB_DONE_VALID(cp))
5118 break;
5119
5120 np->ccb_done[j] = (struct ccb *)CCB_DONE_EMPTY;
5121 np->scripth->done_queue[5*j + 4] =
5122 cpu_to_scr(NCB_SCRIPT_PHYS (np, done_plug));
5123 MEMORY_BARRIER();
5124 np->scripth->done_queue[5*i + 4] =
5125 cpu_to_scr(NCB_SCRIPT_PHYS (np, done_end));
5126
5127 if (cp->host_status & HS_DONEMASK)
5128 ncr_complete (np, cp);
5129 else if (cp->host_status & HS_SKIPMASK)
5130 ncr_ccb_skipped (np, cp);
5131
5132 i = j;
5133 }
5134 np->ccb_done_ic = i;
5135#else
5136 cp = np->ccb;
5137 while (cp) {
5138 if (cp->host_status & HS_DONEMASK)
5139 ncr_complete (np, cp);
5140 else if (cp->host_status & HS_SKIPMASK)
5141 ncr_ccb_skipped (np, cp);
5142 cp = cp->link_ccb;
5143 }
5144#endif
5145}
5146
5147/*
5148** Complete all active CCBs.
5149*/
5150void ncr_wakeup (struct ncb *np, u_long code)
5151{
5152 struct ccb *cp = np->ccb;
5153
5154 while (cp) {
5155 if (cp->host_status != HS_IDLE) {
5156 cp->host_status = code;
5157 ncr_complete (np, cp);
5158 }
5159 cp = cp->link_ccb;
5160 }
5161}
5162
5163/*
5164** Reset ncr chip.
5165*/
5166
5167/* Some initialisation must be done immediately following reset, for 53c720,
5168 * at least. EA (dcntl bit 5) isn't set here as it is set once only in
5169 * the _detect function.
5170 */
5171static void ncr_chip_reset(struct ncb *np, int delay)
5172{
5173 OUTB (nc_istat, SRST);
5174 udelay(delay);
5175 OUTB (nc_istat, 0 );
5176
5177 if (np->features & FE_EHP)
5178 OUTB (nc_ctest0, EHP);
5179 if (np->features & FE_MUX)
5180 OUTB (nc_ctest4, MUX);
5181}
5182
5183
5184/*==========================================================
5185**
5186**
5187** Start NCR chip.
5188**
5189**
5190**==========================================================
5191*/
5192
5193void ncr_init (struct ncb *np, int reset, char * msg, u_long code)
5194{
5195 int i;
5196
5197 /*
5198 ** Reset chip if asked, otherwise just clear fifos.
5199 */
5200
5201 if (reset) {
5202 OUTB (nc_istat, SRST);
5203 udelay(100);
5204 }
5205 else {
5206 OUTB (nc_stest3, TE|CSF);
5207 OUTONB (nc_ctest3, CLF);
5208 }
5209
5210 /*
5211 ** Message.
5212 */
5213
5214 if (msg) printk (KERN_INFO "%s: restart (%s).\n", ncr_name (np), msg);
5215
5216 /*
5217 ** Clear Start Queue
5218 */
5219 np->queuedepth = MAX_START - 1; /* 1 entry needed as end marker */
5220 for (i = 1; i < MAX_START + MAX_START; i += 2)
5221 np->scripth0->tryloop[i] =
5222 cpu_to_scr(NCB_SCRIPT_PHYS (np, idle));
5223
5224 /*
5225 ** Start at first entry.
5226 */
5227 np->squeueput = 0;
5228 np->script0->startpos[0] = cpu_to_scr(NCB_SCRIPTH_PHYS (np, tryloop));
5229
5230#ifdef SCSI_NCR_CCB_DONE_SUPPORT
5231 /*
5232 ** Clear Done Queue
5233 */
5234 for (i = 0; i < MAX_DONE; i++) {
5235 np->ccb_done[i] = (struct ccb *)CCB_DONE_EMPTY;
5236 np->scripth0->done_queue[5*i + 4] =
5237 cpu_to_scr(NCB_SCRIPT_PHYS (np, done_end));
5238 }
5239#endif
5240
5241 /*
5242 ** Start at first entry.
5243 */
5244 np->script0->done_pos[0] = cpu_to_scr(NCB_SCRIPTH_PHYS (np,done_queue));
5245 np->ccb_done_ic = MAX_DONE-1;
5246 np->scripth0->done_queue[5*(MAX_DONE-1) + 4] =
5247 cpu_to_scr(NCB_SCRIPT_PHYS (np, done_plug));
5248
5249 /*
5250 ** Wakeup all pending jobs.
5251 */
5252 ncr_wakeup (np, code);
5253
5254 /*
5255 ** Init chip.
5256 */
5257
5258 /*
5259 ** Remove reset; big delay because the 895 needs time for the
5260 ** bus mode to settle
5261 */
5262 ncr_chip_reset(np, 2000);
5263
5264 OUTB (nc_scntl0, np->rv_scntl0 | 0xc0);
5265 /* full arb., ena parity, par->ATN */
5266 OUTB (nc_scntl1, 0x00); /* odd parity, and remove CRST!! */
5267
5268 ncr_selectclock(np, np->rv_scntl3); /* Select SCSI clock */
5269
5270 OUTB (nc_scid , RRE|np->myaddr); /* Adapter SCSI address */
5271 OUTW (nc_respid, 1ul<<np->myaddr); /* Id to respond to */
5272 OUTB (nc_istat , SIGP ); /* Signal Process */
5273 OUTB (nc_dmode , np->rv_dmode); /* Burst length, dma mode */
5274 OUTB (nc_ctest5, np->rv_ctest5); /* Large fifo + large burst */
5275
5276 OUTB (nc_dcntl , NOCOM|np->rv_dcntl); /* Protect SFBR */
5277 OUTB (nc_ctest0, np->rv_ctest0); /* 720: CDIS and EHP */
5278 OUTB (nc_ctest3, np->rv_ctest3); /* Write and invalidate */
5279 OUTB (nc_ctest4, np->rv_ctest4); /* Master parity checking */
5280
5281 OUTB (nc_stest2, EXT|np->rv_stest2); /* Extended Sreq/Sack filtering */
5282 OUTB (nc_stest3, TE); /* TolerANT enable */
5283 OUTB (nc_stime0, 0x0c ); /* HTH disabled STO 0.25 sec */
5284
5285 /*
5286 ** Disable disconnects.
5287 */
5288
5289 np->disc = 0;
5290
5291 /*
5292 ** Enable GPIO0 pin for writing if LED support.
5293 */
5294
5295 if (np->features & FE_LED0) {
5296 OUTOFFB (nc_gpcntl, 0x01);
5297 }
5298
5299 /*
5300 ** enable ints
5301 */
5302
5303 OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR);
5304 OUTB (nc_dien , MDPE|BF|ABRT|SSI|SIR|IID);
5305
5306 /*
5307 ** Fill in target structure.
5308 ** Reinitialize usrsync.
5309 ** Reinitialize usrwide.
5310 ** Prepare sync negotiation according to actual SCSI bus mode.
5311 */
5312
5313 for (i=0;i<MAX_TARGET;i++) {
5314 struct tcb *tp = &np->target[i];
5315
5316 tp->sval = 0;
5317 tp->wval = np->rv_scntl3;
5318
5319 if (tp->usrsync != 255) {
5320 if (tp->usrsync <= np->maxsync) {
5321 if (tp->usrsync < np->minsync) {
5322 tp->usrsync = np->minsync;
5323 }
5324 }
5325 else
5326 tp->usrsync = 255;
5327 }
5328
5329 if (tp->usrwide > np->maxwide)
5330 tp->usrwide = np->maxwide;
5331
5332 }
5333
5334 /*
5335 ** Start script processor.
5336 */
5337 if (np->paddr2) {
5338 if (bootverbose)
5339 printk ("%s: Downloading SCSI SCRIPTS.\n",
5340 ncr_name(np));
5341 OUTL (nc_scratcha, vtobus(np->script0));
5342 OUTL_DSP (NCB_SCRIPTH_PHYS (np, start_ram));
5343 }
5344 else
5345 OUTL_DSP (NCB_SCRIPT_PHYS (np, start));
5346}
5347
5348/*==========================================================
5349**
5350** Prepare the negotiation values for wide and
5351** synchronous transfers.
5352**
5353**==========================================================
5354*/
5355
5356static void ncr_negotiate (struct ncb* np, struct tcb* tp)
5357{
5358 /*
5359 ** minsync unit is 4ns !
5360 */
5361
5362 u_long minsync = tp->usrsync;
5363
5364 /*
5365 ** SCSI bus mode limit
5366 */
5367
5368 if (np->scsi_mode && np->scsi_mode == SMODE_SE) {
5369 if (minsync < 12) minsync = 12;
5370 }
5371
5372 /*
5373 ** our limit ..
5374 */
5375
5376 if (minsync < np->minsync)
5377 minsync = np->minsync;
5378
5379 /*
5380 ** divider limit
5381 */
5382
5383 if (minsync > np->maxsync)
5384 minsync = 255;
5385
5386 if (tp->maxoffs > np->maxoffs)
5387 tp->maxoffs = np->maxoffs;
5388
5389 tp->minsync = minsync;
5390 tp->maxoffs = (minsync<255 ? tp->maxoffs : 0);
5391
5392 /*
5393 ** period=0: has to negotiate sync transfer
5394 */
5395
5396 tp->period=0;
5397
5398 /*
5399 ** widedone=0: has to negotiate wide transfer
5400 */
5401 tp->widedone=0;
5402}
5403
5404/*==========================================================
5405**
5406** Get clock factor and sync divisor for a given
5407** synchronous factor period.
5408** Returns the clock factor (in sxfer) and scntl3
5409** synchronous divisor field.
5410**
5411**==========================================================
5412*/
5413
5414static void ncr_getsync(struct ncb *np, u_char sfac, u_char *fakp, u_char *scntl3p)
5415{
5416 u_long clk = np->clock_khz; /* SCSI clock frequency in kHz */
5417 int div = np->clock_divn; /* Number of divisors supported */
5418 u_long fak; /* Sync factor in sxfer */
5419 u_long per; /* Period in tenths of ns */
5420 u_long kpc; /* (per * clk) */
5421
5422 /*
5423 ** Compute the synchronous period in tenths of nano-seconds
5424 */
5425 if (sfac <= 10) per = 250;
5426 else if (sfac == 11) per = 303;
5427 else if (sfac == 12) per = 500;
5428 else per = 40 * sfac;
5429
5430 /*
5431 ** Look for the greatest clock divisor that allows an
5432 ** input speed faster than the period.
5433 */
5434 kpc = per * clk;
36c7b302 5435 while (--div > 0)
1da177e4
LT		 5436 if (kpc >= (div_10M[div] << 2)) break;
5437
5438 /*
5439 ** Calculate the lowest clock factor that allows an output
5440 ** speed not faster than the period.
5441 */
5442 fak = (kpc - 1) / div_10M[div] + 1;
5443
5444#if 0 /* This optimization does not seem very useful */
5445
5446 per = (fak * div_10M[div]) / clk;
5447
5448 /*
5449 ** Why not to try the immediate lower divisor and to choose
5450 ** the one that allows the fastest output speed ?
5451 ** We don't want input speed too much greater than output speed.
5452 */
5453 if (div >= 1 && fak < 8) {
5454 u_long fak2, per2;
5455 fak2 = (kpc - 1) / div_10M[div-1] + 1;
5456 per2 = (fak2 * div_10M[div-1]) / clk;
5457 if (per2 < per && fak2 <= 8) {
5458 fak = fak2;
5459 per = per2;
5460 --div;
5461 }
5462 }
5463#endif
5464
5465 if (fak < 4) fak = 4; /* Should never happen, too bad ... */
5466
5467 /*
5468 ** Compute and return sync parameters for the ncr
5469 */
5470 *fakp = fak - 4;
5471 *scntl3p = ((div+1) << 4) + (sfac < 25 ? 0x80 : 0);
5472}
5473
5474
5475/*==========================================================
5476**
5477** Set actual values, sync status and patch all ccbs of
5478** a target according to new sync/wide agreement.
5479**
5480**==========================================================
5481*/
5482
5483static void ncr_set_sync_wide_status (struct ncb *np, u_char target)
5484{
5485 struct ccb *cp;
5486 struct tcb *tp = &np->target[target];
5487
5488 /*
5489 ** set actual value and sync_status
5490 */
5491 OUTB (nc_sxfer, tp->sval);
5492 np->sync_st = tp->sval;
5493 OUTB (nc_scntl3, tp->wval);
5494 np->wide_st = tp->wval;
5495
5496 /*
5497 ** patch ALL ccbs of this target.
5498 */
5499 for (cp = np->ccb; cp; cp = cp->link_ccb) {
5500 if (!cp->cmd) continue;
422c0d61 5501 if (scmd_id(cp->cmd) != target) continue;
1da177e4
LT		 5502#if 0
5503 cp->sync_status = tp->sval;
5504 cp->wide_status = tp->wval;
5505#endif
5506 cp->phys.select.sel_scntl3 = tp->wval;
5507 cp->phys.select.sel_sxfer = tp->sval;
5508 }
5509}
5510
5511/*==========================================================
5512**
5513** Switch sync mode for current job and it's target
5514**
5515**==========================================================
5516*/
5517
5518static void ncr_setsync (struct ncb *np, struct ccb *cp, u_char scntl3, u_char sxfer)
5519{
5520 struct scsi_cmnd *cmd = cp->cmd;
5521 struct tcb *tp;
5522 u_char target = INB (nc_sdid) & 0x0f;
5523 u_char idiv;
5524
422c0d61 5525 BUG_ON(target != (scmd_id(cmd) & 0xf));
1da177e4
LT		 5526
5527 tp = &np->target[target];
5528
5529 if (!scntl3 || !(sxfer & 0x1f))
5530 scntl3 = np->rv_scntl3;
5531 scntl3 = (scntl3 & 0xf0) | (tp->wval & EWS) | (np->rv_scntl3 & 0x07);
5532
5533 /*
5534 ** Deduce the value of controller sync period from scntl3.
5535 ** period is in tenths of nano-seconds.
5536 */
5537
5538 idiv = ((scntl3 >> 4) & 0x7);
5539 if ((sxfer & 0x1f) && idiv)
5540 tp->period = (((sxfer>>5)+4)*div_10M[idiv-1])/np->clock_khz;
5541 else
5542 tp->period = 0xffff;
5543
5544 /* Stop there if sync parameters are unchanged */
5545 if (tp->sval == sxfer && tp->wval == scntl3)
5546 return;
5547 tp->sval = sxfer;
5548 tp->wval = scntl3;
5549
5550 if (sxfer & 0x01f) {
5551 /* Disable extended Sreq/Sack filtering */
5552 if (tp->period <= 2000)
5553 OUTOFFB(nc_stest2, EXT);
5554 }
5555
5556 spi_display_xfer_agreement(tp->starget);
5557
5558 /*
5559 ** set actual value and sync_status
5560 ** patch ALL ccbs of this target.
5561 */
5562 ncr_set_sync_wide_status(np, target);
5563}
5564
5565/*==========================================================
5566**
5567** Switch wide mode for current job and it's target
5568** SCSI specs say: a SCSI device that accepts a WDTR
5569** message shall reset the synchronous agreement to
5570** asynchronous mode.
5571**
5572**==========================================================
5573*/
5574
5575static void ncr_setwide (struct ncb *np, struct ccb *cp, u_char wide, u_char ack)
5576{
5577 struct scsi_cmnd *cmd = cp->cmd;
5578 u16 target = INB (nc_sdid) & 0x0f;
5579 struct tcb *tp;
5580 u_char scntl3;
5581 u_char sxfer;
5582
422c0d61 5583 BUG_ON(target != (scmd_id(cmd) & 0xf));
1da177e4
LT		 5584
5585 tp = &np->target[target];
5586 tp->widedone = wide+1;
5587 scntl3 = (tp->wval & (~EWS)) | (wide ? EWS : 0);
5588
5589 sxfer = ack ? 0 : tp->sval;
5590
5591 /*
5592 ** Stop there if sync/wide parameters are unchanged
5593 */
5594 if (tp->sval == sxfer && tp->wval == scntl3) return;
5595 tp->sval = sxfer;
5596 tp->wval = scntl3;
5597
5598 /*
5599 ** Bells and whistles ;-)
5600 */
5601 if (bootverbose >= 2) {
5602 dev_info(&cmd->device->sdev_target->dev, "WIDE SCSI %sabled.\n",
5603 (scntl3 & EWS) ? "en" : "dis");
5604 }
5605
5606 /*
5607 ** set actual value and sync_status
5608 ** patch ALL ccbs of this target.
5609 */
5610 ncr_set_sync_wide_status(np, target);
5611}
5612
5613/*==========================================================
5614**
5615** Switch tagged mode for a target.
5616**
5617**==========================================================
5618*/
5619
5620static void ncr_setup_tags (struct ncb *np, struct scsi_device *sdev)
5621{
5622 unsigned char tn = sdev->id, ln = sdev->lun;
5623 struct tcb *tp = &np->target[tn];
5624 struct lcb *lp = tp->lp[ln];
5625 u_char reqtags, maxdepth;
5626
5627 /*
5628 ** Just in case ...
5629 */
5630 if ((!tp) || (!lp) || !sdev)
5631 return;
5632
5633 /*
5634 ** If SCSI device queue depth is not yet set, leave here.
5635 */
5636 if (!lp->scdev_depth)
5637 return;
5638
5639 /*
5640 ** Donnot allow more tags than the SCSI driver can queue
5641 ** for this device.
5642 ** Donnot allow more tags than we can handle.
5643 */
5644 maxdepth = lp->scdev_depth;
5645 if (maxdepth > lp->maxnxs) maxdepth = lp->maxnxs;
5646 if (lp->maxtags > maxdepth) lp->maxtags = maxdepth;
5647 if (lp->numtags > maxdepth) lp->numtags = maxdepth;
5648
5649 /*
5650 ** only devices conformant to ANSI Version >= 2
5651 ** only devices capable of tagged commands
5652 ** only if enabled by user ..
5653 */
5654 if (sdev->tagged_supported && lp->numtags > 1) {
5655 reqtags = lp->numtags;
5656 } else {
5657 reqtags = 1;
5658 }
5659
5660 /*
5661 ** Update max number of tags
5662 */
5663 lp->numtags = reqtags;
5664 if (lp->numtags > lp->maxtags)
5665 lp->maxtags = lp->numtags;
5666
5667 /*
5668 ** If we want to switch tag mode, we must wait
5669 ** for no CCB to be active.
5670 */
5671 if (reqtags > 1 && lp->usetags) { /* Stay in tagged mode */
5672 if (lp->queuedepth == reqtags) /* Already announced */
5673 return;
5674 lp->queuedepth = reqtags;
5675 }
5676 else if (reqtags <= 1 && !lp->usetags) { /* Stay in untagged mode */
5677 lp->queuedepth = reqtags;
5678 return;
5679 }
5680 else { /* Want to switch tag mode */
5681 if (lp->busyccbs) /* If not yet safe, return */
5682 return;
5683 lp->queuedepth = reqtags;
5684 lp->usetags = reqtags > 1 ? 1 : 0;
5685 }
5686
5687 /*
5688 ** Patch the lun mini-script, according to tag mode.
5689 */
5690 lp->jump_tag.l_paddr = lp->usetags?
5691 cpu_to_scr(NCB_SCRIPT_PHYS(np, resel_tag)) :
5692 cpu_to_scr(NCB_SCRIPT_PHYS(np, resel_notag));
5693
5694 /*
5695 ** Announce change to user.
5696 */
5697 if (bootverbose) {
5698 if (lp->usetags) {
5699 dev_info(&sdev->sdev_gendev,
5700 "tagged command queue depth set to %d\n",
5701 reqtags);
5702 } else {
5703 dev_info(&sdev->sdev_gendev,
5704 "tagged command queueing disabled\n");
5705 }
5706 }
5707}
5708
5709/*==========================================================
5710**
5711**
5712** ncr timeout handler.
5713**
5714**
5715**==========================================================
5716**
5717** Misused to keep the driver running when
5718** interrupts are not configured correctly.
5719**
5720**----------------------------------------------------------
5721*/
5722
5723static void ncr_timeout (struct ncb *np)
5724{
f2be34a3 5725 u_long thistime = jiffies;
1da177e4
LT		 5726
5727 /*
5728 ** If release process in progress, let's go
5729 ** Set the release stage from 1 to 2 to synchronize
5730 ** with the release process.
5731 */
5732
5733 if (np->release_stage) {
5734 if (np->release_stage == 1) np->release_stage = 2;
5735 return;
5736 }
5737
f2be34a3 5738 np->timer.expires = jiffies + SCSI_NCR_TIMER_INTERVAL;
1da177e4
LT		 5739 add_timer(&np->timer);
5740
5741 /*
5742 ** If we are resetting the ncr, wait for settle_time before
5743 ** clearing it. Then command processing will be resumed.
5744 */
5745 if (np->settle_time) {
5746 if (np->settle_time <= thistime) {
5747 if (bootverbose > 1)
5748 printk("%s: command processing resumed\n", ncr_name(np));
5749 np->settle_time = 0;
5750 np->disc = 1;
5751 requeue_waiting_list(np);
5752 }
5753 return;
5754 }
5755
5756 /*
5757 ** Since the generic scsi driver only allows us 0.5 second
5758 ** to perform abort of a command, we must look at ccbs about
5759 ** every 0.25 second.
5760 */
5761 if (np->lasttime + 4*HZ < thistime) {
5762 /*
5763 ** block ncr interrupts
5764 */
5765 np->lasttime = thistime;
5766 }
5767
5768#ifdef SCSI_NCR_BROKEN_INTR
5769 if (INB(nc_istat) & (INTF|SIP|DIP)) {
5770
5771 /*
5772 ** Process pending interrupts.
5773 */
5774 if (DEBUG_FLAGS & DEBUG_TINY) printk ("{");
5775 ncr_exception (np);
5776 if (DEBUG_FLAGS & DEBUG_TINY) printk ("}");
5777 }
5778#endif /* SCSI_NCR_BROKEN_INTR */
5779}
5780
5781/*==========================================================
5782**
5783** log message for real hard errors
5784**
5785** "ncr0 targ 0?: ERROR (ds:si) (so-si-sd) (sxfer/scntl3) @ name (dsp:dbc)."
5786** " reg: r0 r1 r2 r3 r4 r5 r6 ..... rf."
5787**
5788** exception register:
5789** ds: dstat
5790** si: sist
5791**
5792** SCSI bus lines:
5793** so: control lines as driver by NCR.
5794** si: control lines as seen by NCR.
5795** sd: scsi data lines as seen by NCR.
5796**
5797** wide/fastmode:
5798** sxfer: (see the manual)
5799** scntl3: (see the manual)
5800**
5801** current script command:
5802** dsp: script address (relative to start of script).
5803** dbc: first word of script command.
5804**
5805** First 16 register of the chip:
5806** r0..rf
5807**
5808**==========================================================
5809*/
5810
5811static void ncr_log_hard_error(struct ncb *np, u16 sist, u_char dstat)
5812{
5813 u32 dsp;
5814 int script_ofs;
5815 int script_size;
5816 char *script_name;
5817 u_char *script_base;
5818 int i;
5819
5820 dsp = INL (nc_dsp);
5821
5822 if (dsp > np->p_script && dsp <= np->p_script + sizeof(struct script)) {
5823 script_ofs = dsp - np->p_script;
5824 script_size = sizeof(struct script);
5825 script_base = (u_char *) np->script0;
5826 script_name = "script";
5827 }
5828 else if (np->p_scripth < dsp &&
5829 dsp <= np->p_scripth + sizeof(struct scripth)) {
5830 script_ofs = dsp - np->p_scripth;
5831 script_size = sizeof(struct scripth);
5832 script_base = (u_char *) np->scripth0;
5833 script_name = "scripth";
5834 } else {
5835 script_ofs = dsp;
5836 script_size = 0;
5837 script_base = NULL;
5838 script_name = "mem";
5839 }
5840
5841 printk ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x) @ (%s %x:%08x).\n",
5842 ncr_name (np), (unsigned)INB (nc_sdid)&0x0f, dstat, sist,
5843 (unsigned)INB (nc_socl), (unsigned)INB (nc_sbcl), (unsigned)INB (nc_sbdl),
5844 (unsigned)INB (nc_sxfer),(unsigned)INB (nc_scntl3), script_name, script_ofs,
5845 (unsigned)INL (nc_dbc));
5846
5847 if (((script_ofs & 3) == 0) &&
5848 (unsigned)script_ofs < script_size) {
5849 printk ("%s: script cmd = %08x\n", ncr_name(np),
5850 scr_to_cpu((int) *(ncrcmd *)(script_base + script_ofs)));
5851 }
5852
5853 printk ("%s: regdump:", ncr_name(np));
5854 for (i=0; i<16;i++)
5855 printk (" %02x", (unsigned)INB_OFF(i));
5856 printk (".\n");
5857}
5858
5859/*============================================================
5860**
5861** ncr chip exception handler.
5862**
5863**============================================================
5864**
5865** In normal cases, interrupt conditions occur one at a
5866** time. The ncr is able to stack in some extra registers
0779bf2d
ML		 5867** other interrupts that will occur after the first one.
5868** But, several interrupts may occur at the same time.
1da177e4
LT		 5869**
5870** We probably should only try to deal with the normal
5871** case, but it seems that multiple interrupts occur in
5872** some cases that are not abnormal at all.
5873**
5874** The most frequent interrupt condition is Phase Mismatch.
5875** We should want to service this interrupt quickly.
5876** A SCSI parity error may be delivered at the same time.
5877** The SIR interrupt is not very frequent in this driver,
5878** since the INTFLY is likely used for command completion
5879** signaling.
5880** The Selection Timeout interrupt may be triggered with
5881** IID and/or UDC.
5882** The SBMC interrupt (SCSI Bus Mode Change) may probably
5883** occur at any time.
5884**
5885** This handler try to deal as cleverly as possible with all
5886** the above.
5887**
5888**============================================================
5889*/
5890
5891void ncr_exception (struct ncb *np)
5892{
5893 u_char istat, dstat;
5894 u16 sist;
5895 int i;
5896
5897 /*
5898 ** interrupt on the fly ?
5899 ** Since the global header may be copied back to a CCB
5900 ** using a posted PCI memory write, the last operation on
5901 ** the istat register is a READ in order to flush posted
5902 ** PCI write commands.
5903 */
5904 istat = INB (nc_istat);
5905 if (istat & INTF) {
5906 OUTB (nc_istat, (istat & SIGP) | INTF);
5907 istat = INB (nc_istat);
5908 if (DEBUG_FLAGS & DEBUG_TINY) printk ("F ");
5909 ncr_wakeup_done (np);
5910 }
5911
5912 if (!(istat & (SIP|DIP)))
5913 return;
5914
5915 if (istat & CABRT)
5916 OUTB (nc_istat, CABRT);
5917
5918 /*
5919 ** Steinbach's Guideline for Systems Programming:
5920 ** Never test for an error condition you don't know how to handle.
5921 */
5922
5923 sist = (istat & SIP) ? INW (nc_sist) : 0;
5924 dstat = (istat & DIP) ? INB (nc_dstat) : 0;
5925
5926 if (DEBUG_FLAGS & DEBUG_TINY)
5927 printk ("<%d|%x:%x|%x:%x>",
5928 (int)INB(nc_scr0),
5929 dstat,sist,
5930 (unsigned)INL(nc_dsp),
5931 (unsigned)INL(nc_dbc));
5932
5933 /*========================================================
5934 ** First, interrupts we want to service cleanly.
5935 **
5936 ** Phase mismatch is the most frequent interrupt, and
5937 ** so we have to service it as quickly and as cleanly
5938 ** as possible.
5939 ** Programmed interrupts are rarely used in this driver,
5940 ** but we must handle them cleanly anyway.
5941 ** We try to deal with PAR and SBMC combined with
5942 ** some other interrupt(s).
5943 **=========================================================
5944 */
5945
5946 if (!(sist & (STO|GEN|HTH|SGE|UDC|RST)) &&
5947 !(dstat & (MDPE|BF|ABRT|IID))) {
5948 if ((sist & SBMC) && ncr_int_sbmc (np))
5949 return;
5950 if ((sist & PAR) && ncr_int_par (np))
5951 return;
5952 if (sist & MA) {
5953 ncr_int_ma (np);
5954 return;
5955 }
5956 if (dstat & SIR) {
5957 ncr_int_sir (np);
5958 return;
5959 }
5960 /*
5961 ** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 2.
5962 */
5963 if (!(sist & (SBMC|PAR)) && !(dstat & SSI)) {
5964 printk( "%s: unknown interrupt(s) ignored, "
5965 "ISTAT=%x DSTAT=%x SIST=%x\n",
5966 ncr_name(np), istat, dstat, sist);
5967 return;
5968 }
5969 OUTONB_STD ();
5970 return;
5971 }
5972
5973 /*========================================================
5974 ** Now, interrupts that need some fixing up.
5975 ** Order and multiple interrupts is so less important.
5976 **
5977 ** If SRST has been asserted, we just reset the chip.
5978 **
5979 ** Selection is intirely handled by the chip. If the
5980 ** chip says STO, we trust it. Seems some other
5981 ** interrupts may occur at the same time (UDC, IID), so
5982 ** we ignore them. In any case we do enough fix-up
5983 ** in the service routine.
5984 ** We just exclude some fatal dma errors.
5985 **=========================================================
5986 */
5987
5988 if (sist & RST) {
5989 ncr_init (np, 1, bootverbose ? "scsi reset" : NULL, HS_RESET);
5990 return;
5991 }
5992
5993 if ((sist & STO) &&
5994 !(dstat & (MDPE|BF|ABRT))) {
5995 /*
5996 ** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 1.
5997 */
5998 OUTONB (nc_ctest3, CLF);
5999
6000 ncr_int_sto (np);
6001 return;
6002 }
6003
6004 /*=========================================================
6005 ** Now, interrupts we are not able to recover cleanly.
6006 ** (At least for the moment).
6007 **
6008 ** Do the register dump.
6009 ** Log message for real hard errors.
6010 ** Clear all fifos.
6011 ** For MDPE, BF, ABORT, IID, SGE and HTH we reset the
6012 ** BUS and the chip.
6013 ** We are more soft for UDC.
6014 **=========================================================
6015 */
6016
f2be34a3
MW		 6017 if (time_after(jiffies, np->regtime)) {
6018 np->regtime = jiffies + 10*HZ;
1da177e4
LT		 6019 for (i = 0; i<sizeof(np->regdump); i++)
6020 ((char*)&np->regdump)[i] = INB_OFF(i);
6021 np->regdump.nc_dstat = dstat;
6022 np->regdump.nc_sist = sist;
6023 }
6024
6025 ncr_log_hard_error(np, sist, dstat);
6026
6027 printk ("%s: have to clear fifos.\n", ncr_name (np));
6028 OUTB (nc_stest3, TE|CSF);
6029 OUTONB (nc_ctest3, CLF);
6030
6031 if ((sist & (SGE)) ||
6032 (dstat & (MDPE|BF|ABRT|IID))) {
6033 ncr_start_reset(np);
6034 return;
6035 }
6036
6037 if (sist & HTH) {
6038 printk ("%s: handshake timeout\n", ncr_name(np));
6039 ncr_start_reset(np);
6040 return;
6041 }
6042
6043 if (sist & UDC) {
6044 printk ("%s: unexpected disconnect\n", ncr_name(np));
6045 OUTB (HS_PRT, HS_UNEXPECTED);
6046 OUTL_DSP (NCB_SCRIPT_PHYS (np, cleanup));
6047 return;
6048 }
6049
6050 /*=========================================================
6051 ** We just miss the cause of the interrupt. :(
6052 ** Print a message. The timeout will do the real work.
6053 **=========================================================
6054 */
6055 printk ("%s: unknown interrupt\n", ncr_name(np));
6056}
6057
6058/*==========================================================
6059**
6060** ncr chip exception handler for selection timeout
6061**
6062**==========================================================
6063**
6064** There seems to be a bug in the 53c810.
6065** Although a STO-Interrupt is pending,
6066** it continues executing script commands.
6067** But it will fail and interrupt (IID) on
6068** the next instruction where it's looking
6069** for a valid phase.
6070**
6071**----------------------------------------------------------
6072*/
6073
6074void ncr_int_sto (struct ncb *np)
6075{
6076 u_long dsa;
6077 struct ccb *cp;
6078 if (DEBUG_FLAGS & DEBUG_TINY) printk ("T");
6079
6080 /*
6081 ** look for ccb and set the status.
6082 */
6083
6084 dsa = INL (nc_dsa);
6085 cp = np->ccb;
6086 while (cp && (CCB_PHYS (cp, phys) != dsa))
6087 cp = cp->link_ccb;
6088
6089 if (cp) {
6090 cp-> host_status = HS_SEL_TIMEOUT;
6091 ncr_complete (np, cp);
6092 }
6093
6094 /*
6095 ** repair start queue and jump to start point.
6096 */
6097
6098 OUTL_DSP (NCB_SCRIPTH_PHYS (np, sto_restart));
6099 return;
6100}
6101
6102/*==========================================================
6103**
6104** ncr chip exception handler for SCSI bus mode change
6105**
6106**==========================================================
6107**
6108** spi2-r12 11.2.3 says a transceiver mode change must
6109** generate a reset event and a device that detects a reset
6110** event shall initiate a hard reset. It says also that a
6111** device that detects a mode change shall set data transfer
6112** mode to eight bit asynchronous, etc...
6113** So, just resetting should be enough.
6114**
6115**
6116**----------------------------------------------------------
6117*/
6118
6119static int ncr_int_sbmc (struct ncb *np)
6120{
6121 u_char scsi_mode = INB (nc_stest4) & SMODE;
6122
6123 if (scsi_mode != np->scsi_mode) {
6124 printk("%s: SCSI bus mode change from %x to %x.\n",
6125 ncr_name(np), np->scsi_mode, scsi_mode);
6126
6127 np->scsi_mode = scsi_mode;
6128
6129
6130 /*
6131 ** Suspend command processing for 1 second and
6132 ** reinitialize all except the chip.
6133 */
f2be34a3 6134 np->settle_time = jiffies + HZ;
1da177e4
LT		 6135 ncr_init (np, 0, bootverbose ? "scsi mode change" : NULL, HS_RESET);
6136 return 1;
6137 }
6138 return 0;
6139}
6140
6141/*==========================================================
6142**
6143** ncr chip exception handler for SCSI parity error.
6144**
6145**==========================================================
6146**
6147**
6148**----------------------------------------------------------
6149*/
6150
6151static int ncr_int_par (struct ncb *np)
6152{
6153 u_char hsts = INB (HS_PRT);
6154 u32 dbc = INL (nc_dbc);
6155 u_char sstat1 = INB (nc_sstat1);
6156 int phase = -1;
6157 int msg = -1;
6158 u32 jmp;
6159
6160 printk("%s: SCSI parity error detected: SCR1=%d DBC=%x SSTAT1=%x\n",
6161 ncr_name(np), hsts, dbc, sstat1);
6162
6163 /*
6164 * Ignore the interrupt if the NCR is not connected
6165 * to the SCSI bus, since the right work should have
6166 * been done on unexpected disconnection handling.
6167 */
6168 if (!(INB (nc_scntl1) & ISCON))
6169 return 0;
6170
6171 /*
6172 * If the nexus is not clearly identified, reset the bus.
6173 * We will try to do better later.
6174 */
6175 if (hsts & HS_INVALMASK)
6176 goto reset_all;
6177
6178 /*
6179 * If the SCSI parity error occurs in MSG IN phase, prepare a
6180 * MSG PARITY message. Otherwise, prepare a INITIATOR DETECTED
6181 * ERROR message and let the device decide to retry the command
6182 * or to terminate with check condition. If we were in MSG IN
6183 * phase waiting for the response of a negotiation, we will
6184 * get SIR_NEGO_FAILED at dispatch.
6185 */
6186 if (!(dbc & 0xc0000000))
6187 phase = (dbc >> 24) & 7;
6188 if (phase == 7)
b0dc1db1 6189 msg = MSG_PARITY_ERROR;
1da177e4 6190 else
b0dc1db1 6191 msg = INITIATOR_ERROR;
1da177e4
LT		 6192
6193
6194 /*
6195 * If the NCR stopped on a MOVE ^ DATA_IN, we jump to a
6196 * script that will ignore all data in bytes until phase
6197 * change, since we are not sure the chip will wait the phase
6198 * change prior to delivering the interrupt.
6199 */
6200 if (phase == 1)
6201 jmp = NCB_SCRIPTH_PHYS (np, par_err_data_in);
6202 else
6203 jmp = NCB_SCRIPTH_PHYS (np, par_err_other);
6204
6205 OUTONB (nc_ctest3, CLF ); /* clear dma fifo */
6206 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */
6207
6208 np->msgout[0] = msg;
6209 OUTL_DSP (jmp);
6210 return 1;
6211
6212reset_all:
6213 ncr_start_reset(np);
6214 return 1;
6215}
6216
6217/*==========================================================
6218**
6219**
6220** ncr chip exception handler for phase errors.
6221**
6222**
6223**==========================================================
6224**
6225** We have to construct a new transfer descriptor,
6226** to transfer the rest of the current block.
6227**
6228**----------------------------------------------------------
6229*/
6230
6231static void ncr_int_ma (struct ncb *np)
6232{
6233 u32 dbc;
6234 u32 rest;
6235 u32 dsp;
6236 u32 dsa;
6237 u32 nxtdsp;
6238 u32 newtmp;
6239 u32 *vdsp;
6240 u32 oadr, olen;
6241 u32 *tblp;
6242 ncrcmd *newcmd;
6243 u_char cmd, sbcl;
6244 struct ccb *cp;
6245
6246 dsp = INL (nc_dsp);
6247 dbc = INL (nc_dbc);
6248 sbcl = INB (nc_sbcl);
6249
6250 cmd = dbc >> 24;
6251 rest = dbc & 0xffffff;
6252
6253 /*
6254 ** Take into account dma fifo and various buffers and latches,
6255 ** only if the interrupted phase is an OUTPUT phase.
6256 */
6257
6258 if ((cmd & 1) == 0) {
6259 u_char ctest5, ss0, ss2;
6260 u16 delta;
6261
6262 ctest5 = (np->rv_ctest5 & DFS) ? INB (nc_ctest5) : 0;
6263 if (ctest5 & DFS)
6264 delta=(((ctest5 << 8) | (INB (nc_dfifo) & 0xff)) - rest) & 0x3ff;
6265 else
6266 delta=(INB (nc_dfifo) - rest) & 0x7f;
6267
6268 /*
6269 ** The data in the dma fifo has not been transferred to
6270 ** the target -> add the amount to the rest
6271 ** and clear the data.
6272 ** Check the sstat2 register in case of wide transfer.
6273 */
6274
6275 rest += delta;
6276 ss0 = INB (nc_sstat0);
6277 if (ss0 & OLF) rest++;
6278 if (ss0 & ORF) rest++;
6279 if (INB(nc_scntl3) & EWS) {
6280 ss2 = INB (nc_sstat2);
6281 if (ss2 & OLF1) rest++;
6282 if (ss2 & ORF1) rest++;
6283 }
6284
6285 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE))
6286 printk ("P%x%x RL=%d D=%d SS0=%x ", cmd&7, sbcl&7,
6287 (unsigned) rest, (unsigned) delta, ss0);
6288
6289 } else {
6290 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE))
6291 printk ("P%x%x RL=%d ", cmd&7, sbcl&7, rest);
6292 }
6293
6294 /*
6295 ** Clear fifos.
6296 */
6297 OUTONB (nc_ctest3, CLF ); /* clear dma fifo */
6298 OUTB (nc_stest3, TE|CSF); /* clear scsi fifo */
6299
6300 /*
6301 ** locate matching cp.
6302 ** if the interrupted phase is DATA IN or DATA OUT,
6303 ** trust the global header.
6304 */
6305 dsa = INL (nc_dsa);
6306 if (!(cmd & 6)) {
6307 cp = np->header.cp;
6308 if (CCB_PHYS(cp, phys) != dsa)
6309 cp = NULL;
6310 } else {
6311 cp = np->ccb;
6312 while (cp && (CCB_PHYS (cp, phys) != dsa))
6313 cp = cp->link_ccb;
6314 }
6315
6316 /*
6317 ** try to find the interrupted script command,
6318 ** and the address at which to continue.
6319 */
6320 vdsp = NULL;
6321 nxtdsp = 0;
6322 if (dsp > np->p_script &&
6323 dsp <= np->p_script + sizeof(struct script)) {
6324 vdsp = (u32 *)((char*)np->script0 + (dsp-np->p_script-8));
6325 nxtdsp = dsp;
6326 }
6327 else if (dsp > np->p_scripth &&
6328 dsp <= np->p_scripth + sizeof(struct scripth)) {
6329 vdsp = (u32 *)((char*)np->scripth0 + (dsp-np->p_scripth-8));
6330 nxtdsp = dsp;
6331 }
6332 else if (cp) {
6333 if (dsp == CCB_PHYS (cp, patch[2])) {
6334 vdsp = &cp->patch[0];
6335 nxtdsp = scr_to_cpu(vdsp[3]);
6336 }
6337 else if (dsp == CCB_PHYS (cp, patch[6])) {
6338 vdsp = &cp->patch[4];
6339 nxtdsp = scr_to_cpu(vdsp[3]);
6340 }
6341 }
6342
6343 /*
6344 ** log the information
6345 */
6346
6347 if (DEBUG_FLAGS & DEBUG_PHASE) {
6348 printk ("\nCP=%p CP2=%p DSP=%x NXT=%x VDSP=%p CMD=%x ",
6349 cp, np->header.cp,
6350 (unsigned)dsp,
6351 (unsigned)nxtdsp, vdsp, cmd);
6352 }
6353
6354 /*
6355 ** cp=0 means that the DSA does not point to a valid control
6356 ** block. This should not happen since we donnot use multi-byte
6357 ** move while we are being reselected ot after command complete.
6358 ** We are not able to recover from such a phase error.
6359 */
6360 if (!cp) {
6361 printk ("%s: SCSI phase error fixup: "
6362 "CCB already dequeued (0x%08lx)\n",
6363 ncr_name (np), (u_long) np->header.cp);
6364 goto reset_all;
6365 }
6366
6367 /*
6368 ** get old startaddress and old length.
6369 */
6370
6371 oadr = scr_to_cpu(vdsp[1]);
6372
6373 if (cmd & 0x10) { /* Table indirect */
6374 tblp = (u32 *) ((char*) &cp->phys + oadr);
6375 olen = scr_to_cpu(tblp[0]);
6376 oadr = scr_to_cpu(tblp[1]);
6377 } else {
6378 tblp = (u32 *) 0;
6379 olen = scr_to_cpu(vdsp[0]) & 0xffffff;
6380 }
6381
6382 if (DEBUG_FLAGS & DEBUG_PHASE) {
6383 printk ("OCMD=%x\nTBLP=%p OLEN=%x OADR=%x\n",
6384 (unsigned) (scr_to_cpu(vdsp[0]) >> 24),
6385 tblp,
6386 (unsigned) olen,
6387 (unsigned) oadr);
6388 }
6389
6390 /*
6391 ** check cmd against assumed interrupted script command.
6392 */
6393
6394 if (cmd != (scr_to_cpu(vdsp[0]) >> 24)) {
6395 PRINT_ADDR(cp->cmd, "internal error: cmd=%02x != %02x=(vdsp[0] "
6396 ">> 24)\n", cmd, scr_to_cpu(vdsp[0]) >> 24);
6397
6398 goto reset_all;
6399 }
6400
6401 /*
6402 ** cp != np->header.cp means that the header of the CCB
6403 ** currently being processed has not yet been copied to
6404 ** the global header area. That may happen if the device did
6405 ** not accept all our messages after having been selected.
6406 */
6407 if (cp != np->header.cp) {
6408 printk ("%s: SCSI phase error fixup: "
6409 "CCB address mismatch (0x%08lx != 0x%08lx)\n",
6410 ncr_name (np), (u_long) cp, (u_long) np->header.cp);
6411 }
6412
6413 /*
6414 ** if old phase not dataphase, leave here.
6415 */
6416
6417 if (cmd & 0x06) {
6418 PRINT_ADDR(cp->cmd, "phase change %x-%x %d@%08x resid=%d.\n",
6419 cmd&7, sbcl&7, (unsigned)olen,
6420 (unsigned)oadr, (unsigned)rest);
6421 goto unexpected_phase;
6422 }
6423
6424 /*
6425 ** choose the correct patch area.
6426 ** if savep points to one, choose the other.
6427 */
6428
6429 newcmd = cp->patch;
6430 newtmp = CCB_PHYS (cp, patch);
6431 if (newtmp == scr_to_cpu(cp->phys.header.savep)) {
6432 newcmd = &cp->patch[4];
6433 newtmp = CCB_PHYS (cp, patch[4]);
6434 }
6435
6436 /*
6437 ** fillin the commands
6438 */
6439
6440 newcmd[0] = cpu_to_scr(((cmd & 0x0f) << 24) | rest);
6441 newcmd[1] = cpu_to_scr(oadr + olen - rest);
6442 newcmd[2] = cpu_to_scr(SCR_JUMP);
6443 newcmd[3] = cpu_to_scr(nxtdsp);
6444
6445 if (DEBUG_FLAGS & DEBUG_PHASE) {
6446 PRINT_ADDR(cp->cmd, "newcmd[%d] %x %x %x %x.\n",
6447 (int) (newcmd - cp->patch),
6448 (unsigned)scr_to_cpu(newcmd[0]),
6449 (unsigned)scr_to_cpu(newcmd[1]),
6450 (unsigned)scr_to_cpu(newcmd[2]),
6451 (unsigned)scr_to_cpu(newcmd[3]));
6452 }
6453 /*
6454 ** fake the return address (to the patch).
6455 ** and restart script processor at dispatcher.
6456 */
6457 OUTL (nc_temp, newtmp);
6458 OUTL_DSP (NCB_SCRIPT_PHYS (np, dispatch));
6459 return;
6460
6461 /*
6462 ** Unexpected phase changes that occurs when the current phase
6463 ** is not a DATA IN or DATA OUT phase are due to error conditions.
6464 ** Such event may only happen when the SCRIPTS is using a
6465 ** multibyte SCSI MOVE.
6466 **
6467 ** Phase change Some possible cause
6468 **
6469 ** COMMAND --> MSG IN SCSI parity error detected by target.
6470 ** COMMAND --> STATUS Bad command or refused by target.
6471 ** MSG OUT --> MSG IN Message rejected by target.
6472 ** MSG OUT --> COMMAND Bogus target that discards extended
6473 ** negotiation messages.
6474 **
6475 ** The code below does not care of the new phase and so
6476 ** trusts the target. Why to annoy it ?
6477 ** If the interrupted phase is COMMAND phase, we restart at
6478 ** dispatcher.
6479 ** If a target does not get all the messages after selection,
6480 ** the code assumes blindly that the target discards extended
6481 ** messages and clears the negotiation status.
6482 ** If the target does not want all our response to negotiation,
6483 ** we force a SIR_NEGO_PROTO interrupt (it is a hack that avoids
6484 ** bloat for such a should_not_happen situation).
6485 ** In all other situation, we reset the BUS.
af901ca1 6486 ** Are these assumptions reasonable ? (Wait and see ...)
1da177e4
LT		 6487 */
6488unexpected_phase:
6489 dsp -= 8;
6490 nxtdsp = 0;
6491
6492 switch (cmd & 7) {
6493 case 2: /* COMMAND phase */
6494 nxtdsp = NCB_SCRIPT_PHYS (np, dispatch);
6495 break;
6496#if 0
6497 case 3: /* STATUS phase */
6498 nxtdsp = NCB_SCRIPT_PHYS (np, dispatch);
6499 break;
6500#endif
6501 case 6: /* MSG OUT phase */
6502 np->scripth->nxtdsp_go_on[0] = cpu_to_scr(dsp + 8);
6503 if (dsp == NCB_SCRIPT_PHYS (np, send_ident)) {
6504 cp->host_status = HS_BUSY;
6505 nxtdsp = NCB_SCRIPTH_PHYS (np, clratn_go_on);
6506 }
6507 else if (dsp == NCB_SCRIPTH_PHYS (np, send_wdtr) ||
6508 dsp == NCB_SCRIPTH_PHYS (np, send_sdtr)) {
6509 nxtdsp = NCB_SCRIPTH_PHYS (np, nego_bad_phase);
6510 }
6511 break;
6512#if 0
6513 case 7: /* MSG IN phase */
6514 nxtdsp = NCB_SCRIPT_PHYS (np, clrack);
6515 break;
6516#endif
6517 }
6518
6519 if (nxtdsp) {
6520 OUTL_DSP (nxtdsp);
6521 return;
6522 }
6523
6524reset_all:
6525 ncr_start_reset(np);
6526}
6527
6528
6529static void ncr_sir_to_redo(struct ncb *np, int num, struct ccb *cp)
6530{
6531 struct scsi_cmnd *cmd = cp->cmd;
6532 struct tcb *tp = &np->target[cmd->device->id];
6533 struct lcb *lp = tp->lp[cmd->device->lun];
6534 struct list_head *qp;
6535 struct ccb * cp2;
6536 int disc_cnt = 0;
6537 int busy_cnt = 0;
6538 u32 startp;
6539 u_char s_status = INB (SS_PRT);
6540
6541 /*
6542 ** Let the SCRIPTS processor skip all not yet started CCBs,
6543 ** and count disconnected CCBs. Since the busy queue is in
6544 ** the same order as the chip start queue, disconnected CCBs
6545 ** are before cp and busy ones after.
6546 */
6547 if (lp) {
6548 qp = lp->busy_ccbq.prev;
6549 while (qp != &lp->busy_ccbq) {
6550 cp2 = list_entry(qp, struct ccb, link_ccbq);
6551 qp = qp->prev;
6552 ++busy_cnt;
6553 if (cp2 == cp)
6554 break;
6555 cp2->start.schedule.l_paddr =
6556 cpu_to_scr(NCB_SCRIPTH_PHYS (np, skip));
6557 }
6558 lp->held_ccb = cp; /* Requeue when this one completes */
6559 disc_cnt = lp->queuedccbs - busy_cnt;
6560 }
6561
6562 switch(s_status) {
6563 default: /* Just for safety, should never happen */
6564 case S_QUEUE_FULL:
6565 /*
6566 ** Decrease number of tags to the number of
6567 ** disconnected commands.
6568 */
6569 if (!lp)
6570 goto out;
6571 if (bootverbose >= 1) {
6572 PRINT_ADDR(cmd, "QUEUE FULL! %d busy, %d disconnected "
6573 "CCBs\n", busy_cnt, disc_cnt);
6574 }
6575 if (disc_cnt < lp->numtags) {
6576 lp->numtags = disc_cnt > 2 ? disc_cnt : 2;
6577 lp->num_good = 0;
6578 ncr_setup_tags (np, cmd->device);
6579 }
6580 /*
6581 ** Requeue the command to the start queue.
6582 ** If any disconnected commands,
6583 ** Clear SIGP.
6584 ** Jump to reselect.
6585 */
6586 cp->phys.header.savep = cp->startp;
6587 cp->host_status = HS_BUSY;
6588 cp->scsi_status = S_ILLEGAL;
6589
6590 ncr_put_start_queue(np, cp);
6591 if (disc_cnt)
6592 INB (nc_ctest2); /* Clear SIGP */
6593 OUTL_DSP (NCB_SCRIPT_PHYS (np, reselect));
6594 return;
6595 case S_TERMINATED:
6596 case S_CHECK_COND:
6597 /*
6598 ** If we were requesting sense, give up.
6599 */
6600 if (cp->auto_sense)
6601 goto out;
6602
6603 /*
6604 ** Device returned CHECK CONDITION status.
6605 ** Prepare all needed data strutures for getting
6606 ** sense data.
6607 **
6608 ** identify message
6609 */
6610 cp->scsi_smsg2[0] = IDENTIFY(0, cmd->device->lun);
6611 cp->phys.smsg.addr = cpu_to_scr(CCB_PHYS (cp, scsi_smsg2));
6612 cp->phys.smsg.size = cpu_to_scr(1);
6613
6614 /*
6615 ** sense command
6616 */
6617 cp->phys.cmd.addr = cpu_to_scr(CCB_PHYS (cp, sensecmd));
6618 cp->phys.cmd.size = cpu_to_scr(6);
6619
6620 /*
6621 ** patch requested size into sense command
6622 */
6623 cp->sensecmd[0] = 0x03;
9cb78c16 6624 cp->sensecmd[1] = (cmd->device->lun & 0x7) << 5;
1da177e4
LT		 6625 cp->sensecmd[4] = sizeof(cp->sense_buf);
6626
6627 /*
6628 ** sense data
6629 */
6630 memset(cp->sense_buf, 0, sizeof(cp->sense_buf));
6631 cp->phys.sense.addr = cpu_to_scr(CCB_PHYS(cp,sense_buf[0]));
6632 cp->phys.sense.size = cpu_to_scr(sizeof(cp->sense_buf));
6633
6634 /*
6635 ** requeue the command.
6636 */
6637 startp = cpu_to_scr(NCB_SCRIPTH_PHYS (np, sdata_in));
6638
6639 cp->phys.header.savep = startp;
6640 cp->phys.header.goalp = startp + 24;
6641 cp->phys.header.lastp = startp;
6642 cp->phys.header.wgoalp = startp + 24;
6643 cp->phys.header.wlastp = startp;
6644
6645 cp->host_status = HS_BUSY;
6646 cp->scsi_status = S_ILLEGAL;
6647 cp->auto_sense = s_status;
6648
6649 cp->start.schedule.l_paddr =
6650 cpu_to_scr(NCB_SCRIPT_PHYS (np, select));
6651
6652 /*
6653 ** Select without ATN for quirky devices.
6654 */
6655 if (cmd->device->select_no_atn)
6656 cp->start.schedule.l_paddr =
6657 cpu_to_scr(NCB_SCRIPTH_PHYS (np, select_no_atn));
6658
6659 ncr_put_start_queue(np, cp);
6660
6661 OUTL_DSP (NCB_SCRIPT_PHYS (np, start));
6662 return;
6663 }
6664
6665out:
6666 OUTONB_STD ();
6667 return;
6668}
6669
6670
6671/*==========================================================
6672**
6673**
6674** ncr chip exception handler for programmed interrupts.
6675**
6676**
6677**==========================================================
6678*/
6679
6680void ncr_int_sir (struct ncb *np)
6681{
6682 u_char scntl3;
6683 u_char chg, ofs, per, fak, wide;
6684 u_char num = INB (nc_dsps);
6685 struct ccb *cp=NULL;
6686 u_long dsa = INL (nc_dsa);
6687 u_char target = INB (nc_sdid) & 0x0f;
6688 struct tcb *tp = &np->target[target];
6689 struct scsi_target *starget = tp->starget;
6690
6691 if (DEBUG_FLAGS & DEBUG_TINY) printk ("I#%d", num);
6692
6693 switch (num) {
6694 case SIR_INTFLY:
6695 /*
6696 ** This is used for HP Zalon/53c720 where INTFLY
6697 ** operation is currently broken.
6698 */
6699 ncr_wakeup_done(np);
6700#ifdef SCSI_NCR_CCB_DONE_SUPPORT
6701 OUTL(nc_dsp, NCB_SCRIPT_PHYS (np, done_end) + 8);
6702#else
6703 OUTL(nc_dsp, NCB_SCRIPT_PHYS (np, start));
6704#endif
6705 return;
6706 case SIR_RESEL_NO_MSG_IN:
6707 case SIR_RESEL_NO_IDENTIFY:
6708 /*
6709 ** If devices reselecting without sending an IDENTIFY
6710 ** message still exist, this should help.
6711 ** We just assume lun=0, 1 CCB, no tag.
6712 */
6713 if (tp->lp[0]) {
6714 OUTL_DSP (scr_to_cpu(tp->lp[0]->jump_ccb[0]));
6715 return;
6716 }
6717 case SIR_RESEL_BAD_TARGET: /* Will send a TARGET RESET message */
6718 case SIR_RESEL_BAD_LUN: /* Will send a TARGET RESET message */
6719 case SIR_RESEL_BAD_I_T_L_Q: /* Will send an ABORT TAG message */
6720 case SIR_RESEL_BAD_I_T_L: /* Will send an ABORT message */
6721 printk ("%s:%d: SIR %d, "
6722 "incorrect nexus identification on reselection\n",
6723 ncr_name (np), target, num);
6724 goto out;
6725 case SIR_DONE_OVERFLOW:
6726 printk ("%s:%d: SIR %d, "
6727 "CCB done queue overflow\n",
6728 ncr_name (np), target, num);
6729 goto out;
6730 case SIR_BAD_STATUS:
6731 cp = np->header.cp;
6732 if (!cp || CCB_PHYS (cp, phys) != dsa)
6733 goto out;
6734 ncr_sir_to_redo(np, num, cp);
6735 return;
6736 default:
6737 /*
6738 ** lookup the ccb
6739 */
6740 cp = np->ccb;
6741 while (cp && (CCB_PHYS (cp, phys) != dsa))
6742 cp = cp->link_ccb;
6743
6744 BUG_ON(!cp);
6745 BUG_ON(cp != np->header.cp);
6746
6747 if (!cp || cp != np->header.cp)
6748 goto out;
6749 }
6750
6751 switch (num) {
6752/*-----------------------------------------------------------------------------
6753**
6754** Was Sie schon immer ueber transfermode negotiation wissen wollten ...
b0dc1db1
MW		 6755** ("Everything you've always wanted to know about transfer mode
6756** negotiation")
1da177e4
LT		 6757**
6758** We try to negotiate sync and wide transfer only after
6759** a successful inquire command. We look at byte 7 of the
6760** inquire data to determine the capabilities of the target.
6761**
6762** When we try to negotiate, we append the negotiation message
6763** to the identify and (maybe) simple tag message.
6764** The host status field is set to HS_NEGOTIATE to mark this
6765** situation.
6766**
0779bf2d 6767** If the target doesn't answer this message immediately
1da177e4
LT		 6768** (as required by the standard), the SIR_NEGO_FAIL interrupt
6769** will be raised eventually.
6770** The handler removes the HS_NEGOTIATE status, and sets the
6771** negotiated value to the default (async / nowide).
6772**
6773** If we receive a matching answer immediately, we check it
6774** for validity, and set the values.
6775**
6776** If we receive a Reject message immediately, we assume the
6777** negotiation has failed, and fall back to standard values.
6778**
6779** If we receive a negotiation message while not in HS_NEGOTIATE
6780** state, it's a target initiated negotiation. We prepare a
6781** (hopefully) valid answer, set our parameters, and send back
6782** this answer to the target.
6783**
6784** If the target doesn't fetch the answer (no message out phase),
6785** we assume the negotiation has failed, and fall back to default
6786** settings.
6787**
6788** When we set the values, we adjust them in all ccbs belonging
6789** to this target, in the controller's register, and in the "phys"
6790** field of the controller's struct ncb.
6791**
6792** Possible cases: hs sir msg_in value send goto
6793** We try to negotiate:
6794** -> target doesn't msgin NEG FAIL noop defa. - dispatch
6795** -> target rejected our msg NEG FAIL reject defa. - dispatch
6796** -> target answered (ok) NEG SYNC sdtr set - clrack
6797** -> target answered (!ok) NEG SYNC sdtr defa. REJ--->msg_bad
6798** -> target answered (ok) NEG WIDE wdtr set - clrack
6799** -> target answered (!ok) NEG WIDE wdtr defa. REJ--->msg_bad
6800** -> any other msgin NEG FAIL noop defa. - dispatch
6801**
6802** Target tries to negotiate:
6803** -> incoming message --- SYNC sdtr set SDTR -
6804** -> incoming message --- WIDE wdtr set WDTR -
6805** We sent our answer:
6806** -> target doesn't msgout --- PROTO ? defa. - dispatch
6807**
6808**-----------------------------------------------------------------------------
6809*/
6810
6811 case SIR_NEGO_FAILED:
6812 /*-------------------------------------------------------
6813 **
6814 ** Negotiation failed.
6815 ** Target doesn't send an answer message,
6816 ** or target rejected our message.
6817 **
6818 ** Remove negotiation request.
6819 **
6820 **-------------------------------------------------------
6821 */
6822 OUTB (HS_PRT, HS_BUSY);
6823
6824 /* fall through */
6825
6826 case SIR_NEGO_PROTO:
6827 /*-------------------------------------------------------
6828 **
6829 ** Negotiation failed.
6830 ** Target doesn't fetch the answer message.
6831 **
6832 **-------------------------------------------------------
6833 */
6834
6835 if (DEBUG_FLAGS & DEBUG_NEGO) {
6836 PRINT_ADDR(cp->cmd, "negotiation failed sir=%x "
6837 "status=%x.\n", num, cp->nego_status);
6838 }
6839
6840 /*
6841 ** any error in negotiation:
6842 ** fall back to default mode.
6843 */
6844 switch (cp->nego_status) {
6845
6846 case NS_SYNC:
6847 spi_period(starget) = 0;
6848 spi_offset(starget) = 0;
6849 ncr_setsync (np, cp, 0, 0xe0);
6850 break;
6851
6852 case NS_WIDE:
6853 spi_width(starget) = 0;
6854 ncr_setwide (np, cp, 0, 0);
6855 break;
6856
6857 }
b0dc1db1
MW		 6858 np->msgin [0] = NOP;
6859 np->msgout[0] = NOP;
1da177e4
LT		 6860 cp->nego_status = 0;
6861 break;
6862
6863 case SIR_NEGO_SYNC:
6864 if (DEBUG_FLAGS & DEBUG_NEGO) {
6865 ncr_print_msg(cp, "sync msgin", np->msgin);
6866 }
6867
6868 chg = 0;
6869 per = np->msgin[3];
6870 ofs = np->msgin[4];
6871 if (ofs==0) per=255;
6872
6873 /*
6874 ** if target sends SDTR message,
6875 ** it CAN transfer synch.
6876 */
6877
6878 if (ofs && starget)
6879 spi_support_sync(starget) = 1;
6880
6881 /*
6882 ** check values against driver limits.
6883 */
6884
6885 if (per < np->minsync)
6886 {chg = 1; per = np->minsync;}
6887 if (per < tp->minsync)
6888 {chg = 1; per = tp->minsync;}
6889 if (ofs > tp->maxoffs)
6890 {chg = 1; ofs = tp->maxoffs;}
6891
6892 /*
6893 ** Check against controller limits.
6894 */
6895 fak = 7;
6896 scntl3 = 0;
6897 if (ofs != 0) {
6898 ncr_getsync(np, per, &fak, &scntl3);
6899 if (fak > 7) {
6900 chg = 1;
6901 ofs = 0;
6902 }
6903 }
6904 if (ofs == 0) {
6905 fak = 7;
6906 per = 0;
6907 scntl3 = 0;
6908 tp->minsync = 0;
6909 }
6910
6911 if (DEBUG_FLAGS & DEBUG_NEGO) {
6912 PRINT_ADDR(cp->cmd, "sync: per=%d scntl3=0x%x ofs=%d "
6913 "fak=%d chg=%d.\n", per, scntl3, ofs, fak, chg);
6914 }
6915
6916 if (INB (HS_PRT) == HS_NEGOTIATE) {
6917 OUTB (HS_PRT, HS_BUSY);
6918 switch (cp->nego_status) {
6919
6920 case NS_SYNC:
6921 /* This was an answer message */
6922 if (chg) {
6923 /* Answer wasn't acceptable. */
6924 spi_period(starget) = 0;
6925 spi_offset(starget) = 0;
6926 ncr_setsync(np, cp, 0, 0xe0);
6927 OUTL_DSP(NCB_SCRIPT_PHYS (np, msg_bad));
6928 } else {
6929 /* Answer is ok. */
6930 spi_period(starget) = per;
6931 spi_offset(starget) = ofs;
6932 ncr_setsync(np, cp, scntl3, (fak<<5)|ofs);
6933 OUTL_DSP(NCB_SCRIPT_PHYS (np, clrack));
6934 }
6935 return;
6936
6937 case NS_WIDE:
6938 spi_width(starget) = 0;
6939 ncr_setwide(np, cp, 0, 0);
6940 break;
6941 }
6942 }
6943
6944 /*
6945 ** It was a request. Set value and
6946 ** prepare an answer message
6947 */
6948
6949 spi_period(starget) = per;
6950 spi_offset(starget) = ofs;
6951 ncr_setsync(np, cp, scntl3, (fak<<5)|ofs);
6952
6ea3c0b2 6953 spi_populate_sync_msg(np->msgout, per, ofs);
1da177e4
LT		 6954 cp->nego_status = NS_SYNC;
6955
6956 if (DEBUG_FLAGS & DEBUG_NEGO) {
6957 ncr_print_msg(cp, "sync msgout", np->msgout);
6958 }
6959
6960 if (!ofs) {
6961 OUTL_DSP (NCB_SCRIPT_PHYS (np, msg_bad));
6962 return;
6963 }
b0dc1db1 6964 np->msgin [0] = NOP;
1da177e4
LT		 6965
6966 break;
6967
6968 case SIR_NEGO_WIDE:
6969 /*
6970 ** Wide request message received.
6971 */
6972 if (DEBUG_FLAGS & DEBUG_NEGO) {
6973 ncr_print_msg(cp, "wide msgin", np->msgin);
6974 }
6975
6976 /*
6977 ** get requested values.
6978 */
6979
6980 chg = 0;
6981 wide = np->msgin[3];
6982
6983 /*
6984 ** if target sends WDTR message,
6985 ** it CAN transfer wide.
6986 */
6987
6988 if (wide && starget)
6989 spi_support_wide(starget) = 1;
6990
6991 /*
6992 ** check values against driver limits.
6993 */
6994
6995 if (wide > tp->usrwide)
6996 {chg = 1; wide = tp->usrwide;}
6997
6998 if (DEBUG_FLAGS & DEBUG_NEGO) {
6999 PRINT_ADDR(cp->cmd, "wide: wide=%d chg=%d.\n", wide,
7000 chg);
7001 }
7002
7003 if (INB (HS_PRT) == HS_NEGOTIATE) {
7004 OUTB (HS_PRT, HS_BUSY);
7005 switch (cp->nego_status) {
7006
7007 case NS_WIDE:
7008 /*
7009 ** This was an answer message
7010 */
7011 if (chg) {
7012 /* Answer wasn't acceptable. */
7013 spi_width(starget) = 0;
7014 ncr_setwide(np, cp, 0, 1);
7015 OUTL_DSP (NCB_SCRIPT_PHYS (np, msg_bad));
7016 } else {
7017 /* Answer is ok. */
7018 spi_width(starget) = wide;
7019 ncr_setwide(np, cp, wide, 1);
7020 OUTL_DSP (NCB_SCRIPT_PHYS (np, clrack));
7021 }
7022 return;
7023
7024 case NS_SYNC:
7025 spi_period(starget) = 0;
7026 spi_offset(starget) = 0;
7027 ncr_setsync(np, cp, 0, 0xe0);
7028 break;
7029 }
7030 }
7031
7032 /*
7033 ** It was a request, set value and
7034 ** prepare an answer message
7035 */
7036
7037 spi_width(starget) = wide;
7038 ncr_setwide(np, cp, wide, 1);
6ea3c0b2 7039 spi_populate_width_msg(np->msgout, wide);
1da177e4 7040
b0dc1db1 7041 np->msgin [0] = NOP;
1da177e4
LT		 7042
7043 cp->nego_status = NS_WIDE;
7044
7045 if (DEBUG_FLAGS & DEBUG_NEGO) {
7046 ncr_print_msg(cp, "wide msgout", np->msgin);
7047 }
7048 break;
7049
7050/*--------------------------------------------------------------------
7051**
7052** Processing of special messages
7053**
7054**--------------------------------------------------------------------
7055*/
7056
7057 case SIR_REJECT_RECEIVED:
7058 /*-----------------------------------------------
7059 **
b0dc1db1 7060 ** We received a MESSAGE_REJECT.
1da177e4
LT		 7061 **
7062 **-----------------------------------------------
7063 */
7064
b0dc1db1 7065 PRINT_ADDR(cp->cmd, "MESSAGE_REJECT received (%x:%x).\n",
1da177e4
LT		 7066 (unsigned)scr_to_cpu(np->lastmsg), np->msgout[0]);
7067 break;
7068
7069 case SIR_REJECT_SENT:
7070 /*-----------------------------------------------
7071 **
7072 ** We received an unknown message
7073 **
7074 **-----------------------------------------------
7075 */
7076
b0dc1db1 7077 ncr_print_msg(cp, "MESSAGE_REJECT sent for", np->msgin);
1da177e4
LT		 7078 break;
7079
7080/*--------------------------------------------------------------------
7081**
7082** Processing of special messages
7083**
7084**--------------------------------------------------------------------
7085*/
7086
7087 case SIR_IGN_RESIDUE:
7088 /*-----------------------------------------------
7089 **
7090 ** We received an IGNORE RESIDUE message,
7091 ** which couldn't be handled by the script.
7092 **
7093 **-----------------------------------------------
7094 */
7095
b0dc1db1 7096 PRINT_ADDR(cp->cmd, "IGNORE_WIDE_RESIDUE received, but not yet "
1da177e4
LT		 7097 "implemented.\n");
7098 break;
7099#if 0
7100 case SIR_MISSING_SAVE:
7101 /*-----------------------------------------------
7102 **
7103 ** We received an DISCONNECT message,
7104 ** but the datapointer wasn't saved before.
7105 **
7106 **-----------------------------------------------
7107 */
7108
b0dc1db1 7109 PRINT_ADDR(cp->cmd, "DISCONNECT received, but datapointer "
1da177e4
LT		 7110 "not saved: data=%x save=%x goal=%x.\n",
7111 (unsigned) INL (nc_temp),
7112 (unsigned) scr_to_cpu(np->header.savep),
7113 (unsigned) scr_to_cpu(np->header.goalp));
7114 break;
7115#endif
7116 }
7117
7118out:
7119 OUTONB_STD ();
7120}
7121
7122/*==========================================================
7123**
7124**
7125** Acquire a control block
7126**
7127**
7128**==========================================================
7129*/
7130
7131static struct ccb *ncr_get_ccb(struct ncb *np, struct scsi_cmnd *cmd)
7132{
7133 u_char tn = cmd->device->id;
7134 u_char ln = cmd->device->lun;
7135 struct tcb *tp = &np->target[tn];
7136 struct lcb *lp = tp->lp[ln];
7137 u_char tag = NO_TAG;
7138 struct ccb *cp = NULL;
7139
7140 /*
7141 ** Lun structure available ?
7142 */
7143 if (lp) {
7144 struct list_head *qp;
7145 /*
7146 ** Keep from using more tags than we can handle.
7147 */
7148 if (lp->usetags && lp->busyccbs >= lp->maxnxs)
7149 return NULL;
7150
7151 /*
7152 ** Allocate a new CCB if needed.
7153 */
7154 if (list_empty(&lp->free_ccbq))
7155 ncr_alloc_ccb(np, tn, ln);
7156
7157 /*
7158 ** Look for free CCB
7159 */
7160 qp = ncr_list_pop(&lp->free_ccbq);
7161 if (qp) {
7162 cp = list_entry(qp, struct ccb, link_ccbq);
7163 if (cp->magic) {
7164 PRINT_ADDR(cmd, "ccb free list corrupted "
7165 "(@%p)\n", cp);
7166 cp = NULL;
7167 } else {
7168 list_add_tail(qp, &lp->wait_ccbq);
7169 ++lp->busyccbs;
7170 }
7171 }
7172
7173 /*
7174 ** If a CCB is available,
7175 ** Get a tag for this nexus if required.
7176 */
7177 if (cp) {
7178 if (lp->usetags)
7179 tag = lp->cb_tags[lp->ia_tag];
7180 }
7181 else if (lp->actccbs > 0)
7182 return NULL;
7183 }
7184
7185 /*
7186 ** if nothing available, take the default.
7187 */
7188 if (!cp)
7189 cp = np->ccb;
7190
7191 /*
7192 ** Wait until available.
7193 */
7194#if 0
7195 while (cp->magic) {
7196 if (flags & SCSI_NOSLEEP) break;
7197 if (tsleep ((caddr_t)cp, PRIBIO|PCATCH, "ncr", 0))
7198 break;
7199 }
7200#endif
7201
7202 if (cp->magic)
7203 return NULL;
7204
7205 cp->magic = 1;
7206
7207 /*
7208 ** Move to next available tag if tag used.
7209 */
7210 if (lp) {
7211 if (tag != NO_TAG) {
7212 ++lp->ia_tag;
7213 if (lp->ia_tag == MAX_TAGS)
7214 lp->ia_tag = 0;
7215 lp->tags_umap |= (((tagmap_t) 1) << tag);
7216 }
7217 }
7218
7219 /*
7220 ** Remember all informations needed to free this CCB.
7221 */
7222 cp->tag = tag;
7223 cp->target = tn;
7224 cp->lun = ln;
7225
7226 if (DEBUG_FLAGS & DEBUG_TAGS) {
7227 PRINT_ADDR(cmd, "ccb @%p using tag %d.\n", cp, tag);
7228 }
7229
7230 return cp;
7231}
7232
7233/*==========================================================
7234**
7235**
7236** Release one control block
7237**
7238**
7239**==========================================================
7240*/
7241
7242static void ncr_free_ccb (struct ncb *np, struct ccb *cp)
7243{
7244 struct tcb *tp = &np->target[cp->target];
7245 struct lcb *lp = tp->lp[cp->lun];
7246
7247 if (DEBUG_FLAGS & DEBUG_TAGS) {
7248 PRINT_ADDR(cp->cmd, "ccb @%p freeing tag %d.\n", cp, cp->tag);
7249 }
7250
7251 /*
7252 ** If lun control block available,
7253 ** decrement active commands and increment credit,
7254 ** free the tag if any and remove the JUMP for reselect.
7255 */
7256 if (lp) {
7257 if (cp->tag != NO_TAG) {
7258 lp->cb_tags[lp->if_tag++] = cp->tag;
7259 if (lp->if_tag == MAX_TAGS)
7260 lp->if_tag = 0;
7261 lp->tags_umap &= ~(((tagmap_t) 1) << cp->tag);
7262 lp->tags_smap &= lp->tags_umap;
7263 lp->jump_ccb[cp->tag] =
7264 cpu_to_scr(NCB_SCRIPTH_PHYS(np, bad_i_t_l_q));
7265 } else {
7266 lp->jump_ccb[0] =
7267 cpu_to_scr(NCB_SCRIPTH_PHYS(np, bad_i_t_l));
7268 }
7269 }
7270
7271 /*
7272 ** Make this CCB available.
7273 */
7274
7275 if (lp) {
7276 if (cp != np->ccb)
7277 list_move(&cp->link_ccbq, &lp->free_ccbq);
7278 --lp->busyccbs;
7279 if (cp->queued) {
7280 --lp->queuedccbs;
7281 }
7282 }
7283 cp -> host_status = HS_IDLE;
7284 cp -> magic = 0;
7285 if (cp->queued) {
7286 --np->queuedccbs;
7287 cp->queued = 0;
7288 }
7289
7290#if 0
7291 if (cp == np->ccb)
7292 wakeup ((caddr_t) cp);
7293#endif
7294}
7295
7296
7297#define ncr_reg_bus_addr(r) (np->paddr + offsetof (struct ncr_reg, r))
7298
7299/*------------------------------------------------------------------------
7300** Initialize the fixed part of a CCB structure.
7301**------------------------------------------------------------------------
7302**------------------------------------------------------------------------
7303*/
7304static void ncr_init_ccb(struct ncb *np, struct ccb *cp)
7305{
7306 ncrcmd copy_4 = np->features & FE_PFEN ? SCR_COPY(4) : SCR_COPY_F(4);
7307
7308 /*
7309 ** Remember virtual and bus address of this ccb.
7310 */
7311 cp->p_ccb = vtobus(cp);
7312 cp->phys.header.cp = cp;
7313
7314 /*
7315 ** This allows list_del to work for the default ccb.
7316 */
7317 INIT_LIST_HEAD(&cp->link_ccbq);
7318
7319 /*
7320 ** Initialyze the start and restart launch script.
7321 **
7322 ** COPY(4) @(...p_phys), @(dsa)
7323 ** JUMP @(sched_point)
7324 */
7325 cp->start.setup_dsa[0] = cpu_to_scr(copy_4);
7326 cp->start.setup_dsa[1] = cpu_to_scr(CCB_PHYS(cp, start.p_phys));
7327 cp->start.setup_dsa[2] = cpu_to_scr(ncr_reg_bus_addr(nc_dsa));
7328 cp->start.schedule.l_cmd = cpu_to_scr(SCR_JUMP);
7329 cp->start.p_phys = cpu_to_scr(CCB_PHYS(cp, phys));
7330
7331 memcpy(&cp->restart, &cp->start, sizeof(cp->restart));
7332
7333 cp->start.schedule.l_paddr = cpu_to_scr(NCB_SCRIPT_PHYS (np, idle));
7334 cp->restart.schedule.l_paddr = cpu_to_scr(NCB_SCRIPTH_PHYS (np, abort));
7335}
7336
7337
7338/*------------------------------------------------------------------------
7339** Allocate a CCB and initialize its fixed part.
7340**------------------------------------------------------------------------
7341**------------------------------------------------------------------------
7342*/
7343static void ncr_alloc_ccb(struct ncb *np, u_char tn, u_char ln)
7344{
7345 struct tcb *tp = &np->target[tn];
7346 struct lcb *lp = tp->lp[ln];
7347 struct ccb *cp = NULL;
7348
7349 /*
7350 ** Allocate memory for this CCB.
7351 */
7352 cp = m_calloc_dma(sizeof(struct ccb), "CCB");
7353 if (!cp)
7354 return;
7355
7356 /*
7357 ** Count it and initialyze it.
7358 */
7359 lp->actccbs++;
7360 np->actccbs++;
7361 memset(cp, 0, sizeof (*cp));
7362 ncr_init_ccb(np, cp);
7363
7364 /*
7365 ** Chain into wakeup list and free ccb queue and take it
7366 ** into account for tagged commands.
7367 */
7368 cp->link_ccb = np->ccb->link_ccb;
7369 np->ccb->link_ccb = cp;
7370
7371 list_add(&cp->link_ccbq, &lp->free_ccbq);
7372}
7373
7374/*==========================================================
7375**
7376**
7377** Allocation of resources for Targets/Luns/Tags.
7378**
7379**
7380**==========================================================
7381*/
7382
7383
7384/*------------------------------------------------------------------------
7385** Target control block initialisation.
7386**------------------------------------------------------------------------
7387** This data structure is fully initialized after a SCSI command
7388** has been successfully completed for this target.
7389** It contains a SCRIPT that is called on target reselection.
7390**------------------------------------------------------------------------
7391*/
7392static void ncr_init_tcb (struct ncb *np, u_char tn)
7393{
7394 struct tcb *tp = &np->target[tn];
7395 ncrcmd copy_1 = np->features & FE_PFEN ? SCR_COPY(1) : SCR_COPY_F(1);
7396 int th = tn & 3;
7397 int i;
7398
7399 /*
7400 ** Jump to next tcb if SFBR does not match this target.
7401 ** JUMP IF (SFBR != #target#), @(next tcb)
7402 */
7403 tp->jump_tcb.l_cmd =
7404 cpu_to_scr((SCR_JUMP ^ IFFALSE (DATA (0x80 + tn))));
7405 tp->jump_tcb.l_paddr = np->jump_tcb[th].l_paddr;
7406
7407 /*
7408 ** Load the synchronous transfer register.
7409 ** COPY @(tp->sval), @(sxfer)
7410 */
7411 tp->getscr[0] = cpu_to_scr(copy_1);
7412 tp->getscr[1] = cpu_to_scr(vtobus (&tp->sval));
7413#ifdef SCSI_NCR_BIG_ENDIAN
7414 tp->getscr[2] = cpu_to_scr(ncr_reg_bus_addr(nc_sxfer) ^ 3);
7415#else
7416 tp->getscr[2] = cpu_to_scr(ncr_reg_bus_addr(nc_sxfer));
7417#endif
7418
7419 /*
7420 ** Load the timing register.
7421 ** COPY @(tp->wval), @(scntl3)
7422 */
7423 tp->getscr[3] = cpu_to_scr(copy_1);
7424 tp->getscr[4] = cpu_to_scr(vtobus (&tp->wval));
7425#ifdef SCSI_NCR_BIG_ENDIAN
7426 tp->getscr[5] = cpu_to_scr(ncr_reg_bus_addr(nc_scntl3) ^ 3);
7427#else
7428 tp->getscr[5] = cpu_to_scr(ncr_reg_bus_addr(nc_scntl3));
7429#endif
7430
7431 /*
7432 ** Get the IDENTIFY message and the lun.
7433 ** CALL @script(resel_lun)
7434 */
7435 tp->call_lun.l_cmd = cpu_to_scr(SCR_CALL);
7436 tp->call_lun.l_paddr = cpu_to_scr(NCB_SCRIPT_PHYS (np, resel_lun));
7437
7438 /*
7439 ** Look for the lun control block of this nexus.
7440 ** For i = 0 to 3
7441 ** JUMP ^ IFTRUE (MASK (i, 3)), @(next_lcb)
7442 */
7443 for (i = 0 ; i < 4 ; i++) {
7444 tp->jump_lcb[i].l_cmd =
7445 cpu_to_scr((SCR_JUMP ^ IFTRUE (MASK (i, 3))));
7446 tp->jump_lcb[i].l_paddr =
7447 cpu_to_scr(NCB_SCRIPTH_PHYS (np, bad_identify));
7448 }
7449
7450 /*
7451 ** Link this target control block to the JUMP chain.
7452 */
7453 np->jump_tcb[th].l_paddr = cpu_to_scr(vtobus (&tp->jump_tcb));
7454
7455 /*
7456 ** These assert's should be moved at driver initialisations.
7457 */
7458#ifdef SCSI_NCR_BIG_ENDIAN
7459 BUG_ON(((offsetof(struct ncr_reg, nc_sxfer) ^
7460 offsetof(struct tcb , sval )) &3) != 3);
7461 BUG_ON(((offsetof(struct ncr_reg, nc_scntl3) ^
7462 offsetof(struct tcb , wval )) &3) != 3);
7463#else
7464 BUG_ON(((offsetof(struct ncr_reg, nc_sxfer) ^
7465 offsetof(struct tcb , sval )) &3) != 0);
7466 BUG_ON(((offsetof(struct ncr_reg, nc_scntl3) ^
7467 offsetof(struct tcb , wval )) &3) != 0);
7468#endif
7469}
7470
7471
7472/*------------------------------------------------------------------------
7473** Lun control block allocation and initialization.
7474**------------------------------------------------------------------------
7475** This data structure is allocated and initialized after a SCSI
7476** command has been successfully completed for this target/lun.
7477**------------------------------------------------------------------------
7478*/
7479static struct lcb *ncr_alloc_lcb (struct ncb *np, u_char tn, u_char ln)
7480{
7481 struct tcb *tp = &np->target[tn];
7482 struct lcb *lp = tp->lp[ln];
7483 ncrcmd copy_4 = np->features & FE_PFEN ? SCR_COPY(4) : SCR_COPY_F(4);
7484 int lh = ln & 3;
7485
7486 /*
7487 ** Already done, return.
7488 */
7489 if (lp)
7490 return lp;
7491
7492 /*
7493 ** Allocate the lcb.
7494 */
7495 lp = m_calloc_dma(sizeof(struct lcb), "LCB");
7496 if (!lp)
7497 goto fail;
7498 memset(lp, 0, sizeof(*lp));
7499 tp->lp[ln] = lp;
7500
7501 /*
7502 ** Initialize the target control block if not yet.
7503 */
7504 if (!tp->jump_tcb.l_cmd)
7505 ncr_init_tcb(np, tn);
7506
7507 /*
7508 ** Initialize the CCB queue headers.
7509 */
7510 INIT_LIST_HEAD(&lp->free_ccbq);
7511 INIT_LIST_HEAD(&lp->busy_ccbq);
7512 INIT_LIST_HEAD(&lp->wait_ccbq);
7513 INIT_LIST_HEAD(&lp->skip_ccbq);
7514
7515 /*
7516 ** Set max CCBs to 1 and use the default 1 entry
7517 ** jump table by default.
7518 */
7519 lp->maxnxs = 1;
7520 lp->jump_ccb = &lp->jump_ccb_0;
7521 lp->p_jump_ccb = cpu_to_scr(vtobus(lp->jump_ccb));
7522
7523 /*
7524 ** Initilialyze the reselect script:
7525 **
7526 ** Jump to next lcb if SFBR does not match this lun.
7527 ** Load TEMP with the CCB direct jump table bus address.
7528 ** Get the SIMPLE TAG message and the tag.
7529 **
7530 ** JUMP IF (SFBR != #lun#), @(next lcb)
7531 ** COPY @(lp->p_jump_ccb), @(temp)
7532 ** JUMP @script(resel_notag)
7533 */
7534 lp->jump_lcb.l_cmd =
7535 cpu_to_scr((SCR_JUMP ^ IFFALSE (MASK (0x80+ln, 0xff))));
7536 lp->jump_lcb.l_paddr = tp->jump_lcb[lh].l_paddr;
7537
7538 lp->load_jump_ccb[0] = cpu_to_scr(copy_4);
7539 lp->load_jump_ccb[1] = cpu_to_scr(vtobus (&lp->p_jump_ccb));
7540 lp->load_jump_ccb[2] = cpu_to_scr(ncr_reg_bus_addr(nc_temp));
7541
7542 lp->jump_tag.l_cmd = cpu_to_scr(SCR_JUMP);
7543 lp->jump_tag.l_paddr = cpu_to_scr(NCB_SCRIPT_PHYS (np, resel_notag));
7544
7545 /*
7546 ** Link this lun control block to the JUMP chain.
7547 */
7548 tp->jump_lcb[lh].l_paddr = cpu_to_scr(vtobus (&lp->jump_lcb));
7549
7550 /*
7551 ** Initialize command queuing control.
7552 */
7553 lp->busyccbs = 1;
7554 lp->queuedccbs = 1;
7555 lp->queuedepth = 1;
7556fail:
7557 return lp;
7558}
7559
7560
7561/*------------------------------------------------------------------------
7562** Lun control block setup on INQUIRY data received.
7563**------------------------------------------------------------------------
7564** We only support WIDE, SYNC for targets and CMDQ for logical units.
7565** This setup is done on each INQUIRY since we are expecting user
7566** will play with CHANGE DEFINITION commands. :-)
7567**------------------------------------------------------------------------
7568*/
7569static struct lcb *ncr_setup_lcb (struct ncb *np, struct scsi_device *sdev)
7570{
7571 unsigned char tn = sdev->id, ln = sdev->lun;
7572 struct tcb *tp = &np->target[tn];
7573 struct lcb *lp = tp->lp[ln];
7574
7575 /* If no lcb, try to allocate it. */
7576 if (!lp && !(lp = ncr_alloc_lcb(np, tn, ln)))
7577 goto fail;
7578
7579 /*
7580 ** If unit supports tagged commands, allocate the
7581 ** CCB JUMP table if not yet.
7582 */
7583 if (sdev->tagged_supported && lp->jump_ccb == &lp->jump_ccb_0) {
7584 int i;
7585 lp->jump_ccb = m_calloc_dma(256, "JUMP_CCB");
7586 if (!lp->jump_ccb) {
7587 lp->jump_ccb = &lp->jump_ccb_0;
7588 goto fail;
7589 }
7590 lp->p_jump_ccb = cpu_to_scr(vtobus(lp->jump_ccb));
7591 for (i = 0 ; i < 64 ; i++)
7592 lp->jump_ccb[i] =
7593 cpu_to_scr(NCB_SCRIPTH_PHYS (np, bad_i_t_l_q));
7594 for (i = 0 ; i < MAX_TAGS ; i++)
7595 lp->cb_tags[i] = i;
7596 lp->maxnxs = MAX_TAGS;
f2be34a3 7597 lp->tags_stime = jiffies + 3*HZ;
1da177e4
LT		 7598 ncr_setup_tags (np, sdev);
7599 }
7600
7601
7602fail:
7603 return lp;
7604}
7605
7606/*==========================================================
7607**
7608**
7609** Build Scatter Gather Block
7610**
7611**
7612**==========================================================
7613**
7614** The transfer area may be scattered among
7615** several non adjacent physical pages.
7616**
7617** We may use MAX_SCATTER blocks.
7618**
7619**----------------------------------------------------------
7620*/
7621
7622/*
7623** We try to reduce the number of interrupts caused
7624** by unexpected phase changes due to disconnects.
7625** A typical harddisk may disconnect before ANY block.
7626** If we wanted to avoid unexpected phase changes at all
7627** we had to use a break point every 512 bytes.
7628** Of course the number of scatter/gather blocks is
7629** limited.
7630** Under Linux, the scatter/gatter blocks are provided by
7631** the generic driver. We just have to copy addresses and
7632** sizes to the data segment array.
7633*/
7634
1da177e4
LT		 7635static int ncr_scatter(struct ncb *np, struct ccb *cp, struct scsi_cmnd *cmd)
7636{
7637 int segment = 0;
69eca4f5 7638 int use_sg = scsi_sg_count(cmd);
1da177e4
LT		 7639
7640 cp->data_len = 0;
7641
69eca4f5
FT		 7642 use_sg = map_scsi_sg_data(np, cmd);
7643 if (use_sg > 0) {
7644 struct scatterlist *sg;
1da177e4
LT		 7645 struct scr_tblmove *data;
7646
7647 if (use_sg > MAX_SCATTER) {
7648 unmap_scsi_data(np, cmd);
7649 return -1;
7650 }
7651
7652 data = &cp->phys.data[MAX_SCATTER - use_sg];
7653
69eca4f5
FT		 7654 scsi_for_each_sg(cmd, sg, use_sg, segment) {
7655 dma_addr_t baddr = sg_dma_address(sg);
7656 unsigned int len = sg_dma_len(sg);
1da177e4
LT		 7657
7658 ncr_build_sge(np, &data[segment], baddr, len);
7659 cp->data_len += len;
7660 }
69eca4f5 7661 } else
1da177e4 7662 segment = -2;
1da177e4
LT		 7663
7664 return segment;
7665}
7666
7667/*==========================================================
7668**
7669**
7670** Test the bus snoop logic :-(
7671**
7672** Has to be called with interrupts disabled.
7673**
7674**
7675**==========================================================
7676*/
7677
7678static int __init ncr_regtest (struct ncb* np)
7679{
7680 register volatile u32 data;
7681 /*
7682 ** ncr registers may NOT be cached.
7683 ** write 0xffffffff to a read only register area,
7684 ** and try to read it back.
7685 */
7686 data = 0xffffffff;
7687 OUTL_OFF(offsetof(struct ncr_reg, nc_dstat), data);
7688 data = INL_OFF(offsetof(struct ncr_reg, nc_dstat));
7689#if 1
7690 if (data == 0xffffffff) {
7691#else
7692 if ((data & 0xe2f0fffd) != 0x02000080) {
7693#endif
7694 printk ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n",
7695 (unsigned) data);
7696 return (0x10);
7697 }
7698 return (0);
7699}
7700
7701static int __init ncr_snooptest (struct ncb* np)
7702{
7703 u32 ncr_rd, ncr_wr, ncr_bk, host_rd, host_wr, pc;
7704 int i, err=0;
7705 if (np->reg) {
7706 err |= ncr_regtest (np);
7707 if (err)
7708 return (err);
7709 }
7710
7711 /* init */
7712 pc = NCB_SCRIPTH_PHYS (np, snooptest);
7713 host_wr = 1;
7714 ncr_wr = 2;
7715 /*
7716 ** Set memory and register.
7717 */
7718 np->ncr_cache = cpu_to_scr(host_wr);
7719 OUTL (nc_temp, ncr_wr);
7720 /*
7721 ** Start script (exchange values)
7722 */
7723 OUTL_DSP (pc);
7724 /*
7725 ** Wait 'til done (with timeout)
7726 */
7727 for (i=0; i<NCR_SNOOP_TIMEOUT; i++)
7728 if (INB(nc_istat) & (INTF|SIP|DIP))
7729 break;
7730 /*
7731 ** Save termination position.
7732 */
7733 pc = INL (nc_dsp);
7734 /*
7735 ** Read memory and register.
7736 */
7737 host_rd = scr_to_cpu(np->ncr_cache);
7738 ncr_rd = INL (nc_scratcha);
7739 ncr_bk = INL (nc_temp);
7740 /*
7741 ** Reset ncr chip
7742 */
7743 ncr_chip_reset(np, 100);
7744 /*
7745 ** check for timeout
7746 */
7747 if (i>=NCR_SNOOP_TIMEOUT) {
7748 printk ("CACHE TEST FAILED: timeout.\n");
7749 return (0x20);
7750 }
7751 /*
7752 ** Check termination position.
7753 */
7754 if (pc != NCB_SCRIPTH_PHYS (np, snoopend)+8) {
7755 printk ("CACHE TEST FAILED: script execution failed.\n");
7756 printk ("start=%08lx, pc=%08lx, end=%08lx\n",
7757 (u_long) NCB_SCRIPTH_PHYS (np, snooptest), (u_long) pc,
7758 (u_long) NCB_SCRIPTH_PHYS (np, snoopend) +8);
7759 return (0x40);
7760 }
7761 /*
7762 ** Show results.
7763 */
7764 if (host_wr != ncr_rd) {
7765 printk ("CACHE TEST FAILED: host wrote %d, ncr read %d.\n",
7766 (int) host_wr, (int) ncr_rd);
7767 err |= 1;
7768 }
7769 if (host_rd != ncr_wr) {
7770 printk ("CACHE TEST FAILED: ncr wrote %d, host read %d.\n",
7771 (int) ncr_wr, (int) host_rd);
7772 err |= 2;
7773 }
7774 if (ncr_bk != ncr_wr) {
7775 printk ("CACHE TEST FAILED: ncr wrote %d, read back %d.\n",
7776 (int) ncr_wr, (int) ncr_bk);
7777 err |= 4;
7778 }
7779 return (err);
7780}
7781
7782/*==========================================================
7783**
7784** Determine the ncr's clock frequency.
7785** This is essential for the negotiation
7786** of the synchronous transfer rate.
7787**
7788**==========================================================
7789**
7790** Note: we have to return the correct value.
b0dc1db1 7791** THERE IS NO SAFE DEFAULT VALUE.
1da177e4
LT		 7792**
7793** Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock.
7794** 53C860 and 53C875 rev. 1 support fast20 transfers but
7795** do not have a clock doubler and so are provided with a
7796** 80 MHz clock. All other fast20 boards incorporate a doubler
7797** and so should be delivered with a 40 MHz clock.
7798** The future fast40 chips (895/895) use a 40 Mhz base clock
7799** and provide a clock quadrupler (160 Mhz). The code below
7800** tries to deal as cleverly as possible with all this stuff.
7801**
7802**----------------------------------------------------------
7803*/
7804
7805/*
7806 * Select NCR SCSI clock frequency
7807 */
7808static void ncr_selectclock(struct ncb *np, u_char scntl3)
7809{
7810 if (np->multiplier < 2) {
7811 OUTB(nc_scntl3, scntl3);
7812 return;
7813 }
7814
7815 if (bootverbose >= 2)
7816 printk ("%s: enabling clock multiplier\n", ncr_name(np));
7817
7818 OUTB(nc_stest1, DBLEN); /* Enable clock multiplier */
7819 if (np->multiplier > 2) { /* Poll bit 5 of stest4 for quadrupler */
7820 int i = 20;
7821 while (!(INB(nc_stest4) & LCKFRQ) && --i > 0)
7822 udelay(20);
7823 if (!i)
7824 printk("%s: the chip cannot lock the frequency\n", ncr_name(np));
7825 } else /* Wait 20 micro-seconds for doubler */
7826 udelay(20);
7827 OUTB(nc_stest3, HSC); /* Halt the scsi clock */
7828 OUTB(nc_scntl3, scntl3);
7829 OUTB(nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */
7830 OUTB(nc_stest3, 0x00); /* Restart scsi clock */
7831}
7832
7833
7834/*
7835 * calculate NCR SCSI clock frequency (in KHz)
7836 */
7837static unsigned __init ncrgetfreq (struct ncb *np, int gen)
7838{
7839 unsigned ms = 0;
7840 char count = 0;
7841
7842 /*
7843 * Measure GEN timer delay in order
7844 * to calculate SCSI clock frequency
7845 *
7846 * This code will never execute too
7847 * many loop iterations (if DELAY is
7848 * reasonably correct). It could get
7849 * too low a delay (too high a freq.)
7850 * if the CPU is slow executing the
7851 * loop for some reason (an NMI, for
7852 * example). For this reason we will
7853 * if multiple measurements are to be
7854 * performed trust the higher delay
7855 * (lower frequency returned).
7856 */
7857 OUTB (nc_stest1, 0); /* make sure clock doubler is OFF */
7858 OUTW (nc_sien , 0); /* mask all scsi interrupts */
7859 (void) INW (nc_sist); /* clear pending scsi interrupt */
7860 OUTB (nc_dien , 0); /* mask all dma interrupts */
7861 (void) INW (nc_sist); /* another one, just to be sure :) */
7862 OUTB (nc_scntl3, 4); /* set pre-scaler to divide by 3 */
7863 OUTB (nc_stime1, 0); /* disable general purpose timer */
7864 OUTB (nc_stime1, gen); /* set to nominal delay of 1<<gen * 125us */
7865 while (!(INW(nc_sist) & GEN) && ms++ < 100000) {
7866 for (count = 0; count < 10; count ++)
7867 udelay(100); /* count ms */
7868 }
7869 OUTB (nc_stime1, 0); /* disable general purpose timer */
7870 /*
7871 * set prescaler to divide by whatever 0 means
7872 * 0 ought to choose divide by 2, but appears
7873 * to set divide by 3.5 mode in my 53c810 ...
7874 */
7875 OUTB (nc_scntl3, 0);
7876
7877 if (bootverbose >= 2)
7878 printk ("%s: Delay (GEN=%d): %u msec\n", ncr_name(np), gen, ms);
7879 /*
7880 * adjust for prescaler, and convert into KHz
7881 */
7882 return ms ? ((1 << gen) * 4340) / ms : 0;
7883}
7884
7885/*
7886 * Get/probe NCR SCSI clock frequency
7887 */
7888static void __init ncr_getclock (struct ncb *np, int mult)
7889{
7890 unsigned char scntl3 = INB(nc_scntl3);
7891 unsigned char stest1 = INB(nc_stest1);
7892 unsigned f1;
7893
7894 np->multiplier = 1;
7895 f1 = 40000;
7896
7897 /*
7898 ** True with 875 or 895 with clock multiplier selected
7899 */
7900 if (mult > 1 && (stest1 & (DBLEN+DBLSEL)) == DBLEN+DBLSEL) {
7901 if (bootverbose >= 2)
7902 printk ("%s: clock multiplier found\n", ncr_name(np));
7903 np->multiplier = mult;
7904 }
7905
7906 /*
7907 ** If multiplier not found or scntl3 not 7,5,3,
7908 ** reset chip and get frequency from general purpose timer.
7909 ** Otherwise trust scntl3 BIOS setting.
7910 */
7911 if (np->multiplier != mult || (scntl3 & 7) < 3 || !(scntl3 & 1)) {
7912 unsigned f2;
7913
7914 ncr_chip_reset(np, 5);
7915
7916 (void) ncrgetfreq (np, 11); /* throw away first result */
7917 f1 = ncrgetfreq (np, 11);
7918 f2 = ncrgetfreq (np, 11);
7919
7920 if(bootverbose)
7921 printk ("%s: NCR clock is %uKHz, %uKHz\n", ncr_name(np), f1, f2);
7922
7923 if (f1 > f2) f1 = f2; /* trust lower result */
7924
7925 if (f1 < 45000) f1 = 40000;
7926 else if (f1 < 55000) f1 = 50000;
7927 else f1 = 80000;
7928
7929 if (f1 < 80000 && mult > 1) {
7930 if (bootverbose >= 2)
7931 printk ("%s: clock multiplier assumed\n", ncr_name(np));
7932 np->multiplier = mult;
7933 }
7934 } else {
7935 if ((scntl3 & 7) == 3) f1 = 40000;
7936 else if ((scntl3 & 7) == 5) f1 = 80000;
7937 else f1 = 160000;
7938
7939 f1 /= np->multiplier;
7940 }
7941
7942 /*
7943 ** Compute controller synchronous parameters.
7944 */
7945 f1 *= np->multiplier;
7946 np->clock_khz = f1;
7947}
7948
7949/*===================== LINUX ENTRY POINTS SECTION ==========================*/
7950
7951static int ncr53c8xx_slave_alloc(struct scsi_device *device)
7952{
7953 struct Scsi_Host *host = device->host;
7954 struct ncb *np = ((struct host_data *) host->hostdata)->ncb;
7955 struct tcb *tp = &np->target[device->id];
7956 tp->starget = device->sdev_target;
7957
7958 return 0;
7959}
7960
7961static int ncr53c8xx_slave_configure(struct scsi_device *device)
7962{
7963 struct Scsi_Host *host = device->host;
7964 struct ncb *np = ((struct host_data *) host->hostdata)->ncb;
7965 struct tcb *tp = &np->target[device->id];
7966 struct lcb *lp = tp->lp[device->lun];
7967 int numtags, depth_to_use;
7968
7969 ncr_setup_lcb(np, device);
7970
7971 /*
7972 ** Select queue depth from driver setup.
7973 ** Donnot use more than configured by user.
7974 ** Use at least 2.
7975 ** Donnot use more than our maximum.
7976 */
7977 numtags = device_queue_depth(np->unit, device->id, device->lun);
7978 if (numtags > tp->usrtags)
7979 numtags = tp->usrtags;
7980 if (!device->tagged_supported)
7981 numtags = 1;
7982 depth_to_use = numtags;
7983 if (depth_to_use < 2)
7984 depth_to_use = 2;
7985 if (depth_to_use > MAX_TAGS)
7986 depth_to_use = MAX_TAGS;
7987
db5ed4df 7988 scsi_change_queue_depth(device, depth_to_use);
1da177e4
LT		 7989
7990 /*
7991 ** Since the queue depth is not tunable under Linux,
7992 ** we need to know this value in order not to
7993 ** announce stupid things to user.
7994 **
7995 ** XXX(hch): As of Linux 2.6 it certainly _is_ tunable..
7996 ** In fact we just tuned it, or did I miss
7997 ** something important? :)
7998 */
7999 if (lp) {
8000 lp->numtags = lp->maxtags = numtags;
8001 lp->scdev_depth = depth_to_use;
8002 }
8003 ncr_setup_tags (np, device);
8004
8005#ifdef DEBUG_NCR53C8XX
8006 printk("ncr53c8xx_select_queue_depth: host=%d, id=%d, lun=%d, depth=%d\n",
8007 np->unit, device->id, device->lun, depth_to_use);
8008#endif
8009
8010 if (spi_support_sync(device->sdev_target) &&
8011 !spi_initial_dv(device->sdev_target))
8012 spi_dv_device(device);
8013 return 0;
8014}
8015
f281233d 8016static int ncr53c8xx_queue_command_lck (struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
1da177e4
LT		 8017{
8018 struct ncb *np = ((struct host_data *) cmd->device->host->hostdata)->ncb;
8019 unsigned long flags;
8020 int sts;
8021
8022#ifdef DEBUG_NCR53C8XX
8023printk("ncr53c8xx_queue_command\n");
8024#endif
8025
8026 cmd->scsi_done = done;
8027 cmd->host_scribble = NULL;
8028 cmd->__data_mapped = 0;
8029 cmd->__data_mapping = 0;
8030
8031 spin_lock_irqsave(&np->smp_lock, flags);
8032
8033 if ((sts = ncr_queue_command(np, cmd)) != DID_OK) {
78adb2bc 8034 cmd->result = sts << 16;
1da177e4
LT		 8035#ifdef DEBUG_NCR53C8XX
8036printk("ncr53c8xx : command not queued - result=%d\n", sts);
8037#endif
8038 }
8039#ifdef DEBUG_NCR53C8XX
8040 else
8041printk("ncr53c8xx : command successfully queued\n");
8042#endif
8043
8044 spin_unlock_irqrestore(&np->smp_lock, flags);
8045
8046 if (sts != DID_OK) {
8047 unmap_scsi_data(np, cmd);
8048 done(cmd);
8049 sts = 0;
8050 }
8051
8052 return sts;
8053}
8054
f281233d
JG		 8055static DEF_SCSI_QCMD(ncr53c8xx_queue_command)
8056
7d12e780 8057irqreturn_t ncr53c8xx_intr(int irq, void *dev_id)
1da177e4
LT		 8058{
8059 unsigned long flags;
8060 struct Scsi_Host *shost = (struct Scsi_Host *)dev_id;
8061 struct host_data *host_data = (struct host_data *)shost->hostdata;
8062 struct ncb *np = host_data->ncb;
8063 struct scsi_cmnd *done_list;
8064
8065#ifdef DEBUG_NCR53C8XX
8066 printk("ncr53c8xx : interrupt received\n");
8067#endif
8068
8069 if (DEBUG_FLAGS & DEBUG_TINY) printk ("[");
8070
8071 spin_lock_irqsave(&np->smp_lock, flags);
8072 ncr_exception(np);
8073 done_list = np->done_list;
8074 np->done_list = NULL;
8075 spin_unlock_irqrestore(&np->smp_lock, flags);
8076
8077 if (DEBUG_FLAGS & DEBUG_TINY) printk ("]\n");
8078
8079 if (done_list)
8080 ncr_flush_done_cmds(done_list);
8081 return IRQ_HANDLED;
8082}
8083
e99e88a9 8084static void ncr53c8xx_timeout(struct timer_list *t)
1da177e4 8085{
e99e88a9 8086 struct ncb *np = from_timer(np, t, timer);
1da177e4
LT		 8087 unsigned long flags;
8088 struct scsi_cmnd *done_list;
8089
8090 spin_lock_irqsave(&np->smp_lock, flags);
8091 ncr_timeout(np);
8092 done_list = np->done_list;
8093 np->done_list = NULL;
8094 spin_unlock_irqrestore(&np->smp_lock, flags);
8095
8096 if (done_list)
8097 ncr_flush_done_cmds(done_list);
8098}
8099
8100static int ncr53c8xx_bus_reset(struct scsi_cmnd *cmd)
8101{
8102 struct ncb *np = ((struct host_data *) cmd->device->host->hostdata)->ncb;
8103 int sts;
8104 unsigned long flags;
8105 struct scsi_cmnd *done_list;
8106
8107 /*
8108 * If the mid-level driver told us reset is synchronous, it seems
8109 * that we must call the done() callback for the involved command,
8110 * even if this command was not queued to the low-level driver,
8111 * before returning SUCCESS.
8112 */
8113
8114 spin_lock_irqsave(&np->smp_lock, flags);
8115 sts = ncr_reset_bus(np, cmd, 1);
8116
8117 done_list = np->done_list;
8118 np->done_list = NULL;
8119 spin_unlock_irqrestore(&np->smp_lock, flags);
8120
8121 ncr_flush_done_cmds(done_list);
8122
8123 return sts;
8124}
8125
8126#if 0 /* unused and broken */
8127static int ncr53c8xx_abort(struct scsi_cmnd *cmd)
8128{
8129 struct ncb *np = ((struct host_data *) cmd->device->host->hostdata)->ncb;
8130 int sts;
8131 unsigned long flags;
8132 struct scsi_cmnd *done_list;
8133
5cd049a5 8134 printk("ncr53c8xx_abort\n");
1da177e4
LT		 8135
8136 NCR_LOCK_NCB(np, flags);
8137
1da177e4
LT		 8138 sts = ncr_abort_command(np, cmd);
8139out:
8140 done_list = np->done_list;
8141 np->done_list = NULL;
8142 NCR_UNLOCK_NCB(np, flags);
8143
8144 ncr_flush_done_cmds(done_list);
8145
8146 return sts;
8147}
8148#endif
8149
8150
8151/*
8152** Scsi command waiting list management.
8153**
8154** It may happen that we cannot insert a scsi command into the start queue,
8155** in the following circumstances.
8156** Too few preallocated ccb(s),
8157** maxtags < cmd_per_lun of the Linux host control block,
8158** etc...
8159** Such scsi commands are inserted into a waiting list.
8160** When a scsi command complete, we try to requeue the commands of the
8161** waiting list.
8162*/
8163
8164#define next_wcmd host_scribble
8165
8166static void insert_into_waiting_list(struct ncb *np, struct scsi_cmnd *cmd)
8167{
8168 struct scsi_cmnd *wcmd;
8169
8170#ifdef DEBUG_WAITING_LIST
8171 printk("%s: cmd %lx inserted into waiting list\n", ncr_name(np), (u_long) cmd);
8172#endif
8173 cmd->next_wcmd = NULL;
8174 if (!(wcmd = np->waiting_list)) np->waiting_list = cmd;
8175 else {
172c122d 8176 while (wcmd->next_wcmd)
1da177e4
LT		 8177 wcmd = (struct scsi_cmnd *) wcmd->next_wcmd;
8178 wcmd->next_wcmd = (char *) cmd;
8179 }
8180}
8181
8182static struct scsi_cmnd *retrieve_from_waiting_list(int to_remove, struct ncb *np, struct scsi_cmnd *cmd)
8183{
8184 struct scsi_cmnd **pcmd = &np->waiting_list;
8185
8186 while (*pcmd) {
8187 if (cmd == *pcmd) {
8188 if (to_remove) {
8189 *pcmd = (struct scsi_cmnd *) cmd->next_wcmd;
8190 cmd->next_wcmd = NULL;
8191 }
8192#ifdef DEBUG_WAITING_LIST
8193 printk("%s: cmd %lx retrieved from waiting list\n", ncr_name(np), (u_long) cmd);
8194#endif
8195 return cmd;
8196 }
8197 pcmd = (struct scsi_cmnd **) &(*pcmd)->next_wcmd;
8198 }
8199 return NULL;
8200}
8201
8202static void process_waiting_list(struct ncb *np, int sts)
8203{
8204 struct scsi_cmnd *waiting_list, *wcmd;
8205
8206 waiting_list = np->waiting_list;
8207 np->waiting_list = NULL;
8208
8209#ifdef DEBUG_WAITING_LIST
8210 if (waiting_list) printk("%s: waiting_list=%lx processing sts=%d\n", ncr_name(np), (u_long) waiting_list, sts);
8211#endif
726792b2 8212 while ((wcmd = waiting_list) != NULL) {
1da177e4
LT		 8213 waiting_list = (struct scsi_cmnd *) wcmd->next_wcmd;
8214 wcmd->next_wcmd = NULL;
8215 if (sts == DID_OK) {
8216#ifdef DEBUG_WAITING_LIST
8217 printk("%s: cmd %lx trying to requeue\n", ncr_name(np), (u_long) wcmd);
8218#endif
8219 sts = ncr_queue_command(np, wcmd);
8220 }
8221 if (sts != DID_OK) {
8222#ifdef DEBUG_WAITING_LIST
8223 printk("%s: cmd %lx done forced sts=%d\n", ncr_name(np), (u_long) wcmd, sts);
8224#endif
78adb2bc 8225 wcmd->result = sts << 16;
1da177e4
LT		 8226 ncr_queue_done_cmd(np, wcmd);
8227 }
8228 }
8229}
8230
8231#undef next_wcmd
8232
ee959b00
TJ		 8233static ssize_t show_ncr53c8xx_revision(struct device *dev,
8234 struct device_attribute *attr, char *buf)
1da177e4
LT		 8235{
8236 struct Scsi_Host *host = class_to_shost(dev);
8237 struct host_data *host_data = (struct host_data *)host->hostdata;
8238
8239 return snprintf(buf, 20, "0x%x\n", host_data->ncb->revision_id);
8240}
8241
ee959b00 8242static struct device_attribute ncr53c8xx_revision_attr = {
1da177e4
LT		 8243 .attr = { .name = "revision", .mode = S_IRUGO, },
8244 .show = show_ncr53c8xx_revision,
8245};
8246
ee959b00 8247static struct device_attribute *ncr53c8xx_host_attrs[] = {
1da177e4
LT		 8248 &ncr53c8xx_revision_attr,
8249 NULL
8250};
8251
8252/*==========================================================
8253**
8254** Boot command line.
8255**
8256**==========================================================
8257*/
8258#ifdef MODULE
8259char *ncr53c8xx; /* command line passed by insmod */
8260module_param(ncr53c8xx, charp, 0);
8261#endif
8262
db3a8815 8263#ifndef MODULE
1da177e4
LT		 8264static int __init ncr53c8xx_setup(char *str)
8265{
8266 return sym53c8xx__setup(str);
8267}
8268
1da177e4
LT		 8269__setup("ncr53c8xx=", ncr53c8xx_setup);
8270#endif
8271
8272
8273/*
8274 * Host attach and initialisations.
8275 *
8276 * Allocate host data and ncb structure.
8277 * Request IO region and remap MMIO region.
8278 * Do chip initialization.
8279 * If all is OK, install interrupt handling and
8280 * start the timer daemon.
8281 */
8282struct Scsi_Host * __init ncr_attach(struct scsi_host_template *tpnt,
8283 int unit, struct ncr_device *device)
8284{
8285 struct host_data *host_data;
8286 struct ncb *np = NULL;
8287 struct Scsi_Host *instance = NULL;
8288 u_long flags = 0;
8289 int i;
8290
8291 if (!tpnt->name)
8292 tpnt->name = SCSI_NCR_DRIVER_NAME;
8293 if (!tpnt->shost_attrs)
8294 tpnt->shost_attrs = ncr53c8xx_host_attrs;
8295
8296 tpnt->queuecommand = ncr53c8xx_queue_command;
8297 tpnt->slave_configure = ncr53c8xx_slave_configure;
8298 tpnt->slave_alloc = ncr53c8xx_slave_alloc;
8299 tpnt->eh_bus_reset_handler = ncr53c8xx_bus_reset;
8300 tpnt->can_queue = SCSI_NCR_CAN_QUEUE;
8301 tpnt->this_id = 7;
8302 tpnt->sg_tablesize = SCSI_NCR_SG_TABLESIZE;
8303 tpnt->cmd_per_lun = SCSI_NCR_CMD_PER_LUN;
1da177e4
LT		 8304
8305 if (device->differential)
8306 driver_setup.diff_support = device->differential;
8307
8308 printk(KERN_INFO "ncr53c720-%d: rev 0x%x irq %d\n",
8309 unit, device->chip.revision_id, device->slot.irq);
8310
8311 instance = scsi_host_alloc(tpnt, sizeof(*host_data));
8312 if (!instance)
8313 goto attach_error;
8314 host_data = (struct host_data *) instance->hostdata;
8315
8316 np = __m_calloc_dma(device->dev, sizeof(struct ncb), "NCB");
8317 if (!np)
8318 goto attach_error;
8319 spin_lock_init(&np->smp_lock);
8320 np->dev = device->dev;
8321 np->p_ncb = vtobus(np);
8322 host_data->ncb = np;
8323
8324 np->ccb = m_calloc_dma(sizeof(struct ccb), "CCB");
8325 if (!np->ccb)
8326 goto attach_error;
8327
8328 /* Store input information in the host data structure. */
8329 np->unit = unit;
8330 np->verbose = driver_setup.verbose;
8331 sprintf(np->inst_name, "ncr53c720-%d", np->unit);
8332 np->revision_id = device->chip.revision_id;
8333 np->features = device->chip.features;
8334 np->clock_divn = device->chip.nr_divisor;
8335 np->maxoffs = device->chip.offset_max;
8336 np->maxburst = device->chip.burst_max;
8337 np->myaddr = device->host_id;
8338
8339 /* Allocate SCRIPTS areas. */
8340 np->script0 = m_calloc_dma(sizeof(struct script), "SCRIPT");
8341 if (!np->script0)
8342 goto attach_error;
8343 np->scripth0 = m_calloc_dma(sizeof(struct scripth), "SCRIPTH");
8344 if (!np->scripth0)
8345 goto attach_error;
8346
e99e88a9 8347 timer_setup(&np->timer, ncr53c8xx_timeout, 0);
1da177e4
LT		 8348
8349 /* Try to map the controller chip to virtual and physical memory. */
8350
8351 np->paddr = device->slot.base;
8352 np->paddr2 = (np->features & FE_RAM) ? device->slot.base_2 : 0;
8353
8354 if (device->slot.base_v)
8355 np->vaddr = device->slot.base_v;
8356 else
8357 np->vaddr = ioremap(device->slot.base_c, 128);
8358
8359 if (!np->vaddr) {
8360 printk(KERN_ERR
8361 "%s: can't map memory mapped IO region\n",ncr_name(np));
8362 goto attach_error;
8363 } else {
8364 if (bootverbose > 1)
8365 printk(KERN_INFO
8366 "%s: using memory mapped IO at virtual address 0x%lx\n", ncr_name(np), (u_long) np->vaddr);
8367 }
8368
8369 /* Make the controller's registers available. Now the INB INW INL
8370 * OUTB OUTW OUTL macros can be used safely.
8371 */
8372
8373 np->reg = (struct ncr_reg __iomem *)np->vaddr;
8374
8375 /* Do chip dependent initialization. */
8376 ncr_prepare_setting(np);
8377
8378 if (np->paddr2 && sizeof(struct script) > 4096) {
8379 np->paddr2 = 0;
8380 printk(KERN_WARNING "%s: script too large, NOT using on chip RAM.\n",
8381 ncr_name(np));
8382 }
8383
8384 instance->max_channel = 0;
8385 instance->this_id = np->myaddr;
8386 instance->max_id = np->maxwide ? 16 : 8;
8387 instance->max_lun = SCSI_NCR_MAX_LUN;
8388 instance->base = (unsigned long) np->reg;
8389 instance->irq = device->slot.irq;
8390 instance->unique_id = device->slot.base;
8391 instance->dma_channel = 0;
8392 instance->cmd_per_lun = MAX_TAGS;
8393 instance->can_queue = (MAX_START-4);
8394 /* This can happen if you forget to call ncr53c8xx_init from
8395 * your module_init */
8396 BUG_ON(!ncr53c8xx_transport_template);
8397 instance->transportt = ncr53c8xx_transport_template;
1da177e4
LT		 8398
8399 /* Patch script to physical addresses */
8400 ncr_script_fill(&script0, &scripth0);
8401
8402 np->scripth = np->scripth0;
8403 np->p_scripth = vtobus(np->scripth);
8404 np->p_script = (np->paddr2) ? np->paddr2 : vtobus(np->script0);
8405
8406 ncr_script_copy_and_bind(np, (ncrcmd *) &script0,
8407 (ncrcmd *) np->script0, sizeof(struct script));
8408 ncr_script_copy_and_bind(np, (ncrcmd *) &scripth0,
8409 (ncrcmd *) np->scripth0, sizeof(struct scripth));
8410 np->ccb->p_ccb = vtobus (np->ccb);
8411
8412 /* Patch the script for LED support. */
8413
8414 if (np->features & FE_LED0) {
8415 np->script0->idle[0] =
8416 cpu_to_scr(SCR_REG_REG(gpreg, SCR_OR, 0x01));
8417 np->script0->reselected[0] =
8418 cpu_to_scr(SCR_REG_REG(gpreg, SCR_AND, 0xfe));
8419 np->script0->start[0] =
8420 cpu_to_scr(SCR_REG_REG(gpreg, SCR_AND, 0xfe));
8421 }
8422
8423 /*
8424 * Look for the target control block of this nexus.
8425 * For i = 0 to 3
8426 * JUMP ^ IFTRUE (MASK (i, 3)), @(next_lcb)
8427 */
8428 for (i = 0 ; i < 4 ; i++) {
8429 np->jump_tcb[i].l_cmd =
8430 cpu_to_scr((SCR_JUMP ^ IFTRUE (MASK (i, 3))));
8431 np->jump_tcb[i].l_paddr =
8432 cpu_to_scr(NCB_SCRIPTH_PHYS (np, bad_target));
8433 }
8434
8435 ncr_chip_reset(np, 100);
8436
8437 /* Now check the cache handling of the chipset. */
8438
8439 if (ncr_snooptest(np)) {
8440 printk(KERN_ERR "CACHE INCORRECTLY CONFIGURED.\n");
8441 goto attach_error;
8442 }
8443
8444 /* Install the interrupt handler. */
8445 np->irq = device->slot.irq;
8446
8447 /* Initialize the fixed part of the default ccb. */
8448 ncr_init_ccb(np, np->ccb);
8449
8450 /*
8451 * After SCSI devices have been opened, we cannot reset the bus
8452 * safely, so we do it here. Interrupt handler does the real work.
8453 * Process the reset exception if interrupts are not enabled yet.
8454 * Then enable disconnects.
8455 */
8456 spin_lock_irqsave(&np->smp_lock, flags);
8457 if (ncr_reset_scsi_bus(np, 0, driver_setup.settle_delay) != 0) {
8458 printk(KERN_ERR "%s: FATAL ERROR: CHECK SCSI BUS - CABLES, TERMINATION, DEVICE POWER etc.!\n", ncr_name(np));
8459
8460 spin_unlock_irqrestore(&np->smp_lock, flags);
8461 goto attach_error;
8462 }
8463 ncr_exception(np);
8464
8465 np->disc = 1;
8466
8467 /*
8468 * The middle-level SCSI driver does not wait for devices to settle.
8469 * Wait synchronously if more than 2 seconds.
8470 */
8471 if (driver_setup.settle_delay > 2) {
8472 printk(KERN_INFO "%s: waiting %d seconds for scsi devices to settle...\n",
8473 ncr_name(np), driver_setup.settle_delay);
8474 mdelay(1000 * driver_setup.settle_delay);
8475 }
8476
8477 /* start the timeout daemon */
8478 np->lasttime=0;
8479 ncr_timeout (np);
8480
8481 /* use SIMPLE TAG messages by default */
8482#ifdef SCSI_NCR_ALWAYS_SIMPLE_TAG
b0dc1db1 8483 np->order = SIMPLE_QUEUE_TAG;
1da177e4
LT		 8484#endif
8485
8486 spin_unlock_irqrestore(&np->smp_lock, flags);
8487
8488 return instance;
8489
8490 attach_error:
8491 if (!instance)
8492 return NULL;
8493 printk(KERN_INFO "%s: detaching...\n", ncr_name(np));
8494 if (!np)
8495 goto unregister;
8496 if (np->scripth0)
8497 m_free_dma(np->scripth0, sizeof(struct scripth), "SCRIPTH");
8498 if (np->script0)
8499 m_free_dma(np->script0, sizeof(struct script), "SCRIPT");
8500 if (np->ccb)
8501 m_free_dma(np->ccb, sizeof(struct ccb), "CCB");
8502 m_free_dma(np, sizeof(struct ncb), "NCB");
8503 host_data->ncb = NULL;
8504
8505 unregister:
8506 scsi_host_put(instance);
8507
8508 return NULL;
8509}
8510
8511
dffe807c 8512void ncr53c8xx_release(struct Scsi_Host *host)
1da177e4 8513{
dffe807c 8514 struct host_data *host_data = shost_priv(host);
1da177e4
LT		 8515#ifdef DEBUG_NCR53C8XX
8516 printk("ncr53c8xx: release\n");
8517#endif
dffe807c 8518 if (host_data->ncb)
1da177e4 8519 ncr_detach(host_data->ncb);
dffe807c 8520 scsi_host_put(host);
1da177e4
LT		 8521}
8522
8523static void ncr53c8xx_set_period(struct scsi_target *starget, int period)
8524{
8525 struct Scsi_Host *shost = dev_to_shost(starget->dev.parent);
8526 struct ncb *np = ((struct host_data *)shost->hostdata)->ncb;
8527 struct tcb *tp = &np->target[starget->id];
8528
8529 if (period > np->maxsync)
8530 period = np->maxsync;
8531 else if (period < np->minsync)
8532 period = np->minsync;
8533
8534 tp->usrsync = period;
8535
8536 ncr_negotiate(np, tp);
8537}
8538
8539static void ncr53c8xx_set_offset(struct scsi_target *starget, int offset)
8540{
8541 struct Scsi_Host *shost = dev_to_shost(starget->dev.parent);
8542 struct ncb *np = ((struct host_data *)shost->hostdata)->ncb;
8543 struct tcb *tp = &np->target[starget->id];
8544
8545 if (offset > np->maxoffs)
8546 offset = np->maxoffs;
8547 else if (offset < 0)
8548 offset = 0;
8549
8550 tp->maxoffs = offset;
8551
8552 ncr_negotiate(np, tp);
8553}
8554
8555static void ncr53c8xx_set_width(struct scsi_target *starget, int width)
8556{
8557 struct Scsi_Host *shost = dev_to_shost(starget->dev.parent);
8558 struct ncb *np = ((struct host_data *)shost->hostdata)->ncb;
8559 struct tcb *tp = &np->target[starget->id];
8560
8561 if (width > np->maxwide)
8562 width = np->maxwide;
8563 else if (width < 0)
8564 width = 0;
8565
8566 tp->usrwide = width;
8567
8568 ncr_negotiate(np, tp);
8569}
8570
8571static void ncr53c8xx_get_signalling(struct Scsi_Host *shost)
8572{
8573 struct ncb *np = ((struct host_data *)shost->hostdata)->ncb;
8574 enum spi_signal_type type;
8575
8576 switch (np->scsi_mode) {
8577 case SMODE_SE:
8578 type = SPI_SIGNAL_SE;
8579 break;
8580 case SMODE_HVD:
8581 type = SPI_SIGNAL_HVD;
8582 break;
8583 default:
8584 type = SPI_SIGNAL_UNKNOWN;
8585 break;
8586 }
8587 spi_signalling(shost) = type;
8588}
8589
8590static struct spi_function_template ncr53c8xx_transport_functions = {
8591 .set_period = ncr53c8xx_set_period,
8592 .show_period = 1,
8593 .set_offset = ncr53c8xx_set_offset,
8594 .show_offset = 1,
8595 .set_width = ncr53c8xx_set_width,
8596 .show_width = 1,
8597 .get_signalling = ncr53c8xx_get_signalling,
8598};
8599
8600int __init ncr53c8xx_init(void)
8601{
8602 ncr53c8xx_transport_template = spi_attach_transport(&ncr53c8xx_transport_functions);
8603 if (!ncr53c8xx_transport_template)
8604 return -ENODEV;
8605 return 0;
8606}
8607
8608void ncr53c8xx_exit(void)
8609{
8610 spi_release_transport(ncr53c8xx_transport_template);
8611}
Linux 6.x block layer and io_uring tree(s)