[linux-2.6-block.git] / drivers / scsi / mvumi.h

/*
  * Marvell UMI head file
  *
  * Copyright 2011 Marvell. <jyli@marvell.com>
  *
  * This file is licensed under GPLv2.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; version 2 of the
  * License.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  * General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  * USA
 */

#ifndef MVUMI_H
#define MVUMI_H

#define MAX_BASE_ADDRESS	6

#define VER_MAJOR		1
#define VER_MINOR		1
#define VER_OEM			0
#define VER_BUILD		1500

#define MV_DRIVER_NAME			"mvumi"
#define PCI_VENDOR_ID_MARVELL_2		0x1b4b
#define PCI_DEVICE_ID_MARVELL_MV9143	0x9143
#define PCI_DEVICE_ID_MARVELL_MV9580	0x9580

#define MVUMI_INTERNAL_CMD_WAIT_TIME	45
#define MVUMI_INQUIRY_LENGTH		44
#define MVUMI_INQUIRY_UUID_OFF		36
#define MVUMI_INQUIRY_UUID_LEN		8

#define IS_DMA64			(sizeof(dma_addr_t) == 8)

enum mvumi_qc_result {
	MV_QUEUE_COMMAND_RESULT_SENT = 0,
	MV_QUEUE_COMMAND_RESULT_NO_RESOURCE,
};

struct mvumi_hw_regs {
	/* For CPU */
	void *main_int_cause_reg;
	void *enpointa_mask_reg;
	void *enpointb_mask_reg;
	void *rstoutn_en_reg;
	void *ctrl_sts_reg;
	void *rstoutn_mask_reg;
	void *sys_soft_rst_reg;

	/* For Doorbell */
	void *pciea_to_arm_drbl_reg;
	void *arm_to_pciea_drbl_reg;
	void *arm_to_pciea_mask_reg;
	void *pciea_to_arm_msg0;
	void *pciea_to_arm_msg1;
	void *arm_to_pciea_msg0;
	void *arm_to_pciea_msg1;

	/* reset register */
	void *reset_request;
	void *reset_enable;

	/* For Message Unit */
	void *inb_list_basel;
	void *inb_list_baseh;
	void *inb_aval_count_basel;
	void *inb_aval_count_baseh;
	void *inb_write_pointer;
	void *inb_read_pointer;
	void *outb_list_basel;
	void *outb_list_baseh;
	void *outb_copy_basel;
	void *outb_copy_baseh;
	void *outb_copy_pointer;
	void *outb_read_pointer;
	void *inb_isr_cause;
	void *outb_isr_cause;
	void *outb_coal_cfg;
	void *outb_coal_timeout;

	/* Bit setting for HW */
	u32 int_comaout;
	u32 int_comaerr;
	u32 int_dl_cpu2pciea;
	u32 int_mu;
	u32 int_drbl_int_mask;
	u32 int_main_int_mask;
	u32 cl_pointer_toggle;
	u32 cl_slot_num_mask;
	u32 clic_irq;
	u32 clic_in_err;
	u32 clic_out_err;
};

struct mvumi_dyn_list_entry {
	u32 src_low_addr;
	u32 src_high_addr;
	u32 if_length;
	u32 reserve;
};

#define SCSI_CMD_MARVELL_SPECIFIC	0xE1
#define CDB_CORE_MODULE			0x1
#define CDB_CORE_SHUTDOWN		0xB

enum {
	DRBL_HANDSHAKE			= 1 << 0,
	DRBL_SOFT_RESET			= 1 << 1,
	DRBL_BUS_CHANGE			= 1 << 2,
	DRBL_EVENT_NOTIFY		= 1 << 3,
	DRBL_MU_RESET			= 1 << 4,
	DRBL_HANDSHAKE_ISR		= DRBL_HANDSHAKE,

	/*
	* Command flag is the flag for the CDB command itself
	*/
	/* 1-non data; 0-data command */
	CMD_FLAG_NON_DATA		= 1 << 0,
	CMD_FLAG_DMA			= 1 << 1,
	CMD_FLAG_PIO			= 1 << 2,
	/* 1-host read data */
	CMD_FLAG_DATA_IN		= 1 << 3,
	/* 1-host write data */
	CMD_FLAG_DATA_OUT		= 1 << 4,
	CMD_FLAG_PRDT_IN_HOST		= 1 << 5,
};

#define APICDB0_EVENT			0xF4
#define APICDB1_EVENT_GETEVENT		0
#define APICDB1_HOST_GETEVENT		1
#define MAX_EVENTS_RETURNED		6

#define DEVICE_OFFLINE	0
#define DEVICE_ONLINE	1

struct mvumi_hotplug_event {
	u16 size;
	u8 dummy[2];
	u8 bitmap[0];
};

struct mvumi_driver_event {
	u32	time_stamp;
	u32	sequence_no;
	u32	event_id;
	u8	severity;
	u8	param_count;
	u16	device_id;
	u32	params[4];
	u8	sense_data_length;
	u8	Reserved1;
	u8	sense_data[30];
};

struct mvumi_event_req {
	unsigned char	count;
	unsigned char	reserved[3];
	struct mvumi_driver_event  events[MAX_EVENTS_RETURNED];
};

struct mvumi_events_wq {
	struct work_struct work_q;
	struct mvumi_hba *mhba;
	unsigned int event;
	void *param;
};

#define HS_CAPABILITY_SUPPORT_COMPACT_SG	(1U << 4)
#define HS_CAPABILITY_SUPPORT_PRD_HOST		(1U << 5)
#define HS_CAPABILITY_SUPPORT_DYN_SRC		(1U << 6)
#define HS_CAPABILITY_NEW_PAGE_IO_DEPTH_DEF	(1U << 14)

#define MVUMI_MAX_SG_ENTRY	32
#define SGD_EOT			(1L << 27)
#define SGD_EOT_CP		(1L << 22)

struct mvumi_sgl {
	u32	baseaddr_l;
	u32	baseaddr_h;
	u32	flags;
	u32	size;
};
struct mvumi_compact_sgl {
	u32	baseaddr_l;
	u32	baseaddr_h;
	u32	flags;
};

#define GET_COMPACT_SGD_SIZE(sgd)	\
	((((struct mvumi_compact_sgl *)(sgd))->flags) & 0x3FFFFFL)

#define SET_COMPACT_SGD_SIZE(sgd, sz) do {			\
	(((struct mvumi_compact_sgl *)(sgd))->flags) &= ~0x3FFFFFL;	\
	(((struct mvumi_compact_sgl *)(sgd))->flags) |= (sz);		\
} while (0)
#define sgd_getsz(_mhba, sgd, sz) do {				\
	if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG)	\
		(sz) = GET_COMPACT_SGD_SIZE(sgd);	\
	else \
		(sz) = (sgd)->size;			\
} while (0)

#define sgd_setsz(_mhba, sgd, sz) do {				\
	if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG)	\
		SET_COMPACT_SGD_SIZE(sgd, sz);		\
	else \
		(sgd)->size = (sz);			\
} while (0)

#define sgd_inc(_mhba, sgd) do {	\
	if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG)	\
		sgd = (struct mvumi_sgl *)(((unsigned char *) (sgd)) + 12); \
	else \
		sgd = (struct mvumi_sgl *)(((unsigned char *) (sgd)) + 16); \
} while (0)

struct mvumi_res {
	struct list_head entry;
	dma_addr_t bus_addr;
	void *virt_addr;
	unsigned int size;
	unsigned short type;	/* enum Resource_Type */
};

/* Resource type */
enum resource_type {
	RESOURCE_CACHED_MEMORY = 0,
	RESOURCE_UNCACHED_MEMORY
};

struct mvumi_sense_data {
	u8 error_code:7;
	u8 valid:1;
	u8 segment_number;
	u8 sense_key:4;
	u8 reserved:1;
	u8 incorrect_length:1;
	u8 end_of_media:1;
	u8 file_mark:1;
	u8 information[4];
	u8 additional_sense_length;
	u8 command_specific_information[4];
	u8 additional_sense_code;
	u8 additional_sense_code_qualifier;
	u8 field_replaceable_unit_code;
	u8 sense_key_specific[3];
};

/* Request initiator must set the status to REQ_STATUS_PENDING. */
#define REQ_STATUS_PENDING		0x80

struct mvumi_cmd {
	struct list_head queue_pointer;
	struct mvumi_msg_frame *frame;
	dma_addr_t frame_phys;
	struct scsi_cmnd *scmd;
	atomic_t sync_cmd;
	void *data_buf;
	unsigned short request_id;
	unsigned char cmd_status;
};

/*
 * the function type of the in bound frame
 */
#define CL_FUN_SCSI_CMD			0x1

struct mvumi_msg_frame {
	u16 device_id;
	u16 tag;
	u8 cmd_flag;
	u8 req_function;
	u8 cdb_length;
	u8 sg_counts;
	u32 data_transfer_length;
	u16 request_id;
	u16 reserved1;
	u8 cdb[MAX_COMMAND_SIZE];
	u32 payload[1];
};

/*
 * the respond flag for data_payload of the out bound frame
 */
#define CL_RSP_FLAG_NODATA		0x0
#define CL_RSP_FLAG_SENSEDATA		0x1

struct mvumi_rsp_frame {
	u16 device_id;
	u16 tag;
	u8 req_status;
	u8 rsp_flag;	/* Indicates the type of Data_Payload.*/
	u16 request_id;
	u32 payload[1];
};

struct mvumi_ob_data {
	struct list_head list;
	unsigned char data[0];
};

struct version_info {
	u32 ver_major;
	u32 ver_minor;
	u32 ver_oem;
	u32 ver_build;
};

#define FW_MAX_DELAY			30
#define MVUMI_FW_BUSY			(1U << 0)
#define MVUMI_FW_ATTACH			(1U << 1)
#define MVUMI_FW_ALLOC			(1U << 2)

/*
 * State is the state of the MU
 */
#define FW_STATE_IDLE			0
#define FW_STATE_STARTING		1
#define FW_STATE_HANDSHAKING		2
#define FW_STATE_STARTED		3
#define FW_STATE_ABORT			4

#define HANDSHAKE_SIGNATURE		0x5A5A5A5AL
#define HANDSHAKE_READYSTATE		0x55AA5AA5L
#define HANDSHAKE_DONESTATE		0x55AAA55AL

/* HandShake Status definition */
#define HS_STATUS_OK			1
#define HS_STATUS_ERR			2
#define HS_STATUS_INVALID		3

/* HandShake State/Cmd definition */
#define HS_S_START			1
#define HS_S_RESET			2
#define HS_S_PAGE_ADDR			3
#define HS_S_QUERY_PAGE			4
#define HS_S_SEND_PAGE			5
#define HS_S_END			6
#define HS_S_ABORT			7
#define HS_PAGE_VERIFY_SIZE		128

#define HS_GET_STATE(a)			(a & 0xFFFF)
#define HS_GET_STATUS(a)		((a & 0xFFFF0000) >> 16)
#define HS_SET_STATE(a, b)		(a |= (b & 0xFFFF))
#define HS_SET_STATUS(a, b)		(a |= ((b & 0xFFFF) << 16))

/* handshake frame */
struct mvumi_hs_frame {
	u16 size;
	/* host information */
	u8 host_type;
	u8 reserved_1[1];
	struct version_info host_ver; /* bios or driver version */

	/* controller information */
	u32 system_io_bus;
	u32 slot_number;
	u32 intr_level;
	u32 intr_vector;

	/* communication list configuration */
	u32 ib_baseaddr_l;
	u32 ib_baseaddr_h;
	u32 ob_baseaddr_l;
	u32 ob_baseaddr_h;

	u8 ib_entry_size;
	u8 ob_entry_size;
	u8 ob_depth;
	u8 ib_depth;

	/* system time */
	u64 seconds_since1970;
};

struct mvumi_hs_header {
	u8	page_code;
	u8	checksum;
	u16	frame_length;
	u32	frame_content[1];
};

/*
 * the page code type of the handshake header
 */
#define HS_PAGE_FIRM_CAP	0x1
#define HS_PAGE_HOST_INFO	0x2
#define HS_PAGE_FIRM_CTL	0x3
#define HS_PAGE_CL_INFO		0x4
#define HS_PAGE_TOTAL		0x5

#define HSP_SIZE(i)	sizeof(struct mvumi_hs_page##i)

#define HSP_MAX_SIZE ({					\
	int size, m1, m2;				\
	m1 = max(HSP_SIZE(1), HSP_SIZE(3));		\
	m2 = max(HSP_SIZE(2), HSP_SIZE(4));		\
	size = max(m1, m2);				\
	size;						\
})

/* The format of the page code for Firmware capability */
struct mvumi_hs_page1 {
	u8 pagecode;
	u8 checksum;
	u16 frame_length;

	u16 number_of_ports;
	u16 max_devices_support;
	u16 max_io_support;
	u16 umi_ver;
	u32 max_transfer_size;
	struct version_info fw_ver;
	u8 cl_in_max_entry_size;
	u8 cl_out_max_entry_size;
	u8 cl_inout_list_depth;
	u8 total_pages;
	u16 capability;
	u16 reserved1;
};

/* The format of the page code for Host information */
struct mvumi_hs_page2 {
	u8 pagecode;
	u8 checksum;
	u16 frame_length;

	u8 host_type;
	u8 host_cap;
	u8 reserved[2];
	struct version_info host_ver;
	u32 system_io_bus;
	u32 slot_number;
	u32 intr_level;
	u32 intr_vector;
	u64 seconds_since1970;
};

/* The format of the page code for firmware control  */
struct mvumi_hs_page3 {
	u8	pagecode;
	u8	checksum;
	u16	frame_length;
	u16	control;
	u8	reserved[2];
	u32	host_bufferaddr_l;
	u32	host_bufferaddr_h;
	u32	host_eventaddr_l;
	u32	host_eventaddr_h;
};

struct mvumi_hs_page4 {
	u8	pagecode;
	u8	checksum;
	u16	frame_length;
	u32	ib_baseaddr_l;
	u32	ib_baseaddr_h;
	u32	ob_baseaddr_l;
	u32	ob_baseaddr_h;
	u8	ib_entry_size;
	u8	ob_entry_size;
	u8	ob_depth;
	u8	ib_depth;
};

struct mvumi_tag {
	unsigned short *stack;
	unsigned short top;
	unsigned short size;
};

struct mvumi_device {
	struct list_head list;
	struct scsi_device *sdev;
	u64	wwid;
	u8	dev_type;
	int	id;
};

struct mvumi_hba {
	void *base_addr[MAX_BASE_ADDRESS];
	u32 pci_base[MAX_BASE_ADDRESS];
	void *mmio;
	struct list_head cmd_pool;
	struct Scsi_Host *shost;
	wait_queue_head_t int_cmd_wait_q;
	struct pci_dev *pdev;
	unsigned int unique_id;
	atomic_t fw_outstanding;
	struct mvumi_instance_template *instancet;

	void *ib_list;
	dma_addr_t ib_list_phys;

	void *ib_frame;
	dma_addr_t ib_frame_phys;

	void *ob_list;
	dma_addr_t ob_list_phys;

	void *ib_shadow;
	dma_addr_t ib_shadow_phys;

	void *ob_shadow;
	dma_addr_t ob_shadow_phys;

	void *handshake_page;
	dma_addr_t handshake_page_phys;

	unsigned int global_isr;
	unsigned int isr_status;

	unsigned short max_sge;
	unsigned short max_target_id;
	unsigned char *target_map;
	unsigned int max_io;
	unsigned int list_num_io;
	unsigned int ib_max_size;
	unsigned int ob_max_size;
	unsigned int ib_max_size_setting;
	unsigned int ob_max_size_setting;
	unsigned int max_transfer_size;
	unsigned char hba_total_pages;
	unsigned char fw_flag;
	unsigned char request_id_enabled;
	unsigned char eot_flag;
	unsigned short hba_capability;
	unsigned short io_seq;

	unsigned int ib_cur_slot;
	unsigned int ob_cur_slot;
	unsigned int fw_state;
	struct mutex sas_discovery_mutex;

	struct list_head ob_data_list;
	struct list_head free_ob_list;
	struct list_head res_list;
	struct list_head waiting_req_list;

	struct mvumi_tag tag_pool;
	struct mvumi_cmd **tag_cmd;
	struct mvumi_hw_regs *regs;
	struct mutex device_lock;
	struct list_head mhba_dev_list;
	struct list_head shost_dev_list;
	struct task_struct *dm_thread;
	atomic_t pnp_count;
};

struct mvumi_instance_template {
	void (*fire_cmd) (struct mvumi_hba *, struct mvumi_cmd *);
	void (*enable_intr) (struct mvumi_hba *);
	void (*disable_intr) (struct mvumi_hba *);
	int (*clear_intr) (void *);
	unsigned int (*read_fw_status_reg) (struct mvumi_hba *);
	unsigned int (*check_ib_list) (struct mvumi_hba *);
	int (*check_ob_list) (struct mvumi_hba *, unsigned int *,
			      unsigned int *);
	int (*reset_host) (struct mvumi_hba *);
};

extern struct timezone sys_tz;
#endif
Commit	Line	Data
f0c568a4 JL	1	/*
	2	* Marvell UMI head file
	3	*
	4	* Copyright 2011 Marvell. <jyli@marvell.com>
	5	*
	6	* This file is licensed under GPLv2.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; version 2 of the
	11	* License.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	16	* General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
	21	* USA
	22	*/
	23
	24	#ifndef MVUMI_H
	25	#define MVUMI_H
	26
	27	#define MAX_BASE_ADDRESS 6
	28
	29	#define VER_MAJOR 1
	30	#define VER_MINOR 1
	31	#define VER_OEM 0
	32	#define VER_BUILD 1500
	33
	34	#define MV_DRIVER_NAME "mvumi"
	35	#define PCI_VENDOR_ID_MARVELL_2 0x1b4b
	36	#define PCI_DEVICE_ID_MARVELL_MV9143 0x9143
bd756dde	37	#define PCI_DEVICE_ID_MARVELL_MV9580 0x9580
f0c568a4 JL	38
f0c568a4 JL	39	#define MVUMI_INTERNAL_CMD_WAIT_TIME 45
bd756dde SF	40	#define MVUMI_INQUIRY_LENGTH 44
	41	#define MVUMI_INQUIRY_UUID_OFF 36
	42	#define MVUMI_INQUIRY_UUID_LEN 8
f0c568a4 JL	43
	44	#define IS_DMA64 (sizeof(dma_addr_t) == 8)
	45
	46	enum mvumi_qc_result {
bd756dde	47	MV_QUEUE_COMMAND_RESULT_SENT = 0,
f0c568a4 JL	48	MV_QUEUE_COMMAND_RESULT_NO_RESOURCE,
	49	};
	50
bd756dde SF	51	struct mvumi_hw_regs {
	52	/* For CPU */
	53	void *main_int_cause_reg;
	54	void *enpointa_mask_reg;
	55	void *enpointb_mask_reg;
	56	void *rstoutn_en_reg;
	57	void *ctrl_sts_reg;
	58	void *rstoutn_mask_reg;
	59	void *sys_soft_rst_reg;
	60
	61	/* For Doorbell */
	62	void *pciea_to_arm_drbl_reg;
	63	void *arm_to_pciea_drbl_reg;
	64	void *arm_to_pciea_mask_reg;
	65	void *pciea_to_arm_msg0;
	66	void *pciea_to_arm_msg1;
	67	void *arm_to_pciea_msg0;
	68	void *arm_to_pciea_msg1;
	69
	70	/* reset register */
	71	void *reset_request;
	72	void *reset_enable;
	73
	74	/* For Message Unit */
	75	void *inb_list_basel;
	76	void *inb_list_baseh;
	77	void *inb_aval_count_basel;
	78	void *inb_aval_count_baseh;
	79	void *inb_write_pointer;
	80	void *inb_read_pointer;
	81	void *outb_list_basel;
	82	void *outb_list_baseh;
	83	void *outb_copy_basel;
	84	void *outb_copy_baseh;
	85	void *outb_copy_pointer;
	86	void *outb_read_pointer;
	87	void *inb_isr_cause;
	88	void *outb_isr_cause;
	89	void *outb_coal_cfg;
	90	void *outb_coal_timeout;
	91
	92	/* Bit setting for HW */
	93	u32 int_comaout;
	94	u32 int_comaerr;
	95	u32 int_dl_cpu2pciea;
	96	u32 int_mu;
	97	u32 int_drbl_int_mask;
	98	u32 int_main_int_mask;
	99	u32 cl_pointer_toggle;
	100	u32 cl_slot_num_mask;
	101	u32 clic_irq;
	102	u32 clic_in_err;
	103	u32 clic_out_err;
	104	};
f0c568a4	105
bd756dde SF	106	struct mvumi_dyn_list_entry {
	107	u32 src_low_addr;
	108	u32 src_high_addr;
	109	u32 if_length;
	110	u32 reserve;
	111	};
f0c568a4	112
bd756dde SF	113	#define SCSI_CMD_MARVELL_SPECIFIC 0xE1
	114	#define CDB_CORE_MODULE 0x1
	115	#define CDB_CORE_SHUTDOWN 0xB
f0c568a4	116
bd756dde	117	enum {
f0c568a4 JL	118	DRBL_HANDSHAKE = 1 << 0,
	119	DRBL_SOFT_RESET = 1 << 1,
	120	DRBL_BUS_CHANGE = 1 << 2,
	121	DRBL_EVENT_NOTIFY = 1 << 3,
	122	DRBL_MU_RESET = 1 << 4,
	123	DRBL_HANDSHAKE_ISR = DRBL_HANDSHAKE,
	124
f0c568a4 JL	125	/*
	126	* Command flag is the flag for the CDB command itself
	127	*/
	128	/* 1-non data; 0-data command */
	129	CMD_FLAG_NON_DATA = 1 << 0,
	130	CMD_FLAG_DMA = 1 << 1,
	131	CMD_FLAG_PIO = 1 << 2,
	132	/* 1-host read data */
	133	CMD_FLAG_DATA_IN = 1 << 3,
	134	/* 1-host write data */
	135	CMD_FLAG_DATA_OUT = 1 << 4,
bd756dde	136	CMD_FLAG_PRDT_IN_HOST = 1 << 5,
f0c568a4 JL	137	};
	138
	139	#define APICDB0_EVENT 0xF4
	140	#define APICDB1_EVENT_GETEVENT 0
bd756dde	141	#define APICDB1_HOST_GETEVENT 1
f0c568a4 JL	142	#define MAX_EVENTS_RETURNED 6
f0c568a4 JL	143
bd756dde SF	144	#define DEVICE_OFFLINE 0
	145	#define DEVICE_ONLINE 1
	146
	147	struct mvumi_hotplug_event {
	148	u16 size;
	149	u8 dummy[2];
	150	u8 bitmap[0];
	151	};
	152
f0c568a4 JL	153	struct mvumi_driver_event {
	154	u32 time_stamp;
	155	u32 sequence_no;
	156	u32 event_id;
	157	u8 severity;
	158	u8 param_count;
	159	u16 device_id;
	160	u32 params[4];
	161	u8 sense_data_length;
	162	u8 Reserved1;
	163	u8 sense_data[30];
	164	};
	165
	166	struct mvumi_event_req {
	167	unsigned char count;
	168	unsigned char reserved[3];
	169	struct mvumi_driver_event events[MAX_EVENTS_RETURNED];
	170	};
	171
	172	struct mvumi_events_wq {
	173	struct work_struct work_q;
	174	struct mvumi_hba *mhba;
	175	unsigned int event;
	176	void *param;
	177	};
	178
bd756dde SF	179	#define HS_CAPABILITY_SUPPORT_COMPACT_SG (1U << 4)
	180	#define HS_CAPABILITY_SUPPORT_PRD_HOST (1U << 5)
	181	#define HS_CAPABILITY_SUPPORT_DYN_SRC (1U << 6)
	182	#define HS_CAPABILITY_NEW_PAGE_IO_DEPTH_DEF (1U << 14)
	183
f0c568a4 JL	184	#define MVUMI_MAX_SG_ENTRY 32
f0c568a4 JL	185	#define SGD_EOT (1L << 27)
bd756dde	186	#define SGD_EOT_CP (1L << 22)
f0c568a4 JL	187
	188	struct mvumi_sgl {
	189	u32 baseaddr_l;
	190	u32 baseaddr_h;
	191	u32 flags;
	192	u32 size;
	193	};
bd756dde SF	194	struct mvumi_compact_sgl {
	195	u32 baseaddr_l;
	196	u32 baseaddr_h;
	197	u32 flags;
	198	};
	199
	200	#define GET_COMPACT_SGD_SIZE(sgd) \
	201	((((struct mvumi_compact_sgl *)(sgd))->flags) & 0x3FFFFFL)
	202
	203	#define SET_COMPACT_SGD_SIZE(sgd, sz) do { \
	204	(((struct mvumi_compact_sgl *)(sgd))->flags) &= ~0x3FFFFFL; \
	205	(((struct mvumi_compact_sgl *)(sgd))->flags) \|= (sz); \
	206	} while (0)
	207	#define sgd_getsz(_mhba, sgd, sz) do { \
	208	if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \
	209	(sz) = GET_COMPACT_SGD_SIZE(sgd); \
	210	else \
	211	(sz) = (sgd)->size; \
	212	} while (0)
	213
	214	#define sgd_setsz(_mhba, sgd, sz) do { \
	215	if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \
	216	SET_COMPACT_SGD_SIZE(sgd, sz); \
	217	else \
	218	(sgd)->size = (sz); \
	219	} while (0)
	220
	221	#define sgd_inc(_mhba, sgd) do { \
	222	if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \
	223	sgd = (struct mvumi_sgl )(((unsigned char ) (sgd)) + 12); \
	224	else \
	225	sgd = (struct mvumi_sgl )(((unsigned char ) (sgd)) + 16); \
	226	} while (0)
f0c568a4 JL	227
	228	struct mvumi_res {
	229	struct list_head entry;
	230	dma_addr_t bus_addr;
	231	void *virt_addr;
	232	unsigned int size;
	233	unsigned short type; /* enum Resource_Type */
	234	};
	235
	236	/* Resource type */
	237	enum resource_type {
	238	RESOURCE_CACHED_MEMORY = 0,
	239	RESOURCE_UNCACHED_MEMORY
	240	};
	241
	242	struct mvumi_sense_data {
bd756dde	243	u8 error_code:7;
f0c568a4 JL	244	u8 valid:1;
	245	u8 segment_number;
	246	u8 sense_key:4;
	247	u8 reserved:1;
	248	u8 incorrect_length:1;
	249	u8 end_of_media:1;
	250	u8 file_mark:1;
	251	u8 information[4];
	252	u8 additional_sense_length;
	253	u8 command_specific_information[4];
	254	u8 additional_sense_code;
	255	u8 additional_sense_code_qualifier;
	256	u8 field_replaceable_unit_code;
	257	u8 sense_key_specific[3];
	258	};
	259
	260	/* Request initiator must set the status to REQ_STATUS_PENDING. */
	261	#define REQ_STATUS_PENDING 0x80
	262
	263	struct mvumi_cmd {
	264	struct list_head queue_pointer;
	265	struct mvumi_msg_frame *frame;
bd756dde	266	dma_addr_t frame_phys;
f0c568a4 JL	267	struct scsi_cmnd *scmd;
	268	atomic_t sync_cmd;
	269	void *data_buf;
	270	unsigned short request_id;
	271	unsigned char cmd_status;
	272	};
	273
	274	/*
	275	* the function type of the in bound frame
	276	*/
	277	#define CL_FUN_SCSI_CMD 0x1
	278
	279	struct mvumi_msg_frame {
	280	u16 device_id;
	281	u16 tag;
	282	u8 cmd_flag;
	283	u8 req_function;
	284	u8 cdb_length;
	285	u8 sg_counts;
	286	u32 data_transfer_length;
	287	u16 request_id;
	288	u16 reserved1;
	289	u8 cdb[MAX_COMMAND_SIZE];
	290	u32 payload[1];
	291	};
	292
	293	/*
	294	* the respond flag for data_payload of the out bound frame
	295	*/
	296	#define CL_RSP_FLAG_NODATA 0x0
	297	#define CL_RSP_FLAG_SENSEDATA 0x1
	298
	299	struct mvumi_rsp_frame {
	300	u16 device_id;
	301	u16 tag;
	302	u8 req_status;
	303	u8 rsp_flag; /* Indicates the type of Data_Payload.*/
	304	u16 request_id;
	305	u32 payload[1];
	306	};
	307
	308	struct mvumi_ob_data {
	309	struct list_head list;
	310	unsigned char data[0];
	311	};
	312
	313	struct version_info {
	314	u32 ver_major;
	315	u32 ver_minor;
	316	u32 ver_oem;
	317	u32 ver_build;
	318	};
	319
	320	#define FW_MAX_DELAY 30
	321	#define MVUMI_FW_BUSY (1U << 0)
	322	#define MVUMI_FW_ATTACH (1U << 1)
	323	#define MVUMI_FW_ALLOC (1U << 2)
	324
	325	/*
	326	* State is the state of the MU
	327	*/
	328	#define FW_STATE_IDLE 0
	329	#define FW_STATE_STARTING 1
	330	#define FW_STATE_HANDSHAKING 2
331	#define FW_STATE_STARTED 3
332	#define FW_STATE_ABORT 4
333
334	#define HANDSHAKE_SIGNATURE 0x5A5A5A5AL
335	#define HANDSHAKE_READYSTATE 0x55AA5AA5L
336	#define HANDSHAKE_DONESTATE 0x55AAA55AL
337
338	/* HandShake Status definition */
339	#define HS_STATUS_OK 1
340	#define HS_STATUS_ERR 2
341	#define HS_STATUS_INVALID 3
342
343	/* HandShake State/Cmd definition */
344	#define HS_S_START 1
345	#define HS_S_RESET 2
346	#define HS_S_PAGE_ADDR 3
347	#define HS_S_QUERY_PAGE 4
348	#define HS_S_SEND_PAGE 5
349	#define HS_S_END 6
350	#define HS_S_ABORT 7
351	#define HS_PAGE_VERIFY_SIZE 128
352
353	#define HS_GET_STATE(a) (a & 0xFFFF)
354	#define HS_GET_STATUS(a) ((a & 0xFFFF0000) >> 16)
355	#define HS_SET_STATE(a, b) (a \|= (b & 0xFFFF))
356	#define HS_SET_STATUS(a, b) (a \|= ((b & 0xFFFF) << 16))
357
358	/* handshake frame */
359	struct mvumi_hs_frame {
360	u16 size;
361	/* host information */
362	u8 host_type;
363	u8 reserved_1[1];
364	struct version_info host_ver; /* bios or driver version */
365
366	/* controller information */
367	u32 system_io_bus;
368	u32 slot_number;
369	u32 intr_level;
370	u32 intr_vector;
371
372	/* communication list configuration */
373	u32 ib_baseaddr_l;
374	u32 ib_baseaddr_h;
375	u32 ob_baseaddr_l;
376	u32 ob_baseaddr_h;
377
378	u8 ib_entry_size;
379	u8 ob_entry_size;
380	u8 ob_depth;
381	u8 ib_depth;
382
383	/* system time */
384	u64 seconds_since1970;
385	};
386
387	struct mvumi_hs_header {
388	u8 page_code;
389	u8 checksum;
390	u16 frame_length;
391	u32 frame_content[1];
392	};
393
394	/*
395	* the page code type of the handshake header
396	*/
397	#define HS_PAGE_FIRM_CAP 0x1
398	#define HS_PAGE_HOST_INFO 0x2
399	#define HS_PAGE_FIRM_CTL 0x3
400	#define HS_PAGE_CL_INFO 0x4
401	#define HS_PAGE_TOTAL 0x5
402
403	#define HSP_SIZE(i) sizeof(struct mvumi_hs_page##i)
404
405	#define HSP_MAX_SIZE ({ \
406	int size, m1, m2; \
407	m1 = max(HSP_SIZE(1), HSP_SIZE(3)); \
408	m2 = max(HSP_SIZE(2), HSP_SIZE(4)); \
409	size = max(m1, m2); \
410	size; \
411	})
412
413	/* The format of the page code for Firmware capability */
414	struct mvumi_hs_page1 {
415	u8 pagecode;
416	u8 checksum;
417	u16 frame_length;
418
419	u16 number_of_ports;
420	u16 max_devices_support;
421	u16 max_io_support;
422	u16 umi_ver;
423	u32 max_transfer_size;
424	struct version_info fw_ver;
425	u8 cl_in_max_entry_size;
426	u8 cl_out_max_entry_size;
427	u8 cl_inout_list_depth;
428	u8 total_pages;
429	u16 capability;
430	u16 reserved1;
431	};
432
433	/* The format of the page code for Host information */
434	struct mvumi_hs_page2 {
435	u8 pagecode;
436	u8 checksum;
437	u16 frame_length;
438
439	u8 host_type;
bd756dde SF	440	u8 host_cap;
bd756dde SF	441	u8 reserved[2];
f0c568a4 JL	442	struct version_info host_ver;
	443	u32 system_io_bus;
	444	u32 slot_number;
	445	u32 intr_level;
	446	u32 intr_vector;
	447	u64 seconds_since1970;
	448	};
	449
	450	/* The format of the page code for firmware control */
	451	struct mvumi_hs_page3 {
	452	u8 pagecode;
	453	u8 checksum;
	454	u16 frame_length;
	455	u16 control;
	456	u8 reserved[2];
	457	u32 host_bufferaddr_l;
	458	u32 host_bufferaddr_h;
	459	u32 host_eventaddr_l;
	460	u32 host_eventaddr_h;
	461	};
	462
	463	struct mvumi_hs_page4 {
	464	u8 pagecode;
	465	u8 checksum;
	466	u16 frame_length;
	467	u32 ib_baseaddr_l;
	468	u32 ib_baseaddr_h;
	469	u32 ob_baseaddr_l;
	470	u32 ob_baseaddr_h;
	471	u8 ib_entry_size;
	472	u8 ob_entry_size;
	473	u8 ob_depth;
	474	u8 ib_depth;
	475	};
	476
	477	struct mvumi_tag {
	478	unsigned short *stack;
	479	unsigned short top;
	480	unsigned short size;
	481	};
	482
bd756dde SF	483	struct mvumi_device {
	484	struct list_head list;
	485	struct scsi_device *sdev;
	486	u64 wwid;
	487	u8 dev_type;
	488	int id;
	489	};
	490
f0c568a4 JL	491	struct mvumi_hba {
f0c568a4 JL	492	void *base_addr[MAX_BASE_ADDRESS];
bd756dde	493	u32 pci_base[MAX_BASE_ADDRESS];
f0c568a4 JL	494	void *mmio;
	495	struct list_head cmd_pool;
	496	struct Scsi_Host *shost;
	497	wait_queue_head_t int_cmd_wait_q;
	498	struct pci_dev *pdev;
	499	unsigned int unique_id;
	500	atomic_t fw_outstanding;
	501	struct mvumi_instance_template *instancet;
	502
	503	void *ib_list;
	504	dma_addr_t ib_list_phys;
	505
bd756dde SF	506	void *ib_frame;
	507	dma_addr_t ib_frame_phys;
	508
f0c568a4 JL	509	void *ob_list;
	510	dma_addr_t ob_list_phys;
	511
	512	void *ib_shadow;
	513	dma_addr_t ib_shadow_phys;
	514
	515	void *ob_shadow;
	516	dma_addr_t ob_shadow_phys;
	517
	518	void *handshake_page;
	519	dma_addr_t handshake_page_phys;
	520
	521	unsigned int global_isr;
	522	unsigned int isr_status;
	523
	524	unsigned short max_sge;
	525	unsigned short max_target_id;
	526	unsigned char *target_map;
	527	unsigned int max_io;
	528	unsigned int list_num_io;
	529	unsigned int ib_max_size;
	530	unsigned int ob_max_size;
	531	unsigned int ib_max_size_setting;
	532	unsigned int ob_max_size_setting;
	533	unsigned int max_transfer_size;
	534	unsigned char hba_total_pages;
	535	unsigned char fw_flag;
	536	unsigned char request_id_enabled;
bd756dde	537	unsigned char eot_flag;
f0c568a4 JL	538	unsigned short hba_capability;
	539	unsigned short io_seq;
	540
	541	unsigned int ib_cur_slot;
	542	unsigned int ob_cur_slot;
	543	unsigned int fw_state;
bd756dde	544	struct mutex sas_discovery_mutex;
f0c568a4 JL	545
	546	struct list_head ob_data_list;
	547	struct list_head free_ob_list;
	548	struct list_head res_list;
	549	struct list_head waiting_req_list;
	550
	551	struct mvumi_tag tag_pool;
	552	struct mvumi_cmd **tag_cmd;
bd756dde SF	553	struct mvumi_hw_regs *regs;
	554	struct mutex device_lock;
	555	struct list_head mhba_dev_list;
	556	struct list_head shost_dev_list;
	557	struct task_struct *dm_thread;
	558	atomic_t pnp_count;
f0c568a4 JL	559	};
	560
	561	struct mvumi_instance_template {
bd756dde SF	562	void (fire_cmd) (struct mvumi_hba , struct mvumi_cmd *);
	563	void (enable_intr) (struct mvumi_hba );
	564	void (disable_intr) (struct mvumi_hba );
	565	int (clear_intr) (void );
	566	unsigned int (read_fw_status_reg) (struct mvumi_hba );
	567	unsigned int (check_ib_list) (struct mvumi_hba );
	568	int (check_ob_list) (struct mvumi_hba , unsigned int *,
	569	unsigned int *);
	570	int (reset_host) (struct mvumi_hba );
f0c568a4 JL	571	};
	572
	573	extern struct timezone sys_tz;
	574	#endif