projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SCSI] mvsas: Remove unused macros, variables and functions
[linux-2.6-block.git] / drivers / scsi / mvsas / mv_sas.h
CommitLineData
dd4969a8 1/*
20b09c29
AY		 2 * Marvell 88SE64xx/88SE94xx main function head file
3 *
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
0b15fb1f 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
20b09c29
AY		 7 *
8 * This file is licensed under GPLv2.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; version 2 of the
13 * License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
23 * USA
24*/
dd4969a8
JG		 25
26#ifndef _MV_SAS_H_
27#define _MV_SAS_H_
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/spinlock.h>
32#include <linux/delay.h>
33#include <linux/types.h>
34#include <linux/ctype.h>
35#include <linux/dma-mapping.h>
36#include <linux/pci.h>
37#include <linux/platform_device.h>
38#include <linux/interrupt.h>
39#include <linux/irq.h>
5a0e3ad6 40#include <linux/slab.h>
dd4969a8
JG		 41#include <linux/vmalloc.h>
42#include <scsi/libsas.h>
9dc9fd94 43#include <scsi/scsi.h>
dd4969a8
JG		 44#include <scsi/scsi_tcq.h>
45#include <scsi/sas_ata.h>
46#include <linux/version.h>
47#include "mv_defs.h"
48
20b09c29
AY		 49#define DRV_NAME "mvsas"
50#define DRV_VERSION "0.8.2"
dd4969a8 51#define MVS_ID_NOT_MAPPED 0x7f
20b09c29 52#define WIDE_PORT_MAX_PHY 4
20b09c29
AY		 53#define mv_printk(fmt, arg ...) \
54 printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg)
55#ifdef MV_DEBUG
56#define mv_dprintk(format, arg...) \
57 printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg)
58#else
59#define mv_dprintk(format, arg...)
60#endif
61#define MV_MAX_U32 0xffffffff
62
83c7b61c 63extern int interrupt_coalescing;
20b09c29
AY		 64extern struct mvs_tgt_initiator mvs_tgt;
65extern struct mvs_info *tgt_mvi;
66extern const struct mvs_dispatch mvs_64xx_dispatch;
67extern const struct mvs_dispatch mvs_94xx_dispatch;
0b15fb1f 68extern struct kmem_cache *mvs_task_list_cache;
20b09c29
AY		 69
70#define DEV_IS_EXPANDER(type) \
71 ((type == EDGE_DEV) || (type == FANOUT_DEV))
dd4969a8 72
20b09c29
AY		 73#define bit(n) ((u32)1 << n)
74
75#define for_each_phy(__lseq_mask, __mc, __lseq) \
76 for ((__mc) = (__lseq_mask), (__lseq) = 0; \
77 (__mc) != 0 ; \
dd4969a8
JG		 78 (++__lseq), (__mc) >>= 1)
79
20b09c29
AY		 80#define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f)
81#define UNASSOC_D2H_FIS(id) \
82 ((void *) mvi->rx_fis + 0x100 * id)
83#define SATA_RECEIVED_FIS_LIST(reg_set) \
84 ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set)
85#define SATA_RECEIVED_SDB_FIS(reg_set) \
86 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
87#define SATA_RECEIVED_D2H_FIS(reg_set) \
88 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
89#define SATA_RECEIVED_PIO_FIS(reg_set) \
90 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
91#define SATA_RECEIVED_DMA_FIS(reg_set) \
92 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)
93
94enum dev_status {
95 MVS_DEV_NORMAL = 0x0,
96 MVS_DEV_EH = 0x1,
97};
98
99
100struct mvs_info;
101
102struct mvs_dispatch {
103 char *name;
104 int (*chip_init)(struct mvs_info *mvi);
105 int (*spi_init)(struct mvs_info *mvi);
106 int (*chip_ioremap)(struct mvs_info *mvi);
107 void (*chip_iounmap)(struct mvs_info *mvi);
108 irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat);
109 u32 (*isr_status)(struct mvs_info *mvi, int irq);
110 void (*interrupt_enable)(struct mvs_info *mvi);
111 void (*interrupt_disable)(struct mvs_info *mvi);
112
113 u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port);
114 void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val);
115
116 u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port);
117 void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val);
118 void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr);
119
120 u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port);
121 void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val);
122 void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr);
123
124 u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port);
125 void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val);
126
127 u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port);
128 void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val);
129
20b09c29 130 void (*command_active)(struct mvs_info *mvi, u32 slot_idx);
9dc9fd94 131 void (*clear_srs_irq)(struct mvs_info *mvi, u8 reg_set, u8 clear_all);
20b09c29
AY		 132 void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type,
133 u32 tfs);
134 void (*start_delivery)(struct mvs_info *mvi, u32 tx);
135 u32 (*rx_update)(struct mvs_info *mvi);
136 void (*int_full)(struct mvs_info *mvi);
137 u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs);
138 void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs);
139 u32 (*prd_size)(void);
140 u32 (*prd_count)(void);
141 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
142 void (*detect_porttype)(struct mvs_info *mvi, int i);
143 int (*oob_done)(struct mvs_info *mvi, int i);
144 void (*fix_phy_info)(struct mvs_info *mvi, int i,
145 struct sas_identify_frame *id);
146 void (*phy_work_around)(struct mvs_info *mvi, int i);
147 void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id,
148 struct sas_phy_linkrates *rates);
149 u32 (*phy_max_link_rate)(void);
150 void (*phy_disable)(struct mvs_info *mvi, u32 phy_id);
151 void (*phy_enable)(struct mvs_info *mvi, u32 phy_id);
152 void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard);
153 void (*stp_reset)(struct mvs_info *mvi, u32 phy_id);
154 void (*clear_active_cmds)(struct mvs_info *mvi);
155 u32 (*spi_read_data)(struct mvs_info *mvi);
156 void (*spi_write_data)(struct mvs_info *mvi, u32 data);
157 int (*spi_buildcmd)(struct mvs_info *mvi,
158 u32 *dwCmd,
159 u8 cmd,
160 u8 read,
161 u8 length,
162 u32 addr
163 );
164 int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd);
165 int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout);
8882f081
XY		 166 void (*dma_fix)(struct mvs_info *mvi, u32 phy_mask,
167 int buf_len, int from, void *prd);
83c7b61c 168 void (*tune_interrupt)(struct mvs_info *mvi, u32 time);
534ff101 169 void (*non_spec_ncq_error)(struct mvs_info *mvi);
20b09c29
AY		 170
171};
172
dd4969a8 173struct mvs_chip_info {
20b09c29
AY		 174 u32 n_host;
175 u32 n_phy;
176 u32 fis_offs;
177 u32 fis_count;
178 u32 srs_sz;
179 u32 slot_width;
180 const struct mvs_dispatch *dispatch;
dd4969a8 181};
20b09c29
AY		 182#define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
183#define MVS_RX_FISL_SZ \
184 (mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100))
185#define MVS_CHIP_DISP (mvi->chip->dispatch)
dd4969a8
JG		 186
187struct mvs_err_info {
188 __le32 flags;
189 __le32 flags2;
190};
191
192struct mvs_cmd_hdr {
193 __le32 flags; /* PRD tbl len; SAS, SATA ctl */
194 __le32 lens; /* cmd, max resp frame len */
195 __le32 tags; /* targ port xfer tag; tag */
196 __le32 data_len; /* data xfer len */
20b09c29 197 __le64 cmd_tbl; /* command table address */
dd4969a8
JG		 198 __le64 open_frame; /* open addr frame address */
199 __le64 status_buf; /* status buffer address */
200 __le64 prd_tbl; /* PRD tbl address */
201 __le32 reserved[4];
202};
203
204struct mvs_port {
205 struct asd_sas_port sas_port;
206 u8 port_attached;
dd4969a8
JG		 207 u8 wide_port_phymap;
208 struct list_head list;
209};
210
211struct mvs_phy {
20b09c29 212 struct mvs_info *mvi;
dd4969a8
JG		 213 struct mvs_port *port;
214 struct asd_sas_phy sas_phy;
215 struct sas_identify identify;
216 struct scsi_device *sdev;
20b09c29 217 struct timer_list timer;
dd4969a8
JG		 218 u64 dev_sas_addr;
219 u64 att_dev_sas_addr;
220 u32 att_dev_info;
221 u32 dev_info;
222 u32 phy_type;
223 u32 phy_status;
224 u32 irq_status;
225 u32 frame_rcvd_size;
226 u8 frame_rcvd[32];
227 u8 phy_attached;
20b09c29
AY		 228 u8 phy_mode;
229 u8 reserved[2];
230 u32 phy_event;
dd4969a8
JG		 231 enum sas_linkrate minimum_linkrate;
232 enum sas_linkrate maximum_linkrate;
233};
234
20b09c29 235struct mvs_device {
9870d9a2 236 struct list_head dev_entry;
20b09c29 237 enum sas_dev_type dev_type;
9870d9a2 238 struct mvs_info *mvi_info;
20b09c29 239 struct domain_device *sas_device;
9dc9fd94 240 struct timer_list timer;
20b09c29
AY		 241 u32 attached_phy;
242 u32 device_id;
9dc9fd94 243 u32 running_req;
20b09c29
AY		 244 u8 taskfileset;
245 u8 dev_status;
246 u16 reserved;
20b09c29
AY		 247};
248
f1f82a91
XY		 249/* Generate PHY tunning parameters */
250struct phy_tuning {
251 /* 1 bit, transmitter emphasis enable */
252 u8 trans_emp_en:1;
253 /* 4 bits, transmitter emphasis amplitude */
254 u8 trans_emp_amp:4;
255 /* 3 bits, reserved space */
256 u8 Reserved_2bit_1:3;
257 /* 5 bits, transmitter amplitude */
258 u8 trans_amp:5;
259 /* 2 bits, transmitter amplitude adjust */
260 u8 trans_amp_adj:2;
261 /* 1 bit, reserved space */
262 u8 resv_2bit_2:1;
263 /* 2 bytes, reserved space */
264 u8 reserved[2];
265};
266
267struct ffe_control {
268 /* 4 bits, FFE Capacitor Select (value range 0~F) */
269 u8 ffe_cap_sel:4;
270 /* 3 bits, FFE Resistor Select (value range 0~7) */
271 u8 ffe_rss_sel:3;
272 /* 1 bit reserve*/
273 u8 reserved:1;
274};
275
276/*
277 * HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes.
278 * The data area is valid only Signature="MRVL".
279 * If any member fills with 0xFF, the member is invalid.
280 */
281struct hba_info_page {
282 /* Dword 0 */
283 /* 4 bytes, structure signature,should be "MRVL" at first initial */
284 u8 signature[4];
285
286 /* Dword 1-13 */
287 u32 reserved1[13];
288
289 /* Dword 14-29 */
290 /* 64 bytes, SAS address for each port */
291 u64 sas_addr[8];
292
293 /* Dword 30-31 */
294 /* 8 bytes for vanir 8 port PHY FFE seeting
295 * BIT 0~3 : FFE Capacitor select(value range 0~F)
296 * BIT 4~6 : FFE Resistor select(value range 0~7)
297 * BIT 7: reserve.
298 */
299
300 struct ffe_control ffe_ctl[8];
301 /* Dword 32 -43 */
302 u32 reserved2[12];
303
304 /* Dword 44-45 */
305 /* 8 bytes, 0: 1.5G, 1: 3.0G, should be 0x01 at first initial */
306 u8 phy_rate[8];
307
308 /* Dword 46-53 */
309 /* 32 bytes, PHY tuning parameters for each PHY*/
310 struct phy_tuning phy_tuning[8];
311
312 /* Dword 54-63 */
313 u32 reserved3[10];
314}; /* total 256 bytes */
315
dd4969a8 316struct mvs_slot_info {
20b09c29
AY		 317 struct list_head entry;
318 union {
319 struct sas_task *task;
320 void *tdata;
321 };
dd4969a8
JG		 322 u32 n_elem;
323 u32 tx;
20b09c29 324 u32 slot_tag;
dd4969a8
JG		 325
326 /* DMA buffer for storing cmd tbl, open addr frame, status buffer,
327 * and PRD table
328 */
329 void *buf;
330 dma_addr_t buf_dma;
dd4969a8
JG		 331 void *response;
332 struct mvs_port *port;
20b09c29
AY		 333 struct mvs_device *device;
334 void *open_frame;
dd4969a8
JG		 335};
336
337struct mvs_info {
338 unsigned long flags;
339
340 /* host-wide lock */
341 spinlock_t lock;
342
343 /* our device */
344 struct pci_dev *pdev;
20b09c29 345 struct device *dev;
dd4969a8
JG		 346
347 /* enhanced mode registers */
348 void __iomem *regs;
349
20b09c29
AY		 350 /* peripheral or soc registers */
351 void __iomem *regs_ex;
dd4969a8
JG		 352 u8 sas_addr[SAS_ADDR_SIZE];
353
354 /* SCSI/SAS glue */
20b09c29 355 struct sas_ha_struct *sas;
dd4969a8
JG		 356 struct Scsi_Host *shost;
357
358 /* TX (delivery) DMA ring */
359 __le32 *tx;
360 dma_addr_t tx_dma;
361
362 /* cached next-producer idx */
363 u32 tx_prod;
364
365 /* RX (completion) DMA ring */
20b09c29 366 __le32 *rx;
dd4969a8
JG		 367 dma_addr_t rx_dma;
368
369 /* RX consumer idx */
370 u32 rx_cons;
371
372 /* RX'd FIS area */
373 __le32 *rx_fis;
374 dma_addr_t rx_fis_dma;
375
376 /* DMA command header slots */
377 struct mvs_cmd_hdr *slot;
378 dma_addr_t slot_dma;
379
20b09c29 380 u32 chip_id;
dd4969a8
JG		 381 const struct mvs_chip_info *chip;
382
20b09c29 383 int tags_num;
b89e8f53 384 unsigned long *tags;
20b09c29 385 /* further per-slot information */
dd4969a8
JG		 386 struct mvs_phy phy[MVS_MAX_PHYS];
387 struct mvs_port port[MVS_MAX_PHYS];
20b09c29
AY		 388 u32 id;
389 u64 sata_reg_set;
390 struct list_head *hba_list;
391 struct list_head soc_entry;
392 struct list_head wq_list;
393 unsigned long instance;
394 u16 flashid;
395 u32 flashsize;
396 u32 flashsectSize;
397
398 void *addon;
f1f82a91 399 struct hba_info_page hba_info_param;
20b09c29 400 struct mvs_device devices[MVS_MAX_DEVICES];
20b09c29
AY		 401 void *bulk_buffer;
402 dma_addr_t bulk_buffer_dma;
8882f081
XY		 403 void *bulk_buffer1;
404 dma_addr_t bulk_buffer_dma1;
20b09c29 405#define TRASH_BUCKET_SIZE 0x20000
0b15fb1f 406 void *dma_pool;
20b09c29
AY		 407 struct mvs_slot_info slot_info[0];
408};
409
410struct mvs_prv_info{
411 u8 n_host;
412 u8 n_phy;
413 u16 reserve;
414 struct mvs_info *mvi[2];
415};
416
417struct mvs_wq {
418 struct delayed_work work_q;
419 struct mvs_info *mvi;
420 void *data;
421 int handler;
422 struct list_head entry;
dd4969a8
JG		 423};
424
20b09c29
AY		 425struct mvs_task_exec_info {
426 struct sas_task *task;
427 struct mvs_cmd_hdr *hdr;
428 struct mvs_port *port;
429 u32 tag;
430 int n_elem;
431};
432
0b15fb1f
XY		 433struct mvs_task_list {
434 struct sas_task *task;
435 struct list_head list;
436};
437
20b09c29
AY		 438
439/******************** function prototype *********************/
440void mvs_get_sas_addr(void *buf, u32 buflen);
441void mvs_tag_clear(struct mvs_info *mvi, u32 tag);
442void mvs_tag_free(struct mvs_info *mvi, u32 tag);
443void mvs_tag_set(struct mvs_info *mvi, unsigned int tag);
444int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out);
445void mvs_tag_init(struct mvs_info *mvi);
446void mvs_iounmap(void __iomem *regs);
447int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex);
448void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard);
dd4969a8
JG		 449int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
450 void *funcdata);
20b09c29
AY		 451void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id,
452 u32 off_lo, u32 off_hi, u64 sas_addr);
453int mvs_slave_alloc(struct scsi_device *scsi_dev);
dd4969a8
JG		 454int mvs_slave_configure(struct scsi_device *sdev);
455void mvs_scan_start(struct Scsi_Host *shost);
456int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time);
20b09c29
AY		 457int mvs_queue_command(struct sas_task *task, const int num,
458 gfp_t gfp_flags);
459int mvs_abort_task(struct sas_task *task);
460int mvs_abort_task_set(struct domain_device *dev, u8 *lun);
461int mvs_clear_aca(struct domain_device *dev, u8 *lun);
462int mvs_clear_task_set(struct domain_device *dev, u8 * lun);
dd4969a8 463void mvs_port_formed(struct asd_sas_phy *sas_phy);
20b09c29
AY		 464void mvs_port_deformed(struct asd_sas_phy *sas_phy);
465int mvs_dev_found(struct domain_device *dev);
466void mvs_dev_gone(struct domain_device *dev);
467int mvs_lu_reset(struct domain_device *dev, u8 *lun);
468int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags);
dd4969a8 469int mvs_I_T_nexus_reset(struct domain_device *dev);
20b09c29 470int mvs_query_task(struct sas_task *task);
9dc9fd94
S		 471void mvs_release_task(struct mvs_info *mvi,
472 struct domain_device *dev);
473void mvs_do_release_task(struct mvs_info *mvi, int phy_no,
20b09c29
AY		 474 struct domain_device *dev);
475void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events);
476void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
477int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
534ff101 478struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi, u8 reg_set);
dd4969a8 479#endif
20b09c29 480
Linux 6.x block layer and io_uring tree(s)