[linux-2.6-block.git] / drivers / scsi / mvsas / mv_sas.h

/*
 * Marvell 88SE64xx/88SE94xx main function head file
 *
 * Copyright 2007 Red Hat, Inc.
 * Copyright 2008 Marvell. <kewei@marvell.com>
 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
 *
 * This file is licensed under GPLv2.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; version 2 of the
 * License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
 * USA
*/

#ifndef _MV_SAS_H_
#define _MV_SAS_H_

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/ctype.h>
#include <linux/dma-mapping.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <asm/unaligned.h>
#include <scsi/libsas.h>
#include <scsi/scsi.h>
#include <scsi/scsi_tcq.h>
#include <scsi/sas_ata.h>
#include "mv_defs.h"

#define DRV_NAME		"mvsas"
#define DRV_VERSION		"0.8.16"
#define MVS_ID_NOT_MAPPED	0x7f
#define WIDE_PORT_MAX_PHY		4
#define mv_printk(fmt, arg ...)	\
	printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg)
#ifdef MV_DEBUG
#define mv_dprintk(format, arg...)	\
	printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg)
#else
#define mv_dprintk(format, arg...)
#endif
#define MV_MAX_U32			0xffffffff

extern int interrupt_coalescing;
extern struct mvs_tgt_initiator mvs_tgt;
extern struct mvs_info *tgt_mvi;
extern const struct mvs_dispatch mvs_64xx_dispatch;
extern const struct mvs_dispatch mvs_94xx_dispatch;

#define DEV_IS_EXPANDER(type)	\
	((type == SAS_EDGE_EXPANDER_DEVICE) || (type == SAS_FANOUT_EXPANDER_DEVICE))

#define bit(n) ((u64)1 << n)

#define for_each_phy(__lseq_mask, __mc, __lseq)			\
	for ((__mc) = (__lseq_mask), (__lseq) = 0;		\
					(__mc) != 0 ;		\
					(++__lseq), (__mc) >>= 1)

#define MVS_PHY_ID (1U << sas_phy->id)
#define MV_INIT_DELAYED_WORK(w, f, d)	INIT_DELAYED_WORK(w, f)
#define UNASSOC_D2H_FIS(id)		\
	((void *) mvi->rx_fis + 0x100 * id)
#define SATA_RECEIVED_FIS_LIST(reg_set)	\
	((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set)
#define SATA_RECEIVED_SDB_FIS(reg_set)	\
	(SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
#define SATA_RECEIVED_D2H_FIS(reg_set)	\
	(SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
#define SATA_RECEIVED_PIO_FIS(reg_set)	\
	(SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
#define SATA_RECEIVED_DMA_FIS(reg_set)	\
	(SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)

enum dev_status {
	MVS_DEV_NORMAL = 0x0,
	MVS_DEV_EH	= 0x1,
};

enum dev_reset {
	MVS_SOFT_RESET	= 0,
	MVS_HARD_RESET	= 1,
	MVS_PHY_TUNE	= 2,
};

struct mvs_info;
struct mvs_prv_info;

struct mvs_dispatch {
	char *name;
	int (*chip_init)(struct mvs_info *mvi);
	int (*spi_init)(struct mvs_info *mvi);
	int (*chip_ioremap)(struct mvs_info *mvi);
	void (*chip_iounmap)(struct mvs_info *mvi);
	irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat);
	u32 (*isr_status)(struct mvs_info *mvi, int irq);
	void (*interrupt_enable)(struct mvs_info *mvi);
	void (*interrupt_disable)(struct mvs_info *mvi);

	u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port);
	void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val);

	u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port);
	void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val);
	void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr);

	u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port);
	void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val);
	void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr);

	u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port);
	void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val);

	u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port);
	void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val);

	void (*command_active)(struct mvs_info *mvi, u32 slot_idx);
	void (*clear_srs_irq)(struct mvs_info *mvi, u8 reg_set, u8 clear_all);
	void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type,
				u32 tfs);
	void (*start_delivery)(struct mvs_info *mvi, u32 tx);
	u32 (*rx_update)(struct mvs_info *mvi);
	void (*int_full)(struct mvs_info *mvi);
	u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs);
	void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs);
	u32 (*prd_size)(void);
	u32 (*prd_count)(void);
	void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
	void (*detect_porttype)(struct mvs_info *mvi, int i);
	int (*oob_done)(struct mvs_info *mvi, int i);
	void (*fix_phy_info)(struct mvs_info *mvi, int i,
				struct sas_identify_frame *id);
	void (*phy_work_around)(struct mvs_info *mvi, int i);
	void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id,
				struct sas_phy_linkrates *rates);
	u32 (*phy_max_link_rate)(void);
	void (*phy_disable)(struct mvs_info *mvi, u32 phy_id);
	void (*phy_enable)(struct mvs_info *mvi, u32 phy_id);
	void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard);
	void (*stp_reset)(struct mvs_info *mvi, u32 phy_id);
	void (*clear_active_cmds)(struct mvs_info *mvi);
	u32 (*spi_read_data)(struct mvs_info *mvi);
	void (*spi_write_data)(struct mvs_info *mvi, u32 data);
	int (*spi_buildcmd)(struct mvs_info *mvi,
						u32      *dwCmd,
						u8       cmd,
						u8       read,
						u8       length,
						u32      addr
						);
	int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd);
	int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout);
	void (*dma_fix)(struct mvs_info *mvi, u32 phy_mask,
				int buf_len, int from, void *prd);
	void (*tune_interrupt)(struct mvs_info *mvi, u32 time);
	void (*non_spec_ncq_error)(struct mvs_info *mvi);
	int (*gpio_write)(struct mvs_prv_info *mvs_prv, u8 reg_type,
			u8 reg_index, u8 reg_count, u8 *write_data);

};

struct mvs_chip_info {
	u32 		n_host;
	u32 		n_phy;
	u32 		fis_offs;
	u32 		fis_count;
	u32 		srs_sz;
	u32		sg_width;
	u32 		slot_width;
	const struct mvs_dispatch *dispatch;
};
#define MVS_MAX_SG		(1U << mvi->chip->sg_width)
#define MVS_CHIP_SLOT_SZ	(1U << mvi->chip->slot_width)
#define MVS_RX_FISL_SZ		\
	(mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100))
#define MVS_CHIP_DISP		(mvi->chip->dispatch)

struct mvs_err_info {
	__le32			flags;
	__le32			flags2;
};

struct mvs_cmd_hdr {
	__le32			flags;	/* PRD tbl len; SAS, SATA ctl */
	__le32			lens;	/* cmd, max resp frame len */
	__le32			tags;	/* targ port xfer tag; tag */
	__le32			data_len;	/* data xfer len */
	__le64			cmd_tbl;  	/* command table address */
	__le64			open_frame;	/* open addr frame address */
	__le64			status_buf;	/* status buffer address */
	__le64			prd_tbl;		/* PRD tbl address */
	__le32			reserved[4];
};

struct mvs_port {
	struct asd_sas_port	sas_port;
	u8			port_attached;
	u8			wide_port_phymap;
	struct list_head	list;
};

struct mvs_phy {
	struct mvs_info 		*mvi;
	struct mvs_port		*port;
	struct asd_sas_phy	sas_phy;
	struct sas_identify	identify;
	struct scsi_device	*sdev;
	struct timer_list timer;
	u64		dev_sas_addr;
	u64		att_dev_sas_addr;
	u32		att_dev_info;
	u32		dev_info;
	u32		phy_type;
	u32		phy_status;
	u32		irq_status;
	u32		frame_rcvd_size;
	u8		frame_rcvd[32];
	u8		phy_attached;
	u8		phy_mode;
	u8		reserved[2];
	u32		phy_event;
	enum sas_linkrate	minimum_linkrate;
	enum sas_linkrate	maximum_linkrate;
};

struct mvs_device {
	struct list_head		dev_entry;
	enum sas_device_type dev_type;
	struct mvs_info *mvi_info;
	struct domain_device *sas_device;
	struct timer_list timer;
	u32 attached_phy;
	u32 device_id;
	u32 running_req;
	u8 taskfileset;
	u8 dev_status;
	u16 reserved;
};

/* Generate  PHY tunning parameters */
struct phy_tuning {
	/* 1 bit,  transmitter emphasis enable	*/
	u8	trans_emp_en:1;
	/* 4 bits, transmitter emphasis amplitude */
	u8	trans_emp_amp:4;
	/* 3 bits, reserved space */
	u8	Reserved_2bit_1:3;
	/* 5 bits, transmitter amplitude */
	u8	trans_amp:5;
	/* 2 bits, transmitter amplitude adjust */
	u8	trans_amp_adj:2;
	/* 1 bit, reserved space */
	u8	resv_2bit_2:1;
	/* 2 bytes, reserved space */
	u8	reserved[2];
};

struct ffe_control {
	/* 4 bits,  FFE Capacitor Select  (value range 0~F)  */
	u8 ffe_cap_sel:4;
	/* 3 bits,  FFE Resistor Select (value range 0~7) */
	u8 ffe_rss_sel:3;
	/* 1 bit reserve*/
	u8 reserved:1;
};

/*
 * HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes.
 * The data area is valid only Signature="MRVL".
 * If any member fills with 0xFF, the member is invalid.
 */
struct hba_info_page {
	/* Dword 0 */
	/* 4 bytes, structure signature,should be "MRVL" at first initial */
	u8 signature[4];

	/* Dword 1-13 */
	u32 reserved1[13];

	/* Dword 14-29 */
	/* 64 bytes, SAS address for each port */
	u64 sas_addr[8];

	/* Dword 30-31 */
	/* 8 bytes for vanir 8 port PHY FFE seeting
	 * BIT 0~3 : FFE Capacitor select(value range 0~F)
	 * BIT 4~6 : FFE Resistor select(value range 0~7)
	 * BIT 7: reserve.
	 */

	struct ffe_control  ffe_ctl[8];
	/* Dword 32 -43 */
	u32 reserved2[12];

	/* Dword 44-45 */
	/* 8 bytes,  0:  1.5G, 1: 3.0G, should be 0x01 at first initial */
	u8 phy_rate[8];

	/* Dword 46-53 */
	/* 32 bytes, PHY tuning parameters for each PHY*/
	struct phy_tuning   phy_tuning[8];

	/* Dword 54-63 */
	u32 reserved3[10];
};	/* total 256 bytes */

struct mvs_slot_info {
	struct list_head entry;
	union {
		struct sas_task *task;
		void *tdata;
	};
	u32 n_elem;
	u32 tx;
	u32 slot_tag;

	/* DMA buffer for storing cmd tbl, open addr frame, status buffer,
	 * and PRD table
	 */
	void *buf;
	dma_addr_t buf_dma;
	void *response;
	struct mvs_port *port;
	struct mvs_device	*device;
	void *open_frame;
};

struct mvs_info {
	unsigned long flags;

	/* host-wide lock */
	spinlock_t lock;

	/* our device */
	struct pci_dev *pdev;
	struct device *dev;

	/* enhanced mode registers */
	void __iomem *regs;

	/* peripheral or soc registers */
	void __iomem *regs_ex;
	u8 sas_addr[SAS_ADDR_SIZE];

	/* SCSI/SAS glue */
	struct sas_ha_struct *sas;
	struct Scsi_Host *shost;

	/* TX (delivery) DMA ring */
	__le32 *tx;
	dma_addr_t tx_dma;

	/* cached next-producer idx */
	u32 tx_prod;

	/* RX (completion) DMA ring */
	__le32	*rx;
	dma_addr_t rx_dma;

	/* RX consumer idx */
	u32 rx_cons;

	/* RX'd FIS area */
	__le32 *rx_fis;
	dma_addr_t rx_fis_dma;

	/* DMA command header slots */
	struct mvs_cmd_hdr *slot;
	dma_addr_t slot_dma;

	u32 chip_id;
	const struct mvs_chip_info *chip;

	int tags_num;
	unsigned long *tags;
	/* further per-slot information */
	struct mvs_phy phy[MVS_MAX_PHYS];
	struct mvs_port port[MVS_MAX_PHYS];
	u32 id;
	u64 sata_reg_set;
	struct list_head *hba_list;
	struct list_head soc_entry;
	struct list_head wq_list;
	unsigned long instance;
	u16 flashid;
	u32 flashsize;
	u32 flashsectSize;

	void *addon;
	struct hba_info_page hba_info_param;
	struct mvs_device	devices[MVS_MAX_DEVICES];
	void *bulk_buffer;
	dma_addr_t bulk_buffer_dma;
	void *bulk_buffer1;
	dma_addr_t bulk_buffer_dma1;
#define TRASH_BUCKET_SIZE    	0x20000
	void *dma_pool;
	struct mvs_slot_info slot_info[0];
};

struct mvs_prv_info{
	u8 n_host;
	u8 n_phy;
	u8 scan_finished;
	u8 reserve;
	struct mvs_info *mvi[2];
	struct tasklet_struct mv_tasklet;
};

struct mvs_wq {
	struct delayed_work work_q;
	struct mvs_info *mvi;
	void *data;
	int handler;
	struct list_head entry;
};

struct mvs_task_exec_info {
	struct sas_task *task;
	struct mvs_cmd_hdr *hdr;
	struct mvs_port *port;
	u32 tag;
	int n_elem;
};

/******************** function prototype *********************/
void mvs_get_sas_addr(void *buf, u32 buflen);
void mvs_tag_clear(struct mvs_info *mvi, u32 tag);
void mvs_tag_free(struct mvs_info *mvi, u32 tag);
void mvs_tag_set(struct mvs_info *mvi, unsigned int tag);
int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out);
void mvs_tag_init(struct mvs_info *mvi);
void mvs_iounmap(void __iomem *regs);
int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex);
void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard);
int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
			void *funcdata);
void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
		      u32 off_hi, u64 sas_addr);
void mvs_scan_start(struct Scsi_Host *shost);
int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time);
int mvs_queue_command(struct sas_task *task, gfp_t gfp_flags);
int mvs_abort_task(struct sas_task *task);
int mvs_abort_task_set(struct domain_device *dev, u8 *lun);
int mvs_clear_aca(struct domain_device *dev, u8 *lun);
int mvs_clear_task_set(struct domain_device *dev, u8 * lun);
void mvs_port_formed(struct asd_sas_phy *sas_phy);
void mvs_port_deformed(struct asd_sas_phy *sas_phy);
int mvs_dev_found(struct domain_device *dev);
void mvs_dev_gone(struct domain_device *dev);
int mvs_lu_reset(struct domain_device *dev, u8 *lun);
int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags);
int mvs_I_T_nexus_reset(struct domain_device *dev);
int mvs_query_task(struct sas_task *task);
void mvs_release_task(struct mvs_info *mvi,
			struct domain_device *dev);
void mvs_do_release_task(struct mvs_info *mvi, int phy_no,
			struct domain_device *dev);
void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events);
void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi, u8 reg_set);
int mvs_gpio_write(struct sas_ha_struct *, u8 reg_type, u8 reg_index,
			u8 reg_count, u8 *write_data);
#endif
Commit	Line	Data
dd4969a8	1	/*
20b09c29 AY	2	* Marvell 88SE64xx/88SE94xx main function head file
	3	*
	4	* Copyright 2007 Red Hat, Inc.
	5	* Copyright 2008 Marvell. <kewei@marvell.com>
0b15fb1f	6	* Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
20b09c29 AY	7	*
	8	* This file is licensed under GPLv2.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; version 2 of the
	13	* License.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
	23	* USA
	24	*/
dd4969a8 JG	25
	26	#ifndef _MV_SAS_H_
	27	#define _MV_SAS_H_
	28
	29	#include <linux/kernel.h>
	30	#include <linux/module.h>
	31	#include <linux/spinlock.h>
	32	#include <linux/delay.h>
	33	#include <linux/types.h>
	34	#include <linux/ctype.h>
	35	#include <linux/dma-mapping.h>
	36	#include <linux/pci.h>
	37	#include <linux/platform_device.h>
	38	#include <linux/interrupt.h>
	39	#include <linux/irq.h>
5a0e3ad6	40	#include <linux/slab.h>
dd4969a8	41	#include <linux/vmalloc.h>
53a983c4	42	#include <asm/unaligned.h>
dd4969a8	43	#include <scsi/libsas.h>
9dc9fd94	44	#include <scsi/scsi.h>
dd4969a8 JG	45	#include <scsi/scsi_tcq.h>
dd4969a8 JG	46	#include <scsi/sas_ata.h>
dd4969a8 JG	47	#include "mv_defs.h"
dd4969a8 JG	48
20b09c29	49	#define DRV_NAME "mvsas"
4f3f812d	50	#define DRV_VERSION "0.8.16"
dd4969a8	51	#define MVS_ID_NOT_MAPPED 0x7f
20b09c29	52	#define WIDE_PORT_MAX_PHY 4
20b09c29 AY	53	#define mv_printk(fmt, arg ...) \
	54	printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg)
	55	#ifdef MV_DEBUG
	56	#define mv_dprintk(format, arg...) \
	57	printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg)
	58	#else
	59	#define mv_dprintk(format, arg...)
	60	#endif
	61	#define MV_MAX_U32 0xffffffff
	62
83c7b61c	63	extern int interrupt_coalescing;
20b09c29 AY	64	extern struct mvs_tgt_initiator mvs_tgt;
	65	extern struct mvs_info *tgt_mvi;
	66	extern const struct mvs_dispatch mvs_64xx_dispatch;
	67	extern const struct mvs_dispatch mvs_94xx_dispatch;
	68
	69	#define DEV_IS_EXPANDER(type) \
aa9f8328	70	((type == SAS_EDGE_EXPANDER_DEVICE) \|\| (type == SAS_FANOUT_EXPANDER_DEVICE))
dd4969a8	71
beecadea	72	#define bit(n) ((u64)1 << n)
20b09c29 AY	73
	74	#define for_each_phy(__lseq_mask, __mc, __lseq) \
	75	for ((__mc) = (__lseq_mask), (__lseq) = 0; \
	76	(__mc) != 0 ; \
dd4969a8 JG	77	(++__lseq), (__mc) >>= 1)
dd4969a8 JG	78
7c237c5f	79	#define MVS_PHY_ID (1U << sas_phy->id)
20b09c29 AY	80	#define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f)
	81	#define UNASSOC_D2H_FIS(id) \
	82	((void ) mvi->rx_fis + 0x100 id)
	83	#define SATA_RECEIVED_FIS_LIST(reg_set) \
	84	((void ) mvi->rx_fis + mvi->chip->fis_offs + 0x100 reg_set)
	85	#define SATA_RECEIVED_SDB_FIS(reg_set) \
	86	(SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
	87	#define SATA_RECEIVED_D2H_FIS(reg_set) \
	88	(SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
	89	#define SATA_RECEIVED_PIO_FIS(reg_set) \
	90	(SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
	91	#define SATA_RECEIVED_DMA_FIS(reg_set) \
	92	(SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)
	93
	94	enum dev_status {
	95	MVS_DEV_NORMAL = 0x0,
	96	MVS_DEV_EH = 0x1,
	97	};
	98
a4632aae XY	99	enum dev_reset {
	100	MVS_SOFT_RESET = 0,
	101	MVS_HARD_RESET = 1,
	102	MVS_PHY_TUNE = 2,
	103	};
20b09c29 AY	104
20b09c29 AY	105	struct mvs_info;
c56f5f1d	106	struct mvs_prv_info;
20b09c29 AY	107
	108	struct mvs_dispatch {
	109	char *name;
	110	int (chip_init)(struct mvs_info mvi);
	111	int (spi_init)(struct mvs_info mvi);
	112	int (chip_ioremap)(struct mvs_info mvi);
	113	void (chip_iounmap)(struct mvs_info mvi);
	114	irqreturn_t (isr)(struct mvs_info mvi, int irq, u32 stat);
	115	u32 (isr_status)(struct mvs_info mvi, int irq);
	116	void (interrupt_enable)(struct mvs_info mvi);
	117	void (interrupt_disable)(struct mvs_info mvi);
	118
	119	u32 (read_phy_ctl)(struct mvs_info mvi, u32 port);
	120	void (write_phy_ctl)(struct mvs_info mvi, u32 port, u32 val);
	121
	122	u32 (read_port_cfg_data)(struct mvs_info mvi, u32 port);
	123	void (write_port_cfg_data)(struct mvs_info mvi, u32 port, u32 val);
	124	void (write_port_cfg_addr)(struct mvs_info mvi, u32 port, u32 addr);
	125
	126	u32 (read_port_vsr_data)(struct mvs_info mvi, u32 port);
	127	void (write_port_vsr_data)(struct mvs_info mvi, u32 port, u32 val);
	128	void (write_port_vsr_addr)(struct mvs_info mvi, u32 port, u32 addr);
	129
	130	u32 (read_port_irq_stat)(struct mvs_info mvi, u32 port);
	131	void (write_port_irq_stat)(struct mvs_info mvi, u32 port, u32 val);
	132
	133	u32 (read_port_irq_mask)(struct mvs_info mvi, u32 port);
	134	void (write_port_irq_mask)(struct mvs_info mvi, u32 port, u32 val);
	135
20b09c29	136	void (command_active)(struct mvs_info mvi, u32 slot_idx);
9dc9fd94	137	void (clear_srs_irq)(struct mvs_info mvi, u8 reg_set, u8 clear_all);
20b09c29 AY	138	void (issue_stop)(struct mvs_info mvi, enum mvs_port_type type,
	139	u32 tfs);
	140	void (start_delivery)(struct mvs_info mvi, u32 tx);
	141	u32 (rx_update)(struct mvs_info mvi);
	142	void (int_full)(struct mvs_info mvi);
	143	u8 (assign_reg_set)(struct mvs_info mvi, u8 *tfs);
	144	void (free_reg_set)(struct mvs_info mvi, u8 *tfs);
	145	u32 (*prd_size)(void);
	146	u32 (*prd_count)(void);
	147	void (make_prd)(struct scatterlist scatter, int nr, void *prd);
	148	void (detect_porttype)(struct mvs_info mvi, int i);
	149	int (oob_done)(struct mvs_info mvi, int i);
	150	void (fix_phy_info)(struct mvs_info mvi, int i,
	151	struct sas_identify_frame *id);
	152	void (phy_work_around)(struct mvs_info mvi, int i);
	153	void (phy_set_link_rate)(struct mvs_info mvi, u32 phy_id,
	154	struct sas_phy_linkrates *rates);
	155	u32 (*phy_max_link_rate)(void);
	156	void (phy_disable)(struct mvs_info mvi, u32 phy_id);
	157	void (phy_enable)(struct mvs_info mvi, u32 phy_id);
	158	void (phy_reset)(struct mvs_info mvi, u32 phy_id, int hard);
	159	void (stp_reset)(struct mvs_info mvi, u32 phy_id);
	160	void (clear_active_cmds)(struct mvs_info mvi);
	161	u32 (spi_read_data)(struct mvs_info mvi);
	162	void (spi_write_data)(struct mvs_info mvi, u32 data);
	163	int (spi_buildcmd)(struct mvs_info mvi,
	164	u32 *dwCmd,
	165	u8 cmd,
	166	u8 read,
	167	u8 length,
	168	u32 addr
	169	);
	170	int (spi_issuecmd)(struct mvs_info mvi, u32 cmd);
	171	int (spi_waitdataready)(struct mvs_info mvi, u32 timeout);
8882f081 XY	172	void (dma_fix)(struct mvs_info mvi, u32 phy_mask,
8882f081 XY	173	int buf_len, int from, void *prd);
83c7b61c	174	void (tune_interrupt)(struct mvs_info mvi, u32 time);
534ff101	175	void (non_spec_ncq_error)(struct mvs_info mvi);
c56f5f1d WW	176	int (gpio_write)(struct mvs_prv_info mvs_prv, u8 reg_type,
c56f5f1d WW	177	u8 reg_index, u8 reg_count, u8 *write_data);
20b09c29 AY	178
	179	};
	180
dd4969a8	181	struct mvs_chip_info {
20b09c29 AY	182	u32 n_host;
	183	u32 n_phy;
	184	u32 fis_offs;
	185	u32 fis_count;
	186	u32 srs_sz;
a4632aae	187	u32 sg_width;
20b09c29 AY	188	u32 slot_width;
20b09c29 AY	189	const struct mvs_dispatch *dispatch;
dd4969a8	190	};
a4632aae	191	#define MVS_MAX_SG (1U << mvi->chip->sg_width)
20b09c29 AY	192	#define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
	193	#define MVS_RX_FISL_SZ \
	194	(mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100))
	195	#define MVS_CHIP_DISP (mvi->chip->dispatch)
dd4969a8 JG	196
	197	struct mvs_err_info {
	198	__le32 flags;
	199	__le32 flags2;
	200	};
	201
	202	struct mvs_cmd_hdr {
	203	__le32 flags; /* PRD tbl len; SAS, SATA ctl */
	204	__le32 lens; /* cmd, max resp frame len */
	205	__le32 tags; /* targ port xfer tag; tag */
	206	__le32 data_len; /* data xfer len */
20b09c29	207	__le64 cmd_tbl; /* command table address */
dd4969a8 JG	208	__le64 open_frame; /* open addr frame address */
	209	__le64 status_buf; /* status buffer address */
	210	__le64 prd_tbl; /* PRD tbl address */
	211	__le32 reserved[4];
	212	};
	213
	214	struct mvs_port {
	215	struct asd_sas_port sas_port;
	216	u8 port_attached;
dd4969a8 JG	217	u8 wide_port_phymap;
	218	struct list_head list;
	219	};
	220
	221	struct mvs_phy {
20b09c29	222	struct mvs_info *mvi;
dd4969a8 JG	223	struct mvs_port *port;
	224	struct asd_sas_phy sas_phy;
	225	struct sas_identify identify;
	226	struct scsi_device *sdev;
20b09c29	227	struct timer_list timer;
dd4969a8 JG	228	u64 dev_sas_addr;
	229	u64 att_dev_sas_addr;
	230	u32 att_dev_info;
	231	u32 dev_info;
	232	u32 phy_type;
	233	u32 phy_status;
	234	u32 irq_status;
	235	u32 frame_rcvd_size;
	236	u8 frame_rcvd[32];
	237	u8 phy_attached;
20b09c29 AY	238	u8 phy_mode;
	239	u8 reserved[2];
	240	u32 phy_event;
dd4969a8 JG	241	enum sas_linkrate minimum_linkrate;
	242	enum sas_linkrate maximum_linkrate;
	243	};
	244
20b09c29	245	struct mvs_device {
9870d9a2	246	struct list_head dev_entry;
aa9f8328	247	enum sas_device_type dev_type;
9870d9a2	248	struct mvs_info *mvi_info;
20b09c29	249	struct domain_device *sas_device;
9dc9fd94	250	struct timer_list timer;
20b09c29 AY	251	u32 attached_phy;
20b09c29 AY	252	u32 device_id;
9dc9fd94	253	u32 running_req;
20b09c29 AY	254	u8 taskfileset;
	255	u8 dev_status;
	256	u16 reserved;
20b09c29 AY	257	};
20b09c29 AY	258
f1f82a91 XY	259	/* Generate PHY tunning parameters */
	260	struct phy_tuning {
	261	/* 1 bit, transmitter emphasis enable */
	262	u8 trans_emp_en:1;
	263	/* 4 bits, transmitter emphasis amplitude */
	264	u8 trans_emp_amp:4;
	265	/* 3 bits, reserved space */
	266	u8 Reserved_2bit_1:3;
	267	/* 5 bits, transmitter amplitude */
	268	u8 trans_amp:5;
	269	/* 2 bits, transmitter amplitude adjust */
	270	u8 trans_amp_adj:2;
	271	/* 1 bit, reserved space */
	272	u8 resv_2bit_2:1;
	273	/* 2 bytes, reserved space */
	274	u8 reserved[2];
	275	};
	276
	277	struct ffe_control {
	278	/* 4 bits, FFE Capacitor Select (value range 0~F) */
	279	u8 ffe_cap_sel:4;
	280	/* 3 bits, FFE Resistor Select (value range 0~7) */
	281	u8 ffe_rss_sel:3;
	282	/* 1 bit reserve*/
	283	u8 reserved:1;
	284	};
	285
	286	/*
	287	* HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes.
	288	* The data area is valid only Signature="MRVL".
	289	* If any member fills with 0xFF, the member is invalid.
	290	*/
	291	struct hba_info_page {
	292	/* Dword 0 */
	293	/* 4 bytes, structure signature,should be "MRVL" at first initial */
	294	u8 signature[4];
	295
	296	/* Dword 1-13 */
	297	u32 reserved1[13];
	298
	299	/* Dword 14-29 */
	300	/* 64 bytes, SAS address for each port */
	301	u64 sas_addr[8];
	302
	303	/* Dword 30-31 */
	304	/* 8 bytes for vanir 8 port PHY FFE seeting
	305	* BIT 0~3 : FFE Capacitor select(value range 0~F)
	306	* BIT 4~6 : FFE Resistor select(value range 0~7)
	307	* BIT 7: reserve.
	308	*/
	309
	310	struct ffe_control ffe_ctl[8];
	311	/* Dword 32 -43 */
	312	u32 reserved2[12];
	313
	314	/* Dword 44-45 */
	315	/* 8 bytes, 0: 1.5G, 1: 3.0G, should be 0x01 at first initial */
	316	u8 phy_rate[8];
	317
	318	/* Dword 46-53 */
	319	/* 32 bytes, PHY tuning parameters for each PHY*/
	320	struct phy_tuning phy_tuning[8];
	321
	322	/* Dword 54-63 */
323	u32 reserved3[10];
324	}; /* total 256 bytes */
325
dd4969a8	326	struct mvs_slot_info {
20b09c29 AY	327	struct list_head entry;
	328	union {
	329	struct sas_task *task;
	330	void *tdata;
	331	};
dd4969a8 JG	332	u32 n_elem;
dd4969a8 JG	333	u32 tx;
20b09c29	334	u32 slot_tag;
dd4969a8 JG	335
	336	/* DMA buffer for storing cmd tbl, open addr frame, status buffer,
	337	* and PRD table
	338	*/
	339	void *buf;
	340	dma_addr_t buf_dma;
dd4969a8 JG	341	void *response;
dd4969a8 JG	342	struct mvs_port *port;
20b09c29 AY	343	struct mvs_device *device;
20b09c29 AY	344	void *open_frame;
dd4969a8 JG	345	};
	346
	347	struct mvs_info {
	348	unsigned long flags;
	349
	350	/* host-wide lock */
	351	spinlock_t lock;
	352
	353	/* our device */
	354	struct pci_dev *pdev;
20b09c29	355	struct device *dev;
dd4969a8 JG	356
	357	/* enhanced mode registers */
	358	void __iomem *regs;
	359
20b09c29 AY	360	/* peripheral or soc registers */
20b09c29 AY	361	void __iomem *regs_ex;
dd4969a8 JG	362	u8 sas_addr[SAS_ADDR_SIZE];
	363
	364	/* SCSI/SAS glue */
20b09c29	365	struct sas_ha_struct *sas;
dd4969a8 JG	366	struct Scsi_Host *shost;
	367
	368	/* TX (delivery) DMA ring */
	369	__le32 *tx;
	370	dma_addr_t tx_dma;
	371
	372	/* cached next-producer idx */
	373	u32 tx_prod;
	374
	375	/* RX (completion) DMA ring */
20b09c29	376	__le32 *rx;
dd4969a8 JG	377	dma_addr_t rx_dma;
	378
	379	/* RX consumer idx */
	380	u32 rx_cons;
	381
	382	/* RX'd FIS area */
	383	__le32 *rx_fis;
	384	dma_addr_t rx_fis_dma;
	385
	386	/* DMA command header slots */
	387	struct mvs_cmd_hdr *slot;
	388	dma_addr_t slot_dma;
	389
20b09c29	390	u32 chip_id;
dd4969a8 JG	391	const struct mvs_chip_info *chip;
dd4969a8 JG	392
20b09c29	393	int tags_num;
b89e8f53	394	unsigned long *tags;
20b09c29	395	/* further per-slot information */
dd4969a8 JG	396	struct mvs_phy phy[MVS_MAX_PHYS];
dd4969a8 JG	397	struct mvs_port port[MVS_MAX_PHYS];
20b09c29 AY	398	u32 id;
	399	u64 sata_reg_set;
	400	struct list_head *hba_list;
	401	struct list_head soc_entry;
	402	struct list_head wq_list;
	403	unsigned long instance;
	404	u16 flashid;
	405	u32 flashsize;
	406	u32 flashsectSize;
	407
	408	void *addon;
f1f82a91	409	struct hba_info_page hba_info_param;
20b09c29	410	struct mvs_device devices[MVS_MAX_DEVICES];
20b09c29 AY	411	void *bulk_buffer;
20b09c29 AY	412	dma_addr_t bulk_buffer_dma;
8882f081 XY	413	void *bulk_buffer1;
8882f081 XY	414	dma_addr_t bulk_buffer_dma1;
20b09c29	415	#define TRASH_BUCKET_SIZE 0x20000
0b15fb1f	416	void *dma_pool;
20b09c29 AY	417	struct mvs_slot_info slot_info[0];
	418	};
	419
	420	struct mvs_prv_info{
	421	u8 n_host;
	422	u8 n_phy;
84fbd0ce XY	423	u8 scan_finished;
84fbd0ce XY	424	u8 reserve;
20b09c29	425	struct mvs_info *mvi[2];
6f8ac161	426	struct tasklet_struct mv_tasklet;
20b09c29 AY	427	};
	428
	429	struct mvs_wq {
	430	struct delayed_work work_q;
	431	struct mvs_info *mvi;
	432	void *data;
	433	int handler;
	434	struct list_head entry;
dd4969a8 JG	435	};
dd4969a8 JG	436
20b09c29 AY	437	struct mvs_task_exec_info {
	438	struct sas_task *task;
	439	struct mvs_cmd_hdr *hdr;
	440	struct mvs_port *port;
	441	u32 tag;
	442	int n_elem;
	443	};
	444
20b09c29 AY	445	/****************** function prototype *******************/
	446	void mvs_get_sas_addr(void *buf, u32 buflen);
	447	void mvs_tag_clear(struct mvs_info *mvi, u32 tag);
	448	void mvs_tag_free(struct mvs_info *mvi, u32 tag);
	449	void mvs_tag_set(struct mvs_info *mvi, unsigned int tag);
	450	int mvs_tag_alloc(struct mvs_info mvi, u32 tag_out);
	451	void mvs_tag_init(struct mvs_info *mvi);
	452	void mvs_iounmap(void __iomem *regs);
	453	int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex);
	454	void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard);
dd4969a8 JG	455	int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
dd4969a8 JG	456	void *funcdata);
6f039790 GKH	457	void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
6f039790 GKH	458	u32 off_hi, u64 sas_addr);
dd4969a8 JG	459	void mvs_scan_start(struct Scsi_Host *shost);
dd4969a8 JG	460	int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time);
79855d17	461	int mvs_queue_command(struct sas_task *task, gfp_t gfp_flags);
20b09c29 AY	462	int mvs_abort_task(struct sas_task *task);
	463	int mvs_abort_task_set(struct domain_device dev, u8 lun);
	464	int mvs_clear_aca(struct domain_device dev, u8 lun);
	465	int mvs_clear_task_set(struct domain_device dev, u8 lun);
dd4969a8	466	void mvs_port_formed(struct asd_sas_phy *sas_phy);
20b09c29 AY	467	void mvs_port_deformed(struct asd_sas_phy *sas_phy);
	468	int mvs_dev_found(struct domain_device *dev);
	469	void mvs_dev_gone(struct domain_device *dev);
	470	int mvs_lu_reset(struct domain_device dev, u8 lun);
	471	int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags);
dd4969a8	472	int mvs_I_T_nexus_reset(struct domain_device *dev);
20b09c29	473	int mvs_query_task(struct sas_task *task);
9dc9fd94 S	474	void mvs_release_task(struct mvs_info *mvi,
	475	struct domain_device *dev);
	476	void mvs_do_release_task(struct mvs_info *mvi, int phy_no,
20b09c29 AY	477	struct domain_device *dev);
	478	void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events);
	479	void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
	480	int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
534ff101	481	struct mvs_device mvs_find_dev_by_reg_set(struct mvs_info mvi, u8 reg_set);
c56f5f1d WW	482	int mvs_gpio_write(struct sas_ha_struct *, u8 reg_type, u8 reg_index,
c56f5f1d WW	483	u8 reg_count, u8 *write_data);
dd4969a8	484	#endif
20b09c29	485