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qla2xxx: prevent board_disable from running during EEH
[linux-2.6-block.git] / drivers / scsi / mvsas / mv_init.c
CommitLineData
dd4969a8 1/*
20b09c29
AY		 2 * Marvell 88SE64xx/88SE94xx pci init
3 *
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
0b15fb1f 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
20b09c29
AY		 7 *
8 * This file is licensed under GPLv2.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; version 2 of the
13 * License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
23 * USA
24*/
dd4969a8 25
dd4969a8
JG		 26
27#include "mv_sas.h"
dd4969a8 28
83c7b61c
XY		 29int interrupt_coalescing = 0x80;
30
dd4969a8 31static struct scsi_transport_template *mvs_stt;
dd4969a8 32static const struct mvs_chip_info mvs_chips[] = {
a4632aae
XY		 33 [chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
34 [chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
35 [chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, },
36 [chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
37 [chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
38 [chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
39 [chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },
40 [chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },
41 [chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },
dd4969a8
JG		 42};
43
83c7b61c
XY		 44struct device_attribute *mvst_host_attrs[];
45
20b09c29
AY		 46#define SOC_SAS_NUM 2
47
dd4969a8
JG		 48static struct scsi_host_template mvs_sht = {
49 .module = THIS_MODULE,
50 .name = DRV_NAME,
51 .queuecommand = sas_queuecommand,
52 .target_alloc = sas_target_alloc,
e211e2c7 53 .slave_configure = sas_slave_configure,
dd4969a8
JG		 54 .scan_finished = mvs_scan_finished,
55 .scan_start = mvs_scan_start,
56 .change_queue_depth = sas_change_queue_depth,
dd4969a8
JG		 57 .bios_param = sas_bios_param,
58 .can_queue = 1,
dd4969a8 59 .this_id = -1,
b89e8f53 60 .sg_tablesize = SG_ALL,
dd4969a8
JG		 61 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
62 .use_clustering = ENABLE_CLUSTERING,
9dc9fd94 63 .eh_device_reset_handler = sas_eh_device_reset_handler,
dd4969a8 64 .eh_bus_reset_handler = sas_eh_bus_reset_handler,
dd4969a8
JG		 65 .target_destroy = sas_target_destroy,
66 .ioctl = sas_ioctl,
83c7b61c 67 .shost_attrs = mvst_host_attrs,
2ecb204d 68 .use_blk_tags = 1,
c40ecc12 69 .track_queue_depth = 1,
dd4969a8
JG		 70};
71
72static struct sas_domain_function_template mvs_transport_ops = {
20b09c29 73 .lldd_dev_found = mvs_dev_found,
9dc9fd94 74 .lldd_dev_gone = mvs_dev_gone,
20b09c29 75 .lldd_execute_task = mvs_queue_command,
dd4969a8 76 .lldd_control_phy = mvs_phy_control,
20b09c29
AY		 77
78 .lldd_abort_task = mvs_abort_task,
79 .lldd_abort_task_set = mvs_abort_task_set,
80 .lldd_clear_aca = mvs_clear_aca,
9dc9fd94 81 .lldd_clear_task_set = mvs_clear_task_set,
dd4969a8 82 .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset,
20b09c29
AY		 83 .lldd_lu_reset = mvs_lu_reset,
84 .lldd_query_task = mvs_query_task,
20b09c29
AY		 85 .lldd_port_formed = mvs_port_formed,
86 .lldd_port_deformed = mvs_port_deformed,
87
dd4969a8
JG		 88};
89
6f039790 90static void mvs_phy_init(struct mvs_info *mvi, int phy_id)
dd4969a8
JG		 91{
92 struct mvs_phy *phy = &mvi->phy[phy_id];
93 struct asd_sas_phy *sas_phy = &phy->sas_phy;
94
20b09c29 95 phy->mvi = mvi;
84fbd0ce 96 phy->port = NULL;
20b09c29 97 init_timer(&phy->timer);
dd4969a8
JG		 98 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
99 sas_phy->class = SAS;
100 sas_phy->iproto = SAS_PROTOCOL_ALL;
101 sas_phy->tproto = 0;
102 sas_phy->type = PHY_TYPE_PHYSICAL;
103 sas_phy->role = PHY_ROLE_INITIATOR;
104 sas_phy->oob_mode = OOB_NOT_CONNECTED;
105 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
106
107 sas_phy->id = phy_id;
108 sas_phy->sas_addr = &mvi->sas_addr[0];
109 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
20b09c29 110 sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
dd4969a8
JG		 111 sas_phy->lldd_phy = phy;
112}
113
114static void mvs_free(struct mvs_info *mvi)
115{
20b09c29
AY		 116 struct mvs_wq *mwq;
117 int slot_nr;
dd4969a8
JG		 118
119 if (!mvi)
120 return;
121
20b09c29
AY		 122 if (mvi->flags & MVF_FLAG_SOC)
123 slot_nr = MVS_SOC_SLOTS;
124 else
b89e8f53 125 slot_nr = MVS_CHIP_SLOT_SZ;
dd4969a8 126
0b15fb1f
XY		 127 if (mvi->dma_pool)
128 pci_pool_destroy(mvi->dma_pool);
dd4969a8
JG		 129
130 if (mvi->tx)
20b09c29 131 dma_free_coherent(mvi->dev,
dd4969a8
JG		 132 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
133 mvi->tx, mvi->tx_dma);
134 if (mvi->rx_fis)
20b09c29 135 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
dd4969a8
JG		 136 mvi->rx_fis, mvi->rx_fis_dma);
137 if (mvi->rx)
20b09c29 138 dma_free_coherent(mvi->dev,
dd4969a8
JG		 139 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
140 mvi->rx, mvi->rx_dma);
141 if (mvi->slot)
20b09c29
AY		 142 dma_free_coherent(mvi->dev,
143 sizeof(*mvi->slot) * slot_nr,
dd4969a8 144 mvi->slot, mvi->slot_dma);
8882f081 145
20b09c29
AY		 146 if (mvi->bulk_buffer)
147 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
148 mvi->bulk_buffer, mvi->bulk_buffer_dma);
8882f081
XY		 149 if (mvi->bulk_buffer1)
150 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
151 mvi->bulk_buffer1, mvi->bulk_buffer_dma1);
20b09c29
AY		 152
153 MVS_CHIP_DISP->chip_iounmap(mvi);
dd4969a8
JG		 154 if (mvi->shost)
155 scsi_host_put(mvi->shost);
20b09c29
AY		 156 list_for_each_entry(mwq, &mvi->wq_list, entry)
157 cancel_delayed_work(&mwq->work_q);
b89e8f53 158 kfree(mvi->tags);
dd4969a8
JG		 159 kfree(mvi);
160}
161
6f8ac161 162#ifdef CONFIG_SCSI_MVSAS_TASKLET
20b09c29 163static void mvs_tasklet(unsigned long opaque)
dd4969a8 164{
20b09c29
AY		 165 u32 stat;
166 u16 core_nr, i = 0;
dd4969a8 167
20b09c29
AY		 168 struct mvs_info *mvi;
169 struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;
170
171 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
172 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
173
174 if (unlikely(!mvi))
175 BUG_ON(1);
176
6f8ac161
XY		 177 stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq);
178 if (!stat)
179 goto out;
180
20b09c29
AY		 181 for (i = 0; i < core_nr; i++) {
182 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
6f8ac161 183 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat);
20b09c29 184 }
6f8ac161
XY		 185out:
186 MVS_CHIP_DISP->interrupt_enable(mvi);
dd4969a8 187
dd4969a8
JG		 188}
189#endif
190
191static irqreturn_t mvs_interrupt(int irq, void *opaque)
192{
6f8ac161 193 u32 core_nr;
dd4969a8 194 u32 stat;
20b09c29
AY		 195 struct mvs_info *mvi;
196 struct sas_ha_struct *sha = opaque;
6f8ac161
XY		 197#ifndef CONFIG_SCSI_MVSAS_TASKLET
198 u32 i;
199#endif
dd4969a8 200
20b09c29
AY		 201 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
202 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
dd4969a8 203
20b09c29 204 if (unlikely(!mvi))
dd4969a8 205 return IRQ_NONE;
6f8ac161
XY		 206#ifdef CONFIG_SCSI_MVSAS_TASKLET
207 MVS_CHIP_DISP->interrupt_disable(mvi);
208#endif
dd4969a8 209
20b09c29 210 stat = MVS_CHIP_DISP->isr_status(mvi, irq);
6f8ac161
XY		 211 if (!stat) {
212 #ifdef CONFIG_SCSI_MVSAS_TASKLET
213 MVS_CHIP_DISP->interrupt_enable(mvi);
214 #endif
20b09c29 215 return IRQ_NONE;
6f8ac161 216 }
dd4969a8 217
6f8ac161
XY		 218#ifdef CONFIG_SCSI_MVSAS_TASKLET
219 tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
dd4969a8 220#else
20b09c29
AY		 221 for (i = 0; i < core_nr; i++) {
222 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
223 MVS_CHIP_DISP->isr(mvi, irq, stat);
224 }
dd4969a8
JG		 225#endif
226 return IRQ_HANDLED;
227}
228
6f039790 229static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
dd4969a8 230{
9dc9fd94 231 int i = 0, slot_nr;
0b15fb1f 232 char pool_name[32];
dd4969a8 233
20b09c29
AY		 234 if (mvi->flags & MVF_FLAG_SOC)
235 slot_nr = MVS_SOC_SLOTS;
236 else
b89e8f53 237 slot_nr = MVS_CHIP_SLOT_SZ;
dd4969a8
JG		 238
239 spin_lock_init(&mvi->lock);
20b09c29 240 for (i = 0; i < mvi->chip->n_phy; i++) {
dd4969a8 241 mvs_phy_init(mvi, i);
dd4969a8
JG		 242 mvi->port[i].wide_port_phymap = 0;
243 mvi->port[i].port_attached = 0;
244 INIT_LIST_HEAD(&mvi->port[i].list);
245 }
20b09c29
AY		 246 for (i = 0; i < MVS_MAX_DEVICES; i++) {
247 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
aa9f8328 248 mvi->devices[i].dev_type = SAS_PHY_UNUSED;
20b09c29
AY		 249 mvi->devices[i].device_id = i;
250 mvi->devices[i].dev_status = MVS_DEV_NORMAL;
9dc9fd94 251 init_timer(&mvi->devices[i].timer);
20b09c29 252 }
dd4969a8
JG		 253
254 /*
255 * alloc and init our DMA areas
256 */
20b09c29 257 mvi->tx = dma_alloc_coherent(mvi->dev,
dd4969a8
JG		 258 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
259 &mvi->tx_dma, GFP_KERNEL);
260 if (!mvi->tx)
261 goto err_out;
262 memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ);
20b09c29 263 mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
dd4969a8
JG		 264 &mvi->rx_fis_dma, GFP_KERNEL);
265 if (!mvi->rx_fis)
266 goto err_out;
267 memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ);
268
20b09c29 269 mvi->rx = dma_alloc_coherent(mvi->dev,
dd4969a8
JG		 270 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
271 &mvi->rx_dma, GFP_KERNEL);
272 if (!mvi->rx)
273 goto err_out;
274 memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1));
dd4969a8
JG		 275 mvi->rx[0] = cpu_to_le32(0xfff);
276 mvi->rx_cons = 0xfff;
277
20b09c29
AY		 278 mvi->slot = dma_alloc_coherent(mvi->dev,
279 sizeof(*mvi->slot) * slot_nr,
dd4969a8
JG		 280 &mvi->slot_dma, GFP_KERNEL);
281 if (!mvi->slot)
282 goto err_out;
20b09c29 283 memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr);
dd4969a8 284
20b09c29
AY		 285 mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
286 TRASH_BUCKET_SIZE,
287 &mvi->bulk_buffer_dma, GFP_KERNEL);
288 if (!mvi->bulk_buffer)
289 goto err_out;
8882f081
XY		 290
291 mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev,
292 TRASH_BUCKET_SIZE,
293 &mvi->bulk_buffer_dma1, GFP_KERNEL);
294 if (!mvi->bulk_buffer1)
295 goto err_out;
296
0b15fb1f
XY		 297 sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id);
298 mvi->dma_pool = pci_pool_create(pool_name, mvi->pdev, MVS_SLOT_BUF_SZ, 16, 0);
299 if (!mvi->dma_pool) {
300 printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name);
dd4969a8 301 goto err_out;
dd4969a8 302 }
0b15fb1f
XY		 303 mvi->tags_num = slot_nr;
304
20b09c29
AY		 305 /* Initialize tags */
306 mvs_tag_init(mvi);
307 return 0;
308err_out:
309 return 1;
310}
311
dd4969a8 312
20b09c29
AY		 313int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
314{
315 unsigned long res_start, res_len, res_flag, res_flag_ex = 0;
316 struct pci_dev *pdev = mvi->pdev;
317 if (bar_ex != -1) {
318 /*
319 * ioremap main and peripheral registers
320 */
321 res_start = pci_resource_start(pdev, bar_ex);
322 res_len = pci_resource_len(pdev, bar_ex);
323 if (!res_start || !res_len)
324 goto err_out;
325
326 res_flag_ex = pci_resource_flags(pdev, bar_ex);
327 if (res_flag_ex & IORESOURCE_MEM) {
328 if (res_flag_ex & IORESOURCE_CACHEABLE)
329 mvi->regs_ex = ioremap(res_start, res_len);
330 else
331 mvi->regs_ex = ioremap_nocache(res_start,
332 res_len);
333 } else
334 mvi->regs_ex = (void *)res_start;
335 if (!mvi->regs_ex)
336 goto err_out;
337 }
338
339 res_start = pci_resource_start(pdev, bar);
340 res_len = pci_resource_len(pdev, bar);
341 if (!res_start || !res_len)
342 goto err_out;
343
344 res_flag = pci_resource_flags(pdev, bar);
345 if (res_flag & IORESOURCE_CACHEABLE)
346 mvi->regs = ioremap(res_start, res_len);
347 else
348 mvi->regs = ioremap_nocache(res_start, res_len);
349
350 if (!mvi->regs) {
351 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
352 iounmap(mvi->regs_ex);
353 mvi->regs_ex = NULL;
dd4969a8 354 goto err_out;
20b09c29
AY		 355 }
356
357 return 0;
358err_out:
359 return -1;
360}
361
362void mvs_iounmap(void __iomem *regs)
363{
364 iounmap(regs);
365}
366
6f039790 367static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev,
20b09c29
AY		 368 const struct pci_device_id *ent,
369 struct Scsi_Host *shost, unsigned int id)
370{
84fbd0ce 371 struct mvs_info *mvi = NULL;
20b09c29
AY		 372 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
373
b89e8f53
XY		 374 mvi = kzalloc(sizeof(*mvi) +
375 (1L << mvs_chips[ent->driver_data].slot_width) *
376 sizeof(struct mvs_slot_info), GFP_KERNEL);
20b09c29
AY		 377 if (!mvi)
378 return NULL;
dd4969a8 379
20b09c29
AY		 380 mvi->pdev = pdev;
381 mvi->dev = &pdev->dev;
382 mvi->chip_id = ent->driver_data;
383 mvi->chip = &mvs_chips[mvi->chip_id];
384 INIT_LIST_HEAD(&mvi->wq_list);
20b09c29
AY		 385
386 ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
387 ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
388
389 mvi->id = id;
390 mvi->sas = sha;
391 mvi->shost = shost;
20b09c29 392
b89e8f53
XY		 393 mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL);
394 if (!mvi->tags)
395 goto err_out;
396
20b09c29
AY		 397 if (MVS_CHIP_DISP->chip_ioremap(mvi))
398 goto err_out;
399 if (!mvs_alloc(mvi, shost))
400 return mvi;
dd4969a8
JG		 401err_out:
402 mvs_free(mvi);
403 return NULL;
404}
405
dd4969a8
JG		 406static int pci_go_64(struct pci_dev *pdev)
407{
408 int rc;
409
410 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
411 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
412 if (rc) {
413 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
414 if (rc) {
415 dev_printk(KERN_ERR, &pdev->dev,
416 "64-bit DMA enable failed\n");
417 return rc;
418 }
419 }
420 } else {
421 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
422 if (rc) {
423 dev_printk(KERN_ERR, &pdev->dev,
424 "32-bit DMA enable failed\n");
425 return rc;
426 }
427 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
428 if (rc) {
429 dev_printk(KERN_ERR, &pdev->dev,
430 "32-bit consistent DMA enable failed\n");
431 return rc;
432 }
433 }
434
435 return rc;
436}
437
6f039790 438static int mvs_prep_sas_ha_init(struct Scsi_Host *shost,
20b09c29
AY		 439 const struct mvs_chip_info *chip_info)
440{
441 int phy_nr, port_nr; unsigned short core_nr;
442 struct asd_sas_phy **arr_phy;
443 struct asd_sas_port **arr_port;
444 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
445
446 core_nr = chip_info->n_host;
447 phy_nr = core_nr * chip_info->n_phy;
448 port_nr = phy_nr;
449
450 memset(sha, 0x00, sizeof(struct sas_ha_struct));
451 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
452 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
453 if (!arr_phy || !arr_port)
454 goto exit_free;
455
456 sha->sas_phy = arr_phy;
457 sha->sas_port = arr_port;
9dc9fd94 458 sha->core.shost = shost;
20b09c29
AY		 459
460 sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);
461 if (!sha->lldd_ha)
462 goto exit_free;
463
464 ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
465
466 shost->transportt = mvs_stt;
a4632aae 467 shost->max_id = MVS_MAX_DEVICES;
20b09c29
AY		 468 shost->max_lun = ~0;
469 shost->max_channel = 1;
470 shost->max_cmd_len = 16;
471
472 return 0;
473exit_free:
474 kfree(arr_phy);
475 kfree(arr_port);
476 return -1;
477
478}
479
6f039790 480static void mvs_post_sas_ha_init(struct Scsi_Host *shost,
20b09c29
AY		 481 const struct mvs_chip_info *chip_info)
482{
483 int can_queue, i = 0, j = 0;
484 struct mvs_info *mvi = NULL;
485 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
486 unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
487
488 for (j = 0; j < nr_core; j++) {
489 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
490 for (i = 0; i < chip_info->n_phy; i++) {
491 sha->sas_phy[j * chip_info->n_phy + i] =
492 &mvi->phy[i].sas_phy;
493 sha->sas_port[j * chip_info->n_phy + i] =
494 &mvi->port[i].sas_port;
495 }
496 }
497
498 sha->sas_ha_name = DRV_NAME;
499 sha->dev = mvi->dev;
500 sha->lldd_module = THIS_MODULE;
501 sha->sas_addr = &mvi->sas_addr[0];
502
503 sha->num_phys = nr_core * chip_info->n_phy;
504
20b09c29
AY		 505 if (mvi->flags & MVF_FLAG_SOC)
506 can_queue = MVS_SOC_CAN_QUEUE;
507 else
b89e8f53 508 can_queue = MVS_CHIP_SLOT_SZ;
20b09c29 509
a4632aae 510 shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG);
20b09c29 511 shost->can_queue = can_queue;
b89e8f53 512 mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE;
20b09c29
AY		 513 sha->core.shost = mvi->shost;
514}
515
516static void mvs_init_sas_add(struct mvs_info *mvi)
517{
518 u8 i;
519 for (i = 0; i < mvi->chip->n_phy; i++) {
520 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
521 mvi->phy[i].dev_sas_addr =
522 cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
523 }
524
525 memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
526}
527
6f039790 528static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent)
dd4969a8 529{
20b09c29 530 unsigned int rc, nhost = 0;
dd4969a8 531 struct mvs_info *mvi;
6f8ac161 532 struct mvs_prv_info *mpi;
dd4969a8 533 irq_handler_t irq_handler = mvs_interrupt;
20b09c29
AY		 534 struct Scsi_Host *shost = NULL;
535 const struct mvs_chip_info *chip;
dd4969a8 536
20b09c29
AY		 537 dev_printk(KERN_INFO, &pdev->dev,
538 "mvsas: driver version %s\n", DRV_VERSION);
dd4969a8
JG		 539 rc = pci_enable_device(pdev);
540 if (rc)
20b09c29 541 goto err_out_enable;
dd4969a8
JG		 542
543 pci_set_master(pdev);
544
545 rc = pci_request_regions(pdev, DRV_NAME);
546 if (rc)
547 goto err_out_disable;
548
549 rc = pci_go_64(pdev);
550 if (rc)
551 goto err_out_regions;
552
20b09c29
AY		 553 shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
554 if (!shost) {
dd4969a8
JG		 555 rc = -ENOMEM;
556 goto err_out_regions;
557 }
558
20b09c29
AY		 559 chip = &mvs_chips[ent->driver_data];
560 SHOST_TO_SAS_HA(shost) =
561 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
562 if (!SHOST_TO_SAS_HA(shost)) {
563 kfree(shost);
564 rc = -ENOMEM;
565 goto err_out_regions;
dd4969a8 566 }
dd4969a8 567
20b09c29
AY		 568 rc = mvs_prep_sas_ha_init(shost, chip);
569 if (rc) {
570 kfree(shost);
571 rc = -ENOMEM;
572 goto err_out_regions;
573 }
dd4969a8 574
20b09c29 575 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
dd4969a8 576
20b09c29
AY		 577 do {
578 mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
579 if (!mvi) {
580 rc = -ENOMEM;
581 goto err_out_regions;
582 }
583
f1f82a91
XY		 584 memset(&mvi->hba_info_param, 0xFF,
585 sizeof(struct hba_info_page));
586
20b09c29
AY		 587 mvs_init_sas_add(mvi);
588
589 mvi->instance = nhost;
590 rc = MVS_CHIP_DISP->chip_init(mvi);
591 if (rc) {
592 mvs_free(mvi);
593 goto err_out_regions;
594 }
595 nhost++;
596 } while (nhost < chip->n_host);
6f8ac161
XY		 597 mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha);
598#ifdef CONFIG_SCSI_MVSAS_TASKLET
599 tasklet_init(&(mpi->mv_tasklet), mvs_tasklet,
9dc9fd94
S		 600 (unsigned long)SHOST_TO_SAS_HA(shost));
601#endif
20b09c29
AY		 602
603 mvs_post_sas_ha_init(shost, chip);
604
605 rc = scsi_add_host(shost, &pdev->dev);
dd4969a8
JG		 606 if (rc)
607 goto err_out_shost;
608
20b09c29
AY		 609 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
610 if (rc)
611 goto err_out_shost;
612 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,
613 DRV_NAME, SHOST_TO_SAS_HA(shost));
614 if (rc)
615 goto err_not_sas;
dd4969a8 616
20b09c29 617 MVS_CHIP_DISP->interrupt_enable(mvi);
dd4969a8
JG		 618
619 scsi_scan_host(mvi->shost);
620
621 return 0;
622
20b09c29
AY		 623err_not_sas:
624 sas_unregister_ha(SHOST_TO_SAS_HA(shost));
dd4969a8
JG		 625err_out_shost:
626 scsi_remove_host(mvi->shost);
dd4969a8
JG		 627err_out_regions:
628 pci_release_regions(pdev);
629err_out_disable:
630 pci_disable_device(pdev);
20b09c29 631err_out_enable:
dd4969a8
JG		 632 return rc;
633}
634
6f039790 635static void mvs_pci_remove(struct pci_dev *pdev)
dd4969a8 636{
20b09c29
AY		 637 unsigned short core_nr, i = 0;
638 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
639 struct mvs_info *mvi = NULL;
dd4969a8 640
20b09c29
AY		 641 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
642 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
dd4969a8 643
6f8ac161
XY		 644#ifdef CONFIG_SCSI_MVSAS_TASKLET
645 tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);
20b09c29 646#endif
dd4969a8 647
20b09c29
AY		 648 sas_unregister_ha(sha);
649 sas_remove_host(mvi->shost);
650 scsi_remove_host(mvi->shost);
651
652 MVS_CHIP_DISP->interrupt_disable(mvi);
b89e8f53 653 free_irq(mvi->pdev->irq, sha);
20b09c29
AY		 654 for (i = 0; i < core_nr; i++) {
655 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
dd4969a8 656 mvs_free(mvi);
dd4969a8 657 }
20b09c29
AY		 658 kfree(sha->sas_phy);
659 kfree(sha->sas_port);
660 kfree(sha);
661 pci_release_regions(pdev);
dd4969a8 662 pci_disable_device(pdev);
20b09c29 663 return;
dd4969a8
JG		 664}
665
6f039790 666static struct pci_device_id mvs_pci_table[] = {
dd4969a8
JG		 667 { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
668 { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
669 {
670 .vendor = PCI_VENDOR_ID_MARVELL,
671 .device = 0x6440,
672 .subvendor = PCI_ANY_ID,
673 .subdevice = 0x6480,
674 .class = 0,
675 .class_mask = 0,
20b09c29 676 .driver_data = chip_6485,
dd4969a8
JG		 677 },
678 { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
20b09c29
AY		 679 { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },
680 { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
681 { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
f31491dc
NC		 682 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 },
683 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 },
7ec4ad01 684 { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 },
463b8977
HLT		 685 { PCI_VDEVICE(TTI, 0x2710), chip_9480 },
686 { PCI_VDEVICE(TTI, 0x2720), chip_9480 },
687 { PCI_VDEVICE(TTI, 0x2721), chip_9480 },
688 { PCI_VDEVICE(TTI, 0x2722), chip_9480 },
689 { PCI_VDEVICE(TTI, 0x2740), chip_9480 },
690 { PCI_VDEVICE(TTI, 0x2744), chip_9480 },
691 { PCI_VDEVICE(TTI, 0x2760), chip_9480 },
f7e45b6a 692 {
412e704f 693 .vendor = PCI_VENDOR_ID_MARVELL_EXT,
f7e45b6a
XY		 694 .device = 0x9480,
695 .subvendor = PCI_ANY_ID,
696 .subdevice = 0x9480,
697 .class = 0,
698 .class_mask = 0,
699 .driver_data = chip_9480,
700 },
82140283 701 {
412e704f 702 .vendor = PCI_VENDOR_ID_MARVELL_EXT,
82140283
XY		 703 .device = 0x9445,
704 .subvendor = PCI_ANY_ID,
705 .subdevice = 0x9480,
706 .class = 0,
707 .class_mask = 0,
708 .driver_data = chip_9445,
709 },
710 {
412e704f 711 .vendor = PCI_VENDOR_ID_MARVELL_EXT,
82140283
XY		 712 .device = 0x9485,
713 .subvendor = PCI_ANY_ID,
714 .subdevice = 0x9480,
715 .class = 0,
716 .class_mask = 0,
717 .driver_data = chip_9485,
718 },
e90b25fa
BH		 719 {
720 .vendor = PCI_VENDOR_ID_MARVELL_EXT,
721 .device = 0x9485,
722 .subvendor = PCI_ANY_ID,
723 .subdevice = 0x9485,
724 .class = 0,
725 .class_mask = 0,
726 .driver_data = chip_9485,
727 },
99a700bc
RJ		 728 { PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */
729 { PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
730 { PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
731 { PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
732 { PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
733 { PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
734 { PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
735 { PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
736 { PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
737 { PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */
dd4969a8
JG		 738
739 { } /* terminate list */
740};
741
742static struct pci_driver mvs_pci_driver = {
743 .name = DRV_NAME,
744 .id_table = mvs_pci_table,
745 .probe = mvs_pci_init,
6f039790 746 .remove = mvs_pci_remove,
dd4969a8
JG		 747};
748
83c7b61c
XY		 749static ssize_t
750mvs_show_driver_version(struct device *cdev,
751 struct device_attribute *attr, char *buffer)
752{
753 return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION);
754}
755
756static DEVICE_ATTR(driver_version,
757 S_IRUGO,
758 mvs_show_driver_version,
759 NULL);
760
761static ssize_t
762mvs_store_interrupt_coalescing(struct device *cdev,
763 struct device_attribute *attr,
764 const char *buffer, size_t size)
765{
766 int val = 0;
767 struct mvs_info *mvi = NULL;
768 struct Scsi_Host *shost = class_to_shost(cdev);
769 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
770 u8 i, core_nr;
771 if (buffer == NULL)
772 return size;
773
774 if (sscanf(buffer, "%d", &val) != 1)
775 return -EINVAL;
776
777 if (val >= 0x10000) {
778 mv_dprintk("interrupt coalescing timer %d us is"
779 "too long\n", val);
780 return strlen(buffer);
781 }
782
783 interrupt_coalescing = val;
784
785 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
786 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
787
788 if (unlikely(!mvi))
789 return -EINVAL;
790
791 for (i = 0; i < core_nr; i++) {
792 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
793 if (MVS_CHIP_DISP->tune_interrupt)
794 MVS_CHIP_DISP->tune_interrupt(mvi,
795 interrupt_coalescing);
796 }
797 mv_dprintk("set interrupt coalescing time to %d us\n",
798 interrupt_coalescing);
799 return strlen(buffer);
800}
801
802static ssize_t mvs_show_interrupt_coalescing(struct device *cdev,
803 struct device_attribute *attr, char *buffer)
804{
805 return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing);
806}
807
808static DEVICE_ATTR(interrupt_coalescing,
809 S_IRUGO|S_IWUSR,
810 mvs_show_interrupt_coalescing,
811 mvs_store_interrupt_coalescing);
812
20b09c29
AY		 813/* task handler */
814struct task_struct *mvs_th;
dd4969a8
JG		 815static int __init mvs_init(void)
816{
817 int rc;
dd4969a8
JG		 818 mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
819 if (!mvs_stt)
820 return -ENOMEM;
821
822 rc = pci_register_driver(&mvs_pci_driver);
823 if (rc)
824 goto err_out;
825
826 return 0;
827
828err_out:
829 sas_release_transport(mvs_stt);
830 return rc;
831}
832
833static void __exit mvs_exit(void)
834{
835 pci_unregister_driver(&mvs_pci_driver);
836 sas_release_transport(mvs_stt);
837}
838
83c7b61c
XY		 839struct device_attribute *mvst_host_attrs[] = {
840 &dev_attr_driver_version,
841 &dev_attr_interrupt_coalescing,
842 NULL,
843};
844
dd4969a8
JG		 845module_init(mvs_init);
846module_exit(mvs_exit);
847
848MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
849MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
850MODULE_VERSION(DRV_VERSION);
851MODULE_LICENSE("GPL");
20b09c29 852#ifdef CONFIG_PCI
dd4969a8 853MODULE_DEVICE_TABLE(pci, mvs_pci_table);
20b09c29 854#endif
Linux 6.x block layer and io_uring tree(s)