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f92363d1 SR |
1 | /* |
2 | * This is the Fusion MPT base driver providing common API layer interface | |
3 | * for access to MPT (Message Passing Technology) firmware. | |
4 | * | |
5 | * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c | |
a4ffce0d | 6 | * Copyright (C) 2012-2014 LSI Corporation |
a03bd153 SR |
7 | * Copyright (C) 2013-2014 Avago Technologies |
8 | * (mailto: MPT-FusionLinux.pdl@avagotech.com) | |
f92363d1 SR |
9 | * |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version 2 | |
13 | * of the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * NO WARRANTY | |
21 | * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR | |
22 | * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT | |
23 | * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, | |
24 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is | |
25 | * solely responsible for determining the appropriateness of using and | |
26 | * distributing the Program and assumes all risks associated with its | |
27 | * exercise of rights under this Agreement, including but not limited to | |
28 | * the risks and costs of program errors, damage to or loss of data, | |
29 | * programs or equipment, and unavailability or interruption of operations. | |
30 | ||
31 | * DISCLAIMER OF LIABILITY | |
32 | * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY | |
33 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
34 | * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND | |
35 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR | |
36 | * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE | |
37 | * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED | |
38 | * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES | |
39 | ||
40 | * You should have received a copy of the GNU General Public License | |
41 | * along with this program; if not, write to the Free Software | |
42 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, | |
43 | * USA. | |
44 | */ | |
45 | ||
f92363d1 SR |
46 | #include <linux/kernel.h> |
47 | #include <linux/module.h> | |
48 | #include <linux/errno.h> | |
49 | #include <linux/init.h> | |
50 | #include <linux/slab.h> | |
51 | #include <linux/types.h> | |
52 | #include <linux/pci.h> | |
53 | #include <linux/kdev_t.h> | |
54 | #include <linux/blkdev.h> | |
55 | #include <linux/delay.h> | |
56 | #include <linux/interrupt.h> | |
57 | #include <linux/dma-mapping.h> | |
58 | #include <linux/io.h> | |
59 | #include <linux/time.h> | |
23409bd4 | 60 | #include <linux/ktime.h> |
f92363d1 | 61 | #include <linux/kthread.h> |
016d5c35 | 62 | #include <asm/page.h> /* To get host page size per arch */ |
f92363d1 SR |
63 | #include <linux/aer.h> |
64 | ||
65 | ||
66 | #include "mpt3sas_base.h" | |
67 | ||
68 | static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS]; | |
69 | ||
70 | ||
71 | #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */ | |
72 | ||
73 | /* maximum controller queue depth */ | |
74 | #define MAX_HBA_QUEUE_DEPTH 30000 | |
75 | #define MAX_CHAIN_DEPTH 100000 | |
76 | static int max_queue_depth = -1; | |
77 | module_param(max_queue_depth, int, 0); | |
78 | MODULE_PARM_DESC(max_queue_depth, " max controller queue depth "); | |
79 | ||
80 | static int max_sgl_entries = -1; | |
81 | module_param(max_sgl_entries, int, 0); | |
82 | MODULE_PARM_DESC(max_sgl_entries, " max sg entries "); | |
83 | ||
84 | static int msix_disable = -1; | |
85 | module_param(msix_disable, int, 0); | |
86 | MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)"); | |
87 | ||
64038301 SPS |
88 | static int smp_affinity_enable = 1; |
89 | module_param(smp_affinity_enable, int, S_IRUGO); | |
23b389c2 | 90 | MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disable Default: enable(1)"); |
64038301 | 91 | |
fb77bb53 | 92 | static int max_msix_vectors = -1; |
9c500060 SR |
93 | module_param(max_msix_vectors, int, 0); |
94 | MODULE_PARM_DESC(max_msix_vectors, | |
fb77bb53 | 95 | " max msix vectors"); |
f92363d1 SR |
96 | |
97 | static int mpt3sas_fwfault_debug; | |
98 | MODULE_PARM_DESC(mpt3sas_fwfault_debug, | |
99 | " enable detection of firmware fault and halt firmware - (default=0)"); | |
100 | ||
9b05c91a | 101 | static int |
98c56ad3 | 102 | _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc); |
f92363d1 | 103 | |
d37306ca C |
104 | /** |
105 | * mpt3sas_base_check_cmd_timeout - Function | |
106 | * to check timeout and command termination due | |
107 | * to Host reset. | |
108 | * | |
109 | * @ioc: per adapter object. | |
110 | * @status: Status of issued command. | |
111 | * @mpi_request:mf request pointer. | |
112 | * @sz: size of buffer. | |
113 | * | |
114 | * @Returns - 1/0 Reset to be done or Not | |
115 | */ | |
116 | u8 | |
117 | mpt3sas_base_check_cmd_timeout(struct MPT3SAS_ADAPTER *ioc, | |
118 | u8 status, void *mpi_request, int sz) | |
119 | { | |
120 | u8 issue_reset = 0; | |
121 | ||
122 | if (!(status & MPT3_CMD_RESET)) | |
123 | issue_reset = 1; | |
124 | ||
125 | pr_err(MPT3SAS_FMT "Command %s\n", ioc->name, | |
126 | ((issue_reset == 0) ? "terminated due to Host Reset" : "Timeout")); | |
127 | _debug_dump_mf(mpi_request, sz); | |
128 | ||
129 | return issue_reset; | |
130 | } | |
131 | ||
f92363d1 SR |
132 | /** |
133 | * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug. | |
4beb4867 BVA |
134 | * @val: ? |
135 | * @kp: ? | |
f92363d1 | 136 | * |
4beb4867 | 137 | * Return: ? |
f92363d1 SR |
138 | */ |
139 | static int | |
e4dca7b7 | 140 | _scsih_set_fwfault_debug(const char *val, const struct kernel_param *kp) |
f92363d1 SR |
141 | { |
142 | int ret = param_set_int(val, kp); | |
143 | struct MPT3SAS_ADAPTER *ioc; | |
144 | ||
145 | if (ret) | |
146 | return ret; | |
147 | ||
08c4d550 | 148 | /* global ioc spinlock to protect controller list on list operations */ |
f92363d1 | 149 | pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug); |
08c4d550 | 150 | spin_lock(&gioc_lock); |
f92363d1 SR |
151 | list_for_each_entry(ioc, &mpt3sas_ioc_list, list) |
152 | ioc->fwfault_debug = mpt3sas_fwfault_debug; | |
08c4d550 | 153 | spin_unlock(&gioc_lock); |
f92363d1 SR |
154 | return 0; |
155 | } | |
156 | module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug, | |
157 | param_get_int, &mpt3sas_fwfault_debug, 0644); | |
158 | ||
b4472d71 SPS |
159 | /** |
160 | * _base_clone_reply_to_sys_mem - copies reply to reply free iomem | |
161 | * in BAR0 space. | |
162 | * | |
163 | * @ioc: per adapter object | |
164 | * @reply: reply message frame(lower 32bit addr) | |
165 | * @index: System request message index. | |
b4472d71 SPS |
166 | */ |
167 | static void | |
168 | _base_clone_reply_to_sys_mem(struct MPT3SAS_ADAPTER *ioc, u32 reply, | |
169 | u32 index) | |
170 | { | |
171 | /* | |
172 | * 256 is offset within sys register. | |
173 | * 256 offset MPI frame starts. Max MPI frame supported is 32. | |
174 | * 32 * 128 = 4K. From here, Clone of reply free for mcpu starts | |
175 | */ | |
176 | u16 cmd_credit = ioc->facts.RequestCredit + 1; | |
177 | void __iomem *reply_free_iomem = (void __iomem *)ioc->chip + | |
178 | MPI_FRAME_START_OFFSET + | |
179 | (cmd_credit * ioc->request_sz) + (index * sizeof(u32)); | |
180 | ||
181 | writel(reply, reply_free_iomem); | |
182 | } | |
183 | ||
e5747439 SPS |
184 | /** |
185 | * _base_clone_mpi_to_sys_mem - Writes/copies MPI frames | |
186 | * to system/BAR0 region. | |
187 | * | |
4beb4867 | 188 | * @dst_iomem: Pointer to the destination location in BAR0 space. |
e5747439 SPS |
189 | * @src: Pointer to the Source data. |
190 | * @size: Size of data to be copied. | |
191 | */ | |
192 | static void | |
193 | _base_clone_mpi_to_sys_mem(void *dst_iomem, void *src, u32 size) | |
194 | { | |
195 | int i; | |
196 | u32 *src_virt_mem = (u32 *)src; | |
197 | ||
198 | for (i = 0; i < size/4; i++) | |
199 | writel((u32)src_virt_mem[i], | |
200 | (void __iomem *)dst_iomem + (i * 4)); | |
201 | } | |
202 | ||
182ac784 SPS |
203 | /** |
204 | * _base_clone_to_sys_mem - Writes/copies data to system/BAR0 region | |
205 | * | |
206 | * @dst_iomem: Pointer to the destination location in BAR0 space. | |
207 | * @src: Pointer to the Source data. | |
208 | * @size: Size of data to be copied. | |
209 | */ | |
210 | static void | |
211 | _base_clone_to_sys_mem(void __iomem *dst_iomem, void *src, u32 size) | |
212 | { | |
213 | int i; | |
214 | u32 *src_virt_mem = (u32 *)(src); | |
215 | ||
216 | for (i = 0; i < size/4; i++) | |
217 | writel((u32)src_virt_mem[i], | |
218 | (void __iomem *)dst_iomem + (i * 4)); | |
219 | } | |
220 | ||
22ae5a3c SPS |
221 | /** |
222 | * _base_get_chain - Calculates and Returns virtual chain address | |
223 | * for the provided smid in BAR0 space. | |
224 | * | |
225 | * @ioc: per adapter object | |
226 | * @smid: system request message index | |
227 | * @sge_chain_count: Scatter gather chain count. | |
228 | * | |
4beb4867 | 229 | * Return: the chain address. |
22ae5a3c SPS |
230 | */ |
231 | static inline void __iomem* | |
232 | _base_get_chain(struct MPT3SAS_ADAPTER *ioc, u16 smid, | |
233 | u8 sge_chain_count) | |
234 | { | |
235 | void __iomem *base_chain, *chain_virt; | |
236 | u16 cmd_credit = ioc->facts.RequestCredit + 1; | |
237 | ||
238 | base_chain = (void __iomem *)ioc->chip + MPI_FRAME_START_OFFSET + | |
239 | (cmd_credit * ioc->request_sz) + | |
240 | REPLY_FREE_POOL_SIZE; | |
241 | chain_virt = base_chain + (smid * ioc->facts.MaxChainDepth * | |
242 | ioc->request_sz) + (sge_chain_count * ioc->request_sz); | |
243 | return chain_virt; | |
244 | } | |
245 | ||
246 | /** | |
247 | * _base_get_chain_phys - Calculates and Returns physical address | |
248 | * in BAR0 for scatter gather chains, for | |
249 | * the provided smid. | |
250 | * | |
251 | * @ioc: per adapter object | |
252 | * @smid: system request message index | |
253 | * @sge_chain_count: Scatter gather chain count. | |
254 | * | |
4beb4867 | 255 | * Return: Physical chain address. |
22ae5a3c | 256 | */ |
6f9e09fd | 257 | static inline phys_addr_t |
22ae5a3c SPS |
258 | _base_get_chain_phys(struct MPT3SAS_ADAPTER *ioc, u16 smid, |
259 | u8 sge_chain_count) | |
260 | { | |
6f9e09fd | 261 | phys_addr_t base_chain_phys, chain_phys; |
22ae5a3c SPS |
262 | u16 cmd_credit = ioc->facts.RequestCredit + 1; |
263 | ||
6f9e09fd | 264 | base_chain_phys = ioc->chip_phys + MPI_FRAME_START_OFFSET + |
22ae5a3c SPS |
265 | (cmd_credit * ioc->request_sz) + |
266 | REPLY_FREE_POOL_SIZE; | |
267 | chain_phys = base_chain_phys + (smid * ioc->facts.MaxChainDepth * | |
268 | ioc->request_sz) + (sge_chain_count * ioc->request_sz); | |
269 | return chain_phys; | |
270 | } | |
271 | ||
272 | /** | |
273 | * _base_get_buffer_bar0 - Calculates and Returns BAR0 mapped Host | |
274 | * buffer address for the provided smid. | |
275 | * (Each smid can have 64K starts from 17024) | |
276 | * | |
277 | * @ioc: per adapter object | |
278 | * @smid: system request message index | |
279 | * | |
4beb4867 | 280 | * Return: Pointer to buffer location in BAR0. |
22ae5a3c SPS |
281 | */ |
282 | ||
283 | static void __iomem * | |
284 | _base_get_buffer_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
285 | { | |
286 | u16 cmd_credit = ioc->facts.RequestCredit + 1; | |
287 | // Added extra 1 to reach end of chain. | |
288 | void __iomem *chain_end = _base_get_chain(ioc, | |
289 | cmd_credit + 1, | |
290 | ioc->facts.MaxChainDepth); | |
291 | return chain_end + (smid * 64 * 1024); | |
292 | } | |
293 | ||
294 | /** | |
295 | * _base_get_buffer_phys_bar0 - Calculates and Returns BAR0 mapped | |
296 | * Host buffer Physical address for the provided smid. | |
297 | * (Each smid can have 64K starts from 17024) | |
298 | * | |
299 | * @ioc: per adapter object | |
300 | * @smid: system request message index | |
301 | * | |
4beb4867 | 302 | * Return: Pointer to buffer location in BAR0. |
22ae5a3c | 303 | */ |
6f9e09fd | 304 | static phys_addr_t |
22ae5a3c SPS |
305 | _base_get_buffer_phys_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid) |
306 | { | |
307 | u16 cmd_credit = ioc->facts.RequestCredit + 1; | |
6f9e09fd | 308 | phys_addr_t chain_end_phys = _base_get_chain_phys(ioc, |
22ae5a3c SPS |
309 | cmd_credit + 1, |
310 | ioc->facts.MaxChainDepth); | |
311 | return chain_end_phys + (smid * 64 * 1024); | |
312 | } | |
313 | ||
182ac784 SPS |
314 | /** |
315 | * _base_get_chain_buffer_dma_to_chain_buffer - Iterates chain | |
316 | * lookup list and Provides chain_buffer | |
317 | * address for the matching dma address. | |
318 | * (Each smid can have 64K starts from 17024) | |
319 | * | |
320 | * @ioc: per adapter object | |
321 | * @chain_buffer_dma: Chain buffer dma address. | |
322 | * | |
4beb4867 | 323 | * Return: Pointer to chain buffer. Or Null on Failure. |
182ac784 SPS |
324 | */ |
325 | static void * | |
326 | _base_get_chain_buffer_dma_to_chain_buffer(struct MPT3SAS_ADAPTER *ioc, | |
327 | dma_addr_t chain_buffer_dma) | |
328 | { | |
93204b78 C |
329 | u16 index, j; |
330 | struct chain_tracker *ct; | |
331 | ||
332 | for (index = 0; index < ioc->scsiio_depth; index++) { | |
333 | for (j = 0; j < ioc->chains_needed_per_io; j++) { | |
334 | ct = &ioc->chain_lookup[index].chains_per_smid[j]; | |
335 | if (ct && ct->chain_buffer_dma == chain_buffer_dma) | |
336 | return ct->chain_buffer; | |
337 | } | |
182ac784 SPS |
338 | } |
339 | pr_info(MPT3SAS_FMT | |
340 | "Provided chain_buffer_dma address is not in the lookup list\n", | |
341 | ioc->name); | |
342 | return NULL; | |
343 | } | |
344 | ||
345 | /** | |
346 | * _clone_sg_entries - MPI EP's scsiio and config requests | |
347 | * are handled here. Base function for | |
348 | * double buffering, before submitting | |
349 | * the requests. | |
350 | * | |
351 | * @ioc: per adapter object. | |
352 | * @mpi_request: mf request pointer. | |
353 | * @smid: system request message index. | |
182ac784 SPS |
354 | */ |
355 | static void _clone_sg_entries(struct MPT3SAS_ADAPTER *ioc, | |
356 | void *mpi_request, u16 smid) | |
357 | { | |
358 | Mpi2SGESimple32_t *sgel, *sgel_next; | |
359 | u32 sgl_flags, sge_chain_count = 0; | |
360 | bool is_write = 0; | |
361 | u16 i = 0; | |
362 | void __iomem *buffer_iomem; | |
6f9e09fd | 363 | phys_addr_t buffer_iomem_phys; |
182ac784 | 364 | void __iomem *buff_ptr; |
6f9e09fd | 365 | phys_addr_t buff_ptr_phys; |
182ac784 | 366 | void __iomem *dst_chain_addr[MCPU_MAX_CHAINS_PER_IO]; |
6f9e09fd AB |
367 | void *src_chain_addr[MCPU_MAX_CHAINS_PER_IO]; |
368 | phys_addr_t dst_addr_phys; | |
182ac784 SPS |
369 | MPI2RequestHeader_t *request_hdr; |
370 | struct scsi_cmnd *scmd; | |
371 | struct scatterlist *sg_scmd = NULL; | |
372 | int is_scsiio_req = 0; | |
373 | ||
374 | request_hdr = (MPI2RequestHeader_t *) mpi_request; | |
375 | ||
376 | if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST) { | |
377 | Mpi25SCSIIORequest_t *scsiio_request = | |
378 | (Mpi25SCSIIORequest_t *)mpi_request; | |
379 | sgel = (Mpi2SGESimple32_t *) &scsiio_request->SGL; | |
380 | is_scsiio_req = 1; | |
381 | } else if (request_hdr->Function == MPI2_FUNCTION_CONFIG) { | |
382 | Mpi2ConfigRequest_t *config_req = | |
383 | (Mpi2ConfigRequest_t *)mpi_request; | |
384 | sgel = (Mpi2SGESimple32_t *) &config_req->PageBufferSGE; | |
385 | } else | |
386 | return; | |
387 | ||
388 | /* From smid we can get scsi_cmd, once we have sg_scmd, | |
389 | * we just need to get sg_virt and sg_next to get virual | |
390 | * address associated with sgel->Address. | |
391 | */ | |
392 | ||
393 | if (is_scsiio_req) { | |
394 | /* Get scsi_cmd using smid */ | |
395 | scmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid); | |
396 | if (scmd == NULL) { | |
397 | pr_err(MPT3SAS_FMT "scmd is NULL\n", ioc->name); | |
398 | return; | |
399 | } | |
400 | ||
401 | /* Get sg_scmd from scmd provided */ | |
402 | sg_scmd = scsi_sglist(scmd); | |
403 | } | |
404 | ||
405 | /* | |
406 | * 0 - 255 System register | |
407 | * 256 - 4352 MPI Frame. (This is based on maxCredit 32) | |
408 | * 4352 - 4864 Reply_free pool (512 byte is reserved | |
409 | * considering maxCredit 32. Reply need extra | |
410 | * room, for mCPU case kept four times of | |
411 | * maxCredit). | |
412 | * 4864 - 17152 SGE chain element. (32cmd * 3 chain of | |
413 | * 128 byte size = 12288) | |
414 | * 17152 - x Host buffer mapped with smid. | |
415 | * (Each smid can have 64K Max IO.) | |
416 | * BAR0+Last 1K MSIX Addr and Data | |
417 | * Total size in use 2113664 bytes of 4MB BAR0 | |
418 | */ | |
419 | ||
420 | buffer_iomem = _base_get_buffer_bar0(ioc, smid); | |
421 | buffer_iomem_phys = _base_get_buffer_phys_bar0(ioc, smid); | |
422 | ||
423 | buff_ptr = buffer_iomem; | |
424 | buff_ptr_phys = buffer_iomem_phys; | |
6f9e09fd | 425 | WARN_ON(buff_ptr_phys > U32_MAX); |
182ac784 | 426 | |
cf6bf971 | 427 | if (le32_to_cpu(sgel->FlagsLength) & |
182ac784 SPS |
428 | (MPI2_SGE_FLAGS_HOST_TO_IOC << MPI2_SGE_FLAGS_SHIFT)) |
429 | is_write = 1; | |
430 | ||
431 | for (i = 0; i < MPT_MIN_PHYS_SEGMENTS + ioc->facts.MaxChainDepth; i++) { | |
432 | ||
cf6bf971 C |
433 | sgl_flags = |
434 | (le32_to_cpu(sgel->FlagsLength) >> MPI2_SGE_FLAGS_SHIFT); | |
182ac784 SPS |
435 | |
436 | switch (sgl_flags & MPI2_SGE_FLAGS_ELEMENT_MASK) { | |
437 | case MPI2_SGE_FLAGS_CHAIN_ELEMENT: | |
438 | /* | |
439 | * Helper function which on passing | |
440 | * chain_buffer_dma returns chain_buffer. Get | |
441 | * the virtual address for sgel->Address | |
442 | */ | |
443 | sgel_next = | |
444 | _base_get_chain_buffer_dma_to_chain_buffer(ioc, | |
cf6bf971 | 445 | le32_to_cpu(sgel->Address)); |
182ac784 SPS |
446 | if (sgel_next == NULL) |
447 | return; | |
448 | /* | |
449 | * This is coping 128 byte chain | |
450 | * frame (not a host buffer) | |
451 | */ | |
452 | dst_chain_addr[sge_chain_count] = | |
453 | _base_get_chain(ioc, | |
454 | smid, sge_chain_count); | |
455 | src_chain_addr[sge_chain_count] = | |
456 | (void *) sgel_next; | |
6f9e09fd | 457 | dst_addr_phys = _base_get_chain_phys(ioc, |
182ac784 | 458 | smid, sge_chain_count); |
6f9e09fd | 459 | WARN_ON(dst_addr_phys > U32_MAX); |
cf6bf971 C |
460 | sgel->Address = |
461 | cpu_to_le32(lower_32_bits(dst_addr_phys)); | |
182ac784 SPS |
462 | sgel = sgel_next; |
463 | sge_chain_count++; | |
464 | break; | |
465 | case MPI2_SGE_FLAGS_SIMPLE_ELEMENT: | |
466 | if (is_write) { | |
467 | if (is_scsiio_req) { | |
468 | _base_clone_to_sys_mem(buff_ptr, | |
469 | sg_virt(sg_scmd), | |
cf6bf971 C |
470 | (le32_to_cpu(sgel->FlagsLength) & |
471 | 0x00ffffff)); | |
6f9e09fd AB |
472 | /* |
473 | * FIXME: this relies on a a zero | |
474 | * PCI mem_offset. | |
475 | */ | |
cf6bf971 C |
476 | sgel->Address = |
477 | cpu_to_le32((u32)buff_ptr_phys); | |
182ac784 SPS |
478 | } else { |
479 | _base_clone_to_sys_mem(buff_ptr, | |
480 | ioc->config_vaddr, | |
cf6bf971 C |
481 | (le32_to_cpu(sgel->FlagsLength) & |
482 | 0x00ffffff)); | |
483 | sgel->Address = | |
484 | cpu_to_le32((u32)buff_ptr_phys); | |
182ac784 SPS |
485 | } |
486 | } | |
cf6bf971 C |
487 | buff_ptr += (le32_to_cpu(sgel->FlagsLength) & |
488 | 0x00ffffff); | |
489 | buff_ptr_phys += (le32_to_cpu(sgel->FlagsLength) & | |
490 | 0x00ffffff); | |
491 | if ((le32_to_cpu(sgel->FlagsLength) & | |
182ac784 SPS |
492 | (MPI2_SGE_FLAGS_END_OF_BUFFER |
493 | << MPI2_SGE_FLAGS_SHIFT))) | |
494 | goto eob_clone_chain; | |
495 | else { | |
496 | /* | |
497 | * Every single element in MPT will have | |
498 | * associated sg_next. Better to sanity that | |
499 | * sg_next is not NULL, but it will be a bug | |
500 | * if it is null. | |
501 | */ | |
502 | if (is_scsiio_req) { | |
503 | sg_scmd = sg_next(sg_scmd); | |
504 | if (sg_scmd) | |
505 | sgel++; | |
506 | else | |
507 | goto eob_clone_chain; | |
508 | } | |
509 | } | |
510 | break; | |
511 | } | |
512 | } | |
513 | ||
514 | eob_clone_chain: | |
515 | for (i = 0; i < sge_chain_count; i++) { | |
516 | if (is_scsiio_req) | |
517 | _base_clone_to_sys_mem(dst_chain_addr[i], | |
518 | src_chain_addr[i], ioc->request_sz); | |
519 | } | |
520 | } | |
521 | ||
f92363d1 SR |
522 | /** |
523 | * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc | |
524 | * @arg: input argument, used to derive ioc | |
525 | * | |
4beb4867 BVA |
526 | * Return: |
527 | * 0 if controller is removed from pci subsystem. | |
528 | * -1 for other case. | |
f92363d1 SR |
529 | */ |
530 | static int mpt3sas_remove_dead_ioc_func(void *arg) | |
531 | { | |
532 | struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg; | |
533 | struct pci_dev *pdev; | |
534 | ||
535 | if ((ioc == NULL)) | |
536 | return -1; | |
537 | ||
538 | pdev = ioc->pdev; | |
539 | if ((pdev == NULL)) | |
540 | return -1; | |
64cdb418 | 541 | pci_stop_and_remove_bus_device_locked(pdev); |
f92363d1 SR |
542 | return 0; |
543 | } | |
544 | ||
545 | /** | |
546 | * _base_fault_reset_work - workq handling ioc fault conditions | |
547 | * @work: input argument, used to derive ioc | |
f92363d1 | 548 | * |
4beb4867 | 549 | * Context: sleep. |
f92363d1 SR |
550 | */ |
551 | static void | |
552 | _base_fault_reset_work(struct work_struct *work) | |
553 | { | |
554 | struct MPT3SAS_ADAPTER *ioc = | |
555 | container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work); | |
556 | unsigned long flags; | |
557 | u32 doorbell; | |
558 | int rc; | |
559 | struct task_struct *p; | |
560 | ||
561 | ||
562 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
16e179bd | 563 | if (ioc->shost_recovery || ioc->pci_error_recovery) |
f92363d1 SR |
564 | goto rearm_timer; |
565 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
566 | ||
567 | doorbell = mpt3sas_base_get_iocstate(ioc, 0); | |
568 | if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) { | |
569 | pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n", | |
570 | ioc->name); | |
571 | ||
16e179bd SR |
572 | /* It may be possible that EEH recovery can resolve some of |
573 | * pci bus failure issues rather removing the dead ioc function | |
574 | * by considering controller is in a non-operational state. So | |
575 | * here priority is given to the EEH recovery. If it doesn't | |
576 | * not resolve this issue, mpt3sas driver will consider this | |
577 | * controller to non-operational state and remove the dead ioc | |
578 | * function. | |
579 | */ | |
580 | if (ioc->non_operational_loop++ < 5) { | |
581 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, | |
582 | flags); | |
583 | goto rearm_timer; | |
584 | } | |
585 | ||
f92363d1 SR |
586 | /* |
587 | * Call _scsih_flush_pending_cmds callback so that we flush all | |
588 | * pending commands back to OS. This call is required to aovid | |
589 | * deadlock at block layer. Dead IOC will fail to do diag reset, | |
590 | * and this call is safe since dead ioc will never return any | |
591 | * command back from HW. | |
592 | */ | |
593 | ioc->schedule_dead_ioc_flush_running_cmds(ioc); | |
594 | /* | |
595 | * Set remove_host flag early since kernel thread will | |
596 | * take some time to execute. | |
597 | */ | |
598 | ioc->remove_host = 1; | |
599 | /*Remove the Dead Host */ | |
600 | p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc, | |
c84b06a4 | 601 | "%s_dead_ioc_%d", ioc->driver_name, ioc->id); |
f92363d1 SR |
602 | if (IS_ERR(p)) |
603 | pr_err(MPT3SAS_FMT | |
604 | "%s: Running mpt3sas_dead_ioc thread failed !!!!\n", | |
605 | ioc->name, __func__); | |
606 | else | |
607 | pr_err(MPT3SAS_FMT | |
608 | "%s: Running mpt3sas_dead_ioc thread success !!!!\n", | |
609 | ioc->name, __func__); | |
610 | return; /* don't rearm timer */ | |
611 | } | |
612 | ||
16e179bd SR |
613 | ioc->non_operational_loop = 0; |
614 | ||
f92363d1 | 615 | if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) { |
98c56ad3 | 616 | rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); |
f92363d1 SR |
617 | pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name, |
618 | __func__, (rc == 0) ? "success" : "failed"); | |
619 | doorbell = mpt3sas_base_get_iocstate(ioc, 0); | |
620 | if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) | |
621 | mpt3sas_base_fault_info(ioc, doorbell & | |
622 | MPI2_DOORBELL_DATA_MASK); | |
623 | if (rc && (doorbell & MPI2_IOC_STATE_MASK) != | |
624 | MPI2_IOC_STATE_OPERATIONAL) | |
625 | return; /* don't rearm timer */ | |
626 | } | |
627 | ||
628 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
629 | rearm_timer: | |
630 | if (ioc->fault_reset_work_q) | |
631 | queue_delayed_work(ioc->fault_reset_work_q, | |
632 | &ioc->fault_reset_work, | |
633 | msecs_to_jiffies(FAULT_POLLING_INTERVAL)); | |
634 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
635 | } | |
636 | ||
637 | /** | |
638 | * mpt3sas_base_start_watchdog - start the fault_reset_work_q | |
639 | * @ioc: per adapter object | |
f92363d1 | 640 | * |
4beb4867 | 641 | * Context: sleep. |
f92363d1 SR |
642 | */ |
643 | void | |
644 | mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc) | |
645 | { | |
646 | unsigned long flags; | |
647 | ||
648 | if (ioc->fault_reset_work_q) | |
649 | return; | |
650 | ||
651 | /* initialize fault polling */ | |
652 | ||
653 | INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work); | |
654 | snprintf(ioc->fault_reset_work_q_name, | |
c84b06a4 SR |
655 | sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status", |
656 | ioc->driver_name, ioc->id); | |
f92363d1 SR |
657 | ioc->fault_reset_work_q = |
658 | create_singlethread_workqueue(ioc->fault_reset_work_q_name); | |
659 | if (!ioc->fault_reset_work_q) { | |
660 | pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n", | |
661 | ioc->name, __func__, __LINE__); | |
199fd79a | 662 | return; |
f92363d1 SR |
663 | } |
664 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
665 | if (ioc->fault_reset_work_q) | |
666 | queue_delayed_work(ioc->fault_reset_work_q, | |
667 | &ioc->fault_reset_work, | |
668 | msecs_to_jiffies(FAULT_POLLING_INTERVAL)); | |
669 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
670 | } | |
671 | ||
672 | /** | |
673 | * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q | |
674 | * @ioc: per adapter object | |
f92363d1 | 675 | * |
4beb4867 | 676 | * Context: sleep. |
f92363d1 SR |
677 | */ |
678 | void | |
679 | mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc) | |
680 | { | |
681 | unsigned long flags; | |
682 | struct workqueue_struct *wq; | |
683 | ||
684 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
685 | wq = ioc->fault_reset_work_q; | |
686 | ioc->fault_reset_work_q = NULL; | |
687 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
688 | if (wq) { | |
4dc06fd8 | 689 | if (!cancel_delayed_work_sync(&ioc->fault_reset_work)) |
f92363d1 SR |
690 | flush_workqueue(wq); |
691 | destroy_workqueue(wq); | |
692 | } | |
693 | } | |
694 | ||
695 | /** | |
696 | * mpt3sas_base_fault_info - verbose translation of firmware FAULT code | |
697 | * @ioc: per adapter object | |
698 | * @fault_code: fault code | |
f92363d1 SR |
699 | */ |
700 | void | |
701 | mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code) | |
702 | { | |
703 | pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n", | |
704 | ioc->name, fault_code); | |
705 | } | |
706 | ||
707 | /** | |
708 | * mpt3sas_halt_firmware - halt's mpt controller firmware | |
709 | * @ioc: per adapter object | |
710 | * | |
711 | * For debugging timeout related issues. Writing 0xCOFFEE00 | |
712 | * to the doorbell register will halt controller firmware. With | |
713 | * the purpose to stop both driver and firmware, the enduser can | |
714 | * obtain a ring buffer from controller UART. | |
715 | */ | |
716 | void | |
717 | mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc) | |
718 | { | |
719 | u32 doorbell; | |
720 | ||
721 | if (!ioc->fwfault_debug) | |
722 | return; | |
723 | ||
724 | dump_stack(); | |
725 | ||
726 | doorbell = readl(&ioc->chip->Doorbell); | |
727 | if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) | |
728 | mpt3sas_base_fault_info(ioc , doorbell); | |
729 | else { | |
730 | writel(0xC0FFEE00, &ioc->chip->Doorbell); | |
731 | pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n", | |
732 | ioc->name); | |
733 | } | |
734 | ||
735 | if (ioc->fwfault_debug == 2) | |
736 | for (;;) | |
737 | ; | |
738 | else | |
739 | panic("panic in %s\n", __func__); | |
740 | } | |
741 | ||
f92363d1 SR |
742 | /** |
743 | * _base_sas_ioc_info - verbose translation of the ioc status | |
744 | * @ioc: per adapter object | |
745 | * @mpi_reply: reply mf payload returned from firmware | |
746 | * @request_hdr: request mf | |
f92363d1 SR |
747 | */ |
748 | static void | |
749 | _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply, | |
750 | MPI2RequestHeader_t *request_hdr) | |
751 | { | |
752 | u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & | |
753 | MPI2_IOCSTATUS_MASK; | |
754 | char *desc = NULL; | |
755 | u16 frame_sz; | |
756 | char *func_str = NULL; | |
757 | ||
758 | /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */ | |
759 | if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST || | |
760 | request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH || | |
761 | request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION) | |
762 | return; | |
763 | ||
764 | if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE) | |
765 | return; | |
766 | ||
767 | switch (ioc_status) { | |
768 | ||
769 | /**************************************************************************** | |
770 | * Common IOCStatus values for all replies | |
771 | ****************************************************************************/ | |
772 | ||
773 | case MPI2_IOCSTATUS_INVALID_FUNCTION: | |
774 | desc = "invalid function"; | |
775 | break; | |
776 | case MPI2_IOCSTATUS_BUSY: | |
777 | desc = "busy"; | |
778 | break; | |
779 | case MPI2_IOCSTATUS_INVALID_SGL: | |
780 | desc = "invalid sgl"; | |
781 | break; | |
782 | case MPI2_IOCSTATUS_INTERNAL_ERROR: | |
783 | desc = "internal error"; | |
784 | break; | |
785 | case MPI2_IOCSTATUS_INVALID_VPID: | |
786 | desc = "invalid vpid"; | |
787 | break; | |
788 | case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: | |
789 | desc = "insufficient resources"; | |
790 | break; | |
b130b0d5 SS |
791 | case MPI2_IOCSTATUS_INSUFFICIENT_POWER: |
792 | desc = "insufficient power"; | |
793 | break; | |
f92363d1 SR |
794 | case MPI2_IOCSTATUS_INVALID_FIELD: |
795 | desc = "invalid field"; | |
796 | break; | |
797 | case MPI2_IOCSTATUS_INVALID_STATE: | |
798 | desc = "invalid state"; | |
799 | break; | |
800 | case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED: | |
801 | desc = "op state not supported"; | |
802 | break; | |
803 | ||
804 | /**************************************************************************** | |
805 | * Config IOCStatus values | |
806 | ****************************************************************************/ | |
807 | ||
808 | case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION: | |
809 | desc = "config invalid action"; | |
810 | break; | |
811 | case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE: | |
812 | desc = "config invalid type"; | |
813 | break; | |
814 | case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE: | |
815 | desc = "config invalid page"; | |
816 | break; | |
817 | case MPI2_IOCSTATUS_CONFIG_INVALID_DATA: | |
818 | desc = "config invalid data"; | |
819 | break; | |
820 | case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS: | |
821 | desc = "config no defaults"; | |
822 | break; | |
823 | case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT: | |
824 | desc = "config cant commit"; | |
825 | break; | |
826 | ||
827 | /**************************************************************************** | |
828 | * SCSI IO Reply | |
829 | ****************************************************************************/ | |
830 | ||
831 | case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR: | |
832 | case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE: | |
833 | case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: | |
834 | case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: | |
835 | case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: | |
836 | case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: | |
837 | case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: | |
838 | case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: | |
839 | case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: | |
840 | case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED: | |
841 | case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: | |
842 | case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: | |
843 | break; | |
844 | ||
845 | /**************************************************************************** | |
846 | * For use by SCSI Initiator and SCSI Target end-to-end data protection | |
847 | ****************************************************************************/ | |
848 | ||
849 | case MPI2_IOCSTATUS_EEDP_GUARD_ERROR: | |
850 | desc = "eedp guard error"; | |
851 | break; | |
852 | case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR: | |
853 | desc = "eedp ref tag error"; | |
854 | break; | |
855 | case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR: | |
856 | desc = "eedp app tag error"; | |
857 | break; | |
858 | ||
859 | /**************************************************************************** | |
860 | * SCSI Target values | |
861 | ****************************************************************************/ | |
862 | ||
863 | case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX: | |
864 | desc = "target invalid io index"; | |
865 | break; | |
866 | case MPI2_IOCSTATUS_TARGET_ABORTED: | |
867 | desc = "target aborted"; | |
868 | break; | |
869 | case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: | |
870 | desc = "target no conn retryable"; | |
871 | break; | |
872 | case MPI2_IOCSTATUS_TARGET_NO_CONNECTION: | |
873 | desc = "target no connection"; | |
874 | break; | |
875 | case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: | |
876 | desc = "target xfer count mismatch"; | |
877 | break; | |
878 | case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: | |
879 | desc = "target data offset error"; | |
880 | break; | |
881 | case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: | |
882 | desc = "target too much write data"; | |
883 | break; | |
884 | case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT: | |
885 | desc = "target iu too short"; | |
886 | break; | |
887 | case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: | |
888 | desc = "target ack nak timeout"; | |
889 | break; | |
890 | case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED: | |
891 | desc = "target nak received"; | |
892 | break; | |
893 | ||
894 | /**************************************************************************** | |
895 | * Serial Attached SCSI values | |
896 | ****************************************************************************/ | |
897 | ||
898 | case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: | |
899 | desc = "smp request failed"; | |
900 | break; | |
901 | case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: | |
902 | desc = "smp data overrun"; | |
903 | break; | |
904 | ||
905 | /**************************************************************************** | |
906 | * Diagnostic Buffer Post / Diagnostic Release values | |
907 | ****************************************************************************/ | |
908 | ||
909 | case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED: | |
910 | desc = "diagnostic released"; | |
911 | break; | |
912 | default: | |
913 | break; | |
914 | } | |
915 | ||
916 | if (!desc) | |
917 | return; | |
918 | ||
919 | switch (request_hdr->Function) { | |
920 | case MPI2_FUNCTION_CONFIG: | |
921 | frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size; | |
922 | func_str = "config_page"; | |
923 | break; | |
924 | case MPI2_FUNCTION_SCSI_TASK_MGMT: | |
925 | frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t); | |
926 | func_str = "task_mgmt"; | |
927 | break; | |
928 | case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL: | |
929 | frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t); | |
930 | func_str = "sas_iounit_ctl"; | |
931 | break; | |
932 | case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR: | |
933 | frame_sz = sizeof(Mpi2SepRequest_t); | |
934 | func_str = "enclosure"; | |
935 | break; | |
936 | case MPI2_FUNCTION_IOC_INIT: | |
937 | frame_sz = sizeof(Mpi2IOCInitRequest_t); | |
938 | func_str = "ioc_init"; | |
939 | break; | |
940 | case MPI2_FUNCTION_PORT_ENABLE: | |
941 | frame_sz = sizeof(Mpi2PortEnableRequest_t); | |
942 | func_str = "port_enable"; | |
943 | break; | |
944 | case MPI2_FUNCTION_SMP_PASSTHROUGH: | |
945 | frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size; | |
946 | func_str = "smp_passthru"; | |
947 | break; | |
aff39e61 SPS |
948 | case MPI2_FUNCTION_NVME_ENCAPSULATED: |
949 | frame_sz = sizeof(Mpi26NVMeEncapsulatedRequest_t) + | |
950 | ioc->sge_size; | |
951 | func_str = "nvme_encapsulated"; | |
952 | break; | |
f92363d1 SR |
953 | default: |
954 | frame_sz = 32; | |
955 | func_str = "unknown"; | |
956 | break; | |
957 | } | |
958 | ||
959 | pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n", | |
960 | ioc->name, desc, ioc_status, request_hdr, func_str); | |
961 | ||
962 | _debug_dump_mf(request_hdr, frame_sz/4); | |
963 | } | |
964 | ||
965 | /** | |
966 | * _base_display_event_data - verbose translation of firmware asyn events | |
967 | * @ioc: per adapter object | |
968 | * @mpi_reply: reply mf payload returned from firmware | |
f92363d1 SR |
969 | */ |
970 | static void | |
971 | _base_display_event_data(struct MPT3SAS_ADAPTER *ioc, | |
972 | Mpi2EventNotificationReply_t *mpi_reply) | |
973 | { | |
974 | char *desc = NULL; | |
975 | u16 event; | |
976 | ||
977 | if (!(ioc->logging_level & MPT_DEBUG_EVENTS)) | |
978 | return; | |
979 | ||
980 | event = le16_to_cpu(mpi_reply->Event); | |
981 | ||
982 | switch (event) { | |
983 | case MPI2_EVENT_LOG_DATA: | |
984 | desc = "Log Data"; | |
985 | break; | |
986 | case MPI2_EVENT_STATE_CHANGE: | |
987 | desc = "Status Change"; | |
988 | break; | |
989 | case MPI2_EVENT_HARD_RESET_RECEIVED: | |
990 | desc = "Hard Reset Received"; | |
991 | break; | |
992 | case MPI2_EVENT_EVENT_CHANGE: | |
993 | desc = "Event Change"; | |
994 | break; | |
995 | case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: | |
996 | desc = "Device Status Change"; | |
997 | break; | |
998 | case MPI2_EVENT_IR_OPERATION_STATUS: | |
7786ab6a SR |
999 | if (!ioc->hide_ir_msg) |
1000 | desc = "IR Operation Status"; | |
f92363d1 SR |
1001 | break; |
1002 | case MPI2_EVENT_SAS_DISCOVERY: | |
1003 | { | |
1004 | Mpi2EventDataSasDiscovery_t *event_data = | |
1005 | (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData; | |
1006 | pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name, | |
1007 | (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ? | |
1008 | "start" : "stop"); | |
1009 | if (event_data->DiscoveryStatus) | |
bbaf61e2 | 1010 | pr_cont(" discovery_status(0x%08x)", |
f92363d1 | 1011 | le32_to_cpu(event_data->DiscoveryStatus)); |
bbaf61e2 | 1012 | pr_cont("\n"); |
f92363d1 SR |
1013 | return; |
1014 | } | |
1015 | case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: | |
1016 | desc = "SAS Broadcast Primitive"; | |
1017 | break; | |
1018 | case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: | |
1019 | desc = "SAS Init Device Status Change"; | |
1020 | break; | |
1021 | case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW: | |
1022 | desc = "SAS Init Table Overflow"; | |
1023 | break; | |
1024 | case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: | |
1025 | desc = "SAS Topology Change List"; | |
1026 | break; | |
1027 | case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: | |
1028 | desc = "SAS Enclosure Device Status Change"; | |
1029 | break; | |
1030 | case MPI2_EVENT_IR_VOLUME: | |
7786ab6a SR |
1031 | if (!ioc->hide_ir_msg) |
1032 | desc = "IR Volume"; | |
f92363d1 SR |
1033 | break; |
1034 | case MPI2_EVENT_IR_PHYSICAL_DISK: | |
7786ab6a SR |
1035 | if (!ioc->hide_ir_msg) |
1036 | desc = "IR Physical Disk"; | |
f92363d1 SR |
1037 | break; |
1038 | case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: | |
7786ab6a SR |
1039 | if (!ioc->hide_ir_msg) |
1040 | desc = "IR Configuration Change List"; | |
f92363d1 SR |
1041 | break; |
1042 | case MPI2_EVENT_LOG_ENTRY_ADDED: | |
7786ab6a SR |
1043 | if (!ioc->hide_ir_msg) |
1044 | desc = "Log Entry Added"; | |
f92363d1 | 1045 | break; |
2d8ce8c9 SR |
1046 | case MPI2_EVENT_TEMP_THRESHOLD: |
1047 | desc = "Temperature Threshold"; | |
1048 | break; | |
a470a51c | 1049 | case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION: |
b99b1993 | 1050 | desc = "Cable Event"; |
a470a51c | 1051 | break; |
95540b8e C |
1052 | case MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR: |
1053 | desc = "SAS Device Discovery Error"; | |
1054 | break; | |
4318c734 SPS |
1055 | case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE: |
1056 | desc = "PCIE Device Status Change"; | |
1057 | break; | |
1058 | case MPI2_EVENT_PCIE_ENUMERATION: | |
1059 | { | |
1060 | Mpi26EventDataPCIeEnumeration_t *event_data = | |
1061 | (Mpi26EventDataPCIeEnumeration_t *)mpi_reply->EventData; | |
1062 | pr_info(MPT3SAS_FMT "PCIE Enumeration: (%s)", ioc->name, | |
1063 | (event_data->ReasonCode == | |
1064 | MPI26_EVENT_PCIE_ENUM_RC_STARTED) ? | |
1065 | "start" : "stop"); | |
1066 | if (event_data->EnumerationStatus) | |
1067 | pr_info("enumeration_status(0x%08x)", | |
1068 | le32_to_cpu(event_data->EnumerationStatus)); | |
1069 | pr_info("\n"); | |
1070 | return; | |
1071 | } | |
1072 | case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: | |
1073 | desc = "PCIE Topology Change List"; | |
1074 | break; | |
f92363d1 SR |
1075 | } |
1076 | ||
1077 | if (!desc) | |
1078 | return; | |
1079 | ||
1080 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc); | |
1081 | } | |
f92363d1 SR |
1082 | |
1083 | /** | |
1084 | * _base_sas_log_info - verbose translation of firmware log info | |
1085 | * @ioc: per adapter object | |
1086 | * @log_info: log info | |
f92363d1 SR |
1087 | */ |
1088 | static void | |
1089 | _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info) | |
1090 | { | |
1091 | union loginfo_type { | |
1092 | u32 loginfo; | |
1093 | struct { | |
1094 | u32 subcode:16; | |
1095 | u32 code:8; | |
1096 | u32 originator:4; | |
1097 | u32 bus_type:4; | |
1098 | } dw; | |
1099 | }; | |
1100 | union loginfo_type sas_loginfo; | |
1101 | char *originator_str = NULL; | |
1102 | ||
1103 | sas_loginfo.loginfo = log_info; | |
1104 | if (sas_loginfo.dw.bus_type != 3 /*SAS*/) | |
1105 | return; | |
1106 | ||
1107 | /* each nexus loss loginfo */ | |
1108 | if (log_info == 0x31170000) | |
1109 | return; | |
1110 | ||
1111 | /* eat the loginfos associated with task aborts */ | |
1112 | if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info == | |
1113 | 0x31140000 || log_info == 0x31130000)) | |
1114 | return; | |
1115 | ||
1116 | switch (sas_loginfo.dw.originator) { | |
1117 | case 0: | |
1118 | originator_str = "IOP"; | |
1119 | break; | |
1120 | case 1: | |
1121 | originator_str = "PL"; | |
1122 | break; | |
1123 | case 2: | |
7786ab6a SR |
1124 | if (!ioc->hide_ir_msg) |
1125 | originator_str = "IR"; | |
1126 | else | |
1127 | originator_str = "WarpDrive"; | |
f92363d1 SR |
1128 | break; |
1129 | } | |
1130 | ||
1131 | pr_warn(MPT3SAS_FMT | |
1132 | "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n", | |
1133 | ioc->name, log_info, | |
1134 | originator_str, sas_loginfo.dw.code, | |
1135 | sas_loginfo.dw.subcode); | |
1136 | } | |
1137 | ||
1138 | /** | |
1139 | * _base_display_reply_info - | |
1140 | * @ioc: per adapter object | |
1141 | * @smid: system request message index | |
1142 | * @msix_index: MSIX table index supplied by the OS | |
1143 | * @reply: reply message frame(lower 32bit addr) | |
f92363d1 SR |
1144 | */ |
1145 | static void | |
1146 | _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, | |
1147 | u32 reply) | |
1148 | { | |
1149 | MPI2DefaultReply_t *mpi_reply; | |
1150 | u16 ioc_status; | |
1151 | u32 loginfo = 0; | |
1152 | ||
1153 | mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); | |
1154 | if (unlikely(!mpi_reply)) { | |
1155 | pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n", | |
1156 | ioc->name, __FILE__, __LINE__, __func__); | |
1157 | return; | |
1158 | } | |
1159 | ioc_status = le16_to_cpu(mpi_reply->IOCStatus); | |
af009411 | 1160 | |
f92363d1 SR |
1161 | if ((ioc_status & MPI2_IOCSTATUS_MASK) && |
1162 | (ioc->logging_level & MPT_DEBUG_REPLY)) { | |
1163 | _base_sas_ioc_info(ioc , mpi_reply, | |
1164 | mpt3sas_base_get_msg_frame(ioc, smid)); | |
1165 | } | |
af009411 | 1166 | |
f92363d1 SR |
1167 | if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { |
1168 | loginfo = le32_to_cpu(mpi_reply->IOCLogInfo); | |
1169 | _base_sas_log_info(ioc, loginfo); | |
1170 | } | |
1171 | ||
1172 | if (ioc_status || loginfo) { | |
1173 | ioc_status &= MPI2_IOCSTATUS_MASK; | |
1174 | mpt3sas_trigger_mpi(ioc, ioc_status, loginfo); | |
1175 | } | |
1176 | } | |
1177 | ||
1178 | /** | |
1179 | * mpt3sas_base_done - base internal command completion routine | |
1180 | * @ioc: per adapter object | |
1181 | * @smid: system request message index | |
1182 | * @msix_index: MSIX table index supplied by the OS | |
1183 | * @reply: reply message frame(lower 32bit addr) | |
1184 | * | |
4beb4867 BVA |
1185 | * Return: |
1186 | * 1 meaning mf should be freed from _base_interrupt | |
1187 | * 0 means the mf is freed from this function. | |
f92363d1 SR |
1188 | */ |
1189 | u8 | |
1190 | mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, | |
1191 | u32 reply) | |
1192 | { | |
1193 | MPI2DefaultReply_t *mpi_reply; | |
1194 | ||
1195 | mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); | |
1196 | if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK) | |
fd0331b3 | 1197 | return mpt3sas_check_for_pending_internal_cmds(ioc, smid); |
f92363d1 SR |
1198 | |
1199 | if (ioc->base_cmds.status == MPT3_CMD_NOT_USED) | |
1200 | return 1; | |
1201 | ||
1202 | ioc->base_cmds.status |= MPT3_CMD_COMPLETE; | |
1203 | if (mpi_reply) { | |
1204 | ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID; | |
1205 | memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); | |
1206 | } | |
1207 | ioc->base_cmds.status &= ~MPT3_CMD_PENDING; | |
1208 | ||
1209 | complete(&ioc->base_cmds.done); | |
1210 | return 1; | |
1211 | } | |
1212 | ||
1213 | /** | |
1214 | * _base_async_event - main callback handler for firmware asyn events | |
1215 | * @ioc: per adapter object | |
1216 | * @msix_index: MSIX table index supplied by the OS | |
1217 | * @reply: reply message frame(lower 32bit addr) | |
1218 | * | |
4beb4867 BVA |
1219 | * Return: |
1220 | * 1 meaning mf should be freed from _base_interrupt | |
1221 | * 0 means the mf is freed from this function. | |
f92363d1 SR |
1222 | */ |
1223 | static u8 | |
1224 | _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply) | |
1225 | { | |
1226 | Mpi2EventNotificationReply_t *mpi_reply; | |
1227 | Mpi2EventAckRequest_t *ack_request; | |
1228 | u16 smid; | |
fd0331b3 | 1229 | struct _event_ack_list *delayed_event_ack; |
f92363d1 SR |
1230 | |
1231 | mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); | |
1232 | if (!mpi_reply) | |
1233 | return 1; | |
1234 | if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION) | |
1235 | return 1; | |
af009411 | 1236 | |
f92363d1 | 1237 | _base_display_event_data(ioc, mpi_reply); |
af009411 | 1238 | |
f92363d1 SR |
1239 | if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED)) |
1240 | goto out; | |
1241 | smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); | |
1242 | if (!smid) { | |
fd0331b3 SS |
1243 | delayed_event_ack = kzalloc(sizeof(*delayed_event_ack), |
1244 | GFP_ATOMIC); | |
1245 | if (!delayed_event_ack) | |
1246 | goto out; | |
1247 | INIT_LIST_HEAD(&delayed_event_ack->list); | |
1248 | delayed_event_ack->Event = mpi_reply->Event; | |
1249 | delayed_event_ack->EventContext = mpi_reply->EventContext; | |
1250 | list_add_tail(&delayed_event_ack->list, | |
1251 | &ioc->delayed_event_ack_list); | |
1252 | dewtprintk(ioc, pr_info(MPT3SAS_FMT | |
1253 | "DELAYED: EVENT ACK: event (0x%04x)\n", | |
1254 | ioc->name, le16_to_cpu(mpi_reply->Event))); | |
f92363d1 SR |
1255 | goto out; |
1256 | } | |
1257 | ||
1258 | ack_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
1259 | memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t)); | |
1260 | ack_request->Function = MPI2_FUNCTION_EVENT_ACK; | |
1261 | ack_request->Event = mpi_reply->Event; | |
1262 | ack_request->EventContext = mpi_reply->EventContext; | |
1263 | ack_request->VF_ID = 0; /* TODO */ | |
1264 | ack_request->VP_ID = 0; | |
40114bde | 1265 | mpt3sas_base_put_smid_default(ioc, smid); |
f92363d1 SR |
1266 | |
1267 | out: | |
1268 | ||
1269 | /* scsih callback handler */ | |
1270 | mpt3sas_scsih_event_callback(ioc, msix_index, reply); | |
1271 | ||
1272 | /* ctl callback handler */ | |
1273 | mpt3sas_ctl_event_callback(ioc, msix_index, reply); | |
1274 | ||
1275 | return 1; | |
1276 | } | |
1277 | ||
61dfb8a5 | 1278 | static struct scsiio_tracker * |
dbec4c90 | 1279 | _get_st_from_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid) |
12e7c678 | 1280 | { |
dbec4c90 SPS |
1281 | struct scsi_cmnd *cmd; |
1282 | ||
12e7c678 HR |
1283 | if (WARN_ON(!smid) || |
1284 | WARN_ON(smid >= ioc->hi_priority_smid)) | |
1285 | return NULL; | |
dbec4c90 SPS |
1286 | |
1287 | cmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid); | |
1288 | if (cmd) | |
1289 | return scsi_cmd_priv(cmd); | |
1290 | ||
1291 | return NULL; | |
12e7c678 HR |
1292 | } |
1293 | ||
f92363d1 SR |
1294 | /** |
1295 | * _base_get_cb_idx - obtain the callback index | |
1296 | * @ioc: per adapter object | |
1297 | * @smid: system request message index | |
1298 | * | |
4beb4867 | 1299 | * Return: callback index. |
f92363d1 SR |
1300 | */ |
1301 | static u8 | |
1302 | _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
1303 | { | |
1304 | int i; | |
b0cd285e | 1305 | u16 ctl_smid = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT + 1; |
ba4494d4 | 1306 | u8 cb_idx = 0xFF; |
f92363d1 SR |
1307 | |
1308 | if (smid < ioc->hi_priority_smid) { | |
12e7c678 HR |
1309 | struct scsiio_tracker *st; |
1310 | ||
b0cd285e | 1311 | if (smid < ctl_smid) { |
dbec4c90 | 1312 | st = _get_st_from_smid(ioc, smid); |
b0cd285e HR |
1313 | if (st) |
1314 | cb_idx = st->cb_idx; | |
1315 | } else if (smid == ctl_smid) | |
1316 | cb_idx = ioc->ctl_cb_idx; | |
f92363d1 SR |
1317 | } else if (smid < ioc->internal_smid) { |
1318 | i = smid - ioc->hi_priority_smid; | |
1319 | cb_idx = ioc->hpr_lookup[i].cb_idx; | |
1320 | } else if (smid <= ioc->hba_queue_depth) { | |
1321 | i = smid - ioc->internal_smid; | |
1322 | cb_idx = ioc->internal_lookup[i].cb_idx; | |
ba4494d4 | 1323 | } |
f92363d1 SR |
1324 | return cb_idx; |
1325 | } | |
1326 | ||
1327 | /** | |
1328 | * _base_mask_interrupts - disable interrupts | |
1329 | * @ioc: per adapter object | |
1330 | * | |
1331 | * Disabling ResetIRQ, Reply and Doorbell Interrupts | |
f92363d1 SR |
1332 | */ |
1333 | static void | |
1334 | _base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc) | |
1335 | { | |
1336 | u32 him_register; | |
1337 | ||
1338 | ioc->mask_interrupts = 1; | |
1339 | him_register = readl(&ioc->chip->HostInterruptMask); | |
1340 | him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK; | |
1341 | writel(him_register, &ioc->chip->HostInterruptMask); | |
1342 | readl(&ioc->chip->HostInterruptMask); | |
1343 | } | |
1344 | ||
1345 | /** | |
1346 | * _base_unmask_interrupts - enable interrupts | |
1347 | * @ioc: per adapter object | |
1348 | * | |
1349 | * Enabling only Reply Interrupts | |
f92363d1 SR |
1350 | */ |
1351 | static void | |
1352 | _base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc) | |
1353 | { | |
1354 | u32 him_register; | |
1355 | ||
1356 | him_register = readl(&ioc->chip->HostInterruptMask); | |
1357 | him_register &= ~MPI2_HIM_RIM; | |
1358 | writel(him_register, &ioc->chip->HostInterruptMask); | |
1359 | ioc->mask_interrupts = 0; | |
1360 | } | |
1361 | ||
1362 | union reply_descriptor { | |
1363 | u64 word; | |
1364 | struct { | |
1365 | u32 low; | |
1366 | u32 high; | |
1367 | } u; | |
1368 | }; | |
1369 | ||
1370 | /** | |
1371 | * _base_interrupt - MPT adapter (IOC) specific interrupt handler. | |
1372 | * @irq: irq number (not used) | |
1373 | * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure | |
f92363d1 | 1374 | * |
4beb4867 | 1375 | * Return: IRQ_HANDLED if processed, else IRQ_NONE. |
f92363d1 SR |
1376 | */ |
1377 | static irqreturn_t | |
1378 | _base_interrupt(int irq, void *bus_id) | |
1379 | { | |
1380 | struct adapter_reply_queue *reply_q = bus_id; | |
1381 | union reply_descriptor rd; | |
1382 | u32 completed_cmds; | |
1383 | u8 request_desript_type; | |
1384 | u16 smid; | |
1385 | u8 cb_idx; | |
1386 | u32 reply; | |
1387 | u8 msix_index = reply_q->msix_index; | |
1388 | struct MPT3SAS_ADAPTER *ioc = reply_q->ioc; | |
1389 | Mpi2ReplyDescriptorsUnion_t *rpf; | |
1390 | u8 rc; | |
1391 | ||
1392 | if (ioc->mask_interrupts) | |
1393 | return IRQ_NONE; | |
1394 | ||
1395 | if (!atomic_add_unless(&reply_q->busy, 1, 1)) | |
1396 | return IRQ_NONE; | |
1397 | ||
1398 | rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index]; | |
1399 | request_desript_type = rpf->Default.ReplyFlags | |
1400 | & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; | |
1401 | if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) { | |
1402 | atomic_dec(&reply_q->busy); | |
1403 | return IRQ_NONE; | |
1404 | } | |
1405 | ||
1406 | completed_cmds = 0; | |
1407 | cb_idx = 0xFF; | |
1408 | do { | |
1409 | rd.word = le64_to_cpu(rpf->Words); | |
1410 | if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX) | |
1411 | goto out; | |
1412 | reply = 0; | |
1413 | smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1); | |
1414 | if (request_desript_type == | |
1415 | MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS || | |
1416 | request_desript_type == | |
aff39e61 SPS |
1417 | MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS || |
1418 | request_desript_type == | |
1419 | MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS) { | |
f92363d1 SR |
1420 | cb_idx = _base_get_cb_idx(ioc, smid); |
1421 | if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && | |
1422 | (likely(mpt_callbacks[cb_idx] != NULL))) { | |
1423 | rc = mpt_callbacks[cb_idx](ioc, smid, | |
1424 | msix_index, 0); | |
1425 | if (rc) | |
1426 | mpt3sas_base_free_smid(ioc, smid); | |
1427 | } | |
1428 | } else if (request_desript_type == | |
1429 | MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { | |
1430 | reply = le32_to_cpu( | |
1431 | rpf->AddressReply.ReplyFrameAddress); | |
1432 | if (reply > ioc->reply_dma_max_address || | |
1433 | reply < ioc->reply_dma_min_address) | |
1434 | reply = 0; | |
1435 | if (smid) { | |
1436 | cb_idx = _base_get_cb_idx(ioc, smid); | |
1437 | if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && | |
1438 | (likely(mpt_callbacks[cb_idx] != NULL))) { | |
1439 | rc = mpt_callbacks[cb_idx](ioc, smid, | |
1440 | msix_index, reply); | |
1441 | if (reply) | |
1442 | _base_display_reply_info(ioc, | |
1443 | smid, msix_index, reply); | |
1444 | if (rc) | |
1445 | mpt3sas_base_free_smid(ioc, | |
1446 | smid); | |
1447 | } | |
1448 | } else { | |
1449 | _base_async_event(ioc, msix_index, reply); | |
1450 | } | |
1451 | ||
1452 | /* reply free queue handling */ | |
1453 | if (reply) { | |
1454 | ioc->reply_free_host_index = | |
1455 | (ioc->reply_free_host_index == | |
1456 | (ioc->reply_free_queue_depth - 1)) ? | |
1457 | 0 : ioc->reply_free_host_index + 1; | |
1458 | ioc->reply_free[ioc->reply_free_host_index] = | |
1459 | cpu_to_le32(reply); | |
b4472d71 SPS |
1460 | if (ioc->is_mcpu_endpoint) |
1461 | _base_clone_reply_to_sys_mem(ioc, | |
cf6bf971 | 1462 | reply, |
b4472d71 | 1463 | ioc->reply_free_host_index); |
f92363d1 SR |
1464 | writel(ioc->reply_free_host_index, |
1465 | &ioc->chip->ReplyFreeHostIndex); | |
1466 | } | |
1467 | } | |
1468 | ||
1469 | rpf->Words = cpu_to_le64(ULLONG_MAX); | |
1470 | reply_q->reply_post_host_index = | |
1471 | (reply_q->reply_post_host_index == | |
1472 | (ioc->reply_post_queue_depth - 1)) ? 0 : | |
1473 | reply_q->reply_post_host_index + 1; | |
1474 | request_desript_type = | |
1475 | reply_q->reply_post_free[reply_q->reply_post_host_index]. | |
1476 | Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; | |
1477 | completed_cmds++; | |
6b4c335a C |
1478 | /* Update the reply post host index after continuously |
1479 | * processing the threshold number of Reply Descriptors. | |
1480 | * So that FW can find enough entries to post the Reply | |
1481 | * Descriptors in the reply descriptor post queue. | |
1482 | */ | |
1483 | if (completed_cmds > ioc->hba_queue_depth/3) { | |
1484 | if (ioc->combined_reply_queue) { | |
1485 | writel(reply_q->reply_post_host_index | | |
1486 | ((msix_index & 7) << | |
1487 | MPI2_RPHI_MSIX_INDEX_SHIFT), | |
1488 | ioc->replyPostRegisterIndex[msix_index/8]); | |
1489 | } else { | |
1490 | writel(reply_q->reply_post_host_index | | |
1491 | (msix_index << | |
1492 | MPI2_RPHI_MSIX_INDEX_SHIFT), | |
1493 | &ioc->chip->ReplyPostHostIndex); | |
1494 | } | |
1495 | completed_cmds = 1; | |
1496 | } | |
f92363d1 SR |
1497 | if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) |
1498 | goto out; | |
1499 | if (!reply_q->reply_post_host_index) | |
1500 | rpf = reply_q->reply_post_free; | |
1501 | else | |
1502 | rpf++; | |
1503 | } while (1); | |
1504 | ||
1505 | out: | |
1506 | ||
1507 | if (!completed_cmds) { | |
1508 | atomic_dec(&reply_q->busy); | |
1509 | return IRQ_NONE; | |
1510 | } | |
1511 | ||
7786ab6a SR |
1512 | if (ioc->is_warpdrive) { |
1513 | writel(reply_q->reply_post_host_index, | |
1514 | ioc->reply_post_host_index[msix_index]); | |
1515 | atomic_dec(&reply_q->busy); | |
1516 | return IRQ_HANDLED; | |
1517 | } | |
fb77bb53 SR |
1518 | |
1519 | /* Update Reply Post Host Index. | |
1520 | * For those HBA's which support combined reply queue feature | |
1521 | * 1. Get the correct Supplemental Reply Post Host Index Register. | |
1522 | * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host | |
1523 | * Index Register address bank i.e replyPostRegisterIndex[], | |
1524 | * 2. Then update this register with new reply host index value | |
1525 | * in ReplyPostIndex field and the MSIxIndex field with | |
1526 | * msix_index value reduced to a value between 0 and 7, | |
1527 | * using a modulo 8 operation. Since each Supplemental Reply Post | |
1528 | * Host Index Register supports 8 MSI-X vectors. | |
1529 | * | |
1530 | * For other HBA's just update the Reply Post Host Index register with | |
1531 | * new reply host index value in ReplyPostIndex Field and msix_index | |
1532 | * value in MSIxIndex field. | |
1533 | */ | |
0bb337c9 | 1534 | if (ioc->combined_reply_queue) |
fb77bb53 SR |
1535 | writel(reply_q->reply_post_host_index | ((msix_index & 7) << |
1536 | MPI2_RPHI_MSIX_INDEX_SHIFT), | |
1537 | ioc->replyPostRegisterIndex[msix_index/8]); | |
1538 | else | |
1539 | writel(reply_q->reply_post_host_index | (msix_index << | |
1540 | MPI2_RPHI_MSIX_INDEX_SHIFT), | |
1541 | &ioc->chip->ReplyPostHostIndex); | |
f92363d1 SR |
1542 | atomic_dec(&reply_q->busy); |
1543 | return IRQ_HANDLED; | |
1544 | } | |
1545 | ||
1546 | /** | |
1547 | * _base_is_controller_msix_enabled - is controller support muli-reply queues | |
1548 | * @ioc: per adapter object | |
1549 | * | |
4beb4867 | 1550 | * Return: Whether or not MSI/X is enabled. |
f92363d1 SR |
1551 | */ |
1552 | static inline int | |
1553 | _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc) | |
1554 | { | |
1555 | return (ioc->facts.IOCCapabilities & | |
1556 | MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable; | |
1557 | } | |
1558 | ||
1559 | /** | |
5f0dfb7a | 1560 | * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts |
f92363d1 | 1561 | * @ioc: per adapter object |
5f0dfb7a | 1562 | * Context: non ISR conext |
f92363d1 | 1563 | * |
5f0dfb7a | 1564 | * Called when a Task Management request has completed. |
f92363d1 SR |
1565 | */ |
1566 | void | |
5f0dfb7a | 1567 | mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
1568 | { |
1569 | struct adapter_reply_queue *reply_q; | |
1570 | ||
1571 | /* If MSIX capability is turned off | |
1572 | * then multi-queues are not enabled | |
1573 | */ | |
1574 | if (!_base_is_controller_msix_enabled(ioc)) | |
1575 | return; | |
1576 | ||
1577 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { | |
5f0dfb7a C |
1578 | if (ioc->shost_recovery || ioc->remove_host || |
1579 | ioc->pci_error_recovery) | |
f92363d1 SR |
1580 | return; |
1581 | /* TMs are on msix_index == 0 */ | |
1582 | if (reply_q->msix_index == 0) | |
1583 | continue; | |
1d55abc0 | 1584 | synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index)); |
f92363d1 SR |
1585 | } |
1586 | } | |
1587 | ||
1588 | /** | |
1589 | * mpt3sas_base_release_callback_handler - clear interrupt callback handler | |
1590 | * @cb_idx: callback index | |
f92363d1 SR |
1591 | */ |
1592 | void | |
1593 | mpt3sas_base_release_callback_handler(u8 cb_idx) | |
1594 | { | |
1595 | mpt_callbacks[cb_idx] = NULL; | |
1596 | } | |
1597 | ||
1598 | /** | |
1599 | * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler | |
1600 | * @cb_func: callback function | |
1601 | * | |
4beb4867 | 1602 | * Return: Index of @cb_func. |
f92363d1 SR |
1603 | */ |
1604 | u8 | |
1605 | mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func) | |
1606 | { | |
1607 | u8 cb_idx; | |
1608 | ||
1609 | for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--) | |
1610 | if (mpt_callbacks[cb_idx] == NULL) | |
1611 | break; | |
1612 | ||
1613 | mpt_callbacks[cb_idx] = cb_func; | |
1614 | return cb_idx; | |
1615 | } | |
1616 | ||
1617 | /** | |
1618 | * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler | |
f92363d1 SR |
1619 | */ |
1620 | void | |
1621 | mpt3sas_base_initialize_callback_handler(void) | |
1622 | { | |
1623 | u8 cb_idx; | |
1624 | ||
1625 | for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++) | |
1626 | mpt3sas_base_release_callback_handler(cb_idx); | |
1627 | } | |
1628 | ||
1629 | ||
1630 | /** | |
1631 | * _base_build_zero_len_sge - build zero length sg entry | |
1632 | * @ioc: per adapter object | |
1633 | * @paddr: virtual address for SGE | |
1634 | * | |
1635 | * Create a zero length scatter gather entry to insure the IOCs hardware has | |
1636 | * something to use if the target device goes brain dead and tries | |
1637 | * to send data even when none is asked for. | |
f92363d1 SR |
1638 | */ |
1639 | static void | |
1640 | _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr) | |
1641 | { | |
1642 | u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT | | |
1643 | MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST | | |
1644 | MPI2_SGE_FLAGS_SIMPLE_ELEMENT) << | |
1645 | MPI2_SGE_FLAGS_SHIFT); | |
1646 | ioc->base_add_sg_single(paddr, flags_length, -1); | |
1647 | } | |
1648 | ||
1649 | /** | |
1650 | * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr. | |
1651 | * @paddr: virtual address for SGE | |
1652 | * @flags_length: SGE flags and data transfer length | |
1653 | * @dma_addr: Physical address | |
f92363d1 SR |
1654 | */ |
1655 | static void | |
1656 | _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr) | |
1657 | { | |
1658 | Mpi2SGESimple32_t *sgel = paddr; | |
1659 | ||
1660 | flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING | | |
1661 | MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; | |
1662 | sgel->FlagsLength = cpu_to_le32(flags_length); | |
1663 | sgel->Address = cpu_to_le32(dma_addr); | |
1664 | } | |
1665 | ||
1666 | ||
1667 | /** | |
1668 | * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr. | |
1669 | * @paddr: virtual address for SGE | |
1670 | * @flags_length: SGE flags and data transfer length | |
1671 | * @dma_addr: Physical address | |
f92363d1 SR |
1672 | */ |
1673 | static void | |
1674 | _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr) | |
1675 | { | |
1676 | Mpi2SGESimple64_t *sgel = paddr; | |
1677 | ||
1678 | flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING | | |
1679 | MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; | |
1680 | sgel->FlagsLength = cpu_to_le32(flags_length); | |
1681 | sgel->Address = cpu_to_le64(dma_addr); | |
1682 | } | |
1683 | ||
1684 | /** | |
1685 | * _base_get_chain_buffer_tracker - obtain chain tracker | |
1686 | * @ioc: per adapter object | |
dbec4c90 | 1687 | * @scmd: SCSI commands of the IO request |
f92363d1 | 1688 | * |
4beb4867 | 1689 | * Return: chain tracker from chain_lookup table using key as |
93204b78 | 1690 | * smid and smid's chain_offset. |
f92363d1 SR |
1691 | */ |
1692 | static struct chain_tracker * | |
dbec4c90 SPS |
1693 | _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, |
1694 | struct scsi_cmnd *scmd) | |
f92363d1 SR |
1695 | { |
1696 | struct chain_tracker *chain_req; | |
dbec4c90 | 1697 | struct scsiio_tracker *st = scsi_cmd_priv(scmd); |
93204b78 C |
1698 | u16 smid = st->smid; |
1699 | u8 chain_offset = | |
1700 | atomic_read(&ioc->chain_lookup[smid - 1].chain_offset); | |
f92363d1 | 1701 | |
93204b78 | 1702 | if (chain_offset == ioc->chains_needed_per_io) |
f92363d1 | 1703 | return NULL; |
93204b78 C |
1704 | |
1705 | chain_req = &ioc->chain_lookup[smid - 1].chains_per_smid[chain_offset]; | |
1706 | atomic_inc(&ioc->chain_lookup[smid - 1].chain_offset); | |
f92363d1 SR |
1707 | return chain_req; |
1708 | } | |
1709 | ||
1710 | ||
1711 | /** | |
1712 | * _base_build_sg - build generic sg | |
1713 | * @ioc: per adapter object | |
1714 | * @psge: virtual address for SGE | |
1715 | * @data_out_dma: physical address for WRITES | |
1716 | * @data_out_sz: data xfer size for WRITES | |
1717 | * @data_in_dma: physical address for READS | |
1718 | * @data_in_sz: data xfer size for READS | |
f92363d1 SR |
1719 | */ |
1720 | static void | |
1721 | _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge, | |
1722 | dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, | |
1723 | size_t data_in_sz) | |
1724 | { | |
1725 | u32 sgl_flags; | |
1726 | ||
1727 | if (!data_out_sz && !data_in_sz) { | |
1728 | _base_build_zero_len_sge(ioc, psge); | |
1729 | return; | |
1730 | } | |
1731 | ||
1732 | if (data_out_sz && data_in_sz) { | |
1733 | /* WRITE sgel first */ | |
1734 | sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | | |
1735 | MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC); | |
1736 | sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; | |
1737 | ioc->base_add_sg_single(psge, sgl_flags | | |
1738 | data_out_sz, data_out_dma); | |
1739 | ||
1740 | /* incr sgel */ | |
1741 | psge += ioc->sge_size; | |
1742 | ||
1743 | /* READ sgel last */ | |
1744 | sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | | |
1745 | MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | | |
1746 | MPI2_SGE_FLAGS_END_OF_LIST); | |
1747 | sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; | |
1748 | ioc->base_add_sg_single(psge, sgl_flags | | |
1749 | data_in_sz, data_in_dma); | |
1750 | } else if (data_out_sz) /* WRITE */ { | |
1751 | sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | | |
1752 | MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | | |
1753 | MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC); | |
1754 | sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; | |
1755 | ioc->base_add_sg_single(psge, sgl_flags | | |
1756 | data_out_sz, data_out_dma); | |
1757 | } else if (data_in_sz) /* READ */ { | |
1758 | sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | | |
1759 | MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | | |
1760 | MPI2_SGE_FLAGS_END_OF_LIST); | |
1761 | sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; | |
1762 | ioc->base_add_sg_single(psge, sgl_flags | | |
1763 | data_in_sz, data_in_dma); | |
1764 | } | |
1765 | } | |
1766 | ||
aff39e61 SPS |
1767 | /* IEEE format sgls */ |
1768 | ||
1769 | /** | |
1770 | * _base_build_nvme_prp - This function is called for NVMe end devices to build | |
1771 | * a native SGL (NVMe PRP). The native SGL is built starting in the first PRP | |
1772 | * entry of the NVMe message (PRP1). If the data buffer is small enough to be | |
1773 | * described entirely using PRP1, then PRP2 is not used. If needed, PRP2 is | |
1774 | * used to describe a larger data buffer. If the data buffer is too large to | |
1775 | * describe using the two PRP entriess inside the NVMe message, then PRP1 | |
1776 | * describes the first data memory segment, and PRP2 contains a pointer to a PRP | |
1777 | * list located elsewhere in memory to describe the remaining data memory | |
1778 | * segments. The PRP list will be contiguous. | |
4beb4867 | 1779 | * |
aff39e61 SPS |
1780 | * The native SGL for NVMe devices is a Physical Region Page (PRP). A PRP |
1781 | * consists of a list of PRP entries to describe a number of noncontigous | |
1782 | * physical memory segments as a single memory buffer, just as a SGL does. Note | |
1783 | * however, that this function is only used by the IOCTL call, so the memory | |
1784 | * given will be guaranteed to be contiguous. There is no need to translate | |
1785 | * non-contiguous SGL into a PRP in this case. All PRPs will describe | |
1786 | * contiguous space that is one page size each. | |
1787 | * | |
1788 | * Each NVMe message contains two PRP entries. The first (PRP1) either contains | |
1789 | * a PRP list pointer or a PRP element, depending upon the command. PRP2 | |
1790 | * contains the second PRP element if the memory being described fits within 2 | |
1791 | * PRP entries, or a PRP list pointer if the PRP spans more than two entries. | |
1792 | * | |
1793 | * A PRP list pointer contains the address of a PRP list, structured as a linear | |
1794 | * array of PRP entries. Each PRP entry in this list describes a segment of | |
1795 | * physical memory. | |
1796 | * | |
1797 | * Each 64-bit PRP entry comprises an address and an offset field. The address | |
1798 | * always points at the beginning of a 4KB physical memory page, and the offset | |
1799 | * describes where within that 4KB page the memory segment begins. Only the | |
1800 | * first element in a PRP list may contain a non-zero offest, implying that all | |
1801 | * memory segments following the first begin at the start of a 4KB page. | |
1802 | * | |
1803 | * Each PRP element normally describes 4KB of physical memory, with exceptions | |
1804 | * for the first and last elements in the list. If the memory being described | |
1805 | * by the list begins at a non-zero offset within the first 4KB page, then the | |
1806 | * first PRP element will contain a non-zero offset indicating where the region | |
1807 | * begins within the 4KB page. The last memory segment may end before the end | |
1808 | * of the 4KB segment, depending upon the overall size of the memory being | |
1809 | * described by the PRP list. | |
1810 | * | |
1811 | * Since PRP entries lack any indication of size, the overall data buffer length | |
1812 | * is used to determine where the end of the data memory buffer is located, and | |
1813 | * how many PRP entries are required to describe it. | |
1814 | * | |
1815 | * @ioc: per adapter object | |
1816 | * @smid: system request message index for getting asscociated SGL | |
1817 | * @nvme_encap_request: the NVMe request msg frame pointer | |
1818 | * @data_out_dma: physical address for WRITES | |
1819 | * @data_out_sz: data xfer size for WRITES | |
1820 | * @data_in_dma: physical address for READS | |
1821 | * @data_in_sz: data xfer size for READS | |
aff39e61 SPS |
1822 | */ |
1823 | static void | |
1824 | _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, | |
1825 | Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, | |
1826 | dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, | |
1827 | size_t data_in_sz) | |
1828 | { | |
1829 | int prp_size = NVME_PRP_SIZE; | |
d8335ae2 AB |
1830 | __le64 *prp_entry, *prp1_entry, *prp2_entry; |
1831 | __le64 *prp_page; | |
1832 | dma_addr_t prp_entry_dma, prp_page_dma, dma_addr; | |
aff39e61 SPS |
1833 | u32 offset, entry_len; |
1834 | u32 page_mask_result, page_mask; | |
aff39e61 | 1835 | size_t length; |
84203b35 BVA |
1836 | struct mpt3sas_nvme_cmd *nvme_cmd = |
1837 | (void *)nvme_encap_request->NVMe_Command; | |
aff39e61 SPS |
1838 | |
1839 | /* | |
1840 | * Not all commands require a data transfer. If no data, just return | |
1841 | * without constructing any PRP. | |
1842 | */ | |
1843 | if (!data_in_sz && !data_out_sz) | |
1844 | return; | |
84203b35 BVA |
1845 | prp1_entry = &nvme_cmd->prp1; |
1846 | prp2_entry = &nvme_cmd->prp2; | |
aff39e61 SPS |
1847 | prp_entry = prp1_entry; |
1848 | /* | |
1849 | * For the PRP entries, use the specially allocated buffer of | |
1850 | * contiguous memory. | |
1851 | */ | |
494f401b | 1852 | prp_page = (__le64 *)mpt3sas_base_get_pcie_sgl(ioc, smid); |
d8335ae2 | 1853 | prp_page_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid); |
aff39e61 SPS |
1854 | |
1855 | /* | |
1856 | * Check if we are within 1 entry of a page boundary we don't | |
1857 | * want our first entry to be a PRP List entry. | |
1858 | */ | |
1859 | page_mask = ioc->page_size - 1; | |
1860 | page_mask_result = (uintptr_t)((u8 *)prp_page + prp_size) & page_mask; | |
1861 | if (!page_mask_result) { | |
1862 | /* Bump up to next page boundary. */ | |
494f401b | 1863 | prp_page = (__le64 *)((u8 *)prp_page + prp_size); |
d8335ae2 | 1864 | prp_page_dma = prp_page_dma + prp_size; |
aff39e61 SPS |
1865 | } |
1866 | ||
1867 | /* | |
1868 | * Set PRP physical pointer, which initially points to the current PRP | |
1869 | * DMA memory page. | |
1870 | */ | |
d8335ae2 | 1871 | prp_entry_dma = prp_page_dma; |
aff39e61 SPS |
1872 | |
1873 | /* Get physical address and length of the data buffer. */ | |
1874 | if (data_in_sz) { | |
d8335ae2 | 1875 | dma_addr = data_in_dma; |
aff39e61 SPS |
1876 | length = data_in_sz; |
1877 | } else { | |
d8335ae2 | 1878 | dma_addr = data_out_dma; |
aff39e61 SPS |
1879 | length = data_out_sz; |
1880 | } | |
1881 | ||
1882 | /* Loop while the length is not zero. */ | |
1883 | while (length) { | |
1884 | /* | |
1885 | * Check if we need to put a list pointer here if we are at | |
1886 | * page boundary - prp_size (8 bytes). | |
1887 | */ | |
d8335ae2 | 1888 | page_mask_result = (prp_entry_dma + prp_size) & page_mask; |
aff39e61 SPS |
1889 | if (!page_mask_result) { |
1890 | /* | |
1891 | * This is the last entry in a PRP List, so we need to | |
1892 | * put a PRP list pointer here. What this does is: | |
1893 | * - bump the current memory pointer to the next | |
1894 | * address, which will be the next full page. | |
1895 | * - set the PRP Entry to point to that page. This | |
1896 | * is now the PRP List pointer. | |
1897 | * - bump the PRP Entry pointer the start of the | |
1898 | * next page. Since all of this PRP memory is | |
1899 | * contiguous, no need to get a new page - it's | |
1900 | * just the next address. | |
1901 | */ | |
d8335ae2 AB |
1902 | prp_entry_dma++; |
1903 | *prp_entry = cpu_to_le64(prp_entry_dma); | |
aff39e61 SPS |
1904 | prp_entry++; |
1905 | } | |
1906 | ||
1907 | /* Need to handle if entry will be part of a page. */ | |
d8335ae2 | 1908 | offset = dma_addr & page_mask; |
aff39e61 SPS |
1909 | entry_len = ioc->page_size - offset; |
1910 | ||
1911 | if (prp_entry == prp1_entry) { | |
1912 | /* | |
1913 | * Must fill in the first PRP pointer (PRP1) before | |
1914 | * moving on. | |
1915 | */ | |
d8335ae2 | 1916 | *prp1_entry = cpu_to_le64(dma_addr); |
aff39e61 SPS |
1917 | |
1918 | /* | |
1919 | * Now point to the second PRP entry within the | |
1920 | * command (PRP2). | |
1921 | */ | |
1922 | prp_entry = prp2_entry; | |
1923 | } else if (prp_entry == prp2_entry) { | |
1924 | /* | |
1925 | * Should the PRP2 entry be a PRP List pointer or just | |
1926 | * a regular PRP pointer? If there is more than one | |
1927 | * more page of data, must use a PRP List pointer. | |
1928 | */ | |
1929 | if (length > ioc->page_size) { | |
1930 | /* | |
1931 | * PRP2 will contain a PRP List pointer because | |
1932 | * more PRP's are needed with this command. The | |
1933 | * list will start at the beginning of the | |
1934 | * contiguous buffer. | |
1935 | */ | |
d8335ae2 | 1936 | *prp2_entry = cpu_to_le64(prp_entry_dma); |
aff39e61 SPS |
1937 | |
1938 | /* | |
1939 | * The next PRP Entry will be the start of the | |
1940 | * first PRP List. | |
1941 | */ | |
1942 | prp_entry = prp_page; | |
1943 | } else { | |
1944 | /* | |
1945 | * After this, the PRP Entries are complete. | |
1946 | * This command uses 2 PRP's and no PRP list. | |
1947 | */ | |
d8335ae2 | 1948 | *prp2_entry = cpu_to_le64(dma_addr); |
aff39e61 SPS |
1949 | } |
1950 | } else { | |
1951 | /* | |
1952 | * Put entry in list and bump the addresses. | |
1953 | * | |
1954 | * After PRP1 and PRP2 are filled in, this will fill in | |
1955 | * all remaining PRP entries in a PRP List, one per | |
1956 | * each time through the loop. | |
1957 | */ | |
d8335ae2 | 1958 | *prp_entry = cpu_to_le64(dma_addr); |
aff39e61 | 1959 | prp_entry++; |
d8335ae2 | 1960 | prp_entry_dma++; |
aff39e61 SPS |
1961 | } |
1962 | ||
1963 | /* | |
1964 | * Bump the phys address of the command's data buffer by the | |
1965 | * entry_len. | |
1966 | */ | |
d8335ae2 | 1967 | dma_addr += entry_len; |
aff39e61 SPS |
1968 | |
1969 | /* Decrement length accounting for last partial page. */ | |
1970 | if (entry_len > length) | |
1971 | length = 0; | |
1972 | else | |
1973 | length -= entry_len; | |
1974 | } | |
1975 | } | |
1976 | ||
016d5c35 SPS |
1977 | /** |
1978 | * base_make_prp_nvme - | |
1979 | * Prepare PRPs(Physical Region Page)- SGLs specific to NVMe drives only | |
1980 | * | |
1981 | * @ioc: per adapter object | |
1982 | * @scmd: SCSI command from the mid-layer | |
1983 | * @mpi_request: mpi request | |
1984 | * @smid: msg Index | |
1985 | * @sge_count: scatter gather element count. | |
1986 | * | |
4beb4867 | 1987 | * Return: true: PRPs are built |
016d5c35 SPS |
1988 | * false: IEEE SGLs needs to be built |
1989 | */ | |
494f401b | 1990 | static void |
016d5c35 SPS |
1991 | base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc, |
1992 | struct scsi_cmnd *scmd, | |
1993 | Mpi25SCSIIORequest_t *mpi_request, | |
1994 | u16 smid, int sge_count) | |
1995 | { | |
d8335ae2 | 1996 | int sge_len, num_prp_in_chain = 0; |
016d5c35 | 1997 | Mpi25IeeeSgeChain64_t *main_chain_element, *ptr_first_sgl; |
494f401b | 1998 | __le64 *curr_buff; |
d8335ae2 | 1999 | dma_addr_t msg_dma, sge_addr, offset; |
016d5c35 SPS |
2000 | u32 page_mask, page_mask_result; |
2001 | struct scatterlist *sg_scmd; | |
2002 | u32 first_prp_len; | |
2003 | int data_len = scsi_bufflen(scmd); | |
2004 | u32 nvme_pg_size; | |
2005 | ||
2006 | nvme_pg_size = max_t(u32, ioc->page_size, NVME_PRP_PAGE_SIZE); | |
2007 | /* | |
2008 | * Nvme has a very convoluted prp format. One prp is required | |
2009 | * for each page or partial page. Driver need to split up OS sg_list | |
2010 | * entries if it is longer than one page or cross a page | |
2011 | * boundary. Driver also have to insert a PRP list pointer entry as | |
2012 | * the last entry in each physical page of the PRP list. | |
2013 | * | |
2014 | * NOTE: The first PRP "entry" is actually placed in the first | |
2015 | * SGL entry in the main message as IEEE 64 format. The 2nd | |
2016 | * entry in the main message is the chain element, and the rest | |
2017 | * of the PRP entries are built in the contiguous pcie buffer. | |
2018 | */ | |
2019 | page_mask = nvme_pg_size - 1; | |
2020 | ||
2021 | /* | |
2022 | * Native SGL is needed. | |
2023 | * Put a chain element in main message frame that points to the first | |
2024 | * chain buffer. | |
2025 | * | |
2026 | * NOTE: The ChainOffset field must be 0 when using a chain pointer to | |
2027 | * a native SGL. | |
2028 | */ | |
2029 | ||
2030 | /* Set main message chain element pointer */ | |
2031 | main_chain_element = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL; | |
2032 | /* | |
2033 | * For NVMe the chain element needs to be the 2nd SG entry in the main | |
2034 | * message. | |
2035 | */ | |
2036 | main_chain_element = (Mpi25IeeeSgeChain64_t *) | |
2037 | ((u8 *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64)); | |
2038 | ||
2039 | /* | |
2040 | * For the PRP entries, use the specially allocated buffer of | |
2041 | * contiguous memory. Normal chain buffers can't be used | |
2042 | * because each chain buffer would need to be the size of an OS | |
2043 | * page (4k). | |
2044 | */ | |
2045 | curr_buff = mpt3sas_base_get_pcie_sgl(ioc, smid); | |
d8335ae2 | 2046 | msg_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid); |
016d5c35 | 2047 | |
d8335ae2 | 2048 | main_chain_element->Address = cpu_to_le64(msg_dma); |
016d5c35 SPS |
2049 | main_chain_element->NextChainOffset = 0; |
2050 | main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | | |
2051 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | | |
2052 | MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP; | |
2053 | ||
2054 | /* Build first prp, sge need not to be page aligned*/ | |
2055 | ptr_first_sgl = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL; | |
2056 | sg_scmd = scsi_sglist(scmd); | |
2057 | sge_addr = sg_dma_address(sg_scmd); | |
2058 | sge_len = sg_dma_len(sg_scmd); | |
2059 | ||
d8335ae2 | 2060 | offset = sge_addr & page_mask; |
016d5c35 SPS |
2061 | first_prp_len = nvme_pg_size - offset; |
2062 | ||
2063 | ptr_first_sgl->Address = cpu_to_le64(sge_addr); | |
2064 | ptr_first_sgl->Length = cpu_to_le32(first_prp_len); | |
2065 | ||
2066 | data_len -= first_prp_len; | |
2067 | ||
2068 | if (sge_len > first_prp_len) { | |
2069 | sge_addr += first_prp_len; | |
2070 | sge_len -= first_prp_len; | |
2071 | } else if (data_len && (sge_len == first_prp_len)) { | |
2072 | sg_scmd = sg_next(sg_scmd); | |
2073 | sge_addr = sg_dma_address(sg_scmd); | |
2074 | sge_len = sg_dma_len(sg_scmd); | |
2075 | } | |
2076 | ||
2077 | for (;;) { | |
d8335ae2 | 2078 | offset = sge_addr & page_mask; |
016d5c35 SPS |
2079 | |
2080 | /* Put PRP pointer due to page boundary*/ | |
2081 | page_mask_result = (uintptr_t)(curr_buff + 1) & page_mask; | |
2082 | if (unlikely(!page_mask_result)) { | |
2083 | scmd_printk(KERN_NOTICE, | |
2084 | scmd, "page boundary curr_buff: 0x%p\n", | |
2085 | curr_buff); | |
d8335ae2 AB |
2086 | msg_dma += 8; |
2087 | *curr_buff = cpu_to_le64(msg_dma); | |
016d5c35 SPS |
2088 | curr_buff++; |
2089 | num_prp_in_chain++; | |
2090 | } | |
2091 | ||
2092 | *curr_buff = cpu_to_le64(sge_addr); | |
2093 | curr_buff++; | |
d8335ae2 | 2094 | msg_dma += 8; |
016d5c35 SPS |
2095 | num_prp_in_chain++; |
2096 | ||
2097 | sge_addr += nvme_pg_size; | |
2098 | sge_len -= nvme_pg_size; | |
2099 | data_len -= nvme_pg_size; | |
2100 | ||
2101 | if (data_len <= 0) | |
2102 | break; | |
2103 | ||
2104 | if (sge_len > 0) | |
2105 | continue; | |
2106 | ||
2107 | sg_scmd = sg_next(sg_scmd); | |
2108 | sge_addr = sg_dma_address(sg_scmd); | |
2109 | sge_len = sg_dma_len(sg_scmd); | |
2110 | } | |
2111 | ||
2112 | main_chain_element->Length = | |
2113 | cpu_to_le32(num_prp_in_chain * sizeof(u64)); | |
2114 | return; | |
2115 | } | |
2116 | ||
2117 | static bool | |
2118 | base_is_prp_possible(struct MPT3SAS_ADAPTER *ioc, | |
2119 | struct _pcie_device *pcie_device, struct scsi_cmnd *scmd, int sge_count) | |
2120 | { | |
2121 | u32 data_length = 0; | |
016d5c35 SPS |
2122 | bool build_prp = true; |
2123 | ||
494f401b | 2124 | data_length = scsi_bufflen(scmd); |
016d5c35 SPS |
2125 | |
2126 | /* If Datalenth is <= 16K and number of SGE’s entries are <= 2 | |
2127 | * we built IEEE SGL | |
2128 | */ | |
2129 | if ((data_length <= NVME_PRP_PAGE_SIZE*4) && (sge_count <= 2)) | |
2130 | build_prp = false; | |
2131 | ||
2132 | return build_prp; | |
2133 | } | |
2134 | ||
2135 | /** | |
2136 | * _base_check_pcie_native_sgl - This function is called for PCIe end devices to | |
2137 | * determine if the driver needs to build a native SGL. If so, that native | |
2138 | * SGL is built in the special contiguous buffers allocated especially for | |
2139 | * PCIe SGL creation. If the driver will not build a native SGL, return | |
2140 | * TRUE and a normal IEEE SGL will be built. Currently this routine | |
2141 | * supports NVMe. | |
2142 | * @ioc: per adapter object | |
2143 | * @mpi_request: mf request pointer | |
2144 | * @smid: system request message index | |
2145 | * @scmd: scsi command | |
2146 | * @pcie_device: points to the PCIe device's info | |
2147 | * | |
4beb4867 | 2148 | * Return: 0 if native SGL was built, 1 if no SGL was built |
016d5c35 SPS |
2149 | */ |
2150 | static int | |
2151 | _base_check_pcie_native_sgl(struct MPT3SAS_ADAPTER *ioc, | |
2152 | Mpi25SCSIIORequest_t *mpi_request, u16 smid, struct scsi_cmnd *scmd, | |
2153 | struct _pcie_device *pcie_device) | |
2154 | { | |
016d5c35 SPS |
2155 | int sges_left; |
2156 | ||
2157 | /* Get the SG list pointer and info. */ | |
016d5c35 SPS |
2158 | sges_left = scsi_dma_map(scmd); |
2159 | if (sges_left < 0) { | |
2160 | sdev_printk(KERN_ERR, scmd->device, | |
2161 | "scsi_dma_map failed: request for %d bytes!\n", | |
2162 | scsi_bufflen(scmd)); | |
2163 | return 1; | |
2164 | } | |
2165 | ||
2166 | /* Check if we need to build a native SG list. */ | |
2167 | if (base_is_prp_possible(ioc, pcie_device, | |
2168 | scmd, sges_left) == 0) { | |
2169 | /* We built a native SG list, just return. */ | |
2170 | goto out; | |
2171 | } | |
2172 | ||
2173 | /* | |
2174 | * Build native NVMe PRP. | |
2175 | */ | |
2176 | base_make_prp_nvme(ioc, scmd, mpi_request, | |
2177 | smid, sges_left); | |
2178 | ||
2179 | return 0; | |
2180 | out: | |
2181 | scsi_dma_unmap(scmd); | |
2182 | return 1; | |
2183 | } | |
f92363d1 SR |
2184 | |
2185 | /** | |
2186 | * _base_add_sg_single_ieee - add sg element for IEEE format | |
2187 | * @paddr: virtual address for SGE | |
2188 | * @flags: SGE flags | |
2189 | * @chain_offset: number of 128 byte elements from start of segment | |
2190 | * @length: data transfer length | |
2191 | * @dma_addr: Physical address | |
f92363d1 SR |
2192 | */ |
2193 | static void | |
2194 | _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length, | |
2195 | dma_addr_t dma_addr) | |
2196 | { | |
2197 | Mpi25IeeeSgeChain64_t *sgel = paddr; | |
2198 | ||
2199 | sgel->Flags = flags; | |
2200 | sgel->NextChainOffset = chain_offset; | |
2201 | sgel->Length = cpu_to_le32(length); | |
2202 | sgel->Address = cpu_to_le64(dma_addr); | |
2203 | } | |
2204 | ||
2205 | /** | |
2206 | * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format | |
2207 | * @ioc: per adapter object | |
2208 | * @paddr: virtual address for SGE | |
2209 | * | |
2210 | * Create a zero length scatter gather entry to insure the IOCs hardware has | |
2211 | * something to use if the target device goes brain dead and tries | |
2212 | * to send data even when none is asked for. | |
f92363d1 SR |
2213 | */ |
2214 | static void | |
2215 | _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr) | |
2216 | { | |
2217 | u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | | |
2218 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | | |
2219 | MPI25_IEEE_SGE_FLAGS_END_OF_LIST); | |
b130b0d5 | 2220 | |
f92363d1 SR |
2221 | _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1); |
2222 | } | |
2223 | ||
471ef9d4 SR |
2224 | /** |
2225 | * _base_build_sg_scmd - main sg creation routine | |
016d5c35 | 2226 | * pcie_device is unused here! |
471ef9d4 SR |
2227 | * @ioc: per adapter object |
2228 | * @scmd: scsi command | |
2229 | * @smid: system request message index | |
016d5c35 | 2230 | * @unused: unused pcie_device pointer |
471ef9d4 SR |
2231 | * Context: none. |
2232 | * | |
2233 | * The main routine that builds scatter gather table from a given | |
2234 | * scsi request sent via the .queuecommand main handler. | |
2235 | * | |
4beb4867 | 2236 | * Return: 0 success, anything else error |
471ef9d4 SR |
2237 | */ |
2238 | static int | |
2239 | _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc, | |
016d5c35 | 2240 | struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *unused) |
471ef9d4 SR |
2241 | { |
2242 | Mpi2SCSIIORequest_t *mpi_request; | |
2243 | dma_addr_t chain_dma; | |
2244 | struct scatterlist *sg_scmd; | |
2245 | void *sg_local, *chain; | |
2246 | u32 chain_offset; | |
2247 | u32 chain_length; | |
2248 | u32 chain_flags; | |
2249 | int sges_left; | |
2250 | u32 sges_in_segment; | |
2251 | u32 sgl_flags; | |
2252 | u32 sgl_flags_last_element; | |
2253 | u32 sgl_flags_end_buffer; | |
2254 | struct chain_tracker *chain_req; | |
2255 | ||
2256 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
2257 | ||
2258 | /* init scatter gather flags */ | |
2259 | sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT; | |
2260 | if (scmd->sc_data_direction == DMA_TO_DEVICE) | |
2261 | sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC; | |
2262 | sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT) | |
2263 | << MPI2_SGE_FLAGS_SHIFT; | |
2264 | sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT | | |
2265 | MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST) | |
2266 | << MPI2_SGE_FLAGS_SHIFT; | |
2267 | sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; | |
2268 | ||
2269 | sg_scmd = scsi_sglist(scmd); | |
2270 | sges_left = scsi_dma_map(scmd); | |
2271 | if (sges_left < 0) { | |
2272 | sdev_printk(KERN_ERR, scmd->device, | |
2273 | "pci_map_sg failed: request for %d bytes!\n", | |
2274 | scsi_bufflen(scmd)); | |
2275 | return -ENOMEM; | |
2276 | } | |
2277 | ||
2278 | sg_local = &mpi_request->SGL; | |
2279 | sges_in_segment = ioc->max_sges_in_main_message; | |
2280 | if (sges_left <= sges_in_segment) | |
2281 | goto fill_in_last_segment; | |
2282 | ||
2283 | mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) + | |
2284 | (sges_in_segment * ioc->sge_size))/4; | |
2285 | ||
2286 | /* fill in main message segment when there is a chain following */ | |
2287 | while (sges_in_segment) { | |
2288 | if (sges_in_segment == 1) | |
2289 | ioc->base_add_sg_single(sg_local, | |
2290 | sgl_flags_last_element | sg_dma_len(sg_scmd), | |
2291 | sg_dma_address(sg_scmd)); | |
2292 | else | |
2293 | ioc->base_add_sg_single(sg_local, sgl_flags | | |
2294 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
2295 | sg_scmd = sg_next(sg_scmd); | |
2296 | sg_local += ioc->sge_size; | |
2297 | sges_left--; | |
2298 | sges_in_segment--; | |
2299 | } | |
2300 | ||
2301 | /* initializing the chain flags and pointers */ | |
2302 | chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT; | |
dbec4c90 | 2303 | chain_req = _base_get_chain_buffer_tracker(ioc, scmd); |
471ef9d4 SR |
2304 | if (!chain_req) |
2305 | return -1; | |
2306 | chain = chain_req->chain_buffer; | |
2307 | chain_dma = chain_req->chain_buffer_dma; | |
2308 | do { | |
2309 | sges_in_segment = (sges_left <= | |
2310 | ioc->max_sges_in_chain_message) ? sges_left : | |
2311 | ioc->max_sges_in_chain_message; | |
2312 | chain_offset = (sges_left == sges_in_segment) ? | |
2313 | 0 : (sges_in_segment * ioc->sge_size)/4; | |
2314 | chain_length = sges_in_segment * ioc->sge_size; | |
2315 | if (chain_offset) { | |
2316 | chain_offset = chain_offset << | |
2317 | MPI2_SGE_CHAIN_OFFSET_SHIFT; | |
2318 | chain_length += ioc->sge_size; | |
2319 | } | |
2320 | ioc->base_add_sg_single(sg_local, chain_flags | chain_offset | | |
2321 | chain_length, chain_dma); | |
2322 | sg_local = chain; | |
2323 | if (!chain_offset) | |
2324 | goto fill_in_last_segment; | |
2325 | ||
2326 | /* fill in chain segments */ | |
2327 | while (sges_in_segment) { | |
2328 | if (sges_in_segment == 1) | |
2329 | ioc->base_add_sg_single(sg_local, | |
2330 | sgl_flags_last_element | | |
2331 | sg_dma_len(sg_scmd), | |
2332 | sg_dma_address(sg_scmd)); | |
2333 | else | |
2334 | ioc->base_add_sg_single(sg_local, sgl_flags | | |
2335 | sg_dma_len(sg_scmd), | |
2336 | sg_dma_address(sg_scmd)); | |
2337 | sg_scmd = sg_next(sg_scmd); | |
2338 | sg_local += ioc->sge_size; | |
2339 | sges_left--; | |
2340 | sges_in_segment--; | |
2341 | } | |
2342 | ||
dbec4c90 | 2343 | chain_req = _base_get_chain_buffer_tracker(ioc, scmd); |
471ef9d4 SR |
2344 | if (!chain_req) |
2345 | return -1; | |
2346 | chain = chain_req->chain_buffer; | |
2347 | chain_dma = chain_req->chain_buffer_dma; | |
2348 | } while (1); | |
2349 | ||
2350 | ||
2351 | fill_in_last_segment: | |
2352 | ||
2353 | /* fill the last segment */ | |
2354 | while (sges_left) { | |
2355 | if (sges_left == 1) | |
2356 | ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer | | |
2357 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
2358 | else | |
2359 | ioc->base_add_sg_single(sg_local, sgl_flags | | |
2360 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
2361 | sg_scmd = sg_next(sg_scmd); | |
2362 | sg_local += ioc->sge_size; | |
2363 | sges_left--; | |
2364 | } | |
2365 | ||
2366 | return 0; | |
2367 | } | |
2368 | ||
f92363d1 SR |
2369 | /** |
2370 | * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format | |
2371 | * @ioc: per adapter object | |
2372 | * @scmd: scsi command | |
2373 | * @smid: system request message index | |
016d5c35 SPS |
2374 | * @pcie_device: Pointer to pcie_device. If set, the pcie native sgl will be |
2375 | * constructed on need. | |
f92363d1 SR |
2376 | * Context: none. |
2377 | * | |
2378 | * The main routine that builds scatter gather table from a given | |
2379 | * scsi request sent via the .queuecommand main handler. | |
2380 | * | |
4beb4867 | 2381 | * Return: 0 success, anything else error |
f92363d1 SR |
2382 | */ |
2383 | static int | |
2384 | _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc, | |
016d5c35 | 2385 | struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device) |
f92363d1 | 2386 | { |
016d5c35 | 2387 | Mpi25SCSIIORequest_t *mpi_request; |
f92363d1 SR |
2388 | dma_addr_t chain_dma; |
2389 | struct scatterlist *sg_scmd; | |
2390 | void *sg_local, *chain; | |
2391 | u32 chain_offset; | |
2392 | u32 chain_length; | |
f92363d1 SR |
2393 | int sges_left; |
2394 | u32 sges_in_segment; | |
2395 | u8 simple_sgl_flags; | |
2396 | u8 simple_sgl_flags_last; | |
2397 | u8 chain_sgl_flags; | |
2398 | struct chain_tracker *chain_req; | |
2399 | ||
2400 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
2401 | ||
2402 | /* init scatter gather flags */ | |
2403 | simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | | |
2404 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; | |
2405 | simple_sgl_flags_last = simple_sgl_flags | | |
2406 | MPI25_IEEE_SGE_FLAGS_END_OF_LIST; | |
2407 | chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | | |
2408 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; | |
2409 | ||
016d5c35 SPS |
2410 | /* Check if we need to build a native SG list. */ |
2411 | if ((pcie_device) && (_base_check_pcie_native_sgl(ioc, mpi_request, | |
2412 | smid, scmd, pcie_device) == 0)) { | |
2413 | /* We built a native SG list, just return. */ | |
2414 | return 0; | |
2415 | } | |
2416 | ||
f92363d1 SR |
2417 | sg_scmd = scsi_sglist(scmd); |
2418 | sges_left = scsi_dma_map(scmd); | |
62f5c74c | 2419 | if (sges_left < 0) { |
f92363d1 SR |
2420 | sdev_printk(KERN_ERR, scmd->device, |
2421 | "pci_map_sg failed: request for %d bytes!\n", | |
2422 | scsi_bufflen(scmd)); | |
2423 | return -ENOMEM; | |
2424 | } | |
2425 | ||
2426 | sg_local = &mpi_request->SGL; | |
2427 | sges_in_segment = (ioc->request_sz - | |
016d5c35 | 2428 | offsetof(Mpi25SCSIIORequest_t, SGL))/ioc->sge_size_ieee; |
f92363d1 SR |
2429 | if (sges_left <= sges_in_segment) |
2430 | goto fill_in_last_segment; | |
2431 | ||
2432 | mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) + | |
016d5c35 | 2433 | (offsetof(Mpi25SCSIIORequest_t, SGL)/ioc->sge_size_ieee); |
f92363d1 SR |
2434 | |
2435 | /* fill in main message segment when there is a chain following */ | |
2436 | while (sges_in_segment > 1) { | |
2437 | _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, | |
2438 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
2439 | sg_scmd = sg_next(sg_scmd); | |
2440 | sg_local += ioc->sge_size_ieee; | |
2441 | sges_left--; | |
2442 | sges_in_segment--; | |
2443 | } | |
2444 | ||
25ef16d0 | 2445 | /* initializing the pointers */ |
dbec4c90 | 2446 | chain_req = _base_get_chain_buffer_tracker(ioc, scmd); |
f92363d1 SR |
2447 | if (!chain_req) |
2448 | return -1; | |
2449 | chain = chain_req->chain_buffer; | |
2450 | chain_dma = chain_req->chain_buffer_dma; | |
2451 | do { | |
2452 | sges_in_segment = (sges_left <= | |
2453 | ioc->max_sges_in_chain_message) ? sges_left : | |
2454 | ioc->max_sges_in_chain_message; | |
2455 | chain_offset = (sges_left == sges_in_segment) ? | |
2456 | 0 : sges_in_segment; | |
2457 | chain_length = sges_in_segment * ioc->sge_size_ieee; | |
2458 | if (chain_offset) | |
2459 | chain_length += ioc->sge_size_ieee; | |
2460 | _base_add_sg_single_ieee(sg_local, chain_sgl_flags, | |
2461 | chain_offset, chain_length, chain_dma); | |
2462 | ||
2463 | sg_local = chain; | |
2464 | if (!chain_offset) | |
2465 | goto fill_in_last_segment; | |
2466 | ||
2467 | /* fill in chain segments */ | |
2468 | while (sges_in_segment) { | |
2469 | _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, | |
2470 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
2471 | sg_scmd = sg_next(sg_scmd); | |
2472 | sg_local += ioc->sge_size_ieee; | |
2473 | sges_left--; | |
2474 | sges_in_segment--; | |
2475 | } | |
2476 | ||
dbec4c90 | 2477 | chain_req = _base_get_chain_buffer_tracker(ioc, scmd); |
f92363d1 SR |
2478 | if (!chain_req) |
2479 | return -1; | |
2480 | chain = chain_req->chain_buffer; | |
2481 | chain_dma = chain_req->chain_buffer_dma; | |
2482 | } while (1); | |
2483 | ||
2484 | ||
2485 | fill_in_last_segment: | |
2486 | ||
2487 | /* fill the last segment */ | |
62f5c74c | 2488 | while (sges_left > 0) { |
f92363d1 SR |
2489 | if (sges_left == 1) |
2490 | _base_add_sg_single_ieee(sg_local, | |
2491 | simple_sgl_flags_last, 0, sg_dma_len(sg_scmd), | |
2492 | sg_dma_address(sg_scmd)); | |
2493 | else | |
2494 | _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, | |
2495 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
2496 | sg_scmd = sg_next(sg_scmd); | |
2497 | sg_local += ioc->sge_size_ieee; | |
2498 | sges_left--; | |
2499 | } | |
2500 | ||
2501 | return 0; | |
2502 | } | |
2503 | ||
2504 | /** | |
2505 | * _base_build_sg_ieee - build generic sg for IEEE format | |
2506 | * @ioc: per adapter object | |
2507 | * @psge: virtual address for SGE | |
2508 | * @data_out_dma: physical address for WRITES | |
2509 | * @data_out_sz: data xfer size for WRITES | |
2510 | * @data_in_dma: physical address for READS | |
2511 | * @data_in_sz: data xfer size for READS | |
f92363d1 SR |
2512 | */ |
2513 | static void | |
2514 | _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge, | |
2515 | dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, | |
2516 | size_t data_in_sz) | |
2517 | { | |
2518 | u8 sgl_flags; | |
2519 | ||
2520 | if (!data_out_sz && !data_in_sz) { | |
2521 | _base_build_zero_len_sge_ieee(ioc, psge); | |
2522 | return; | |
2523 | } | |
2524 | ||
2525 | if (data_out_sz && data_in_sz) { | |
2526 | /* WRITE sgel first */ | |
2527 | sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | | |
2528 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; | |
2529 | _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, | |
2530 | data_out_dma); | |
2531 | ||
2532 | /* incr sgel */ | |
2533 | psge += ioc->sge_size_ieee; | |
2534 | ||
2535 | /* READ sgel last */ | |
2536 | sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; | |
2537 | _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, | |
2538 | data_in_dma); | |
2539 | } else if (data_out_sz) /* WRITE */ { | |
2540 | sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | | |
2541 | MPI25_IEEE_SGE_FLAGS_END_OF_LIST | | |
2542 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; | |
2543 | _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, | |
2544 | data_out_dma); | |
2545 | } else if (data_in_sz) /* READ */ { | |
2546 | sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | | |
2547 | MPI25_IEEE_SGE_FLAGS_END_OF_LIST | | |
2548 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; | |
2549 | _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, | |
2550 | data_in_dma); | |
2551 | } | |
2552 | } | |
2553 | ||
2554 | #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10)) | |
2555 | ||
2556 | /** | |
2557 | * _base_config_dma_addressing - set dma addressing | |
2558 | * @ioc: per adapter object | |
2559 | * @pdev: PCI device struct | |
2560 | * | |
4beb4867 | 2561 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
2562 | */ |
2563 | static int | |
2564 | _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev) | |
2565 | { | |
2566 | struct sysinfo s; | |
9b05c91a SR |
2567 | u64 consistent_dma_mask; |
2568 | ||
0448f019 SPS |
2569 | if (ioc->is_mcpu_endpoint) |
2570 | goto try_32bit; | |
2571 | ||
9b05c91a SR |
2572 | if (ioc->dma_mask) |
2573 | consistent_dma_mask = DMA_BIT_MASK(64); | |
2574 | else | |
2575 | consistent_dma_mask = DMA_BIT_MASK(32); | |
f92363d1 SR |
2576 | |
2577 | if (sizeof(dma_addr_t) > 4) { | |
2578 | const uint64_t required_mask = | |
2579 | dma_get_required_mask(&pdev->dev); | |
2580 | if ((required_mask > DMA_BIT_MASK(32)) && | |
2581 | !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && | |
9b05c91a | 2582 | !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) { |
f92363d1 SR |
2583 | ioc->base_add_sg_single = &_base_add_sg_single_64; |
2584 | ioc->sge_size = sizeof(Mpi2SGESimple64_t); | |
9b05c91a | 2585 | ioc->dma_mask = 64; |
f92363d1 SR |
2586 | goto out; |
2587 | } | |
2588 | } | |
2589 | ||
0448f019 | 2590 | try_32bit: |
f92363d1 SR |
2591 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) |
2592 | && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { | |
2593 | ioc->base_add_sg_single = &_base_add_sg_single_32; | |
2594 | ioc->sge_size = sizeof(Mpi2SGESimple32_t); | |
9b05c91a | 2595 | ioc->dma_mask = 32; |
f92363d1 SR |
2596 | } else |
2597 | return -ENODEV; | |
2598 | ||
2599 | out: | |
2600 | si_meminfo(&s); | |
2601 | pr_info(MPT3SAS_FMT | |
9b05c91a SR |
2602 | "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n", |
2603 | ioc->name, ioc->dma_mask, convert_to_kb(s.totalram)); | |
2604 | ||
2605 | return 0; | |
2606 | } | |
f92363d1 | 2607 | |
9b05c91a SR |
2608 | static int |
2609 | _base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc, | |
2610 | struct pci_dev *pdev) | |
2611 | { | |
2612 | if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { | |
2613 | if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) | |
2614 | return -ENODEV; | |
2615 | } | |
f92363d1 SR |
2616 | return 0; |
2617 | } | |
2618 | ||
2619 | /** | |
2620 | * _base_check_enable_msix - checks MSIX capabable. | |
2621 | * @ioc: per adapter object | |
2622 | * | |
2623 | * Check to see if card is capable of MSIX, and set number | |
2624 | * of available msix vectors | |
2625 | */ | |
2626 | static int | |
2627 | _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc) | |
2628 | { | |
2629 | int base; | |
2630 | u16 message_control; | |
2631 | ||
42081173 SR |
2632 | /* Check whether controller SAS2008 B0 controller, |
2633 | * if it is SAS2008 B0 controller use IO-APIC instead of MSIX | |
2634 | */ | |
2635 | if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 && | |
2636 | ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) { | |
2637 | return -EINVAL; | |
2638 | } | |
2639 | ||
f92363d1 SR |
2640 | base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX); |
2641 | if (!base) { | |
2642 | dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n", | |
2643 | ioc->name)); | |
2644 | return -EINVAL; | |
2645 | } | |
2646 | ||
2647 | /* get msix vector count */ | |
42081173 SR |
2648 | /* NUMA_IO not supported for older controllers */ |
2649 | if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 || | |
2650 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 || | |
2651 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 || | |
2652 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 || | |
2653 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 || | |
2654 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 || | |
2655 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2) | |
2656 | ioc->msix_vector_count = 1; | |
2657 | else { | |
2658 | pci_read_config_word(ioc->pdev, base + 2, &message_control); | |
2659 | ioc->msix_vector_count = (message_control & 0x3FF) + 1; | |
2660 | } | |
f92363d1 SR |
2661 | dinitprintk(ioc, pr_info(MPT3SAS_FMT |
2662 | "msix is supported, vector_count(%d)\n", | |
2663 | ioc->name, ioc->msix_vector_count)); | |
2664 | return 0; | |
2665 | } | |
2666 | ||
2667 | /** | |
2668 | * _base_free_irq - free irq | |
2669 | * @ioc: per adapter object | |
2670 | * | |
2671 | * Freeing respective reply_queue from the list. | |
2672 | */ | |
2673 | static void | |
2674 | _base_free_irq(struct MPT3SAS_ADAPTER *ioc) | |
2675 | { | |
2676 | struct adapter_reply_queue *reply_q, *next; | |
2677 | ||
2678 | if (list_empty(&ioc->reply_queue_list)) | |
2679 | return; | |
2680 | ||
2681 | list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) { | |
2682 | list_del(&reply_q->list); | |
1d55abc0 HR |
2683 | free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index), |
2684 | reply_q); | |
f92363d1 SR |
2685 | kfree(reply_q); |
2686 | } | |
2687 | } | |
2688 | ||
2689 | /** | |
2690 | * _base_request_irq - request irq | |
2691 | * @ioc: per adapter object | |
2692 | * @index: msix index into vector table | |
f92363d1 SR |
2693 | * |
2694 | * Inserting respective reply_queue into the list. | |
2695 | */ | |
2696 | static int | |
1d55abc0 | 2697 | _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index) |
f92363d1 | 2698 | { |
1d55abc0 | 2699 | struct pci_dev *pdev = ioc->pdev; |
f92363d1 SR |
2700 | struct adapter_reply_queue *reply_q; |
2701 | int r; | |
2702 | ||
2703 | reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL); | |
2704 | if (!reply_q) { | |
2705 | pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n", | |
2706 | ioc->name, (int)sizeof(struct adapter_reply_queue)); | |
2707 | return -ENOMEM; | |
2708 | } | |
2709 | reply_q->ioc = ioc; | |
2710 | reply_q->msix_index = index; | |
14b3114d | 2711 | |
f92363d1 SR |
2712 | atomic_set(&reply_q->busy, 0); |
2713 | if (ioc->msix_enable) | |
2714 | snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d", | |
c84b06a4 | 2715 | ioc->driver_name, ioc->id, index); |
f92363d1 SR |
2716 | else |
2717 | snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d", | |
c84b06a4 | 2718 | ioc->driver_name, ioc->id); |
1d55abc0 HR |
2719 | r = request_irq(pci_irq_vector(pdev, index), _base_interrupt, |
2720 | IRQF_SHARED, reply_q->name, reply_q); | |
f92363d1 SR |
2721 | if (r) { |
2722 | pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n", | |
1d55abc0 | 2723 | reply_q->name, pci_irq_vector(pdev, index)); |
da3cec25 | 2724 | kfree(reply_q); |
f92363d1 SR |
2725 | return -EBUSY; |
2726 | } | |
2727 | ||
2728 | INIT_LIST_HEAD(&reply_q->list); | |
2729 | list_add_tail(&reply_q->list, &ioc->reply_queue_list); | |
2730 | return 0; | |
2731 | } | |
2732 | ||
2733 | /** | |
2734 | * _base_assign_reply_queues - assigning msix index for each cpu | |
2735 | * @ioc: per adapter object | |
2736 | * | |
2737 | * The enduser would need to set the affinity via /proc/irq/#/smp_affinity | |
2738 | * | |
2739 | * It would nice if we could call irq_set_affinity, however it is not | |
2740 | * an exported symbol | |
2741 | */ | |
2742 | static void | |
2743 | _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc) | |
2744 | { | |
91b265bf | 2745 | unsigned int cpu, nr_cpus, nr_msix, index = 0; |
14b3114d | 2746 | struct adapter_reply_queue *reply_q; |
f92363d1 SR |
2747 | |
2748 | if (!_base_is_controller_msix_enabled(ioc)) | |
2749 | return; | |
2750 | ||
2751 | memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz); | |
2752 | ||
91b265bf MP |
2753 | nr_cpus = num_online_cpus(); |
2754 | nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count, | |
2755 | ioc->facts.MaxMSIxVectors); | |
2756 | if (!nr_msix) | |
2757 | return; | |
f92363d1 | 2758 | |
1d55abc0 HR |
2759 | if (smp_affinity_enable) { |
2760 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { | |
2761 | const cpumask_t *mask = pci_irq_get_affinity(ioc->pdev, | |
2762 | reply_q->msix_index); | |
2763 | if (!mask) { | |
2764 | pr_warn(MPT3SAS_FMT "no affinity for msi %x\n", | |
2765 | ioc->name, reply_q->msix_index); | |
2766 | continue; | |
2767 | } | |
2768 | ||
4a8842de TH |
2769 | for_each_cpu_and(cpu, mask, cpu_online_mask) { |
2770 | if (cpu >= ioc->cpu_msix_table_sz) | |
2771 | break; | |
1d55abc0 | 2772 | ioc->cpu_msix_table[cpu] = reply_q->msix_index; |
4a8842de | 2773 | } |
1d55abc0 HR |
2774 | } |
2775 | return; | |
2776 | } | |
91b265bf MP |
2777 | cpu = cpumask_first(cpu_online_mask); |
2778 | ||
14b3114d SR |
2779 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { |
2780 | ||
91b265bf MP |
2781 | unsigned int i, group = nr_cpus / nr_msix; |
2782 | ||
14b3114d SR |
2783 | if (cpu >= nr_cpus) |
2784 | break; | |
2785 | ||
91b265bf MP |
2786 | if (index < nr_cpus % nr_msix) |
2787 | group++; | |
2788 | ||
2789 | for (i = 0 ; i < group ; i++) { | |
1d55abc0 | 2790 | ioc->cpu_msix_table[cpu] = reply_q->msix_index; |
91b265bf | 2791 | cpu = cpumask_next(cpu, cpu_online_mask); |
f92363d1 | 2792 | } |
91b265bf | 2793 | index++; |
14b3114d | 2794 | } |
f92363d1 SR |
2795 | } |
2796 | ||
2797 | /** | |
2798 | * _base_disable_msix - disables msix | |
2799 | * @ioc: per adapter object | |
2800 | * | |
2801 | */ | |
2802 | static void | |
2803 | _base_disable_msix(struct MPT3SAS_ADAPTER *ioc) | |
2804 | { | |
2805 | if (!ioc->msix_enable) | |
2806 | return; | |
2807 | pci_disable_msix(ioc->pdev); | |
2808 | ioc->msix_enable = 0; | |
2809 | } | |
2810 | ||
2811 | /** | |
2812 | * _base_enable_msix - enables msix, failback to io_apic | |
2813 | * @ioc: per adapter object | |
2814 | * | |
2815 | */ | |
2816 | static int | |
2817 | _base_enable_msix(struct MPT3SAS_ADAPTER *ioc) | |
2818 | { | |
f92363d1 | 2819 | int r; |
bb350661 | 2820 | int i, local_max_msix_vectors; |
f92363d1 | 2821 | u8 try_msix = 0; |
1d55abc0 | 2822 | unsigned int irq_flags = PCI_IRQ_MSIX; |
f92363d1 | 2823 | |
f92363d1 SR |
2824 | if (msix_disable == -1 || msix_disable == 0) |
2825 | try_msix = 1; | |
2826 | ||
2827 | if (!try_msix) | |
2828 | goto try_ioapic; | |
2829 | ||
2830 | if (_base_check_enable_msix(ioc) != 0) | |
2831 | goto try_ioapic; | |
2832 | ||
2833 | ioc->reply_queue_count = min_t(int, ioc->cpu_count, | |
1d55abc0 | 2834 | ioc->msix_vector_count); |
f92363d1 | 2835 | |
9c500060 SR |
2836 | printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores" |
2837 | ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count, | |
2838 | ioc->cpu_count, max_msix_vectors); | |
2839 | ||
9b05c91a | 2840 | if (!ioc->rdpq_array_enable && max_msix_vectors == -1) |
06f5f976 | 2841 | local_max_msix_vectors = (reset_devices) ? 1 : 8; |
bb350661 SPS |
2842 | else |
2843 | local_max_msix_vectors = max_msix_vectors; | |
9b05c91a | 2844 | |
1d55abc0 | 2845 | if (local_max_msix_vectors > 0) |
bb350661 | 2846 | ioc->reply_queue_count = min_t(int, local_max_msix_vectors, |
9c500060 | 2847 | ioc->reply_queue_count); |
1d55abc0 | 2848 | else if (local_max_msix_vectors == 0) |
9b05c91a | 2849 | goto try_ioapic; |
9c500060 | 2850 | |
64038301 SPS |
2851 | if (ioc->msix_vector_count < ioc->cpu_count) |
2852 | smp_affinity_enable = 0; | |
2853 | ||
1d55abc0 HR |
2854 | if (smp_affinity_enable) |
2855 | irq_flags |= PCI_IRQ_AFFINITY; | |
f92363d1 | 2856 | |
1d55abc0 HR |
2857 | r = pci_alloc_irq_vectors(ioc->pdev, 1, ioc->reply_queue_count, |
2858 | irq_flags); | |
2859 | if (r < 0) { | |
f92363d1 | 2860 | dfailprintk(ioc, pr_info(MPT3SAS_FMT |
1d55abc0 | 2861 | "pci_alloc_irq_vectors failed (r=%d) !!!\n", |
f92363d1 | 2862 | ioc->name, r)); |
f92363d1 SR |
2863 | goto try_ioapic; |
2864 | } | |
2865 | ||
2866 | ioc->msix_enable = 1; | |
1d55abc0 HR |
2867 | ioc->reply_queue_count = r; |
2868 | for (i = 0; i < ioc->reply_queue_count; i++) { | |
2869 | r = _base_request_irq(ioc, i); | |
f92363d1 SR |
2870 | if (r) { |
2871 | _base_free_irq(ioc); | |
2872 | _base_disable_msix(ioc); | |
f92363d1 SR |
2873 | goto try_ioapic; |
2874 | } | |
2875 | } | |
2876 | ||
f92363d1 SR |
2877 | return 0; |
2878 | ||
2879 | /* failback to io_apic interrupt routing */ | |
2880 | try_ioapic: | |
2881 | ||
9b05c91a | 2882 | ioc->reply_queue_count = 1; |
1d55abc0 HR |
2883 | r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY); |
2884 | if (r < 0) { | |
2885 | dfailprintk(ioc, pr_info(MPT3SAS_FMT | |
2886 | "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n", | |
2887 | ioc->name, r)); | |
2888 | } else | |
2889 | r = _base_request_irq(ioc, 0); | |
f92363d1 SR |
2890 | |
2891 | return r; | |
2892 | } | |
2893 | ||
580d4e31 SR |
2894 | /** |
2895 | * mpt3sas_base_unmap_resources - free controller resources | |
2896 | * @ioc: per adapter object | |
2897 | */ | |
8bbb1cf6 | 2898 | static void |
580d4e31 SR |
2899 | mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc) |
2900 | { | |
2901 | struct pci_dev *pdev = ioc->pdev; | |
2902 | ||
2903 | dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n", | |
2904 | ioc->name, __func__)); | |
2905 | ||
2906 | _base_free_irq(ioc); | |
2907 | _base_disable_msix(ioc); | |
2908 | ||
2b48be65 C |
2909 | kfree(ioc->replyPostRegisterIndex); |
2910 | ioc->replyPostRegisterIndex = NULL; | |
2911 | ||
580d4e31 SR |
2912 | |
2913 | if (ioc->chip_phys) { | |
2914 | iounmap(ioc->chip); | |
2915 | ioc->chip_phys = 0; | |
2916 | } | |
2917 | ||
2918 | if (pci_is_enabled(pdev)) { | |
2919 | pci_release_selected_regions(ioc->pdev, ioc->bars); | |
2920 | pci_disable_pcie_error_reporting(pdev); | |
2921 | pci_disable_device(pdev); | |
2922 | } | |
2923 | } | |
2924 | ||
f92363d1 SR |
2925 | /** |
2926 | * mpt3sas_base_map_resources - map in controller resources (io/irq/memap) | |
2927 | * @ioc: per adapter object | |
2928 | * | |
4beb4867 | 2929 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
2930 | */ |
2931 | int | |
2932 | mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc) | |
2933 | { | |
2934 | struct pci_dev *pdev = ioc->pdev; | |
2935 | u32 memap_sz; | |
2936 | u32 pio_sz; | |
2937 | int i, r = 0; | |
2938 | u64 pio_chip = 0; | |
6f9e09fd | 2939 | phys_addr_t chip_phys = 0; |
f92363d1 SR |
2940 | struct adapter_reply_queue *reply_q; |
2941 | ||
2942 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", | |
2943 | ioc->name, __func__)); | |
2944 | ||
2945 | ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
2946 | if (pci_enable_device_mem(pdev)) { | |
2947 | pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n", | |
2948 | ioc->name); | |
cf9bd21a | 2949 | ioc->bars = 0; |
f92363d1 SR |
2950 | return -ENODEV; |
2951 | } | |
2952 | ||
2953 | ||
2954 | if (pci_request_selected_regions(pdev, ioc->bars, | |
c84b06a4 | 2955 | ioc->driver_name)) { |
f92363d1 SR |
2956 | pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n", |
2957 | ioc->name); | |
cf9bd21a | 2958 | ioc->bars = 0; |
f92363d1 SR |
2959 | r = -ENODEV; |
2960 | goto out_fail; | |
2961 | } | |
2962 | ||
2963 | /* AER (Advanced Error Reporting) hooks */ | |
2964 | pci_enable_pcie_error_reporting(pdev); | |
2965 | ||
2966 | pci_set_master(pdev); | |
2967 | ||
2968 | ||
2969 | if (_base_config_dma_addressing(ioc, pdev) != 0) { | |
2970 | pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n", | |
2971 | ioc->name, pci_name(pdev)); | |
2972 | r = -ENODEV; | |
2973 | goto out_fail; | |
2974 | } | |
2975 | ||
5aeeb78a SR |
2976 | for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) && |
2977 | (!memap_sz || !pio_sz); i++) { | |
f92363d1 SR |
2978 | if (pci_resource_flags(pdev, i) & IORESOURCE_IO) { |
2979 | if (pio_sz) | |
2980 | continue; | |
2981 | pio_chip = (u64)pci_resource_start(pdev, i); | |
2982 | pio_sz = pci_resource_len(pdev, i); | |
2983 | } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { | |
2984 | if (memap_sz) | |
2985 | continue; | |
2986 | ioc->chip_phys = pci_resource_start(pdev, i); | |
6f9e09fd | 2987 | chip_phys = ioc->chip_phys; |
f92363d1 SR |
2988 | memap_sz = pci_resource_len(pdev, i); |
2989 | ioc->chip = ioremap(ioc->chip_phys, memap_sz); | |
f92363d1 SR |
2990 | } |
2991 | } | |
2992 | ||
5aeeb78a SR |
2993 | if (ioc->chip == NULL) { |
2994 | pr_err(MPT3SAS_FMT "unable to map adapter memory! " | |
2995 | " or resource not found\n", ioc->name); | |
2996 | r = -EINVAL; | |
2997 | goto out_fail; | |
2998 | } | |
2999 | ||
f92363d1 | 3000 | _base_mask_interrupts(ioc); |
9b05c91a | 3001 | |
98c56ad3 | 3002 | r = _base_get_ioc_facts(ioc); |
9b05c91a SR |
3003 | if (r) |
3004 | goto out_fail; | |
3005 | ||
3006 | if (!ioc->rdpq_array_enable_assigned) { | |
3007 | ioc->rdpq_array_enable = ioc->rdpq_array_capable; | |
3008 | ioc->rdpq_array_enable_assigned = 1; | |
3009 | } | |
3010 | ||
f92363d1 SR |
3011 | r = _base_enable_msix(ioc); |
3012 | if (r) | |
3013 | goto out_fail; | |
3014 | ||
fb77bb53 SR |
3015 | /* Use the Combined reply queue feature only for SAS3 C0 & higher |
3016 | * revision HBAs and also only when reply queue count is greater than 8 | |
3017 | */ | |
2b48be65 | 3018 | if (ioc->combined_reply_queue) { |
fb77bb53 SR |
3019 | /* Determine the Supplemental Reply Post Host Index Registers |
3020 | * Addresse. Supplemental Reply Post Host Index Registers | |
3021 | * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and | |
3022 | * each register is at offset bytes of | |
3023 | * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one. | |
3024 | */ | |
3025 | ioc->replyPostRegisterIndex = kcalloc( | |
0bb337c9 | 3026 | ioc->combined_reply_index_count, |
fb77bb53 SR |
3027 | sizeof(resource_size_t *), GFP_KERNEL); |
3028 | if (!ioc->replyPostRegisterIndex) { | |
3029 | dfailprintk(ioc, printk(MPT3SAS_FMT | |
3030 | "allocation for reply Post Register Index failed!!!\n", | |
3031 | ioc->name)); | |
3032 | r = -ENOMEM; | |
3033 | goto out_fail; | |
3034 | } | |
3035 | ||
0bb337c9 | 3036 | for (i = 0; i < ioc->combined_reply_index_count; i++) { |
fb77bb53 | 3037 | ioc->replyPostRegisterIndex[i] = (resource_size_t *) |
cf6bf971 | 3038 | ((u8 __force *)&ioc->chip->Doorbell + |
fb77bb53 SR |
3039 | MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET + |
3040 | (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET)); | |
3041 | } | |
2b48be65 | 3042 | } |
fb77bb53 | 3043 | |
ce7c6c9e GE |
3044 | if (ioc->is_warpdrive) { |
3045 | ioc->reply_post_host_index[0] = (resource_size_t __iomem *) | |
3046 | &ioc->chip->ReplyPostHostIndex; | |
3047 | ||
3048 | for (i = 1; i < ioc->cpu_msix_table_sz; i++) | |
3049 | ioc->reply_post_host_index[i] = | |
3050 | (resource_size_t __iomem *) | |
3051 | ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1) | |
3052 | * 4))); | |
3053 | } | |
3054 | ||
f92363d1 SR |
3055 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) |
3056 | pr_info(MPT3SAS_FMT "%s: IRQ %d\n", | |
3057 | reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" : | |
1d55abc0 HR |
3058 | "IO-APIC enabled"), |
3059 | pci_irq_vector(ioc->pdev, reply_q->msix_index)); | |
f92363d1 | 3060 | |
6f9e09fd AB |
3061 | pr_info(MPT3SAS_FMT "iomem(%pap), mapped(0x%p), size(%d)\n", |
3062 | ioc->name, &chip_phys, ioc->chip, memap_sz); | |
f92363d1 SR |
3063 | pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n", |
3064 | ioc->name, (unsigned long long)pio_chip, pio_sz); | |
3065 | ||
3066 | /* Save PCI configuration state for recovery from PCI AER/EEH errors */ | |
3067 | pci_save_state(pdev); | |
3068 | return 0; | |
3069 | ||
3070 | out_fail: | |
580d4e31 | 3071 | mpt3sas_base_unmap_resources(ioc); |
f92363d1 SR |
3072 | return r; |
3073 | } | |
3074 | ||
3075 | /** | |
3076 | * mpt3sas_base_get_msg_frame - obtain request mf pointer | |
3077 | * @ioc: per adapter object | |
3078 | * @smid: system request message index(smid zero is invalid) | |
3079 | * | |
4beb4867 | 3080 | * Return: virt pointer to message frame. |
f92363d1 SR |
3081 | */ |
3082 | void * | |
3083 | mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
3084 | { | |
3085 | return (void *)(ioc->request + (smid * ioc->request_sz)); | |
3086 | } | |
3087 | ||
3088 | /** | |
3089 | * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr | |
3090 | * @ioc: per adapter object | |
3091 | * @smid: system request message index | |
3092 | * | |
4beb4867 | 3093 | * Return: virt pointer to sense buffer. |
f92363d1 SR |
3094 | */ |
3095 | void * | |
3096 | mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
3097 | { | |
3098 | return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE)); | |
3099 | } | |
3100 | ||
3101 | /** | |
3102 | * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr | |
3103 | * @ioc: per adapter object | |
3104 | * @smid: system request message index | |
3105 | * | |
4beb4867 | 3106 | * Return: phys pointer to the low 32bit address of the sense buffer. |
f92363d1 SR |
3107 | */ |
3108 | __le32 | |
3109 | mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
3110 | { | |
3111 | return cpu_to_le32(ioc->sense_dma + ((smid - 1) * | |
3112 | SCSI_SENSE_BUFFERSIZE)); | |
3113 | } | |
3114 | ||
016d5c35 SPS |
3115 | /** |
3116 | * mpt3sas_base_get_pcie_sgl - obtain a PCIe SGL virt addr | |
3117 | * @ioc: per adapter object | |
3118 | * @smid: system request message index | |
3119 | * | |
4beb4867 | 3120 | * Return: virt pointer to a PCIe SGL. |
016d5c35 SPS |
3121 | */ |
3122 | void * | |
3123 | mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
3124 | { | |
dbec4c90 | 3125 | return (void *)(ioc->pcie_sg_lookup[smid - 1].pcie_sgl); |
016d5c35 SPS |
3126 | } |
3127 | ||
3128 | /** | |
3129 | * mpt3sas_base_get_pcie_sgl_dma - obtain a PCIe SGL dma addr | |
3130 | * @ioc: per adapter object | |
3131 | * @smid: system request message index | |
3132 | * | |
4beb4867 | 3133 | * Return: phys pointer to the address of the PCIe buffer. |
016d5c35 | 3134 | */ |
d8335ae2 | 3135 | dma_addr_t |
016d5c35 SPS |
3136 | mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid) |
3137 | { | |
dbec4c90 | 3138 | return ioc->pcie_sg_lookup[smid - 1].pcie_sgl_dma; |
016d5c35 SPS |
3139 | } |
3140 | ||
f92363d1 SR |
3141 | /** |
3142 | * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address | |
3143 | * @ioc: per adapter object | |
3144 | * @phys_addr: lower 32 physical addr of the reply | |
3145 | * | |
3146 | * Converts 32bit lower physical addr into a virt address. | |
3147 | */ | |
3148 | void * | |
3149 | mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr) | |
3150 | { | |
3151 | if (!phys_addr) | |
3152 | return NULL; | |
3153 | return ioc->reply + (phys_addr - (u32)ioc->reply_dma); | |
3154 | } | |
3155 | ||
03d1fb3a SS |
3156 | static inline u8 |
3157 | _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc) | |
3158 | { | |
3159 | return ioc->cpu_msix_table[raw_smp_processor_id()]; | |
3160 | } | |
3161 | ||
f92363d1 SR |
3162 | /** |
3163 | * mpt3sas_base_get_smid - obtain a free smid from internal queue | |
3164 | * @ioc: per adapter object | |
3165 | * @cb_idx: callback index | |
3166 | * | |
4beb4867 | 3167 | * Return: smid (zero is invalid) |
f92363d1 SR |
3168 | */ |
3169 | u16 | |
3170 | mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) | |
3171 | { | |
3172 | unsigned long flags; | |
3173 | struct request_tracker *request; | |
3174 | u16 smid; | |
3175 | ||
3176 | spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); | |
3177 | if (list_empty(&ioc->internal_free_list)) { | |
3178 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
3179 | pr_err(MPT3SAS_FMT "%s: smid not available\n", | |
3180 | ioc->name, __func__); | |
3181 | return 0; | |
3182 | } | |
3183 | ||
3184 | request = list_entry(ioc->internal_free_list.next, | |
3185 | struct request_tracker, tracker_list); | |
3186 | request->cb_idx = cb_idx; | |
3187 | smid = request->smid; | |
3188 | list_del(&request->tracker_list); | |
3189 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
3190 | return smid; | |
3191 | } | |
3192 | ||
3193 | /** | |
3194 | * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue | |
3195 | * @ioc: per adapter object | |
3196 | * @cb_idx: callback index | |
3197 | * @scmd: pointer to scsi command object | |
3198 | * | |
4beb4867 | 3199 | * Return: smid (zero is invalid) |
f92363d1 SR |
3200 | */ |
3201 | u16 | |
3202 | mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx, | |
3203 | struct scsi_cmnd *scmd) | |
3204 | { | |
dbec4c90 SPS |
3205 | struct scsiio_tracker *request = scsi_cmd_priv(scmd); |
3206 | unsigned int tag = scmd->request->tag; | |
f92363d1 SR |
3207 | u16 smid; |
3208 | ||
dbec4c90 | 3209 | smid = tag + 1; |
f92363d1 | 3210 | request->cb_idx = cb_idx; |
03d1fb3a | 3211 | request->msix_io = _base_get_msix_index(ioc); |
dbec4c90 SPS |
3212 | request->smid = smid; |
3213 | INIT_LIST_HEAD(&request->chain_list); | |
f92363d1 SR |
3214 | return smid; |
3215 | } | |
3216 | ||
3217 | /** | |
3218 | * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue | |
3219 | * @ioc: per adapter object | |
3220 | * @cb_idx: callback index | |
3221 | * | |
4beb4867 | 3222 | * Return: smid (zero is invalid) |
f92363d1 SR |
3223 | */ |
3224 | u16 | |
3225 | mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) | |
3226 | { | |
3227 | unsigned long flags; | |
3228 | struct request_tracker *request; | |
3229 | u16 smid; | |
3230 | ||
3231 | spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); | |
3232 | if (list_empty(&ioc->hpr_free_list)) { | |
3233 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
3234 | return 0; | |
3235 | } | |
3236 | ||
3237 | request = list_entry(ioc->hpr_free_list.next, | |
3238 | struct request_tracker, tracker_list); | |
3239 | request->cb_idx = cb_idx; | |
3240 | smid = request->smid; | |
3241 | list_del(&request->tracker_list); | |
3242 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
3243 | return smid; | |
3244 | } | |
3245 | ||
6a2d4618 HR |
3246 | static void |
3247 | _base_recovery_check(struct MPT3SAS_ADAPTER *ioc) | |
3248 | { | |
3249 | /* | |
3250 | * See _wait_for_commands_to_complete() call with regards to this code. | |
3251 | */ | |
3252 | if (ioc->shost_recovery && ioc->pending_io_count) { | |
c84b023a | 3253 | ioc->pending_io_count = scsi_host_busy(ioc->shost); |
272e253c | 3254 | if (ioc->pending_io_count == 0) |
6a2d4618 | 3255 | wake_up(&ioc->reset_wq); |
6a2d4618 HR |
3256 | } |
3257 | } | |
3258 | ||
dbec4c90 SPS |
3259 | void mpt3sas_base_clear_st(struct MPT3SAS_ADAPTER *ioc, |
3260 | struct scsiio_tracker *st) | |
3261 | { | |
3262 | if (WARN_ON(st->smid == 0)) | |
3263 | return; | |
3264 | st->cb_idx = 0xFF; | |
3265 | st->direct_io = 0; | |
93204b78 | 3266 | atomic_set(&ioc->chain_lookup[st->smid - 1].chain_offset, 0); |
dbec4c90 SPS |
3267 | } |
3268 | ||
f92363d1 SR |
3269 | /** |
3270 | * mpt3sas_base_free_smid - put smid back on free_list | |
3271 | * @ioc: per adapter object | |
3272 | * @smid: system request message index | |
f92363d1 SR |
3273 | */ |
3274 | void | |
3275 | mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
3276 | { | |
3277 | unsigned long flags; | |
3278 | int i; | |
f92363d1 | 3279 | |
f92363d1 | 3280 | if (smid < ioc->hi_priority_smid) { |
dbec4c90 | 3281 | struct scsiio_tracker *st; |
f92363d1 | 3282 | |
dbec4c90 SPS |
3283 | st = _get_st_from_smid(ioc, smid); |
3284 | if (!st) { | |
3285 | _base_recovery_check(ioc); | |
3286 | return; | |
3287 | } | |
3288 | mpt3sas_base_clear_st(ioc, st); | |
6a2d4618 | 3289 | _base_recovery_check(ioc); |
f92363d1 | 3290 | return; |
dbec4c90 SPS |
3291 | } |
3292 | ||
3293 | spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); | |
3294 | if (smid < ioc->internal_smid) { | |
f92363d1 SR |
3295 | /* hi-priority */ |
3296 | i = smid - ioc->hi_priority_smid; | |
3297 | ioc->hpr_lookup[i].cb_idx = 0xFF; | |
3298 | list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list); | |
3299 | } else if (smid <= ioc->hba_queue_depth) { | |
3300 | /* internal queue */ | |
3301 | i = smid - ioc->internal_smid; | |
3302 | ioc->internal_lookup[i].cb_idx = 0xFF; | |
3303 | list_add(&ioc->internal_lookup[i].tracker_list, | |
3304 | &ioc->internal_free_list); | |
3305 | } | |
3306 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
3307 | } | |
3308 | ||
e5747439 SPS |
3309 | /** |
3310 | * _base_mpi_ep_writeq - 32 bit write to MMIO | |
3311 | * @b: data payload | |
3312 | * @addr: address in MMIO space | |
3313 | * @writeq_lock: spin lock | |
3314 | * | |
3315 | * This special handling for MPI EP to take care of 32 bit | |
3316 | * environment where its not quarenteed to send the entire word | |
3317 | * in one transfer. | |
3318 | */ | |
3319 | static inline void | |
3320 | _base_mpi_ep_writeq(__u64 b, volatile void __iomem *addr, | |
3321 | spinlock_t *writeq_lock) | |
3322 | { | |
3323 | unsigned long flags; | |
cf6bf971 | 3324 | __u64 data_out = b; |
e5747439 SPS |
3325 | |
3326 | spin_lock_irqsave(writeq_lock, flags); | |
3327 | writel((u32)(data_out), addr); | |
3328 | writel((u32)(data_out >> 32), (addr + 4)); | |
10ee1f22 | 3329 | mmiowb(); |
e5747439 SPS |
3330 | spin_unlock_irqrestore(writeq_lock, flags); |
3331 | } | |
3332 | ||
f92363d1 SR |
3333 | /** |
3334 | * _base_writeq - 64 bit write to MMIO | |
f92363d1 SR |
3335 | * @b: data payload |
3336 | * @addr: address in MMIO space | |
3337 | * @writeq_lock: spin lock | |
3338 | * | |
3339 | * Glue for handling an atomic 64 bit word to MMIO. This special handling takes | |
3340 | * care of 32 bit environment where its not quarenteed to send the entire word | |
3341 | * in one transfer. | |
3342 | */ | |
3343 | #if defined(writeq) && defined(CONFIG_64BIT) | |
3344 | static inline void | |
3345 | _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) | |
3346 | { | |
cf6bf971 | 3347 | writeq(b, addr); |
f92363d1 SR |
3348 | } |
3349 | #else | |
3350 | static inline void | |
3351 | _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) | |
3352 | { | |
e5747439 | 3353 | _base_mpi_ep_writeq(b, addr, writeq_lock); |
f92363d1 SR |
3354 | } |
3355 | #endif | |
3356 | ||
e5747439 SPS |
3357 | /** |
3358 | * _base_put_smid_mpi_ep_scsi_io - send SCSI_IO request to firmware | |
3359 | * @ioc: per adapter object | |
3360 | * @smid: system request message index | |
3361 | * @handle: device handle | |
e5747439 SPS |
3362 | */ |
3363 | static void | |
3364 | _base_put_smid_mpi_ep_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle) | |
3365 | { | |
3366 | Mpi2RequestDescriptorUnion_t descriptor; | |
3367 | u64 *request = (u64 *)&descriptor; | |
3368 | void *mpi_req_iomem; | |
3369 | __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid); | |
3370 | ||
3371 | _clone_sg_entries(ioc, (void *) mfp, smid); | |
cf6bf971 | 3372 | mpi_req_iomem = (void __force *)ioc->chip + |
e5747439 SPS |
3373 | MPI_FRAME_START_OFFSET + (smid * ioc->request_sz); |
3374 | _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp, | |
3375 | ioc->request_sz); | |
3376 | descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; | |
3377 | descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc); | |
3378 | descriptor.SCSIIO.SMID = cpu_to_le16(smid); | |
3379 | descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); | |
3380 | descriptor.SCSIIO.LMID = 0; | |
3381 | _base_mpi_ep_writeq(*request, &ioc->chip->RequestDescriptorPostLow, | |
3382 | &ioc->scsi_lookup_lock); | |
3383 | } | |
3384 | ||
f92363d1 | 3385 | /** |
81c16f83 | 3386 | * _base_put_smid_scsi_io - send SCSI_IO request to firmware |
f92363d1 SR |
3387 | * @ioc: per adapter object |
3388 | * @smid: system request message index | |
3389 | * @handle: device handle | |
f92363d1 | 3390 | */ |
81c16f83 SPS |
3391 | static void |
3392 | _base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle) | |
f92363d1 SR |
3393 | { |
3394 | Mpi2RequestDescriptorUnion_t descriptor; | |
3395 | u64 *request = (u64 *)&descriptor; | |
3396 | ||
3397 | ||
3398 | descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; | |
3399 | descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc); | |
3400 | descriptor.SCSIIO.SMID = cpu_to_le16(smid); | |
3401 | descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); | |
3402 | descriptor.SCSIIO.LMID = 0; | |
3403 | _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, | |
3404 | &ioc->scsi_lookup_lock); | |
3405 | } | |
3406 | ||
3407 | /** | |
40114bde | 3408 | * mpt3sas_base_put_smid_fast_path - send fast path request to firmware |
f92363d1 SR |
3409 | * @ioc: per adapter object |
3410 | * @smid: system request message index | |
3411 | * @handle: device handle | |
f92363d1 | 3412 | */ |
40114bde SP |
3413 | void |
3414 | mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid, | |
f92363d1 SR |
3415 | u16 handle) |
3416 | { | |
3417 | Mpi2RequestDescriptorUnion_t descriptor; | |
3418 | u64 *request = (u64 *)&descriptor; | |
3419 | ||
3420 | descriptor.SCSIIO.RequestFlags = | |
3421 | MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; | |
3422 | descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc); | |
3423 | descriptor.SCSIIO.SMID = cpu_to_le16(smid); | |
3424 | descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); | |
3425 | descriptor.SCSIIO.LMID = 0; | |
3426 | _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, | |
3427 | &ioc->scsi_lookup_lock); | |
3428 | } | |
3429 | ||
3430 | /** | |
40114bde | 3431 | * mpt3sas_base_put_smid_hi_priority - send Task Management request to firmware |
f92363d1 SR |
3432 | * @ioc: per adapter object |
3433 | * @smid: system request message index | |
03d1fb3a | 3434 | * @msix_task: msix_task will be same as msix of IO incase of task abort else 0. |
f92363d1 | 3435 | */ |
40114bde SP |
3436 | void |
3437 | mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid, | |
03d1fb3a | 3438 | u16 msix_task) |
f92363d1 SR |
3439 | { |
3440 | Mpi2RequestDescriptorUnion_t descriptor; | |
e5747439 SPS |
3441 | void *mpi_req_iomem; |
3442 | u64 *request; | |
3443 | ||
3444 | if (ioc->is_mcpu_endpoint) { | |
e5747439 SPS |
3445 | __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid); |
3446 | ||
e5747439 | 3447 | /* TBD 256 is offset within sys register. */ |
cf6bf971 C |
3448 | mpi_req_iomem = (void __force *)ioc->chip |
3449 | + MPI_FRAME_START_OFFSET | |
e5747439 SPS |
3450 | + (smid * ioc->request_sz); |
3451 | _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp, | |
3452 | ioc->request_sz); | |
3453 | } | |
3454 | ||
3455 | request = (u64 *)&descriptor; | |
f92363d1 SR |
3456 | |
3457 | descriptor.HighPriority.RequestFlags = | |
3458 | MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; | |
03d1fb3a | 3459 | descriptor.HighPriority.MSIxIndex = msix_task; |
f92363d1 SR |
3460 | descriptor.HighPriority.SMID = cpu_to_le16(smid); |
3461 | descriptor.HighPriority.LMID = 0; | |
3462 | descriptor.HighPriority.Reserved1 = 0; | |
e5747439 SPS |
3463 | if (ioc->is_mcpu_endpoint) |
3464 | _base_mpi_ep_writeq(*request, | |
3465 | &ioc->chip->RequestDescriptorPostLow, | |
3466 | &ioc->scsi_lookup_lock); | |
3467 | else | |
3468 | _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, | |
3469 | &ioc->scsi_lookup_lock); | |
f92363d1 SR |
3470 | } |
3471 | ||
aff39e61 | 3472 | /** |
40114bde | 3473 | * mpt3sas_base_put_smid_nvme_encap - send NVMe encapsulated request to |
aff39e61 SPS |
3474 | * firmware |
3475 | * @ioc: per adapter object | |
3476 | * @smid: system request message index | |
aff39e61 | 3477 | */ |
40114bde SP |
3478 | void |
3479 | mpt3sas_base_put_smid_nvme_encap(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
aff39e61 SPS |
3480 | { |
3481 | Mpi2RequestDescriptorUnion_t descriptor; | |
3482 | u64 *request = (u64 *)&descriptor; | |
3483 | ||
3484 | descriptor.Default.RequestFlags = | |
3485 | MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED; | |
3486 | descriptor.Default.MSIxIndex = _base_get_msix_index(ioc); | |
3487 | descriptor.Default.SMID = cpu_to_le16(smid); | |
3488 | descriptor.Default.LMID = 0; | |
3489 | descriptor.Default.DescriptorTypeDependent = 0; | |
3490 | _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, | |
3491 | &ioc->scsi_lookup_lock); | |
3492 | } | |
3493 | ||
f92363d1 | 3494 | /** |
40114bde | 3495 | * mpt3sas_base_put_smid_default - Default, primarily used for config pages |
f92363d1 SR |
3496 | * @ioc: per adapter object |
3497 | * @smid: system request message index | |
f92363d1 | 3498 | */ |
40114bde SP |
3499 | void |
3500 | mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
f92363d1 SR |
3501 | { |
3502 | Mpi2RequestDescriptorUnion_t descriptor; | |
e5747439 SPS |
3503 | void *mpi_req_iomem; |
3504 | u64 *request; | |
e5747439 SPS |
3505 | |
3506 | if (ioc->is_mcpu_endpoint) { | |
3507 | __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid); | |
3508 | ||
e5747439 SPS |
3509 | _clone_sg_entries(ioc, (void *) mfp, smid); |
3510 | /* TBD 256 is offset within sys register */ | |
cf6bf971 | 3511 | mpi_req_iomem = (void __force *)ioc->chip + |
e5747439 SPS |
3512 | MPI_FRAME_START_OFFSET + (smid * ioc->request_sz); |
3513 | _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp, | |
3514 | ioc->request_sz); | |
3515 | } | |
3516 | request = (u64 *)&descriptor; | |
f92363d1 SR |
3517 | descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; |
3518 | descriptor.Default.MSIxIndex = _base_get_msix_index(ioc); | |
3519 | descriptor.Default.SMID = cpu_to_le16(smid); | |
3520 | descriptor.Default.LMID = 0; | |
3521 | descriptor.Default.DescriptorTypeDependent = 0; | |
e5747439 SPS |
3522 | if (ioc->is_mcpu_endpoint) |
3523 | _base_mpi_ep_writeq(*request, | |
3524 | &ioc->chip->RequestDescriptorPostLow, | |
3525 | &ioc->scsi_lookup_lock); | |
3526 | else | |
3527 | _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, | |
3528 | &ioc->scsi_lookup_lock); | |
f92363d1 SR |
3529 | } |
3530 | ||
1117b31a | 3531 | /** |
989e43c7 | 3532 | * _base_display_OEMs_branding - Display branding string |
1117b31a | 3533 | * @ioc: per adapter object |
1117b31a SR |
3534 | */ |
3535 | static void | |
989e43c7 | 3536 | _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc) |
1117b31a SR |
3537 | { |
3538 | if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL) | |
3539 | return; | |
3540 | ||
989e43c7 SR |
3541 | switch (ioc->pdev->subsystem_vendor) { |
3542 | case PCI_VENDOR_ID_INTEL: | |
3543 | switch (ioc->pdev->device) { | |
3544 | case MPI2_MFGPAGE_DEVID_SAS2008: | |
3545 | switch (ioc->pdev->subsystem_device) { | |
3546 | case MPT2SAS_INTEL_RMS2LL080_SSDID: | |
3547 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3548 | MPT2SAS_INTEL_RMS2LL080_BRANDING); | |
3549 | break; | |
3550 | case MPT2SAS_INTEL_RMS2LL040_SSDID: | |
3551 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3552 | MPT2SAS_INTEL_RMS2LL040_BRANDING); | |
3553 | break; | |
3554 | case MPT2SAS_INTEL_SSD910_SSDID: | |
3555 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3556 | MPT2SAS_INTEL_SSD910_BRANDING); | |
3557 | break; | |
3558 | default: | |
3559 | pr_info(MPT3SAS_FMT | |
3560 | "Intel(R) Controller: Subsystem ID: 0x%X\n", | |
3561 | ioc->name, ioc->pdev->subsystem_device); | |
3562 | break; | |
3563 | } | |
3564 | case MPI2_MFGPAGE_DEVID_SAS2308_2: | |
3565 | switch (ioc->pdev->subsystem_device) { | |
3566 | case MPT2SAS_INTEL_RS25GB008_SSDID: | |
3567 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3568 | MPT2SAS_INTEL_RS25GB008_BRANDING); | |
3569 | break; | |
3570 | case MPT2SAS_INTEL_RMS25JB080_SSDID: | |
3571 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3572 | MPT2SAS_INTEL_RMS25JB080_BRANDING); | |
3573 | break; | |
3574 | case MPT2SAS_INTEL_RMS25JB040_SSDID: | |
3575 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3576 | MPT2SAS_INTEL_RMS25JB040_BRANDING); | |
3577 | break; | |
3578 | case MPT2SAS_INTEL_RMS25KB080_SSDID: | |
3579 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3580 | MPT2SAS_INTEL_RMS25KB080_BRANDING); | |
3581 | break; | |
3582 | case MPT2SAS_INTEL_RMS25KB040_SSDID: | |
3583 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3584 | MPT2SAS_INTEL_RMS25KB040_BRANDING); | |
3585 | break; | |
3586 | case MPT2SAS_INTEL_RMS25LB040_SSDID: | |
3587 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3588 | MPT2SAS_INTEL_RMS25LB040_BRANDING); | |
3589 | break; | |
3590 | case MPT2SAS_INTEL_RMS25LB080_SSDID: | |
3591 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3592 | MPT2SAS_INTEL_RMS25LB080_BRANDING); | |
3593 | break; | |
3594 | default: | |
3595 | pr_info(MPT3SAS_FMT | |
3596 | "Intel(R) Controller: Subsystem ID: 0x%X\n", | |
3597 | ioc->name, ioc->pdev->subsystem_device); | |
3598 | break; | |
3599 | } | |
3600 | case MPI25_MFGPAGE_DEVID_SAS3008: | |
3601 | switch (ioc->pdev->subsystem_device) { | |
3602 | case MPT3SAS_INTEL_RMS3JC080_SSDID: | |
3603 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3604 | MPT3SAS_INTEL_RMS3JC080_BRANDING); | |
3605 | break; | |
3606 | ||
3607 | case MPT3SAS_INTEL_RS3GC008_SSDID: | |
3608 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3609 | MPT3SAS_INTEL_RS3GC008_BRANDING); | |
3610 | break; | |
3611 | case MPT3SAS_INTEL_RS3FC044_SSDID: | |
3612 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3613 | MPT3SAS_INTEL_RS3FC044_BRANDING); | |
3614 | break; | |
3615 | case MPT3SAS_INTEL_RS3UC080_SSDID: | |
3616 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3617 | MPT3SAS_INTEL_RS3UC080_BRANDING); | |
3618 | break; | |
3619 | default: | |
3620 | pr_info(MPT3SAS_FMT | |
3621 | "Intel(R) Controller: Subsystem ID: 0x%X\n", | |
3622 | ioc->name, ioc->pdev->subsystem_device); | |
3623 | break; | |
3624 | } | |
1117b31a SR |
3625 | break; |
3626 | default: | |
3627 | pr_info(MPT3SAS_FMT | |
989e43c7 SR |
3628 | "Intel(R) Controller: Subsystem ID: 0x%X\n", |
3629 | ioc->name, ioc->pdev->subsystem_device); | |
1117b31a SR |
3630 | break; |
3631 | } | |
3632 | break; | |
989e43c7 SR |
3633 | case PCI_VENDOR_ID_DELL: |
3634 | switch (ioc->pdev->device) { | |
3635 | case MPI2_MFGPAGE_DEVID_SAS2008: | |
3636 | switch (ioc->pdev->subsystem_device) { | |
3637 | case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID: | |
3638 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3639 | MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING); | |
3640 | break; | |
3641 | case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID: | |
3642 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3643 | MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING); | |
3644 | break; | |
3645 | case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID: | |
3646 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3647 | MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING); | |
3648 | break; | |
3649 | case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID: | |
3650 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3651 | MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING); | |
3652 | break; | |
3653 | case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID: | |
3654 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3655 | MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING); | |
3656 | break; | |
3657 | case MPT2SAS_DELL_PERC_H200_SSDID: | |
3658 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3659 | MPT2SAS_DELL_PERC_H200_BRANDING); | |
3660 | break; | |
3661 | case MPT2SAS_DELL_6GBPS_SAS_SSDID: | |
3662 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3663 | MPT2SAS_DELL_6GBPS_SAS_BRANDING); | |
3664 | break; | |
3665 | default: | |
3666 | pr_info(MPT3SAS_FMT | |
3667 | "Dell 6Gbps HBA: Subsystem ID: 0x%X\n", | |
3668 | ioc->name, ioc->pdev->subsystem_device); | |
3669 | break; | |
3670 | } | |
3671 | break; | |
3672 | case MPI25_MFGPAGE_DEVID_SAS3008: | |
3673 | switch (ioc->pdev->subsystem_device) { | |
3674 | case MPT3SAS_DELL_12G_HBA_SSDID: | |
3675 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3676 | MPT3SAS_DELL_12G_HBA_BRANDING); | |
3677 | break; | |
3678 | default: | |
3679 | pr_info(MPT3SAS_FMT | |
3680 | "Dell 12Gbps HBA: Subsystem ID: 0x%X\n", | |
3681 | ioc->name, ioc->pdev->subsystem_device); | |
3682 | break; | |
3683 | } | |
fb84dfc4 SR |
3684 | break; |
3685 | default: | |
3686 | pr_info(MPT3SAS_FMT | |
989e43c7 | 3687 | "Dell HBA: Subsystem ID: 0x%X\n", ioc->name, |
fb84dfc4 SR |
3688 | ioc->pdev->subsystem_device); |
3689 | break; | |
3690 | } | |
3691 | break; | |
989e43c7 SR |
3692 | case PCI_VENDOR_ID_CISCO: |
3693 | switch (ioc->pdev->device) { | |
3694 | case MPI25_MFGPAGE_DEVID_SAS3008: | |
3695 | switch (ioc->pdev->subsystem_device) { | |
3696 | case MPT3SAS_CISCO_12G_8E_HBA_SSDID: | |
3697 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3698 | MPT3SAS_CISCO_12G_8E_HBA_BRANDING); | |
3699 | break; | |
3700 | case MPT3SAS_CISCO_12G_8I_HBA_SSDID: | |
3701 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3702 | MPT3SAS_CISCO_12G_8I_HBA_BRANDING); | |
3703 | break; | |
3704 | case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: | |
3705 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3706 | MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); | |
3707 | break; | |
3708 | default: | |
3709 | pr_info(MPT3SAS_FMT | |
3710 | "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", | |
3711 | ioc->name, ioc->pdev->subsystem_device); | |
3712 | break; | |
3713 | } | |
d8eb4a47 | 3714 | break; |
989e43c7 SR |
3715 | case MPI25_MFGPAGE_DEVID_SAS3108_1: |
3716 | switch (ioc->pdev->subsystem_device) { | |
3717 | case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: | |
3718 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
d8eb4a47 | 3719 | MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); |
989e43c7 SR |
3720 | break; |
3721 | case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID: | |
3722 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3723 | MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING | |
3724 | ); | |
3725 | break; | |
3726 | default: | |
3727 | pr_info(MPT3SAS_FMT | |
3728 | "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", | |
3729 | ioc->name, ioc->pdev->subsystem_device); | |
3730 | break; | |
3731 | } | |
38e4141e SR |
3732 | break; |
3733 | default: | |
3734 | pr_info(MPT3SAS_FMT | |
989e43c7 SR |
3735 | "Cisco SAS HBA: Subsystem ID: 0x%X\n", |
3736 | ioc->name, ioc->pdev->subsystem_device); | |
38e4141e SR |
3737 | break; |
3738 | } | |
3739 | break; | |
989e43c7 SR |
3740 | case MPT2SAS_HP_3PAR_SSVID: |
3741 | switch (ioc->pdev->device) { | |
3742 | case MPI2_MFGPAGE_DEVID_SAS2004: | |
3743 | switch (ioc->pdev->subsystem_device) { | |
3744 | case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID: | |
3745 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3746 | MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING); | |
3747 | break; | |
3748 | default: | |
3749 | pr_info(MPT3SAS_FMT | |
3750 | "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", | |
3751 | ioc->name, ioc->pdev->subsystem_device); | |
3752 | break; | |
3753 | } | |
3754 | case MPI2_MFGPAGE_DEVID_SAS2308_2: | |
3755 | switch (ioc->pdev->subsystem_device) { | |
3756 | case MPT2SAS_HP_2_4_INTERNAL_SSDID: | |
3757 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3758 | MPT2SAS_HP_2_4_INTERNAL_BRANDING); | |
3759 | break; | |
3760 | case MPT2SAS_HP_2_4_EXTERNAL_SSDID: | |
3761 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3762 | MPT2SAS_HP_2_4_EXTERNAL_BRANDING); | |
3763 | break; | |
3764 | case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID: | |
3765 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3766 | MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING); | |
3767 | break; | |
3768 | case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID: | |
3769 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3770 | MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING); | |
3771 | break; | |
3772 | default: | |
3773 | pr_info(MPT3SAS_FMT | |
3774 | "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", | |
3775 | ioc->name, ioc->pdev->subsystem_device); | |
3776 | break; | |
3777 | } | |
d8eb4a47 SR |
3778 | default: |
3779 | pr_info(MPT3SAS_FMT | |
989e43c7 SR |
3780 | "HP SAS HBA: Subsystem ID: 0x%X\n", |
3781 | ioc->name, ioc->pdev->subsystem_device); | |
d8eb4a47 SR |
3782 | break; |
3783 | } | |
38e4141e | 3784 | default: |
38e4141e SR |
3785 | break; |
3786 | } | |
3787 | } | |
fb84dfc4 | 3788 | |
3d29ed85 C |
3789 | /** |
3790 | * _base_display_fwpkg_version - sends FWUpload request to pull FWPkg | |
3791 | * version from FW Image Header. | |
3792 | * @ioc: per adapter object | |
3793 | * | |
4beb4867 | 3794 | * Return: 0 for success, non-zero for failure. |
3d29ed85 C |
3795 | */ |
3796 | static int | |
3797 | _base_display_fwpkg_version(struct MPT3SAS_ADAPTER *ioc) | |
3798 | { | |
3799 | Mpi2FWImageHeader_t *FWImgHdr; | |
3800 | Mpi25FWUploadRequest_t *mpi_request; | |
3801 | Mpi2FWUploadReply_t mpi_reply; | |
3802 | int r = 0; | |
3803 | void *fwpkg_data = NULL; | |
3804 | dma_addr_t fwpkg_data_dma; | |
3805 | u16 smid, ioc_status; | |
3806 | size_t data_length; | |
3807 | ||
3808 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3809 | __func__)); | |
3810 | ||
3811 | if (ioc->base_cmds.status & MPT3_CMD_PENDING) { | |
3812 | pr_err(MPT3SAS_FMT "%s: internal command already in use\n", | |
3813 | ioc->name, __func__); | |
3814 | return -EAGAIN; | |
3815 | } | |
3816 | ||
3817 | data_length = sizeof(Mpi2FWImageHeader_t); | |
3818 | fwpkg_data = pci_alloc_consistent(ioc->pdev, data_length, | |
3819 | &fwpkg_data_dma); | |
3820 | if (!fwpkg_data) { | |
3821 | pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", | |
3822 | ioc->name, __FILE__, __LINE__, __func__); | |
3823 | return -ENOMEM; | |
3824 | } | |
3825 | ||
3826 | smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); | |
3827 | if (!smid) { | |
3828 | pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", | |
3829 | ioc->name, __func__); | |
3830 | r = -EAGAIN; | |
3831 | goto out; | |
3832 | } | |
3833 | ||
3834 | ioc->base_cmds.status = MPT3_CMD_PENDING; | |
3835 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
3836 | ioc->base_cmds.smid = smid; | |
3837 | memset(mpi_request, 0, sizeof(Mpi25FWUploadRequest_t)); | |
3838 | mpi_request->Function = MPI2_FUNCTION_FW_UPLOAD; | |
3839 | mpi_request->ImageType = MPI2_FW_UPLOAD_ITYPE_FW_FLASH; | |
3840 | mpi_request->ImageSize = cpu_to_le32(data_length); | |
3841 | ioc->build_sg(ioc, &mpi_request->SGL, 0, 0, fwpkg_data_dma, | |
3842 | data_length); | |
3843 | init_completion(&ioc->base_cmds.done); | |
3844 | mpt3sas_base_put_smid_default(ioc, smid); | |
3845 | /* Wait for 15 seconds */ | |
3846 | wait_for_completion_timeout(&ioc->base_cmds.done, | |
3847 | FW_IMG_HDR_READ_TIMEOUT*HZ); | |
3848 | pr_info(MPT3SAS_FMT "%s: complete\n", | |
3849 | ioc->name, __func__); | |
3850 | if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { | |
3851 | pr_err(MPT3SAS_FMT "%s: timeout\n", | |
3852 | ioc->name, __func__); | |
3853 | _debug_dump_mf(mpi_request, | |
3854 | sizeof(Mpi25FWUploadRequest_t)/4); | |
3855 | r = -ETIME; | |
3856 | } else { | |
3857 | memset(&mpi_reply, 0, sizeof(Mpi2FWUploadReply_t)); | |
3858 | if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) { | |
3859 | memcpy(&mpi_reply, ioc->base_cmds.reply, | |
3860 | sizeof(Mpi2FWUploadReply_t)); | |
3861 | ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & | |
3862 | MPI2_IOCSTATUS_MASK; | |
3863 | if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { | |
3864 | FWImgHdr = (Mpi2FWImageHeader_t *)fwpkg_data; | |
3865 | if (FWImgHdr->PackageVersion.Word) { | |
3866 | pr_info(MPT3SAS_FMT "FW Package Version" | |
3867 | "(%02d.%02d.%02d.%02d)\n", | |
3868 | ioc->name, | |
3869 | FWImgHdr->PackageVersion.Struct.Major, | |
3870 | FWImgHdr->PackageVersion.Struct.Minor, | |
3871 | FWImgHdr->PackageVersion.Struct.Unit, | |
3872 | FWImgHdr->PackageVersion.Struct.Dev); | |
3873 | } | |
3874 | } else { | |
3875 | _debug_dump_mf(&mpi_reply, | |
3876 | sizeof(Mpi2FWUploadReply_t)/4); | |
3877 | } | |
3878 | } | |
3879 | } | |
3880 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; | |
3881 | out: | |
3882 | if (fwpkg_data) | |
3883 | pci_free_consistent(ioc->pdev, data_length, fwpkg_data, | |
3884 | fwpkg_data_dma); | |
3885 | return r; | |
3886 | } | |
3887 | ||
f92363d1 SR |
3888 | /** |
3889 | * _base_display_ioc_capabilities - Disply IOC's capabilities. | |
3890 | * @ioc: per adapter object | |
f92363d1 SR |
3891 | */ |
3892 | static void | |
3893 | _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc) | |
3894 | { | |
3895 | int i = 0; | |
3896 | char desc[16]; | |
3897 | u32 iounit_pg1_flags; | |
3898 | u32 bios_version; | |
3899 | ||
3900 | bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion); | |
3901 | strncpy(desc, ioc->manu_pg0.ChipName, 16); | |
3902 | pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\ | |
3903 | "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n", | |
3904 | ioc->name, desc, | |
3905 | (ioc->facts.FWVersion.Word & 0xFF000000) >> 24, | |
3906 | (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16, | |
3907 | (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8, | |
3908 | ioc->facts.FWVersion.Word & 0x000000FF, | |
3909 | ioc->pdev->revision, | |
3910 | (bios_version & 0xFF000000) >> 24, | |
3911 | (bios_version & 0x00FF0000) >> 16, | |
3912 | (bios_version & 0x0000FF00) >> 8, | |
3913 | bios_version & 0x000000FF); | |
3914 | ||
989e43c7 | 3915 | _base_display_OEMs_branding(ioc); |
1117b31a | 3916 | |
016d5c35 SPS |
3917 | if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) { |
3918 | pr_info("%sNVMe", i ? "," : ""); | |
3919 | i++; | |
3920 | } | |
3921 | ||
f92363d1 SR |
3922 | pr_info(MPT3SAS_FMT "Protocol=(", ioc->name); |
3923 | ||
3924 | if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) { | |
3925 | pr_info("Initiator"); | |
3926 | i++; | |
3927 | } | |
3928 | ||
3929 | if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) { | |
3930 | pr_info("%sTarget", i ? "," : ""); | |
3931 | i++; | |
3932 | } | |
3933 | ||
3934 | i = 0; | |
3935 | pr_info("), "); | |
3936 | pr_info("Capabilities=("); | |
3937 | ||
7786ab6a SR |
3938 | if (!ioc->hide_ir_msg) { |
3939 | if (ioc->facts.IOCCapabilities & | |
f92363d1 SR |
3940 | MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) { |
3941 | pr_info("Raid"); | |
3942 | i++; | |
7786ab6a | 3943 | } |
f92363d1 SR |
3944 | } |
3945 | ||
3946 | if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) { | |
3947 | pr_info("%sTLR", i ? "," : ""); | |
3948 | i++; | |
3949 | } | |
3950 | ||
3951 | if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) { | |
3952 | pr_info("%sMulticast", i ? "," : ""); | |
3953 | i++; | |
3954 | } | |
3955 | ||
3956 | if (ioc->facts.IOCCapabilities & | |
3957 | MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) { | |
3958 | pr_info("%sBIDI Target", i ? "," : ""); | |
3959 | i++; | |
3960 | } | |
3961 | ||
3962 | if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) { | |
3963 | pr_info("%sEEDP", i ? "," : ""); | |
3964 | i++; | |
3965 | } | |
3966 | ||
3967 | if (ioc->facts.IOCCapabilities & | |
3968 | MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) { | |
3969 | pr_info("%sSnapshot Buffer", i ? "," : ""); | |
3970 | i++; | |
3971 | } | |
3972 | ||
3973 | if (ioc->facts.IOCCapabilities & | |
3974 | MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) { | |
3975 | pr_info("%sDiag Trace Buffer", i ? "," : ""); | |
3976 | i++; | |
3977 | } | |
3978 | ||
3979 | if (ioc->facts.IOCCapabilities & | |
3980 | MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) { | |
3981 | pr_info("%sDiag Extended Buffer", i ? "," : ""); | |
3982 | i++; | |
3983 | } | |
3984 | ||
3985 | if (ioc->facts.IOCCapabilities & | |
3986 | MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) { | |
3987 | pr_info("%sTask Set Full", i ? "," : ""); | |
3988 | i++; | |
3989 | } | |
3990 | ||
3991 | iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); | |
3992 | if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) { | |
3993 | pr_info("%sNCQ", i ? "," : ""); | |
3994 | i++; | |
3995 | } | |
3996 | ||
3997 | pr_info(")\n"); | |
3998 | } | |
3999 | ||
4000 | /** | |
4001 | * mpt3sas_base_update_missing_delay - change the missing delay timers | |
4002 | * @ioc: per adapter object | |
4003 | * @device_missing_delay: amount of time till device is reported missing | |
4004 | * @io_missing_delay: interval IO is returned when there is a missing device | |
4005 | * | |
f92363d1 SR |
4006 | * Passed on the command line, this function will modify the device missing |
4007 | * delay, as well as the io missing delay. This should be called at driver | |
4008 | * load time. | |
4009 | */ | |
4010 | void | |
4011 | mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc, | |
4012 | u16 device_missing_delay, u8 io_missing_delay) | |
4013 | { | |
4014 | u16 dmd, dmd_new, dmd_orignal; | |
4015 | u8 io_missing_delay_original; | |
4016 | u16 sz; | |
4017 | Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL; | |
4018 | Mpi2ConfigReply_t mpi_reply; | |
4019 | u8 num_phys = 0; | |
4020 | u16 ioc_status; | |
4021 | ||
4022 | mpt3sas_config_get_number_hba_phys(ioc, &num_phys); | |
4023 | if (!num_phys) | |
4024 | return; | |
4025 | ||
4026 | sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys * | |
4027 | sizeof(Mpi2SasIOUnit1PhyData_t)); | |
4028 | sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL); | |
4029 | if (!sas_iounit_pg1) { | |
4030 | pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", | |
4031 | ioc->name, __FILE__, __LINE__, __func__); | |
4032 | goto out; | |
4033 | } | |
4034 | if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply, | |
4035 | sas_iounit_pg1, sz))) { | |
4036 | pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", | |
4037 | ioc->name, __FILE__, __LINE__, __func__); | |
4038 | goto out; | |
4039 | } | |
4040 | ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & | |
4041 | MPI2_IOCSTATUS_MASK; | |
4042 | if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { | |
4043 | pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", | |
4044 | ioc->name, __FILE__, __LINE__, __func__); | |
4045 | goto out; | |
4046 | } | |
4047 | ||
4048 | /* device missing delay */ | |
4049 | dmd = sas_iounit_pg1->ReportDeviceMissingDelay; | |
4050 | if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) | |
4051 | dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; | |
4052 | else | |
4053 | dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; | |
4054 | dmd_orignal = dmd; | |
4055 | if (device_missing_delay > 0x7F) { | |
4056 | dmd = (device_missing_delay > 0x7F0) ? 0x7F0 : | |
4057 | device_missing_delay; | |
4058 | dmd = dmd / 16; | |
4059 | dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16; | |
4060 | } else | |
4061 | dmd = device_missing_delay; | |
4062 | sas_iounit_pg1->ReportDeviceMissingDelay = dmd; | |
4063 | ||
4064 | /* io missing delay */ | |
4065 | io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay; | |
4066 | sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay; | |
4067 | ||
4068 | if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1, | |
4069 | sz)) { | |
4070 | if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) | |
4071 | dmd_new = (dmd & | |
4072 | MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; | |
4073 | else | |
4074 | dmd_new = | |
4075 | dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; | |
4076 | pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n", | |
4077 | ioc->name, dmd_orignal, dmd_new); | |
4078 | pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n", | |
4079 | ioc->name, io_missing_delay_original, | |
4080 | io_missing_delay); | |
4081 | ioc->device_missing_delay = dmd_new; | |
4082 | ioc->io_missing_delay = io_missing_delay; | |
4083 | } | |
4084 | ||
4085 | out: | |
4086 | kfree(sas_iounit_pg1); | |
4087 | } | |
4beb4867 | 4088 | |
f92363d1 SR |
4089 | /** |
4090 | * _base_static_config_pages - static start of day config pages | |
4091 | * @ioc: per adapter object | |
f92363d1 SR |
4092 | */ |
4093 | static void | |
4094 | _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc) | |
4095 | { | |
4096 | Mpi2ConfigReply_t mpi_reply; | |
4097 | u32 iounit_pg1_flags; | |
4098 | ||
c1a6c5ac | 4099 | ioc->nvme_abort_timeout = 30; |
f92363d1 SR |
4100 | mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0); |
4101 | if (ioc->ir_firmware) | |
4102 | mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply, | |
4103 | &ioc->manu_pg10); | |
4104 | ||
4105 | /* | |
4106 | * Ensure correct T10 PI operation if vendor left EEDPTagMode | |
4107 | * flag unset in NVDATA. | |
4108 | */ | |
4109 | mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11); | |
4110 | if (ioc->manu_pg11.EEDPTagMode == 0) { | |
4111 | pr_err("%s: overriding NVDATA EEDPTagMode setting\n", | |
4112 | ioc->name); | |
4113 | ioc->manu_pg11.EEDPTagMode &= ~0x3; | |
4114 | ioc->manu_pg11.EEDPTagMode |= 0x1; | |
4115 | mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply, | |
4116 | &ioc->manu_pg11); | |
4117 | } | |
c1a6c5ac C |
4118 | if (ioc->manu_pg11.AddlFlags2 & NVME_TASK_MNGT_CUSTOM_MASK) |
4119 | ioc->tm_custom_handling = 1; | |
4120 | else { | |
4121 | ioc->tm_custom_handling = 0; | |
4122 | if (ioc->manu_pg11.NVMeAbortTO < NVME_TASK_ABORT_MIN_TIMEOUT) | |
4123 | ioc->nvme_abort_timeout = NVME_TASK_ABORT_MIN_TIMEOUT; | |
4124 | else if (ioc->manu_pg11.NVMeAbortTO > | |
4125 | NVME_TASK_ABORT_MAX_TIMEOUT) | |
4126 | ioc->nvme_abort_timeout = NVME_TASK_ABORT_MAX_TIMEOUT; | |
4127 | else | |
4128 | ioc->nvme_abort_timeout = ioc->manu_pg11.NVMeAbortTO; | |
4129 | } | |
f92363d1 SR |
4130 | |
4131 | mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2); | |
4132 | mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3); | |
4133 | mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8); | |
4134 | mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0); | |
4135 | mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); | |
2d8ce8c9 | 4136 | mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8); |
f92363d1 SR |
4137 | _base_display_ioc_capabilities(ioc); |
4138 | ||
4139 | /* | |
4140 | * Enable task_set_full handling in iounit_pg1 when the | |
4141 | * facts capabilities indicate that its supported. | |
4142 | */ | |
4143 | iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); | |
4144 | if ((ioc->facts.IOCCapabilities & | |
4145 | MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING)) | |
4146 | iounit_pg1_flags &= | |
4147 | ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; | |
4148 | else | |
4149 | iounit_pg1_flags |= | |
4150 | MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; | |
4151 | ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags); | |
4152 | mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); | |
2d8ce8c9 SR |
4153 | |
4154 | if (ioc->iounit_pg8.NumSensors) | |
4155 | ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors; | |
f92363d1 SR |
4156 | } |
4157 | ||
22a923c3 C |
4158 | /** |
4159 | * mpt3sas_free_enclosure_list - release memory | |
4160 | * @ioc: per adapter object | |
4161 | * | |
4162 | * Free memory allocated during encloure add. | |
22a923c3 C |
4163 | */ |
4164 | void | |
4165 | mpt3sas_free_enclosure_list(struct MPT3SAS_ADAPTER *ioc) | |
4166 | { | |
4167 | struct _enclosure_node *enclosure_dev, *enclosure_dev_next; | |
4168 | ||
4169 | /* Free enclosure list */ | |
4170 | list_for_each_entry_safe(enclosure_dev, | |
4171 | enclosure_dev_next, &ioc->enclosure_list, list) { | |
4172 | list_del(&enclosure_dev->list); | |
4173 | kfree(enclosure_dev); | |
4174 | } | |
4175 | } | |
4176 | ||
f92363d1 SR |
4177 | /** |
4178 | * _base_release_memory_pools - release memory | |
4179 | * @ioc: per adapter object | |
4180 | * | |
4181 | * Free memory allocated from _base_allocate_memory_pools. | |
f92363d1 SR |
4182 | */ |
4183 | static void | |
4184 | _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) | |
4185 | { | |
9b05c91a | 4186 | int i = 0; |
93204b78 C |
4187 | int j = 0; |
4188 | struct chain_tracker *ct; | |
9b05c91a | 4189 | struct reply_post_struct *rps; |
f92363d1 SR |
4190 | |
4191 | dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
4192 | __func__)); | |
4193 | ||
4194 | if (ioc->request) { | |
4195 | pci_free_consistent(ioc->pdev, ioc->request_dma_sz, | |
4196 | ioc->request, ioc->request_dma); | |
4197 | dexitprintk(ioc, pr_info(MPT3SAS_FMT | |
4198 | "request_pool(0x%p): free\n", | |
4199 | ioc->name, ioc->request)); | |
4200 | ioc->request = NULL; | |
4201 | } | |
4202 | ||
4203 | if (ioc->sense) { | |
e9d98418 RP |
4204 | dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma); |
4205 | dma_pool_destroy(ioc->sense_dma_pool); | |
f92363d1 SR |
4206 | dexitprintk(ioc, pr_info(MPT3SAS_FMT |
4207 | "sense_pool(0x%p): free\n", | |
4208 | ioc->name, ioc->sense)); | |
4209 | ioc->sense = NULL; | |
4210 | } | |
4211 | ||
4212 | if (ioc->reply) { | |
e9d98418 RP |
4213 | dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma); |
4214 | dma_pool_destroy(ioc->reply_dma_pool); | |
f92363d1 SR |
4215 | dexitprintk(ioc, pr_info(MPT3SAS_FMT |
4216 | "reply_pool(0x%p): free\n", | |
4217 | ioc->name, ioc->reply)); | |
4218 | ioc->reply = NULL; | |
4219 | } | |
4220 | ||
4221 | if (ioc->reply_free) { | |
e9d98418 | 4222 | dma_pool_free(ioc->reply_free_dma_pool, ioc->reply_free, |
f92363d1 | 4223 | ioc->reply_free_dma); |
e9d98418 | 4224 | dma_pool_destroy(ioc->reply_free_dma_pool); |
f92363d1 SR |
4225 | dexitprintk(ioc, pr_info(MPT3SAS_FMT |
4226 | "reply_free_pool(0x%p): free\n", | |
4227 | ioc->name, ioc->reply_free)); | |
4228 | ioc->reply_free = NULL; | |
4229 | } | |
4230 | ||
9b05c91a SR |
4231 | if (ioc->reply_post) { |
4232 | do { | |
4233 | rps = &ioc->reply_post[i]; | |
4234 | if (rps->reply_post_free) { | |
e9d98418 | 4235 | dma_pool_free( |
9b05c91a SR |
4236 | ioc->reply_post_free_dma_pool, |
4237 | rps->reply_post_free, | |
4238 | rps->reply_post_free_dma); | |
4239 | dexitprintk(ioc, pr_info(MPT3SAS_FMT | |
4240 | "reply_post_free_pool(0x%p): free\n", | |
4241 | ioc->name, rps->reply_post_free)); | |
4242 | rps->reply_post_free = NULL; | |
4243 | } | |
4244 | } while (ioc->rdpq_array_enable && | |
4245 | (++i < ioc->reply_queue_count)); | |
cd33223b C |
4246 | if (ioc->reply_post_free_array && |
4247 | ioc->rdpq_array_enable) { | |
4248 | dma_pool_free(ioc->reply_post_free_array_dma_pool, | |
4249 | ioc->reply_post_free_array, | |
4250 | ioc->reply_post_free_array_dma); | |
4251 | ioc->reply_post_free_array = NULL; | |
4252 | } | |
4253 | dma_pool_destroy(ioc->reply_post_free_array_dma_pool); | |
e9d98418 | 4254 | dma_pool_destroy(ioc->reply_post_free_dma_pool); |
9b05c91a | 4255 | kfree(ioc->reply_post); |
f92363d1 SR |
4256 | } |
4257 | ||
016d5c35 SPS |
4258 | if (ioc->pcie_sgl_dma_pool) { |
4259 | for (i = 0; i < ioc->scsiio_depth; i++) { | |
dbec4c90 SPS |
4260 | dma_pool_free(ioc->pcie_sgl_dma_pool, |
4261 | ioc->pcie_sg_lookup[i].pcie_sgl, | |
4262 | ioc->pcie_sg_lookup[i].pcie_sgl_dma); | |
016d5c35 SPS |
4263 | } |
4264 | if (ioc->pcie_sgl_dma_pool) | |
13a06405 | 4265 | dma_pool_destroy(ioc->pcie_sgl_dma_pool); |
016d5c35 SPS |
4266 | } |
4267 | ||
f92363d1 SR |
4268 | if (ioc->config_page) { |
4269 | dexitprintk(ioc, pr_info(MPT3SAS_FMT | |
4270 | "config_page(0x%p): free\n", ioc->name, | |
4271 | ioc->config_page)); | |
4272 | pci_free_consistent(ioc->pdev, ioc->config_page_sz, | |
4273 | ioc->config_page, ioc->config_page_dma); | |
4274 | } | |
4275 | ||
f92363d1 SR |
4276 | kfree(ioc->hpr_lookup); |
4277 | kfree(ioc->internal_lookup); | |
4278 | if (ioc->chain_lookup) { | |
93204b78 | 4279 | for (i = 0; i < ioc->scsiio_depth; i++) { |
74522a92 C |
4280 | for (j = ioc->chains_per_prp_buffer; |
4281 | j < ioc->chains_needed_per_io; j++) { | |
93204b78 C |
4282 | ct = &ioc->chain_lookup[i].chains_per_smid[j]; |
4283 | if (ct && ct->chain_buffer) | |
4284 | dma_pool_free(ioc->chain_dma_pool, | |
4285 | ct->chain_buffer, | |
4286 | ct->chain_buffer_dma); | |
4287 | } | |
4288 | kfree(ioc->chain_lookup[i].chains_per_smid); | |
f92363d1 | 4289 | } |
e9d98418 | 4290 | dma_pool_destroy(ioc->chain_dma_pool); |
93204b78 | 4291 | kfree(ioc->chain_lookup); |
f92363d1 SR |
4292 | ioc->chain_lookup = NULL; |
4293 | } | |
4294 | } | |
4295 | ||
e21fef6f C |
4296 | /** |
4297 | * is_MSB_are_same - checks whether all reply queues in a set are | |
4298 | * having same upper 32bits in their base memory address. | |
4299 | * @reply_pool_start_address: Base address of a reply queue set | |
4300 | * @pool_sz: Size of single Reply Descriptor Post Queues pool size | |
4301 | * | |
4beb4867 BVA |
4302 | * Return: 1 if reply queues in a set have a same upper 32bits in their base |
4303 | * memory address, else 0. | |
e21fef6f C |
4304 | */ |
4305 | ||
4306 | static int | |
4307 | is_MSB_are_same(long reply_pool_start_address, u32 pool_sz) | |
4308 | { | |
4309 | long reply_pool_end_address; | |
4310 | ||
4311 | reply_pool_end_address = reply_pool_start_address + pool_sz; | |
4312 | ||
4313 | if (upper_32_bits(reply_pool_start_address) == | |
4314 | upper_32_bits(reply_pool_end_address)) | |
4315 | return 1; | |
4316 | else | |
4317 | return 0; | |
4318 | } | |
4319 | ||
f92363d1 SR |
4320 | /** |
4321 | * _base_allocate_memory_pools - allocate start of day memory pools | |
4322 | * @ioc: per adapter object | |
f92363d1 | 4323 | * |
4beb4867 | 4324 | * Return: 0 success, anything else error. |
f92363d1 SR |
4325 | */ |
4326 | static int | |
98c56ad3 | 4327 | _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
4328 | { |
4329 | struct mpt3sas_facts *facts; | |
4330 | u16 max_sge_elements; | |
4331 | u16 chains_needed_per_io; | |
cd33223b | 4332 | u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz; |
f92363d1 | 4333 | u32 retry_sz; |
016d5c35 | 4334 | u16 max_request_credit, nvme_blocks_needed; |
f92363d1 SR |
4335 | unsigned short sg_tablesize; |
4336 | u16 sge_size; | |
93204b78 C |
4337 | int i, j; |
4338 | struct chain_tracker *ct; | |
f92363d1 SR |
4339 | |
4340 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
4341 | __func__)); | |
4342 | ||
4343 | ||
4344 | retry_sz = 0; | |
4345 | facts = &ioc->facts; | |
4346 | ||
4347 | /* command line tunables for max sgl entries */ | |
4348 | if (max_sgl_entries != -1) | |
4349 | sg_tablesize = max_sgl_entries; | |
471ef9d4 SR |
4350 | else { |
4351 | if (ioc->hba_mpi_version_belonged == MPI2_VERSION) | |
4352 | sg_tablesize = MPT2SAS_SG_DEPTH; | |
4353 | else | |
4354 | sg_tablesize = MPT3SAS_SG_DEPTH; | |
4355 | } | |
f92363d1 | 4356 | |
06f5f976 SR |
4357 | /* max sgl entries <= MPT_KDUMP_MIN_PHYS_SEGMENTS in KDUMP mode */ |
4358 | if (reset_devices) | |
4359 | sg_tablesize = min_t(unsigned short, sg_tablesize, | |
4360 | MPT_KDUMP_MIN_PHYS_SEGMENTS); | |
4361 | ||
0448f019 SPS |
4362 | if (ioc->is_mcpu_endpoint) |
4363 | ioc->shost->sg_tablesize = MPT_MIN_PHYS_SEGMENTS; | |
4364 | else { | |
4365 | if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS) | |
4366 | sg_tablesize = MPT_MIN_PHYS_SEGMENTS; | |
4367 | else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) { | |
4368 | sg_tablesize = min_t(unsigned short, sg_tablesize, | |
4369 | SG_MAX_SEGMENTS); | |
4370 | pr_warn(MPT3SAS_FMT | |
4371 | "sg_tablesize(%u) is bigger than kernel " | |
4372 | "defined SG_CHUNK_SIZE(%u)\n", ioc->name, | |
4373 | sg_tablesize, MPT_MAX_PHYS_SEGMENTS); | |
4374 | } | |
4375 | ioc->shost->sg_tablesize = sg_tablesize; | |
ad666a0f | 4376 | } |
f92363d1 | 4377 | |
fd0331b3 SS |
4378 | ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)), |
4379 | (facts->RequestCredit / 4)); | |
4380 | if (ioc->internal_depth < INTERNAL_CMDS_COUNT) { | |
4381 | if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT + | |
4382 | INTERNAL_SCSIIO_CMDS_COUNT)) { | |
4383 | pr_err(MPT3SAS_FMT "IOC doesn't have enough Request \ | |
4384 | Credits, it has just %d number of credits\n", | |
4385 | ioc->name, facts->RequestCredit); | |
4386 | return -ENOMEM; | |
4387 | } | |
4388 | ioc->internal_depth = 10; | |
4389 | } | |
4390 | ||
4391 | ioc->hi_priority_depth = ioc->internal_depth - (5); | |
f92363d1 SR |
4392 | /* command line tunables for max controller queue depth */ |
4393 | if (max_queue_depth != -1 && max_queue_depth != 0) { | |
4394 | max_request_credit = min_t(u16, max_queue_depth + | |
fd0331b3 | 4395 | ioc->internal_depth, facts->RequestCredit); |
f92363d1 SR |
4396 | if (max_request_credit > MAX_HBA_QUEUE_DEPTH) |
4397 | max_request_credit = MAX_HBA_QUEUE_DEPTH; | |
06f5f976 SR |
4398 | } else if (reset_devices) |
4399 | max_request_credit = min_t(u16, facts->RequestCredit, | |
4400 | (MPT3SAS_KDUMP_SCSI_IO_DEPTH + ioc->internal_depth)); | |
4401 | else | |
f92363d1 SR |
4402 | max_request_credit = min_t(u16, facts->RequestCredit, |
4403 | MAX_HBA_QUEUE_DEPTH); | |
4404 | ||
fd0331b3 SS |
4405 | /* Firmware maintains additional facts->HighPriorityCredit number of |
4406 | * credits for HiPriprity Request messages, so hba queue depth will be | |
4407 | * sum of max_request_credit and high priority queue depth. | |
4408 | */ | |
4409 | ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth; | |
f92363d1 SR |
4410 | |
4411 | /* request frame size */ | |
4412 | ioc->request_sz = facts->IOCRequestFrameSize * 4; | |
4413 | ||
4414 | /* reply frame size */ | |
4415 | ioc->reply_sz = facts->ReplyFrameSize * 4; | |
4416 | ||
ebb3024e SS |
4417 | /* chain segment size */ |
4418 | if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { | |
4419 | if (facts->IOCMaxChainSegmentSize) | |
4420 | ioc->chain_segment_sz = | |
4421 | facts->IOCMaxChainSegmentSize * | |
4422 | MAX_CHAIN_ELEMT_SZ; | |
4423 | else | |
4424 | /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */ | |
4425 | ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS * | |
4426 | MAX_CHAIN_ELEMT_SZ; | |
4427 | } else | |
4428 | ioc->chain_segment_sz = ioc->request_sz; | |
4429 | ||
f92363d1 SR |
4430 | /* calculate the max scatter element size */ |
4431 | sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee); | |
4432 | ||
4433 | retry_allocation: | |
4434 | total_sz = 0; | |
4435 | /* calculate number of sg elements left over in the 1st frame */ | |
4436 | max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) - | |
4437 | sizeof(Mpi2SGEIOUnion_t)) + sge_size); | |
4438 | ioc->max_sges_in_main_message = max_sge_elements/sge_size; | |
4439 | ||
4440 | /* now do the same for a chain buffer */ | |
ebb3024e | 4441 | max_sge_elements = ioc->chain_segment_sz - sge_size; |
f92363d1 SR |
4442 | ioc->max_sges_in_chain_message = max_sge_elements/sge_size; |
4443 | ||
4444 | /* | |
4445 | * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE | |
4446 | */ | |
4447 | chains_needed_per_io = ((ioc->shost->sg_tablesize - | |
4448 | ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message) | |
4449 | + 1; | |
4450 | if (chains_needed_per_io > facts->MaxChainDepth) { | |
4451 | chains_needed_per_io = facts->MaxChainDepth; | |
4452 | ioc->shost->sg_tablesize = min_t(u16, | |
4453 | ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message | |
4454 | * chains_needed_per_io), ioc->shost->sg_tablesize); | |
4455 | } | |
4456 | ioc->chains_needed_per_io = chains_needed_per_io; | |
4457 | ||
4458 | /* reply free queue sizing - taking into account for 64 FW events */ | |
4459 | ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; | |
4460 | ||
0448f019 SPS |
4461 | /* mCPU manage single counters for simplicity */ |
4462 | if (ioc->is_mcpu_endpoint) | |
4463 | ioc->reply_post_queue_depth = ioc->reply_free_queue_depth; | |
4464 | else { | |
4465 | /* calculate reply descriptor post queue depth */ | |
4466 | ioc->reply_post_queue_depth = ioc->hba_queue_depth + | |
4467 | ioc->reply_free_queue_depth + 1; | |
4468 | /* align the reply post queue on the next 16 count boundary */ | |
4469 | if (ioc->reply_post_queue_depth % 16) | |
4470 | ioc->reply_post_queue_depth += 16 - | |
4471 | (ioc->reply_post_queue_depth % 16); | |
4472 | } | |
f92363d1 | 4473 | |
f92363d1 SR |
4474 | if (ioc->reply_post_queue_depth > |
4475 | facts->MaxReplyDescriptorPostQueueDepth) { | |
4476 | ioc->reply_post_queue_depth = | |
4477 | facts->MaxReplyDescriptorPostQueueDepth - | |
4478 | (facts->MaxReplyDescriptorPostQueueDepth % 16); | |
4479 | ioc->hba_queue_depth = | |
4480 | ((ioc->reply_post_queue_depth - 64) / 2) - 1; | |
4481 | ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; | |
4482 | } | |
4483 | ||
4484 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \ | |
4485 | "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), " | |
4486 | "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message, | |
4487 | ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize, | |
4488 | ioc->chains_needed_per_io)); | |
4489 | ||
9b05c91a SR |
4490 | /* reply post queue, 16 byte align */ |
4491 | reply_post_free_sz = ioc->reply_post_queue_depth * | |
4492 | sizeof(Mpi2DefaultReplyDescriptor_t); | |
4493 | ||
4494 | sz = reply_post_free_sz; | |
4495 | if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable) | |
4496 | sz *= ioc->reply_queue_count; | |
4497 | ||
4498 | ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ? | |
4499 | (ioc->reply_queue_count):1, | |
4500 | sizeof(struct reply_post_struct), GFP_KERNEL); | |
4501 | ||
4502 | if (!ioc->reply_post) { | |
4503 | pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n", | |
4504 | ioc->name); | |
4505 | goto out; | |
4506 | } | |
e9d98418 RP |
4507 | ioc->reply_post_free_dma_pool = dma_pool_create("reply_post_free pool", |
4508 | &ioc->pdev->dev, sz, 16, 0); | |
9b05c91a SR |
4509 | if (!ioc->reply_post_free_dma_pool) { |
4510 | pr_err(MPT3SAS_FMT | |
e9d98418 | 4511 | "reply_post_free pool: dma_pool_create failed\n", |
9b05c91a SR |
4512 | ioc->name); |
4513 | goto out; | |
4514 | } | |
4515 | i = 0; | |
4516 | do { | |
4517 | ioc->reply_post[i].reply_post_free = | |
e9d98418 | 4518 | dma_pool_alloc(ioc->reply_post_free_dma_pool, |
9b05c91a SR |
4519 | GFP_KERNEL, |
4520 | &ioc->reply_post[i].reply_post_free_dma); | |
4521 | if (!ioc->reply_post[i].reply_post_free) { | |
4522 | pr_err(MPT3SAS_FMT | |
e9d98418 | 4523 | "reply_post_free pool: dma_pool_alloc failed\n", |
9b05c91a SR |
4524 | ioc->name); |
4525 | goto out; | |
4526 | } | |
4527 | memset(ioc->reply_post[i].reply_post_free, 0, sz); | |
4528 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
4529 | "reply post free pool (0x%p): depth(%d)," | |
4530 | "element_size(%d), pool_size(%d kB)\n", ioc->name, | |
4531 | ioc->reply_post[i].reply_post_free, | |
4532 | ioc->reply_post_queue_depth, 8, sz/1024)); | |
4533 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
4534 | "reply_post_free_dma = (0x%llx)\n", ioc->name, | |
4535 | (unsigned long long) | |
4536 | ioc->reply_post[i].reply_post_free_dma)); | |
4537 | total_sz += sz; | |
4538 | } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count)); | |
4539 | ||
4540 | if (ioc->dma_mask == 64) { | |
4541 | if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) { | |
4542 | pr_warn(MPT3SAS_FMT | |
4543 | "no suitable consistent DMA mask for %s\n", | |
4544 | ioc->name, pci_name(ioc->pdev)); | |
4545 | goto out; | |
4546 | } | |
4547 | } | |
4548 | ||
f92363d1 SR |
4549 | ioc->scsiio_depth = ioc->hba_queue_depth - |
4550 | ioc->hi_priority_depth - ioc->internal_depth; | |
4551 | ||
4552 | /* set the scsi host can_queue depth | |
4553 | * with some internal commands that could be outstanding | |
4554 | */ | |
fd0331b3 | 4555 | ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT; |
f92363d1 SR |
4556 | dinitprintk(ioc, pr_info(MPT3SAS_FMT |
4557 | "scsi host: can_queue depth (%d)\n", | |
4558 | ioc->name, ioc->shost->can_queue)); | |
4559 | ||
4560 | ||
4561 | /* contiguous pool for request and chains, 16 byte align, one extra " | |
4562 | * "frame for smid=0 | |
4563 | */ | |
4564 | ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth; | |
4565 | sz = ((ioc->scsiio_depth + 1) * ioc->request_sz); | |
4566 | ||
4567 | /* hi-priority queue */ | |
4568 | sz += (ioc->hi_priority_depth * ioc->request_sz); | |
4569 | ||
4570 | /* internal queue */ | |
4571 | sz += (ioc->internal_depth * ioc->request_sz); | |
4572 | ||
4573 | ioc->request_dma_sz = sz; | |
4574 | ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma); | |
4575 | if (!ioc->request) { | |
4576 | pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \ | |
4577 | "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), " | |
4578 | "total(%d kB)\n", ioc->name, ioc->hba_queue_depth, | |
4579 | ioc->chains_needed_per_io, ioc->request_sz, sz/1024); | |
4580 | if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH) | |
4581 | goto out; | |
fd0331b3 SS |
4582 | retry_sz = 64; |
4583 | ioc->hba_queue_depth -= retry_sz; | |
8ff045c9 | 4584 | _base_release_memory_pools(ioc); |
f92363d1 SR |
4585 | goto retry_allocation; |
4586 | } | |
4587 | ||
4588 | if (retry_sz) | |
4589 | pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \ | |
4590 | "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), " | |
4591 | "total(%d kb)\n", ioc->name, ioc->hba_queue_depth, | |
4592 | ioc->chains_needed_per_io, ioc->request_sz, sz/1024); | |
4593 | ||
4594 | /* hi-priority queue */ | |
4595 | ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) * | |
4596 | ioc->request_sz); | |
4597 | ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) * | |
4598 | ioc->request_sz); | |
4599 | ||
4600 | /* internal queue */ | |
4601 | ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth * | |
4602 | ioc->request_sz); | |
4603 | ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth * | |
4604 | ioc->request_sz); | |
4605 | ||
4606 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
4607 | "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n", | |
4608 | ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz, | |
4609 | (ioc->hba_queue_depth * ioc->request_sz)/1024)); | |
4610 | ||
4611 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n", | |
4612 | ioc->name, (unsigned long long) ioc->request_dma)); | |
4613 | total_sz += sz; | |
4614 | ||
f92363d1 SR |
4615 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n", |
4616 | ioc->name, ioc->request, ioc->scsiio_depth)); | |
4617 | ||
4618 | ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH); | |
93204b78 C |
4619 | sz = ioc->scsiio_depth * sizeof(struct chain_lookup); |
4620 | ioc->chain_lookup = kzalloc(sz, GFP_KERNEL); | |
f92363d1 | 4621 | if (!ioc->chain_lookup) { |
93204b78 | 4622 | pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages " |
74522a92 | 4623 | "failed\n", ioc->name); |
f92363d1 SR |
4624 | goto out; |
4625 | } | |
93204b78 C |
4626 | |
4627 | sz = ioc->chains_needed_per_io * sizeof(struct chain_tracker); | |
4628 | for (i = 0; i < ioc->scsiio_depth; i++) { | |
4629 | ioc->chain_lookup[i].chains_per_smid = kzalloc(sz, GFP_KERNEL); | |
4630 | if (!ioc->chain_lookup[i].chains_per_smid) { | |
4631 | pr_err(MPT3SAS_FMT "chain_lookup: " | |
4632 | " kzalloc failed\n", ioc->name); | |
4633 | goto out; | |
4634 | } | |
4635 | } | |
4636 | ||
f92363d1 SR |
4637 | /* initialize hi-priority queue smid's */ |
4638 | ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth, | |
4639 | sizeof(struct request_tracker), GFP_KERNEL); | |
4640 | if (!ioc->hpr_lookup) { | |
4641 | pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n", | |
4642 | ioc->name); | |
4643 | goto out; | |
4644 | } | |
4645 | ioc->hi_priority_smid = ioc->scsiio_depth + 1; | |
4646 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
4647 | "hi_priority(0x%p): depth(%d), start smid(%d)\n", | |
4648 | ioc->name, ioc->hi_priority, | |
4649 | ioc->hi_priority_depth, ioc->hi_priority_smid)); | |
4650 | ||
4651 | /* initialize internal queue smid's */ | |
4652 | ioc->internal_lookup = kcalloc(ioc->internal_depth, | |
4653 | sizeof(struct request_tracker), GFP_KERNEL); | |
4654 | if (!ioc->internal_lookup) { | |
4655 | pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n", | |
4656 | ioc->name); | |
4657 | goto out; | |
4658 | } | |
4659 | ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth; | |
4660 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
4661 | "internal(0x%p): depth(%d), start smid(%d)\n", | |
4662 | ioc->name, ioc->internal, | |
4663 | ioc->internal_depth, ioc->internal_smid)); | |
016d5c35 SPS |
4664 | /* |
4665 | * The number of NVMe page sized blocks needed is: | |
4666 | * (((sg_tablesize * 8) - 1) / (page_size - 8)) + 1 | |
4667 | * ((sg_tablesize * 8) - 1) is the max PRP's minus the first PRP entry | |
4668 | * that is placed in the main message frame. 8 is the size of each PRP | |
4669 | * entry or PRP list pointer entry. 8 is subtracted from page_size | |
4670 | * because of the PRP list pointer entry at the end of a page, so this | |
4671 | * is not counted as a PRP entry. The 1 added page is a round up. | |
4672 | * | |
4673 | * To avoid allocation failures due to the amount of memory that could | |
4674 | * be required for NVMe PRP's, only each set of NVMe blocks will be | |
4675 | * contiguous, so a new set is allocated for each possible I/O. | |
4676 | */ | |
74522a92 | 4677 | ioc->chains_per_prp_buffer = 0; |
016d5c35 SPS |
4678 | if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) { |
4679 | nvme_blocks_needed = | |
4680 | (ioc->shost->sg_tablesize * NVME_PRP_SIZE) - 1; | |
4681 | nvme_blocks_needed /= (ioc->page_size - NVME_PRP_SIZE); | |
4682 | nvme_blocks_needed++; | |
4683 | ||
dbec4c90 SPS |
4684 | sz = sizeof(struct pcie_sg_list) * ioc->scsiio_depth; |
4685 | ioc->pcie_sg_lookup = kzalloc(sz, GFP_KERNEL); | |
4686 | if (!ioc->pcie_sg_lookup) { | |
4687 | pr_info(MPT3SAS_FMT | |
4688 | "PCIe SGL lookup: kzalloc failed\n", ioc->name); | |
4689 | goto out; | |
4690 | } | |
016d5c35 SPS |
4691 | sz = nvme_blocks_needed * ioc->page_size; |
4692 | ioc->pcie_sgl_dma_pool = | |
13a06405 | 4693 | dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz, 16, 0); |
016d5c35 SPS |
4694 | if (!ioc->pcie_sgl_dma_pool) { |
4695 | pr_info(MPT3SAS_FMT | |
13a06405 | 4696 | "PCIe SGL pool: dma_pool_create failed\n", |
016d5c35 SPS |
4697 | ioc->name); |
4698 | goto out; | |
4699 | } | |
74522a92 C |
4700 | |
4701 | ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz; | |
4702 | ioc->chains_per_prp_buffer = min(ioc->chains_per_prp_buffer, | |
4703 | ioc->chains_needed_per_io); | |
4704 | ||
016d5c35 | 4705 | for (i = 0; i < ioc->scsiio_depth; i++) { |
dbec4c90 SPS |
4706 | ioc->pcie_sg_lookup[i].pcie_sgl = dma_pool_alloc( |
4707 | ioc->pcie_sgl_dma_pool, GFP_KERNEL, | |
4708 | &ioc->pcie_sg_lookup[i].pcie_sgl_dma); | |
4709 | if (!ioc->pcie_sg_lookup[i].pcie_sgl) { | |
016d5c35 | 4710 | pr_info(MPT3SAS_FMT |
13a06405 | 4711 | "PCIe SGL pool: dma_pool_alloc failed\n", |
016d5c35 SPS |
4712 | ioc->name); |
4713 | goto out; | |
4714 | } | |
74522a92 C |
4715 | for (j = 0; j < ioc->chains_per_prp_buffer; j++) { |
4716 | ct = &ioc->chain_lookup[i].chains_per_smid[j]; | |
4717 | ct->chain_buffer = | |
4718 | ioc->pcie_sg_lookup[i].pcie_sgl + | |
4719 | (j * ioc->chain_segment_sz); | |
4720 | ct->chain_buffer_dma = | |
4721 | ioc->pcie_sg_lookup[i].pcie_sgl_dma + | |
4722 | (j * ioc->chain_segment_sz); | |
4723 | } | |
016d5c35 | 4724 | } |
f92363d1 | 4725 | |
016d5c35 SPS |
4726 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "PCIe sgl pool depth(%d), " |
4727 | "element_size(%d), pool_size(%d kB)\n", ioc->name, | |
4728 | ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024)); | |
74522a92 C |
4729 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "Number of chains can " |
4730 | "fit in a PRP page(%d)\n", ioc->name, | |
4731 | ioc->chains_per_prp_buffer)); | |
016d5c35 SPS |
4732 | total_sz += sz * ioc->scsiio_depth; |
4733 | } | |
74522a92 C |
4734 | |
4735 | ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev, | |
4736 | ioc->chain_segment_sz, 16, 0); | |
4737 | if (!ioc->chain_dma_pool) { | |
4738 | pr_err(MPT3SAS_FMT "chain_dma_pool: dma_pool_create failed\n", | |
4739 | ioc->name); | |
4740 | goto out; | |
4741 | } | |
4742 | for (i = 0; i < ioc->scsiio_depth; i++) { | |
4743 | for (j = ioc->chains_per_prp_buffer; | |
4744 | j < ioc->chains_needed_per_io; j++) { | |
4745 | ct = &ioc->chain_lookup[i].chains_per_smid[j]; | |
4746 | ct->chain_buffer = dma_pool_alloc( | |
4747 | ioc->chain_dma_pool, GFP_KERNEL, | |
4748 | &ct->chain_buffer_dma); | |
4749 | if (!ct->chain_buffer) { | |
4750 | pr_err(MPT3SAS_FMT "chain_lookup: " | |
4751 | " pci_pool_alloc failed\n", ioc->name); | |
4752 | _base_release_memory_pools(ioc); | |
4753 | goto out; | |
4754 | } | |
4755 | } | |
4756 | total_sz += ioc->chain_segment_sz; | |
4757 | } | |
4758 | ||
4759 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
4760 | "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n", | |
4761 | ioc->name, ioc->chain_depth, ioc->chain_segment_sz, | |
4762 | ((ioc->chain_depth * ioc->chain_segment_sz))/1024)); | |
4763 | ||
f92363d1 SR |
4764 | /* sense buffers, 4 byte align */ |
4765 | sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE; | |
e9d98418 RP |
4766 | ioc->sense_dma_pool = dma_pool_create("sense pool", &ioc->pdev->dev, sz, |
4767 | 4, 0); | |
f92363d1 | 4768 | if (!ioc->sense_dma_pool) { |
e9d98418 | 4769 | pr_err(MPT3SAS_FMT "sense pool: dma_pool_create failed\n", |
f92363d1 SR |
4770 | ioc->name); |
4771 | goto out; | |
4772 | } | |
e9d98418 | 4773 | ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL, |
f92363d1 SR |
4774 | &ioc->sense_dma); |
4775 | if (!ioc->sense) { | |
e9d98418 | 4776 | pr_err(MPT3SAS_FMT "sense pool: dma_pool_alloc failed\n", |
f92363d1 SR |
4777 | ioc->name); |
4778 | goto out; | |
4779 | } | |
e21fef6f C |
4780 | /* sense buffer requires to be in same 4 gb region. |
4781 | * Below function will check the same. | |
4782 | * In case of failure, new pci pool will be created with updated | |
4783 | * alignment. Older allocation and pool will be destroyed. | |
4784 | * Alignment will be used such a way that next allocation if | |
4785 | * success, will always meet same 4gb region requirement. | |
4786 | * Actual requirement is not alignment, but we need start and end of | |
4787 | * DMA address must have same upper 32 bit address. | |
4788 | */ | |
4789 | if (!is_MSB_are_same((long)ioc->sense, sz)) { | |
4790 | //Release Sense pool & Reallocate | |
4791 | dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma); | |
4792 | dma_pool_destroy(ioc->sense_dma_pool); | |
4793 | ioc->sense = NULL; | |
4794 | ||
4795 | ioc->sense_dma_pool = | |
4796 | dma_pool_create("sense pool", &ioc->pdev->dev, sz, | |
4797 | roundup_pow_of_two(sz), 0); | |
4798 | if (!ioc->sense_dma_pool) { | |
4799 | pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n", | |
4800 | ioc->name); | |
4801 | goto out; | |
4802 | } | |
4803 | ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL, | |
4804 | &ioc->sense_dma); | |
4805 | if (!ioc->sense) { | |
4806 | pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n", | |
4807 | ioc->name); | |
4808 | goto out; | |
4809 | } | |
4810 | } | |
f92363d1 SR |
4811 | dinitprintk(ioc, pr_info(MPT3SAS_FMT |
4812 | "sense pool(0x%p): depth(%d), element_size(%d), pool_size" | |
4813 | "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth, | |
4814 | SCSI_SENSE_BUFFERSIZE, sz/1024)); | |
4815 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n", | |
4816 | ioc->name, (unsigned long long)ioc->sense_dma)); | |
4817 | total_sz += sz; | |
4818 | ||
4819 | /* reply pool, 4 byte align */ | |
4820 | sz = ioc->reply_free_queue_depth * ioc->reply_sz; | |
e9d98418 RP |
4821 | ioc->reply_dma_pool = dma_pool_create("reply pool", &ioc->pdev->dev, sz, |
4822 | 4, 0); | |
f92363d1 | 4823 | if (!ioc->reply_dma_pool) { |
e9d98418 | 4824 | pr_err(MPT3SAS_FMT "reply pool: dma_pool_create failed\n", |
f92363d1 SR |
4825 | ioc->name); |
4826 | goto out; | |
4827 | } | |
e9d98418 | 4828 | ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL, |
f92363d1 SR |
4829 | &ioc->reply_dma); |
4830 | if (!ioc->reply) { | |
e9d98418 | 4831 | pr_err(MPT3SAS_FMT "reply pool: dma_pool_alloc failed\n", |
f92363d1 SR |
4832 | ioc->name); |
4833 | goto out; | |
4834 | } | |
4835 | ioc->reply_dma_min_address = (u32)(ioc->reply_dma); | |
4836 | ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz; | |
4837 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
4838 | "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n", | |
4839 | ioc->name, ioc->reply, | |
4840 | ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024)); | |
4841 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n", | |
4842 | ioc->name, (unsigned long long)ioc->reply_dma)); | |
4843 | total_sz += sz; | |
4844 | ||
4845 | /* reply free queue, 16 byte align */ | |
4846 | sz = ioc->reply_free_queue_depth * 4; | |
e9d98418 RP |
4847 | ioc->reply_free_dma_pool = dma_pool_create("reply_free pool", |
4848 | &ioc->pdev->dev, sz, 16, 0); | |
f92363d1 | 4849 | if (!ioc->reply_free_dma_pool) { |
e9d98418 | 4850 | pr_err(MPT3SAS_FMT "reply_free pool: dma_pool_create failed\n", |
f92363d1 SR |
4851 | ioc->name); |
4852 | goto out; | |
4853 | } | |
e9d98418 | 4854 | ioc->reply_free = dma_pool_alloc(ioc->reply_free_dma_pool, GFP_KERNEL, |
f92363d1 SR |
4855 | &ioc->reply_free_dma); |
4856 | if (!ioc->reply_free) { | |
e9d98418 | 4857 | pr_err(MPT3SAS_FMT "reply_free pool: dma_pool_alloc failed\n", |
f92363d1 SR |
4858 | ioc->name); |
4859 | goto out; | |
4860 | } | |
4861 | memset(ioc->reply_free, 0, sz); | |
4862 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \ | |
4863 | "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name, | |
4864 | ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024)); | |
4865 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
4866 | "reply_free_dma (0x%llx)\n", | |
4867 | ioc->name, (unsigned long long)ioc->reply_free_dma)); | |
4868 | total_sz += sz; | |
4869 | ||
cd33223b C |
4870 | if (ioc->rdpq_array_enable) { |
4871 | reply_post_free_array_sz = ioc->reply_queue_count * | |
4872 | sizeof(Mpi2IOCInitRDPQArrayEntry); | |
4873 | ioc->reply_post_free_array_dma_pool = | |
4874 | dma_pool_create("reply_post_free_array pool", | |
4875 | &ioc->pdev->dev, reply_post_free_array_sz, 16, 0); | |
4876 | if (!ioc->reply_post_free_array_dma_pool) { | |
4877 | dinitprintk(ioc, | |
4878 | pr_info(MPT3SAS_FMT "reply_post_free_array pool: " | |
4879 | "dma_pool_create failed\n", ioc->name)); | |
4880 | goto out; | |
4881 | } | |
4882 | ioc->reply_post_free_array = | |
4883 | dma_pool_alloc(ioc->reply_post_free_array_dma_pool, | |
4884 | GFP_KERNEL, &ioc->reply_post_free_array_dma); | |
4885 | if (!ioc->reply_post_free_array) { | |
4886 | dinitprintk(ioc, | |
4887 | pr_info(MPT3SAS_FMT "reply_post_free_array pool: " | |
4888 | "dma_pool_alloc failed\n", ioc->name)); | |
4889 | goto out; | |
4890 | } | |
4891 | } | |
f92363d1 SR |
4892 | ioc->config_page_sz = 512; |
4893 | ioc->config_page = pci_alloc_consistent(ioc->pdev, | |
4894 | ioc->config_page_sz, &ioc->config_page_dma); | |
4895 | if (!ioc->config_page) { | |
4896 | pr_err(MPT3SAS_FMT | |
e9d98418 | 4897 | "config page: dma_pool_alloc failed\n", |
f92363d1 SR |
4898 | ioc->name); |
4899 | goto out; | |
4900 | } | |
4901 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
4902 | "config page(0x%p): size(%d)\n", | |
4903 | ioc->name, ioc->config_page, ioc->config_page_sz)); | |
4904 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n", | |
4905 | ioc->name, (unsigned long long)ioc->config_page_dma)); | |
4906 | total_sz += ioc->config_page_sz; | |
4907 | ||
4908 | pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n", | |
4909 | ioc->name, total_sz/1024); | |
4910 | pr_info(MPT3SAS_FMT | |
4911 | "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n", | |
4912 | ioc->name, ioc->shost->can_queue, facts->RequestCredit); | |
4913 | pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n", | |
4914 | ioc->name, ioc->shost->sg_tablesize); | |
4915 | return 0; | |
4916 | ||
4917 | out: | |
4918 | return -ENOMEM; | |
4919 | } | |
4920 | ||
4921 | /** | |
4922 | * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter. | |
4923 | * @ioc: Pointer to MPT_ADAPTER structure | |
4924 | * @cooked: Request raw or cooked IOC state | |
4925 | * | |
4beb4867 | 4926 | * Return: all IOC Doorbell register bits if cooked==0, else just the |
f92363d1 SR |
4927 | * Doorbell bits in MPI_IOC_STATE_MASK. |
4928 | */ | |
4929 | u32 | |
4930 | mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked) | |
4931 | { | |
4932 | u32 s, sc; | |
4933 | ||
4934 | s = readl(&ioc->chip->Doorbell); | |
4935 | sc = s & MPI2_IOC_STATE_MASK; | |
4936 | return cooked ? sc : s; | |
4937 | } | |
4938 | ||
4939 | /** | |
4940 | * _base_wait_on_iocstate - waiting on a particular ioc state | |
4beb4867 | 4941 | * @ioc: ? |
f92363d1 SR |
4942 | * @ioc_state: controller state { READY, OPERATIONAL, or RESET } |
4943 | * @timeout: timeout in second | |
f92363d1 | 4944 | * |
4beb4867 | 4945 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
4946 | */ |
4947 | static int | |
98c56ad3 | 4948 | _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout) |
f92363d1 SR |
4949 | { |
4950 | u32 count, cntdn; | |
4951 | u32 current_state; | |
4952 | ||
4953 | count = 0; | |
98c56ad3 | 4954 | cntdn = 1000 * timeout; |
f92363d1 SR |
4955 | do { |
4956 | current_state = mpt3sas_base_get_iocstate(ioc, 1); | |
4957 | if (current_state == ioc_state) | |
4958 | return 0; | |
4959 | if (count && current_state == MPI2_IOC_STATE_FAULT) | |
4960 | break; | |
98c56ad3 CO |
4961 | |
4962 | usleep_range(1000, 1500); | |
f92363d1 SR |
4963 | count++; |
4964 | } while (--cntdn); | |
4965 | ||
4966 | return current_state; | |
4967 | } | |
4968 | ||
4969 | /** | |
4970 | * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by | |
4971 | * a write to the doorbell) | |
4972 | * @ioc: per adapter object | |
f92363d1 | 4973 | * |
4beb4867 | 4974 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
4975 | * |
4976 | * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell. | |
4977 | */ | |
4dc8c808 | 4978 | static int |
98c56ad3 | 4979 | _base_diag_reset(struct MPT3SAS_ADAPTER *ioc); |
4dc8c808 | 4980 | |
f92363d1 | 4981 | static int |
98c56ad3 | 4982 | _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout) |
f92363d1 SR |
4983 | { |
4984 | u32 cntdn, count; | |
4985 | u32 int_status; | |
4986 | ||
4987 | count = 0; | |
98c56ad3 | 4988 | cntdn = 1000 * timeout; |
f92363d1 SR |
4989 | do { |
4990 | int_status = readl(&ioc->chip->HostInterruptStatus); | |
4991 | if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { | |
4992 | dhsprintk(ioc, pr_info(MPT3SAS_FMT | |
4993 | "%s: successful count(%d), timeout(%d)\n", | |
4994 | ioc->name, __func__, count, timeout)); | |
4995 | return 0; | |
4996 | } | |
98c56ad3 CO |
4997 | |
4998 | usleep_range(1000, 1500); | |
4999 | count++; | |
5000 | } while (--cntdn); | |
5001 | ||
5002 | pr_err(MPT3SAS_FMT | |
5003 | "%s: failed due to timeout count(%d), int_status(%x)!\n", | |
5004 | ioc->name, __func__, count, int_status); | |
5005 | return -EFAULT; | |
5006 | } | |
5007 | ||
5008 | static int | |
5009 | _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout) | |
5010 | { | |
5011 | u32 cntdn, count; | |
5012 | u32 int_status; | |
5013 | ||
5014 | count = 0; | |
5015 | cntdn = 2000 * timeout; | |
5016 | do { | |
5017 | int_status = readl(&ioc->chip->HostInterruptStatus); | |
5018 | if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { | |
5019 | dhsprintk(ioc, pr_info(MPT3SAS_FMT | |
5020 | "%s: successful count(%d), timeout(%d)\n", | |
5021 | ioc->name, __func__, count, timeout)); | |
5022 | return 0; | |
5023 | } | |
5024 | ||
5025 | udelay(500); | |
f92363d1 SR |
5026 | count++; |
5027 | } while (--cntdn); | |
5028 | ||
5029 | pr_err(MPT3SAS_FMT | |
5030 | "%s: failed due to timeout count(%d), int_status(%x)!\n", | |
5031 | ioc->name, __func__, count, int_status); | |
5032 | return -EFAULT; | |
98c56ad3 | 5033 | |
f92363d1 SR |
5034 | } |
5035 | ||
5036 | /** | |
5037 | * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell. | |
5038 | * @ioc: per adapter object | |
5039 | * @timeout: timeout in second | |
f92363d1 | 5040 | * |
4beb4867 | 5041 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
5042 | * |
5043 | * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to | |
5044 | * doorbell. | |
5045 | */ | |
5046 | static int | |
98c56ad3 | 5047 | _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout) |
f92363d1 SR |
5048 | { |
5049 | u32 cntdn, count; | |
5050 | u32 int_status; | |
5051 | u32 doorbell; | |
5052 | ||
5053 | count = 0; | |
98c56ad3 | 5054 | cntdn = 1000 * timeout; |
f92363d1 SR |
5055 | do { |
5056 | int_status = readl(&ioc->chip->HostInterruptStatus); | |
5057 | if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) { | |
5058 | dhsprintk(ioc, pr_info(MPT3SAS_FMT | |
5059 | "%s: successful count(%d), timeout(%d)\n", | |
5060 | ioc->name, __func__, count, timeout)); | |
5061 | return 0; | |
5062 | } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { | |
5063 | doorbell = readl(&ioc->chip->Doorbell); | |
5064 | if ((doorbell & MPI2_IOC_STATE_MASK) == | |
5065 | MPI2_IOC_STATE_FAULT) { | |
5066 | mpt3sas_base_fault_info(ioc , doorbell); | |
5067 | return -EFAULT; | |
5068 | } | |
5069 | } else if (int_status == 0xFFFFFFFF) | |
5070 | goto out; | |
5071 | ||
98c56ad3 | 5072 | usleep_range(1000, 1500); |
f92363d1 SR |
5073 | count++; |
5074 | } while (--cntdn); | |
5075 | ||
5076 | out: | |
5077 | pr_err(MPT3SAS_FMT | |
5078 | "%s: failed due to timeout count(%d), int_status(%x)!\n", | |
5079 | ioc->name, __func__, count, int_status); | |
5080 | return -EFAULT; | |
5081 | } | |
5082 | ||
5083 | /** | |
5084 | * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use | |
5085 | * @ioc: per adapter object | |
5086 | * @timeout: timeout in second | |
f92363d1 | 5087 | * |
4beb4867 | 5088 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
5089 | */ |
5090 | static int | |
98c56ad3 | 5091 | _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout) |
f92363d1 SR |
5092 | { |
5093 | u32 cntdn, count; | |
5094 | u32 doorbell_reg; | |
5095 | ||
5096 | count = 0; | |
98c56ad3 | 5097 | cntdn = 1000 * timeout; |
f92363d1 SR |
5098 | do { |
5099 | doorbell_reg = readl(&ioc->chip->Doorbell); | |
5100 | if (!(doorbell_reg & MPI2_DOORBELL_USED)) { | |
5101 | dhsprintk(ioc, pr_info(MPT3SAS_FMT | |
5102 | "%s: successful count(%d), timeout(%d)\n", | |
5103 | ioc->name, __func__, count, timeout)); | |
5104 | return 0; | |
5105 | } | |
98c56ad3 CO |
5106 | |
5107 | usleep_range(1000, 1500); | |
f92363d1 SR |
5108 | count++; |
5109 | } while (--cntdn); | |
5110 | ||
5111 | pr_err(MPT3SAS_FMT | |
5112 | "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n", | |
5113 | ioc->name, __func__, count, doorbell_reg); | |
5114 | return -EFAULT; | |
5115 | } | |
5116 | ||
5117 | /** | |
5118 | * _base_send_ioc_reset - send doorbell reset | |
5119 | * @ioc: per adapter object | |
5120 | * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET | |
5121 | * @timeout: timeout in second | |
f92363d1 | 5122 | * |
4beb4867 | 5123 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
5124 | */ |
5125 | static int | |
98c56ad3 | 5126 | _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout) |
f92363d1 SR |
5127 | { |
5128 | u32 ioc_state; | |
5129 | int r = 0; | |
5130 | ||
5131 | if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) { | |
5132 | pr_err(MPT3SAS_FMT "%s: unknown reset_type\n", | |
5133 | ioc->name, __func__); | |
5134 | return -EFAULT; | |
5135 | } | |
5136 | ||
5137 | if (!(ioc->facts.IOCCapabilities & | |
5138 | MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY)) | |
5139 | return -EFAULT; | |
5140 | ||
5141 | pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name); | |
5142 | ||
5143 | writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT, | |
5144 | &ioc->chip->Doorbell); | |
98c56ad3 | 5145 | if ((_base_wait_for_doorbell_ack(ioc, 15))) { |
f92363d1 SR |
5146 | r = -EFAULT; |
5147 | goto out; | |
5148 | } | |
98c56ad3 | 5149 | ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout); |
f92363d1 SR |
5150 | if (ioc_state) { |
5151 | pr_err(MPT3SAS_FMT | |
5152 | "%s: failed going to ready state (ioc_state=0x%x)\n", | |
5153 | ioc->name, __func__, ioc_state); | |
5154 | r = -EFAULT; | |
5155 | goto out; | |
5156 | } | |
5157 | out: | |
5158 | pr_info(MPT3SAS_FMT "message unit reset: %s\n", | |
5159 | ioc->name, ((r == 0) ? "SUCCESS" : "FAILED")); | |
5160 | return r; | |
5161 | } | |
5162 | ||
5163 | /** | |
5164 | * _base_handshake_req_reply_wait - send request thru doorbell interface | |
5165 | * @ioc: per adapter object | |
5166 | * @request_bytes: request length | |
5167 | * @request: pointer having request payload | |
5168 | * @reply_bytes: reply length | |
5169 | * @reply: pointer to reply payload | |
5170 | * @timeout: timeout in second | |
f92363d1 | 5171 | * |
4beb4867 | 5172 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
5173 | */ |
5174 | static int | |
5175 | _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes, | |
98c56ad3 | 5176 | u32 *request, int reply_bytes, u16 *reply, int timeout) |
f92363d1 SR |
5177 | { |
5178 | MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply; | |
5179 | int i; | |
5180 | u8 failed; | |
f92363d1 SR |
5181 | __le32 *mfp; |
5182 | ||
5183 | /* make sure doorbell is not in use */ | |
5184 | if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) { | |
5185 | pr_err(MPT3SAS_FMT | |
5186 | "doorbell is in use (line=%d)\n", | |
5187 | ioc->name, __LINE__); | |
5188 | return -EFAULT; | |
5189 | } | |
5190 | ||
5191 | /* clear pending doorbell interrupts from previous state changes */ | |
5192 | if (readl(&ioc->chip->HostInterruptStatus) & | |
5193 | MPI2_HIS_IOC2SYS_DB_STATUS) | |
5194 | writel(0, &ioc->chip->HostInterruptStatus); | |
5195 | ||
5196 | /* send message to ioc */ | |
5197 | writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) | | |
5198 | ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)), | |
5199 | &ioc->chip->Doorbell); | |
5200 | ||
98c56ad3 | 5201 | if ((_base_spin_on_doorbell_int(ioc, 5))) { |
f92363d1 SR |
5202 | pr_err(MPT3SAS_FMT |
5203 | "doorbell handshake int failed (line=%d)\n", | |
5204 | ioc->name, __LINE__); | |
5205 | return -EFAULT; | |
5206 | } | |
5207 | writel(0, &ioc->chip->HostInterruptStatus); | |
5208 | ||
98c56ad3 | 5209 | if ((_base_wait_for_doorbell_ack(ioc, 5))) { |
f92363d1 SR |
5210 | pr_err(MPT3SAS_FMT |
5211 | "doorbell handshake ack failed (line=%d)\n", | |
5212 | ioc->name, __LINE__); | |
5213 | return -EFAULT; | |
5214 | } | |
5215 | ||
5216 | /* send message 32-bits at a time */ | |
5217 | for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) { | |
cf6bf971 | 5218 | writel((u32)(request[i]), &ioc->chip->Doorbell); |
98c56ad3 | 5219 | if ((_base_wait_for_doorbell_ack(ioc, 5))) |
f92363d1 SR |
5220 | failed = 1; |
5221 | } | |
5222 | ||
5223 | if (failed) { | |
5224 | pr_err(MPT3SAS_FMT | |
5225 | "doorbell handshake sending request failed (line=%d)\n", | |
5226 | ioc->name, __LINE__); | |
5227 | return -EFAULT; | |
5228 | } | |
5229 | ||
5230 | /* now wait for the reply */ | |
98c56ad3 | 5231 | if ((_base_wait_for_doorbell_int(ioc, timeout))) { |
f92363d1 SR |
5232 | pr_err(MPT3SAS_FMT |
5233 | "doorbell handshake int failed (line=%d)\n", | |
5234 | ioc->name, __LINE__); | |
5235 | return -EFAULT; | |
5236 | } | |
5237 | ||
5238 | /* read the first two 16-bits, it gives the total length of the reply */ | |
cf6bf971 | 5239 | reply[0] = (u16)(readl(&ioc->chip->Doorbell) |
f92363d1 SR |
5240 | & MPI2_DOORBELL_DATA_MASK); |
5241 | writel(0, &ioc->chip->HostInterruptStatus); | |
98c56ad3 | 5242 | if ((_base_wait_for_doorbell_int(ioc, 5))) { |
f92363d1 SR |
5243 | pr_err(MPT3SAS_FMT |
5244 | "doorbell handshake int failed (line=%d)\n", | |
5245 | ioc->name, __LINE__); | |
5246 | return -EFAULT; | |
5247 | } | |
cf6bf971 | 5248 | reply[1] = (u16)(readl(&ioc->chip->Doorbell) |
f92363d1 SR |
5249 | & MPI2_DOORBELL_DATA_MASK); |
5250 | writel(0, &ioc->chip->HostInterruptStatus); | |
5251 | ||
5252 | for (i = 2; i < default_reply->MsgLength * 2; i++) { | |
98c56ad3 | 5253 | if ((_base_wait_for_doorbell_int(ioc, 5))) { |
f92363d1 SR |
5254 | pr_err(MPT3SAS_FMT |
5255 | "doorbell handshake int failed (line=%d)\n", | |
5256 | ioc->name, __LINE__); | |
5257 | return -EFAULT; | |
5258 | } | |
5259 | if (i >= reply_bytes/2) /* overflow case */ | |
8bbb1cf6 | 5260 | readl(&ioc->chip->Doorbell); |
f92363d1 | 5261 | else |
cf6bf971 | 5262 | reply[i] = (u16)(readl(&ioc->chip->Doorbell) |
f92363d1 SR |
5263 | & MPI2_DOORBELL_DATA_MASK); |
5264 | writel(0, &ioc->chip->HostInterruptStatus); | |
5265 | } | |
5266 | ||
98c56ad3 CO |
5267 | _base_wait_for_doorbell_int(ioc, 5); |
5268 | if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) { | |
f92363d1 SR |
5269 | dhsprintk(ioc, pr_info(MPT3SAS_FMT |
5270 | "doorbell is in use (line=%d)\n", ioc->name, __LINE__)); | |
5271 | } | |
5272 | writel(0, &ioc->chip->HostInterruptStatus); | |
5273 | ||
5274 | if (ioc->logging_level & MPT_DEBUG_INIT) { | |
5275 | mfp = (__le32 *)reply; | |
5276 | pr_info("\toffset:data\n"); | |
5277 | for (i = 0; i < reply_bytes/4; i++) | |
5278 | pr_info("\t[0x%02x]:%08x\n", i*4, | |
5279 | le32_to_cpu(mfp[i])); | |
5280 | } | |
5281 | return 0; | |
5282 | } | |
5283 | ||
5284 | /** | |
5285 | * mpt3sas_base_sas_iounit_control - send sas iounit control to FW | |
5286 | * @ioc: per adapter object | |
5287 | * @mpi_reply: the reply payload from FW | |
5288 | * @mpi_request: the request payload sent to FW | |
5289 | * | |
5290 | * The SAS IO Unit Control Request message allows the host to perform low-level | |
5291 | * operations, such as resets on the PHYs of the IO Unit, also allows the host | |
5292 | * to obtain the IOC assigned device handles for a device if it has other | |
5293 | * identifying information about the device, in addition allows the host to | |
5294 | * remove IOC resources associated with the device. | |
5295 | * | |
4beb4867 | 5296 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
5297 | */ |
5298 | int | |
5299 | mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc, | |
5300 | Mpi2SasIoUnitControlReply_t *mpi_reply, | |
5301 | Mpi2SasIoUnitControlRequest_t *mpi_request) | |
5302 | { | |
5303 | u16 smid; | |
5304 | u32 ioc_state; | |
d37306ca | 5305 | u8 issue_reset = 0; |
f92363d1 SR |
5306 | int rc; |
5307 | void *request; | |
5308 | u16 wait_state_count; | |
5309 | ||
5310 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
5311 | __func__)); | |
5312 | ||
5313 | mutex_lock(&ioc->base_cmds.mutex); | |
5314 | ||
5315 | if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { | |
5316 | pr_err(MPT3SAS_FMT "%s: base_cmd in use\n", | |
5317 | ioc->name, __func__); | |
5318 | rc = -EAGAIN; | |
5319 | goto out; | |
5320 | } | |
5321 | ||
5322 | wait_state_count = 0; | |
5323 | ioc_state = mpt3sas_base_get_iocstate(ioc, 1); | |
5324 | while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { | |
5325 | if (wait_state_count++ == 10) { | |
5326 | pr_err(MPT3SAS_FMT | |
5327 | "%s: failed due to ioc not operational\n", | |
5328 | ioc->name, __func__); | |
5329 | rc = -EFAULT; | |
5330 | goto out; | |
5331 | } | |
5332 | ssleep(1); | |
5333 | ioc_state = mpt3sas_base_get_iocstate(ioc, 1); | |
5334 | pr_info(MPT3SAS_FMT | |
5335 | "%s: waiting for operational state(count=%d)\n", | |
5336 | ioc->name, __func__, wait_state_count); | |
5337 | } | |
5338 | ||
5339 | smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); | |
5340 | if (!smid) { | |
5341 | pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", | |
5342 | ioc->name, __func__); | |
5343 | rc = -EAGAIN; | |
5344 | goto out; | |
5345 | } | |
5346 | ||
5347 | rc = 0; | |
5348 | ioc->base_cmds.status = MPT3_CMD_PENDING; | |
5349 | request = mpt3sas_base_get_msg_frame(ioc, smid); | |
5350 | ioc->base_cmds.smid = smid; | |
5351 | memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)); | |
5352 | if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || | |
5353 | mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) | |
5354 | ioc->ioc_link_reset_in_progress = 1; | |
5355 | init_completion(&ioc->base_cmds.done); | |
40114bde | 5356 | mpt3sas_base_put_smid_default(ioc, smid); |
8bbb1cf6 | 5357 | wait_for_completion_timeout(&ioc->base_cmds.done, |
f92363d1 SR |
5358 | msecs_to_jiffies(10000)); |
5359 | if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || | |
5360 | mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) && | |
5361 | ioc->ioc_link_reset_in_progress) | |
5362 | ioc->ioc_link_reset_in_progress = 0; | |
5363 | if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { | |
d37306ca C |
5364 | issue_reset = |
5365 | mpt3sas_base_check_cmd_timeout(ioc, | |
5366 | ioc->base_cmds.status, mpi_request, | |
5367 | sizeof(Mpi2SasIoUnitControlRequest_t)/4); | |
f92363d1 SR |
5368 | goto issue_host_reset; |
5369 | } | |
5370 | if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) | |
5371 | memcpy(mpi_reply, ioc->base_cmds.reply, | |
5372 | sizeof(Mpi2SasIoUnitControlReply_t)); | |
5373 | else | |
5374 | memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t)); | |
5375 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; | |
5376 | goto out; | |
5377 | ||
5378 | issue_host_reset: | |
5379 | if (issue_reset) | |
98c56ad3 | 5380 | mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); |
f92363d1 SR |
5381 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; |
5382 | rc = -EFAULT; | |
5383 | out: | |
5384 | mutex_unlock(&ioc->base_cmds.mutex); | |
5385 | return rc; | |
5386 | } | |
5387 | ||
5388 | /** | |
5389 | * mpt3sas_base_scsi_enclosure_processor - sending request to sep device | |
5390 | * @ioc: per adapter object | |
5391 | * @mpi_reply: the reply payload from FW | |
5392 | * @mpi_request: the request payload sent to FW | |
5393 | * | |
5394 | * The SCSI Enclosure Processor request message causes the IOC to | |
5395 | * communicate with SES devices to control LED status signals. | |
5396 | * | |
4beb4867 | 5397 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
5398 | */ |
5399 | int | |
5400 | mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc, | |
5401 | Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request) | |
5402 | { | |
5403 | u16 smid; | |
5404 | u32 ioc_state; | |
d37306ca | 5405 | u8 issue_reset = 0; |
f92363d1 SR |
5406 | int rc; |
5407 | void *request; | |
5408 | u16 wait_state_count; | |
5409 | ||
5410 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
5411 | __func__)); | |
5412 | ||
5413 | mutex_lock(&ioc->base_cmds.mutex); | |
5414 | ||
5415 | if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { | |
5416 | pr_err(MPT3SAS_FMT "%s: base_cmd in use\n", | |
5417 | ioc->name, __func__); | |
5418 | rc = -EAGAIN; | |
5419 | goto out; | |
5420 | } | |
5421 | ||
5422 | wait_state_count = 0; | |
5423 | ioc_state = mpt3sas_base_get_iocstate(ioc, 1); | |
5424 | while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { | |
5425 | if (wait_state_count++ == 10) { | |
5426 | pr_err(MPT3SAS_FMT | |
5427 | "%s: failed due to ioc not operational\n", | |
5428 | ioc->name, __func__); | |
5429 | rc = -EFAULT; | |
5430 | goto out; | |
5431 | } | |
5432 | ssleep(1); | |
5433 | ioc_state = mpt3sas_base_get_iocstate(ioc, 1); | |
5434 | pr_info(MPT3SAS_FMT | |
5435 | "%s: waiting for operational state(count=%d)\n", | |
5436 | ioc->name, | |
5437 | __func__, wait_state_count); | |
5438 | } | |
5439 | ||
5440 | smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); | |
5441 | if (!smid) { | |
5442 | pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", | |
5443 | ioc->name, __func__); | |
5444 | rc = -EAGAIN; | |
5445 | goto out; | |
5446 | } | |
5447 | ||
5448 | rc = 0; | |
5449 | ioc->base_cmds.status = MPT3_CMD_PENDING; | |
5450 | request = mpt3sas_base_get_msg_frame(ioc, smid); | |
5451 | ioc->base_cmds.smid = smid; | |
5452 | memcpy(request, mpi_request, sizeof(Mpi2SepReply_t)); | |
5453 | init_completion(&ioc->base_cmds.done); | |
40114bde | 5454 | mpt3sas_base_put_smid_default(ioc, smid); |
8bbb1cf6 | 5455 | wait_for_completion_timeout(&ioc->base_cmds.done, |
f92363d1 SR |
5456 | msecs_to_jiffies(10000)); |
5457 | if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { | |
d37306ca C |
5458 | issue_reset = |
5459 | mpt3sas_base_check_cmd_timeout(ioc, | |
5460 | ioc->base_cmds.status, mpi_request, | |
5461 | sizeof(Mpi2SepRequest_t)/4); | |
f92363d1 SR |
5462 | goto issue_host_reset; |
5463 | } | |
5464 | if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) | |
5465 | memcpy(mpi_reply, ioc->base_cmds.reply, | |
5466 | sizeof(Mpi2SepReply_t)); | |
5467 | else | |
5468 | memset(mpi_reply, 0, sizeof(Mpi2SepReply_t)); | |
5469 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; | |
5470 | goto out; | |
5471 | ||
5472 | issue_host_reset: | |
5473 | if (issue_reset) | |
98c56ad3 | 5474 | mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); |
f92363d1 SR |
5475 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; |
5476 | rc = -EFAULT; | |
5477 | out: | |
5478 | mutex_unlock(&ioc->base_cmds.mutex); | |
5479 | return rc; | |
5480 | } | |
5481 | ||
5482 | /** | |
5483 | * _base_get_port_facts - obtain port facts reply and save in ioc | |
5484 | * @ioc: per adapter object | |
4beb4867 | 5485 | * @port: ? |
f92363d1 | 5486 | * |
4beb4867 | 5487 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
5488 | */ |
5489 | static int | |
98c56ad3 | 5490 | _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port) |
f92363d1 SR |
5491 | { |
5492 | Mpi2PortFactsRequest_t mpi_request; | |
5493 | Mpi2PortFactsReply_t mpi_reply; | |
5494 | struct mpt3sas_port_facts *pfacts; | |
5495 | int mpi_reply_sz, mpi_request_sz, r; | |
5496 | ||
5497 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
5498 | __func__)); | |
5499 | ||
5500 | mpi_reply_sz = sizeof(Mpi2PortFactsReply_t); | |
5501 | mpi_request_sz = sizeof(Mpi2PortFactsRequest_t); | |
5502 | memset(&mpi_request, 0, mpi_request_sz); | |
5503 | mpi_request.Function = MPI2_FUNCTION_PORT_FACTS; | |
5504 | mpi_request.PortNumber = port; | |
5505 | r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, | |
98c56ad3 | 5506 | (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5); |
f92363d1 SR |
5507 | |
5508 | if (r != 0) { | |
5509 | pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", | |
5510 | ioc->name, __func__, r); | |
5511 | return r; | |
5512 | } | |
5513 | ||
5514 | pfacts = &ioc->pfacts[port]; | |
5515 | memset(pfacts, 0, sizeof(struct mpt3sas_port_facts)); | |
5516 | pfacts->PortNumber = mpi_reply.PortNumber; | |
5517 | pfacts->VP_ID = mpi_reply.VP_ID; | |
5518 | pfacts->VF_ID = mpi_reply.VF_ID; | |
5519 | pfacts->MaxPostedCmdBuffers = | |
5520 | le16_to_cpu(mpi_reply.MaxPostedCmdBuffers); | |
5521 | ||
5522 | return 0; | |
5523 | } | |
5524 | ||
4dc8c808 SR |
5525 | /** |
5526 | * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL | |
5527 | * @ioc: per adapter object | |
5528 | * @timeout: | |
4dc8c808 | 5529 | * |
4beb4867 | 5530 | * Return: 0 for success, non-zero for failure. |
4dc8c808 SR |
5531 | */ |
5532 | static int | |
98c56ad3 | 5533 | _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout) |
4dc8c808 SR |
5534 | { |
5535 | u32 ioc_state; | |
5536 | int rc; | |
5537 | ||
5538 | dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name, | |
5539 | __func__)); | |
5540 | ||
5541 | if (ioc->pci_error_recovery) { | |
5542 | dfailprintk(ioc, printk(MPT3SAS_FMT | |
5543 | "%s: host in pci error recovery\n", ioc->name, __func__)); | |
5544 | return -EFAULT; | |
5545 | } | |
5546 | ||
5547 | ioc_state = mpt3sas_base_get_iocstate(ioc, 0); | |
5548 | dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n", | |
5549 | ioc->name, __func__, ioc_state)); | |
5550 | ||
5551 | if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) || | |
5552 | (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) | |
5553 | return 0; | |
5554 | ||
5555 | if (ioc_state & MPI2_DOORBELL_USED) { | |
5556 | dhsprintk(ioc, printk(MPT3SAS_FMT | |
5557 | "unexpected doorbell active!\n", ioc->name)); | |
5558 | goto issue_diag_reset; | |
5559 | } | |
5560 | ||
5561 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { | |
5562 | mpt3sas_base_fault_info(ioc, ioc_state & | |
5563 | MPI2_DOORBELL_DATA_MASK); | |
5564 | goto issue_diag_reset; | |
5565 | } | |
5566 | ||
98c56ad3 | 5567 | ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout); |
4dc8c808 SR |
5568 | if (ioc_state) { |
5569 | dfailprintk(ioc, printk(MPT3SAS_FMT | |
5570 | "%s: failed going to ready state (ioc_state=0x%x)\n", | |
5571 | ioc->name, __func__, ioc_state)); | |
5572 | return -EFAULT; | |
5573 | } | |
5574 | ||
5575 | issue_diag_reset: | |
98c56ad3 | 5576 | rc = _base_diag_reset(ioc); |
4dc8c808 SR |
5577 | return rc; |
5578 | } | |
5579 | ||
f92363d1 SR |
5580 | /** |
5581 | * _base_get_ioc_facts - obtain ioc facts reply and save in ioc | |
5582 | * @ioc: per adapter object | |
f92363d1 | 5583 | * |
4beb4867 | 5584 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
5585 | */ |
5586 | static int | |
98c56ad3 | 5587 | _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
5588 | { |
5589 | Mpi2IOCFactsRequest_t mpi_request; | |
5590 | Mpi2IOCFactsReply_t mpi_reply; | |
5591 | struct mpt3sas_facts *facts; | |
5592 | int mpi_reply_sz, mpi_request_sz, r; | |
5593 | ||
5594 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
5595 | __func__)); | |
5596 | ||
98c56ad3 | 5597 | r = _base_wait_for_iocstate(ioc, 10); |
4dc8c808 SR |
5598 | if (r) { |
5599 | dfailprintk(ioc, printk(MPT3SAS_FMT | |
5600 | "%s: failed getting to correct state\n", | |
5601 | ioc->name, __func__)); | |
5602 | return r; | |
5603 | } | |
f92363d1 SR |
5604 | mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t); |
5605 | mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t); | |
5606 | memset(&mpi_request, 0, mpi_request_sz); | |
5607 | mpi_request.Function = MPI2_FUNCTION_IOC_FACTS; | |
5608 | r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, | |
98c56ad3 | 5609 | (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5); |
f92363d1 SR |
5610 | |
5611 | if (r != 0) { | |
5612 | pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", | |
5613 | ioc->name, __func__, r); | |
5614 | return r; | |
5615 | } | |
5616 | ||
5617 | facts = &ioc->facts; | |
5618 | memset(facts, 0, sizeof(struct mpt3sas_facts)); | |
5619 | facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion); | |
5620 | facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion); | |
5621 | facts->VP_ID = mpi_reply.VP_ID; | |
5622 | facts->VF_ID = mpi_reply.VF_ID; | |
5623 | facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions); | |
5624 | facts->MaxChainDepth = mpi_reply.MaxChainDepth; | |
5625 | facts->WhoInit = mpi_reply.WhoInit; | |
5626 | facts->NumberOfPorts = mpi_reply.NumberOfPorts; | |
5627 | facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors; | |
2b48be65 C |
5628 | if (ioc->msix_enable && (facts->MaxMSIxVectors <= |
5629 | MAX_COMBINED_MSIX_VECTORS(ioc->is_gen35_ioc))) | |
5630 | ioc->combined_reply_queue = 0; | |
f92363d1 SR |
5631 | facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit); |
5632 | facts->MaxReplyDescriptorPostQueueDepth = | |
5633 | le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth); | |
5634 | facts->ProductID = le16_to_cpu(mpi_reply.ProductID); | |
5635 | facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities); | |
5636 | if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID)) | |
5637 | ioc->ir_firmware = 1; | |
9b05c91a | 5638 | if ((facts->IOCCapabilities & |
06f5f976 | 5639 | MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE) && (!reset_devices)) |
9b05c91a | 5640 | ioc->rdpq_array_capable = 1; |
f92363d1 SR |
5641 | facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word); |
5642 | facts->IOCRequestFrameSize = | |
5643 | le16_to_cpu(mpi_reply.IOCRequestFrameSize); | |
ebb3024e SS |
5644 | if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { |
5645 | facts->IOCMaxChainSegmentSize = | |
5646 | le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize); | |
5647 | } | |
f92363d1 SR |
5648 | facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators); |
5649 | facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets); | |
5650 | ioc->shost->max_id = -1; | |
5651 | facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders); | |
5652 | facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures); | |
5653 | facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags); | |
5654 | facts->HighPriorityCredit = | |
5655 | le16_to_cpu(mpi_reply.HighPriorityCredit); | |
5656 | facts->ReplyFrameSize = mpi_reply.ReplyFrameSize; | |
5657 | facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle); | |
016d5c35 SPS |
5658 | facts->CurrentHostPageSize = mpi_reply.CurrentHostPageSize; |
5659 | ||
5660 | /* | |
5661 | * Get the Page Size from IOC Facts. If it's 0, default to 4k. | |
5662 | */ | |
5663 | ioc->page_size = 1 << facts->CurrentHostPageSize; | |
5664 | if (ioc->page_size == 1) { | |
5665 | pr_info(MPT3SAS_FMT "CurrentHostPageSize is 0: Setting " | |
5666 | "default host page size to 4k\n", ioc->name); | |
5667 | ioc->page_size = 1 << MPT3SAS_HOST_PAGE_SIZE_4K; | |
5668 | } | |
5669 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "CurrentHostPageSize(%d)\n", | |
5670 | ioc->name, facts->CurrentHostPageSize)); | |
f92363d1 SR |
5671 | |
5672 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
5673 | "hba queue depth(%d), max chains per io(%d)\n", | |
5674 | ioc->name, facts->RequestCredit, | |
5675 | facts->MaxChainDepth)); | |
5676 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
5677 | "request frame size(%d), reply frame size(%d)\n", ioc->name, | |
5678 | facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4)); | |
5679 | return 0; | |
5680 | } | |
5681 | ||
5682 | /** | |
5683 | * _base_send_ioc_init - send ioc_init to firmware | |
5684 | * @ioc: per adapter object | |
f92363d1 | 5685 | * |
4beb4867 | 5686 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
5687 | */ |
5688 | static int | |
98c56ad3 | 5689 | _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
5690 | { |
5691 | Mpi2IOCInitRequest_t mpi_request; | |
5692 | Mpi2IOCInitReply_t mpi_reply; | |
9b05c91a | 5693 | int i, r = 0; |
23409bd4 | 5694 | ktime_t current_time; |
f92363d1 | 5695 | u16 ioc_status; |
9b05c91a | 5696 | u32 reply_post_free_array_sz = 0; |
f92363d1 SR |
5697 | |
5698 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
5699 | __func__)); | |
5700 | ||
5701 | memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t)); | |
5702 | mpi_request.Function = MPI2_FUNCTION_IOC_INIT; | |
5703 | mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER; | |
5704 | mpi_request.VF_ID = 0; /* TODO */ | |
5705 | mpi_request.VP_ID = 0; | |
d357e84d | 5706 | mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged); |
f92363d1 | 5707 | mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION); |
016d5c35 | 5708 | mpi_request.HostPageSize = MPT3SAS_HOST_PAGE_SIZE_4K; |
f92363d1 SR |
5709 | |
5710 | if (_base_is_controller_msix_enabled(ioc)) | |
5711 | mpi_request.HostMSIxVectors = ioc->reply_queue_count; | |
5712 | mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4); | |
5713 | mpi_request.ReplyDescriptorPostQueueDepth = | |
5714 | cpu_to_le16(ioc->reply_post_queue_depth); | |
5715 | mpi_request.ReplyFreeQueueDepth = | |
5716 | cpu_to_le16(ioc->reply_free_queue_depth); | |
5717 | ||
5718 | mpi_request.SenseBufferAddressHigh = | |
5719 | cpu_to_le32((u64)ioc->sense_dma >> 32); | |
5720 | mpi_request.SystemReplyAddressHigh = | |
5721 | cpu_to_le32((u64)ioc->reply_dma >> 32); | |
5722 | mpi_request.SystemRequestFrameBaseAddress = | |
5723 | cpu_to_le64((u64)ioc->request_dma); | |
5724 | mpi_request.ReplyFreeQueueAddress = | |
5725 | cpu_to_le64((u64)ioc->reply_free_dma); | |
f92363d1 | 5726 | |
9b05c91a SR |
5727 | if (ioc->rdpq_array_enable) { |
5728 | reply_post_free_array_sz = ioc->reply_queue_count * | |
5729 | sizeof(Mpi2IOCInitRDPQArrayEntry); | |
cd33223b | 5730 | memset(ioc->reply_post_free_array, 0, reply_post_free_array_sz); |
9b05c91a | 5731 | for (i = 0; i < ioc->reply_queue_count; i++) |
cd33223b | 5732 | ioc->reply_post_free_array[i].RDPQBaseAddress = |
9b05c91a SR |
5733 | cpu_to_le64( |
5734 | (u64)ioc->reply_post[i].reply_post_free_dma); | |
5735 | mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE; | |
5736 | mpi_request.ReplyDescriptorPostQueueAddress = | |
cd33223b | 5737 | cpu_to_le64((u64)ioc->reply_post_free_array_dma); |
9b05c91a SR |
5738 | } else { |
5739 | mpi_request.ReplyDescriptorPostQueueAddress = | |
5740 | cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma); | |
5741 | } | |
f92363d1 SR |
5742 | |
5743 | /* This time stamp specifies number of milliseconds | |
5744 | * since epoch ~ midnight January 1, 1970. | |
5745 | */ | |
23409bd4 TR |
5746 | current_time = ktime_get_real(); |
5747 | mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time)); | |
f92363d1 SR |
5748 | |
5749 | if (ioc->logging_level & MPT_DEBUG_INIT) { | |
5750 | __le32 *mfp; | |
5751 | int i; | |
5752 | ||
5753 | mfp = (__le32 *)&mpi_request; | |
5754 | pr_info("\toffset:data\n"); | |
5755 | for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++) | |
5756 | pr_info("\t[0x%02x]:%08x\n", i*4, | |
5757 | le32_to_cpu(mfp[i])); | |
5758 | } | |
5759 | ||
5760 | r = _base_handshake_req_reply_wait(ioc, | |
5761 | sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request, | |
98c56ad3 | 5762 | sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10); |
f92363d1 SR |
5763 | |
5764 | if (r != 0) { | |
5765 | pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", | |
5766 | ioc->name, __func__, r); | |
cd33223b | 5767 | return r; |
f92363d1 SR |
5768 | } |
5769 | ||
5770 | ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK; | |
5771 | if (ioc_status != MPI2_IOCSTATUS_SUCCESS || | |
5772 | mpi_reply.IOCLogInfo) { | |
5773 | pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__); | |
5774 | r = -EIO; | |
5775 | } | |
5776 | ||
9b05c91a | 5777 | return r; |
f92363d1 SR |
5778 | } |
5779 | ||
5780 | /** | |
5781 | * mpt3sas_port_enable_done - command completion routine for port enable | |
5782 | * @ioc: per adapter object | |
5783 | * @smid: system request message index | |
5784 | * @msix_index: MSIX table index supplied by the OS | |
5785 | * @reply: reply message frame(lower 32bit addr) | |
5786 | * | |
4beb4867 BVA |
5787 | * Return: 1 meaning mf should be freed from _base_interrupt |
5788 | * 0 means the mf is freed from this function. | |
f92363d1 SR |
5789 | */ |
5790 | u8 | |
5791 | mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, | |
5792 | u32 reply) | |
5793 | { | |
5794 | MPI2DefaultReply_t *mpi_reply; | |
5795 | u16 ioc_status; | |
5796 | ||
5797 | if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED) | |
5798 | return 1; | |
5799 | ||
5800 | mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); | |
5801 | if (!mpi_reply) | |
5802 | return 1; | |
5803 | ||
5804 | if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE) | |
5805 | return 1; | |
5806 | ||
5807 | ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING; | |
5808 | ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE; | |
5809 | ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID; | |
5810 | memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); | |
5811 | ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; | |
5812 | if (ioc_status != MPI2_IOCSTATUS_SUCCESS) | |
5813 | ioc->port_enable_failed = 1; | |
5814 | ||
5815 | if (ioc->is_driver_loading) { | |
5816 | if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { | |
5817 | mpt3sas_port_enable_complete(ioc); | |
5818 | return 1; | |
5819 | } else { | |
5820 | ioc->start_scan_failed = ioc_status; | |
5821 | ioc->start_scan = 0; | |
5822 | return 1; | |
5823 | } | |
5824 | } | |
5825 | complete(&ioc->port_enable_cmds.done); | |
5826 | return 1; | |
5827 | } | |
5828 | ||
5829 | /** | |
5830 | * _base_send_port_enable - send port_enable(discovery stuff) to firmware | |
5831 | * @ioc: per adapter object | |
f92363d1 | 5832 | * |
4beb4867 | 5833 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
5834 | */ |
5835 | static int | |
98c56ad3 | 5836 | _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
5837 | { |
5838 | Mpi2PortEnableRequest_t *mpi_request; | |
5839 | Mpi2PortEnableReply_t *mpi_reply; | |
f92363d1 SR |
5840 | int r = 0; |
5841 | u16 smid; | |
5842 | u16 ioc_status; | |
5843 | ||
5844 | pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name); | |
5845 | ||
5846 | if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { | |
5847 | pr_err(MPT3SAS_FMT "%s: internal command already in use\n", | |
5848 | ioc->name, __func__); | |
5849 | return -EAGAIN; | |
5850 | } | |
5851 | ||
5852 | smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); | |
5853 | if (!smid) { | |
5854 | pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", | |
5855 | ioc->name, __func__); | |
5856 | return -EAGAIN; | |
5857 | } | |
5858 | ||
5859 | ioc->port_enable_cmds.status = MPT3_CMD_PENDING; | |
5860 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
5861 | ioc->port_enable_cmds.smid = smid; | |
5862 | memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); | |
5863 | mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; | |
5864 | ||
5865 | init_completion(&ioc->port_enable_cmds.done); | |
40114bde | 5866 | mpt3sas_base_put_smid_default(ioc, smid); |
8bbb1cf6 | 5867 | wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ); |
f92363d1 SR |
5868 | if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) { |
5869 | pr_err(MPT3SAS_FMT "%s: timeout\n", | |
5870 | ioc->name, __func__); | |
5871 | _debug_dump_mf(mpi_request, | |
5872 | sizeof(Mpi2PortEnableRequest_t)/4); | |
5873 | if (ioc->port_enable_cmds.status & MPT3_CMD_RESET) | |
5874 | r = -EFAULT; | |
5875 | else | |
5876 | r = -ETIME; | |
5877 | goto out; | |
5878 | } | |
5879 | ||
5880 | mpi_reply = ioc->port_enable_cmds.reply; | |
5881 | ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; | |
5882 | if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { | |
5883 | pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n", | |
5884 | ioc->name, __func__, ioc_status); | |
5885 | r = -EFAULT; | |
5886 | goto out; | |
5887 | } | |
5888 | ||
5889 | out: | |
5890 | ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; | |
5891 | pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ? | |
5892 | "SUCCESS" : "FAILED")); | |
5893 | return r; | |
5894 | } | |
5895 | ||
5896 | /** | |
5897 | * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply) | |
5898 | * @ioc: per adapter object | |
5899 | * | |
4beb4867 | 5900 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
5901 | */ |
5902 | int | |
5903 | mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc) | |
5904 | { | |
5905 | Mpi2PortEnableRequest_t *mpi_request; | |
5906 | u16 smid; | |
5907 | ||
5908 | pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name); | |
5909 | ||
5910 | if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { | |
5911 | pr_err(MPT3SAS_FMT "%s: internal command already in use\n", | |
5912 | ioc->name, __func__); | |
5913 | return -EAGAIN; | |
5914 | } | |
5915 | ||
5916 | smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); | |
5917 | if (!smid) { | |
5918 | pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", | |
5919 | ioc->name, __func__); | |
5920 | return -EAGAIN; | |
5921 | } | |
5922 | ||
5923 | ioc->port_enable_cmds.status = MPT3_CMD_PENDING; | |
5924 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
5925 | ioc->port_enable_cmds.smid = smid; | |
5926 | memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); | |
5927 | mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; | |
5928 | ||
40114bde | 5929 | mpt3sas_base_put_smid_default(ioc, smid); |
f92363d1 SR |
5930 | return 0; |
5931 | } | |
5932 | ||
5933 | /** | |
5934 | * _base_determine_wait_on_discovery - desposition | |
5935 | * @ioc: per adapter object | |
5936 | * | |
5937 | * Decide whether to wait on discovery to complete. Used to either | |
5938 | * locate boot device, or report volumes ahead of physical devices. | |
5939 | * | |
4beb4867 | 5940 | * Return: 1 for wait, 0 for don't wait. |
f92363d1 SR |
5941 | */ |
5942 | static int | |
5943 | _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc) | |
5944 | { | |
5945 | /* We wait for discovery to complete if IR firmware is loaded. | |
5946 | * The sas topology events arrive before PD events, so we need time to | |
5947 | * turn on the bit in ioc->pd_handles to indicate PD | |
5948 | * Also, it maybe required to report Volumes ahead of physical | |
5949 | * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set. | |
5950 | */ | |
5951 | if (ioc->ir_firmware) | |
5952 | return 1; | |
5953 | ||
5954 | /* if no Bios, then we don't need to wait */ | |
5955 | if (!ioc->bios_pg3.BiosVersion) | |
5956 | return 0; | |
5957 | ||
5958 | /* Bios is present, then we drop down here. | |
5959 | * | |
5960 | * If there any entries in the Bios Page 2, then we wait | |
5961 | * for discovery to complete. | |
5962 | */ | |
5963 | ||
5964 | /* Current Boot Device */ | |
5965 | if ((ioc->bios_pg2.CurrentBootDeviceForm & | |
5966 | MPI2_BIOSPAGE2_FORM_MASK) == | |
5967 | MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && | |
5968 | /* Request Boot Device */ | |
5969 | (ioc->bios_pg2.ReqBootDeviceForm & | |
5970 | MPI2_BIOSPAGE2_FORM_MASK) == | |
5971 | MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && | |
5972 | /* Alternate Request Boot Device */ | |
5973 | (ioc->bios_pg2.ReqAltBootDeviceForm & | |
5974 | MPI2_BIOSPAGE2_FORM_MASK) == | |
5975 | MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED) | |
5976 | return 0; | |
5977 | ||
5978 | return 1; | |
5979 | } | |
5980 | ||
5981 | /** | |
5982 | * _base_unmask_events - turn on notification for this event | |
5983 | * @ioc: per adapter object | |
5984 | * @event: firmware event | |
5985 | * | |
5986 | * The mask is stored in ioc->event_masks. | |
5987 | */ | |
5988 | static void | |
5989 | _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event) | |
5990 | { | |
5991 | u32 desired_event; | |
5992 | ||
5993 | if (event >= 128) | |
5994 | return; | |
5995 | ||
5996 | desired_event = (1 << (event % 32)); | |
5997 | ||
5998 | if (event < 32) | |
5999 | ioc->event_masks[0] &= ~desired_event; | |
6000 | else if (event < 64) | |
6001 | ioc->event_masks[1] &= ~desired_event; | |
6002 | else if (event < 96) | |
6003 | ioc->event_masks[2] &= ~desired_event; | |
6004 | else if (event < 128) | |
6005 | ioc->event_masks[3] &= ~desired_event; | |
6006 | } | |
6007 | ||
6008 | /** | |
6009 | * _base_event_notification - send event notification | |
6010 | * @ioc: per adapter object | |
f92363d1 | 6011 | * |
4beb4867 | 6012 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
6013 | */ |
6014 | static int | |
98c56ad3 | 6015 | _base_event_notification(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
6016 | { |
6017 | Mpi2EventNotificationRequest_t *mpi_request; | |
f92363d1 SR |
6018 | u16 smid; |
6019 | int r = 0; | |
6020 | int i; | |
6021 | ||
6022 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
6023 | __func__)); | |
6024 | ||
6025 | if (ioc->base_cmds.status & MPT3_CMD_PENDING) { | |
6026 | pr_err(MPT3SAS_FMT "%s: internal command already in use\n", | |
6027 | ioc->name, __func__); | |
6028 | return -EAGAIN; | |
6029 | } | |
6030 | ||
6031 | smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); | |
6032 | if (!smid) { | |
6033 | pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", | |
6034 | ioc->name, __func__); | |
6035 | return -EAGAIN; | |
6036 | } | |
6037 | ioc->base_cmds.status = MPT3_CMD_PENDING; | |
6038 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
6039 | ioc->base_cmds.smid = smid; | |
6040 | memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t)); | |
6041 | mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; | |
6042 | mpi_request->VF_ID = 0; /* TODO */ | |
6043 | mpi_request->VP_ID = 0; | |
6044 | for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) | |
6045 | mpi_request->EventMasks[i] = | |
6046 | cpu_to_le32(ioc->event_masks[i]); | |
6047 | init_completion(&ioc->base_cmds.done); | |
40114bde | 6048 | mpt3sas_base_put_smid_default(ioc, smid); |
8bbb1cf6 | 6049 | wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ); |
f92363d1 SR |
6050 | if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { |
6051 | pr_err(MPT3SAS_FMT "%s: timeout\n", | |
6052 | ioc->name, __func__); | |
6053 | _debug_dump_mf(mpi_request, | |
6054 | sizeof(Mpi2EventNotificationRequest_t)/4); | |
6055 | if (ioc->base_cmds.status & MPT3_CMD_RESET) | |
6056 | r = -EFAULT; | |
6057 | else | |
6058 | r = -ETIME; | |
6059 | } else | |
6060 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n", | |
6061 | ioc->name, __func__)); | |
6062 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; | |
6063 | return r; | |
6064 | } | |
6065 | ||
6066 | /** | |
6067 | * mpt3sas_base_validate_event_type - validating event types | |
6068 | * @ioc: per adapter object | |
4beb4867 | 6069 | * @event_type: firmware event |
f92363d1 SR |
6070 | * |
6071 | * This will turn on firmware event notification when application | |
6072 | * ask for that event. We don't mask events that are already enabled. | |
6073 | */ | |
6074 | void | |
6075 | mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type) | |
6076 | { | |
6077 | int i, j; | |
6078 | u32 event_mask, desired_event; | |
6079 | u8 send_update_to_fw; | |
6080 | ||
6081 | for (i = 0, send_update_to_fw = 0; i < | |
6082 | MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) { | |
6083 | event_mask = ~event_type[i]; | |
6084 | desired_event = 1; | |
6085 | for (j = 0; j < 32; j++) { | |
6086 | if (!(event_mask & desired_event) && | |
6087 | (ioc->event_masks[i] & desired_event)) { | |
6088 | ioc->event_masks[i] &= ~desired_event; | |
6089 | send_update_to_fw = 1; | |
6090 | } | |
6091 | desired_event = (desired_event << 1); | |
6092 | } | |
6093 | } | |
6094 | ||
6095 | if (!send_update_to_fw) | |
6096 | return; | |
6097 | ||
6098 | mutex_lock(&ioc->base_cmds.mutex); | |
98c56ad3 | 6099 | _base_event_notification(ioc); |
f92363d1 SR |
6100 | mutex_unlock(&ioc->base_cmds.mutex); |
6101 | } | |
6102 | ||
6103 | /** | |
6104 | * _base_diag_reset - the "big hammer" start of day reset | |
6105 | * @ioc: per adapter object | |
f92363d1 | 6106 | * |
4beb4867 | 6107 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
6108 | */ |
6109 | static int | |
98c56ad3 | 6110 | _base_diag_reset(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
6111 | { |
6112 | u32 host_diagnostic; | |
6113 | u32 ioc_state; | |
6114 | u32 count; | |
6115 | u32 hcb_size; | |
6116 | ||
6117 | pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name); | |
6118 | ||
6119 | drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n", | |
6120 | ioc->name)); | |
6121 | ||
6122 | count = 0; | |
6123 | do { | |
6124 | /* Write magic sequence to WriteSequence register | |
6125 | * Loop until in diagnostic mode | |
6126 | */ | |
6127 | drsprintk(ioc, pr_info(MPT3SAS_FMT | |
6128 | "write magic sequence\n", ioc->name)); | |
6129 | writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); | |
6130 | writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence); | |
6131 | writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence); | |
6132 | writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence); | |
6133 | writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence); | |
6134 | writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence); | |
6135 | writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence); | |
6136 | ||
6137 | /* wait 100 msec */ | |
98c56ad3 | 6138 | msleep(100); |
f92363d1 SR |
6139 | |
6140 | if (count++ > 20) | |
6141 | goto out; | |
6142 | ||
6143 | host_diagnostic = readl(&ioc->chip->HostDiagnostic); | |
6144 | drsprintk(ioc, pr_info(MPT3SAS_FMT | |
6145 | "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n", | |
6146 | ioc->name, count, host_diagnostic)); | |
6147 | ||
6148 | } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0); | |
6149 | ||
6150 | hcb_size = readl(&ioc->chip->HCBSize); | |
6151 | ||
6152 | drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n", | |
6153 | ioc->name)); | |
6154 | writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER, | |
6155 | &ioc->chip->HostDiagnostic); | |
6156 | ||
b453ff84 | 6157 | /*This delay allows the chip PCIe hardware time to finish reset tasks*/ |
98c56ad3 | 6158 | msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000); |
f92363d1 | 6159 | |
b453ff84 SR |
6160 | /* Approximately 300 second max wait */ |
6161 | for (count = 0; count < (300000000 / | |
6162 | MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) { | |
f92363d1 SR |
6163 | |
6164 | host_diagnostic = readl(&ioc->chip->HostDiagnostic); | |
6165 | ||
6166 | if (host_diagnostic == 0xFFFFFFFF) | |
6167 | goto out; | |
6168 | if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER)) | |
6169 | break; | |
6170 | ||
98c56ad3 | 6171 | msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000); |
f92363d1 SR |
6172 | } |
6173 | ||
6174 | if (host_diagnostic & MPI2_DIAG_HCB_MODE) { | |
6175 | ||
6176 | drsprintk(ioc, pr_info(MPT3SAS_FMT | |
6177 | "restart the adapter assuming the HCB Address points to good F/W\n", | |
6178 | ioc->name)); | |
6179 | host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK; | |
6180 | host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW; | |
6181 | writel(host_diagnostic, &ioc->chip->HostDiagnostic); | |
6182 | ||
6183 | drsprintk(ioc, pr_info(MPT3SAS_FMT | |
6184 | "re-enable the HCDW\n", ioc->name)); | |
6185 | writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE, | |
6186 | &ioc->chip->HCBSize); | |
6187 | } | |
6188 | ||
6189 | drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n", | |
6190 | ioc->name)); | |
6191 | writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET, | |
6192 | &ioc->chip->HostDiagnostic); | |
6193 | ||
6194 | drsprintk(ioc, pr_info(MPT3SAS_FMT | |
6195 | "disable writes to the diagnostic register\n", ioc->name)); | |
6196 | writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); | |
6197 | ||
6198 | drsprintk(ioc, pr_info(MPT3SAS_FMT | |
6199 | "Wait for FW to go to the READY state\n", ioc->name)); | |
98c56ad3 | 6200 | ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20); |
f92363d1 SR |
6201 | if (ioc_state) { |
6202 | pr_err(MPT3SAS_FMT | |
6203 | "%s: failed going to ready state (ioc_state=0x%x)\n", | |
6204 | ioc->name, __func__, ioc_state); | |
6205 | goto out; | |
6206 | } | |
6207 | ||
6208 | pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name); | |
6209 | return 0; | |
6210 | ||
6211 | out: | |
6212 | pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name); | |
6213 | return -EFAULT; | |
6214 | } | |
6215 | ||
6216 | /** | |
6217 | * _base_make_ioc_ready - put controller in READY state | |
6218 | * @ioc: per adapter object | |
f92363d1 SR |
6219 | * @type: FORCE_BIG_HAMMER or SOFT_RESET |
6220 | * | |
4beb4867 | 6221 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
6222 | */ |
6223 | static int | |
98c56ad3 | 6224 | _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type) |
f92363d1 SR |
6225 | { |
6226 | u32 ioc_state; | |
6227 | int rc; | |
6228 | int count; | |
6229 | ||
6230 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
6231 | __func__)); | |
6232 | ||
6233 | if (ioc->pci_error_recovery) | |
6234 | return 0; | |
6235 | ||
6236 | ioc_state = mpt3sas_base_get_iocstate(ioc, 0); | |
6237 | dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n", | |
6238 | ioc->name, __func__, ioc_state)); | |
6239 | ||
6240 | /* if in RESET state, it should move to READY state shortly */ | |
6241 | count = 0; | |
6242 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { | |
6243 | while ((ioc_state & MPI2_IOC_STATE_MASK) != | |
6244 | MPI2_IOC_STATE_READY) { | |
6245 | if (count++ == 10) { | |
6246 | pr_err(MPT3SAS_FMT | |
6247 | "%s: failed going to ready state (ioc_state=0x%x)\n", | |
6248 | ioc->name, __func__, ioc_state); | |
6249 | return -EFAULT; | |
6250 | } | |
98c56ad3 | 6251 | ssleep(1); |
f92363d1 SR |
6252 | ioc_state = mpt3sas_base_get_iocstate(ioc, 0); |
6253 | } | |
6254 | } | |
6255 | ||
6256 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) | |
6257 | return 0; | |
6258 | ||
6259 | if (ioc_state & MPI2_DOORBELL_USED) { | |
6260 | dhsprintk(ioc, pr_info(MPT3SAS_FMT | |
6261 | "unexpected doorbell active!\n", | |
6262 | ioc->name)); | |
6263 | goto issue_diag_reset; | |
6264 | } | |
6265 | ||
6266 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { | |
6267 | mpt3sas_base_fault_info(ioc, ioc_state & | |
6268 | MPI2_DOORBELL_DATA_MASK); | |
6269 | goto issue_diag_reset; | |
6270 | } | |
6271 | ||
6272 | if (type == FORCE_BIG_HAMMER) | |
6273 | goto issue_diag_reset; | |
6274 | ||
6275 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) | |
6276 | if (!(_base_send_ioc_reset(ioc, | |
98c56ad3 | 6277 | MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) { |
f92363d1 SR |
6278 | return 0; |
6279 | } | |
6280 | ||
6281 | issue_diag_reset: | |
98c56ad3 | 6282 | rc = _base_diag_reset(ioc); |
f92363d1 SR |
6283 | return rc; |
6284 | } | |
6285 | ||
6286 | /** | |
6287 | * _base_make_ioc_operational - put controller in OPERATIONAL state | |
6288 | * @ioc: per adapter object | |
f92363d1 | 6289 | * |
4beb4867 | 6290 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
6291 | */ |
6292 | static int | |
98c56ad3 | 6293 | _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 | 6294 | { |
5ec8a175 | 6295 | int r, i, index; |
f92363d1 SR |
6296 | unsigned long flags; |
6297 | u32 reply_address; | |
6298 | u16 smid; | |
6299 | struct _tr_list *delayed_tr, *delayed_tr_next; | |
fd0331b3 SS |
6300 | struct _sc_list *delayed_sc, *delayed_sc_next; |
6301 | struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next; | |
7786ab6a | 6302 | u8 hide_flag; |
f92363d1 | 6303 | struct adapter_reply_queue *reply_q; |
5ec8a175 | 6304 | Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig; |
f92363d1 SR |
6305 | |
6306 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
6307 | __func__)); | |
6308 | ||
6309 | /* clean the delayed target reset list */ | |
6310 | list_for_each_entry_safe(delayed_tr, delayed_tr_next, | |
6311 | &ioc->delayed_tr_list, list) { | |
6312 | list_del(&delayed_tr->list); | |
6313 | kfree(delayed_tr); | |
6314 | } | |
6315 | ||
6316 | ||
6317 | list_for_each_entry_safe(delayed_tr, delayed_tr_next, | |
6318 | &ioc->delayed_tr_volume_list, list) { | |
6319 | list_del(&delayed_tr->list); | |
6320 | kfree(delayed_tr); | |
6321 | } | |
6322 | ||
fd0331b3 SS |
6323 | list_for_each_entry_safe(delayed_sc, delayed_sc_next, |
6324 | &ioc->delayed_sc_list, list) { | |
6325 | list_del(&delayed_sc->list); | |
6326 | kfree(delayed_sc); | |
6327 | } | |
6328 | ||
6329 | list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next, | |
6330 | &ioc->delayed_event_ack_list, list) { | |
6331 | list_del(&delayed_event_ack->list); | |
6332 | kfree(delayed_event_ack); | |
6333 | } | |
6334 | ||
f92363d1 | 6335 | spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); |
f92363d1 SR |
6336 | |
6337 | /* hi-priority queue */ | |
6338 | INIT_LIST_HEAD(&ioc->hpr_free_list); | |
6339 | smid = ioc->hi_priority_smid; | |
6340 | for (i = 0; i < ioc->hi_priority_depth; i++, smid++) { | |
6341 | ioc->hpr_lookup[i].cb_idx = 0xFF; | |
6342 | ioc->hpr_lookup[i].smid = smid; | |
6343 | list_add_tail(&ioc->hpr_lookup[i].tracker_list, | |
6344 | &ioc->hpr_free_list); | |
6345 | } | |
6346 | ||
6347 | /* internal queue */ | |
6348 | INIT_LIST_HEAD(&ioc->internal_free_list); | |
6349 | smid = ioc->internal_smid; | |
6350 | for (i = 0; i < ioc->internal_depth; i++, smid++) { | |
6351 | ioc->internal_lookup[i].cb_idx = 0xFF; | |
6352 | ioc->internal_lookup[i].smid = smid; | |
6353 | list_add_tail(&ioc->internal_lookup[i].tracker_list, | |
6354 | &ioc->internal_free_list); | |
6355 | } | |
6356 | ||
f92363d1 SR |
6357 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); |
6358 | ||
6359 | /* initialize Reply Free Queue */ | |
6360 | for (i = 0, reply_address = (u32)ioc->reply_dma ; | |
6361 | i < ioc->reply_free_queue_depth ; i++, reply_address += | |
b4472d71 | 6362 | ioc->reply_sz) { |
f92363d1 | 6363 | ioc->reply_free[i] = cpu_to_le32(reply_address); |
b4472d71 SPS |
6364 | if (ioc->is_mcpu_endpoint) |
6365 | _base_clone_reply_to_sys_mem(ioc, | |
cf6bf971 | 6366 | reply_address, i); |
b4472d71 | 6367 | } |
f92363d1 SR |
6368 | |
6369 | /* initialize reply queues */ | |
6370 | if (ioc->is_driver_loading) | |
6371 | _base_assign_reply_queues(ioc); | |
6372 | ||
6373 | /* initialize Reply Post Free Queue */ | |
5ec8a175 CO |
6374 | index = 0; |
6375 | reply_post_free_contig = ioc->reply_post[0].reply_post_free; | |
f92363d1 | 6376 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { |
5ec8a175 CO |
6377 | /* |
6378 | * If RDPQ is enabled, switch to the next allocation. | |
6379 | * Otherwise advance within the contiguous region. | |
6380 | */ | |
6381 | if (ioc->rdpq_array_enable) { | |
6382 | reply_q->reply_post_free = | |
6383 | ioc->reply_post[index++].reply_post_free; | |
6384 | } else { | |
6385 | reply_q->reply_post_free = reply_post_free_contig; | |
6386 | reply_post_free_contig += ioc->reply_post_queue_depth; | |
6387 | } | |
6388 | ||
f92363d1 | 6389 | reply_q->reply_post_host_index = 0; |
f92363d1 SR |
6390 | for (i = 0; i < ioc->reply_post_queue_depth; i++) |
6391 | reply_q->reply_post_free[i].Words = | |
6392 | cpu_to_le64(ULLONG_MAX); | |
6393 | if (!_base_is_controller_msix_enabled(ioc)) | |
6394 | goto skip_init_reply_post_free_queue; | |
f92363d1 SR |
6395 | } |
6396 | skip_init_reply_post_free_queue: | |
6397 | ||
98c56ad3 | 6398 | r = _base_send_ioc_init(ioc); |
f92363d1 SR |
6399 | if (r) |
6400 | return r; | |
6401 | ||
6402 | /* initialize reply free host index */ | |
6403 | ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1; | |
6404 | writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex); | |
6405 | ||
6406 | /* initialize reply post host index */ | |
6407 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { | |
0bb337c9 | 6408 | if (ioc->combined_reply_queue) |
fb77bb53 SR |
6409 | writel((reply_q->msix_index & 7)<< |
6410 | MPI2_RPHI_MSIX_INDEX_SHIFT, | |
6411 | ioc->replyPostRegisterIndex[reply_q->msix_index/8]); | |
6412 | else | |
6413 | writel(reply_q->msix_index << | |
6414 | MPI2_RPHI_MSIX_INDEX_SHIFT, | |
6415 | &ioc->chip->ReplyPostHostIndex); | |
6416 | ||
f92363d1 SR |
6417 | if (!_base_is_controller_msix_enabled(ioc)) |
6418 | goto skip_init_reply_post_host_index; | |
6419 | } | |
6420 | ||
6421 | skip_init_reply_post_host_index: | |
6422 | ||
6423 | _base_unmask_interrupts(ioc); | |
3d29ed85 C |
6424 | |
6425 | if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { | |
6426 | r = _base_display_fwpkg_version(ioc); | |
6427 | if (r) | |
6428 | return r; | |
6429 | } | |
6430 | ||
6431 | _base_static_config_pages(ioc); | |
98c56ad3 | 6432 | r = _base_event_notification(ioc); |
f92363d1 SR |
6433 | if (r) |
6434 | return r; | |
6435 | ||
f92363d1 | 6436 | if (ioc->is_driver_loading) { |
7786ab6a SR |
6437 | |
6438 | if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier | |
6439 | == 0x80) { | |
6440 | hide_flag = (u8) ( | |
6441 | le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) & | |
6442 | MFG_PAGE10_HIDE_SSDS_MASK); | |
6443 | if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK) | |
6444 | ioc->mfg_pg10_hide_flag = hide_flag; | |
6445 | } | |
6446 | ||
f92363d1 SR |
6447 | ioc->wait_for_discovery_to_complete = |
6448 | _base_determine_wait_on_discovery(ioc); | |
6449 | ||
6450 | return r; /* scan_start and scan_finished support */ | |
6451 | } | |
6452 | ||
98c56ad3 | 6453 | r = _base_send_port_enable(ioc); |
f92363d1 SR |
6454 | if (r) |
6455 | return r; | |
6456 | ||
6457 | return r; | |
6458 | } | |
6459 | ||
6460 | /** | |
6461 | * mpt3sas_base_free_resources - free resources controller resources | |
6462 | * @ioc: per adapter object | |
f92363d1 SR |
6463 | */ |
6464 | void | |
6465 | mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc) | |
6466 | { | |
f92363d1 SR |
6467 | dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, |
6468 | __func__)); | |
6469 | ||
08c4d550 SR |
6470 | /* synchronizing freeing resource with pci_access_mutex lock */ |
6471 | mutex_lock(&ioc->pci_access_mutex); | |
cf9bd21a JL |
6472 | if (ioc->chip_phys && ioc->chip) { |
6473 | _base_mask_interrupts(ioc); | |
6474 | ioc->shost_recovery = 1; | |
98c56ad3 | 6475 | _base_make_ioc_ready(ioc, SOFT_RESET); |
cf9bd21a JL |
6476 | ioc->shost_recovery = 0; |
6477 | } | |
6478 | ||
580d4e31 | 6479 | mpt3sas_base_unmap_resources(ioc); |
08c4d550 | 6480 | mutex_unlock(&ioc->pci_access_mutex); |
f92363d1 SR |
6481 | return; |
6482 | } | |
6483 | ||
6484 | /** | |
6485 | * mpt3sas_base_attach - attach controller instance | |
6486 | * @ioc: per adapter object | |
6487 | * | |
4beb4867 | 6488 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
6489 | */ |
6490 | int | |
6491 | mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc) | |
6492 | { | |
6493 | int r, i; | |
6494 | int cpu_id, last_cpu_id = 0; | |
6495 | ||
6496 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
6497 | __func__)); | |
6498 | ||
6499 | /* setup cpu_msix_table */ | |
6500 | ioc->cpu_count = num_online_cpus(); | |
6501 | for_each_online_cpu(cpu_id) | |
6502 | last_cpu_id = cpu_id; | |
6503 | ioc->cpu_msix_table_sz = last_cpu_id + 1; | |
6504 | ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL); | |
6505 | ioc->reply_queue_count = 1; | |
6506 | if (!ioc->cpu_msix_table) { | |
6507 | dfailprintk(ioc, pr_info(MPT3SAS_FMT | |
6508 | "allocation for cpu_msix_table failed!!!\n", | |
6509 | ioc->name)); | |
6510 | r = -ENOMEM; | |
6511 | goto out_free_resources; | |
6512 | } | |
6513 | ||
7786ab6a SR |
6514 | if (ioc->is_warpdrive) { |
6515 | ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz, | |
6516 | sizeof(resource_size_t *), GFP_KERNEL); | |
6517 | if (!ioc->reply_post_host_index) { | |
6518 | dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation " | |
1d55abc0 HR |
6519 | "for reply_post_host_index failed!!!\n", |
6520 | ioc->name)); | |
7786ab6a SR |
6521 | r = -ENOMEM; |
6522 | goto out_free_resources; | |
6523 | } | |
6524 | } | |
6525 | ||
9b05c91a SR |
6526 | ioc->rdpq_array_enable_assigned = 0; |
6527 | ioc->dma_mask = 0; | |
f92363d1 SR |
6528 | r = mpt3sas_base_map_resources(ioc); |
6529 | if (r) | |
6530 | goto out_free_resources; | |
6531 | ||
f92363d1 | 6532 | pci_set_drvdata(ioc->pdev, ioc->shost); |
98c56ad3 | 6533 | r = _base_get_ioc_facts(ioc); |
f92363d1 SR |
6534 | if (r) |
6535 | goto out_free_resources; | |
6536 | ||
471ef9d4 SR |
6537 | switch (ioc->hba_mpi_version_belonged) { |
6538 | case MPI2_VERSION: | |
6539 | ioc->build_sg_scmd = &_base_build_sg_scmd; | |
6540 | ioc->build_sg = &_base_build_sg; | |
6541 | ioc->build_zero_len_sge = &_base_build_zero_len_sge; | |
6542 | break; | |
6543 | case MPI25_VERSION: | |
b130b0d5 | 6544 | case MPI26_VERSION: |
471ef9d4 SR |
6545 | /* |
6546 | * In SAS3.0, | |
6547 | * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and | |
6548 | * Target Status - all require the IEEE formated scatter gather | |
6549 | * elements. | |
6550 | */ | |
6551 | ioc->build_sg_scmd = &_base_build_sg_scmd_ieee; | |
6552 | ioc->build_sg = &_base_build_sg_ieee; | |
aff39e61 | 6553 | ioc->build_nvme_prp = &_base_build_nvme_prp; |
471ef9d4 SR |
6554 | ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee; |
6555 | ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t); | |
81c16f83 | 6556 | |
471ef9d4 SR |
6557 | break; |
6558 | } | |
f92363d1 | 6559 | |
40114bde SP |
6560 | if (ioc->is_mcpu_endpoint) |
6561 | ioc->put_smid_scsi_io = &_base_put_smid_mpi_ep_scsi_io; | |
6562 | else | |
6563 | ioc->put_smid_scsi_io = &_base_put_smid_scsi_io; | |
81c16f83 | 6564 | |
f92363d1 SR |
6565 | /* |
6566 | * These function pointers for other requests that don't | |
6567 | * the require IEEE scatter gather elements. | |
6568 | * | |
6569 | * For example Configuration Pages and SAS IOUNIT Control don't. | |
6570 | */ | |
6571 | ioc->build_sg_mpi = &_base_build_sg; | |
6572 | ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge; | |
6573 | ||
98c56ad3 | 6574 | r = _base_make_ioc_ready(ioc, SOFT_RESET); |
f92363d1 SR |
6575 | if (r) |
6576 | goto out_free_resources; | |
6577 | ||
6578 | ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts, | |
6579 | sizeof(struct mpt3sas_port_facts), GFP_KERNEL); | |
6580 | if (!ioc->pfacts) { | |
6581 | r = -ENOMEM; | |
6582 | goto out_free_resources; | |
6583 | } | |
6584 | ||
6585 | for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) { | |
98c56ad3 | 6586 | r = _base_get_port_facts(ioc, i); |
f92363d1 SR |
6587 | if (r) |
6588 | goto out_free_resources; | |
6589 | } | |
6590 | ||
98c56ad3 | 6591 | r = _base_allocate_memory_pools(ioc); |
f92363d1 SR |
6592 | if (r) |
6593 | goto out_free_resources; | |
6594 | ||
6595 | init_waitqueue_head(&ioc->reset_wq); | |
6596 | ||
6597 | /* allocate memory pd handle bitmask list */ | |
6598 | ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8); | |
6599 | if (ioc->facts.MaxDevHandle % 8) | |
6600 | ioc->pd_handles_sz++; | |
6601 | ioc->pd_handles = kzalloc(ioc->pd_handles_sz, | |
6602 | GFP_KERNEL); | |
6603 | if (!ioc->pd_handles) { | |
6604 | r = -ENOMEM; | |
6605 | goto out_free_resources; | |
6606 | } | |
6607 | ioc->blocking_handles = kzalloc(ioc->pd_handles_sz, | |
6608 | GFP_KERNEL); | |
6609 | if (!ioc->blocking_handles) { | |
6610 | r = -ENOMEM; | |
6611 | goto out_free_resources; | |
6612 | } | |
6613 | ||
c696f7b8 SPS |
6614 | /* allocate memory for pending OS device add list */ |
6615 | ioc->pend_os_device_add_sz = (ioc->facts.MaxDevHandle / 8); | |
6616 | if (ioc->facts.MaxDevHandle % 8) | |
6617 | ioc->pend_os_device_add_sz++; | |
6618 | ioc->pend_os_device_add = kzalloc(ioc->pend_os_device_add_sz, | |
6619 | GFP_KERNEL); | |
6620 | if (!ioc->pend_os_device_add) | |
6621 | goto out_free_resources; | |
6622 | ||
6623 | ioc->device_remove_in_progress_sz = ioc->pend_os_device_add_sz; | |
6624 | ioc->device_remove_in_progress = | |
6625 | kzalloc(ioc->device_remove_in_progress_sz, GFP_KERNEL); | |
6626 | if (!ioc->device_remove_in_progress) | |
6627 | goto out_free_resources; | |
6628 | ||
f92363d1 SR |
6629 | ioc->fwfault_debug = mpt3sas_fwfault_debug; |
6630 | ||
6631 | /* base internal command bits */ | |
6632 | mutex_init(&ioc->base_cmds.mutex); | |
6633 | ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
6634 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; | |
6635 | ||
6636 | /* port_enable command bits */ | |
6637 | ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
6638 | ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; | |
6639 | ||
6640 | /* transport internal command bits */ | |
6641 | ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
6642 | ioc->transport_cmds.status = MPT3_CMD_NOT_USED; | |
6643 | mutex_init(&ioc->transport_cmds.mutex); | |
6644 | ||
6645 | /* scsih internal command bits */ | |
6646 | ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
6647 | ioc->scsih_cmds.status = MPT3_CMD_NOT_USED; | |
6648 | mutex_init(&ioc->scsih_cmds.mutex); | |
6649 | ||
6650 | /* task management internal command bits */ | |
6651 | ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
6652 | ioc->tm_cmds.status = MPT3_CMD_NOT_USED; | |
6653 | mutex_init(&ioc->tm_cmds.mutex); | |
6654 | ||
6655 | /* config page internal command bits */ | |
6656 | ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
6657 | ioc->config_cmds.status = MPT3_CMD_NOT_USED; | |
6658 | mutex_init(&ioc->config_cmds.mutex); | |
6659 | ||
6660 | /* ctl module internal command bits */ | |
6661 | ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
6662 | ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL); | |
6663 | ioc->ctl_cmds.status = MPT3_CMD_NOT_USED; | |
6664 | mutex_init(&ioc->ctl_cmds.mutex); | |
6665 | ||
a5dd7efd CJ |
6666 | if (!ioc->base_cmds.reply || !ioc->port_enable_cmds.reply || |
6667 | !ioc->transport_cmds.reply || !ioc->scsih_cmds.reply || | |
6668 | !ioc->tm_cmds.reply || !ioc->config_cmds.reply || | |
6669 | !ioc->ctl_cmds.reply || !ioc->ctl_cmds.sense) { | |
f92363d1 SR |
6670 | r = -ENOMEM; |
6671 | goto out_free_resources; | |
6672 | } | |
6673 | ||
6674 | for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) | |
6675 | ioc->event_masks[i] = -1; | |
6676 | ||
6677 | /* here we enable the events we care about */ | |
6678 | _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY); | |
6679 | _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE); | |
6680 | _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST); | |
6681 | _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE); | |
6682 | _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE); | |
6683 | _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST); | |
6684 | _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME); | |
6685 | _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK); | |
6686 | _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS); | |
6687 | _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED); | |
2d8ce8c9 | 6688 | _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD); |
b99b1993 | 6689 | _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION); |
95540b8e | 6690 | _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR); |
4318c734 SPS |
6691 | if (ioc->hba_mpi_version_belonged == MPI26_VERSION) { |
6692 | if (ioc->is_gen35_ioc) { | |
6693 | _base_unmask_events(ioc, | |
6694 | MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE); | |
6695 | _base_unmask_events(ioc, MPI2_EVENT_PCIE_ENUMERATION); | |
6696 | _base_unmask_events(ioc, | |
6697 | MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST); | |
6698 | } | |
6699 | } | |
98c56ad3 | 6700 | r = _base_make_ioc_operational(ioc); |
f92363d1 SR |
6701 | if (r) |
6702 | goto out_free_resources; | |
6703 | ||
16e179bd | 6704 | ioc->non_operational_loop = 0; |
459325c4 | 6705 | ioc->got_task_abort_from_ioctl = 0; |
f92363d1 SR |
6706 | return 0; |
6707 | ||
6708 | out_free_resources: | |
6709 | ||
6710 | ioc->remove_host = 1; | |
6711 | ||
6712 | mpt3sas_base_free_resources(ioc); | |
6713 | _base_release_memory_pools(ioc); | |
6714 | pci_set_drvdata(ioc->pdev, NULL); | |
6715 | kfree(ioc->cpu_msix_table); | |
7786ab6a SR |
6716 | if (ioc->is_warpdrive) |
6717 | kfree(ioc->reply_post_host_index); | |
f92363d1 SR |
6718 | kfree(ioc->pd_handles); |
6719 | kfree(ioc->blocking_handles); | |
c696f7b8 SPS |
6720 | kfree(ioc->device_remove_in_progress); |
6721 | kfree(ioc->pend_os_device_add); | |
f92363d1 SR |
6722 | kfree(ioc->tm_cmds.reply); |
6723 | kfree(ioc->transport_cmds.reply); | |
6724 | kfree(ioc->scsih_cmds.reply); | |
6725 | kfree(ioc->config_cmds.reply); | |
6726 | kfree(ioc->base_cmds.reply); | |
6727 | kfree(ioc->port_enable_cmds.reply); | |
6728 | kfree(ioc->ctl_cmds.reply); | |
6729 | kfree(ioc->ctl_cmds.sense); | |
6730 | kfree(ioc->pfacts); | |
6731 | ioc->ctl_cmds.reply = NULL; | |
6732 | ioc->base_cmds.reply = NULL; | |
6733 | ioc->tm_cmds.reply = NULL; | |
6734 | ioc->scsih_cmds.reply = NULL; | |
6735 | ioc->transport_cmds.reply = NULL; | |
6736 | ioc->config_cmds.reply = NULL; | |
6737 | ioc->pfacts = NULL; | |
6738 | return r; | |
6739 | } | |
6740 | ||
6741 | ||
6742 | /** | |
6743 | * mpt3sas_base_detach - remove controller instance | |
6744 | * @ioc: per adapter object | |
f92363d1 SR |
6745 | */ |
6746 | void | |
6747 | mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc) | |
6748 | { | |
6749 | dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
6750 | __func__)); | |
6751 | ||
6752 | mpt3sas_base_stop_watchdog(ioc); | |
6753 | mpt3sas_base_free_resources(ioc); | |
6754 | _base_release_memory_pools(ioc); | |
22a923c3 | 6755 | mpt3sas_free_enclosure_list(ioc); |
f92363d1 SR |
6756 | pci_set_drvdata(ioc->pdev, NULL); |
6757 | kfree(ioc->cpu_msix_table); | |
7786ab6a SR |
6758 | if (ioc->is_warpdrive) |
6759 | kfree(ioc->reply_post_host_index); | |
f92363d1 SR |
6760 | kfree(ioc->pd_handles); |
6761 | kfree(ioc->blocking_handles); | |
c696f7b8 SPS |
6762 | kfree(ioc->device_remove_in_progress); |
6763 | kfree(ioc->pend_os_device_add); | |
f92363d1 SR |
6764 | kfree(ioc->pfacts); |
6765 | kfree(ioc->ctl_cmds.reply); | |
6766 | kfree(ioc->ctl_cmds.sense); | |
6767 | kfree(ioc->base_cmds.reply); | |
6768 | kfree(ioc->port_enable_cmds.reply); | |
6769 | kfree(ioc->tm_cmds.reply); | |
6770 | kfree(ioc->transport_cmds.reply); | |
6771 | kfree(ioc->scsih_cmds.reply); | |
6772 | kfree(ioc->config_cmds.reply); | |
6773 | } | |
6774 | ||
6775 | /** | |
c7a35705 | 6776 | * _base_pre_reset_handler - pre reset handler |
f92363d1 | 6777 | * @ioc: per adapter object |
f92363d1 | 6778 | */ |
c7a35705 | 6779 | static void _base_pre_reset_handler(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 | 6780 | { |
c7a35705 BVA |
6781 | mpt3sas_scsih_pre_reset_handler(ioc); |
6782 | mpt3sas_ctl_pre_reset_handler(ioc); | |
6783 | dtmprintk(ioc, pr_info(MPT3SAS_FMT | |
6784 | "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__)); | |
6785 | } | |
6786 | ||
6787 | /** | |
6788 | * _base_after_reset_handler - after reset handler | |
6789 | * @ioc: per adapter object | |
6790 | */ | |
6791 | static void _base_after_reset_handler(struct MPT3SAS_ADAPTER *ioc) | |
6792 | { | |
6793 | mpt3sas_scsih_after_reset_handler(ioc); | |
6794 | mpt3sas_ctl_after_reset_handler(ioc); | |
6795 | dtmprintk(ioc, pr_info(MPT3SAS_FMT | |
6796 | "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__)); | |
6797 | if (ioc->transport_cmds.status & MPT3_CMD_PENDING) { | |
6798 | ioc->transport_cmds.status |= MPT3_CMD_RESET; | |
6799 | mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid); | |
6800 | complete(&ioc->transport_cmds.done); | |
6801 | } | |
6802 | if (ioc->base_cmds.status & MPT3_CMD_PENDING) { | |
6803 | ioc->base_cmds.status |= MPT3_CMD_RESET; | |
6804 | mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid); | |
6805 | complete(&ioc->base_cmds.done); | |
6806 | } | |
6807 | if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { | |
6808 | ioc->port_enable_failed = 1; | |
6809 | ioc->port_enable_cmds.status |= MPT3_CMD_RESET; | |
6810 | mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid); | |
6811 | if (ioc->is_driver_loading) { | |
6812 | ioc->start_scan_failed = | |
6813 | MPI2_IOCSTATUS_INTERNAL_ERROR; | |
6814 | ioc->start_scan = 0; | |
6815 | ioc->port_enable_cmds.status = | |
6816 | MPT3_CMD_NOT_USED; | |
6817 | } else { | |
6818 | complete(&ioc->port_enable_cmds.done); | |
f92363d1 | 6819 | } |
f92363d1 | 6820 | } |
c7a35705 BVA |
6821 | if (ioc->config_cmds.status & MPT3_CMD_PENDING) { |
6822 | ioc->config_cmds.status |= MPT3_CMD_RESET; | |
6823 | mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid); | |
6824 | ioc->config_cmds.smid = USHRT_MAX; | |
6825 | complete(&ioc->config_cmds.done); | |
6826 | } | |
6827 | } | |
6828 | ||
6829 | /** | |
6830 | * _base_reset_done_handler - reset done handler | |
6831 | * @ioc: per adapter object | |
6832 | */ | |
6833 | static void _base_reset_done_handler(struct MPT3SAS_ADAPTER *ioc) | |
6834 | { | |
6835 | mpt3sas_scsih_reset_done_handler(ioc); | |
6836 | mpt3sas_ctl_reset_done_handler(ioc); | |
6837 | dtmprintk(ioc, pr_info(MPT3SAS_FMT | |
6838 | "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__)); | |
f92363d1 SR |
6839 | } |
6840 | ||
6841 | /** | |
c666d3be | 6842 | * mpt3sas_wait_for_commands_to_complete - reset controller |
f92363d1 | 6843 | * @ioc: Pointer to MPT_ADAPTER structure |
f92363d1 | 6844 | * |
272e253c | 6845 | * This function is waiting 10s for all pending commands to complete |
f92363d1 SR |
6846 | * prior to putting controller in reset. |
6847 | */ | |
c666d3be SR |
6848 | void |
6849 | mpt3sas_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc) | |
f92363d1 SR |
6850 | { |
6851 | u32 ioc_state; | |
f92363d1 SR |
6852 | |
6853 | ioc->pending_io_count = 0; | |
f92363d1 SR |
6854 | |
6855 | ioc_state = mpt3sas_base_get_iocstate(ioc, 0); | |
6856 | if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) | |
6857 | return; | |
6858 | ||
6859 | /* pending command count */ | |
c84b023a | 6860 | ioc->pending_io_count = scsi_host_busy(ioc->shost); |
f92363d1 SR |
6861 | |
6862 | if (!ioc->pending_io_count) | |
6863 | return; | |
6864 | ||
6865 | /* wait for pending commands to complete */ | |
6866 | wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ); | |
6867 | } | |
6868 | ||
6869 | /** | |
6870 | * mpt3sas_base_hard_reset_handler - reset controller | |
6871 | * @ioc: Pointer to MPT_ADAPTER structure | |
f92363d1 SR |
6872 | * @type: FORCE_BIG_HAMMER or SOFT_RESET |
6873 | * | |
4beb4867 | 6874 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
6875 | */ |
6876 | int | |
98c56ad3 | 6877 | mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, |
f92363d1 SR |
6878 | enum reset_type type) |
6879 | { | |
6880 | int r; | |
6881 | unsigned long flags; | |
6882 | u32 ioc_state; | |
6883 | u8 is_fault = 0, is_trigger = 0; | |
6884 | ||
6885 | dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name, | |
6886 | __func__)); | |
6887 | ||
6888 | if (ioc->pci_error_recovery) { | |
6889 | pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n", | |
6890 | ioc->name, __func__); | |
6891 | r = 0; | |
6892 | goto out_unlocked; | |
6893 | } | |
6894 | ||
6895 | if (mpt3sas_fwfault_debug) | |
6896 | mpt3sas_halt_firmware(ioc); | |
6897 | ||
f92363d1 | 6898 | /* wait for an active reset in progress to complete */ |
982ea6f9 | 6899 | mutex_lock(&ioc->reset_in_progress_mutex); |
f92363d1 SR |
6900 | |
6901 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
6902 | ioc->shost_recovery = 1; | |
6903 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
6904 | ||
6905 | if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & | |
6906 | MPT3_DIAG_BUFFER_IS_REGISTERED) && | |
6907 | (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & | |
6908 | MPT3_DIAG_BUFFER_IS_RELEASED))) { | |
6909 | is_trigger = 1; | |
6910 | ioc_state = mpt3sas_base_get_iocstate(ioc, 0); | |
6911 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) | |
6912 | is_fault = 1; | |
6913 | } | |
c7a35705 | 6914 | _base_pre_reset_handler(ioc); |
c666d3be | 6915 | mpt3sas_wait_for_commands_to_complete(ioc); |
f92363d1 | 6916 | _base_mask_interrupts(ioc); |
98c56ad3 | 6917 | r = _base_make_ioc_ready(ioc, type); |
f92363d1 SR |
6918 | if (r) |
6919 | goto out; | |
c7a35705 | 6920 | _base_after_reset_handler(ioc); |
f92363d1 SR |
6921 | |
6922 | /* If this hard reset is called while port enable is active, then | |
6923 | * there is no reason to call make_ioc_operational | |
6924 | */ | |
6925 | if (ioc->is_driver_loading && ioc->port_enable_failed) { | |
6926 | ioc->remove_host = 1; | |
6927 | r = -EFAULT; | |
6928 | goto out; | |
6929 | } | |
98c56ad3 | 6930 | r = _base_get_ioc_facts(ioc); |
f92363d1 SR |
6931 | if (r) |
6932 | goto out; | |
9b05c91a SR |
6933 | |
6934 | if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable) | |
6935 | panic("%s: Issue occurred with flashing controller firmware." | |
6936 | "Please reboot the system and ensure that the correct" | |
6937 | " firmware version is running\n", ioc->name); | |
6938 | ||
98c56ad3 | 6939 | r = _base_make_ioc_operational(ioc); |
f92363d1 | 6940 | if (!r) |
c7a35705 | 6941 | _base_reset_done_handler(ioc); |
f92363d1 SR |
6942 | |
6943 | out: | |
6944 | dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n", | |
6945 | ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED"))); | |
6946 | ||
6947 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
f92363d1 SR |
6948 | ioc->shost_recovery = 0; |
6949 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
6950 | ioc->ioc_reset_count++; | |
6951 | mutex_unlock(&ioc->reset_in_progress_mutex); | |
6952 | ||
6953 | out_unlocked: | |
6954 | if ((r == 0) && is_trigger) { | |
6955 | if (is_fault) | |
6956 | mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT); | |
6957 | else | |
6958 | mpt3sas_trigger_master(ioc, | |
6959 | MASTER_TRIGGER_ADAPTER_RESET); | |
6960 | } | |
6961 | dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name, | |
6962 | __func__)); | |
6963 | return r; | |
6964 | } |