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aic94xx: set an error code on failure
[linux-2.6-block.git] / drivers / scsi / mpt3sas / mpt3sas_base.c
CommitLineData
f92363d1
SR		 1/*
2 * This is the Fusion MPT base driver providing common API layer interface
3 * for access to MPT (Message Passing Technology) firmware.
4 *
5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
a4ffce0d 6 * Copyright (C) 2012-2014 LSI Corporation
a03bd153
SR		 7 * Copyright (C) 2013-2014 Avago Technologies
8 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
f92363d1
SR		 9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * NO WARRANTY
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25 * solely responsible for determining the appropriateness of using and
26 * distributing the Program and assumes all risks associated with its
27 * exercise of rights under this Agreement, including but not limited to
28 * the risks and costs of program errors, damage to or loss of data,
29 * programs or equipment, and unavailability or interruption of operations.
30
31 * DISCLAIMER OF LIABILITY
32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
43 * USA.
44 */
45
f92363d1
SR		 46#include <linux/kernel.h>
47#include <linux/module.h>
48#include <linux/errno.h>
49#include <linux/init.h>
50#include <linux/slab.h>
51#include <linux/types.h>
52#include <linux/pci.h>
53#include <linux/kdev_t.h>
54#include <linux/blkdev.h>
55#include <linux/delay.h>
56#include <linux/interrupt.h>
57#include <linux/dma-mapping.h>
58#include <linux/io.h>
59#include <linux/time.h>
60#include <linux/kthread.h>
61#include <linux/aer.h>
62
63
64#include "mpt3sas_base.h"
65
66static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
67
68
69#define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
70
71 /* maximum controller queue depth */
72#define MAX_HBA_QUEUE_DEPTH 30000
73#define MAX_CHAIN_DEPTH 100000
74static int max_queue_depth = -1;
75module_param(max_queue_depth, int, 0);
76MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
77
78static int max_sgl_entries = -1;
79module_param(max_sgl_entries, int, 0);
80MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
81
82static int msix_disable = -1;
83module_param(msix_disable, int, 0);
84MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
85
9c500060
SR		 86static int max_msix_vectors = 8;
87module_param(max_msix_vectors, int, 0);
88MODULE_PARM_DESC(max_msix_vectors,
89 " max msix vectors - (default=8)");
f92363d1
SR		 90
91static int mpt3sas_fwfault_debug;
92MODULE_PARM_DESC(mpt3sas_fwfault_debug,
93 " enable detection of firmware fault and halt firmware - (default=0)");
94
9b05c91a
SR		 95static int
96_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag);
f92363d1
SR		 97
98/**
99 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
100 *
101 */
102static int
103_scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
104{
105 int ret = param_set_int(val, kp);
106 struct MPT3SAS_ADAPTER *ioc;
107
108 if (ret)
109 return ret;
110
111 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
112 list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
113 ioc->fwfault_debug = mpt3sas_fwfault_debug;
114 return 0;
115}
116module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
117 param_get_int, &mpt3sas_fwfault_debug, 0644);
118
119/**
120 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
121 * @arg: input argument, used to derive ioc
122 *
123 * Return 0 if controller is removed from pci subsystem.
124 * Return -1 for other case.
125 */
126static int mpt3sas_remove_dead_ioc_func(void *arg)
127{
128 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
129 struct pci_dev *pdev;
130
131 if ((ioc == NULL))
132 return -1;
133
134 pdev = ioc->pdev;
135 if ((pdev == NULL))
136 return -1;
64cdb418 137 pci_stop_and_remove_bus_device_locked(pdev);
f92363d1
SR		 138 return 0;
139}
140
141/**
142 * _base_fault_reset_work - workq handling ioc fault conditions
143 * @work: input argument, used to derive ioc
144 * Context: sleep.
145 *
146 * Return nothing.
147 */
148static void
149_base_fault_reset_work(struct work_struct *work)
150{
151 struct MPT3SAS_ADAPTER *ioc =
152 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
153 unsigned long flags;
154 u32 doorbell;
155 int rc;
156 struct task_struct *p;
157
158
159 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
160 if (ioc->shost_recovery)
161 goto rearm_timer;
162 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
163
164 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
165 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
166 pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
167 ioc->name);
168
169 /*
170 * Call _scsih_flush_pending_cmds callback so that we flush all
171 * pending commands back to OS. This call is required to aovid
172 * deadlock at block layer. Dead IOC will fail to do diag reset,
173 * and this call is safe since dead ioc will never return any
174 * command back from HW.
175 */
176 ioc->schedule_dead_ioc_flush_running_cmds(ioc);
177 /*
178 * Set remove_host flag early since kernel thread will
179 * take some time to execute.
180 */
181 ioc->remove_host = 1;
182 /*Remove the Dead Host */
183 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
184 "mpt3sas_dead_ioc_%d", ioc->id);
185 if (IS_ERR(p))
186 pr_err(MPT3SAS_FMT
187 "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
188 ioc->name, __func__);
189 else
190 pr_err(MPT3SAS_FMT
191 "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
192 ioc->name, __func__);
193 return; /* don't rearm timer */
194 }
195
196 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
197 rc = mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
198 FORCE_BIG_HAMMER);
199 pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
200 __func__, (rc == 0) ? "success" : "failed");
201 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
202 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
203 mpt3sas_base_fault_info(ioc, doorbell &
204 MPI2_DOORBELL_DATA_MASK);
205 if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
206 MPI2_IOC_STATE_OPERATIONAL)
207 return; /* don't rearm timer */
208 }
209
210 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
211 rearm_timer:
212 if (ioc->fault_reset_work_q)
213 queue_delayed_work(ioc->fault_reset_work_q,
214 &ioc->fault_reset_work,
215 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
216 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
217}
218
219/**
220 * mpt3sas_base_start_watchdog - start the fault_reset_work_q
221 * @ioc: per adapter object
222 * Context: sleep.
223 *
224 * Return nothing.
225 */
226void
227mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
228{
229 unsigned long flags;
230
231 if (ioc->fault_reset_work_q)
232 return;
233
234 /* initialize fault polling */
235
236 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
237 snprintf(ioc->fault_reset_work_q_name,
238 sizeof(ioc->fault_reset_work_q_name), "poll_%d_status", ioc->id);
239 ioc->fault_reset_work_q =
240 create_singlethread_workqueue(ioc->fault_reset_work_q_name);
241 if (!ioc->fault_reset_work_q) {
242 pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
243 ioc->name, __func__, __LINE__);
244 return;
245 }
246 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
247 if (ioc->fault_reset_work_q)
248 queue_delayed_work(ioc->fault_reset_work_q,
249 &ioc->fault_reset_work,
250 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
251 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
252}
253
254/**
255 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
256 * @ioc: per adapter object
257 * Context: sleep.
258 *
259 * Return nothing.
260 */
261void
262mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
263{
264 unsigned long flags;
265 struct workqueue_struct *wq;
266
267 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
268 wq = ioc->fault_reset_work_q;
269 ioc->fault_reset_work_q = NULL;
270 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
271 if (wq) {
4dc06fd8 272 if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
f92363d1
SR		 273 flush_workqueue(wq);
274 destroy_workqueue(wq);
275 }
276}
277
278/**
279 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
280 * @ioc: per adapter object
281 * @fault_code: fault code
282 *
283 * Return nothing.
284 */
285void
286mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
287{
288 pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
289 ioc->name, fault_code);
290}
291
292/**
293 * mpt3sas_halt_firmware - halt's mpt controller firmware
294 * @ioc: per adapter object
295 *
296 * For debugging timeout related issues. Writing 0xCOFFEE00
297 * to the doorbell register will halt controller firmware. With
298 * the purpose to stop both driver and firmware, the enduser can
299 * obtain a ring buffer from controller UART.
300 */
301void
302mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
303{
304 u32 doorbell;
305
306 if (!ioc->fwfault_debug)
307 return;
308
309 dump_stack();
310
311 doorbell = readl(&ioc->chip->Doorbell);
312 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
313 mpt3sas_base_fault_info(ioc , doorbell);
314 else {
315 writel(0xC0FFEE00, &ioc->chip->Doorbell);
316 pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
317 ioc->name);
318 }
319
320 if (ioc->fwfault_debug == 2)
321 for (;;)
322 ;
323 else
324 panic("panic in %s\n", __func__);
325}
326
327#ifdef CONFIG_SCSI_MPT3SAS_LOGGING
328/**
329 * _base_sas_ioc_info - verbose translation of the ioc status
330 * @ioc: per adapter object
331 * @mpi_reply: reply mf payload returned from firmware
332 * @request_hdr: request mf
333 *
334 * Return nothing.
335 */
336static void
337_base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
338 MPI2RequestHeader_t *request_hdr)
339{
340 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
341 MPI2_IOCSTATUS_MASK;
342 char *desc = NULL;
343 u16 frame_sz;
344 char *func_str = NULL;
345
346 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
347 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
348 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
349 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
350 return;
351
352 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
353 return;
354
355 switch (ioc_status) {
356
357/****************************************************************************
358* Common IOCStatus values for all replies
359****************************************************************************/
360
361 case MPI2_IOCSTATUS_INVALID_FUNCTION:
362 desc = "invalid function";
363 break;
364 case MPI2_IOCSTATUS_BUSY:
365 desc = "busy";
366 break;
367 case MPI2_IOCSTATUS_INVALID_SGL:
368 desc = "invalid sgl";
369 break;
370 case MPI2_IOCSTATUS_INTERNAL_ERROR:
371 desc = "internal error";
372 break;
373 case MPI2_IOCSTATUS_INVALID_VPID:
374 desc = "invalid vpid";
375 break;
376 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
377 desc = "insufficient resources";
378 break;
379 case MPI2_IOCSTATUS_INVALID_FIELD:
380 desc = "invalid field";
381 break;
382 case MPI2_IOCSTATUS_INVALID_STATE:
383 desc = "invalid state";
384 break;
385 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
386 desc = "op state not supported";
387 break;
388
389/****************************************************************************
390* Config IOCStatus values
391****************************************************************************/
392
393 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
394 desc = "config invalid action";
395 break;
396 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
397 desc = "config invalid type";
398 break;
399 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
400 desc = "config invalid page";
401 break;
402 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
403 desc = "config invalid data";
404 break;
405 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
406 desc = "config no defaults";
407 break;
408 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
409 desc = "config cant commit";
410 break;
411
412/****************************************************************************
413* SCSI IO Reply
414****************************************************************************/
415
416 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
417 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
418 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
419 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
420 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
421 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
422 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
423 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
424 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
425 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
426 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
427 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
428 break;
429
430/****************************************************************************
431* For use by SCSI Initiator and SCSI Target end-to-end data protection
432****************************************************************************/
433
434 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
435 desc = "eedp guard error";
436 break;
437 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
438 desc = "eedp ref tag error";
439 break;
440 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
441 desc = "eedp app tag error";
442 break;
443
444/****************************************************************************
445* SCSI Target values
446****************************************************************************/
447
448 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
449 desc = "target invalid io index";
450 break;
451 case MPI2_IOCSTATUS_TARGET_ABORTED:
452 desc = "target aborted";
453 break;
454 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
455 desc = "target no conn retryable";
456 break;
457 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
458 desc = "target no connection";
459 break;
460 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
461 desc = "target xfer count mismatch";
462 break;
463 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
464 desc = "target data offset error";
465 break;
466 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
467 desc = "target too much write data";
468 break;
469 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
470 desc = "target iu too short";
471 break;
472 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
473 desc = "target ack nak timeout";
474 break;
475 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
476 desc = "target nak received";
477 break;
478
479/****************************************************************************
480* Serial Attached SCSI values
481****************************************************************************/
482
483 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
484 desc = "smp request failed";
485 break;
486 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
487 desc = "smp data overrun";
488 break;
489
490/****************************************************************************
491* Diagnostic Buffer Post / Diagnostic Release values
492****************************************************************************/
493
494 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
495 desc = "diagnostic released";
496 break;
497 default:
498 break;
499 }
500
501 if (!desc)
502 return;
503
504 switch (request_hdr->Function) {
505 case MPI2_FUNCTION_CONFIG:
506 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
507 func_str = "config_page";
508 break;
509 case MPI2_FUNCTION_SCSI_TASK_MGMT:
510 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
511 func_str = "task_mgmt";
512 break;
513 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
514 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
515 func_str = "sas_iounit_ctl";
516 break;
517 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
518 frame_sz = sizeof(Mpi2SepRequest_t);
519 func_str = "enclosure";
520 break;
521 case MPI2_FUNCTION_IOC_INIT:
522 frame_sz = sizeof(Mpi2IOCInitRequest_t);
523 func_str = "ioc_init";
524 break;
525 case MPI2_FUNCTION_PORT_ENABLE:
526 frame_sz = sizeof(Mpi2PortEnableRequest_t);
527 func_str = "port_enable";
528 break;
529 case MPI2_FUNCTION_SMP_PASSTHROUGH:
530 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
531 func_str = "smp_passthru";
532 break;
533 default:
534 frame_sz = 32;
535 func_str = "unknown";
536 break;
537 }
538
539 pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
540 ioc->name, desc, ioc_status, request_hdr, func_str);
541
542 _debug_dump_mf(request_hdr, frame_sz/4);
543}
544
545/**
546 * _base_display_event_data - verbose translation of firmware asyn events
547 * @ioc: per adapter object
548 * @mpi_reply: reply mf payload returned from firmware
549 *
550 * Return nothing.
551 */
552static void
553_base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
554 Mpi2EventNotificationReply_t *mpi_reply)
555{
556 char *desc = NULL;
557 u16 event;
558
559 if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
560 return;
561
562 event = le16_to_cpu(mpi_reply->Event);
563
564 switch (event) {
565 case MPI2_EVENT_LOG_DATA:
566 desc = "Log Data";
567 break;
568 case MPI2_EVENT_STATE_CHANGE:
569 desc = "Status Change";
570 break;
571 case MPI2_EVENT_HARD_RESET_RECEIVED:
572 desc = "Hard Reset Received";
573 break;
574 case MPI2_EVENT_EVENT_CHANGE:
575 desc = "Event Change";
576 break;
577 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
578 desc = "Device Status Change";
579 break;
580 case MPI2_EVENT_IR_OPERATION_STATUS:
581 desc = "IR Operation Status";
582 break;
583 case MPI2_EVENT_SAS_DISCOVERY:
584 {
585 Mpi2EventDataSasDiscovery_t *event_data =
586 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
587 pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
588 (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
589 "start" : "stop");
590 if (event_data->DiscoveryStatus)
591 pr_info("discovery_status(0x%08x)",
592 le32_to_cpu(event_data->DiscoveryStatus));
593 pr_info("\n");
594 return;
595 }
596 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
597 desc = "SAS Broadcast Primitive";
598 break;
599 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
600 desc = "SAS Init Device Status Change";
601 break;
602 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
603 desc = "SAS Init Table Overflow";
604 break;
605 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
606 desc = "SAS Topology Change List";
607 break;
608 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
609 desc = "SAS Enclosure Device Status Change";
610 break;
611 case MPI2_EVENT_IR_VOLUME:
612 desc = "IR Volume";
613 break;
614 case MPI2_EVENT_IR_PHYSICAL_DISK:
615 desc = "IR Physical Disk";
616 break;
617 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
618 desc = "IR Configuration Change List";
619 break;
620 case MPI2_EVENT_LOG_ENTRY_ADDED:
621 desc = "Log Entry Added";
622 break;
2d8ce8c9
SR		 623 case MPI2_EVENT_TEMP_THRESHOLD:
624 desc = "Temperature Threshold";
625 break;
f92363d1
SR		 626 }
627
628 if (!desc)
629 return;
630
631 pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
632}
633#endif
634
635/**
636 * _base_sas_log_info - verbose translation of firmware log info
637 * @ioc: per adapter object
638 * @log_info: log info
639 *
640 * Return nothing.
641 */
642static void
643_base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
644{
645 union loginfo_type {
646 u32 loginfo;
647 struct {
648 u32 subcode:16;
649 u32 code:8;
650 u32 originator:4;
651 u32 bus_type:4;
652 } dw;
653 };
654 union loginfo_type sas_loginfo;
655 char *originator_str = NULL;
656
657 sas_loginfo.loginfo = log_info;
658 if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
659 return;
660
661 /* each nexus loss loginfo */
662 if (log_info == 0x31170000)
663 return;
664
665 /* eat the loginfos associated with task aborts */
666 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
667 0x31140000 || log_info == 0x31130000))
668 return;
669
670 switch (sas_loginfo.dw.originator) {
671 case 0:
672 originator_str = "IOP";
673 break;
674 case 1:
675 originator_str = "PL";
676 break;
677 case 2:
678 originator_str = "IR";
679 break;
680 }
681
682 pr_warn(MPT3SAS_FMT
683 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
684 ioc->name, log_info,
685 originator_str, sas_loginfo.dw.code,
686 sas_loginfo.dw.subcode);
687}
688
689/**
690 * _base_display_reply_info -
691 * @ioc: per adapter object
692 * @smid: system request message index
693 * @msix_index: MSIX table index supplied by the OS
694 * @reply: reply message frame(lower 32bit addr)
695 *
696 * Return nothing.
697 */
698static void
699_base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
700 u32 reply)
701{
702 MPI2DefaultReply_t *mpi_reply;
703 u16 ioc_status;
704 u32 loginfo = 0;
705
706 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
707 if (unlikely(!mpi_reply)) {
708 pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
709 ioc->name, __FILE__, __LINE__, __func__);
710 return;
711 }
712 ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
713#ifdef CONFIG_SCSI_MPT3SAS_LOGGING
714 if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
715 (ioc->logging_level & MPT_DEBUG_REPLY)) {
716 _base_sas_ioc_info(ioc , mpi_reply,
717 mpt3sas_base_get_msg_frame(ioc, smid));
718 }
719#endif
720 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
721 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
722 _base_sas_log_info(ioc, loginfo);
723 }
724
725 if (ioc_status || loginfo) {
726 ioc_status &= MPI2_IOCSTATUS_MASK;
727 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
728 }
729}
730
731/**
732 * mpt3sas_base_done - base internal command completion routine
733 * @ioc: per adapter object
734 * @smid: system request message index
735 * @msix_index: MSIX table index supplied by the OS
736 * @reply: reply message frame(lower 32bit addr)
737 *
738 * Return 1 meaning mf should be freed from _base_interrupt
739 * 0 means the mf is freed from this function.
740 */
741u8
742mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
743 u32 reply)
744{
745 MPI2DefaultReply_t *mpi_reply;
746
747 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
748 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
749 return 1;
750
751 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
752 return 1;
753
754 ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
755 if (mpi_reply) {
756 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
757 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
758 }
759 ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
760
761 complete(&ioc->base_cmds.done);
762 return 1;
763}
764
765/**
766 * _base_async_event - main callback handler for firmware asyn events
767 * @ioc: per adapter object
768 * @msix_index: MSIX table index supplied by the OS
769 * @reply: reply message frame(lower 32bit addr)
770 *
771 * Return 1 meaning mf should be freed from _base_interrupt
772 * 0 means the mf is freed from this function.
773 */
774static u8
775_base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
776{
777 Mpi2EventNotificationReply_t *mpi_reply;
778 Mpi2EventAckRequest_t *ack_request;
779 u16 smid;
780
781 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
782 if (!mpi_reply)
783 return 1;
784 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
785 return 1;
786#ifdef CONFIG_SCSI_MPT3SAS_LOGGING
787 _base_display_event_data(ioc, mpi_reply);
788#endif
789 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
790 goto out;
791 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
792 if (!smid) {
793 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
794 ioc->name, __func__);
795 goto out;
796 }
797
798 ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
799 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
800 ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
801 ack_request->Event = mpi_reply->Event;
802 ack_request->EventContext = mpi_reply->EventContext;
803 ack_request->VF_ID = 0; /* TODO */
804 ack_request->VP_ID = 0;
805 mpt3sas_base_put_smid_default(ioc, smid);
806
807 out:
808
809 /* scsih callback handler */
810 mpt3sas_scsih_event_callback(ioc, msix_index, reply);
811
812 /* ctl callback handler */
813 mpt3sas_ctl_event_callback(ioc, msix_index, reply);
814
815 return 1;
816}
817
818/**
819 * _base_get_cb_idx - obtain the callback index
820 * @ioc: per adapter object
821 * @smid: system request message index
822 *
823 * Return callback index.
824 */
825static u8
826_base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
827{
828 int i;
829 u8 cb_idx;
830
831 if (smid < ioc->hi_priority_smid) {
832 i = smid - 1;
833 cb_idx = ioc->scsi_lookup[i].cb_idx;
834 } else if (smid < ioc->internal_smid) {
835 i = smid - ioc->hi_priority_smid;
836 cb_idx = ioc->hpr_lookup[i].cb_idx;
837 } else if (smid <= ioc->hba_queue_depth) {
838 i = smid - ioc->internal_smid;
839 cb_idx = ioc->internal_lookup[i].cb_idx;
840 } else
841 cb_idx = 0xFF;
842 return cb_idx;
843}
844
845/**
846 * _base_mask_interrupts - disable interrupts
847 * @ioc: per adapter object
848 *
849 * Disabling ResetIRQ, Reply and Doorbell Interrupts
850 *
851 * Return nothing.
852 */
853static void
854_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
855{
856 u32 him_register;
857
858 ioc->mask_interrupts = 1;
859 him_register = readl(&ioc->chip->HostInterruptMask);
860 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
861 writel(him_register, &ioc->chip->HostInterruptMask);
862 readl(&ioc->chip->HostInterruptMask);
863}
864
865/**
866 * _base_unmask_interrupts - enable interrupts
867 * @ioc: per adapter object
868 *
869 * Enabling only Reply Interrupts
870 *
871 * Return nothing.
872 */
873static void
874_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
875{
876 u32 him_register;
877
878 him_register = readl(&ioc->chip->HostInterruptMask);
879 him_register &= ~MPI2_HIM_RIM;
880 writel(him_register, &ioc->chip->HostInterruptMask);
881 ioc->mask_interrupts = 0;
882}
883
884union reply_descriptor {
885 u64 word;
886 struct {
887 u32 low;
888 u32 high;
889 } u;
890};
891
892/**
893 * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
894 * @irq: irq number (not used)
895 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
896 * @r: pt_regs pointer (not used)
897 *
898 * Return IRQ_HANDLE if processed, else IRQ_NONE.
899 */
900static irqreturn_t
901_base_interrupt(int irq, void *bus_id)
902{
903 struct adapter_reply_queue *reply_q = bus_id;
904 union reply_descriptor rd;
905 u32 completed_cmds;
906 u8 request_desript_type;
907 u16 smid;
908 u8 cb_idx;
909 u32 reply;
910 u8 msix_index = reply_q->msix_index;
911 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
912 Mpi2ReplyDescriptorsUnion_t *rpf;
913 u8 rc;
914
915 if (ioc->mask_interrupts)
916 return IRQ_NONE;
917
918 if (!atomic_add_unless(&reply_q->busy, 1, 1))
919 return IRQ_NONE;
920
921 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
922 request_desript_type = rpf->Default.ReplyFlags
923 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
924 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
925 atomic_dec(&reply_q->busy);
926 return IRQ_NONE;
927 }
928
929 completed_cmds = 0;
930 cb_idx = 0xFF;
931 do {
932 rd.word = le64_to_cpu(rpf->Words);
933 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
934 goto out;
935 reply = 0;
936 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
937 if (request_desript_type ==
938 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
939 request_desript_type ==
940 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
941 cb_idx = _base_get_cb_idx(ioc, smid);
942 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
943 (likely(mpt_callbacks[cb_idx] != NULL))) {
944 rc = mpt_callbacks[cb_idx](ioc, smid,
945 msix_index, 0);
946 if (rc)
947 mpt3sas_base_free_smid(ioc, smid);
948 }
949 } else if (request_desript_type ==
950 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
951 reply = le32_to_cpu(
952 rpf->AddressReply.ReplyFrameAddress);
953 if (reply > ioc->reply_dma_max_address ||
954 reply < ioc->reply_dma_min_address)
955 reply = 0;
956 if (smid) {
957 cb_idx = _base_get_cb_idx(ioc, smid);
958 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
959 (likely(mpt_callbacks[cb_idx] != NULL))) {
960 rc = mpt_callbacks[cb_idx](ioc, smid,
961 msix_index, reply);
962 if (reply)
963 _base_display_reply_info(ioc,
964 smid, msix_index, reply);
965 if (rc)
966 mpt3sas_base_free_smid(ioc,
967 smid);
968 }
969 } else {
970 _base_async_event(ioc, msix_index, reply);
971 }
972
973 /* reply free queue handling */
974 if (reply) {
975 ioc->reply_free_host_index =
976 (ioc->reply_free_host_index ==
977 (ioc->reply_free_queue_depth - 1)) ?
978 0 : ioc->reply_free_host_index + 1;
979 ioc->reply_free[ioc->reply_free_host_index] =
980 cpu_to_le32(reply);
981 wmb();
982 writel(ioc->reply_free_host_index,
983 &ioc->chip->ReplyFreeHostIndex);
984 }
985 }
986
987 rpf->Words = cpu_to_le64(ULLONG_MAX);
988 reply_q->reply_post_host_index =
989 (reply_q->reply_post_host_index ==
990 (ioc->reply_post_queue_depth - 1)) ? 0 :
991 reply_q->reply_post_host_index + 1;
992 request_desript_type =
993 reply_q->reply_post_free[reply_q->reply_post_host_index].
994 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
995 completed_cmds++;
996 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
997 goto out;
998 if (!reply_q->reply_post_host_index)
999 rpf = reply_q->reply_post_free;
1000 else
1001 rpf++;
1002 } while (1);
1003
1004 out:
1005
1006 if (!completed_cmds) {
1007 atomic_dec(&reply_q->busy);
1008 return IRQ_NONE;
1009 }
1010
1011 wmb();
1012 writel(reply_q->reply_post_host_index | (msix_index <<
1013 MPI2_RPHI_MSIX_INDEX_SHIFT), &ioc->chip->ReplyPostHostIndex);
1014 atomic_dec(&reply_q->busy);
1015 return IRQ_HANDLED;
1016}
1017
1018/**
1019 * _base_is_controller_msix_enabled - is controller support muli-reply queues
1020 * @ioc: per adapter object
1021 *
1022 */
1023static inline int
1024_base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1025{
1026 return (ioc->facts.IOCCapabilities &
1027 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1028}
1029
1030/**
1031 * mpt3sas_base_flush_reply_queues - flushing the MSIX reply queues
1032 * @ioc: per adapter object
1033 * Context: ISR conext
1034 *
1035 * Called when a Task Management request has completed. We want
1036 * to flush the other reply queues so all the outstanding IO has been
1037 * completed back to OS before we process the TM completetion.
1038 *
1039 * Return nothing.
1040 */
1041void
1042mpt3sas_base_flush_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1043{
1044 struct adapter_reply_queue *reply_q;
1045
1046 /* If MSIX capability is turned off
1047 * then multi-queues are not enabled
1048 */
1049 if (!_base_is_controller_msix_enabled(ioc))
1050 return;
1051
1052 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1053 if (ioc->shost_recovery)
1054 return;
1055 /* TMs are on msix_index == 0 */
1056 if (reply_q->msix_index == 0)
1057 continue;
1058 _base_interrupt(reply_q->vector, (void *)reply_q);
1059 }
1060}
1061
1062/**
1063 * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1064 * @cb_idx: callback index
1065 *
1066 * Return nothing.
1067 */
1068void
1069mpt3sas_base_release_callback_handler(u8 cb_idx)
1070{
1071 mpt_callbacks[cb_idx] = NULL;
1072}
1073
1074/**
1075 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1076 * @cb_func: callback function
1077 *
1078 * Returns cb_func.
1079 */
1080u8
1081mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1082{
1083 u8 cb_idx;
1084
1085 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1086 if (mpt_callbacks[cb_idx] == NULL)
1087 break;
1088
1089 mpt_callbacks[cb_idx] = cb_func;
1090 return cb_idx;
1091}
1092
1093/**
1094 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1095 *
1096 * Return nothing.
1097 */
1098void
1099mpt3sas_base_initialize_callback_handler(void)
1100{
1101 u8 cb_idx;
1102
1103 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1104 mpt3sas_base_release_callback_handler(cb_idx);
1105}
1106
1107
1108/**
1109 * _base_build_zero_len_sge - build zero length sg entry
1110 * @ioc: per adapter object
1111 * @paddr: virtual address for SGE
1112 *
1113 * Create a zero length scatter gather entry to insure the IOCs hardware has
1114 * something to use if the target device goes brain dead and tries
1115 * to send data even when none is asked for.
1116 *
1117 * Return nothing.
1118 */
1119static void
1120_base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1121{
1122 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1123 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1124 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1125 MPI2_SGE_FLAGS_SHIFT);
1126 ioc->base_add_sg_single(paddr, flags_length, -1);
1127}
1128
1129/**
1130 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1131 * @paddr: virtual address for SGE
1132 * @flags_length: SGE flags and data transfer length
1133 * @dma_addr: Physical address
1134 *
1135 * Return nothing.
1136 */
1137static void
1138_base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1139{
1140 Mpi2SGESimple32_t *sgel = paddr;
1141
1142 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1143 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1144 sgel->FlagsLength = cpu_to_le32(flags_length);
1145 sgel->Address = cpu_to_le32(dma_addr);
1146}
1147
1148
1149/**
1150 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
1151 * @paddr: virtual address for SGE
1152 * @flags_length: SGE flags and data transfer length
1153 * @dma_addr: Physical address
1154 *
1155 * Return nothing.
1156 */
1157static void
1158_base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1159{
1160 Mpi2SGESimple64_t *sgel = paddr;
1161
1162 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
1163 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1164 sgel->FlagsLength = cpu_to_le32(flags_length);
1165 sgel->Address = cpu_to_le64(dma_addr);
1166}
1167
1168/**
1169 * _base_get_chain_buffer_tracker - obtain chain tracker
1170 * @ioc: per adapter object
1171 * @smid: smid associated to an IO request
1172 *
1173 * Returns chain tracker(from ioc->free_chain_list)
1174 */
1175static struct chain_tracker *
1176_base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1177{
1178 struct chain_tracker *chain_req;
1179 unsigned long flags;
1180
1181 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1182 if (list_empty(&ioc->free_chain_list)) {
1183 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1184 dfailprintk(ioc, pr_warn(MPT3SAS_FMT
1185 "chain buffers not available\n", ioc->name));
1186 return NULL;
1187 }
1188 chain_req = list_entry(ioc->free_chain_list.next,
1189 struct chain_tracker, tracker_list);
1190 list_del_init(&chain_req->tracker_list);
1191 list_add_tail(&chain_req->tracker_list,
1192 &ioc->scsi_lookup[smid - 1].chain_list);
1193 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1194 return chain_req;
1195}
1196
1197
1198/**
1199 * _base_build_sg - build generic sg
1200 * @ioc: per adapter object
1201 * @psge: virtual address for SGE
1202 * @data_out_dma: physical address for WRITES
1203 * @data_out_sz: data xfer size for WRITES
1204 * @data_in_dma: physical address for READS
1205 * @data_in_sz: data xfer size for READS
1206 *
1207 * Return nothing.
1208 */
1209static void
1210_base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
1211 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1212 size_t data_in_sz)
1213{
1214 u32 sgl_flags;
1215
1216 if (!data_out_sz && !data_in_sz) {
1217 _base_build_zero_len_sge(ioc, psge);
1218 return;
1219 }
1220
1221 if (data_out_sz && data_in_sz) {
1222 /* WRITE sgel first */
1223 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1224 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
1225 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1226 ioc->base_add_sg_single(psge, sgl_flags |
1227 data_out_sz, data_out_dma);
1228
1229 /* incr sgel */
1230 psge += ioc->sge_size;
1231
1232 /* READ sgel last */
1233 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1234 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1235 MPI2_SGE_FLAGS_END_OF_LIST);
1236 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1237 ioc->base_add_sg_single(psge, sgl_flags |
1238 data_in_sz, data_in_dma);
1239 } else if (data_out_sz) /* WRITE */ {
1240 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1241 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1242 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
1243 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1244 ioc->base_add_sg_single(psge, sgl_flags |
1245 data_out_sz, data_out_dma);
1246 } else if (data_in_sz) /* READ */ {
1247 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1248 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1249 MPI2_SGE_FLAGS_END_OF_LIST);
1250 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1251 ioc->base_add_sg_single(psge, sgl_flags |
1252 data_in_sz, data_in_dma);
1253 }
1254}
1255
1256/* IEEE format sgls */
1257
1258/**
1259 * _base_add_sg_single_ieee - add sg element for IEEE format
1260 * @paddr: virtual address for SGE
1261 * @flags: SGE flags
1262 * @chain_offset: number of 128 byte elements from start of segment
1263 * @length: data transfer length
1264 * @dma_addr: Physical address
1265 *
1266 * Return nothing.
1267 */
1268static void
1269_base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
1270 dma_addr_t dma_addr)
1271{
1272 Mpi25IeeeSgeChain64_t *sgel = paddr;
1273
1274 sgel->Flags = flags;
1275 sgel->NextChainOffset = chain_offset;
1276 sgel->Length = cpu_to_le32(length);
1277 sgel->Address = cpu_to_le64(dma_addr);
1278}
1279
1280/**
1281 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
1282 * @ioc: per adapter object
1283 * @paddr: virtual address for SGE
1284 *
1285 * Create a zero length scatter gather entry to insure the IOCs hardware has
1286 * something to use if the target device goes brain dead and tries
1287 * to send data even when none is asked for.
1288 *
1289 * Return nothing.
1290 */
1291static void
1292_base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1293{
1294 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1295 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
1296 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
1297 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
1298}
1299
1300/**
1301 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
1302 * @ioc: per adapter object
1303 * @scmd: scsi command
1304 * @smid: system request message index
1305 * Context: none.
1306 *
1307 * The main routine that builds scatter gather table from a given
1308 * scsi request sent via the .queuecommand main handler.
1309 *
1310 * Returns 0 success, anything else error
1311 */
1312static int
1313_base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
1314 struct scsi_cmnd *scmd, u16 smid)
1315{
1316 Mpi2SCSIIORequest_t *mpi_request;
1317 dma_addr_t chain_dma;
1318 struct scatterlist *sg_scmd;
1319 void *sg_local, *chain;
1320 u32 chain_offset;
1321 u32 chain_length;
f92363d1
SR		 1322 int sges_left;
1323 u32 sges_in_segment;
1324 u8 simple_sgl_flags;
1325 u8 simple_sgl_flags_last;
1326 u8 chain_sgl_flags;
1327 struct chain_tracker *chain_req;
1328
1329 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1330
1331 /* init scatter gather flags */
1332 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1333 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1334 simple_sgl_flags_last = simple_sgl_flags |
1335 MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1336 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
1337 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1338
1339 sg_scmd = scsi_sglist(scmd);
1340 sges_left = scsi_dma_map(scmd);
1341 if (!sges_left) {
1342 sdev_printk(KERN_ERR, scmd->device,
1343 "pci_map_sg failed: request for %d bytes!\n",
1344 scsi_bufflen(scmd));
1345 return -ENOMEM;
1346 }
1347
1348 sg_local = &mpi_request->SGL;
1349 sges_in_segment = (ioc->request_sz -
1350 offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
1351 if (sges_left <= sges_in_segment)
1352 goto fill_in_last_segment;
1353
1354 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
1355 (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
1356
1357 /* fill in main message segment when there is a chain following */
1358 while (sges_in_segment > 1) {
1359 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1360 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1361 sg_scmd = sg_next(sg_scmd);
1362 sg_local += ioc->sge_size_ieee;
1363 sges_left--;
1364 sges_in_segment--;
1365 }
1366
25ef16d0 1367 /* initializing the pointers */
f92363d1
SR		 1368 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1369 if (!chain_req)
1370 return -1;
1371 chain = chain_req->chain_buffer;
1372 chain_dma = chain_req->chain_buffer_dma;
1373 do {
1374 sges_in_segment = (sges_left <=
1375 ioc->max_sges_in_chain_message) ? sges_left :
1376 ioc->max_sges_in_chain_message;
1377 chain_offset = (sges_left == sges_in_segment) ?
1378 0 : sges_in_segment;
1379 chain_length = sges_in_segment * ioc->sge_size_ieee;
1380 if (chain_offset)
1381 chain_length += ioc->sge_size_ieee;
1382 _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
1383 chain_offset, chain_length, chain_dma);
1384
1385 sg_local = chain;
1386 if (!chain_offset)
1387 goto fill_in_last_segment;
1388
1389 /* fill in chain segments */
1390 while (sges_in_segment) {
1391 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1392 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1393 sg_scmd = sg_next(sg_scmd);
1394 sg_local += ioc->sge_size_ieee;
1395 sges_left--;
1396 sges_in_segment--;
1397 }
1398
1399 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1400 if (!chain_req)
1401 return -1;
1402 chain = chain_req->chain_buffer;
1403 chain_dma = chain_req->chain_buffer_dma;
1404 } while (1);
1405
1406
1407 fill_in_last_segment:
1408
1409 /* fill the last segment */
1410 while (sges_left) {
1411 if (sges_left == 1)
1412 _base_add_sg_single_ieee(sg_local,
1413 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
1414 sg_dma_address(sg_scmd));
1415 else
1416 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1417 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1418 sg_scmd = sg_next(sg_scmd);
1419 sg_local += ioc->sge_size_ieee;
1420 sges_left--;
1421 }
1422
1423 return 0;
1424}
1425
1426/**
1427 * _base_build_sg_ieee - build generic sg for IEEE format
1428 * @ioc: per adapter object
1429 * @psge: virtual address for SGE
1430 * @data_out_dma: physical address for WRITES
1431 * @data_out_sz: data xfer size for WRITES
1432 * @data_in_dma: physical address for READS
1433 * @data_in_sz: data xfer size for READS
1434 *
1435 * Return nothing.
1436 */
1437static void
1438_base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
1439 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1440 size_t data_in_sz)
1441{
1442 u8 sgl_flags;
1443
1444 if (!data_out_sz && !data_in_sz) {
1445 _base_build_zero_len_sge_ieee(ioc, psge);
1446 return;
1447 }
1448
1449 if (data_out_sz && data_in_sz) {
1450 /* WRITE sgel first */
1451 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1452 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1453 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1454 data_out_dma);
1455
1456 /* incr sgel */
1457 psge += ioc->sge_size_ieee;
1458
1459 /* READ sgel last */
1460 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1461 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1462 data_in_dma);
1463 } else if (data_out_sz) /* WRITE */ {
1464 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1465 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1466 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1467 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1468 data_out_dma);
1469 } else if (data_in_sz) /* READ */ {
1470 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1471 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1472 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1473 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1474 data_in_dma);
1475 }
1476}
1477
1478#define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
1479
1480/**
1481 * _base_config_dma_addressing - set dma addressing
1482 * @ioc: per adapter object
1483 * @pdev: PCI device struct
1484 *
1485 * Returns 0 for success, non-zero for failure.
1486 */
1487static int
1488_base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
1489{
1490 struct sysinfo s;
9b05c91a
SR		 1491 u64 consistent_dma_mask;
1492
1493 if (ioc->dma_mask)
1494 consistent_dma_mask = DMA_BIT_MASK(64);
1495 else
1496 consistent_dma_mask = DMA_BIT_MASK(32);
f92363d1
SR		 1497
1498 if (sizeof(dma_addr_t) > 4) {
1499 const uint64_t required_mask =
1500 dma_get_required_mask(&pdev->dev);
1501 if ((required_mask > DMA_BIT_MASK(32)) &&
1502 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
9b05c91a 1503 !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
f92363d1
SR		 1504 ioc->base_add_sg_single = &_base_add_sg_single_64;
1505 ioc->sge_size = sizeof(Mpi2SGESimple64_t);
9b05c91a 1506 ioc->dma_mask = 64;
f92363d1
SR		 1507 goto out;
1508 }
1509 }
1510
1511 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1512 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1513 ioc->base_add_sg_single = &_base_add_sg_single_32;
1514 ioc->sge_size = sizeof(Mpi2SGESimple32_t);
9b05c91a 1515 ioc->dma_mask = 32;
f92363d1
SR		 1516 } else
1517 return -ENODEV;
1518
1519 out:
1520 si_meminfo(&s);
1521 pr_info(MPT3SAS_FMT
9b05c91a
SR		 1522 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
1523 ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
1524
1525 return 0;
1526}
f92363d1 1527
9b05c91a
SR		 1528static int
1529_base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
1530 struct pci_dev *pdev)
1531{
1532 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1533 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
1534 return -ENODEV;
1535 }
f92363d1
SR		 1536 return 0;
1537}
1538
1539/**
1540 * _base_check_enable_msix - checks MSIX capabable.
1541 * @ioc: per adapter object
1542 *
1543 * Check to see if card is capable of MSIX, and set number
1544 * of available msix vectors
1545 */
1546static int
1547_base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1548{
1549 int base;
1550 u16 message_control;
1551
1552 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
1553 if (!base) {
1554 dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
1555 ioc->name));
1556 return -EINVAL;
1557 }
1558
1559 /* get msix vector count */
1560
1561 pci_read_config_word(ioc->pdev, base + 2, &message_control);
1562 ioc->msix_vector_count = (message_control & 0x3FF) + 1;
1563 if (ioc->msix_vector_count > 8)
1564 ioc->msix_vector_count = 8;
1565 dinitprintk(ioc, pr_info(MPT3SAS_FMT
1566 "msix is supported, vector_count(%d)\n",
1567 ioc->name, ioc->msix_vector_count));
1568 return 0;
1569}
1570
1571/**
1572 * _base_free_irq - free irq
1573 * @ioc: per adapter object
1574 *
1575 * Freeing respective reply_queue from the list.
1576 */
1577static void
1578_base_free_irq(struct MPT3SAS_ADAPTER *ioc)
1579{
1580 struct adapter_reply_queue *reply_q, *next;
1581
1582 if (list_empty(&ioc->reply_queue_list))
1583 return;
1584
1585 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1586 list_del(&reply_q->list);
14b3114d
SR		 1587 irq_set_affinity_hint(reply_q->vector, NULL);
1588 free_cpumask_var(reply_q->affinity_hint);
f92363d1
SR		 1589 synchronize_irq(reply_q->vector);
1590 free_irq(reply_q->vector, reply_q);
1591 kfree(reply_q);
1592 }
1593}
1594
1595/**
1596 * _base_request_irq - request irq
1597 * @ioc: per adapter object
1598 * @index: msix index into vector table
1599 * @vector: irq vector
1600 *
1601 * Inserting respective reply_queue into the list.
1602 */
1603static int
1604_base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index, u32 vector)
1605{
1606 struct adapter_reply_queue *reply_q;
1607 int r;
1608
1609 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
1610 if (!reply_q) {
1611 pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
1612 ioc->name, (int)sizeof(struct adapter_reply_queue));
1613 return -ENOMEM;
1614 }
1615 reply_q->ioc = ioc;
1616 reply_q->msix_index = index;
1617 reply_q->vector = vector;
14b3114d
SR		 1618
1619 if (!alloc_cpumask_var(&reply_q->affinity_hint, GFP_KERNEL))
1620 return -ENOMEM;
1621 cpumask_clear(reply_q->affinity_hint);
1622
f92363d1
SR		 1623 atomic_set(&reply_q->busy, 0);
1624 if (ioc->msix_enable)
1625 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
1626 MPT3SAS_DRIVER_NAME, ioc->id, index);
1627 else
1628 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
1629 MPT3SAS_DRIVER_NAME, ioc->id);
1630 r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name,
1631 reply_q);
1632 if (r) {
1633 pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
1634 reply_q->name, vector);
1635 kfree(reply_q);
1636 return -EBUSY;
1637 }
1638
1639 INIT_LIST_HEAD(&reply_q->list);
1640 list_add_tail(&reply_q->list, &ioc->reply_queue_list);
1641 return 0;
1642}
1643
1644/**
1645 * _base_assign_reply_queues - assigning msix index for each cpu
1646 * @ioc: per adapter object
1647 *
1648 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
1649 *
1650 * It would nice if we could call irq_set_affinity, however it is not
1651 * an exported symbol
1652 */
1653static void
1654_base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1655{
91b265bf 1656 unsigned int cpu, nr_cpus, nr_msix, index = 0;
14b3114d 1657 struct adapter_reply_queue *reply_q;
f92363d1
SR		 1658
1659 if (!_base_is_controller_msix_enabled(ioc))
1660 return;
1661
1662 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
1663
91b265bf
MP		 1664 nr_cpus = num_online_cpus();
1665 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
1666 ioc->facts.MaxMSIxVectors);
1667 if (!nr_msix)
1668 return;
f92363d1 1669
91b265bf
MP		 1670 cpu = cpumask_first(cpu_online_mask);
1671
14b3114d
SR		 1672 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1673
91b265bf
MP		 1674 unsigned int i, group = nr_cpus / nr_msix;
1675
14b3114d
SR		 1676 if (cpu >= nr_cpus)
1677 break;
1678
91b265bf
MP		 1679 if (index < nr_cpus % nr_msix)
1680 group++;
1681
1682 for (i = 0 ; i < group ; i++) {
1683 ioc->cpu_msix_table[cpu] = index;
14b3114d
SR		 1684 cpumask_or(reply_q->affinity_hint,
1685 reply_q->affinity_hint, get_cpu_mask(cpu));
91b265bf 1686 cpu = cpumask_next(cpu, cpu_online_mask);
f92363d1 1687 }
91b265bf 1688
14b3114d
SR		 1689 if (irq_set_affinity_hint(reply_q->vector,
1690 reply_q->affinity_hint))
1691 dinitprintk(ioc, pr_info(MPT3SAS_FMT
1692 "error setting affinity hint for irq vector %d\n",
1693 ioc->name, reply_q->vector));
91b265bf 1694 index++;
14b3114d 1695 }
f92363d1
SR		 1696}
1697
1698/**
1699 * _base_disable_msix - disables msix
1700 * @ioc: per adapter object
1701 *
1702 */
1703static void
1704_base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
1705{
1706 if (!ioc->msix_enable)
1707 return;
1708 pci_disable_msix(ioc->pdev);
1709 ioc->msix_enable = 0;
1710}
1711
1712/**
1713 * _base_enable_msix - enables msix, failback to io_apic
1714 * @ioc: per adapter object
1715 *
1716 */
1717static int
1718_base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1719{
1720 struct msix_entry *entries, *a;
1721 int r;
1722 int i;
1723 u8 try_msix = 0;
1724
f92363d1
SR		 1725 if (msix_disable == -1 || msix_disable == 0)
1726 try_msix = 1;
1727
1728 if (!try_msix)
1729 goto try_ioapic;
1730
1731 if (_base_check_enable_msix(ioc) != 0)
1732 goto try_ioapic;
1733
1734 ioc->reply_queue_count = min_t(int, ioc->cpu_count,
1735 ioc->msix_vector_count);
1736
9c500060
SR		 1737 printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
1738 ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
1739 ioc->cpu_count, max_msix_vectors);
1740
9b05c91a
SR		 1741 if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
1742 max_msix_vectors = 8;
1743
9c500060
SR		 1744 if (max_msix_vectors > 0) {
1745 ioc->reply_queue_count = min_t(int, max_msix_vectors,
1746 ioc->reply_queue_count);
1747 ioc->msix_vector_count = ioc->reply_queue_count;
9b05c91a
SR		 1748 } else if (max_msix_vectors == 0)
1749 goto try_ioapic;
9c500060 1750
f92363d1
SR		 1751 entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry),
1752 GFP_KERNEL);
1753 if (!entries) {
1754 dfailprintk(ioc, pr_info(MPT3SAS_FMT
1755 "kcalloc failed @ at %s:%d/%s() !!!\n",
1756 ioc->name, __FILE__, __LINE__, __func__));
1757 goto try_ioapic;
1758 }
1759
1760 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++)
1761 a->entry = i;
1762
6bfa6907 1763 r = pci_enable_msix_exact(ioc->pdev, entries, ioc->reply_queue_count);
f92363d1
SR		 1764 if (r) {
1765 dfailprintk(ioc, pr_info(MPT3SAS_FMT
6bfa6907 1766 "pci_enable_msix_exact failed (r=%d) !!!\n",
f92363d1
SR		 1767 ioc->name, r));
1768 kfree(entries);
1769 goto try_ioapic;
1770 }
1771
1772 ioc->msix_enable = 1;
1773 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) {
1774 r = _base_request_irq(ioc, i, a->vector);
1775 if (r) {
1776 _base_free_irq(ioc);
1777 _base_disable_msix(ioc);
1778 kfree(entries);
1779 goto try_ioapic;
1780 }
1781 }
1782
1783 kfree(entries);
1784 return 0;
1785
1786/* failback to io_apic interrupt routing */
1787 try_ioapic:
1788
9b05c91a 1789 ioc->reply_queue_count = 1;
f92363d1
SR		 1790 r = _base_request_irq(ioc, 0, ioc->pdev->irq);
1791
1792 return r;
1793}
1794
1795/**
1796 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
1797 * @ioc: per adapter object
1798 *
1799 * Returns 0 for success, non-zero for failure.
1800 */
1801int
1802mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
1803{
1804 struct pci_dev *pdev = ioc->pdev;
1805 u32 memap_sz;
1806 u32 pio_sz;
1807 int i, r = 0;
1808 u64 pio_chip = 0;
1809 u64 chip_phys = 0;
1810 struct adapter_reply_queue *reply_q;
1811
1812 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
1813 ioc->name, __func__));
1814
1815 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
1816 if (pci_enable_device_mem(pdev)) {
1817 pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
1818 ioc->name);
cf9bd21a 1819 ioc->bars = 0;
f92363d1
SR		 1820 return -ENODEV;
1821 }
1822
1823
1824 if (pci_request_selected_regions(pdev, ioc->bars,
1825 MPT3SAS_DRIVER_NAME)) {
1826 pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
1827 ioc->name);
cf9bd21a 1828 ioc->bars = 0;
f92363d1
SR		 1829 r = -ENODEV;
1830 goto out_fail;
1831 }
1832
1833/* AER (Advanced Error Reporting) hooks */
1834 pci_enable_pcie_error_reporting(pdev);
1835
1836 pci_set_master(pdev);
1837
1838
1839 if (_base_config_dma_addressing(ioc, pdev) != 0) {
1840 pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
1841 ioc->name, pci_name(pdev));
1842 r = -ENODEV;
1843 goto out_fail;
1844 }
1845
5aeeb78a
SR		 1846 for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
1847 (!memap_sz || !pio_sz); i++) {
f92363d1
SR		 1848 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1849 if (pio_sz)
1850 continue;
1851 pio_chip = (u64)pci_resource_start(pdev, i);
1852 pio_sz = pci_resource_len(pdev, i);
1853 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
1854 if (memap_sz)
1855 continue;
1856 ioc->chip_phys = pci_resource_start(pdev, i);
1857 chip_phys = (u64)ioc->chip_phys;
1858 memap_sz = pci_resource_len(pdev, i);
1859 ioc->chip = ioremap(ioc->chip_phys, memap_sz);
f92363d1
SR		 1860 }
1861 }
1862
5aeeb78a
SR		 1863 if (ioc->chip == NULL) {
1864 pr_err(MPT3SAS_FMT "unable to map adapter memory! "
1865 " or resource not found\n", ioc->name);
1866 r = -EINVAL;
1867 goto out_fail;
1868 }
1869
f92363d1 1870 _base_mask_interrupts(ioc);
9b05c91a
SR		 1871
1872 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
1873 if (r)
1874 goto out_fail;
1875
1876 if (!ioc->rdpq_array_enable_assigned) {
1877 ioc->rdpq_array_enable = ioc->rdpq_array_capable;
1878 ioc->rdpq_array_enable_assigned = 1;
1879 }
1880
f92363d1
SR		 1881 r = _base_enable_msix(ioc);
1882 if (r)
1883 goto out_fail;
1884
1885 list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
1886 pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
1887 reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
1888 "IO-APIC enabled"), reply_q->vector);
1889
1890 pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
1891 ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
1892 pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
1893 ioc->name, (unsigned long long)pio_chip, pio_sz);
1894
1895 /* Save PCI configuration state for recovery from PCI AER/EEH errors */
1896 pci_save_state(pdev);
1897 return 0;
1898
1899 out_fail:
1900 if (ioc->chip_phys)
1901 iounmap(ioc->chip);
1902 ioc->chip_phys = 0;
1903 pci_release_selected_regions(ioc->pdev, ioc->bars);
1904 pci_disable_pcie_error_reporting(pdev);
1905 pci_disable_device(pdev);
1906 return r;
1907}
1908
1909/**
1910 * mpt3sas_base_get_msg_frame - obtain request mf pointer
1911 * @ioc: per adapter object
1912 * @smid: system request message index(smid zero is invalid)
1913 *
1914 * Returns virt pointer to message frame.
1915 */
1916void *
1917mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1918{
1919 return (void *)(ioc->request + (smid * ioc->request_sz));
1920}
1921
1922/**
1923 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
1924 * @ioc: per adapter object
1925 * @smid: system request message index
1926 *
1927 * Returns virt pointer to sense buffer.
1928 */
1929void *
1930mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1931{
1932 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
1933}
1934
1935/**
1936 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
1937 * @ioc: per adapter object
1938 * @smid: system request message index
1939 *
1940 * Returns phys pointer to the low 32bit address of the sense buffer.
1941 */
1942__le32
1943mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1944{
1945 return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
1946 SCSI_SENSE_BUFFERSIZE));
1947}
1948
1949/**
1950 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
1951 * @ioc: per adapter object
1952 * @phys_addr: lower 32 physical addr of the reply
1953 *
1954 * Converts 32bit lower physical addr into a virt address.
1955 */
1956void *
1957mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
1958{
1959 if (!phys_addr)
1960 return NULL;
1961 return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
1962}
1963
1964/**
1965 * mpt3sas_base_get_smid - obtain a free smid from internal queue
1966 * @ioc: per adapter object
1967 * @cb_idx: callback index
1968 *
1969 * Returns smid (zero is invalid)
1970 */
1971u16
1972mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
1973{
1974 unsigned long flags;
1975 struct request_tracker *request;
1976 u16 smid;
1977
1978 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1979 if (list_empty(&ioc->internal_free_list)) {
1980 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1981 pr_err(MPT3SAS_FMT "%s: smid not available\n",
1982 ioc->name, __func__);
1983 return 0;
1984 }
1985
1986 request = list_entry(ioc->internal_free_list.next,
1987 struct request_tracker, tracker_list);
1988 request->cb_idx = cb_idx;
1989 smid = request->smid;
1990 list_del(&request->tracker_list);
1991 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1992 return smid;
1993}
1994
1995/**
1996 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
1997 * @ioc: per adapter object
1998 * @cb_idx: callback index
1999 * @scmd: pointer to scsi command object
2000 *
2001 * Returns smid (zero is invalid)
2002 */
2003u16
2004mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
2005 struct scsi_cmnd *scmd)
2006{
2007 unsigned long flags;
2008 struct scsiio_tracker *request;
2009 u16 smid;
2010
2011 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2012 if (list_empty(&ioc->free_list)) {
2013 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2014 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2015 ioc->name, __func__);
2016 return 0;
2017 }
2018
2019 request = list_entry(ioc->free_list.next,
2020 struct scsiio_tracker, tracker_list);
2021 request->scmd = scmd;
2022 request->cb_idx = cb_idx;
2023 smid = request->smid;
2024 list_del(&request->tracker_list);
2025 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2026 return smid;
2027}
2028
2029/**
2030 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
2031 * @ioc: per adapter object
2032 * @cb_idx: callback index
2033 *
2034 * Returns smid (zero is invalid)
2035 */
2036u16
2037mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2038{
2039 unsigned long flags;
2040 struct request_tracker *request;
2041 u16 smid;
2042
2043 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2044 if (list_empty(&ioc->hpr_free_list)) {
2045 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2046 return 0;
2047 }
2048
2049 request = list_entry(ioc->hpr_free_list.next,
2050 struct request_tracker, tracker_list);
2051 request->cb_idx = cb_idx;
2052 smid = request->smid;
2053 list_del(&request->tracker_list);
2054 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2055 return smid;
2056}
2057
2058/**
2059 * mpt3sas_base_free_smid - put smid back on free_list
2060 * @ioc: per adapter object
2061 * @smid: system request message index
2062 *
2063 * Return nothing.
2064 */
2065void
2066mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2067{
2068 unsigned long flags;
2069 int i;
2070 struct chain_tracker *chain_req, *next;
2071
2072 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2073 if (smid < ioc->hi_priority_smid) {
2074 /* scsiio queue */
2075 i = smid - 1;
2076 if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
2077 list_for_each_entry_safe(chain_req, next,
2078 &ioc->scsi_lookup[i].chain_list, tracker_list) {
2079 list_del_init(&chain_req->tracker_list);
2080 list_add(&chain_req->tracker_list,
2081 &ioc->free_chain_list);
2082 }
2083 }
2084 ioc->scsi_lookup[i].cb_idx = 0xFF;
2085 ioc->scsi_lookup[i].scmd = NULL;
2086 list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list);
2087 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2088
2089 /*
2090 * See _wait_for_commands_to_complete() call with regards
2091 * to this code.
2092 */
2093 if (ioc->shost_recovery && ioc->pending_io_count) {
2094 if (ioc->pending_io_count == 1)
2095 wake_up(&ioc->reset_wq);
2096 ioc->pending_io_count--;
2097 }
2098 return;
2099 } else if (smid < ioc->internal_smid) {
2100 /* hi-priority */
2101 i = smid - ioc->hi_priority_smid;
2102 ioc->hpr_lookup[i].cb_idx = 0xFF;
2103 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
2104 } else if (smid <= ioc->hba_queue_depth) {
2105 /* internal queue */
2106 i = smid - ioc->internal_smid;
2107 ioc->internal_lookup[i].cb_idx = 0xFF;
2108 list_add(&ioc->internal_lookup[i].tracker_list,
2109 &ioc->internal_free_list);
2110 }
2111 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2112}
2113
2114/**
2115 * _base_writeq - 64 bit write to MMIO
2116 * @ioc: per adapter object
2117 * @b: data payload
2118 * @addr: address in MMIO space
2119 * @writeq_lock: spin lock
2120 *
2121 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
2122 * care of 32 bit environment where its not quarenteed to send the entire word
2123 * in one transfer.
2124 */
2125#if defined(writeq) && defined(CONFIG_64BIT)
2126static inline void
2127_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2128{
2129 writeq(cpu_to_le64(b), addr);
2130}
2131#else
2132static inline void
2133_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2134{
2135 unsigned long flags;
2136 __u64 data_out = cpu_to_le64(b);
2137
2138 spin_lock_irqsave(writeq_lock, flags);
2139 writel((u32)(data_out), addr);
2140 writel((u32)(data_out >> 32), (addr + 4));
2141 spin_unlock_irqrestore(writeq_lock, flags);
2142}
2143#endif
2144
2145static inline u8
2146_base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
2147{
2148 return ioc->cpu_msix_table[raw_smp_processor_id()];
2149}
2150
2151/**
2152 * mpt3sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
2153 * @ioc: per adapter object
2154 * @smid: system request message index
2155 * @handle: device handle
2156 *
2157 * Return nothing.
2158 */
2159void
2160mpt3sas_base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
2161{
2162 Mpi2RequestDescriptorUnion_t descriptor;
2163 u64 *request = (u64 *)&descriptor;
2164
2165
2166 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
2167 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2168 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2169 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2170 descriptor.SCSIIO.LMID = 0;
2171 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2172 &ioc->scsi_lookup_lock);
2173}
2174
2175/**
2176 * mpt3sas_base_put_smid_fast_path - send fast path request to firmware
2177 * @ioc: per adapter object
2178 * @smid: system request message index
2179 * @handle: device handle
2180 *
2181 * Return nothing.
2182 */
2183void
2184mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2185 u16 handle)
2186{
2187 Mpi2RequestDescriptorUnion_t descriptor;
2188 u64 *request = (u64 *)&descriptor;
2189
2190 descriptor.SCSIIO.RequestFlags =
2191 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
2192 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2193 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2194 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2195 descriptor.SCSIIO.LMID = 0;
2196 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2197 &ioc->scsi_lookup_lock);
2198}
2199
2200/**
2201 * mpt3sas_base_put_smid_hi_priority - send Task Managment request to firmware
2202 * @ioc: per adapter object
2203 * @smid: system request message index
2204 *
2205 * Return nothing.
2206 */
2207void
2208mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2209{
2210 Mpi2RequestDescriptorUnion_t descriptor;
2211 u64 *request = (u64 *)&descriptor;
2212
2213 descriptor.HighPriority.RequestFlags =
2214 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
2215 descriptor.HighPriority.MSIxIndex = 0;
2216 descriptor.HighPriority.SMID = cpu_to_le16(smid);
2217 descriptor.HighPriority.LMID = 0;
2218 descriptor.HighPriority.Reserved1 = 0;
2219 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2220 &ioc->scsi_lookup_lock);
2221}
2222
2223/**
2224 * mpt3sas_base_put_smid_default - Default, primarily used for config pages
2225 * @ioc: per adapter object
2226 * @smid: system request message index
2227 *
2228 * Return nothing.
2229 */
2230void
2231mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2232{
2233 Mpi2RequestDescriptorUnion_t descriptor;
2234 u64 *request = (u64 *)&descriptor;
2235
2236 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2237 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
2238 descriptor.Default.SMID = cpu_to_le16(smid);
2239 descriptor.Default.LMID = 0;
2240 descriptor.Default.DescriptorTypeDependent = 0;
2241 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2242 &ioc->scsi_lookup_lock);
2243}
2244
1117b31a
SR		 2245/**
2246 * _base_display_intel_branding - Display branding string
2247 * @ioc: per adapter object
2248 *
2249 * Return nothing.
2250 */
2251static void
2252_base_display_intel_branding(struct MPT3SAS_ADAPTER *ioc)
2253{
2254 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
2255 return;
2256
2257 switch (ioc->pdev->device) {
2258 case MPI25_MFGPAGE_DEVID_SAS3008:
2259 switch (ioc->pdev->subsystem_device) {
2260 case MPT3SAS_INTEL_RMS3JC080_SSDID:
2261 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2262 MPT3SAS_INTEL_RMS3JC080_BRANDING);
2263 break;
2264
2265 case MPT3SAS_INTEL_RS3GC008_SSDID:
2266 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2267 MPT3SAS_INTEL_RS3GC008_BRANDING);
2268 break;
2269 case MPT3SAS_INTEL_RS3FC044_SSDID:
2270 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2271 MPT3SAS_INTEL_RS3FC044_BRANDING);
2272 break;
2273 case MPT3SAS_INTEL_RS3UC080_SSDID:
2274 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2275 MPT3SAS_INTEL_RS3UC080_BRANDING);
2276 break;
2277 default:
2278 pr_info(MPT3SAS_FMT
2279 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2280 ioc->name, ioc->pdev->subsystem_device);
2281 break;
2282 }
2283 break;
2284 default:
2285 pr_info(MPT3SAS_FMT
2286 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2287 ioc->name, ioc->pdev->subsystem_device);
2288 break;
2289 }
2290}
2291
f92363d1
SR		 2292
2293
2294/**
2295 * _base_display_ioc_capabilities - Disply IOC's capabilities.
2296 * @ioc: per adapter object
2297 *
2298 * Return nothing.
2299 */
2300static void
2301_base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
2302{
2303 int i = 0;
2304 char desc[16];
2305 u32 iounit_pg1_flags;
2306 u32 bios_version;
2307
2308 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
2309 strncpy(desc, ioc->manu_pg0.ChipName, 16);
2310 pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
2311 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
2312 ioc->name, desc,
2313 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
2314 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
2315 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
2316 ioc->facts.FWVersion.Word & 0x000000FF,
2317 ioc->pdev->revision,
2318 (bios_version & 0xFF000000) >> 24,
2319 (bios_version & 0x00FF0000) >> 16,
2320 (bios_version & 0x0000FF00) >> 8,
2321 bios_version & 0x000000FF);
2322
1117b31a
SR		 2323 _base_display_intel_branding(ioc);
2324
f92363d1
SR		 2325 pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
2326
2327 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
2328 pr_info("Initiator");
2329 i++;
2330 }
2331
2332 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
2333 pr_info("%sTarget", i ? "," : "");
2334 i++;
2335 }
2336
2337 i = 0;
2338 pr_info("), ");
2339 pr_info("Capabilities=(");
2340
2341 if (ioc->facts.IOCCapabilities &
2342 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
2343 pr_info("Raid");
2344 i++;
2345 }
2346
2347 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
2348 pr_info("%sTLR", i ? "," : "");
2349 i++;
2350 }
2351
2352 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
2353 pr_info("%sMulticast", i ? "," : "");
2354 i++;
2355 }
2356
2357 if (ioc->facts.IOCCapabilities &
2358 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
2359 pr_info("%sBIDI Target", i ? "," : "");
2360 i++;
2361 }
2362
2363 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
2364 pr_info("%sEEDP", i ? "," : "");
2365 i++;
2366 }
2367
2368 if (ioc->facts.IOCCapabilities &
2369 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
2370 pr_info("%sSnapshot Buffer", i ? "," : "");
2371 i++;
2372 }
2373
2374 if (ioc->facts.IOCCapabilities &
2375 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
2376 pr_info("%sDiag Trace Buffer", i ? "," : "");
2377 i++;
2378 }
2379
2380 if (ioc->facts.IOCCapabilities &
2381 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
2382 pr_info("%sDiag Extended Buffer", i ? "," : "");
2383 i++;
2384 }
2385
2386 if (ioc->facts.IOCCapabilities &
2387 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
2388 pr_info("%sTask Set Full", i ? "," : "");
2389 i++;
2390 }
2391
2392 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2393 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
2394 pr_info("%sNCQ", i ? "," : "");
2395 i++;
2396 }
2397
2398 pr_info(")\n");
2399}
2400
2401/**
2402 * mpt3sas_base_update_missing_delay - change the missing delay timers
2403 * @ioc: per adapter object
2404 * @device_missing_delay: amount of time till device is reported missing
2405 * @io_missing_delay: interval IO is returned when there is a missing device
2406 *
2407 * Return nothing.
2408 *
2409 * Passed on the command line, this function will modify the device missing
2410 * delay, as well as the io missing delay. This should be called at driver
2411 * load time.
2412 */
2413void
2414mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
2415 u16 device_missing_delay, u8 io_missing_delay)
2416{
2417 u16 dmd, dmd_new, dmd_orignal;
2418 u8 io_missing_delay_original;
2419 u16 sz;
2420 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
2421 Mpi2ConfigReply_t mpi_reply;
2422 u8 num_phys = 0;
2423 u16 ioc_status;
2424
2425 mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
2426 if (!num_phys)
2427 return;
2428
2429 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
2430 sizeof(Mpi2SasIOUnit1PhyData_t));
2431 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
2432 if (!sas_iounit_pg1) {
2433 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2434 ioc->name, __FILE__, __LINE__, __func__);
2435 goto out;
2436 }
2437 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
2438 sas_iounit_pg1, sz))) {
2439 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2440 ioc->name, __FILE__, __LINE__, __func__);
2441 goto out;
2442 }
2443 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
2444 MPI2_IOCSTATUS_MASK;
2445 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
2446 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2447 ioc->name, __FILE__, __LINE__, __func__);
2448 goto out;
2449 }
2450
2451 /* device missing delay */
2452 dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
2453 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2454 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2455 else
2456 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2457 dmd_orignal = dmd;
2458 if (device_missing_delay > 0x7F) {
2459 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
2460 device_missing_delay;
2461 dmd = dmd / 16;
2462 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
2463 } else
2464 dmd = device_missing_delay;
2465 sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
2466
2467 /* io missing delay */
2468 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
2469 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
2470
2471 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
2472 sz)) {
2473 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2474 dmd_new = (dmd &
2475 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2476 else
2477 dmd_new =
2478 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2479 pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
2480 ioc->name, dmd_orignal, dmd_new);
2481 pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
2482 ioc->name, io_missing_delay_original,
2483 io_missing_delay);
2484 ioc->device_missing_delay = dmd_new;
2485 ioc->io_missing_delay = io_missing_delay;
2486 }
2487
2488out:
2489 kfree(sas_iounit_pg1);
2490}
2491/**
2492 * _base_static_config_pages - static start of day config pages
2493 * @ioc: per adapter object
2494 *
2495 * Return nothing.
2496 */
2497static void
2498_base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
2499{
2500 Mpi2ConfigReply_t mpi_reply;
2501 u32 iounit_pg1_flags;
2502
2503 mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
2504 if (ioc->ir_firmware)
2505 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
2506 &ioc->manu_pg10);
2507
2508 /*
2509 * Ensure correct T10 PI operation if vendor left EEDPTagMode
2510 * flag unset in NVDATA.
2511 */
2512 mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
2513 if (ioc->manu_pg11.EEDPTagMode == 0) {
2514 pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
2515 ioc->name);
2516 ioc->manu_pg11.EEDPTagMode &= ~0x3;
2517 ioc->manu_pg11.EEDPTagMode |= 0x1;
2518 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
2519 &ioc->manu_pg11);
2520 }
2521
2522 mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
2523 mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
2524 mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
2525 mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
2526 mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2d8ce8c9 2527 mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
f92363d1
SR		 2528 _base_display_ioc_capabilities(ioc);
2529
2530 /*
2531 * Enable task_set_full handling in iounit_pg1 when the
2532 * facts capabilities indicate that its supported.
2533 */
2534 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2535 if ((ioc->facts.IOCCapabilities &
2536 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
2537 iounit_pg1_flags &=
2538 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
2539 else
2540 iounit_pg1_flags |=
2541 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
2542 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
2543 mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2d8ce8c9
SR		 2544
2545 if (ioc->iounit_pg8.NumSensors)
2546 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
f92363d1
SR		 2547}
2548
2549/**
2550 * _base_release_memory_pools - release memory
2551 * @ioc: per adapter object
2552 *
2553 * Free memory allocated from _base_allocate_memory_pools.
2554 *
2555 * Return nothing.
2556 */
2557static void
2558_base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
2559{
9b05c91a
SR		 2560 int i = 0;
2561 struct reply_post_struct *rps;
f92363d1
SR		 2562
2563 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2564 __func__));
2565
2566 if (ioc->request) {
2567 pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
2568 ioc->request, ioc->request_dma);
2569 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2570 "request_pool(0x%p): free\n",
2571 ioc->name, ioc->request));
2572 ioc->request = NULL;
2573 }
2574
2575 if (ioc->sense) {
2576 pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
2577 if (ioc->sense_dma_pool)
2578 pci_pool_destroy(ioc->sense_dma_pool);
2579 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2580 "sense_pool(0x%p): free\n",
2581 ioc->name, ioc->sense));
2582 ioc->sense = NULL;
2583 }
2584
2585 if (ioc->reply) {
2586 pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
2587 if (ioc->reply_dma_pool)
2588 pci_pool_destroy(ioc->reply_dma_pool);
2589 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2590 "reply_pool(0x%p): free\n",
2591 ioc->name, ioc->reply));
2592 ioc->reply = NULL;
2593 }
2594
2595 if (ioc->reply_free) {
2596 pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
2597 ioc->reply_free_dma);
2598 if (ioc->reply_free_dma_pool)
2599 pci_pool_destroy(ioc->reply_free_dma_pool);
2600 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2601 "reply_free_pool(0x%p): free\n",
2602 ioc->name, ioc->reply_free));
2603 ioc->reply_free = NULL;
2604 }
2605
9b05c91a
SR		 2606 if (ioc->reply_post) {
2607 do {
2608 rps = &ioc->reply_post[i];
2609 if (rps->reply_post_free) {
2610 pci_pool_free(
2611 ioc->reply_post_free_dma_pool,
2612 rps->reply_post_free,
2613 rps->reply_post_free_dma);
2614 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2615 "reply_post_free_pool(0x%p): free\n",
2616 ioc->name, rps->reply_post_free));
2617 rps->reply_post_free = NULL;
2618 }
2619 } while (ioc->rdpq_array_enable &&
2620 (++i < ioc->reply_queue_count));
2621
f92363d1
SR		 2622 if (ioc->reply_post_free_dma_pool)
2623 pci_pool_destroy(ioc->reply_post_free_dma_pool);
9b05c91a 2624 kfree(ioc->reply_post);
f92363d1
SR		 2625 }
2626
2627 if (ioc->config_page) {
2628 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2629 "config_page(0x%p): free\n", ioc->name,
2630 ioc->config_page));
2631 pci_free_consistent(ioc->pdev, ioc->config_page_sz,
2632 ioc->config_page, ioc->config_page_dma);
2633 }
2634
2635 if (ioc->scsi_lookup) {
2636 free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
2637 ioc->scsi_lookup = NULL;
2638 }
2639 kfree(ioc->hpr_lookup);
2640 kfree(ioc->internal_lookup);
2641 if (ioc->chain_lookup) {
2642 for (i = 0; i < ioc->chain_depth; i++) {
2643 if (ioc->chain_lookup[i].chain_buffer)
2644 pci_pool_free(ioc->chain_dma_pool,
2645 ioc->chain_lookup[i].chain_buffer,
2646 ioc->chain_lookup[i].chain_buffer_dma);
2647 }
2648 if (ioc->chain_dma_pool)
2649 pci_pool_destroy(ioc->chain_dma_pool);
2650 free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
2651 ioc->chain_lookup = NULL;
2652 }
2653}
2654
2655/**
2656 * _base_allocate_memory_pools - allocate start of day memory pools
2657 * @ioc: per adapter object
2658 * @sleep_flag: CAN_SLEEP or NO_SLEEP
2659 *
2660 * Returns 0 success, anything else error
2661 */
2662static int
2663_base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
2664{
2665 struct mpt3sas_facts *facts;
2666 u16 max_sge_elements;
2667 u16 chains_needed_per_io;
2668 u32 sz, total_sz, reply_post_free_sz;
2669 u32 retry_sz;
2670 u16 max_request_credit;
2671 unsigned short sg_tablesize;
2672 u16 sge_size;
2673 int i;
2674
2675 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2676 __func__));
2677
2678
2679 retry_sz = 0;
2680 facts = &ioc->facts;
2681
2682 /* command line tunables for max sgl entries */
2683 if (max_sgl_entries != -1)
2684 sg_tablesize = max_sgl_entries;
2685 else
2686 sg_tablesize = MPT3SAS_SG_DEPTH;
2687
2688 if (sg_tablesize < MPT3SAS_MIN_PHYS_SEGMENTS)
2689 sg_tablesize = MPT3SAS_MIN_PHYS_SEGMENTS;
ad666a0f
SR		 2690 else if (sg_tablesize > MPT3SAS_MAX_PHYS_SEGMENTS) {
2691 sg_tablesize = min_t(unsigned short, sg_tablesize,
2692 SCSI_MAX_SG_CHAIN_SEGMENTS);
2693 pr_warn(MPT3SAS_FMT
2694 "sg_tablesize(%u) is bigger than kernel"
2695 " defined SCSI_MAX_SG_SEGMENTS(%u)\n", ioc->name,
2696 sg_tablesize, MPT3SAS_MAX_PHYS_SEGMENTS);
2697 }
f92363d1
SR		 2698 ioc->shost->sg_tablesize = sg_tablesize;
2699
2700 ioc->hi_priority_depth = facts->HighPriorityCredit;
2701 ioc->internal_depth = ioc->hi_priority_depth + (5);
2702 /* command line tunables for max controller queue depth */
2703 if (max_queue_depth != -1 && max_queue_depth != 0) {
2704 max_request_credit = min_t(u16, max_queue_depth +
2705 ioc->hi_priority_depth + ioc->internal_depth,
2706 facts->RequestCredit);
2707 if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
2708 max_request_credit = MAX_HBA_QUEUE_DEPTH;
2709 } else
2710 max_request_credit = min_t(u16, facts->RequestCredit,
2711 MAX_HBA_QUEUE_DEPTH);
2712
2713 ioc->hba_queue_depth = max_request_credit;
2714
2715 /* request frame size */
2716 ioc->request_sz = facts->IOCRequestFrameSize * 4;
2717
2718 /* reply frame size */
2719 ioc->reply_sz = facts->ReplyFrameSize * 4;
2720
2721 /* calculate the max scatter element size */
2722 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
2723
2724 retry_allocation:
2725 total_sz = 0;
2726 /* calculate number of sg elements left over in the 1st frame */
2727 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
2728 sizeof(Mpi2SGEIOUnion_t)) + sge_size);
2729 ioc->max_sges_in_main_message = max_sge_elements/sge_size;
2730
2731 /* now do the same for a chain buffer */
2732 max_sge_elements = ioc->request_sz - sge_size;
2733 ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
2734
2735 /*
2736 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
2737 */
2738 chains_needed_per_io = ((ioc->shost->sg_tablesize -
2739 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
2740 + 1;
2741 if (chains_needed_per_io > facts->MaxChainDepth) {
2742 chains_needed_per_io = facts->MaxChainDepth;
2743 ioc->shost->sg_tablesize = min_t(u16,
2744 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
2745 * chains_needed_per_io), ioc->shost->sg_tablesize);
2746 }
2747 ioc->chains_needed_per_io = chains_needed_per_io;
2748
2749 /* reply free queue sizing - taking into account for 64 FW events */
2750 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
2751
2752 /* calculate reply descriptor post queue depth */
2753 ioc->reply_post_queue_depth = ioc->hba_queue_depth +
2754 ioc->reply_free_queue_depth + 1 ;
2755 /* align the reply post queue on the next 16 count boundary */
2756 if (ioc->reply_post_queue_depth % 16)
2757 ioc->reply_post_queue_depth += 16 -
2758 (ioc->reply_post_queue_depth % 16);
2759
2760
2761 if (ioc->reply_post_queue_depth >
2762 facts->MaxReplyDescriptorPostQueueDepth) {
2763 ioc->reply_post_queue_depth =
2764 facts->MaxReplyDescriptorPostQueueDepth -
2765 (facts->MaxReplyDescriptorPostQueueDepth % 16);
2766 ioc->hba_queue_depth =
2767 ((ioc->reply_post_queue_depth - 64) / 2) - 1;
2768 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
2769 }
2770
2771 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
2772 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
2773 "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
2774 ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
2775 ioc->chains_needed_per_io));
2776
9b05c91a
SR		 2777 /* reply post queue, 16 byte align */
2778 reply_post_free_sz = ioc->reply_post_queue_depth *
2779 sizeof(Mpi2DefaultReplyDescriptor_t);
2780
2781 sz = reply_post_free_sz;
2782 if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
2783 sz *= ioc->reply_queue_count;
2784
2785 ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
2786 (ioc->reply_queue_count):1,
2787 sizeof(struct reply_post_struct), GFP_KERNEL);
2788
2789 if (!ioc->reply_post) {
2790 pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n",
2791 ioc->name);
2792 goto out;
2793 }
2794 ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
2795 ioc->pdev, sz, 16, 0);
2796 if (!ioc->reply_post_free_dma_pool) {
2797 pr_err(MPT3SAS_FMT
2798 "reply_post_free pool: pci_pool_create failed\n",
2799 ioc->name);
2800 goto out;
2801 }
2802 i = 0;
2803 do {
2804 ioc->reply_post[i].reply_post_free =
2805 pci_pool_alloc(ioc->reply_post_free_dma_pool,
2806 GFP_KERNEL,
2807 &ioc->reply_post[i].reply_post_free_dma);
2808 if (!ioc->reply_post[i].reply_post_free) {
2809 pr_err(MPT3SAS_FMT
2810 "reply_post_free pool: pci_pool_alloc failed\n",
2811 ioc->name);
2812 goto out;
2813 }
2814 memset(ioc->reply_post[i].reply_post_free, 0, sz);
2815 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2816 "reply post free pool (0x%p): depth(%d),"
2817 "element_size(%d), pool_size(%d kB)\n", ioc->name,
2818 ioc->reply_post[i].reply_post_free,
2819 ioc->reply_post_queue_depth, 8, sz/1024));
2820 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2821 "reply_post_free_dma = (0x%llx)\n", ioc->name,
2822 (unsigned long long)
2823 ioc->reply_post[i].reply_post_free_dma));
2824 total_sz += sz;
2825 } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
2826
2827 if (ioc->dma_mask == 64) {
2828 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
2829 pr_warn(MPT3SAS_FMT
2830 "no suitable consistent DMA mask for %s\n",
2831 ioc->name, pci_name(ioc->pdev));
2832 goto out;
2833 }
2834 }
2835
f92363d1
SR		 2836 ioc->scsiio_depth = ioc->hba_queue_depth -
2837 ioc->hi_priority_depth - ioc->internal_depth;
2838
2839 /* set the scsi host can_queue depth
2840 * with some internal commands that could be outstanding
2841 */
2842 ioc->shost->can_queue = ioc->scsiio_depth;
2843 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2844 "scsi host: can_queue depth (%d)\n",
2845 ioc->name, ioc->shost->can_queue));
2846
2847
2848 /* contiguous pool for request and chains, 16 byte align, one extra "
2849 * "frame for smid=0
2850 */
2851 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
2852 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
2853
2854 /* hi-priority queue */
2855 sz += (ioc->hi_priority_depth * ioc->request_sz);
2856
2857 /* internal queue */
2858 sz += (ioc->internal_depth * ioc->request_sz);
2859
2860 ioc->request_dma_sz = sz;
2861 ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
2862 if (!ioc->request) {
2863 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
2864 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
2865 "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
2866 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
2867 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
2868 goto out;
2869 retry_sz += 64;
2870 ioc->hba_queue_depth = max_request_credit - retry_sz;
2871 goto retry_allocation;
2872 }
2873
2874 if (retry_sz)
2875 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
2876 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
2877 "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
2878 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
2879
2880 /* hi-priority queue */
2881 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
2882 ioc->request_sz);
2883 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
2884 ioc->request_sz);
2885
2886 /* internal queue */
2887 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
2888 ioc->request_sz);
2889 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
2890 ioc->request_sz);
2891
2892 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2893 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
2894 ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
2895 (ioc->hba_queue_depth * ioc->request_sz)/1024));
2896
2897 dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
2898 ioc->name, (unsigned long long) ioc->request_dma));
2899 total_sz += sz;
2900
2901 sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
2902 ioc->scsi_lookup_pages = get_order(sz);
2903 ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
2904 GFP_KERNEL, ioc->scsi_lookup_pages);
2905 if (!ioc->scsi_lookup) {
2906 pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n",
2907 ioc->name, (int)sz);
2908 goto out;
2909 }
2910
2911 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
2912 ioc->name, ioc->request, ioc->scsiio_depth));
2913
2914 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
2915 sz = ioc->chain_depth * sizeof(struct chain_tracker);
2916 ioc->chain_pages = get_order(sz);
2917 ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
2918 GFP_KERNEL, ioc->chain_pages);
2919 if (!ioc->chain_lookup) {
2920 pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n",
2921 ioc->name);
2922 goto out;
2923 }
2924 ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev,
2925 ioc->request_sz, 16, 0);
2926 if (!ioc->chain_dma_pool) {
2927 pr_err(MPT3SAS_FMT "chain_dma_pool: pci_pool_create failed\n",
2928 ioc->name);
2929 goto out;
2930 }
2931 for (i = 0; i < ioc->chain_depth; i++) {
2932 ioc->chain_lookup[i].chain_buffer = pci_pool_alloc(
2933 ioc->chain_dma_pool , GFP_KERNEL,
2934 &ioc->chain_lookup[i].chain_buffer_dma);
2935 if (!ioc->chain_lookup[i].chain_buffer) {
2936 ioc->chain_depth = i;
2937 goto chain_done;
2938 }
2939 total_sz += ioc->request_sz;
2940 }
2941 chain_done:
2942 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2943 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
2944 ioc->name, ioc->chain_depth, ioc->request_sz,
2945 ((ioc->chain_depth * ioc->request_sz))/1024));
2946
2947 /* initialize hi-priority queue smid's */
2948 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
2949 sizeof(struct request_tracker), GFP_KERNEL);
2950 if (!ioc->hpr_lookup) {
2951 pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
2952 ioc->name);
2953 goto out;
2954 }
2955 ioc->hi_priority_smid = ioc->scsiio_depth + 1;
2956 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2957 "hi_priority(0x%p): depth(%d), start smid(%d)\n",
2958 ioc->name, ioc->hi_priority,
2959 ioc->hi_priority_depth, ioc->hi_priority_smid));
2960
2961 /* initialize internal queue smid's */
2962 ioc->internal_lookup = kcalloc(ioc->internal_depth,
2963 sizeof(struct request_tracker), GFP_KERNEL);
2964 if (!ioc->internal_lookup) {
2965 pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
2966 ioc->name);
2967 goto out;
2968 }
2969 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
2970 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2971 "internal(0x%p): depth(%d), start smid(%d)\n",
2972 ioc->name, ioc->internal,
2973 ioc->internal_depth, ioc->internal_smid));
2974
2975 /* sense buffers, 4 byte align */
2976 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
2977 ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
2978 0);
2979 if (!ioc->sense_dma_pool) {
2980 pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n",
2981 ioc->name);
2982 goto out;
2983 }
2984 ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
2985 &ioc->sense_dma);
2986 if (!ioc->sense) {
2987 pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n",
2988 ioc->name);
2989 goto out;
2990 }
2991 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2992 "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
2993 "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
2994 SCSI_SENSE_BUFFERSIZE, sz/1024));
2995 dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
2996 ioc->name, (unsigned long long)ioc->sense_dma));
2997 total_sz += sz;
2998
2999 /* reply pool, 4 byte align */
3000 sz = ioc->reply_free_queue_depth * ioc->reply_sz;
3001 ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
3002 0);
3003 if (!ioc->reply_dma_pool) {
3004 pr_err(MPT3SAS_FMT "reply pool: pci_pool_create failed\n",
3005 ioc->name);
3006 goto out;
3007 }
3008 ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
3009 &ioc->reply_dma);
3010 if (!ioc->reply) {
3011 pr_err(MPT3SAS_FMT "reply pool: pci_pool_alloc failed\n",
3012 ioc->name);
3013 goto out;
3014 }
3015 ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
3016 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
3017 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3018 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3019 ioc->name, ioc->reply,
3020 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
3021 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
3022 ioc->name, (unsigned long long)ioc->reply_dma));
3023 total_sz += sz;
3024
3025 /* reply free queue, 16 byte align */
3026 sz = ioc->reply_free_queue_depth * 4;
3027 ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
3028 ioc->pdev, sz, 16, 0);
3029 if (!ioc->reply_free_dma_pool) {
3030 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_create failed\n",
3031 ioc->name);
3032 goto out;
3033 }
3034 ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
3035 &ioc->reply_free_dma);
3036 if (!ioc->reply_free) {
3037 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_alloc failed\n",
3038 ioc->name);
3039 goto out;
3040 }
3041 memset(ioc->reply_free, 0, sz);
3042 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
3043 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
3044 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
3045 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3046 "reply_free_dma (0x%llx)\n",
3047 ioc->name, (unsigned long long)ioc->reply_free_dma));
3048 total_sz += sz;
3049
f92363d1
SR		 3050 ioc->config_page_sz = 512;
3051 ioc->config_page = pci_alloc_consistent(ioc->pdev,
3052 ioc->config_page_sz, &ioc->config_page_dma);
3053 if (!ioc->config_page) {
3054 pr_err(MPT3SAS_FMT
3055 "config page: pci_pool_alloc failed\n",
3056 ioc->name);
3057 goto out;
3058 }
3059 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3060 "config page(0x%p): size(%d)\n",
3061 ioc->name, ioc->config_page, ioc->config_page_sz));
3062 dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
3063 ioc->name, (unsigned long long)ioc->config_page_dma));
3064 total_sz += ioc->config_page_sz;
3065
3066 pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
3067 ioc->name, total_sz/1024);
3068 pr_info(MPT3SAS_FMT
3069 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
3070 ioc->name, ioc->shost->can_queue, facts->RequestCredit);
3071 pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
3072 ioc->name, ioc->shost->sg_tablesize);
3073 return 0;
3074
3075 out:
3076 return -ENOMEM;
3077}
3078
3079/**
3080 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
3081 * @ioc: Pointer to MPT_ADAPTER structure
3082 * @cooked: Request raw or cooked IOC state
3083 *
3084 * Returns all IOC Doorbell register bits if cooked==0, else just the
3085 * Doorbell bits in MPI_IOC_STATE_MASK.
3086 */
3087u32
3088mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
3089{
3090 u32 s, sc;
3091
3092 s = readl(&ioc->chip->Doorbell);
3093 sc = s & MPI2_IOC_STATE_MASK;
3094 return cooked ? sc : s;
3095}
3096
3097/**
3098 * _base_wait_on_iocstate - waiting on a particular ioc state
3099 * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
3100 * @timeout: timeout in second
3101 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3102 *
3103 * Returns 0 for success, non-zero for failure.
3104 */
3105static int
3106_base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout,
3107 int sleep_flag)
3108{
3109 u32 count, cntdn;
3110 u32 current_state;
3111
3112 count = 0;
3113 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3114 do {
3115 current_state = mpt3sas_base_get_iocstate(ioc, 1);
3116 if (current_state == ioc_state)
3117 return 0;
3118 if (count && current_state == MPI2_IOC_STATE_FAULT)
3119 break;
3120 if (sleep_flag == CAN_SLEEP)
3121 usleep_range(1000, 1500);
3122 else
3123 udelay(500);
3124 count++;
3125 } while (--cntdn);
3126
3127 return current_state;
3128}
3129
3130/**
3131 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
3132 * a write to the doorbell)
3133 * @ioc: per adapter object
3134 * @timeout: timeout in second
3135 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3136 *
3137 * Returns 0 for success, non-zero for failure.
3138 *
3139 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
3140 */
3141static int
3142_base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout,
3143 int sleep_flag)
3144{
3145 u32 cntdn, count;
3146 u32 int_status;
3147
3148 count = 0;
3149 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3150 do {
3151 int_status = readl(&ioc->chip->HostInterruptStatus);
3152 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3153 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3154 "%s: successful count(%d), timeout(%d)\n",
3155 ioc->name, __func__, count, timeout));
3156 return 0;
3157 }
3158 if (sleep_flag == CAN_SLEEP)
3159 usleep_range(1000, 1500);
3160 else
3161 udelay(500);
3162 count++;
3163 } while (--cntdn);
3164
3165 pr_err(MPT3SAS_FMT
3166 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3167 ioc->name, __func__, count, int_status);
3168 return -EFAULT;
3169}
3170
3171/**
3172 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
3173 * @ioc: per adapter object
3174 * @timeout: timeout in second
3175 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3176 *
3177 * Returns 0 for success, non-zero for failure.
3178 *
3179 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
3180 * doorbell.
3181 */
3182static int
3183_base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout,
3184 int sleep_flag)
3185{
3186 u32 cntdn, count;
3187 u32 int_status;
3188 u32 doorbell;
3189
3190 count = 0;
3191 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3192 do {
3193 int_status = readl(&ioc->chip->HostInterruptStatus);
3194 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
3195 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3196 "%s: successful count(%d), timeout(%d)\n",
3197 ioc->name, __func__, count, timeout));
3198 return 0;
3199 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3200 doorbell = readl(&ioc->chip->Doorbell);
3201 if ((doorbell & MPI2_IOC_STATE_MASK) ==
3202 MPI2_IOC_STATE_FAULT) {
3203 mpt3sas_base_fault_info(ioc , doorbell);
3204 return -EFAULT;
3205 }
3206 } else if (int_status == 0xFFFFFFFF)
3207 goto out;
3208
3209 if (sleep_flag == CAN_SLEEP)
3210 usleep_range(1000, 1500);
3211 else
3212 udelay(500);
3213 count++;
3214 } while (--cntdn);
3215
3216 out:
3217 pr_err(MPT3SAS_FMT
3218 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3219 ioc->name, __func__, count, int_status);
3220 return -EFAULT;
3221}
3222
3223/**
3224 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
3225 * @ioc: per adapter object
3226 * @timeout: timeout in second
3227 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3228 *
3229 * Returns 0 for success, non-zero for failure.
3230 *
3231 */
3232static int
3233_base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout,
3234 int sleep_flag)
3235{
3236 u32 cntdn, count;
3237 u32 doorbell_reg;
3238
3239 count = 0;
3240 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3241 do {
3242 doorbell_reg = readl(&ioc->chip->Doorbell);
3243 if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
3244 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3245 "%s: successful count(%d), timeout(%d)\n",
3246 ioc->name, __func__, count, timeout));
3247 return 0;
3248 }
3249 if (sleep_flag == CAN_SLEEP)
3250 usleep_range(1000, 1500);
3251 else
3252 udelay(500);
3253 count++;
3254 } while (--cntdn);
3255
3256 pr_err(MPT3SAS_FMT
3257 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
3258 ioc->name, __func__, count, doorbell_reg);
3259 return -EFAULT;
3260}
3261
3262/**
3263 * _base_send_ioc_reset - send doorbell reset
3264 * @ioc: per adapter object
3265 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
3266 * @timeout: timeout in second
3267 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3268 *
3269 * Returns 0 for success, non-zero for failure.
3270 */
3271static int
3272_base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout,
3273 int sleep_flag)
3274{
3275 u32 ioc_state;
3276 int r = 0;
3277
3278 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
3279 pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
3280 ioc->name, __func__);
3281 return -EFAULT;
3282 }
3283
3284 if (!(ioc->facts.IOCCapabilities &
3285 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
3286 return -EFAULT;
3287
3288 pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
3289
3290 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
3291 &ioc->chip->Doorbell);
3292 if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) {
3293 r = -EFAULT;
3294 goto out;
3295 }
3296 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
3297 timeout, sleep_flag);
3298 if (ioc_state) {
3299 pr_err(MPT3SAS_FMT
3300 "%s: failed going to ready state (ioc_state=0x%x)\n",
3301 ioc->name, __func__, ioc_state);
3302 r = -EFAULT;
3303 goto out;
3304 }
3305 out:
3306 pr_info(MPT3SAS_FMT "message unit reset: %s\n",
3307 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
3308 return r;
3309}
3310
3311/**
3312 * _base_handshake_req_reply_wait - send request thru doorbell interface
3313 * @ioc: per adapter object
3314 * @request_bytes: request length
3315 * @request: pointer having request payload
3316 * @reply_bytes: reply length
3317 * @reply: pointer to reply payload
3318 * @timeout: timeout in second
3319 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3320 *
3321 * Returns 0 for success, non-zero for failure.
3322 */
3323static int
3324_base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
3325 u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag)
3326{
3327 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
3328 int i;
3329 u8 failed;
3330 u16 dummy;
3331 __le32 *mfp;
3332
3333 /* make sure doorbell is not in use */
3334 if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
3335 pr_err(MPT3SAS_FMT
3336 "doorbell is in use (line=%d)\n",
3337 ioc->name, __LINE__);
3338 return -EFAULT;
3339 }
3340
3341 /* clear pending doorbell interrupts from previous state changes */
3342 if (readl(&ioc->chip->HostInterruptStatus) &
3343 MPI2_HIS_IOC2SYS_DB_STATUS)
3344 writel(0, &ioc->chip->HostInterruptStatus);
3345
3346 /* send message to ioc */
3347 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
3348 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
3349 &ioc->chip->Doorbell);
3350
3351 if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) {
3352 pr_err(MPT3SAS_FMT
3353 "doorbell handshake int failed (line=%d)\n",
3354 ioc->name, __LINE__);
3355 return -EFAULT;
3356 }
3357 writel(0, &ioc->chip->HostInterruptStatus);
3358
3359 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) {
3360 pr_err(MPT3SAS_FMT
3361 "doorbell handshake ack failed (line=%d)\n",
3362 ioc->name, __LINE__);
3363 return -EFAULT;
3364 }
3365
3366 /* send message 32-bits at a time */
3367 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
3368 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
3369 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag)))
3370 failed = 1;
3371 }
3372
3373 if (failed) {
3374 pr_err(MPT3SAS_FMT
3375 "doorbell handshake sending request failed (line=%d)\n",
3376 ioc->name, __LINE__);
3377 return -EFAULT;
3378 }
3379
3380 /* now wait for the reply */
3381 if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) {
3382 pr_err(MPT3SAS_FMT
3383 "doorbell handshake int failed (line=%d)\n",
3384 ioc->name, __LINE__);
3385 return -EFAULT;
3386 }
3387
3388 /* read the first two 16-bits, it gives the total length of the reply */
3389 reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3390 & MPI2_DOORBELL_DATA_MASK);
3391 writel(0, &ioc->chip->HostInterruptStatus);
3392 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3393 pr_err(MPT3SAS_FMT
3394 "doorbell handshake int failed (line=%d)\n",
3395 ioc->name, __LINE__);
3396 return -EFAULT;
3397 }
3398 reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3399 & MPI2_DOORBELL_DATA_MASK);
3400 writel(0, &ioc->chip->HostInterruptStatus);
3401
3402 for (i = 2; i < default_reply->MsgLength * 2; i++) {
3403 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3404 pr_err(MPT3SAS_FMT
3405 "doorbell handshake int failed (line=%d)\n",
3406 ioc->name, __LINE__);
3407 return -EFAULT;
3408 }
3409 if (i >= reply_bytes/2) /* overflow case */
3410 dummy = readl(&ioc->chip->Doorbell);
3411 else
3412 reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3413 & MPI2_DOORBELL_DATA_MASK);
3414 writel(0, &ioc->chip->HostInterruptStatus);
3415 }
3416
3417 _base_wait_for_doorbell_int(ioc, 5, sleep_flag);
3418 if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) {
3419 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3420 "doorbell is in use (line=%d)\n", ioc->name, __LINE__));
3421 }
3422 writel(0, &ioc->chip->HostInterruptStatus);
3423
3424 if (ioc->logging_level & MPT_DEBUG_INIT) {
3425 mfp = (__le32 *)reply;
3426 pr_info("\toffset:data\n");
3427 for (i = 0; i < reply_bytes/4; i++)
3428 pr_info("\t[0x%02x]:%08x\n", i*4,
3429 le32_to_cpu(mfp[i]));
3430 }
3431 return 0;
3432}
3433
3434/**
3435 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
3436 * @ioc: per adapter object
3437 * @mpi_reply: the reply payload from FW
3438 * @mpi_request: the request payload sent to FW
3439 *
3440 * The SAS IO Unit Control Request message allows the host to perform low-level
3441 * operations, such as resets on the PHYs of the IO Unit, also allows the host
3442 * to obtain the IOC assigned device handles for a device if it has other
3443 * identifying information about the device, in addition allows the host to
3444 * remove IOC resources associated with the device.
3445 *
3446 * Returns 0 for success, non-zero for failure.
3447 */
3448int
3449mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
3450 Mpi2SasIoUnitControlReply_t *mpi_reply,
3451 Mpi2SasIoUnitControlRequest_t *mpi_request)
3452{
3453 u16 smid;
3454 u32 ioc_state;
3455 unsigned long timeleft;
eb44552b 3456 bool issue_reset = false;
f92363d1
SR		 3457 int rc;
3458 void *request;
3459 u16 wait_state_count;
3460
3461 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3462 __func__));
3463
3464 mutex_lock(&ioc->base_cmds.mutex);
3465
3466 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
3467 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
3468 ioc->name, __func__);
3469 rc = -EAGAIN;
3470 goto out;
3471 }
3472
3473 wait_state_count = 0;
3474 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3475 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
3476 if (wait_state_count++ == 10) {
3477 pr_err(MPT3SAS_FMT
3478 "%s: failed due to ioc not operational\n",
3479 ioc->name, __func__);
3480 rc = -EFAULT;
3481 goto out;
3482 }
3483 ssleep(1);
3484 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3485 pr_info(MPT3SAS_FMT
3486 "%s: waiting for operational state(count=%d)\n",
3487 ioc->name, __func__, wait_state_count);
3488 }
3489
3490 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
3491 if (!smid) {
3492 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
3493 ioc->name, __func__);
3494 rc = -EAGAIN;
3495 goto out;
3496 }
3497
3498 rc = 0;
3499 ioc->base_cmds.status = MPT3_CMD_PENDING;
3500 request = mpt3sas_base_get_msg_frame(ioc, smid);
3501 ioc->base_cmds.smid = smid;
3502 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
3503 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
3504 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
3505 ioc->ioc_link_reset_in_progress = 1;
3506 init_completion(&ioc->base_cmds.done);
3507 mpt3sas_base_put_smid_default(ioc, smid);
3508 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
3509 msecs_to_jiffies(10000));
3510 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
3511 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
3512 ioc->ioc_link_reset_in_progress)
3513 ioc->ioc_link_reset_in_progress = 0;
3514 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
3515 pr_err(MPT3SAS_FMT "%s: timeout\n",
3516 ioc->name, __func__);
3517 _debug_dump_mf(mpi_request,
3518 sizeof(Mpi2SasIoUnitControlRequest_t)/4);
3519 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
eb44552b 3520 issue_reset = true;
f92363d1
SR		 3521 goto issue_host_reset;
3522 }
3523 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
3524 memcpy(mpi_reply, ioc->base_cmds.reply,
3525 sizeof(Mpi2SasIoUnitControlReply_t));
3526 else
3527 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
3528 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3529 goto out;
3530
3531 issue_host_reset:
3532 if (issue_reset)
3533 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
3534 FORCE_BIG_HAMMER);
3535 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3536 rc = -EFAULT;
3537 out:
3538 mutex_unlock(&ioc->base_cmds.mutex);
3539 return rc;
3540}
3541
3542/**
3543 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
3544 * @ioc: per adapter object
3545 * @mpi_reply: the reply payload from FW
3546 * @mpi_request: the request payload sent to FW
3547 *
3548 * The SCSI Enclosure Processor request message causes the IOC to
3549 * communicate with SES devices to control LED status signals.
3550 *
3551 * Returns 0 for success, non-zero for failure.
3552 */
3553int
3554mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
3555 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
3556{
3557 u16 smid;
3558 u32 ioc_state;
3559 unsigned long timeleft;
eb44552b 3560 bool issue_reset = false;
f92363d1
SR		 3561 int rc;
3562 void *request;
3563 u16 wait_state_count;
3564
3565 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3566 __func__));
3567
3568 mutex_lock(&ioc->base_cmds.mutex);
3569
3570 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
3571 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
3572 ioc->name, __func__);
3573 rc = -EAGAIN;
3574 goto out;
3575 }
3576
3577 wait_state_count = 0;
3578 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3579 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
3580 if (wait_state_count++ == 10) {
3581 pr_err(MPT3SAS_FMT
3582 "%s: failed due to ioc not operational\n",
3583 ioc->name, __func__);
3584 rc = -EFAULT;
3585 goto out;
3586 }
3587 ssleep(1);
3588 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3589 pr_info(MPT3SAS_FMT
3590 "%s: waiting for operational state(count=%d)\n",
3591 ioc->name,
3592 __func__, wait_state_count);
3593 }
3594
3595 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
3596 if (!smid) {
3597 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
3598 ioc->name, __func__);
3599 rc = -EAGAIN;
3600 goto out;
3601 }
3602
3603 rc = 0;
3604 ioc->base_cmds.status = MPT3_CMD_PENDING;
3605 request = mpt3sas_base_get_msg_frame(ioc, smid);
3606 ioc->base_cmds.smid = smid;
3607 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
3608 init_completion(&ioc->base_cmds.done);
3609 mpt3sas_base_put_smid_default(ioc, smid);
3610 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
3611 msecs_to_jiffies(10000));
3612 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
3613 pr_err(MPT3SAS_FMT "%s: timeout\n",
3614 ioc->name, __func__);
3615 _debug_dump_mf(mpi_request,
3616 sizeof(Mpi2SepRequest_t)/4);
3617 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
eb44552b 3618 issue_reset = false;
f92363d1
SR		 3619 goto issue_host_reset;
3620 }
3621 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
3622 memcpy(mpi_reply, ioc->base_cmds.reply,
3623 sizeof(Mpi2SepReply_t));
3624 else
3625 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
3626 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3627 goto out;
3628
3629 issue_host_reset:
3630 if (issue_reset)
3631 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
3632 FORCE_BIG_HAMMER);
3633 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3634 rc = -EFAULT;
3635 out:
3636 mutex_unlock(&ioc->base_cmds.mutex);
3637 return rc;
3638}
3639
3640/**
3641 * _base_get_port_facts - obtain port facts reply and save in ioc
3642 * @ioc: per adapter object
3643 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3644 *
3645 * Returns 0 for success, non-zero for failure.
3646 */
3647static int
3648_base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port, int sleep_flag)
3649{
3650 Mpi2PortFactsRequest_t mpi_request;
3651 Mpi2PortFactsReply_t mpi_reply;
3652 struct mpt3sas_port_facts *pfacts;
3653 int mpi_reply_sz, mpi_request_sz, r;
3654
3655 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3656 __func__));
3657
3658 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
3659 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
3660 memset(&mpi_request, 0, mpi_request_sz);
3661 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
3662 mpi_request.PortNumber = port;
3663 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
3664 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
3665
3666 if (r != 0) {
3667 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
3668 ioc->name, __func__, r);
3669 return r;
3670 }
3671
3672 pfacts = &ioc->pfacts[port];
3673 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
3674 pfacts->PortNumber = mpi_reply.PortNumber;
3675 pfacts->VP_ID = mpi_reply.VP_ID;
3676 pfacts->VF_ID = mpi_reply.VF_ID;
3677 pfacts->MaxPostedCmdBuffers =
3678 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
3679
3680 return 0;
3681}
3682
3683/**
3684 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
3685 * @ioc: per adapter object
3686 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3687 *
3688 * Returns 0 for success, non-zero for failure.
3689 */
3690static int
3691_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
3692{
3693 Mpi2IOCFactsRequest_t mpi_request;
3694 Mpi2IOCFactsReply_t mpi_reply;
3695 struct mpt3sas_facts *facts;
3696 int mpi_reply_sz, mpi_request_sz, r;
3697
3698 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3699 __func__));
3700
3701 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
3702 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
3703 memset(&mpi_request, 0, mpi_request_sz);
3704 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
3705 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
3706 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
3707
3708 if (r != 0) {
3709 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
3710 ioc->name, __func__, r);
3711 return r;
3712 }
3713
3714 facts = &ioc->facts;
3715 memset(facts, 0, sizeof(struct mpt3sas_facts));
3716 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
3717 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
3718 facts->VP_ID = mpi_reply.VP_ID;
3719 facts->VF_ID = mpi_reply.VF_ID;
3720 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
3721 facts->MaxChainDepth = mpi_reply.MaxChainDepth;
3722 facts->WhoInit = mpi_reply.WhoInit;
3723 facts->NumberOfPorts = mpi_reply.NumberOfPorts;
3724 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
3725 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
3726 facts->MaxReplyDescriptorPostQueueDepth =
3727 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
3728 facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
3729 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
3730 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
3731 ioc->ir_firmware = 1;
9b05c91a
SR		 3732 if ((facts->IOCCapabilities &
3733 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE))
3734 ioc->rdpq_array_capable = 1;
f92363d1
SR		 3735 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
3736 facts->IOCRequestFrameSize =
3737 le16_to_cpu(mpi_reply.IOCRequestFrameSize);
3738 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
3739 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
3740 ioc->shost->max_id = -1;
3741 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
3742 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
3743 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
3744 facts->HighPriorityCredit =
3745 le16_to_cpu(mpi_reply.HighPriorityCredit);
3746 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
3747 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
3748
3749 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3750 "hba queue depth(%d), max chains per io(%d)\n",
3751 ioc->name, facts->RequestCredit,
3752 facts->MaxChainDepth));
3753 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3754 "request frame size(%d), reply frame size(%d)\n", ioc->name,
3755 facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
3756 return 0;
3757}
3758
3759/**
3760 * _base_send_ioc_init - send ioc_init to firmware
3761 * @ioc: per adapter object
3762 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3763 *
3764 * Returns 0 for success, non-zero for failure.
3765 */
3766static int
3767_base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
3768{
3769 Mpi2IOCInitRequest_t mpi_request;
3770 Mpi2IOCInitReply_t mpi_reply;
9b05c91a 3771 int i, r = 0;
f92363d1
SR		 3772 struct timeval current_time;
3773 u16 ioc_status;
9b05c91a
SR		 3774 u32 reply_post_free_array_sz = 0;
3775 Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL;
3776 dma_addr_t reply_post_free_array_dma;
f92363d1
SR		 3777
3778 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3779 __func__));
3780
3781 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
3782 mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
3783 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
3784 mpi_request.VF_ID = 0; /* TODO */
3785 mpi_request.VP_ID = 0;
3786 mpi_request.MsgVersion = cpu_to_le16(MPI2_VERSION);
3787 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
3788
3789 if (_base_is_controller_msix_enabled(ioc))
3790 mpi_request.HostMSIxVectors = ioc->reply_queue_count;
3791 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
3792 mpi_request.ReplyDescriptorPostQueueDepth =
3793 cpu_to_le16(ioc->reply_post_queue_depth);
3794 mpi_request.ReplyFreeQueueDepth =
3795 cpu_to_le16(ioc->reply_free_queue_depth);
3796
3797 mpi_request.SenseBufferAddressHigh =
3798 cpu_to_le32((u64)ioc->sense_dma >> 32);
3799 mpi_request.SystemReplyAddressHigh =
3800 cpu_to_le32((u64)ioc->reply_dma >> 32);
3801 mpi_request.SystemRequestFrameBaseAddress =
3802 cpu_to_le64((u64)ioc->request_dma);
3803 mpi_request.ReplyFreeQueueAddress =
3804 cpu_to_le64((u64)ioc->reply_free_dma);
f92363d1 3805
9b05c91a
SR		 3806 if (ioc->rdpq_array_enable) {
3807 reply_post_free_array_sz = ioc->reply_queue_count *
3808 sizeof(Mpi2IOCInitRDPQArrayEntry);
3809 reply_post_free_array = pci_alloc_consistent(ioc->pdev,
3810 reply_post_free_array_sz, &reply_post_free_array_dma);
3811 if (!reply_post_free_array) {
3812 pr_err(MPT3SAS_FMT
3813 "reply_post_free_array: pci_alloc_consistent failed\n",
3814 ioc->name);
3815 r = -ENOMEM;
3816 goto out;
3817 }
3818 memset(reply_post_free_array, 0, reply_post_free_array_sz);
3819 for (i = 0; i < ioc->reply_queue_count; i++)
3820 reply_post_free_array[i].RDPQBaseAddress =
3821 cpu_to_le64(
3822 (u64)ioc->reply_post[i].reply_post_free_dma);
3823 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
3824 mpi_request.ReplyDescriptorPostQueueAddress =
3825 cpu_to_le64((u64)reply_post_free_array_dma);
3826 } else {
3827 mpi_request.ReplyDescriptorPostQueueAddress =
3828 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
3829 }
f92363d1
SR		 3830
3831 /* This time stamp specifies number of milliseconds
3832 * since epoch ~ midnight January 1, 1970.
3833 */
3834 do_gettimeofday(&current_time);
3835 mpi_request.TimeStamp = cpu_to_le64((u64)current_time.tv_sec * 1000 +
3836 (current_time.tv_usec / 1000));
3837
3838 if (ioc->logging_level & MPT_DEBUG_INIT) {
3839 __le32 *mfp;
3840 int i;
3841
3842 mfp = (__le32 *)&mpi_request;
3843 pr_info("\toffset:data\n");
3844 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
3845 pr_info("\t[0x%02x]:%08x\n", i*4,
3846 le32_to_cpu(mfp[i]));
3847 }
3848
3849 r = _base_handshake_req_reply_wait(ioc,
3850 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
3851 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10,
3852 sleep_flag);
3853
3854 if (r != 0) {
3855 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
3856 ioc->name, __func__, r);
9b05c91a 3857 goto out;
f92363d1
SR		 3858 }
3859
3860 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
3861 if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
3862 mpi_reply.IOCLogInfo) {
3863 pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
3864 r = -EIO;
3865 }
3866
9b05c91a
SR		 3867out:
3868 if (reply_post_free_array)
3869 pci_free_consistent(ioc->pdev, reply_post_free_array_sz,
3870 reply_post_free_array,
3871 reply_post_free_array_dma);
3872 return r;
f92363d1
SR		 3873}
3874
3875/**
3876 * mpt3sas_port_enable_done - command completion routine for port enable
3877 * @ioc: per adapter object
3878 * @smid: system request message index
3879 * @msix_index: MSIX table index supplied by the OS
3880 * @reply: reply message frame(lower 32bit addr)
3881 *
3882 * Return 1 meaning mf should be freed from _base_interrupt
3883 * 0 means the mf is freed from this function.
3884 */
3885u8
3886mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
3887 u32 reply)
3888{
3889 MPI2DefaultReply_t *mpi_reply;
3890 u16 ioc_status;
3891
3892 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
3893 return 1;
3894
3895 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
3896 if (!mpi_reply)
3897 return 1;
3898
3899 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
3900 return 1;
3901
3902 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
3903 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
3904 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
3905 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
3906 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
3907 if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
3908 ioc->port_enable_failed = 1;
3909
3910 if (ioc->is_driver_loading) {
3911 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
3912 mpt3sas_port_enable_complete(ioc);
3913 return 1;
3914 } else {
3915 ioc->start_scan_failed = ioc_status;
3916 ioc->start_scan = 0;
3917 return 1;
3918 }
3919 }
3920 complete(&ioc->port_enable_cmds.done);
3921 return 1;
3922}
3923
3924/**
3925 * _base_send_port_enable - send port_enable(discovery stuff) to firmware
3926 * @ioc: per adapter object
3927 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3928 *
3929 * Returns 0 for success, non-zero for failure.
3930 */
3931static int
3932_base_send_port_enable(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
3933{
3934 Mpi2PortEnableRequest_t *mpi_request;
3935 Mpi2PortEnableReply_t *mpi_reply;
3936 unsigned long timeleft;
3937 int r = 0;
3938 u16 smid;
3939 u16 ioc_status;
3940
3941 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
3942
3943 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
3944 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
3945 ioc->name, __func__);
3946 return -EAGAIN;
3947 }
3948
3949 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
3950 if (!smid) {
3951 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
3952 ioc->name, __func__);
3953 return -EAGAIN;
3954 }
3955
3956 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
3957 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
3958 ioc->port_enable_cmds.smid = smid;
3959 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
3960 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
3961
3962 init_completion(&ioc->port_enable_cmds.done);
3963 mpt3sas_base_put_smid_default(ioc, smid);
3964 timeleft = wait_for_completion_timeout(&ioc->port_enable_cmds.done,
3965 300*HZ);
3966 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
3967 pr_err(MPT3SAS_FMT "%s: timeout\n",
3968 ioc->name, __func__);
3969 _debug_dump_mf(mpi_request,
3970 sizeof(Mpi2PortEnableRequest_t)/4);
3971 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
3972 r = -EFAULT;
3973 else
3974 r = -ETIME;
3975 goto out;
3976 }
3977
3978 mpi_reply = ioc->port_enable_cmds.reply;
3979 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
3980 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
3981 pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
3982 ioc->name, __func__, ioc_status);
3983 r = -EFAULT;
3984 goto out;
3985 }
3986
3987 out:
3988 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
3989 pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
3990 "SUCCESS" : "FAILED"));
3991 return r;
3992}
3993
3994/**
3995 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
3996 * @ioc: per adapter object
3997 *
3998 * Returns 0 for success, non-zero for failure.
3999 */
4000int
4001mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
4002{
4003 Mpi2PortEnableRequest_t *mpi_request;
4004 u16 smid;
4005
4006 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4007
4008 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4009 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4010 ioc->name, __func__);
4011 return -EAGAIN;
4012 }
4013
4014 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4015 if (!smid) {
4016 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4017 ioc->name, __func__);
4018 return -EAGAIN;
4019 }
4020
4021 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4022 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4023 ioc->port_enable_cmds.smid = smid;
4024 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4025 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4026
4027 mpt3sas_base_put_smid_default(ioc, smid);
4028 return 0;
4029}
4030
4031/**
4032 * _base_determine_wait_on_discovery - desposition
4033 * @ioc: per adapter object
4034 *
4035 * Decide whether to wait on discovery to complete. Used to either
4036 * locate boot device, or report volumes ahead of physical devices.
4037 *
4038 * Returns 1 for wait, 0 for don't wait
4039 */
4040static int
4041_base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
4042{
4043 /* We wait for discovery to complete if IR firmware is loaded.
4044 * The sas topology events arrive before PD events, so we need time to
4045 * turn on the bit in ioc->pd_handles to indicate PD
4046 * Also, it maybe required to report Volumes ahead of physical
4047 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
4048 */
4049 if (ioc->ir_firmware)
4050 return 1;
4051
4052 /* if no Bios, then we don't need to wait */
4053 if (!ioc->bios_pg3.BiosVersion)
4054 return 0;
4055
4056 /* Bios is present, then we drop down here.
4057 *
4058 * If there any entries in the Bios Page 2, then we wait
4059 * for discovery to complete.
4060 */
4061
4062 /* Current Boot Device */
4063 if ((ioc->bios_pg2.CurrentBootDeviceForm &
4064 MPI2_BIOSPAGE2_FORM_MASK) ==
4065 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4066 /* Request Boot Device */
4067 (ioc->bios_pg2.ReqBootDeviceForm &
4068 MPI2_BIOSPAGE2_FORM_MASK) ==
4069 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4070 /* Alternate Request Boot Device */
4071 (ioc->bios_pg2.ReqAltBootDeviceForm &
4072 MPI2_BIOSPAGE2_FORM_MASK) ==
4073 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
4074 return 0;
4075
4076 return 1;
4077}
4078
4079/**
4080 * _base_unmask_events - turn on notification for this event
4081 * @ioc: per adapter object
4082 * @event: firmware event
4083 *
4084 * The mask is stored in ioc->event_masks.
4085 */
4086static void
4087_base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
4088{
4089 u32 desired_event;
4090
4091 if (event >= 128)
4092 return;
4093
4094 desired_event = (1 << (event % 32));
4095
4096 if (event < 32)
4097 ioc->event_masks[0] &= ~desired_event;
4098 else if (event < 64)
4099 ioc->event_masks[1] &= ~desired_event;
4100 else if (event < 96)
4101 ioc->event_masks[2] &= ~desired_event;
4102 else if (event < 128)
4103 ioc->event_masks[3] &= ~desired_event;
4104}
4105
4106/**
4107 * _base_event_notification - send event notification
4108 * @ioc: per adapter object
4109 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4110 *
4111 * Returns 0 for success, non-zero for failure.
4112 */
4113static int
4114_base_event_notification(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4115{
4116 Mpi2EventNotificationRequest_t *mpi_request;
4117 unsigned long timeleft;
4118 u16 smid;
4119 int r = 0;
4120 int i;
4121
4122 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4123 __func__));
4124
4125 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4126 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4127 ioc->name, __func__);
4128 return -EAGAIN;
4129 }
4130
4131 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4132 if (!smid) {
4133 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4134 ioc->name, __func__);
4135 return -EAGAIN;
4136 }
4137 ioc->base_cmds.status = MPT3_CMD_PENDING;
4138 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4139 ioc->base_cmds.smid = smid;
4140 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
4141 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
4142 mpi_request->VF_ID = 0; /* TODO */
4143 mpi_request->VP_ID = 0;
4144 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4145 mpi_request->EventMasks[i] =
4146 cpu_to_le32(ioc->event_masks[i]);
4147 init_completion(&ioc->base_cmds.done);
4148 mpt3sas_base_put_smid_default(ioc, smid);
4149 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
4150 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4151 pr_err(MPT3SAS_FMT "%s: timeout\n",
4152 ioc->name, __func__);
4153 _debug_dump_mf(mpi_request,
4154 sizeof(Mpi2EventNotificationRequest_t)/4);
4155 if (ioc->base_cmds.status & MPT3_CMD_RESET)
4156 r = -EFAULT;
4157 else
4158 r = -ETIME;
4159 } else
4160 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
4161 ioc->name, __func__));
4162 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4163 return r;
4164}
4165
4166/**
4167 * mpt3sas_base_validate_event_type - validating event types
4168 * @ioc: per adapter object
4169 * @event: firmware event
4170 *
4171 * This will turn on firmware event notification when application
4172 * ask for that event. We don't mask events that are already enabled.
4173 */
4174void
4175mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
4176{
4177 int i, j;
4178 u32 event_mask, desired_event;
4179 u8 send_update_to_fw;
4180
4181 for (i = 0, send_update_to_fw = 0; i <
4182 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
4183 event_mask = ~event_type[i];
4184 desired_event = 1;
4185 for (j = 0; j < 32; j++) {
4186 if (!(event_mask & desired_event) &&
4187 (ioc->event_masks[i] & desired_event)) {
4188 ioc->event_masks[i] &= ~desired_event;
4189 send_update_to_fw = 1;
4190 }
4191 desired_event = (desired_event << 1);
4192 }
4193 }
4194
4195 if (!send_update_to_fw)
4196 return;
4197
4198 mutex_lock(&ioc->base_cmds.mutex);
4199 _base_event_notification(ioc, CAN_SLEEP);
4200 mutex_unlock(&ioc->base_cmds.mutex);
4201}
4202
4203/**
4204 * _base_diag_reset - the "big hammer" start of day reset
4205 * @ioc: per adapter object
4206 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4207 *
4208 * Returns 0 for success, non-zero for failure.
4209 */
4210static int
4211_base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4212{
4213 u32 host_diagnostic;
4214 u32 ioc_state;
4215 u32 count;
4216 u32 hcb_size;
4217
4218 pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
4219
4220 drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
4221 ioc->name));
4222
4223 count = 0;
4224 do {
4225 /* Write magic sequence to WriteSequence register
4226 * Loop until in diagnostic mode
4227 */
4228 drsprintk(ioc, pr_info(MPT3SAS_FMT
4229 "write magic sequence\n", ioc->name));
4230 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4231 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
4232 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
4233 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
4234 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
4235 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
4236 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
4237
4238 /* wait 100 msec */
4239 if (sleep_flag == CAN_SLEEP)
4240 msleep(100);
4241 else
4242 mdelay(100);
4243
4244 if (count++ > 20)
4245 goto out;
4246
4247 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4248 drsprintk(ioc, pr_info(MPT3SAS_FMT
4249 "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
4250 ioc->name, count, host_diagnostic));
4251
4252 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
4253
4254 hcb_size = readl(&ioc->chip->HCBSize);
4255
4256 drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
4257 ioc->name));
4258 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
4259 &ioc->chip->HostDiagnostic);
4260
b453ff84
SR		 4261 /*This delay allows the chip PCIe hardware time to finish reset tasks*/
4262 if (sleep_flag == CAN_SLEEP)
4263 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
4264 else
4265 mdelay(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
f92363d1 4266
b453ff84
SR		 4267 /* Approximately 300 second max wait */
4268 for (count = 0; count < (300000000 /
4269 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
f92363d1
SR		 4270
4271 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4272
4273 if (host_diagnostic == 0xFFFFFFFF)
4274 goto out;
4275 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
4276 break;
4277
b453ff84 4278 /* Wait to pass the second read delay window */
f92363d1 4279 if (sleep_flag == CAN_SLEEP)
b453ff84
SR		 4280 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4281 / 1000);
f92363d1 4282 else
b453ff84
SR		 4283 mdelay(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4284 / 1000);
f92363d1
SR		 4285 }
4286
4287 if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
4288
4289 drsprintk(ioc, pr_info(MPT3SAS_FMT
4290 "restart the adapter assuming the HCB Address points to good F/W\n",
4291 ioc->name));
4292 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
4293 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
4294 writel(host_diagnostic, &ioc->chip->HostDiagnostic);
4295
4296 drsprintk(ioc, pr_info(MPT3SAS_FMT
4297 "re-enable the HCDW\n", ioc->name));
4298 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
4299 &ioc->chip->HCBSize);
4300 }
4301
4302 drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
4303 ioc->name));
4304 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
4305 &ioc->chip->HostDiagnostic);
4306
4307 drsprintk(ioc, pr_info(MPT3SAS_FMT
4308 "disable writes to the diagnostic register\n", ioc->name));
4309 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4310
4311 drsprintk(ioc, pr_info(MPT3SAS_FMT
4312 "Wait for FW to go to the READY state\n", ioc->name));
4313 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20,
4314 sleep_flag);
4315 if (ioc_state) {
4316 pr_err(MPT3SAS_FMT
4317 "%s: failed going to ready state (ioc_state=0x%x)\n",
4318 ioc->name, __func__, ioc_state);
4319 goto out;
4320 }
4321
4322 pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
4323 return 0;
4324
4325 out:
4326 pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
4327 return -EFAULT;
4328}
4329
4330/**
4331 * _base_make_ioc_ready - put controller in READY state
4332 * @ioc: per adapter object
4333 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4334 * @type: FORCE_BIG_HAMMER or SOFT_RESET
4335 *
4336 * Returns 0 for success, non-zero for failure.
4337 */
4338static int
4339_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
4340 enum reset_type type)
4341{
4342 u32 ioc_state;
4343 int rc;
4344 int count;
4345
4346 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4347 __func__));
4348
4349 if (ioc->pci_error_recovery)
4350 return 0;
4351
4352 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4353 dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4354 ioc->name, __func__, ioc_state));
4355
4356 /* if in RESET state, it should move to READY state shortly */
4357 count = 0;
4358 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
4359 while ((ioc_state & MPI2_IOC_STATE_MASK) !=
4360 MPI2_IOC_STATE_READY) {
4361 if (count++ == 10) {
4362 pr_err(MPT3SAS_FMT
4363 "%s: failed going to ready state (ioc_state=0x%x)\n",
4364 ioc->name, __func__, ioc_state);
4365 return -EFAULT;
4366 }
4367 if (sleep_flag == CAN_SLEEP)
4368 ssleep(1);
4369 else
4370 mdelay(1000);
4371 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4372 }
4373 }
4374
4375 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
4376 return 0;
4377
4378 if (ioc_state & MPI2_DOORBELL_USED) {
4379 dhsprintk(ioc, pr_info(MPT3SAS_FMT
4380 "unexpected doorbell active!\n",
4381 ioc->name));
4382 goto issue_diag_reset;
4383 }
4384
4385 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4386 mpt3sas_base_fault_info(ioc, ioc_state &
4387 MPI2_DOORBELL_DATA_MASK);
4388 goto issue_diag_reset;
4389 }
4390
4391 if (type == FORCE_BIG_HAMMER)
4392 goto issue_diag_reset;
4393
4394 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4395 if (!(_base_send_ioc_reset(ioc,
4396 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP))) {
4397 return 0;
4398 }
4399
4400 issue_diag_reset:
4401 rc = _base_diag_reset(ioc, CAN_SLEEP);
4402 return rc;
4403}
4404
4405/**
4406 * _base_make_ioc_operational - put controller in OPERATIONAL state
4407 * @ioc: per adapter object
4408 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4409 *
4410 * Returns 0 for success, non-zero for failure.
4411 */
4412static int
4413_base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4414{
4415 int r, i;
4416 unsigned long flags;
4417 u32 reply_address;
4418 u16 smid;
4419 struct _tr_list *delayed_tr, *delayed_tr_next;
4420 struct adapter_reply_queue *reply_q;
4421 long reply_post_free;
9b05c91a 4422 u32 reply_post_free_sz, index = 0;
f92363d1
SR		 4423
4424 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4425 __func__));
4426
4427 /* clean the delayed target reset list */
4428 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
4429 &ioc->delayed_tr_list, list) {
4430 list_del(&delayed_tr->list);
4431 kfree(delayed_tr);
4432 }
4433
4434
4435 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
4436 &ioc->delayed_tr_volume_list, list) {
4437 list_del(&delayed_tr->list);
4438 kfree(delayed_tr);
4439 }
4440
4441 /* initialize the scsi lookup free list */
4442 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
4443 INIT_LIST_HEAD(&ioc->free_list);
4444 smid = 1;
4445 for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
4446 INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
4447 ioc->scsi_lookup[i].cb_idx = 0xFF;
4448 ioc->scsi_lookup[i].smid = smid;
4449 ioc->scsi_lookup[i].scmd = NULL;
4450 list_add_tail(&ioc->scsi_lookup[i].tracker_list,
4451 &ioc->free_list);
4452 }
4453
4454 /* hi-priority queue */
4455 INIT_LIST_HEAD(&ioc->hpr_free_list);
4456 smid = ioc->hi_priority_smid;
4457 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
4458 ioc->hpr_lookup[i].cb_idx = 0xFF;
4459 ioc->hpr_lookup[i].smid = smid;
4460 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
4461 &ioc->hpr_free_list);
4462 }
4463
4464 /* internal queue */
4465 INIT_LIST_HEAD(&ioc->internal_free_list);
4466 smid = ioc->internal_smid;
4467 for (i = 0; i < ioc->internal_depth; i++, smid++) {
4468 ioc->internal_lookup[i].cb_idx = 0xFF;
4469 ioc->internal_lookup[i].smid = smid;
4470 list_add_tail(&ioc->internal_lookup[i].tracker_list,
4471 &ioc->internal_free_list);
4472 }
4473
4474 /* chain pool */
4475 INIT_LIST_HEAD(&ioc->free_chain_list);
4476 for (i = 0; i < ioc->chain_depth; i++)
4477 list_add_tail(&ioc->chain_lookup[i].tracker_list,
4478 &ioc->free_chain_list);
4479
4480 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
4481
4482 /* initialize Reply Free Queue */
4483 for (i = 0, reply_address = (u32)ioc->reply_dma ;
4484 i < ioc->reply_free_queue_depth ; i++, reply_address +=
4485 ioc->reply_sz)
4486 ioc->reply_free[i] = cpu_to_le32(reply_address);
4487
4488 /* initialize reply queues */
4489 if (ioc->is_driver_loading)
4490 _base_assign_reply_queues(ioc);
4491
4492 /* initialize Reply Post Free Queue */
f92363d1
SR		 4493 reply_post_free_sz = ioc->reply_post_queue_depth *
4494 sizeof(Mpi2DefaultReplyDescriptor_t);
9b05c91a 4495 reply_post_free = (long)ioc->reply_post[index].reply_post_free;
f92363d1
SR		 4496 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
4497 reply_q->reply_post_host_index = 0;
4498 reply_q->reply_post_free = (Mpi2ReplyDescriptorsUnion_t *)
4499 reply_post_free;
4500 for (i = 0; i < ioc->reply_post_queue_depth; i++)
4501 reply_q->reply_post_free[i].Words =
4502 cpu_to_le64(ULLONG_MAX);
4503 if (!_base_is_controller_msix_enabled(ioc))
4504 goto skip_init_reply_post_free_queue;
9b05c91a
SR		 4505 /*
4506 * If RDPQ is enabled, switch to the next allocation.
4507 * Otherwise advance within the contiguous region.
4508 */
4509 if (ioc->rdpq_array_enable)
4510 reply_post_free = (long)
4511 ioc->reply_post[++index].reply_post_free;
4512 else
4513 reply_post_free += reply_post_free_sz;
f92363d1
SR		 4514 }
4515 skip_init_reply_post_free_queue:
4516
4517 r = _base_send_ioc_init(ioc, sleep_flag);
4518 if (r)
4519 return r;
4520
4521 /* initialize reply free host index */
4522 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
4523 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
4524
4525 /* initialize reply post host index */
4526 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
4527 writel(reply_q->msix_index << MPI2_RPHI_MSIX_INDEX_SHIFT,
4528 &ioc->chip->ReplyPostHostIndex);
4529 if (!_base_is_controller_msix_enabled(ioc))
4530 goto skip_init_reply_post_host_index;
4531 }
4532
4533 skip_init_reply_post_host_index:
4534
4535 _base_unmask_interrupts(ioc);
4536 r = _base_event_notification(ioc, sleep_flag);
4537 if (r)
4538 return r;
4539
4540 if (sleep_flag == CAN_SLEEP)
4541 _base_static_config_pages(ioc);
4542
4543
4544 if (ioc->is_driver_loading) {
4545 ioc->wait_for_discovery_to_complete =
4546 _base_determine_wait_on_discovery(ioc);
4547
4548 return r; /* scan_start and scan_finished support */
4549 }
4550
4551 r = _base_send_port_enable(ioc, sleep_flag);
4552 if (r)
4553 return r;
4554
4555 return r;
4556}
4557
4558/**
4559 * mpt3sas_base_free_resources - free resources controller resources
4560 * @ioc: per adapter object
4561 *
4562 * Return nothing.
4563 */
4564void
4565mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
4566{
4567 struct pci_dev *pdev = ioc->pdev;
4568
4569 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4570 __func__));
4571
cf9bd21a
JL		 4572 if (ioc->chip_phys && ioc->chip) {
4573 _base_mask_interrupts(ioc);
4574 ioc->shost_recovery = 1;
4575 _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
4576 ioc->shost_recovery = 0;
4577 }
4578
f92363d1
SR		 4579 _base_free_irq(ioc);
4580 _base_disable_msix(ioc);
cf9bd21a
JL		 4581
4582 if (ioc->chip_phys && ioc->chip)
f92363d1
SR		 4583 iounmap(ioc->chip);
4584 ioc->chip_phys = 0;
cf9bd21a
JL		 4585
4586 if (pci_is_enabled(pdev)) {
4587 pci_release_selected_regions(ioc->pdev, ioc->bars);
4588 pci_disable_pcie_error_reporting(pdev);
4589 pci_disable_device(pdev);
4590 }
f92363d1
SR		 4591 return;
4592}
4593
4594/**
4595 * mpt3sas_base_attach - attach controller instance
4596 * @ioc: per adapter object
4597 *
4598 * Returns 0 for success, non-zero for failure.
4599 */
4600int
4601mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
4602{
4603 int r, i;
4604 int cpu_id, last_cpu_id = 0;
4605
4606 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4607 __func__));
4608
4609 /* setup cpu_msix_table */
4610 ioc->cpu_count = num_online_cpus();
4611 for_each_online_cpu(cpu_id)
4612 last_cpu_id = cpu_id;
4613 ioc->cpu_msix_table_sz = last_cpu_id + 1;
4614 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
4615 ioc->reply_queue_count = 1;
4616 if (!ioc->cpu_msix_table) {
4617 dfailprintk(ioc, pr_info(MPT3SAS_FMT
4618 "allocation for cpu_msix_table failed!!!\n",
4619 ioc->name));
4620 r = -ENOMEM;
4621 goto out_free_resources;
4622 }
4623
9b05c91a
SR		 4624 ioc->rdpq_array_enable_assigned = 0;
4625 ioc->dma_mask = 0;
f92363d1
SR		 4626 r = mpt3sas_base_map_resources(ioc);
4627 if (r)
4628 goto out_free_resources;
4629
4630
4631 pci_set_drvdata(ioc->pdev, ioc->shost);
4632 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
4633 if (r)
4634 goto out_free_resources;
4635
4636 /*
4637 * In SAS3.0,
4638 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
4639 * Target Status - all require the IEEE formated scatter gather
4640 * elements.
4641 */
4642
4643 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
4644 ioc->build_sg = &_base_build_sg_ieee;
4645 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
4646 ioc->mpi25 = 1;
4647 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
4648
4649 /*
4650 * These function pointers for other requests that don't
4651 * the require IEEE scatter gather elements.
4652 *
4653 * For example Configuration Pages and SAS IOUNIT Control don't.
4654 */
4655 ioc->build_sg_mpi = &_base_build_sg;
4656 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
4657
4658 r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
4659 if (r)
4660 goto out_free_resources;
4661
4662 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
4663 sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
4664 if (!ioc->pfacts) {
4665 r = -ENOMEM;
4666 goto out_free_resources;
4667 }
4668
4669 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
4670 r = _base_get_port_facts(ioc, i, CAN_SLEEP);
4671 if (r)
4672 goto out_free_resources;
4673 }
4674
4675 r = _base_allocate_memory_pools(ioc, CAN_SLEEP);
4676 if (r)
4677 goto out_free_resources;
4678
4679 init_waitqueue_head(&ioc->reset_wq);
4680
4681 /* allocate memory pd handle bitmask list */
4682 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
4683 if (ioc->facts.MaxDevHandle % 8)
4684 ioc->pd_handles_sz++;
4685 ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
4686 GFP_KERNEL);
4687 if (!ioc->pd_handles) {
4688 r = -ENOMEM;
4689 goto out_free_resources;
4690 }
4691 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
4692 GFP_KERNEL);
4693 if (!ioc->blocking_handles) {
4694 r = -ENOMEM;
4695 goto out_free_resources;
4696 }
4697
4698 ioc->fwfault_debug = mpt3sas_fwfault_debug;
4699
4700 /* base internal command bits */
4701 mutex_init(&ioc->base_cmds.mutex);
4702 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4703 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4704
4705 /* port_enable command bits */
4706 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4707 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
4708
4709 /* transport internal command bits */
4710 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4711 ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
4712 mutex_init(&ioc->transport_cmds.mutex);
4713
4714 /* scsih internal command bits */
4715 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4716 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
4717 mutex_init(&ioc->scsih_cmds.mutex);
4718
4719 /* task management internal command bits */
4720 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4721 ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
4722 mutex_init(&ioc->tm_cmds.mutex);
4723
4724 /* config page internal command bits */
4725 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4726 ioc->config_cmds.status = MPT3_CMD_NOT_USED;
4727 mutex_init(&ioc->config_cmds.mutex);
4728
4729 /* ctl module internal command bits */
4730 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4731 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
4732 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
4733 mutex_init(&ioc->ctl_cmds.mutex);
4734
4735 if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
4736 !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
4737 !ioc->config_cmds.reply || !ioc->ctl_cmds.reply ||
4738 !ioc->ctl_cmds.sense) {
4739 r = -ENOMEM;
4740 goto out_free_resources;
4741 }
4742
4743 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4744 ioc->event_masks[i] = -1;
4745
4746 /* here we enable the events we care about */
4747 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
4748 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
4749 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
4750 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
4751 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
4752 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
4753 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
4754 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
4755 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
4756 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
2d8ce8c9 4757 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
f92363d1
SR		 4758
4759 r = _base_make_ioc_operational(ioc, CAN_SLEEP);
4760 if (r)
4761 goto out_free_resources;
4762
4763 return 0;
4764
4765 out_free_resources:
4766
4767 ioc->remove_host = 1;
4768
4769 mpt3sas_base_free_resources(ioc);
4770 _base_release_memory_pools(ioc);
4771 pci_set_drvdata(ioc->pdev, NULL);
4772 kfree(ioc->cpu_msix_table);
4773 kfree(ioc->pd_handles);
4774 kfree(ioc->blocking_handles);
4775 kfree(ioc->tm_cmds.reply);
4776 kfree(ioc->transport_cmds.reply);
4777 kfree(ioc->scsih_cmds.reply);
4778 kfree(ioc->config_cmds.reply);
4779 kfree(ioc->base_cmds.reply);
4780 kfree(ioc->port_enable_cmds.reply);
4781 kfree(ioc->ctl_cmds.reply);
4782 kfree(ioc->ctl_cmds.sense);
4783 kfree(ioc->pfacts);
4784 ioc->ctl_cmds.reply = NULL;
4785 ioc->base_cmds.reply = NULL;
4786 ioc->tm_cmds.reply = NULL;
4787 ioc->scsih_cmds.reply = NULL;
4788 ioc->transport_cmds.reply = NULL;
4789 ioc->config_cmds.reply = NULL;
4790 ioc->pfacts = NULL;
4791 return r;
4792}
4793
4794
4795/**
4796 * mpt3sas_base_detach - remove controller instance
4797 * @ioc: per adapter object
4798 *
4799 * Return nothing.
4800 */
4801void
4802mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
4803{
4804 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4805 __func__));
4806
4807 mpt3sas_base_stop_watchdog(ioc);
4808 mpt3sas_base_free_resources(ioc);
4809 _base_release_memory_pools(ioc);
4810 pci_set_drvdata(ioc->pdev, NULL);
4811 kfree(ioc->cpu_msix_table);
4812 kfree(ioc->pd_handles);
4813 kfree(ioc->blocking_handles);
4814 kfree(ioc->pfacts);
4815 kfree(ioc->ctl_cmds.reply);
4816 kfree(ioc->ctl_cmds.sense);
4817 kfree(ioc->base_cmds.reply);
4818 kfree(ioc->port_enable_cmds.reply);
4819 kfree(ioc->tm_cmds.reply);
4820 kfree(ioc->transport_cmds.reply);
4821 kfree(ioc->scsih_cmds.reply);
4822 kfree(ioc->config_cmds.reply);
4823}
4824
4825/**
4826 * _base_reset_handler - reset callback handler (for base)
4827 * @ioc: per adapter object
4828 * @reset_phase: phase
4829 *
4830 * The handler for doing any required cleanup or initialization.
4831 *
4832 * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET,
4833 * MPT3_IOC_DONE_RESET
4834 *
4835 * Return nothing.
4836 */
4837static void
4838_base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase)
4839{
4840 mpt3sas_scsih_reset_handler(ioc, reset_phase);
4841 mpt3sas_ctl_reset_handler(ioc, reset_phase);
4842 switch (reset_phase) {
4843 case MPT3_IOC_PRE_RESET:
4844 dtmprintk(ioc, pr_info(MPT3SAS_FMT
4845 "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
4846 break;
4847 case MPT3_IOC_AFTER_RESET:
4848 dtmprintk(ioc, pr_info(MPT3SAS_FMT
4849 "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
4850 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
4851 ioc->transport_cmds.status |= MPT3_CMD_RESET;
4852 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
4853 complete(&ioc->transport_cmds.done);
4854 }
4855 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4856 ioc->base_cmds.status |= MPT3_CMD_RESET;
4857 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
4858 complete(&ioc->base_cmds.done);
4859 }
4860 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4861 ioc->port_enable_failed = 1;
4862 ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
4863 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
4864 if (ioc->is_driver_loading) {
4865 ioc->start_scan_failed =
4866 MPI2_IOCSTATUS_INTERNAL_ERROR;
4867 ioc->start_scan = 0;
4868 ioc->port_enable_cmds.status =
4869 MPT3_CMD_NOT_USED;
4870 } else
4871 complete(&ioc->port_enable_cmds.done);
4872 }
4873 if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
4874 ioc->config_cmds.status |= MPT3_CMD_RESET;
4875 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
4876 ioc->config_cmds.smid = USHRT_MAX;
4877 complete(&ioc->config_cmds.done);
4878 }
4879 break;
4880 case MPT3_IOC_DONE_RESET:
4881 dtmprintk(ioc, pr_info(MPT3SAS_FMT
4882 "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
4883 break;
4884 }
4885}
4886
4887/**
4888 * _wait_for_commands_to_complete - reset controller
4889 * @ioc: Pointer to MPT_ADAPTER structure
4890 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4891 *
4892 * This function waiting(3s) for all pending commands to complete
4893 * prior to putting controller in reset.
4894 */
4895static void
4896_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4897{
4898 u32 ioc_state;
4899 unsigned long flags;
4900 u16 i;
4901
4902 ioc->pending_io_count = 0;
4903 if (sleep_flag != CAN_SLEEP)
4904 return;
4905
4906 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4907 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
4908 return;
4909
4910 /* pending command count */
4911 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
4912 for (i = 0; i < ioc->scsiio_depth; i++)
4913 if (ioc->scsi_lookup[i].cb_idx != 0xFF)
4914 ioc->pending_io_count++;
4915 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
4916
4917 if (!ioc->pending_io_count)
4918 return;
4919
4920 /* wait for pending commands to complete */
4921 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
4922}
4923
4924/**
4925 * mpt3sas_base_hard_reset_handler - reset controller
4926 * @ioc: Pointer to MPT_ADAPTER structure
4927 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4928 * @type: FORCE_BIG_HAMMER or SOFT_RESET
4929 *
4930 * Returns 0 for success, non-zero for failure.
4931 */
4932int
4933mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
4934 enum reset_type type)
4935{
4936 int r;
4937 unsigned long flags;
4938 u32 ioc_state;
4939 u8 is_fault = 0, is_trigger = 0;
4940
4941 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
4942 __func__));
4943
4944 if (ioc->pci_error_recovery) {
4945 pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
4946 ioc->name, __func__);
4947 r = 0;
4948 goto out_unlocked;
4949 }
4950
4951 if (mpt3sas_fwfault_debug)
4952 mpt3sas_halt_firmware(ioc);
4953
4954 /* TODO - What we really should be doing is pulling
4955 * out all the code associated with NO_SLEEP; its never used.
4956 * That is legacy code from mpt fusion driver, ported over.
4957 * I will leave this BUG_ON here for now till its been resolved.
4958 */
4959 BUG_ON(sleep_flag == NO_SLEEP);
4960
4961 /* wait for an active reset in progress to complete */
4962 if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
4963 do {
4964 ssleep(1);
4965 } while (ioc->shost_recovery == 1);
4966 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
4967 __func__));
4968 return ioc->ioc_reset_in_progress_status;
4969 }
4970
4971 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
4972 ioc->shost_recovery = 1;
4973 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
4974
4975 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
4976 MPT3_DIAG_BUFFER_IS_REGISTERED) &&
4977 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
4978 MPT3_DIAG_BUFFER_IS_RELEASED))) {
4979 is_trigger = 1;
4980 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4981 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
4982 is_fault = 1;
4983 }
4984 _base_reset_handler(ioc, MPT3_IOC_PRE_RESET);
4985 _wait_for_commands_to_complete(ioc, sleep_flag);
4986 _base_mask_interrupts(ioc);
4987 r = _base_make_ioc_ready(ioc, sleep_flag, type);
4988 if (r)
4989 goto out;
4990 _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET);
4991
4992 /* If this hard reset is called while port enable is active, then
4993 * there is no reason to call make_ioc_operational
4994 */
4995 if (ioc->is_driver_loading && ioc->port_enable_failed) {
4996 ioc->remove_host = 1;
4997 r = -EFAULT;
4998 goto out;
4999 }
5000 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
5001 if (r)
5002 goto out;
9b05c91a
SR		 5003
5004 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
5005 panic("%s: Issue occurred with flashing controller firmware."
5006 "Please reboot the system and ensure that the correct"
5007 " firmware version is running\n", ioc->name);
5008
f92363d1
SR		 5009 r = _base_make_ioc_operational(ioc, sleep_flag);
5010 if (!r)
5011 _base_reset_handler(ioc, MPT3_IOC_DONE_RESET);
5012
5013 out:
5014 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
5015 ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
5016
5017 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5018 ioc->ioc_reset_in_progress_status = r;
5019 ioc->shost_recovery = 0;
5020 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5021 ioc->ioc_reset_count++;
5022 mutex_unlock(&ioc->reset_in_progress_mutex);
5023
5024 out_unlocked:
5025 if ((r == 0) && is_trigger) {
5026 if (is_fault)
5027 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
5028 else
5029 mpt3sas_trigger_master(ioc,
5030 MASTER_TRIGGER_ADAPTER_RESET);
5031 }
5032 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5033 __func__));
5034 return r;
5035}
Linux 6.x block layer and io_uring tree(s)