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mpt3sas: Added OEM Gen2 PnP ID branding names
[linux-2.6-block.git] / drivers / scsi / mpt3sas / mpt3sas_base.c
CommitLineData
f92363d1
SR		 1/*
2 * This is the Fusion MPT base driver providing common API layer interface
3 * for access to MPT (Message Passing Technology) firmware.
4 *
5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
a4ffce0d 6 * Copyright (C) 2012-2014 LSI Corporation
a03bd153
SR		 7 * Copyright (C) 2013-2014 Avago Technologies
8 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
f92363d1
SR		 9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * NO WARRANTY
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25 * solely responsible for determining the appropriateness of using and
26 * distributing the Program and assumes all risks associated with its
27 * exercise of rights under this Agreement, including but not limited to
28 * the risks and costs of program errors, damage to or loss of data,
29 * programs or equipment, and unavailability or interruption of operations.
30
31 * DISCLAIMER OF LIABILITY
32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
43 * USA.
44 */
45
f92363d1
SR		 46#include <linux/kernel.h>
47#include <linux/module.h>
48#include <linux/errno.h>
49#include <linux/init.h>
50#include <linux/slab.h>
51#include <linux/types.h>
52#include <linux/pci.h>
53#include <linux/kdev_t.h>
54#include <linux/blkdev.h>
55#include <linux/delay.h>
56#include <linux/interrupt.h>
57#include <linux/dma-mapping.h>
58#include <linux/io.h>
59#include <linux/time.h>
60#include <linux/kthread.h>
61#include <linux/aer.h>
62
63
64#include "mpt3sas_base.h"
65
66static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
67
68
69#define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
70
71 /* maximum controller queue depth */
72#define MAX_HBA_QUEUE_DEPTH 30000
73#define MAX_CHAIN_DEPTH 100000
74static int max_queue_depth = -1;
75module_param(max_queue_depth, int, 0);
76MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
77
78static int max_sgl_entries = -1;
79module_param(max_sgl_entries, int, 0);
80MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
81
82static int msix_disable = -1;
83module_param(msix_disable, int, 0);
84MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
85
fb77bb53 86static int max_msix_vectors = -1;
9c500060
SR		 87module_param(max_msix_vectors, int, 0);
88MODULE_PARM_DESC(max_msix_vectors,
fb77bb53 89 " max msix vectors");
f92363d1
SR		 90
91static int mpt3sas_fwfault_debug;
92MODULE_PARM_DESC(mpt3sas_fwfault_debug,
93 " enable detection of firmware fault and halt firmware - (default=0)");
94
9b05c91a
SR		 95static int
96_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag);
f92363d1
SR		 97
98/**
99 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
100 *
101 */
102static int
103_scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
104{
105 int ret = param_set_int(val, kp);
106 struct MPT3SAS_ADAPTER *ioc;
107
108 if (ret)
109 return ret;
110
111 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
112 list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
113 ioc->fwfault_debug = mpt3sas_fwfault_debug;
114 return 0;
115}
116module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
117 param_get_int, &mpt3sas_fwfault_debug, 0644);
118
119/**
120 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
121 * @arg: input argument, used to derive ioc
122 *
123 * Return 0 if controller is removed from pci subsystem.
124 * Return -1 for other case.
125 */
126static int mpt3sas_remove_dead_ioc_func(void *arg)
127{
128 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
129 struct pci_dev *pdev;
130
131 if ((ioc == NULL))
132 return -1;
133
134 pdev = ioc->pdev;
135 if ((pdev == NULL))
136 return -1;
64cdb418 137 pci_stop_and_remove_bus_device_locked(pdev);
f92363d1
SR		 138 return 0;
139}
140
141/**
142 * _base_fault_reset_work - workq handling ioc fault conditions
143 * @work: input argument, used to derive ioc
144 * Context: sleep.
145 *
146 * Return nothing.
147 */
148static void
149_base_fault_reset_work(struct work_struct *work)
150{
151 struct MPT3SAS_ADAPTER *ioc =
152 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
153 unsigned long flags;
154 u32 doorbell;
155 int rc;
156 struct task_struct *p;
157
158
159 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
16e179bd 160 if (ioc->shost_recovery || ioc->pci_error_recovery)
f92363d1
SR		 161 goto rearm_timer;
162 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
163
164 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
165 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
166 pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
167 ioc->name);
168
16e179bd
SR		 169 /* It may be possible that EEH recovery can resolve some of
170 * pci bus failure issues rather removing the dead ioc function
171 * by considering controller is in a non-operational state. So
172 * here priority is given to the EEH recovery. If it doesn't
173 * not resolve this issue, mpt3sas driver will consider this
174 * controller to non-operational state and remove the dead ioc
175 * function.
176 */
177 if (ioc->non_operational_loop++ < 5) {
178 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
179 flags);
180 goto rearm_timer;
181 }
182
f92363d1
SR		 183 /*
184 * Call _scsih_flush_pending_cmds callback so that we flush all
185 * pending commands back to OS. This call is required to aovid
186 * deadlock at block layer. Dead IOC will fail to do diag reset,
187 * and this call is safe since dead ioc will never return any
188 * command back from HW.
189 */
190 ioc->schedule_dead_ioc_flush_running_cmds(ioc);
191 /*
192 * Set remove_host flag early since kernel thread will
193 * take some time to execute.
194 */
195 ioc->remove_host = 1;
196 /*Remove the Dead Host */
197 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
198 "mpt3sas_dead_ioc_%d", ioc->id);
199 if (IS_ERR(p))
200 pr_err(MPT3SAS_FMT
201 "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
202 ioc->name, __func__);
203 else
204 pr_err(MPT3SAS_FMT
205 "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
206 ioc->name, __func__);
207 return; /* don't rearm timer */
208 }
209
16e179bd
SR		 210 ioc->non_operational_loop = 0;
211
f92363d1
SR		 212 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
213 rc = mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
214 FORCE_BIG_HAMMER);
215 pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
216 __func__, (rc == 0) ? "success" : "failed");
217 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
218 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
219 mpt3sas_base_fault_info(ioc, doorbell &
220 MPI2_DOORBELL_DATA_MASK);
221 if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
222 MPI2_IOC_STATE_OPERATIONAL)
223 return; /* don't rearm timer */
224 }
225
226 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
227 rearm_timer:
228 if (ioc->fault_reset_work_q)
229 queue_delayed_work(ioc->fault_reset_work_q,
230 &ioc->fault_reset_work,
231 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
232 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
233}
234
235/**
236 * mpt3sas_base_start_watchdog - start the fault_reset_work_q
237 * @ioc: per adapter object
238 * Context: sleep.
239 *
240 * Return nothing.
241 */
242void
243mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
244{
245 unsigned long flags;
246
247 if (ioc->fault_reset_work_q)
248 return;
249
250 /* initialize fault polling */
251
252 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
253 snprintf(ioc->fault_reset_work_q_name,
254 sizeof(ioc->fault_reset_work_q_name), "poll_%d_status", ioc->id);
255 ioc->fault_reset_work_q =
256 create_singlethread_workqueue(ioc->fault_reset_work_q_name);
257 if (!ioc->fault_reset_work_q) {
258 pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
259 ioc->name, __func__, __LINE__);
260 return;
261 }
262 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
263 if (ioc->fault_reset_work_q)
264 queue_delayed_work(ioc->fault_reset_work_q,
265 &ioc->fault_reset_work,
266 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
267 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
268}
269
270/**
271 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
272 * @ioc: per adapter object
273 * Context: sleep.
274 *
275 * Return nothing.
276 */
277void
278mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
279{
280 unsigned long flags;
281 struct workqueue_struct *wq;
282
283 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
284 wq = ioc->fault_reset_work_q;
285 ioc->fault_reset_work_q = NULL;
286 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
287 if (wq) {
4dc06fd8 288 if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
f92363d1
SR		 289 flush_workqueue(wq);
290 destroy_workqueue(wq);
291 }
292}
293
294/**
295 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
296 * @ioc: per adapter object
297 * @fault_code: fault code
298 *
299 * Return nothing.
300 */
301void
302mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
303{
304 pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
305 ioc->name, fault_code);
306}
307
308/**
309 * mpt3sas_halt_firmware - halt's mpt controller firmware
310 * @ioc: per adapter object
311 *
312 * For debugging timeout related issues. Writing 0xCOFFEE00
313 * to the doorbell register will halt controller firmware. With
314 * the purpose to stop both driver and firmware, the enduser can
315 * obtain a ring buffer from controller UART.
316 */
317void
318mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
319{
320 u32 doorbell;
321
322 if (!ioc->fwfault_debug)
323 return;
324
325 dump_stack();
326
327 doorbell = readl(&ioc->chip->Doorbell);
328 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
329 mpt3sas_base_fault_info(ioc , doorbell);
330 else {
331 writel(0xC0FFEE00, &ioc->chip->Doorbell);
332 pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
333 ioc->name);
334 }
335
336 if (ioc->fwfault_debug == 2)
337 for (;;)
338 ;
339 else
340 panic("panic in %s\n", __func__);
341}
342
f92363d1
SR		 343/**
344 * _base_sas_ioc_info - verbose translation of the ioc status
345 * @ioc: per adapter object
346 * @mpi_reply: reply mf payload returned from firmware
347 * @request_hdr: request mf
348 *
349 * Return nothing.
350 */
351static void
352_base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
353 MPI2RequestHeader_t *request_hdr)
354{
355 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
356 MPI2_IOCSTATUS_MASK;
357 char *desc = NULL;
358 u16 frame_sz;
359 char *func_str = NULL;
360
361 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
362 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
363 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
364 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
365 return;
366
367 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
368 return;
369
370 switch (ioc_status) {
371
372/****************************************************************************
373* Common IOCStatus values for all replies
374****************************************************************************/
375
376 case MPI2_IOCSTATUS_INVALID_FUNCTION:
377 desc = "invalid function";
378 break;
379 case MPI2_IOCSTATUS_BUSY:
380 desc = "busy";
381 break;
382 case MPI2_IOCSTATUS_INVALID_SGL:
383 desc = "invalid sgl";
384 break;
385 case MPI2_IOCSTATUS_INTERNAL_ERROR:
386 desc = "internal error";
387 break;
388 case MPI2_IOCSTATUS_INVALID_VPID:
389 desc = "invalid vpid";
390 break;
391 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
392 desc = "insufficient resources";
393 break;
394 case MPI2_IOCSTATUS_INVALID_FIELD:
395 desc = "invalid field";
396 break;
397 case MPI2_IOCSTATUS_INVALID_STATE:
398 desc = "invalid state";
399 break;
400 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
401 desc = "op state not supported";
402 break;
403
404/****************************************************************************
405* Config IOCStatus values
406****************************************************************************/
407
408 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
409 desc = "config invalid action";
410 break;
411 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
412 desc = "config invalid type";
413 break;
414 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
415 desc = "config invalid page";
416 break;
417 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
418 desc = "config invalid data";
419 break;
420 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
421 desc = "config no defaults";
422 break;
423 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
424 desc = "config cant commit";
425 break;
426
427/****************************************************************************
428* SCSI IO Reply
429****************************************************************************/
430
431 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
432 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
433 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
434 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
435 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
436 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
437 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
438 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
439 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
440 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
441 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
442 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
443 break;
444
445/****************************************************************************
446* For use by SCSI Initiator and SCSI Target end-to-end data protection
447****************************************************************************/
448
449 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
450 desc = "eedp guard error";
451 break;
452 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
453 desc = "eedp ref tag error";
454 break;
455 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
456 desc = "eedp app tag error";
457 break;
458
459/****************************************************************************
460* SCSI Target values
461****************************************************************************/
462
463 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
464 desc = "target invalid io index";
465 break;
466 case MPI2_IOCSTATUS_TARGET_ABORTED:
467 desc = "target aborted";
468 break;
469 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
470 desc = "target no conn retryable";
471 break;
472 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
473 desc = "target no connection";
474 break;
475 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
476 desc = "target xfer count mismatch";
477 break;
478 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
479 desc = "target data offset error";
480 break;
481 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
482 desc = "target too much write data";
483 break;
484 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
485 desc = "target iu too short";
486 break;
487 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
488 desc = "target ack nak timeout";
489 break;
490 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
491 desc = "target nak received";
492 break;
493
494/****************************************************************************
495* Serial Attached SCSI values
496****************************************************************************/
497
498 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
499 desc = "smp request failed";
500 break;
501 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
502 desc = "smp data overrun";
503 break;
504
505/****************************************************************************
506* Diagnostic Buffer Post / Diagnostic Release values
507****************************************************************************/
508
509 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
510 desc = "diagnostic released";
511 break;
512 default:
513 break;
514 }
515
516 if (!desc)
517 return;
518
519 switch (request_hdr->Function) {
520 case MPI2_FUNCTION_CONFIG:
521 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
522 func_str = "config_page";
523 break;
524 case MPI2_FUNCTION_SCSI_TASK_MGMT:
525 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
526 func_str = "task_mgmt";
527 break;
528 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
529 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
530 func_str = "sas_iounit_ctl";
531 break;
532 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
533 frame_sz = sizeof(Mpi2SepRequest_t);
534 func_str = "enclosure";
535 break;
536 case MPI2_FUNCTION_IOC_INIT:
537 frame_sz = sizeof(Mpi2IOCInitRequest_t);
538 func_str = "ioc_init";
539 break;
540 case MPI2_FUNCTION_PORT_ENABLE:
541 frame_sz = sizeof(Mpi2PortEnableRequest_t);
542 func_str = "port_enable";
543 break;
544 case MPI2_FUNCTION_SMP_PASSTHROUGH:
545 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
546 func_str = "smp_passthru";
547 break;
548 default:
549 frame_sz = 32;
550 func_str = "unknown";
551 break;
552 }
553
554 pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
555 ioc->name, desc, ioc_status, request_hdr, func_str);
556
557 _debug_dump_mf(request_hdr, frame_sz/4);
558}
559
560/**
561 * _base_display_event_data - verbose translation of firmware asyn events
562 * @ioc: per adapter object
563 * @mpi_reply: reply mf payload returned from firmware
564 *
565 * Return nothing.
566 */
567static void
568_base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
569 Mpi2EventNotificationReply_t *mpi_reply)
570{
571 char *desc = NULL;
572 u16 event;
573
574 if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
575 return;
576
577 event = le16_to_cpu(mpi_reply->Event);
578
579 switch (event) {
580 case MPI2_EVENT_LOG_DATA:
581 desc = "Log Data";
582 break;
583 case MPI2_EVENT_STATE_CHANGE:
584 desc = "Status Change";
585 break;
586 case MPI2_EVENT_HARD_RESET_RECEIVED:
587 desc = "Hard Reset Received";
588 break;
589 case MPI2_EVENT_EVENT_CHANGE:
590 desc = "Event Change";
591 break;
592 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
593 desc = "Device Status Change";
594 break;
595 case MPI2_EVENT_IR_OPERATION_STATUS:
7786ab6a
SR		 596 if (!ioc->hide_ir_msg)
597 desc = "IR Operation Status";
f92363d1
SR		 598 break;
599 case MPI2_EVENT_SAS_DISCOVERY:
600 {
601 Mpi2EventDataSasDiscovery_t *event_data =
602 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
603 pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
604 (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
605 "start" : "stop");
606 if (event_data->DiscoveryStatus)
607 pr_info("discovery_status(0x%08x)",
608 le32_to_cpu(event_data->DiscoveryStatus));
609 pr_info("\n");
610 return;
611 }
612 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
613 desc = "SAS Broadcast Primitive";
614 break;
615 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
616 desc = "SAS Init Device Status Change";
617 break;
618 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
619 desc = "SAS Init Table Overflow";
620 break;
621 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
622 desc = "SAS Topology Change List";
623 break;
624 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
625 desc = "SAS Enclosure Device Status Change";
626 break;
627 case MPI2_EVENT_IR_VOLUME:
7786ab6a
SR		 628 if (!ioc->hide_ir_msg)
629 desc = "IR Volume";
f92363d1
SR		 630 break;
631 case MPI2_EVENT_IR_PHYSICAL_DISK:
7786ab6a
SR		 632 if (!ioc->hide_ir_msg)
633 desc = "IR Physical Disk";
f92363d1
SR		 634 break;
635 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7786ab6a
SR		 636 if (!ioc->hide_ir_msg)
637 desc = "IR Configuration Change List";
f92363d1
SR		 638 break;
639 case MPI2_EVENT_LOG_ENTRY_ADDED:
7786ab6a
SR		 640 if (!ioc->hide_ir_msg)
641 desc = "Log Entry Added";
f92363d1 642 break;
2d8ce8c9
SR		 643 case MPI2_EVENT_TEMP_THRESHOLD:
644 desc = "Temperature Threshold";
645 break;
f92363d1
SR		 646 }
647
648 if (!desc)
649 return;
650
651 pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
652}
f92363d1
SR		 653
654/**
655 * _base_sas_log_info - verbose translation of firmware log info
656 * @ioc: per adapter object
657 * @log_info: log info
658 *
659 * Return nothing.
660 */
661static void
662_base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
663{
664 union loginfo_type {
665 u32 loginfo;
666 struct {
667 u32 subcode:16;
668 u32 code:8;
669 u32 originator:4;
670 u32 bus_type:4;
671 } dw;
672 };
673 union loginfo_type sas_loginfo;
674 char *originator_str = NULL;
675
676 sas_loginfo.loginfo = log_info;
677 if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
678 return;
679
680 /* each nexus loss loginfo */
681 if (log_info == 0x31170000)
682 return;
683
684 /* eat the loginfos associated with task aborts */
685 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
686 0x31140000 || log_info == 0x31130000))
687 return;
688
689 switch (sas_loginfo.dw.originator) {
690 case 0:
691 originator_str = "IOP";
692 break;
693 case 1:
694 originator_str = "PL";
695 break;
696 case 2:
7786ab6a
SR		 697 if (!ioc->hide_ir_msg)
698 originator_str = "IR";
699 else
700 originator_str = "WarpDrive";
f92363d1
SR		 701 break;
702 }
703
704 pr_warn(MPT3SAS_FMT
705 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
706 ioc->name, log_info,
707 originator_str, sas_loginfo.dw.code,
708 sas_loginfo.dw.subcode);
709}
710
711/**
712 * _base_display_reply_info -
713 * @ioc: per adapter object
714 * @smid: system request message index
715 * @msix_index: MSIX table index supplied by the OS
716 * @reply: reply message frame(lower 32bit addr)
717 *
718 * Return nothing.
719 */
720static void
721_base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
722 u32 reply)
723{
724 MPI2DefaultReply_t *mpi_reply;
725 u16 ioc_status;
726 u32 loginfo = 0;
727
728 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
729 if (unlikely(!mpi_reply)) {
730 pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
731 ioc->name, __FILE__, __LINE__, __func__);
732 return;
733 }
734 ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
af009411 735
f92363d1
SR		 736 if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
737 (ioc->logging_level & MPT_DEBUG_REPLY)) {
738 _base_sas_ioc_info(ioc , mpi_reply,
739 mpt3sas_base_get_msg_frame(ioc, smid));
740 }
af009411 741
f92363d1
SR		 742 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
743 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
744 _base_sas_log_info(ioc, loginfo);
745 }
746
747 if (ioc_status || loginfo) {
748 ioc_status &= MPI2_IOCSTATUS_MASK;
749 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
750 }
751}
752
753/**
754 * mpt3sas_base_done - base internal command completion routine
755 * @ioc: per adapter object
756 * @smid: system request message index
757 * @msix_index: MSIX table index supplied by the OS
758 * @reply: reply message frame(lower 32bit addr)
759 *
760 * Return 1 meaning mf should be freed from _base_interrupt
761 * 0 means the mf is freed from this function.
762 */
763u8
764mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
765 u32 reply)
766{
767 MPI2DefaultReply_t *mpi_reply;
768
769 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
770 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
771 return 1;
772
773 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
774 return 1;
775
776 ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
777 if (mpi_reply) {
778 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
779 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
780 }
781 ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
782
783 complete(&ioc->base_cmds.done);
784 return 1;
785}
786
787/**
788 * _base_async_event - main callback handler for firmware asyn events
789 * @ioc: per adapter object
790 * @msix_index: MSIX table index supplied by the OS
791 * @reply: reply message frame(lower 32bit addr)
792 *
793 * Return 1 meaning mf should be freed from _base_interrupt
794 * 0 means the mf is freed from this function.
795 */
796static u8
797_base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
798{
799 Mpi2EventNotificationReply_t *mpi_reply;
800 Mpi2EventAckRequest_t *ack_request;
801 u16 smid;
802
803 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
804 if (!mpi_reply)
805 return 1;
806 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
807 return 1;
af009411 808
f92363d1 809 _base_display_event_data(ioc, mpi_reply);
af009411 810
f92363d1
SR		 811 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
812 goto out;
813 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
814 if (!smid) {
815 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
816 ioc->name, __func__);
817 goto out;
818 }
819
820 ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
821 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
822 ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
823 ack_request->Event = mpi_reply->Event;
824 ack_request->EventContext = mpi_reply->EventContext;
825 ack_request->VF_ID = 0; /* TODO */
826 ack_request->VP_ID = 0;
827 mpt3sas_base_put_smid_default(ioc, smid);
828
829 out:
830
831 /* scsih callback handler */
832 mpt3sas_scsih_event_callback(ioc, msix_index, reply);
833
834 /* ctl callback handler */
835 mpt3sas_ctl_event_callback(ioc, msix_index, reply);
836
837 return 1;
838}
839
840/**
841 * _base_get_cb_idx - obtain the callback index
842 * @ioc: per adapter object
843 * @smid: system request message index
844 *
845 * Return callback index.
846 */
847static u8
848_base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
849{
850 int i;
851 u8 cb_idx;
852
853 if (smid < ioc->hi_priority_smid) {
854 i = smid - 1;
855 cb_idx = ioc->scsi_lookup[i].cb_idx;
856 } else if (smid < ioc->internal_smid) {
857 i = smid - ioc->hi_priority_smid;
858 cb_idx = ioc->hpr_lookup[i].cb_idx;
859 } else if (smid <= ioc->hba_queue_depth) {
860 i = smid - ioc->internal_smid;
861 cb_idx = ioc->internal_lookup[i].cb_idx;
862 } else
863 cb_idx = 0xFF;
864 return cb_idx;
865}
866
867/**
868 * _base_mask_interrupts - disable interrupts
869 * @ioc: per adapter object
870 *
871 * Disabling ResetIRQ, Reply and Doorbell Interrupts
872 *
873 * Return nothing.
874 */
875static void
876_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
877{
878 u32 him_register;
879
880 ioc->mask_interrupts = 1;
881 him_register = readl(&ioc->chip->HostInterruptMask);
882 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
883 writel(him_register, &ioc->chip->HostInterruptMask);
884 readl(&ioc->chip->HostInterruptMask);
885}
886
887/**
888 * _base_unmask_interrupts - enable interrupts
889 * @ioc: per adapter object
890 *
891 * Enabling only Reply Interrupts
892 *
893 * Return nothing.
894 */
895static void
896_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
897{
898 u32 him_register;
899
900 him_register = readl(&ioc->chip->HostInterruptMask);
901 him_register &= ~MPI2_HIM_RIM;
902 writel(him_register, &ioc->chip->HostInterruptMask);
903 ioc->mask_interrupts = 0;
904}
905
906union reply_descriptor {
907 u64 word;
908 struct {
909 u32 low;
910 u32 high;
911 } u;
912};
913
914/**
915 * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
916 * @irq: irq number (not used)
917 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
918 * @r: pt_regs pointer (not used)
919 *
920 * Return IRQ_HANDLE if processed, else IRQ_NONE.
921 */
922static irqreturn_t
923_base_interrupt(int irq, void *bus_id)
924{
925 struct adapter_reply_queue *reply_q = bus_id;
926 union reply_descriptor rd;
927 u32 completed_cmds;
928 u8 request_desript_type;
929 u16 smid;
930 u8 cb_idx;
931 u32 reply;
932 u8 msix_index = reply_q->msix_index;
933 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
934 Mpi2ReplyDescriptorsUnion_t *rpf;
935 u8 rc;
936
937 if (ioc->mask_interrupts)
938 return IRQ_NONE;
939
940 if (!atomic_add_unless(&reply_q->busy, 1, 1))
941 return IRQ_NONE;
942
943 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
944 request_desript_type = rpf->Default.ReplyFlags
945 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
946 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
947 atomic_dec(&reply_q->busy);
948 return IRQ_NONE;
949 }
950
951 completed_cmds = 0;
952 cb_idx = 0xFF;
953 do {
954 rd.word = le64_to_cpu(rpf->Words);
955 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
956 goto out;
957 reply = 0;
958 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
959 if (request_desript_type ==
960 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
961 request_desript_type ==
962 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
963 cb_idx = _base_get_cb_idx(ioc, smid);
964 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
965 (likely(mpt_callbacks[cb_idx] != NULL))) {
966 rc = mpt_callbacks[cb_idx](ioc, smid,
967 msix_index, 0);
968 if (rc)
969 mpt3sas_base_free_smid(ioc, smid);
970 }
971 } else if (request_desript_type ==
972 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
973 reply = le32_to_cpu(
974 rpf->AddressReply.ReplyFrameAddress);
975 if (reply > ioc->reply_dma_max_address ||
976 reply < ioc->reply_dma_min_address)
977 reply = 0;
978 if (smid) {
979 cb_idx = _base_get_cb_idx(ioc, smid);
980 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
981 (likely(mpt_callbacks[cb_idx] != NULL))) {
982 rc = mpt_callbacks[cb_idx](ioc, smid,
983 msix_index, reply);
984 if (reply)
985 _base_display_reply_info(ioc,
986 smid, msix_index, reply);
987 if (rc)
988 mpt3sas_base_free_smid(ioc,
989 smid);
990 }
991 } else {
992 _base_async_event(ioc, msix_index, reply);
993 }
994
995 /* reply free queue handling */
996 if (reply) {
997 ioc->reply_free_host_index =
998 (ioc->reply_free_host_index ==
999 (ioc->reply_free_queue_depth - 1)) ?
1000 0 : ioc->reply_free_host_index + 1;
1001 ioc->reply_free[ioc->reply_free_host_index] =
1002 cpu_to_le32(reply);
1003 wmb();
1004 writel(ioc->reply_free_host_index,
1005 &ioc->chip->ReplyFreeHostIndex);
1006 }
1007 }
1008
1009 rpf->Words = cpu_to_le64(ULLONG_MAX);
1010 reply_q->reply_post_host_index =
1011 (reply_q->reply_post_host_index ==
1012 (ioc->reply_post_queue_depth - 1)) ? 0 :
1013 reply_q->reply_post_host_index + 1;
1014 request_desript_type =
1015 reply_q->reply_post_free[reply_q->reply_post_host_index].
1016 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1017 completed_cmds++;
1018 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1019 goto out;
1020 if (!reply_q->reply_post_host_index)
1021 rpf = reply_q->reply_post_free;
1022 else
1023 rpf++;
1024 } while (1);
1025
1026 out:
1027
1028 if (!completed_cmds) {
1029 atomic_dec(&reply_q->busy);
1030 return IRQ_NONE;
1031 }
1032
1033 wmb();
7786ab6a
SR		 1034 if (ioc->is_warpdrive) {
1035 writel(reply_q->reply_post_host_index,
1036 ioc->reply_post_host_index[msix_index]);
1037 atomic_dec(&reply_q->busy);
1038 return IRQ_HANDLED;
1039 }
fb77bb53
SR		 1040
1041 /* Update Reply Post Host Index.
1042 * For those HBA's which support combined reply queue feature
1043 * 1. Get the correct Supplemental Reply Post Host Index Register.
1044 * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1045 * Index Register address bank i.e replyPostRegisterIndex[],
1046 * 2. Then update this register with new reply host index value
1047 * in ReplyPostIndex field and the MSIxIndex field with
1048 * msix_index value reduced to a value between 0 and 7,
1049 * using a modulo 8 operation. Since each Supplemental Reply Post
1050 * Host Index Register supports 8 MSI-X vectors.
1051 *
1052 * For other HBA's just update the Reply Post Host Index register with
1053 * new reply host index value in ReplyPostIndex Field and msix_index
1054 * value in MSIxIndex field.
1055 */
1056 if (ioc->msix96_vector)
1057 writel(reply_q->reply_post_host_index | ((msix_index & 7) <<
1058 MPI2_RPHI_MSIX_INDEX_SHIFT),
1059 ioc->replyPostRegisterIndex[msix_index/8]);
1060 else
1061 writel(reply_q->reply_post_host_index | (msix_index <<
1062 MPI2_RPHI_MSIX_INDEX_SHIFT),
1063 &ioc->chip->ReplyPostHostIndex);
f92363d1
SR		 1064 atomic_dec(&reply_q->busy);
1065 return IRQ_HANDLED;
1066}
1067
1068/**
1069 * _base_is_controller_msix_enabled - is controller support muli-reply queues
1070 * @ioc: per adapter object
1071 *
1072 */
1073static inline int
1074_base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1075{
1076 return (ioc->facts.IOCCapabilities &
1077 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1078}
1079
1080/**
1081 * mpt3sas_base_flush_reply_queues - flushing the MSIX reply queues
1082 * @ioc: per adapter object
1083 * Context: ISR conext
1084 *
1085 * Called when a Task Management request has completed. We want
1086 * to flush the other reply queues so all the outstanding IO has been
1087 * completed back to OS before we process the TM completetion.
1088 *
1089 * Return nothing.
1090 */
1091void
1092mpt3sas_base_flush_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1093{
1094 struct adapter_reply_queue *reply_q;
1095
1096 /* If MSIX capability is turned off
1097 * then multi-queues are not enabled
1098 */
1099 if (!_base_is_controller_msix_enabled(ioc))
1100 return;
1101
1102 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1103 if (ioc->shost_recovery)
1104 return;
1105 /* TMs are on msix_index == 0 */
1106 if (reply_q->msix_index == 0)
1107 continue;
1108 _base_interrupt(reply_q->vector, (void *)reply_q);
1109 }
1110}
1111
1112/**
1113 * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1114 * @cb_idx: callback index
1115 *
1116 * Return nothing.
1117 */
1118void
1119mpt3sas_base_release_callback_handler(u8 cb_idx)
1120{
1121 mpt_callbacks[cb_idx] = NULL;
1122}
1123
1124/**
1125 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1126 * @cb_func: callback function
1127 *
1128 * Returns cb_func.
1129 */
1130u8
1131mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1132{
1133 u8 cb_idx;
1134
1135 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1136 if (mpt_callbacks[cb_idx] == NULL)
1137 break;
1138
1139 mpt_callbacks[cb_idx] = cb_func;
1140 return cb_idx;
1141}
1142
1143/**
1144 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1145 *
1146 * Return nothing.
1147 */
1148void
1149mpt3sas_base_initialize_callback_handler(void)
1150{
1151 u8 cb_idx;
1152
1153 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1154 mpt3sas_base_release_callback_handler(cb_idx);
1155}
1156
1157
1158/**
1159 * _base_build_zero_len_sge - build zero length sg entry
1160 * @ioc: per adapter object
1161 * @paddr: virtual address for SGE
1162 *
1163 * Create a zero length scatter gather entry to insure the IOCs hardware has
1164 * something to use if the target device goes brain dead and tries
1165 * to send data even when none is asked for.
1166 *
1167 * Return nothing.
1168 */
1169static void
1170_base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1171{
1172 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1173 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1174 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1175 MPI2_SGE_FLAGS_SHIFT);
1176 ioc->base_add_sg_single(paddr, flags_length, -1);
1177}
1178
1179/**
1180 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1181 * @paddr: virtual address for SGE
1182 * @flags_length: SGE flags and data transfer length
1183 * @dma_addr: Physical address
1184 *
1185 * Return nothing.
1186 */
1187static void
1188_base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1189{
1190 Mpi2SGESimple32_t *sgel = paddr;
1191
1192 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1193 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1194 sgel->FlagsLength = cpu_to_le32(flags_length);
1195 sgel->Address = cpu_to_le32(dma_addr);
1196}
1197
1198
1199/**
1200 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
1201 * @paddr: virtual address for SGE
1202 * @flags_length: SGE flags and data transfer length
1203 * @dma_addr: Physical address
1204 *
1205 * Return nothing.
1206 */
1207static void
1208_base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1209{
1210 Mpi2SGESimple64_t *sgel = paddr;
1211
1212 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
1213 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1214 sgel->FlagsLength = cpu_to_le32(flags_length);
1215 sgel->Address = cpu_to_le64(dma_addr);
1216}
1217
1218/**
1219 * _base_get_chain_buffer_tracker - obtain chain tracker
1220 * @ioc: per adapter object
1221 * @smid: smid associated to an IO request
1222 *
1223 * Returns chain tracker(from ioc->free_chain_list)
1224 */
1225static struct chain_tracker *
1226_base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1227{
1228 struct chain_tracker *chain_req;
1229 unsigned long flags;
1230
1231 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1232 if (list_empty(&ioc->free_chain_list)) {
1233 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1234 dfailprintk(ioc, pr_warn(MPT3SAS_FMT
1235 "chain buffers not available\n", ioc->name));
1236 return NULL;
1237 }
1238 chain_req = list_entry(ioc->free_chain_list.next,
1239 struct chain_tracker, tracker_list);
1240 list_del_init(&chain_req->tracker_list);
1241 list_add_tail(&chain_req->tracker_list,
1242 &ioc->scsi_lookup[smid - 1].chain_list);
1243 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1244 return chain_req;
1245}
1246
1247
1248/**
1249 * _base_build_sg - build generic sg
1250 * @ioc: per adapter object
1251 * @psge: virtual address for SGE
1252 * @data_out_dma: physical address for WRITES
1253 * @data_out_sz: data xfer size for WRITES
1254 * @data_in_dma: physical address for READS
1255 * @data_in_sz: data xfer size for READS
1256 *
1257 * Return nothing.
1258 */
1259static void
1260_base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
1261 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1262 size_t data_in_sz)
1263{
1264 u32 sgl_flags;
1265
1266 if (!data_out_sz && !data_in_sz) {
1267 _base_build_zero_len_sge(ioc, psge);
1268 return;
1269 }
1270
1271 if (data_out_sz && data_in_sz) {
1272 /* WRITE sgel first */
1273 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1274 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
1275 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1276 ioc->base_add_sg_single(psge, sgl_flags |
1277 data_out_sz, data_out_dma);
1278
1279 /* incr sgel */
1280 psge += ioc->sge_size;
1281
1282 /* READ sgel last */
1283 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1284 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1285 MPI2_SGE_FLAGS_END_OF_LIST);
1286 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1287 ioc->base_add_sg_single(psge, sgl_flags |
1288 data_in_sz, data_in_dma);
1289 } else if (data_out_sz) /* WRITE */ {
1290 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1291 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1292 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
1293 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1294 ioc->base_add_sg_single(psge, sgl_flags |
1295 data_out_sz, data_out_dma);
1296 } else if (data_in_sz) /* READ */ {
1297 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1298 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1299 MPI2_SGE_FLAGS_END_OF_LIST);
1300 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1301 ioc->base_add_sg_single(psge, sgl_flags |
1302 data_in_sz, data_in_dma);
1303 }
1304}
1305
1306/* IEEE format sgls */
1307
1308/**
1309 * _base_add_sg_single_ieee - add sg element for IEEE format
1310 * @paddr: virtual address for SGE
1311 * @flags: SGE flags
1312 * @chain_offset: number of 128 byte elements from start of segment
1313 * @length: data transfer length
1314 * @dma_addr: Physical address
1315 *
1316 * Return nothing.
1317 */
1318static void
1319_base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
1320 dma_addr_t dma_addr)
1321{
1322 Mpi25IeeeSgeChain64_t *sgel = paddr;
1323
1324 sgel->Flags = flags;
1325 sgel->NextChainOffset = chain_offset;
1326 sgel->Length = cpu_to_le32(length);
1327 sgel->Address = cpu_to_le64(dma_addr);
1328}
1329
1330/**
1331 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
1332 * @ioc: per adapter object
1333 * @paddr: virtual address for SGE
1334 *
1335 * Create a zero length scatter gather entry to insure the IOCs hardware has
1336 * something to use if the target device goes brain dead and tries
1337 * to send data even when none is asked for.
1338 *
1339 * Return nothing.
1340 */
1341static void
1342_base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1343{
1344 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1345 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
1346 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
1347 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
1348}
1349
471ef9d4
SR		 1350/**
1351 * _base_build_sg_scmd - main sg creation routine
1352 * @ioc: per adapter object
1353 * @scmd: scsi command
1354 * @smid: system request message index
1355 * Context: none.
1356 *
1357 * The main routine that builds scatter gather table from a given
1358 * scsi request sent via the .queuecommand main handler.
1359 *
1360 * Returns 0 success, anything else error
1361 */
1362static int
1363_base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
1364 struct scsi_cmnd *scmd, u16 smid)
1365{
1366 Mpi2SCSIIORequest_t *mpi_request;
1367 dma_addr_t chain_dma;
1368 struct scatterlist *sg_scmd;
1369 void *sg_local, *chain;
1370 u32 chain_offset;
1371 u32 chain_length;
1372 u32 chain_flags;
1373 int sges_left;
1374 u32 sges_in_segment;
1375 u32 sgl_flags;
1376 u32 sgl_flags_last_element;
1377 u32 sgl_flags_end_buffer;
1378 struct chain_tracker *chain_req;
1379
1380 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1381
1382 /* init scatter gather flags */
1383 sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
1384 if (scmd->sc_data_direction == DMA_TO_DEVICE)
1385 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
1386 sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
1387 << MPI2_SGE_FLAGS_SHIFT;
1388 sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
1389 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
1390 << MPI2_SGE_FLAGS_SHIFT;
1391 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1392
1393 sg_scmd = scsi_sglist(scmd);
1394 sges_left = scsi_dma_map(scmd);
1395 if (sges_left < 0) {
1396 sdev_printk(KERN_ERR, scmd->device,
1397 "pci_map_sg failed: request for %d bytes!\n",
1398 scsi_bufflen(scmd));
1399 return -ENOMEM;
1400 }
1401
1402 sg_local = &mpi_request->SGL;
1403 sges_in_segment = ioc->max_sges_in_main_message;
1404 if (sges_left <= sges_in_segment)
1405 goto fill_in_last_segment;
1406
1407 mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
1408 (sges_in_segment * ioc->sge_size))/4;
1409
1410 /* fill in main message segment when there is a chain following */
1411 while (sges_in_segment) {
1412 if (sges_in_segment == 1)
1413 ioc->base_add_sg_single(sg_local,
1414 sgl_flags_last_element | sg_dma_len(sg_scmd),
1415 sg_dma_address(sg_scmd));
1416 else
1417 ioc->base_add_sg_single(sg_local, sgl_flags |
1418 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1419 sg_scmd = sg_next(sg_scmd);
1420 sg_local += ioc->sge_size;
1421 sges_left--;
1422 sges_in_segment--;
1423 }
1424
1425 /* initializing the chain flags and pointers */
1426 chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
1427 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1428 if (!chain_req)
1429 return -1;
1430 chain = chain_req->chain_buffer;
1431 chain_dma = chain_req->chain_buffer_dma;
1432 do {
1433 sges_in_segment = (sges_left <=
1434 ioc->max_sges_in_chain_message) ? sges_left :
1435 ioc->max_sges_in_chain_message;
1436 chain_offset = (sges_left == sges_in_segment) ?
1437 0 : (sges_in_segment * ioc->sge_size)/4;
1438 chain_length = sges_in_segment * ioc->sge_size;
1439 if (chain_offset) {
1440 chain_offset = chain_offset <<
1441 MPI2_SGE_CHAIN_OFFSET_SHIFT;
1442 chain_length += ioc->sge_size;
1443 }
1444 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
1445 chain_length, chain_dma);
1446 sg_local = chain;
1447 if (!chain_offset)
1448 goto fill_in_last_segment;
1449
1450 /* fill in chain segments */
1451 while (sges_in_segment) {
1452 if (sges_in_segment == 1)
1453 ioc->base_add_sg_single(sg_local,
1454 sgl_flags_last_element |
1455 sg_dma_len(sg_scmd),
1456 sg_dma_address(sg_scmd));
1457 else
1458 ioc->base_add_sg_single(sg_local, sgl_flags |
1459 sg_dma_len(sg_scmd),
1460 sg_dma_address(sg_scmd));
1461 sg_scmd = sg_next(sg_scmd);
1462 sg_local += ioc->sge_size;
1463 sges_left--;
1464 sges_in_segment--;
1465 }
1466
1467 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1468 if (!chain_req)
1469 return -1;
1470 chain = chain_req->chain_buffer;
1471 chain_dma = chain_req->chain_buffer_dma;
1472 } while (1);
1473
1474
1475 fill_in_last_segment:
1476
1477 /* fill the last segment */
1478 while (sges_left) {
1479 if (sges_left == 1)
1480 ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
1481 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1482 else
1483 ioc->base_add_sg_single(sg_local, sgl_flags |
1484 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1485 sg_scmd = sg_next(sg_scmd);
1486 sg_local += ioc->sge_size;
1487 sges_left--;
1488 }
1489
1490 return 0;
1491}
1492
f92363d1
SR		 1493/**
1494 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
1495 * @ioc: per adapter object
1496 * @scmd: scsi command
1497 * @smid: system request message index
1498 * Context: none.
1499 *
1500 * The main routine that builds scatter gather table from a given
1501 * scsi request sent via the .queuecommand main handler.
1502 *
1503 * Returns 0 success, anything else error
1504 */
1505static int
1506_base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
1507 struct scsi_cmnd *scmd, u16 smid)
1508{
1509 Mpi2SCSIIORequest_t *mpi_request;
1510 dma_addr_t chain_dma;
1511 struct scatterlist *sg_scmd;
1512 void *sg_local, *chain;
1513 u32 chain_offset;
1514 u32 chain_length;
f92363d1
SR		 1515 int sges_left;
1516 u32 sges_in_segment;
1517 u8 simple_sgl_flags;
1518 u8 simple_sgl_flags_last;
1519 u8 chain_sgl_flags;
1520 struct chain_tracker *chain_req;
1521
1522 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1523
1524 /* init scatter gather flags */
1525 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1526 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1527 simple_sgl_flags_last = simple_sgl_flags |
1528 MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1529 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
1530 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1531
1532 sg_scmd = scsi_sglist(scmd);
1533 sges_left = scsi_dma_map(scmd);
62f5c74c 1534 if (sges_left < 0) {
f92363d1
SR		 1535 sdev_printk(KERN_ERR, scmd->device,
1536 "pci_map_sg failed: request for %d bytes!\n",
1537 scsi_bufflen(scmd));
1538 return -ENOMEM;
1539 }
1540
1541 sg_local = &mpi_request->SGL;
1542 sges_in_segment = (ioc->request_sz -
1543 offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
1544 if (sges_left <= sges_in_segment)
1545 goto fill_in_last_segment;
1546
1547 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
1548 (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
1549
1550 /* fill in main message segment when there is a chain following */
1551 while (sges_in_segment > 1) {
1552 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1553 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1554 sg_scmd = sg_next(sg_scmd);
1555 sg_local += ioc->sge_size_ieee;
1556 sges_left--;
1557 sges_in_segment--;
1558 }
1559
25ef16d0 1560 /* initializing the pointers */
f92363d1
SR		 1561 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1562 if (!chain_req)
1563 return -1;
1564 chain = chain_req->chain_buffer;
1565 chain_dma = chain_req->chain_buffer_dma;
1566 do {
1567 sges_in_segment = (sges_left <=
1568 ioc->max_sges_in_chain_message) ? sges_left :
1569 ioc->max_sges_in_chain_message;
1570 chain_offset = (sges_left == sges_in_segment) ?
1571 0 : sges_in_segment;
1572 chain_length = sges_in_segment * ioc->sge_size_ieee;
1573 if (chain_offset)
1574 chain_length += ioc->sge_size_ieee;
1575 _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
1576 chain_offset, chain_length, chain_dma);
1577
1578 sg_local = chain;
1579 if (!chain_offset)
1580 goto fill_in_last_segment;
1581
1582 /* fill in chain segments */
1583 while (sges_in_segment) {
1584 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1585 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1586 sg_scmd = sg_next(sg_scmd);
1587 sg_local += ioc->sge_size_ieee;
1588 sges_left--;
1589 sges_in_segment--;
1590 }
1591
1592 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1593 if (!chain_req)
1594 return -1;
1595 chain = chain_req->chain_buffer;
1596 chain_dma = chain_req->chain_buffer_dma;
1597 } while (1);
1598
1599
1600 fill_in_last_segment:
1601
1602 /* fill the last segment */
62f5c74c 1603 while (sges_left > 0) {
f92363d1
SR		 1604 if (sges_left == 1)
1605 _base_add_sg_single_ieee(sg_local,
1606 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
1607 sg_dma_address(sg_scmd));
1608 else
1609 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1610 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1611 sg_scmd = sg_next(sg_scmd);
1612 sg_local += ioc->sge_size_ieee;
1613 sges_left--;
1614 }
1615
1616 return 0;
1617}
1618
1619/**
1620 * _base_build_sg_ieee - build generic sg for IEEE format
1621 * @ioc: per adapter object
1622 * @psge: virtual address for SGE
1623 * @data_out_dma: physical address for WRITES
1624 * @data_out_sz: data xfer size for WRITES
1625 * @data_in_dma: physical address for READS
1626 * @data_in_sz: data xfer size for READS
1627 *
1628 * Return nothing.
1629 */
1630static void
1631_base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
1632 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1633 size_t data_in_sz)
1634{
1635 u8 sgl_flags;
1636
1637 if (!data_out_sz && !data_in_sz) {
1638 _base_build_zero_len_sge_ieee(ioc, psge);
1639 return;
1640 }
1641
1642 if (data_out_sz && data_in_sz) {
1643 /* WRITE sgel first */
1644 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1645 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1646 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1647 data_out_dma);
1648
1649 /* incr sgel */
1650 psge += ioc->sge_size_ieee;
1651
1652 /* READ sgel last */
1653 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1654 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1655 data_in_dma);
1656 } else if (data_out_sz) /* WRITE */ {
1657 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1658 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1659 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1660 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1661 data_out_dma);
1662 } else if (data_in_sz) /* READ */ {
1663 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1664 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1665 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1666 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1667 data_in_dma);
1668 }
1669}
1670
1671#define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
1672
1673/**
1674 * _base_config_dma_addressing - set dma addressing
1675 * @ioc: per adapter object
1676 * @pdev: PCI device struct
1677 *
1678 * Returns 0 for success, non-zero for failure.
1679 */
1680static int
1681_base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
1682{
1683 struct sysinfo s;
9b05c91a
SR		 1684 u64 consistent_dma_mask;
1685
1686 if (ioc->dma_mask)
1687 consistent_dma_mask = DMA_BIT_MASK(64);
1688 else
1689 consistent_dma_mask = DMA_BIT_MASK(32);
f92363d1
SR		 1690
1691 if (sizeof(dma_addr_t) > 4) {
1692 const uint64_t required_mask =
1693 dma_get_required_mask(&pdev->dev);
1694 if ((required_mask > DMA_BIT_MASK(32)) &&
1695 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
9b05c91a 1696 !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
f92363d1
SR		 1697 ioc->base_add_sg_single = &_base_add_sg_single_64;
1698 ioc->sge_size = sizeof(Mpi2SGESimple64_t);
9b05c91a 1699 ioc->dma_mask = 64;
f92363d1
SR		 1700 goto out;
1701 }
1702 }
1703
1704 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1705 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1706 ioc->base_add_sg_single = &_base_add_sg_single_32;
1707 ioc->sge_size = sizeof(Mpi2SGESimple32_t);
9b05c91a 1708 ioc->dma_mask = 32;
f92363d1
SR		 1709 } else
1710 return -ENODEV;
1711
1712 out:
1713 si_meminfo(&s);
1714 pr_info(MPT3SAS_FMT
9b05c91a
SR		 1715 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
1716 ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
1717
1718 return 0;
1719}
f92363d1 1720
9b05c91a
SR		 1721static int
1722_base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
1723 struct pci_dev *pdev)
1724{
1725 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1726 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
1727 return -ENODEV;
1728 }
f92363d1
SR		 1729 return 0;
1730}
1731
1732/**
1733 * _base_check_enable_msix - checks MSIX capabable.
1734 * @ioc: per adapter object
1735 *
1736 * Check to see if card is capable of MSIX, and set number
1737 * of available msix vectors
1738 */
1739static int
1740_base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1741{
1742 int base;
1743 u16 message_control;
1744
42081173
SR		 1745 /* Check whether controller SAS2008 B0 controller,
1746 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
1747 */
1748 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
1749 ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
1750 return -EINVAL;
1751 }
1752
f92363d1
SR		 1753 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
1754 if (!base) {
1755 dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
1756 ioc->name));
1757 return -EINVAL;
1758 }
1759
1760 /* get msix vector count */
42081173
SR		 1761 /* NUMA_IO not supported for older controllers */
1762 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
1763 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
1764 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
1765 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
1766 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
1767 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
1768 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
1769 ioc->msix_vector_count = 1;
1770 else {
1771 pci_read_config_word(ioc->pdev, base + 2, &message_control);
1772 ioc->msix_vector_count = (message_control & 0x3FF) + 1;
1773 }
f92363d1
SR		 1774 dinitprintk(ioc, pr_info(MPT3SAS_FMT
1775 "msix is supported, vector_count(%d)\n",
1776 ioc->name, ioc->msix_vector_count));
1777 return 0;
1778}
1779
1780/**
1781 * _base_free_irq - free irq
1782 * @ioc: per adapter object
1783 *
1784 * Freeing respective reply_queue from the list.
1785 */
1786static void
1787_base_free_irq(struct MPT3SAS_ADAPTER *ioc)
1788{
1789 struct adapter_reply_queue *reply_q, *next;
1790
1791 if (list_empty(&ioc->reply_queue_list))
1792 return;
1793
1794 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1795 list_del(&reply_q->list);
14b3114d
SR		 1796 irq_set_affinity_hint(reply_q->vector, NULL);
1797 free_cpumask_var(reply_q->affinity_hint);
f92363d1
SR		 1798 synchronize_irq(reply_q->vector);
1799 free_irq(reply_q->vector, reply_q);
1800 kfree(reply_q);
1801 }
1802}
1803
1804/**
1805 * _base_request_irq - request irq
1806 * @ioc: per adapter object
1807 * @index: msix index into vector table
1808 * @vector: irq vector
1809 *
1810 * Inserting respective reply_queue into the list.
1811 */
1812static int
1813_base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index, u32 vector)
1814{
1815 struct adapter_reply_queue *reply_q;
1816 int r;
1817
1818 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
1819 if (!reply_q) {
1820 pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
1821 ioc->name, (int)sizeof(struct adapter_reply_queue));
1822 return -ENOMEM;
1823 }
1824 reply_q->ioc = ioc;
1825 reply_q->msix_index = index;
1826 reply_q->vector = vector;
14b3114d
SR		 1827
1828 if (!alloc_cpumask_var(&reply_q->affinity_hint, GFP_KERNEL))
1829 return -ENOMEM;
1830 cpumask_clear(reply_q->affinity_hint);
1831
f92363d1
SR		 1832 atomic_set(&reply_q->busy, 0);
1833 if (ioc->msix_enable)
1834 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
d357e84d 1835 driver_name, ioc->id, index);
f92363d1
SR		 1836 else
1837 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
d357e84d 1838 driver_name, ioc->id);
f92363d1
SR		 1839 r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name,
1840 reply_q);
1841 if (r) {
1842 pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
1843 reply_q->name, vector);
1844 kfree(reply_q);
1845 return -EBUSY;
1846 }
1847
1848 INIT_LIST_HEAD(&reply_q->list);
1849 list_add_tail(&reply_q->list, &ioc->reply_queue_list);
1850 return 0;
1851}
1852
1853/**
1854 * _base_assign_reply_queues - assigning msix index for each cpu
1855 * @ioc: per adapter object
1856 *
1857 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
1858 *
1859 * It would nice if we could call irq_set_affinity, however it is not
1860 * an exported symbol
1861 */
1862static void
1863_base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1864{
91b265bf 1865 unsigned int cpu, nr_cpus, nr_msix, index = 0;
14b3114d 1866 struct adapter_reply_queue *reply_q;
f92363d1
SR		 1867
1868 if (!_base_is_controller_msix_enabled(ioc))
1869 return;
1870
1871 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
1872
91b265bf
MP		 1873 nr_cpus = num_online_cpus();
1874 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
1875 ioc->facts.MaxMSIxVectors);
1876 if (!nr_msix)
1877 return;
f92363d1 1878
91b265bf
MP		 1879 cpu = cpumask_first(cpu_online_mask);
1880
14b3114d
SR		 1881 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1882
91b265bf
MP		 1883 unsigned int i, group = nr_cpus / nr_msix;
1884
14b3114d
SR		 1885 if (cpu >= nr_cpus)
1886 break;
1887
91b265bf
MP		 1888 if (index < nr_cpus % nr_msix)
1889 group++;
1890
1891 for (i = 0 ; i < group ; i++) {
1892 ioc->cpu_msix_table[cpu] = index;
14b3114d
SR		 1893 cpumask_or(reply_q->affinity_hint,
1894 reply_q->affinity_hint, get_cpu_mask(cpu));
91b265bf 1895 cpu = cpumask_next(cpu, cpu_online_mask);
f92363d1 1896 }
91b265bf 1897
14b3114d
SR		 1898 if (irq_set_affinity_hint(reply_q->vector,
1899 reply_q->affinity_hint))
1900 dinitprintk(ioc, pr_info(MPT3SAS_FMT
1901 "error setting affinity hint for irq vector %d\n",
1902 ioc->name, reply_q->vector));
91b265bf 1903 index++;
14b3114d 1904 }
f92363d1
SR		 1905}
1906
1907/**
1908 * _base_disable_msix - disables msix
1909 * @ioc: per adapter object
1910 *
1911 */
1912static void
1913_base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
1914{
1915 if (!ioc->msix_enable)
1916 return;
1917 pci_disable_msix(ioc->pdev);
1918 ioc->msix_enable = 0;
1919}
1920
1921/**
1922 * _base_enable_msix - enables msix, failback to io_apic
1923 * @ioc: per adapter object
1924 *
1925 */
1926static int
1927_base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1928{
1929 struct msix_entry *entries, *a;
1930 int r;
1931 int i;
1932 u8 try_msix = 0;
1933
f92363d1
SR		 1934 if (msix_disable == -1 || msix_disable == 0)
1935 try_msix = 1;
1936
1937 if (!try_msix)
1938 goto try_ioapic;
1939
1940 if (_base_check_enable_msix(ioc) != 0)
1941 goto try_ioapic;
1942
1943 ioc->reply_queue_count = min_t(int, ioc->cpu_count,
1944 ioc->msix_vector_count);
1945
9c500060
SR		 1946 printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
1947 ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
1948 ioc->cpu_count, max_msix_vectors);
1949
9b05c91a
SR		 1950 if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
1951 max_msix_vectors = 8;
1952
9c500060
SR		 1953 if (max_msix_vectors > 0) {
1954 ioc->reply_queue_count = min_t(int, max_msix_vectors,
1955 ioc->reply_queue_count);
1956 ioc->msix_vector_count = ioc->reply_queue_count;
9b05c91a
SR		 1957 } else if (max_msix_vectors == 0)
1958 goto try_ioapic;
9c500060 1959
f92363d1
SR		 1960 entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry),
1961 GFP_KERNEL);
1962 if (!entries) {
1963 dfailprintk(ioc, pr_info(MPT3SAS_FMT
1964 "kcalloc failed @ at %s:%d/%s() !!!\n",
1965 ioc->name, __FILE__, __LINE__, __func__));
1966 goto try_ioapic;
1967 }
1968
1969 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++)
1970 a->entry = i;
1971
6bfa6907 1972 r = pci_enable_msix_exact(ioc->pdev, entries, ioc->reply_queue_count);
f92363d1
SR		 1973 if (r) {
1974 dfailprintk(ioc, pr_info(MPT3SAS_FMT
6bfa6907 1975 "pci_enable_msix_exact failed (r=%d) !!!\n",
f92363d1
SR		 1976 ioc->name, r));
1977 kfree(entries);
1978 goto try_ioapic;
1979 }
1980
1981 ioc->msix_enable = 1;
1982 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) {
1983 r = _base_request_irq(ioc, i, a->vector);
1984 if (r) {
1985 _base_free_irq(ioc);
1986 _base_disable_msix(ioc);
1987 kfree(entries);
1988 goto try_ioapic;
1989 }
1990 }
1991
1992 kfree(entries);
1993 return 0;
1994
1995/* failback to io_apic interrupt routing */
1996 try_ioapic:
1997
9b05c91a 1998 ioc->reply_queue_count = 1;
f92363d1
SR		 1999 r = _base_request_irq(ioc, 0, ioc->pdev->irq);
2000
2001 return r;
2002}
2003
580d4e31
SR		 2004/**
2005 * mpt3sas_base_unmap_resources - free controller resources
2006 * @ioc: per adapter object
2007 */
2008void
2009mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
2010{
2011 struct pci_dev *pdev = ioc->pdev;
2012
2013 dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n",
2014 ioc->name, __func__));
2015
2016 _base_free_irq(ioc);
2017 _base_disable_msix(ioc);
2018
2019 if (ioc->msix96_vector)
2020 kfree(ioc->replyPostRegisterIndex);
2021
2022 if (ioc->chip_phys) {
2023 iounmap(ioc->chip);
2024 ioc->chip_phys = 0;
2025 }
2026
2027 if (pci_is_enabled(pdev)) {
2028 pci_release_selected_regions(ioc->pdev, ioc->bars);
2029 pci_disable_pcie_error_reporting(pdev);
2030 pci_disable_device(pdev);
2031 }
2032}
2033
f92363d1
SR		 2034/**
2035 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
2036 * @ioc: per adapter object
2037 *
2038 * Returns 0 for success, non-zero for failure.
2039 */
2040int
2041mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
2042{
2043 struct pci_dev *pdev = ioc->pdev;
2044 u32 memap_sz;
2045 u32 pio_sz;
2046 int i, r = 0;
2047 u64 pio_chip = 0;
2048 u64 chip_phys = 0;
2049 struct adapter_reply_queue *reply_q;
2050
2051 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
2052 ioc->name, __func__));
2053
2054 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
2055 if (pci_enable_device_mem(pdev)) {
2056 pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
2057 ioc->name);
cf9bd21a 2058 ioc->bars = 0;
f92363d1
SR		 2059 return -ENODEV;
2060 }
2061
2062
2063 if (pci_request_selected_regions(pdev, ioc->bars,
d357e84d 2064 driver_name)) {
f92363d1
SR		 2065 pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
2066 ioc->name);
cf9bd21a 2067 ioc->bars = 0;
f92363d1
SR		 2068 r = -ENODEV;
2069 goto out_fail;
2070 }
2071
2072/* AER (Advanced Error Reporting) hooks */
2073 pci_enable_pcie_error_reporting(pdev);
2074
2075 pci_set_master(pdev);
2076
2077
2078 if (_base_config_dma_addressing(ioc, pdev) != 0) {
2079 pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
2080 ioc->name, pci_name(pdev));
2081 r = -ENODEV;
2082 goto out_fail;
2083 }
2084
5aeeb78a
SR		 2085 for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
2086 (!memap_sz || !pio_sz); i++) {
f92363d1
SR		 2087 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
2088 if (pio_sz)
2089 continue;
2090 pio_chip = (u64)pci_resource_start(pdev, i);
2091 pio_sz = pci_resource_len(pdev, i);
2092 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
2093 if (memap_sz)
2094 continue;
2095 ioc->chip_phys = pci_resource_start(pdev, i);
2096 chip_phys = (u64)ioc->chip_phys;
2097 memap_sz = pci_resource_len(pdev, i);
2098 ioc->chip = ioremap(ioc->chip_phys, memap_sz);
f92363d1
SR		 2099 }
2100 }
2101
5aeeb78a
SR		 2102 if (ioc->chip == NULL) {
2103 pr_err(MPT3SAS_FMT "unable to map adapter memory! "
2104 " or resource not found\n", ioc->name);
2105 r = -EINVAL;
2106 goto out_fail;
2107 }
2108
f92363d1 2109 _base_mask_interrupts(ioc);
9b05c91a
SR		 2110
2111 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
2112 if (r)
2113 goto out_fail;
2114
2115 if (!ioc->rdpq_array_enable_assigned) {
2116 ioc->rdpq_array_enable = ioc->rdpq_array_capable;
2117 ioc->rdpq_array_enable_assigned = 1;
2118 }
2119
f92363d1
SR		 2120 r = _base_enable_msix(ioc);
2121 if (r)
2122 goto out_fail;
2123
fb77bb53
SR		 2124 /* Use the Combined reply queue feature only for SAS3 C0 & higher
2125 * revision HBAs and also only when reply queue count is greater than 8
2126 */
2127 if (ioc->msix96_vector && ioc->reply_queue_count > 8) {
2128 /* Determine the Supplemental Reply Post Host Index Registers
2129 * Addresse. Supplemental Reply Post Host Index Registers
2130 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
2131 * each register is at offset bytes of
2132 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
2133 */
2134 ioc->replyPostRegisterIndex = kcalloc(
2135 MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT,
2136 sizeof(resource_size_t *), GFP_KERNEL);
2137 if (!ioc->replyPostRegisterIndex) {
2138 dfailprintk(ioc, printk(MPT3SAS_FMT
2139 "allocation for reply Post Register Index failed!!!\n",
2140 ioc->name));
2141 r = -ENOMEM;
2142 goto out_fail;
2143 }
2144
2145 for (i = 0; i < MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT; i++) {
2146 ioc->replyPostRegisterIndex[i] = (resource_size_t *)
2147 ((u8 *)&ioc->chip->Doorbell +
2148 MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
2149 (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
2150 }
2151 } else
2152 ioc->msix96_vector = 0;
2153
f92363d1
SR		 2154 list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
2155 pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
2156 reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
2157 "IO-APIC enabled"), reply_q->vector);
2158
2159 pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
2160 ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
2161 pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
2162 ioc->name, (unsigned long long)pio_chip, pio_sz);
2163
2164 /* Save PCI configuration state for recovery from PCI AER/EEH errors */
2165 pci_save_state(pdev);
2166 return 0;
2167
2168 out_fail:
580d4e31 2169 mpt3sas_base_unmap_resources(ioc);
f92363d1
SR		 2170 return r;
2171}
2172
2173/**
2174 * mpt3sas_base_get_msg_frame - obtain request mf pointer
2175 * @ioc: per adapter object
2176 * @smid: system request message index(smid zero is invalid)
2177 *
2178 * Returns virt pointer to message frame.
2179 */
2180void *
2181mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2182{
2183 return (void *)(ioc->request + (smid * ioc->request_sz));
2184}
2185
2186/**
2187 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
2188 * @ioc: per adapter object
2189 * @smid: system request message index
2190 *
2191 * Returns virt pointer to sense buffer.
2192 */
2193void *
2194mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2195{
2196 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
2197}
2198
2199/**
2200 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
2201 * @ioc: per adapter object
2202 * @smid: system request message index
2203 *
2204 * Returns phys pointer to the low 32bit address of the sense buffer.
2205 */
2206__le32
2207mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2208{
2209 return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
2210 SCSI_SENSE_BUFFERSIZE));
2211}
2212
2213/**
2214 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
2215 * @ioc: per adapter object
2216 * @phys_addr: lower 32 physical addr of the reply
2217 *
2218 * Converts 32bit lower physical addr into a virt address.
2219 */
2220void *
2221mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
2222{
2223 if (!phys_addr)
2224 return NULL;
2225 return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
2226}
2227
2228/**
2229 * mpt3sas_base_get_smid - obtain a free smid from internal queue
2230 * @ioc: per adapter object
2231 * @cb_idx: callback index
2232 *
2233 * Returns smid (zero is invalid)
2234 */
2235u16
2236mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2237{
2238 unsigned long flags;
2239 struct request_tracker *request;
2240 u16 smid;
2241
2242 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2243 if (list_empty(&ioc->internal_free_list)) {
2244 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2245 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2246 ioc->name, __func__);
2247 return 0;
2248 }
2249
2250 request = list_entry(ioc->internal_free_list.next,
2251 struct request_tracker, tracker_list);
2252 request->cb_idx = cb_idx;
2253 smid = request->smid;
2254 list_del(&request->tracker_list);
2255 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2256 return smid;
2257}
2258
2259/**
2260 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
2261 * @ioc: per adapter object
2262 * @cb_idx: callback index
2263 * @scmd: pointer to scsi command object
2264 *
2265 * Returns smid (zero is invalid)
2266 */
2267u16
2268mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
2269 struct scsi_cmnd *scmd)
2270{
2271 unsigned long flags;
2272 struct scsiio_tracker *request;
2273 u16 smid;
2274
2275 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2276 if (list_empty(&ioc->free_list)) {
2277 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2278 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2279 ioc->name, __func__);
2280 return 0;
2281 }
2282
2283 request = list_entry(ioc->free_list.next,
2284 struct scsiio_tracker, tracker_list);
2285 request->scmd = scmd;
2286 request->cb_idx = cb_idx;
2287 smid = request->smid;
2288 list_del(&request->tracker_list);
2289 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2290 return smid;
2291}
2292
2293/**
2294 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
2295 * @ioc: per adapter object
2296 * @cb_idx: callback index
2297 *
2298 * Returns smid (zero is invalid)
2299 */
2300u16
2301mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2302{
2303 unsigned long flags;
2304 struct request_tracker *request;
2305 u16 smid;
2306
2307 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2308 if (list_empty(&ioc->hpr_free_list)) {
2309 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2310 return 0;
2311 }
2312
2313 request = list_entry(ioc->hpr_free_list.next,
2314 struct request_tracker, tracker_list);
2315 request->cb_idx = cb_idx;
2316 smid = request->smid;
2317 list_del(&request->tracker_list);
2318 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2319 return smid;
2320}
2321
2322/**
2323 * mpt3sas_base_free_smid - put smid back on free_list
2324 * @ioc: per adapter object
2325 * @smid: system request message index
2326 *
2327 * Return nothing.
2328 */
2329void
2330mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2331{
2332 unsigned long flags;
2333 int i;
2334 struct chain_tracker *chain_req, *next;
2335
2336 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2337 if (smid < ioc->hi_priority_smid) {
2338 /* scsiio queue */
2339 i = smid - 1;
2340 if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
2341 list_for_each_entry_safe(chain_req, next,
2342 &ioc->scsi_lookup[i].chain_list, tracker_list) {
2343 list_del_init(&chain_req->tracker_list);
2344 list_add(&chain_req->tracker_list,
2345 &ioc->free_chain_list);
2346 }
2347 }
2348 ioc->scsi_lookup[i].cb_idx = 0xFF;
2349 ioc->scsi_lookup[i].scmd = NULL;
7786ab6a 2350 ioc->scsi_lookup[i].direct_io = 0;
f92363d1
SR		 2351 list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list);
2352 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2353
2354 /*
2355 * See _wait_for_commands_to_complete() call with regards
2356 * to this code.
2357 */
2358 if (ioc->shost_recovery && ioc->pending_io_count) {
2359 if (ioc->pending_io_count == 1)
2360 wake_up(&ioc->reset_wq);
2361 ioc->pending_io_count--;
2362 }
2363 return;
2364 } else if (smid < ioc->internal_smid) {
2365 /* hi-priority */
2366 i = smid - ioc->hi_priority_smid;
2367 ioc->hpr_lookup[i].cb_idx = 0xFF;
2368 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
2369 } else if (smid <= ioc->hba_queue_depth) {
2370 /* internal queue */
2371 i = smid - ioc->internal_smid;
2372 ioc->internal_lookup[i].cb_idx = 0xFF;
2373 list_add(&ioc->internal_lookup[i].tracker_list,
2374 &ioc->internal_free_list);
2375 }
2376 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2377}
2378
2379/**
2380 * _base_writeq - 64 bit write to MMIO
2381 * @ioc: per adapter object
2382 * @b: data payload
2383 * @addr: address in MMIO space
2384 * @writeq_lock: spin lock
2385 *
2386 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
2387 * care of 32 bit environment where its not quarenteed to send the entire word
2388 * in one transfer.
2389 */
2390#if defined(writeq) && defined(CONFIG_64BIT)
2391static inline void
2392_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2393{
2394 writeq(cpu_to_le64(b), addr);
2395}
2396#else
2397static inline void
2398_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2399{
2400 unsigned long flags;
2401 __u64 data_out = cpu_to_le64(b);
2402
2403 spin_lock_irqsave(writeq_lock, flags);
2404 writel((u32)(data_out), addr);
2405 writel((u32)(data_out >> 32), (addr + 4));
2406 spin_unlock_irqrestore(writeq_lock, flags);
2407}
2408#endif
2409
2410static inline u8
2411_base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
2412{
2413 return ioc->cpu_msix_table[raw_smp_processor_id()];
2414}
2415
2416/**
2417 * mpt3sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
2418 * @ioc: per adapter object
2419 * @smid: system request message index
2420 * @handle: device handle
2421 *
2422 * Return nothing.
2423 */
2424void
2425mpt3sas_base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
2426{
2427 Mpi2RequestDescriptorUnion_t descriptor;
2428 u64 *request = (u64 *)&descriptor;
2429
2430
2431 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
2432 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2433 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2434 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2435 descriptor.SCSIIO.LMID = 0;
2436 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2437 &ioc->scsi_lookup_lock);
2438}
2439
2440/**
2441 * mpt3sas_base_put_smid_fast_path - send fast path request to firmware
2442 * @ioc: per adapter object
2443 * @smid: system request message index
2444 * @handle: device handle
2445 *
2446 * Return nothing.
2447 */
2448void
2449mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2450 u16 handle)
2451{
2452 Mpi2RequestDescriptorUnion_t descriptor;
2453 u64 *request = (u64 *)&descriptor;
2454
2455 descriptor.SCSIIO.RequestFlags =
2456 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
2457 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2458 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2459 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2460 descriptor.SCSIIO.LMID = 0;
2461 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2462 &ioc->scsi_lookup_lock);
2463}
2464
2465/**
2466 * mpt3sas_base_put_smid_hi_priority - send Task Managment request to firmware
2467 * @ioc: per adapter object
2468 * @smid: system request message index
2469 *
2470 * Return nothing.
2471 */
2472void
2473mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2474{
2475 Mpi2RequestDescriptorUnion_t descriptor;
2476 u64 *request = (u64 *)&descriptor;
2477
2478 descriptor.HighPriority.RequestFlags =
2479 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
2480 descriptor.HighPriority.MSIxIndex = 0;
2481 descriptor.HighPriority.SMID = cpu_to_le16(smid);
2482 descriptor.HighPriority.LMID = 0;
2483 descriptor.HighPriority.Reserved1 = 0;
2484 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2485 &ioc->scsi_lookup_lock);
2486}
2487
2488/**
2489 * mpt3sas_base_put_smid_default - Default, primarily used for config pages
2490 * @ioc: per adapter object
2491 * @smid: system request message index
2492 *
2493 * Return nothing.
2494 */
2495void
2496mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2497{
2498 Mpi2RequestDescriptorUnion_t descriptor;
2499 u64 *request = (u64 *)&descriptor;
2500
2501 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2502 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
2503 descriptor.Default.SMID = cpu_to_le16(smid);
2504 descriptor.Default.LMID = 0;
2505 descriptor.Default.DescriptorTypeDependent = 0;
2506 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2507 &ioc->scsi_lookup_lock);
2508}
2509
1117b31a 2510/**
989e43c7 2511 * _base_display_OEMs_branding - Display branding string
1117b31a
SR		 2512 * @ioc: per adapter object
2513 *
2514 * Return nothing.
2515 */
2516static void
989e43c7 2517_base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc)
1117b31a
SR		 2518{
2519 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
2520 return;
2521
989e43c7
SR		 2522 switch (ioc->pdev->subsystem_vendor) {
2523 case PCI_VENDOR_ID_INTEL:
2524 switch (ioc->pdev->device) {
2525 case MPI2_MFGPAGE_DEVID_SAS2008:
2526 switch (ioc->pdev->subsystem_device) {
2527 case MPT2SAS_INTEL_RMS2LL080_SSDID:
2528 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2529 MPT2SAS_INTEL_RMS2LL080_BRANDING);
2530 break;
2531 case MPT2SAS_INTEL_RMS2LL040_SSDID:
2532 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2533 MPT2SAS_INTEL_RMS2LL040_BRANDING);
2534 break;
2535 case MPT2SAS_INTEL_SSD910_SSDID:
2536 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2537 MPT2SAS_INTEL_SSD910_BRANDING);
2538 break;
2539 default:
2540 pr_info(MPT3SAS_FMT
2541 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2542 ioc->name, ioc->pdev->subsystem_device);
2543 break;
2544 }
2545 case MPI2_MFGPAGE_DEVID_SAS2308_2:
2546 switch (ioc->pdev->subsystem_device) {
2547 case MPT2SAS_INTEL_RS25GB008_SSDID:
2548 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2549 MPT2SAS_INTEL_RS25GB008_BRANDING);
2550 break;
2551 case MPT2SAS_INTEL_RMS25JB080_SSDID:
2552 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2553 MPT2SAS_INTEL_RMS25JB080_BRANDING);
2554 break;
2555 case MPT2SAS_INTEL_RMS25JB040_SSDID:
2556 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2557 MPT2SAS_INTEL_RMS25JB040_BRANDING);
2558 break;
2559 case MPT2SAS_INTEL_RMS25KB080_SSDID:
2560 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2561 MPT2SAS_INTEL_RMS25KB080_BRANDING);
2562 break;
2563 case MPT2SAS_INTEL_RMS25KB040_SSDID:
2564 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2565 MPT2SAS_INTEL_RMS25KB040_BRANDING);
2566 break;
2567 case MPT2SAS_INTEL_RMS25LB040_SSDID:
2568 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2569 MPT2SAS_INTEL_RMS25LB040_BRANDING);
2570 break;
2571 case MPT2SAS_INTEL_RMS25LB080_SSDID:
2572 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2573 MPT2SAS_INTEL_RMS25LB080_BRANDING);
2574 break;
2575 default:
2576 pr_info(MPT3SAS_FMT
2577 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2578 ioc->name, ioc->pdev->subsystem_device);
2579 break;
2580 }
2581 case MPI25_MFGPAGE_DEVID_SAS3008:
2582 switch (ioc->pdev->subsystem_device) {
2583 case MPT3SAS_INTEL_RMS3JC080_SSDID:
2584 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2585 MPT3SAS_INTEL_RMS3JC080_BRANDING);
2586 break;
2587
2588 case MPT3SAS_INTEL_RS3GC008_SSDID:
2589 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2590 MPT3SAS_INTEL_RS3GC008_BRANDING);
2591 break;
2592 case MPT3SAS_INTEL_RS3FC044_SSDID:
2593 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2594 MPT3SAS_INTEL_RS3FC044_BRANDING);
2595 break;
2596 case MPT3SAS_INTEL_RS3UC080_SSDID:
2597 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2598 MPT3SAS_INTEL_RS3UC080_BRANDING);
2599 break;
2600 default:
2601 pr_info(MPT3SAS_FMT
2602 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2603 ioc->name, ioc->pdev->subsystem_device);
2604 break;
2605 }
1117b31a
SR		 2606 break;
2607 default:
2608 pr_info(MPT3SAS_FMT
989e43c7
SR		 2609 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2610 ioc->name, ioc->pdev->subsystem_device);
1117b31a
SR		 2611 break;
2612 }
2613 break;
989e43c7
SR		 2614 case PCI_VENDOR_ID_DELL:
2615 switch (ioc->pdev->device) {
2616 case MPI2_MFGPAGE_DEVID_SAS2008:
2617 switch (ioc->pdev->subsystem_device) {
2618 case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
2619 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2620 MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
2621 break;
2622 case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
2623 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2624 MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
2625 break;
2626 case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
2627 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2628 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
2629 break;
2630 case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
2631 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2632 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
2633 break;
2634 case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
2635 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2636 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
2637 break;
2638 case MPT2SAS_DELL_PERC_H200_SSDID:
2639 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2640 MPT2SAS_DELL_PERC_H200_BRANDING);
2641 break;
2642 case MPT2SAS_DELL_6GBPS_SAS_SSDID:
2643 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2644 MPT2SAS_DELL_6GBPS_SAS_BRANDING);
2645 break;
2646 default:
2647 pr_info(MPT3SAS_FMT
2648 "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
2649 ioc->name, ioc->pdev->subsystem_device);
2650 break;
2651 }
2652 break;
2653 case MPI25_MFGPAGE_DEVID_SAS3008:
2654 switch (ioc->pdev->subsystem_device) {
2655 case MPT3SAS_DELL_12G_HBA_SSDID:
2656 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2657 MPT3SAS_DELL_12G_HBA_BRANDING);
2658 break;
2659 default:
2660 pr_info(MPT3SAS_FMT
2661 "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
2662 ioc->name, ioc->pdev->subsystem_device);
2663 break;
2664 }
fb84dfc4
SR		 2665 break;
2666 default:
2667 pr_info(MPT3SAS_FMT
989e43c7 2668 "Dell HBA: Subsystem ID: 0x%X\n", ioc->name,
fb84dfc4
SR		 2669 ioc->pdev->subsystem_device);
2670 break;
2671 }
2672 break;
989e43c7
SR		 2673 case PCI_VENDOR_ID_CISCO:
2674 switch (ioc->pdev->device) {
2675 case MPI25_MFGPAGE_DEVID_SAS3008:
2676 switch (ioc->pdev->subsystem_device) {
2677 case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
2678 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2679 MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
2680 break;
2681 case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
2682 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2683 MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
2684 break;
2685 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2686 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2687 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
2688 break;
2689 default:
2690 pr_info(MPT3SAS_FMT
2691 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2692 ioc->name, ioc->pdev->subsystem_device);
2693 break;
2694 }
d8eb4a47 2695 break;
989e43c7
SR		 2696 case MPI25_MFGPAGE_DEVID_SAS3108_1:
2697 switch (ioc->pdev->subsystem_device) {
2698 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2699 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
d8eb4a47 2700 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
989e43c7
SR		 2701 break;
2702 case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
2703 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2704 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING
2705 );
2706 break;
2707 default:
2708 pr_info(MPT3SAS_FMT
2709 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2710 ioc->name, ioc->pdev->subsystem_device);
2711 break;
2712 }
38e4141e
SR		 2713 break;
2714 default:
2715 pr_info(MPT3SAS_FMT
989e43c7
SR		 2716 "Cisco SAS HBA: Subsystem ID: 0x%X\n",
2717 ioc->name, ioc->pdev->subsystem_device);
38e4141e
SR		 2718 break;
2719 }
2720 break;
989e43c7
SR		 2721 case MPT2SAS_HP_3PAR_SSVID:
2722 switch (ioc->pdev->device) {
2723 case MPI2_MFGPAGE_DEVID_SAS2004:
2724 switch (ioc->pdev->subsystem_device) {
2725 case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
2726 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2727 MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
2728 break;
2729 default:
2730 pr_info(MPT3SAS_FMT
2731 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
2732 ioc->name, ioc->pdev->subsystem_device);
2733 break;
2734 }
2735 case MPI2_MFGPAGE_DEVID_SAS2308_2:
2736 switch (ioc->pdev->subsystem_device) {
2737 case MPT2SAS_HP_2_4_INTERNAL_SSDID:
2738 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2739 MPT2SAS_HP_2_4_INTERNAL_BRANDING);
2740 break;
2741 case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
2742 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2743 MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
2744 break;
2745 case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
2746 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2747 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
2748 break;
2749 case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
2750 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2751 MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
2752 break;
2753 default:
2754 pr_info(MPT3SAS_FMT
2755 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
2756 ioc->name, ioc->pdev->subsystem_device);
2757 break;
2758 }
d8eb4a47
SR		 2759 default:
2760 pr_info(MPT3SAS_FMT
989e43c7
SR		 2761 "HP SAS HBA: Subsystem ID: 0x%X\n",
2762 ioc->name, ioc->pdev->subsystem_device);
d8eb4a47
SR		 2763 break;
2764 }
38e4141e 2765 default:
38e4141e
SR		 2766 break;
2767 }
2768}
fb84dfc4 2769
f92363d1
SR		 2770/**
2771 * _base_display_ioc_capabilities - Disply IOC's capabilities.
2772 * @ioc: per adapter object
2773 *
2774 * Return nothing.
2775 */
2776static void
2777_base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
2778{
2779 int i = 0;
2780 char desc[16];
2781 u32 iounit_pg1_flags;
2782 u32 bios_version;
2783
2784 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
2785 strncpy(desc, ioc->manu_pg0.ChipName, 16);
2786 pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
2787 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
2788 ioc->name, desc,
2789 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
2790 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
2791 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
2792 ioc->facts.FWVersion.Word & 0x000000FF,
2793 ioc->pdev->revision,
2794 (bios_version & 0xFF000000) >> 24,
2795 (bios_version & 0x00FF0000) >> 16,
2796 (bios_version & 0x0000FF00) >> 8,
2797 bios_version & 0x000000FF);
2798
989e43c7 2799 _base_display_OEMs_branding(ioc);
1117b31a 2800
f92363d1
SR		 2801 pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
2802
2803 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
2804 pr_info("Initiator");
2805 i++;
2806 }
2807
2808 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
2809 pr_info("%sTarget", i ? "," : "");
2810 i++;
2811 }
2812
2813 i = 0;
2814 pr_info("), ");
2815 pr_info("Capabilities=(");
2816
7786ab6a
SR		 2817 if (!ioc->hide_ir_msg) {
2818 if (ioc->facts.IOCCapabilities &
f92363d1
SR		 2819 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
2820 pr_info("Raid");
2821 i++;
7786ab6a 2822 }
f92363d1
SR		 2823 }
2824
2825 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
2826 pr_info("%sTLR", i ? "," : "");
2827 i++;
2828 }
2829
2830 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
2831 pr_info("%sMulticast", i ? "," : "");
2832 i++;
2833 }
2834
2835 if (ioc->facts.IOCCapabilities &
2836 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
2837 pr_info("%sBIDI Target", i ? "," : "");
2838 i++;
2839 }
2840
2841 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
2842 pr_info("%sEEDP", i ? "," : "");
2843 i++;
2844 }
2845
2846 if (ioc->facts.IOCCapabilities &
2847 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
2848 pr_info("%sSnapshot Buffer", i ? "," : "");
2849 i++;
2850 }
2851
2852 if (ioc->facts.IOCCapabilities &
2853 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
2854 pr_info("%sDiag Trace Buffer", i ? "," : "");
2855 i++;
2856 }
2857
2858 if (ioc->facts.IOCCapabilities &
2859 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
2860 pr_info("%sDiag Extended Buffer", i ? "," : "");
2861 i++;
2862 }
2863
2864 if (ioc->facts.IOCCapabilities &
2865 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
2866 pr_info("%sTask Set Full", i ? "," : "");
2867 i++;
2868 }
2869
2870 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2871 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
2872 pr_info("%sNCQ", i ? "," : "");
2873 i++;
2874 }
2875
2876 pr_info(")\n");
2877}
2878
2879/**
2880 * mpt3sas_base_update_missing_delay - change the missing delay timers
2881 * @ioc: per adapter object
2882 * @device_missing_delay: amount of time till device is reported missing
2883 * @io_missing_delay: interval IO is returned when there is a missing device
2884 *
2885 * Return nothing.
2886 *
2887 * Passed on the command line, this function will modify the device missing
2888 * delay, as well as the io missing delay. This should be called at driver
2889 * load time.
2890 */
2891void
2892mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
2893 u16 device_missing_delay, u8 io_missing_delay)
2894{
2895 u16 dmd, dmd_new, dmd_orignal;
2896 u8 io_missing_delay_original;
2897 u16 sz;
2898 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
2899 Mpi2ConfigReply_t mpi_reply;
2900 u8 num_phys = 0;
2901 u16 ioc_status;
2902
2903 mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
2904 if (!num_phys)
2905 return;
2906
2907 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
2908 sizeof(Mpi2SasIOUnit1PhyData_t));
2909 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
2910 if (!sas_iounit_pg1) {
2911 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2912 ioc->name, __FILE__, __LINE__, __func__);
2913 goto out;
2914 }
2915 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
2916 sas_iounit_pg1, sz))) {
2917 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2918 ioc->name, __FILE__, __LINE__, __func__);
2919 goto out;
2920 }
2921 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
2922 MPI2_IOCSTATUS_MASK;
2923 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
2924 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2925 ioc->name, __FILE__, __LINE__, __func__);
2926 goto out;
2927 }
2928
2929 /* device missing delay */
2930 dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
2931 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2932 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2933 else
2934 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2935 dmd_orignal = dmd;
2936 if (device_missing_delay > 0x7F) {
2937 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
2938 device_missing_delay;
2939 dmd = dmd / 16;
2940 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
2941 } else
2942 dmd = device_missing_delay;
2943 sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
2944
2945 /* io missing delay */
2946 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
2947 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
2948
2949 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
2950 sz)) {
2951 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2952 dmd_new = (dmd &
2953 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2954 else
2955 dmd_new =
2956 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2957 pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
2958 ioc->name, dmd_orignal, dmd_new);
2959 pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
2960 ioc->name, io_missing_delay_original,
2961 io_missing_delay);
2962 ioc->device_missing_delay = dmd_new;
2963 ioc->io_missing_delay = io_missing_delay;
2964 }
2965
2966out:
2967 kfree(sas_iounit_pg1);
2968}
2969/**
2970 * _base_static_config_pages - static start of day config pages
2971 * @ioc: per adapter object
2972 *
2973 * Return nothing.
2974 */
2975static void
2976_base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
2977{
2978 Mpi2ConfigReply_t mpi_reply;
2979 u32 iounit_pg1_flags;
2980
2981 mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
2982 if (ioc->ir_firmware)
2983 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
2984 &ioc->manu_pg10);
2985
2986 /*
2987 * Ensure correct T10 PI operation if vendor left EEDPTagMode
2988 * flag unset in NVDATA.
2989 */
2990 mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
2991 if (ioc->manu_pg11.EEDPTagMode == 0) {
2992 pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
2993 ioc->name);
2994 ioc->manu_pg11.EEDPTagMode &= ~0x3;
2995 ioc->manu_pg11.EEDPTagMode |= 0x1;
2996 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
2997 &ioc->manu_pg11);
2998 }
2999
3000 mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
3001 mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
3002 mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
3003 mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
3004 mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2d8ce8c9 3005 mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
f92363d1
SR		 3006 _base_display_ioc_capabilities(ioc);
3007
3008 /*
3009 * Enable task_set_full handling in iounit_pg1 when the
3010 * facts capabilities indicate that its supported.
3011 */
3012 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
3013 if ((ioc->facts.IOCCapabilities &
3014 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
3015 iounit_pg1_flags &=
3016 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3017 else
3018 iounit_pg1_flags |=
3019 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3020 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
3021 mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2d8ce8c9
SR		 3022
3023 if (ioc->iounit_pg8.NumSensors)
3024 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
f92363d1
SR		 3025}
3026
3027/**
3028 * _base_release_memory_pools - release memory
3029 * @ioc: per adapter object
3030 *
3031 * Free memory allocated from _base_allocate_memory_pools.
3032 *
3033 * Return nothing.
3034 */
3035static void
3036_base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
3037{
9b05c91a
SR		 3038 int i = 0;
3039 struct reply_post_struct *rps;
f92363d1
SR		 3040
3041 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3042 __func__));
3043
3044 if (ioc->request) {
3045 pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
3046 ioc->request, ioc->request_dma);
3047 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3048 "request_pool(0x%p): free\n",
3049 ioc->name, ioc->request));
3050 ioc->request = NULL;
3051 }
3052
3053 if (ioc->sense) {
3054 pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
3055 if (ioc->sense_dma_pool)
3056 pci_pool_destroy(ioc->sense_dma_pool);
3057 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3058 "sense_pool(0x%p): free\n",
3059 ioc->name, ioc->sense));
3060 ioc->sense = NULL;
3061 }
3062
3063 if (ioc->reply) {
3064 pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
3065 if (ioc->reply_dma_pool)
3066 pci_pool_destroy(ioc->reply_dma_pool);
3067 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3068 "reply_pool(0x%p): free\n",
3069 ioc->name, ioc->reply));
3070 ioc->reply = NULL;
3071 }
3072
3073 if (ioc->reply_free) {
3074 pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
3075 ioc->reply_free_dma);
3076 if (ioc->reply_free_dma_pool)
3077 pci_pool_destroy(ioc->reply_free_dma_pool);
3078 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3079 "reply_free_pool(0x%p): free\n",
3080 ioc->name, ioc->reply_free));
3081 ioc->reply_free = NULL;
3082 }
3083
9b05c91a
SR		 3084 if (ioc->reply_post) {
3085 do {
3086 rps = &ioc->reply_post[i];
3087 if (rps->reply_post_free) {
3088 pci_pool_free(
3089 ioc->reply_post_free_dma_pool,
3090 rps->reply_post_free,
3091 rps->reply_post_free_dma);
3092 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3093 "reply_post_free_pool(0x%p): free\n",
3094 ioc->name, rps->reply_post_free));
3095 rps->reply_post_free = NULL;
3096 }
3097 } while (ioc->rdpq_array_enable &&
3098 (++i < ioc->reply_queue_count));
3099
f92363d1
SR		 3100 if (ioc->reply_post_free_dma_pool)
3101 pci_pool_destroy(ioc->reply_post_free_dma_pool);
9b05c91a 3102 kfree(ioc->reply_post);
f92363d1
SR		 3103 }
3104
3105 if (ioc->config_page) {
3106 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3107 "config_page(0x%p): free\n", ioc->name,
3108 ioc->config_page));
3109 pci_free_consistent(ioc->pdev, ioc->config_page_sz,
3110 ioc->config_page, ioc->config_page_dma);
3111 }
3112
3113 if (ioc->scsi_lookup) {
3114 free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
3115 ioc->scsi_lookup = NULL;
3116 }
3117 kfree(ioc->hpr_lookup);
3118 kfree(ioc->internal_lookup);
3119 if (ioc->chain_lookup) {
3120 for (i = 0; i < ioc->chain_depth; i++) {
3121 if (ioc->chain_lookup[i].chain_buffer)
3122 pci_pool_free(ioc->chain_dma_pool,
3123 ioc->chain_lookup[i].chain_buffer,
3124 ioc->chain_lookup[i].chain_buffer_dma);
3125 }
3126 if (ioc->chain_dma_pool)
3127 pci_pool_destroy(ioc->chain_dma_pool);
3128 free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
3129 ioc->chain_lookup = NULL;
3130 }
3131}
3132
3133/**
3134 * _base_allocate_memory_pools - allocate start of day memory pools
3135 * @ioc: per adapter object
3136 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3137 *
3138 * Returns 0 success, anything else error
3139 */
3140static int
3141_base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
3142{
3143 struct mpt3sas_facts *facts;
3144 u16 max_sge_elements;
3145 u16 chains_needed_per_io;
3146 u32 sz, total_sz, reply_post_free_sz;
3147 u32 retry_sz;
3148 u16 max_request_credit;
3149 unsigned short sg_tablesize;
3150 u16 sge_size;
3151 int i;
3152
3153 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3154 __func__));
3155
3156
3157 retry_sz = 0;
3158 facts = &ioc->facts;
3159
3160 /* command line tunables for max sgl entries */
3161 if (max_sgl_entries != -1)
3162 sg_tablesize = max_sgl_entries;
471ef9d4
SR		 3163 else {
3164 if (ioc->hba_mpi_version_belonged == MPI2_VERSION)
3165 sg_tablesize = MPT2SAS_SG_DEPTH;
3166 else
3167 sg_tablesize = MPT3SAS_SG_DEPTH;
3168 }
f92363d1 3169
8a7e4c24
SR		 3170 if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS)
3171 sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
3172 else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
ad666a0f
SR		 3173 sg_tablesize = min_t(unsigned short, sg_tablesize,
3174 SCSI_MAX_SG_CHAIN_SEGMENTS);
3175 pr_warn(MPT3SAS_FMT
3176 "sg_tablesize(%u) is bigger than kernel"
3177 " defined SCSI_MAX_SG_SEGMENTS(%u)\n", ioc->name,
8a7e4c24 3178 sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
ad666a0f 3179 }
f92363d1
SR		 3180 ioc->shost->sg_tablesize = sg_tablesize;
3181
3182 ioc->hi_priority_depth = facts->HighPriorityCredit;
3183 ioc->internal_depth = ioc->hi_priority_depth + (5);
3184 /* command line tunables for max controller queue depth */
3185 if (max_queue_depth != -1 && max_queue_depth != 0) {
3186 max_request_credit = min_t(u16, max_queue_depth +
3187 ioc->hi_priority_depth + ioc->internal_depth,
3188 facts->RequestCredit);
3189 if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
3190 max_request_credit = MAX_HBA_QUEUE_DEPTH;
3191 } else
3192 max_request_credit = min_t(u16, facts->RequestCredit,
3193 MAX_HBA_QUEUE_DEPTH);
3194
3195 ioc->hba_queue_depth = max_request_credit;
3196
3197 /* request frame size */
3198 ioc->request_sz = facts->IOCRequestFrameSize * 4;
3199
3200 /* reply frame size */
3201 ioc->reply_sz = facts->ReplyFrameSize * 4;
3202
3203 /* calculate the max scatter element size */
3204 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
3205
3206 retry_allocation:
3207 total_sz = 0;
3208 /* calculate number of sg elements left over in the 1st frame */
3209 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
3210 sizeof(Mpi2SGEIOUnion_t)) + sge_size);
3211 ioc->max_sges_in_main_message = max_sge_elements/sge_size;
3212
3213 /* now do the same for a chain buffer */
3214 max_sge_elements = ioc->request_sz - sge_size;
3215 ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
3216
3217 /*
3218 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
3219 */
3220 chains_needed_per_io = ((ioc->shost->sg_tablesize -
3221 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
3222 + 1;
3223 if (chains_needed_per_io > facts->MaxChainDepth) {
3224 chains_needed_per_io = facts->MaxChainDepth;
3225 ioc->shost->sg_tablesize = min_t(u16,
3226 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
3227 * chains_needed_per_io), ioc->shost->sg_tablesize);
3228 }
3229 ioc->chains_needed_per_io = chains_needed_per_io;
3230
3231 /* reply free queue sizing - taking into account for 64 FW events */
3232 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3233
3234 /* calculate reply descriptor post queue depth */
3235 ioc->reply_post_queue_depth = ioc->hba_queue_depth +
3236 ioc->reply_free_queue_depth + 1 ;
3237 /* align the reply post queue on the next 16 count boundary */
3238 if (ioc->reply_post_queue_depth % 16)
3239 ioc->reply_post_queue_depth += 16 -
3240 (ioc->reply_post_queue_depth % 16);
3241
3242
3243 if (ioc->reply_post_queue_depth >
3244 facts->MaxReplyDescriptorPostQueueDepth) {
3245 ioc->reply_post_queue_depth =
3246 facts->MaxReplyDescriptorPostQueueDepth -
3247 (facts->MaxReplyDescriptorPostQueueDepth % 16);
3248 ioc->hba_queue_depth =
3249 ((ioc->reply_post_queue_depth - 64) / 2) - 1;
3250 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3251 }
3252
3253 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
3254 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
3255 "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
3256 ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
3257 ioc->chains_needed_per_io));
3258
9b05c91a
SR		 3259 /* reply post queue, 16 byte align */
3260 reply_post_free_sz = ioc->reply_post_queue_depth *
3261 sizeof(Mpi2DefaultReplyDescriptor_t);
3262
3263 sz = reply_post_free_sz;
3264 if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
3265 sz *= ioc->reply_queue_count;
3266
3267 ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
3268 (ioc->reply_queue_count):1,
3269 sizeof(struct reply_post_struct), GFP_KERNEL);
3270
3271 if (!ioc->reply_post) {
3272 pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n",
3273 ioc->name);
3274 goto out;
3275 }
3276 ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
3277 ioc->pdev, sz, 16, 0);
3278 if (!ioc->reply_post_free_dma_pool) {
3279 pr_err(MPT3SAS_FMT
3280 "reply_post_free pool: pci_pool_create failed\n",
3281 ioc->name);
3282 goto out;
3283 }
3284 i = 0;
3285 do {
3286 ioc->reply_post[i].reply_post_free =
3287 pci_pool_alloc(ioc->reply_post_free_dma_pool,
3288 GFP_KERNEL,
3289 &ioc->reply_post[i].reply_post_free_dma);
3290 if (!ioc->reply_post[i].reply_post_free) {
3291 pr_err(MPT3SAS_FMT
3292 "reply_post_free pool: pci_pool_alloc failed\n",
3293 ioc->name);
3294 goto out;
3295 }
3296 memset(ioc->reply_post[i].reply_post_free, 0, sz);
3297 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3298 "reply post free pool (0x%p): depth(%d),"
3299 "element_size(%d), pool_size(%d kB)\n", ioc->name,
3300 ioc->reply_post[i].reply_post_free,
3301 ioc->reply_post_queue_depth, 8, sz/1024));
3302 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3303 "reply_post_free_dma = (0x%llx)\n", ioc->name,
3304 (unsigned long long)
3305 ioc->reply_post[i].reply_post_free_dma));
3306 total_sz += sz;
3307 } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
3308
3309 if (ioc->dma_mask == 64) {
3310 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
3311 pr_warn(MPT3SAS_FMT
3312 "no suitable consistent DMA mask for %s\n",
3313 ioc->name, pci_name(ioc->pdev));
3314 goto out;
3315 }
3316 }
3317
f92363d1
SR		 3318 ioc->scsiio_depth = ioc->hba_queue_depth -
3319 ioc->hi_priority_depth - ioc->internal_depth;
3320
3321 /* set the scsi host can_queue depth
3322 * with some internal commands that could be outstanding
3323 */
3324 ioc->shost->can_queue = ioc->scsiio_depth;
3325 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3326 "scsi host: can_queue depth (%d)\n",
3327 ioc->name, ioc->shost->can_queue));
3328
3329
3330 /* contiguous pool for request and chains, 16 byte align, one extra "
3331 * "frame for smid=0
3332 */
3333 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
3334 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
3335
3336 /* hi-priority queue */
3337 sz += (ioc->hi_priority_depth * ioc->request_sz);
3338
3339 /* internal queue */
3340 sz += (ioc->internal_depth * ioc->request_sz);
3341
3342 ioc->request_dma_sz = sz;
3343 ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
3344 if (!ioc->request) {
3345 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3346 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3347 "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
3348 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3349 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
3350 goto out;
3351 retry_sz += 64;
3352 ioc->hba_queue_depth = max_request_credit - retry_sz;
3353 goto retry_allocation;
3354 }
3355
3356 if (retry_sz)
3357 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3358 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3359 "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
3360 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3361
3362 /* hi-priority queue */
3363 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
3364 ioc->request_sz);
3365 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
3366 ioc->request_sz);
3367
3368 /* internal queue */
3369 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
3370 ioc->request_sz);
3371 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
3372 ioc->request_sz);
3373
3374 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3375 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3376 ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
3377 (ioc->hba_queue_depth * ioc->request_sz)/1024));
3378
3379 dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
3380 ioc->name, (unsigned long long) ioc->request_dma));
3381 total_sz += sz;
3382
3383 sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
3384 ioc->scsi_lookup_pages = get_order(sz);
3385 ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
3386 GFP_KERNEL, ioc->scsi_lookup_pages);
3387 if (!ioc->scsi_lookup) {
3388 pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n",
3389 ioc->name, (int)sz);
3390 goto out;
3391 }
3392
3393 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
3394 ioc->name, ioc->request, ioc->scsiio_depth));
3395
3396 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
3397 sz = ioc->chain_depth * sizeof(struct chain_tracker);
3398 ioc->chain_pages = get_order(sz);
3399 ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
3400 GFP_KERNEL, ioc->chain_pages);
3401 if (!ioc->chain_lookup) {
3402 pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n",
3403 ioc->name);
3404 goto out;
3405 }
3406 ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev,
3407 ioc->request_sz, 16, 0);
3408 if (!ioc->chain_dma_pool) {
3409 pr_err(MPT3SAS_FMT "chain_dma_pool: pci_pool_create failed\n",
3410 ioc->name);
3411 goto out;
3412 }
3413 for (i = 0; i < ioc->chain_depth; i++) {
3414 ioc->chain_lookup[i].chain_buffer = pci_pool_alloc(
3415 ioc->chain_dma_pool , GFP_KERNEL,
3416 &ioc->chain_lookup[i].chain_buffer_dma);
3417 if (!ioc->chain_lookup[i].chain_buffer) {
3418 ioc->chain_depth = i;
3419 goto chain_done;
3420 }
3421 total_sz += ioc->request_sz;
3422 }
3423 chain_done:
3424 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3425 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
3426 ioc->name, ioc->chain_depth, ioc->request_sz,
3427 ((ioc->chain_depth * ioc->request_sz))/1024));
3428
3429 /* initialize hi-priority queue smid's */
3430 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
3431 sizeof(struct request_tracker), GFP_KERNEL);
3432 if (!ioc->hpr_lookup) {
3433 pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
3434 ioc->name);
3435 goto out;
3436 }
3437 ioc->hi_priority_smid = ioc->scsiio_depth + 1;
3438 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3439 "hi_priority(0x%p): depth(%d), start smid(%d)\n",
3440 ioc->name, ioc->hi_priority,
3441 ioc->hi_priority_depth, ioc->hi_priority_smid));
3442
3443 /* initialize internal queue smid's */
3444 ioc->internal_lookup = kcalloc(ioc->internal_depth,
3445 sizeof(struct request_tracker), GFP_KERNEL);
3446 if (!ioc->internal_lookup) {
3447 pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
3448 ioc->name);
3449 goto out;
3450 }
3451 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
3452 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3453 "internal(0x%p): depth(%d), start smid(%d)\n",
3454 ioc->name, ioc->internal,
3455 ioc->internal_depth, ioc->internal_smid));
3456
3457 /* sense buffers, 4 byte align */
3458 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
3459 ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
3460 0);
3461 if (!ioc->sense_dma_pool) {
3462 pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n",
3463 ioc->name);
3464 goto out;
3465 }
3466 ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
3467 &ioc->sense_dma);
3468 if (!ioc->sense) {
3469 pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n",
3470 ioc->name);
3471 goto out;
3472 }
3473 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3474 "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
3475 "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
3476 SCSI_SENSE_BUFFERSIZE, sz/1024));
3477 dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
3478 ioc->name, (unsigned long long)ioc->sense_dma));
3479 total_sz += sz;
3480
3481 /* reply pool, 4 byte align */
3482 sz = ioc->reply_free_queue_depth * ioc->reply_sz;
3483 ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
3484 0);
3485 if (!ioc->reply_dma_pool) {
3486 pr_err(MPT3SAS_FMT "reply pool: pci_pool_create failed\n",
3487 ioc->name);
3488 goto out;
3489 }
3490 ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
3491 &ioc->reply_dma);
3492 if (!ioc->reply) {
3493 pr_err(MPT3SAS_FMT "reply pool: pci_pool_alloc failed\n",
3494 ioc->name);
3495 goto out;
3496 }
3497 ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
3498 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
3499 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3500 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3501 ioc->name, ioc->reply,
3502 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
3503 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
3504 ioc->name, (unsigned long long)ioc->reply_dma));
3505 total_sz += sz;
3506
3507 /* reply free queue, 16 byte align */
3508 sz = ioc->reply_free_queue_depth * 4;
3509 ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
3510 ioc->pdev, sz, 16, 0);
3511 if (!ioc->reply_free_dma_pool) {
3512 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_create failed\n",
3513 ioc->name);
3514 goto out;
3515 }
3516 ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
3517 &ioc->reply_free_dma);
3518 if (!ioc->reply_free) {
3519 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_alloc failed\n",
3520 ioc->name);
3521 goto out;
3522 }
3523 memset(ioc->reply_free, 0, sz);
3524 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
3525 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
3526 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
3527 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3528 "reply_free_dma (0x%llx)\n",
3529 ioc->name, (unsigned long long)ioc->reply_free_dma));
3530 total_sz += sz;
3531
f92363d1
SR		 3532 ioc->config_page_sz = 512;
3533 ioc->config_page = pci_alloc_consistent(ioc->pdev,
3534 ioc->config_page_sz, &ioc->config_page_dma);
3535 if (!ioc->config_page) {
3536 pr_err(MPT3SAS_FMT
3537 "config page: pci_pool_alloc failed\n",
3538 ioc->name);
3539 goto out;
3540 }
3541 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3542 "config page(0x%p): size(%d)\n",
3543 ioc->name, ioc->config_page, ioc->config_page_sz));
3544 dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
3545 ioc->name, (unsigned long long)ioc->config_page_dma));
3546 total_sz += ioc->config_page_sz;
3547
3548 pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
3549 ioc->name, total_sz/1024);
3550 pr_info(MPT3SAS_FMT
3551 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
3552 ioc->name, ioc->shost->can_queue, facts->RequestCredit);
3553 pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
3554 ioc->name, ioc->shost->sg_tablesize);
3555 return 0;
3556
3557 out:
3558 return -ENOMEM;
3559}
3560
3561/**
3562 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
3563 * @ioc: Pointer to MPT_ADAPTER structure
3564 * @cooked: Request raw or cooked IOC state
3565 *
3566 * Returns all IOC Doorbell register bits if cooked==0, else just the
3567 * Doorbell bits in MPI_IOC_STATE_MASK.
3568 */
3569u32
3570mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
3571{
3572 u32 s, sc;
3573
3574 s = readl(&ioc->chip->Doorbell);
3575 sc = s & MPI2_IOC_STATE_MASK;
3576 return cooked ? sc : s;
3577}
3578
3579/**
3580 * _base_wait_on_iocstate - waiting on a particular ioc state
3581 * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
3582 * @timeout: timeout in second
3583 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3584 *
3585 * Returns 0 for success, non-zero for failure.
3586 */
3587static int
3588_base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout,
3589 int sleep_flag)
3590{
3591 u32 count, cntdn;
3592 u32 current_state;
3593
3594 count = 0;
3595 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3596 do {
3597 current_state = mpt3sas_base_get_iocstate(ioc, 1);
3598 if (current_state == ioc_state)
3599 return 0;
3600 if (count && current_state == MPI2_IOC_STATE_FAULT)
3601 break;
3602 if (sleep_flag == CAN_SLEEP)
3603 usleep_range(1000, 1500);
3604 else
3605 udelay(500);
3606 count++;
3607 } while (--cntdn);
3608
3609 return current_state;
3610}
3611
3612/**
3613 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
3614 * a write to the doorbell)
3615 * @ioc: per adapter object
3616 * @timeout: timeout in second
3617 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3618 *
3619 * Returns 0 for success, non-zero for failure.
3620 *
3621 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
3622 */
4dc8c808
SR		 3623static int
3624_base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag);
3625
f92363d1
SR		 3626static int
3627_base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout,
3628 int sleep_flag)
3629{
3630 u32 cntdn, count;
3631 u32 int_status;
3632
3633 count = 0;
3634 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3635 do {
3636 int_status = readl(&ioc->chip->HostInterruptStatus);
3637 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3638 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3639 "%s: successful count(%d), timeout(%d)\n",
3640 ioc->name, __func__, count, timeout));
3641 return 0;
3642 }
3643 if (sleep_flag == CAN_SLEEP)
3644 usleep_range(1000, 1500);
3645 else
3646 udelay(500);
3647 count++;
3648 } while (--cntdn);
3649
3650 pr_err(MPT3SAS_FMT
3651 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3652 ioc->name, __func__, count, int_status);
3653 return -EFAULT;
3654}
3655
3656/**
3657 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
3658 * @ioc: per adapter object
3659 * @timeout: timeout in second
3660 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3661 *
3662 * Returns 0 for success, non-zero for failure.
3663 *
3664 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
3665 * doorbell.
3666 */
3667static int
3668_base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout,
3669 int sleep_flag)
3670{
3671 u32 cntdn, count;
3672 u32 int_status;
3673 u32 doorbell;
3674
3675 count = 0;
3676 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3677 do {
3678 int_status = readl(&ioc->chip->HostInterruptStatus);
3679 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
3680 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3681 "%s: successful count(%d), timeout(%d)\n",
3682 ioc->name, __func__, count, timeout));
3683 return 0;
3684 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3685 doorbell = readl(&ioc->chip->Doorbell);
3686 if ((doorbell & MPI2_IOC_STATE_MASK) ==
3687 MPI2_IOC_STATE_FAULT) {
3688 mpt3sas_base_fault_info(ioc , doorbell);
3689 return -EFAULT;
3690 }
3691 } else if (int_status == 0xFFFFFFFF)
3692 goto out;
3693
3694 if (sleep_flag == CAN_SLEEP)
3695 usleep_range(1000, 1500);
3696 else
3697 udelay(500);
3698 count++;
3699 } while (--cntdn);
3700
3701 out:
3702 pr_err(MPT3SAS_FMT
3703 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3704 ioc->name, __func__, count, int_status);
3705 return -EFAULT;
3706}
3707
3708/**
3709 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
3710 * @ioc: per adapter object
3711 * @timeout: timeout in second
3712 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3713 *
3714 * Returns 0 for success, non-zero for failure.
3715 *
3716 */
3717static int
3718_base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout,
3719 int sleep_flag)
3720{
3721 u32 cntdn, count;
3722 u32 doorbell_reg;
3723
3724 count = 0;
3725 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3726 do {
3727 doorbell_reg = readl(&ioc->chip->Doorbell);
3728 if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
3729 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3730 "%s: successful count(%d), timeout(%d)\n",
3731 ioc->name, __func__, count, timeout));
3732 return 0;
3733 }
3734 if (sleep_flag == CAN_SLEEP)
3735 usleep_range(1000, 1500);
3736 else
3737 udelay(500);
3738 count++;
3739 } while (--cntdn);
3740
3741 pr_err(MPT3SAS_FMT
3742 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
3743 ioc->name, __func__, count, doorbell_reg);
3744 return -EFAULT;
3745}
3746
3747/**
3748 * _base_send_ioc_reset - send doorbell reset
3749 * @ioc: per adapter object
3750 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
3751 * @timeout: timeout in second
3752 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3753 *
3754 * Returns 0 for success, non-zero for failure.
3755 */
3756static int
3757_base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout,
3758 int sleep_flag)
3759{
3760 u32 ioc_state;
3761 int r = 0;
3762
3763 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
3764 pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
3765 ioc->name, __func__);
3766 return -EFAULT;
3767 }
3768
3769 if (!(ioc->facts.IOCCapabilities &
3770 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
3771 return -EFAULT;
3772
3773 pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
3774
3775 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
3776 &ioc->chip->Doorbell);
3777 if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) {
3778 r = -EFAULT;
3779 goto out;
3780 }
3781 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
3782 timeout, sleep_flag);
3783 if (ioc_state) {
3784 pr_err(MPT3SAS_FMT
3785 "%s: failed going to ready state (ioc_state=0x%x)\n",
3786 ioc->name, __func__, ioc_state);
3787 r = -EFAULT;
3788 goto out;
3789 }
3790 out:
3791 pr_info(MPT3SAS_FMT "message unit reset: %s\n",
3792 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
3793 return r;
3794}
3795
3796/**
3797 * _base_handshake_req_reply_wait - send request thru doorbell interface
3798 * @ioc: per adapter object
3799 * @request_bytes: request length
3800 * @request: pointer having request payload
3801 * @reply_bytes: reply length
3802 * @reply: pointer to reply payload
3803 * @timeout: timeout in second
3804 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3805 *
3806 * Returns 0 for success, non-zero for failure.
3807 */
3808static int
3809_base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
3810 u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag)
3811{
3812 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
3813 int i;
3814 u8 failed;
3815 u16 dummy;
3816 __le32 *mfp;
3817
3818 /* make sure doorbell is not in use */
3819 if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
3820 pr_err(MPT3SAS_FMT
3821 "doorbell is in use (line=%d)\n",
3822 ioc->name, __LINE__);
3823 return -EFAULT;
3824 }
3825
3826 /* clear pending doorbell interrupts from previous state changes */
3827 if (readl(&ioc->chip->HostInterruptStatus) &
3828 MPI2_HIS_IOC2SYS_DB_STATUS)
3829 writel(0, &ioc->chip->HostInterruptStatus);
3830
3831 /* send message to ioc */
3832 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
3833 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
3834 &ioc->chip->Doorbell);
3835
3836 if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) {
3837 pr_err(MPT3SAS_FMT
3838 "doorbell handshake int failed (line=%d)\n",
3839 ioc->name, __LINE__);
3840 return -EFAULT;
3841 }
3842 writel(0, &ioc->chip->HostInterruptStatus);
3843
3844 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) {
3845 pr_err(MPT3SAS_FMT
3846 "doorbell handshake ack failed (line=%d)\n",
3847 ioc->name, __LINE__);
3848 return -EFAULT;
3849 }
3850
3851 /* send message 32-bits at a time */
3852 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
3853 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
3854 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag)))
3855 failed = 1;
3856 }
3857
3858 if (failed) {
3859 pr_err(MPT3SAS_FMT
3860 "doorbell handshake sending request failed (line=%d)\n",
3861 ioc->name, __LINE__);
3862 return -EFAULT;
3863 }
3864
3865 /* now wait for the reply */
3866 if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) {
3867 pr_err(MPT3SAS_FMT
3868 "doorbell handshake int failed (line=%d)\n",
3869 ioc->name, __LINE__);
3870 return -EFAULT;
3871 }
3872
3873 /* read the first two 16-bits, it gives the total length of the reply */
3874 reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3875 & MPI2_DOORBELL_DATA_MASK);
3876 writel(0, &ioc->chip->HostInterruptStatus);
3877 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3878 pr_err(MPT3SAS_FMT
3879 "doorbell handshake int failed (line=%d)\n",
3880 ioc->name, __LINE__);
3881 return -EFAULT;
3882 }
3883 reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3884 & MPI2_DOORBELL_DATA_MASK);
3885 writel(0, &ioc->chip->HostInterruptStatus);
3886
3887 for (i = 2; i < default_reply->MsgLength * 2; i++) {
3888 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3889 pr_err(MPT3SAS_FMT
3890 "doorbell handshake int failed (line=%d)\n",
3891 ioc->name, __LINE__);
3892 return -EFAULT;
3893 }
3894 if (i >= reply_bytes/2) /* overflow case */
3895 dummy = readl(&ioc->chip->Doorbell);
3896 else
3897 reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3898 & MPI2_DOORBELL_DATA_MASK);
3899 writel(0, &ioc->chip->HostInterruptStatus);
3900 }
3901
3902 _base_wait_for_doorbell_int(ioc, 5, sleep_flag);
3903 if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) {
3904 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3905 "doorbell is in use (line=%d)\n", ioc->name, __LINE__));
3906 }
3907 writel(0, &ioc->chip->HostInterruptStatus);
3908
3909 if (ioc->logging_level & MPT_DEBUG_INIT) {
3910 mfp = (__le32 *)reply;
3911 pr_info("\toffset:data\n");
3912 for (i = 0; i < reply_bytes/4; i++)
3913 pr_info("\t[0x%02x]:%08x\n", i*4,
3914 le32_to_cpu(mfp[i]));
3915 }
3916 return 0;
3917}
3918
3919/**
3920 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
3921 * @ioc: per adapter object
3922 * @mpi_reply: the reply payload from FW
3923 * @mpi_request: the request payload sent to FW
3924 *
3925 * The SAS IO Unit Control Request message allows the host to perform low-level
3926 * operations, such as resets on the PHYs of the IO Unit, also allows the host
3927 * to obtain the IOC assigned device handles for a device if it has other
3928 * identifying information about the device, in addition allows the host to
3929 * remove IOC resources associated with the device.
3930 *
3931 * Returns 0 for success, non-zero for failure.
3932 */
3933int
3934mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
3935 Mpi2SasIoUnitControlReply_t *mpi_reply,
3936 Mpi2SasIoUnitControlRequest_t *mpi_request)
3937{
3938 u16 smid;
3939 u32 ioc_state;
3940 unsigned long timeleft;
eb44552b 3941 bool issue_reset = false;
f92363d1
SR		 3942 int rc;
3943 void *request;
3944 u16 wait_state_count;
3945
3946 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3947 __func__));
3948
3949 mutex_lock(&ioc->base_cmds.mutex);
3950
3951 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
3952 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
3953 ioc->name, __func__);
3954 rc = -EAGAIN;
3955 goto out;
3956 }
3957
3958 wait_state_count = 0;
3959 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3960 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
3961 if (wait_state_count++ == 10) {
3962 pr_err(MPT3SAS_FMT
3963 "%s: failed due to ioc not operational\n",
3964 ioc->name, __func__);
3965 rc = -EFAULT;
3966 goto out;
3967 }
3968 ssleep(1);
3969 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3970 pr_info(MPT3SAS_FMT
3971 "%s: waiting for operational state(count=%d)\n",
3972 ioc->name, __func__, wait_state_count);
3973 }
3974
3975 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
3976 if (!smid) {
3977 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
3978 ioc->name, __func__);
3979 rc = -EAGAIN;
3980 goto out;
3981 }
3982
3983 rc = 0;
3984 ioc->base_cmds.status = MPT3_CMD_PENDING;
3985 request = mpt3sas_base_get_msg_frame(ioc, smid);
3986 ioc->base_cmds.smid = smid;
3987 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
3988 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
3989 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
3990 ioc->ioc_link_reset_in_progress = 1;
3991 init_completion(&ioc->base_cmds.done);
3992 mpt3sas_base_put_smid_default(ioc, smid);
3993 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
3994 msecs_to_jiffies(10000));
3995 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
3996 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
3997 ioc->ioc_link_reset_in_progress)
3998 ioc->ioc_link_reset_in_progress = 0;
3999 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4000 pr_err(MPT3SAS_FMT "%s: timeout\n",
4001 ioc->name, __func__);
4002 _debug_dump_mf(mpi_request,
4003 sizeof(Mpi2SasIoUnitControlRequest_t)/4);
4004 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
eb44552b 4005 issue_reset = true;
f92363d1
SR		 4006 goto issue_host_reset;
4007 }
4008 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4009 memcpy(mpi_reply, ioc->base_cmds.reply,
4010 sizeof(Mpi2SasIoUnitControlReply_t));
4011 else
4012 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
4013 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4014 goto out;
4015
4016 issue_host_reset:
4017 if (issue_reset)
4018 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
4019 FORCE_BIG_HAMMER);
4020 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4021 rc = -EFAULT;
4022 out:
4023 mutex_unlock(&ioc->base_cmds.mutex);
4024 return rc;
4025}
4026
4027/**
4028 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
4029 * @ioc: per adapter object
4030 * @mpi_reply: the reply payload from FW
4031 * @mpi_request: the request payload sent to FW
4032 *
4033 * The SCSI Enclosure Processor request message causes the IOC to
4034 * communicate with SES devices to control LED status signals.
4035 *
4036 * Returns 0 for success, non-zero for failure.
4037 */
4038int
4039mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
4040 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
4041{
4042 u16 smid;
4043 u32 ioc_state;
4044 unsigned long timeleft;
eb44552b 4045 bool issue_reset = false;
f92363d1
SR		 4046 int rc;
4047 void *request;
4048 u16 wait_state_count;
4049
4050 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4051 __func__));
4052
4053 mutex_lock(&ioc->base_cmds.mutex);
4054
4055 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
4056 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
4057 ioc->name, __func__);
4058 rc = -EAGAIN;
4059 goto out;
4060 }
4061
4062 wait_state_count = 0;
4063 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4064 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
4065 if (wait_state_count++ == 10) {
4066 pr_err(MPT3SAS_FMT
4067 "%s: failed due to ioc not operational\n",
4068 ioc->name, __func__);
4069 rc = -EFAULT;
4070 goto out;
4071 }
4072 ssleep(1);
4073 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4074 pr_info(MPT3SAS_FMT
4075 "%s: waiting for operational state(count=%d)\n",
4076 ioc->name,
4077 __func__, wait_state_count);
4078 }
4079
4080 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4081 if (!smid) {
4082 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4083 ioc->name, __func__);
4084 rc = -EAGAIN;
4085 goto out;
4086 }
4087
4088 rc = 0;
4089 ioc->base_cmds.status = MPT3_CMD_PENDING;
4090 request = mpt3sas_base_get_msg_frame(ioc, smid);
4091 ioc->base_cmds.smid = smid;
4092 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
4093 init_completion(&ioc->base_cmds.done);
4094 mpt3sas_base_put_smid_default(ioc, smid);
4095 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
4096 msecs_to_jiffies(10000));
4097 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4098 pr_err(MPT3SAS_FMT "%s: timeout\n",
4099 ioc->name, __func__);
4100 _debug_dump_mf(mpi_request,
4101 sizeof(Mpi2SepRequest_t)/4);
4102 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
eb44552b 4103 issue_reset = false;
f92363d1
SR		 4104 goto issue_host_reset;
4105 }
4106 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4107 memcpy(mpi_reply, ioc->base_cmds.reply,
4108 sizeof(Mpi2SepReply_t));
4109 else
4110 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
4111 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4112 goto out;
4113
4114 issue_host_reset:
4115 if (issue_reset)
4116 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
4117 FORCE_BIG_HAMMER);
4118 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4119 rc = -EFAULT;
4120 out:
4121 mutex_unlock(&ioc->base_cmds.mutex);
4122 return rc;
4123}
4124
4125/**
4126 * _base_get_port_facts - obtain port facts reply and save in ioc
4127 * @ioc: per adapter object
4128 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4129 *
4130 * Returns 0 for success, non-zero for failure.
4131 */
4132static int
4133_base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port, int sleep_flag)
4134{
4135 Mpi2PortFactsRequest_t mpi_request;
4136 Mpi2PortFactsReply_t mpi_reply;
4137 struct mpt3sas_port_facts *pfacts;
4138 int mpi_reply_sz, mpi_request_sz, r;
4139
4140 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4141 __func__));
4142
4143 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
4144 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
4145 memset(&mpi_request, 0, mpi_request_sz);
4146 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
4147 mpi_request.PortNumber = port;
4148 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
4149 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
4150
4151 if (r != 0) {
4152 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4153 ioc->name, __func__, r);
4154 return r;
4155 }
4156
4157 pfacts = &ioc->pfacts[port];
4158 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
4159 pfacts->PortNumber = mpi_reply.PortNumber;
4160 pfacts->VP_ID = mpi_reply.VP_ID;
4161 pfacts->VF_ID = mpi_reply.VF_ID;
4162 pfacts->MaxPostedCmdBuffers =
4163 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
4164
4165 return 0;
4166}
4167
4dc8c808
SR		 4168/**
4169 * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
4170 * @ioc: per adapter object
4171 * @timeout:
4172 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4173 *
4174 * Returns 0 for success, non-zero for failure.
4175 */
4176static int
4177_base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout,
4178 int sleep_flag)
4179{
4180 u32 ioc_state;
4181 int rc;
4182
4183 dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name,
4184 __func__));
4185
4186 if (ioc->pci_error_recovery) {
4187 dfailprintk(ioc, printk(MPT3SAS_FMT
4188 "%s: host in pci error recovery\n", ioc->name, __func__));
4189 return -EFAULT;
4190 }
4191
4192 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4193 dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4194 ioc->name, __func__, ioc_state));
4195
4196 if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
4197 (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4198 return 0;
4199
4200 if (ioc_state & MPI2_DOORBELL_USED) {
4201 dhsprintk(ioc, printk(MPT3SAS_FMT
4202 "unexpected doorbell active!\n", ioc->name));
4203 goto issue_diag_reset;
4204 }
4205
4206 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4207 mpt3sas_base_fault_info(ioc, ioc_state &
4208 MPI2_DOORBELL_DATA_MASK);
4209 goto issue_diag_reset;
4210 }
4211
4212 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
4213 timeout, sleep_flag);
4214 if (ioc_state) {
4215 dfailprintk(ioc, printk(MPT3SAS_FMT
4216 "%s: failed going to ready state (ioc_state=0x%x)\n",
4217 ioc->name, __func__, ioc_state));
4218 return -EFAULT;
4219 }
4220
4221 issue_diag_reset:
4222 rc = _base_diag_reset(ioc, sleep_flag);
4223 return rc;
4224}
4225
f92363d1
SR		 4226/**
4227 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
4228 * @ioc: per adapter object
4229 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4230 *
4231 * Returns 0 for success, non-zero for failure.
4232 */
4233static int
4234_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4235{
4236 Mpi2IOCFactsRequest_t mpi_request;
4237 Mpi2IOCFactsReply_t mpi_reply;
4238 struct mpt3sas_facts *facts;
4239 int mpi_reply_sz, mpi_request_sz, r;
4240
4241 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4242 __func__));
4243
4dc8c808
SR		 4244 r = _base_wait_for_iocstate(ioc, 10, sleep_flag);
4245 if (r) {
4246 dfailprintk(ioc, printk(MPT3SAS_FMT
4247 "%s: failed getting to correct state\n",
4248 ioc->name, __func__));
4249 return r;
4250 }
f92363d1
SR		 4251 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
4252 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
4253 memset(&mpi_request, 0, mpi_request_sz);
4254 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
4255 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
4256 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
4257
4258 if (r != 0) {
4259 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4260 ioc->name, __func__, r);
4261 return r;
4262 }
4263
4264 facts = &ioc->facts;
4265 memset(facts, 0, sizeof(struct mpt3sas_facts));
4266 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
4267 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
4268 facts->VP_ID = mpi_reply.VP_ID;
4269 facts->VF_ID = mpi_reply.VF_ID;
4270 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
4271 facts->MaxChainDepth = mpi_reply.MaxChainDepth;
4272 facts->WhoInit = mpi_reply.WhoInit;
4273 facts->NumberOfPorts = mpi_reply.NumberOfPorts;
4274 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
4275 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
4276 facts->MaxReplyDescriptorPostQueueDepth =
4277 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
4278 facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
4279 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
4280 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
4281 ioc->ir_firmware = 1;
9b05c91a
SR		 4282 if ((facts->IOCCapabilities &
4283 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE))
4284 ioc->rdpq_array_capable = 1;
f92363d1
SR		 4285 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
4286 facts->IOCRequestFrameSize =
4287 le16_to_cpu(mpi_reply.IOCRequestFrameSize);
4288 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
4289 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
4290 ioc->shost->max_id = -1;
4291 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
4292 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
4293 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
4294 facts->HighPriorityCredit =
4295 le16_to_cpu(mpi_reply.HighPriorityCredit);
4296 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
4297 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
4298
4299 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4300 "hba queue depth(%d), max chains per io(%d)\n",
4301 ioc->name, facts->RequestCredit,
4302 facts->MaxChainDepth));
4303 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4304 "request frame size(%d), reply frame size(%d)\n", ioc->name,
4305 facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
4306 return 0;
4307}
4308
4309/**
4310 * _base_send_ioc_init - send ioc_init to firmware
4311 * @ioc: per adapter object
4312 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4313 *
4314 * Returns 0 for success, non-zero for failure.
4315 */
4316static int
4317_base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4318{
4319 Mpi2IOCInitRequest_t mpi_request;
4320 Mpi2IOCInitReply_t mpi_reply;
9b05c91a 4321 int i, r = 0;
f92363d1
SR		 4322 struct timeval current_time;
4323 u16 ioc_status;
9b05c91a
SR		 4324 u32 reply_post_free_array_sz = 0;
4325 Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL;
4326 dma_addr_t reply_post_free_array_dma;
f92363d1
SR		 4327
4328 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4329 __func__));
4330
4331 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
4332 mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
4333 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
4334 mpi_request.VF_ID = 0; /* TODO */
4335 mpi_request.VP_ID = 0;
d357e84d 4336 mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
f92363d1
SR		 4337 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
4338
4339 if (_base_is_controller_msix_enabled(ioc))
4340 mpi_request.HostMSIxVectors = ioc->reply_queue_count;
4341 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
4342 mpi_request.ReplyDescriptorPostQueueDepth =
4343 cpu_to_le16(ioc->reply_post_queue_depth);
4344 mpi_request.ReplyFreeQueueDepth =
4345 cpu_to_le16(ioc->reply_free_queue_depth);
4346
4347 mpi_request.SenseBufferAddressHigh =
4348 cpu_to_le32((u64)ioc->sense_dma >> 32);
4349 mpi_request.SystemReplyAddressHigh =
4350 cpu_to_le32((u64)ioc->reply_dma >> 32);
4351 mpi_request.SystemRequestFrameBaseAddress =
4352 cpu_to_le64((u64)ioc->request_dma);
4353 mpi_request.ReplyFreeQueueAddress =
4354 cpu_to_le64((u64)ioc->reply_free_dma);
f92363d1 4355
9b05c91a
SR		 4356 if (ioc->rdpq_array_enable) {
4357 reply_post_free_array_sz = ioc->reply_queue_count *
4358 sizeof(Mpi2IOCInitRDPQArrayEntry);
4359 reply_post_free_array = pci_alloc_consistent(ioc->pdev,
4360 reply_post_free_array_sz, &reply_post_free_array_dma);
4361 if (!reply_post_free_array) {
4362 pr_err(MPT3SAS_FMT
4363 "reply_post_free_array: pci_alloc_consistent failed\n",
4364 ioc->name);
4365 r = -ENOMEM;
4366 goto out;
4367 }
4368 memset(reply_post_free_array, 0, reply_post_free_array_sz);
4369 for (i = 0; i < ioc->reply_queue_count; i++)
4370 reply_post_free_array[i].RDPQBaseAddress =
4371 cpu_to_le64(
4372 (u64)ioc->reply_post[i].reply_post_free_dma);
4373 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
4374 mpi_request.ReplyDescriptorPostQueueAddress =
4375 cpu_to_le64((u64)reply_post_free_array_dma);
4376 } else {
4377 mpi_request.ReplyDescriptorPostQueueAddress =
4378 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
4379 }
f92363d1
SR		 4380
4381 /* This time stamp specifies number of milliseconds
4382 * since epoch ~ midnight January 1, 1970.
4383 */
4384 do_gettimeofday(&current_time);
4385 mpi_request.TimeStamp = cpu_to_le64((u64)current_time.tv_sec * 1000 +
4386 (current_time.tv_usec / 1000));
4387
4388 if (ioc->logging_level & MPT_DEBUG_INIT) {
4389 __le32 *mfp;
4390 int i;
4391
4392 mfp = (__le32 *)&mpi_request;
4393 pr_info("\toffset:data\n");
4394 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
4395 pr_info("\t[0x%02x]:%08x\n", i*4,
4396 le32_to_cpu(mfp[i]));
4397 }
4398
4399 r = _base_handshake_req_reply_wait(ioc,
4400 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
4401 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10,
4402 sleep_flag);
4403
4404 if (r != 0) {
4405 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4406 ioc->name, __func__, r);
9b05c91a 4407 goto out;
f92363d1
SR		 4408 }
4409
4410 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
4411 if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
4412 mpi_reply.IOCLogInfo) {
4413 pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
4414 r = -EIO;
4415 }
4416
9b05c91a
SR		 4417out:
4418 if (reply_post_free_array)
4419 pci_free_consistent(ioc->pdev, reply_post_free_array_sz,
4420 reply_post_free_array,
4421 reply_post_free_array_dma);
4422 return r;
f92363d1
SR		 4423}
4424
4425/**
4426 * mpt3sas_port_enable_done - command completion routine for port enable
4427 * @ioc: per adapter object
4428 * @smid: system request message index
4429 * @msix_index: MSIX table index supplied by the OS
4430 * @reply: reply message frame(lower 32bit addr)
4431 *
4432 * Return 1 meaning mf should be freed from _base_interrupt
4433 * 0 means the mf is freed from this function.
4434 */
4435u8
4436mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
4437 u32 reply)
4438{
4439 MPI2DefaultReply_t *mpi_reply;
4440 u16 ioc_status;
4441
4442 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
4443 return 1;
4444
4445 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
4446 if (!mpi_reply)
4447 return 1;
4448
4449 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
4450 return 1;
4451
4452 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
4453 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
4454 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
4455 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
4456 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4457 if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
4458 ioc->port_enable_failed = 1;
4459
4460 if (ioc->is_driver_loading) {
4461 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
4462 mpt3sas_port_enable_complete(ioc);
4463 return 1;
4464 } else {
4465 ioc->start_scan_failed = ioc_status;
4466 ioc->start_scan = 0;
4467 return 1;
4468 }
4469 }
4470 complete(&ioc->port_enable_cmds.done);
4471 return 1;
4472}
4473
4474/**
4475 * _base_send_port_enable - send port_enable(discovery stuff) to firmware
4476 * @ioc: per adapter object
4477 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4478 *
4479 * Returns 0 for success, non-zero for failure.
4480 */
4481static int
4482_base_send_port_enable(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4483{
4484 Mpi2PortEnableRequest_t *mpi_request;
4485 Mpi2PortEnableReply_t *mpi_reply;
4486 unsigned long timeleft;
4487 int r = 0;
4488 u16 smid;
4489 u16 ioc_status;
4490
4491 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4492
4493 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4494 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4495 ioc->name, __func__);
4496 return -EAGAIN;
4497 }
4498
4499 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4500 if (!smid) {
4501 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4502 ioc->name, __func__);
4503 return -EAGAIN;
4504 }
4505
4506 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4507 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4508 ioc->port_enable_cmds.smid = smid;
4509 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4510 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4511
4512 init_completion(&ioc->port_enable_cmds.done);
4513 mpt3sas_base_put_smid_default(ioc, smid);
4514 timeleft = wait_for_completion_timeout(&ioc->port_enable_cmds.done,
4515 300*HZ);
4516 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
4517 pr_err(MPT3SAS_FMT "%s: timeout\n",
4518 ioc->name, __func__);
4519 _debug_dump_mf(mpi_request,
4520 sizeof(Mpi2PortEnableRequest_t)/4);
4521 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
4522 r = -EFAULT;
4523 else
4524 r = -ETIME;
4525 goto out;
4526 }
4527
4528 mpi_reply = ioc->port_enable_cmds.reply;
4529 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4530 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4531 pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
4532 ioc->name, __func__, ioc_status);
4533 r = -EFAULT;
4534 goto out;
4535 }
4536
4537 out:
4538 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
4539 pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
4540 "SUCCESS" : "FAILED"));
4541 return r;
4542}
4543
4544/**
4545 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
4546 * @ioc: per adapter object
4547 *
4548 * Returns 0 for success, non-zero for failure.
4549 */
4550int
4551mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
4552{
4553 Mpi2PortEnableRequest_t *mpi_request;
4554 u16 smid;
4555
4556 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4557
4558 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4559 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4560 ioc->name, __func__);
4561 return -EAGAIN;
4562 }
4563
4564 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4565 if (!smid) {
4566 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4567 ioc->name, __func__);
4568 return -EAGAIN;
4569 }
4570
4571 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4572 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4573 ioc->port_enable_cmds.smid = smid;
4574 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4575 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4576
4577 mpt3sas_base_put_smid_default(ioc, smid);
4578 return 0;
4579}
4580
4581/**
4582 * _base_determine_wait_on_discovery - desposition
4583 * @ioc: per adapter object
4584 *
4585 * Decide whether to wait on discovery to complete. Used to either
4586 * locate boot device, or report volumes ahead of physical devices.
4587 *
4588 * Returns 1 for wait, 0 for don't wait
4589 */
4590static int
4591_base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
4592{
4593 /* We wait for discovery to complete if IR firmware is loaded.
4594 * The sas topology events arrive before PD events, so we need time to
4595 * turn on the bit in ioc->pd_handles to indicate PD
4596 * Also, it maybe required to report Volumes ahead of physical
4597 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
4598 */
4599 if (ioc->ir_firmware)
4600 return 1;
4601
4602 /* if no Bios, then we don't need to wait */
4603 if (!ioc->bios_pg3.BiosVersion)
4604 return 0;
4605
4606 /* Bios is present, then we drop down here.
4607 *
4608 * If there any entries in the Bios Page 2, then we wait
4609 * for discovery to complete.
4610 */
4611
4612 /* Current Boot Device */
4613 if ((ioc->bios_pg2.CurrentBootDeviceForm &
4614 MPI2_BIOSPAGE2_FORM_MASK) ==
4615 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4616 /* Request Boot Device */
4617 (ioc->bios_pg2.ReqBootDeviceForm &
4618 MPI2_BIOSPAGE2_FORM_MASK) ==
4619 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4620 /* Alternate Request Boot Device */
4621 (ioc->bios_pg2.ReqAltBootDeviceForm &
4622 MPI2_BIOSPAGE2_FORM_MASK) ==
4623 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
4624 return 0;
4625
4626 return 1;
4627}
4628
4629/**
4630 * _base_unmask_events - turn on notification for this event
4631 * @ioc: per adapter object
4632 * @event: firmware event
4633 *
4634 * The mask is stored in ioc->event_masks.
4635 */
4636static void
4637_base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
4638{
4639 u32 desired_event;
4640
4641 if (event >= 128)
4642 return;
4643
4644 desired_event = (1 << (event % 32));
4645
4646 if (event < 32)
4647 ioc->event_masks[0] &= ~desired_event;
4648 else if (event < 64)
4649 ioc->event_masks[1] &= ~desired_event;
4650 else if (event < 96)
4651 ioc->event_masks[2] &= ~desired_event;
4652 else if (event < 128)
4653 ioc->event_masks[3] &= ~desired_event;
4654}
4655
4656/**
4657 * _base_event_notification - send event notification
4658 * @ioc: per adapter object
4659 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4660 *
4661 * Returns 0 for success, non-zero for failure.
4662 */
4663static int
4664_base_event_notification(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4665{
4666 Mpi2EventNotificationRequest_t *mpi_request;
4667 unsigned long timeleft;
4668 u16 smid;
4669 int r = 0;
4670 int i;
4671
4672 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4673 __func__));
4674
4675 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4676 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4677 ioc->name, __func__);
4678 return -EAGAIN;
4679 }
4680
4681 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4682 if (!smid) {
4683 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4684 ioc->name, __func__);
4685 return -EAGAIN;
4686 }
4687 ioc->base_cmds.status = MPT3_CMD_PENDING;
4688 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4689 ioc->base_cmds.smid = smid;
4690 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
4691 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
4692 mpi_request->VF_ID = 0; /* TODO */
4693 mpi_request->VP_ID = 0;
4694 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4695 mpi_request->EventMasks[i] =
4696 cpu_to_le32(ioc->event_masks[i]);
4697 init_completion(&ioc->base_cmds.done);
4698 mpt3sas_base_put_smid_default(ioc, smid);
4699 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
4700 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4701 pr_err(MPT3SAS_FMT "%s: timeout\n",
4702 ioc->name, __func__);
4703 _debug_dump_mf(mpi_request,
4704 sizeof(Mpi2EventNotificationRequest_t)/4);
4705 if (ioc->base_cmds.status & MPT3_CMD_RESET)
4706 r = -EFAULT;
4707 else
4708 r = -ETIME;
4709 } else
4710 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
4711 ioc->name, __func__));
4712 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4713 return r;
4714}
4715
4716/**
4717 * mpt3sas_base_validate_event_type - validating event types
4718 * @ioc: per adapter object
4719 * @event: firmware event
4720 *
4721 * This will turn on firmware event notification when application
4722 * ask for that event. We don't mask events that are already enabled.
4723 */
4724void
4725mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
4726{
4727 int i, j;
4728 u32 event_mask, desired_event;
4729 u8 send_update_to_fw;
4730
4731 for (i = 0, send_update_to_fw = 0; i <
4732 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
4733 event_mask = ~event_type[i];
4734 desired_event = 1;
4735 for (j = 0; j < 32; j++) {
4736 if (!(event_mask & desired_event) &&
4737 (ioc->event_masks[i] & desired_event)) {
4738 ioc->event_masks[i] &= ~desired_event;
4739 send_update_to_fw = 1;
4740 }
4741 desired_event = (desired_event << 1);
4742 }
4743 }
4744
4745 if (!send_update_to_fw)
4746 return;
4747
4748 mutex_lock(&ioc->base_cmds.mutex);
4749 _base_event_notification(ioc, CAN_SLEEP);
4750 mutex_unlock(&ioc->base_cmds.mutex);
4751}
4752
4753/**
4754 * _base_diag_reset - the "big hammer" start of day reset
4755 * @ioc: per adapter object
4756 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4757 *
4758 * Returns 0 for success, non-zero for failure.
4759 */
4760static int
4761_base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4762{
4763 u32 host_diagnostic;
4764 u32 ioc_state;
4765 u32 count;
4766 u32 hcb_size;
4767
4768 pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
4769
4770 drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
4771 ioc->name));
4772
4773 count = 0;
4774 do {
4775 /* Write magic sequence to WriteSequence register
4776 * Loop until in diagnostic mode
4777 */
4778 drsprintk(ioc, pr_info(MPT3SAS_FMT
4779 "write magic sequence\n", ioc->name));
4780 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4781 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
4782 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
4783 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
4784 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
4785 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
4786 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
4787
4788 /* wait 100 msec */
4789 if (sleep_flag == CAN_SLEEP)
4790 msleep(100);
4791 else
4792 mdelay(100);
4793
4794 if (count++ > 20)
4795 goto out;
4796
4797 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4798 drsprintk(ioc, pr_info(MPT3SAS_FMT
4799 "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
4800 ioc->name, count, host_diagnostic));
4801
4802 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
4803
4804 hcb_size = readl(&ioc->chip->HCBSize);
4805
4806 drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
4807 ioc->name));
4808 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
4809 &ioc->chip->HostDiagnostic);
4810
b453ff84
SR		 4811 /*This delay allows the chip PCIe hardware time to finish reset tasks*/
4812 if (sleep_flag == CAN_SLEEP)
4813 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
4814 else
4815 mdelay(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
f92363d1 4816
b453ff84
SR		 4817 /* Approximately 300 second max wait */
4818 for (count = 0; count < (300000000 /
4819 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
f92363d1
SR		 4820
4821 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4822
4823 if (host_diagnostic == 0xFFFFFFFF)
4824 goto out;
4825 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
4826 break;
4827
b453ff84 4828 /* Wait to pass the second read delay window */
f92363d1 4829 if (sleep_flag == CAN_SLEEP)
b453ff84
SR		 4830 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4831 / 1000);
f92363d1 4832 else
b453ff84
SR		 4833 mdelay(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4834 / 1000);
f92363d1
SR		 4835 }
4836
4837 if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
4838
4839 drsprintk(ioc, pr_info(MPT3SAS_FMT
4840 "restart the adapter assuming the HCB Address points to good F/W\n",
4841 ioc->name));
4842 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
4843 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
4844 writel(host_diagnostic, &ioc->chip->HostDiagnostic);
4845
4846 drsprintk(ioc, pr_info(MPT3SAS_FMT
4847 "re-enable the HCDW\n", ioc->name));
4848 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
4849 &ioc->chip->HCBSize);
4850 }
4851
4852 drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
4853 ioc->name));
4854 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
4855 &ioc->chip->HostDiagnostic);
4856
4857 drsprintk(ioc, pr_info(MPT3SAS_FMT
4858 "disable writes to the diagnostic register\n", ioc->name));
4859 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4860
4861 drsprintk(ioc, pr_info(MPT3SAS_FMT
4862 "Wait for FW to go to the READY state\n", ioc->name));
4863 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20,
4864 sleep_flag);
4865 if (ioc_state) {
4866 pr_err(MPT3SAS_FMT
4867 "%s: failed going to ready state (ioc_state=0x%x)\n",
4868 ioc->name, __func__, ioc_state);
4869 goto out;
4870 }
4871
4872 pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
4873 return 0;
4874
4875 out:
4876 pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
4877 return -EFAULT;
4878}
4879
4880/**
4881 * _base_make_ioc_ready - put controller in READY state
4882 * @ioc: per adapter object
4883 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4884 * @type: FORCE_BIG_HAMMER or SOFT_RESET
4885 *
4886 * Returns 0 for success, non-zero for failure.
4887 */
4888static int
4889_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
4890 enum reset_type type)
4891{
4892 u32 ioc_state;
4893 int rc;
4894 int count;
4895
4896 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4897 __func__));
4898
4899 if (ioc->pci_error_recovery)
4900 return 0;
4901
4902 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4903 dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4904 ioc->name, __func__, ioc_state));
4905
4906 /* if in RESET state, it should move to READY state shortly */
4907 count = 0;
4908 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
4909 while ((ioc_state & MPI2_IOC_STATE_MASK) !=
4910 MPI2_IOC_STATE_READY) {
4911 if (count++ == 10) {
4912 pr_err(MPT3SAS_FMT
4913 "%s: failed going to ready state (ioc_state=0x%x)\n",
4914 ioc->name, __func__, ioc_state);
4915 return -EFAULT;
4916 }
4917 if (sleep_flag == CAN_SLEEP)
4918 ssleep(1);
4919 else
4920 mdelay(1000);
4921 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4922 }
4923 }
4924
4925 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
4926 return 0;
4927
4928 if (ioc_state & MPI2_DOORBELL_USED) {
4929 dhsprintk(ioc, pr_info(MPT3SAS_FMT
4930 "unexpected doorbell active!\n",
4931 ioc->name));
4932 goto issue_diag_reset;
4933 }
4934
4935 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4936 mpt3sas_base_fault_info(ioc, ioc_state &
4937 MPI2_DOORBELL_DATA_MASK);
4938 goto issue_diag_reset;
4939 }
4940
4941 if (type == FORCE_BIG_HAMMER)
4942 goto issue_diag_reset;
4943
4944 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4945 if (!(_base_send_ioc_reset(ioc,
4946 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP))) {
4947 return 0;
4948 }
4949
4950 issue_diag_reset:
4951 rc = _base_diag_reset(ioc, CAN_SLEEP);
4952 return rc;
4953}
4954
4955/**
4956 * _base_make_ioc_operational - put controller in OPERATIONAL state
4957 * @ioc: per adapter object
4958 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4959 *
4960 * Returns 0 for success, non-zero for failure.
4961 */
4962static int
4963_base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4964{
4965 int r, i;
4966 unsigned long flags;
4967 u32 reply_address;
4968 u16 smid;
4969 struct _tr_list *delayed_tr, *delayed_tr_next;
7786ab6a 4970 u8 hide_flag;
f92363d1
SR		 4971 struct adapter_reply_queue *reply_q;
4972 long reply_post_free;
9b05c91a 4973 u32 reply_post_free_sz, index = 0;
f92363d1
SR		 4974
4975 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4976 __func__));
4977
4978 /* clean the delayed target reset list */
4979 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
4980 &ioc->delayed_tr_list, list) {
4981 list_del(&delayed_tr->list);
4982 kfree(delayed_tr);
4983 }
4984
4985
4986 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
4987 &ioc->delayed_tr_volume_list, list) {
4988 list_del(&delayed_tr->list);
4989 kfree(delayed_tr);
4990 }
4991
4992 /* initialize the scsi lookup free list */
4993 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
4994 INIT_LIST_HEAD(&ioc->free_list);
4995 smid = 1;
4996 for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
4997 INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
4998 ioc->scsi_lookup[i].cb_idx = 0xFF;
4999 ioc->scsi_lookup[i].smid = smid;
5000 ioc->scsi_lookup[i].scmd = NULL;
7786ab6a 5001 ioc->scsi_lookup[i].direct_io = 0;
f92363d1
SR		 5002 list_add_tail(&ioc->scsi_lookup[i].tracker_list,
5003 &ioc->free_list);
5004 }
5005
5006 /* hi-priority queue */
5007 INIT_LIST_HEAD(&ioc->hpr_free_list);
5008 smid = ioc->hi_priority_smid;
5009 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
5010 ioc->hpr_lookup[i].cb_idx = 0xFF;
5011 ioc->hpr_lookup[i].smid = smid;
5012 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
5013 &ioc->hpr_free_list);
5014 }
5015
5016 /* internal queue */
5017 INIT_LIST_HEAD(&ioc->internal_free_list);
5018 smid = ioc->internal_smid;
5019 for (i = 0; i < ioc->internal_depth; i++, smid++) {
5020 ioc->internal_lookup[i].cb_idx = 0xFF;
5021 ioc->internal_lookup[i].smid = smid;
5022 list_add_tail(&ioc->internal_lookup[i].tracker_list,
5023 &ioc->internal_free_list);
5024 }
5025
5026 /* chain pool */
5027 INIT_LIST_HEAD(&ioc->free_chain_list);
5028 for (i = 0; i < ioc->chain_depth; i++)
5029 list_add_tail(&ioc->chain_lookup[i].tracker_list,
5030 &ioc->free_chain_list);
5031
5032 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5033
5034 /* initialize Reply Free Queue */
5035 for (i = 0, reply_address = (u32)ioc->reply_dma ;
5036 i < ioc->reply_free_queue_depth ; i++, reply_address +=
5037 ioc->reply_sz)
5038 ioc->reply_free[i] = cpu_to_le32(reply_address);
5039
5040 /* initialize reply queues */
5041 if (ioc->is_driver_loading)
5042 _base_assign_reply_queues(ioc);
5043
5044 /* initialize Reply Post Free Queue */
f92363d1
SR		 5045 reply_post_free_sz = ioc->reply_post_queue_depth *
5046 sizeof(Mpi2DefaultReplyDescriptor_t);
9b05c91a 5047 reply_post_free = (long)ioc->reply_post[index].reply_post_free;
f92363d1
SR		 5048 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
5049 reply_q->reply_post_host_index = 0;
5050 reply_q->reply_post_free = (Mpi2ReplyDescriptorsUnion_t *)
5051 reply_post_free;
5052 for (i = 0; i < ioc->reply_post_queue_depth; i++)
5053 reply_q->reply_post_free[i].Words =
5054 cpu_to_le64(ULLONG_MAX);
5055 if (!_base_is_controller_msix_enabled(ioc))
5056 goto skip_init_reply_post_free_queue;
9b05c91a
SR		 5057 /*
5058 * If RDPQ is enabled, switch to the next allocation.
5059 * Otherwise advance within the contiguous region.
5060 */
5061 if (ioc->rdpq_array_enable)
5062 reply_post_free = (long)
5063 ioc->reply_post[++index].reply_post_free;
5064 else
5065 reply_post_free += reply_post_free_sz;
f92363d1
SR		 5066 }
5067 skip_init_reply_post_free_queue:
5068
5069 r = _base_send_ioc_init(ioc, sleep_flag);
5070 if (r)
5071 return r;
5072
5073 /* initialize reply free host index */
5074 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
5075 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
5076
5077 /* initialize reply post host index */
5078 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
fb77bb53
SR		 5079 if (ioc->msix96_vector)
5080 writel((reply_q->msix_index & 7)<<
5081 MPI2_RPHI_MSIX_INDEX_SHIFT,
5082 ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
5083 else
5084 writel(reply_q->msix_index <<
5085 MPI2_RPHI_MSIX_INDEX_SHIFT,
5086 &ioc->chip->ReplyPostHostIndex);
5087
f92363d1
SR		 5088 if (!_base_is_controller_msix_enabled(ioc))
5089 goto skip_init_reply_post_host_index;
5090 }
5091
5092 skip_init_reply_post_host_index:
5093
5094 _base_unmask_interrupts(ioc);
5095 r = _base_event_notification(ioc, sleep_flag);
5096 if (r)
5097 return r;
5098
5099 if (sleep_flag == CAN_SLEEP)
5100 _base_static_config_pages(ioc);
5101
5102
5103 if (ioc->is_driver_loading) {
7786ab6a
SR		 5104
5105 if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier
5106 == 0x80) {
5107 hide_flag = (u8) (
5108 le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) &
5109 MFG_PAGE10_HIDE_SSDS_MASK);
5110 if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
5111 ioc->mfg_pg10_hide_flag = hide_flag;
5112 }
5113
f92363d1
SR		 5114 ioc->wait_for_discovery_to_complete =
5115 _base_determine_wait_on_discovery(ioc);
5116
5117 return r; /* scan_start and scan_finished support */
5118 }
5119
5120 r = _base_send_port_enable(ioc, sleep_flag);
5121 if (r)
5122 return r;
5123
5124 return r;
5125}
5126
5127/**
5128 * mpt3sas_base_free_resources - free resources controller resources
5129 * @ioc: per adapter object
5130 *
5131 * Return nothing.
5132 */
5133void
5134mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
5135{
f92363d1
SR		 5136 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5137 __func__));
5138
cf9bd21a
JL		 5139 if (ioc->chip_phys && ioc->chip) {
5140 _base_mask_interrupts(ioc);
5141 ioc->shost_recovery = 1;
5142 _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
5143 ioc->shost_recovery = 0;
5144 }
5145
580d4e31 5146 mpt3sas_base_unmap_resources(ioc);
f92363d1
SR		 5147 return;
5148}
5149
5150/**
5151 * mpt3sas_base_attach - attach controller instance
5152 * @ioc: per adapter object
5153 *
5154 * Returns 0 for success, non-zero for failure.
5155 */
5156int
5157mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
5158{
5159 int r, i;
5160 int cpu_id, last_cpu_id = 0;
5161
5162 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5163 __func__));
5164
5165 /* setup cpu_msix_table */
5166 ioc->cpu_count = num_online_cpus();
5167 for_each_online_cpu(cpu_id)
5168 last_cpu_id = cpu_id;
5169 ioc->cpu_msix_table_sz = last_cpu_id + 1;
5170 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
5171 ioc->reply_queue_count = 1;
5172 if (!ioc->cpu_msix_table) {
5173 dfailprintk(ioc, pr_info(MPT3SAS_FMT
5174 "allocation for cpu_msix_table failed!!!\n",
5175 ioc->name));
5176 r = -ENOMEM;
5177 goto out_free_resources;
5178 }
5179
7786ab6a
SR		 5180 if (ioc->is_warpdrive) {
5181 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
5182 sizeof(resource_size_t *), GFP_KERNEL);
5183 if (!ioc->reply_post_host_index) {
5184 dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation "
5185 "for cpu_msix_table failed!!!\n", ioc->name));
5186 r = -ENOMEM;
5187 goto out_free_resources;
5188 }
5189 }
5190
9b05c91a
SR		 5191 ioc->rdpq_array_enable_assigned = 0;
5192 ioc->dma_mask = 0;
f92363d1
SR		 5193 r = mpt3sas_base_map_resources(ioc);
5194 if (r)
5195 goto out_free_resources;
5196
7786ab6a
SR		 5197 if (ioc->is_warpdrive) {
5198 ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
5199 &ioc->chip->ReplyPostHostIndex;
5200
5201 for (i = 1; i < ioc->cpu_msix_table_sz; i++)
5202 ioc->reply_post_host_index[i] =
5203 (resource_size_t __iomem *)
5204 ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
5205 * 4)));
5206 }
f92363d1
SR		 5207
5208 pci_set_drvdata(ioc->pdev, ioc->shost);
5209 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
5210 if (r)
5211 goto out_free_resources;
5212
471ef9d4
SR		 5213 switch (ioc->hba_mpi_version_belonged) {
5214 case MPI2_VERSION:
5215 ioc->build_sg_scmd = &_base_build_sg_scmd;
5216 ioc->build_sg = &_base_build_sg;
5217 ioc->build_zero_len_sge = &_base_build_zero_len_sge;
5218 break;
5219 case MPI25_VERSION:
5220 /*
5221 * In SAS3.0,
5222 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
5223 * Target Status - all require the IEEE formated scatter gather
5224 * elements.
5225 */
5226 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
5227 ioc->build_sg = &_base_build_sg_ieee;
5228 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
5229 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
5230 break;
5231 }
f92363d1
SR		 5232
5233 /*
5234 * These function pointers for other requests that don't
5235 * the require IEEE scatter gather elements.
5236 *
5237 * For example Configuration Pages and SAS IOUNIT Control don't.
5238 */
5239 ioc->build_sg_mpi = &_base_build_sg;
5240 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
5241
5242 r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
5243 if (r)
5244 goto out_free_resources;
5245
5246 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
5247 sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
5248 if (!ioc->pfacts) {
5249 r = -ENOMEM;
5250 goto out_free_resources;
5251 }
5252
5253 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
5254 r = _base_get_port_facts(ioc, i, CAN_SLEEP);
5255 if (r)
5256 goto out_free_resources;
5257 }
5258
5259 r = _base_allocate_memory_pools(ioc, CAN_SLEEP);
5260 if (r)
5261 goto out_free_resources;
5262
5263 init_waitqueue_head(&ioc->reset_wq);
5264
5265 /* allocate memory pd handle bitmask list */
5266 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
5267 if (ioc->facts.MaxDevHandle % 8)
5268 ioc->pd_handles_sz++;
5269 ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
5270 GFP_KERNEL);
5271 if (!ioc->pd_handles) {
5272 r = -ENOMEM;
5273 goto out_free_resources;
5274 }
5275 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
5276 GFP_KERNEL);
5277 if (!ioc->blocking_handles) {
5278 r = -ENOMEM;
5279 goto out_free_resources;
5280 }
5281
5282 ioc->fwfault_debug = mpt3sas_fwfault_debug;
5283
5284 /* base internal command bits */
5285 mutex_init(&ioc->base_cmds.mutex);
5286 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5287 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
5288
5289 /* port_enable command bits */
5290 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5291 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
5292
5293 /* transport internal command bits */
5294 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5295 ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
5296 mutex_init(&ioc->transport_cmds.mutex);
5297
5298 /* scsih internal command bits */
5299 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5300 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
5301 mutex_init(&ioc->scsih_cmds.mutex);
5302
5303 /* task management internal command bits */
5304 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5305 ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
5306 mutex_init(&ioc->tm_cmds.mutex);
5307
5308 /* config page internal command bits */
5309 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5310 ioc->config_cmds.status = MPT3_CMD_NOT_USED;
5311 mutex_init(&ioc->config_cmds.mutex);
5312
5313 /* ctl module internal command bits */
5314 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5315 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
5316 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
5317 mutex_init(&ioc->ctl_cmds.mutex);
5318
5319 if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
5320 !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
5321 !ioc->config_cmds.reply || !ioc->ctl_cmds.reply ||
5322 !ioc->ctl_cmds.sense) {
5323 r = -ENOMEM;
5324 goto out_free_resources;
5325 }
5326
5327 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
5328 ioc->event_masks[i] = -1;
5329
5330 /* here we enable the events we care about */
5331 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
5332 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
5333 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
5334 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
5335 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
5336 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
5337 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
5338 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
5339 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
5340 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
2d8ce8c9 5341 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
f92363d1
SR		 5342
5343 r = _base_make_ioc_operational(ioc, CAN_SLEEP);
5344 if (r)
5345 goto out_free_resources;
5346
16e179bd 5347 ioc->non_operational_loop = 0;
f92363d1
SR		 5348 return 0;
5349
5350 out_free_resources:
5351
5352 ioc->remove_host = 1;
5353
5354 mpt3sas_base_free_resources(ioc);
5355 _base_release_memory_pools(ioc);
5356 pci_set_drvdata(ioc->pdev, NULL);
5357 kfree(ioc->cpu_msix_table);
7786ab6a
SR		 5358 if (ioc->is_warpdrive)
5359 kfree(ioc->reply_post_host_index);
f92363d1
SR		 5360 kfree(ioc->pd_handles);
5361 kfree(ioc->blocking_handles);
5362 kfree(ioc->tm_cmds.reply);
5363 kfree(ioc->transport_cmds.reply);
5364 kfree(ioc->scsih_cmds.reply);
5365 kfree(ioc->config_cmds.reply);
5366 kfree(ioc->base_cmds.reply);
5367 kfree(ioc->port_enable_cmds.reply);
5368 kfree(ioc->ctl_cmds.reply);
5369 kfree(ioc->ctl_cmds.sense);
5370 kfree(ioc->pfacts);
5371 ioc->ctl_cmds.reply = NULL;
5372 ioc->base_cmds.reply = NULL;
5373 ioc->tm_cmds.reply = NULL;
5374 ioc->scsih_cmds.reply = NULL;
5375 ioc->transport_cmds.reply = NULL;
5376 ioc->config_cmds.reply = NULL;
5377 ioc->pfacts = NULL;
5378 return r;
5379}
5380
5381
5382/**
5383 * mpt3sas_base_detach - remove controller instance
5384 * @ioc: per adapter object
5385 *
5386 * Return nothing.
5387 */
5388void
5389mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
5390{
5391 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5392 __func__));
5393
5394 mpt3sas_base_stop_watchdog(ioc);
5395 mpt3sas_base_free_resources(ioc);
5396 _base_release_memory_pools(ioc);
5397 pci_set_drvdata(ioc->pdev, NULL);
5398 kfree(ioc->cpu_msix_table);
7786ab6a
SR		 5399 if (ioc->is_warpdrive)
5400 kfree(ioc->reply_post_host_index);
f92363d1
SR		 5401 kfree(ioc->pd_handles);
5402 kfree(ioc->blocking_handles);
5403 kfree(ioc->pfacts);
5404 kfree(ioc->ctl_cmds.reply);
5405 kfree(ioc->ctl_cmds.sense);
5406 kfree(ioc->base_cmds.reply);
5407 kfree(ioc->port_enable_cmds.reply);
5408 kfree(ioc->tm_cmds.reply);
5409 kfree(ioc->transport_cmds.reply);
5410 kfree(ioc->scsih_cmds.reply);
5411 kfree(ioc->config_cmds.reply);
5412}
5413
5414/**
5415 * _base_reset_handler - reset callback handler (for base)
5416 * @ioc: per adapter object
5417 * @reset_phase: phase
5418 *
5419 * The handler for doing any required cleanup or initialization.
5420 *
5421 * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET,
5422 * MPT3_IOC_DONE_RESET
5423 *
5424 * Return nothing.
5425 */
5426static void
5427_base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase)
5428{
5429 mpt3sas_scsih_reset_handler(ioc, reset_phase);
5430 mpt3sas_ctl_reset_handler(ioc, reset_phase);
5431 switch (reset_phase) {
5432 case MPT3_IOC_PRE_RESET:
5433 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5434 "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
5435 break;
5436 case MPT3_IOC_AFTER_RESET:
5437 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5438 "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
5439 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
5440 ioc->transport_cmds.status |= MPT3_CMD_RESET;
5441 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
5442 complete(&ioc->transport_cmds.done);
5443 }
5444 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
5445 ioc->base_cmds.status |= MPT3_CMD_RESET;
5446 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
5447 complete(&ioc->base_cmds.done);
5448 }
5449 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5450 ioc->port_enable_failed = 1;
5451 ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
5452 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
5453 if (ioc->is_driver_loading) {
5454 ioc->start_scan_failed =
5455 MPI2_IOCSTATUS_INTERNAL_ERROR;
5456 ioc->start_scan = 0;
5457 ioc->port_enable_cmds.status =
5458 MPT3_CMD_NOT_USED;
5459 } else
5460 complete(&ioc->port_enable_cmds.done);
5461 }
5462 if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
5463 ioc->config_cmds.status |= MPT3_CMD_RESET;
5464 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
5465 ioc->config_cmds.smid = USHRT_MAX;
5466 complete(&ioc->config_cmds.done);
5467 }
5468 break;
5469 case MPT3_IOC_DONE_RESET:
5470 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5471 "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
5472 break;
5473 }
5474}
5475
5476/**
5477 * _wait_for_commands_to_complete - reset controller
5478 * @ioc: Pointer to MPT_ADAPTER structure
5479 * @sleep_flag: CAN_SLEEP or NO_SLEEP
5480 *
5481 * This function waiting(3s) for all pending commands to complete
5482 * prior to putting controller in reset.
5483 */
5484static void
5485_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
5486{
5487 u32 ioc_state;
5488 unsigned long flags;
5489 u16 i;
5490
5491 ioc->pending_io_count = 0;
5492 if (sleep_flag != CAN_SLEEP)
5493 return;
5494
5495 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5496 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
5497 return;
5498
5499 /* pending command count */
5500 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5501 for (i = 0; i < ioc->scsiio_depth; i++)
5502 if (ioc->scsi_lookup[i].cb_idx != 0xFF)
5503 ioc->pending_io_count++;
5504 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5505
5506 if (!ioc->pending_io_count)
5507 return;
5508
5509 /* wait for pending commands to complete */
5510 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
5511}
5512
5513/**
5514 * mpt3sas_base_hard_reset_handler - reset controller
5515 * @ioc: Pointer to MPT_ADAPTER structure
5516 * @sleep_flag: CAN_SLEEP or NO_SLEEP
5517 * @type: FORCE_BIG_HAMMER or SOFT_RESET
5518 *
5519 * Returns 0 for success, non-zero for failure.
5520 */
5521int
5522mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
5523 enum reset_type type)
5524{
5525 int r;
5526 unsigned long flags;
5527 u32 ioc_state;
5528 u8 is_fault = 0, is_trigger = 0;
5529
5530 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
5531 __func__));
5532
5533 if (ioc->pci_error_recovery) {
5534 pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
5535 ioc->name, __func__);
5536 r = 0;
5537 goto out_unlocked;
5538 }
5539
5540 if (mpt3sas_fwfault_debug)
5541 mpt3sas_halt_firmware(ioc);
5542
5543 /* TODO - What we really should be doing is pulling
5544 * out all the code associated with NO_SLEEP; its never used.
5545 * That is legacy code from mpt fusion driver, ported over.
5546 * I will leave this BUG_ON here for now till its been resolved.
5547 */
5548 BUG_ON(sleep_flag == NO_SLEEP);
5549
5550 /* wait for an active reset in progress to complete */
5551 if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
5552 do {
5553 ssleep(1);
5554 } while (ioc->shost_recovery == 1);
5555 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5556 __func__));
5557 return ioc->ioc_reset_in_progress_status;
5558 }
5559
5560 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5561 ioc->shost_recovery = 1;
5562 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5563
5564 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5565 MPT3_DIAG_BUFFER_IS_REGISTERED) &&
5566 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5567 MPT3_DIAG_BUFFER_IS_RELEASED))) {
5568 is_trigger = 1;
5569 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5570 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
5571 is_fault = 1;
5572 }
5573 _base_reset_handler(ioc, MPT3_IOC_PRE_RESET);
5574 _wait_for_commands_to_complete(ioc, sleep_flag);
5575 _base_mask_interrupts(ioc);
5576 r = _base_make_ioc_ready(ioc, sleep_flag, type);
5577 if (r)
5578 goto out;
5579 _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET);
5580
5581 /* If this hard reset is called while port enable is active, then
5582 * there is no reason to call make_ioc_operational
5583 */
5584 if (ioc->is_driver_loading && ioc->port_enable_failed) {
5585 ioc->remove_host = 1;
5586 r = -EFAULT;
5587 goto out;
5588 }
5589 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
5590 if (r)
5591 goto out;
9b05c91a
SR		 5592
5593 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
5594 panic("%s: Issue occurred with flashing controller firmware."
5595 "Please reboot the system and ensure that the correct"
5596 " firmware version is running\n", ioc->name);
5597
f92363d1
SR		 5598 r = _base_make_ioc_operational(ioc, sleep_flag);
5599 if (!r)
5600 _base_reset_handler(ioc, MPT3_IOC_DONE_RESET);
5601
5602 out:
5603 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
5604 ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
5605
5606 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5607 ioc->ioc_reset_in_progress_status = r;
5608 ioc->shost_recovery = 0;
5609 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5610 ioc->ioc_reset_count++;
5611 mutex_unlock(&ioc->reset_in_progress_mutex);
5612
5613 out_unlocked:
5614 if ((r == 0) && is_trigger) {
5615 if (is_fault)
5616 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
5617 else
5618 mpt3sas_trigger_master(ioc,
5619 MASTER_TRIGGER_ADAPTER_RESET);
5620 }
5621 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5622 __func__));
5623 return r;
5624}
Linux 6.x block layer and io_uring tree(s)