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mpt3sas: Updated MPI Header to 2.00.42
[linux-2.6-block.git] / drivers / scsi / mpt3sas / mpt3sas_base.c
CommitLineData
f92363d1
SR		 1/*
2 * This is the Fusion MPT base driver providing common API layer interface
3 * for access to MPT (Message Passing Technology) firmware.
4 *
5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
a4ffce0d 6 * Copyright (C) 2012-2014 LSI Corporation
a03bd153
SR		 7 * Copyright (C) 2013-2014 Avago Technologies
8 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
f92363d1
SR		 9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * NO WARRANTY
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25 * solely responsible for determining the appropriateness of using and
26 * distributing the Program and assumes all risks associated with its
27 * exercise of rights under this Agreement, including but not limited to
28 * the risks and costs of program errors, damage to or loss of data,
29 * programs or equipment, and unavailability or interruption of operations.
30
31 * DISCLAIMER OF LIABILITY
32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
43 * USA.
44 */
45
f92363d1
SR		 46#include <linux/kernel.h>
47#include <linux/module.h>
48#include <linux/errno.h>
49#include <linux/init.h>
50#include <linux/slab.h>
51#include <linux/types.h>
52#include <linux/pci.h>
53#include <linux/kdev_t.h>
54#include <linux/blkdev.h>
55#include <linux/delay.h>
56#include <linux/interrupt.h>
57#include <linux/dma-mapping.h>
58#include <linux/io.h>
59#include <linux/time.h>
60#include <linux/kthread.h>
61#include <linux/aer.h>
62
63
64#include "mpt3sas_base.h"
65
66static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
67
68
69#define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
70
71 /* maximum controller queue depth */
72#define MAX_HBA_QUEUE_DEPTH 30000
73#define MAX_CHAIN_DEPTH 100000
74static int max_queue_depth = -1;
75module_param(max_queue_depth, int, 0);
76MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
77
78static int max_sgl_entries = -1;
79module_param(max_sgl_entries, int, 0);
80MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
81
82static int msix_disable = -1;
83module_param(msix_disable, int, 0);
84MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
85
64038301
SPS		 86static int smp_affinity_enable = 1;
87module_param(smp_affinity_enable, int, S_IRUGO);
88MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disbale Default: enable(1)");
89
fb77bb53 90static int max_msix_vectors = -1;
9c500060
SR		 91module_param(max_msix_vectors, int, 0);
92MODULE_PARM_DESC(max_msix_vectors,
fb77bb53 93 " max msix vectors");
f92363d1
SR		 94
95static int mpt3sas_fwfault_debug;
96MODULE_PARM_DESC(mpt3sas_fwfault_debug,
97 " enable detection of firmware fault and halt firmware - (default=0)");
98
9b05c91a
SR		 99static int
100_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag);
f92363d1
SR		 101
102/**
103 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
104 *
105 */
106static int
107_scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
108{
109 int ret = param_set_int(val, kp);
110 struct MPT3SAS_ADAPTER *ioc;
111
112 if (ret)
113 return ret;
114
08c4d550 115 /* global ioc spinlock to protect controller list on list operations */
f92363d1 116 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
08c4d550 117 spin_lock(&gioc_lock);
f92363d1
SR		 118 list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
119 ioc->fwfault_debug = mpt3sas_fwfault_debug;
08c4d550 120 spin_unlock(&gioc_lock);
f92363d1
SR		 121 return 0;
122}
123module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
124 param_get_int, &mpt3sas_fwfault_debug, 0644);
125
126/**
127 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
128 * @arg: input argument, used to derive ioc
129 *
130 * Return 0 if controller is removed from pci subsystem.
131 * Return -1 for other case.
132 */
133static int mpt3sas_remove_dead_ioc_func(void *arg)
134{
135 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
136 struct pci_dev *pdev;
137
138 if ((ioc == NULL))
139 return -1;
140
141 pdev = ioc->pdev;
142 if ((pdev == NULL))
143 return -1;
64cdb418 144 pci_stop_and_remove_bus_device_locked(pdev);
f92363d1
SR		 145 return 0;
146}
147
148/**
149 * _base_fault_reset_work - workq handling ioc fault conditions
150 * @work: input argument, used to derive ioc
151 * Context: sleep.
152 *
153 * Return nothing.
154 */
155static void
156_base_fault_reset_work(struct work_struct *work)
157{
158 struct MPT3SAS_ADAPTER *ioc =
159 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
160 unsigned long flags;
161 u32 doorbell;
162 int rc;
163 struct task_struct *p;
164
165
166 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
16e179bd 167 if (ioc->shost_recovery || ioc->pci_error_recovery)
f92363d1
SR		 168 goto rearm_timer;
169 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
170
171 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
172 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
173 pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
174 ioc->name);
175
16e179bd
SR		 176 /* It may be possible that EEH recovery can resolve some of
177 * pci bus failure issues rather removing the dead ioc function
178 * by considering controller is in a non-operational state. So
179 * here priority is given to the EEH recovery. If it doesn't
180 * not resolve this issue, mpt3sas driver will consider this
181 * controller to non-operational state and remove the dead ioc
182 * function.
183 */
184 if (ioc->non_operational_loop++ < 5) {
185 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
186 flags);
187 goto rearm_timer;
188 }
189
f92363d1
SR		 190 /*
191 * Call _scsih_flush_pending_cmds callback so that we flush all
192 * pending commands back to OS. This call is required to aovid
193 * deadlock at block layer. Dead IOC will fail to do diag reset,
194 * and this call is safe since dead ioc will never return any
195 * command back from HW.
196 */
197 ioc->schedule_dead_ioc_flush_running_cmds(ioc);
198 /*
199 * Set remove_host flag early since kernel thread will
200 * take some time to execute.
201 */
202 ioc->remove_host = 1;
203 /*Remove the Dead Host */
204 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
c84b06a4 205 "%s_dead_ioc_%d", ioc->driver_name, ioc->id);
f92363d1
SR		 206 if (IS_ERR(p))
207 pr_err(MPT3SAS_FMT
208 "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
209 ioc->name, __func__);
210 else
211 pr_err(MPT3SAS_FMT
212 "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
213 ioc->name, __func__);
214 return; /* don't rearm timer */
215 }
216
16e179bd
SR		 217 ioc->non_operational_loop = 0;
218
f92363d1
SR		 219 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
220 rc = mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
221 FORCE_BIG_HAMMER);
222 pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
223 __func__, (rc == 0) ? "success" : "failed");
224 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
225 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
226 mpt3sas_base_fault_info(ioc, doorbell &
227 MPI2_DOORBELL_DATA_MASK);
228 if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
229 MPI2_IOC_STATE_OPERATIONAL)
230 return; /* don't rearm timer */
231 }
232
233 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
234 rearm_timer:
235 if (ioc->fault_reset_work_q)
236 queue_delayed_work(ioc->fault_reset_work_q,
237 &ioc->fault_reset_work,
238 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
239 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
240}
241
242/**
243 * mpt3sas_base_start_watchdog - start the fault_reset_work_q
244 * @ioc: per adapter object
245 * Context: sleep.
246 *
247 * Return nothing.
248 */
249void
250mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
251{
252 unsigned long flags;
253
254 if (ioc->fault_reset_work_q)
255 return;
256
257 /* initialize fault polling */
258
259 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
260 snprintf(ioc->fault_reset_work_q_name,
c84b06a4
SR		 261 sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status",
262 ioc->driver_name, ioc->id);
f92363d1
SR		 263 ioc->fault_reset_work_q =
264 create_singlethread_workqueue(ioc->fault_reset_work_q_name);
265 if (!ioc->fault_reset_work_q) {
266 pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
267 ioc->name, __func__, __LINE__);
268 return;
269 }
270 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
271 if (ioc->fault_reset_work_q)
272 queue_delayed_work(ioc->fault_reset_work_q,
273 &ioc->fault_reset_work,
274 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
275 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
276}
277
278/**
279 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
280 * @ioc: per adapter object
281 * Context: sleep.
282 *
283 * Return nothing.
284 */
285void
286mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
287{
288 unsigned long flags;
289 struct workqueue_struct *wq;
290
291 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
292 wq = ioc->fault_reset_work_q;
293 ioc->fault_reset_work_q = NULL;
294 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
295 if (wq) {
4dc06fd8 296 if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
f92363d1
SR		 297 flush_workqueue(wq);
298 destroy_workqueue(wq);
299 }
300}
301
302/**
303 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
304 * @ioc: per adapter object
305 * @fault_code: fault code
306 *
307 * Return nothing.
308 */
309void
310mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
311{
312 pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
313 ioc->name, fault_code);
314}
315
316/**
317 * mpt3sas_halt_firmware - halt's mpt controller firmware
318 * @ioc: per adapter object
319 *
320 * For debugging timeout related issues. Writing 0xCOFFEE00
321 * to the doorbell register will halt controller firmware. With
322 * the purpose to stop both driver and firmware, the enduser can
323 * obtain a ring buffer from controller UART.
324 */
325void
326mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
327{
328 u32 doorbell;
329
330 if (!ioc->fwfault_debug)
331 return;
332
333 dump_stack();
334
335 doorbell = readl(&ioc->chip->Doorbell);
336 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
337 mpt3sas_base_fault_info(ioc , doorbell);
338 else {
339 writel(0xC0FFEE00, &ioc->chip->Doorbell);
340 pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
341 ioc->name);
342 }
343
344 if (ioc->fwfault_debug == 2)
345 for (;;)
346 ;
347 else
348 panic("panic in %s\n", __func__);
349}
350
f92363d1
SR		 351/**
352 * _base_sas_ioc_info - verbose translation of the ioc status
353 * @ioc: per adapter object
354 * @mpi_reply: reply mf payload returned from firmware
355 * @request_hdr: request mf
356 *
357 * Return nothing.
358 */
359static void
360_base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
361 MPI2RequestHeader_t *request_hdr)
362{
363 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
364 MPI2_IOCSTATUS_MASK;
365 char *desc = NULL;
366 u16 frame_sz;
367 char *func_str = NULL;
368
369 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
370 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
371 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
372 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
373 return;
374
375 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
376 return;
377
378 switch (ioc_status) {
379
380/****************************************************************************
381* Common IOCStatus values for all replies
382****************************************************************************/
383
384 case MPI2_IOCSTATUS_INVALID_FUNCTION:
385 desc = "invalid function";
386 break;
387 case MPI2_IOCSTATUS_BUSY:
388 desc = "busy";
389 break;
390 case MPI2_IOCSTATUS_INVALID_SGL:
391 desc = "invalid sgl";
392 break;
393 case MPI2_IOCSTATUS_INTERNAL_ERROR:
394 desc = "internal error";
395 break;
396 case MPI2_IOCSTATUS_INVALID_VPID:
397 desc = "invalid vpid";
398 break;
399 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
400 desc = "insufficient resources";
401 break;
b130b0d5
SS		 402 case MPI2_IOCSTATUS_INSUFFICIENT_POWER:
403 desc = "insufficient power";
404 break;
f92363d1
SR		 405 case MPI2_IOCSTATUS_INVALID_FIELD:
406 desc = "invalid field";
407 break;
408 case MPI2_IOCSTATUS_INVALID_STATE:
409 desc = "invalid state";
410 break;
411 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
412 desc = "op state not supported";
413 break;
414
415/****************************************************************************
416* Config IOCStatus values
417****************************************************************************/
418
419 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
420 desc = "config invalid action";
421 break;
422 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
423 desc = "config invalid type";
424 break;
425 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
426 desc = "config invalid page";
427 break;
428 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
429 desc = "config invalid data";
430 break;
431 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
432 desc = "config no defaults";
433 break;
434 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
435 desc = "config cant commit";
436 break;
437
438/****************************************************************************
439* SCSI IO Reply
440****************************************************************************/
441
442 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
443 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
444 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
445 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
446 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
447 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
448 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
449 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
450 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
451 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
452 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
453 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
454 break;
455
456/****************************************************************************
457* For use by SCSI Initiator and SCSI Target end-to-end data protection
458****************************************************************************/
459
460 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
461 desc = "eedp guard error";
462 break;
463 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
464 desc = "eedp ref tag error";
465 break;
466 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
467 desc = "eedp app tag error";
468 break;
469
470/****************************************************************************
471* SCSI Target values
472****************************************************************************/
473
474 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
475 desc = "target invalid io index";
476 break;
477 case MPI2_IOCSTATUS_TARGET_ABORTED:
478 desc = "target aborted";
479 break;
480 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
481 desc = "target no conn retryable";
482 break;
483 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
484 desc = "target no connection";
485 break;
486 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
487 desc = "target xfer count mismatch";
488 break;
489 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
490 desc = "target data offset error";
491 break;
492 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
493 desc = "target too much write data";
494 break;
495 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
496 desc = "target iu too short";
497 break;
498 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
499 desc = "target ack nak timeout";
500 break;
501 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
502 desc = "target nak received";
503 break;
504
505/****************************************************************************
506* Serial Attached SCSI values
507****************************************************************************/
508
509 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
510 desc = "smp request failed";
511 break;
512 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
513 desc = "smp data overrun";
514 break;
515
516/****************************************************************************
517* Diagnostic Buffer Post / Diagnostic Release values
518****************************************************************************/
519
520 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
521 desc = "diagnostic released";
522 break;
523 default:
524 break;
525 }
526
527 if (!desc)
528 return;
529
530 switch (request_hdr->Function) {
531 case MPI2_FUNCTION_CONFIG:
532 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
533 func_str = "config_page";
534 break;
535 case MPI2_FUNCTION_SCSI_TASK_MGMT:
536 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
537 func_str = "task_mgmt";
538 break;
539 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
540 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
541 func_str = "sas_iounit_ctl";
542 break;
543 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
544 frame_sz = sizeof(Mpi2SepRequest_t);
545 func_str = "enclosure";
546 break;
547 case MPI2_FUNCTION_IOC_INIT:
548 frame_sz = sizeof(Mpi2IOCInitRequest_t);
549 func_str = "ioc_init";
550 break;
551 case MPI2_FUNCTION_PORT_ENABLE:
552 frame_sz = sizeof(Mpi2PortEnableRequest_t);
553 func_str = "port_enable";
554 break;
555 case MPI2_FUNCTION_SMP_PASSTHROUGH:
556 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
557 func_str = "smp_passthru";
558 break;
559 default:
560 frame_sz = 32;
561 func_str = "unknown";
562 break;
563 }
564
565 pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
566 ioc->name, desc, ioc_status, request_hdr, func_str);
567
568 _debug_dump_mf(request_hdr, frame_sz/4);
569}
570
571/**
572 * _base_display_event_data - verbose translation of firmware asyn events
573 * @ioc: per adapter object
574 * @mpi_reply: reply mf payload returned from firmware
575 *
576 * Return nothing.
577 */
578static void
579_base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
580 Mpi2EventNotificationReply_t *mpi_reply)
581{
582 char *desc = NULL;
583 u16 event;
584
585 if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
586 return;
587
588 event = le16_to_cpu(mpi_reply->Event);
589
590 switch (event) {
591 case MPI2_EVENT_LOG_DATA:
592 desc = "Log Data";
593 break;
594 case MPI2_EVENT_STATE_CHANGE:
595 desc = "Status Change";
596 break;
597 case MPI2_EVENT_HARD_RESET_RECEIVED:
598 desc = "Hard Reset Received";
599 break;
600 case MPI2_EVENT_EVENT_CHANGE:
601 desc = "Event Change";
602 break;
603 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
604 desc = "Device Status Change";
605 break;
606 case MPI2_EVENT_IR_OPERATION_STATUS:
7786ab6a
SR		 607 if (!ioc->hide_ir_msg)
608 desc = "IR Operation Status";
f92363d1
SR		 609 break;
610 case MPI2_EVENT_SAS_DISCOVERY:
611 {
612 Mpi2EventDataSasDiscovery_t *event_data =
613 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
614 pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
615 (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
616 "start" : "stop");
617 if (event_data->DiscoveryStatus)
618 pr_info("discovery_status(0x%08x)",
619 le32_to_cpu(event_data->DiscoveryStatus));
620 pr_info("\n");
621 return;
622 }
623 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
624 desc = "SAS Broadcast Primitive";
625 break;
626 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
627 desc = "SAS Init Device Status Change";
628 break;
629 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
630 desc = "SAS Init Table Overflow";
631 break;
632 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
633 desc = "SAS Topology Change List";
634 break;
635 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
636 desc = "SAS Enclosure Device Status Change";
637 break;
638 case MPI2_EVENT_IR_VOLUME:
7786ab6a
SR		 639 if (!ioc->hide_ir_msg)
640 desc = "IR Volume";
f92363d1
SR		 641 break;
642 case MPI2_EVENT_IR_PHYSICAL_DISK:
7786ab6a
SR		 643 if (!ioc->hide_ir_msg)
644 desc = "IR Physical Disk";
f92363d1
SR		 645 break;
646 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7786ab6a
SR		 647 if (!ioc->hide_ir_msg)
648 desc = "IR Configuration Change List";
f92363d1
SR		 649 break;
650 case MPI2_EVENT_LOG_ENTRY_ADDED:
7786ab6a
SR		 651 if (!ioc->hide_ir_msg)
652 desc = "Log Entry Added";
f92363d1 653 break;
2d8ce8c9
SR		 654 case MPI2_EVENT_TEMP_THRESHOLD:
655 desc = "Temperature Threshold";
656 break;
f92363d1
SR		 657 }
658
659 if (!desc)
660 return;
661
662 pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
663}
f92363d1
SR		 664
665/**
666 * _base_sas_log_info - verbose translation of firmware log info
667 * @ioc: per adapter object
668 * @log_info: log info
669 *
670 * Return nothing.
671 */
672static void
673_base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
674{
675 union loginfo_type {
676 u32 loginfo;
677 struct {
678 u32 subcode:16;
679 u32 code:8;
680 u32 originator:4;
681 u32 bus_type:4;
682 } dw;
683 };
684 union loginfo_type sas_loginfo;
685 char *originator_str = NULL;
686
687 sas_loginfo.loginfo = log_info;
688 if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
689 return;
690
691 /* each nexus loss loginfo */
692 if (log_info == 0x31170000)
693 return;
694
695 /* eat the loginfos associated with task aborts */
696 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
697 0x31140000 || log_info == 0x31130000))
698 return;
699
700 switch (sas_loginfo.dw.originator) {
701 case 0:
702 originator_str = "IOP";
703 break;
704 case 1:
705 originator_str = "PL";
706 break;
707 case 2:
7786ab6a
SR		 708 if (!ioc->hide_ir_msg)
709 originator_str = "IR";
710 else
711 originator_str = "WarpDrive";
f92363d1
SR		 712 break;
713 }
714
715 pr_warn(MPT3SAS_FMT
716 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
717 ioc->name, log_info,
718 originator_str, sas_loginfo.dw.code,
719 sas_loginfo.dw.subcode);
720}
721
722/**
723 * _base_display_reply_info -
724 * @ioc: per adapter object
725 * @smid: system request message index
726 * @msix_index: MSIX table index supplied by the OS
727 * @reply: reply message frame(lower 32bit addr)
728 *
729 * Return nothing.
730 */
731static void
732_base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
733 u32 reply)
734{
735 MPI2DefaultReply_t *mpi_reply;
736 u16 ioc_status;
737 u32 loginfo = 0;
738
739 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
740 if (unlikely(!mpi_reply)) {
741 pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
742 ioc->name, __FILE__, __LINE__, __func__);
743 return;
744 }
745 ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
af009411 746
f92363d1
SR		 747 if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
748 (ioc->logging_level & MPT_DEBUG_REPLY)) {
749 _base_sas_ioc_info(ioc , mpi_reply,
750 mpt3sas_base_get_msg_frame(ioc, smid));
751 }
af009411 752
f92363d1
SR		 753 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
754 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
755 _base_sas_log_info(ioc, loginfo);
756 }
757
758 if (ioc_status || loginfo) {
759 ioc_status &= MPI2_IOCSTATUS_MASK;
760 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
761 }
762}
763
764/**
765 * mpt3sas_base_done - base internal command completion routine
766 * @ioc: per adapter object
767 * @smid: system request message index
768 * @msix_index: MSIX table index supplied by the OS
769 * @reply: reply message frame(lower 32bit addr)
770 *
771 * Return 1 meaning mf should be freed from _base_interrupt
772 * 0 means the mf is freed from this function.
773 */
774u8
775mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
776 u32 reply)
777{
778 MPI2DefaultReply_t *mpi_reply;
779
780 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
781 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
fd0331b3 782 return mpt3sas_check_for_pending_internal_cmds(ioc, smid);
f92363d1
SR		 783
784 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
785 return 1;
786
787 ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
788 if (mpi_reply) {
789 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
790 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
791 }
792 ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
793
794 complete(&ioc->base_cmds.done);
795 return 1;
796}
797
798/**
799 * _base_async_event - main callback handler for firmware asyn events
800 * @ioc: per adapter object
801 * @msix_index: MSIX table index supplied by the OS
802 * @reply: reply message frame(lower 32bit addr)
803 *
804 * Return 1 meaning mf should be freed from _base_interrupt
805 * 0 means the mf is freed from this function.
806 */
807static u8
808_base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
809{
810 Mpi2EventNotificationReply_t *mpi_reply;
811 Mpi2EventAckRequest_t *ack_request;
812 u16 smid;
fd0331b3 813 struct _event_ack_list *delayed_event_ack;
f92363d1
SR		 814
815 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
816 if (!mpi_reply)
817 return 1;
818 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
819 return 1;
af009411 820
f92363d1 821 _base_display_event_data(ioc, mpi_reply);
af009411 822
f92363d1
SR		 823 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
824 goto out;
825 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
826 if (!smid) {
fd0331b3
SS		 827 delayed_event_ack = kzalloc(sizeof(*delayed_event_ack),
828 GFP_ATOMIC);
829 if (!delayed_event_ack)
830 goto out;
831 INIT_LIST_HEAD(&delayed_event_ack->list);
832 delayed_event_ack->Event = mpi_reply->Event;
833 delayed_event_ack->EventContext = mpi_reply->EventContext;
834 list_add_tail(&delayed_event_ack->list,
835 &ioc->delayed_event_ack_list);
836 dewtprintk(ioc, pr_info(MPT3SAS_FMT
837 "DELAYED: EVENT ACK: event (0x%04x)\n",
838 ioc->name, le16_to_cpu(mpi_reply->Event)));
f92363d1
SR		 839 goto out;
840 }
841
842 ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
843 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
844 ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
845 ack_request->Event = mpi_reply->Event;
846 ack_request->EventContext = mpi_reply->EventContext;
847 ack_request->VF_ID = 0; /* TODO */
848 ack_request->VP_ID = 0;
849 mpt3sas_base_put_smid_default(ioc, smid);
850
851 out:
852
853 /* scsih callback handler */
854 mpt3sas_scsih_event_callback(ioc, msix_index, reply);
855
856 /* ctl callback handler */
857 mpt3sas_ctl_event_callback(ioc, msix_index, reply);
858
859 return 1;
860}
861
862/**
863 * _base_get_cb_idx - obtain the callback index
864 * @ioc: per adapter object
865 * @smid: system request message index
866 *
867 * Return callback index.
868 */
869static u8
870_base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
871{
872 int i;
873 u8 cb_idx;
874
875 if (smid < ioc->hi_priority_smid) {
876 i = smid - 1;
877 cb_idx = ioc->scsi_lookup[i].cb_idx;
878 } else if (smid < ioc->internal_smid) {
879 i = smid - ioc->hi_priority_smid;
880 cb_idx = ioc->hpr_lookup[i].cb_idx;
881 } else if (smid <= ioc->hba_queue_depth) {
882 i = smid - ioc->internal_smid;
883 cb_idx = ioc->internal_lookup[i].cb_idx;
884 } else
885 cb_idx = 0xFF;
886 return cb_idx;
887}
888
889/**
890 * _base_mask_interrupts - disable interrupts
891 * @ioc: per adapter object
892 *
893 * Disabling ResetIRQ, Reply and Doorbell Interrupts
894 *
895 * Return nothing.
896 */
897static void
898_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
899{
900 u32 him_register;
901
902 ioc->mask_interrupts = 1;
903 him_register = readl(&ioc->chip->HostInterruptMask);
904 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
905 writel(him_register, &ioc->chip->HostInterruptMask);
906 readl(&ioc->chip->HostInterruptMask);
907}
908
909/**
910 * _base_unmask_interrupts - enable interrupts
911 * @ioc: per adapter object
912 *
913 * Enabling only Reply Interrupts
914 *
915 * Return nothing.
916 */
917static void
918_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
919{
920 u32 him_register;
921
922 him_register = readl(&ioc->chip->HostInterruptMask);
923 him_register &= ~MPI2_HIM_RIM;
924 writel(him_register, &ioc->chip->HostInterruptMask);
925 ioc->mask_interrupts = 0;
926}
927
928union reply_descriptor {
929 u64 word;
930 struct {
931 u32 low;
932 u32 high;
933 } u;
934};
935
936/**
937 * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
938 * @irq: irq number (not used)
939 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
940 * @r: pt_regs pointer (not used)
941 *
942 * Return IRQ_HANDLE if processed, else IRQ_NONE.
943 */
944static irqreturn_t
945_base_interrupt(int irq, void *bus_id)
946{
947 struct adapter_reply_queue *reply_q = bus_id;
948 union reply_descriptor rd;
949 u32 completed_cmds;
950 u8 request_desript_type;
951 u16 smid;
952 u8 cb_idx;
953 u32 reply;
954 u8 msix_index = reply_q->msix_index;
955 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
956 Mpi2ReplyDescriptorsUnion_t *rpf;
957 u8 rc;
958
959 if (ioc->mask_interrupts)
960 return IRQ_NONE;
961
962 if (!atomic_add_unless(&reply_q->busy, 1, 1))
963 return IRQ_NONE;
964
965 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
966 request_desript_type = rpf->Default.ReplyFlags
967 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
968 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
969 atomic_dec(&reply_q->busy);
970 return IRQ_NONE;
971 }
972
973 completed_cmds = 0;
974 cb_idx = 0xFF;
975 do {
976 rd.word = le64_to_cpu(rpf->Words);
977 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
978 goto out;
979 reply = 0;
980 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
981 if (request_desript_type ==
982 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
983 request_desript_type ==
984 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
985 cb_idx = _base_get_cb_idx(ioc, smid);
986 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
987 (likely(mpt_callbacks[cb_idx] != NULL))) {
988 rc = mpt_callbacks[cb_idx](ioc, smid,
989 msix_index, 0);
990 if (rc)
991 mpt3sas_base_free_smid(ioc, smid);
992 }
993 } else if (request_desript_type ==
994 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
995 reply = le32_to_cpu(
996 rpf->AddressReply.ReplyFrameAddress);
997 if (reply > ioc->reply_dma_max_address ||
998 reply < ioc->reply_dma_min_address)
999 reply = 0;
1000 if (smid) {
1001 cb_idx = _base_get_cb_idx(ioc, smid);
1002 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1003 (likely(mpt_callbacks[cb_idx] != NULL))) {
1004 rc = mpt_callbacks[cb_idx](ioc, smid,
1005 msix_index, reply);
1006 if (reply)
1007 _base_display_reply_info(ioc,
1008 smid, msix_index, reply);
1009 if (rc)
1010 mpt3sas_base_free_smid(ioc,
1011 smid);
1012 }
1013 } else {
1014 _base_async_event(ioc, msix_index, reply);
1015 }
1016
1017 /* reply free queue handling */
1018 if (reply) {
1019 ioc->reply_free_host_index =
1020 (ioc->reply_free_host_index ==
1021 (ioc->reply_free_queue_depth - 1)) ?
1022 0 : ioc->reply_free_host_index + 1;
1023 ioc->reply_free[ioc->reply_free_host_index] =
1024 cpu_to_le32(reply);
1025 wmb();
1026 writel(ioc->reply_free_host_index,
1027 &ioc->chip->ReplyFreeHostIndex);
1028 }
1029 }
1030
1031 rpf->Words = cpu_to_le64(ULLONG_MAX);
1032 reply_q->reply_post_host_index =
1033 (reply_q->reply_post_host_index ==
1034 (ioc->reply_post_queue_depth - 1)) ? 0 :
1035 reply_q->reply_post_host_index + 1;
1036 request_desript_type =
1037 reply_q->reply_post_free[reply_q->reply_post_host_index].
1038 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1039 completed_cmds++;
1040 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1041 goto out;
1042 if (!reply_q->reply_post_host_index)
1043 rpf = reply_q->reply_post_free;
1044 else
1045 rpf++;
1046 } while (1);
1047
1048 out:
1049
1050 if (!completed_cmds) {
1051 atomic_dec(&reply_q->busy);
1052 return IRQ_NONE;
1053 }
1054
1055 wmb();
7786ab6a
SR		 1056 if (ioc->is_warpdrive) {
1057 writel(reply_q->reply_post_host_index,
1058 ioc->reply_post_host_index[msix_index]);
1059 atomic_dec(&reply_q->busy);
1060 return IRQ_HANDLED;
1061 }
fb77bb53
SR		 1062
1063 /* Update Reply Post Host Index.
1064 * For those HBA's which support combined reply queue feature
1065 * 1. Get the correct Supplemental Reply Post Host Index Register.
1066 * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1067 * Index Register address bank i.e replyPostRegisterIndex[],
1068 * 2. Then update this register with new reply host index value
1069 * in ReplyPostIndex field and the MSIxIndex field with
1070 * msix_index value reduced to a value between 0 and 7,
1071 * using a modulo 8 operation. Since each Supplemental Reply Post
1072 * Host Index Register supports 8 MSI-X vectors.
1073 *
1074 * For other HBA's just update the Reply Post Host Index register with
1075 * new reply host index value in ReplyPostIndex Field and msix_index
1076 * value in MSIxIndex field.
1077 */
1078 if (ioc->msix96_vector)
1079 writel(reply_q->reply_post_host_index | ((msix_index & 7) <<
1080 MPI2_RPHI_MSIX_INDEX_SHIFT),
1081 ioc->replyPostRegisterIndex[msix_index/8]);
1082 else
1083 writel(reply_q->reply_post_host_index | (msix_index <<
1084 MPI2_RPHI_MSIX_INDEX_SHIFT),
1085 &ioc->chip->ReplyPostHostIndex);
f92363d1
SR		 1086 atomic_dec(&reply_q->busy);
1087 return IRQ_HANDLED;
1088}
1089
1090/**
1091 * _base_is_controller_msix_enabled - is controller support muli-reply queues
1092 * @ioc: per adapter object
1093 *
1094 */
1095static inline int
1096_base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1097{
1098 return (ioc->facts.IOCCapabilities &
1099 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1100}
1101
1102/**
1103 * mpt3sas_base_flush_reply_queues - flushing the MSIX reply queues
1104 * @ioc: per adapter object
1105 * Context: ISR conext
1106 *
1107 * Called when a Task Management request has completed. We want
1108 * to flush the other reply queues so all the outstanding IO has been
1109 * completed back to OS before we process the TM completetion.
1110 *
1111 * Return nothing.
1112 */
1113void
1114mpt3sas_base_flush_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1115{
1116 struct adapter_reply_queue *reply_q;
1117
1118 /* If MSIX capability is turned off
1119 * then multi-queues are not enabled
1120 */
1121 if (!_base_is_controller_msix_enabled(ioc))
1122 return;
1123
1124 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1125 if (ioc->shost_recovery)
1126 return;
1127 /* TMs are on msix_index == 0 */
1128 if (reply_q->msix_index == 0)
1129 continue;
1130 _base_interrupt(reply_q->vector, (void *)reply_q);
1131 }
1132}
1133
1134/**
1135 * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1136 * @cb_idx: callback index
1137 *
1138 * Return nothing.
1139 */
1140void
1141mpt3sas_base_release_callback_handler(u8 cb_idx)
1142{
1143 mpt_callbacks[cb_idx] = NULL;
1144}
1145
1146/**
1147 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1148 * @cb_func: callback function
1149 *
1150 * Returns cb_func.
1151 */
1152u8
1153mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1154{
1155 u8 cb_idx;
1156
1157 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1158 if (mpt_callbacks[cb_idx] == NULL)
1159 break;
1160
1161 mpt_callbacks[cb_idx] = cb_func;
1162 return cb_idx;
1163}
1164
1165/**
1166 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1167 *
1168 * Return nothing.
1169 */
1170void
1171mpt3sas_base_initialize_callback_handler(void)
1172{
1173 u8 cb_idx;
1174
1175 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1176 mpt3sas_base_release_callback_handler(cb_idx);
1177}
1178
1179
1180/**
1181 * _base_build_zero_len_sge - build zero length sg entry
1182 * @ioc: per adapter object
1183 * @paddr: virtual address for SGE
1184 *
1185 * Create a zero length scatter gather entry to insure the IOCs hardware has
1186 * something to use if the target device goes brain dead and tries
1187 * to send data even when none is asked for.
1188 *
1189 * Return nothing.
1190 */
1191static void
1192_base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1193{
1194 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1195 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1196 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1197 MPI2_SGE_FLAGS_SHIFT);
1198 ioc->base_add_sg_single(paddr, flags_length, -1);
1199}
1200
1201/**
1202 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1203 * @paddr: virtual address for SGE
1204 * @flags_length: SGE flags and data transfer length
1205 * @dma_addr: Physical address
1206 *
1207 * Return nothing.
1208 */
1209static void
1210_base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1211{
1212 Mpi2SGESimple32_t *sgel = paddr;
1213
1214 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1215 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1216 sgel->FlagsLength = cpu_to_le32(flags_length);
1217 sgel->Address = cpu_to_le32(dma_addr);
1218}
1219
1220
1221/**
1222 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
1223 * @paddr: virtual address for SGE
1224 * @flags_length: SGE flags and data transfer length
1225 * @dma_addr: Physical address
1226 *
1227 * Return nothing.
1228 */
1229static void
1230_base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1231{
1232 Mpi2SGESimple64_t *sgel = paddr;
1233
1234 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
1235 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1236 sgel->FlagsLength = cpu_to_le32(flags_length);
1237 sgel->Address = cpu_to_le64(dma_addr);
1238}
1239
1240/**
1241 * _base_get_chain_buffer_tracker - obtain chain tracker
1242 * @ioc: per adapter object
1243 * @smid: smid associated to an IO request
1244 *
1245 * Returns chain tracker(from ioc->free_chain_list)
1246 */
1247static struct chain_tracker *
1248_base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1249{
1250 struct chain_tracker *chain_req;
1251 unsigned long flags;
1252
1253 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1254 if (list_empty(&ioc->free_chain_list)) {
1255 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1256 dfailprintk(ioc, pr_warn(MPT3SAS_FMT
1257 "chain buffers not available\n", ioc->name));
1258 return NULL;
1259 }
1260 chain_req = list_entry(ioc->free_chain_list.next,
1261 struct chain_tracker, tracker_list);
1262 list_del_init(&chain_req->tracker_list);
1263 list_add_tail(&chain_req->tracker_list,
1264 &ioc->scsi_lookup[smid - 1].chain_list);
1265 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1266 return chain_req;
1267}
1268
1269
1270/**
1271 * _base_build_sg - build generic sg
1272 * @ioc: per adapter object
1273 * @psge: virtual address for SGE
1274 * @data_out_dma: physical address for WRITES
1275 * @data_out_sz: data xfer size for WRITES
1276 * @data_in_dma: physical address for READS
1277 * @data_in_sz: data xfer size for READS
1278 *
1279 * Return nothing.
1280 */
1281static void
1282_base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
1283 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1284 size_t data_in_sz)
1285{
1286 u32 sgl_flags;
1287
1288 if (!data_out_sz && !data_in_sz) {
1289 _base_build_zero_len_sge(ioc, psge);
1290 return;
1291 }
1292
1293 if (data_out_sz && data_in_sz) {
1294 /* WRITE sgel first */
1295 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1296 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
1297 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1298 ioc->base_add_sg_single(psge, sgl_flags |
1299 data_out_sz, data_out_dma);
1300
1301 /* incr sgel */
1302 psge += ioc->sge_size;
1303
1304 /* READ sgel last */
1305 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1306 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1307 MPI2_SGE_FLAGS_END_OF_LIST);
1308 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1309 ioc->base_add_sg_single(psge, sgl_flags |
1310 data_in_sz, data_in_dma);
1311 } else if (data_out_sz) /* WRITE */ {
1312 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1313 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1314 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
1315 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1316 ioc->base_add_sg_single(psge, sgl_flags |
1317 data_out_sz, data_out_dma);
1318 } else if (data_in_sz) /* READ */ {
1319 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1320 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1321 MPI2_SGE_FLAGS_END_OF_LIST);
1322 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1323 ioc->base_add_sg_single(psge, sgl_flags |
1324 data_in_sz, data_in_dma);
1325 }
1326}
1327
1328/* IEEE format sgls */
1329
1330/**
1331 * _base_add_sg_single_ieee - add sg element for IEEE format
1332 * @paddr: virtual address for SGE
1333 * @flags: SGE flags
1334 * @chain_offset: number of 128 byte elements from start of segment
1335 * @length: data transfer length
1336 * @dma_addr: Physical address
1337 *
1338 * Return nothing.
1339 */
1340static void
1341_base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
1342 dma_addr_t dma_addr)
1343{
1344 Mpi25IeeeSgeChain64_t *sgel = paddr;
1345
1346 sgel->Flags = flags;
1347 sgel->NextChainOffset = chain_offset;
1348 sgel->Length = cpu_to_le32(length);
1349 sgel->Address = cpu_to_le64(dma_addr);
1350}
1351
1352/**
1353 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
1354 * @ioc: per adapter object
1355 * @paddr: virtual address for SGE
1356 *
1357 * Create a zero length scatter gather entry to insure the IOCs hardware has
1358 * something to use if the target device goes brain dead and tries
1359 * to send data even when none is asked for.
1360 *
1361 * Return nothing.
1362 */
1363static void
1364_base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1365{
1366 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1367 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
1368 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
b130b0d5 1369
f92363d1
SR		 1370 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
1371}
1372
471ef9d4
SR		 1373/**
1374 * _base_build_sg_scmd - main sg creation routine
1375 * @ioc: per adapter object
1376 * @scmd: scsi command
1377 * @smid: system request message index
1378 * Context: none.
1379 *
1380 * The main routine that builds scatter gather table from a given
1381 * scsi request sent via the .queuecommand main handler.
1382 *
1383 * Returns 0 success, anything else error
1384 */
1385static int
1386_base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
1387 struct scsi_cmnd *scmd, u16 smid)
1388{
1389 Mpi2SCSIIORequest_t *mpi_request;
1390 dma_addr_t chain_dma;
1391 struct scatterlist *sg_scmd;
1392 void *sg_local, *chain;
1393 u32 chain_offset;
1394 u32 chain_length;
1395 u32 chain_flags;
1396 int sges_left;
1397 u32 sges_in_segment;
1398 u32 sgl_flags;
1399 u32 sgl_flags_last_element;
1400 u32 sgl_flags_end_buffer;
1401 struct chain_tracker *chain_req;
1402
1403 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1404
1405 /* init scatter gather flags */
1406 sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
1407 if (scmd->sc_data_direction == DMA_TO_DEVICE)
1408 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
1409 sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
1410 << MPI2_SGE_FLAGS_SHIFT;
1411 sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
1412 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
1413 << MPI2_SGE_FLAGS_SHIFT;
1414 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1415
1416 sg_scmd = scsi_sglist(scmd);
1417 sges_left = scsi_dma_map(scmd);
1418 if (sges_left < 0) {
1419 sdev_printk(KERN_ERR, scmd->device,
1420 "pci_map_sg failed: request for %d bytes!\n",
1421 scsi_bufflen(scmd));
1422 return -ENOMEM;
1423 }
1424
1425 sg_local = &mpi_request->SGL;
1426 sges_in_segment = ioc->max_sges_in_main_message;
1427 if (sges_left <= sges_in_segment)
1428 goto fill_in_last_segment;
1429
1430 mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
1431 (sges_in_segment * ioc->sge_size))/4;
1432
1433 /* fill in main message segment when there is a chain following */
1434 while (sges_in_segment) {
1435 if (sges_in_segment == 1)
1436 ioc->base_add_sg_single(sg_local,
1437 sgl_flags_last_element | sg_dma_len(sg_scmd),
1438 sg_dma_address(sg_scmd));
1439 else
1440 ioc->base_add_sg_single(sg_local, sgl_flags |
1441 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1442 sg_scmd = sg_next(sg_scmd);
1443 sg_local += ioc->sge_size;
1444 sges_left--;
1445 sges_in_segment--;
1446 }
1447
1448 /* initializing the chain flags and pointers */
1449 chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
1450 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1451 if (!chain_req)
1452 return -1;
1453 chain = chain_req->chain_buffer;
1454 chain_dma = chain_req->chain_buffer_dma;
1455 do {
1456 sges_in_segment = (sges_left <=
1457 ioc->max_sges_in_chain_message) ? sges_left :
1458 ioc->max_sges_in_chain_message;
1459 chain_offset = (sges_left == sges_in_segment) ?
1460 0 : (sges_in_segment * ioc->sge_size)/4;
1461 chain_length = sges_in_segment * ioc->sge_size;
1462 if (chain_offset) {
1463 chain_offset = chain_offset <<
1464 MPI2_SGE_CHAIN_OFFSET_SHIFT;
1465 chain_length += ioc->sge_size;
1466 }
1467 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
1468 chain_length, chain_dma);
1469 sg_local = chain;
1470 if (!chain_offset)
1471 goto fill_in_last_segment;
1472
1473 /* fill in chain segments */
1474 while (sges_in_segment) {
1475 if (sges_in_segment == 1)
1476 ioc->base_add_sg_single(sg_local,
1477 sgl_flags_last_element |
1478 sg_dma_len(sg_scmd),
1479 sg_dma_address(sg_scmd));
1480 else
1481 ioc->base_add_sg_single(sg_local, sgl_flags |
1482 sg_dma_len(sg_scmd),
1483 sg_dma_address(sg_scmd));
1484 sg_scmd = sg_next(sg_scmd);
1485 sg_local += ioc->sge_size;
1486 sges_left--;
1487 sges_in_segment--;
1488 }
1489
1490 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1491 if (!chain_req)
1492 return -1;
1493 chain = chain_req->chain_buffer;
1494 chain_dma = chain_req->chain_buffer_dma;
1495 } while (1);
1496
1497
1498 fill_in_last_segment:
1499
1500 /* fill the last segment */
1501 while (sges_left) {
1502 if (sges_left == 1)
1503 ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
1504 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1505 else
1506 ioc->base_add_sg_single(sg_local, sgl_flags |
1507 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1508 sg_scmd = sg_next(sg_scmd);
1509 sg_local += ioc->sge_size;
1510 sges_left--;
1511 }
1512
1513 return 0;
1514}
1515
f92363d1
SR		 1516/**
1517 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
1518 * @ioc: per adapter object
1519 * @scmd: scsi command
1520 * @smid: system request message index
1521 * Context: none.
1522 *
1523 * The main routine that builds scatter gather table from a given
1524 * scsi request sent via the .queuecommand main handler.
1525 *
1526 * Returns 0 success, anything else error
1527 */
1528static int
1529_base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
1530 struct scsi_cmnd *scmd, u16 smid)
1531{
1532 Mpi2SCSIIORequest_t *mpi_request;
1533 dma_addr_t chain_dma;
1534 struct scatterlist *sg_scmd;
1535 void *sg_local, *chain;
1536 u32 chain_offset;
1537 u32 chain_length;
f92363d1
SR		 1538 int sges_left;
1539 u32 sges_in_segment;
1540 u8 simple_sgl_flags;
1541 u8 simple_sgl_flags_last;
1542 u8 chain_sgl_flags;
1543 struct chain_tracker *chain_req;
1544
1545 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1546
1547 /* init scatter gather flags */
1548 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1549 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1550 simple_sgl_flags_last = simple_sgl_flags |
1551 MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1552 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
1553 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1554
1555 sg_scmd = scsi_sglist(scmd);
1556 sges_left = scsi_dma_map(scmd);
62f5c74c 1557 if (sges_left < 0) {
f92363d1
SR		 1558 sdev_printk(KERN_ERR, scmd->device,
1559 "pci_map_sg failed: request for %d bytes!\n",
1560 scsi_bufflen(scmd));
1561 return -ENOMEM;
1562 }
1563
1564 sg_local = &mpi_request->SGL;
1565 sges_in_segment = (ioc->request_sz -
1566 offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
1567 if (sges_left <= sges_in_segment)
1568 goto fill_in_last_segment;
1569
1570 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
1571 (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
1572
1573 /* fill in main message segment when there is a chain following */
1574 while (sges_in_segment > 1) {
1575 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1576 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1577 sg_scmd = sg_next(sg_scmd);
1578 sg_local += ioc->sge_size_ieee;
1579 sges_left--;
1580 sges_in_segment--;
1581 }
1582
25ef16d0 1583 /* initializing the pointers */
f92363d1
SR		 1584 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1585 if (!chain_req)
1586 return -1;
1587 chain = chain_req->chain_buffer;
1588 chain_dma = chain_req->chain_buffer_dma;
1589 do {
1590 sges_in_segment = (sges_left <=
1591 ioc->max_sges_in_chain_message) ? sges_left :
1592 ioc->max_sges_in_chain_message;
1593 chain_offset = (sges_left == sges_in_segment) ?
1594 0 : sges_in_segment;
1595 chain_length = sges_in_segment * ioc->sge_size_ieee;
1596 if (chain_offset)
1597 chain_length += ioc->sge_size_ieee;
1598 _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
1599 chain_offset, chain_length, chain_dma);
1600
1601 sg_local = chain;
1602 if (!chain_offset)
1603 goto fill_in_last_segment;
1604
1605 /* fill in chain segments */
1606 while (sges_in_segment) {
1607 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1608 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1609 sg_scmd = sg_next(sg_scmd);
1610 sg_local += ioc->sge_size_ieee;
1611 sges_left--;
1612 sges_in_segment--;
1613 }
1614
1615 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1616 if (!chain_req)
1617 return -1;
1618 chain = chain_req->chain_buffer;
1619 chain_dma = chain_req->chain_buffer_dma;
1620 } while (1);
1621
1622
1623 fill_in_last_segment:
1624
1625 /* fill the last segment */
62f5c74c 1626 while (sges_left > 0) {
f92363d1
SR		 1627 if (sges_left == 1)
1628 _base_add_sg_single_ieee(sg_local,
1629 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
1630 sg_dma_address(sg_scmd));
1631 else
1632 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1633 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1634 sg_scmd = sg_next(sg_scmd);
1635 sg_local += ioc->sge_size_ieee;
1636 sges_left--;
1637 }
1638
1639 return 0;
1640}
1641
1642/**
1643 * _base_build_sg_ieee - build generic sg for IEEE format
1644 * @ioc: per adapter object
1645 * @psge: virtual address for SGE
1646 * @data_out_dma: physical address for WRITES
1647 * @data_out_sz: data xfer size for WRITES
1648 * @data_in_dma: physical address for READS
1649 * @data_in_sz: data xfer size for READS
1650 *
1651 * Return nothing.
1652 */
1653static void
1654_base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
1655 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1656 size_t data_in_sz)
1657{
1658 u8 sgl_flags;
1659
1660 if (!data_out_sz && !data_in_sz) {
1661 _base_build_zero_len_sge_ieee(ioc, psge);
1662 return;
1663 }
1664
1665 if (data_out_sz && data_in_sz) {
1666 /* WRITE sgel first */
1667 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1668 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1669 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1670 data_out_dma);
1671
1672 /* incr sgel */
1673 psge += ioc->sge_size_ieee;
1674
1675 /* READ sgel last */
1676 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1677 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1678 data_in_dma);
1679 } else if (data_out_sz) /* WRITE */ {
1680 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1681 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1682 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1683 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1684 data_out_dma);
1685 } else if (data_in_sz) /* READ */ {
1686 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1687 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1688 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1689 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1690 data_in_dma);
1691 }
1692}
1693
1694#define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
1695
1696/**
1697 * _base_config_dma_addressing - set dma addressing
1698 * @ioc: per adapter object
1699 * @pdev: PCI device struct
1700 *
1701 * Returns 0 for success, non-zero for failure.
1702 */
1703static int
1704_base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
1705{
1706 struct sysinfo s;
9b05c91a
SR		 1707 u64 consistent_dma_mask;
1708
1709 if (ioc->dma_mask)
1710 consistent_dma_mask = DMA_BIT_MASK(64);
1711 else
1712 consistent_dma_mask = DMA_BIT_MASK(32);
f92363d1
SR		 1713
1714 if (sizeof(dma_addr_t) > 4) {
1715 const uint64_t required_mask =
1716 dma_get_required_mask(&pdev->dev);
1717 if ((required_mask > DMA_BIT_MASK(32)) &&
1718 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
9b05c91a 1719 !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
f92363d1
SR		 1720 ioc->base_add_sg_single = &_base_add_sg_single_64;
1721 ioc->sge_size = sizeof(Mpi2SGESimple64_t);
9b05c91a 1722 ioc->dma_mask = 64;
f92363d1
SR		 1723 goto out;
1724 }
1725 }
1726
1727 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1728 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1729 ioc->base_add_sg_single = &_base_add_sg_single_32;
1730 ioc->sge_size = sizeof(Mpi2SGESimple32_t);
9b05c91a 1731 ioc->dma_mask = 32;
f92363d1
SR		 1732 } else
1733 return -ENODEV;
1734
1735 out:
1736 si_meminfo(&s);
1737 pr_info(MPT3SAS_FMT
9b05c91a
SR		 1738 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
1739 ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
1740
1741 return 0;
1742}
f92363d1 1743
9b05c91a
SR		 1744static int
1745_base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
1746 struct pci_dev *pdev)
1747{
1748 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1749 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
1750 return -ENODEV;
1751 }
f92363d1
SR		 1752 return 0;
1753}
1754
1755/**
1756 * _base_check_enable_msix - checks MSIX capabable.
1757 * @ioc: per adapter object
1758 *
1759 * Check to see if card is capable of MSIX, and set number
1760 * of available msix vectors
1761 */
1762static int
1763_base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1764{
1765 int base;
1766 u16 message_control;
1767
42081173
SR		 1768 /* Check whether controller SAS2008 B0 controller,
1769 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
1770 */
1771 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
1772 ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
1773 return -EINVAL;
1774 }
1775
f92363d1
SR		 1776 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
1777 if (!base) {
1778 dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
1779 ioc->name));
1780 return -EINVAL;
1781 }
1782
1783 /* get msix vector count */
42081173
SR		 1784 /* NUMA_IO not supported for older controllers */
1785 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
1786 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
1787 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
1788 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
1789 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
1790 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
1791 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
1792 ioc->msix_vector_count = 1;
1793 else {
1794 pci_read_config_word(ioc->pdev, base + 2, &message_control);
1795 ioc->msix_vector_count = (message_control & 0x3FF) + 1;
1796 }
f92363d1
SR		 1797 dinitprintk(ioc, pr_info(MPT3SAS_FMT
1798 "msix is supported, vector_count(%d)\n",
1799 ioc->name, ioc->msix_vector_count));
1800 return 0;
1801}
1802
1803/**
1804 * _base_free_irq - free irq
1805 * @ioc: per adapter object
1806 *
1807 * Freeing respective reply_queue from the list.
1808 */
1809static void
1810_base_free_irq(struct MPT3SAS_ADAPTER *ioc)
1811{
1812 struct adapter_reply_queue *reply_q, *next;
1813
1814 if (list_empty(&ioc->reply_queue_list))
1815 return;
1816
1817 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1818 list_del(&reply_q->list);
64038301
SPS		 1819 if (smp_affinity_enable) {
1820 irq_set_affinity_hint(reply_q->vector, NULL);
1821 free_cpumask_var(reply_q->affinity_hint);
1822 }
f92363d1
SR		 1823 synchronize_irq(reply_q->vector);
1824 free_irq(reply_q->vector, reply_q);
1825 kfree(reply_q);
1826 }
1827}
1828
1829/**
1830 * _base_request_irq - request irq
1831 * @ioc: per adapter object
1832 * @index: msix index into vector table
1833 * @vector: irq vector
1834 *
1835 * Inserting respective reply_queue into the list.
1836 */
1837static int
1838_base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index, u32 vector)
1839{
1840 struct adapter_reply_queue *reply_q;
1841 int r;
1842
1843 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
1844 if (!reply_q) {
1845 pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
1846 ioc->name, (int)sizeof(struct adapter_reply_queue));
1847 return -ENOMEM;
1848 }
1849 reply_q->ioc = ioc;
1850 reply_q->msix_index = index;
1851 reply_q->vector = vector;
14b3114d 1852
64038301
SPS		 1853 if (smp_affinity_enable) {
1854 if (!zalloc_cpumask_var(&reply_q->affinity_hint, GFP_KERNEL)) {
1855 kfree(reply_q);
1856 return -ENOMEM;
1857 }
1858 cpumask_clear(reply_q->affinity_hint);
1859 }
14b3114d 1860
f92363d1
SR		 1861 atomic_set(&reply_q->busy, 0);
1862 if (ioc->msix_enable)
1863 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
c84b06a4 1864 ioc->driver_name, ioc->id, index);
f92363d1
SR		 1865 else
1866 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
c84b06a4 1867 ioc->driver_name, ioc->id);
f92363d1
SR		 1868 r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name,
1869 reply_q);
1870 if (r) {
1871 pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
1872 reply_q->name, vector);
1873 kfree(reply_q);
64038301 1874 free_cpumask_var(reply_q->affinity_hint);
f92363d1
SR		 1875 return -EBUSY;
1876 }
1877
1878 INIT_LIST_HEAD(&reply_q->list);
1879 list_add_tail(&reply_q->list, &ioc->reply_queue_list);
1880 return 0;
1881}
1882
1883/**
1884 * _base_assign_reply_queues - assigning msix index for each cpu
1885 * @ioc: per adapter object
1886 *
1887 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
1888 *
1889 * It would nice if we could call irq_set_affinity, however it is not
1890 * an exported symbol
1891 */
1892static void
1893_base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1894{
91b265bf 1895 unsigned int cpu, nr_cpus, nr_msix, index = 0;
14b3114d 1896 struct adapter_reply_queue *reply_q;
f92363d1
SR		 1897
1898 if (!_base_is_controller_msix_enabled(ioc))
1899 return;
1900
1901 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
1902
91b265bf
MP		 1903 nr_cpus = num_online_cpus();
1904 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
1905 ioc->facts.MaxMSIxVectors);
1906 if (!nr_msix)
1907 return;
f92363d1 1908
91b265bf
MP		 1909 cpu = cpumask_first(cpu_online_mask);
1910
14b3114d
SR		 1911 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1912
91b265bf
MP		 1913 unsigned int i, group = nr_cpus / nr_msix;
1914
14b3114d
SR		 1915 if (cpu >= nr_cpus)
1916 break;
1917
91b265bf
MP		 1918 if (index < nr_cpus % nr_msix)
1919 group++;
1920
1921 for (i = 0 ; i < group ; i++) {
1922 ioc->cpu_msix_table[cpu] = index;
64038301
SPS		 1923 if (smp_affinity_enable)
1924 cpumask_or(reply_q->affinity_hint,
14b3114d 1925 reply_q->affinity_hint, get_cpu_mask(cpu));
91b265bf 1926 cpu = cpumask_next(cpu, cpu_online_mask);
f92363d1 1927 }
64038301
SPS		 1928 if (smp_affinity_enable)
1929 if (irq_set_affinity_hint(reply_q->vector,
14b3114d 1930 reply_q->affinity_hint))
64038301
SPS		 1931 dinitprintk(ioc, pr_info(MPT3SAS_FMT
1932 "Err setting affinity hint to irq vector %d\n",
1933 ioc->name, reply_q->vector));
91b265bf 1934 index++;
14b3114d 1935 }
f92363d1
SR		 1936}
1937
1938/**
1939 * _base_disable_msix - disables msix
1940 * @ioc: per adapter object
1941 *
1942 */
1943static void
1944_base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
1945{
1946 if (!ioc->msix_enable)
1947 return;
1948 pci_disable_msix(ioc->pdev);
1949 ioc->msix_enable = 0;
1950}
1951
1952/**
1953 * _base_enable_msix - enables msix, failback to io_apic
1954 * @ioc: per adapter object
1955 *
1956 */
1957static int
1958_base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1959{
1960 struct msix_entry *entries, *a;
1961 int r;
1962 int i;
1963 u8 try_msix = 0;
1964
f92363d1
SR		 1965 if (msix_disable == -1 || msix_disable == 0)
1966 try_msix = 1;
1967
1968 if (!try_msix)
1969 goto try_ioapic;
1970
1971 if (_base_check_enable_msix(ioc) != 0)
1972 goto try_ioapic;
1973
1974 ioc->reply_queue_count = min_t(int, ioc->cpu_count,
1975 ioc->msix_vector_count);
1976
9c500060
SR		 1977 printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
1978 ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
1979 ioc->cpu_count, max_msix_vectors);
1980
9b05c91a
SR		 1981 if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
1982 max_msix_vectors = 8;
1983
9c500060
SR		 1984 if (max_msix_vectors > 0) {
1985 ioc->reply_queue_count = min_t(int, max_msix_vectors,
1986 ioc->reply_queue_count);
1987 ioc->msix_vector_count = ioc->reply_queue_count;
9b05c91a
SR		 1988 } else if (max_msix_vectors == 0)
1989 goto try_ioapic;
9c500060 1990
64038301
SPS		 1991 if (ioc->msix_vector_count < ioc->cpu_count)
1992 smp_affinity_enable = 0;
1993
f92363d1
SR		 1994 entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry),
1995 GFP_KERNEL);
1996 if (!entries) {
1997 dfailprintk(ioc, pr_info(MPT3SAS_FMT
1998 "kcalloc failed @ at %s:%d/%s() !!!\n",
1999 ioc->name, __FILE__, __LINE__, __func__));
2000 goto try_ioapic;
2001 }
2002
2003 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++)
2004 a->entry = i;
2005
6bfa6907 2006 r = pci_enable_msix_exact(ioc->pdev, entries, ioc->reply_queue_count);
f92363d1
SR		 2007 if (r) {
2008 dfailprintk(ioc, pr_info(MPT3SAS_FMT
6bfa6907 2009 "pci_enable_msix_exact failed (r=%d) !!!\n",
f92363d1
SR		 2010 ioc->name, r));
2011 kfree(entries);
2012 goto try_ioapic;
2013 }
2014
2015 ioc->msix_enable = 1;
2016 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) {
2017 r = _base_request_irq(ioc, i, a->vector);
2018 if (r) {
2019 _base_free_irq(ioc);
2020 _base_disable_msix(ioc);
2021 kfree(entries);
2022 goto try_ioapic;
2023 }
2024 }
2025
2026 kfree(entries);
2027 return 0;
2028
2029/* failback to io_apic interrupt routing */
2030 try_ioapic:
2031
9b05c91a 2032 ioc->reply_queue_count = 1;
f92363d1
SR		 2033 r = _base_request_irq(ioc, 0, ioc->pdev->irq);
2034
2035 return r;
2036}
2037
580d4e31
SR		 2038/**
2039 * mpt3sas_base_unmap_resources - free controller resources
2040 * @ioc: per adapter object
2041 */
2042void
2043mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
2044{
2045 struct pci_dev *pdev = ioc->pdev;
2046
2047 dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n",
2048 ioc->name, __func__));
2049
2050 _base_free_irq(ioc);
2051 _base_disable_msix(ioc);
2052
5f985d88 2053 if (ioc->msix96_vector) {
580d4e31 2054 kfree(ioc->replyPostRegisterIndex);
5f985d88
TH		 2055 ioc->replyPostRegisterIndex = NULL;
2056 }
580d4e31
SR		 2057
2058 if (ioc->chip_phys) {
2059 iounmap(ioc->chip);
2060 ioc->chip_phys = 0;
2061 }
2062
2063 if (pci_is_enabled(pdev)) {
2064 pci_release_selected_regions(ioc->pdev, ioc->bars);
2065 pci_disable_pcie_error_reporting(pdev);
2066 pci_disable_device(pdev);
2067 }
2068}
2069
f92363d1
SR		 2070/**
2071 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
2072 * @ioc: per adapter object
2073 *
2074 * Returns 0 for success, non-zero for failure.
2075 */
2076int
2077mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
2078{
2079 struct pci_dev *pdev = ioc->pdev;
2080 u32 memap_sz;
2081 u32 pio_sz;
2082 int i, r = 0;
2083 u64 pio_chip = 0;
2084 u64 chip_phys = 0;
2085 struct adapter_reply_queue *reply_q;
2086
2087 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
2088 ioc->name, __func__));
2089
2090 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
2091 if (pci_enable_device_mem(pdev)) {
2092 pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
2093 ioc->name);
cf9bd21a 2094 ioc->bars = 0;
f92363d1
SR		 2095 return -ENODEV;
2096 }
2097
2098
2099 if (pci_request_selected_regions(pdev, ioc->bars,
c84b06a4 2100 ioc->driver_name)) {
f92363d1
SR		 2101 pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
2102 ioc->name);
cf9bd21a 2103 ioc->bars = 0;
f92363d1
SR		 2104 r = -ENODEV;
2105 goto out_fail;
2106 }
2107
2108/* AER (Advanced Error Reporting) hooks */
2109 pci_enable_pcie_error_reporting(pdev);
2110
2111 pci_set_master(pdev);
2112
2113
2114 if (_base_config_dma_addressing(ioc, pdev) != 0) {
2115 pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
2116 ioc->name, pci_name(pdev));
2117 r = -ENODEV;
2118 goto out_fail;
2119 }
2120
5aeeb78a
SR		 2121 for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
2122 (!memap_sz || !pio_sz); i++) {
f92363d1
SR		 2123 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
2124 if (pio_sz)
2125 continue;
2126 pio_chip = (u64)pci_resource_start(pdev, i);
2127 pio_sz = pci_resource_len(pdev, i);
2128 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
2129 if (memap_sz)
2130 continue;
2131 ioc->chip_phys = pci_resource_start(pdev, i);
2132 chip_phys = (u64)ioc->chip_phys;
2133 memap_sz = pci_resource_len(pdev, i);
2134 ioc->chip = ioremap(ioc->chip_phys, memap_sz);
f92363d1
SR		 2135 }
2136 }
2137
5aeeb78a
SR		 2138 if (ioc->chip == NULL) {
2139 pr_err(MPT3SAS_FMT "unable to map adapter memory! "
2140 " or resource not found\n", ioc->name);
2141 r = -EINVAL;
2142 goto out_fail;
2143 }
2144
f92363d1 2145 _base_mask_interrupts(ioc);
9b05c91a
SR		 2146
2147 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
2148 if (r)
2149 goto out_fail;
2150
2151 if (!ioc->rdpq_array_enable_assigned) {
2152 ioc->rdpq_array_enable = ioc->rdpq_array_capable;
2153 ioc->rdpq_array_enable_assigned = 1;
2154 }
2155
f92363d1
SR		 2156 r = _base_enable_msix(ioc);
2157 if (r)
2158 goto out_fail;
2159
fb77bb53
SR		 2160 /* Use the Combined reply queue feature only for SAS3 C0 & higher
2161 * revision HBAs and also only when reply queue count is greater than 8
2162 */
2163 if (ioc->msix96_vector && ioc->reply_queue_count > 8) {
2164 /* Determine the Supplemental Reply Post Host Index Registers
2165 * Addresse. Supplemental Reply Post Host Index Registers
2166 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
2167 * each register is at offset bytes of
2168 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
2169 */
2170 ioc->replyPostRegisterIndex = kcalloc(
2171 MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT,
2172 sizeof(resource_size_t *), GFP_KERNEL);
2173 if (!ioc->replyPostRegisterIndex) {
2174 dfailprintk(ioc, printk(MPT3SAS_FMT
2175 "allocation for reply Post Register Index failed!!!\n",
2176 ioc->name));
2177 r = -ENOMEM;
2178 goto out_fail;
2179 }
2180
2181 for (i = 0; i < MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT; i++) {
2182 ioc->replyPostRegisterIndex[i] = (resource_size_t *)
2183 ((u8 *)&ioc->chip->Doorbell +
2184 MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
2185 (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
2186 }
2187 } else
2188 ioc->msix96_vector = 0;
2189
f92363d1
SR		 2190 list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
2191 pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
2192 reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
2193 "IO-APIC enabled"), reply_q->vector);
2194
2195 pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
2196 ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
2197 pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
2198 ioc->name, (unsigned long long)pio_chip, pio_sz);
2199
2200 /* Save PCI configuration state for recovery from PCI AER/EEH errors */
2201 pci_save_state(pdev);
2202 return 0;
2203
2204 out_fail:
580d4e31 2205 mpt3sas_base_unmap_resources(ioc);
f92363d1
SR		 2206 return r;
2207}
2208
2209/**
2210 * mpt3sas_base_get_msg_frame - obtain request mf pointer
2211 * @ioc: per adapter object
2212 * @smid: system request message index(smid zero is invalid)
2213 *
2214 * Returns virt pointer to message frame.
2215 */
2216void *
2217mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2218{
2219 return (void *)(ioc->request + (smid * ioc->request_sz));
2220}
2221
2222/**
2223 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
2224 * @ioc: per adapter object
2225 * @smid: system request message index
2226 *
2227 * Returns virt pointer to sense buffer.
2228 */
2229void *
2230mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2231{
2232 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
2233}
2234
2235/**
2236 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
2237 * @ioc: per adapter object
2238 * @smid: system request message index
2239 *
2240 * Returns phys pointer to the low 32bit address of the sense buffer.
2241 */
2242__le32
2243mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2244{
2245 return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
2246 SCSI_SENSE_BUFFERSIZE));
2247}
2248
2249/**
2250 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
2251 * @ioc: per adapter object
2252 * @phys_addr: lower 32 physical addr of the reply
2253 *
2254 * Converts 32bit lower physical addr into a virt address.
2255 */
2256void *
2257mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
2258{
2259 if (!phys_addr)
2260 return NULL;
2261 return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
2262}
2263
2264/**
2265 * mpt3sas_base_get_smid - obtain a free smid from internal queue
2266 * @ioc: per adapter object
2267 * @cb_idx: callback index
2268 *
2269 * Returns smid (zero is invalid)
2270 */
2271u16
2272mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2273{
2274 unsigned long flags;
2275 struct request_tracker *request;
2276 u16 smid;
2277
2278 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2279 if (list_empty(&ioc->internal_free_list)) {
2280 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2281 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2282 ioc->name, __func__);
2283 return 0;
2284 }
2285
2286 request = list_entry(ioc->internal_free_list.next,
2287 struct request_tracker, tracker_list);
2288 request->cb_idx = cb_idx;
2289 smid = request->smid;
2290 list_del(&request->tracker_list);
2291 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2292 return smid;
2293}
2294
2295/**
2296 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
2297 * @ioc: per adapter object
2298 * @cb_idx: callback index
2299 * @scmd: pointer to scsi command object
2300 *
2301 * Returns smid (zero is invalid)
2302 */
2303u16
2304mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
2305 struct scsi_cmnd *scmd)
2306{
2307 unsigned long flags;
2308 struct scsiio_tracker *request;
2309 u16 smid;
2310
2311 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2312 if (list_empty(&ioc->free_list)) {
2313 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2314 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2315 ioc->name, __func__);
2316 return 0;
2317 }
2318
2319 request = list_entry(ioc->free_list.next,
2320 struct scsiio_tracker, tracker_list);
2321 request->scmd = scmd;
2322 request->cb_idx = cb_idx;
2323 smid = request->smid;
2324 list_del(&request->tracker_list);
2325 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2326 return smid;
2327}
2328
2329/**
2330 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
2331 * @ioc: per adapter object
2332 * @cb_idx: callback index
2333 *
2334 * Returns smid (zero is invalid)
2335 */
2336u16
2337mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2338{
2339 unsigned long flags;
2340 struct request_tracker *request;
2341 u16 smid;
2342
2343 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2344 if (list_empty(&ioc->hpr_free_list)) {
2345 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2346 return 0;
2347 }
2348
2349 request = list_entry(ioc->hpr_free_list.next,
2350 struct request_tracker, tracker_list);
2351 request->cb_idx = cb_idx;
2352 smid = request->smid;
2353 list_del(&request->tracker_list);
2354 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2355 return smid;
2356}
2357
2358/**
2359 * mpt3sas_base_free_smid - put smid back on free_list
2360 * @ioc: per adapter object
2361 * @smid: system request message index
2362 *
2363 * Return nothing.
2364 */
2365void
2366mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2367{
2368 unsigned long flags;
2369 int i;
2370 struct chain_tracker *chain_req, *next;
2371
2372 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2373 if (smid < ioc->hi_priority_smid) {
2374 /* scsiio queue */
2375 i = smid - 1;
2376 if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
2377 list_for_each_entry_safe(chain_req, next,
2378 &ioc->scsi_lookup[i].chain_list, tracker_list) {
2379 list_del_init(&chain_req->tracker_list);
2380 list_add(&chain_req->tracker_list,
2381 &ioc->free_chain_list);
2382 }
2383 }
2384 ioc->scsi_lookup[i].cb_idx = 0xFF;
2385 ioc->scsi_lookup[i].scmd = NULL;
7786ab6a 2386 ioc->scsi_lookup[i].direct_io = 0;
f92363d1
SR		 2387 list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list);
2388 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2389
2390 /*
2391 * See _wait_for_commands_to_complete() call with regards
2392 * to this code.
2393 */
2394 if (ioc->shost_recovery && ioc->pending_io_count) {
2395 if (ioc->pending_io_count == 1)
2396 wake_up(&ioc->reset_wq);
2397 ioc->pending_io_count--;
2398 }
2399 return;
2400 } else if (smid < ioc->internal_smid) {
2401 /* hi-priority */
2402 i = smid - ioc->hi_priority_smid;
2403 ioc->hpr_lookup[i].cb_idx = 0xFF;
2404 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
2405 } else if (smid <= ioc->hba_queue_depth) {
2406 /* internal queue */
2407 i = smid - ioc->internal_smid;
2408 ioc->internal_lookup[i].cb_idx = 0xFF;
2409 list_add(&ioc->internal_lookup[i].tracker_list,
2410 &ioc->internal_free_list);
2411 }
2412 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2413}
2414
2415/**
2416 * _base_writeq - 64 bit write to MMIO
2417 * @ioc: per adapter object
2418 * @b: data payload
2419 * @addr: address in MMIO space
2420 * @writeq_lock: spin lock
2421 *
2422 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
2423 * care of 32 bit environment where its not quarenteed to send the entire word
2424 * in one transfer.
2425 */
2426#if defined(writeq) && defined(CONFIG_64BIT)
2427static inline void
2428_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2429{
2430 writeq(cpu_to_le64(b), addr);
2431}
2432#else
2433static inline void
2434_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2435{
2436 unsigned long flags;
2437 __u64 data_out = cpu_to_le64(b);
2438
2439 spin_lock_irqsave(writeq_lock, flags);
2440 writel((u32)(data_out), addr);
2441 writel((u32)(data_out >> 32), (addr + 4));
2442 spin_unlock_irqrestore(writeq_lock, flags);
2443}
2444#endif
2445
2446static inline u8
2447_base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
2448{
2449 return ioc->cpu_msix_table[raw_smp_processor_id()];
2450}
2451
2452/**
2453 * mpt3sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
2454 * @ioc: per adapter object
2455 * @smid: system request message index
2456 * @handle: device handle
2457 *
2458 * Return nothing.
2459 */
2460void
2461mpt3sas_base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
2462{
2463 Mpi2RequestDescriptorUnion_t descriptor;
2464 u64 *request = (u64 *)&descriptor;
2465
2466
2467 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
2468 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2469 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2470 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2471 descriptor.SCSIIO.LMID = 0;
2472 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2473 &ioc->scsi_lookup_lock);
2474}
2475
2476/**
2477 * mpt3sas_base_put_smid_fast_path - send fast path request to firmware
2478 * @ioc: per adapter object
2479 * @smid: system request message index
2480 * @handle: device handle
2481 *
2482 * Return nothing.
2483 */
2484void
2485mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2486 u16 handle)
2487{
2488 Mpi2RequestDescriptorUnion_t descriptor;
2489 u64 *request = (u64 *)&descriptor;
2490
2491 descriptor.SCSIIO.RequestFlags =
2492 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
2493 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2494 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2495 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2496 descriptor.SCSIIO.LMID = 0;
2497 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2498 &ioc->scsi_lookup_lock);
2499}
2500
2501/**
2502 * mpt3sas_base_put_smid_hi_priority - send Task Managment request to firmware
2503 * @ioc: per adapter object
2504 * @smid: system request message index
2505 *
2506 * Return nothing.
2507 */
2508void
2509mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2510{
2511 Mpi2RequestDescriptorUnion_t descriptor;
2512 u64 *request = (u64 *)&descriptor;
2513
2514 descriptor.HighPriority.RequestFlags =
2515 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
2516 descriptor.HighPriority.MSIxIndex = 0;
2517 descriptor.HighPriority.SMID = cpu_to_le16(smid);
2518 descriptor.HighPriority.LMID = 0;
2519 descriptor.HighPriority.Reserved1 = 0;
2520 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2521 &ioc->scsi_lookup_lock);
2522}
2523
2524/**
2525 * mpt3sas_base_put_smid_default - Default, primarily used for config pages
2526 * @ioc: per adapter object
2527 * @smid: system request message index
2528 *
2529 * Return nothing.
2530 */
2531void
2532mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2533{
2534 Mpi2RequestDescriptorUnion_t descriptor;
2535 u64 *request = (u64 *)&descriptor;
2536
2537 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2538 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
2539 descriptor.Default.SMID = cpu_to_le16(smid);
2540 descriptor.Default.LMID = 0;
2541 descriptor.Default.DescriptorTypeDependent = 0;
2542 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2543 &ioc->scsi_lookup_lock);
2544}
2545
1117b31a 2546/**
989e43c7 2547 * _base_display_OEMs_branding - Display branding string
1117b31a
SR		 2548 * @ioc: per adapter object
2549 *
2550 * Return nothing.
2551 */
2552static void
989e43c7 2553_base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc)
1117b31a
SR		 2554{
2555 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
2556 return;
2557
989e43c7
SR		 2558 switch (ioc->pdev->subsystem_vendor) {
2559 case PCI_VENDOR_ID_INTEL:
2560 switch (ioc->pdev->device) {
2561 case MPI2_MFGPAGE_DEVID_SAS2008:
2562 switch (ioc->pdev->subsystem_device) {
2563 case MPT2SAS_INTEL_RMS2LL080_SSDID:
2564 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2565 MPT2SAS_INTEL_RMS2LL080_BRANDING);
2566 break;
2567 case MPT2SAS_INTEL_RMS2LL040_SSDID:
2568 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2569 MPT2SAS_INTEL_RMS2LL040_BRANDING);
2570 break;
2571 case MPT2SAS_INTEL_SSD910_SSDID:
2572 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2573 MPT2SAS_INTEL_SSD910_BRANDING);
2574 break;
2575 default:
2576 pr_info(MPT3SAS_FMT
2577 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2578 ioc->name, ioc->pdev->subsystem_device);
2579 break;
2580 }
2581 case MPI2_MFGPAGE_DEVID_SAS2308_2:
2582 switch (ioc->pdev->subsystem_device) {
2583 case MPT2SAS_INTEL_RS25GB008_SSDID:
2584 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2585 MPT2SAS_INTEL_RS25GB008_BRANDING);
2586 break;
2587 case MPT2SAS_INTEL_RMS25JB080_SSDID:
2588 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2589 MPT2SAS_INTEL_RMS25JB080_BRANDING);
2590 break;
2591 case MPT2SAS_INTEL_RMS25JB040_SSDID:
2592 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2593 MPT2SAS_INTEL_RMS25JB040_BRANDING);
2594 break;
2595 case MPT2SAS_INTEL_RMS25KB080_SSDID:
2596 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2597 MPT2SAS_INTEL_RMS25KB080_BRANDING);
2598 break;
2599 case MPT2SAS_INTEL_RMS25KB040_SSDID:
2600 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2601 MPT2SAS_INTEL_RMS25KB040_BRANDING);
2602 break;
2603 case MPT2SAS_INTEL_RMS25LB040_SSDID:
2604 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2605 MPT2SAS_INTEL_RMS25LB040_BRANDING);
2606 break;
2607 case MPT2SAS_INTEL_RMS25LB080_SSDID:
2608 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2609 MPT2SAS_INTEL_RMS25LB080_BRANDING);
2610 break;
2611 default:
2612 pr_info(MPT3SAS_FMT
2613 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2614 ioc->name, ioc->pdev->subsystem_device);
2615 break;
2616 }
2617 case MPI25_MFGPAGE_DEVID_SAS3008:
2618 switch (ioc->pdev->subsystem_device) {
2619 case MPT3SAS_INTEL_RMS3JC080_SSDID:
2620 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2621 MPT3SAS_INTEL_RMS3JC080_BRANDING);
2622 break;
2623
2624 case MPT3SAS_INTEL_RS3GC008_SSDID:
2625 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2626 MPT3SAS_INTEL_RS3GC008_BRANDING);
2627 break;
2628 case MPT3SAS_INTEL_RS3FC044_SSDID:
2629 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2630 MPT3SAS_INTEL_RS3FC044_BRANDING);
2631 break;
2632 case MPT3SAS_INTEL_RS3UC080_SSDID:
2633 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2634 MPT3SAS_INTEL_RS3UC080_BRANDING);
2635 break;
2636 default:
2637 pr_info(MPT3SAS_FMT
2638 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2639 ioc->name, ioc->pdev->subsystem_device);
2640 break;
2641 }
1117b31a
SR		 2642 break;
2643 default:
2644 pr_info(MPT3SAS_FMT
989e43c7
SR		 2645 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2646 ioc->name, ioc->pdev->subsystem_device);
1117b31a
SR		 2647 break;
2648 }
2649 break;
989e43c7
SR		 2650 case PCI_VENDOR_ID_DELL:
2651 switch (ioc->pdev->device) {
2652 case MPI2_MFGPAGE_DEVID_SAS2008:
2653 switch (ioc->pdev->subsystem_device) {
2654 case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
2655 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2656 MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
2657 break;
2658 case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
2659 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2660 MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
2661 break;
2662 case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
2663 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2664 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
2665 break;
2666 case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
2667 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2668 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
2669 break;
2670 case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
2671 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2672 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
2673 break;
2674 case MPT2SAS_DELL_PERC_H200_SSDID:
2675 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2676 MPT2SAS_DELL_PERC_H200_BRANDING);
2677 break;
2678 case MPT2SAS_DELL_6GBPS_SAS_SSDID:
2679 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2680 MPT2SAS_DELL_6GBPS_SAS_BRANDING);
2681 break;
2682 default:
2683 pr_info(MPT3SAS_FMT
2684 "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
2685 ioc->name, ioc->pdev->subsystem_device);
2686 break;
2687 }
2688 break;
2689 case MPI25_MFGPAGE_DEVID_SAS3008:
2690 switch (ioc->pdev->subsystem_device) {
2691 case MPT3SAS_DELL_12G_HBA_SSDID:
2692 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2693 MPT3SAS_DELL_12G_HBA_BRANDING);
2694 break;
2695 default:
2696 pr_info(MPT3SAS_FMT
2697 "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
2698 ioc->name, ioc->pdev->subsystem_device);
2699 break;
2700 }
fb84dfc4
SR		 2701 break;
2702 default:
2703 pr_info(MPT3SAS_FMT
989e43c7 2704 "Dell HBA: Subsystem ID: 0x%X\n", ioc->name,
fb84dfc4
SR		 2705 ioc->pdev->subsystem_device);
2706 break;
2707 }
2708 break;
989e43c7
SR		 2709 case PCI_VENDOR_ID_CISCO:
2710 switch (ioc->pdev->device) {
2711 case MPI25_MFGPAGE_DEVID_SAS3008:
2712 switch (ioc->pdev->subsystem_device) {
2713 case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
2714 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2715 MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
2716 break;
2717 case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
2718 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2719 MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
2720 break;
2721 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2722 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2723 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
2724 break;
2725 default:
2726 pr_info(MPT3SAS_FMT
2727 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2728 ioc->name, ioc->pdev->subsystem_device);
2729 break;
2730 }
d8eb4a47 2731 break;
989e43c7
SR		 2732 case MPI25_MFGPAGE_DEVID_SAS3108_1:
2733 switch (ioc->pdev->subsystem_device) {
2734 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
2735 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
d8eb4a47 2736 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
989e43c7
SR		 2737 break;
2738 case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
2739 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2740 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING
2741 );
2742 break;
2743 default:
2744 pr_info(MPT3SAS_FMT
2745 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
2746 ioc->name, ioc->pdev->subsystem_device);
2747 break;
2748 }
38e4141e
SR		 2749 break;
2750 default:
2751 pr_info(MPT3SAS_FMT
989e43c7
SR		 2752 "Cisco SAS HBA: Subsystem ID: 0x%X\n",
2753 ioc->name, ioc->pdev->subsystem_device);
38e4141e
SR		 2754 break;
2755 }
2756 break;
989e43c7
SR		 2757 case MPT2SAS_HP_3PAR_SSVID:
2758 switch (ioc->pdev->device) {
2759 case MPI2_MFGPAGE_DEVID_SAS2004:
2760 switch (ioc->pdev->subsystem_device) {
2761 case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
2762 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2763 MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
2764 break;
2765 default:
2766 pr_info(MPT3SAS_FMT
2767 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
2768 ioc->name, ioc->pdev->subsystem_device);
2769 break;
2770 }
2771 case MPI2_MFGPAGE_DEVID_SAS2308_2:
2772 switch (ioc->pdev->subsystem_device) {
2773 case MPT2SAS_HP_2_4_INTERNAL_SSDID:
2774 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2775 MPT2SAS_HP_2_4_INTERNAL_BRANDING);
2776 break;
2777 case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
2778 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2779 MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
2780 break;
2781 case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
2782 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2783 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
2784 break;
2785 case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
2786 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2787 MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
2788 break;
2789 default:
2790 pr_info(MPT3SAS_FMT
2791 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
2792 ioc->name, ioc->pdev->subsystem_device);
2793 break;
2794 }
d8eb4a47
SR		 2795 default:
2796 pr_info(MPT3SAS_FMT
989e43c7
SR		 2797 "HP SAS HBA: Subsystem ID: 0x%X\n",
2798 ioc->name, ioc->pdev->subsystem_device);
d8eb4a47
SR		 2799 break;
2800 }
38e4141e 2801 default:
38e4141e
SR		 2802 break;
2803 }
2804}
fb84dfc4 2805
f92363d1
SR		 2806/**
2807 * _base_display_ioc_capabilities - Disply IOC's capabilities.
2808 * @ioc: per adapter object
2809 *
2810 * Return nothing.
2811 */
2812static void
2813_base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
2814{
2815 int i = 0;
2816 char desc[16];
2817 u32 iounit_pg1_flags;
2818 u32 bios_version;
2819
2820 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
2821 strncpy(desc, ioc->manu_pg0.ChipName, 16);
2822 pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
2823 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
2824 ioc->name, desc,
2825 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
2826 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
2827 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
2828 ioc->facts.FWVersion.Word & 0x000000FF,
2829 ioc->pdev->revision,
2830 (bios_version & 0xFF000000) >> 24,
2831 (bios_version & 0x00FF0000) >> 16,
2832 (bios_version & 0x0000FF00) >> 8,
2833 bios_version & 0x000000FF);
2834
989e43c7 2835 _base_display_OEMs_branding(ioc);
1117b31a 2836
f92363d1
SR		 2837 pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
2838
2839 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
2840 pr_info("Initiator");
2841 i++;
2842 }
2843
2844 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
2845 pr_info("%sTarget", i ? "," : "");
2846 i++;
2847 }
2848
2849 i = 0;
2850 pr_info("), ");
2851 pr_info("Capabilities=(");
2852
7786ab6a
SR		 2853 if (!ioc->hide_ir_msg) {
2854 if (ioc->facts.IOCCapabilities &
f92363d1
SR		 2855 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
2856 pr_info("Raid");
2857 i++;
7786ab6a 2858 }
f92363d1
SR		 2859 }
2860
2861 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
2862 pr_info("%sTLR", i ? "," : "");
2863 i++;
2864 }
2865
2866 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
2867 pr_info("%sMulticast", i ? "," : "");
2868 i++;
2869 }
2870
2871 if (ioc->facts.IOCCapabilities &
2872 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
2873 pr_info("%sBIDI Target", i ? "," : "");
2874 i++;
2875 }
2876
2877 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
2878 pr_info("%sEEDP", i ? "," : "");
2879 i++;
2880 }
2881
2882 if (ioc->facts.IOCCapabilities &
2883 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
2884 pr_info("%sSnapshot Buffer", i ? "," : "");
2885 i++;
2886 }
2887
2888 if (ioc->facts.IOCCapabilities &
2889 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
2890 pr_info("%sDiag Trace Buffer", i ? "," : "");
2891 i++;
2892 }
2893
2894 if (ioc->facts.IOCCapabilities &
2895 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
2896 pr_info("%sDiag Extended Buffer", i ? "," : "");
2897 i++;
2898 }
2899
2900 if (ioc->facts.IOCCapabilities &
2901 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
2902 pr_info("%sTask Set Full", i ? "," : "");
2903 i++;
2904 }
2905
2906 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2907 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
2908 pr_info("%sNCQ", i ? "," : "");
2909 i++;
2910 }
2911
2912 pr_info(")\n");
2913}
2914
2915/**
2916 * mpt3sas_base_update_missing_delay - change the missing delay timers
2917 * @ioc: per adapter object
2918 * @device_missing_delay: amount of time till device is reported missing
2919 * @io_missing_delay: interval IO is returned when there is a missing device
2920 *
2921 * Return nothing.
2922 *
2923 * Passed on the command line, this function will modify the device missing
2924 * delay, as well as the io missing delay. This should be called at driver
2925 * load time.
2926 */
2927void
2928mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
2929 u16 device_missing_delay, u8 io_missing_delay)
2930{
2931 u16 dmd, dmd_new, dmd_orignal;
2932 u8 io_missing_delay_original;
2933 u16 sz;
2934 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
2935 Mpi2ConfigReply_t mpi_reply;
2936 u8 num_phys = 0;
2937 u16 ioc_status;
2938
2939 mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
2940 if (!num_phys)
2941 return;
2942
2943 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
2944 sizeof(Mpi2SasIOUnit1PhyData_t));
2945 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
2946 if (!sas_iounit_pg1) {
2947 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2948 ioc->name, __FILE__, __LINE__, __func__);
2949 goto out;
2950 }
2951 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
2952 sas_iounit_pg1, sz))) {
2953 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2954 ioc->name, __FILE__, __LINE__, __func__);
2955 goto out;
2956 }
2957 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
2958 MPI2_IOCSTATUS_MASK;
2959 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
2960 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2961 ioc->name, __FILE__, __LINE__, __func__);
2962 goto out;
2963 }
2964
2965 /* device missing delay */
2966 dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
2967 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2968 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2969 else
2970 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2971 dmd_orignal = dmd;
2972 if (device_missing_delay > 0x7F) {
2973 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
2974 device_missing_delay;
2975 dmd = dmd / 16;
2976 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
2977 } else
2978 dmd = device_missing_delay;
2979 sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
2980
2981 /* io missing delay */
2982 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
2983 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
2984
2985 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
2986 sz)) {
2987 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2988 dmd_new = (dmd &
2989 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2990 else
2991 dmd_new =
2992 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2993 pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
2994 ioc->name, dmd_orignal, dmd_new);
2995 pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
2996 ioc->name, io_missing_delay_original,
2997 io_missing_delay);
2998 ioc->device_missing_delay = dmd_new;
2999 ioc->io_missing_delay = io_missing_delay;
3000 }
3001
3002out:
3003 kfree(sas_iounit_pg1);
3004}
3005/**
3006 * _base_static_config_pages - static start of day config pages
3007 * @ioc: per adapter object
3008 *
3009 * Return nothing.
3010 */
3011static void
3012_base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
3013{
3014 Mpi2ConfigReply_t mpi_reply;
3015 u32 iounit_pg1_flags;
3016
3017 mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
3018 if (ioc->ir_firmware)
3019 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
3020 &ioc->manu_pg10);
3021
3022 /*
3023 * Ensure correct T10 PI operation if vendor left EEDPTagMode
3024 * flag unset in NVDATA.
3025 */
3026 mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
3027 if (ioc->manu_pg11.EEDPTagMode == 0) {
3028 pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
3029 ioc->name);
3030 ioc->manu_pg11.EEDPTagMode &= ~0x3;
3031 ioc->manu_pg11.EEDPTagMode |= 0x1;
3032 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
3033 &ioc->manu_pg11);
3034 }
3035
3036 mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
3037 mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
3038 mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
3039 mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
3040 mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2d8ce8c9 3041 mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
f92363d1
SR		 3042 _base_display_ioc_capabilities(ioc);
3043
3044 /*
3045 * Enable task_set_full handling in iounit_pg1 when the
3046 * facts capabilities indicate that its supported.
3047 */
3048 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
3049 if ((ioc->facts.IOCCapabilities &
3050 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
3051 iounit_pg1_flags &=
3052 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3053 else
3054 iounit_pg1_flags |=
3055 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
3056 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
3057 mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2d8ce8c9
SR		 3058
3059 if (ioc->iounit_pg8.NumSensors)
3060 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
f92363d1
SR		 3061}
3062
3063/**
3064 * _base_release_memory_pools - release memory
3065 * @ioc: per adapter object
3066 *
3067 * Free memory allocated from _base_allocate_memory_pools.
3068 *
3069 * Return nothing.
3070 */
3071static void
3072_base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
3073{
9b05c91a
SR		 3074 int i = 0;
3075 struct reply_post_struct *rps;
f92363d1
SR		 3076
3077 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3078 __func__));
3079
3080 if (ioc->request) {
3081 pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
3082 ioc->request, ioc->request_dma);
3083 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3084 "request_pool(0x%p): free\n",
3085 ioc->name, ioc->request));
3086 ioc->request = NULL;
3087 }
3088
3089 if (ioc->sense) {
3090 pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
3091 if (ioc->sense_dma_pool)
3092 pci_pool_destroy(ioc->sense_dma_pool);
3093 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3094 "sense_pool(0x%p): free\n",
3095 ioc->name, ioc->sense));
3096 ioc->sense = NULL;
3097 }
3098
3099 if (ioc->reply) {
3100 pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
3101 if (ioc->reply_dma_pool)
3102 pci_pool_destroy(ioc->reply_dma_pool);
3103 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3104 "reply_pool(0x%p): free\n",
3105 ioc->name, ioc->reply));
3106 ioc->reply = NULL;
3107 }
3108
3109 if (ioc->reply_free) {
3110 pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
3111 ioc->reply_free_dma);
3112 if (ioc->reply_free_dma_pool)
3113 pci_pool_destroy(ioc->reply_free_dma_pool);
3114 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3115 "reply_free_pool(0x%p): free\n",
3116 ioc->name, ioc->reply_free));
3117 ioc->reply_free = NULL;
3118 }
3119
9b05c91a
SR		 3120 if (ioc->reply_post) {
3121 do {
3122 rps = &ioc->reply_post[i];
3123 if (rps->reply_post_free) {
3124 pci_pool_free(
3125 ioc->reply_post_free_dma_pool,
3126 rps->reply_post_free,
3127 rps->reply_post_free_dma);
3128 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3129 "reply_post_free_pool(0x%p): free\n",
3130 ioc->name, rps->reply_post_free));
3131 rps->reply_post_free = NULL;
3132 }
3133 } while (ioc->rdpq_array_enable &&
3134 (++i < ioc->reply_queue_count));
3135
f92363d1
SR		 3136 if (ioc->reply_post_free_dma_pool)
3137 pci_pool_destroy(ioc->reply_post_free_dma_pool);
9b05c91a 3138 kfree(ioc->reply_post);
f92363d1
SR		 3139 }
3140
3141 if (ioc->config_page) {
3142 dexitprintk(ioc, pr_info(MPT3SAS_FMT
3143 "config_page(0x%p): free\n", ioc->name,
3144 ioc->config_page));
3145 pci_free_consistent(ioc->pdev, ioc->config_page_sz,
3146 ioc->config_page, ioc->config_page_dma);
3147 }
3148
3149 if (ioc->scsi_lookup) {
3150 free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
3151 ioc->scsi_lookup = NULL;
3152 }
3153 kfree(ioc->hpr_lookup);
3154 kfree(ioc->internal_lookup);
3155 if (ioc->chain_lookup) {
3156 for (i = 0; i < ioc->chain_depth; i++) {
3157 if (ioc->chain_lookup[i].chain_buffer)
3158 pci_pool_free(ioc->chain_dma_pool,
3159 ioc->chain_lookup[i].chain_buffer,
3160 ioc->chain_lookup[i].chain_buffer_dma);
3161 }
3162 if (ioc->chain_dma_pool)
3163 pci_pool_destroy(ioc->chain_dma_pool);
3164 free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
3165 ioc->chain_lookup = NULL;
3166 }
3167}
3168
3169/**
3170 * _base_allocate_memory_pools - allocate start of day memory pools
3171 * @ioc: per adapter object
3172 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3173 *
3174 * Returns 0 success, anything else error
3175 */
3176static int
3177_base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
3178{
3179 struct mpt3sas_facts *facts;
3180 u16 max_sge_elements;
3181 u16 chains_needed_per_io;
3182 u32 sz, total_sz, reply_post_free_sz;
3183 u32 retry_sz;
3184 u16 max_request_credit;
3185 unsigned short sg_tablesize;
3186 u16 sge_size;
3187 int i;
3188
3189 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3190 __func__));
3191
3192
3193 retry_sz = 0;
3194 facts = &ioc->facts;
3195
3196 /* command line tunables for max sgl entries */
3197 if (max_sgl_entries != -1)
3198 sg_tablesize = max_sgl_entries;
471ef9d4
SR		 3199 else {
3200 if (ioc->hba_mpi_version_belonged == MPI2_VERSION)
3201 sg_tablesize = MPT2SAS_SG_DEPTH;
3202 else
3203 sg_tablesize = MPT3SAS_SG_DEPTH;
3204 }
f92363d1 3205
8a7e4c24
SR		 3206 if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS)
3207 sg_tablesize = MPT_MIN_PHYS_SEGMENTS;
3208 else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
ad666a0f
SR		 3209 sg_tablesize = min_t(unsigned short, sg_tablesize,
3210 SCSI_MAX_SG_CHAIN_SEGMENTS);
3211 pr_warn(MPT3SAS_FMT
3212 "sg_tablesize(%u) is bigger than kernel"
3213 " defined SCSI_MAX_SG_SEGMENTS(%u)\n", ioc->name,
8a7e4c24 3214 sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
ad666a0f 3215 }
f92363d1
SR		 3216 ioc->shost->sg_tablesize = sg_tablesize;
3217
fd0331b3
SS		 3218 ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)),
3219 (facts->RequestCredit / 4));
3220 if (ioc->internal_depth < INTERNAL_CMDS_COUNT) {
3221 if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT +
3222 INTERNAL_SCSIIO_CMDS_COUNT)) {
3223 pr_err(MPT3SAS_FMT "IOC doesn't have enough Request \
3224 Credits, it has just %d number of credits\n",
3225 ioc->name, facts->RequestCredit);
3226 return -ENOMEM;
3227 }
3228 ioc->internal_depth = 10;
3229 }
3230
3231 ioc->hi_priority_depth = ioc->internal_depth - (5);
f92363d1
SR		 3232 /* command line tunables for max controller queue depth */
3233 if (max_queue_depth != -1 && max_queue_depth != 0) {
3234 max_request_credit = min_t(u16, max_queue_depth +
fd0331b3 3235 ioc->internal_depth, facts->RequestCredit);
f92363d1
SR		 3236 if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
3237 max_request_credit = MAX_HBA_QUEUE_DEPTH;
3238 } else
3239 max_request_credit = min_t(u16, facts->RequestCredit,
3240 MAX_HBA_QUEUE_DEPTH);
3241
fd0331b3
SS		 3242 /* Firmware maintains additional facts->HighPriorityCredit number of
3243 * credits for HiPriprity Request messages, so hba queue depth will be
3244 * sum of max_request_credit and high priority queue depth.
3245 */
3246 ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth;
f92363d1
SR		 3247
3248 /* request frame size */
3249 ioc->request_sz = facts->IOCRequestFrameSize * 4;
3250
3251 /* reply frame size */
3252 ioc->reply_sz = facts->ReplyFrameSize * 4;
3253
ebb3024e
SS		 3254 /* chain segment size */
3255 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
3256 if (facts->IOCMaxChainSegmentSize)
3257 ioc->chain_segment_sz =
3258 facts->IOCMaxChainSegmentSize *
3259 MAX_CHAIN_ELEMT_SZ;
3260 else
3261 /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */
3262 ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS *
3263 MAX_CHAIN_ELEMT_SZ;
3264 } else
3265 ioc->chain_segment_sz = ioc->request_sz;
3266
f92363d1
SR		 3267 /* calculate the max scatter element size */
3268 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
3269
3270 retry_allocation:
3271 total_sz = 0;
3272 /* calculate number of sg elements left over in the 1st frame */
3273 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
3274 sizeof(Mpi2SGEIOUnion_t)) + sge_size);
3275 ioc->max_sges_in_main_message = max_sge_elements/sge_size;
3276
3277 /* now do the same for a chain buffer */
ebb3024e 3278 max_sge_elements = ioc->chain_segment_sz - sge_size;
f92363d1
SR		 3279 ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
3280
3281 /*
3282 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
3283 */
3284 chains_needed_per_io = ((ioc->shost->sg_tablesize -
3285 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
3286 + 1;
3287 if (chains_needed_per_io > facts->MaxChainDepth) {
3288 chains_needed_per_io = facts->MaxChainDepth;
3289 ioc->shost->sg_tablesize = min_t(u16,
3290 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
3291 * chains_needed_per_io), ioc->shost->sg_tablesize);
3292 }
3293 ioc->chains_needed_per_io = chains_needed_per_io;
3294
3295 /* reply free queue sizing - taking into account for 64 FW events */
3296 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3297
3298 /* calculate reply descriptor post queue depth */
3299 ioc->reply_post_queue_depth = ioc->hba_queue_depth +
3300 ioc->reply_free_queue_depth + 1 ;
3301 /* align the reply post queue on the next 16 count boundary */
3302 if (ioc->reply_post_queue_depth % 16)
3303 ioc->reply_post_queue_depth += 16 -
3304 (ioc->reply_post_queue_depth % 16);
3305
f92363d1
SR		 3306 if (ioc->reply_post_queue_depth >
3307 facts->MaxReplyDescriptorPostQueueDepth) {
3308 ioc->reply_post_queue_depth =
3309 facts->MaxReplyDescriptorPostQueueDepth -
3310 (facts->MaxReplyDescriptorPostQueueDepth % 16);
3311 ioc->hba_queue_depth =
3312 ((ioc->reply_post_queue_depth - 64) / 2) - 1;
3313 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
3314 }
3315
3316 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
3317 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
3318 "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
3319 ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
3320 ioc->chains_needed_per_io));
3321
9b05c91a
SR		 3322 /* reply post queue, 16 byte align */
3323 reply_post_free_sz = ioc->reply_post_queue_depth *
3324 sizeof(Mpi2DefaultReplyDescriptor_t);
3325
3326 sz = reply_post_free_sz;
3327 if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
3328 sz *= ioc->reply_queue_count;
3329
3330 ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
3331 (ioc->reply_queue_count):1,
3332 sizeof(struct reply_post_struct), GFP_KERNEL);
3333
3334 if (!ioc->reply_post) {
3335 pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n",
3336 ioc->name);
3337 goto out;
3338 }
3339 ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
3340 ioc->pdev, sz, 16, 0);
3341 if (!ioc->reply_post_free_dma_pool) {
3342 pr_err(MPT3SAS_FMT
3343 "reply_post_free pool: pci_pool_create failed\n",
3344 ioc->name);
3345 goto out;
3346 }
3347 i = 0;
3348 do {
3349 ioc->reply_post[i].reply_post_free =
3350 pci_pool_alloc(ioc->reply_post_free_dma_pool,
3351 GFP_KERNEL,
3352 &ioc->reply_post[i].reply_post_free_dma);
3353 if (!ioc->reply_post[i].reply_post_free) {
3354 pr_err(MPT3SAS_FMT
3355 "reply_post_free pool: pci_pool_alloc failed\n",
3356 ioc->name);
3357 goto out;
3358 }
3359 memset(ioc->reply_post[i].reply_post_free, 0, sz);
3360 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3361 "reply post free pool (0x%p): depth(%d),"
3362 "element_size(%d), pool_size(%d kB)\n", ioc->name,
3363 ioc->reply_post[i].reply_post_free,
3364 ioc->reply_post_queue_depth, 8, sz/1024));
3365 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3366 "reply_post_free_dma = (0x%llx)\n", ioc->name,
3367 (unsigned long long)
3368 ioc->reply_post[i].reply_post_free_dma));
3369 total_sz += sz;
3370 } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
3371
3372 if (ioc->dma_mask == 64) {
3373 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
3374 pr_warn(MPT3SAS_FMT
3375 "no suitable consistent DMA mask for %s\n",
3376 ioc->name, pci_name(ioc->pdev));
3377 goto out;
3378 }
3379 }
3380
f92363d1
SR		 3381 ioc->scsiio_depth = ioc->hba_queue_depth -
3382 ioc->hi_priority_depth - ioc->internal_depth;
3383
3384 /* set the scsi host can_queue depth
3385 * with some internal commands that could be outstanding
3386 */
fd0331b3 3387 ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT;
f92363d1
SR		 3388 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3389 "scsi host: can_queue depth (%d)\n",
3390 ioc->name, ioc->shost->can_queue));
3391
3392
3393 /* contiguous pool for request and chains, 16 byte align, one extra "
3394 * "frame for smid=0
3395 */
3396 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
3397 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
3398
3399 /* hi-priority queue */
3400 sz += (ioc->hi_priority_depth * ioc->request_sz);
3401
3402 /* internal queue */
3403 sz += (ioc->internal_depth * ioc->request_sz);
3404
3405 ioc->request_dma_sz = sz;
3406 ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
3407 if (!ioc->request) {
3408 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3409 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3410 "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
3411 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3412 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
3413 goto out;
fd0331b3
SS		 3414 retry_sz = 64;
3415 ioc->hba_queue_depth -= retry_sz;
f92363d1
SR		 3416 goto retry_allocation;
3417 }
3418
3419 if (retry_sz)
3420 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
3421 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
3422 "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
3423 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
3424
3425 /* hi-priority queue */
3426 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
3427 ioc->request_sz);
3428 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
3429 ioc->request_sz);
3430
3431 /* internal queue */
3432 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
3433 ioc->request_sz);
3434 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
3435 ioc->request_sz);
3436
3437 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3438 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3439 ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
3440 (ioc->hba_queue_depth * ioc->request_sz)/1024));
3441
3442 dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
3443 ioc->name, (unsigned long long) ioc->request_dma));
3444 total_sz += sz;
3445
3446 sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
3447 ioc->scsi_lookup_pages = get_order(sz);
3448 ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
3449 GFP_KERNEL, ioc->scsi_lookup_pages);
3450 if (!ioc->scsi_lookup) {
3451 pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n",
3452 ioc->name, (int)sz);
3453 goto out;
3454 }
3455
3456 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
3457 ioc->name, ioc->request, ioc->scsiio_depth));
3458
3459 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
3460 sz = ioc->chain_depth * sizeof(struct chain_tracker);
3461 ioc->chain_pages = get_order(sz);
3462 ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
3463 GFP_KERNEL, ioc->chain_pages);
3464 if (!ioc->chain_lookup) {
3465 pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n",
3466 ioc->name);
3467 goto out;
3468 }
3469 ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev,
ebb3024e 3470 ioc->chain_segment_sz, 16, 0);
f92363d1
SR		 3471 if (!ioc->chain_dma_pool) {
3472 pr_err(MPT3SAS_FMT "chain_dma_pool: pci_pool_create failed\n",
3473 ioc->name);
3474 goto out;
3475 }
3476 for (i = 0; i < ioc->chain_depth; i++) {
3477 ioc->chain_lookup[i].chain_buffer = pci_pool_alloc(
3478 ioc->chain_dma_pool , GFP_KERNEL,
3479 &ioc->chain_lookup[i].chain_buffer_dma);
3480 if (!ioc->chain_lookup[i].chain_buffer) {
3481 ioc->chain_depth = i;
3482 goto chain_done;
3483 }
ebb3024e 3484 total_sz += ioc->chain_segment_sz;
f92363d1
SR		 3485 }
3486 chain_done:
3487 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3488 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
ebb3024e
SS		 3489 ioc->name, ioc->chain_depth, ioc->chain_segment_sz,
3490 ((ioc->chain_depth * ioc->chain_segment_sz))/1024));
f92363d1
SR		 3491
3492 /* initialize hi-priority queue smid's */
3493 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
3494 sizeof(struct request_tracker), GFP_KERNEL);
3495 if (!ioc->hpr_lookup) {
3496 pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
3497 ioc->name);
3498 goto out;
3499 }
3500 ioc->hi_priority_smid = ioc->scsiio_depth + 1;
3501 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3502 "hi_priority(0x%p): depth(%d), start smid(%d)\n",
3503 ioc->name, ioc->hi_priority,
3504 ioc->hi_priority_depth, ioc->hi_priority_smid));
3505
3506 /* initialize internal queue smid's */
3507 ioc->internal_lookup = kcalloc(ioc->internal_depth,
3508 sizeof(struct request_tracker), GFP_KERNEL);
3509 if (!ioc->internal_lookup) {
3510 pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
3511 ioc->name);
3512 goto out;
3513 }
3514 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
3515 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3516 "internal(0x%p): depth(%d), start smid(%d)\n",
3517 ioc->name, ioc->internal,
3518 ioc->internal_depth, ioc->internal_smid));
3519
3520 /* sense buffers, 4 byte align */
3521 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
3522 ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
3523 0);
3524 if (!ioc->sense_dma_pool) {
3525 pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n",
3526 ioc->name);
3527 goto out;
3528 }
3529 ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
3530 &ioc->sense_dma);
3531 if (!ioc->sense) {
3532 pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n",
3533 ioc->name);
3534 goto out;
3535 }
3536 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3537 "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
3538 "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
3539 SCSI_SENSE_BUFFERSIZE, sz/1024));
3540 dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
3541 ioc->name, (unsigned long long)ioc->sense_dma));
3542 total_sz += sz;
3543
3544 /* reply pool, 4 byte align */
3545 sz = ioc->reply_free_queue_depth * ioc->reply_sz;
3546 ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
3547 0);
3548 if (!ioc->reply_dma_pool) {
3549 pr_err(MPT3SAS_FMT "reply pool: pci_pool_create failed\n",
3550 ioc->name);
3551 goto out;
3552 }
3553 ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
3554 &ioc->reply_dma);
3555 if (!ioc->reply) {
3556 pr_err(MPT3SAS_FMT "reply pool: pci_pool_alloc failed\n",
3557 ioc->name);
3558 goto out;
3559 }
3560 ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
3561 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
3562 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3563 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3564 ioc->name, ioc->reply,
3565 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
3566 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
3567 ioc->name, (unsigned long long)ioc->reply_dma));
3568 total_sz += sz;
3569
3570 /* reply free queue, 16 byte align */
3571 sz = ioc->reply_free_queue_depth * 4;
3572 ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
3573 ioc->pdev, sz, 16, 0);
3574 if (!ioc->reply_free_dma_pool) {
3575 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_create failed\n",
3576 ioc->name);
3577 goto out;
3578 }
3579 ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
3580 &ioc->reply_free_dma);
3581 if (!ioc->reply_free) {
3582 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_alloc failed\n",
3583 ioc->name);
3584 goto out;
3585 }
3586 memset(ioc->reply_free, 0, sz);
3587 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
3588 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
3589 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
3590 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3591 "reply_free_dma (0x%llx)\n",
3592 ioc->name, (unsigned long long)ioc->reply_free_dma));
3593 total_sz += sz;
3594
f92363d1
SR		 3595 ioc->config_page_sz = 512;
3596 ioc->config_page = pci_alloc_consistent(ioc->pdev,
3597 ioc->config_page_sz, &ioc->config_page_dma);
3598 if (!ioc->config_page) {
3599 pr_err(MPT3SAS_FMT
3600 "config page: pci_pool_alloc failed\n",
3601 ioc->name);
3602 goto out;
3603 }
3604 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3605 "config page(0x%p): size(%d)\n",
3606 ioc->name, ioc->config_page, ioc->config_page_sz));
3607 dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
3608 ioc->name, (unsigned long long)ioc->config_page_dma));
3609 total_sz += ioc->config_page_sz;
3610
3611 pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
3612 ioc->name, total_sz/1024);
3613 pr_info(MPT3SAS_FMT
3614 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
3615 ioc->name, ioc->shost->can_queue, facts->RequestCredit);
3616 pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
3617 ioc->name, ioc->shost->sg_tablesize);
3618 return 0;
3619
3620 out:
3621 return -ENOMEM;
3622}
3623
3624/**
3625 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
3626 * @ioc: Pointer to MPT_ADAPTER structure
3627 * @cooked: Request raw or cooked IOC state
3628 *
3629 * Returns all IOC Doorbell register bits if cooked==0, else just the
3630 * Doorbell bits in MPI_IOC_STATE_MASK.
3631 */
3632u32
3633mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
3634{
3635 u32 s, sc;
3636
3637 s = readl(&ioc->chip->Doorbell);
3638 sc = s & MPI2_IOC_STATE_MASK;
3639 return cooked ? sc : s;
3640}
3641
3642/**
3643 * _base_wait_on_iocstate - waiting on a particular ioc state
3644 * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
3645 * @timeout: timeout in second
3646 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3647 *
3648 * Returns 0 for success, non-zero for failure.
3649 */
3650static int
3651_base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout,
3652 int sleep_flag)
3653{
3654 u32 count, cntdn;
3655 u32 current_state;
3656
3657 count = 0;
3658 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3659 do {
3660 current_state = mpt3sas_base_get_iocstate(ioc, 1);
3661 if (current_state == ioc_state)
3662 return 0;
3663 if (count && current_state == MPI2_IOC_STATE_FAULT)
3664 break;
3665 if (sleep_flag == CAN_SLEEP)
3666 usleep_range(1000, 1500);
3667 else
3668 udelay(500);
3669 count++;
3670 } while (--cntdn);
3671
3672 return current_state;
3673}
3674
3675/**
3676 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
3677 * a write to the doorbell)
3678 * @ioc: per adapter object
3679 * @timeout: timeout in second
3680 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3681 *
3682 * Returns 0 for success, non-zero for failure.
3683 *
3684 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
3685 */
4dc8c808
SR		 3686static int
3687_base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag);
3688
f92363d1
SR		 3689static int
3690_base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout,
3691 int sleep_flag)
3692{
3693 u32 cntdn, count;
3694 u32 int_status;
3695
3696 count = 0;
3697 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3698 do {
3699 int_status = readl(&ioc->chip->HostInterruptStatus);
3700 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3701 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3702 "%s: successful count(%d), timeout(%d)\n",
3703 ioc->name, __func__, count, timeout));
3704 return 0;
3705 }
3706 if (sleep_flag == CAN_SLEEP)
3707 usleep_range(1000, 1500);
3708 else
3709 udelay(500);
3710 count++;
3711 } while (--cntdn);
3712
3713 pr_err(MPT3SAS_FMT
3714 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3715 ioc->name, __func__, count, int_status);
3716 return -EFAULT;
3717}
3718
3719/**
3720 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
3721 * @ioc: per adapter object
3722 * @timeout: timeout in second
3723 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3724 *
3725 * Returns 0 for success, non-zero for failure.
3726 *
3727 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
3728 * doorbell.
3729 */
3730static int
3731_base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout,
3732 int sleep_flag)
3733{
3734 u32 cntdn, count;
3735 u32 int_status;
3736 u32 doorbell;
3737
3738 count = 0;
3739 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3740 do {
3741 int_status = readl(&ioc->chip->HostInterruptStatus);
3742 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
3743 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3744 "%s: successful count(%d), timeout(%d)\n",
3745 ioc->name, __func__, count, timeout));
3746 return 0;
3747 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3748 doorbell = readl(&ioc->chip->Doorbell);
3749 if ((doorbell & MPI2_IOC_STATE_MASK) ==
3750 MPI2_IOC_STATE_FAULT) {
3751 mpt3sas_base_fault_info(ioc , doorbell);
3752 return -EFAULT;
3753 }
3754 } else if (int_status == 0xFFFFFFFF)
3755 goto out;
3756
3757 if (sleep_flag == CAN_SLEEP)
3758 usleep_range(1000, 1500);
3759 else
3760 udelay(500);
3761 count++;
3762 } while (--cntdn);
3763
3764 out:
3765 pr_err(MPT3SAS_FMT
3766 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3767 ioc->name, __func__, count, int_status);
3768 return -EFAULT;
3769}
3770
3771/**
3772 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
3773 * @ioc: per adapter object
3774 * @timeout: timeout in second
3775 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3776 *
3777 * Returns 0 for success, non-zero for failure.
3778 *
3779 */
3780static int
3781_base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout,
3782 int sleep_flag)
3783{
3784 u32 cntdn, count;
3785 u32 doorbell_reg;
3786
3787 count = 0;
3788 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3789 do {
3790 doorbell_reg = readl(&ioc->chip->Doorbell);
3791 if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
3792 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3793 "%s: successful count(%d), timeout(%d)\n",
3794 ioc->name, __func__, count, timeout));
3795 return 0;
3796 }
3797 if (sleep_flag == CAN_SLEEP)
3798 usleep_range(1000, 1500);
3799 else
3800 udelay(500);
3801 count++;
3802 } while (--cntdn);
3803
3804 pr_err(MPT3SAS_FMT
3805 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
3806 ioc->name, __func__, count, doorbell_reg);
3807 return -EFAULT;
3808}
3809
3810/**
3811 * _base_send_ioc_reset - send doorbell reset
3812 * @ioc: per adapter object
3813 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
3814 * @timeout: timeout in second
3815 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3816 *
3817 * Returns 0 for success, non-zero for failure.
3818 */
3819static int
3820_base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout,
3821 int sleep_flag)
3822{
3823 u32 ioc_state;
3824 int r = 0;
3825
3826 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
3827 pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
3828 ioc->name, __func__);
3829 return -EFAULT;
3830 }
3831
3832 if (!(ioc->facts.IOCCapabilities &
3833 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
3834 return -EFAULT;
3835
3836 pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
3837
3838 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
3839 &ioc->chip->Doorbell);
3840 if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) {
3841 r = -EFAULT;
3842 goto out;
3843 }
3844 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
3845 timeout, sleep_flag);
3846 if (ioc_state) {
3847 pr_err(MPT3SAS_FMT
3848 "%s: failed going to ready state (ioc_state=0x%x)\n",
3849 ioc->name, __func__, ioc_state);
3850 r = -EFAULT;
3851 goto out;
3852 }
3853 out:
3854 pr_info(MPT3SAS_FMT "message unit reset: %s\n",
3855 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
3856 return r;
3857}
3858
3859/**
3860 * _base_handshake_req_reply_wait - send request thru doorbell interface
3861 * @ioc: per adapter object
3862 * @request_bytes: request length
3863 * @request: pointer having request payload
3864 * @reply_bytes: reply length
3865 * @reply: pointer to reply payload
3866 * @timeout: timeout in second
3867 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3868 *
3869 * Returns 0 for success, non-zero for failure.
3870 */
3871static int
3872_base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
3873 u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag)
3874{
3875 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
3876 int i;
3877 u8 failed;
3878 u16 dummy;
3879 __le32 *mfp;
3880
3881 /* make sure doorbell is not in use */
3882 if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
3883 pr_err(MPT3SAS_FMT
3884 "doorbell is in use (line=%d)\n",
3885 ioc->name, __LINE__);
3886 return -EFAULT;
3887 }
3888
3889 /* clear pending doorbell interrupts from previous state changes */
3890 if (readl(&ioc->chip->HostInterruptStatus) &
3891 MPI2_HIS_IOC2SYS_DB_STATUS)
3892 writel(0, &ioc->chip->HostInterruptStatus);
3893
3894 /* send message to ioc */
3895 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
3896 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
3897 &ioc->chip->Doorbell);
3898
3899 if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) {
3900 pr_err(MPT3SAS_FMT
3901 "doorbell handshake int failed (line=%d)\n",
3902 ioc->name, __LINE__);
3903 return -EFAULT;
3904 }
3905 writel(0, &ioc->chip->HostInterruptStatus);
3906
3907 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) {
3908 pr_err(MPT3SAS_FMT
3909 "doorbell handshake ack failed (line=%d)\n",
3910 ioc->name, __LINE__);
3911 return -EFAULT;
3912 }
3913
3914 /* send message 32-bits at a time */
3915 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
3916 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
3917 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag)))
3918 failed = 1;
3919 }
3920
3921 if (failed) {
3922 pr_err(MPT3SAS_FMT
3923 "doorbell handshake sending request failed (line=%d)\n",
3924 ioc->name, __LINE__);
3925 return -EFAULT;
3926 }
3927
3928 /* now wait for the reply */
3929 if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) {
3930 pr_err(MPT3SAS_FMT
3931 "doorbell handshake int failed (line=%d)\n",
3932 ioc->name, __LINE__);
3933 return -EFAULT;
3934 }
3935
3936 /* read the first two 16-bits, it gives the total length of the reply */
3937 reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3938 & MPI2_DOORBELL_DATA_MASK);
3939 writel(0, &ioc->chip->HostInterruptStatus);
3940 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3941 pr_err(MPT3SAS_FMT
3942 "doorbell handshake int failed (line=%d)\n",
3943 ioc->name, __LINE__);
3944 return -EFAULT;
3945 }
3946 reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3947 & MPI2_DOORBELL_DATA_MASK);
3948 writel(0, &ioc->chip->HostInterruptStatus);
3949
3950 for (i = 2; i < default_reply->MsgLength * 2; i++) {
3951 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3952 pr_err(MPT3SAS_FMT
3953 "doorbell handshake int failed (line=%d)\n",
3954 ioc->name, __LINE__);
3955 return -EFAULT;
3956 }
3957 if (i >= reply_bytes/2) /* overflow case */
3958 dummy = readl(&ioc->chip->Doorbell);
3959 else
3960 reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3961 & MPI2_DOORBELL_DATA_MASK);
3962 writel(0, &ioc->chip->HostInterruptStatus);
3963 }
3964
3965 _base_wait_for_doorbell_int(ioc, 5, sleep_flag);
3966 if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) {
3967 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3968 "doorbell is in use (line=%d)\n", ioc->name, __LINE__));
3969 }
3970 writel(0, &ioc->chip->HostInterruptStatus);
3971
3972 if (ioc->logging_level & MPT_DEBUG_INIT) {
3973 mfp = (__le32 *)reply;
3974 pr_info("\toffset:data\n");
3975 for (i = 0; i < reply_bytes/4; i++)
3976 pr_info("\t[0x%02x]:%08x\n", i*4,
3977 le32_to_cpu(mfp[i]));
3978 }
3979 return 0;
3980}
3981
3982/**
3983 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
3984 * @ioc: per adapter object
3985 * @mpi_reply: the reply payload from FW
3986 * @mpi_request: the request payload sent to FW
3987 *
3988 * The SAS IO Unit Control Request message allows the host to perform low-level
3989 * operations, such as resets on the PHYs of the IO Unit, also allows the host
3990 * to obtain the IOC assigned device handles for a device if it has other
3991 * identifying information about the device, in addition allows the host to
3992 * remove IOC resources associated with the device.
3993 *
3994 * Returns 0 for success, non-zero for failure.
3995 */
3996int
3997mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
3998 Mpi2SasIoUnitControlReply_t *mpi_reply,
3999 Mpi2SasIoUnitControlRequest_t *mpi_request)
4000{
4001 u16 smid;
4002 u32 ioc_state;
4003 unsigned long timeleft;
eb44552b 4004 bool issue_reset = false;
f92363d1
SR		 4005 int rc;
4006 void *request;
4007 u16 wait_state_count;
4008
4009 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4010 __func__));
4011
4012 mutex_lock(&ioc->base_cmds.mutex);
4013
4014 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
4015 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
4016 ioc->name, __func__);
4017 rc = -EAGAIN;
4018 goto out;
4019 }
4020
4021 wait_state_count = 0;
4022 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4023 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
4024 if (wait_state_count++ == 10) {
4025 pr_err(MPT3SAS_FMT
4026 "%s: failed due to ioc not operational\n",
4027 ioc->name, __func__);
4028 rc = -EFAULT;
4029 goto out;
4030 }
4031 ssleep(1);
4032 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4033 pr_info(MPT3SAS_FMT
4034 "%s: waiting for operational state(count=%d)\n",
4035 ioc->name, __func__, wait_state_count);
4036 }
4037
4038 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4039 if (!smid) {
4040 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4041 ioc->name, __func__);
4042 rc = -EAGAIN;
4043 goto out;
4044 }
4045
4046 rc = 0;
4047 ioc->base_cmds.status = MPT3_CMD_PENDING;
4048 request = mpt3sas_base_get_msg_frame(ioc, smid);
4049 ioc->base_cmds.smid = smid;
4050 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
4051 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
4052 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
4053 ioc->ioc_link_reset_in_progress = 1;
4054 init_completion(&ioc->base_cmds.done);
4055 mpt3sas_base_put_smid_default(ioc, smid);
4056 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
4057 msecs_to_jiffies(10000));
4058 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
4059 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
4060 ioc->ioc_link_reset_in_progress)
4061 ioc->ioc_link_reset_in_progress = 0;
4062 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4063 pr_err(MPT3SAS_FMT "%s: timeout\n",
4064 ioc->name, __func__);
4065 _debug_dump_mf(mpi_request,
4066 sizeof(Mpi2SasIoUnitControlRequest_t)/4);
4067 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
eb44552b 4068 issue_reset = true;
f92363d1
SR		 4069 goto issue_host_reset;
4070 }
4071 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4072 memcpy(mpi_reply, ioc->base_cmds.reply,
4073 sizeof(Mpi2SasIoUnitControlReply_t));
4074 else
4075 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
4076 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4077 goto out;
4078
4079 issue_host_reset:
4080 if (issue_reset)
4081 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
4082 FORCE_BIG_HAMMER);
4083 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4084 rc = -EFAULT;
4085 out:
4086 mutex_unlock(&ioc->base_cmds.mutex);
4087 return rc;
4088}
4089
4090/**
4091 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
4092 * @ioc: per adapter object
4093 * @mpi_reply: the reply payload from FW
4094 * @mpi_request: the request payload sent to FW
4095 *
4096 * The SCSI Enclosure Processor request message causes the IOC to
4097 * communicate with SES devices to control LED status signals.
4098 *
4099 * Returns 0 for success, non-zero for failure.
4100 */
4101int
4102mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
4103 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
4104{
4105 u16 smid;
4106 u32 ioc_state;
4107 unsigned long timeleft;
eb44552b 4108 bool issue_reset = false;
f92363d1
SR		 4109 int rc;
4110 void *request;
4111 u16 wait_state_count;
4112
4113 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4114 __func__));
4115
4116 mutex_lock(&ioc->base_cmds.mutex);
4117
4118 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
4119 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
4120 ioc->name, __func__);
4121 rc = -EAGAIN;
4122 goto out;
4123 }
4124
4125 wait_state_count = 0;
4126 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4127 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
4128 if (wait_state_count++ == 10) {
4129 pr_err(MPT3SAS_FMT
4130 "%s: failed due to ioc not operational\n",
4131 ioc->name, __func__);
4132 rc = -EFAULT;
4133 goto out;
4134 }
4135 ssleep(1);
4136 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
4137 pr_info(MPT3SAS_FMT
4138 "%s: waiting for operational state(count=%d)\n",
4139 ioc->name,
4140 __func__, wait_state_count);
4141 }
4142
4143 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4144 if (!smid) {
4145 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4146 ioc->name, __func__);
4147 rc = -EAGAIN;
4148 goto out;
4149 }
4150
4151 rc = 0;
4152 ioc->base_cmds.status = MPT3_CMD_PENDING;
4153 request = mpt3sas_base_get_msg_frame(ioc, smid);
4154 ioc->base_cmds.smid = smid;
4155 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
4156 init_completion(&ioc->base_cmds.done);
4157 mpt3sas_base_put_smid_default(ioc, smid);
4158 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
4159 msecs_to_jiffies(10000));
4160 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4161 pr_err(MPT3SAS_FMT "%s: timeout\n",
4162 ioc->name, __func__);
4163 _debug_dump_mf(mpi_request,
4164 sizeof(Mpi2SepRequest_t)/4);
4165 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
eb44552b 4166 issue_reset = false;
f92363d1
SR		 4167 goto issue_host_reset;
4168 }
4169 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
4170 memcpy(mpi_reply, ioc->base_cmds.reply,
4171 sizeof(Mpi2SepReply_t));
4172 else
4173 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
4174 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4175 goto out;
4176
4177 issue_host_reset:
4178 if (issue_reset)
4179 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
4180 FORCE_BIG_HAMMER);
4181 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4182 rc = -EFAULT;
4183 out:
4184 mutex_unlock(&ioc->base_cmds.mutex);
4185 return rc;
4186}
4187
4188/**
4189 * _base_get_port_facts - obtain port facts reply and save in ioc
4190 * @ioc: per adapter object
4191 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4192 *
4193 * Returns 0 for success, non-zero for failure.
4194 */
4195static int
4196_base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port, int sleep_flag)
4197{
4198 Mpi2PortFactsRequest_t mpi_request;
4199 Mpi2PortFactsReply_t mpi_reply;
4200 struct mpt3sas_port_facts *pfacts;
4201 int mpi_reply_sz, mpi_request_sz, r;
4202
4203 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4204 __func__));
4205
4206 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
4207 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
4208 memset(&mpi_request, 0, mpi_request_sz);
4209 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
4210 mpi_request.PortNumber = port;
4211 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
4212 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
4213
4214 if (r != 0) {
4215 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4216 ioc->name, __func__, r);
4217 return r;
4218 }
4219
4220 pfacts = &ioc->pfacts[port];
4221 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
4222 pfacts->PortNumber = mpi_reply.PortNumber;
4223 pfacts->VP_ID = mpi_reply.VP_ID;
4224 pfacts->VF_ID = mpi_reply.VF_ID;
4225 pfacts->MaxPostedCmdBuffers =
4226 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
4227
4228 return 0;
4229}
4230
4dc8c808
SR		 4231/**
4232 * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
4233 * @ioc: per adapter object
4234 * @timeout:
4235 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4236 *
4237 * Returns 0 for success, non-zero for failure.
4238 */
4239static int
4240_base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout,
4241 int sleep_flag)
4242{
4243 u32 ioc_state;
4244 int rc;
4245
4246 dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name,
4247 __func__));
4248
4249 if (ioc->pci_error_recovery) {
4250 dfailprintk(ioc, printk(MPT3SAS_FMT
4251 "%s: host in pci error recovery\n", ioc->name, __func__));
4252 return -EFAULT;
4253 }
4254
4255 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4256 dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4257 ioc->name, __func__, ioc_state));
4258
4259 if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
4260 (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4261 return 0;
4262
4263 if (ioc_state & MPI2_DOORBELL_USED) {
4264 dhsprintk(ioc, printk(MPT3SAS_FMT
4265 "unexpected doorbell active!\n", ioc->name));
4266 goto issue_diag_reset;
4267 }
4268
4269 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4270 mpt3sas_base_fault_info(ioc, ioc_state &
4271 MPI2_DOORBELL_DATA_MASK);
4272 goto issue_diag_reset;
4273 }
4274
4275 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
4276 timeout, sleep_flag);
4277 if (ioc_state) {
4278 dfailprintk(ioc, printk(MPT3SAS_FMT
4279 "%s: failed going to ready state (ioc_state=0x%x)\n",
4280 ioc->name, __func__, ioc_state));
4281 return -EFAULT;
4282 }
4283
4284 issue_diag_reset:
4285 rc = _base_diag_reset(ioc, sleep_flag);
4286 return rc;
4287}
4288
f92363d1
SR		 4289/**
4290 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
4291 * @ioc: per adapter object
4292 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4293 *
4294 * Returns 0 for success, non-zero for failure.
4295 */
4296static int
4297_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4298{
4299 Mpi2IOCFactsRequest_t mpi_request;
4300 Mpi2IOCFactsReply_t mpi_reply;
4301 struct mpt3sas_facts *facts;
4302 int mpi_reply_sz, mpi_request_sz, r;
4303
4304 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4305 __func__));
4306
4dc8c808
SR		 4307 r = _base_wait_for_iocstate(ioc, 10, sleep_flag);
4308 if (r) {
4309 dfailprintk(ioc, printk(MPT3SAS_FMT
4310 "%s: failed getting to correct state\n",
4311 ioc->name, __func__));
4312 return r;
4313 }
f92363d1
SR		 4314 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
4315 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
4316 memset(&mpi_request, 0, mpi_request_sz);
4317 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
4318 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
4319 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
4320
4321 if (r != 0) {
4322 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4323 ioc->name, __func__, r);
4324 return r;
4325 }
4326
4327 facts = &ioc->facts;
4328 memset(facts, 0, sizeof(struct mpt3sas_facts));
4329 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
4330 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
4331 facts->VP_ID = mpi_reply.VP_ID;
4332 facts->VF_ID = mpi_reply.VF_ID;
4333 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
4334 facts->MaxChainDepth = mpi_reply.MaxChainDepth;
4335 facts->WhoInit = mpi_reply.WhoInit;
4336 facts->NumberOfPorts = mpi_reply.NumberOfPorts;
4337 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
4338 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
4339 facts->MaxReplyDescriptorPostQueueDepth =
4340 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
4341 facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
4342 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
4343 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
4344 ioc->ir_firmware = 1;
9b05c91a
SR		 4345 if ((facts->IOCCapabilities &
4346 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE))
4347 ioc->rdpq_array_capable = 1;
f92363d1
SR		 4348 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
4349 facts->IOCRequestFrameSize =
4350 le16_to_cpu(mpi_reply.IOCRequestFrameSize);
ebb3024e
SS		 4351 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
4352 facts->IOCMaxChainSegmentSize =
4353 le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize);
4354 }
f92363d1
SR		 4355 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
4356 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
4357 ioc->shost->max_id = -1;
4358 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
4359 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
4360 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
4361 facts->HighPriorityCredit =
4362 le16_to_cpu(mpi_reply.HighPriorityCredit);
4363 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
4364 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
4365
4366 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4367 "hba queue depth(%d), max chains per io(%d)\n",
4368 ioc->name, facts->RequestCredit,
4369 facts->MaxChainDepth));
4370 dinitprintk(ioc, pr_info(MPT3SAS_FMT
4371 "request frame size(%d), reply frame size(%d)\n", ioc->name,
4372 facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
4373 return 0;
4374}
4375
4376/**
4377 * _base_send_ioc_init - send ioc_init to firmware
4378 * @ioc: per adapter object
4379 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4380 *
4381 * Returns 0 for success, non-zero for failure.
4382 */
4383static int
4384_base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4385{
4386 Mpi2IOCInitRequest_t mpi_request;
4387 Mpi2IOCInitReply_t mpi_reply;
9b05c91a 4388 int i, r = 0;
f92363d1
SR		 4389 struct timeval current_time;
4390 u16 ioc_status;
9b05c91a
SR		 4391 u32 reply_post_free_array_sz = 0;
4392 Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL;
4393 dma_addr_t reply_post_free_array_dma;
f92363d1
SR		 4394
4395 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4396 __func__));
4397
4398 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
4399 mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
4400 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
4401 mpi_request.VF_ID = 0; /* TODO */
4402 mpi_request.VP_ID = 0;
d357e84d 4403 mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged);
f92363d1
SR		 4404 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
4405
4406 if (_base_is_controller_msix_enabled(ioc))
4407 mpi_request.HostMSIxVectors = ioc->reply_queue_count;
4408 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
4409 mpi_request.ReplyDescriptorPostQueueDepth =
4410 cpu_to_le16(ioc->reply_post_queue_depth);
4411 mpi_request.ReplyFreeQueueDepth =
4412 cpu_to_le16(ioc->reply_free_queue_depth);
4413
4414 mpi_request.SenseBufferAddressHigh =
4415 cpu_to_le32((u64)ioc->sense_dma >> 32);
4416 mpi_request.SystemReplyAddressHigh =
4417 cpu_to_le32((u64)ioc->reply_dma >> 32);
4418 mpi_request.SystemRequestFrameBaseAddress =
4419 cpu_to_le64((u64)ioc->request_dma);
4420 mpi_request.ReplyFreeQueueAddress =
4421 cpu_to_le64((u64)ioc->reply_free_dma);
f92363d1 4422
9b05c91a
SR		 4423 if (ioc->rdpq_array_enable) {
4424 reply_post_free_array_sz = ioc->reply_queue_count *
4425 sizeof(Mpi2IOCInitRDPQArrayEntry);
4426 reply_post_free_array = pci_alloc_consistent(ioc->pdev,
4427 reply_post_free_array_sz, &reply_post_free_array_dma);
4428 if (!reply_post_free_array) {
4429 pr_err(MPT3SAS_FMT
4430 "reply_post_free_array: pci_alloc_consistent failed\n",
4431 ioc->name);
4432 r = -ENOMEM;
4433 goto out;
4434 }
4435 memset(reply_post_free_array, 0, reply_post_free_array_sz);
4436 for (i = 0; i < ioc->reply_queue_count; i++)
4437 reply_post_free_array[i].RDPQBaseAddress =
4438 cpu_to_le64(
4439 (u64)ioc->reply_post[i].reply_post_free_dma);
4440 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
4441 mpi_request.ReplyDescriptorPostQueueAddress =
4442 cpu_to_le64((u64)reply_post_free_array_dma);
4443 } else {
4444 mpi_request.ReplyDescriptorPostQueueAddress =
4445 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
4446 }
f92363d1
SR		 4447
4448 /* This time stamp specifies number of milliseconds
4449 * since epoch ~ midnight January 1, 1970.
4450 */
4451 do_gettimeofday(&current_time);
4452 mpi_request.TimeStamp = cpu_to_le64((u64)current_time.tv_sec * 1000 +
4453 (current_time.tv_usec / 1000));
4454
4455 if (ioc->logging_level & MPT_DEBUG_INIT) {
4456 __le32 *mfp;
4457 int i;
4458
4459 mfp = (__le32 *)&mpi_request;
4460 pr_info("\toffset:data\n");
4461 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
4462 pr_info("\t[0x%02x]:%08x\n", i*4,
4463 le32_to_cpu(mfp[i]));
4464 }
4465
4466 r = _base_handshake_req_reply_wait(ioc,
4467 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
4468 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10,
4469 sleep_flag);
4470
4471 if (r != 0) {
4472 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
4473 ioc->name, __func__, r);
9b05c91a 4474 goto out;
f92363d1
SR		 4475 }
4476
4477 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
4478 if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
4479 mpi_reply.IOCLogInfo) {
4480 pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
4481 r = -EIO;
4482 }
4483
9b05c91a
SR		 4484out:
4485 if (reply_post_free_array)
4486 pci_free_consistent(ioc->pdev, reply_post_free_array_sz,
4487 reply_post_free_array,
4488 reply_post_free_array_dma);
4489 return r;
f92363d1
SR		 4490}
4491
4492/**
4493 * mpt3sas_port_enable_done - command completion routine for port enable
4494 * @ioc: per adapter object
4495 * @smid: system request message index
4496 * @msix_index: MSIX table index supplied by the OS
4497 * @reply: reply message frame(lower 32bit addr)
4498 *
4499 * Return 1 meaning mf should be freed from _base_interrupt
4500 * 0 means the mf is freed from this function.
4501 */
4502u8
4503mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
4504 u32 reply)
4505{
4506 MPI2DefaultReply_t *mpi_reply;
4507 u16 ioc_status;
4508
4509 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
4510 return 1;
4511
4512 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
4513 if (!mpi_reply)
4514 return 1;
4515
4516 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
4517 return 1;
4518
4519 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
4520 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
4521 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
4522 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
4523 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4524 if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
4525 ioc->port_enable_failed = 1;
4526
4527 if (ioc->is_driver_loading) {
4528 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
4529 mpt3sas_port_enable_complete(ioc);
4530 return 1;
4531 } else {
4532 ioc->start_scan_failed = ioc_status;
4533 ioc->start_scan = 0;
4534 return 1;
4535 }
4536 }
4537 complete(&ioc->port_enable_cmds.done);
4538 return 1;
4539}
4540
4541/**
4542 * _base_send_port_enable - send port_enable(discovery stuff) to firmware
4543 * @ioc: per adapter object
4544 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4545 *
4546 * Returns 0 for success, non-zero for failure.
4547 */
4548static int
4549_base_send_port_enable(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4550{
4551 Mpi2PortEnableRequest_t *mpi_request;
4552 Mpi2PortEnableReply_t *mpi_reply;
4553 unsigned long timeleft;
4554 int r = 0;
4555 u16 smid;
4556 u16 ioc_status;
4557
4558 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4559
4560 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4561 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4562 ioc->name, __func__);
4563 return -EAGAIN;
4564 }
4565
4566 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4567 if (!smid) {
4568 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4569 ioc->name, __func__);
4570 return -EAGAIN;
4571 }
4572
4573 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4574 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4575 ioc->port_enable_cmds.smid = smid;
4576 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4577 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4578
4579 init_completion(&ioc->port_enable_cmds.done);
4580 mpt3sas_base_put_smid_default(ioc, smid);
4581 timeleft = wait_for_completion_timeout(&ioc->port_enable_cmds.done,
4582 300*HZ);
4583 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
4584 pr_err(MPT3SAS_FMT "%s: timeout\n",
4585 ioc->name, __func__);
4586 _debug_dump_mf(mpi_request,
4587 sizeof(Mpi2PortEnableRequest_t)/4);
4588 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
4589 r = -EFAULT;
4590 else
4591 r = -ETIME;
4592 goto out;
4593 }
4594
4595 mpi_reply = ioc->port_enable_cmds.reply;
4596 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4597 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4598 pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
4599 ioc->name, __func__, ioc_status);
4600 r = -EFAULT;
4601 goto out;
4602 }
4603
4604 out:
4605 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
4606 pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
4607 "SUCCESS" : "FAILED"));
4608 return r;
4609}
4610
4611/**
4612 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
4613 * @ioc: per adapter object
4614 *
4615 * Returns 0 for success, non-zero for failure.
4616 */
4617int
4618mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
4619{
4620 Mpi2PortEnableRequest_t *mpi_request;
4621 u16 smid;
4622
4623 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4624
4625 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4626 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4627 ioc->name, __func__);
4628 return -EAGAIN;
4629 }
4630
4631 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4632 if (!smid) {
4633 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4634 ioc->name, __func__);
4635 return -EAGAIN;
4636 }
4637
4638 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4639 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4640 ioc->port_enable_cmds.smid = smid;
4641 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4642 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4643
4644 mpt3sas_base_put_smid_default(ioc, smid);
4645 return 0;
4646}
4647
4648/**
4649 * _base_determine_wait_on_discovery - desposition
4650 * @ioc: per adapter object
4651 *
4652 * Decide whether to wait on discovery to complete. Used to either
4653 * locate boot device, or report volumes ahead of physical devices.
4654 *
4655 * Returns 1 for wait, 0 for don't wait
4656 */
4657static int
4658_base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
4659{
4660 /* We wait for discovery to complete if IR firmware is loaded.
4661 * The sas topology events arrive before PD events, so we need time to
4662 * turn on the bit in ioc->pd_handles to indicate PD
4663 * Also, it maybe required to report Volumes ahead of physical
4664 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
4665 */
4666 if (ioc->ir_firmware)
4667 return 1;
4668
4669 /* if no Bios, then we don't need to wait */
4670 if (!ioc->bios_pg3.BiosVersion)
4671 return 0;
4672
4673 /* Bios is present, then we drop down here.
4674 *
4675 * If there any entries in the Bios Page 2, then we wait
4676 * for discovery to complete.
4677 */
4678
4679 /* Current Boot Device */
4680 if ((ioc->bios_pg2.CurrentBootDeviceForm &
4681 MPI2_BIOSPAGE2_FORM_MASK) ==
4682 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4683 /* Request Boot Device */
4684 (ioc->bios_pg2.ReqBootDeviceForm &
4685 MPI2_BIOSPAGE2_FORM_MASK) ==
4686 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4687 /* Alternate Request Boot Device */
4688 (ioc->bios_pg2.ReqAltBootDeviceForm &
4689 MPI2_BIOSPAGE2_FORM_MASK) ==
4690 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
4691 return 0;
4692
4693 return 1;
4694}
4695
4696/**
4697 * _base_unmask_events - turn on notification for this event
4698 * @ioc: per adapter object
4699 * @event: firmware event
4700 *
4701 * The mask is stored in ioc->event_masks.
4702 */
4703static void
4704_base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
4705{
4706 u32 desired_event;
4707
4708 if (event >= 128)
4709 return;
4710
4711 desired_event = (1 << (event % 32));
4712
4713 if (event < 32)
4714 ioc->event_masks[0] &= ~desired_event;
4715 else if (event < 64)
4716 ioc->event_masks[1] &= ~desired_event;
4717 else if (event < 96)
4718 ioc->event_masks[2] &= ~desired_event;
4719 else if (event < 128)
4720 ioc->event_masks[3] &= ~desired_event;
4721}
4722
4723/**
4724 * _base_event_notification - send event notification
4725 * @ioc: per adapter object
4726 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4727 *
4728 * Returns 0 for success, non-zero for failure.
4729 */
4730static int
4731_base_event_notification(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4732{
4733 Mpi2EventNotificationRequest_t *mpi_request;
4734 unsigned long timeleft;
4735 u16 smid;
4736 int r = 0;
4737 int i;
4738
4739 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4740 __func__));
4741
4742 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4743 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4744 ioc->name, __func__);
4745 return -EAGAIN;
4746 }
4747
4748 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4749 if (!smid) {
4750 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4751 ioc->name, __func__);
4752 return -EAGAIN;
4753 }
4754 ioc->base_cmds.status = MPT3_CMD_PENDING;
4755 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4756 ioc->base_cmds.smid = smid;
4757 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
4758 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
4759 mpi_request->VF_ID = 0; /* TODO */
4760 mpi_request->VP_ID = 0;
4761 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4762 mpi_request->EventMasks[i] =
4763 cpu_to_le32(ioc->event_masks[i]);
4764 init_completion(&ioc->base_cmds.done);
4765 mpt3sas_base_put_smid_default(ioc, smid);
4766 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
4767 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4768 pr_err(MPT3SAS_FMT "%s: timeout\n",
4769 ioc->name, __func__);
4770 _debug_dump_mf(mpi_request,
4771 sizeof(Mpi2EventNotificationRequest_t)/4);
4772 if (ioc->base_cmds.status & MPT3_CMD_RESET)
4773 r = -EFAULT;
4774 else
4775 r = -ETIME;
4776 } else
4777 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
4778 ioc->name, __func__));
4779 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4780 return r;
4781}
4782
4783/**
4784 * mpt3sas_base_validate_event_type - validating event types
4785 * @ioc: per adapter object
4786 * @event: firmware event
4787 *
4788 * This will turn on firmware event notification when application
4789 * ask for that event. We don't mask events that are already enabled.
4790 */
4791void
4792mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
4793{
4794 int i, j;
4795 u32 event_mask, desired_event;
4796 u8 send_update_to_fw;
4797
4798 for (i = 0, send_update_to_fw = 0; i <
4799 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
4800 event_mask = ~event_type[i];
4801 desired_event = 1;
4802 for (j = 0; j < 32; j++) {
4803 if (!(event_mask & desired_event) &&
4804 (ioc->event_masks[i] & desired_event)) {
4805 ioc->event_masks[i] &= ~desired_event;
4806 send_update_to_fw = 1;
4807 }
4808 desired_event = (desired_event << 1);
4809 }
4810 }
4811
4812 if (!send_update_to_fw)
4813 return;
4814
4815 mutex_lock(&ioc->base_cmds.mutex);
4816 _base_event_notification(ioc, CAN_SLEEP);
4817 mutex_unlock(&ioc->base_cmds.mutex);
4818}
4819
4820/**
4821 * _base_diag_reset - the "big hammer" start of day reset
4822 * @ioc: per adapter object
4823 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4824 *
4825 * Returns 0 for success, non-zero for failure.
4826 */
4827static int
4828_base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4829{
4830 u32 host_diagnostic;
4831 u32 ioc_state;
4832 u32 count;
4833 u32 hcb_size;
4834
4835 pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
4836
4837 drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
4838 ioc->name));
4839
4840 count = 0;
4841 do {
4842 /* Write magic sequence to WriteSequence register
4843 * Loop until in diagnostic mode
4844 */
4845 drsprintk(ioc, pr_info(MPT3SAS_FMT
4846 "write magic sequence\n", ioc->name));
4847 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4848 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
4849 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
4850 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
4851 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
4852 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
4853 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
4854
4855 /* wait 100 msec */
4856 if (sleep_flag == CAN_SLEEP)
4857 msleep(100);
4858 else
4859 mdelay(100);
4860
4861 if (count++ > 20)
4862 goto out;
4863
4864 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4865 drsprintk(ioc, pr_info(MPT3SAS_FMT
4866 "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
4867 ioc->name, count, host_diagnostic));
4868
4869 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
4870
4871 hcb_size = readl(&ioc->chip->HCBSize);
4872
4873 drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
4874 ioc->name));
4875 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
4876 &ioc->chip->HostDiagnostic);
4877
b453ff84
SR		 4878 /*This delay allows the chip PCIe hardware time to finish reset tasks*/
4879 if (sleep_flag == CAN_SLEEP)
4880 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
4881 else
4882 mdelay(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
f92363d1 4883
b453ff84
SR		 4884 /* Approximately 300 second max wait */
4885 for (count = 0; count < (300000000 /
4886 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
f92363d1
SR		 4887
4888 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4889
4890 if (host_diagnostic == 0xFFFFFFFF)
4891 goto out;
4892 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
4893 break;
4894
b453ff84 4895 /* Wait to pass the second read delay window */
f92363d1 4896 if (sleep_flag == CAN_SLEEP)
b453ff84
SR		 4897 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4898 / 1000);
f92363d1 4899 else
b453ff84
SR		 4900 mdelay(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4901 / 1000);
f92363d1
SR		 4902 }
4903
4904 if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
4905
4906 drsprintk(ioc, pr_info(MPT3SAS_FMT
4907 "restart the adapter assuming the HCB Address points to good F/W\n",
4908 ioc->name));
4909 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
4910 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
4911 writel(host_diagnostic, &ioc->chip->HostDiagnostic);
4912
4913 drsprintk(ioc, pr_info(MPT3SAS_FMT
4914 "re-enable the HCDW\n", ioc->name));
4915 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
4916 &ioc->chip->HCBSize);
4917 }
4918
4919 drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
4920 ioc->name));
4921 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
4922 &ioc->chip->HostDiagnostic);
4923
4924 drsprintk(ioc, pr_info(MPT3SAS_FMT
4925 "disable writes to the diagnostic register\n", ioc->name));
4926 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4927
4928 drsprintk(ioc, pr_info(MPT3SAS_FMT
4929 "Wait for FW to go to the READY state\n", ioc->name));
4930 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20,
4931 sleep_flag);
4932 if (ioc_state) {
4933 pr_err(MPT3SAS_FMT
4934 "%s: failed going to ready state (ioc_state=0x%x)\n",
4935 ioc->name, __func__, ioc_state);
4936 goto out;
4937 }
4938
4939 pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
4940 return 0;
4941
4942 out:
4943 pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
4944 return -EFAULT;
4945}
4946
4947/**
4948 * _base_make_ioc_ready - put controller in READY state
4949 * @ioc: per adapter object
4950 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4951 * @type: FORCE_BIG_HAMMER or SOFT_RESET
4952 *
4953 * Returns 0 for success, non-zero for failure.
4954 */
4955static int
4956_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
4957 enum reset_type type)
4958{
4959 u32 ioc_state;
4960 int rc;
4961 int count;
4962
4963 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4964 __func__));
4965
4966 if (ioc->pci_error_recovery)
4967 return 0;
4968
4969 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4970 dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4971 ioc->name, __func__, ioc_state));
4972
4973 /* if in RESET state, it should move to READY state shortly */
4974 count = 0;
4975 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
4976 while ((ioc_state & MPI2_IOC_STATE_MASK) !=
4977 MPI2_IOC_STATE_READY) {
4978 if (count++ == 10) {
4979 pr_err(MPT3SAS_FMT
4980 "%s: failed going to ready state (ioc_state=0x%x)\n",
4981 ioc->name, __func__, ioc_state);
4982 return -EFAULT;
4983 }
4984 if (sleep_flag == CAN_SLEEP)
4985 ssleep(1);
4986 else
4987 mdelay(1000);
4988 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4989 }
4990 }
4991
4992 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
4993 return 0;
4994
4995 if (ioc_state & MPI2_DOORBELL_USED) {
4996 dhsprintk(ioc, pr_info(MPT3SAS_FMT
4997 "unexpected doorbell active!\n",
4998 ioc->name));
4999 goto issue_diag_reset;
5000 }
5001
5002 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
5003 mpt3sas_base_fault_info(ioc, ioc_state &
5004 MPI2_DOORBELL_DATA_MASK);
5005 goto issue_diag_reset;
5006 }
5007
5008 if (type == FORCE_BIG_HAMMER)
5009 goto issue_diag_reset;
5010
5011 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
5012 if (!(_base_send_ioc_reset(ioc,
5013 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP))) {
5014 return 0;
5015 }
5016
5017 issue_diag_reset:
5018 rc = _base_diag_reset(ioc, CAN_SLEEP);
5019 return rc;
5020}
5021
5022/**
5023 * _base_make_ioc_operational - put controller in OPERATIONAL state
5024 * @ioc: per adapter object
5025 * @sleep_flag: CAN_SLEEP or NO_SLEEP
5026 *
5027 * Returns 0 for success, non-zero for failure.
5028 */
5029static int
5030_base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
5031{
5032 int r, i;
5033 unsigned long flags;
5034 u32 reply_address;
5035 u16 smid;
5036 struct _tr_list *delayed_tr, *delayed_tr_next;
fd0331b3
SS		 5037 struct _sc_list *delayed_sc, *delayed_sc_next;
5038 struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next;
7786ab6a 5039 u8 hide_flag;
f92363d1
SR		 5040 struct adapter_reply_queue *reply_q;
5041 long reply_post_free;
9b05c91a 5042 u32 reply_post_free_sz, index = 0;
f92363d1
SR		 5043
5044 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5045 __func__));
5046
5047 /* clean the delayed target reset list */
5048 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
5049 &ioc->delayed_tr_list, list) {
5050 list_del(&delayed_tr->list);
5051 kfree(delayed_tr);
5052 }
5053
5054
5055 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
5056 &ioc->delayed_tr_volume_list, list) {
5057 list_del(&delayed_tr->list);
5058 kfree(delayed_tr);
5059 }
5060
fd0331b3
SS		 5061 list_for_each_entry_safe(delayed_sc, delayed_sc_next,
5062 &ioc->delayed_sc_list, list) {
5063 list_del(&delayed_sc->list);
5064 kfree(delayed_sc);
5065 }
5066
5067 list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next,
5068 &ioc->delayed_event_ack_list, list) {
5069 list_del(&delayed_event_ack->list);
5070 kfree(delayed_event_ack);
5071 }
5072
f92363d1
SR		 5073 /* initialize the scsi lookup free list */
5074 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5075 INIT_LIST_HEAD(&ioc->free_list);
5076 smid = 1;
5077 for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
5078 INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
5079 ioc->scsi_lookup[i].cb_idx = 0xFF;
5080 ioc->scsi_lookup[i].smid = smid;
5081 ioc->scsi_lookup[i].scmd = NULL;
7786ab6a 5082 ioc->scsi_lookup[i].direct_io = 0;
f92363d1
SR		 5083 list_add_tail(&ioc->scsi_lookup[i].tracker_list,
5084 &ioc->free_list);
5085 }
5086
5087 /* hi-priority queue */
5088 INIT_LIST_HEAD(&ioc->hpr_free_list);
5089 smid = ioc->hi_priority_smid;
5090 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
5091 ioc->hpr_lookup[i].cb_idx = 0xFF;
5092 ioc->hpr_lookup[i].smid = smid;
5093 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
5094 &ioc->hpr_free_list);
5095 }
5096
5097 /* internal queue */
5098 INIT_LIST_HEAD(&ioc->internal_free_list);
5099 smid = ioc->internal_smid;
5100 for (i = 0; i < ioc->internal_depth; i++, smid++) {
5101 ioc->internal_lookup[i].cb_idx = 0xFF;
5102 ioc->internal_lookup[i].smid = smid;
5103 list_add_tail(&ioc->internal_lookup[i].tracker_list,
5104 &ioc->internal_free_list);
5105 }
5106
5107 /* chain pool */
5108 INIT_LIST_HEAD(&ioc->free_chain_list);
5109 for (i = 0; i < ioc->chain_depth; i++)
5110 list_add_tail(&ioc->chain_lookup[i].tracker_list,
5111 &ioc->free_chain_list);
5112
5113 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5114
5115 /* initialize Reply Free Queue */
5116 for (i = 0, reply_address = (u32)ioc->reply_dma ;
5117 i < ioc->reply_free_queue_depth ; i++, reply_address +=
5118 ioc->reply_sz)
5119 ioc->reply_free[i] = cpu_to_le32(reply_address);
5120
5121 /* initialize reply queues */
5122 if (ioc->is_driver_loading)
5123 _base_assign_reply_queues(ioc);
5124
5125 /* initialize Reply Post Free Queue */
f92363d1
SR		 5126 reply_post_free_sz = ioc->reply_post_queue_depth *
5127 sizeof(Mpi2DefaultReplyDescriptor_t);
9b05c91a 5128 reply_post_free = (long)ioc->reply_post[index].reply_post_free;
f92363d1
SR		 5129 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
5130 reply_q->reply_post_host_index = 0;
5131 reply_q->reply_post_free = (Mpi2ReplyDescriptorsUnion_t *)
5132 reply_post_free;
5133 for (i = 0; i < ioc->reply_post_queue_depth; i++)
5134 reply_q->reply_post_free[i].Words =
5135 cpu_to_le64(ULLONG_MAX);
5136 if (!_base_is_controller_msix_enabled(ioc))
5137 goto skip_init_reply_post_free_queue;
9b05c91a
SR		 5138 /*
5139 * If RDPQ is enabled, switch to the next allocation.
5140 * Otherwise advance within the contiguous region.
5141 */
5142 if (ioc->rdpq_array_enable)
5143 reply_post_free = (long)
5144 ioc->reply_post[++index].reply_post_free;
5145 else
5146 reply_post_free += reply_post_free_sz;
f92363d1
SR		 5147 }
5148 skip_init_reply_post_free_queue:
5149
5150 r = _base_send_ioc_init(ioc, sleep_flag);
5151 if (r)
5152 return r;
5153
5154 /* initialize reply free host index */
5155 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
5156 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
5157
5158 /* initialize reply post host index */
5159 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
fb77bb53
SR		 5160 if (ioc->msix96_vector)
5161 writel((reply_q->msix_index & 7)<<
5162 MPI2_RPHI_MSIX_INDEX_SHIFT,
5163 ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
5164 else
5165 writel(reply_q->msix_index <<
5166 MPI2_RPHI_MSIX_INDEX_SHIFT,
5167 &ioc->chip->ReplyPostHostIndex);
5168
f92363d1
SR		 5169 if (!_base_is_controller_msix_enabled(ioc))
5170 goto skip_init_reply_post_host_index;
5171 }
5172
5173 skip_init_reply_post_host_index:
5174
5175 _base_unmask_interrupts(ioc);
5176 r = _base_event_notification(ioc, sleep_flag);
5177 if (r)
5178 return r;
5179
5180 if (sleep_flag == CAN_SLEEP)
5181 _base_static_config_pages(ioc);
5182
5183
5184 if (ioc->is_driver_loading) {
7786ab6a
SR		 5185
5186 if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier
5187 == 0x80) {
5188 hide_flag = (u8) (
5189 le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) &
5190 MFG_PAGE10_HIDE_SSDS_MASK);
5191 if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK)
5192 ioc->mfg_pg10_hide_flag = hide_flag;
5193 }
5194
f92363d1
SR		 5195 ioc->wait_for_discovery_to_complete =
5196 _base_determine_wait_on_discovery(ioc);
5197
5198 return r; /* scan_start and scan_finished support */
5199 }
5200
5201 r = _base_send_port_enable(ioc, sleep_flag);
5202 if (r)
5203 return r;
5204
5205 return r;
5206}
5207
5208/**
5209 * mpt3sas_base_free_resources - free resources controller resources
5210 * @ioc: per adapter object
5211 *
5212 * Return nothing.
5213 */
5214void
5215mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
5216{
f92363d1
SR		 5217 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5218 __func__));
5219
08c4d550
SR		 5220 /* synchronizing freeing resource with pci_access_mutex lock */
5221 mutex_lock(&ioc->pci_access_mutex);
cf9bd21a
JL		 5222 if (ioc->chip_phys && ioc->chip) {
5223 _base_mask_interrupts(ioc);
5224 ioc->shost_recovery = 1;
5225 _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
5226 ioc->shost_recovery = 0;
5227 }
5228
580d4e31 5229 mpt3sas_base_unmap_resources(ioc);
08c4d550 5230 mutex_unlock(&ioc->pci_access_mutex);
f92363d1
SR		 5231 return;
5232}
5233
5234/**
5235 * mpt3sas_base_attach - attach controller instance
5236 * @ioc: per adapter object
5237 *
5238 * Returns 0 for success, non-zero for failure.
5239 */
5240int
5241mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
5242{
5243 int r, i;
5244 int cpu_id, last_cpu_id = 0;
5245
5246 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5247 __func__));
5248
5249 /* setup cpu_msix_table */
5250 ioc->cpu_count = num_online_cpus();
5251 for_each_online_cpu(cpu_id)
5252 last_cpu_id = cpu_id;
5253 ioc->cpu_msix_table_sz = last_cpu_id + 1;
5254 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
5255 ioc->reply_queue_count = 1;
5256 if (!ioc->cpu_msix_table) {
5257 dfailprintk(ioc, pr_info(MPT3SAS_FMT
5258 "allocation for cpu_msix_table failed!!!\n",
5259 ioc->name));
5260 r = -ENOMEM;
5261 goto out_free_resources;
5262 }
5263
7786ab6a
SR		 5264 if (ioc->is_warpdrive) {
5265 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
5266 sizeof(resource_size_t *), GFP_KERNEL);
5267 if (!ioc->reply_post_host_index) {
5268 dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation "
5269 "for cpu_msix_table failed!!!\n", ioc->name));
5270 r = -ENOMEM;
5271 goto out_free_resources;
5272 }
5273 }
5274
9b05c91a
SR		 5275 ioc->rdpq_array_enable_assigned = 0;
5276 ioc->dma_mask = 0;
f92363d1
SR		 5277 r = mpt3sas_base_map_resources(ioc);
5278 if (r)
5279 goto out_free_resources;
5280
7786ab6a
SR		 5281 if (ioc->is_warpdrive) {
5282 ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
5283 &ioc->chip->ReplyPostHostIndex;
5284
5285 for (i = 1; i < ioc->cpu_msix_table_sz; i++)
5286 ioc->reply_post_host_index[i] =
5287 (resource_size_t __iomem *)
5288 ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
5289 * 4)));
5290 }
f92363d1
SR		 5291
5292 pci_set_drvdata(ioc->pdev, ioc->shost);
5293 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
5294 if (r)
5295 goto out_free_resources;
5296
471ef9d4
SR		 5297 switch (ioc->hba_mpi_version_belonged) {
5298 case MPI2_VERSION:
5299 ioc->build_sg_scmd = &_base_build_sg_scmd;
5300 ioc->build_sg = &_base_build_sg;
5301 ioc->build_zero_len_sge = &_base_build_zero_len_sge;
5302 break;
5303 case MPI25_VERSION:
b130b0d5 5304 case MPI26_VERSION:
471ef9d4
SR		 5305 /*
5306 * In SAS3.0,
5307 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
5308 * Target Status - all require the IEEE formated scatter gather
5309 * elements.
5310 */
5311 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
5312 ioc->build_sg = &_base_build_sg_ieee;
5313 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
5314 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
5315 break;
5316 }
f92363d1
SR		 5317
5318 /*
5319 * These function pointers for other requests that don't
5320 * the require IEEE scatter gather elements.
5321 *
5322 * For example Configuration Pages and SAS IOUNIT Control don't.
5323 */
5324 ioc->build_sg_mpi = &_base_build_sg;
5325 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
5326
5327 r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
5328 if (r)
5329 goto out_free_resources;
5330
5331 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
5332 sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
5333 if (!ioc->pfacts) {
5334 r = -ENOMEM;
5335 goto out_free_resources;
5336 }
5337
5338 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
5339 r = _base_get_port_facts(ioc, i, CAN_SLEEP);
5340 if (r)
5341 goto out_free_resources;
5342 }
5343
5344 r = _base_allocate_memory_pools(ioc, CAN_SLEEP);
5345 if (r)
5346 goto out_free_resources;
5347
5348 init_waitqueue_head(&ioc->reset_wq);
5349
5350 /* allocate memory pd handle bitmask list */
5351 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
5352 if (ioc->facts.MaxDevHandle % 8)
5353 ioc->pd_handles_sz++;
5354 ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
5355 GFP_KERNEL);
5356 if (!ioc->pd_handles) {
5357 r = -ENOMEM;
5358 goto out_free_resources;
5359 }
5360 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
5361 GFP_KERNEL);
5362 if (!ioc->blocking_handles) {
5363 r = -ENOMEM;
5364 goto out_free_resources;
5365 }
5366
5367 ioc->fwfault_debug = mpt3sas_fwfault_debug;
5368
5369 /* base internal command bits */
5370 mutex_init(&ioc->base_cmds.mutex);
5371 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5372 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
5373
5374 /* port_enable command bits */
5375 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5376 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
5377
5378 /* transport internal command bits */
5379 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5380 ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
5381 mutex_init(&ioc->transport_cmds.mutex);
5382
5383 /* scsih internal command bits */
5384 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5385 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
5386 mutex_init(&ioc->scsih_cmds.mutex);
5387
5388 /* task management internal command bits */
5389 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5390 ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
5391 mutex_init(&ioc->tm_cmds.mutex);
5392
5393 /* config page internal command bits */
5394 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5395 ioc->config_cmds.status = MPT3_CMD_NOT_USED;
5396 mutex_init(&ioc->config_cmds.mutex);
5397
5398 /* ctl module internal command bits */
5399 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
5400 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
5401 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
5402 mutex_init(&ioc->ctl_cmds.mutex);
5403
5404 if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
5405 !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
5406 !ioc->config_cmds.reply || !ioc->ctl_cmds.reply ||
5407 !ioc->ctl_cmds.sense) {
5408 r = -ENOMEM;
5409 goto out_free_resources;
5410 }
5411
5412 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
5413 ioc->event_masks[i] = -1;
5414
5415 /* here we enable the events we care about */
5416 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
5417 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
5418 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
5419 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
5420 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
5421 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
5422 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
5423 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
5424 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
5425 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
2d8ce8c9 5426 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
f92363d1
SR		 5427
5428 r = _base_make_ioc_operational(ioc, CAN_SLEEP);
5429 if (r)
5430 goto out_free_resources;
5431
16e179bd 5432 ioc->non_operational_loop = 0;
f92363d1
SR		 5433 return 0;
5434
5435 out_free_resources:
5436
5437 ioc->remove_host = 1;
5438
5439 mpt3sas_base_free_resources(ioc);
5440 _base_release_memory_pools(ioc);
5441 pci_set_drvdata(ioc->pdev, NULL);
5442 kfree(ioc->cpu_msix_table);
7786ab6a
SR		 5443 if (ioc->is_warpdrive)
5444 kfree(ioc->reply_post_host_index);
f92363d1
SR		 5445 kfree(ioc->pd_handles);
5446 kfree(ioc->blocking_handles);
5447 kfree(ioc->tm_cmds.reply);
5448 kfree(ioc->transport_cmds.reply);
5449 kfree(ioc->scsih_cmds.reply);
5450 kfree(ioc->config_cmds.reply);
5451 kfree(ioc->base_cmds.reply);
5452 kfree(ioc->port_enable_cmds.reply);
5453 kfree(ioc->ctl_cmds.reply);
5454 kfree(ioc->ctl_cmds.sense);
5455 kfree(ioc->pfacts);
5456 ioc->ctl_cmds.reply = NULL;
5457 ioc->base_cmds.reply = NULL;
5458 ioc->tm_cmds.reply = NULL;
5459 ioc->scsih_cmds.reply = NULL;
5460 ioc->transport_cmds.reply = NULL;
5461 ioc->config_cmds.reply = NULL;
5462 ioc->pfacts = NULL;
5463 return r;
5464}
5465
5466
5467/**
5468 * mpt3sas_base_detach - remove controller instance
5469 * @ioc: per adapter object
5470 *
5471 * Return nothing.
5472 */
5473void
5474mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
5475{
5476 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5477 __func__));
5478
5479 mpt3sas_base_stop_watchdog(ioc);
5480 mpt3sas_base_free_resources(ioc);
5481 _base_release_memory_pools(ioc);
5482 pci_set_drvdata(ioc->pdev, NULL);
5483 kfree(ioc->cpu_msix_table);
7786ab6a
SR		 5484 if (ioc->is_warpdrive)
5485 kfree(ioc->reply_post_host_index);
f92363d1
SR		 5486 kfree(ioc->pd_handles);
5487 kfree(ioc->blocking_handles);
5488 kfree(ioc->pfacts);
5489 kfree(ioc->ctl_cmds.reply);
5490 kfree(ioc->ctl_cmds.sense);
5491 kfree(ioc->base_cmds.reply);
5492 kfree(ioc->port_enable_cmds.reply);
5493 kfree(ioc->tm_cmds.reply);
5494 kfree(ioc->transport_cmds.reply);
5495 kfree(ioc->scsih_cmds.reply);
5496 kfree(ioc->config_cmds.reply);
5497}
5498
5499/**
5500 * _base_reset_handler - reset callback handler (for base)
5501 * @ioc: per adapter object
5502 * @reset_phase: phase
5503 *
5504 * The handler for doing any required cleanup or initialization.
5505 *
5506 * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET,
5507 * MPT3_IOC_DONE_RESET
5508 *
5509 * Return nothing.
5510 */
5511static void
5512_base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase)
5513{
5514 mpt3sas_scsih_reset_handler(ioc, reset_phase);
5515 mpt3sas_ctl_reset_handler(ioc, reset_phase);
5516 switch (reset_phase) {
5517 case MPT3_IOC_PRE_RESET:
5518 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5519 "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
5520 break;
5521 case MPT3_IOC_AFTER_RESET:
5522 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5523 "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
5524 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
5525 ioc->transport_cmds.status |= MPT3_CMD_RESET;
5526 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
5527 complete(&ioc->transport_cmds.done);
5528 }
5529 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
5530 ioc->base_cmds.status |= MPT3_CMD_RESET;
5531 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
5532 complete(&ioc->base_cmds.done);
5533 }
5534 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5535 ioc->port_enable_failed = 1;
5536 ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
5537 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
5538 if (ioc->is_driver_loading) {
5539 ioc->start_scan_failed =
5540 MPI2_IOCSTATUS_INTERNAL_ERROR;
5541 ioc->start_scan = 0;
5542 ioc->port_enable_cmds.status =
5543 MPT3_CMD_NOT_USED;
5544 } else
5545 complete(&ioc->port_enable_cmds.done);
5546 }
5547 if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
5548 ioc->config_cmds.status |= MPT3_CMD_RESET;
5549 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
5550 ioc->config_cmds.smid = USHRT_MAX;
5551 complete(&ioc->config_cmds.done);
5552 }
5553 break;
5554 case MPT3_IOC_DONE_RESET:
5555 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5556 "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
5557 break;
5558 }
5559}
5560
5561/**
5562 * _wait_for_commands_to_complete - reset controller
5563 * @ioc: Pointer to MPT_ADAPTER structure
5564 * @sleep_flag: CAN_SLEEP or NO_SLEEP
5565 *
5566 * This function waiting(3s) for all pending commands to complete
5567 * prior to putting controller in reset.
5568 */
5569static void
5570_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
5571{
5572 u32 ioc_state;
5573 unsigned long flags;
5574 u16 i;
5575
5576 ioc->pending_io_count = 0;
5577 if (sleep_flag != CAN_SLEEP)
5578 return;
5579
5580 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5581 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
5582 return;
5583
5584 /* pending command count */
5585 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5586 for (i = 0; i < ioc->scsiio_depth; i++)
5587 if (ioc->scsi_lookup[i].cb_idx != 0xFF)
5588 ioc->pending_io_count++;
5589 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5590
5591 if (!ioc->pending_io_count)
5592 return;
5593
5594 /* wait for pending commands to complete */
5595 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
5596}
5597
5598/**
5599 * mpt3sas_base_hard_reset_handler - reset controller
5600 * @ioc: Pointer to MPT_ADAPTER structure
5601 * @sleep_flag: CAN_SLEEP or NO_SLEEP
5602 * @type: FORCE_BIG_HAMMER or SOFT_RESET
5603 *
5604 * Returns 0 for success, non-zero for failure.
5605 */
5606int
5607mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
5608 enum reset_type type)
5609{
5610 int r;
5611 unsigned long flags;
5612 u32 ioc_state;
5613 u8 is_fault = 0, is_trigger = 0;
5614
5615 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
5616 __func__));
5617
5618 if (ioc->pci_error_recovery) {
5619 pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
5620 ioc->name, __func__);
5621 r = 0;
5622 goto out_unlocked;
5623 }
5624
5625 if (mpt3sas_fwfault_debug)
5626 mpt3sas_halt_firmware(ioc);
5627
5628 /* TODO - What we really should be doing is pulling
5629 * out all the code associated with NO_SLEEP; its never used.
5630 * That is legacy code from mpt fusion driver, ported over.
5631 * I will leave this BUG_ON here for now till its been resolved.
5632 */
5633 BUG_ON(sleep_flag == NO_SLEEP);
5634
5635 /* wait for an active reset in progress to complete */
5636 if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
5637 do {
5638 ssleep(1);
5639 } while (ioc->shost_recovery == 1);
5640 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5641 __func__));
5642 return ioc->ioc_reset_in_progress_status;
5643 }
5644
5645 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5646 ioc->shost_recovery = 1;
5647 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5648
5649 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5650 MPT3_DIAG_BUFFER_IS_REGISTERED) &&
5651 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5652 MPT3_DIAG_BUFFER_IS_RELEASED))) {
5653 is_trigger = 1;
5654 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5655 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
5656 is_fault = 1;
5657 }
5658 _base_reset_handler(ioc, MPT3_IOC_PRE_RESET);
5659 _wait_for_commands_to_complete(ioc, sleep_flag);
5660 _base_mask_interrupts(ioc);
5661 r = _base_make_ioc_ready(ioc, sleep_flag, type);
5662 if (r)
5663 goto out;
5664 _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET);
5665
5666 /* If this hard reset is called while port enable is active, then
5667 * there is no reason to call make_ioc_operational
5668 */
5669 if (ioc->is_driver_loading && ioc->port_enable_failed) {
5670 ioc->remove_host = 1;
5671 r = -EFAULT;
5672 goto out;
5673 }
5674 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
5675 if (r)
5676 goto out;
9b05c91a
SR		 5677
5678 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
5679 panic("%s: Issue occurred with flashing controller firmware."
5680 "Please reboot the system and ensure that the correct"
5681 " firmware version is running\n", ioc->name);
5682
f92363d1
SR		 5683 r = _base_make_ioc_operational(ioc, sleep_flag);
5684 if (!r)
5685 _base_reset_handler(ioc, MPT3_IOC_DONE_RESET);
5686
5687 out:
5688 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
5689 ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
5690
5691 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5692 ioc->ioc_reset_in_progress_status = r;
5693 ioc->shost_recovery = 0;
5694 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5695 ioc->ioc_reset_count++;
5696 mutex_unlock(&ioc->reset_in_progress_mutex);
5697
5698 out_unlocked:
5699 if ((r == 0) && is_trigger) {
5700 if (is_fault)
5701 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
5702 else
5703 mpt3sas_trigger_master(ioc,
5704 MASTER_TRIGGER_ADAPTER_RESET);
5705 }
5706 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5707 __func__));
5708 return r;
5709}
Linux 6.x block layer and io_uring tree(s)