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f92363d1 SR |
1 | /* |
2 | * This is the Fusion MPT base driver providing common API layer interface | |
3 | * for access to MPT (Message Passing Technology) firmware. | |
4 | * | |
5 | * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c | |
a4ffce0d | 6 | * Copyright (C) 2012-2014 LSI Corporation |
a03bd153 SR |
7 | * Copyright (C) 2013-2014 Avago Technologies |
8 | * (mailto: MPT-FusionLinux.pdl@avagotech.com) | |
f92363d1 SR |
9 | * |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version 2 | |
13 | * of the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * NO WARRANTY | |
21 | * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR | |
22 | * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT | |
23 | * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, | |
24 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is | |
25 | * solely responsible for determining the appropriateness of using and | |
26 | * distributing the Program and assumes all risks associated with its | |
27 | * exercise of rights under this Agreement, including but not limited to | |
28 | * the risks and costs of program errors, damage to or loss of data, | |
29 | * programs or equipment, and unavailability or interruption of operations. | |
30 | ||
31 | * DISCLAIMER OF LIABILITY | |
32 | * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY | |
33 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
34 | * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND | |
35 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR | |
36 | * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE | |
37 | * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED | |
38 | * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES | |
39 | ||
40 | * You should have received a copy of the GNU General Public License | |
41 | * along with this program; if not, write to the Free Software | |
42 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, | |
43 | * USA. | |
44 | */ | |
45 | ||
f92363d1 SR |
46 | #include <linux/kernel.h> |
47 | #include <linux/module.h> | |
48 | #include <linux/errno.h> | |
49 | #include <linux/init.h> | |
50 | #include <linux/slab.h> | |
51 | #include <linux/types.h> | |
52 | #include <linux/pci.h> | |
53 | #include <linux/kdev_t.h> | |
54 | #include <linux/blkdev.h> | |
55 | #include <linux/delay.h> | |
56 | #include <linux/interrupt.h> | |
57 | #include <linux/dma-mapping.h> | |
58 | #include <linux/io.h> | |
59 | #include <linux/time.h> | |
23409bd4 | 60 | #include <linux/ktime.h> |
f92363d1 | 61 | #include <linux/kthread.h> |
016d5c35 | 62 | #include <asm/page.h> /* To get host page size per arch */ |
f92363d1 SR |
63 | #include <linux/aer.h> |
64 | ||
65 | ||
66 | #include "mpt3sas_base.h" | |
67 | ||
68 | static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS]; | |
69 | ||
70 | ||
71 | #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */ | |
72 | ||
73 | /* maximum controller queue depth */ | |
74 | #define MAX_HBA_QUEUE_DEPTH 30000 | |
75 | #define MAX_CHAIN_DEPTH 100000 | |
76 | static int max_queue_depth = -1; | |
77 | module_param(max_queue_depth, int, 0); | |
78 | MODULE_PARM_DESC(max_queue_depth, " max controller queue depth "); | |
79 | ||
80 | static int max_sgl_entries = -1; | |
81 | module_param(max_sgl_entries, int, 0); | |
82 | MODULE_PARM_DESC(max_sgl_entries, " max sg entries "); | |
83 | ||
84 | static int msix_disable = -1; | |
85 | module_param(msix_disable, int, 0); | |
86 | MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)"); | |
87 | ||
64038301 SPS |
88 | static int smp_affinity_enable = 1; |
89 | module_param(smp_affinity_enable, int, S_IRUGO); | |
90 | MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disbale Default: enable(1)"); | |
91 | ||
fb77bb53 | 92 | static int max_msix_vectors = -1; |
9c500060 SR |
93 | module_param(max_msix_vectors, int, 0); |
94 | MODULE_PARM_DESC(max_msix_vectors, | |
fb77bb53 | 95 | " max msix vectors"); |
f92363d1 SR |
96 | |
97 | static int mpt3sas_fwfault_debug; | |
98 | MODULE_PARM_DESC(mpt3sas_fwfault_debug, | |
99 | " enable detection of firmware fault and halt firmware - (default=0)"); | |
100 | ||
9b05c91a | 101 | static int |
98c56ad3 | 102 | _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc); |
f92363d1 SR |
103 | |
104 | /** | |
105 | * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug. | |
106 | * | |
107 | */ | |
108 | static int | |
109 | _scsih_set_fwfault_debug(const char *val, struct kernel_param *kp) | |
110 | { | |
111 | int ret = param_set_int(val, kp); | |
112 | struct MPT3SAS_ADAPTER *ioc; | |
113 | ||
114 | if (ret) | |
115 | return ret; | |
116 | ||
08c4d550 | 117 | /* global ioc spinlock to protect controller list on list operations */ |
f92363d1 | 118 | pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug); |
08c4d550 | 119 | spin_lock(&gioc_lock); |
f92363d1 SR |
120 | list_for_each_entry(ioc, &mpt3sas_ioc_list, list) |
121 | ioc->fwfault_debug = mpt3sas_fwfault_debug; | |
08c4d550 | 122 | spin_unlock(&gioc_lock); |
f92363d1 SR |
123 | return 0; |
124 | } | |
125 | module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug, | |
126 | param_get_int, &mpt3sas_fwfault_debug, 0644); | |
127 | ||
128 | /** | |
129 | * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc | |
130 | * @arg: input argument, used to derive ioc | |
131 | * | |
132 | * Return 0 if controller is removed from pci subsystem. | |
133 | * Return -1 for other case. | |
134 | */ | |
135 | static int mpt3sas_remove_dead_ioc_func(void *arg) | |
136 | { | |
137 | struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg; | |
138 | struct pci_dev *pdev; | |
139 | ||
140 | if ((ioc == NULL)) | |
141 | return -1; | |
142 | ||
143 | pdev = ioc->pdev; | |
144 | if ((pdev == NULL)) | |
145 | return -1; | |
64cdb418 | 146 | pci_stop_and_remove_bus_device_locked(pdev); |
f92363d1 SR |
147 | return 0; |
148 | } | |
149 | ||
150 | /** | |
151 | * _base_fault_reset_work - workq handling ioc fault conditions | |
152 | * @work: input argument, used to derive ioc | |
153 | * Context: sleep. | |
154 | * | |
155 | * Return nothing. | |
156 | */ | |
157 | static void | |
158 | _base_fault_reset_work(struct work_struct *work) | |
159 | { | |
160 | struct MPT3SAS_ADAPTER *ioc = | |
161 | container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work); | |
162 | unsigned long flags; | |
163 | u32 doorbell; | |
164 | int rc; | |
165 | struct task_struct *p; | |
166 | ||
167 | ||
168 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
16e179bd | 169 | if (ioc->shost_recovery || ioc->pci_error_recovery) |
f92363d1 SR |
170 | goto rearm_timer; |
171 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
172 | ||
173 | doorbell = mpt3sas_base_get_iocstate(ioc, 0); | |
174 | if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) { | |
175 | pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n", | |
176 | ioc->name); | |
177 | ||
16e179bd SR |
178 | /* It may be possible that EEH recovery can resolve some of |
179 | * pci bus failure issues rather removing the dead ioc function | |
180 | * by considering controller is in a non-operational state. So | |
181 | * here priority is given to the EEH recovery. If it doesn't | |
182 | * not resolve this issue, mpt3sas driver will consider this | |
183 | * controller to non-operational state and remove the dead ioc | |
184 | * function. | |
185 | */ | |
186 | if (ioc->non_operational_loop++ < 5) { | |
187 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, | |
188 | flags); | |
189 | goto rearm_timer; | |
190 | } | |
191 | ||
f92363d1 SR |
192 | /* |
193 | * Call _scsih_flush_pending_cmds callback so that we flush all | |
194 | * pending commands back to OS. This call is required to aovid | |
195 | * deadlock at block layer. Dead IOC will fail to do diag reset, | |
196 | * and this call is safe since dead ioc will never return any | |
197 | * command back from HW. | |
198 | */ | |
199 | ioc->schedule_dead_ioc_flush_running_cmds(ioc); | |
200 | /* | |
201 | * Set remove_host flag early since kernel thread will | |
202 | * take some time to execute. | |
203 | */ | |
204 | ioc->remove_host = 1; | |
205 | /*Remove the Dead Host */ | |
206 | p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc, | |
c84b06a4 | 207 | "%s_dead_ioc_%d", ioc->driver_name, ioc->id); |
f92363d1 SR |
208 | if (IS_ERR(p)) |
209 | pr_err(MPT3SAS_FMT | |
210 | "%s: Running mpt3sas_dead_ioc thread failed !!!!\n", | |
211 | ioc->name, __func__); | |
212 | else | |
213 | pr_err(MPT3SAS_FMT | |
214 | "%s: Running mpt3sas_dead_ioc thread success !!!!\n", | |
215 | ioc->name, __func__); | |
216 | return; /* don't rearm timer */ | |
217 | } | |
218 | ||
16e179bd SR |
219 | ioc->non_operational_loop = 0; |
220 | ||
f92363d1 | 221 | if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) { |
98c56ad3 | 222 | rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); |
f92363d1 SR |
223 | pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name, |
224 | __func__, (rc == 0) ? "success" : "failed"); | |
225 | doorbell = mpt3sas_base_get_iocstate(ioc, 0); | |
226 | if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) | |
227 | mpt3sas_base_fault_info(ioc, doorbell & | |
228 | MPI2_DOORBELL_DATA_MASK); | |
229 | if (rc && (doorbell & MPI2_IOC_STATE_MASK) != | |
230 | MPI2_IOC_STATE_OPERATIONAL) | |
231 | return; /* don't rearm timer */ | |
232 | } | |
233 | ||
234 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
235 | rearm_timer: | |
236 | if (ioc->fault_reset_work_q) | |
237 | queue_delayed_work(ioc->fault_reset_work_q, | |
238 | &ioc->fault_reset_work, | |
239 | msecs_to_jiffies(FAULT_POLLING_INTERVAL)); | |
240 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
241 | } | |
242 | ||
243 | /** | |
244 | * mpt3sas_base_start_watchdog - start the fault_reset_work_q | |
245 | * @ioc: per adapter object | |
246 | * Context: sleep. | |
247 | * | |
248 | * Return nothing. | |
249 | */ | |
250 | void | |
251 | mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc) | |
252 | { | |
253 | unsigned long flags; | |
254 | ||
255 | if (ioc->fault_reset_work_q) | |
256 | return; | |
257 | ||
258 | /* initialize fault polling */ | |
259 | ||
260 | INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work); | |
261 | snprintf(ioc->fault_reset_work_q_name, | |
c84b06a4 SR |
262 | sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status", |
263 | ioc->driver_name, ioc->id); | |
f92363d1 SR |
264 | ioc->fault_reset_work_q = |
265 | create_singlethread_workqueue(ioc->fault_reset_work_q_name); | |
266 | if (!ioc->fault_reset_work_q) { | |
267 | pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n", | |
268 | ioc->name, __func__, __LINE__); | |
269 | return; | |
270 | } | |
271 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
272 | if (ioc->fault_reset_work_q) | |
273 | queue_delayed_work(ioc->fault_reset_work_q, | |
274 | &ioc->fault_reset_work, | |
275 | msecs_to_jiffies(FAULT_POLLING_INTERVAL)); | |
276 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
277 | } | |
278 | ||
279 | /** | |
280 | * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q | |
281 | * @ioc: per adapter object | |
282 | * Context: sleep. | |
283 | * | |
284 | * Return nothing. | |
285 | */ | |
286 | void | |
287 | mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc) | |
288 | { | |
289 | unsigned long flags; | |
290 | struct workqueue_struct *wq; | |
291 | ||
292 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
293 | wq = ioc->fault_reset_work_q; | |
294 | ioc->fault_reset_work_q = NULL; | |
295 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
296 | if (wq) { | |
4dc06fd8 | 297 | if (!cancel_delayed_work_sync(&ioc->fault_reset_work)) |
f92363d1 SR |
298 | flush_workqueue(wq); |
299 | destroy_workqueue(wq); | |
300 | } | |
301 | } | |
302 | ||
303 | /** | |
304 | * mpt3sas_base_fault_info - verbose translation of firmware FAULT code | |
305 | * @ioc: per adapter object | |
306 | * @fault_code: fault code | |
307 | * | |
308 | * Return nothing. | |
309 | */ | |
310 | void | |
311 | mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code) | |
312 | { | |
313 | pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n", | |
314 | ioc->name, fault_code); | |
315 | } | |
316 | ||
317 | /** | |
318 | * mpt3sas_halt_firmware - halt's mpt controller firmware | |
319 | * @ioc: per adapter object | |
320 | * | |
321 | * For debugging timeout related issues. Writing 0xCOFFEE00 | |
322 | * to the doorbell register will halt controller firmware. With | |
323 | * the purpose to stop both driver and firmware, the enduser can | |
324 | * obtain a ring buffer from controller UART. | |
325 | */ | |
326 | void | |
327 | mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc) | |
328 | { | |
329 | u32 doorbell; | |
330 | ||
331 | if (!ioc->fwfault_debug) | |
332 | return; | |
333 | ||
334 | dump_stack(); | |
335 | ||
336 | doorbell = readl(&ioc->chip->Doorbell); | |
337 | if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) | |
338 | mpt3sas_base_fault_info(ioc , doorbell); | |
339 | else { | |
340 | writel(0xC0FFEE00, &ioc->chip->Doorbell); | |
341 | pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n", | |
342 | ioc->name); | |
343 | } | |
344 | ||
345 | if (ioc->fwfault_debug == 2) | |
346 | for (;;) | |
347 | ; | |
348 | else | |
349 | panic("panic in %s\n", __func__); | |
350 | } | |
351 | ||
f92363d1 SR |
352 | /** |
353 | * _base_sas_ioc_info - verbose translation of the ioc status | |
354 | * @ioc: per adapter object | |
355 | * @mpi_reply: reply mf payload returned from firmware | |
356 | * @request_hdr: request mf | |
357 | * | |
358 | * Return nothing. | |
359 | */ | |
360 | static void | |
361 | _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply, | |
362 | MPI2RequestHeader_t *request_hdr) | |
363 | { | |
364 | u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & | |
365 | MPI2_IOCSTATUS_MASK; | |
366 | char *desc = NULL; | |
367 | u16 frame_sz; | |
368 | char *func_str = NULL; | |
369 | ||
370 | /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */ | |
371 | if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST || | |
372 | request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH || | |
373 | request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION) | |
374 | return; | |
375 | ||
376 | if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE) | |
377 | return; | |
378 | ||
379 | switch (ioc_status) { | |
380 | ||
381 | /**************************************************************************** | |
382 | * Common IOCStatus values for all replies | |
383 | ****************************************************************************/ | |
384 | ||
385 | case MPI2_IOCSTATUS_INVALID_FUNCTION: | |
386 | desc = "invalid function"; | |
387 | break; | |
388 | case MPI2_IOCSTATUS_BUSY: | |
389 | desc = "busy"; | |
390 | break; | |
391 | case MPI2_IOCSTATUS_INVALID_SGL: | |
392 | desc = "invalid sgl"; | |
393 | break; | |
394 | case MPI2_IOCSTATUS_INTERNAL_ERROR: | |
395 | desc = "internal error"; | |
396 | break; | |
397 | case MPI2_IOCSTATUS_INVALID_VPID: | |
398 | desc = "invalid vpid"; | |
399 | break; | |
400 | case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: | |
401 | desc = "insufficient resources"; | |
402 | break; | |
b130b0d5 SS |
403 | case MPI2_IOCSTATUS_INSUFFICIENT_POWER: |
404 | desc = "insufficient power"; | |
405 | break; | |
f92363d1 SR |
406 | case MPI2_IOCSTATUS_INVALID_FIELD: |
407 | desc = "invalid field"; | |
408 | break; | |
409 | case MPI2_IOCSTATUS_INVALID_STATE: | |
410 | desc = "invalid state"; | |
411 | break; | |
412 | case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED: | |
413 | desc = "op state not supported"; | |
414 | break; | |
415 | ||
416 | /**************************************************************************** | |
417 | * Config IOCStatus values | |
418 | ****************************************************************************/ | |
419 | ||
420 | case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION: | |
421 | desc = "config invalid action"; | |
422 | break; | |
423 | case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE: | |
424 | desc = "config invalid type"; | |
425 | break; | |
426 | case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE: | |
427 | desc = "config invalid page"; | |
428 | break; | |
429 | case MPI2_IOCSTATUS_CONFIG_INVALID_DATA: | |
430 | desc = "config invalid data"; | |
431 | break; | |
432 | case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS: | |
433 | desc = "config no defaults"; | |
434 | break; | |
435 | case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT: | |
436 | desc = "config cant commit"; | |
437 | break; | |
438 | ||
439 | /**************************************************************************** | |
440 | * SCSI IO Reply | |
441 | ****************************************************************************/ | |
442 | ||
443 | case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR: | |
444 | case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE: | |
445 | case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: | |
446 | case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: | |
447 | case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: | |
448 | case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: | |
449 | case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: | |
450 | case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: | |
451 | case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: | |
452 | case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED: | |
453 | case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: | |
454 | case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: | |
455 | break; | |
456 | ||
457 | /**************************************************************************** | |
458 | * For use by SCSI Initiator and SCSI Target end-to-end data protection | |
459 | ****************************************************************************/ | |
460 | ||
461 | case MPI2_IOCSTATUS_EEDP_GUARD_ERROR: | |
462 | desc = "eedp guard error"; | |
463 | break; | |
464 | case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR: | |
465 | desc = "eedp ref tag error"; | |
466 | break; | |
467 | case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR: | |
468 | desc = "eedp app tag error"; | |
469 | break; | |
470 | ||
471 | /**************************************************************************** | |
472 | * SCSI Target values | |
473 | ****************************************************************************/ | |
474 | ||
475 | case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX: | |
476 | desc = "target invalid io index"; | |
477 | break; | |
478 | case MPI2_IOCSTATUS_TARGET_ABORTED: | |
479 | desc = "target aborted"; | |
480 | break; | |
481 | case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: | |
482 | desc = "target no conn retryable"; | |
483 | break; | |
484 | case MPI2_IOCSTATUS_TARGET_NO_CONNECTION: | |
485 | desc = "target no connection"; | |
486 | break; | |
487 | case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: | |
488 | desc = "target xfer count mismatch"; | |
489 | break; | |
490 | case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: | |
491 | desc = "target data offset error"; | |
492 | break; | |
493 | case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: | |
494 | desc = "target too much write data"; | |
495 | break; | |
496 | case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT: | |
497 | desc = "target iu too short"; | |
498 | break; | |
499 | case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: | |
500 | desc = "target ack nak timeout"; | |
501 | break; | |
502 | case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED: | |
503 | desc = "target nak received"; | |
504 | break; | |
505 | ||
506 | /**************************************************************************** | |
507 | * Serial Attached SCSI values | |
508 | ****************************************************************************/ | |
509 | ||
510 | case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: | |
511 | desc = "smp request failed"; | |
512 | break; | |
513 | case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: | |
514 | desc = "smp data overrun"; | |
515 | break; | |
516 | ||
517 | /**************************************************************************** | |
518 | * Diagnostic Buffer Post / Diagnostic Release values | |
519 | ****************************************************************************/ | |
520 | ||
521 | case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED: | |
522 | desc = "diagnostic released"; | |
523 | break; | |
524 | default: | |
525 | break; | |
526 | } | |
527 | ||
528 | if (!desc) | |
529 | return; | |
530 | ||
531 | switch (request_hdr->Function) { | |
532 | case MPI2_FUNCTION_CONFIG: | |
533 | frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size; | |
534 | func_str = "config_page"; | |
535 | break; | |
536 | case MPI2_FUNCTION_SCSI_TASK_MGMT: | |
537 | frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t); | |
538 | func_str = "task_mgmt"; | |
539 | break; | |
540 | case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL: | |
541 | frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t); | |
542 | func_str = "sas_iounit_ctl"; | |
543 | break; | |
544 | case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR: | |
545 | frame_sz = sizeof(Mpi2SepRequest_t); | |
546 | func_str = "enclosure"; | |
547 | break; | |
548 | case MPI2_FUNCTION_IOC_INIT: | |
549 | frame_sz = sizeof(Mpi2IOCInitRequest_t); | |
550 | func_str = "ioc_init"; | |
551 | break; | |
552 | case MPI2_FUNCTION_PORT_ENABLE: | |
553 | frame_sz = sizeof(Mpi2PortEnableRequest_t); | |
554 | func_str = "port_enable"; | |
555 | break; | |
556 | case MPI2_FUNCTION_SMP_PASSTHROUGH: | |
557 | frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size; | |
558 | func_str = "smp_passthru"; | |
559 | break; | |
560 | default: | |
561 | frame_sz = 32; | |
562 | func_str = "unknown"; | |
563 | break; | |
564 | } | |
565 | ||
566 | pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n", | |
567 | ioc->name, desc, ioc_status, request_hdr, func_str); | |
568 | ||
569 | _debug_dump_mf(request_hdr, frame_sz/4); | |
570 | } | |
571 | ||
572 | /** | |
573 | * _base_display_event_data - verbose translation of firmware asyn events | |
574 | * @ioc: per adapter object | |
575 | * @mpi_reply: reply mf payload returned from firmware | |
576 | * | |
577 | * Return nothing. | |
578 | */ | |
579 | static void | |
580 | _base_display_event_data(struct MPT3SAS_ADAPTER *ioc, | |
581 | Mpi2EventNotificationReply_t *mpi_reply) | |
582 | { | |
583 | char *desc = NULL; | |
584 | u16 event; | |
585 | ||
586 | if (!(ioc->logging_level & MPT_DEBUG_EVENTS)) | |
587 | return; | |
588 | ||
589 | event = le16_to_cpu(mpi_reply->Event); | |
590 | ||
591 | switch (event) { | |
592 | case MPI2_EVENT_LOG_DATA: | |
593 | desc = "Log Data"; | |
594 | break; | |
595 | case MPI2_EVENT_STATE_CHANGE: | |
596 | desc = "Status Change"; | |
597 | break; | |
598 | case MPI2_EVENT_HARD_RESET_RECEIVED: | |
599 | desc = "Hard Reset Received"; | |
600 | break; | |
601 | case MPI2_EVENT_EVENT_CHANGE: | |
602 | desc = "Event Change"; | |
603 | break; | |
604 | case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: | |
605 | desc = "Device Status Change"; | |
606 | break; | |
607 | case MPI2_EVENT_IR_OPERATION_STATUS: | |
7786ab6a SR |
608 | if (!ioc->hide_ir_msg) |
609 | desc = "IR Operation Status"; | |
f92363d1 SR |
610 | break; |
611 | case MPI2_EVENT_SAS_DISCOVERY: | |
612 | { | |
613 | Mpi2EventDataSasDiscovery_t *event_data = | |
614 | (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData; | |
615 | pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name, | |
616 | (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ? | |
617 | "start" : "stop"); | |
618 | if (event_data->DiscoveryStatus) | |
bbaf61e2 | 619 | pr_cont(" discovery_status(0x%08x)", |
f92363d1 | 620 | le32_to_cpu(event_data->DiscoveryStatus)); |
bbaf61e2 | 621 | pr_cont("\n"); |
f92363d1 SR |
622 | return; |
623 | } | |
624 | case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: | |
625 | desc = "SAS Broadcast Primitive"; | |
626 | break; | |
627 | case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: | |
628 | desc = "SAS Init Device Status Change"; | |
629 | break; | |
630 | case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW: | |
631 | desc = "SAS Init Table Overflow"; | |
632 | break; | |
633 | case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: | |
634 | desc = "SAS Topology Change List"; | |
635 | break; | |
636 | case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: | |
637 | desc = "SAS Enclosure Device Status Change"; | |
638 | break; | |
639 | case MPI2_EVENT_IR_VOLUME: | |
7786ab6a SR |
640 | if (!ioc->hide_ir_msg) |
641 | desc = "IR Volume"; | |
f92363d1 SR |
642 | break; |
643 | case MPI2_EVENT_IR_PHYSICAL_DISK: | |
7786ab6a SR |
644 | if (!ioc->hide_ir_msg) |
645 | desc = "IR Physical Disk"; | |
f92363d1 SR |
646 | break; |
647 | case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: | |
7786ab6a SR |
648 | if (!ioc->hide_ir_msg) |
649 | desc = "IR Configuration Change List"; | |
f92363d1 SR |
650 | break; |
651 | case MPI2_EVENT_LOG_ENTRY_ADDED: | |
7786ab6a SR |
652 | if (!ioc->hide_ir_msg) |
653 | desc = "Log Entry Added"; | |
f92363d1 | 654 | break; |
2d8ce8c9 SR |
655 | case MPI2_EVENT_TEMP_THRESHOLD: |
656 | desc = "Temperature Threshold"; | |
657 | break; | |
a470a51c | 658 | case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION: |
b99b1993 | 659 | desc = "Cable Event"; |
a470a51c | 660 | break; |
f92363d1 SR |
661 | } |
662 | ||
663 | if (!desc) | |
664 | return; | |
665 | ||
666 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc); | |
667 | } | |
f92363d1 SR |
668 | |
669 | /** | |
670 | * _base_sas_log_info - verbose translation of firmware log info | |
671 | * @ioc: per adapter object | |
672 | * @log_info: log info | |
673 | * | |
674 | * Return nothing. | |
675 | */ | |
676 | static void | |
677 | _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info) | |
678 | { | |
679 | union loginfo_type { | |
680 | u32 loginfo; | |
681 | struct { | |
682 | u32 subcode:16; | |
683 | u32 code:8; | |
684 | u32 originator:4; | |
685 | u32 bus_type:4; | |
686 | } dw; | |
687 | }; | |
688 | union loginfo_type sas_loginfo; | |
689 | char *originator_str = NULL; | |
690 | ||
691 | sas_loginfo.loginfo = log_info; | |
692 | if (sas_loginfo.dw.bus_type != 3 /*SAS*/) | |
693 | return; | |
694 | ||
695 | /* each nexus loss loginfo */ | |
696 | if (log_info == 0x31170000) | |
697 | return; | |
698 | ||
699 | /* eat the loginfos associated with task aborts */ | |
700 | if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info == | |
701 | 0x31140000 || log_info == 0x31130000)) | |
702 | return; | |
703 | ||
704 | switch (sas_loginfo.dw.originator) { | |
705 | case 0: | |
706 | originator_str = "IOP"; | |
707 | break; | |
708 | case 1: | |
709 | originator_str = "PL"; | |
710 | break; | |
711 | case 2: | |
7786ab6a SR |
712 | if (!ioc->hide_ir_msg) |
713 | originator_str = "IR"; | |
714 | else | |
715 | originator_str = "WarpDrive"; | |
f92363d1 SR |
716 | break; |
717 | } | |
718 | ||
719 | pr_warn(MPT3SAS_FMT | |
720 | "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n", | |
721 | ioc->name, log_info, | |
722 | originator_str, sas_loginfo.dw.code, | |
723 | sas_loginfo.dw.subcode); | |
724 | } | |
725 | ||
726 | /** | |
727 | * _base_display_reply_info - | |
728 | * @ioc: per adapter object | |
729 | * @smid: system request message index | |
730 | * @msix_index: MSIX table index supplied by the OS | |
731 | * @reply: reply message frame(lower 32bit addr) | |
732 | * | |
733 | * Return nothing. | |
734 | */ | |
735 | static void | |
736 | _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, | |
737 | u32 reply) | |
738 | { | |
739 | MPI2DefaultReply_t *mpi_reply; | |
740 | u16 ioc_status; | |
741 | u32 loginfo = 0; | |
742 | ||
743 | mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); | |
744 | if (unlikely(!mpi_reply)) { | |
745 | pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n", | |
746 | ioc->name, __FILE__, __LINE__, __func__); | |
747 | return; | |
748 | } | |
749 | ioc_status = le16_to_cpu(mpi_reply->IOCStatus); | |
af009411 | 750 | |
f92363d1 SR |
751 | if ((ioc_status & MPI2_IOCSTATUS_MASK) && |
752 | (ioc->logging_level & MPT_DEBUG_REPLY)) { | |
753 | _base_sas_ioc_info(ioc , mpi_reply, | |
754 | mpt3sas_base_get_msg_frame(ioc, smid)); | |
755 | } | |
af009411 | 756 | |
f92363d1 SR |
757 | if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { |
758 | loginfo = le32_to_cpu(mpi_reply->IOCLogInfo); | |
759 | _base_sas_log_info(ioc, loginfo); | |
760 | } | |
761 | ||
762 | if (ioc_status || loginfo) { | |
763 | ioc_status &= MPI2_IOCSTATUS_MASK; | |
764 | mpt3sas_trigger_mpi(ioc, ioc_status, loginfo); | |
765 | } | |
766 | } | |
767 | ||
768 | /** | |
769 | * mpt3sas_base_done - base internal command completion routine | |
770 | * @ioc: per adapter object | |
771 | * @smid: system request message index | |
772 | * @msix_index: MSIX table index supplied by the OS | |
773 | * @reply: reply message frame(lower 32bit addr) | |
774 | * | |
775 | * Return 1 meaning mf should be freed from _base_interrupt | |
776 | * 0 means the mf is freed from this function. | |
777 | */ | |
778 | u8 | |
779 | mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, | |
780 | u32 reply) | |
781 | { | |
782 | MPI2DefaultReply_t *mpi_reply; | |
783 | ||
784 | mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); | |
785 | if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK) | |
fd0331b3 | 786 | return mpt3sas_check_for_pending_internal_cmds(ioc, smid); |
f92363d1 SR |
787 | |
788 | if (ioc->base_cmds.status == MPT3_CMD_NOT_USED) | |
789 | return 1; | |
790 | ||
791 | ioc->base_cmds.status |= MPT3_CMD_COMPLETE; | |
792 | if (mpi_reply) { | |
793 | ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID; | |
794 | memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); | |
795 | } | |
796 | ioc->base_cmds.status &= ~MPT3_CMD_PENDING; | |
797 | ||
798 | complete(&ioc->base_cmds.done); | |
799 | return 1; | |
800 | } | |
801 | ||
802 | /** | |
803 | * _base_async_event - main callback handler for firmware asyn events | |
804 | * @ioc: per adapter object | |
805 | * @msix_index: MSIX table index supplied by the OS | |
806 | * @reply: reply message frame(lower 32bit addr) | |
807 | * | |
808 | * Return 1 meaning mf should be freed from _base_interrupt | |
809 | * 0 means the mf is freed from this function. | |
810 | */ | |
811 | static u8 | |
812 | _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply) | |
813 | { | |
814 | Mpi2EventNotificationReply_t *mpi_reply; | |
815 | Mpi2EventAckRequest_t *ack_request; | |
816 | u16 smid; | |
fd0331b3 | 817 | struct _event_ack_list *delayed_event_ack; |
f92363d1 SR |
818 | |
819 | mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); | |
820 | if (!mpi_reply) | |
821 | return 1; | |
822 | if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION) | |
823 | return 1; | |
af009411 | 824 | |
f92363d1 | 825 | _base_display_event_data(ioc, mpi_reply); |
af009411 | 826 | |
f92363d1 SR |
827 | if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED)) |
828 | goto out; | |
829 | smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); | |
830 | if (!smid) { | |
fd0331b3 SS |
831 | delayed_event_ack = kzalloc(sizeof(*delayed_event_ack), |
832 | GFP_ATOMIC); | |
833 | if (!delayed_event_ack) | |
834 | goto out; | |
835 | INIT_LIST_HEAD(&delayed_event_ack->list); | |
836 | delayed_event_ack->Event = mpi_reply->Event; | |
837 | delayed_event_ack->EventContext = mpi_reply->EventContext; | |
838 | list_add_tail(&delayed_event_ack->list, | |
839 | &ioc->delayed_event_ack_list); | |
840 | dewtprintk(ioc, pr_info(MPT3SAS_FMT | |
841 | "DELAYED: EVENT ACK: event (0x%04x)\n", | |
842 | ioc->name, le16_to_cpu(mpi_reply->Event))); | |
f92363d1 SR |
843 | goto out; |
844 | } | |
845 | ||
846 | ack_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
847 | memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t)); | |
848 | ack_request->Function = MPI2_FUNCTION_EVENT_ACK; | |
849 | ack_request->Event = mpi_reply->Event; | |
850 | ack_request->EventContext = mpi_reply->EventContext; | |
851 | ack_request->VF_ID = 0; /* TODO */ | |
852 | ack_request->VP_ID = 0; | |
81c16f83 | 853 | ioc->put_smid_default(ioc, smid); |
f92363d1 SR |
854 | |
855 | out: | |
856 | ||
857 | /* scsih callback handler */ | |
858 | mpt3sas_scsih_event_callback(ioc, msix_index, reply); | |
859 | ||
860 | /* ctl callback handler */ | |
861 | mpt3sas_ctl_event_callback(ioc, msix_index, reply); | |
862 | ||
863 | return 1; | |
864 | } | |
865 | ||
866 | /** | |
867 | * _base_get_cb_idx - obtain the callback index | |
868 | * @ioc: per adapter object | |
869 | * @smid: system request message index | |
870 | * | |
871 | * Return callback index. | |
872 | */ | |
873 | static u8 | |
874 | _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
875 | { | |
876 | int i; | |
877 | u8 cb_idx; | |
878 | ||
879 | if (smid < ioc->hi_priority_smid) { | |
880 | i = smid - 1; | |
881 | cb_idx = ioc->scsi_lookup[i].cb_idx; | |
882 | } else if (smid < ioc->internal_smid) { | |
883 | i = smid - ioc->hi_priority_smid; | |
884 | cb_idx = ioc->hpr_lookup[i].cb_idx; | |
885 | } else if (smid <= ioc->hba_queue_depth) { | |
886 | i = smid - ioc->internal_smid; | |
887 | cb_idx = ioc->internal_lookup[i].cb_idx; | |
888 | } else | |
889 | cb_idx = 0xFF; | |
890 | return cb_idx; | |
891 | } | |
892 | ||
893 | /** | |
894 | * _base_mask_interrupts - disable interrupts | |
895 | * @ioc: per adapter object | |
896 | * | |
897 | * Disabling ResetIRQ, Reply and Doorbell Interrupts | |
898 | * | |
899 | * Return nothing. | |
900 | */ | |
901 | static void | |
902 | _base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc) | |
903 | { | |
904 | u32 him_register; | |
905 | ||
906 | ioc->mask_interrupts = 1; | |
907 | him_register = readl(&ioc->chip->HostInterruptMask); | |
908 | him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK; | |
909 | writel(him_register, &ioc->chip->HostInterruptMask); | |
910 | readl(&ioc->chip->HostInterruptMask); | |
911 | } | |
912 | ||
913 | /** | |
914 | * _base_unmask_interrupts - enable interrupts | |
915 | * @ioc: per adapter object | |
916 | * | |
917 | * Enabling only Reply Interrupts | |
918 | * | |
919 | * Return nothing. | |
920 | */ | |
921 | static void | |
922 | _base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc) | |
923 | { | |
924 | u32 him_register; | |
925 | ||
926 | him_register = readl(&ioc->chip->HostInterruptMask); | |
927 | him_register &= ~MPI2_HIM_RIM; | |
928 | writel(him_register, &ioc->chip->HostInterruptMask); | |
929 | ioc->mask_interrupts = 0; | |
930 | } | |
931 | ||
932 | union reply_descriptor { | |
933 | u64 word; | |
934 | struct { | |
935 | u32 low; | |
936 | u32 high; | |
937 | } u; | |
938 | }; | |
939 | ||
940 | /** | |
941 | * _base_interrupt - MPT adapter (IOC) specific interrupt handler. | |
942 | * @irq: irq number (not used) | |
943 | * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure | |
944 | * @r: pt_regs pointer (not used) | |
945 | * | |
946 | * Return IRQ_HANDLE if processed, else IRQ_NONE. | |
947 | */ | |
948 | static irqreturn_t | |
949 | _base_interrupt(int irq, void *bus_id) | |
950 | { | |
951 | struct adapter_reply_queue *reply_q = bus_id; | |
952 | union reply_descriptor rd; | |
953 | u32 completed_cmds; | |
954 | u8 request_desript_type; | |
955 | u16 smid; | |
956 | u8 cb_idx; | |
957 | u32 reply; | |
958 | u8 msix_index = reply_q->msix_index; | |
959 | struct MPT3SAS_ADAPTER *ioc = reply_q->ioc; | |
960 | Mpi2ReplyDescriptorsUnion_t *rpf; | |
961 | u8 rc; | |
962 | ||
963 | if (ioc->mask_interrupts) | |
964 | return IRQ_NONE; | |
965 | ||
966 | if (!atomic_add_unless(&reply_q->busy, 1, 1)) | |
967 | return IRQ_NONE; | |
968 | ||
969 | rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index]; | |
970 | request_desript_type = rpf->Default.ReplyFlags | |
971 | & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; | |
972 | if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) { | |
973 | atomic_dec(&reply_q->busy); | |
974 | return IRQ_NONE; | |
975 | } | |
976 | ||
977 | completed_cmds = 0; | |
978 | cb_idx = 0xFF; | |
979 | do { | |
980 | rd.word = le64_to_cpu(rpf->Words); | |
981 | if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX) | |
982 | goto out; | |
983 | reply = 0; | |
984 | smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1); | |
985 | if (request_desript_type == | |
986 | MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS || | |
987 | request_desript_type == | |
988 | MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) { | |
989 | cb_idx = _base_get_cb_idx(ioc, smid); | |
990 | if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && | |
991 | (likely(mpt_callbacks[cb_idx] != NULL))) { | |
992 | rc = mpt_callbacks[cb_idx](ioc, smid, | |
993 | msix_index, 0); | |
994 | if (rc) | |
995 | mpt3sas_base_free_smid(ioc, smid); | |
996 | } | |
997 | } else if (request_desript_type == | |
998 | MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { | |
999 | reply = le32_to_cpu( | |
1000 | rpf->AddressReply.ReplyFrameAddress); | |
1001 | if (reply > ioc->reply_dma_max_address || | |
1002 | reply < ioc->reply_dma_min_address) | |
1003 | reply = 0; | |
1004 | if (smid) { | |
1005 | cb_idx = _base_get_cb_idx(ioc, smid); | |
1006 | if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && | |
1007 | (likely(mpt_callbacks[cb_idx] != NULL))) { | |
1008 | rc = mpt_callbacks[cb_idx](ioc, smid, | |
1009 | msix_index, reply); | |
1010 | if (reply) | |
1011 | _base_display_reply_info(ioc, | |
1012 | smid, msix_index, reply); | |
1013 | if (rc) | |
1014 | mpt3sas_base_free_smid(ioc, | |
1015 | smid); | |
1016 | } | |
1017 | } else { | |
1018 | _base_async_event(ioc, msix_index, reply); | |
1019 | } | |
1020 | ||
1021 | /* reply free queue handling */ | |
1022 | if (reply) { | |
1023 | ioc->reply_free_host_index = | |
1024 | (ioc->reply_free_host_index == | |
1025 | (ioc->reply_free_queue_depth - 1)) ? | |
1026 | 0 : ioc->reply_free_host_index + 1; | |
1027 | ioc->reply_free[ioc->reply_free_host_index] = | |
1028 | cpu_to_le32(reply); | |
f92363d1 SR |
1029 | writel(ioc->reply_free_host_index, |
1030 | &ioc->chip->ReplyFreeHostIndex); | |
1031 | } | |
1032 | } | |
1033 | ||
1034 | rpf->Words = cpu_to_le64(ULLONG_MAX); | |
1035 | reply_q->reply_post_host_index = | |
1036 | (reply_q->reply_post_host_index == | |
1037 | (ioc->reply_post_queue_depth - 1)) ? 0 : | |
1038 | reply_q->reply_post_host_index + 1; | |
1039 | request_desript_type = | |
1040 | reply_q->reply_post_free[reply_q->reply_post_host_index]. | |
1041 | Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; | |
1042 | completed_cmds++; | |
6b4c335a C |
1043 | /* Update the reply post host index after continuously |
1044 | * processing the threshold number of Reply Descriptors. | |
1045 | * So that FW can find enough entries to post the Reply | |
1046 | * Descriptors in the reply descriptor post queue. | |
1047 | */ | |
1048 | if (completed_cmds > ioc->hba_queue_depth/3) { | |
1049 | if (ioc->combined_reply_queue) { | |
1050 | writel(reply_q->reply_post_host_index | | |
1051 | ((msix_index & 7) << | |
1052 | MPI2_RPHI_MSIX_INDEX_SHIFT), | |
1053 | ioc->replyPostRegisterIndex[msix_index/8]); | |
1054 | } else { | |
1055 | writel(reply_q->reply_post_host_index | | |
1056 | (msix_index << | |
1057 | MPI2_RPHI_MSIX_INDEX_SHIFT), | |
1058 | &ioc->chip->ReplyPostHostIndex); | |
1059 | } | |
1060 | completed_cmds = 1; | |
1061 | } | |
f92363d1 SR |
1062 | if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) |
1063 | goto out; | |
1064 | if (!reply_q->reply_post_host_index) | |
1065 | rpf = reply_q->reply_post_free; | |
1066 | else | |
1067 | rpf++; | |
1068 | } while (1); | |
1069 | ||
1070 | out: | |
1071 | ||
1072 | if (!completed_cmds) { | |
1073 | atomic_dec(&reply_q->busy); | |
1074 | return IRQ_NONE; | |
1075 | } | |
1076 | ||
7786ab6a SR |
1077 | if (ioc->is_warpdrive) { |
1078 | writel(reply_q->reply_post_host_index, | |
1079 | ioc->reply_post_host_index[msix_index]); | |
1080 | atomic_dec(&reply_q->busy); | |
1081 | return IRQ_HANDLED; | |
1082 | } | |
fb77bb53 SR |
1083 | |
1084 | /* Update Reply Post Host Index. | |
1085 | * For those HBA's which support combined reply queue feature | |
1086 | * 1. Get the correct Supplemental Reply Post Host Index Register. | |
1087 | * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host | |
1088 | * Index Register address bank i.e replyPostRegisterIndex[], | |
1089 | * 2. Then update this register with new reply host index value | |
1090 | * in ReplyPostIndex field and the MSIxIndex field with | |
1091 | * msix_index value reduced to a value between 0 and 7, | |
1092 | * using a modulo 8 operation. Since each Supplemental Reply Post | |
1093 | * Host Index Register supports 8 MSI-X vectors. | |
1094 | * | |
1095 | * For other HBA's just update the Reply Post Host Index register with | |
1096 | * new reply host index value in ReplyPostIndex Field and msix_index | |
1097 | * value in MSIxIndex field. | |
1098 | */ | |
0bb337c9 | 1099 | if (ioc->combined_reply_queue) |
fb77bb53 SR |
1100 | writel(reply_q->reply_post_host_index | ((msix_index & 7) << |
1101 | MPI2_RPHI_MSIX_INDEX_SHIFT), | |
1102 | ioc->replyPostRegisterIndex[msix_index/8]); | |
1103 | else | |
1104 | writel(reply_q->reply_post_host_index | (msix_index << | |
1105 | MPI2_RPHI_MSIX_INDEX_SHIFT), | |
1106 | &ioc->chip->ReplyPostHostIndex); | |
f92363d1 SR |
1107 | atomic_dec(&reply_q->busy); |
1108 | return IRQ_HANDLED; | |
1109 | } | |
1110 | ||
1111 | /** | |
1112 | * _base_is_controller_msix_enabled - is controller support muli-reply queues | |
1113 | * @ioc: per adapter object | |
1114 | * | |
1115 | */ | |
1116 | static inline int | |
1117 | _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc) | |
1118 | { | |
1119 | return (ioc->facts.IOCCapabilities & | |
1120 | MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable; | |
1121 | } | |
1122 | ||
1123 | /** | |
5f0dfb7a | 1124 | * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts |
f92363d1 | 1125 | * @ioc: per adapter object |
5f0dfb7a | 1126 | * Context: non ISR conext |
f92363d1 | 1127 | * |
5f0dfb7a | 1128 | * Called when a Task Management request has completed. |
f92363d1 SR |
1129 | * |
1130 | * Return nothing. | |
1131 | */ | |
1132 | void | |
5f0dfb7a | 1133 | mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
1134 | { |
1135 | struct adapter_reply_queue *reply_q; | |
1136 | ||
1137 | /* If MSIX capability is turned off | |
1138 | * then multi-queues are not enabled | |
1139 | */ | |
1140 | if (!_base_is_controller_msix_enabled(ioc)) | |
1141 | return; | |
1142 | ||
1143 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { | |
5f0dfb7a C |
1144 | if (ioc->shost_recovery || ioc->remove_host || |
1145 | ioc->pci_error_recovery) | |
f92363d1 SR |
1146 | return; |
1147 | /* TMs are on msix_index == 0 */ | |
1148 | if (reply_q->msix_index == 0) | |
1149 | continue; | |
1d55abc0 | 1150 | synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index)); |
f92363d1 SR |
1151 | } |
1152 | } | |
1153 | ||
1154 | /** | |
1155 | * mpt3sas_base_release_callback_handler - clear interrupt callback handler | |
1156 | * @cb_idx: callback index | |
1157 | * | |
1158 | * Return nothing. | |
1159 | */ | |
1160 | void | |
1161 | mpt3sas_base_release_callback_handler(u8 cb_idx) | |
1162 | { | |
1163 | mpt_callbacks[cb_idx] = NULL; | |
1164 | } | |
1165 | ||
1166 | /** | |
1167 | * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler | |
1168 | * @cb_func: callback function | |
1169 | * | |
1170 | * Returns cb_func. | |
1171 | */ | |
1172 | u8 | |
1173 | mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func) | |
1174 | { | |
1175 | u8 cb_idx; | |
1176 | ||
1177 | for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--) | |
1178 | if (mpt_callbacks[cb_idx] == NULL) | |
1179 | break; | |
1180 | ||
1181 | mpt_callbacks[cb_idx] = cb_func; | |
1182 | return cb_idx; | |
1183 | } | |
1184 | ||
1185 | /** | |
1186 | * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler | |
1187 | * | |
1188 | * Return nothing. | |
1189 | */ | |
1190 | void | |
1191 | mpt3sas_base_initialize_callback_handler(void) | |
1192 | { | |
1193 | u8 cb_idx; | |
1194 | ||
1195 | for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++) | |
1196 | mpt3sas_base_release_callback_handler(cb_idx); | |
1197 | } | |
1198 | ||
1199 | ||
1200 | /** | |
1201 | * _base_build_zero_len_sge - build zero length sg entry | |
1202 | * @ioc: per adapter object | |
1203 | * @paddr: virtual address for SGE | |
1204 | * | |
1205 | * Create a zero length scatter gather entry to insure the IOCs hardware has | |
1206 | * something to use if the target device goes brain dead and tries | |
1207 | * to send data even when none is asked for. | |
1208 | * | |
1209 | * Return nothing. | |
1210 | */ | |
1211 | static void | |
1212 | _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr) | |
1213 | { | |
1214 | u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT | | |
1215 | MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST | | |
1216 | MPI2_SGE_FLAGS_SIMPLE_ELEMENT) << | |
1217 | MPI2_SGE_FLAGS_SHIFT); | |
1218 | ioc->base_add_sg_single(paddr, flags_length, -1); | |
1219 | } | |
1220 | ||
1221 | /** | |
1222 | * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr. | |
1223 | * @paddr: virtual address for SGE | |
1224 | * @flags_length: SGE flags and data transfer length | |
1225 | * @dma_addr: Physical address | |
1226 | * | |
1227 | * Return nothing. | |
1228 | */ | |
1229 | static void | |
1230 | _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr) | |
1231 | { | |
1232 | Mpi2SGESimple32_t *sgel = paddr; | |
1233 | ||
1234 | flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING | | |
1235 | MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; | |
1236 | sgel->FlagsLength = cpu_to_le32(flags_length); | |
1237 | sgel->Address = cpu_to_le32(dma_addr); | |
1238 | } | |
1239 | ||
1240 | ||
1241 | /** | |
1242 | * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr. | |
1243 | * @paddr: virtual address for SGE | |
1244 | * @flags_length: SGE flags and data transfer length | |
1245 | * @dma_addr: Physical address | |
1246 | * | |
1247 | * Return nothing. | |
1248 | */ | |
1249 | static void | |
1250 | _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr) | |
1251 | { | |
1252 | Mpi2SGESimple64_t *sgel = paddr; | |
1253 | ||
1254 | flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING | | |
1255 | MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; | |
1256 | sgel->FlagsLength = cpu_to_le32(flags_length); | |
1257 | sgel->Address = cpu_to_le64(dma_addr); | |
1258 | } | |
1259 | ||
1260 | /** | |
1261 | * _base_get_chain_buffer_tracker - obtain chain tracker | |
1262 | * @ioc: per adapter object | |
1263 | * @smid: smid associated to an IO request | |
1264 | * | |
1265 | * Returns chain tracker(from ioc->free_chain_list) | |
1266 | */ | |
1267 | static struct chain_tracker * | |
1268 | _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
1269 | { | |
1270 | struct chain_tracker *chain_req; | |
1271 | unsigned long flags; | |
1272 | ||
1273 | spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); | |
1274 | if (list_empty(&ioc->free_chain_list)) { | |
1275 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
1276 | dfailprintk(ioc, pr_warn(MPT3SAS_FMT | |
1277 | "chain buffers not available\n", ioc->name)); | |
1278 | return NULL; | |
1279 | } | |
1280 | chain_req = list_entry(ioc->free_chain_list.next, | |
1281 | struct chain_tracker, tracker_list); | |
1282 | list_del_init(&chain_req->tracker_list); | |
1283 | list_add_tail(&chain_req->tracker_list, | |
1284 | &ioc->scsi_lookup[smid - 1].chain_list); | |
1285 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
1286 | return chain_req; | |
1287 | } | |
1288 | ||
1289 | ||
1290 | /** | |
1291 | * _base_build_sg - build generic sg | |
1292 | * @ioc: per adapter object | |
1293 | * @psge: virtual address for SGE | |
1294 | * @data_out_dma: physical address for WRITES | |
1295 | * @data_out_sz: data xfer size for WRITES | |
1296 | * @data_in_dma: physical address for READS | |
1297 | * @data_in_sz: data xfer size for READS | |
1298 | * | |
1299 | * Return nothing. | |
1300 | */ | |
1301 | static void | |
1302 | _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge, | |
1303 | dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, | |
1304 | size_t data_in_sz) | |
1305 | { | |
1306 | u32 sgl_flags; | |
1307 | ||
1308 | if (!data_out_sz && !data_in_sz) { | |
1309 | _base_build_zero_len_sge(ioc, psge); | |
1310 | return; | |
1311 | } | |
1312 | ||
1313 | if (data_out_sz && data_in_sz) { | |
1314 | /* WRITE sgel first */ | |
1315 | sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | | |
1316 | MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC); | |
1317 | sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; | |
1318 | ioc->base_add_sg_single(psge, sgl_flags | | |
1319 | data_out_sz, data_out_dma); | |
1320 | ||
1321 | /* incr sgel */ | |
1322 | psge += ioc->sge_size; | |
1323 | ||
1324 | /* READ sgel last */ | |
1325 | sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | | |
1326 | MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | | |
1327 | MPI2_SGE_FLAGS_END_OF_LIST); | |
1328 | sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; | |
1329 | ioc->base_add_sg_single(psge, sgl_flags | | |
1330 | data_in_sz, data_in_dma); | |
1331 | } else if (data_out_sz) /* WRITE */ { | |
1332 | sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | | |
1333 | MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | | |
1334 | MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC); | |
1335 | sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; | |
1336 | ioc->base_add_sg_single(psge, sgl_flags | | |
1337 | data_out_sz, data_out_dma); | |
1338 | } else if (data_in_sz) /* READ */ { | |
1339 | sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | | |
1340 | MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | | |
1341 | MPI2_SGE_FLAGS_END_OF_LIST); | |
1342 | sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; | |
1343 | ioc->base_add_sg_single(psge, sgl_flags | | |
1344 | data_in_sz, data_in_dma); | |
1345 | } | |
1346 | } | |
1347 | ||
016d5c35 SPS |
1348 | /** |
1349 | * base_make_prp_nvme - | |
1350 | * Prepare PRPs(Physical Region Page)- SGLs specific to NVMe drives only | |
1351 | * | |
1352 | * @ioc: per adapter object | |
1353 | * @scmd: SCSI command from the mid-layer | |
1354 | * @mpi_request: mpi request | |
1355 | * @smid: msg Index | |
1356 | * @sge_count: scatter gather element count. | |
1357 | * | |
1358 | * Returns: true: PRPs are built | |
1359 | * false: IEEE SGLs needs to be built | |
1360 | */ | |
1361 | void | |
1362 | base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc, | |
1363 | struct scsi_cmnd *scmd, | |
1364 | Mpi25SCSIIORequest_t *mpi_request, | |
1365 | u16 smid, int sge_count) | |
1366 | { | |
1367 | int sge_len, offset, num_prp_in_chain = 0; | |
1368 | Mpi25IeeeSgeChain64_t *main_chain_element, *ptr_first_sgl; | |
1369 | u64 *curr_buff; | |
1370 | dma_addr_t msg_phys; | |
1371 | u64 sge_addr; | |
1372 | u32 page_mask, page_mask_result; | |
1373 | struct scatterlist *sg_scmd; | |
1374 | u32 first_prp_len; | |
1375 | int data_len = scsi_bufflen(scmd); | |
1376 | u32 nvme_pg_size; | |
1377 | ||
1378 | nvme_pg_size = max_t(u32, ioc->page_size, NVME_PRP_PAGE_SIZE); | |
1379 | /* | |
1380 | * Nvme has a very convoluted prp format. One prp is required | |
1381 | * for each page or partial page. Driver need to split up OS sg_list | |
1382 | * entries if it is longer than one page or cross a page | |
1383 | * boundary. Driver also have to insert a PRP list pointer entry as | |
1384 | * the last entry in each physical page of the PRP list. | |
1385 | * | |
1386 | * NOTE: The first PRP "entry" is actually placed in the first | |
1387 | * SGL entry in the main message as IEEE 64 format. The 2nd | |
1388 | * entry in the main message is the chain element, and the rest | |
1389 | * of the PRP entries are built in the contiguous pcie buffer. | |
1390 | */ | |
1391 | page_mask = nvme_pg_size - 1; | |
1392 | ||
1393 | /* | |
1394 | * Native SGL is needed. | |
1395 | * Put a chain element in main message frame that points to the first | |
1396 | * chain buffer. | |
1397 | * | |
1398 | * NOTE: The ChainOffset field must be 0 when using a chain pointer to | |
1399 | * a native SGL. | |
1400 | */ | |
1401 | ||
1402 | /* Set main message chain element pointer */ | |
1403 | main_chain_element = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL; | |
1404 | /* | |
1405 | * For NVMe the chain element needs to be the 2nd SG entry in the main | |
1406 | * message. | |
1407 | */ | |
1408 | main_chain_element = (Mpi25IeeeSgeChain64_t *) | |
1409 | ((u8 *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64)); | |
1410 | ||
1411 | /* | |
1412 | * For the PRP entries, use the specially allocated buffer of | |
1413 | * contiguous memory. Normal chain buffers can't be used | |
1414 | * because each chain buffer would need to be the size of an OS | |
1415 | * page (4k). | |
1416 | */ | |
1417 | curr_buff = mpt3sas_base_get_pcie_sgl(ioc, smid); | |
1418 | msg_phys = (dma_addr_t)mpt3sas_base_get_pcie_sgl_dma(ioc, smid); | |
1419 | ||
1420 | main_chain_element->Address = cpu_to_le64(msg_phys); | |
1421 | main_chain_element->NextChainOffset = 0; | |
1422 | main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | | |
1423 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | | |
1424 | MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP; | |
1425 | ||
1426 | /* Build first prp, sge need not to be page aligned*/ | |
1427 | ptr_first_sgl = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL; | |
1428 | sg_scmd = scsi_sglist(scmd); | |
1429 | sge_addr = sg_dma_address(sg_scmd); | |
1430 | sge_len = sg_dma_len(sg_scmd); | |
1431 | ||
1432 | offset = (u32)(sge_addr & page_mask); | |
1433 | first_prp_len = nvme_pg_size - offset; | |
1434 | ||
1435 | ptr_first_sgl->Address = cpu_to_le64(sge_addr); | |
1436 | ptr_first_sgl->Length = cpu_to_le32(first_prp_len); | |
1437 | ||
1438 | data_len -= first_prp_len; | |
1439 | ||
1440 | if (sge_len > first_prp_len) { | |
1441 | sge_addr += first_prp_len; | |
1442 | sge_len -= first_prp_len; | |
1443 | } else if (data_len && (sge_len == first_prp_len)) { | |
1444 | sg_scmd = sg_next(sg_scmd); | |
1445 | sge_addr = sg_dma_address(sg_scmd); | |
1446 | sge_len = sg_dma_len(sg_scmd); | |
1447 | } | |
1448 | ||
1449 | for (;;) { | |
1450 | offset = (u32)(sge_addr & page_mask); | |
1451 | ||
1452 | /* Put PRP pointer due to page boundary*/ | |
1453 | page_mask_result = (uintptr_t)(curr_buff + 1) & page_mask; | |
1454 | if (unlikely(!page_mask_result)) { | |
1455 | scmd_printk(KERN_NOTICE, | |
1456 | scmd, "page boundary curr_buff: 0x%p\n", | |
1457 | curr_buff); | |
1458 | msg_phys += 8; | |
1459 | *curr_buff = cpu_to_le64(msg_phys); | |
1460 | curr_buff++; | |
1461 | num_prp_in_chain++; | |
1462 | } | |
1463 | ||
1464 | *curr_buff = cpu_to_le64(sge_addr); | |
1465 | curr_buff++; | |
1466 | msg_phys += 8; | |
1467 | num_prp_in_chain++; | |
1468 | ||
1469 | sge_addr += nvme_pg_size; | |
1470 | sge_len -= nvme_pg_size; | |
1471 | data_len -= nvme_pg_size; | |
1472 | ||
1473 | if (data_len <= 0) | |
1474 | break; | |
1475 | ||
1476 | if (sge_len > 0) | |
1477 | continue; | |
1478 | ||
1479 | sg_scmd = sg_next(sg_scmd); | |
1480 | sge_addr = sg_dma_address(sg_scmd); | |
1481 | sge_len = sg_dma_len(sg_scmd); | |
1482 | } | |
1483 | ||
1484 | main_chain_element->Length = | |
1485 | cpu_to_le32(num_prp_in_chain * sizeof(u64)); | |
1486 | return; | |
1487 | } | |
1488 | ||
1489 | static bool | |
1490 | base_is_prp_possible(struct MPT3SAS_ADAPTER *ioc, | |
1491 | struct _pcie_device *pcie_device, struct scsi_cmnd *scmd, int sge_count) | |
1492 | { | |
1493 | u32 data_length = 0; | |
1494 | struct scatterlist *sg_scmd; | |
1495 | bool build_prp = true; | |
1496 | ||
1497 | data_length = cpu_to_le32(scsi_bufflen(scmd)); | |
1498 | sg_scmd = scsi_sglist(scmd); | |
1499 | ||
1500 | /* If Datalenth is <= 16K and number of SGE’s entries are <= 2 | |
1501 | * we built IEEE SGL | |
1502 | */ | |
1503 | if ((data_length <= NVME_PRP_PAGE_SIZE*4) && (sge_count <= 2)) | |
1504 | build_prp = false; | |
1505 | ||
1506 | return build_prp; | |
1507 | } | |
1508 | ||
1509 | /** | |
1510 | * _base_check_pcie_native_sgl - This function is called for PCIe end devices to | |
1511 | * determine if the driver needs to build a native SGL. If so, that native | |
1512 | * SGL is built in the special contiguous buffers allocated especially for | |
1513 | * PCIe SGL creation. If the driver will not build a native SGL, return | |
1514 | * TRUE and a normal IEEE SGL will be built. Currently this routine | |
1515 | * supports NVMe. | |
1516 | * @ioc: per adapter object | |
1517 | * @mpi_request: mf request pointer | |
1518 | * @smid: system request message index | |
1519 | * @scmd: scsi command | |
1520 | * @pcie_device: points to the PCIe device's info | |
1521 | * | |
1522 | * Returns 0 if native SGL was built, 1 if no SGL was built | |
1523 | */ | |
1524 | static int | |
1525 | _base_check_pcie_native_sgl(struct MPT3SAS_ADAPTER *ioc, | |
1526 | Mpi25SCSIIORequest_t *mpi_request, u16 smid, struct scsi_cmnd *scmd, | |
1527 | struct _pcie_device *pcie_device) | |
1528 | { | |
1529 | struct scatterlist *sg_scmd; | |
1530 | int sges_left; | |
1531 | ||
1532 | /* Get the SG list pointer and info. */ | |
1533 | sg_scmd = scsi_sglist(scmd); | |
1534 | sges_left = scsi_dma_map(scmd); | |
1535 | if (sges_left < 0) { | |
1536 | sdev_printk(KERN_ERR, scmd->device, | |
1537 | "scsi_dma_map failed: request for %d bytes!\n", | |
1538 | scsi_bufflen(scmd)); | |
1539 | return 1; | |
1540 | } | |
1541 | ||
1542 | /* Check if we need to build a native SG list. */ | |
1543 | if (base_is_prp_possible(ioc, pcie_device, | |
1544 | scmd, sges_left) == 0) { | |
1545 | /* We built a native SG list, just return. */ | |
1546 | goto out; | |
1547 | } | |
1548 | ||
1549 | /* | |
1550 | * Build native NVMe PRP. | |
1551 | */ | |
1552 | base_make_prp_nvme(ioc, scmd, mpi_request, | |
1553 | smid, sges_left); | |
1554 | ||
1555 | return 0; | |
1556 | out: | |
1557 | scsi_dma_unmap(scmd); | |
1558 | return 1; | |
1559 | } | |
f92363d1 SR |
1560 | |
1561 | /** | |
1562 | * _base_add_sg_single_ieee - add sg element for IEEE format | |
1563 | * @paddr: virtual address for SGE | |
1564 | * @flags: SGE flags | |
1565 | * @chain_offset: number of 128 byte elements from start of segment | |
1566 | * @length: data transfer length | |
1567 | * @dma_addr: Physical address | |
1568 | * | |
1569 | * Return nothing. | |
1570 | */ | |
1571 | static void | |
1572 | _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length, | |
1573 | dma_addr_t dma_addr) | |
1574 | { | |
1575 | Mpi25IeeeSgeChain64_t *sgel = paddr; | |
1576 | ||
1577 | sgel->Flags = flags; | |
1578 | sgel->NextChainOffset = chain_offset; | |
1579 | sgel->Length = cpu_to_le32(length); | |
1580 | sgel->Address = cpu_to_le64(dma_addr); | |
1581 | } | |
1582 | ||
1583 | /** | |
1584 | * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format | |
1585 | * @ioc: per adapter object | |
1586 | * @paddr: virtual address for SGE | |
1587 | * | |
1588 | * Create a zero length scatter gather entry to insure the IOCs hardware has | |
1589 | * something to use if the target device goes brain dead and tries | |
1590 | * to send data even when none is asked for. | |
1591 | * | |
1592 | * Return nothing. | |
1593 | */ | |
1594 | static void | |
1595 | _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr) | |
1596 | { | |
1597 | u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | | |
1598 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | | |
1599 | MPI25_IEEE_SGE_FLAGS_END_OF_LIST); | |
b130b0d5 | 1600 | |
f92363d1 SR |
1601 | _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1); |
1602 | } | |
1603 | ||
471ef9d4 SR |
1604 | /** |
1605 | * _base_build_sg_scmd - main sg creation routine | |
016d5c35 | 1606 | * pcie_device is unused here! |
471ef9d4 SR |
1607 | * @ioc: per adapter object |
1608 | * @scmd: scsi command | |
1609 | * @smid: system request message index | |
016d5c35 | 1610 | * @unused: unused pcie_device pointer |
471ef9d4 SR |
1611 | * Context: none. |
1612 | * | |
1613 | * The main routine that builds scatter gather table from a given | |
1614 | * scsi request sent via the .queuecommand main handler. | |
1615 | * | |
1616 | * Returns 0 success, anything else error | |
1617 | */ | |
1618 | static int | |
1619 | _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc, | |
016d5c35 | 1620 | struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *unused) |
471ef9d4 SR |
1621 | { |
1622 | Mpi2SCSIIORequest_t *mpi_request; | |
1623 | dma_addr_t chain_dma; | |
1624 | struct scatterlist *sg_scmd; | |
1625 | void *sg_local, *chain; | |
1626 | u32 chain_offset; | |
1627 | u32 chain_length; | |
1628 | u32 chain_flags; | |
1629 | int sges_left; | |
1630 | u32 sges_in_segment; | |
1631 | u32 sgl_flags; | |
1632 | u32 sgl_flags_last_element; | |
1633 | u32 sgl_flags_end_buffer; | |
1634 | struct chain_tracker *chain_req; | |
1635 | ||
1636 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
1637 | ||
1638 | /* init scatter gather flags */ | |
1639 | sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT; | |
1640 | if (scmd->sc_data_direction == DMA_TO_DEVICE) | |
1641 | sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC; | |
1642 | sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT) | |
1643 | << MPI2_SGE_FLAGS_SHIFT; | |
1644 | sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT | | |
1645 | MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST) | |
1646 | << MPI2_SGE_FLAGS_SHIFT; | |
1647 | sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; | |
1648 | ||
1649 | sg_scmd = scsi_sglist(scmd); | |
1650 | sges_left = scsi_dma_map(scmd); | |
1651 | if (sges_left < 0) { | |
1652 | sdev_printk(KERN_ERR, scmd->device, | |
1653 | "pci_map_sg failed: request for %d bytes!\n", | |
1654 | scsi_bufflen(scmd)); | |
1655 | return -ENOMEM; | |
1656 | } | |
1657 | ||
1658 | sg_local = &mpi_request->SGL; | |
1659 | sges_in_segment = ioc->max_sges_in_main_message; | |
1660 | if (sges_left <= sges_in_segment) | |
1661 | goto fill_in_last_segment; | |
1662 | ||
1663 | mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) + | |
1664 | (sges_in_segment * ioc->sge_size))/4; | |
1665 | ||
1666 | /* fill in main message segment when there is a chain following */ | |
1667 | while (sges_in_segment) { | |
1668 | if (sges_in_segment == 1) | |
1669 | ioc->base_add_sg_single(sg_local, | |
1670 | sgl_flags_last_element | sg_dma_len(sg_scmd), | |
1671 | sg_dma_address(sg_scmd)); | |
1672 | else | |
1673 | ioc->base_add_sg_single(sg_local, sgl_flags | | |
1674 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
1675 | sg_scmd = sg_next(sg_scmd); | |
1676 | sg_local += ioc->sge_size; | |
1677 | sges_left--; | |
1678 | sges_in_segment--; | |
1679 | } | |
1680 | ||
1681 | /* initializing the chain flags and pointers */ | |
1682 | chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT; | |
1683 | chain_req = _base_get_chain_buffer_tracker(ioc, smid); | |
1684 | if (!chain_req) | |
1685 | return -1; | |
1686 | chain = chain_req->chain_buffer; | |
1687 | chain_dma = chain_req->chain_buffer_dma; | |
1688 | do { | |
1689 | sges_in_segment = (sges_left <= | |
1690 | ioc->max_sges_in_chain_message) ? sges_left : | |
1691 | ioc->max_sges_in_chain_message; | |
1692 | chain_offset = (sges_left == sges_in_segment) ? | |
1693 | 0 : (sges_in_segment * ioc->sge_size)/4; | |
1694 | chain_length = sges_in_segment * ioc->sge_size; | |
1695 | if (chain_offset) { | |
1696 | chain_offset = chain_offset << | |
1697 | MPI2_SGE_CHAIN_OFFSET_SHIFT; | |
1698 | chain_length += ioc->sge_size; | |
1699 | } | |
1700 | ioc->base_add_sg_single(sg_local, chain_flags | chain_offset | | |
1701 | chain_length, chain_dma); | |
1702 | sg_local = chain; | |
1703 | if (!chain_offset) | |
1704 | goto fill_in_last_segment; | |
1705 | ||
1706 | /* fill in chain segments */ | |
1707 | while (sges_in_segment) { | |
1708 | if (sges_in_segment == 1) | |
1709 | ioc->base_add_sg_single(sg_local, | |
1710 | sgl_flags_last_element | | |
1711 | sg_dma_len(sg_scmd), | |
1712 | sg_dma_address(sg_scmd)); | |
1713 | else | |
1714 | ioc->base_add_sg_single(sg_local, sgl_flags | | |
1715 | sg_dma_len(sg_scmd), | |
1716 | sg_dma_address(sg_scmd)); | |
1717 | sg_scmd = sg_next(sg_scmd); | |
1718 | sg_local += ioc->sge_size; | |
1719 | sges_left--; | |
1720 | sges_in_segment--; | |
1721 | } | |
1722 | ||
1723 | chain_req = _base_get_chain_buffer_tracker(ioc, smid); | |
1724 | if (!chain_req) | |
1725 | return -1; | |
1726 | chain = chain_req->chain_buffer; | |
1727 | chain_dma = chain_req->chain_buffer_dma; | |
1728 | } while (1); | |
1729 | ||
1730 | ||
1731 | fill_in_last_segment: | |
1732 | ||
1733 | /* fill the last segment */ | |
1734 | while (sges_left) { | |
1735 | if (sges_left == 1) | |
1736 | ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer | | |
1737 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
1738 | else | |
1739 | ioc->base_add_sg_single(sg_local, sgl_flags | | |
1740 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
1741 | sg_scmd = sg_next(sg_scmd); | |
1742 | sg_local += ioc->sge_size; | |
1743 | sges_left--; | |
1744 | } | |
1745 | ||
1746 | return 0; | |
1747 | } | |
1748 | ||
f92363d1 SR |
1749 | /** |
1750 | * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format | |
1751 | * @ioc: per adapter object | |
1752 | * @scmd: scsi command | |
1753 | * @smid: system request message index | |
016d5c35 SPS |
1754 | * @pcie_device: Pointer to pcie_device. If set, the pcie native sgl will be |
1755 | * constructed on need. | |
f92363d1 SR |
1756 | * Context: none. |
1757 | * | |
1758 | * The main routine that builds scatter gather table from a given | |
1759 | * scsi request sent via the .queuecommand main handler. | |
1760 | * | |
1761 | * Returns 0 success, anything else error | |
1762 | */ | |
1763 | static int | |
1764 | _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc, | |
016d5c35 | 1765 | struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device) |
f92363d1 | 1766 | { |
016d5c35 | 1767 | Mpi25SCSIIORequest_t *mpi_request; |
f92363d1 SR |
1768 | dma_addr_t chain_dma; |
1769 | struct scatterlist *sg_scmd; | |
1770 | void *sg_local, *chain; | |
1771 | u32 chain_offset; | |
1772 | u32 chain_length; | |
f92363d1 SR |
1773 | int sges_left; |
1774 | u32 sges_in_segment; | |
1775 | u8 simple_sgl_flags; | |
1776 | u8 simple_sgl_flags_last; | |
1777 | u8 chain_sgl_flags; | |
1778 | struct chain_tracker *chain_req; | |
1779 | ||
1780 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
1781 | ||
1782 | /* init scatter gather flags */ | |
1783 | simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | | |
1784 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; | |
1785 | simple_sgl_flags_last = simple_sgl_flags | | |
1786 | MPI25_IEEE_SGE_FLAGS_END_OF_LIST; | |
1787 | chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | | |
1788 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; | |
1789 | ||
016d5c35 SPS |
1790 | /* Check if we need to build a native SG list. */ |
1791 | if ((pcie_device) && (_base_check_pcie_native_sgl(ioc, mpi_request, | |
1792 | smid, scmd, pcie_device) == 0)) { | |
1793 | /* We built a native SG list, just return. */ | |
1794 | return 0; | |
1795 | } | |
1796 | ||
f92363d1 SR |
1797 | sg_scmd = scsi_sglist(scmd); |
1798 | sges_left = scsi_dma_map(scmd); | |
62f5c74c | 1799 | if (sges_left < 0) { |
f92363d1 SR |
1800 | sdev_printk(KERN_ERR, scmd->device, |
1801 | "pci_map_sg failed: request for %d bytes!\n", | |
1802 | scsi_bufflen(scmd)); | |
1803 | return -ENOMEM; | |
1804 | } | |
1805 | ||
1806 | sg_local = &mpi_request->SGL; | |
1807 | sges_in_segment = (ioc->request_sz - | |
016d5c35 | 1808 | offsetof(Mpi25SCSIIORequest_t, SGL))/ioc->sge_size_ieee; |
f92363d1 SR |
1809 | if (sges_left <= sges_in_segment) |
1810 | goto fill_in_last_segment; | |
1811 | ||
1812 | mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) + | |
016d5c35 | 1813 | (offsetof(Mpi25SCSIIORequest_t, SGL)/ioc->sge_size_ieee); |
f92363d1 SR |
1814 | |
1815 | /* fill in main message segment when there is a chain following */ | |
1816 | while (sges_in_segment > 1) { | |
1817 | _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, | |
1818 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
1819 | sg_scmd = sg_next(sg_scmd); | |
1820 | sg_local += ioc->sge_size_ieee; | |
1821 | sges_left--; | |
1822 | sges_in_segment--; | |
1823 | } | |
1824 | ||
25ef16d0 | 1825 | /* initializing the pointers */ |
f92363d1 SR |
1826 | chain_req = _base_get_chain_buffer_tracker(ioc, smid); |
1827 | if (!chain_req) | |
1828 | return -1; | |
1829 | chain = chain_req->chain_buffer; | |
1830 | chain_dma = chain_req->chain_buffer_dma; | |
1831 | do { | |
1832 | sges_in_segment = (sges_left <= | |
1833 | ioc->max_sges_in_chain_message) ? sges_left : | |
1834 | ioc->max_sges_in_chain_message; | |
1835 | chain_offset = (sges_left == sges_in_segment) ? | |
1836 | 0 : sges_in_segment; | |
1837 | chain_length = sges_in_segment * ioc->sge_size_ieee; | |
1838 | if (chain_offset) | |
1839 | chain_length += ioc->sge_size_ieee; | |
1840 | _base_add_sg_single_ieee(sg_local, chain_sgl_flags, | |
1841 | chain_offset, chain_length, chain_dma); | |
1842 | ||
1843 | sg_local = chain; | |
1844 | if (!chain_offset) | |
1845 | goto fill_in_last_segment; | |
1846 | ||
1847 | /* fill in chain segments */ | |
1848 | while (sges_in_segment) { | |
1849 | _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, | |
1850 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
1851 | sg_scmd = sg_next(sg_scmd); | |
1852 | sg_local += ioc->sge_size_ieee; | |
1853 | sges_left--; | |
1854 | sges_in_segment--; | |
1855 | } | |
1856 | ||
1857 | chain_req = _base_get_chain_buffer_tracker(ioc, smid); | |
1858 | if (!chain_req) | |
1859 | return -1; | |
1860 | chain = chain_req->chain_buffer; | |
1861 | chain_dma = chain_req->chain_buffer_dma; | |
1862 | } while (1); | |
1863 | ||
1864 | ||
1865 | fill_in_last_segment: | |
1866 | ||
1867 | /* fill the last segment */ | |
62f5c74c | 1868 | while (sges_left > 0) { |
f92363d1 SR |
1869 | if (sges_left == 1) |
1870 | _base_add_sg_single_ieee(sg_local, | |
1871 | simple_sgl_flags_last, 0, sg_dma_len(sg_scmd), | |
1872 | sg_dma_address(sg_scmd)); | |
1873 | else | |
1874 | _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, | |
1875 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
1876 | sg_scmd = sg_next(sg_scmd); | |
1877 | sg_local += ioc->sge_size_ieee; | |
1878 | sges_left--; | |
1879 | } | |
1880 | ||
1881 | return 0; | |
1882 | } | |
1883 | ||
1884 | /** | |
1885 | * _base_build_sg_ieee - build generic sg for IEEE format | |
1886 | * @ioc: per adapter object | |
1887 | * @psge: virtual address for SGE | |
1888 | * @data_out_dma: physical address for WRITES | |
1889 | * @data_out_sz: data xfer size for WRITES | |
1890 | * @data_in_dma: physical address for READS | |
1891 | * @data_in_sz: data xfer size for READS | |
1892 | * | |
1893 | * Return nothing. | |
1894 | */ | |
1895 | static void | |
1896 | _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge, | |
1897 | dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, | |
1898 | size_t data_in_sz) | |
1899 | { | |
1900 | u8 sgl_flags; | |
1901 | ||
1902 | if (!data_out_sz && !data_in_sz) { | |
1903 | _base_build_zero_len_sge_ieee(ioc, psge); | |
1904 | return; | |
1905 | } | |
1906 | ||
1907 | if (data_out_sz && data_in_sz) { | |
1908 | /* WRITE sgel first */ | |
1909 | sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | | |
1910 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; | |
1911 | _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, | |
1912 | data_out_dma); | |
1913 | ||
1914 | /* incr sgel */ | |
1915 | psge += ioc->sge_size_ieee; | |
1916 | ||
1917 | /* READ sgel last */ | |
1918 | sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; | |
1919 | _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, | |
1920 | data_in_dma); | |
1921 | } else if (data_out_sz) /* WRITE */ { | |
1922 | sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | | |
1923 | MPI25_IEEE_SGE_FLAGS_END_OF_LIST | | |
1924 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; | |
1925 | _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, | |
1926 | data_out_dma); | |
1927 | } else if (data_in_sz) /* READ */ { | |
1928 | sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | | |
1929 | MPI25_IEEE_SGE_FLAGS_END_OF_LIST | | |
1930 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; | |
1931 | _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, | |
1932 | data_in_dma); | |
1933 | } | |
1934 | } | |
1935 | ||
1936 | #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10)) | |
1937 | ||
1938 | /** | |
1939 | * _base_config_dma_addressing - set dma addressing | |
1940 | * @ioc: per adapter object | |
1941 | * @pdev: PCI device struct | |
1942 | * | |
1943 | * Returns 0 for success, non-zero for failure. | |
1944 | */ | |
1945 | static int | |
1946 | _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev) | |
1947 | { | |
1948 | struct sysinfo s; | |
9b05c91a SR |
1949 | u64 consistent_dma_mask; |
1950 | ||
1951 | if (ioc->dma_mask) | |
1952 | consistent_dma_mask = DMA_BIT_MASK(64); | |
1953 | else | |
1954 | consistent_dma_mask = DMA_BIT_MASK(32); | |
f92363d1 SR |
1955 | |
1956 | if (sizeof(dma_addr_t) > 4) { | |
1957 | const uint64_t required_mask = | |
1958 | dma_get_required_mask(&pdev->dev); | |
1959 | if ((required_mask > DMA_BIT_MASK(32)) && | |
1960 | !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && | |
9b05c91a | 1961 | !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) { |
f92363d1 SR |
1962 | ioc->base_add_sg_single = &_base_add_sg_single_64; |
1963 | ioc->sge_size = sizeof(Mpi2SGESimple64_t); | |
9b05c91a | 1964 | ioc->dma_mask = 64; |
f92363d1 SR |
1965 | goto out; |
1966 | } | |
1967 | } | |
1968 | ||
1969 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) | |
1970 | && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { | |
1971 | ioc->base_add_sg_single = &_base_add_sg_single_32; | |
1972 | ioc->sge_size = sizeof(Mpi2SGESimple32_t); | |
9b05c91a | 1973 | ioc->dma_mask = 32; |
f92363d1 SR |
1974 | } else |
1975 | return -ENODEV; | |
1976 | ||
1977 | out: | |
1978 | si_meminfo(&s); | |
1979 | pr_info(MPT3SAS_FMT | |
9b05c91a SR |
1980 | "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n", |
1981 | ioc->name, ioc->dma_mask, convert_to_kb(s.totalram)); | |
1982 | ||
1983 | return 0; | |
1984 | } | |
f92363d1 | 1985 | |
9b05c91a SR |
1986 | static int |
1987 | _base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc, | |
1988 | struct pci_dev *pdev) | |
1989 | { | |
1990 | if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { | |
1991 | if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) | |
1992 | return -ENODEV; | |
1993 | } | |
f92363d1 SR |
1994 | return 0; |
1995 | } | |
1996 | ||
1997 | /** | |
1998 | * _base_check_enable_msix - checks MSIX capabable. | |
1999 | * @ioc: per adapter object | |
2000 | * | |
2001 | * Check to see if card is capable of MSIX, and set number | |
2002 | * of available msix vectors | |
2003 | */ | |
2004 | static int | |
2005 | _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc) | |
2006 | { | |
2007 | int base; | |
2008 | u16 message_control; | |
2009 | ||
42081173 SR |
2010 | /* Check whether controller SAS2008 B0 controller, |
2011 | * if it is SAS2008 B0 controller use IO-APIC instead of MSIX | |
2012 | */ | |
2013 | if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 && | |
2014 | ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) { | |
2015 | return -EINVAL; | |
2016 | } | |
2017 | ||
f92363d1 SR |
2018 | base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX); |
2019 | if (!base) { | |
2020 | dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n", | |
2021 | ioc->name)); | |
2022 | return -EINVAL; | |
2023 | } | |
2024 | ||
2025 | /* get msix vector count */ | |
42081173 SR |
2026 | /* NUMA_IO not supported for older controllers */ |
2027 | if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 || | |
2028 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 || | |
2029 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 || | |
2030 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 || | |
2031 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 || | |
2032 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 || | |
2033 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2) | |
2034 | ioc->msix_vector_count = 1; | |
2035 | else { | |
2036 | pci_read_config_word(ioc->pdev, base + 2, &message_control); | |
2037 | ioc->msix_vector_count = (message_control & 0x3FF) + 1; | |
2038 | } | |
f92363d1 SR |
2039 | dinitprintk(ioc, pr_info(MPT3SAS_FMT |
2040 | "msix is supported, vector_count(%d)\n", | |
2041 | ioc->name, ioc->msix_vector_count)); | |
2042 | return 0; | |
2043 | } | |
2044 | ||
2045 | /** | |
2046 | * _base_free_irq - free irq | |
2047 | * @ioc: per adapter object | |
2048 | * | |
2049 | * Freeing respective reply_queue from the list. | |
2050 | */ | |
2051 | static void | |
2052 | _base_free_irq(struct MPT3SAS_ADAPTER *ioc) | |
2053 | { | |
2054 | struct adapter_reply_queue *reply_q, *next; | |
2055 | ||
2056 | if (list_empty(&ioc->reply_queue_list)) | |
2057 | return; | |
2058 | ||
2059 | list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) { | |
2060 | list_del(&reply_q->list); | |
1d55abc0 HR |
2061 | free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index), |
2062 | reply_q); | |
f92363d1 SR |
2063 | kfree(reply_q); |
2064 | } | |
2065 | } | |
2066 | ||
2067 | /** | |
2068 | * _base_request_irq - request irq | |
2069 | * @ioc: per adapter object | |
2070 | * @index: msix index into vector table | |
f92363d1 SR |
2071 | * |
2072 | * Inserting respective reply_queue into the list. | |
2073 | */ | |
2074 | static int | |
1d55abc0 | 2075 | _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index) |
f92363d1 | 2076 | { |
1d55abc0 | 2077 | struct pci_dev *pdev = ioc->pdev; |
f92363d1 SR |
2078 | struct adapter_reply_queue *reply_q; |
2079 | int r; | |
2080 | ||
2081 | reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL); | |
2082 | if (!reply_q) { | |
2083 | pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n", | |
2084 | ioc->name, (int)sizeof(struct adapter_reply_queue)); | |
2085 | return -ENOMEM; | |
2086 | } | |
2087 | reply_q->ioc = ioc; | |
2088 | reply_q->msix_index = index; | |
14b3114d | 2089 | |
f92363d1 SR |
2090 | atomic_set(&reply_q->busy, 0); |
2091 | if (ioc->msix_enable) | |
2092 | snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d", | |
c84b06a4 | 2093 | ioc->driver_name, ioc->id, index); |
f92363d1 SR |
2094 | else |
2095 | snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d", | |
c84b06a4 | 2096 | ioc->driver_name, ioc->id); |
1d55abc0 HR |
2097 | r = request_irq(pci_irq_vector(pdev, index), _base_interrupt, |
2098 | IRQF_SHARED, reply_q->name, reply_q); | |
f92363d1 SR |
2099 | if (r) { |
2100 | pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n", | |
1d55abc0 | 2101 | reply_q->name, pci_irq_vector(pdev, index)); |
da3cec25 | 2102 | kfree(reply_q); |
f92363d1 SR |
2103 | return -EBUSY; |
2104 | } | |
2105 | ||
2106 | INIT_LIST_HEAD(&reply_q->list); | |
2107 | list_add_tail(&reply_q->list, &ioc->reply_queue_list); | |
2108 | return 0; | |
2109 | } | |
2110 | ||
2111 | /** | |
2112 | * _base_assign_reply_queues - assigning msix index for each cpu | |
2113 | * @ioc: per adapter object | |
2114 | * | |
2115 | * The enduser would need to set the affinity via /proc/irq/#/smp_affinity | |
2116 | * | |
2117 | * It would nice if we could call irq_set_affinity, however it is not | |
2118 | * an exported symbol | |
2119 | */ | |
2120 | static void | |
2121 | _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc) | |
2122 | { | |
91b265bf | 2123 | unsigned int cpu, nr_cpus, nr_msix, index = 0; |
14b3114d | 2124 | struct adapter_reply_queue *reply_q; |
f92363d1 SR |
2125 | |
2126 | if (!_base_is_controller_msix_enabled(ioc)) | |
2127 | return; | |
2128 | ||
2129 | memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz); | |
2130 | ||
91b265bf MP |
2131 | nr_cpus = num_online_cpus(); |
2132 | nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count, | |
2133 | ioc->facts.MaxMSIxVectors); | |
2134 | if (!nr_msix) | |
2135 | return; | |
f92363d1 | 2136 | |
1d55abc0 HR |
2137 | if (smp_affinity_enable) { |
2138 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { | |
2139 | const cpumask_t *mask = pci_irq_get_affinity(ioc->pdev, | |
2140 | reply_q->msix_index); | |
2141 | if (!mask) { | |
2142 | pr_warn(MPT3SAS_FMT "no affinity for msi %x\n", | |
2143 | ioc->name, reply_q->msix_index); | |
2144 | continue; | |
2145 | } | |
2146 | ||
2147 | for_each_cpu(cpu, mask) | |
2148 | ioc->cpu_msix_table[cpu] = reply_q->msix_index; | |
2149 | } | |
2150 | return; | |
2151 | } | |
91b265bf MP |
2152 | cpu = cpumask_first(cpu_online_mask); |
2153 | ||
14b3114d SR |
2154 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { |
2155 | ||
91b265bf MP |
2156 | unsigned int i, group = nr_cpus / nr_msix; |
2157 | ||
14b3114d SR |
2158 | if (cpu >= nr_cpus) |
2159 | break; | |
2160 | ||
91b265bf MP |
2161 | if (index < nr_cpus % nr_msix) |
2162 | group++; | |
2163 | ||
2164 | for (i = 0 ; i < group ; i++) { | |
1d55abc0 | 2165 | ioc->cpu_msix_table[cpu] = reply_q->msix_index; |
91b265bf | 2166 | cpu = cpumask_next(cpu, cpu_online_mask); |
f92363d1 | 2167 | } |
91b265bf | 2168 | index++; |
14b3114d | 2169 | } |
f92363d1 SR |
2170 | } |
2171 | ||
2172 | /** | |
2173 | * _base_disable_msix - disables msix | |
2174 | * @ioc: per adapter object | |
2175 | * | |
2176 | */ | |
2177 | static void | |
2178 | _base_disable_msix(struct MPT3SAS_ADAPTER *ioc) | |
2179 | { | |
2180 | if (!ioc->msix_enable) | |
2181 | return; | |
2182 | pci_disable_msix(ioc->pdev); | |
2183 | ioc->msix_enable = 0; | |
2184 | } | |
2185 | ||
2186 | /** | |
2187 | * _base_enable_msix - enables msix, failback to io_apic | |
2188 | * @ioc: per adapter object | |
2189 | * | |
2190 | */ | |
2191 | static int | |
2192 | _base_enable_msix(struct MPT3SAS_ADAPTER *ioc) | |
2193 | { | |
f92363d1 | 2194 | int r; |
bb350661 | 2195 | int i, local_max_msix_vectors; |
f92363d1 | 2196 | u8 try_msix = 0; |
1d55abc0 | 2197 | unsigned int irq_flags = PCI_IRQ_MSIX; |
f92363d1 | 2198 | |
f92363d1 SR |
2199 | if (msix_disable == -1 || msix_disable == 0) |
2200 | try_msix = 1; | |
2201 | ||
2202 | if (!try_msix) | |
2203 | goto try_ioapic; | |
2204 | ||
2205 | if (_base_check_enable_msix(ioc) != 0) | |
2206 | goto try_ioapic; | |
2207 | ||
2208 | ioc->reply_queue_count = min_t(int, ioc->cpu_count, | |
1d55abc0 | 2209 | ioc->msix_vector_count); |
f92363d1 | 2210 | |
9c500060 SR |
2211 | printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores" |
2212 | ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count, | |
2213 | ioc->cpu_count, max_msix_vectors); | |
2214 | ||
9b05c91a | 2215 | if (!ioc->rdpq_array_enable && max_msix_vectors == -1) |
06f5f976 | 2216 | local_max_msix_vectors = (reset_devices) ? 1 : 8; |
bb350661 SPS |
2217 | else |
2218 | local_max_msix_vectors = max_msix_vectors; | |
9b05c91a | 2219 | |
1d55abc0 | 2220 | if (local_max_msix_vectors > 0) |
bb350661 | 2221 | ioc->reply_queue_count = min_t(int, local_max_msix_vectors, |
9c500060 | 2222 | ioc->reply_queue_count); |
1d55abc0 | 2223 | else if (local_max_msix_vectors == 0) |
9b05c91a | 2224 | goto try_ioapic; |
9c500060 | 2225 | |
64038301 SPS |
2226 | if (ioc->msix_vector_count < ioc->cpu_count) |
2227 | smp_affinity_enable = 0; | |
2228 | ||
1d55abc0 HR |
2229 | if (smp_affinity_enable) |
2230 | irq_flags |= PCI_IRQ_AFFINITY; | |
f92363d1 | 2231 | |
1d55abc0 HR |
2232 | r = pci_alloc_irq_vectors(ioc->pdev, 1, ioc->reply_queue_count, |
2233 | irq_flags); | |
2234 | if (r < 0) { | |
f92363d1 | 2235 | dfailprintk(ioc, pr_info(MPT3SAS_FMT |
1d55abc0 | 2236 | "pci_alloc_irq_vectors failed (r=%d) !!!\n", |
f92363d1 | 2237 | ioc->name, r)); |
f92363d1 SR |
2238 | goto try_ioapic; |
2239 | } | |
2240 | ||
2241 | ioc->msix_enable = 1; | |
1d55abc0 HR |
2242 | ioc->reply_queue_count = r; |
2243 | for (i = 0; i < ioc->reply_queue_count; i++) { | |
2244 | r = _base_request_irq(ioc, i); | |
f92363d1 SR |
2245 | if (r) { |
2246 | _base_free_irq(ioc); | |
2247 | _base_disable_msix(ioc); | |
f92363d1 SR |
2248 | goto try_ioapic; |
2249 | } | |
2250 | } | |
2251 | ||
f92363d1 SR |
2252 | return 0; |
2253 | ||
2254 | /* failback to io_apic interrupt routing */ | |
2255 | try_ioapic: | |
2256 | ||
9b05c91a | 2257 | ioc->reply_queue_count = 1; |
1d55abc0 HR |
2258 | r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY); |
2259 | if (r < 0) { | |
2260 | dfailprintk(ioc, pr_info(MPT3SAS_FMT | |
2261 | "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n", | |
2262 | ioc->name, r)); | |
2263 | } else | |
2264 | r = _base_request_irq(ioc, 0); | |
f92363d1 SR |
2265 | |
2266 | return r; | |
2267 | } | |
2268 | ||
580d4e31 SR |
2269 | /** |
2270 | * mpt3sas_base_unmap_resources - free controller resources | |
2271 | * @ioc: per adapter object | |
2272 | */ | |
8bbb1cf6 | 2273 | static void |
580d4e31 SR |
2274 | mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc) |
2275 | { | |
2276 | struct pci_dev *pdev = ioc->pdev; | |
2277 | ||
2278 | dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n", | |
2279 | ioc->name, __func__)); | |
2280 | ||
2281 | _base_free_irq(ioc); | |
2282 | _base_disable_msix(ioc); | |
2283 | ||
0bb337c9 | 2284 | if (ioc->combined_reply_queue) { |
580d4e31 | 2285 | kfree(ioc->replyPostRegisterIndex); |
5f985d88 TH |
2286 | ioc->replyPostRegisterIndex = NULL; |
2287 | } | |
580d4e31 SR |
2288 | |
2289 | if (ioc->chip_phys) { | |
2290 | iounmap(ioc->chip); | |
2291 | ioc->chip_phys = 0; | |
2292 | } | |
2293 | ||
2294 | if (pci_is_enabled(pdev)) { | |
2295 | pci_release_selected_regions(ioc->pdev, ioc->bars); | |
2296 | pci_disable_pcie_error_reporting(pdev); | |
2297 | pci_disable_device(pdev); | |
2298 | } | |
2299 | } | |
2300 | ||
f92363d1 SR |
2301 | /** |
2302 | * mpt3sas_base_map_resources - map in controller resources (io/irq/memap) | |
2303 | * @ioc: per adapter object | |
2304 | * | |
2305 | * Returns 0 for success, non-zero for failure. | |
2306 | */ | |
2307 | int | |
2308 | mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc) | |
2309 | { | |
2310 | struct pci_dev *pdev = ioc->pdev; | |
2311 | u32 memap_sz; | |
2312 | u32 pio_sz; | |
2313 | int i, r = 0; | |
2314 | u64 pio_chip = 0; | |
2315 | u64 chip_phys = 0; | |
2316 | struct adapter_reply_queue *reply_q; | |
2317 | ||
2318 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", | |
2319 | ioc->name, __func__)); | |
2320 | ||
2321 | ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
2322 | if (pci_enable_device_mem(pdev)) { | |
2323 | pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n", | |
2324 | ioc->name); | |
cf9bd21a | 2325 | ioc->bars = 0; |
f92363d1 SR |
2326 | return -ENODEV; |
2327 | } | |
2328 | ||
2329 | ||
2330 | if (pci_request_selected_regions(pdev, ioc->bars, | |
c84b06a4 | 2331 | ioc->driver_name)) { |
f92363d1 SR |
2332 | pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n", |
2333 | ioc->name); | |
cf9bd21a | 2334 | ioc->bars = 0; |
f92363d1 SR |
2335 | r = -ENODEV; |
2336 | goto out_fail; | |
2337 | } | |
2338 | ||
2339 | /* AER (Advanced Error Reporting) hooks */ | |
2340 | pci_enable_pcie_error_reporting(pdev); | |
2341 | ||
2342 | pci_set_master(pdev); | |
2343 | ||
2344 | ||
2345 | if (_base_config_dma_addressing(ioc, pdev) != 0) { | |
2346 | pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n", | |
2347 | ioc->name, pci_name(pdev)); | |
2348 | r = -ENODEV; | |
2349 | goto out_fail; | |
2350 | } | |
2351 | ||
5aeeb78a SR |
2352 | for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) && |
2353 | (!memap_sz || !pio_sz); i++) { | |
f92363d1 SR |
2354 | if (pci_resource_flags(pdev, i) & IORESOURCE_IO) { |
2355 | if (pio_sz) | |
2356 | continue; | |
2357 | pio_chip = (u64)pci_resource_start(pdev, i); | |
2358 | pio_sz = pci_resource_len(pdev, i); | |
2359 | } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { | |
2360 | if (memap_sz) | |
2361 | continue; | |
2362 | ioc->chip_phys = pci_resource_start(pdev, i); | |
2363 | chip_phys = (u64)ioc->chip_phys; | |
2364 | memap_sz = pci_resource_len(pdev, i); | |
2365 | ioc->chip = ioremap(ioc->chip_phys, memap_sz); | |
f92363d1 SR |
2366 | } |
2367 | } | |
2368 | ||
5aeeb78a SR |
2369 | if (ioc->chip == NULL) { |
2370 | pr_err(MPT3SAS_FMT "unable to map adapter memory! " | |
2371 | " or resource not found\n", ioc->name); | |
2372 | r = -EINVAL; | |
2373 | goto out_fail; | |
2374 | } | |
2375 | ||
f92363d1 | 2376 | _base_mask_interrupts(ioc); |
9b05c91a | 2377 | |
98c56ad3 | 2378 | r = _base_get_ioc_facts(ioc); |
9b05c91a SR |
2379 | if (r) |
2380 | goto out_fail; | |
2381 | ||
2382 | if (!ioc->rdpq_array_enable_assigned) { | |
2383 | ioc->rdpq_array_enable = ioc->rdpq_array_capable; | |
2384 | ioc->rdpq_array_enable_assigned = 1; | |
2385 | } | |
2386 | ||
f92363d1 SR |
2387 | r = _base_enable_msix(ioc); |
2388 | if (r) | |
2389 | goto out_fail; | |
2390 | ||
fb77bb53 SR |
2391 | /* Use the Combined reply queue feature only for SAS3 C0 & higher |
2392 | * revision HBAs and also only when reply queue count is greater than 8 | |
2393 | */ | |
0bb337c9 | 2394 | if (ioc->combined_reply_queue && ioc->reply_queue_count > 8) { |
fb77bb53 SR |
2395 | /* Determine the Supplemental Reply Post Host Index Registers |
2396 | * Addresse. Supplemental Reply Post Host Index Registers | |
2397 | * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and | |
2398 | * each register is at offset bytes of | |
2399 | * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one. | |
2400 | */ | |
2401 | ioc->replyPostRegisterIndex = kcalloc( | |
0bb337c9 | 2402 | ioc->combined_reply_index_count, |
fb77bb53 SR |
2403 | sizeof(resource_size_t *), GFP_KERNEL); |
2404 | if (!ioc->replyPostRegisterIndex) { | |
2405 | dfailprintk(ioc, printk(MPT3SAS_FMT | |
2406 | "allocation for reply Post Register Index failed!!!\n", | |
2407 | ioc->name)); | |
2408 | r = -ENOMEM; | |
2409 | goto out_fail; | |
2410 | } | |
2411 | ||
0bb337c9 | 2412 | for (i = 0; i < ioc->combined_reply_index_count; i++) { |
fb77bb53 SR |
2413 | ioc->replyPostRegisterIndex[i] = (resource_size_t *) |
2414 | ((u8 *)&ioc->chip->Doorbell + | |
2415 | MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET + | |
2416 | (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET)); | |
2417 | } | |
2418 | } else | |
0bb337c9 | 2419 | ioc->combined_reply_queue = 0; |
fb77bb53 | 2420 | |
ce7c6c9e GE |
2421 | if (ioc->is_warpdrive) { |
2422 | ioc->reply_post_host_index[0] = (resource_size_t __iomem *) | |
2423 | &ioc->chip->ReplyPostHostIndex; | |
2424 | ||
2425 | for (i = 1; i < ioc->cpu_msix_table_sz; i++) | |
2426 | ioc->reply_post_host_index[i] = | |
2427 | (resource_size_t __iomem *) | |
2428 | ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1) | |
2429 | * 4))); | |
2430 | } | |
2431 | ||
f92363d1 SR |
2432 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) |
2433 | pr_info(MPT3SAS_FMT "%s: IRQ %d\n", | |
2434 | reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" : | |
1d55abc0 HR |
2435 | "IO-APIC enabled"), |
2436 | pci_irq_vector(ioc->pdev, reply_q->msix_index)); | |
f92363d1 SR |
2437 | |
2438 | pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n", | |
2439 | ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz); | |
2440 | pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n", | |
2441 | ioc->name, (unsigned long long)pio_chip, pio_sz); | |
2442 | ||
2443 | /* Save PCI configuration state for recovery from PCI AER/EEH errors */ | |
2444 | pci_save_state(pdev); | |
2445 | return 0; | |
2446 | ||
2447 | out_fail: | |
580d4e31 | 2448 | mpt3sas_base_unmap_resources(ioc); |
f92363d1 SR |
2449 | return r; |
2450 | } | |
2451 | ||
2452 | /** | |
2453 | * mpt3sas_base_get_msg_frame - obtain request mf pointer | |
2454 | * @ioc: per adapter object | |
2455 | * @smid: system request message index(smid zero is invalid) | |
2456 | * | |
2457 | * Returns virt pointer to message frame. | |
2458 | */ | |
2459 | void * | |
2460 | mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
2461 | { | |
2462 | return (void *)(ioc->request + (smid * ioc->request_sz)); | |
2463 | } | |
2464 | ||
2465 | /** | |
2466 | * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr | |
2467 | * @ioc: per adapter object | |
2468 | * @smid: system request message index | |
2469 | * | |
2470 | * Returns virt pointer to sense buffer. | |
2471 | */ | |
2472 | void * | |
2473 | mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
2474 | { | |
2475 | return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE)); | |
2476 | } | |
2477 | ||
2478 | /** | |
2479 | * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr | |
2480 | * @ioc: per adapter object | |
2481 | * @smid: system request message index | |
2482 | * | |
2483 | * Returns phys pointer to the low 32bit address of the sense buffer. | |
2484 | */ | |
2485 | __le32 | |
2486 | mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
2487 | { | |
2488 | return cpu_to_le32(ioc->sense_dma + ((smid - 1) * | |
2489 | SCSI_SENSE_BUFFERSIZE)); | |
2490 | } | |
2491 | ||
016d5c35 SPS |
2492 | /** |
2493 | * mpt3sas_base_get_pcie_sgl - obtain a PCIe SGL virt addr | |
2494 | * @ioc: per adapter object | |
2495 | * @smid: system request message index | |
2496 | * | |
2497 | * Returns virt pointer to a PCIe SGL. | |
2498 | */ | |
2499 | void * | |
2500 | mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
2501 | { | |
2502 | return (void *)(ioc->scsi_lookup[smid - 1].pcie_sg_list.pcie_sgl); | |
2503 | } | |
2504 | ||
2505 | /** | |
2506 | * mpt3sas_base_get_pcie_sgl_dma - obtain a PCIe SGL dma addr | |
2507 | * @ioc: per adapter object | |
2508 | * @smid: system request message index | |
2509 | * | |
2510 | * Returns phys pointer to the address of the PCIe buffer. | |
2511 | */ | |
2512 | void * | |
2513 | mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
2514 | { | |
2515 | return (void *)(uintptr_t) | |
2516 | (ioc->scsi_lookup[smid - 1].pcie_sg_list.pcie_sgl_dma); | |
2517 | } | |
2518 | ||
f92363d1 SR |
2519 | /** |
2520 | * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address | |
2521 | * @ioc: per adapter object | |
2522 | * @phys_addr: lower 32 physical addr of the reply | |
2523 | * | |
2524 | * Converts 32bit lower physical addr into a virt address. | |
2525 | */ | |
2526 | void * | |
2527 | mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr) | |
2528 | { | |
2529 | if (!phys_addr) | |
2530 | return NULL; | |
2531 | return ioc->reply + (phys_addr - (u32)ioc->reply_dma); | |
2532 | } | |
2533 | ||
03d1fb3a SS |
2534 | static inline u8 |
2535 | _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc) | |
2536 | { | |
2537 | return ioc->cpu_msix_table[raw_smp_processor_id()]; | |
2538 | } | |
2539 | ||
f92363d1 SR |
2540 | /** |
2541 | * mpt3sas_base_get_smid - obtain a free smid from internal queue | |
2542 | * @ioc: per adapter object | |
2543 | * @cb_idx: callback index | |
2544 | * | |
2545 | * Returns smid (zero is invalid) | |
2546 | */ | |
2547 | u16 | |
2548 | mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) | |
2549 | { | |
2550 | unsigned long flags; | |
2551 | struct request_tracker *request; | |
2552 | u16 smid; | |
2553 | ||
2554 | spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); | |
2555 | if (list_empty(&ioc->internal_free_list)) { | |
2556 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
2557 | pr_err(MPT3SAS_FMT "%s: smid not available\n", | |
2558 | ioc->name, __func__); | |
2559 | return 0; | |
2560 | } | |
2561 | ||
2562 | request = list_entry(ioc->internal_free_list.next, | |
2563 | struct request_tracker, tracker_list); | |
2564 | request->cb_idx = cb_idx; | |
2565 | smid = request->smid; | |
2566 | list_del(&request->tracker_list); | |
2567 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
2568 | return smid; | |
2569 | } | |
2570 | ||
2571 | /** | |
2572 | * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue | |
2573 | * @ioc: per adapter object | |
2574 | * @cb_idx: callback index | |
2575 | * @scmd: pointer to scsi command object | |
2576 | * | |
2577 | * Returns smid (zero is invalid) | |
2578 | */ | |
2579 | u16 | |
2580 | mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx, | |
2581 | struct scsi_cmnd *scmd) | |
2582 | { | |
2583 | unsigned long flags; | |
2584 | struct scsiio_tracker *request; | |
2585 | u16 smid; | |
2586 | ||
2587 | spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); | |
2588 | if (list_empty(&ioc->free_list)) { | |
2589 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
2590 | pr_err(MPT3SAS_FMT "%s: smid not available\n", | |
2591 | ioc->name, __func__); | |
2592 | return 0; | |
2593 | } | |
2594 | ||
2595 | request = list_entry(ioc->free_list.next, | |
2596 | struct scsiio_tracker, tracker_list); | |
2597 | request->scmd = scmd; | |
2598 | request->cb_idx = cb_idx; | |
2599 | smid = request->smid; | |
03d1fb3a | 2600 | request->msix_io = _base_get_msix_index(ioc); |
f92363d1 SR |
2601 | list_del(&request->tracker_list); |
2602 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
2603 | return smid; | |
2604 | } | |
2605 | ||
2606 | /** | |
2607 | * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue | |
2608 | * @ioc: per adapter object | |
2609 | * @cb_idx: callback index | |
2610 | * | |
2611 | * Returns smid (zero is invalid) | |
2612 | */ | |
2613 | u16 | |
2614 | mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) | |
2615 | { | |
2616 | unsigned long flags; | |
2617 | struct request_tracker *request; | |
2618 | u16 smid; | |
2619 | ||
2620 | spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); | |
2621 | if (list_empty(&ioc->hpr_free_list)) { | |
2622 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
2623 | return 0; | |
2624 | } | |
2625 | ||
2626 | request = list_entry(ioc->hpr_free_list.next, | |
2627 | struct request_tracker, tracker_list); | |
2628 | request->cb_idx = cb_idx; | |
2629 | smid = request->smid; | |
2630 | list_del(&request->tracker_list); | |
2631 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
2632 | return smid; | |
2633 | } | |
2634 | ||
2635 | /** | |
2636 | * mpt3sas_base_free_smid - put smid back on free_list | |
2637 | * @ioc: per adapter object | |
2638 | * @smid: system request message index | |
2639 | * | |
2640 | * Return nothing. | |
2641 | */ | |
2642 | void | |
2643 | mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
2644 | { | |
2645 | unsigned long flags; | |
2646 | int i; | |
2647 | struct chain_tracker *chain_req, *next; | |
2648 | ||
2649 | spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); | |
2650 | if (smid < ioc->hi_priority_smid) { | |
2651 | /* scsiio queue */ | |
2652 | i = smid - 1; | |
2653 | if (!list_empty(&ioc->scsi_lookup[i].chain_list)) { | |
2654 | list_for_each_entry_safe(chain_req, next, | |
2655 | &ioc->scsi_lookup[i].chain_list, tracker_list) { | |
2656 | list_del_init(&chain_req->tracker_list); | |
2657 | list_add(&chain_req->tracker_list, | |
2658 | &ioc->free_chain_list); | |
2659 | } | |
2660 | } | |
2661 | ioc->scsi_lookup[i].cb_idx = 0xFF; | |
2662 | ioc->scsi_lookup[i].scmd = NULL; | |
7786ab6a | 2663 | ioc->scsi_lookup[i].direct_io = 0; |
f92363d1 SR |
2664 | list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list); |
2665 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
2666 | ||
2667 | /* | |
2668 | * See _wait_for_commands_to_complete() call with regards | |
2669 | * to this code. | |
2670 | */ | |
2671 | if (ioc->shost_recovery && ioc->pending_io_count) { | |
2672 | if (ioc->pending_io_count == 1) | |
2673 | wake_up(&ioc->reset_wq); | |
2674 | ioc->pending_io_count--; | |
2675 | } | |
2676 | return; | |
2677 | } else if (smid < ioc->internal_smid) { | |
2678 | /* hi-priority */ | |
2679 | i = smid - ioc->hi_priority_smid; | |
2680 | ioc->hpr_lookup[i].cb_idx = 0xFF; | |
2681 | list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list); | |
2682 | } else if (smid <= ioc->hba_queue_depth) { | |
2683 | /* internal queue */ | |
2684 | i = smid - ioc->internal_smid; | |
2685 | ioc->internal_lookup[i].cb_idx = 0xFF; | |
2686 | list_add(&ioc->internal_lookup[i].tracker_list, | |
2687 | &ioc->internal_free_list); | |
2688 | } | |
2689 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
2690 | } | |
2691 | ||
2692 | /** | |
2693 | * _base_writeq - 64 bit write to MMIO | |
2694 | * @ioc: per adapter object | |
2695 | * @b: data payload | |
2696 | * @addr: address in MMIO space | |
2697 | * @writeq_lock: spin lock | |
2698 | * | |
2699 | * Glue for handling an atomic 64 bit word to MMIO. This special handling takes | |
2700 | * care of 32 bit environment where its not quarenteed to send the entire word | |
2701 | * in one transfer. | |
2702 | */ | |
2703 | #if defined(writeq) && defined(CONFIG_64BIT) | |
2704 | static inline void | |
2705 | _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) | |
2706 | { | |
2707 | writeq(cpu_to_le64(b), addr); | |
2708 | } | |
2709 | #else | |
2710 | static inline void | |
2711 | _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) | |
2712 | { | |
2713 | unsigned long flags; | |
2714 | __u64 data_out = cpu_to_le64(b); | |
2715 | ||
2716 | spin_lock_irqsave(writeq_lock, flags); | |
2717 | writel((u32)(data_out), addr); | |
2718 | writel((u32)(data_out >> 32), (addr + 4)); | |
2719 | spin_unlock_irqrestore(writeq_lock, flags); | |
2720 | } | |
2721 | #endif | |
2722 | ||
f92363d1 | 2723 | /** |
81c16f83 | 2724 | * _base_put_smid_scsi_io - send SCSI_IO request to firmware |
f92363d1 SR |
2725 | * @ioc: per adapter object |
2726 | * @smid: system request message index | |
2727 | * @handle: device handle | |
2728 | * | |
2729 | * Return nothing. | |
2730 | */ | |
81c16f83 SPS |
2731 | static void |
2732 | _base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle) | |
f92363d1 SR |
2733 | { |
2734 | Mpi2RequestDescriptorUnion_t descriptor; | |
2735 | u64 *request = (u64 *)&descriptor; | |
2736 | ||
2737 | ||
2738 | descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; | |
2739 | descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc); | |
2740 | descriptor.SCSIIO.SMID = cpu_to_le16(smid); | |
2741 | descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); | |
2742 | descriptor.SCSIIO.LMID = 0; | |
2743 | _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, | |
2744 | &ioc->scsi_lookup_lock); | |
2745 | } | |
2746 | ||
2747 | /** | |
81c16f83 | 2748 | * _base_put_smid_fast_path - send fast path request to firmware |
f92363d1 SR |
2749 | * @ioc: per adapter object |
2750 | * @smid: system request message index | |
2751 | * @handle: device handle | |
2752 | * | |
2753 | * Return nothing. | |
2754 | */ | |
81c16f83 SPS |
2755 | static void |
2756 | _base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid, | |
f92363d1 SR |
2757 | u16 handle) |
2758 | { | |
2759 | Mpi2RequestDescriptorUnion_t descriptor; | |
2760 | u64 *request = (u64 *)&descriptor; | |
2761 | ||
2762 | descriptor.SCSIIO.RequestFlags = | |
2763 | MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; | |
2764 | descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc); | |
2765 | descriptor.SCSIIO.SMID = cpu_to_le16(smid); | |
2766 | descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); | |
2767 | descriptor.SCSIIO.LMID = 0; | |
2768 | _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, | |
2769 | &ioc->scsi_lookup_lock); | |
2770 | } | |
2771 | ||
2772 | /** | |
81c16f83 | 2773 | * _base_put_smid_hi_priority - send Task Management request to firmware |
f92363d1 SR |
2774 | * @ioc: per adapter object |
2775 | * @smid: system request message index | |
03d1fb3a | 2776 | * @msix_task: msix_task will be same as msix of IO incase of task abort else 0. |
f92363d1 SR |
2777 | * Return nothing. |
2778 | */ | |
81c16f83 SPS |
2779 | static void |
2780 | _base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid, | |
03d1fb3a | 2781 | u16 msix_task) |
f92363d1 SR |
2782 | { |
2783 | Mpi2RequestDescriptorUnion_t descriptor; | |
2784 | u64 *request = (u64 *)&descriptor; | |
2785 | ||
2786 | descriptor.HighPriority.RequestFlags = | |
2787 | MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; | |
03d1fb3a | 2788 | descriptor.HighPriority.MSIxIndex = msix_task; |
f92363d1 SR |
2789 | descriptor.HighPriority.SMID = cpu_to_le16(smid); |
2790 | descriptor.HighPriority.LMID = 0; | |
2791 | descriptor.HighPriority.Reserved1 = 0; | |
2792 | _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, | |
2793 | &ioc->scsi_lookup_lock); | |
2794 | } | |
2795 | ||
2796 | /** | |
81c16f83 | 2797 | * _base_put_smid_default - Default, primarily used for config pages |
f92363d1 SR |
2798 | * @ioc: per adapter object |
2799 | * @smid: system request message index | |
2800 | * | |
2801 | * Return nothing. | |
2802 | */ | |
81c16f83 SPS |
2803 | static void |
2804 | _base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
f92363d1 SR |
2805 | { |
2806 | Mpi2RequestDescriptorUnion_t descriptor; | |
2807 | u64 *request = (u64 *)&descriptor; | |
2808 | ||
2809 | descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; | |
2810 | descriptor.Default.MSIxIndex = _base_get_msix_index(ioc); | |
2811 | descriptor.Default.SMID = cpu_to_le16(smid); | |
2812 | descriptor.Default.LMID = 0; | |
2813 | descriptor.Default.DescriptorTypeDependent = 0; | |
2814 | _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, | |
2815 | &ioc->scsi_lookup_lock); | |
2816 | } | |
2817 | ||
81c16f83 SPS |
2818 | /** |
2819 | * _base_put_smid_scsi_io_atomic - send SCSI_IO request to firmware using | |
2820 | * Atomic Request Descriptor | |
2821 | * @ioc: per adapter object | |
2822 | * @smid: system request message index | |
2823 | * @handle: device handle, unused in this function, for function type match | |
2824 | * | |
2825 | * Return nothing. | |
2826 | */ | |
2827 | static void | |
2828 | _base_put_smid_scsi_io_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, | |
2829 | u16 handle) | |
2830 | { | |
2831 | Mpi26AtomicRequestDescriptor_t descriptor; | |
2832 | u32 *request = (u32 *)&descriptor; | |
2833 | ||
2834 | descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; | |
2835 | descriptor.MSIxIndex = _base_get_msix_index(ioc); | |
2836 | descriptor.SMID = cpu_to_le16(smid); | |
2837 | ||
2838 | writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); | |
2839 | } | |
2840 | ||
2841 | /** | |
2842 | * _base_put_smid_fast_path_atomic - send fast path request to firmware | |
2843 | * using Atomic Request Descriptor | |
2844 | * @ioc: per adapter object | |
2845 | * @smid: system request message index | |
2846 | * @handle: device handle, unused in this function, for function type match | |
2847 | * Return nothing | |
2848 | */ | |
2849 | static void | |
2850 | _base_put_smid_fast_path_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, | |
2851 | u16 handle) | |
2852 | { | |
2853 | Mpi26AtomicRequestDescriptor_t descriptor; | |
2854 | u32 *request = (u32 *)&descriptor; | |
2855 | ||
2856 | descriptor.RequestFlags = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; | |
2857 | descriptor.MSIxIndex = _base_get_msix_index(ioc); | |
2858 | descriptor.SMID = cpu_to_le16(smid); | |
2859 | ||
2860 | writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); | |
2861 | } | |
2862 | ||
2863 | /** | |
2864 | * _base_put_smid_hi_priority_atomic - send Task Management request to | |
2865 | * firmware using Atomic Request Descriptor | |
2866 | * @ioc: per adapter object | |
2867 | * @smid: system request message index | |
2868 | * @msix_task: msix_task will be same as msix of IO incase of task abort else 0 | |
2869 | * | |
2870 | * Return nothing. | |
2871 | */ | |
2872 | static void | |
2873 | _base_put_smid_hi_priority_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, | |
2874 | u16 msix_task) | |
2875 | { | |
2876 | Mpi26AtomicRequestDescriptor_t descriptor; | |
2877 | u32 *request = (u32 *)&descriptor; | |
2878 | ||
2879 | descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; | |
2880 | descriptor.MSIxIndex = msix_task; | |
2881 | descriptor.SMID = cpu_to_le16(smid); | |
2882 | ||
2883 | writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); | |
2884 | } | |
2885 | ||
2886 | /** | |
2887 | * _base_put_smid_default - Default, primarily used for config pages | |
2888 | * use Atomic Request Descriptor | |
2889 | * @ioc: per adapter object | |
2890 | * @smid: system request message index | |
2891 | * | |
2892 | * Return nothing. | |
2893 | */ | |
2894 | static void | |
2895 | _base_put_smid_default_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
2896 | { | |
2897 | Mpi26AtomicRequestDescriptor_t descriptor; | |
2898 | u32 *request = (u32 *)&descriptor; | |
2899 | ||
2900 | descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; | |
2901 | descriptor.MSIxIndex = _base_get_msix_index(ioc); | |
2902 | descriptor.SMID = cpu_to_le16(smid); | |
2903 | ||
2904 | writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); | |
2905 | } | |
2906 | ||
1117b31a | 2907 | /** |
989e43c7 | 2908 | * _base_display_OEMs_branding - Display branding string |
1117b31a SR |
2909 | * @ioc: per adapter object |
2910 | * | |
2911 | * Return nothing. | |
2912 | */ | |
2913 | static void | |
989e43c7 | 2914 | _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc) |
1117b31a SR |
2915 | { |
2916 | if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL) | |
2917 | return; | |
2918 | ||
989e43c7 SR |
2919 | switch (ioc->pdev->subsystem_vendor) { |
2920 | case PCI_VENDOR_ID_INTEL: | |
2921 | switch (ioc->pdev->device) { | |
2922 | case MPI2_MFGPAGE_DEVID_SAS2008: | |
2923 | switch (ioc->pdev->subsystem_device) { | |
2924 | case MPT2SAS_INTEL_RMS2LL080_SSDID: | |
2925 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
2926 | MPT2SAS_INTEL_RMS2LL080_BRANDING); | |
2927 | break; | |
2928 | case MPT2SAS_INTEL_RMS2LL040_SSDID: | |
2929 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
2930 | MPT2SAS_INTEL_RMS2LL040_BRANDING); | |
2931 | break; | |
2932 | case MPT2SAS_INTEL_SSD910_SSDID: | |
2933 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
2934 | MPT2SAS_INTEL_SSD910_BRANDING); | |
2935 | break; | |
2936 | default: | |
2937 | pr_info(MPT3SAS_FMT | |
2938 | "Intel(R) Controller: Subsystem ID: 0x%X\n", | |
2939 | ioc->name, ioc->pdev->subsystem_device); | |
2940 | break; | |
2941 | } | |
2942 | case MPI2_MFGPAGE_DEVID_SAS2308_2: | |
2943 | switch (ioc->pdev->subsystem_device) { | |
2944 | case MPT2SAS_INTEL_RS25GB008_SSDID: | |
2945 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
2946 | MPT2SAS_INTEL_RS25GB008_BRANDING); | |
2947 | break; | |
2948 | case MPT2SAS_INTEL_RMS25JB080_SSDID: | |
2949 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
2950 | MPT2SAS_INTEL_RMS25JB080_BRANDING); | |
2951 | break; | |
2952 | case MPT2SAS_INTEL_RMS25JB040_SSDID: | |
2953 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
2954 | MPT2SAS_INTEL_RMS25JB040_BRANDING); | |
2955 | break; | |
2956 | case MPT2SAS_INTEL_RMS25KB080_SSDID: | |
2957 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
2958 | MPT2SAS_INTEL_RMS25KB080_BRANDING); | |
2959 | break; | |
2960 | case MPT2SAS_INTEL_RMS25KB040_SSDID: | |
2961 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
2962 | MPT2SAS_INTEL_RMS25KB040_BRANDING); | |
2963 | break; | |
2964 | case MPT2SAS_INTEL_RMS25LB040_SSDID: | |
2965 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
2966 | MPT2SAS_INTEL_RMS25LB040_BRANDING); | |
2967 | break; | |
2968 | case MPT2SAS_INTEL_RMS25LB080_SSDID: | |
2969 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
2970 | MPT2SAS_INTEL_RMS25LB080_BRANDING); | |
2971 | break; | |
2972 | default: | |
2973 | pr_info(MPT3SAS_FMT | |
2974 | "Intel(R) Controller: Subsystem ID: 0x%X\n", | |
2975 | ioc->name, ioc->pdev->subsystem_device); | |
2976 | break; | |
2977 | } | |
2978 | case MPI25_MFGPAGE_DEVID_SAS3008: | |
2979 | switch (ioc->pdev->subsystem_device) { | |
2980 | case MPT3SAS_INTEL_RMS3JC080_SSDID: | |
2981 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
2982 | MPT3SAS_INTEL_RMS3JC080_BRANDING); | |
2983 | break; | |
2984 | ||
2985 | case MPT3SAS_INTEL_RS3GC008_SSDID: | |
2986 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
2987 | MPT3SAS_INTEL_RS3GC008_BRANDING); | |
2988 | break; | |
2989 | case MPT3SAS_INTEL_RS3FC044_SSDID: | |
2990 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
2991 | MPT3SAS_INTEL_RS3FC044_BRANDING); | |
2992 | break; | |
2993 | case MPT3SAS_INTEL_RS3UC080_SSDID: | |
2994 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
2995 | MPT3SAS_INTEL_RS3UC080_BRANDING); | |
2996 | break; | |
2997 | default: | |
2998 | pr_info(MPT3SAS_FMT | |
2999 | "Intel(R) Controller: Subsystem ID: 0x%X\n", | |
3000 | ioc->name, ioc->pdev->subsystem_device); | |
3001 | break; | |
3002 | } | |
1117b31a SR |
3003 | break; |
3004 | default: | |
3005 | pr_info(MPT3SAS_FMT | |
989e43c7 SR |
3006 | "Intel(R) Controller: Subsystem ID: 0x%X\n", |
3007 | ioc->name, ioc->pdev->subsystem_device); | |
1117b31a SR |
3008 | break; |
3009 | } | |
3010 | break; | |
989e43c7 SR |
3011 | case PCI_VENDOR_ID_DELL: |
3012 | switch (ioc->pdev->device) { | |
3013 | case MPI2_MFGPAGE_DEVID_SAS2008: | |
3014 | switch (ioc->pdev->subsystem_device) { | |
3015 | case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID: | |
3016 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3017 | MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING); | |
3018 | break; | |
3019 | case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID: | |
3020 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3021 | MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING); | |
3022 | break; | |
3023 | case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID: | |
3024 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3025 | MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING); | |
3026 | break; | |
3027 | case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID: | |
3028 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3029 | MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING); | |
3030 | break; | |
3031 | case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID: | |
3032 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3033 | MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING); | |
3034 | break; | |
3035 | case MPT2SAS_DELL_PERC_H200_SSDID: | |
3036 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3037 | MPT2SAS_DELL_PERC_H200_BRANDING); | |
3038 | break; | |
3039 | case MPT2SAS_DELL_6GBPS_SAS_SSDID: | |
3040 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3041 | MPT2SAS_DELL_6GBPS_SAS_BRANDING); | |
3042 | break; | |
3043 | default: | |
3044 | pr_info(MPT3SAS_FMT | |
3045 | "Dell 6Gbps HBA: Subsystem ID: 0x%X\n", | |
3046 | ioc->name, ioc->pdev->subsystem_device); | |
3047 | break; | |
3048 | } | |
3049 | break; | |
3050 | case MPI25_MFGPAGE_DEVID_SAS3008: | |
3051 | switch (ioc->pdev->subsystem_device) { | |
3052 | case MPT3SAS_DELL_12G_HBA_SSDID: | |
3053 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3054 | MPT3SAS_DELL_12G_HBA_BRANDING); | |
3055 | break; | |
3056 | default: | |
3057 | pr_info(MPT3SAS_FMT | |
3058 | "Dell 12Gbps HBA: Subsystem ID: 0x%X\n", | |
3059 | ioc->name, ioc->pdev->subsystem_device); | |
3060 | break; | |
3061 | } | |
fb84dfc4 SR |
3062 | break; |
3063 | default: | |
3064 | pr_info(MPT3SAS_FMT | |
989e43c7 | 3065 | "Dell HBA: Subsystem ID: 0x%X\n", ioc->name, |
fb84dfc4 SR |
3066 | ioc->pdev->subsystem_device); |
3067 | break; | |
3068 | } | |
3069 | break; | |
989e43c7 SR |
3070 | case PCI_VENDOR_ID_CISCO: |
3071 | switch (ioc->pdev->device) { | |
3072 | case MPI25_MFGPAGE_DEVID_SAS3008: | |
3073 | switch (ioc->pdev->subsystem_device) { | |
3074 | case MPT3SAS_CISCO_12G_8E_HBA_SSDID: | |
3075 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3076 | MPT3SAS_CISCO_12G_8E_HBA_BRANDING); | |
3077 | break; | |
3078 | case MPT3SAS_CISCO_12G_8I_HBA_SSDID: | |
3079 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3080 | MPT3SAS_CISCO_12G_8I_HBA_BRANDING); | |
3081 | break; | |
3082 | case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: | |
3083 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3084 | MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); | |
3085 | break; | |
3086 | default: | |
3087 | pr_info(MPT3SAS_FMT | |
3088 | "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", | |
3089 | ioc->name, ioc->pdev->subsystem_device); | |
3090 | break; | |
3091 | } | |
d8eb4a47 | 3092 | break; |
989e43c7 SR |
3093 | case MPI25_MFGPAGE_DEVID_SAS3108_1: |
3094 | switch (ioc->pdev->subsystem_device) { | |
3095 | case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: | |
3096 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
d8eb4a47 | 3097 | MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); |
989e43c7 SR |
3098 | break; |
3099 | case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID: | |
3100 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3101 | MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING | |
3102 | ); | |
3103 | break; | |
3104 | default: | |
3105 | pr_info(MPT3SAS_FMT | |
3106 | "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", | |
3107 | ioc->name, ioc->pdev->subsystem_device); | |
3108 | break; | |
3109 | } | |
38e4141e SR |
3110 | break; |
3111 | default: | |
3112 | pr_info(MPT3SAS_FMT | |
989e43c7 SR |
3113 | "Cisco SAS HBA: Subsystem ID: 0x%X\n", |
3114 | ioc->name, ioc->pdev->subsystem_device); | |
38e4141e SR |
3115 | break; |
3116 | } | |
3117 | break; | |
989e43c7 SR |
3118 | case MPT2SAS_HP_3PAR_SSVID: |
3119 | switch (ioc->pdev->device) { | |
3120 | case MPI2_MFGPAGE_DEVID_SAS2004: | |
3121 | switch (ioc->pdev->subsystem_device) { | |
3122 | case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID: | |
3123 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3124 | MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING); | |
3125 | break; | |
3126 | default: | |
3127 | pr_info(MPT3SAS_FMT | |
3128 | "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", | |
3129 | ioc->name, ioc->pdev->subsystem_device); | |
3130 | break; | |
3131 | } | |
3132 | case MPI2_MFGPAGE_DEVID_SAS2308_2: | |
3133 | switch (ioc->pdev->subsystem_device) { | |
3134 | case MPT2SAS_HP_2_4_INTERNAL_SSDID: | |
3135 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3136 | MPT2SAS_HP_2_4_INTERNAL_BRANDING); | |
3137 | break; | |
3138 | case MPT2SAS_HP_2_4_EXTERNAL_SSDID: | |
3139 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3140 | MPT2SAS_HP_2_4_EXTERNAL_BRANDING); | |
3141 | break; | |
3142 | case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID: | |
3143 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3144 | MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING); | |
3145 | break; | |
3146 | case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID: | |
3147 | pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3148 | MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING); | |
3149 | break; | |
3150 | default: | |
3151 | pr_info(MPT3SAS_FMT | |
3152 | "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", | |
3153 | ioc->name, ioc->pdev->subsystem_device); | |
3154 | break; | |
3155 | } | |
d8eb4a47 SR |
3156 | default: |
3157 | pr_info(MPT3SAS_FMT | |
989e43c7 SR |
3158 | "HP SAS HBA: Subsystem ID: 0x%X\n", |
3159 | ioc->name, ioc->pdev->subsystem_device); | |
d8eb4a47 SR |
3160 | break; |
3161 | } | |
38e4141e | 3162 | default: |
38e4141e SR |
3163 | break; |
3164 | } | |
3165 | } | |
fb84dfc4 | 3166 | |
f92363d1 SR |
3167 | /** |
3168 | * _base_display_ioc_capabilities - Disply IOC's capabilities. | |
3169 | * @ioc: per adapter object | |
3170 | * | |
3171 | * Return nothing. | |
3172 | */ | |
3173 | static void | |
3174 | _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc) | |
3175 | { | |
3176 | int i = 0; | |
3177 | char desc[16]; | |
3178 | u32 iounit_pg1_flags; | |
3179 | u32 bios_version; | |
3180 | ||
3181 | bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion); | |
3182 | strncpy(desc, ioc->manu_pg0.ChipName, 16); | |
3183 | pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\ | |
3184 | "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n", | |
3185 | ioc->name, desc, | |
3186 | (ioc->facts.FWVersion.Word & 0xFF000000) >> 24, | |
3187 | (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16, | |
3188 | (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8, | |
3189 | ioc->facts.FWVersion.Word & 0x000000FF, | |
3190 | ioc->pdev->revision, | |
3191 | (bios_version & 0xFF000000) >> 24, | |
3192 | (bios_version & 0x00FF0000) >> 16, | |
3193 | (bios_version & 0x0000FF00) >> 8, | |
3194 | bios_version & 0x000000FF); | |
3195 | ||
989e43c7 | 3196 | _base_display_OEMs_branding(ioc); |
1117b31a | 3197 | |
016d5c35 SPS |
3198 | if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) { |
3199 | pr_info("%sNVMe", i ? "," : ""); | |
3200 | i++; | |
3201 | } | |
3202 | ||
f92363d1 SR |
3203 | pr_info(MPT3SAS_FMT "Protocol=(", ioc->name); |
3204 | ||
3205 | if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) { | |
3206 | pr_info("Initiator"); | |
3207 | i++; | |
3208 | } | |
3209 | ||
3210 | if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) { | |
3211 | pr_info("%sTarget", i ? "," : ""); | |
3212 | i++; | |
3213 | } | |
3214 | ||
3215 | i = 0; | |
3216 | pr_info("), "); | |
3217 | pr_info("Capabilities=("); | |
3218 | ||
7786ab6a SR |
3219 | if (!ioc->hide_ir_msg) { |
3220 | if (ioc->facts.IOCCapabilities & | |
f92363d1 SR |
3221 | MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) { |
3222 | pr_info("Raid"); | |
3223 | i++; | |
7786ab6a | 3224 | } |
f92363d1 SR |
3225 | } |
3226 | ||
3227 | if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) { | |
3228 | pr_info("%sTLR", i ? "," : ""); | |
3229 | i++; | |
3230 | } | |
3231 | ||
3232 | if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) { | |
3233 | pr_info("%sMulticast", i ? "," : ""); | |
3234 | i++; | |
3235 | } | |
3236 | ||
3237 | if (ioc->facts.IOCCapabilities & | |
3238 | MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) { | |
3239 | pr_info("%sBIDI Target", i ? "," : ""); | |
3240 | i++; | |
3241 | } | |
3242 | ||
3243 | if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) { | |
3244 | pr_info("%sEEDP", i ? "," : ""); | |
3245 | i++; | |
3246 | } | |
3247 | ||
3248 | if (ioc->facts.IOCCapabilities & | |
3249 | MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) { | |
3250 | pr_info("%sSnapshot Buffer", i ? "," : ""); | |
3251 | i++; | |
3252 | } | |
3253 | ||
3254 | if (ioc->facts.IOCCapabilities & | |
3255 | MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) { | |
3256 | pr_info("%sDiag Trace Buffer", i ? "," : ""); | |
3257 | i++; | |
3258 | } | |
3259 | ||
3260 | if (ioc->facts.IOCCapabilities & | |
3261 | MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) { | |
3262 | pr_info("%sDiag Extended Buffer", i ? "," : ""); | |
3263 | i++; | |
3264 | } | |
3265 | ||
3266 | if (ioc->facts.IOCCapabilities & | |
3267 | MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) { | |
3268 | pr_info("%sTask Set Full", i ? "," : ""); | |
3269 | i++; | |
3270 | } | |
3271 | ||
3272 | iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); | |
3273 | if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) { | |
3274 | pr_info("%sNCQ", i ? "," : ""); | |
3275 | i++; | |
3276 | } | |
3277 | ||
3278 | pr_info(")\n"); | |
3279 | } | |
3280 | ||
3281 | /** | |
3282 | * mpt3sas_base_update_missing_delay - change the missing delay timers | |
3283 | * @ioc: per adapter object | |
3284 | * @device_missing_delay: amount of time till device is reported missing | |
3285 | * @io_missing_delay: interval IO is returned when there is a missing device | |
3286 | * | |
3287 | * Return nothing. | |
3288 | * | |
3289 | * Passed on the command line, this function will modify the device missing | |
3290 | * delay, as well as the io missing delay. This should be called at driver | |
3291 | * load time. | |
3292 | */ | |
3293 | void | |
3294 | mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc, | |
3295 | u16 device_missing_delay, u8 io_missing_delay) | |
3296 | { | |
3297 | u16 dmd, dmd_new, dmd_orignal; | |
3298 | u8 io_missing_delay_original; | |
3299 | u16 sz; | |
3300 | Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL; | |
3301 | Mpi2ConfigReply_t mpi_reply; | |
3302 | u8 num_phys = 0; | |
3303 | u16 ioc_status; | |
3304 | ||
3305 | mpt3sas_config_get_number_hba_phys(ioc, &num_phys); | |
3306 | if (!num_phys) | |
3307 | return; | |
3308 | ||
3309 | sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys * | |
3310 | sizeof(Mpi2SasIOUnit1PhyData_t)); | |
3311 | sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL); | |
3312 | if (!sas_iounit_pg1) { | |
3313 | pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", | |
3314 | ioc->name, __FILE__, __LINE__, __func__); | |
3315 | goto out; | |
3316 | } | |
3317 | if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply, | |
3318 | sas_iounit_pg1, sz))) { | |
3319 | pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", | |
3320 | ioc->name, __FILE__, __LINE__, __func__); | |
3321 | goto out; | |
3322 | } | |
3323 | ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & | |
3324 | MPI2_IOCSTATUS_MASK; | |
3325 | if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { | |
3326 | pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", | |
3327 | ioc->name, __FILE__, __LINE__, __func__); | |
3328 | goto out; | |
3329 | } | |
3330 | ||
3331 | /* device missing delay */ | |
3332 | dmd = sas_iounit_pg1->ReportDeviceMissingDelay; | |
3333 | if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) | |
3334 | dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; | |
3335 | else | |
3336 | dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; | |
3337 | dmd_orignal = dmd; | |
3338 | if (device_missing_delay > 0x7F) { | |
3339 | dmd = (device_missing_delay > 0x7F0) ? 0x7F0 : | |
3340 | device_missing_delay; | |
3341 | dmd = dmd / 16; | |
3342 | dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16; | |
3343 | } else | |
3344 | dmd = device_missing_delay; | |
3345 | sas_iounit_pg1->ReportDeviceMissingDelay = dmd; | |
3346 | ||
3347 | /* io missing delay */ | |
3348 | io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay; | |
3349 | sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay; | |
3350 | ||
3351 | if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1, | |
3352 | sz)) { | |
3353 | if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) | |
3354 | dmd_new = (dmd & | |
3355 | MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; | |
3356 | else | |
3357 | dmd_new = | |
3358 | dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; | |
3359 | pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n", | |
3360 | ioc->name, dmd_orignal, dmd_new); | |
3361 | pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n", | |
3362 | ioc->name, io_missing_delay_original, | |
3363 | io_missing_delay); | |
3364 | ioc->device_missing_delay = dmd_new; | |
3365 | ioc->io_missing_delay = io_missing_delay; | |
3366 | } | |
3367 | ||
3368 | out: | |
3369 | kfree(sas_iounit_pg1); | |
3370 | } | |
3371 | /** | |
3372 | * _base_static_config_pages - static start of day config pages | |
3373 | * @ioc: per adapter object | |
3374 | * | |
3375 | * Return nothing. | |
3376 | */ | |
3377 | static void | |
3378 | _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc) | |
3379 | { | |
3380 | Mpi2ConfigReply_t mpi_reply; | |
3381 | u32 iounit_pg1_flags; | |
3382 | ||
3383 | mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0); | |
3384 | if (ioc->ir_firmware) | |
3385 | mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply, | |
3386 | &ioc->manu_pg10); | |
3387 | ||
3388 | /* | |
3389 | * Ensure correct T10 PI operation if vendor left EEDPTagMode | |
3390 | * flag unset in NVDATA. | |
3391 | */ | |
3392 | mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11); | |
3393 | if (ioc->manu_pg11.EEDPTagMode == 0) { | |
3394 | pr_err("%s: overriding NVDATA EEDPTagMode setting\n", | |
3395 | ioc->name); | |
3396 | ioc->manu_pg11.EEDPTagMode &= ~0x3; | |
3397 | ioc->manu_pg11.EEDPTagMode |= 0x1; | |
3398 | mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply, | |
3399 | &ioc->manu_pg11); | |
3400 | } | |
3401 | ||
3402 | mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2); | |
3403 | mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3); | |
3404 | mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8); | |
3405 | mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0); | |
3406 | mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); | |
2d8ce8c9 | 3407 | mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8); |
f92363d1 SR |
3408 | _base_display_ioc_capabilities(ioc); |
3409 | ||
3410 | /* | |
3411 | * Enable task_set_full handling in iounit_pg1 when the | |
3412 | * facts capabilities indicate that its supported. | |
3413 | */ | |
3414 | iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); | |
3415 | if ((ioc->facts.IOCCapabilities & | |
3416 | MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING)) | |
3417 | iounit_pg1_flags &= | |
3418 | ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; | |
3419 | else | |
3420 | iounit_pg1_flags |= | |
3421 | MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; | |
3422 | ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags); | |
3423 | mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); | |
2d8ce8c9 SR |
3424 | |
3425 | if (ioc->iounit_pg8.NumSensors) | |
3426 | ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors; | |
f92363d1 SR |
3427 | } |
3428 | ||
3429 | /** | |
3430 | * _base_release_memory_pools - release memory | |
3431 | * @ioc: per adapter object | |
3432 | * | |
3433 | * Free memory allocated from _base_allocate_memory_pools. | |
3434 | * | |
3435 | * Return nothing. | |
3436 | */ | |
3437 | static void | |
3438 | _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) | |
3439 | { | |
9b05c91a SR |
3440 | int i = 0; |
3441 | struct reply_post_struct *rps; | |
f92363d1 SR |
3442 | |
3443 | dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3444 | __func__)); | |
3445 | ||
3446 | if (ioc->request) { | |
3447 | pci_free_consistent(ioc->pdev, ioc->request_dma_sz, | |
3448 | ioc->request, ioc->request_dma); | |
3449 | dexitprintk(ioc, pr_info(MPT3SAS_FMT | |
3450 | "request_pool(0x%p): free\n", | |
3451 | ioc->name, ioc->request)); | |
3452 | ioc->request = NULL; | |
3453 | } | |
3454 | ||
3455 | if (ioc->sense) { | |
e9d98418 RP |
3456 | dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma); |
3457 | dma_pool_destroy(ioc->sense_dma_pool); | |
f92363d1 SR |
3458 | dexitprintk(ioc, pr_info(MPT3SAS_FMT |
3459 | "sense_pool(0x%p): free\n", | |
3460 | ioc->name, ioc->sense)); | |
3461 | ioc->sense = NULL; | |
3462 | } | |
3463 | ||
3464 | if (ioc->reply) { | |
e9d98418 RP |
3465 | dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma); |
3466 | dma_pool_destroy(ioc->reply_dma_pool); | |
f92363d1 SR |
3467 | dexitprintk(ioc, pr_info(MPT3SAS_FMT |
3468 | "reply_pool(0x%p): free\n", | |
3469 | ioc->name, ioc->reply)); | |
3470 | ioc->reply = NULL; | |
3471 | } | |
3472 | ||
3473 | if (ioc->reply_free) { | |
e9d98418 | 3474 | dma_pool_free(ioc->reply_free_dma_pool, ioc->reply_free, |
f92363d1 | 3475 | ioc->reply_free_dma); |
e9d98418 | 3476 | dma_pool_destroy(ioc->reply_free_dma_pool); |
f92363d1 SR |
3477 | dexitprintk(ioc, pr_info(MPT3SAS_FMT |
3478 | "reply_free_pool(0x%p): free\n", | |
3479 | ioc->name, ioc->reply_free)); | |
3480 | ioc->reply_free = NULL; | |
3481 | } | |
3482 | ||
9b05c91a SR |
3483 | if (ioc->reply_post) { |
3484 | do { | |
3485 | rps = &ioc->reply_post[i]; | |
3486 | if (rps->reply_post_free) { | |
e9d98418 | 3487 | dma_pool_free( |
9b05c91a SR |
3488 | ioc->reply_post_free_dma_pool, |
3489 | rps->reply_post_free, | |
3490 | rps->reply_post_free_dma); | |
3491 | dexitprintk(ioc, pr_info(MPT3SAS_FMT | |
3492 | "reply_post_free_pool(0x%p): free\n", | |
3493 | ioc->name, rps->reply_post_free)); | |
3494 | rps->reply_post_free = NULL; | |
3495 | } | |
3496 | } while (ioc->rdpq_array_enable && | |
3497 | (++i < ioc->reply_queue_count)); | |
3498 | ||
e9d98418 | 3499 | dma_pool_destroy(ioc->reply_post_free_dma_pool); |
9b05c91a | 3500 | kfree(ioc->reply_post); |
f92363d1 SR |
3501 | } |
3502 | ||
016d5c35 SPS |
3503 | if (ioc->pcie_sgl_dma_pool) { |
3504 | for (i = 0; i < ioc->scsiio_depth; i++) { | |
3505 | if (ioc->scsi_lookup[i].pcie_sg_list.pcie_sgl) | |
3506 | pci_pool_free(ioc->pcie_sgl_dma_pool, | |
3507 | ioc->scsi_lookup[i].pcie_sg_list.pcie_sgl, | |
3508 | ioc->scsi_lookup[i].pcie_sg_list.pcie_sgl_dma); | |
3509 | } | |
3510 | if (ioc->pcie_sgl_dma_pool) | |
3511 | pci_pool_destroy(ioc->pcie_sgl_dma_pool); | |
3512 | } | |
3513 | ||
f92363d1 SR |
3514 | if (ioc->config_page) { |
3515 | dexitprintk(ioc, pr_info(MPT3SAS_FMT | |
3516 | "config_page(0x%p): free\n", ioc->name, | |
3517 | ioc->config_page)); | |
3518 | pci_free_consistent(ioc->pdev, ioc->config_page_sz, | |
3519 | ioc->config_page, ioc->config_page_dma); | |
3520 | } | |
3521 | ||
3522 | if (ioc->scsi_lookup) { | |
3523 | free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages); | |
3524 | ioc->scsi_lookup = NULL; | |
3525 | } | |
3526 | kfree(ioc->hpr_lookup); | |
3527 | kfree(ioc->internal_lookup); | |
3528 | if (ioc->chain_lookup) { | |
3529 | for (i = 0; i < ioc->chain_depth; i++) { | |
3530 | if (ioc->chain_lookup[i].chain_buffer) | |
e9d98418 | 3531 | dma_pool_free(ioc->chain_dma_pool, |
f92363d1 SR |
3532 | ioc->chain_lookup[i].chain_buffer, |
3533 | ioc->chain_lookup[i].chain_buffer_dma); | |
3534 | } | |
e9d98418 | 3535 | dma_pool_destroy(ioc->chain_dma_pool); |
f92363d1 SR |
3536 | free_pages((ulong)ioc->chain_lookup, ioc->chain_pages); |
3537 | ioc->chain_lookup = NULL; | |
3538 | } | |
3539 | } | |
3540 | ||
3541 | /** | |
3542 | * _base_allocate_memory_pools - allocate start of day memory pools | |
3543 | * @ioc: per adapter object | |
f92363d1 SR |
3544 | * |
3545 | * Returns 0 success, anything else error | |
3546 | */ | |
3547 | static int | |
98c56ad3 | 3548 | _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
3549 | { |
3550 | struct mpt3sas_facts *facts; | |
3551 | u16 max_sge_elements; | |
3552 | u16 chains_needed_per_io; | |
3553 | u32 sz, total_sz, reply_post_free_sz; | |
3554 | u32 retry_sz; | |
016d5c35 | 3555 | u16 max_request_credit, nvme_blocks_needed; |
f92363d1 SR |
3556 | unsigned short sg_tablesize; |
3557 | u16 sge_size; | |
3558 | int i; | |
3559 | ||
3560 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
3561 | __func__)); | |
3562 | ||
3563 | ||
3564 | retry_sz = 0; | |
3565 | facts = &ioc->facts; | |
3566 | ||
3567 | /* command line tunables for max sgl entries */ | |
3568 | if (max_sgl_entries != -1) | |
3569 | sg_tablesize = max_sgl_entries; | |
471ef9d4 SR |
3570 | else { |
3571 | if (ioc->hba_mpi_version_belonged == MPI2_VERSION) | |
3572 | sg_tablesize = MPT2SAS_SG_DEPTH; | |
3573 | else | |
3574 | sg_tablesize = MPT3SAS_SG_DEPTH; | |
3575 | } | |
f92363d1 | 3576 | |
06f5f976 SR |
3577 | /* max sgl entries <= MPT_KDUMP_MIN_PHYS_SEGMENTS in KDUMP mode */ |
3578 | if (reset_devices) | |
3579 | sg_tablesize = min_t(unsigned short, sg_tablesize, | |
3580 | MPT_KDUMP_MIN_PHYS_SEGMENTS); | |
3581 | ||
8a7e4c24 SR |
3582 | if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS) |
3583 | sg_tablesize = MPT_MIN_PHYS_SEGMENTS; | |
3584 | else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) { | |
ad666a0f | 3585 | sg_tablesize = min_t(unsigned short, sg_tablesize, |
65e8617f | 3586 | SG_MAX_SEGMENTS); |
ad666a0f SR |
3587 | pr_warn(MPT3SAS_FMT |
3588 | "sg_tablesize(%u) is bigger than kernel" | |
65e8617f | 3589 | " defined SG_CHUNK_SIZE(%u)\n", ioc->name, |
8a7e4c24 | 3590 | sg_tablesize, MPT_MAX_PHYS_SEGMENTS); |
ad666a0f | 3591 | } |
f92363d1 SR |
3592 | ioc->shost->sg_tablesize = sg_tablesize; |
3593 | ||
fd0331b3 SS |
3594 | ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)), |
3595 | (facts->RequestCredit / 4)); | |
3596 | if (ioc->internal_depth < INTERNAL_CMDS_COUNT) { | |
3597 | if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT + | |
3598 | INTERNAL_SCSIIO_CMDS_COUNT)) { | |
3599 | pr_err(MPT3SAS_FMT "IOC doesn't have enough Request \ | |
3600 | Credits, it has just %d number of credits\n", | |
3601 | ioc->name, facts->RequestCredit); | |
3602 | return -ENOMEM; | |
3603 | } | |
3604 | ioc->internal_depth = 10; | |
3605 | } | |
3606 | ||
3607 | ioc->hi_priority_depth = ioc->internal_depth - (5); | |
f92363d1 SR |
3608 | /* command line tunables for max controller queue depth */ |
3609 | if (max_queue_depth != -1 && max_queue_depth != 0) { | |
3610 | max_request_credit = min_t(u16, max_queue_depth + | |
fd0331b3 | 3611 | ioc->internal_depth, facts->RequestCredit); |
f92363d1 SR |
3612 | if (max_request_credit > MAX_HBA_QUEUE_DEPTH) |
3613 | max_request_credit = MAX_HBA_QUEUE_DEPTH; | |
06f5f976 SR |
3614 | } else if (reset_devices) |
3615 | max_request_credit = min_t(u16, facts->RequestCredit, | |
3616 | (MPT3SAS_KDUMP_SCSI_IO_DEPTH + ioc->internal_depth)); | |
3617 | else | |
f92363d1 SR |
3618 | max_request_credit = min_t(u16, facts->RequestCredit, |
3619 | MAX_HBA_QUEUE_DEPTH); | |
3620 | ||
fd0331b3 SS |
3621 | /* Firmware maintains additional facts->HighPriorityCredit number of |
3622 | * credits for HiPriprity Request messages, so hba queue depth will be | |
3623 | * sum of max_request_credit and high priority queue depth. | |
3624 | */ | |
3625 | ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth; | |
f92363d1 SR |
3626 | |
3627 | /* request frame size */ | |
3628 | ioc->request_sz = facts->IOCRequestFrameSize * 4; | |
3629 | ||
3630 | /* reply frame size */ | |
3631 | ioc->reply_sz = facts->ReplyFrameSize * 4; | |
3632 | ||
ebb3024e SS |
3633 | /* chain segment size */ |
3634 | if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { | |
3635 | if (facts->IOCMaxChainSegmentSize) | |
3636 | ioc->chain_segment_sz = | |
3637 | facts->IOCMaxChainSegmentSize * | |
3638 | MAX_CHAIN_ELEMT_SZ; | |
3639 | else | |
3640 | /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */ | |
3641 | ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS * | |
3642 | MAX_CHAIN_ELEMT_SZ; | |
3643 | } else | |
3644 | ioc->chain_segment_sz = ioc->request_sz; | |
3645 | ||
f92363d1 SR |
3646 | /* calculate the max scatter element size */ |
3647 | sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee); | |
3648 | ||
3649 | retry_allocation: | |
3650 | total_sz = 0; | |
3651 | /* calculate number of sg elements left over in the 1st frame */ | |
3652 | max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) - | |
3653 | sizeof(Mpi2SGEIOUnion_t)) + sge_size); | |
3654 | ioc->max_sges_in_main_message = max_sge_elements/sge_size; | |
3655 | ||
3656 | /* now do the same for a chain buffer */ | |
ebb3024e | 3657 | max_sge_elements = ioc->chain_segment_sz - sge_size; |
f92363d1 SR |
3658 | ioc->max_sges_in_chain_message = max_sge_elements/sge_size; |
3659 | ||
3660 | /* | |
3661 | * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE | |
3662 | */ | |
3663 | chains_needed_per_io = ((ioc->shost->sg_tablesize - | |
3664 | ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message) | |
3665 | + 1; | |
3666 | if (chains_needed_per_io > facts->MaxChainDepth) { | |
3667 | chains_needed_per_io = facts->MaxChainDepth; | |
3668 | ioc->shost->sg_tablesize = min_t(u16, | |
3669 | ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message | |
3670 | * chains_needed_per_io), ioc->shost->sg_tablesize); | |
3671 | } | |
3672 | ioc->chains_needed_per_io = chains_needed_per_io; | |
3673 | ||
3674 | /* reply free queue sizing - taking into account for 64 FW events */ | |
3675 | ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; | |
3676 | ||
3677 | /* calculate reply descriptor post queue depth */ | |
3678 | ioc->reply_post_queue_depth = ioc->hba_queue_depth + | |
3679 | ioc->reply_free_queue_depth + 1 ; | |
3680 | /* align the reply post queue on the next 16 count boundary */ | |
3681 | if (ioc->reply_post_queue_depth % 16) | |
3682 | ioc->reply_post_queue_depth += 16 - | |
3683 | (ioc->reply_post_queue_depth % 16); | |
3684 | ||
f92363d1 SR |
3685 | if (ioc->reply_post_queue_depth > |
3686 | facts->MaxReplyDescriptorPostQueueDepth) { | |
3687 | ioc->reply_post_queue_depth = | |
3688 | facts->MaxReplyDescriptorPostQueueDepth - | |
3689 | (facts->MaxReplyDescriptorPostQueueDepth % 16); | |
3690 | ioc->hba_queue_depth = | |
3691 | ((ioc->reply_post_queue_depth - 64) / 2) - 1; | |
3692 | ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; | |
3693 | } | |
3694 | ||
3695 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \ | |
3696 | "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), " | |
3697 | "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message, | |
3698 | ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize, | |
3699 | ioc->chains_needed_per_io)); | |
3700 | ||
9b05c91a SR |
3701 | /* reply post queue, 16 byte align */ |
3702 | reply_post_free_sz = ioc->reply_post_queue_depth * | |
3703 | sizeof(Mpi2DefaultReplyDescriptor_t); | |
3704 | ||
3705 | sz = reply_post_free_sz; | |
3706 | if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable) | |
3707 | sz *= ioc->reply_queue_count; | |
3708 | ||
3709 | ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ? | |
3710 | (ioc->reply_queue_count):1, | |
3711 | sizeof(struct reply_post_struct), GFP_KERNEL); | |
3712 | ||
3713 | if (!ioc->reply_post) { | |
3714 | pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n", | |
3715 | ioc->name); | |
3716 | goto out; | |
3717 | } | |
e9d98418 RP |
3718 | ioc->reply_post_free_dma_pool = dma_pool_create("reply_post_free pool", |
3719 | &ioc->pdev->dev, sz, 16, 0); | |
9b05c91a SR |
3720 | if (!ioc->reply_post_free_dma_pool) { |
3721 | pr_err(MPT3SAS_FMT | |
e9d98418 | 3722 | "reply_post_free pool: dma_pool_create failed\n", |
9b05c91a SR |
3723 | ioc->name); |
3724 | goto out; | |
3725 | } | |
3726 | i = 0; | |
3727 | do { | |
3728 | ioc->reply_post[i].reply_post_free = | |
e9d98418 | 3729 | dma_pool_alloc(ioc->reply_post_free_dma_pool, |
9b05c91a SR |
3730 | GFP_KERNEL, |
3731 | &ioc->reply_post[i].reply_post_free_dma); | |
3732 | if (!ioc->reply_post[i].reply_post_free) { | |
3733 | pr_err(MPT3SAS_FMT | |
e9d98418 | 3734 | "reply_post_free pool: dma_pool_alloc failed\n", |
9b05c91a SR |
3735 | ioc->name); |
3736 | goto out; | |
3737 | } | |
3738 | memset(ioc->reply_post[i].reply_post_free, 0, sz); | |
3739 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
3740 | "reply post free pool (0x%p): depth(%d)," | |
3741 | "element_size(%d), pool_size(%d kB)\n", ioc->name, | |
3742 | ioc->reply_post[i].reply_post_free, | |
3743 | ioc->reply_post_queue_depth, 8, sz/1024)); | |
3744 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
3745 | "reply_post_free_dma = (0x%llx)\n", ioc->name, | |
3746 | (unsigned long long) | |
3747 | ioc->reply_post[i].reply_post_free_dma)); | |
3748 | total_sz += sz; | |
3749 | } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count)); | |
3750 | ||
3751 | if (ioc->dma_mask == 64) { | |
3752 | if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) { | |
3753 | pr_warn(MPT3SAS_FMT | |
3754 | "no suitable consistent DMA mask for %s\n", | |
3755 | ioc->name, pci_name(ioc->pdev)); | |
3756 | goto out; | |
3757 | } | |
3758 | } | |
3759 | ||
f92363d1 SR |
3760 | ioc->scsiio_depth = ioc->hba_queue_depth - |
3761 | ioc->hi_priority_depth - ioc->internal_depth; | |
3762 | ||
3763 | /* set the scsi host can_queue depth | |
3764 | * with some internal commands that could be outstanding | |
3765 | */ | |
fd0331b3 | 3766 | ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT; |
f92363d1 SR |
3767 | dinitprintk(ioc, pr_info(MPT3SAS_FMT |
3768 | "scsi host: can_queue depth (%d)\n", | |
3769 | ioc->name, ioc->shost->can_queue)); | |
3770 | ||
3771 | ||
3772 | /* contiguous pool for request and chains, 16 byte align, one extra " | |
3773 | * "frame for smid=0 | |
3774 | */ | |
3775 | ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth; | |
3776 | sz = ((ioc->scsiio_depth + 1) * ioc->request_sz); | |
3777 | ||
3778 | /* hi-priority queue */ | |
3779 | sz += (ioc->hi_priority_depth * ioc->request_sz); | |
3780 | ||
3781 | /* internal queue */ | |
3782 | sz += (ioc->internal_depth * ioc->request_sz); | |
3783 | ||
3784 | ioc->request_dma_sz = sz; | |
3785 | ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma); | |
3786 | if (!ioc->request) { | |
3787 | pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \ | |
3788 | "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), " | |
3789 | "total(%d kB)\n", ioc->name, ioc->hba_queue_depth, | |
3790 | ioc->chains_needed_per_io, ioc->request_sz, sz/1024); | |
3791 | if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH) | |
3792 | goto out; | |
fd0331b3 SS |
3793 | retry_sz = 64; |
3794 | ioc->hba_queue_depth -= retry_sz; | |
8ff045c9 | 3795 | _base_release_memory_pools(ioc); |
f92363d1 SR |
3796 | goto retry_allocation; |
3797 | } | |
3798 | ||
3799 | if (retry_sz) | |
3800 | pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \ | |
3801 | "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), " | |
3802 | "total(%d kb)\n", ioc->name, ioc->hba_queue_depth, | |
3803 | ioc->chains_needed_per_io, ioc->request_sz, sz/1024); | |
3804 | ||
3805 | /* hi-priority queue */ | |
3806 | ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) * | |
3807 | ioc->request_sz); | |
3808 | ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) * | |
3809 | ioc->request_sz); | |
3810 | ||
3811 | /* internal queue */ | |
3812 | ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth * | |
3813 | ioc->request_sz); | |
3814 | ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth * | |
3815 | ioc->request_sz); | |
3816 | ||
3817 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
3818 | "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n", | |
3819 | ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz, | |
3820 | (ioc->hba_queue_depth * ioc->request_sz)/1024)); | |
3821 | ||
3822 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n", | |
3823 | ioc->name, (unsigned long long) ioc->request_dma)); | |
3824 | total_sz += sz; | |
3825 | ||
3826 | sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker); | |
3827 | ioc->scsi_lookup_pages = get_order(sz); | |
3828 | ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages( | |
3829 | GFP_KERNEL, ioc->scsi_lookup_pages); | |
3830 | if (!ioc->scsi_lookup) { | |
3831 | pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n", | |
3832 | ioc->name, (int)sz); | |
3833 | goto out; | |
3834 | } | |
3835 | ||
3836 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n", | |
3837 | ioc->name, ioc->request, ioc->scsiio_depth)); | |
3838 | ||
3839 | ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH); | |
3840 | sz = ioc->chain_depth * sizeof(struct chain_tracker); | |
3841 | ioc->chain_pages = get_order(sz); | |
3842 | ioc->chain_lookup = (struct chain_tracker *)__get_free_pages( | |
3843 | GFP_KERNEL, ioc->chain_pages); | |
3844 | if (!ioc->chain_lookup) { | |
3845 | pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n", | |
3846 | ioc->name); | |
3847 | goto out; | |
3848 | } | |
e9d98418 | 3849 | ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev, |
ebb3024e | 3850 | ioc->chain_segment_sz, 16, 0); |
f92363d1 | 3851 | if (!ioc->chain_dma_pool) { |
e9d98418 | 3852 | pr_err(MPT3SAS_FMT "chain_dma_pool: dma_pool_create failed\n", |
f92363d1 SR |
3853 | ioc->name); |
3854 | goto out; | |
3855 | } | |
3856 | for (i = 0; i < ioc->chain_depth; i++) { | |
e9d98418 | 3857 | ioc->chain_lookup[i].chain_buffer = dma_pool_alloc( |
f92363d1 SR |
3858 | ioc->chain_dma_pool , GFP_KERNEL, |
3859 | &ioc->chain_lookup[i].chain_buffer_dma); | |
3860 | if (!ioc->chain_lookup[i].chain_buffer) { | |
3861 | ioc->chain_depth = i; | |
3862 | goto chain_done; | |
3863 | } | |
ebb3024e | 3864 | total_sz += ioc->chain_segment_sz; |
f92363d1 SR |
3865 | } |
3866 | chain_done: | |
3867 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
3868 | "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n", | |
ebb3024e SS |
3869 | ioc->name, ioc->chain_depth, ioc->chain_segment_sz, |
3870 | ((ioc->chain_depth * ioc->chain_segment_sz))/1024)); | |
f92363d1 SR |
3871 | |
3872 | /* initialize hi-priority queue smid's */ | |
3873 | ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth, | |
3874 | sizeof(struct request_tracker), GFP_KERNEL); | |
3875 | if (!ioc->hpr_lookup) { | |
3876 | pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n", | |
3877 | ioc->name); | |
3878 | goto out; | |
3879 | } | |
3880 | ioc->hi_priority_smid = ioc->scsiio_depth + 1; | |
3881 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
3882 | "hi_priority(0x%p): depth(%d), start smid(%d)\n", | |
3883 | ioc->name, ioc->hi_priority, | |
3884 | ioc->hi_priority_depth, ioc->hi_priority_smid)); | |
3885 | ||
3886 | /* initialize internal queue smid's */ | |
3887 | ioc->internal_lookup = kcalloc(ioc->internal_depth, | |
3888 | sizeof(struct request_tracker), GFP_KERNEL); | |
3889 | if (!ioc->internal_lookup) { | |
3890 | pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n", | |
3891 | ioc->name); | |
3892 | goto out; | |
3893 | } | |
3894 | ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth; | |
3895 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
3896 | "internal(0x%p): depth(%d), start smid(%d)\n", | |
3897 | ioc->name, ioc->internal, | |
3898 | ioc->internal_depth, ioc->internal_smid)); | |
016d5c35 SPS |
3899 | /* |
3900 | * The number of NVMe page sized blocks needed is: | |
3901 | * (((sg_tablesize * 8) - 1) / (page_size - 8)) + 1 | |
3902 | * ((sg_tablesize * 8) - 1) is the max PRP's minus the first PRP entry | |
3903 | * that is placed in the main message frame. 8 is the size of each PRP | |
3904 | * entry or PRP list pointer entry. 8 is subtracted from page_size | |
3905 | * because of the PRP list pointer entry at the end of a page, so this | |
3906 | * is not counted as a PRP entry. The 1 added page is a round up. | |
3907 | * | |
3908 | * To avoid allocation failures due to the amount of memory that could | |
3909 | * be required for NVMe PRP's, only each set of NVMe blocks will be | |
3910 | * contiguous, so a new set is allocated for each possible I/O. | |
3911 | */ | |
3912 | if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) { | |
3913 | nvme_blocks_needed = | |
3914 | (ioc->shost->sg_tablesize * NVME_PRP_SIZE) - 1; | |
3915 | nvme_blocks_needed /= (ioc->page_size - NVME_PRP_SIZE); | |
3916 | nvme_blocks_needed++; | |
3917 | ||
3918 | sz = nvme_blocks_needed * ioc->page_size; | |
3919 | ioc->pcie_sgl_dma_pool = | |
3920 | pci_pool_create("PCIe SGL pool", ioc->pdev, sz, 16, 0); | |
3921 | if (!ioc->pcie_sgl_dma_pool) { | |
3922 | pr_info(MPT3SAS_FMT | |
3923 | "PCIe SGL pool: pci_pool_create failed\n", | |
3924 | ioc->name); | |
3925 | goto out; | |
3926 | } | |
3927 | for (i = 0; i < ioc->scsiio_depth; i++) { | |
3928 | ioc->scsi_lookup[i].pcie_sg_list.pcie_sgl = | |
3929 | pci_pool_alloc(ioc->pcie_sgl_dma_pool, | |
3930 | GFP_KERNEL, | |
3931 | &ioc->scsi_lookup[i].pcie_sg_list.pcie_sgl_dma); | |
3932 | if (!ioc->scsi_lookup[i].pcie_sg_list.pcie_sgl) { | |
3933 | pr_info(MPT3SAS_FMT | |
3934 | "PCIe SGL pool: pci_pool_alloc failed\n", | |
3935 | ioc->name); | |
3936 | goto out; | |
3937 | } | |
3938 | } | |
f92363d1 | 3939 | |
016d5c35 SPS |
3940 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "PCIe sgl pool depth(%d), " |
3941 | "element_size(%d), pool_size(%d kB)\n", ioc->name, | |
3942 | ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024)); | |
3943 | total_sz += sz * ioc->scsiio_depth; | |
3944 | } | |
f92363d1 SR |
3945 | /* sense buffers, 4 byte align */ |
3946 | sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE; | |
e9d98418 RP |
3947 | ioc->sense_dma_pool = dma_pool_create("sense pool", &ioc->pdev->dev, sz, |
3948 | 4, 0); | |
f92363d1 | 3949 | if (!ioc->sense_dma_pool) { |
e9d98418 | 3950 | pr_err(MPT3SAS_FMT "sense pool: dma_pool_create failed\n", |
f92363d1 SR |
3951 | ioc->name); |
3952 | goto out; | |
3953 | } | |
e9d98418 | 3954 | ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL, |
f92363d1 SR |
3955 | &ioc->sense_dma); |
3956 | if (!ioc->sense) { | |
e9d98418 | 3957 | pr_err(MPT3SAS_FMT "sense pool: dma_pool_alloc failed\n", |
f92363d1 SR |
3958 | ioc->name); |
3959 | goto out; | |
3960 | } | |
3961 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
3962 | "sense pool(0x%p): depth(%d), element_size(%d), pool_size" | |
3963 | "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth, | |
3964 | SCSI_SENSE_BUFFERSIZE, sz/1024)); | |
3965 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n", | |
3966 | ioc->name, (unsigned long long)ioc->sense_dma)); | |
3967 | total_sz += sz; | |
3968 | ||
3969 | /* reply pool, 4 byte align */ | |
3970 | sz = ioc->reply_free_queue_depth * ioc->reply_sz; | |
e9d98418 RP |
3971 | ioc->reply_dma_pool = dma_pool_create("reply pool", &ioc->pdev->dev, sz, |
3972 | 4, 0); | |
f92363d1 | 3973 | if (!ioc->reply_dma_pool) { |
e9d98418 | 3974 | pr_err(MPT3SAS_FMT "reply pool: dma_pool_create failed\n", |
f92363d1 SR |
3975 | ioc->name); |
3976 | goto out; | |
3977 | } | |
e9d98418 | 3978 | ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL, |
f92363d1 SR |
3979 | &ioc->reply_dma); |
3980 | if (!ioc->reply) { | |
e9d98418 | 3981 | pr_err(MPT3SAS_FMT "reply pool: dma_pool_alloc failed\n", |
f92363d1 SR |
3982 | ioc->name); |
3983 | goto out; | |
3984 | } | |
3985 | ioc->reply_dma_min_address = (u32)(ioc->reply_dma); | |
3986 | ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz; | |
3987 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
3988 | "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n", | |
3989 | ioc->name, ioc->reply, | |
3990 | ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024)); | |
3991 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n", | |
3992 | ioc->name, (unsigned long long)ioc->reply_dma)); | |
3993 | total_sz += sz; | |
3994 | ||
3995 | /* reply free queue, 16 byte align */ | |
3996 | sz = ioc->reply_free_queue_depth * 4; | |
e9d98418 RP |
3997 | ioc->reply_free_dma_pool = dma_pool_create("reply_free pool", |
3998 | &ioc->pdev->dev, sz, 16, 0); | |
f92363d1 | 3999 | if (!ioc->reply_free_dma_pool) { |
e9d98418 | 4000 | pr_err(MPT3SAS_FMT "reply_free pool: dma_pool_create failed\n", |
f92363d1 SR |
4001 | ioc->name); |
4002 | goto out; | |
4003 | } | |
e9d98418 | 4004 | ioc->reply_free = dma_pool_alloc(ioc->reply_free_dma_pool, GFP_KERNEL, |
f92363d1 SR |
4005 | &ioc->reply_free_dma); |
4006 | if (!ioc->reply_free) { | |
e9d98418 | 4007 | pr_err(MPT3SAS_FMT "reply_free pool: dma_pool_alloc failed\n", |
f92363d1 SR |
4008 | ioc->name); |
4009 | goto out; | |
4010 | } | |
4011 | memset(ioc->reply_free, 0, sz); | |
4012 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \ | |
4013 | "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name, | |
4014 | ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024)); | |
4015 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
4016 | "reply_free_dma (0x%llx)\n", | |
4017 | ioc->name, (unsigned long long)ioc->reply_free_dma)); | |
4018 | total_sz += sz; | |
4019 | ||
f92363d1 SR |
4020 | ioc->config_page_sz = 512; |
4021 | ioc->config_page = pci_alloc_consistent(ioc->pdev, | |
4022 | ioc->config_page_sz, &ioc->config_page_dma); | |
4023 | if (!ioc->config_page) { | |
4024 | pr_err(MPT3SAS_FMT | |
e9d98418 | 4025 | "config page: dma_pool_alloc failed\n", |
f92363d1 SR |
4026 | ioc->name); |
4027 | goto out; | |
4028 | } | |
4029 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
4030 | "config page(0x%p): size(%d)\n", | |
4031 | ioc->name, ioc->config_page, ioc->config_page_sz)); | |
4032 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n", | |
4033 | ioc->name, (unsigned long long)ioc->config_page_dma)); | |
4034 | total_sz += ioc->config_page_sz; | |
4035 | ||
4036 | pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n", | |
4037 | ioc->name, total_sz/1024); | |
4038 | pr_info(MPT3SAS_FMT | |
4039 | "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n", | |
4040 | ioc->name, ioc->shost->can_queue, facts->RequestCredit); | |
4041 | pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n", | |
4042 | ioc->name, ioc->shost->sg_tablesize); | |
4043 | return 0; | |
4044 | ||
4045 | out: | |
4046 | return -ENOMEM; | |
4047 | } | |
4048 | ||
4049 | /** | |
4050 | * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter. | |
4051 | * @ioc: Pointer to MPT_ADAPTER structure | |
4052 | * @cooked: Request raw or cooked IOC state | |
4053 | * | |
4054 | * Returns all IOC Doorbell register bits if cooked==0, else just the | |
4055 | * Doorbell bits in MPI_IOC_STATE_MASK. | |
4056 | */ | |
4057 | u32 | |
4058 | mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked) | |
4059 | { | |
4060 | u32 s, sc; | |
4061 | ||
4062 | s = readl(&ioc->chip->Doorbell); | |
4063 | sc = s & MPI2_IOC_STATE_MASK; | |
4064 | return cooked ? sc : s; | |
4065 | } | |
4066 | ||
4067 | /** | |
4068 | * _base_wait_on_iocstate - waiting on a particular ioc state | |
4069 | * @ioc_state: controller state { READY, OPERATIONAL, or RESET } | |
4070 | * @timeout: timeout in second | |
f92363d1 SR |
4071 | * |
4072 | * Returns 0 for success, non-zero for failure. | |
4073 | */ | |
4074 | static int | |
98c56ad3 | 4075 | _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout) |
f92363d1 SR |
4076 | { |
4077 | u32 count, cntdn; | |
4078 | u32 current_state; | |
4079 | ||
4080 | count = 0; | |
98c56ad3 | 4081 | cntdn = 1000 * timeout; |
f92363d1 SR |
4082 | do { |
4083 | current_state = mpt3sas_base_get_iocstate(ioc, 1); | |
4084 | if (current_state == ioc_state) | |
4085 | return 0; | |
4086 | if (count && current_state == MPI2_IOC_STATE_FAULT) | |
4087 | break; | |
98c56ad3 CO |
4088 | |
4089 | usleep_range(1000, 1500); | |
f92363d1 SR |
4090 | count++; |
4091 | } while (--cntdn); | |
4092 | ||
4093 | return current_state; | |
4094 | } | |
4095 | ||
4096 | /** | |
4097 | * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by | |
4098 | * a write to the doorbell) | |
4099 | * @ioc: per adapter object | |
4100 | * @timeout: timeout in second | |
f92363d1 SR |
4101 | * |
4102 | * Returns 0 for success, non-zero for failure. | |
4103 | * | |
4104 | * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell. | |
4105 | */ | |
4dc8c808 | 4106 | static int |
98c56ad3 | 4107 | _base_diag_reset(struct MPT3SAS_ADAPTER *ioc); |
4dc8c808 | 4108 | |
f92363d1 | 4109 | static int |
98c56ad3 | 4110 | _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout) |
f92363d1 SR |
4111 | { |
4112 | u32 cntdn, count; | |
4113 | u32 int_status; | |
4114 | ||
4115 | count = 0; | |
98c56ad3 | 4116 | cntdn = 1000 * timeout; |
f92363d1 SR |
4117 | do { |
4118 | int_status = readl(&ioc->chip->HostInterruptStatus); | |
4119 | if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { | |
4120 | dhsprintk(ioc, pr_info(MPT3SAS_FMT | |
4121 | "%s: successful count(%d), timeout(%d)\n", | |
4122 | ioc->name, __func__, count, timeout)); | |
4123 | return 0; | |
4124 | } | |
98c56ad3 CO |
4125 | |
4126 | usleep_range(1000, 1500); | |
4127 | count++; | |
4128 | } while (--cntdn); | |
4129 | ||
4130 | pr_err(MPT3SAS_FMT | |
4131 | "%s: failed due to timeout count(%d), int_status(%x)!\n", | |
4132 | ioc->name, __func__, count, int_status); | |
4133 | return -EFAULT; | |
4134 | } | |
4135 | ||
4136 | static int | |
4137 | _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout) | |
4138 | { | |
4139 | u32 cntdn, count; | |
4140 | u32 int_status; | |
4141 | ||
4142 | count = 0; | |
4143 | cntdn = 2000 * timeout; | |
4144 | do { | |
4145 | int_status = readl(&ioc->chip->HostInterruptStatus); | |
4146 | if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { | |
4147 | dhsprintk(ioc, pr_info(MPT3SAS_FMT | |
4148 | "%s: successful count(%d), timeout(%d)\n", | |
4149 | ioc->name, __func__, count, timeout)); | |
4150 | return 0; | |
4151 | } | |
4152 | ||
4153 | udelay(500); | |
f92363d1 SR |
4154 | count++; |
4155 | } while (--cntdn); | |
4156 | ||
4157 | pr_err(MPT3SAS_FMT | |
4158 | "%s: failed due to timeout count(%d), int_status(%x)!\n", | |
4159 | ioc->name, __func__, count, int_status); | |
4160 | return -EFAULT; | |
98c56ad3 | 4161 | |
f92363d1 SR |
4162 | } |
4163 | ||
4164 | /** | |
4165 | * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell. | |
4166 | * @ioc: per adapter object | |
4167 | * @timeout: timeout in second | |
f92363d1 SR |
4168 | * |
4169 | * Returns 0 for success, non-zero for failure. | |
4170 | * | |
4171 | * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to | |
4172 | * doorbell. | |
4173 | */ | |
4174 | static int | |
98c56ad3 | 4175 | _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout) |
f92363d1 SR |
4176 | { |
4177 | u32 cntdn, count; | |
4178 | u32 int_status; | |
4179 | u32 doorbell; | |
4180 | ||
4181 | count = 0; | |
98c56ad3 | 4182 | cntdn = 1000 * timeout; |
f92363d1 SR |
4183 | do { |
4184 | int_status = readl(&ioc->chip->HostInterruptStatus); | |
4185 | if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) { | |
4186 | dhsprintk(ioc, pr_info(MPT3SAS_FMT | |
4187 | "%s: successful count(%d), timeout(%d)\n", | |
4188 | ioc->name, __func__, count, timeout)); | |
4189 | return 0; | |
4190 | } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { | |
4191 | doorbell = readl(&ioc->chip->Doorbell); | |
4192 | if ((doorbell & MPI2_IOC_STATE_MASK) == | |
4193 | MPI2_IOC_STATE_FAULT) { | |
4194 | mpt3sas_base_fault_info(ioc , doorbell); | |
4195 | return -EFAULT; | |
4196 | } | |
4197 | } else if (int_status == 0xFFFFFFFF) | |
4198 | goto out; | |
4199 | ||
98c56ad3 | 4200 | usleep_range(1000, 1500); |
f92363d1 SR |
4201 | count++; |
4202 | } while (--cntdn); | |
4203 | ||
4204 | out: | |
4205 | pr_err(MPT3SAS_FMT | |
4206 | "%s: failed due to timeout count(%d), int_status(%x)!\n", | |
4207 | ioc->name, __func__, count, int_status); | |
4208 | return -EFAULT; | |
4209 | } | |
4210 | ||
4211 | /** | |
4212 | * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use | |
4213 | * @ioc: per adapter object | |
4214 | * @timeout: timeout in second | |
f92363d1 SR |
4215 | * |
4216 | * Returns 0 for success, non-zero for failure. | |
4217 | * | |
4218 | */ | |
4219 | static int | |
98c56ad3 | 4220 | _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout) |
f92363d1 SR |
4221 | { |
4222 | u32 cntdn, count; | |
4223 | u32 doorbell_reg; | |
4224 | ||
4225 | count = 0; | |
98c56ad3 | 4226 | cntdn = 1000 * timeout; |
f92363d1 SR |
4227 | do { |
4228 | doorbell_reg = readl(&ioc->chip->Doorbell); | |
4229 | if (!(doorbell_reg & MPI2_DOORBELL_USED)) { | |
4230 | dhsprintk(ioc, pr_info(MPT3SAS_FMT | |
4231 | "%s: successful count(%d), timeout(%d)\n", | |
4232 | ioc->name, __func__, count, timeout)); | |
4233 | return 0; | |
4234 | } | |
98c56ad3 CO |
4235 | |
4236 | usleep_range(1000, 1500); | |
f92363d1 SR |
4237 | count++; |
4238 | } while (--cntdn); | |
4239 | ||
4240 | pr_err(MPT3SAS_FMT | |
4241 | "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n", | |
4242 | ioc->name, __func__, count, doorbell_reg); | |
4243 | return -EFAULT; | |
4244 | } | |
4245 | ||
4246 | /** | |
4247 | * _base_send_ioc_reset - send doorbell reset | |
4248 | * @ioc: per adapter object | |
4249 | * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET | |
4250 | * @timeout: timeout in second | |
f92363d1 SR |
4251 | * |
4252 | * Returns 0 for success, non-zero for failure. | |
4253 | */ | |
4254 | static int | |
98c56ad3 | 4255 | _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout) |
f92363d1 SR |
4256 | { |
4257 | u32 ioc_state; | |
4258 | int r = 0; | |
4259 | ||
4260 | if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) { | |
4261 | pr_err(MPT3SAS_FMT "%s: unknown reset_type\n", | |
4262 | ioc->name, __func__); | |
4263 | return -EFAULT; | |
4264 | } | |
4265 | ||
4266 | if (!(ioc->facts.IOCCapabilities & | |
4267 | MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY)) | |
4268 | return -EFAULT; | |
4269 | ||
4270 | pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name); | |
4271 | ||
4272 | writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT, | |
4273 | &ioc->chip->Doorbell); | |
98c56ad3 | 4274 | if ((_base_wait_for_doorbell_ack(ioc, 15))) { |
f92363d1 SR |
4275 | r = -EFAULT; |
4276 | goto out; | |
4277 | } | |
98c56ad3 | 4278 | ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout); |
f92363d1 SR |
4279 | if (ioc_state) { |
4280 | pr_err(MPT3SAS_FMT | |
4281 | "%s: failed going to ready state (ioc_state=0x%x)\n", | |
4282 | ioc->name, __func__, ioc_state); | |
4283 | r = -EFAULT; | |
4284 | goto out; | |
4285 | } | |
4286 | out: | |
4287 | pr_info(MPT3SAS_FMT "message unit reset: %s\n", | |
4288 | ioc->name, ((r == 0) ? "SUCCESS" : "FAILED")); | |
4289 | return r; | |
4290 | } | |
4291 | ||
4292 | /** | |
4293 | * _base_handshake_req_reply_wait - send request thru doorbell interface | |
4294 | * @ioc: per adapter object | |
4295 | * @request_bytes: request length | |
4296 | * @request: pointer having request payload | |
4297 | * @reply_bytes: reply length | |
4298 | * @reply: pointer to reply payload | |
4299 | * @timeout: timeout in second | |
f92363d1 SR |
4300 | * |
4301 | * Returns 0 for success, non-zero for failure. | |
4302 | */ | |
4303 | static int | |
4304 | _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes, | |
98c56ad3 | 4305 | u32 *request, int reply_bytes, u16 *reply, int timeout) |
f92363d1 SR |
4306 | { |
4307 | MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply; | |
4308 | int i; | |
4309 | u8 failed; | |
f92363d1 SR |
4310 | __le32 *mfp; |
4311 | ||
4312 | /* make sure doorbell is not in use */ | |
4313 | if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) { | |
4314 | pr_err(MPT3SAS_FMT | |
4315 | "doorbell is in use (line=%d)\n", | |
4316 | ioc->name, __LINE__); | |
4317 | return -EFAULT; | |
4318 | } | |
4319 | ||
4320 | /* clear pending doorbell interrupts from previous state changes */ | |
4321 | if (readl(&ioc->chip->HostInterruptStatus) & | |
4322 | MPI2_HIS_IOC2SYS_DB_STATUS) | |
4323 | writel(0, &ioc->chip->HostInterruptStatus); | |
4324 | ||
4325 | /* send message to ioc */ | |
4326 | writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) | | |
4327 | ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)), | |
4328 | &ioc->chip->Doorbell); | |
4329 | ||
98c56ad3 | 4330 | if ((_base_spin_on_doorbell_int(ioc, 5))) { |
f92363d1 SR |
4331 | pr_err(MPT3SAS_FMT |
4332 | "doorbell handshake int failed (line=%d)\n", | |
4333 | ioc->name, __LINE__); | |
4334 | return -EFAULT; | |
4335 | } | |
4336 | writel(0, &ioc->chip->HostInterruptStatus); | |
4337 | ||
98c56ad3 | 4338 | if ((_base_wait_for_doorbell_ack(ioc, 5))) { |
f92363d1 SR |
4339 | pr_err(MPT3SAS_FMT |
4340 | "doorbell handshake ack failed (line=%d)\n", | |
4341 | ioc->name, __LINE__); | |
4342 | return -EFAULT; | |
4343 | } | |
4344 | ||
4345 | /* send message 32-bits at a time */ | |
4346 | for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) { | |
4347 | writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell); | |
98c56ad3 | 4348 | if ((_base_wait_for_doorbell_ack(ioc, 5))) |
f92363d1 SR |
4349 | failed = 1; |
4350 | } | |
4351 | ||
4352 | if (failed) { | |
4353 | pr_err(MPT3SAS_FMT | |
4354 | "doorbell handshake sending request failed (line=%d)\n", | |
4355 | ioc->name, __LINE__); | |
4356 | return -EFAULT; | |
4357 | } | |
4358 | ||
4359 | /* now wait for the reply */ | |
98c56ad3 | 4360 | if ((_base_wait_for_doorbell_int(ioc, timeout))) { |
f92363d1 SR |
4361 | pr_err(MPT3SAS_FMT |
4362 | "doorbell handshake int failed (line=%d)\n", | |
4363 | ioc->name, __LINE__); | |
4364 | return -EFAULT; | |
4365 | } | |
4366 | ||
4367 | /* read the first two 16-bits, it gives the total length of the reply */ | |
4368 | reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell) | |
4369 | & MPI2_DOORBELL_DATA_MASK); | |
4370 | writel(0, &ioc->chip->HostInterruptStatus); | |
98c56ad3 | 4371 | if ((_base_wait_for_doorbell_int(ioc, 5))) { |
f92363d1 SR |
4372 | pr_err(MPT3SAS_FMT |
4373 | "doorbell handshake int failed (line=%d)\n", | |
4374 | ioc->name, __LINE__); | |
4375 | return -EFAULT; | |
4376 | } | |
4377 | reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell) | |
4378 | & MPI2_DOORBELL_DATA_MASK); | |
4379 | writel(0, &ioc->chip->HostInterruptStatus); | |
4380 | ||
4381 | for (i = 2; i < default_reply->MsgLength * 2; i++) { | |
98c56ad3 | 4382 | if ((_base_wait_for_doorbell_int(ioc, 5))) { |
f92363d1 SR |
4383 | pr_err(MPT3SAS_FMT |
4384 | "doorbell handshake int failed (line=%d)\n", | |
4385 | ioc->name, __LINE__); | |
4386 | return -EFAULT; | |
4387 | } | |
4388 | if (i >= reply_bytes/2) /* overflow case */ | |
8bbb1cf6 | 4389 | readl(&ioc->chip->Doorbell); |
f92363d1 SR |
4390 | else |
4391 | reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell) | |
4392 | & MPI2_DOORBELL_DATA_MASK); | |
4393 | writel(0, &ioc->chip->HostInterruptStatus); | |
4394 | } | |
4395 | ||
98c56ad3 CO |
4396 | _base_wait_for_doorbell_int(ioc, 5); |
4397 | if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) { | |
f92363d1 SR |
4398 | dhsprintk(ioc, pr_info(MPT3SAS_FMT |
4399 | "doorbell is in use (line=%d)\n", ioc->name, __LINE__)); | |
4400 | } | |
4401 | writel(0, &ioc->chip->HostInterruptStatus); | |
4402 | ||
4403 | if (ioc->logging_level & MPT_DEBUG_INIT) { | |
4404 | mfp = (__le32 *)reply; | |
4405 | pr_info("\toffset:data\n"); | |
4406 | for (i = 0; i < reply_bytes/4; i++) | |
4407 | pr_info("\t[0x%02x]:%08x\n", i*4, | |
4408 | le32_to_cpu(mfp[i])); | |
4409 | } | |
4410 | return 0; | |
4411 | } | |
4412 | ||
4413 | /** | |
4414 | * mpt3sas_base_sas_iounit_control - send sas iounit control to FW | |
4415 | * @ioc: per adapter object | |
4416 | * @mpi_reply: the reply payload from FW | |
4417 | * @mpi_request: the request payload sent to FW | |
4418 | * | |
4419 | * The SAS IO Unit Control Request message allows the host to perform low-level | |
4420 | * operations, such as resets on the PHYs of the IO Unit, also allows the host | |
4421 | * to obtain the IOC assigned device handles for a device if it has other | |
4422 | * identifying information about the device, in addition allows the host to | |
4423 | * remove IOC resources associated with the device. | |
4424 | * | |
4425 | * Returns 0 for success, non-zero for failure. | |
4426 | */ | |
4427 | int | |
4428 | mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc, | |
4429 | Mpi2SasIoUnitControlReply_t *mpi_reply, | |
4430 | Mpi2SasIoUnitControlRequest_t *mpi_request) | |
4431 | { | |
4432 | u16 smid; | |
4433 | u32 ioc_state; | |
eb44552b | 4434 | bool issue_reset = false; |
f92363d1 SR |
4435 | int rc; |
4436 | void *request; | |
4437 | u16 wait_state_count; | |
4438 | ||
4439 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
4440 | __func__)); | |
4441 | ||
4442 | mutex_lock(&ioc->base_cmds.mutex); | |
4443 | ||
4444 | if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { | |
4445 | pr_err(MPT3SAS_FMT "%s: base_cmd in use\n", | |
4446 | ioc->name, __func__); | |
4447 | rc = -EAGAIN; | |
4448 | goto out; | |
4449 | } | |
4450 | ||
4451 | wait_state_count = 0; | |
4452 | ioc_state = mpt3sas_base_get_iocstate(ioc, 1); | |
4453 | while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { | |
4454 | if (wait_state_count++ == 10) { | |
4455 | pr_err(MPT3SAS_FMT | |
4456 | "%s: failed due to ioc not operational\n", | |
4457 | ioc->name, __func__); | |
4458 | rc = -EFAULT; | |
4459 | goto out; | |
4460 | } | |
4461 | ssleep(1); | |
4462 | ioc_state = mpt3sas_base_get_iocstate(ioc, 1); | |
4463 | pr_info(MPT3SAS_FMT | |
4464 | "%s: waiting for operational state(count=%d)\n", | |
4465 | ioc->name, __func__, wait_state_count); | |
4466 | } | |
4467 | ||
4468 | smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); | |
4469 | if (!smid) { | |
4470 | pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", | |
4471 | ioc->name, __func__); | |
4472 | rc = -EAGAIN; | |
4473 | goto out; | |
4474 | } | |
4475 | ||
4476 | rc = 0; | |
4477 | ioc->base_cmds.status = MPT3_CMD_PENDING; | |
4478 | request = mpt3sas_base_get_msg_frame(ioc, smid); | |
4479 | ioc->base_cmds.smid = smid; | |
4480 | memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)); | |
4481 | if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || | |
4482 | mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) | |
4483 | ioc->ioc_link_reset_in_progress = 1; | |
4484 | init_completion(&ioc->base_cmds.done); | |
81c16f83 | 4485 | ioc->put_smid_default(ioc, smid); |
8bbb1cf6 | 4486 | wait_for_completion_timeout(&ioc->base_cmds.done, |
f92363d1 SR |
4487 | msecs_to_jiffies(10000)); |
4488 | if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || | |
4489 | mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) && | |
4490 | ioc->ioc_link_reset_in_progress) | |
4491 | ioc->ioc_link_reset_in_progress = 0; | |
4492 | if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { | |
4493 | pr_err(MPT3SAS_FMT "%s: timeout\n", | |
4494 | ioc->name, __func__); | |
4495 | _debug_dump_mf(mpi_request, | |
4496 | sizeof(Mpi2SasIoUnitControlRequest_t)/4); | |
4497 | if (!(ioc->base_cmds.status & MPT3_CMD_RESET)) | |
eb44552b | 4498 | issue_reset = true; |
f92363d1 SR |
4499 | goto issue_host_reset; |
4500 | } | |
4501 | if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) | |
4502 | memcpy(mpi_reply, ioc->base_cmds.reply, | |
4503 | sizeof(Mpi2SasIoUnitControlReply_t)); | |
4504 | else | |
4505 | memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t)); | |
4506 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; | |
4507 | goto out; | |
4508 | ||
4509 | issue_host_reset: | |
4510 | if (issue_reset) | |
98c56ad3 | 4511 | mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); |
f92363d1 SR |
4512 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; |
4513 | rc = -EFAULT; | |
4514 | out: | |
4515 | mutex_unlock(&ioc->base_cmds.mutex); | |
4516 | return rc; | |
4517 | } | |
4518 | ||
4519 | /** | |
4520 | * mpt3sas_base_scsi_enclosure_processor - sending request to sep device | |
4521 | * @ioc: per adapter object | |
4522 | * @mpi_reply: the reply payload from FW | |
4523 | * @mpi_request: the request payload sent to FW | |
4524 | * | |
4525 | * The SCSI Enclosure Processor request message causes the IOC to | |
4526 | * communicate with SES devices to control LED status signals. | |
4527 | * | |
4528 | * Returns 0 for success, non-zero for failure. | |
4529 | */ | |
4530 | int | |
4531 | mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc, | |
4532 | Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request) | |
4533 | { | |
4534 | u16 smid; | |
4535 | u32 ioc_state; | |
eb44552b | 4536 | bool issue_reset = false; |
f92363d1 SR |
4537 | int rc; |
4538 | void *request; | |
4539 | u16 wait_state_count; | |
4540 | ||
4541 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
4542 | __func__)); | |
4543 | ||
4544 | mutex_lock(&ioc->base_cmds.mutex); | |
4545 | ||
4546 | if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { | |
4547 | pr_err(MPT3SAS_FMT "%s: base_cmd in use\n", | |
4548 | ioc->name, __func__); | |
4549 | rc = -EAGAIN; | |
4550 | goto out; | |
4551 | } | |
4552 | ||
4553 | wait_state_count = 0; | |
4554 | ioc_state = mpt3sas_base_get_iocstate(ioc, 1); | |
4555 | while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { | |
4556 | if (wait_state_count++ == 10) { | |
4557 | pr_err(MPT3SAS_FMT | |
4558 | "%s: failed due to ioc not operational\n", | |
4559 | ioc->name, __func__); | |
4560 | rc = -EFAULT; | |
4561 | goto out; | |
4562 | } | |
4563 | ssleep(1); | |
4564 | ioc_state = mpt3sas_base_get_iocstate(ioc, 1); | |
4565 | pr_info(MPT3SAS_FMT | |
4566 | "%s: waiting for operational state(count=%d)\n", | |
4567 | ioc->name, | |
4568 | __func__, wait_state_count); | |
4569 | } | |
4570 | ||
4571 | smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); | |
4572 | if (!smid) { | |
4573 | pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", | |
4574 | ioc->name, __func__); | |
4575 | rc = -EAGAIN; | |
4576 | goto out; | |
4577 | } | |
4578 | ||
4579 | rc = 0; | |
4580 | ioc->base_cmds.status = MPT3_CMD_PENDING; | |
4581 | request = mpt3sas_base_get_msg_frame(ioc, smid); | |
4582 | ioc->base_cmds.smid = smid; | |
4583 | memcpy(request, mpi_request, sizeof(Mpi2SepReply_t)); | |
4584 | init_completion(&ioc->base_cmds.done); | |
81c16f83 | 4585 | ioc->put_smid_default(ioc, smid); |
8bbb1cf6 | 4586 | wait_for_completion_timeout(&ioc->base_cmds.done, |
f92363d1 SR |
4587 | msecs_to_jiffies(10000)); |
4588 | if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { | |
4589 | pr_err(MPT3SAS_FMT "%s: timeout\n", | |
4590 | ioc->name, __func__); | |
4591 | _debug_dump_mf(mpi_request, | |
4592 | sizeof(Mpi2SepRequest_t)/4); | |
4593 | if (!(ioc->base_cmds.status & MPT3_CMD_RESET)) | |
eb44552b | 4594 | issue_reset = false; |
f92363d1 SR |
4595 | goto issue_host_reset; |
4596 | } | |
4597 | if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) | |
4598 | memcpy(mpi_reply, ioc->base_cmds.reply, | |
4599 | sizeof(Mpi2SepReply_t)); | |
4600 | else | |
4601 | memset(mpi_reply, 0, sizeof(Mpi2SepReply_t)); | |
4602 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; | |
4603 | goto out; | |
4604 | ||
4605 | issue_host_reset: | |
4606 | if (issue_reset) | |
98c56ad3 | 4607 | mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); |
f92363d1 SR |
4608 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; |
4609 | rc = -EFAULT; | |
4610 | out: | |
4611 | mutex_unlock(&ioc->base_cmds.mutex); | |
4612 | return rc; | |
4613 | } | |
4614 | ||
4615 | /** | |
4616 | * _base_get_port_facts - obtain port facts reply and save in ioc | |
4617 | * @ioc: per adapter object | |
f92363d1 SR |
4618 | * |
4619 | * Returns 0 for success, non-zero for failure. | |
4620 | */ | |
4621 | static int | |
98c56ad3 | 4622 | _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port) |
f92363d1 SR |
4623 | { |
4624 | Mpi2PortFactsRequest_t mpi_request; | |
4625 | Mpi2PortFactsReply_t mpi_reply; | |
4626 | struct mpt3sas_port_facts *pfacts; | |
4627 | int mpi_reply_sz, mpi_request_sz, r; | |
4628 | ||
4629 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
4630 | __func__)); | |
4631 | ||
4632 | mpi_reply_sz = sizeof(Mpi2PortFactsReply_t); | |
4633 | mpi_request_sz = sizeof(Mpi2PortFactsRequest_t); | |
4634 | memset(&mpi_request, 0, mpi_request_sz); | |
4635 | mpi_request.Function = MPI2_FUNCTION_PORT_FACTS; | |
4636 | mpi_request.PortNumber = port; | |
4637 | r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, | |
98c56ad3 | 4638 | (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5); |
f92363d1 SR |
4639 | |
4640 | if (r != 0) { | |
4641 | pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", | |
4642 | ioc->name, __func__, r); | |
4643 | return r; | |
4644 | } | |
4645 | ||
4646 | pfacts = &ioc->pfacts[port]; | |
4647 | memset(pfacts, 0, sizeof(struct mpt3sas_port_facts)); | |
4648 | pfacts->PortNumber = mpi_reply.PortNumber; | |
4649 | pfacts->VP_ID = mpi_reply.VP_ID; | |
4650 | pfacts->VF_ID = mpi_reply.VF_ID; | |
4651 | pfacts->MaxPostedCmdBuffers = | |
4652 | le16_to_cpu(mpi_reply.MaxPostedCmdBuffers); | |
4653 | ||
4654 | return 0; | |
4655 | } | |
4656 | ||
4dc8c808 SR |
4657 | /** |
4658 | * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL | |
4659 | * @ioc: per adapter object | |
4660 | * @timeout: | |
4dc8c808 SR |
4661 | * |
4662 | * Returns 0 for success, non-zero for failure. | |
4663 | */ | |
4664 | static int | |
98c56ad3 | 4665 | _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout) |
4dc8c808 SR |
4666 | { |
4667 | u32 ioc_state; | |
4668 | int rc; | |
4669 | ||
4670 | dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name, | |
4671 | __func__)); | |
4672 | ||
4673 | if (ioc->pci_error_recovery) { | |
4674 | dfailprintk(ioc, printk(MPT3SAS_FMT | |
4675 | "%s: host in pci error recovery\n", ioc->name, __func__)); | |
4676 | return -EFAULT; | |
4677 | } | |
4678 | ||
4679 | ioc_state = mpt3sas_base_get_iocstate(ioc, 0); | |
4680 | dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n", | |
4681 | ioc->name, __func__, ioc_state)); | |
4682 | ||
4683 | if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) || | |
4684 | (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) | |
4685 | return 0; | |
4686 | ||
4687 | if (ioc_state & MPI2_DOORBELL_USED) { | |
4688 | dhsprintk(ioc, printk(MPT3SAS_FMT | |
4689 | "unexpected doorbell active!\n", ioc->name)); | |
4690 | goto issue_diag_reset; | |
4691 | } | |
4692 | ||
4693 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { | |
4694 | mpt3sas_base_fault_info(ioc, ioc_state & | |
4695 | MPI2_DOORBELL_DATA_MASK); | |
4696 | goto issue_diag_reset; | |
4697 | } | |
4698 | ||
98c56ad3 | 4699 | ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout); |
4dc8c808 SR |
4700 | if (ioc_state) { |
4701 | dfailprintk(ioc, printk(MPT3SAS_FMT | |
4702 | "%s: failed going to ready state (ioc_state=0x%x)\n", | |
4703 | ioc->name, __func__, ioc_state)); | |
4704 | return -EFAULT; | |
4705 | } | |
4706 | ||
4707 | issue_diag_reset: | |
98c56ad3 | 4708 | rc = _base_diag_reset(ioc); |
4dc8c808 SR |
4709 | return rc; |
4710 | } | |
4711 | ||
f92363d1 SR |
4712 | /** |
4713 | * _base_get_ioc_facts - obtain ioc facts reply and save in ioc | |
4714 | * @ioc: per adapter object | |
f92363d1 SR |
4715 | * |
4716 | * Returns 0 for success, non-zero for failure. | |
4717 | */ | |
4718 | static int | |
98c56ad3 | 4719 | _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
4720 | { |
4721 | Mpi2IOCFactsRequest_t mpi_request; | |
4722 | Mpi2IOCFactsReply_t mpi_reply; | |
4723 | struct mpt3sas_facts *facts; | |
4724 | int mpi_reply_sz, mpi_request_sz, r; | |
4725 | ||
4726 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
4727 | __func__)); | |
4728 | ||
98c56ad3 | 4729 | r = _base_wait_for_iocstate(ioc, 10); |
4dc8c808 SR |
4730 | if (r) { |
4731 | dfailprintk(ioc, printk(MPT3SAS_FMT | |
4732 | "%s: failed getting to correct state\n", | |
4733 | ioc->name, __func__)); | |
4734 | return r; | |
4735 | } | |
f92363d1 SR |
4736 | mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t); |
4737 | mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t); | |
4738 | memset(&mpi_request, 0, mpi_request_sz); | |
4739 | mpi_request.Function = MPI2_FUNCTION_IOC_FACTS; | |
4740 | r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, | |
98c56ad3 | 4741 | (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5); |
f92363d1 SR |
4742 | |
4743 | if (r != 0) { | |
4744 | pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", | |
4745 | ioc->name, __func__, r); | |
4746 | return r; | |
4747 | } | |
4748 | ||
4749 | facts = &ioc->facts; | |
4750 | memset(facts, 0, sizeof(struct mpt3sas_facts)); | |
4751 | facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion); | |
4752 | facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion); | |
4753 | facts->VP_ID = mpi_reply.VP_ID; | |
4754 | facts->VF_ID = mpi_reply.VF_ID; | |
4755 | facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions); | |
4756 | facts->MaxChainDepth = mpi_reply.MaxChainDepth; | |
4757 | facts->WhoInit = mpi_reply.WhoInit; | |
4758 | facts->NumberOfPorts = mpi_reply.NumberOfPorts; | |
4759 | facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors; | |
4760 | facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit); | |
4761 | facts->MaxReplyDescriptorPostQueueDepth = | |
4762 | le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth); | |
4763 | facts->ProductID = le16_to_cpu(mpi_reply.ProductID); | |
4764 | facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities); | |
4765 | if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID)) | |
4766 | ioc->ir_firmware = 1; | |
9b05c91a | 4767 | if ((facts->IOCCapabilities & |
06f5f976 | 4768 | MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE) && (!reset_devices)) |
9b05c91a | 4769 | ioc->rdpq_array_capable = 1; |
81c16f83 SPS |
4770 | if (facts->IOCCapabilities & MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ) |
4771 | ioc->atomic_desc_capable = 1; | |
f92363d1 SR |
4772 | facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word); |
4773 | facts->IOCRequestFrameSize = | |
4774 | le16_to_cpu(mpi_reply.IOCRequestFrameSize); | |
ebb3024e SS |
4775 | if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { |
4776 | facts->IOCMaxChainSegmentSize = | |
4777 | le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize); | |
4778 | } | |
f92363d1 SR |
4779 | facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators); |
4780 | facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets); | |
4781 | ioc->shost->max_id = -1; | |
4782 | facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders); | |
4783 | facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures); | |
4784 | facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags); | |
4785 | facts->HighPriorityCredit = | |
4786 | le16_to_cpu(mpi_reply.HighPriorityCredit); | |
4787 | facts->ReplyFrameSize = mpi_reply.ReplyFrameSize; | |
4788 | facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle); | |
016d5c35 SPS |
4789 | facts->CurrentHostPageSize = mpi_reply.CurrentHostPageSize; |
4790 | ||
4791 | /* | |
4792 | * Get the Page Size from IOC Facts. If it's 0, default to 4k. | |
4793 | */ | |
4794 | ioc->page_size = 1 << facts->CurrentHostPageSize; | |
4795 | if (ioc->page_size == 1) { | |
4796 | pr_info(MPT3SAS_FMT "CurrentHostPageSize is 0: Setting " | |
4797 | "default host page size to 4k\n", ioc->name); | |
4798 | ioc->page_size = 1 << MPT3SAS_HOST_PAGE_SIZE_4K; | |
4799 | } | |
4800 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "CurrentHostPageSize(%d)\n", | |
4801 | ioc->name, facts->CurrentHostPageSize)); | |
f92363d1 SR |
4802 | |
4803 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
4804 | "hba queue depth(%d), max chains per io(%d)\n", | |
4805 | ioc->name, facts->RequestCredit, | |
4806 | facts->MaxChainDepth)); | |
4807 | dinitprintk(ioc, pr_info(MPT3SAS_FMT | |
4808 | "request frame size(%d), reply frame size(%d)\n", ioc->name, | |
4809 | facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4)); | |
4810 | return 0; | |
4811 | } | |
4812 | ||
4813 | /** | |
4814 | * _base_send_ioc_init - send ioc_init to firmware | |
4815 | * @ioc: per adapter object | |
f92363d1 SR |
4816 | * |
4817 | * Returns 0 for success, non-zero for failure. | |
4818 | */ | |
4819 | static int | |
98c56ad3 | 4820 | _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
4821 | { |
4822 | Mpi2IOCInitRequest_t mpi_request; | |
4823 | Mpi2IOCInitReply_t mpi_reply; | |
9b05c91a | 4824 | int i, r = 0; |
23409bd4 | 4825 | ktime_t current_time; |
f92363d1 | 4826 | u16 ioc_status; |
9b05c91a SR |
4827 | u32 reply_post_free_array_sz = 0; |
4828 | Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL; | |
4829 | dma_addr_t reply_post_free_array_dma; | |
f92363d1 SR |
4830 | |
4831 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
4832 | __func__)); | |
4833 | ||
4834 | memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t)); | |
4835 | mpi_request.Function = MPI2_FUNCTION_IOC_INIT; | |
4836 | mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER; | |
4837 | mpi_request.VF_ID = 0; /* TODO */ | |
4838 | mpi_request.VP_ID = 0; | |
d357e84d | 4839 | mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged); |
f92363d1 | 4840 | mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION); |
016d5c35 | 4841 | mpi_request.HostPageSize = MPT3SAS_HOST_PAGE_SIZE_4K; |
f92363d1 SR |
4842 | |
4843 | if (_base_is_controller_msix_enabled(ioc)) | |
4844 | mpi_request.HostMSIxVectors = ioc->reply_queue_count; | |
4845 | mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4); | |
4846 | mpi_request.ReplyDescriptorPostQueueDepth = | |
4847 | cpu_to_le16(ioc->reply_post_queue_depth); | |
4848 | mpi_request.ReplyFreeQueueDepth = | |
4849 | cpu_to_le16(ioc->reply_free_queue_depth); | |
4850 | ||
4851 | mpi_request.SenseBufferAddressHigh = | |
4852 | cpu_to_le32((u64)ioc->sense_dma >> 32); | |
4853 | mpi_request.SystemReplyAddressHigh = | |
4854 | cpu_to_le32((u64)ioc->reply_dma >> 32); | |
4855 | mpi_request.SystemRequestFrameBaseAddress = | |
4856 | cpu_to_le64((u64)ioc->request_dma); | |
4857 | mpi_request.ReplyFreeQueueAddress = | |
4858 | cpu_to_le64((u64)ioc->reply_free_dma); | |
f92363d1 | 4859 | |
9b05c91a SR |
4860 | if (ioc->rdpq_array_enable) { |
4861 | reply_post_free_array_sz = ioc->reply_queue_count * | |
4862 | sizeof(Mpi2IOCInitRDPQArrayEntry); | |
4863 | reply_post_free_array = pci_alloc_consistent(ioc->pdev, | |
4864 | reply_post_free_array_sz, &reply_post_free_array_dma); | |
4865 | if (!reply_post_free_array) { | |
4866 | pr_err(MPT3SAS_FMT | |
4867 | "reply_post_free_array: pci_alloc_consistent failed\n", | |
4868 | ioc->name); | |
4869 | r = -ENOMEM; | |
4870 | goto out; | |
4871 | } | |
4872 | memset(reply_post_free_array, 0, reply_post_free_array_sz); | |
4873 | for (i = 0; i < ioc->reply_queue_count; i++) | |
4874 | reply_post_free_array[i].RDPQBaseAddress = | |
4875 | cpu_to_le64( | |
4876 | (u64)ioc->reply_post[i].reply_post_free_dma); | |
4877 | mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE; | |
4878 | mpi_request.ReplyDescriptorPostQueueAddress = | |
4879 | cpu_to_le64((u64)reply_post_free_array_dma); | |
4880 | } else { | |
4881 | mpi_request.ReplyDescriptorPostQueueAddress = | |
4882 | cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma); | |
4883 | } | |
f92363d1 SR |
4884 | |
4885 | /* This time stamp specifies number of milliseconds | |
4886 | * since epoch ~ midnight January 1, 1970. | |
4887 | */ | |
23409bd4 TR |
4888 | current_time = ktime_get_real(); |
4889 | mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time)); | |
f92363d1 SR |
4890 | |
4891 | if (ioc->logging_level & MPT_DEBUG_INIT) { | |
4892 | __le32 *mfp; | |
4893 | int i; | |
4894 | ||
4895 | mfp = (__le32 *)&mpi_request; | |
4896 | pr_info("\toffset:data\n"); | |
4897 | for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++) | |
4898 | pr_info("\t[0x%02x]:%08x\n", i*4, | |
4899 | le32_to_cpu(mfp[i])); | |
4900 | } | |
4901 | ||
4902 | r = _base_handshake_req_reply_wait(ioc, | |
4903 | sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request, | |
98c56ad3 | 4904 | sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10); |
f92363d1 SR |
4905 | |
4906 | if (r != 0) { | |
4907 | pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", | |
4908 | ioc->name, __func__, r); | |
9b05c91a | 4909 | goto out; |
f92363d1 SR |
4910 | } |
4911 | ||
4912 | ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK; | |
4913 | if (ioc_status != MPI2_IOCSTATUS_SUCCESS || | |
4914 | mpi_reply.IOCLogInfo) { | |
4915 | pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__); | |
4916 | r = -EIO; | |
4917 | } | |
4918 | ||
9b05c91a SR |
4919 | out: |
4920 | if (reply_post_free_array) | |
4921 | pci_free_consistent(ioc->pdev, reply_post_free_array_sz, | |
4922 | reply_post_free_array, | |
4923 | reply_post_free_array_dma); | |
4924 | return r; | |
f92363d1 SR |
4925 | } |
4926 | ||
4927 | /** | |
4928 | * mpt3sas_port_enable_done - command completion routine for port enable | |
4929 | * @ioc: per adapter object | |
4930 | * @smid: system request message index | |
4931 | * @msix_index: MSIX table index supplied by the OS | |
4932 | * @reply: reply message frame(lower 32bit addr) | |
4933 | * | |
4934 | * Return 1 meaning mf should be freed from _base_interrupt | |
4935 | * 0 means the mf is freed from this function. | |
4936 | */ | |
4937 | u8 | |
4938 | mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, | |
4939 | u32 reply) | |
4940 | { | |
4941 | MPI2DefaultReply_t *mpi_reply; | |
4942 | u16 ioc_status; | |
4943 | ||
4944 | if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED) | |
4945 | return 1; | |
4946 | ||
4947 | mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); | |
4948 | if (!mpi_reply) | |
4949 | return 1; | |
4950 | ||
4951 | if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE) | |
4952 | return 1; | |
4953 | ||
4954 | ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING; | |
4955 | ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE; | |
4956 | ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID; | |
4957 | memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); | |
4958 | ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; | |
4959 | if (ioc_status != MPI2_IOCSTATUS_SUCCESS) | |
4960 | ioc->port_enable_failed = 1; | |
4961 | ||
4962 | if (ioc->is_driver_loading) { | |
4963 | if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { | |
4964 | mpt3sas_port_enable_complete(ioc); | |
4965 | return 1; | |
4966 | } else { | |
4967 | ioc->start_scan_failed = ioc_status; | |
4968 | ioc->start_scan = 0; | |
4969 | return 1; | |
4970 | } | |
4971 | } | |
4972 | complete(&ioc->port_enable_cmds.done); | |
4973 | return 1; | |
4974 | } | |
4975 | ||
4976 | /** | |
4977 | * _base_send_port_enable - send port_enable(discovery stuff) to firmware | |
4978 | * @ioc: per adapter object | |
f92363d1 SR |
4979 | * |
4980 | * Returns 0 for success, non-zero for failure. | |
4981 | */ | |
4982 | static int | |
98c56ad3 | 4983 | _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
4984 | { |
4985 | Mpi2PortEnableRequest_t *mpi_request; | |
4986 | Mpi2PortEnableReply_t *mpi_reply; | |
f92363d1 SR |
4987 | int r = 0; |
4988 | u16 smid; | |
4989 | u16 ioc_status; | |
4990 | ||
4991 | pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name); | |
4992 | ||
4993 | if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { | |
4994 | pr_err(MPT3SAS_FMT "%s: internal command already in use\n", | |
4995 | ioc->name, __func__); | |
4996 | return -EAGAIN; | |
4997 | } | |
4998 | ||
4999 | smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); | |
5000 | if (!smid) { | |
5001 | pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", | |
5002 | ioc->name, __func__); | |
5003 | return -EAGAIN; | |
5004 | } | |
5005 | ||
5006 | ioc->port_enable_cmds.status = MPT3_CMD_PENDING; | |
5007 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
5008 | ioc->port_enable_cmds.smid = smid; | |
5009 | memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); | |
5010 | mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; | |
5011 | ||
5012 | init_completion(&ioc->port_enable_cmds.done); | |
81c16f83 | 5013 | ioc->put_smid_default(ioc, smid); |
8bbb1cf6 | 5014 | wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ); |
f92363d1 SR |
5015 | if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) { |
5016 | pr_err(MPT3SAS_FMT "%s: timeout\n", | |
5017 | ioc->name, __func__); | |
5018 | _debug_dump_mf(mpi_request, | |
5019 | sizeof(Mpi2PortEnableRequest_t)/4); | |
5020 | if (ioc->port_enable_cmds.status & MPT3_CMD_RESET) | |
5021 | r = -EFAULT; | |
5022 | else | |
5023 | r = -ETIME; | |
5024 | goto out; | |
5025 | } | |
5026 | ||
5027 | mpi_reply = ioc->port_enable_cmds.reply; | |
5028 | ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; | |
5029 | if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { | |
5030 | pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n", | |
5031 | ioc->name, __func__, ioc_status); | |
5032 | r = -EFAULT; | |
5033 | goto out; | |
5034 | } | |
5035 | ||
5036 | out: | |
5037 | ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; | |
5038 | pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ? | |
5039 | "SUCCESS" : "FAILED")); | |
5040 | return r; | |
5041 | } | |
5042 | ||
5043 | /** | |
5044 | * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply) | |
5045 | * @ioc: per adapter object | |
5046 | * | |
5047 | * Returns 0 for success, non-zero for failure. | |
5048 | */ | |
5049 | int | |
5050 | mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc) | |
5051 | { | |
5052 | Mpi2PortEnableRequest_t *mpi_request; | |
5053 | u16 smid; | |
5054 | ||
5055 | pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name); | |
5056 | ||
5057 | if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { | |
5058 | pr_err(MPT3SAS_FMT "%s: internal command already in use\n", | |
5059 | ioc->name, __func__); | |
5060 | return -EAGAIN; | |
5061 | } | |
5062 | ||
5063 | smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); | |
5064 | if (!smid) { | |
5065 | pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", | |
5066 | ioc->name, __func__); | |
5067 | return -EAGAIN; | |
5068 | } | |
5069 | ||
5070 | ioc->port_enable_cmds.status = MPT3_CMD_PENDING; | |
5071 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
5072 | ioc->port_enable_cmds.smid = smid; | |
5073 | memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); | |
5074 | mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; | |
5075 | ||
81c16f83 | 5076 | ioc->put_smid_default(ioc, smid); |
f92363d1 SR |
5077 | return 0; |
5078 | } | |
5079 | ||
5080 | /** | |
5081 | * _base_determine_wait_on_discovery - desposition | |
5082 | * @ioc: per adapter object | |
5083 | * | |
5084 | * Decide whether to wait on discovery to complete. Used to either | |
5085 | * locate boot device, or report volumes ahead of physical devices. | |
5086 | * | |
5087 | * Returns 1 for wait, 0 for don't wait | |
5088 | */ | |
5089 | static int | |
5090 | _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc) | |
5091 | { | |
5092 | /* We wait for discovery to complete if IR firmware is loaded. | |
5093 | * The sas topology events arrive before PD events, so we need time to | |
5094 | * turn on the bit in ioc->pd_handles to indicate PD | |
5095 | * Also, it maybe required to report Volumes ahead of physical | |
5096 | * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set. | |
5097 | */ | |
5098 | if (ioc->ir_firmware) | |
5099 | return 1; | |
5100 | ||
5101 | /* if no Bios, then we don't need to wait */ | |
5102 | if (!ioc->bios_pg3.BiosVersion) | |
5103 | return 0; | |
5104 | ||
5105 | /* Bios is present, then we drop down here. | |
5106 | * | |
5107 | * If there any entries in the Bios Page 2, then we wait | |
5108 | * for discovery to complete. | |
5109 | */ | |
5110 | ||
5111 | /* Current Boot Device */ | |
5112 | if ((ioc->bios_pg2.CurrentBootDeviceForm & | |
5113 | MPI2_BIOSPAGE2_FORM_MASK) == | |
5114 | MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && | |
5115 | /* Request Boot Device */ | |
5116 | (ioc->bios_pg2.ReqBootDeviceForm & | |
5117 | MPI2_BIOSPAGE2_FORM_MASK) == | |
5118 | MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && | |
5119 | /* Alternate Request Boot Device */ | |
5120 | (ioc->bios_pg2.ReqAltBootDeviceForm & | |
5121 | MPI2_BIOSPAGE2_FORM_MASK) == | |
5122 | MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED) | |
5123 | return 0; | |
5124 | ||
5125 | return 1; | |
5126 | } | |
5127 | ||
5128 | /** | |
5129 | * _base_unmask_events - turn on notification for this event | |
5130 | * @ioc: per adapter object | |
5131 | * @event: firmware event | |
5132 | * | |
5133 | * The mask is stored in ioc->event_masks. | |
5134 | */ | |
5135 | static void | |
5136 | _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event) | |
5137 | { | |
5138 | u32 desired_event; | |
5139 | ||
5140 | if (event >= 128) | |
5141 | return; | |
5142 | ||
5143 | desired_event = (1 << (event % 32)); | |
5144 | ||
5145 | if (event < 32) | |
5146 | ioc->event_masks[0] &= ~desired_event; | |
5147 | else if (event < 64) | |
5148 | ioc->event_masks[1] &= ~desired_event; | |
5149 | else if (event < 96) | |
5150 | ioc->event_masks[2] &= ~desired_event; | |
5151 | else if (event < 128) | |
5152 | ioc->event_masks[3] &= ~desired_event; | |
5153 | } | |
5154 | ||
5155 | /** | |
5156 | * _base_event_notification - send event notification | |
5157 | * @ioc: per adapter object | |
f92363d1 SR |
5158 | * |
5159 | * Returns 0 for success, non-zero for failure. | |
5160 | */ | |
5161 | static int | |
98c56ad3 | 5162 | _base_event_notification(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
5163 | { |
5164 | Mpi2EventNotificationRequest_t *mpi_request; | |
f92363d1 SR |
5165 | u16 smid; |
5166 | int r = 0; | |
5167 | int i; | |
5168 | ||
5169 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
5170 | __func__)); | |
5171 | ||
5172 | if (ioc->base_cmds.status & MPT3_CMD_PENDING) { | |
5173 | pr_err(MPT3SAS_FMT "%s: internal command already in use\n", | |
5174 | ioc->name, __func__); | |
5175 | return -EAGAIN; | |
5176 | } | |
5177 | ||
5178 | smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); | |
5179 | if (!smid) { | |
5180 | pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", | |
5181 | ioc->name, __func__); | |
5182 | return -EAGAIN; | |
5183 | } | |
5184 | ioc->base_cmds.status = MPT3_CMD_PENDING; | |
5185 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
5186 | ioc->base_cmds.smid = smid; | |
5187 | memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t)); | |
5188 | mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; | |
5189 | mpi_request->VF_ID = 0; /* TODO */ | |
5190 | mpi_request->VP_ID = 0; | |
5191 | for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) | |
5192 | mpi_request->EventMasks[i] = | |
5193 | cpu_to_le32(ioc->event_masks[i]); | |
5194 | init_completion(&ioc->base_cmds.done); | |
81c16f83 | 5195 | ioc->put_smid_default(ioc, smid); |
8bbb1cf6 | 5196 | wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ); |
f92363d1 SR |
5197 | if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { |
5198 | pr_err(MPT3SAS_FMT "%s: timeout\n", | |
5199 | ioc->name, __func__); | |
5200 | _debug_dump_mf(mpi_request, | |
5201 | sizeof(Mpi2EventNotificationRequest_t)/4); | |
5202 | if (ioc->base_cmds.status & MPT3_CMD_RESET) | |
5203 | r = -EFAULT; | |
5204 | else | |
5205 | r = -ETIME; | |
5206 | } else | |
5207 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n", | |
5208 | ioc->name, __func__)); | |
5209 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; | |
5210 | return r; | |
5211 | } | |
5212 | ||
5213 | /** | |
5214 | * mpt3sas_base_validate_event_type - validating event types | |
5215 | * @ioc: per adapter object | |
5216 | * @event: firmware event | |
5217 | * | |
5218 | * This will turn on firmware event notification when application | |
5219 | * ask for that event. We don't mask events that are already enabled. | |
5220 | */ | |
5221 | void | |
5222 | mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type) | |
5223 | { | |
5224 | int i, j; | |
5225 | u32 event_mask, desired_event; | |
5226 | u8 send_update_to_fw; | |
5227 | ||
5228 | for (i = 0, send_update_to_fw = 0; i < | |
5229 | MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) { | |
5230 | event_mask = ~event_type[i]; | |
5231 | desired_event = 1; | |
5232 | for (j = 0; j < 32; j++) { | |
5233 | if (!(event_mask & desired_event) && | |
5234 | (ioc->event_masks[i] & desired_event)) { | |
5235 | ioc->event_masks[i] &= ~desired_event; | |
5236 | send_update_to_fw = 1; | |
5237 | } | |
5238 | desired_event = (desired_event << 1); | |
5239 | } | |
5240 | } | |
5241 | ||
5242 | if (!send_update_to_fw) | |
5243 | return; | |
5244 | ||
5245 | mutex_lock(&ioc->base_cmds.mutex); | |
98c56ad3 | 5246 | _base_event_notification(ioc); |
f92363d1 SR |
5247 | mutex_unlock(&ioc->base_cmds.mutex); |
5248 | } | |
5249 | ||
5250 | /** | |
5251 | * _base_diag_reset - the "big hammer" start of day reset | |
5252 | * @ioc: per adapter object | |
f92363d1 SR |
5253 | * |
5254 | * Returns 0 for success, non-zero for failure. | |
5255 | */ | |
5256 | static int | |
98c56ad3 | 5257 | _base_diag_reset(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
5258 | { |
5259 | u32 host_diagnostic; | |
5260 | u32 ioc_state; | |
5261 | u32 count; | |
5262 | u32 hcb_size; | |
5263 | ||
5264 | pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name); | |
5265 | ||
5266 | drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n", | |
5267 | ioc->name)); | |
5268 | ||
5269 | count = 0; | |
5270 | do { | |
5271 | /* Write magic sequence to WriteSequence register | |
5272 | * Loop until in diagnostic mode | |
5273 | */ | |
5274 | drsprintk(ioc, pr_info(MPT3SAS_FMT | |
5275 | "write magic sequence\n", ioc->name)); | |
5276 | writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); | |
5277 | writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence); | |
5278 | writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence); | |
5279 | writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence); | |
5280 | writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence); | |
5281 | writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence); | |
5282 | writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence); | |
5283 | ||
5284 | /* wait 100 msec */ | |
98c56ad3 | 5285 | msleep(100); |
f92363d1 SR |
5286 | |
5287 | if (count++ > 20) | |
5288 | goto out; | |
5289 | ||
5290 | host_diagnostic = readl(&ioc->chip->HostDiagnostic); | |
5291 | drsprintk(ioc, pr_info(MPT3SAS_FMT | |
5292 | "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n", | |
5293 | ioc->name, count, host_diagnostic)); | |
5294 | ||
5295 | } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0); | |
5296 | ||
5297 | hcb_size = readl(&ioc->chip->HCBSize); | |
5298 | ||
5299 | drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n", | |
5300 | ioc->name)); | |
5301 | writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER, | |
5302 | &ioc->chip->HostDiagnostic); | |
5303 | ||
b453ff84 | 5304 | /*This delay allows the chip PCIe hardware time to finish reset tasks*/ |
98c56ad3 | 5305 | msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000); |
f92363d1 | 5306 | |
b453ff84 SR |
5307 | /* Approximately 300 second max wait */ |
5308 | for (count = 0; count < (300000000 / | |
5309 | MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) { | |
f92363d1 SR |
5310 | |
5311 | host_diagnostic = readl(&ioc->chip->HostDiagnostic); | |
5312 | ||
5313 | if (host_diagnostic == 0xFFFFFFFF) | |
5314 | goto out; | |
5315 | if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER)) | |
5316 | break; | |
5317 | ||
98c56ad3 | 5318 | msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000); |
f92363d1 SR |
5319 | } |
5320 | ||
5321 | if (host_diagnostic & MPI2_DIAG_HCB_MODE) { | |
5322 | ||
5323 | drsprintk(ioc, pr_info(MPT3SAS_FMT | |
5324 | "restart the adapter assuming the HCB Address points to good F/W\n", | |
5325 | ioc->name)); | |
5326 | host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK; | |
5327 | host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW; | |
5328 | writel(host_diagnostic, &ioc->chip->HostDiagnostic); | |
5329 | ||
5330 | drsprintk(ioc, pr_info(MPT3SAS_FMT | |
5331 | "re-enable the HCDW\n", ioc->name)); | |
5332 | writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE, | |
5333 | &ioc->chip->HCBSize); | |
5334 | } | |
5335 | ||
5336 | drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n", | |
5337 | ioc->name)); | |
5338 | writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET, | |
5339 | &ioc->chip->HostDiagnostic); | |
5340 | ||
5341 | drsprintk(ioc, pr_info(MPT3SAS_FMT | |
5342 | "disable writes to the diagnostic register\n", ioc->name)); | |
5343 | writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); | |
5344 | ||
5345 | drsprintk(ioc, pr_info(MPT3SAS_FMT | |
5346 | "Wait for FW to go to the READY state\n", ioc->name)); | |
98c56ad3 | 5347 | ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20); |
f92363d1 SR |
5348 | if (ioc_state) { |
5349 | pr_err(MPT3SAS_FMT | |
5350 | "%s: failed going to ready state (ioc_state=0x%x)\n", | |
5351 | ioc->name, __func__, ioc_state); | |
5352 | goto out; | |
5353 | } | |
5354 | ||
5355 | pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name); | |
5356 | return 0; | |
5357 | ||
5358 | out: | |
5359 | pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name); | |
5360 | return -EFAULT; | |
5361 | } | |
5362 | ||
5363 | /** | |
5364 | * _base_make_ioc_ready - put controller in READY state | |
5365 | * @ioc: per adapter object | |
f92363d1 SR |
5366 | * @type: FORCE_BIG_HAMMER or SOFT_RESET |
5367 | * | |
5368 | * Returns 0 for success, non-zero for failure. | |
5369 | */ | |
5370 | static int | |
98c56ad3 | 5371 | _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type) |
f92363d1 SR |
5372 | { |
5373 | u32 ioc_state; | |
5374 | int rc; | |
5375 | int count; | |
5376 | ||
5377 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
5378 | __func__)); | |
5379 | ||
5380 | if (ioc->pci_error_recovery) | |
5381 | return 0; | |
5382 | ||
5383 | ioc_state = mpt3sas_base_get_iocstate(ioc, 0); | |
5384 | dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n", | |
5385 | ioc->name, __func__, ioc_state)); | |
5386 | ||
5387 | /* if in RESET state, it should move to READY state shortly */ | |
5388 | count = 0; | |
5389 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { | |
5390 | while ((ioc_state & MPI2_IOC_STATE_MASK) != | |
5391 | MPI2_IOC_STATE_READY) { | |
5392 | if (count++ == 10) { | |
5393 | pr_err(MPT3SAS_FMT | |
5394 | "%s: failed going to ready state (ioc_state=0x%x)\n", | |
5395 | ioc->name, __func__, ioc_state); | |
5396 | return -EFAULT; | |
5397 | } | |
98c56ad3 | 5398 | ssleep(1); |
f92363d1 SR |
5399 | ioc_state = mpt3sas_base_get_iocstate(ioc, 0); |
5400 | } | |
5401 | } | |
5402 | ||
5403 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) | |
5404 | return 0; | |
5405 | ||
5406 | if (ioc_state & MPI2_DOORBELL_USED) { | |
5407 | dhsprintk(ioc, pr_info(MPT3SAS_FMT | |
5408 | "unexpected doorbell active!\n", | |
5409 | ioc->name)); | |
5410 | goto issue_diag_reset; | |
5411 | } | |
5412 | ||
5413 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { | |
5414 | mpt3sas_base_fault_info(ioc, ioc_state & | |
5415 | MPI2_DOORBELL_DATA_MASK); | |
5416 | goto issue_diag_reset; | |
5417 | } | |
5418 | ||
5419 | if (type == FORCE_BIG_HAMMER) | |
5420 | goto issue_diag_reset; | |
5421 | ||
5422 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) | |
5423 | if (!(_base_send_ioc_reset(ioc, | |
98c56ad3 | 5424 | MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) { |
f92363d1 SR |
5425 | return 0; |
5426 | } | |
5427 | ||
5428 | issue_diag_reset: | |
98c56ad3 | 5429 | rc = _base_diag_reset(ioc); |
f92363d1 SR |
5430 | return rc; |
5431 | } | |
5432 | ||
5433 | /** | |
5434 | * _base_make_ioc_operational - put controller in OPERATIONAL state | |
5435 | * @ioc: per adapter object | |
f92363d1 SR |
5436 | * |
5437 | * Returns 0 for success, non-zero for failure. | |
5438 | */ | |
5439 | static int | |
98c56ad3 | 5440 | _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 | 5441 | { |
5ec8a175 | 5442 | int r, i, index; |
f92363d1 SR |
5443 | unsigned long flags; |
5444 | u32 reply_address; | |
5445 | u16 smid; | |
5446 | struct _tr_list *delayed_tr, *delayed_tr_next; | |
fd0331b3 SS |
5447 | struct _sc_list *delayed_sc, *delayed_sc_next; |
5448 | struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next; | |
7786ab6a | 5449 | u8 hide_flag; |
f92363d1 | 5450 | struct adapter_reply_queue *reply_q; |
5ec8a175 | 5451 | Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig; |
f92363d1 SR |
5452 | |
5453 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
5454 | __func__)); | |
5455 | ||
5456 | /* clean the delayed target reset list */ | |
5457 | list_for_each_entry_safe(delayed_tr, delayed_tr_next, | |
5458 | &ioc->delayed_tr_list, list) { | |
5459 | list_del(&delayed_tr->list); | |
5460 | kfree(delayed_tr); | |
5461 | } | |
5462 | ||
5463 | ||
5464 | list_for_each_entry_safe(delayed_tr, delayed_tr_next, | |
5465 | &ioc->delayed_tr_volume_list, list) { | |
5466 | list_del(&delayed_tr->list); | |
5467 | kfree(delayed_tr); | |
5468 | } | |
5469 | ||
fd0331b3 SS |
5470 | list_for_each_entry_safe(delayed_sc, delayed_sc_next, |
5471 | &ioc->delayed_sc_list, list) { | |
5472 | list_del(&delayed_sc->list); | |
5473 | kfree(delayed_sc); | |
5474 | } | |
5475 | ||
5476 | list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next, | |
5477 | &ioc->delayed_event_ack_list, list) { | |
5478 | list_del(&delayed_event_ack->list); | |
5479 | kfree(delayed_event_ack); | |
5480 | } | |
5481 | ||
f92363d1 SR |
5482 | /* initialize the scsi lookup free list */ |
5483 | spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); | |
5484 | INIT_LIST_HEAD(&ioc->free_list); | |
5485 | smid = 1; | |
5486 | for (i = 0; i < ioc->scsiio_depth; i++, smid++) { | |
5487 | INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list); | |
5488 | ioc->scsi_lookup[i].cb_idx = 0xFF; | |
5489 | ioc->scsi_lookup[i].smid = smid; | |
5490 | ioc->scsi_lookup[i].scmd = NULL; | |
7786ab6a | 5491 | ioc->scsi_lookup[i].direct_io = 0; |
f92363d1 SR |
5492 | list_add_tail(&ioc->scsi_lookup[i].tracker_list, |
5493 | &ioc->free_list); | |
5494 | } | |
5495 | ||
5496 | /* hi-priority queue */ | |
5497 | INIT_LIST_HEAD(&ioc->hpr_free_list); | |
5498 | smid = ioc->hi_priority_smid; | |
5499 | for (i = 0; i < ioc->hi_priority_depth; i++, smid++) { | |
5500 | ioc->hpr_lookup[i].cb_idx = 0xFF; | |
5501 | ioc->hpr_lookup[i].smid = smid; | |
5502 | list_add_tail(&ioc->hpr_lookup[i].tracker_list, | |
5503 | &ioc->hpr_free_list); | |
5504 | } | |
5505 | ||
5506 | /* internal queue */ | |
5507 | INIT_LIST_HEAD(&ioc->internal_free_list); | |
5508 | smid = ioc->internal_smid; | |
5509 | for (i = 0; i < ioc->internal_depth; i++, smid++) { | |
5510 | ioc->internal_lookup[i].cb_idx = 0xFF; | |
5511 | ioc->internal_lookup[i].smid = smid; | |
5512 | list_add_tail(&ioc->internal_lookup[i].tracker_list, | |
5513 | &ioc->internal_free_list); | |
5514 | } | |
5515 | ||
5516 | /* chain pool */ | |
5517 | INIT_LIST_HEAD(&ioc->free_chain_list); | |
5518 | for (i = 0; i < ioc->chain_depth; i++) | |
5519 | list_add_tail(&ioc->chain_lookup[i].tracker_list, | |
5520 | &ioc->free_chain_list); | |
5521 | ||
5522 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
5523 | ||
5524 | /* initialize Reply Free Queue */ | |
5525 | for (i = 0, reply_address = (u32)ioc->reply_dma ; | |
5526 | i < ioc->reply_free_queue_depth ; i++, reply_address += | |
5527 | ioc->reply_sz) | |
5528 | ioc->reply_free[i] = cpu_to_le32(reply_address); | |
5529 | ||
5530 | /* initialize reply queues */ | |
5531 | if (ioc->is_driver_loading) | |
5532 | _base_assign_reply_queues(ioc); | |
5533 | ||
5534 | /* initialize Reply Post Free Queue */ | |
5ec8a175 CO |
5535 | index = 0; |
5536 | reply_post_free_contig = ioc->reply_post[0].reply_post_free; | |
f92363d1 | 5537 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { |
5ec8a175 CO |
5538 | /* |
5539 | * If RDPQ is enabled, switch to the next allocation. | |
5540 | * Otherwise advance within the contiguous region. | |
5541 | */ | |
5542 | if (ioc->rdpq_array_enable) { | |
5543 | reply_q->reply_post_free = | |
5544 | ioc->reply_post[index++].reply_post_free; | |
5545 | } else { | |
5546 | reply_q->reply_post_free = reply_post_free_contig; | |
5547 | reply_post_free_contig += ioc->reply_post_queue_depth; | |
5548 | } | |
5549 | ||
f92363d1 | 5550 | reply_q->reply_post_host_index = 0; |
f92363d1 SR |
5551 | for (i = 0; i < ioc->reply_post_queue_depth; i++) |
5552 | reply_q->reply_post_free[i].Words = | |
5553 | cpu_to_le64(ULLONG_MAX); | |
5554 | if (!_base_is_controller_msix_enabled(ioc)) | |
5555 | goto skip_init_reply_post_free_queue; | |
f92363d1 SR |
5556 | } |
5557 | skip_init_reply_post_free_queue: | |
5558 | ||
98c56ad3 | 5559 | r = _base_send_ioc_init(ioc); |
f92363d1 SR |
5560 | if (r) |
5561 | return r; | |
5562 | ||
5563 | /* initialize reply free host index */ | |
5564 | ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1; | |
5565 | writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex); | |
5566 | ||
5567 | /* initialize reply post host index */ | |
5568 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { | |
0bb337c9 | 5569 | if (ioc->combined_reply_queue) |
fb77bb53 SR |
5570 | writel((reply_q->msix_index & 7)<< |
5571 | MPI2_RPHI_MSIX_INDEX_SHIFT, | |
5572 | ioc->replyPostRegisterIndex[reply_q->msix_index/8]); | |
5573 | else | |
5574 | writel(reply_q->msix_index << | |
5575 | MPI2_RPHI_MSIX_INDEX_SHIFT, | |
5576 | &ioc->chip->ReplyPostHostIndex); | |
5577 | ||
f92363d1 SR |
5578 | if (!_base_is_controller_msix_enabled(ioc)) |
5579 | goto skip_init_reply_post_host_index; | |
5580 | } | |
5581 | ||
5582 | skip_init_reply_post_host_index: | |
5583 | ||
5584 | _base_unmask_interrupts(ioc); | |
98c56ad3 | 5585 | r = _base_event_notification(ioc); |
f92363d1 SR |
5586 | if (r) |
5587 | return r; | |
5588 | ||
98c56ad3 | 5589 | _base_static_config_pages(ioc); |
f92363d1 SR |
5590 | |
5591 | if (ioc->is_driver_loading) { | |
7786ab6a SR |
5592 | |
5593 | if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier | |
5594 | == 0x80) { | |
5595 | hide_flag = (u8) ( | |
5596 | le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) & | |
5597 | MFG_PAGE10_HIDE_SSDS_MASK); | |
5598 | if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK) | |
5599 | ioc->mfg_pg10_hide_flag = hide_flag; | |
5600 | } | |
5601 | ||
f92363d1 SR |
5602 | ioc->wait_for_discovery_to_complete = |
5603 | _base_determine_wait_on_discovery(ioc); | |
5604 | ||
5605 | return r; /* scan_start and scan_finished support */ | |
5606 | } | |
5607 | ||
98c56ad3 | 5608 | r = _base_send_port_enable(ioc); |
f92363d1 SR |
5609 | if (r) |
5610 | return r; | |
5611 | ||
5612 | return r; | |
5613 | } | |
5614 | ||
5615 | /** | |
5616 | * mpt3sas_base_free_resources - free resources controller resources | |
5617 | * @ioc: per adapter object | |
5618 | * | |
5619 | * Return nothing. | |
5620 | */ | |
5621 | void | |
5622 | mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc) | |
5623 | { | |
f92363d1 SR |
5624 | dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, |
5625 | __func__)); | |
5626 | ||
08c4d550 SR |
5627 | /* synchronizing freeing resource with pci_access_mutex lock */ |
5628 | mutex_lock(&ioc->pci_access_mutex); | |
cf9bd21a JL |
5629 | if (ioc->chip_phys && ioc->chip) { |
5630 | _base_mask_interrupts(ioc); | |
5631 | ioc->shost_recovery = 1; | |
98c56ad3 | 5632 | _base_make_ioc_ready(ioc, SOFT_RESET); |
cf9bd21a JL |
5633 | ioc->shost_recovery = 0; |
5634 | } | |
5635 | ||
580d4e31 | 5636 | mpt3sas_base_unmap_resources(ioc); |
08c4d550 | 5637 | mutex_unlock(&ioc->pci_access_mutex); |
f92363d1 SR |
5638 | return; |
5639 | } | |
5640 | ||
5641 | /** | |
5642 | * mpt3sas_base_attach - attach controller instance | |
5643 | * @ioc: per adapter object | |
5644 | * | |
5645 | * Returns 0 for success, non-zero for failure. | |
5646 | */ | |
5647 | int | |
5648 | mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc) | |
5649 | { | |
5650 | int r, i; | |
5651 | int cpu_id, last_cpu_id = 0; | |
5652 | ||
5653 | dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
5654 | __func__)); | |
5655 | ||
5656 | /* setup cpu_msix_table */ | |
5657 | ioc->cpu_count = num_online_cpus(); | |
5658 | for_each_online_cpu(cpu_id) | |
5659 | last_cpu_id = cpu_id; | |
5660 | ioc->cpu_msix_table_sz = last_cpu_id + 1; | |
5661 | ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL); | |
5662 | ioc->reply_queue_count = 1; | |
5663 | if (!ioc->cpu_msix_table) { | |
5664 | dfailprintk(ioc, pr_info(MPT3SAS_FMT | |
5665 | "allocation for cpu_msix_table failed!!!\n", | |
5666 | ioc->name)); | |
5667 | r = -ENOMEM; | |
5668 | goto out_free_resources; | |
5669 | } | |
5670 | ||
7786ab6a SR |
5671 | if (ioc->is_warpdrive) { |
5672 | ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz, | |
5673 | sizeof(resource_size_t *), GFP_KERNEL); | |
5674 | if (!ioc->reply_post_host_index) { | |
5675 | dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation " | |
1d55abc0 HR |
5676 | "for reply_post_host_index failed!!!\n", |
5677 | ioc->name)); | |
7786ab6a SR |
5678 | r = -ENOMEM; |
5679 | goto out_free_resources; | |
5680 | } | |
5681 | } | |
5682 | ||
9b05c91a SR |
5683 | ioc->rdpq_array_enable_assigned = 0; |
5684 | ioc->dma_mask = 0; | |
f92363d1 SR |
5685 | r = mpt3sas_base_map_resources(ioc); |
5686 | if (r) | |
5687 | goto out_free_resources; | |
5688 | ||
f92363d1 | 5689 | pci_set_drvdata(ioc->pdev, ioc->shost); |
98c56ad3 | 5690 | r = _base_get_ioc_facts(ioc); |
f92363d1 SR |
5691 | if (r) |
5692 | goto out_free_resources; | |
5693 | ||
471ef9d4 SR |
5694 | switch (ioc->hba_mpi_version_belonged) { |
5695 | case MPI2_VERSION: | |
5696 | ioc->build_sg_scmd = &_base_build_sg_scmd; | |
5697 | ioc->build_sg = &_base_build_sg; | |
5698 | ioc->build_zero_len_sge = &_base_build_zero_len_sge; | |
5699 | break; | |
5700 | case MPI25_VERSION: | |
b130b0d5 | 5701 | case MPI26_VERSION: |
471ef9d4 SR |
5702 | /* |
5703 | * In SAS3.0, | |
5704 | * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and | |
5705 | * Target Status - all require the IEEE formated scatter gather | |
5706 | * elements. | |
5707 | */ | |
5708 | ioc->build_sg_scmd = &_base_build_sg_scmd_ieee; | |
5709 | ioc->build_sg = &_base_build_sg_ieee; | |
5710 | ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee; | |
5711 | ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t); | |
81c16f83 | 5712 | |
471ef9d4 SR |
5713 | break; |
5714 | } | |
f92363d1 | 5715 | |
81c16f83 SPS |
5716 | if (ioc->atomic_desc_capable) { |
5717 | ioc->put_smid_default = &_base_put_smid_default_atomic; | |
5718 | ioc->put_smid_scsi_io = &_base_put_smid_scsi_io_atomic; | |
5719 | ioc->put_smid_fast_path = &_base_put_smid_fast_path_atomic; | |
5720 | ioc->put_smid_hi_priority = &_base_put_smid_hi_priority_atomic; | |
5721 | } else { | |
5722 | ioc->put_smid_default = &_base_put_smid_default; | |
5723 | ioc->put_smid_scsi_io = &_base_put_smid_scsi_io; | |
5724 | ioc->put_smid_fast_path = &_base_put_smid_fast_path; | |
5725 | ioc->put_smid_hi_priority = &_base_put_smid_hi_priority; | |
5726 | } | |
5727 | ||
5728 | ||
f92363d1 SR |
5729 | /* |
5730 | * These function pointers for other requests that don't | |
5731 | * the require IEEE scatter gather elements. | |
5732 | * | |
5733 | * For example Configuration Pages and SAS IOUNIT Control don't. | |
5734 | */ | |
5735 | ioc->build_sg_mpi = &_base_build_sg; | |
5736 | ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge; | |
5737 | ||
98c56ad3 | 5738 | r = _base_make_ioc_ready(ioc, SOFT_RESET); |
f92363d1 SR |
5739 | if (r) |
5740 | goto out_free_resources; | |
5741 | ||
5742 | ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts, | |
5743 | sizeof(struct mpt3sas_port_facts), GFP_KERNEL); | |
5744 | if (!ioc->pfacts) { | |
5745 | r = -ENOMEM; | |
5746 | goto out_free_resources; | |
5747 | } | |
5748 | ||
5749 | for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) { | |
98c56ad3 | 5750 | r = _base_get_port_facts(ioc, i); |
f92363d1 SR |
5751 | if (r) |
5752 | goto out_free_resources; | |
5753 | } | |
5754 | ||
98c56ad3 | 5755 | r = _base_allocate_memory_pools(ioc); |
f92363d1 SR |
5756 | if (r) |
5757 | goto out_free_resources; | |
5758 | ||
5759 | init_waitqueue_head(&ioc->reset_wq); | |
5760 | ||
5761 | /* allocate memory pd handle bitmask list */ | |
5762 | ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8); | |
5763 | if (ioc->facts.MaxDevHandle % 8) | |
5764 | ioc->pd_handles_sz++; | |
5765 | ioc->pd_handles = kzalloc(ioc->pd_handles_sz, | |
5766 | GFP_KERNEL); | |
5767 | if (!ioc->pd_handles) { | |
5768 | r = -ENOMEM; | |
5769 | goto out_free_resources; | |
5770 | } | |
5771 | ioc->blocking_handles = kzalloc(ioc->pd_handles_sz, | |
5772 | GFP_KERNEL); | |
5773 | if (!ioc->blocking_handles) { | |
5774 | r = -ENOMEM; | |
5775 | goto out_free_resources; | |
5776 | } | |
5777 | ||
c696f7b8 SPS |
5778 | /* allocate memory for pending OS device add list */ |
5779 | ioc->pend_os_device_add_sz = (ioc->facts.MaxDevHandle / 8); | |
5780 | if (ioc->facts.MaxDevHandle % 8) | |
5781 | ioc->pend_os_device_add_sz++; | |
5782 | ioc->pend_os_device_add = kzalloc(ioc->pend_os_device_add_sz, | |
5783 | GFP_KERNEL); | |
5784 | if (!ioc->pend_os_device_add) | |
5785 | goto out_free_resources; | |
5786 | ||
5787 | ioc->device_remove_in_progress_sz = ioc->pend_os_device_add_sz; | |
5788 | ioc->device_remove_in_progress = | |
5789 | kzalloc(ioc->device_remove_in_progress_sz, GFP_KERNEL); | |
5790 | if (!ioc->device_remove_in_progress) | |
5791 | goto out_free_resources; | |
5792 | ||
f92363d1 SR |
5793 | ioc->fwfault_debug = mpt3sas_fwfault_debug; |
5794 | ||
5795 | /* base internal command bits */ | |
5796 | mutex_init(&ioc->base_cmds.mutex); | |
5797 | ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
5798 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; | |
5799 | ||
5800 | /* port_enable command bits */ | |
5801 | ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
5802 | ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; | |
5803 | ||
5804 | /* transport internal command bits */ | |
5805 | ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
5806 | ioc->transport_cmds.status = MPT3_CMD_NOT_USED; | |
5807 | mutex_init(&ioc->transport_cmds.mutex); | |
5808 | ||
5809 | /* scsih internal command bits */ | |
5810 | ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
5811 | ioc->scsih_cmds.status = MPT3_CMD_NOT_USED; | |
5812 | mutex_init(&ioc->scsih_cmds.mutex); | |
5813 | ||
5814 | /* task management internal command bits */ | |
5815 | ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
5816 | ioc->tm_cmds.status = MPT3_CMD_NOT_USED; | |
5817 | mutex_init(&ioc->tm_cmds.mutex); | |
5818 | ||
5819 | /* config page internal command bits */ | |
5820 | ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
5821 | ioc->config_cmds.status = MPT3_CMD_NOT_USED; | |
5822 | mutex_init(&ioc->config_cmds.mutex); | |
5823 | ||
5824 | /* ctl module internal command bits */ | |
5825 | ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
5826 | ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL); | |
5827 | ioc->ctl_cmds.status = MPT3_CMD_NOT_USED; | |
5828 | mutex_init(&ioc->ctl_cmds.mutex); | |
5829 | ||
a5dd7efd CJ |
5830 | if (!ioc->base_cmds.reply || !ioc->port_enable_cmds.reply || |
5831 | !ioc->transport_cmds.reply || !ioc->scsih_cmds.reply || | |
5832 | !ioc->tm_cmds.reply || !ioc->config_cmds.reply || | |
5833 | !ioc->ctl_cmds.reply || !ioc->ctl_cmds.sense) { | |
f92363d1 SR |
5834 | r = -ENOMEM; |
5835 | goto out_free_resources; | |
5836 | } | |
5837 | ||
5838 | for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) | |
5839 | ioc->event_masks[i] = -1; | |
5840 | ||
5841 | /* here we enable the events we care about */ | |
5842 | _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY); | |
5843 | _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE); | |
5844 | _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST); | |
5845 | _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE); | |
5846 | _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE); | |
5847 | _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST); | |
5848 | _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME); | |
5849 | _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK); | |
5850 | _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS); | |
5851 | _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED); | |
2d8ce8c9 | 5852 | _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD); |
b99b1993 | 5853 | _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION); |
f92363d1 | 5854 | |
98c56ad3 | 5855 | r = _base_make_ioc_operational(ioc); |
f92363d1 SR |
5856 | if (r) |
5857 | goto out_free_resources; | |
5858 | ||
16e179bd | 5859 | ioc->non_operational_loop = 0; |
459325c4 | 5860 | ioc->got_task_abort_from_ioctl = 0; |
f92363d1 SR |
5861 | return 0; |
5862 | ||
5863 | out_free_resources: | |
5864 | ||
5865 | ioc->remove_host = 1; | |
5866 | ||
5867 | mpt3sas_base_free_resources(ioc); | |
5868 | _base_release_memory_pools(ioc); | |
5869 | pci_set_drvdata(ioc->pdev, NULL); | |
5870 | kfree(ioc->cpu_msix_table); | |
7786ab6a SR |
5871 | if (ioc->is_warpdrive) |
5872 | kfree(ioc->reply_post_host_index); | |
f92363d1 SR |
5873 | kfree(ioc->pd_handles); |
5874 | kfree(ioc->blocking_handles); | |
c696f7b8 SPS |
5875 | kfree(ioc->device_remove_in_progress); |
5876 | kfree(ioc->pend_os_device_add); | |
f92363d1 SR |
5877 | kfree(ioc->tm_cmds.reply); |
5878 | kfree(ioc->transport_cmds.reply); | |
5879 | kfree(ioc->scsih_cmds.reply); | |
5880 | kfree(ioc->config_cmds.reply); | |
5881 | kfree(ioc->base_cmds.reply); | |
5882 | kfree(ioc->port_enable_cmds.reply); | |
5883 | kfree(ioc->ctl_cmds.reply); | |
5884 | kfree(ioc->ctl_cmds.sense); | |
5885 | kfree(ioc->pfacts); | |
5886 | ioc->ctl_cmds.reply = NULL; | |
5887 | ioc->base_cmds.reply = NULL; | |
5888 | ioc->tm_cmds.reply = NULL; | |
5889 | ioc->scsih_cmds.reply = NULL; | |
5890 | ioc->transport_cmds.reply = NULL; | |
5891 | ioc->config_cmds.reply = NULL; | |
5892 | ioc->pfacts = NULL; | |
5893 | return r; | |
5894 | } | |
5895 | ||
5896 | ||
5897 | /** | |
5898 | * mpt3sas_base_detach - remove controller instance | |
5899 | * @ioc: per adapter object | |
5900 | * | |
5901 | * Return nothing. | |
5902 | */ | |
5903 | void | |
5904 | mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc) | |
5905 | { | |
5906 | dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, | |
5907 | __func__)); | |
5908 | ||
5909 | mpt3sas_base_stop_watchdog(ioc); | |
5910 | mpt3sas_base_free_resources(ioc); | |
5911 | _base_release_memory_pools(ioc); | |
5912 | pci_set_drvdata(ioc->pdev, NULL); | |
5913 | kfree(ioc->cpu_msix_table); | |
7786ab6a SR |
5914 | if (ioc->is_warpdrive) |
5915 | kfree(ioc->reply_post_host_index); | |
f92363d1 SR |
5916 | kfree(ioc->pd_handles); |
5917 | kfree(ioc->blocking_handles); | |
c696f7b8 SPS |
5918 | kfree(ioc->device_remove_in_progress); |
5919 | kfree(ioc->pend_os_device_add); | |
f92363d1 SR |
5920 | kfree(ioc->pfacts); |
5921 | kfree(ioc->ctl_cmds.reply); | |
5922 | kfree(ioc->ctl_cmds.sense); | |
5923 | kfree(ioc->base_cmds.reply); | |
5924 | kfree(ioc->port_enable_cmds.reply); | |
5925 | kfree(ioc->tm_cmds.reply); | |
5926 | kfree(ioc->transport_cmds.reply); | |
5927 | kfree(ioc->scsih_cmds.reply); | |
5928 | kfree(ioc->config_cmds.reply); | |
5929 | } | |
5930 | ||
5931 | /** | |
5932 | * _base_reset_handler - reset callback handler (for base) | |
5933 | * @ioc: per adapter object | |
5934 | * @reset_phase: phase | |
5935 | * | |
5936 | * The handler for doing any required cleanup or initialization. | |
5937 | * | |
5938 | * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET, | |
5939 | * MPT3_IOC_DONE_RESET | |
5940 | * | |
5941 | * Return nothing. | |
5942 | */ | |
5943 | static void | |
5944 | _base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase) | |
5945 | { | |
5946 | mpt3sas_scsih_reset_handler(ioc, reset_phase); | |
5947 | mpt3sas_ctl_reset_handler(ioc, reset_phase); | |
5948 | switch (reset_phase) { | |
5949 | case MPT3_IOC_PRE_RESET: | |
5950 | dtmprintk(ioc, pr_info(MPT3SAS_FMT | |
5951 | "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__)); | |
5952 | break; | |
5953 | case MPT3_IOC_AFTER_RESET: | |
5954 | dtmprintk(ioc, pr_info(MPT3SAS_FMT | |
5955 | "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__)); | |
5956 | if (ioc->transport_cmds.status & MPT3_CMD_PENDING) { | |
5957 | ioc->transport_cmds.status |= MPT3_CMD_RESET; | |
5958 | mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid); | |
5959 | complete(&ioc->transport_cmds.done); | |
5960 | } | |
5961 | if (ioc->base_cmds.status & MPT3_CMD_PENDING) { | |
5962 | ioc->base_cmds.status |= MPT3_CMD_RESET; | |
5963 | mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid); | |
5964 | complete(&ioc->base_cmds.done); | |
5965 | } | |
5966 | if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { | |
5967 | ioc->port_enable_failed = 1; | |
5968 | ioc->port_enable_cmds.status |= MPT3_CMD_RESET; | |
5969 | mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid); | |
5970 | if (ioc->is_driver_loading) { | |
5971 | ioc->start_scan_failed = | |
5972 | MPI2_IOCSTATUS_INTERNAL_ERROR; | |
5973 | ioc->start_scan = 0; | |
5974 | ioc->port_enable_cmds.status = | |
5975 | MPT3_CMD_NOT_USED; | |
5976 | } else | |
5977 | complete(&ioc->port_enable_cmds.done); | |
5978 | } | |
5979 | if (ioc->config_cmds.status & MPT3_CMD_PENDING) { | |
5980 | ioc->config_cmds.status |= MPT3_CMD_RESET; | |
5981 | mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid); | |
5982 | ioc->config_cmds.smid = USHRT_MAX; | |
5983 | complete(&ioc->config_cmds.done); | |
5984 | } | |
5985 | break; | |
5986 | case MPT3_IOC_DONE_RESET: | |
5987 | dtmprintk(ioc, pr_info(MPT3SAS_FMT | |
5988 | "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__)); | |
5989 | break; | |
5990 | } | |
5991 | } | |
5992 | ||
5993 | /** | |
5994 | * _wait_for_commands_to_complete - reset controller | |
5995 | * @ioc: Pointer to MPT_ADAPTER structure | |
f92363d1 SR |
5996 | * |
5997 | * This function waiting(3s) for all pending commands to complete | |
5998 | * prior to putting controller in reset. | |
5999 | */ | |
6000 | static void | |
98c56ad3 | 6001 | _wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
6002 | { |
6003 | u32 ioc_state; | |
6004 | unsigned long flags; | |
6005 | u16 i; | |
6006 | ||
6007 | ioc->pending_io_count = 0; | |
f92363d1 SR |
6008 | |
6009 | ioc_state = mpt3sas_base_get_iocstate(ioc, 0); | |
6010 | if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) | |
6011 | return; | |
6012 | ||
6013 | /* pending command count */ | |
6014 | spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); | |
6015 | for (i = 0; i < ioc->scsiio_depth; i++) | |
6016 | if (ioc->scsi_lookup[i].cb_idx != 0xFF) | |
6017 | ioc->pending_io_count++; | |
6018 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
6019 | ||
6020 | if (!ioc->pending_io_count) | |
6021 | return; | |
6022 | ||
6023 | /* wait for pending commands to complete */ | |
6024 | wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ); | |
6025 | } | |
6026 | ||
6027 | /** | |
6028 | * mpt3sas_base_hard_reset_handler - reset controller | |
6029 | * @ioc: Pointer to MPT_ADAPTER structure | |
f92363d1 SR |
6030 | * @type: FORCE_BIG_HAMMER or SOFT_RESET |
6031 | * | |
6032 | * Returns 0 for success, non-zero for failure. | |
6033 | */ | |
6034 | int | |
98c56ad3 | 6035 | mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, |
f92363d1 SR |
6036 | enum reset_type type) |
6037 | { | |
6038 | int r; | |
6039 | unsigned long flags; | |
6040 | u32 ioc_state; | |
6041 | u8 is_fault = 0, is_trigger = 0; | |
6042 | ||
6043 | dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name, | |
6044 | __func__)); | |
6045 | ||
6046 | if (ioc->pci_error_recovery) { | |
6047 | pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n", | |
6048 | ioc->name, __func__); | |
6049 | r = 0; | |
6050 | goto out_unlocked; | |
6051 | } | |
6052 | ||
6053 | if (mpt3sas_fwfault_debug) | |
6054 | mpt3sas_halt_firmware(ioc); | |
6055 | ||
f92363d1 SR |
6056 | /* wait for an active reset in progress to complete */ |
6057 | if (!mutex_trylock(&ioc->reset_in_progress_mutex)) { | |
6058 | do { | |
6059 | ssleep(1); | |
6060 | } while (ioc->shost_recovery == 1); | |
6061 | dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name, | |
6062 | __func__)); | |
6063 | return ioc->ioc_reset_in_progress_status; | |
6064 | } | |
6065 | ||
6066 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
6067 | ioc->shost_recovery = 1; | |
6068 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
6069 | ||
6070 | if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & | |
6071 | MPT3_DIAG_BUFFER_IS_REGISTERED) && | |
6072 | (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & | |
6073 | MPT3_DIAG_BUFFER_IS_RELEASED))) { | |
6074 | is_trigger = 1; | |
6075 | ioc_state = mpt3sas_base_get_iocstate(ioc, 0); | |
6076 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) | |
6077 | is_fault = 1; | |
6078 | } | |
6079 | _base_reset_handler(ioc, MPT3_IOC_PRE_RESET); | |
98c56ad3 | 6080 | _wait_for_commands_to_complete(ioc); |
f92363d1 | 6081 | _base_mask_interrupts(ioc); |
98c56ad3 | 6082 | r = _base_make_ioc_ready(ioc, type); |
f92363d1 SR |
6083 | if (r) |
6084 | goto out; | |
6085 | _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET); | |
6086 | ||
6087 | /* If this hard reset is called while port enable is active, then | |
6088 | * there is no reason to call make_ioc_operational | |
6089 | */ | |
6090 | if (ioc->is_driver_loading && ioc->port_enable_failed) { | |
6091 | ioc->remove_host = 1; | |
6092 | r = -EFAULT; | |
6093 | goto out; | |
6094 | } | |
98c56ad3 | 6095 | r = _base_get_ioc_facts(ioc); |
f92363d1 SR |
6096 | if (r) |
6097 | goto out; | |
9b05c91a SR |
6098 | |
6099 | if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable) | |
6100 | panic("%s: Issue occurred with flashing controller firmware." | |
6101 | "Please reboot the system and ensure that the correct" | |
6102 | " firmware version is running\n", ioc->name); | |
6103 | ||
98c56ad3 | 6104 | r = _base_make_ioc_operational(ioc); |
f92363d1 SR |
6105 | if (!r) |
6106 | _base_reset_handler(ioc, MPT3_IOC_DONE_RESET); | |
6107 | ||
6108 | out: | |
6109 | dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n", | |
6110 | ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED"))); | |
6111 | ||
6112 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
6113 | ioc->ioc_reset_in_progress_status = r; | |
6114 | ioc->shost_recovery = 0; | |
6115 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
6116 | ioc->ioc_reset_count++; | |
6117 | mutex_unlock(&ioc->reset_in_progress_mutex); | |
6118 | ||
6119 | out_unlocked: | |
6120 | if ((r == 0) && is_trigger) { | |
6121 | if (is_fault) | |
6122 | mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT); | |
6123 | else | |
6124 | mpt3sas_trigger_master(ioc, | |
6125 | MASTER_TRIGGER_ADAPTER_RESET); | |
6126 | } | |
6127 | dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name, | |
6128 | __func__)); | |
6129 | return r; | |
6130 | } |