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f92363d1 SR |
1 | /* |
2 | * This is the Fusion MPT base driver providing common API layer interface | |
3 | * for access to MPT (Message Passing Technology) firmware. | |
4 | * | |
5 | * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c | |
a4ffce0d | 6 | * Copyright (C) 2012-2014 LSI Corporation |
a03bd153 SR |
7 | * Copyright (C) 2013-2014 Avago Technologies |
8 | * (mailto: MPT-FusionLinux.pdl@avagotech.com) | |
f92363d1 SR |
9 | * |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version 2 | |
13 | * of the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * NO WARRANTY | |
21 | * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR | |
22 | * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT | |
23 | * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, | |
24 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is | |
25 | * solely responsible for determining the appropriateness of using and | |
26 | * distributing the Program and assumes all risks associated with its | |
27 | * exercise of rights under this Agreement, including but not limited to | |
28 | * the risks and costs of program errors, damage to or loss of data, | |
29 | * programs or equipment, and unavailability or interruption of operations. | |
30 | ||
31 | * DISCLAIMER OF LIABILITY | |
32 | * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY | |
33 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
34 | * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND | |
35 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR | |
36 | * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE | |
37 | * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED | |
38 | * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES | |
39 | ||
40 | * You should have received a copy of the GNU General Public License | |
41 | * along with this program; if not, write to the Free Software | |
42 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, | |
43 | * USA. | |
44 | */ | |
45 | ||
f92363d1 SR |
46 | #include <linux/kernel.h> |
47 | #include <linux/module.h> | |
48 | #include <linux/errno.h> | |
49 | #include <linux/init.h> | |
50 | #include <linux/slab.h> | |
51 | #include <linux/types.h> | |
52 | #include <linux/pci.h> | |
53 | #include <linux/kdev_t.h> | |
54 | #include <linux/blkdev.h> | |
55 | #include <linux/delay.h> | |
56 | #include <linux/interrupt.h> | |
57 | #include <linux/dma-mapping.h> | |
58 | #include <linux/io.h> | |
59 | #include <linux/time.h> | |
23409bd4 | 60 | #include <linux/ktime.h> |
f92363d1 | 61 | #include <linux/kthread.h> |
016d5c35 | 62 | #include <asm/page.h> /* To get host page size per arch */ |
f92363d1 SR |
63 | |
64 | ||
65 | #include "mpt3sas_base.h" | |
66 | ||
67 | static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS]; | |
68 | ||
69 | ||
70 | #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */ | |
71 | ||
72 | /* maximum controller queue depth */ | |
73 | #define MAX_HBA_QUEUE_DEPTH 30000 | |
74 | #define MAX_CHAIN_DEPTH 100000 | |
75 | static int max_queue_depth = -1; | |
ab9f5adb | 76 | module_param(max_queue_depth, int, 0444); |
f92363d1 SR |
77 | MODULE_PARM_DESC(max_queue_depth, " max controller queue depth "); |
78 | ||
79 | static int max_sgl_entries = -1; | |
ab9f5adb | 80 | module_param(max_sgl_entries, int, 0444); |
f92363d1 SR |
81 | MODULE_PARM_DESC(max_sgl_entries, " max sg entries "); |
82 | ||
83 | static int msix_disable = -1; | |
ab9f5adb | 84 | module_param(msix_disable, int, 0444); |
f92363d1 SR |
85 | MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)"); |
86 | ||
64038301 | 87 | static int smp_affinity_enable = 1; |
ab9f5adb | 88 | module_param(smp_affinity_enable, int, 0444); |
23b389c2 | 89 | MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disable Default: enable(1)"); |
64038301 | 90 | |
fb77bb53 | 91 | static int max_msix_vectors = -1; |
ab9f5adb | 92 | module_param(max_msix_vectors, int, 0444); |
9c500060 | 93 | MODULE_PARM_DESC(max_msix_vectors, |
fb77bb53 | 94 | " max msix vectors"); |
f92363d1 | 95 | |
288addd6 | 96 | static int irqpoll_weight = -1; |
ab9f5adb | 97 | module_param(irqpoll_weight, int, 0444); |
288addd6 SP |
98 | MODULE_PARM_DESC(irqpoll_weight, |
99 | "irq poll weight (default= one fourth of HBA queue depth)"); | |
100 | ||
f92363d1 SR |
101 | static int mpt3sas_fwfault_debug; |
102 | MODULE_PARM_DESC(mpt3sas_fwfault_debug, | |
103 | " enable detection of firmware fault and halt firmware - (default=0)"); | |
104 | ||
ca7e1e9d | 105 | static int perf_mode = -1; |
ab9f5adb | 106 | module_param(perf_mode, int, 0444); |
ca7e1e9d SP |
107 | MODULE_PARM_DESC(perf_mode, |
108 | "Performance mode (only for Aero/Sea Generation), options:\n\t\t" | |
109 | "0 - balanced: high iops mode is enabled &\n\t\t" | |
110 | "interrupt coalescing is enabled only on high iops queues,\n\t\t" | |
111 | "1 - iops: high iops mode is disabled &\n\t\t" | |
112 | "interrupt coalescing is enabled on all queues,\n\t\t" | |
113 | "2 - latency: high iops mode is disabled &\n\t\t" | |
114 | "interrupt coalescing is enabled on all queues with timeout value 0xA,\n" | |
381abbd1 | 115 | "\t\tdefault - default perf_mode is 'balanced'" |
ca7e1e9d SP |
116 | ); |
117 | ||
432bc7ca SR |
118 | static int poll_queues; |
119 | module_param(poll_queues, int, 0444); | |
120 | MODULE_PARM_DESC(poll_queues, "Number of queues to be use for io_uring poll mode.\n\t\t" | |
121 | "This parameter is effective only if host_tagset_enable=1. &\n\t\t" | |
122 | "when poll_queues are enabled then &\n\t\t" | |
123 | "perf_mode is set to latency mode. &\n\t\t" | |
124 | ); | |
125 | ||
ca7e1e9d SP |
126 | enum mpt3sas_perf_mode { |
127 | MPT_PERF_MODE_DEFAULT = -1, | |
128 | MPT_PERF_MODE_BALANCED = 0, | |
129 | MPT_PERF_MODE_IOPS = 1, | |
130 | MPT_PERF_MODE_LATENCY = 2, | |
131 | }; | |
132 | ||
e8c2307e SR |
133 | static int |
134 | _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, | |
135 | u32 ioc_state, int timeout); | |
9b05c91a | 136 | static int |
98c56ad3 | 137 | _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc); |
fce0aa08 | 138 | static void |
fce0aa08 | 139 | _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc); |
f92363d1 | 140 | |
4ca10f3e | 141 | static u32 |
08540650 | 142 | _base_readl_ext_retry(const void __iomem *addr); |
4ca10f3e | 143 | |
d37306ca C |
144 | /** |
145 | * mpt3sas_base_check_cmd_timeout - Function | |
146 | * to check timeout and command termination due | |
147 | * to Host reset. | |
148 | * | |
149 | * @ioc: per adapter object. | |
150 | * @status: Status of issued command. | |
151 | * @mpi_request:mf request pointer. | |
152 | * @sz: size of buffer. | |
153 | * | |
2910a4a9 | 154 | * Return: 1/0 Reset to be done or Not |
d37306ca C |
155 | */ |
156 | u8 | |
157 | mpt3sas_base_check_cmd_timeout(struct MPT3SAS_ADAPTER *ioc, | |
158 | u8 status, void *mpi_request, int sz) | |
159 | { | |
160 | u8 issue_reset = 0; | |
161 | ||
162 | if (!(status & MPT3_CMD_RESET)) | |
163 | issue_reset = 1; | |
164 | ||
919d8a3f JP |
165 | ioc_err(ioc, "Command %s\n", |
166 | issue_reset == 0 ? "terminated due to Host Reset" : "Timeout"); | |
d37306ca C |
167 | _debug_dump_mf(mpi_request, sz); |
168 | ||
169 | return issue_reset; | |
170 | } | |
171 | ||
f92363d1 SR |
172 | /** |
173 | * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug. | |
4beb4867 BVA |
174 | * @val: ? |
175 | * @kp: ? | |
f92363d1 | 176 | * |
4beb4867 | 177 | * Return: ? |
f92363d1 SR |
178 | */ |
179 | static int | |
e4dca7b7 | 180 | _scsih_set_fwfault_debug(const char *val, const struct kernel_param *kp) |
f92363d1 SR |
181 | { |
182 | int ret = param_set_int(val, kp); | |
183 | struct MPT3SAS_ADAPTER *ioc; | |
184 | ||
185 | if (ret) | |
186 | return ret; | |
187 | ||
08c4d550 | 188 | /* global ioc spinlock to protect controller list on list operations */ |
f92363d1 | 189 | pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug); |
08c4d550 | 190 | spin_lock(&gioc_lock); |
f92363d1 SR |
191 | list_for_each_entry(ioc, &mpt3sas_ioc_list, list) |
192 | ioc->fwfault_debug = mpt3sas_fwfault_debug; | |
08c4d550 | 193 | spin_unlock(&gioc_lock); |
f92363d1 SR |
194 | return 0; |
195 | } | |
196 | module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug, | |
197 | param_get_int, &mpt3sas_fwfault_debug, 0644); | |
198 | ||
b8992029 SP |
199 | /** |
200 | * _base_readl_aero - retry readl for max three times. | |
9133d27e | 201 | * @addr: MPT Fusion system interface register address |
b8992029 SP |
202 | * |
203 | * Retry the readl() for max three times if it gets zero value | |
204 | * while reading the system interface register. | |
205 | */ | |
206 | static inline u32 | |
08540650 | 207 | _base_readl_aero(const void __iomem *addr) |
b8992029 SP |
208 | { |
209 | u32 i = 0, ret_val; | |
210 | ||
211 | do { | |
212 | ret_val = readl(addr); | |
213 | i++; | |
214 | } while (ret_val == 0 && i < 3); | |
215 | ||
216 | return ret_val; | |
217 | } | |
218 | ||
4ca10f3e | 219 | static u32 |
08540650 | 220 | _base_readl_ext_retry(const void __iomem *addr) |
4ca10f3e RK |
221 | { |
222 | u32 i, ret_val; | |
223 | ||
224 | for (i = 0 ; i < 30 ; i++) { | |
225 | ret_val = readl(addr); | |
3c978492 RK |
226 | if (ret_val != 0) |
227 | break; | |
4ca10f3e RK |
228 | } |
229 | ||
230 | return ret_val; | |
231 | } | |
232 | ||
b8992029 | 233 | static inline u32 |
08540650 | 234 | _base_readl(const void __iomem *addr) |
b8992029 SP |
235 | { |
236 | return readl(addr); | |
237 | } | |
238 | ||
b4472d71 SPS |
239 | /** |
240 | * _base_clone_reply_to_sys_mem - copies reply to reply free iomem | |
241 | * in BAR0 space. | |
242 | * | |
243 | * @ioc: per adapter object | |
244 | * @reply: reply message frame(lower 32bit addr) | |
245 | * @index: System request message index. | |
b4472d71 SPS |
246 | */ |
247 | static void | |
248 | _base_clone_reply_to_sys_mem(struct MPT3SAS_ADAPTER *ioc, u32 reply, | |
249 | u32 index) | |
250 | { | |
251 | /* | |
252 | * 256 is offset within sys register. | |
253 | * 256 offset MPI frame starts. Max MPI frame supported is 32. | |
254 | * 32 * 128 = 4K. From here, Clone of reply free for mcpu starts | |
255 | */ | |
256 | u16 cmd_credit = ioc->facts.RequestCredit + 1; | |
257 | void __iomem *reply_free_iomem = (void __iomem *)ioc->chip + | |
258 | MPI_FRAME_START_OFFSET + | |
259 | (cmd_credit * ioc->request_sz) + (index * sizeof(u32)); | |
260 | ||
261 | writel(reply, reply_free_iomem); | |
262 | } | |
263 | ||
e5747439 SPS |
264 | /** |
265 | * _base_clone_mpi_to_sys_mem - Writes/copies MPI frames | |
266 | * to system/BAR0 region. | |
267 | * | |
4beb4867 | 268 | * @dst_iomem: Pointer to the destination location in BAR0 space. |
e5747439 SPS |
269 | * @src: Pointer to the Source data. |
270 | * @size: Size of data to be copied. | |
271 | */ | |
272 | static void | |
273 | _base_clone_mpi_to_sys_mem(void *dst_iomem, void *src, u32 size) | |
274 | { | |
275 | int i; | |
276 | u32 *src_virt_mem = (u32 *)src; | |
277 | ||
278 | for (i = 0; i < size/4; i++) | |
279 | writel((u32)src_virt_mem[i], | |
280 | (void __iomem *)dst_iomem + (i * 4)); | |
281 | } | |
282 | ||
182ac784 SPS |
283 | /** |
284 | * _base_clone_to_sys_mem - Writes/copies data to system/BAR0 region | |
285 | * | |
286 | * @dst_iomem: Pointer to the destination location in BAR0 space. | |
287 | * @src: Pointer to the Source data. | |
288 | * @size: Size of data to be copied. | |
289 | */ | |
290 | static void | |
291 | _base_clone_to_sys_mem(void __iomem *dst_iomem, void *src, u32 size) | |
292 | { | |
293 | int i; | |
294 | u32 *src_virt_mem = (u32 *)(src); | |
295 | ||
296 | for (i = 0; i < size/4; i++) | |
297 | writel((u32)src_virt_mem[i], | |
298 | (void __iomem *)dst_iomem + (i * 4)); | |
299 | } | |
300 | ||
22ae5a3c SPS |
301 | /** |
302 | * _base_get_chain - Calculates and Returns virtual chain address | |
303 | * for the provided smid in BAR0 space. | |
304 | * | |
305 | * @ioc: per adapter object | |
306 | * @smid: system request message index | |
307 | * @sge_chain_count: Scatter gather chain count. | |
308 | * | |
4beb4867 | 309 | * Return: the chain address. |
22ae5a3c SPS |
310 | */ |
311 | static inline void __iomem* | |
312 | _base_get_chain(struct MPT3SAS_ADAPTER *ioc, u16 smid, | |
313 | u8 sge_chain_count) | |
314 | { | |
315 | void __iomem *base_chain, *chain_virt; | |
316 | u16 cmd_credit = ioc->facts.RequestCredit + 1; | |
317 | ||
318 | base_chain = (void __iomem *)ioc->chip + MPI_FRAME_START_OFFSET + | |
319 | (cmd_credit * ioc->request_sz) + | |
320 | REPLY_FREE_POOL_SIZE; | |
321 | chain_virt = base_chain + (smid * ioc->facts.MaxChainDepth * | |
322 | ioc->request_sz) + (sge_chain_count * ioc->request_sz); | |
323 | return chain_virt; | |
324 | } | |
325 | ||
326 | /** | |
327 | * _base_get_chain_phys - Calculates and Returns physical address | |
328 | * in BAR0 for scatter gather chains, for | |
329 | * the provided smid. | |
330 | * | |
331 | * @ioc: per adapter object | |
332 | * @smid: system request message index | |
333 | * @sge_chain_count: Scatter gather chain count. | |
334 | * | |
4beb4867 | 335 | * Return: Physical chain address. |
22ae5a3c | 336 | */ |
6f9e09fd | 337 | static inline phys_addr_t |
22ae5a3c SPS |
338 | _base_get_chain_phys(struct MPT3SAS_ADAPTER *ioc, u16 smid, |
339 | u8 sge_chain_count) | |
340 | { | |
6f9e09fd | 341 | phys_addr_t base_chain_phys, chain_phys; |
22ae5a3c SPS |
342 | u16 cmd_credit = ioc->facts.RequestCredit + 1; |
343 | ||
6f9e09fd | 344 | base_chain_phys = ioc->chip_phys + MPI_FRAME_START_OFFSET + |
22ae5a3c SPS |
345 | (cmd_credit * ioc->request_sz) + |
346 | REPLY_FREE_POOL_SIZE; | |
347 | chain_phys = base_chain_phys + (smid * ioc->facts.MaxChainDepth * | |
348 | ioc->request_sz) + (sge_chain_count * ioc->request_sz); | |
349 | return chain_phys; | |
350 | } | |
351 | ||
352 | /** | |
353 | * _base_get_buffer_bar0 - Calculates and Returns BAR0 mapped Host | |
354 | * buffer address for the provided smid. | |
355 | * (Each smid can have 64K starts from 17024) | |
356 | * | |
357 | * @ioc: per adapter object | |
358 | * @smid: system request message index | |
359 | * | |
4beb4867 | 360 | * Return: Pointer to buffer location in BAR0. |
22ae5a3c SPS |
361 | */ |
362 | ||
363 | static void __iomem * | |
364 | _base_get_buffer_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
365 | { | |
366 | u16 cmd_credit = ioc->facts.RequestCredit + 1; | |
367 | // Added extra 1 to reach end of chain. | |
368 | void __iomem *chain_end = _base_get_chain(ioc, | |
369 | cmd_credit + 1, | |
370 | ioc->facts.MaxChainDepth); | |
371 | return chain_end + (smid * 64 * 1024); | |
372 | } | |
373 | ||
374 | /** | |
375 | * _base_get_buffer_phys_bar0 - Calculates and Returns BAR0 mapped | |
376 | * Host buffer Physical address for the provided smid. | |
377 | * (Each smid can have 64K starts from 17024) | |
378 | * | |
379 | * @ioc: per adapter object | |
380 | * @smid: system request message index | |
381 | * | |
4beb4867 | 382 | * Return: Pointer to buffer location in BAR0. |
22ae5a3c | 383 | */ |
6f9e09fd | 384 | static phys_addr_t |
22ae5a3c SPS |
385 | _base_get_buffer_phys_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid) |
386 | { | |
387 | u16 cmd_credit = ioc->facts.RequestCredit + 1; | |
6f9e09fd | 388 | phys_addr_t chain_end_phys = _base_get_chain_phys(ioc, |
22ae5a3c SPS |
389 | cmd_credit + 1, |
390 | ioc->facts.MaxChainDepth); | |
391 | return chain_end_phys + (smid * 64 * 1024); | |
392 | } | |
393 | ||
182ac784 SPS |
394 | /** |
395 | * _base_get_chain_buffer_dma_to_chain_buffer - Iterates chain | |
396 | * lookup list and Provides chain_buffer | |
397 | * address for the matching dma address. | |
398 | * (Each smid can have 64K starts from 17024) | |
399 | * | |
400 | * @ioc: per adapter object | |
401 | * @chain_buffer_dma: Chain buffer dma address. | |
402 | * | |
4beb4867 | 403 | * Return: Pointer to chain buffer. Or Null on Failure. |
182ac784 SPS |
404 | */ |
405 | static void * | |
406 | _base_get_chain_buffer_dma_to_chain_buffer(struct MPT3SAS_ADAPTER *ioc, | |
407 | dma_addr_t chain_buffer_dma) | |
408 | { | |
93204b78 C |
409 | u16 index, j; |
410 | struct chain_tracker *ct; | |
411 | ||
412 | for (index = 0; index < ioc->scsiio_depth; index++) { | |
413 | for (j = 0; j < ioc->chains_needed_per_io; j++) { | |
414 | ct = &ioc->chain_lookup[index].chains_per_smid[j]; | |
415 | if (ct && ct->chain_buffer_dma == chain_buffer_dma) | |
416 | return ct->chain_buffer; | |
417 | } | |
182ac784 | 418 | } |
919d8a3f | 419 | ioc_info(ioc, "Provided chain_buffer_dma address is not in the lookup list\n"); |
182ac784 SPS |
420 | return NULL; |
421 | } | |
422 | ||
423 | /** | |
424 | * _clone_sg_entries - MPI EP's scsiio and config requests | |
425 | * are handled here. Base function for | |
426 | * double buffering, before submitting | |
427 | * the requests. | |
428 | * | |
429 | * @ioc: per adapter object. | |
430 | * @mpi_request: mf request pointer. | |
431 | * @smid: system request message index. | |
182ac784 SPS |
432 | */ |
433 | static void _clone_sg_entries(struct MPT3SAS_ADAPTER *ioc, | |
434 | void *mpi_request, u16 smid) | |
435 | { | |
436 | Mpi2SGESimple32_t *sgel, *sgel_next; | |
437 | u32 sgl_flags, sge_chain_count = 0; | |
355f46b9 | 438 | bool is_write = false; |
182ac784 SPS |
439 | u16 i = 0; |
440 | void __iomem *buffer_iomem; | |
6f9e09fd | 441 | phys_addr_t buffer_iomem_phys; |
182ac784 | 442 | void __iomem *buff_ptr; |
6f9e09fd | 443 | phys_addr_t buff_ptr_phys; |
182ac784 | 444 | void __iomem *dst_chain_addr[MCPU_MAX_CHAINS_PER_IO]; |
6f9e09fd AB |
445 | void *src_chain_addr[MCPU_MAX_CHAINS_PER_IO]; |
446 | phys_addr_t dst_addr_phys; | |
182ac784 SPS |
447 | MPI2RequestHeader_t *request_hdr; |
448 | struct scsi_cmnd *scmd; | |
449 | struct scatterlist *sg_scmd = NULL; | |
450 | int is_scsiio_req = 0; | |
451 | ||
452 | request_hdr = (MPI2RequestHeader_t *) mpi_request; | |
453 | ||
454 | if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST) { | |
455 | Mpi25SCSIIORequest_t *scsiio_request = | |
456 | (Mpi25SCSIIORequest_t *)mpi_request; | |
457 | sgel = (Mpi2SGESimple32_t *) &scsiio_request->SGL; | |
458 | is_scsiio_req = 1; | |
459 | } else if (request_hdr->Function == MPI2_FUNCTION_CONFIG) { | |
460 | Mpi2ConfigRequest_t *config_req = | |
461 | (Mpi2ConfigRequest_t *)mpi_request; | |
462 | sgel = (Mpi2SGESimple32_t *) &config_req->PageBufferSGE; | |
463 | } else | |
464 | return; | |
465 | ||
466 | /* From smid we can get scsi_cmd, once we have sg_scmd, | |
2910a4a9 | 467 | * we just need to get sg_virt and sg_next to get virtual |
182ac784 SPS |
468 | * address associated with sgel->Address. |
469 | */ | |
470 | ||
471 | if (is_scsiio_req) { | |
472 | /* Get scsi_cmd using smid */ | |
473 | scmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid); | |
474 | if (scmd == NULL) { | |
919d8a3f | 475 | ioc_err(ioc, "scmd is NULL\n"); |
182ac784 SPS |
476 | return; |
477 | } | |
478 | ||
479 | /* Get sg_scmd from scmd provided */ | |
480 | sg_scmd = scsi_sglist(scmd); | |
481 | } | |
482 | ||
483 | /* | |
484 | * 0 - 255 System register | |
485 | * 256 - 4352 MPI Frame. (This is based on maxCredit 32) | |
486 | * 4352 - 4864 Reply_free pool (512 byte is reserved | |
487 | * considering maxCredit 32. Reply need extra | |
488 | * room, for mCPU case kept four times of | |
489 | * maxCredit). | |
490 | * 4864 - 17152 SGE chain element. (32cmd * 3 chain of | |
491 | * 128 byte size = 12288) | |
492 | * 17152 - x Host buffer mapped with smid. | |
493 | * (Each smid can have 64K Max IO.) | |
494 | * BAR0+Last 1K MSIX Addr and Data | |
495 | * Total size in use 2113664 bytes of 4MB BAR0 | |
496 | */ | |
497 | ||
498 | buffer_iomem = _base_get_buffer_bar0(ioc, smid); | |
499 | buffer_iomem_phys = _base_get_buffer_phys_bar0(ioc, smid); | |
500 | ||
501 | buff_ptr = buffer_iomem; | |
502 | buff_ptr_phys = buffer_iomem_phys; | |
6f9e09fd | 503 | WARN_ON(buff_ptr_phys > U32_MAX); |
182ac784 | 504 | |
cf6bf971 | 505 | if (le32_to_cpu(sgel->FlagsLength) & |
182ac784 | 506 | (MPI2_SGE_FLAGS_HOST_TO_IOC << MPI2_SGE_FLAGS_SHIFT)) |
355f46b9 | 507 | is_write = true; |
182ac784 SPS |
508 | |
509 | for (i = 0; i < MPT_MIN_PHYS_SEGMENTS + ioc->facts.MaxChainDepth; i++) { | |
510 | ||
cf6bf971 C |
511 | sgl_flags = |
512 | (le32_to_cpu(sgel->FlagsLength) >> MPI2_SGE_FLAGS_SHIFT); | |
182ac784 SPS |
513 | |
514 | switch (sgl_flags & MPI2_SGE_FLAGS_ELEMENT_MASK) { | |
515 | case MPI2_SGE_FLAGS_CHAIN_ELEMENT: | |
516 | /* | |
517 | * Helper function which on passing | |
518 | * chain_buffer_dma returns chain_buffer. Get | |
519 | * the virtual address for sgel->Address | |
520 | */ | |
521 | sgel_next = | |
522 | _base_get_chain_buffer_dma_to_chain_buffer(ioc, | |
cf6bf971 | 523 | le32_to_cpu(sgel->Address)); |
182ac784 SPS |
524 | if (sgel_next == NULL) |
525 | return; | |
526 | /* | |
527 | * This is coping 128 byte chain | |
528 | * frame (not a host buffer) | |
529 | */ | |
530 | dst_chain_addr[sge_chain_count] = | |
531 | _base_get_chain(ioc, | |
532 | smid, sge_chain_count); | |
533 | src_chain_addr[sge_chain_count] = | |
534 | (void *) sgel_next; | |
6f9e09fd | 535 | dst_addr_phys = _base_get_chain_phys(ioc, |
182ac784 | 536 | smid, sge_chain_count); |
6f9e09fd | 537 | WARN_ON(dst_addr_phys > U32_MAX); |
cf6bf971 C |
538 | sgel->Address = |
539 | cpu_to_le32(lower_32_bits(dst_addr_phys)); | |
182ac784 SPS |
540 | sgel = sgel_next; |
541 | sge_chain_count++; | |
542 | break; | |
543 | case MPI2_SGE_FLAGS_SIMPLE_ELEMENT: | |
544 | if (is_write) { | |
545 | if (is_scsiio_req) { | |
546 | _base_clone_to_sys_mem(buff_ptr, | |
547 | sg_virt(sg_scmd), | |
cf6bf971 C |
548 | (le32_to_cpu(sgel->FlagsLength) & |
549 | 0x00ffffff)); | |
6f9e09fd AB |
550 | /* |
551 | * FIXME: this relies on a a zero | |
552 | * PCI mem_offset. | |
553 | */ | |
cf6bf971 C |
554 | sgel->Address = |
555 | cpu_to_le32((u32)buff_ptr_phys); | |
182ac784 SPS |
556 | } else { |
557 | _base_clone_to_sys_mem(buff_ptr, | |
558 | ioc->config_vaddr, | |
cf6bf971 C |
559 | (le32_to_cpu(sgel->FlagsLength) & |
560 | 0x00ffffff)); | |
561 | sgel->Address = | |
562 | cpu_to_le32((u32)buff_ptr_phys); | |
182ac784 SPS |
563 | } |
564 | } | |
cf6bf971 C |
565 | buff_ptr += (le32_to_cpu(sgel->FlagsLength) & |
566 | 0x00ffffff); | |
567 | buff_ptr_phys += (le32_to_cpu(sgel->FlagsLength) & | |
568 | 0x00ffffff); | |
569 | if ((le32_to_cpu(sgel->FlagsLength) & | |
182ac784 SPS |
570 | (MPI2_SGE_FLAGS_END_OF_BUFFER |
571 | << MPI2_SGE_FLAGS_SHIFT))) | |
572 | goto eob_clone_chain; | |
573 | else { | |
574 | /* | |
575 | * Every single element in MPT will have | |
576 | * associated sg_next. Better to sanity that | |
577 | * sg_next is not NULL, but it will be a bug | |
578 | * if it is null. | |
579 | */ | |
580 | if (is_scsiio_req) { | |
581 | sg_scmd = sg_next(sg_scmd); | |
582 | if (sg_scmd) | |
583 | sgel++; | |
584 | else | |
585 | goto eob_clone_chain; | |
586 | } | |
587 | } | |
588 | break; | |
589 | } | |
590 | } | |
591 | ||
592 | eob_clone_chain: | |
593 | for (i = 0; i < sge_chain_count; i++) { | |
594 | if (is_scsiio_req) | |
595 | _base_clone_to_sys_mem(dst_chain_addr[i], | |
596 | src_chain_addr[i], ioc->request_sz); | |
597 | } | |
598 | } | |
599 | ||
f92363d1 SR |
600 | /** |
601 | * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc | |
602 | * @arg: input argument, used to derive ioc | |
603 | * | |
4beb4867 BVA |
604 | * Return: |
605 | * 0 if controller is removed from pci subsystem. | |
606 | * -1 for other case. | |
f92363d1 SR |
607 | */ |
608 | static int mpt3sas_remove_dead_ioc_func(void *arg) | |
609 | { | |
610 | struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg; | |
611 | struct pci_dev *pdev; | |
612 | ||
b51d577a | 613 | if (!ioc) |
f92363d1 SR |
614 | return -1; |
615 | ||
616 | pdev = ioc->pdev; | |
b51d577a | 617 | if (!pdev) |
f92363d1 | 618 | return -1; |
64cdb418 | 619 | pci_stop_and_remove_bus_device_locked(pdev); |
f92363d1 SR |
620 | return 0; |
621 | } | |
622 | ||
f98790c0 SP |
623 | /** |
624 | * _base_sync_drv_fw_timestamp - Sync Drive-Fw TimeStamp. | |
625 | * @ioc: Per Adapter Object | |
626 | * | |
2910a4a9 | 627 | * Return: nothing. |
f98790c0 SP |
628 | */ |
629 | static void _base_sync_drv_fw_timestamp(struct MPT3SAS_ADAPTER *ioc) | |
630 | { | |
631 | Mpi26IoUnitControlRequest_t *mpi_request; | |
632 | Mpi26IoUnitControlReply_t *mpi_reply; | |
633 | u16 smid; | |
634 | ktime_t current_time; | |
635 | u64 TimeStamp = 0; | |
636 | u8 issue_reset = 0; | |
637 | ||
638 | mutex_lock(&ioc->scsih_cmds.mutex); | |
639 | if (ioc->scsih_cmds.status != MPT3_CMD_NOT_USED) { | |
640 | ioc_err(ioc, "scsih_cmd in use %s\n", __func__); | |
641 | goto out; | |
642 | } | |
643 | ioc->scsih_cmds.status = MPT3_CMD_PENDING; | |
644 | smid = mpt3sas_base_get_smid(ioc, ioc->scsih_cb_idx); | |
645 | if (!smid) { | |
646 | ioc_err(ioc, "Failed obtaining a smid %s\n", __func__); | |
647 | ioc->scsih_cmds.status = MPT3_CMD_NOT_USED; | |
648 | goto out; | |
649 | } | |
650 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
651 | ioc->scsih_cmds.smid = smid; | |
652 | memset(mpi_request, 0, sizeof(Mpi26IoUnitControlRequest_t)); | |
653 | mpi_request->Function = MPI2_FUNCTION_IO_UNIT_CONTROL; | |
654 | mpi_request->Operation = MPI26_CTRL_OP_SET_IOC_PARAMETER; | |
655 | mpi_request->IOCParameter = MPI26_SET_IOC_PARAMETER_SYNC_TIMESTAMP; | |
656 | current_time = ktime_get_real(); | |
657 | TimeStamp = ktime_to_ms(current_time); | |
5ecae9f8 SR |
658 | mpi_request->Reserved7 = cpu_to_le32(TimeStamp >> 32); |
659 | mpi_request->IOCParameterValue = cpu_to_le32(TimeStamp & 0xFFFFFFFF); | |
f98790c0 SP |
660 | init_completion(&ioc->scsih_cmds.done); |
661 | ioc->put_smid_default(ioc, smid); | |
662 | dinitprintk(ioc, ioc_info(ioc, | |
663 | "Io Unit Control Sync TimeStamp (sending), @time %lld ms\n", | |
664 | TimeStamp)); | |
665 | wait_for_completion_timeout(&ioc->scsih_cmds.done, | |
666 | MPT3SAS_TIMESYNC_TIMEOUT_SECONDS*HZ); | |
667 | if (!(ioc->scsih_cmds.status & MPT3_CMD_COMPLETE)) { | |
668 | mpt3sas_check_cmd_timeout(ioc, | |
669 | ioc->scsih_cmds.status, mpi_request, | |
670 | sizeof(Mpi2SasIoUnitControlRequest_t)/4, issue_reset); | |
671 | goto issue_host_reset; | |
672 | } | |
673 | if (ioc->scsih_cmds.status & MPT3_CMD_REPLY_VALID) { | |
674 | mpi_reply = ioc->scsih_cmds.reply; | |
675 | dinitprintk(ioc, ioc_info(ioc, | |
676 | "Io Unit Control sync timestamp (complete): ioc_status(0x%04x), loginfo(0x%08x)\n", | |
677 | le16_to_cpu(mpi_reply->IOCStatus), | |
678 | le32_to_cpu(mpi_reply->IOCLogInfo))); | |
679 | } | |
680 | issue_host_reset: | |
681 | if (issue_reset) | |
682 | mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); | |
683 | ioc->scsih_cmds.status = MPT3_CMD_NOT_USED; | |
684 | out: | |
685 | mutex_unlock(&ioc->scsih_cmds.mutex); | |
686 | } | |
687 | ||
f92363d1 SR |
688 | /** |
689 | * _base_fault_reset_work - workq handling ioc fault conditions | |
690 | * @work: input argument, used to derive ioc | |
f92363d1 | 691 | * |
4beb4867 | 692 | * Context: sleep. |
f92363d1 SR |
693 | */ |
694 | static void | |
695 | _base_fault_reset_work(struct work_struct *work) | |
696 | { | |
697 | struct MPT3SAS_ADAPTER *ioc = | |
698 | container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work); | |
699 | unsigned long flags; | |
700 | u32 doorbell; | |
701 | int rc; | |
702 | struct task_struct *p; | |
703 | ||
704 | ||
705 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
fce0aa08 SR |
706 | if ((ioc->shost_recovery && (ioc->ioc_coredump_loop == 0)) || |
707 | ioc->pci_error_recovery) | |
f92363d1 SR |
708 | goto rearm_timer; |
709 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
710 | ||
711 | doorbell = mpt3sas_base_get_iocstate(ioc, 0); | |
712 | if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) { | |
919d8a3f | 713 | ioc_err(ioc, "SAS host is non-operational !!!!\n"); |
f92363d1 | 714 | |
16e179bd SR |
715 | /* It may be possible that EEH recovery can resolve some of |
716 | * pci bus failure issues rather removing the dead ioc function | |
717 | * by considering controller is in a non-operational state. So | |
718 | * here priority is given to the EEH recovery. If it doesn't | |
719 | * not resolve this issue, mpt3sas driver will consider this | |
720 | * controller to non-operational state and remove the dead ioc | |
721 | * function. | |
722 | */ | |
723 | if (ioc->non_operational_loop++ < 5) { | |
724 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, | |
725 | flags); | |
726 | goto rearm_timer; | |
727 | } | |
728 | ||
f92363d1 SR |
729 | /* |
730 | * Call _scsih_flush_pending_cmds callback so that we flush all | |
2910a4a9 | 731 | * pending commands back to OS. This call is required to avoid |
f92363d1 SR |
732 | * deadlock at block layer. Dead IOC will fail to do diag reset, |
733 | * and this call is safe since dead ioc will never return any | |
734 | * command back from HW. | |
735 | */ | |
432bc7ca | 736 | mpt3sas_base_pause_mq_polling(ioc); |
f92363d1 SR |
737 | ioc->schedule_dead_ioc_flush_running_cmds(ioc); |
738 | /* | |
739 | * Set remove_host flag early since kernel thread will | |
740 | * take some time to execute. | |
741 | */ | |
742 | ioc->remove_host = 1; | |
743 | /*Remove the Dead Host */ | |
744 | p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc, | |
c84b06a4 | 745 | "%s_dead_ioc_%d", ioc->driver_name, ioc->id); |
f92363d1 | 746 | if (IS_ERR(p)) |
919d8a3f JP |
747 | ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread failed !!!!\n", |
748 | __func__); | |
f92363d1 | 749 | else |
919d8a3f JP |
750 | ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread success !!!!\n", |
751 | __func__); | |
f92363d1 SR |
752 | return; /* don't rearm timer */ |
753 | } | |
754 | ||
fce0aa08 SR |
755 | if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) { |
756 | u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ? | |
757 | ioc->manu_pg11.CoreDumpTOSec : | |
758 | MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS; | |
759 | ||
760 | timeout /= (FAULT_POLLING_INTERVAL/1000); | |
761 | ||
762 | if (ioc->ioc_coredump_loop == 0) { | |
c5977718 | 763 | mpt3sas_print_coredump_info(ioc, |
fce0aa08 SR |
764 | doorbell & MPI2_DOORBELL_DATA_MASK); |
765 | /* do not accept any IOs and disable the interrupts */ | |
766 | spin_lock_irqsave( | |
767 | &ioc->ioc_reset_in_progress_lock, flags); | |
768 | ioc->shost_recovery = 1; | |
769 | spin_unlock_irqrestore( | |
770 | &ioc->ioc_reset_in_progress_lock, flags); | |
5afa9d44 | 771 | mpt3sas_base_mask_interrupts(ioc); |
432bc7ca | 772 | mpt3sas_base_pause_mq_polling(ioc); |
fce0aa08 SR |
773 | _base_clear_outstanding_commands(ioc); |
774 | } | |
775 | ||
776 | ioc_info(ioc, "%s: CoreDump loop %d.", | |
777 | __func__, ioc->ioc_coredump_loop); | |
778 | ||
779 | /* Wait until CoreDump completes or times out */ | |
780 | if (ioc->ioc_coredump_loop++ < timeout) { | |
781 | spin_lock_irqsave( | |
782 | &ioc->ioc_reset_in_progress_lock, flags); | |
783 | goto rearm_timer; | |
784 | } | |
785 | } | |
16e179bd | 786 | |
fce0aa08 SR |
787 | if (ioc->ioc_coredump_loop) { |
788 | if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_COREDUMP) | |
789 | ioc_err(ioc, "%s: CoreDump completed. LoopCount: %d", | |
790 | __func__, ioc->ioc_coredump_loop); | |
791 | else | |
792 | ioc_err(ioc, "%s: CoreDump Timed out. LoopCount: %d", | |
793 | __func__, ioc->ioc_coredump_loop); | |
794 | ioc->ioc_coredump_loop = MPT3SAS_COREDUMP_LOOP_DONE; | |
795 | } | |
796 | ioc->non_operational_loop = 0; | |
f92363d1 | 797 | if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) { |
98c56ad3 | 798 | rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); |
919d8a3f JP |
799 | ioc_warn(ioc, "%s: hard reset: %s\n", |
800 | __func__, rc == 0 ? "success" : "failed"); | |
f92363d1 | 801 | doorbell = mpt3sas_base_get_iocstate(ioc, 0); |
fce0aa08 | 802 | if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { |
c5977718 | 803 | mpt3sas_print_fault_code(ioc, doorbell & |
f92363d1 | 804 | MPI2_DOORBELL_DATA_MASK); |
fce0aa08 SR |
805 | } else if ((doorbell & MPI2_IOC_STATE_MASK) == |
806 | MPI2_IOC_STATE_COREDUMP) | |
c5977718 | 807 | mpt3sas_print_coredump_info(ioc, doorbell & |
fce0aa08 | 808 | MPI2_DOORBELL_DATA_MASK); |
f92363d1 SR |
809 | if (rc && (doorbell & MPI2_IOC_STATE_MASK) != |
810 | MPI2_IOC_STATE_OPERATIONAL) | |
811 | return; /* don't rearm timer */ | |
812 | } | |
fce0aa08 | 813 | ioc->ioc_coredump_loop = 0; |
f98790c0 SP |
814 | if (ioc->time_sync_interval && |
815 | ++ioc->timestamp_update_count >= ioc->time_sync_interval) { | |
816 | ioc->timestamp_update_count = 0; | |
817 | _base_sync_drv_fw_timestamp(ioc); | |
818 | } | |
f92363d1 SR |
819 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); |
820 | rearm_timer: | |
821 | if (ioc->fault_reset_work_q) | |
822 | queue_delayed_work(ioc->fault_reset_work_q, | |
823 | &ioc->fault_reset_work, | |
824 | msecs_to_jiffies(FAULT_POLLING_INTERVAL)); | |
825 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
826 | } | |
827 | ||
828 | /** | |
829 | * mpt3sas_base_start_watchdog - start the fault_reset_work_q | |
830 | * @ioc: per adapter object | |
f92363d1 | 831 | * |
4beb4867 | 832 | * Context: sleep. |
f92363d1 SR |
833 | */ |
834 | void | |
835 | mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc) | |
836 | { | |
837 | unsigned long flags; | |
838 | ||
839 | if (ioc->fault_reset_work_q) | |
840 | return; | |
841 | ||
f98790c0 | 842 | ioc->timestamp_update_count = 0; |
f92363d1 SR |
843 | /* initialize fault polling */ |
844 | ||
845 | INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work); | |
846 | snprintf(ioc->fault_reset_work_q_name, | |
c84b06a4 SR |
847 | sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status", |
848 | ioc->driver_name, ioc->id); | |
f92363d1 SR |
849 | ioc->fault_reset_work_q = |
850 | create_singlethread_workqueue(ioc->fault_reset_work_q_name); | |
851 | if (!ioc->fault_reset_work_q) { | |
919d8a3f | 852 | ioc_err(ioc, "%s: failed (line=%d)\n", __func__, __LINE__); |
199fd79a | 853 | return; |
f92363d1 SR |
854 | } |
855 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
856 | if (ioc->fault_reset_work_q) | |
857 | queue_delayed_work(ioc->fault_reset_work_q, | |
858 | &ioc->fault_reset_work, | |
859 | msecs_to_jiffies(FAULT_POLLING_INTERVAL)); | |
860 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
861 | } | |
862 | ||
863 | /** | |
864 | * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q | |
865 | * @ioc: per adapter object | |
f92363d1 | 866 | * |
4beb4867 | 867 | * Context: sleep. |
f92363d1 SR |
868 | */ |
869 | void | |
870 | mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc) | |
871 | { | |
872 | unsigned long flags; | |
873 | struct workqueue_struct *wq; | |
874 | ||
875 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
876 | wq = ioc->fault_reset_work_q; | |
877 | ioc->fault_reset_work_q = NULL; | |
878 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
879 | if (wq) { | |
4dc06fd8 | 880 | if (!cancel_delayed_work_sync(&ioc->fault_reset_work)) |
f92363d1 SR |
881 | flush_workqueue(wq); |
882 | destroy_workqueue(wq); | |
883 | } | |
884 | } | |
885 | ||
886 | /** | |
887 | * mpt3sas_base_fault_info - verbose translation of firmware FAULT code | |
888 | * @ioc: per adapter object | |
889 | * @fault_code: fault code | |
f92363d1 SR |
890 | */ |
891 | void | |
efef34cb | 892 | mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc, u16 fault_code) |
f92363d1 | 893 | { |
919d8a3f | 894 | ioc_err(ioc, "fault_state(0x%04x)!\n", fault_code); |
f92363d1 SR |
895 | } |
896 | ||
e8c2307e SR |
897 | /** |
898 | * mpt3sas_base_coredump_info - verbose translation of firmware CoreDump state | |
899 | * @ioc: per adapter object | |
900 | * @fault_code: fault code | |
901 | * | |
2910a4a9 | 902 | * Return: nothing. |
e8c2307e SR |
903 | */ |
904 | void | |
905 | mpt3sas_base_coredump_info(struct MPT3SAS_ADAPTER *ioc, u16 fault_code) | |
906 | { | |
907 | ioc_err(ioc, "coredump_state(0x%04x)!\n", fault_code); | |
908 | } | |
909 | ||
910 | /** | |
911 | * mpt3sas_base_wait_for_coredump_completion - Wait until coredump | |
912 | * completes or times out | |
913 | * @ioc: per adapter object | |
9133d27e | 914 | * @caller: caller function name |
e8c2307e | 915 | * |
2910a4a9 | 916 | * Return: 0 for success, non-zero for failure. |
e8c2307e SR |
917 | */ |
918 | int | |
919 | mpt3sas_base_wait_for_coredump_completion(struct MPT3SAS_ADAPTER *ioc, | |
920 | const char *caller) | |
921 | { | |
922 | u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ? | |
923 | ioc->manu_pg11.CoreDumpTOSec : | |
924 | MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS; | |
925 | ||
926 | int ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_FAULT, | |
927 | timeout); | |
928 | ||
929 | if (ioc_state) | |
930 | ioc_err(ioc, | |
931 | "%s: CoreDump timed out. (ioc_state=0x%x)\n", | |
932 | caller, ioc_state); | |
933 | else | |
934 | ioc_info(ioc, | |
935 | "%s: CoreDump completed. (ioc_state=0x%x)\n", | |
936 | caller, ioc_state); | |
937 | ||
938 | return ioc_state; | |
939 | } | |
940 | ||
f92363d1 SR |
941 | /** |
942 | * mpt3sas_halt_firmware - halt's mpt controller firmware | |
943 | * @ioc: per adapter object | |
944 | * | |
945 | * For debugging timeout related issues. Writing 0xCOFFEE00 | |
946 | * to the doorbell register will halt controller firmware. With | |
947 | * the purpose to stop both driver and firmware, the enduser can | |
948 | * obtain a ring buffer from controller UART. | |
949 | */ | |
950 | void | |
951 | mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc) | |
952 | { | |
953 | u32 doorbell; | |
954 | ||
955 | if (!ioc->fwfault_debug) | |
956 | return; | |
957 | ||
958 | dump_stack(); | |
959 | ||
4ca10f3e | 960 | doorbell = ioc->base_readl_ext_retry(&ioc->chip->Doorbell); |
e8c2307e | 961 | if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { |
c5977718 | 962 | mpt3sas_print_fault_code(ioc, doorbell & |
e8c2307e SR |
963 | MPI2_DOORBELL_DATA_MASK); |
964 | } else if ((doorbell & MPI2_IOC_STATE_MASK) == | |
965 | MPI2_IOC_STATE_COREDUMP) { | |
c5977718 | 966 | mpt3sas_print_coredump_info(ioc, doorbell & |
e8c2307e SR |
967 | MPI2_DOORBELL_DATA_MASK); |
968 | } else { | |
f92363d1 | 969 | writel(0xC0FFEE00, &ioc->chip->Doorbell); |
919d8a3f | 970 | ioc_err(ioc, "Firmware is halted due to command timeout\n"); |
f92363d1 SR |
971 | } |
972 | ||
973 | if (ioc->fwfault_debug == 2) | |
974 | for (;;) | |
975 | ; | |
976 | else | |
977 | panic("panic in %s\n", __func__); | |
978 | } | |
979 | ||
f92363d1 SR |
980 | /** |
981 | * _base_sas_ioc_info - verbose translation of the ioc status | |
982 | * @ioc: per adapter object | |
983 | * @mpi_reply: reply mf payload returned from firmware | |
984 | * @request_hdr: request mf | |
f92363d1 SR |
985 | */ |
986 | static void | |
987 | _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply, | |
988 | MPI2RequestHeader_t *request_hdr) | |
989 | { | |
990 | u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & | |
991 | MPI2_IOCSTATUS_MASK; | |
992 | char *desc = NULL; | |
993 | u16 frame_sz; | |
994 | char *func_str = NULL; | |
995 | ||
996 | /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */ | |
997 | if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST || | |
998 | request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH || | |
999 | request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION) | |
1000 | return; | |
1001 | ||
1002 | if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE) | |
1003 | return; | |
aec93e8e SP |
1004 | /* |
1005 | * Older Firmware version doesn't support driver trigger pages. | |
1006 | * So, skip displaying 'config invalid type' type | |
1007 | * of error message. | |
1008 | */ | |
1009 | if (request_hdr->Function == MPI2_FUNCTION_CONFIG) { | |
1010 | Mpi2ConfigRequest_t *rqst = (Mpi2ConfigRequest_t *)request_hdr; | |
1011 | ||
1012 | if ((rqst->ExtPageType == | |
1013 | MPI2_CONFIG_EXTPAGETYPE_DRIVER_PERSISTENT_TRIGGER) && | |
1014 | !(ioc->logging_level & MPT_DEBUG_CONFIG)) { | |
1015 | return; | |
1016 | } | |
1017 | } | |
f92363d1 SR |
1018 | |
1019 | switch (ioc_status) { | |
1020 | ||
1021 | /**************************************************************************** | |
1022 | * Common IOCStatus values for all replies | |
1023 | ****************************************************************************/ | |
1024 | ||
1025 | case MPI2_IOCSTATUS_INVALID_FUNCTION: | |
1026 | desc = "invalid function"; | |
1027 | break; | |
1028 | case MPI2_IOCSTATUS_BUSY: | |
1029 | desc = "busy"; | |
1030 | break; | |
1031 | case MPI2_IOCSTATUS_INVALID_SGL: | |
1032 | desc = "invalid sgl"; | |
1033 | break; | |
1034 | case MPI2_IOCSTATUS_INTERNAL_ERROR: | |
1035 | desc = "internal error"; | |
1036 | break; | |
1037 | case MPI2_IOCSTATUS_INVALID_VPID: | |
1038 | desc = "invalid vpid"; | |
1039 | break; | |
1040 | case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: | |
1041 | desc = "insufficient resources"; | |
1042 | break; | |
b130b0d5 SS |
1043 | case MPI2_IOCSTATUS_INSUFFICIENT_POWER: |
1044 | desc = "insufficient power"; | |
1045 | break; | |
f92363d1 SR |
1046 | case MPI2_IOCSTATUS_INVALID_FIELD: |
1047 | desc = "invalid field"; | |
1048 | break; | |
1049 | case MPI2_IOCSTATUS_INVALID_STATE: | |
1050 | desc = "invalid state"; | |
1051 | break; | |
1052 | case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED: | |
1053 | desc = "op state not supported"; | |
1054 | break; | |
1055 | ||
1056 | /**************************************************************************** | |
1057 | * Config IOCStatus values | |
1058 | ****************************************************************************/ | |
1059 | ||
1060 | case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION: | |
1061 | desc = "config invalid action"; | |
1062 | break; | |
1063 | case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE: | |
1064 | desc = "config invalid type"; | |
1065 | break; | |
1066 | case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE: | |
1067 | desc = "config invalid page"; | |
1068 | break; | |
1069 | case MPI2_IOCSTATUS_CONFIG_INVALID_DATA: | |
1070 | desc = "config invalid data"; | |
1071 | break; | |
1072 | case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS: | |
1073 | desc = "config no defaults"; | |
1074 | break; | |
1075 | case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT: | |
efef34cb | 1076 | desc = "config can't commit"; |
f92363d1 SR |
1077 | break; |
1078 | ||
1079 | /**************************************************************************** | |
1080 | * SCSI IO Reply | |
1081 | ****************************************************************************/ | |
1082 | ||
1083 | case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR: | |
1084 | case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE: | |
1085 | case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: | |
1086 | case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: | |
1087 | case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: | |
1088 | case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: | |
1089 | case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: | |
1090 | case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: | |
1091 | case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: | |
1092 | case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED: | |
1093 | case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: | |
1094 | case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: | |
1095 | break; | |
1096 | ||
1097 | /**************************************************************************** | |
1098 | * For use by SCSI Initiator and SCSI Target end-to-end data protection | |
1099 | ****************************************************************************/ | |
1100 | ||
1101 | case MPI2_IOCSTATUS_EEDP_GUARD_ERROR: | |
1102 | desc = "eedp guard error"; | |
1103 | break; | |
1104 | case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR: | |
1105 | desc = "eedp ref tag error"; | |
1106 | break; | |
1107 | case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR: | |
1108 | desc = "eedp app tag error"; | |
1109 | break; | |
1110 | ||
1111 | /**************************************************************************** | |
1112 | * SCSI Target values | |
1113 | ****************************************************************************/ | |
1114 | ||
1115 | case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX: | |
1116 | desc = "target invalid io index"; | |
1117 | break; | |
1118 | case MPI2_IOCSTATUS_TARGET_ABORTED: | |
1119 | desc = "target aborted"; | |
1120 | break; | |
1121 | case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: | |
1122 | desc = "target no conn retryable"; | |
1123 | break; | |
1124 | case MPI2_IOCSTATUS_TARGET_NO_CONNECTION: | |
1125 | desc = "target no connection"; | |
1126 | break; | |
1127 | case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: | |
1128 | desc = "target xfer count mismatch"; | |
1129 | break; | |
1130 | case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: | |
1131 | desc = "target data offset error"; | |
1132 | break; | |
1133 | case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: | |
1134 | desc = "target too much write data"; | |
1135 | break; | |
1136 | case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT: | |
1137 | desc = "target iu too short"; | |
1138 | break; | |
1139 | case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: | |
1140 | desc = "target ack nak timeout"; | |
1141 | break; | |
1142 | case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED: | |
1143 | desc = "target nak received"; | |
1144 | break; | |
1145 | ||
1146 | /**************************************************************************** | |
1147 | * Serial Attached SCSI values | |
1148 | ****************************************************************************/ | |
1149 | ||
1150 | case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: | |
1151 | desc = "smp request failed"; | |
1152 | break; | |
1153 | case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: | |
1154 | desc = "smp data overrun"; | |
1155 | break; | |
1156 | ||
1157 | /**************************************************************************** | |
1158 | * Diagnostic Buffer Post / Diagnostic Release values | |
1159 | ****************************************************************************/ | |
1160 | ||
1161 | case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED: | |
1162 | desc = "diagnostic released"; | |
1163 | break; | |
1164 | default: | |
1165 | break; | |
1166 | } | |
1167 | ||
1168 | if (!desc) | |
1169 | return; | |
1170 | ||
1171 | switch (request_hdr->Function) { | |
1172 | case MPI2_FUNCTION_CONFIG: | |
1173 | frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size; | |
1174 | func_str = "config_page"; | |
1175 | break; | |
1176 | case MPI2_FUNCTION_SCSI_TASK_MGMT: | |
1177 | frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t); | |
1178 | func_str = "task_mgmt"; | |
1179 | break; | |
1180 | case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL: | |
1181 | frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t); | |
1182 | func_str = "sas_iounit_ctl"; | |
1183 | break; | |
1184 | case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR: | |
1185 | frame_sz = sizeof(Mpi2SepRequest_t); | |
1186 | func_str = "enclosure"; | |
1187 | break; | |
1188 | case MPI2_FUNCTION_IOC_INIT: | |
1189 | frame_sz = sizeof(Mpi2IOCInitRequest_t); | |
1190 | func_str = "ioc_init"; | |
1191 | break; | |
1192 | case MPI2_FUNCTION_PORT_ENABLE: | |
1193 | frame_sz = sizeof(Mpi2PortEnableRequest_t); | |
1194 | func_str = "port_enable"; | |
1195 | break; | |
1196 | case MPI2_FUNCTION_SMP_PASSTHROUGH: | |
1197 | frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size; | |
1198 | func_str = "smp_passthru"; | |
1199 | break; | |
aff39e61 SPS |
1200 | case MPI2_FUNCTION_NVME_ENCAPSULATED: |
1201 | frame_sz = sizeof(Mpi26NVMeEncapsulatedRequest_t) + | |
1202 | ioc->sge_size; | |
1203 | func_str = "nvme_encapsulated"; | |
1204 | break; | |
f92363d1 SR |
1205 | default: |
1206 | frame_sz = 32; | |
1207 | func_str = "unknown"; | |
1208 | break; | |
1209 | } | |
1210 | ||
919d8a3f JP |
1211 | ioc_warn(ioc, "ioc_status: %s(0x%04x), request(0x%p),(%s)\n", |
1212 | desc, ioc_status, request_hdr, func_str); | |
f92363d1 SR |
1213 | |
1214 | _debug_dump_mf(request_hdr, frame_sz/4); | |
1215 | } | |
1216 | ||
1217 | /** | |
1218 | * _base_display_event_data - verbose translation of firmware asyn events | |
1219 | * @ioc: per adapter object | |
1220 | * @mpi_reply: reply mf payload returned from firmware | |
f92363d1 SR |
1221 | */ |
1222 | static void | |
1223 | _base_display_event_data(struct MPT3SAS_ADAPTER *ioc, | |
1224 | Mpi2EventNotificationReply_t *mpi_reply) | |
1225 | { | |
1226 | char *desc = NULL; | |
1227 | u16 event; | |
1228 | ||
1229 | if (!(ioc->logging_level & MPT_DEBUG_EVENTS)) | |
1230 | return; | |
1231 | ||
1232 | event = le16_to_cpu(mpi_reply->Event); | |
1233 | ||
1234 | switch (event) { | |
1235 | case MPI2_EVENT_LOG_DATA: | |
1236 | desc = "Log Data"; | |
1237 | break; | |
1238 | case MPI2_EVENT_STATE_CHANGE: | |
1239 | desc = "Status Change"; | |
1240 | break; | |
1241 | case MPI2_EVENT_HARD_RESET_RECEIVED: | |
1242 | desc = "Hard Reset Received"; | |
1243 | break; | |
1244 | case MPI2_EVENT_EVENT_CHANGE: | |
1245 | desc = "Event Change"; | |
1246 | break; | |
1247 | case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: | |
1248 | desc = "Device Status Change"; | |
1249 | break; | |
1250 | case MPI2_EVENT_IR_OPERATION_STATUS: | |
7786ab6a SR |
1251 | if (!ioc->hide_ir_msg) |
1252 | desc = "IR Operation Status"; | |
f92363d1 SR |
1253 | break; |
1254 | case MPI2_EVENT_SAS_DISCOVERY: | |
1255 | { | |
1256 | Mpi2EventDataSasDiscovery_t *event_data = | |
1257 | (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData; | |
919d8a3f JP |
1258 | ioc_info(ioc, "Discovery: (%s)", |
1259 | event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED ? | |
1260 | "start" : "stop"); | |
f92363d1 | 1261 | if (event_data->DiscoveryStatus) |
bbaf61e2 | 1262 | pr_cont(" discovery_status(0x%08x)", |
f92363d1 | 1263 | le32_to_cpu(event_data->DiscoveryStatus)); |
bbaf61e2 | 1264 | pr_cont("\n"); |
f92363d1 SR |
1265 | return; |
1266 | } | |
1267 | case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: | |
1268 | desc = "SAS Broadcast Primitive"; | |
1269 | break; | |
1270 | case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: | |
1271 | desc = "SAS Init Device Status Change"; | |
1272 | break; | |
1273 | case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW: | |
1274 | desc = "SAS Init Table Overflow"; | |
1275 | break; | |
1276 | case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: | |
1277 | desc = "SAS Topology Change List"; | |
1278 | break; | |
1279 | case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: | |
1280 | desc = "SAS Enclosure Device Status Change"; | |
1281 | break; | |
1282 | case MPI2_EVENT_IR_VOLUME: | |
7786ab6a SR |
1283 | if (!ioc->hide_ir_msg) |
1284 | desc = "IR Volume"; | |
f92363d1 SR |
1285 | break; |
1286 | case MPI2_EVENT_IR_PHYSICAL_DISK: | |
7786ab6a SR |
1287 | if (!ioc->hide_ir_msg) |
1288 | desc = "IR Physical Disk"; | |
f92363d1 SR |
1289 | break; |
1290 | case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: | |
7786ab6a SR |
1291 | if (!ioc->hide_ir_msg) |
1292 | desc = "IR Configuration Change List"; | |
f92363d1 SR |
1293 | break; |
1294 | case MPI2_EVENT_LOG_ENTRY_ADDED: | |
7786ab6a SR |
1295 | if (!ioc->hide_ir_msg) |
1296 | desc = "Log Entry Added"; | |
f92363d1 | 1297 | break; |
2d8ce8c9 SR |
1298 | case MPI2_EVENT_TEMP_THRESHOLD: |
1299 | desc = "Temperature Threshold"; | |
1300 | break; | |
a470a51c | 1301 | case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION: |
b99b1993 | 1302 | desc = "Cable Event"; |
a470a51c | 1303 | break; |
95540b8e C |
1304 | case MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR: |
1305 | desc = "SAS Device Discovery Error"; | |
1306 | break; | |
4318c734 SPS |
1307 | case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE: |
1308 | desc = "PCIE Device Status Change"; | |
1309 | break; | |
1310 | case MPI2_EVENT_PCIE_ENUMERATION: | |
1311 | { | |
1312 | Mpi26EventDataPCIeEnumeration_t *event_data = | |
1313 | (Mpi26EventDataPCIeEnumeration_t *)mpi_reply->EventData; | |
919d8a3f JP |
1314 | ioc_info(ioc, "PCIE Enumeration: (%s)", |
1315 | event_data->ReasonCode == MPI26_EVENT_PCIE_ENUM_RC_STARTED ? | |
1316 | "start" : "stop"); | |
4318c734 | 1317 | if (event_data->EnumerationStatus) |
919d8a3f JP |
1318 | pr_cont("enumeration_status(0x%08x)", |
1319 | le32_to_cpu(event_data->EnumerationStatus)); | |
1320 | pr_cont("\n"); | |
4318c734 SPS |
1321 | return; |
1322 | } | |
1323 | case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: | |
1324 | desc = "PCIE Topology Change List"; | |
1325 | break; | |
f92363d1 SR |
1326 | } |
1327 | ||
1328 | if (!desc) | |
1329 | return; | |
1330 | ||
919d8a3f | 1331 | ioc_info(ioc, "%s\n", desc); |
f92363d1 | 1332 | } |
f92363d1 SR |
1333 | |
1334 | /** | |
1335 | * _base_sas_log_info - verbose translation of firmware log info | |
1336 | * @ioc: per adapter object | |
1337 | * @log_info: log info | |
f92363d1 SR |
1338 | */ |
1339 | static void | |
efef34cb | 1340 | _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc, u32 log_info) |
f92363d1 SR |
1341 | { |
1342 | union loginfo_type { | |
1343 | u32 loginfo; | |
1344 | struct { | |
1345 | u32 subcode:16; | |
1346 | u32 code:8; | |
1347 | u32 originator:4; | |
1348 | u32 bus_type:4; | |
1349 | } dw; | |
1350 | }; | |
1351 | union loginfo_type sas_loginfo; | |
1352 | char *originator_str = NULL; | |
1353 | ||
1354 | sas_loginfo.loginfo = log_info; | |
1355 | if (sas_loginfo.dw.bus_type != 3 /*SAS*/) | |
1356 | return; | |
1357 | ||
1358 | /* each nexus loss loginfo */ | |
1359 | if (log_info == 0x31170000) | |
1360 | return; | |
1361 | ||
1362 | /* eat the loginfos associated with task aborts */ | |
1363 | if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info == | |
1364 | 0x31140000 || log_info == 0x31130000)) | |
1365 | return; | |
1366 | ||
1367 | switch (sas_loginfo.dw.originator) { | |
1368 | case 0: | |
1369 | originator_str = "IOP"; | |
1370 | break; | |
1371 | case 1: | |
1372 | originator_str = "PL"; | |
1373 | break; | |
1374 | case 2: | |
7786ab6a SR |
1375 | if (!ioc->hide_ir_msg) |
1376 | originator_str = "IR"; | |
1377 | else | |
1378 | originator_str = "WarpDrive"; | |
f92363d1 SR |
1379 | break; |
1380 | } | |
1381 | ||
919d8a3f JP |
1382 | ioc_warn(ioc, "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n", |
1383 | log_info, | |
1384 | originator_str, sas_loginfo.dw.code, sas_loginfo.dw.subcode); | |
f92363d1 SR |
1385 | } |
1386 | ||
1387 | /** | |
2910a4a9 | 1388 | * _base_display_reply_info - handle reply descriptors depending on IOC Status |
f92363d1 SR |
1389 | * @ioc: per adapter object |
1390 | * @smid: system request message index | |
1391 | * @msix_index: MSIX table index supplied by the OS | |
2910a4a9 | 1392 | * @reply: reply message frame (lower 32bit addr) |
f92363d1 SR |
1393 | */ |
1394 | static void | |
1395 | _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, | |
1396 | u32 reply) | |
1397 | { | |
1398 | MPI2DefaultReply_t *mpi_reply; | |
1399 | u16 ioc_status; | |
1400 | u32 loginfo = 0; | |
1401 | ||
1402 | mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); | |
1403 | if (unlikely(!mpi_reply)) { | |
919d8a3f JP |
1404 | ioc_err(ioc, "mpi_reply not valid at %s:%d/%s()!\n", |
1405 | __FILE__, __LINE__, __func__); | |
f92363d1 SR |
1406 | return; |
1407 | } | |
1408 | ioc_status = le16_to_cpu(mpi_reply->IOCStatus); | |
af009411 | 1409 | |
f92363d1 SR |
1410 | if ((ioc_status & MPI2_IOCSTATUS_MASK) && |
1411 | (ioc->logging_level & MPT_DEBUG_REPLY)) { | |
efef34cb | 1412 | _base_sas_ioc_info(ioc, mpi_reply, |
f92363d1 SR |
1413 | mpt3sas_base_get_msg_frame(ioc, smid)); |
1414 | } | |
af009411 | 1415 | |
f92363d1 SR |
1416 | if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { |
1417 | loginfo = le32_to_cpu(mpi_reply->IOCLogInfo); | |
1418 | _base_sas_log_info(ioc, loginfo); | |
1419 | } | |
1420 | ||
1421 | if (ioc_status || loginfo) { | |
1422 | ioc_status &= MPI2_IOCSTATUS_MASK; | |
1423 | mpt3sas_trigger_mpi(ioc, ioc_status, loginfo); | |
1424 | } | |
1425 | } | |
1426 | ||
1427 | /** | |
1428 | * mpt3sas_base_done - base internal command completion routine | |
1429 | * @ioc: per adapter object | |
1430 | * @smid: system request message index | |
1431 | * @msix_index: MSIX table index supplied by the OS | |
1432 | * @reply: reply message frame(lower 32bit addr) | |
1433 | * | |
4beb4867 BVA |
1434 | * Return: |
1435 | * 1 meaning mf should be freed from _base_interrupt | |
1436 | * 0 means the mf is freed from this function. | |
f92363d1 SR |
1437 | */ |
1438 | u8 | |
1439 | mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, | |
1440 | u32 reply) | |
1441 | { | |
1442 | MPI2DefaultReply_t *mpi_reply; | |
1443 | ||
1444 | mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); | |
1445 | if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK) | |
fd0331b3 | 1446 | return mpt3sas_check_for_pending_internal_cmds(ioc, smid); |
f92363d1 SR |
1447 | |
1448 | if (ioc->base_cmds.status == MPT3_CMD_NOT_USED) | |
1449 | return 1; | |
1450 | ||
1451 | ioc->base_cmds.status |= MPT3_CMD_COMPLETE; | |
1452 | if (mpi_reply) { | |
1453 | ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID; | |
1454 | memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); | |
1455 | } | |
1456 | ioc->base_cmds.status &= ~MPT3_CMD_PENDING; | |
1457 | ||
1458 | complete(&ioc->base_cmds.done); | |
1459 | return 1; | |
1460 | } | |
1461 | ||
1462 | /** | |
1463 | * _base_async_event - main callback handler for firmware asyn events | |
1464 | * @ioc: per adapter object | |
1465 | * @msix_index: MSIX table index supplied by the OS | |
1466 | * @reply: reply message frame(lower 32bit addr) | |
1467 | * | |
4beb4867 BVA |
1468 | * Return: |
1469 | * 1 meaning mf should be freed from _base_interrupt | |
1470 | * 0 means the mf is freed from this function. | |
f92363d1 SR |
1471 | */ |
1472 | static u8 | |
1473 | _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply) | |
1474 | { | |
1475 | Mpi2EventNotificationReply_t *mpi_reply; | |
1476 | Mpi2EventAckRequest_t *ack_request; | |
1477 | u16 smid; | |
fd0331b3 | 1478 | struct _event_ack_list *delayed_event_ack; |
f92363d1 SR |
1479 | |
1480 | mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); | |
1481 | if (!mpi_reply) | |
1482 | return 1; | |
1483 | if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION) | |
1484 | return 1; | |
af009411 | 1485 | |
f92363d1 | 1486 | _base_display_event_data(ioc, mpi_reply); |
af009411 | 1487 | |
f92363d1 SR |
1488 | if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED)) |
1489 | goto out; | |
1490 | smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); | |
1491 | if (!smid) { | |
fd0331b3 SS |
1492 | delayed_event_ack = kzalloc(sizeof(*delayed_event_ack), |
1493 | GFP_ATOMIC); | |
1494 | if (!delayed_event_ack) | |
1495 | goto out; | |
1496 | INIT_LIST_HEAD(&delayed_event_ack->list); | |
1497 | delayed_event_ack->Event = mpi_reply->Event; | |
1498 | delayed_event_ack->EventContext = mpi_reply->EventContext; | |
1499 | list_add_tail(&delayed_event_ack->list, | |
1500 | &ioc->delayed_event_ack_list); | |
919d8a3f JP |
1501 | dewtprintk(ioc, |
1502 | ioc_info(ioc, "DELAYED: EVENT ACK: event (0x%04x)\n", | |
1503 | le16_to_cpu(mpi_reply->Event))); | |
f92363d1 SR |
1504 | goto out; |
1505 | } | |
1506 | ||
1507 | ack_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
1508 | memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t)); | |
1509 | ack_request->Function = MPI2_FUNCTION_EVENT_ACK; | |
1510 | ack_request->Event = mpi_reply->Event; | |
1511 | ack_request->EventContext = mpi_reply->EventContext; | |
1512 | ack_request->VF_ID = 0; /* TODO */ | |
1513 | ack_request->VP_ID = 0; | |
078a4cc1 | 1514 | ioc->put_smid_default(ioc, smid); |
f92363d1 SR |
1515 | |
1516 | out: | |
1517 | ||
1518 | /* scsih callback handler */ | |
1519 | mpt3sas_scsih_event_callback(ioc, msix_index, reply); | |
1520 | ||
1521 | /* ctl callback handler */ | |
1522 | mpt3sas_ctl_event_callback(ioc, msix_index, reply); | |
1523 | ||
1524 | return 1; | |
1525 | } | |
1526 | ||
61dfb8a5 | 1527 | static struct scsiio_tracker * |
dbec4c90 | 1528 | _get_st_from_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid) |
12e7c678 | 1529 | { |
dbec4c90 SPS |
1530 | struct scsi_cmnd *cmd; |
1531 | ||
12e7c678 HR |
1532 | if (WARN_ON(!smid) || |
1533 | WARN_ON(smid >= ioc->hi_priority_smid)) | |
1534 | return NULL; | |
dbec4c90 SPS |
1535 | |
1536 | cmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid); | |
1537 | if (cmd) | |
1538 | return scsi_cmd_priv(cmd); | |
1539 | ||
1540 | return NULL; | |
12e7c678 HR |
1541 | } |
1542 | ||
f92363d1 SR |
1543 | /** |
1544 | * _base_get_cb_idx - obtain the callback index | |
1545 | * @ioc: per adapter object | |
1546 | * @smid: system request message index | |
1547 | * | |
4beb4867 | 1548 | * Return: callback index. |
f92363d1 SR |
1549 | */ |
1550 | static u8 | |
1551 | _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
1552 | { | |
1553 | int i; | |
b0cd285e | 1554 | u16 ctl_smid = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT + 1; |
ba4494d4 | 1555 | u8 cb_idx = 0xFF; |
f92363d1 SR |
1556 | |
1557 | if (smid < ioc->hi_priority_smid) { | |
12e7c678 HR |
1558 | struct scsiio_tracker *st; |
1559 | ||
b0cd285e | 1560 | if (smid < ctl_smid) { |
dbec4c90 | 1561 | st = _get_st_from_smid(ioc, smid); |
b0cd285e HR |
1562 | if (st) |
1563 | cb_idx = st->cb_idx; | |
1564 | } else if (smid == ctl_smid) | |
1565 | cb_idx = ioc->ctl_cb_idx; | |
f92363d1 SR |
1566 | } else if (smid < ioc->internal_smid) { |
1567 | i = smid - ioc->hi_priority_smid; | |
1568 | cb_idx = ioc->hpr_lookup[i].cb_idx; | |
1569 | } else if (smid <= ioc->hba_queue_depth) { | |
1570 | i = smid - ioc->internal_smid; | |
1571 | cb_idx = ioc->internal_lookup[i].cb_idx; | |
ba4494d4 | 1572 | } |
f92363d1 SR |
1573 | return cb_idx; |
1574 | } | |
1575 | ||
432bc7ca SR |
1576 | /** |
1577 | * mpt3sas_base_pause_mq_polling - pause polling on the mq poll queues | |
1578 | * when driver is flushing out the IOs. | |
1579 | * @ioc: per adapter object | |
1580 | * | |
1581 | * Pause polling on the mq poll (io uring) queues when driver is flushing | |
1582 | * out the IOs. Otherwise we may see the race condition of completing the same | |
1583 | * IO from two paths. | |
1584 | * | |
1585 | * Returns nothing. | |
1586 | */ | |
1587 | void | |
1588 | mpt3sas_base_pause_mq_polling(struct MPT3SAS_ADAPTER *ioc) | |
1589 | { | |
1590 | int iopoll_q_count = | |
1591 | ioc->reply_queue_count - ioc->iopoll_q_start_index; | |
1592 | int qid; | |
1593 | ||
1594 | for (qid = 0; qid < iopoll_q_count; qid++) | |
1595 | atomic_set(&ioc->io_uring_poll_queues[qid].pause, 1); | |
1596 | ||
1597 | /* | |
1598 | * wait for current poll to complete. | |
1599 | */ | |
1600 | for (qid = 0; qid < iopoll_q_count; qid++) { | |
e4953a93 SR |
1601 | while (atomic_read(&ioc->io_uring_poll_queues[qid].busy)) { |
1602 | cpu_relax(); | |
432bc7ca | 1603 | udelay(500); |
e4953a93 | 1604 | } |
432bc7ca SR |
1605 | } |
1606 | } | |
1607 | ||
1608 | /** | |
1609 | * mpt3sas_base_resume_mq_polling - Resume polling on mq poll queues. | |
1610 | * @ioc: per adapter object | |
1611 | * | |
1612 | * Returns nothing. | |
1613 | */ | |
1614 | void | |
1615 | mpt3sas_base_resume_mq_polling(struct MPT3SAS_ADAPTER *ioc) | |
1616 | { | |
1617 | int iopoll_q_count = | |
1618 | ioc->reply_queue_count - ioc->iopoll_q_start_index; | |
1619 | int qid; | |
1620 | ||
1621 | for (qid = 0; qid < iopoll_q_count; qid++) | |
1622 | atomic_set(&ioc->io_uring_poll_queues[qid].pause, 0); | |
1623 | } | |
1624 | ||
f92363d1 | 1625 | /** |
5afa9d44 | 1626 | * mpt3sas_base_mask_interrupts - disable interrupts |
f92363d1 SR |
1627 | * @ioc: per adapter object |
1628 | * | |
1629 | * Disabling ResetIRQ, Reply and Doorbell Interrupts | |
f92363d1 | 1630 | */ |
5afa9d44 SP |
1631 | void |
1632 | mpt3sas_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc) | |
f92363d1 SR |
1633 | { |
1634 | u32 him_register; | |
1635 | ||
1636 | ioc->mask_interrupts = 1; | |
306eaf27 | 1637 | him_register = ioc->base_readl(&ioc->chip->HostInterruptMask); |
f92363d1 SR |
1638 | him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK; |
1639 | writel(him_register, &ioc->chip->HostInterruptMask); | |
306eaf27 | 1640 | ioc->base_readl(&ioc->chip->HostInterruptMask); |
f92363d1 SR |
1641 | } |
1642 | ||
1643 | /** | |
5afa9d44 | 1644 | * mpt3sas_base_unmask_interrupts - enable interrupts |
f92363d1 SR |
1645 | * @ioc: per adapter object |
1646 | * | |
1647 | * Enabling only Reply Interrupts | |
f92363d1 | 1648 | */ |
5afa9d44 SP |
1649 | void |
1650 | mpt3sas_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc) | |
f92363d1 SR |
1651 | { |
1652 | u32 him_register; | |
1653 | ||
306eaf27 | 1654 | him_register = ioc->base_readl(&ioc->chip->HostInterruptMask); |
f92363d1 SR |
1655 | him_register &= ~MPI2_HIM_RIM; |
1656 | writel(him_register, &ioc->chip->HostInterruptMask); | |
1657 | ioc->mask_interrupts = 0; | |
1658 | } | |
1659 | ||
1660 | union reply_descriptor { | |
1661 | u64 word; | |
1662 | struct { | |
1663 | u32 low; | |
1664 | u32 high; | |
1665 | } u; | |
1666 | }; | |
1667 | ||
51e3b2ad SP |
1668 | static u32 base_mod64(u64 dividend, u32 divisor) |
1669 | { | |
1670 | u32 remainder; | |
1671 | ||
1672 | if (!divisor) | |
1673 | pr_err("mpt3sas: DIVISOR is zero, in div fn\n"); | |
1674 | remainder = do_div(dividend, divisor); | |
1675 | return remainder; | |
1676 | } | |
1677 | ||
f92363d1 | 1678 | /** |
233af108 SP |
1679 | * _base_process_reply_queue - Process reply descriptors from reply |
1680 | * descriptor post queue. | |
1681 | * @reply_q: per IRQ's reply queue object. | |
f92363d1 | 1682 | * |
233af108 SP |
1683 | * Return: number of reply descriptors processed from reply |
1684 | * descriptor queue. | |
f92363d1 | 1685 | */ |
233af108 SP |
1686 | static int |
1687 | _base_process_reply_queue(struct adapter_reply_queue *reply_q) | |
f92363d1 | 1688 | { |
f92363d1 | 1689 | union reply_descriptor rd; |
288addd6 | 1690 | u64 completed_cmds; |
2c063507 | 1691 | u8 request_descript_type; |
f92363d1 SR |
1692 | u16 smid; |
1693 | u8 cb_idx; | |
1694 | u32 reply; | |
1695 | u8 msix_index = reply_q->msix_index; | |
1696 | struct MPT3SAS_ADAPTER *ioc = reply_q->ioc; | |
1697 | Mpi2ReplyDescriptorsUnion_t *rpf; | |
1698 | u8 rc; | |
1699 | ||
233af108 | 1700 | completed_cmds = 0; |
f92363d1 | 1701 | if (!atomic_add_unless(&reply_q->busy, 1, 1)) |
233af108 | 1702 | return completed_cmds; |
f92363d1 SR |
1703 | |
1704 | rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index]; | |
2c063507 | 1705 | request_descript_type = rpf->Default.ReplyFlags |
f92363d1 | 1706 | & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; |
2c063507 | 1707 | if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) { |
f92363d1 | 1708 | atomic_dec(&reply_q->busy); |
233af108 | 1709 | return completed_cmds; |
f92363d1 SR |
1710 | } |
1711 | ||
f92363d1 SR |
1712 | cb_idx = 0xFF; |
1713 | do { | |
1714 | rd.word = le64_to_cpu(rpf->Words); | |
1715 | if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX) | |
1716 | goto out; | |
1717 | reply = 0; | |
1718 | smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1); | |
2c063507 | 1719 | if (request_descript_type == |
f92363d1 | 1720 | MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS || |
2c063507 | 1721 | request_descript_type == |
aff39e61 | 1722 | MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS || |
2c063507 | 1723 | request_descript_type == |
aff39e61 | 1724 | MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS) { |
f92363d1 SR |
1725 | cb_idx = _base_get_cb_idx(ioc, smid); |
1726 | if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && | |
1727 | (likely(mpt_callbacks[cb_idx] != NULL))) { | |
1728 | rc = mpt_callbacks[cb_idx](ioc, smid, | |
1729 | msix_index, 0); | |
1730 | if (rc) | |
1731 | mpt3sas_base_free_smid(ioc, smid); | |
1732 | } | |
2c063507 | 1733 | } else if (request_descript_type == |
f92363d1 SR |
1734 | MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { |
1735 | reply = le32_to_cpu( | |
1736 | rpf->AddressReply.ReplyFrameAddress); | |
1737 | if (reply > ioc->reply_dma_max_address || | |
1738 | reply < ioc->reply_dma_min_address) | |
1739 | reply = 0; | |
1740 | if (smid) { | |
1741 | cb_idx = _base_get_cb_idx(ioc, smid); | |
1742 | if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && | |
1743 | (likely(mpt_callbacks[cb_idx] != NULL))) { | |
1744 | rc = mpt_callbacks[cb_idx](ioc, smid, | |
1745 | msix_index, reply); | |
1746 | if (reply) | |
1747 | _base_display_reply_info(ioc, | |
1748 | smid, msix_index, reply); | |
1749 | if (rc) | |
1750 | mpt3sas_base_free_smid(ioc, | |
1751 | smid); | |
1752 | } | |
1753 | } else { | |
1754 | _base_async_event(ioc, msix_index, reply); | |
1755 | } | |
1756 | ||
1757 | /* reply free queue handling */ | |
1758 | if (reply) { | |
1759 | ioc->reply_free_host_index = | |
1760 | (ioc->reply_free_host_index == | |
1761 | (ioc->reply_free_queue_depth - 1)) ? | |
1762 | 0 : ioc->reply_free_host_index + 1; | |
1763 | ioc->reply_free[ioc->reply_free_host_index] = | |
1764 | cpu_to_le32(reply); | |
b4472d71 SPS |
1765 | if (ioc->is_mcpu_endpoint) |
1766 | _base_clone_reply_to_sys_mem(ioc, | |
cf6bf971 | 1767 | reply, |
b4472d71 | 1768 | ioc->reply_free_host_index); |
f92363d1 SR |
1769 | writel(ioc->reply_free_host_index, |
1770 | &ioc->chip->ReplyFreeHostIndex); | |
1771 | } | |
1772 | } | |
1773 | ||
1774 | rpf->Words = cpu_to_le64(ULLONG_MAX); | |
1775 | reply_q->reply_post_host_index = | |
1776 | (reply_q->reply_post_host_index == | |
1777 | (ioc->reply_post_queue_depth - 1)) ? 0 : | |
1778 | reply_q->reply_post_host_index + 1; | |
2c063507 | 1779 | request_descript_type = |
f92363d1 SR |
1780 | reply_q->reply_post_free[reply_q->reply_post_host_index]. |
1781 | Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; | |
1782 | completed_cmds++; | |
6b4c335a C |
1783 | /* Update the reply post host index after continuously |
1784 | * processing the threshold number of Reply Descriptors. | |
1785 | * So that FW can find enough entries to post the Reply | |
1786 | * Descriptors in the reply descriptor post queue. | |
1787 | */ | |
3d49f742 | 1788 | if (completed_cmds >= ioc->thresh_hold) { |
6b4c335a C |
1789 | if (ioc->combined_reply_queue) { |
1790 | writel(reply_q->reply_post_host_index | | |
1791 | ((msix_index & 7) << | |
1792 | MPI2_RPHI_MSIX_INDEX_SHIFT), | |
1793 | ioc->replyPostRegisterIndex[msix_index/8]); | |
1794 | } else { | |
1795 | writel(reply_q->reply_post_host_index | | |
1796 | (msix_index << | |
1797 | MPI2_RPHI_MSIX_INDEX_SHIFT), | |
1798 | &ioc->chip->ReplyPostHostIndex); | |
1799 | } | |
432bc7ca SR |
1800 | if (!reply_q->is_iouring_poll_q && |
1801 | !reply_q->irq_poll_scheduled) { | |
320e77ac SP |
1802 | reply_q->irq_poll_scheduled = true; |
1803 | irq_poll_sched(&reply_q->irqpoll); | |
1804 | } | |
ea9006df CIK |
1805 | atomic_dec(&reply_q->busy); |
1806 | return completed_cmds; | |
6b4c335a | 1807 | } |
2c063507 | 1808 | if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) |
f92363d1 SR |
1809 | goto out; |
1810 | if (!reply_q->reply_post_host_index) | |
1811 | rpf = reply_q->reply_post_free; | |
1812 | else | |
1813 | rpf++; | |
1814 | } while (1); | |
1815 | ||
1816 | out: | |
1817 | ||
1818 | if (!completed_cmds) { | |
1819 | atomic_dec(&reply_q->busy); | |
233af108 | 1820 | return completed_cmds; |
f92363d1 SR |
1821 | } |
1822 | ||
7786ab6a SR |
1823 | if (ioc->is_warpdrive) { |
1824 | writel(reply_q->reply_post_host_index, | |
1825 | ioc->reply_post_host_index[msix_index]); | |
1826 | atomic_dec(&reply_q->busy); | |
233af108 | 1827 | return completed_cmds; |
7786ab6a | 1828 | } |
fb77bb53 SR |
1829 | |
1830 | /* Update Reply Post Host Index. | |
1831 | * For those HBA's which support combined reply queue feature | |
1832 | * 1. Get the correct Supplemental Reply Post Host Index Register. | |
1833 | * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host | |
1834 | * Index Register address bank i.e replyPostRegisterIndex[], | |
1835 | * 2. Then update this register with new reply host index value | |
1836 | * in ReplyPostIndex field and the MSIxIndex field with | |
1837 | * msix_index value reduced to a value between 0 and 7, | |
1838 | * using a modulo 8 operation. Since each Supplemental Reply Post | |
1839 | * Host Index Register supports 8 MSI-X vectors. | |
1840 | * | |
1841 | * For other HBA's just update the Reply Post Host Index register with | |
1842 | * new reply host index value in ReplyPostIndex Field and msix_index | |
1843 | * value in MSIxIndex field. | |
1844 | */ | |
0bb337c9 | 1845 | if (ioc->combined_reply_queue) |
fb77bb53 SR |
1846 | writel(reply_q->reply_post_host_index | ((msix_index & 7) << |
1847 | MPI2_RPHI_MSIX_INDEX_SHIFT), | |
1848 | ioc->replyPostRegisterIndex[msix_index/8]); | |
1849 | else | |
1850 | writel(reply_q->reply_post_host_index | (msix_index << | |
1851 | MPI2_RPHI_MSIX_INDEX_SHIFT), | |
1852 | &ioc->chip->ReplyPostHostIndex); | |
f92363d1 | 1853 | atomic_dec(&reply_q->busy); |
233af108 SP |
1854 | return completed_cmds; |
1855 | } | |
1856 | ||
432bc7ca SR |
1857 | /** |
1858 | * mpt3sas_blk_mq_poll - poll the blk mq poll queue | |
1859 | * @shost: Scsi_Host object | |
1860 | * @queue_num: hw ctx queue number | |
1861 | * | |
1862 | * Return number of entries that has been processed from poll queue. | |
1863 | */ | |
1864 | int mpt3sas_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num) | |
1865 | { | |
1866 | struct MPT3SAS_ADAPTER *ioc = | |
1867 | (struct MPT3SAS_ADAPTER *)shost->hostdata; | |
1868 | struct adapter_reply_queue *reply_q; | |
1869 | int num_entries = 0; | |
1870 | int qid = queue_num - ioc->iopoll_q_start_index; | |
1871 | ||
1872 | if (atomic_read(&ioc->io_uring_poll_queues[qid].pause) || | |
1873 | !atomic_add_unless(&ioc->io_uring_poll_queues[qid].busy, 1, 1)) | |
1874 | return 0; | |
1875 | ||
1876 | reply_q = ioc->io_uring_poll_queues[qid].reply_q; | |
1877 | ||
1878 | num_entries = _base_process_reply_queue(reply_q); | |
1879 | atomic_dec(&ioc->io_uring_poll_queues[qid].busy); | |
1880 | ||
1881 | return num_entries; | |
1882 | } | |
1883 | ||
233af108 SP |
1884 | /** |
1885 | * _base_interrupt - MPT adapter (IOC) specific interrupt handler. | |
1886 | * @irq: irq number (not used) | |
1887 | * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure | |
1888 | * | |
1889 | * Return: IRQ_HANDLED if processed, else IRQ_NONE. | |
1890 | */ | |
1891 | static irqreturn_t | |
1892 | _base_interrupt(int irq, void *bus_id) | |
1893 | { | |
1894 | struct adapter_reply_queue *reply_q = bus_id; | |
1895 | struct MPT3SAS_ADAPTER *ioc = reply_q->ioc; | |
1896 | ||
1897 | if (ioc->mask_interrupts) | |
1898 | return IRQ_NONE; | |
320e77ac SP |
1899 | if (reply_q->irq_poll_scheduled) |
1900 | return IRQ_HANDLED; | |
233af108 SP |
1901 | return ((_base_process_reply_queue(reply_q) > 0) ? |
1902 | IRQ_HANDLED : IRQ_NONE); | |
f92363d1 SR |
1903 | } |
1904 | ||
320e77ac SP |
1905 | /** |
1906 | * _base_irqpoll - IRQ poll callback handler | |
9133d27e DLM |
1907 | * @irqpoll: irq_poll object |
1908 | * @budget: irq poll weight | |
320e77ac | 1909 | * |
2910a4a9 | 1910 | * Return: number of reply descriptors processed |
320e77ac SP |
1911 | */ |
1912 | static int | |
1913 | _base_irqpoll(struct irq_poll *irqpoll, int budget) | |
1914 | { | |
1915 | struct adapter_reply_queue *reply_q; | |
1916 | int num_entries = 0; | |
1917 | ||
1918 | reply_q = container_of(irqpoll, struct adapter_reply_queue, | |
1919 | irqpoll); | |
1920 | if (reply_q->irq_line_enable) { | |
b614d55b | 1921 | disable_irq_nosync(reply_q->os_irq); |
320e77ac SP |
1922 | reply_q->irq_line_enable = false; |
1923 | } | |
1924 | num_entries = _base_process_reply_queue(reply_q); | |
1925 | if (num_entries < budget) { | |
1926 | irq_poll_complete(irqpoll); | |
1927 | reply_q->irq_poll_scheduled = false; | |
1928 | reply_q->irq_line_enable = true; | |
1929 | enable_irq(reply_q->os_irq); | |
5feed64f SR |
1930 | /* |
1931 | * Go for one more round of processing the | |
2910a4a9 | 1932 | * reply descriptor post queue in case the HBA |
5feed64f SR |
1933 | * Firmware has posted some reply descriptors |
1934 | * while reenabling the IRQ. | |
1935 | */ | |
1936 | _base_process_reply_queue(reply_q); | |
320e77ac SP |
1937 | } |
1938 | ||
1939 | return num_entries; | |
1940 | } | |
1941 | ||
1942 | /** | |
1943 | * _base_init_irqpolls - initliaze IRQ polls | |
1944 | * @ioc: per adapter object | |
1945 | * | |
2910a4a9 | 1946 | * Return: nothing |
320e77ac SP |
1947 | */ |
1948 | static void | |
1949 | _base_init_irqpolls(struct MPT3SAS_ADAPTER *ioc) | |
1950 | { | |
1951 | struct adapter_reply_queue *reply_q, *next; | |
1952 | ||
1953 | if (list_empty(&ioc->reply_queue_list)) | |
1954 | return; | |
1955 | ||
1956 | list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) { | |
432bc7ca SR |
1957 | if (reply_q->is_iouring_poll_q) |
1958 | continue; | |
320e77ac SP |
1959 | irq_poll_init(&reply_q->irqpoll, |
1960 | ioc->hba_queue_depth/4, _base_irqpoll); | |
1961 | reply_q->irq_poll_scheduled = false; | |
1962 | reply_q->irq_line_enable = true; | |
1963 | reply_q->os_irq = pci_irq_vector(ioc->pdev, | |
1964 | reply_q->msix_index); | |
1965 | } | |
f92363d1 SR |
1966 | } |
1967 | ||
1968 | /** | |
1969 | * _base_is_controller_msix_enabled - is controller support muli-reply queues | |
1970 | * @ioc: per adapter object | |
1971 | * | |
4beb4867 | 1972 | * Return: Whether or not MSI/X is enabled. |
f92363d1 SR |
1973 | */ |
1974 | static inline int | |
1975 | _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc) | |
1976 | { | |
1977 | return (ioc->facts.IOCCapabilities & | |
1978 | MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable; | |
1979 | } | |
1980 | ||
1981 | /** | |
5f0dfb7a | 1982 | * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts |
f92363d1 | 1983 | * @ioc: per adapter object |
711a923c SP |
1984 | * @poll: poll over reply descriptor pools incase interrupt for |
1985 | * timed-out SCSI command got delayed | |
2910a4a9 | 1986 | * Context: non-ISR context |
f92363d1 | 1987 | * |
5f0dfb7a | 1988 | * Called when a Task Management request has completed. |
f92363d1 SR |
1989 | */ |
1990 | void | |
711a923c | 1991 | mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc, u8 poll) |
f92363d1 SR |
1992 | { |
1993 | struct adapter_reply_queue *reply_q; | |
1994 | ||
1995 | /* If MSIX capability is turned off | |
1996 | * then multi-queues are not enabled | |
1997 | */ | |
1998 | if (!_base_is_controller_msix_enabled(ioc)) | |
1999 | return; | |
2000 | ||
2001 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { | |
5f0dfb7a C |
2002 | if (ioc->shost_recovery || ioc->remove_host || |
2003 | ioc->pci_error_recovery) | |
f92363d1 SR |
2004 | return; |
2005 | /* TMs are on msix_index == 0 */ | |
2006 | if (reply_q->msix_index == 0) | |
2007 | continue; | |
432bc7ca SR |
2008 | |
2009 | if (reply_q->is_iouring_poll_q) { | |
2010 | _base_process_reply_queue(reply_q); | |
2011 | continue; | |
2012 | } | |
2013 | ||
45181eab | 2014 | synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index)); |
320e77ac SP |
2015 | if (reply_q->irq_poll_scheduled) { |
2016 | /* Calling irq_poll_disable will wait for any pending | |
2017 | * callbacks to have completed. | |
2018 | */ | |
2019 | irq_poll_disable(&reply_q->irqpoll); | |
2020 | irq_poll_enable(&reply_q->irqpoll); | |
45181eab TH |
2021 | /* check how the scheduled poll has ended, |
2022 | * clean up only if necessary | |
2023 | */ | |
2024 | if (reply_q->irq_poll_scheduled) { | |
2025 | reply_q->irq_poll_scheduled = false; | |
2026 | reply_q->irq_line_enable = true; | |
2027 | enable_irq(reply_q->os_irq); | |
2028 | } | |
320e77ac | 2029 | } |
69ad4ef8 ML |
2030 | |
2031 | if (poll) | |
2032 | _base_process_reply_queue(reply_q); | |
f92363d1 SR |
2033 | } |
2034 | } | |
2035 | ||
2036 | /** | |
2037 | * mpt3sas_base_release_callback_handler - clear interrupt callback handler | |
2038 | * @cb_idx: callback index | |
f92363d1 SR |
2039 | */ |
2040 | void | |
2041 | mpt3sas_base_release_callback_handler(u8 cb_idx) | |
2042 | { | |
2043 | mpt_callbacks[cb_idx] = NULL; | |
2044 | } | |
2045 | ||
2046 | /** | |
2047 | * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler | |
2048 | * @cb_func: callback function | |
2049 | * | |
4beb4867 | 2050 | * Return: Index of @cb_func. |
f92363d1 SR |
2051 | */ |
2052 | u8 | |
2053 | mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func) | |
2054 | { | |
2055 | u8 cb_idx; | |
2056 | ||
2057 | for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--) | |
2058 | if (mpt_callbacks[cb_idx] == NULL) | |
2059 | break; | |
2060 | ||
2061 | mpt_callbacks[cb_idx] = cb_func; | |
2062 | return cb_idx; | |
2063 | } | |
2064 | ||
2065 | /** | |
2066 | * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler | |
f92363d1 SR |
2067 | */ |
2068 | void | |
2069 | mpt3sas_base_initialize_callback_handler(void) | |
2070 | { | |
2071 | u8 cb_idx; | |
2072 | ||
2073 | for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++) | |
2074 | mpt3sas_base_release_callback_handler(cb_idx); | |
2075 | } | |
2076 | ||
2077 | ||
2078 | /** | |
2079 | * _base_build_zero_len_sge - build zero length sg entry | |
2080 | * @ioc: per adapter object | |
2081 | * @paddr: virtual address for SGE | |
2082 | * | |
2083 | * Create a zero length scatter gather entry to insure the IOCs hardware has | |
2084 | * something to use if the target device goes brain dead and tries | |
2085 | * to send data even when none is asked for. | |
f92363d1 SR |
2086 | */ |
2087 | static void | |
2088 | _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr) | |
2089 | { | |
2090 | u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT | | |
2091 | MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST | | |
2092 | MPI2_SGE_FLAGS_SIMPLE_ELEMENT) << | |
2093 | MPI2_SGE_FLAGS_SHIFT); | |
2094 | ioc->base_add_sg_single(paddr, flags_length, -1); | |
2095 | } | |
2096 | ||
2097 | /** | |
2098 | * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr. | |
2099 | * @paddr: virtual address for SGE | |
2100 | * @flags_length: SGE flags and data transfer length | |
2101 | * @dma_addr: Physical address | |
f92363d1 SR |
2102 | */ |
2103 | static void | |
2104 | _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr) | |
2105 | { | |
2106 | Mpi2SGESimple32_t *sgel = paddr; | |
2107 | ||
2108 | flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING | | |
2109 | MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; | |
2110 | sgel->FlagsLength = cpu_to_le32(flags_length); | |
2111 | sgel->Address = cpu_to_le32(dma_addr); | |
2112 | } | |
2113 | ||
2114 | ||
2115 | /** | |
2116 | * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr. | |
2117 | * @paddr: virtual address for SGE | |
2118 | * @flags_length: SGE flags and data transfer length | |
2119 | * @dma_addr: Physical address | |
f92363d1 SR |
2120 | */ |
2121 | static void | |
2122 | _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr) | |
2123 | { | |
2124 | Mpi2SGESimple64_t *sgel = paddr; | |
2125 | ||
2126 | flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING | | |
2127 | MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; | |
2128 | sgel->FlagsLength = cpu_to_le32(flags_length); | |
2129 | sgel->Address = cpu_to_le64(dma_addr); | |
2130 | } | |
2131 | ||
2132 | /** | |
2133 | * _base_get_chain_buffer_tracker - obtain chain tracker | |
2134 | * @ioc: per adapter object | |
dbec4c90 | 2135 | * @scmd: SCSI commands of the IO request |
f92363d1 | 2136 | * |
4beb4867 | 2137 | * Return: chain tracker from chain_lookup table using key as |
93204b78 | 2138 | * smid and smid's chain_offset. |
f92363d1 SR |
2139 | */ |
2140 | static struct chain_tracker * | |
dbec4c90 SPS |
2141 | _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, |
2142 | struct scsi_cmnd *scmd) | |
f92363d1 SR |
2143 | { |
2144 | struct chain_tracker *chain_req; | |
dbec4c90 | 2145 | struct scsiio_tracker *st = scsi_cmd_priv(scmd); |
93204b78 C |
2146 | u16 smid = st->smid; |
2147 | u8 chain_offset = | |
2148 | atomic_read(&ioc->chain_lookup[smid - 1].chain_offset); | |
f92363d1 | 2149 | |
93204b78 | 2150 | if (chain_offset == ioc->chains_needed_per_io) |
f92363d1 | 2151 | return NULL; |
93204b78 C |
2152 | |
2153 | chain_req = &ioc->chain_lookup[smid - 1].chains_per_smid[chain_offset]; | |
2154 | atomic_inc(&ioc->chain_lookup[smid - 1].chain_offset); | |
f92363d1 SR |
2155 | return chain_req; |
2156 | } | |
2157 | ||
2158 | ||
2159 | /** | |
2160 | * _base_build_sg - build generic sg | |
2161 | * @ioc: per adapter object | |
2162 | * @psge: virtual address for SGE | |
2163 | * @data_out_dma: physical address for WRITES | |
2164 | * @data_out_sz: data xfer size for WRITES | |
2165 | * @data_in_dma: physical address for READS | |
2166 | * @data_in_sz: data xfer size for READS | |
f92363d1 SR |
2167 | */ |
2168 | static void | |
2169 | _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge, | |
2170 | dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, | |
2171 | size_t data_in_sz) | |
2172 | { | |
2173 | u32 sgl_flags; | |
2174 | ||
2175 | if (!data_out_sz && !data_in_sz) { | |
2176 | _base_build_zero_len_sge(ioc, psge); | |
2177 | return; | |
2178 | } | |
2179 | ||
2180 | if (data_out_sz && data_in_sz) { | |
2181 | /* WRITE sgel first */ | |
2182 | sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | | |
2183 | MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC); | |
2184 | sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; | |
2185 | ioc->base_add_sg_single(psge, sgl_flags | | |
2186 | data_out_sz, data_out_dma); | |
2187 | ||
2188 | /* incr sgel */ | |
2189 | psge += ioc->sge_size; | |
2190 | ||
2191 | /* READ sgel last */ | |
2192 | sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | | |
2193 | MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | | |
2194 | MPI2_SGE_FLAGS_END_OF_LIST); | |
2195 | sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; | |
2196 | ioc->base_add_sg_single(psge, sgl_flags | | |
2197 | data_in_sz, data_in_dma); | |
2198 | } else if (data_out_sz) /* WRITE */ { | |
2199 | sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | | |
2200 | MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | | |
2201 | MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC); | |
2202 | sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; | |
2203 | ioc->base_add_sg_single(psge, sgl_flags | | |
2204 | data_out_sz, data_out_dma); | |
2205 | } else if (data_in_sz) /* READ */ { | |
2206 | sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | | |
2207 | MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | | |
2208 | MPI2_SGE_FLAGS_END_OF_LIST); | |
2209 | sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; | |
2210 | ioc->base_add_sg_single(psge, sgl_flags | | |
2211 | data_in_sz, data_in_dma); | |
2212 | } | |
2213 | } | |
2214 | ||
aff39e61 SPS |
2215 | /* IEEE format sgls */ |
2216 | ||
2217 | /** | |
2218 | * _base_build_nvme_prp - This function is called for NVMe end devices to build | |
2910a4a9 RD |
2219 | * a native SGL (NVMe PRP). |
2220 | * @ioc: per adapter object | |
2221 | * @smid: system request message index for getting asscociated SGL | |
2222 | * @nvme_encap_request: the NVMe request msg frame pointer | |
2223 | * @data_out_dma: physical address for WRITES | |
2224 | * @data_out_sz: data xfer size for WRITES | |
2225 | * @data_in_dma: physical address for READS | |
2226 | * @data_in_sz: data xfer size for READS | |
2227 | * | |
2228 | * The native SGL is built starting in the first PRP | |
aff39e61 SPS |
2229 | * entry of the NVMe message (PRP1). If the data buffer is small enough to be |
2230 | * described entirely using PRP1, then PRP2 is not used. If needed, PRP2 is | |
2231 | * used to describe a larger data buffer. If the data buffer is too large to | |
2232 | * describe using the two PRP entriess inside the NVMe message, then PRP1 | |
2233 | * describes the first data memory segment, and PRP2 contains a pointer to a PRP | |
2234 | * list located elsewhere in memory to describe the remaining data memory | |
2235 | * segments. The PRP list will be contiguous. | |
4beb4867 | 2236 | * |
aff39e61 SPS |
2237 | * The native SGL for NVMe devices is a Physical Region Page (PRP). A PRP |
2238 | * consists of a list of PRP entries to describe a number of noncontigous | |
2239 | * physical memory segments as a single memory buffer, just as a SGL does. Note | |
2240 | * however, that this function is only used by the IOCTL call, so the memory | |
2241 | * given will be guaranteed to be contiguous. There is no need to translate | |
2242 | * non-contiguous SGL into a PRP in this case. All PRPs will describe | |
2243 | * contiguous space that is one page size each. | |
2244 | * | |
2245 | * Each NVMe message contains two PRP entries. The first (PRP1) either contains | |
2246 | * a PRP list pointer or a PRP element, depending upon the command. PRP2 | |
2247 | * contains the second PRP element if the memory being described fits within 2 | |
2248 | * PRP entries, or a PRP list pointer if the PRP spans more than two entries. | |
2249 | * | |
2250 | * A PRP list pointer contains the address of a PRP list, structured as a linear | |
2251 | * array of PRP entries. Each PRP entry in this list describes a segment of | |
2252 | * physical memory. | |
2253 | * | |
2254 | * Each 64-bit PRP entry comprises an address and an offset field. The address | |
2255 | * always points at the beginning of a 4KB physical memory page, and the offset | |
2256 | * describes where within that 4KB page the memory segment begins. Only the | |
2910a4a9 | 2257 | * first element in a PRP list may contain a non-zero offset, implying that all |
aff39e61 SPS |
2258 | * memory segments following the first begin at the start of a 4KB page. |
2259 | * | |
2260 | * Each PRP element normally describes 4KB of physical memory, with exceptions | |
2261 | * for the first and last elements in the list. If the memory being described | |
2262 | * by the list begins at a non-zero offset within the first 4KB page, then the | |
2263 | * first PRP element will contain a non-zero offset indicating where the region | |
2264 | * begins within the 4KB page. The last memory segment may end before the end | |
2265 | * of the 4KB segment, depending upon the overall size of the memory being | |
2266 | * described by the PRP list. | |
2267 | * | |
2268 | * Since PRP entries lack any indication of size, the overall data buffer length | |
2269 | * is used to determine where the end of the data memory buffer is located, and | |
2270 | * how many PRP entries are required to describe it. | |
aff39e61 SPS |
2271 | */ |
2272 | static void | |
2273 | _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, | |
2274 | Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, | |
2275 | dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, | |
2276 | size_t data_in_sz) | |
2277 | { | |
2278 | int prp_size = NVME_PRP_SIZE; | |
d8335ae2 AB |
2279 | __le64 *prp_entry, *prp1_entry, *prp2_entry; |
2280 | __le64 *prp_page; | |
2281 | dma_addr_t prp_entry_dma, prp_page_dma, dma_addr; | |
aff39e61 SPS |
2282 | u32 offset, entry_len; |
2283 | u32 page_mask_result, page_mask; | |
aff39e61 | 2284 | size_t length; |
84203b35 BVA |
2285 | struct mpt3sas_nvme_cmd *nvme_cmd = |
2286 | (void *)nvme_encap_request->NVMe_Command; | |
aff39e61 SPS |
2287 | |
2288 | /* | |
2289 | * Not all commands require a data transfer. If no data, just return | |
2290 | * without constructing any PRP. | |
2291 | */ | |
2292 | if (!data_in_sz && !data_out_sz) | |
2293 | return; | |
84203b35 BVA |
2294 | prp1_entry = &nvme_cmd->prp1; |
2295 | prp2_entry = &nvme_cmd->prp2; | |
aff39e61 SPS |
2296 | prp_entry = prp1_entry; |
2297 | /* | |
2298 | * For the PRP entries, use the specially allocated buffer of | |
2299 | * contiguous memory. | |
2300 | */ | |
494f401b | 2301 | prp_page = (__le64 *)mpt3sas_base_get_pcie_sgl(ioc, smid); |
d8335ae2 | 2302 | prp_page_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid); |
aff39e61 SPS |
2303 | |
2304 | /* | |
2305 | * Check if we are within 1 entry of a page boundary we don't | |
2306 | * want our first entry to be a PRP List entry. | |
2307 | */ | |
2308 | page_mask = ioc->page_size - 1; | |
2309 | page_mask_result = (uintptr_t)((u8 *)prp_page + prp_size) & page_mask; | |
2310 | if (!page_mask_result) { | |
2311 | /* Bump up to next page boundary. */ | |
494f401b | 2312 | prp_page = (__le64 *)((u8 *)prp_page + prp_size); |
d8335ae2 | 2313 | prp_page_dma = prp_page_dma + prp_size; |
aff39e61 SPS |
2314 | } |
2315 | ||
2316 | /* | |
2317 | * Set PRP physical pointer, which initially points to the current PRP | |
2318 | * DMA memory page. | |
2319 | */ | |
d8335ae2 | 2320 | prp_entry_dma = prp_page_dma; |
aff39e61 SPS |
2321 | |
2322 | /* Get physical address and length of the data buffer. */ | |
2323 | if (data_in_sz) { | |
d8335ae2 | 2324 | dma_addr = data_in_dma; |
aff39e61 SPS |
2325 | length = data_in_sz; |
2326 | } else { | |
d8335ae2 | 2327 | dma_addr = data_out_dma; |
aff39e61 SPS |
2328 | length = data_out_sz; |
2329 | } | |
2330 | ||
2331 | /* Loop while the length is not zero. */ | |
2332 | while (length) { | |
2333 | /* | |
2334 | * Check if we need to put a list pointer here if we are at | |
2335 | * page boundary - prp_size (8 bytes). | |
2336 | */ | |
d8335ae2 | 2337 | page_mask_result = (prp_entry_dma + prp_size) & page_mask; |
aff39e61 SPS |
2338 | if (!page_mask_result) { |
2339 | /* | |
2340 | * This is the last entry in a PRP List, so we need to | |
2341 | * put a PRP list pointer here. What this does is: | |
2342 | * - bump the current memory pointer to the next | |
2343 | * address, which will be the next full page. | |
2344 | * - set the PRP Entry to point to that page. This | |
2345 | * is now the PRP List pointer. | |
2346 | * - bump the PRP Entry pointer the start of the | |
2347 | * next page. Since all of this PRP memory is | |
2348 | * contiguous, no need to get a new page - it's | |
2349 | * just the next address. | |
2350 | */ | |
d8335ae2 AB |
2351 | prp_entry_dma++; |
2352 | *prp_entry = cpu_to_le64(prp_entry_dma); | |
aff39e61 SPS |
2353 | prp_entry++; |
2354 | } | |
2355 | ||
2356 | /* Need to handle if entry will be part of a page. */ | |
d8335ae2 | 2357 | offset = dma_addr & page_mask; |
aff39e61 SPS |
2358 | entry_len = ioc->page_size - offset; |
2359 | ||
2360 | if (prp_entry == prp1_entry) { | |
2361 | /* | |
2362 | * Must fill in the first PRP pointer (PRP1) before | |
2363 | * moving on. | |
2364 | */ | |
d8335ae2 | 2365 | *prp1_entry = cpu_to_le64(dma_addr); |
aff39e61 SPS |
2366 | |
2367 | /* | |
2368 | * Now point to the second PRP entry within the | |
2369 | * command (PRP2). | |
2370 | */ | |
2371 | prp_entry = prp2_entry; | |
2372 | } else if (prp_entry == prp2_entry) { | |
2373 | /* | |
2374 | * Should the PRP2 entry be a PRP List pointer or just | |
2375 | * a regular PRP pointer? If there is more than one | |
2376 | * more page of data, must use a PRP List pointer. | |
2377 | */ | |
2378 | if (length > ioc->page_size) { | |
2379 | /* | |
2380 | * PRP2 will contain a PRP List pointer because | |
2381 | * more PRP's are needed with this command. The | |
2382 | * list will start at the beginning of the | |
2383 | * contiguous buffer. | |
2384 | */ | |
d8335ae2 | 2385 | *prp2_entry = cpu_to_le64(prp_entry_dma); |
aff39e61 SPS |
2386 | |
2387 | /* | |
2388 | * The next PRP Entry will be the start of the | |
2389 | * first PRP List. | |
2390 | */ | |
2391 | prp_entry = prp_page; | |
2392 | } else { | |
2393 | /* | |
2394 | * After this, the PRP Entries are complete. | |
2395 | * This command uses 2 PRP's and no PRP list. | |
2396 | */ | |
d8335ae2 | 2397 | *prp2_entry = cpu_to_le64(dma_addr); |
aff39e61 SPS |
2398 | } |
2399 | } else { | |
2400 | /* | |
2401 | * Put entry in list and bump the addresses. | |
2402 | * | |
2403 | * After PRP1 and PRP2 are filled in, this will fill in | |
2404 | * all remaining PRP entries in a PRP List, one per | |
2405 | * each time through the loop. | |
2406 | */ | |
d8335ae2 | 2407 | *prp_entry = cpu_to_le64(dma_addr); |
aff39e61 | 2408 | prp_entry++; |
d8335ae2 | 2409 | prp_entry_dma++; |
aff39e61 SPS |
2410 | } |
2411 | ||
2412 | /* | |
2413 | * Bump the phys address of the command's data buffer by the | |
2414 | * entry_len. | |
2415 | */ | |
d8335ae2 | 2416 | dma_addr += entry_len; |
aff39e61 SPS |
2417 | |
2418 | /* Decrement length accounting for last partial page. */ | |
2419 | if (entry_len > length) | |
2420 | length = 0; | |
2421 | else | |
2422 | length -= entry_len; | |
2423 | } | |
2424 | } | |
2425 | ||
016d5c35 | 2426 | /** |
2910a4a9 RD |
2427 | * base_make_prp_nvme - Prepare PRPs (Physical Region Page) - |
2428 | * SGLs specific to NVMe drives only | |
016d5c35 SPS |
2429 | * |
2430 | * @ioc: per adapter object | |
2431 | * @scmd: SCSI command from the mid-layer | |
2432 | * @mpi_request: mpi request | |
2433 | * @smid: msg Index | |
2434 | * @sge_count: scatter gather element count. | |
2435 | * | |
4beb4867 | 2436 | * Return: true: PRPs are built |
016d5c35 SPS |
2437 | * false: IEEE SGLs needs to be built |
2438 | */ | |
494f401b | 2439 | static void |
016d5c35 SPS |
2440 | base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc, |
2441 | struct scsi_cmnd *scmd, | |
2442 | Mpi25SCSIIORequest_t *mpi_request, | |
2443 | u16 smid, int sge_count) | |
2444 | { | |
d8335ae2 | 2445 | int sge_len, num_prp_in_chain = 0; |
016d5c35 | 2446 | Mpi25IeeeSgeChain64_t *main_chain_element, *ptr_first_sgl; |
494f401b | 2447 | __le64 *curr_buff; |
d8335ae2 | 2448 | dma_addr_t msg_dma, sge_addr, offset; |
016d5c35 SPS |
2449 | u32 page_mask, page_mask_result; |
2450 | struct scatterlist *sg_scmd; | |
2451 | u32 first_prp_len; | |
2452 | int data_len = scsi_bufflen(scmd); | |
2453 | u32 nvme_pg_size; | |
2454 | ||
2455 | nvme_pg_size = max_t(u32, ioc->page_size, NVME_PRP_PAGE_SIZE); | |
2456 | /* | |
2457 | * Nvme has a very convoluted prp format. One prp is required | |
2458 | * for each page or partial page. Driver need to split up OS sg_list | |
2459 | * entries if it is longer than one page or cross a page | |
2460 | * boundary. Driver also have to insert a PRP list pointer entry as | |
2461 | * the last entry in each physical page of the PRP list. | |
2462 | * | |
2463 | * NOTE: The first PRP "entry" is actually placed in the first | |
2464 | * SGL entry in the main message as IEEE 64 format. The 2nd | |
2465 | * entry in the main message is the chain element, and the rest | |
2466 | * of the PRP entries are built in the contiguous pcie buffer. | |
2467 | */ | |
2468 | page_mask = nvme_pg_size - 1; | |
2469 | ||
2470 | /* | |
2471 | * Native SGL is needed. | |
2472 | * Put a chain element in main message frame that points to the first | |
2473 | * chain buffer. | |
2474 | * | |
2475 | * NOTE: The ChainOffset field must be 0 when using a chain pointer to | |
2476 | * a native SGL. | |
2477 | */ | |
2478 | ||
2479 | /* Set main message chain element pointer */ | |
2480 | main_chain_element = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL; | |
2481 | /* | |
2482 | * For NVMe the chain element needs to be the 2nd SG entry in the main | |
2483 | * message. | |
2484 | */ | |
2485 | main_chain_element = (Mpi25IeeeSgeChain64_t *) | |
2486 | ((u8 *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64)); | |
2487 | ||
2488 | /* | |
2489 | * For the PRP entries, use the specially allocated buffer of | |
2490 | * contiguous memory. Normal chain buffers can't be used | |
2491 | * because each chain buffer would need to be the size of an OS | |
2492 | * page (4k). | |
2493 | */ | |
2494 | curr_buff = mpt3sas_base_get_pcie_sgl(ioc, smid); | |
d8335ae2 | 2495 | msg_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid); |
016d5c35 | 2496 | |
d8335ae2 | 2497 | main_chain_element->Address = cpu_to_le64(msg_dma); |
016d5c35 SPS |
2498 | main_chain_element->NextChainOffset = 0; |
2499 | main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | | |
2500 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | | |
2501 | MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP; | |
2502 | ||
2503 | /* Build first prp, sge need not to be page aligned*/ | |
2504 | ptr_first_sgl = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL; | |
2505 | sg_scmd = scsi_sglist(scmd); | |
2506 | sge_addr = sg_dma_address(sg_scmd); | |
2507 | sge_len = sg_dma_len(sg_scmd); | |
2508 | ||
d8335ae2 | 2509 | offset = sge_addr & page_mask; |
016d5c35 SPS |
2510 | first_prp_len = nvme_pg_size - offset; |
2511 | ||
2512 | ptr_first_sgl->Address = cpu_to_le64(sge_addr); | |
2513 | ptr_first_sgl->Length = cpu_to_le32(first_prp_len); | |
2514 | ||
2515 | data_len -= first_prp_len; | |
2516 | ||
2517 | if (sge_len > first_prp_len) { | |
2518 | sge_addr += first_prp_len; | |
2519 | sge_len -= first_prp_len; | |
2520 | } else if (data_len && (sge_len == first_prp_len)) { | |
2521 | sg_scmd = sg_next(sg_scmd); | |
2522 | sge_addr = sg_dma_address(sg_scmd); | |
2523 | sge_len = sg_dma_len(sg_scmd); | |
2524 | } | |
2525 | ||
2526 | for (;;) { | |
d8335ae2 | 2527 | offset = sge_addr & page_mask; |
016d5c35 SPS |
2528 | |
2529 | /* Put PRP pointer due to page boundary*/ | |
2530 | page_mask_result = (uintptr_t)(curr_buff + 1) & page_mask; | |
2531 | if (unlikely(!page_mask_result)) { | |
2532 | scmd_printk(KERN_NOTICE, | |
2533 | scmd, "page boundary curr_buff: 0x%p\n", | |
2534 | curr_buff); | |
d8335ae2 AB |
2535 | msg_dma += 8; |
2536 | *curr_buff = cpu_to_le64(msg_dma); | |
016d5c35 SPS |
2537 | curr_buff++; |
2538 | num_prp_in_chain++; | |
2539 | } | |
2540 | ||
2541 | *curr_buff = cpu_to_le64(sge_addr); | |
2542 | curr_buff++; | |
d8335ae2 | 2543 | msg_dma += 8; |
016d5c35 SPS |
2544 | num_prp_in_chain++; |
2545 | ||
2546 | sge_addr += nvme_pg_size; | |
2547 | sge_len -= nvme_pg_size; | |
2548 | data_len -= nvme_pg_size; | |
2549 | ||
2550 | if (data_len <= 0) | |
2551 | break; | |
2552 | ||
2553 | if (sge_len > 0) | |
2554 | continue; | |
2555 | ||
2556 | sg_scmd = sg_next(sg_scmd); | |
2557 | sge_addr = sg_dma_address(sg_scmd); | |
2558 | sge_len = sg_dma_len(sg_scmd); | |
2559 | } | |
2560 | ||
2561 | main_chain_element->Length = | |
2562 | cpu_to_le32(num_prp_in_chain * sizeof(u64)); | |
2563 | return; | |
2564 | } | |
2565 | ||
2566 | static bool | |
2567 | base_is_prp_possible(struct MPT3SAS_ADAPTER *ioc, | |
2568 | struct _pcie_device *pcie_device, struct scsi_cmnd *scmd, int sge_count) | |
2569 | { | |
2570 | u32 data_length = 0; | |
016d5c35 SPS |
2571 | bool build_prp = true; |
2572 | ||
494f401b | 2573 | data_length = scsi_bufflen(scmd); |
5bb309db SP |
2574 | if (pcie_device && |
2575 | (mpt3sas_scsih_is_pcie_scsi_device(pcie_device->device_info))) { | |
2576 | build_prp = false; | |
2577 | return build_prp; | |
2578 | } | |
016d5c35 SPS |
2579 | |
2580 | /* If Datalenth is <= 16K and number of SGE’s entries are <= 2 | |
2581 | * we built IEEE SGL | |
2582 | */ | |
2583 | if ((data_length <= NVME_PRP_PAGE_SIZE*4) && (sge_count <= 2)) | |
2584 | build_prp = false; | |
2585 | ||
2586 | return build_prp; | |
2587 | } | |
2588 | ||
2589 | /** | |
2590 | * _base_check_pcie_native_sgl - This function is called for PCIe end devices to | |
2591 | * determine if the driver needs to build a native SGL. If so, that native | |
2592 | * SGL is built in the special contiguous buffers allocated especially for | |
2593 | * PCIe SGL creation. If the driver will not build a native SGL, return | |
2594 | * TRUE and a normal IEEE SGL will be built. Currently this routine | |
2595 | * supports NVMe. | |
2596 | * @ioc: per adapter object | |
2597 | * @mpi_request: mf request pointer | |
2598 | * @smid: system request message index | |
2599 | * @scmd: scsi command | |
2600 | * @pcie_device: points to the PCIe device's info | |
2601 | * | |
4beb4867 | 2602 | * Return: 0 if native SGL was built, 1 if no SGL was built |
016d5c35 SPS |
2603 | */ |
2604 | static int | |
2605 | _base_check_pcie_native_sgl(struct MPT3SAS_ADAPTER *ioc, | |
2606 | Mpi25SCSIIORequest_t *mpi_request, u16 smid, struct scsi_cmnd *scmd, | |
2607 | struct _pcie_device *pcie_device) | |
2608 | { | |
016d5c35 SPS |
2609 | int sges_left; |
2610 | ||
2611 | /* Get the SG list pointer and info. */ | |
016d5c35 | 2612 | sges_left = scsi_dma_map(scmd); |
0c25422d | 2613 | if (sges_left < 0) |
016d5c35 | 2614 | return 1; |
016d5c35 SPS |
2615 | |
2616 | /* Check if we need to build a native SG list. */ | |
bfb3f00c YL |
2617 | if (!base_is_prp_possible(ioc, pcie_device, |
2618 | scmd, sges_left)) { | |
016d5c35 SPS |
2619 | /* We built a native SG list, just return. */ |
2620 | goto out; | |
2621 | } | |
2622 | ||
2623 | /* | |
2624 | * Build native NVMe PRP. | |
2625 | */ | |
2626 | base_make_prp_nvme(ioc, scmd, mpi_request, | |
2627 | smid, sges_left); | |
2628 | ||
2629 | return 0; | |
2630 | out: | |
2631 | scsi_dma_unmap(scmd); | |
2632 | return 1; | |
2633 | } | |
f92363d1 SR |
2634 | |
2635 | /** | |
2636 | * _base_add_sg_single_ieee - add sg element for IEEE format | |
2637 | * @paddr: virtual address for SGE | |
2638 | * @flags: SGE flags | |
2639 | * @chain_offset: number of 128 byte elements from start of segment | |
2640 | * @length: data transfer length | |
2641 | * @dma_addr: Physical address | |
f92363d1 SR |
2642 | */ |
2643 | static void | |
2644 | _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length, | |
2645 | dma_addr_t dma_addr) | |
2646 | { | |
2647 | Mpi25IeeeSgeChain64_t *sgel = paddr; | |
2648 | ||
2649 | sgel->Flags = flags; | |
2650 | sgel->NextChainOffset = chain_offset; | |
2651 | sgel->Length = cpu_to_le32(length); | |
2652 | sgel->Address = cpu_to_le64(dma_addr); | |
2653 | } | |
2654 | ||
2655 | /** | |
2656 | * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format | |
2657 | * @ioc: per adapter object | |
2658 | * @paddr: virtual address for SGE | |
2659 | * | |
2660 | * Create a zero length scatter gather entry to insure the IOCs hardware has | |
2661 | * something to use if the target device goes brain dead and tries | |
2662 | * to send data even when none is asked for. | |
f92363d1 SR |
2663 | */ |
2664 | static void | |
2665 | _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr) | |
2666 | { | |
2667 | u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | | |
2668 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | | |
2669 | MPI25_IEEE_SGE_FLAGS_END_OF_LIST); | |
b130b0d5 | 2670 | |
f92363d1 SR |
2671 | _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1); |
2672 | } | |
2673 | ||
471ef9d4 SR |
2674 | /** |
2675 | * _base_build_sg_scmd - main sg creation routine | |
016d5c35 | 2676 | * pcie_device is unused here! |
471ef9d4 SR |
2677 | * @ioc: per adapter object |
2678 | * @scmd: scsi command | |
2679 | * @smid: system request message index | |
016d5c35 | 2680 | * @unused: unused pcie_device pointer |
471ef9d4 SR |
2681 | * Context: none. |
2682 | * | |
2683 | * The main routine that builds scatter gather table from a given | |
2684 | * scsi request sent via the .queuecommand main handler. | |
2685 | * | |
4beb4867 | 2686 | * Return: 0 success, anything else error |
471ef9d4 SR |
2687 | */ |
2688 | static int | |
2689 | _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc, | |
016d5c35 | 2690 | struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *unused) |
471ef9d4 SR |
2691 | { |
2692 | Mpi2SCSIIORequest_t *mpi_request; | |
2693 | dma_addr_t chain_dma; | |
2694 | struct scatterlist *sg_scmd; | |
2695 | void *sg_local, *chain; | |
2696 | u32 chain_offset; | |
2697 | u32 chain_length; | |
2698 | u32 chain_flags; | |
2699 | int sges_left; | |
2700 | u32 sges_in_segment; | |
2701 | u32 sgl_flags; | |
2702 | u32 sgl_flags_last_element; | |
2703 | u32 sgl_flags_end_buffer; | |
2704 | struct chain_tracker *chain_req; | |
2705 | ||
2706 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
2707 | ||
2708 | /* init scatter gather flags */ | |
2709 | sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT; | |
2710 | if (scmd->sc_data_direction == DMA_TO_DEVICE) | |
2711 | sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC; | |
2712 | sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT) | |
2713 | << MPI2_SGE_FLAGS_SHIFT; | |
2714 | sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT | | |
2715 | MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST) | |
2716 | << MPI2_SGE_FLAGS_SHIFT; | |
2717 | sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; | |
2718 | ||
2719 | sg_scmd = scsi_sglist(scmd); | |
2720 | sges_left = scsi_dma_map(scmd); | |
0c25422d | 2721 | if (sges_left < 0) |
471ef9d4 | 2722 | return -ENOMEM; |
471ef9d4 SR |
2723 | |
2724 | sg_local = &mpi_request->SGL; | |
2725 | sges_in_segment = ioc->max_sges_in_main_message; | |
2726 | if (sges_left <= sges_in_segment) | |
2727 | goto fill_in_last_segment; | |
2728 | ||
2729 | mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) + | |
2730 | (sges_in_segment * ioc->sge_size))/4; | |
2731 | ||
2732 | /* fill in main message segment when there is a chain following */ | |
2733 | while (sges_in_segment) { | |
2734 | if (sges_in_segment == 1) | |
2735 | ioc->base_add_sg_single(sg_local, | |
2736 | sgl_flags_last_element | sg_dma_len(sg_scmd), | |
2737 | sg_dma_address(sg_scmd)); | |
2738 | else | |
2739 | ioc->base_add_sg_single(sg_local, sgl_flags | | |
2740 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
2741 | sg_scmd = sg_next(sg_scmd); | |
2742 | sg_local += ioc->sge_size; | |
2743 | sges_left--; | |
2744 | sges_in_segment--; | |
2745 | } | |
2746 | ||
2747 | /* initializing the chain flags and pointers */ | |
2748 | chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT; | |
dbec4c90 | 2749 | chain_req = _base_get_chain_buffer_tracker(ioc, scmd); |
471ef9d4 SR |
2750 | if (!chain_req) |
2751 | return -1; | |
2752 | chain = chain_req->chain_buffer; | |
2753 | chain_dma = chain_req->chain_buffer_dma; | |
2754 | do { | |
2755 | sges_in_segment = (sges_left <= | |
2756 | ioc->max_sges_in_chain_message) ? sges_left : | |
2757 | ioc->max_sges_in_chain_message; | |
2758 | chain_offset = (sges_left == sges_in_segment) ? | |
2759 | 0 : (sges_in_segment * ioc->sge_size)/4; | |
2760 | chain_length = sges_in_segment * ioc->sge_size; | |
2761 | if (chain_offset) { | |
2762 | chain_offset = chain_offset << | |
2763 | MPI2_SGE_CHAIN_OFFSET_SHIFT; | |
2764 | chain_length += ioc->sge_size; | |
2765 | } | |
2766 | ioc->base_add_sg_single(sg_local, chain_flags | chain_offset | | |
2767 | chain_length, chain_dma); | |
2768 | sg_local = chain; | |
2769 | if (!chain_offset) | |
2770 | goto fill_in_last_segment; | |
2771 | ||
2772 | /* fill in chain segments */ | |
2773 | while (sges_in_segment) { | |
2774 | if (sges_in_segment == 1) | |
2775 | ioc->base_add_sg_single(sg_local, | |
2776 | sgl_flags_last_element | | |
2777 | sg_dma_len(sg_scmd), | |
2778 | sg_dma_address(sg_scmd)); | |
2779 | else | |
2780 | ioc->base_add_sg_single(sg_local, sgl_flags | | |
2781 | sg_dma_len(sg_scmd), | |
2782 | sg_dma_address(sg_scmd)); | |
2783 | sg_scmd = sg_next(sg_scmd); | |
2784 | sg_local += ioc->sge_size; | |
2785 | sges_left--; | |
2786 | sges_in_segment--; | |
2787 | } | |
2788 | ||
dbec4c90 | 2789 | chain_req = _base_get_chain_buffer_tracker(ioc, scmd); |
471ef9d4 SR |
2790 | if (!chain_req) |
2791 | return -1; | |
2792 | chain = chain_req->chain_buffer; | |
2793 | chain_dma = chain_req->chain_buffer_dma; | |
2794 | } while (1); | |
2795 | ||
2796 | ||
2797 | fill_in_last_segment: | |
2798 | ||
2799 | /* fill the last segment */ | |
2800 | while (sges_left) { | |
2801 | if (sges_left == 1) | |
2802 | ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer | | |
2803 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
2804 | else | |
2805 | ioc->base_add_sg_single(sg_local, sgl_flags | | |
2806 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
2807 | sg_scmd = sg_next(sg_scmd); | |
2808 | sg_local += ioc->sge_size; | |
2809 | sges_left--; | |
2810 | } | |
2811 | ||
2812 | return 0; | |
2813 | } | |
2814 | ||
f92363d1 SR |
2815 | /** |
2816 | * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format | |
2817 | * @ioc: per adapter object | |
2818 | * @scmd: scsi command | |
2819 | * @smid: system request message index | |
016d5c35 SPS |
2820 | * @pcie_device: Pointer to pcie_device. If set, the pcie native sgl will be |
2821 | * constructed on need. | |
f92363d1 SR |
2822 | * Context: none. |
2823 | * | |
2824 | * The main routine that builds scatter gather table from a given | |
2825 | * scsi request sent via the .queuecommand main handler. | |
2826 | * | |
4beb4867 | 2827 | * Return: 0 success, anything else error |
f92363d1 SR |
2828 | */ |
2829 | static int | |
2830 | _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc, | |
016d5c35 | 2831 | struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device) |
f92363d1 | 2832 | { |
016d5c35 | 2833 | Mpi25SCSIIORequest_t *mpi_request; |
f92363d1 SR |
2834 | dma_addr_t chain_dma; |
2835 | struct scatterlist *sg_scmd; | |
2836 | void *sg_local, *chain; | |
2837 | u32 chain_offset; | |
2838 | u32 chain_length; | |
f92363d1 SR |
2839 | int sges_left; |
2840 | u32 sges_in_segment; | |
2841 | u8 simple_sgl_flags; | |
2842 | u8 simple_sgl_flags_last; | |
2843 | u8 chain_sgl_flags; | |
2844 | struct chain_tracker *chain_req; | |
2845 | ||
2846 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
2847 | ||
2848 | /* init scatter gather flags */ | |
2849 | simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | | |
2850 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; | |
2851 | simple_sgl_flags_last = simple_sgl_flags | | |
2852 | MPI25_IEEE_SGE_FLAGS_END_OF_LIST; | |
2853 | chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | | |
2854 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; | |
2855 | ||
016d5c35 SPS |
2856 | /* Check if we need to build a native SG list. */ |
2857 | if ((pcie_device) && (_base_check_pcie_native_sgl(ioc, mpi_request, | |
2858 | smid, scmd, pcie_device) == 0)) { | |
2859 | /* We built a native SG list, just return. */ | |
2860 | return 0; | |
2861 | } | |
2862 | ||
f92363d1 SR |
2863 | sg_scmd = scsi_sglist(scmd); |
2864 | sges_left = scsi_dma_map(scmd); | |
0c25422d | 2865 | if (sges_left < 0) |
f92363d1 | 2866 | return -ENOMEM; |
f92363d1 SR |
2867 | |
2868 | sg_local = &mpi_request->SGL; | |
2869 | sges_in_segment = (ioc->request_sz - | |
016d5c35 | 2870 | offsetof(Mpi25SCSIIORequest_t, SGL))/ioc->sge_size_ieee; |
f92363d1 SR |
2871 | if (sges_left <= sges_in_segment) |
2872 | goto fill_in_last_segment; | |
2873 | ||
2874 | mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) + | |
016d5c35 | 2875 | (offsetof(Mpi25SCSIIORequest_t, SGL)/ioc->sge_size_ieee); |
f92363d1 SR |
2876 | |
2877 | /* fill in main message segment when there is a chain following */ | |
2878 | while (sges_in_segment > 1) { | |
2879 | _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, | |
2880 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
2881 | sg_scmd = sg_next(sg_scmd); | |
2882 | sg_local += ioc->sge_size_ieee; | |
2883 | sges_left--; | |
2884 | sges_in_segment--; | |
2885 | } | |
2886 | ||
25ef16d0 | 2887 | /* initializing the pointers */ |
dbec4c90 | 2888 | chain_req = _base_get_chain_buffer_tracker(ioc, scmd); |
f92363d1 SR |
2889 | if (!chain_req) |
2890 | return -1; | |
2891 | chain = chain_req->chain_buffer; | |
2892 | chain_dma = chain_req->chain_buffer_dma; | |
2893 | do { | |
2894 | sges_in_segment = (sges_left <= | |
2895 | ioc->max_sges_in_chain_message) ? sges_left : | |
2896 | ioc->max_sges_in_chain_message; | |
2897 | chain_offset = (sges_left == sges_in_segment) ? | |
2898 | 0 : sges_in_segment; | |
2899 | chain_length = sges_in_segment * ioc->sge_size_ieee; | |
2900 | if (chain_offset) | |
2901 | chain_length += ioc->sge_size_ieee; | |
2902 | _base_add_sg_single_ieee(sg_local, chain_sgl_flags, | |
2903 | chain_offset, chain_length, chain_dma); | |
2904 | ||
2905 | sg_local = chain; | |
2906 | if (!chain_offset) | |
2907 | goto fill_in_last_segment; | |
2908 | ||
2909 | /* fill in chain segments */ | |
2910 | while (sges_in_segment) { | |
2911 | _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, | |
2912 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
2913 | sg_scmd = sg_next(sg_scmd); | |
2914 | sg_local += ioc->sge_size_ieee; | |
2915 | sges_left--; | |
2916 | sges_in_segment--; | |
2917 | } | |
2918 | ||
dbec4c90 | 2919 | chain_req = _base_get_chain_buffer_tracker(ioc, scmd); |
f92363d1 SR |
2920 | if (!chain_req) |
2921 | return -1; | |
2922 | chain = chain_req->chain_buffer; | |
2923 | chain_dma = chain_req->chain_buffer_dma; | |
2924 | } while (1); | |
2925 | ||
2926 | ||
2927 | fill_in_last_segment: | |
2928 | ||
2929 | /* fill the last segment */ | |
62f5c74c | 2930 | while (sges_left > 0) { |
f92363d1 SR |
2931 | if (sges_left == 1) |
2932 | _base_add_sg_single_ieee(sg_local, | |
2933 | simple_sgl_flags_last, 0, sg_dma_len(sg_scmd), | |
2934 | sg_dma_address(sg_scmd)); | |
2935 | else | |
2936 | _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, | |
2937 | sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); | |
2938 | sg_scmd = sg_next(sg_scmd); | |
2939 | sg_local += ioc->sge_size_ieee; | |
2940 | sges_left--; | |
2941 | } | |
2942 | ||
2943 | return 0; | |
2944 | } | |
2945 | ||
2946 | /** | |
2947 | * _base_build_sg_ieee - build generic sg for IEEE format | |
2948 | * @ioc: per adapter object | |
2949 | * @psge: virtual address for SGE | |
2950 | * @data_out_dma: physical address for WRITES | |
2951 | * @data_out_sz: data xfer size for WRITES | |
2952 | * @data_in_dma: physical address for READS | |
2953 | * @data_in_sz: data xfer size for READS | |
f92363d1 SR |
2954 | */ |
2955 | static void | |
2956 | _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge, | |
2957 | dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, | |
2958 | size_t data_in_sz) | |
2959 | { | |
2960 | u8 sgl_flags; | |
2961 | ||
2962 | if (!data_out_sz && !data_in_sz) { | |
2963 | _base_build_zero_len_sge_ieee(ioc, psge); | |
2964 | return; | |
2965 | } | |
2966 | ||
2967 | if (data_out_sz && data_in_sz) { | |
2968 | /* WRITE sgel first */ | |
2969 | sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | | |
2970 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; | |
2971 | _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, | |
2972 | data_out_dma); | |
2973 | ||
2974 | /* incr sgel */ | |
2975 | psge += ioc->sge_size_ieee; | |
2976 | ||
2977 | /* READ sgel last */ | |
2978 | sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; | |
2979 | _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, | |
2980 | data_in_dma); | |
2981 | } else if (data_out_sz) /* WRITE */ { | |
2982 | sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | | |
2983 | MPI25_IEEE_SGE_FLAGS_END_OF_LIST | | |
2984 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; | |
2985 | _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, | |
2986 | data_out_dma); | |
2987 | } else if (data_in_sz) /* READ */ { | |
2988 | sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | | |
2989 | MPI25_IEEE_SGE_FLAGS_END_OF_LIST | | |
2990 | MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; | |
2991 | _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, | |
2992 | data_in_dma); | |
2993 | } | |
2994 | } | |
2995 | ||
2996 | #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10)) | |
2997 | ||
2998 | /** | |
2999 | * _base_config_dma_addressing - set dma addressing | |
3000 | * @ioc: per adapter object | |
3001 | * @pdev: PCI device struct | |
3002 | * | |
4beb4867 | 3003 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
3004 | */ |
3005 | static int | |
3006 | _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev) | |
3007 | { | |
3008 | struct sysinfo s; | |
9df65096 | 3009 | u64 coherent_dma_mask, dma_mask; |
0448f019 | 3010 | |
06e472ac | 3011 | if (ioc->is_mcpu_endpoint || sizeof(dma_addr_t) == 4) { |
d6adc251 | 3012 | ioc->dma_mask = 32; |
9df65096 | 3013 | coherent_dma_mask = dma_mask = DMA_BIT_MASK(32); |
ba27c5cf | 3014 | /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */ |
9df65096 | 3015 | } else if (ioc->hba_mpi_version_belonged > MPI2_VERSION) { |
d6adc251 | 3016 | ioc->dma_mask = 63; |
9df65096 SR |
3017 | coherent_dma_mask = dma_mask = DMA_BIT_MASK(63); |
3018 | } else { | |
d6adc251 | 3019 | ioc->dma_mask = 64; |
9df65096 SR |
3020 | coherent_dma_mask = dma_mask = DMA_BIT_MASK(64); |
3021 | } | |
3022 | ||
3023 | if (ioc->use_32bit_dma) | |
3024 | coherent_dma_mask = DMA_BIT_MASK(32); | |
1c2048bd | 3025 | |
9df65096 SR |
3026 | if (dma_set_mask(&pdev->dev, dma_mask) || |
3027 | dma_set_coherent_mask(&pdev->dev, coherent_dma_mask)) | |
f92363d1 SR |
3028 | return -ENODEV; |
3029 | ||
d6adc251 | 3030 | if (ioc->dma_mask > 32) { |
ba27c5cf CH |
3031 | ioc->base_add_sg_single = &_base_add_sg_single_64; |
3032 | ioc->sge_size = sizeof(Mpi2SGESimple64_t); | |
3033 | } else { | |
3034 | ioc->base_add_sg_single = &_base_add_sg_single_32; | |
3035 | ioc->sge_size = sizeof(Mpi2SGESimple32_t); | |
3036 | } | |
3037 | ||
f92363d1 | 3038 | si_meminfo(&s); |
919d8a3f | 3039 | ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n", |
d6adc251 | 3040 | ioc->dma_mask, convert_to_kb(s.totalram)); |
9b05c91a SR |
3041 | |
3042 | return 0; | |
3043 | } | |
f92363d1 | 3044 | |
f92363d1 SR |
3045 | /** |
3046 | * _base_check_enable_msix - checks MSIX capabable. | |
3047 | * @ioc: per adapter object | |
3048 | * | |
3049 | * Check to see if card is capable of MSIX, and set number | |
3050 | * of available msix vectors | |
3051 | */ | |
3052 | static int | |
3053 | _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc) | |
3054 | { | |
3055 | int base; | |
3056 | u16 message_control; | |
3057 | ||
42081173 SR |
3058 | /* Check whether controller SAS2008 B0 controller, |
3059 | * if it is SAS2008 B0 controller use IO-APIC instead of MSIX | |
3060 | */ | |
3061 | if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 && | |
3062 | ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) { | |
3063 | return -EINVAL; | |
3064 | } | |
3065 | ||
f92363d1 SR |
3066 | base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX); |
3067 | if (!base) { | |
919d8a3f | 3068 | dfailprintk(ioc, ioc_info(ioc, "msix not supported\n")); |
f92363d1 SR |
3069 | return -EINVAL; |
3070 | } | |
3071 | ||
3072 | /* get msix vector count */ | |
42081173 SR |
3073 | /* NUMA_IO not supported for older controllers */ |
3074 | if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 || | |
3075 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 || | |
3076 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 || | |
3077 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 || | |
3078 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 || | |
3079 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 || | |
3080 | ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2) | |
3081 | ioc->msix_vector_count = 1; | |
3082 | else { | |
3083 | pci_read_config_word(ioc->pdev, base + 2, &message_control); | |
3084 | ioc->msix_vector_count = (message_control & 0x3FF) + 1; | |
3085 | } | |
919d8a3f JP |
3086 | dinitprintk(ioc, ioc_info(ioc, "msix is supported, vector_count(%d)\n", |
3087 | ioc->msix_vector_count)); | |
f92363d1 SR |
3088 | return 0; |
3089 | } | |
3090 | ||
3091 | /** | |
fae21608 | 3092 | * mpt3sas_base_free_irq - free irq |
f92363d1 SR |
3093 | * @ioc: per adapter object |
3094 | * | |
3095 | * Freeing respective reply_queue from the list. | |
3096 | */ | |
fae21608 SR |
3097 | void |
3098 | mpt3sas_base_free_irq(struct MPT3SAS_ADAPTER *ioc) | |
f92363d1 | 3099 | { |
fdb8ed13 | 3100 | unsigned int irq; |
f92363d1 SR |
3101 | struct adapter_reply_queue *reply_q, *next; |
3102 | ||
3103 | if (list_empty(&ioc->reply_queue_list)) | |
3104 | return; | |
3105 | ||
3106 | list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) { | |
3107 | list_del(&reply_q->list); | |
432bc7ca SR |
3108 | if (reply_q->is_iouring_poll_q) { |
3109 | kfree(reply_q); | |
3110 | continue; | |
3111 | } | |
3112 | ||
fdb8ed13 NNL |
3113 | if (ioc->smp_affinity_enable) { |
3114 | irq = pci_irq_vector(ioc->pdev, reply_q->msix_index); | |
3115 | irq_update_affinity_hint(irq, NULL); | |
3116 | } | |
1d55abc0 HR |
3117 | free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index), |
3118 | reply_q); | |
f92363d1 SR |
3119 | kfree(reply_q); |
3120 | } | |
3121 | } | |
3122 | ||
3123 | /** | |
3124 | * _base_request_irq - request irq | |
3125 | * @ioc: per adapter object | |
3126 | * @index: msix index into vector table | |
f92363d1 SR |
3127 | * |
3128 | * Inserting respective reply_queue into the list. | |
3129 | */ | |
3130 | static int | |
1d55abc0 | 3131 | _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index) |
f92363d1 | 3132 | { |
1d55abc0 | 3133 | struct pci_dev *pdev = ioc->pdev; |
f92363d1 | 3134 | struct adapter_reply_queue *reply_q; |
432bc7ca | 3135 | int r, qid; |
f92363d1 SR |
3136 | |
3137 | reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL); | |
3138 | if (!reply_q) { | |
919d8a3f JP |
3139 | ioc_err(ioc, "unable to allocate memory %zu!\n", |
3140 | sizeof(struct adapter_reply_queue)); | |
f92363d1 SR |
3141 | return -ENOMEM; |
3142 | } | |
3143 | reply_q->ioc = ioc; | |
3144 | reply_q->msix_index = index; | |
14b3114d | 3145 | |
f92363d1 | 3146 | atomic_set(&reply_q->busy, 0); |
432bc7ca SR |
3147 | |
3148 | if (index >= ioc->iopoll_q_start_index) { | |
3149 | qid = index - ioc->iopoll_q_start_index; | |
3150 | snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-mq-poll%d", | |
3151 | ioc->driver_name, ioc->id, qid); | |
3152 | reply_q->is_iouring_poll_q = 1; | |
3153 | ioc->io_uring_poll_queues[qid].reply_q = reply_q; | |
3154 | goto out; | |
3155 | } | |
3156 | ||
3157 | ||
f92363d1 SR |
3158 | if (ioc->msix_enable) |
3159 | snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d", | |
c84b06a4 | 3160 | ioc->driver_name, ioc->id, index); |
f92363d1 SR |
3161 | else |
3162 | snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d", | |
c84b06a4 | 3163 | ioc->driver_name, ioc->id); |
1d55abc0 HR |
3164 | r = request_irq(pci_irq_vector(pdev, index), _base_interrupt, |
3165 | IRQF_SHARED, reply_q->name, reply_q); | |
f92363d1 | 3166 | if (r) { |
fc7d510e | 3167 | pr_err("%s: unable to allocate interrupt %d!\n", |
1d55abc0 | 3168 | reply_q->name, pci_irq_vector(pdev, index)); |
da3cec25 | 3169 | kfree(reply_q); |
f92363d1 SR |
3170 | return -EBUSY; |
3171 | } | |
432bc7ca | 3172 | out: |
f92363d1 SR |
3173 | INIT_LIST_HEAD(&reply_q->list); |
3174 | list_add_tail(&reply_q->list, &ioc->reply_queue_list); | |
3175 | return 0; | |
3176 | } | |
3177 | ||
3178 | /** | |
3179 | * _base_assign_reply_queues - assigning msix index for each cpu | |
3180 | * @ioc: per adapter object | |
3181 | * | |
3182 | * The enduser would need to set the affinity via /proc/irq/#/smp_affinity | |
f92363d1 SR |
3183 | */ |
3184 | static void | |
3185 | _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc) | |
3186 | { | |
fdb8ed13 | 3187 | unsigned int cpu, nr_cpus, nr_msix, index = 0, irq; |
14b3114d | 3188 | struct adapter_reply_queue *reply_q; |
432bc7ca SR |
3189 | int iopoll_q_count = ioc->reply_queue_count - |
3190 | ioc->iopoll_q_start_index; | |
fdb8ed13 | 3191 | const struct cpumask *mask; |
f92363d1 SR |
3192 | |
3193 | if (!_base_is_controller_msix_enabled(ioc)) | |
3194 | return; | |
eedc42a0 SR |
3195 | |
3196 | if (ioc->msix_load_balance) | |
51e3b2ad | 3197 | return; |
f92363d1 SR |
3198 | |
3199 | memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz); | |
3200 | ||
91b265bf MP |
3201 | nr_cpus = num_online_cpus(); |
3202 | nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count, | |
3203 | ioc->facts.MaxMSIxVectors); | |
3204 | if (!nr_msix) | |
3205 | return; | |
f92363d1 | 3206 | |
610ef1e9 | 3207 | if (ioc->smp_affinity_enable) { |
728bbc6c SP |
3208 | |
3209 | /* | |
3210 | * set irq affinity to local numa node for those irqs | |
3211 | * corresponding to high iops queues. | |
3212 | */ | |
3213 | if (ioc->high_iops_queues) { | |
fdb8ed13 | 3214 | mask = cpumask_of_node(dev_to_node(&ioc->pdev->dev)); |
728bbc6c SP |
3215 | for (index = 0; index < ioc->high_iops_queues; |
3216 | index++) { | |
fdb8ed13 NNL |
3217 | irq = pci_irq_vector(ioc->pdev, index); |
3218 | irq_set_affinity_and_hint(irq, mask); | |
728bbc6c SP |
3219 | } |
3220 | } | |
3221 | ||
1d55abc0 | 3222 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { |
728bbc6c SP |
3223 | const cpumask_t *mask; |
3224 | ||
432bc7ca SR |
3225 | if (reply_q->msix_index < ioc->high_iops_queues || |
3226 | reply_q->msix_index >= ioc->iopoll_q_start_index) | |
728bbc6c SP |
3227 | continue; |
3228 | ||
3229 | mask = pci_irq_get_affinity(ioc->pdev, | |
3230 | reply_q->msix_index); | |
1d55abc0 | 3231 | if (!mask) { |
919d8a3f JP |
3232 | ioc_warn(ioc, "no affinity for msi %x\n", |
3233 | reply_q->msix_index); | |
728bbc6c | 3234 | goto fall_back; |
1d55abc0 HR |
3235 | } |
3236 | ||
4a8842de TH |
3237 | for_each_cpu_and(cpu, mask, cpu_online_mask) { |
3238 | if (cpu >= ioc->cpu_msix_table_sz) | |
3239 | break; | |
1d55abc0 | 3240 | ioc->cpu_msix_table[cpu] = reply_q->msix_index; |
4a8842de | 3241 | } |
1d55abc0 HR |
3242 | } |
3243 | return; | |
3244 | } | |
728bbc6c SP |
3245 | |
3246 | fall_back: | |
91b265bf | 3247 | cpu = cpumask_first(cpu_online_mask); |
432bc7ca | 3248 | nr_msix -= (ioc->high_iops_queues - iopoll_q_count); |
728bbc6c | 3249 | index = 0; |
91b265bf | 3250 | |
14b3114d | 3251 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { |
91b265bf MP |
3252 | unsigned int i, group = nr_cpus / nr_msix; |
3253 | ||
432bc7ca SR |
3254 | if (reply_q->msix_index < ioc->high_iops_queues || |
3255 | reply_q->msix_index >= ioc->iopoll_q_start_index) | |
728bbc6c SP |
3256 | continue; |
3257 | ||
14b3114d SR |
3258 | if (cpu >= nr_cpus) |
3259 | break; | |
3260 | ||
91b265bf MP |
3261 | if (index < nr_cpus % nr_msix) |
3262 | group++; | |
3263 | ||
3264 | for (i = 0 ; i < group ; i++) { | |
1d55abc0 | 3265 | ioc->cpu_msix_table[cpu] = reply_q->msix_index; |
91b265bf | 3266 | cpu = cpumask_next(cpu, cpu_online_mask); |
f92363d1 | 3267 | } |
91b265bf | 3268 | index++; |
14b3114d | 3269 | } |
f92363d1 SR |
3270 | } |
3271 | ||
18fd3d8c SP |
3272 | /** |
3273 | * _base_check_and_enable_high_iops_queues - enable high iops mode | |
9133d27e DLM |
3274 | * @ioc: per adapter object |
3275 | * @hba_msix_vector_count: msix vectors supported by HBA | |
18fd3d8c SP |
3276 | * |
3277 | * Enable high iops queues only if | |
3278 | * - HBA is a SEA/AERO controller and | |
3279 | * - MSI-Xs vector supported by the HBA is 128 and | |
3280 | * - total CPU count in the system >=16 and | |
3281 | * - loaded driver with default max_msix_vectors module parameter and | |
3282 | * - system booted in non kdump mode | |
3283 | * | |
2910a4a9 | 3284 | * Return: nothing. |
18fd3d8c SP |
3285 | */ |
3286 | static void | |
3287 | _base_check_and_enable_high_iops_queues(struct MPT3SAS_ADAPTER *ioc, | |
3288 | int hba_msix_vector_count) | |
3289 | { | |
48d6f0a6 | 3290 | u16 lnksta, speed; |
ca7e1e9d | 3291 | |
432bc7ca SR |
3292 | /* |
3293 | * Disable high iops queues if io uring poll queues are enabled. | |
3294 | */ | |
ca7e1e9d | 3295 | if (perf_mode == MPT_PERF_MODE_IOPS || |
432bc7ca SR |
3296 | perf_mode == MPT_PERF_MODE_LATENCY || |
3297 | ioc->io_uring_poll_queues) { | |
ca7e1e9d SP |
3298 | ioc->high_iops_queues = 0; |
3299 | return; | |
3300 | } | |
3301 | ||
3302 | if (perf_mode == MPT_PERF_MODE_DEFAULT) { | |
3303 | ||
48d6f0a6 SR |
3304 | pcie_capability_read_word(ioc->pdev, PCI_EXP_LNKSTA, &lnksta); |
3305 | speed = lnksta & PCI_EXP_LNKSTA_CLS; | |
ca7e1e9d | 3306 | |
48d6f0a6 | 3307 | if (speed < 0x4) { |
ca7e1e9d SP |
3308 | ioc->high_iops_queues = 0; |
3309 | return; | |
3310 | } | |
3311 | } | |
18fd3d8c SP |
3312 | |
3313 | if (!reset_devices && ioc->is_aero_ioc && | |
3314 | hba_msix_vector_count == MPT3SAS_GEN35_MAX_MSIX_QUEUES && | |
3315 | num_online_cpus() >= MPT3SAS_HIGH_IOPS_REPLY_QUEUES && | |
3316 | max_msix_vectors == -1) | |
3317 | ioc->high_iops_queues = MPT3SAS_HIGH_IOPS_REPLY_QUEUES; | |
3318 | else | |
3319 | ioc->high_iops_queues = 0; | |
3320 | } | |
3321 | ||
f92363d1 | 3322 | /** |
fae21608 | 3323 | * mpt3sas_base_disable_msix - disables msix |
f92363d1 SR |
3324 | * @ioc: per adapter object |
3325 | * | |
3326 | */ | |
fae21608 SR |
3327 | void |
3328 | mpt3sas_base_disable_msix(struct MPT3SAS_ADAPTER *ioc) | |
f92363d1 SR |
3329 | { |
3330 | if (!ioc->msix_enable) | |
3331 | return; | |
728bbc6c | 3332 | pci_free_irq_vectors(ioc->pdev); |
f92363d1 | 3333 | ioc->msix_enable = 0; |
432bc7ca | 3334 | kfree(ioc->io_uring_poll_queues); |
f92363d1 SR |
3335 | } |
3336 | ||
728bbc6c SP |
3337 | /** |
3338 | * _base_alloc_irq_vectors - allocate msix vectors | |
3339 | * @ioc: per adapter object | |
3340 | * | |
3341 | */ | |
3342 | static int | |
3343 | _base_alloc_irq_vectors(struct MPT3SAS_ADAPTER *ioc) | |
3344 | { | |
3345 | int i, irq_flags = PCI_IRQ_MSIX; | |
3346 | struct irq_affinity desc = { .pre_vectors = ioc->high_iops_queues }; | |
3347 | struct irq_affinity *descp = &desc; | |
432bc7ca SR |
3348 | /* |
3349 | * Don't allocate msix vectors for poll_queues. | |
3350 | * msix_vectors is always within a range of FW supported reply queue. | |
3351 | */ | |
3352 | int nr_msix_vectors = ioc->iopoll_q_start_index; | |
3353 | ||
728bbc6c | 3354 | |
610ef1e9 | 3355 | if (ioc->smp_affinity_enable) |
432bc7ca | 3356 | irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES; |
728bbc6c SP |
3357 | else |
3358 | descp = NULL; | |
3359 | ||
432bc7ca SR |
3360 | ioc_info(ioc, " %d %d %d\n", ioc->high_iops_queues, |
3361 | ioc->reply_queue_count, nr_msix_vectors); | |
728bbc6c SP |
3362 | |
3363 | i = pci_alloc_irq_vectors_affinity(ioc->pdev, | |
3364 | ioc->high_iops_queues, | |
432bc7ca | 3365 | nr_msix_vectors, irq_flags, descp); |
728bbc6c SP |
3366 | |
3367 | return i; | |
3368 | } | |
3369 | ||
f92363d1 SR |
3370 | /** |
3371 | * _base_enable_msix - enables msix, failback to io_apic | |
3372 | * @ioc: per adapter object | |
3373 | * | |
3374 | */ | |
3375 | static int | |
3376 | _base_enable_msix(struct MPT3SAS_ADAPTER *ioc) | |
3377 | { | |
f92363d1 | 3378 | int r; |
bb350661 | 3379 | int i, local_max_msix_vectors; |
f92363d1 | 3380 | u8 try_msix = 0; |
432bc7ca | 3381 | int iopoll_q_count = 0; |
f92363d1 | 3382 | |
eedc42a0 SR |
3383 | ioc->msix_load_balance = false; |
3384 | ||
f92363d1 SR |
3385 | if (msix_disable == -1 || msix_disable == 0) |
3386 | try_msix = 1; | |
3387 | ||
3388 | if (!try_msix) | |
3389 | goto try_ioapic; | |
3390 | ||
3391 | if (_base_check_enable_msix(ioc) != 0) | |
3392 | goto try_ioapic; | |
3393 | ||
18fd3d8c SP |
3394 | ioc_info(ioc, "MSI-X vectors supported: %d\n", ioc->msix_vector_count); |
3395 | pr_info("\t no of cores: %d, max_msix_vectors: %d\n", | |
3396 | ioc->cpu_count, max_msix_vectors); | |
432bc7ca | 3397 | |
18fd3d8c | 3398 | ioc->reply_queue_count = |
432bc7ca | 3399 | min_t(int, ioc->cpu_count, ioc->msix_vector_count); |
9c500060 | 3400 | |
9b05c91a | 3401 | if (!ioc->rdpq_array_enable && max_msix_vectors == -1) |
06f5f976 | 3402 | local_max_msix_vectors = (reset_devices) ? 1 : 8; |
bb350661 SPS |
3403 | else |
3404 | local_max_msix_vectors = max_msix_vectors; | |
9b05c91a | 3405 | |
432bc7ca | 3406 | if (local_max_msix_vectors == 0) |
9b05c91a | 3407 | goto try_ioapic; |
9c500060 | 3408 | |
eedc42a0 SR |
3409 | /* |
3410 | * Enable msix_load_balance only if combined reply queue mode is | |
3411 | * disabled on SAS3 & above generation HBA devices. | |
3412 | */ | |
3413 | if (!ioc->combined_reply_queue && | |
3414 | ioc->hba_mpi_version_belonged != MPI2_VERSION) { | |
5b061980 SR |
3415 | ioc_info(ioc, |
3416 | "combined ReplyQueue is off, Enabling msix load balance\n"); | |
eedc42a0 SR |
3417 | ioc->msix_load_balance = true; |
3418 | } | |
3419 | ||
3420 | /* | |
3421 | * smp affinity setting is not need when msix load balance | |
3422 | * is enabled. | |
3423 | */ | |
3424 | if (ioc->msix_load_balance) | |
610ef1e9 | 3425 | ioc->smp_affinity_enable = 0; |
64038301 | 3426 | |
432bc7ca SR |
3427 | if (!ioc->smp_affinity_enable || ioc->reply_queue_count <= 1) |
3428 | ioc->shost->host_tagset = 0; | |
3429 | ||
3430 | /* | |
3431 | * Enable io uring poll queues only if host_tagset is enabled. | |
3432 | */ | |
3433 | if (ioc->shost->host_tagset) | |
3434 | iopoll_q_count = poll_queues; | |
3435 | ||
3436 | if (iopoll_q_count) { | |
3437 | ioc->io_uring_poll_queues = kcalloc(iopoll_q_count, | |
3438 | sizeof(struct io_uring_poll_queue), GFP_KERNEL); | |
3439 | if (!ioc->io_uring_poll_queues) | |
3440 | iopoll_q_count = 0; | |
3441 | } | |
3442 | ||
3443 | if (ioc->is_aero_ioc) | |
3444 | _base_check_and_enable_high_iops_queues(ioc, | |
3445 | ioc->msix_vector_count); | |
3446 | ||
3447 | /* | |
3448 | * Add high iops queues count to reply queue count if high iops queues | |
3449 | * are enabled. | |
3450 | */ | |
3451 | ioc->reply_queue_count = min_t(int, | |
3452 | ioc->reply_queue_count + ioc->high_iops_queues, | |
3453 | ioc->msix_vector_count); | |
3454 | ||
3455 | /* | |
3456 | * Adjust the reply queue count incase reply queue count | |
3457 | * exceeds the user provided MSIx vectors count. | |
3458 | */ | |
3459 | if (local_max_msix_vectors > 0) | |
3460 | ioc->reply_queue_count = min_t(int, local_max_msix_vectors, | |
3461 | ioc->reply_queue_count); | |
3462 | /* | |
3463 | * Add io uring poll queues count to reply queues count | |
3464 | * if io uring is enabled in driver. | |
3465 | */ | |
3466 | if (iopoll_q_count) { | |
3467 | if (ioc->reply_queue_count < (iopoll_q_count + MPT3_MIN_IRQS)) | |
3468 | iopoll_q_count = 0; | |
3469 | ioc->reply_queue_count = min_t(int, | |
3470 | ioc->reply_queue_count + iopoll_q_count, | |
3471 | ioc->msix_vector_count); | |
3472 | } | |
3473 | ||
3474 | /* | |
3475 | * Starting index of io uring poll queues in reply queue list. | |
3476 | */ | |
3477 | ioc->iopoll_q_start_index = | |
3478 | ioc->reply_queue_count - iopoll_q_count; | |
3479 | ||
728bbc6c | 3480 | r = _base_alloc_irq_vectors(ioc); |
1d55abc0 | 3481 | if (r < 0) { |
5b061980 | 3482 | ioc_info(ioc, "pci_alloc_irq_vectors failed (r=%d) !!!\n", r); |
f92363d1 SR |
3483 | goto try_ioapic; |
3484 | } | |
3485 | ||
432bc7ca SR |
3486 | /* |
3487 | * Adjust the reply queue count if the allocated | |
3488 | * MSIx vectors is less then the requested number | |
3489 | * of MSIx vectors. | |
3490 | */ | |
3491 | if (r < ioc->iopoll_q_start_index) { | |
3492 | ioc->reply_queue_count = r + iopoll_q_count; | |
3493 | ioc->iopoll_q_start_index = | |
3494 | ioc->reply_queue_count - iopoll_q_count; | |
3495 | } | |
3496 | ||
f92363d1 | 3497 | ioc->msix_enable = 1; |
1d55abc0 HR |
3498 | for (i = 0; i < ioc->reply_queue_count; i++) { |
3499 | r = _base_request_irq(ioc, i); | |
f92363d1 | 3500 | if (r) { |
fae21608 SR |
3501 | mpt3sas_base_free_irq(ioc); |
3502 | mpt3sas_base_disable_msix(ioc); | |
f92363d1 SR |
3503 | goto try_ioapic; |
3504 | } | |
3505 | } | |
3506 | ||
18fd3d8c SP |
3507 | ioc_info(ioc, "High IOPs queues : %s\n", |
3508 | ioc->high_iops_queues ? "enabled" : "disabled"); | |
3509 | ||
f92363d1 SR |
3510 | return 0; |
3511 | ||
3512 | /* failback to io_apic interrupt routing */ | |
3513 | try_ioapic: | |
18fd3d8c SP |
3514 | ioc->high_iops_queues = 0; |
3515 | ioc_info(ioc, "High IOPs queues : disabled\n"); | |
9b05c91a | 3516 | ioc->reply_queue_count = 1; |
432bc7ca | 3517 | ioc->iopoll_q_start_index = ioc->reply_queue_count - 0; |
1d55abc0 HR |
3518 | r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY); |
3519 | if (r < 0) { | |
919d8a3f JP |
3520 | dfailprintk(ioc, |
3521 | ioc_info(ioc, "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n", | |
3522 | r)); | |
1d55abc0 HR |
3523 | } else |
3524 | r = _base_request_irq(ioc, 0); | |
f92363d1 SR |
3525 | |
3526 | return r; | |
3527 | } | |
3528 | ||
580d4e31 SR |
3529 | /** |
3530 | * mpt3sas_base_unmap_resources - free controller resources | |
3531 | * @ioc: per adapter object | |
3532 | */ | |
8bbb1cf6 | 3533 | static void |
580d4e31 SR |
3534 | mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc) |
3535 | { | |
3536 | struct pci_dev *pdev = ioc->pdev; | |
3537 | ||
1f95a47e | 3538 | dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); |
580d4e31 | 3539 | |
fae21608 SR |
3540 | mpt3sas_base_free_irq(ioc); |
3541 | mpt3sas_base_disable_msix(ioc); | |
580d4e31 | 3542 | |
2b48be65 C |
3543 | kfree(ioc->replyPostRegisterIndex); |
3544 | ioc->replyPostRegisterIndex = NULL; | |
3545 | ||
580d4e31 SR |
3546 | |
3547 | if (ioc->chip_phys) { | |
3548 | iounmap(ioc->chip); | |
3549 | ioc->chip_phys = 0; | |
3550 | } | |
3551 | ||
3552 | if (pci_is_enabled(pdev)) { | |
3553 | pci_release_selected_regions(ioc->pdev, ioc->bars); | |
580d4e31 SR |
3554 | pci_disable_device(pdev); |
3555 | } | |
3556 | } | |
3557 | ||
9c067c05 SP |
3558 | static int |
3559 | _base_diag_reset(struct MPT3SAS_ADAPTER *ioc); | |
3560 | ||
3561 | /** | |
19a622c3 | 3562 | * mpt3sas_base_check_for_fault_and_issue_reset - check if IOC is in fault state |
9c067c05 SP |
3563 | * and if it is in fault state then issue diag reset. |
3564 | * @ioc: per adapter object | |
3565 | * | |
2910a4a9 | 3566 | * Return: 0 for success, non-zero for failure. |
9c067c05 | 3567 | */ |
19a622c3 SP |
3568 | int |
3569 | mpt3sas_base_check_for_fault_and_issue_reset(struct MPT3SAS_ADAPTER *ioc) | |
9c067c05 SP |
3570 | { |
3571 | u32 ioc_state; | |
3572 | int rc = -EFAULT; | |
3573 | ||
3574 | dinitprintk(ioc, pr_info("%s\n", __func__)); | |
3575 | if (ioc->pci_error_recovery) | |
3576 | return 0; | |
3577 | ioc_state = mpt3sas_base_get_iocstate(ioc, 0); | |
3578 | dhsprintk(ioc, pr_info("%s: ioc_state(0x%08x)\n", __func__, ioc_state)); | |
3579 | ||
3580 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { | |
c5977718 | 3581 | mpt3sas_print_fault_code(ioc, ioc_state & |
9c067c05 | 3582 | MPI2_DOORBELL_DATA_MASK); |
19a622c3 | 3583 | mpt3sas_base_mask_interrupts(ioc); |
9c067c05 | 3584 | rc = _base_diag_reset(ioc); |
e8c2307e SR |
3585 | } else if ((ioc_state & MPI2_IOC_STATE_MASK) == |
3586 | MPI2_IOC_STATE_COREDUMP) { | |
c5977718 | 3587 | mpt3sas_print_coredump_info(ioc, ioc_state & |
e8c2307e SR |
3588 | MPI2_DOORBELL_DATA_MASK); |
3589 | mpt3sas_base_wait_for_coredump_completion(ioc, __func__); | |
19a622c3 | 3590 | mpt3sas_base_mask_interrupts(ioc); |
e8c2307e | 3591 | rc = _base_diag_reset(ioc); |
9c067c05 SP |
3592 | } |
3593 | ||
3594 | return rc; | |
3595 | } | |
3596 | ||
f92363d1 SR |
3597 | /** |
3598 | * mpt3sas_base_map_resources - map in controller resources (io/irq/memap) | |
3599 | * @ioc: per adapter object | |
3600 | * | |
4beb4867 | 3601 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
3602 | */ |
3603 | int | |
3604 | mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc) | |
3605 | { | |
3606 | struct pci_dev *pdev = ioc->pdev; | |
3607 | u32 memap_sz; | |
3608 | u32 pio_sz; | |
9c067c05 | 3609 | int i, r = 0, rc; |
f92363d1 | 3610 | u64 pio_chip = 0; |
6f9e09fd | 3611 | phys_addr_t chip_phys = 0; |
f92363d1 | 3612 | struct adapter_reply_queue *reply_q; |
432bc7ca | 3613 | int iopoll_q_count = 0; |
f92363d1 | 3614 | |
919d8a3f | 3615 | dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); |
f92363d1 SR |
3616 | |
3617 | ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
3618 | if (pci_enable_device_mem(pdev)) { | |
919d8a3f | 3619 | ioc_warn(ioc, "pci_enable_device_mem: failed\n"); |
cf9bd21a | 3620 | ioc->bars = 0; |
f92363d1 SR |
3621 | return -ENODEV; |
3622 | } | |
3623 | ||
3624 | ||
3625 | if (pci_request_selected_regions(pdev, ioc->bars, | |
c84b06a4 | 3626 | ioc->driver_name)) { |
919d8a3f | 3627 | ioc_warn(ioc, "pci_request_selected_regions: failed\n"); |
cf9bd21a | 3628 | ioc->bars = 0; |
f92363d1 SR |
3629 | r = -ENODEV; |
3630 | goto out_fail; | |
3631 | } | |
3632 | ||
f92363d1 SR |
3633 | pci_set_master(pdev); |
3634 | ||
3635 | ||
3636 | if (_base_config_dma_addressing(ioc, pdev) != 0) { | |
919d8a3f | 3637 | ioc_warn(ioc, "no suitable DMA mask for %s\n", pci_name(pdev)); |
f92363d1 SR |
3638 | r = -ENODEV; |
3639 | goto out_fail; | |
3640 | } | |
3641 | ||
5aeeb78a SR |
3642 | for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) && |
3643 | (!memap_sz || !pio_sz); i++) { | |
f92363d1 SR |
3644 | if (pci_resource_flags(pdev, i) & IORESOURCE_IO) { |
3645 | if (pio_sz) | |
3646 | continue; | |
3647 | pio_chip = (u64)pci_resource_start(pdev, i); | |
3648 | pio_sz = pci_resource_len(pdev, i); | |
3649 | } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { | |
3650 | if (memap_sz) | |
3651 | continue; | |
3652 | ioc->chip_phys = pci_resource_start(pdev, i); | |
6f9e09fd | 3653 | chip_phys = ioc->chip_phys; |
f92363d1 SR |
3654 | memap_sz = pci_resource_len(pdev, i); |
3655 | ioc->chip = ioremap(ioc->chip_phys, memap_sz); | |
f92363d1 SR |
3656 | } |
3657 | } | |
3658 | ||
5aeeb78a | 3659 | if (ioc->chip == NULL) { |
5b061980 SR |
3660 | ioc_err(ioc, |
3661 | "unable to map adapter memory! or resource not found\n"); | |
5aeeb78a SR |
3662 | r = -EINVAL; |
3663 | goto out_fail; | |
3664 | } | |
3665 | ||
5afa9d44 | 3666 | mpt3sas_base_mask_interrupts(ioc); |
9b05c91a | 3667 | |
98c56ad3 | 3668 | r = _base_get_ioc_facts(ioc); |
9c067c05 | 3669 | if (r) { |
19a622c3 | 3670 | rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc); |
9c067c05 SP |
3671 | if (rc || (_base_get_ioc_facts(ioc))) |
3672 | goto out_fail; | |
3673 | } | |
9b05c91a SR |
3674 | |
3675 | if (!ioc->rdpq_array_enable_assigned) { | |
3676 | ioc->rdpq_array_enable = ioc->rdpq_array_capable; | |
3677 | ioc->rdpq_array_enable_assigned = 1; | |
3678 | } | |
3679 | ||
f92363d1 SR |
3680 | r = _base_enable_msix(ioc); |
3681 | if (r) | |
3682 | goto out_fail; | |
3683 | ||
432bc7ca SR |
3684 | iopoll_q_count = ioc->reply_queue_count - ioc->iopoll_q_start_index; |
3685 | for (i = 0; i < iopoll_q_count; i++) { | |
3686 | atomic_set(&ioc->io_uring_poll_queues[i].busy, 0); | |
3687 | atomic_set(&ioc->io_uring_poll_queues[i].pause, 0); | |
3688 | } | |
3689 | ||
320e77ac SP |
3690 | if (!ioc->is_driver_loading) |
3691 | _base_init_irqpolls(ioc); | |
fb77bb53 SR |
3692 | /* Use the Combined reply queue feature only for SAS3 C0 & higher |
3693 | * revision HBAs and also only when reply queue count is greater than 8 | |
3694 | */ | |
2b48be65 | 3695 | if (ioc->combined_reply_queue) { |
fb77bb53 SR |
3696 | /* Determine the Supplemental Reply Post Host Index Registers |
3697 | * Addresse. Supplemental Reply Post Host Index Registers | |
3698 | * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and | |
3699 | * each register is at offset bytes of | |
3700 | * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one. | |
3701 | */ | |
3702 | ioc->replyPostRegisterIndex = kcalloc( | |
0bb337c9 | 3703 | ioc->combined_reply_index_count, |
fb77bb53 SR |
3704 | sizeof(resource_size_t *), GFP_KERNEL); |
3705 | if (!ioc->replyPostRegisterIndex) { | |
5b061980 SR |
3706 | ioc_err(ioc, |
3707 | "allocation for replyPostRegisterIndex failed!\n"); | |
fb77bb53 SR |
3708 | r = -ENOMEM; |
3709 | goto out_fail; | |
3710 | } | |
3711 | ||
0bb337c9 | 3712 | for (i = 0; i < ioc->combined_reply_index_count; i++) { |
fe413ab3 DLM |
3713 | ioc->replyPostRegisterIndex[i] = |
3714 | (resource_size_t __iomem *) | |
3715 | ((u8 __force *)&ioc->chip->Doorbell + | |
3716 | MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET + | |
3717 | (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET)); | |
fb77bb53 | 3718 | } |
2b48be65 | 3719 | } |
fb77bb53 | 3720 | |
ce7c6c9e GE |
3721 | if (ioc->is_warpdrive) { |
3722 | ioc->reply_post_host_index[0] = (resource_size_t __iomem *) | |
3723 | &ioc->chip->ReplyPostHostIndex; | |
3724 | ||
3725 | for (i = 1; i < ioc->cpu_msix_table_sz; i++) | |
3726 | ioc->reply_post_host_index[i] = | |
3727 | (resource_size_t __iomem *) | |
3728 | ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1) | |
3729 | * 4))); | |
3730 | } | |
3731 | ||
432bc7ca SR |
3732 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { |
3733 | if (reply_q->msix_index >= ioc->iopoll_q_start_index) { | |
3734 | pr_info("%s: enabled: index: %d\n", | |
3735 | reply_q->name, reply_q->msix_index); | |
3736 | continue; | |
3737 | } | |
3738 | ||
fc7d510e JP |
3739 | pr_info("%s: %s enabled: IRQ %d\n", |
3740 | reply_q->name, | |
3741 | ioc->msix_enable ? "PCI-MSI-X" : "IO-APIC", | |
3742 | pci_irq_vector(ioc->pdev, reply_q->msix_index)); | |
432bc7ca | 3743 | } |
f92363d1 | 3744 | |
919d8a3f JP |
3745 | ioc_info(ioc, "iomem(%pap), mapped(0x%p), size(%d)\n", |
3746 | &chip_phys, ioc->chip, memap_sz); | |
3747 | ioc_info(ioc, "ioport(0x%016llx), size(%d)\n", | |
3748 | (unsigned long long)pio_chip, pio_sz); | |
f92363d1 SR |
3749 | |
3750 | /* Save PCI configuration state for recovery from PCI AER/EEH errors */ | |
3751 | pci_save_state(pdev); | |
3752 | return 0; | |
3753 | ||
3754 | out_fail: | |
580d4e31 | 3755 | mpt3sas_base_unmap_resources(ioc); |
f92363d1 SR |
3756 | return r; |
3757 | } | |
3758 | ||
3759 | /** | |
3760 | * mpt3sas_base_get_msg_frame - obtain request mf pointer | |
3761 | * @ioc: per adapter object | |
3762 | * @smid: system request message index(smid zero is invalid) | |
3763 | * | |
4beb4867 | 3764 | * Return: virt pointer to message frame. |
f92363d1 SR |
3765 | */ |
3766 | void * | |
3767 | mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
3768 | { | |
3769 | return (void *)(ioc->request + (smid * ioc->request_sz)); | |
3770 | } | |
3771 | ||
3772 | /** | |
3773 | * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr | |
3774 | * @ioc: per adapter object | |
3775 | * @smid: system request message index | |
3776 | * | |
4beb4867 | 3777 | * Return: virt pointer to sense buffer. |
f92363d1 SR |
3778 | */ |
3779 | void * | |
3780 | mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
3781 | { | |
3782 | return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE)); | |
3783 | } | |
3784 | ||
3785 | /** | |
3786 | * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr | |
3787 | * @ioc: per adapter object | |
3788 | * @smid: system request message index | |
3789 | * | |
4beb4867 | 3790 | * Return: phys pointer to the low 32bit address of the sense buffer. |
f92363d1 SR |
3791 | */ |
3792 | __le32 | |
3793 | mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
3794 | { | |
3795 | return cpu_to_le32(ioc->sense_dma + ((smid - 1) * | |
3796 | SCSI_SENSE_BUFFERSIZE)); | |
3797 | } | |
3798 | ||
016d5c35 SPS |
3799 | /** |
3800 | * mpt3sas_base_get_pcie_sgl - obtain a PCIe SGL virt addr | |
3801 | * @ioc: per adapter object | |
3802 | * @smid: system request message index | |
3803 | * | |
4beb4867 | 3804 | * Return: virt pointer to a PCIe SGL. |
016d5c35 SPS |
3805 | */ |
3806 | void * | |
3807 | mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
3808 | { | |
dbec4c90 | 3809 | return (void *)(ioc->pcie_sg_lookup[smid - 1].pcie_sgl); |
016d5c35 SPS |
3810 | } |
3811 | ||
3812 | /** | |
3813 | * mpt3sas_base_get_pcie_sgl_dma - obtain a PCIe SGL dma addr | |
3814 | * @ioc: per adapter object | |
3815 | * @smid: system request message index | |
3816 | * | |
4beb4867 | 3817 | * Return: phys pointer to the address of the PCIe buffer. |
016d5c35 | 3818 | */ |
d8335ae2 | 3819 | dma_addr_t |
016d5c35 SPS |
3820 | mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid) |
3821 | { | |
dbec4c90 | 3822 | return ioc->pcie_sg_lookup[smid - 1].pcie_sgl_dma; |
016d5c35 SPS |
3823 | } |
3824 | ||
f92363d1 SR |
3825 | /** |
3826 | * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address | |
3827 | * @ioc: per adapter object | |
3828 | * @phys_addr: lower 32 physical addr of the reply | |
3829 | * | |
3830 | * Converts 32bit lower physical addr into a virt address. | |
3831 | */ | |
3832 | void * | |
3833 | mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr) | |
3834 | { | |
3835 | if (!phys_addr) | |
3836 | return NULL; | |
3837 | return ioc->reply + (phys_addr - (u32)ioc->reply_dma); | |
3838 | } | |
3839 | ||
02136516 SP |
3840 | /** |
3841 | * _base_get_msix_index - get the msix index | |
3842 | * @ioc: per adapter object | |
3843 | * @scmd: scsi_cmnd object | |
3844 | * | |
2910a4a9 | 3845 | * Return: msix index of general reply queues, |
02136516 SP |
3846 | * i.e. reply queue on which IO request's reply |
3847 | * should be posted by the HBA firmware. | |
3848 | */ | |
03d1fb3a | 3849 | static inline u8 |
02136516 SP |
3850 | _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc, |
3851 | struct scsi_cmnd *scmd) | |
03d1fb3a | 3852 | { |
51e3b2ad SP |
3853 | /* Enables reply_queue load balancing */ |
3854 | if (ioc->msix_load_balance) | |
3855 | return ioc->reply_queue_count ? | |
3856 | base_mod64(atomic64_add_return(1, | |
3857 | &ioc->total_io_cnt), ioc->reply_queue_count) : 0; | |
3858 | ||
664f0dce | 3859 | if (scmd && ioc->shost->nr_hw_queues > 1) { |
24b3c922 | 3860 | u32 tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd)); |
03d1fb3a | 3861 | |
664f0dce SR |
3862 | return blk_mq_unique_tag_to_hwq(tag) + |
3863 | ioc->high_iops_queues; | |
3864 | } | |
c50ed99c | 3865 | |
664f0dce | 3866 | return ioc->cpu_msix_table[raw_smp_processor_id()]; |
c50ed99c SR |
3867 | } |
3868 | ||
5dd48a55 SP |
3869 | /** |
3870 | * _base_get_high_iops_msix_index - get the msix index of | |
3871 | * high iops queues | |
3872 | * @ioc: per adapter object | |
3873 | * @scmd: scsi_cmnd object | |
3874 | * | |
2910a4a9 | 3875 | * Return: msix index of high iops reply queues. |
5dd48a55 SP |
3876 | * i.e. high iops reply queue on which IO request's |
3877 | * reply should be posted by the HBA firmware. | |
3878 | */ | |
3879 | static inline u8 | |
3880 | _base_get_high_iops_msix_index(struct MPT3SAS_ADAPTER *ioc, | |
3881 | struct scsi_cmnd *scmd) | |
3882 | { | |
3883 | /** | |
3884 | * Round robin the IO interrupts among the high iops | |
3885 | * reply queues in terms of batch count 16 when outstanding | |
3886 | * IOs on the target device is >=8. | |
3887 | */ | |
664f0dce | 3888 | |
020b0f0a | 3889 | if (scsi_device_busy(scmd->device) > MPT3SAS_DEVICE_HIGH_IOPS_DEPTH) |
5dd48a55 SP |
3890 | return base_mod64(( |
3891 | atomic64_add_return(1, &ioc->high_iops_outstanding) / | |
3892 | MPT3SAS_HIGH_IOPS_BATCH_COUNT), | |
3893 | MPT3SAS_HIGH_IOPS_REPLY_QUEUES); | |
3894 | ||
3895 | return _base_get_msix_index(ioc, scmd); | |
3896 | } | |
3897 | ||
f92363d1 SR |
3898 | /** |
3899 | * mpt3sas_base_get_smid - obtain a free smid from internal queue | |
3900 | * @ioc: per adapter object | |
3901 | * @cb_idx: callback index | |
3902 | * | |
4beb4867 | 3903 | * Return: smid (zero is invalid) |
f92363d1 SR |
3904 | */ |
3905 | u16 | |
3906 | mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) | |
3907 | { | |
3908 | unsigned long flags; | |
3909 | struct request_tracker *request; | |
3910 | u16 smid; | |
3911 | ||
3912 | spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); | |
3913 | if (list_empty(&ioc->internal_free_list)) { | |
3914 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
919d8a3f | 3915 | ioc_err(ioc, "%s: smid not available\n", __func__); |
f92363d1 SR |
3916 | return 0; |
3917 | } | |
3918 | ||
3919 | request = list_entry(ioc->internal_free_list.next, | |
3920 | struct request_tracker, tracker_list); | |
3921 | request->cb_idx = cb_idx; | |
3922 | smid = request->smid; | |
3923 | list_del(&request->tracker_list); | |
3924 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
3925 | return smid; | |
3926 | } | |
3927 | ||
3928 | /** | |
3929 | * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue | |
3930 | * @ioc: per adapter object | |
3931 | * @cb_idx: callback index | |
3932 | * @scmd: pointer to scsi command object | |
3933 | * | |
4beb4867 | 3934 | * Return: smid (zero is invalid) |
f92363d1 SR |
3935 | */ |
3936 | u16 | |
3937 | mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx, | |
3938 | struct scsi_cmnd *scmd) | |
3939 | { | |
dbec4c90 | 3940 | struct scsiio_tracker *request = scsi_cmd_priv(scmd); |
f92363d1 | 3941 | u16 smid; |
664f0dce SR |
3942 | u32 tag, unique_tag; |
3943 | ||
24b3c922 | 3944 | unique_tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd)); |
664f0dce SR |
3945 | tag = blk_mq_unique_tag_to_tag(unique_tag); |
3946 | ||
3947 | /* | |
3948 | * Store hw queue number corresponding to the tag. | |
3949 | * This hw queue number is used later to determine | |
3950 | * the unique_tag using the logic below. This unique_tag | |
3951 | * is used to retrieve the scmd pointer corresponding | |
3952 | * to tag using scsi_host_find_tag() API. | |
3953 | * | |
3954 | * tag = smid - 1; | |
3955 | * unique_tag = ioc->io_queue_num[tag] << BLK_MQ_UNIQUE_TAG_BITS | tag; | |
3956 | */ | |
3957 | ioc->io_queue_num[tag] = blk_mq_unique_tag_to_hwq(unique_tag); | |
f92363d1 | 3958 | |
dbec4c90 | 3959 | smid = tag + 1; |
f92363d1 | 3960 | request->cb_idx = cb_idx; |
dbec4c90 | 3961 | request->smid = smid; |
998c3001 | 3962 | request->scmd = scmd; |
dbec4c90 | 3963 | INIT_LIST_HEAD(&request->chain_list); |
f92363d1 SR |
3964 | return smid; |
3965 | } | |
3966 | ||
3967 | /** | |
3968 | * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue | |
3969 | * @ioc: per adapter object | |
3970 | * @cb_idx: callback index | |
3971 | * | |
4beb4867 | 3972 | * Return: smid (zero is invalid) |
f92363d1 SR |
3973 | */ |
3974 | u16 | |
3975 | mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) | |
3976 | { | |
3977 | unsigned long flags; | |
3978 | struct request_tracker *request; | |
3979 | u16 smid; | |
3980 | ||
3981 | spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); | |
3982 | if (list_empty(&ioc->hpr_free_list)) { | |
3983 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
3984 | return 0; | |
3985 | } | |
3986 | ||
3987 | request = list_entry(ioc->hpr_free_list.next, | |
3988 | struct request_tracker, tracker_list); | |
3989 | request->cb_idx = cb_idx; | |
3990 | smid = request->smid; | |
3991 | list_del(&request->tracker_list); | |
3992 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
3993 | return smid; | |
3994 | } | |
3995 | ||
6a2d4618 HR |
3996 | static void |
3997 | _base_recovery_check(struct MPT3SAS_ADAPTER *ioc) | |
3998 | { | |
3999 | /* | |
4000 | * See _wait_for_commands_to_complete() call with regards to this code. | |
4001 | */ | |
4002 | if (ioc->shost_recovery && ioc->pending_io_count) { | |
c84b023a | 4003 | ioc->pending_io_count = scsi_host_busy(ioc->shost); |
272e253c | 4004 | if (ioc->pending_io_count == 0) |
6a2d4618 | 4005 | wake_up(&ioc->reset_wq); |
6a2d4618 HR |
4006 | } |
4007 | } | |
4008 | ||
dbec4c90 SPS |
4009 | void mpt3sas_base_clear_st(struct MPT3SAS_ADAPTER *ioc, |
4010 | struct scsiio_tracker *st) | |
4011 | { | |
4012 | if (WARN_ON(st->smid == 0)) | |
4013 | return; | |
4014 | st->cb_idx = 0xFF; | |
4015 | st->direct_io = 0; | |
998c3001 | 4016 | st->scmd = NULL; |
93204b78 | 4017 | atomic_set(&ioc->chain_lookup[st->smid - 1].chain_offset, 0); |
e7018314 | 4018 | st->smid = 0; |
dbec4c90 SPS |
4019 | } |
4020 | ||
f92363d1 SR |
4021 | /** |
4022 | * mpt3sas_base_free_smid - put smid back on free_list | |
4023 | * @ioc: per adapter object | |
4024 | * @smid: system request message index | |
f92363d1 SR |
4025 | */ |
4026 | void | |
4027 | mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
4028 | { | |
4029 | unsigned long flags; | |
4030 | int i; | |
f92363d1 | 4031 | |
f92363d1 | 4032 | if (smid < ioc->hi_priority_smid) { |
dbec4c90 | 4033 | struct scsiio_tracker *st; |
c2fe742f | 4034 | void *request; |
f92363d1 | 4035 | |
dbec4c90 SPS |
4036 | st = _get_st_from_smid(ioc, smid); |
4037 | if (!st) { | |
4038 | _base_recovery_check(ioc); | |
4039 | return; | |
4040 | } | |
c2fe742f SR |
4041 | |
4042 | /* Clear MPI request frame */ | |
4043 | request = mpt3sas_base_get_msg_frame(ioc, smid); | |
4044 | memset(request, 0, ioc->request_sz); | |
4045 | ||
dbec4c90 | 4046 | mpt3sas_base_clear_st(ioc, st); |
6a2d4618 | 4047 | _base_recovery_check(ioc); |
664f0dce | 4048 | ioc->io_queue_num[smid - 1] = 0; |
f92363d1 | 4049 | return; |
dbec4c90 SPS |
4050 | } |
4051 | ||
4052 | spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); | |
4053 | if (smid < ioc->internal_smid) { | |
f92363d1 SR |
4054 | /* hi-priority */ |
4055 | i = smid - ioc->hi_priority_smid; | |
4056 | ioc->hpr_lookup[i].cb_idx = 0xFF; | |
4057 | list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list); | |
4058 | } else if (smid <= ioc->hba_queue_depth) { | |
4059 | /* internal queue */ | |
4060 | i = smid - ioc->internal_smid; | |
4061 | ioc->internal_lookup[i].cb_idx = 0xFF; | |
4062 | list_add(&ioc->internal_lookup[i].tracker_list, | |
4063 | &ioc->internal_free_list); | |
4064 | } | |
4065 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); | |
4066 | } | |
4067 | ||
e5747439 SPS |
4068 | /** |
4069 | * _base_mpi_ep_writeq - 32 bit write to MMIO | |
4070 | * @b: data payload | |
4071 | * @addr: address in MMIO space | |
4072 | * @writeq_lock: spin lock | |
4073 | * | |
4074 | * This special handling for MPI EP to take care of 32 bit | |
4075 | * environment where its not quarenteed to send the entire word | |
4076 | * in one transfer. | |
4077 | */ | |
4078 | static inline void | |
4079 | _base_mpi_ep_writeq(__u64 b, volatile void __iomem *addr, | |
4080 | spinlock_t *writeq_lock) | |
4081 | { | |
4082 | unsigned long flags; | |
e5747439 SPS |
4083 | |
4084 | spin_lock_irqsave(writeq_lock, flags); | |
09c2f95a SR |
4085 | __raw_writel((u32)(b), addr); |
4086 | __raw_writel((u32)(b >> 32), (addr + 4)); | |
e5747439 SPS |
4087 | spin_unlock_irqrestore(writeq_lock, flags); |
4088 | } | |
4089 | ||
f92363d1 SR |
4090 | /** |
4091 | * _base_writeq - 64 bit write to MMIO | |
f92363d1 SR |
4092 | * @b: data payload |
4093 | * @addr: address in MMIO space | |
4094 | * @writeq_lock: spin lock | |
4095 | * | |
4096 | * Glue for handling an atomic 64 bit word to MMIO. This special handling takes | |
4097 | * care of 32 bit environment where its not quarenteed to send the entire word | |
4098 | * in one transfer. | |
4099 | */ | |
4100 | #if defined(writeq) && defined(CONFIG_64BIT) | |
4101 | static inline void | |
4102 | _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) | |
4103 | { | |
23c3828a | 4104 | wmb(); |
09c2f95a | 4105 | __raw_writeq(b, addr); |
23c3828a | 4106 | barrier(); |
f92363d1 SR |
4107 | } |
4108 | #else | |
4109 | static inline void | |
4110 | _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) | |
4111 | { | |
e5747439 | 4112 | _base_mpi_ep_writeq(b, addr, writeq_lock); |
f92363d1 SR |
4113 | } |
4114 | #endif | |
4115 | ||
998c3001 SP |
4116 | /** |
4117 | * _base_set_and_get_msix_index - get the msix index and assign to msix_io | |
4118 | * variable of scsi tracker | |
4119 | * @ioc: per adapter object | |
4120 | * @smid: system request message index | |
4121 | * | |
2910a4a9 | 4122 | * Return: msix index. |
998c3001 SP |
4123 | */ |
4124 | static u8 | |
4125 | _base_set_and_get_msix_index(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
4126 | { | |
4127 | struct scsiio_tracker *st = NULL; | |
4128 | ||
4129 | if (smid < ioc->hi_priority_smid) | |
4130 | st = _get_st_from_smid(ioc, smid); | |
4131 | ||
4132 | if (st == NULL) | |
4133 | return _base_get_msix_index(ioc, NULL); | |
4134 | ||
4135 | st->msix_io = ioc->get_msix_index_for_smlio(ioc, st->scmd); | |
4136 | return st->msix_io; | |
4137 | } | |
4138 | ||
e5747439 SPS |
4139 | /** |
4140 | * _base_put_smid_mpi_ep_scsi_io - send SCSI_IO request to firmware | |
4141 | * @ioc: per adapter object | |
4142 | * @smid: system request message index | |
4143 | * @handle: device handle | |
e5747439 SPS |
4144 | */ |
4145 | static void | |
078a4cc1 SP |
4146 | _base_put_smid_mpi_ep_scsi_io(struct MPT3SAS_ADAPTER *ioc, |
4147 | u16 smid, u16 handle) | |
e5747439 SPS |
4148 | { |
4149 | Mpi2RequestDescriptorUnion_t descriptor; | |
4150 | u64 *request = (u64 *)&descriptor; | |
4151 | void *mpi_req_iomem; | |
4152 | __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid); | |
4153 | ||
4154 | _clone_sg_entries(ioc, (void *) mfp, smid); | |
cf6bf971 | 4155 | mpi_req_iomem = (void __force *)ioc->chip + |
e5747439 SPS |
4156 | MPI_FRAME_START_OFFSET + (smid * ioc->request_sz); |
4157 | _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp, | |
4158 | ioc->request_sz); | |
4159 | descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; | |
998c3001 | 4160 | descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); |
e5747439 SPS |
4161 | descriptor.SCSIIO.SMID = cpu_to_le16(smid); |
4162 | descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); | |
4163 | descriptor.SCSIIO.LMID = 0; | |
4164 | _base_mpi_ep_writeq(*request, &ioc->chip->RequestDescriptorPostLow, | |
4165 | &ioc->scsi_lookup_lock); | |
4166 | } | |
4167 | ||
f92363d1 | 4168 | /** |
81c16f83 | 4169 | * _base_put_smid_scsi_io - send SCSI_IO request to firmware |
f92363d1 SR |
4170 | * @ioc: per adapter object |
4171 | * @smid: system request message index | |
4172 | * @handle: device handle | |
f92363d1 | 4173 | */ |
81c16f83 SPS |
4174 | static void |
4175 | _base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle) | |
f92363d1 SR |
4176 | { |
4177 | Mpi2RequestDescriptorUnion_t descriptor; | |
4178 | u64 *request = (u64 *)&descriptor; | |
4179 | ||
4180 | ||
4181 | descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; | |
998c3001 | 4182 | descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); |
f92363d1 SR |
4183 | descriptor.SCSIIO.SMID = cpu_to_le16(smid); |
4184 | descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); | |
4185 | descriptor.SCSIIO.LMID = 0; | |
4186 | _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, | |
4187 | &ioc->scsi_lookup_lock); | |
4188 | } | |
4189 | ||
4190 | /** | |
078a4cc1 | 4191 | * _base_put_smid_fast_path - send fast path request to firmware |
f92363d1 SR |
4192 | * @ioc: per adapter object |
4193 | * @smid: system request message index | |
4194 | * @handle: device handle | |
f92363d1 | 4195 | */ |
078a4cc1 SP |
4196 | static void |
4197 | _base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid, | |
f92363d1 SR |
4198 | u16 handle) |
4199 | { | |
4200 | Mpi2RequestDescriptorUnion_t descriptor; | |
4201 | u64 *request = (u64 *)&descriptor; | |
4202 | ||
4203 | descriptor.SCSIIO.RequestFlags = | |
4204 | MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; | |
998c3001 | 4205 | descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); |
f92363d1 SR |
4206 | descriptor.SCSIIO.SMID = cpu_to_le16(smid); |
4207 | descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); | |
4208 | descriptor.SCSIIO.LMID = 0; | |
4209 | _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, | |
4210 | &ioc->scsi_lookup_lock); | |
4211 | } | |
4212 | ||
4213 | /** | |
078a4cc1 | 4214 | * _base_put_smid_hi_priority - send Task Management request to firmware |
f92363d1 SR |
4215 | * @ioc: per adapter object |
4216 | * @smid: system request message index | |
2910a4a9 | 4217 | * @msix_task: msix_task will be same as msix of IO in case of task abort else 0 |
f92363d1 | 4218 | */ |
078a4cc1 SP |
4219 | static void |
4220 | _base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid, | |
03d1fb3a | 4221 | u16 msix_task) |
f92363d1 SR |
4222 | { |
4223 | Mpi2RequestDescriptorUnion_t descriptor; | |
e5747439 SPS |
4224 | void *mpi_req_iomem; |
4225 | u64 *request; | |
4226 | ||
4227 | if (ioc->is_mcpu_endpoint) { | |
e5747439 SPS |
4228 | __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid); |
4229 | ||
e5747439 | 4230 | /* TBD 256 is offset within sys register. */ |
cf6bf971 C |
4231 | mpi_req_iomem = (void __force *)ioc->chip |
4232 | + MPI_FRAME_START_OFFSET | |
e5747439 SPS |
4233 | + (smid * ioc->request_sz); |
4234 | _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp, | |
4235 | ioc->request_sz); | |
4236 | } | |
4237 | ||
4238 | request = (u64 *)&descriptor; | |
f92363d1 SR |
4239 | |
4240 | descriptor.HighPriority.RequestFlags = | |
4241 | MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; | |
03d1fb3a | 4242 | descriptor.HighPriority.MSIxIndex = msix_task; |
f92363d1 SR |
4243 | descriptor.HighPriority.SMID = cpu_to_le16(smid); |
4244 | descriptor.HighPriority.LMID = 0; | |
4245 | descriptor.HighPriority.Reserved1 = 0; | |
e5747439 SPS |
4246 | if (ioc->is_mcpu_endpoint) |
4247 | _base_mpi_ep_writeq(*request, | |
4248 | &ioc->chip->RequestDescriptorPostLow, | |
4249 | &ioc->scsi_lookup_lock); | |
4250 | else | |
4251 | _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, | |
4252 | &ioc->scsi_lookup_lock); | |
f92363d1 SR |
4253 | } |
4254 | ||
aff39e61 | 4255 | /** |
40114bde | 4256 | * mpt3sas_base_put_smid_nvme_encap - send NVMe encapsulated request to |
aff39e61 SPS |
4257 | * firmware |
4258 | * @ioc: per adapter object | |
4259 | * @smid: system request message index | |
aff39e61 | 4260 | */ |
40114bde SP |
4261 | void |
4262 | mpt3sas_base_put_smid_nvme_encap(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
aff39e61 SPS |
4263 | { |
4264 | Mpi2RequestDescriptorUnion_t descriptor; | |
4265 | u64 *request = (u64 *)&descriptor; | |
4266 | ||
4267 | descriptor.Default.RequestFlags = | |
4268 | MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED; | |
998c3001 | 4269 | descriptor.Default.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); |
aff39e61 SPS |
4270 | descriptor.Default.SMID = cpu_to_le16(smid); |
4271 | descriptor.Default.LMID = 0; | |
4272 | descriptor.Default.DescriptorTypeDependent = 0; | |
4273 | _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, | |
4274 | &ioc->scsi_lookup_lock); | |
4275 | } | |
4276 | ||
f92363d1 | 4277 | /** |
078a4cc1 | 4278 | * _base_put_smid_default - Default, primarily used for config pages |
f92363d1 SR |
4279 | * @ioc: per adapter object |
4280 | * @smid: system request message index | |
f92363d1 | 4281 | */ |
078a4cc1 SP |
4282 | static void |
4283 | _base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
f92363d1 SR |
4284 | { |
4285 | Mpi2RequestDescriptorUnion_t descriptor; | |
e5747439 SPS |
4286 | void *mpi_req_iomem; |
4287 | u64 *request; | |
e5747439 SPS |
4288 | |
4289 | if (ioc->is_mcpu_endpoint) { | |
4290 | __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid); | |
4291 | ||
e5747439 SPS |
4292 | _clone_sg_entries(ioc, (void *) mfp, smid); |
4293 | /* TBD 256 is offset within sys register */ | |
cf6bf971 | 4294 | mpi_req_iomem = (void __force *)ioc->chip + |
e5747439 SPS |
4295 | MPI_FRAME_START_OFFSET + (smid * ioc->request_sz); |
4296 | _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp, | |
4297 | ioc->request_sz); | |
4298 | } | |
4299 | request = (u64 *)&descriptor; | |
f92363d1 | 4300 | descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; |
998c3001 | 4301 | descriptor.Default.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); |
f92363d1 SR |
4302 | descriptor.Default.SMID = cpu_to_le16(smid); |
4303 | descriptor.Default.LMID = 0; | |
4304 | descriptor.Default.DescriptorTypeDependent = 0; | |
e5747439 SPS |
4305 | if (ioc->is_mcpu_endpoint) |
4306 | _base_mpi_ep_writeq(*request, | |
4307 | &ioc->chip->RequestDescriptorPostLow, | |
4308 | &ioc->scsi_lookup_lock); | |
4309 | else | |
4310 | _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, | |
4311 | &ioc->scsi_lookup_lock); | |
f92363d1 SR |
4312 | } |
4313 | ||
79c74d03 SP |
4314 | /** |
4315 | * _base_put_smid_scsi_io_atomic - send SCSI_IO request to firmware using | |
4316 | * Atomic Request Descriptor | |
4317 | * @ioc: per adapter object | |
4318 | * @smid: system request message index | |
4319 | * @handle: device handle, unused in this function, for function type match | |
4320 | * | |
2910a4a9 | 4321 | * Return: nothing. |
79c74d03 SP |
4322 | */ |
4323 | static void | |
4324 | _base_put_smid_scsi_io_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, | |
4325 | u16 handle) | |
4326 | { | |
4327 | Mpi26AtomicRequestDescriptor_t descriptor; | |
4328 | u32 *request = (u32 *)&descriptor; | |
4329 | ||
4330 | descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; | |
998c3001 | 4331 | descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); |
79c74d03 SP |
4332 | descriptor.SMID = cpu_to_le16(smid); |
4333 | ||
f920642e | 4334 | writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); |
79c74d03 SP |
4335 | } |
4336 | ||
4337 | /** | |
4338 | * _base_put_smid_fast_path_atomic - send fast path request to firmware | |
4339 | * using Atomic Request Descriptor | |
4340 | * @ioc: per adapter object | |
4341 | * @smid: system request message index | |
4342 | * @handle: device handle, unused in this function, for function type match | |
2910a4a9 | 4343 | * Return: nothing |
79c74d03 SP |
4344 | */ |
4345 | static void | |
4346 | _base_put_smid_fast_path_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, | |
4347 | u16 handle) | |
4348 | { | |
4349 | Mpi26AtomicRequestDescriptor_t descriptor; | |
4350 | u32 *request = (u32 *)&descriptor; | |
4351 | ||
4352 | descriptor.RequestFlags = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; | |
998c3001 | 4353 | descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); |
79c74d03 SP |
4354 | descriptor.SMID = cpu_to_le16(smid); |
4355 | ||
f920642e | 4356 | writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); |
79c74d03 SP |
4357 | } |
4358 | ||
4359 | /** | |
4360 | * _base_put_smid_hi_priority_atomic - send Task Management request to | |
4361 | * firmware using Atomic Request Descriptor | |
4362 | * @ioc: per adapter object | |
4363 | * @smid: system request message index | |
2910a4a9 | 4364 | * @msix_task: msix_task will be same as msix of IO in case of task abort else 0 |
79c74d03 | 4365 | * |
2910a4a9 | 4366 | * Return: nothing. |
79c74d03 SP |
4367 | */ |
4368 | static void | |
4369 | _base_put_smid_hi_priority_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid, | |
4370 | u16 msix_task) | |
4371 | { | |
4372 | Mpi26AtomicRequestDescriptor_t descriptor; | |
4373 | u32 *request = (u32 *)&descriptor; | |
4374 | ||
4375 | descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; | |
4376 | descriptor.MSIxIndex = msix_task; | |
4377 | descriptor.SMID = cpu_to_le16(smid); | |
4378 | ||
f920642e | 4379 | writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); |
79c74d03 SP |
4380 | } |
4381 | ||
4382 | /** | |
e015e0de | 4383 | * _base_put_smid_default_atomic - Default, primarily used for config pages |
79c74d03 SP |
4384 | * use Atomic Request Descriptor |
4385 | * @ioc: per adapter object | |
4386 | * @smid: system request message index | |
4387 | * | |
2910a4a9 | 4388 | * Return: nothing. |
79c74d03 SP |
4389 | */ |
4390 | static void | |
4391 | _base_put_smid_default_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid) | |
4392 | { | |
4393 | Mpi26AtomicRequestDescriptor_t descriptor; | |
4394 | u32 *request = (u32 *)&descriptor; | |
4395 | ||
4396 | descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; | |
998c3001 | 4397 | descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid); |
79c74d03 SP |
4398 | descriptor.SMID = cpu_to_le16(smid); |
4399 | ||
f920642e | 4400 | writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost); |
79c74d03 SP |
4401 | } |
4402 | ||
1117b31a | 4403 | /** |
989e43c7 | 4404 | * _base_display_OEMs_branding - Display branding string |
1117b31a | 4405 | * @ioc: per adapter object |
1117b31a SR |
4406 | */ |
4407 | static void | |
989e43c7 | 4408 | _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc) |
1117b31a SR |
4409 | { |
4410 | if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL) | |
4411 | return; | |
4412 | ||
989e43c7 SR |
4413 | switch (ioc->pdev->subsystem_vendor) { |
4414 | case PCI_VENDOR_ID_INTEL: | |
4415 | switch (ioc->pdev->device) { | |
4416 | case MPI2_MFGPAGE_DEVID_SAS2008: | |
4417 | switch (ioc->pdev->subsystem_device) { | |
4418 | case MPT2SAS_INTEL_RMS2LL080_SSDID: | |
919d8a3f JP |
4419 | ioc_info(ioc, "%s\n", |
4420 | MPT2SAS_INTEL_RMS2LL080_BRANDING); | |
989e43c7 SR |
4421 | break; |
4422 | case MPT2SAS_INTEL_RMS2LL040_SSDID: | |
919d8a3f JP |
4423 | ioc_info(ioc, "%s\n", |
4424 | MPT2SAS_INTEL_RMS2LL040_BRANDING); | |
989e43c7 SR |
4425 | break; |
4426 | case MPT2SAS_INTEL_SSD910_SSDID: | |
919d8a3f JP |
4427 | ioc_info(ioc, "%s\n", |
4428 | MPT2SAS_INTEL_SSD910_BRANDING); | |
989e43c7 SR |
4429 | break; |
4430 | default: | |
919d8a3f JP |
4431 | ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n", |
4432 | ioc->pdev->subsystem_device); | |
989e43c7 SR |
4433 | break; |
4434 | } | |
7850b51b | 4435 | break; |
989e43c7 SR |
4436 | case MPI2_MFGPAGE_DEVID_SAS2308_2: |
4437 | switch (ioc->pdev->subsystem_device) { | |
4438 | case MPT2SAS_INTEL_RS25GB008_SSDID: | |
919d8a3f JP |
4439 | ioc_info(ioc, "%s\n", |
4440 | MPT2SAS_INTEL_RS25GB008_BRANDING); | |
989e43c7 SR |
4441 | break; |
4442 | case MPT2SAS_INTEL_RMS25JB080_SSDID: | |
919d8a3f JP |
4443 | ioc_info(ioc, "%s\n", |
4444 | MPT2SAS_INTEL_RMS25JB080_BRANDING); | |
989e43c7 SR |
4445 | break; |
4446 | case MPT2SAS_INTEL_RMS25JB040_SSDID: | |
919d8a3f JP |
4447 | ioc_info(ioc, "%s\n", |
4448 | MPT2SAS_INTEL_RMS25JB040_BRANDING); | |
989e43c7 SR |
4449 | break; |
4450 | case MPT2SAS_INTEL_RMS25KB080_SSDID: | |
919d8a3f JP |
4451 | ioc_info(ioc, "%s\n", |
4452 | MPT2SAS_INTEL_RMS25KB080_BRANDING); | |
989e43c7 SR |
4453 | break; |
4454 | case MPT2SAS_INTEL_RMS25KB040_SSDID: | |
919d8a3f JP |
4455 | ioc_info(ioc, "%s\n", |
4456 | MPT2SAS_INTEL_RMS25KB040_BRANDING); | |
989e43c7 SR |
4457 | break; |
4458 | case MPT2SAS_INTEL_RMS25LB040_SSDID: | |
919d8a3f JP |
4459 | ioc_info(ioc, "%s\n", |
4460 | MPT2SAS_INTEL_RMS25LB040_BRANDING); | |
989e43c7 SR |
4461 | break; |
4462 | case MPT2SAS_INTEL_RMS25LB080_SSDID: | |
919d8a3f JP |
4463 | ioc_info(ioc, "%s\n", |
4464 | MPT2SAS_INTEL_RMS25LB080_BRANDING); | |
989e43c7 SR |
4465 | break; |
4466 | default: | |
919d8a3f JP |
4467 | ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n", |
4468 | ioc->pdev->subsystem_device); | |
989e43c7 SR |
4469 | break; |
4470 | } | |
7850b51b | 4471 | break; |
989e43c7 SR |
4472 | case MPI25_MFGPAGE_DEVID_SAS3008: |
4473 | switch (ioc->pdev->subsystem_device) { | |
4474 | case MPT3SAS_INTEL_RMS3JC080_SSDID: | |
919d8a3f JP |
4475 | ioc_info(ioc, "%s\n", |
4476 | MPT3SAS_INTEL_RMS3JC080_BRANDING); | |
989e43c7 SR |
4477 | break; |
4478 | ||
4479 | case MPT3SAS_INTEL_RS3GC008_SSDID: | |
919d8a3f JP |
4480 | ioc_info(ioc, "%s\n", |
4481 | MPT3SAS_INTEL_RS3GC008_BRANDING); | |
989e43c7 SR |
4482 | break; |
4483 | case MPT3SAS_INTEL_RS3FC044_SSDID: | |
919d8a3f JP |
4484 | ioc_info(ioc, "%s\n", |
4485 | MPT3SAS_INTEL_RS3FC044_BRANDING); | |
989e43c7 SR |
4486 | break; |
4487 | case MPT3SAS_INTEL_RS3UC080_SSDID: | |
919d8a3f JP |
4488 | ioc_info(ioc, "%s\n", |
4489 | MPT3SAS_INTEL_RS3UC080_BRANDING); | |
989e43c7 SR |
4490 | break; |
4491 | default: | |
919d8a3f JP |
4492 | ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n", |
4493 | ioc->pdev->subsystem_device); | |
989e43c7 SR |
4494 | break; |
4495 | } | |
1117b31a SR |
4496 | break; |
4497 | default: | |
919d8a3f JP |
4498 | ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n", |
4499 | ioc->pdev->subsystem_device); | |
1117b31a SR |
4500 | break; |
4501 | } | |
4502 | break; | |
989e43c7 SR |
4503 | case PCI_VENDOR_ID_DELL: |
4504 | switch (ioc->pdev->device) { | |
4505 | case MPI2_MFGPAGE_DEVID_SAS2008: | |
4506 | switch (ioc->pdev->subsystem_device) { | |
4507 | case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID: | |
919d8a3f JP |
4508 | ioc_info(ioc, "%s\n", |
4509 | MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING); | |
989e43c7 SR |
4510 | break; |
4511 | case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID: | |
919d8a3f JP |
4512 | ioc_info(ioc, "%s\n", |
4513 | MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING); | |
989e43c7 SR |
4514 | break; |
4515 | case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID: | |
919d8a3f JP |
4516 | ioc_info(ioc, "%s\n", |
4517 | MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING); | |
989e43c7 SR |
4518 | break; |
4519 | case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID: | |
919d8a3f JP |
4520 | ioc_info(ioc, "%s\n", |
4521 | MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING); | |
989e43c7 SR |
4522 | break; |
4523 | case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID: | |
919d8a3f JP |
4524 | ioc_info(ioc, "%s\n", |
4525 | MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING); | |
989e43c7 SR |
4526 | break; |
4527 | case MPT2SAS_DELL_PERC_H200_SSDID: | |
919d8a3f JP |
4528 | ioc_info(ioc, "%s\n", |
4529 | MPT2SAS_DELL_PERC_H200_BRANDING); | |
989e43c7 SR |
4530 | break; |
4531 | case MPT2SAS_DELL_6GBPS_SAS_SSDID: | |
919d8a3f JP |
4532 | ioc_info(ioc, "%s\n", |
4533 | MPT2SAS_DELL_6GBPS_SAS_BRANDING); | |
989e43c7 SR |
4534 | break; |
4535 | default: | |
919d8a3f JP |
4536 | ioc_info(ioc, "Dell 6Gbps HBA: Subsystem ID: 0x%X\n", |
4537 | ioc->pdev->subsystem_device); | |
989e43c7 SR |
4538 | break; |
4539 | } | |
4540 | break; | |
4541 | case MPI25_MFGPAGE_DEVID_SAS3008: | |
4542 | switch (ioc->pdev->subsystem_device) { | |
4543 | case MPT3SAS_DELL_12G_HBA_SSDID: | |
919d8a3f JP |
4544 | ioc_info(ioc, "%s\n", |
4545 | MPT3SAS_DELL_12G_HBA_BRANDING); | |
989e43c7 SR |
4546 | break; |
4547 | default: | |
919d8a3f JP |
4548 | ioc_info(ioc, "Dell 12Gbps HBA: Subsystem ID: 0x%X\n", |
4549 | ioc->pdev->subsystem_device); | |
989e43c7 SR |
4550 | break; |
4551 | } | |
fb84dfc4 SR |
4552 | break; |
4553 | default: | |
919d8a3f JP |
4554 | ioc_info(ioc, "Dell HBA: Subsystem ID: 0x%X\n", |
4555 | ioc->pdev->subsystem_device); | |
fb84dfc4 SR |
4556 | break; |
4557 | } | |
4558 | break; | |
989e43c7 SR |
4559 | case PCI_VENDOR_ID_CISCO: |
4560 | switch (ioc->pdev->device) { | |
4561 | case MPI25_MFGPAGE_DEVID_SAS3008: | |
4562 | switch (ioc->pdev->subsystem_device) { | |
4563 | case MPT3SAS_CISCO_12G_8E_HBA_SSDID: | |
919d8a3f JP |
4564 | ioc_info(ioc, "%s\n", |
4565 | MPT3SAS_CISCO_12G_8E_HBA_BRANDING); | |
989e43c7 SR |
4566 | break; |
4567 | case MPT3SAS_CISCO_12G_8I_HBA_SSDID: | |
919d8a3f JP |
4568 | ioc_info(ioc, "%s\n", |
4569 | MPT3SAS_CISCO_12G_8I_HBA_BRANDING); | |
989e43c7 SR |
4570 | break; |
4571 | case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: | |
919d8a3f JP |
4572 | ioc_info(ioc, "%s\n", |
4573 | MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); | |
989e43c7 SR |
4574 | break; |
4575 | default: | |
919d8a3f JP |
4576 | ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", |
4577 | ioc->pdev->subsystem_device); | |
989e43c7 SR |
4578 | break; |
4579 | } | |
d8eb4a47 | 4580 | break; |
989e43c7 SR |
4581 | case MPI25_MFGPAGE_DEVID_SAS3108_1: |
4582 | switch (ioc->pdev->subsystem_device) { | |
4583 | case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: | |
919d8a3f JP |
4584 | ioc_info(ioc, "%s\n", |
4585 | MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); | |
989e43c7 SR |
4586 | break; |
4587 | case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID: | |
919d8a3f JP |
4588 | ioc_info(ioc, "%s\n", |
4589 | MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING); | |
989e43c7 SR |
4590 | break; |
4591 | default: | |
919d8a3f JP |
4592 | ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", |
4593 | ioc->pdev->subsystem_device); | |
989e43c7 SR |
4594 | break; |
4595 | } | |
38e4141e SR |
4596 | break; |
4597 | default: | |
919d8a3f JP |
4598 | ioc_info(ioc, "Cisco SAS HBA: Subsystem ID: 0x%X\n", |
4599 | ioc->pdev->subsystem_device); | |
38e4141e SR |
4600 | break; |
4601 | } | |
4602 | break; | |
989e43c7 SR |
4603 | case MPT2SAS_HP_3PAR_SSVID: |
4604 | switch (ioc->pdev->device) { | |
4605 | case MPI2_MFGPAGE_DEVID_SAS2004: | |
4606 | switch (ioc->pdev->subsystem_device) { | |
4607 | case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID: | |
919d8a3f JP |
4608 | ioc_info(ioc, "%s\n", |
4609 | MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING); | |
989e43c7 SR |
4610 | break; |
4611 | default: | |
919d8a3f JP |
4612 | ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", |
4613 | ioc->pdev->subsystem_device); | |
989e43c7 SR |
4614 | break; |
4615 | } | |
7850b51b | 4616 | break; |
989e43c7 SR |
4617 | case MPI2_MFGPAGE_DEVID_SAS2308_2: |
4618 | switch (ioc->pdev->subsystem_device) { | |
4619 | case MPT2SAS_HP_2_4_INTERNAL_SSDID: | |
919d8a3f JP |
4620 | ioc_info(ioc, "%s\n", |
4621 | MPT2SAS_HP_2_4_INTERNAL_BRANDING); | |
989e43c7 SR |
4622 | break; |
4623 | case MPT2SAS_HP_2_4_EXTERNAL_SSDID: | |
919d8a3f JP |
4624 | ioc_info(ioc, "%s\n", |
4625 | MPT2SAS_HP_2_4_EXTERNAL_BRANDING); | |
989e43c7 SR |
4626 | break; |
4627 | case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID: | |
919d8a3f JP |
4628 | ioc_info(ioc, "%s\n", |
4629 | MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING); | |
989e43c7 SR |
4630 | break; |
4631 | case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID: | |
919d8a3f JP |
4632 | ioc_info(ioc, "%s\n", |
4633 | MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING); | |
989e43c7 SR |
4634 | break; |
4635 | default: | |
919d8a3f JP |
4636 | ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", |
4637 | ioc->pdev->subsystem_device); | |
989e43c7 SR |
4638 | break; |
4639 | } | |
7850b51b | 4640 | break; |
d8eb4a47 | 4641 | default: |
919d8a3f JP |
4642 | ioc_info(ioc, "HP SAS HBA: Subsystem ID: 0x%X\n", |
4643 | ioc->pdev->subsystem_device); | |
d8eb4a47 SR |
4644 | break; |
4645 | } | |
84a84cc6 | 4646 | break; |
38e4141e | 4647 | default: |
38e4141e SR |
4648 | break; |
4649 | } | |
4650 | } | |
fb84dfc4 | 4651 | |
3d29ed85 C |
4652 | /** |
4653 | * _base_display_fwpkg_version - sends FWUpload request to pull FWPkg | |
4654 | * version from FW Image Header. | |
4655 | * @ioc: per adapter object | |
4656 | * | |
4beb4867 | 4657 | * Return: 0 for success, non-zero for failure. |
3d29ed85 C |
4658 | */ |
4659 | static int | |
4660 | _base_display_fwpkg_version(struct MPT3SAS_ADAPTER *ioc) | |
4661 | { | |
b06ff102 SR |
4662 | Mpi2FWImageHeader_t *fw_img_hdr; |
4663 | Mpi26ComponentImageHeader_t *cmp_img_hdr; | |
3d29ed85 C |
4664 | Mpi25FWUploadRequest_t *mpi_request; |
4665 | Mpi2FWUploadReply_t mpi_reply; | |
19a622c3 | 4666 | int r = 0, issue_diag_reset = 0; |
b06ff102 | 4667 | u32 package_version = 0; |
3d29ed85 C |
4668 | void *fwpkg_data = NULL; |
4669 | dma_addr_t fwpkg_data_dma; | |
4670 | u16 smid, ioc_status; | |
4671 | size_t data_length; | |
4672 | ||
919d8a3f | 4673 | dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); |
3d29ed85 C |
4674 | |
4675 | if (ioc->base_cmds.status & MPT3_CMD_PENDING) { | |
919d8a3f | 4676 | ioc_err(ioc, "%s: internal command already in use\n", __func__); |
3d29ed85 C |
4677 | return -EAGAIN; |
4678 | } | |
4679 | ||
4680 | data_length = sizeof(Mpi2FWImageHeader_t); | |
1c2048bd CH |
4681 | fwpkg_data = dma_alloc_coherent(&ioc->pdev->dev, data_length, |
4682 | &fwpkg_data_dma, GFP_KERNEL); | |
3d29ed85 | 4683 | if (!fwpkg_data) { |
5b061980 SR |
4684 | ioc_err(ioc, |
4685 | "Memory allocation for fwpkg data failed at %s:%d/%s()!\n", | |
919d8a3f | 4686 | __FILE__, __LINE__, __func__); |
3d29ed85 C |
4687 | return -ENOMEM; |
4688 | } | |
4689 | ||
4690 | smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); | |
4691 | if (!smid) { | |
919d8a3f | 4692 | ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); |
3d29ed85 C |
4693 | r = -EAGAIN; |
4694 | goto out; | |
4695 | } | |
4696 | ||
4697 | ioc->base_cmds.status = MPT3_CMD_PENDING; | |
4698 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
4699 | ioc->base_cmds.smid = smid; | |
4700 | memset(mpi_request, 0, sizeof(Mpi25FWUploadRequest_t)); | |
4701 | mpi_request->Function = MPI2_FUNCTION_FW_UPLOAD; | |
4702 | mpi_request->ImageType = MPI2_FW_UPLOAD_ITYPE_FW_FLASH; | |
4703 | mpi_request->ImageSize = cpu_to_le32(data_length); | |
4704 | ioc->build_sg(ioc, &mpi_request->SGL, 0, 0, fwpkg_data_dma, | |
4705 | data_length); | |
4706 | init_completion(&ioc->base_cmds.done); | |
078a4cc1 | 4707 | ioc->put_smid_default(ioc, smid); |
3d29ed85 C |
4708 | /* Wait for 15 seconds */ |
4709 | wait_for_completion_timeout(&ioc->base_cmds.done, | |
4710 | FW_IMG_HDR_READ_TIMEOUT*HZ); | |
919d8a3f | 4711 | ioc_info(ioc, "%s: complete\n", __func__); |
3d29ed85 | 4712 | if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { |
919d8a3f | 4713 | ioc_err(ioc, "%s: timeout\n", __func__); |
3d29ed85 C |
4714 | _debug_dump_mf(mpi_request, |
4715 | sizeof(Mpi25FWUploadRequest_t)/4); | |
19a622c3 | 4716 | issue_diag_reset = 1; |
3d29ed85 C |
4717 | } else { |
4718 | memset(&mpi_reply, 0, sizeof(Mpi2FWUploadReply_t)); | |
4719 | if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) { | |
4720 | memcpy(&mpi_reply, ioc->base_cmds.reply, | |
4721 | sizeof(Mpi2FWUploadReply_t)); | |
4722 | ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & | |
4723 | MPI2_IOCSTATUS_MASK; | |
4724 | if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { | |
b06ff102 SR |
4725 | fw_img_hdr = (Mpi2FWImageHeader_t *)fwpkg_data; |
4726 | if (le32_to_cpu(fw_img_hdr->Signature) == | |
4727 | MPI26_IMAGE_HEADER_SIGNATURE0_MPI26) { | |
4728 | cmp_img_hdr = | |
4729 | (Mpi26ComponentImageHeader_t *) | |
4730 | (fwpkg_data); | |
4731 | package_version = | |
4732 | le32_to_cpu( | |
4733 | cmp_img_hdr->ApplicationSpecific); | |
4734 | } else | |
4735 | package_version = | |
4736 | le32_to_cpu( | |
4737 | fw_img_hdr->PackageVersion.Word); | |
4738 | if (package_version) | |
4739 | ioc_info(ioc, | |
4740 | "FW Package Ver(%02d.%02d.%02d.%02d)\n", | |
4741 | ((package_version) & 0xFF000000) >> 24, | |
4742 | ((package_version) & 0x00FF0000) >> 16, | |
4743 | ((package_version) & 0x0000FF00) >> 8, | |
4744 | (package_version) & 0x000000FF); | |
3d29ed85 C |
4745 | } else { |
4746 | _debug_dump_mf(&mpi_reply, | |
4747 | sizeof(Mpi2FWUploadReply_t)/4); | |
4748 | } | |
4749 | } | |
4750 | } | |
4751 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; | |
4752 | out: | |
4753 | if (fwpkg_data) | |
1c2048bd | 4754 | dma_free_coherent(&ioc->pdev->dev, data_length, fwpkg_data, |
3d29ed85 | 4755 | fwpkg_data_dma); |
19a622c3 SP |
4756 | if (issue_diag_reset) { |
4757 | if (ioc->drv_internal_flags & MPT_DRV_INTERNAL_FIRST_PE_ISSUED) | |
4758 | return -EFAULT; | |
4759 | if (mpt3sas_base_check_for_fault_and_issue_reset(ioc)) | |
4760 | return -EFAULT; | |
4761 | r = -EAGAIN; | |
4762 | } | |
3d29ed85 C |
4763 | return r; |
4764 | } | |
4765 | ||
f92363d1 | 4766 | /** |
2910a4a9 | 4767 | * _base_display_ioc_capabilities - Display IOC's capabilities. |
f92363d1 | 4768 | * @ioc: per adapter object |
f92363d1 SR |
4769 | */ |
4770 | static void | |
4771 | _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc) | |
4772 | { | |
4773 | int i = 0; | |
8e129add | 4774 | char desc[17] = {0}; |
f92363d1 | 4775 | u32 iounit_pg1_flags; |
f92363d1 | 4776 | |
f92363d1 | 4777 | strncpy(desc, ioc->manu_pg0.ChipName, 16); |
3fc5d6d6 | 4778 | ioc_info(ioc, "%s: FWVersion(%02d.%02d.%02d.%02d), ChipRevision(0x%02x)\n", |
919d8a3f JP |
4779 | desc, |
4780 | (ioc->facts.FWVersion.Word & 0xFF000000) >> 24, | |
4781 | (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16, | |
4782 | (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8, | |
4783 | ioc->facts.FWVersion.Word & 0x000000FF, | |
3fc5d6d6 | 4784 | ioc->pdev->revision); |
f92363d1 | 4785 | |
989e43c7 | 4786 | _base_display_OEMs_branding(ioc); |
1117b31a | 4787 | |
016d5c35 SPS |
4788 | if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) { |
4789 | pr_info("%sNVMe", i ? "," : ""); | |
4790 | i++; | |
4791 | } | |
4792 | ||
919d8a3f | 4793 | ioc_info(ioc, "Protocol=("); |
f92363d1 SR |
4794 | |
4795 | if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) { | |
919d8a3f | 4796 | pr_cont("Initiator"); |
f92363d1 SR |
4797 | i++; |
4798 | } | |
4799 | ||
4800 | if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) { | |
919d8a3f | 4801 | pr_cont("%sTarget", i ? "," : ""); |
f92363d1 SR |
4802 | i++; |
4803 | } | |
4804 | ||
4805 | i = 0; | |
919d8a3f | 4806 | pr_cont("), Capabilities=("); |
f92363d1 | 4807 | |
7786ab6a SR |
4808 | if (!ioc->hide_ir_msg) { |
4809 | if (ioc->facts.IOCCapabilities & | |
f92363d1 | 4810 | MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) { |
919d8a3f | 4811 | pr_cont("Raid"); |
f92363d1 | 4812 | i++; |
7786ab6a | 4813 | } |
f92363d1 SR |
4814 | } |
4815 | ||
4816 | if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) { | |
919d8a3f | 4817 | pr_cont("%sTLR", i ? "," : ""); |
f92363d1 SR |
4818 | i++; |
4819 | } | |
4820 | ||
4821 | if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) { | |
919d8a3f | 4822 | pr_cont("%sMulticast", i ? "," : ""); |
f92363d1 SR |
4823 | i++; |
4824 | } | |
4825 | ||
4826 | if (ioc->facts.IOCCapabilities & | |
4827 | MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) { | |
919d8a3f | 4828 | pr_cont("%sBIDI Target", i ? "," : ""); |
f92363d1 SR |
4829 | i++; |
4830 | } | |
4831 | ||
4832 | if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) { | |
919d8a3f | 4833 | pr_cont("%sEEDP", i ? "," : ""); |
f92363d1 SR |
4834 | i++; |
4835 | } | |
4836 | ||
4837 | if (ioc->facts.IOCCapabilities & | |
4838 | MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) { | |
919d8a3f | 4839 | pr_cont("%sSnapshot Buffer", i ? "," : ""); |
f92363d1 SR |
4840 | i++; |
4841 | } | |
4842 | ||
4843 | if (ioc->facts.IOCCapabilities & | |
4844 | MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) { | |
919d8a3f | 4845 | pr_cont("%sDiag Trace Buffer", i ? "," : ""); |
f92363d1 SR |
4846 | i++; |
4847 | } | |
4848 | ||
4849 | if (ioc->facts.IOCCapabilities & | |
4850 | MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) { | |
919d8a3f | 4851 | pr_cont("%sDiag Extended Buffer", i ? "," : ""); |
f92363d1 SR |
4852 | i++; |
4853 | } | |
4854 | ||
4855 | if (ioc->facts.IOCCapabilities & | |
4856 | MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) { | |
919d8a3f | 4857 | pr_cont("%sTask Set Full", i ? "," : ""); |
f92363d1 SR |
4858 | i++; |
4859 | } | |
4860 | ||
4861 | iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); | |
4862 | if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) { | |
919d8a3f | 4863 | pr_cont("%sNCQ", i ? "," : ""); |
f92363d1 SR |
4864 | i++; |
4865 | } | |
4866 | ||
919d8a3f | 4867 | pr_cont(")\n"); |
f92363d1 SR |
4868 | } |
4869 | ||
4870 | /** | |
4871 | * mpt3sas_base_update_missing_delay - change the missing delay timers | |
4872 | * @ioc: per adapter object | |
4873 | * @device_missing_delay: amount of time till device is reported missing | |
4874 | * @io_missing_delay: interval IO is returned when there is a missing device | |
4875 | * | |
f92363d1 SR |
4876 | * Passed on the command line, this function will modify the device missing |
4877 | * delay, as well as the io missing delay. This should be called at driver | |
4878 | * load time. | |
4879 | */ | |
4880 | void | |
4881 | mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc, | |
4882 | u16 device_missing_delay, u8 io_missing_delay) | |
4883 | { | |
4884 | u16 dmd, dmd_new, dmd_orignal; | |
4885 | u8 io_missing_delay_original; | |
4886 | u16 sz; | |
4887 | Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL; | |
4888 | Mpi2ConfigReply_t mpi_reply; | |
4889 | u8 num_phys = 0; | |
4890 | u16 ioc_status; | |
4891 | ||
4892 | mpt3sas_config_get_number_hba_phys(ioc, &num_phys); | |
4893 | if (!num_phys) | |
4894 | return; | |
4895 | ||
f4f76e14 | 4896 | sz = struct_size(sas_iounit_pg1, PhyData, num_phys); |
f92363d1 SR |
4897 | sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL); |
4898 | if (!sas_iounit_pg1) { | |
919d8a3f JP |
4899 | ioc_err(ioc, "failure at %s:%d/%s()!\n", |
4900 | __FILE__, __LINE__, __func__); | |
f92363d1 SR |
4901 | goto out; |
4902 | } | |
4903 | if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply, | |
4904 | sas_iounit_pg1, sz))) { | |
919d8a3f JP |
4905 | ioc_err(ioc, "failure at %s:%d/%s()!\n", |
4906 | __FILE__, __LINE__, __func__); | |
f92363d1 SR |
4907 | goto out; |
4908 | } | |
4909 | ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & | |
4910 | MPI2_IOCSTATUS_MASK; | |
4911 | if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { | |
919d8a3f JP |
4912 | ioc_err(ioc, "failure at %s:%d/%s()!\n", |
4913 | __FILE__, __LINE__, __func__); | |
f92363d1 SR |
4914 | goto out; |
4915 | } | |
4916 | ||
4917 | /* device missing delay */ | |
4918 | dmd = sas_iounit_pg1->ReportDeviceMissingDelay; | |
4919 | if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) | |
4920 | dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; | |
4921 | else | |
4922 | dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; | |
4923 | dmd_orignal = dmd; | |
4924 | if (device_missing_delay > 0x7F) { | |
4925 | dmd = (device_missing_delay > 0x7F0) ? 0x7F0 : | |
4926 | device_missing_delay; | |
4927 | dmd = dmd / 16; | |
4928 | dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16; | |
4929 | } else | |
4930 | dmd = device_missing_delay; | |
4931 | sas_iounit_pg1->ReportDeviceMissingDelay = dmd; | |
4932 | ||
4933 | /* io missing delay */ | |
4934 | io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay; | |
4935 | sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay; | |
4936 | ||
4937 | if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1, | |
4938 | sz)) { | |
4939 | if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) | |
4940 | dmd_new = (dmd & | |
4941 | MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; | |
4942 | else | |
4943 | dmd_new = | |
4944 | dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; | |
919d8a3f JP |
4945 | ioc_info(ioc, "device_missing_delay: old(%d), new(%d)\n", |
4946 | dmd_orignal, dmd_new); | |
4947 | ioc_info(ioc, "ioc_missing_delay: old(%d), new(%d)\n", | |
4948 | io_missing_delay_original, | |
4949 | io_missing_delay); | |
f92363d1 SR |
4950 | ioc->device_missing_delay = dmd_new; |
4951 | ioc->io_missing_delay = io_missing_delay; | |
4952 | } | |
4953 | ||
4954 | out: | |
4955 | kfree(sas_iounit_pg1); | |
4956 | } | |
4beb4867 | 4957 | |
ca7e1e9d SP |
4958 | /** |
4959 | * _base_update_ioc_page1_inlinewith_perf_mode - Update IOC Page1 fields | |
4960 | * according to performance mode. | |
4961 | * @ioc : per adapter object | |
4962 | * | |
19a622c3 SP |
4963 | * Return: zero on success; otherwise return EAGAIN error code asking the |
4964 | * caller to retry. | |
ca7e1e9d | 4965 | */ |
19a622c3 | 4966 | static int |
ca7e1e9d SP |
4967 | _base_update_ioc_page1_inlinewith_perf_mode(struct MPT3SAS_ADAPTER *ioc) |
4968 | { | |
4969 | Mpi2IOCPage1_t ioc_pg1; | |
4970 | Mpi2ConfigReply_t mpi_reply; | |
19a622c3 | 4971 | int rc; |
ca7e1e9d | 4972 | |
19a622c3 SP |
4973 | rc = mpt3sas_config_get_ioc_pg1(ioc, &mpi_reply, &ioc->ioc_pg1_copy); |
4974 | if (rc) | |
4975 | return rc; | |
ca7e1e9d SP |
4976 | memcpy(&ioc_pg1, &ioc->ioc_pg1_copy, sizeof(Mpi2IOCPage1_t)); |
4977 | ||
4978 | switch (perf_mode) { | |
4979 | case MPT_PERF_MODE_DEFAULT: | |
4980 | case MPT_PERF_MODE_BALANCED: | |
4981 | if (ioc->high_iops_queues) { | |
4982 | ioc_info(ioc, | |
4983 | "Enable interrupt coalescing only for first\t" | |
4984 | "%d reply queues\n", | |
4985 | MPT3SAS_HIGH_IOPS_REPLY_QUEUES); | |
4986 | /* | |
4987 | * If 31st bit is zero then interrupt coalescing is | |
4988 | * enabled for all reply descriptor post queues. | |
4989 | * If 31st bit is set to one then user can | |
4990 | * enable/disable interrupt coalescing on per reply | |
4991 | * descriptor post queue group(8) basis. So to enable | |
4992 | * interrupt coalescing only on first reply descriptor | |
4993 | * post queue group 31st bit and zero th bit is enabled. | |
4994 | */ | |
4995 | ioc_pg1.ProductSpecific = cpu_to_le32(0x80000000 | | |
4996 | ((1 << MPT3SAS_HIGH_IOPS_REPLY_QUEUES/8) - 1)); | |
19a622c3 SP |
4997 | rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1); |
4998 | if (rc) | |
4999 | return rc; | |
ca7e1e9d | 5000 | ioc_info(ioc, "performance mode: balanced\n"); |
19a622c3 | 5001 | return 0; |
ca7e1e9d | 5002 | } |
df561f66 | 5003 | fallthrough; |
ca7e1e9d SP |
5004 | case MPT_PERF_MODE_LATENCY: |
5005 | /* | |
5006 | * Enable interrupt coalescing on all reply queues | |
5007 | * with timeout value 0xA | |
5008 | */ | |
5009 | ioc_pg1.CoalescingTimeout = cpu_to_le32(0xa); | |
5010 | ioc_pg1.Flags |= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING); | |
5011 | ioc_pg1.ProductSpecific = 0; | |
19a622c3 SP |
5012 | rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1); |
5013 | if (rc) | |
5014 | return rc; | |
ca7e1e9d SP |
5015 | ioc_info(ioc, "performance mode: latency\n"); |
5016 | break; | |
5017 | case MPT_PERF_MODE_IOPS: | |
5018 | /* | |
5019 | * Enable interrupt coalescing on all reply queues. | |
5020 | */ | |
5021 | ioc_info(ioc, | |
5022 | "performance mode: iops with coalescing timeout: 0x%x\n", | |
5023 | le32_to_cpu(ioc_pg1.CoalescingTimeout)); | |
5024 | ioc_pg1.Flags |= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING); | |
5025 | ioc_pg1.ProductSpecific = 0; | |
19a622c3 SP |
5026 | rc = mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1); |
5027 | if (rc) | |
5028 | return rc; | |
ca7e1e9d SP |
5029 | break; |
5030 | } | |
19a622c3 | 5031 | return 0; |
ca7e1e9d SP |
5032 | } |
5033 | ||
71b3fb8f SP |
5034 | /** |
5035 | * _base_get_event_diag_triggers - get event diag trigger values from | |
5036 | * persistent pages | |
5037 | * @ioc : per adapter object | |
5038 | * | |
2910a4a9 | 5039 | * Return: nothing. |
71b3fb8f | 5040 | */ |
19a622c3 | 5041 | static int |
71b3fb8f SP |
5042 | _base_get_event_diag_triggers(struct MPT3SAS_ADAPTER *ioc) |
5043 | { | |
5044 | Mpi26DriverTriggerPage2_t trigger_pg2; | |
5045 | struct SL_WH_EVENT_TRIGGER_T *event_tg; | |
e5035459 | 5046 | MPI26_DRIVER_MPI_EVENT_TRIGGER_ENTRY *mpi_event_tg; |
71b3fb8f SP |
5047 | Mpi2ConfigReply_t mpi_reply; |
5048 | int r = 0, i = 0; | |
5049 | u16 count = 0; | |
5050 | u16 ioc_status; | |
5051 | ||
5052 | r = mpt3sas_config_get_driver_trigger_pg2(ioc, &mpi_reply, | |
5053 | &trigger_pg2); | |
5054 | if (r) | |
19a622c3 | 5055 | return r; |
71b3fb8f SP |
5056 | |
5057 | ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & | |
5058 | MPI2_IOCSTATUS_MASK; | |
5059 | if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { | |
5060 | dinitprintk(ioc, | |
5061 | ioc_err(ioc, | |
5062 | "%s: Failed to get trigger pg2, ioc_status(0x%04x)\n", | |
5063 | __func__, ioc_status)); | |
19a622c3 | 5064 | return 0; |
71b3fb8f SP |
5065 | } |
5066 | ||
5067 | if (le16_to_cpu(trigger_pg2.NumMPIEventTrigger)) { | |
5068 | count = le16_to_cpu(trigger_pg2.NumMPIEventTrigger); | |
5069 | count = min_t(u16, NUM_VALID_ENTRIES, count); | |
5070 | ioc->diag_trigger_event.ValidEntries = count; | |
5071 | ||
5072 | event_tg = &ioc->diag_trigger_event.EventTriggerEntry[0]; | |
5073 | mpi_event_tg = &trigger_pg2.MPIEventTriggers[0]; | |
5074 | for (i = 0; i < count; i++) { | |
5075 | event_tg->EventValue = le16_to_cpu( | |
5076 | mpi_event_tg->MPIEventCode); | |
5077 | event_tg->LogEntryQualifier = le16_to_cpu( | |
5078 | mpi_event_tg->MPIEventCodeSpecific); | |
5079 | event_tg++; | |
5080 | mpi_event_tg++; | |
5081 | } | |
5082 | } | |
19a622c3 | 5083 | return 0; |
71b3fb8f SP |
5084 | } |
5085 | ||
2a5c3a35 SP |
5086 | /** |
5087 | * _base_get_scsi_diag_triggers - get scsi diag trigger values from | |
5088 | * persistent pages | |
5089 | * @ioc : per adapter object | |
5090 | * | |
19a622c3 | 5091 | * Return: 0 on success; otherwise return failure status. |
2a5c3a35 | 5092 | */ |
19a622c3 | 5093 | static int |
2a5c3a35 SP |
5094 | _base_get_scsi_diag_triggers(struct MPT3SAS_ADAPTER *ioc) |
5095 | { | |
5096 | Mpi26DriverTriggerPage3_t trigger_pg3; | |
5097 | struct SL_WH_SCSI_TRIGGER_T *scsi_tg; | |
e5035459 | 5098 | MPI26_DRIVER_SCSI_SENSE_TRIGGER_ENTRY *mpi_scsi_tg; |
2a5c3a35 SP |
5099 | Mpi2ConfigReply_t mpi_reply; |
5100 | int r = 0, i = 0; | |
5101 | u16 count = 0; | |
5102 | u16 ioc_status; | |
5103 | ||
5104 | r = mpt3sas_config_get_driver_trigger_pg3(ioc, &mpi_reply, | |
5105 | &trigger_pg3); | |
5106 | if (r) | |
19a622c3 | 5107 | return r; |
2a5c3a35 SP |
5108 | |
5109 | ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & | |
5110 | MPI2_IOCSTATUS_MASK; | |
5111 | if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { | |
5112 | dinitprintk(ioc, | |
5113 | ioc_err(ioc, | |
5114 | "%s: Failed to get trigger pg3, ioc_status(0x%04x)\n", | |
5115 | __func__, ioc_status)); | |
19a622c3 | 5116 | return 0; |
2a5c3a35 SP |
5117 | } |
5118 | ||
5119 | if (le16_to_cpu(trigger_pg3.NumSCSISenseTrigger)) { | |
5120 | count = le16_to_cpu(trigger_pg3.NumSCSISenseTrigger); | |
5121 | count = min_t(u16, NUM_VALID_ENTRIES, count); | |
5122 | ioc->diag_trigger_scsi.ValidEntries = count; | |
5123 | ||
5124 | scsi_tg = &ioc->diag_trigger_scsi.SCSITriggerEntry[0]; | |
5125 | mpi_scsi_tg = &trigger_pg3.SCSISenseTriggers[0]; | |
5126 | for (i = 0; i < count; i++) { | |
5127 | scsi_tg->ASCQ = mpi_scsi_tg->ASCQ; | |
5128 | scsi_tg->ASC = mpi_scsi_tg->ASC; | |
5129 | scsi_tg->SenseKey = mpi_scsi_tg->SenseKey; | |
5130 | ||
5131 | scsi_tg++; | |
5132 | mpi_scsi_tg++; | |
5133 | } | |
5134 | } | |
19a622c3 | 5135 | return 0; |
2a5c3a35 SP |
5136 | } |
5137 | ||
0e17a87c SP |
5138 | /** |
5139 | * _base_get_mpi_diag_triggers - get mpi diag trigger values from | |
5140 | * persistent pages | |
5141 | * @ioc : per adapter object | |
5142 | * | |
19a622c3 | 5143 | * Return: 0 on success; otherwise return failure status. |
0e17a87c | 5144 | */ |
19a622c3 | 5145 | static int |
0e17a87c SP |
5146 | _base_get_mpi_diag_triggers(struct MPT3SAS_ADAPTER *ioc) |
5147 | { | |
5148 | Mpi26DriverTriggerPage4_t trigger_pg4; | |
5149 | struct SL_WH_MPI_TRIGGER_T *status_tg; | |
e5035459 | 5150 | MPI26_DRIVER_IOCSTATUS_LOGINFO_TRIGGER_ENTRY *mpi_status_tg; |
0e17a87c SP |
5151 | Mpi2ConfigReply_t mpi_reply; |
5152 | int r = 0, i = 0; | |
5153 | u16 count = 0; | |
5154 | u16 ioc_status; | |
5155 | ||
5156 | r = mpt3sas_config_get_driver_trigger_pg4(ioc, &mpi_reply, | |
5157 | &trigger_pg4); | |
5158 | if (r) | |
19a622c3 | 5159 | return r; |
0e17a87c SP |
5160 | |
5161 | ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & | |
5162 | MPI2_IOCSTATUS_MASK; | |
5163 | if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { | |
5164 | dinitprintk(ioc, | |
5165 | ioc_err(ioc, | |
5166 | "%s: Failed to get trigger pg4, ioc_status(0x%04x)\n", | |
5167 | __func__, ioc_status)); | |
19a622c3 | 5168 | return 0; |
0e17a87c SP |
5169 | } |
5170 | ||
5171 | if (le16_to_cpu(trigger_pg4.NumIOCStatusLogInfoTrigger)) { | |
5172 | count = le16_to_cpu(trigger_pg4.NumIOCStatusLogInfoTrigger); | |
5173 | count = min_t(u16, NUM_VALID_ENTRIES, count); | |
5174 | ioc->diag_trigger_mpi.ValidEntries = count; | |
5175 | ||
5176 | status_tg = &ioc->diag_trigger_mpi.MPITriggerEntry[0]; | |
5177 | mpi_status_tg = &trigger_pg4.IOCStatusLoginfoTriggers[0]; | |
5178 | ||
5179 | for (i = 0; i < count; i++) { | |
5180 | status_tg->IOCStatus = le16_to_cpu( | |
5181 | mpi_status_tg->IOCStatus); | |
5182 | status_tg->IocLogInfo = le32_to_cpu( | |
5183 | mpi_status_tg->LogInfo); | |
5184 | ||
5185 | status_tg++; | |
5186 | mpi_status_tg++; | |
5187 | } | |
5188 | } | |
19a622c3 | 5189 | return 0; |
0e17a87c SP |
5190 | } |
5191 | ||
bb855f2a SP |
5192 | /** |
5193 | * _base_get_master_diag_triggers - get master diag trigger values from | |
5194 | * persistent pages | |
5195 | * @ioc : per adapter object | |
5196 | * | |
2910a4a9 | 5197 | * Return: nothing. |
bb855f2a | 5198 | */ |
19a622c3 | 5199 | static int |
bb855f2a SP |
5200 | _base_get_master_diag_triggers(struct MPT3SAS_ADAPTER *ioc) |
5201 | { | |
5202 | Mpi26DriverTriggerPage1_t trigger_pg1; | |
5203 | Mpi2ConfigReply_t mpi_reply; | |
5204 | int r; | |
5205 | u16 ioc_status; | |
5206 | ||
5207 | r = mpt3sas_config_get_driver_trigger_pg1(ioc, &mpi_reply, | |
5208 | &trigger_pg1); | |
5209 | if (r) | |
19a622c3 | 5210 | return r; |
bb855f2a SP |
5211 | |
5212 | ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & | |
5213 | MPI2_IOCSTATUS_MASK; | |
5214 | if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { | |
5215 | dinitprintk(ioc, | |
5216 | ioc_err(ioc, | |
5217 | "%s: Failed to get trigger pg1, ioc_status(0x%04x)\n", | |
5218 | __func__, ioc_status)); | |
19a622c3 | 5219 | return 0; |
bb855f2a SP |
5220 | } |
5221 | ||
5222 | if (le16_to_cpu(trigger_pg1.NumMasterTrigger)) | |
5223 | ioc->diag_trigger_master.MasterData |= | |
5224 | le32_to_cpu( | |
5225 | trigger_pg1.MasterTriggers[0].MasterTriggerFlags); | |
19a622c3 | 5226 | return 0; |
bb855f2a SP |
5227 | } |
5228 | ||
aec93e8e SP |
5229 | /** |
5230 | * _base_check_for_trigger_pages_support - checks whether HBA FW supports | |
5231 | * driver trigger pages or not | |
5232 | * @ioc : per adapter object | |
19a622c3 SP |
5233 | * @trigger_flags : address where trigger page0's TriggerFlags value is copied |
5234 | * | |
5235 | * Return: trigger flags mask if HBA FW supports driver trigger pages; | |
5236 | * otherwise returns %-EFAULT if driver trigger pages are not supported by FW or | |
5237 | * return EAGAIN if diag reset occurred due to FW fault and asking the | |
5238 | * caller to retry the command. | |
aec93e8e | 5239 | * |
aec93e8e SP |
5240 | */ |
5241 | static int | |
19a622c3 | 5242 | _base_check_for_trigger_pages_support(struct MPT3SAS_ADAPTER *ioc, u32 *trigger_flags) |
aec93e8e SP |
5243 | { |
5244 | Mpi26DriverTriggerPage0_t trigger_pg0; | |
5245 | int r = 0; | |
5246 | Mpi2ConfigReply_t mpi_reply; | |
5247 | u16 ioc_status; | |
5248 | ||
5249 | r = mpt3sas_config_get_driver_trigger_pg0(ioc, &mpi_reply, | |
5250 | &trigger_pg0); | |
5251 | if (r) | |
19a622c3 | 5252 | return r; |
aec93e8e SP |
5253 | |
5254 | ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & | |
5255 | MPI2_IOCSTATUS_MASK; | |
5256 | if (ioc_status != MPI2_IOCSTATUS_SUCCESS) | |
5257 | return -EFAULT; | |
5258 | ||
19a622c3 SP |
5259 | *trigger_flags = le16_to_cpu(trigger_pg0.TriggerFlags); |
5260 | return 0; | |
aec93e8e SP |
5261 | } |
5262 | ||
5263 | /** | |
5264 | * _base_get_diag_triggers - Retrieve diag trigger values from | |
5265 | * persistent pages. | |
5266 | * @ioc : per adapter object | |
5267 | * | |
19a622c3 SP |
5268 | * Return: zero on success; otherwise return EAGAIN error codes |
5269 | * asking the caller to retry. | |
aec93e8e | 5270 | */ |
19a622c3 | 5271 | static int |
aec93e8e SP |
5272 | _base_get_diag_triggers(struct MPT3SAS_ADAPTER *ioc) |
5273 | { | |
8b3c8035 | 5274 | int trigger_flags; |
19a622c3 | 5275 | int r; |
aec93e8e SP |
5276 | |
5277 | /* | |
5278 | * Default setting of master trigger. | |
5279 | */ | |
5280 | ioc->diag_trigger_master.MasterData = | |
5281 | (MASTER_TRIGGER_FW_FAULT + MASTER_TRIGGER_ADAPTER_RESET); | |
bb855f2a | 5282 | |
19a622c3 SP |
5283 | r = _base_check_for_trigger_pages_support(ioc, &trigger_flags); |
5284 | if (r) { | |
5285 | if (r == -EAGAIN) | |
5286 | return r; | |
5287 | /* | |
5288 | * Don't go for error handling when FW doesn't support | |
5289 | * driver trigger pages. | |
5290 | */ | |
5291 | return 0; | |
5292 | } | |
bb855f2a | 5293 | |
aec93e8e | 5294 | ioc->supports_trigger_pages = 1; |
bb855f2a SP |
5295 | |
5296 | /* | |
5297 | * Retrieve master diag trigger values from driver trigger pg1 | |
5298 | * if master trigger bit enabled in TriggerFlags. | |
5299 | */ | |
5300 | if ((u16)trigger_flags & | |
19a622c3 SP |
5301 | MPI26_DRIVER_TRIGGER0_FLAG_MASTER_TRIGGER_VALID) { |
5302 | r = _base_get_master_diag_triggers(ioc); | |
5303 | if (r) | |
5304 | return r; | |
5305 | } | |
71b3fb8f SP |
5306 | |
5307 | /* | |
5308 | * Retrieve event diag trigger values from driver trigger pg2 | |
5309 | * if event trigger bit enabled in TriggerFlags. | |
5310 | */ | |
5311 | if ((u16)trigger_flags & | |
19a622c3 SP |
5312 | MPI26_DRIVER_TRIGGER0_FLAG_MPI_EVENT_TRIGGER_VALID) { |
5313 | r = _base_get_event_diag_triggers(ioc); | |
5314 | if (r) | |
5315 | return r; | |
5316 | } | |
71b3fb8f | 5317 | |
2a5c3a35 SP |
5318 | /* |
5319 | * Retrieve scsi diag trigger values from driver trigger pg3 | |
5320 | * if scsi trigger bit enabled in TriggerFlags. | |
5321 | */ | |
5322 | if ((u16)trigger_flags & | |
19a622c3 SP |
5323 | MPI26_DRIVER_TRIGGER0_FLAG_SCSI_SENSE_TRIGGER_VALID) { |
5324 | r = _base_get_scsi_diag_triggers(ioc); | |
5325 | if (r) | |
5326 | return r; | |
5327 | } | |
0e17a87c SP |
5328 | /* |
5329 | * Retrieve mpi error diag trigger values from driver trigger pg4 | |
5330 | * if loginfo trigger bit enabled in TriggerFlags. | |
5331 | */ | |
5332 | if ((u16)trigger_flags & | |
19a622c3 SP |
5333 | MPI26_DRIVER_TRIGGER0_FLAG_LOGINFO_TRIGGER_VALID) { |
5334 | r = _base_get_mpi_diag_triggers(ioc); | |
5335 | if (r) | |
5336 | return r; | |
5337 | } | |
5338 | return 0; | |
aec93e8e SP |
5339 | } |
5340 | ||
9b271c69 SP |
5341 | /** |
5342 | * _base_update_diag_trigger_pages - Update the driver trigger pages after | |
2910a4a9 | 5343 | * online FW update, in case updated FW supports driver |
9b271c69 SP |
5344 | * trigger pages. |
5345 | * @ioc : per adapter object | |
5346 | * | |
2910a4a9 | 5347 | * Return: nothing. |
9b271c69 SP |
5348 | */ |
5349 | static void | |
5350 | _base_update_diag_trigger_pages(struct MPT3SAS_ADAPTER *ioc) | |
5351 | { | |
5352 | ||
5353 | if (ioc->diag_trigger_master.MasterData) | |
5354 | mpt3sas_config_update_driver_trigger_pg1(ioc, | |
5355 | &ioc->diag_trigger_master, 1); | |
5356 | ||
5357 | if (ioc->diag_trigger_event.ValidEntries) | |
5358 | mpt3sas_config_update_driver_trigger_pg2(ioc, | |
5359 | &ioc->diag_trigger_event, 1); | |
5360 | ||
5361 | if (ioc->diag_trigger_scsi.ValidEntries) | |
5362 | mpt3sas_config_update_driver_trigger_pg3(ioc, | |
5363 | &ioc->diag_trigger_scsi, 1); | |
5364 | ||
5365 | if (ioc->diag_trigger_mpi.ValidEntries) | |
5366 | mpt3sas_config_update_driver_trigger_pg4(ioc, | |
5367 | &ioc->diag_trigger_mpi, 1); | |
5368 | } | |
5369 | ||
787f2448 SP |
5370 | /** |
5371 | * _base_assign_fw_reported_qd - Get FW reported QD for SAS/SATA devices. | |
5372 | * - On failure set default QD values. | |
5373 | * @ioc : per adapter object | |
5374 | * | |
5375 | * Returns 0 for success, non-zero for failure. | |
5376 | * | |
5377 | */ | |
5378 | static int _base_assign_fw_reported_qd(struct MPT3SAS_ADAPTER *ioc) | |
5379 | { | |
5380 | Mpi2ConfigReply_t mpi_reply; | |
dde41e0c | 5381 | Mpi2SasIOUnitPage1_t sas_iounit_pg1; |
787f2448 | 5382 | Mpi26PCIeIOUnitPage1_t pcie_iounit_pg1; |
120f1d95 | 5383 | u16 depth; |
787f2448 SP |
5384 | int rc = 0; |
5385 | ||
5386 | ioc->max_wideport_qd = MPT3SAS_SAS_QUEUE_DEPTH; | |
5387 | ioc->max_narrowport_qd = MPT3SAS_SAS_QUEUE_DEPTH; | |
5388 | ioc->max_sata_qd = MPT3SAS_SATA_QUEUE_DEPTH; | |
5389 | ioc->max_nvme_qd = MPT3SAS_NVME_QUEUE_DEPTH; | |
5390 | if (!ioc->is_gen35_ioc) | |
5391 | goto out; | |
5392 | /* sas iounit page 1 */ | |
787f2448 | 5393 | rc = mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply, |
dde41e0c | 5394 | &sas_iounit_pg1, sizeof(Mpi2SasIOUnitPage1_t)); |
787f2448 SP |
5395 | if (rc) { |
5396 | pr_err("%s: failure at %s:%d/%s()!\n", | |
5397 | ioc->name, __FILE__, __LINE__, __func__); | |
5398 | goto out; | |
5399 | } | |
120f1d95 | 5400 | |
dde41e0c | 5401 | depth = le16_to_cpu(sas_iounit_pg1.SASWideMaxQueueDepth); |
120f1d95 HD |
5402 | ioc->max_wideport_qd = (depth ? depth : MPT3SAS_SAS_QUEUE_DEPTH); |
5403 | ||
dde41e0c | 5404 | depth = le16_to_cpu(sas_iounit_pg1.SASNarrowMaxQueueDepth); |
120f1d95 HD |
5405 | ioc->max_narrowport_qd = (depth ? depth : MPT3SAS_SAS_QUEUE_DEPTH); |
5406 | ||
dde41e0c | 5407 | depth = sas_iounit_pg1.SATAMaxQDepth; |
120f1d95 HD |
5408 | ioc->max_sata_qd = (depth ? depth : MPT3SAS_SATA_QUEUE_DEPTH); |
5409 | ||
787f2448 SP |
5410 | /* pcie iounit page 1 */ |
5411 | rc = mpt3sas_config_get_pcie_iounit_pg1(ioc, &mpi_reply, | |
5412 | &pcie_iounit_pg1, sizeof(Mpi26PCIeIOUnitPage1_t)); | |
5413 | if (rc) { | |
5414 | pr_err("%s: failure at %s:%d/%s()!\n", | |
5415 | ioc->name, __FILE__, __LINE__, __func__); | |
5416 | goto out; | |
5417 | } | |
5418 | ioc->max_nvme_qd = (le16_to_cpu(pcie_iounit_pg1.NVMeMaxQueueDepth)) ? | |
5419 | (le16_to_cpu(pcie_iounit_pg1.NVMeMaxQueueDepth)) : | |
5420 | MPT3SAS_NVME_QUEUE_DEPTH; | |
5421 | out: | |
5422 | dinitprintk(ioc, pr_err( | |
5423 | "MaxWidePortQD: 0x%x MaxNarrowPortQD: 0x%x MaxSataQD: 0x%x MaxNvmeQD: 0x%x\n", | |
5424 | ioc->max_wideport_qd, ioc->max_narrowport_qd, | |
5425 | ioc->max_sata_qd, ioc->max_nvme_qd)); | |
787f2448 SP |
5426 | return rc; |
5427 | } | |
5428 | ||
91cf186a BG |
5429 | /** |
5430 | * mpt3sas_atto_validate_nvram - validate the ATTO nvram read from mfg pg1 | |
5431 | * | |
5432 | * @ioc : per adapter object | |
5433 | * @n : ptr to the ATTO nvram structure | |
5434 | * Return: 0 for success, non-zero for failure. | |
5435 | */ | |
5436 | static int | |
5437 | mpt3sas_atto_validate_nvram(struct MPT3SAS_ADAPTER *ioc, | |
5438 | struct ATTO_SAS_NVRAM *n) | |
5439 | { | |
5440 | int r = -EINVAL; | |
5441 | union ATTO_SAS_ADDRESS *s1; | |
5442 | u32 len; | |
5443 | u8 *pb; | |
5444 | u8 ckSum; | |
5445 | ||
5446 | /* validate nvram checksum */ | |
5447 | pb = (u8 *) n; | |
5448 | ckSum = ATTO_SASNVR_CKSUM_SEED; | |
5449 | len = sizeof(struct ATTO_SAS_NVRAM); | |
5450 | ||
5451 | while (len--) | |
5452 | ckSum = ckSum + pb[len]; | |
5453 | ||
5454 | if (ckSum) { | |
5455 | ioc_err(ioc, "Invalid ATTO NVRAM checksum\n"); | |
5456 | return r; | |
5457 | } | |
5458 | ||
5459 | s1 = (union ATTO_SAS_ADDRESS *) n->SasAddr; | |
5460 | ||
5461 | if (n->Signature[0] != 'E' | |
5462 | || n->Signature[1] != 'S' | |
5463 | || n->Signature[2] != 'A' | |
5464 | || n->Signature[3] != 'S') | |
5465 | ioc_err(ioc, "Invalid ATTO NVRAM signature\n"); | |
5466 | else if (n->Version > ATTO_SASNVR_VERSION) | |
5467 | ioc_info(ioc, "Invalid ATTO NVRAM version"); | |
5468 | else if ((n->SasAddr[7] & (ATTO_SAS_ADDR_ALIGN - 1)) | |
5469 | || s1->b[0] != 0x50 | |
5470 | || s1->b[1] != 0x01 | |
5471 | || s1->b[2] != 0x08 | |
5472 | || (s1->b[3] & 0xF0) != 0x60 | |
5473 | || ((s1->b[3] & 0x0F) | le32_to_cpu(s1->d[1])) == 0) { | |
5474 | ioc_err(ioc, "Invalid ATTO SAS address\n"); | |
5475 | } else | |
5476 | r = 0; | |
5477 | return r; | |
5478 | } | |
5479 | ||
5480 | /** | |
5481 | * mpt3sas_atto_get_sas_addr - get the ATTO SAS address from mfg page 1 | |
5482 | * | |
5483 | * @ioc : per adapter object | |
5484 | * @*sas_addr : return sas address | |
5485 | * Return: 0 for success, non-zero for failure. | |
5486 | */ | |
5487 | static int | |
5488 | mpt3sas_atto_get_sas_addr(struct MPT3SAS_ADAPTER *ioc, union ATTO_SAS_ADDRESS *sas_addr) | |
5489 | { | |
5490 | Mpi2ManufacturingPage1_t mfg_pg1; | |
5491 | Mpi2ConfigReply_t mpi_reply; | |
5492 | struct ATTO_SAS_NVRAM *nvram; | |
5493 | int r; | |
5494 | __be64 addr; | |
5495 | ||
5496 | r = mpt3sas_config_get_manufacturing_pg1(ioc, &mpi_reply, &mfg_pg1); | |
5497 | if (r) { | |
5498 | ioc_err(ioc, "Failed to read manufacturing page 1\n"); | |
5499 | return r; | |
5500 | } | |
5501 | ||
5502 | /* validate nvram */ | |
5503 | nvram = (struct ATTO_SAS_NVRAM *) mfg_pg1.VPD; | |
5504 | r = mpt3sas_atto_validate_nvram(ioc, nvram); | |
5505 | if (r) | |
5506 | return r; | |
5507 | ||
5508 | addr = *((__be64 *) nvram->SasAddr); | |
5509 | sas_addr->q = cpu_to_le64(be64_to_cpu(addr)); | |
5510 | return r; | |
5511 | } | |
5512 | ||
5513 | /** | |
5514 | * mpt3sas_atto_init - perform initializaion for ATTO branded | |
5515 | * adapter. | |
5516 | * @ioc : per adapter object | |
5517 | *5 | |
5518 | * Return: 0 for success, non-zero for failure. | |
5519 | */ | |
5520 | static int | |
5521 | mpt3sas_atto_init(struct MPT3SAS_ADAPTER *ioc) | |
5522 | { | |
5523 | int sz = 0; | |
5524 | Mpi2BiosPage4_t *bios_pg4 = NULL; | |
5525 | Mpi2ConfigReply_t mpi_reply; | |
5526 | int r; | |
5527 | int ix; | |
5528 | union ATTO_SAS_ADDRESS sas_addr; | |
5529 | union ATTO_SAS_ADDRESS temp; | |
5530 | union ATTO_SAS_ADDRESS bias; | |
5531 | ||
5532 | r = mpt3sas_atto_get_sas_addr(ioc, &sas_addr); | |
5533 | if (r) | |
5534 | return r; | |
5535 | ||
5536 | /* get header first to get size */ | |
5537 | r = mpt3sas_config_get_bios_pg4(ioc, &mpi_reply, NULL, 0); | |
5538 | if (r) { | |
5539 | ioc_err(ioc, "Failed to read ATTO bios page 4 header.\n"); | |
5540 | return r; | |
5541 | } | |
5542 | ||
5543 | sz = mpi_reply.Header.PageLength * sizeof(u32); | |
5544 | bios_pg4 = kzalloc(sz, GFP_KERNEL); | |
5545 | if (!bios_pg4) { | |
5546 | ioc_err(ioc, "Failed to allocate memory for ATTO bios page.\n"); | |
5547 | return -ENOMEM; | |
5548 | } | |
5549 | ||
5550 | /* read bios page 4 */ | |
5551 | r = mpt3sas_config_get_bios_pg4(ioc, &mpi_reply, bios_pg4, sz); | |
5552 | if (r) { | |
5553 | ioc_err(ioc, "Failed to read ATTO bios page 4\n"); | |
5554 | goto out; | |
5555 | } | |
5556 | ||
5557 | /* Update bios page 4 with the ATTO WWID */ | |
5558 | bias.q = sas_addr.q; | |
5559 | bias.b[7] += ATTO_SAS_ADDR_DEVNAME_BIAS; | |
5560 | ||
5561 | for (ix = 0; ix < bios_pg4->NumPhys; ix++) { | |
5562 | temp.q = sas_addr.q; | |
5563 | temp.b[7] += ix; | |
5564 | bios_pg4->Phy[ix].ReassignmentWWID = temp.q; | |
5565 | bios_pg4->Phy[ix].ReassignmentDeviceName = bias.q; | |
5566 | } | |
5567 | r = mpt3sas_config_set_bios_pg4(ioc, &mpi_reply, bios_pg4, sz); | |
5568 | ||
5569 | out: | |
5570 | kfree(bios_pg4); | |
5571 | return r; | |
5572 | } | |
5573 | ||
f92363d1 SR |
5574 | /** |
5575 | * _base_static_config_pages - static start of day config pages | |
5576 | * @ioc: per adapter object | |
f92363d1 | 5577 | */ |
19a622c3 | 5578 | static int |
f92363d1 SR |
5579 | _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc) |
5580 | { | |
66f2a53f | 5581 | Mpi2IOUnitPage8_t iounit_pg8; |
f92363d1 SR |
5582 | Mpi2ConfigReply_t mpi_reply; |
5583 | u32 iounit_pg1_flags; | |
9b271c69 | 5584 | int tg_flags = 0; |
19a622c3 | 5585 | int rc; |
c1a6c5ac | 5586 | ioc->nvme_abort_timeout = 30; |
f92363d1 | 5587 | |
19a622c3 SP |
5588 | rc = mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, |
5589 | &ioc->manu_pg0); | |
5590 | if (rc) | |
5591 | return rc; | |
5592 | if (ioc->ir_firmware) { | |
5593 | rc = mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply, | |
5594 | &ioc->manu_pg10); | |
5595 | if (rc) | |
5596 | return rc; | |
5597 | } | |
91cf186a BG |
5598 | |
5599 | if (ioc->pdev->vendor == MPI2_MFGPAGE_VENDORID_ATTO) { | |
5600 | rc = mpt3sas_atto_init(ioc); | |
5601 | if (rc) | |
5602 | return rc; | |
5603 | } | |
5604 | ||
f92363d1 SR |
5605 | /* |
5606 | * Ensure correct T10 PI operation if vendor left EEDPTagMode | |
5607 | * flag unset in NVDATA. | |
5608 | */ | |
19a622c3 SP |
5609 | rc = mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, |
5610 | &ioc->manu_pg11); | |
5611 | if (rc) | |
5612 | return rc; | |
6cd1bc7b | 5613 | if (!ioc->is_gen35_ioc && ioc->manu_pg11.EEDPTagMode == 0) { |
f92363d1 SR |
5614 | pr_err("%s: overriding NVDATA EEDPTagMode setting\n", |
5615 | ioc->name); | |
5616 | ioc->manu_pg11.EEDPTagMode &= ~0x3; | |
5617 | ioc->manu_pg11.EEDPTagMode |= 0x1; | |
5618 | mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply, | |
5619 | &ioc->manu_pg11); | |
5620 | } | |
c1a6c5ac C |
5621 | if (ioc->manu_pg11.AddlFlags2 & NVME_TASK_MNGT_CUSTOM_MASK) |
5622 | ioc->tm_custom_handling = 1; | |
5623 | else { | |
5624 | ioc->tm_custom_handling = 0; | |
5625 | if (ioc->manu_pg11.NVMeAbortTO < NVME_TASK_ABORT_MIN_TIMEOUT) | |
5626 | ioc->nvme_abort_timeout = NVME_TASK_ABORT_MIN_TIMEOUT; | |
5627 | else if (ioc->manu_pg11.NVMeAbortTO > | |
5628 | NVME_TASK_ABORT_MAX_TIMEOUT) | |
5629 | ioc->nvme_abort_timeout = NVME_TASK_ABORT_MAX_TIMEOUT; | |
5630 | else | |
5631 | ioc->nvme_abort_timeout = ioc->manu_pg11.NVMeAbortTO; | |
5632 | } | |
f98790c0 SP |
5633 | ioc->time_sync_interval = |
5634 | ioc->manu_pg11.TimeSyncInterval & MPT3SAS_TIMESYNC_MASK; | |
5635 | if (ioc->time_sync_interval) { | |
5636 | if (ioc->manu_pg11.TimeSyncInterval & MPT3SAS_TIMESYNC_UNIT_MASK) | |
5637 | ioc->time_sync_interval = | |
5638 | ioc->time_sync_interval * SECONDS_PER_HOUR; | |
5639 | else | |
5640 | ioc->time_sync_interval = | |
5641 | ioc->time_sync_interval * SECONDS_PER_MIN; | |
5642 | dinitprintk(ioc, ioc_info(ioc, | |
5643 | "Driver-FW TimeSync interval is %d seconds. ManuPg11 TimeSync Unit is in %s\n", | |
5644 | ioc->time_sync_interval, (ioc->manu_pg11.TimeSyncInterval & | |
5645 | MPT3SAS_TIMESYNC_UNIT_MASK) ? "Hour" : "Minute")); | |
5646 | } else { | |
5647 | if (ioc->is_gen35_ioc) | |
5648 | ioc_warn(ioc, | |
5649 | "TimeSync Interval in Manuf page-11 is not enabled. Periodic Time-Sync will be disabled\n"); | |
5650 | } | |
787f2448 SP |
5651 | rc = _base_assign_fw_reported_qd(ioc); |
5652 | if (rc) | |
5653 | return rc; | |
91cf186a BG |
5654 | |
5655 | /* | |
5656 | * ATTO doesn't use bios page 2 and 3 for bios settings. | |
5657 | */ | |
5658 | if (ioc->pdev->vendor == MPI2_MFGPAGE_VENDORID_ATTO) | |
5659 | ioc->bios_pg3.BiosVersion = 0; | |
5660 | else { | |
5661 | rc = mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2); | |
5662 | if (rc) | |
5663 | return rc; | |
5664 | rc = mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3); | |
5665 | if (rc) | |
5666 | return rc; | |
5667 | } | |
5668 | ||
19a622c3 SP |
5669 | rc = mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8); |
5670 | if (rc) | |
5671 | return rc; | |
5672 | rc = mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0); | |
5673 | if (rc) | |
5674 | return rc; | |
5675 | rc = mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); | |
5676 | if (rc) | |
5677 | return rc; | |
66f2a53f | 5678 | rc = mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &iounit_pg8); |
19a622c3 SP |
5679 | if (rc) |
5680 | return rc; | |
f92363d1 SR |
5681 | _base_display_ioc_capabilities(ioc); |
5682 | ||
5683 | /* | |
5684 | * Enable task_set_full handling in iounit_pg1 when the | |
5685 | * facts capabilities indicate that its supported. | |
5686 | */ | |
5687 | iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); | |
5688 | if ((ioc->facts.IOCCapabilities & | |
5689 | MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING)) | |
5690 | iounit_pg1_flags &= | |
5691 | ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; | |
5692 | else | |
5693 | iounit_pg1_flags |= | |
5694 | MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; | |
5695 | ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags); | |
19a622c3 SP |
5696 | rc = mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); |
5697 | if (rc) | |
5698 | return rc; | |
2d8ce8c9 | 5699 | |
66f2a53f JS |
5700 | if (iounit_pg8.NumSensors) |
5701 | ioc->temp_sensors_count = iounit_pg8.NumSensors; | |
19a622c3 SP |
5702 | if (ioc->is_aero_ioc) { |
5703 | rc = _base_update_ioc_page1_inlinewith_perf_mode(ioc); | |
5704 | if (rc) | |
5705 | return rc; | |
5706 | } | |
aec93e8e | 5707 | if (ioc->is_gen35_ioc) { |
19a622c3 SP |
5708 | if (ioc->is_driver_loading) { |
5709 | rc = _base_get_diag_triggers(ioc); | |
5710 | if (rc) | |
5711 | return rc; | |
5712 | } else { | |
9b271c69 SP |
5713 | /* |
5714 | * In case of online HBA FW update operation, | |
5715 | * check whether updated FW supports the driver trigger | |
5716 | * pages or not. | |
5717 | * - If previous FW has not supported driver trigger | |
5718 | * pages and newer FW supports them then update these | |
5719 | * pages with current diag trigger values. | |
5720 | * - If previous FW has supported driver trigger pages | |
5721 | * and new FW doesn't support them then disable | |
5722 | * support_trigger_pages flag. | |
5723 | */ | |
19a622c3 | 5724 | _base_check_for_trigger_pages_support(ioc, &tg_flags); |
9b271c69 SP |
5725 | if (!ioc->supports_trigger_pages && tg_flags != -EFAULT) |
5726 | _base_update_diag_trigger_pages(ioc); | |
5727 | else if (ioc->supports_trigger_pages && | |
5728 | tg_flags == -EFAULT) | |
5729 | ioc->supports_trigger_pages = 0; | |
5730 | } | |
aec93e8e | 5731 | } |
19a622c3 | 5732 | return 0; |
f92363d1 SR |
5733 | } |
5734 | ||
22a923c3 C |
5735 | /** |
5736 | * mpt3sas_free_enclosure_list - release memory | |
5737 | * @ioc: per adapter object | |
5738 | * | |
206a3afa | 5739 | * Free memory allocated during enclosure add. |
22a923c3 C |
5740 | */ |
5741 | void | |
5742 | mpt3sas_free_enclosure_list(struct MPT3SAS_ADAPTER *ioc) | |
5743 | { | |
5744 | struct _enclosure_node *enclosure_dev, *enclosure_dev_next; | |
5745 | ||
5746 | /* Free enclosure list */ | |
5747 | list_for_each_entry_safe(enclosure_dev, | |
5748 | enclosure_dev_next, &ioc->enclosure_list, list) { | |
5749 | list_del(&enclosure_dev->list); | |
5750 | kfree(enclosure_dev); | |
5751 | } | |
5752 | } | |
5753 | ||
f92363d1 SR |
5754 | /** |
5755 | * _base_release_memory_pools - release memory | |
5756 | * @ioc: per adapter object | |
5757 | * | |
5758 | * Free memory allocated from _base_allocate_memory_pools. | |
f92363d1 SR |
5759 | */ |
5760 | static void | |
5761 | _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) | |
5762 | { | |
9b05c91a | 5763 | int i = 0; |
93204b78 | 5764 | int j = 0; |
8012209e | 5765 | int dma_alloc_count = 0; |
93204b78 | 5766 | struct chain_tracker *ct; |
f56577e8 | 5767 | int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1; |
f92363d1 | 5768 | |
919d8a3f | 5769 | dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); |
f92363d1 SR |
5770 | |
5771 | if (ioc->request) { | |
1c2048bd | 5772 | dma_free_coherent(&ioc->pdev->dev, ioc->request_dma_sz, |
f92363d1 | 5773 | ioc->request, ioc->request_dma); |
919d8a3f JP |
5774 | dexitprintk(ioc, |
5775 | ioc_info(ioc, "request_pool(0x%p): free\n", | |
5776 | ioc->request)); | |
f92363d1 SR |
5777 | ioc->request = NULL; |
5778 | } | |
5779 | ||
5780 | if (ioc->sense) { | |
e9d98418 RP |
5781 | dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma); |
5782 | dma_pool_destroy(ioc->sense_dma_pool); | |
919d8a3f JP |
5783 | dexitprintk(ioc, |
5784 | ioc_info(ioc, "sense_pool(0x%p): free\n", | |
5785 | ioc->sense)); | |
f92363d1 SR |
5786 | ioc->sense = NULL; |
5787 | } | |
5788 | ||
5789 | if (ioc->reply) { | |
e9d98418 RP |
5790 | dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma); |
5791 | dma_pool_destroy(ioc->reply_dma_pool); | |
919d8a3f JP |
5792 | dexitprintk(ioc, |
5793 | ioc_info(ioc, "reply_pool(0x%p): free\n", | |
5794 | ioc->reply)); | |
f92363d1 SR |
5795 | ioc->reply = NULL; |
5796 | } | |
5797 | ||
5798 | if (ioc->reply_free) { | |
e9d98418 | 5799 | dma_pool_free(ioc->reply_free_dma_pool, ioc->reply_free, |
f92363d1 | 5800 | ioc->reply_free_dma); |
e9d98418 | 5801 | dma_pool_destroy(ioc->reply_free_dma_pool); |
919d8a3f JP |
5802 | dexitprintk(ioc, |
5803 | ioc_info(ioc, "reply_free_pool(0x%p): free\n", | |
5804 | ioc->reply_free)); | |
f92363d1 SR |
5805 | ioc->reply_free = NULL; |
5806 | } | |
5807 | ||
9b05c91a | 5808 | if (ioc->reply_post) { |
f56577e8 | 5809 | dma_alloc_count = DIV_ROUND_UP(count, |
8012209e | 5810 | RDPQ_MAX_INDEX_IN_ONE_CHUNK); |
f56577e8 | 5811 | for (i = 0; i < count; i++) { |
8012209e SP |
5812 | if (i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0 |
5813 | && dma_alloc_count) { | |
5814 | if (ioc->reply_post[i].reply_post_free) { | |
5815 | dma_pool_free( | |
5816 | ioc->reply_post_free_dma_pool, | |
5817 | ioc->reply_post[i].reply_post_free, | |
5818 | ioc->reply_post[i].reply_post_free_dma); | |
5819 | dexitprintk(ioc, ioc_info(ioc, | |
5820 | "reply_post_free_pool(0x%p): free\n", | |
5821 | ioc->reply_post[i].reply_post_free)); | |
5822 | ioc->reply_post[i].reply_post_free = | |
5823 | NULL; | |
5824 | } | |
5825 | --dma_alloc_count; | |
9b05c91a | 5826 | } |
8012209e SP |
5827 | } |
5828 | dma_pool_destroy(ioc->reply_post_free_dma_pool); | |
cd33223b C |
5829 | if (ioc->reply_post_free_array && |
5830 | ioc->rdpq_array_enable) { | |
5831 | dma_pool_free(ioc->reply_post_free_array_dma_pool, | |
8012209e SP |
5832 | ioc->reply_post_free_array, |
5833 | ioc->reply_post_free_array_dma); | |
cd33223b C |
5834 | ioc->reply_post_free_array = NULL; |
5835 | } | |
5836 | dma_pool_destroy(ioc->reply_post_free_array_dma_pool); | |
9b05c91a | 5837 | kfree(ioc->reply_post); |
f92363d1 SR |
5838 | } |
5839 | ||
016d5c35 SPS |
5840 | if (ioc->pcie_sgl_dma_pool) { |
5841 | for (i = 0; i < ioc->scsiio_depth; i++) { | |
dbec4c90 SPS |
5842 | dma_pool_free(ioc->pcie_sgl_dma_pool, |
5843 | ioc->pcie_sg_lookup[i].pcie_sgl, | |
5844 | ioc->pcie_sg_lookup[i].pcie_sgl_dma); | |
d6adc251 | 5845 | ioc->pcie_sg_lookup[i].pcie_sgl = NULL; |
016d5c35 | 5846 | } |
baf3fbf2 | 5847 | dma_pool_destroy(ioc->pcie_sgl_dma_pool); |
016d5c35 | 5848 | } |
54dd9601 TH |
5849 | kfree(ioc->pcie_sg_lookup); |
5850 | ioc->pcie_sg_lookup = NULL; | |
5851 | ||
f92363d1 | 5852 | if (ioc->config_page) { |
919d8a3f JP |
5853 | dexitprintk(ioc, |
5854 | ioc_info(ioc, "config_page(0x%p): free\n", | |
5855 | ioc->config_page)); | |
1c2048bd | 5856 | dma_free_coherent(&ioc->pdev->dev, ioc->config_page_sz, |
f92363d1 SR |
5857 | ioc->config_page, ioc->config_page_dma); |
5858 | } | |
5859 | ||
f92363d1 | 5860 | kfree(ioc->hpr_lookup); |
cbbfdb2a | 5861 | ioc->hpr_lookup = NULL; |
f92363d1 | 5862 | kfree(ioc->internal_lookup); |
cbbfdb2a | 5863 | ioc->internal_lookup = NULL; |
f92363d1 | 5864 | if (ioc->chain_lookup) { |
93204b78 | 5865 | for (i = 0; i < ioc->scsiio_depth; i++) { |
74522a92 C |
5866 | for (j = ioc->chains_per_prp_buffer; |
5867 | j < ioc->chains_needed_per_io; j++) { | |
93204b78 C |
5868 | ct = &ioc->chain_lookup[i].chains_per_smid[j]; |
5869 | if (ct && ct->chain_buffer) | |
5870 | dma_pool_free(ioc->chain_dma_pool, | |
5871 | ct->chain_buffer, | |
5872 | ct->chain_buffer_dma); | |
5873 | } | |
5874 | kfree(ioc->chain_lookup[i].chains_per_smid); | |
f92363d1 | 5875 | } |
e9d98418 | 5876 | dma_pool_destroy(ioc->chain_dma_pool); |
93204b78 | 5877 | kfree(ioc->chain_lookup); |
f92363d1 SR |
5878 | ioc->chain_lookup = NULL; |
5879 | } | |
664f0dce SR |
5880 | |
5881 | kfree(ioc->io_queue_num); | |
5882 | ioc->io_queue_num = NULL; | |
f92363d1 SR |
5883 | } |
5884 | ||
e21fef6f | 5885 | /** |
550dc875 | 5886 | * mpt3sas_check_same_4gb_region - checks whether all reply queues in a set are |
e21fef6f | 5887 | * having same upper 32bits in their base memory address. |
6eaa7714 | 5888 | * @start_address: Base address of a reply queue set |
e21fef6f C |
5889 | * @pool_sz: Size of single Reply Descriptor Post Queues pool size |
5890 | * | |
4beb4867 BVA |
5891 | * Return: 1 if reply queues in a set have a same upper 32bits in their base |
5892 | * memory address, else 0. | |
e21fef6f | 5893 | */ |
e21fef6f | 5894 | static int |
208cc9fe | 5895 | mpt3sas_check_same_4gb_region(dma_addr_t start_address, u32 pool_sz) |
e21fef6f | 5896 | { |
208cc9fe | 5897 | dma_addr_t end_address; |
e21fef6f | 5898 | |
208cc9fe | 5899 | end_address = start_address + pool_sz - 1; |
e21fef6f | 5900 | |
208cc9fe | 5901 | if (upper_32_bits(start_address) == upper_32_bits(end_address)) |
e21fef6f C |
5902 | return 1; |
5903 | else | |
5904 | return 0; | |
5905 | } | |
5906 | ||
d6adc251 SP |
5907 | /** |
5908 | * _base_reduce_hba_queue_depth- Retry with reduced queue depth | |
5909 | * @ioc: Adapter object | |
5910 | * | |
5911 | * Return: 0 for success, non-zero for failure. | |
5912 | **/ | |
5913 | static inline int | |
5914 | _base_reduce_hba_queue_depth(struct MPT3SAS_ADAPTER *ioc) | |
5915 | { | |
5916 | int reduce_sz = 64; | |
5917 | ||
5918 | if ((ioc->hba_queue_depth - reduce_sz) > | |
5919 | (ioc->internal_depth + INTERNAL_SCSIIO_CMDS_COUNT)) { | |
5920 | ioc->hba_queue_depth -= reduce_sz; | |
5921 | return 0; | |
5922 | } else | |
5923 | return -ENOMEM; | |
5924 | } | |
5925 | ||
5926 | /** | |
5927 | * _base_allocate_pcie_sgl_pool - Allocating DMA'able memory | |
5928 | * for pcie sgl pools. | |
5929 | * @ioc: Adapter object | |
5930 | * @sz: DMA Pool size | |
3ad0b1da | 5931 | * |
d6adc251 SP |
5932 | * Return: 0 for success, non-zero for failure. |
5933 | */ | |
5934 | ||
5935 | static int | |
5936 | _base_allocate_pcie_sgl_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz) | |
5937 | { | |
5938 | int i = 0, j = 0; | |
5939 | struct chain_tracker *ct; | |
5940 | ||
5941 | ioc->pcie_sgl_dma_pool = | |
5942 | dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz, | |
5943 | ioc->page_size, 0); | |
5944 | if (!ioc->pcie_sgl_dma_pool) { | |
5945 | ioc_err(ioc, "PCIe SGL pool: dma_pool_create failed\n"); | |
5946 | return -ENOMEM; | |
5947 | } | |
5948 | ||
5949 | ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz; | |
5950 | ioc->chains_per_prp_buffer = | |
5951 | min(ioc->chains_per_prp_buffer, ioc->chains_needed_per_io); | |
5952 | for (i = 0; i < ioc->scsiio_depth; i++) { | |
5953 | ioc->pcie_sg_lookup[i].pcie_sgl = | |
5954 | dma_pool_alloc(ioc->pcie_sgl_dma_pool, GFP_KERNEL, | |
5955 | &ioc->pcie_sg_lookup[i].pcie_sgl_dma); | |
5956 | if (!ioc->pcie_sg_lookup[i].pcie_sgl) { | |
5957 | ioc_err(ioc, "PCIe SGL pool: dma_pool_alloc failed\n"); | |
5958 | return -EAGAIN; | |
5959 | } | |
5960 | ||
5961 | if (!mpt3sas_check_same_4gb_region( | |
208cc9fe | 5962 | ioc->pcie_sg_lookup[i].pcie_sgl_dma, sz)) { |
d6adc251 SP |
5963 | ioc_err(ioc, "PCIE SGLs are not in same 4G !! pcie sgl (0x%p) dma = (0x%llx)\n", |
5964 | ioc->pcie_sg_lookup[i].pcie_sgl, | |
5965 | (unsigned long long) | |
5966 | ioc->pcie_sg_lookup[i].pcie_sgl_dma); | |
5967 | ioc->use_32bit_dma = true; | |
5968 | return -EAGAIN; | |
5969 | } | |
5970 | ||
5971 | for (j = 0; j < ioc->chains_per_prp_buffer; j++) { | |
5972 | ct = &ioc->chain_lookup[i].chains_per_smid[j]; | |
5973 | ct->chain_buffer = | |
5974 | ioc->pcie_sg_lookup[i].pcie_sgl + | |
5975 | (j * ioc->chain_segment_sz); | |
5976 | ct->chain_buffer_dma = | |
5977 | ioc->pcie_sg_lookup[i].pcie_sgl_dma + | |
5978 | (j * ioc->chain_segment_sz); | |
5979 | } | |
5980 | } | |
5981 | dinitprintk(ioc, ioc_info(ioc, | |
5982 | "PCIe sgl pool depth(%d), element_size(%d), pool_size(%d kB)\n", | |
5983 | ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024)); | |
5984 | dinitprintk(ioc, ioc_info(ioc, | |
5985 | "Number of chains can fit in a PRP page(%d)\n", | |
5986 | ioc->chains_per_prp_buffer)); | |
5987 | return 0; | |
5988 | } | |
5989 | ||
7dd847da SP |
5990 | /** |
5991 | * _base_allocate_chain_dma_pool - Allocating DMA'able memory | |
5992 | * for chain dma pool. | |
5993 | * @ioc: Adapter object | |
5994 | * @sz: DMA Pool size | |
3ad0b1da | 5995 | * |
7dd847da SP |
5996 | * Return: 0 for success, non-zero for failure. |
5997 | */ | |
5998 | static int | |
5999 | _base_allocate_chain_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz) | |
6000 | { | |
6001 | int i = 0, j = 0; | |
6002 | struct chain_tracker *ctr; | |
6003 | ||
6004 | ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev, | |
6005 | ioc->chain_segment_sz, 16, 0); | |
6006 | if (!ioc->chain_dma_pool) | |
6007 | return -ENOMEM; | |
6008 | ||
6009 | for (i = 0; i < ioc->scsiio_depth; i++) { | |
6010 | for (j = ioc->chains_per_prp_buffer; | |
6011 | j < ioc->chains_needed_per_io; j++) { | |
6012 | ctr = &ioc->chain_lookup[i].chains_per_smid[j]; | |
6013 | ctr->chain_buffer = dma_pool_alloc(ioc->chain_dma_pool, | |
6014 | GFP_KERNEL, &ctr->chain_buffer_dma); | |
6015 | if (!ctr->chain_buffer) | |
6016 | return -EAGAIN; | |
208cc9fe SR |
6017 | if (!mpt3sas_check_same_4gb_region( |
6018 | ctr->chain_buffer_dma, ioc->chain_segment_sz)) { | |
7dd847da SP |
6019 | ioc_err(ioc, |
6020 | "Chain buffers are not in same 4G !!! Chain buff (0x%p) dma = (0x%llx)\n", | |
6021 | ctr->chain_buffer, | |
6022 | (unsigned long long)ctr->chain_buffer_dma); | |
6023 | ioc->use_32bit_dma = true; | |
6024 | return -EAGAIN; | |
6025 | } | |
6026 | } | |
6027 | } | |
6028 | dinitprintk(ioc, ioc_info(ioc, | |
6029 | "chain_lookup depth (%d), frame_size(%d), pool_size(%d kB)\n", | |
6030 | ioc->scsiio_depth, ioc->chain_segment_sz, ((ioc->scsiio_depth * | |
6031 | (ioc->chains_needed_per_io - ioc->chains_per_prp_buffer) * | |
6032 | ioc->chain_segment_sz))/1024)); | |
6033 | return 0; | |
6034 | } | |
6035 | ||
970ac2bb SP |
6036 | /** |
6037 | * _base_allocate_sense_dma_pool - Allocating DMA'able memory | |
6038 | * for sense dma pool. | |
6039 | * @ioc: Adapter object | |
6040 | * @sz: DMA Pool size | |
6041 | * Return: 0 for success, non-zero for failure. | |
6042 | */ | |
6043 | static int | |
6044 | _base_allocate_sense_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz) | |
6045 | { | |
6046 | ioc->sense_dma_pool = | |
6047 | dma_pool_create("sense pool", &ioc->pdev->dev, sz, 4, 0); | |
6048 | if (!ioc->sense_dma_pool) | |
6049 | return -ENOMEM; | |
6050 | ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, | |
6051 | GFP_KERNEL, &ioc->sense_dma); | |
6052 | if (!ioc->sense) | |
6053 | return -EAGAIN; | |
208cc9fe | 6054 | if (!mpt3sas_check_same_4gb_region(ioc->sense_dma, sz)) { |
970ac2bb SP |
6055 | dinitprintk(ioc, pr_err( |
6056 | "Bad Sense Pool! sense (0x%p) sense_dma = (0x%llx)\n", | |
6057 | ioc->sense, (unsigned long long) ioc->sense_dma)); | |
6058 | ioc->use_32bit_dma = true; | |
6059 | return -EAGAIN; | |
6060 | } | |
6061 | ioc_info(ioc, | |
6062 | "sense pool(0x%p) - dma(0x%llx): depth(%d), element_size(%d), pool_size (%d kB)\n", | |
6063 | ioc->sense, (unsigned long long)ioc->sense_dma, | |
6064 | ioc->scsiio_depth, SCSI_SENSE_BUFFERSIZE, sz/1024); | |
6065 | return 0; | |
6066 | } | |
6067 | ||
58501fd9 SP |
6068 | /** |
6069 | * _base_allocate_reply_pool - Allocating DMA'able memory | |
6070 | * for reply pool. | |
6071 | * @ioc: Adapter object | |
6072 | * @sz: DMA Pool size | |
6073 | * Return: 0 for success, non-zero for failure. | |
6074 | */ | |
6075 | static int | |
6076 | _base_allocate_reply_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz) | |
6077 | { | |
6078 | /* reply pool, 4 byte align */ | |
6079 | ioc->reply_dma_pool = dma_pool_create("reply pool", | |
6080 | &ioc->pdev->dev, sz, 4, 0); | |
6081 | if (!ioc->reply_dma_pool) | |
6082 | return -ENOMEM; | |
6083 | ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL, | |
6084 | &ioc->reply_dma); | |
6085 | if (!ioc->reply) | |
6086 | return -EAGAIN; | |
208cc9fe | 6087 | if (!mpt3sas_check_same_4gb_region(ioc->reply_dma, sz)) { |
58501fd9 SP |
6088 | dinitprintk(ioc, pr_err( |
6089 | "Bad Reply Pool! Reply (0x%p) Reply dma = (0x%llx)\n", | |
6090 | ioc->reply, (unsigned long long) ioc->reply_dma)); | |
6091 | ioc->use_32bit_dma = true; | |
6092 | return -EAGAIN; | |
6093 | } | |
6094 | ioc->reply_dma_min_address = (u32)(ioc->reply_dma); | |
6095 | ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz; | |
6096 | ioc_info(ioc, | |
6097 | "reply pool(0x%p) - dma(0x%llx): depth(%d), frame_size(%d), pool_size(%d kB)\n", | |
6098 | ioc->reply, (unsigned long long)ioc->reply_dma, | |
6099 | ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024); | |
6100 | return 0; | |
6101 | } | |
6102 | ||
2e4e8587 SP |
6103 | /** |
6104 | * _base_allocate_reply_free_dma_pool - Allocating DMA'able memory | |
6105 | * for reply free dma pool. | |
6106 | * @ioc: Adapter object | |
6107 | * @sz: DMA Pool size | |
6108 | * Return: 0 for success, non-zero for failure. | |
6109 | */ | |
6110 | static int | |
6111 | _base_allocate_reply_free_dma_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz) | |
6112 | { | |
6113 | /* reply free queue, 16 byte align */ | |
6114 | ioc->reply_free_dma_pool = dma_pool_create( | |
6115 | "reply_free pool", &ioc->pdev->dev, sz, 16, 0); | |
6116 | if (!ioc->reply_free_dma_pool) | |
6117 | return -ENOMEM; | |
6118 | ioc->reply_free = dma_pool_alloc(ioc->reply_free_dma_pool, | |
6119 | GFP_KERNEL, &ioc->reply_free_dma); | |
6120 | if (!ioc->reply_free) | |
6121 | return -EAGAIN; | |
208cc9fe | 6122 | if (!mpt3sas_check_same_4gb_region(ioc->reply_free_dma, sz)) { |
2e4e8587 SP |
6123 | dinitprintk(ioc, |
6124 | pr_err("Bad Reply Free Pool! Reply Free (0x%p) Reply Free dma = (0x%llx)\n", | |
6125 | ioc->reply_free, (unsigned long long) ioc->reply_free_dma)); | |
6126 | ioc->use_32bit_dma = true; | |
6127 | return -EAGAIN; | |
6128 | } | |
6129 | memset(ioc->reply_free, 0, sz); | |
6130 | dinitprintk(ioc, ioc_info(ioc, | |
6131 | "reply_free pool(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n", | |
6132 | ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024)); | |
6133 | dinitprintk(ioc, ioc_info(ioc, | |
6134 | "reply_free_dma (0x%llx)\n", | |
6135 | (unsigned long long)ioc->reply_free_dma)); | |
6136 | return 0; | |
6137 | } | |
6138 | ||
c569de89 SP |
6139 | /** |
6140 | * _base_allocate_reply_post_free_array - Allocating DMA'able memory | |
6141 | * for reply post free array. | |
6142 | * @ioc: Adapter object | |
6143 | * @reply_post_free_array_sz: DMA Pool size | |
6144 | * Return: 0 for success, non-zero for failure. | |
6145 | */ | |
6146 | ||
6147 | static int | |
6148 | _base_allocate_reply_post_free_array(struct MPT3SAS_ADAPTER *ioc, | |
6149 | u32 reply_post_free_array_sz) | |
6150 | { | |
6151 | ioc->reply_post_free_array_dma_pool = | |
6152 | dma_pool_create("reply_post_free_array pool", | |
6153 | &ioc->pdev->dev, reply_post_free_array_sz, 16, 0); | |
6154 | if (!ioc->reply_post_free_array_dma_pool) | |
6155 | return -ENOMEM; | |
6156 | ioc->reply_post_free_array = | |
6157 | dma_pool_alloc(ioc->reply_post_free_array_dma_pool, | |
6158 | GFP_KERNEL, &ioc->reply_post_free_array_dma); | |
6159 | if (!ioc->reply_post_free_array) | |
6160 | return -EAGAIN; | |
208cc9fe | 6161 | if (!mpt3sas_check_same_4gb_region(ioc->reply_post_free_array_dma, |
c569de89 SP |
6162 | reply_post_free_array_sz)) { |
6163 | dinitprintk(ioc, pr_err( | |
6164 | "Bad Reply Free Pool! Reply Free (0x%p) Reply Free dma = (0x%llx)\n", | |
6165 | ioc->reply_free, | |
6166 | (unsigned long long) ioc->reply_free_dma)); | |
6167 | ioc->use_32bit_dma = true; | |
6168 | return -EAGAIN; | |
6169 | } | |
6170 | return 0; | |
6171 | } | |
85896421 SP |
6172 | /** |
6173 | * base_alloc_rdpq_dma_pool - Allocating DMA'able memory | |
6174 | * for reply queues. | |
6175 | * @ioc: per adapter object | |
6176 | * @sz: DMA Pool size | |
6177 | * Return: 0 for success, non-zero for failure. | |
6178 | */ | |
6179 | static int | |
6180 | base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz) | |
6181 | { | |
8012209e SP |
6182 | int i = 0; |
6183 | u32 dma_alloc_count = 0; | |
6184 | int reply_post_free_sz = ioc->reply_post_queue_depth * | |
6185 | sizeof(Mpi2DefaultReplyDescriptor_t); | |
85896421 SP |
6186 | int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1; |
6187 | ||
6188 | ioc->reply_post = kcalloc(count, sizeof(struct reply_post_struct), | |
6189 | GFP_KERNEL); | |
6190 | if (!ioc->reply_post) | |
6191 | return -ENOMEM; | |
8012209e SP |
6192 | /* |
6193 | * For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and | |
6194 | * VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should | |
6195 | * be within 4GB boundary i.e reply queues in a set must have same | |
6196 | * upper 32-bits in their memory address. so here driver is allocating | |
6197 | * the DMA'able memory for reply queues according. | |
6198 | * Driver uses limitation of | |
6199 | * VENTURA_SERIES to manage INVADER_SERIES as well. | |
6200 | */ | |
f56577e8 | 6201 | dma_alloc_count = DIV_ROUND_UP(count, |
8012209e | 6202 | RDPQ_MAX_INDEX_IN_ONE_CHUNK); |
85896421 | 6203 | ioc->reply_post_free_dma_pool = |
8012209e SP |
6204 | dma_pool_create("reply_post_free pool", |
6205 | &ioc->pdev->dev, sz, 16, 0); | |
85896421 SP |
6206 | if (!ioc->reply_post_free_dma_pool) |
6207 | return -ENOMEM; | |
f56577e8 | 6208 | for (i = 0; i < count; i++) { |
8012209e SP |
6209 | if ((i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0) && dma_alloc_count) { |
6210 | ioc->reply_post[i].reply_post_free = | |
61e6ba03 | 6211 | dma_pool_zalloc(ioc->reply_post_free_dma_pool, |
8012209e SP |
6212 | GFP_KERNEL, |
6213 | &ioc->reply_post[i].reply_post_free_dma); | |
6214 | if (!ioc->reply_post[i].reply_post_free) | |
6215 | return -ENOMEM; | |
6216 | /* | |
6217 | * Each set of RDPQ pool must satisfy 4gb boundary | |
6218 | * restriction. | |
6219 | * 1) Check if allocated resources for RDPQ pool are in | |
6220 | * the same 4GB range. | |
6221 | * 2) If #1 is true, continue with 64 bit DMA. | |
6222 | * 3) If #1 is false, return 1. which means free all the | |
6223 | * resources and set DMA mask to 32 and allocate. | |
6224 | */ | |
6225 | if (!mpt3sas_check_same_4gb_region( | |
208cc9fe | 6226 | ioc->reply_post[i].reply_post_free_dma, sz)) { |
8012209e SP |
6227 | dinitprintk(ioc, |
6228 | ioc_err(ioc, "bad Replypost free pool(0x%p)" | |
6229 | "reply_post_free_dma = (0x%llx)\n", | |
6230 | ioc->reply_post[i].reply_post_free, | |
6231 | (unsigned long long) | |
6232 | ioc->reply_post[i].reply_post_free_dma)); | |
6233 | return -EAGAIN; | |
6234 | } | |
8012209e | 6235 | dma_alloc_count--; |
85896421 | 6236 | |
8012209e SP |
6237 | } else { |
6238 | ioc->reply_post[i].reply_post_free = | |
6239 | (Mpi2ReplyDescriptorsUnion_t *) | |
6240 | ((long)ioc->reply_post[i-1].reply_post_free | |
6241 | + reply_post_free_sz); | |
6242 | ioc->reply_post[i].reply_post_free_dma = | |
6243 | (dma_addr_t) | |
6244 | (ioc->reply_post[i-1].reply_post_free_dma + | |
6245 | reply_post_free_sz); | |
6246 | } | |
6247 | } | |
85896421 SP |
6248 | return 0; |
6249 | } | |
6250 | ||
f92363d1 SR |
6251 | /** |
6252 | * _base_allocate_memory_pools - allocate start of day memory pools | |
6253 | * @ioc: per adapter object | |
f92363d1 | 6254 | * |
4beb4867 | 6255 | * Return: 0 success, anything else error. |
f92363d1 SR |
6256 | */ |
6257 | static int | |
98c56ad3 | 6258 | _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
6259 | { |
6260 | struct mpt3sas_facts *facts; | |
6261 | u16 max_sge_elements; | |
6262 | u16 chains_needed_per_io; | |
cd33223b | 6263 | u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz; |
f92363d1 | 6264 | u32 retry_sz; |
970ac2bb | 6265 | u32 rdpq_sz = 0, sense_sz = 0; |
016d5c35 | 6266 | u16 max_request_credit, nvme_blocks_needed; |
f92363d1 SR |
6267 | unsigned short sg_tablesize; |
6268 | u16 sge_size; | |
7dd847da | 6269 | int i; |
d6adc251 | 6270 | int ret = 0, rc = 0; |
f92363d1 | 6271 | |
919d8a3f | 6272 | dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); |
f92363d1 SR |
6273 | |
6274 | ||
6275 | retry_sz = 0; | |
6276 | facts = &ioc->facts; | |
6277 | ||
6278 | /* command line tunables for max sgl entries */ | |
6279 | if (max_sgl_entries != -1) | |
6280 | sg_tablesize = max_sgl_entries; | |
471ef9d4 SR |
6281 | else { |
6282 | if (ioc->hba_mpi_version_belonged == MPI2_VERSION) | |
6283 | sg_tablesize = MPT2SAS_SG_DEPTH; | |
6284 | else | |
6285 | sg_tablesize = MPT3SAS_SG_DEPTH; | |
6286 | } | |
f92363d1 | 6287 | |
06f5f976 SR |
6288 | /* max sgl entries <= MPT_KDUMP_MIN_PHYS_SEGMENTS in KDUMP mode */ |
6289 | if (reset_devices) | |
6290 | sg_tablesize = min_t(unsigned short, sg_tablesize, | |
6291 | MPT_KDUMP_MIN_PHYS_SEGMENTS); | |
6292 | ||
0448f019 SPS |
6293 | if (ioc->is_mcpu_endpoint) |
6294 | ioc->shost->sg_tablesize = MPT_MIN_PHYS_SEGMENTS; | |
6295 | else { | |
6296 | if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS) | |
6297 | sg_tablesize = MPT_MIN_PHYS_SEGMENTS; | |
6298 | else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) { | |
6299 | sg_tablesize = min_t(unsigned short, sg_tablesize, | |
6300 | SG_MAX_SEGMENTS); | |
919d8a3f JP |
6301 | ioc_warn(ioc, "sg_tablesize(%u) is bigger than kernel defined SG_CHUNK_SIZE(%u)\n", |
6302 | sg_tablesize, MPT_MAX_PHYS_SEGMENTS); | |
0448f019 SPS |
6303 | } |
6304 | ioc->shost->sg_tablesize = sg_tablesize; | |
ad666a0f | 6305 | } |
f92363d1 | 6306 | |
fd0331b3 SS |
6307 | ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)), |
6308 | (facts->RequestCredit / 4)); | |
6309 | if (ioc->internal_depth < INTERNAL_CMDS_COUNT) { | |
6310 | if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT + | |
6311 | INTERNAL_SCSIIO_CMDS_COUNT)) { | |
919d8a3f JP |
6312 | ioc_err(ioc, "IOC doesn't have enough Request Credits, it has just %d number of credits\n", |
6313 | facts->RequestCredit); | |
fd0331b3 SS |
6314 | return -ENOMEM; |
6315 | } | |
6316 | ioc->internal_depth = 10; | |
6317 | } | |
6318 | ||
6319 | ioc->hi_priority_depth = ioc->internal_depth - (5); | |
f92363d1 SR |
6320 | /* command line tunables for max controller queue depth */ |
6321 | if (max_queue_depth != -1 && max_queue_depth != 0) { | |
6322 | max_request_credit = min_t(u16, max_queue_depth + | |
fd0331b3 | 6323 | ioc->internal_depth, facts->RequestCredit); |
f92363d1 SR |
6324 | if (max_request_credit > MAX_HBA_QUEUE_DEPTH) |
6325 | max_request_credit = MAX_HBA_QUEUE_DEPTH; | |
06f5f976 SR |
6326 | } else if (reset_devices) |
6327 | max_request_credit = min_t(u16, facts->RequestCredit, | |
6328 | (MPT3SAS_KDUMP_SCSI_IO_DEPTH + ioc->internal_depth)); | |
6329 | else | |
f92363d1 SR |
6330 | max_request_credit = min_t(u16, facts->RequestCredit, |
6331 | MAX_HBA_QUEUE_DEPTH); | |
6332 | ||
fd0331b3 SS |
6333 | /* Firmware maintains additional facts->HighPriorityCredit number of |
6334 | * credits for HiPriprity Request messages, so hba queue depth will be | |
6335 | * sum of max_request_credit and high priority queue depth. | |
6336 | */ | |
6337 | ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth; | |
f92363d1 SR |
6338 | |
6339 | /* request frame size */ | |
6340 | ioc->request_sz = facts->IOCRequestFrameSize * 4; | |
6341 | ||
6342 | /* reply frame size */ | |
6343 | ioc->reply_sz = facts->ReplyFrameSize * 4; | |
6344 | ||
ebb3024e SS |
6345 | /* chain segment size */ |
6346 | if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { | |
6347 | if (facts->IOCMaxChainSegmentSize) | |
6348 | ioc->chain_segment_sz = | |
6349 | facts->IOCMaxChainSegmentSize * | |
6350 | MAX_CHAIN_ELEMT_SZ; | |
6351 | else | |
6352 | /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */ | |
6353 | ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS * | |
6354 | MAX_CHAIN_ELEMT_SZ; | |
6355 | } else | |
6356 | ioc->chain_segment_sz = ioc->request_sz; | |
6357 | ||
f92363d1 SR |
6358 | /* calculate the max scatter element size */ |
6359 | sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee); | |
6360 | ||
6361 | retry_allocation: | |
6362 | total_sz = 0; | |
6363 | /* calculate number of sg elements left over in the 1st frame */ | |
6364 | max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) - | |
6365 | sizeof(Mpi2SGEIOUnion_t)) + sge_size); | |
6366 | ioc->max_sges_in_main_message = max_sge_elements/sge_size; | |
6367 | ||
6368 | /* now do the same for a chain buffer */ | |
ebb3024e | 6369 | max_sge_elements = ioc->chain_segment_sz - sge_size; |
f92363d1 SR |
6370 | ioc->max_sges_in_chain_message = max_sge_elements/sge_size; |
6371 | ||
6372 | /* | |
6373 | * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE | |
6374 | */ | |
6375 | chains_needed_per_io = ((ioc->shost->sg_tablesize - | |
6376 | ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message) | |
6377 | + 1; | |
6378 | if (chains_needed_per_io > facts->MaxChainDepth) { | |
6379 | chains_needed_per_io = facts->MaxChainDepth; | |
6380 | ioc->shost->sg_tablesize = min_t(u16, | |
6381 | ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message | |
6382 | * chains_needed_per_io), ioc->shost->sg_tablesize); | |
6383 | } | |
6384 | ioc->chains_needed_per_io = chains_needed_per_io; | |
6385 | ||
6386 | /* reply free queue sizing - taking into account for 64 FW events */ | |
6387 | ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; | |
6388 | ||
0448f019 SPS |
6389 | /* mCPU manage single counters for simplicity */ |
6390 | if (ioc->is_mcpu_endpoint) | |
6391 | ioc->reply_post_queue_depth = ioc->reply_free_queue_depth; | |
6392 | else { | |
6393 | /* calculate reply descriptor post queue depth */ | |
6394 | ioc->reply_post_queue_depth = ioc->hba_queue_depth + | |
6395 | ioc->reply_free_queue_depth + 1; | |
6396 | /* align the reply post queue on the next 16 count boundary */ | |
6397 | if (ioc->reply_post_queue_depth % 16) | |
6398 | ioc->reply_post_queue_depth += 16 - | |
6399 | (ioc->reply_post_queue_depth % 16); | |
6400 | } | |
f92363d1 | 6401 | |
f92363d1 SR |
6402 | if (ioc->reply_post_queue_depth > |
6403 | facts->MaxReplyDescriptorPostQueueDepth) { | |
6404 | ioc->reply_post_queue_depth = | |
6405 | facts->MaxReplyDescriptorPostQueueDepth - | |
6406 | (facts->MaxReplyDescriptorPostQueueDepth % 16); | |
6407 | ioc->hba_queue_depth = | |
6408 | ((ioc->reply_post_queue_depth - 64) / 2) - 1; | |
6409 | ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; | |
6410 | } | |
6411 | ||
5b061980 SR |
6412 | ioc_info(ioc, |
6413 | "scatter gather: sge_in_main_msg(%d), sge_per_chain(%d), " | |
6414 | "sge_per_io(%d), chains_per_io(%d)\n", | |
6415 | ioc->max_sges_in_main_message, | |
6416 | ioc->max_sges_in_chain_message, | |
6417 | ioc->shost->sg_tablesize, | |
6418 | ioc->chains_needed_per_io); | |
f92363d1 | 6419 | |
9b05c91a SR |
6420 | /* reply post queue, 16 byte align */ |
6421 | reply_post_free_sz = ioc->reply_post_queue_depth * | |
6422 | sizeof(Mpi2DefaultReplyDescriptor_t); | |
8012209e | 6423 | rdpq_sz = reply_post_free_sz * RDPQ_MAX_INDEX_IN_ONE_CHUNK; |
d309ae07 SR |
6424 | if ((_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable) |
6425 | || (ioc->reply_queue_count < RDPQ_MAX_INDEX_IN_ONE_CHUNK)) | |
8012209e SP |
6426 | rdpq_sz = reply_post_free_sz * ioc->reply_queue_count; |
6427 | ret = base_alloc_rdpq_dma_pool(ioc, rdpq_sz); | |
6428 | if (ret == -EAGAIN) { | |
6429 | /* | |
6430 | * Free allocated bad RDPQ memory pools. | |
6431 | * Change dma coherent mask to 32 bit and reallocate RDPQ | |
6432 | */ | |
6433 | _base_release_memory_pools(ioc); | |
6434 | ioc->use_32bit_dma = true; | |
6435 | if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) { | |
6436 | ioc_err(ioc, | |
6437 | "32 DMA mask failed %s\n", pci_name(ioc->pdev)); | |
6438 | return -ENODEV; | |
6439 | } | |
6440 | if (base_alloc_rdpq_dma_pool(ioc, rdpq_sz)) | |
6441 | return -ENOMEM; | |
6442 | } else if (ret == -ENOMEM) | |
6443 | return -ENOMEM; | |
6444 | total_sz = rdpq_sz * (!ioc->rdpq_array_enable ? 1 : | |
6445 | DIV_ROUND_UP(ioc->reply_queue_count, RDPQ_MAX_INDEX_IN_ONE_CHUNK)); | |
f92363d1 SR |
6446 | ioc->scsiio_depth = ioc->hba_queue_depth - |
6447 | ioc->hi_priority_depth - ioc->internal_depth; | |
6448 | ||
6449 | /* set the scsi host can_queue depth | |
6450 | * with some internal commands that could be outstanding | |
6451 | */ | |
fd0331b3 | 6452 | ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT; |
919d8a3f JP |
6453 | dinitprintk(ioc, |
6454 | ioc_info(ioc, "scsi host: can_queue depth (%d)\n", | |
6455 | ioc->shost->can_queue)); | |
f92363d1 | 6456 | |
f92363d1 SR |
6457 | /* contiguous pool for request and chains, 16 byte align, one extra " |
6458 | * "frame for smid=0 | |
6459 | */ | |
6460 | ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth; | |
6461 | sz = ((ioc->scsiio_depth + 1) * ioc->request_sz); | |
6462 | ||
6463 | /* hi-priority queue */ | |
6464 | sz += (ioc->hi_priority_depth * ioc->request_sz); | |
6465 | ||
6466 | /* internal queue */ | |
6467 | sz += (ioc->internal_depth * ioc->request_sz); | |
6468 | ||
6469 | ioc->request_dma_sz = sz; | |
1c2048bd CH |
6470 | ioc->request = dma_alloc_coherent(&ioc->pdev->dev, sz, |
6471 | &ioc->request_dma, GFP_KERNEL); | |
f92363d1 | 6472 | if (!ioc->request) { |
1c2048bd | 6473 | ioc_err(ioc, "request pool: dma_alloc_coherent failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kB)\n", |
919d8a3f JP |
6474 | ioc->hba_queue_depth, ioc->chains_needed_per_io, |
6475 | ioc->request_sz, sz / 1024); | |
f92363d1 SR |
6476 | if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH) |
6477 | goto out; | |
fd0331b3 SS |
6478 | retry_sz = 64; |
6479 | ioc->hba_queue_depth -= retry_sz; | |
8ff045c9 | 6480 | _base_release_memory_pools(ioc); |
f92363d1 SR |
6481 | goto retry_allocation; |
6482 | } | |
6483 | ||
6484 | if (retry_sz) | |
1c2048bd | 6485 | ioc_err(ioc, "request pool: dma_alloc_coherent succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kb)\n", |
919d8a3f JP |
6486 | ioc->hba_queue_depth, ioc->chains_needed_per_io, |
6487 | ioc->request_sz, sz / 1024); | |
f92363d1 SR |
6488 | |
6489 | /* hi-priority queue */ | |
6490 | ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) * | |
6491 | ioc->request_sz); | |
6492 | ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) * | |
6493 | ioc->request_sz); | |
6494 | ||
6495 | /* internal queue */ | |
6496 | ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth * | |
6497 | ioc->request_sz); | |
6498 | ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth * | |
6499 | ioc->request_sz); | |
6500 | ||
5b061980 SR |
6501 | ioc_info(ioc, |
6502 | "request pool(0x%p) - dma(0x%llx): " | |
6503 | "depth(%d), frame_size(%d), pool_size(%d kB)\n", | |
6504 | ioc->request, (unsigned long long) ioc->request_dma, | |
6505 | ioc->hba_queue_depth, ioc->request_sz, | |
6506 | (ioc->hba_queue_depth * ioc->request_sz) / 1024); | |
f92363d1 | 6507 | |
f92363d1 SR |
6508 | total_sz += sz; |
6509 | ||
919d8a3f JP |
6510 | dinitprintk(ioc, |
6511 | ioc_info(ioc, "scsiio(0x%p): depth(%d)\n", | |
6512 | ioc->request, ioc->scsiio_depth)); | |
f92363d1 SR |
6513 | |
6514 | ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH); | |
93204b78 C |
6515 | sz = ioc->scsiio_depth * sizeof(struct chain_lookup); |
6516 | ioc->chain_lookup = kzalloc(sz, GFP_KERNEL); | |
f92363d1 | 6517 | if (!ioc->chain_lookup) { |
919d8a3f | 6518 | ioc_err(ioc, "chain_lookup: __get_free_pages failed\n"); |
f92363d1 SR |
6519 | goto out; |
6520 | } | |
93204b78 C |
6521 | |
6522 | sz = ioc->chains_needed_per_io * sizeof(struct chain_tracker); | |
6523 | for (i = 0; i < ioc->scsiio_depth; i++) { | |
6524 | ioc->chain_lookup[i].chains_per_smid = kzalloc(sz, GFP_KERNEL); | |
6525 | if (!ioc->chain_lookup[i].chains_per_smid) { | |
919d8a3f | 6526 | ioc_err(ioc, "chain_lookup: kzalloc failed\n"); |
93204b78 C |
6527 | goto out; |
6528 | } | |
6529 | } | |
6530 | ||
f92363d1 SR |
6531 | /* initialize hi-priority queue smid's */ |
6532 | ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth, | |
6533 | sizeof(struct request_tracker), GFP_KERNEL); | |
6534 | if (!ioc->hpr_lookup) { | |
919d8a3f | 6535 | ioc_err(ioc, "hpr_lookup: kcalloc failed\n"); |
f92363d1 SR |
6536 | goto out; |
6537 | } | |
6538 | ioc->hi_priority_smid = ioc->scsiio_depth + 1; | |
919d8a3f JP |
6539 | dinitprintk(ioc, |
6540 | ioc_info(ioc, "hi_priority(0x%p): depth(%d), start smid(%d)\n", | |
6541 | ioc->hi_priority, | |
6542 | ioc->hi_priority_depth, ioc->hi_priority_smid)); | |
f92363d1 SR |
6543 | |
6544 | /* initialize internal queue smid's */ | |
6545 | ioc->internal_lookup = kcalloc(ioc->internal_depth, | |
6546 | sizeof(struct request_tracker), GFP_KERNEL); | |
6547 | if (!ioc->internal_lookup) { | |
919d8a3f | 6548 | ioc_err(ioc, "internal_lookup: kcalloc failed\n"); |
f92363d1 SR |
6549 | goto out; |
6550 | } | |
6551 | ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth; | |
919d8a3f JP |
6552 | dinitprintk(ioc, |
6553 | ioc_info(ioc, "internal(0x%p): depth(%d), start smid(%d)\n", | |
6554 | ioc->internal, | |
6555 | ioc->internal_depth, ioc->internal_smid)); | |
664f0dce SR |
6556 | |
6557 | ioc->io_queue_num = kcalloc(ioc->scsiio_depth, | |
6558 | sizeof(u16), GFP_KERNEL); | |
6559 | if (!ioc->io_queue_num) | |
6560 | goto out; | |
016d5c35 SPS |
6561 | /* |
6562 | * The number of NVMe page sized blocks needed is: | |
6563 | * (((sg_tablesize * 8) - 1) / (page_size - 8)) + 1 | |
6564 | * ((sg_tablesize * 8) - 1) is the max PRP's minus the first PRP entry | |
6565 | * that is placed in the main message frame. 8 is the size of each PRP | |
6566 | * entry or PRP list pointer entry. 8 is subtracted from page_size | |
6567 | * because of the PRP list pointer entry at the end of a page, so this | |
6568 | * is not counted as a PRP entry. The 1 added page is a round up. | |
6569 | * | |
6570 | * To avoid allocation failures due to the amount of memory that could | |
6571 | * be required for NVMe PRP's, only each set of NVMe blocks will be | |
6572 | * contiguous, so a new set is allocated for each possible I/O. | |
6573 | */ | |
d6adc251 | 6574 | |
74522a92 | 6575 | ioc->chains_per_prp_buffer = 0; |
016d5c35 SPS |
6576 | if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) { |
6577 | nvme_blocks_needed = | |
6578 | (ioc->shost->sg_tablesize * NVME_PRP_SIZE) - 1; | |
6579 | nvme_blocks_needed /= (ioc->page_size - NVME_PRP_SIZE); | |
6580 | nvme_blocks_needed++; | |
6581 | ||
dbec4c90 SPS |
6582 | sz = sizeof(struct pcie_sg_list) * ioc->scsiio_depth; |
6583 | ioc->pcie_sg_lookup = kzalloc(sz, GFP_KERNEL); | |
6584 | if (!ioc->pcie_sg_lookup) { | |
919d8a3f | 6585 | ioc_info(ioc, "PCIe SGL lookup: kzalloc failed\n"); |
dbec4c90 SPS |
6586 | goto out; |
6587 | } | |
016d5c35 | 6588 | sz = nvme_blocks_needed * ioc->page_size; |
d6adc251 SP |
6589 | rc = _base_allocate_pcie_sgl_pool(ioc, sz); |
6590 | if (rc == -ENOMEM) | |
6591 | return -ENOMEM; | |
6592 | else if (rc == -EAGAIN) | |
6593 | goto try_32bit_dma; | |
016d5c35 SPS |
6594 | total_sz += sz * ioc->scsiio_depth; |
6595 | } | |
74522a92 | 6596 | |
7dd847da SP |
6597 | rc = _base_allocate_chain_dma_pool(ioc, ioc->chain_segment_sz); |
6598 | if (rc == -ENOMEM) | |
6599 | return -ENOMEM; | |
6600 | else if (rc == -EAGAIN) | |
6601 | goto try_32bit_dma; | |
6602 | total_sz += ioc->chain_segment_sz * ((ioc->chains_needed_per_io - | |
6603 | ioc->chains_per_prp_buffer) * ioc->scsiio_depth); | |
919d8a3f | 6604 | dinitprintk(ioc, |
7dd847da SP |
6605 | ioc_info(ioc, "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n", |
6606 | ioc->chain_depth, ioc->chain_segment_sz, | |
6607 | (ioc->chain_depth * ioc->chain_segment_sz) / 1024)); | |
f92363d1 | 6608 | /* sense buffers, 4 byte align */ |
970ac2bb SP |
6609 | sense_sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE; |
6610 | rc = _base_allocate_sense_dma_pool(ioc, sense_sz); | |
6611 | if (rc == -ENOMEM) | |
6612 | return -ENOMEM; | |
6613 | else if (rc == -EAGAIN) | |
6614 | goto try_32bit_dma; | |
6615 | total_sz += sense_sz; | |
f92363d1 SR |
6616 | /* reply pool, 4 byte align */ |
6617 | sz = ioc->reply_free_queue_depth * ioc->reply_sz; | |
58501fd9 SP |
6618 | rc = _base_allocate_reply_pool(ioc, sz); |
6619 | if (rc == -ENOMEM) | |
6620 | return -ENOMEM; | |
6621 | else if (rc == -EAGAIN) | |
6622 | goto try_32bit_dma; | |
f92363d1 | 6623 | total_sz += sz; |
2e4e8587 | 6624 | |
f92363d1 SR |
6625 | /* reply free queue, 16 byte align */ |
6626 | sz = ioc->reply_free_queue_depth * 4; | |
2e4e8587 SP |
6627 | rc = _base_allocate_reply_free_dma_pool(ioc, sz); |
6628 | if (rc == -ENOMEM) | |
6629 | return -ENOMEM; | |
6630 | else if (rc == -EAGAIN) | |
6631 | goto try_32bit_dma; | |
919d8a3f JP |
6632 | dinitprintk(ioc, |
6633 | ioc_info(ioc, "reply_free_dma (0x%llx)\n", | |
6634 | (unsigned long long)ioc->reply_free_dma)); | |
f92363d1 | 6635 | total_sz += sz; |
cd33223b C |
6636 | if (ioc->rdpq_array_enable) { |
6637 | reply_post_free_array_sz = ioc->reply_queue_count * | |
6638 | sizeof(Mpi2IOCInitRDPQArrayEntry); | |
c569de89 SP |
6639 | rc = _base_allocate_reply_post_free_array(ioc, |
6640 | reply_post_free_array_sz); | |
6641 | if (rc == -ENOMEM) | |
6642 | return -ENOMEM; | |
6643 | else if (rc == -EAGAIN) | |
6644 | goto try_32bit_dma; | |
cd33223b | 6645 | } |
f92363d1 | 6646 | ioc->config_page_sz = 512; |
1c2048bd CH |
6647 | ioc->config_page = dma_alloc_coherent(&ioc->pdev->dev, |
6648 | ioc->config_page_sz, &ioc->config_page_dma, GFP_KERNEL); | |
f92363d1 | 6649 | if (!ioc->config_page) { |
919d8a3f | 6650 | ioc_err(ioc, "config page: dma_pool_alloc failed\n"); |
f92363d1 SR |
6651 | goto out; |
6652 | } | |
5b061980 SR |
6653 | |
6654 | ioc_info(ioc, "config page(0x%p) - dma(0x%llx): size(%d)\n", | |
6655 | ioc->config_page, (unsigned long long)ioc->config_page_dma, | |
6656 | ioc->config_page_sz); | |
f92363d1 SR |
6657 | total_sz += ioc->config_page_sz; |
6658 | ||
919d8a3f JP |
6659 | ioc_info(ioc, "Allocated physical memory: size(%d kB)\n", |
6660 | total_sz / 1024); | |
6661 | ioc_info(ioc, "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n", | |
6662 | ioc->shost->can_queue, facts->RequestCredit); | |
6663 | ioc_info(ioc, "Scatter Gather Elements per IO(%d)\n", | |
6664 | ioc->shost->sg_tablesize); | |
f92363d1 SR |
6665 | return 0; |
6666 | ||
d6adc251 SP |
6667 | try_32bit_dma: |
6668 | _base_release_memory_pools(ioc); | |
6669 | if (ioc->use_32bit_dma && (ioc->dma_mask > 32)) { | |
6670 | /* Change dma coherent mask to 32 bit and reallocate */ | |
6671 | if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) { | |
6672 | pr_err("Setting 32 bit coherent DMA mask Failed %s\n", | |
6673 | pci_name(ioc->pdev)); | |
6674 | return -ENODEV; | |
6675 | } | |
6676 | } else if (_base_reduce_hba_queue_depth(ioc) != 0) | |
6677 | return -ENOMEM; | |
6678 | goto retry_allocation; | |
6679 | ||
f92363d1 SR |
6680 | out: |
6681 | return -ENOMEM; | |
6682 | } | |
6683 | ||
6684 | /** | |
6685 | * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter. | |
6686 | * @ioc: Pointer to MPT_ADAPTER structure | |
6687 | * @cooked: Request raw or cooked IOC state | |
6688 | * | |
4beb4867 | 6689 | * Return: all IOC Doorbell register bits if cooked==0, else just the |
f92363d1 SR |
6690 | * Doorbell bits in MPI_IOC_STATE_MASK. |
6691 | */ | |
6692 | u32 | |
6693 | mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked) | |
6694 | { | |
6695 | u32 s, sc; | |
6696 | ||
4ca10f3e | 6697 | s = ioc->base_readl_ext_retry(&ioc->chip->Doorbell); |
f92363d1 SR |
6698 | sc = s & MPI2_IOC_STATE_MASK; |
6699 | return cooked ? sc : s; | |
6700 | } | |
6701 | ||
6702 | /** | |
6703 | * _base_wait_on_iocstate - waiting on a particular ioc state | |
4beb4867 | 6704 | * @ioc: ? |
f92363d1 SR |
6705 | * @ioc_state: controller state { READY, OPERATIONAL, or RESET } |
6706 | * @timeout: timeout in second | |
f92363d1 | 6707 | * |
4beb4867 | 6708 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
6709 | */ |
6710 | static int | |
98c56ad3 | 6711 | _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout) |
f92363d1 SR |
6712 | { |
6713 | u32 count, cntdn; | |
6714 | u32 current_state; | |
6715 | ||
6716 | count = 0; | |
98c56ad3 | 6717 | cntdn = 1000 * timeout; |
f92363d1 SR |
6718 | do { |
6719 | current_state = mpt3sas_base_get_iocstate(ioc, 1); | |
6720 | if (current_state == ioc_state) | |
6721 | return 0; | |
6722 | if (count && current_state == MPI2_IOC_STATE_FAULT) | |
6723 | break; | |
e8c2307e SR |
6724 | if (count && current_state == MPI2_IOC_STATE_COREDUMP) |
6725 | break; | |
98c56ad3 CO |
6726 | |
6727 | usleep_range(1000, 1500); | |
f92363d1 SR |
6728 | count++; |
6729 | } while (--cntdn); | |
6730 | ||
6731 | return current_state; | |
6732 | } | |
6733 | ||
af6ec1ee SP |
6734 | /** |
6735 | * _base_dump_reg_set - This function will print hexdump of register set. | |
6736 | * @ioc: per adapter object | |
6737 | * | |
2910a4a9 | 6738 | * Return: nothing. |
af6ec1ee SP |
6739 | */ |
6740 | static inline void | |
6741 | _base_dump_reg_set(struct MPT3SAS_ADAPTER *ioc) | |
6742 | { | |
6743 | unsigned int i, sz = 256; | |
6744 | u32 __iomem *reg = (u32 __iomem *)ioc->chip; | |
6745 | ||
6746 | ioc_info(ioc, "System Register set:\n"); | |
6747 | for (i = 0; i < (sz / sizeof(u32)); i++) | |
6748 | pr_info("%08x: %08x\n", (i * 4), readl(®[i])); | |
6749 | } | |
6750 | ||
f92363d1 SR |
6751 | /** |
6752 | * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by | |
6753 | * a write to the doorbell) | |
6754 | * @ioc: per adapter object | |
9133d27e | 6755 | * @timeout: timeout in seconds |
f92363d1 | 6756 | * |
4beb4867 | 6757 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
6758 | * |
6759 | * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell. | |
6760 | */ | |
4dc8c808 | 6761 | |
f92363d1 | 6762 | static int |
98c56ad3 | 6763 | _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout) |
f92363d1 SR |
6764 | { |
6765 | u32 cntdn, count; | |
6766 | u32 int_status; | |
6767 | ||
6768 | count = 0; | |
98c56ad3 | 6769 | cntdn = 1000 * timeout; |
f92363d1 | 6770 | do { |
306eaf27 | 6771 | int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus); |
f92363d1 | 6772 | if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { |
919d8a3f JP |
6773 | dhsprintk(ioc, |
6774 | ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n", | |
6775 | __func__, count, timeout)); | |
f92363d1 SR |
6776 | return 0; |
6777 | } | |
98c56ad3 CO |
6778 | |
6779 | usleep_range(1000, 1500); | |
6780 | count++; | |
6781 | } while (--cntdn); | |
6782 | ||
919d8a3f JP |
6783 | ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n", |
6784 | __func__, count, int_status); | |
98c56ad3 CO |
6785 | return -EFAULT; |
6786 | } | |
6787 | ||
6788 | static int | |
6789 | _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout) | |
6790 | { | |
6791 | u32 cntdn, count; | |
6792 | u32 int_status; | |
6793 | ||
6794 | count = 0; | |
6795 | cntdn = 2000 * timeout; | |
6796 | do { | |
306eaf27 | 6797 | int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus); |
98c56ad3 | 6798 | if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { |
919d8a3f JP |
6799 | dhsprintk(ioc, |
6800 | ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n", | |
6801 | __func__, count, timeout)); | |
98c56ad3 CO |
6802 | return 0; |
6803 | } | |
6804 | ||
6805 | udelay(500); | |
f92363d1 SR |
6806 | count++; |
6807 | } while (--cntdn); | |
6808 | ||
919d8a3f JP |
6809 | ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n", |
6810 | __func__, count, int_status); | |
f92363d1 | 6811 | return -EFAULT; |
98c56ad3 | 6812 | |
f92363d1 SR |
6813 | } |
6814 | ||
6815 | /** | |
6816 | * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell. | |
6817 | * @ioc: per adapter object | |
6818 | * @timeout: timeout in second | |
f92363d1 | 6819 | * |
4beb4867 | 6820 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
6821 | * |
6822 | * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to | |
6823 | * doorbell. | |
6824 | */ | |
6825 | static int | |
98c56ad3 | 6826 | _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout) |
f92363d1 SR |
6827 | { |
6828 | u32 cntdn, count; | |
6829 | u32 int_status; | |
6830 | u32 doorbell; | |
6831 | ||
6832 | count = 0; | |
98c56ad3 | 6833 | cntdn = 1000 * timeout; |
f92363d1 | 6834 | do { |
306eaf27 | 6835 | int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus); |
f92363d1 | 6836 | if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) { |
919d8a3f JP |
6837 | dhsprintk(ioc, |
6838 | ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n", | |
6839 | __func__, count, timeout)); | |
f92363d1 SR |
6840 | return 0; |
6841 | } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { | |
4ca10f3e | 6842 | doorbell = ioc->base_readl_ext_retry(&ioc->chip->Doorbell); |
f92363d1 SR |
6843 | if ((doorbell & MPI2_IOC_STATE_MASK) == |
6844 | MPI2_IOC_STATE_FAULT) { | |
c5977718 | 6845 | mpt3sas_print_fault_code(ioc, doorbell); |
f92363d1 SR |
6846 | return -EFAULT; |
6847 | } | |
e8c2307e SR |
6848 | if ((doorbell & MPI2_IOC_STATE_MASK) == |
6849 | MPI2_IOC_STATE_COREDUMP) { | |
c5977718 | 6850 | mpt3sas_print_coredump_info(ioc, doorbell); |
e8c2307e SR |
6851 | return -EFAULT; |
6852 | } | |
f92363d1 SR |
6853 | } else if (int_status == 0xFFFFFFFF) |
6854 | goto out; | |
6855 | ||
98c56ad3 | 6856 | usleep_range(1000, 1500); |
f92363d1 SR |
6857 | count++; |
6858 | } while (--cntdn); | |
6859 | ||
6860 | out: | |
919d8a3f JP |
6861 | ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n", |
6862 | __func__, count, int_status); | |
f92363d1 SR |
6863 | return -EFAULT; |
6864 | } | |
6865 | ||
6866 | /** | |
6867 | * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use | |
6868 | * @ioc: per adapter object | |
6869 | * @timeout: timeout in second | |
f92363d1 | 6870 | * |
4beb4867 | 6871 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
6872 | */ |
6873 | static int | |
98c56ad3 | 6874 | _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout) |
f92363d1 SR |
6875 | { |
6876 | u32 cntdn, count; | |
6877 | u32 doorbell_reg; | |
6878 | ||
6879 | count = 0; | |
98c56ad3 | 6880 | cntdn = 1000 * timeout; |
f92363d1 | 6881 | do { |
4ca10f3e | 6882 | doorbell_reg = ioc->base_readl_ext_retry(&ioc->chip->Doorbell); |
f92363d1 | 6883 | if (!(doorbell_reg & MPI2_DOORBELL_USED)) { |
919d8a3f JP |
6884 | dhsprintk(ioc, |
6885 | ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n", | |
6886 | __func__, count, timeout)); | |
f92363d1 SR |
6887 | return 0; |
6888 | } | |
98c56ad3 CO |
6889 | |
6890 | usleep_range(1000, 1500); | |
f92363d1 SR |
6891 | count++; |
6892 | } while (--cntdn); | |
6893 | ||
919d8a3f JP |
6894 | ioc_err(ioc, "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n", |
6895 | __func__, count, doorbell_reg); | |
f92363d1 SR |
6896 | return -EFAULT; |
6897 | } | |
6898 | ||
6899 | /** | |
6900 | * _base_send_ioc_reset - send doorbell reset | |
6901 | * @ioc: per adapter object | |
6902 | * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET | |
6903 | * @timeout: timeout in second | |
f92363d1 | 6904 | * |
4beb4867 | 6905 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
6906 | */ |
6907 | static int | |
98c56ad3 | 6908 | _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout) |
f92363d1 SR |
6909 | { |
6910 | u32 ioc_state; | |
6911 | int r = 0; | |
e8c2307e | 6912 | unsigned long flags; |
f92363d1 SR |
6913 | |
6914 | if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) { | |
919d8a3f | 6915 | ioc_err(ioc, "%s: unknown reset_type\n", __func__); |
f92363d1 SR |
6916 | return -EFAULT; |
6917 | } | |
6918 | ||
6919 | if (!(ioc->facts.IOCCapabilities & | |
6920 | MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY)) | |
6921 | return -EFAULT; | |
6922 | ||
919d8a3f | 6923 | ioc_info(ioc, "sending message unit reset !!\n"); |
f92363d1 SR |
6924 | |
6925 | writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT, | |
6926 | &ioc->chip->Doorbell); | |
98c56ad3 | 6927 | if ((_base_wait_for_doorbell_ack(ioc, 15))) { |
f92363d1 SR |
6928 | r = -EFAULT; |
6929 | goto out; | |
6930 | } | |
e8c2307e | 6931 | |
98c56ad3 | 6932 | ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout); |
f92363d1 | 6933 | if (ioc_state) { |
919d8a3f JP |
6934 | ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n", |
6935 | __func__, ioc_state); | |
f92363d1 SR |
6936 | r = -EFAULT; |
6937 | goto out; | |
6938 | } | |
6939 | out: | |
e8c2307e SR |
6940 | if (r != 0) { |
6941 | ioc_state = mpt3sas_base_get_iocstate(ioc, 0); | |
6942 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
6943 | /* | |
6944 | * Wait for IOC state CoreDump to clear only during | |
6945 | * HBA initialization & release time. | |
6946 | */ | |
6947 | if ((ioc_state & MPI2_IOC_STATE_MASK) == | |
6948 | MPI2_IOC_STATE_COREDUMP && (ioc->is_driver_loading == 1 || | |
6949 | ioc->fault_reset_work_q == NULL)) { | |
6950 | spin_unlock_irqrestore( | |
6951 | &ioc->ioc_reset_in_progress_lock, flags); | |
c5977718 | 6952 | mpt3sas_print_coredump_info(ioc, ioc_state); |
e8c2307e SR |
6953 | mpt3sas_base_wait_for_coredump_completion(ioc, |
6954 | __func__); | |
6955 | spin_lock_irqsave( | |
6956 | &ioc->ioc_reset_in_progress_lock, flags); | |
6957 | } | |
6958 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
6959 | } | |
919d8a3f JP |
6960 | ioc_info(ioc, "message unit reset: %s\n", |
6961 | r == 0 ? "SUCCESS" : "FAILED"); | |
f92363d1 SR |
6962 | return r; |
6963 | } | |
6964 | ||
f4305749 SP |
6965 | /** |
6966 | * mpt3sas_wait_for_ioc - IOC's operational state is checked here. | |
6967 | * @ioc: per adapter object | |
9133d27e | 6968 | * @timeout: timeout in seconds |
f4305749 SP |
6969 | * |
6970 | * Return: Waits up to timeout seconds for the IOC to | |
6971 | * become operational. Returns 0 if IOC is present | |
2910a4a9 | 6972 | * and operational; otherwise returns %-EFAULT. |
f4305749 SP |
6973 | */ |
6974 | ||
6975 | int | |
6976 | mpt3sas_wait_for_ioc(struct MPT3SAS_ADAPTER *ioc, int timeout) | |
6977 | { | |
6978 | int wait_state_count = 0; | |
6979 | u32 ioc_state; | |
6980 | ||
a064a647 | 6981 | do { |
f4305749 | 6982 | ioc_state = mpt3sas_base_get_iocstate(ioc, 1); |
a064a647 SP |
6983 | if (ioc_state == MPI2_IOC_STATE_OPERATIONAL) |
6984 | break; | |
19a622c3 SP |
6985 | |
6986 | /* | |
6987 | * Watchdog thread will be started after IOC Initialization, so | |
6988 | * no need to wait here for IOC state to become operational | |
6989 | * when IOC Initialization is on. Instead the driver will | |
6990 | * return ETIME status, so that calling function can issue | |
6991 | * diag reset operation and retry the command. | |
6992 | */ | |
6993 | if (ioc->is_driver_loading) | |
6994 | return -ETIME; | |
6995 | ||
a064a647 | 6996 | ssleep(1); |
f4305749 | 6997 | ioc_info(ioc, "%s: waiting for operational state(count=%d)\n", |
a064a647 SP |
6998 | __func__, ++wait_state_count); |
6999 | } while (--timeout); | |
7000 | if (!timeout) { | |
7001 | ioc_err(ioc, "%s: failed due to ioc not operational\n", __func__); | |
7002 | return -EFAULT; | |
f4305749 SP |
7003 | } |
7004 | if (wait_state_count) | |
7005 | ioc_info(ioc, "ioc is operational\n"); | |
f4305749 SP |
7006 | return 0; |
7007 | } | |
7008 | ||
f92363d1 SR |
7009 | /** |
7010 | * _base_handshake_req_reply_wait - send request thru doorbell interface | |
7011 | * @ioc: per adapter object | |
7012 | * @request_bytes: request length | |
7013 | * @request: pointer having request payload | |
7014 | * @reply_bytes: reply length | |
7015 | * @reply: pointer to reply payload | |
7016 | * @timeout: timeout in second | |
f92363d1 | 7017 | * |
4beb4867 | 7018 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
7019 | */ |
7020 | static int | |
7021 | _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes, | |
98c56ad3 | 7022 | u32 *request, int reply_bytes, u16 *reply, int timeout) |
f92363d1 SR |
7023 | { |
7024 | MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply; | |
7025 | int i; | |
7026 | u8 failed; | |
f92363d1 SR |
7027 | __le32 *mfp; |
7028 | ||
7029 | /* make sure doorbell is not in use */ | |
4ca10f3e | 7030 | if ((ioc->base_readl_ext_retry(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) { |
919d8a3f | 7031 | ioc_err(ioc, "doorbell is in use (line=%d)\n", __LINE__); |
f92363d1 SR |
7032 | return -EFAULT; |
7033 | } | |
7034 | ||
7035 | /* clear pending doorbell interrupts from previous state changes */ | |
306eaf27 | 7036 | if (ioc->base_readl(&ioc->chip->HostInterruptStatus) & |
f92363d1 SR |
7037 | MPI2_HIS_IOC2SYS_DB_STATUS) |
7038 | writel(0, &ioc->chip->HostInterruptStatus); | |
7039 | ||
7040 | /* send message to ioc */ | |
7041 | writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) | | |
7042 | ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)), | |
7043 | &ioc->chip->Doorbell); | |
7044 | ||
98c56ad3 | 7045 | if ((_base_spin_on_doorbell_int(ioc, 5))) { |
919d8a3f JP |
7046 | ioc_err(ioc, "doorbell handshake int failed (line=%d)\n", |
7047 | __LINE__); | |
f92363d1 SR |
7048 | return -EFAULT; |
7049 | } | |
7050 | writel(0, &ioc->chip->HostInterruptStatus); | |
7051 | ||
98c56ad3 | 7052 | if ((_base_wait_for_doorbell_ack(ioc, 5))) { |
919d8a3f JP |
7053 | ioc_err(ioc, "doorbell handshake ack failed (line=%d)\n", |
7054 | __LINE__); | |
f92363d1 SR |
7055 | return -EFAULT; |
7056 | } | |
7057 | ||
7058 | /* send message 32-bits at a time */ | |
7059 | for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) { | |
f920642e | 7060 | writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell); |
98c56ad3 | 7061 | if ((_base_wait_for_doorbell_ack(ioc, 5))) |
f92363d1 SR |
7062 | failed = 1; |
7063 | } | |
7064 | ||
7065 | if (failed) { | |
919d8a3f JP |
7066 | ioc_err(ioc, "doorbell handshake sending request failed (line=%d)\n", |
7067 | __LINE__); | |
f92363d1 SR |
7068 | return -EFAULT; |
7069 | } | |
7070 | ||
7071 | /* now wait for the reply */ | |
98c56ad3 | 7072 | if ((_base_wait_for_doorbell_int(ioc, timeout))) { |
919d8a3f JP |
7073 | ioc_err(ioc, "doorbell handshake int failed (line=%d)\n", |
7074 | __LINE__); | |
f92363d1 SR |
7075 | return -EFAULT; |
7076 | } | |
7077 | ||
7078 | /* read the first two 16-bits, it gives the total length of the reply */ | |
4ca10f3e | 7079 | reply[0] = le16_to_cpu(ioc->base_readl_ext_retry(&ioc->chip->Doorbell) |
d82e6848 | 7080 | & MPI2_DOORBELL_DATA_MASK); |
f92363d1 | 7081 | writel(0, &ioc->chip->HostInterruptStatus); |
98c56ad3 | 7082 | if ((_base_wait_for_doorbell_int(ioc, 5))) { |
919d8a3f JP |
7083 | ioc_err(ioc, "doorbell handshake int failed (line=%d)\n", |
7084 | __LINE__); | |
f92363d1 SR |
7085 | return -EFAULT; |
7086 | } | |
4ca10f3e | 7087 | reply[1] = le16_to_cpu(ioc->base_readl_ext_retry(&ioc->chip->Doorbell) |
d82e6848 | 7088 | & MPI2_DOORBELL_DATA_MASK); |
f92363d1 SR |
7089 | writel(0, &ioc->chip->HostInterruptStatus); |
7090 | ||
7091 | for (i = 2; i < default_reply->MsgLength * 2; i++) { | |
98c56ad3 | 7092 | if ((_base_wait_for_doorbell_int(ioc, 5))) { |
919d8a3f JP |
7093 | ioc_err(ioc, "doorbell handshake int failed (line=%d)\n", |
7094 | __LINE__); | |
f92363d1 SR |
7095 | return -EFAULT; |
7096 | } | |
7097 | if (i >= reply_bytes/2) /* overflow case */ | |
4ca10f3e | 7098 | ioc->base_readl_ext_retry(&ioc->chip->Doorbell); |
f92363d1 | 7099 | else |
d82e6848 | 7100 | reply[i] = le16_to_cpu( |
4ca10f3e | 7101 | ioc->base_readl_ext_retry(&ioc->chip->Doorbell) |
d82e6848 | 7102 | & MPI2_DOORBELL_DATA_MASK); |
f92363d1 SR |
7103 | writel(0, &ioc->chip->HostInterruptStatus); |
7104 | } | |
7105 | ||
98c56ad3 CO |
7106 | _base_wait_for_doorbell_int(ioc, 5); |
7107 | if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) { | |
919d8a3f JP |
7108 | dhsprintk(ioc, |
7109 | ioc_info(ioc, "doorbell is in use (line=%d)\n", | |
7110 | __LINE__)); | |
f92363d1 SR |
7111 | } |
7112 | writel(0, &ioc->chip->HostInterruptStatus); | |
7113 | ||
7114 | if (ioc->logging_level & MPT_DEBUG_INIT) { | |
7115 | mfp = (__le32 *)reply; | |
7116 | pr_info("\toffset:data\n"); | |
7117 | for (i = 0; i < reply_bytes/4; i++) | |
5b061980 | 7118 | ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4, |
f92363d1 SR |
7119 | le32_to_cpu(mfp[i])); |
7120 | } | |
7121 | return 0; | |
7122 | } | |
7123 | ||
7124 | /** | |
7125 | * mpt3sas_base_sas_iounit_control - send sas iounit control to FW | |
7126 | * @ioc: per adapter object | |
7127 | * @mpi_reply: the reply payload from FW | |
7128 | * @mpi_request: the request payload sent to FW | |
7129 | * | |
7130 | * The SAS IO Unit Control Request message allows the host to perform low-level | |
7131 | * operations, such as resets on the PHYs of the IO Unit, also allows the host | |
7132 | * to obtain the IOC assigned device handles for a device if it has other | |
7133 | * identifying information about the device, in addition allows the host to | |
7134 | * remove IOC resources associated with the device. | |
7135 | * | |
4beb4867 | 7136 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
7137 | */ |
7138 | int | |
7139 | mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc, | |
7140 | Mpi2SasIoUnitControlReply_t *mpi_reply, | |
7141 | Mpi2SasIoUnitControlRequest_t *mpi_request) | |
7142 | { | |
7143 | u16 smid; | |
d37306ca | 7144 | u8 issue_reset = 0; |
f92363d1 SR |
7145 | int rc; |
7146 | void *request; | |
f92363d1 | 7147 | |
919d8a3f | 7148 | dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); |
f92363d1 SR |
7149 | |
7150 | mutex_lock(&ioc->base_cmds.mutex); | |
7151 | ||
7152 | if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { | |
919d8a3f | 7153 | ioc_err(ioc, "%s: base_cmd in use\n", __func__); |
f92363d1 SR |
7154 | rc = -EAGAIN; |
7155 | goto out; | |
7156 | } | |
7157 | ||
f4305749 SP |
7158 | rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT); |
7159 | if (rc) | |
7160 | goto out; | |
f92363d1 SR |
7161 | |
7162 | smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); | |
7163 | if (!smid) { | |
919d8a3f | 7164 | ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); |
f92363d1 SR |
7165 | rc = -EAGAIN; |
7166 | goto out; | |
7167 | } | |
7168 | ||
7169 | rc = 0; | |
7170 | ioc->base_cmds.status = MPT3_CMD_PENDING; | |
7171 | request = mpt3sas_base_get_msg_frame(ioc, smid); | |
7172 | ioc->base_cmds.smid = smid; | |
7173 | memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)); | |
7174 | if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || | |
7175 | mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) | |
7176 | ioc->ioc_link_reset_in_progress = 1; | |
7177 | init_completion(&ioc->base_cmds.done); | |
078a4cc1 | 7178 | ioc->put_smid_default(ioc, smid); |
8bbb1cf6 | 7179 | wait_for_completion_timeout(&ioc->base_cmds.done, |
f92363d1 SR |
7180 | msecs_to_jiffies(10000)); |
7181 | if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || | |
7182 | mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) && | |
7183 | ioc->ioc_link_reset_in_progress) | |
7184 | ioc->ioc_link_reset_in_progress = 0; | |
7185 | if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { | |
c6bdb6a1 SR |
7186 | mpt3sas_check_cmd_timeout(ioc, ioc->base_cmds.status, |
7187 | mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)/4, | |
7188 | issue_reset); | |
f92363d1 SR |
7189 | goto issue_host_reset; |
7190 | } | |
7191 | if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) | |
7192 | memcpy(mpi_reply, ioc->base_cmds.reply, | |
7193 | sizeof(Mpi2SasIoUnitControlReply_t)); | |
7194 | else | |
7195 | memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t)); | |
7196 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; | |
7197 | goto out; | |
7198 | ||
7199 | issue_host_reset: | |
7200 | if (issue_reset) | |
98c56ad3 | 7201 | mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); |
f92363d1 SR |
7202 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; |
7203 | rc = -EFAULT; | |
7204 | out: | |
7205 | mutex_unlock(&ioc->base_cmds.mutex); | |
7206 | return rc; | |
7207 | } | |
7208 | ||
7209 | /** | |
7210 | * mpt3sas_base_scsi_enclosure_processor - sending request to sep device | |
7211 | * @ioc: per adapter object | |
7212 | * @mpi_reply: the reply payload from FW | |
7213 | * @mpi_request: the request payload sent to FW | |
7214 | * | |
7215 | * The SCSI Enclosure Processor request message causes the IOC to | |
7216 | * communicate with SES devices to control LED status signals. | |
7217 | * | |
4beb4867 | 7218 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
7219 | */ |
7220 | int | |
7221 | mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc, | |
7222 | Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request) | |
7223 | { | |
7224 | u16 smid; | |
d37306ca | 7225 | u8 issue_reset = 0; |
f92363d1 SR |
7226 | int rc; |
7227 | void *request; | |
f92363d1 | 7228 | |
919d8a3f | 7229 | dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); |
f92363d1 SR |
7230 | |
7231 | mutex_lock(&ioc->base_cmds.mutex); | |
7232 | ||
7233 | if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { | |
919d8a3f | 7234 | ioc_err(ioc, "%s: base_cmd in use\n", __func__); |
f92363d1 SR |
7235 | rc = -EAGAIN; |
7236 | goto out; | |
7237 | } | |
7238 | ||
f4305749 SP |
7239 | rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT); |
7240 | if (rc) | |
7241 | goto out; | |
f92363d1 SR |
7242 | |
7243 | smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); | |
7244 | if (!smid) { | |
919d8a3f | 7245 | ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); |
f92363d1 SR |
7246 | rc = -EAGAIN; |
7247 | goto out; | |
7248 | } | |
7249 | ||
7250 | rc = 0; | |
7251 | ioc->base_cmds.status = MPT3_CMD_PENDING; | |
7252 | request = mpt3sas_base_get_msg_frame(ioc, smid); | |
7253 | ioc->base_cmds.smid = smid; | |
e224e03b | 7254 | memset(request, 0, ioc->request_sz); |
f92363d1 SR |
7255 | memcpy(request, mpi_request, sizeof(Mpi2SepReply_t)); |
7256 | init_completion(&ioc->base_cmds.done); | |
078a4cc1 | 7257 | ioc->put_smid_default(ioc, smid); |
8bbb1cf6 | 7258 | wait_for_completion_timeout(&ioc->base_cmds.done, |
f92363d1 SR |
7259 | msecs_to_jiffies(10000)); |
7260 | if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { | |
c6bdb6a1 SR |
7261 | mpt3sas_check_cmd_timeout(ioc, |
7262 | ioc->base_cmds.status, mpi_request, | |
7263 | sizeof(Mpi2SepRequest_t)/4, issue_reset); | |
f92363d1 SR |
7264 | goto issue_host_reset; |
7265 | } | |
7266 | if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) | |
7267 | memcpy(mpi_reply, ioc->base_cmds.reply, | |
7268 | sizeof(Mpi2SepReply_t)); | |
7269 | else | |
7270 | memset(mpi_reply, 0, sizeof(Mpi2SepReply_t)); | |
7271 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; | |
7272 | goto out; | |
7273 | ||
7274 | issue_host_reset: | |
7275 | if (issue_reset) | |
98c56ad3 | 7276 | mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); |
f92363d1 SR |
7277 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; |
7278 | rc = -EFAULT; | |
7279 | out: | |
7280 | mutex_unlock(&ioc->base_cmds.mutex); | |
7281 | return rc; | |
7282 | } | |
7283 | ||
7284 | /** | |
7285 | * _base_get_port_facts - obtain port facts reply and save in ioc | |
7286 | * @ioc: per adapter object | |
4beb4867 | 7287 | * @port: ? |
f92363d1 | 7288 | * |
4beb4867 | 7289 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
7290 | */ |
7291 | static int | |
98c56ad3 | 7292 | _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port) |
f92363d1 SR |
7293 | { |
7294 | Mpi2PortFactsRequest_t mpi_request; | |
7295 | Mpi2PortFactsReply_t mpi_reply; | |
7296 | struct mpt3sas_port_facts *pfacts; | |
7297 | int mpi_reply_sz, mpi_request_sz, r; | |
7298 | ||
919d8a3f | 7299 | dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); |
f92363d1 SR |
7300 | |
7301 | mpi_reply_sz = sizeof(Mpi2PortFactsReply_t); | |
7302 | mpi_request_sz = sizeof(Mpi2PortFactsRequest_t); | |
7303 | memset(&mpi_request, 0, mpi_request_sz); | |
7304 | mpi_request.Function = MPI2_FUNCTION_PORT_FACTS; | |
7305 | mpi_request.PortNumber = port; | |
7306 | r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, | |
98c56ad3 | 7307 | (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5); |
f92363d1 SR |
7308 | |
7309 | if (r != 0) { | |
919d8a3f | 7310 | ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r); |
f92363d1 SR |
7311 | return r; |
7312 | } | |
7313 | ||
7314 | pfacts = &ioc->pfacts[port]; | |
7315 | memset(pfacts, 0, sizeof(struct mpt3sas_port_facts)); | |
7316 | pfacts->PortNumber = mpi_reply.PortNumber; | |
7317 | pfacts->VP_ID = mpi_reply.VP_ID; | |
7318 | pfacts->VF_ID = mpi_reply.VF_ID; | |
7319 | pfacts->MaxPostedCmdBuffers = | |
7320 | le16_to_cpu(mpi_reply.MaxPostedCmdBuffers); | |
7321 | ||
7322 | return 0; | |
7323 | } | |
7324 | ||
4dc8c808 SR |
7325 | /** |
7326 | * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL | |
7327 | * @ioc: per adapter object | |
7328 | * @timeout: | |
4dc8c808 | 7329 | * |
4beb4867 | 7330 | * Return: 0 for success, non-zero for failure. |
4dc8c808 SR |
7331 | */ |
7332 | static int | |
98c56ad3 | 7333 | _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout) |
4dc8c808 SR |
7334 | { |
7335 | u32 ioc_state; | |
7336 | int rc; | |
7337 | ||
1f95a47e | 7338 | dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); |
4dc8c808 SR |
7339 | |
7340 | if (ioc->pci_error_recovery) { | |
1f95a47e JP |
7341 | dfailprintk(ioc, |
7342 | ioc_info(ioc, "%s: host in pci error recovery\n", | |
7343 | __func__)); | |
4dc8c808 SR |
7344 | return -EFAULT; |
7345 | } | |
7346 | ||
7347 | ioc_state = mpt3sas_base_get_iocstate(ioc, 0); | |
1f95a47e JP |
7348 | dhsprintk(ioc, |
7349 | ioc_info(ioc, "%s: ioc_state(0x%08x)\n", | |
7350 | __func__, ioc_state)); | |
4dc8c808 SR |
7351 | |
7352 | if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) || | |
7353 | (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) | |
7354 | return 0; | |
7355 | ||
7356 | if (ioc_state & MPI2_DOORBELL_USED) { | |
1f95a47e | 7357 | dhsprintk(ioc, ioc_info(ioc, "unexpected doorbell active!\n")); |
4dc8c808 SR |
7358 | goto issue_diag_reset; |
7359 | } | |
7360 | ||
7361 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { | |
c5977718 | 7362 | mpt3sas_print_fault_code(ioc, ioc_state & |
4dc8c808 SR |
7363 | MPI2_DOORBELL_DATA_MASK); |
7364 | goto issue_diag_reset; | |
e8c2307e SR |
7365 | } else if ((ioc_state & MPI2_IOC_STATE_MASK) == |
7366 | MPI2_IOC_STATE_COREDUMP) { | |
7367 | ioc_info(ioc, | |
7368 | "%s: Skipping the diag reset here. (ioc_state=0x%x)\n", | |
7369 | __func__, ioc_state); | |
7370 | return -EFAULT; | |
4dc8c808 SR |
7371 | } |
7372 | ||
98c56ad3 | 7373 | ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout); |
4dc8c808 | 7374 | if (ioc_state) { |
1f95a47e JP |
7375 | dfailprintk(ioc, |
7376 | ioc_info(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n", | |
7377 | __func__, ioc_state)); | |
4dc8c808 SR |
7378 | return -EFAULT; |
7379 | } | |
7380 | ||
ee0017c3 RK |
7381 | return 0; |
7382 | ||
7383 | issue_diag_reset: | |
98c56ad3 | 7384 | rc = _base_diag_reset(ioc); |
4dc8c808 SR |
7385 | return rc; |
7386 | } | |
7387 | ||
f92363d1 SR |
7388 | /** |
7389 | * _base_get_ioc_facts - obtain ioc facts reply and save in ioc | |
7390 | * @ioc: per adapter object | |
f92363d1 | 7391 | * |
4beb4867 | 7392 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
7393 | */ |
7394 | static int | |
98c56ad3 | 7395 | _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
7396 | { |
7397 | Mpi2IOCFactsRequest_t mpi_request; | |
7398 | Mpi2IOCFactsReply_t mpi_reply; | |
7399 | struct mpt3sas_facts *facts; | |
7400 | int mpi_reply_sz, mpi_request_sz, r; | |
7401 | ||
919d8a3f | 7402 | dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); |
f92363d1 | 7403 | |
98c56ad3 | 7404 | r = _base_wait_for_iocstate(ioc, 10); |
4dc8c808 | 7405 | if (r) { |
1f95a47e JP |
7406 | dfailprintk(ioc, |
7407 | ioc_info(ioc, "%s: failed getting to correct state\n", | |
7408 | __func__)); | |
4dc8c808 SR |
7409 | return r; |
7410 | } | |
f92363d1 SR |
7411 | mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t); |
7412 | mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t); | |
7413 | memset(&mpi_request, 0, mpi_request_sz); | |
7414 | mpi_request.Function = MPI2_FUNCTION_IOC_FACTS; | |
7415 | r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, | |
98c56ad3 | 7416 | (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5); |
f92363d1 SR |
7417 | |
7418 | if (r != 0) { | |
919d8a3f | 7419 | ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r); |
f92363d1 SR |
7420 | return r; |
7421 | } | |
7422 | ||
7423 | facts = &ioc->facts; | |
7424 | memset(facts, 0, sizeof(struct mpt3sas_facts)); | |
7425 | facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion); | |
7426 | facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion); | |
7427 | facts->VP_ID = mpi_reply.VP_ID; | |
7428 | facts->VF_ID = mpi_reply.VF_ID; | |
7429 | facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions); | |
7430 | facts->MaxChainDepth = mpi_reply.MaxChainDepth; | |
7431 | facts->WhoInit = mpi_reply.WhoInit; | |
7432 | facts->NumberOfPorts = mpi_reply.NumberOfPorts; | |
7433 | facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors; | |
2b48be65 C |
7434 | if (ioc->msix_enable && (facts->MaxMSIxVectors <= |
7435 | MAX_COMBINED_MSIX_VECTORS(ioc->is_gen35_ioc))) | |
7436 | ioc->combined_reply_queue = 0; | |
f92363d1 SR |
7437 | facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit); |
7438 | facts->MaxReplyDescriptorPostQueueDepth = | |
7439 | le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth); | |
7440 | facts->ProductID = le16_to_cpu(mpi_reply.ProductID); | |
7441 | facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities); | |
7442 | if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID)) | |
7443 | ioc->ir_firmware = 1; | |
9b05c91a | 7444 | if ((facts->IOCCapabilities & |
06f5f976 | 7445 | MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE) && (!reset_devices)) |
9b05c91a | 7446 | ioc->rdpq_array_capable = 1; |
79c74d03 SP |
7447 | if ((facts->IOCCapabilities & MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ) |
7448 | && ioc->is_aero_ioc) | |
7449 | ioc->atomic_desc_capable = 1; | |
f92363d1 SR |
7450 | facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word); |
7451 | facts->IOCRequestFrameSize = | |
7452 | le16_to_cpu(mpi_reply.IOCRequestFrameSize); | |
ebb3024e SS |
7453 | if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { |
7454 | facts->IOCMaxChainSegmentSize = | |
7455 | le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize); | |
7456 | } | |
f92363d1 SR |
7457 | facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators); |
7458 | facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets); | |
7459 | ioc->shost->max_id = -1; | |
7460 | facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders); | |
7461 | facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures); | |
7462 | facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags); | |
7463 | facts->HighPriorityCredit = | |
7464 | le16_to_cpu(mpi_reply.HighPriorityCredit); | |
7465 | facts->ReplyFrameSize = mpi_reply.ReplyFrameSize; | |
7466 | facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle); | |
016d5c35 SPS |
7467 | facts->CurrentHostPageSize = mpi_reply.CurrentHostPageSize; |
7468 | ||
7469 | /* | |
7470 | * Get the Page Size from IOC Facts. If it's 0, default to 4k. | |
7471 | */ | |
7472 | ioc->page_size = 1 << facts->CurrentHostPageSize; | |
7473 | if (ioc->page_size == 1) { | |
919d8a3f | 7474 | ioc_info(ioc, "CurrentHostPageSize is 0: Setting default host page size to 4k\n"); |
016d5c35 SPS |
7475 | ioc->page_size = 1 << MPT3SAS_HOST_PAGE_SIZE_4K; |
7476 | } | |
919d8a3f JP |
7477 | dinitprintk(ioc, |
7478 | ioc_info(ioc, "CurrentHostPageSize(%d)\n", | |
7479 | facts->CurrentHostPageSize)); | |
7480 | ||
7481 | dinitprintk(ioc, | |
7482 | ioc_info(ioc, "hba queue depth(%d), max chains per io(%d)\n", | |
7483 | facts->RequestCredit, facts->MaxChainDepth)); | |
7484 | dinitprintk(ioc, | |
7485 | ioc_info(ioc, "request frame size(%d), reply frame size(%d)\n", | |
7486 | facts->IOCRequestFrameSize * 4, | |
7487 | facts->ReplyFrameSize * 4)); | |
f92363d1 SR |
7488 | return 0; |
7489 | } | |
7490 | ||
7491 | /** | |
7492 | * _base_send_ioc_init - send ioc_init to firmware | |
7493 | * @ioc: per adapter object | |
f92363d1 | 7494 | * |
4beb4867 | 7495 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
7496 | */ |
7497 | static int | |
98c56ad3 | 7498 | _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
7499 | { |
7500 | Mpi2IOCInitRequest_t mpi_request; | |
7501 | Mpi2IOCInitReply_t mpi_reply; | |
9b05c91a | 7502 | int i, r = 0; |
23409bd4 | 7503 | ktime_t current_time; |
f92363d1 | 7504 | u16 ioc_status; |
9b05c91a | 7505 | u32 reply_post_free_array_sz = 0; |
f92363d1 | 7506 | |
919d8a3f | 7507 | dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); |
f92363d1 SR |
7508 | |
7509 | memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t)); | |
7510 | mpi_request.Function = MPI2_FUNCTION_IOC_INIT; | |
7511 | mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER; | |
7512 | mpi_request.VF_ID = 0; /* TODO */ | |
7513 | mpi_request.VP_ID = 0; | |
d357e84d | 7514 | mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged); |
f92363d1 | 7515 | mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION); |
016d5c35 | 7516 | mpi_request.HostPageSize = MPT3SAS_HOST_PAGE_SIZE_4K; |
f92363d1 SR |
7517 | |
7518 | if (_base_is_controller_msix_enabled(ioc)) | |
7519 | mpi_request.HostMSIxVectors = ioc->reply_queue_count; | |
7520 | mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4); | |
7521 | mpi_request.ReplyDescriptorPostQueueDepth = | |
7522 | cpu_to_le16(ioc->reply_post_queue_depth); | |
7523 | mpi_request.ReplyFreeQueueDepth = | |
7524 | cpu_to_le16(ioc->reply_free_queue_depth); | |
7525 | ||
7526 | mpi_request.SenseBufferAddressHigh = | |
7527 | cpu_to_le32((u64)ioc->sense_dma >> 32); | |
7528 | mpi_request.SystemReplyAddressHigh = | |
7529 | cpu_to_le32((u64)ioc->reply_dma >> 32); | |
7530 | mpi_request.SystemRequestFrameBaseAddress = | |
7531 | cpu_to_le64((u64)ioc->request_dma); | |
7532 | mpi_request.ReplyFreeQueueAddress = | |
7533 | cpu_to_le64((u64)ioc->reply_free_dma); | |
f92363d1 | 7534 | |
9b05c91a SR |
7535 | if (ioc->rdpq_array_enable) { |
7536 | reply_post_free_array_sz = ioc->reply_queue_count * | |
7537 | sizeof(Mpi2IOCInitRDPQArrayEntry); | |
cd33223b | 7538 | memset(ioc->reply_post_free_array, 0, reply_post_free_array_sz); |
9b05c91a | 7539 | for (i = 0; i < ioc->reply_queue_count; i++) |
cd33223b | 7540 | ioc->reply_post_free_array[i].RDPQBaseAddress = |
9b05c91a SR |
7541 | cpu_to_le64( |
7542 | (u64)ioc->reply_post[i].reply_post_free_dma); | |
7543 | mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE; | |
7544 | mpi_request.ReplyDescriptorPostQueueAddress = | |
cd33223b | 7545 | cpu_to_le64((u64)ioc->reply_post_free_array_dma); |
9b05c91a SR |
7546 | } else { |
7547 | mpi_request.ReplyDescriptorPostQueueAddress = | |
7548 | cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma); | |
7549 | } | |
f92363d1 | 7550 | |
e8c2307e SR |
7551 | /* |
7552 | * Set the flag to enable CoreDump state feature in IOC firmware. | |
7553 | */ | |
7554 | mpi_request.ConfigurationFlags |= | |
7555 | cpu_to_le16(MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE); | |
7556 | ||
f92363d1 SR |
7557 | /* This time stamp specifies number of milliseconds |
7558 | * since epoch ~ midnight January 1, 1970. | |
7559 | */ | |
23409bd4 TR |
7560 | current_time = ktime_get_real(); |
7561 | mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time)); | |
f92363d1 SR |
7562 | |
7563 | if (ioc->logging_level & MPT_DEBUG_INIT) { | |
7564 | __le32 *mfp; | |
7565 | int i; | |
7566 | ||
7567 | mfp = (__le32 *)&mpi_request; | |
5b061980 | 7568 | ioc_info(ioc, "\toffset:data\n"); |
f92363d1 | 7569 | for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++) |
5b061980 | 7570 | ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4, |
f92363d1 SR |
7571 | le32_to_cpu(mfp[i])); |
7572 | } | |
7573 | ||
7574 | r = _base_handshake_req_reply_wait(ioc, | |
7575 | sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request, | |
85dad327 | 7576 | sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 30); |
f92363d1 SR |
7577 | |
7578 | if (r != 0) { | |
919d8a3f | 7579 | ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r); |
cd33223b | 7580 | return r; |
f92363d1 SR |
7581 | } |
7582 | ||
7583 | ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK; | |
7584 | if (ioc_status != MPI2_IOCSTATUS_SUCCESS || | |
7585 | mpi_reply.IOCLogInfo) { | |
919d8a3f | 7586 | ioc_err(ioc, "%s: failed\n", __func__); |
f92363d1 SR |
7587 | r = -EIO; |
7588 | } | |
7589 | ||
f98790c0 SP |
7590 | /* Reset TimeSync Counter*/ |
7591 | ioc->timestamp_update_count = 0; | |
9b05c91a | 7592 | return r; |
f92363d1 SR |
7593 | } |
7594 | ||
7595 | /** | |
7596 | * mpt3sas_port_enable_done - command completion routine for port enable | |
7597 | * @ioc: per adapter object | |
7598 | * @smid: system request message index | |
7599 | * @msix_index: MSIX table index supplied by the OS | |
7600 | * @reply: reply message frame(lower 32bit addr) | |
7601 | * | |
4beb4867 BVA |
7602 | * Return: 1 meaning mf should be freed from _base_interrupt |
7603 | * 0 means the mf is freed from this function. | |
f92363d1 SR |
7604 | */ |
7605 | u8 | |
7606 | mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, | |
7607 | u32 reply) | |
7608 | { | |
7609 | MPI2DefaultReply_t *mpi_reply; | |
7610 | u16 ioc_status; | |
7611 | ||
7612 | if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED) | |
7613 | return 1; | |
7614 | ||
7615 | mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); | |
7616 | if (!mpi_reply) | |
7617 | return 1; | |
7618 | ||
7619 | if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE) | |
7620 | return 1; | |
7621 | ||
7622 | ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING; | |
7623 | ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE; | |
7624 | ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID; | |
7625 | memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); | |
7626 | ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; | |
7627 | if (ioc_status != MPI2_IOCSTATUS_SUCCESS) | |
7628 | ioc->port_enable_failed = 1; | |
7629 | ||
a0815c45 | 7630 | if (ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE_ASYNC) { |
cf750be8 | 7631 | ioc->port_enable_cmds.status &= ~MPT3_CMD_COMPLETE_ASYNC; |
f92363d1 SR |
7632 | if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { |
7633 | mpt3sas_port_enable_complete(ioc); | |
7634 | return 1; | |
7635 | } else { | |
7636 | ioc->start_scan_failed = ioc_status; | |
7637 | ioc->start_scan = 0; | |
7638 | return 1; | |
7639 | } | |
7640 | } | |
7641 | complete(&ioc->port_enable_cmds.done); | |
7642 | return 1; | |
7643 | } | |
7644 | ||
7645 | /** | |
7646 | * _base_send_port_enable - send port_enable(discovery stuff) to firmware | |
7647 | * @ioc: per adapter object | |
f92363d1 | 7648 | * |
4beb4867 | 7649 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
7650 | */ |
7651 | static int | |
98c56ad3 | 7652 | _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
7653 | { |
7654 | Mpi2PortEnableRequest_t *mpi_request; | |
7655 | Mpi2PortEnableReply_t *mpi_reply; | |
f92363d1 SR |
7656 | int r = 0; |
7657 | u16 smid; | |
7658 | u16 ioc_status; | |
7659 | ||
919d8a3f | 7660 | ioc_info(ioc, "sending port enable !!\n"); |
f92363d1 SR |
7661 | |
7662 | if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { | |
919d8a3f | 7663 | ioc_err(ioc, "%s: internal command already in use\n", __func__); |
f92363d1 SR |
7664 | return -EAGAIN; |
7665 | } | |
7666 | ||
7667 | smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); | |
7668 | if (!smid) { | |
919d8a3f | 7669 | ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); |
f92363d1 SR |
7670 | return -EAGAIN; |
7671 | } | |
7672 | ||
7673 | ioc->port_enable_cmds.status = MPT3_CMD_PENDING; | |
7674 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
7675 | ioc->port_enable_cmds.smid = smid; | |
7676 | memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); | |
7677 | mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; | |
7678 | ||
7679 | init_completion(&ioc->port_enable_cmds.done); | |
078a4cc1 | 7680 | ioc->put_smid_default(ioc, smid); |
8bbb1cf6 | 7681 | wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ); |
f92363d1 | 7682 | if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) { |
919d8a3f | 7683 | ioc_err(ioc, "%s: timeout\n", __func__); |
f92363d1 SR |
7684 | _debug_dump_mf(mpi_request, |
7685 | sizeof(Mpi2PortEnableRequest_t)/4); | |
7686 | if (ioc->port_enable_cmds.status & MPT3_CMD_RESET) | |
7687 | r = -EFAULT; | |
7688 | else | |
7689 | r = -ETIME; | |
7690 | goto out; | |
7691 | } | |
7692 | ||
7693 | mpi_reply = ioc->port_enable_cmds.reply; | |
7694 | ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; | |
7695 | if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { | |
919d8a3f JP |
7696 | ioc_err(ioc, "%s: failed with (ioc_status=0x%08x)\n", |
7697 | __func__, ioc_status); | |
f92363d1 SR |
7698 | r = -EFAULT; |
7699 | goto out; | |
7700 | } | |
7701 | ||
7702 | out: | |
7703 | ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; | |
919d8a3f | 7704 | ioc_info(ioc, "port enable: %s\n", r == 0 ? "SUCCESS" : "FAILED"); |
f92363d1 SR |
7705 | return r; |
7706 | } | |
7707 | ||
7708 | /** | |
7709 | * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply) | |
7710 | * @ioc: per adapter object | |
7711 | * | |
4beb4867 | 7712 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
7713 | */ |
7714 | int | |
7715 | mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc) | |
7716 | { | |
7717 | Mpi2PortEnableRequest_t *mpi_request; | |
7718 | u16 smid; | |
7719 | ||
919d8a3f | 7720 | ioc_info(ioc, "sending port enable !!\n"); |
f92363d1 SR |
7721 | |
7722 | if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { | |
919d8a3f | 7723 | ioc_err(ioc, "%s: internal command already in use\n", __func__); |
f92363d1 SR |
7724 | return -EAGAIN; |
7725 | } | |
7726 | ||
7727 | smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); | |
7728 | if (!smid) { | |
919d8a3f | 7729 | ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); |
f92363d1 SR |
7730 | return -EAGAIN; |
7731 | } | |
19a622c3 | 7732 | ioc->drv_internal_flags |= MPT_DRV_INTERNAL_FIRST_PE_ISSUED; |
f92363d1 | 7733 | ioc->port_enable_cmds.status = MPT3_CMD_PENDING; |
a0815c45 | 7734 | ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE_ASYNC; |
f92363d1 SR |
7735 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); |
7736 | ioc->port_enable_cmds.smid = smid; | |
7737 | memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); | |
7738 | mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; | |
7739 | ||
078a4cc1 | 7740 | ioc->put_smid_default(ioc, smid); |
f92363d1 SR |
7741 | return 0; |
7742 | } | |
7743 | ||
7744 | /** | |
7745 | * _base_determine_wait_on_discovery - desposition | |
7746 | * @ioc: per adapter object | |
7747 | * | |
7748 | * Decide whether to wait on discovery to complete. Used to either | |
7749 | * locate boot device, or report volumes ahead of physical devices. | |
7750 | * | |
4beb4867 | 7751 | * Return: 1 for wait, 0 for don't wait. |
f92363d1 SR |
7752 | */ |
7753 | static int | |
7754 | _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc) | |
7755 | { | |
7756 | /* We wait for discovery to complete if IR firmware is loaded. | |
7757 | * The sas topology events arrive before PD events, so we need time to | |
7758 | * turn on the bit in ioc->pd_handles to indicate PD | |
7759 | * Also, it maybe required to report Volumes ahead of physical | |
7760 | * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set. | |
7761 | */ | |
7762 | if (ioc->ir_firmware) | |
7763 | return 1; | |
7764 | ||
7765 | /* if no Bios, then we don't need to wait */ | |
7766 | if (!ioc->bios_pg3.BiosVersion) | |
7767 | return 0; | |
7768 | ||
7769 | /* Bios is present, then we drop down here. | |
7770 | * | |
7771 | * If there any entries in the Bios Page 2, then we wait | |
7772 | * for discovery to complete. | |
7773 | */ | |
7774 | ||
7775 | /* Current Boot Device */ | |
7776 | if ((ioc->bios_pg2.CurrentBootDeviceForm & | |
7777 | MPI2_BIOSPAGE2_FORM_MASK) == | |
7778 | MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && | |
7779 | /* Request Boot Device */ | |
7780 | (ioc->bios_pg2.ReqBootDeviceForm & | |
7781 | MPI2_BIOSPAGE2_FORM_MASK) == | |
7782 | MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && | |
7783 | /* Alternate Request Boot Device */ | |
7784 | (ioc->bios_pg2.ReqAltBootDeviceForm & | |
7785 | MPI2_BIOSPAGE2_FORM_MASK) == | |
7786 | MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED) | |
7787 | return 0; | |
7788 | ||
7789 | return 1; | |
7790 | } | |
7791 | ||
7792 | /** | |
7793 | * _base_unmask_events - turn on notification for this event | |
7794 | * @ioc: per adapter object | |
7795 | * @event: firmware event | |
7796 | * | |
7797 | * The mask is stored in ioc->event_masks. | |
7798 | */ | |
7799 | static void | |
7800 | _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event) | |
7801 | { | |
7802 | u32 desired_event; | |
7803 | ||
7804 | if (event >= 128) | |
7805 | return; | |
7806 | ||
7807 | desired_event = (1 << (event % 32)); | |
7808 | ||
7809 | if (event < 32) | |
7810 | ioc->event_masks[0] &= ~desired_event; | |
7811 | else if (event < 64) | |
7812 | ioc->event_masks[1] &= ~desired_event; | |
7813 | else if (event < 96) | |
7814 | ioc->event_masks[2] &= ~desired_event; | |
7815 | else if (event < 128) | |
7816 | ioc->event_masks[3] &= ~desired_event; | |
7817 | } | |
7818 | ||
7819 | /** | |
7820 | * _base_event_notification - send event notification | |
7821 | * @ioc: per adapter object | |
f92363d1 | 7822 | * |
4beb4867 | 7823 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
7824 | */ |
7825 | static int | |
98c56ad3 | 7826 | _base_event_notification(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
7827 | { |
7828 | Mpi2EventNotificationRequest_t *mpi_request; | |
f92363d1 SR |
7829 | u16 smid; |
7830 | int r = 0; | |
19a622c3 | 7831 | int i, issue_diag_reset = 0; |
f92363d1 | 7832 | |
919d8a3f | 7833 | dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); |
f92363d1 SR |
7834 | |
7835 | if (ioc->base_cmds.status & MPT3_CMD_PENDING) { | |
919d8a3f | 7836 | ioc_err(ioc, "%s: internal command already in use\n", __func__); |
f92363d1 SR |
7837 | return -EAGAIN; |
7838 | } | |
7839 | ||
7840 | smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); | |
7841 | if (!smid) { | |
919d8a3f | 7842 | ioc_err(ioc, "%s: failed obtaining a smid\n", __func__); |
f92363d1 SR |
7843 | return -EAGAIN; |
7844 | } | |
7845 | ioc->base_cmds.status = MPT3_CMD_PENDING; | |
7846 | mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); | |
7847 | ioc->base_cmds.smid = smid; | |
7848 | memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t)); | |
7849 | mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; | |
7850 | mpi_request->VF_ID = 0; /* TODO */ | |
7851 | mpi_request->VP_ID = 0; | |
7852 | for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) | |
7853 | mpi_request->EventMasks[i] = | |
7854 | cpu_to_le32(ioc->event_masks[i]); | |
7855 | init_completion(&ioc->base_cmds.done); | |
078a4cc1 | 7856 | ioc->put_smid_default(ioc, smid); |
8bbb1cf6 | 7857 | wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ); |
f92363d1 | 7858 | if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { |
919d8a3f | 7859 | ioc_err(ioc, "%s: timeout\n", __func__); |
f92363d1 SR |
7860 | _debug_dump_mf(mpi_request, |
7861 | sizeof(Mpi2EventNotificationRequest_t)/4); | |
7862 | if (ioc->base_cmds.status & MPT3_CMD_RESET) | |
7863 | r = -EFAULT; | |
7864 | else | |
19a622c3 SP |
7865 | issue_diag_reset = 1; |
7866 | ||
f92363d1 | 7867 | } else |
919d8a3f | 7868 | dinitprintk(ioc, ioc_info(ioc, "%s: complete\n", __func__)); |
f92363d1 | 7869 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; |
19a622c3 SP |
7870 | |
7871 | if (issue_diag_reset) { | |
7872 | if (ioc->drv_internal_flags & MPT_DRV_INTERNAL_FIRST_PE_ISSUED) | |
7873 | return -EFAULT; | |
7874 | if (mpt3sas_base_check_for_fault_and_issue_reset(ioc)) | |
7875 | return -EFAULT; | |
7876 | r = -EAGAIN; | |
7877 | } | |
f92363d1 SR |
7878 | return r; |
7879 | } | |
7880 | ||
7881 | /** | |
7882 | * mpt3sas_base_validate_event_type - validating event types | |
7883 | * @ioc: per adapter object | |
4beb4867 | 7884 | * @event_type: firmware event |
f92363d1 SR |
7885 | * |
7886 | * This will turn on firmware event notification when application | |
7887 | * ask for that event. We don't mask events that are already enabled. | |
7888 | */ | |
7889 | void | |
7890 | mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type) | |
7891 | { | |
7892 | int i, j; | |
7893 | u32 event_mask, desired_event; | |
7894 | u8 send_update_to_fw; | |
7895 | ||
7896 | for (i = 0, send_update_to_fw = 0; i < | |
7897 | MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) { | |
7898 | event_mask = ~event_type[i]; | |
7899 | desired_event = 1; | |
7900 | for (j = 0; j < 32; j++) { | |
7901 | if (!(event_mask & desired_event) && | |
7902 | (ioc->event_masks[i] & desired_event)) { | |
7903 | ioc->event_masks[i] &= ~desired_event; | |
7904 | send_update_to_fw = 1; | |
7905 | } | |
7906 | desired_event = (desired_event << 1); | |
7907 | } | |
7908 | } | |
7909 | ||
7910 | if (!send_update_to_fw) | |
7911 | return; | |
7912 | ||
7913 | mutex_lock(&ioc->base_cmds.mutex); | |
98c56ad3 | 7914 | _base_event_notification(ioc); |
f92363d1 SR |
7915 | mutex_unlock(&ioc->base_cmds.mutex); |
7916 | } | |
7917 | ||
7918 | /** | |
7919 | * _base_diag_reset - the "big hammer" start of day reset | |
7920 | * @ioc: per adapter object | |
f92363d1 | 7921 | * |
4beb4867 | 7922 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
7923 | */ |
7924 | static int | |
98c56ad3 | 7925 | _base_diag_reset(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 SR |
7926 | { |
7927 | u32 host_diagnostic; | |
7928 | u32 ioc_state; | |
7929 | u32 count; | |
7930 | u32 hcb_size; | |
7931 | ||
919d8a3f | 7932 | ioc_info(ioc, "sending diag reset !!\n"); |
f92363d1 | 7933 | |
3c860469 SR |
7934 | pci_cfg_access_lock(ioc->pdev); |
7935 | ||
919d8a3f | 7936 | drsprintk(ioc, ioc_info(ioc, "clear interrupts\n")); |
f92363d1 SR |
7937 | |
7938 | count = 0; | |
7939 | do { | |
7940 | /* Write magic sequence to WriteSequence register | |
7941 | * Loop until in diagnostic mode | |
7942 | */ | |
919d8a3f | 7943 | drsprintk(ioc, ioc_info(ioc, "write magic sequence\n")); |
f92363d1 SR |
7944 | writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); |
7945 | writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence); | |
7946 | writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence); | |
7947 | writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence); | |
7948 | writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence); | |
7949 | writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence); | |
7950 | writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence); | |
7951 | ||
7952 | /* wait 100 msec */ | |
98c56ad3 | 7953 | msleep(100); |
f92363d1 | 7954 | |
5b061980 SR |
7955 | if (count++ > 20) { |
7956 | ioc_info(ioc, | |
7957 | "Stop writing magic sequence after 20 retries\n"); | |
af6ec1ee | 7958 | _base_dump_reg_set(ioc); |
f92363d1 | 7959 | goto out; |
5b061980 | 7960 | } |
f92363d1 | 7961 | |
4ca10f3e | 7962 | host_diagnostic = ioc->base_readl_ext_retry(&ioc->chip->HostDiagnostic); |
919d8a3f JP |
7963 | drsprintk(ioc, |
7964 | ioc_info(ioc, "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n", | |
7965 | count, host_diagnostic)); | |
f92363d1 SR |
7966 | |
7967 | } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0); | |
7968 | ||
306eaf27 | 7969 | hcb_size = ioc->base_readl(&ioc->chip->HCBSize); |
f92363d1 | 7970 | |
919d8a3f | 7971 | drsprintk(ioc, ioc_info(ioc, "diag reset: issued\n")); |
f92363d1 SR |
7972 | writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER, |
7973 | &ioc->chip->HostDiagnostic); | |
7974 | ||
b453ff84 | 7975 | /*This delay allows the chip PCIe hardware time to finish reset tasks*/ |
98c56ad3 | 7976 | msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000); |
f92363d1 | 7977 | |
b453ff84 SR |
7978 | /* Approximately 300 second max wait */ |
7979 | for (count = 0; count < (300000000 / | |
7980 | MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) { | |
f92363d1 | 7981 | |
4ca10f3e | 7982 | host_diagnostic = ioc->base_readl_ext_retry(&ioc->chip->HostDiagnostic); |
f92363d1 | 7983 | |
5b061980 SR |
7984 | if (host_diagnostic == 0xFFFFFFFF) { |
7985 | ioc_info(ioc, | |
7986 | "Invalid host diagnostic register value\n"); | |
af6ec1ee | 7987 | _base_dump_reg_set(ioc); |
f92363d1 | 7988 | goto out; |
5b061980 | 7989 | } |
f92363d1 SR |
7990 | if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER)) |
7991 | break; | |
7992 | ||
98c56ad3 | 7993 | msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000); |
f92363d1 SR |
7994 | } |
7995 | ||
7996 | if (host_diagnostic & MPI2_DIAG_HCB_MODE) { | |
7997 | ||
919d8a3f JP |
7998 | drsprintk(ioc, |
7999 | ioc_info(ioc, "restart the adapter assuming the HCB Address points to good F/W\n")); | |
f92363d1 SR |
8000 | host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK; |
8001 | host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW; | |
8002 | writel(host_diagnostic, &ioc->chip->HostDiagnostic); | |
8003 | ||
919d8a3f | 8004 | drsprintk(ioc, ioc_info(ioc, "re-enable the HCDW\n")); |
f92363d1 SR |
8005 | writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE, |
8006 | &ioc->chip->HCBSize); | |
8007 | } | |
8008 | ||
919d8a3f | 8009 | drsprintk(ioc, ioc_info(ioc, "restart the adapter\n")); |
f92363d1 SR |
8010 | writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET, |
8011 | &ioc->chip->HostDiagnostic); | |
8012 | ||
919d8a3f JP |
8013 | drsprintk(ioc, |
8014 | ioc_info(ioc, "disable writes to the diagnostic register\n")); | |
f92363d1 SR |
8015 | writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); |
8016 | ||
919d8a3f | 8017 | drsprintk(ioc, ioc_info(ioc, "Wait for FW to go to the READY state\n")); |
98c56ad3 | 8018 | ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20); |
f92363d1 | 8019 | if (ioc_state) { |
919d8a3f JP |
8020 | ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n", |
8021 | __func__, ioc_state); | |
af6ec1ee | 8022 | _base_dump_reg_set(ioc); |
f92363d1 SR |
8023 | goto out; |
8024 | } | |
8025 | ||
3c860469 | 8026 | pci_cfg_access_unlock(ioc->pdev); |
919d8a3f | 8027 | ioc_info(ioc, "diag reset: SUCCESS\n"); |
f92363d1 SR |
8028 | return 0; |
8029 | ||
8030 | out: | |
3c860469 | 8031 | pci_cfg_access_unlock(ioc->pdev); |
919d8a3f | 8032 | ioc_err(ioc, "diag reset: FAILED\n"); |
f92363d1 SR |
8033 | return -EFAULT; |
8034 | } | |
8035 | ||
8036 | /** | |
fae21608 | 8037 | * mpt3sas_base_make_ioc_ready - put controller in READY state |
f92363d1 | 8038 | * @ioc: per adapter object |
f92363d1 SR |
8039 | * @type: FORCE_BIG_HAMMER or SOFT_RESET |
8040 | * | |
4beb4867 | 8041 | * Return: 0 for success, non-zero for failure. |
f92363d1 | 8042 | */ |
fae21608 SR |
8043 | int |
8044 | mpt3sas_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type) | |
f92363d1 SR |
8045 | { |
8046 | u32 ioc_state; | |
8047 | int rc; | |
8048 | int count; | |
8049 | ||
919d8a3f | 8050 | dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); |
f92363d1 SR |
8051 | |
8052 | if (ioc->pci_error_recovery) | |
8053 | return 0; | |
8054 | ||
8055 | ioc_state = mpt3sas_base_get_iocstate(ioc, 0); | |
919d8a3f JP |
8056 | dhsprintk(ioc, |
8057 | ioc_info(ioc, "%s: ioc_state(0x%08x)\n", | |
8058 | __func__, ioc_state)); | |
f92363d1 SR |
8059 | |
8060 | /* if in RESET state, it should move to READY state shortly */ | |
8061 | count = 0; | |
8062 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { | |
8063 | while ((ioc_state & MPI2_IOC_STATE_MASK) != | |
8064 | MPI2_IOC_STATE_READY) { | |
8065 | if (count++ == 10) { | |
919d8a3f JP |
8066 | ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n", |
8067 | __func__, ioc_state); | |
f92363d1 SR |
8068 | return -EFAULT; |
8069 | } | |
98c56ad3 | 8070 | ssleep(1); |
f92363d1 SR |
8071 | ioc_state = mpt3sas_base_get_iocstate(ioc, 0); |
8072 | } | |
8073 | } | |
8074 | ||
8075 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) | |
8076 | return 0; | |
8077 | ||
8078 | if (ioc_state & MPI2_DOORBELL_USED) { | |
5b061980 | 8079 | ioc_info(ioc, "unexpected doorbell active!\n"); |
f92363d1 SR |
8080 | goto issue_diag_reset; |
8081 | } | |
8082 | ||
8083 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { | |
c5977718 | 8084 | mpt3sas_print_fault_code(ioc, ioc_state & |
f92363d1 SR |
8085 | MPI2_DOORBELL_DATA_MASK); |
8086 | goto issue_diag_reset; | |
8087 | } | |
8088 | ||
e8c2307e | 8089 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) { |
fce0aa08 SR |
8090 | /* |
8091 | * if host reset is invoked while watch dog thread is waiting | |
8092 | * for IOC state to be changed to Fault state then driver has | |
8093 | * to wait here for CoreDump state to clear otherwise reset | |
8094 | * will be issued to the FW and FW move the IOC state to | |
8095 | * reset state without copying the FW logs to coredump region. | |
8096 | */ | |
8097 | if (ioc->ioc_coredump_loop != MPT3SAS_COREDUMP_LOOP_DONE) { | |
c5977718 | 8098 | mpt3sas_print_coredump_info(ioc, ioc_state & |
fce0aa08 SR |
8099 | MPI2_DOORBELL_DATA_MASK); |
8100 | mpt3sas_base_wait_for_coredump_completion(ioc, | |
8101 | __func__); | |
8102 | } | |
e8c2307e SR |
8103 | goto issue_diag_reset; |
8104 | } | |
8105 | ||
f92363d1 SR |
8106 | if (type == FORCE_BIG_HAMMER) |
8107 | goto issue_diag_reset; | |
8108 | ||
8109 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) | |
8110 | if (!(_base_send_ioc_reset(ioc, | |
98c56ad3 | 8111 | MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) { |
f92363d1 SR |
8112 | return 0; |
8113 | } | |
8114 | ||
8115 | issue_diag_reset: | |
98c56ad3 | 8116 | rc = _base_diag_reset(ioc); |
f92363d1 SR |
8117 | return rc; |
8118 | } | |
8119 | ||
8120 | /** | |
8121 | * _base_make_ioc_operational - put controller in OPERATIONAL state | |
8122 | * @ioc: per adapter object | |
f92363d1 | 8123 | * |
4beb4867 | 8124 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
8125 | */ |
8126 | static int | |
98c56ad3 | 8127 | _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 | 8128 | { |
9c067c05 | 8129 | int r, i, index, rc; |
f92363d1 SR |
8130 | unsigned long flags; |
8131 | u32 reply_address; | |
8132 | u16 smid; | |
8133 | struct _tr_list *delayed_tr, *delayed_tr_next; | |
fd0331b3 SS |
8134 | struct _sc_list *delayed_sc, *delayed_sc_next; |
8135 | struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next; | |
7786ab6a | 8136 | u8 hide_flag; |
f92363d1 | 8137 | struct adapter_reply_queue *reply_q; |
5ec8a175 | 8138 | Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig; |
f92363d1 | 8139 | |
919d8a3f | 8140 | dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); |
f92363d1 SR |
8141 | |
8142 | /* clean the delayed target reset list */ | |
8143 | list_for_each_entry_safe(delayed_tr, delayed_tr_next, | |
8144 | &ioc->delayed_tr_list, list) { | |
8145 | list_del(&delayed_tr->list); | |
8146 | kfree(delayed_tr); | |
8147 | } | |
8148 | ||
8149 | ||
8150 | list_for_each_entry_safe(delayed_tr, delayed_tr_next, | |
8151 | &ioc->delayed_tr_volume_list, list) { | |
8152 | list_del(&delayed_tr->list); | |
8153 | kfree(delayed_tr); | |
8154 | } | |
8155 | ||
fd0331b3 SS |
8156 | list_for_each_entry_safe(delayed_sc, delayed_sc_next, |
8157 | &ioc->delayed_sc_list, list) { | |
8158 | list_del(&delayed_sc->list); | |
8159 | kfree(delayed_sc); | |
8160 | } | |
8161 | ||
8162 | list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next, | |
8163 | &ioc->delayed_event_ack_list, list) { | |
8164 | list_del(&delayed_event_ack->list); | |
8165 | kfree(delayed_event_ack); | |
8166 | } | |
8167 | ||
f92363d1 | 8168 | spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); |
f92363d1 SR |
8169 | |
8170 | /* hi-priority queue */ | |
8171 | INIT_LIST_HEAD(&ioc->hpr_free_list); | |
8172 | smid = ioc->hi_priority_smid; | |
8173 | for (i = 0; i < ioc->hi_priority_depth; i++, smid++) { | |
8174 | ioc->hpr_lookup[i].cb_idx = 0xFF; | |
8175 | ioc->hpr_lookup[i].smid = smid; | |
8176 | list_add_tail(&ioc->hpr_lookup[i].tracker_list, | |
8177 | &ioc->hpr_free_list); | |
8178 | } | |
8179 | ||
8180 | /* internal queue */ | |
8181 | INIT_LIST_HEAD(&ioc->internal_free_list); | |
8182 | smid = ioc->internal_smid; | |
8183 | for (i = 0; i < ioc->internal_depth; i++, smid++) { | |
8184 | ioc->internal_lookup[i].cb_idx = 0xFF; | |
8185 | ioc->internal_lookup[i].smid = smid; | |
8186 | list_add_tail(&ioc->internal_lookup[i].tracker_list, | |
8187 | &ioc->internal_free_list); | |
8188 | } | |
8189 | ||
f92363d1 SR |
8190 | spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); |
8191 | ||
8192 | /* initialize Reply Free Queue */ | |
8193 | for (i = 0, reply_address = (u32)ioc->reply_dma ; | |
8194 | i < ioc->reply_free_queue_depth ; i++, reply_address += | |
b4472d71 | 8195 | ioc->reply_sz) { |
f92363d1 | 8196 | ioc->reply_free[i] = cpu_to_le32(reply_address); |
b4472d71 SPS |
8197 | if (ioc->is_mcpu_endpoint) |
8198 | _base_clone_reply_to_sys_mem(ioc, | |
cf6bf971 | 8199 | reply_address, i); |
b4472d71 | 8200 | } |
f92363d1 SR |
8201 | |
8202 | /* initialize reply queues */ | |
8203 | if (ioc->is_driver_loading) | |
8204 | _base_assign_reply_queues(ioc); | |
8205 | ||
8206 | /* initialize Reply Post Free Queue */ | |
5ec8a175 CO |
8207 | index = 0; |
8208 | reply_post_free_contig = ioc->reply_post[0].reply_post_free; | |
f92363d1 | 8209 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { |
5ec8a175 CO |
8210 | /* |
8211 | * If RDPQ is enabled, switch to the next allocation. | |
8212 | * Otherwise advance within the contiguous region. | |
8213 | */ | |
8214 | if (ioc->rdpq_array_enable) { | |
8215 | reply_q->reply_post_free = | |
8216 | ioc->reply_post[index++].reply_post_free; | |
8217 | } else { | |
8218 | reply_q->reply_post_free = reply_post_free_contig; | |
8219 | reply_post_free_contig += ioc->reply_post_queue_depth; | |
8220 | } | |
8221 | ||
f92363d1 | 8222 | reply_q->reply_post_host_index = 0; |
f92363d1 SR |
8223 | for (i = 0; i < ioc->reply_post_queue_depth; i++) |
8224 | reply_q->reply_post_free[i].Words = | |
8225 | cpu_to_le64(ULLONG_MAX); | |
8226 | if (!_base_is_controller_msix_enabled(ioc)) | |
8227 | goto skip_init_reply_post_free_queue; | |
f92363d1 SR |
8228 | } |
8229 | skip_init_reply_post_free_queue: | |
8230 | ||
98c56ad3 | 8231 | r = _base_send_ioc_init(ioc); |
9c067c05 SP |
8232 | if (r) { |
8233 | /* | |
8234 | * No need to check IOC state for fault state & issue | |
8235 | * diag reset during host reset. This check is need | |
8236 | * only during driver load time. | |
8237 | */ | |
8238 | if (!ioc->is_driver_loading) | |
8239 | return r; | |
8240 | ||
19a622c3 | 8241 | rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc); |
9c067c05 SP |
8242 | if (rc || (_base_send_ioc_init(ioc))) |
8243 | return r; | |
8244 | } | |
f92363d1 SR |
8245 | |
8246 | /* initialize reply free host index */ | |
8247 | ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1; | |
8248 | writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex); | |
8249 | ||
8250 | /* initialize reply post host index */ | |
8251 | list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { | |
0bb337c9 | 8252 | if (ioc->combined_reply_queue) |
fb77bb53 SR |
8253 | writel((reply_q->msix_index & 7)<< |
8254 | MPI2_RPHI_MSIX_INDEX_SHIFT, | |
8255 | ioc->replyPostRegisterIndex[reply_q->msix_index/8]); | |
8256 | else | |
8257 | writel(reply_q->msix_index << | |
8258 | MPI2_RPHI_MSIX_INDEX_SHIFT, | |
8259 | &ioc->chip->ReplyPostHostIndex); | |
8260 | ||
f92363d1 SR |
8261 | if (!_base_is_controller_msix_enabled(ioc)) |
8262 | goto skip_init_reply_post_host_index; | |
8263 | } | |
8264 | ||
8265 | skip_init_reply_post_host_index: | |
8266 | ||
5afa9d44 | 8267 | mpt3sas_base_unmask_interrupts(ioc); |
3d29ed85 C |
8268 | |
8269 | if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { | |
8270 | r = _base_display_fwpkg_version(ioc); | |
8271 | if (r) | |
8272 | return r; | |
8273 | } | |
8274 | ||
40d32727 | 8275 | r = _base_static_config_pages(ioc); |
19a622c3 SP |
8276 | if (r) |
8277 | return r; | |
8278 | ||
98c56ad3 | 8279 | r = _base_event_notification(ioc); |
f92363d1 SR |
8280 | if (r) |
8281 | return r; | |
8282 | ||
a0815c45 | 8283 | if (!ioc->shost_recovery) { |
7786ab6a SR |
8284 | |
8285 | if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier | |
8286 | == 0x80) { | |
8287 | hide_flag = (u8) ( | |
8288 | le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) & | |
8289 | MFG_PAGE10_HIDE_SSDS_MASK); | |
8290 | if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK) | |
8291 | ioc->mfg_pg10_hide_flag = hide_flag; | |
8292 | } | |
8293 | ||
f92363d1 SR |
8294 | ioc->wait_for_discovery_to_complete = |
8295 | _base_determine_wait_on_discovery(ioc); | |
8296 | ||
8297 | return r; /* scan_start and scan_finished support */ | |
8298 | } | |
8299 | ||
98c56ad3 | 8300 | r = _base_send_port_enable(ioc); |
f92363d1 SR |
8301 | if (r) |
8302 | return r; | |
8303 | ||
8304 | return r; | |
8305 | } | |
8306 | ||
8307 | /** | |
8308 | * mpt3sas_base_free_resources - free resources controller resources | |
8309 | * @ioc: per adapter object | |
f92363d1 SR |
8310 | */ |
8311 | void | |
8312 | mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc) | |
8313 | { | |
919d8a3f | 8314 | dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); |
f92363d1 | 8315 | |
08c4d550 SR |
8316 | /* synchronizing freeing resource with pci_access_mutex lock */ |
8317 | mutex_lock(&ioc->pci_access_mutex); | |
cf9bd21a | 8318 | if (ioc->chip_phys && ioc->chip) { |
5afa9d44 | 8319 | mpt3sas_base_mask_interrupts(ioc); |
cf9bd21a | 8320 | ioc->shost_recovery = 1; |
fae21608 | 8321 | mpt3sas_base_make_ioc_ready(ioc, SOFT_RESET); |
cf9bd21a JL |
8322 | ioc->shost_recovery = 0; |
8323 | } | |
8324 | ||
580d4e31 | 8325 | mpt3sas_base_unmap_resources(ioc); |
08c4d550 | 8326 | mutex_unlock(&ioc->pci_access_mutex); |
f92363d1 SR |
8327 | return; |
8328 | } | |
8329 | ||
8330 | /** | |
8331 | * mpt3sas_base_attach - attach controller instance | |
8332 | * @ioc: per adapter object | |
8333 | * | |
4beb4867 | 8334 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
8335 | */ |
8336 | int | |
8337 | mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc) | |
8338 | { | |
9c067c05 | 8339 | int r, i, rc; |
f92363d1 SR |
8340 | int cpu_id, last_cpu_id = 0; |
8341 | ||
919d8a3f | 8342 | dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); |
f92363d1 SR |
8343 | |
8344 | /* setup cpu_msix_table */ | |
8345 | ioc->cpu_count = num_online_cpus(); | |
8346 | for_each_online_cpu(cpu_id) | |
8347 | last_cpu_id = cpu_id; | |
8348 | ioc->cpu_msix_table_sz = last_cpu_id + 1; | |
8349 | ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL); | |
8350 | ioc->reply_queue_count = 1; | |
8351 | if (!ioc->cpu_msix_table) { | |
5b061980 | 8352 | ioc_info(ioc, "Allocation for cpu_msix_table failed!!!\n"); |
f92363d1 SR |
8353 | r = -ENOMEM; |
8354 | goto out_free_resources; | |
8355 | } | |
8356 | ||
7786ab6a SR |
8357 | if (ioc->is_warpdrive) { |
8358 | ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz, | |
8359 | sizeof(resource_size_t *), GFP_KERNEL); | |
8360 | if (!ioc->reply_post_host_index) { | |
5b061980 | 8361 | ioc_info(ioc, "Allocation for reply_post_host_index failed!!!\n"); |
7786ab6a SR |
8362 | r = -ENOMEM; |
8363 | goto out_free_resources; | |
8364 | } | |
8365 | } | |
8366 | ||
610ef1e9 SR |
8367 | ioc->smp_affinity_enable = smp_affinity_enable; |
8368 | ||
9b05c91a | 8369 | ioc->rdpq_array_enable_assigned = 0; |
55d4ce45 | 8370 | ioc->use_32bit_dma = false; |
d6adc251 | 8371 | ioc->dma_mask = 64; |
4ca10f3e | 8372 | if (ioc->is_aero_ioc) { |
b8992029 | 8373 | ioc->base_readl = &_base_readl_aero; |
4ca10f3e RK |
8374 | ioc->base_readl_ext_retry = &_base_readl_ext_retry; |
8375 | } else { | |
b8992029 | 8376 | ioc->base_readl = &_base_readl; |
4ca10f3e RK |
8377 | ioc->base_readl_ext_retry = &_base_readl; |
8378 | } | |
f92363d1 SR |
8379 | r = mpt3sas_base_map_resources(ioc); |
8380 | if (r) | |
8381 | goto out_free_resources; | |
8382 | ||
f92363d1 | 8383 | pci_set_drvdata(ioc->pdev, ioc->shost); |
98c56ad3 | 8384 | r = _base_get_ioc_facts(ioc); |
9c067c05 | 8385 | if (r) { |
19a622c3 | 8386 | rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc); |
9c067c05 SP |
8387 | if (rc || (_base_get_ioc_facts(ioc))) |
8388 | goto out_free_resources; | |
8389 | } | |
f92363d1 | 8390 | |
471ef9d4 SR |
8391 | switch (ioc->hba_mpi_version_belonged) { |
8392 | case MPI2_VERSION: | |
8393 | ioc->build_sg_scmd = &_base_build_sg_scmd; | |
8394 | ioc->build_sg = &_base_build_sg; | |
8395 | ioc->build_zero_len_sge = &_base_build_zero_len_sge; | |
5dd48a55 | 8396 | ioc->get_msix_index_for_smlio = &_base_get_msix_index; |
471ef9d4 SR |
8397 | break; |
8398 | case MPI25_VERSION: | |
b130b0d5 | 8399 | case MPI26_VERSION: |
471ef9d4 SR |
8400 | /* |
8401 | * In SAS3.0, | |
8402 | * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and | |
2910a4a9 | 8403 | * Target Status - all require the IEEE formatted scatter gather |
471ef9d4 SR |
8404 | * elements. |
8405 | */ | |
8406 | ioc->build_sg_scmd = &_base_build_sg_scmd_ieee; | |
8407 | ioc->build_sg = &_base_build_sg_ieee; | |
aff39e61 | 8408 | ioc->build_nvme_prp = &_base_build_nvme_prp; |
471ef9d4 SR |
8409 | ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee; |
8410 | ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t); | |
5dd48a55 SP |
8411 | if (ioc->high_iops_queues) |
8412 | ioc->get_msix_index_for_smlio = | |
8413 | &_base_get_high_iops_msix_index; | |
8414 | else | |
8415 | ioc->get_msix_index_for_smlio = &_base_get_msix_index; | |
471ef9d4 SR |
8416 | break; |
8417 | } | |
79c74d03 SP |
8418 | if (ioc->atomic_desc_capable) { |
8419 | ioc->put_smid_default = &_base_put_smid_default_atomic; | |
8420 | ioc->put_smid_scsi_io = &_base_put_smid_scsi_io_atomic; | |
8421 | ioc->put_smid_fast_path = | |
8422 | &_base_put_smid_fast_path_atomic; | |
8423 | ioc->put_smid_hi_priority = | |
8424 | &_base_put_smid_hi_priority_atomic; | |
8425 | } else { | |
8426 | ioc->put_smid_default = &_base_put_smid_default; | |
8427 | ioc->put_smid_fast_path = &_base_put_smid_fast_path; | |
8428 | ioc->put_smid_hi_priority = &_base_put_smid_hi_priority; | |
8429 | if (ioc->is_mcpu_endpoint) | |
8430 | ioc->put_smid_scsi_io = | |
8431 | &_base_put_smid_mpi_ep_scsi_io; | |
8432 | else | |
8433 | ioc->put_smid_scsi_io = &_base_put_smid_scsi_io; | |
8434 | } | |
f92363d1 SR |
8435 | /* |
8436 | * These function pointers for other requests that don't | |
8437 | * the require IEEE scatter gather elements. | |
8438 | * | |
8439 | * For example Configuration Pages and SAS IOUNIT Control don't. | |
8440 | */ | |
8441 | ioc->build_sg_mpi = &_base_build_sg; | |
8442 | ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge; | |
8443 | ||
fae21608 | 8444 | r = mpt3sas_base_make_ioc_ready(ioc, SOFT_RESET); |
f92363d1 SR |
8445 | if (r) |
8446 | goto out_free_resources; | |
8447 | ||
8448 | ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts, | |
8449 | sizeof(struct mpt3sas_port_facts), GFP_KERNEL); | |
8450 | if (!ioc->pfacts) { | |
8451 | r = -ENOMEM; | |
8452 | goto out_free_resources; | |
8453 | } | |
8454 | ||
8455 | for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) { | |
98c56ad3 | 8456 | r = _base_get_port_facts(ioc, i); |
9c067c05 | 8457 | if (r) { |
19a622c3 | 8458 | rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc); |
9c067c05 SP |
8459 | if (rc || (_base_get_port_facts(ioc, i))) |
8460 | goto out_free_resources; | |
8461 | } | |
f92363d1 SR |
8462 | } |
8463 | ||
98c56ad3 | 8464 | r = _base_allocate_memory_pools(ioc); |
f92363d1 SR |
8465 | if (r) |
8466 | goto out_free_resources; | |
8467 | ||
288addd6 SP |
8468 | if (irqpoll_weight > 0) |
8469 | ioc->thresh_hold = irqpoll_weight; | |
8470 | else | |
8471 | ioc->thresh_hold = ioc->hba_queue_depth/4; | |
8472 | ||
320e77ac | 8473 | _base_init_irqpolls(ioc); |
f92363d1 SR |
8474 | init_waitqueue_head(&ioc->reset_wq); |
8475 | ||
8476 | /* allocate memory pd handle bitmask list */ | |
8477 | ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8); | |
8478 | if (ioc->facts.MaxDevHandle % 8) | |
8479 | ioc->pd_handles_sz++; | |
8480 | ioc->pd_handles = kzalloc(ioc->pd_handles_sz, | |
8481 | GFP_KERNEL); | |
8482 | if (!ioc->pd_handles) { | |
8483 | r = -ENOMEM; | |
8484 | goto out_free_resources; | |
8485 | } | |
8486 | ioc->blocking_handles = kzalloc(ioc->pd_handles_sz, | |
8487 | GFP_KERNEL); | |
8488 | if (!ioc->blocking_handles) { | |
8489 | r = -ENOMEM; | |
8490 | goto out_free_resources; | |
8491 | } | |
8492 | ||
c696f7b8 SPS |
8493 | /* allocate memory for pending OS device add list */ |
8494 | ioc->pend_os_device_add_sz = (ioc->facts.MaxDevHandle / 8); | |
8495 | if (ioc->facts.MaxDevHandle % 8) | |
8496 | ioc->pend_os_device_add_sz++; | |
8497 | ioc->pend_os_device_add = kzalloc(ioc->pend_os_device_add_sz, | |
8498 | GFP_KERNEL); | |
3401ecf7 JJB |
8499 | if (!ioc->pend_os_device_add) { |
8500 | r = -ENOMEM; | |
c696f7b8 | 8501 | goto out_free_resources; |
3401ecf7 | 8502 | } |
c696f7b8 SPS |
8503 | |
8504 | ioc->device_remove_in_progress_sz = ioc->pend_os_device_add_sz; | |
8505 | ioc->device_remove_in_progress = | |
8506 | kzalloc(ioc->device_remove_in_progress_sz, GFP_KERNEL); | |
3401ecf7 JJB |
8507 | if (!ioc->device_remove_in_progress) { |
8508 | r = -ENOMEM; | |
c696f7b8 | 8509 | goto out_free_resources; |
3401ecf7 | 8510 | } |
c696f7b8 | 8511 | |
f92363d1 SR |
8512 | ioc->fwfault_debug = mpt3sas_fwfault_debug; |
8513 | ||
8514 | /* base internal command bits */ | |
8515 | mutex_init(&ioc->base_cmds.mutex); | |
8516 | ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
8517 | ioc->base_cmds.status = MPT3_CMD_NOT_USED; | |
8518 | ||
8519 | /* port_enable command bits */ | |
8520 | ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
8521 | ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; | |
8522 | ||
8523 | /* transport internal command bits */ | |
8524 | ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
8525 | ioc->transport_cmds.status = MPT3_CMD_NOT_USED; | |
8526 | mutex_init(&ioc->transport_cmds.mutex); | |
8527 | ||
8528 | /* scsih internal command bits */ | |
8529 | ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
8530 | ioc->scsih_cmds.status = MPT3_CMD_NOT_USED; | |
8531 | mutex_init(&ioc->scsih_cmds.mutex); | |
8532 | ||
8533 | /* task management internal command bits */ | |
8534 | ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
8535 | ioc->tm_cmds.status = MPT3_CMD_NOT_USED; | |
8536 | mutex_init(&ioc->tm_cmds.mutex); | |
8537 | ||
8538 | /* config page internal command bits */ | |
8539 | ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
8540 | ioc->config_cmds.status = MPT3_CMD_NOT_USED; | |
8541 | mutex_init(&ioc->config_cmds.mutex); | |
8542 | ||
8543 | /* ctl module internal command bits */ | |
8544 | ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); | |
8545 | ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL); | |
8546 | ioc->ctl_cmds.status = MPT3_CMD_NOT_USED; | |
8547 | mutex_init(&ioc->ctl_cmds.mutex); | |
8548 | ||
a5dd7efd CJ |
8549 | if (!ioc->base_cmds.reply || !ioc->port_enable_cmds.reply || |
8550 | !ioc->transport_cmds.reply || !ioc->scsih_cmds.reply || | |
8551 | !ioc->tm_cmds.reply || !ioc->config_cmds.reply || | |
8552 | !ioc->ctl_cmds.reply || !ioc->ctl_cmds.sense) { | |
f92363d1 SR |
8553 | r = -ENOMEM; |
8554 | goto out_free_resources; | |
8555 | } | |
8556 | ||
8557 | for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) | |
8558 | ioc->event_masks[i] = -1; | |
8559 | ||
8560 | /* here we enable the events we care about */ | |
8561 | _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY); | |
8562 | _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE); | |
8563 | _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST); | |
8564 | _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE); | |
8565 | _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE); | |
8566 | _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST); | |
8567 | _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME); | |
8568 | _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK); | |
8569 | _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS); | |
8570 | _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED); | |
2d8ce8c9 | 8571 | _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD); |
b99b1993 | 8572 | _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION); |
95540b8e | 8573 | _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR); |
4318c734 SPS |
8574 | if (ioc->hba_mpi_version_belonged == MPI26_VERSION) { |
8575 | if (ioc->is_gen35_ioc) { | |
8576 | _base_unmask_events(ioc, | |
8577 | MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE); | |
8578 | _base_unmask_events(ioc, MPI2_EVENT_PCIE_ENUMERATION); | |
8579 | _base_unmask_events(ioc, | |
8580 | MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST); | |
8581 | } | |
8582 | } | |
98c56ad3 | 8583 | r = _base_make_ioc_operational(ioc); |
19a622c3 SP |
8584 | if (r == -EAGAIN) { |
8585 | r = _base_make_ioc_operational(ioc); | |
8586 | if (r) | |
8587 | goto out_free_resources; | |
8588 | } | |
f92363d1 | 8589 | |
ffedeae1 SP |
8590 | /* |
8591 | * Copy current copy of IOCFacts in prev_fw_facts | |
8592 | * and it will be used during online firmware upgrade. | |
8593 | */ | |
8594 | memcpy(&ioc->prev_fw_facts, &ioc->facts, | |
8595 | sizeof(struct mpt3sas_facts)); | |
8596 | ||
16e179bd | 8597 | ioc->non_operational_loop = 0; |
fce0aa08 | 8598 | ioc->ioc_coredump_loop = 0; |
459325c4 | 8599 | ioc->got_task_abort_from_ioctl = 0; |
f92363d1 SR |
8600 | return 0; |
8601 | ||
8602 | out_free_resources: | |
8603 | ||
8604 | ioc->remove_host = 1; | |
8605 | ||
8606 | mpt3sas_base_free_resources(ioc); | |
8607 | _base_release_memory_pools(ioc); | |
8608 | pci_set_drvdata(ioc->pdev, NULL); | |
8609 | kfree(ioc->cpu_msix_table); | |
7786ab6a SR |
8610 | if (ioc->is_warpdrive) |
8611 | kfree(ioc->reply_post_host_index); | |
f92363d1 SR |
8612 | kfree(ioc->pd_handles); |
8613 | kfree(ioc->blocking_handles); | |
c696f7b8 SPS |
8614 | kfree(ioc->device_remove_in_progress); |
8615 | kfree(ioc->pend_os_device_add); | |
f92363d1 SR |
8616 | kfree(ioc->tm_cmds.reply); |
8617 | kfree(ioc->transport_cmds.reply); | |
8618 | kfree(ioc->scsih_cmds.reply); | |
8619 | kfree(ioc->config_cmds.reply); | |
8620 | kfree(ioc->base_cmds.reply); | |
8621 | kfree(ioc->port_enable_cmds.reply); | |
8622 | kfree(ioc->ctl_cmds.reply); | |
8623 | kfree(ioc->ctl_cmds.sense); | |
8624 | kfree(ioc->pfacts); | |
8625 | ioc->ctl_cmds.reply = NULL; | |
8626 | ioc->base_cmds.reply = NULL; | |
8627 | ioc->tm_cmds.reply = NULL; | |
8628 | ioc->scsih_cmds.reply = NULL; | |
8629 | ioc->transport_cmds.reply = NULL; | |
8630 | ioc->config_cmds.reply = NULL; | |
8631 | ioc->pfacts = NULL; | |
8632 | return r; | |
8633 | } | |
8634 | ||
8635 | ||
8636 | /** | |
8637 | * mpt3sas_base_detach - remove controller instance | |
8638 | * @ioc: per adapter object | |
f92363d1 SR |
8639 | */ |
8640 | void | |
8641 | mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc) | |
8642 | { | |
919d8a3f | 8643 | dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); |
f92363d1 SR |
8644 | |
8645 | mpt3sas_base_stop_watchdog(ioc); | |
8646 | mpt3sas_base_free_resources(ioc); | |
8647 | _base_release_memory_pools(ioc); | |
22a923c3 | 8648 | mpt3sas_free_enclosure_list(ioc); |
f92363d1 SR |
8649 | pci_set_drvdata(ioc->pdev, NULL); |
8650 | kfree(ioc->cpu_msix_table); | |
7786ab6a SR |
8651 | if (ioc->is_warpdrive) |
8652 | kfree(ioc->reply_post_host_index); | |
f92363d1 SR |
8653 | kfree(ioc->pd_handles); |
8654 | kfree(ioc->blocking_handles); | |
c696f7b8 SPS |
8655 | kfree(ioc->device_remove_in_progress); |
8656 | kfree(ioc->pend_os_device_add); | |
f92363d1 SR |
8657 | kfree(ioc->pfacts); |
8658 | kfree(ioc->ctl_cmds.reply); | |
8659 | kfree(ioc->ctl_cmds.sense); | |
8660 | kfree(ioc->base_cmds.reply); | |
8661 | kfree(ioc->port_enable_cmds.reply); | |
8662 | kfree(ioc->tm_cmds.reply); | |
8663 | kfree(ioc->transport_cmds.reply); | |
8664 | kfree(ioc->scsih_cmds.reply); | |
8665 | kfree(ioc->config_cmds.reply); | |
8666 | } | |
8667 | ||
8668 | /** | |
c7a35705 | 8669 | * _base_pre_reset_handler - pre reset handler |
f92363d1 | 8670 | * @ioc: per adapter object |
f92363d1 | 8671 | */ |
c7a35705 | 8672 | static void _base_pre_reset_handler(struct MPT3SAS_ADAPTER *ioc) |
f92363d1 | 8673 | { |
c7a35705 BVA |
8674 | mpt3sas_scsih_pre_reset_handler(ioc); |
8675 | mpt3sas_ctl_pre_reset_handler(ioc); | |
919d8a3f | 8676 | dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_PRE_RESET\n", __func__)); |
c7a35705 BVA |
8677 | } |
8678 | ||
8679 | /** | |
36c6c7f7 | 8680 | * _base_clear_outstanding_mpt_commands - clears outstanding mpt commands |
c7a35705 BVA |
8681 | * @ioc: per adapter object |
8682 | */ | |
36c6c7f7 SR |
8683 | static void |
8684 | _base_clear_outstanding_mpt_commands(struct MPT3SAS_ADAPTER *ioc) | |
c7a35705 | 8685 | { |
36c6c7f7 SR |
8686 | dtmprintk(ioc, |
8687 | ioc_info(ioc, "%s: clear outstanding mpt cmds\n", __func__)); | |
c7a35705 BVA |
8688 | if (ioc->transport_cmds.status & MPT3_CMD_PENDING) { |
8689 | ioc->transport_cmds.status |= MPT3_CMD_RESET; | |
8690 | mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid); | |
8691 | complete(&ioc->transport_cmds.done); | |
8692 | } | |
8693 | if (ioc->base_cmds.status & MPT3_CMD_PENDING) { | |
8694 | ioc->base_cmds.status |= MPT3_CMD_RESET; | |
8695 | mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid); | |
8696 | complete(&ioc->base_cmds.done); | |
8697 | } | |
8698 | if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { | |
8699 | ioc->port_enable_failed = 1; | |
8700 | ioc->port_enable_cmds.status |= MPT3_CMD_RESET; | |
8701 | mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid); | |
8702 | if (ioc->is_driver_loading) { | |
8703 | ioc->start_scan_failed = | |
8704 | MPI2_IOCSTATUS_INTERNAL_ERROR; | |
8705 | ioc->start_scan = 0; | |
c7a35705 BVA |
8706 | } else { |
8707 | complete(&ioc->port_enable_cmds.done); | |
f92363d1 | 8708 | } |
f92363d1 | 8709 | } |
c7a35705 BVA |
8710 | if (ioc->config_cmds.status & MPT3_CMD_PENDING) { |
8711 | ioc->config_cmds.status |= MPT3_CMD_RESET; | |
8712 | mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid); | |
8713 | ioc->config_cmds.smid = USHRT_MAX; | |
8714 | complete(&ioc->config_cmds.done); | |
8715 | } | |
8716 | } | |
8717 | ||
36c6c7f7 SR |
8718 | /** |
8719 | * _base_clear_outstanding_commands - clear all outstanding commands | |
8720 | * @ioc: per adapter object | |
8721 | */ | |
8722 | static void _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc) | |
8723 | { | |
8724 | mpt3sas_scsih_clear_outstanding_scsi_tm_commands(ioc); | |
8725 | mpt3sas_ctl_clear_outstanding_ioctls(ioc); | |
8726 | _base_clear_outstanding_mpt_commands(ioc); | |
8727 | } | |
8728 | ||
c7a35705 BVA |
8729 | /** |
8730 | * _base_reset_done_handler - reset done handler | |
8731 | * @ioc: per adapter object | |
8732 | */ | |
8733 | static void _base_reset_done_handler(struct MPT3SAS_ADAPTER *ioc) | |
8734 | { | |
8735 | mpt3sas_scsih_reset_done_handler(ioc); | |
8736 | mpt3sas_ctl_reset_done_handler(ioc); | |
919d8a3f | 8737 | dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_DONE_RESET\n", __func__)); |
f92363d1 SR |
8738 | } |
8739 | ||
8740 | /** | |
c666d3be | 8741 | * mpt3sas_wait_for_commands_to_complete - reset controller |
f92363d1 | 8742 | * @ioc: Pointer to MPT_ADAPTER structure |
f92363d1 | 8743 | * |
272e253c | 8744 | * This function is waiting 10s for all pending commands to complete |
f92363d1 SR |
8745 | * prior to putting controller in reset. |
8746 | */ | |
c666d3be SR |
8747 | void |
8748 | mpt3sas_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc) | |
f92363d1 SR |
8749 | { |
8750 | u32 ioc_state; | |
f92363d1 SR |
8751 | |
8752 | ioc->pending_io_count = 0; | |
f92363d1 SR |
8753 | |
8754 | ioc_state = mpt3sas_base_get_iocstate(ioc, 0); | |
8755 | if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) | |
8756 | return; | |
8757 | ||
8758 | /* pending command count */ | |
c84b023a | 8759 | ioc->pending_io_count = scsi_host_busy(ioc->shost); |
f92363d1 SR |
8760 | |
8761 | if (!ioc->pending_io_count) | |
8762 | return; | |
8763 | ||
8764 | /* wait for pending commands to complete */ | |
8765 | wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ); | |
8766 | } | |
8767 | ||
ffedeae1 SP |
8768 | /** |
8769 | * _base_check_ioc_facts_changes - Look for increase/decrease of IOCFacts | |
8770 | * attributes during online firmware upgrade and update the corresponding | |
8771 | * IOC variables accordingly. | |
8772 | * | |
8773 | * @ioc: Pointer to MPT_ADAPTER structure | |
8774 | */ | |
8775 | static int | |
8776 | _base_check_ioc_facts_changes(struct MPT3SAS_ADAPTER *ioc) | |
8777 | { | |
8778 | u16 pd_handles_sz; | |
8779 | void *pd_handles = NULL, *blocking_handles = NULL; | |
8780 | void *pend_os_device_add = NULL, *device_remove_in_progress = NULL; | |
8781 | struct mpt3sas_facts *old_facts = &ioc->prev_fw_facts; | |
8782 | ||
8783 | if (ioc->facts.MaxDevHandle > old_facts->MaxDevHandle) { | |
8784 | pd_handles_sz = (ioc->facts.MaxDevHandle / 8); | |
8785 | if (ioc->facts.MaxDevHandle % 8) | |
8786 | pd_handles_sz++; | |
8787 | ||
8788 | pd_handles = krealloc(ioc->pd_handles, pd_handles_sz, | |
8789 | GFP_KERNEL); | |
8790 | if (!pd_handles) { | |
8791 | ioc_info(ioc, | |
8792 | "Unable to allocate the memory for pd_handles of sz: %d\n", | |
8793 | pd_handles_sz); | |
8794 | return -ENOMEM; | |
8795 | } | |
8796 | memset(pd_handles + ioc->pd_handles_sz, 0, | |
8797 | (pd_handles_sz - ioc->pd_handles_sz)); | |
8798 | ioc->pd_handles = pd_handles; | |
8799 | ||
8800 | blocking_handles = krealloc(ioc->blocking_handles, | |
8801 | pd_handles_sz, GFP_KERNEL); | |
8802 | if (!blocking_handles) { | |
8803 | ioc_info(ioc, | |
8804 | "Unable to allocate the memory for " | |
8805 | "blocking_handles of sz: %d\n", | |
8806 | pd_handles_sz); | |
8807 | return -ENOMEM; | |
8808 | } | |
8809 | memset(blocking_handles + ioc->pd_handles_sz, 0, | |
8810 | (pd_handles_sz - ioc->pd_handles_sz)); | |
8811 | ioc->blocking_handles = blocking_handles; | |
8812 | ioc->pd_handles_sz = pd_handles_sz; | |
8813 | ||
8814 | pend_os_device_add = krealloc(ioc->pend_os_device_add, | |
8815 | pd_handles_sz, GFP_KERNEL); | |
8816 | if (!pend_os_device_add) { | |
8817 | ioc_info(ioc, | |
8818 | "Unable to allocate the memory for pend_os_device_add of sz: %d\n", | |
8819 | pd_handles_sz); | |
8820 | return -ENOMEM; | |
8821 | } | |
8822 | memset(pend_os_device_add + ioc->pend_os_device_add_sz, 0, | |
8823 | (pd_handles_sz - ioc->pend_os_device_add_sz)); | |
8824 | ioc->pend_os_device_add = pend_os_device_add; | |
8825 | ioc->pend_os_device_add_sz = pd_handles_sz; | |
8826 | ||
8827 | device_remove_in_progress = krealloc( | |
8828 | ioc->device_remove_in_progress, pd_handles_sz, GFP_KERNEL); | |
8829 | if (!device_remove_in_progress) { | |
8830 | ioc_info(ioc, | |
8831 | "Unable to allocate the memory for " | |
8832 | "device_remove_in_progress of sz: %d\n " | |
8833 | , pd_handles_sz); | |
8834 | return -ENOMEM; | |
8835 | } | |
8836 | memset(device_remove_in_progress + | |
8837 | ioc->device_remove_in_progress_sz, 0, | |
8838 | (pd_handles_sz - ioc->device_remove_in_progress_sz)); | |
8839 | ioc->device_remove_in_progress = device_remove_in_progress; | |
8840 | ioc->device_remove_in_progress_sz = pd_handles_sz; | |
8841 | } | |
8842 | ||
8843 | memcpy(&ioc->prev_fw_facts, &ioc->facts, sizeof(struct mpt3sas_facts)); | |
8844 | return 0; | |
8845 | } | |
8846 | ||
f92363d1 SR |
8847 | /** |
8848 | * mpt3sas_base_hard_reset_handler - reset controller | |
8849 | * @ioc: Pointer to MPT_ADAPTER structure | |
f92363d1 SR |
8850 | * @type: FORCE_BIG_HAMMER or SOFT_RESET |
8851 | * | |
4beb4867 | 8852 | * Return: 0 for success, non-zero for failure. |
f92363d1 SR |
8853 | */ |
8854 | int | |
98c56ad3 | 8855 | mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, |
f92363d1 SR |
8856 | enum reset_type type) |
8857 | { | |
8858 | int r; | |
8859 | unsigned long flags; | |
8860 | u32 ioc_state; | |
8861 | u8 is_fault = 0, is_trigger = 0; | |
8862 | ||
919d8a3f | 8863 | dtmprintk(ioc, ioc_info(ioc, "%s: enter\n", __func__)); |
f92363d1 SR |
8864 | |
8865 | if (ioc->pci_error_recovery) { | |
919d8a3f | 8866 | ioc_err(ioc, "%s: pci error recovery reset\n", __func__); |
f92363d1 SR |
8867 | r = 0; |
8868 | goto out_unlocked; | |
8869 | } | |
8870 | ||
8871 | if (mpt3sas_fwfault_debug) | |
8872 | mpt3sas_halt_firmware(ioc); | |
8873 | ||
f92363d1 | 8874 | /* wait for an active reset in progress to complete */ |
982ea6f9 | 8875 | mutex_lock(&ioc->reset_in_progress_mutex); |
f92363d1 SR |
8876 | |
8877 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
8878 | ioc->shost_recovery = 1; | |
8879 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
8880 | ||
8881 | if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & | |
8882 | MPT3_DIAG_BUFFER_IS_REGISTERED) && | |
8883 | (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & | |
8884 | MPT3_DIAG_BUFFER_IS_RELEASED))) { | |
8885 | is_trigger = 1; | |
8886 | ioc_state = mpt3sas_base_get_iocstate(ioc, 0); | |
fce0aa08 SR |
8887 | if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT || |
8888 | (ioc_state & MPI2_IOC_STATE_MASK) == | |
688c1a0a | 8889 | MPI2_IOC_STATE_COREDUMP) { |
f92363d1 | 8890 | is_fault = 1; |
688c1a0a SP |
8891 | ioc->htb_rel.trigger_info_dwords[1] = |
8892 | (ioc_state & MPI2_DOORBELL_DATA_MASK); | |
8893 | } | |
f92363d1 | 8894 | } |
c7a35705 | 8895 | _base_pre_reset_handler(ioc); |
c666d3be | 8896 | mpt3sas_wait_for_commands_to_complete(ioc); |
5afa9d44 | 8897 | mpt3sas_base_mask_interrupts(ioc); |
432bc7ca | 8898 | mpt3sas_base_pause_mq_polling(ioc); |
fae21608 | 8899 | r = mpt3sas_base_make_ioc_ready(ioc, type); |
f92363d1 SR |
8900 | if (r) |
8901 | goto out; | |
36c6c7f7 | 8902 | _base_clear_outstanding_commands(ioc); |
f92363d1 SR |
8903 | |
8904 | /* If this hard reset is called while port enable is active, then | |
8905 | * there is no reason to call make_ioc_operational | |
8906 | */ | |
8907 | if (ioc->is_driver_loading && ioc->port_enable_failed) { | |
8908 | ioc->remove_host = 1; | |
8909 | r = -EFAULT; | |
8910 | goto out; | |
8911 | } | |
98c56ad3 | 8912 | r = _base_get_ioc_facts(ioc); |
f92363d1 SR |
8913 | if (r) |
8914 | goto out; | |
9b05c91a | 8915 | |
ffedeae1 SP |
8916 | r = _base_check_ioc_facts_changes(ioc); |
8917 | if (r) { | |
8918 | ioc_info(ioc, | |
8919 | "Some of the parameters got changed in this new firmware" | |
8920 | " image and it requires system reboot\n"); | |
8921 | goto out; | |
8922 | } | |
9b05c91a SR |
8923 | if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable) |
8924 | panic("%s: Issue occurred with flashing controller firmware." | |
8925 | "Please reboot the system and ensure that the correct" | |
8926 | " firmware version is running\n", ioc->name); | |
8927 | ||
98c56ad3 | 8928 | r = _base_make_ioc_operational(ioc); |
f92363d1 | 8929 | if (!r) |
c7a35705 | 8930 | _base_reset_done_handler(ioc); |
f92363d1 SR |
8931 | |
8932 | out: | |
5b061980 | 8933 | ioc_info(ioc, "%s: %s\n", __func__, r == 0 ? "SUCCESS" : "FAILED"); |
f92363d1 SR |
8934 | |
8935 | spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); | |
f92363d1 SR |
8936 | ioc->shost_recovery = 0; |
8937 | spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); | |
8938 | ioc->ioc_reset_count++; | |
8939 | mutex_unlock(&ioc->reset_in_progress_mutex); | |
432bc7ca | 8940 | mpt3sas_base_resume_mq_polling(ioc); |
f92363d1 SR |
8941 | |
8942 | out_unlocked: | |
8943 | if ((r == 0) && is_trigger) { | |
8944 | if (is_fault) | |
8945 | mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT); | |
8946 | else | |
8947 | mpt3sas_trigger_master(ioc, | |
8948 | MASTER_TRIGGER_ADAPTER_RESET); | |
8949 | } | |
919d8a3f | 8950 | dtmprintk(ioc, ioc_info(ioc, "%s: exit\n", __func__)); |
f92363d1 SR |
8951 | return r; |
8952 | } |