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megaraid_sas: driver version upgrade and remove some meta data of driver
[linux-2.6-block.git] / drivers / scsi / megaraid / megaraid_sas.h
CommitLineData
c4a3e0a5 1/*
3f1530c1 2 * Linux MegaRAID driver for SAS based RAID controllers
c4a3e0a5 3 *
ae59057b 4 * Copyright (c) 2003-2012 LSI Corporation.
c4a3e0a5 5 *
3f1530c1 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
c4a3e0a5 10 *
3f1530c1 11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
c4a3e0a5 15 *
3f1530c1 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * FILE: megaraid_sas.h
21 *
22 * Authors: LSI Corporation
23 *
24 * Send feedback to: <megaraidlinux@lsi.com>
25 *
26 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
27 * ATTN: Linuxraid
c4a3e0a5
BS		 28 */
29
30#ifndef LSI_MEGARAID_SAS_H
31#define LSI_MEGARAID_SAS_H
32
a69b74d3 33/*
c4a3e0a5
BS		 34 * MegaRAID SAS Driver meta data
35 */
d98a6deb 36#define MEGASAS_VERSION "06.805.06.01-rc1"
0e98936c
SP		 37
38/*
39 * Device IDs
40 */
41#define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
af7a5647 42#define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
0e98936c 43#define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
6610a6b3
YB		 44#define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
45#define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
87911122
YB		 46#define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
47#define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
9c915a8c 48#define PCI_DEVICE_ID_LSI_FUSION 0x005b
229fe47c 49#define PCI_DEVICE_ID_LSI_PLASMA 0x002f
36807e67 50#define PCI_DEVICE_ID_LSI_INVADER 0x005d
21d3c710 51#define PCI_DEVICE_ID_LSI_FURY 0x005f
0e98936c 52
39b72c3c
SS		 53/*
54 * Intel HBA SSDIDs
55 */
56#define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
57#define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
58#define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
59#define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
60#define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
61#define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
62
63/*
64 * Intel HBA branding
65 */
66#define MEGARAID_INTEL_RS3DC080_BRANDING \
67 "Intel(R) RAID Controller RS3DC080"
68#define MEGARAID_INTEL_RS3DC040_BRANDING \
69 "Intel(R) RAID Controller RS3DC040"
70#define MEGARAID_INTEL_RS3SC008_BRANDING \
71 "Intel(R) RAID Controller RS3SC008"
72#define MEGARAID_INTEL_RS3MC044_BRANDING \
73 "Intel(R) RAID Controller RS3MC044"
74#define MEGARAID_INTEL_RS3WC080_BRANDING \
75 "Intel(R) RAID Controller RS3WC080"
76#define MEGARAID_INTEL_RS3WC040_BRANDING \
77 "Intel(R) RAID Controller RS3WC040"
78
c4a3e0a5
BS		 79/*
80 * =====================================
81 * MegaRAID SAS MFI firmware definitions
82 * =====================================
83 */
84
85/*
86 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
87 * protocol between the software and firmware. Commands are issued using
88 * "message frames"
89 */
90
a69b74d3 91/*
c4a3e0a5
BS		 92 * FW posts its state in upper 4 bits of outbound_msg_0 register
93 */
94#define MFI_STATE_MASK 0xF0000000
95#define MFI_STATE_UNDEFINED 0x00000000
96#define MFI_STATE_BB_INIT 0x10000000
97#define MFI_STATE_FW_INIT 0x40000000
98#define MFI_STATE_WAIT_HANDSHAKE 0x60000000
99#define MFI_STATE_FW_INIT_2 0x70000000
100#define MFI_STATE_DEVICE_SCAN 0x80000000
e3bbff9f 101#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
c4a3e0a5
BS		 102#define MFI_STATE_FLUSH_CACHE 0xA0000000
103#define MFI_STATE_READY 0xB0000000
104#define MFI_STATE_OPERATIONAL 0xC0000000
105#define MFI_STATE_FAULT 0xF0000000
fc62b3fc
SS		 106#define MFI_STATE_FORCE_OCR 0x00000080
107#define MFI_STATE_DMADONE 0x00000008
108#define MFI_STATE_CRASH_DUMP_DONE 0x00000004
7e70e733 109#define MFI_RESET_REQUIRED 0x00000001
110#define MFI_RESET_ADAPTER 0x00000002
c4a3e0a5
BS		 111#define MEGAMFI_FRAME_SIZE 64
112
a69b74d3 113/*
c4a3e0a5
BS		 114 * During FW init, clear pending cmds & reset state using inbound_msg_0
115 *
116 * ABORT : Abort all pending cmds
117 * READY : Move from OPERATIONAL to READY state; discard queue info
118 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
119 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
e3bbff9f
SP		 120 * HOTPLUG : Resume from Hotplug
121 * MFI_STOP_ADP : Send signal to FW to stop processing
c4a3e0a5 122 */
39a98554 123#define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
124#define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
125#define DIAG_WRITE_ENABLE (0x00000080)
126#define DIAG_RESET_ADAPTER (0x00000004)
127
128#define MFI_ADP_RESET 0x00000040
e3bbff9f 129#define MFI_INIT_ABORT 0x00000001
c4a3e0a5
BS		 130#define MFI_INIT_READY 0x00000002
131#define MFI_INIT_MFIMODE 0x00000004
132#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
e3bbff9f
SP		 133#define MFI_INIT_HOTPLUG 0x00000010
134#define MFI_STOP_ADP 0x00000020
135#define MFI_RESET_FLAGS MFI_INIT_READY| \
136 MFI_INIT_MFIMODE| \
137 MFI_INIT_ABORT
c4a3e0a5 138
a69b74d3 139/*
c4a3e0a5
BS		 140 * MFI frame flags
141 */
142#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
143#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
144#define MFI_FRAME_SGL32 0x0000
145#define MFI_FRAME_SGL64 0x0002
146#define MFI_FRAME_SENSE32 0x0000
147#define MFI_FRAME_SENSE64 0x0004
148#define MFI_FRAME_DIR_NONE 0x0000
149#define MFI_FRAME_DIR_WRITE 0x0008
150#define MFI_FRAME_DIR_READ 0x0010
151#define MFI_FRAME_DIR_BOTH 0x0018
f4c9a131 152#define MFI_FRAME_IEEE 0x0020
c4a3e0a5 153
a69b74d3 154/*
c4a3e0a5
BS		 155 * Definition for cmd_status
156 */
157#define MFI_CMD_STATUS_POLL_MODE 0xFF
158
a69b74d3 159/*
c4a3e0a5
BS		 160 * MFI command opcodes
161 */
162#define MFI_CMD_INIT 0x00
163#define MFI_CMD_LD_READ 0x01
164#define MFI_CMD_LD_WRITE 0x02
165#define MFI_CMD_LD_SCSI_IO 0x03
166#define MFI_CMD_PD_SCSI_IO 0x04
167#define MFI_CMD_DCMD 0x05
168#define MFI_CMD_ABORT 0x06
169#define MFI_CMD_SMP 0x07
170#define MFI_CMD_STP 0x08
e5f93a36 171#define MFI_CMD_INVALID 0xff
c4a3e0a5
BS		 172
173#define MR_DCMD_CTRL_GET_INFO 0x01010000
bdc6fb8d 174#define MR_DCMD_LD_GET_LIST 0x03010000
21c9e160 175#define MR_DCMD_LD_LIST_QUERY 0x03010100
c4a3e0a5
BS		 176
177#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
178#define MR_FLUSH_CTRL_CACHE 0x01
179#define MR_FLUSH_DISK_CACHE 0x02
180
181#define MR_DCMD_CTRL_SHUTDOWN 0x01050000
31ea7088 182#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
c4a3e0a5
BS		 183#define MR_ENABLE_DRIVE_SPINDOWN 0x01
184
185#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
186#define MR_DCMD_CTRL_EVENT_GET 0x01040300
187#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
188#define MR_DCMD_LD_GET_PROPERTIES 0x03030000
189
190#define MR_DCMD_CLUSTER 0x08000000
191#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
192#define MR_DCMD_CLUSTER_RESET_LD 0x08010200
81e403ce 193#define MR_DCMD_PD_LIST_QUERY 0x02010100
c4a3e0a5 194
fc62b3fc
SS		 195#define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100
196#define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600)
197
bc93d425
SS		 198/*
199 * Global functions
200 */
201extern u8 MR_ValidateMapInfo(struct megasas_instance *instance);
202
203
a69b74d3 204/*
c4a3e0a5
BS		 205 * MFI command completion codes
206 */
207enum MFI_STAT {
208 MFI_STAT_OK = 0x00,
209 MFI_STAT_INVALID_CMD = 0x01,
210 MFI_STAT_INVALID_DCMD = 0x02,
211 MFI_STAT_INVALID_PARAMETER = 0x03,
212 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
213 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
214 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
215 MFI_STAT_APP_IN_USE = 0x07,
216 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
217 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
218 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
219 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
220 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
221 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
222 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
223 MFI_STAT_FLASH_BUSY = 0x0f,
224 MFI_STAT_FLASH_ERROR = 0x10,
225 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
226 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
227 MFI_STAT_FLASH_NOT_OPEN = 0x13,
228 MFI_STAT_FLASH_NOT_STARTED = 0x14,
229 MFI_STAT_FLUSH_FAILED = 0x15,
230 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
231 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
232 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
233 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
234 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
235 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
236 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
237 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
238 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
239 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
240 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
241 MFI_STAT_MFC_HW_ERROR = 0x21,
242 MFI_STAT_NO_HW_PRESENT = 0x22,
243 MFI_STAT_NOT_FOUND = 0x23,
244 MFI_STAT_NOT_IN_ENCL = 0x24,
245 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
246 MFI_STAT_PD_TYPE_WRONG = 0x26,
247 MFI_STAT_PR_DISABLED = 0x27,
248 MFI_STAT_ROW_INDEX_INVALID = 0x28,
249 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
250 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
251 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
252 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
253 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
254 MFI_STAT_SCSI_IO_FAILED = 0x2e,
255 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
256 MFI_STAT_SHUTDOWN_FAILED = 0x30,
257 MFI_STAT_TIME_NOT_SET = 0x31,
258 MFI_STAT_WRONG_STATE = 0x32,
259 MFI_STAT_LD_OFFLINE = 0x33,
260 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
261 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
262 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
263 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
264 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
36807e67 265 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
c4a3e0a5
BS		 266
267 MFI_STAT_INVALID_STATUS = 0xFF
268};
269
fc62b3fc
SS		 270/*
271 * Crash dump related defines
272 */
273#define MAX_CRASH_DUMP_SIZE 512
274#define CRASH_DMA_BUF_SIZE (1024 * 1024)
275
276enum MR_FW_CRASH_DUMP_STATE {
277 UNAVAILABLE = 0,
278 AVAILABLE = 1,
279 COPYING = 2,
280 COPIED = 3,
281 COPY_ERROR = 4,
282};
283
284enum _MR_CRASH_BUF_STATUS {
285 MR_CRASH_BUF_TURN_OFF = 0,
286 MR_CRASH_BUF_TURN_ON = 1,
287};
288
c4a3e0a5
BS		 289/*
290 * Number of mailbox bytes in DCMD message frame
291 */
292#define MFI_MBOX_SIZE 12
293
294enum MR_EVT_CLASS {
295
296 MR_EVT_CLASS_DEBUG = -2,
297 MR_EVT_CLASS_PROGRESS = -1,
298 MR_EVT_CLASS_INFO = 0,
299 MR_EVT_CLASS_WARNING = 1,
300 MR_EVT_CLASS_CRITICAL = 2,
301 MR_EVT_CLASS_FATAL = 3,
302 MR_EVT_CLASS_DEAD = 4,
303
304};
305
306enum MR_EVT_LOCALE {
307
308 MR_EVT_LOCALE_LD = 0x0001,
309 MR_EVT_LOCALE_PD = 0x0002,
310 MR_EVT_LOCALE_ENCL = 0x0004,
311 MR_EVT_LOCALE_BBU = 0x0008,
312 MR_EVT_LOCALE_SAS = 0x0010,
313 MR_EVT_LOCALE_CTRL = 0x0020,
314 MR_EVT_LOCALE_CONFIG = 0x0040,
315 MR_EVT_LOCALE_CLUSTER = 0x0080,
316 MR_EVT_LOCALE_ALL = 0xffff,
317
318};
319
320enum MR_EVT_ARGS {
321
322 MR_EVT_ARGS_NONE,
323 MR_EVT_ARGS_CDB_SENSE,
324 MR_EVT_ARGS_LD,
325 MR_EVT_ARGS_LD_COUNT,
326 MR_EVT_ARGS_LD_LBA,
327 MR_EVT_ARGS_LD_OWNER,
328 MR_EVT_ARGS_LD_LBA_PD_LBA,
329 MR_EVT_ARGS_LD_PROG,
330 MR_EVT_ARGS_LD_STATE,
331 MR_EVT_ARGS_LD_STRIP,
332 MR_EVT_ARGS_PD,
333 MR_EVT_ARGS_PD_ERR,
334 MR_EVT_ARGS_PD_LBA,
335 MR_EVT_ARGS_PD_LBA_LD,
336 MR_EVT_ARGS_PD_PROG,
337 MR_EVT_ARGS_PD_STATE,
338 MR_EVT_ARGS_PCI,
339 MR_EVT_ARGS_RATE,
340 MR_EVT_ARGS_STR,
341 MR_EVT_ARGS_TIME,
342 MR_EVT_ARGS_ECC,
81e403ce
YB		 343 MR_EVT_ARGS_LD_PROP,
344 MR_EVT_ARGS_PD_SPARE,
345 MR_EVT_ARGS_PD_INDEX,
346 MR_EVT_ARGS_DIAG_PASS,
347 MR_EVT_ARGS_DIAG_FAIL,
348 MR_EVT_ARGS_PD_LBA_LBA,
349 MR_EVT_ARGS_PORT_PHY,
350 MR_EVT_ARGS_PD_MISSING,
351 MR_EVT_ARGS_PD_ADDRESS,
352 MR_EVT_ARGS_BITMAP,
353 MR_EVT_ARGS_CONNECTOR,
354 MR_EVT_ARGS_PD_PD,
355 MR_EVT_ARGS_PD_FRU,
356 MR_EVT_ARGS_PD_PATHINFO,
357 MR_EVT_ARGS_PD_POWER_STATE,
358 MR_EVT_ARGS_GENERIC,
359};
c4a3e0a5 360
81e403ce
YB		 361/*
362 * define constants for device list query options
363 */
364enum MR_PD_QUERY_TYPE {
365 MR_PD_QUERY_TYPE_ALL = 0,
366 MR_PD_QUERY_TYPE_STATE = 1,
367 MR_PD_QUERY_TYPE_POWER_STATE = 2,
368 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
369 MR_PD_QUERY_TYPE_SPEED = 4,
370 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
c4a3e0a5
BS		 371};
372
21c9e160 373enum MR_LD_QUERY_TYPE {
374 MR_LD_QUERY_TYPE_ALL = 0,
375 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
376 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2,
377 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3,
378 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4,
379};
380
381
7e8a75f4
YB		 382#define MR_EVT_CFG_CLEARED 0x0004
383#define MR_EVT_LD_STATE_CHANGE 0x0051
384#define MR_EVT_PD_INSERTED 0x005b
385#define MR_EVT_PD_REMOVED 0x0070
386#define MR_EVT_LD_CREATED 0x008a
387#define MR_EVT_LD_DELETED 0x008b
388#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
389#define MR_EVT_LD_OFFLINE 0x00fc
390#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
7e8a75f4 391
81e403ce
YB		 392enum MR_PD_STATE {
393 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
394 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
395 MR_PD_STATE_HOT_SPARE = 0x02,
396 MR_PD_STATE_OFFLINE = 0x10,
397 MR_PD_STATE_FAILED = 0x11,
398 MR_PD_STATE_REBUILD = 0x14,
399 MR_PD_STATE_ONLINE = 0x18,
400 MR_PD_STATE_COPYBACK = 0x20,
401 MR_PD_STATE_SYSTEM = 0x40,
402 };
403
404
405 /*
406 * defines the physical drive address structure
407 */
408struct MR_PD_ADDRESS {
409 u16 deviceId;
410 u16 enclDeviceId;
411
412 union {
413 struct {
414 u8 enclIndex;
415 u8 slotNumber;
416 } mrPdAddress;
417 struct {
418 u8 enclPosition;
419 u8 enclConnectorIndex;
420 } mrEnclAddress;
421 };
422 u8 scsiDevType;
423 union {
424 u8 connectedPortBitmap;
425 u8 connectedPortNumbers;
426 };
427 u64 sasAddr[2];
428} __packed;
429
430/*
431 * defines the physical drive list structure
432 */
433struct MR_PD_LIST {
434 u32 size;
435 u32 count;
436 struct MR_PD_ADDRESS addr[1];
437} __packed;
438
439struct megasas_pd_list {
440 u16 tid;
441 u8 driveType;
442 u8 driveState;
443} __packed;
444
bdc6fb8d
YB		 445 /*
446 * defines the logical drive reference structure
447 */
448union MR_LD_REF {
449 struct {
450 u8 targetId;
451 u8 reserved;
452 u16 seqNum;
453 };
454 u32 ref;
455} __packed;
456
457/*
458 * defines the logical drive list structure
459 */
460struct MR_LD_LIST {
461 u32 ldCount;
462 u32 reserved;
463 struct {
464 union MR_LD_REF ref;
465 u8 state;
466 u8 reserved[3];
467 u64 size;
51087a86 468 } ldList[MAX_LOGICAL_DRIVES_EXT];
bdc6fb8d
YB		 469} __packed;
470
21c9e160 471struct MR_LD_TARGETID_LIST {
472 u32 size;
473 u32 count;
474 u8 pad[3];
51087a86 475 u8 targetId[MAX_LOGICAL_DRIVES_EXT];
21c9e160 476};
477
478
c4a3e0a5
BS		 479/*
480 * SAS controller properties
481 */
482struct megasas_ctrl_prop {
483
484 u16 seq_num;
485 u16 pred_fail_poll_interval;
486 u16 intr_throttle_count;
487 u16 intr_throttle_timeouts;
488 u8 rebuild_rate;
489 u8 patrol_read_rate;
490 u8 bgi_rate;
491 u8 cc_rate;
492 u8 recon_rate;
493 u8 cache_flush_interval;
494 u8 spinup_drv_count;
495 u8 spinup_delay;
496 u8 cluster_enable;
497 u8 coercion_mode;
498 u8 alarm_enable;
499 u8 disable_auto_rebuild;
500 u8 disable_battery_warn;
501 u8 ecc_bucket_size;
502 u16 ecc_bucket_leak_rate;
503 u8 restore_hotspare_on_insertion;
504 u8 expose_encl_devices;
39a98554 505 u8 maintainPdFailHistory;
506 u8 disallowHostRequestReordering;
507 u8 abortCCOnError;
508 u8 loadBalanceMode;
509 u8 disableAutoDetectBackplane;
510
511 u8 snapVDSpace;
512
513 /*
514 * Add properties that can be controlled by
515 * a bit in the following structure.
516 */
39a98554 517 struct {
94cd65dd
SS		 518#if defined(__BIG_ENDIAN_BITFIELD)
519 u32 reserved:18;
520 u32 enableJBOD:1;
521 u32 disableSpinDownHS:1;
522 u32 allowBootWithPinnedCache:1;
523 u32 disableOnlineCtrlReset:1;
524 u32 enableSecretKeyControl:1;
525 u32 autoEnhancedImport:1;
526 u32 enableSpinDownUnconfigured:1;
527 u32 SSDPatrolReadEnabled:1;
528 u32 SSDSMARTerEnabled:1;
529 u32 disableNCQ:1;
530 u32 useFdeOnly:1;
531 u32 prCorrectUnconfiguredAreas:1;
532 u32 SMARTerEnabled:1;
533 u32 copyBackDisabled:1;
534#else
535 u32 copyBackDisabled:1;
536 u32 SMARTerEnabled:1;
537 u32 prCorrectUnconfiguredAreas:1;
538 u32 useFdeOnly:1;
539 u32 disableNCQ:1;
540 u32 SSDSMARTerEnabled:1;
541 u32 SSDPatrolReadEnabled:1;
542 u32 enableSpinDownUnconfigured:1;
543 u32 autoEnhancedImport:1;
544 u32 enableSecretKeyControl:1;
545 u32 disableOnlineCtrlReset:1;
546 u32 allowBootWithPinnedCache:1;
547 u32 disableSpinDownHS:1;
548 u32 enableJBOD:1;
549 u32 reserved:18;
550#endif
39a98554 551 } OnOffProperties;
552 u8 autoSnapVDSpace;
553 u8 viewSpace;
554 u16 spinDownTime;
555 u8 reserved[24];
81e403ce 556} __packed;
c4a3e0a5
BS		 557
558/*
559 * SAS controller information
560 */
561struct megasas_ctrl_info {
562
563 /*
564 * PCI device information
565 */
566 struct {
567
568 u16 vendor_id;
569 u16 device_id;
570 u16 sub_vendor_id;
571 u16 sub_device_id;
572 u8 reserved[24];
573
574 } __attribute__ ((packed)) pci;
575
576 /*
577 * Host interface information
578 */
579 struct {
580
581 u8 PCIX:1;
582 u8 PCIE:1;
583 u8 iSCSI:1;
584 u8 SAS_3G:1;
229fe47c 585 u8 SRIOV:1;
586 u8 reserved_0:3;
c4a3e0a5
BS		 587 u8 reserved_1[6];
588 u8 port_count;
589 u64 port_addr[8];
590
591 } __attribute__ ((packed)) host_interface;
592
593 /*
594 * Device (backend) interface information
595 */
596 struct {
597
598 u8 SPI:1;
599 u8 SAS_3G:1;
600 u8 SATA_1_5G:1;
601 u8 SATA_3G:1;
602 u8 reserved_0:4;
603 u8 reserved_1[6];
604 u8 port_count;
605 u64 port_addr[8];
606
607 } __attribute__ ((packed)) device_interface;
608
609 /*
610 * List of components residing in flash. All str are null terminated
611 */
612 u32 image_check_word;
613 u32 image_component_count;
614
615 struct {
616
617 char name[8];
618 char version[32];
619 char build_date[16];
620 char built_time[16];
621
622 } __attribute__ ((packed)) image_component[8];
623
624 /*
625 * List of flash components that have been flashed on the card, but
626 * are not in use, pending reset of the adapter. This list will be
627 * empty if a flash operation has not occurred. All stings are null
628 * terminated
629 */
630 u32 pending_image_component_count;
631
632 struct {
633
634 char name[8];
635 char version[32];
636 char build_date[16];
637 char build_time[16];
638
639 } __attribute__ ((packed)) pending_image_component[8];
640
641 u8 max_arms;
642 u8 max_spans;
643 u8 max_arrays;
644 u8 max_lds;
645
646 char product_name[80];
647 char serial_no[32];
648
649 /*
650 * Other physical/controller/operation information. Indicates the
651 * presence of the hardware
652 */
653 struct {
654
655 u32 bbu:1;
656 u32 alarm:1;
657 u32 nvram:1;
658 u32 uart:1;
659 u32 reserved:28;
660
661 } __attribute__ ((packed)) hw_present;
662
663 u32 current_fw_time;
664
665 /*
666 * Maximum data transfer sizes
667 */
668 u16 max_concurrent_cmds;
669 u16 max_sge_count;
670 u32 max_request_size;
671
672 /*
673 * Logical and physical device counts
674 */
675 u16 ld_present_count;
676 u16 ld_degraded_count;
677 u16 ld_offline_count;
678
679 u16 pd_present_count;
680 u16 pd_disk_present_count;
681 u16 pd_disk_pred_failure_count;
682 u16 pd_disk_failed_count;
683
684 /*
685 * Memory size information
686 */
687 u16 nvram_size;
688 u16 memory_size;
689 u16 flash_size;
690
691 /*
692 * Error counters
693 */
694 u16 mem_correctable_error_count;
695 u16 mem_uncorrectable_error_count;
696
697 /*
698 * Cluster information
699 */
700 u8 cluster_permitted;
701 u8 cluster_active;
702
703 /*
704 * Additional max data transfer sizes
705 */
706 u16 max_strips_per_io;
707
708 /*
709 * Controller capabilities structures
710 */
711 struct {
712
713 u32 raid_level_0:1;
714 u32 raid_level_1:1;
715 u32 raid_level_5:1;
716 u32 raid_level_1E:1;
717 u32 raid_level_6:1;
718 u32 reserved:27;
719
720 } __attribute__ ((packed)) raid_levels;
721
722 struct {
723
724 u32 rbld_rate:1;
725 u32 cc_rate:1;
726 u32 bgi_rate:1;
727 u32 recon_rate:1;
728 u32 patrol_rate:1;
729 u32 alarm_control:1;
730 u32 cluster_supported:1;
731 u32 bbu:1;
732 u32 spanning_allowed:1;
733 u32 dedicated_hotspares:1;
734 u32 revertible_hotspares:1;
735 u32 foreign_config_import:1;
736 u32 self_diagnostic:1;
737 u32 mixed_redundancy_arr:1;
738 u32 global_hot_spares:1;
739 u32 reserved:17;
740
741 } __attribute__ ((packed)) adapter_operations;
742
743 struct {
744
745 u32 read_policy:1;
746 u32 write_policy:1;
747 u32 io_policy:1;
748 u32 access_policy:1;
749 u32 disk_cache_policy:1;
750 u32 reserved:27;
751
752 } __attribute__ ((packed)) ld_operations;
753
754 struct {
755
756 u8 min;
757 u8 max;
758 u8 reserved[2];
759
760 } __attribute__ ((packed)) stripe_sz_ops;
761
762 struct {
763
764 u32 force_online:1;
765 u32 force_offline:1;
766 u32 force_rebuild:1;
767 u32 reserved:29;
768
769 } __attribute__ ((packed)) pd_operations;
770
771 struct {
772
773 u32 ctrl_supports_sas:1;
774 u32 ctrl_supports_sata:1;
775 u32 allow_mix_in_encl:1;
776 u32 allow_mix_in_ld:1;
777 u32 allow_sata_in_cluster:1;
778 u32 reserved:27;
779
780 } __attribute__ ((packed)) pd_mix_support;
781
782 /*
783 * Define ECC single-bit-error bucket information
784 */
785 u8 ecc_bucket_count;
786 u8 reserved_2[11];
787
788 /*
789 * Include the controller properties (changeable items)
790 */
791 struct megasas_ctrl_prop properties;
792
793 /*
794 * Define FW pkg version (set in envt v'bles on OEM basis)
795 */
796 char package_version[0x60];
797
c4a3e0a5 798
bc93d425
SS		 799 /*
800 * If adapterOperations.supportMoreThan8Phys is set,
801 * and deviceInterface.portCount is greater than 8,
802 * SAS Addrs for first 8 ports shall be populated in
803 * deviceInterface.portAddr, and the rest shall be
804 * populated in deviceInterfacePortAddr2.
805 */
806 u64 deviceInterfacePortAddr2[8]; /*6a0h */
807 u8 reserved3[128]; /*6e0h */
808
809 struct { /*760h */
810 u16 minPdRaidLevel_0:4;
811 u16 maxPdRaidLevel_0:12;
812
813 u16 minPdRaidLevel_1:4;
814 u16 maxPdRaidLevel_1:12;
815
816 u16 minPdRaidLevel_5:4;
817 u16 maxPdRaidLevel_5:12;
818
819 u16 minPdRaidLevel_1E:4;
820 u16 maxPdRaidLevel_1E:12;
821
822 u16 minPdRaidLevel_6:4;
823 u16 maxPdRaidLevel_6:12;
824
825 u16 minPdRaidLevel_10:4;
826 u16 maxPdRaidLevel_10:12;
827
828 u16 minPdRaidLevel_50:4;
829 u16 maxPdRaidLevel_50:12;
830
831 u16 minPdRaidLevel_60:4;
832 u16 maxPdRaidLevel_60:12;
833
834 u16 minPdRaidLevel_1E_RLQ0:4;
835 u16 maxPdRaidLevel_1E_RLQ0:12;
836
837 u16 minPdRaidLevel_1E0_RLQ0:4;
838 u16 maxPdRaidLevel_1E0_RLQ0:12;
839
840 u16 reserved[6];
841 } pdsForRaidLevels;
842
843 u16 maxPds; /*780h */
844 u16 maxDedHSPs; /*782h */
845 u16 maxGlobalHSPs; /*784h */
846 u16 ddfSize; /*786h */
847 u8 maxLdsPerArray; /*788h */
848 u8 partitionsInDDF; /*789h */
849 u8 lockKeyBinding; /*78ah */
850 u8 maxPITsPerLd; /*78bh */
851 u8 maxViewsPerLd; /*78ch */
852 u8 maxTargetId; /*78dh */
853 u16 maxBvlVdSize; /*78eh */
854
855 u16 maxConfigurableSSCSize; /*790h */
856 u16 currentSSCsize; /*792h */
857
858 char expanderFwVersion[12]; /*794h */
859
860 u16 PFKTrialTimeRemaining; /*7A0h */
861
862 u16 cacheMemorySize; /*7A2h */
863
864 struct { /*7A4h */
94cd65dd 865#if defined(__BIG_ENDIAN_BITFIELD)
229fe47c 866 u32 reserved:5;
867 u32 activePassive:2;
868 u32 supportConfigAutoBalance:1;
869 u32 mpio:1;
870 u32 supportDataLDonSSCArray:1;
871 u32 supportPointInTimeProgress:1;
94cd65dd
SS		 872 u32 supportUnevenSpans:1;
873 u32 dedicatedHotSparesLimited:1;
874 u32 headlessMode:1;
875 u32 supportEmulatedDrives:1;
876 u32 supportResetNow:1;
877 u32 realTimeScheduler:1;
878 u32 supportSSDPatrolRead:1;
879 u32 supportPerfTuning:1;
880 u32 disableOnlinePFKChange:1;
881 u32 supportJBOD:1;
882 u32 supportBootTimePFKChange:1;
883 u32 supportSetLinkSpeed:1;
884 u32 supportEmergencySpares:1;
885 u32 supportSuspendResumeBGops:1;
886 u32 blockSSDWriteCacheChange:1;
887 u32 supportShieldState:1;
888 u32 supportLdBBMInfo:1;
889 u32 supportLdPIType3:1;
890 u32 supportLdPIType2:1;
891 u32 supportLdPIType1:1;
892 u32 supportPIcontroller:1;
893#else
bc93d425
SS		 894 u32 supportPIcontroller:1;
895 u32 supportLdPIType1:1;
896 u32 supportLdPIType2:1;
897 u32 supportLdPIType3:1;
898 u32 supportLdBBMInfo:1;
899 u32 supportShieldState:1;
900 u32 blockSSDWriteCacheChange:1;
901 u32 supportSuspendResumeBGops:1;
902 u32 supportEmergencySpares:1;
903 u32 supportSetLinkSpeed:1;
904 u32 supportBootTimePFKChange:1;
905 u32 supportJBOD:1;
906 u32 disableOnlinePFKChange:1;
907 u32 supportPerfTuning:1;
908 u32 supportSSDPatrolRead:1;
909 u32 realTimeScheduler:1;
910
911 u32 supportResetNow:1;
912 u32 supportEmulatedDrives:1;
913 u32 headlessMode:1;
914 u32 dedicatedHotSparesLimited:1;
915
916
917 u32 supportUnevenSpans:1;
229fe47c 918 u32 supportPointInTimeProgress:1;
919 u32 supportDataLDonSSCArray:1;
920 u32 mpio:1;
921 u32 supportConfigAutoBalance:1;
922 u32 activePassive:2;
923 u32 reserved:5;
94cd65dd 924#endif
bc93d425
SS		 925 } adapterOperations2;
926
927 u8 driverVersion[32]; /*7A8h */
928 u8 maxDAPdCountSpinup60; /*7C8h */
929 u8 temperatureROC; /*7C9h */
930 u8 temperatureCtrl; /*7CAh */
931 u8 reserved4; /*7CBh */
932 u16 maxConfigurablePds; /*7CCh */
933
934
935 u8 reserved5[2]; /*0x7CDh */
936
937 /*
938 * HA cluster information
939 */
940 struct {
51087a86
SS		 941#if defined(__BIG_ENDIAN_BITFIELD)
942 u32 reserved:26;
943 u32 premiumFeatureMismatch:1;
944 u32 ctrlPropIncompatible:1;
945 u32 fwVersionMismatch:1;
946 u32 hwIncompatible:1;
947 u32 peerIsIncompatible:1;
948 u32 peerIsPresent:1;
949#else
bc93d425
SS		 950 u32 peerIsPresent:1;
951 u32 peerIsIncompatible:1;
952 u32 hwIncompatible:1;
953 u32 fwVersionMismatch:1;
954 u32 ctrlPropIncompatible:1;
955 u32 premiumFeatureMismatch:1;
956 u32 reserved:26;
51087a86 957#endif
bc93d425
SS		 958 } cluster;
959
960 char clusterId[16]; /*7D4h */
229fe47c 961 struct {
962 u8 maxVFsSupported; /*0x7E4*/
963 u8 numVFsEnabled; /*0x7E5*/
964 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/
965 u8 reserved; /*0x7E7*/
966 } iov;
bc93d425 967
fc62b3fc
SS		 968 struct {
969#if defined(__BIG_ENDIAN_BITFIELD)
970 u32 reserved:25;
971 u32 supportCrashDump:1;
51087a86
SS		 972 u32 supportMaxExtLDs:1;
973 u32 supportT10RebuildAssist:1;
974 u32 supportDisableImmediateIO:1;
975 u32 supportThermalPollInterval:1;
976 u32 supportPersonalityChange:2;
fc62b3fc 977#else
51087a86
SS		 978 u32 supportPersonalityChange:2;
979 u32 supportThermalPollInterval:1;
980 u32 supportDisableImmediateIO:1;
981 u32 supportT10RebuildAssist:1;
982 u32 supportMaxExtLDs:1;
fc62b3fc
SS		 983 u32 supportCrashDump:1;
984 u32 reserved:25;
985#endif
986 } adapterOperations3;
987
988 u8 pad[0x800-0x7EC];
81e403ce 989} __packed;
c4a3e0a5
BS		 990
991/*
992 * ===============================
993 * MegaRAID SAS driver definitions
994 * ===============================
995 */
996#define MEGASAS_MAX_PD_CHANNELS 2
51087a86 997#define MEGASAS_MAX_LD_CHANNELS 2
c4a3e0a5
BS		 998#define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
999 MEGASAS_MAX_LD_CHANNELS)
1000#define MEGASAS_MAX_DEV_PER_CHANNEL 128
1001#define MEGASAS_DEFAULT_INIT_ID -1
1002#define MEGASAS_MAX_LUN 8
6bf579a3 1003#define MEGASAS_DEFAULT_CMD_PER_LUN 256
81e403ce
YB		 1004#define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
1005 MEGASAS_MAX_DEV_PER_CHANNEL)
bdc6fb8d
YB		 1006#define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
1007 MEGASAS_MAX_DEV_PER_CHANNEL)
c4a3e0a5 1008
1fd10685 1009#define MEGASAS_MAX_SECTORS (2*1024)
42a8d2b3 1010#define MEGASAS_MAX_SECTORS_IEEE (2*128)
658dcedb
SP		 1011#define MEGASAS_DBG_LVL 1
1012
05e9ebbe
SP		 1013#define MEGASAS_FW_BUSY 1
1014
51087a86
SS		 1015#define VD_EXT_DEBUG 0
1016
90dc9d98
SS		 1017enum MR_MFI_MPT_PTHR_FLAGS {
1018 MFI_MPT_DETACHED = 0,
1019 MFI_LIST_ADDED = 1,
1020 MFI_MPT_ATTACHED = 2,
1021};
1022
d532dbe2 1023/* Frame Type */
1024#define IO_FRAME 0
1025#define PTHRU_FRAME 1
1026
c4a3e0a5
BS		 1027/*
1028 * When SCSI mid-layer calls driver's reset routine, driver waits for
1029 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1030 * that the driver cannot _actually_ abort or reset pending commands. While
1031 * it is waiting for the commands to complete, it prints a diagnostic message
1032 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1033 */
1034#define MEGASAS_RESET_WAIT_TIME 180
2a3681e5 1035#define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
c4a3e0a5 1036#define MEGASAS_RESET_NOTICE_INTERVAL 5
c4a3e0a5 1037#define MEGASAS_IOCTL_CMD 0
05e9ebbe 1038#define MEGASAS_DEFAULT_CMD_TIMEOUT 90
c5daa6a9 1039#define MEGASAS_THROTTLE_QUEUE_DEPTH 16
90dc9d98 1040#define MEGASAS_BLOCKED_CMD_TIMEOUT 60
c4a3e0a5
BS		 1041/*
1042 * FW reports the maximum of number of commands that it can accept (maximum
1043 * commands that can be outstanding) at any time. The driver must report a
1044 * lower number to the mid layer because it can issue a few internal commands
1045 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1046 * is shown below
1047 */
1048#define MEGASAS_INT_CMDS 32
7bebf5c7 1049#define MEGASAS_SKINNY_INT_CMDS 5
c4a3e0a5 1050
d46a3ad6 1051#define MEGASAS_MAX_MSIX_QUEUES 128
c4a3e0a5
BS		 1052/*
1053 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1054 * SGLs based on the size of dma_addr_t
1055 */
1056#define IS_DMA64 (sizeof(dma_addr_t) == 8)
1057
39a98554 1058#define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
1059
1060#define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
1061#define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
1062#define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
1063
c4a3e0a5 1064#define MFI_OB_INTR_STATUS_MASK 0x00000002
14faea9f 1065#define MFI_POLL_TIMEOUT_SECS 60
229fe47c 1066#define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ)
1067#define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30)
1068#define MEGASAS_ROUTINE_WAIT_TIME_VF 300
f9876f0b 1069#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
6610a6b3
YB		 1070#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
1071#define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
87911122
YB		 1072#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
1073#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
0e98936c 1074
39a98554 1075#define MFI_1068_PCSR_OFFSET 0x84
1076#define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
1077#define MFI_1068_FW_READY 0xDDDD0000
d46a3ad6
SS		 1078
1079#define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
1080#define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
1081#define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
1082#define MR_MAX_MSIX_REG_ARRAY 16
0e98936c
SP		 1083/*
1084* register set for both 1068 and 1078 controllers
1085* structure extended for 1078 registers
1086*/
f9876f0b 1087
c4a3e0a5 1088struct megasas_register_set {
9c915a8c 1089 u32 doorbell; /*0000h*/
1090 u32 fusion_seq_offset; /*0004h*/
1091 u32 fusion_host_diag; /*0008h*/
1092 u32 reserved_01; /*000Ch*/
c4a3e0a5 1093
f9876f0b
SP		 1094 u32 inbound_msg_0; /*0010h*/
1095 u32 inbound_msg_1; /*0014h*/
1096 u32 outbound_msg_0; /*0018h*/
1097 u32 outbound_msg_1; /*001Ch*/
c4a3e0a5 1098
f9876f0b
SP		 1099 u32 inbound_doorbell; /*0020h*/
1100 u32 inbound_intr_status; /*0024h*/
1101 u32 inbound_intr_mask; /*0028h*/
c4a3e0a5 1102
f9876f0b
SP		 1103 u32 outbound_doorbell; /*002Ch*/
1104 u32 outbound_intr_status; /*0030h*/
1105 u32 outbound_intr_mask; /*0034h*/
c4a3e0a5 1106
f9876f0b 1107 u32 reserved_1[2]; /*0038h*/
c4a3e0a5 1108
f9876f0b
SP		 1109 u32 inbound_queue_port; /*0040h*/
1110 u32 outbound_queue_port; /*0044h*/
c4a3e0a5 1111
9c915a8c 1112 u32 reserved_2[9]; /*0048h*/
1113 u32 reply_post_host_index; /*006Ch*/
1114 u32 reserved_2_2[12]; /*0070h*/
c4a3e0a5 1115
f9876f0b 1116 u32 outbound_doorbell_clear; /*00A0h*/
c4a3e0a5 1117
f9876f0b
SP		 1118 u32 reserved_3[3]; /*00A4h*/
1119
1120 u32 outbound_scratch_pad ; /*00B0h*/
9c915a8c 1121 u32 outbound_scratch_pad_2; /*00B4h*/
f9876f0b 1122
9c915a8c 1123 u32 reserved_4[2]; /*00B8h*/
f9876f0b
SP		 1124
1125 u32 inbound_low_queue_port ; /*00C0h*/
1126
1127 u32 inbound_high_queue_port ; /*00C4h*/
1128
1129 u32 reserved_5; /*00C8h*/
39a98554 1130 u32 res_6[11]; /*CCh*/
1131 u32 host_diag;
1132 u32 seq_offset;
1133 u32 index_registers[807]; /*00CCh*/
c4a3e0a5
BS		 1134} __attribute__ ((packed));
1135
1136struct megasas_sge32 {
1137
1138 u32 phys_addr;
1139 u32 length;
1140
1141} __attribute__ ((packed));
1142
1143struct megasas_sge64 {
1144
1145 u64 phys_addr;
1146 u32 length;
1147
1148} __attribute__ ((packed));
1149
f4c9a131
YB		 1150struct megasas_sge_skinny {
1151 u64 phys_addr;
1152 u32 length;
1153 u32 flag;
1154} __packed;
1155
c4a3e0a5
BS		 1156union megasas_sgl {
1157
1158 struct megasas_sge32 sge32[1];
1159 struct megasas_sge64 sge64[1];
f4c9a131 1160 struct megasas_sge_skinny sge_skinny[1];
c4a3e0a5
BS		 1161
1162} __attribute__ ((packed));
1163
1164struct megasas_header {
1165
1166 u8 cmd; /*00h */
1167 u8 sense_len; /*01h */
1168 u8 cmd_status; /*02h */
1169 u8 scsi_status; /*03h */
1170
1171 u8 target_id; /*04h */
1172 u8 lun; /*05h */
1173 u8 cdb_len; /*06h */
1174 u8 sge_count; /*07h */
1175
1176 u32 context; /*08h */
1177 u32 pad_0; /*0Ch */
1178
1179 u16 flags; /*10h */
1180 u16 timeout; /*12h */
1181 u32 data_xferlen; /*14h */
1182
1183} __attribute__ ((packed));
1184
1185union megasas_sgl_frame {
1186
1187 struct megasas_sge32 sge32[8];
1188 struct megasas_sge64 sge64[5];
1189
1190} __attribute__ ((packed));
1191
d46a3ad6
SS		 1192typedef union _MFI_CAPABILITIES {
1193 struct {
94cd65dd 1194#if defined(__BIG_ENDIAN_BITFIELD)
d2552ebe
SS		 1195 u32 reserved:27;
1196 u32 support_ndrive_r1_lb:1;
51087a86
SS		 1197 u32 support_max_255lds:1;
1198 u32 reserved1:1;
94cd65dd
SS		 1199 u32 support_additional_msix:1;
1200 u32 support_fp_remote_lun:1;
1201#else
d46a3ad6
SS		 1202 u32 support_fp_remote_lun:1;
1203 u32 support_additional_msix:1;
51087a86
SS		 1204 u32 reserved1:1;
1205 u32 support_max_255lds:1;
d2552ebe
SS		 1206 u32 support_ndrive_r1_lb:1;
1207 u32 reserved:27;
94cd65dd 1208#endif
d46a3ad6
SS		 1209 } mfi_capabilities;
1210 u32 reg;
1211} MFI_CAPABILITIES;
1212
c4a3e0a5
BS		 1213struct megasas_init_frame {
1214
1215 u8 cmd; /*00h */
1216 u8 reserved_0; /*01h */
1217 u8 cmd_status; /*02h */
1218
1219 u8 reserved_1; /*03h */
d46a3ad6 1220 MFI_CAPABILITIES driver_operations; /*04h*/
c4a3e0a5
BS		 1221
1222 u32 context; /*08h */
1223 u32 pad_0; /*0Ch */
1224
1225 u16 flags; /*10h */
1226 u16 reserved_3; /*12h */
1227 u32 data_xfer_len; /*14h */
1228
1229 u32 queue_info_new_phys_addr_lo; /*18h */
1230 u32 queue_info_new_phys_addr_hi; /*1Ch */
1231 u32 queue_info_old_phys_addr_lo; /*20h */
1232 u32 queue_info_old_phys_addr_hi; /*24h */
1233
1234 u32 reserved_4[6]; /*28h */
1235
1236} __attribute__ ((packed));
1237
1238struct megasas_init_queue_info {
1239
1240 u32 init_flags; /*00h */
1241 u32 reply_queue_entries; /*04h */
1242
1243 u32 reply_queue_start_phys_addr_lo; /*08h */
1244 u32 reply_queue_start_phys_addr_hi; /*0Ch */
1245 u32 producer_index_phys_addr_lo; /*10h */
1246 u32 producer_index_phys_addr_hi; /*14h */
1247 u32 consumer_index_phys_addr_lo; /*18h */
1248 u32 consumer_index_phys_addr_hi; /*1Ch */
1249
1250} __attribute__ ((packed));
1251
1252struct megasas_io_frame {
1253
1254 u8 cmd; /*00h */
1255 u8 sense_len; /*01h */
1256 u8 cmd_status; /*02h */
1257 u8 scsi_status; /*03h */
1258
1259 u8 target_id; /*04h */
1260 u8 access_byte; /*05h */
1261 u8 reserved_0; /*06h */
1262 u8 sge_count; /*07h */
1263
1264 u32 context; /*08h */
1265 u32 pad_0; /*0Ch */
1266
1267 u16 flags; /*10h */
1268 u16 timeout; /*12h */
1269 u32 lba_count; /*14h */
1270
1271 u32 sense_buf_phys_addr_lo; /*18h */
1272 u32 sense_buf_phys_addr_hi; /*1Ch */
1273
1274 u32 start_lba_lo; /*20h */
1275 u32 start_lba_hi; /*24h */
1276
1277 union megasas_sgl sgl; /*28h */
1278
1279} __attribute__ ((packed));
1280
1281struct megasas_pthru_frame {
1282
1283 u8 cmd; /*00h */
1284 u8 sense_len; /*01h */
1285 u8 cmd_status; /*02h */
1286 u8 scsi_status; /*03h */
1287
1288 u8 target_id; /*04h */
1289 u8 lun; /*05h */
1290 u8 cdb_len; /*06h */
1291 u8 sge_count; /*07h */
1292
1293 u32 context; /*08h */
1294 u32 pad_0; /*0Ch */
1295
1296 u16 flags; /*10h */
1297 u16 timeout; /*12h */
1298 u32 data_xfer_len; /*14h */
1299
1300 u32 sense_buf_phys_addr_lo; /*18h */
1301 u32 sense_buf_phys_addr_hi; /*1Ch */
1302
1303 u8 cdb[16]; /*20h */
1304 union megasas_sgl sgl; /*30h */
1305
1306} __attribute__ ((packed));
1307
1308struct megasas_dcmd_frame {
1309
1310 u8 cmd; /*00h */
1311 u8 reserved_0; /*01h */
1312 u8 cmd_status; /*02h */
1313 u8 reserved_1[4]; /*03h */
1314 u8 sge_count; /*07h */
1315
1316 u32 context; /*08h */
1317 u32 pad_0; /*0Ch */
1318
1319 u16 flags; /*10h */
1320 u16 timeout; /*12h */
1321
1322 u32 data_xfer_len; /*14h */
1323 u32 opcode; /*18h */
1324
1325 union { /*1Ch */
1326 u8 b[12];
1327 u16 s[6];
1328 u32 w[3];
1329 } mbox;
1330
1331 union megasas_sgl sgl; /*28h */
1332
1333} __attribute__ ((packed));
1334
1335struct megasas_abort_frame {
1336
1337 u8 cmd; /*00h */
1338 u8 reserved_0; /*01h */
1339 u8 cmd_status; /*02h */
1340
1341 u8 reserved_1; /*03h */
1342 u32 reserved_2; /*04h */
1343
1344 u32 context; /*08h */
1345 u32 pad_0; /*0Ch */
1346
1347 u16 flags; /*10h */
1348 u16 reserved_3; /*12h */
1349 u32 reserved_4; /*14h */
1350
1351 u32 abort_context; /*18h */
1352 u32 pad_1; /*1Ch */
1353
1354 u32 abort_mfi_phys_addr_lo; /*20h */
1355 u32 abort_mfi_phys_addr_hi; /*24h */
1356
1357 u32 reserved_5[6]; /*28h */
1358
1359} __attribute__ ((packed));
1360
1361struct megasas_smp_frame {
1362
1363 u8 cmd; /*00h */
1364 u8 reserved_1; /*01h */
1365 u8 cmd_status; /*02h */
1366 u8 connection_status; /*03h */
1367
1368 u8 reserved_2[3]; /*04h */
1369 u8 sge_count; /*07h */
1370
1371 u32 context; /*08h */
1372 u32 pad_0; /*0Ch */
1373
1374 u16 flags; /*10h */
1375 u16 timeout; /*12h */
1376
1377 u32 data_xfer_len; /*14h */
1378 u64 sas_addr; /*18h */
1379
1380 union {
1381 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1382 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1383 } sgl;
1384
1385} __attribute__ ((packed));
1386
1387struct megasas_stp_frame {
1388
1389 u8 cmd; /*00h */
1390 u8 reserved_1; /*01h */
1391 u8 cmd_status; /*02h */
1392 u8 reserved_2; /*03h */
1393
1394 u8 target_id; /*04h */
1395 u8 reserved_3[2]; /*05h */
1396 u8 sge_count; /*07h */
1397
1398 u32 context; /*08h */
1399 u32 pad_0; /*0Ch */
1400
1401 u16 flags; /*10h */
1402 u16 timeout; /*12h */
1403
1404 u32 data_xfer_len; /*14h */
1405
1406 u16 fis[10]; /*18h */
1407 u32 stp_flags;
1408
1409 union {
1410 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1411 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1412 } sgl;
1413
1414} __attribute__ ((packed));
1415
1416union megasas_frame {
1417
1418 struct megasas_header hdr;
1419 struct megasas_init_frame init;
1420 struct megasas_io_frame io;
1421 struct megasas_pthru_frame pthru;
1422 struct megasas_dcmd_frame dcmd;
1423 struct megasas_abort_frame abort;
1424 struct megasas_smp_frame smp;
1425 struct megasas_stp_frame stp;
1426
1427 u8 raw_bytes[64];
1428};
1429
1430struct megasas_cmd;
1431
1432union megasas_evt_class_locale {
1433
1434 struct {
be26374b 1435#ifndef __BIG_ENDIAN_BITFIELD
c4a3e0a5
BS		 1436 u16 locale;
1437 u8 reserved;
1438 s8 class;
be26374b
SS		 1439#else
1440 s8 class;
1441 u8 reserved;
1442 u16 locale;
1443#endif
c4a3e0a5
BS		 1444 } __attribute__ ((packed)) members;
1445
1446 u32 word;
1447
1448} __attribute__ ((packed));
1449
1450struct megasas_evt_log_info {
1451 u32 newest_seq_num;
1452 u32 oldest_seq_num;
1453 u32 clear_seq_num;
1454 u32 shutdown_seq_num;
1455 u32 boot_seq_num;
1456
1457} __attribute__ ((packed));
1458
1459struct megasas_progress {
1460
1461 u16 progress;
1462 u16 elapsed_seconds;
1463
1464} __attribute__ ((packed));
1465
1466struct megasas_evtarg_ld {
1467
1468 u16 target_id;
1469 u8 ld_index;
1470 u8 reserved;
1471
1472} __attribute__ ((packed));
1473
1474struct megasas_evtarg_pd {
1475 u16 device_id;
1476 u8 encl_index;
1477 u8 slot_number;
1478
1479} __attribute__ ((packed));
1480
1481struct megasas_evt_detail {
1482
1483 u32 seq_num;
1484 u32 time_stamp;
1485 u32 code;
1486 union megasas_evt_class_locale cl;
1487 u8 arg_type;
1488 u8 reserved1[15];
1489
1490 union {
1491 struct {
1492 struct megasas_evtarg_pd pd;
1493 u8 cdb_length;
1494 u8 sense_length;
1495 u8 reserved[2];
1496 u8 cdb[16];
1497 u8 sense[64];
1498 } __attribute__ ((packed)) cdbSense;
1499
1500 struct megasas_evtarg_ld ld;
1501
1502 struct {
1503 struct megasas_evtarg_ld ld;
1504 u64 count;
1505 } __attribute__ ((packed)) ld_count;
1506
1507 struct {
1508 u64 lba;
1509 struct megasas_evtarg_ld ld;
1510 } __attribute__ ((packed)) ld_lba;
1511
1512 struct {
1513 struct megasas_evtarg_ld ld;
1514 u32 prevOwner;
1515 u32 newOwner;
1516 } __attribute__ ((packed)) ld_owner;
1517
1518 struct {
1519 u64 ld_lba;
1520 u64 pd_lba;
1521 struct megasas_evtarg_ld ld;
1522 struct megasas_evtarg_pd pd;
1523 } __attribute__ ((packed)) ld_lba_pd_lba;
1524
1525 struct {
1526 struct megasas_evtarg_ld ld;
1527 struct megasas_progress prog;
1528 } __attribute__ ((packed)) ld_prog;
1529
1530 struct {
1531 struct megasas_evtarg_ld ld;
1532 u32 prev_state;
1533 u32 new_state;
1534 } __attribute__ ((packed)) ld_state;
1535
1536 struct {
1537 u64 strip;
1538 struct megasas_evtarg_ld ld;
1539 } __attribute__ ((packed)) ld_strip;
1540
1541 struct megasas_evtarg_pd pd;
1542
1543 struct {
1544 struct megasas_evtarg_pd pd;
1545 u32 err;
1546 } __attribute__ ((packed)) pd_err;
1547
1548 struct {
1549 u64 lba;
1550 struct megasas_evtarg_pd pd;
1551 } __attribute__ ((packed)) pd_lba;
1552
1553 struct {
1554 u64 lba;
1555 struct megasas_evtarg_pd pd;
1556 struct megasas_evtarg_ld ld;
1557 } __attribute__ ((packed)) pd_lba_ld;
1558
1559 struct {
1560 struct megasas_evtarg_pd pd;
1561 struct megasas_progress prog;
1562 } __attribute__ ((packed)) pd_prog;
1563
1564 struct {
1565 struct megasas_evtarg_pd pd;
1566 u32 prevState;
1567 u32 newState;
1568 } __attribute__ ((packed)) pd_state;
1569
1570 struct {
1571 u16 vendorId;
1572 u16 deviceId;
1573 u16 subVendorId;
1574 u16 subDeviceId;
1575 } __attribute__ ((packed)) pci;
1576
1577 u32 rate;
1578 char str[96];
1579
1580 struct {
1581 u32 rtc;
1582 u32 elapsedSeconds;
1583 } __attribute__ ((packed)) time;
1584
1585 struct {
1586 u32 ecar;
1587 u32 elog;
1588 char str[64];
1589 } __attribute__ ((packed)) ecc;
1590
1591 u8 b[96];
1592 u16 s[48];
1593 u32 w[24];
1594 u64 d[12];
1595 } args;
1596
1597 char description[128];
1598
1599} __attribute__ ((packed));
1600
7e8a75f4 1601struct megasas_aen_event {
c1d390d8 1602 struct delayed_work hotplug_work;
7e8a75f4
YB		 1603 struct megasas_instance *instance;
1604};
1605
c8e858fe 1606struct megasas_irq_context {
1607 struct megasas_instance *instance;
1608 u32 MSIxIndex;
1609};
1610
c4a3e0a5
BS		 1611struct megasas_instance {
1612
1613 u32 *producer;
1614 dma_addr_t producer_h;
1615 u32 *consumer;
1616 dma_addr_t consumer_h;
229fe47c 1617 struct MR_LD_VF_AFFILIATION *vf_affiliation;
1618 dma_addr_t vf_affiliation_h;
1619 struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
1620 dma_addr_t vf_affiliation_111_h;
1621 struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
1622 dma_addr_t hb_host_mem_h;
c4a3e0a5
BS		 1623
1624 u32 *reply_queue;
1625 dma_addr_t reply_queue_h;
1626
fc62b3fc
SS		 1627 u32 *crash_dump_buf;
1628 dma_addr_t crash_dump_h;
1629 void *crash_buf[MAX_CRASH_DUMP_SIZE];
1630 u32 crash_buf_pages;
1631 unsigned int fw_crash_buffer_size;
1632 unsigned int fw_crash_state;
1633 unsigned int fw_crash_buffer_offset;
1634 u32 drv_buf_index;
1635 u32 drv_buf_alloc;
1636 u32 crash_dump_fw_support;
1637 u32 crash_dump_drv_support;
1638 u32 crash_dump_app_support;
1639 spinlock_t crashdump_lock;
1640
c4a3e0a5 1641 struct megasas_register_set __iomem *reg_set;
d46a3ad6 1642 u32 *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
81e403ce 1643 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
999ece0a 1644 struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD];
bdc6fb8d 1645 u8 ld_ids[MEGASAS_MAX_LD_IDS];
c4a3e0a5 1646 s8 init_id;
c4a3e0a5
BS		 1647
1648 u16 max_num_sge;
1649 u16 max_fw_cmds;
9c915a8c 1650 /* For Fusion its num IOCTL cmds, for others MFI based its
1651 max_fw_cmds */
1652 u16 max_mfi_cmds;
c4a3e0a5 1653 u32 max_sectors_per_req;
7e8a75f4 1654 struct megasas_aen_event *ev;
c4a3e0a5
BS		 1655
1656 struct megasas_cmd **cmd_list;
1657 struct list_head cmd_pool;
39a98554 1658 /* used to sync fire the cmd to fw */
90dc9d98 1659 spinlock_t mfi_pool_lock;
39a98554 1660 /* used to sync fire the cmd to fw */
1661 spinlock_t hba_lock;
7343eb65 1662 /* used to synch producer, consumer ptrs in dpc */
1663 spinlock_t completion_lock;
c4a3e0a5
BS		 1664 struct dma_pool *frame_dma_pool;
1665 struct dma_pool *sense_dma_pool;
1666
1667 struct megasas_evt_detail *evt_detail;
1668 dma_addr_t evt_detail_h;
1669 struct megasas_cmd *aen_cmd;
e5a69e27 1670 struct mutex aen_mutex;
c4a3e0a5
BS		 1671 struct semaphore ioctl_sem;
1672
1673 struct Scsi_Host *host;
1674
1675 wait_queue_head_t int_cmd_wait_q;
1676 wait_queue_head_t abort_cmd_wait_q;
1677
1678 struct pci_dev *pdev;
1679 u32 unique_id;
39a98554 1680 u32 fw_support_ieee;
c4a3e0a5 1681
e4a082c7 1682 atomic_t fw_outstanding;
39a98554 1683 atomic_t fw_reset_no_pci_access;
1341c939
SP		 1684
1685 struct megasas_instance_template *instancet;
5d018ad0 1686 struct tasklet_struct isr_tasklet;
39a98554 1687 struct work_struct work_init;
fc62b3fc 1688 struct work_struct crash_init;
05e9ebbe
SP		 1689
1690 u8 flag;
c3518837 1691 u8 unload;
f4c9a131 1692 u8 flag_ieee;
39a98554 1693 u8 issuepend_done;
1694 u8 disableOnlineCtrlReset;
bc93d425 1695 u8 UnevenSpanSupport;
51087a86
SS		 1696
1697 u8 supportmax256vd;
1698 u16 fw_supported_vd_count;
1699 u16 fw_supported_pd_count;
1700
1701 u16 drv_supported_vd_count;
1702 u16 drv_supported_pd_count;
1703
39a98554 1704 u8 adprecovery;
05e9ebbe 1705 unsigned long last_time;
39a98554 1706 u32 mfiStatus;
1707 u32 last_seq_num;
ad84db2e 1708
39a98554 1709 struct list_head internal_reset_pending_q;
80d9da98 1710
25985edc 1711 /* Ptr to hba specific information */
9c915a8c 1712 void *ctrl_context;
51087a86
SS		 1713 u32 ctrl_context_pages;
1714 struct megasas_ctrl_info *ctrl_info;
c8e858fe 1715 unsigned int msix_vectors;
1716 struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES];
1717 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
9c915a8c 1718 u64 map_id;
1719 struct megasas_cmd *map_update_cmd;
b6d5d880 1720 unsigned long bar;
9c915a8c 1721 long reset_flags;
1722 struct mutex reset_mutex;
229fe47c 1723 struct timer_list sriov_heartbeat_timer;
1724 char skip_heartbeat_timer_del;
1725 u8 requestorId;
229fe47c 1726 char PlasmaFW111;
1727 char mpio;
c5daa6a9 1728 int throttlequeuedepth;
d46a3ad6 1729 u8 mask_interrupts;
404a8a1a 1730 u8 is_imr;
39a98554 1731};
229fe47c 1732struct MR_LD_VF_MAP {
1733 u32 size;
1734 union MR_LD_REF ref;
1735 u8 ldVfCount;
1736 u8 reserved[6];
1737 u8 policy[1];
1738};
1739
1740struct MR_LD_VF_AFFILIATION {
1741 u32 size;
1742 u8 ldCount;
1743 u8 vfCount;
1744 u8 thisVf;
1745 u8 reserved[9];
1746 struct MR_LD_VF_MAP map[1];
1747};
1748
1749/* Plasma 1.11 FW backward compatibility structures */
1750#define IOV_111_OFFSET 0x7CE
1751#define MAX_VIRTUAL_FUNCTIONS 8
4cbfea88 1752#define MR_LD_ACCESS_HIDDEN 15
229fe47c 1753
1754struct IOV_111 {
1755 u8 maxVFsSupported;
1756 u8 numVFsEnabled;
1757 u8 requestorId;
1758 u8 reserved[5];
1759};
1760
1761struct MR_LD_VF_MAP_111 {
1762 u8 targetId;
1763 u8 reserved[3];
1764 u8 policy[MAX_VIRTUAL_FUNCTIONS];
1765};
1766
1767struct MR_LD_VF_AFFILIATION_111 {
1768 u8 vdCount;
1769 u8 vfCount;
1770 u8 thisVf;
1771 u8 reserved[5];
1772 struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
1773};
1774
1775struct MR_CTRL_HB_HOST_MEM {
1776 struct {
1777 u32 fwCounter; /* Firmware heart beat counter */
1778 struct {
1779 u32 debugmode:1; /* 1=Firmware is in debug mode.
1780 Heart beat will not be updated. */
1781 u32 reserved:31;
1782 } debug;
1783 u32 reserved_fw[6];
1784 u32 driverCounter; /* Driver heart beat counter. 0x20 */
1785 u32 reserved_driver[7];
1786 } HB;
1787 u8 pad[0x400-0x40];
1788};
39a98554 1789
1790enum {
1791 MEGASAS_HBA_OPERATIONAL = 0,
1792 MEGASAS_ADPRESET_SM_INFAULT = 1,
1793 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1794 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
1795 MEGASAS_HW_CRITICAL_ERROR = 4,
229fe47c 1796 MEGASAS_ADPRESET_SM_POLLING = 5,
39a98554 1797 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
c4a3e0a5
BS		 1798};
1799
0c79e681
YB		 1800struct megasas_instance_template {
1801 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1802 u32, struct megasas_register_set __iomem *);
1803
d46a3ad6
SS		 1804 void (*enable_intr)(struct megasas_instance *);
1805 void (*disable_intr)(struct megasas_instance *);
0c79e681
YB		 1806
1807 int (*clear_intr)(struct megasas_register_set __iomem *);
1808
1809 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
39a98554 1810 int (*adp_reset)(struct megasas_instance *, \
1811 struct megasas_register_set __iomem *);
1812 int (*check_reset)(struct megasas_instance *, \
1813 struct megasas_register_set __iomem *);
cd50ba8e 1814 irqreturn_t (*service_isr)(int irq, void *devp);
1815 void (*tasklet)(unsigned long);
1816 u32 (*init_adapter)(struct megasas_instance *);
1817 u32 (*build_and_issue_cmd) (struct megasas_instance *,
1818 struct scsi_cmnd *);
1819 void (*issue_dcmd) (struct megasas_instance *instance,
1820 struct megasas_cmd *cmd);
0c79e681
YB		 1821};
1822
c4a3e0a5
BS		 1823#define MEGASAS_IS_LOGICAL(scp) \
1824 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1825
1826#define MEGASAS_DEV_INDEX(inst, scp) \
1827 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1828 scp->device->id
1829
1830struct megasas_cmd {
1831
1832 union megasas_frame *frame;
1833 dma_addr_t frame_phys_addr;
1834 u8 *sense;
1835 dma_addr_t sense_phys_addr;
1836
1837 u32 index;
1838 u8 sync_cmd;
1839 u8 cmd_status;
39a98554 1840 u8 abort_aen;
1841 u8 retry_for_fw_reset;
1842
c4a3e0a5
BS		 1843
1844 struct list_head list;
1845 struct scsi_cmnd *scmd;
90dc9d98
SS		 1846
1847 void *mpt_pthr_cmd_blocked;
1848 atomic_t mfi_mpt_pthr;
1849 u8 is_wait_event;
1850
c4a3e0a5 1851 struct megasas_instance *instance;
9c915a8c 1852 union {
1853 struct {
1854 u16 smid;
1855 u16 resvd;
1856 } context;
1857 u32 frame_count;
1858 };
c4a3e0a5
BS		 1859};
1860
1861#define MAX_MGMT_ADAPTERS 1024
1862#define MAX_IOCTL_SGE 16
1863
1864struct megasas_iocpacket {
1865
1866 u16 host_no;
1867 u16 __pad1;
1868 u32 sgl_off;
1869 u32 sge_count;
1870 u32 sense_off;
1871 u32 sense_len;
1872 union {
1873 u8 raw[128];
1874 struct megasas_header hdr;
1875 } frame;
1876
1877 struct iovec sgl[MAX_IOCTL_SGE];
1878
1879} __attribute__ ((packed));
1880
1881struct megasas_aen {
1882 u16 host_no;
1883 u16 __pad1;
1884 u32 seq_num;
1885 u32 class_locale_word;
1886} __attribute__ ((packed));
1887
1888#ifdef CONFIG_COMPAT
1889struct compat_megasas_iocpacket {
1890 u16 host_no;
1891 u16 __pad1;
1892 u32 sgl_off;
1893 u32 sge_count;
1894 u32 sense_off;
1895 u32 sense_len;
1896 union {
1897 u8 raw[128];
1898 struct megasas_header hdr;
1899 } frame;
1900 struct compat_iovec sgl[MAX_IOCTL_SGE];
1901} __attribute__ ((packed));
1902
0e98936c 1903#define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
c4a3e0a5
BS		 1904#endif
1905
cb59aa6a 1906#define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
c4a3e0a5
BS		 1907#define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1908
1909struct megasas_mgmt_info {
1910
1911 u16 count;
1912 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1913 int max_index;
1914};
1915
21c9e160 1916u8
1917MR_BuildRaidContext(struct megasas_instance *instance,
1918 struct IO_REQUEST_INFO *io_info,
1919 struct RAID_CONTEXT *pRAID_Context,
51087a86
SS		 1920 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
1921u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
1922struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
1923u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
1924u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
1925u16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
1926u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
1927
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SS		 1928u16 get_updated_dev_handle(struct megasas_instance *instance,
1929 struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *in_info);
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SS		 1930void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
1931 struct LD_LOAD_BALANCE_INFO *lbInfo);
1932int megasas_get_ctrl_info(struct megasas_instance *instance,
1933 struct megasas_ctrl_info *ctrl_info);
fc62b3fc 1934int megasas_set_crash_dump_params(struct megasas_instance *instance,
51087a86 1935 u8 crash_buf_state);
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SS		 1936void megasas_free_host_crash_buffer(struct megasas_instance *instance);
1937void megasas_fusion_crash_dump_wq(struct work_struct *work);
51087a86 1938
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SS		 1939void megasas_return_cmd_fusion(struct megasas_instance *instance,
1940 struct megasas_cmd_fusion *cmd);
1941int megasas_issue_blocked_cmd(struct megasas_instance *instance,
1942 struct megasas_cmd *cmd, int timeout);
1943void __megasas_return_cmd(struct megasas_instance *instance,
1944 struct megasas_cmd *cmd);
1945
1946void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
1947 struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
1948
c4a3e0a5 1949#endif /*LSI_MEGARAID_SAS_H */
Linux 6.x block layer and io_uring tree(s)