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scsi: megaraid_sas: add print in device removal path
[linux-2.6-block.git] / drivers / scsi / megaraid / megaraid_sas.h
CommitLineData
c4a3e0a5 1/*
3f1530c1 2 * Linux MegaRAID driver for SAS based RAID controllers
c4a3e0a5 3 *
e399065b
SS		 4 * Copyright (c) 2003-2013 LSI Corporation
5 * Copyright (c) 2013-2014 Avago Technologies
c4a3e0a5 6 *
3f1530c1 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
c4a3e0a5 11 *
3f1530c1 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
c4a3e0a5 16 *
3f1530c1 17 * You should have received a copy of the GNU General Public License
e399065b 18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
3f1530c1 19 *
20 * FILE: megaraid_sas.h
21 *
e399065b
SS		 22 * Authors: Avago Technologies
23 * Kashyap Desai <kashyap.desai@avagotech.com>
24 * Sumit Saxena <sumit.saxena@avagotech.com>
3f1530c1 25 *
e399065b 26 * Send feedback to: megaraidlinux.pdl@avagotech.com
3f1530c1 27 *
e399065b
SS		 28 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
29 * San Jose, California 95131
c4a3e0a5
BS		 30 */
31
32#ifndef LSI_MEGARAID_SAS_H
33#define LSI_MEGARAID_SAS_H
34
a69b74d3 35/*
c4a3e0a5
BS		 36 * MegaRAID SAS Driver meta data
37 */
223e4b93
SC		 38#define MEGASAS_VERSION "07.700.00.00-rc1"
39#define MEGASAS_RELDATE "November 29, 2016"
0e98936c
SP		 40
41/*
42 * Device IDs
43 */
44#define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
af7a5647 45#define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
0e98936c 46#define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
6610a6b3
YB		 47#define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
48#define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
87911122
YB		 49#define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
50#define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
9c915a8c 51#define PCI_DEVICE_ID_LSI_FUSION 0x005b
229fe47c 52#define PCI_DEVICE_ID_LSI_PLASMA 0x002f
36807e67 53#define PCI_DEVICE_ID_LSI_INVADER 0x005d
21d3c710 54#define PCI_DEVICE_ID_LSI_FURY 0x005f
90c204bc 55#define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce
56#define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf
7364d34b 57#define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052
58#define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053
45f4f2eb
SC		 59#define PCI_DEVICE_ID_LSI_VENTURA 0x0014
60#define PCI_DEVICE_ID_LSI_HARPOON 0x0016
61#define PCI_DEVICE_ID_LSI_TOMCAT 0x0017
62#define PCI_DEVICE_ID_LSI_VENTURA_4PORT 0x001B
63#define PCI_DEVICE_ID_LSI_CRUSADER_4PORT 0x001C
0e98936c 64
39b72c3c
SS		 65/*
66 * Intel HBA SSDIDs
67 */
68#define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
69#define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
70#define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
71#define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
72#define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
73#define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
7364d34b 74#define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B
39b72c3c 75
90c204bc 76/*
77 * Intruder HBA SSDIDs
78 */
79#define MEGARAID_INTRUDER_SSDID1 0x9371
80#define MEGARAID_INTRUDER_SSDID2 0x9390
81#define MEGARAID_INTRUDER_SSDID3 0x9370
82
39b72c3c
SS		 83/*
84 * Intel HBA branding
85 */
86#define MEGARAID_INTEL_RS3DC080_BRANDING \
87 "Intel(R) RAID Controller RS3DC080"
88#define MEGARAID_INTEL_RS3DC040_BRANDING \
89 "Intel(R) RAID Controller RS3DC040"
90#define MEGARAID_INTEL_RS3SC008_BRANDING \
91 "Intel(R) RAID Controller RS3SC008"
92#define MEGARAID_INTEL_RS3MC044_BRANDING \
93 "Intel(R) RAID Controller RS3MC044"
94#define MEGARAID_INTEL_RS3WC080_BRANDING \
95 "Intel(R) RAID Controller RS3WC080"
96#define MEGARAID_INTEL_RS3WC040_BRANDING \
97 "Intel(R) RAID Controller RS3WC040"
7364d34b 98#define MEGARAID_INTEL_RMS3BC160_BRANDING \
99 "Intel(R) Integrated RAID Module RMS3BC160"
39b72c3c 100
c4a3e0a5
BS		 101/*
102 * =====================================
103 * MegaRAID SAS MFI firmware definitions
104 * =====================================
105 */
106
107/*
45f4f2eb 108 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
c4a3e0a5
BS		 109 * protocol between the software and firmware. Commands are issued using
110 * "message frames"
111 */
112
a69b74d3 113/*
c4a3e0a5
BS		 114 * FW posts its state in upper 4 bits of outbound_msg_0 register
115 */
116#define MFI_STATE_MASK 0xF0000000
117#define MFI_STATE_UNDEFINED 0x00000000
118#define MFI_STATE_BB_INIT 0x10000000
119#define MFI_STATE_FW_INIT 0x40000000
120#define MFI_STATE_WAIT_HANDSHAKE 0x60000000
121#define MFI_STATE_FW_INIT_2 0x70000000
122#define MFI_STATE_DEVICE_SCAN 0x80000000
e3bbff9f 123#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
c4a3e0a5
BS		 124#define MFI_STATE_FLUSH_CACHE 0xA0000000
125#define MFI_STATE_READY 0xB0000000
126#define MFI_STATE_OPERATIONAL 0xC0000000
127#define MFI_STATE_FAULT 0xF0000000
fc62b3fc
SS		 128#define MFI_STATE_FORCE_OCR 0x00000080
129#define MFI_STATE_DMADONE 0x00000008
130#define MFI_STATE_CRASH_DUMP_DONE 0x00000004
7e70e733 131#define MFI_RESET_REQUIRED 0x00000001
132#define MFI_RESET_ADAPTER 0x00000002
c4a3e0a5
BS		 133#define MEGAMFI_FRAME_SIZE 64
134
a69b74d3 135/*
c4a3e0a5
BS		 136 * During FW init, clear pending cmds & reset state using inbound_msg_0
137 *
138 * ABORT : Abort all pending cmds
139 * READY : Move from OPERATIONAL to READY state; discard queue info
140 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
141 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
e3bbff9f
SP		 142 * HOTPLUG : Resume from Hotplug
143 * MFI_STOP_ADP : Send signal to FW to stop processing
c4a3e0a5 144 */
39a98554 145#define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
146#define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
147#define DIAG_WRITE_ENABLE (0x00000080)
148#define DIAG_RESET_ADAPTER (0x00000004)
149
150#define MFI_ADP_RESET 0x00000040
e3bbff9f 151#define MFI_INIT_ABORT 0x00000001
c4a3e0a5
BS		 152#define MFI_INIT_READY 0x00000002
153#define MFI_INIT_MFIMODE 0x00000004
154#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
e3bbff9f
SP		 155#define MFI_INIT_HOTPLUG 0x00000010
156#define MFI_STOP_ADP 0x00000020
157#define MFI_RESET_FLAGS MFI_INIT_READY| \
158 MFI_INIT_MFIMODE| \
159 MFI_INIT_ABORT
179ac142 160#define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
c4a3e0a5 161
a69b74d3 162/*
c4a3e0a5
BS		 163 * MFI frame flags
164 */
165#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
166#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
167#define MFI_FRAME_SGL32 0x0000
168#define MFI_FRAME_SGL64 0x0002
169#define MFI_FRAME_SENSE32 0x0000
170#define MFI_FRAME_SENSE64 0x0004
171#define MFI_FRAME_DIR_NONE 0x0000
172#define MFI_FRAME_DIR_WRITE 0x0008
173#define MFI_FRAME_DIR_READ 0x0010
174#define MFI_FRAME_DIR_BOTH 0x0018
f4c9a131 175#define MFI_FRAME_IEEE 0x0020
c4a3e0a5 176
4026e9aa
SS		 177/* Driver internal */
178#define DRV_DCMD_POLLED_MODE 0x1
6d40afbc 179#define DRV_DCMD_SKIP_REFIRE 0x2
4026e9aa 180
a69b74d3 181/*
c4a3e0a5
BS		 182 * Definition for cmd_status
183 */
184#define MFI_CMD_STATUS_POLL_MODE 0xFF
185
a69b74d3 186/*
c4a3e0a5
BS		 187 * MFI command opcodes
188 */
189#define MFI_CMD_INIT 0x00
190#define MFI_CMD_LD_READ 0x01
191#define MFI_CMD_LD_WRITE 0x02
192#define MFI_CMD_LD_SCSI_IO 0x03
193#define MFI_CMD_PD_SCSI_IO 0x04
194#define MFI_CMD_DCMD 0x05
195#define MFI_CMD_ABORT 0x06
196#define MFI_CMD_SMP 0x07
197#define MFI_CMD_STP 0x08
e5f93a36 198#define MFI_CMD_INVALID 0xff
c4a3e0a5
BS		 199
200#define MR_DCMD_CTRL_GET_INFO 0x01010000
bdc6fb8d 201#define MR_DCMD_LD_GET_LIST 0x03010000
21c9e160 202#define MR_DCMD_LD_LIST_QUERY 0x03010100
c4a3e0a5
BS		 203
204#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
205#define MR_FLUSH_CTRL_CACHE 0x01
206#define MR_FLUSH_DISK_CACHE 0x02
207
208#define MR_DCMD_CTRL_SHUTDOWN 0x01050000
31ea7088 209#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
c4a3e0a5
BS		 210#define MR_ENABLE_DRIVE_SPINDOWN 0x01
211
212#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
213#define MR_DCMD_CTRL_EVENT_GET 0x01040300
214#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
215#define MR_DCMD_LD_GET_PROPERTIES 0x03030000
216
217#define MR_DCMD_CLUSTER 0x08000000
218#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
219#define MR_DCMD_CLUSTER_RESET_LD 0x08010200
81e403ce 220#define MR_DCMD_PD_LIST_QUERY 0x02010100
c4a3e0a5 221
fc62b3fc
SS		 222#define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100
223#define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600)
2216c305 224#define MR_DCMD_PD_GET_INFO 0x02020000
fc62b3fc 225
bc93d425
SS		 226/*
227 * Global functions
228 */
229extern u8 MR_ValidateMapInfo(struct megasas_instance *instance);
230
231
a69b74d3 232/*
c4a3e0a5
BS		 233 * MFI command completion codes
234 */
235enum MFI_STAT {
236 MFI_STAT_OK = 0x00,
237 MFI_STAT_INVALID_CMD = 0x01,
238 MFI_STAT_INVALID_DCMD = 0x02,
239 MFI_STAT_INVALID_PARAMETER = 0x03,
240 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
241 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
242 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
243 MFI_STAT_APP_IN_USE = 0x07,
244 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
245 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
246 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
247 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
248 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
249 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
250 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
251 MFI_STAT_FLASH_BUSY = 0x0f,
252 MFI_STAT_FLASH_ERROR = 0x10,
253 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
254 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
255 MFI_STAT_FLASH_NOT_OPEN = 0x13,
256 MFI_STAT_FLASH_NOT_STARTED = 0x14,
257 MFI_STAT_FLUSH_FAILED = 0x15,
258 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
259 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
260 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
261 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
262 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
263 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
264 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
265 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
266 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
267 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
268 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
269 MFI_STAT_MFC_HW_ERROR = 0x21,
270 MFI_STAT_NO_HW_PRESENT = 0x22,
271 MFI_STAT_NOT_FOUND = 0x23,
272 MFI_STAT_NOT_IN_ENCL = 0x24,
273 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
274 MFI_STAT_PD_TYPE_WRONG = 0x26,
275 MFI_STAT_PR_DISABLED = 0x27,
276 MFI_STAT_ROW_INDEX_INVALID = 0x28,
277 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
278 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
279 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
280 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
281 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
282 MFI_STAT_SCSI_IO_FAILED = 0x2e,
283 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
284 MFI_STAT_SHUTDOWN_FAILED = 0x30,
285 MFI_STAT_TIME_NOT_SET = 0x31,
286 MFI_STAT_WRONG_STATE = 0x32,
287 MFI_STAT_LD_OFFLINE = 0x33,
288 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
289 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
290 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
291 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
292 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
36807e67 293 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
c4a3e0a5
BS		 294
295 MFI_STAT_INVALID_STATUS = 0xFF
296};
297
714f5177 298enum mfi_evt_class {
299 MFI_EVT_CLASS_DEBUG = -2,
300 MFI_EVT_CLASS_PROGRESS = -1,
301 MFI_EVT_CLASS_INFO = 0,
302 MFI_EVT_CLASS_WARNING = 1,
303 MFI_EVT_CLASS_CRITICAL = 2,
304 MFI_EVT_CLASS_FATAL = 3,
305 MFI_EVT_CLASS_DEAD = 4
306};
307
fc62b3fc
SS		 308/*
309 * Crash dump related defines
310 */
311#define MAX_CRASH_DUMP_SIZE 512
312#define CRASH_DMA_BUF_SIZE (1024 * 1024)
313
314enum MR_FW_CRASH_DUMP_STATE {
315 UNAVAILABLE = 0,
316 AVAILABLE = 1,
317 COPYING = 2,
318 COPIED = 3,
319 COPY_ERROR = 4,
320};
321
322enum _MR_CRASH_BUF_STATUS {
323 MR_CRASH_BUF_TURN_OFF = 0,
324 MR_CRASH_BUF_TURN_ON = 1,
325};
326
c4a3e0a5
BS		 327/*
328 * Number of mailbox bytes in DCMD message frame
329 */
330#define MFI_MBOX_SIZE 12
331
332enum MR_EVT_CLASS {
333
334 MR_EVT_CLASS_DEBUG = -2,
335 MR_EVT_CLASS_PROGRESS = -1,
336 MR_EVT_CLASS_INFO = 0,
337 MR_EVT_CLASS_WARNING = 1,
338 MR_EVT_CLASS_CRITICAL = 2,
339 MR_EVT_CLASS_FATAL = 3,
340 MR_EVT_CLASS_DEAD = 4,
341
342};
343
344enum MR_EVT_LOCALE {
345
346 MR_EVT_LOCALE_LD = 0x0001,
347 MR_EVT_LOCALE_PD = 0x0002,
348 MR_EVT_LOCALE_ENCL = 0x0004,
349 MR_EVT_LOCALE_BBU = 0x0008,
350 MR_EVT_LOCALE_SAS = 0x0010,
351 MR_EVT_LOCALE_CTRL = 0x0020,
352 MR_EVT_LOCALE_CONFIG = 0x0040,
353 MR_EVT_LOCALE_CLUSTER = 0x0080,
354 MR_EVT_LOCALE_ALL = 0xffff,
355
356};
357
358enum MR_EVT_ARGS {
359
360 MR_EVT_ARGS_NONE,
361 MR_EVT_ARGS_CDB_SENSE,
362 MR_EVT_ARGS_LD,
363 MR_EVT_ARGS_LD_COUNT,
364 MR_EVT_ARGS_LD_LBA,
365 MR_EVT_ARGS_LD_OWNER,
366 MR_EVT_ARGS_LD_LBA_PD_LBA,
367 MR_EVT_ARGS_LD_PROG,
368 MR_EVT_ARGS_LD_STATE,
369 MR_EVT_ARGS_LD_STRIP,
370 MR_EVT_ARGS_PD,
371 MR_EVT_ARGS_PD_ERR,
372 MR_EVT_ARGS_PD_LBA,
373 MR_EVT_ARGS_PD_LBA_LD,
374 MR_EVT_ARGS_PD_PROG,
375 MR_EVT_ARGS_PD_STATE,
376 MR_EVT_ARGS_PCI,
377 MR_EVT_ARGS_RATE,
378 MR_EVT_ARGS_STR,
379 MR_EVT_ARGS_TIME,
380 MR_EVT_ARGS_ECC,
81e403ce
YB		 381 MR_EVT_ARGS_LD_PROP,
382 MR_EVT_ARGS_PD_SPARE,
383 MR_EVT_ARGS_PD_INDEX,
384 MR_EVT_ARGS_DIAG_PASS,
385 MR_EVT_ARGS_DIAG_FAIL,
386 MR_EVT_ARGS_PD_LBA_LBA,
387 MR_EVT_ARGS_PORT_PHY,
388 MR_EVT_ARGS_PD_MISSING,
389 MR_EVT_ARGS_PD_ADDRESS,
390 MR_EVT_ARGS_BITMAP,
391 MR_EVT_ARGS_CONNECTOR,
392 MR_EVT_ARGS_PD_PD,
393 MR_EVT_ARGS_PD_FRU,
394 MR_EVT_ARGS_PD_PATHINFO,
395 MR_EVT_ARGS_PD_POWER_STATE,
396 MR_EVT_ARGS_GENERIC,
397};
c4a3e0a5 398
357ae967 399
400#define SGE_BUFFER_SIZE 4096
8f67c8c5 401#define MEGASAS_CLUSTER_ID_SIZE 16
81e403ce
YB		 402/*
403 * define constants for device list query options
404 */
405enum MR_PD_QUERY_TYPE {
406 MR_PD_QUERY_TYPE_ALL = 0,
407 MR_PD_QUERY_TYPE_STATE = 1,
408 MR_PD_QUERY_TYPE_POWER_STATE = 2,
409 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
410 MR_PD_QUERY_TYPE_SPEED = 4,
411 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
c4a3e0a5
BS		 412};
413
21c9e160 414enum MR_LD_QUERY_TYPE {
415 MR_LD_QUERY_TYPE_ALL = 0,
416 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
417 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2,
418 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3,
419 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4,
420};
421
422
7e8a75f4
YB		 423#define MR_EVT_CFG_CLEARED 0x0004
424#define MR_EVT_LD_STATE_CHANGE 0x0051
425#define MR_EVT_PD_INSERTED 0x005b
426#define MR_EVT_PD_REMOVED 0x0070
427#define MR_EVT_LD_CREATED 0x008a
428#define MR_EVT_LD_DELETED 0x008b
429#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
430#define MR_EVT_LD_OFFLINE 0x00fc
431#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
c4bd2654 432#define MR_EVT_CTRL_PROP_CHANGED 0x012f
7e8a75f4 433
81e403ce
YB		 434enum MR_PD_STATE {
435 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
436 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
437 MR_PD_STATE_HOT_SPARE = 0x02,
438 MR_PD_STATE_OFFLINE = 0x10,
439 MR_PD_STATE_FAILED = 0x11,
440 MR_PD_STATE_REBUILD = 0x14,
441 MR_PD_STATE_ONLINE = 0x18,
442 MR_PD_STATE_COPYBACK = 0x20,
443 MR_PD_STATE_SYSTEM = 0x40,
444 };
445
2216c305
SS		 446union MR_PD_REF {
447 struct {
448 u16 deviceId;
449 u16 seqNum;
450 } mrPdRef;
451 u32 ref;
452};
453
454/*
455 * define the DDF Type bit structure
456 */
457union MR_PD_DDF_TYPE {
458 struct {
459 union {
460 struct {
461#ifndef __BIG_ENDIAN_BITFIELD
462 u16 forcedPDGUID:1;
463 u16 inVD:1;
464 u16 isGlobalSpare:1;
465 u16 isSpare:1;
466 u16 isForeign:1;
467 u16 reserved:7;
468 u16 intf:4;
469#else
470 u16 intf:4;
471 u16 reserved:7;
472 u16 isForeign:1;
473 u16 isSpare:1;
474 u16 isGlobalSpare:1;
475 u16 inVD:1;
476 u16 forcedPDGUID:1;
477#endif
478 } pdType;
479 u16 type;
480 };
481 u16 reserved;
482 } ddf;
483 struct {
484 u32 reserved;
485 } nonDisk;
486 u32 type;
487} __packed;
488
489/*
490 * defines the progress structure
491 */
492union MR_PROGRESS {
493 struct {
494 u16 progress;
495 union {
496 u16 elapsedSecs;
497 u16 elapsedSecsForLastPercent;
498 };
499 } mrProgress;
500 u32 w;
501} __packed;
502
503/*
504 * defines the physical drive progress structure
505 */
506struct MR_PD_PROGRESS {
507 struct {
508#ifndef MFI_BIG_ENDIAN
509 u32 rbld:1;
510 u32 patrol:1;
511 u32 clear:1;
512 u32 copyBack:1;
513 u32 erase:1;
514 u32 locate:1;
515 u32 reserved:26;
516#else
517 u32 reserved:26;
518 u32 locate:1;
519 u32 erase:1;
520 u32 copyBack:1;
521 u32 clear:1;
522 u32 patrol:1;
523 u32 rbld:1;
524#endif
525 } active;
526 union MR_PROGRESS rbld;
527 union MR_PROGRESS patrol;
528 union {
529 union MR_PROGRESS clear;
530 union MR_PROGRESS erase;
531 };
532
533 struct {
534#ifndef MFI_BIG_ENDIAN
535 u32 rbld:1;
536 u32 patrol:1;
537 u32 clear:1;
538 u32 copyBack:1;
539 u32 erase:1;
540 u32 reserved:27;
541#else
542 u32 reserved:27;
543 u32 erase:1;
544 u32 copyBack:1;
545 u32 clear:1;
546 u32 patrol:1;
547 u32 rbld:1;
548#endif
549 } pause;
550
551 union MR_PROGRESS reserved[3];
552} __packed;
553
554struct MR_PD_INFO {
555 union MR_PD_REF ref;
556 u8 inquiryData[96];
557 u8 vpdPage83[64];
558 u8 notSupported;
559 u8 scsiDevType;
560
561 union {
562 u8 connectedPortBitmap;
563 u8 connectedPortNumbers;
564 };
565
566 u8 deviceSpeed;
567 u32 mediaErrCount;
568 u32 otherErrCount;
569 u32 predFailCount;
570 u32 lastPredFailEventSeqNum;
571
572 u16 fwState;
573 u8 disabledForRemoval;
574 u8 linkSpeed;
575 union MR_PD_DDF_TYPE state;
576
577 struct {
578 u8 count;
579#ifndef __BIG_ENDIAN_BITFIELD
580 u8 isPathBroken:4;
581 u8 reserved3:3;
582 u8 widePortCapable:1;
583#else
584 u8 widePortCapable:1;
585 u8 reserved3:3;
586 u8 isPathBroken:4;
587#endif
588
589 u8 connectorIndex[2];
590 u8 reserved[4];
591 u64 sasAddr[2];
592 u8 reserved2[16];
593 } pathInfo;
594
595 u64 rawSize;
596 u64 nonCoercedSize;
597 u64 coercedSize;
598 u16 enclDeviceId;
599 u8 enclIndex;
600
601 union {
602 u8 slotNumber;
603 u8 enclConnectorIndex;
604 };
605
606 struct MR_PD_PROGRESS progInfo;
607 u8 badBlockTableFull;
608 u8 unusableInCurrentConfig;
609 u8 vpdPage83Ext[64];
610 u8 powerState;
611 u8 enclPosition;
612 u32 allowedOps;
613 u16 copyBackPartnerId;
614 u16 enclPartnerDeviceId;
615 struct {
616#ifndef __BIG_ENDIAN_BITFIELD
617 u16 fdeCapable:1;
618 u16 fdeEnabled:1;
619 u16 secured:1;
620 u16 locked:1;
621 u16 foreign:1;
622 u16 needsEKM:1;
623 u16 reserved:10;
624#else
625 u16 reserved:10;
626 u16 needsEKM:1;
627 u16 foreign:1;
628 u16 locked:1;
629 u16 secured:1;
630 u16 fdeEnabled:1;
631 u16 fdeCapable:1;
632#endif
633 } security;
634 u8 mediaType;
635 u8 notCertified;
636 u8 bridgeVendor[8];
637 u8 bridgeProductIdentification[16];
638 u8 bridgeProductRevisionLevel[4];
639 u8 satBridgeExists;
640
641 u8 interfaceType;
642 u8 temperature;
643 u8 emulatedBlockSize;
644 u16 userDataBlockSize;
645 u16 reserved2;
646
647 struct {
648#ifndef __BIG_ENDIAN_BITFIELD
649 u32 piType:3;
650 u32 piFormatted:1;
651 u32 piEligible:1;
652 u32 NCQ:1;
653 u32 WCE:1;
654 u32 commissionedSpare:1;
655 u32 emergencySpare:1;
656 u32 ineligibleForSSCD:1;
657 u32 ineligibleForLd:1;
658 u32 useSSEraseType:1;
659 u32 wceUnchanged:1;
660 u32 supportScsiUnmap:1;
661 u32 reserved:18;
662#else
663 u32 reserved:18;
664 u32 supportScsiUnmap:1;
665 u32 wceUnchanged:1;
666 u32 useSSEraseType:1;
667 u32 ineligibleForLd:1;
668 u32 ineligibleForSSCD:1;
669 u32 emergencySpare:1;
670 u32 commissionedSpare:1;
671 u32 WCE:1;
672 u32 NCQ:1;
673 u32 piEligible:1;
674 u32 piFormatted:1;
675 u32 piType:3;
676#endif
677 } properties;
678
679 u64 shieldDiagCompletionTime;
680 u8 shieldCounter;
681
682 u8 linkSpeedOther;
683 u8 reserved4[2];
684
685 struct {
686#ifndef __BIG_ENDIAN_BITFIELD
687 u32 bbmErrCountSupported:1;
688 u32 bbmErrCount:31;
689#else
690 u32 bbmErrCount:31;
691 u32 bbmErrCountSupported:1;
692#endif
693 } bbmErr;
694
695 u8 reserved1[512-428];
696} __packed;
81e403ce 697
96188a89
S		 698/*
699 * Definition of structure used to expose attributes of VD or JBOD
700 * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP
701 * is fired by driver)
702 */
703struct MR_TARGET_PROPERTIES {
704 u32 max_io_size_kb;
705 u32 device_qdepth;
706 u32 sector_size;
707 u8 reserved[500];
708} __packed;
709
81e403ce
YB		 710 /*
711 * defines the physical drive address structure
712 */
713struct MR_PD_ADDRESS {
9ab9ed38 714 __le16 deviceId;
81e403ce
YB		 715 u16 enclDeviceId;
716
717 union {
718 struct {
719 u8 enclIndex;
720 u8 slotNumber;
721 } mrPdAddress;
722 struct {
723 u8 enclPosition;
724 u8 enclConnectorIndex;
725 } mrEnclAddress;
726 };
727 u8 scsiDevType;
728 union {
729 u8 connectedPortBitmap;
730 u8 connectedPortNumbers;
731 };
732 u64 sasAddr[2];
733} __packed;
734
735/*
736 * defines the physical drive list structure
737 */
738struct MR_PD_LIST {
9ab9ed38
CH		 739 __le32 size;
740 __le32 count;
81e403ce
YB		 741 struct MR_PD_ADDRESS addr[1];
742} __packed;
743
744struct megasas_pd_list {
745 u16 tid;
746 u8 driveType;
747 u8 driveState;
748} __packed;
749
bdc6fb8d
YB		 750 /*
751 * defines the logical drive reference structure
752 */
753union MR_LD_REF {
754 struct {
755 u8 targetId;
756 u8 reserved;
9ab9ed38 757 __le16 seqNum;
bdc6fb8d 758 };
9ab9ed38 759 __le32 ref;
bdc6fb8d
YB		 760} __packed;
761
762/*
763 * defines the logical drive list structure
764 */
765struct MR_LD_LIST {
9ab9ed38
CH		 766 __le32 ldCount;
767 __le32 reserved;
bdc6fb8d
YB		 768 struct {
769 union MR_LD_REF ref;
770 u8 state;
771 u8 reserved[3];
9ab9ed38 772 __le64 size;
51087a86 773 } ldList[MAX_LOGICAL_DRIVES_EXT];
bdc6fb8d
YB		 774} __packed;
775
21c9e160 776struct MR_LD_TARGETID_LIST {
9ab9ed38
CH		 777 __le32 size;
778 __le32 count;
21c9e160 779 u8 pad[3];
51087a86 780 u8 targetId[MAX_LOGICAL_DRIVES_EXT];
21c9e160 781};
782
783
c4a3e0a5
BS		 784/*
785 * SAS controller properties
786 */
787struct megasas_ctrl_prop {
788
789 u16 seq_num;
790 u16 pred_fail_poll_interval;
791 u16 intr_throttle_count;
792 u16 intr_throttle_timeouts;
793 u8 rebuild_rate;
794 u8 patrol_read_rate;
795 u8 bgi_rate;
796 u8 cc_rate;
797 u8 recon_rate;
798 u8 cache_flush_interval;
799 u8 spinup_drv_count;
800 u8 spinup_delay;
801 u8 cluster_enable;
802 u8 coercion_mode;
803 u8 alarm_enable;
804 u8 disable_auto_rebuild;
805 u8 disable_battery_warn;
806 u8 ecc_bucket_size;
807 u16 ecc_bucket_leak_rate;
808 u8 restore_hotspare_on_insertion;
809 u8 expose_encl_devices;
39a98554 810 u8 maintainPdFailHistory;
811 u8 disallowHostRequestReordering;
812 u8 abortCCOnError;
813 u8 loadBalanceMode;
814 u8 disableAutoDetectBackplane;
815
816 u8 snapVDSpace;
817
818 /*
819 * Add properties that can be controlled by
820 * a bit in the following structure.
821 */
39a98554 822 struct {
94cd65dd
SS		 823#if defined(__BIG_ENDIAN_BITFIELD)
824 u32 reserved:18;
825 u32 enableJBOD:1;
826 u32 disableSpinDownHS:1;
827 u32 allowBootWithPinnedCache:1;
828 u32 disableOnlineCtrlReset:1;
829 u32 enableSecretKeyControl:1;
830 u32 autoEnhancedImport:1;
831 u32 enableSpinDownUnconfigured:1;
832 u32 SSDPatrolReadEnabled:1;
833 u32 SSDSMARTerEnabled:1;
834 u32 disableNCQ:1;
835 u32 useFdeOnly:1;
836 u32 prCorrectUnconfiguredAreas:1;
837 u32 SMARTerEnabled:1;
838 u32 copyBackDisabled:1;
839#else
840 u32 copyBackDisabled:1;
841 u32 SMARTerEnabled:1;
842 u32 prCorrectUnconfiguredAreas:1;
843 u32 useFdeOnly:1;
844 u32 disableNCQ:1;
845 u32 SSDSMARTerEnabled:1;
846 u32 SSDPatrolReadEnabled:1;
847 u32 enableSpinDownUnconfigured:1;
848 u32 autoEnhancedImport:1;
849 u32 enableSecretKeyControl:1;
850 u32 disableOnlineCtrlReset:1;
851 u32 allowBootWithPinnedCache:1;
852 u32 disableSpinDownHS:1;
853 u32 enableJBOD:1;
854 u32 reserved:18;
855#endif
39a98554 856 } OnOffProperties;
857 u8 autoSnapVDSpace;
858 u8 viewSpace;
9ab9ed38 859 __le16 spinDownTime;
39a98554 860 u8 reserved[24];
81e403ce 861} __packed;
c4a3e0a5
BS		 862
863/*
864 * SAS controller information
865 */
866struct megasas_ctrl_info {
867
868 /*
869 * PCI device information
870 */
871 struct {
872
9ab9ed38
CH		 873 __le16 vendor_id;
874 __le16 device_id;
875 __le16 sub_vendor_id;
876 __le16 sub_device_id;
c4a3e0a5
BS		 877 u8 reserved[24];
878
879 } __attribute__ ((packed)) pci;
880
881 /*
882 * Host interface information
883 */
884 struct {
885
886 u8 PCIX:1;
887 u8 PCIE:1;
888 u8 iSCSI:1;
889 u8 SAS_3G:1;
229fe47c 890 u8 SRIOV:1;
891 u8 reserved_0:3;
c4a3e0a5
BS		 892 u8 reserved_1[6];
893 u8 port_count;
894 u64 port_addr[8];
895
896 } __attribute__ ((packed)) host_interface;
897
898 /*
899 * Device (backend) interface information
900 */
901 struct {
902
903 u8 SPI:1;
904 u8 SAS_3G:1;
905 u8 SATA_1_5G:1;
906 u8 SATA_3G:1;
907 u8 reserved_0:4;
908 u8 reserved_1[6];
909 u8 port_count;
910 u64 port_addr[8];
911
912 } __attribute__ ((packed)) device_interface;
913
914 /*
915 * List of components residing in flash. All str are null terminated
916 */
9ab9ed38
CH		 917 __le32 image_check_word;
918 __le32 image_component_count;
c4a3e0a5
BS		 919
920 struct {
921
922 char name[8];
923 char version[32];
924 char build_date[16];
925 char built_time[16];
926
927 } __attribute__ ((packed)) image_component[8];
928
929 /*
930 * List of flash components that have been flashed on the card, but
931 * are not in use, pending reset of the adapter. This list will be
932 * empty if a flash operation has not occurred. All stings are null
933 * terminated
934 */
9ab9ed38 935 __le32 pending_image_component_count;
c4a3e0a5
BS		 936
937 struct {
938
939 char name[8];
940 char version[32];
941 char build_date[16];
942 char build_time[16];
943
944 } __attribute__ ((packed)) pending_image_component[8];
945
946 u8 max_arms;
947 u8 max_spans;
948 u8 max_arrays;
949 u8 max_lds;
950
951 char product_name[80];
952 char serial_no[32];
953
954 /*
955 * Other physical/controller/operation information. Indicates the
956 * presence of the hardware
957 */
958 struct {
959
960 u32 bbu:1;
961 u32 alarm:1;
962 u32 nvram:1;
963 u32 uart:1;
964 u32 reserved:28;
965
966 } __attribute__ ((packed)) hw_present;
967
9ab9ed38 968 __le32 current_fw_time;
c4a3e0a5
BS		 969
970 /*
971 * Maximum data transfer sizes
972 */
9ab9ed38
CH		 973 __le16 max_concurrent_cmds;
974 __le16 max_sge_count;
975 __le32 max_request_size;
c4a3e0a5
BS		 976
977 /*
978 * Logical and physical device counts
979 */
9ab9ed38
CH		 980 __le16 ld_present_count;
981 __le16 ld_degraded_count;
982 __le16 ld_offline_count;
c4a3e0a5 983
9ab9ed38
CH		 984 __le16 pd_present_count;
985 __le16 pd_disk_present_count;
986 __le16 pd_disk_pred_failure_count;
987 __le16 pd_disk_failed_count;
c4a3e0a5
BS		 988
989 /*
990 * Memory size information
991 */
9ab9ed38
CH		 992 __le16 nvram_size;
993 __le16 memory_size;
994 __le16 flash_size;
c4a3e0a5
BS		 995
996 /*
997 * Error counters
998 */
9ab9ed38
CH		 999 __le16 mem_correctable_error_count;
1000 __le16 mem_uncorrectable_error_count;
c4a3e0a5
BS		 1001
1002 /*
1003 * Cluster information
1004 */
1005 u8 cluster_permitted;
1006 u8 cluster_active;
1007
1008 /*
1009 * Additional max data transfer sizes
1010 */
9ab9ed38 1011 __le16 max_strips_per_io;
c4a3e0a5
BS		 1012
1013 /*
1014 * Controller capabilities structures
1015 */
1016 struct {
1017
1018 u32 raid_level_0:1;
1019 u32 raid_level_1:1;
1020 u32 raid_level_5:1;
1021 u32 raid_level_1E:1;
1022 u32 raid_level_6:1;
1023 u32 reserved:27;
1024
1025 } __attribute__ ((packed)) raid_levels;
1026
1027 struct {
1028
1029 u32 rbld_rate:1;
1030 u32 cc_rate:1;
1031 u32 bgi_rate:1;
1032 u32 recon_rate:1;
1033 u32 patrol_rate:1;
1034 u32 alarm_control:1;
1035 u32 cluster_supported:1;
1036 u32 bbu:1;
1037 u32 spanning_allowed:1;
1038 u32 dedicated_hotspares:1;
1039 u32 revertible_hotspares:1;
1040 u32 foreign_config_import:1;
1041 u32 self_diagnostic:1;
1042 u32 mixed_redundancy_arr:1;
1043 u32 global_hot_spares:1;
1044 u32 reserved:17;
1045
1046 } __attribute__ ((packed)) adapter_operations;
1047
1048 struct {
1049
1050 u32 read_policy:1;
1051 u32 write_policy:1;
1052 u32 io_policy:1;
1053 u32 access_policy:1;
1054 u32 disk_cache_policy:1;
1055 u32 reserved:27;
1056
1057 } __attribute__ ((packed)) ld_operations;
1058
1059 struct {
1060
1061 u8 min;
1062 u8 max;
1063 u8 reserved[2];
1064
1065 } __attribute__ ((packed)) stripe_sz_ops;
1066
1067 struct {
1068
1069 u32 force_online:1;
1070 u32 force_offline:1;
1071 u32 force_rebuild:1;
1072 u32 reserved:29;
1073
1074 } __attribute__ ((packed)) pd_operations;
1075
1076 struct {
1077
1078 u32 ctrl_supports_sas:1;
1079 u32 ctrl_supports_sata:1;
1080 u32 allow_mix_in_encl:1;
1081 u32 allow_mix_in_ld:1;
1082 u32 allow_sata_in_cluster:1;
1083 u32 reserved:27;
1084
1085 } __attribute__ ((packed)) pd_mix_support;
1086
1087 /*
1088 * Define ECC single-bit-error bucket information
1089 */
1090 u8 ecc_bucket_count;
1091 u8 reserved_2[11];
1092
1093 /*
1094 * Include the controller properties (changeable items)
1095 */
1096 struct megasas_ctrl_prop properties;
1097
1098 /*
1099 * Define FW pkg version (set in envt v'bles on OEM basis)
1100 */
1101 char package_version[0x60];
1102
c4a3e0a5 1103
bc93d425
SS		 1104 /*
1105 * If adapterOperations.supportMoreThan8Phys is set,
1106 * and deviceInterface.portCount is greater than 8,
1107 * SAS Addrs for first 8 ports shall be populated in
1108 * deviceInterface.portAddr, and the rest shall be
1109 * populated in deviceInterfacePortAddr2.
1110 */
9ab9ed38 1111 __le64 deviceInterfacePortAddr2[8]; /*6a0h */
bc93d425
SS		 1112 u8 reserved3[128]; /*6e0h */
1113
1114 struct { /*760h */
1115 u16 minPdRaidLevel_0:4;
1116 u16 maxPdRaidLevel_0:12;
1117
1118 u16 minPdRaidLevel_1:4;
1119 u16 maxPdRaidLevel_1:12;
1120
1121 u16 minPdRaidLevel_5:4;
1122 u16 maxPdRaidLevel_5:12;
1123
1124 u16 minPdRaidLevel_1E:4;
1125 u16 maxPdRaidLevel_1E:12;
1126
1127 u16 minPdRaidLevel_6:4;
1128 u16 maxPdRaidLevel_6:12;
1129
1130 u16 minPdRaidLevel_10:4;
1131 u16 maxPdRaidLevel_10:12;
1132
1133 u16 minPdRaidLevel_50:4;
1134 u16 maxPdRaidLevel_50:12;
1135
1136 u16 minPdRaidLevel_60:4;
1137 u16 maxPdRaidLevel_60:12;
1138
1139 u16 minPdRaidLevel_1E_RLQ0:4;
1140 u16 maxPdRaidLevel_1E_RLQ0:12;
1141
1142 u16 minPdRaidLevel_1E0_RLQ0:4;
1143 u16 maxPdRaidLevel_1E0_RLQ0:12;
1144
1145 u16 reserved[6];
1146 } pdsForRaidLevels;
1147
9ab9ed38
CH		 1148 __le16 maxPds; /*780h */
1149 __le16 maxDedHSPs; /*782h */
1150 __le16 maxGlobalHSP; /*784h */
1151 __le16 ddfSize; /*786h */
bc93d425
SS		 1152 u8 maxLdsPerArray; /*788h */
1153 u8 partitionsInDDF; /*789h */
1154 u8 lockKeyBinding; /*78ah */
1155 u8 maxPITsPerLd; /*78bh */
1156 u8 maxViewsPerLd; /*78ch */
1157 u8 maxTargetId; /*78dh */
9ab9ed38 1158 __le16 maxBvlVdSize; /*78eh */
bc93d425 1159
9ab9ed38
CH		 1160 __le16 maxConfigurableSSCSize; /*790h */
1161 __le16 currentSSCsize; /*792h */
bc93d425
SS		 1162
1163 char expanderFwVersion[12]; /*794h */
1164
9ab9ed38 1165 __le16 PFKTrialTimeRemaining; /*7A0h */
bc93d425 1166
9ab9ed38 1167 __le16 cacheMemorySize; /*7A2h */
bc93d425
SS		 1168
1169 struct { /*7A4h */
94cd65dd 1170#if defined(__BIG_ENDIAN_BITFIELD)
229fe47c 1171 u32 reserved:5;
1172 u32 activePassive:2;
1173 u32 supportConfigAutoBalance:1;
1174 u32 mpio:1;
1175 u32 supportDataLDonSSCArray:1;
1176 u32 supportPointInTimeProgress:1;
94cd65dd
SS		 1177 u32 supportUnevenSpans:1;
1178 u32 dedicatedHotSparesLimited:1;
1179 u32 headlessMode:1;
1180 u32 supportEmulatedDrives:1;
1181 u32 supportResetNow:1;
1182 u32 realTimeScheduler:1;
1183 u32 supportSSDPatrolRead:1;
1184 u32 supportPerfTuning:1;
1185 u32 disableOnlinePFKChange:1;
1186 u32 supportJBOD:1;
1187 u32 supportBootTimePFKChange:1;
1188 u32 supportSetLinkSpeed:1;
1189 u32 supportEmergencySpares:1;
1190 u32 supportSuspendResumeBGops:1;
1191 u32 blockSSDWriteCacheChange:1;
1192 u32 supportShieldState:1;
1193 u32 supportLdBBMInfo:1;
1194 u32 supportLdPIType3:1;
1195 u32 supportLdPIType2:1;
1196 u32 supportLdPIType1:1;
1197 u32 supportPIcontroller:1;
1198#else
bc93d425
SS		 1199 u32 supportPIcontroller:1;
1200 u32 supportLdPIType1:1;
1201 u32 supportLdPIType2:1;
1202 u32 supportLdPIType3:1;
1203 u32 supportLdBBMInfo:1;
1204 u32 supportShieldState:1;
1205 u32 blockSSDWriteCacheChange:1;
1206 u32 supportSuspendResumeBGops:1;
1207 u32 supportEmergencySpares:1;
1208 u32 supportSetLinkSpeed:1;
1209 u32 supportBootTimePFKChange:1;
1210 u32 supportJBOD:1;
1211 u32 disableOnlinePFKChange:1;
1212 u32 supportPerfTuning:1;
1213 u32 supportSSDPatrolRead:1;
1214 u32 realTimeScheduler:1;
1215
1216 u32 supportResetNow:1;
1217 u32 supportEmulatedDrives:1;
1218 u32 headlessMode:1;
1219 u32 dedicatedHotSparesLimited:1;
1220
1221
1222 u32 supportUnevenSpans:1;
229fe47c 1223 u32 supportPointInTimeProgress:1;
1224 u32 supportDataLDonSSCArray:1;
1225 u32 mpio:1;
1226 u32 supportConfigAutoBalance:1;
1227 u32 activePassive:2;
1228 u32 reserved:5;
94cd65dd 1229#endif
bc93d425
SS		 1230 } adapterOperations2;
1231
1232 u8 driverVersion[32]; /*7A8h */
1233 u8 maxDAPdCountSpinup60; /*7C8h */
1234 u8 temperatureROC; /*7C9h */
1235 u8 temperatureCtrl; /*7CAh */
1236 u8 reserved4; /*7CBh */
9ab9ed38 1237 __le16 maxConfigurablePds; /*7CCh */
bc93d425
SS		 1238
1239
1240 u8 reserved5[2]; /*0x7CDh */
1241
1242 /*
1243 * HA cluster information
1244 */
1245 struct {
51087a86 1246#if defined(__BIG_ENDIAN_BITFIELD)
8f67c8c5
SS		 1247 u32 reserved:25;
1248 u32 passive:1;
51087a86
SS		 1249 u32 premiumFeatureMismatch:1;
1250 u32 ctrlPropIncompatible:1;
1251 u32 fwVersionMismatch:1;
1252 u32 hwIncompatible:1;
1253 u32 peerIsIncompatible:1;
1254 u32 peerIsPresent:1;
1255#else
bc93d425
SS		 1256 u32 peerIsPresent:1;
1257 u32 peerIsIncompatible:1;
1258 u32 hwIncompatible:1;
1259 u32 fwVersionMismatch:1;
1260 u32 ctrlPropIncompatible:1;
1261 u32 premiumFeatureMismatch:1;
8f67c8c5
SS		 1262 u32 passive:1;
1263 u32 reserved:25;
51087a86 1264#endif
bc93d425
SS		 1265 } cluster;
1266
8f67c8c5 1267 char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */
229fe47c 1268 struct {
1269 u8 maxVFsSupported; /*0x7E4*/
1270 u8 numVFsEnabled; /*0x7E5*/
1271 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/
1272 u8 reserved; /*0x7E7*/
1273 } iov;
bc93d425 1274
fc62b3fc
SS		 1275 struct {
1276#if defined(__BIG_ENDIAN_BITFIELD)
3761cb4c 1277 u32 reserved:7;
1278 u32 useSeqNumJbodFP:1;
0be3f4c9 1279 u32 supportExtendedSSCSize:1;
1280 u32 supportDiskCacheSettingForSysPDs:1;
1281 u32 supportCPLDUpdate:1;
1282 u32 supportTTYLogCompression:1;
7497cde8
SS		 1283 u32 discardCacheDuringLDDelete:1;
1284 u32 supportSecurityonJBOD:1;
1285 u32 supportCacheBypassModes:1;
1286 u32 supportDisableSESMonitoring:1;
1287 u32 supportForceFlash:1;
1288 u32 supportNVDRAM:1;
1289 u32 supportDrvActivityLEDSetting:1;
1290 u32 supportAllowedOpsforDrvRemoval:1;
1291 u32 supportHOQRebuild:1;
1292 u32 supportForceTo512e:1;
1293 u32 supportNVCacheErase:1;
1294 u32 supportDebugQueue:1;
1295 u32 supportSwZone:1;
fc62b3fc 1296 u32 supportCrashDump:1;
51087a86
SS		 1297 u32 supportMaxExtLDs:1;
1298 u32 supportT10RebuildAssist:1;
1299 u32 supportDisableImmediateIO:1;
1300 u32 supportThermalPollInterval:1;
1301 u32 supportPersonalityChange:2;
fc62b3fc 1302#else
51087a86
SS		 1303 u32 supportPersonalityChange:2;
1304 u32 supportThermalPollInterval:1;
1305 u32 supportDisableImmediateIO:1;
1306 u32 supportT10RebuildAssist:1;
7497cde8
SS		 1307 u32 supportMaxExtLDs:1;
1308 u32 supportCrashDump:1;
1309 u32 supportSwZone:1;
1310 u32 supportDebugQueue:1;
1311 u32 supportNVCacheErase:1;
1312 u32 supportForceTo512e:1;
1313 u32 supportHOQRebuild:1;
1314 u32 supportAllowedOpsforDrvRemoval:1;
1315 u32 supportDrvActivityLEDSetting:1;
1316 u32 supportNVDRAM:1;
1317 u32 supportForceFlash:1;
1318 u32 supportDisableSESMonitoring:1;
1319 u32 supportCacheBypassModes:1;
1320 u32 supportSecurityonJBOD:1;
1321 u32 discardCacheDuringLDDelete:1;
0be3f4c9 1322 u32 supportTTYLogCompression:1;
1323 u32 supportCPLDUpdate:1;
1324 u32 supportDiskCacheSettingForSysPDs:1;
1325 u32 supportExtendedSSCSize:1;
3761cb4c 1326 u32 useSeqNumJbodFP:1;
1327 u32 reserved:7;
fc62b3fc
SS		 1328#endif
1329 } adapterOperations3;
1330
ede7c3ce
SC		 1331 struct {
1332#if defined(__BIG_ENDIAN_BITFIELD)
1333 u8 reserved:7;
1334 /* Indicates whether the CPLD image is part of
1335 * the package and stored in flash
1336 */
1337 u8 cpld_in_flash:1;
1338#else
1339 u8 cpld_in_flash:1;
1340 u8 reserved:7;
1341#endif
1342 u8 reserved1[3];
1343 /* Null terminated string. Has the version
1344 * information if cpld_in_flash = FALSE
1345 */
1346 u8 userCodeDefinition[12];
1347 } cpld; /* Valid only if upgradableCPLD is TRUE */
1348
1349 struct {
1350 #if defined(__BIG_ENDIAN_BITFIELD)
1351 u16 reserved:8;
1352 u16 fw_swaps_bbu_vpd_info:1;
1353 u16 support_pd_map_target_id:1;
1354 u16 support_ses_ctrl_in_multipathcfg:1;
1355 u16 image_upload_supported:1;
1356 u16 support_encrypted_mfc:1;
1357 u16 supported_enc_algo:1;
1358 u16 support_ibutton_less:1;
1359 u16 ctrl_info_ext_supported:1;
1360 #else
1361
1362 u16 ctrl_info_ext_supported:1;
1363 u16 support_ibutton_less:1;
1364 u16 supported_enc_algo:1;
1365 u16 support_encrypted_mfc:1;
1366 u16 image_upload_supported:1;
1367 /* FW supports LUN based association and target port based */
1368 u16 support_ses_ctrl_in_multipathcfg:1;
1369 /* association for the SES device connected in multipath mode */
1370 /* FW defines Jbod target Id within MR_PD_CFG_SEQ */
1371 u16 support_pd_map_target_id:1;
1372 /* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to
1373 * provide the data in little endian order
1374 */
1375 u16 fw_swaps_bbu_vpd_info:1;
1376 u16 reserved:8;
1377 #endif
1378 } adapter_operations4;
1379 u8 pad[0x800-0x7FE]; /* 0x7FE pad to 2K for expansion */
81e403ce 1380} __packed;
c4a3e0a5
BS		 1381
1382/*
1383 * ===============================
1384 * MegaRAID SAS driver definitions
1385 * ===============================
1386 */
1387#define MEGASAS_MAX_PD_CHANNELS 2
51087a86 1388#define MEGASAS_MAX_LD_CHANNELS 2
c4a3e0a5
BS		 1389#define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
1390 MEGASAS_MAX_LD_CHANNELS)
1391#define MEGASAS_MAX_DEV_PER_CHANNEL 128
1392#define MEGASAS_DEFAULT_INIT_ID -1
1393#define MEGASAS_MAX_LUN 8
6bf579a3 1394#define MEGASAS_DEFAULT_CMD_PER_LUN 256
81e403ce
YB		 1395#define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
1396 MEGASAS_MAX_DEV_PER_CHANNEL)
bdc6fb8d
YB		 1397#define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
1398 MEGASAS_MAX_DEV_PER_CHANNEL)
c4a3e0a5 1399
1fd10685 1400#define MEGASAS_MAX_SECTORS (2*1024)
42a8d2b3 1401#define MEGASAS_MAX_SECTORS_IEEE (2*128)
658dcedb
SP		 1402#define MEGASAS_DBG_LVL 1
1403
05e9ebbe
SP		 1404#define MEGASAS_FW_BUSY 1
1405
51087a86
SS		 1406#define VD_EXT_DEBUG 0
1407
def0eab3
S		 1408/* Driver's internal Logging levels*/
1409#define OCR_LOGS (1 << 0)
1410
11c71cb4
SS		 1411#define SCAN_PD_CHANNEL 0x1
1412#define SCAN_VD_CHANNEL 0x2
90dc9d98 1413
c3e385a1 1414#define MEGASAS_KDUMP_QUEUE_DEPTH 100
a48ba0ec
S		 1415#define MR_LARGE_IO_MIN_SIZE (32 * 1024)
1416#define MR_R1_LDIO_PIGGYBACK_DEFAULT 4
c3e385a1 1417
7497cde8
SS		 1418enum MR_SCSI_CMD_TYPE {
1419 READ_WRITE_LDIO = 0,
1420 NON_READ_WRITE_LDIO = 1,
1421 READ_WRITE_SYSPDIO = 2,
1422 NON_READ_WRITE_SYSPDIO = 3,
1423};
1424
6d40afbc
SS		 1425enum DCMD_TIMEOUT_ACTION {
1426 INITIATE_OCR = 0,
1427 KILL_ADAPTER = 1,
1428 IGNORE_TIMEOUT = 2,
1429};
308ec459
SS		 1430
1431enum FW_BOOT_CONTEXT {
1432 PROBE_CONTEXT = 0,
1433 OCR_CONTEXT = 1,
1434};
1435
d532dbe2 1436/* Frame Type */
1437#define IO_FRAME 0
1438#define PTHRU_FRAME 1
1439
c4a3e0a5
BS		 1440/*
1441 * When SCSI mid-layer calls driver's reset routine, driver waits for
1442 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1443 * that the driver cannot _actually_ abort or reset pending commands. While
1444 * it is waiting for the commands to complete, it prints a diagnostic message
1445 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1446 */
1447#define MEGASAS_RESET_WAIT_TIME 180
2a3681e5 1448#define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
c4a3e0a5 1449#define MEGASAS_RESET_NOTICE_INTERVAL 5
c4a3e0a5 1450#define MEGASAS_IOCTL_CMD 0
05e9ebbe 1451#define MEGASAS_DEFAULT_CMD_TIMEOUT 90
c5daa6a9 1452#define MEGASAS_THROTTLE_QUEUE_DEPTH 16
90dc9d98 1453#define MEGASAS_BLOCKED_CMD_TIMEOUT 60
c4a3e0a5
BS		 1454/*
1455 * FW reports the maximum of number of commands that it can accept (maximum
1456 * commands that can be outstanding) at any time. The driver must report a
1457 * lower number to the mid layer because it can issue a few internal commands
1458 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1459 * is shown below
1460 */
1461#define MEGASAS_INT_CMDS 32
7bebf5c7 1462#define MEGASAS_SKINNY_INT_CMDS 5
ae09a6c1
SS		 1463#define MEGASAS_FUSION_INTERNAL_CMDS 5
1464#define MEGASAS_FUSION_IOCTL_CMDS 3
f26ac3a1 1465#define MEGASAS_MFI_IOCTL_CMDS 27
c4a3e0a5 1466
d46a3ad6 1467#define MEGASAS_MAX_MSIX_QUEUES 128
c4a3e0a5
BS		 1468/*
1469 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1470 * SGLs based on the size of dma_addr_t
1471 */
1472#define IS_DMA64 (sizeof(dma_addr_t) == 8)
1473
39a98554 1474#define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
1475
1476#define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
1477#define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
1478#define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
1479
c4a3e0a5 1480#define MFI_OB_INTR_STATUS_MASK 0x00000002
14faea9f 1481#define MFI_POLL_TIMEOUT_SECS 60
6d40afbc 1482#define MFI_IO_TIMEOUT_SECS 180
229fe47c 1483#define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ)
1484#define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30)
1485#define MEGASAS_ROUTINE_WAIT_TIME_VF 300
f9876f0b 1486#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
6610a6b3
YB		 1487#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
1488#define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
87911122
YB		 1489#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
1490#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
0e98936c 1491
39a98554 1492#define MFI_1068_PCSR_OFFSET 0x84
1493#define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
1494#define MFI_1068_FW_READY 0xDDDD0000
d46a3ad6
SS		 1495
1496#define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
1497#define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
1498#define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
1499#define MR_MAX_MSIX_REG_ARRAY 16
179ac142 1500#define MR_RDPQ_MODE_OFFSET 0X00800000
d889344e
SC		 1501
1502#define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16
1503#define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF
1504#define MR_MIN_MAP_SIZE 0x10000
1505/* 64k */
1506
d0fc91d6
KD		 1507#define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000
1508
0e98936c
SP		 1509/*
1510* register set for both 1068 and 1078 controllers
1511* structure extended for 1078 registers
1512*/
45f4f2eb 1513
c4a3e0a5 1514struct megasas_register_set {
9c915a8c 1515 u32 doorbell; /*0000h*/
1516 u32 fusion_seq_offset; /*0004h*/
1517 u32 fusion_host_diag; /*0008h*/
1518 u32 reserved_01; /*000Ch*/
c4a3e0a5 1519
f9876f0b
SP		 1520 u32 inbound_msg_0; /*0010h*/
1521 u32 inbound_msg_1; /*0014h*/
1522 u32 outbound_msg_0; /*0018h*/
1523 u32 outbound_msg_1; /*001Ch*/
c4a3e0a5 1524
f9876f0b
SP		 1525 u32 inbound_doorbell; /*0020h*/
1526 u32 inbound_intr_status; /*0024h*/
1527 u32 inbound_intr_mask; /*0028h*/
c4a3e0a5 1528
f9876f0b
SP		 1529 u32 outbound_doorbell; /*002Ch*/
1530 u32 outbound_intr_status; /*0030h*/
1531 u32 outbound_intr_mask; /*0034h*/
c4a3e0a5 1532
f9876f0b 1533 u32 reserved_1[2]; /*0038h*/
c4a3e0a5 1534
f9876f0b
SP		 1535 u32 inbound_queue_port; /*0040h*/
1536 u32 outbound_queue_port; /*0044h*/
c4a3e0a5 1537
9c915a8c 1538 u32 reserved_2[9]; /*0048h*/
1539 u32 reply_post_host_index; /*006Ch*/
1540 u32 reserved_2_2[12]; /*0070h*/
c4a3e0a5 1541
f9876f0b 1542 u32 outbound_doorbell_clear; /*00A0h*/
c4a3e0a5 1543
f9876f0b
SP		 1544 u32 reserved_3[3]; /*00A4h*/
1545
1546 u32 outbound_scratch_pad ; /*00B0h*/
9c915a8c 1547 u32 outbound_scratch_pad_2; /*00B4h*/
179ac142 1548 u32 outbound_scratch_pad_3; /*00B8h*/
15dd0381 1549 u32 outbound_scratch_pad_4; /*00BCh*/
f9876f0b 1550
f9876f0b
SP		 1551
1552 u32 inbound_low_queue_port ; /*00C0h*/
1553
1554 u32 inbound_high_queue_port ; /*00C4h*/
1555
45f4f2eb 1556 u32 inbound_single_queue_port; /*00C8h*/
39a98554 1557 u32 res_6[11]; /*CCh*/
1558 u32 host_diag;
1559 u32 seq_offset;
1560 u32 index_registers[807]; /*00CCh*/
c4a3e0a5
BS		 1561} __attribute__ ((packed));
1562
1563struct megasas_sge32 {
1564
9ab9ed38
CH		 1565 __le32 phys_addr;
1566 __le32 length;
c4a3e0a5
BS		 1567
1568} __attribute__ ((packed));
1569
1570struct megasas_sge64 {
1571
9ab9ed38
CH		 1572 __le64 phys_addr;
1573 __le32 length;
c4a3e0a5
BS		 1574
1575} __attribute__ ((packed));
1576
f4c9a131 1577struct megasas_sge_skinny {
9ab9ed38
CH		 1578 __le64 phys_addr;
1579 __le32 length;
1580 __le32 flag;
f4c9a131
YB		 1581} __packed;
1582
c4a3e0a5
BS		 1583union megasas_sgl {
1584
1585 struct megasas_sge32 sge32[1];
1586 struct megasas_sge64 sge64[1];
f4c9a131 1587 struct megasas_sge_skinny sge_skinny[1];
c4a3e0a5
BS		 1588
1589} __attribute__ ((packed));
1590
1591struct megasas_header {
1592
1593 u8 cmd; /*00h */
1594 u8 sense_len; /*01h */
1595 u8 cmd_status; /*02h */
1596 u8 scsi_status; /*03h */
1597
1598 u8 target_id; /*04h */
1599 u8 lun; /*05h */
1600 u8 cdb_len; /*06h */
1601 u8 sge_count; /*07h */
1602
9ab9ed38
CH		 1603 __le32 context; /*08h */
1604 __le32 pad_0; /*0Ch */
c4a3e0a5 1605
9ab9ed38
CH		 1606 __le16 flags; /*10h */
1607 __le16 timeout; /*12h */
1608 __le32 data_xferlen; /*14h */
c4a3e0a5
BS		 1609
1610} __attribute__ ((packed));
1611
1612union megasas_sgl_frame {
1613
1614 struct megasas_sge32 sge32[8];
1615 struct megasas_sge64 sge64[5];
1616
1617} __attribute__ ((packed));
1618
d46a3ad6
SS		 1619typedef union _MFI_CAPABILITIES {
1620 struct {
94cd65dd 1621#if defined(__BIG_ENDIAN_BITFIELD)
ede7c3ce
SC		 1622 u32 reserved:19;
1623 u32 support_pd_map_target_id:1;
1624 u32 support_qd_throttling:1;
1625 u32 support_fp_rlbypass:1;
1626 u32 support_vfid_in_ioframe:1;
1627 u32 support_ext_io_size:1;
1628 u32 support_ext_queue_depth:1;
1629 u32 security_protocol_cmds_fw:1;
1630 u32 support_core_affinity:1;
1631 u32 support_ndrive_r1_lb:1;
1632 u32 support_max_255lds:1;
1633 u32 support_fastpath_wb:1;
1634 u32 support_additional_msix:1;
1635 u32 support_fp_remote_lun:1;
94cd65dd 1636#else
ede7c3ce
SC		 1637 u32 support_fp_remote_lun:1;
1638 u32 support_additional_msix:1;
1639 u32 support_fastpath_wb:1;
1640 u32 support_max_255lds:1;
1641 u32 support_ndrive_r1_lb:1;
1642 u32 support_core_affinity:1;
1643 u32 security_protocol_cmds_fw:1;
1644 u32 support_ext_queue_depth:1;
1645 u32 support_ext_io_size:1;
1646 u32 support_vfid_in_ioframe:1;
1647 u32 support_fp_rlbypass:1;
1648 u32 support_qd_throttling:1;
1649 u32 support_pd_map_target_id:1;
1650 u32 reserved:19;
94cd65dd 1651#endif
d46a3ad6 1652 } mfi_capabilities;
9ab9ed38 1653 __le32 reg;
d46a3ad6
SS		 1654} MFI_CAPABILITIES;
1655
c4a3e0a5
BS		 1656struct megasas_init_frame {
1657
1658 u8 cmd; /*00h */
1659 u8 reserved_0; /*01h */
1660 u8 cmd_status; /*02h */
1661
1662 u8 reserved_1; /*03h */
d46a3ad6 1663 MFI_CAPABILITIES driver_operations; /*04h*/
c4a3e0a5 1664
9ab9ed38
CH		 1665 __le32 context; /*08h */
1666 __le32 pad_0; /*0Ch */
c4a3e0a5 1667
9ab9ed38
CH		 1668 __le16 flags; /*10h */
1669 __le16 reserved_3; /*12h */
1670 __le32 data_xfer_len; /*14h */
c4a3e0a5 1671
9ab9ed38
CH		 1672 __le32 queue_info_new_phys_addr_lo; /*18h */
1673 __le32 queue_info_new_phys_addr_hi; /*1Ch */
1674 __le32 queue_info_old_phys_addr_lo; /*20h */
1675 __le32 queue_info_old_phys_addr_hi; /*24h */
1676 __le32 reserved_4[2]; /*28h */
1677 __le32 system_info_lo; /*30h */
1678 __le32 system_info_hi; /*34h */
1679 __le32 reserved_5[2]; /*38h */
c4a3e0a5
BS		 1680
1681} __attribute__ ((packed));
1682
1683struct megasas_init_queue_info {
1684
9ab9ed38
CH		 1685 __le32 init_flags; /*00h */
1686 __le32 reply_queue_entries; /*04h */
c4a3e0a5 1687
9ab9ed38
CH		 1688 __le32 reply_queue_start_phys_addr_lo; /*08h */
1689 __le32 reply_queue_start_phys_addr_hi; /*0Ch */
1690 __le32 producer_index_phys_addr_lo; /*10h */
1691 __le32 producer_index_phys_addr_hi; /*14h */
1692 __le32 consumer_index_phys_addr_lo; /*18h */
1693 __le32 consumer_index_phys_addr_hi; /*1Ch */
c4a3e0a5
BS		 1694
1695} __attribute__ ((packed));
1696
1697struct megasas_io_frame {
1698
1699 u8 cmd; /*00h */
1700 u8 sense_len; /*01h */
1701 u8 cmd_status; /*02h */
1702 u8 scsi_status; /*03h */
1703
1704 u8 target_id; /*04h */
1705 u8 access_byte; /*05h */
1706 u8 reserved_0; /*06h */
1707 u8 sge_count; /*07h */
1708
9ab9ed38
CH		 1709 __le32 context; /*08h */
1710 __le32 pad_0; /*0Ch */
c4a3e0a5 1711
9ab9ed38
CH		 1712 __le16 flags; /*10h */
1713 __le16 timeout; /*12h */
1714 __le32 lba_count; /*14h */
c4a3e0a5 1715
9ab9ed38
CH		 1716 __le32 sense_buf_phys_addr_lo; /*18h */
1717 __le32 sense_buf_phys_addr_hi; /*1Ch */
c4a3e0a5 1718
9ab9ed38
CH		 1719 __le32 start_lba_lo; /*20h */
1720 __le32 start_lba_hi; /*24h */
c4a3e0a5
BS		 1721
1722 union megasas_sgl sgl; /*28h */
1723
1724} __attribute__ ((packed));
1725
1726struct megasas_pthru_frame {
1727
1728 u8 cmd; /*00h */
1729 u8 sense_len; /*01h */
1730 u8 cmd_status; /*02h */
1731 u8 scsi_status; /*03h */
1732
1733 u8 target_id; /*04h */
1734 u8 lun; /*05h */
1735 u8 cdb_len; /*06h */
1736 u8 sge_count; /*07h */
1737
9ab9ed38
CH		 1738 __le32 context; /*08h */
1739 __le32 pad_0; /*0Ch */
c4a3e0a5 1740
9ab9ed38
CH		 1741 __le16 flags; /*10h */
1742 __le16 timeout; /*12h */
1743 __le32 data_xfer_len; /*14h */
c4a3e0a5 1744
9ab9ed38
CH		 1745 __le32 sense_buf_phys_addr_lo; /*18h */
1746 __le32 sense_buf_phys_addr_hi; /*1Ch */
c4a3e0a5
BS		 1747
1748 u8 cdb[16]; /*20h */
1749 union megasas_sgl sgl; /*30h */
1750
1751} __attribute__ ((packed));
1752
1753struct megasas_dcmd_frame {
1754
1755 u8 cmd; /*00h */
1756 u8 reserved_0; /*01h */
1757 u8 cmd_status; /*02h */
1758 u8 reserved_1[4]; /*03h */
1759 u8 sge_count; /*07h */
1760
9ab9ed38
CH		 1761 __le32 context; /*08h */
1762 __le32 pad_0; /*0Ch */
c4a3e0a5 1763
9ab9ed38
CH		 1764 __le16 flags; /*10h */
1765 __le16 timeout; /*12h */
c4a3e0a5 1766
9ab9ed38
CH		 1767 __le32 data_xfer_len; /*14h */
1768 __le32 opcode; /*18h */
c4a3e0a5
BS		 1769
1770 union { /*1Ch */
1771 u8 b[12];
9ab9ed38
CH		 1772 __le16 s[6];
1773 __le32 w[3];
c4a3e0a5
BS		 1774 } mbox;
1775
1776 union megasas_sgl sgl; /*28h */
1777
1778} __attribute__ ((packed));
1779
1780struct megasas_abort_frame {
1781
1782 u8 cmd; /*00h */
1783 u8 reserved_0; /*01h */
1784 u8 cmd_status; /*02h */
1785
1786 u8 reserved_1; /*03h */
9ab9ed38 1787 __le32 reserved_2; /*04h */
c4a3e0a5 1788
9ab9ed38
CH		 1789 __le32 context; /*08h */
1790 __le32 pad_0; /*0Ch */
c4a3e0a5 1791
9ab9ed38
CH		 1792 __le16 flags; /*10h */
1793 __le16 reserved_3; /*12h */
1794 __le32 reserved_4; /*14h */
c4a3e0a5 1795
9ab9ed38
CH		 1796 __le32 abort_context; /*18h */
1797 __le32 pad_1; /*1Ch */
c4a3e0a5 1798
9ab9ed38
CH		 1799 __le32 abort_mfi_phys_addr_lo; /*20h */
1800 __le32 abort_mfi_phys_addr_hi; /*24h */
c4a3e0a5 1801
9ab9ed38 1802 __le32 reserved_5[6]; /*28h */
c4a3e0a5
BS		 1803
1804} __attribute__ ((packed));
1805
1806struct megasas_smp_frame {
1807
1808 u8 cmd; /*00h */
1809 u8 reserved_1; /*01h */
1810 u8 cmd_status; /*02h */
1811 u8 connection_status; /*03h */
1812
1813 u8 reserved_2[3]; /*04h */
1814 u8 sge_count; /*07h */
1815
9ab9ed38
CH		 1816 __le32 context; /*08h */
1817 __le32 pad_0; /*0Ch */
c4a3e0a5 1818
9ab9ed38
CH		 1819 __le16 flags; /*10h */
1820 __le16 timeout; /*12h */
c4a3e0a5 1821
9ab9ed38
CH		 1822 __le32 data_xfer_len; /*14h */
1823 __le64 sas_addr; /*18h */
c4a3e0a5
BS		 1824
1825 union {
1826 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1827 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1828 } sgl;
1829
1830} __attribute__ ((packed));
1831
1832struct megasas_stp_frame {
1833
1834 u8 cmd; /*00h */
1835 u8 reserved_1; /*01h */
1836 u8 cmd_status; /*02h */
1837 u8 reserved_2; /*03h */
1838
1839 u8 target_id; /*04h */
1840 u8 reserved_3[2]; /*05h */
1841 u8 sge_count; /*07h */
1842
9ab9ed38
CH		 1843 __le32 context; /*08h */
1844 __le32 pad_0; /*0Ch */
c4a3e0a5 1845
9ab9ed38
CH		 1846 __le16 flags; /*10h */
1847 __le16 timeout; /*12h */
c4a3e0a5 1848
9ab9ed38 1849 __le32 data_xfer_len; /*14h */
c4a3e0a5 1850
9ab9ed38
CH		 1851 __le16 fis[10]; /*18h */
1852 __le32 stp_flags;
c4a3e0a5
BS		 1853
1854 union {
1855 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1856 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1857 } sgl;
1858
1859} __attribute__ ((packed));
1860
1861union megasas_frame {
1862
1863 struct megasas_header hdr;
1864 struct megasas_init_frame init;
1865 struct megasas_io_frame io;
1866 struct megasas_pthru_frame pthru;
1867 struct megasas_dcmd_frame dcmd;
1868 struct megasas_abort_frame abort;
1869 struct megasas_smp_frame smp;
1870 struct megasas_stp_frame stp;
1871
1872 u8 raw_bytes[64];
1873};
1874
18365b13
SS		 1875/**
1876 * struct MR_PRIV_DEVICE - sdev private hostdata
1877 * @is_tm_capable: firmware managed tm_capable flag
1878 * @tm_busy: TM request is in progress
1879 */
1880struct MR_PRIV_DEVICE {
1881 bool is_tm_capable;
1882 bool tm_busy;
a48ba0ec 1883 atomic_t r1_ldio_hint;
15dd0381 1884 u8 interface_type;
18365b13 1885};
c4a3e0a5
BS		 1886struct megasas_cmd;
1887
1888union megasas_evt_class_locale {
1889
1890 struct {
be26374b 1891#ifndef __BIG_ENDIAN_BITFIELD
c4a3e0a5
BS		 1892 u16 locale;
1893 u8 reserved;
1894 s8 class;
be26374b
SS		 1895#else
1896 s8 class;
1897 u8 reserved;
1898 u16 locale;
1899#endif
c4a3e0a5
BS		 1900 } __attribute__ ((packed)) members;
1901
1902 u32 word;
1903
1904} __attribute__ ((packed));
1905
1906struct megasas_evt_log_info {
9ab9ed38
CH		 1907 __le32 newest_seq_num;
1908 __le32 oldest_seq_num;
1909 __le32 clear_seq_num;
1910 __le32 shutdown_seq_num;
1911 __le32 boot_seq_num;
c4a3e0a5
BS		 1912
1913} __attribute__ ((packed));
1914
1915struct megasas_progress {
1916
9ab9ed38
CH		 1917 __le16 progress;
1918 __le16 elapsed_seconds;
c4a3e0a5
BS		 1919
1920} __attribute__ ((packed));
1921
1922struct megasas_evtarg_ld {
1923
1924 u16 target_id;
1925 u8 ld_index;
1926 u8 reserved;
1927
1928} __attribute__ ((packed));
1929
1930struct megasas_evtarg_pd {
1931 u16 device_id;
1932 u8 encl_index;
1933 u8 slot_number;
1934
1935} __attribute__ ((packed));
1936
1937struct megasas_evt_detail {
1938
9ab9ed38
CH		 1939 __le32 seq_num;
1940 __le32 time_stamp;
1941 __le32 code;
c4a3e0a5
BS		 1942 union megasas_evt_class_locale cl;
1943 u8 arg_type;
1944 u8 reserved1[15];
1945
1946 union {
1947 struct {
1948 struct megasas_evtarg_pd pd;
1949 u8 cdb_length;
1950 u8 sense_length;
1951 u8 reserved[2];
1952 u8 cdb[16];
1953 u8 sense[64];
1954 } __attribute__ ((packed)) cdbSense;
1955
1956 struct megasas_evtarg_ld ld;
1957
1958 struct {
1959 struct megasas_evtarg_ld ld;
9ab9ed38 1960 __le64 count;
c4a3e0a5
BS		 1961 } __attribute__ ((packed)) ld_count;
1962
1963 struct {
9ab9ed38 1964 __le64 lba;
c4a3e0a5
BS		 1965 struct megasas_evtarg_ld ld;
1966 } __attribute__ ((packed)) ld_lba;
1967
1968 struct {
1969 struct megasas_evtarg_ld ld;
9ab9ed38
CH		 1970 __le32 prevOwner;
1971 __le32 newOwner;
c4a3e0a5
BS		 1972 } __attribute__ ((packed)) ld_owner;
1973
1974 struct {
1975 u64 ld_lba;
1976 u64 pd_lba;
1977 struct megasas_evtarg_ld ld;
1978 struct megasas_evtarg_pd pd;
1979 } __attribute__ ((packed)) ld_lba_pd_lba;
1980
1981 struct {
1982 struct megasas_evtarg_ld ld;
1983 struct megasas_progress prog;
1984 } __attribute__ ((packed)) ld_prog;
1985
1986 struct {
1987 struct megasas_evtarg_ld ld;
1988 u32 prev_state;
1989 u32 new_state;
1990 } __attribute__ ((packed)) ld_state;
1991
1992 struct {
1993 u64 strip;
1994 struct megasas_evtarg_ld ld;
1995 } __attribute__ ((packed)) ld_strip;
1996
1997 struct megasas_evtarg_pd pd;
1998
1999 struct {
2000 struct megasas_evtarg_pd pd;
2001 u32 err;
2002 } __attribute__ ((packed)) pd_err;
2003
2004 struct {
2005 u64 lba;
2006 struct megasas_evtarg_pd pd;
2007 } __attribute__ ((packed)) pd_lba;
2008
2009 struct {
2010 u64 lba;
2011 struct megasas_evtarg_pd pd;
2012 struct megasas_evtarg_ld ld;
2013 } __attribute__ ((packed)) pd_lba_ld;
2014
2015 struct {
2016 struct megasas_evtarg_pd pd;
2017 struct megasas_progress prog;
2018 } __attribute__ ((packed)) pd_prog;
2019
2020 struct {
2021 struct megasas_evtarg_pd pd;
2022 u32 prevState;
2023 u32 newState;
2024 } __attribute__ ((packed)) pd_state;
2025
2026 struct {
2027 u16 vendorId;
9ab9ed38 2028 __le16 deviceId;
c4a3e0a5
BS		 2029 u16 subVendorId;
2030 u16 subDeviceId;
2031 } __attribute__ ((packed)) pci;
2032
2033 u32 rate;
2034 char str[96];
2035
2036 struct {
2037 u32 rtc;
2038 u32 elapsedSeconds;
2039 } __attribute__ ((packed)) time;
2040
2041 struct {
2042 u32 ecar;
2043 u32 elog;
2044 char str[64];
2045 } __attribute__ ((packed)) ecc;
2046
2047 u8 b[96];
9ab9ed38
CH		 2048 __le16 s[48];
2049 __le32 w[24];
2050 __le64 d[12];
c4a3e0a5
BS		 2051 } args;
2052
2053 char description[128];
2054
2055} __attribute__ ((packed));
2056
7e8a75f4 2057struct megasas_aen_event {
c1d390d8 2058 struct delayed_work hotplug_work;
7e8a75f4
YB		 2059 struct megasas_instance *instance;
2060};
2061
c8e858fe 2062struct megasas_irq_context {
2063 struct megasas_instance *instance;
2064 u32 MSIxIndex;
2065};
2066
5765c5b8
SS		 2067struct MR_DRV_SYSTEM_INFO {
2068 u8 infoVersion;
2069 u8 systemIdLength;
2070 u16 reserved0;
2071 u8 systemId[64];
2072 u8 reserved[1980];
2073};
2074
2216c305 2075enum MR_PD_TYPE {
15dd0381
S		 2076 UNKNOWN_DRIVE = 0,
2077 PARALLEL_SCSI = 1,
2078 SAS_PD = 2,
2079 SATA_PD = 3,
2080 FC_PD = 4,
2081 NVME_PD = 5,
2216c305
SS		 2082};
2083
2084/* JBOD Queue depth definitions */
2085#define MEGASAS_SATA_QD 32
2086#define MEGASAS_SAS_QD 64
2087#define MEGASAS_DEFAULT_PD_QD 64
15dd0381
S		 2088#define MEGASAS_NVME_QD 32
2089
2090#define MR_DEFAULT_NVME_PAGE_SIZE 4096
2091#define MR_DEFAULT_NVME_PAGE_SHIFT 12
2092#define MR_DEFAULT_NVME_MDTS_KB 128
2093#define MR_NVME_PAGE_SIZE_MASK 0x000000FF
2216c305 2094
c4a3e0a5
BS		 2095struct megasas_instance {
2096
9ab9ed38 2097 __le32 *producer;
c4a3e0a5 2098 dma_addr_t producer_h;
9ab9ed38 2099 __le32 *consumer;
c4a3e0a5 2100 dma_addr_t consumer_h;
5765c5b8
SS		 2101 struct MR_DRV_SYSTEM_INFO *system_info_buf;
2102 dma_addr_t system_info_h;
229fe47c 2103 struct MR_LD_VF_AFFILIATION *vf_affiliation;
2104 dma_addr_t vf_affiliation_h;
2105 struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
2106 dma_addr_t vf_affiliation_111_h;
2107 struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
2108 dma_addr_t hb_host_mem_h;
2216c305
SS		 2109 struct MR_PD_INFO *pd_info;
2110 dma_addr_t pd_info_h;
96188a89
S		 2111 struct MR_TARGET_PROPERTIES *tgt_prop;
2112 dma_addr_t tgt_prop_h;
c4a3e0a5 2113
9ab9ed38 2114 __le32 *reply_queue;
c4a3e0a5
BS		 2115 dma_addr_t reply_queue_h;
2116
fc62b3fc
SS		 2117 u32 *crash_dump_buf;
2118 dma_addr_t crash_dump_h;
2119 void *crash_buf[MAX_CRASH_DUMP_SIZE];
2120 u32 crash_buf_pages;
2121 unsigned int fw_crash_buffer_size;
2122 unsigned int fw_crash_state;
2123 unsigned int fw_crash_buffer_offset;
2124 u32 drv_buf_index;
2125 u32 drv_buf_alloc;
2126 u32 crash_dump_fw_support;
2127 u32 crash_dump_drv_support;
2128 u32 crash_dump_app_support;
7497cde8 2129 u32 secure_jbod_support;
ede7c3ce 2130 u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */
3761cb4c 2131 bool use_seqnum_jbod_fp; /* Added for PD sequence */
fc62b3fc
SS		 2132 spinlock_t crashdump_lock;
2133
c4a3e0a5 2134 struct megasas_register_set __iomem *reg_set;
8a232bb3 2135 u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
81e403ce 2136 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
999ece0a 2137 struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD];
7497cde8 2138 u8 ld_ids[MEGASAS_MAX_LD_IDS];
c4a3e0a5 2139 s8 init_id;
c4a3e0a5
BS		 2140
2141 u16 max_num_sge;
2142 u16 max_fw_cmds;
69c337c0 2143 u16 max_mpt_cmds;
9c915a8c 2144 u16 max_mfi_cmds;
ae09a6c1 2145 u16 max_scsi_cmds;
308ec459
SS		 2146 u16 ldio_threshold;
2147 u16 cur_can_queue;
c4a3e0a5 2148 u32 max_sectors_per_req;
7e8a75f4 2149 struct megasas_aen_event *ev;
c4a3e0a5
BS		 2150
2151 struct megasas_cmd **cmd_list;
2152 struct list_head cmd_pool;
39a98554 2153 /* used to sync fire the cmd to fw */
90dc9d98 2154 spinlock_t mfi_pool_lock;
39a98554 2155 /* used to sync fire the cmd to fw */
2156 spinlock_t hba_lock;
7343eb65 2157 /* used to synch producer, consumer ptrs in dpc */
fdd84e25 2158 spinlock_t stream_lock;
7343eb65 2159 spinlock_t completion_lock;
c4a3e0a5
BS		 2160 struct dma_pool *frame_dma_pool;
2161 struct dma_pool *sense_dma_pool;
2162
2163 struct megasas_evt_detail *evt_detail;
2164 dma_addr_t evt_detail_h;
2165 struct megasas_cmd *aen_cmd;
2216c305 2166 struct mutex hba_mutex;
c4a3e0a5
BS		 2167 struct semaphore ioctl_sem;
2168
2169 struct Scsi_Host *host;
2170
2171 wait_queue_head_t int_cmd_wait_q;
2172 wait_queue_head_t abort_cmd_wait_q;
2173
2174 struct pci_dev *pdev;
2175 u32 unique_id;
39a98554 2176 u32 fw_support_ieee;
c4a3e0a5 2177
e4a082c7 2178 atomic_t fw_outstanding;
308ec459 2179 atomic_t ldio_outstanding;
39a98554 2180 atomic_t fw_reset_no_pci_access;
33203bc4
S		 2181 atomic_t ieee_sgl;
2182 atomic_t prp_sgl;
2183 atomic_t sge_holes_type1;
2184 atomic_t sge_holes_type2;
2185 atomic_t sge_holes_type3;
1341c939
SP		 2186
2187 struct megasas_instance_template *instancet;
5d018ad0 2188 struct tasklet_struct isr_tasklet;
39a98554 2189 struct work_struct work_init;
fc62b3fc 2190 struct work_struct crash_init;
05e9ebbe
SP		 2191
2192 u8 flag;
c3518837 2193 u8 unload;
f4c9a131 2194 u8 flag_ieee;
39a98554 2195 u8 issuepend_done;
2196 u8 disableOnlineCtrlReset;
bc93d425 2197 u8 UnevenSpanSupport;
51087a86
SS		 2198
2199 u8 supportmax256vd;
30845586 2200 u8 pd_list_not_supported;
51087a86
SS		 2201 u16 fw_supported_vd_count;
2202 u16 fw_supported_pd_count;
2203
2204 u16 drv_supported_vd_count;
2205 u16 drv_supported_pd_count;
2206
8a01a41d 2207 atomic_t adprecovery;
05e9ebbe 2208 unsigned long last_time;
39a98554 2209 u32 mfiStatus;
2210 u32 last_seq_num;
ad84db2e 2211
39a98554 2212 struct list_head internal_reset_pending_q;
80d9da98 2213
25985edc 2214 /* Ptr to hba specific information */
9c915a8c 2215 void *ctrl_context;
51087a86
SS		 2216 u32 ctrl_context_pages;
2217 struct megasas_ctrl_info *ctrl_info;
c8e858fe 2218 unsigned int msix_vectors;
c8e858fe 2219 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
9c915a8c 2220 u64 map_id;
3761cb4c 2221 u64 pd_seq_map_id;
9c915a8c 2222 struct megasas_cmd *map_update_cmd;
3761cb4c 2223 struct megasas_cmd *jbod_seq_cmd;
b6d5d880 2224 unsigned long bar;
9c915a8c 2225 long reset_flags;
2226 struct mutex reset_mutex;
229fe47c 2227 struct timer_list sriov_heartbeat_timer;
2228 char skip_heartbeat_timer_del;
2229 u8 requestorId;
229fe47c 2230 char PlasmaFW111;
8f67c8c5
SS		 2231 char clusterId[MEGASAS_CLUSTER_ID_SIZE];
2232 u8 peerIsPresent;
2233 u8 passive;
ae09a6c1 2234 u16 throttlequeuedepth;
d46a3ad6 2235 u8 mask_interrupts;
bd5f9484 2236 u16 max_chain_frame_sz;
404a8a1a 2237 u8 is_imr;
179ac142 2238 u8 is_rdpq;
5765c5b8 2239 bool dev_handle;
d0fc91d6 2240 bool fw_sync_cache_support;
45f4f2eb 2241 bool is_ventura;
2493c67e 2242 bool msix_combined;
d889344e 2243 u16 max_raid_mapsize;
a48ba0ec
S		 2244 /* preffered count to send as LDIO irrspective of FP capable.*/
2245 u8 r1_ldio_hint_default;
15dd0381 2246 u32 nvme_page_size;
39a98554 2247};
229fe47c 2248struct MR_LD_VF_MAP {
2249 u32 size;
2250 union MR_LD_REF ref;
2251 u8 ldVfCount;
2252 u8 reserved[6];
2253 u8 policy[1];
2254};
2255
2256struct MR_LD_VF_AFFILIATION {
2257 u32 size;
2258 u8 ldCount;
2259 u8 vfCount;
2260 u8 thisVf;
2261 u8 reserved[9];
2262 struct MR_LD_VF_MAP map[1];
2263};
2264
2265/* Plasma 1.11 FW backward compatibility structures */
2266#define IOV_111_OFFSET 0x7CE
2267#define MAX_VIRTUAL_FUNCTIONS 8
4cbfea88 2268#define MR_LD_ACCESS_HIDDEN 15
229fe47c 2269
2270struct IOV_111 {
2271 u8 maxVFsSupported;
2272 u8 numVFsEnabled;
2273 u8 requestorId;
2274 u8 reserved[5];
2275};
2276
2277struct MR_LD_VF_MAP_111 {
2278 u8 targetId;
2279 u8 reserved[3];
2280 u8 policy[MAX_VIRTUAL_FUNCTIONS];
2281};
2282
2283struct MR_LD_VF_AFFILIATION_111 {
2284 u8 vdCount;
2285 u8 vfCount;
2286 u8 thisVf;
2287 u8 reserved[5];
2288 struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
2289};
2290
2291struct MR_CTRL_HB_HOST_MEM {
2292 struct {
2293 u32 fwCounter; /* Firmware heart beat counter */
2294 struct {
2295 u32 debugmode:1; /* 1=Firmware is in debug mode.
2296 Heart beat will not be updated. */
2297 u32 reserved:31;
2298 } debug;
2299 u32 reserved_fw[6];
2300 u32 driverCounter; /* Driver heart beat counter. 0x20 */
2301 u32 reserved_driver[7];
2302 } HB;
2303 u8 pad[0x400-0x40];
2304};
39a98554 2305
2306enum {
2307 MEGASAS_HBA_OPERATIONAL = 0,
2308 MEGASAS_ADPRESET_SM_INFAULT = 1,
2309 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
2310 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
2311 MEGASAS_HW_CRITICAL_ERROR = 4,
229fe47c 2312 MEGASAS_ADPRESET_SM_POLLING = 5,
39a98554 2313 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
c4a3e0a5
BS		 2314};
2315
0c79e681
YB		 2316struct megasas_instance_template {
2317 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
2318 u32, struct megasas_register_set __iomem *);
2319
d46a3ad6
SS		 2320 void (*enable_intr)(struct megasas_instance *);
2321 void (*disable_intr)(struct megasas_instance *);
0c79e681
YB		 2322
2323 int (*clear_intr)(struct megasas_register_set __iomem *);
2324
2325 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
39a98554 2326 int (*adp_reset)(struct megasas_instance *, \
2327 struct megasas_register_set __iomem *);
2328 int (*check_reset)(struct megasas_instance *, \
2329 struct megasas_register_set __iomem *);
cd50ba8e 2330 irqreturn_t (*service_isr)(int irq, void *devp);
2331 void (*tasklet)(unsigned long);
2332 u32 (*init_adapter)(struct megasas_instance *);
2333 u32 (*build_and_issue_cmd) (struct megasas_instance *,
2334 struct scsi_cmnd *);
f4fc2093 2335 void (*issue_dcmd)(struct megasas_instance *instance,
cd50ba8e 2336 struct megasas_cmd *cmd);
0c79e681
YB		 2337};
2338
3cabd162
S		 2339#define MEGASAS_IS_LOGICAL(sdev) \
2340 ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1)
c4a3e0a5 2341
4a5c814d
SS		 2342#define MEGASAS_DEV_INDEX(scp) \
2343 (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
2344 scp->device->id)
2345
2346#define MEGASAS_PD_INDEX(scp) \
2347 ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \
2348 scp->device->id)
c4a3e0a5
BS		 2349
2350struct megasas_cmd {
2351
2352 union megasas_frame *frame;
2353 dma_addr_t frame_phys_addr;
2354 u8 *sense;
2355 dma_addr_t sense_phys_addr;
2356
2357 u32 index;
2358 u8 sync_cmd;
2be2a988 2359 u8 cmd_status_drv;
39a98554 2360 u8 abort_aen;
2361 u8 retry_for_fw_reset;
2362
c4a3e0a5
BS		 2363
2364 struct list_head list;
2365 struct scsi_cmnd *scmd;
4026e9aa 2366 u8 flags;
90dc9d98 2367
c4a3e0a5 2368 struct megasas_instance *instance;
9c915a8c 2369 union {
2370 struct {
2371 u16 smid;
2372 u16 resvd;
2373 } context;
2374 u32 frame_count;
2375 };
c4a3e0a5
BS		 2376};
2377
2378#define MAX_MGMT_ADAPTERS 1024
2379#define MAX_IOCTL_SGE 16
2380
2381struct megasas_iocpacket {
2382
2383 u16 host_no;
2384 u16 __pad1;
2385 u32 sgl_off;
2386 u32 sge_count;
2387 u32 sense_off;
2388 u32 sense_len;
2389 union {
2390 u8 raw[128];
2391 struct megasas_header hdr;
2392 } frame;
2393
2394 struct iovec sgl[MAX_IOCTL_SGE];
2395
2396} __attribute__ ((packed));
2397
2398struct megasas_aen {
2399 u16 host_no;
2400 u16 __pad1;
2401 u32 seq_num;
2402 u32 class_locale_word;
2403} __attribute__ ((packed));
2404
2405#ifdef CONFIG_COMPAT
2406struct compat_megasas_iocpacket {
2407 u16 host_no;
2408 u16 __pad1;
2409 u32 sgl_off;
2410 u32 sge_count;
2411 u32 sense_off;
2412 u32 sense_len;
2413 union {
2414 u8 raw[128];
2415 struct megasas_header hdr;
2416 } frame;
2417 struct compat_iovec sgl[MAX_IOCTL_SGE];
2418} __attribute__ ((packed));
2419
0e98936c 2420#define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
c4a3e0a5
BS		 2421#endif
2422
cb59aa6a 2423#define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
c4a3e0a5
BS		 2424#define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
2425
2426struct megasas_mgmt_info {
2427
2428 u16 count;
2429 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
2430 int max_index;
2431};
2432
6d40afbc
SS		 2433enum MEGASAS_OCR_CAUSE {
2434 FW_FAULT_OCR = 0,
2435 SCSIIO_TIMEOUT_OCR = 1,
2436 MFI_IO_TIMEOUT_OCR = 2,
2437};
2438
2439enum DCMD_RETURN_STATUS {
2440 DCMD_SUCCESS = 0,
2441 DCMD_TIMEOUT = 1,
2442 DCMD_FAILED = 2,
2443 DCMD_NOT_FIRED = 3,
2444};
2445
21c9e160 2446u8
2447MR_BuildRaidContext(struct megasas_instance *instance,
2448 struct IO_REQUEST_INFO *io_info,
2449 struct RAID_CONTEXT *pRAID_Context,
51087a86
SS		 2450 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
2451u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
2452struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2453u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
2454u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
9ab9ed38 2455__le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
51087a86
SS		 2456u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2457
9ab9ed38 2458__le16 get_updated_dev_handle(struct megasas_instance *instance,
33203bc4
S		 2459 struct LD_LOAD_BALANCE_INFO *lbInfo,
2460 struct IO_REQUEST_INFO *in_info,
2461 struct MR_DRV_RAID_MAP_ALL *drv_map);
51087a86
SS		 2462void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
2463 struct LD_LOAD_BALANCE_INFO *lbInfo);
d009b576 2464int megasas_get_ctrl_info(struct megasas_instance *instance);
3761cb4c 2465/* PD sequence */
2466int
2467megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend);
15dd0381 2468void megasas_set_dynamic_target_properties(struct scsi_device *sdev);
fc62b3fc 2469int megasas_set_crash_dump_params(struct megasas_instance *instance,
51087a86 2470 u8 crash_buf_state);
fc62b3fc
SS		 2471void megasas_free_host_crash_buffer(struct megasas_instance *instance);
2472void megasas_fusion_crash_dump_wq(struct work_struct *work);
51087a86 2473
90dc9d98
SS		 2474void megasas_return_cmd_fusion(struct megasas_instance *instance,
2475 struct megasas_cmd_fusion *cmd);
2476int megasas_issue_blocked_cmd(struct megasas_instance *instance,
2477 struct megasas_cmd *cmd, int timeout);
2478void __megasas_return_cmd(struct megasas_instance *instance,
2479 struct megasas_cmd *cmd);
2480
2481void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
2482 struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
7497cde8 2483int megasas_cmd_type(struct scsi_cmnd *cmd);
3761cb4c 2484void megasas_setup_jbod_map(struct megasas_instance *instance);
90dc9d98 2485
18365b13
SS		 2486void megasas_update_sdev_properties(struct scsi_device *sdev);
2487int megasas_reset_fusion(struct Scsi_Host *shost, int reason);
2488int megasas_task_abort_fusion(struct scsi_cmnd *scmd);
2489int megasas_reset_target_fusion(struct scsi_cmnd *scmd);
33203bc4 2490u32 mega_mod64(u64 dividend, u32 divisor);
c4a3e0a5 2491#endif /*LSI_MEGARAID_SAS_H */
Linux 6.x block layer and io_uring tree(s)