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c4a3e0a5 | 1 | /* |
3f1530c1 | 2 | * Linux MegaRAID driver for SAS based RAID controllers |
c4a3e0a5 | 3 | * |
ae59057b | 4 | * Copyright (c) 2003-2012 LSI Corporation. |
c4a3e0a5 | 5 | * |
3f1530c1 | 6 | * This program is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
c4a3e0a5 | 10 | * |
3f1530c1 | 11 | * This program is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
c4a3e0a5 | 15 | * |
3f1530c1 | 16 | * You should have received a copy of the GNU General Public License |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | * | |
20 | * FILE: megaraid_sas.h | |
21 | * | |
22 | * Authors: LSI Corporation | |
23 | * | |
24 | * Send feedback to: <megaraidlinux@lsi.com> | |
25 | * | |
26 | * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035 | |
27 | * ATTN: Linuxraid | |
c4a3e0a5 BS |
28 | */ |
29 | ||
30 | #ifndef LSI_MEGARAID_SAS_H | |
31 | #define LSI_MEGARAID_SAS_H | |
32 | ||
a69b74d3 | 33 | /* |
c4a3e0a5 BS |
34 | * MegaRAID SAS Driver meta data |
35 | */ | |
2b4857c3 | 36 | #define MEGASAS_VERSION "06.700.06.00-rc1" |
37 | #define MEGASAS_RELDATE "Aug. 31, 2013" | |
38 | #define MEGASAS_EXT_VERSION "Sat. Aug. 31 17:00:00 PDT 2013" | |
0e98936c SP |
39 | |
40 | /* | |
41 | * Device IDs | |
42 | */ | |
43 | #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 | |
af7a5647 | 44 | #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C |
0e98936c | 45 | #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 |
6610a6b3 YB |
46 | #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 |
47 | #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 | |
87911122 YB |
48 | #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 |
49 | #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 | |
9c915a8c | 50 | #define PCI_DEVICE_ID_LSI_FUSION 0x005b |
36807e67 | 51 | #define PCI_DEVICE_ID_LSI_INVADER 0x005d |
21d3c710 | 52 | #define PCI_DEVICE_ID_LSI_FURY 0x005f |
0e98936c | 53 | |
39b72c3c SS |
54 | /* |
55 | * Intel HBA SSDIDs | |
56 | */ | |
57 | #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360 | |
58 | #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362 | |
59 | #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380 | |
60 | #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381 | |
61 | #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341 | |
62 | #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343 | |
63 | ||
64 | /* | |
65 | * Intel HBA branding | |
66 | */ | |
67 | #define MEGARAID_INTEL_RS3DC080_BRANDING \ | |
68 | "Intel(R) RAID Controller RS3DC080" | |
69 | #define MEGARAID_INTEL_RS3DC040_BRANDING \ | |
70 | "Intel(R) RAID Controller RS3DC040" | |
71 | #define MEGARAID_INTEL_RS3SC008_BRANDING \ | |
72 | "Intel(R) RAID Controller RS3SC008" | |
73 | #define MEGARAID_INTEL_RS3MC044_BRANDING \ | |
74 | "Intel(R) RAID Controller RS3MC044" | |
75 | #define MEGARAID_INTEL_RS3WC080_BRANDING \ | |
76 | "Intel(R) RAID Controller RS3WC080" | |
77 | #define MEGARAID_INTEL_RS3WC040_BRANDING \ | |
78 | "Intel(R) RAID Controller RS3WC040" | |
79 | ||
c4a3e0a5 BS |
80 | /* |
81 | * ===================================== | |
82 | * MegaRAID SAS MFI firmware definitions | |
83 | * ===================================== | |
84 | */ | |
85 | ||
86 | /* | |
87 | * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for | |
88 | * protocol between the software and firmware. Commands are issued using | |
89 | * "message frames" | |
90 | */ | |
91 | ||
a69b74d3 | 92 | /* |
c4a3e0a5 BS |
93 | * FW posts its state in upper 4 bits of outbound_msg_0 register |
94 | */ | |
95 | #define MFI_STATE_MASK 0xF0000000 | |
96 | #define MFI_STATE_UNDEFINED 0x00000000 | |
97 | #define MFI_STATE_BB_INIT 0x10000000 | |
98 | #define MFI_STATE_FW_INIT 0x40000000 | |
99 | #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 | |
100 | #define MFI_STATE_FW_INIT_2 0x70000000 | |
101 | #define MFI_STATE_DEVICE_SCAN 0x80000000 | |
e3bbff9f | 102 | #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 |
c4a3e0a5 BS |
103 | #define MFI_STATE_FLUSH_CACHE 0xA0000000 |
104 | #define MFI_STATE_READY 0xB0000000 | |
105 | #define MFI_STATE_OPERATIONAL 0xC0000000 | |
106 | #define MFI_STATE_FAULT 0xF0000000 | |
7e70e733 | 107 | #define MFI_RESET_REQUIRED 0x00000001 |
108 | #define MFI_RESET_ADAPTER 0x00000002 | |
c4a3e0a5 BS |
109 | #define MEGAMFI_FRAME_SIZE 64 |
110 | ||
a69b74d3 | 111 | /* |
c4a3e0a5 BS |
112 | * During FW init, clear pending cmds & reset state using inbound_msg_0 |
113 | * | |
114 | * ABORT : Abort all pending cmds | |
115 | * READY : Move from OPERATIONAL to READY state; discard queue info | |
116 | * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) | |
117 | * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver | |
e3bbff9f SP |
118 | * HOTPLUG : Resume from Hotplug |
119 | * MFI_STOP_ADP : Send signal to FW to stop processing | |
c4a3e0a5 | 120 | */ |
39a98554 | 121 | #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */ |
122 | #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */ | |
123 | #define DIAG_WRITE_ENABLE (0x00000080) | |
124 | #define DIAG_RESET_ADAPTER (0x00000004) | |
125 | ||
126 | #define MFI_ADP_RESET 0x00000040 | |
e3bbff9f | 127 | #define MFI_INIT_ABORT 0x00000001 |
c4a3e0a5 BS |
128 | #define MFI_INIT_READY 0x00000002 |
129 | #define MFI_INIT_MFIMODE 0x00000004 | |
130 | #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 | |
e3bbff9f SP |
131 | #define MFI_INIT_HOTPLUG 0x00000010 |
132 | #define MFI_STOP_ADP 0x00000020 | |
133 | #define MFI_RESET_FLAGS MFI_INIT_READY| \ | |
134 | MFI_INIT_MFIMODE| \ | |
135 | MFI_INIT_ABORT | |
c4a3e0a5 | 136 | |
a69b74d3 | 137 | /* |
c4a3e0a5 BS |
138 | * MFI frame flags |
139 | */ | |
140 | #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 | |
141 | #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 | |
142 | #define MFI_FRAME_SGL32 0x0000 | |
143 | #define MFI_FRAME_SGL64 0x0002 | |
144 | #define MFI_FRAME_SENSE32 0x0000 | |
145 | #define MFI_FRAME_SENSE64 0x0004 | |
146 | #define MFI_FRAME_DIR_NONE 0x0000 | |
147 | #define MFI_FRAME_DIR_WRITE 0x0008 | |
148 | #define MFI_FRAME_DIR_READ 0x0010 | |
149 | #define MFI_FRAME_DIR_BOTH 0x0018 | |
f4c9a131 | 150 | #define MFI_FRAME_IEEE 0x0020 |
c4a3e0a5 | 151 | |
a69b74d3 | 152 | /* |
c4a3e0a5 BS |
153 | * Definition for cmd_status |
154 | */ | |
155 | #define MFI_CMD_STATUS_POLL_MODE 0xFF | |
156 | ||
a69b74d3 | 157 | /* |
c4a3e0a5 BS |
158 | * MFI command opcodes |
159 | */ | |
160 | #define MFI_CMD_INIT 0x00 | |
161 | #define MFI_CMD_LD_READ 0x01 | |
162 | #define MFI_CMD_LD_WRITE 0x02 | |
163 | #define MFI_CMD_LD_SCSI_IO 0x03 | |
164 | #define MFI_CMD_PD_SCSI_IO 0x04 | |
165 | #define MFI_CMD_DCMD 0x05 | |
166 | #define MFI_CMD_ABORT 0x06 | |
167 | #define MFI_CMD_SMP 0x07 | |
168 | #define MFI_CMD_STP 0x08 | |
e5f93a36 | 169 | #define MFI_CMD_INVALID 0xff |
c4a3e0a5 BS |
170 | |
171 | #define MR_DCMD_CTRL_GET_INFO 0x01010000 | |
bdc6fb8d | 172 | #define MR_DCMD_LD_GET_LIST 0x03010000 |
21c9e160 | 173 | #define MR_DCMD_LD_LIST_QUERY 0x03010100 |
c4a3e0a5 BS |
174 | |
175 | #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 | |
176 | #define MR_FLUSH_CTRL_CACHE 0x01 | |
177 | #define MR_FLUSH_DISK_CACHE 0x02 | |
178 | ||
179 | #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 | |
31ea7088 | 180 | #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 |
c4a3e0a5 BS |
181 | #define MR_ENABLE_DRIVE_SPINDOWN 0x01 |
182 | ||
183 | #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 | |
184 | #define MR_DCMD_CTRL_EVENT_GET 0x01040300 | |
185 | #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 | |
186 | #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 | |
187 | ||
188 | #define MR_DCMD_CLUSTER 0x08000000 | |
189 | #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 | |
190 | #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 | |
81e403ce | 191 | #define MR_DCMD_PD_LIST_QUERY 0x02010100 |
c4a3e0a5 | 192 | |
bc93d425 SS |
193 | /* |
194 | * Global functions | |
195 | */ | |
196 | extern u8 MR_ValidateMapInfo(struct megasas_instance *instance); | |
197 | ||
198 | ||
a69b74d3 | 199 | /* |
c4a3e0a5 BS |
200 | * MFI command completion codes |
201 | */ | |
202 | enum MFI_STAT { | |
203 | MFI_STAT_OK = 0x00, | |
204 | MFI_STAT_INVALID_CMD = 0x01, | |
205 | MFI_STAT_INVALID_DCMD = 0x02, | |
206 | MFI_STAT_INVALID_PARAMETER = 0x03, | |
207 | MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, | |
208 | MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, | |
209 | MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, | |
210 | MFI_STAT_APP_IN_USE = 0x07, | |
211 | MFI_STAT_APP_NOT_INITIALIZED = 0x08, | |
212 | MFI_STAT_ARRAY_INDEX_INVALID = 0x09, | |
213 | MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, | |
214 | MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, | |
215 | MFI_STAT_DEVICE_NOT_FOUND = 0x0c, | |
216 | MFI_STAT_DRIVE_TOO_SMALL = 0x0d, | |
217 | MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, | |
218 | MFI_STAT_FLASH_BUSY = 0x0f, | |
219 | MFI_STAT_FLASH_ERROR = 0x10, | |
220 | MFI_STAT_FLASH_IMAGE_BAD = 0x11, | |
221 | MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, | |
222 | MFI_STAT_FLASH_NOT_OPEN = 0x13, | |
223 | MFI_STAT_FLASH_NOT_STARTED = 0x14, | |
224 | MFI_STAT_FLUSH_FAILED = 0x15, | |
225 | MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, | |
226 | MFI_STAT_LD_CC_IN_PROGRESS = 0x17, | |
227 | MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, | |
228 | MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, | |
229 | MFI_STAT_LD_MAX_CONFIGURED = 0x1a, | |
230 | MFI_STAT_LD_NOT_OPTIMAL = 0x1b, | |
231 | MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, | |
232 | MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, | |
233 | MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, | |
234 | MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, | |
235 | MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, | |
236 | MFI_STAT_MFC_HW_ERROR = 0x21, | |
237 | MFI_STAT_NO_HW_PRESENT = 0x22, | |
238 | MFI_STAT_NOT_FOUND = 0x23, | |
239 | MFI_STAT_NOT_IN_ENCL = 0x24, | |
240 | MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, | |
241 | MFI_STAT_PD_TYPE_WRONG = 0x26, | |
242 | MFI_STAT_PR_DISABLED = 0x27, | |
243 | MFI_STAT_ROW_INDEX_INVALID = 0x28, | |
244 | MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, | |
245 | MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, | |
246 | MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, | |
247 | MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, | |
248 | MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, | |
249 | MFI_STAT_SCSI_IO_FAILED = 0x2e, | |
250 | MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, | |
251 | MFI_STAT_SHUTDOWN_FAILED = 0x30, | |
252 | MFI_STAT_TIME_NOT_SET = 0x31, | |
253 | MFI_STAT_WRONG_STATE = 0x32, | |
254 | MFI_STAT_LD_OFFLINE = 0x33, | |
255 | MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, | |
256 | MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, | |
257 | MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, | |
258 | MFI_STAT_I2C_ERRORS_DETECTED = 0x37, | |
259 | MFI_STAT_PCI_ERRORS_DETECTED = 0x38, | |
36807e67 | 260 | MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, |
c4a3e0a5 BS |
261 | |
262 | MFI_STAT_INVALID_STATUS = 0xFF | |
263 | }; | |
264 | ||
265 | /* | |
266 | * Number of mailbox bytes in DCMD message frame | |
267 | */ | |
268 | #define MFI_MBOX_SIZE 12 | |
269 | ||
270 | enum MR_EVT_CLASS { | |
271 | ||
272 | MR_EVT_CLASS_DEBUG = -2, | |
273 | MR_EVT_CLASS_PROGRESS = -1, | |
274 | MR_EVT_CLASS_INFO = 0, | |
275 | MR_EVT_CLASS_WARNING = 1, | |
276 | MR_EVT_CLASS_CRITICAL = 2, | |
277 | MR_EVT_CLASS_FATAL = 3, | |
278 | MR_EVT_CLASS_DEAD = 4, | |
279 | ||
280 | }; | |
281 | ||
282 | enum MR_EVT_LOCALE { | |
283 | ||
284 | MR_EVT_LOCALE_LD = 0x0001, | |
285 | MR_EVT_LOCALE_PD = 0x0002, | |
286 | MR_EVT_LOCALE_ENCL = 0x0004, | |
287 | MR_EVT_LOCALE_BBU = 0x0008, | |
288 | MR_EVT_LOCALE_SAS = 0x0010, | |
289 | MR_EVT_LOCALE_CTRL = 0x0020, | |
290 | MR_EVT_LOCALE_CONFIG = 0x0040, | |
291 | MR_EVT_LOCALE_CLUSTER = 0x0080, | |
292 | MR_EVT_LOCALE_ALL = 0xffff, | |
293 | ||
294 | }; | |
295 | ||
296 | enum MR_EVT_ARGS { | |
297 | ||
298 | MR_EVT_ARGS_NONE, | |
299 | MR_EVT_ARGS_CDB_SENSE, | |
300 | MR_EVT_ARGS_LD, | |
301 | MR_EVT_ARGS_LD_COUNT, | |
302 | MR_EVT_ARGS_LD_LBA, | |
303 | MR_EVT_ARGS_LD_OWNER, | |
304 | MR_EVT_ARGS_LD_LBA_PD_LBA, | |
305 | MR_EVT_ARGS_LD_PROG, | |
306 | MR_EVT_ARGS_LD_STATE, | |
307 | MR_EVT_ARGS_LD_STRIP, | |
308 | MR_EVT_ARGS_PD, | |
309 | MR_EVT_ARGS_PD_ERR, | |
310 | MR_EVT_ARGS_PD_LBA, | |
311 | MR_EVT_ARGS_PD_LBA_LD, | |
312 | MR_EVT_ARGS_PD_PROG, | |
313 | MR_EVT_ARGS_PD_STATE, | |
314 | MR_EVT_ARGS_PCI, | |
315 | MR_EVT_ARGS_RATE, | |
316 | MR_EVT_ARGS_STR, | |
317 | MR_EVT_ARGS_TIME, | |
318 | MR_EVT_ARGS_ECC, | |
81e403ce YB |
319 | MR_EVT_ARGS_LD_PROP, |
320 | MR_EVT_ARGS_PD_SPARE, | |
321 | MR_EVT_ARGS_PD_INDEX, | |
322 | MR_EVT_ARGS_DIAG_PASS, | |
323 | MR_EVT_ARGS_DIAG_FAIL, | |
324 | MR_EVT_ARGS_PD_LBA_LBA, | |
325 | MR_EVT_ARGS_PORT_PHY, | |
326 | MR_EVT_ARGS_PD_MISSING, | |
327 | MR_EVT_ARGS_PD_ADDRESS, | |
328 | MR_EVT_ARGS_BITMAP, | |
329 | MR_EVT_ARGS_CONNECTOR, | |
330 | MR_EVT_ARGS_PD_PD, | |
331 | MR_EVT_ARGS_PD_FRU, | |
332 | MR_EVT_ARGS_PD_PATHINFO, | |
333 | MR_EVT_ARGS_PD_POWER_STATE, | |
334 | MR_EVT_ARGS_GENERIC, | |
335 | }; | |
c4a3e0a5 | 336 | |
81e403ce YB |
337 | /* |
338 | * define constants for device list query options | |
339 | */ | |
340 | enum MR_PD_QUERY_TYPE { | |
341 | MR_PD_QUERY_TYPE_ALL = 0, | |
342 | MR_PD_QUERY_TYPE_STATE = 1, | |
343 | MR_PD_QUERY_TYPE_POWER_STATE = 2, | |
344 | MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, | |
345 | MR_PD_QUERY_TYPE_SPEED = 4, | |
346 | MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, | |
c4a3e0a5 BS |
347 | }; |
348 | ||
21c9e160 | 349 | enum MR_LD_QUERY_TYPE { |
350 | MR_LD_QUERY_TYPE_ALL = 0, | |
351 | MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1, | |
352 | MR_LD_QUERY_TYPE_USED_TGT_IDS = 2, | |
353 | MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3, | |
354 | MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4, | |
355 | }; | |
356 | ||
357 | ||
7e8a75f4 YB |
358 | #define MR_EVT_CFG_CLEARED 0x0004 |
359 | #define MR_EVT_LD_STATE_CHANGE 0x0051 | |
360 | #define MR_EVT_PD_INSERTED 0x005b | |
361 | #define MR_EVT_PD_REMOVED 0x0070 | |
362 | #define MR_EVT_LD_CREATED 0x008a | |
363 | #define MR_EVT_LD_DELETED 0x008b | |
364 | #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db | |
365 | #define MR_EVT_LD_OFFLINE 0x00fc | |
366 | #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 | |
367 | #define MAX_LOGICAL_DRIVES 64 | |
368 | ||
81e403ce YB |
369 | enum MR_PD_STATE { |
370 | MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, | |
371 | MR_PD_STATE_UNCONFIGURED_BAD = 0x01, | |
372 | MR_PD_STATE_HOT_SPARE = 0x02, | |
373 | MR_PD_STATE_OFFLINE = 0x10, | |
374 | MR_PD_STATE_FAILED = 0x11, | |
375 | MR_PD_STATE_REBUILD = 0x14, | |
376 | MR_PD_STATE_ONLINE = 0x18, | |
377 | MR_PD_STATE_COPYBACK = 0x20, | |
378 | MR_PD_STATE_SYSTEM = 0x40, | |
379 | }; | |
380 | ||
381 | ||
382 | /* | |
383 | * defines the physical drive address structure | |
384 | */ | |
385 | struct MR_PD_ADDRESS { | |
386 | u16 deviceId; | |
387 | u16 enclDeviceId; | |
388 | ||
389 | union { | |
390 | struct { | |
391 | u8 enclIndex; | |
392 | u8 slotNumber; | |
393 | } mrPdAddress; | |
394 | struct { | |
395 | u8 enclPosition; | |
396 | u8 enclConnectorIndex; | |
397 | } mrEnclAddress; | |
398 | }; | |
399 | u8 scsiDevType; | |
400 | union { | |
401 | u8 connectedPortBitmap; | |
402 | u8 connectedPortNumbers; | |
403 | }; | |
404 | u64 sasAddr[2]; | |
405 | } __packed; | |
406 | ||
407 | /* | |
408 | * defines the physical drive list structure | |
409 | */ | |
410 | struct MR_PD_LIST { | |
411 | u32 size; | |
412 | u32 count; | |
413 | struct MR_PD_ADDRESS addr[1]; | |
414 | } __packed; | |
415 | ||
416 | struct megasas_pd_list { | |
417 | u16 tid; | |
418 | u8 driveType; | |
419 | u8 driveState; | |
420 | } __packed; | |
421 | ||
bdc6fb8d YB |
422 | /* |
423 | * defines the logical drive reference structure | |
424 | */ | |
425 | union MR_LD_REF { | |
426 | struct { | |
427 | u8 targetId; | |
428 | u8 reserved; | |
429 | u16 seqNum; | |
430 | }; | |
431 | u32 ref; | |
432 | } __packed; | |
433 | ||
434 | /* | |
435 | * defines the logical drive list structure | |
436 | */ | |
437 | struct MR_LD_LIST { | |
438 | u32 ldCount; | |
439 | u32 reserved; | |
440 | struct { | |
441 | union MR_LD_REF ref; | |
442 | u8 state; | |
443 | u8 reserved[3]; | |
444 | u64 size; | |
445 | } ldList[MAX_LOGICAL_DRIVES]; | |
446 | } __packed; | |
447 | ||
21c9e160 | 448 | struct MR_LD_TARGETID_LIST { |
449 | u32 size; | |
450 | u32 count; | |
451 | u8 pad[3]; | |
452 | u8 targetId[MAX_LOGICAL_DRIVES]; | |
453 | }; | |
454 | ||
455 | ||
c4a3e0a5 BS |
456 | /* |
457 | * SAS controller properties | |
458 | */ | |
459 | struct megasas_ctrl_prop { | |
460 | ||
461 | u16 seq_num; | |
462 | u16 pred_fail_poll_interval; | |
463 | u16 intr_throttle_count; | |
464 | u16 intr_throttle_timeouts; | |
465 | u8 rebuild_rate; | |
466 | u8 patrol_read_rate; | |
467 | u8 bgi_rate; | |
468 | u8 cc_rate; | |
469 | u8 recon_rate; | |
470 | u8 cache_flush_interval; | |
471 | u8 spinup_drv_count; | |
472 | u8 spinup_delay; | |
473 | u8 cluster_enable; | |
474 | u8 coercion_mode; | |
475 | u8 alarm_enable; | |
476 | u8 disable_auto_rebuild; | |
477 | u8 disable_battery_warn; | |
478 | u8 ecc_bucket_size; | |
479 | u16 ecc_bucket_leak_rate; | |
480 | u8 restore_hotspare_on_insertion; | |
481 | u8 expose_encl_devices; | |
39a98554 | 482 | u8 maintainPdFailHistory; |
483 | u8 disallowHostRequestReordering; | |
484 | u8 abortCCOnError; | |
485 | u8 loadBalanceMode; | |
486 | u8 disableAutoDetectBackplane; | |
487 | ||
488 | u8 snapVDSpace; | |
489 | ||
490 | /* | |
491 | * Add properties that can be controlled by | |
492 | * a bit in the following structure. | |
493 | */ | |
39a98554 | 494 | struct { |
94cd65dd SS |
495 | #if defined(__BIG_ENDIAN_BITFIELD) |
496 | u32 reserved:18; | |
497 | u32 enableJBOD:1; | |
498 | u32 disableSpinDownHS:1; | |
499 | u32 allowBootWithPinnedCache:1; | |
500 | u32 disableOnlineCtrlReset:1; | |
501 | u32 enableSecretKeyControl:1; | |
502 | u32 autoEnhancedImport:1; | |
503 | u32 enableSpinDownUnconfigured:1; | |
504 | u32 SSDPatrolReadEnabled:1; | |
505 | u32 SSDSMARTerEnabled:1; | |
506 | u32 disableNCQ:1; | |
507 | u32 useFdeOnly:1; | |
508 | u32 prCorrectUnconfiguredAreas:1; | |
509 | u32 SMARTerEnabled:1; | |
510 | u32 copyBackDisabled:1; | |
511 | #else | |
512 | u32 copyBackDisabled:1; | |
513 | u32 SMARTerEnabled:1; | |
514 | u32 prCorrectUnconfiguredAreas:1; | |
515 | u32 useFdeOnly:1; | |
516 | u32 disableNCQ:1; | |
517 | u32 SSDSMARTerEnabled:1; | |
518 | u32 SSDPatrolReadEnabled:1; | |
519 | u32 enableSpinDownUnconfigured:1; | |
520 | u32 autoEnhancedImport:1; | |
521 | u32 enableSecretKeyControl:1; | |
522 | u32 disableOnlineCtrlReset:1; | |
523 | u32 allowBootWithPinnedCache:1; | |
524 | u32 disableSpinDownHS:1; | |
525 | u32 enableJBOD:1; | |
526 | u32 reserved:18; | |
527 | #endif | |
39a98554 | 528 | } OnOffProperties; |
529 | u8 autoSnapVDSpace; | |
530 | u8 viewSpace; | |
531 | u16 spinDownTime; | |
532 | u8 reserved[24]; | |
81e403ce | 533 | } __packed; |
c4a3e0a5 BS |
534 | |
535 | /* | |
536 | * SAS controller information | |
537 | */ | |
538 | struct megasas_ctrl_info { | |
539 | ||
540 | /* | |
541 | * PCI device information | |
542 | */ | |
543 | struct { | |
544 | ||
545 | u16 vendor_id; | |
546 | u16 device_id; | |
547 | u16 sub_vendor_id; | |
548 | u16 sub_device_id; | |
549 | u8 reserved[24]; | |
550 | ||
551 | } __attribute__ ((packed)) pci; | |
552 | ||
553 | /* | |
554 | * Host interface information | |
555 | */ | |
556 | struct { | |
557 | ||
558 | u8 PCIX:1; | |
559 | u8 PCIE:1; | |
560 | u8 iSCSI:1; | |
561 | u8 SAS_3G:1; | |
562 | u8 reserved_0:4; | |
563 | u8 reserved_1[6]; | |
564 | u8 port_count; | |
565 | u64 port_addr[8]; | |
566 | ||
567 | } __attribute__ ((packed)) host_interface; | |
568 | ||
569 | /* | |
570 | * Device (backend) interface information | |
571 | */ | |
572 | struct { | |
573 | ||
574 | u8 SPI:1; | |
575 | u8 SAS_3G:1; | |
576 | u8 SATA_1_5G:1; | |
577 | u8 SATA_3G:1; | |
578 | u8 reserved_0:4; | |
579 | u8 reserved_1[6]; | |
580 | u8 port_count; | |
581 | u64 port_addr[8]; | |
582 | ||
583 | } __attribute__ ((packed)) device_interface; | |
584 | ||
585 | /* | |
586 | * List of components residing in flash. All str are null terminated | |
587 | */ | |
588 | u32 image_check_word; | |
589 | u32 image_component_count; | |
590 | ||
591 | struct { | |
592 | ||
593 | char name[8]; | |
594 | char version[32]; | |
595 | char build_date[16]; | |
596 | char built_time[16]; | |
597 | ||
598 | } __attribute__ ((packed)) image_component[8]; | |
599 | ||
600 | /* | |
601 | * List of flash components that have been flashed on the card, but | |
602 | * are not in use, pending reset of the adapter. This list will be | |
603 | * empty if a flash operation has not occurred. All stings are null | |
604 | * terminated | |
605 | */ | |
606 | u32 pending_image_component_count; | |
607 | ||
608 | struct { | |
609 | ||
610 | char name[8]; | |
611 | char version[32]; | |
612 | char build_date[16]; | |
613 | char build_time[16]; | |
614 | ||
615 | } __attribute__ ((packed)) pending_image_component[8]; | |
616 | ||
617 | u8 max_arms; | |
618 | u8 max_spans; | |
619 | u8 max_arrays; | |
620 | u8 max_lds; | |
621 | ||
622 | char product_name[80]; | |
623 | char serial_no[32]; | |
624 | ||
625 | /* | |
626 | * Other physical/controller/operation information. Indicates the | |
627 | * presence of the hardware | |
628 | */ | |
629 | struct { | |
630 | ||
631 | u32 bbu:1; | |
632 | u32 alarm:1; | |
633 | u32 nvram:1; | |
634 | u32 uart:1; | |
635 | u32 reserved:28; | |
636 | ||
637 | } __attribute__ ((packed)) hw_present; | |
638 | ||
639 | u32 current_fw_time; | |
640 | ||
641 | /* | |
642 | * Maximum data transfer sizes | |
643 | */ | |
644 | u16 max_concurrent_cmds; | |
645 | u16 max_sge_count; | |
646 | u32 max_request_size; | |
647 | ||
648 | /* | |
649 | * Logical and physical device counts | |
650 | */ | |
651 | u16 ld_present_count; | |
652 | u16 ld_degraded_count; | |
653 | u16 ld_offline_count; | |
654 | ||
655 | u16 pd_present_count; | |
656 | u16 pd_disk_present_count; | |
657 | u16 pd_disk_pred_failure_count; | |
658 | u16 pd_disk_failed_count; | |
659 | ||
660 | /* | |
661 | * Memory size information | |
662 | */ | |
663 | u16 nvram_size; | |
664 | u16 memory_size; | |
665 | u16 flash_size; | |
666 | ||
667 | /* | |
668 | * Error counters | |
669 | */ | |
670 | u16 mem_correctable_error_count; | |
671 | u16 mem_uncorrectable_error_count; | |
672 | ||
673 | /* | |
674 | * Cluster information | |
675 | */ | |
676 | u8 cluster_permitted; | |
677 | u8 cluster_active; | |
678 | ||
679 | /* | |
680 | * Additional max data transfer sizes | |
681 | */ | |
682 | u16 max_strips_per_io; | |
683 | ||
684 | /* | |
685 | * Controller capabilities structures | |
686 | */ | |
687 | struct { | |
688 | ||
689 | u32 raid_level_0:1; | |
690 | u32 raid_level_1:1; | |
691 | u32 raid_level_5:1; | |
692 | u32 raid_level_1E:1; | |
693 | u32 raid_level_6:1; | |
694 | u32 reserved:27; | |
695 | ||
696 | } __attribute__ ((packed)) raid_levels; | |
697 | ||
698 | struct { | |
699 | ||
700 | u32 rbld_rate:1; | |
701 | u32 cc_rate:1; | |
702 | u32 bgi_rate:1; | |
703 | u32 recon_rate:1; | |
704 | u32 patrol_rate:1; | |
705 | u32 alarm_control:1; | |
706 | u32 cluster_supported:1; | |
707 | u32 bbu:1; | |
708 | u32 spanning_allowed:1; | |
709 | u32 dedicated_hotspares:1; | |
710 | u32 revertible_hotspares:1; | |
711 | u32 foreign_config_import:1; | |
712 | u32 self_diagnostic:1; | |
713 | u32 mixed_redundancy_arr:1; | |
714 | u32 global_hot_spares:1; | |
715 | u32 reserved:17; | |
716 | ||
717 | } __attribute__ ((packed)) adapter_operations; | |
718 | ||
719 | struct { | |
720 | ||
721 | u32 read_policy:1; | |
722 | u32 write_policy:1; | |
723 | u32 io_policy:1; | |
724 | u32 access_policy:1; | |
725 | u32 disk_cache_policy:1; | |
726 | u32 reserved:27; | |
727 | ||
728 | } __attribute__ ((packed)) ld_operations; | |
729 | ||
730 | struct { | |
731 | ||
732 | u8 min; | |
733 | u8 max; | |
734 | u8 reserved[2]; | |
735 | ||
736 | } __attribute__ ((packed)) stripe_sz_ops; | |
737 | ||
738 | struct { | |
739 | ||
740 | u32 force_online:1; | |
741 | u32 force_offline:1; | |
742 | u32 force_rebuild:1; | |
743 | u32 reserved:29; | |
744 | ||
745 | } __attribute__ ((packed)) pd_operations; | |
746 | ||
747 | struct { | |
748 | ||
749 | u32 ctrl_supports_sas:1; | |
750 | u32 ctrl_supports_sata:1; | |
751 | u32 allow_mix_in_encl:1; | |
752 | u32 allow_mix_in_ld:1; | |
753 | u32 allow_sata_in_cluster:1; | |
754 | u32 reserved:27; | |
755 | ||
756 | } __attribute__ ((packed)) pd_mix_support; | |
757 | ||
758 | /* | |
759 | * Define ECC single-bit-error bucket information | |
760 | */ | |
761 | u8 ecc_bucket_count; | |
762 | u8 reserved_2[11]; | |
763 | ||
764 | /* | |
765 | * Include the controller properties (changeable items) | |
766 | */ | |
767 | struct megasas_ctrl_prop properties; | |
768 | ||
769 | /* | |
770 | * Define FW pkg version (set in envt v'bles on OEM basis) | |
771 | */ | |
772 | char package_version[0x60]; | |
773 | ||
c4a3e0a5 | 774 | |
bc93d425 SS |
775 | /* |
776 | * If adapterOperations.supportMoreThan8Phys is set, | |
777 | * and deviceInterface.portCount is greater than 8, | |
778 | * SAS Addrs for first 8 ports shall be populated in | |
779 | * deviceInterface.portAddr, and the rest shall be | |
780 | * populated in deviceInterfacePortAddr2. | |
781 | */ | |
782 | u64 deviceInterfacePortAddr2[8]; /*6a0h */ | |
783 | u8 reserved3[128]; /*6e0h */ | |
784 | ||
785 | struct { /*760h */ | |
786 | u16 minPdRaidLevel_0:4; | |
787 | u16 maxPdRaidLevel_0:12; | |
788 | ||
789 | u16 minPdRaidLevel_1:4; | |
790 | u16 maxPdRaidLevel_1:12; | |
791 | ||
792 | u16 minPdRaidLevel_5:4; | |
793 | u16 maxPdRaidLevel_5:12; | |
794 | ||
795 | u16 minPdRaidLevel_1E:4; | |
796 | u16 maxPdRaidLevel_1E:12; | |
797 | ||
798 | u16 minPdRaidLevel_6:4; | |
799 | u16 maxPdRaidLevel_6:12; | |
800 | ||
801 | u16 minPdRaidLevel_10:4; | |
802 | u16 maxPdRaidLevel_10:12; | |
803 | ||
804 | u16 minPdRaidLevel_50:4; | |
805 | u16 maxPdRaidLevel_50:12; | |
806 | ||
807 | u16 minPdRaidLevel_60:4; | |
808 | u16 maxPdRaidLevel_60:12; | |
809 | ||
810 | u16 minPdRaidLevel_1E_RLQ0:4; | |
811 | u16 maxPdRaidLevel_1E_RLQ0:12; | |
812 | ||
813 | u16 minPdRaidLevel_1E0_RLQ0:4; | |
814 | u16 maxPdRaidLevel_1E0_RLQ0:12; | |
815 | ||
816 | u16 reserved[6]; | |
817 | } pdsForRaidLevels; | |
818 | ||
819 | u16 maxPds; /*780h */ | |
820 | u16 maxDedHSPs; /*782h */ | |
821 | u16 maxGlobalHSPs; /*784h */ | |
822 | u16 ddfSize; /*786h */ | |
823 | u8 maxLdsPerArray; /*788h */ | |
824 | u8 partitionsInDDF; /*789h */ | |
825 | u8 lockKeyBinding; /*78ah */ | |
826 | u8 maxPITsPerLd; /*78bh */ | |
827 | u8 maxViewsPerLd; /*78ch */ | |
828 | u8 maxTargetId; /*78dh */ | |
829 | u16 maxBvlVdSize; /*78eh */ | |
830 | ||
831 | u16 maxConfigurableSSCSize; /*790h */ | |
832 | u16 currentSSCsize; /*792h */ | |
833 | ||
834 | char expanderFwVersion[12]; /*794h */ | |
835 | ||
836 | u16 PFKTrialTimeRemaining; /*7A0h */ | |
837 | ||
838 | u16 cacheMemorySize; /*7A2h */ | |
839 | ||
840 | struct { /*7A4h */ | |
94cd65dd SS |
841 | #if defined(__BIG_ENDIAN_BITFIELD) |
842 | u32 reserved:11; | |
843 | u32 supportUnevenSpans:1; | |
844 | u32 dedicatedHotSparesLimited:1; | |
845 | u32 headlessMode:1; | |
846 | u32 supportEmulatedDrives:1; | |
847 | u32 supportResetNow:1; | |
848 | u32 realTimeScheduler:1; | |
849 | u32 supportSSDPatrolRead:1; | |
850 | u32 supportPerfTuning:1; | |
851 | u32 disableOnlinePFKChange:1; | |
852 | u32 supportJBOD:1; | |
853 | u32 supportBootTimePFKChange:1; | |
854 | u32 supportSetLinkSpeed:1; | |
855 | u32 supportEmergencySpares:1; | |
856 | u32 supportSuspendResumeBGops:1; | |
857 | u32 blockSSDWriteCacheChange:1; | |
858 | u32 supportShieldState:1; | |
859 | u32 supportLdBBMInfo:1; | |
860 | u32 supportLdPIType3:1; | |
861 | u32 supportLdPIType2:1; | |
862 | u32 supportLdPIType1:1; | |
863 | u32 supportPIcontroller:1; | |
864 | #else | |
bc93d425 SS |
865 | u32 supportPIcontroller:1; |
866 | u32 supportLdPIType1:1; | |
867 | u32 supportLdPIType2:1; | |
868 | u32 supportLdPIType3:1; | |
869 | u32 supportLdBBMInfo:1; | |
870 | u32 supportShieldState:1; | |
871 | u32 blockSSDWriteCacheChange:1; | |
872 | u32 supportSuspendResumeBGops:1; | |
873 | u32 supportEmergencySpares:1; | |
874 | u32 supportSetLinkSpeed:1; | |
875 | u32 supportBootTimePFKChange:1; | |
876 | u32 supportJBOD:1; | |
877 | u32 disableOnlinePFKChange:1; | |
878 | u32 supportPerfTuning:1; | |
879 | u32 supportSSDPatrolRead:1; | |
880 | u32 realTimeScheduler:1; | |
881 | ||
882 | u32 supportResetNow:1; | |
883 | u32 supportEmulatedDrives:1; | |
884 | u32 headlessMode:1; | |
885 | u32 dedicatedHotSparesLimited:1; | |
886 | ||
887 | ||
888 | u32 supportUnevenSpans:1; | |
889 | u32 reserved:11; | |
94cd65dd | 890 | #endif |
bc93d425 SS |
891 | } adapterOperations2; |
892 | ||
893 | u8 driverVersion[32]; /*7A8h */ | |
894 | u8 maxDAPdCountSpinup60; /*7C8h */ | |
895 | u8 temperatureROC; /*7C9h */ | |
896 | u8 temperatureCtrl; /*7CAh */ | |
897 | u8 reserved4; /*7CBh */ | |
898 | u16 maxConfigurablePds; /*7CCh */ | |
899 | ||
900 | ||
901 | u8 reserved5[2]; /*0x7CDh */ | |
902 | ||
903 | /* | |
904 | * HA cluster information | |
905 | */ | |
906 | struct { | |
907 | u32 peerIsPresent:1; | |
908 | u32 peerIsIncompatible:1; | |
909 | u32 hwIncompatible:1; | |
910 | u32 fwVersionMismatch:1; | |
911 | u32 ctrlPropIncompatible:1; | |
912 | u32 premiumFeatureMismatch:1; | |
913 | u32 reserved:26; | |
914 | } cluster; | |
915 | ||
916 | char clusterId[16]; /*7D4h */ | |
917 | ||
918 | u8 pad[0x800-0x7E4]; /*7E4 */ | |
81e403ce | 919 | } __packed; |
c4a3e0a5 BS |
920 | |
921 | /* | |
922 | * =============================== | |
923 | * MegaRAID SAS driver definitions | |
924 | * =============================== | |
925 | */ | |
926 | #define MEGASAS_MAX_PD_CHANNELS 2 | |
21c9e160 | 927 | #define MEGASAS_MAX_LD_CHANNELS 1 |
c4a3e0a5 BS |
928 | #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ |
929 | MEGASAS_MAX_LD_CHANNELS) | |
930 | #define MEGASAS_MAX_DEV_PER_CHANNEL 128 | |
931 | #define MEGASAS_DEFAULT_INIT_ID -1 | |
932 | #define MEGASAS_MAX_LUN 8 | |
933 | #define MEGASAS_MAX_LD 64 | |
6bf579a3 | 934 | #define MEGASAS_DEFAULT_CMD_PER_LUN 256 |
81e403ce YB |
935 | #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \ |
936 | MEGASAS_MAX_DEV_PER_CHANNEL) | |
bdc6fb8d YB |
937 | #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \ |
938 | MEGASAS_MAX_DEV_PER_CHANNEL) | |
c4a3e0a5 | 939 | |
1fd10685 | 940 | #define MEGASAS_MAX_SECTORS (2*1024) |
42a8d2b3 | 941 | #define MEGASAS_MAX_SECTORS_IEEE (2*128) |
658dcedb SP |
942 | #define MEGASAS_DBG_LVL 1 |
943 | ||
05e9ebbe SP |
944 | #define MEGASAS_FW_BUSY 1 |
945 | ||
d532dbe2 | 946 | /* Frame Type */ |
947 | #define IO_FRAME 0 | |
948 | #define PTHRU_FRAME 1 | |
949 | ||
c4a3e0a5 BS |
950 | /* |
951 | * When SCSI mid-layer calls driver's reset routine, driver waits for | |
952 | * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note | |
953 | * that the driver cannot _actually_ abort or reset pending commands. While | |
954 | * it is waiting for the commands to complete, it prints a diagnostic message | |
955 | * every MEGASAS_RESET_NOTICE_INTERVAL seconds | |
956 | */ | |
957 | #define MEGASAS_RESET_WAIT_TIME 180 | |
2a3681e5 | 958 | #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 |
c4a3e0a5 | 959 | #define MEGASAS_RESET_NOTICE_INTERVAL 5 |
c4a3e0a5 | 960 | #define MEGASAS_IOCTL_CMD 0 |
05e9ebbe | 961 | #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 |
c5daa6a9 | 962 | #define MEGASAS_THROTTLE_QUEUE_DEPTH 16 |
c4a3e0a5 BS |
963 | |
964 | /* | |
965 | * FW reports the maximum of number of commands that it can accept (maximum | |
966 | * commands that can be outstanding) at any time. The driver must report a | |
967 | * lower number to the mid layer because it can issue a few internal commands | |
968 | * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs | |
969 | * is shown below | |
970 | */ | |
971 | #define MEGASAS_INT_CMDS 32 | |
7bebf5c7 | 972 | #define MEGASAS_SKINNY_INT_CMDS 5 |
c4a3e0a5 | 973 | |
d46a3ad6 | 974 | #define MEGASAS_MAX_MSIX_QUEUES 128 |
c4a3e0a5 BS |
975 | /* |
976 | * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit | |
977 | * SGLs based on the size of dma_addr_t | |
978 | */ | |
979 | #define IS_DMA64 (sizeof(dma_addr_t) == 8) | |
980 | ||
39a98554 | 981 | #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 |
982 | ||
983 | #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 | |
984 | #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 | |
985 | #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 | |
986 | ||
c4a3e0a5 | 987 | #define MFI_OB_INTR_STATUS_MASK 0x00000002 |
14faea9f | 988 | #define MFI_POLL_TIMEOUT_SECS 60 |
c4a3e0a5 | 989 | |
f9876f0b | 990 | #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 |
6610a6b3 YB |
991 | #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 |
992 | #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) | |
87911122 YB |
993 | #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 |
994 | #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) | |
0e98936c | 995 | |
39a98554 | 996 | #define MFI_1068_PCSR_OFFSET 0x84 |
997 | #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 | |
998 | #define MFI_1068_FW_READY 0xDDDD0000 | |
d46a3ad6 SS |
999 | |
1000 | #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F | |
1001 | #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000 | |
1002 | #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 | |
1003 | #define MR_MAX_MSIX_REG_ARRAY 16 | |
0e98936c SP |
1004 | /* |
1005 | * register set for both 1068 and 1078 controllers | |
1006 | * structure extended for 1078 registers | |
1007 | */ | |
f9876f0b | 1008 | |
c4a3e0a5 | 1009 | struct megasas_register_set { |
9c915a8c | 1010 | u32 doorbell; /*0000h*/ |
1011 | u32 fusion_seq_offset; /*0004h*/ | |
1012 | u32 fusion_host_diag; /*0008h*/ | |
1013 | u32 reserved_01; /*000Ch*/ | |
c4a3e0a5 | 1014 | |
f9876f0b SP |
1015 | u32 inbound_msg_0; /*0010h*/ |
1016 | u32 inbound_msg_1; /*0014h*/ | |
1017 | u32 outbound_msg_0; /*0018h*/ | |
1018 | u32 outbound_msg_1; /*001Ch*/ | |
c4a3e0a5 | 1019 | |
f9876f0b SP |
1020 | u32 inbound_doorbell; /*0020h*/ |
1021 | u32 inbound_intr_status; /*0024h*/ | |
1022 | u32 inbound_intr_mask; /*0028h*/ | |
c4a3e0a5 | 1023 | |
f9876f0b SP |
1024 | u32 outbound_doorbell; /*002Ch*/ |
1025 | u32 outbound_intr_status; /*0030h*/ | |
1026 | u32 outbound_intr_mask; /*0034h*/ | |
c4a3e0a5 | 1027 | |
f9876f0b | 1028 | u32 reserved_1[2]; /*0038h*/ |
c4a3e0a5 | 1029 | |
f9876f0b SP |
1030 | u32 inbound_queue_port; /*0040h*/ |
1031 | u32 outbound_queue_port; /*0044h*/ | |
c4a3e0a5 | 1032 | |
9c915a8c | 1033 | u32 reserved_2[9]; /*0048h*/ |
1034 | u32 reply_post_host_index; /*006Ch*/ | |
1035 | u32 reserved_2_2[12]; /*0070h*/ | |
c4a3e0a5 | 1036 | |
f9876f0b | 1037 | u32 outbound_doorbell_clear; /*00A0h*/ |
c4a3e0a5 | 1038 | |
f9876f0b SP |
1039 | u32 reserved_3[3]; /*00A4h*/ |
1040 | ||
1041 | u32 outbound_scratch_pad ; /*00B0h*/ | |
9c915a8c | 1042 | u32 outbound_scratch_pad_2; /*00B4h*/ |
f9876f0b | 1043 | |
9c915a8c | 1044 | u32 reserved_4[2]; /*00B8h*/ |
f9876f0b SP |
1045 | |
1046 | u32 inbound_low_queue_port ; /*00C0h*/ | |
1047 | ||
1048 | u32 inbound_high_queue_port ; /*00C4h*/ | |
1049 | ||
1050 | u32 reserved_5; /*00C8h*/ | |
39a98554 | 1051 | u32 res_6[11]; /*CCh*/ |
1052 | u32 host_diag; | |
1053 | u32 seq_offset; | |
1054 | u32 index_registers[807]; /*00CCh*/ | |
c4a3e0a5 BS |
1055 | } __attribute__ ((packed)); |
1056 | ||
1057 | struct megasas_sge32 { | |
1058 | ||
1059 | u32 phys_addr; | |
1060 | u32 length; | |
1061 | ||
1062 | } __attribute__ ((packed)); | |
1063 | ||
1064 | struct megasas_sge64 { | |
1065 | ||
1066 | u64 phys_addr; | |
1067 | u32 length; | |
1068 | ||
1069 | } __attribute__ ((packed)); | |
1070 | ||
f4c9a131 YB |
1071 | struct megasas_sge_skinny { |
1072 | u64 phys_addr; | |
1073 | u32 length; | |
1074 | u32 flag; | |
1075 | } __packed; | |
1076 | ||
c4a3e0a5 BS |
1077 | union megasas_sgl { |
1078 | ||
1079 | struct megasas_sge32 sge32[1]; | |
1080 | struct megasas_sge64 sge64[1]; | |
f4c9a131 | 1081 | struct megasas_sge_skinny sge_skinny[1]; |
c4a3e0a5 BS |
1082 | |
1083 | } __attribute__ ((packed)); | |
1084 | ||
1085 | struct megasas_header { | |
1086 | ||
1087 | u8 cmd; /*00h */ | |
1088 | u8 sense_len; /*01h */ | |
1089 | u8 cmd_status; /*02h */ | |
1090 | u8 scsi_status; /*03h */ | |
1091 | ||
1092 | u8 target_id; /*04h */ | |
1093 | u8 lun; /*05h */ | |
1094 | u8 cdb_len; /*06h */ | |
1095 | u8 sge_count; /*07h */ | |
1096 | ||
1097 | u32 context; /*08h */ | |
1098 | u32 pad_0; /*0Ch */ | |
1099 | ||
1100 | u16 flags; /*10h */ | |
1101 | u16 timeout; /*12h */ | |
1102 | u32 data_xferlen; /*14h */ | |
1103 | ||
1104 | } __attribute__ ((packed)); | |
1105 | ||
1106 | union megasas_sgl_frame { | |
1107 | ||
1108 | struct megasas_sge32 sge32[8]; | |
1109 | struct megasas_sge64 sge64[5]; | |
1110 | ||
1111 | } __attribute__ ((packed)); | |
1112 | ||
d46a3ad6 SS |
1113 | typedef union _MFI_CAPABILITIES { |
1114 | struct { | |
94cd65dd SS |
1115 | #if defined(__BIG_ENDIAN_BITFIELD) |
1116 | u32 reserved:30; | |
1117 | u32 support_additional_msix:1; | |
1118 | u32 support_fp_remote_lun:1; | |
1119 | #else | |
d46a3ad6 SS |
1120 | u32 support_fp_remote_lun:1; |
1121 | u32 support_additional_msix:1; | |
1122 | u32 reserved:30; | |
94cd65dd | 1123 | #endif |
d46a3ad6 SS |
1124 | } mfi_capabilities; |
1125 | u32 reg; | |
1126 | } MFI_CAPABILITIES; | |
1127 | ||
c4a3e0a5 BS |
1128 | struct megasas_init_frame { |
1129 | ||
1130 | u8 cmd; /*00h */ | |
1131 | u8 reserved_0; /*01h */ | |
1132 | u8 cmd_status; /*02h */ | |
1133 | ||
1134 | u8 reserved_1; /*03h */ | |
d46a3ad6 | 1135 | MFI_CAPABILITIES driver_operations; /*04h*/ |
c4a3e0a5 BS |
1136 | |
1137 | u32 context; /*08h */ | |
1138 | u32 pad_0; /*0Ch */ | |
1139 | ||
1140 | u16 flags; /*10h */ | |
1141 | u16 reserved_3; /*12h */ | |
1142 | u32 data_xfer_len; /*14h */ | |
1143 | ||
1144 | u32 queue_info_new_phys_addr_lo; /*18h */ | |
1145 | u32 queue_info_new_phys_addr_hi; /*1Ch */ | |
1146 | u32 queue_info_old_phys_addr_lo; /*20h */ | |
1147 | u32 queue_info_old_phys_addr_hi; /*24h */ | |
1148 | ||
1149 | u32 reserved_4[6]; /*28h */ | |
1150 | ||
1151 | } __attribute__ ((packed)); | |
1152 | ||
1153 | struct megasas_init_queue_info { | |
1154 | ||
1155 | u32 init_flags; /*00h */ | |
1156 | u32 reply_queue_entries; /*04h */ | |
1157 | ||
1158 | u32 reply_queue_start_phys_addr_lo; /*08h */ | |
1159 | u32 reply_queue_start_phys_addr_hi; /*0Ch */ | |
1160 | u32 producer_index_phys_addr_lo; /*10h */ | |
1161 | u32 producer_index_phys_addr_hi; /*14h */ | |
1162 | u32 consumer_index_phys_addr_lo; /*18h */ | |
1163 | u32 consumer_index_phys_addr_hi; /*1Ch */ | |
1164 | ||
1165 | } __attribute__ ((packed)); | |
1166 | ||
1167 | struct megasas_io_frame { | |
1168 | ||
1169 | u8 cmd; /*00h */ | |
1170 | u8 sense_len; /*01h */ | |
1171 | u8 cmd_status; /*02h */ | |
1172 | u8 scsi_status; /*03h */ | |
1173 | ||
1174 | u8 target_id; /*04h */ | |
1175 | u8 access_byte; /*05h */ | |
1176 | u8 reserved_0; /*06h */ | |
1177 | u8 sge_count; /*07h */ | |
1178 | ||
1179 | u32 context; /*08h */ | |
1180 | u32 pad_0; /*0Ch */ | |
1181 | ||
1182 | u16 flags; /*10h */ | |
1183 | u16 timeout; /*12h */ | |
1184 | u32 lba_count; /*14h */ | |
1185 | ||
1186 | u32 sense_buf_phys_addr_lo; /*18h */ | |
1187 | u32 sense_buf_phys_addr_hi; /*1Ch */ | |
1188 | ||
1189 | u32 start_lba_lo; /*20h */ | |
1190 | u32 start_lba_hi; /*24h */ | |
1191 | ||
1192 | union megasas_sgl sgl; /*28h */ | |
1193 | ||
1194 | } __attribute__ ((packed)); | |
1195 | ||
1196 | struct megasas_pthru_frame { | |
1197 | ||
1198 | u8 cmd; /*00h */ | |
1199 | u8 sense_len; /*01h */ | |
1200 | u8 cmd_status; /*02h */ | |
1201 | u8 scsi_status; /*03h */ | |
1202 | ||
1203 | u8 target_id; /*04h */ | |
1204 | u8 lun; /*05h */ | |
1205 | u8 cdb_len; /*06h */ | |
1206 | u8 sge_count; /*07h */ | |
1207 | ||
1208 | u32 context; /*08h */ | |
1209 | u32 pad_0; /*0Ch */ | |
1210 | ||
1211 | u16 flags; /*10h */ | |
1212 | u16 timeout; /*12h */ | |
1213 | u32 data_xfer_len; /*14h */ | |
1214 | ||
1215 | u32 sense_buf_phys_addr_lo; /*18h */ | |
1216 | u32 sense_buf_phys_addr_hi; /*1Ch */ | |
1217 | ||
1218 | u8 cdb[16]; /*20h */ | |
1219 | union megasas_sgl sgl; /*30h */ | |
1220 | ||
1221 | } __attribute__ ((packed)); | |
1222 | ||
1223 | struct megasas_dcmd_frame { | |
1224 | ||
1225 | u8 cmd; /*00h */ | |
1226 | u8 reserved_0; /*01h */ | |
1227 | u8 cmd_status; /*02h */ | |
1228 | u8 reserved_1[4]; /*03h */ | |
1229 | u8 sge_count; /*07h */ | |
1230 | ||
1231 | u32 context; /*08h */ | |
1232 | u32 pad_0; /*0Ch */ | |
1233 | ||
1234 | u16 flags; /*10h */ | |
1235 | u16 timeout; /*12h */ | |
1236 | ||
1237 | u32 data_xfer_len; /*14h */ | |
1238 | u32 opcode; /*18h */ | |
1239 | ||
1240 | union { /*1Ch */ | |
1241 | u8 b[12]; | |
1242 | u16 s[6]; | |
1243 | u32 w[3]; | |
1244 | } mbox; | |
1245 | ||
1246 | union megasas_sgl sgl; /*28h */ | |
1247 | ||
1248 | } __attribute__ ((packed)); | |
1249 | ||
1250 | struct megasas_abort_frame { | |
1251 | ||
1252 | u8 cmd; /*00h */ | |
1253 | u8 reserved_0; /*01h */ | |
1254 | u8 cmd_status; /*02h */ | |
1255 | ||
1256 | u8 reserved_1; /*03h */ | |
1257 | u32 reserved_2; /*04h */ | |
1258 | ||
1259 | u32 context; /*08h */ | |
1260 | u32 pad_0; /*0Ch */ | |
1261 | ||
1262 | u16 flags; /*10h */ | |
1263 | u16 reserved_3; /*12h */ | |
1264 | u32 reserved_4; /*14h */ | |
1265 | ||
1266 | u32 abort_context; /*18h */ | |
1267 | u32 pad_1; /*1Ch */ | |
1268 | ||
1269 | u32 abort_mfi_phys_addr_lo; /*20h */ | |
1270 | u32 abort_mfi_phys_addr_hi; /*24h */ | |
1271 | ||
1272 | u32 reserved_5[6]; /*28h */ | |
1273 | ||
1274 | } __attribute__ ((packed)); | |
1275 | ||
1276 | struct megasas_smp_frame { | |
1277 | ||
1278 | u8 cmd; /*00h */ | |
1279 | u8 reserved_1; /*01h */ | |
1280 | u8 cmd_status; /*02h */ | |
1281 | u8 connection_status; /*03h */ | |
1282 | ||
1283 | u8 reserved_2[3]; /*04h */ | |
1284 | u8 sge_count; /*07h */ | |
1285 | ||
1286 | u32 context; /*08h */ | |
1287 | u32 pad_0; /*0Ch */ | |
1288 | ||
1289 | u16 flags; /*10h */ | |
1290 | u16 timeout; /*12h */ | |
1291 | ||
1292 | u32 data_xfer_len; /*14h */ | |
1293 | u64 sas_addr; /*18h */ | |
1294 | ||
1295 | union { | |
1296 | struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ | |
1297 | struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ | |
1298 | } sgl; | |
1299 | ||
1300 | } __attribute__ ((packed)); | |
1301 | ||
1302 | struct megasas_stp_frame { | |
1303 | ||
1304 | u8 cmd; /*00h */ | |
1305 | u8 reserved_1; /*01h */ | |
1306 | u8 cmd_status; /*02h */ | |
1307 | u8 reserved_2; /*03h */ | |
1308 | ||
1309 | u8 target_id; /*04h */ | |
1310 | u8 reserved_3[2]; /*05h */ | |
1311 | u8 sge_count; /*07h */ | |
1312 | ||
1313 | u32 context; /*08h */ | |
1314 | u32 pad_0; /*0Ch */ | |
1315 | ||
1316 | u16 flags; /*10h */ | |
1317 | u16 timeout; /*12h */ | |
1318 | ||
1319 | u32 data_xfer_len; /*14h */ | |
1320 | ||
1321 | u16 fis[10]; /*18h */ | |
1322 | u32 stp_flags; | |
1323 | ||
1324 | union { | |
1325 | struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ | |
1326 | struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ | |
1327 | } sgl; | |
1328 | ||
1329 | } __attribute__ ((packed)); | |
1330 | ||
1331 | union megasas_frame { | |
1332 | ||
1333 | struct megasas_header hdr; | |
1334 | struct megasas_init_frame init; | |
1335 | struct megasas_io_frame io; | |
1336 | struct megasas_pthru_frame pthru; | |
1337 | struct megasas_dcmd_frame dcmd; | |
1338 | struct megasas_abort_frame abort; | |
1339 | struct megasas_smp_frame smp; | |
1340 | struct megasas_stp_frame stp; | |
1341 | ||
1342 | u8 raw_bytes[64]; | |
1343 | }; | |
1344 | ||
1345 | struct megasas_cmd; | |
1346 | ||
1347 | union megasas_evt_class_locale { | |
1348 | ||
1349 | struct { | |
be26374b | 1350 | #ifndef __BIG_ENDIAN_BITFIELD |
c4a3e0a5 BS |
1351 | u16 locale; |
1352 | u8 reserved; | |
1353 | s8 class; | |
be26374b SS |
1354 | #else |
1355 | s8 class; | |
1356 | u8 reserved; | |
1357 | u16 locale; | |
1358 | #endif | |
c4a3e0a5 BS |
1359 | } __attribute__ ((packed)) members; |
1360 | ||
1361 | u32 word; | |
1362 | ||
1363 | } __attribute__ ((packed)); | |
1364 | ||
1365 | struct megasas_evt_log_info { | |
1366 | u32 newest_seq_num; | |
1367 | u32 oldest_seq_num; | |
1368 | u32 clear_seq_num; | |
1369 | u32 shutdown_seq_num; | |
1370 | u32 boot_seq_num; | |
1371 | ||
1372 | } __attribute__ ((packed)); | |
1373 | ||
1374 | struct megasas_progress { | |
1375 | ||
1376 | u16 progress; | |
1377 | u16 elapsed_seconds; | |
1378 | ||
1379 | } __attribute__ ((packed)); | |
1380 | ||
1381 | struct megasas_evtarg_ld { | |
1382 | ||
1383 | u16 target_id; | |
1384 | u8 ld_index; | |
1385 | u8 reserved; | |
1386 | ||
1387 | } __attribute__ ((packed)); | |
1388 | ||
1389 | struct megasas_evtarg_pd { | |
1390 | u16 device_id; | |
1391 | u8 encl_index; | |
1392 | u8 slot_number; | |
1393 | ||
1394 | } __attribute__ ((packed)); | |
1395 | ||
1396 | struct megasas_evt_detail { | |
1397 | ||
1398 | u32 seq_num; | |
1399 | u32 time_stamp; | |
1400 | u32 code; | |
1401 | union megasas_evt_class_locale cl; | |
1402 | u8 arg_type; | |
1403 | u8 reserved1[15]; | |
1404 | ||
1405 | union { | |
1406 | struct { | |
1407 | struct megasas_evtarg_pd pd; | |
1408 | u8 cdb_length; | |
1409 | u8 sense_length; | |
1410 | u8 reserved[2]; | |
1411 | u8 cdb[16]; | |
1412 | u8 sense[64]; | |
1413 | } __attribute__ ((packed)) cdbSense; | |
1414 | ||
1415 | struct megasas_evtarg_ld ld; | |
1416 | ||
1417 | struct { | |
1418 | struct megasas_evtarg_ld ld; | |
1419 | u64 count; | |
1420 | } __attribute__ ((packed)) ld_count; | |
1421 | ||
1422 | struct { | |
1423 | u64 lba; | |
1424 | struct megasas_evtarg_ld ld; | |
1425 | } __attribute__ ((packed)) ld_lba; | |
1426 | ||
1427 | struct { | |
1428 | struct megasas_evtarg_ld ld; | |
1429 | u32 prevOwner; | |
1430 | u32 newOwner; | |
1431 | } __attribute__ ((packed)) ld_owner; | |
1432 | ||
1433 | struct { | |
1434 | u64 ld_lba; | |
1435 | u64 pd_lba; | |
1436 | struct megasas_evtarg_ld ld; | |
1437 | struct megasas_evtarg_pd pd; | |
1438 | } __attribute__ ((packed)) ld_lba_pd_lba; | |
1439 | ||
1440 | struct { | |
1441 | struct megasas_evtarg_ld ld; | |
1442 | struct megasas_progress prog; | |
1443 | } __attribute__ ((packed)) ld_prog; | |
1444 | ||
1445 | struct { | |
1446 | struct megasas_evtarg_ld ld; | |
1447 | u32 prev_state; | |
1448 | u32 new_state; | |
1449 | } __attribute__ ((packed)) ld_state; | |
1450 | ||
1451 | struct { | |
1452 | u64 strip; | |
1453 | struct megasas_evtarg_ld ld; | |
1454 | } __attribute__ ((packed)) ld_strip; | |
1455 | ||
1456 | struct megasas_evtarg_pd pd; | |
1457 | ||
1458 | struct { | |
1459 | struct megasas_evtarg_pd pd; | |
1460 | u32 err; | |
1461 | } __attribute__ ((packed)) pd_err; | |
1462 | ||
1463 | struct { | |
1464 | u64 lba; | |
1465 | struct megasas_evtarg_pd pd; | |
1466 | } __attribute__ ((packed)) pd_lba; | |
1467 | ||
1468 | struct { | |
1469 | u64 lba; | |
1470 | struct megasas_evtarg_pd pd; | |
1471 | struct megasas_evtarg_ld ld; | |
1472 | } __attribute__ ((packed)) pd_lba_ld; | |
1473 | ||
1474 | struct { | |
1475 | struct megasas_evtarg_pd pd; | |
1476 | struct megasas_progress prog; | |
1477 | } __attribute__ ((packed)) pd_prog; | |
1478 | ||
1479 | struct { | |
1480 | struct megasas_evtarg_pd pd; | |
1481 | u32 prevState; | |
1482 | u32 newState; | |
1483 | } __attribute__ ((packed)) pd_state; | |
1484 | ||
1485 | struct { | |
1486 | u16 vendorId; | |
1487 | u16 deviceId; | |
1488 | u16 subVendorId; | |
1489 | u16 subDeviceId; | |
1490 | } __attribute__ ((packed)) pci; | |
1491 | ||
1492 | u32 rate; | |
1493 | char str[96]; | |
1494 | ||
1495 | struct { | |
1496 | u32 rtc; | |
1497 | u32 elapsedSeconds; | |
1498 | } __attribute__ ((packed)) time; | |
1499 | ||
1500 | struct { | |
1501 | u32 ecar; | |
1502 | u32 elog; | |
1503 | char str[64]; | |
1504 | } __attribute__ ((packed)) ecc; | |
1505 | ||
1506 | u8 b[96]; | |
1507 | u16 s[48]; | |
1508 | u32 w[24]; | |
1509 | u64 d[12]; | |
1510 | } args; | |
1511 | ||
1512 | char description[128]; | |
1513 | ||
1514 | } __attribute__ ((packed)); | |
1515 | ||
7e8a75f4 | 1516 | struct megasas_aen_event { |
c1d390d8 | 1517 | struct delayed_work hotplug_work; |
7e8a75f4 YB |
1518 | struct megasas_instance *instance; |
1519 | }; | |
1520 | ||
c8e858fe | 1521 | struct megasas_irq_context { |
1522 | struct megasas_instance *instance; | |
1523 | u32 MSIxIndex; | |
1524 | }; | |
1525 | ||
c4a3e0a5 BS |
1526 | struct megasas_instance { |
1527 | ||
1528 | u32 *producer; | |
1529 | dma_addr_t producer_h; | |
1530 | u32 *consumer; | |
1531 | dma_addr_t consumer_h; | |
1532 | ||
1533 | u32 *reply_queue; | |
1534 | dma_addr_t reply_queue_h; | |
1535 | ||
c4a3e0a5 | 1536 | struct megasas_register_set __iomem *reg_set; |
d46a3ad6 | 1537 | u32 *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY]; |
81e403ce | 1538 | struct megasas_pd_list pd_list[MEGASAS_MAX_PD]; |
999ece0a | 1539 | struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD]; |
bdc6fb8d | 1540 | u8 ld_ids[MEGASAS_MAX_LD_IDS]; |
c4a3e0a5 | 1541 | s8 init_id; |
c4a3e0a5 BS |
1542 | |
1543 | u16 max_num_sge; | |
1544 | u16 max_fw_cmds; | |
9c915a8c | 1545 | /* For Fusion its num IOCTL cmds, for others MFI based its |
1546 | max_fw_cmds */ | |
1547 | u16 max_mfi_cmds; | |
c4a3e0a5 | 1548 | u32 max_sectors_per_req; |
7e8a75f4 | 1549 | struct megasas_aen_event *ev; |
c4a3e0a5 BS |
1550 | |
1551 | struct megasas_cmd **cmd_list; | |
1552 | struct list_head cmd_pool; | |
39a98554 | 1553 | /* used to sync fire the cmd to fw */ |
c4a3e0a5 | 1554 | spinlock_t cmd_pool_lock; |
39a98554 | 1555 | /* used to sync fire the cmd to fw */ |
1556 | spinlock_t hba_lock; | |
7343eb65 | 1557 | /* used to synch producer, consumer ptrs in dpc */ |
1558 | spinlock_t completion_lock; | |
c4a3e0a5 BS |
1559 | struct dma_pool *frame_dma_pool; |
1560 | struct dma_pool *sense_dma_pool; | |
1561 | ||
1562 | struct megasas_evt_detail *evt_detail; | |
1563 | dma_addr_t evt_detail_h; | |
1564 | struct megasas_cmd *aen_cmd; | |
e5a69e27 | 1565 | struct mutex aen_mutex; |
c4a3e0a5 BS |
1566 | struct semaphore ioctl_sem; |
1567 | ||
1568 | struct Scsi_Host *host; | |
1569 | ||
1570 | wait_queue_head_t int_cmd_wait_q; | |
1571 | wait_queue_head_t abort_cmd_wait_q; | |
1572 | ||
1573 | struct pci_dev *pdev; | |
1574 | u32 unique_id; | |
39a98554 | 1575 | u32 fw_support_ieee; |
c4a3e0a5 | 1576 | |
e4a082c7 | 1577 | atomic_t fw_outstanding; |
39a98554 | 1578 | atomic_t fw_reset_no_pci_access; |
1341c939 SP |
1579 | |
1580 | struct megasas_instance_template *instancet; | |
5d018ad0 | 1581 | struct tasklet_struct isr_tasklet; |
39a98554 | 1582 | struct work_struct work_init; |
05e9ebbe SP |
1583 | |
1584 | u8 flag; | |
c3518837 | 1585 | u8 unload; |
f4c9a131 | 1586 | u8 flag_ieee; |
39a98554 | 1587 | u8 issuepend_done; |
1588 | u8 disableOnlineCtrlReset; | |
bc93d425 | 1589 | u8 UnevenSpanSupport; |
39a98554 | 1590 | u8 adprecovery; |
05e9ebbe | 1591 | unsigned long last_time; |
39a98554 | 1592 | u32 mfiStatus; |
1593 | u32 last_seq_num; | |
ad84db2e | 1594 | |
39a98554 | 1595 | struct list_head internal_reset_pending_q; |
80d9da98 | 1596 | |
25985edc | 1597 | /* Ptr to hba specific information */ |
9c915a8c | 1598 | void *ctrl_context; |
c8e858fe | 1599 | unsigned int msix_vectors; |
1600 | struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES]; | |
1601 | struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES]; | |
9c915a8c | 1602 | u64 map_id; |
1603 | struct megasas_cmd *map_update_cmd; | |
b6d5d880 | 1604 | unsigned long bar; |
9c915a8c | 1605 | long reset_flags; |
1606 | struct mutex reset_mutex; | |
c5daa6a9 | 1607 | int throttlequeuedepth; |
d46a3ad6 | 1608 | u8 mask_interrupts; |
404a8a1a | 1609 | u8 is_imr; |
39a98554 | 1610 | }; |
1611 | ||
1612 | enum { | |
1613 | MEGASAS_HBA_OPERATIONAL = 0, | |
1614 | MEGASAS_ADPRESET_SM_INFAULT = 1, | |
1615 | MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, | |
1616 | MEGASAS_ADPRESET_SM_OPERATIONAL = 3, | |
1617 | MEGASAS_HW_CRITICAL_ERROR = 4, | |
1618 | MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, | |
c4a3e0a5 BS |
1619 | }; |
1620 | ||
0c79e681 YB |
1621 | struct megasas_instance_template { |
1622 | void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \ | |
1623 | u32, struct megasas_register_set __iomem *); | |
1624 | ||
d46a3ad6 SS |
1625 | void (*enable_intr)(struct megasas_instance *); |
1626 | void (*disable_intr)(struct megasas_instance *); | |
0c79e681 YB |
1627 | |
1628 | int (*clear_intr)(struct megasas_register_set __iomem *); | |
1629 | ||
1630 | u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); | |
39a98554 | 1631 | int (*adp_reset)(struct megasas_instance *, \ |
1632 | struct megasas_register_set __iomem *); | |
1633 | int (*check_reset)(struct megasas_instance *, \ | |
1634 | struct megasas_register_set __iomem *); | |
cd50ba8e | 1635 | irqreturn_t (*service_isr)(int irq, void *devp); |
1636 | void (*tasklet)(unsigned long); | |
1637 | u32 (*init_adapter)(struct megasas_instance *); | |
1638 | u32 (*build_and_issue_cmd) (struct megasas_instance *, | |
1639 | struct scsi_cmnd *); | |
1640 | void (*issue_dcmd) (struct megasas_instance *instance, | |
1641 | struct megasas_cmd *cmd); | |
0c79e681 YB |
1642 | }; |
1643 | ||
c4a3e0a5 BS |
1644 | #define MEGASAS_IS_LOGICAL(scp) \ |
1645 | (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1 | |
1646 | ||
1647 | #define MEGASAS_DEV_INDEX(inst, scp) \ | |
1648 | ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ | |
1649 | scp->device->id | |
1650 | ||
1651 | struct megasas_cmd { | |
1652 | ||
1653 | union megasas_frame *frame; | |
1654 | dma_addr_t frame_phys_addr; | |
1655 | u8 *sense; | |
1656 | dma_addr_t sense_phys_addr; | |
1657 | ||
1658 | u32 index; | |
1659 | u8 sync_cmd; | |
1660 | u8 cmd_status; | |
39a98554 | 1661 | u8 abort_aen; |
1662 | u8 retry_for_fw_reset; | |
1663 | ||
c4a3e0a5 BS |
1664 | |
1665 | struct list_head list; | |
1666 | struct scsi_cmnd *scmd; | |
1667 | struct megasas_instance *instance; | |
9c915a8c | 1668 | union { |
1669 | struct { | |
1670 | u16 smid; | |
1671 | u16 resvd; | |
1672 | } context; | |
1673 | u32 frame_count; | |
1674 | }; | |
c4a3e0a5 BS |
1675 | }; |
1676 | ||
1677 | #define MAX_MGMT_ADAPTERS 1024 | |
1678 | #define MAX_IOCTL_SGE 16 | |
1679 | ||
1680 | struct megasas_iocpacket { | |
1681 | ||
1682 | u16 host_no; | |
1683 | u16 __pad1; | |
1684 | u32 sgl_off; | |
1685 | u32 sge_count; | |
1686 | u32 sense_off; | |
1687 | u32 sense_len; | |
1688 | union { | |
1689 | u8 raw[128]; | |
1690 | struct megasas_header hdr; | |
1691 | } frame; | |
1692 | ||
1693 | struct iovec sgl[MAX_IOCTL_SGE]; | |
1694 | ||
1695 | } __attribute__ ((packed)); | |
1696 | ||
1697 | struct megasas_aen { | |
1698 | u16 host_no; | |
1699 | u16 __pad1; | |
1700 | u32 seq_num; | |
1701 | u32 class_locale_word; | |
1702 | } __attribute__ ((packed)); | |
1703 | ||
1704 | #ifdef CONFIG_COMPAT | |
1705 | struct compat_megasas_iocpacket { | |
1706 | u16 host_no; | |
1707 | u16 __pad1; | |
1708 | u32 sgl_off; | |
1709 | u32 sge_count; | |
1710 | u32 sense_off; | |
1711 | u32 sense_len; | |
1712 | union { | |
1713 | u8 raw[128]; | |
1714 | struct megasas_header hdr; | |
1715 | } frame; | |
1716 | struct compat_iovec sgl[MAX_IOCTL_SGE]; | |
1717 | } __attribute__ ((packed)); | |
1718 | ||
0e98936c | 1719 | #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) |
c4a3e0a5 BS |
1720 | #endif |
1721 | ||
cb59aa6a | 1722 | #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) |
c4a3e0a5 BS |
1723 | #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) |
1724 | ||
1725 | struct megasas_mgmt_info { | |
1726 | ||
1727 | u16 count; | |
1728 | struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; | |
1729 | int max_index; | |
1730 | }; | |
1731 | ||
21c9e160 | 1732 | u8 |
1733 | MR_BuildRaidContext(struct megasas_instance *instance, | |
1734 | struct IO_REQUEST_INFO *io_info, | |
1735 | struct RAID_CONTEXT *pRAID_Context, | |
1736 | struct MR_FW_RAID_MAP_ALL *map, u8 **raidLUN); | |
be26374b | 1737 | u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_FW_RAID_MAP_ALL *map); |
21c9e160 | 1738 | struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_FW_RAID_MAP_ALL *map); |
1739 | u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_FW_RAID_MAP_ALL *map); | |
1740 | u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_FW_RAID_MAP_ALL *map); | |
1741 | u16 MR_PdDevHandleGet(u32 pd, struct MR_FW_RAID_MAP_ALL *map); | |
1742 | u16 MR_GetLDTgtId(u32 ld, struct MR_FW_RAID_MAP_ALL *map); | |
1743 | ||
c4a3e0a5 | 1744 | #endif /*LSI_MEGARAID_SAS_H */ |