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megaraid_sas: Update device queue depth based on interface type
[linux-2.6-block.git] / drivers / scsi / megaraid / megaraid_sas.h
CommitLineData
c4a3e0a5 1/*
3f1530c1 2 * Linux MegaRAID driver for SAS based RAID controllers
c4a3e0a5 3 *
e399065b
SS		 4 * Copyright (c) 2003-2013 LSI Corporation
5 * Copyright (c) 2013-2014 Avago Technologies
c4a3e0a5 6 *
3f1530c1 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
c4a3e0a5 11 *
3f1530c1 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
c4a3e0a5 16 *
3f1530c1 17 * You should have received a copy of the GNU General Public License
e399065b 18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
3f1530c1 19 *
20 * FILE: megaraid_sas.h
21 *
e399065b
SS		 22 * Authors: Avago Technologies
23 * Kashyap Desai <kashyap.desai@avagotech.com>
24 * Sumit Saxena <sumit.saxena@avagotech.com>
3f1530c1 25 *
e399065b 26 * Send feedback to: megaraidlinux.pdl@avagotech.com
3f1530c1 27 *
e399065b
SS		 28 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
29 * San Jose, California 95131
c4a3e0a5
BS		 30 */
31
32#ifndef LSI_MEGARAID_SAS_H
33#define LSI_MEGARAID_SAS_H
34
a69b74d3 35/*
c4a3e0a5
BS		 36 * MegaRAID SAS Driver meta data
37 */
afb2b5dd 38#define MEGASAS_VERSION "06.808.16.00-rc1"
39#define MEGASAS_RELDATE "Oct. 8, 2015"
0e98936c
SP		 40
41/*
42 * Device IDs
43 */
44#define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
af7a5647 45#define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
0e98936c 46#define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
6610a6b3
YB		 47#define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
48#define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
87911122
YB		 49#define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
50#define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
9c915a8c 51#define PCI_DEVICE_ID_LSI_FUSION 0x005b
229fe47c 52#define PCI_DEVICE_ID_LSI_PLASMA 0x002f
36807e67 53#define PCI_DEVICE_ID_LSI_INVADER 0x005d
21d3c710 54#define PCI_DEVICE_ID_LSI_FURY 0x005f
90c204bc 55#define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce
56#define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf
7364d34b 57#define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052
58#define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053
0e98936c 59
39b72c3c
SS		 60/*
61 * Intel HBA SSDIDs
62 */
63#define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
64#define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
65#define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
66#define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
67#define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
68#define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
7364d34b 69#define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B
39b72c3c 70
90c204bc 71/*
72 * Intruder HBA SSDIDs
73 */
74#define MEGARAID_INTRUDER_SSDID1 0x9371
75#define MEGARAID_INTRUDER_SSDID2 0x9390
76#define MEGARAID_INTRUDER_SSDID3 0x9370
77
39b72c3c
SS		 78/*
79 * Intel HBA branding
80 */
81#define MEGARAID_INTEL_RS3DC080_BRANDING \
82 "Intel(R) RAID Controller RS3DC080"
83#define MEGARAID_INTEL_RS3DC040_BRANDING \
84 "Intel(R) RAID Controller RS3DC040"
85#define MEGARAID_INTEL_RS3SC008_BRANDING \
86 "Intel(R) RAID Controller RS3SC008"
87#define MEGARAID_INTEL_RS3MC044_BRANDING \
88 "Intel(R) RAID Controller RS3MC044"
89#define MEGARAID_INTEL_RS3WC080_BRANDING \
90 "Intel(R) RAID Controller RS3WC080"
91#define MEGARAID_INTEL_RS3WC040_BRANDING \
92 "Intel(R) RAID Controller RS3WC040"
7364d34b 93#define MEGARAID_INTEL_RMS3BC160_BRANDING \
94 "Intel(R) Integrated RAID Module RMS3BC160"
39b72c3c 95
c4a3e0a5
BS		 96/*
97 * =====================================
98 * MegaRAID SAS MFI firmware definitions
99 * =====================================
100 */
101
102/*
103 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
104 * protocol between the software and firmware. Commands are issued using
105 * "message frames"
106 */
107
a69b74d3 108/*
c4a3e0a5
BS		 109 * FW posts its state in upper 4 bits of outbound_msg_0 register
110 */
111#define MFI_STATE_MASK 0xF0000000
112#define MFI_STATE_UNDEFINED 0x00000000
113#define MFI_STATE_BB_INIT 0x10000000
114#define MFI_STATE_FW_INIT 0x40000000
115#define MFI_STATE_WAIT_HANDSHAKE 0x60000000
116#define MFI_STATE_FW_INIT_2 0x70000000
117#define MFI_STATE_DEVICE_SCAN 0x80000000
e3bbff9f 118#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
c4a3e0a5
BS		 119#define MFI_STATE_FLUSH_CACHE 0xA0000000
120#define MFI_STATE_READY 0xB0000000
121#define MFI_STATE_OPERATIONAL 0xC0000000
122#define MFI_STATE_FAULT 0xF0000000
fc62b3fc
SS		 123#define MFI_STATE_FORCE_OCR 0x00000080
124#define MFI_STATE_DMADONE 0x00000008
125#define MFI_STATE_CRASH_DUMP_DONE 0x00000004
7e70e733 126#define MFI_RESET_REQUIRED 0x00000001
127#define MFI_RESET_ADAPTER 0x00000002
c4a3e0a5
BS		 128#define MEGAMFI_FRAME_SIZE 64
129
a69b74d3 130/*
c4a3e0a5
BS		 131 * During FW init, clear pending cmds & reset state using inbound_msg_0
132 *
133 * ABORT : Abort all pending cmds
134 * READY : Move from OPERATIONAL to READY state; discard queue info
135 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
136 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
e3bbff9f
SP		 137 * HOTPLUG : Resume from Hotplug
138 * MFI_STOP_ADP : Send signal to FW to stop processing
c4a3e0a5 139 */
39a98554 140#define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
141#define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
142#define DIAG_WRITE_ENABLE (0x00000080)
143#define DIAG_RESET_ADAPTER (0x00000004)
144
145#define MFI_ADP_RESET 0x00000040
e3bbff9f 146#define MFI_INIT_ABORT 0x00000001
c4a3e0a5
BS		 147#define MFI_INIT_READY 0x00000002
148#define MFI_INIT_MFIMODE 0x00000004
149#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
e3bbff9f
SP		 150#define MFI_INIT_HOTPLUG 0x00000010
151#define MFI_STOP_ADP 0x00000020
152#define MFI_RESET_FLAGS MFI_INIT_READY| \
153 MFI_INIT_MFIMODE| \
154 MFI_INIT_ABORT
c4a3e0a5 155
a69b74d3 156/*
c4a3e0a5
BS		 157 * MFI frame flags
158 */
159#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
160#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
161#define MFI_FRAME_SGL32 0x0000
162#define MFI_FRAME_SGL64 0x0002
163#define MFI_FRAME_SENSE32 0x0000
164#define MFI_FRAME_SENSE64 0x0004
165#define MFI_FRAME_DIR_NONE 0x0000
166#define MFI_FRAME_DIR_WRITE 0x0008
167#define MFI_FRAME_DIR_READ 0x0010
168#define MFI_FRAME_DIR_BOTH 0x0018
f4c9a131 169#define MFI_FRAME_IEEE 0x0020
c4a3e0a5 170
4026e9aa
SS		 171/* Driver internal */
172#define DRV_DCMD_POLLED_MODE 0x1
6d40afbc 173#define DRV_DCMD_SKIP_REFIRE 0x2
4026e9aa 174
a69b74d3 175/*
c4a3e0a5
BS		 176 * Definition for cmd_status
177 */
178#define MFI_CMD_STATUS_POLL_MODE 0xFF
179
a69b74d3 180/*
c4a3e0a5
BS		 181 * MFI command opcodes
182 */
183#define MFI_CMD_INIT 0x00
184#define MFI_CMD_LD_READ 0x01
185#define MFI_CMD_LD_WRITE 0x02
186#define MFI_CMD_LD_SCSI_IO 0x03
187#define MFI_CMD_PD_SCSI_IO 0x04
188#define MFI_CMD_DCMD 0x05
189#define MFI_CMD_ABORT 0x06
190#define MFI_CMD_SMP 0x07
191#define MFI_CMD_STP 0x08
e5f93a36 192#define MFI_CMD_INVALID 0xff
c4a3e0a5
BS		 193
194#define MR_DCMD_CTRL_GET_INFO 0x01010000
bdc6fb8d 195#define MR_DCMD_LD_GET_LIST 0x03010000
21c9e160 196#define MR_DCMD_LD_LIST_QUERY 0x03010100
c4a3e0a5
BS		 197
198#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
199#define MR_FLUSH_CTRL_CACHE 0x01
200#define MR_FLUSH_DISK_CACHE 0x02
201
202#define MR_DCMD_CTRL_SHUTDOWN 0x01050000
31ea7088 203#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
c4a3e0a5
BS		 204#define MR_ENABLE_DRIVE_SPINDOWN 0x01
205
206#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
207#define MR_DCMD_CTRL_EVENT_GET 0x01040300
208#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
209#define MR_DCMD_LD_GET_PROPERTIES 0x03030000
210
211#define MR_DCMD_CLUSTER 0x08000000
212#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
213#define MR_DCMD_CLUSTER_RESET_LD 0x08010200
81e403ce 214#define MR_DCMD_PD_LIST_QUERY 0x02010100
c4a3e0a5 215
fc62b3fc
SS		 216#define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100
217#define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600)
2216c305 218#define MR_DCMD_PD_GET_INFO 0x02020000
fc62b3fc 219
bc93d425
SS		 220/*
221 * Global functions
222 */
223extern u8 MR_ValidateMapInfo(struct megasas_instance *instance);
224
225
a69b74d3 226/*
c4a3e0a5
BS		 227 * MFI command completion codes
228 */
229enum MFI_STAT {
230 MFI_STAT_OK = 0x00,
231 MFI_STAT_INVALID_CMD = 0x01,
232 MFI_STAT_INVALID_DCMD = 0x02,
233 MFI_STAT_INVALID_PARAMETER = 0x03,
234 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
235 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
236 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
237 MFI_STAT_APP_IN_USE = 0x07,
238 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
239 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
240 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
241 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
242 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
243 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
244 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
245 MFI_STAT_FLASH_BUSY = 0x0f,
246 MFI_STAT_FLASH_ERROR = 0x10,
247 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
248 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
249 MFI_STAT_FLASH_NOT_OPEN = 0x13,
250 MFI_STAT_FLASH_NOT_STARTED = 0x14,
251 MFI_STAT_FLUSH_FAILED = 0x15,
252 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
253 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
254 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
255 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
256 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
257 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
258 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
259 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
260 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
261 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
262 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
263 MFI_STAT_MFC_HW_ERROR = 0x21,
264 MFI_STAT_NO_HW_PRESENT = 0x22,
265 MFI_STAT_NOT_FOUND = 0x23,
266 MFI_STAT_NOT_IN_ENCL = 0x24,
267 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
268 MFI_STAT_PD_TYPE_WRONG = 0x26,
269 MFI_STAT_PR_DISABLED = 0x27,
270 MFI_STAT_ROW_INDEX_INVALID = 0x28,
271 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
272 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
273 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
274 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
275 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
276 MFI_STAT_SCSI_IO_FAILED = 0x2e,
277 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
278 MFI_STAT_SHUTDOWN_FAILED = 0x30,
279 MFI_STAT_TIME_NOT_SET = 0x31,
280 MFI_STAT_WRONG_STATE = 0x32,
281 MFI_STAT_LD_OFFLINE = 0x33,
282 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
283 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
284 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
285 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
286 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
36807e67 287 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
c4a3e0a5
BS		 288
289 MFI_STAT_INVALID_STATUS = 0xFF
290};
291
714f5177 292enum mfi_evt_class {
293 MFI_EVT_CLASS_DEBUG = -2,
294 MFI_EVT_CLASS_PROGRESS = -1,
295 MFI_EVT_CLASS_INFO = 0,
296 MFI_EVT_CLASS_WARNING = 1,
297 MFI_EVT_CLASS_CRITICAL = 2,
298 MFI_EVT_CLASS_FATAL = 3,
299 MFI_EVT_CLASS_DEAD = 4
300};
301
fc62b3fc
SS		 302/*
303 * Crash dump related defines
304 */
305#define MAX_CRASH_DUMP_SIZE 512
306#define CRASH_DMA_BUF_SIZE (1024 * 1024)
307
308enum MR_FW_CRASH_DUMP_STATE {
309 UNAVAILABLE = 0,
310 AVAILABLE = 1,
311 COPYING = 2,
312 COPIED = 3,
313 COPY_ERROR = 4,
314};
315
316enum _MR_CRASH_BUF_STATUS {
317 MR_CRASH_BUF_TURN_OFF = 0,
318 MR_CRASH_BUF_TURN_ON = 1,
319};
320
c4a3e0a5
BS		 321/*
322 * Number of mailbox bytes in DCMD message frame
323 */
324#define MFI_MBOX_SIZE 12
325
326enum MR_EVT_CLASS {
327
328 MR_EVT_CLASS_DEBUG = -2,
329 MR_EVT_CLASS_PROGRESS = -1,
330 MR_EVT_CLASS_INFO = 0,
331 MR_EVT_CLASS_WARNING = 1,
332 MR_EVT_CLASS_CRITICAL = 2,
333 MR_EVT_CLASS_FATAL = 3,
334 MR_EVT_CLASS_DEAD = 4,
335
336};
337
338enum MR_EVT_LOCALE {
339
340 MR_EVT_LOCALE_LD = 0x0001,
341 MR_EVT_LOCALE_PD = 0x0002,
342 MR_EVT_LOCALE_ENCL = 0x0004,
343 MR_EVT_LOCALE_BBU = 0x0008,
344 MR_EVT_LOCALE_SAS = 0x0010,
345 MR_EVT_LOCALE_CTRL = 0x0020,
346 MR_EVT_LOCALE_CONFIG = 0x0040,
347 MR_EVT_LOCALE_CLUSTER = 0x0080,
348 MR_EVT_LOCALE_ALL = 0xffff,
349
350};
351
352enum MR_EVT_ARGS {
353
354 MR_EVT_ARGS_NONE,
355 MR_EVT_ARGS_CDB_SENSE,
356 MR_EVT_ARGS_LD,
357 MR_EVT_ARGS_LD_COUNT,
358 MR_EVT_ARGS_LD_LBA,
359 MR_EVT_ARGS_LD_OWNER,
360 MR_EVT_ARGS_LD_LBA_PD_LBA,
361 MR_EVT_ARGS_LD_PROG,
362 MR_EVT_ARGS_LD_STATE,
363 MR_EVT_ARGS_LD_STRIP,
364 MR_EVT_ARGS_PD,
365 MR_EVT_ARGS_PD_ERR,
366 MR_EVT_ARGS_PD_LBA,
367 MR_EVT_ARGS_PD_LBA_LD,
368 MR_EVT_ARGS_PD_PROG,
369 MR_EVT_ARGS_PD_STATE,
370 MR_EVT_ARGS_PCI,
371 MR_EVT_ARGS_RATE,
372 MR_EVT_ARGS_STR,
373 MR_EVT_ARGS_TIME,
374 MR_EVT_ARGS_ECC,
81e403ce
YB		 375 MR_EVT_ARGS_LD_PROP,
376 MR_EVT_ARGS_PD_SPARE,
377 MR_EVT_ARGS_PD_INDEX,
378 MR_EVT_ARGS_DIAG_PASS,
379 MR_EVT_ARGS_DIAG_FAIL,
380 MR_EVT_ARGS_PD_LBA_LBA,
381 MR_EVT_ARGS_PORT_PHY,
382 MR_EVT_ARGS_PD_MISSING,
383 MR_EVT_ARGS_PD_ADDRESS,
384 MR_EVT_ARGS_BITMAP,
385 MR_EVT_ARGS_CONNECTOR,
386 MR_EVT_ARGS_PD_PD,
387 MR_EVT_ARGS_PD_FRU,
388 MR_EVT_ARGS_PD_PATHINFO,
389 MR_EVT_ARGS_PD_POWER_STATE,
390 MR_EVT_ARGS_GENERIC,
391};
c4a3e0a5 392
357ae967 393
394#define SGE_BUFFER_SIZE 4096
81e403ce
YB		 395/*
396 * define constants for device list query options
397 */
398enum MR_PD_QUERY_TYPE {
399 MR_PD_QUERY_TYPE_ALL = 0,
400 MR_PD_QUERY_TYPE_STATE = 1,
401 MR_PD_QUERY_TYPE_POWER_STATE = 2,
402 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
403 MR_PD_QUERY_TYPE_SPEED = 4,
404 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
c4a3e0a5
BS		 405};
406
21c9e160 407enum MR_LD_QUERY_TYPE {
408 MR_LD_QUERY_TYPE_ALL = 0,
409 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
410 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2,
411 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3,
412 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4,
413};
414
415
7e8a75f4
YB		 416#define MR_EVT_CFG_CLEARED 0x0004
417#define MR_EVT_LD_STATE_CHANGE 0x0051
418#define MR_EVT_PD_INSERTED 0x005b
419#define MR_EVT_PD_REMOVED 0x0070
420#define MR_EVT_LD_CREATED 0x008a
421#define MR_EVT_LD_DELETED 0x008b
422#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
423#define MR_EVT_LD_OFFLINE 0x00fc
424#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
c4bd2654 425#define MR_EVT_CTRL_PROP_CHANGED 0x012f
7e8a75f4 426
81e403ce
YB		 427enum MR_PD_STATE {
428 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
429 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
430 MR_PD_STATE_HOT_SPARE = 0x02,
431 MR_PD_STATE_OFFLINE = 0x10,
432 MR_PD_STATE_FAILED = 0x11,
433 MR_PD_STATE_REBUILD = 0x14,
434 MR_PD_STATE_ONLINE = 0x18,
435 MR_PD_STATE_COPYBACK = 0x20,
436 MR_PD_STATE_SYSTEM = 0x40,
437 };
438
2216c305
SS		 439union MR_PD_REF {
440 struct {
441 u16 deviceId;
442 u16 seqNum;
443 } mrPdRef;
444 u32 ref;
445};
446
447/*
448 * define the DDF Type bit structure
449 */
450union MR_PD_DDF_TYPE {
451 struct {
452 union {
453 struct {
454#ifndef __BIG_ENDIAN_BITFIELD
455 u16 forcedPDGUID:1;
456 u16 inVD:1;
457 u16 isGlobalSpare:1;
458 u16 isSpare:1;
459 u16 isForeign:1;
460 u16 reserved:7;
461 u16 intf:4;
462#else
463 u16 intf:4;
464 u16 reserved:7;
465 u16 isForeign:1;
466 u16 isSpare:1;
467 u16 isGlobalSpare:1;
468 u16 inVD:1;
469 u16 forcedPDGUID:1;
470#endif
471 } pdType;
472 u16 type;
473 };
474 u16 reserved;
475 } ddf;
476 struct {
477 u32 reserved;
478 } nonDisk;
479 u32 type;
480} __packed;
481
482/*
483 * defines the progress structure
484 */
485union MR_PROGRESS {
486 struct {
487 u16 progress;
488 union {
489 u16 elapsedSecs;
490 u16 elapsedSecsForLastPercent;
491 };
492 } mrProgress;
493 u32 w;
494} __packed;
495
496/*
497 * defines the physical drive progress structure
498 */
499struct MR_PD_PROGRESS {
500 struct {
501#ifndef MFI_BIG_ENDIAN
502 u32 rbld:1;
503 u32 patrol:1;
504 u32 clear:1;
505 u32 copyBack:1;
506 u32 erase:1;
507 u32 locate:1;
508 u32 reserved:26;
509#else
510 u32 reserved:26;
511 u32 locate:1;
512 u32 erase:1;
513 u32 copyBack:1;
514 u32 clear:1;
515 u32 patrol:1;
516 u32 rbld:1;
517#endif
518 } active;
519 union MR_PROGRESS rbld;
520 union MR_PROGRESS patrol;
521 union {
522 union MR_PROGRESS clear;
523 union MR_PROGRESS erase;
524 };
525
526 struct {
527#ifndef MFI_BIG_ENDIAN
528 u32 rbld:1;
529 u32 patrol:1;
530 u32 clear:1;
531 u32 copyBack:1;
532 u32 erase:1;
533 u32 reserved:27;
534#else
535 u32 reserved:27;
536 u32 erase:1;
537 u32 copyBack:1;
538 u32 clear:1;
539 u32 patrol:1;
540 u32 rbld:1;
541#endif
542 } pause;
543
544 union MR_PROGRESS reserved[3];
545} __packed;
546
547struct MR_PD_INFO {
548 union MR_PD_REF ref;
549 u8 inquiryData[96];
550 u8 vpdPage83[64];
551 u8 notSupported;
552 u8 scsiDevType;
553
554 union {
555 u8 connectedPortBitmap;
556 u8 connectedPortNumbers;
557 };
558
559 u8 deviceSpeed;
560 u32 mediaErrCount;
561 u32 otherErrCount;
562 u32 predFailCount;
563 u32 lastPredFailEventSeqNum;
564
565 u16 fwState;
566 u8 disabledForRemoval;
567 u8 linkSpeed;
568 union MR_PD_DDF_TYPE state;
569
570 struct {
571 u8 count;
572#ifndef __BIG_ENDIAN_BITFIELD
573 u8 isPathBroken:4;
574 u8 reserved3:3;
575 u8 widePortCapable:1;
576#else
577 u8 widePortCapable:1;
578 u8 reserved3:3;
579 u8 isPathBroken:4;
580#endif
581
582 u8 connectorIndex[2];
583 u8 reserved[4];
584 u64 sasAddr[2];
585 u8 reserved2[16];
586 } pathInfo;
587
588 u64 rawSize;
589 u64 nonCoercedSize;
590 u64 coercedSize;
591 u16 enclDeviceId;
592 u8 enclIndex;
593
594 union {
595 u8 slotNumber;
596 u8 enclConnectorIndex;
597 };
598
599 struct MR_PD_PROGRESS progInfo;
600 u8 badBlockTableFull;
601 u8 unusableInCurrentConfig;
602 u8 vpdPage83Ext[64];
603 u8 powerState;
604 u8 enclPosition;
605 u32 allowedOps;
606 u16 copyBackPartnerId;
607 u16 enclPartnerDeviceId;
608 struct {
609#ifndef __BIG_ENDIAN_BITFIELD
610 u16 fdeCapable:1;
611 u16 fdeEnabled:1;
612 u16 secured:1;
613 u16 locked:1;
614 u16 foreign:1;
615 u16 needsEKM:1;
616 u16 reserved:10;
617#else
618 u16 reserved:10;
619 u16 needsEKM:1;
620 u16 foreign:1;
621 u16 locked:1;
622 u16 secured:1;
623 u16 fdeEnabled:1;
624 u16 fdeCapable:1;
625#endif
626 } security;
627 u8 mediaType;
628 u8 notCertified;
629 u8 bridgeVendor[8];
630 u8 bridgeProductIdentification[16];
631 u8 bridgeProductRevisionLevel[4];
632 u8 satBridgeExists;
633
634 u8 interfaceType;
635 u8 temperature;
636 u8 emulatedBlockSize;
637 u16 userDataBlockSize;
638 u16 reserved2;
639
640 struct {
641#ifndef __BIG_ENDIAN_BITFIELD
642 u32 piType:3;
643 u32 piFormatted:1;
644 u32 piEligible:1;
645 u32 NCQ:1;
646 u32 WCE:1;
647 u32 commissionedSpare:1;
648 u32 emergencySpare:1;
649 u32 ineligibleForSSCD:1;
650 u32 ineligibleForLd:1;
651 u32 useSSEraseType:1;
652 u32 wceUnchanged:1;
653 u32 supportScsiUnmap:1;
654 u32 reserved:18;
655#else
656 u32 reserved:18;
657 u32 supportScsiUnmap:1;
658 u32 wceUnchanged:1;
659 u32 useSSEraseType:1;
660 u32 ineligibleForLd:1;
661 u32 ineligibleForSSCD:1;
662 u32 emergencySpare:1;
663 u32 commissionedSpare:1;
664 u32 WCE:1;
665 u32 NCQ:1;
666 u32 piEligible:1;
667 u32 piFormatted:1;
668 u32 piType:3;
669#endif
670 } properties;
671
672 u64 shieldDiagCompletionTime;
673 u8 shieldCounter;
674
675 u8 linkSpeedOther;
676 u8 reserved4[2];
677
678 struct {
679#ifndef __BIG_ENDIAN_BITFIELD
680 u32 bbmErrCountSupported:1;
681 u32 bbmErrCount:31;
682#else
683 u32 bbmErrCount:31;
684 u32 bbmErrCountSupported:1;
685#endif
686 } bbmErr;
687
688 u8 reserved1[512-428];
689} __packed;
81e403ce
YB		 690
691 /*
692 * defines the physical drive address structure
693 */
694struct MR_PD_ADDRESS {
9ab9ed38 695 __le16 deviceId;
81e403ce
YB		 696 u16 enclDeviceId;
697
698 union {
699 struct {
700 u8 enclIndex;
701 u8 slotNumber;
702 } mrPdAddress;
703 struct {
704 u8 enclPosition;
705 u8 enclConnectorIndex;
706 } mrEnclAddress;
707 };
708 u8 scsiDevType;
709 union {
710 u8 connectedPortBitmap;
711 u8 connectedPortNumbers;
712 };
713 u64 sasAddr[2];
714} __packed;
715
716/*
717 * defines the physical drive list structure
718 */
719struct MR_PD_LIST {
9ab9ed38
CH		 720 __le32 size;
721 __le32 count;
81e403ce
YB		 722 struct MR_PD_ADDRESS addr[1];
723} __packed;
724
725struct megasas_pd_list {
726 u16 tid;
727 u8 driveType;
728 u8 driveState;
2216c305 729 u8 interface;
81e403ce
YB		 730} __packed;
731
bdc6fb8d
YB		 732 /*
733 * defines the logical drive reference structure
734 */
735union MR_LD_REF {
736 struct {
737 u8 targetId;
738 u8 reserved;
9ab9ed38 739 __le16 seqNum;
bdc6fb8d 740 };
9ab9ed38 741 __le32 ref;
bdc6fb8d
YB		 742} __packed;
743
744/*
745 * defines the logical drive list structure
746 */
747struct MR_LD_LIST {
9ab9ed38
CH		 748 __le32 ldCount;
749 __le32 reserved;
bdc6fb8d
YB		 750 struct {
751 union MR_LD_REF ref;
752 u8 state;
753 u8 reserved[3];
9ab9ed38 754 __le64 size;
51087a86 755 } ldList[MAX_LOGICAL_DRIVES_EXT];
bdc6fb8d
YB		 756} __packed;
757
21c9e160 758struct MR_LD_TARGETID_LIST {
9ab9ed38
CH		 759 __le32 size;
760 __le32 count;
21c9e160 761 u8 pad[3];
51087a86 762 u8 targetId[MAX_LOGICAL_DRIVES_EXT];
21c9e160 763};
764
765
c4a3e0a5
BS		 766/*
767 * SAS controller properties
768 */
769struct megasas_ctrl_prop {
770
771 u16 seq_num;
772 u16 pred_fail_poll_interval;
773 u16 intr_throttle_count;
774 u16 intr_throttle_timeouts;
775 u8 rebuild_rate;
776 u8 patrol_read_rate;
777 u8 bgi_rate;
778 u8 cc_rate;
779 u8 recon_rate;
780 u8 cache_flush_interval;
781 u8 spinup_drv_count;
782 u8 spinup_delay;
783 u8 cluster_enable;
784 u8 coercion_mode;
785 u8 alarm_enable;
786 u8 disable_auto_rebuild;
787 u8 disable_battery_warn;
788 u8 ecc_bucket_size;
789 u16 ecc_bucket_leak_rate;
790 u8 restore_hotspare_on_insertion;
791 u8 expose_encl_devices;
39a98554 792 u8 maintainPdFailHistory;
793 u8 disallowHostRequestReordering;
794 u8 abortCCOnError;
795 u8 loadBalanceMode;
796 u8 disableAutoDetectBackplane;
797
798 u8 snapVDSpace;
799
800 /*
801 * Add properties that can be controlled by
802 * a bit in the following structure.
803 */
39a98554 804 struct {
94cd65dd
SS		 805#if defined(__BIG_ENDIAN_BITFIELD)
806 u32 reserved:18;
807 u32 enableJBOD:1;
808 u32 disableSpinDownHS:1;
809 u32 allowBootWithPinnedCache:1;
810 u32 disableOnlineCtrlReset:1;
811 u32 enableSecretKeyControl:1;
812 u32 autoEnhancedImport:1;
813 u32 enableSpinDownUnconfigured:1;
814 u32 SSDPatrolReadEnabled:1;
815 u32 SSDSMARTerEnabled:1;
816 u32 disableNCQ:1;
817 u32 useFdeOnly:1;
818 u32 prCorrectUnconfiguredAreas:1;
819 u32 SMARTerEnabled:1;
820 u32 copyBackDisabled:1;
821#else
822 u32 copyBackDisabled:1;
823 u32 SMARTerEnabled:1;
824 u32 prCorrectUnconfiguredAreas:1;
825 u32 useFdeOnly:1;
826 u32 disableNCQ:1;
827 u32 SSDSMARTerEnabled:1;
828 u32 SSDPatrolReadEnabled:1;
829 u32 enableSpinDownUnconfigured:1;
830 u32 autoEnhancedImport:1;
831 u32 enableSecretKeyControl:1;
832 u32 disableOnlineCtrlReset:1;
833 u32 allowBootWithPinnedCache:1;
834 u32 disableSpinDownHS:1;
835 u32 enableJBOD:1;
836 u32 reserved:18;
837#endif
39a98554 838 } OnOffProperties;
839 u8 autoSnapVDSpace;
840 u8 viewSpace;
9ab9ed38 841 __le16 spinDownTime;
39a98554 842 u8 reserved[24];
81e403ce 843} __packed;
c4a3e0a5
BS		 844
845/*
846 * SAS controller information
847 */
848struct megasas_ctrl_info {
849
850 /*
851 * PCI device information
852 */
853 struct {
854
9ab9ed38
CH		 855 __le16 vendor_id;
856 __le16 device_id;
857 __le16 sub_vendor_id;
858 __le16 sub_device_id;
c4a3e0a5
BS		 859 u8 reserved[24];
860
861 } __attribute__ ((packed)) pci;
862
863 /*
864 * Host interface information
865 */
866 struct {
867
868 u8 PCIX:1;
869 u8 PCIE:1;
870 u8 iSCSI:1;
871 u8 SAS_3G:1;
229fe47c 872 u8 SRIOV:1;
873 u8 reserved_0:3;
c4a3e0a5
BS		 874 u8 reserved_1[6];
875 u8 port_count;
876 u64 port_addr[8];
877
878 } __attribute__ ((packed)) host_interface;
879
880 /*
881 * Device (backend) interface information
882 */
883 struct {
884
885 u8 SPI:1;
886 u8 SAS_3G:1;
887 u8 SATA_1_5G:1;
888 u8 SATA_3G:1;
889 u8 reserved_0:4;
890 u8 reserved_1[6];
891 u8 port_count;
892 u64 port_addr[8];
893
894 } __attribute__ ((packed)) device_interface;
895
896 /*
897 * List of components residing in flash. All str are null terminated
898 */
9ab9ed38
CH		 899 __le32 image_check_word;
900 __le32 image_component_count;
c4a3e0a5
BS		 901
902 struct {
903
904 char name[8];
905 char version[32];
906 char build_date[16];
907 char built_time[16];
908
909 } __attribute__ ((packed)) image_component[8];
910
911 /*
912 * List of flash components that have been flashed on the card, but
913 * are not in use, pending reset of the adapter. This list will be
914 * empty if a flash operation has not occurred. All stings are null
915 * terminated
916 */
9ab9ed38 917 __le32 pending_image_component_count;
c4a3e0a5
BS		 918
919 struct {
920
921 char name[8];
922 char version[32];
923 char build_date[16];
924 char build_time[16];
925
926 } __attribute__ ((packed)) pending_image_component[8];
927
928 u8 max_arms;
929 u8 max_spans;
930 u8 max_arrays;
931 u8 max_lds;
932
933 char product_name[80];
934 char serial_no[32];
935
936 /*
937 * Other physical/controller/operation information. Indicates the
938 * presence of the hardware
939 */
940 struct {
941
942 u32 bbu:1;
943 u32 alarm:1;
944 u32 nvram:1;
945 u32 uart:1;
946 u32 reserved:28;
947
948 } __attribute__ ((packed)) hw_present;
949
9ab9ed38 950 __le32 current_fw_time;
c4a3e0a5
BS		 951
952 /*
953 * Maximum data transfer sizes
954 */
9ab9ed38
CH		 955 __le16 max_concurrent_cmds;
956 __le16 max_sge_count;
957 __le32 max_request_size;
c4a3e0a5
BS		 958
959 /*
960 * Logical and physical device counts
961 */
9ab9ed38
CH		 962 __le16 ld_present_count;
963 __le16 ld_degraded_count;
964 __le16 ld_offline_count;
c4a3e0a5 965
9ab9ed38
CH		 966 __le16 pd_present_count;
967 __le16 pd_disk_present_count;
968 __le16 pd_disk_pred_failure_count;
969 __le16 pd_disk_failed_count;
c4a3e0a5
BS		 970
971 /*
972 * Memory size information
973 */
9ab9ed38
CH		 974 __le16 nvram_size;
975 __le16 memory_size;
976 __le16 flash_size;
c4a3e0a5
BS		 977
978 /*
979 * Error counters
980 */
9ab9ed38
CH		 981 __le16 mem_correctable_error_count;
982 __le16 mem_uncorrectable_error_count;
c4a3e0a5
BS		 983
984 /*
985 * Cluster information
986 */
987 u8 cluster_permitted;
988 u8 cluster_active;
989
990 /*
991 * Additional max data transfer sizes
992 */
9ab9ed38 993 __le16 max_strips_per_io;
c4a3e0a5
BS		 994
995 /*
996 * Controller capabilities structures
997 */
998 struct {
999
1000 u32 raid_level_0:1;
1001 u32 raid_level_1:1;
1002 u32 raid_level_5:1;
1003 u32 raid_level_1E:1;
1004 u32 raid_level_6:1;
1005 u32 reserved:27;
1006
1007 } __attribute__ ((packed)) raid_levels;
1008
1009 struct {
1010
1011 u32 rbld_rate:1;
1012 u32 cc_rate:1;
1013 u32 bgi_rate:1;
1014 u32 recon_rate:1;
1015 u32 patrol_rate:1;
1016 u32 alarm_control:1;
1017 u32 cluster_supported:1;
1018 u32 bbu:1;
1019 u32 spanning_allowed:1;
1020 u32 dedicated_hotspares:1;
1021 u32 revertible_hotspares:1;
1022 u32 foreign_config_import:1;
1023 u32 self_diagnostic:1;
1024 u32 mixed_redundancy_arr:1;
1025 u32 global_hot_spares:1;
1026 u32 reserved:17;
1027
1028 } __attribute__ ((packed)) adapter_operations;
1029
1030 struct {
1031
1032 u32 read_policy:1;
1033 u32 write_policy:1;
1034 u32 io_policy:1;
1035 u32 access_policy:1;
1036 u32 disk_cache_policy:1;
1037 u32 reserved:27;
1038
1039 } __attribute__ ((packed)) ld_operations;
1040
1041 struct {
1042
1043 u8 min;
1044 u8 max;
1045 u8 reserved[2];
1046
1047 } __attribute__ ((packed)) stripe_sz_ops;
1048
1049 struct {
1050
1051 u32 force_online:1;
1052 u32 force_offline:1;
1053 u32 force_rebuild:1;
1054 u32 reserved:29;
1055
1056 } __attribute__ ((packed)) pd_operations;
1057
1058 struct {
1059
1060 u32 ctrl_supports_sas:1;
1061 u32 ctrl_supports_sata:1;
1062 u32 allow_mix_in_encl:1;
1063 u32 allow_mix_in_ld:1;
1064 u32 allow_sata_in_cluster:1;
1065 u32 reserved:27;
1066
1067 } __attribute__ ((packed)) pd_mix_support;
1068
1069 /*
1070 * Define ECC single-bit-error bucket information
1071 */
1072 u8 ecc_bucket_count;
1073 u8 reserved_2[11];
1074
1075 /*
1076 * Include the controller properties (changeable items)
1077 */
1078 struct megasas_ctrl_prop properties;
1079
1080 /*
1081 * Define FW pkg version (set in envt v'bles on OEM basis)
1082 */
1083 char package_version[0x60];
1084
c4a3e0a5 1085
bc93d425
SS		 1086 /*
1087 * If adapterOperations.supportMoreThan8Phys is set,
1088 * and deviceInterface.portCount is greater than 8,
1089 * SAS Addrs for first 8 ports shall be populated in
1090 * deviceInterface.portAddr, and the rest shall be
1091 * populated in deviceInterfacePortAddr2.
1092 */
9ab9ed38 1093 __le64 deviceInterfacePortAddr2[8]; /*6a0h */
bc93d425
SS		 1094 u8 reserved3[128]; /*6e0h */
1095
1096 struct { /*760h */
1097 u16 minPdRaidLevel_0:4;
1098 u16 maxPdRaidLevel_0:12;
1099
1100 u16 minPdRaidLevel_1:4;
1101 u16 maxPdRaidLevel_1:12;
1102
1103 u16 minPdRaidLevel_5:4;
1104 u16 maxPdRaidLevel_5:12;
1105
1106 u16 minPdRaidLevel_1E:4;
1107 u16 maxPdRaidLevel_1E:12;
1108
1109 u16 minPdRaidLevel_6:4;
1110 u16 maxPdRaidLevel_6:12;
1111
1112 u16 minPdRaidLevel_10:4;
1113 u16 maxPdRaidLevel_10:12;
1114
1115 u16 minPdRaidLevel_50:4;
1116 u16 maxPdRaidLevel_50:12;
1117
1118 u16 minPdRaidLevel_60:4;
1119 u16 maxPdRaidLevel_60:12;
1120
1121 u16 minPdRaidLevel_1E_RLQ0:4;
1122 u16 maxPdRaidLevel_1E_RLQ0:12;
1123
1124 u16 minPdRaidLevel_1E0_RLQ0:4;
1125 u16 maxPdRaidLevel_1E0_RLQ0:12;
1126
1127 u16 reserved[6];
1128 } pdsForRaidLevels;
1129
9ab9ed38
CH		 1130 __le16 maxPds; /*780h */
1131 __le16 maxDedHSPs; /*782h */
1132 __le16 maxGlobalHSP; /*784h */
1133 __le16 ddfSize; /*786h */
bc93d425
SS		 1134 u8 maxLdsPerArray; /*788h */
1135 u8 partitionsInDDF; /*789h */
1136 u8 lockKeyBinding; /*78ah */
1137 u8 maxPITsPerLd; /*78bh */
1138 u8 maxViewsPerLd; /*78ch */
1139 u8 maxTargetId; /*78dh */
9ab9ed38 1140 __le16 maxBvlVdSize; /*78eh */
bc93d425 1141
9ab9ed38
CH		 1142 __le16 maxConfigurableSSCSize; /*790h */
1143 __le16 currentSSCsize; /*792h */
bc93d425
SS		 1144
1145 char expanderFwVersion[12]; /*794h */
1146
9ab9ed38 1147 __le16 PFKTrialTimeRemaining; /*7A0h */
bc93d425 1148
9ab9ed38 1149 __le16 cacheMemorySize; /*7A2h */
bc93d425
SS		 1150
1151 struct { /*7A4h */
94cd65dd 1152#if defined(__BIG_ENDIAN_BITFIELD)
229fe47c 1153 u32 reserved:5;
1154 u32 activePassive:2;
1155 u32 supportConfigAutoBalance:1;
1156 u32 mpio:1;
1157 u32 supportDataLDonSSCArray:1;
1158 u32 supportPointInTimeProgress:1;
94cd65dd
SS		 1159 u32 supportUnevenSpans:1;
1160 u32 dedicatedHotSparesLimited:1;
1161 u32 headlessMode:1;
1162 u32 supportEmulatedDrives:1;
1163 u32 supportResetNow:1;
1164 u32 realTimeScheduler:1;
1165 u32 supportSSDPatrolRead:1;
1166 u32 supportPerfTuning:1;
1167 u32 disableOnlinePFKChange:1;
1168 u32 supportJBOD:1;
1169 u32 supportBootTimePFKChange:1;
1170 u32 supportSetLinkSpeed:1;
1171 u32 supportEmergencySpares:1;
1172 u32 supportSuspendResumeBGops:1;
1173 u32 blockSSDWriteCacheChange:1;
1174 u32 supportShieldState:1;
1175 u32 supportLdBBMInfo:1;
1176 u32 supportLdPIType3:1;
1177 u32 supportLdPIType2:1;
1178 u32 supportLdPIType1:1;
1179 u32 supportPIcontroller:1;
1180#else
bc93d425
SS		 1181 u32 supportPIcontroller:1;
1182 u32 supportLdPIType1:1;
1183 u32 supportLdPIType2:1;
1184 u32 supportLdPIType3:1;
1185 u32 supportLdBBMInfo:1;
1186 u32 supportShieldState:1;
1187 u32 blockSSDWriteCacheChange:1;
1188 u32 supportSuspendResumeBGops:1;
1189 u32 supportEmergencySpares:1;
1190 u32 supportSetLinkSpeed:1;
1191 u32 supportBootTimePFKChange:1;
1192 u32 supportJBOD:1;
1193 u32 disableOnlinePFKChange:1;
1194 u32 supportPerfTuning:1;
1195 u32 supportSSDPatrolRead:1;
1196 u32 realTimeScheduler:1;
1197
1198 u32 supportResetNow:1;
1199 u32 supportEmulatedDrives:1;
1200 u32 headlessMode:1;
1201 u32 dedicatedHotSparesLimited:1;
1202
1203
1204 u32 supportUnevenSpans:1;
229fe47c 1205 u32 supportPointInTimeProgress:1;
1206 u32 supportDataLDonSSCArray:1;
1207 u32 mpio:1;
1208 u32 supportConfigAutoBalance:1;
1209 u32 activePassive:2;
1210 u32 reserved:5;
94cd65dd 1211#endif
bc93d425
SS		 1212 } adapterOperations2;
1213
1214 u8 driverVersion[32]; /*7A8h */
1215 u8 maxDAPdCountSpinup60; /*7C8h */
1216 u8 temperatureROC; /*7C9h */
1217 u8 temperatureCtrl; /*7CAh */
1218 u8 reserved4; /*7CBh */
9ab9ed38 1219 __le16 maxConfigurablePds; /*7CCh */
bc93d425
SS		 1220
1221
1222 u8 reserved5[2]; /*0x7CDh */
1223
1224 /*
1225 * HA cluster information
1226 */
1227 struct {
51087a86
SS		 1228#if defined(__BIG_ENDIAN_BITFIELD)
1229 u32 reserved:26;
1230 u32 premiumFeatureMismatch:1;
1231 u32 ctrlPropIncompatible:1;
1232 u32 fwVersionMismatch:1;
1233 u32 hwIncompatible:1;
1234 u32 peerIsIncompatible:1;
1235 u32 peerIsPresent:1;
1236#else
bc93d425
SS		 1237 u32 peerIsPresent:1;
1238 u32 peerIsIncompatible:1;
1239 u32 hwIncompatible:1;
1240 u32 fwVersionMismatch:1;
1241 u32 ctrlPropIncompatible:1;
1242 u32 premiumFeatureMismatch:1;
1243 u32 reserved:26;
51087a86 1244#endif
bc93d425
SS		 1245 } cluster;
1246
1247 char clusterId[16]; /*7D4h */
229fe47c 1248 struct {
1249 u8 maxVFsSupported; /*0x7E4*/
1250 u8 numVFsEnabled; /*0x7E5*/
1251 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/
1252 u8 reserved; /*0x7E7*/
1253 } iov;
bc93d425 1254
fc62b3fc
SS		 1255 struct {
1256#if defined(__BIG_ENDIAN_BITFIELD)
3761cb4c 1257 u32 reserved:7;
1258 u32 useSeqNumJbodFP:1;
0be3f4c9 1259 u32 supportExtendedSSCSize:1;
1260 u32 supportDiskCacheSettingForSysPDs:1;
1261 u32 supportCPLDUpdate:1;
1262 u32 supportTTYLogCompression:1;
7497cde8
SS		 1263 u32 discardCacheDuringLDDelete:1;
1264 u32 supportSecurityonJBOD:1;
1265 u32 supportCacheBypassModes:1;
1266 u32 supportDisableSESMonitoring:1;
1267 u32 supportForceFlash:1;
1268 u32 supportNVDRAM:1;
1269 u32 supportDrvActivityLEDSetting:1;
1270 u32 supportAllowedOpsforDrvRemoval:1;
1271 u32 supportHOQRebuild:1;
1272 u32 supportForceTo512e:1;
1273 u32 supportNVCacheErase:1;
1274 u32 supportDebugQueue:1;
1275 u32 supportSwZone:1;
fc62b3fc 1276 u32 supportCrashDump:1;
51087a86
SS		 1277 u32 supportMaxExtLDs:1;
1278 u32 supportT10RebuildAssist:1;
1279 u32 supportDisableImmediateIO:1;
1280 u32 supportThermalPollInterval:1;
1281 u32 supportPersonalityChange:2;
fc62b3fc 1282#else
51087a86
SS		 1283 u32 supportPersonalityChange:2;
1284 u32 supportThermalPollInterval:1;
1285 u32 supportDisableImmediateIO:1;
1286 u32 supportT10RebuildAssist:1;
7497cde8
SS		 1287 u32 supportMaxExtLDs:1;
1288 u32 supportCrashDump:1;
1289 u32 supportSwZone:1;
1290 u32 supportDebugQueue:1;
1291 u32 supportNVCacheErase:1;
1292 u32 supportForceTo512e:1;
1293 u32 supportHOQRebuild:1;
1294 u32 supportAllowedOpsforDrvRemoval:1;
1295 u32 supportDrvActivityLEDSetting:1;
1296 u32 supportNVDRAM:1;
1297 u32 supportForceFlash:1;
1298 u32 supportDisableSESMonitoring:1;
1299 u32 supportCacheBypassModes:1;
1300 u32 supportSecurityonJBOD:1;
1301 u32 discardCacheDuringLDDelete:1;
0be3f4c9 1302 u32 supportTTYLogCompression:1;
1303 u32 supportCPLDUpdate:1;
1304 u32 supportDiskCacheSettingForSysPDs:1;
1305 u32 supportExtendedSSCSize:1;
3761cb4c 1306 u32 useSeqNumJbodFP:1;
1307 u32 reserved:7;
fc62b3fc
SS		 1308#endif
1309 } adapterOperations3;
1310
1311 u8 pad[0x800-0x7EC];
81e403ce 1312} __packed;
c4a3e0a5
BS		 1313
1314/*
1315 * ===============================
1316 * MegaRAID SAS driver definitions
1317 * ===============================
1318 */
1319#define MEGASAS_MAX_PD_CHANNELS 2
51087a86 1320#define MEGASAS_MAX_LD_CHANNELS 2
c4a3e0a5
BS		 1321#define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
1322 MEGASAS_MAX_LD_CHANNELS)
1323#define MEGASAS_MAX_DEV_PER_CHANNEL 128
1324#define MEGASAS_DEFAULT_INIT_ID -1
1325#define MEGASAS_MAX_LUN 8
6bf579a3 1326#define MEGASAS_DEFAULT_CMD_PER_LUN 256
81e403ce
YB		 1327#define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
1328 MEGASAS_MAX_DEV_PER_CHANNEL)
bdc6fb8d
YB		 1329#define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
1330 MEGASAS_MAX_DEV_PER_CHANNEL)
c4a3e0a5 1331
1fd10685 1332#define MEGASAS_MAX_SECTORS (2*1024)
42a8d2b3 1333#define MEGASAS_MAX_SECTORS_IEEE (2*128)
658dcedb
SP		 1334#define MEGASAS_DBG_LVL 1
1335
05e9ebbe
SP		 1336#define MEGASAS_FW_BUSY 1
1337
51087a86
SS		 1338#define VD_EXT_DEBUG 0
1339
11c71cb4
SS		 1340#define SCAN_PD_CHANNEL 0x1
1341#define SCAN_VD_CHANNEL 0x2
90dc9d98 1342
7497cde8
SS		 1343enum MR_SCSI_CMD_TYPE {
1344 READ_WRITE_LDIO = 0,
1345 NON_READ_WRITE_LDIO = 1,
1346 READ_WRITE_SYSPDIO = 2,
1347 NON_READ_WRITE_SYSPDIO = 3,
1348};
1349
6d40afbc
SS		 1350enum DCMD_TIMEOUT_ACTION {
1351 INITIATE_OCR = 0,
1352 KILL_ADAPTER = 1,
1353 IGNORE_TIMEOUT = 2,
1354};
d532dbe2 1355/* Frame Type */
1356#define IO_FRAME 0
1357#define PTHRU_FRAME 1
1358
c4a3e0a5
BS		 1359/*
1360 * When SCSI mid-layer calls driver's reset routine, driver waits for
1361 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1362 * that the driver cannot _actually_ abort or reset pending commands. While
1363 * it is waiting for the commands to complete, it prints a diagnostic message
1364 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1365 */
1366#define MEGASAS_RESET_WAIT_TIME 180
2a3681e5 1367#define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
c4a3e0a5 1368#define MEGASAS_RESET_NOTICE_INTERVAL 5
c4a3e0a5 1369#define MEGASAS_IOCTL_CMD 0
05e9ebbe 1370#define MEGASAS_DEFAULT_CMD_TIMEOUT 90
c5daa6a9 1371#define MEGASAS_THROTTLE_QUEUE_DEPTH 16
90dc9d98 1372#define MEGASAS_BLOCKED_CMD_TIMEOUT 60
c4a3e0a5
BS		 1373/*
1374 * FW reports the maximum of number of commands that it can accept (maximum
1375 * commands that can be outstanding) at any time. The driver must report a
1376 * lower number to the mid layer because it can issue a few internal commands
1377 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1378 * is shown below
1379 */
1380#define MEGASAS_INT_CMDS 32
7bebf5c7 1381#define MEGASAS_SKINNY_INT_CMDS 5
ae09a6c1
SS		 1382#define MEGASAS_FUSION_INTERNAL_CMDS 5
1383#define MEGASAS_FUSION_IOCTL_CMDS 3
f26ac3a1 1384#define MEGASAS_MFI_IOCTL_CMDS 27
c4a3e0a5 1385
d46a3ad6 1386#define MEGASAS_MAX_MSIX_QUEUES 128
c4a3e0a5
BS		 1387/*
1388 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1389 * SGLs based on the size of dma_addr_t
1390 */
1391#define IS_DMA64 (sizeof(dma_addr_t) == 8)
1392
39a98554 1393#define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
1394
1395#define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
1396#define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
1397#define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
1398
c4a3e0a5 1399#define MFI_OB_INTR_STATUS_MASK 0x00000002
14faea9f 1400#define MFI_POLL_TIMEOUT_SECS 60
6d40afbc 1401#define MFI_IO_TIMEOUT_SECS 180
229fe47c 1402#define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ)
1403#define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30)
1404#define MEGASAS_ROUTINE_WAIT_TIME_VF 300
f9876f0b 1405#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
6610a6b3
YB		 1406#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
1407#define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
87911122
YB		 1408#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
1409#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
0e98936c 1410
39a98554 1411#define MFI_1068_PCSR_OFFSET 0x84
1412#define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
1413#define MFI_1068_FW_READY 0xDDDD0000
d46a3ad6
SS		 1414
1415#define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
1416#define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
1417#define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
1418#define MR_MAX_MSIX_REG_ARRAY 16
0e98936c
SP		 1419/*
1420* register set for both 1068 and 1078 controllers
1421* structure extended for 1078 registers
1422*/
f9876f0b 1423
c4a3e0a5 1424struct megasas_register_set {
9c915a8c 1425 u32 doorbell; /*0000h*/
1426 u32 fusion_seq_offset; /*0004h*/
1427 u32 fusion_host_diag; /*0008h*/
1428 u32 reserved_01; /*000Ch*/
c4a3e0a5 1429
f9876f0b
SP		 1430 u32 inbound_msg_0; /*0010h*/
1431 u32 inbound_msg_1; /*0014h*/
1432 u32 outbound_msg_0; /*0018h*/
1433 u32 outbound_msg_1; /*001Ch*/
c4a3e0a5 1434
f9876f0b
SP		 1435 u32 inbound_doorbell; /*0020h*/
1436 u32 inbound_intr_status; /*0024h*/
1437 u32 inbound_intr_mask; /*0028h*/
c4a3e0a5 1438
f9876f0b
SP		 1439 u32 outbound_doorbell; /*002Ch*/
1440 u32 outbound_intr_status; /*0030h*/
1441 u32 outbound_intr_mask; /*0034h*/
c4a3e0a5 1442
f9876f0b 1443 u32 reserved_1[2]; /*0038h*/
c4a3e0a5 1444
f9876f0b
SP		 1445 u32 inbound_queue_port; /*0040h*/
1446 u32 outbound_queue_port; /*0044h*/
c4a3e0a5 1447
9c915a8c 1448 u32 reserved_2[9]; /*0048h*/
1449 u32 reply_post_host_index; /*006Ch*/
1450 u32 reserved_2_2[12]; /*0070h*/
c4a3e0a5 1451
f9876f0b 1452 u32 outbound_doorbell_clear; /*00A0h*/
c4a3e0a5 1453
f9876f0b
SP		 1454 u32 reserved_3[3]; /*00A4h*/
1455
1456 u32 outbound_scratch_pad ; /*00B0h*/
9c915a8c 1457 u32 outbound_scratch_pad_2; /*00B4h*/
f9876f0b 1458
9c915a8c 1459 u32 reserved_4[2]; /*00B8h*/
f9876f0b
SP		 1460
1461 u32 inbound_low_queue_port ; /*00C0h*/
1462
1463 u32 inbound_high_queue_port ; /*00C4h*/
1464
1465 u32 reserved_5; /*00C8h*/
39a98554 1466 u32 res_6[11]; /*CCh*/
1467 u32 host_diag;
1468 u32 seq_offset;
1469 u32 index_registers[807]; /*00CCh*/
c4a3e0a5
BS		 1470} __attribute__ ((packed));
1471
1472struct megasas_sge32 {
1473
9ab9ed38
CH		 1474 __le32 phys_addr;
1475 __le32 length;
c4a3e0a5
BS		 1476
1477} __attribute__ ((packed));
1478
1479struct megasas_sge64 {
1480
9ab9ed38
CH		 1481 __le64 phys_addr;
1482 __le32 length;
c4a3e0a5
BS		 1483
1484} __attribute__ ((packed));
1485
f4c9a131 1486struct megasas_sge_skinny {
9ab9ed38
CH		 1487 __le64 phys_addr;
1488 __le32 length;
1489 __le32 flag;
f4c9a131
YB		 1490} __packed;
1491
c4a3e0a5
BS		 1492union megasas_sgl {
1493
1494 struct megasas_sge32 sge32[1];
1495 struct megasas_sge64 sge64[1];
f4c9a131 1496 struct megasas_sge_skinny sge_skinny[1];
c4a3e0a5
BS		 1497
1498} __attribute__ ((packed));
1499
1500struct megasas_header {
1501
1502 u8 cmd; /*00h */
1503 u8 sense_len; /*01h */
1504 u8 cmd_status; /*02h */
1505 u8 scsi_status; /*03h */
1506
1507 u8 target_id; /*04h */
1508 u8 lun; /*05h */
1509 u8 cdb_len; /*06h */
1510 u8 sge_count; /*07h */
1511
9ab9ed38
CH		 1512 __le32 context; /*08h */
1513 __le32 pad_0; /*0Ch */
c4a3e0a5 1514
9ab9ed38
CH		 1515 __le16 flags; /*10h */
1516 __le16 timeout; /*12h */
1517 __le32 data_xferlen; /*14h */
c4a3e0a5
BS		 1518
1519} __attribute__ ((packed));
1520
1521union megasas_sgl_frame {
1522
1523 struct megasas_sge32 sge32[8];
1524 struct megasas_sge64 sge64[5];
1525
1526} __attribute__ ((packed));
1527
d46a3ad6
SS		 1528typedef union _MFI_CAPABILITIES {
1529 struct {
94cd65dd 1530#if defined(__BIG_ENDIAN_BITFIELD)
bd5f9484 1531 u32 reserved:23;
1532 u32 support_ext_io_size:1;
0be3f4c9 1533 u32 support_ext_queue_depth:1;
7497cde8
SS		 1534 u32 security_protocol_cmds_fw:1;
1535 u32 support_core_affinity:1;
d2552ebe 1536 u32 support_ndrive_r1_lb:1;
51087a86 1537 u32 support_max_255lds:1;
7497cde8 1538 u32 support_fastpath_wb:1;
94cd65dd
SS		 1539 u32 support_additional_msix:1;
1540 u32 support_fp_remote_lun:1;
1541#else
d46a3ad6
SS		 1542 u32 support_fp_remote_lun:1;
1543 u32 support_additional_msix:1;
7497cde8 1544 u32 support_fastpath_wb:1;
51087a86 1545 u32 support_max_255lds:1;
d2552ebe 1546 u32 support_ndrive_r1_lb:1;
7497cde8
SS		 1547 u32 support_core_affinity:1;
1548 u32 security_protocol_cmds_fw:1;
0be3f4c9 1549 u32 support_ext_queue_depth:1;
bd5f9484 1550 u32 support_ext_io_size:1;
1551 u32 reserved:23;
94cd65dd 1552#endif
d46a3ad6 1553 } mfi_capabilities;
9ab9ed38 1554 __le32 reg;
d46a3ad6
SS		 1555} MFI_CAPABILITIES;
1556
c4a3e0a5
BS		 1557struct megasas_init_frame {
1558
1559 u8 cmd; /*00h */
1560 u8 reserved_0; /*01h */
1561 u8 cmd_status; /*02h */
1562
1563 u8 reserved_1; /*03h */
d46a3ad6 1564 MFI_CAPABILITIES driver_operations; /*04h*/
c4a3e0a5 1565
9ab9ed38
CH		 1566 __le32 context; /*08h */
1567 __le32 pad_0; /*0Ch */
c4a3e0a5 1568
9ab9ed38
CH		 1569 __le16 flags; /*10h */
1570 __le16 reserved_3; /*12h */
1571 __le32 data_xfer_len; /*14h */
c4a3e0a5 1572
9ab9ed38
CH		 1573 __le32 queue_info_new_phys_addr_lo; /*18h */
1574 __le32 queue_info_new_phys_addr_hi; /*1Ch */
1575 __le32 queue_info_old_phys_addr_lo; /*20h */
1576 __le32 queue_info_old_phys_addr_hi; /*24h */
1577 __le32 reserved_4[2]; /*28h */
1578 __le32 system_info_lo; /*30h */
1579 __le32 system_info_hi; /*34h */
1580 __le32 reserved_5[2]; /*38h */
c4a3e0a5
BS		 1581
1582} __attribute__ ((packed));
1583
1584struct megasas_init_queue_info {
1585
9ab9ed38
CH		 1586 __le32 init_flags; /*00h */
1587 __le32 reply_queue_entries; /*04h */
c4a3e0a5 1588
9ab9ed38
CH		 1589 __le32 reply_queue_start_phys_addr_lo; /*08h */
1590 __le32 reply_queue_start_phys_addr_hi; /*0Ch */
1591 __le32 producer_index_phys_addr_lo; /*10h */
1592 __le32 producer_index_phys_addr_hi; /*14h */
1593 __le32 consumer_index_phys_addr_lo; /*18h */
1594 __le32 consumer_index_phys_addr_hi; /*1Ch */
c4a3e0a5
BS		 1595
1596} __attribute__ ((packed));
1597
1598struct megasas_io_frame {
1599
1600 u8 cmd; /*00h */
1601 u8 sense_len; /*01h */
1602 u8 cmd_status; /*02h */
1603 u8 scsi_status; /*03h */
1604
1605 u8 target_id; /*04h */
1606 u8 access_byte; /*05h */
1607 u8 reserved_0; /*06h */
1608 u8 sge_count; /*07h */
1609
9ab9ed38
CH		 1610 __le32 context; /*08h */
1611 __le32 pad_0; /*0Ch */
c4a3e0a5 1612
9ab9ed38
CH		 1613 __le16 flags; /*10h */
1614 __le16 timeout; /*12h */
1615 __le32 lba_count; /*14h */
c4a3e0a5 1616
9ab9ed38
CH		 1617 __le32 sense_buf_phys_addr_lo; /*18h */
1618 __le32 sense_buf_phys_addr_hi; /*1Ch */
c4a3e0a5 1619
9ab9ed38
CH		 1620 __le32 start_lba_lo; /*20h */
1621 __le32 start_lba_hi; /*24h */
c4a3e0a5
BS		 1622
1623 union megasas_sgl sgl; /*28h */
1624
1625} __attribute__ ((packed));
1626
1627struct megasas_pthru_frame {
1628
1629 u8 cmd; /*00h */
1630 u8 sense_len; /*01h */
1631 u8 cmd_status; /*02h */
1632 u8 scsi_status; /*03h */
1633
1634 u8 target_id; /*04h */
1635 u8 lun; /*05h */
1636 u8 cdb_len; /*06h */
1637 u8 sge_count; /*07h */
1638
9ab9ed38
CH		 1639 __le32 context; /*08h */
1640 __le32 pad_0; /*0Ch */
c4a3e0a5 1641
9ab9ed38
CH		 1642 __le16 flags; /*10h */
1643 __le16 timeout; /*12h */
1644 __le32 data_xfer_len; /*14h */
c4a3e0a5 1645
9ab9ed38
CH		 1646 __le32 sense_buf_phys_addr_lo; /*18h */
1647 __le32 sense_buf_phys_addr_hi; /*1Ch */
c4a3e0a5
BS		 1648
1649 u8 cdb[16]; /*20h */
1650 union megasas_sgl sgl; /*30h */
1651
1652} __attribute__ ((packed));
1653
1654struct megasas_dcmd_frame {
1655
1656 u8 cmd; /*00h */
1657 u8 reserved_0; /*01h */
1658 u8 cmd_status; /*02h */
1659 u8 reserved_1[4]; /*03h */
1660 u8 sge_count; /*07h */
1661
9ab9ed38
CH		 1662 __le32 context; /*08h */
1663 __le32 pad_0; /*0Ch */
c4a3e0a5 1664
9ab9ed38
CH		 1665 __le16 flags; /*10h */
1666 __le16 timeout; /*12h */
c4a3e0a5 1667
9ab9ed38
CH		 1668 __le32 data_xfer_len; /*14h */
1669 __le32 opcode; /*18h */
c4a3e0a5
BS		 1670
1671 union { /*1Ch */
1672 u8 b[12];
9ab9ed38
CH		 1673 __le16 s[6];
1674 __le32 w[3];
c4a3e0a5
BS		 1675 } mbox;
1676
1677 union megasas_sgl sgl; /*28h */
1678
1679} __attribute__ ((packed));
1680
1681struct megasas_abort_frame {
1682
1683 u8 cmd; /*00h */
1684 u8 reserved_0; /*01h */
1685 u8 cmd_status; /*02h */
1686
1687 u8 reserved_1; /*03h */
9ab9ed38 1688 __le32 reserved_2; /*04h */
c4a3e0a5 1689
9ab9ed38
CH		 1690 __le32 context; /*08h */
1691 __le32 pad_0; /*0Ch */
c4a3e0a5 1692
9ab9ed38
CH		 1693 __le16 flags; /*10h */
1694 __le16 reserved_3; /*12h */
1695 __le32 reserved_4; /*14h */
c4a3e0a5 1696
9ab9ed38
CH		 1697 __le32 abort_context; /*18h */
1698 __le32 pad_1; /*1Ch */
c4a3e0a5 1699
9ab9ed38
CH		 1700 __le32 abort_mfi_phys_addr_lo; /*20h */
1701 __le32 abort_mfi_phys_addr_hi; /*24h */
c4a3e0a5 1702
9ab9ed38 1703 __le32 reserved_5[6]; /*28h */
c4a3e0a5
BS		 1704
1705} __attribute__ ((packed));
1706
1707struct megasas_smp_frame {
1708
1709 u8 cmd; /*00h */
1710 u8 reserved_1; /*01h */
1711 u8 cmd_status; /*02h */
1712 u8 connection_status; /*03h */
1713
1714 u8 reserved_2[3]; /*04h */
1715 u8 sge_count; /*07h */
1716
9ab9ed38
CH		 1717 __le32 context; /*08h */
1718 __le32 pad_0; /*0Ch */
c4a3e0a5 1719
9ab9ed38
CH		 1720 __le16 flags; /*10h */
1721 __le16 timeout; /*12h */
c4a3e0a5 1722
9ab9ed38
CH		 1723 __le32 data_xfer_len; /*14h */
1724 __le64 sas_addr; /*18h */
c4a3e0a5
BS		 1725
1726 union {
1727 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1728 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1729 } sgl;
1730
1731} __attribute__ ((packed));
1732
1733struct megasas_stp_frame {
1734
1735 u8 cmd; /*00h */
1736 u8 reserved_1; /*01h */
1737 u8 cmd_status; /*02h */
1738 u8 reserved_2; /*03h */
1739
1740 u8 target_id; /*04h */
1741 u8 reserved_3[2]; /*05h */
1742 u8 sge_count; /*07h */
1743
9ab9ed38
CH		 1744 __le32 context; /*08h */
1745 __le32 pad_0; /*0Ch */
c4a3e0a5 1746
9ab9ed38
CH		 1747 __le16 flags; /*10h */
1748 __le16 timeout; /*12h */
c4a3e0a5 1749
9ab9ed38 1750 __le32 data_xfer_len; /*14h */
c4a3e0a5 1751
9ab9ed38
CH		 1752 __le16 fis[10]; /*18h */
1753 __le32 stp_flags;
c4a3e0a5
BS		 1754
1755 union {
1756 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1757 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1758 } sgl;
1759
1760} __attribute__ ((packed));
1761
1762union megasas_frame {
1763
1764 struct megasas_header hdr;
1765 struct megasas_init_frame init;
1766 struct megasas_io_frame io;
1767 struct megasas_pthru_frame pthru;
1768 struct megasas_dcmd_frame dcmd;
1769 struct megasas_abort_frame abort;
1770 struct megasas_smp_frame smp;
1771 struct megasas_stp_frame stp;
1772
1773 u8 raw_bytes[64];
1774};
1775
18365b13
SS		 1776/**
1777 * struct MR_PRIV_DEVICE - sdev private hostdata
1778 * @is_tm_capable: firmware managed tm_capable flag
1779 * @tm_busy: TM request is in progress
1780 */
1781struct MR_PRIV_DEVICE {
1782 bool is_tm_capable;
1783 bool tm_busy;
1784};
c4a3e0a5
BS		 1785struct megasas_cmd;
1786
1787union megasas_evt_class_locale {
1788
1789 struct {
be26374b 1790#ifndef __BIG_ENDIAN_BITFIELD
c4a3e0a5
BS		 1791 u16 locale;
1792 u8 reserved;
1793 s8 class;
be26374b
SS		 1794#else
1795 s8 class;
1796 u8 reserved;
1797 u16 locale;
1798#endif
c4a3e0a5
BS		 1799 } __attribute__ ((packed)) members;
1800
1801 u32 word;
1802
1803} __attribute__ ((packed));
1804
1805struct megasas_evt_log_info {
9ab9ed38
CH		 1806 __le32 newest_seq_num;
1807 __le32 oldest_seq_num;
1808 __le32 clear_seq_num;
1809 __le32 shutdown_seq_num;
1810 __le32 boot_seq_num;
c4a3e0a5
BS		 1811
1812} __attribute__ ((packed));
1813
1814struct megasas_progress {
1815
9ab9ed38
CH		 1816 __le16 progress;
1817 __le16 elapsed_seconds;
c4a3e0a5
BS		 1818
1819} __attribute__ ((packed));
1820
1821struct megasas_evtarg_ld {
1822
1823 u16 target_id;
1824 u8 ld_index;
1825 u8 reserved;
1826
1827} __attribute__ ((packed));
1828
1829struct megasas_evtarg_pd {
1830 u16 device_id;
1831 u8 encl_index;
1832 u8 slot_number;
1833
1834} __attribute__ ((packed));
1835
1836struct megasas_evt_detail {
1837
9ab9ed38
CH		 1838 __le32 seq_num;
1839 __le32 time_stamp;
1840 __le32 code;
c4a3e0a5
BS		 1841 union megasas_evt_class_locale cl;
1842 u8 arg_type;
1843 u8 reserved1[15];
1844
1845 union {
1846 struct {
1847 struct megasas_evtarg_pd pd;
1848 u8 cdb_length;
1849 u8 sense_length;
1850 u8 reserved[2];
1851 u8 cdb[16];
1852 u8 sense[64];
1853 } __attribute__ ((packed)) cdbSense;
1854
1855 struct megasas_evtarg_ld ld;
1856
1857 struct {
1858 struct megasas_evtarg_ld ld;
9ab9ed38 1859 __le64 count;
c4a3e0a5
BS		 1860 } __attribute__ ((packed)) ld_count;
1861
1862 struct {
9ab9ed38 1863 __le64 lba;
c4a3e0a5
BS		 1864 struct megasas_evtarg_ld ld;
1865 } __attribute__ ((packed)) ld_lba;
1866
1867 struct {
1868 struct megasas_evtarg_ld ld;
9ab9ed38
CH		 1869 __le32 prevOwner;
1870 __le32 newOwner;
c4a3e0a5
BS		 1871 } __attribute__ ((packed)) ld_owner;
1872
1873 struct {
1874 u64 ld_lba;
1875 u64 pd_lba;
1876 struct megasas_evtarg_ld ld;
1877 struct megasas_evtarg_pd pd;
1878 } __attribute__ ((packed)) ld_lba_pd_lba;
1879
1880 struct {
1881 struct megasas_evtarg_ld ld;
1882 struct megasas_progress prog;
1883 } __attribute__ ((packed)) ld_prog;
1884
1885 struct {
1886 struct megasas_evtarg_ld ld;
1887 u32 prev_state;
1888 u32 new_state;
1889 } __attribute__ ((packed)) ld_state;
1890
1891 struct {
1892 u64 strip;
1893 struct megasas_evtarg_ld ld;
1894 } __attribute__ ((packed)) ld_strip;
1895
1896 struct megasas_evtarg_pd pd;
1897
1898 struct {
1899 struct megasas_evtarg_pd pd;
1900 u32 err;
1901 } __attribute__ ((packed)) pd_err;
1902
1903 struct {
1904 u64 lba;
1905 struct megasas_evtarg_pd pd;
1906 } __attribute__ ((packed)) pd_lba;
1907
1908 struct {
1909 u64 lba;
1910 struct megasas_evtarg_pd pd;
1911 struct megasas_evtarg_ld ld;
1912 } __attribute__ ((packed)) pd_lba_ld;
1913
1914 struct {
1915 struct megasas_evtarg_pd pd;
1916 struct megasas_progress prog;
1917 } __attribute__ ((packed)) pd_prog;
1918
1919 struct {
1920 struct megasas_evtarg_pd pd;
1921 u32 prevState;
1922 u32 newState;
1923 } __attribute__ ((packed)) pd_state;
1924
1925 struct {
1926 u16 vendorId;
9ab9ed38 1927 __le16 deviceId;
c4a3e0a5
BS		 1928 u16 subVendorId;
1929 u16 subDeviceId;
1930 } __attribute__ ((packed)) pci;
1931
1932 u32 rate;
1933 char str[96];
1934
1935 struct {
1936 u32 rtc;
1937 u32 elapsedSeconds;
1938 } __attribute__ ((packed)) time;
1939
1940 struct {
1941 u32 ecar;
1942 u32 elog;
1943 char str[64];
1944 } __attribute__ ((packed)) ecc;
1945
1946 u8 b[96];
9ab9ed38
CH		 1947 __le16 s[48];
1948 __le32 w[24];
1949 __le64 d[12];
c4a3e0a5
BS		 1950 } args;
1951
1952 char description[128];
1953
1954} __attribute__ ((packed));
1955
7e8a75f4 1956struct megasas_aen_event {
c1d390d8 1957 struct delayed_work hotplug_work;
7e8a75f4
YB		 1958 struct megasas_instance *instance;
1959};
1960
c8e858fe 1961struct megasas_irq_context {
1962 struct megasas_instance *instance;
1963 u32 MSIxIndex;
1964};
1965
5765c5b8
SS		 1966struct MR_DRV_SYSTEM_INFO {
1967 u8 infoVersion;
1968 u8 systemIdLength;
1969 u16 reserved0;
1970 u8 systemId[64];
1971 u8 reserved[1980];
1972};
1973
2216c305
SS		 1974enum MR_PD_TYPE {
1975 UNKNOWN_DRIVE = 0,
1976 PARALLEL_SCSI = 1,
1977 SAS_PD = 2,
1978 SATA_PD = 3,
1979 FC_PD = 4,
1980};
1981
1982/* JBOD Queue depth definitions */
1983#define MEGASAS_SATA_QD 32
1984#define MEGASAS_SAS_QD 64
1985#define MEGASAS_DEFAULT_PD_QD 64
1986
c4a3e0a5
BS		 1987struct megasas_instance {
1988
9ab9ed38 1989 __le32 *producer;
c4a3e0a5 1990 dma_addr_t producer_h;
9ab9ed38 1991 __le32 *consumer;
c4a3e0a5 1992 dma_addr_t consumer_h;
5765c5b8
SS		 1993 struct MR_DRV_SYSTEM_INFO *system_info_buf;
1994 dma_addr_t system_info_h;
229fe47c 1995 struct MR_LD_VF_AFFILIATION *vf_affiliation;
1996 dma_addr_t vf_affiliation_h;
1997 struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
1998 dma_addr_t vf_affiliation_111_h;
1999 struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
2000 dma_addr_t hb_host_mem_h;
2216c305
SS		 2001 struct MR_PD_INFO *pd_info;
2002 dma_addr_t pd_info_h;
c4a3e0a5 2003
9ab9ed38 2004 __le32 *reply_queue;
c4a3e0a5
BS		 2005 dma_addr_t reply_queue_h;
2006
fc62b3fc
SS		 2007 u32 *crash_dump_buf;
2008 dma_addr_t crash_dump_h;
2009 void *crash_buf[MAX_CRASH_DUMP_SIZE];
2010 u32 crash_buf_pages;
2011 unsigned int fw_crash_buffer_size;
2012 unsigned int fw_crash_state;
2013 unsigned int fw_crash_buffer_offset;
2014 u32 drv_buf_index;
2015 u32 drv_buf_alloc;
2016 u32 crash_dump_fw_support;
2017 u32 crash_dump_drv_support;
2018 u32 crash_dump_app_support;
7497cde8 2019 u32 secure_jbod_support;
3761cb4c 2020 bool use_seqnum_jbod_fp; /* Added for PD sequence */
fc62b3fc
SS		 2021 spinlock_t crashdump_lock;
2022
c4a3e0a5 2023 struct megasas_register_set __iomem *reg_set;
8a232bb3 2024 u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
81e403ce 2025 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
999ece0a 2026 struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD];
7497cde8 2027 u8 ld_ids[MEGASAS_MAX_LD_IDS];
c4a3e0a5 2028 s8 init_id;
c4a3e0a5
BS		 2029
2030 u16 max_num_sge;
2031 u16 max_fw_cmds;
9c915a8c 2032 u16 max_mfi_cmds;
ae09a6c1 2033 u16 max_scsi_cmds;
c4a3e0a5 2034 u32 max_sectors_per_req;
7e8a75f4 2035 struct megasas_aen_event *ev;
c4a3e0a5
BS		 2036
2037 struct megasas_cmd **cmd_list;
2038 struct list_head cmd_pool;
39a98554 2039 /* used to sync fire the cmd to fw */
90dc9d98 2040 spinlock_t mfi_pool_lock;
39a98554 2041 /* used to sync fire the cmd to fw */
2042 spinlock_t hba_lock;
7343eb65 2043 /* used to synch producer, consumer ptrs in dpc */
2044 spinlock_t completion_lock;
c4a3e0a5
BS		 2045 struct dma_pool *frame_dma_pool;
2046 struct dma_pool *sense_dma_pool;
2047
2048 struct megasas_evt_detail *evt_detail;
2049 dma_addr_t evt_detail_h;
2050 struct megasas_cmd *aen_cmd;
2216c305 2051 struct mutex hba_mutex;
c4a3e0a5
BS		 2052 struct semaphore ioctl_sem;
2053
2054 struct Scsi_Host *host;
2055
2056 wait_queue_head_t int_cmd_wait_q;
2057 wait_queue_head_t abort_cmd_wait_q;
2058
2059 struct pci_dev *pdev;
2060 u32 unique_id;
39a98554 2061 u32 fw_support_ieee;
c4a3e0a5 2062
e4a082c7 2063 atomic_t fw_outstanding;
39a98554 2064 atomic_t fw_reset_no_pci_access;
1341c939
SP		 2065
2066 struct megasas_instance_template *instancet;
5d018ad0 2067 struct tasklet_struct isr_tasklet;
39a98554 2068 struct work_struct work_init;
fc62b3fc 2069 struct work_struct crash_init;
05e9ebbe
SP		 2070
2071 u8 flag;
c3518837 2072 u8 unload;
f4c9a131 2073 u8 flag_ieee;
39a98554 2074 u8 issuepend_done;
2075 u8 disableOnlineCtrlReset;
bc93d425 2076 u8 UnevenSpanSupport;
51087a86
SS		 2077
2078 u8 supportmax256vd;
aed335ee 2079 u8 allow_fw_scan;
51087a86
SS		 2080 u16 fw_supported_vd_count;
2081 u16 fw_supported_pd_count;
2082
2083 u16 drv_supported_vd_count;
2084 u16 drv_supported_pd_count;
2085
39a98554 2086 u8 adprecovery;
05e9ebbe 2087 unsigned long last_time;
39a98554 2088 u32 mfiStatus;
2089 u32 last_seq_num;
ad84db2e 2090
39a98554 2091 struct list_head internal_reset_pending_q;
80d9da98 2092
25985edc 2093 /* Ptr to hba specific information */
9c915a8c 2094 void *ctrl_context;
51087a86
SS		 2095 u32 ctrl_context_pages;
2096 struct megasas_ctrl_info *ctrl_info;
c8e858fe 2097 unsigned int msix_vectors;
2098 struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES];
2099 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
9c915a8c 2100 u64 map_id;
3761cb4c 2101 u64 pd_seq_map_id;
9c915a8c 2102 struct megasas_cmd *map_update_cmd;
3761cb4c 2103 struct megasas_cmd *jbod_seq_cmd;
b6d5d880 2104 unsigned long bar;
9c915a8c 2105 long reset_flags;
2106 struct mutex reset_mutex;
229fe47c 2107 struct timer_list sriov_heartbeat_timer;
2108 char skip_heartbeat_timer_del;
2109 u8 requestorId;
229fe47c 2110 char PlasmaFW111;
2111 char mpio;
ae09a6c1 2112 u16 throttlequeuedepth;
d46a3ad6 2113 u8 mask_interrupts;
bd5f9484 2114 u16 max_chain_frame_sz;
404a8a1a 2115 u8 is_imr;
5765c5b8 2116 bool dev_handle;
39a98554 2117};
229fe47c 2118struct MR_LD_VF_MAP {
2119 u32 size;
2120 union MR_LD_REF ref;
2121 u8 ldVfCount;
2122 u8 reserved[6];
2123 u8 policy[1];
2124};
2125
2126struct MR_LD_VF_AFFILIATION {
2127 u32 size;
2128 u8 ldCount;
2129 u8 vfCount;
2130 u8 thisVf;
2131 u8 reserved[9];
2132 struct MR_LD_VF_MAP map[1];
2133};
2134
2135/* Plasma 1.11 FW backward compatibility structures */
2136#define IOV_111_OFFSET 0x7CE
2137#define MAX_VIRTUAL_FUNCTIONS 8
4cbfea88 2138#define MR_LD_ACCESS_HIDDEN 15
229fe47c 2139
2140struct IOV_111 {
2141 u8 maxVFsSupported;
2142 u8 numVFsEnabled;
2143 u8 requestorId;
2144 u8 reserved[5];
2145};
2146
2147struct MR_LD_VF_MAP_111 {
2148 u8 targetId;
2149 u8 reserved[3];
2150 u8 policy[MAX_VIRTUAL_FUNCTIONS];
2151};
2152
2153struct MR_LD_VF_AFFILIATION_111 {
2154 u8 vdCount;
2155 u8 vfCount;
2156 u8 thisVf;
2157 u8 reserved[5];
2158 struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
2159};
2160
2161struct MR_CTRL_HB_HOST_MEM {
2162 struct {
2163 u32 fwCounter; /* Firmware heart beat counter */
2164 struct {
2165 u32 debugmode:1; /* 1=Firmware is in debug mode.
2166 Heart beat will not be updated. */
2167 u32 reserved:31;
2168 } debug;
2169 u32 reserved_fw[6];
2170 u32 driverCounter; /* Driver heart beat counter. 0x20 */
2171 u32 reserved_driver[7];
2172 } HB;
2173 u8 pad[0x400-0x40];
2174};
39a98554 2175
2176enum {
2177 MEGASAS_HBA_OPERATIONAL = 0,
2178 MEGASAS_ADPRESET_SM_INFAULT = 1,
2179 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
2180 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
2181 MEGASAS_HW_CRITICAL_ERROR = 4,
229fe47c 2182 MEGASAS_ADPRESET_SM_POLLING = 5,
39a98554 2183 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
c4a3e0a5
BS		 2184};
2185
0c79e681
YB		 2186struct megasas_instance_template {
2187 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
2188 u32, struct megasas_register_set __iomem *);
2189
d46a3ad6
SS		 2190 void (*enable_intr)(struct megasas_instance *);
2191 void (*disable_intr)(struct megasas_instance *);
0c79e681
YB		 2192
2193 int (*clear_intr)(struct megasas_register_set __iomem *);
2194
2195 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
39a98554 2196 int (*adp_reset)(struct megasas_instance *, \
2197 struct megasas_register_set __iomem *);
2198 int (*check_reset)(struct megasas_instance *, \
2199 struct megasas_register_set __iomem *);
cd50ba8e 2200 irqreturn_t (*service_isr)(int irq, void *devp);
2201 void (*tasklet)(unsigned long);
2202 u32 (*init_adapter)(struct megasas_instance *);
2203 u32 (*build_and_issue_cmd) (struct megasas_instance *,
2204 struct scsi_cmnd *);
6d40afbc 2205 int (*issue_dcmd)(struct megasas_instance *instance,
cd50ba8e 2206 struct megasas_cmd *cmd);
0c79e681
YB		 2207};
2208
c4a3e0a5
BS		 2209#define MEGASAS_IS_LOGICAL(scp) \
2210 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
2211
4a5c814d
SS		 2212#define MEGASAS_DEV_INDEX(scp) \
2213 (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
2214 scp->device->id)
2215
2216#define MEGASAS_PD_INDEX(scp) \
2217 ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \
2218 scp->device->id)
c4a3e0a5
BS		 2219
2220struct megasas_cmd {
2221
2222 union megasas_frame *frame;
2223 dma_addr_t frame_phys_addr;
2224 u8 *sense;
2225 dma_addr_t sense_phys_addr;
2226
2227 u32 index;
2228 u8 sync_cmd;
2be2a988 2229 u8 cmd_status_drv;
39a98554 2230 u8 abort_aen;
2231 u8 retry_for_fw_reset;
2232
c4a3e0a5
BS		 2233
2234 struct list_head list;
2235 struct scsi_cmnd *scmd;
4026e9aa 2236 u8 flags;
90dc9d98 2237
c4a3e0a5 2238 struct megasas_instance *instance;
9c915a8c 2239 union {
2240 struct {
2241 u16 smid;
2242 u16 resvd;
2243 } context;
2244 u32 frame_count;
2245 };
c4a3e0a5
BS		 2246};
2247
2248#define MAX_MGMT_ADAPTERS 1024
2249#define MAX_IOCTL_SGE 16
2250
2251struct megasas_iocpacket {
2252
2253 u16 host_no;
2254 u16 __pad1;
2255 u32 sgl_off;
2256 u32 sge_count;
2257 u32 sense_off;
2258 u32 sense_len;
2259 union {
2260 u8 raw[128];
2261 struct megasas_header hdr;
2262 } frame;
2263
2264 struct iovec sgl[MAX_IOCTL_SGE];
2265
2266} __attribute__ ((packed));
2267
2268struct megasas_aen {
2269 u16 host_no;
2270 u16 __pad1;
2271 u32 seq_num;
2272 u32 class_locale_word;
2273} __attribute__ ((packed));
2274
2275#ifdef CONFIG_COMPAT
2276struct compat_megasas_iocpacket {
2277 u16 host_no;
2278 u16 __pad1;
2279 u32 sgl_off;
2280 u32 sge_count;
2281 u32 sense_off;
2282 u32 sense_len;
2283 union {
2284 u8 raw[128];
2285 struct megasas_header hdr;
2286 } frame;
2287 struct compat_iovec sgl[MAX_IOCTL_SGE];
2288} __attribute__ ((packed));
2289
0e98936c 2290#define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
c4a3e0a5
BS		 2291#endif
2292
cb59aa6a 2293#define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
c4a3e0a5
BS		 2294#define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
2295
2296struct megasas_mgmt_info {
2297
2298 u16 count;
2299 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
2300 int max_index;
2301};
2302
6d40afbc
SS		 2303enum MEGASAS_OCR_CAUSE {
2304 FW_FAULT_OCR = 0,
2305 SCSIIO_TIMEOUT_OCR = 1,
2306 MFI_IO_TIMEOUT_OCR = 2,
2307};
2308
2309enum DCMD_RETURN_STATUS {
2310 DCMD_SUCCESS = 0,
2311 DCMD_TIMEOUT = 1,
2312 DCMD_FAILED = 2,
2313 DCMD_NOT_FIRED = 3,
2314};
2315
21c9e160 2316u8
2317MR_BuildRaidContext(struct megasas_instance *instance,
2318 struct IO_REQUEST_INFO *io_info,
2319 struct RAID_CONTEXT *pRAID_Context,
51087a86
SS		 2320 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
2321u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
2322struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2323u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
2324u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
9ab9ed38 2325__le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
51087a86
SS		 2326u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2327
9ab9ed38 2328__le16 get_updated_dev_handle(struct megasas_instance *instance,
d2552ebe 2329 struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *in_info);
51087a86
SS		 2330void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
2331 struct LD_LOAD_BALANCE_INFO *lbInfo);
d009b576 2332int megasas_get_ctrl_info(struct megasas_instance *instance);
3761cb4c 2333/* PD sequence */
2334int
2335megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend);
fc62b3fc 2336int megasas_set_crash_dump_params(struct megasas_instance *instance,
51087a86 2337 u8 crash_buf_state);
fc62b3fc
SS		 2338void megasas_free_host_crash_buffer(struct megasas_instance *instance);
2339void megasas_fusion_crash_dump_wq(struct work_struct *work);
51087a86 2340
90dc9d98
SS		 2341void megasas_return_cmd_fusion(struct megasas_instance *instance,
2342 struct megasas_cmd_fusion *cmd);
2343int megasas_issue_blocked_cmd(struct megasas_instance *instance,
2344 struct megasas_cmd *cmd, int timeout);
2345void __megasas_return_cmd(struct megasas_instance *instance,
2346 struct megasas_cmd *cmd);
2347
2348void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
2349 struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
7497cde8 2350int megasas_cmd_type(struct scsi_cmnd *cmd);
3761cb4c 2351void megasas_setup_jbod_map(struct megasas_instance *instance);
90dc9d98 2352
18365b13
SS		 2353void megasas_update_sdev_properties(struct scsi_device *sdev);
2354int megasas_reset_fusion(struct Scsi_Host *shost, int reason);
2355int megasas_task_abort_fusion(struct scsi_cmnd *scmd);
2356int megasas_reset_target_fusion(struct scsi_cmnd *scmd);
c4a3e0a5 2357#endif /*LSI_MEGARAID_SAS_H */
Linux 6.x block layer and io_uring tree(s)