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scsi: lpfc: Fix link speed reporting for 4-link trunk
[linux-block.git] / drivers / scsi / lpfc / lpfc_sli4.h
CommitLineData
da0436e9
JS		 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
0d041215 4 * Copyright (C) 2017-2019 Broadcom. All Rights Reserved. The term *
4ae2ebde 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
51f4ca3c 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. *
da0436e9 7 * EMULEX and SLI are trademarks of Emulex. *
d080abe0 8 * www.broadcom.com *
da0436e9
JS		 9 * *
10 * This program is free software; you can redistribute it and/or *
11 * modify it under the terms of version 2 of the GNU General *
12 * Public License as published by the Free Software Foundation. *
13 * This program is distributed in the hope that it will be useful. *
14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18 * TO BE LEGALLY INVALID. See the GNU General Public License for *
19 * more details, a copy of which can be found in the file COPYING *
20 * included with this package. *
21 *******************************************************************/
22
63df6d63
JS		 23#if defined(CONFIG_DEBUG_FS) && !defined(CONFIG_SCSI_LPFC_DEBUG_FS)
24#define CONFIG_SCSI_LPFC_DEBUG_FS
25#endif
26
da0436e9 27#define LPFC_ACTIVE_MBOX_WAIT_CNT 100
5af5eee7
JS		 28#define LPFC_XRI_EXCH_BUSY_WAIT_TMO 10000
29#define LPFC_XRI_EXCH_BUSY_WAIT_T1 10
30#define LPFC_XRI_EXCH_BUSY_WAIT_T2 30000
da0436e9 31#define LPFC_RPI_LOW_WATER_MARK 10
ecfd03c6 32
a93ff37a
JS		 33#define LPFC_UNREG_FCF 1
34#define LPFC_SKIP_UNREG_FCF 0
35
ecfd03c6
JS		 36/* Amount of time in seconds for waiting FCF rediscovery to complete */
37#define LPFC_FCF_REDISCOVER_WAIT_TMO 2000 /* msec */
38
da0436e9
JS		 39/* Number of SGL entries can be posted in a 4KB nonembedded mbox command */
40#define LPFC_NEMBED_MBOX_SGL_CNT 254
41
67d12733 42/* Multi-queue arrangement for FCP EQ/CQ/WQ tuples */
cdb42bec 43#define LPFC_HBA_HDWQ_MIN 0
6a828b0f 44#define LPFC_HBA_HDWQ_MAX 128
cdb42bec 45#define LPFC_HBA_HDWQ_DEF 0
da0436e9 46
0794d601
JS		 47/* Common buffer size to accomidate SCSI and NVME IO buffers */
48#define LPFC_COMMON_IO_BUF_SZ 768
49
da0436e9
JS		 50/*
51 * Provide the default FCF Record attributes used by the driver
52 * when nonFIP mode is configured and there is no other default
53 * FCF Record attributes.
54 */
55#define LPFC_FCOE_FCF_DEF_INDEX 0
56#define LPFC_FCOE_FCF_GET_FIRST 0xFFFF
57#define LPFC_FCOE_FCF_NEXT_NONE 0xFFFF
58
dbb6b3ab
JS		 59#define LPFC_FCOE_NULL_VID 0xFFF
60#define LPFC_FCOE_IGNORE_VID 0xFFFF
61
da0436e9
JS		 62/* First 3 bytes of default FCF MAC is specified by FC_MAP */
63#define LPFC_FCOE_FCF_MAC3 0xFF
64#define LPFC_FCOE_FCF_MAC4 0xFF
65#define LPFC_FCOE_FCF_MAC5 0xFE
66#define LPFC_FCOE_FCF_MAP0 0x0E
67#define LPFC_FCOE_FCF_MAP1 0xFC
68#define LPFC_FCOE_FCF_MAP2 0x00
98fc5dd9 69#define LPFC_FCOE_MAX_RCV_SIZE 0x800
da0436e9
JS		 70#define LPFC_FCOE_FKA_ADV_PER 0
71#define LPFC_FCOE_FIP_PRIORITY 0x80
72
6669f9bb
JS		 73#define sli4_sid_from_fc_hdr(fc_hdr) \
74 ((fc_hdr)->fh_s_id[0] << 16 | \
75 (fc_hdr)->fh_s_id[1] << 8 | \
76 (fc_hdr)->fh_s_id[2])
77
939723a4
JS		 78#define sli4_did_from_fc_hdr(fc_hdr) \
79 ((fc_hdr)->fh_d_id[0] << 16 | \
80 (fc_hdr)->fh_d_id[1] << 8 | \
81 (fc_hdr)->fh_d_id[2])
82
5ffc266e
JS		 83#define sli4_fctl_from_fc_hdr(fc_hdr) \
84 ((fc_hdr)->fh_f_ctl[0] << 16 | \
85 (fc_hdr)->fh_f_ctl[1] << 8 | \
86 (fc_hdr)->fh_f_ctl[2])
87
939723a4
JS		 88#define sli4_type_from_fc_hdr(fc_hdr) \
89 ((fc_hdr)->fh_type)
90
88a2cfbb
JS		 91#define LPFC_FW_RESET_MAXIMUM_WAIT_10MS_CNT 12000
92
c71ab861
JS		 93#define INT_FW_UPGRADE 0
94#define RUN_FW_UPGRADE 1
95
da0436e9
JS		 96enum lpfc_sli4_queue_type {
97 LPFC_EQ,
98 LPFC_GCQ,
99 LPFC_MCQ,
100 LPFC_WCQ,
101 LPFC_RCQ,
102 LPFC_MQ,
103 LPFC_WQ,
104 LPFC_HRQ,
105 LPFC_DRQ
106};
107
108/* The queue sub-type defines the functional purpose of the queue */
109enum lpfc_sli4_queue_subtype {
110 LPFC_NONE,
111 LPFC_MBOX,
112 LPFC_FCP,
113 LPFC_ELS,
895427bd 114 LPFC_NVME,
f358dd0c 115 LPFC_NVMET,
895427bd 116 LPFC_NVME_LS,
da0436e9
JS		 117 LPFC_USOL
118};
119
120union sli4_qe {
121 void *address;
122 struct lpfc_eqe *eqe;
123 struct lpfc_cqe *cqe;
124 struct lpfc_mcqe *mcqe;
125 struct lpfc_wcqe_complete *wcqe_complete;
126 struct lpfc_wcqe_release *wcqe_release;
127 struct sli4_wcqe_xri_aborted *wcqe_xri_aborted;
128 struct lpfc_rcqe_complete *rcqe_complete;
129 struct lpfc_mqe *mqe;
130 union lpfc_wqe *wqe;
0c651878 131 union lpfc_wqe128 *wqe128;
da0436e9
JS		 132 struct lpfc_rqe *rqe;
133};
134
895427bd
JS		 135/* RQ buffer list */
136struct lpfc_rqb {
137 uint16_t entry_count; /* Current number of RQ slots */
138 uint16_t buffer_count; /* Current number of buffers posted */
139 struct list_head rqb_buffer_list; /* buffers assigned to this HBQ */
140 /* Callback for HBQ buffer allocation */
141 struct rqb_dmabuf *(*rqb_alloc_buffer)(struct lpfc_hba *);
142 /* Callback for HBQ buffer free */
143 void (*rqb_free_buffer)(struct lpfc_hba *,
144 struct rqb_dmabuf *);
145};
146
da0436e9
JS		 147struct lpfc_queue {
148 struct list_head list;
895427bd 149 struct list_head wq_list;
6e8e1c14 150 struct list_head wqfull_list;
da0436e9
JS		 151 enum lpfc_sli4_queue_type type;
152 enum lpfc_sli4_queue_subtype subtype;
153 struct lpfc_hba *phba;
154 struct list_head child_list;
895427bd
JS		 155 struct list_head page_list;
156 struct list_head sgl_list;
32517fc0 157 struct list_head cpu_list;
da0436e9
JS		 158 uint32_t entry_count; /* Number of entries to support on the queue */
159 uint32_t entry_size; /* Size of each queue entry. */
32517fc0
JS		 160 uint32_t notify_interval; /* Queue Notification Interval
161 * For chip->host queues (EQ, CQ, RQ):
162 * specifies the interval (number of
163 * entries) where the doorbell is rung to
164 * notify the chip of entry consumption.
165 * For host->chip queues (WQ):
166 * specifies the interval (number of
167 * entries) where consumption CQE is
168 * requested to indicate WQ entries
169 * consumed by the chip.
170 * Not used on an MQ.
171 */
172#define LPFC_EQ_NOTIFY_INTRVL 16
173#define LPFC_CQ_NOTIFY_INTRVL 16
174#define LPFC_WQ_NOTIFY_INTRVL 16
175#define LPFC_RQ_NOTIFY_INTRVL 16
176 uint32_t max_proc_limit; /* Queue Processing Limit
177 * For chip->host queues (EQ, CQ):
178 * specifies the maximum number of
179 * entries to be consumed in one
180 * processing iteration sequence. Queue
181 * will be rearmed after each iteration.
182 * Not used on an MQ, RQ or WQ.
183 */
184#define LPFC_EQ_MAX_PROC_LIMIT 256
185#define LPFC_CQ_MIN_PROC_LIMIT 64
186#define LPFC_CQ_MAX_PROC_LIMIT LPFC_CQE_EXP_COUNT // 4096
187#define LPFC_CQ_DEF_MAX_PROC_LIMIT LPFC_CQE_DEF_COUNT // 1024
188#define LPFC_CQ_MIN_THRESHOLD_TO_POLL 64
189#define LPFC_CQ_MAX_THRESHOLD_TO_POLL LPFC_CQ_DEF_MAX_PROC_LIMIT
190#define LPFC_CQ_DEF_THRESHOLD_TO_POLL LPFC_CQ_DEF_MAX_PROC_LIMIT
191 uint32_t queue_claimed; /* indicates queue is being processed */
da0436e9 192 uint32_t queue_id; /* Queue ID assigned by the hardware */
2a622bfb 193 uint32_t assoc_qid; /* Queue ID associated with, for CQ/WQ/MQ */
da0436e9
JS		 194 uint32_t host_index; /* The host's index for putting or getting */
195 uint32_t hba_index; /* The last known hba index for get or put */
6a828b0f 196 uint32_t q_mode;
b84daac9 197
2a76a283 198 struct lpfc_sli_ring *pring; /* ptr to io ring associated with q */
895427bd 199 struct lpfc_rqb *rqbp; /* ptr to RQ buffers */
2a76a283 200
81b96eda
JS		 201 uint16_t page_count; /* Number of pages allocated for this queue */
202 uint16_t page_size; /* size of page allocated for this queue */
a51e41b6 203#define LPFC_EXPANDED_PAGE_SIZE 16384
81b96eda 204#define LPFC_DEFAULT_PAGE_SIZE 4096
6a828b0f
JS		 205 uint16_t chann; /* Hardware Queue association WQ/CQ */
206 /* CPU affinity for EQ */
207#define LPFC_FIND_BY_EQ 0
208#define LPFC_FIND_BY_HDWQ 1
6e8e1c14 209 uint8_t db_format;
962bc51b
JS		 210#define LPFC_DB_RING_FORMAT 0x01
211#define LPFC_DB_LIST_FORMAT 0x02
6e8e1c14
JS		 212 uint8_t q_flag;
213#define HBA_NVMET_WQFULL 0x1 /* We hit WQ Full condition for NVMET */
962bc51b 214 void __iomem *db_regaddr;
1351e69f
JS		 215 uint16_t dpp_enable;
216 uint16_t dpp_id;
217 void __iomem *dpp_regaddr;
218
b84daac9
JS		 219 /* For q stats */
220 uint32_t q_cnt_1;
221 uint32_t q_cnt_2;
222 uint32_t q_cnt_3;
223 uint64_t q_cnt_4;
224/* defines for EQ stats */
225#define EQ_max_eqe q_cnt_1
226#define EQ_no_entry q_cnt_2
0cf07f84 227#define EQ_cqe_cnt q_cnt_3
b84daac9
JS		 228#define EQ_processed q_cnt_4
229
230/* defines for CQ stats */
231#define CQ_mbox q_cnt_1
232#define CQ_max_cqe q_cnt_1
233#define CQ_release_wqe q_cnt_2
234#define CQ_xri_aborted q_cnt_3
235#define CQ_wq q_cnt_4
236
237/* defines for WQ stats */
238#define WQ_overflow q_cnt_1
239#define WQ_posted q_cnt_4
240
241/* defines for RQ stats */
242#define RQ_no_posted_buf q_cnt_1
243#define RQ_no_buf_found q_cnt_2
547077a4 244#define RQ_buf_posted q_cnt_3
b84daac9
JS		 245#define RQ_rcv_buf q_cnt_4
246
32517fc0
JS		 247 struct work_struct irqwork;
248 struct work_struct spwork;
249 struct delayed_work sched_irqwork;
250 struct delayed_work sched_spwork;
f485c18d 251
895427bd 252 uint64_t isr_timestamp;
5e5b511d 253 uint16_t hdwq;
32517fc0 254 uint16_t last_cpu; /* most recent cpu */
7365f6fd 255 uint8_t qe_valid;
895427bd 256 struct lpfc_queue *assoc_qp;
da0436e9
JS		 257 union sli4_qe qe[1]; /* array to index entries (must be last) */
258};
259
da0436e9 260struct lpfc_sli4_link {
f3339800 261 uint32_t speed;
da0436e9
JS		 262 uint8_t duplex;
263 uint8_t status;
70f3c073
JS		 264 uint8_t type;
265 uint8_t number;
da0436e9 266 uint8_t fault;
f3339800 267 uint32_t logical_speed;
70f3c073 268 uint16_t topology;
da0436e9
JS		 269};
270
ecfd03c6
JS		 271struct lpfc_fcf_rec {
272 uint8_t fabric_name[8];
273 uint8_t switch_name[8];
da0436e9
JS		 274 uint8_t mac_addr[6];
275 uint16_t fcf_indx;
ecfd03c6
JS		 276 uint32_t priority;
277 uint16_t vlan_id;
278 uint32_t addr_mode;
279 uint32_t flag;
280#define BOOT_ENABLE 0x01
281#define RECORD_VALID 0x02
282};
283
7d791df7
JS		 284struct lpfc_fcf_pri_rec {
285 uint16_t fcf_index;
286#define LPFC_FCF_ON_PRI_LIST 0x0001
287#define LPFC_FCF_FLOGI_FAILED 0x0002
288 uint16_t flag;
289 uint32_t priority;
290};
291
292struct lpfc_fcf_pri {
293 struct list_head list;
294 struct lpfc_fcf_pri_rec fcf_rec;
295};
296
297/*
298 * Maximum FCF table index, it is for driver internal book keeping, it
299 * just needs to be no less than the supported HBA's FCF table size.
300 */
301#define LPFC_SLI4_FCF_TBL_INDX_MAX 32
302
ecfd03c6 303struct lpfc_fcf {
da0436e9
JS		 304 uint16_t fcfi;
305 uint32_t fcf_flag;
306#define FCF_AVAILABLE 0x01 /* FCF available for discovery */
307#define FCF_REGISTERED 0x02 /* FCF registered with FW */
ecfd03c6
JS		 308#define FCF_SCAN_DONE 0x04 /* FCF table scan done */
309#define FCF_IN_USE 0x08 /* Atleast one discovery completed */
0c9ab6f5
JS		 310#define FCF_INIT_DISC 0x10 /* Initial FCF discovery */
311#define FCF_DEAD_DISC 0x20 /* FCF DEAD fast FCF failover discovery */
312#define FCF_ACVL_DISC 0x40 /* All CVL fast FCF failover discovery */
313#define FCF_DISCOVERY (FCF_INIT_DISC | FCF_DEAD_DISC | FCF_ACVL_DISC)
314#define FCF_REDISC_PEND 0x80 /* FCF rediscovery pending */
315#define FCF_REDISC_EVT 0x100 /* FCF rediscovery event to worker thread */
316#define FCF_REDISC_FOV 0x200 /* Post FCF rediscovery fast failover */
a93ff37a 317#define FCF_REDISC_PROG (FCF_REDISC_PEND | FCF_REDISC_EVT)
036cad1f 318 uint16_t fcf_redisc_attempted;
da0436e9 319 uint32_t addr_mode;
999d813f 320 uint32_t eligible_fcf_cnt;
ecfd03c6
JS		 321 struct lpfc_fcf_rec current_rec;
322 struct lpfc_fcf_rec failover_rec;
7d791df7
JS		 323 struct list_head fcf_pri_list;
324 struct lpfc_fcf_pri fcf_pri[LPFC_SLI4_FCF_TBL_INDX_MAX];
325 uint32_t current_fcf_scan_pri;
ecfd03c6 326 struct timer_list redisc_wait;
0c9ab6f5 327 unsigned long *fcf_rr_bmask; /* Eligible FCF indexes for RR failover */
da0436e9
JS		 328};
329
0c9ab6f5 330
da0436e9
JS		 331#define LPFC_REGION23_SIGNATURE "RG23"
332#define LPFC_REGION23_VERSION 1
333#define LPFC_REGION23_LAST_REC 0xff
a0c87cbd
JS		 334#define DRIVER_SPECIFIC_TYPE 0xA2
335#define LINUX_DRIVER_ID 0x20
336#define PORT_STE_TYPE 0x1
337
da0436e9
JS		 338struct lpfc_fip_param_hdr {
339 uint8_t type;
340#define FCOE_PARAM_TYPE 0xA0
341 uint8_t length;
342#define FCOE_PARAM_LENGTH 2
343 uint8_t parm_version;
344#define FIPP_VERSION 0x01
345 uint8_t parm_flags;
346#define lpfc_fip_param_hdr_fipp_mode_SHIFT 6
347#define lpfc_fip_param_hdr_fipp_mode_MASK 0x3
348#define lpfc_fip_param_hdr_fipp_mode_WORD parm_flags
6a9c52cf 349#define FIPP_MODE_ON 0x1
da0436e9
JS		 350#define FIPP_MODE_OFF 0x0
351#define FIPP_VLAN_VALID 0x1
352};
353
354struct lpfc_fcoe_params {
355 uint8_t fc_map[3];
356 uint8_t reserved1;
357 uint16_t vlan_tag;
358 uint8_t reserved[2];
359};
360
361struct lpfc_fcf_conn_hdr {
362 uint8_t type;
363#define FCOE_CONN_TBL_TYPE 0xA1
364 uint8_t length; /* words */
365 uint8_t reserved[2];
366};
367
368struct lpfc_fcf_conn_rec {
369 uint16_t flags;
370#define FCFCNCT_VALID 0x0001
371#define FCFCNCT_BOOT 0x0002
372#define FCFCNCT_PRIMARY 0x0004 /* if not set, Secondary */
373#define FCFCNCT_FBNM_VALID 0x0008
374#define FCFCNCT_SWNM_VALID 0x0010
375#define FCFCNCT_VLAN_VALID 0x0020
376#define FCFCNCT_AM_VALID 0x0040
377#define FCFCNCT_AM_PREFERRED 0x0080 /* if not set, AM Required */
378#define FCFCNCT_AM_SPMA 0x0100 /* if not set, FPMA */
379
380 uint16_t vlan_tag;
381 uint8_t fabric_name[8];
382 uint8_t switch_name[8];
383};
384
385struct lpfc_fcf_conn_entry {
386 struct list_head list;
387 struct lpfc_fcf_conn_rec conn_rec;
388};
389
390/*
391 * Define the host's bootstrap mailbox. This structure contains
392 * the member attributes needed to create, use, and destroy the
393 * bootstrap mailbox region.
394 *
395 * The macro definitions for the bmbx data structure are defined
396 * in lpfc_hw4.h with the register definition.
397 */
398struct lpfc_bmbx {
399 struct lpfc_dmabuf *dmabuf;
400 struct dma_address dma_address;
401 void *avirt;
402 dma_addr_t aphys;
403 uint32_t bmbx_size;
404};
405
406#define LPFC_EQE_SIZE LPFC_EQE_SIZE_4
407
408#define LPFC_EQE_SIZE_4B 4
409#define LPFC_EQE_SIZE_16B 16
410#define LPFC_CQE_SIZE 16
411#define LPFC_WQE_SIZE 64
0c651878 412#define LPFC_WQE128_SIZE 128
da0436e9
JS		 413#define LPFC_MQE_SIZE 256
414#define LPFC_RQE_SIZE 8
415
416#define LPFC_EQE_DEF_COUNT 1024
ff78d8f9 417#define LPFC_CQE_DEF_COUNT 1024
a51e41b6 418#define LPFC_CQE_EXP_COUNT 4096
f1126688 419#define LPFC_WQE_DEF_COUNT 256
a51e41b6 420#define LPFC_WQE_EXP_COUNT 1024
da0436e9
JS		 421#define LPFC_MQE_DEF_COUNT 16
422#define LPFC_RQE_DEF_COUNT 512
423
424#define LPFC_QUEUE_NOARM false
425#define LPFC_QUEUE_REARM true
426
427
428/*
429 * SLI4 CT field defines
430 */
431#define SLI4_CT_RPI 0
432#define SLI4_CT_VPI 1
433#define SLI4_CT_VFI 2
434#define SLI4_CT_FCFI 3
435
da0436e9
JS		 436/*
437 * SLI4 specific data structures
438 */
439struct lpfc_max_cfg_param {
440 uint16_t max_xri;
441 uint16_t xri_base;
442 uint16_t xri_used;
443 uint16_t max_rpi;
444 uint16_t rpi_base;
445 uint16_t rpi_used;
446 uint16_t max_vpi;
447 uint16_t vpi_base;
448 uint16_t vpi_used;
449 uint16_t max_vfi;
450 uint16_t vfi_base;
451 uint16_t vfi_used;
452 uint16_t max_fcfi;
da0436e9
JS		 453 uint16_t fcfi_used;
454 uint16_t max_eq;
455 uint16_t max_rq;
456 uint16_t max_cq;
457 uint16_t max_wq;
458};
459
460struct lpfc_hba;
461/* SLI4 HBA multi-fcp queue handler struct */
b83d005e 462#define LPFC_SLI4_HANDLER_NAME_SZ 16
895427bd 463struct lpfc_hba_eq_hdl {
da0436e9 464 uint32_t idx;
b83d005e 465 char handler_name[LPFC_SLI4_HANDLER_NAME_SZ];
da0436e9
JS		 466 struct lpfc_hba *phba;
467};
468
44fd7fe3
JS		 469/*BB Credit recovery value*/
470struct lpfc_bbscn_params {
471 uint32_t word0;
472#define lpfc_bbscn_min_SHIFT 0
473#define lpfc_bbscn_min_MASK 0x0000000F
474#define lpfc_bbscn_min_WORD word0
475#define lpfc_bbscn_max_SHIFT 4
476#define lpfc_bbscn_max_MASK 0x0000000F
477#define lpfc_bbscn_max_WORD word0
478#define lpfc_bbscn_def_SHIFT 8
479#define lpfc_bbscn_def_MASK 0x0000000F
480#define lpfc_bbscn_def_WORD word0
481};
482
28baac74
JS		 483/* Port Capabilities for SLI4 Parameters */
484struct lpfc_pc_sli4_params {
485 uint32_t supported;
486 uint32_t if_type;
487 uint32_t sli_rev;
488 uint32_t sli_family;
489 uint32_t featurelevel_1;
490 uint32_t featurelevel_2;
491 uint32_t proto_types;
492#define LPFC_SLI4_PROTO_FCOE 0x0000001
493#define LPFC_SLI4_PROTO_FC 0x0000002
494#define LPFC_SLI4_PROTO_NIC 0x0000004
495#define LPFC_SLI4_PROTO_ISCSI 0x0000008
496#define LPFC_SLI4_PROTO_RDMA 0x0000010
497 uint32_t sge_supp_len;
498 uint32_t if_page_sz;
499 uint32_t rq_db_window;
500 uint32_t loopbk_scope;
1ba981fd 501 uint32_t oas_supported;
28baac74
JS		 502 uint32_t eq_pages_max;
503 uint32_t eqe_size;
504 uint32_t cq_pages_max;
505 uint32_t cqe_size;
506 uint32_t mq_pages_max;
507 uint32_t mqe_size;
508 uint32_t mq_elem_cnt;
509 uint32_t wq_pages_max;
510 uint32_t wqe_size;
511 uint32_t rq_pages_max;
512 uint32_t rqe_size;
513 uint32_t hdr_pages_max;
514 uint32_t hdr_size;
515 uint32_t hdr_pp_align;
516 uint32_t sgl_pages_max;
517 uint32_t sgl_pp_align;
fedd3b7b
JS		 518 uint8_t cqv;
519 uint8_t mqv;
520 uint8_t wqv;
521 uint8_t rqv;
7365f6fd
JS		 522 uint8_t eqav;
523 uint8_t cqav;
0c651878 524 uint8_t wqsize;
66e9e6bf 525 uint8_t bv1s;
0c651878
JS		 526#define LPFC_WQ_SZ64_SUPPORT 1
527#define LPFC_WQ_SZ128_SUPPORT 2
895427bd 528 uint8_t wqpcnt;
28baac74
JS		 529};
530
c176ffa0
JS		 531#define LPFC_CQ_4K_PAGE_SZ 0x1
532#define LPFC_CQ_16K_PAGE_SZ 0x4
533#define LPFC_WQ_4K_PAGE_SZ 0x1
534#define LPFC_WQ_16K_PAGE_SZ 0x4
535
912e3acd
JS		 536struct lpfc_iov {
537 uint32_t pf_number;
538 uint32_t vf_number;
539};
540
cd1c8301
JS		 541struct lpfc_sli4_lnk_info {
542 uint8_t lnk_dv;
543#define LPFC_LNK_DAT_INVAL 0
544#define LPFC_LNK_DAT_VAL 1
545 uint8_t lnk_tp;
546#define LPFC_LNK_GE 0x0 /* FCoE */
547#define LPFC_LNK_FC 0x1 /* FC */
548 uint8_t lnk_no;
448193b5 549 uint8_t optic_state;
cd1c8301
JS		 550};
551
895427bd 552#define LPFC_SLI4_HANDLER_CNT (LPFC_HBA_IO_CHAN_MAX+ \
1ba981fd 553 LPFC_FOF_IO_CHAN_NUM)
4305f183 554
7bb03bbf
JS		 555/* Used for IRQ vector to CPU mapping */
556struct lpfc_vector_map_info {
557 uint16_t phys_id;
558 uint16_t core_id;
559 uint16_t irq;
6a828b0f 560 uint16_t eq;
b3295c2a 561 uint16_t hdwq;
6a828b0f 562 uint16_t hyper;
7bb03bbf
JS		 563};
564#define LPFC_VECTOR_MAP_EMPTY 0xffff
7bb03bbf 565
c490850a
JS		 566/* Multi-XRI pool */
567#define XRI_BATCH 8
568
569struct lpfc_pbl_pool {
570 struct list_head list;
571 u32 count;
572 spinlock_t lock; /* lock for pbl_pool*/
573};
574
575struct lpfc_pvt_pool {
576 u32 low_watermark;
577 u32 high_watermark;
578
579 struct list_head list;
580 u32 count;
581 spinlock_t lock; /* lock for pvt_pool */
582};
583
584struct lpfc_multixri_pool {
585 u32 xri_limit;
586
587 /* Starting point when searching a pbl_pool with round-robin method */
588 u32 rrb_next_hwqid;
589
590 /* Used by lpfc_adjust_pvt_pool_count.
591 * io_req_count is incremented by 1 during IO submission. The heartbeat
592 * handler uses these two variables to determine if pvt_pool is idle or
593 * busy.
594 */
595 u32 prev_io_req_count;
596 u32 io_req_count;
597
598 /* statistics */
599 u32 pbl_empty_count;
600#ifdef LPFC_MXP_STAT
601 u32 above_limit_count;
602 u32 below_limit_count;
603 u32 local_pbl_hit_count;
604 u32 other_pbl_hit_count;
605 u32 stat_max_hwm;
606
607#define LPFC_MXP_SNAPSHOT_TAKEN 3 /* snapshot is taken at 3rd heartbeats */
608 u32 stat_pbl_count;
609 u32 stat_pvt_count;
610 u32 stat_busy_count;
611 u32 stat_snapshot_taken;
612#endif
613
614 /* TODO: Separate pvt_pool into get and put list */
615 struct lpfc_pbl_pool pbl_pool; /* Public free XRI pool */
616 struct lpfc_pvt_pool pvt_pool; /* Private free XRI pool */
617};
618
4c47efc1
JS		 619struct lpfc_fc4_ctrl_stat {
620 u32 input_requests;
621 u32 output_requests;
622 u32 control_requests;
623 u32 io_cmpls;
624};
625
6a828b0f
JS		 626#ifdef LPFC_HDWQ_LOCK_STAT
627struct lpfc_lock_stat {
628 uint32_t alloc_xri_get;
629 uint32_t alloc_xri_put;
630 uint32_t free_xri;
631 uint32_t wq_access;
632 uint32_t alloc_pvt_pool;
633 uint32_t mv_from_pvt_pool;
634 uint32_t mv_to_pub_pool;
635 uint32_t mv_to_pvt_pool;
636 uint32_t free_pub_pool;
637 uint32_t free_pvt_pool;
638};
639#endif
640
32517fc0
JS		 641struct lpfc_eq_intr_info {
642 struct list_head list;
643 uint32_t icnt;
644};
645
da0436e9 646/* SLI4 HBA data structure entries */
cdb42bec
JS		 647struct lpfc_sli4_hdw_queue {
648 /* Pointers to the constructed SLI4 queues */
649 struct lpfc_queue *hba_eq; /* Event queues for HBA */
650 struct lpfc_queue *fcp_cq; /* Fast-path FCP compl queue */
651 struct lpfc_queue *nvme_cq; /* Fast-path NVME compl queue */
652 struct lpfc_queue *fcp_wq; /* Fast-path FCP work queue */
653 struct lpfc_queue *nvme_wq; /* Fast-path NVME work queue */
654 uint16_t fcp_cq_map;
655 uint16_t nvme_cq_map;
5e5b511d
JS		 656
657 /* Keep track of IO buffers for this hardware queue */
658 spinlock_t io_buf_list_get_lock; /* Common buf alloc list lock */
659 struct list_head lpfc_io_buf_list_get;
660 spinlock_t io_buf_list_put_lock; /* Common buf free list lock */
661 struct list_head lpfc_io_buf_list_put;
662 spinlock_t abts_scsi_buf_list_lock; /* list of aborted SCSI IOs */
663 struct list_head lpfc_abts_scsi_buf_list;
664 spinlock_t abts_nvme_buf_list_lock; /* list of aborted NVME IOs */
665 struct list_head lpfc_abts_nvme_buf_list;
666 uint32_t total_io_bufs;
667 uint32_t get_io_bufs;
668 uint32_t put_io_bufs;
669 uint32_t empty_io_bufs;
670 uint32_t abts_scsi_io_bufs;
671 uint32_t abts_nvme_io_bufs;
63df6d63 672
c490850a
JS		 673 /* Multi-XRI pool per HWQ */
674 struct lpfc_multixri_pool *p_multixri_pool;
675
4c47efc1
JS		 676 /* FC-4 Stats counters */
677 struct lpfc_fc4_ctrl_stat nvme_cstat;
678 struct lpfc_fc4_ctrl_stat scsi_cstat;
6a828b0f
JS		 679#ifdef LPFC_HDWQ_LOCK_STAT
680 struct lpfc_lock_stat lock_conflict;
681#endif
4c47efc1 682
63df6d63
JS		 683#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
684#define LPFC_CHECK_CPU_CNT 128
685 uint32_t cpucheck_rcv_io[LPFC_CHECK_CPU_CNT];
686 uint32_t cpucheck_xmt_io[LPFC_CHECK_CPU_CNT];
687 uint32_t cpucheck_cmpl_io[LPFC_CHECK_CPU_CNT];
688#endif
cdb42bec
JS		 689};
690
6a828b0f
JS		 691#ifdef LPFC_HDWQ_LOCK_STAT
692/* compile time trylock stats */
693#define lpfc_qp_spin_lock_irqsave(lock, flag, qp, lstat) \
694 { \
695 int only_once = 1; \
696 while (spin_trylock_irqsave(lock, flag) == 0) { \
697 if (only_once) { \
698 only_once = 0; \
699 qp->lock_conflict.lstat++; \
700 } \
701 } \
702 }
703#define lpfc_qp_spin_lock(lock, qp, lstat) \
704 { \
705 int only_once = 1; \
706 while (spin_trylock(lock) == 0) { \
707 if (only_once) { \
708 only_once = 0; \
709 qp->lock_conflict.lstat++; \
710 } \
711 } \
712 }
713#else
714#define lpfc_qp_spin_lock_irqsave(lock, flag, qp, lstat) \
715 spin_lock_irqsave(lock, flag)
716#define lpfc_qp_spin_lock(lock, qp, lstat) spin_lock(lock)
717#endif
718
da0436e9
JS		 719struct lpfc_sli4_hba {
720 void __iomem *conf_regs_memmap_p; /* Kernel memory mapped address for
1351e69f
JS		 721 * config space registers
722 */
da0436e9 723 void __iomem *ctrl_regs_memmap_p; /* Kernel memory mapped address for
1351e69f
JS		 724 * control registers
725 */
da0436e9 726 void __iomem *drbl_regs_memmap_p; /* Kernel memory mapped address for
1351e69f
JS		 727 * doorbell registers
728 */
729 void __iomem *dpp_regs_memmap_p; /* Kernel memory mapped address for
730 * dpp registers
731 */
2fcee4bf
JS		 732 union {
733 struct {
734 /* IF Type 0, BAR 0 PCI cfg space reg mem map */
735 void __iomem *UERRLOregaddr;
736 void __iomem *UERRHIregaddr;
737 void __iomem *UEMASKLOregaddr;
738 void __iomem *UEMASKHIregaddr;
739 } if_type0;
740 struct {
741 /* IF Type 2, BAR 0 PCI cfg space reg mem map. */
742 void __iomem *STATUSregaddr;
743 void __iomem *CTRLregaddr;
744 void __iomem *ERR1regaddr;
2e90f4b5
JS		 745#define SLIPORT_ERR1_REG_ERR_CODE_1 0x1
746#define SLIPORT_ERR1_REG_ERR_CODE_2 0x2
2fcee4bf 747 void __iomem *ERR2regaddr;
2e90f4b5
JS		 748#define SLIPORT_ERR2_REG_FW_RESTART 0x0
749#define SLIPORT_ERR2_REG_FUNC_PROVISON 0x1
750#define SLIPORT_ERR2_REG_FORCED_DUMP 0x2
751#define SLIPORT_ERR2_REG_FAILURE_EQ 0x3
752#define SLIPORT_ERR2_REG_FAILURE_CQ 0x4
753#define SLIPORT_ERR2_REG_FAILURE_BUS 0x5
754#define SLIPORT_ERR2_REG_FAILURE_RQ 0x6
0cf07f84 755 void __iomem *EQDregaddr;
2fcee4bf
JS		 756 } if_type2;
757 } u;
758
759 /* IF type 0, BAR1 and if type 2, Bar 0 CSR register memory map */
760 void __iomem *PSMPHRregaddr;
761
762 /* Well-known SLI INTF register memory map. */
763 void __iomem *SLIINTFregaddr;
764
765 /* IF type 0, BAR 1 function CSR register memory map */
766 void __iomem *ISRregaddr; /* HST_ISR register */
767 void __iomem *IMRregaddr; /* HST_IMR register */
768 void __iomem *ISCRregaddr; /* HST_ISCR register */
769 /* IF type 0, BAR 0 and if type 2, BAR 0 doorbell register memory map */
770 void __iomem *RQDBregaddr; /* RQ_DOORBELL register */
771 void __iomem *WQDBregaddr; /* WQ_DOORBELL register */
9dd35425
JS		 772 void __iomem *CQDBregaddr; /* CQ_DOORBELL register */
773 void __iomem *EQDBregaddr; /* EQ_DOORBELL register */
2fcee4bf
JS		 774 void __iomem *MQDBregaddr; /* MQ_DOORBELL register */
775 void __iomem *BMBXregaddr; /* BootStrap MBX register */
da0436e9 776
a747c9ce
JS		 777 uint32_t ue_mask_lo;
778 uint32_t ue_mask_hi;
65791f1f
JS		 779 uint32_t ue_to_sr;
780 uint32_t ue_to_rp;
28baac74
JS		 781 struct lpfc_register sli_intf;
782 struct lpfc_pc_sli4_params pc_sli4_params;
44fd7fe3 783 struct lpfc_bbscn_params bbscn_params;
895427bd 784 struct lpfc_hba_eq_hdl *hba_eq_hdl; /* HBA per-WQ handle */
67d12733 785
b71413dd 786 void (*sli4_eq_clr_intr)(struct lpfc_queue *q);
32517fc0
JS		 787 void (*sli4_write_eq_db)(struct lpfc_hba *phba, struct lpfc_queue *eq,
788 uint32_t count, bool arm);
789 void (*sli4_write_cq_db)(struct lpfc_hba *phba, struct lpfc_queue *cq,
790 uint32_t count, bool arm);
b71413dd 791
da0436e9 792 /* Pointers to the constructed SLI4 queues */
cdb42bec
JS		 793 struct lpfc_sli4_hdw_queue *hdwq;
794 struct list_head lpfc_wq_list;
795
796 /* Pointers to the constructed SLI4 queues for NVMET */
2d7dbc4c
JS		 797 struct lpfc_queue **nvmet_cqset; /* Fast-path NVMET CQ Set queues */
798 struct lpfc_queue **nvmet_mrq_hdr; /* Fast-path NVMET hdr MRQs */
799 struct lpfc_queue **nvmet_mrq_data; /* Fast-path NVMET data MRQs */
67d12733
JS		 800
801 struct lpfc_queue *mbx_cq; /* Slow-path mailbox complete queue */
802 struct lpfc_queue *els_cq; /* Slow-path ELS response complete queue */
895427bd 803 struct lpfc_queue *nvmels_cq; /* NVME LS complete queue */
da0436e9
JS		 804 struct lpfc_queue *mbx_wq; /* Slow-path MBOX work queue */
805 struct lpfc_queue *els_wq; /* Slow-path ELS work queue */
895427bd 806 struct lpfc_queue *nvmels_wq; /* NVME LS work queue */
da0436e9
JS		 807 struct lpfc_queue *hdr_rq; /* Slow-path Header Receive queue */
808 struct lpfc_queue *dat_rq; /* Slow-path Data Receive queue */
da0436e9 809
895427bd
JS		 810 struct lpfc_name wwnn;
811 struct lpfc_name wwpn;
812
9a86ed48 813 uint32_t fw_func_mode; /* FW function protocol mode */
962bc51b
JS		 814 uint32_t ulp0_mode; /* ULP0 protocol mode */
815 uint32_t ulp1_mode; /* ULP1 protocol mode */
816
1ba981fd 817 /* Optimized Access Storage specific queues/structures */
1ba981fd
JS		 818 uint64_t oas_next_lun;
819 uint8_t oas_next_tgt_wwpn[8];
820 uint8_t oas_next_vpt_wwpn[8];
821
da0436e9
JS		 822 /* Setup information for various queue parameters */
823 int eq_esize;
824 int eq_ecount;
825 int cq_esize;
826 int cq_ecount;
827 int wq_esize;
828 int wq_ecount;
829 int mq_esize;
830 int mq_ecount;
831 int rq_esize;
832 int rq_ecount;
833#define LPFC_SP_EQ_MAX_INTR_SEC 10000
834#define LPFC_FP_EQ_MAX_INTR_SEC 10000
835
836 uint32_t intr_enable;
837 struct lpfc_bmbx bmbx;
838 struct lpfc_max_cfg_param max_cfg_param;
6d368e53
JS		 839 uint16_t extents_in_use; /* must allocate resource extents. */
840 uint16_t rpi_hdrs_in_use; /* must post rpi hdrs if set. */
da0436e9
JS		 841 uint16_t next_xri; /* last_xri - max_cfg_param.xri_base = used */
842 uint16_t next_rpi;
5e5b511d
JS		 843 uint16_t io_xri_max;
844 uint16_t io_xri_cnt;
845 uint16_t io_xri_start;
895427bd 846 uint16_t els_xri_cnt;
f358dd0c 847 uint16_t nvmet_xri_cnt;
a8cf5dfe
JS		 848 uint16_t nvmet_io_wait_cnt;
849 uint16_t nvmet_io_wait_total;
6a828b0f
JS		 850 uint16_t cq_max;
851 struct lpfc_queue **cq_lookup;
895427bd 852 struct list_head lpfc_els_sgl_list;
da0436e9 853 struct list_head lpfc_abts_els_sgl_list;
5e5b511d
JS		 854 spinlock_t abts_scsi_buf_list_lock; /* list of aborted SCSI IOs */
855 struct list_head lpfc_abts_scsi_buf_list;
f358dd0c 856 struct list_head lpfc_nvmet_sgl_list;
5e5b511d 857 spinlock_t abts_nvmet_buf_list_lock; /* list of aborted NVMET IOs */
86c67379 858 struct list_head lpfc_abts_nvmet_ctx_list;
a8cf5dfe 859 struct list_head lpfc_nvmet_io_wait_list;
66d7ce93 860 struct lpfc_nvmet_ctx_info *nvmet_ctx_info;
da0436e9
JS		 861 struct lpfc_sglq **lpfc_sglq_active_list;
862 struct list_head lpfc_rpi_hdr_list;
863 unsigned long *rpi_bmask;
6d368e53 864 uint16_t *rpi_ids;
da0436e9 865 uint16_t rpi_count;
6d368e53
JS		 866 struct list_head lpfc_rpi_blk_list;
867 unsigned long *xri_bmask;
868 uint16_t *xri_ids;
6d368e53
JS		 869 struct list_head lpfc_xri_blk_list;
870 unsigned long *vfi_bmask;
871 uint16_t *vfi_ids;
872 uint16_t vfi_count;
873 struct list_head lpfc_vfi_blk_list;
da0436e9 874 struct lpfc_sli4_flags sli4_flags;
45ed1190 875 struct list_head sp_queue_event;
da0436e9
JS		 876 struct list_head sp_cqe_event_pool;
877 struct list_head sp_asynce_work_queue;
878 struct list_head sp_fcp_xri_aborted_work_queue;
879 struct list_head sp_els_xri_aborted_work_queue;
880 struct list_head sp_unsol_work_queue;
881 struct lpfc_sli4_link link_state;
cd1c8301
JS		 882 struct lpfc_sli4_lnk_info lnk_info;
883 uint32_t pport_name_sta;
884#define LPFC_SLI4_PPNAME_NON 0
885#define LPFC_SLI4_PPNAME_GET 1
912e3acd 886 struct lpfc_iov iov;
895427bd 887 spinlock_t sgl_list_lock; /* list of aborted els IOs */
a8cf5dfe 888 spinlock_t nvmet_io_wait_lock; /* IOs waiting for ctx resources */
8b017a30 889 uint32_t physical_port;
7bb03bbf
JS		 890
891 /* CPU to vector mapping information */
892 struct lpfc_vector_map_info *cpu_map;
222e9239 893 uint16_t num_possible_cpu;
7bb03bbf 894 uint16_t num_present_cpu;
76fd07a6 895 uint16_t curr_disp_cpu;
32517fc0 896 struct lpfc_eq_intr_info __percpu *eq_info;
1dc5ec24
JS		 897 uint32_t conf_trunk;
898#define lpfc_conf_trunk_port0_WORD conf_trunk
899#define lpfc_conf_trunk_port0_SHIFT 0
900#define lpfc_conf_trunk_port0_MASK 0x1
901#define lpfc_conf_trunk_port1_WORD conf_trunk
902#define lpfc_conf_trunk_port1_SHIFT 1
903#define lpfc_conf_trunk_port1_MASK 0x1
904#define lpfc_conf_trunk_port2_WORD conf_trunk
905#define lpfc_conf_trunk_port2_SHIFT 2
906#define lpfc_conf_trunk_port2_MASK 0x1
907#define lpfc_conf_trunk_port3_WORD conf_trunk
908#define lpfc_conf_trunk_port3_SHIFT 3
909#define lpfc_conf_trunk_port3_MASK 0x1
da0436e9
JS		 910};
911
912enum lpfc_sge_type {
913 GEN_BUFF_TYPE,
895427bd 914 SCSI_BUFF_TYPE,
f358dd0c 915 NVMET_BUFF_TYPE
da0436e9
JS		 916};
917
0f65ff68
JS		 918enum lpfc_sgl_state {
919 SGL_FREED,
920 SGL_ALLOCATED,
921 SGL_XRI_ABORTED
922};
923
da0436e9
JS		 924struct lpfc_sglq {
925 /* lpfc_sglqs are used in double linked lists */
926 struct list_head list;
927 struct list_head clist;
928 enum lpfc_sge_type buff_type; /* is this a scsi sgl */
0f65ff68 929 enum lpfc_sgl_state state;
19ca7609 930 struct lpfc_nodelist *ndlp; /* ndlp associated with IO */
da0436e9 931 uint16_t iotag; /* pre-assigned IO tag */
6d368e53 932 uint16_t sli4_lxritag; /* logical pre-assigned xri. */
da0436e9
JS		 933 uint16_t sli4_xritag; /* pre-assigned XRI, (OXID) tag. */
934 struct sli4_sge *sgl; /* pre-assigned SGL */
935 void *virt; /* virtual address. */
936 dma_addr_t phys; /* physical address */
937};
938
939struct lpfc_rpi_hdr {
940 struct list_head list;
941 uint32_t len;
942 struct lpfc_dmabuf *dmabuf;
943 uint32_t page_count;
944 uint32_t start_rpi;
845d9e8d 945 uint16_t next_rpi;
da0436e9
JS		 946};
947
6d368e53
JS		 948struct lpfc_rsrc_blks {
949 struct list_head list;
950 uint16_t rsrc_start;
951 uint16_t rsrc_size;
952 uint16_t rsrc_used;
953};
954
86478875
JS		 955struct lpfc_rdp_context {
956 struct lpfc_nodelist *ndlp;
957 uint16_t ox_id;
958 uint16_t rx_id;
959 READ_LNK_VAR link_stat;
960 uint8_t page_a0[DMP_SFF_PAGE_A0_SIZE];
961 uint8_t page_a2[DMP_SFF_PAGE_A2_SIZE];
962 void (*cmpl)(struct lpfc_hba *, struct lpfc_rdp_context*, int);
963};
964
8b017a30
JS		 965struct lpfc_lcb_context {
966 uint8_t sub_command;
967 uint8_t type;
66e9e6bf 968 uint8_t capability;
8b017a30 969 uint8_t frequency;
66e9e6bf 970 uint16_t duration;
8b017a30
JS		 971 uint16_t ox_id;
972 uint16_t rx_id;
973 struct lpfc_nodelist *ndlp;
974};
975
976
da0436e9
JS		 977/*
978 * SLI4 specific function prototypes
979 */
980int lpfc_pci_function_reset(struct lpfc_hba *);
73d91e50 981int lpfc_sli4_pdev_status_reg_wait(struct lpfc_hba *);
da0436e9 982int lpfc_sli4_hba_setup(struct lpfc_hba *);
da0436e9
JS		 983int lpfc_sli4_config(struct lpfc_hba *, struct lpfcMboxq *, uint8_t,
984 uint8_t, uint32_t, bool);
985void lpfc_sli4_mbox_cmd_free(struct lpfc_hba *, struct lpfcMboxq *);
986void lpfc_sli4_mbx_sge_set(struct lpfcMboxq *, uint32_t, dma_addr_t, uint32_t);
987void lpfc_sli4_mbx_sge_get(struct lpfcMboxq *, uint32_t,
988 struct lpfc_mbx_sge *);
0c9ab6f5
JS		 989int lpfc_sli4_mbx_read_fcf_rec(struct lpfc_hba *, struct lpfcMboxq *,
990 uint16_t);
da0436e9
JS		 991
992void lpfc_sli4_hba_reset(struct lpfc_hba *);
993struct lpfc_queue *lpfc_sli4_queue_alloc(struct lpfc_hba *, uint32_t,
81b96eda 994 uint32_t, uint32_t);
da0436e9 995void lpfc_sli4_queue_free(struct lpfc_queue *);
a2fc4aef 996int lpfc_eq_create(struct lpfc_hba *, struct lpfc_queue *, uint32_t);
cb733e35
JS		 997void lpfc_modify_hba_eq_delay(struct lpfc_hba *phba, uint32_t startq,
998 uint32_t numq, uint32_t usdelay);
a2fc4aef 999int lpfc_cq_create(struct lpfc_hba *, struct lpfc_queue *,
da0436e9 1000 struct lpfc_queue *, uint32_t, uint32_t);
2d7dbc4c 1001int lpfc_cq_create_set(struct lpfc_hba *phba, struct lpfc_queue **cqp,
cdb42bec 1002 struct lpfc_sli4_hdw_queue *hdwq, uint32_t type,
2d7dbc4c 1003 uint32_t subtype);
b19a061a
JS		 1004int32_t lpfc_mq_create(struct lpfc_hba *, struct lpfc_queue *,
1005 struct lpfc_queue *, uint32_t);
a2fc4aef 1006int lpfc_wq_create(struct lpfc_hba *, struct lpfc_queue *,
da0436e9 1007 struct lpfc_queue *, uint32_t);
a2fc4aef 1008int lpfc_rq_create(struct lpfc_hba *, struct lpfc_queue *,
da0436e9 1009 struct lpfc_queue *, struct lpfc_queue *, uint32_t);
2d7dbc4c
JS		 1010int lpfc_mrq_create(struct lpfc_hba *phba, struct lpfc_queue **hrqp,
1011 struct lpfc_queue **drqp, struct lpfc_queue **cqp,
1012 uint32_t subtype);
a2fc4aef
JS		 1013int lpfc_eq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1014int lpfc_cq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1015int lpfc_mq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1016int lpfc_wq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1017int lpfc_rq_destroy(struct lpfc_hba *, struct lpfc_queue *,
da0436e9
JS		 1018 struct lpfc_queue *);
1019int lpfc_sli4_queue_setup(struct lpfc_hba *);
1020void lpfc_sli4_queue_unset(struct lpfc_hba *);
1021int lpfc_sli4_post_sgl(struct lpfc_hba *, dma_addr_t, dma_addr_t, uint16_t);
5e5b511d 1022int lpfc_repost_io_sgl_list(struct lpfc_hba *phba);
da0436e9 1023uint16_t lpfc_sli4_next_xritag(struct lpfc_hba *);
f7bc6434 1024void lpfc_sli4_free_xri(struct lpfc_hba *, int);
da0436e9 1025int lpfc_sli4_post_async_mbox(struct lpfc_hba *);
da0436e9
JS		 1026struct lpfc_cq_event *__lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
1027struct lpfc_cq_event *lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
1028void __lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
1029void lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
1030int lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *);
1031int lpfc_sli4_post_rpi_hdr(struct lpfc_hba *, struct lpfc_rpi_hdr *);
1032int lpfc_sli4_post_all_rpi_hdrs(struct lpfc_hba *);
1033struct lpfc_rpi_hdr *lpfc_sli4_create_rpi_hdr(struct lpfc_hba *);
1034void lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *);
1035int lpfc_sli4_alloc_rpi(struct lpfc_hba *);
1036void lpfc_sli4_free_rpi(struct lpfc_hba *, int);
1037void lpfc_sli4_remove_rpis(struct lpfc_hba *);
1038void lpfc_sli4_async_event_proc(struct lpfc_hba *);
ecfd03c6 1039void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *);
6b5151fd
JS		 1040int lpfc_sli4_resume_rpi(struct lpfc_nodelist *,
1041 void (*)(struct lpfc_hba *, LPFC_MBOXQ_t *), void *);
da0436e9
JS		 1042void lpfc_sli4_fcp_xri_abort_event_proc(struct lpfc_hba *);
1043void lpfc_sli4_els_xri_abort_event_proc(struct lpfc_hba *);
1044void lpfc_sli4_fcp_xri_aborted(struct lpfc_hba *,
5e5b511d 1045 struct sli4_wcqe_xri_aborted *, int);
318083ad 1046void lpfc_sli4_nvme_xri_aborted(struct lpfc_hba *phba,
5e5b511d 1047 struct sli4_wcqe_xri_aborted *axri, int idx);
318083ad
JS		 1048void lpfc_sli4_nvmet_xri_aborted(struct lpfc_hba *phba,
1049 struct sli4_wcqe_xri_aborted *axri);
da0436e9
JS		 1050void lpfc_sli4_els_xri_aborted(struct lpfc_hba *,
1051 struct sli4_wcqe_xri_aborted *);
1151e3ec
JS		 1052void lpfc_sli4_vport_delete_els_xri_aborted(struct lpfc_vport *);
1053void lpfc_sli4_vport_delete_fcp_xri_aborted(struct lpfc_vport *);
da0436e9
JS		 1054int lpfc_sli4_brdreset(struct lpfc_hba *);
1055int lpfc_sli4_add_fcf_record(struct lpfc_hba *, struct fcf_record *);
1056void lpfc_sli_remove_dflt_fcf(struct lpfc_hba *);
1057int lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *);
895427bd 1058int lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba);
76a95d75 1059int lpfc_sli4_init_vpi(struct lpfc_vport *);
b71413dd 1060inline void lpfc_sli4_eq_clr_intr(struct lpfc_queue *);
32517fc0
JS		 1061void lpfc_sli4_write_cq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1062 uint32_t count, bool arm);
1063void lpfc_sli4_write_eq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1064 uint32_t count, bool arm);
27d6ac0a 1065inline void lpfc_sli4_if6_eq_clr_intr(struct lpfc_queue *q);
32517fc0
JS		 1066void lpfc_sli4_if6_write_cq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1067 uint32_t count, bool arm);
1068void lpfc_sli4_if6_write_eq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1069 uint32_t count, bool arm);
da0436e9 1070void lpfc_sli4_fcfi_unreg(struct lpfc_hba *, uint16_t);
0c9ab6f5
JS		 1071int lpfc_sli4_fcf_scan_read_fcf_rec(struct lpfc_hba *, uint16_t);
1072int lpfc_sli4_fcf_rr_read_fcf_rec(struct lpfc_hba *, uint16_t);
1073int lpfc_sli4_read_fcf_rec(struct lpfc_hba *, uint16_t);
1074void lpfc_mbx_cmpl_fcf_scan_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
1075void lpfc_mbx_cmpl_fcf_rr_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
1076void lpfc_mbx_cmpl_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
1077int lpfc_sli4_unregister_fcf(struct lpfc_hba *);
da0436e9 1078int lpfc_sli4_post_status_check(struct lpfc_hba *);
a183a15f
JS		 1079uint8_t lpfc_sli_config_mbox_subsys_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
1080uint8_t lpfc_sli_config_mbox_opcode_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
d2cc9bcd 1081void lpfc_sli4_ras_dma_free(struct lpfc_hba *phba);
Linux 6.x block layer and io_uring tree(s)