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scsi: lpfc: Revise interrupt coalescing for missing scenarios
[linux-2.6-block.git] / drivers / scsi / lpfc / lpfc_sli4.h
CommitLineData
da0436e9
JS		 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
0d041215 4 * Copyright (C) 2017-2019 Broadcom. All Rights Reserved. The term *
4ae2ebde 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
51f4ca3c 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. *
da0436e9 7 * EMULEX and SLI are trademarks of Emulex. *
d080abe0 8 * www.broadcom.com *
da0436e9
JS		 9 * *
10 * This program is free software; you can redistribute it and/or *
11 * modify it under the terms of version 2 of the GNU General *
12 * Public License as published by the Free Software Foundation. *
13 * This program is distributed in the hope that it will be useful. *
14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18 * TO BE LEGALLY INVALID. See the GNU General Public License for *
19 * more details, a copy of which can be found in the file COPYING *
20 * included with this package. *
21 *******************************************************************/
22
63df6d63
JS		 23#if defined(CONFIG_DEBUG_FS) && !defined(CONFIG_SCSI_LPFC_DEBUG_FS)
24#define CONFIG_SCSI_LPFC_DEBUG_FS
25#endif
26
da0436e9 27#define LPFC_ACTIVE_MBOX_WAIT_CNT 100
5af5eee7
JS		 28#define LPFC_XRI_EXCH_BUSY_WAIT_TMO 10000
29#define LPFC_XRI_EXCH_BUSY_WAIT_T1 10
30#define LPFC_XRI_EXCH_BUSY_WAIT_T2 30000
da0436e9 31#define LPFC_RPI_LOW_WATER_MARK 10
ecfd03c6 32
a93ff37a
JS		 33#define LPFC_UNREG_FCF 1
34#define LPFC_SKIP_UNREG_FCF 0
35
ecfd03c6
JS		 36/* Amount of time in seconds for waiting FCF rediscovery to complete */
37#define LPFC_FCF_REDISCOVER_WAIT_TMO 2000 /* msec */
38
da0436e9
JS		 39/* Number of SGL entries can be posted in a 4KB nonembedded mbox command */
40#define LPFC_NEMBED_MBOX_SGL_CNT 254
41
67d12733 42/* Multi-queue arrangement for FCP EQ/CQ/WQ tuples */
cdb42bec 43#define LPFC_HBA_HDWQ_MIN 0
6a828b0f 44#define LPFC_HBA_HDWQ_MAX 128
cdb42bec 45#define LPFC_HBA_HDWQ_DEF 0
da0436e9 46
77ffd346
JS		 47/* FCP MQ queue count limiting */
48#define LPFC_FCP_MQ_THRESHOLD_MIN 0
0622800d 49#define LPFC_FCP_MQ_THRESHOLD_MAX 256
77ffd346
JS		 50#define LPFC_FCP_MQ_THRESHOLD_DEF 8
51
da0436e9
JS		 52/*
53 * Provide the default FCF Record attributes used by the driver
54 * when nonFIP mode is configured and there is no other default
55 * FCF Record attributes.
56 */
57#define LPFC_FCOE_FCF_DEF_INDEX 0
58#define LPFC_FCOE_FCF_GET_FIRST 0xFFFF
59#define LPFC_FCOE_FCF_NEXT_NONE 0xFFFF
60
dbb6b3ab
JS		 61#define LPFC_FCOE_NULL_VID 0xFFF
62#define LPFC_FCOE_IGNORE_VID 0xFFFF
63
da0436e9
JS		 64/* First 3 bytes of default FCF MAC is specified by FC_MAP */
65#define LPFC_FCOE_FCF_MAC3 0xFF
66#define LPFC_FCOE_FCF_MAC4 0xFF
67#define LPFC_FCOE_FCF_MAC5 0xFE
68#define LPFC_FCOE_FCF_MAP0 0x0E
69#define LPFC_FCOE_FCF_MAP1 0xFC
70#define LPFC_FCOE_FCF_MAP2 0x00
98fc5dd9 71#define LPFC_FCOE_MAX_RCV_SIZE 0x800
da0436e9
JS		 72#define LPFC_FCOE_FKA_ADV_PER 0
73#define LPFC_FCOE_FIP_PRIORITY 0x80
74
6669f9bb
JS		 75#define sli4_sid_from_fc_hdr(fc_hdr) \
76 ((fc_hdr)->fh_s_id[0] << 16 | \
77 (fc_hdr)->fh_s_id[1] << 8 | \
78 (fc_hdr)->fh_s_id[2])
79
939723a4
JS		 80#define sli4_did_from_fc_hdr(fc_hdr) \
81 ((fc_hdr)->fh_d_id[0] << 16 | \
82 (fc_hdr)->fh_d_id[1] << 8 | \
83 (fc_hdr)->fh_d_id[2])
84
5ffc266e
JS		 85#define sli4_fctl_from_fc_hdr(fc_hdr) \
86 ((fc_hdr)->fh_f_ctl[0] << 16 | \
87 (fc_hdr)->fh_f_ctl[1] << 8 | \
88 (fc_hdr)->fh_f_ctl[2])
89
939723a4
JS		 90#define sli4_type_from_fc_hdr(fc_hdr) \
91 ((fc_hdr)->fh_type)
92
88a2cfbb
JS		 93#define LPFC_FW_RESET_MAXIMUM_WAIT_10MS_CNT 12000
94
c71ab861
JS		 95#define INT_FW_UPGRADE 0
96#define RUN_FW_UPGRADE 1
97
da0436e9
JS		 98enum lpfc_sli4_queue_type {
99 LPFC_EQ,
100 LPFC_GCQ,
101 LPFC_MCQ,
102 LPFC_WCQ,
103 LPFC_RCQ,
104 LPFC_MQ,
105 LPFC_WQ,
106 LPFC_HRQ,
107 LPFC_DRQ
108};
109
110/* The queue sub-type defines the functional purpose of the queue */
111enum lpfc_sli4_queue_subtype {
112 LPFC_NONE,
113 LPFC_MBOX,
c00f62e6 114 LPFC_IO,
da0436e9 115 LPFC_ELS,
f358dd0c 116 LPFC_NVMET,
895427bd 117 LPFC_NVME_LS,
da0436e9
JS		 118 LPFC_USOL
119};
120
895427bd
JS		 121/* RQ buffer list */
122struct lpfc_rqb {
123 uint16_t entry_count; /* Current number of RQ slots */
124 uint16_t buffer_count; /* Current number of buffers posted */
125 struct list_head rqb_buffer_list; /* buffers assigned to this HBQ */
126 /* Callback for HBQ buffer allocation */
127 struct rqb_dmabuf *(*rqb_alloc_buffer)(struct lpfc_hba *);
128 /* Callback for HBQ buffer free */
129 void (*rqb_free_buffer)(struct lpfc_hba *,
130 struct rqb_dmabuf *);
131};
132
da0436e9
JS		 133struct lpfc_queue {
134 struct list_head list;
895427bd 135 struct list_head wq_list;
6e8e1c14 136 struct list_head wqfull_list;
da0436e9
JS		 137 enum lpfc_sli4_queue_type type;
138 enum lpfc_sli4_queue_subtype subtype;
139 struct lpfc_hba *phba;
140 struct list_head child_list;
895427bd
JS		 141 struct list_head page_list;
142 struct list_head sgl_list;
32517fc0 143 struct list_head cpu_list;
da0436e9
JS		 144 uint32_t entry_count; /* Number of entries to support on the queue */
145 uint32_t entry_size; /* Size of each queue entry. */
9afbee3d 146 uint32_t entry_cnt_per_pg;
32517fc0
JS		 147 uint32_t notify_interval; /* Queue Notification Interval
148 * For chip->host queues (EQ, CQ, RQ):
149 * specifies the interval (number of
150 * entries) where the doorbell is rung to
151 * notify the chip of entry consumption.
152 * For host->chip queues (WQ):
153 * specifies the interval (number of
154 * entries) where consumption CQE is
155 * requested to indicate WQ entries
156 * consumed by the chip.
157 * Not used on an MQ.
158 */
159#define LPFC_EQ_NOTIFY_INTRVL 16
160#define LPFC_CQ_NOTIFY_INTRVL 16
161#define LPFC_WQ_NOTIFY_INTRVL 16
162#define LPFC_RQ_NOTIFY_INTRVL 16
163 uint32_t max_proc_limit; /* Queue Processing Limit
164 * For chip->host queues (EQ, CQ):
165 * specifies the maximum number of
166 * entries to be consumed in one
167 * processing iteration sequence. Queue
168 * will be rearmed after each iteration.
169 * Not used on an MQ, RQ or WQ.
170 */
171#define LPFC_EQ_MAX_PROC_LIMIT 256
172#define LPFC_CQ_MIN_PROC_LIMIT 64
173#define LPFC_CQ_MAX_PROC_LIMIT LPFC_CQE_EXP_COUNT // 4096
174#define LPFC_CQ_DEF_MAX_PROC_LIMIT LPFC_CQE_DEF_COUNT // 1024
175#define LPFC_CQ_MIN_THRESHOLD_TO_POLL 64
176#define LPFC_CQ_MAX_THRESHOLD_TO_POLL LPFC_CQ_DEF_MAX_PROC_LIMIT
177#define LPFC_CQ_DEF_THRESHOLD_TO_POLL LPFC_CQ_DEF_MAX_PROC_LIMIT
178 uint32_t queue_claimed; /* indicates queue is being processed */
da0436e9 179 uint32_t queue_id; /* Queue ID assigned by the hardware */
2a622bfb 180 uint32_t assoc_qid; /* Queue ID associated with, for CQ/WQ/MQ */
da0436e9
JS		 181 uint32_t host_index; /* The host's index for putting or getting */
182 uint32_t hba_index; /* The last known hba index for get or put */
6a828b0f 183 uint32_t q_mode;
b84daac9 184
2a76a283 185 struct lpfc_sli_ring *pring; /* ptr to io ring associated with q */
895427bd 186 struct lpfc_rqb *rqbp; /* ptr to RQ buffers */
2a76a283 187
81b96eda
JS		 188 uint16_t page_count; /* Number of pages allocated for this queue */
189 uint16_t page_size; /* size of page allocated for this queue */
a51e41b6 190#define LPFC_EXPANDED_PAGE_SIZE 16384
81b96eda 191#define LPFC_DEFAULT_PAGE_SIZE 4096
6a828b0f
JS		 192 uint16_t chann; /* Hardware Queue association WQ/CQ */
193 /* CPU affinity for EQ */
194#define LPFC_FIND_BY_EQ 0
195#define LPFC_FIND_BY_HDWQ 1
6e8e1c14 196 uint8_t db_format;
962bc51b
JS		 197#define LPFC_DB_RING_FORMAT 0x01
198#define LPFC_DB_LIST_FORMAT 0x02
6e8e1c14
JS		 199 uint8_t q_flag;
200#define HBA_NVMET_WQFULL 0x1 /* We hit WQ Full condition for NVMET */
d74a89aa 201#define HBA_NVMET_CQ_NOTIFY 0x1 /* LPFC_NVMET_CQ_NOTIFY CQEs this EQE */
8156d378 202#define HBA_EQ_DELAY_CHK 0x2 /* EQ is a candidate for coalescing */
d74a89aa 203#define LPFC_NVMET_CQ_NOTIFY 4
962bc51b 204 void __iomem *db_regaddr;
1351e69f
JS		 205 uint16_t dpp_enable;
206 uint16_t dpp_id;
207 void __iomem *dpp_regaddr;
208
b84daac9
JS		 209 /* For q stats */
210 uint32_t q_cnt_1;
211 uint32_t q_cnt_2;
212 uint32_t q_cnt_3;
213 uint64_t q_cnt_4;
214/* defines for EQ stats */
215#define EQ_max_eqe q_cnt_1
216#define EQ_no_entry q_cnt_2
0cf07f84 217#define EQ_cqe_cnt q_cnt_3
b84daac9
JS		 218#define EQ_processed q_cnt_4
219
220/* defines for CQ stats */
221#define CQ_mbox q_cnt_1
222#define CQ_max_cqe q_cnt_1
223#define CQ_release_wqe q_cnt_2
224#define CQ_xri_aborted q_cnt_3
225#define CQ_wq q_cnt_4
226
227/* defines for WQ stats */
228#define WQ_overflow q_cnt_1
229#define WQ_posted q_cnt_4
230
231/* defines for RQ stats */
232#define RQ_no_posted_buf q_cnt_1
233#define RQ_no_buf_found q_cnt_2
547077a4 234#define RQ_buf_posted q_cnt_3
b84daac9
JS		 235#define RQ_rcv_buf q_cnt_4
236
32517fc0
JS		 237 struct work_struct irqwork;
238 struct work_struct spwork;
239 struct delayed_work sched_irqwork;
240 struct delayed_work sched_spwork;
f485c18d 241
895427bd 242 uint64_t isr_timestamp;
5e5b511d 243 uint16_t hdwq;
32517fc0 244 uint16_t last_cpu; /* most recent cpu */
7365f6fd 245 uint8_t qe_valid;
895427bd 246 struct lpfc_queue *assoc_qp;
9afbee3d 247 void **q_pgs; /* array to index entries per page */
da0436e9
JS		 248};
249
da0436e9 250struct lpfc_sli4_link {
f3339800 251 uint32_t speed;
da0436e9
JS		 252 uint8_t duplex;
253 uint8_t status;
70f3c073
JS		 254 uint8_t type;
255 uint8_t number;
da0436e9 256 uint8_t fault;
f3339800 257 uint32_t logical_speed;
70f3c073 258 uint16_t topology;
da0436e9
JS		 259};
260
ecfd03c6
JS		 261struct lpfc_fcf_rec {
262 uint8_t fabric_name[8];
263 uint8_t switch_name[8];
da0436e9
JS		 264 uint8_t mac_addr[6];
265 uint16_t fcf_indx;
ecfd03c6
JS		 266 uint32_t priority;
267 uint16_t vlan_id;
268 uint32_t addr_mode;
269 uint32_t flag;
270#define BOOT_ENABLE 0x01
271#define RECORD_VALID 0x02
272};
273
7d791df7
JS		 274struct lpfc_fcf_pri_rec {
275 uint16_t fcf_index;
276#define LPFC_FCF_ON_PRI_LIST 0x0001
277#define LPFC_FCF_FLOGI_FAILED 0x0002
278 uint16_t flag;
279 uint32_t priority;
280};
281
282struct lpfc_fcf_pri {
283 struct list_head list;
284 struct lpfc_fcf_pri_rec fcf_rec;
285};
286
287/*
288 * Maximum FCF table index, it is for driver internal book keeping, it
289 * just needs to be no less than the supported HBA's FCF table size.
290 */
291#define LPFC_SLI4_FCF_TBL_INDX_MAX 32
292
ecfd03c6 293struct lpfc_fcf {
da0436e9
JS		 294 uint16_t fcfi;
295 uint32_t fcf_flag;
296#define FCF_AVAILABLE 0x01 /* FCF available for discovery */
297#define FCF_REGISTERED 0x02 /* FCF registered with FW */
ecfd03c6
JS		 298#define FCF_SCAN_DONE 0x04 /* FCF table scan done */
299#define FCF_IN_USE 0x08 /* Atleast one discovery completed */
0c9ab6f5
JS		 300#define FCF_INIT_DISC 0x10 /* Initial FCF discovery */
301#define FCF_DEAD_DISC 0x20 /* FCF DEAD fast FCF failover discovery */
302#define FCF_ACVL_DISC 0x40 /* All CVL fast FCF failover discovery */
303#define FCF_DISCOVERY (FCF_INIT_DISC | FCF_DEAD_DISC | FCF_ACVL_DISC)
304#define FCF_REDISC_PEND 0x80 /* FCF rediscovery pending */
305#define FCF_REDISC_EVT 0x100 /* FCF rediscovery event to worker thread */
306#define FCF_REDISC_FOV 0x200 /* Post FCF rediscovery fast failover */
a93ff37a 307#define FCF_REDISC_PROG (FCF_REDISC_PEND | FCF_REDISC_EVT)
036cad1f 308 uint16_t fcf_redisc_attempted;
da0436e9 309 uint32_t addr_mode;
999d813f 310 uint32_t eligible_fcf_cnt;
ecfd03c6
JS		 311 struct lpfc_fcf_rec current_rec;
312 struct lpfc_fcf_rec failover_rec;
7d791df7
JS		 313 struct list_head fcf_pri_list;
314 struct lpfc_fcf_pri fcf_pri[LPFC_SLI4_FCF_TBL_INDX_MAX];
315 uint32_t current_fcf_scan_pri;
ecfd03c6 316 struct timer_list redisc_wait;
0c9ab6f5 317 unsigned long *fcf_rr_bmask; /* Eligible FCF indexes for RR failover */
da0436e9
JS		 318};
319
0c9ab6f5 320
da0436e9
JS		 321#define LPFC_REGION23_SIGNATURE "RG23"
322#define LPFC_REGION23_VERSION 1
323#define LPFC_REGION23_LAST_REC 0xff
a0c87cbd
JS		 324#define DRIVER_SPECIFIC_TYPE 0xA2
325#define LINUX_DRIVER_ID 0x20
326#define PORT_STE_TYPE 0x1
327
da0436e9
JS		 328struct lpfc_fip_param_hdr {
329 uint8_t type;
330#define FCOE_PARAM_TYPE 0xA0
331 uint8_t length;
332#define FCOE_PARAM_LENGTH 2
333 uint8_t parm_version;
334#define FIPP_VERSION 0x01
335 uint8_t parm_flags;
336#define lpfc_fip_param_hdr_fipp_mode_SHIFT 6
337#define lpfc_fip_param_hdr_fipp_mode_MASK 0x3
338#define lpfc_fip_param_hdr_fipp_mode_WORD parm_flags
6a9c52cf 339#define FIPP_MODE_ON 0x1
da0436e9
JS		 340#define FIPP_MODE_OFF 0x0
341#define FIPP_VLAN_VALID 0x1
342};
343
344struct lpfc_fcoe_params {
345 uint8_t fc_map[3];
346 uint8_t reserved1;
347 uint16_t vlan_tag;
348 uint8_t reserved[2];
349};
350
351struct lpfc_fcf_conn_hdr {
352 uint8_t type;
353#define FCOE_CONN_TBL_TYPE 0xA1
354 uint8_t length; /* words */
355 uint8_t reserved[2];
356};
357
358struct lpfc_fcf_conn_rec {
359 uint16_t flags;
360#define FCFCNCT_VALID 0x0001
361#define FCFCNCT_BOOT 0x0002
362#define FCFCNCT_PRIMARY 0x0004 /* if not set, Secondary */
363#define FCFCNCT_FBNM_VALID 0x0008
364#define FCFCNCT_SWNM_VALID 0x0010
365#define FCFCNCT_VLAN_VALID 0x0020
366#define FCFCNCT_AM_VALID 0x0040
367#define FCFCNCT_AM_PREFERRED 0x0080 /* if not set, AM Required */
368#define FCFCNCT_AM_SPMA 0x0100 /* if not set, FPMA */
369
370 uint16_t vlan_tag;
371 uint8_t fabric_name[8];
372 uint8_t switch_name[8];
373};
374
375struct lpfc_fcf_conn_entry {
376 struct list_head list;
377 struct lpfc_fcf_conn_rec conn_rec;
378};
379
380/*
381 * Define the host's bootstrap mailbox. This structure contains
382 * the member attributes needed to create, use, and destroy the
383 * bootstrap mailbox region.
384 *
385 * The macro definitions for the bmbx data structure are defined
386 * in lpfc_hw4.h with the register definition.
387 */
388struct lpfc_bmbx {
389 struct lpfc_dmabuf *dmabuf;
390 struct dma_address dma_address;
391 void *avirt;
392 dma_addr_t aphys;
393 uint32_t bmbx_size;
394};
395
396#define LPFC_EQE_SIZE LPFC_EQE_SIZE_4
397
398#define LPFC_EQE_SIZE_4B 4
399#define LPFC_EQE_SIZE_16B 16
400#define LPFC_CQE_SIZE 16
401#define LPFC_WQE_SIZE 64
0c651878 402#define LPFC_WQE128_SIZE 128
da0436e9
JS		 403#define LPFC_MQE_SIZE 256
404#define LPFC_RQE_SIZE 8
405
406#define LPFC_EQE_DEF_COUNT 1024
ff78d8f9 407#define LPFC_CQE_DEF_COUNT 1024
a51e41b6 408#define LPFC_CQE_EXP_COUNT 4096
f1126688 409#define LPFC_WQE_DEF_COUNT 256
a51e41b6 410#define LPFC_WQE_EXP_COUNT 1024
da0436e9
JS		 411#define LPFC_MQE_DEF_COUNT 16
412#define LPFC_RQE_DEF_COUNT 512
413
414#define LPFC_QUEUE_NOARM false
415#define LPFC_QUEUE_REARM true
416
417
418/*
419 * SLI4 CT field defines
420 */
421#define SLI4_CT_RPI 0
422#define SLI4_CT_VPI 1
423#define SLI4_CT_VFI 2
424#define SLI4_CT_FCFI 3
425
da0436e9
JS		 426/*
427 * SLI4 specific data structures
428 */
429struct lpfc_max_cfg_param {
430 uint16_t max_xri;
431 uint16_t xri_base;
432 uint16_t xri_used;
433 uint16_t max_rpi;
434 uint16_t rpi_base;
435 uint16_t rpi_used;
436 uint16_t max_vpi;
437 uint16_t vpi_base;
438 uint16_t vpi_used;
439 uint16_t max_vfi;
440 uint16_t vfi_base;
441 uint16_t vfi_used;
442 uint16_t max_fcfi;
da0436e9
JS		 443 uint16_t fcfi_used;
444 uint16_t max_eq;
445 uint16_t max_rq;
446 uint16_t max_cq;
447 uint16_t max_wq;
448};
449
450struct lpfc_hba;
451/* SLI4 HBA multi-fcp queue handler struct */
b83d005e 452#define LPFC_SLI4_HANDLER_NAME_SZ 16
895427bd 453struct lpfc_hba_eq_hdl {
da0436e9 454 uint32_t idx;
b83d005e 455 char handler_name[LPFC_SLI4_HANDLER_NAME_SZ];
da0436e9 456 struct lpfc_hba *phba;
657add4e 457 struct lpfc_queue *eq;
da0436e9
JS		 458};
459
44fd7fe3
JS		 460/*BB Credit recovery value*/
461struct lpfc_bbscn_params {
462 uint32_t word0;
463#define lpfc_bbscn_min_SHIFT 0
464#define lpfc_bbscn_min_MASK 0x0000000F
465#define lpfc_bbscn_min_WORD word0
466#define lpfc_bbscn_max_SHIFT 4
467#define lpfc_bbscn_max_MASK 0x0000000F
468#define lpfc_bbscn_max_WORD word0
469#define lpfc_bbscn_def_SHIFT 8
470#define lpfc_bbscn_def_MASK 0x0000000F
471#define lpfc_bbscn_def_WORD word0
472};
473
28baac74
JS		 474/* Port Capabilities for SLI4 Parameters */
475struct lpfc_pc_sli4_params {
476 uint32_t supported;
477 uint32_t if_type;
478 uint32_t sli_rev;
479 uint32_t sli_family;
480 uint32_t featurelevel_1;
481 uint32_t featurelevel_2;
482 uint32_t proto_types;
483#define LPFC_SLI4_PROTO_FCOE 0x0000001
484#define LPFC_SLI4_PROTO_FC 0x0000002
485#define LPFC_SLI4_PROTO_NIC 0x0000004
486#define LPFC_SLI4_PROTO_ISCSI 0x0000008
487#define LPFC_SLI4_PROTO_RDMA 0x0000010
488 uint32_t sge_supp_len;
489 uint32_t if_page_sz;
490 uint32_t rq_db_window;
491 uint32_t loopbk_scope;
1ba981fd 492 uint32_t oas_supported;
28baac74
JS		 493 uint32_t eq_pages_max;
494 uint32_t eqe_size;
495 uint32_t cq_pages_max;
496 uint32_t cqe_size;
497 uint32_t mq_pages_max;
498 uint32_t mqe_size;
499 uint32_t mq_elem_cnt;
500 uint32_t wq_pages_max;
501 uint32_t wqe_size;
502 uint32_t rq_pages_max;
503 uint32_t rqe_size;
504 uint32_t hdr_pages_max;
505 uint32_t hdr_size;
506 uint32_t hdr_pp_align;
507 uint32_t sgl_pages_max;
508 uint32_t sgl_pp_align;
fedd3b7b
JS		 509 uint8_t cqv;
510 uint8_t mqv;
511 uint8_t wqv;
512 uint8_t rqv;
7365f6fd
JS		 513 uint8_t eqav;
514 uint8_t cqav;
0c651878 515 uint8_t wqsize;
66e9e6bf 516 uint8_t bv1s;
0c651878
JS		 517#define LPFC_WQ_SZ64_SUPPORT 1
518#define LPFC_WQ_SZ128_SUPPORT 2
895427bd 519 uint8_t wqpcnt;
c15e0704 520 uint8_t nvme;
28baac74
JS		 521};
522
c176ffa0
JS		 523#define LPFC_CQ_4K_PAGE_SZ 0x1
524#define LPFC_CQ_16K_PAGE_SZ 0x4
525#define LPFC_WQ_4K_PAGE_SZ 0x1
526#define LPFC_WQ_16K_PAGE_SZ 0x4
527
912e3acd
JS		 528struct lpfc_iov {
529 uint32_t pf_number;
530 uint32_t vf_number;
531};
532
cd1c8301
JS		 533struct lpfc_sli4_lnk_info {
534 uint8_t lnk_dv;
535#define LPFC_LNK_DAT_INVAL 0
536#define LPFC_LNK_DAT_VAL 1
537 uint8_t lnk_tp;
9a66d990
JS		 538#define LPFC_LNK_GE 0x0 /* FCoE */
539#define LPFC_LNK_FC 0x1 /* FC */
540#define LPFC_LNK_FC_TRUNKED 0x2 /* FC_Trunked */
cd1c8301 541 uint8_t lnk_no;
448193b5 542 uint8_t optic_state;
cd1c8301
JS		 543};
544
895427bd 545#define LPFC_SLI4_HANDLER_CNT (LPFC_HBA_IO_CHAN_MAX+ \
1ba981fd 546 LPFC_FOF_IO_CHAN_NUM)
4305f183 547
7bb03bbf
JS		 548/* Used for IRQ vector to CPU mapping */
549struct lpfc_vector_map_info {
550 uint16_t phys_id;
551 uint16_t core_id;
552 uint16_t irq;
6a828b0f 553 uint16_t eq;
b3295c2a 554 uint16_t hdwq;
d9954a2d
JS		 555 uint16_t flag;
556#define LPFC_CPU_MAP_HYPER 0x1
557#define LPFC_CPU_MAP_UNASSIGN 0x2
657add4e 558#define LPFC_CPU_FIRST_IRQ 0x4
7bb03bbf
JS		 559};
560#define LPFC_VECTOR_MAP_EMPTY 0xffff
7bb03bbf 561
c490850a
JS		 562/* Multi-XRI pool */
563#define XRI_BATCH 8
564
565struct lpfc_pbl_pool {
566 struct list_head list;
567 u32 count;
568 spinlock_t lock; /* lock for pbl_pool*/
569};
570
571struct lpfc_pvt_pool {
572 u32 low_watermark;
573 u32 high_watermark;
574
575 struct list_head list;
576 u32 count;
577 spinlock_t lock; /* lock for pvt_pool */
578};
579
580struct lpfc_multixri_pool {
581 u32 xri_limit;
582
583 /* Starting point when searching a pbl_pool with round-robin method */
584 u32 rrb_next_hwqid;
585
586 /* Used by lpfc_adjust_pvt_pool_count.
587 * io_req_count is incremented by 1 during IO submission. The heartbeat
588 * handler uses these two variables to determine if pvt_pool is idle or
589 * busy.
590 */
591 u32 prev_io_req_count;
592 u32 io_req_count;
593
594 /* statistics */
595 u32 pbl_empty_count;
596#ifdef LPFC_MXP_STAT
597 u32 above_limit_count;
598 u32 below_limit_count;
599 u32 local_pbl_hit_count;
600 u32 other_pbl_hit_count;
601 u32 stat_max_hwm;
602
603#define LPFC_MXP_SNAPSHOT_TAKEN 3 /* snapshot is taken at 3rd heartbeats */
604 u32 stat_pbl_count;
605 u32 stat_pvt_count;
606 u32 stat_busy_count;
607 u32 stat_snapshot_taken;
608#endif
609
610 /* TODO: Separate pvt_pool into get and put list */
611 struct lpfc_pbl_pool pbl_pool; /* Public free XRI pool */
612 struct lpfc_pvt_pool pvt_pool; /* Private free XRI pool */
613};
614
4c47efc1
JS		 615struct lpfc_fc4_ctrl_stat {
616 u32 input_requests;
617 u32 output_requests;
618 u32 control_requests;
619 u32 io_cmpls;
620};
621
6a828b0f
JS		 622#ifdef LPFC_HDWQ_LOCK_STAT
623struct lpfc_lock_stat {
624 uint32_t alloc_xri_get;
625 uint32_t alloc_xri_put;
626 uint32_t free_xri;
627 uint32_t wq_access;
628 uint32_t alloc_pvt_pool;
629 uint32_t mv_from_pvt_pool;
630 uint32_t mv_to_pub_pool;
631 uint32_t mv_to_pvt_pool;
632 uint32_t free_pub_pool;
633 uint32_t free_pvt_pool;
634};
635#endif
636
32517fc0
JS		 637struct lpfc_eq_intr_info {
638 struct list_head list;
639 uint32_t icnt;
640};
641
da0436e9 642/* SLI4 HBA data structure entries */
cdb42bec
JS		 643struct lpfc_sli4_hdw_queue {
644 /* Pointers to the constructed SLI4 queues */
645 struct lpfc_queue *hba_eq; /* Event queues for HBA */
c00f62e6
JS		 646 struct lpfc_queue *io_cq; /* Fast-path FCP & NVME compl queue */
647 struct lpfc_queue *io_wq; /* Fast-path FCP & NVME work queue */
648 uint16_t io_cq_map;
5e5b511d
JS		 649
650 /* Keep track of IO buffers for this hardware queue */
651 spinlock_t io_buf_list_get_lock; /* Common buf alloc list lock */
652 struct list_head lpfc_io_buf_list_get;
653 spinlock_t io_buf_list_put_lock; /* Common buf free list lock */
654 struct list_head lpfc_io_buf_list_put;
c00f62e6
JS		 655 spinlock_t abts_io_buf_list_lock; /* list of aborted IOs */
656 struct list_head lpfc_abts_io_buf_list;
5e5b511d
JS		 657 uint32_t total_io_bufs;
658 uint32_t get_io_bufs;
659 uint32_t put_io_bufs;
660 uint32_t empty_io_bufs;
661 uint32_t abts_scsi_io_bufs;
662 uint32_t abts_nvme_io_bufs;
63df6d63 663
c490850a
JS		 664 /* Multi-XRI pool per HWQ */
665 struct lpfc_multixri_pool *p_multixri_pool;
666
4c47efc1
JS		 667 /* FC-4 Stats counters */
668 struct lpfc_fc4_ctrl_stat nvme_cstat;
669 struct lpfc_fc4_ctrl_stat scsi_cstat;
6a828b0f
JS		 670#ifdef LPFC_HDWQ_LOCK_STAT
671 struct lpfc_lock_stat lock_conflict;
672#endif
4c47efc1 673
63df6d63
JS		 674#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
675#define LPFC_CHECK_CPU_CNT 128
676 uint32_t cpucheck_rcv_io[LPFC_CHECK_CPU_CNT];
677 uint32_t cpucheck_xmt_io[LPFC_CHECK_CPU_CNT];
678 uint32_t cpucheck_cmpl_io[LPFC_CHECK_CPU_CNT];
679#endif
d79c9e9d
JS		 680
681 /* Per HDWQ pool resources */
682 struct list_head sgl_list;
683 struct list_head cmd_rsp_buf_list;
684
685 /* Lock for syncing Per HDWQ pool resources */
686 spinlock_t hdwq_lock;
cdb42bec
JS		 687};
688
6a828b0f
JS		 689#ifdef LPFC_HDWQ_LOCK_STAT
690/* compile time trylock stats */
691#define lpfc_qp_spin_lock_irqsave(lock, flag, qp, lstat) \
692 { \
693 int only_once = 1; \
694 while (spin_trylock_irqsave(lock, flag) == 0) { \
695 if (only_once) { \
696 only_once = 0; \
697 qp->lock_conflict.lstat++; \
698 } \
699 } \
700 }
701#define lpfc_qp_spin_lock(lock, qp, lstat) \
702 { \
703 int only_once = 1; \
704 while (spin_trylock(lock) == 0) { \
705 if (only_once) { \
706 only_once = 0; \
707 qp->lock_conflict.lstat++; \
708 } \
709 } \
710 }
711#else
712#define lpfc_qp_spin_lock_irqsave(lock, flag, qp, lstat) \
713 spin_lock_irqsave(lock, flag)
714#define lpfc_qp_spin_lock(lock, qp, lstat) spin_lock(lock)
715#endif
716
da0436e9
JS		 717struct lpfc_sli4_hba {
718 void __iomem *conf_regs_memmap_p; /* Kernel memory mapped address for
1351e69f
JS		 719 * config space registers
720 */
da0436e9 721 void __iomem *ctrl_regs_memmap_p; /* Kernel memory mapped address for
1351e69f
JS		 722 * control registers
723 */
da0436e9 724 void __iomem *drbl_regs_memmap_p; /* Kernel memory mapped address for
1351e69f
JS		 725 * doorbell registers
726 */
727 void __iomem *dpp_regs_memmap_p; /* Kernel memory mapped address for
728 * dpp registers
729 */
2fcee4bf
JS		 730 union {
731 struct {
732 /* IF Type 0, BAR 0 PCI cfg space reg mem map */
733 void __iomem *UERRLOregaddr;
734 void __iomem *UERRHIregaddr;
735 void __iomem *UEMASKLOregaddr;
736 void __iomem *UEMASKHIregaddr;
737 } if_type0;
738 struct {
739 /* IF Type 2, BAR 0 PCI cfg space reg mem map. */
740 void __iomem *STATUSregaddr;
741 void __iomem *CTRLregaddr;
742 void __iomem *ERR1regaddr;
2e90f4b5
JS		 743#define SLIPORT_ERR1_REG_ERR_CODE_1 0x1
744#define SLIPORT_ERR1_REG_ERR_CODE_2 0x2
2fcee4bf 745 void __iomem *ERR2regaddr;
2e90f4b5
JS		 746#define SLIPORT_ERR2_REG_FW_RESTART 0x0
747#define SLIPORT_ERR2_REG_FUNC_PROVISON 0x1
748#define SLIPORT_ERR2_REG_FORCED_DUMP 0x2
749#define SLIPORT_ERR2_REG_FAILURE_EQ 0x3
750#define SLIPORT_ERR2_REG_FAILURE_CQ 0x4
751#define SLIPORT_ERR2_REG_FAILURE_BUS 0x5
752#define SLIPORT_ERR2_REG_FAILURE_RQ 0x6
0cf07f84 753 void __iomem *EQDregaddr;
2fcee4bf
JS		 754 } if_type2;
755 } u;
756
757 /* IF type 0, BAR1 and if type 2, Bar 0 CSR register memory map */
758 void __iomem *PSMPHRregaddr;
759
760 /* Well-known SLI INTF register memory map. */
761 void __iomem *SLIINTFregaddr;
762
763 /* IF type 0, BAR 1 function CSR register memory map */
764 void __iomem *ISRregaddr; /* HST_ISR register */
765 void __iomem *IMRregaddr; /* HST_IMR register */
766 void __iomem *ISCRregaddr; /* HST_ISCR register */
767 /* IF type 0, BAR 0 and if type 2, BAR 0 doorbell register memory map */
768 void __iomem *RQDBregaddr; /* RQ_DOORBELL register */
769 void __iomem *WQDBregaddr; /* WQ_DOORBELL register */
9dd35425
JS		 770 void __iomem *CQDBregaddr; /* CQ_DOORBELL register */
771 void __iomem *EQDBregaddr; /* EQ_DOORBELL register */
2fcee4bf
JS		 772 void __iomem *MQDBregaddr; /* MQ_DOORBELL register */
773 void __iomem *BMBXregaddr; /* BootStrap MBX register */
da0436e9 774
a747c9ce
JS		 775 uint32_t ue_mask_lo;
776 uint32_t ue_mask_hi;
65791f1f
JS		 777 uint32_t ue_to_sr;
778 uint32_t ue_to_rp;
28baac74
JS		 779 struct lpfc_register sli_intf;
780 struct lpfc_pc_sli4_params pc_sli4_params;
44fd7fe3 781 struct lpfc_bbscn_params bbscn_params;
895427bd 782 struct lpfc_hba_eq_hdl *hba_eq_hdl; /* HBA per-WQ handle */
67d12733 783
b71413dd 784 void (*sli4_eq_clr_intr)(struct lpfc_queue *q);
32517fc0
JS		 785 void (*sli4_write_eq_db)(struct lpfc_hba *phba, struct lpfc_queue *eq,
786 uint32_t count, bool arm);
787 void (*sli4_write_cq_db)(struct lpfc_hba *phba, struct lpfc_queue *cq,
788 uint32_t count, bool arm);
b71413dd 789
da0436e9 790 /* Pointers to the constructed SLI4 queues */
cdb42bec
JS		 791 struct lpfc_sli4_hdw_queue *hdwq;
792 struct list_head lpfc_wq_list;
793
794 /* Pointers to the constructed SLI4 queues for NVMET */
2d7dbc4c
JS		 795 struct lpfc_queue **nvmet_cqset; /* Fast-path NVMET CQ Set queues */
796 struct lpfc_queue **nvmet_mrq_hdr; /* Fast-path NVMET hdr MRQs */
797 struct lpfc_queue **nvmet_mrq_data; /* Fast-path NVMET data MRQs */
67d12733
JS		 798
799 struct lpfc_queue *mbx_cq; /* Slow-path mailbox complete queue */
800 struct lpfc_queue *els_cq; /* Slow-path ELS response complete queue */
895427bd 801 struct lpfc_queue *nvmels_cq; /* NVME LS complete queue */
da0436e9
JS		 802 struct lpfc_queue *mbx_wq; /* Slow-path MBOX work queue */
803 struct lpfc_queue *els_wq; /* Slow-path ELS work queue */
895427bd 804 struct lpfc_queue *nvmels_wq; /* NVME LS work queue */
da0436e9
JS		 805 struct lpfc_queue *hdr_rq; /* Slow-path Header Receive queue */
806 struct lpfc_queue *dat_rq; /* Slow-path Data Receive queue */
da0436e9 807
895427bd
JS		 808 struct lpfc_name wwnn;
809 struct lpfc_name wwpn;
810
9a86ed48 811 uint32_t fw_func_mode; /* FW function protocol mode */
962bc51b
JS		 812 uint32_t ulp0_mode; /* ULP0 protocol mode */
813 uint32_t ulp1_mode; /* ULP1 protocol mode */
814
1ba981fd 815 /* Optimized Access Storage specific queues/structures */
1ba981fd
JS		 816 uint64_t oas_next_lun;
817 uint8_t oas_next_tgt_wwpn[8];
818 uint8_t oas_next_vpt_wwpn[8];
819
da0436e9
JS		 820 /* Setup information for various queue parameters */
821 int eq_esize;
822 int eq_ecount;
823 int cq_esize;
824 int cq_ecount;
825 int wq_esize;
826 int wq_ecount;
827 int mq_esize;
828 int mq_ecount;
829 int rq_esize;
830 int rq_ecount;
831#define LPFC_SP_EQ_MAX_INTR_SEC 10000
832#define LPFC_FP_EQ_MAX_INTR_SEC 10000
833
834 uint32_t intr_enable;
835 struct lpfc_bmbx bmbx;
836 struct lpfc_max_cfg_param max_cfg_param;
6d368e53
JS		 837 uint16_t extents_in_use; /* must allocate resource extents. */
838 uint16_t rpi_hdrs_in_use; /* must post rpi hdrs if set. */
da0436e9
JS		 839 uint16_t next_xri; /* last_xri - max_cfg_param.xri_base = used */
840 uint16_t next_rpi;
5e5b511d
JS		 841 uint16_t io_xri_max;
842 uint16_t io_xri_cnt;
843 uint16_t io_xri_start;
895427bd 844 uint16_t els_xri_cnt;
f358dd0c 845 uint16_t nvmet_xri_cnt;
a8cf5dfe
JS		 846 uint16_t nvmet_io_wait_cnt;
847 uint16_t nvmet_io_wait_total;
6a828b0f
JS		 848 uint16_t cq_max;
849 struct lpfc_queue **cq_lookup;
895427bd 850 struct list_head lpfc_els_sgl_list;
da0436e9 851 struct list_head lpfc_abts_els_sgl_list;
c00f62e6
JS		 852 spinlock_t abts_io_buf_list_lock; /* list of aborted SCSI IOs */
853 struct list_head lpfc_abts_io_buf_list;
f358dd0c 854 struct list_head lpfc_nvmet_sgl_list;
5e5b511d 855 spinlock_t abts_nvmet_buf_list_lock; /* list of aborted NVMET IOs */
86c67379 856 struct list_head lpfc_abts_nvmet_ctx_list;
79d8c4ce
JS		 857 spinlock_t t_active_list_lock; /* list of active NVMET IOs */
858 struct list_head t_active_ctx_list;
a8cf5dfe 859 struct list_head lpfc_nvmet_io_wait_list;
66d7ce93 860 struct lpfc_nvmet_ctx_info *nvmet_ctx_info;
da0436e9
JS		 861 struct lpfc_sglq **lpfc_sglq_active_list;
862 struct list_head lpfc_rpi_hdr_list;
863 unsigned long *rpi_bmask;
6d368e53 864 uint16_t *rpi_ids;
da0436e9 865 uint16_t rpi_count;
6d368e53
JS		 866 struct list_head lpfc_rpi_blk_list;
867 unsigned long *xri_bmask;
868 uint16_t *xri_ids;
6d368e53
JS		 869 struct list_head lpfc_xri_blk_list;
870 unsigned long *vfi_bmask;
871 uint16_t *vfi_ids;
872 uint16_t vfi_count;
873 struct list_head lpfc_vfi_blk_list;
da0436e9 874 struct lpfc_sli4_flags sli4_flags;
45ed1190 875 struct list_head sp_queue_event;
da0436e9
JS		 876 struct list_head sp_cqe_event_pool;
877 struct list_head sp_asynce_work_queue;
878 struct list_head sp_fcp_xri_aborted_work_queue;
879 struct list_head sp_els_xri_aborted_work_queue;
880 struct list_head sp_unsol_work_queue;
881 struct lpfc_sli4_link link_state;
cd1c8301
JS		 882 struct lpfc_sli4_lnk_info lnk_info;
883 uint32_t pport_name_sta;
884#define LPFC_SLI4_PPNAME_NON 0
885#define LPFC_SLI4_PPNAME_GET 1
912e3acd 886 struct lpfc_iov iov;
895427bd 887 spinlock_t sgl_list_lock; /* list of aborted els IOs */
a8cf5dfe 888 spinlock_t nvmet_io_wait_lock; /* IOs waiting for ctx resources */
8b017a30 889 uint32_t physical_port;
7bb03bbf
JS		 890
891 /* CPU to vector mapping information */
892 struct lpfc_vector_map_info *cpu_map;
222e9239 893 uint16_t num_possible_cpu;
7bb03bbf 894 uint16_t num_present_cpu;
76fd07a6 895 uint16_t curr_disp_cpu;
32517fc0 896 struct lpfc_eq_intr_info __percpu *eq_info;
1dc5ec24
JS		 897 uint32_t conf_trunk;
898#define lpfc_conf_trunk_port0_WORD conf_trunk
899#define lpfc_conf_trunk_port0_SHIFT 0
900#define lpfc_conf_trunk_port0_MASK 0x1
901#define lpfc_conf_trunk_port1_WORD conf_trunk
902#define lpfc_conf_trunk_port1_SHIFT 1
903#define lpfc_conf_trunk_port1_MASK 0x1
904#define lpfc_conf_trunk_port2_WORD conf_trunk
905#define lpfc_conf_trunk_port2_SHIFT 2
906#define lpfc_conf_trunk_port2_MASK 0x1
907#define lpfc_conf_trunk_port3_WORD conf_trunk
908#define lpfc_conf_trunk_port3_SHIFT 3
909#define lpfc_conf_trunk_port3_MASK 0x1
9a66d990
JS		 910#define lpfc_conf_trunk_port0_nd_WORD conf_trunk
911#define lpfc_conf_trunk_port0_nd_SHIFT 4
912#define lpfc_conf_trunk_port0_nd_MASK 0x1
913#define lpfc_conf_trunk_port1_nd_WORD conf_trunk
914#define lpfc_conf_trunk_port1_nd_SHIFT 5
915#define lpfc_conf_trunk_port1_nd_MASK 0x1
916#define lpfc_conf_trunk_port2_nd_WORD conf_trunk
917#define lpfc_conf_trunk_port2_nd_SHIFT 6
918#define lpfc_conf_trunk_port2_nd_MASK 0x1
919#define lpfc_conf_trunk_port3_nd_WORD conf_trunk
920#define lpfc_conf_trunk_port3_nd_SHIFT 7
921#define lpfc_conf_trunk_port3_nd_MASK 0x1
da0436e9
JS		 922};
923
924enum lpfc_sge_type {
925 GEN_BUFF_TYPE,
895427bd 926 SCSI_BUFF_TYPE,
f358dd0c 927 NVMET_BUFF_TYPE
da0436e9
JS		 928};
929
0f65ff68
JS		 930enum lpfc_sgl_state {
931 SGL_FREED,
932 SGL_ALLOCATED,
933 SGL_XRI_ABORTED
934};
935
da0436e9
JS		 936struct lpfc_sglq {
937 /* lpfc_sglqs are used in double linked lists */
938 struct list_head list;
939 struct list_head clist;
940 enum lpfc_sge_type buff_type; /* is this a scsi sgl */
0f65ff68 941 enum lpfc_sgl_state state;
19ca7609 942 struct lpfc_nodelist *ndlp; /* ndlp associated with IO */
da0436e9 943 uint16_t iotag; /* pre-assigned IO tag */
6d368e53 944 uint16_t sli4_lxritag; /* logical pre-assigned xri. */
da0436e9
JS		 945 uint16_t sli4_xritag; /* pre-assigned XRI, (OXID) tag. */
946 struct sli4_sge *sgl; /* pre-assigned SGL */
947 void *virt; /* virtual address. */
948 dma_addr_t phys; /* physical address */
949};
950
951struct lpfc_rpi_hdr {
952 struct list_head list;
953 uint32_t len;
954 struct lpfc_dmabuf *dmabuf;
955 uint32_t page_count;
956 uint32_t start_rpi;
845d9e8d 957 uint16_t next_rpi;
da0436e9
JS		 958};
959
6d368e53
JS		 960struct lpfc_rsrc_blks {
961 struct list_head list;
962 uint16_t rsrc_start;
963 uint16_t rsrc_size;
964 uint16_t rsrc_used;
965};
966
86478875
JS		 967struct lpfc_rdp_context {
968 struct lpfc_nodelist *ndlp;
969 uint16_t ox_id;
970 uint16_t rx_id;
971 READ_LNK_VAR link_stat;
972 uint8_t page_a0[DMP_SFF_PAGE_A0_SIZE];
973 uint8_t page_a2[DMP_SFF_PAGE_A2_SIZE];
974 void (*cmpl)(struct lpfc_hba *, struct lpfc_rdp_context*, int);
975};
976
8b017a30
JS		 977struct lpfc_lcb_context {
978 uint8_t sub_command;
979 uint8_t type;
66e9e6bf 980 uint8_t capability;
8b017a30 981 uint8_t frequency;
66e9e6bf 982 uint16_t duration;
8b017a30
JS		 983 uint16_t ox_id;
984 uint16_t rx_id;
985 struct lpfc_nodelist *ndlp;
986};
987
988
da0436e9
JS		 989/*
990 * SLI4 specific function prototypes
991 */
992int lpfc_pci_function_reset(struct lpfc_hba *);
73d91e50 993int lpfc_sli4_pdev_status_reg_wait(struct lpfc_hba *);
da0436e9 994int lpfc_sli4_hba_setup(struct lpfc_hba *);
da0436e9
JS		 995int lpfc_sli4_config(struct lpfc_hba *, struct lpfcMboxq *, uint8_t,
996 uint8_t, uint32_t, bool);
997void lpfc_sli4_mbox_cmd_free(struct lpfc_hba *, struct lpfcMboxq *);
998void lpfc_sli4_mbx_sge_set(struct lpfcMboxq *, uint32_t, dma_addr_t, uint32_t);
999void lpfc_sli4_mbx_sge_get(struct lpfcMboxq *, uint32_t,
1000 struct lpfc_mbx_sge *);
0c9ab6f5
JS		 1001int lpfc_sli4_mbx_read_fcf_rec(struct lpfc_hba *, struct lpfcMboxq *,
1002 uint16_t);
da0436e9
JS		 1003
1004void lpfc_sli4_hba_reset(struct lpfc_hba *);
c1a21ebc
JS		 1005struct lpfc_queue *lpfc_sli4_queue_alloc(struct lpfc_hba *phba,
1006 uint32_t page_size,
1007 uint32_t entry_size,
1008 uint32_t entry_count, int cpu);
da0436e9 1009void lpfc_sli4_queue_free(struct lpfc_queue *);
a2fc4aef 1010int lpfc_eq_create(struct lpfc_hba *, struct lpfc_queue *, uint32_t);
cb733e35
JS		 1011void lpfc_modify_hba_eq_delay(struct lpfc_hba *phba, uint32_t startq,
1012 uint32_t numq, uint32_t usdelay);
a2fc4aef 1013int lpfc_cq_create(struct lpfc_hba *, struct lpfc_queue *,
da0436e9 1014 struct lpfc_queue *, uint32_t, uint32_t);
2d7dbc4c 1015int lpfc_cq_create_set(struct lpfc_hba *phba, struct lpfc_queue **cqp,
cdb42bec 1016 struct lpfc_sli4_hdw_queue *hdwq, uint32_t type,
2d7dbc4c 1017 uint32_t subtype);
b19a061a
JS		 1018int32_t lpfc_mq_create(struct lpfc_hba *, struct lpfc_queue *,
1019 struct lpfc_queue *, uint32_t);
a2fc4aef 1020int lpfc_wq_create(struct lpfc_hba *, struct lpfc_queue *,
da0436e9 1021 struct lpfc_queue *, uint32_t);
a2fc4aef 1022int lpfc_rq_create(struct lpfc_hba *, struct lpfc_queue *,
da0436e9 1023 struct lpfc_queue *, struct lpfc_queue *, uint32_t);
2d7dbc4c
JS		 1024int lpfc_mrq_create(struct lpfc_hba *phba, struct lpfc_queue **hrqp,
1025 struct lpfc_queue **drqp, struct lpfc_queue **cqp,
1026 uint32_t subtype);
a2fc4aef
JS		 1027int lpfc_eq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1028int lpfc_cq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1029int lpfc_mq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1030int lpfc_wq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1031int lpfc_rq_destroy(struct lpfc_hba *, struct lpfc_queue *,
da0436e9
JS		 1032 struct lpfc_queue *);
1033int lpfc_sli4_queue_setup(struct lpfc_hba *);
1034void lpfc_sli4_queue_unset(struct lpfc_hba *);
1035int lpfc_sli4_post_sgl(struct lpfc_hba *, dma_addr_t, dma_addr_t, uint16_t);
5e5b511d 1036int lpfc_repost_io_sgl_list(struct lpfc_hba *phba);
da0436e9 1037uint16_t lpfc_sli4_next_xritag(struct lpfc_hba *);
f7bc6434 1038void lpfc_sli4_free_xri(struct lpfc_hba *, int);
da0436e9 1039int lpfc_sli4_post_async_mbox(struct lpfc_hba *);
da0436e9
JS		 1040struct lpfc_cq_event *__lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
1041struct lpfc_cq_event *lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
1042void __lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
1043void lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
1044int lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *);
1045int lpfc_sli4_post_rpi_hdr(struct lpfc_hba *, struct lpfc_rpi_hdr *);
1046int lpfc_sli4_post_all_rpi_hdrs(struct lpfc_hba *);
1047struct lpfc_rpi_hdr *lpfc_sli4_create_rpi_hdr(struct lpfc_hba *);
1048void lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *);
1049int lpfc_sli4_alloc_rpi(struct lpfc_hba *);
1050void lpfc_sli4_free_rpi(struct lpfc_hba *, int);
1051void lpfc_sli4_remove_rpis(struct lpfc_hba *);
1052void lpfc_sli4_async_event_proc(struct lpfc_hba *);
ecfd03c6 1053void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *);
6b5151fd
JS		 1054int lpfc_sli4_resume_rpi(struct lpfc_nodelist *,
1055 void (*)(struct lpfc_hba *, LPFC_MBOXQ_t *), void *);
da0436e9
JS		 1056void lpfc_sli4_fcp_xri_abort_event_proc(struct lpfc_hba *);
1057void lpfc_sli4_els_xri_abort_event_proc(struct lpfc_hba *);
318083ad 1058void lpfc_sli4_nvme_xri_aborted(struct lpfc_hba *phba,
c00f62e6
JS		 1059 struct sli4_wcqe_xri_aborted *axri,
1060 struct lpfc_io_buf *lpfc_ncmd);
1061void lpfc_sli4_io_xri_aborted(struct lpfc_hba *phba,
1062 struct sli4_wcqe_xri_aborted *axri, int idx);
318083ad
JS		 1063void lpfc_sli4_nvmet_xri_aborted(struct lpfc_hba *phba,
1064 struct sli4_wcqe_xri_aborted *axri);
da0436e9
JS		 1065void lpfc_sli4_els_xri_aborted(struct lpfc_hba *,
1066 struct sli4_wcqe_xri_aborted *);
1151e3ec
JS		 1067void lpfc_sli4_vport_delete_els_xri_aborted(struct lpfc_vport *);
1068void lpfc_sli4_vport_delete_fcp_xri_aborted(struct lpfc_vport *);
da0436e9
JS		 1069int lpfc_sli4_brdreset(struct lpfc_hba *);
1070int lpfc_sli4_add_fcf_record(struct lpfc_hba *, struct fcf_record *);
1071void lpfc_sli_remove_dflt_fcf(struct lpfc_hba *);
1072int lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *);
895427bd 1073int lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba);
76a95d75 1074int lpfc_sli4_init_vpi(struct lpfc_vport *);
92f3b327 1075void lpfc_sli4_eq_clr_intr(struct lpfc_queue *);
32517fc0
JS		 1076void lpfc_sli4_write_cq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1077 uint32_t count, bool arm);
1078void lpfc_sli4_write_eq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1079 uint32_t count, bool arm);
92f3b327 1080void lpfc_sli4_if6_eq_clr_intr(struct lpfc_queue *q);
32517fc0
JS		 1081void lpfc_sli4_if6_write_cq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1082 uint32_t count, bool arm);
1083void lpfc_sli4_if6_write_eq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1084 uint32_t count, bool arm);
da0436e9 1085void lpfc_sli4_fcfi_unreg(struct lpfc_hba *, uint16_t);
0c9ab6f5
JS		 1086int lpfc_sli4_fcf_scan_read_fcf_rec(struct lpfc_hba *, uint16_t);
1087int lpfc_sli4_fcf_rr_read_fcf_rec(struct lpfc_hba *, uint16_t);
1088int lpfc_sli4_read_fcf_rec(struct lpfc_hba *, uint16_t);
1089void lpfc_mbx_cmpl_fcf_scan_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
1090void lpfc_mbx_cmpl_fcf_rr_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
1091void lpfc_mbx_cmpl_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
1092int lpfc_sli4_unregister_fcf(struct lpfc_hba *);
da0436e9 1093int lpfc_sli4_post_status_check(struct lpfc_hba *);
a183a15f
JS		 1094uint8_t lpfc_sli_config_mbox_subsys_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
1095uint8_t lpfc_sli_config_mbox_opcode_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
d2cc9bcd 1096void lpfc_sli4_ras_dma_free(struct lpfc_hba *phba);
d79c9e9d
JS		 1097struct sli4_hybrid_sgl *lpfc_get_sgl_per_hdwq(struct lpfc_hba *phba,
1098 struct lpfc_io_buf *buf);
1099struct fcp_cmd_rsp_buf *lpfc_get_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba,
1100 struct lpfc_io_buf *buf);
1101int lpfc_put_sgl_per_hdwq(struct lpfc_hba *phba, struct lpfc_io_buf *buf);
1102int lpfc_put_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba,
1103 struct lpfc_io_buf *buf);
1104void lpfc_free_sgl_per_hdwq(struct lpfc_hba *phba,
1105 struct lpfc_sli4_hdw_queue *hdwq);
1106void lpfc_free_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba,
1107 struct lpfc_sli4_hdw_queue *hdwq);
c88725dd
JB		 1108static inline void *lpfc_sli4_qe(struct lpfc_queue *q, uint16_t idx)
1109{
1110 return q->q_pgs[idx / q->entry_cnt_per_pg] +
1111 (q->entry_size * (idx % q->entry_cnt_per_pg));
1112}
Linux 6.x block layer and io_uring tree(s)