projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
scsi: lpfc: Fix crash in target side cable pulls hitting WAIT_FOR_UNREG
[linux-2.6-block.git] / drivers / scsi / lpfc / lpfc_sli4.h
CommitLineData
da0436e9
JS		 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
0d041215 4 * Copyright (C) 2017-2019 Broadcom. All Rights Reserved. The term *
4ae2ebde 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
51f4ca3c 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. *
da0436e9 7 * EMULEX and SLI are trademarks of Emulex. *
d080abe0 8 * www.broadcom.com *
da0436e9
JS		 9 * *
10 * This program is free software; you can redistribute it and/or *
11 * modify it under the terms of version 2 of the GNU General *
12 * Public License as published by the Free Software Foundation. *
13 * This program is distributed in the hope that it will be useful. *
14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18 * TO BE LEGALLY INVALID. See the GNU General Public License for *
19 * more details, a copy of which can be found in the file COPYING *
20 * included with this package. *
21 *******************************************************************/
22
63df6d63
JS		 23#if defined(CONFIG_DEBUG_FS) && !defined(CONFIG_SCSI_LPFC_DEBUG_FS)
24#define CONFIG_SCSI_LPFC_DEBUG_FS
25#endif
26
da0436e9 27#define LPFC_ACTIVE_MBOX_WAIT_CNT 100
5af5eee7
JS		 28#define LPFC_XRI_EXCH_BUSY_WAIT_TMO 10000
29#define LPFC_XRI_EXCH_BUSY_WAIT_T1 10
30#define LPFC_XRI_EXCH_BUSY_WAIT_T2 30000
da0436e9 31#define LPFC_RPI_LOW_WATER_MARK 10
ecfd03c6 32
a93ff37a
JS		 33#define LPFC_UNREG_FCF 1
34#define LPFC_SKIP_UNREG_FCF 0
35
ecfd03c6
JS		 36/* Amount of time in seconds for waiting FCF rediscovery to complete */
37#define LPFC_FCF_REDISCOVER_WAIT_TMO 2000 /* msec */
38
da0436e9
JS		 39/* Number of SGL entries can be posted in a 4KB nonembedded mbox command */
40#define LPFC_NEMBED_MBOX_SGL_CNT 254
41
67d12733 42/* Multi-queue arrangement for FCP EQ/CQ/WQ tuples */
cdb42bec 43#define LPFC_HBA_HDWQ_MIN 0
dcaa2136
JS		 44#define LPFC_HBA_HDWQ_MAX 256
45#define LPFC_HBA_HDWQ_DEF LPFC_HBA_HDWQ_MIN
46
47/* irq_chann range, values */
48#define LPFC_IRQ_CHANN_MIN 0
49#define LPFC_IRQ_CHANN_MAX 256
50#define LPFC_IRQ_CHANN_DEF LPFC_IRQ_CHANN_MIN
da0436e9 51
77ffd346
JS		 52/* FCP MQ queue count limiting */
53#define LPFC_FCP_MQ_THRESHOLD_MIN 0
0622800d 54#define LPFC_FCP_MQ_THRESHOLD_MAX 256
77ffd346
JS		 55#define LPFC_FCP_MQ_THRESHOLD_DEF 8
56
da0436e9
JS		 57/*
58 * Provide the default FCF Record attributes used by the driver
59 * when nonFIP mode is configured and there is no other default
60 * FCF Record attributes.
61 */
62#define LPFC_FCOE_FCF_DEF_INDEX 0
63#define LPFC_FCOE_FCF_GET_FIRST 0xFFFF
64#define LPFC_FCOE_FCF_NEXT_NONE 0xFFFF
65
dbb6b3ab
JS		 66#define LPFC_FCOE_NULL_VID 0xFFF
67#define LPFC_FCOE_IGNORE_VID 0xFFFF
68
da0436e9
JS		 69/* First 3 bytes of default FCF MAC is specified by FC_MAP */
70#define LPFC_FCOE_FCF_MAC3 0xFF
71#define LPFC_FCOE_FCF_MAC4 0xFF
72#define LPFC_FCOE_FCF_MAC5 0xFE
73#define LPFC_FCOE_FCF_MAP0 0x0E
74#define LPFC_FCOE_FCF_MAP1 0xFC
75#define LPFC_FCOE_FCF_MAP2 0x00
98fc5dd9 76#define LPFC_FCOE_MAX_RCV_SIZE 0x800
da0436e9
JS		 77#define LPFC_FCOE_FKA_ADV_PER 0
78#define LPFC_FCOE_FIP_PRIORITY 0x80
79
6669f9bb
JS		 80#define sli4_sid_from_fc_hdr(fc_hdr) \
81 ((fc_hdr)->fh_s_id[0] << 16 | \
82 (fc_hdr)->fh_s_id[1] << 8 | \
83 (fc_hdr)->fh_s_id[2])
84
939723a4
JS		 85#define sli4_did_from_fc_hdr(fc_hdr) \
86 ((fc_hdr)->fh_d_id[0] << 16 | \
87 (fc_hdr)->fh_d_id[1] << 8 | \
88 (fc_hdr)->fh_d_id[2])
89
5ffc266e
JS		 90#define sli4_fctl_from_fc_hdr(fc_hdr) \
91 ((fc_hdr)->fh_f_ctl[0] << 16 | \
92 (fc_hdr)->fh_f_ctl[1] << 8 | \
93 (fc_hdr)->fh_f_ctl[2])
94
939723a4
JS		 95#define sli4_type_from_fc_hdr(fc_hdr) \
96 ((fc_hdr)->fh_type)
97
88a2cfbb
JS		 98#define LPFC_FW_RESET_MAXIMUM_WAIT_10MS_CNT 12000
99
c71ab861
JS		 100#define INT_FW_UPGRADE 0
101#define RUN_FW_UPGRADE 1
102
da0436e9
JS		 103enum lpfc_sli4_queue_type {
104 LPFC_EQ,
105 LPFC_GCQ,
106 LPFC_MCQ,
107 LPFC_WCQ,
108 LPFC_RCQ,
109 LPFC_MQ,
110 LPFC_WQ,
111 LPFC_HRQ,
112 LPFC_DRQ
113};
114
115/* The queue sub-type defines the functional purpose of the queue */
116enum lpfc_sli4_queue_subtype {
117 LPFC_NONE,
118 LPFC_MBOX,
c00f62e6 119 LPFC_IO,
da0436e9 120 LPFC_ELS,
f358dd0c 121 LPFC_NVMET,
895427bd 122 LPFC_NVME_LS,
da0436e9
JS		 123 LPFC_USOL
124};
125
895427bd
JS		 126/* RQ buffer list */
127struct lpfc_rqb {
128 uint16_t entry_count; /* Current number of RQ slots */
129 uint16_t buffer_count; /* Current number of buffers posted */
130 struct list_head rqb_buffer_list; /* buffers assigned to this HBQ */
131 /* Callback for HBQ buffer allocation */
132 struct rqb_dmabuf *(*rqb_alloc_buffer)(struct lpfc_hba *);
133 /* Callback for HBQ buffer free */
134 void (*rqb_free_buffer)(struct lpfc_hba *,
135 struct rqb_dmabuf *);
136};
137
da0436e9
JS		 138struct lpfc_queue {
139 struct list_head list;
895427bd 140 struct list_head wq_list;
93a4d6f4
JS		 141
142 /*
143 * If interrupts are in effect on _all_ the eq's the footprint
144 * of polling code is zero (except mode). This memory is chec-
145 * ked for every io to see if the io needs to be polled and
146 * while completion to check if the eq's needs to be rearmed.
147 * Keep in same cacheline as the queue ptr to avoid cpu fetch
148 * stalls. Using 1B memory will leave us with 7B hole. Fill
149 * it with other frequently used members.
150 */
151 uint16_t last_cpu; /* most recent cpu */
152 uint16_t hdwq;
153 uint8_t qe_valid;
154 uint8_t mode; /* interrupt or polling */
155#define LPFC_EQ_INTERRUPT 0
156#define LPFC_EQ_POLL 1
157
6e8e1c14 158 struct list_head wqfull_list;
da0436e9
JS		 159 enum lpfc_sli4_queue_type type;
160 enum lpfc_sli4_queue_subtype subtype;
161 struct lpfc_hba *phba;
162 struct list_head child_list;
895427bd
JS		 163 struct list_head page_list;
164 struct list_head sgl_list;
32517fc0 165 struct list_head cpu_list;
da0436e9
JS		 166 uint32_t entry_count; /* Number of entries to support on the queue */
167 uint32_t entry_size; /* Size of each queue entry. */
9afbee3d 168 uint32_t entry_cnt_per_pg;
32517fc0
JS		 169 uint32_t notify_interval; /* Queue Notification Interval
170 * For chip->host queues (EQ, CQ, RQ):
171 * specifies the interval (number of
172 * entries) where the doorbell is rung to
173 * notify the chip of entry consumption.
174 * For host->chip queues (WQ):
175 * specifies the interval (number of
176 * entries) where consumption CQE is
177 * requested to indicate WQ entries
178 * consumed by the chip.
179 * Not used on an MQ.
180 */
181#define LPFC_EQ_NOTIFY_INTRVL 16
182#define LPFC_CQ_NOTIFY_INTRVL 16
183#define LPFC_WQ_NOTIFY_INTRVL 16
184#define LPFC_RQ_NOTIFY_INTRVL 16
185 uint32_t max_proc_limit; /* Queue Processing Limit
186 * For chip->host queues (EQ, CQ):
187 * specifies the maximum number of
188 * entries to be consumed in one
189 * processing iteration sequence. Queue
190 * will be rearmed after each iteration.
191 * Not used on an MQ, RQ or WQ.
192 */
193#define LPFC_EQ_MAX_PROC_LIMIT 256
194#define LPFC_CQ_MIN_PROC_LIMIT 64
195#define LPFC_CQ_MAX_PROC_LIMIT LPFC_CQE_EXP_COUNT // 4096
196#define LPFC_CQ_DEF_MAX_PROC_LIMIT LPFC_CQE_DEF_COUNT // 1024
197#define LPFC_CQ_MIN_THRESHOLD_TO_POLL 64
198#define LPFC_CQ_MAX_THRESHOLD_TO_POLL LPFC_CQ_DEF_MAX_PROC_LIMIT
199#define LPFC_CQ_DEF_THRESHOLD_TO_POLL LPFC_CQ_DEF_MAX_PROC_LIMIT
200 uint32_t queue_claimed; /* indicates queue is being processed */
da0436e9 201 uint32_t queue_id; /* Queue ID assigned by the hardware */
2a622bfb 202 uint32_t assoc_qid; /* Queue ID associated with, for CQ/WQ/MQ */
da0436e9
JS		 203 uint32_t host_index; /* The host's index for putting or getting */
204 uint32_t hba_index; /* The last known hba index for get or put */
6a828b0f 205 uint32_t q_mode;
b84daac9 206
2a76a283 207 struct lpfc_sli_ring *pring; /* ptr to io ring associated with q */
895427bd 208 struct lpfc_rqb *rqbp; /* ptr to RQ buffers */
2a76a283 209
81b96eda
JS		 210 uint16_t page_count; /* Number of pages allocated for this queue */
211 uint16_t page_size; /* size of page allocated for this queue */
a51e41b6 212#define LPFC_EXPANDED_PAGE_SIZE 16384
81b96eda 213#define LPFC_DEFAULT_PAGE_SIZE 4096
6a828b0f
JS		 214 uint16_t chann; /* Hardware Queue association WQ/CQ */
215 /* CPU affinity for EQ */
216#define LPFC_FIND_BY_EQ 0
217#define LPFC_FIND_BY_HDWQ 1
6e8e1c14 218 uint8_t db_format;
962bc51b
JS		 219#define LPFC_DB_RING_FORMAT 0x01
220#define LPFC_DB_LIST_FORMAT 0x02
6e8e1c14
JS		 221 uint8_t q_flag;
222#define HBA_NVMET_WQFULL 0x1 /* We hit WQ Full condition for NVMET */
d74a89aa 223#define HBA_NVMET_CQ_NOTIFY 0x1 /* LPFC_NVMET_CQ_NOTIFY CQEs this EQE */
8156d378 224#define HBA_EQ_DELAY_CHK 0x2 /* EQ is a candidate for coalescing */
d74a89aa 225#define LPFC_NVMET_CQ_NOTIFY 4
962bc51b 226 void __iomem *db_regaddr;
1351e69f
JS		 227 uint16_t dpp_enable;
228 uint16_t dpp_id;
229 void __iomem *dpp_regaddr;
230
b84daac9
JS		 231 /* For q stats */
232 uint32_t q_cnt_1;
233 uint32_t q_cnt_2;
234 uint32_t q_cnt_3;
235 uint64_t q_cnt_4;
236/* defines for EQ stats */
237#define EQ_max_eqe q_cnt_1
238#define EQ_no_entry q_cnt_2
0cf07f84 239#define EQ_cqe_cnt q_cnt_3
b84daac9
JS		 240#define EQ_processed q_cnt_4
241
242/* defines for CQ stats */
243#define CQ_mbox q_cnt_1
244#define CQ_max_cqe q_cnt_1
245#define CQ_release_wqe q_cnt_2
246#define CQ_xri_aborted q_cnt_3
247#define CQ_wq q_cnt_4
248
249/* defines for WQ stats */
250#define WQ_overflow q_cnt_1
251#define WQ_posted q_cnt_4
252
253/* defines for RQ stats */
254#define RQ_no_posted_buf q_cnt_1
255#define RQ_no_buf_found q_cnt_2
547077a4 256#define RQ_buf_posted q_cnt_3
b84daac9
JS		 257#define RQ_rcv_buf q_cnt_4
258
32517fc0
JS		 259 struct work_struct irqwork;
260 struct work_struct spwork;
261 struct delayed_work sched_irqwork;
262 struct delayed_work sched_spwork;
f485c18d 263
895427bd
JS		 264 uint64_t isr_timestamp;
265 struct lpfc_queue *assoc_qp;
93a4d6f4 266 struct list_head _poll_list;
9afbee3d 267 void **q_pgs; /* array to index entries per page */
da0436e9
JS		 268};
269
da0436e9 270struct lpfc_sli4_link {
f3339800 271 uint32_t speed;
da0436e9
JS		 272 uint8_t duplex;
273 uint8_t status;
70f3c073
JS		 274 uint8_t type;
275 uint8_t number;
da0436e9 276 uint8_t fault;
f3339800 277 uint32_t logical_speed;
70f3c073 278 uint16_t topology;
da0436e9
JS		 279};
280
ecfd03c6
JS		 281struct lpfc_fcf_rec {
282 uint8_t fabric_name[8];
283 uint8_t switch_name[8];
da0436e9
JS		 284 uint8_t mac_addr[6];
285 uint16_t fcf_indx;
ecfd03c6
JS		 286 uint32_t priority;
287 uint16_t vlan_id;
288 uint32_t addr_mode;
289 uint32_t flag;
290#define BOOT_ENABLE 0x01
291#define RECORD_VALID 0x02
292};
293
7d791df7
JS		 294struct lpfc_fcf_pri_rec {
295 uint16_t fcf_index;
296#define LPFC_FCF_ON_PRI_LIST 0x0001
297#define LPFC_FCF_FLOGI_FAILED 0x0002
298 uint16_t flag;
299 uint32_t priority;
300};
301
302struct lpfc_fcf_pri {
303 struct list_head list;
304 struct lpfc_fcf_pri_rec fcf_rec;
305};
306
307/*
308 * Maximum FCF table index, it is for driver internal book keeping, it
309 * just needs to be no less than the supported HBA's FCF table size.
310 */
311#define LPFC_SLI4_FCF_TBL_INDX_MAX 32
312
ecfd03c6 313struct lpfc_fcf {
da0436e9
JS		 314 uint16_t fcfi;
315 uint32_t fcf_flag;
316#define FCF_AVAILABLE 0x01 /* FCF available for discovery */
317#define FCF_REGISTERED 0x02 /* FCF registered with FW */
ecfd03c6
JS		 318#define FCF_SCAN_DONE 0x04 /* FCF table scan done */
319#define FCF_IN_USE 0x08 /* Atleast one discovery completed */
0c9ab6f5
JS		 320#define FCF_INIT_DISC 0x10 /* Initial FCF discovery */
321#define FCF_DEAD_DISC 0x20 /* FCF DEAD fast FCF failover discovery */
322#define FCF_ACVL_DISC 0x40 /* All CVL fast FCF failover discovery */
323#define FCF_DISCOVERY (FCF_INIT_DISC | FCF_DEAD_DISC | FCF_ACVL_DISC)
324#define FCF_REDISC_PEND 0x80 /* FCF rediscovery pending */
325#define FCF_REDISC_EVT 0x100 /* FCF rediscovery event to worker thread */
326#define FCF_REDISC_FOV 0x200 /* Post FCF rediscovery fast failover */
a93ff37a 327#define FCF_REDISC_PROG (FCF_REDISC_PEND | FCF_REDISC_EVT)
036cad1f 328 uint16_t fcf_redisc_attempted;
da0436e9 329 uint32_t addr_mode;
999d813f 330 uint32_t eligible_fcf_cnt;
ecfd03c6
JS		 331 struct lpfc_fcf_rec current_rec;
332 struct lpfc_fcf_rec failover_rec;
7d791df7
JS		 333 struct list_head fcf_pri_list;
334 struct lpfc_fcf_pri fcf_pri[LPFC_SLI4_FCF_TBL_INDX_MAX];
335 uint32_t current_fcf_scan_pri;
ecfd03c6 336 struct timer_list redisc_wait;
0c9ab6f5 337 unsigned long *fcf_rr_bmask; /* Eligible FCF indexes for RR failover */
da0436e9
JS		 338};
339
0c9ab6f5 340
da0436e9
JS		 341#define LPFC_REGION23_SIGNATURE "RG23"
342#define LPFC_REGION23_VERSION 1
343#define LPFC_REGION23_LAST_REC 0xff
a0c87cbd
JS		 344#define DRIVER_SPECIFIC_TYPE 0xA2
345#define LINUX_DRIVER_ID 0x20
346#define PORT_STE_TYPE 0x1
347
da0436e9
JS		 348struct lpfc_fip_param_hdr {
349 uint8_t type;
350#define FCOE_PARAM_TYPE 0xA0
351 uint8_t length;
352#define FCOE_PARAM_LENGTH 2
353 uint8_t parm_version;
354#define FIPP_VERSION 0x01
355 uint8_t parm_flags;
356#define lpfc_fip_param_hdr_fipp_mode_SHIFT 6
357#define lpfc_fip_param_hdr_fipp_mode_MASK 0x3
358#define lpfc_fip_param_hdr_fipp_mode_WORD parm_flags
6a9c52cf 359#define FIPP_MODE_ON 0x1
da0436e9
JS		 360#define FIPP_MODE_OFF 0x0
361#define FIPP_VLAN_VALID 0x1
362};
363
364struct lpfc_fcoe_params {
365 uint8_t fc_map[3];
366 uint8_t reserved1;
367 uint16_t vlan_tag;
368 uint8_t reserved[2];
369};
370
371struct lpfc_fcf_conn_hdr {
372 uint8_t type;
373#define FCOE_CONN_TBL_TYPE 0xA1
374 uint8_t length; /* words */
375 uint8_t reserved[2];
376};
377
378struct lpfc_fcf_conn_rec {
379 uint16_t flags;
380#define FCFCNCT_VALID 0x0001
381#define FCFCNCT_BOOT 0x0002
382#define FCFCNCT_PRIMARY 0x0004 /* if not set, Secondary */
383#define FCFCNCT_FBNM_VALID 0x0008
384#define FCFCNCT_SWNM_VALID 0x0010
385#define FCFCNCT_VLAN_VALID 0x0020
386#define FCFCNCT_AM_VALID 0x0040
387#define FCFCNCT_AM_PREFERRED 0x0080 /* if not set, AM Required */
388#define FCFCNCT_AM_SPMA 0x0100 /* if not set, FPMA */
389
390 uint16_t vlan_tag;
391 uint8_t fabric_name[8];
392 uint8_t switch_name[8];
393};
394
395struct lpfc_fcf_conn_entry {
396 struct list_head list;
397 struct lpfc_fcf_conn_rec conn_rec;
398};
399
400/*
401 * Define the host's bootstrap mailbox. This structure contains
402 * the member attributes needed to create, use, and destroy the
403 * bootstrap mailbox region.
404 *
405 * The macro definitions for the bmbx data structure are defined
406 * in lpfc_hw4.h with the register definition.
407 */
408struct lpfc_bmbx {
409 struct lpfc_dmabuf *dmabuf;
410 struct dma_address dma_address;
411 void *avirt;
412 dma_addr_t aphys;
413 uint32_t bmbx_size;
414};
415
416#define LPFC_EQE_SIZE LPFC_EQE_SIZE_4
417
418#define LPFC_EQE_SIZE_4B 4
419#define LPFC_EQE_SIZE_16B 16
420#define LPFC_CQE_SIZE 16
421#define LPFC_WQE_SIZE 64
0c651878 422#define LPFC_WQE128_SIZE 128
da0436e9
JS		 423#define LPFC_MQE_SIZE 256
424#define LPFC_RQE_SIZE 8
425
426#define LPFC_EQE_DEF_COUNT 1024
ff78d8f9 427#define LPFC_CQE_DEF_COUNT 1024
a51e41b6 428#define LPFC_CQE_EXP_COUNT 4096
f1126688 429#define LPFC_WQE_DEF_COUNT 256
a51e41b6 430#define LPFC_WQE_EXP_COUNT 1024
da0436e9
JS		 431#define LPFC_MQE_DEF_COUNT 16
432#define LPFC_RQE_DEF_COUNT 512
433
434#define LPFC_QUEUE_NOARM false
435#define LPFC_QUEUE_REARM true
436
437
438/*
439 * SLI4 CT field defines
440 */
441#define SLI4_CT_RPI 0
442#define SLI4_CT_VPI 1
443#define SLI4_CT_VFI 2
444#define SLI4_CT_FCFI 3
445
da0436e9
JS		 446/*
447 * SLI4 specific data structures
448 */
449struct lpfc_max_cfg_param {
450 uint16_t max_xri;
451 uint16_t xri_base;
452 uint16_t xri_used;
453 uint16_t max_rpi;
454 uint16_t rpi_base;
455 uint16_t rpi_used;
456 uint16_t max_vpi;
457 uint16_t vpi_base;
458 uint16_t vpi_used;
459 uint16_t max_vfi;
460 uint16_t vfi_base;
461 uint16_t vfi_used;
462 uint16_t max_fcfi;
da0436e9
JS		 463 uint16_t fcfi_used;
464 uint16_t max_eq;
465 uint16_t max_rq;
466 uint16_t max_cq;
467 uint16_t max_wq;
468};
469
470struct lpfc_hba;
471/* SLI4 HBA multi-fcp queue handler struct */
b83d005e 472#define LPFC_SLI4_HANDLER_NAME_SZ 16
895427bd 473struct lpfc_hba_eq_hdl {
da0436e9 474 uint32_t idx;
dcaa2136 475 uint16_t irq;
b83d005e 476 char handler_name[LPFC_SLI4_HANDLER_NAME_SZ];
da0436e9 477 struct lpfc_hba *phba;
657add4e 478 struct lpfc_queue *eq;
dcaa2136 479 struct cpumask aff_mask;
da0436e9
JS		 480};
481
dcaa2136
JS		 482#define lpfc_get_eq_hdl(eqidx) (&phba->sli4_hba.hba_eq_hdl[eqidx])
483#define lpfc_get_aff_mask(eqidx) (&phba->sli4_hba.hba_eq_hdl[eqidx].aff_mask)
484#define lpfc_get_irq(eqidx) (phba->sli4_hba.hba_eq_hdl[eqidx].irq)
485
44fd7fe3
JS		 486/*BB Credit recovery value*/
487struct lpfc_bbscn_params {
488 uint32_t word0;
489#define lpfc_bbscn_min_SHIFT 0
490#define lpfc_bbscn_min_MASK 0x0000000F
491#define lpfc_bbscn_min_WORD word0
492#define lpfc_bbscn_max_SHIFT 4
493#define lpfc_bbscn_max_MASK 0x0000000F
494#define lpfc_bbscn_max_WORD word0
495#define lpfc_bbscn_def_SHIFT 8
496#define lpfc_bbscn_def_MASK 0x0000000F
497#define lpfc_bbscn_def_WORD word0
498};
499
28baac74
JS		 500/* Port Capabilities for SLI4 Parameters */
501struct lpfc_pc_sli4_params {
502 uint32_t supported;
503 uint32_t if_type;
504 uint32_t sli_rev;
505 uint32_t sli_family;
506 uint32_t featurelevel_1;
507 uint32_t featurelevel_2;
508 uint32_t proto_types;
509#define LPFC_SLI4_PROTO_FCOE 0x0000001
510#define LPFC_SLI4_PROTO_FC 0x0000002
511#define LPFC_SLI4_PROTO_NIC 0x0000004
512#define LPFC_SLI4_PROTO_ISCSI 0x0000008
513#define LPFC_SLI4_PROTO_RDMA 0x0000010
514 uint32_t sge_supp_len;
515 uint32_t if_page_sz;
516 uint32_t rq_db_window;
517 uint32_t loopbk_scope;
1ba981fd 518 uint32_t oas_supported;
28baac74
JS		 519 uint32_t eq_pages_max;
520 uint32_t eqe_size;
521 uint32_t cq_pages_max;
522 uint32_t cqe_size;
523 uint32_t mq_pages_max;
524 uint32_t mqe_size;
525 uint32_t mq_elem_cnt;
526 uint32_t wq_pages_max;
527 uint32_t wqe_size;
528 uint32_t rq_pages_max;
529 uint32_t rqe_size;
530 uint32_t hdr_pages_max;
531 uint32_t hdr_size;
532 uint32_t hdr_pp_align;
533 uint32_t sgl_pages_max;
534 uint32_t sgl_pp_align;
fedd3b7b
JS		 535 uint8_t cqv;
536 uint8_t mqv;
537 uint8_t wqv;
538 uint8_t rqv;
7365f6fd
JS		 539 uint8_t eqav;
540 uint8_t cqav;
0c651878 541 uint8_t wqsize;
66e9e6bf 542 uint8_t bv1s;
83c6cb1a 543 uint8_t pls;
0c651878
JS		 544#define LPFC_WQ_SZ64_SUPPORT 1
545#define LPFC_WQ_SZ128_SUPPORT 2
895427bd 546 uint8_t wqpcnt;
c15e0704 547 uint8_t nvme;
28baac74
JS		 548};
549
c176ffa0
JS		 550#define LPFC_CQ_4K_PAGE_SZ 0x1
551#define LPFC_CQ_16K_PAGE_SZ 0x4
552#define LPFC_WQ_4K_PAGE_SZ 0x1
553#define LPFC_WQ_16K_PAGE_SZ 0x4
554
912e3acd
JS		 555struct lpfc_iov {
556 uint32_t pf_number;
557 uint32_t vf_number;
558};
559
cd1c8301
JS		 560struct lpfc_sli4_lnk_info {
561 uint8_t lnk_dv;
562#define LPFC_LNK_DAT_INVAL 0
563#define LPFC_LNK_DAT_VAL 1
564 uint8_t lnk_tp;
9a66d990
JS		 565#define LPFC_LNK_GE 0x0 /* FCoE */
566#define LPFC_LNK_FC 0x1 /* FC */
567#define LPFC_LNK_FC_TRUNKED 0x2 /* FC_Trunked */
cd1c8301 568 uint8_t lnk_no;
448193b5 569 uint8_t optic_state;
cd1c8301
JS		 570};
571
895427bd 572#define LPFC_SLI4_HANDLER_CNT (LPFC_HBA_IO_CHAN_MAX+ \
1ba981fd 573 LPFC_FOF_IO_CHAN_NUM)
4305f183 574
dcaa2136 575/* Used for tracking CPU mapping attributes */
7bb03bbf
JS		 576struct lpfc_vector_map_info {
577 uint16_t phys_id;
578 uint16_t core_id;
6a828b0f 579 uint16_t eq;
b3295c2a 580 uint16_t hdwq;
d9954a2d
JS		 581 uint16_t flag;
582#define LPFC_CPU_MAP_HYPER 0x1
583#define LPFC_CPU_MAP_UNASSIGN 0x2
657add4e 584#define LPFC_CPU_FIRST_IRQ 0x4
7bb03bbf
JS		 585};
586#define LPFC_VECTOR_MAP_EMPTY 0xffff
7bb03bbf 587
c490850a
JS		 588/* Multi-XRI pool */
589#define XRI_BATCH 8
590
591struct lpfc_pbl_pool {
592 struct list_head list;
593 u32 count;
594 spinlock_t lock; /* lock for pbl_pool*/
595};
596
597struct lpfc_pvt_pool {
598 u32 low_watermark;
599 u32 high_watermark;
600
601 struct list_head list;
602 u32 count;
603 spinlock_t lock; /* lock for pvt_pool */
604};
605
606struct lpfc_multixri_pool {
607 u32 xri_limit;
608
609 /* Starting point when searching a pbl_pool with round-robin method */
610 u32 rrb_next_hwqid;
611
612 /* Used by lpfc_adjust_pvt_pool_count.
613 * io_req_count is incremented by 1 during IO submission. The heartbeat
614 * handler uses these two variables to determine if pvt_pool is idle or
615 * busy.
616 */
617 u32 prev_io_req_count;
618 u32 io_req_count;
619
620 /* statistics */
621 u32 pbl_empty_count;
622#ifdef LPFC_MXP_STAT
623 u32 above_limit_count;
624 u32 below_limit_count;
625 u32 local_pbl_hit_count;
626 u32 other_pbl_hit_count;
627 u32 stat_max_hwm;
628
629#define LPFC_MXP_SNAPSHOT_TAKEN 3 /* snapshot is taken at 3rd heartbeats */
630 u32 stat_pbl_count;
631 u32 stat_pvt_count;
632 u32 stat_busy_count;
633 u32 stat_snapshot_taken;
634#endif
635
636 /* TODO: Separate pvt_pool into get and put list */
637 struct lpfc_pbl_pool pbl_pool; /* Public free XRI pool */
638 struct lpfc_pvt_pool pvt_pool; /* Private free XRI pool */
639};
640
4c47efc1
JS		 641struct lpfc_fc4_ctrl_stat {
642 u32 input_requests;
643 u32 output_requests;
644 u32 control_requests;
645 u32 io_cmpls;
646};
647
6a828b0f
JS		 648#ifdef LPFC_HDWQ_LOCK_STAT
649struct lpfc_lock_stat {
650 uint32_t alloc_xri_get;
651 uint32_t alloc_xri_put;
652 uint32_t free_xri;
653 uint32_t wq_access;
654 uint32_t alloc_pvt_pool;
655 uint32_t mv_from_pvt_pool;
656 uint32_t mv_to_pub_pool;
657 uint32_t mv_to_pvt_pool;
658 uint32_t free_pub_pool;
659 uint32_t free_pvt_pool;
660};
661#endif
662
32517fc0
JS		 663struct lpfc_eq_intr_info {
664 struct list_head list;
665 uint32_t icnt;
666};
667
da0436e9 668/* SLI4 HBA data structure entries */
cdb42bec
JS		 669struct lpfc_sli4_hdw_queue {
670 /* Pointers to the constructed SLI4 queues */
671 struct lpfc_queue *hba_eq; /* Event queues for HBA */
c00f62e6
JS		 672 struct lpfc_queue *io_cq; /* Fast-path FCP & NVME compl queue */
673 struct lpfc_queue *io_wq; /* Fast-path FCP & NVME work queue */
674 uint16_t io_cq_map;
5e5b511d
JS		 675
676 /* Keep track of IO buffers for this hardware queue */
677 spinlock_t io_buf_list_get_lock; /* Common buf alloc list lock */
678 struct list_head lpfc_io_buf_list_get;
679 spinlock_t io_buf_list_put_lock; /* Common buf free list lock */
680 struct list_head lpfc_io_buf_list_put;
c00f62e6
JS		 681 spinlock_t abts_io_buf_list_lock; /* list of aborted IOs */
682 struct list_head lpfc_abts_io_buf_list;
5e5b511d
JS		 683 uint32_t total_io_bufs;
684 uint32_t get_io_bufs;
685 uint32_t put_io_bufs;
686 uint32_t empty_io_bufs;
687 uint32_t abts_scsi_io_bufs;
688 uint32_t abts_nvme_io_bufs;
63df6d63 689
c490850a
JS		 690 /* Multi-XRI pool per HWQ */
691 struct lpfc_multixri_pool *p_multixri_pool;
692
4c47efc1
JS		 693 /* FC-4 Stats counters */
694 struct lpfc_fc4_ctrl_stat nvme_cstat;
695 struct lpfc_fc4_ctrl_stat scsi_cstat;
6a828b0f
JS		 696#ifdef LPFC_HDWQ_LOCK_STAT
697 struct lpfc_lock_stat lock_conflict;
698#endif
4c47efc1 699
63df6d63
JS		 700#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
701#define LPFC_CHECK_CPU_CNT 128
702 uint32_t cpucheck_rcv_io[LPFC_CHECK_CPU_CNT];
703 uint32_t cpucheck_xmt_io[LPFC_CHECK_CPU_CNT];
704 uint32_t cpucheck_cmpl_io[LPFC_CHECK_CPU_CNT];
705#endif
d79c9e9d
JS		 706
707 /* Per HDWQ pool resources */
708 struct list_head sgl_list;
709 struct list_head cmd_rsp_buf_list;
710
711 /* Lock for syncing Per HDWQ pool resources */
712 spinlock_t hdwq_lock;
cdb42bec
JS		 713};
714
6a828b0f
JS		 715#ifdef LPFC_HDWQ_LOCK_STAT
716/* compile time trylock stats */
717#define lpfc_qp_spin_lock_irqsave(lock, flag, qp, lstat) \
718 { \
719 int only_once = 1; \
720 while (spin_trylock_irqsave(lock, flag) == 0) { \
721 if (only_once) { \
722 only_once = 0; \
723 qp->lock_conflict.lstat++; \
724 } \
725 } \
726 }
727#define lpfc_qp_spin_lock(lock, qp, lstat) \
728 { \
729 int only_once = 1; \
730 while (spin_trylock(lock) == 0) { \
731 if (only_once) { \
732 only_once = 0; \
733 qp->lock_conflict.lstat++; \
734 } \
735 } \
736 }
737#else
738#define lpfc_qp_spin_lock_irqsave(lock, flag, qp, lstat) \
739 spin_lock_irqsave(lock, flag)
740#define lpfc_qp_spin_lock(lock, qp, lstat) spin_lock(lock)
741#endif
742
da0436e9
JS		 743struct lpfc_sli4_hba {
744 void __iomem *conf_regs_memmap_p; /* Kernel memory mapped address for
1351e69f
JS		 745 * config space registers
746 */
da0436e9 747 void __iomem *ctrl_regs_memmap_p; /* Kernel memory mapped address for
1351e69f
JS		 748 * control registers
749 */
da0436e9 750 void __iomem *drbl_regs_memmap_p; /* Kernel memory mapped address for
1351e69f
JS		 751 * doorbell registers
752 */
753 void __iomem *dpp_regs_memmap_p; /* Kernel memory mapped address for
754 * dpp registers
755 */
2fcee4bf
JS		 756 union {
757 struct {
758 /* IF Type 0, BAR 0 PCI cfg space reg mem map */
759 void __iomem *UERRLOregaddr;
760 void __iomem *UERRHIregaddr;
761 void __iomem *UEMASKLOregaddr;
762 void __iomem *UEMASKHIregaddr;
763 } if_type0;
764 struct {
765 /* IF Type 2, BAR 0 PCI cfg space reg mem map. */
766 void __iomem *STATUSregaddr;
767 void __iomem *CTRLregaddr;
768 void __iomem *ERR1regaddr;
2e90f4b5
JS		 769#define SLIPORT_ERR1_REG_ERR_CODE_1 0x1
770#define SLIPORT_ERR1_REG_ERR_CODE_2 0x2
2fcee4bf 771 void __iomem *ERR2regaddr;
2e90f4b5
JS		 772#define SLIPORT_ERR2_REG_FW_RESTART 0x0
773#define SLIPORT_ERR2_REG_FUNC_PROVISON 0x1
774#define SLIPORT_ERR2_REG_FORCED_DUMP 0x2
775#define SLIPORT_ERR2_REG_FAILURE_EQ 0x3
776#define SLIPORT_ERR2_REG_FAILURE_CQ 0x4
777#define SLIPORT_ERR2_REG_FAILURE_BUS 0x5
778#define SLIPORT_ERR2_REG_FAILURE_RQ 0x6
0cf07f84 779 void __iomem *EQDregaddr;
2fcee4bf
JS		 780 } if_type2;
781 } u;
782
783 /* IF type 0, BAR1 and if type 2, Bar 0 CSR register memory map */
784 void __iomem *PSMPHRregaddr;
785
786 /* Well-known SLI INTF register memory map. */
787 void __iomem *SLIINTFregaddr;
788
789 /* IF type 0, BAR 1 function CSR register memory map */
790 void __iomem *ISRregaddr; /* HST_ISR register */
791 void __iomem *IMRregaddr; /* HST_IMR register */
792 void __iomem *ISCRregaddr; /* HST_ISCR register */
793 /* IF type 0, BAR 0 and if type 2, BAR 0 doorbell register memory map */
794 void __iomem *RQDBregaddr; /* RQ_DOORBELL register */
795 void __iomem *WQDBregaddr; /* WQ_DOORBELL register */
9dd35425
JS		 796 void __iomem *CQDBregaddr; /* CQ_DOORBELL register */
797 void __iomem *EQDBregaddr; /* EQ_DOORBELL register */
2fcee4bf
JS		 798 void __iomem *MQDBregaddr; /* MQ_DOORBELL register */
799 void __iomem *BMBXregaddr; /* BootStrap MBX register */
da0436e9 800
a747c9ce
JS		 801 uint32_t ue_mask_lo;
802 uint32_t ue_mask_hi;
65791f1f
JS		 803 uint32_t ue_to_sr;
804 uint32_t ue_to_rp;
28baac74
JS		 805 struct lpfc_register sli_intf;
806 struct lpfc_pc_sli4_params pc_sli4_params;
44fd7fe3 807 struct lpfc_bbscn_params bbscn_params;
895427bd 808 struct lpfc_hba_eq_hdl *hba_eq_hdl; /* HBA per-WQ handle */
67d12733 809
b71413dd 810 void (*sli4_eq_clr_intr)(struct lpfc_queue *q);
32517fc0
JS		 811 void (*sli4_write_eq_db)(struct lpfc_hba *phba, struct lpfc_queue *eq,
812 uint32_t count, bool arm);
813 void (*sli4_write_cq_db)(struct lpfc_hba *phba, struct lpfc_queue *cq,
814 uint32_t count, bool arm);
b71413dd 815
da0436e9 816 /* Pointers to the constructed SLI4 queues */
cdb42bec
JS		 817 struct lpfc_sli4_hdw_queue *hdwq;
818 struct list_head lpfc_wq_list;
819
820 /* Pointers to the constructed SLI4 queues for NVMET */
2d7dbc4c
JS		 821 struct lpfc_queue **nvmet_cqset; /* Fast-path NVMET CQ Set queues */
822 struct lpfc_queue **nvmet_mrq_hdr; /* Fast-path NVMET hdr MRQs */
823 struct lpfc_queue **nvmet_mrq_data; /* Fast-path NVMET data MRQs */
67d12733
JS		 824
825 struct lpfc_queue *mbx_cq; /* Slow-path mailbox complete queue */
826 struct lpfc_queue *els_cq; /* Slow-path ELS response complete queue */
895427bd 827 struct lpfc_queue *nvmels_cq; /* NVME LS complete queue */
da0436e9
JS		 828 struct lpfc_queue *mbx_wq; /* Slow-path MBOX work queue */
829 struct lpfc_queue *els_wq; /* Slow-path ELS work queue */
895427bd 830 struct lpfc_queue *nvmels_wq; /* NVME LS work queue */
da0436e9
JS		 831 struct lpfc_queue *hdr_rq; /* Slow-path Header Receive queue */
832 struct lpfc_queue *dat_rq; /* Slow-path Data Receive queue */
da0436e9 833
895427bd
JS		 834 struct lpfc_name wwnn;
835 struct lpfc_name wwpn;
836
9a86ed48 837 uint32_t fw_func_mode; /* FW function protocol mode */
962bc51b
JS		 838 uint32_t ulp0_mode; /* ULP0 protocol mode */
839 uint32_t ulp1_mode; /* ULP1 protocol mode */
840
1ba981fd 841 /* Optimized Access Storage specific queues/structures */
1ba981fd
JS		 842 uint64_t oas_next_lun;
843 uint8_t oas_next_tgt_wwpn[8];
844 uint8_t oas_next_vpt_wwpn[8];
845
da0436e9
JS		 846 /* Setup information for various queue parameters */
847 int eq_esize;
848 int eq_ecount;
849 int cq_esize;
850 int cq_ecount;
851 int wq_esize;
852 int wq_ecount;
853 int mq_esize;
854 int mq_ecount;
855 int rq_esize;
856 int rq_ecount;
857#define LPFC_SP_EQ_MAX_INTR_SEC 10000
858#define LPFC_FP_EQ_MAX_INTR_SEC 10000
859
860 uint32_t intr_enable;
861 struct lpfc_bmbx bmbx;
862 struct lpfc_max_cfg_param max_cfg_param;
6d368e53
JS		 863 uint16_t extents_in_use; /* must allocate resource extents. */
864 uint16_t rpi_hdrs_in_use; /* must post rpi hdrs if set. */
da0436e9
JS		 865 uint16_t next_xri; /* last_xri - max_cfg_param.xri_base = used */
866 uint16_t next_rpi;
5e5b511d
JS		 867 uint16_t io_xri_max;
868 uint16_t io_xri_cnt;
869 uint16_t io_xri_start;
895427bd 870 uint16_t els_xri_cnt;
f358dd0c 871 uint16_t nvmet_xri_cnt;
a8cf5dfe
JS		 872 uint16_t nvmet_io_wait_cnt;
873 uint16_t nvmet_io_wait_total;
6a828b0f
JS		 874 uint16_t cq_max;
875 struct lpfc_queue **cq_lookup;
895427bd 876 struct list_head lpfc_els_sgl_list;
da0436e9 877 struct list_head lpfc_abts_els_sgl_list;
c00f62e6
JS		 878 spinlock_t abts_io_buf_list_lock; /* list of aborted SCSI IOs */
879 struct list_head lpfc_abts_io_buf_list;
f358dd0c 880 struct list_head lpfc_nvmet_sgl_list;
5e5b511d 881 spinlock_t abts_nvmet_buf_list_lock; /* list of aborted NVMET IOs */
86c67379 882 struct list_head lpfc_abts_nvmet_ctx_list;
79d8c4ce
JS		 883 spinlock_t t_active_list_lock; /* list of active NVMET IOs */
884 struct list_head t_active_ctx_list;
a8cf5dfe 885 struct list_head lpfc_nvmet_io_wait_list;
66d7ce93 886 struct lpfc_nvmet_ctx_info *nvmet_ctx_info;
da0436e9
JS		 887 struct lpfc_sglq **lpfc_sglq_active_list;
888 struct list_head lpfc_rpi_hdr_list;
889 unsigned long *rpi_bmask;
6d368e53 890 uint16_t *rpi_ids;
da0436e9 891 uint16_t rpi_count;
6d368e53
JS		 892 struct list_head lpfc_rpi_blk_list;
893 unsigned long *xri_bmask;
894 uint16_t *xri_ids;
6d368e53
JS		 895 struct list_head lpfc_xri_blk_list;
896 unsigned long *vfi_bmask;
897 uint16_t *vfi_ids;
898 uint16_t vfi_count;
899 struct list_head lpfc_vfi_blk_list;
da0436e9 900 struct lpfc_sli4_flags sli4_flags;
45ed1190 901 struct list_head sp_queue_event;
da0436e9
JS		 902 struct list_head sp_cqe_event_pool;
903 struct list_head sp_asynce_work_queue;
904 struct list_head sp_fcp_xri_aborted_work_queue;
905 struct list_head sp_els_xri_aborted_work_queue;
906 struct list_head sp_unsol_work_queue;
907 struct lpfc_sli4_link link_state;
cd1c8301
JS		 908 struct lpfc_sli4_lnk_info lnk_info;
909 uint32_t pport_name_sta;
910#define LPFC_SLI4_PPNAME_NON 0
911#define LPFC_SLI4_PPNAME_GET 1
912e3acd 912 struct lpfc_iov iov;
895427bd 913 spinlock_t sgl_list_lock; /* list of aborted els IOs */
a8cf5dfe 914 spinlock_t nvmet_io_wait_lock; /* IOs waiting for ctx resources */
8b017a30 915 uint32_t physical_port;
7bb03bbf
JS		 916
917 /* CPU to vector mapping information */
918 struct lpfc_vector_map_info *cpu_map;
222e9239 919 uint16_t num_possible_cpu;
7bb03bbf 920 uint16_t num_present_cpu;
dcaa2136 921 struct cpumask numa_mask;
76fd07a6 922 uint16_t curr_disp_cpu;
32517fc0 923 struct lpfc_eq_intr_info __percpu *eq_info;
1dc5ec24
JS		 924 uint32_t conf_trunk;
925#define lpfc_conf_trunk_port0_WORD conf_trunk
926#define lpfc_conf_trunk_port0_SHIFT 0
927#define lpfc_conf_trunk_port0_MASK 0x1
928#define lpfc_conf_trunk_port1_WORD conf_trunk
929#define lpfc_conf_trunk_port1_SHIFT 1
930#define lpfc_conf_trunk_port1_MASK 0x1
931#define lpfc_conf_trunk_port2_WORD conf_trunk
932#define lpfc_conf_trunk_port2_SHIFT 2
933#define lpfc_conf_trunk_port2_MASK 0x1
934#define lpfc_conf_trunk_port3_WORD conf_trunk
935#define lpfc_conf_trunk_port3_SHIFT 3
936#define lpfc_conf_trunk_port3_MASK 0x1
9a66d990
JS		 937#define lpfc_conf_trunk_port0_nd_WORD conf_trunk
938#define lpfc_conf_trunk_port0_nd_SHIFT 4
939#define lpfc_conf_trunk_port0_nd_MASK 0x1
940#define lpfc_conf_trunk_port1_nd_WORD conf_trunk
941#define lpfc_conf_trunk_port1_nd_SHIFT 5
942#define lpfc_conf_trunk_port1_nd_MASK 0x1
943#define lpfc_conf_trunk_port2_nd_WORD conf_trunk
944#define lpfc_conf_trunk_port2_nd_SHIFT 6
945#define lpfc_conf_trunk_port2_nd_MASK 0x1
946#define lpfc_conf_trunk_port3_nd_WORD conf_trunk
947#define lpfc_conf_trunk_port3_nd_SHIFT 7
948#define lpfc_conf_trunk_port3_nd_MASK 0x1
da0436e9
JS		 949};
950
951enum lpfc_sge_type {
952 GEN_BUFF_TYPE,
895427bd 953 SCSI_BUFF_TYPE,
f358dd0c 954 NVMET_BUFF_TYPE
da0436e9
JS		 955};
956
0f65ff68
JS		 957enum lpfc_sgl_state {
958 SGL_FREED,
959 SGL_ALLOCATED,
960 SGL_XRI_ABORTED
961};
962
da0436e9
JS		 963struct lpfc_sglq {
964 /* lpfc_sglqs are used in double linked lists */
965 struct list_head list;
966 struct list_head clist;
967 enum lpfc_sge_type buff_type; /* is this a scsi sgl */
0f65ff68 968 enum lpfc_sgl_state state;
19ca7609 969 struct lpfc_nodelist *ndlp; /* ndlp associated with IO */
da0436e9 970 uint16_t iotag; /* pre-assigned IO tag */
6d368e53 971 uint16_t sli4_lxritag; /* logical pre-assigned xri. */
da0436e9
JS		 972 uint16_t sli4_xritag; /* pre-assigned XRI, (OXID) tag. */
973 struct sli4_sge *sgl; /* pre-assigned SGL */
974 void *virt; /* virtual address. */
975 dma_addr_t phys; /* physical address */
976};
977
978struct lpfc_rpi_hdr {
979 struct list_head list;
980 uint32_t len;
981 struct lpfc_dmabuf *dmabuf;
982 uint32_t page_count;
983 uint32_t start_rpi;
845d9e8d 984 uint16_t next_rpi;
da0436e9
JS		 985};
986
6d368e53
JS		 987struct lpfc_rsrc_blks {
988 struct list_head list;
989 uint16_t rsrc_start;
990 uint16_t rsrc_size;
991 uint16_t rsrc_used;
992};
993
86478875
JS		 994struct lpfc_rdp_context {
995 struct lpfc_nodelist *ndlp;
996 uint16_t ox_id;
997 uint16_t rx_id;
998 READ_LNK_VAR link_stat;
999 uint8_t page_a0[DMP_SFF_PAGE_A0_SIZE];
1000 uint8_t page_a2[DMP_SFF_PAGE_A2_SIZE];
1001 void (*cmpl)(struct lpfc_hba *, struct lpfc_rdp_context*, int);
1002};
1003
8b017a30
JS		 1004struct lpfc_lcb_context {
1005 uint8_t sub_command;
1006 uint8_t type;
66e9e6bf 1007 uint8_t capability;
8b017a30 1008 uint8_t frequency;
66e9e6bf 1009 uint16_t duration;
8b017a30
JS		 1010 uint16_t ox_id;
1011 uint16_t rx_id;
1012 struct lpfc_nodelist *ndlp;
1013};
1014
1015
da0436e9
JS		 1016/*
1017 * SLI4 specific function prototypes
1018 */
1019int lpfc_pci_function_reset(struct lpfc_hba *);
73d91e50 1020int lpfc_sli4_pdev_status_reg_wait(struct lpfc_hba *);
da0436e9 1021int lpfc_sli4_hba_setup(struct lpfc_hba *);
da0436e9
JS		 1022int lpfc_sli4_config(struct lpfc_hba *, struct lpfcMboxq *, uint8_t,
1023 uint8_t, uint32_t, bool);
1024void lpfc_sli4_mbox_cmd_free(struct lpfc_hba *, struct lpfcMboxq *);
1025void lpfc_sli4_mbx_sge_set(struct lpfcMboxq *, uint32_t, dma_addr_t, uint32_t);
1026void lpfc_sli4_mbx_sge_get(struct lpfcMboxq *, uint32_t,
1027 struct lpfc_mbx_sge *);
0c9ab6f5
JS		 1028int lpfc_sli4_mbx_read_fcf_rec(struct lpfc_hba *, struct lpfcMboxq *,
1029 uint16_t);
da0436e9
JS		 1030
1031void lpfc_sli4_hba_reset(struct lpfc_hba *);
c1a21ebc
JS		 1032struct lpfc_queue *lpfc_sli4_queue_alloc(struct lpfc_hba *phba,
1033 uint32_t page_size,
1034 uint32_t entry_size,
1035 uint32_t entry_count, int cpu);
da0436e9 1036void lpfc_sli4_queue_free(struct lpfc_queue *);
a2fc4aef 1037int lpfc_eq_create(struct lpfc_hba *, struct lpfc_queue *, uint32_t);
cb733e35
JS		 1038void lpfc_modify_hba_eq_delay(struct lpfc_hba *phba, uint32_t startq,
1039 uint32_t numq, uint32_t usdelay);
a2fc4aef 1040int lpfc_cq_create(struct lpfc_hba *, struct lpfc_queue *,
da0436e9 1041 struct lpfc_queue *, uint32_t, uint32_t);
2d7dbc4c 1042int lpfc_cq_create_set(struct lpfc_hba *phba, struct lpfc_queue **cqp,
cdb42bec 1043 struct lpfc_sli4_hdw_queue *hdwq, uint32_t type,
2d7dbc4c 1044 uint32_t subtype);
b19a061a
JS		 1045int32_t lpfc_mq_create(struct lpfc_hba *, struct lpfc_queue *,
1046 struct lpfc_queue *, uint32_t);
a2fc4aef 1047int lpfc_wq_create(struct lpfc_hba *, struct lpfc_queue *,
da0436e9 1048 struct lpfc_queue *, uint32_t);
a2fc4aef 1049int lpfc_rq_create(struct lpfc_hba *, struct lpfc_queue *,
da0436e9 1050 struct lpfc_queue *, struct lpfc_queue *, uint32_t);
2d7dbc4c
JS		 1051int lpfc_mrq_create(struct lpfc_hba *phba, struct lpfc_queue **hrqp,
1052 struct lpfc_queue **drqp, struct lpfc_queue **cqp,
1053 uint32_t subtype);
a2fc4aef
JS		 1054int lpfc_eq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1055int lpfc_cq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1056int lpfc_mq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1057int lpfc_wq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1058int lpfc_rq_destroy(struct lpfc_hba *, struct lpfc_queue *,
da0436e9
JS		 1059 struct lpfc_queue *);
1060int lpfc_sli4_queue_setup(struct lpfc_hba *);
1061void lpfc_sli4_queue_unset(struct lpfc_hba *);
1062int lpfc_sli4_post_sgl(struct lpfc_hba *, dma_addr_t, dma_addr_t, uint16_t);
5e5b511d 1063int lpfc_repost_io_sgl_list(struct lpfc_hba *phba);
da0436e9 1064uint16_t lpfc_sli4_next_xritag(struct lpfc_hba *);
f7bc6434 1065void lpfc_sli4_free_xri(struct lpfc_hba *, int);
da0436e9 1066int lpfc_sli4_post_async_mbox(struct lpfc_hba *);
da0436e9
JS		 1067struct lpfc_cq_event *__lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
1068struct lpfc_cq_event *lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
1069void __lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
1070void lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
1071int lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *);
1072int lpfc_sli4_post_rpi_hdr(struct lpfc_hba *, struct lpfc_rpi_hdr *);
1073int lpfc_sli4_post_all_rpi_hdrs(struct lpfc_hba *);
1074struct lpfc_rpi_hdr *lpfc_sli4_create_rpi_hdr(struct lpfc_hba *);
1075void lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *);
1076int lpfc_sli4_alloc_rpi(struct lpfc_hba *);
1077void lpfc_sli4_free_rpi(struct lpfc_hba *, int);
1078void lpfc_sli4_remove_rpis(struct lpfc_hba *);
1079void lpfc_sli4_async_event_proc(struct lpfc_hba *);
ecfd03c6 1080void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *);
6b5151fd
JS		 1081int lpfc_sli4_resume_rpi(struct lpfc_nodelist *,
1082 void (*)(struct lpfc_hba *, LPFC_MBOXQ_t *), void *);
da0436e9
JS		 1083void lpfc_sli4_fcp_xri_abort_event_proc(struct lpfc_hba *);
1084void lpfc_sli4_els_xri_abort_event_proc(struct lpfc_hba *);
318083ad 1085void lpfc_sli4_nvme_xri_aborted(struct lpfc_hba *phba,
c00f62e6
JS		 1086 struct sli4_wcqe_xri_aborted *axri,
1087 struct lpfc_io_buf *lpfc_ncmd);
1088void lpfc_sli4_io_xri_aborted(struct lpfc_hba *phba,
1089 struct sli4_wcqe_xri_aborted *axri, int idx);
318083ad
JS		 1090void lpfc_sli4_nvmet_xri_aborted(struct lpfc_hba *phba,
1091 struct sli4_wcqe_xri_aborted *axri);
da0436e9
JS		 1092void lpfc_sli4_els_xri_aborted(struct lpfc_hba *,
1093 struct sli4_wcqe_xri_aborted *);
1151e3ec
JS		 1094void lpfc_sli4_vport_delete_els_xri_aborted(struct lpfc_vport *);
1095void lpfc_sli4_vport_delete_fcp_xri_aborted(struct lpfc_vport *);
da0436e9
JS		 1096int lpfc_sli4_brdreset(struct lpfc_hba *);
1097int lpfc_sli4_add_fcf_record(struct lpfc_hba *, struct fcf_record *);
1098void lpfc_sli_remove_dflt_fcf(struct lpfc_hba *);
1099int lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *);
895427bd 1100int lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba);
76a95d75 1101int lpfc_sli4_init_vpi(struct lpfc_vport *);
92f3b327 1102void lpfc_sli4_eq_clr_intr(struct lpfc_queue *);
32517fc0
JS		 1103void lpfc_sli4_write_cq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1104 uint32_t count, bool arm);
1105void lpfc_sli4_write_eq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1106 uint32_t count, bool arm);
92f3b327 1107void lpfc_sli4_if6_eq_clr_intr(struct lpfc_queue *q);
32517fc0
JS		 1108void lpfc_sli4_if6_write_cq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1109 uint32_t count, bool arm);
1110void lpfc_sli4_if6_write_eq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1111 uint32_t count, bool arm);
da0436e9 1112void lpfc_sli4_fcfi_unreg(struct lpfc_hba *, uint16_t);
0c9ab6f5
JS		 1113int lpfc_sli4_fcf_scan_read_fcf_rec(struct lpfc_hba *, uint16_t);
1114int lpfc_sli4_fcf_rr_read_fcf_rec(struct lpfc_hba *, uint16_t);
1115int lpfc_sli4_read_fcf_rec(struct lpfc_hba *, uint16_t);
1116void lpfc_mbx_cmpl_fcf_scan_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
1117void lpfc_mbx_cmpl_fcf_rr_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
1118void lpfc_mbx_cmpl_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
1119int lpfc_sli4_unregister_fcf(struct lpfc_hba *);
da0436e9 1120int lpfc_sli4_post_status_check(struct lpfc_hba *);
a183a15f
JS		 1121uint8_t lpfc_sli_config_mbox_subsys_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
1122uint8_t lpfc_sli_config_mbox_opcode_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
d2cc9bcd 1123void lpfc_sli4_ras_dma_free(struct lpfc_hba *phba);
d79c9e9d
JS		 1124struct sli4_hybrid_sgl *lpfc_get_sgl_per_hdwq(struct lpfc_hba *phba,
1125 struct lpfc_io_buf *buf);
1126struct fcp_cmd_rsp_buf *lpfc_get_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba,
1127 struct lpfc_io_buf *buf);
1128int lpfc_put_sgl_per_hdwq(struct lpfc_hba *phba, struct lpfc_io_buf *buf);
1129int lpfc_put_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba,
1130 struct lpfc_io_buf *buf);
1131void lpfc_free_sgl_per_hdwq(struct lpfc_hba *phba,
1132 struct lpfc_sli4_hdw_queue *hdwq);
1133void lpfc_free_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba,
1134 struct lpfc_sli4_hdw_queue *hdwq);
c88725dd
JB		 1135static inline void *lpfc_sli4_qe(struct lpfc_queue *q, uint16_t idx)
1136{
1137 return q->q_pgs[idx / q->entry_cnt_per_pg] +
1138 (q->entry_size * (idx % q->entry_cnt_per_pg));
1139}
Linux 6.x block layer and io_uring tree(s)