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[SCSI] hptiop: Support HighPoint RR4520/RR4522 HBA
[linux-2.6-block.git] / drivers / scsi / lpfc / lpfc_sli4.h
CommitLineData
da0436e9
JS		 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
792581de 4 * Copyright (C) 2009-2011 Emulex. All rights reserved. *
da0436e9
JS		 5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
20
21#define LPFC_ACTIVE_MBOX_WAIT_CNT 100
5af5eee7
JS		 22#define LPFC_XRI_EXCH_BUSY_WAIT_TMO 10000
23#define LPFC_XRI_EXCH_BUSY_WAIT_T1 10
24#define LPFC_XRI_EXCH_BUSY_WAIT_T2 30000
da0436e9 25#define LPFC_RELEASE_NOTIFICATION_INTERVAL 32
da0436e9 26#define LPFC_RPI_LOW_WATER_MARK 10
ecfd03c6 27
a93ff37a
JS		 28#define LPFC_UNREG_FCF 1
29#define LPFC_SKIP_UNREG_FCF 0
30
ecfd03c6
JS		 31/* Amount of time in seconds for waiting FCF rediscovery to complete */
32#define LPFC_FCF_REDISCOVER_WAIT_TMO 2000 /* msec */
33
da0436e9
JS		 34/* Number of SGL entries can be posted in a 4KB nonembedded mbox command */
35#define LPFC_NEMBED_MBOX_SGL_CNT 254
36
67d12733
JS		 37/* Multi-queue arrangement for FCP EQ/CQ/WQ tuples */
38#define LPFC_FCP_IO_CHAN_DEF 4
39#define LPFC_FCP_IO_CHAN_MIN 1
82c3e9ba 40#define LPFC_FCP_IO_CHAN_MAX 16
da0436e9
JS		 41
42/*
43 * Provide the default FCF Record attributes used by the driver
44 * when nonFIP mode is configured and there is no other default
45 * FCF Record attributes.
46 */
47#define LPFC_FCOE_FCF_DEF_INDEX 0
48#define LPFC_FCOE_FCF_GET_FIRST 0xFFFF
49#define LPFC_FCOE_FCF_NEXT_NONE 0xFFFF
50
dbb6b3ab
JS		 51#define LPFC_FCOE_NULL_VID 0xFFF
52#define LPFC_FCOE_IGNORE_VID 0xFFFF
53
da0436e9
JS		 54/* First 3 bytes of default FCF MAC is specified by FC_MAP */
55#define LPFC_FCOE_FCF_MAC3 0xFF
56#define LPFC_FCOE_FCF_MAC4 0xFF
57#define LPFC_FCOE_FCF_MAC5 0xFE
58#define LPFC_FCOE_FCF_MAP0 0x0E
59#define LPFC_FCOE_FCF_MAP1 0xFC
60#define LPFC_FCOE_FCF_MAP2 0x00
98fc5dd9 61#define LPFC_FCOE_MAX_RCV_SIZE 0x800
da0436e9
JS		 62#define LPFC_FCOE_FKA_ADV_PER 0
63#define LPFC_FCOE_FIP_PRIORITY 0x80
64
6669f9bb
JS		 65#define sli4_sid_from_fc_hdr(fc_hdr) \
66 ((fc_hdr)->fh_s_id[0] << 16 | \
67 (fc_hdr)->fh_s_id[1] << 8 | \
68 (fc_hdr)->fh_s_id[2])
69
939723a4
JS		 70#define sli4_did_from_fc_hdr(fc_hdr) \
71 ((fc_hdr)->fh_d_id[0] << 16 | \
72 (fc_hdr)->fh_d_id[1] << 8 | \
73 (fc_hdr)->fh_d_id[2])
74
5ffc266e
JS		 75#define sli4_fctl_from_fc_hdr(fc_hdr) \
76 ((fc_hdr)->fh_f_ctl[0] << 16 | \
77 (fc_hdr)->fh_f_ctl[1] << 8 | \
78 (fc_hdr)->fh_f_ctl[2])
79
939723a4
JS		 80#define sli4_type_from_fc_hdr(fc_hdr) \
81 ((fc_hdr)->fh_type)
82
88a2cfbb
JS		 83#define LPFC_FW_RESET_MAXIMUM_WAIT_10MS_CNT 12000
84
da0436e9
JS		 85enum lpfc_sli4_queue_type {
86 LPFC_EQ,
87 LPFC_GCQ,
88 LPFC_MCQ,
89 LPFC_WCQ,
90 LPFC_RCQ,
91 LPFC_MQ,
92 LPFC_WQ,
93 LPFC_HRQ,
94 LPFC_DRQ
95};
96
97/* The queue sub-type defines the functional purpose of the queue */
98enum lpfc_sli4_queue_subtype {
99 LPFC_NONE,
100 LPFC_MBOX,
101 LPFC_FCP,
102 LPFC_ELS,
103 LPFC_USOL
104};
105
106union sli4_qe {
107 void *address;
108 struct lpfc_eqe *eqe;
109 struct lpfc_cqe *cqe;
110 struct lpfc_mcqe *mcqe;
111 struct lpfc_wcqe_complete *wcqe_complete;
112 struct lpfc_wcqe_release *wcqe_release;
113 struct sli4_wcqe_xri_aborted *wcqe_xri_aborted;
114 struct lpfc_rcqe_complete *rcqe_complete;
115 struct lpfc_mqe *mqe;
116 union lpfc_wqe *wqe;
117 struct lpfc_rqe *rqe;
118};
119
120struct lpfc_queue {
121 struct list_head list;
122 enum lpfc_sli4_queue_type type;
123 enum lpfc_sli4_queue_subtype subtype;
124 struct lpfc_hba *phba;
125 struct list_head child_list;
126 uint32_t entry_count; /* Number of entries to support on the queue */
127 uint32_t entry_size; /* Size of each queue entry. */
73d91e50
JS		 128 uint32_t entry_repost; /* Count of entries before doorbell is rung */
129#define LPFC_QUEUE_MIN_REPOST 8
da0436e9 130 uint32_t queue_id; /* Queue ID assigned by the hardware */
2a622bfb 131 uint32_t assoc_qid; /* Queue ID associated with, for CQ/WQ/MQ */
da0436e9
JS		 132 struct list_head page_list;
133 uint32_t page_count; /* Number of pages allocated for this queue */
da0436e9
JS		 134 uint32_t host_index; /* The host's index for putting or getting */
135 uint32_t hba_index; /* The last known hba index for get or put */
b84daac9 136
2a76a283
JS		 137 struct lpfc_sli_ring *pring; /* ptr to io ring associated with q */
138
b84daac9
JS		 139 /* For q stats */
140 uint32_t q_cnt_1;
141 uint32_t q_cnt_2;
142 uint32_t q_cnt_3;
143 uint64_t q_cnt_4;
144/* defines for EQ stats */
145#define EQ_max_eqe q_cnt_1
146#define EQ_no_entry q_cnt_2
147#define EQ_badstate q_cnt_3
148#define EQ_processed q_cnt_4
149
150/* defines for CQ stats */
151#define CQ_mbox q_cnt_1
152#define CQ_max_cqe q_cnt_1
153#define CQ_release_wqe q_cnt_2
154#define CQ_xri_aborted q_cnt_3
155#define CQ_wq q_cnt_4
156
157/* defines for WQ stats */
158#define WQ_overflow q_cnt_1
159#define WQ_posted q_cnt_4
160
161/* defines for RQ stats */
162#define RQ_no_posted_buf q_cnt_1
163#define RQ_no_buf_found q_cnt_2
164#define RQ_buf_trunc q_cnt_3
165#define RQ_rcv_buf q_cnt_4
166
da0436e9
JS		 167 union sli4_qe qe[1]; /* array to index entries (must be last) */
168};
169
da0436e9 170struct lpfc_sli4_link {
8b68cd52 171 uint16_t speed;
da0436e9
JS		 172 uint8_t duplex;
173 uint8_t status;
70f3c073
JS		 174 uint8_t type;
175 uint8_t number;
da0436e9 176 uint8_t fault;
65467b6b 177 uint16_t logical_speed;
70f3c073 178 uint16_t topology;
da0436e9
JS		 179};
180
ecfd03c6
JS		 181struct lpfc_fcf_rec {
182 uint8_t fabric_name[8];
183 uint8_t switch_name[8];
da0436e9
JS		 184 uint8_t mac_addr[6];
185 uint16_t fcf_indx;
ecfd03c6
JS		 186 uint32_t priority;
187 uint16_t vlan_id;
188 uint32_t addr_mode;
189 uint32_t flag;
190#define BOOT_ENABLE 0x01
191#define RECORD_VALID 0x02
192};
193
7d791df7
JS		 194struct lpfc_fcf_pri_rec {
195 uint16_t fcf_index;
196#define LPFC_FCF_ON_PRI_LIST 0x0001
197#define LPFC_FCF_FLOGI_FAILED 0x0002
198 uint16_t flag;
199 uint32_t priority;
200};
201
202struct lpfc_fcf_pri {
203 struct list_head list;
204 struct lpfc_fcf_pri_rec fcf_rec;
205};
206
207/*
208 * Maximum FCF table index, it is for driver internal book keeping, it
209 * just needs to be no less than the supported HBA's FCF table size.
210 */
211#define LPFC_SLI4_FCF_TBL_INDX_MAX 32
212
ecfd03c6 213struct lpfc_fcf {
da0436e9
JS		 214 uint16_t fcfi;
215 uint32_t fcf_flag;
216#define FCF_AVAILABLE 0x01 /* FCF available for discovery */
217#define FCF_REGISTERED 0x02 /* FCF registered with FW */
ecfd03c6
JS		 218#define FCF_SCAN_DONE 0x04 /* FCF table scan done */
219#define FCF_IN_USE 0x08 /* Atleast one discovery completed */
0c9ab6f5
JS		 220#define FCF_INIT_DISC 0x10 /* Initial FCF discovery */
221#define FCF_DEAD_DISC 0x20 /* FCF DEAD fast FCF failover discovery */
222#define FCF_ACVL_DISC 0x40 /* All CVL fast FCF failover discovery */
223#define FCF_DISCOVERY (FCF_INIT_DISC | FCF_DEAD_DISC | FCF_ACVL_DISC)
224#define FCF_REDISC_PEND 0x80 /* FCF rediscovery pending */
225#define FCF_REDISC_EVT 0x100 /* FCF rediscovery event to worker thread */
226#define FCF_REDISC_FOV 0x200 /* Post FCF rediscovery fast failover */
a93ff37a 227#define FCF_REDISC_PROG (FCF_REDISC_PEND | FCF_REDISC_EVT)
da0436e9 228 uint32_t addr_mode;
999d813f 229 uint32_t eligible_fcf_cnt;
ecfd03c6
JS		 230 struct lpfc_fcf_rec current_rec;
231 struct lpfc_fcf_rec failover_rec;
7d791df7
JS		 232 struct list_head fcf_pri_list;
233 struct lpfc_fcf_pri fcf_pri[LPFC_SLI4_FCF_TBL_INDX_MAX];
234 uint32_t current_fcf_scan_pri;
ecfd03c6 235 struct timer_list redisc_wait;
0c9ab6f5 236 unsigned long *fcf_rr_bmask; /* Eligible FCF indexes for RR failover */
da0436e9
JS		 237};
238
0c9ab6f5 239
da0436e9
JS		 240#define LPFC_REGION23_SIGNATURE "RG23"
241#define LPFC_REGION23_VERSION 1
242#define LPFC_REGION23_LAST_REC 0xff
a0c87cbd
JS		 243#define DRIVER_SPECIFIC_TYPE 0xA2
244#define LINUX_DRIVER_ID 0x20
245#define PORT_STE_TYPE 0x1
246
da0436e9
JS		 247struct lpfc_fip_param_hdr {
248 uint8_t type;
249#define FCOE_PARAM_TYPE 0xA0
250 uint8_t length;
251#define FCOE_PARAM_LENGTH 2
252 uint8_t parm_version;
253#define FIPP_VERSION 0x01
254 uint8_t parm_flags;
255#define lpfc_fip_param_hdr_fipp_mode_SHIFT 6
256#define lpfc_fip_param_hdr_fipp_mode_MASK 0x3
257#define lpfc_fip_param_hdr_fipp_mode_WORD parm_flags
6a9c52cf 258#define FIPP_MODE_ON 0x1
da0436e9
JS		 259#define FIPP_MODE_OFF 0x0
260#define FIPP_VLAN_VALID 0x1
261};
262
263struct lpfc_fcoe_params {
264 uint8_t fc_map[3];
265 uint8_t reserved1;
266 uint16_t vlan_tag;
267 uint8_t reserved[2];
268};
269
270struct lpfc_fcf_conn_hdr {
271 uint8_t type;
272#define FCOE_CONN_TBL_TYPE 0xA1
273 uint8_t length; /* words */
274 uint8_t reserved[2];
275};
276
277struct lpfc_fcf_conn_rec {
278 uint16_t flags;
279#define FCFCNCT_VALID 0x0001
280#define FCFCNCT_BOOT 0x0002
281#define FCFCNCT_PRIMARY 0x0004 /* if not set, Secondary */
282#define FCFCNCT_FBNM_VALID 0x0008
283#define FCFCNCT_SWNM_VALID 0x0010
284#define FCFCNCT_VLAN_VALID 0x0020
285#define FCFCNCT_AM_VALID 0x0040
286#define FCFCNCT_AM_PREFERRED 0x0080 /* if not set, AM Required */
287#define FCFCNCT_AM_SPMA 0x0100 /* if not set, FPMA */
288
289 uint16_t vlan_tag;
290 uint8_t fabric_name[8];
291 uint8_t switch_name[8];
292};
293
294struct lpfc_fcf_conn_entry {
295 struct list_head list;
296 struct lpfc_fcf_conn_rec conn_rec;
297};
298
299/*
300 * Define the host's bootstrap mailbox. This structure contains
301 * the member attributes needed to create, use, and destroy the
302 * bootstrap mailbox region.
303 *
304 * The macro definitions for the bmbx data structure are defined
305 * in lpfc_hw4.h with the register definition.
306 */
307struct lpfc_bmbx {
308 struct lpfc_dmabuf *dmabuf;
309 struct dma_address dma_address;
310 void *avirt;
311 dma_addr_t aphys;
312 uint32_t bmbx_size;
313};
314
315#define LPFC_EQE_SIZE LPFC_EQE_SIZE_4
316
317#define LPFC_EQE_SIZE_4B 4
318#define LPFC_EQE_SIZE_16B 16
319#define LPFC_CQE_SIZE 16
320#define LPFC_WQE_SIZE 64
321#define LPFC_MQE_SIZE 256
322#define LPFC_RQE_SIZE 8
323
324#define LPFC_EQE_DEF_COUNT 1024
ff78d8f9 325#define LPFC_CQE_DEF_COUNT 1024
f1126688 326#define LPFC_WQE_DEF_COUNT 256
da0436e9
JS		 327#define LPFC_MQE_DEF_COUNT 16
328#define LPFC_RQE_DEF_COUNT 512
329
330#define LPFC_QUEUE_NOARM false
331#define LPFC_QUEUE_REARM true
332
333
334/*
335 * SLI4 CT field defines
336 */
337#define SLI4_CT_RPI 0
338#define SLI4_CT_VPI 1
339#define SLI4_CT_VFI 2
340#define SLI4_CT_FCFI 3
341
28baac74
JS		 342#define LPFC_SLI4_FL1_MAX_SEGMENT_SIZE 0x10000
343#define LPFC_SLI4_FL1_MAX_BUF_SIZE 0X2000
344#define LPFC_SLI4_MIN_BUF_SIZE 0x400
345#define LPFC_SLI4_MAX_BUF_SIZE 0x20000
da0436e9
JS		 346
347/*
348 * SLI4 specific data structures
349 */
350struct lpfc_max_cfg_param {
351 uint16_t max_xri;
352 uint16_t xri_base;
353 uint16_t xri_used;
354 uint16_t max_rpi;
355 uint16_t rpi_base;
356 uint16_t rpi_used;
357 uint16_t max_vpi;
358 uint16_t vpi_base;
359 uint16_t vpi_used;
360 uint16_t max_vfi;
361 uint16_t vfi_base;
362 uint16_t vfi_used;
363 uint16_t max_fcfi;
da0436e9
JS		 364 uint16_t fcfi_used;
365 uint16_t max_eq;
366 uint16_t max_rq;
367 uint16_t max_cq;
368 uint16_t max_wq;
369};
370
371struct lpfc_hba;
372/* SLI4 HBA multi-fcp queue handler struct */
373struct lpfc_fcp_eq_hdl {
374 uint32_t idx;
375 struct lpfc_hba *phba;
ba20c853 376 atomic_t fcp_eq_in_use;
da0436e9
JS		 377};
378
28baac74
JS		 379/* Port Capabilities for SLI4 Parameters */
380struct lpfc_pc_sli4_params {
381 uint32_t supported;
382 uint32_t if_type;
383 uint32_t sli_rev;
384 uint32_t sli_family;
385 uint32_t featurelevel_1;
386 uint32_t featurelevel_2;
387 uint32_t proto_types;
388#define LPFC_SLI4_PROTO_FCOE 0x0000001
389#define LPFC_SLI4_PROTO_FC 0x0000002
390#define LPFC_SLI4_PROTO_NIC 0x0000004
391#define LPFC_SLI4_PROTO_ISCSI 0x0000008
392#define LPFC_SLI4_PROTO_RDMA 0x0000010
393 uint32_t sge_supp_len;
394 uint32_t if_page_sz;
395 uint32_t rq_db_window;
396 uint32_t loopbk_scope;
397 uint32_t eq_pages_max;
398 uint32_t eqe_size;
399 uint32_t cq_pages_max;
400 uint32_t cqe_size;
401 uint32_t mq_pages_max;
402 uint32_t mqe_size;
403 uint32_t mq_elem_cnt;
404 uint32_t wq_pages_max;
405 uint32_t wqe_size;
406 uint32_t rq_pages_max;
407 uint32_t rqe_size;
408 uint32_t hdr_pages_max;
409 uint32_t hdr_size;
410 uint32_t hdr_pp_align;
411 uint32_t sgl_pages_max;
412 uint32_t sgl_pp_align;
fedd3b7b
JS		 413 uint8_t cqv;
414 uint8_t mqv;
415 uint8_t wqv;
416 uint8_t rqv;
28baac74
JS		 417};
418
912e3acd
JS		 419struct lpfc_iov {
420 uint32_t pf_number;
421 uint32_t vf_number;
422};
423
cd1c8301
JS		 424struct lpfc_sli4_lnk_info {
425 uint8_t lnk_dv;
426#define LPFC_LNK_DAT_INVAL 0
427#define LPFC_LNK_DAT_VAL 1
428 uint8_t lnk_tp;
429#define LPFC_LNK_GE 0x0 /* FCoE */
430#define LPFC_LNK_FC 0x1 /* FC */
431 uint8_t lnk_no;
432};
433
4305f183
JS		 434#define LPFC_SLI4_HANDLER_NAME_SZ 16
435
da0436e9
JS		 436/* SLI4 HBA data structure entries */
437struct lpfc_sli4_hba {
438 void __iomem *conf_regs_memmap_p; /* Kernel memory mapped address for
439 PCI BAR0, config space registers */
440 void __iomem *ctrl_regs_memmap_p; /* Kernel memory mapped address for
441 PCI BAR1, control registers */
442 void __iomem *drbl_regs_memmap_p; /* Kernel memory mapped address for
443 PCI BAR2, doorbell registers */
2fcee4bf
JS		 444 union {
445 struct {
446 /* IF Type 0, BAR 0 PCI cfg space reg mem map */
447 void __iomem *UERRLOregaddr;
448 void __iomem *UERRHIregaddr;
449 void __iomem *UEMASKLOregaddr;
450 void __iomem *UEMASKHIregaddr;
451 } if_type0;
452 struct {
453 /* IF Type 2, BAR 0 PCI cfg space reg mem map. */
454 void __iomem *STATUSregaddr;
455 void __iomem *CTRLregaddr;
456 void __iomem *ERR1regaddr;
2e90f4b5
JS		 457#define SLIPORT_ERR1_REG_ERR_CODE_1 0x1
458#define SLIPORT_ERR1_REG_ERR_CODE_2 0x2
2fcee4bf 459 void __iomem *ERR2regaddr;
2e90f4b5
JS		 460#define SLIPORT_ERR2_REG_FW_RESTART 0x0
461#define SLIPORT_ERR2_REG_FUNC_PROVISON 0x1
462#define SLIPORT_ERR2_REG_FORCED_DUMP 0x2
463#define SLIPORT_ERR2_REG_FAILURE_EQ 0x3
464#define SLIPORT_ERR2_REG_FAILURE_CQ 0x4
465#define SLIPORT_ERR2_REG_FAILURE_BUS 0x5
466#define SLIPORT_ERR2_REG_FAILURE_RQ 0x6
2fcee4bf
JS		 467 } if_type2;
468 } u;
469
470 /* IF type 0, BAR1 and if type 2, Bar 0 CSR register memory map */
471 void __iomem *PSMPHRregaddr;
472
473 /* Well-known SLI INTF register memory map. */
474 void __iomem *SLIINTFregaddr;
475
476 /* IF type 0, BAR 1 function CSR register memory map */
477 void __iomem *ISRregaddr; /* HST_ISR register */
478 void __iomem *IMRregaddr; /* HST_IMR register */
479 void __iomem *ISCRregaddr; /* HST_ISCR register */
480 /* IF type 0, BAR 0 and if type 2, BAR 0 doorbell register memory map */
481 void __iomem *RQDBregaddr; /* RQ_DOORBELL register */
482 void __iomem *WQDBregaddr; /* WQ_DOORBELL register */
483 void __iomem *EQCQDBregaddr; /* EQCQ_DOORBELL register */
484 void __iomem *MQDBregaddr; /* MQ_DOORBELL register */
485 void __iomem *BMBXregaddr; /* BootStrap MBX register */
da0436e9 486
a747c9ce
JS		 487 uint32_t ue_mask_lo;
488 uint32_t ue_mask_hi;
28baac74
JS		 489 struct lpfc_register sli_intf;
490 struct lpfc_pc_sli4_params pc_sli4_params;
da0436e9 491 struct msix_entry *msix_entries;
4305f183 492 uint8_t handler_name[LPFC_FCP_IO_CHAN_MAX][LPFC_SLI4_HANDLER_NAME_SZ];
da0436e9 493 struct lpfc_fcp_eq_hdl *fcp_eq_hdl; /* FCP per-WQ handle */
67d12733 494
da0436e9 495 /* Pointers to the constructed SLI4 queues */
67d12733
JS		 496 struct lpfc_queue **hba_eq;/* Event queues for HBA */
497 struct lpfc_queue **fcp_cq;/* Fast-path FCP compl queue */
da0436e9 498 struct lpfc_queue **fcp_wq;/* Fast-path FCP work queue */
67d12733
JS		 499 uint16_t *fcp_cq_map;
500
501 struct lpfc_queue *mbx_cq; /* Slow-path mailbox complete queue */
502 struct lpfc_queue *els_cq; /* Slow-path ELS response complete queue */
da0436e9
JS		 503 struct lpfc_queue *mbx_wq; /* Slow-path MBOX work queue */
504 struct lpfc_queue *els_wq; /* Slow-path ELS work queue */
505 struct lpfc_queue *hdr_rq; /* Slow-path Header Receive queue */
506 struct lpfc_queue *dat_rq; /* Slow-path Data Receive queue */
da0436e9
JS		 507
508 /* Setup information for various queue parameters */
509 int eq_esize;
510 int eq_ecount;
511 int cq_esize;
512 int cq_ecount;
513 int wq_esize;
514 int wq_ecount;
515 int mq_esize;
516 int mq_ecount;
517 int rq_esize;
518 int rq_ecount;
519#define LPFC_SP_EQ_MAX_INTR_SEC 10000
520#define LPFC_FP_EQ_MAX_INTR_SEC 10000
521
522 uint32_t intr_enable;
523 struct lpfc_bmbx bmbx;
524 struct lpfc_max_cfg_param max_cfg_param;
6d368e53
JS		 525 uint16_t extents_in_use; /* must allocate resource extents. */
526 uint16_t rpi_hdrs_in_use; /* must post rpi hdrs if set. */
da0436e9
JS		 527 uint16_t next_xri; /* last_xri - max_cfg_param.xri_base = used */
528 uint16_t next_rpi;
529 uint16_t scsi_xri_max;
530 uint16_t scsi_xri_cnt;
8a9d2e80 531 uint16_t els_xri_cnt;
6d368e53 532 uint16_t scsi_xri_start;
da0436e9
JS		 533 struct list_head lpfc_free_sgl_list;
534 struct list_head lpfc_sgl_list;
da0436e9 535 struct list_head lpfc_abts_els_sgl_list;
da0436e9 536 struct list_head lpfc_abts_scsi_buf_list;
da0436e9
JS		 537 struct lpfc_sglq **lpfc_sglq_active_list;
538 struct list_head lpfc_rpi_hdr_list;
539 unsigned long *rpi_bmask;
6d368e53 540 uint16_t *rpi_ids;
da0436e9 541 uint16_t rpi_count;
6d368e53
JS		 542 struct list_head lpfc_rpi_blk_list;
543 unsigned long *xri_bmask;
544 uint16_t *xri_ids;
6d368e53
JS		 545 struct list_head lpfc_xri_blk_list;
546 unsigned long *vfi_bmask;
547 uint16_t *vfi_ids;
548 uint16_t vfi_count;
549 struct list_head lpfc_vfi_blk_list;
da0436e9 550 struct lpfc_sli4_flags sli4_flags;
45ed1190 551 struct list_head sp_queue_event;
da0436e9
JS		 552 struct list_head sp_cqe_event_pool;
553 struct list_head sp_asynce_work_queue;
554 struct list_head sp_fcp_xri_aborted_work_queue;
555 struct list_head sp_els_xri_aborted_work_queue;
556 struct list_head sp_unsol_work_queue;
557 struct lpfc_sli4_link link_state;
cd1c8301
JS		 558 struct lpfc_sli4_lnk_info lnk_info;
559 uint32_t pport_name_sta;
560#define LPFC_SLI4_PPNAME_NON 0
561#define LPFC_SLI4_PPNAME_GET 1
912e3acd 562 struct lpfc_iov iov;
da0436e9
JS		 563 spinlock_t abts_scsi_buf_list_lock; /* list of aborted SCSI IOs */
564 spinlock_t abts_sgl_list_lock; /* list of aborted els IOs */
565};
566
567enum lpfc_sge_type {
568 GEN_BUFF_TYPE,
569 SCSI_BUFF_TYPE
570};
571
0f65ff68
JS		 572enum lpfc_sgl_state {
573 SGL_FREED,
574 SGL_ALLOCATED,
575 SGL_XRI_ABORTED
576};
577
da0436e9
JS		 578struct lpfc_sglq {
579 /* lpfc_sglqs are used in double linked lists */
580 struct list_head list;
581 struct list_head clist;
582 enum lpfc_sge_type buff_type; /* is this a scsi sgl */
0f65ff68 583 enum lpfc_sgl_state state;
19ca7609 584 struct lpfc_nodelist *ndlp; /* ndlp associated with IO */
da0436e9 585 uint16_t iotag; /* pre-assigned IO tag */
6d368e53 586 uint16_t sli4_lxritag; /* logical pre-assigned xri. */
da0436e9
JS		 587 uint16_t sli4_xritag; /* pre-assigned XRI, (OXID) tag. */
588 struct sli4_sge *sgl; /* pre-assigned SGL */
589 void *virt; /* virtual address. */
590 dma_addr_t phys; /* physical address */
591};
592
593struct lpfc_rpi_hdr {
594 struct list_head list;
595 uint32_t len;
596 struct lpfc_dmabuf *dmabuf;
597 uint32_t page_count;
598 uint32_t start_rpi;
599};
600
6d368e53
JS		 601struct lpfc_rsrc_blks {
602 struct list_head list;
603 uint16_t rsrc_start;
604 uint16_t rsrc_size;
605 uint16_t rsrc_used;
606};
607
da0436e9
JS		 608/*
609 * SLI4 specific function prototypes
610 */
611int lpfc_pci_function_reset(struct lpfc_hba *);
73d91e50 612int lpfc_sli4_pdev_status_reg_wait(struct lpfc_hba *);
da0436e9 613int lpfc_sli4_hba_setup(struct lpfc_hba *);
da0436e9
JS		 614int lpfc_sli4_config(struct lpfc_hba *, struct lpfcMboxq *, uint8_t,
615 uint8_t, uint32_t, bool);
616void lpfc_sli4_mbox_cmd_free(struct lpfc_hba *, struct lpfcMboxq *);
617void lpfc_sli4_mbx_sge_set(struct lpfcMboxq *, uint32_t, dma_addr_t, uint32_t);
618void lpfc_sli4_mbx_sge_get(struct lpfcMboxq *, uint32_t,
619 struct lpfc_mbx_sge *);
0c9ab6f5
JS		 620int lpfc_sli4_mbx_read_fcf_rec(struct lpfc_hba *, struct lpfcMboxq *,
621 uint16_t);
da0436e9
JS		 622
623void lpfc_sli4_hba_reset(struct lpfc_hba *);
624struct lpfc_queue *lpfc_sli4_queue_alloc(struct lpfc_hba *, uint32_t,
625 uint32_t);
626void lpfc_sli4_queue_free(struct lpfc_queue *);
ee02006b 627uint32_t lpfc_eq_create(struct lpfc_hba *, struct lpfc_queue *, uint32_t);
173edbb2 628uint32_t lpfc_modify_fcp_eq_delay(struct lpfc_hba *, uint16_t);
da0436e9
JS		 629uint32_t lpfc_cq_create(struct lpfc_hba *, struct lpfc_queue *,
630 struct lpfc_queue *, uint32_t, uint32_t);
b19a061a
JS		 631int32_t lpfc_mq_create(struct lpfc_hba *, struct lpfc_queue *,
632 struct lpfc_queue *, uint32_t);
da0436e9
JS		 633uint32_t lpfc_wq_create(struct lpfc_hba *, struct lpfc_queue *,
634 struct lpfc_queue *, uint32_t);
635uint32_t lpfc_rq_create(struct lpfc_hba *, struct lpfc_queue *,
636 struct lpfc_queue *, struct lpfc_queue *, uint32_t);
73d91e50 637void lpfc_rq_adjust_repost(struct lpfc_hba *, struct lpfc_queue *, int);
da0436e9
JS		 638uint32_t lpfc_eq_destroy(struct lpfc_hba *, struct lpfc_queue *);
639uint32_t lpfc_cq_destroy(struct lpfc_hba *, struct lpfc_queue *);
640uint32_t lpfc_mq_destroy(struct lpfc_hba *, struct lpfc_queue *);
641uint32_t lpfc_wq_destroy(struct lpfc_hba *, struct lpfc_queue *);
642uint32_t lpfc_rq_destroy(struct lpfc_hba *, struct lpfc_queue *,
643 struct lpfc_queue *);
644int lpfc_sli4_queue_setup(struct lpfc_hba *);
645void lpfc_sli4_queue_unset(struct lpfc_hba *);
646int lpfc_sli4_post_sgl(struct lpfc_hba *, dma_addr_t, dma_addr_t, uint16_t);
647int lpfc_sli4_repost_scsi_sgl_list(struct lpfc_hba *);
da0436e9
JS		 648uint16_t lpfc_sli4_next_xritag(struct lpfc_hba *);
649int lpfc_sli4_post_async_mbox(struct lpfc_hba *);
da0436e9
JS		 650int lpfc_sli4_post_scsi_sgl_block(struct lpfc_hba *, struct list_head *, int);
651struct lpfc_cq_event *__lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
652struct lpfc_cq_event *lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
653void __lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
654void lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
655int lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *);
656int lpfc_sli4_post_rpi_hdr(struct lpfc_hba *, struct lpfc_rpi_hdr *);
657int lpfc_sli4_post_all_rpi_hdrs(struct lpfc_hba *);
658struct lpfc_rpi_hdr *lpfc_sli4_create_rpi_hdr(struct lpfc_hba *);
659void lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *);
660int lpfc_sli4_alloc_rpi(struct lpfc_hba *);
661void lpfc_sli4_free_rpi(struct lpfc_hba *, int);
662void lpfc_sli4_remove_rpis(struct lpfc_hba *);
663void lpfc_sli4_async_event_proc(struct lpfc_hba *);
ecfd03c6 664void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *);
6b5151fd
JS		 665int lpfc_sli4_resume_rpi(struct lpfc_nodelist *,
666 void (*)(struct lpfc_hba *, LPFC_MBOXQ_t *), void *);
da0436e9
JS		 667void lpfc_sli4_fcp_xri_abort_event_proc(struct lpfc_hba *);
668void lpfc_sli4_els_xri_abort_event_proc(struct lpfc_hba *);
669void lpfc_sli4_fcp_xri_aborted(struct lpfc_hba *,
670 struct sli4_wcqe_xri_aborted *);
671void lpfc_sli4_els_xri_aborted(struct lpfc_hba *,
672 struct sli4_wcqe_xri_aborted *);
1151e3ec
JS		 673void lpfc_sli4_vport_delete_els_xri_aborted(struct lpfc_vport *);
674void lpfc_sli4_vport_delete_fcp_xri_aborted(struct lpfc_vport *);
da0436e9
JS		 675int lpfc_sli4_brdreset(struct lpfc_hba *);
676int lpfc_sli4_add_fcf_record(struct lpfc_hba *, struct fcf_record *);
677void lpfc_sli_remove_dflt_fcf(struct lpfc_hba *);
678int lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *);
76a95d75 679int lpfc_sli4_init_vpi(struct lpfc_vport *);
da0436e9
JS		 680uint32_t lpfc_sli4_cq_release(struct lpfc_queue *, bool);
681uint32_t lpfc_sli4_eq_release(struct lpfc_queue *, bool);
682void lpfc_sli4_fcfi_unreg(struct lpfc_hba *, uint16_t);
0c9ab6f5
JS		 683int lpfc_sli4_fcf_scan_read_fcf_rec(struct lpfc_hba *, uint16_t);
684int lpfc_sli4_fcf_rr_read_fcf_rec(struct lpfc_hba *, uint16_t);
685int lpfc_sli4_read_fcf_rec(struct lpfc_hba *, uint16_t);
686void lpfc_mbx_cmpl_fcf_scan_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
687void lpfc_mbx_cmpl_fcf_rr_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
688void lpfc_mbx_cmpl_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
689int lpfc_sli4_unregister_fcf(struct lpfc_hba *);
da0436e9 690int lpfc_sli4_post_status_check(struct lpfc_hba *);
a183a15f
JS		 691uint8_t lpfc_sli_config_mbox_subsys_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
692uint8_t lpfc_sli_config_mbox_opcode_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
Linux 6.x block layer and io_uring tree(s)