scsi: lpfc: Fix duplicate wq_create_version check
[linux-2.6-block.git] / drivers / scsi / lpfc / lpfc_init.c
CommitLineData
dea3101e 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
145e5a8a 4 * Copyright (C) 2017-2020 Broadcom. All Rights Reserved. The term *
3e21d1cb 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
50611577 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
c44ce173 7 * EMULEX and SLI are trademarks of Emulex. *
d080abe0 8 * www.broadcom.com *
c44ce173 9 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
dea3101e 10 * *
11 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC
12 * modify it under the terms of version 2 of the GNU General *
13 * Public License as published by the Free Software Foundation. *
14 * This program is distributed in the hope that it will be useful. *
15 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
16 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
18 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
19 * TO BE LEGALLY INVALID. See the GNU General Public License for *
20 * more details, a copy of which can be found in the file COPYING *
21 * included with this package. *
dea3101e 22 *******************************************************************/
23
dea3101e 24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/idr.h>
28#include <linux/interrupt.h>
acf3368f 29#include <linux/module.h>
dea3101e 30#include <linux/kthread.h>
31#include <linux/pci.h>
32#include <linux/spinlock.h>
92d7f7b0 33#include <linux/ctype.h>
0d878419 34#include <linux/aer.h>
5a0e3ad6 35#include <linux/slab.h>
52d52440 36#include <linux/firmware.h>
3ef6d24c 37#include <linux/miscdevice.h>
7bb03bbf 38#include <linux/percpu.h>
895427bd 39#include <linux/msi.h>
6a828b0f 40#include <linux/irq.h>
286871a6 41#include <linux/bitops.h>
31f06d2e 42#include <linux/crash_dump.h>
dcaa2136 43#include <linux/cpu.h>
93a4d6f4 44#include <linux/cpuhotplug.h>
dea3101e 45
91886523 46#include <scsi/scsi.h>
dea3101e 47#include <scsi/scsi_device.h>
48#include <scsi/scsi_host.h>
49#include <scsi/scsi_transport_fc.h>
86c67379
JS
50#include <scsi/scsi_tcq.h>
51#include <scsi/fc/fc_fs.h>
52
da0436e9 53#include "lpfc_hw4.h"
dea3101e 54#include "lpfc_hw.h"
55#include "lpfc_sli.h"
da0436e9 56#include "lpfc_sli4.h"
ea2151b4 57#include "lpfc_nl.h"
dea3101e 58#include "lpfc_disc.h"
dea3101e 59#include "lpfc.h"
895427bd
JS
60#include "lpfc_scsi.h"
61#include "lpfc_nvme.h"
dea3101e 62#include "lpfc_logmsg.h"
63#include "lpfc_crtn.h"
92d7f7b0 64#include "lpfc_vport.h"
dea3101e 65#include "lpfc_version.h"
12f44457 66#include "lpfc_ids.h"
dea3101e 67
93a4d6f4 68static enum cpuhp_state lpfc_cpuhp_state;
7bb03bbf 69/* Used when mapping IRQ vectors in a driver centric manner */
d7b761b0 70static uint32_t lpfc_present_cpu;
7bb03bbf 71
93a4d6f4
JS
72static void __lpfc_cpuhp_remove(struct lpfc_hba *phba);
73static void lpfc_cpuhp_remove(struct lpfc_hba *phba);
74static void lpfc_cpuhp_add(struct lpfc_hba *phba);
dea3101e 75static void lpfc_get_hba_model_desc(struct lpfc_hba *, uint8_t *, uint8_t *);
76static int lpfc_post_rcv_buf(struct lpfc_hba *);
5350d872 77static int lpfc_sli4_queue_verify(struct lpfc_hba *);
da0436e9
JS
78static int lpfc_create_bootstrap_mbox(struct lpfc_hba *);
79static int lpfc_setup_endian_order(struct lpfc_hba *);
da0436e9 80static void lpfc_destroy_bootstrap_mbox(struct lpfc_hba *);
8a9d2e80 81static void lpfc_free_els_sgl_list(struct lpfc_hba *);
f358dd0c 82static void lpfc_free_nvmet_sgl_list(struct lpfc_hba *);
8a9d2e80 83static void lpfc_init_sgl_list(struct lpfc_hba *);
da0436e9
JS
84static int lpfc_init_active_sgl_array(struct lpfc_hba *);
85static void lpfc_free_active_sgl(struct lpfc_hba *);
86static int lpfc_hba_down_post_s3(struct lpfc_hba *phba);
87static int lpfc_hba_down_post_s4(struct lpfc_hba *phba);
88static int lpfc_sli4_cq_event_pool_create(struct lpfc_hba *);
89static void lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *);
90static void lpfc_sli4_cq_event_release_all(struct lpfc_hba *);
618a5230
JS
91static void lpfc_sli4_disable_intr(struct lpfc_hba *);
92static uint32_t lpfc_sli4_enable_intr(struct lpfc_hba *, uint32_t);
1ba981fd 93static void lpfc_sli4_oas_verify(struct lpfc_hba *phba);
6a828b0f 94static uint16_t lpfc_find_cpu_handle(struct lpfc_hba *, uint16_t, int);
aa6ff309 95static void lpfc_setup_bg(struct lpfc_hba *, struct Scsi_Host *);
dea3101e 96
97static struct scsi_transport_template *lpfc_transport_template = NULL;
92d7f7b0 98static struct scsi_transport_template *lpfc_vport_transport_template = NULL;
dea3101e 99static DEFINE_IDR(lpfc_hba_index);
f358dd0c 100#define LPFC_NVMET_BUF_POST 254
dea3101e 101
e59058c4 102/**
3621a710 103 * lpfc_config_port_prep - Perform lpfc initialization prior to config port
e59058c4
JS
104 * @phba: pointer to lpfc hba data structure.
105 *
106 * This routine will do LPFC initialization prior to issuing the CONFIG_PORT
107 * mailbox command. It retrieves the revision information from the HBA and
108 * collects the Vital Product Data (VPD) about the HBA for preparing the
109 * configuration of the HBA.
110 *
111 * Return codes:
112 * 0 - success.
113 * -ERESTART - requests the SLI layer to reset the HBA and try again.
114 * Any other value - indicates an error.
115 **/
dea3101e 116int
2e0fef85 117lpfc_config_port_prep(struct lpfc_hba *phba)
dea3101e 118{
119 lpfc_vpd_t *vp = &phba->vpd;
120 int i = 0, rc;
121 LPFC_MBOXQ_t *pmb;
122 MAILBOX_t *mb;
123 char *lpfc_vpd_data = NULL;
124 uint16_t offset = 0;
125 static char licensed[56] =
126 "key unlock for use with gnu public licensed code only\0";
65a29c16 127 static int init_key = 1;
dea3101e 128
129 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
130 if (!pmb) {
2e0fef85 131 phba->link_state = LPFC_HBA_ERROR;
dea3101e 132 return -ENOMEM;
133 }
134
04c68496 135 mb = &pmb->u.mb;
2e0fef85 136 phba->link_state = LPFC_INIT_MBX_CMDS;
dea3101e 137
138 if (lpfc_is_LC_HBA(phba->pcidev->device)) {
65a29c16
JS
139 if (init_key) {
140 uint32_t *ptext = (uint32_t *) licensed;
dea3101e 141
65a29c16
JS
142 for (i = 0; i < 56; i += sizeof (uint32_t), ptext++)
143 *ptext = cpu_to_be32(*ptext);
144 init_key = 0;
145 }
dea3101e 146
147 lpfc_read_nv(phba, pmb);
148 memset((char*)mb->un.varRDnvp.rsvd3, 0,
149 sizeof (mb->un.varRDnvp.rsvd3));
150 memcpy((char*)mb->un.varRDnvp.rsvd3, licensed,
151 sizeof (licensed));
152
153 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
154
155 if (rc != MBX_SUCCESS) {
372c187b 156 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 157 "0324 Config Port initialization "
dea3101e 158 "error, mbxCmd x%x READ_NVPARM, "
159 "mbxStatus x%x\n",
dea3101e 160 mb->mbxCommand, mb->mbxStatus);
161 mempool_free(pmb, phba->mbox_mem_pool);
162 return -ERESTART;
163 }
164 memcpy(phba->wwnn, (char *)mb->un.varRDnvp.nodename,
2e0fef85
JS
165 sizeof(phba->wwnn));
166 memcpy(phba->wwpn, (char *)mb->un.varRDnvp.portname,
167 sizeof(phba->wwpn));
dea3101e 168 }
169
dfb75133
MW
170 /*
171 * Clear all option bits except LPFC_SLI3_BG_ENABLED,
172 * which was already set in lpfc_get_cfgparam()
173 */
174 phba->sli3_options &= (uint32_t)LPFC_SLI3_BG_ENABLED;
92d7f7b0 175
dea3101e 176 /* Setup and issue mailbox READ REV command */
177 lpfc_read_rev(phba, pmb);
178 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
179 if (rc != MBX_SUCCESS) {
372c187b 180 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 181 "0439 Adapter failed to init, mbxCmd x%x "
dea3101e 182 "READ_REV, mbxStatus x%x\n",
dea3101e 183 mb->mbxCommand, mb->mbxStatus);
184 mempool_free( pmb, phba->mbox_mem_pool);
185 return -ERESTART;
186 }
187
92d7f7b0 188
1de933f3
JSEC
189 /*
190 * The value of rr must be 1 since the driver set the cv field to 1.
191 * This setting requires the FW to set all revision fields.
dea3101e 192 */
1de933f3 193 if (mb->un.varRdRev.rr == 0) {
dea3101e 194 vp->rev.rBit = 0;
372c187b 195 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011
JS
196 "0440 Adapter failed to init, READ_REV has "
197 "missing revision information.\n");
dea3101e 198 mempool_free(pmb, phba->mbox_mem_pool);
199 return -ERESTART;
dea3101e 200 }
201
495a714c
JS
202 if (phba->sli_rev == 3 && !mb->un.varRdRev.v3rsp) {
203 mempool_free(pmb, phba->mbox_mem_pool);
ed957684 204 return -EINVAL;
495a714c 205 }
ed957684 206
dea3101e 207 /* Save information as VPD data */
1de933f3 208 vp->rev.rBit = 1;
92d7f7b0 209 memcpy(&vp->sli3Feat, &mb->un.varRdRev.sli3Feat, sizeof(uint32_t));
1de933f3
JSEC
210 vp->rev.sli1FwRev = mb->un.varRdRev.sli1FwRev;
211 memcpy(vp->rev.sli1FwName, (char*) mb->un.varRdRev.sli1FwName, 16);
212 vp->rev.sli2FwRev = mb->un.varRdRev.sli2FwRev;
213 memcpy(vp->rev.sli2FwName, (char *) mb->un.varRdRev.sli2FwName, 16);
dea3101e 214 vp->rev.biuRev = mb->un.varRdRev.biuRev;
215 vp->rev.smRev = mb->un.varRdRev.smRev;
216 vp->rev.smFwRev = mb->un.varRdRev.un.smFwRev;
217 vp->rev.endecRev = mb->un.varRdRev.endecRev;
218 vp->rev.fcphHigh = mb->un.varRdRev.fcphHigh;
219 vp->rev.fcphLow = mb->un.varRdRev.fcphLow;
220 vp->rev.feaLevelHigh = mb->un.varRdRev.feaLevelHigh;
221 vp->rev.feaLevelLow = mb->un.varRdRev.feaLevelLow;
222 vp->rev.postKernRev = mb->un.varRdRev.postKernRev;
223 vp->rev.opFwRev = mb->un.varRdRev.opFwRev;
224
92d7f7b0
JS
225 /* If the sli feature level is less then 9, we must
226 * tear down all RPIs and VPIs on link down if NPIV
227 * is enabled.
228 */
229 if (vp->rev.feaLevelHigh < 9)
230 phba->sli3_options |= LPFC_SLI3_VPORT_TEARDOWN;
231
dea3101e 232 if (lpfc_is_LC_HBA(phba->pcidev->device))
233 memcpy(phba->RandomData, (char *)&mb->un.varWords[24],
234 sizeof (phba->RandomData));
235
dea3101e 236 /* Get adapter VPD information */
dea3101e 237 lpfc_vpd_data = kmalloc(DMP_VPD_SIZE, GFP_KERNEL);
238 if (!lpfc_vpd_data)
d7c255b2 239 goto out_free_mbox;
dea3101e 240 do {
a0c87cbd 241 lpfc_dump_mem(phba, pmb, offset, DMP_REGION_VPD);
dea3101e 242 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
243
244 if (rc != MBX_SUCCESS) {
245 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011 246 "0441 VPD not present on adapter, "
dea3101e 247 "mbxCmd x%x DUMP VPD, mbxStatus x%x\n",
dea3101e 248 mb->mbxCommand, mb->mbxStatus);
74b72a59 249 mb->un.varDmp.word_cnt = 0;
dea3101e 250 }
04c68496
JS
251 /* dump mem may return a zero when finished or we got a
252 * mailbox error, either way we are done.
253 */
254 if (mb->un.varDmp.word_cnt == 0)
255 break;
d91e3abb
DK
256
257 i = mb->un.varDmp.word_cnt * sizeof(uint32_t);
258 if (offset + i > DMP_VPD_SIZE)
259 i = DMP_VPD_SIZE - offset;
d7c255b2 260 lpfc_sli_pcimem_bcopy(((uint8_t *)mb) + DMP_RSP_OFFSET,
d91e3abb
DK
261 lpfc_vpd_data + offset, i);
262 offset += i;
263 } while (offset < DMP_VPD_SIZE);
264
74b72a59 265 lpfc_parse_vpd(phba, lpfc_vpd_data, offset);
dea3101e 266
267 kfree(lpfc_vpd_data);
dea3101e 268out_free_mbox:
269 mempool_free(pmb, phba->mbox_mem_pool);
270 return 0;
271}
272
e59058c4 273/**
3621a710 274 * lpfc_config_async_cmpl - Completion handler for config async event mbox cmd
e59058c4
JS
275 * @phba: pointer to lpfc hba data structure.
276 * @pmboxq: pointer to the driver internal queue element for mailbox command.
277 *
278 * This is the completion handler for driver's configuring asynchronous event
279 * mailbox command to the device. If the mailbox command returns successfully,
280 * it will set internal async event support flag to 1; otherwise, it will
281 * set internal async event support flag to 0.
282 **/
57127f15
JS
283static void
284lpfc_config_async_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
285{
04c68496 286 if (pmboxq->u.mb.mbxStatus == MBX_SUCCESS)
57127f15
JS
287 phba->temp_sensor_support = 1;
288 else
289 phba->temp_sensor_support = 0;
290 mempool_free(pmboxq, phba->mbox_mem_pool);
291 return;
292}
293
97207482 294/**
3621a710 295 * lpfc_dump_wakeup_param_cmpl - dump memory mailbox command completion handler
97207482
JS
296 * @phba: pointer to lpfc hba data structure.
297 * @pmboxq: pointer to the driver internal queue element for mailbox command.
298 *
299 * This is the completion handler for dump mailbox command for getting
300 * wake up parameters. When this command complete, the response contain
301 * Option rom version of the HBA. This function translate the version number
302 * into a human readable string and store it in OptionROMVersion.
303 **/
304static void
305lpfc_dump_wakeup_param_cmpl(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmboxq)
306{
307 struct prog_id *prg;
308 uint32_t prog_id_word;
309 char dist = ' ';
310 /* character array used for decoding dist type. */
311 char dist_char[] = "nabx";
312
04c68496 313 if (pmboxq->u.mb.mbxStatus != MBX_SUCCESS) {
9f1e1b50 314 mempool_free(pmboxq, phba->mbox_mem_pool);
97207482 315 return;
9f1e1b50 316 }
97207482
JS
317
318 prg = (struct prog_id *) &prog_id_word;
319
320 /* word 7 contain option rom version */
04c68496 321 prog_id_word = pmboxq->u.mb.un.varWords[7];
97207482
JS
322
323 /* Decode the Option rom version word to a readable string */
324 if (prg->dist < 4)
325 dist = dist_char[prg->dist];
326
327 if ((prg->dist == 3) && (prg->num == 0))
a2fc4aef 328 snprintf(phba->OptionROMVersion, 32, "%d.%d%d",
97207482
JS
329 prg->ver, prg->rev, prg->lev);
330 else
a2fc4aef 331 snprintf(phba->OptionROMVersion, 32, "%d.%d%d%c%d",
97207482
JS
332 prg->ver, prg->rev, prg->lev,
333 dist, prg->num);
9f1e1b50 334 mempool_free(pmboxq, phba->mbox_mem_pool);
97207482
JS
335 return;
336}
337
0558056c
JS
338/**
339 * lpfc_update_vport_wwn - Updates the fc_nodename, fc_portname,
340 * cfg_soft_wwnn, cfg_soft_wwpn
341 * @vport: pointer to lpfc vport data structure.
342 *
343 *
344 * Return codes
345 * None.
346 **/
347void
348lpfc_update_vport_wwn(struct lpfc_vport *vport)
349{
aeb3c817
JS
350 uint8_t vvvl = vport->fc_sparam.cmn.valid_vendor_ver_level;
351 u32 *fawwpn_key = (u32 *)&vport->fc_sparam.un.vendorVersion[0];
352
0558056c
JS
353 /* If the soft name exists then update it using the service params */
354 if (vport->phba->cfg_soft_wwnn)
355 u64_to_wwn(vport->phba->cfg_soft_wwnn,
356 vport->fc_sparam.nodeName.u.wwn);
357 if (vport->phba->cfg_soft_wwpn)
358 u64_to_wwn(vport->phba->cfg_soft_wwpn,
359 vport->fc_sparam.portName.u.wwn);
360
361 /*
362 * If the name is empty or there exists a soft name
363 * then copy the service params name, otherwise use the fc name
364 */
365 if (vport->fc_nodename.u.wwn[0] == 0 || vport->phba->cfg_soft_wwnn)
366 memcpy(&vport->fc_nodename, &vport->fc_sparam.nodeName,
367 sizeof(struct lpfc_name));
368 else
369 memcpy(&vport->fc_sparam.nodeName, &vport->fc_nodename,
370 sizeof(struct lpfc_name));
371
aeb3c817
JS
372 /*
373 * If the port name has changed, then set the Param changes flag
374 * to unreg the login
375 */
376 if (vport->fc_portname.u.wwn[0] != 0 &&
377 memcmp(&vport->fc_portname, &vport->fc_sparam.portName,
378 sizeof(struct lpfc_name)))
379 vport->vport_flag |= FAWWPN_PARAM_CHG;
380
381 if (vport->fc_portname.u.wwn[0] == 0 ||
382 vport->phba->cfg_soft_wwpn ||
383 (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR) ||
384 vport->vport_flag & FAWWPN_SET) {
0558056c
JS
385 memcpy(&vport->fc_portname, &vport->fc_sparam.portName,
386 sizeof(struct lpfc_name));
aeb3c817
JS
387 vport->vport_flag &= ~FAWWPN_SET;
388 if (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR)
389 vport->vport_flag |= FAWWPN_SET;
390 }
0558056c
JS
391 else
392 memcpy(&vport->fc_sparam.portName, &vport->fc_portname,
393 sizeof(struct lpfc_name));
394}
395
e59058c4 396/**
3621a710 397 * lpfc_config_port_post - Perform lpfc initialization after config port
e59058c4
JS
398 * @phba: pointer to lpfc hba data structure.
399 *
400 * This routine will do LPFC initialization after the CONFIG_PORT mailbox
401 * command call. It performs all internal resource and state setups on the
402 * port: post IOCB buffers, enable appropriate host interrupt attentions,
403 * ELS ring timers, etc.
404 *
405 * Return codes
406 * 0 - success.
407 * Any other value - error.
408 **/
dea3101e 409int
2e0fef85 410lpfc_config_port_post(struct lpfc_hba *phba)
dea3101e 411{
2e0fef85 412 struct lpfc_vport *vport = phba->pport;
a257bf90 413 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
dea3101e 414 LPFC_MBOXQ_t *pmb;
415 MAILBOX_t *mb;
416 struct lpfc_dmabuf *mp;
417 struct lpfc_sli *psli = &phba->sli;
418 uint32_t status, timeout;
2e0fef85
JS
419 int i, j;
420 int rc;
dea3101e 421
7af67051
JS
422 spin_lock_irq(&phba->hbalock);
423 /*
424 * If the Config port completed correctly the HBA is not
425 * over heated any more.
426 */
427 if (phba->over_temp_state == HBA_OVER_TEMP)
428 phba->over_temp_state = HBA_NORMAL_TEMP;
429 spin_unlock_irq(&phba->hbalock);
430
dea3101e 431 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
432 if (!pmb) {
2e0fef85 433 phba->link_state = LPFC_HBA_ERROR;
dea3101e 434 return -ENOMEM;
435 }
04c68496 436 mb = &pmb->u.mb;
dea3101e 437
dea3101e 438 /* Get login parameters for NID. */
9f1177a3
JS
439 rc = lpfc_read_sparam(phba, pmb, 0);
440 if (rc) {
441 mempool_free(pmb, phba->mbox_mem_pool);
442 return -ENOMEM;
443 }
444
ed957684 445 pmb->vport = vport;
dea3101e 446 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
372c187b 447 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 448 "0448 Adapter failed init, mbxCmd x%x "
dea3101e 449 "READ_SPARM mbxStatus x%x\n",
dea3101e 450 mb->mbxCommand, mb->mbxStatus);
2e0fef85 451 phba->link_state = LPFC_HBA_ERROR;
3e1f0718 452 mp = (struct lpfc_dmabuf *)pmb->ctx_buf;
9f1177a3 453 mempool_free(pmb, phba->mbox_mem_pool);
dea3101e 454 lpfc_mbuf_free(phba, mp->virt, mp->phys);
455 kfree(mp);
456 return -EIO;
457 }
458
3e1f0718 459 mp = (struct lpfc_dmabuf *)pmb->ctx_buf;
dea3101e 460
2e0fef85 461 memcpy(&vport->fc_sparam, mp->virt, sizeof (struct serv_parm));
dea3101e 462 lpfc_mbuf_free(phba, mp->virt, mp->phys);
463 kfree(mp);
3e1f0718 464 pmb->ctx_buf = NULL;
0558056c 465 lpfc_update_vport_wwn(vport);
a257bf90
JS
466
467 /* Update the fc_host data structures with new wwn. */
468 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
469 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
21e9a0a5 470 fc_host_max_npiv_vports(shost) = phba->max_vpi;
a257bf90 471
dea3101e 472 /* If no serial number in VPD data, use low 6 bytes of WWNN */
473 /* This should be consolidated into parse_vpd ? - mr */
474 if (phba->SerialNumber[0] == 0) {
475 uint8_t *outptr;
476
2e0fef85 477 outptr = &vport->fc_nodename.u.s.IEEE[0];
dea3101e 478 for (i = 0; i < 12; i++) {
479 status = *outptr++;
480 j = ((status & 0xf0) >> 4);
481 if (j <= 9)
482 phba->SerialNumber[i] =
483 (char)((uint8_t) 0x30 + (uint8_t) j);
484 else
485 phba->SerialNumber[i] =
486 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
487 i++;
488 j = (status & 0xf);
489 if (j <= 9)
490 phba->SerialNumber[i] =
491 (char)((uint8_t) 0x30 + (uint8_t) j);
492 else
493 phba->SerialNumber[i] =
494 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
495 }
496 }
497
dea3101e 498 lpfc_read_config(phba, pmb);
ed957684 499 pmb->vport = vport;
dea3101e 500 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
372c187b 501 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 502 "0453 Adapter failed to init, mbxCmd x%x "
dea3101e 503 "READ_CONFIG, mbxStatus x%x\n",
dea3101e 504 mb->mbxCommand, mb->mbxStatus);
2e0fef85 505 phba->link_state = LPFC_HBA_ERROR;
dea3101e 506 mempool_free( pmb, phba->mbox_mem_pool);
507 return -EIO;
508 }
509
a0c87cbd
JS
510 /* Check if the port is disabled */
511 lpfc_sli_read_link_ste(phba);
512
dea3101e 513 /* Reset the DFT_HBA_Q_DEPTH to the max xri */
f6770e7d 514 if (phba->cfg_hba_queue_depth > mb->un.varRdConfig.max_xri) {
572709e2
JS
515 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
516 "3359 HBA queue depth changed from %d to %d\n",
f6770e7d
JS
517 phba->cfg_hba_queue_depth,
518 mb->un.varRdConfig.max_xri);
519 phba->cfg_hba_queue_depth = mb->un.varRdConfig.max_xri;
572709e2 520 }
dea3101e 521
522 phba->lmt = mb->un.varRdConfig.lmt;
74b72a59
JW
523
524 /* Get the default values for Model Name and Description */
525 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
526
2e0fef85 527 phba->link_state = LPFC_LINK_DOWN;
dea3101e 528
0b727fea 529 /* Only process IOCBs on ELS ring till hba_state is READY */
895427bd
JS
530 if (psli->sli3_ring[LPFC_EXTRA_RING].sli.sli3.cmdringaddr)
531 psli->sli3_ring[LPFC_EXTRA_RING].flag |= LPFC_STOP_IOCB_EVENT;
532 if (psli->sli3_ring[LPFC_FCP_RING].sli.sli3.cmdringaddr)
533 psli->sli3_ring[LPFC_FCP_RING].flag |= LPFC_STOP_IOCB_EVENT;
dea3101e 534
535 /* Post receive buffers for desired rings */
ed957684
JS
536 if (phba->sli_rev != 3)
537 lpfc_post_rcv_buf(phba);
dea3101e 538
9399627f
JS
539 /*
540 * Configure HBA MSI-X attention conditions to messages if MSI-X mode
541 */
542 if (phba->intr_type == MSIX) {
543 rc = lpfc_config_msi(phba, pmb);
544 if (rc) {
545 mempool_free(pmb, phba->mbox_mem_pool);
546 return -EIO;
547 }
548 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
549 if (rc != MBX_SUCCESS) {
372c187b 550 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
9399627f
JS
551 "0352 Config MSI mailbox command "
552 "failed, mbxCmd x%x, mbxStatus x%x\n",
04c68496
JS
553 pmb->u.mb.mbxCommand,
554 pmb->u.mb.mbxStatus);
9399627f
JS
555 mempool_free(pmb, phba->mbox_mem_pool);
556 return -EIO;
557 }
558 }
559
04c68496 560 spin_lock_irq(&phba->hbalock);
9399627f
JS
561 /* Initialize ERATT handling flag */
562 phba->hba_flag &= ~HBA_ERATT_HANDLED;
563
dea3101e 564 /* Enable appropriate host interrupts */
9940b97b
JS
565 if (lpfc_readl(phba->HCregaddr, &status)) {
566 spin_unlock_irq(&phba->hbalock);
567 return -EIO;
568 }
dea3101e 569 status |= HC_MBINT_ENA | HC_ERINT_ENA | HC_LAINT_ENA;
570 if (psli->num_rings > 0)
571 status |= HC_R0INT_ENA;
572 if (psli->num_rings > 1)
573 status |= HC_R1INT_ENA;
574 if (psli->num_rings > 2)
575 status |= HC_R2INT_ENA;
576 if (psli->num_rings > 3)
577 status |= HC_R3INT_ENA;
578
875fbdfe
JSEC
579 if ((phba->cfg_poll & ENABLE_FCP_RING_POLLING) &&
580 (phba->cfg_poll & DISABLE_FCP_RING_INT))
9399627f 581 status &= ~(HC_R0INT_ENA);
875fbdfe 582
dea3101e 583 writel(status, phba->HCregaddr);
584 readl(phba->HCregaddr); /* flush */
2e0fef85 585 spin_unlock_irq(&phba->hbalock);
dea3101e 586
9399627f
JS
587 /* Set up ring-0 (ELS) timer */
588 timeout = phba->fc_ratov * 2;
256ec0d0
JS
589 mod_timer(&vport->els_tmofunc,
590 jiffies + msecs_to_jiffies(1000 * timeout));
9399627f 591 /* Set up heart beat (HB) timer */
256ec0d0
JS
592 mod_timer(&phba->hb_tmofunc,
593 jiffies + msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
594 phba->hb_outstanding = 0;
595 phba->last_completion_time = jiffies;
9399627f 596 /* Set up error attention (ERATT) polling timer */
256ec0d0 597 mod_timer(&phba->eratt_poll,
65791f1f 598 jiffies + msecs_to_jiffies(1000 * phba->eratt_poll_interval));
dea3101e 599
a0c87cbd 600 if (phba->hba_flag & LINK_DISABLED) {
372c187b
DK
601 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
602 "2598 Adapter Link is disabled.\n");
a0c87cbd
JS
603 lpfc_down_link(phba, pmb);
604 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
605 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
606 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
372c187b
DK
607 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
608 "2599 Adapter failed to issue DOWN_LINK"
609 " mbox command rc 0x%x\n", rc);
a0c87cbd
JS
610
611 mempool_free(pmb, phba->mbox_mem_pool);
612 return -EIO;
613 }
e40a02c1 614 } else if (phba->cfg_suppress_link_up == LPFC_INITIALIZE_LINK) {
026abb87
JS
615 mempool_free(pmb, phba->mbox_mem_pool);
616 rc = phba->lpfc_hba_init_link(phba, MBX_NOWAIT);
617 if (rc)
618 return rc;
dea3101e 619 }
620 /* MBOX buffer will be freed in mbox compl */
57127f15 621 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9f1177a3
JS
622 if (!pmb) {
623 phba->link_state = LPFC_HBA_ERROR;
624 return -ENOMEM;
625 }
626
57127f15
JS
627 lpfc_config_async(phba, pmb, LPFC_ELS_RING);
628 pmb->mbox_cmpl = lpfc_config_async_cmpl;
629 pmb->vport = phba->pport;
630 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
dea3101e 631
57127f15 632 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
372c187b 633 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
57127f15 634 "0456 Adapter failed to issue "
e4e74273 635 "ASYNCEVT_ENABLE mbox status x%x\n",
57127f15
JS
636 rc);
637 mempool_free(pmb, phba->mbox_mem_pool);
638 }
97207482
JS
639
640 /* Get Option rom version */
641 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9f1177a3
JS
642 if (!pmb) {
643 phba->link_state = LPFC_HBA_ERROR;
644 return -ENOMEM;
645 }
646
97207482
JS
647 lpfc_dump_wakeup_param(phba, pmb);
648 pmb->mbox_cmpl = lpfc_dump_wakeup_param_cmpl;
649 pmb->vport = phba->pport;
650 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
651
652 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
372c187b
DK
653 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
654 "0435 Adapter failed "
e4e74273 655 "to get Option ROM version status x%x\n", rc);
97207482
JS
656 mempool_free(pmb, phba->mbox_mem_pool);
657 }
658
d7c255b2 659 return 0;
ce8b3ce5
JS
660}
661
84d1b006
JS
662/**
663 * lpfc_hba_init_link - Initialize the FC link
664 * @phba: pointer to lpfc hba data structure.
6e7288d9 665 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
84d1b006
JS
666 *
667 * This routine will issue the INIT_LINK mailbox command call.
668 * It is available to other drivers through the lpfc_hba data
669 * structure for use as a delayed link up mechanism with the
670 * module parameter lpfc_suppress_link_up.
671 *
672 * Return code
673 * 0 - success
674 * Any other value - error
675 **/
e399b228 676static int
6e7288d9 677lpfc_hba_init_link(struct lpfc_hba *phba, uint32_t flag)
1b51197d
JS
678{
679 return lpfc_hba_init_link_fc_topology(phba, phba->cfg_topology, flag);
680}
681
682/**
683 * lpfc_hba_init_link_fc_topology - Initialize FC link with desired topology
684 * @phba: pointer to lpfc hba data structure.
685 * @fc_topology: desired fc topology.
686 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
687 *
688 * This routine will issue the INIT_LINK mailbox command call.
689 * It is available to other drivers through the lpfc_hba data
690 * structure for use as a delayed link up mechanism with the
691 * module parameter lpfc_suppress_link_up.
692 *
693 * Return code
694 * 0 - success
695 * Any other value - error
696 **/
697int
698lpfc_hba_init_link_fc_topology(struct lpfc_hba *phba, uint32_t fc_topology,
699 uint32_t flag)
84d1b006
JS
700{
701 struct lpfc_vport *vport = phba->pport;
702 LPFC_MBOXQ_t *pmb;
703 MAILBOX_t *mb;
704 int rc;
705
706 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
707 if (!pmb) {
708 phba->link_state = LPFC_HBA_ERROR;
709 return -ENOMEM;
710 }
711 mb = &pmb->u.mb;
712 pmb->vport = vport;
713
026abb87
JS
714 if ((phba->cfg_link_speed > LPFC_USER_LINK_SPEED_MAX) ||
715 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_1G) &&
716 !(phba->lmt & LMT_1Gb)) ||
717 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_2G) &&
718 !(phba->lmt & LMT_2Gb)) ||
719 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_4G) &&
720 !(phba->lmt & LMT_4Gb)) ||
721 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_8G) &&
722 !(phba->lmt & LMT_8Gb)) ||
723 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_10G) &&
724 !(phba->lmt & LMT_10Gb)) ||
725 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_16G) &&
d38dd52c
JS
726 !(phba->lmt & LMT_16Gb)) ||
727 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_32G) &&
fbd8a6ba
JS
728 !(phba->lmt & LMT_32Gb)) ||
729 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_64G) &&
730 !(phba->lmt & LMT_64Gb))) {
026abb87 731 /* Reset link speed to auto */
372c187b
DK
732 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
733 "1302 Invalid speed for this board:%d "
734 "Reset link speed to auto.\n",
735 phba->cfg_link_speed);
026abb87
JS
736 phba->cfg_link_speed = LPFC_USER_LINK_SPEED_AUTO;
737 }
1b51197d 738 lpfc_init_link(phba, pmb, fc_topology, phba->cfg_link_speed);
84d1b006 739 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
1b51197d
JS
740 if (phba->sli_rev < LPFC_SLI_REV4)
741 lpfc_set_loopback_flag(phba);
6e7288d9 742 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
76a95d75 743 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
372c187b
DK
744 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
745 "0498 Adapter failed to init, mbxCmd x%x "
746 "INIT_LINK, mbxStatus x%x\n",
747 mb->mbxCommand, mb->mbxStatus);
76a95d75
JS
748 if (phba->sli_rev <= LPFC_SLI_REV3) {
749 /* Clear all interrupt enable conditions */
750 writel(0, phba->HCregaddr);
751 readl(phba->HCregaddr); /* flush */
752 /* Clear all pending interrupts */
753 writel(0xffffffff, phba->HAregaddr);
754 readl(phba->HAregaddr); /* flush */
755 }
84d1b006 756 phba->link_state = LPFC_HBA_ERROR;
6e7288d9 757 if (rc != MBX_BUSY || flag == MBX_POLL)
84d1b006
JS
758 mempool_free(pmb, phba->mbox_mem_pool);
759 return -EIO;
760 }
e40a02c1 761 phba->cfg_suppress_link_up = LPFC_INITIALIZE_LINK;
6e7288d9
JS
762 if (flag == MBX_POLL)
763 mempool_free(pmb, phba->mbox_mem_pool);
84d1b006
JS
764
765 return 0;
766}
767
768/**
769 * lpfc_hba_down_link - this routine downs the FC link
6e7288d9
JS
770 * @phba: pointer to lpfc hba data structure.
771 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
84d1b006
JS
772 *
773 * This routine will issue the DOWN_LINK mailbox command call.
774 * It is available to other drivers through the lpfc_hba data
775 * structure for use to stop the link.
776 *
777 * Return code
778 * 0 - success
779 * Any other value - error
780 **/
e399b228 781static int
6e7288d9 782lpfc_hba_down_link(struct lpfc_hba *phba, uint32_t flag)
84d1b006
JS
783{
784 LPFC_MBOXQ_t *pmb;
785 int rc;
786
787 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
788 if (!pmb) {
789 phba->link_state = LPFC_HBA_ERROR;
790 return -ENOMEM;
791 }
792
372c187b
DK
793 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
794 "0491 Adapter Link is disabled.\n");
84d1b006
JS
795 lpfc_down_link(phba, pmb);
796 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
6e7288d9 797 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
84d1b006 798 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
372c187b
DK
799 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
800 "2522 Adapter failed to issue DOWN_LINK"
801 " mbox command rc 0x%x\n", rc);
84d1b006
JS
802
803 mempool_free(pmb, phba->mbox_mem_pool);
804 return -EIO;
805 }
6e7288d9
JS
806 if (flag == MBX_POLL)
807 mempool_free(pmb, phba->mbox_mem_pool);
808
84d1b006
JS
809 return 0;
810}
811
e59058c4 812/**
3621a710 813 * lpfc_hba_down_prep - Perform lpfc uninitialization prior to HBA reset
e59058c4
JS
814 * @phba: pointer to lpfc HBA data structure.
815 *
816 * This routine will do LPFC uninitialization before the HBA is reset when
817 * bringing down the SLI Layer.
818 *
819 * Return codes
820 * 0 - success.
821 * Any other value - error.
822 **/
dea3101e 823int
2e0fef85 824lpfc_hba_down_prep(struct lpfc_hba *phba)
dea3101e 825{
1b32f6aa
JS
826 struct lpfc_vport **vports;
827 int i;
3772a991
JS
828
829 if (phba->sli_rev <= LPFC_SLI_REV3) {
830 /* Disable interrupts */
831 writel(0, phba->HCregaddr);
832 readl(phba->HCregaddr); /* flush */
833 }
dea3101e 834
1b32f6aa
JS
835 if (phba->pport->load_flag & FC_UNLOADING)
836 lpfc_cleanup_discovery_resources(phba->pport);
837 else {
838 vports = lpfc_create_vport_work_array(phba);
839 if (vports != NULL)
3772a991
JS
840 for (i = 0; i <= phba->max_vports &&
841 vports[i] != NULL; i++)
1b32f6aa
JS
842 lpfc_cleanup_discovery_resources(vports[i]);
843 lpfc_destroy_vport_work_array(phba, vports);
7f5f3d0d
JS
844 }
845 return 0;
dea3101e 846}
847
68e814f5
JS
848/**
849 * lpfc_sli4_free_sp_events - Cleanup sp_queue_events to free
850 * rspiocb which got deferred
851 *
852 * @phba: pointer to lpfc HBA data structure.
853 *
854 * This routine will cleanup completed slow path events after HBA is reset
855 * when bringing down the SLI Layer.
856 *
857 *
858 * Return codes
859 * void.
860 **/
861static void
862lpfc_sli4_free_sp_events(struct lpfc_hba *phba)
863{
864 struct lpfc_iocbq *rspiocbq;
865 struct hbq_dmabuf *dmabuf;
866 struct lpfc_cq_event *cq_event;
867
868 spin_lock_irq(&phba->hbalock);
869 phba->hba_flag &= ~HBA_SP_QUEUE_EVT;
870 spin_unlock_irq(&phba->hbalock);
871
872 while (!list_empty(&phba->sli4_hba.sp_queue_event)) {
873 /* Get the response iocb from the head of work queue */
874 spin_lock_irq(&phba->hbalock);
875 list_remove_head(&phba->sli4_hba.sp_queue_event,
876 cq_event, struct lpfc_cq_event, list);
877 spin_unlock_irq(&phba->hbalock);
878
879 switch (bf_get(lpfc_wcqe_c_code, &cq_event->cqe.wcqe_cmpl)) {
880 case CQE_CODE_COMPL_WQE:
881 rspiocbq = container_of(cq_event, struct lpfc_iocbq,
882 cq_event);
883 lpfc_sli_release_iocbq(phba, rspiocbq);
884 break;
885 case CQE_CODE_RECEIVE:
886 case CQE_CODE_RECEIVE_V1:
887 dmabuf = container_of(cq_event, struct hbq_dmabuf,
888 cq_event);
889 lpfc_in_buf_free(phba, &dmabuf->dbuf);
890 }
891 }
892}
893
e59058c4 894/**
bcece5f5 895 * lpfc_hba_free_post_buf - Perform lpfc uninitialization after HBA reset
e59058c4
JS
896 * @phba: pointer to lpfc HBA data structure.
897 *
bcece5f5
JS
898 * This routine will cleanup posted ELS buffers after the HBA is reset
899 * when bringing down the SLI Layer.
900 *
e59058c4
JS
901 *
902 * Return codes
bcece5f5 903 * void.
e59058c4 904 **/
bcece5f5
JS
905static void
906lpfc_hba_free_post_buf(struct lpfc_hba *phba)
41415862
JW
907{
908 struct lpfc_sli *psli = &phba->sli;
909 struct lpfc_sli_ring *pring;
910 struct lpfc_dmabuf *mp, *next_mp;
07eab624
JS
911 LIST_HEAD(buflist);
912 int count;
41415862 913
92d7f7b0
JS
914 if (phba->sli3_options & LPFC_SLI3_HBQ_ENABLED)
915 lpfc_sli_hbqbuf_free_all(phba);
916 else {
917 /* Cleanup preposted buffers on the ELS ring */
895427bd 918 pring = &psli->sli3_ring[LPFC_ELS_RING];
07eab624
JS
919 spin_lock_irq(&phba->hbalock);
920 list_splice_init(&pring->postbufq, &buflist);
921 spin_unlock_irq(&phba->hbalock);
922
923 count = 0;
924 list_for_each_entry_safe(mp, next_mp, &buflist, list) {
92d7f7b0 925 list_del(&mp->list);
07eab624 926 count++;
92d7f7b0
JS
927 lpfc_mbuf_free(phba, mp->virt, mp->phys);
928 kfree(mp);
929 }
07eab624
JS
930
931 spin_lock_irq(&phba->hbalock);
932 pring->postbufq_cnt -= count;
bcece5f5 933 spin_unlock_irq(&phba->hbalock);
41415862 934 }
bcece5f5
JS
935}
936
937/**
938 * lpfc_hba_clean_txcmplq - Perform lpfc uninitialization after HBA reset
939 * @phba: pointer to lpfc HBA data structure.
940 *
941 * This routine will cleanup the txcmplq after the HBA is reset when bringing
942 * down the SLI Layer.
943 *
944 * Return codes
945 * void
946 **/
947static void
948lpfc_hba_clean_txcmplq(struct lpfc_hba *phba)
949{
950 struct lpfc_sli *psli = &phba->sli;
895427bd 951 struct lpfc_queue *qp = NULL;
bcece5f5
JS
952 struct lpfc_sli_ring *pring;
953 LIST_HEAD(completions);
954 int i;
c1dd9111 955 struct lpfc_iocbq *piocb, *next_iocb;
bcece5f5 956
895427bd
JS
957 if (phba->sli_rev != LPFC_SLI_REV4) {
958 for (i = 0; i < psli->num_rings; i++) {
959 pring = &psli->sli3_ring[i];
bcece5f5 960 spin_lock_irq(&phba->hbalock);
895427bd
JS
961 /* At this point in time the HBA is either reset or DOA
962 * Nothing should be on txcmplq as it will
963 * NEVER complete.
964 */
965 list_splice_init(&pring->txcmplq, &completions);
966 pring->txcmplq_cnt = 0;
bcece5f5 967 spin_unlock_irq(&phba->hbalock);
09372820 968
895427bd
JS
969 lpfc_sli_abort_iocb_ring(phba, pring);
970 }
a257bf90 971 /* Cancel all the IOCBs from the completions list */
895427bd
JS
972 lpfc_sli_cancel_iocbs(phba, &completions,
973 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
974 return;
975 }
976 list_for_each_entry(qp, &phba->sli4_hba.lpfc_wq_list, wq_list) {
977 pring = qp->pring;
978 if (!pring)
979 continue;
980 spin_lock_irq(&pring->ring_lock);
c1dd9111
JS
981 list_for_each_entry_safe(piocb, next_iocb,
982 &pring->txcmplq, list)
983 piocb->iocb_flag &= ~LPFC_IO_ON_TXCMPLQ;
895427bd
JS
984 list_splice_init(&pring->txcmplq, &completions);
985 pring->txcmplq_cnt = 0;
986 spin_unlock_irq(&pring->ring_lock);
41415862
JW
987 lpfc_sli_abort_iocb_ring(phba, pring);
988 }
895427bd
JS
989 /* Cancel all the IOCBs from the completions list */
990 lpfc_sli_cancel_iocbs(phba, &completions,
991 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
bcece5f5 992}
41415862 993
bcece5f5
JS
994/**
995 * lpfc_hba_down_post_s3 - Perform lpfc uninitialization after HBA reset
bcece5f5
JS
996 * @phba: pointer to lpfc HBA data structure.
997 *
998 * This routine will do uninitialization after the HBA is reset when bring
999 * down the SLI Layer.
1000 *
1001 * Return codes
1002 * 0 - success.
1003 * Any other value - error.
1004 **/
1005static int
1006lpfc_hba_down_post_s3(struct lpfc_hba *phba)
1007{
1008 lpfc_hba_free_post_buf(phba);
1009 lpfc_hba_clean_txcmplq(phba);
41415862
JW
1010 return 0;
1011}
5af5eee7 1012
da0436e9
JS
1013/**
1014 * lpfc_hba_down_post_s4 - Perform lpfc uninitialization after HBA reset
1015 * @phba: pointer to lpfc HBA data structure.
1016 *
1017 * This routine will do uninitialization after the HBA is reset when bring
1018 * down the SLI Layer.
1019 *
1020 * Return codes
af901ca1 1021 * 0 - success.
da0436e9
JS
1022 * Any other value - error.
1023 **/
1024static int
1025lpfc_hba_down_post_s4(struct lpfc_hba *phba)
1026{
c490850a 1027 struct lpfc_io_buf *psb, *psb_next;
7cacae2a 1028 struct lpfc_async_xchg_ctx *ctxp, *ctxp_next;
5e5b511d 1029 struct lpfc_sli4_hdw_queue *qp;
da0436e9 1030 LIST_HEAD(aborts);
895427bd 1031 LIST_HEAD(nvme_aborts);
86c67379 1032 LIST_HEAD(nvmet_aborts);
0f65ff68 1033 struct lpfc_sglq *sglq_entry = NULL;
5e5b511d 1034 int cnt, idx;
0f65ff68 1035
895427bd
JS
1036
1037 lpfc_sli_hbqbuf_free_all(phba);
bcece5f5
JS
1038 lpfc_hba_clean_txcmplq(phba);
1039
da0436e9
JS
1040 /* At this point in time the HBA is either reset or DOA. Either
1041 * way, nothing should be on lpfc_abts_els_sgl_list, it needs to be
895427bd 1042 * on the lpfc_els_sgl_list so that it can either be freed if the
da0436e9
JS
1043 * driver is unloading or reposted if the driver is restarting
1044 * the port.
1045 */
895427bd 1046 spin_lock_irq(&phba->hbalock); /* required for lpfc_els_sgl_list and */
da0436e9 1047 /* scsl_buf_list */
895427bd 1048 /* sgl_list_lock required because worker thread uses this
da0436e9
JS
1049 * list.
1050 */
895427bd 1051 spin_lock(&phba->sli4_hba.sgl_list_lock);
0f65ff68
JS
1052 list_for_each_entry(sglq_entry,
1053 &phba->sli4_hba.lpfc_abts_els_sgl_list, list)
1054 sglq_entry->state = SGL_FREED;
1055
da0436e9 1056 list_splice_init(&phba->sli4_hba.lpfc_abts_els_sgl_list,
895427bd
JS
1057 &phba->sli4_hba.lpfc_els_sgl_list);
1058
f358dd0c 1059
895427bd 1060 spin_unlock(&phba->sli4_hba.sgl_list_lock);
5e5b511d
JS
1061
1062 /* abts_xxxx_buf_list_lock required because worker thread uses this
da0436e9
JS
1063 * list.
1064 */
5e5b511d
JS
1065 cnt = 0;
1066 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
1067 qp = &phba->sli4_hba.hdwq[idx];
da0436e9 1068
c00f62e6
JS
1069 spin_lock(&qp->abts_io_buf_list_lock);
1070 list_splice_init(&qp->lpfc_abts_io_buf_list,
5e5b511d 1071 &aborts);
68e814f5 1072
0794d601 1073 list_for_each_entry_safe(psb, psb_next, &aborts, list) {
86c67379
JS
1074 psb->pCmd = NULL;
1075 psb->status = IOSTAT_SUCCESS;
cf1a1d3e 1076 cnt++;
86c67379 1077 }
5e5b511d
JS
1078 spin_lock(&qp->io_buf_list_put_lock);
1079 list_splice_init(&aborts, &qp->lpfc_io_buf_list_put);
1080 qp->put_io_bufs += qp->abts_scsi_io_bufs;
c00f62e6 1081 qp->put_io_bufs += qp->abts_nvme_io_bufs;
5e5b511d 1082 qp->abts_scsi_io_bufs = 0;
c00f62e6 1083 qp->abts_nvme_io_bufs = 0;
5e5b511d 1084 spin_unlock(&qp->io_buf_list_put_lock);
c00f62e6 1085 spin_unlock(&qp->abts_io_buf_list_lock);
5e5b511d 1086 }
731eedcb 1087 spin_unlock_irq(&phba->hbalock);
86c67379 1088
5e5b511d 1089 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
731eedcb 1090 spin_lock_irq(&phba->sli4_hba.abts_nvmet_buf_list_lock);
5e5b511d
JS
1091 list_splice_init(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list,
1092 &nvmet_aborts);
731eedcb 1093 spin_unlock_irq(&phba->sli4_hba.abts_nvmet_buf_list_lock);
86c67379 1094 list_for_each_entry_safe(ctxp, ctxp_next, &nvmet_aborts, list) {
7b7f551b 1095 ctxp->flag &= ~(LPFC_NVME_XBUSY | LPFC_NVME_ABORT_OP);
6c621a22 1096 lpfc_nvmet_ctxbuf_post(phba, ctxp->ctxbuf);
86c67379 1097 }
895427bd 1098 }
895427bd 1099
68e814f5 1100 lpfc_sli4_free_sp_events(phba);
5e5b511d 1101 return cnt;
da0436e9
JS
1102}
1103
1104/**
1105 * lpfc_hba_down_post - Wrapper func for hba down post routine
1106 * @phba: pointer to lpfc HBA data structure.
1107 *
1108 * This routine wraps the actual SLI3 or SLI4 routine for performing
1109 * uninitialization after the HBA is reset when bring down the SLI Layer.
1110 *
1111 * Return codes
af901ca1 1112 * 0 - success.
da0436e9
JS
1113 * Any other value - error.
1114 **/
1115int
1116lpfc_hba_down_post(struct lpfc_hba *phba)
1117{
1118 return (*phba->lpfc_hba_down_post)(phba);
1119}
41415862 1120
e59058c4 1121/**
3621a710 1122 * lpfc_hb_timeout - The HBA-timer timeout handler
fe614acd 1123 * @t: timer context used to obtain the pointer to lpfc hba data structure.
e59058c4
JS
1124 *
1125 * This is the HBA-timer timeout handler registered to the lpfc driver. When
1126 * this timer fires, a HBA timeout event shall be posted to the lpfc driver
1127 * work-port-events bitmap and the worker thread is notified. This timeout
1128 * event will be used by the worker thread to invoke the actual timeout
1129 * handler routine, lpfc_hb_timeout_handler. Any periodical operations will
1130 * be performed in the timeout handler and the HBA timeout event bit shall
1131 * be cleared by the worker thread after it has taken the event bitmap out.
1132 **/
a6ababd2 1133static void
f22eb4d3 1134lpfc_hb_timeout(struct timer_list *t)
858c9f6c
JS
1135{
1136 struct lpfc_hba *phba;
5e9d9b82 1137 uint32_t tmo_posted;
858c9f6c
JS
1138 unsigned long iflag;
1139
f22eb4d3 1140 phba = from_timer(phba, t, hb_tmofunc);
9399627f
JS
1141
1142 /* Check for heart beat timeout conditions */
858c9f6c 1143 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
5e9d9b82
JS
1144 tmo_posted = phba->pport->work_port_events & WORKER_HB_TMO;
1145 if (!tmo_posted)
858c9f6c
JS
1146 phba->pport->work_port_events |= WORKER_HB_TMO;
1147 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
1148
9399627f 1149 /* Tell the worker thread there is work to do */
5e9d9b82
JS
1150 if (!tmo_posted)
1151 lpfc_worker_wake_up(phba);
858c9f6c
JS
1152 return;
1153}
1154
19ca7609
JS
1155/**
1156 * lpfc_rrq_timeout - The RRQ-timer timeout handler
fe614acd 1157 * @t: timer context used to obtain the pointer to lpfc hba data structure.
19ca7609
JS
1158 *
1159 * This is the RRQ-timer timeout handler registered to the lpfc driver. When
1160 * this timer fires, a RRQ timeout event shall be posted to the lpfc driver
1161 * work-port-events bitmap and the worker thread is notified. This timeout
1162 * event will be used by the worker thread to invoke the actual timeout
1163 * handler routine, lpfc_rrq_handler. Any periodical operations will
1164 * be performed in the timeout handler and the RRQ timeout event bit shall
1165 * be cleared by the worker thread after it has taken the event bitmap out.
1166 **/
1167static void
f22eb4d3 1168lpfc_rrq_timeout(struct timer_list *t)
19ca7609
JS
1169{
1170 struct lpfc_hba *phba;
19ca7609
JS
1171 unsigned long iflag;
1172
f22eb4d3 1173 phba = from_timer(phba, t, rrq_tmr);
19ca7609 1174 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
06918ac5
JS
1175 if (!(phba->pport->load_flag & FC_UNLOADING))
1176 phba->hba_flag |= HBA_RRQ_ACTIVE;
1177 else
1178 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
19ca7609 1179 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
06918ac5
JS
1180
1181 if (!(phba->pport->load_flag & FC_UNLOADING))
1182 lpfc_worker_wake_up(phba);
19ca7609
JS
1183}
1184
e59058c4 1185/**
3621a710 1186 * lpfc_hb_mbox_cmpl - The lpfc heart-beat mailbox command callback function
e59058c4
JS
1187 * @phba: pointer to lpfc hba data structure.
1188 * @pmboxq: pointer to the driver internal queue element for mailbox command.
1189 *
1190 * This is the callback function to the lpfc heart-beat mailbox command.
1191 * If configured, the lpfc driver issues the heart-beat mailbox command to
1192 * the HBA every LPFC_HB_MBOX_INTERVAL (current 5) seconds. At the time the
1193 * heart-beat mailbox command is issued, the driver shall set up heart-beat
1194 * timeout timer to LPFC_HB_MBOX_TIMEOUT (current 30) seconds and marks
1195 * heart-beat outstanding state. Once the mailbox command comes back and
1196 * no error conditions detected, the heart-beat mailbox command timer is
1197 * reset to LPFC_HB_MBOX_INTERVAL seconds and the heart-beat outstanding
1198 * state is cleared for the next heart-beat. If the timer expired with the
1199 * heart-beat outstanding state set, the driver will put the HBA offline.
1200 **/
858c9f6c
JS
1201static void
1202lpfc_hb_mbox_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
1203{
1204 unsigned long drvr_flag;
1205
1206 spin_lock_irqsave(&phba->hbalock, drvr_flag);
1207 phba->hb_outstanding = 0;
1208 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
1209
9399627f 1210 /* Check and reset heart-beat timer is necessary */
858c9f6c
JS
1211 mempool_free(pmboxq, phba->mbox_mem_pool);
1212 if (!(phba->pport->fc_flag & FC_OFFLINE_MODE) &&
1213 !(phba->link_state == LPFC_HBA_ERROR) &&
51ef4c26 1214 !(phba->pport->load_flag & FC_UNLOADING))
858c9f6c 1215 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1216 jiffies +
1217 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
1218 return;
1219}
1220
fe614acd 1221/*
317aeb83
DK
1222 * lpfc_idle_stat_delay_work - idle_stat tracking
1223 *
1224 * This routine tracks per-cq idle_stat and determines polling decisions.
1225 *
1226 * Return codes:
1227 * None
1228 **/
1229static void
1230lpfc_idle_stat_delay_work(struct work_struct *work)
1231{
1232 struct lpfc_hba *phba = container_of(to_delayed_work(work),
1233 struct lpfc_hba,
1234 idle_stat_delay_work);
1235 struct lpfc_queue *cq;
1236 struct lpfc_sli4_hdw_queue *hdwq;
1237 struct lpfc_idle_stat *idle_stat;
1238 u32 i, idle_percent;
1239 u64 wall, wall_idle, diff_wall, diff_idle, busy_time;
1240
1241 if (phba->pport->load_flag & FC_UNLOADING)
1242 return;
1243
1244 if (phba->link_state == LPFC_HBA_ERROR ||
1245 phba->pport->fc_flag & FC_OFFLINE_MODE)
1246 goto requeue;
1247
1248 for_each_present_cpu(i) {
1249 hdwq = &phba->sli4_hba.hdwq[phba->sli4_hba.cpu_map[i].hdwq];
1250 cq = hdwq->io_cq;
1251
1252 /* Skip if we've already handled this cq's primary CPU */
1253 if (cq->chann != i)
1254 continue;
1255
1256 idle_stat = &phba->sli4_hba.idle_stat[i];
1257
1258 /* get_cpu_idle_time returns values as running counters. Thus,
1259 * to know the amount for this period, the prior counter values
1260 * need to be subtracted from the current counter values.
1261 * From there, the idle time stat can be calculated as a
1262 * percentage of 100 - the sum of the other consumption times.
1263 */
1264 wall_idle = get_cpu_idle_time(i, &wall, 1);
1265 diff_idle = wall_idle - idle_stat->prev_idle;
1266 diff_wall = wall - idle_stat->prev_wall;
1267
1268 if (diff_wall <= diff_idle)
1269 busy_time = 0;
1270 else
1271 busy_time = diff_wall - diff_idle;
1272
1273 idle_percent = div64_u64(100 * busy_time, diff_wall);
1274 idle_percent = 100 - idle_percent;
1275
1276 if (idle_percent < 15)
1277 cq->poll_mode = LPFC_QUEUE_WORK;
1278 else
1279 cq->poll_mode = LPFC_IRQ_POLL;
1280
1281 idle_stat->prev_idle = wall_idle;
1282 idle_stat->prev_wall = wall;
1283 }
1284
1285requeue:
1286 schedule_delayed_work(&phba->idle_stat_delay_work,
1287 msecs_to_jiffies(LPFC_IDLE_STAT_DELAY));
1288}
1289
32517fc0
JS
1290static void
1291lpfc_hb_eq_delay_work(struct work_struct *work)
1292{
1293 struct lpfc_hba *phba = container_of(to_delayed_work(work),
1294 struct lpfc_hba, eq_delay_work);
1295 struct lpfc_eq_intr_info *eqi, *eqi_new;
1296 struct lpfc_queue *eq, *eq_next;
8156d378 1297 unsigned char *ena_delay = NULL;
32517fc0
JS
1298 uint32_t usdelay;
1299 int i;
1300
1301 if (!phba->cfg_auto_imax || phba->pport->load_flag & FC_UNLOADING)
1302 return;
1303
1304 if (phba->link_state == LPFC_HBA_ERROR ||
1305 phba->pport->fc_flag & FC_OFFLINE_MODE)
1306 goto requeue;
1307
8156d378
JS
1308 ena_delay = kcalloc(phba->sli4_hba.num_possible_cpu, sizeof(*ena_delay),
1309 GFP_KERNEL);
1310 if (!ena_delay)
32517fc0
JS
1311 goto requeue;
1312
8156d378
JS
1313 for (i = 0; i < phba->cfg_irq_chann; i++) {
1314 /* Get the EQ corresponding to the IRQ vector */
1315 eq = phba->sli4_hba.hba_eq_hdl[i].eq;
1316 if (!eq)
1317 continue;
1318 if (eq->q_mode || eq->q_flag & HBA_EQ_DELAY_CHK) {
1319 eq->q_flag &= ~HBA_EQ_DELAY_CHK;
1320 ena_delay[eq->last_cpu] = 1;
8d34a59c 1321 }
8156d378 1322 }
32517fc0
JS
1323
1324 for_each_present_cpu(i) {
32517fc0 1325 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, i);
8156d378
JS
1326 if (ena_delay[i]) {
1327 usdelay = (eqi->icnt >> 10) * LPFC_EQ_DELAY_STEP;
1328 if (usdelay > LPFC_MAX_AUTO_EQ_DELAY)
1329 usdelay = LPFC_MAX_AUTO_EQ_DELAY;
1330 } else {
1331 usdelay = 0;
8d34a59c 1332 }
32517fc0 1333
32517fc0
JS
1334 eqi->icnt = 0;
1335
1336 list_for_each_entry_safe(eq, eq_next, &eqi->list, cpu_list) {
8156d378 1337 if (unlikely(eq->last_cpu != i)) {
32517fc0
JS
1338 eqi_new = per_cpu_ptr(phba->sli4_hba.eq_info,
1339 eq->last_cpu);
1340 list_move_tail(&eq->cpu_list, &eqi_new->list);
1341 continue;
1342 }
1343 if (usdelay != eq->q_mode)
1344 lpfc_modify_hba_eq_delay(phba, eq->hdwq, 1,
1345 usdelay);
1346 }
1347 }
1348
8156d378 1349 kfree(ena_delay);
32517fc0
JS
1350
1351requeue:
1352 queue_delayed_work(phba->wq, &phba->eq_delay_work,
1353 msecs_to_jiffies(LPFC_EQ_DELAY_MSECS));
1354}
1355
c490850a
JS
1356/**
1357 * lpfc_hb_mxp_handler - Multi-XRI pools handler to adjust XRI distribution
1358 * @phba: pointer to lpfc hba data structure.
1359 *
1360 * For each heartbeat, this routine does some heuristic methods to adjust
1361 * XRI distribution. The goal is to fully utilize free XRIs.
1362 **/
1363static void lpfc_hb_mxp_handler(struct lpfc_hba *phba)
1364{
1365 u32 i;
1366 u32 hwq_count;
1367
1368 hwq_count = phba->cfg_hdw_queue;
1369 for (i = 0; i < hwq_count; i++) {
1370 /* Adjust XRIs in private pool */
1371 lpfc_adjust_pvt_pool_count(phba, i);
1372
1373 /* Adjust high watermark */
1374 lpfc_adjust_high_watermark(phba, i);
1375
1376#ifdef LPFC_MXP_STAT
1377 /* Snapshot pbl, pvt and busy count */
1378 lpfc_snapshot_mxp(phba, i);
1379#endif
1380 }
1381}
1382
e59058c4 1383/**
3621a710 1384 * lpfc_hb_timeout_handler - The HBA-timer timeout handler
e59058c4
JS
1385 * @phba: pointer to lpfc hba data structure.
1386 *
1387 * This is the actual HBA-timer timeout handler to be invoked by the worker
1388 * thread whenever the HBA timer fired and HBA-timeout event posted. This
1389 * handler performs any periodic operations needed for the device. If such
1390 * periodic event has already been attended to either in the interrupt handler
1391 * or by processing slow-ring or fast-ring events within the HBA-timer
1392 * timeout window (LPFC_HB_MBOX_INTERVAL), this handler just simply resets
1393 * the timer for the next timeout period. If lpfc heart-beat mailbox command
1394 * is configured and there is no heart-beat mailbox command outstanding, a
1395 * heart-beat mailbox is issued and timer set properly. Otherwise, if there
1396 * has been a heart-beat mailbox command outstanding, the HBA shall be put
1397 * to offline.
1398 **/
858c9f6c
JS
1399void
1400lpfc_hb_timeout_handler(struct lpfc_hba *phba)
1401{
45ed1190 1402 struct lpfc_vport **vports;
858c9f6c 1403 LPFC_MBOXQ_t *pmboxq;
0ff10d46 1404 struct lpfc_dmabuf *buf_ptr;
45ed1190 1405 int retval, i;
858c9f6c 1406 struct lpfc_sli *psli = &phba->sli;
0ff10d46 1407 LIST_HEAD(completions);
858c9f6c 1408
c490850a
JS
1409 if (phba->cfg_xri_rebalancing) {
1410 /* Multi-XRI pools handler */
1411 lpfc_hb_mxp_handler(phba);
1412 }
858c9f6c 1413
45ed1190
JS
1414 vports = lpfc_create_vport_work_array(phba);
1415 if (vports != NULL)
4258e98e 1416 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
45ed1190 1417 lpfc_rcv_seq_check_edtov(vports[i]);
e3ba04c9 1418 lpfc_fdmi_change_check(vports[i]);
4258e98e 1419 }
45ed1190
JS
1420 lpfc_destroy_vport_work_array(phba, vports);
1421
858c9f6c 1422 if ((phba->link_state == LPFC_HBA_ERROR) ||
51ef4c26 1423 (phba->pport->load_flag & FC_UNLOADING) ||
858c9f6c
JS
1424 (phba->pport->fc_flag & FC_OFFLINE_MODE))
1425 return;
1426
1427 spin_lock_irq(&phba->pport->work_port_lock);
858c9f6c 1428
256ec0d0
JS
1429 if (time_after(phba->last_completion_time +
1430 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL),
1431 jiffies)) {
858c9f6c
JS
1432 spin_unlock_irq(&phba->pport->work_port_lock);
1433 if (!phba->hb_outstanding)
1434 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1435 jiffies +
1436 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
1437 else
1438 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1439 jiffies +
1440 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
858c9f6c
JS
1441 return;
1442 }
1443 spin_unlock_irq(&phba->pport->work_port_lock);
1444
0ff10d46
JS
1445 if (phba->elsbuf_cnt &&
1446 (phba->elsbuf_cnt == phba->elsbuf_prev_cnt)) {
1447 spin_lock_irq(&phba->hbalock);
1448 list_splice_init(&phba->elsbuf, &completions);
1449 phba->elsbuf_cnt = 0;
1450 phba->elsbuf_prev_cnt = 0;
1451 spin_unlock_irq(&phba->hbalock);
1452
1453 while (!list_empty(&completions)) {
1454 list_remove_head(&completions, buf_ptr,
1455 struct lpfc_dmabuf, list);
1456 lpfc_mbuf_free(phba, buf_ptr->virt, buf_ptr->phys);
1457 kfree(buf_ptr);
1458 }
1459 }
1460 phba->elsbuf_prev_cnt = phba->elsbuf_cnt;
1461
858c9f6c 1462 /* If there is no heart beat outstanding, issue a heartbeat command */
13815c83
JS
1463 if (phba->cfg_enable_hba_heartbeat) {
1464 if (!phba->hb_outstanding) {
bc73905a
JS
1465 if ((!(psli->sli_flag & LPFC_SLI_MBOX_ACTIVE)) &&
1466 (list_empty(&psli->mboxq))) {
1467 pmboxq = mempool_alloc(phba->mbox_mem_pool,
1468 GFP_KERNEL);
1469 if (!pmboxq) {
1470 mod_timer(&phba->hb_tmofunc,
1471 jiffies +
256ec0d0
JS
1472 msecs_to_jiffies(1000 *
1473 LPFC_HB_MBOX_INTERVAL));
bc73905a
JS
1474 return;
1475 }
1476
1477 lpfc_heart_beat(phba, pmboxq);
1478 pmboxq->mbox_cmpl = lpfc_hb_mbox_cmpl;
1479 pmboxq->vport = phba->pport;
1480 retval = lpfc_sli_issue_mbox(phba, pmboxq,
1481 MBX_NOWAIT);
1482
1483 if (retval != MBX_BUSY &&
1484 retval != MBX_SUCCESS) {
1485 mempool_free(pmboxq,
1486 phba->mbox_mem_pool);
1487 mod_timer(&phba->hb_tmofunc,
1488 jiffies +
256ec0d0
JS
1489 msecs_to_jiffies(1000 *
1490 LPFC_HB_MBOX_INTERVAL));
bc73905a
JS
1491 return;
1492 }
1493 phba->skipped_hb = 0;
1494 phba->hb_outstanding = 1;
1495 } else if (time_before_eq(phba->last_completion_time,
1496 phba->skipped_hb)) {
1497 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
1498 "2857 Last completion time not "
1499 " updated in %d ms\n",
1500 jiffies_to_msecs(jiffies
1501 - phba->last_completion_time));
1502 } else
1503 phba->skipped_hb = jiffies;
1504
858c9f6c 1505 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1506 jiffies +
1507 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
858c9f6c 1508 return;
13815c83
JS
1509 } else {
1510 /*
1511 * If heart beat timeout called with hb_outstanding set
dcf2a4e0
JS
1512 * we need to give the hb mailbox cmd a chance to
1513 * complete or TMO.
13815c83 1514 */
dcf2a4e0
JS
1515 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1516 "0459 Adapter heartbeat still out"
1517 "standing:last compl time was %d ms.\n",
1518 jiffies_to_msecs(jiffies
1519 - phba->last_completion_time));
1520 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1521 jiffies +
1522 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
858c9f6c 1523 }
4258e98e
JS
1524 } else {
1525 mod_timer(&phba->hb_tmofunc,
1526 jiffies +
1527 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
1528 }
1529}
1530
e59058c4 1531/**
3621a710 1532 * lpfc_offline_eratt - Bring lpfc offline on hardware error attention
e59058c4
JS
1533 * @phba: pointer to lpfc hba data structure.
1534 *
1535 * This routine is called to bring the HBA offline when HBA hardware error
1536 * other than Port Error 6 has been detected.
1537 **/
09372820
JS
1538static void
1539lpfc_offline_eratt(struct lpfc_hba *phba)
1540{
1541 struct lpfc_sli *psli = &phba->sli;
1542
1543 spin_lock_irq(&phba->hbalock);
f4b4c68f 1544 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
09372820 1545 spin_unlock_irq(&phba->hbalock);
618a5230 1546 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
09372820
JS
1547
1548 lpfc_offline(phba);
1549 lpfc_reset_barrier(phba);
f4b4c68f 1550 spin_lock_irq(&phba->hbalock);
09372820 1551 lpfc_sli_brdreset(phba);
f4b4c68f 1552 spin_unlock_irq(&phba->hbalock);
09372820
JS
1553 lpfc_hba_down_post(phba);
1554 lpfc_sli_brdready(phba, HS_MBRDY);
1555 lpfc_unblock_mgmt_io(phba);
1556 phba->link_state = LPFC_HBA_ERROR;
1557 return;
1558}
1559
da0436e9
JS
1560/**
1561 * lpfc_sli4_offline_eratt - Bring lpfc offline on SLI4 hardware error attention
1562 * @phba: pointer to lpfc hba data structure.
1563 *
1564 * This routine is called to bring a SLI4 HBA offline when HBA hardware error
1565 * other than Port Error 6 has been detected.
1566 **/
a88dbb6a 1567void
da0436e9
JS
1568lpfc_sli4_offline_eratt(struct lpfc_hba *phba)
1569{
946727dc
JS
1570 spin_lock_irq(&phba->hbalock);
1571 phba->link_state = LPFC_HBA_ERROR;
1572 spin_unlock_irq(&phba->hbalock);
1573
618a5230 1574 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
c00f62e6 1575 lpfc_sli_flush_io_rings(phba);
da0436e9 1576 lpfc_offline(phba);
da0436e9 1577 lpfc_hba_down_post(phba);
da0436e9 1578 lpfc_unblock_mgmt_io(phba);
da0436e9
JS
1579}
1580
a257bf90
JS
1581/**
1582 * lpfc_handle_deferred_eratt - The HBA hardware deferred error handler
1583 * @phba: pointer to lpfc hba data structure.
1584 *
1585 * This routine is invoked to handle the deferred HBA hardware error
1586 * conditions. This type of error is indicated by HBA by setting ER1
1587 * and another ER bit in the host status register. The driver will
1588 * wait until the ER1 bit clears before handling the error condition.
1589 **/
1590static void
1591lpfc_handle_deferred_eratt(struct lpfc_hba *phba)
1592{
1593 uint32_t old_host_status = phba->work_hs;
a257bf90
JS
1594 struct lpfc_sli *psli = &phba->sli;
1595
f4b4c68f
JS
1596 /* If the pci channel is offline, ignore possible errors,
1597 * since we cannot communicate with the pci card anyway.
1598 */
1599 if (pci_channel_offline(phba->pcidev)) {
1600 spin_lock_irq(&phba->hbalock);
1601 phba->hba_flag &= ~DEFER_ERATT;
1602 spin_unlock_irq(&phba->hbalock);
1603 return;
1604 }
1605
372c187b
DK
1606 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1607 "0479 Deferred Adapter Hardware Error "
1608 "Data: x%x x%x x%x\n",
1609 phba->work_hs, phba->work_status[0],
1610 phba->work_status[1]);
a257bf90
JS
1611
1612 spin_lock_irq(&phba->hbalock);
f4b4c68f 1613 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
a257bf90
JS
1614 spin_unlock_irq(&phba->hbalock);
1615
1616
1617 /*
1618 * Firmware stops when it triggred erratt. That could cause the I/Os
1619 * dropped by the firmware. Error iocb (I/O) on txcmplq and let the
1620 * SCSI layer retry it after re-establishing link.
1621 */
db55fba8 1622 lpfc_sli_abort_fcp_rings(phba);
a257bf90
JS
1623
1624 /*
1625 * There was a firmware error. Take the hba offline and then
1626 * attempt to restart it.
1627 */
618a5230 1628 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
a257bf90
JS
1629 lpfc_offline(phba);
1630
1631 /* Wait for the ER1 bit to clear.*/
1632 while (phba->work_hs & HS_FFER1) {
1633 msleep(100);
9940b97b
JS
1634 if (lpfc_readl(phba->HSregaddr, &phba->work_hs)) {
1635 phba->work_hs = UNPLUG_ERR ;
1636 break;
1637 }
a257bf90
JS
1638 /* If driver is unloading let the worker thread continue */
1639 if (phba->pport->load_flag & FC_UNLOADING) {
1640 phba->work_hs = 0;
1641 break;
1642 }
1643 }
1644
1645 /*
1646 * This is to ptrotect against a race condition in which
1647 * first write to the host attention register clear the
1648 * host status register.
1649 */
1650 if ((!phba->work_hs) && (!(phba->pport->load_flag & FC_UNLOADING)))
1651 phba->work_hs = old_host_status & ~HS_FFER1;
1652
3772a991 1653 spin_lock_irq(&phba->hbalock);
a257bf90 1654 phba->hba_flag &= ~DEFER_ERATT;
3772a991 1655 spin_unlock_irq(&phba->hbalock);
a257bf90
JS
1656 phba->work_status[0] = readl(phba->MBslimaddr + 0xa8);
1657 phba->work_status[1] = readl(phba->MBslimaddr + 0xac);
1658}
1659
3772a991
JS
1660static void
1661lpfc_board_errevt_to_mgmt(struct lpfc_hba *phba)
1662{
1663 struct lpfc_board_event_header board_event;
1664 struct Scsi_Host *shost;
1665
1666 board_event.event_type = FC_REG_BOARD_EVENT;
1667 board_event.subcategory = LPFC_EVENT_PORTINTERR;
1668 shost = lpfc_shost_from_vport(phba->pport);
1669 fc_host_post_vendor_event(shost, fc_get_event_number(),
1670 sizeof(board_event),
1671 (char *) &board_event,
1672 LPFC_NL_VENDOR_ID);
1673}
1674
e59058c4 1675/**
3772a991 1676 * lpfc_handle_eratt_s3 - The SLI3 HBA hardware error handler
e59058c4
JS
1677 * @phba: pointer to lpfc hba data structure.
1678 *
1679 * This routine is invoked to handle the following HBA hardware error
1680 * conditions:
1681 * 1 - HBA error attention interrupt
1682 * 2 - DMA ring index out of range
1683 * 3 - Mailbox command came back as unknown
1684 **/
3772a991
JS
1685static void
1686lpfc_handle_eratt_s3(struct lpfc_hba *phba)
dea3101e 1687{
2e0fef85 1688 struct lpfc_vport *vport = phba->pport;
2e0fef85 1689 struct lpfc_sli *psli = &phba->sli;
d2873e4c 1690 uint32_t event_data;
57127f15
JS
1691 unsigned long temperature;
1692 struct temp_event temp_event_data;
92d7f7b0 1693 struct Scsi_Host *shost;
2e0fef85 1694
8d63f375 1695 /* If the pci channel is offline, ignore possible errors,
3772a991
JS
1696 * since we cannot communicate with the pci card anyway.
1697 */
1698 if (pci_channel_offline(phba->pcidev)) {
1699 spin_lock_irq(&phba->hbalock);
1700 phba->hba_flag &= ~DEFER_ERATT;
1701 spin_unlock_irq(&phba->hbalock);
8d63f375 1702 return;
3772a991
JS
1703 }
1704
13815c83
JS
1705 /* If resets are disabled then leave the HBA alone and return */
1706 if (!phba->cfg_enable_hba_reset)
1707 return;
dea3101e 1708
ea2151b4 1709 /* Send an internal error event to mgmt application */
3772a991 1710 lpfc_board_errevt_to_mgmt(phba);
ea2151b4 1711
a257bf90
JS
1712 if (phba->hba_flag & DEFER_ERATT)
1713 lpfc_handle_deferred_eratt(phba);
1714
dcf2a4e0
JS
1715 if ((phba->work_hs & HS_FFER6) || (phba->work_hs & HS_FFER8)) {
1716 if (phba->work_hs & HS_FFER6)
1717 /* Re-establishing Link */
1718 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1719 "1301 Re-establishing Link "
1720 "Data: x%x x%x x%x\n",
1721 phba->work_hs, phba->work_status[0],
1722 phba->work_status[1]);
1723 if (phba->work_hs & HS_FFER8)
1724 /* Device Zeroization */
1725 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1726 "2861 Host Authentication device "
1727 "zeroization Data:x%x x%x x%x\n",
1728 phba->work_hs, phba->work_status[0],
1729 phba->work_status[1]);
58da1ffb 1730
92d7f7b0 1731 spin_lock_irq(&phba->hbalock);
f4b4c68f 1732 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
92d7f7b0 1733 spin_unlock_irq(&phba->hbalock);
dea3101e 1734
1735 /*
1736 * Firmware stops when it triggled erratt with HS_FFER6.
1737 * That could cause the I/Os dropped by the firmware.
1738 * Error iocb (I/O) on txcmplq and let the SCSI layer
1739 * retry it after re-establishing link.
1740 */
db55fba8 1741 lpfc_sli_abort_fcp_rings(phba);
dea3101e 1742
dea3101e 1743 /*
1744 * There was a firmware error. Take the hba offline and then
1745 * attempt to restart it.
1746 */
618a5230 1747 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
dea3101e 1748 lpfc_offline(phba);
41415862 1749 lpfc_sli_brdrestart(phba);
dea3101e 1750 if (lpfc_online(phba) == 0) { /* Initialize the HBA */
46fa311e 1751 lpfc_unblock_mgmt_io(phba);
dea3101e 1752 return;
1753 }
46fa311e 1754 lpfc_unblock_mgmt_io(phba);
57127f15
JS
1755 } else if (phba->work_hs & HS_CRIT_TEMP) {
1756 temperature = readl(phba->MBslimaddr + TEMPERATURE_OFFSET);
1757 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1758 temp_event_data.event_code = LPFC_CRIT_TEMP;
1759 temp_event_data.data = (uint32_t)temperature;
1760
372c187b 1761 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
d7c255b2 1762 "0406 Adapter maximum temperature exceeded "
57127f15
JS
1763 "(%ld), taking this port offline "
1764 "Data: x%x x%x x%x\n",
1765 temperature, phba->work_hs,
1766 phba->work_status[0], phba->work_status[1]);
1767
1768 shost = lpfc_shost_from_vport(phba->pport);
1769 fc_host_post_vendor_event(shost, fc_get_event_number(),
1770 sizeof(temp_event_data),
1771 (char *) &temp_event_data,
1772 SCSI_NL_VID_TYPE_PCI
1773 | PCI_VENDOR_ID_EMULEX);
1774
7af67051 1775 spin_lock_irq(&phba->hbalock);
7af67051
JS
1776 phba->over_temp_state = HBA_OVER_TEMP;
1777 spin_unlock_irq(&phba->hbalock);
09372820 1778 lpfc_offline_eratt(phba);
57127f15 1779
dea3101e 1780 } else {
1781 /* The if clause above forces this code path when the status
9399627f
JS
1782 * failure is a value other than FFER6. Do not call the offline
1783 * twice. This is the adapter hardware error path.
dea3101e 1784 */
372c187b 1785 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 1786 "0457 Adapter Hardware Error "
dea3101e 1787 "Data: x%x x%x x%x\n",
e8b62011 1788 phba->work_hs,
dea3101e 1789 phba->work_status[0], phba->work_status[1]);
1790
d2873e4c 1791 event_data = FC_REG_DUMP_EVENT;
92d7f7b0 1792 shost = lpfc_shost_from_vport(vport);
2e0fef85 1793 fc_host_post_vendor_event(shost, fc_get_event_number(),
d2873e4c
JS
1794 sizeof(event_data), (char *) &event_data,
1795 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
1796
09372820 1797 lpfc_offline_eratt(phba);
dea3101e 1798 }
9399627f 1799 return;
dea3101e 1800}
1801
618a5230
JS
1802/**
1803 * lpfc_sli4_port_sta_fn_reset - The SLI4 function reset due to port status reg
1804 * @phba: pointer to lpfc hba data structure.
1805 * @mbx_action: flag for mailbox shutdown action.
fe614acd 1806 * @en_rn_msg: send reset/port recovery message.
618a5230
JS
1807 * This routine is invoked to perform an SLI4 port PCI function reset in
1808 * response to port status register polling attention. It waits for port
1809 * status register (ERR, RDY, RN) bits before proceeding with function reset.
1810 * During this process, interrupt vectors are freed and later requested
1811 * for handling possible port resource change.
1812 **/
1813static int
e10b2022
JS
1814lpfc_sli4_port_sta_fn_reset(struct lpfc_hba *phba, int mbx_action,
1815 bool en_rn_msg)
618a5230
JS
1816{
1817 int rc;
1818 uint32_t intr_mode;
1819
27d6ac0a 1820 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) >=
65791f1f
JS
1821 LPFC_SLI_INTF_IF_TYPE_2) {
1822 /*
1823 * On error status condition, driver need to wait for port
1824 * ready before performing reset.
1825 */
1826 rc = lpfc_sli4_pdev_status_reg_wait(phba);
0e916ee7 1827 if (rc)
65791f1f
JS
1828 return rc;
1829 }
0e916ee7 1830
65791f1f
JS
1831 /* need reset: attempt for port recovery */
1832 if (en_rn_msg)
372c187b 1833 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
1834 "2887 Reset Needed: Attempting Port "
1835 "Recovery...\n");
1836 lpfc_offline_prep(phba, mbx_action);
c00f62e6 1837 lpfc_sli_flush_io_rings(phba);
65791f1f
JS
1838 lpfc_offline(phba);
1839 /* release interrupt for possible resource change */
1840 lpfc_sli4_disable_intr(phba);
5a9eeff5
JS
1841 rc = lpfc_sli_brdrestart(phba);
1842 if (rc) {
372c187b 1843 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5a9eeff5
JS
1844 "6309 Failed to restart board\n");
1845 return rc;
1846 }
65791f1f
JS
1847 /* request and enable interrupt */
1848 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
1849 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 1850 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
1851 "3175 Failed to enable interrupt\n");
1852 return -EIO;
618a5230 1853 }
65791f1f
JS
1854 phba->intr_mode = intr_mode;
1855 rc = lpfc_online(phba);
1856 if (rc == 0)
1857 lpfc_unblock_mgmt_io(phba);
1858
618a5230
JS
1859 return rc;
1860}
1861
da0436e9
JS
1862/**
1863 * lpfc_handle_eratt_s4 - The SLI4 HBA hardware error handler
1864 * @phba: pointer to lpfc hba data structure.
1865 *
1866 * This routine is invoked to handle the SLI4 HBA hardware error attention
1867 * conditions.
1868 **/
1869static void
1870lpfc_handle_eratt_s4(struct lpfc_hba *phba)
1871{
1872 struct lpfc_vport *vport = phba->pport;
1873 uint32_t event_data;
1874 struct Scsi_Host *shost;
2fcee4bf 1875 uint32_t if_type;
2e90f4b5
JS
1876 struct lpfc_register portstat_reg = {0};
1877 uint32_t reg_err1, reg_err2;
1878 uint32_t uerrlo_reg, uemasklo_reg;
65791f1f 1879 uint32_t smphr_port_status = 0, pci_rd_rc1, pci_rd_rc2;
e10b2022 1880 bool en_rn_msg = true;
946727dc 1881 struct temp_event temp_event_data;
65791f1f
JS
1882 struct lpfc_register portsmphr_reg;
1883 int rc, i;
da0436e9
JS
1884
1885 /* If the pci channel is offline, ignore possible errors, since
1886 * we cannot communicate with the pci card anyway.
1887 */
32a93100 1888 if (pci_channel_offline(phba->pcidev)) {
372c187b 1889 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
32a93100
JS
1890 "3166 pci channel is offline\n");
1891 lpfc_sli4_offline_eratt(phba);
da0436e9 1892 return;
32a93100 1893 }
da0436e9 1894
65791f1f 1895 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
2fcee4bf
JS
1896 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
1897 switch (if_type) {
1898 case LPFC_SLI_INTF_IF_TYPE_0:
2e90f4b5
JS
1899 pci_rd_rc1 = lpfc_readl(
1900 phba->sli4_hba.u.if_type0.UERRLOregaddr,
1901 &uerrlo_reg);
1902 pci_rd_rc2 = lpfc_readl(
1903 phba->sli4_hba.u.if_type0.UEMASKLOregaddr,
1904 &uemasklo_reg);
1905 /* consider PCI bus read error as pci_channel_offline */
1906 if (pci_rd_rc1 == -EIO && pci_rd_rc2 == -EIO)
1907 return;
65791f1f
JS
1908 if (!(phba->hba_flag & HBA_RECOVERABLE_UE)) {
1909 lpfc_sli4_offline_eratt(phba);
1910 return;
1911 }
372c187b 1912 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
1913 "7623 Checking UE recoverable");
1914
1915 for (i = 0; i < phba->sli4_hba.ue_to_sr / 1000; i++) {
1916 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
1917 &portsmphr_reg.word0))
1918 continue;
1919
1920 smphr_port_status = bf_get(lpfc_port_smphr_port_status,
1921 &portsmphr_reg);
1922 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
1923 LPFC_PORT_SEM_UE_RECOVERABLE)
1924 break;
1925 /*Sleep for 1Sec, before checking SEMAPHORE */
1926 msleep(1000);
1927 }
1928
372c187b 1929 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
1930 "4827 smphr_port_status x%x : Waited %dSec",
1931 smphr_port_status, i);
1932
1933 /* Recoverable UE, reset the HBA device */
1934 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
1935 LPFC_PORT_SEM_UE_RECOVERABLE) {
1936 for (i = 0; i < 20; i++) {
1937 msleep(1000);
1938 if (!lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
1939 &portsmphr_reg.word0) &&
1940 (LPFC_POST_STAGE_PORT_READY ==
1941 bf_get(lpfc_port_smphr_port_status,
1942 &portsmphr_reg))) {
1943 rc = lpfc_sli4_port_sta_fn_reset(phba,
1944 LPFC_MBX_NO_WAIT, en_rn_msg);
1945 if (rc == 0)
1946 return;
372c187b
DK
1947 lpfc_printf_log(phba, KERN_ERR,
1948 LOG_TRACE_EVENT,
65791f1f
JS
1949 "4215 Failed to recover UE");
1950 break;
1951 }
1952 }
1953 }
372c187b 1954 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
1955 "7624 Firmware not ready: Failing UE recovery,"
1956 " waited %dSec", i);
8c24a4f6 1957 phba->link_state = LPFC_HBA_ERROR;
2fcee4bf 1958 break;
946727dc 1959
2fcee4bf 1960 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 1961 case LPFC_SLI_INTF_IF_TYPE_6:
2e90f4b5
JS
1962 pci_rd_rc1 = lpfc_readl(
1963 phba->sli4_hba.u.if_type2.STATUSregaddr,
1964 &portstat_reg.word0);
1965 /* consider PCI bus read error as pci_channel_offline */
6b5151fd 1966 if (pci_rd_rc1 == -EIO) {
372c187b 1967 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
6b5151fd
JS
1968 "3151 PCI bus read access failure: x%x\n",
1969 readl(phba->sli4_hba.u.if_type2.STATUSregaddr));
32a93100 1970 lpfc_sli4_offline_eratt(phba);
2e90f4b5 1971 return;
6b5151fd 1972 }
2e90f4b5
JS
1973 reg_err1 = readl(phba->sli4_hba.u.if_type2.ERR1regaddr);
1974 reg_err2 = readl(phba->sli4_hba.u.if_type2.ERR2regaddr);
2fcee4bf 1975 if (bf_get(lpfc_sliport_status_oti, &portstat_reg)) {
372c187b
DK
1976 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1977 "2889 Port Overtemperature event, "
1978 "taking port offline Data: x%x x%x\n",
1979 reg_err1, reg_err2);
946727dc 1980
310429ef 1981 phba->sfp_alarm |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
946727dc
JS
1982 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1983 temp_event_data.event_code = LPFC_CRIT_TEMP;
1984 temp_event_data.data = 0xFFFFFFFF;
1985
1986 shost = lpfc_shost_from_vport(phba->pport);
1987 fc_host_post_vendor_event(shost, fc_get_event_number(),
1988 sizeof(temp_event_data),
1989 (char *)&temp_event_data,
1990 SCSI_NL_VID_TYPE_PCI
1991 | PCI_VENDOR_ID_EMULEX);
1992
2fcee4bf
JS
1993 spin_lock_irq(&phba->hbalock);
1994 phba->over_temp_state = HBA_OVER_TEMP;
1995 spin_unlock_irq(&phba->hbalock);
1996 lpfc_sli4_offline_eratt(phba);
946727dc 1997 return;
2fcee4bf 1998 }
2e90f4b5 1999 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
e10b2022 2000 reg_err2 == SLIPORT_ERR2_REG_FW_RESTART) {
372c187b 2001 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e10b2022
JS
2002 "3143 Port Down: Firmware Update "
2003 "Detected\n");
2004 en_rn_msg = false;
2005 } else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
2e90f4b5 2006 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
372c187b 2007 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2e90f4b5
JS
2008 "3144 Port Down: Debug Dump\n");
2009 else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
2010 reg_err2 == SLIPORT_ERR2_REG_FUNC_PROVISON)
372c187b 2011 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2e90f4b5 2012 "3145 Port Down: Provisioning\n");
618a5230 2013
946727dc
JS
2014 /* If resets are disabled then leave the HBA alone and return */
2015 if (!phba->cfg_enable_hba_reset)
2016 return;
2017
618a5230 2018 /* Check port status register for function reset */
e10b2022
JS
2019 rc = lpfc_sli4_port_sta_fn_reset(phba, LPFC_MBX_NO_WAIT,
2020 en_rn_msg);
618a5230
JS
2021 if (rc == 0) {
2022 /* don't report event on forced debug dump */
2023 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
2024 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
2025 return;
2026 else
2027 break;
2fcee4bf 2028 }
618a5230 2029 /* fall through for not able to recover */
372c187b 2030 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
8c24a4f6
JS
2031 "3152 Unrecoverable error\n");
2032 phba->link_state = LPFC_HBA_ERROR;
2fcee4bf
JS
2033 break;
2034 case LPFC_SLI_INTF_IF_TYPE_1:
2035 default:
2036 break;
2037 }
2e90f4b5
JS
2038 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
2039 "3123 Report dump event to upper layer\n");
2040 /* Send an internal error event to mgmt application */
2041 lpfc_board_errevt_to_mgmt(phba);
2042
2043 event_data = FC_REG_DUMP_EVENT;
2044 shost = lpfc_shost_from_vport(vport);
2045 fc_host_post_vendor_event(shost, fc_get_event_number(),
2046 sizeof(event_data), (char *) &event_data,
2047 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
da0436e9
JS
2048}
2049
2050/**
2051 * lpfc_handle_eratt - Wrapper func for handling hba error attention
2052 * @phba: pointer to lpfc HBA data structure.
2053 *
2054 * This routine wraps the actual SLI3 or SLI4 hba error attention handling
2055 * routine from the API jump table function pointer from the lpfc_hba struct.
2056 *
2057 * Return codes
af901ca1 2058 * 0 - success.
da0436e9
JS
2059 * Any other value - error.
2060 **/
2061void
2062lpfc_handle_eratt(struct lpfc_hba *phba)
2063{
2064 (*phba->lpfc_handle_eratt)(phba);
2065}
2066
e59058c4 2067/**
3621a710 2068 * lpfc_handle_latt - The HBA link event handler
e59058c4
JS
2069 * @phba: pointer to lpfc hba data structure.
2070 *
2071 * This routine is invoked from the worker thread to handle a HBA host
895427bd 2072 * attention link event. SLI3 only.
e59058c4 2073 **/
dea3101e 2074void
2e0fef85 2075lpfc_handle_latt(struct lpfc_hba *phba)
dea3101e 2076{
2e0fef85
JS
2077 struct lpfc_vport *vport = phba->pport;
2078 struct lpfc_sli *psli = &phba->sli;
dea3101e 2079 LPFC_MBOXQ_t *pmb;
2080 volatile uint32_t control;
2081 struct lpfc_dmabuf *mp;
09372820 2082 int rc = 0;
dea3101e 2083
2084 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
09372820
JS
2085 if (!pmb) {
2086 rc = 1;
dea3101e 2087 goto lpfc_handle_latt_err_exit;
09372820 2088 }
dea3101e 2089
2090 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
09372820
JS
2091 if (!mp) {
2092 rc = 2;
dea3101e 2093 goto lpfc_handle_latt_free_pmb;
09372820 2094 }
dea3101e 2095
2096 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
09372820
JS
2097 if (!mp->virt) {
2098 rc = 3;
dea3101e 2099 goto lpfc_handle_latt_free_mp;
09372820 2100 }
dea3101e 2101
6281bfe0 2102 /* Cleanup any outstanding ELS commands */
549e55cd 2103 lpfc_els_flush_all_cmd(phba);
dea3101e 2104
2105 psli->slistat.link_event++;
76a95d75
JS
2106 lpfc_read_topology(phba, pmb, mp);
2107 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
2e0fef85 2108 pmb->vport = vport;
0d2b6b83 2109 /* Block ELS IOCBs until we have processed this mbox command */
895427bd 2110 phba->sli.sli3_ring[LPFC_ELS_RING].flag |= LPFC_STOP_IOCB_EVENT;
0b727fea 2111 rc = lpfc_sli_issue_mbox (phba, pmb, MBX_NOWAIT);
09372820
JS
2112 if (rc == MBX_NOT_FINISHED) {
2113 rc = 4;
14691150 2114 goto lpfc_handle_latt_free_mbuf;
09372820 2115 }
dea3101e 2116
2117 /* Clear Link Attention in HA REG */
2e0fef85 2118 spin_lock_irq(&phba->hbalock);
dea3101e 2119 writel(HA_LATT, phba->HAregaddr);
2120 readl(phba->HAregaddr); /* flush */
2e0fef85 2121 spin_unlock_irq(&phba->hbalock);
dea3101e 2122
2123 return;
2124
14691150 2125lpfc_handle_latt_free_mbuf:
895427bd 2126 phba->sli.sli3_ring[LPFC_ELS_RING].flag &= ~LPFC_STOP_IOCB_EVENT;
14691150 2127 lpfc_mbuf_free(phba, mp->virt, mp->phys);
dea3101e 2128lpfc_handle_latt_free_mp:
2129 kfree(mp);
2130lpfc_handle_latt_free_pmb:
1dcb58e5 2131 mempool_free(pmb, phba->mbox_mem_pool);
dea3101e 2132lpfc_handle_latt_err_exit:
2133 /* Enable Link attention interrupts */
2e0fef85 2134 spin_lock_irq(&phba->hbalock);
dea3101e 2135 psli->sli_flag |= LPFC_PROCESS_LA;
2136 control = readl(phba->HCregaddr);
2137 control |= HC_LAINT_ENA;
2138 writel(control, phba->HCregaddr);
2139 readl(phba->HCregaddr); /* flush */
2140
2141 /* Clear Link Attention in HA REG */
2142 writel(HA_LATT, phba->HAregaddr);
2143 readl(phba->HAregaddr); /* flush */
2e0fef85 2144 spin_unlock_irq(&phba->hbalock);
dea3101e 2145 lpfc_linkdown(phba);
2e0fef85 2146 phba->link_state = LPFC_HBA_ERROR;
dea3101e 2147
372c187b
DK
2148 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2149 "0300 LATT: Cannot issue READ_LA: Data:%d\n", rc);
dea3101e 2150
2151 return;
2152}
2153
e59058c4 2154/**
3621a710 2155 * lpfc_parse_vpd - Parse VPD (Vital Product Data)
e59058c4
JS
2156 * @phba: pointer to lpfc hba data structure.
2157 * @vpd: pointer to the vital product data.
2158 * @len: length of the vital product data in bytes.
2159 *
2160 * This routine parses the Vital Product Data (VPD). The VPD is treated as
2161 * an array of characters. In this routine, the ModelName, ProgramType, and
2162 * ModelDesc, etc. fields of the phba data structure will be populated.
2163 *
2164 * Return codes
2165 * 0 - pointer to the VPD passed in is NULL
2166 * 1 - success
2167 **/
3772a991 2168int
2e0fef85 2169lpfc_parse_vpd(struct lpfc_hba *phba, uint8_t *vpd, int len)
dea3101e 2170{
2171 uint8_t lenlo, lenhi;
07da60c1 2172 int Length;
dea3101e 2173 int i, j;
2174 int finished = 0;
2175 int index = 0;
2176
2177 if (!vpd)
2178 return 0;
2179
2180 /* Vital Product */
ed957684 2181 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011 2182 "0455 Vital Product Data: x%x x%x x%x x%x\n",
dea3101e 2183 (uint32_t) vpd[0], (uint32_t) vpd[1], (uint32_t) vpd[2],
2184 (uint32_t) vpd[3]);
74b72a59 2185 while (!finished && (index < (len - 4))) {
dea3101e 2186 switch (vpd[index]) {
2187 case 0x82:
74b72a59 2188 case 0x91:
dea3101e 2189 index += 1;
2190 lenlo = vpd[index];
2191 index += 1;
2192 lenhi = vpd[index];
2193 index += 1;
2194 i = ((((unsigned short)lenhi) << 8) + lenlo);
2195 index += i;
2196 break;
2197 case 0x90:
2198 index += 1;
2199 lenlo = vpd[index];
2200 index += 1;
2201 lenhi = vpd[index];
2202 index += 1;
2203 Length = ((((unsigned short)lenhi) << 8) + lenlo);
74b72a59
JW
2204 if (Length > len - index)
2205 Length = len - index;
dea3101e 2206 while (Length > 0) {
2207 /* Look for Serial Number */
2208 if ((vpd[index] == 'S') && (vpd[index+1] == 'N')) {
2209 index += 2;
2210 i = vpd[index];
2211 index += 1;
2212 j = 0;
2213 Length -= (3+i);
2214 while(i--) {
2215 phba->SerialNumber[j++] = vpd[index++];
2216 if (j == 31)
2217 break;
2218 }
2219 phba->SerialNumber[j] = 0;
2220 continue;
2221 }
2222 else if ((vpd[index] == 'V') && (vpd[index+1] == '1')) {
2223 phba->vpd_flag |= VPD_MODEL_DESC;
2224 index += 2;
2225 i = vpd[index];
2226 index += 1;
2227 j = 0;
2228 Length -= (3+i);
2229 while(i--) {
2230 phba->ModelDesc[j++] = vpd[index++];
2231 if (j == 255)
2232 break;
2233 }
2234 phba->ModelDesc[j] = 0;
2235 continue;
2236 }
2237 else if ((vpd[index] == 'V') && (vpd[index+1] == '2')) {
2238 phba->vpd_flag |= VPD_MODEL_NAME;
2239 index += 2;
2240 i = vpd[index];
2241 index += 1;
2242 j = 0;
2243 Length -= (3+i);
2244 while(i--) {
2245 phba->ModelName[j++] = vpd[index++];
2246 if (j == 79)
2247 break;
2248 }
2249 phba->ModelName[j] = 0;
2250 continue;
2251 }
2252 else if ((vpd[index] == 'V') && (vpd[index+1] == '3')) {
2253 phba->vpd_flag |= VPD_PROGRAM_TYPE;
2254 index += 2;
2255 i = vpd[index];
2256 index += 1;
2257 j = 0;
2258 Length -= (3+i);
2259 while(i--) {
2260 phba->ProgramType[j++] = vpd[index++];
2261 if (j == 255)
2262 break;
2263 }
2264 phba->ProgramType[j] = 0;
2265 continue;
2266 }
2267 else if ((vpd[index] == 'V') && (vpd[index+1] == '4')) {
2268 phba->vpd_flag |= VPD_PORT;
2269 index += 2;
2270 i = vpd[index];
2271 index += 1;
2272 j = 0;
2273 Length -= (3+i);
2274 while(i--) {
cd1c8301
JS
2275 if ((phba->sli_rev == LPFC_SLI_REV4) &&
2276 (phba->sli4_hba.pport_name_sta ==
2277 LPFC_SLI4_PPNAME_GET)) {
2278 j++;
2279 index++;
2280 } else
2281 phba->Port[j++] = vpd[index++];
2282 if (j == 19)
2283 break;
dea3101e 2284 }
cd1c8301
JS
2285 if ((phba->sli_rev != LPFC_SLI_REV4) ||
2286 (phba->sli4_hba.pport_name_sta ==
2287 LPFC_SLI4_PPNAME_NON))
2288 phba->Port[j] = 0;
dea3101e 2289 continue;
2290 }
2291 else {
2292 index += 2;
2293 i = vpd[index];
2294 index += 1;
2295 index += i;
2296 Length -= (3 + i);
2297 }
2298 }
2299 finished = 0;
2300 break;
2301 case 0x78:
2302 finished = 1;
2303 break;
2304 default:
2305 index ++;
2306 break;
2307 }
74b72a59 2308 }
dea3101e 2309
2310 return(1);
2311}
2312
e59058c4 2313/**
3621a710 2314 * lpfc_get_hba_model_desc - Retrieve HBA device model name and description
e59058c4
JS
2315 * @phba: pointer to lpfc hba data structure.
2316 * @mdp: pointer to the data structure to hold the derived model name.
2317 * @descp: pointer to the data structure to hold the derived description.
2318 *
2319 * This routine retrieves HBA's description based on its registered PCI device
2320 * ID. The @descp passed into this function points to an array of 256 chars. It
2321 * shall be returned with the model name, maximum speed, and the host bus type.
2322 * The @mdp passed into this function points to an array of 80 chars. When the
2323 * function returns, the @mdp will be filled with the model name.
2324 **/
dea3101e 2325static void
2e0fef85 2326lpfc_get_hba_model_desc(struct lpfc_hba *phba, uint8_t *mdp, uint8_t *descp)
dea3101e 2327{
2328 lpfc_vpd_t *vp;
fefcb2b6 2329 uint16_t dev_id = phba->pcidev->device;
74b72a59 2330 int max_speed;
84774a4d 2331 int GE = 0;
da0436e9 2332 int oneConnect = 0; /* default is not a oneConnect */
74b72a59 2333 struct {
a747c9ce
JS
2334 char *name;
2335 char *bus;
2336 char *function;
2337 } m = {"<Unknown>", "", ""};
74b72a59
JW
2338
2339 if (mdp && mdp[0] != '\0'
2340 && descp && descp[0] != '\0')
2341 return;
2342
fbd8a6ba
JS
2343 if (phba->lmt & LMT_64Gb)
2344 max_speed = 64;
2345 else if (phba->lmt & LMT_32Gb)
d38dd52c
JS
2346 max_speed = 32;
2347 else if (phba->lmt & LMT_16Gb)
c0c11512
JS
2348 max_speed = 16;
2349 else if (phba->lmt & LMT_10Gb)
74b72a59
JW
2350 max_speed = 10;
2351 else if (phba->lmt & LMT_8Gb)
2352 max_speed = 8;
2353 else if (phba->lmt & LMT_4Gb)
2354 max_speed = 4;
2355 else if (phba->lmt & LMT_2Gb)
2356 max_speed = 2;
4169d868 2357 else if (phba->lmt & LMT_1Gb)
74b72a59 2358 max_speed = 1;
4169d868
JS
2359 else
2360 max_speed = 0;
dea3101e 2361
2362 vp = &phba->vpd;
dea3101e 2363
e4adb204 2364 switch (dev_id) {
06325e74 2365 case PCI_DEVICE_ID_FIREFLY:
12222f4f
JS
2366 m = (typeof(m)){"LP6000", "PCI",
2367 "Obsolete, Unsupported Fibre Channel Adapter"};
06325e74 2368 break;
dea3101e 2369 case PCI_DEVICE_ID_SUPERFLY:
2370 if (vp->rev.biuRev >= 1 && vp->rev.biuRev <= 3)
12222f4f 2371 m = (typeof(m)){"LP7000", "PCI", ""};
dea3101e 2372 else
12222f4f
JS
2373 m = (typeof(m)){"LP7000E", "PCI", ""};
2374 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
dea3101e 2375 break;
2376 case PCI_DEVICE_ID_DRAGONFLY:
a747c9ce 2377 m = (typeof(m)){"LP8000", "PCI",
12222f4f 2378 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2379 break;
2380 case PCI_DEVICE_ID_CENTAUR:
2381 if (FC_JEDEC_ID(vp->rev.biuRev) == CENTAUR_2G_JEDEC_ID)
12222f4f 2382 m = (typeof(m)){"LP9002", "PCI", ""};
dea3101e 2383 else
12222f4f
JS
2384 m = (typeof(m)){"LP9000", "PCI", ""};
2385 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
dea3101e 2386 break;
2387 case PCI_DEVICE_ID_RFLY:
a747c9ce 2388 m = (typeof(m)){"LP952", "PCI",
12222f4f 2389 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2390 break;
2391 case PCI_DEVICE_ID_PEGASUS:
a747c9ce 2392 m = (typeof(m)){"LP9802", "PCI-X",
12222f4f 2393 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2394 break;
2395 case PCI_DEVICE_ID_THOR:
a747c9ce 2396 m = (typeof(m)){"LP10000", "PCI-X",
12222f4f 2397 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2398 break;
2399 case PCI_DEVICE_ID_VIPER:
a747c9ce 2400 m = (typeof(m)){"LPX1000", "PCI-X",
12222f4f 2401 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2402 break;
2403 case PCI_DEVICE_ID_PFLY:
a747c9ce 2404 m = (typeof(m)){"LP982", "PCI-X",
12222f4f 2405 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2406 break;
2407 case PCI_DEVICE_ID_TFLY:
a747c9ce 2408 m = (typeof(m)){"LP1050", "PCI-X",
12222f4f 2409 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2410 break;
2411 case PCI_DEVICE_ID_HELIOS:
a747c9ce 2412 m = (typeof(m)){"LP11000", "PCI-X2",
12222f4f 2413 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2414 break;
e4adb204 2415 case PCI_DEVICE_ID_HELIOS_SCSP:
a747c9ce 2416 m = (typeof(m)){"LP11000-SP", "PCI-X2",
12222f4f 2417 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2418 break;
2419 case PCI_DEVICE_ID_HELIOS_DCSP:
a747c9ce 2420 m = (typeof(m)){"LP11002-SP", "PCI-X2",
12222f4f 2421 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2422 break;
2423 case PCI_DEVICE_ID_NEPTUNE:
12222f4f
JS
2424 m = (typeof(m)){"LPe1000", "PCIe",
2425 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2426 break;
2427 case PCI_DEVICE_ID_NEPTUNE_SCSP:
12222f4f
JS
2428 m = (typeof(m)){"LPe1000-SP", "PCIe",
2429 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2430 break;
2431 case PCI_DEVICE_ID_NEPTUNE_DCSP:
12222f4f
JS
2432 m = (typeof(m)){"LPe1002-SP", "PCIe",
2433 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204 2434 break;
dea3101e 2435 case PCI_DEVICE_ID_BMID:
a747c9ce 2436 m = (typeof(m)){"LP1150", "PCI-X2", "Fibre Channel Adapter"};
dea3101e 2437 break;
2438 case PCI_DEVICE_ID_BSMB:
12222f4f
JS
2439 m = (typeof(m)){"LP111", "PCI-X2",
2440 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2441 break;
2442 case PCI_DEVICE_ID_ZEPHYR:
a747c9ce 2443 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
dea3101e 2444 break;
e4adb204 2445 case PCI_DEVICE_ID_ZEPHYR_SCSP:
a747c9ce 2446 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
e4adb204
JSEC
2447 break;
2448 case PCI_DEVICE_ID_ZEPHYR_DCSP:
a747c9ce 2449 m = (typeof(m)){"LP2105", "PCIe", "FCoE Adapter"};
a257bf90 2450 GE = 1;
e4adb204 2451 break;
dea3101e 2452 case PCI_DEVICE_ID_ZMID:
a747c9ce 2453 m = (typeof(m)){"LPe1150", "PCIe", "Fibre Channel Adapter"};
dea3101e 2454 break;
2455 case PCI_DEVICE_ID_ZSMB:
a747c9ce 2456 m = (typeof(m)){"LPe111", "PCIe", "Fibre Channel Adapter"};
dea3101e 2457 break;
2458 case PCI_DEVICE_ID_LP101:
12222f4f
JS
2459 m = (typeof(m)){"LP101", "PCI-X",
2460 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2461 break;
2462 case PCI_DEVICE_ID_LP10000S:
12222f4f
JS
2463 m = (typeof(m)){"LP10000-S", "PCI",
2464 "Obsolete, Unsupported Fibre Channel Adapter"};
06325e74 2465 break;
e4adb204 2466 case PCI_DEVICE_ID_LP11000S:
12222f4f
JS
2467 m = (typeof(m)){"LP11000-S", "PCI-X2",
2468 "Obsolete, Unsupported Fibre Channel Adapter"};
18a3b596 2469 break;
e4adb204 2470 case PCI_DEVICE_ID_LPE11000S:
12222f4f
JS
2471 m = (typeof(m)){"LPe11000-S", "PCIe",
2472 "Obsolete, Unsupported Fibre Channel Adapter"};
5cc36b3c 2473 break;
b87eab38 2474 case PCI_DEVICE_ID_SAT:
a747c9ce 2475 m = (typeof(m)){"LPe12000", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2476 break;
2477 case PCI_DEVICE_ID_SAT_MID:
a747c9ce 2478 m = (typeof(m)){"LPe1250", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2479 break;
2480 case PCI_DEVICE_ID_SAT_SMB:
a747c9ce 2481 m = (typeof(m)){"LPe121", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2482 break;
2483 case PCI_DEVICE_ID_SAT_DCSP:
a747c9ce 2484 m = (typeof(m)){"LPe12002-SP", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2485 break;
2486 case PCI_DEVICE_ID_SAT_SCSP:
a747c9ce 2487 m = (typeof(m)){"LPe12000-SP", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2488 break;
2489 case PCI_DEVICE_ID_SAT_S:
a747c9ce 2490 m = (typeof(m)){"LPe12000-S", "PCIe", "Fibre Channel Adapter"};
b87eab38 2491 break;
84774a4d 2492 case PCI_DEVICE_ID_HORNET:
12222f4f
JS
2493 m = (typeof(m)){"LP21000", "PCIe",
2494 "Obsolete, Unsupported FCoE Adapter"};
84774a4d
JS
2495 GE = 1;
2496 break;
2497 case PCI_DEVICE_ID_PROTEUS_VF:
a747c9ce 2498 m = (typeof(m)){"LPev12000", "PCIe IOV",
12222f4f 2499 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d
JS
2500 break;
2501 case PCI_DEVICE_ID_PROTEUS_PF:
a747c9ce 2502 m = (typeof(m)){"LPev12000", "PCIe IOV",
12222f4f 2503 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d
JS
2504 break;
2505 case PCI_DEVICE_ID_PROTEUS_S:
a747c9ce 2506 m = (typeof(m)){"LPemv12002-S", "PCIe IOV",
12222f4f 2507 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d 2508 break;
da0436e9
JS
2509 case PCI_DEVICE_ID_TIGERSHARK:
2510 oneConnect = 1;
a747c9ce 2511 m = (typeof(m)){"OCe10100", "PCIe", "FCoE"};
da0436e9 2512 break;
a747c9ce 2513 case PCI_DEVICE_ID_TOMCAT:
6669f9bb 2514 oneConnect = 1;
a747c9ce
JS
2515 m = (typeof(m)){"OCe11100", "PCIe", "FCoE"};
2516 break;
2517 case PCI_DEVICE_ID_FALCON:
2518 m = (typeof(m)){"LPSe12002-ML1-E", "PCIe",
2519 "EmulexSecure Fibre"};
6669f9bb 2520 break;
98fc5dd9
JS
2521 case PCI_DEVICE_ID_BALIUS:
2522 m = (typeof(m)){"LPVe12002", "PCIe Shared I/O",
12222f4f 2523 "Obsolete, Unsupported Fibre Channel Adapter"};
98fc5dd9 2524 break;
085c647c 2525 case PCI_DEVICE_ID_LANCER_FC:
c0c11512 2526 m = (typeof(m)){"LPe16000", "PCIe", "Fibre Channel Adapter"};
085c647c 2527 break;
12222f4f
JS
2528 case PCI_DEVICE_ID_LANCER_FC_VF:
2529 m = (typeof(m)){"LPe16000", "PCIe",
2530 "Obsolete, Unsupported Fibre Channel Adapter"};
2531 break;
085c647c
JS
2532 case PCI_DEVICE_ID_LANCER_FCOE:
2533 oneConnect = 1;
079b5c91 2534 m = (typeof(m)){"OCe15100", "PCIe", "FCoE"};
085c647c 2535 break;
12222f4f
JS
2536 case PCI_DEVICE_ID_LANCER_FCOE_VF:
2537 oneConnect = 1;
2538 m = (typeof(m)){"OCe15100", "PCIe",
2539 "Obsolete, Unsupported FCoE"};
2540 break;
d38dd52c
JS
2541 case PCI_DEVICE_ID_LANCER_G6_FC:
2542 m = (typeof(m)){"LPe32000", "PCIe", "Fibre Channel Adapter"};
2543 break;
c238b9b6
JS
2544 case PCI_DEVICE_ID_LANCER_G7_FC:
2545 m = (typeof(m)){"LPe36000", "PCIe", "Fibre Channel Adapter"};
2546 break;
f8cafd38
JS
2547 case PCI_DEVICE_ID_SKYHAWK:
2548 case PCI_DEVICE_ID_SKYHAWK_VF:
2549 oneConnect = 1;
2550 m = (typeof(m)){"OCe14000", "PCIe", "FCoE"};
2551 break;
5cc36b3c 2552 default:
a747c9ce 2553 m = (typeof(m)){"Unknown", "", ""};
e4adb204 2554 break;
dea3101e 2555 }
74b72a59
JW
2556
2557 if (mdp && mdp[0] == '\0')
2558 snprintf(mdp, 79,"%s", m.name);
c0c11512
JS
2559 /*
2560 * oneConnect hba requires special processing, they are all initiators
da0436e9
JS
2561 * and we put the port number on the end
2562 */
2563 if (descp && descp[0] == '\0') {
2564 if (oneConnect)
2565 snprintf(descp, 255,
4169d868 2566 "Emulex OneConnect %s, %s Initiator %s",
a747c9ce 2567 m.name, m.function,
da0436e9 2568 phba->Port);
4169d868
JS
2569 else if (max_speed == 0)
2570 snprintf(descp, 255,
290237d2 2571 "Emulex %s %s %s",
4169d868 2572 m.name, m.bus, m.function);
da0436e9
JS
2573 else
2574 snprintf(descp, 255,
2575 "Emulex %s %d%s %s %s",
a747c9ce
JS
2576 m.name, max_speed, (GE) ? "GE" : "Gb",
2577 m.bus, m.function);
da0436e9 2578 }
dea3101e 2579}
2580
e59058c4 2581/**
3621a710 2582 * lpfc_post_buffer - Post IOCB(s) with DMA buffer descriptor(s) to a IOCB ring
e59058c4
JS
2583 * @phba: pointer to lpfc hba data structure.
2584 * @pring: pointer to a IOCB ring.
2585 * @cnt: the number of IOCBs to be posted to the IOCB ring.
2586 *
2587 * This routine posts a given number of IOCBs with the associated DMA buffer
2588 * descriptors specified by the cnt argument to the given IOCB ring.
2589 *
2590 * Return codes
2591 * The number of IOCBs NOT able to be posted to the IOCB ring.
2592 **/
dea3101e 2593int
495a714c 2594lpfc_post_buffer(struct lpfc_hba *phba, struct lpfc_sli_ring *pring, int cnt)
dea3101e 2595{
2596 IOCB_t *icmd;
0bd4ca25 2597 struct lpfc_iocbq *iocb;
dea3101e 2598 struct lpfc_dmabuf *mp1, *mp2;
2599
2600 cnt += pring->missbufcnt;
2601
2602 /* While there are buffers to post */
2603 while (cnt > 0) {
2604 /* Allocate buffer for command iocb */
0bd4ca25 2605 iocb = lpfc_sli_get_iocbq(phba);
dea3101e 2606 if (iocb == NULL) {
2607 pring->missbufcnt = cnt;
2608 return cnt;
2609 }
dea3101e 2610 icmd = &iocb->iocb;
2611
2612 /* 2 buffers can be posted per command */
2613 /* Allocate buffer to post */
2614 mp1 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2615 if (mp1)
98c9ea5c
JS
2616 mp1->virt = lpfc_mbuf_alloc(phba, MEM_PRI, &mp1->phys);
2617 if (!mp1 || !mp1->virt) {
c9475cb0 2618 kfree(mp1);
604a3e30 2619 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2620 pring->missbufcnt = cnt;
2621 return cnt;
2622 }
2623
2624 INIT_LIST_HEAD(&mp1->list);
2625 /* Allocate buffer to post */
2626 if (cnt > 1) {
2627 mp2 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2628 if (mp2)
2629 mp2->virt = lpfc_mbuf_alloc(phba, MEM_PRI,
2630 &mp2->phys);
98c9ea5c 2631 if (!mp2 || !mp2->virt) {
c9475cb0 2632 kfree(mp2);
dea3101e 2633 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2634 kfree(mp1);
604a3e30 2635 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2636 pring->missbufcnt = cnt;
2637 return cnt;
2638 }
2639
2640 INIT_LIST_HEAD(&mp2->list);
2641 } else {
2642 mp2 = NULL;
2643 }
2644
2645 icmd->un.cont64[0].addrHigh = putPaddrHigh(mp1->phys);
2646 icmd->un.cont64[0].addrLow = putPaddrLow(mp1->phys);
2647 icmd->un.cont64[0].tus.f.bdeSize = FCELSSIZE;
2648 icmd->ulpBdeCount = 1;
2649 cnt--;
2650 if (mp2) {
2651 icmd->un.cont64[1].addrHigh = putPaddrHigh(mp2->phys);
2652 icmd->un.cont64[1].addrLow = putPaddrLow(mp2->phys);
2653 icmd->un.cont64[1].tus.f.bdeSize = FCELSSIZE;
2654 cnt--;
2655 icmd->ulpBdeCount = 2;
2656 }
2657
2658 icmd->ulpCommand = CMD_QUE_RING_BUF64_CN;
2659 icmd->ulpLe = 1;
2660
3772a991
JS
2661 if (lpfc_sli_issue_iocb(phba, pring->ringno, iocb, 0) ==
2662 IOCB_ERROR) {
dea3101e 2663 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2664 kfree(mp1);
2665 cnt++;
2666 if (mp2) {
2667 lpfc_mbuf_free(phba, mp2->virt, mp2->phys);
2668 kfree(mp2);
2669 cnt++;
2670 }
604a3e30 2671 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2672 pring->missbufcnt = cnt;
dea3101e 2673 return cnt;
2674 }
dea3101e 2675 lpfc_sli_ringpostbuf_put(phba, pring, mp1);
92d7f7b0 2676 if (mp2)
dea3101e 2677 lpfc_sli_ringpostbuf_put(phba, pring, mp2);
dea3101e 2678 }
2679 pring->missbufcnt = 0;
2680 return 0;
2681}
2682
e59058c4 2683/**
3621a710 2684 * lpfc_post_rcv_buf - Post the initial receive IOCB buffers to ELS ring
e59058c4
JS
2685 * @phba: pointer to lpfc hba data structure.
2686 *
2687 * This routine posts initial receive IOCB buffers to the ELS ring. The
2688 * current number of initial IOCB buffers specified by LPFC_BUF_RING0 is
895427bd 2689 * set to 64 IOCBs. SLI3 only.
e59058c4
JS
2690 *
2691 * Return codes
2692 * 0 - success (currently always success)
2693 **/
dea3101e 2694static int
2e0fef85 2695lpfc_post_rcv_buf(struct lpfc_hba *phba)
dea3101e 2696{
2697 struct lpfc_sli *psli = &phba->sli;
2698
2699 /* Ring 0, ELS / CT buffers */
895427bd 2700 lpfc_post_buffer(phba, &psli->sli3_ring[LPFC_ELS_RING], LPFC_BUF_RING0);
dea3101e 2701 /* Ring 2 - FCP no buffers needed */
2702
2703 return 0;
2704}
2705
2706#define S(N,V) (((V)<<(N))|((V)>>(32-(N))))
2707
e59058c4 2708/**
3621a710 2709 * lpfc_sha_init - Set up initial array of hash table entries
e59058c4
JS
2710 * @HashResultPointer: pointer to an array as hash table.
2711 *
2712 * This routine sets up the initial values to the array of hash table entries
2713 * for the LC HBAs.
2714 **/
dea3101e 2715static void
2716lpfc_sha_init(uint32_t * HashResultPointer)
2717{
2718 HashResultPointer[0] = 0x67452301;
2719 HashResultPointer[1] = 0xEFCDAB89;
2720 HashResultPointer[2] = 0x98BADCFE;
2721 HashResultPointer[3] = 0x10325476;
2722 HashResultPointer[4] = 0xC3D2E1F0;
2723}
2724
e59058c4 2725/**
3621a710 2726 * lpfc_sha_iterate - Iterate initial hash table with the working hash table
e59058c4
JS
2727 * @HashResultPointer: pointer to an initial/result hash table.
2728 * @HashWorkingPointer: pointer to an working hash table.
2729 *
2730 * This routine iterates an initial hash table pointed by @HashResultPointer
2731 * with the values from the working hash table pointeed by @HashWorkingPointer.
2732 * The results are putting back to the initial hash table, returned through
2733 * the @HashResultPointer as the result hash table.
2734 **/
dea3101e 2735static void
2736lpfc_sha_iterate(uint32_t * HashResultPointer, uint32_t * HashWorkingPointer)
2737{
2738 int t;
2739 uint32_t TEMP;
2740 uint32_t A, B, C, D, E;
2741 t = 16;
2742 do {
2743 HashWorkingPointer[t] =
2744 S(1,
2745 HashWorkingPointer[t - 3] ^ HashWorkingPointer[t -
2746 8] ^
2747 HashWorkingPointer[t - 14] ^ HashWorkingPointer[t - 16]);
2748 } while (++t <= 79);
2749 t = 0;
2750 A = HashResultPointer[0];
2751 B = HashResultPointer[1];
2752 C = HashResultPointer[2];
2753 D = HashResultPointer[3];
2754 E = HashResultPointer[4];
2755
2756 do {
2757 if (t < 20) {
2758 TEMP = ((B & C) | ((~B) & D)) + 0x5A827999;
2759 } else if (t < 40) {
2760 TEMP = (B ^ C ^ D) + 0x6ED9EBA1;
2761 } else if (t < 60) {
2762 TEMP = ((B & C) | (B & D) | (C & D)) + 0x8F1BBCDC;
2763 } else {
2764 TEMP = (B ^ C ^ D) + 0xCA62C1D6;
2765 }
2766 TEMP += S(5, A) + E + HashWorkingPointer[t];
2767 E = D;
2768 D = C;
2769 C = S(30, B);
2770 B = A;
2771 A = TEMP;
2772 } while (++t <= 79);
2773
2774 HashResultPointer[0] += A;
2775 HashResultPointer[1] += B;
2776 HashResultPointer[2] += C;
2777 HashResultPointer[3] += D;
2778 HashResultPointer[4] += E;
2779
2780}
2781
e59058c4 2782/**
3621a710 2783 * lpfc_challenge_key - Create challenge key based on WWPN of the HBA
e59058c4
JS
2784 * @RandomChallenge: pointer to the entry of host challenge random number array.
2785 * @HashWorking: pointer to the entry of the working hash array.
2786 *
2787 * This routine calculates the working hash array referred by @HashWorking
2788 * from the challenge random numbers associated with the host, referred by
2789 * @RandomChallenge. The result is put into the entry of the working hash
2790 * array and returned by reference through @HashWorking.
2791 **/
dea3101e 2792static void
2793lpfc_challenge_key(uint32_t * RandomChallenge, uint32_t * HashWorking)
2794{
2795 *HashWorking = (*RandomChallenge ^ *HashWorking);
2796}
2797
e59058c4 2798/**
3621a710 2799 * lpfc_hba_init - Perform special handling for LC HBA initialization
e59058c4
JS
2800 * @phba: pointer to lpfc hba data structure.
2801 * @hbainit: pointer to an array of unsigned 32-bit integers.
2802 *
2803 * This routine performs the special handling for LC HBA initialization.
2804 **/
dea3101e 2805void
2806lpfc_hba_init(struct lpfc_hba *phba, uint32_t *hbainit)
2807{
2808 int t;
2809 uint32_t *HashWorking;
2e0fef85 2810 uint32_t *pwwnn = (uint32_t *) phba->wwnn;
dea3101e 2811
bbfbbbc1 2812 HashWorking = kcalloc(80, sizeof(uint32_t), GFP_KERNEL);
dea3101e 2813 if (!HashWorking)
2814 return;
2815
dea3101e 2816 HashWorking[0] = HashWorking[78] = *pwwnn++;
2817 HashWorking[1] = HashWorking[79] = *pwwnn;
2818
2819 for (t = 0; t < 7; t++)
2820 lpfc_challenge_key(phba->RandomData + t, HashWorking + t);
2821
2822 lpfc_sha_init(hbainit);
2823 lpfc_sha_iterate(hbainit, HashWorking);
2824 kfree(HashWorking);
2825}
2826
e59058c4 2827/**
3621a710 2828 * lpfc_cleanup - Performs vport cleanups before deleting a vport
e59058c4
JS
2829 * @vport: pointer to a virtual N_Port data structure.
2830 *
2831 * This routine performs the necessary cleanups before deleting the @vport.
2832 * It invokes the discovery state machine to perform necessary state
2833 * transitions and to release the ndlps associated with the @vport. Note,
2834 * the physical port is treated as @vport 0.
2835 **/
87af33fe 2836void
2e0fef85 2837lpfc_cleanup(struct lpfc_vport *vport)
dea3101e 2838{
87af33fe 2839 struct lpfc_hba *phba = vport->phba;
dea3101e 2840 struct lpfc_nodelist *ndlp, *next_ndlp;
a8adb832 2841 int i = 0;
dea3101e 2842
87af33fe
JS
2843 if (phba->link_state > LPFC_LINK_DOWN)
2844 lpfc_port_link_failure(vport);
2845
2846 list_for_each_entry_safe(ndlp, next_ndlp, &vport->fc_nodes, nlp_listp) {
e47c9093
JS
2847 if (!NLP_CHK_NODE_ACT(ndlp)) {
2848 ndlp = lpfc_enable_node(vport, ndlp,
2849 NLP_STE_UNUSED_NODE);
2850 if (!ndlp)
2851 continue;
2852 spin_lock_irq(&phba->ndlp_lock);
2853 NLP_SET_FREE_REQ(ndlp);
2854 spin_unlock_irq(&phba->ndlp_lock);
2855 /* Trigger the release of the ndlp memory */
2856 lpfc_nlp_put(ndlp);
2857 continue;
2858 }
2859 spin_lock_irq(&phba->ndlp_lock);
2860 if (NLP_CHK_FREE_REQ(ndlp)) {
2861 /* The ndlp should not be in memory free mode already */
2862 spin_unlock_irq(&phba->ndlp_lock);
2863 continue;
2864 } else
2865 /* Indicate request for freeing ndlp memory */
2866 NLP_SET_FREE_REQ(ndlp);
2867 spin_unlock_irq(&phba->ndlp_lock);
2868
58da1ffb
JS
2869 if (vport->port_type != LPFC_PHYSICAL_PORT &&
2870 ndlp->nlp_DID == Fabric_DID) {
2871 /* Just free up ndlp with Fabric_DID for vports */
2872 lpfc_nlp_put(ndlp);
2873 continue;
2874 }
2875
eff4a01b
JS
2876 /* take care of nodes in unused state before the state
2877 * machine taking action.
2878 */
2879 if (ndlp->nlp_state == NLP_STE_UNUSED_NODE) {
2880 lpfc_nlp_put(ndlp);
2881 continue;
2882 }
2883
87af33fe
JS
2884 if (ndlp->nlp_type & NLP_FABRIC)
2885 lpfc_disc_state_machine(vport, ndlp, NULL,
2886 NLP_EVT_DEVICE_RECOVERY);
e47c9093 2887
87af33fe
JS
2888 lpfc_disc_state_machine(vport, ndlp, NULL,
2889 NLP_EVT_DEVICE_RM);
2890 }
2891
a8adb832
JS
2892 /* At this point, ALL ndlp's should be gone
2893 * because of the previous NLP_EVT_DEVICE_RM.
2894 * Lets wait for this to happen, if needed.
2895 */
87af33fe 2896 while (!list_empty(&vport->fc_nodes)) {
a8adb832 2897 if (i++ > 3000) {
372c187b
DK
2898 lpfc_printf_vlog(vport, KERN_ERR,
2899 LOG_TRACE_EVENT,
a8adb832 2900 "0233 Nodelist not empty\n");
e47c9093
JS
2901 list_for_each_entry_safe(ndlp, next_ndlp,
2902 &vport->fc_nodes, nlp_listp) {
2903 lpfc_printf_vlog(ndlp->vport, KERN_ERR,
372c187b 2904 LOG_TRACE_EVENT,
32350664 2905 "0282 did:x%x ndlp:x%px "
e47c9093
JS
2906 "usgmap:x%x refcnt:%d\n",
2907 ndlp->nlp_DID, (void *)ndlp,
2908 ndlp->nlp_usg_map,
2c935bc5 2909 kref_read(&ndlp->kref));
e47c9093 2910 }
a8adb832 2911 break;
87af33fe 2912 }
a8adb832
JS
2913
2914 /* Wait for any activity on ndlps to settle */
2915 msleep(10);
87af33fe 2916 }
1151e3ec 2917 lpfc_cleanup_vports_rrqs(vport, NULL);
dea3101e 2918}
2919
e59058c4 2920/**
3621a710 2921 * lpfc_stop_vport_timers - Stop all the timers associated with a vport
e59058c4
JS
2922 * @vport: pointer to a virtual N_Port data structure.
2923 *
2924 * This routine stops all the timers associated with a @vport. This function
2925 * is invoked before disabling or deleting a @vport. Note that the physical
2926 * port is treated as @vport 0.
2927 **/
92d7f7b0
JS
2928void
2929lpfc_stop_vport_timers(struct lpfc_vport *vport)
dea3101e 2930{
92d7f7b0 2931 del_timer_sync(&vport->els_tmofunc);
92494144 2932 del_timer_sync(&vport->delayed_disc_tmo);
92d7f7b0
JS
2933 lpfc_can_disctmo(vport);
2934 return;
dea3101e 2935}
2936
ecfd03c6
JS
2937/**
2938 * __lpfc_sli4_stop_fcf_redisc_wait_timer - Stop FCF rediscovery wait timer
2939 * @phba: pointer to lpfc hba data structure.
2940 *
2941 * This routine stops the SLI4 FCF rediscover wait timer if it's on. The
2942 * caller of this routine should already hold the host lock.
2943 **/
2944void
2945__lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2946{
5ac6b303
JS
2947 /* Clear pending FCF rediscovery wait flag */
2948 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
2949
ecfd03c6
JS
2950 /* Now, try to stop the timer */
2951 del_timer(&phba->fcf.redisc_wait);
2952}
2953
2954/**
2955 * lpfc_sli4_stop_fcf_redisc_wait_timer - Stop FCF rediscovery wait timer
2956 * @phba: pointer to lpfc hba data structure.
2957 *
2958 * This routine stops the SLI4 FCF rediscover wait timer if it's on. It
2959 * checks whether the FCF rediscovery wait timer is pending with the host
2960 * lock held before proceeding with disabling the timer and clearing the
2961 * wait timer pendig flag.
2962 **/
2963void
2964lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2965{
2966 spin_lock_irq(&phba->hbalock);
2967 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
2968 /* FCF rediscovery timer already fired or stopped */
2969 spin_unlock_irq(&phba->hbalock);
2970 return;
2971 }
2972 __lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
5ac6b303
JS
2973 /* Clear failover in progress flags */
2974 phba->fcf.fcf_flag &= ~(FCF_DEAD_DISC | FCF_ACVL_DISC);
ecfd03c6
JS
2975 spin_unlock_irq(&phba->hbalock);
2976}
2977
e59058c4 2978/**
3772a991 2979 * lpfc_stop_hba_timers - Stop all the timers associated with an HBA
e59058c4
JS
2980 * @phba: pointer to lpfc hba data structure.
2981 *
2982 * This routine stops all the timers associated with a HBA. This function is
2983 * invoked before either putting a HBA offline or unloading the driver.
2984 **/
3772a991
JS
2985void
2986lpfc_stop_hba_timers(struct lpfc_hba *phba)
dea3101e 2987{
cdb42bec
JS
2988 if (phba->pport)
2989 lpfc_stop_vport_timers(phba->pport);
32517fc0 2990 cancel_delayed_work_sync(&phba->eq_delay_work);
317aeb83 2991 cancel_delayed_work_sync(&phba->idle_stat_delay_work);
2e0fef85 2992 del_timer_sync(&phba->sli.mbox_tmo);
92d7f7b0 2993 del_timer_sync(&phba->fabric_block_timer);
9399627f 2994 del_timer_sync(&phba->eratt_poll);
3772a991 2995 del_timer_sync(&phba->hb_tmofunc);
1151e3ec
JS
2996 if (phba->sli_rev == LPFC_SLI_REV4) {
2997 del_timer_sync(&phba->rrq_tmr);
2998 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
2999 }
3772a991
JS
3000 phba->hb_outstanding = 0;
3001
3002 switch (phba->pci_dev_grp) {
3003 case LPFC_PCI_DEV_LP:
3004 /* Stop any LightPulse device specific driver timers */
3005 del_timer_sync(&phba->fcp_poll_timer);
3006 break;
3007 case LPFC_PCI_DEV_OC:
cc0e5f1c 3008 /* Stop any OneConnect device specific driver timers */
ecfd03c6 3009 lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
3772a991
JS
3010 break;
3011 default:
372c187b 3012 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
3013 "0297 Invalid device group (x%x)\n",
3014 phba->pci_dev_grp);
3015 break;
3016 }
2e0fef85 3017 return;
dea3101e 3018}
3019
e59058c4 3020/**
3621a710 3021 * lpfc_block_mgmt_io - Mark a HBA's management interface as blocked
e59058c4 3022 * @phba: pointer to lpfc hba data structure.
fe614acd 3023 * @mbx_action: flag for mailbox no wait action.
e59058c4
JS
3024 *
3025 * This routine marks a HBA's management interface as blocked. Once the HBA's
3026 * management interface is marked as blocked, all the user space access to
3027 * the HBA, whether they are from sysfs interface or libdfc interface will
3028 * all be blocked. The HBA is set to block the management interface when the
3029 * driver prepares the HBA interface for online or offline.
3030 **/
a6ababd2 3031static void
618a5230 3032lpfc_block_mgmt_io(struct lpfc_hba *phba, int mbx_action)
a6ababd2
AB
3033{
3034 unsigned long iflag;
6e7288d9
JS
3035 uint8_t actcmd = MBX_HEARTBEAT;
3036 unsigned long timeout;
3037
a6ababd2
AB
3038 spin_lock_irqsave(&phba->hbalock, iflag);
3039 phba->sli.sli_flag |= LPFC_BLOCK_MGMT_IO;
618a5230
JS
3040 spin_unlock_irqrestore(&phba->hbalock, iflag);
3041 if (mbx_action == LPFC_MBX_NO_WAIT)
3042 return;
3043 timeout = msecs_to_jiffies(LPFC_MBOX_TMO * 1000) + jiffies;
3044 spin_lock_irqsave(&phba->hbalock, iflag);
a183a15f 3045 if (phba->sli.mbox_active) {
6e7288d9 3046 actcmd = phba->sli.mbox_active->u.mb.mbxCommand;
a183a15f
JS
3047 /* Determine how long we might wait for the active mailbox
3048 * command to be gracefully completed by firmware.
3049 */
3050 timeout = msecs_to_jiffies(lpfc_mbox_tmo_val(phba,
3051 phba->sli.mbox_active) * 1000) + jiffies;
3052 }
a6ababd2 3053 spin_unlock_irqrestore(&phba->hbalock, iflag);
a183a15f 3054
6e7288d9
JS
3055 /* Wait for the outstnading mailbox command to complete */
3056 while (phba->sli.mbox_active) {
3057 /* Check active mailbox complete status every 2ms */
3058 msleep(2);
3059 if (time_after(jiffies, timeout)) {
372c187b
DK
3060 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3061 "2813 Mgmt IO is Blocked %x "
3062 "- mbox cmd %x still active\n",
3063 phba->sli.sli_flag, actcmd);
6e7288d9
JS
3064 break;
3065 }
3066 }
a6ababd2
AB
3067}
3068
6b5151fd
JS
3069/**
3070 * lpfc_sli4_node_prep - Assign RPIs for active nodes.
3071 * @phba: pointer to lpfc hba data structure.
3072 *
3073 * Allocate RPIs for all active remote nodes. This is needed whenever
3074 * an SLI4 adapter is reset and the driver is not unloading. Its purpose
3075 * is to fixup the temporary rpi assignments.
3076 **/
3077void
3078lpfc_sli4_node_prep(struct lpfc_hba *phba)
3079{
3080 struct lpfc_nodelist *ndlp, *next_ndlp;
3081 struct lpfc_vport **vports;
9d3d340d
JS
3082 int i, rpi;
3083 unsigned long flags;
6b5151fd
JS
3084
3085 if (phba->sli_rev != LPFC_SLI_REV4)
3086 return;
3087
3088 vports = lpfc_create_vport_work_array(phba);
9d3d340d
JS
3089 if (vports == NULL)
3090 return;
6b5151fd 3091
9d3d340d
JS
3092 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
3093 if (vports[i]->load_flag & FC_UNLOADING)
3094 continue;
3095
3096 list_for_each_entry_safe(ndlp, next_ndlp,
3097 &vports[i]->fc_nodes,
3098 nlp_listp) {
3099 if (!NLP_CHK_NODE_ACT(ndlp))
3100 continue;
3101 rpi = lpfc_sli4_alloc_rpi(phba);
3102 if (rpi == LPFC_RPI_ALLOC_ERROR) {
3103 spin_lock_irqsave(&phba->ndlp_lock, flags);
3104 NLP_CLR_NODE_ACT(ndlp);
3105 spin_unlock_irqrestore(&phba->ndlp_lock, flags);
3106 continue;
6b5151fd 3107 }
9d3d340d 3108 ndlp->nlp_rpi = rpi;
0f154226
JS
3109 lpfc_printf_vlog(ndlp->vport, KERN_INFO,
3110 LOG_NODE | LOG_DISCOVERY,
3111 "0009 Assign RPI x%x to ndlp x%px "
3112 "DID:x%06x flg:x%x map:x%x\n",
3113 ndlp->nlp_rpi, ndlp, ndlp->nlp_DID,
3114 ndlp->nlp_flag, ndlp->nlp_usg_map);
6b5151fd
JS
3115 }
3116 }
3117 lpfc_destroy_vport_work_array(phba, vports);
3118}
3119
c490850a
JS
3120/**
3121 * lpfc_create_expedite_pool - create expedite pool
3122 * @phba: pointer to lpfc hba data structure.
3123 *
3124 * This routine moves a batch of XRIs from lpfc_io_buf_list_put of HWQ 0
3125 * to expedite pool. Mark them as expedite.
3126 **/
3999df75 3127static void lpfc_create_expedite_pool(struct lpfc_hba *phba)
c490850a
JS
3128{
3129 struct lpfc_sli4_hdw_queue *qp;
3130 struct lpfc_io_buf *lpfc_ncmd;
3131 struct lpfc_io_buf *lpfc_ncmd_next;
3132 struct lpfc_epd_pool *epd_pool;
3133 unsigned long iflag;
3134
3135 epd_pool = &phba->epd_pool;
3136 qp = &phba->sli4_hba.hdwq[0];
3137
3138 spin_lock_init(&epd_pool->lock);
3139 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3140 spin_lock(&epd_pool->lock);
3141 INIT_LIST_HEAD(&epd_pool->list);
3142 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3143 &qp->lpfc_io_buf_list_put, list) {
3144 list_move_tail(&lpfc_ncmd->list, &epd_pool->list);
3145 lpfc_ncmd->expedite = true;
3146 qp->put_io_bufs--;
3147 epd_pool->count++;
3148 if (epd_pool->count >= XRI_BATCH)
3149 break;
3150 }
3151 spin_unlock(&epd_pool->lock);
3152 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3153}
3154
3155/**
3156 * lpfc_destroy_expedite_pool - destroy expedite pool
3157 * @phba: pointer to lpfc hba data structure.
3158 *
3159 * This routine returns XRIs from expedite pool to lpfc_io_buf_list_put
3160 * of HWQ 0. Clear the mark.
3161 **/
3999df75 3162static void lpfc_destroy_expedite_pool(struct lpfc_hba *phba)
c490850a
JS
3163{
3164 struct lpfc_sli4_hdw_queue *qp;
3165 struct lpfc_io_buf *lpfc_ncmd;
3166 struct lpfc_io_buf *lpfc_ncmd_next;
3167 struct lpfc_epd_pool *epd_pool;
3168 unsigned long iflag;
3169
3170 epd_pool = &phba->epd_pool;
3171 qp = &phba->sli4_hba.hdwq[0];
3172
3173 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3174 spin_lock(&epd_pool->lock);
3175 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3176 &epd_pool->list, list) {
3177 list_move_tail(&lpfc_ncmd->list,
3178 &qp->lpfc_io_buf_list_put);
3179 lpfc_ncmd->flags = false;
3180 qp->put_io_bufs++;
3181 epd_pool->count--;
3182 }
3183 spin_unlock(&epd_pool->lock);
3184 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3185}
3186
3187/**
3188 * lpfc_create_multixri_pools - create multi-XRI pools
3189 * @phba: pointer to lpfc hba data structure.
3190 *
3191 * This routine initialize public, private per HWQ. Then, move XRIs from
3192 * lpfc_io_buf_list_put to public pool. High and low watermark are also
3193 * Initialized.
3194 **/
3195void lpfc_create_multixri_pools(struct lpfc_hba *phba)
3196{
3197 u32 i, j;
3198 u32 hwq_count;
3199 u32 count_per_hwq;
3200 struct lpfc_io_buf *lpfc_ncmd;
3201 struct lpfc_io_buf *lpfc_ncmd_next;
3202 unsigned long iflag;
3203 struct lpfc_sli4_hdw_queue *qp;
3204 struct lpfc_multixri_pool *multixri_pool;
3205 struct lpfc_pbl_pool *pbl_pool;
3206 struct lpfc_pvt_pool *pvt_pool;
3207
3208 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3209 "1234 num_hdw_queue=%d num_present_cpu=%d common_xri_cnt=%d\n",
3210 phba->cfg_hdw_queue, phba->sli4_hba.num_present_cpu,
3211 phba->sli4_hba.io_xri_cnt);
3212
3213 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3214 lpfc_create_expedite_pool(phba);
3215
3216 hwq_count = phba->cfg_hdw_queue;
3217 count_per_hwq = phba->sli4_hba.io_xri_cnt / hwq_count;
3218
3219 for (i = 0; i < hwq_count; i++) {
3220 multixri_pool = kzalloc(sizeof(*multixri_pool), GFP_KERNEL);
3221
3222 if (!multixri_pool) {
3223 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3224 "1238 Failed to allocate memory for "
3225 "multixri_pool\n");
3226
3227 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3228 lpfc_destroy_expedite_pool(phba);
3229
3230 j = 0;
3231 while (j < i) {
3232 qp = &phba->sli4_hba.hdwq[j];
3233 kfree(qp->p_multixri_pool);
3234 j++;
3235 }
3236 phba->cfg_xri_rebalancing = 0;
3237 return;
3238 }
3239
3240 qp = &phba->sli4_hba.hdwq[i];
3241 qp->p_multixri_pool = multixri_pool;
3242
3243 multixri_pool->xri_limit = count_per_hwq;
3244 multixri_pool->rrb_next_hwqid = i;
3245
3246 /* Deal with public free xri pool */
3247 pbl_pool = &multixri_pool->pbl_pool;
3248 spin_lock_init(&pbl_pool->lock);
3249 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3250 spin_lock(&pbl_pool->lock);
3251 INIT_LIST_HEAD(&pbl_pool->list);
3252 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3253 &qp->lpfc_io_buf_list_put, list) {
3254 list_move_tail(&lpfc_ncmd->list, &pbl_pool->list);
3255 qp->put_io_bufs--;
3256 pbl_pool->count++;
3257 }
3258 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3259 "1235 Moved %d buffers from PUT list over to pbl_pool[%d]\n",
3260 pbl_pool->count, i);
3261 spin_unlock(&pbl_pool->lock);
3262 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3263
3264 /* Deal with private free xri pool */
3265 pvt_pool = &multixri_pool->pvt_pool;
3266 pvt_pool->high_watermark = multixri_pool->xri_limit / 2;
3267 pvt_pool->low_watermark = XRI_BATCH;
3268 spin_lock_init(&pvt_pool->lock);
3269 spin_lock_irqsave(&pvt_pool->lock, iflag);
3270 INIT_LIST_HEAD(&pvt_pool->list);
3271 pvt_pool->count = 0;
3272 spin_unlock_irqrestore(&pvt_pool->lock, iflag);
3273 }
3274}
3275
3276/**
3277 * lpfc_destroy_multixri_pools - destroy multi-XRI pools
3278 * @phba: pointer to lpfc hba data structure.
3279 *
3280 * This routine returns XRIs from public/private to lpfc_io_buf_list_put.
3281 **/
3999df75 3282static void lpfc_destroy_multixri_pools(struct lpfc_hba *phba)
c490850a
JS
3283{
3284 u32 i;
3285 u32 hwq_count;
3286 struct lpfc_io_buf *lpfc_ncmd;
3287 struct lpfc_io_buf *lpfc_ncmd_next;
3288 unsigned long iflag;
3289 struct lpfc_sli4_hdw_queue *qp;
3290 struct lpfc_multixri_pool *multixri_pool;
3291 struct lpfc_pbl_pool *pbl_pool;
3292 struct lpfc_pvt_pool *pvt_pool;
3293
3294 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3295 lpfc_destroy_expedite_pool(phba);
3296
c00f62e6
JS
3297 if (!(phba->pport->load_flag & FC_UNLOADING))
3298 lpfc_sli_flush_io_rings(phba);
c66a9197 3299
c490850a
JS
3300 hwq_count = phba->cfg_hdw_queue;
3301
3302 for (i = 0; i < hwq_count; i++) {
3303 qp = &phba->sli4_hba.hdwq[i];
3304 multixri_pool = qp->p_multixri_pool;
3305 if (!multixri_pool)
3306 continue;
3307
3308 qp->p_multixri_pool = NULL;
3309
3310 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3311
3312 /* Deal with public free xri pool */
3313 pbl_pool = &multixri_pool->pbl_pool;
3314 spin_lock(&pbl_pool->lock);
3315
3316 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3317 "1236 Moving %d buffers from pbl_pool[%d] TO PUT list\n",
3318 pbl_pool->count, i);
3319
3320 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3321 &pbl_pool->list, list) {
3322 list_move_tail(&lpfc_ncmd->list,
3323 &qp->lpfc_io_buf_list_put);
3324 qp->put_io_bufs++;
3325 pbl_pool->count--;
3326 }
3327
3328 INIT_LIST_HEAD(&pbl_pool->list);
3329 pbl_pool->count = 0;
3330
3331 spin_unlock(&pbl_pool->lock);
3332
3333 /* Deal with private free xri pool */
3334 pvt_pool = &multixri_pool->pvt_pool;
3335 spin_lock(&pvt_pool->lock);
3336
3337 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3338 "1237 Moving %d buffers from pvt_pool[%d] TO PUT list\n",
3339 pvt_pool->count, i);
3340
3341 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3342 &pvt_pool->list, list) {
3343 list_move_tail(&lpfc_ncmd->list,
3344 &qp->lpfc_io_buf_list_put);
3345 qp->put_io_bufs++;
3346 pvt_pool->count--;
3347 }
3348
3349 INIT_LIST_HEAD(&pvt_pool->list);
3350 pvt_pool->count = 0;
3351
3352 spin_unlock(&pvt_pool->lock);
3353 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3354
3355 kfree(multixri_pool);
3356 }
3357}
3358
e59058c4 3359/**
3621a710 3360 * lpfc_online - Initialize and bring a HBA online
e59058c4
JS
3361 * @phba: pointer to lpfc hba data structure.
3362 *
3363 * This routine initializes the HBA and brings a HBA online. During this
3364 * process, the management interface is blocked to prevent user space access
3365 * to the HBA interfering with the driver initialization.
3366 *
3367 * Return codes
3368 * 0 - successful
3369 * 1 - failed
3370 **/
dea3101e 3371int
2e0fef85 3372lpfc_online(struct lpfc_hba *phba)
dea3101e 3373{
372bd282 3374 struct lpfc_vport *vport;
549e55cd 3375 struct lpfc_vport **vports;
a145fda3 3376 int i, error = 0;
16a3a208 3377 bool vpis_cleared = false;
2e0fef85 3378
dea3101e 3379 if (!phba)
3380 return 0;
372bd282 3381 vport = phba->pport;
dea3101e 3382
2e0fef85 3383 if (!(vport->fc_flag & FC_OFFLINE_MODE))
dea3101e 3384 return 0;
3385
ed957684 3386 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
e8b62011 3387 "0458 Bring Adapter online\n");
dea3101e 3388
618a5230 3389 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
46fa311e 3390
da0436e9
JS
3391 if (phba->sli_rev == LPFC_SLI_REV4) {
3392 if (lpfc_sli4_hba_setup(phba)) { /* Initialize SLI4 HBA */
3393 lpfc_unblock_mgmt_io(phba);
3394 return 1;
3395 }
16a3a208
JS
3396 spin_lock_irq(&phba->hbalock);
3397 if (!phba->sli4_hba.max_cfg_param.vpi_used)
3398 vpis_cleared = true;
3399 spin_unlock_irq(&phba->hbalock);
a145fda3
DK
3400
3401 /* Reestablish the local initiator port.
3402 * The offline process destroyed the previous lport.
3403 */
3404 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME &&
3405 !phba->nvmet_support) {
3406 error = lpfc_nvme_create_localport(phba->pport);
3407 if (error)
372c187b 3408 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
a145fda3
DK
3409 "6132 NVME restore reg failed "
3410 "on nvmei error x%x\n", error);
3411 }
da0436e9 3412 } else {
895427bd 3413 lpfc_sli_queue_init(phba);
da0436e9
JS
3414 if (lpfc_sli_hba_setup(phba)) { /* Initialize SLI2/SLI3 HBA */
3415 lpfc_unblock_mgmt_io(phba);
3416 return 1;
3417 }
46fa311e 3418 }
dea3101e 3419
549e55cd 3420 vports = lpfc_create_vport_work_array(phba);
aeb6641f 3421 if (vports != NULL) {
da0436e9 3422 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
549e55cd
JS
3423 struct Scsi_Host *shost;
3424 shost = lpfc_shost_from_vport(vports[i]);
3425 spin_lock_irq(shost->host_lock);
3426 vports[i]->fc_flag &= ~FC_OFFLINE_MODE;
3427 if (phba->sli3_options & LPFC_SLI3_NPIV_ENABLED)
3428 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
16a3a208 3429 if (phba->sli_rev == LPFC_SLI_REV4) {
1c6834a7 3430 vports[i]->fc_flag |= FC_VPORT_NEEDS_INIT_VPI;
16a3a208
JS
3431 if ((vpis_cleared) &&
3432 (vports[i]->port_type !=
3433 LPFC_PHYSICAL_PORT))
3434 vports[i]->vpi = 0;
3435 }
549e55cd
JS
3436 spin_unlock_irq(shost->host_lock);
3437 }
aeb6641f
AB
3438 }
3439 lpfc_destroy_vport_work_array(phba, vports);
dea3101e 3440
c490850a
JS
3441 if (phba->cfg_xri_rebalancing)
3442 lpfc_create_multixri_pools(phba);
3443
93a4d6f4
JS
3444 lpfc_cpuhp_add(phba);
3445
46fa311e 3446 lpfc_unblock_mgmt_io(phba);
dea3101e 3447 return 0;
3448}
3449
e59058c4 3450/**
3621a710 3451 * lpfc_unblock_mgmt_io - Mark a HBA's management interface to be not blocked
e59058c4
JS
3452 * @phba: pointer to lpfc hba data structure.
3453 *
3454 * This routine marks a HBA's management interface as not blocked. Once the
3455 * HBA's management interface is marked as not blocked, all the user space
3456 * access to the HBA, whether they are from sysfs interface or libdfc
3457 * interface will be allowed. The HBA is set to block the management interface
3458 * when the driver prepares the HBA interface for online or offline and then
3459 * set to unblock the management interface afterwards.
3460 **/
46fa311e
JS
3461void
3462lpfc_unblock_mgmt_io(struct lpfc_hba * phba)
3463{
3464 unsigned long iflag;
3465
2e0fef85
JS
3466 spin_lock_irqsave(&phba->hbalock, iflag);
3467 phba->sli.sli_flag &= ~LPFC_BLOCK_MGMT_IO;
3468 spin_unlock_irqrestore(&phba->hbalock, iflag);
46fa311e
JS
3469}
3470
e59058c4 3471/**
3621a710 3472 * lpfc_offline_prep - Prepare a HBA to be brought offline
e59058c4 3473 * @phba: pointer to lpfc hba data structure.
fe614acd 3474 * @mbx_action: flag for mailbox shutdown action.
e59058c4
JS
3475 *
3476 * This routine is invoked to prepare a HBA to be brought offline. It performs
3477 * unregistration login to all the nodes on all vports and flushes the mailbox
3478 * queue to make it ready to be brought offline.
3479 **/
46fa311e 3480void
618a5230 3481lpfc_offline_prep(struct lpfc_hba *phba, int mbx_action)
46fa311e 3482{
2e0fef85 3483 struct lpfc_vport *vport = phba->pport;
46fa311e 3484 struct lpfc_nodelist *ndlp, *next_ndlp;
87af33fe 3485 struct lpfc_vport **vports;
72100cc4 3486 struct Scsi_Host *shost;
87af33fe 3487 int i;
dea3101e 3488
2e0fef85 3489 if (vport->fc_flag & FC_OFFLINE_MODE)
46fa311e 3490 return;
dea3101e 3491
618a5230 3492 lpfc_block_mgmt_io(phba, mbx_action);
dea3101e 3493
3494 lpfc_linkdown(phba);
3495
87af33fe
JS
3496 /* Issue an unreg_login to all nodes on all vports */
3497 vports = lpfc_create_vport_work_array(phba);
3498 if (vports != NULL) {
da0436e9 3499 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
a8adb832
JS
3500 if (vports[i]->load_flag & FC_UNLOADING)
3501 continue;
72100cc4
JS
3502 shost = lpfc_shost_from_vport(vports[i]);
3503 spin_lock_irq(shost->host_lock);
c868595d 3504 vports[i]->vpi_state &= ~LPFC_VPI_REGISTERED;
695a814e
JS
3505 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
3506 vports[i]->fc_flag &= ~FC_VFI_REGISTERED;
72100cc4 3507 spin_unlock_irq(shost->host_lock);
695a814e 3508
87af33fe
JS
3509 shost = lpfc_shost_from_vport(vports[i]);
3510 list_for_each_entry_safe(ndlp, next_ndlp,
3511 &vports[i]->fc_nodes,
3512 nlp_listp) {
0f154226
JS
3513 if ((!NLP_CHK_NODE_ACT(ndlp)) ||
3514 ndlp->nlp_state == NLP_STE_UNUSED_NODE) {
3515 /* Driver must assume RPI is invalid for
3516 * any unused or inactive node.
3517 */
3518 ndlp->nlp_rpi = LPFC_RPI_ALLOC_ERROR;
87af33fe 3519 continue;
0f154226
JS
3520 }
3521
87af33fe
JS
3522 if (ndlp->nlp_type & NLP_FABRIC) {
3523 lpfc_disc_state_machine(vports[i], ndlp,
3524 NULL, NLP_EVT_DEVICE_RECOVERY);
3525 lpfc_disc_state_machine(vports[i], ndlp,
3526 NULL, NLP_EVT_DEVICE_RM);
3527 }
3528 spin_lock_irq(shost->host_lock);
3529 ndlp->nlp_flag &= ~NLP_NPR_ADISC;
401ee0c1 3530 spin_unlock_irq(shost->host_lock);
6b5151fd
JS
3531 /*
3532 * Whenever an SLI4 port goes offline, free the
401ee0c1
JS
3533 * RPI. Get a new RPI when the adapter port
3534 * comes back online.
6b5151fd 3535 */
be6bb941 3536 if (phba->sli_rev == LPFC_SLI_REV4) {
0f154226
JS
3537 lpfc_printf_vlog(ndlp->vport, KERN_INFO,
3538 LOG_NODE | LOG_DISCOVERY,
3539 "0011 Free RPI x%x on "
3540 "ndlp:x%px did x%x "
3541 "usgmap:x%x\n",
3542 ndlp->nlp_rpi, ndlp,
3543 ndlp->nlp_DID,
3544 ndlp->nlp_usg_map);
6b5151fd 3545 lpfc_sli4_free_rpi(phba, ndlp->nlp_rpi);
0f154226 3546 ndlp->nlp_rpi = LPFC_RPI_ALLOC_ERROR;
be6bb941 3547 }
87af33fe
JS
3548 lpfc_unreg_rpi(vports[i], ndlp);
3549 }
3550 }
3551 }
09372820 3552 lpfc_destroy_vport_work_array(phba, vports);
dea3101e 3553
618a5230 3554 lpfc_sli_mbox_sys_shutdown(phba, mbx_action);
f485c18d
DK
3555
3556 if (phba->wq)
3557 flush_workqueue(phba->wq);
46fa311e
JS
3558}
3559
e59058c4 3560/**
3621a710 3561 * lpfc_offline - Bring a HBA offline
e59058c4
JS
3562 * @phba: pointer to lpfc hba data structure.
3563 *
3564 * This routine actually brings a HBA offline. It stops all the timers
3565 * associated with the HBA, brings down the SLI layer, and eventually
3566 * marks the HBA as in offline state for the upper layer protocol.
3567 **/
46fa311e 3568void
2e0fef85 3569lpfc_offline(struct lpfc_hba *phba)
46fa311e 3570{
549e55cd
JS
3571 struct Scsi_Host *shost;
3572 struct lpfc_vport **vports;
3573 int i;
46fa311e 3574
549e55cd 3575 if (phba->pport->fc_flag & FC_OFFLINE_MODE)
46fa311e 3576 return;
688a8863 3577
da0436e9
JS
3578 /* stop port and all timers associated with this hba */
3579 lpfc_stop_port(phba);
4b40d02b
DK
3580
3581 /* Tear down the local and target port registrations. The
3582 * nvme transports need to cleanup.
3583 */
3584 lpfc_nvmet_destroy_targetport(phba);
3585 lpfc_nvme_destroy_localport(phba->pport);
3586
51ef4c26
JS
3587 vports = lpfc_create_vport_work_array(phba);
3588 if (vports != NULL)
da0436e9 3589 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
51ef4c26 3590 lpfc_stop_vport_timers(vports[i]);
09372820 3591 lpfc_destroy_vport_work_array(phba, vports);
92d7f7b0 3592 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
e8b62011 3593 "0460 Bring Adapter offline\n");
dea3101e 3594 /* Bring down the SLI Layer and cleanup. The HBA is offline
3595 now. */
3596 lpfc_sli_hba_down(phba);
92d7f7b0 3597 spin_lock_irq(&phba->hbalock);
7054a606 3598 phba->work_ha = 0;
92d7f7b0 3599 spin_unlock_irq(&phba->hbalock);
549e55cd
JS
3600 vports = lpfc_create_vport_work_array(phba);
3601 if (vports != NULL)
da0436e9 3602 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
549e55cd 3603 shost = lpfc_shost_from_vport(vports[i]);
549e55cd
JS
3604 spin_lock_irq(shost->host_lock);
3605 vports[i]->work_port_events = 0;
3606 vports[i]->fc_flag |= FC_OFFLINE_MODE;
3607 spin_unlock_irq(shost->host_lock);
3608 }
09372820 3609 lpfc_destroy_vport_work_array(phba, vports);
93a4d6f4 3610 __lpfc_cpuhp_remove(phba);
c490850a
JS
3611
3612 if (phba->cfg_xri_rebalancing)
3613 lpfc_destroy_multixri_pools(phba);
dea3101e 3614}
3615
e59058c4 3616/**
3621a710 3617 * lpfc_scsi_free - Free all the SCSI buffers and IOCBs from driver lists
e59058c4
JS
3618 * @phba: pointer to lpfc hba data structure.
3619 *
3620 * This routine is to free all the SCSI buffers and IOCBs from the driver
3621 * list back to kernel. It is called from lpfc_pci_remove_one to free
3622 * the internal resources before the device is removed from the system.
e59058c4 3623 **/
8a9d2e80 3624static void
2e0fef85 3625lpfc_scsi_free(struct lpfc_hba *phba)
dea3101e 3626{
c490850a 3627 struct lpfc_io_buf *sb, *sb_next;
dea3101e 3628
895427bd
JS
3629 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
3630 return;
3631
2e0fef85 3632 spin_lock_irq(&phba->hbalock);
a40fc5f0 3633
dea3101e 3634 /* Release all the lpfc_scsi_bufs maintained by this host. */
a40fc5f0
JS
3635
3636 spin_lock(&phba->scsi_buf_list_put_lock);
3637 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_put,
3638 list) {
dea3101e 3639 list_del(&sb->list);
771db5c0 3640 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
92d7f7b0 3641 sb->dma_handle);
dea3101e 3642 kfree(sb);
3643 phba->total_scsi_bufs--;
3644 }
a40fc5f0
JS
3645 spin_unlock(&phba->scsi_buf_list_put_lock);
3646
3647 spin_lock(&phba->scsi_buf_list_get_lock);
3648 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_get,
3649 list) {
dea3101e 3650 list_del(&sb->list);
771db5c0 3651 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
92d7f7b0 3652 sb->dma_handle);
dea3101e 3653 kfree(sb);
3654 phba->total_scsi_bufs--;
3655 }
a40fc5f0 3656 spin_unlock(&phba->scsi_buf_list_get_lock);
2e0fef85 3657 spin_unlock_irq(&phba->hbalock);
8a9d2e80 3658}
0794d601 3659
895427bd 3660/**
5e5b511d 3661 * lpfc_io_free - Free all the IO buffers and IOCBs from driver lists
895427bd
JS
3662 * @phba: pointer to lpfc hba data structure.
3663 *
0794d601 3664 * This routine is to free all the IO buffers and IOCBs from the driver
895427bd
JS
3665 * list back to kernel. It is called from lpfc_pci_remove_one to free
3666 * the internal resources before the device is removed from the system.
3667 **/
c490850a 3668void
5e5b511d 3669lpfc_io_free(struct lpfc_hba *phba)
895427bd 3670{
c490850a 3671 struct lpfc_io_buf *lpfc_ncmd, *lpfc_ncmd_next;
5e5b511d
JS
3672 struct lpfc_sli4_hdw_queue *qp;
3673 int idx;
895427bd 3674
5e5b511d
JS
3675 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3676 qp = &phba->sli4_hba.hdwq[idx];
3677 /* Release all the lpfc_nvme_bufs maintained by this host. */
3678 spin_lock(&qp->io_buf_list_put_lock);
3679 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3680 &qp->lpfc_io_buf_list_put,
3681 list) {
3682 list_del(&lpfc_ncmd->list);
3683 qp->put_io_bufs--;
3684 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3685 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
d79c9e9d
JS
3686 if (phba->cfg_xpsgl && !phba->nvmet_support)
3687 lpfc_put_sgl_per_hdwq(phba, lpfc_ncmd);
3688 lpfc_put_cmd_rsp_buf_per_hdwq(phba, lpfc_ncmd);
5e5b511d
JS
3689 kfree(lpfc_ncmd);
3690 qp->total_io_bufs--;
3691 }
3692 spin_unlock(&qp->io_buf_list_put_lock);
3693
3694 spin_lock(&qp->io_buf_list_get_lock);
3695 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3696 &qp->lpfc_io_buf_list_get,
3697 list) {
3698 list_del(&lpfc_ncmd->list);
3699 qp->get_io_bufs--;
3700 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3701 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
d79c9e9d
JS
3702 if (phba->cfg_xpsgl && !phba->nvmet_support)
3703 lpfc_put_sgl_per_hdwq(phba, lpfc_ncmd);
3704 lpfc_put_cmd_rsp_buf_per_hdwq(phba, lpfc_ncmd);
5e5b511d
JS
3705 kfree(lpfc_ncmd);
3706 qp->total_io_bufs--;
3707 }
3708 spin_unlock(&qp->io_buf_list_get_lock);
895427bd 3709 }
895427bd 3710}
0794d601 3711
8a9d2e80 3712/**
895427bd 3713 * lpfc_sli4_els_sgl_update - update ELS xri-sgl sizing and mapping
8a9d2e80
JS
3714 * @phba: pointer to lpfc hba data structure.
3715 *
3716 * This routine first calculates the sizes of the current els and allocated
3717 * scsi sgl lists, and then goes through all sgls to updates the physical
3718 * XRIs assigned due to port function reset. During port initialization, the
3719 * current els and allocated scsi sgl lists are 0s.
3720 *
3721 * Return codes
3722 * 0 - successful (for now, it always returns 0)
3723 **/
3724int
895427bd 3725lpfc_sli4_els_sgl_update(struct lpfc_hba *phba)
8a9d2e80
JS
3726{
3727 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
895427bd 3728 uint16_t i, lxri, xri_cnt, els_xri_cnt;
8a9d2e80 3729 LIST_HEAD(els_sgl_list);
8a9d2e80
JS
3730 int rc;
3731
3732 /*
3733 * update on pci function's els xri-sgl list
3734 */
3735 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
895427bd 3736
8a9d2e80
JS
3737 if (els_xri_cnt > phba->sli4_hba.els_xri_cnt) {
3738 /* els xri-sgl expanded */
3739 xri_cnt = els_xri_cnt - phba->sli4_hba.els_xri_cnt;
3740 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3741 "3157 ELS xri-sgl count increased from "
3742 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3743 els_xri_cnt);
3744 /* allocate the additional els sgls */
3745 for (i = 0; i < xri_cnt; i++) {
3746 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3747 GFP_KERNEL);
3748 if (sglq_entry == NULL) {
372c187b
DK
3749 lpfc_printf_log(phba, KERN_ERR,
3750 LOG_TRACE_EVENT,
8a9d2e80
JS
3751 "2562 Failure to allocate an "
3752 "ELS sgl entry:%d\n", i);
3753 rc = -ENOMEM;
3754 goto out_free_mem;
3755 }
3756 sglq_entry->buff_type = GEN_BUFF_TYPE;
3757 sglq_entry->virt = lpfc_mbuf_alloc(phba, 0,
3758 &sglq_entry->phys);
3759 if (sglq_entry->virt == NULL) {
3760 kfree(sglq_entry);
372c187b
DK
3761 lpfc_printf_log(phba, KERN_ERR,
3762 LOG_TRACE_EVENT,
8a9d2e80
JS
3763 "2563 Failure to allocate an "
3764 "ELS mbuf:%d\n", i);
3765 rc = -ENOMEM;
3766 goto out_free_mem;
3767 }
3768 sglq_entry->sgl = sglq_entry->virt;
3769 memset(sglq_entry->sgl, 0, LPFC_BPL_SIZE);
3770 sglq_entry->state = SGL_FREED;
3771 list_add_tail(&sglq_entry->list, &els_sgl_list);
3772 }
38c20673 3773 spin_lock_irq(&phba->hbalock);
895427bd
JS
3774 spin_lock(&phba->sli4_hba.sgl_list_lock);
3775 list_splice_init(&els_sgl_list,
3776 &phba->sli4_hba.lpfc_els_sgl_list);
3777 spin_unlock(&phba->sli4_hba.sgl_list_lock);
38c20673 3778 spin_unlock_irq(&phba->hbalock);
8a9d2e80
JS
3779 } else if (els_xri_cnt < phba->sli4_hba.els_xri_cnt) {
3780 /* els xri-sgl shrinked */
3781 xri_cnt = phba->sli4_hba.els_xri_cnt - els_xri_cnt;
3782 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3783 "3158 ELS xri-sgl count decreased from "
3784 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3785 els_xri_cnt);
3786 spin_lock_irq(&phba->hbalock);
895427bd
JS
3787 spin_lock(&phba->sli4_hba.sgl_list_lock);
3788 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list,
3789 &els_sgl_list);
8a9d2e80
JS
3790 /* release extra els sgls from list */
3791 for (i = 0; i < xri_cnt; i++) {
3792 list_remove_head(&els_sgl_list,
3793 sglq_entry, struct lpfc_sglq, list);
3794 if (sglq_entry) {
895427bd
JS
3795 __lpfc_mbuf_free(phba, sglq_entry->virt,
3796 sglq_entry->phys);
8a9d2e80
JS
3797 kfree(sglq_entry);
3798 }
3799 }
895427bd
JS
3800 list_splice_init(&els_sgl_list,
3801 &phba->sli4_hba.lpfc_els_sgl_list);
3802 spin_unlock(&phba->sli4_hba.sgl_list_lock);
8a9d2e80
JS
3803 spin_unlock_irq(&phba->hbalock);
3804 } else
3805 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3806 "3163 ELS xri-sgl count unchanged: %d\n",
3807 els_xri_cnt);
3808 phba->sli4_hba.els_xri_cnt = els_xri_cnt;
3809
3810 /* update xris to els sgls on the list */
3811 sglq_entry = NULL;
3812 sglq_entry_next = NULL;
3813 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
895427bd 3814 &phba->sli4_hba.lpfc_els_sgl_list, list) {
8a9d2e80
JS
3815 lxri = lpfc_sli4_next_xritag(phba);
3816 if (lxri == NO_XRI) {
372c187b
DK
3817 lpfc_printf_log(phba, KERN_ERR,
3818 LOG_TRACE_EVENT,
8a9d2e80
JS
3819 "2400 Failed to allocate xri for "
3820 "ELS sgl\n");
3821 rc = -ENOMEM;
3822 goto out_free_mem;
3823 }
3824 sglq_entry->sli4_lxritag = lxri;
3825 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3826 }
895427bd
JS
3827 return 0;
3828
3829out_free_mem:
3830 lpfc_free_els_sgl_list(phba);
3831 return rc;
3832}
3833
f358dd0c
JS
3834/**
3835 * lpfc_sli4_nvmet_sgl_update - update xri-sgl sizing and mapping
3836 * @phba: pointer to lpfc hba data structure.
3837 *
3838 * This routine first calculates the sizes of the current els and allocated
3839 * scsi sgl lists, and then goes through all sgls to updates the physical
3840 * XRIs assigned due to port function reset. During port initialization, the
3841 * current els and allocated scsi sgl lists are 0s.
3842 *
3843 * Return codes
3844 * 0 - successful (for now, it always returns 0)
3845 **/
3846int
3847lpfc_sli4_nvmet_sgl_update(struct lpfc_hba *phba)
3848{
3849 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
3850 uint16_t i, lxri, xri_cnt, els_xri_cnt;
6c621a22 3851 uint16_t nvmet_xri_cnt;
f358dd0c
JS
3852 LIST_HEAD(nvmet_sgl_list);
3853 int rc;
3854
3855 /*
3856 * update on pci function's nvmet xri-sgl list
3857 */
3858 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
61f3d4bf 3859
6c621a22
JS
3860 /* For NVMET, ALL remaining XRIs are dedicated for IO processing */
3861 nvmet_xri_cnt = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
f358dd0c
JS
3862 if (nvmet_xri_cnt > phba->sli4_hba.nvmet_xri_cnt) {
3863 /* els xri-sgl expanded */
3864 xri_cnt = nvmet_xri_cnt - phba->sli4_hba.nvmet_xri_cnt;
3865 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3866 "6302 NVMET xri-sgl cnt grew from %d to %d\n",
3867 phba->sli4_hba.nvmet_xri_cnt, nvmet_xri_cnt);
3868 /* allocate the additional nvmet sgls */
3869 for (i = 0; i < xri_cnt; i++) {
3870 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3871 GFP_KERNEL);
3872 if (sglq_entry == NULL) {
372c187b
DK
3873 lpfc_printf_log(phba, KERN_ERR,
3874 LOG_TRACE_EVENT,
f358dd0c
JS
3875 "6303 Failure to allocate an "
3876 "NVMET sgl entry:%d\n", i);
3877 rc = -ENOMEM;
3878 goto out_free_mem;
3879 }
3880 sglq_entry->buff_type = NVMET_BUFF_TYPE;
3881 sglq_entry->virt = lpfc_nvmet_buf_alloc(phba, 0,
3882 &sglq_entry->phys);
3883 if (sglq_entry->virt == NULL) {
3884 kfree(sglq_entry);
372c187b
DK
3885 lpfc_printf_log(phba, KERN_ERR,
3886 LOG_TRACE_EVENT,
f358dd0c
JS
3887 "6304 Failure to allocate an "
3888 "NVMET buf:%d\n", i);
3889 rc = -ENOMEM;
3890 goto out_free_mem;
3891 }
3892 sglq_entry->sgl = sglq_entry->virt;
3893 memset(sglq_entry->sgl, 0,
3894 phba->cfg_sg_dma_buf_size);
3895 sglq_entry->state = SGL_FREED;
3896 list_add_tail(&sglq_entry->list, &nvmet_sgl_list);
3897 }
3898 spin_lock_irq(&phba->hbalock);
3899 spin_lock(&phba->sli4_hba.sgl_list_lock);
3900 list_splice_init(&nvmet_sgl_list,
3901 &phba->sli4_hba.lpfc_nvmet_sgl_list);
3902 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3903 spin_unlock_irq(&phba->hbalock);
3904 } else if (nvmet_xri_cnt < phba->sli4_hba.nvmet_xri_cnt) {
3905 /* nvmet xri-sgl shrunk */
3906 xri_cnt = phba->sli4_hba.nvmet_xri_cnt - nvmet_xri_cnt;
3907 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3908 "6305 NVMET xri-sgl count decreased from "
3909 "%d to %d\n", phba->sli4_hba.nvmet_xri_cnt,
3910 nvmet_xri_cnt);
3911 spin_lock_irq(&phba->hbalock);
3912 spin_lock(&phba->sli4_hba.sgl_list_lock);
3913 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list,
3914 &nvmet_sgl_list);
3915 /* release extra nvmet sgls from list */
3916 for (i = 0; i < xri_cnt; i++) {
3917 list_remove_head(&nvmet_sgl_list,
3918 sglq_entry, struct lpfc_sglq, list);
3919 if (sglq_entry) {
3920 lpfc_nvmet_buf_free(phba, sglq_entry->virt,
3921 sglq_entry->phys);
3922 kfree(sglq_entry);
3923 }
3924 }
3925 list_splice_init(&nvmet_sgl_list,
3926 &phba->sli4_hba.lpfc_nvmet_sgl_list);
3927 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3928 spin_unlock_irq(&phba->hbalock);
3929 } else
3930 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3931 "6306 NVMET xri-sgl count unchanged: %d\n",
3932 nvmet_xri_cnt);
3933 phba->sli4_hba.nvmet_xri_cnt = nvmet_xri_cnt;
3934
3935 /* update xris to nvmet sgls on the list */
3936 sglq_entry = NULL;
3937 sglq_entry_next = NULL;
3938 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
3939 &phba->sli4_hba.lpfc_nvmet_sgl_list, list) {
3940 lxri = lpfc_sli4_next_xritag(phba);
3941 if (lxri == NO_XRI) {
372c187b
DK
3942 lpfc_printf_log(phba, KERN_ERR,
3943 LOG_TRACE_EVENT,
f358dd0c
JS
3944 "6307 Failed to allocate xri for "
3945 "NVMET sgl\n");
3946 rc = -ENOMEM;
3947 goto out_free_mem;
3948 }
3949 sglq_entry->sli4_lxritag = lxri;
3950 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3951 }
3952 return 0;
3953
3954out_free_mem:
3955 lpfc_free_nvmet_sgl_list(phba);
3956 return rc;
3957}
3958
5e5b511d
JS
3959int
3960lpfc_io_buf_flush(struct lpfc_hba *phba, struct list_head *cbuf)
3961{
3962 LIST_HEAD(blist);
3963 struct lpfc_sli4_hdw_queue *qp;
c490850a
JS
3964 struct lpfc_io_buf *lpfc_cmd;
3965 struct lpfc_io_buf *iobufp, *prev_iobufp;
5e5b511d
JS
3966 int idx, cnt, xri, inserted;
3967
3968 cnt = 0;
3969 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3970 qp = &phba->sli4_hba.hdwq[idx];
3971 spin_lock_irq(&qp->io_buf_list_get_lock);
3972 spin_lock(&qp->io_buf_list_put_lock);
3973
3974 /* Take everything off the get and put lists */
3975 list_splice_init(&qp->lpfc_io_buf_list_get, &blist);
3976 list_splice(&qp->lpfc_io_buf_list_put, &blist);
3977 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_get);
3978 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_put);
3979 cnt += qp->get_io_bufs + qp->put_io_bufs;
3980 qp->get_io_bufs = 0;
3981 qp->put_io_bufs = 0;
3982 qp->total_io_bufs = 0;
3983 spin_unlock(&qp->io_buf_list_put_lock);
3984 spin_unlock_irq(&qp->io_buf_list_get_lock);
3985 }
3986
3987 /*
3988 * Take IO buffers off blist and put on cbuf sorted by XRI.
3989 * This is because POST_SGL takes a sequential range of XRIs
3990 * to post to the firmware.
3991 */
3992 for (idx = 0; idx < cnt; idx++) {
c490850a 3993 list_remove_head(&blist, lpfc_cmd, struct lpfc_io_buf, list);
5e5b511d
JS
3994 if (!lpfc_cmd)
3995 return cnt;
3996 if (idx == 0) {
3997 list_add_tail(&lpfc_cmd->list, cbuf);
3998 continue;
3999 }
4000 xri = lpfc_cmd->cur_iocbq.sli4_xritag;
4001 inserted = 0;
4002 prev_iobufp = NULL;
4003 list_for_each_entry(iobufp, cbuf, list) {
4004 if (xri < iobufp->cur_iocbq.sli4_xritag) {
4005 if (prev_iobufp)
4006 list_add(&lpfc_cmd->list,
4007 &prev_iobufp->list);
4008 else
4009 list_add(&lpfc_cmd->list, cbuf);
4010 inserted = 1;
4011 break;
4012 }
4013 prev_iobufp = iobufp;
4014 }
4015 if (!inserted)
4016 list_add_tail(&lpfc_cmd->list, cbuf);
4017 }
4018 return cnt;
4019}
4020
4021int
4022lpfc_io_buf_replenish(struct lpfc_hba *phba, struct list_head *cbuf)
4023{
4024 struct lpfc_sli4_hdw_queue *qp;
c490850a 4025 struct lpfc_io_buf *lpfc_cmd;
5e5b511d
JS
4026 int idx, cnt;
4027
4028 qp = phba->sli4_hba.hdwq;
4029 cnt = 0;
4030 while (!list_empty(cbuf)) {
4031 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
4032 list_remove_head(cbuf, lpfc_cmd,
c490850a 4033 struct lpfc_io_buf, list);
5e5b511d
JS
4034 if (!lpfc_cmd)
4035 return cnt;
4036 cnt++;
4037 qp = &phba->sli4_hba.hdwq[idx];
1fbf9742
JS
4038 lpfc_cmd->hdwq_no = idx;
4039 lpfc_cmd->hdwq = qp;
5e5b511d
JS
4040 lpfc_cmd->cur_iocbq.wqe_cmpl = NULL;
4041 lpfc_cmd->cur_iocbq.iocb_cmpl = NULL;
4042 spin_lock(&qp->io_buf_list_put_lock);
4043 list_add_tail(&lpfc_cmd->list,
4044 &qp->lpfc_io_buf_list_put);
4045 qp->put_io_bufs++;
4046 qp->total_io_bufs++;
4047 spin_unlock(&qp->io_buf_list_put_lock);
4048 }
4049 }
4050 return cnt;
4051}
4052
895427bd 4053/**
5e5b511d 4054 * lpfc_sli4_io_sgl_update - update xri-sgl sizing and mapping
895427bd
JS
4055 * @phba: pointer to lpfc hba data structure.
4056 *
4057 * This routine first calculates the sizes of the current els and allocated
4058 * scsi sgl lists, and then goes through all sgls to updates the physical
4059 * XRIs assigned due to port function reset. During port initialization, the
4060 * current els and allocated scsi sgl lists are 0s.
4061 *
4062 * Return codes
4063 * 0 - successful (for now, it always returns 0)
4064 **/
4065int
5e5b511d 4066lpfc_sli4_io_sgl_update(struct lpfc_hba *phba)
895427bd 4067{
c490850a 4068 struct lpfc_io_buf *lpfc_ncmd = NULL, *lpfc_ncmd_next = NULL;
0794d601 4069 uint16_t i, lxri, els_xri_cnt;
5e5b511d
JS
4070 uint16_t io_xri_cnt, io_xri_max;
4071 LIST_HEAD(io_sgl_list);
0794d601 4072 int rc, cnt;
8a9d2e80 4073
895427bd 4074 /*
0794d601 4075 * update on pci function's allocated nvme xri-sgl list
895427bd 4076 */
8a9d2e80 4077
0794d601
JS
4078 /* maximum number of xris available for nvme buffers */
4079 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
5e5b511d
JS
4080 io_xri_max = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
4081 phba->sli4_hba.io_xri_max = io_xri_max;
895427bd 4082
e8c0a779 4083 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
0794d601
JS
4084 "6074 Current allocated XRI sgl count:%d, "
4085 "maximum XRI count:%d\n",
5e5b511d
JS
4086 phba->sli4_hba.io_xri_cnt,
4087 phba->sli4_hba.io_xri_max);
8a9d2e80 4088
5e5b511d 4089 cnt = lpfc_io_buf_flush(phba, &io_sgl_list);
8a9d2e80 4090
5e5b511d 4091 if (phba->sli4_hba.io_xri_cnt > phba->sli4_hba.io_xri_max) {
0794d601 4092 /* max nvme xri shrunk below the allocated nvme buffers */
5e5b511d
JS
4093 io_xri_cnt = phba->sli4_hba.io_xri_cnt -
4094 phba->sli4_hba.io_xri_max;
0794d601 4095 /* release the extra allocated nvme buffers */
5e5b511d
JS
4096 for (i = 0; i < io_xri_cnt; i++) {
4097 list_remove_head(&io_sgl_list, lpfc_ncmd,
c490850a 4098 struct lpfc_io_buf, list);
0794d601 4099 if (lpfc_ncmd) {
771db5c0 4100 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
0794d601
JS
4101 lpfc_ncmd->data,
4102 lpfc_ncmd->dma_handle);
4103 kfree(lpfc_ncmd);
a2fc4aef 4104 }
8a9d2e80 4105 }
5e5b511d 4106 phba->sli4_hba.io_xri_cnt -= io_xri_cnt;
8a9d2e80
JS
4107 }
4108
0794d601
JS
4109 /* update xris associated to remaining allocated nvme buffers */
4110 lpfc_ncmd = NULL;
4111 lpfc_ncmd_next = NULL;
5e5b511d 4112 phba->sli4_hba.io_xri_cnt = cnt;
0794d601 4113 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
5e5b511d 4114 &io_sgl_list, list) {
8a9d2e80
JS
4115 lxri = lpfc_sli4_next_xritag(phba);
4116 if (lxri == NO_XRI) {
372c187b
DK
4117 lpfc_printf_log(phba, KERN_ERR,
4118 LOG_TRACE_EVENT,
0794d601
JS
4119 "6075 Failed to allocate xri for "
4120 "nvme buffer\n");
8a9d2e80
JS
4121 rc = -ENOMEM;
4122 goto out_free_mem;
4123 }
0794d601
JS
4124 lpfc_ncmd->cur_iocbq.sli4_lxritag = lxri;
4125 lpfc_ncmd->cur_iocbq.sli4_xritag = phba->sli4_hba.xri_ids[lxri];
8a9d2e80 4126 }
5e5b511d 4127 cnt = lpfc_io_buf_replenish(phba, &io_sgl_list);
dea3101e 4128 return 0;
8a9d2e80
JS
4129
4130out_free_mem:
5e5b511d 4131 lpfc_io_free(phba);
8a9d2e80 4132 return rc;
dea3101e 4133}
4134
0794d601 4135/**
5e5b511d 4136 * lpfc_new_io_buf - IO buffer allocator for HBA with SLI4 IF spec
fe614acd
LJ
4137 * @phba: Pointer to lpfc hba data structure.
4138 * @num_to_alloc: The requested number of buffers to allocate.
0794d601
JS
4139 *
4140 * This routine allocates nvme buffers for device with SLI-4 interface spec,
4141 * the nvme buffer contains all the necessary information needed to initiate
4142 * an I/O. After allocating up to @num_to_allocate IO buffers and put
4143 * them on a list, it post them to the port by using SGL block post.
4144 *
4145 * Return codes:
5e5b511d 4146 * int - number of IO buffers that were allocated and posted.
0794d601
JS
4147 * 0 = failure, less than num_to_alloc is a partial failure.
4148 **/
4149int
5e5b511d 4150lpfc_new_io_buf(struct lpfc_hba *phba, int num_to_alloc)
0794d601 4151{
c490850a 4152 struct lpfc_io_buf *lpfc_ncmd;
0794d601
JS
4153 struct lpfc_iocbq *pwqeq;
4154 uint16_t iotag, lxri = 0;
4155 int bcnt, num_posted;
4156 LIST_HEAD(prep_nblist);
4157 LIST_HEAD(post_nblist);
4158 LIST_HEAD(nvme_nblist);
4159
5e5b511d 4160 phba->sli4_hba.io_xri_cnt = 0;
0794d601 4161 for (bcnt = 0; bcnt < num_to_alloc; bcnt++) {
7f9989ba 4162 lpfc_ncmd = kzalloc(sizeof(*lpfc_ncmd), GFP_KERNEL);
0794d601
JS
4163 if (!lpfc_ncmd)
4164 break;
4165 /*
4166 * Get memory from the pci pool to map the virt space to
4167 * pci bus space for an I/O. The DMA buffer includes the
4168 * number of SGE's necessary to support the sg_tablesize.
4169 */
a5c990ee
TM
4170 lpfc_ncmd->data = dma_pool_zalloc(phba->lpfc_sg_dma_buf_pool,
4171 GFP_KERNEL,
4172 &lpfc_ncmd->dma_handle);
0794d601
JS
4173 if (!lpfc_ncmd->data) {
4174 kfree(lpfc_ncmd);
4175 break;
4176 }
0794d601 4177
d79c9e9d
JS
4178 if (phba->cfg_xpsgl && !phba->nvmet_support) {
4179 INIT_LIST_HEAD(&lpfc_ncmd->dma_sgl_xtra_list);
4180 } else {
4181 /*
4182 * 4K Page alignment is CRITICAL to BlockGuard, double
4183 * check to be sure.
4184 */
4185 if ((phba->sli3_options & LPFC_SLI3_BG_ENABLED) &&
4186 (((unsigned long)(lpfc_ncmd->data) &
4187 (unsigned long)(SLI4_PAGE_SIZE - 1)) != 0)) {
372c187b
DK
4188 lpfc_printf_log(phba, KERN_ERR,
4189 LOG_TRACE_EVENT,
d79c9e9d
JS
4190 "3369 Memory alignment err: "
4191 "addr=%lx\n",
4192 (unsigned long)lpfc_ncmd->data);
4193 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4194 lpfc_ncmd->data,
4195 lpfc_ncmd->dma_handle);
4196 kfree(lpfc_ncmd);
4197 break;
4198 }
0794d601
JS
4199 }
4200
d79c9e9d
JS
4201 INIT_LIST_HEAD(&lpfc_ncmd->dma_cmd_rsp_list);
4202
0794d601
JS
4203 lxri = lpfc_sli4_next_xritag(phba);
4204 if (lxri == NO_XRI) {
4205 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4206 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
4207 kfree(lpfc_ncmd);
4208 break;
4209 }
4210 pwqeq = &lpfc_ncmd->cur_iocbq;
4211
4212 /* Allocate iotag for lpfc_ncmd->cur_iocbq. */
4213 iotag = lpfc_sli_next_iotag(phba, pwqeq);
4214 if (iotag == 0) {
4215 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4216 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
4217 kfree(lpfc_ncmd);
372c187b 4218 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0794d601
JS
4219 "6121 Failed to allocate IOTAG for"
4220 " XRI:0x%x\n", lxri);
4221 lpfc_sli4_free_xri(phba, lxri);
4222 break;
4223 }
4224 pwqeq->sli4_lxritag = lxri;
4225 pwqeq->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
4226 pwqeq->context1 = lpfc_ncmd;
4227
4228 /* Initialize local short-hand pointers. */
4229 lpfc_ncmd->dma_sgl = lpfc_ncmd->data;
4230 lpfc_ncmd->dma_phys_sgl = lpfc_ncmd->dma_handle;
4231 lpfc_ncmd->cur_iocbq.context1 = lpfc_ncmd;
c2017260 4232 spin_lock_init(&lpfc_ncmd->buf_lock);
0794d601
JS
4233
4234 /* add the nvme buffer to a post list */
4235 list_add_tail(&lpfc_ncmd->list, &post_nblist);
5e5b511d 4236 phba->sli4_hba.io_xri_cnt++;
0794d601
JS
4237 }
4238 lpfc_printf_log(phba, KERN_INFO, LOG_NVME,
4239 "6114 Allocate %d out of %d requested new NVME "
4240 "buffers\n", bcnt, num_to_alloc);
4241
4242 /* post the list of nvme buffer sgls to port if available */
4243 if (!list_empty(&post_nblist))
5e5b511d 4244 num_posted = lpfc_sli4_post_io_sgl_list(
0794d601
JS
4245 phba, &post_nblist, bcnt);
4246 else
4247 num_posted = 0;
4248
4249 return num_posted;
4250}
4251
96418b5e
JS
4252static uint64_t
4253lpfc_get_wwpn(struct lpfc_hba *phba)
4254{
4255 uint64_t wwn;
4256 int rc;
4257 LPFC_MBOXQ_t *mboxq;
4258 MAILBOX_t *mb;
4259
96418b5e
JS
4260 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
4261 GFP_KERNEL);
4262 if (!mboxq)
4263 return (uint64_t)-1;
4264
4265 /* First get WWN of HBA instance */
4266 lpfc_read_nv(phba, mboxq);
4267 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
4268 if (rc != MBX_SUCCESS) {
372c187b 4269 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
96418b5e
JS
4270 "6019 Mailbox failed , mbxCmd x%x "
4271 "READ_NV, mbxStatus x%x\n",
4272 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
4273 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
4274 mempool_free(mboxq, phba->mbox_mem_pool);
4275 return (uint64_t) -1;
4276 }
4277 mb = &mboxq->u.mb;
4278 memcpy(&wwn, (char *)mb->un.varRDnvp.portname, sizeof(uint64_t));
4279 /* wwn is WWPN of HBA instance */
4280 mempool_free(mboxq, phba->mbox_mem_pool);
4281 if (phba->sli_rev == LPFC_SLI_REV4)
4282 return be64_to_cpu(wwn);
4283 else
286871a6 4284 return rol64(wwn, 32);
96418b5e
JS
4285}
4286
e59058c4 4287/**
3621a710 4288 * lpfc_create_port - Create an FC port
e59058c4
JS
4289 * @phba: pointer to lpfc hba data structure.
4290 * @instance: a unique integer ID to this FC port.
4291 * @dev: pointer to the device data structure.
4292 *
4293 * This routine creates a FC port for the upper layer protocol. The FC port
4294 * can be created on top of either a physical port or a virtual port provided
4295 * by the HBA. This routine also allocates a SCSI host data structure (shost)
4296 * and associates the FC port created before adding the shost into the SCSI
4297 * layer.
4298 *
4299 * Return codes
4300 * @vport - pointer to the virtual N_Port data structure.
4301 * NULL - port create failed.
4302 **/
2e0fef85 4303struct lpfc_vport *
3de2a653 4304lpfc_create_port(struct lpfc_hba *phba, int instance, struct device *dev)
47a8617c 4305{
2e0fef85 4306 struct lpfc_vport *vport;
895427bd 4307 struct Scsi_Host *shost = NULL;
c90b4480 4308 struct scsi_host_template *template;
2e0fef85 4309 int error = 0;
96418b5e
JS
4310 int i;
4311 uint64_t wwn;
4312 bool use_no_reset_hba = false;
56bc8028 4313 int rc;
96418b5e 4314
56bc8028
JS
4315 if (lpfc_no_hba_reset_cnt) {
4316 if (phba->sli_rev < LPFC_SLI_REV4 &&
4317 dev == &phba->pcidev->dev) {
4318 /* Reset the port first */
4319 lpfc_sli_brdrestart(phba);
4320 rc = lpfc_sli_chipset_init(phba);
4321 if (rc)
4322 return NULL;
4323 }
4324 wwn = lpfc_get_wwpn(phba);
4325 }
96418b5e
JS
4326
4327 for (i = 0; i < lpfc_no_hba_reset_cnt; i++) {
4328 if (wwn == lpfc_no_hba_reset[i]) {
372c187b
DK
4329 lpfc_printf_log(phba, KERN_ERR,
4330 LOG_TRACE_EVENT,
96418b5e
JS
4331 "6020 Setting use_no_reset port=%llx\n",
4332 wwn);
4333 use_no_reset_hba = true;
4334 break;
4335 }
4336 }
47a8617c 4337
c90b4480
JS
4338 /* Seed template for SCSI host registration */
4339 if (dev == &phba->pcidev->dev) {
4340 template = &phba->port_template;
4341
4342 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
4343 /* Seed physical port template */
4344 memcpy(template, &lpfc_template, sizeof(*template));
4345
4346 if (use_no_reset_hba) {
4347 /* template is for a no reset SCSI Host */
4348 template->max_sectors = 0xffff;
4349 template->eh_host_reset_handler = NULL;
4350 }
4351
4352 /* Template for all vports this physical port creates */
4353 memcpy(&phba->vport_template, &lpfc_template,
4354 sizeof(*template));
4355 phba->vport_template.max_sectors = 0xffff;
4356 phba->vport_template.shost_attrs = lpfc_vport_attrs;
4357 phba->vport_template.eh_bus_reset_handler = NULL;
4358 phba->vport_template.eh_host_reset_handler = NULL;
4359 phba->vport_template.vendor_id = 0;
4360
4361 /* Initialize the host templates with updated value */
4362 if (phba->sli_rev == LPFC_SLI_REV4) {
4363 template->sg_tablesize = phba->cfg_scsi_seg_cnt;
4364 phba->vport_template.sg_tablesize =
4365 phba->cfg_scsi_seg_cnt;
4366 } else {
4367 template->sg_tablesize = phba->cfg_sg_seg_cnt;
4368 phba->vport_template.sg_tablesize =
4369 phba->cfg_sg_seg_cnt;
4370 }
4371
895427bd 4372 } else {
c90b4480
JS
4373 /* NVMET is for physical port only */
4374 memcpy(template, &lpfc_template_nvme,
4375 sizeof(*template));
895427bd 4376 }
c90b4480
JS
4377 } else {
4378 template = &phba->vport_template;
ea4142f6 4379 }
c90b4480
JS
4380
4381 shost = scsi_host_alloc(template, sizeof(struct lpfc_vport));
2e0fef85
JS
4382 if (!shost)
4383 goto out;
47a8617c 4384
2e0fef85
JS
4385 vport = (struct lpfc_vport *) shost->hostdata;
4386 vport->phba = phba;
2e0fef85 4387 vport->load_flag |= FC_LOADING;
92d7f7b0 4388 vport->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
7f5f3d0d 4389 vport->fc_rscn_flush = 0;
3de2a653 4390 lpfc_get_vport_cfgparam(vport);
895427bd 4391
f6e84790
JS
4392 /* Adjust value in vport */
4393 vport->cfg_enable_fc4_type = phba->cfg_enable_fc4_type;
4394
2e0fef85
JS
4395 shost->unique_id = instance;
4396 shost->max_id = LPFC_MAX_TARGET;
3de2a653 4397 shost->max_lun = vport->cfg_max_luns;
2e0fef85
JS
4398 shost->this_id = -1;
4399 shost->max_cmd_len = 16;
6a828b0f 4400
da0436e9 4401 if (phba->sli_rev == LPFC_SLI_REV4) {
77ffd346
JS
4402 if (!phba->cfg_fcp_mq_threshold ||
4403 phba->cfg_fcp_mq_threshold > phba->cfg_hdw_queue)
4404 phba->cfg_fcp_mq_threshold = phba->cfg_hdw_queue;
4405
4406 shost->nr_hw_queues = min_t(int, 2 * num_possible_nodes(),
4407 phba->cfg_fcp_mq_threshold);
6a828b0f 4408
28baac74 4409 shost->dma_boundary =
cb5172ea 4410 phba->sli4_hba.pc_sli4_params.sge_supp_len-1;
d79c9e9d
JS
4411
4412 if (phba->cfg_xpsgl && !phba->nvmet_support)
4413 shost->sg_tablesize = LPFC_MAX_SG_TABLESIZE;
4414 else
4415 shost->sg_tablesize = phba->cfg_scsi_seg_cnt;
ace44e48
JS
4416 } else
4417 /* SLI-3 has a limited number of hardware queues (3),
4418 * thus there is only one for FCP processing.
4419 */
4420 shost->nr_hw_queues = 1;
81301a9b 4421
47a8617c 4422 /*
2e0fef85
JS
4423 * Set initial can_queue value since 0 is no longer supported and
4424 * scsi_add_host will fail. This will be adjusted later based on the
4425 * max xri value determined in hba setup.
47a8617c 4426 */
2e0fef85 4427 shost->can_queue = phba->cfg_hba_queue_depth - 10;
3de2a653 4428 if (dev != &phba->pcidev->dev) {
92d7f7b0
JS
4429 shost->transportt = lpfc_vport_transport_template;
4430 vport->port_type = LPFC_NPIV_PORT;
4431 } else {
4432 shost->transportt = lpfc_transport_template;
4433 vport->port_type = LPFC_PHYSICAL_PORT;
4434 }
47a8617c 4435
c90b4480
JS
4436 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
4437 "9081 CreatePort TMPLATE type %x TBLsize %d "
4438 "SEGcnt %d/%d\n",
4439 vport->port_type, shost->sg_tablesize,
4440 phba->cfg_scsi_seg_cnt, phba->cfg_sg_seg_cnt);
4441
2e0fef85
JS
4442 /* Initialize all internally managed lists. */
4443 INIT_LIST_HEAD(&vport->fc_nodes);
da0436e9 4444 INIT_LIST_HEAD(&vport->rcv_buffer_list);
2e0fef85 4445 spin_lock_init(&vport->work_port_lock);
47a8617c 4446
f22eb4d3 4447 timer_setup(&vport->fc_disctmo, lpfc_disc_timeout, 0);
47a8617c 4448
f22eb4d3 4449 timer_setup(&vport->els_tmofunc, lpfc_els_timeout, 0);
92494144 4450
f22eb4d3 4451 timer_setup(&vport->delayed_disc_tmo, lpfc_delayed_disc_tmo, 0);
92494144 4452
aa6ff309
JS
4453 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED)
4454 lpfc_setup_bg(phba, shost);
4455
d139b9bd 4456 error = scsi_add_host_with_dma(shost, dev, &phba->pcidev->dev);
2e0fef85
JS
4457 if (error)
4458 goto out_put_shost;
47a8617c 4459
523128e5 4460 spin_lock_irq(&phba->port_list_lock);
2e0fef85 4461 list_add_tail(&vport->listentry, &phba->port_list);
523128e5 4462 spin_unlock_irq(&phba->port_list_lock);
2e0fef85 4463 return vport;
47a8617c 4464
2e0fef85
JS
4465out_put_shost:
4466 scsi_host_put(shost);
4467out:
4468 return NULL;
47a8617c
JS
4469}
4470
e59058c4 4471/**
3621a710 4472 * destroy_port - destroy an FC port
e59058c4
JS
4473 * @vport: pointer to an lpfc virtual N_Port data structure.
4474 *
4475 * This routine destroys a FC port from the upper layer protocol. All the
4476 * resources associated with the port are released.
4477 **/
2e0fef85
JS
4478void
4479destroy_port(struct lpfc_vport *vport)
47a8617c 4480{
92d7f7b0
JS
4481 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
4482 struct lpfc_hba *phba = vport->phba;
47a8617c 4483
858c9f6c 4484 lpfc_debugfs_terminate(vport);
92d7f7b0
JS
4485 fc_remove_host(shost);
4486 scsi_remove_host(shost);
47a8617c 4487
523128e5 4488 spin_lock_irq(&phba->port_list_lock);
92d7f7b0 4489 list_del_init(&vport->listentry);
523128e5 4490 spin_unlock_irq(&phba->port_list_lock);
47a8617c 4491
92d7f7b0 4492 lpfc_cleanup(vport);
47a8617c 4493 return;
47a8617c
JS
4494}
4495
e59058c4 4496/**
3621a710 4497 * lpfc_get_instance - Get a unique integer ID
e59058c4
JS
4498 *
4499 * This routine allocates a unique integer ID from lpfc_hba_index pool. It
4500 * uses the kernel idr facility to perform the task.
4501 *
4502 * Return codes:
4503 * instance - a unique integer ID allocated as the new instance.
4504 * -1 - lpfc get instance failed.
4505 **/
92d7f7b0
JS
4506int
4507lpfc_get_instance(void)
4508{
ab516036
TH
4509 int ret;
4510
4511 ret = idr_alloc(&lpfc_hba_index, NULL, 0, 0, GFP_KERNEL);
4512 return ret < 0 ? -1 : ret;
47a8617c
JS
4513}
4514
e59058c4 4515/**
3621a710 4516 * lpfc_scan_finished - method for SCSI layer to detect whether scan is done
e59058c4
JS
4517 * @shost: pointer to SCSI host data structure.
4518 * @time: elapsed time of the scan in jiffies.
4519 *
4520 * This routine is called by the SCSI layer with a SCSI host to determine
4521 * whether the scan host is finished.
4522 *
4523 * Note: there is no scan_start function as adapter initialization will have
4524 * asynchronously kicked off the link initialization.
4525 *
4526 * Return codes
4527 * 0 - SCSI host scan is not over yet.
4528 * 1 - SCSI host scan is over.
4529 **/
47a8617c
JS
4530int lpfc_scan_finished(struct Scsi_Host *shost, unsigned long time)
4531{
2e0fef85
JS
4532 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4533 struct lpfc_hba *phba = vport->phba;
858c9f6c 4534 int stat = 0;
47a8617c 4535
858c9f6c
JS
4536 spin_lock_irq(shost->host_lock);
4537
51ef4c26 4538 if (vport->load_flag & FC_UNLOADING) {
858c9f6c
JS
4539 stat = 1;
4540 goto finished;
4541 }
256ec0d0 4542 if (time >= msecs_to_jiffies(30 * 1000)) {
2e0fef85 4543 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011
JS
4544 "0461 Scanning longer than 30 "
4545 "seconds. Continuing initialization\n");
858c9f6c 4546 stat = 1;
47a8617c 4547 goto finished;
2e0fef85 4548 }
256ec0d0
JS
4549 if (time >= msecs_to_jiffies(15 * 1000) &&
4550 phba->link_state <= LPFC_LINK_DOWN) {
2e0fef85 4551 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011
JS
4552 "0465 Link down longer than 15 "
4553 "seconds. Continuing initialization\n");
858c9f6c 4554 stat = 1;
47a8617c 4555 goto finished;
2e0fef85 4556 }
47a8617c 4557
2e0fef85 4558 if (vport->port_state != LPFC_VPORT_READY)
858c9f6c 4559 goto finished;
2e0fef85 4560 if (vport->num_disc_nodes || vport->fc_prli_sent)
858c9f6c 4561 goto finished;
256ec0d0 4562 if (vport->fc_map_cnt == 0 && time < msecs_to_jiffies(2 * 1000))
858c9f6c 4563 goto finished;
2e0fef85 4564 if ((phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) != 0)
858c9f6c
JS
4565 goto finished;
4566
4567 stat = 1;
47a8617c
JS
4568
4569finished:
858c9f6c
JS
4570 spin_unlock_irq(shost->host_lock);
4571 return stat;
92d7f7b0 4572}
47a8617c 4573
3999df75 4574static void lpfc_host_supported_speeds_set(struct Scsi_Host *shost)
cd71348a
JS
4575{
4576 struct lpfc_vport *vport = (struct lpfc_vport *)shost->hostdata;
4577 struct lpfc_hba *phba = vport->phba;
4578
4579 fc_host_supported_speeds(shost) = 0;
a1e4d3d8
DK
4580 /*
4581 * Avoid reporting supported link speed for FCoE as it can't be
4582 * controlled via FCoE.
4583 */
4584 if (phba->hba_flag & HBA_FCOE_MODE)
4585 return;
4586
1dc5ec24
JS
4587 if (phba->lmt & LMT_128Gb)
4588 fc_host_supported_speeds(shost) |= FC_PORTSPEED_128GBIT;
cd71348a
JS
4589 if (phba->lmt & LMT_64Gb)
4590 fc_host_supported_speeds(shost) |= FC_PORTSPEED_64GBIT;
4591 if (phba->lmt & LMT_32Gb)
4592 fc_host_supported_speeds(shost) |= FC_PORTSPEED_32GBIT;
4593 if (phba->lmt & LMT_16Gb)
4594 fc_host_supported_speeds(shost) |= FC_PORTSPEED_16GBIT;
4595 if (phba->lmt & LMT_10Gb)
4596 fc_host_supported_speeds(shost) |= FC_PORTSPEED_10GBIT;
4597 if (phba->lmt & LMT_8Gb)
4598 fc_host_supported_speeds(shost) |= FC_PORTSPEED_8GBIT;
4599 if (phba->lmt & LMT_4Gb)
4600 fc_host_supported_speeds(shost) |= FC_PORTSPEED_4GBIT;
4601 if (phba->lmt & LMT_2Gb)
4602 fc_host_supported_speeds(shost) |= FC_PORTSPEED_2GBIT;
4603 if (phba->lmt & LMT_1Gb)
4604 fc_host_supported_speeds(shost) |= FC_PORTSPEED_1GBIT;
4605}
4606
e59058c4 4607/**
3621a710 4608 * lpfc_host_attrib_init - Initialize SCSI host attributes on a FC port
e59058c4
JS
4609 * @shost: pointer to SCSI host data structure.
4610 *
4611 * This routine initializes a given SCSI host attributes on a FC port. The
4612 * SCSI host can be either on top of a physical port or a virtual port.
4613 **/
92d7f7b0
JS
4614void lpfc_host_attrib_init(struct Scsi_Host *shost)
4615{
4616 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4617 struct lpfc_hba *phba = vport->phba;
47a8617c 4618 /*
2e0fef85 4619 * Set fixed host attributes. Must done after lpfc_sli_hba_setup().
47a8617c
JS
4620 */
4621
2e0fef85
JS
4622 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
4623 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
47a8617c
JS
4624 fc_host_supported_classes(shost) = FC_COS_CLASS3;
4625
4626 memset(fc_host_supported_fc4s(shost), 0,
2e0fef85 4627 sizeof(fc_host_supported_fc4s(shost)));
47a8617c
JS
4628 fc_host_supported_fc4s(shost)[2] = 1;
4629 fc_host_supported_fc4s(shost)[7] = 1;
4630
92d7f7b0
JS
4631 lpfc_vport_symbolic_node_name(vport, fc_host_symbolic_name(shost),
4632 sizeof fc_host_symbolic_name(shost));
47a8617c 4633
cd71348a 4634 lpfc_host_supported_speeds_set(shost);
47a8617c
JS
4635
4636 fc_host_maxframe_size(shost) =
2e0fef85
JS
4637 (((uint32_t) vport->fc_sparam.cmn.bbRcvSizeMsb & 0x0F) << 8) |
4638 (uint32_t) vport->fc_sparam.cmn.bbRcvSizeLsb;
47a8617c 4639
0af5d708
MC
4640 fc_host_dev_loss_tmo(shost) = vport->cfg_devloss_tmo;
4641
47a8617c
JS
4642 /* This value is also unchanging */
4643 memset(fc_host_active_fc4s(shost), 0,
2e0fef85 4644 sizeof(fc_host_active_fc4s(shost)));
47a8617c
JS
4645 fc_host_active_fc4s(shost)[2] = 1;
4646 fc_host_active_fc4s(shost)[7] = 1;
4647
92d7f7b0 4648 fc_host_max_npiv_vports(shost) = phba->max_vpi;
47a8617c 4649 spin_lock_irq(shost->host_lock);
51ef4c26 4650 vport->load_flag &= ~FC_LOADING;
47a8617c 4651 spin_unlock_irq(shost->host_lock);
47a8617c 4652}
dea3101e 4653
e59058c4 4654/**
da0436e9 4655 * lpfc_stop_port_s3 - Stop SLI3 device port
e59058c4
JS
4656 * @phba: pointer to lpfc hba data structure.
4657 *
da0436e9
JS
4658 * This routine is invoked to stop an SLI3 device port, it stops the device
4659 * from generating interrupts and stops the device driver's timers for the
4660 * device.
e59058c4 4661 **/
da0436e9
JS
4662static void
4663lpfc_stop_port_s3(struct lpfc_hba *phba)
db2378e0 4664{
da0436e9
JS
4665 /* Clear all interrupt enable conditions */
4666 writel(0, phba->HCregaddr);
4667 readl(phba->HCregaddr); /* flush */
4668 /* Clear all pending interrupts */
4669 writel(0xffffffff, phba->HAregaddr);
4670 readl(phba->HAregaddr); /* flush */
db2378e0 4671
da0436e9
JS
4672 /* Reset some HBA SLI setup states */
4673 lpfc_stop_hba_timers(phba);
4674 phba->pport->work_port_events = 0;
4675}
db2378e0 4676
da0436e9
JS
4677/**
4678 * lpfc_stop_port_s4 - Stop SLI4 device port
4679 * @phba: pointer to lpfc hba data structure.
4680 *
4681 * This routine is invoked to stop an SLI4 device port, it stops the device
4682 * from generating interrupts and stops the device driver's timers for the
4683 * device.
4684 **/
4685static void
4686lpfc_stop_port_s4(struct lpfc_hba *phba)
4687{
4688 /* Reset some HBA SLI4 setup states */
4689 lpfc_stop_hba_timers(phba);
cdb42bec
JS
4690 if (phba->pport)
4691 phba->pport->work_port_events = 0;
da0436e9 4692 phba->sli4_hba.intr_enable = 0;
da0436e9 4693}
9399627f 4694
da0436e9
JS
4695/**
4696 * lpfc_stop_port - Wrapper function for stopping hba port
4697 * @phba: Pointer to HBA context object.
4698 *
4699 * This routine wraps the actual SLI3 or SLI4 hba stop port routine from
4700 * the API jump table function pointer from the lpfc_hba struct.
4701 **/
4702void
4703lpfc_stop_port(struct lpfc_hba *phba)
4704{
4705 phba->lpfc_stop_port(phba);
f485c18d
DK
4706
4707 if (phba->wq)
4708 flush_workqueue(phba->wq);
da0436e9 4709}
db2378e0 4710
ecfd03c6
JS
4711/**
4712 * lpfc_fcf_redisc_wait_start_timer - Start fcf rediscover wait timer
4713 * @phba: Pointer to hba for which this call is being executed.
4714 *
4715 * This routine starts the timer waiting for the FCF rediscovery to complete.
4716 **/
4717void
4718lpfc_fcf_redisc_wait_start_timer(struct lpfc_hba *phba)
4719{
4720 unsigned long fcf_redisc_wait_tmo =
4721 (jiffies + msecs_to_jiffies(LPFC_FCF_REDISCOVER_WAIT_TMO));
4722 /* Start fcf rediscovery wait period timer */
4723 mod_timer(&phba->fcf.redisc_wait, fcf_redisc_wait_tmo);
4724 spin_lock_irq(&phba->hbalock);
4725 /* Allow action to new fcf asynchronous event */
4726 phba->fcf.fcf_flag &= ~(FCF_AVAILABLE | FCF_SCAN_DONE);
4727 /* Mark the FCF rediscovery pending state */
4728 phba->fcf.fcf_flag |= FCF_REDISC_PEND;
4729 spin_unlock_irq(&phba->hbalock);
4730}
4731
4732/**
4733 * lpfc_sli4_fcf_redisc_wait_tmo - FCF table rediscover wait timeout
fe614acd 4734 * @t: Timer context used to obtain the pointer to lpfc hba data structure.
ecfd03c6
JS
4735 *
4736 * This routine is invoked when waiting for FCF table rediscover has been
4737 * timed out. If new FCF record(s) has (have) been discovered during the
4738 * wait period, a new FCF event shall be added to the FCOE async event
4739 * list, and then worker thread shall be waked up for processing from the
4740 * worker thread context.
4741 **/
e399b228 4742static void
f22eb4d3 4743lpfc_sli4_fcf_redisc_wait_tmo(struct timer_list *t)
ecfd03c6 4744{
f22eb4d3 4745 struct lpfc_hba *phba = from_timer(phba, t, fcf.redisc_wait);
ecfd03c6
JS
4746
4747 /* Don't send FCF rediscovery event if timer cancelled */
4748 spin_lock_irq(&phba->hbalock);
4749 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
4750 spin_unlock_irq(&phba->hbalock);
4751 return;
4752 }
4753 /* Clear FCF rediscovery timer pending flag */
4754 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
4755 /* FCF rediscovery event to worker thread */
4756 phba->fcf.fcf_flag |= FCF_REDISC_EVT;
4757 spin_unlock_irq(&phba->hbalock);
0c9ab6f5 4758 lpfc_printf_log(phba, KERN_INFO, LOG_FIP,
a93ff37a 4759 "2776 FCF rediscover quiescent timer expired\n");
ecfd03c6
JS
4760 /* wake up worker thread */
4761 lpfc_worker_wake_up(phba);
4762}
4763
e59058c4 4764/**
da0436e9 4765 * lpfc_sli4_parse_latt_fault - Parse sli4 link-attention link fault code
e59058c4 4766 * @phba: pointer to lpfc hba data structure.
da0436e9 4767 * @acqe_link: pointer to the async link completion queue entry.
e59058c4 4768 *
23288b78 4769 * This routine is to parse the SLI4 link-attention link fault code.
e59058c4 4770 **/
23288b78 4771static void
da0436e9
JS
4772lpfc_sli4_parse_latt_fault(struct lpfc_hba *phba,
4773 struct lpfc_acqe_link *acqe_link)
db2378e0 4774{
da0436e9
JS
4775 switch (bf_get(lpfc_acqe_link_fault, acqe_link)) {
4776 case LPFC_ASYNC_LINK_FAULT_NONE:
4777 case LPFC_ASYNC_LINK_FAULT_LOCAL:
4778 case LPFC_ASYNC_LINK_FAULT_REMOTE:
23288b78 4779 case LPFC_ASYNC_LINK_FAULT_LR_LRR:
da0436e9
JS
4780 break;
4781 default:
372c187b 4782 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
23288b78 4783 "0398 Unknown link fault code: x%x\n",
da0436e9 4784 bf_get(lpfc_acqe_link_fault, acqe_link));
da0436e9
JS
4785 break;
4786 }
db2378e0
JS
4787}
4788
5b75da2f 4789/**
da0436e9 4790 * lpfc_sli4_parse_latt_type - Parse sli4 link attention type
5b75da2f 4791 * @phba: pointer to lpfc hba data structure.
da0436e9 4792 * @acqe_link: pointer to the async link completion queue entry.
5b75da2f 4793 *
da0436e9
JS
4794 * This routine is to parse the SLI4 link attention type and translate it
4795 * into the base driver's link attention type coding.
5b75da2f 4796 *
da0436e9
JS
4797 * Return: Link attention type in terms of base driver's coding.
4798 **/
4799static uint8_t
4800lpfc_sli4_parse_latt_type(struct lpfc_hba *phba,
4801 struct lpfc_acqe_link *acqe_link)
5b75da2f 4802{
da0436e9 4803 uint8_t att_type;
5b75da2f 4804
da0436e9
JS
4805 switch (bf_get(lpfc_acqe_link_status, acqe_link)) {
4806 case LPFC_ASYNC_LINK_STATUS_DOWN:
4807 case LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN:
76a95d75 4808 att_type = LPFC_ATT_LINK_DOWN;
da0436e9
JS
4809 break;
4810 case LPFC_ASYNC_LINK_STATUS_UP:
4811 /* Ignore physical link up events - wait for logical link up */
76a95d75 4812 att_type = LPFC_ATT_RESERVED;
da0436e9
JS
4813 break;
4814 case LPFC_ASYNC_LINK_STATUS_LOGICAL_UP:
76a95d75 4815 att_type = LPFC_ATT_LINK_UP;
da0436e9
JS
4816 break;
4817 default:
372c187b 4818 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
4819 "0399 Invalid link attention type: x%x\n",
4820 bf_get(lpfc_acqe_link_status, acqe_link));
76a95d75 4821 att_type = LPFC_ATT_RESERVED;
da0436e9 4822 break;
5b75da2f 4823 }
da0436e9 4824 return att_type;
5b75da2f
JS
4825}
4826
8b68cd52
JS
4827/**
4828 * lpfc_sli_port_speed_get - Get sli3 link speed code to link speed
4829 * @phba: pointer to lpfc hba data structure.
4830 *
4831 * This routine is to get an SLI3 FC port's link speed in Mbps.
4832 *
4833 * Return: link speed in terms of Mbps.
4834 **/
4835uint32_t
4836lpfc_sli_port_speed_get(struct lpfc_hba *phba)
4837{
4838 uint32_t link_speed;
4839
4840 if (!lpfc_is_link_up(phba))
4841 return 0;
4842
a085e87c
JS
4843 if (phba->sli_rev <= LPFC_SLI_REV3) {
4844 switch (phba->fc_linkspeed) {
4845 case LPFC_LINK_SPEED_1GHZ:
4846 link_speed = 1000;
4847 break;
4848 case LPFC_LINK_SPEED_2GHZ:
4849 link_speed = 2000;
4850 break;
4851 case LPFC_LINK_SPEED_4GHZ:
4852 link_speed = 4000;
4853 break;
4854 case LPFC_LINK_SPEED_8GHZ:
4855 link_speed = 8000;
4856 break;
4857 case LPFC_LINK_SPEED_10GHZ:
4858 link_speed = 10000;
4859 break;
4860 case LPFC_LINK_SPEED_16GHZ:
4861 link_speed = 16000;
4862 break;
4863 default:
4864 link_speed = 0;
4865 }
4866 } else {
4867 if (phba->sli4_hba.link_state.logical_speed)
4868 link_speed =
4869 phba->sli4_hba.link_state.logical_speed;
4870 else
4871 link_speed = phba->sli4_hba.link_state.speed;
8b68cd52
JS
4872 }
4873 return link_speed;
4874}
4875
4876/**
4877 * lpfc_sli4_port_speed_parse - Parse async evt link speed code to link speed
4878 * @phba: pointer to lpfc hba data structure.
4879 * @evt_code: asynchronous event code.
4880 * @speed_code: asynchronous event link speed code.
4881 *
4882 * This routine is to parse the giving SLI4 async event link speed code into
4883 * value of Mbps for the link speed.
4884 *
4885 * Return: link speed in terms of Mbps.
4886 **/
4887static uint32_t
4888lpfc_sli4_port_speed_parse(struct lpfc_hba *phba, uint32_t evt_code,
4889 uint8_t speed_code)
4890{
4891 uint32_t port_speed;
4892
4893 switch (evt_code) {
4894 case LPFC_TRAILER_CODE_LINK:
4895 switch (speed_code) {
26d830ec 4896 case LPFC_ASYNC_LINK_SPEED_ZERO:
8b68cd52
JS
4897 port_speed = 0;
4898 break;
26d830ec 4899 case LPFC_ASYNC_LINK_SPEED_10MBPS:
8b68cd52
JS
4900 port_speed = 10;
4901 break;
26d830ec 4902 case LPFC_ASYNC_LINK_SPEED_100MBPS:
8b68cd52
JS
4903 port_speed = 100;
4904 break;
26d830ec 4905 case LPFC_ASYNC_LINK_SPEED_1GBPS:
8b68cd52
JS
4906 port_speed = 1000;
4907 break;
26d830ec 4908 case LPFC_ASYNC_LINK_SPEED_10GBPS:
8b68cd52
JS
4909 port_speed = 10000;
4910 break;
26d830ec
JS
4911 case LPFC_ASYNC_LINK_SPEED_20GBPS:
4912 port_speed = 20000;
4913 break;
4914 case LPFC_ASYNC_LINK_SPEED_25GBPS:
4915 port_speed = 25000;
4916 break;
4917 case LPFC_ASYNC_LINK_SPEED_40GBPS:
4918 port_speed = 40000;
4919 break;
a1e4d3d8
DK
4920 case LPFC_ASYNC_LINK_SPEED_100GBPS:
4921 port_speed = 100000;
4922 break;
8b68cd52
JS
4923 default:
4924 port_speed = 0;
4925 }
4926 break;
4927 case LPFC_TRAILER_CODE_FC:
4928 switch (speed_code) {
26d830ec 4929 case LPFC_FC_LA_SPEED_UNKNOWN:
8b68cd52
JS
4930 port_speed = 0;
4931 break;
26d830ec 4932 case LPFC_FC_LA_SPEED_1G:
8b68cd52
JS
4933 port_speed = 1000;
4934 break;
26d830ec 4935 case LPFC_FC_LA_SPEED_2G:
8b68cd52
JS
4936 port_speed = 2000;
4937 break;
26d830ec 4938 case LPFC_FC_LA_SPEED_4G:
8b68cd52
JS
4939 port_speed = 4000;
4940 break;
26d830ec 4941 case LPFC_FC_LA_SPEED_8G:
8b68cd52
JS
4942 port_speed = 8000;
4943 break;
26d830ec 4944 case LPFC_FC_LA_SPEED_10G:
8b68cd52
JS
4945 port_speed = 10000;
4946 break;
26d830ec 4947 case LPFC_FC_LA_SPEED_16G:
8b68cd52
JS
4948 port_speed = 16000;
4949 break;
d38dd52c
JS
4950 case LPFC_FC_LA_SPEED_32G:
4951 port_speed = 32000;
4952 break;
fbd8a6ba
JS
4953 case LPFC_FC_LA_SPEED_64G:
4954 port_speed = 64000;
4955 break;
1dc5ec24
JS
4956 case LPFC_FC_LA_SPEED_128G:
4957 port_speed = 128000;
4958 break;
8b68cd52
JS
4959 default:
4960 port_speed = 0;
4961 }
4962 break;
4963 default:
4964 port_speed = 0;
4965 }
4966 return port_speed;
4967}
4968
da0436e9 4969/**
70f3c073 4970 * lpfc_sli4_async_link_evt - Process the asynchronous FCoE link event
da0436e9
JS
4971 * @phba: pointer to lpfc hba data structure.
4972 * @acqe_link: pointer to the async link completion queue entry.
4973 *
70f3c073 4974 * This routine is to handle the SLI4 asynchronous FCoE link event.
da0436e9
JS
4975 **/
4976static void
4977lpfc_sli4_async_link_evt(struct lpfc_hba *phba,
4978 struct lpfc_acqe_link *acqe_link)
4979{
4980 struct lpfc_dmabuf *mp;
4981 LPFC_MBOXQ_t *pmb;
4982 MAILBOX_t *mb;
76a95d75 4983 struct lpfc_mbx_read_top *la;
da0436e9 4984 uint8_t att_type;
76a95d75 4985 int rc;
da0436e9
JS
4986
4987 att_type = lpfc_sli4_parse_latt_type(phba, acqe_link);
76a95d75 4988 if (att_type != LPFC_ATT_LINK_DOWN && att_type != LPFC_ATT_LINK_UP)
da0436e9 4989 return;
32b9793f 4990 phba->fcoe_eventtag = acqe_link->event_tag;
da0436e9
JS
4991 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
4992 if (!pmb) {
372c187b 4993 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
4994 "0395 The mboxq allocation failed\n");
4995 return;
4996 }
4997 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
4998 if (!mp) {
372c187b 4999 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
5000 "0396 The lpfc_dmabuf allocation failed\n");
5001 goto out_free_pmb;
5002 }
5003 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
5004 if (!mp->virt) {
372c187b 5005 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
5006 "0397 The mbuf allocation failed\n");
5007 goto out_free_dmabuf;
5008 }
5009
5010 /* Cleanup any outstanding ELS commands */
5011 lpfc_els_flush_all_cmd(phba);
5012
5013 /* Block ELS IOCBs until we have done process link event */
895427bd 5014 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
da0436e9
JS
5015
5016 /* Update link event statistics */
5017 phba->sli.slistat.link_event++;
5018
76a95d75
JS
5019 /* Create lpfc_handle_latt mailbox command from link ACQE */
5020 lpfc_read_topology(phba, pmb, mp);
5021 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
da0436e9
JS
5022 pmb->vport = phba->pport;
5023
da0436e9
JS
5024 /* Keep the link status for extra SLI4 state machine reference */
5025 phba->sli4_hba.link_state.speed =
8b68cd52
JS
5026 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_LINK,
5027 bf_get(lpfc_acqe_link_speed, acqe_link));
da0436e9
JS
5028 phba->sli4_hba.link_state.duplex =
5029 bf_get(lpfc_acqe_link_duplex, acqe_link);
5030 phba->sli4_hba.link_state.status =
5031 bf_get(lpfc_acqe_link_status, acqe_link);
70f3c073
JS
5032 phba->sli4_hba.link_state.type =
5033 bf_get(lpfc_acqe_link_type, acqe_link);
5034 phba->sli4_hba.link_state.number =
5035 bf_get(lpfc_acqe_link_number, acqe_link);
da0436e9
JS
5036 phba->sli4_hba.link_state.fault =
5037 bf_get(lpfc_acqe_link_fault, acqe_link);
65467b6b 5038 phba->sli4_hba.link_state.logical_speed =
8b68cd52
JS
5039 bf_get(lpfc_acqe_logical_link_speed, acqe_link) * 10;
5040
70f3c073 5041 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
c31098ce
JS
5042 "2900 Async FC/FCoE Link event - Speed:%dGBit "
5043 "duplex:x%x LA Type:x%x Port Type:%d Port Number:%d "
5044 "Logical speed:%dMbps Fault:%d\n",
70f3c073
JS
5045 phba->sli4_hba.link_state.speed,
5046 phba->sli4_hba.link_state.topology,
5047 phba->sli4_hba.link_state.status,
5048 phba->sli4_hba.link_state.type,
5049 phba->sli4_hba.link_state.number,
8b68cd52 5050 phba->sli4_hba.link_state.logical_speed,
70f3c073 5051 phba->sli4_hba.link_state.fault);
76a95d75
JS
5052 /*
5053 * For FC Mode: issue the READ_TOPOLOGY mailbox command to fetch
5054 * topology info. Note: Optional for non FC-AL ports.
5055 */
5056 if (!(phba->hba_flag & HBA_FCOE_MODE)) {
5057 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
5058 if (rc == MBX_NOT_FINISHED)
5059 goto out_free_dmabuf;
5060 return;
5061 }
5062 /*
5063 * For FCoE Mode: fill in all the topology information we need and call
5064 * the READ_TOPOLOGY completion routine to continue without actually
5065 * sending the READ_TOPOLOGY mailbox command to the port.
5066 */
23288b78 5067 /* Initialize completion status */
76a95d75 5068 mb = &pmb->u.mb;
23288b78
JS
5069 mb->mbxStatus = MBX_SUCCESS;
5070
5071 /* Parse port fault information field */
5072 lpfc_sli4_parse_latt_fault(phba, acqe_link);
76a95d75
JS
5073
5074 /* Parse and translate link attention fields */
5075 la = (struct lpfc_mbx_read_top *) &pmb->u.mb.un.varReadTop;
5076 la->eventTag = acqe_link->event_tag;
5077 bf_set(lpfc_mbx_read_top_att_type, la, att_type);
5078 bf_set(lpfc_mbx_read_top_link_spd, la,
a085e87c 5079 (bf_get(lpfc_acqe_link_speed, acqe_link)));
76a95d75
JS
5080
5081 /* Fake the the following irrelvant fields */
5082 bf_set(lpfc_mbx_read_top_topology, la, LPFC_TOPOLOGY_PT_PT);
5083 bf_set(lpfc_mbx_read_top_alpa_granted, la, 0);
5084 bf_set(lpfc_mbx_read_top_il, la, 0);
5085 bf_set(lpfc_mbx_read_top_pb, la, 0);
5086 bf_set(lpfc_mbx_read_top_fa, la, 0);
5087 bf_set(lpfc_mbx_read_top_mm, la, 0);
da0436e9
JS
5088
5089 /* Invoke the lpfc_handle_latt mailbox command callback function */
76a95d75 5090 lpfc_mbx_cmpl_read_topology(phba, pmb);
da0436e9 5091
5b75da2f 5092 return;
da0436e9
JS
5093
5094out_free_dmabuf:
5095 kfree(mp);
5096out_free_pmb:
5097 mempool_free(pmb, phba->mbox_mem_pool);
5098}
5099
1dc5ec24
JS
5100/**
5101 * lpfc_async_link_speed_to_read_top - Parse async evt link speed code to read
5102 * topology.
5103 * @phba: pointer to lpfc hba data structure.
1dc5ec24
JS
5104 * @speed_code: asynchronous event link speed code.
5105 *
5106 * This routine is to parse the giving SLI4 async event link speed code into
5107 * value of Read topology link speed.
5108 *
5109 * Return: link speed in terms of Read topology.
5110 **/
5111static uint8_t
5112lpfc_async_link_speed_to_read_top(struct lpfc_hba *phba, uint8_t speed_code)
5113{
5114 uint8_t port_speed;
5115
5116 switch (speed_code) {
5117 case LPFC_FC_LA_SPEED_1G:
5118 port_speed = LPFC_LINK_SPEED_1GHZ;
5119 break;
5120 case LPFC_FC_LA_SPEED_2G:
5121 port_speed = LPFC_LINK_SPEED_2GHZ;
5122 break;
5123 case LPFC_FC_LA_SPEED_4G:
5124 port_speed = LPFC_LINK_SPEED_4GHZ;
5125 break;
5126 case LPFC_FC_LA_SPEED_8G:
5127 port_speed = LPFC_LINK_SPEED_8GHZ;
5128 break;
5129 case LPFC_FC_LA_SPEED_16G:
5130 port_speed = LPFC_LINK_SPEED_16GHZ;
5131 break;
5132 case LPFC_FC_LA_SPEED_32G:
5133 port_speed = LPFC_LINK_SPEED_32GHZ;
5134 break;
5135 case LPFC_FC_LA_SPEED_64G:
5136 port_speed = LPFC_LINK_SPEED_64GHZ;
5137 break;
5138 case LPFC_FC_LA_SPEED_128G:
5139 port_speed = LPFC_LINK_SPEED_128GHZ;
5140 break;
5141 case LPFC_FC_LA_SPEED_256G:
5142 port_speed = LPFC_LINK_SPEED_256GHZ;
5143 break;
5144 default:
5145 port_speed = 0;
5146 break;
5147 }
5148
5149 return port_speed;
5150}
5151
5152#define trunk_link_status(__idx)\
5153 bf_get(lpfc_acqe_fc_la_trunk_config_port##__idx, acqe_fc) ?\
5154 ((phba->trunk_link.link##__idx.state == LPFC_LINK_UP) ?\
5155 "Link up" : "Link down") : "NA"
5156/* Did port __idx reported an error */
5157#define trunk_port_fault(__idx)\
5158 bf_get(lpfc_acqe_fc_la_trunk_config_port##__idx, acqe_fc) ?\
5159 (port_fault & (1 << __idx) ? "YES" : "NO") : "NA"
5160
5161static void
5162lpfc_update_trunk_link_status(struct lpfc_hba *phba,
5163 struct lpfc_acqe_fc_la *acqe_fc)
5164{
5165 uint8_t port_fault = bf_get(lpfc_acqe_fc_la_trunk_linkmask, acqe_fc);
5166 uint8_t err = bf_get(lpfc_acqe_fc_la_trunk_fault, acqe_fc);
5167
5168 phba->sli4_hba.link_state.speed =
5169 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
5170 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
5171
5172 phba->sli4_hba.link_state.logical_speed =
b8e6f136 5173 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
1dc5ec24
JS
5174 /* We got FC link speed, convert to fc_linkspeed (READ_TOPOLOGY) */
5175 phba->fc_linkspeed =
5176 lpfc_async_link_speed_to_read_top(
5177 phba,
5178 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
5179
5180 if (bf_get(lpfc_acqe_fc_la_trunk_config_port0, acqe_fc)) {
5181 phba->trunk_link.link0.state =
5182 bf_get(lpfc_acqe_fc_la_trunk_link_status_port0, acqe_fc)
5183 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5184 phba->trunk_link.link0.fault = port_fault & 0x1 ? err : 0;
1dc5ec24
JS
5185 }
5186 if (bf_get(lpfc_acqe_fc_la_trunk_config_port1, acqe_fc)) {
5187 phba->trunk_link.link1.state =
5188 bf_get(lpfc_acqe_fc_la_trunk_link_status_port1, acqe_fc)
5189 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5190 phba->trunk_link.link1.fault = port_fault & 0x2 ? err : 0;
1dc5ec24
JS
5191 }
5192 if (bf_get(lpfc_acqe_fc_la_trunk_config_port2, acqe_fc)) {
5193 phba->trunk_link.link2.state =
5194 bf_get(lpfc_acqe_fc_la_trunk_link_status_port2, acqe_fc)
5195 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5196 phba->trunk_link.link2.fault = port_fault & 0x4 ? err : 0;
1dc5ec24
JS
5197 }
5198 if (bf_get(lpfc_acqe_fc_la_trunk_config_port3, acqe_fc)) {
5199 phba->trunk_link.link3.state =
5200 bf_get(lpfc_acqe_fc_la_trunk_link_status_port3, acqe_fc)
5201 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5202 phba->trunk_link.link3.fault = port_fault & 0x8 ? err : 0;
1dc5ec24
JS
5203 }
5204
372c187b 5205 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1dc5ec24
JS
5206 "2910 Async FC Trunking Event - Speed:%d\n"
5207 "\tLogical speed:%d "
5208 "port0: %s port1: %s port2: %s port3: %s\n",
5209 phba->sli4_hba.link_state.speed,
5210 phba->sli4_hba.link_state.logical_speed,
5211 trunk_link_status(0), trunk_link_status(1),
5212 trunk_link_status(2), trunk_link_status(3));
5213
5214 if (port_fault)
372c187b 5215 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1dc5ec24
JS
5216 "3202 trunk error:0x%x (%s) seen on port0:%s "
5217 /*
5218 * SLI-4: We have only 0xA error codes
5219 * defined as of now. print an appropriate
5220 * message in case driver needs to be updated.
5221 */
5222 "port1:%s port2:%s port3:%s\n", err, err > 0xA ?
5223 "UNDEFINED. update driver." : trunk_errmsg[err],
5224 trunk_port_fault(0), trunk_port_fault(1),
5225 trunk_port_fault(2), trunk_port_fault(3));
5226}
5227
5228
70f3c073
JS
5229/**
5230 * lpfc_sli4_async_fc_evt - Process the asynchronous FC link event
5231 * @phba: pointer to lpfc hba data structure.
5232 * @acqe_fc: pointer to the async fc completion queue entry.
5233 *
5234 * This routine is to handle the SLI4 asynchronous FC event. It will simply log
5235 * that the event was received and then issue a read_topology mailbox command so
5236 * that the rest of the driver will treat it the same as SLI3.
5237 **/
5238static void
5239lpfc_sli4_async_fc_evt(struct lpfc_hba *phba, struct lpfc_acqe_fc_la *acqe_fc)
5240{
5241 struct lpfc_dmabuf *mp;
5242 LPFC_MBOXQ_t *pmb;
7bdedb34
JS
5243 MAILBOX_t *mb;
5244 struct lpfc_mbx_read_top *la;
70f3c073
JS
5245 int rc;
5246
5247 if (bf_get(lpfc_trailer_type, acqe_fc) !=
5248 LPFC_FC_LA_EVENT_TYPE_FC_LINK) {
372c187b 5249 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
70f3c073
JS
5250 "2895 Non FC link Event detected.(%d)\n",
5251 bf_get(lpfc_trailer_type, acqe_fc));
5252 return;
5253 }
1dc5ec24
JS
5254
5255 if (bf_get(lpfc_acqe_fc_la_att_type, acqe_fc) ==
5256 LPFC_FC_LA_TYPE_TRUNKING_EVENT) {
5257 lpfc_update_trunk_link_status(phba, acqe_fc);
5258 return;
5259 }
5260
70f3c073
JS
5261 /* Keep the link status for extra SLI4 state machine reference */
5262 phba->sli4_hba.link_state.speed =
8b68cd52
JS
5263 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
5264 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
70f3c073
JS
5265 phba->sli4_hba.link_state.duplex = LPFC_ASYNC_LINK_DUPLEX_FULL;
5266 phba->sli4_hba.link_state.topology =
5267 bf_get(lpfc_acqe_fc_la_topology, acqe_fc);
5268 phba->sli4_hba.link_state.status =
5269 bf_get(lpfc_acqe_fc_la_att_type, acqe_fc);
5270 phba->sli4_hba.link_state.type =
5271 bf_get(lpfc_acqe_fc_la_port_type, acqe_fc);
5272 phba->sli4_hba.link_state.number =
5273 bf_get(lpfc_acqe_fc_la_port_number, acqe_fc);
5274 phba->sli4_hba.link_state.fault =
5275 bf_get(lpfc_acqe_link_fault, acqe_fc);
b8e6f136
JS
5276
5277 if (bf_get(lpfc_acqe_fc_la_att_type, acqe_fc) ==
5278 LPFC_FC_LA_TYPE_LINK_DOWN)
5279 phba->sli4_hba.link_state.logical_speed = 0;
5280 else if (!phba->sli4_hba.conf_trunk)
5281 phba->sli4_hba.link_state.logical_speed =
8b68cd52 5282 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
b8e6f136 5283
70f3c073
JS
5284 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5285 "2896 Async FC event - Speed:%dGBaud Topology:x%x "
5286 "LA Type:x%x Port Type:%d Port Number:%d Logical speed:"
5287 "%dMbps Fault:%d\n",
5288 phba->sli4_hba.link_state.speed,
5289 phba->sli4_hba.link_state.topology,
5290 phba->sli4_hba.link_state.status,
5291 phba->sli4_hba.link_state.type,
5292 phba->sli4_hba.link_state.number,
8b68cd52 5293 phba->sli4_hba.link_state.logical_speed,
70f3c073
JS
5294 phba->sli4_hba.link_state.fault);
5295 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
5296 if (!pmb) {
372c187b 5297 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
70f3c073
JS
5298 "2897 The mboxq allocation failed\n");
5299 return;
5300 }
5301 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
5302 if (!mp) {
372c187b 5303 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
70f3c073
JS
5304 "2898 The lpfc_dmabuf allocation failed\n");
5305 goto out_free_pmb;
5306 }
5307 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
5308 if (!mp->virt) {
372c187b 5309 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
70f3c073
JS
5310 "2899 The mbuf allocation failed\n");
5311 goto out_free_dmabuf;
5312 }
5313
5314 /* Cleanup any outstanding ELS commands */
5315 lpfc_els_flush_all_cmd(phba);
5316
5317 /* Block ELS IOCBs until we have done process link event */
895427bd 5318 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
70f3c073
JS
5319
5320 /* Update link event statistics */
5321 phba->sli.slistat.link_event++;
5322
5323 /* Create lpfc_handle_latt mailbox command from link ACQE */
5324 lpfc_read_topology(phba, pmb, mp);
5325 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
5326 pmb->vport = phba->pport;
5327
7bdedb34 5328 if (phba->sli4_hba.link_state.status != LPFC_FC_LA_TYPE_LINK_UP) {
ae9e28f3
JS
5329 phba->link_flag &= ~(LS_MDS_LINK_DOWN | LS_MDS_LOOPBACK);
5330
5331 switch (phba->sli4_hba.link_state.status) {
5332 case LPFC_FC_LA_TYPE_MDS_LINK_DOWN:
5333 phba->link_flag |= LS_MDS_LINK_DOWN;
5334 break;
5335 case LPFC_FC_LA_TYPE_MDS_LOOPBACK:
5336 phba->link_flag |= LS_MDS_LOOPBACK;
5337 break;
5338 default:
5339 break;
5340 }
5341
23288b78 5342 /* Initialize completion status */
7bdedb34 5343 mb = &pmb->u.mb;
23288b78
JS
5344 mb->mbxStatus = MBX_SUCCESS;
5345
5346 /* Parse port fault information field */
5347 lpfc_sli4_parse_latt_fault(phba, (void *)acqe_fc);
7bdedb34
JS
5348
5349 /* Parse and translate link attention fields */
5350 la = (struct lpfc_mbx_read_top *)&pmb->u.mb.un.varReadTop;
5351 la->eventTag = acqe_fc->event_tag;
7bdedb34 5352
aeb3c817
JS
5353 if (phba->sli4_hba.link_state.status ==
5354 LPFC_FC_LA_TYPE_UNEXP_WWPN) {
5355 bf_set(lpfc_mbx_read_top_att_type, la,
5356 LPFC_FC_LA_TYPE_UNEXP_WWPN);
5357 } else {
5358 bf_set(lpfc_mbx_read_top_att_type, la,
5359 LPFC_FC_LA_TYPE_LINK_DOWN);
5360 }
7bdedb34
JS
5361 /* Invoke the mailbox command callback function */
5362 lpfc_mbx_cmpl_read_topology(phba, pmb);
5363
5364 return;
5365 }
5366
70f3c073
JS
5367 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
5368 if (rc == MBX_NOT_FINISHED)
5369 goto out_free_dmabuf;
5370 return;
5371
5372out_free_dmabuf:
5373 kfree(mp);
5374out_free_pmb:
5375 mempool_free(pmb, phba->mbox_mem_pool);
5376}
5377
5378/**
5379 * lpfc_sli4_async_sli_evt - Process the asynchronous SLI link event
5380 * @phba: pointer to lpfc hba data structure.
fe614acd 5381 * @acqe_sli: pointer to the async SLI completion queue entry.
70f3c073
JS
5382 *
5383 * This routine is to handle the SLI4 asynchronous SLI events.
5384 **/
5385static void
5386lpfc_sli4_async_sli_evt(struct lpfc_hba *phba, struct lpfc_acqe_sli *acqe_sli)
5387{
4b8bae08 5388 char port_name;
8c1312e1 5389 char message[128];
4b8bae08 5390 uint8_t status;
946727dc 5391 uint8_t evt_type;
448193b5 5392 uint8_t operational = 0;
946727dc 5393 struct temp_event temp_event_data;
4b8bae08 5394 struct lpfc_acqe_misconfigured_event *misconfigured;
946727dc 5395 struct Scsi_Host *shost;
cd71348a
JS
5396 struct lpfc_vport **vports;
5397 int rc, i;
946727dc
JS
5398
5399 evt_type = bf_get(lpfc_trailer_type, acqe_sli);
4b8bae08 5400
448193b5 5401 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
d11ed16d
JS
5402 "2901 Async SLI event - Type:%d, Event Data: x%08x "
5403 "x%08x x%08x x%08x\n", evt_type,
448193b5 5404 acqe_sli->event_data1, acqe_sli->event_data2,
d11ed16d 5405 acqe_sli->reserved, acqe_sli->trailer);
4b8bae08
JS
5406
5407 port_name = phba->Port[0];
5408 if (port_name == 0x00)
5409 port_name = '?'; /* get port name is empty */
5410
946727dc
JS
5411 switch (evt_type) {
5412 case LPFC_SLI_EVENT_TYPE_OVER_TEMP:
5413 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
5414 temp_event_data.event_code = LPFC_THRESHOLD_TEMP;
5415 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
5416
5417 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
5418 "3190 Over Temperature:%d Celsius- Port Name %c\n",
5419 acqe_sli->event_data1, port_name);
5420
310429ef 5421 phba->sfp_warning |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
946727dc
JS
5422 shost = lpfc_shost_from_vport(phba->pport);
5423 fc_host_post_vendor_event(shost, fc_get_event_number(),
5424 sizeof(temp_event_data),
5425 (char *)&temp_event_data,
5426 SCSI_NL_VID_TYPE_PCI
5427 | PCI_VENDOR_ID_EMULEX);
5428 break;
5429 case LPFC_SLI_EVENT_TYPE_NORM_TEMP:
5430 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
5431 temp_event_data.event_code = LPFC_NORMAL_TEMP;
5432 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
5433
5434 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5435 "3191 Normal Temperature:%d Celsius - Port Name %c\n",
5436 acqe_sli->event_data1, port_name);
5437
5438 shost = lpfc_shost_from_vport(phba->pport);
5439 fc_host_post_vendor_event(shost, fc_get_event_number(),
5440 sizeof(temp_event_data),
5441 (char *)&temp_event_data,
5442 SCSI_NL_VID_TYPE_PCI
5443 | PCI_VENDOR_ID_EMULEX);
5444 break;
5445 case LPFC_SLI_EVENT_TYPE_MISCONFIGURED:
5446 misconfigured = (struct lpfc_acqe_misconfigured_event *)
4b8bae08
JS
5447 &acqe_sli->event_data1;
5448
946727dc
JS
5449 /* fetch the status for this port */
5450 switch (phba->sli4_hba.lnk_info.lnk_no) {
5451 case LPFC_LINK_NUMBER_0:
448193b5
JS
5452 status = bf_get(lpfc_sli_misconfigured_port0_state,
5453 &misconfigured->theEvent);
5454 operational = bf_get(lpfc_sli_misconfigured_port0_op,
4b8bae08 5455 &misconfigured->theEvent);
946727dc
JS
5456 break;
5457 case LPFC_LINK_NUMBER_1:
448193b5
JS
5458 status = bf_get(lpfc_sli_misconfigured_port1_state,
5459 &misconfigured->theEvent);
5460 operational = bf_get(lpfc_sli_misconfigured_port1_op,
4b8bae08 5461 &misconfigured->theEvent);
946727dc
JS
5462 break;
5463 case LPFC_LINK_NUMBER_2:
448193b5
JS
5464 status = bf_get(lpfc_sli_misconfigured_port2_state,
5465 &misconfigured->theEvent);
5466 operational = bf_get(lpfc_sli_misconfigured_port2_op,
4b8bae08 5467 &misconfigured->theEvent);
946727dc
JS
5468 break;
5469 case LPFC_LINK_NUMBER_3:
448193b5
JS
5470 status = bf_get(lpfc_sli_misconfigured_port3_state,
5471 &misconfigured->theEvent);
5472 operational = bf_get(lpfc_sli_misconfigured_port3_op,
4b8bae08 5473 &misconfigured->theEvent);
946727dc
JS
5474 break;
5475 default:
372c187b 5476 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
448193b5
JS
5477 "3296 "
5478 "LPFC_SLI_EVENT_TYPE_MISCONFIGURED "
5479 "event: Invalid link %d",
5480 phba->sli4_hba.lnk_info.lnk_no);
5481 return;
946727dc 5482 }
4b8bae08 5483
448193b5
JS
5484 /* Skip if optic state unchanged */
5485 if (phba->sli4_hba.lnk_info.optic_state == status)
5486 return;
5487
946727dc
JS
5488 switch (status) {
5489 case LPFC_SLI_EVENT_STATUS_VALID:
448193b5
JS
5490 sprintf(message, "Physical Link is functional");
5491 break;
946727dc
JS
5492 case LPFC_SLI_EVENT_STATUS_NOT_PRESENT:
5493 sprintf(message, "Optics faulted/incorrectly "
5494 "installed/not installed - Reseat optics, "
5495 "if issue not resolved, replace.");
5496 break;
5497 case LPFC_SLI_EVENT_STATUS_WRONG_TYPE:
5498 sprintf(message,
5499 "Optics of two types installed - Remove one "
5500 "optic or install matching pair of optics.");
5501 break;
5502 case LPFC_SLI_EVENT_STATUS_UNSUPPORTED:
5503 sprintf(message, "Incompatible optics - Replace with "
292098be 5504 "compatible optics for card to function.");
946727dc 5505 break;
448193b5
JS
5506 case LPFC_SLI_EVENT_STATUS_UNQUALIFIED:
5507 sprintf(message, "Unqualified optics - Replace with "
5508 "Avago optics for Warranty and Technical "
5509 "Support - Link is%s operational",
2ea259ee 5510 (operational) ? " not" : "");
448193b5
JS
5511 break;
5512 case LPFC_SLI_EVENT_STATUS_UNCERTIFIED:
5513 sprintf(message, "Uncertified optics - Replace with "
5514 "Avago-certified optics to enable link "
5515 "operation - Link is%s operational",
2ea259ee 5516 (operational) ? " not" : "");
448193b5 5517 break;
946727dc
JS
5518 default:
5519 /* firmware is reporting a status we don't know about */
5520 sprintf(message, "Unknown event status x%02x", status);
5521 break;
5522 }
cd71348a
JS
5523
5524 /* Issue READ_CONFIG mbox command to refresh supported speeds */
5525 rc = lpfc_sli4_read_config(phba);
3952e91f 5526 if (rc) {
cd71348a 5527 phba->lmt = 0;
372c187b
DK
5528 lpfc_printf_log(phba, KERN_ERR,
5529 LOG_TRACE_EVENT,
cd71348a 5530 "3194 Unable to retrieve supported "
3952e91f 5531 "speeds, rc = 0x%x\n", rc);
cd71348a
JS
5532 }
5533 vports = lpfc_create_vport_work_array(phba);
5534 if (vports != NULL) {
5535 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
5536 i++) {
5537 shost = lpfc_shost_from_vport(vports[i]);
5538 lpfc_host_supported_speeds_set(shost);
5539 }
5540 }
5541 lpfc_destroy_vport_work_array(phba, vports);
5542
448193b5 5543 phba->sli4_hba.lnk_info.optic_state = status;
946727dc 5544 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
448193b5 5545 "3176 Port Name %c %s\n", port_name, message);
946727dc
JS
5546 break;
5547 case LPFC_SLI_EVENT_TYPE_REMOTE_DPORT:
5548 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5549 "3192 Remote DPort Test Initiated - "
5550 "Event Data1:x%08x Event Data2: x%08x\n",
5551 acqe_sli->event_data1, acqe_sli->event_data2);
4b8bae08 5552 break;
e7d85952
JS
5553 case LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN:
5554 /* Misconfigured WWN. Reports that the SLI Port is configured
5555 * to use FA-WWN, but the attached device doesn’t support it.
5556 * No driver action is required.
5557 * Event Data1 - N.A, Event Data2 - N.A
5558 */
5559 lpfc_log_msg(phba, KERN_WARNING, LOG_SLI,
5560 "2699 Misconfigured FA-WWN - Attached device does "
5561 "not support FA-WWN\n");
5562 break;
d11ed16d
JS
5563 case LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE:
5564 /* EEPROM failure. No driver action is required */
5565 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
5566 "2518 EEPROM failure - "
5567 "Event Data1: x%08x Event Data2: x%08x\n",
5568 acqe_sli->event_data1, acqe_sli->event_data2);
5569 break;
4b8bae08 5570 default:
946727dc 5571 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
d11ed16d 5572 "3193 Unrecognized SLI event, type: 0x%x",
946727dc 5573 evt_type);
4b8bae08
JS
5574 break;
5575 }
70f3c073
JS
5576}
5577
fc2b989b
JS
5578/**
5579 * lpfc_sli4_perform_vport_cvl - Perform clear virtual link on a vport
5580 * @vport: pointer to vport data structure.
5581 *
5582 * This routine is to perform Clear Virtual Link (CVL) on a vport in
5583 * response to a CVL event.
5584 *
5585 * Return the pointer to the ndlp with the vport if successful, otherwise
5586 * return NULL.
5587 **/
5588static struct lpfc_nodelist *
5589lpfc_sli4_perform_vport_cvl(struct lpfc_vport *vport)
5590{
5591 struct lpfc_nodelist *ndlp;
5592 struct Scsi_Host *shost;
5593 struct lpfc_hba *phba;
5594
5595 if (!vport)
5596 return NULL;
fc2b989b
JS
5597 phba = vport->phba;
5598 if (!phba)
5599 return NULL;
78730cfe
JS
5600 ndlp = lpfc_findnode_did(vport, Fabric_DID);
5601 if (!ndlp) {
5602 /* Cannot find existing Fabric ndlp, so allocate a new one */
9d3d340d 5603 ndlp = lpfc_nlp_init(vport, Fabric_DID);
78730cfe
JS
5604 if (!ndlp)
5605 return 0;
78730cfe
JS
5606 /* Set the node type */
5607 ndlp->nlp_type |= NLP_FABRIC;
5608 /* Put ndlp onto node list */
5609 lpfc_enqueue_node(vport, ndlp);
5610 } else if (!NLP_CHK_NODE_ACT(ndlp)) {
5611 /* re-setup ndlp without removing from node list */
5612 ndlp = lpfc_enable_node(vport, ndlp, NLP_STE_UNUSED_NODE);
5613 if (!ndlp)
5614 return 0;
5615 }
63e801ce
JS
5616 if ((phba->pport->port_state < LPFC_FLOGI) &&
5617 (phba->pport->port_state != LPFC_VPORT_FAILED))
fc2b989b
JS
5618 return NULL;
5619 /* If virtual link is not yet instantiated ignore CVL */
63e801ce
JS
5620 if ((vport != phba->pport) && (vport->port_state < LPFC_FDISC)
5621 && (vport->port_state != LPFC_VPORT_FAILED))
fc2b989b
JS
5622 return NULL;
5623 shost = lpfc_shost_from_vport(vport);
5624 if (!shost)
5625 return NULL;
5626 lpfc_linkdown_port(vport);
5627 lpfc_cleanup_pending_mbox(vport);
5628 spin_lock_irq(shost->host_lock);
5629 vport->fc_flag |= FC_VPORT_CVL_RCVD;
5630 spin_unlock_irq(shost->host_lock);
5631
5632 return ndlp;
5633}
5634
5635/**
5636 * lpfc_sli4_perform_all_vport_cvl - Perform clear virtual link on all vports
fe614acd 5637 * @phba: pointer to lpfc hba data structure.
fc2b989b
JS
5638 *
5639 * This routine is to perform Clear Virtual Link (CVL) on all vports in
5640 * response to a FCF dead event.
5641 **/
5642static void
5643lpfc_sli4_perform_all_vport_cvl(struct lpfc_hba *phba)
5644{
5645 struct lpfc_vport **vports;
5646 int i;
5647
5648 vports = lpfc_create_vport_work_array(phba);
5649 if (vports)
5650 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
5651 lpfc_sli4_perform_vport_cvl(vports[i]);
5652 lpfc_destroy_vport_work_array(phba, vports);
5653}
5654
da0436e9 5655/**
76a95d75 5656 * lpfc_sli4_async_fip_evt - Process the asynchronous FCoE FIP event
da0436e9 5657 * @phba: pointer to lpfc hba data structure.
fe614acd 5658 * @acqe_fip: pointer to the async fcoe completion queue entry.
da0436e9
JS
5659 *
5660 * This routine is to handle the SLI4 asynchronous fcoe event.
5661 **/
5662static void
76a95d75 5663lpfc_sli4_async_fip_evt(struct lpfc_hba *phba,
70f3c073 5664 struct lpfc_acqe_fip *acqe_fip)
da0436e9 5665{
70f3c073 5666 uint8_t event_type = bf_get(lpfc_trailer_type, acqe_fip);
da0436e9 5667 int rc;
6669f9bb
JS
5668 struct lpfc_vport *vport;
5669 struct lpfc_nodelist *ndlp;
5670 struct Scsi_Host *shost;
695a814e
JS
5671 int active_vlink_present;
5672 struct lpfc_vport **vports;
5673 int i;
da0436e9 5674
70f3c073
JS
5675 phba->fc_eventTag = acqe_fip->event_tag;
5676 phba->fcoe_eventtag = acqe_fip->event_tag;
da0436e9 5677 switch (event_type) {
70f3c073
JS
5678 case LPFC_FIP_EVENT_TYPE_NEW_FCF:
5679 case LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD:
5680 if (event_type == LPFC_FIP_EVENT_TYPE_NEW_FCF)
372c187b 5681 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
a93ff37a
JS
5682 "2546 New FCF event, evt_tag:x%x, "
5683 "index:x%x\n",
70f3c073
JS
5684 acqe_fip->event_tag,
5685 acqe_fip->index);
999d813f
JS
5686 else
5687 lpfc_printf_log(phba, KERN_WARNING, LOG_FIP |
5688 LOG_DISCOVERY,
a93ff37a
JS
5689 "2788 FCF param modified event, "
5690 "evt_tag:x%x, index:x%x\n",
70f3c073
JS
5691 acqe_fip->event_tag,
5692 acqe_fip->index);
38b92ef8 5693 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
0c9ab6f5
JS
5694 /*
5695 * During period of FCF discovery, read the FCF
5696 * table record indexed by the event to update
a93ff37a 5697 * FCF roundrobin failover eligible FCF bmask.
0c9ab6f5
JS
5698 */
5699 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
5700 LOG_DISCOVERY,
a93ff37a
JS
5701 "2779 Read FCF (x%x) for updating "
5702 "roundrobin FCF failover bmask\n",
70f3c073
JS
5703 acqe_fip->index);
5704 rc = lpfc_sli4_read_fcf_rec(phba, acqe_fip->index);
0c9ab6f5 5705 }
38b92ef8
JS
5706
5707 /* If the FCF discovery is in progress, do nothing. */
3804dc84 5708 spin_lock_irq(&phba->hbalock);
a93ff37a 5709 if (phba->hba_flag & FCF_TS_INPROG) {
38b92ef8
JS
5710 spin_unlock_irq(&phba->hbalock);
5711 break;
5712 }
5713 /* If fast FCF failover rescan event is pending, do nothing */
036cad1f 5714 if (phba->fcf.fcf_flag & (FCF_REDISC_EVT | FCF_REDISC_PEND)) {
38b92ef8
JS
5715 spin_unlock_irq(&phba->hbalock);
5716 break;
5717 }
5718
c2b9712e
JS
5719 /* If the FCF has been in discovered state, do nothing. */
5720 if (phba->fcf.fcf_flag & FCF_SCAN_DONE) {
3804dc84
JS
5721 spin_unlock_irq(&phba->hbalock);
5722 break;
5723 }
5724 spin_unlock_irq(&phba->hbalock);
38b92ef8 5725
0c9ab6f5
JS
5726 /* Otherwise, scan the entire FCF table and re-discover SAN */
5727 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
a93ff37a
JS
5728 "2770 Start FCF table scan per async FCF "
5729 "event, evt_tag:x%x, index:x%x\n",
70f3c073 5730 acqe_fip->event_tag, acqe_fip->index);
0c9ab6f5
JS
5731 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba,
5732 LPFC_FCOE_FCF_GET_FIRST);
da0436e9 5733 if (rc)
372c187b 5734 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0c9ab6f5 5735 "2547 Issue FCF scan read FCF mailbox "
a93ff37a 5736 "command failed (x%x)\n", rc);
da0436e9
JS
5737 break;
5738
70f3c073 5739 case LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL:
372c187b
DK
5740 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5741 "2548 FCF Table full count 0x%x tag 0x%x\n",
5742 bf_get(lpfc_acqe_fip_fcf_count, acqe_fip),
5743 acqe_fip->event_tag);
da0436e9
JS
5744 break;
5745
70f3c073 5746 case LPFC_FIP_EVENT_TYPE_FCF_DEAD:
80c17849 5747 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
372c187b
DK
5748 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5749 "2549 FCF (x%x) disconnected from network, "
5750 "tag:x%x\n", acqe_fip->index,
5751 acqe_fip->event_tag);
38b92ef8
JS
5752 /*
5753 * If we are in the middle of FCF failover process, clear
5754 * the corresponding FCF bit in the roundrobin bitmap.
da0436e9 5755 */
fc2b989b 5756 spin_lock_irq(&phba->hbalock);
a1cadfef
JS
5757 if ((phba->fcf.fcf_flag & FCF_DISCOVERY) &&
5758 (phba->fcf.current_rec.fcf_indx != acqe_fip->index)) {
fc2b989b 5759 spin_unlock_irq(&phba->hbalock);
0c9ab6f5 5760 /* Update FLOGI FCF failover eligible FCF bmask */
70f3c073 5761 lpfc_sli4_fcf_rr_index_clear(phba, acqe_fip->index);
fc2b989b
JS
5762 break;
5763 }
38b92ef8
JS
5764 spin_unlock_irq(&phba->hbalock);
5765
5766 /* If the event is not for currently used fcf do nothing */
70f3c073 5767 if (phba->fcf.current_rec.fcf_indx != acqe_fip->index)
38b92ef8
JS
5768 break;
5769
5770 /*
5771 * Otherwise, request the port to rediscover the entire FCF
5772 * table for a fast recovery from case that the current FCF
5773 * is no longer valid as we are not in the middle of FCF
5774 * failover process already.
5775 */
c2b9712e
JS
5776 spin_lock_irq(&phba->hbalock);
5777 /* Mark the fast failover process in progress */
5778 phba->fcf.fcf_flag |= FCF_DEAD_DISC;
5779 spin_unlock_irq(&phba->hbalock);
5780
5781 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
5782 "2771 Start FCF fast failover process due to "
5783 "FCF DEAD event: evt_tag:x%x, fcf_index:x%x "
5784 "\n", acqe_fip->event_tag, acqe_fip->index);
5785 rc = lpfc_sli4_redisc_fcf_table(phba);
5786 if (rc) {
5787 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
372c187b 5788 LOG_TRACE_EVENT,
7afc0ce9 5789 "2772 Issue FCF rediscover mailbox "
c2b9712e
JS
5790 "command failed, fail through to FCF "
5791 "dead event\n");
5792 spin_lock_irq(&phba->hbalock);
5793 phba->fcf.fcf_flag &= ~FCF_DEAD_DISC;
5794 spin_unlock_irq(&phba->hbalock);
5795 /*
5796 * Last resort will fail over by treating this
5797 * as a link down to FCF registration.
5798 */
5799 lpfc_sli4_fcf_dead_failthrough(phba);
5800 } else {
5801 /* Reset FCF roundrobin bmask for new discovery */
5802 lpfc_sli4_clear_fcf_rr_bmask(phba);
5803 /*
5804 * Handling fast FCF failover to a DEAD FCF event is
5805 * considered equalivant to receiving CVL to all vports.
5806 */
5807 lpfc_sli4_perform_all_vport_cvl(phba);
5808 }
da0436e9 5809 break;
70f3c073 5810 case LPFC_FIP_EVENT_TYPE_CVL:
80c17849 5811 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
372c187b
DK
5812 lpfc_printf_log(phba, KERN_ERR,
5813 LOG_TRACE_EVENT,
6669f9bb 5814 "2718 Clear Virtual Link Received for VPI 0x%x"
70f3c073 5815 " tag 0x%x\n", acqe_fip->index, acqe_fip->event_tag);
6d368e53 5816
6669f9bb 5817 vport = lpfc_find_vport_by_vpid(phba,
5248a749 5818 acqe_fip->index);
fc2b989b 5819 ndlp = lpfc_sli4_perform_vport_cvl(vport);
6669f9bb
JS
5820 if (!ndlp)
5821 break;
695a814e
JS
5822 active_vlink_present = 0;
5823
5824 vports = lpfc_create_vport_work_array(phba);
5825 if (vports) {
5826 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
5827 i++) {
5828 if ((!(vports[i]->fc_flag &
5829 FC_VPORT_CVL_RCVD)) &&
5830 (vports[i]->port_state > LPFC_FDISC)) {
5831 active_vlink_present = 1;
5832 break;
5833 }
5834 }
5835 lpfc_destroy_vport_work_array(phba, vports);
5836 }
5837
cc82355a
JS
5838 /*
5839 * Don't re-instantiate if vport is marked for deletion.
5840 * If we are here first then vport_delete is going to wait
5841 * for discovery to complete.
5842 */
5843 if (!(vport->load_flag & FC_UNLOADING) &&
5844 active_vlink_present) {
695a814e
JS
5845 /*
5846 * If there are other active VLinks present,
5847 * re-instantiate the Vlink using FDISC.
5848 */
256ec0d0
JS
5849 mod_timer(&ndlp->nlp_delayfunc,
5850 jiffies + msecs_to_jiffies(1000));
fc2b989b 5851 shost = lpfc_shost_from_vport(vport);
6669f9bb
JS
5852 spin_lock_irq(shost->host_lock);
5853 ndlp->nlp_flag |= NLP_DELAY_TMO;
5854 spin_unlock_irq(shost->host_lock);
695a814e
JS
5855 ndlp->nlp_last_elscmd = ELS_CMD_FDISC;
5856 vport->port_state = LPFC_FDISC;
5857 } else {
ecfd03c6
JS
5858 /*
5859 * Otherwise, we request port to rediscover
5860 * the entire FCF table for a fast recovery
5861 * from possible case that the current FCF
0c9ab6f5
JS
5862 * is no longer valid if we are not already
5863 * in the FCF failover process.
ecfd03c6 5864 */
fc2b989b 5865 spin_lock_irq(&phba->hbalock);
0c9ab6f5 5866 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
fc2b989b
JS
5867 spin_unlock_irq(&phba->hbalock);
5868 break;
5869 }
5870 /* Mark the fast failover process in progress */
0c9ab6f5 5871 phba->fcf.fcf_flag |= FCF_ACVL_DISC;
fc2b989b 5872 spin_unlock_irq(&phba->hbalock);
0c9ab6f5
JS
5873 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
5874 LOG_DISCOVERY,
a93ff37a 5875 "2773 Start FCF failover per CVL, "
70f3c073 5876 "evt_tag:x%x\n", acqe_fip->event_tag);
ecfd03c6 5877 rc = lpfc_sli4_redisc_fcf_table(phba);
fc2b989b 5878 if (rc) {
0c9ab6f5 5879 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
372c187b 5880 LOG_TRACE_EVENT,
0c9ab6f5 5881 "2774 Issue FCF rediscover "
7afc0ce9 5882 "mailbox command failed, "
0c9ab6f5 5883 "through to CVL event\n");
fc2b989b 5884 spin_lock_irq(&phba->hbalock);
0c9ab6f5 5885 phba->fcf.fcf_flag &= ~FCF_ACVL_DISC;
fc2b989b 5886 spin_unlock_irq(&phba->hbalock);
ecfd03c6
JS
5887 /*
5888 * Last resort will be re-try on the
5889 * the current registered FCF entry.
5890 */
5891 lpfc_retry_pport_discovery(phba);
38b92ef8
JS
5892 } else
5893 /*
5894 * Reset FCF roundrobin bmask for new
5895 * discovery.
5896 */
7d791df7 5897 lpfc_sli4_clear_fcf_rr_bmask(phba);
6669f9bb
JS
5898 }
5899 break;
da0436e9 5900 default:
372c187b
DK
5901 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5902 "0288 Unknown FCoE event type 0x%x event tag "
5903 "0x%x\n", event_type, acqe_fip->event_tag);
da0436e9
JS
5904 break;
5905 }
5906}
5907
5908/**
5909 * lpfc_sli4_async_dcbx_evt - Process the asynchronous dcbx event
5910 * @phba: pointer to lpfc hba data structure.
fe614acd 5911 * @acqe_dcbx: pointer to the async dcbx completion queue entry.
da0436e9
JS
5912 *
5913 * This routine is to handle the SLI4 asynchronous dcbx event.
5914 **/
5915static void
5916lpfc_sli4_async_dcbx_evt(struct lpfc_hba *phba,
5917 struct lpfc_acqe_dcbx *acqe_dcbx)
5918{
4d9ab994 5919 phba->fc_eventTag = acqe_dcbx->event_tag;
372c187b 5920 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
5921 "0290 The SLI4 DCBX asynchronous event is not "
5922 "handled yet\n");
5923}
5924
b19a061a
JS
5925/**
5926 * lpfc_sli4_async_grp5_evt - Process the asynchronous group5 event
5927 * @phba: pointer to lpfc hba data structure.
fe614acd 5928 * @acqe_grp5: pointer to the async grp5 completion queue entry.
b19a061a
JS
5929 *
5930 * This routine is to handle the SLI4 asynchronous grp5 event. A grp5 event
5931 * is an asynchronous notified of a logical link speed change. The Port
5932 * reports the logical link speed in units of 10Mbps.
5933 **/
5934static void
5935lpfc_sli4_async_grp5_evt(struct lpfc_hba *phba,
5936 struct lpfc_acqe_grp5 *acqe_grp5)
5937{
5938 uint16_t prev_ll_spd;
5939
5940 phba->fc_eventTag = acqe_grp5->event_tag;
5941 phba->fcoe_eventtag = acqe_grp5->event_tag;
5942 prev_ll_spd = phba->sli4_hba.link_state.logical_speed;
5943 phba->sli4_hba.link_state.logical_speed =
8b68cd52 5944 (bf_get(lpfc_acqe_grp5_llink_spd, acqe_grp5)) * 10;
b19a061a
JS
5945 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5946 "2789 GRP5 Async Event: Updating logical link speed "
8b68cd52
JS
5947 "from %dMbps to %dMbps\n", prev_ll_spd,
5948 phba->sli4_hba.link_state.logical_speed);
b19a061a
JS
5949}
5950
da0436e9
JS
5951/**
5952 * lpfc_sli4_async_event_proc - Process all the pending asynchronous event
5953 * @phba: pointer to lpfc hba data structure.
5954 *
5955 * This routine is invoked by the worker thread to process all the pending
5956 * SLI4 asynchronous events.
5957 **/
5958void lpfc_sli4_async_event_proc(struct lpfc_hba *phba)
5959{
5960 struct lpfc_cq_event *cq_event;
e7dab164 5961 unsigned long iflags;
da0436e9
JS
5962
5963 /* First, declare the async event has been handled */
e7dab164 5964 spin_lock_irqsave(&phba->hbalock, iflags);
da0436e9 5965 phba->hba_flag &= ~ASYNC_EVENT;
e7dab164
JS
5966 spin_unlock_irqrestore(&phba->hbalock, iflags);
5967
da0436e9 5968 /* Now, handle all the async events */
e7dab164 5969 spin_lock_irqsave(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9 5970 while (!list_empty(&phba->sli4_hba.sp_asynce_work_queue)) {
da0436e9
JS
5971 list_remove_head(&phba->sli4_hba.sp_asynce_work_queue,
5972 cq_event, struct lpfc_cq_event, list);
e7dab164
JS
5973 spin_unlock_irqrestore(&phba->sli4_hba.asynce_list_lock,
5974 iflags);
5975
da0436e9
JS
5976 /* Process the asynchronous event */
5977 switch (bf_get(lpfc_trailer_code, &cq_event->cqe.mcqe_cmpl)) {
5978 case LPFC_TRAILER_CODE_LINK:
5979 lpfc_sli4_async_link_evt(phba,
5980 &cq_event->cqe.acqe_link);
5981 break;
5982 case LPFC_TRAILER_CODE_FCOE:
70f3c073 5983 lpfc_sli4_async_fip_evt(phba, &cq_event->cqe.acqe_fip);
da0436e9
JS
5984 break;
5985 case LPFC_TRAILER_CODE_DCBX:
5986 lpfc_sli4_async_dcbx_evt(phba,
5987 &cq_event->cqe.acqe_dcbx);
5988 break;
b19a061a
JS
5989 case LPFC_TRAILER_CODE_GRP5:
5990 lpfc_sli4_async_grp5_evt(phba,
5991 &cq_event->cqe.acqe_grp5);
5992 break;
70f3c073
JS
5993 case LPFC_TRAILER_CODE_FC:
5994 lpfc_sli4_async_fc_evt(phba, &cq_event->cqe.acqe_fc);
5995 break;
5996 case LPFC_TRAILER_CODE_SLI:
5997 lpfc_sli4_async_sli_evt(phba, &cq_event->cqe.acqe_sli);
5998 break;
da0436e9 5999 default:
372c187b
DK
6000 lpfc_printf_log(phba, KERN_ERR,
6001 LOG_TRACE_EVENT,
291c2548 6002 "1804 Invalid asynchronous event code: "
da0436e9
JS
6003 "x%x\n", bf_get(lpfc_trailer_code,
6004 &cq_event->cqe.mcqe_cmpl));
6005 break;
6006 }
e7dab164 6007
da0436e9
JS
6008 /* Free the completion event processed to the free pool */
6009 lpfc_sli4_cq_event_release(phba, cq_event);
e7dab164 6010 spin_lock_irqsave(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9 6011 }
e7dab164 6012 spin_unlock_irqrestore(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9
JS
6013}
6014
ecfd03c6
JS
6015/**
6016 * lpfc_sli4_fcf_redisc_event_proc - Process fcf table rediscovery event
6017 * @phba: pointer to lpfc hba data structure.
6018 *
6019 * This routine is invoked by the worker thread to process FCF table
6020 * rediscovery pending completion event.
6021 **/
6022void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *phba)
6023{
6024 int rc;
6025
6026 spin_lock_irq(&phba->hbalock);
6027 /* Clear FCF rediscovery timeout event */
6028 phba->fcf.fcf_flag &= ~FCF_REDISC_EVT;
6029 /* Clear driver fast failover FCF record flag */
6030 phba->fcf.failover_rec.flag = 0;
6031 /* Set state for FCF fast failover */
6032 phba->fcf.fcf_flag |= FCF_REDISC_FOV;
6033 spin_unlock_irq(&phba->hbalock);
6034
6035 /* Scan FCF table from the first entry to re-discover SAN */
0c9ab6f5 6036 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
a93ff37a 6037 "2777 Start post-quiescent FCF table scan\n");
0c9ab6f5 6038 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba, LPFC_FCOE_FCF_GET_FIRST);
ecfd03c6 6039 if (rc)
372c187b 6040 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0c9ab6f5
JS
6041 "2747 Issue FCF scan read FCF mailbox "
6042 "command failed 0x%x\n", rc);
ecfd03c6
JS
6043}
6044
da0436e9
JS
6045/**
6046 * lpfc_api_table_setup - Set up per hba pci-device group func api jump table
6047 * @phba: pointer to lpfc hba data structure.
6048 * @dev_grp: The HBA PCI-Device group number.
6049 *
6050 * This routine is invoked to set up the per HBA PCI-Device group function
6051 * API jump table entries.
6052 *
6053 * Return: 0 if success, otherwise -ENODEV
6054 **/
6055int
6056lpfc_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
6057{
6058 int rc;
6059
6060 /* Set up lpfc PCI-device group */
6061 phba->pci_dev_grp = dev_grp;
6062
6063 /* The LPFC_PCI_DEV_OC uses SLI4 */
6064 if (dev_grp == LPFC_PCI_DEV_OC)
6065 phba->sli_rev = LPFC_SLI_REV4;
6066
6067 /* Set up device INIT API function jump table */
6068 rc = lpfc_init_api_table_setup(phba, dev_grp);
6069 if (rc)
6070 return -ENODEV;
6071 /* Set up SCSI API function jump table */
6072 rc = lpfc_scsi_api_table_setup(phba, dev_grp);
6073 if (rc)
6074 return -ENODEV;
6075 /* Set up SLI API function jump table */
6076 rc = lpfc_sli_api_table_setup(phba, dev_grp);
6077 if (rc)
6078 return -ENODEV;
6079 /* Set up MBOX API function jump table */
6080 rc = lpfc_mbox_api_table_setup(phba, dev_grp);
6081 if (rc)
6082 return -ENODEV;
6083
6084 return 0;
5b75da2f
JS
6085}
6086
6087/**
3621a710 6088 * lpfc_log_intr_mode - Log the active interrupt mode
5b75da2f
JS
6089 * @phba: pointer to lpfc hba data structure.
6090 * @intr_mode: active interrupt mode adopted.
6091 *
6092 * This routine it invoked to log the currently used active interrupt mode
6093 * to the device.
3772a991
JS
6094 **/
6095static void lpfc_log_intr_mode(struct lpfc_hba *phba, uint32_t intr_mode)
5b75da2f
JS
6096{
6097 switch (intr_mode) {
6098 case 0:
6099 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
6100 "0470 Enable INTx interrupt mode.\n");
6101 break;
6102 case 1:
6103 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
6104 "0481 Enabled MSI interrupt mode.\n");
6105 break;
6106 case 2:
6107 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
6108 "0480 Enabled MSI-X interrupt mode.\n");
6109 break;
6110 default:
372c187b 6111 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5b75da2f
JS
6112 "0482 Illegal interrupt mode.\n");
6113 break;
6114 }
6115 return;
6116}
6117
5b75da2f 6118/**
3772a991 6119 * lpfc_enable_pci_dev - Enable a generic PCI device.
5b75da2f
JS
6120 * @phba: pointer to lpfc hba data structure.
6121 *
3772a991
JS
6122 * This routine is invoked to enable the PCI device that is common to all
6123 * PCI devices.
5b75da2f
JS
6124 *
6125 * Return codes
af901ca1 6126 * 0 - successful
3772a991 6127 * other values - error
5b75da2f 6128 **/
3772a991
JS
6129static int
6130lpfc_enable_pci_dev(struct lpfc_hba *phba)
5b75da2f 6131{
3772a991 6132 struct pci_dev *pdev;
5b75da2f 6133
3772a991
JS
6134 /* Obtain PCI device reference */
6135 if (!phba->pcidev)
6136 goto out_error;
6137 else
6138 pdev = phba->pcidev;
3772a991
JS
6139 /* Enable PCI device */
6140 if (pci_enable_device_mem(pdev))
6141 goto out_error;
6142 /* Request PCI resource for the device */
e0c0483c 6143 if (pci_request_mem_regions(pdev, LPFC_DRIVER_NAME))
3772a991
JS
6144 goto out_disable_device;
6145 /* Set up device as PCI master and save state for EEH */
6146 pci_set_master(pdev);
6147 pci_try_set_mwi(pdev);
6148 pci_save_state(pdev);
5b75da2f 6149
0558056c 6150 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
453193e0 6151 if (pci_is_pcie(pdev))
0558056c
JS
6152 pdev->needs_freset = 1;
6153
3772a991 6154 return 0;
5b75da2f 6155
3772a991
JS
6156out_disable_device:
6157 pci_disable_device(pdev);
6158out_error:
372c187b 6159 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e0c0483c 6160 "1401 Failed to enable pci device\n");
3772a991 6161 return -ENODEV;
5b75da2f
JS
6162}
6163
6164/**
3772a991 6165 * lpfc_disable_pci_dev - Disable a generic PCI device.
5b75da2f
JS
6166 * @phba: pointer to lpfc hba data structure.
6167 *
3772a991
JS
6168 * This routine is invoked to disable the PCI device that is common to all
6169 * PCI devices.
5b75da2f
JS
6170 **/
6171static void
3772a991 6172lpfc_disable_pci_dev(struct lpfc_hba *phba)
5b75da2f 6173{
3772a991 6174 struct pci_dev *pdev;
5b75da2f 6175
3772a991
JS
6176 /* Obtain PCI device reference */
6177 if (!phba->pcidev)
6178 return;
6179 else
6180 pdev = phba->pcidev;
3772a991 6181 /* Release PCI resource and disable PCI device */
e0c0483c 6182 pci_release_mem_regions(pdev);
3772a991 6183 pci_disable_device(pdev);
5b75da2f
JS
6184
6185 return;
6186}
6187
e59058c4 6188/**
3772a991
JS
6189 * lpfc_reset_hba - Reset a hba
6190 * @phba: pointer to lpfc hba data structure.
e59058c4 6191 *
3772a991
JS
6192 * This routine is invoked to reset a hba device. It brings the HBA
6193 * offline, performs a board restart, and then brings the board back
6194 * online. The lpfc_offline calls lpfc_sli_hba_down which will clean up
6195 * on outstanding mailbox commands.
e59058c4 6196 **/
3772a991
JS
6197void
6198lpfc_reset_hba(struct lpfc_hba *phba)
dea3101e 6199{
3772a991
JS
6200 /* If resets are disabled then set error state and return. */
6201 if (!phba->cfg_enable_hba_reset) {
6202 phba->link_state = LPFC_HBA_ERROR;
6203 return;
6204 }
ee62021a
JS
6205 if (phba->sli.sli_flag & LPFC_SLI_ACTIVE)
6206 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
6207 else
6208 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
3772a991
JS
6209 lpfc_offline(phba);
6210 lpfc_sli_brdrestart(phba);
6211 lpfc_online(phba);
6212 lpfc_unblock_mgmt_io(phba);
6213}
dea3101e 6214
0a96e975
JS
6215/**
6216 * lpfc_sli_sriov_nr_virtfn_get - Get the number of sr-iov virtual functions
6217 * @phba: pointer to lpfc hba data structure.
6218 *
6219 * This function enables the PCI SR-IOV virtual functions to a physical
6220 * function. It invokes the PCI SR-IOV api with the @nr_vfn provided to
6221 * enable the number of virtual functions to the physical function. As
6222 * not all devices support SR-IOV, the return code from the pci_enable_sriov()
6223 * API call does not considered as an error condition for most of the device.
6224 **/
6225uint16_t
6226lpfc_sli_sriov_nr_virtfn_get(struct lpfc_hba *phba)
6227{
6228 struct pci_dev *pdev = phba->pcidev;
6229 uint16_t nr_virtfn;
6230 int pos;
6231
0a96e975
JS
6232 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6233 if (pos == 0)
6234 return 0;
6235
6236 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, &nr_virtfn);
6237 return nr_virtfn;
6238}
6239
912e3acd
JS
6240/**
6241 * lpfc_sli_probe_sriov_nr_virtfn - Enable a number of sr-iov virtual functions
6242 * @phba: pointer to lpfc hba data structure.
6243 * @nr_vfn: number of virtual functions to be enabled.
6244 *
6245 * This function enables the PCI SR-IOV virtual functions to a physical
6246 * function. It invokes the PCI SR-IOV api with the @nr_vfn provided to
6247 * enable the number of virtual functions to the physical function. As
6248 * not all devices support SR-IOV, the return code from the pci_enable_sriov()
6249 * API call does not considered as an error condition for most of the device.
6250 **/
6251int
6252lpfc_sli_probe_sriov_nr_virtfn(struct lpfc_hba *phba, int nr_vfn)
6253{
6254 struct pci_dev *pdev = phba->pcidev;
0a96e975 6255 uint16_t max_nr_vfn;
912e3acd
JS
6256 int rc;
6257
0a96e975
JS
6258 max_nr_vfn = lpfc_sli_sriov_nr_virtfn_get(phba);
6259 if (nr_vfn > max_nr_vfn) {
372c187b 6260 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a96e975
JS
6261 "3057 Requested vfs (%d) greater than "
6262 "supported vfs (%d)", nr_vfn, max_nr_vfn);
6263 return -EINVAL;
6264 }
6265
912e3acd
JS
6266 rc = pci_enable_sriov(pdev, nr_vfn);
6267 if (rc) {
6268 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6269 "2806 Failed to enable sriov on this device "
6270 "with vfn number nr_vf:%d, rc:%d\n",
6271 nr_vfn, rc);
6272 } else
6273 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6274 "2807 Successful enable sriov on this device "
6275 "with vfn number nr_vf:%d\n", nr_vfn);
6276 return rc;
6277}
6278
3772a991 6279/**
895427bd 6280 * lpfc_setup_driver_resource_phase1 - Phase1 etup driver internal resources.
3772a991
JS
6281 * @phba: pointer to lpfc hba data structure.
6282 *
895427bd
JS
6283 * This routine is invoked to set up the driver internal resources before the
6284 * device specific resource setup to support the HBA device it attached to.
3772a991
JS
6285 *
6286 * Return codes
895427bd
JS
6287 * 0 - successful
6288 * other values - error
3772a991
JS
6289 **/
6290static int
895427bd 6291lpfc_setup_driver_resource_phase1(struct lpfc_hba *phba)
3772a991 6292{
895427bd 6293 struct lpfc_sli *psli = &phba->sli;
dea3101e 6294
2e0fef85 6295 /*
895427bd 6296 * Driver resources common to all SLI revisions
2e0fef85 6297 */
895427bd 6298 atomic_set(&phba->fast_event_count, 0);
372c187b
DK
6299 atomic_set(&phba->dbg_log_idx, 0);
6300 atomic_set(&phba->dbg_log_cnt, 0);
6301 atomic_set(&phba->dbg_log_dmping, 0);
895427bd 6302 spin_lock_init(&phba->hbalock);
dea3101e 6303
895427bd
JS
6304 /* Initialize ndlp management spinlock */
6305 spin_lock_init(&phba->ndlp_lock);
6306
523128e5
JS
6307 /* Initialize port_list spinlock */
6308 spin_lock_init(&phba->port_list_lock);
895427bd 6309 INIT_LIST_HEAD(&phba->port_list);
523128e5 6310
895427bd
JS
6311 INIT_LIST_HEAD(&phba->work_list);
6312 init_waitqueue_head(&phba->wait_4_mlo_m_q);
6313
6314 /* Initialize the wait queue head for the kernel thread */
6315 init_waitqueue_head(&phba->work_waitq);
6316
6317 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
f358dd0c 6318 "1403 Protocols supported %s %s %s\n",
895427bd
JS
6319 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) ?
6320 "SCSI" : " "),
6321 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) ?
f358dd0c
JS
6322 "NVME" : " "),
6323 (phba->nvmet_support ? "NVMET" : " "));
895427bd 6324
0794d601
JS
6325 /* Initialize the IO buffer list used by driver for SLI3 SCSI */
6326 spin_lock_init(&phba->scsi_buf_list_get_lock);
6327 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_get);
6328 spin_lock_init(&phba->scsi_buf_list_put_lock);
6329 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_put);
895427bd
JS
6330
6331 /* Initialize the fabric iocb list */
6332 INIT_LIST_HEAD(&phba->fabric_iocb_list);
6333
6334 /* Initialize list to save ELS buffers */
6335 INIT_LIST_HEAD(&phba->elsbuf);
6336
6337 /* Initialize FCF connection rec list */
6338 INIT_LIST_HEAD(&phba->fcf_conn_rec_list);
6339
6340 /* Initialize OAS configuration list */
6341 spin_lock_init(&phba->devicelock);
6342 INIT_LIST_HEAD(&phba->luns);
858c9f6c 6343
3772a991 6344 /* MBOX heartbeat timer */
f22eb4d3 6345 timer_setup(&psli->mbox_tmo, lpfc_mbox_timeout, 0);
3772a991 6346 /* Fabric block timer */
f22eb4d3 6347 timer_setup(&phba->fabric_block_timer, lpfc_fabric_block_timeout, 0);
3772a991 6348 /* EA polling mode timer */
f22eb4d3 6349 timer_setup(&phba->eratt_poll, lpfc_poll_eratt, 0);
895427bd 6350 /* Heartbeat timer */
f22eb4d3 6351 timer_setup(&phba->hb_tmofunc, lpfc_hb_timeout, 0);
895427bd 6352
32517fc0
JS
6353 INIT_DELAYED_WORK(&phba->eq_delay_work, lpfc_hb_eq_delay_work);
6354
317aeb83
DK
6355 INIT_DELAYED_WORK(&phba->idle_stat_delay_work,
6356 lpfc_idle_stat_delay_work);
6357
895427bd
JS
6358 return 0;
6359}
6360
6361/**
6362 * lpfc_sli_driver_resource_setup - Setup driver internal resources for SLI3 dev
6363 * @phba: pointer to lpfc hba data structure.
6364 *
6365 * This routine is invoked to set up the driver internal resources specific to
6366 * support the SLI-3 HBA device it attached to.
6367 *
6368 * Return codes
6369 * 0 - successful
6370 * other values - error
6371 **/
6372static int
6373lpfc_sli_driver_resource_setup(struct lpfc_hba *phba)
6374{
0794d601 6375 int rc, entry_sz;
895427bd
JS
6376
6377 /*
6378 * Initialize timers used by driver
6379 */
6380
6381 /* FCP polling mode timer */
f22eb4d3 6382 timer_setup(&phba->fcp_poll_timer, lpfc_poll_timeout, 0);
dea3101e 6383
3772a991
JS
6384 /* Host attention work mask setup */
6385 phba->work_ha_mask = (HA_ERATT | HA_MBATT | HA_LATT);
6386 phba->work_ha_mask |= (HA_RXMASK << (LPFC_ELS_RING * 4));
dea3101e 6387
3772a991
JS
6388 /* Get all the module params for configuring this host */
6389 lpfc_get_cfgparam(phba);
895427bd
JS
6390 /* Set up phase-1 common device driver resources */
6391
6392 rc = lpfc_setup_driver_resource_phase1(phba);
6393 if (rc)
6394 return -ENODEV;
6395
49198b37
JS
6396 if (phba->pcidev->device == PCI_DEVICE_ID_HORNET) {
6397 phba->menlo_flag |= HBA_MENLO_SUPPORT;
6398 /* check for menlo minimum sg count */
6399 if (phba->cfg_sg_seg_cnt < LPFC_DEFAULT_MENLO_SG_SEG_CNT)
6400 phba->cfg_sg_seg_cnt = LPFC_DEFAULT_MENLO_SG_SEG_CNT;
6401 }
6402
895427bd 6403 if (!phba->sli.sli3_ring)
6396bb22
KC
6404 phba->sli.sli3_ring = kcalloc(LPFC_SLI3_MAX_RING,
6405 sizeof(struct lpfc_sli_ring),
6406 GFP_KERNEL);
895427bd 6407 if (!phba->sli.sli3_ring)
2a76a283
JS
6408 return -ENOMEM;
6409
dea3101e 6410 /*
96f7077f 6411 * Since lpfc_sg_seg_cnt is module parameter, the sg_dma_buf_size
3772a991 6412 * used to create the sg_dma_buf_pool must be dynamically calculated.
dea3101e 6413 */
3772a991 6414
0794d601
JS
6415 if (phba->sli_rev == LPFC_SLI_REV4)
6416 entry_sz = sizeof(struct sli4_sge);
6417 else
6418 entry_sz = sizeof(struct ulp_bde64);
6419
96f7077f 6420 /* There are going to be 2 reserved BDEs: 1 FCP cmnd + 1 FCP rsp */
3772a991 6421 if (phba->cfg_enable_bg) {
96f7077f
JS
6422 /*
6423 * The scsi_buf for a T10-DIF I/O will hold the FCP cmnd,
6424 * the FCP rsp, and a BDE for each. Sice we have no control
6425 * over how many protection data segments the SCSI Layer
6426 * will hand us (ie: there could be one for every block
6427 * in the IO), we just allocate enough BDEs to accomidate
6428 * our max amount and we need to limit lpfc_sg_seg_cnt to
6429 * minimize the risk of running out.
6430 */
6431 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6432 sizeof(struct fcp_rsp) +
0794d601 6433 (LPFC_MAX_SG_SEG_CNT * entry_sz);
96f7077f
JS
6434
6435 if (phba->cfg_sg_seg_cnt > LPFC_MAX_SG_SEG_CNT_DIF)
6436 phba->cfg_sg_seg_cnt = LPFC_MAX_SG_SEG_CNT_DIF;
6437
6438 /* Total BDEs in BPL for scsi_sg_list and scsi_sg_prot_list */
6439 phba->cfg_total_seg_cnt = LPFC_MAX_SG_SEG_CNT;
6440 } else {
6441 /*
6442 * The scsi_buf for a regular I/O will hold the FCP cmnd,
6443 * the FCP rsp, a BDE for each, and a BDE for up to
6444 * cfg_sg_seg_cnt data segments.
6445 */
6446 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6447 sizeof(struct fcp_rsp) +
0794d601 6448 ((phba->cfg_sg_seg_cnt + 2) * entry_sz);
96f7077f
JS
6449
6450 /* Total BDEs in BPL for scsi_sg_list */
6451 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + 2;
901a920f 6452 }
dea3101e 6453
96f7077f 6454 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
c90b4480 6455 "9088 INIT sg_tablesize:%d dmabuf_size:%d total_bde:%d\n",
96f7077f
JS
6456 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
6457 phba->cfg_total_seg_cnt);
dea3101e 6458
3772a991
JS
6459 phba->max_vpi = LPFC_MAX_VPI;
6460 /* This will be set to correct value after config_port mbox */
6461 phba->max_vports = 0;
dea3101e 6462
3772a991
JS
6463 /*
6464 * Initialize the SLI Layer to run with lpfc HBAs.
6465 */
6466 lpfc_sli_setup(phba);
895427bd 6467 lpfc_sli_queue_init(phba);
ed957684 6468
3772a991
JS
6469 /* Allocate device driver memory */
6470 if (lpfc_mem_alloc(phba, BPL_ALIGN_SZ))
6471 return -ENOMEM;
51ef4c26 6472
d79c9e9d
JS
6473 phba->lpfc_sg_dma_buf_pool =
6474 dma_pool_create("lpfc_sg_dma_buf_pool",
6475 &phba->pcidev->dev, phba->cfg_sg_dma_buf_size,
6476 BPL_ALIGN_SZ, 0);
6477
6478 if (!phba->lpfc_sg_dma_buf_pool)
6479 goto fail_free_mem;
6480
6481 phba->lpfc_cmd_rsp_buf_pool =
6482 dma_pool_create("lpfc_cmd_rsp_buf_pool",
6483 &phba->pcidev->dev,
6484 sizeof(struct fcp_cmnd) +
6485 sizeof(struct fcp_rsp),
6486 BPL_ALIGN_SZ, 0);
6487
6488 if (!phba->lpfc_cmd_rsp_buf_pool)
6489 goto fail_free_dma_buf_pool;
6490
912e3acd
JS
6491 /*
6492 * Enable sr-iov virtual functions if supported and configured
6493 * through the module parameter.
6494 */
6495 if (phba->cfg_sriov_nr_virtfn > 0) {
6496 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
6497 phba->cfg_sriov_nr_virtfn);
6498 if (rc) {
6499 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6500 "2808 Requested number of SR-IOV "
6501 "virtual functions (%d) is not "
6502 "supported\n",
6503 phba->cfg_sriov_nr_virtfn);
6504 phba->cfg_sriov_nr_virtfn = 0;
6505 }
6506 }
6507
3772a991 6508 return 0;
d79c9e9d
JS
6509
6510fail_free_dma_buf_pool:
6511 dma_pool_destroy(phba->lpfc_sg_dma_buf_pool);
6512 phba->lpfc_sg_dma_buf_pool = NULL;
6513fail_free_mem:
6514 lpfc_mem_free(phba);
6515 return -ENOMEM;
3772a991 6516}
ed957684 6517
3772a991
JS
6518/**
6519 * lpfc_sli_driver_resource_unset - Unset drvr internal resources for SLI3 dev
6520 * @phba: pointer to lpfc hba data structure.
6521 *
6522 * This routine is invoked to unset the driver internal resources set up
6523 * specific for supporting the SLI-3 HBA device it attached to.
6524 **/
6525static void
6526lpfc_sli_driver_resource_unset(struct lpfc_hba *phba)
6527{
6528 /* Free device driver memory allocated */
6529 lpfc_mem_free_all(phba);
3163f725 6530
3772a991
JS
6531 return;
6532}
dea3101e 6533
3772a991 6534/**
da0436e9 6535 * lpfc_sli4_driver_resource_setup - Setup drvr internal resources for SLI4 dev
3772a991
JS
6536 * @phba: pointer to lpfc hba data structure.
6537 *
da0436e9
JS
6538 * This routine is invoked to set up the driver internal resources specific to
6539 * support the SLI-4 HBA device it attached to.
3772a991
JS
6540 *
6541 * Return codes
af901ca1 6542 * 0 - successful
da0436e9 6543 * other values - error
3772a991
JS
6544 **/
6545static int
da0436e9 6546lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba)
3772a991 6547{
28baac74 6548 LPFC_MBOXQ_t *mboxq;
f358dd0c 6549 MAILBOX_t *mb;
895427bd 6550 int rc, i, max_buf_size;
28baac74
JS
6551 uint8_t pn_page[LPFC_MAX_SUPPORTED_PAGES] = {0};
6552 struct lpfc_mqe *mqe;
09294d46 6553 int longs;
81e6a637 6554 int extra;
f358dd0c 6555 uint64_t wwn;
b92dc72d
JS
6556 u32 if_type;
6557 u32 if_fam;
da0436e9 6558
895427bd 6559 phba->sli4_hba.num_present_cpu = lpfc_present_cpu;
eede4970 6560 phba->sli4_hba.num_possible_cpu = cpumask_last(cpu_possible_mask) + 1;
895427bd
JS
6561 phba->sli4_hba.curr_disp_cpu = 0;
6562
716d3bc5
JS
6563 /* Get all the module params for configuring this host */
6564 lpfc_get_cfgparam(phba);
6565
895427bd
JS
6566 /* Set up phase-1 common device driver resources */
6567 rc = lpfc_setup_driver_resource_phase1(phba);
6568 if (rc)
6569 return -ENODEV;
6570
da0436e9
JS
6571 /* Before proceed, wait for POST done and device ready */
6572 rc = lpfc_sli4_post_status_check(phba);
6573 if (rc)
6574 return -ENODEV;
6575
3cee98db
JS
6576 /* Allocate all driver workqueues here */
6577
6578 /* The lpfc_wq workqueue for deferred irq use */
6579 phba->wq = alloc_workqueue("lpfc_wq", WQ_MEM_RECLAIM, 0);
6580
3772a991 6581 /*
da0436e9 6582 * Initialize timers used by driver
3772a991 6583 */
3772a991 6584
f22eb4d3 6585 timer_setup(&phba->rrq_tmr, lpfc_rrq_timeout, 0);
3772a991 6586
ecfd03c6 6587 /* FCF rediscover timer */
f22eb4d3 6588 timer_setup(&phba->fcf.redisc_wait, lpfc_sli4_fcf_redisc_wait_tmo, 0);
ecfd03c6 6589
7ad20aa9
JS
6590 /*
6591 * Control structure for handling external multi-buffer mailbox
6592 * command pass-through.
6593 */
6594 memset((uint8_t *)&phba->mbox_ext_buf_ctx, 0,
6595 sizeof(struct lpfc_mbox_ext_buf_ctx));
6596 INIT_LIST_HEAD(&phba->mbox_ext_buf_ctx.ext_dmabuf_list);
6597
da0436e9 6598 phba->max_vpi = LPFC_MAX_VPI;
67d12733 6599
da0436e9
JS
6600 /* This will be set to correct value after the read_config mbox */
6601 phba->max_vports = 0;
3772a991 6602
da0436e9
JS
6603 /* Program the default value of vlan_id and fc_map */
6604 phba->valid_vlan = 0;
6605 phba->fc_map[0] = LPFC_FCOE_FCF_MAP0;
6606 phba->fc_map[1] = LPFC_FCOE_FCF_MAP1;
6607 phba->fc_map[2] = LPFC_FCOE_FCF_MAP2;
3772a991 6608
2a76a283
JS
6609 /*
6610 * For SLI4, instead of using ring 0 (LPFC_FCP_RING) for FCP commands
895427bd
JS
6611 * we will associate a new ring, for each EQ/CQ/WQ tuple.
6612 * The WQ create will allocate the ring.
2a76a283 6613 */
09294d46 6614
da0436e9 6615 /* Initialize buffer queue management fields */
895427bd 6616 INIT_LIST_HEAD(&phba->hbqs[LPFC_ELS_HBQ].hbq_buffer_list);
da0436e9
JS
6617 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_sli4_rb_alloc;
6618 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_sli4_rb_free;
3772a991 6619
da0436e9
JS
6620 /*
6621 * Initialize the SLI Layer to run with lpfc SLI4 HBAs.
6622 */
c00f62e6
JS
6623 /* Initialize the Abort buffer list used by driver */
6624 spin_lock_init(&phba->sli4_hba.abts_io_buf_list_lock);
6625 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_io_buf_list);
895427bd
JS
6626
6627 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
6628 /* Initialize the Abort nvme buffer list used by driver */
5e5b511d 6629 spin_lock_init(&phba->sli4_hba.abts_nvmet_buf_list_lock);
86c67379 6630 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
a8cf5dfe 6631 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_io_wait_list);
79d8c4ce
JS
6632 spin_lock_init(&phba->sli4_hba.t_active_list_lock);
6633 INIT_LIST_HEAD(&phba->sli4_hba.t_active_ctx_list);
895427bd
JS
6634 }
6635
da0436e9 6636 /* This abort list used by worker thread */
895427bd 6637 spin_lock_init(&phba->sli4_hba.sgl_list_lock);
a8cf5dfe 6638 spin_lock_init(&phba->sli4_hba.nvmet_io_wait_lock);
e7dab164
JS
6639 spin_lock_init(&phba->sli4_hba.asynce_list_lock);
6640 spin_lock_init(&phba->sli4_hba.els_xri_abrt_list_lock);
3772a991 6641
da0436e9 6642 /*
6d368e53 6643 * Initialize driver internal slow-path work queues
da0436e9 6644 */
3772a991 6645
da0436e9
JS
6646 /* Driver internel slow-path CQ Event pool */
6647 INIT_LIST_HEAD(&phba->sli4_hba.sp_cqe_event_pool);
6648 /* Response IOCB work queue list */
45ed1190 6649 INIT_LIST_HEAD(&phba->sli4_hba.sp_queue_event);
da0436e9
JS
6650 /* Asynchronous event CQ Event work queue list */
6651 INIT_LIST_HEAD(&phba->sli4_hba.sp_asynce_work_queue);
da0436e9
JS
6652 /* Slow-path XRI aborted CQ Event work queue list */
6653 INIT_LIST_HEAD(&phba->sli4_hba.sp_els_xri_aborted_work_queue);
6654 /* Receive queue CQ Event work queue list */
6655 INIT_LIST_HEAD(&phba->sli4_hba.sp_unsol_work_queue);
6656
6d368e53
JS
6657 /* Initialize extent block lists. */
6658 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_blk_list);
6659 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_xri_blk_list);
6660 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_vfi_blk_list);
6661 INIT_LIST_HEAD(&phba->lpfc_vpi_blk_list);
6662
d1f525aa
JS
6663 /* Initialize mboxq lists. If the early init routines fail
6664 * these lists need to be correctly initialized.
6665 */
6666 INIT_LIST_HEAD(&phba->sli.mboxq);
6667 INIT_LIST_HEAD(&phba->sli.mboxq_cmpl);
6668
448193b5
JS
6669 /* initialize optic_state to 0xFF */
6670 phba->sli4_hba.lnk_info.optic_state = 0xff;
6671
da0436e9
JS
6672 /* Allocate device driver memory */
6673 rc = lpfc_mem_alloc(phba, SGL_ALIGN_SZ);
6674 if (rc)
6675 return -ENOMEM;
6676
2fcee4bf 6677 /* IF Type 2 ports get initialized now. */
27d6ac0a 6678 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) >=
2fcee4bf
JS
6679 LPFC_SLI_INTF_IF_TYPE_2) {
6680 rc = lpfc_pci_function_reset(phba);
895427bd
JS
6681 if (unlikely(rc)) {
6682 rc = -ENODEV;
6683 goto out_free_mem;
6684 }
946727dc 6685 phba->temp_sensor_support = 1;
2fcee4bf
JS
6686 }
6687
da0436e9
JS
6688 /* Create the bootstrap mailbox command */
6689 rc = lpfc_create_bootstrap_mbox(phba);
6690 if (unlikely(rc))
6691 goto out_free_mem;
6692
6693 /* Set up the host's endian order with the device. */
6694 rc = lpfc_setup_endian_order(phba);
6695 if (unlikely(rc))
6696 goto out_free_bsmbx;
6697
6698 /* Set up the hba's configuration parameters. */
6699 rc = lpfc_sli4_read_config(phba);
cff261f6
JS
6700 if (unlikely(rc))
6701 goto out_free_bsmbx;
6702 rc = lpfc_mem_alloc_active_rrq_pool_s4(phba);
da0436e9
JS
6703 if (unlikely(rc))
6704 goto out_free_bsmbx;
6705
2fcee4bf
JS
6706 /* IF Type 0 ports get initialized now. */
6707 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
6708 LPFC_SLI_INTF_IF_TYPE_0) {
6709 rc = lpfc_pci_function_reset(phba);
6710 if (unlikely(rc))
6711 goto out_free_bsmbx;
6712 }
da0436e9 6713
cb5172ea
JS
6714 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
6715 GFP_KERNEL);
6716 if (!mboxq) {
6717 rc = -ENOMEM;
6718 goto out_free_bsmbx;
6719 }
6720
f358dd0c 6721 /* Check for NVMET being configured */
895427bd 6722 phba->nvmet_support = 0;
f358dd0c
JS
6723 if (lpfc_enable_nvmet_cnt) {
6724
6725 /* First get WWN of HBA instance */
6726 lpfc_read_nv(phba, mboxq);
6727 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
6728 if (rc != MBX_SUCCESS) {
372c187b
DK
6729 lpfc_printf_log(phba, KERN_ERR,
6730 LOG_TRACE_EVENT,
f358dd0c
JS
6731 "6016 Mailbox failed , mbxCmd x%x "
6732 "READ_NV, mbxStatus x%x\n",
6733 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
6734 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
d1f525aa 6735 mempool_free(mboxq, phba->mbox_mem_pool);
f358dd0c
JS
6736 rc = -EIO;
6737 goto out_free_bsmbx;
6738 }
6739 mb = &mboxq->u.mb;
6740 memcpy(&wwn, (char *)mb->un.varRDnvp.nodename,
6741 sizeof(uint64_t));
6742 wwn = cpu_to_be64(wwn);
6743 phba->sli4_hba.wwnn.u.name = wwn;
6744 memcpy(&wwn, (char *)mb->un.varRDnvp.portname,
6745 sizeof(uint64_t));
6746 /* wwn is WWPN of HBA instance */
6747 wwn = cpu_to_be64(wwn);
6748 phba->sli4_hba.wwpn.u.name = wwn;
6749
6750 /* Check to see if it matches any module parameter */
6751 for (i = 0; i < lpfc_enable_nvmet_cnt; i++) {
6752 if (wwn == lpfc_enable_nvmet[i]) {
7d708033 6753#if (IS_ENABLED(CONFIG_NVME_TARGET_FC))
3c603be9
JS
6754 if (lpfc_nvmet_mem_alloc(phba))
6755 break;
6756
6757 phba->nvmet_support = 1; /* a match */
6758
372c187b
DK
6759 lpfc_printf_log(phba, KERN_ERR,
6760 LOG_TRACE_EVENT,
f358dd0c
JS
6761 "6017 NVME Target %016llx\n",
6762 wwn);
7d708033 6763#else
372c187b
DK
6764 lpfc_printf_log(phba, KERN_ERR,
6765 LOG_TRACE_EVENT,
7d708033
JS
6766 "6021 Can't enable NVME Target."
6767 " NVME_TARGET_FC infrastructure"
6768 " is not in kernel\n");
6769#endif
c490850a
JS
6770 /* Not supported for NVMET */
6771 phba->cfg_xri_rebalancing = 0;
3048e3e8
DK
6772 if (phba->irq_chann_mode == NHT_MODE) {
6773 phba->cfg_irq_chann =
6774 phba->sli4_hba.num_present_cpu;
6775 phba->cfg_hdw_queue =
6776 phba->sli4_hba.num_present_cpu;
6777 phba->irq_chann_mode = NORMAL_MODE;
6778 }
3c603be9 6779 break;
f358dd0c
JS
6780 }
6781 }
6782 }
895427bd
JS
6783
6784 lpfc_nvme_mod_param_dep(phba);
6785
fedd3b7b 6786 /* Get the Supported Pages if PORT_CAPABILITIES is supported by port. */
cb5172ea
JS
6787 lpfc_supported_pages(mboxq);
6788 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
fedd3b7b
JS
6789 if (!rc) {
6790 mqe = &mboxq->u.mqe;
6791 memcpy(&pn_page[0], ((uint8_t *)&mqe->un.supp_pages.word3),
6792 LPFC_MAX_SUPPORTED_PAGES);
6793 for (i = 0; i < LPFC_MAX_SUPPORTED_PAGES; i++) {
6794 switch (pn_page[i]) {
6795 case LPFC_SLI4_PARAMETERS:
6796 phba->sli4_hba.pc_sli4_params.supported = 1;
6797 break;
6798 default:
6799 break;
6800 }
6801 }
6802 /* Read the port's SLI4 Parameters capabilities if supported. */
6803 if (phba->sli4_hba.pc_sli4_params.supported)
6804 rc = lpfc_pc_sli4_params_get(phba, mboxq);
6805 if (rc) {
6806 mempool_free(mboxq, phba->mbox_mem_pool);
6807 rc = -EIO;
6808 goto out_free_bsmbx;
cb5172ea
JS
6809 }
6810 }
65791f1f 6811
fedd3b7b
JS
6812 /*
6813 * Get sli4 parameters that override parameters from Port capabilities.
6d368e53
JS
6814 * If this call fails, it isn't critical unless the SLI4 parameters come
6815 * back in conflict.
fedd3b7b 6816 */
6d368e53
JS
6817 rc = lpfc_get_sli4_parameters(phba, mboxq);
6818 if (rc) {
b92dc72d
JS
6819 if_type = bf_get(lpfc_sli_intf_if_type,
6820 &phba->sli4_hba.sli_intf);
6821 if_fam = bf_get(lpfc_sli_intf_sli_family,
6822 &phba->sli4_hba.sli_intf);
6d368e53
JS
6823 if (phba->sli4_hba.extents_in_use &&
6824 phba->sli4_hba.rpi_hdrs_in_use) {
372c187b
DK
6825 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
6826 "2999 Unsupported SLI4 Parameters "
6827 "Extents and RPI headers enabled.\n");
b92dc72d
JS
6828 if (if_type == LPFC_SLI_INTF_IF_TYPE_0 &&
6829 if_fam == LPFC_SLI_INTF_FAMILY_BE2) {
6830 mempool_free(mboxq, phba->mbox_mem_pool);
6831 rc = -EIO;
6832 goto out_free_bsmbx;
6833 }
6834 }
6835 if (!(if_type == LPFC_SLI_INTF_IF_TYPE_0 &&
6836 if_fam == LPFC_SLI_INTF_FAMILY_BE2)) {
6837 mempool_free(mboxq, phba->mbox_mem_pool);
6838 rc = -EIO;
6839 goto out_free_bsmbx;
6d368e53
JS
6840 }
6841 }
895427bd 6842
d79c9e9d
JS
6843 /*
6844 * 1 for cmd, 1 for rsp, NVME adds an extra one
6845 * for boundary conditions in its max_sgl_segment template.
6846 */
6847 extra = 2;
6848 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
6849 extra++;
6850
6851 /*
6852 * It doesn't matter what family our adapter is in, we are
6853 * limited to 2 Pages, 512 SGEs, for our SGL.
6854 * There are going to be 2 reserved SGEs: 1 FCP cmnd + 1 FCP rsp
6855 */
6856 max_buf_size = (2 * SLI4_PAGE_SIZE);
6857
6858 /*
6859 * Since lpfc_sg_seg_cnt is module param, the sg_dma_buf_size
6860 * used to create the sg_dma_buf_pool must be calculated.
6861 */
6862 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED) {
6863 /* Both cfg_enable_bg and cfg_external_dif code paths */
6864
6865 /*
6866 * The scsi_buf for a T10-DIF I/O holds the FCP cmnd,
6867 * the FCP rsp, and a SGE. Sice we have no control
6868 * over how many protection segments the SCSI Layer
6869 * will hand us (ie: there could be one for every block
6870 * in the IO), just allocate enough SGEs to accomidate
6871 * our max amount and we need to limit lpfc_sg_seg_cnt
6872 * to minimize the risk of running out.
6873 */
6874 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6875 sizeof(struct fcp_rsp) + max_buf_size;
6876
6877 /* Total SGEs for scsi_sg_list and scsi_sg_prot_list */
6878 phba->cfg_total_seg_cnt = LPFC_MAX_SGL_SEG_CNT;
6879
6880 /*
6881 * If supporting DIF, reduce the seg count for scsi to
6882 * allow room for the DIF sges.
6883 */
6884 if (phba->cfg_enable_bg &&
6885 phba->cfg_sg_seg_cnt > LPFC_MAX_BG_SLI4_SEG_CNT_DIF)
6886 phba->cfg_scsi_seg_cnt = LPFC_MAX_BG_SLI4_SEG_CNT_DIF;
6887 else
6888 phba->cfg_scsi_seg_cnt = phba->cfg_sg_seg_cnt;
6889
6890 } else {
6891 /*
6892 * The scsi_buf for a regular I/O holds the FCP cmnd,
6893 * the FCP rsp, a SGE for each, and a SGE for up to
6894 * cfg_sg_seg_cnt data segments.
6895 */
6896 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6897 sizeof(struct fcp_rsp) +
6898 ((phba->cfg_sg_seg_cnt + extra) *
6899 sizeof(struct sli4_sge));
6900
6901 /* Total SGEs for scsi_sg_list */
6902 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + extra;
6903 phba->cfg_scsi_seg_cnt = phba->cfg_sg_seg_cnt;
6904
6905 /*
6906 * NOTE: if (phba->cfg_sg_seg_cnt + extra) <= 256 we only
6907 * need to post 1 page for the SGL.
6908 */
6909 }
6910
6911 if (phba->cfg_xpsgl && !phba->nvmet_support)
6912 phba->cfg_sg_dma_buf_size = LPFC_DEFAULT_XPSGL_SIZE;
6913 else if (phba->cfg_sg_dma_buf_size <= LPFC_MIN_SG_SLI4_BUF_SZ)
6914 phba->cfg_sg_dma_buf_size = LPFC_MIN_SG_SLI4_BUF_SZ;
6915 else
6916 phba->cfg_sg_dma_buf_size =
6917 SLI4_PAGE_ALIGN(phba->cfg_sg_dma_buf_size);
6918
6919 phba->border_sge_num = phba->cfg_sg_dma_buf_size /
6920 sizeof(struct sli4_sge);
6921
6922 /* Limit to LPFC_MAX_NVME_SEG_CNT for NVME. */
6923 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
6924 if (phba->cfg_sg_seg_cnt > LPFC_MAX_NVME_SEG_CNT) {
6925 lpfc_printf_log(phba, KERN_INFO, LOG_NVME | LOG_INIT,
6926 "6300 Reducing NVME sg segment "
6927 "cnt to %d\n",
6928 LPFC_MAX_NVME_SEG_CNT);
6929 phba->cfg_nvme_seg_cnt = LPFC_MAX_NVME_SEG_CNT;
6930 } else
6931 phba->cfg_nvme_seg_cnt = phba->cfg_sg_seg_cnt;
6932 }
6933
d79c9e9d
JS
6934 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
6935 "9087 sg_seg_cnt:%d dmabuf_size:%d "
6936 "total:%d scsi:%d nvme:%d\n",
6937 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
6938 phba->cfg_total_seg_cnt, phba->cfg_scsi_seg_cnt,
6939 phba->cfg_nvme_seg_cnt);
6940
6941 if (phba->cfg_sg_dma_buf_size < SLI4_PAGE_SIZE)
6942 i = phba->cfg_sg_dma_buf_size;
6943 else
6944 i = SLI4_PAGE_SIZE;
6945
6946 phba->lpfc_sg_dma_buf_pool =
6947 dma_pool_create("lpfc_sg_dma_buf_pool",
6948 &phba->pcidev->dev,
6949 phba->cfg_sg_dma_buf_size,
6950 i, 0);
6951 if (!phba->lpfc_sg_dma_buf_pool)
6952 goto out_free_bsmbx;
6953
6954 phba->lpfc_cmd_rsp_buf_pool =
6955 dma_pool_create("lpfc_cmd_rsp_buf_pool",
6956 &phba->pcidev->dev,
6957 sizeof(struct fcp_cmnd) +
6958 sizeof(struct fcp_rsp),
6959 i, 0);
6960 if (!phba->lpfc_cmd_rsp_buf_pool)
6961 goto out_free_sg_dma_buf;
6962
cb5172ea 6963 mempool_free(mboxq, phba->mbox_mem_pool);
1ba981fd
JS
6964
6965 /* Verify OAS is supported */
6966 lpfc_sli4_oas_verify(phba);
1ba981fd 6967
d2cc9bcd
JS
6968 /* Verify RAS support on adapter */
6969 lpfc_sli4_ras_init(phba);
6970
5350d872
JS
6971 /* Verify all the SLI4 queues */
6972 rc = lpfc_sli4_queue_verify(phba);
da0436e9 6973 if (rc)
d79c9e9d 6974 goto out_free_cmd_rsp_buf;
da0436e9
JS
6975
6976 /* Create driver internal CQE event pool */
6977 rc = lpfc_sli4_cq_event_pool_create(phba);
6978 if (rc)
d79c9e9d 6979 goto out_free_cmd_rsp_buf;
da0436e9 6980
8a9d2e80
JS
6981 /* Initialize sgl lists per host */
6982 lpfc_init_sgl_list(phba);
6983
6984 /* Allocate and initialize active sgl array */
da0436e9
JS
6985 rc = lpfc_init_active_sgl_array(phba);
6986 if (rc) {
372c187b 6987 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 6988 "1430 Failed to initialize sgl list.\n");
8a9d2e80 6989 goto out_destroy_cq_event_pool;
da0436e9 6990 }
da0436e9
JS
6991 rc = lpfc_sli4_init_rpi_hdrs(phba);
6992 if (rc) {
372c187b 6993 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
6994 "1432 Failed to initialize rpi headers.\n");
6995 goto out_free_active_sgl;
6996 }
6997
a93ff37a 6998 /* Allocate eligible FCF bmask memory for FCF roundrobin failover */
0c9ab6f5 6999 longs = (LPFC_SLI4_FCF_TBL_INDX_MAX + BITS_PER_LONG - 1)/BITS_PER_LONG;
6396bb22 7000 phba->fcf.fcf_rr_bmask = kcalloc(longs, sizeof(unsigned long),
0c9ab6f5
JS
7001 GFP_KERNEL);
7002 if (!phba->fcf.fcf_rr_bmask) {
372c187b 7003 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0c9ab6f5
JS
7004 "2759 Failed allocate memory for FCF round "
7005 "robin failover bmask\n");
0558056c 7006 rc = -ENOMEM;
0c9ab6f5
JS
7007 goto out_remove_rpi_hdrs;
7008 }
7009
6a828b0f 7010 phba->sli4_hba.hba_eq_hdl = kcalloc(phba->cfg_irq_chann,
cdb42bec
JS
7011 sizeof(struct lpfc_hba_eq_hdl),
7012 GFP_KERNEL);
895427bd 7013 if (!phba->sli4_hba.hba_eq_hdl) {
372c187b 7014 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
67d12733
JS
7015 "2572 Failed allocate memory for "
7016 "fast-path per-EQ handle array\n");
7017 rc = -ENOMEM;
7018 goto out_free_fcf_rr_bmask;
da0436e9
JS
7019 }
7020
222e9239 7021 phba->sli4_hba.cpu_map = kcalloc(phba->sli4_hba.num_possible_cpu,
895427bd
JS
7022 sizeof(struct lpfc_vector_map_info),
7023 GFP_KERNEL);
7bb03bbf 7024 if (!phba->sli4_hba.cpu_map) {
372c187b 7025 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
7bb03bbf
JS
7026 "3327 Failed allocate memory for msi-x "
7027 "interrupt vector mapping\n");
7028 rc = -ENOMEM;
895427bd 7029 goto out_free_hba_eq_hdl;
7bb03bbf 7030 }
b246de17 7031
32517fc0
JS
7032 phba->sli4_hba.eq_info = alloc_percpu(struct lpfc_eq_intr_info);
7033 if (!phba->sli4_hba.eq_info) {
372c187b 7034 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
32517fc0
JS
7035 "3321 Failed allocation for per_cpu stats\n");
7036 rc = -ENOMEM;
7037 goto out_free_hba_cpu_map;
7038 }
840eda96 7039
317aeb83
DK
7040 phba->sli4_hba.idle_stat = kcalloc(phba->sli4_hba.num_possible_cpu,
7041 sizeof(*phba->sli4_hba.idle_stat),
7042 GFP_KERNEL);
7043 if (!phba->sli4_hba.idle_stat) {
372c187b 7044 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
317aeb83
DK
7045 "3390 Failed allocation for idle_stat\n");
7046 rc = -ENOMEM;
7047 goto out_free_hba_eq_info;
7048 }
7049
840eda96
JS
7050#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
7051 phba->sli4_hba.c_stat = alloc_percpu(struct lpfc_hdwq_stat);
7052 if (!phba->sli4_hba.c_stat) {
372c187b 7053 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
840eda96
JS
7054 "3332 Failed allocating per cpu hdwq stats\n");
7055 rc = -ENOMEM;
317aeb83 7056 goto out_free_hba_idle_stat;
840eda96
JS
7057 }
7058#endif
7059
912e3acd
JS
7060 /*
7061 * Enable sr-iov virtual functions if supported and configured
7062 * through the module parameter.
7063 */
7064 if (phba->cfg_sriov_nr_virtfn > 0) {
7065 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
7066 phba->cfg_sriov_nr_virtfn);
7067 if (rc) {
7068 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
7069 "3020 Requested number of SR-IOV "
7070 "virtual functions (%d) is not "
7071 "supported\n",
7072 phba->cfg_sriov_nr_virtfn);
7073 phba->cfg_sriov_nr_virtfn = 0;
7074 }
7075 }
7076
5248a749 7077 return 0;
da0436e9 7078
840eda96 7079#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
317aeb83
DK
7080out_free_hba_idle_stat:
7081 kfree(phba->sli4_hba.idle_stat);
7082#endif
840eda96
JS
7083out_free_hba_eq_info:
7084 free_percpu(phba->sli4_hba.eq_info);
32517fc0
JS
7085out_free_hba_cpu_map:
7086 kfree(phba->sli4_hba.cpu_map);
895427bd
JS
7087out_free_hba_eq_hdl:
7088 kfree(phba->sli4_hba.hba_eq_hdl);
0c9ab6f5
JS
7089out_free_fcf_rr_bmask:
7090 kfree(phba->fcf.fcf_rr_bmask);
da0436e9
JS
7091out_remove_rpi_hdrs:
7092 lpfc_sli4_remove_rpi_hdrs(phba);
7093out_free_active_sgl:
7094 lpfc_free_active_sgl(phba);
da0436e9
JS
7095out_destroy_cq_event_pool:
7096 lpfc_sli4_cq_event_pool_destroy(phba);
d79c9e9d
JS
7097out_free_cmd_rsp_buf:
7098 dma_pool_destroy(phba->lpfc_cmd_rsp_buf_pool);
7099 phba->lpfc_cmd_rsp_buf_pool = NULL;
7100out_free_sg_dma_buf:
7101 dma_pool_destroy(phba->lpfc_sg_dma_buf_pool);
7102 phba->lpfc_sg_dma_buf_pool = NULL;
da0436e9
JS
7103out_free_bsmbx:
7104 lpfc_destroy_bootstrap_mbox(phba);
7105out_free_mem:
7106 lpfc_mem_free(phba);
7107 return rc;
7108}
7109
7110/**
7111 * lpfc_sli4_driver_resource_unset - Unset drvr internal resources for SLI4 dev
7112 * @phba: pointer to lpfc hba data structure.
7113 *
7114 * This routine is invoked to unset the driver internal resources set up
7115 * specific for supporting the SLI-4 HBA device it attached to.
7116 **/
7117static void
7118lpfc_sli4_driver_resource_unset(struct lpfc_hba *phba)
7119{
7120 struct lpfc_fcf_conn_entry *conn_entry, *next_conn_entry;
7121
32517fc0 7122 free_percpu(phba->sli4_hba.eq_info);
840eda96
JS
7123#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
7124 free_percpu(phba->sli4_hba.c_stat);
7125#endif
317aeb83 7126 kfree(phba->sli4_hba.idle_stat);
32517fc0 7127
7bb03bbf
JS
7128 /* Free memory allocated for msi-x interrupt vector to CPU mapping */
7129 kfree(phba->sli4_hba.cpu_map);
222e9239 7130 phba->sli4_hba.num_possible_cpu = 0;
7bb03bbf 7131 phba->sli4_hba.num_present_cpu = 0;
76fd07a6 7132 phba->sli4_hba.curr_disp_cpu = 0;
3048e3e8 7133 cpumask_clear(&phba->sli4_hba.irq_aff_mask);
7bb03bbf 7134
da0436e9 7135 /* Free memory allocated for fast-path work queue handles */
895427bd 7136 kfree(phba->sli4_hba.hba_eq_hdl);
da0436e9
JS
7137
7138 /* Free the allocated rpi headers. */
7139 lpfc_sli4_remove_rpi_hdrs(phba);
d11e31dd 7140 lpfc_sli4_remove_rpis(phba);
da0436e9 7141
0c9ab6f5
JS
7142 /* Free eligible FCF index bmask */
7143 kfree(phba->fcf.fcf_rr_bmask);
7144
da0436e9
JS
7145 /* Free the ELS sgl list */
7146 lpfc_free_active_sgl(phba);
8a9d2e80 7147 lpfc_free_els_sgl_list(phba);
f358dd0c 7148 lpfc_free_nvmet_sgl_list(phba);
da0436e9 7149
da0436e9
JS
7150 /* Free the completion queue EQ event pool */
7151 lpfc_sli4_cq_event_release_all(phba);
7152 lpfc_sli4_cq_event_pool_destroy(phba);
7153
6d368e53
JS
7154 /* Release resource identifiers. */
7155 lpfc_sli4_dealloc_resource_identifiers(phba);
7156
da0436e9
JS
7157 /* Free the bsmbx region. */
7158 lpfc_destroy_bootstrap_mbox(phba);
7159
7160 /* Free the SLI Layer memory with SLI4 HBAs */
7161 lpfc_mem_free_all(phba);
7162
7163 /* Free the current connect table */
7164 list_for_each_entry_safe(conn_entry, next_conn_entry,
4d9ab994
JS
7165 &phba->fcf_conn_rec_list, list) {
7166 list_del_init(&conn_entry->list);
da0436e9 7167 kfree(conn_entry);
4d9ab994 7168 }
da0436e9
JS
7169
7170 return;
7171}
7172
7173/**
25985edc 7174 * lpfc_init_api_table_setup - Set up init api function jump table
da0436e9
JS
7175 * @phba: The hba struct for which this call is being executed.
7176 * @dev_grp: The HBA PCI-Device group number.
7177 *
7178 * This routine sets up the device INIT interface API function jump table
7179 * in @phba struct.
7180 *
7181 * Returns: 0 - success, -ENODEV - failure.
7182 **/
7183int
7184lpfc_init_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
7185{
84d1b006
JS
7186 phba->lpfc_hba_init_link = lpfc_hba_init_link;
7187 phba->lpfc_hba_down_link = lpfc_hba_down_link;
7f86059a 7188 phba->lpfc_selective_reset = lpfc_selective_reset;
da0436e9
JS
7189 switch (dev_grp) {
7190 case LPFC_PCI_DEV_LP:
7191 phba->lpfc_hba_down_post = lpfc_hba_down_post_s3;
7192 phba->lpfc_handle_eratt = lpfc_handle_eratt_s3;
7193 phba->lpfc_stop_port = lpfc_stop_port_s3;
7194 break;
7195 case LPFC_PCI_DEV_OC:
7196 phba->lpfc_hba_down_post = lpfc_hba_down_post_s4;
7197 phba->lpfc_handle_eratt = lpfc_handle_eratt_s4;
7198 phba->lpfc_stop_port = lpfc_stop_port_s4;
7199 break;
7200 default:
372c187b 7201 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
7202 "1431 Invalid HBA PCI-device group: 0x%x\n",
7203 dev_grp);
7204 return -ENODEV;
da0436e9
JS
7205 }
7206 return 0;
7207}
7208
da0436e9
JS
7209/**
7210 * lpfc_setup_driver_resource_phase2 - Phase2 setup driver internal resources.
7211 * @phba: pointer to lpfc hba data structure.
7212 *
7213 * This routine is invoked to set up the driver internal resources after the
7214 * device specific resource setup to support the HBA device it attached to.
7215 *
7216 * Return codes
af901ca1 7217 * 0 - successful
da0436e9
JS
7218 * other values - error
7219 **/
7220static int
7221lpfc_setup_driver_resource_phase2(struct lpfc_hba *phba)
7222{
7223 int error;
7224
7225 /* Startup the kernel thread for this host adapter. */
7226 phba->worker_thread = kthread_run(lpfc_do_work, phba,
7227 "lpfc_worker_%d", phba->brd_no);
7228 if (IS_ERR(phba->worker_thread)) {
7229 error = PTR_ERR(phba->worker_thread);
7230 return error;
3772a991
JS
7231 }
7232
7233 return 0;
7234}
7235
7236/**
7237 * lpfc_unset_driver_resource_phase2 - Phase2 unset driver internal resources.
7238 * @phba: pointer to lpfc hba data structure.
7239 *
7240 * This routine is invoked to unset the driver internal resources set up after
7241 * the device specific resource setup for supporting the HBA device it
7242 * attached to.
7243 **/
7244static void
7245lpfc_unset_driver_resource_phase2(struct lpfc_hba *phba)
7246{
f485c18d
DK
7247 if (phba->wq) {
7248 flush_workqueue(phba->wq);
7249 destroy_workqueue(phba->wq);
7250 phba->wq = NULL;
7251 }
7252
3772a991 7253 /* Stop kernel worker thread */
0cdb84ec
JS
7254 if (phba->worker_thread)
7255 kthread_stop(phba->worker_thread);
3772a991
JS
7256}
7257
7258/**
7259 * lpfc_free_iocb_list - Free iocb list.
7260 * @phba: pointer to lpfc hba data structure.
7261 *
7262 * This routine is invoked to free the driver's IOCB list and memory.
7263 **/
6c621a22 7264void
3772a991
JS
7265lpfc_free_iocb_list(struct lpfc_hba *phba)
7266{
7267 struct lpfc_iocbq *iocbq_entry = NULL, *iocbq_next = NULL;
7268
7269 spin_lock_irq(&phba->hbalock);
7270 list_for_each_entry_safe(iocbq_entry, iocbq_next,
7271 &phba->lpfc_iocb_list, list) {
7272 list_del(&iocbq_entry->list);
7273 kfree(iocbq_entry);
7274 phba->total_iocbq_bufs--;
98c9ea5c 7275 }
3772a991
JS
7276 spin_unlock_irq(&phba->hbalock);
7277
7278 return;
7279}
7280
7281/**
7282 * lpfc_init_iocb_list - Allocate and initialize iocb list.
7283 * @phba: pointer to lpfc hba data structure.
fe614acd 7284 * @iocb_count: number of requested iocbs
3772a991
JS
7285 *
7286 * This routine is invoked to allocate and initizlize the driver's IOCB
7287 * list and set up the IOCB tag array accordingly.
7288 *
7289 * Return codes
af901ca1 7290 * 0 - successful
3772a991
JS
7291 * other values - error
7292 **/
6c621a22 7293int
3772a991
JS
7294lpfc_init_iocb_list(struct lpfc_hba *phba, int iocb_count)
7295{
7296 struct lpfc_iocbq *iocbq_entry = NULL;
7297 uint16_t iotag;
7298 int i;
dea3101e 7299
7300 /* Initialize and populate the iocb list per host. */
7301 INIT_LIST_HEAD(&phba->lpfc_iocb_list);
3772a991 7302 for (i = 0; i < iocb_count; i++) {
dd00cc48 7303 iocbq_entry = kzalloc(sizeof(struct lpfc_iocbq), GFP_KERNEL);
dea3101e 7304 if (iocbq_entry == NULL) {
7305 printk(KERN_ERR "%s: only allocated %d iocbs of "
7306 "expected %d count. Unloading driver.\n",
a5f7337f 7307 __func__, i, iocb_count);
dea3101e 7308 goto out_free_iocbq;
7309 }
7310
604a3e30
JB
7311 iotag = lpfc_sli_next_iotag(phba, iocbq_entry);
7312 if (iotag == 0) {
3772a991 7313 kfree(iocbq_entry);
604a3e30 7314 printk(KERN_ERR "%s: failed to allocate IOTAG. "
3772a991 7315 "Unloading driver.\n", __func__);
604a3e30
JB
7316 goto out_free_iocbq;
7317 }
6d368e53 7318 iocbq_entry->sli4_lxritag = NO_XRI;
3772a991 7319 iocbq_entry->sli4_xritag = NO_XRI;
2e0fef85
JS
7320
7321 spin_lock_irq(&phba->hbalock);
dea3101e 7322 list_add(&iocbq_entry->list, &phba->lpfc_iocb_list);
7323 phba->total_iocbq_bufs++;
2e0fef85 7324 spin_unlock_irq(&phba->hbalock);
dea3101e 7325 }
7326
3772a991 7327 return 0;
dea3101e 7328
3772a991
JS
7329out_free_iocbq:
7330 lpfc_free_iocb_list(phba);
dea3101e 7331
3772a991
JS
7332 return -ENOMEM;
7333}
5e9d9b82 7334
3772a991 7335/**
8a9d2e80 7336 * lpfc_free_sgl_list - Free a given sgl list.
da0436e9 7337 * @phba: pointer to lpfc hba data structure.
8a9d2e80 7338 * @sglq_list: pointer to the head of sgl list.
3772a991 7339 *
8a9d2e80 7340 * This routine is invoked to free a give sgl list and memory.
3772a991 7341 **/
8a9d2e80
JS
7342void
7343lpfc_free_sgl_list(struct lpfc_hba *phba, struct list_head *sglq_list)
3772a991 7344{
da0436e9 7345 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
8a9d2e80
JS
7346
7347 list_for_each_entry_safe(sglq_entry, sglq_next, sglq_list, list) {
7348 list_del(&sglq_entry->list);
7349 lpfc_mbuf_free(phba, sglq_entry->virt, sglq_entry->phys);
7350 kfree(sglq_entry);
7351 }
7352}
7353
7354/**
7355 * lpfc_free_els_sgl_list - Free els sgl list.
7356 * @phba: pointer to lpfc hba data structure.
7357 *
7358 * This routine is invoked to free the driver's els sgl list and memory.
7359 **/
7360static void
7361lpfc_free_els_sgl_list(struct lpfc_hba *phba)
7362{
da0436e9 7363 LIST_HEAD(sglq_list);
dea3101e 7364
8a9d2e80 7365 /* Retrieve all els sgls from driver list */
da0436e9 7366 spin_lock_irq(&phba->hbalock);
895427bd
JS
7367 spin_lock(&phba->sli4_hba.sgl_list_lock);
7368 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list, &sglq_list);
7369 spin_unlock(&phba->sli4_hba.sgl_list_lock);
da0436e9 7370 spin_unlock_irq(&phba->hbalock);
dea3101e 7371
8a9d2e80
JS
7372 /* Now free the sgl list */
7373 lpfc_free_sgl_list(phba, &sglq_list);
da0436e9 7374}
92d7f7b0 7375
f358dd0c
JS
7376/**
7377 * lpfc_free_nvmet_sgl_list - Free nvmet sgl list.
7378 * @phba: pointer to lpfc hba data structure.
7379 *
7380 * This routine is invoked to free the driver's nvmet sgl list and memory.
7381 **/
7382static void
7383lpfc_free_nvmet_sgl_list(struct lpfc_hba *phba)
7384{
7385 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
7386 LIST_HEAD(sglq_list);
7387
7388 /* Retrieve all nvmet sgls from driver list */
7389 spin_lock_irq(&phba->hbalock);
7390 spin_lock(&phba->sli4_hba.sgl_list_lock);
7391 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list, &sglq_list);
7392 spin_unlock(&phba->sli4_hba.sgl_list_lock);
7393 spin_unlock_irq(&phba->hbalock);
7394
7395 /* Now free the sgl list */
7396 list_for_each_entry_safe(sglq_entry, sglq_next, &sglq_list, list) {
7397 list_del(&sglq_entry->list);
7398 lpfc_nvmet_buf_free(phba, sglq_entry->virt, sglq_entry->phys);
7399 kfree(sglq_entry);
7400 }
4b40d02b
DK
7401
7402 /* Update the nvmet_xri_cnt to reflect no current sgls.
7403 * The next initialization cycle sets the count and allocates
7404 * the sgls over again.
7405 */
7406 phba->sli4_hba.nvmet_xri_cnt = 0;
f358dd0c
JS
7407}
7408
da0436e9
JS
7409/**
7410 * lpfc_init_active_sgl_array - Allocate the buf to track active ELS XRIs.
7411 * @phba: pointer to lpfc hba data structure.
7412 *
7413 * This routine is invoked to allocate the driver's active sgl memory.
7414 * This array will hold the sglq_entry's for active IOs.
7415 **/
7416static int
7417lpfc_init_active_sgl_array(struct lpfc_hba *phba)
7418{
7419 int size;
7420 size = sizeof(struct lpfc_sglq *);
7421 size *= phba->sli4_hba.max_cfg_param.max_xri;
7422
7423 phba->sli4_hba.lpfc_sglq_active_list =
7424 kzalloc(size, GFP_KERNEL);
7425 if (!phba->sli4_hba.lpfc_sglq_active_list)
7426 return -ENOMEM;
7427 return 0;
3772a991
JS
7428}
7429
7430/**
da0436e9 7431 * lpfc_free_active_sgl - Free the buf that tracks active ELS XRIs.
3772a991
JS
7432 * @phba: pointer to lpfc hba data structure.
7433 *
da0436e9
JS
7434 * This routine is invoked to walk through the array of active sglq entries
7435 * and free all of the resources.
7436 * This is just a place holder for now.
3772a991
JS
7437 **/
7438static void
da0436e9 7439lpfc_free_active_sgl(struct lpfc_hba *phba)
3772a991 7440{
da0436e9 7441 kfree(phba->sli4_hba.lpfc_sglq_active_list);
3772a991
JS
7442}
7443
7444/**
da0436e9 7445 * lpfc_init_sgl_list - Allocate and initialize sgl list.
3772a991
JS
7446 * @phba: pointer to lpfc hba data structure.
7447 *
da0436e9
JS
7448 * This routine is invoked to allocate and initizlize the driver's sgl
7449 * list and set up the sgl xritag tag array accordingly.
3772a991 7450 *
3772a991 7451 **/
8a9d2e80 7452static void
da0436e9 7453lpfc_init_sgl_list(struct lpfc_hba *phba)
3772a991 7454{
da0436e9 7455 /* Initialize and populate the sglq list per host/VF. */
895427bd 7456 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_els_sgl_list);
da0436e9 7457 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_els_sgl_list);
f358dd0c 7458 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_sgl_list);
86c67379 7459 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
da0436e9 7460
8a9d2e80
JS
7461 /* els xri-sgl book keeping */
7462 phba->sli4_hba.els_xri_cnt = 0;
0ff10d46 7463
895427bd 7464 /* nvme xri-buffer book keeping */
5e5b511d 7465 phba->sli4_hba.io_xri_cnt = 0;
da0436e9
JS
7466}
7467
7468/**
7469 * lpfc_sli4_init_rpi_hdrs - Post the rpi header memory region to the port
7470 * @phba: pointer to lpfc hba data structure.
7471 *
7472 * This routine is invoked to post rpi header templates to the
88a2cfbb 7473 * port for those SLI4 ports that do not support extents. This routine
da0436e9 7474 * posts a PAGE_SIZE memory region to the port to hold up to
88a2cfbb
JS
7475 * PAGE_SIZE modulo 64 rpi context headers. This is an initialization routine
7476 * and should be called only when interrupts are disabled.
da0436e9
JS
7477 *
7478 * Return codes
af901ca1 7479 * 0 - successful
88a2cfbb 7480 * -ERROR - otherwise.
da0436e9
JS
7481 **/
7482int
7483lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *phba)
7484{
7485 int rc = 0;
da0436e9
JS
7486 struct lpfc_rpi_hdr *rpi_hdr;
7487
7488 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_hdr_list);
ff78d8f9 7489 if (!phba->sli4_hba.rpi_hdrs_in_use)
6d368e53 7490 return rc;
6d368e53
JS
7491 if (phba->sli4_hba.extents_in_use)
7492 return -EIO;
da0436e9
JS
7493
7494 rpi_hdr = lpfc_sli4_create_rpi_hdr(phba);
7495 if (!rpi_hdr) {
372c187b 7496 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
7497 "0391 Error during rpi post operation\n");
7498 lpfc_sli4_remove_rpis(phba);
7499 rc = -ENODEV;
7500 }
7501
7502 return rc;
7503}
7504
7505/**
7506 * lpfc_sli4_create_rpi_hdr - Allocate an rpi header memory region
7507 * @phba: pointer to lpfc hba data structure.
7508 *
7509 * This routine is invoked to allocate a single 4KB memory region to
7510 * support rpis and stores them in the phba. This single region
7511 * provides support for up to 64 rpis. The region is used globally
7512 * by the device.
7513 *
7514 * Returns:
7515 * A valid rpi hdr on success.
7516 * A NULL pointer on any failure.
7517 **/
7518struct lpfc_rpi_hdr *
7519lpfc_sli4_create_rpi_hdr(struct lpfc_hba *phba)
7520{
7521 uint16_t rpi_limit, curr_rpi_range;
7522 struct lpfc_dmabuf *dmabuf;
7523 struct lpfc_rpi_hdr *rpi_hdr;
7524
6d368e53
JS
7525 /*
7526 * If the SLI4 port supports extents, posting the rpi header isn't
7527 * required. Set the expected maximum count and let the actual value
7528 * get set when extents are fully allocated.
7529 */
7530 if (!phba->sli4_hba.rpi_hdrs_in_use)
7531 return NULL;
7532 if (phba->sli4_hba.extents_in_use)
7533 return NULL;
7534
7535 /* The limit on the logical index is just the max_rpi count. */
845d9e8d 7536 rpi_limit = phba->sli4_hba.max_cfg_param.max_rpi;
da0436e9
JS
7537
7538 spin_lock_irq(&phba->hbalock);
6d368e53
JS
7539 /*
7540 * Establish the starting RPI in this header block. The starting
7541 * rpi is normalized to a zero base because the physical rpi is
7542 * port based.
7543 */
97f2ecf1 7544 curr_rpi_range = phba->sli4_hba.next_rpi;
da0436e9
JS
7545 spin_unlock_irq(&phba->hbalock);
7546
845d9e8d
JS
7547 /* Reached full RPI range */
7548 if (curr_rpi_range == rpi_limit)
6d368e53 7549 return NULL;
845d9e8d 7550
da0436e9
JS
7551 /*
7552 * First allocate the protocol header region for the port. The
7553 * port expects a 4KB DMA-mapped memory region that is 4K aligned.
7554 */
7555 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
7556 if (!dmabuf)
7557 return NULL;
7558
750afb08
LC
7559 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
7560 LPFC_HDR_TEMPLATE_SIZE,
7561 &dmabuf->phys, GFP_KERNEL);
da0436e9
JS
7562 if (!dmabuf->virt) {
7563 rpi_hdr = NULL;
7564 goto err_free_dmabuf;
7565 }
7566
da0436e9
JS
7567 if (!IS_ALIGNED(dmabuf->phys, LPFC_HDR_TEMPLATE_SIZE)) {
7568 rpi_hdr = NULL;
7569 goto err_free_coherent;
7570 }
7571
7572 /* Save the rpi header data for cleanup later. */
7573 rpi_hdr = kzalloc(sizeof(struct lpfc_rpi_hdr), GFP_KERNEL);
7574 if (!rpi_hdr)
7575 goto err_free_coherent;
7576
7577 rpi_hdr->dmabuf = dmabuf;
7578 rpi_hdr->len = LPFC_HDR_TEMPLATE_SIZE;
7579 rpi_hdr->page_count = 1;
7580 spin_lock_irq(&phba->hbalock);
6d368e53
JS
7581
7582 /* The rpi_hdr stores the logical index only. */
7583 rpi_hdr->start_rpi = curr_rpi_range;
845d9e8d 7584 rpi_hdr->next_rpi = phba->sli4_hba.next_rpi + LPFC_RPI_HDR_COUNT;
da0436e9
JS
7585 list_add_tail(&rpi_hdr->list, &phba->sli4_hba.lpfc_rpi_hdr_list);
7586
da0436e9
JS
7587 spin_unlock_irq(&phba->hbalock);
7588 return rpi_hdr;
7589
7590 err_free_coherent:
7591 dma_free_coherent(&phba->pcidev->dev, LPFC_HDR_TEMPLATE_SIZE,
7592 dmabuf->virt, dmabuf->phys);
7593 err_free_dmabuf:
7594 kfree(dmabuf);
7595 return NULL;
7596}
7597
7598/**
7599 * lpfc_sli4_remove_rpi_hdrs - Remove all rpi header memory regions
7600 * @phba: pointer to lpfc hba data structure.
7601 *
7602 * This routine is invoked to remove all memory resources allocated
6d368e53
JS
7603 * to support rpis for SLI4 ports not supporting extents. This routine
7604 * presumes the caller has released all rpis consumed by fabric or port
7605 * logins and is prepared to have the header pages removed.
da0436e9
JS
7606 **/
7607void
7608lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *phba)
7609{
7610 struct lpfc_rpi_hdr *rpi_hdr, *next_rpi_hdr;
7611
6d368e53
JS
7612 if (!phba->sli4_hba.rpi_hdrs_in_use)
7613 goto exit;
7614
da0436e9
JS
7615 list_for_each_entry_safe(rpi_hdr, next_rpi_hdr,
7616 &phba->sli4_hba.lpfc_rpi_hdr_list, list) {
7617 list_del(&rpi_hdr->list);
7618 dma_free_coherent(&phba->pcidev->dev, rpi_hdr->len,
7619 rpi_hdr->dmabuf->virt, rpi_hdr->dmabuf->phys);
7620 kfree(rpi_hdr->dmabuf);
7621 kfree(rpi_hdr);
7622 }
6d368e53
JS
7623 exit:
7624 /* There are no rpis available to the port now. */
7625 phba->sli4_hba.next_rpi = 0;
da0436e9
JS
7626}
7627
7628/**
7629 * lpfc_hba_alloc - Allocate driver hba data structure for a device.
7630 * @pdev: pointer to pci device data structure.
7631 *
7632 * This routine is invoked to allocate the driver hba data structure for an
7633 * HBA device. If the allocation is successful, the phba reference to the
7634 * PCI device data structure is set.
7635 *
7636 * Return codes
af901ca1 7637 * pointer to @phba - successful
da0436e9
JS
7638 * NULL - error
7639 **/
7640static struct lpfc_hba *
7641lpfc_hba_alloc(struct pci_dev *pdev)
7642{
7643 struct lpfc_hba *phba;
7644
7645 /* Allocate memory for HBA structure */
7646 phba = kzalloc(sizeof(struct lpfc_hba), GFP_KERNEL);
7647 if (!phba) {
e34ccdfe 7648 dev_err(&pdev->dev, "failed to allocate hba struct\n");
da0436e9
JS
7649 return NULL;
7650 }
7651
7652 /* Set reference to PCI device in HBA structure */
7653 phba->pcidev = pdev;
7654
7655 /* Assign an unused board number */
7656 phba->brd_no = lpfc_get_instance();
7657 if (phba->brd_no < 0) {
7658 kfree(phba);
7659 return NULL;
7660 }
65791f1f 7661 phba->eratt_poll_interval = LPFC_ERATT_POLL_INTERVAL;
da0436e9 7662
4fede78f 7663 spin_lock_init(&phba->ct_ev_lock);
f1c3b0fc
JS
7664 INIT_LIST_HEAD(&phba->ct_ev_waiters);
7665
da0436e9
JS
7666 return phba;
7667}
7668
7669/**
7670 * lpfc_hba_free - Free driver hba data structure with a device.
7671 * @phba: pointer to lpfc hba data structure.
7672 *
7673 * This routine is invoked to free the driver hba data structure with an
7674 * HBA device.
7675 **/
7676static void
7677lpfc_hba_free(struct lpfc_hba *phba)
7678{
5e5b511d
JS
7679 if (phba->sli_rev == LPFC_SLI_REV4)
7680 kfree(phba->sli4_hba.hdwq);
7681
da0436e9
JS
7682 /* Release the driver assigned board number */
7683 idr_remove(&lpfc_hba_index, phba->brd_no);
7684
895427bd
JS
7685 /* Free memory allocated with sli3 rings */
7686 kfree(phba->sli.sli3_ring);
7687 phba->sli.sli3_ring = NULL;
2a76a283 7688
da0436e9
JS
7689 kfree(phba);
7690 return;
7691}
7692
7693/**
7694 * lpfc_create_shost - Create hba physical port with associated scsi host.
7695 * @phba: pointer to lpfc hba data structure.
7696 *
7697 * This routine is invoked to create HBA physical port and associate a SCSI
7698 * host with it.
7699 *
7700 * Return codes
af901ca1 7701 * 0 - successful
da0436e9
JS
7702 * other values - error
7703 **/
7704static int
7705lpfc_create_shost(struct lpfc_hba *phba)
7706{
7707 struct lpfc_vport *vport;
7708 struct Scsi_Host *shost;
7709
7710 /* Initialize HBA FC structure */
7711 phba->fc_edtov = FF_DEF_EDTOV;
7712 phba->fc_ratov = FF_DEF_RATOV;
7713 phba->fc_altov = FF_DEF_ALTOV;
7714 phba->fc_arbtov = FF_DEF_ARBTOV;
7715
d7c47992 7716 atomic_set(&phba->sdev_cnt, 0);
da0436e9
JS
7717 vport = lpfc_create_port(phba, phba->brd_no, &phba->pcidev->dev);
7718 if (!vport)
7719 return -ENODEV;
7720
7721 shost = lpfc_shost_from_vport(vport);
7722 phba->pport = vport;
2ea259ee 7723
f358dd0c
JS
7724 if (phba->nvmet_support) {
7725 /* Only 1 vport (pport) will support NVME target */
ea85a20c
JS
7726 phba->targetport = NULL;
7727 phba->cfg_enable_fc4_type = LPFC_ENABLE_NVME;
7728 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME_DISC,
7729 "6076 NVME Target Found\n");
f358dd0c
JS
7730 }
7731
da0436e9
JS
7732 lpfc_debugfs_initialize(vport);
7733 /* Put reference to SCSI host to driver's device private data */
7734 pci_set_drvdata(phba->pcidev, shost);
2e0fef85 7735
4258e98e
JS
7736 /*
7737 * At this point we are fully registered with PSA. In addition,
7738 * any initial discovery should be completed.
7739 */
7740 vport->load_flag |= FC_ALLOW_FDMI;
8663cbbe
JS
7741 if (phba->cfg_enable_SmartSAN ||
7742 (phba->cfg_fdmi_on == LPFC_FDMI_SUPPORT)) {
4258e98e
JS
7743
7744 /* Setup appropriate attribute masks */
7745 vport->fdmi_hba_mask = LPFC_FDMI2_HBA_ATTR;
8663cbbe 7746 if (phba->cfg_enable_SmartSAN)
4258e98e
JS
7747 vport->fdmi_port_mask = LPFC_FDMI2_SMART_ATTR;
7748 else
7749 vport->fdmi_port_mask = LPFC_FDMI2_PORT_ATTR;
7750 }
3772a991
JS
7751 return 0;
7752}
db2378e0 7753
3772a991
JS
7754/**
7755 * lpfc_destroy_shost - Destroy hba physical port with associated scsi host.
7756 * @phba: pointer to lpfc hba data structure.
7757 *
7758 * This routine is invoked to destroy HBA physical port and the associated
7759 * SCSI host.
7760 **/
7761static void
7762lpfc_destroy_shost(struct lpfc_hba *phba)
7763{
7764 struct lpfc_vport *vport = phba->pport;
7765
7766 /* Destroy physical port that associated with the SCSI host */
7767 destroy_port(vport);
7768
7769 return;
7770}
7771
7772/**
7773 * lpfc_setup_bg - Setup Block guard structures and debug areas.
7774 * @phba: pointer to lpfc hba data structure.
7775 * @shost: the shost to be used to detect Block guard settings.
7776 *
7777 * This routine sets up the local Block guard protocol settings for @shost.
7778 * This routine also allocates memory for debugging bg buffers.
7779 **/
7780static void
7781lpfc_setup_bg(struct lpfc_hba *phba, struct Scsi_Host *shost)
7782{
bbeb79b9
JS
7783 uint32_t old_mask;
7784 uint32_t old_guard;
7785
b3b98b74 7786 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
3772a991
JS
7787 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7788 "1478 Registering BlockGuard with the "
7789 "SCSI layer\n");
bbeb79b9 7790
b3b98b74
JS
7791 old_mask = phba->cfg_prot_mask;
7792 old_guard = phba->cfg_prot_guard;
bbeb79b9
JS
7793
7794 /* Only allow supported values */
b3b98b74 7795 phba->cfg_prot_mask &= (SHOST_DIF_TYPE1_PROTECTION |
bbeb79b9
JS
7796 SHOST_DIX_TYPE0_PROTECTION |
7797 SHOST_DIX_TYPE1_PROTECTION);
b3b98b74
JS
7798 phba->cfg_prot_guard &= (SHOST_DIX_GUARD_IP |
7799 SHOST_DIX_GUARD_CRC);
bbeb79b9
JS
7800
7801 /* DIF Type 1 protection for profiles AST1/C1 is end to end */
b3b98b74
JS
7802 if (phba->cfg_prot_mask == SHOST_DIX_TYPE1_PROTECTION)
7803 phba->cfg_prot_mask |= SHOST_DIF_TYPE1_PROTECTION;
bbeb79b9 7804
b3b98b74
JS
7805 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
7806 if ((old_mask != phba->cfg_prot_mask) ||
7807 (old_guard != phba->cfg_prot_guard))
372c187b 7808 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
bbeb79b9
JS
7809 "1475 Registering BlockGuard with the "
7810 "SCSI layer: mask %d guard %d\n",
b3b98b74
JS
7811 phba->cfg_prot_mask,
7812 phba->cfg_prot_guard);
bbeb79b9 7813
b3b98b74
JS
7814 scsi_host_set_prot(shost, phba->cfg_prot_mask);
7815 scsi_host_set_guard(shost, phba->cfg_prot_guard);
bbeb79b9 7816 } else
372c187b 7817 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
bbeb79b9
JS
7818 "1479 Not Registering BlockGuard with the SCSI "
7819 "layer, Bad protection parameters: %d %d\n",
7820 old_mask, old_guard);
3772a991 7821 }
3772a991
JS
7822}
7823
7824/**
7825 * lpfc_post_init_setup - Perform necessary device post initialization setup.
7826 * @phba: pointer to lpfc hba data structure.
7827 *
7828 * This routine is invoked to perform all the necessary post initialization
7829 * setup for the device.
7830 **/
7831static void
7832lpfc_post_init_setup(struct lpfc_hba *phba)
7833{
7834 struct Scsi_Host *shost;
7835 struct lpfc_adapter_event_header adapter_event;
7836
7837 /* Get the default values for Model Name and Description */
7838 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
7839
7840 /*
7841 * hba setup may have changed the hba_queue_depth so we need to
7842 * adjust the value of can_queue.
7843 */
7844 shost = pci_get_drvdata(phba->pcidev);
7845 shost->can_queue = phba->cfg_hba_queue_depth - 10;
3772a991
JS
7846
7847 lpfc_host_attrib_init(shost);
7848
7849 if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
7850 spin_lock_irq(shost->host_lock);
7851 lpfc_poll_start_timer(phba);
7852 spin_unlock_irq(shost->host_lock);
7853 }
7854
7855 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7856 "0428 Perform SCSI scan\n");
7857 /* Send board arrival event to upper layer */
7858 adapter_event.event_type = FC_REG_ADAPTER_EVENT;
7859 adapter_event.subcategory = LPFC_EVENT_ARRIVAL;
7860 fc_host_post_vendor_event(shost, fc_get_event_number(),
7861 sizeof(adapter_event),
7862 (char *) &adapter_event,
7863 LPFC_NL_VENDOR_ID);
7864 return;
7865}
7866
7867/**
7868 * lpfc_sli_pci_mem_setup - Setup SLI3 HBA PCI memory space.
7869 * @phba: pointer to lpfc hba data structure.
7870 *
7871 * This routine is invoked to set up the PCI device memory space for device
7872 * with SLI-3 interface spec.
7873 *
7874 * Return codes
af901ca1 7875 * 0 - successful
3772a991
JS
7876 * other values - error
7877 **/
7878static int
7879lpfc_sli_pci_mem_setup(struct lpfc_hba *phba)
7880{
f30e1bfd 7881 struct pci_dev *pdev = phba->pcidev;
3772a991
JS
7882 unsigned long bar0map_len, bar2map_len;
7883 int i, hbq_count;
7884 void *ptr;
56de8357 7885 int error;
3772a991 7886
f30e1bfd 7887 if (!pdev)
56de8357 7888 return -ENODEV;
3772a991
JS
7889
7890 /* Set the device DMA mask size */
56de8357
HR
7891 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7892 if (error)
7893 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7894 if (error)
f30e1bfd 7895 return error;
56de8357 7896 error = -ENODEV;
3772a991
JS
7897
7898 /* Get the bus address of Bar0 and Bar2 and the number of bytes
7899 * required by each mapping.
7900 */
7901 phba->pci_bar0_map = pci_resource_start(pdev, 0);
7902 bar0map_len = pci_resource_len(pdev, 0);
7903
7904 phba->pci_bar2_map = pci_resource_start(pdev, 2);
7905 bar2map_len = pci_resource_len(pdev, 2);
7906
7907 /* Map HBA SLIM to a kernel virtual address. */
7908 phba->slim_memmap_p = ioremap(phba->pci_bar0_map, bar0map_len);
7909 if (!phba->slim_memmap_p) {
7910 dev_printk(KERN_ERR, &pdev->dev,
7911 "ioremap failed for SLIM memory.\n");
7912 goto out;
7913 }
7914
7915 /* Map HBA Control Registers to a kernel virtual address. */
7916 phba->ctrl_regs_memmap_p = ioremap(phba->pci_bar2_map, bar2map_len);
7917 if (!phba->ctrl_regs_memmap_p) {
7918 dev_printk(KERN_ERR, &pdev->dev,
7919 "ioremap failed for HBA control registers.\n");
7920 goto out_iounmap_slim;
7921 }
7922
7923 /* Allocate memory for SLI-2 structures */
750afb08
LC
7924 phba->slim2p.virt = dma_alloc_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7925 &phba->slim2p.phys, GFP_KERNEL);
3772a991
JS
7926 if (!phba->slim2p.virt)
7927 goto out_iounmap;
7928
3772a991 7929 phba->mbox = phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, mbx);
7a470277
JS
7930 phba->mbox_ext = (phba->slim2p.virt +
7931 offsetof(struct lpfc_sli2_slim, mbx_ext_words));
3772a991
JS
7932 phba->pcb = (phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, pcb));
7933 phba->IOCBs = (phba->slim2p.virt +
7934 offsetof(struct lpfc_sli2_slim, IOCBs));
7935
7936 phba->hbqslimp.virt = dma_alloc_coherent(&pdev->dev,
7937 lpfc_sli_hbq_size(),
7938 &phba->hbqslimp.phys,
7939 GFP_KERNEL);
7940 if (!phba->hbqslimp.virt)
7941 goto out_free_slim;
7942
7943 hbq_count = lpfc_sli_hbq_count();
7944 ptr = phba->hbqslimp.virt;
7945 for (i = 0; i < hbq_count; ++i) {
7946 phba->hbqs[i].hbq_virt = ptr;
7947 INIT_LIST_HEAD(&phba->hbqs[i].hbq_buffer_list);
7948 ptr += (lpfc_hbq_defs[i]->entry_count *
7949 sizeof(struct lpfc_hbq_entry));
7950 }
7951 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_els_hbq_alloc;
7952 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_els_hbq_free;
7953
7954 memset(phba->hbqslimp.virt, 0, lpfc_sli_hbq_size());
7955
3772a991
JS
7956 phba->MBslimaddr = phba->slim_memmap_p;
7957 phba->HAregaddr = phba->ctrl_regs_memmap_p + HA_REG_OFFSET;
7958 phba->CAregaddr = phba->ctrl_regs_memmap_p + CA_REG_OFFSET;
7959 phba->HSregaddr = phba->ctrl_regs_memmap_p + HS_REG_OFFSET;
7960 phba->HCregaddr = phba->ctrl_regs_memmap_p + HC_REG_OFFSET;
7961
7962 return 0;
7963
7964out_free_slim:
7965 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7966 phba->slim2p.virt, phba->slim2p.phys);
7967out_iounmap:
7968 iounmap(phba->ctrl_regs_memmap_p);
7969out_iounmap_slim:
7970 iounmap(phba->slim_memmap_p);
7971out:
7972 return error;
7973}
7974
7975/**
7976 * lpfc_sli_pci_mem_unset - Unset SLI3 HBA PCI memory space.
7977 * @phba: pointer to lpfc hba data structure.
7978 *
7979 * This routine is invoked to unset the PCI device memory space for device
7980 * with SLI-3 interface spec.
7981 **/
7982static void
7983lpfc_sli_pci_mem_unset(struct lpfc_hba *phba)
7984{
7985 struct pci_dev *pdev;
7986
7987 /* Obtain PCI device reference */
7988 if (!phba->pcidev)
7989 return;
7990 else
7991 pdev = phba->pcidev;
7992
7993 /* Free coherent DMA memory allocated */
7994 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
7995 phba->hbqslimp.virt, phba->hbqslimp.phys);
7996 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7997 phba->slim2p.virt, phba->slim2p.phys);
7998
7999 /* I/O memory unmap */
8000 iounmap(phba->ctrl_regs_memmap_p);
8001 iounmap(phba->slim_memmap_p);
8002
8003 return;
8004}
8005
8006/**
da0436e9 8007 * lpfc_sli4_post_status_check - Wait for SLI4 POST done and check status
3772a991
JS
8008 * @phba: pointer to lpfc hba data structure.
8009 *
da0436e9
JS
8010 * This routine is invoked to wait for SLI4 device Power On Self Test (POST)
8011 * done and check status.
3772a991 8012 *
da0436e9 8013 * Return 0 if successful, otherwise -ENODEV.
3772a991 8014 **/
da0436e9
JS
8015int
8016lpfc_sli4_post_status_check(struct lpfc_hba *phba)
3772a991 8017{
2fcee4bf
JS
8018 struct lpfc_register portsmphr_reg, uerrlo_reg, uerrhi_reg;
8019 struct lpfc_register reg_data;
8020 int i, port_error = 0;
8021 uint32_t if_type;
3772a991 8022
9940b97b
JS
8023 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
8024 memset(&reg_data, 0, sizeof(reg_data));
2fcee4bf 8025 if (!phba->sli4_hba.PSMPHRregaddr)
da0436e9 8026 return -ENODEV;
3772a991 8027
da0436e9
JS
8028 /* Wait up to 30 seconds for the SLI Port POST done and ready */
8029 for (i = 0; i < 3000; i++) {
9940b97b
JS
8030 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
8031 &portsmphr_reg.word0) ||
8032 (bf_get(lpfc_port_smphr_perr, &portsmphr_reg))) {
2fcee4bf 8033 /* Port has a fatal POST error, break out */
da0436e9
JS
8034 port_error = -ENODEV;
8035 break;
8036 }
2fcee4bf
JS
8037 if (LPFC_POST_STAGE_PORT_READY ==
8038 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg))
da0436e9 8039 break;
da0436e9 8040 msleep(10);
3772a991
JS
8041 }
8042
2fcee4bf
JS
8043 /*
8044 * If there was a port error during POST, then don't proceed with
8045 * other register reads as the data may not be valid. Just exit.
8046 */
8047 if (port_error) {
372c187b 8048 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
8049 "1408 Port Failed POST - portsmphr=0x%x, "
8050 "perr=x%x, sfi=x%x, nip=x%x, ipc=x%x, scr1=x%x, "
8051 "scr2=x%x, hscratch=x%x, pstatus=x%x\n",
8052 portsmphr_reg.word0,
8053 bf_get(lpfc_port_smphr_perr, &portsmphr_reg),
8054 bf_get(lpfc_port_smphr_sfi, &portsmphr_reg),
8055 bf_get(lpfc_port_smphr_nip, &portsmphr_reg),
8056 bf_get(lpfc_port_smphr_ipc, &portsmphr_reg),
8057 bf_get(lpfc_port_smphr_scr1, &portsmphr_reg),
8058 bf_get(lpfc_port_smphr_scr2, &portsmphr_reg),
8059 bf_get(lpfc_port_smphr_host_scratch, &portsmphr_reg),
8060 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg));
8061 } else {
28baac74 8062 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
2fcee4bf
JS
8063 "2534 Device Info: SLIFamily=0x%x, "
8064 "SLIRev=0x%x, IFType=0x%x, SLIHint_1=0x%x, "
8065 "SLIHint_2=0x%x, FT=0x%x\n",
28baac74
JS
8066 bf_get(lpfc_sli_intf_sli_family,
8067 &phba->sli4_hba.sli_intf),
8068 bf_get(lpfc_sli_intf_slirev,
8069 &phba->sli4_hba.sli_intf),
085c647c
JS
8070 bf_get(lpfc_sli_intf_if_type,
8071 &phba->sli4_hba.sli_intf),
8072 bf_get(lpfc_sli_intf_sli_hint1,
28baac74 8073 &phba->sli4_hba.sli_intf),
085c647c
JS
8074 bf_get(lpfc_sli_intf_sli_hint2,
8075 &phba->sli4_hba.sli_intf),
8076 bf_get(lpfc_sli_intf_func_type,
28baac74 8077 &phba->sli4_hba.sli_intf));
2fcee4bf
JS
8078 /*
8079 * Check for other Port errors during the initialization
8080 * process. Fail the load if the port did not come up
8081 * correctly.
8082 */
8083 if_type = bf_get(lpfc_sli_intf_if_type,
8084 &phba->sli4_hba.sli_intf);
8085 switch (if_type) {
8086 case LPFC_SLI_INTF_IF_TYPE_0:
8087 phba->sli4_hba.ue_mask_lo =
8088 readl(phba->sli4_hba.u.if_type0.UEMASKLOregaddr);
8089 phba->sli4_hba.ue_mask_hi =
8090 readl(phba->sli4_hba.u.if_type0.UEMASKHIregaddr);
8091 uerrlo_reg.word0 =
8092 readl(phba->sli4_hba.u.if_type0.UERRLOregaddr);
8093 uerrhi_reg.word0 =
8094 readl(phba->sli4_hba.u.if_type0.UERRHIregaddr);
8095 if ((~phba->sli4_hba.ue_mask_lo & uerrlo_reg.word0) ||
8096 (~phba->sli4_hba.ue_mask_hi & uerrhi_reg.word0)) {
372c187b
DK
8097 lpfc_printf_log(phba, KERN_ERR,
8098 LOG_TRACE_EVENT,
2fcee4bf
JS
8099 "1422 Unrecoverable Error "
8100 "Detected during POST "
8101 "uerr_lo_reg=0x%x, "
8102 "uerr_hi_reg=0x%x, "
8103 "ue_mask_lo_reg=0x%x, "
8104 "ue_mask_hi_reg=0x%x\n",
8105 uerrlo_reg.word0,
8106 uerrhi_reg.word0,
8107 phba->sli4_hba.ue_mask_lo,
8108 phba->sli4_hba.ue_mask_hi);
8109 port_error = -ENODEV;
8110 }
8111 break;
8112 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 8113 case LPFC_SLI_INTF_IF_TYPE_6:
2fcee4bf 8114 /* Final checks. The port status should be clean. */
9940b97b
JS
8115 if (lpfc_readl(phba->sli4_hba.u.if_type2.STATUSregaddr,
8116 &reg_data.word0) ||
0558056c
JS
8117 (bf_get(lpfc_sliport_status_err, &reg_data) &&
8118 !bf_get(lpfc_sliport_status_rn, &reg_data))) {
2fcee4bf
JS
8119 phba->work_status[0] =
8120 readl(phba->sli4_hba.u.if_type2.
8121 ERR1regaddr);
8122 phba->work_status[1] =
8123 readl(phba->sli4_hba.u.if_type2.
8124 ERR2regaddr);
372c187b 8125 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
8fcb8acd
JS
8126 "2888 Unrecoverable port error "
8127 "following POST: port status reg "
8128 "0x%x, port_smphr reg 0x%x, "
2fcee4bf
JS
8129 "error 1=0x%x, error 2=0x%x\n",
8130 reg_data.word0,
8131 portsmphr_reg.word0,
8132 phba->work_status[0],
8133 phba->work_status[1]);
8134 port_error = -ENODEV;
8135 }
8136 break;
8137 case LPFC_SLI_INTF_IF_TYPE_1:
8138 default:
8139 break;
8140 }
28baac74 8141 }
da0436e9
JS
8142 return port_error;
8143}
3772a991 8144
da0436e9
JS
8145/**
8146 * lpfc_sli4_bar0_register_memmap - Set up SLI4 BAR0 register memory map.
8147 * @phba: pointer to lpfc hba data structure.
2fcee4bf 8148 * @if_type: The SLI4 interface type getting configured.
da0436e9
JS
8149 *
8150 * This routine is invoked to set up SLI4 BAR0 PCI config space register
8151 * memory map.
8152 **/
8153static void
2fcee4bf
JS
8154lpfc_sli4_bar0_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
8155{
8156 switch (if_type) {
8157 case LPFC_SLI_INTF_IF_TYPE_0:
8158 phba->sli4_hba.u.if_type0.UERRLOregaddr =
8159 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_LO;
8160 phba->sli4_hba.u.if_type0.UERRHIregaddr =
8161 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_HI;
8162 phba->sli4_hba.u.if_type0.UEMASKLOregaddr =
8163 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_LO;
8164 phba->sli4_hba.u.if_type0.UEMASKHIregaddr =
8165 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_HI;
8166 phba->sli4_hba.SLIINTFregaddr =
8167 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
8168 break;
8169 case LPFC_SLI_INTF_IF_TYPE_2:
0cf07f84
JS
8170 phba->sli4_hba.u.if_type2.EQDregaddr =
8171 phba->sli4_hba.conf_regs_memmap_p +
8172 LPFC_CTL_PORT_EQ_DELAY_OFFSET;
2fcee4bf 8173 phba->sli4_hba.u.if_type2.ERR1regaddr =
88a2cfbb
JS
8174 phba->sli4_hba.conf_regs_memmap_p +
8175 LPFC_CTL_PORT_ER1_OFFSET;
2fcee4bf 8176 phba->sli4_hba.u.if_type2.ERR2regaddr =
88a2cfbb
JS
8177 phba->sli4_hba.conf_regs_memmap_p +
8178 LPFC_CTL_PORT_ER2_OFFSET;
2fcee4bf 8179 phba->sli4_hba.u.if_type2.CTRLregaddr =
88a2cfbb
JS
8180 phba->sli4_hba.conf_regs_memmap_p +
8181 LPFC_CTL_PORT_CTL_OFFSET;
2fcee4bf 8182 phba->sli4_hba.u.if_type2.STATUSregaddr =
88a2cfbb
JS
8183 phba->sli4_hba.conf_regs_memmap_p +
8184 LPFC_CTL_PORT_STA_OFFSET;
2fcee4bf
JS
8185 phba->sli4_hba.SLIINTFregaddr =
8186 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
8187 phba->sli4_hba.PSMPHRregaddr =
88a2cfbb
JS
8188 phba->sli4_hba.conf_regs_memmap_p +
8189 LPFC_CTL_PORT_SEM_OFFSET;
2fcee4bf 8190 phba->sli4_hba.RQDBregaddr =
962bc51b
JS
8191 phba->sli4_hba.conf_regs_memmap_p +
8192 LPFC_ULP0_RQ_DOORBELL;
2fcee4bf 8193 phba->sli4_hba.WQDBregaddr =
962bc51b
JS
8194 phba->sli4_hba.conf_regs_memmap_p +
8195 LPFC_ULP0_WQ_DOORBELL;
9dd35425 8196 phba->sli4_hba.CQDBregaddr =
2fcee4bf 8197 phba->sli4_hba.conf_regs_memmap_p + LPFC_EQCQ_DOORBELL;
9dd35425 8198 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.CQDBregaddr;
2fcee4bf
JS
8199 phba->sli4_hba.MQDBregaddr =
8200 phba->sli4_hba.conf_regs_memmap_p + LPFC_MQ_DOORBELL;
8201 phba->sli4_hba.BMBXregaddr =
8202 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
8203 break;
27d6ac0a
JS
8204 case LPFC_SLI_INTF_IF_TYPE_6:
8205 phba->sli4_hba.u.if_type2.EQDregaddr =
8206 phba->sli4_hba.conf_regs_memmap_p +
8207 LPFC_CTL_PORT_EQ_DELAY_OFFSET;
8208 phba->sli4_hba.u.if_type2.ERR1regaddr =
8209 phba->sli4_hba.conf_regs_memmap_p +
8210 LPFC_CTL_PORT_ER1_OFFSET;
8211 phba->sli4_hba.u.if_type2.ERR2regaddr =
8212 phba->sli4_hba.conf_regs_memmap_p +
8213 LPFC_CTL_PORT_ER2_OFFSET;
8214 phba->sli4_hba.u.if_type2.CTRLregaddr =
8215 phba->sli4_hba.conf_regs_memmap_p +
8216 LPFC_CTL_PORT_CTL_OFFSET;
8217 phba->sli4_hba.u.if_type2.STATUSregaddr =
8218 phba->sli4_hba.conf_regs_memmap_p +
8219 LPFC_CTL_PORT_STA_OFFSET;
8220 phba->sli4_hba.PSMPHRregaddr =
8221 phba->sli4_hba.conf_regs_memmap_p +
8222 LPFC_CTL_PORT_SEM_OFFSET;
8223 phba->sli4_hba.BMBXregaddr =
8224 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
8225 break;
2fcee4bf
JS
8226 case LPFC_SLI_INTF_IF_TYPE_1:
8227 default:
8228 dev_printk(KERN_ERR, &phba->pcidev->dev,
8229 "FATAL - unsupported SLI4 interface type - %d\n",
8230 if_type);
8231 break;
8232 }
da0436e9 8233}
3772a991 8234
da0436e9
JS
8235/**
8236 * lpfc_sli4_bar1_register_memmap - Set up SLI4 BAR1 register memory map.
8237 * @phba: pointer to lpfc hba data structure.
fe614acd 8238 * @if_type: sli if type to operate on.
da0436e9 8239 *
27d6ac0a 8240 * This routine is invoked to set up SLI4 BAR1 register memory map.
da0436e9
JS
8241 **/
8242static void
27d6ac0a 8243lpfc_sli4_bar1_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
da0436e9 8244{
27d6ac0a
JS
8245 switch (if_type) {
8246 case LPFC_SLI_INTF_IF_TYPE_0:
8247 phba->sli4_hba.PSMPHRregaddr =
8248 phba->sli4_hba.ctrl_regs_memmap_p +
8249 LPFC_SLIPORT_IF0_SMPHR;
8250 phba->sli4_hba.ISRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8251 LPFC_HST_ISR0;
8252 phba->sli4_hba.IMRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8253 LPFC_HST_IMR0;
8254 phba->sli4_hba.ISCRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8255 LPFC_HST_ISCR0;
8256 break;
8257 case LPFC_SLI_INTF_IF_TYPE_6:
8258 phba->sli4_hba.RQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8259 LPFC_IF6_RQ_DOORBELL;
8260 phba->sli4_hba.WQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8261 LPFC_IF6_WQ_DOORBELL;
8262 phba->sli4_hba.CQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8263 LPFC_IF6_CQ_DOORBELL;
8264 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8265 LPFC_IF6_EQ_DOORBELL;
8266 phba->sli4_hba.MQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8267 LPFC_IF6_MQ_DOORBELL;
8268 break;
8269 case LPFC_SLI_INTF_IF_TYPE_2:
8270 case LPFC_SLI_INTF_IF_TYPE_1:
8271 default:
8272 dev_err(&phba->pcidev->dev,
8273 "FATAL - unsupported SLI4 interface type - %d\n",
8274 if_type);
8275 break;
8276 }
3772a991
JS
8277}
8278
8279/**
da0436e9 8280 * lpfc_sli4_bar2_register_memmap - Set up SLI4 BAR2 register memory map.
3772a991 8281 * @phba: pointer to lpfc hba data structure.
da0436e9 8282 * @vf: virtual function number
3772a991 8283 *
da0436e9
JS
8284 * This routine is invoked to set up SLI4 BAR2 doorbell register memory map
8285 * based on the given viftual function number, @vf.
8286 *
8287 * Return 0 if successful, otherwise -ENODEV.
3772a991 8288 **/
da0436e9
JS
8289static int
8290lpfc_sli4_bar2_register_memmap(struct lpfc_hba *phba, uint32_t vf)
3772a991 8291{
da0436e9
JS
8292 if (vf > LPFC_VIR_FUNC_MAX)
8293 return -ENODEV;
3772a991 8294
da0436e9 8295 phba->sli4_hba.RQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
962bc51b
JS
8296 vf * LPFC_VFR_PAGE_SIZE +
8297 LPFC_ULP0_RQ_DOORBELL);
da0436e9 8298 phba->sli4_hba.WQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
962bc51b
JS
8299 vf * LPFC_VFR_PAGE_SIZE +
8300 LPFC_ULP0_WQ_DOORBELL);
9dd35425
JS
8301 phba->sli4_hba.CQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8302 vf * LPFC_VFR_PAGE_SIZE +
8303 LPFC_EQCQ_DOORBELL);
8304 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.CQDBregaddr;
da0436e9
JS
8305 phba->sli4_hba.MQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8306 vf * LPFC_VFR_PAGE_SIZE + LPFC_MQ_DOORBELL);
8307 phba->sli4_hba.BMBXregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8308 vf * LPFC_VFR_PAGE_SIZE + LPFC_BMBX);
8309 return 0;
3772a991
JS
8310}
8311
8312/**
da0436e9 8313 * lpfc_create_bootstrap_mbox - Create the bootstrap mailbox
3772a991
JS
8314 * @phba: pointer to lpfc hba data structure.
8315 *
da0436e9
JS
8316 * This routine is invoked to create the bootstrap mailbox
8317 * region consistent with the SLI-4 interface spec. This
8318 * routine allocates all memory necessary to communicate
8319 * mailbox commands to the port and sets up all alignment
8320 * needs. No locks are expected to be held when calling
8321 * this routine.
3772a991
JS
8322 *
8323 * Return codes
af901ca1 8324 * 0 - successful
d439d286 8325 * -ENOMEM - could not allocated memory.
da0436e9 8326 **/
3772a991 8327static int
da0436e9 8328lpfc_create_bootstrap_mbox(struct lpfc_hba *phba)
3772a991 8329{
da0436e9
JS
8330 uint32_t bmbx_size;
8331 struct lpfc_dmabuf *dmabuf;
8332 struct dma_address *dma_address;
8333 uint32_t pa_addr;
8334 uint64_t phys_addr;
8335
8336 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
8337 if (!dmabuf)
8338 return -ENOMEM;
3772a991 8339
da0436e9
JS
8340 /*
8341 * The bootstrap mailbox region is comprised of 2 parts
8342 * plus an alignment restriction of 16 bytes.
8343 */
8344 bmbx_size = sizeof(struct lpfc_bmbx_create) + (LPFC_ALIGN_16_BYTE - 1);
750afb08
LC
8345 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev, bmbx_size,
8346 &dmabuf->phys, GFP_KERNEL);
da0436e9
JS
8347 if (!dmabuf->virt) {
8348 kfree(dmabuf);
8349 return -ENOMEM;
3772a991
JS
8350 }
8351
da0436e9
JS
8352 /*
8353 * Initialize the bootstrap mailbox pointers now so that the register
8354 * operations are simple later. The mailbox dma address is required
8355 * to be 16-byte aligned. Also align the virtual memory as each
8356 * maibox is copied into the bmbx mailbox region before issuing the
8357 * command to the port.
8358 */
8359 phba->sli4_hba.bmbx.dmabuf = dmabuf;
8360 phba->sli4_hba.bmbx.bmbx_size = bmbx_size;
8361
8362 phba->sli4_hba.bmbx.avirt = PTR_ALIGN(dmabuf->virt,
8363 LPFC_ALIGN_16_BYTE);
8364 phba->sli4_hba.bmbx.aphys = ALIGN(dmabuf->phys,
8365 LPFC_ALIGN_16_BYTE);
8366
8367 /*
8368 * Set the high and low physical addresses now. The SLI4 alignment
8369 * requirement is 16 bytes and the mailbox is posted to the port
8370 * as two 30-bit addresses. The other data is a bit marking whether
8371 * the 30-bit address is the high or low address.
8372 * Upcast bmbx aphys to 64bits so shift instruction compiles
8373 * clean on 32 bit machines.
8374 */
8375 dma_address = &phba->sli4_hba.bmbx.dma_address;
8376 phys_addr = (uint64_t)phba->sli4_hba.bmbx.aphys;
8377 pa_addr = (uint32_t) ((phys_addr >> 34) & 0x3fffffff);
8378 dma_address->addr_hi = (uint32_t) ((pa_addr << 2) |
8379 LPFC_BMBX_BIT1_ADDR_HI);
8380
8381 pa_addr = (uint32_t) ((phba->sli4_hba.bmbx.aphys >> 4) & 0x3fffffff);
8382 dma_address->addr_lo = (uint32_t) ((pa_addr << 2) |
8383 LPFC_BMBX_BIT1_ADDR_LO);
8384 return 0;
3772a991
JS
8385}
8386
8387/**
da0436e9 8388 * lpfc_destroy_bootstrap_mbox - Destroy all bootstrap mailbox resources
3772a991
JS
8389 * @phba: pointer to lpfc hba data structure.
8390 *
da0436e9
JS
8391 * This routine is invoked to teardown the bootstrap mailbox
8392 * region and release all host resources. This routine requires
8393 * the caller to ensure all mailbox commands recovered, no
8394 * additional mailbox comands are sent, and interrupts are disabled
8395 * before calling this routine.
8396 *
8397 **/
3772a991 8398static void
da0436e9 8399lpfc_destroy_bootstrap_mbox(struct lpfc_hba *phba)
3772a991 8400{
da0436e9
JS
8401 dma_free_coherent(&phba->pcidev->dev,
8402 phba->sli4_hba.bmbx.bmbx_size,
8403 phba->sli4_hba.bmbx.dmabuf->virt,
8404 phba->sli4_hba.bmbx.dmabuf->phys);
8405
8406 kfree(phba->sli4_hba.bmbx.dmabuf);
8407 memset(&phba->sli4_hba.bmbx, 0, sizeof(struct lpfc_bmbx));
3772a991
JS
8408}
8409
83c6cb1a
JS
8410static const char * const lpfc_topo_to_str[] = {
8411 "Loop then P2P",
8412 "Loopback",
8413 "P2P Only",
8414 "Unsupported",
8415 "Loop Only",
8416 "Unsupported",
8417 "P2P then Loop",
8418};
8419
fe614acd
LJ
8420#define LINK_FLAGS_DEF 0x0
8421#define LINK_FLAGS_P2P 0x1
8422#define LINK_FLAGS_LOOP 0x2
83c6cb1a
JS
8423/**
8424 * lpfc_map_topology - Map the topology read from READ_CONFIG
8425 * @phba: pointer to lpfc hba data structure.
fe614acd 8426 * @rd_config: pointer to read config data
83c6cb1a
JS
8427 *
8428 * This routine is invoked to map the topology values as read
8429 * from the read config mailbox command. If the persistent
8430 * topology feature is supported, the firmware will provide the
8431 * saved topology information to be used in INIT_LINK
83c6cb1a 8432 **/
83c6cb1a
JS
8433static void
8434lpfc_map_topology(struct lpfc_hba *phba, struct lpfc_mbx_read_config *rd_config)
8435{
8436 u8 ptv, tf, pt;
8437
8438 ptv = bf_get(lpfc_mbx_rd_conf_ptv, rd_config);
8439 tf = bf_get(lpfc_mbx_rd_conf_tf, rd_config);
8440 pt = bf_get(lpfc_mbx_rd_conf_pt, rd_config);
8441
8442 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8443 "2027 Read Config Data : ptv:0x%x, tf:0x%x pt:0x%x",
8444 ptv, tf, pt);
8445 if (!ptv) {
8446 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
8447 "2019 FW does not support persistent topology "
8448 "Using driver parameter defined value [%s]",
8449 lpfc_topo_to_str[phba->cfg_topology]);
8450 return;
8451 }
8452 /* FW supports persistent topology - override module parameter value */
8453 phba->hba_flag |= HBA_PERSISTENT_TOPO;
8454 switch (phba->pcidev->device) {
8455 case PCI_DEVICE_ID_LANCER_G7_FC:
83c6cb1a
JS
8456 case PCI_DEVICE_ID_LANCER_G6_FC:
8457 if (!tf) {
8458 phba->cfg_topology = ((pt == LINK_FLAGS_LOOP)
8459 ? FLAGS_TOPOLOGY_MODE_LOOP
8460 : FLAGS_TOPOLOGY_MODE_PT_PT);
8461 } else {
8462 phba->hba_flag &= ~HBA_PERSISTENT_TOPO;
8463 }
8464 break;
8465 default: /* G5 */
8466 if (tf) {
8467 /* If topology failover set - pt is '0' or '1' */
8468 phba->cfg_topology = (pt ? FLAGS_TOPOLOGY_MODE_PT_LOOP :
8469 FLAGS_TOPOLOGY_MODE_LOOP_PT);
8470 } else {
8471 phba->cfg_topology = ((pt == LINK_FLAGS_P2P)
8472 ? FLAGS_TOPOLOGY_MODE_PT_PT
8473 : FLAGS_TOPOLOGY_MODE_LOOP);
8474 }
8475 break;
8476 }
8477 if (phba->hba_flag & HBA_PERSISTENT_TOPO) {
8478 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8479 "2020 Using persistent topology value [%s]",
8480 lpfc_topo_to_str[phba->cfg_topology]);
8481 } else {
8482 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
8483 "2021 Invalid topology values from FW "
8484 "Using driver parameter defined value [%s]",
8485 lpfc_topo_to_str[phba->cfg_topology]);
8486 }
8487}
8488
3772a991 8489/**
da0436e9 8490 * lpfc_sli4_read_config - Get the config parameters.
3772a991
JS
8491 * @phba: pointer to lpfc hba data structure.
8492 *
da0436e9
JS
8493 * This routine is invoked to read the configuration parameters from the HBA.
8494 * The configuration parameters are used to set the base and maximum values
8495 * for RPI's XRI's VPI's VFI's and FCFIs. These values also affect the resource
8496 * allocation for the port.
3772a991
JS
8497 *
8498 * Return codes
af901ca1 8499 * 0 - successful
25985edc 8500 * -ENOMEM - No available memory
d439d286 8501 * -EIO - The mailbox failed to complete successfully.
3772a991 8502 **/
ff78d8f9 8503int
da0436e9 8504lpfc_sli4_read_config(struct lpfc_hba *phba)
3772a991 8505{
da0436e9
JS
8506 LPFC_MBOXQ_t *pmb;
8507 struct lpfc_mbx_read_config *rd_config;
912e3acd
JS
8508 union lpfc_sli4_cfg_shdr *shdr;
8509 uint32_t shdr_status, shdr_add_status;
8510 struct lpfc_mbx_get_func_cfg *get_func_cfg;
8511 struct lpfc_rsrc_desc_fcfcoe *desc;
8aa134a8 8512 char *pdesc_0;
c691816e 8513 uint16_t forced_link_speed;
6a828b0f 8514 uint32_t if_type, qmin;
8aa134a8 8515 int length, i, rc = 0, rc2;
3772a991 8516
da0436e9
JS
8517 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
8518 if (!pmb) {
372c187b 8519 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
8520 "2011 Unable to allocate memory for issuing "
8521 "SLI_CONFIG_SPECIAL mailbox command\n");
8522 return -ENOMEM;
3772a991
JS
8523 }
8524
da0436e9 8525 lpfc_read_config(phba, pmb);
3772a991 8526
da0436e9
JS
8527 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
8528 if (rc != MBX_SUCCESS) {
372c187b
DK
8529 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
8530 "2012 Mailbox failed , mbxCmd x%x "
8531 "READ_CONFIG, mbxStatus x%x\n",
8532 bf_get(lpfc_mqe_command, &pmb->u.mqe),
8533 bf_get(lpfc_mqe_status, &pmb->u.mqe));
da0436e9
JS
8534 rc = -EIO;
8535 } else {
8536 rd_config = &pmb->u.mqe.un.rd_config;
ff78d8f9
JS
8537 if (bf_get(lpfc_mbx_rd_conf_lnk_ldv, rd_config)) {
8538 phba->sli4_hba.lnk_info.lnk_dv = LPFC_LNK_DAT_VAL;
8539 phba->sli4_hba.lnk_info.lnk_tp =
8540 bf_get(lpfc_mbx_rd_conf_lnk_type, rd_config);
8541 phba->sli4_hba.lnk_info.lnk_no =
8542 bf_get(lpfc_mbx_rd_conf_lnk_numb, rd_config);
8543 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8544 "3081 lnk_type:%d, lnk_numb:%d\n",
8545 phba->sli4_hba.lnk_info.lnk_tp,
8546 phba->sli4_hba.lnk_info.lnk_no);
8547 } else
8548 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
8549 "3082 Mailbox (x%x) returned ldv:x0\n",
8550 bf_get(lpfc_mqe_command, &pmb->u.mqe));
44fd7fe3
JS
8551 if (bf_get(lpfc_mbx_rd_conf_bbscn_def, rd_config)) {
8552 phba->bbcredit_support = 1;
8553 phba->sli4_hba.bbscn_params.word0 = rd_config->word8;
8554 }
8555
1dc5ec24
JS
8556 phba->sli4_hba.conf_trunk =
8557 bf_get(lpfc_mbx_rd_conf_trunk, rd_config);
6d368e53
JS
8558 phba->sli4_hba.extents_in_use =
8559 bf_get(lpfc_mbx_rd_conf_extnts_inuse, rd_config);
da0436e9
JS
8560 phba->sli4_hba.max_cfg_param.max_xri =
8561 bf_get(lpfc_mbx_rd_conf_xri_count, rd_config);
31f06d2e
JS
8562 /* Reduce resource usage in kdump environment */
8563 if (is_kdump_kernel() &&
8564 phba->sli4_hba.max_cfg_param.max_xri > 512)
8565 phba->sli4_hba.max_cfg_param.max_xri = 512;
da0436e9
JS
8566 phba->sli4_hba.max_cfg_param.xri_base =
8567 bf_get(lpfc_mbx_rd_conf_xri_base, rd_config);
8568 phba->sli4_hba.max_cfg_param.max_vpi =
8569 bf_get(lpfc_mbx_rd_conf_vpi_count, rd_config);
8b47ae69
JS
8570 /* Limit the max we support */
8571 if (phba->sli4_hba.max_cfg_param.max_vpi > LPFC_MAX_VPORTS)
8572 phba->sli4_hba.max_cfg_param.max_vpi = LPFC_MAX_VPORTS;
da0436e9
JS
8573 phba->sli4_hba.max_cfg_param.vpi_base =
8574 bf_get(lpfc_mbx_rd_conf_vpi_base, rd_config);
8575 phba->sli4_hba.max_cfg_param.max_rpi =
8576 bf_get(lpfc_mbx_rd_conf_rpi_count, rd_config);
8577 phba->sli4_hba.max_cfg_param.rpi_base =
8578 bf_get(lpfc_mbx_rd_conf_rpi_base, rd_config);
8579 phba->sli4_hba.max_cfg_param.max_vfi =
8580 bf_get(lpfc_mbx_rd_conf_vfi_count, rd_config);
8581 phba->sli4_hba.max_cfg_param.vfi_base =
8582 bf_get(lpfc_mbx_rd_conf_vfi_base, rd_config);
8583 phba->sli4_hba.max_cfg_param.max_fcfi =
8584 bf_get(lpfc_mbx_rd_conf_fcfi_count, rd_config);
da0436e9
JS
8585 phba->sli4_hba.max_cfg_param.max_eq =
8586 bf_get(lpfc_mbx_rd_conf_eq_count, rd_config);
8587 phba->sli4_hba.max_cfg_param.max_rq =
8588 bf_get(lpfc_mbx_rd_conf_rq_count, rd_config);
8589 phba->sli4_hba.max_cfg_param.max_wq =
8590 bf_get(lpfc_mbx_rd_conf_wq_count, rd_config);
8591 phba->sli4_hba.max_cfg_param.max_cq =
8592 bf_get(lpfc_mbx_rd_conf_cq_count, rd_config);
8593 phba->lmt = bf_get(lpfc_mbx_rd_conf_lmt, rd_config);
8594 phba->sli4_hba.next_xri = phba->sli4_hba.max_cfg_param.xri_base;
8595 phba->vpi_base = phba->sli4_hba.max_cfg_param.vpi_base;
8596 phba->vfi_base = phba->sli4_hba.max_cfg_param.vfi_base;
5ffc266e
JS
8597 phba->max_vpi = (phba->sli4_hba.max_cfg_param.max_vpi > 0) ?
8598 (phba->sli4_hba.max_cfg_param.max_vpi - 1) : 0;
da0436e9 8599 phba->max_vports = phba->max_vpi;
83c6cb1a 8600 lpfc_map_topology(phba, rd_config);
da0436e9 8601 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
6d368e53
JS
8602 "2003 cfg params Extents? %d "
8603 "XRI(B:%d M:%d), "
da0436e9
JS
8604 "VPI(B:%d M:%d) "
8605 "VFI(B:%d M:%d) "
8606 "RPI(B:%d M:%d) "
a1e4d3d8 8607 "FCFI:%d EQ:%d CQ:%d WQ:%d RQ:%d lmt:x%x\n",
6d368e53 8608 phba->sli4_hba.extents_in_use,
da0436e9
JS
8609 phba->sli4_hba.max_cfg_param.xri_base,
8610 phba->sli4_hba.max_cfg_param.max_xri,
8611 phba->sli4_hba.max_cfg_param.vpi_base,
8612 phba->sli4_hba.max_cfg_param.max_vpi,
8613 phba->sli4_hba.max_cfg_param.vfi_base,
8614 phba->sli4_hba.max_cfg_param.max_vfi,
8615 phba->sli4_hba.max_cfg_param.rpi_base,
8616 phba->sli4_hba.max_cfg_param.max_rpi,
2ea259ee
JS
8617 phba->sli4_hba.max_cfg_param.max_fcfi,
8618 phba->sli4_hba.max_cfg_param.max_eq,
8619 phba->sli4_hba.max_cfg_param.max_cq,
8620 phba->sli4_hba.max_cfg_param.max_wq,
a1e4d3d8
DK
8621 phba->sli4_hba.max_cfg_param.max_rq,
8622 phba->lmt);
2ea259ee 8623
d38f33b3 8624 /*
6a828b0f
JS
8625 * Calculate queue resources based on how
8626 * many WQ/CQ/EQs are available.
d38f33b3 8627 */
6a828b0f
JS
8628 qmin = phba->sli4_hba.max_cfg_param.max_wq;
8629 if (phba->sli4_hba.max_cfg_param.max_cq < qmin)
8630 qmin = phba->sli4_hba.max_cfg_param.max_cq;
8631 if (phba->sli4_hba.max_cfg_param.max_eq < qmin)
8632 qmin = phba->sli4_hba.max_cfg_param.max_eq;
8633 /*
8634 * Whats left after this can go toward NVME / FCP.
8635 * The minus 4 accounts for ELS, NVME LS, MBOX
8636 * plus one extra. When configured for
8637 * NVMET, FCP io channel WQs are not created.
8638 */
8639 qmin -= 4;
d38f33b3 8640
6a828b0f
JS
8641 /* Check to see if there is enough for NVME */
8642 if ((phba->cfg_irq_chann > qmin) ||
8643 (phba->cfg_hdw_queue > qmin)) {
372c187b 8644 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
9e3e365a
DK
8645 "2005 Reducing Queues - "
8646 "FW resource limitation: "
6a828b0f
JS
8647 "WQ %d CQ %d EQ %d: min %d: "
8648 "IRQ %d HDWQ %d\n",
d38f33b3
JS
8649 phba->sli4_hba.max_cfg_param.max_wq,
8650 phba->sli4_hba.max_cfg_param.max_cq,
6a828b0f
JS
8651 phba->sli4_hba.max_cfg_param.max_eq,
8652 qmin, phba->cfg_irq_chann,
cdb42bec 8653 phba->cfg_hdw_queue);
d38f33b3 8654
6a828b0f
JS
8655 if (phba->cfg_irq_chann > qmin)
8656 phba->cfg_irq_chann = qmin;
8657 if (phba->cfg_hdw_queue > qmin)
8658 phba->cfg_hdw_queue = qmin;
d38f33b3 8659 }
3772a991 8660 }
912e3acd
JS
8661
8662 if (rc)
8663 goto read_cfg_out;
da0436e9 8664
c691816e
JS
8665 /* Update link speed if forced link speed is supported */
8666 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
27d6ac0a 8667 if (if_type >= LPFC_SLI_INTF_IF_TYPE_2) {
c691816e
JS
8668 forced_link_speed =
8669 bf_get(lpfc_mbx_rd_conf_link_speed, rd_config);
8670 if (forced_link_speed) {
8671 phba->hba_flag |= HBA_FORCED_LINK_SPEED;
8672
8673 switch (forced_link_speed) {
8674 case LINK_SPEED_1G:
8675 phba->cfg_link_speed =
8676 LPFC_USER_LINK_SPEED_1G;
8677 break;
8678 case LINK_SPEED_2G:
8679 phba->cfg_link_speed =
8680 LPFC_USER_LINK_SPEED_2G;
8681 break;
8682 case LINK_SPEED_4G:
8683 phba->cfg_link_speed =
8684 LPFC_USER_LINK_SPEED_4G;
8685 break;
8686 case LINK_SPEED_8G:
8687 phba->cfg_link_speed =
8688 LPFC_USER_LINK_SPEED_8G;
8689 break;
8690 case LINK_SPEED_10G:
8691 phba->cfg_link_speed =
8692 LPFC_USER_LINK_SPEED_10G;
8693 break;
8694 case LINK_SPEED_16G:
8695 phba->cfg_link_speed =
8696 LPFC_USER_LINK_SPEED_16G;
8697 break;
8698 case LINK_SPEED_32G:
8699 phba->cfg_link_speed =
8700 LPFC_USER_LINK_SPEED_32G;
8701 break;
fbd8a6ba
JS
8702 case LINK_SPEED_64G:
8703 phba->cfg_link_speed =
8704 LPFC_USER_LINK_SPEED_64G;
8705 break;
c691816e
JS
8706 case 0xffff:
8707 phba->cfg_link_speed =
8708 LPFC_USER_LINK_SPEED_AUTO;
8709 break;
8710 default:
372c187b
DK
8711 lpfc_printf_log(phba, KERN_ERR,
8712 LOG_TRACE_EVENT,
c691816e
JS
8713 "0047 Unrecognized link "
8714 "speed : %d\n",
8715 forced_link_speed);
8716 phba->cfg_link_speed =
8717 LPFC_USER_LINK_SPEED_AUTO;
8718 }
8719 }
8720 }
8721
da0436e9 8722 /* Reset the DFT_HBA_Q_DEPTH to the max xri */
572709e2
JS
8723 length = phba->sli4_hba.max_cfg_param.max_xri -
8724 lpfc_sli4_get_els_iocb_cnt(phba);
8725 if (phba->cfg_hba_queue_depth > length) {
8726 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
8727 "3361 HBA queue depth changed from %d to %d\n",
8728 phba->cfg_hba_queue_depth, length);
8729 phba->cfg_hba_queue_depth = length;
8730 }
912e3acd 8731
27d6ac0a 8732 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) <
912e3acd
JS
8733 LPFC_SLI_INTF_IF_TYPE_2)
8734 goto read_cfg_out;
8735
8736 /* get the pf# and vf# for SLI4 if_type 2 port */
8737 length = (sizeof(struct lpfc_mbx_get_func_cfg) -
8738 sizeof(struct lpfc_sli4_cfg_mhdr));
8739 lpfc_sli4_config(phba, pmb, LPFC_MBOX_SUBSYSTEM_COMMON,
8740 LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG,
8741 length, LPFC_SLI4_MBX_EMBED);
8742
8aa134a8 8743 rc2 = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
912e3acd
JS
8744 shdr = (union lpfc_sli4_cfg_shdr *)
8745 &pmb->u.mqe.un.sli4_config.header.cfg_shdr;
8746 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
8747 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
8aa134a8 8748 if (rc2 || shdr_status || shdr_add_status) {
372c187b 8749 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
912e3acd
JS
8750 "3026 Mailbox failed , mbxCmd x%x "
8751 "GET_FUNCTION_CONFIG, mbxStatus x%x\n",
8752 bf_get(lpfc_mqe_command, &pmb->u.mqe),
8753 bf_get(lpfc_mqe_status, &pmb->u.mqe));
912e3acd
JS
8754 goto read_cfg_out;
8755 }
8756
8757 /* search for fc_fcoe resrouce descriptor */
8758 get_func_cfg = &pmb->u.mqe.un.get_func_cfg;
912e3acd 8759
8aa134a8
JS
8760 pdesc_0 = (char *)&get_func_cfg->func_cfg.desc[0];
8761 desc = (struct lpfc_rsrc_desc_fcfcoe *)pdesc_0;
8762 length = bf_get(lpfc_rsrc_desc_fcfcoe_length, desc);
8763 if (length == LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD)
8764 length = LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH;
8765 else if (length != LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH)
8766 goto read_cfg_out;
8767
912e3acd 8768 for (i = 0; i < LPFC_RSRC_DESC_MAX_NUM; i++) {
8aa134a8 8769 desc = (struct lpfc_rsrc_desc_fcfcoe *)(pdesc_0 + length * i);
912e3acd 8770 if (LPFC_RSRC_DESC_TYPE_FCFCOE ==
8aa134a8 8771 bf_get(lpfc_rsrc_desc_fcfcoe_type, desc)) {
912e3acd
JS
8772 phba->sli4_hba.iov.pf_number =
8773 bf_get(lpfc_rsrc_desc_fcfcoe_pfnum, desc);
8774 phba->sli4_hba.iov.vf_number =
8775 bf_get(lpfc_rsrc_desc_fcfcoe_vfnum, desc);
8776 break;
8777 }
8778 }
8779
8780 if (i < LPFC_RSRC_DESC_MAX_NUM)
8781 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8782 "3027 GET_FUNCTION_CONFIG: pf_number:%d, "
8783 "vf_number:%d\n", phba->sli4_hba.iov.pf_number,
8784 phba->sli4_hba.iov.vf_number);
8aa134a8 8785 else
372c187b 8786 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
912e3acd 8787 "3028 GET_FUNCTION_CONFIG: failed to find "
c4dba187 8788 "Resource Descriptor:x%x\n",
912e3acd 8789 LPFC_RSRC_DESC_TYPE_FCFCOE);
912e3acd
JS
8790
8791read_cfg_out:
8792 mempool_free(pmb, phba->mbox_mem_pool);
da0436e9 8793 return rc;
3772a991
JS
8794}
8795
8796/**
2fcee4bf 8797 * lpfc_setup_endian_order - Write endian order to an SLI4 if_type 0 port.
3772a991
JS
8798 * @phba: pointer to lpfc hba data structure.
8799 *
2fcee4bf
JS
8800 * This routine is invoked to setup the port-side endian order when
8801 * the port if_type is 0. This routine has no function for other
8802 * if_types.
da0436e9
JS
8803 *
8804 * Return codes
af901ca1 8805 * 0 - successful
25985edc 8806 * -ENOMEM - No available memory
d439d286 8807 * -EIO - The mailbox failed to complete successfully.
3772a991 8808 **/
da0436e9
JS
8809static int
8810lpfc_setup_endian_order(struct lpfc_hba *phba)
3772a991 8811{
da0436e9 8812 LPFC_MBOXQ_t *mboxq;
2fcee4bf 8813 uint32_t if_type, rc = 0;
da0436e9
JS
8814 uint32_t endian_mb_data[2] = {HOST_ENDIAN_LOW_WORD0,
8815 HOST_ENDIAN_HIGH_WORD1};
3772a991 8816
2fcee4bf
JS
8817 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
8818 switch (if_type) {
8819 case LPFC_SLI_INTF_IF_TYPE_0:
8820 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
8821 GFP_KERNEL);
8822 if (!mboxq) {
372c187b 8823 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
8824 "0492 Unable to allocate memory for "
8825 "issuing SLI_CONFIG_SPECIAL mailbox "
8826 "command\n");
8827 return -ENOMEM;
8828 }
3772a991 8829
2fcee4bf
JS
8830 /*
8831 * The SLI4_CONFIG_SPECIAL mailbox command requires the first
8832 * two words to contain special data values and no other data.
8833 */
8834 memset(mboxq, 0, sizeof(LPFC_MBOXQ_t));
8835 memcpy(&mboxq->u.mqe, &endian_mb_data, sizeof(endian_mb_data));
8836 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
8837 if (rc != MBX_SUCCESS) {
372c187b 8838 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
8839 "0493 SLI_CONFIG_SPECIAL mailbox "
8840 "failed with status x%x\n",
8841 rc);
8842 rc = -EIO;
8843 }
8844 mempool_free(mboxq, phba->mbox_mem_pool);
8845 break;
27d6ac0a 8846 case LPFC_SLI_INTF_IF_TYPE_6:
2fcee4bf
JS
8847 case LPFC_SLI_INTF_IF_TYPE_2:
8848 case LPFC_SLI_INTF_IF_TYPE_1:
8849 default:
8850 break;
da0436e9 8851 }
da0436e9 8852 return rc;
3772a991
JS
8853}
8854
8855/**
895427bd 8856 * lpfc_sli4_queue_verify - Verify and update EQ counts
3772a991
JS
8857 * @phba: pointer to lpfc hba data structure.
8858 *
895427bd
JS
8859 * This routine is invoked to check the user settable queue counts for EQs.
8860 * After this routine is called the counts will be set to valid values that
5350d872
JS
8861 * adhere to the constraints of the system's interrupt vectors and the port's
8862 * queue resources.
da0436e9
JS
8863 *
8864 * Return codes
af901ca1 8865 * 0 - successful
25985edc 8866 * -ENOMEM - No available memory
3772a991 8867 **/
da0436e9 8868static int
5350d872 8869lpfc_sli4_queue_verify(struct lpfc_hba *phba)
3772a991 8870{
da0436e9 8871 /*
67d12733 8872 * Sanity check for configured queue parameters against the run-time
da0436e9
JS
8873 * device parameters
8874 */
3772a991 8875
bcb24f65 8876 if (phba->nvmet_support) {
97a9ed3b
JS
8877 if (phba->cfg_hdw_queue < phba->cfg_nvmet_mrq)
8878 phba->cfg_nvmet_mrq = phba->cfg_hdw_queue;
982ab128
JS
8879 if (phba->cfg_nvmet_mrq > LPFC_NVMET_MRQ_MAX)
8880 phba->cfg_nvmet_mrq = LPFC_NVMET_MRQ_MAX;
bcb24f65 8881 }
895427bd
JS
8882
8883 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6a828b0f
JS
8884 "2574 IO channels: hdwQ %d IRQ %d MRQ: %d\n",
8885 phba->cfg_hdw_queue, phba->cfg_irq_chann,
8886 phba->cfg_nvmet_mrq);
3772a991 8887
da0436e9
JS
8888 /* Get EQ depth from module parameter, fake the default for now */
8889 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
8890 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
3772a991 8891
5350d872
JS
8892 /* Get CQ depth from module parameter, fake the default for now */
8893 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
8894 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
895427bd
JS
8895 return 0;
8896}
8897
8898static int
c00f62e6 8899lpfc_alloc_io_wq_cq(struct lpfc_hba *phba, int idx)
895427bd
JS
8900{
8901 struct lpfc_queue *qdesc;
c00f62e6 8902 u32 wqesize;
c1a21ebc 8903 int cpu;
895427bd 8904
c00f62e6
JS
8905 cpu = lpfc_find_cpu_handle(phba, idx, LPFC_FIND_BY_HDWQ);
8906 /* Create Fast Path IO CQs */
c176ffa0 8907 if (phba->enab_exp_wqcq_pages)
a51e41b6
JS
8908 /* Increase the CQ size when WQEs contain an embedded cdb */
8909 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
8910 phba->sli4_hba.cq_esize,
c1a21ebc 8911 LPFC_CQE_EXP_COUNT, cpu);
a51e41b6
JS
8912
8913 else
8914 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8915 phba->sli4_hba.cq_esize,
c1a21ebc 8916 phba->sli4_hba.cq_ecount, cpu);
895427bd 8917 if (!qdesc) {
372c187b
DK
8918 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
8919 "0499 Failed allocate fast-path IO CQ (%d)\n",
8920 idx);
895427bd
JS
8921 return 1;
8922 }
7365f6fd 8923 qdesc->qe_valid = 1;
c00f62e6 8924 qdesc->hdwq = idx;
c1a21ebc 8925 qdesc->chann = cpu;
c00f62e6 8926 phba->sli4_hba.hdwq[idx].io_cq = qdesc;
895427bd 8927
c00f62e6 8928 /* Create Fast Path IO WQs */
c176ffa0 8929 if (phba->enab_exp_wqcq_pages) {
a51e41b6 8930 /* Increase the WQ size when WQEs contain an embedded cdb */
c176ffa0
JS
8931 wqesize = (phba->fcp_embed_io) ?
8932 LPFC_WQE128_SIZE : phba->sli4_hba.wq_esize;
a51e41b6 8933 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
c176ffa0 8934 wqesize,
c1a21ebc 8935 LPFC_WQE_EXP_COUNT, cpu);
c176ffa0 8936 } else
a51e41b6
JS
8937 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8938 phba->sli4_hba.wq_esize,
c1a21ebc 8939 phba->sli4_hba.wq_ecount, cpu);
c176ffa0 8940
895427bd 8941 if (!qdesc) {
372c187b 8942 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
c00f62e6
JS
8943 "0503 Failed allocate fast-path IO WQ (%d)\n",
8944 idx);
895427bd
JS
8945 return 1;
8946 }
c00f62e6
JS
8947 qdesc->hdwq = idx;
8948 qdesc->chann = cpu;
8949 phba->sli4_hba.hdwq[idx].io_wq = qdesc;
895427bd 8950 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
5350d872 8951 return 0;
5350d872
JS
8952}
8953
8954/**
8955 * lpfc_sli4_queue_create - Create all the SLI4 queues
8956 * @phba: pointer to lpfc hba data structure.
8957 *
8958 * This routine is invoked to allocate all the SLI4 queues for the FCoE HBA
8959 * operation. For each SLI4 queue type, the parameters such as queue entry
8960 * count (queue depth) shall be taken from the module parameter. For now,
8961 * we just use some constant number as place holder.
8962 *
8963 * Return codes
4907cb7b 8964 * 0 - successful
5350d872
JS
8965 * -ENOMEM - No availble memory
8966 * -EIO - The mailbox failed to complete successfully.
8967 **/
8968int
8969lpfc_sli4_queue_create(struct lpfc_hba *phba)
8970{
8971 struct lpfc_queue *qdesc;
657add4e 8972 int idx, cpu, eqcpu;
5e5b511d 8973 struct lpfc_sli4_hdw_queue *qp;
657add4e
JS
8974 struct lpfc_vector_map_info *cpup;
8975 struct lpfc_vector_map_info *eqcpup;
32517fc0 8976 struct lpfc_eq_intr_info *eqi;
5350d872
JS
8977
8978 /*
67d12733 8979 * Create HBA Record arrays.
895427bd 8980 * Both NVME and FCP will share that same vectors / EQs
5350d872 8981 */
67d12733
JS
8982 phba->sli4_hba.mq_esize = LPFC_MQE_SIZE;
8983 phba->sli4_hba.mq_ecount = LPFC_MQE_DEF_COUNT;
8984 phba->sli4_hba.wq_esize = LPFC_WQE_SIZE;
8985 phba->sli4_hba.wq_ecount = LPFC_WQE_DEF_COUNT;
8986 phba->sli4_hba.rq_esize = LPFC_RQE_SIZE;
8987 phba->sli4_hba.rq_ecount = LPFC_RQE_DEF_COUNT;
895427bd
JS
8988 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
8989 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
8990 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
8991 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
67d12733 8992
cdb42bec 8993 if (!phba->sli4_hba.hdwq) {
5e5b511d
JS
8994 phba->sli4_hba.hdwq = kcalloc(
8995 phba->cfg_hdw_queue, sizeof(struct lpfc_sli4_hdw_queue),
8996 GFP_KERNEL);
8997 if (!phba->sli4_hba.hdwq) {
372c187b 8998 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5e5b511d
JS
8999 "6427 Failed allocate memory for "
9000 "fast-path Hardware Queue array\n");
895427bd
JS
9001 goto out_error;
9002 }
5e5b511d
JS
9003 /* Prepare hardware queues to take IO buffers */
9004 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9005 qp = &phba->sli4_hba.hdwq[idx];
9006 spin_lock_init(&qp->io_buf_list_get_lock);
9007 spin_lock_init(&qp->io_buf_list_put_lock);
9008 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_get);
9009 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_put);
9010 qp->get_io_bufs = 0;
9011 qp->put_io_bufs = 0;
9012 qp->total_io_bufs = 0;
c00f62e6
JS
9013 spin_lock_init(&qp->abts_io_buf_list_lock);
9014 INIT_LIST_HEAD(&qp->lpfc_abts_io_buf_list);
5e5b511d 9015 qp->abts_scsi_io_bufs = 0;
5e5b511d 9016 qp->abts_nvme_io_bufs = 0;
d79c9e9d
JS
9017 INIT_LIST_HEAD(&qp->sgl_list);
9018 INIT_LIST_HEAD(&qp->cmd_rsp_buf_list);
9019 spin_lock_init(&qp->hdwq_lock);
895427bd 9020 }
67d12733
JS
9021 }
9022
cdb42bec 9023 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
2d7dbc4c
JS
9024 if (phba->nvmet_support) {
9025 phba->sli4_hba.nvmet_cqset = kcalloc(
9026 phba->cfg_nvmet_mrq,
9027 sizeof(struct lpfc_queue *),
9028 GFP_KERNEL);
9029 if (!phba->sli4_hba.nvmet_cqset) {
372c187b 9030 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9031 "3121 Fail allocate memory for "
9032 "fast-path CQ set array\n");
9033 goto out_error;
9034 }
9035 phba->sli4_hba.nvmet_mrq_hdr = kcalloc(
9036 phba->cfg_nvmet_mrq,
9037 sizeof(struct lpfc_queue *),
9038 GFP_KERNEL);
9039 if (!phba->sli4_hba.nvmet_mrq_hdr) {
372c187b 9040 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9041 "3122 Fail allocate memory for "
9042 "fast-path RQ set hdr array\n");
9043 goto out_error;
9044 }
9045 phba->sli4_hba.nvmet_mrq_data = kcalloc(
9046 phba->cfg_nvmet_mrq,
9047 sizeof(struct lpfc_queue *),
9048 GFP_KERNEL);
9049 if (!phba->sli4_hba.nvmet_mrq_data) {
372c187b 9050 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9051 "3124 Fail allocate memory for "
9052 "fast-path RQ set data array\n");
9053 goto out_error;
9054 }
9055 }
da0436e9 9056 }
67d12733 9057
895427bd 9058 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
67d12733 9059
895427bd 9060 /* Create HBA Event Queues (EQs) */
657add4e
JS
9061 for_each_present_cpu(cpu) {
9062 /* We only want to create 1 EQ per vector, even though
9063 * multiple CPUs might be using that vector. so only
9064 * selects the CPUs that are LPFC_CPU_FIRST_IRQ.
6a828b0f 9065 */
657add4e
JS
9066 cpup = &phba->sli4_hba.cpu_map[cpu];
9067 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
6a828b0f 9068 continue;
657add4e
JS
9069
9070 /* Get a ptr to the Hardware Queue associated with this CPU */
9071 qp = &phba->sli4_hba.hdwq[cpup->hdwq];
9072
9073 /* Allocate an EQ */
81b96eda
JS
9074 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9075 phba->sli4_hba.eq_esize,
c1a21ebc 9076 phba->sli4_hba.eq_ecount, cpu);
da0436e9 9077 if (!qdesc) {
372c187b 9078 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
657add4e
JS
9079 "0497 Failed allocate EQ (%d)\n",
9080 cpup->hdwq);
67d12733 9081 goto out_error;
da0436e9 9082 }
7365f6fd 9083 qdesc->qe_valid = 1;
657add4e 9084 qdesc->hdwq = cpup->hdwq;
3ad348d9 9085 qdesc->chann = cpu; /* First CPU this EQ is affinitized to */
32517fc0 9086 qdesc->last_cpu = qdesc->chann;
657add4e
JS
9087
9088 /* Save the allocated EQ in the Hardware Queue */
9089 qp->hba_eq = qdesc;
9090
32517fc0
JS
9091 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, qdesc->last_cpu);
9092 list_add(&qdesc->cpu_list, &eqi->list);
895427bd 9093 }
67d12733 9094
657add4e
JS
9095 /* Now we need to populate the other Hardware Queues, that share
9096 * an IRQ vector, with the associated EQ ptr.
9097 */
9098 for_each_present_cpu(cpu) {
9099 cpup = &phba->sli4_hba.cpu_map[cpu];
9100
9101 /* Check for EQ already allocated in previous loop */
9102 if (cpup->flag & LPFC_CPU_FIRST_IRQ)
9103 continue;
9104
9105 /* Check for multiple CPUs per hdwq */
9106 qp = &phba->sli4_hba.hdwq[cpup->hdwq];
9107 if (qp->hba_eq)
9108 continue;
9109
9110 /* We need to share an EQ for this hdwq */
9111 eqcpu = lpfc_find_cpu_handle(phba, cpup->eq, LPFC_FIND_BY_EQ);
9112 eqcpup = &phba->sli4_hba.cpu_map[eqcpu];
9113 qp->hba_eq = phba->sli4_hba.hdwq[eqcpup->hdwq].hba_eq;
9114 }
67d12733 9115
c00f62e6 9116 /* Allocate IO Path SLI4 CQ/WQs */
6a828b0f 9117 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
c00f62e6 9118 if (lpfc_alloc_io_wq_cq(phba, idx))
67d12733 9119 goto out_error;
6a828b0f 9120 }
da0436e9 9121
c00f62e6
JS
9122 if (phba->nvmet_support) {
9123 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
9124 cpu = lpfc_find_cpu_handle(phba, idx,
9125 LPFC_FIND_BY_HDWQ);
9126 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda
JS
9127 LPFC_DEFAULT_PAGE_SIZE,
9128 phba->sli4_hba.cq_esize,
c1a21ebc
JS
9129 phba->sli4_hba.cq_ecount,
9130 cpu);
c00f62e6 9131 if (!qdesc) {
372c187b 9132 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
cdb42bec
JS
9133 "3142 Failed allocate NVME "
9134 "CQ Set (%d)\n", idx);
c00f62e6 9135 goto out_error;
2d7dbc4c 9136 }
c00f62e6
JS
9137 qdesc->qe_valid = 1;
9138 qdesc->hdwq = idx;
9139 qdesc->chann = cpu;
9140 phba->sli4_hba.nvmet_cqset[idx] = qdesc;
2d7dbc4c
JS
9141 }
9142 }
9143
da0436e9 9144 /*
67d12733 9145 * Create Slow Path Completion Queues (CQs)
da0436e9
JS
9146 */
9147
c1a21ebc 9148 cpu = lpfc_find_cpu_handle(phba, 0, LPFC_FIND_BY_EQ);
da0436e9 9149 /* Create slow-path Mailbox Command Complete Queue */
81b96eda
JS
9150 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9151 phba->sli4_hba.cq_esize,
c1a21ebc 9152 phba->sli4_hba.cq_ecount, cpu);
da0436e9 9153 if (!qdesc) {
372c187b 9154 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9155 "0500 Failed allocate slow-path mailbox CQ\n");
67d12733 9156 goto out_error;
da0436e9 9157 }
7365f6fd 9158 qdesc->qe_valid = 1;
da0436e9
JS
9159 phba->sli4_hba.mbx_cq = qdesc;
9160
9161 /* Create slow-path ELS Complete Queue */
81b96eda
JS
9162 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9163 phba->sli4_hba.cq_esize,
c1a21ebc 9164 phba->sli4_hba.cq_ecount, cpu);
da0436e9 9165 if (!qdesc) {
372c187b 9166 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9167 "0501 Failed allocate slow-path ELS CQ\n");
67d12733 9168 goto out_error;
da0436e9 9169 }
7365f6fd 9170 qdesc->qe_valid = 1;
c00f62e6 9171 qdesc->chann = cpu;
da0436e9
JS
9172 phba->sli4_hba.els_cq = qdesc;
9173
da0436e9 9174
5350d872 9175 /*
67d12733 9176 * Create Slow Path Work Queues (WQs)
5350d872 9177 */
da0436e9
JS
9178
9179 /* Create Mailbox Command Queue */
da0436e9 9180
81b96eda
JS
9181 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9182 phba->sli4_hba.mq_esize,
c1a21ebc 9183 phba->sli4_hba.mq_ecount, cpu);
da0436e9 9184 if (!qdesc) {
372c187b 9185 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9186 "0505 Failed allocate slow-path MQ\n");
67d12733 9187 goto out_error;
da0436e9 9188 }
c00f62e6 9189 qdesc->chann = cpu;
da0436e9
JS
9190 phba->sli4_hba.mbx_wq = qdesc;
9191
9192 /*
67d12733 9193 * Create ELS Work Queues
da0436e9 9194 */
da0436e9
JS
9195
9196 /* Create slow-path ELS Work Queue */
81b96eda
JS
9197 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9198 phba->sli4_hba.wq_esize,
c1a21ebc 9199 phba->sli4_hba.wq_ecount, cpu);
da0436e9 9200 if (!qdesc) {
372c187b 9201 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9202 "0504 Failed allocate slow-path ELS WQ\n");
67d12733 9203 goto out_error;
da0436e9 9204 }
c00f62e6 9205 qdesc->chann = cpu;
da0436e9 9206 phba->sli4_hba.els_wq = qdesc;
895427bd
JS
9207 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
9208
9209 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
9210 /* Create NVME LS Complete Queue */
81b96eda
JS
9211 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9212 phba->sli4_hba.cq_esize,
c1a21ebc 9213 phba->sli4_hba.cq_ecount, cpu);
895427bd 9214 if (!qdesc) {
372c187b 9215 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9216 "6079 Failed allocate NVME LS CQ\n");
9217 goto out_error;
9218 }
c00f62e6 9219 qdesc->chann = cpu;
7365f6fd 9220 qdesc->qe_valid = 1;
895427bd
JS
9221 phba->sli4_hba.nvmels_cq = qdesc;
9222
9223 /* Create NVME LS Work Queue */
81b96eda
JS
9224 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9225 phba->sli4_hba.wq_esize,
c1a21ebc 9226 phba->sli4_hba.wq_ecount, cpu);
895427bd 9227 if (!qdesc) {
372c187b 9228 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9229 "6080 Failed allocate NVME LS WQ\n");
9230 goto out_error;
9231 }
c00f62e6 9232 qdesc->chann = cpu;
895427bd
JS
9233 phba->sli4_hba.nvmels_wq = qdesc;
9234 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
9235 }
da0436e9 9236
da0436e9
JS
9237 /*
9238 * Create Receive Queue (RQ)
9239 */
da0436e9
JS
9240
9241 /* Create Receive Queue for header */
81b96eda
JS
9242 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9243 phba->sli4_hba.rq_esize,
c1a21ebc 9244 phba->sli4_hba.rq_ecount, cpu);
da0436e9 9245 if (!qdesc) {
372c187b 9246 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9247 "0506 Failed allocate receive HRQ\n");
67d12733 9248 goto out_error;
da0436e9
JS
9249 }
9250 phba->sli4_hba.hdr_rq = qdesc;
9251
9252 /* Create Receive Queue for data */
81b96eda
JS
9253 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9254 phba->sli4_hba.rq_esize,
c1a21ebc 9255 phba->sli4_hba.rq_ecount, cpu);
da0436e9 9256 if (!qdesc) {
372c187b 9257 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9258 "0507 Failed allocate receive DRQ\n");
67d12733 9259 goto out_error;
da0436e9
JS
9260 }
9261 phba->sli4_hba.dat_rq = qdesc;
9262
cdb42bec
JS
9263 if ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) &&
9264 phba->nvmet_support) {
2d7dbc4c 9265 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
c1a21ebc
JS
9266 cpu = lpfc_find_cpu_handle(phba, idx,
9267 LPFC_FIND_BY_HDWQ);
2d7dbc4c
JS
9268 /* Create NVMET Receive Queue for header */
9269 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda 9270 LPFC_DEFAULT_PAGE_SIZE,
2d7dbc4c 9271 phba->sli4_hba.rq_esize,
c1a21ebc
JS
9272 LPFC_NVMET_RQE_DEF_COUNT,
9273 cpu);
2d7dbc4c 9274 if (!qdesc) {
372c187b 9275 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9276 "3146 Failed allocate "
9277 "receive HRQ\n");
9278 goto out_error;
9279 }
5e5b511d 9280 qdesc->hdwq = idx;
2d7dbc4c
JS
9281 phba->sli4_hba.nvmet_mrq_hdr[idx] = qdesc;
9282
9283 /* Only needed for header of RQ pair */
c1a21ebc
JS
9284 qdesc->rqbp = kzalloc_node(sizeof(*qdesc->rqbp),
9285 GFP_KERNEL,
9286 cpu_to_node(cpu));
2d7dbc4c 9287 if (qdesc->rqbp == NULL) {
372c187b 9288 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9289 "6131 Failed allocate "
9290 "Header RQBP\n");
9291 goto out_error;
9292 }
9293
4b40d02b
DK
9294 /* Put list in known state in case driver load fails. */
9295 INIT_LIST_HEAD(&qdesc->rqbp->rqb_buffer_list);
9296
2d7dbc4c
JS
9297 /* Create NVMET Receive Queue for data */
9298 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda 9299 LPFC_DEFAULT_PAGE_SIZE,
2d7dbc4c 9300 phba->sli4_hba.rq_esize,
c1a21ebc
JS
9301 LPFC_NVMET_RQE_DEF_COUNT,
9302 cpu);
2d7dbc4c 9303 if (!qdesc) {
372c187b 9304 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9305 "3156 Failed allocate "
9306 "receive DRQ\n");
9307 goto out_error;
9308 }
5e5b511d 9309 qdesc->hdwq = idx;
2d7dbc4c
JS
9310 phba->sli4_hba.nvmet_mrq_data[idx] = qdesc;
9311 }
9312 }
9313
4c47efc1
JS
9314 /* Clear NVME stats */
9315 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
9316 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9317 memset(&phba->sli4_hba.hdwq[idx].nvme_cstat, 0,
9318 sizeof(phba->sli4_hba.hdwq[idx].nvme_cstat));
9319 }
9320 }
4c47efc1
JS
9321
9322 /* Clear SCSI stats */
9323 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
9324 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9325 memset(&phba->sli4_hba.hdwq[idx].scsi_cstat, 0,
9326 sizeof(phba->sli4_hba.hdwq[idx].scsi_cstat));
9327 }
9328 }
9329
da0436e9
JS
9330 return 0;
9331
da0436e9 9332out_error:
67d12733 9333 lpfc_sli4_queue_destroy(phba);
da0436e9
JS
9334 return -ENOMEM;
9335}
9336
895427bd
JS
9337static inline void
9338__lpfc_sli4_release_queue(struct lpfc_queue **qp)
9339{
9340 if (*qp != NULL) {
9341 lpfc_sli4_queue_free(*qp);
9342 *qp = NULL;
9343 }
9344}
9345
9346static inline void
9347lpfc_sli4_release_queues(struct lpfc_queue ***qs, int max)
9348{
9349 int idx;
9350
9351 if (*qs == NULL)
9352 return;
9353
9354 for (idx = 0; idx < max; idx++)
9355 __lpfc_sli4_release_queue(&(*qs)[idx]);
9356
9357 kfree(*qs);
9358 *qs = NULL;
9359}
9360
9361static inline void
6a828b0f 9362lpfc_sli4_release_hdwq(struct lpfc_hba *phba)
895427bd 9363{
6a828b0f 9364 struct lpfc_sli4_hdw_queue *hdwq;
657add4e 9365 struct lpfc_queue *eq;
cdb42bec
JS
9366 uint32_t idx;
9367
6a828b0f 9368 hdwq = phba->sli4_hba.hdwq;
6a828b0f 9369
657add4e
JS
9370 /* Loop thru all Hardware Queues */
9371 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9372 /* Free the CQ/WQ corresponding to the Hardware Queue */
c00f62e6
JS
9373 lpfc_sli4_queue_free(hdwq[idx].io_cq);
9374 lpfc_sli4_queue_free(hdwq[idx].io_wq);
821bc882 9375 hdwq[idx].hba_eq = NULL;
c00f62e6
JS
9376 hdwq[idx].io_cq = NULL;
9377 hdwq[idx].io_wq = NULL;
d79c9e9d
JS
9378 if (phba->cfg_xpsgl && !phba->nvmet_support)
9379 lpfc_free_sgl_per_hdwq(phba, &hdwq[idx]);
9380 lpfc_free_cmd_rsp_buf_per_hdwq(phba, &hdwq[idx]);
895427bd 9381 }
657add4e
JS
9382 /* Loop thru all IRQ vectors */
9383 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
9384 /* Free the EQ corresponding to the IRQ vector */
9385 eq = phba->sli4_hba.hba_eq_hdl[idx].eq;
9386 lpfc_sli4_queue_free(eq);
9387 phba->sli4_hba.hba_eq_hdl[idx].eq = NULL;
9388 }
895427bd
JS
9389}
9390
da0436e9
JS
9391/**
9392 * lpfc_sli4_queue_destroy - Destroy all the SLI4 queues
9393 * @phba: pointer to lpfc hba data structure.
9394 *
9395 * This routine is invoked to release all the SLI4 queues with the FCoE HBA
9396 * operation.
9397 *
9398 * Return codes
af901ca1 9399 * 0 - successful
25985edc 9400 * -ENOMEM - No available memory
d439d286 9401 * -EIO - The mailbox failed to complete successfully.
da0436e9 9402 **/
5350d872 9403void
da0436e9
JS
9404lpfc_sli4_queue_destroy(struct lpfc_hba *phba)
9405{
4645f7b5
JS
9406 /*
9407 * Set FREE_INIT before beginning to free the queues.
9408 * Wait until the users of queues to acknowledge to
9409 * release queues by clearing FREE_WAIT.
9410 */
9411 spin_lock_irq(&phba->hbalock);
9412 phba->sli.sli_flag |= LPFC_QUEUE_FREE_INIT;
9413 while (phba->sli.sli_flag & LPFC_QUEUE_FREE_WAIT) {
9414 spin_unlock_irq(&phba->hbalock);
9415 msleep(20);
9416 spin_lock_irq(&phba->hbalock);
9417 }
9418 spin_unlock_irq(&phba->hbalock);
9419
93a4d6f4
JS
9420 lpfc_sli4_cleanup_poll_list(phba);
9421
895427bd 9422 /* Release HBA eqs */
cdb42bec 9423 if (phba->sli4_hba.hdwq)
6a828b0f 9424 lpfc_sli4_release_hdwq(phba);
895427bd 9425
bcb24f65
JS
9426 if (phba->nvmet_support) {
9427 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_cqset,
9428 phba->cfg_nvmet_mrq);
2d7dbc4c 9429
bcb24f65
JS
9430 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_hdr,
9431 phba->cfg_nvmet_mrq);
9432 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_data,
9433 phba->cfg_nvmet_mrq);
9434 }
2d7dbc4c 9435
895427bd
JS
9436 /* Release mailbox command work queue */
9437 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_wq);
9438
9439 /* Release ELS work queue */
9440 __lpfc_sli4_release_queue(&phba->sli4_hba.els_wq);
9441
9442 /* Release ELS work queue */
9443 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_wq);
9444
9445 /* Release unsolicited receive queue */
9446 __lpfc_sli4_release_queue(&phba->sli4_hba.hdr_rq);
9447 __lpfc_sli4_release_queue(&phba->sli4_hba.dat_rq);
9448
9449 /* Release ELS complete queue */
9450 __lpfc_sli4_release_queue(&phba->sli4_hba.els_cq);
9451
9452 /* Release NVME LS complete queue */
9453 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_cq);
9454
9455 /* Release mailbox command complete queue */
9456 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_cq);
9457
9458 /* Everything on this list has been freed */
9459 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
4645f7b5
JS
9460
9461 /* Done with freeing the queues */
9462 spin_lock_irq(&phba->hbalock);
9463 phba->sli.sli_flag &= ~LPFC_QUEUE_FREE_INIT;
9464 spin_unlock_irq(&phba->hbalock);
895427bd
JS
9465}
9466
895427bd
JS
9467int
9468lpfc_free_rq_buffer(struct lpfc_hba *phba, struct lpfc_queue *rq)
9469{
9470 struct lpfc_rqb *rqbp;
9471 struct lpfc_dmabuf *h_buf;
9472 struct rqb_dmabuf *rqb_buffer;
9473
9474 rqbp = rq->rqbp;
9475 while (!list_empty(&rqbp->rqb_buffer_list)) {
9476 list_remove_head(&rqbp->rqb_buffer_list, h_buf,
9477 struct lpfc_dmabuf, list);
9478
9479 rqb_buffer = container_of(h_buf, struct rqb_dmabuf, hbuf);
9480 (rqbp->rqb_free_buffer)(phba, rqb_buffer);
9481 rqbp->buffer_count--;
67d12733 9482 }
895427bd
JS
9483 return 1;
9484}
67d12733 9485
895427bd
JS
9486static int
9487lpfc_create_wq_cq(struct lpfc_hba *phba, struct lpfc_queue *eq,
9488 struct lpfc_queue *cq, struct lpfc_queue *wq, uint16_t *cq_map,
9489 int qidx, uint32_t qtype)
9490{
9491 struct lpfc_sli_ring *pring;
9492 int rc;
9493
9494 if (!eq || !cq || !wq) {
372c187b 9495 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9496 "6085 Fast-path %s (%d) not allocated\n",
9497 ((eq) ? ((cq) ? "WQ" : "CQ") : "EQ"), qidx);
9498 return -ENOMEM;
9499 }
9500
9501 /* create the Cq first */
9502 rc = lpfc_cq_create(phba, cq, eq,
9503 (qtype == LPFC_MBOX) ? LPFC_MCQ : LPFC_WCQ, qtype);
9504 if (rc) {
372c187b
DK
9505 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
9506 "6086 Failed setup of CQ (%d), rc = 0x%x\n",
9507 qidx, (uint32_t)rc);
895427bd 9508 return rc;
67d12733
JS
9509 }
9510
895427bd 9511 if (qtype != LPFC_MBOX) {
cdb42bec 9512 /* Setup cq_map for fast lookup */
895427bd
JS
9513 if (cq_map)
9514 *cq_map = cq->queue_id;
da0436e9 9515
895427bd
JS
9516 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9517 "6087 CQ setup: cq[%d]-id=%d, parent eq[%d]-id=%d\n",
9518 qidx, cq->queue_id, qidx, eq->queue_id);
da0436e9 9519
895427bd
JS
9520 /* create the wq */
9521 rc = lpfc_wq_create(phba, wq, cq, qtype);
9522 if (rc) {
372c187b 9523 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
c835c085 9524 "4618 Fail setup fastpath WQ (%d), rc = 0x%x\n",
895427bd
JS
9525 qidx, (uint32_t)rc);
9526 /* no need to tear down cq - caller will do so */
9527 return rc;
9528 }
da0436e9 9529
895427bd
JS
9530 /* Bind this CQ/WQ to the NVME ring */
9531 pring = wq->pring;
9532 pring->sli.sli4.wqp = (void *)wq;
9533 cq->pring = pring;
da0436e9 9534
895427bd
JS
9535 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9536 "2593 WQ setup: wq[%d]-id=%d assoc=%d, cq[%d]-id=%d\n",
9537 qidx, wq->queue_id, wq->assoc_qid, qidx, cq->queue_id);
9538 } else {
9539 rc = lpfc_mq_create(phba, wq, cq, LPFC_MBOX);
9540 if (rc) {
372c187b
DK
9541 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
9542 "0539 Failed setup of slow-path MQ: "
9543 "rc = 0x%x\n", rc);
895427bd
JS
9544 /* no need to tear down cq - caller will do so */
9545 return rc;
9546 }
da0436e9 9547
895427bd
JS
9548 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9549 "2589 MBX MQ setup: wq-id=%d, parent cq-id=%d\n",
9550 phba->sli4_hba.mbx_wq->queue_id,
9551 phba->sli4_hba.mbx_cq->queue_id);
67d12733 9552 }
da0436e9 9553
895427bd 9554 return 0;
da0436e9
JS
9555}
9556
6a828b0f
JS
9557/**
9558 * lpfc_setup_cq_lookup - Setup the CQ lookup table
9559 * @phba: pointer to lpfc hba data structure.
9560 *
9561 * This routine will populate the cq_lookup table by all
9562 * available CQ queue_id's.
9563 **/
3999df75 9564static void
6a828b0f
JS
9565lpfc_setup_cq_lookup(struct lpfc_hba *phba)
9566{
9567 struct lpfc_queue *eq, *childq;
6a828b0f
JS
9568 int qidx;
9569
6a828b0f
JS
9570 memset(phba->sli4_hba.cq_lookup, 0,
9571 (sizeof(struct lpfc_queue *) * (phba->sli4_hba.cq_max + 1)));
657add4e 9572 /* Loop thru all IRQ vectors */
6a828b0f 9573 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
657add4e
JS
9574 /* Get the EQ corresponding to the IRQ vector */
9575 eq = phba->sli4_hba.hba_eq_hdl[qidx].eq;
6a828b0f
JS
9576 if (!eq)
9577 continue;
657add4e 9578 /* Loop through all CQs associated with that EQ */
6a828b0f
JS
9579 list_for_each_entry(childq, &eq->child_list, list) {
9580 if (childq->queue_id > phba->sli4_hba.cq_max)
9581 continue;
c00f62e6 9582 if (childq->subtype == LPFC_IO)
6a828b0f
JS
9583 phba->sli4_hba.cq_lookup[childq->queue_id] =
9584 childq;
9585 }
9586 }
9587}
9588
da0436e9
JS
9589/**
9590 * lpfc_sli4_queue_setup - Set up all the SLI4 queues
9591 * @phba: pointer to lpfc hba data structure.
9592 *
9593 * This routine is invoked to set up all the SLI4 queues for the FCoE HBA
9594 * operation.
9595 *
9596 * Return codes
af901ca1 9597 * 0 - successful
25985edc 9598 * -ENOMEM - No available memory
d439d286 9599 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
9600 **/
9601int
9602lpfc_sli4_queue_setup(struct lpfc_hba *phba)
9603{
962bc51b
JS
9604 uint32_t shdr_status, shdr_add_status;
9605 union lpfc_sli4_cfg_shdr *shdr;
657add4e 9606 struct lpfc_vector_map_info *cpup;
cdb42bec 9607 struct lpfc_sli4_hdw_queue *qp;
962bc51b 9608 LPFC_MBOXQ_t *mboxq;
657add4e 9609 int qidx, cpu;
cb733e35 9610 uint32_t length, usdelay;
895427bd 9611 int rc = -ENOMEM;
962bc51b
JS
9612
9613 /* Check for dual-ULP support */
9614 mboxq = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9615 if (!mboxq) {
372c187b 9616 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
962bc51b
JS
9617 "3249 Unable to allocate memory for "
9618 "QUERY_FW_CFG mailbox command\n");
9619 return -ENOMEM;
9620 }
9621 length = (sizeof(struct lpfc_mbx_query_fw_config) -
9622 sizeof(struct lpfc_sli4_cfg_mhdr));
9623 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
9624 LPFC_MBOX_OPCODE_QUERY_FW_CFG,
9625 length, LPFC_SLI4_MBX_EMBED);
9626
9627 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
9628
9629 shdr = (union lpfc_sli4_cfg_shdr *)
9630 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
9631 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
9632 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
9633 if (shdr_status || shdr_add_status || rc) {
372c187b 9634 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
962bc51b
JS
9635 "3250 QUERY_FW_CFG mailbox failed with status "
9636 "x%x add_status x%x, mbx status x%x\n",
9637 shdr_status, shdr_add_status, rc);
9638 if (rc != MBX_TIMEOUT)
9639 mempool_free(mboxq, phba->mbox_mem_pool);
9640 rc = -ENXIO;
9641 goto out_error;
9642 }
9643
9644 phba->sli4_hba.fw_func_mode =
9645 mboxq->u.mqe.un.query_fw_cfg.rsp.function_mode;
9646 phba->sli4_hba.ulp0_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp0_mode;
9647 phba->sli4_hba.ulp1_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp1_mode;
8b017a30
JS
9648 phba->sli4_hba.physical_port =
9649 mboxq->u.mqe.un.query_fw_cfg.rsp.physical_port;
962bc51b
JS
9650 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9651 "3251 QUERY_FW_CFG: func_mode:x%x, ulp0_mode:x%x, "
9652 "ulp1_mode:x%x\n", phba->sli4_hba.fw_func_mode,
9653 phba->sli4_hba.ulp0_mode, phba->sli4_hba.ulp1_mode);
9654
9655 if (rc != MBX_TIMEOUT)
9656 mempool_free(mboxq, phba->mbox_mem_pool);
da0436e9
JS
9657
9658 /*
67d12733 9659 * Set up HBA Event Queues (EQs)
da0436e9 9660 */
cdb42bec 9661 qp = phba->sli4_hba.hdwq;
da0436e9 9662
67d12733 9663 /* Set up HBA event queue */
cdb42bec 9664 if (!qp) {
372c187b 9665 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2e90f4b5 9666 "3147 Fast-path EQs not allocated\n");
1b51197d 9667 rc = -ENOMEM;
67d12733 9668 goto out_error;
2e90f4b5 9669 }
657add4e
JS
9670
9671 /* Loop thru all IRQ vectors */
6a828b0f 9672 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
657add4e
JS
9673 /* Create HBA Event Queues (EQs) in order */
9674 for_each_present_cpu(cpu) {
9675 cpup = &phba->sli4_hba.cpu_map[cpu];
9676
9677 /* Look for the CPU thats using that vector with
9678 * LPFC_CPU_FIRST_IRQ set.
9679 */
9680 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
9681 continue;
9682 if (qidx != cpup->eq)
9683 continue;
9684
9685 /* Create an EQ for that vector */
9686 rc = lpfc_eq_create(phba, qp[cpup->hdwq].hba_eq,
9687 phba->cfg_fcp_imax);
9688 if (rc) {
372c187b 9689 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
657add4e
JS
9690 "0523 Failed setup of fast-path"
9691 " EQ (%d), rc = 0x%x\n",
9692 cpup->eq, (uint32_t)rc);
9693 goto out_destroy;
9694 }
9695
9696 /* Save the EQ for that vector in the hba_eq_hdl */
9697 phba->sli4_hba.hba_eq_hdl[cpup->eq].eq =
9698 qp[cpup->hdwq].hba_eq;
9699
9700 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9701 "2584 HBA EQ setup: queue[%d]-id=%d\n",
9702 cpup->eq,
9703 qp[cpup->hdwq].hba_eq->queue_id);
da0436e9 9704 }
67d12733
JS
9705 }
9706
657add4e 9707 /* Loop thru all Hardware Queues */
cdb42bec 9708 for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {
657add4e
JS
9709 cpu = lpfc_find_cpu_handle(phba, qidx, LPFC_FIND_BY_HDWQ);
9710 cpup = &phba->sli4_hba.cpu_map[cpu];
9711
9712 /* Create the CQ/WQ corresponding to the Hardware Queue */
cdb42bec 9713 rc = lpfc_create_wq_cq(phba,
657add4e 9714 phba->sli4_hba.hdwq[cpup->hdwq].hba_eq,
c00f62e6
JS
9715 qp[qidx].io_cq,
9716 qp[qidx].io_wq,
9717 &phba->sli4_hba.hdwq[qidx].io_cq_map,
9718 qidx,
9719 LPFC_IO);
cdb42bec 9720 if (rc) {
372c187b 9721 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd 9722 "0535 Failed to setup fastpath "
c00f62e6 9723 "IO WQ/CQ (%d), rc = 0x%x\n",
895427bd 9724 qidx, (uint32_t)rc);
cdb42bec 9725 goto out_destroy;
895427bd 9726 }
67d12733 9727 }
895427bd 9728
da0436e9 9729 /*
895427bd 9730 * Set up Slow Path Complete Queues (CQs)
da0436e9
JS
9731 */
9732
895427bd 9733 /* Set up slow-path MBOX CQ/MQ */
da0436e9 9734
895427bd 9735 if (!phba->sli4_hba.mbx_cq || !phba->sli4_hba.mbx_wq) {
372c187b 9736 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9737 "0528 %s not allocated\n",
9738 phba->sli4_hba.mbx_cq ?
d1f525aa 9739 "Mailbox WQ" : "Mailbox CQ");
1b51197d 9740 rc = -ENOMEM;
895427bd 9741 goto out_destroy;
da0436e9 9742 }
da0436e9 9743
cdb42bec 9744 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
d1f525aa
JS
9745 phba->sli4_hba.mbx_cq,
9746 phba->sli4_hba.mbx_wq,
9747 NULL, 0, LPFC_MBOX);
da0436e9 9748 if (rc) {
372c187b 9749 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9750 "0529 Failed setup of mailbox WQ/CQ: rc = 0x%x\n",
9751 (uint32_t)rc);
9752 goto out_destroy;
da0436e9 9753 }
2d7dbc4c
JS
9754 if (phba->nvmet_support) {
9755 if (!phba->sli4_hba.nvmet_cqset) {
372c187b 9756 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9757 "3165 Fast-path NVME CQ Set "
9758 "array not allocated\n");
9759 rc = -ENOMEM;
9760 goto out_destroy;
9761 }
9762 if (phba->cfg_nvmet_mrq > 1) {
9763 rc = lpfc_cq_create_set(phba,
9764 phba->sli4_hba.nvmet_cqset,
cdb42bec 9765 qp,
2d7dbc4c
JS
9766 LPFC_WCQ, LPFC_NVMET);
9767 if (rc) {
372c187b 9768 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9769 "3164 Failed setup of NVME CQ "
9770 "Set, rc = 0x%x\n",
9771 (uint32_t)rc);
9772 goto out_destroy;
9773 }
9774 } else {
9775 /* Set up NVMET Receive Complete Queue */
9776 rc = lpfc_cq_create(phba, phba->sli4_hba.nvmet_cqset[0],
cdb42bec 9777 qp[0].hba_eq,
2d7dbc4c
JS
9778 LPFC_WCQ, LPFC_NVMET);
9779 if (rc) {
372c187b 9780 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9781 "6089 Failed setup NVMET CQ: "
9782 "rc = 0x%x\n", (uint32_t)rc);
9783 goto out_destroy;
9784 }
81b96eda
JS
9785 phba->sli4_hba.nvmet_cqset[0]->chann = 0;
9786
2d7dbc4c
JS
9787 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9788 "6090 NVMET CQ setup: cq-id=%d, "
9789 "parent eq-id=%d\n",
9790 phba->sli4_hba.nvmet_cqset[0]->queue_id,
cdb42bec 9791 qp[0].hba_eq->queue_id);
2d7dbc4c
JS
9792 }
9793 }
da0436e9 9794
895427bd
JS
9795 /* Set up slow-path ELS WQ/CQ */
9796 if (!phba->sli4_hba.els_cq || !phba->sli4_hba.els_wq) {
372c187b 9797 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9798 "0530 ELS %s not allocated\n",
9799 phba->sli4_hba.els_cq ? "WQ" : "CQ");
1b51197d 9800 rc = -ENOMEM;
895427bd 9801 goto out_destroy;
da0436e9 9802 }
cdb42bec
JS
9803 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
9804 phba->sli4_hba.els_cq,
9805 phba->sli4_hba.els_wq,
9806 NULL, 0, LPFC_ELS);
da0436e9 9807 if (rc) {
372c187b 9808 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
cdb42bec
JS
9809 "0525 Failed setup of ELS WQ/CQ: rc = 0x%x\n",
9810 (uint32_t)rc);
895427bd 9811 goto out_destroy;
da0436e9
JS
9812 }
9813 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9814 "2590 ELS WQ setup: wq-id=%d, parent cq-id=%d\n",
9815 phba->sli4_hba.els_wq->queue_id,
9816 phba->sli4_hba.els_cq->queue_id);
9817
cdb42bec 9818 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
895427bd
JS
9819 /* Set up NVME LS Complete Queue */
9820 if (!phba->sli4_hba.nvmels_cq || !phba->sli4_hba.nvmels_wq) {
372c187b 9821 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9822 "6091 LS %s not allocated\n",
9823 phba->sli4_hba.nvmels_cq ? "WQ" : "CQ");
9824 rc = -ENOMEM;
9825 goto out_destroy;
9826 }
cdb42bec
JS
9827 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
9828 phba->sli4_hba.nvmels_cq,
9829 phba->sli4_hba.nvmels_wq,
9830 NULL, 0, LPFC_NVME_LS);
895427bd 9831 if (rc) {
372c187b 9832 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
cdb42bec
JS
9833 "0526 Failed setup of NVVME LS WQ/CQ: "
9834 "rc = 0x%x\n", (uint32_t)rc);
895427bd
JS
9835 goto out_destroy;
9836 }
9837
9838 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9839 "6096 ELS WQ setup: wq-id=%d, "
9840 "parent cq-id=%d\n",
9841 phba->sli4_hba.nvmels_wq->queue_id,
9842 phba->sli4_hba.nvmels_cq->queue_id);
9843 }
9844
2d7dbc4c
JS
9845 /*
9846 * Create NVMET Receive Queue (RQ)
9847 */
9848 if (phba->nvmet_support) {
9849 if ((!phba->sli4_hba.nvmet_cqset) ||
9850 (!phba->sli4_hba.nvmet_mrq_hdr) ||
9851 (!phba->sli4_hba.nvmet_mrq_data)) {
372c187b 9852 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9853 "6130 MRQ CQ Queues not "
9854 "allocated\n");
9855 rc = -ENOMEM;
9856 goto out_destroy;
9857 }
9858 if (phba->cfg_nvmet_mrq > 1) {
9859 rc = lpfc_mrq_create(phba,
9860 phba->sli4_hba.nvmet_mrq_hdr,
9861 phba->sli4_hba.nvmet_mrq_data,
9862 phba->sli4_hba.nvmet_cqset,
9863 LPFC_NVMET);
9864 if (rc) {
372c187b 9865 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9866 "6098 Failed setup of NVMET "
9867 "MRQ: rc = 0x%x\n",
9868 (uint32_t)rc);
9869 goto out_destroy;
9870 }
9871
9872 } else {
9873 rc = lpfc_rq_create(phba,
9874 phba->sli4_hba.nvmet_mrq_hdr[0],
9875 phba->sli4_hba.nvmet_mrq_data[0],
9876 phba->sli4_hba.nvmet_cqset[0],
9877 LPFC_NVMET);
9878 if (rc) {
372c187b 9879 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9880 "6057 Failed setup of NVMET "
9881 "Receive Queue: rc = 0x%x\n",
9882 (uint32_t)rc);
9883 goto out_destroy;
9884 }
9885
9886 lpfc_printf_log(
9887 phba, KERN_INFO, LOG_INIT,
9888 "6099 NVMET RQ setup: hdr-rq-id=%d, "
9889 "dat-rq-id=%d parent cq-id=%d\n",
9890 phba->sli4_hba.nvmet_mrq_hdr[0]->queue_id,
9891 phba->sli4_hba.nvmet_mrq_data[0]->queue_id,
9892 phba->sli4_hba.nvmet_cqset[0]->queue_id);
9893
9894 }
9895 }
9896
da0436e9 9897 if (!phba->sli4_hba.hdr_rq || !phba->sli4_hba.dat_rq) {
372c187b 9898 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9899 "0540 Receive Queue not allocated\n");
1b51197d 9900 rc = -ENOMEM;
895427bd 9901 goto out_destroy;
da0436e9 9902 }
73d91e50 9903
da0436e9 9904 rc = lpfc_rq_create(phba, phba->sli4_hba.hdr_rq, phba->sli4_hba.dat_rq,
4d9ab994 9905 phba->sli4_hba.els_cq, LPFC_USOL);
da0436e9 9906 if (rc) {
372c187b 9907 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9908 "0541 Failed setup of Receive Queue: "
a2fc4aef 9909 "rc = 0x%x\n", (uint32_t)rc);
895427bd 9910 goto out_destroy;
da0436e9 9911 }
73d91e50 9912
da0436e9
JS
9913 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9914 "2592 USL RQ setup: hdr-rq-id=%d, dat-rq-id=%d "
9915 "parent cq-id=%d\n",
9916 phba->sli4_hba.hdr_rq->queue_id,
9917 phba->sli4_hba.dat_rq->queue_id,
4d9ab994 9918 phba->sli4_hba.els_cq->queue_id);
1ba981fd 9919
cb733e35
JS
9920 if (phba->cfg_fcp_imax)
9921 usdelay = LPFC_SEC_TO_USEC / phba->cfg_fcp_imax;
9922 else
9923 usdelay = 0;
9924
6a828b0f 9925 for (qidx = 0; qidx < phba->cfg_irq_chann;
cdb42bec 9926 qidx += LPFC_MAX_EQ_DELAY_EQID_CNT)
0cf07f84 9927 lpfc_modify_hba_eq_delay(phba, qidx, LPFC_MAX_EQ_DELAY_EQID_CNT,
cb733e35 9928 usdelay);
43140ca6 9929
6a828b0f
JS
9930 if (phba->sli4_hba.cq_max) {
9931 kfree(phba->sli4_hba.cq_lookup);
9932 phba->sli4_hba.cq_lookup = kcalloc((phba->sli4_hba.cq_max + 1),
9933 sizeof(struct lpfc_queue *), GFP_KERNEL);
9934 if (!phba->sli4_hba.cq_lookup) {
372c187b 9935 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
6a828b0f
JS
9936 "0549 Failed setup of CQ Lookup table: "
9937 "size 0x%x\n", phba->sli4_hba.cq_max);
fad28e3d 9938 rc = -ENOMEM;
895427bd 9939 goto out_destroy;
1ba981fd 9940 }
6a828b0f 9941 lpfc_setup_cq_lookup(phba);
1ba981fd 9942 }
da0436e9
JS
9943 return 0;
9944
895427bd
JS
9945out_destroy:
9946 lpfc_sli4_queue_unset(phba);
da0436e9
JS
9947out_error:
9948 return rc;
9949}
9950
9951/**
9952 * lpfc_sli4_queue_unset - Unset all the SLI4 queues
9953 * @phba: pointer to lpfc hba data structure.
9954 *
9955 * This routine is invoked to unset all the SLI4 queues with the FCoE HBA
9956 * operation.
9957 *
9958 * Return codes
af901ca1 9959 * 0 - successful
25985edc 9960 * -ENOMEM - No available memory
d439d286 9961 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
9962 **/
9963void
9964lpfc_sli4_queue_unset(struct lpfc_hba *phba)
9965{
cdb42bec 9966 struct lpfc_sli4_hdw_queue *qp;
657add4e 9967 struct lpfc_queue *eq;
895427bd 9968 int qidx;
da0436e9
JS
9969
9970 /* Unset mailbox command work queue */
895427bd
JS
9971 if (phba->sli4_hba.mbx_wq)
9972 lpfc_mq_destroy(phba, phba->sli4_hba.mbx_wq);
9973
9974 /* Unset NVME LS work queue */
9975 if (phba->sli4_hba.nvmels_wq)
9976 lpfc_wq_destroy(phba, phba->sli4_hba.nvmels_wq);
9977
da0436e9 9978 /* Unset ELS work queue */
019c0d66 9979 if (phba->sli4_hba.els_wq)
895427bd
JS
9980 lpfc_wq_destroy(phba, phba->sli4_hba.els_wq);
9981
da0436e9 9982 /* Unset unsolicited receive queue */
895427bd
JS
9983 if (phba->sli4_hba.hdr_rq)
9984 lpfc_rq_destroy(phba, phba->sli4_hba.hdr_rq,
9985 phba->sli4_hba.dat_rq);
9986
da0436e9 9987 /* Unset mailbox command complete queue */
895427bd
JS
9988 if (phba->sli4_hba.mbx_cq)
9989 lpfc_cq_destroy(phba, phba->sli4_hba.mbx_cq);
9990
da0436e9 9991 /* Unset ELS complete queue */
895427bd
JS
9992 if (phba->sli4_hba.els_cq)
9993 lpfc_cq_destroy(phba, phba->sli4_hba.els_cq);
9994
9995 /* Unset NVME LS complete queue */
9996 if (phba->sli4_hba.nvmels_cq)
9997 lpfc_cq_destroy(phba, phba->sli4_hba.nvmels_cq);
9998
bcb24f65
JS
9999 if (phba->nvmet_support) {
10000 /* Unset NVMET MRQ queue */
10001 if (phba->sli4_hba.nvmet_mrq_hdr) {
10002 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
10003 lpfc_rq_destroy(
10004 phba,
2d7dbc4c
JS
10005 phba->sli4_hba.nvmet_mrq_hdr[qidx],
10006 phba->sli4_hba.nvmet_mrq_data[qidx]);
bcb24f65 10007 }
2d7dbc4c 10008
bcb24f65
JS
10009 /* Unset NVMET CQ Set complete queue */
10010 if (phba->sli4_hba.nvmet_cqset) {
10011 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
10012 lpfc_cq_destroy(
10013 phba, phba->sli4_hba.nvmet_cqset[qidx]);
10014 }
2d7dbc4c
JS
10015 }
10016
cdb42bec
JS
10017 /* Unset fast-path SLI4 queues */
10018 if (phba->sli4_hba.hdwq) {
657add4e 10019 /* Loop thru all Hardware Queues */
cdb42bec 10020 for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {
657add4e 10021 /* Destroy the CQ/WQ corresponding to Hardware Queue */
cdb42bec 10022 qp = &phba->sli4_hba.hdwq[qidx];
c00f62e6
JS
10023 lpfc_wq_destroy(phba, qp->io_wq);
10024 lpfc_cq_destroy(phba, qp->io_cq);
657add4e
JS
10025 }
10026 /* Loop thru all IRQ vectors */
10027 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
10028 /* Destroy the EQ corresponding to the IRQ vector */
10029 eq = phba->sli4_hba.hba_eq_hdl[qidx].eq;
10030 lpfc_eq_destroy(phba, eq);
cdb42bec
JS
10031 }
10032 }
895427bd 10033
6a828b0f
JS
10034 kfree(phba->sli4_hba.cq_lookup);
10035 phba->sli4_hba.cq_lookup = NULL;
10036 phba->sli4_hba.cq_max = 0;
da0436e9
JS
10037}
10038
10039/**
10040 * lpfc_sli4_cq_event_pool_create - Create completion-queue event free pool
10041 * @phba: pointer to lpfc hba data structure.
10042 *
10043 * This routine is invoked to allocate and set up a pool of completion queue
10044 * events. The body of the completion queue event is a completion queue entry
10045 * CQE. For now, this pool is used for the interrupt service routine to queue
10046 * the following HBA completion queue events for the worker thread to process:
10047 * - Mailbox asynchronous events
10048 * - Receive queue completion unsolicited events
10049 * Later, this can be used for all the slow-path events.
10050 *
10051 * Return codes
af901ca1 10052 * 0 - successful
25985edc 10053 * -ENOMEM - No available memory
da0436e9
JS
10054 **/
10055static int
10056lpfc_sli4_cq_event_pool_create(struct lpfc_hba *phba)
10057{
10058 struct lpfc_cq_event *cq_event;
10059 int i;
10060
10061 for (i = 0; i < (4 * phba->sli4_hba.cq_ecount); i++) {
10062 cq_event = kmalloc(sizeof(struct lpfc_cq_event), GFP_KERNEL);
10063 if (!cq_event)
10064 goto out_pool_create_fail;
10065 list_add_tail(&cq_event->list,
10066 &phba->sli4_hba.sp_cqe_event_pool);
10067 }
10068 return 0;
10069
10070out_pool_create_fail:
10071 lpfc_sli4_cq_event_pool_destroy(phba);
10072 return -ENOMEM;
10073}
10074
10075/**
10076 * lpfc_sli4_cq_event_pool_destroy - Free completion-queue event free pool
10077 * @phba: pointer to lpfc hba data structure.
10078 *
10079 * This routine is invoked to free the pool of completion queue events at
10080 * driver unload time. Note that, it is the responsibility of the driver
10081 * cleanup routine to free all the outstanding completion-queue events
10082 * allocated from this pool back into the pool before invoking this routine
10083 * to destroy the pool.
10084 **/
10085static void
10086lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *phba)
10087{
10088 struct lpfc_cq_event *cq_event, *next_cq_event;
10089
10090 list_for_each_entry_safe(cq_event, next_cq_event,
10091 &phba->sli4_hba.sp_cqe_event_pool, list) {
10092 list_del(&cq_event->list);
10093 kfree(cq_event);
10094 }
10095}
10096
10097/**
10098 * __lpfc_sli4_cq_event_alloc - Allocate a completion-queue event from free pool
10099 * @phba: pointer to lpfc hba data structure.
10100 *
10101 * This routine is the lock free version of the API invoked to allocate a
10102 * completion-queue event from the free pool.
10103 *
10104 * Return: Pointer to the newly allocated completion-queue event if successful
10105 * NULL otherwise.
10106 **/
10107struct lpfc_cq_event *
10108__lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
10109{
10110 struct lpfc_cq_event *cq_event = NULL;
10111
10112 list_remove_head(&phba->sli4_hba.sp_cqe_event_pool, cq_event,
10113 struct lpfc_cq_event, list);
10114 return cq_event;
10115}
10116
10117/**
10118 * lpfc_sli4_cq_event_alloc - Allocate a completion-queue event from free pool
10119 * @phba: pointer to lpfc hba data structure.
10120 *
10121 * This routine is the lock version of the API invoked to allocate a
10122 * completion-queue event from the free pool.
10123 *
10124 * Return: Pointer to the newly allocated completion-queue event if successful
10125 * NULL otherwise.
10126 **/
10127struct lpfc_cq_event *
10128lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
10129{
10130 struct lpfc_cq_event *cq_event;
10131 unsigned long iflags;
10132
10133 spin_lock_irqsave(&phba->hbalock, iflags);
10134 cq_event = __lpfc_sli4_cq_event_alloc(phba);
10135 spin_unlock_irqrestore(&phba->hbalock, iflags);
10136 return cq_event;
10137}
10138
10139/**
10140 * __lpfc_sli4_cq_event_release - Release a completion-queue event to free pool
10141 * @phba: pointer to lpfc hba data structure.
10142 * @cq_event: pointer to the completion queue event to be freed.
10143 *
10144 * This routine is the lock free version of the API invoked to release a
10145 * completion-queue event back into the free pool.
10146 **/
10147void
10148__lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
10149 struct lpfc_cq_event *cq_event)
10150{
10151 list_add_tail(&cq_event->list, &phba->sli4_hba.sp_cqe_event_pool);
10152}
10153
10154/**
10155 * lpfc_sli4_cq_event_release - Release a completion-queue event to free pool
10156 * @phba: pointer to lpfc hba data structure.
10157 * @cq_event: pointer to the completion queue event to be freed.
10158 *
10159 * This routine is the lock version of the API invoked to release a
10160 * completion-queue event back into the free pool.
10161 **/
10162void
10163lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
10164 struct lpfc_cq_event *cq_event)
10165{
10166 unsigned long iflags;
10167 spin_lock_irqsave(&phba->hbalock, iflags);
10168 __lpfc_sli4_cq_event_release(phba, cq_event);
10169 spin_unlock_irqrestore(&phba->hbalock, iflags);
10170}
10171
10172/**
10173 * lpfc_sli4_cq_event_release_all - Release all cq events to the free pool
10174 * @phba: pointer to lpfc hba data structure.
10175 *
10176 * This routine is to free all the pending completion-queue events to the
10177 * back into the free pool for device reset.
10178 **/
10179static void
10180lpfc_sli4_cq_event_release_all(struct lpfc_hba *phba)
10181{
e7dab164
JS
10182 LIST_HEAD(cq_event_list);
10183 struct lpfc_cq_event *cq_event;
da0436e9
JS
10184 unsigned long iflags;
10185
10186 /* Retrieve all the pending WCQEs from pending WCQE lists */
e7dab164 10187
da0436e9 10188 /* Pending ELS XRI abort events */
e7dab164 10189 spin_lock_irqsave(&phba->sli4_hba.els_xri_abrt_list_lock, iflags);
da0436e9 10190 list_splice_init(&phba->sli4_hba.sp_els_xri_aborted_work_queue,
e7dab164
JS
10191 &cq_event_list);
10192 spin_unlock_irqrestore(&phba->sli4_hba.els_xri_abrt_list_lock, iflags);
10193
da0436e9 10194 /* Pending asynnc events */
e7dab164 10195 spin_lock_irqsave(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9 10196 list_splice_init(&phba->sli4_hba.sp_asynce_work_queue,
e7dab164
JS
10197 &cq_event_list);
10198 spin_unlock_irqrestore(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9 10199
e7dab164
JS
10200 while (!list_empty(&cq_event_list)) {
10201 list_remove_head(&cq_event_list, cq_event,
10202 struct lpfc_cq_event, list);
10203 lpfc_sli4_cq_event_release(phba, cq_event);
da0436e9
JS
10204 }
10205}
10206
10207/**
10208 * lpfc_pci_function_reset - Reset pci function.
10209 * @phba: pointer to lpfc hba data structure.
10210 *
10211 * This routine is invoked to request a PCI function reset. It will destroys
10212 * all resources assigned to the PCI function which originates this request.
10213 *
10214 * Return codes
af901ca1 10215 * 0 - successful
25985edc 10216 * -ENOMEM - No available memory
d439d286 10217 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
10218 **/
10219int
10220lpfc_pci_function_reset(struct lpfc_hba *phba)
10221{
10222 LPFC_MBOXQ_t *mboxq;
2fcee4bf 10223 uint32_t rc = 0, if_type;
da0436e9 10224 uint32_t shdr_status, shdr_add_status;
2f6fa2c9
JS
10225 uint32_t rdy_chk;
10226 uint32_t port_reset = 0;
da0436e9 10227 union lpfc_sli4_cfg_shdr *shdr;
2fcee4bf 10228 struct lpfc_register reg_data;
2b81f942 10229 uint16_t devid;
da0436e9 10230
2fcee4bf
JS
10231 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
10232 switch (if_type) {
10233 case LPFC_SLI_INTF_IF_TYPE_0:
10234 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
10235 GFP_KERNEL);
10236 if (!mboxq) {
372c187b 10237 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
10238 "0494 Unable to allocate memory for "
10239 "issuing SLI_FUNCTION_RESET mailbox "
10240 "command\n");
10241 return -ENOMEM;
10242 }
da0436e9 10243
2fcee4bf
JS
10244 /* Setup PCI function reset mailbox-ioctl command */
10245 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
10246 LPFC_MBOX_OPCODE_FUNCTION_RESET, 0,
10247 LPFC_SLI4_MBX_EMBED);
10248 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
10249 shdr = (union lpfc_sli4_cfg_shdr *)
10250 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
10251 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
10252 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status,
10253 &shdr->response);
10254 if (rc != MBX_TIMEOUT)
10255 mempool_free(mboxq, phba->mbox_mem_pool);
10256 if (shdr_status || shdr_add_status || rc) {
372c187b 10257 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
10258 "0495 SLI_FUNCTION_RESET mailbox "
10259 "failed with status x%x add_status x%x,"
10260 " mbx status x%x\n",
10261 shdr_status, shdr_add_status, rc);
10262 rc = -ENXIO;
10263 }
10264 break;
10265 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 10266 case LPFC_SLI_INTF_IF_TYPE_6:
2f6fa2c9
JS
10267wait:
10268 /*
10269 * Poll the Port Status Register and wait for RDY for
10270 * up to 30 seconds. If the port doesn't respond, treat
10271 * it as an error.
10272 */
77d093fb 10273 for (rdy_chk = 0; rdy_chk < 1500; rdy_chk++) {
2f6fa2c9
JS
10274 if (lpfc_readl(phba->sli4_hba.u.if_type2.
10275 STATUSregaddr, &reg_data.word0)) {
10276 rc = -ENODEV;
10277 goto out;
10278 }
10279 if (bf_get(lpfc_sliport_status_rdy, &reg_data))
10280 break;
10281 msleep(20);
10282 }
10283
10284 if (!bf_get(lpfc_sliport_status_rdy, &reg_data)) {
10285 phba->work_status[0] = readl(
10286 phba->sli4_hba.u.if_type2.ERR1regaddr);
10287 phba->work_status[1] = readl(
10288 phba->sli4_hba.u.if_type2.ERR2regaddr);
372c187b 10289 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2f6fa2c9
JS
10290 "2890 Port not ready, port status reg "
10291 "0x%x error 1=0x%x, error 2=0x%x\n",
10292 reg_data.word0,
10293 phba->work_status[0],
10294 phba->work_status[1]);
10295 rc = -ENODEV;
10296 goto out;
10297 }
10298
10299 if (!port_reset) {
10300 /*
10301 * Reset the port now
10302 */
2fcee4bf
JS
10303 reg_data.word0 = 0;
10304 bf_set(lpfc_sliport_ctrl_end, &reg_data,
10305 LPFC_SLIPORT_LITTLE_ENDIAN);
10306 bf_set(lpfc_sliport_ctrl_ip, &reg_data,
10307 LPFC_SLIPORT_INIT_PORT);
10308 writel(reg_data.word0, phba->sli4_hba.u.if_type2.
10309 CTRLregaddr);
8fcb8acd 10310 /* flush */
2b81f942
JS
10311 pci_read_config_word(phba->pcidev,
10312 PCI_DEVICE_ID, &devid);
2fcee4bf 10313
2f6fa2c9
JS
10314 port_reset = 1;
10315 msleep(20);
10316 goto wait;
10317 } else if (bf_get(lpfc_sliport_status_rn, &reg_data)) {
10318 rc = -ENODEV;
10319 goto out;
2fcee4bf
JS
10320 }
10321 break;
2f6fa2c9 10322
2fcee4bf
JS
10323 case LPFC_SLI_INTF_IF_TYPE_1:
10324 default:
10325 break;
da0436e9 10326 }
2fcee4bf 10327
73d91e50 10328out:
2fcee4bf 10329 /* Catch the not-ready port failure after a port reset. */
2f6fa2c9 10330 if (rc) {
372c187b 10331 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
229adb0e 10332 "3317 HBA not functional: IP Reset Failed "
2f6fa2c9 10333 "try: echo fw_reset > board_mode\n");
2fcee4bf 10334 rc = -ENODEV;
229adb0e 10335 }
2fcee4bf 10336
da0436e9
JS
10337 return rc;
10338}
10339
da0436e9
JS
10340/**
10341 * lpfc_sli4_pci_mem_setup - Setup SLI4 HBA PCI memory space.
10342 * @phba: pointer to lpfc hba data structure.
10343 *
10344 * This routine is invoked to set up the PCI device memory space for device
10345 * with SLI-4 interface spec.
10346 *
10347 * Return codes
af901ca1 10348 * 0 - successful
da0436e9
JS
10349 * other values - error
10350 **/
10351static int
10352lpfc_sli4_pci_mem_setup(struct lpfc_hba *phba)
10353{
f30e1bfd 10354 struct pci_dev *pdev = phba->pcidev;
da0436e9 10355 unsigned long bar0map_len, bar1map_len, bar2map_len;
3a487ff7 10356 int error;
2fcee4bf 10357 uint32_t if_type;
da0436e9 10358
f30e1bfd 10359 if (!pdev)
56de8357 10360 return -ENODEV;
da0436e9
JS
10361
10362 /* Set the device DMA mask size */
56de8357
HR
10363 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
10364 if (error)
10365 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10366 if (error)
f30e1bfd 10367 return error;
da0436e9 10368
2fcee4bf
JS
10369 /*
10370 * The BARs and register set definitions and offset locations are
10371 * dependent on the if_type.
10372 */
10373 if (pci_read_config_dword(pdev, LPFC_SLI_INTF,
10374 &phba->sli4_hba.sli_intf.word0)) {
3a487ff7 10375 return -ENODEV;
2fcee4bf
JS
10376 }
10377
10378 /* There is no SLI3 failback for SLI4 devices. */
10379 if (bf_get(lpfc_sli_intf_valid, &phba->sli4_hba.sli_intf) !=
10380 LPFC_SLI_INTF_VALID) {
372c187b 10381 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
10382 "2894 SLI_INTF reg contents invalid "
10383 "sli_intf reg 0x%x\n",
10384 phba->sli4_hba.sli_intf.word0);
3a487ff7 10385 return -ENODEV;
2fcee4bf
JS
10386 }
10387
10388 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
10389 /*
10390 * Get the bus address of SLI4 device Bar regions and the
10391 * number of bytes required by each mapping. The mapping of the
10392 * particular PCI BARs regions is dependent on the type of
10393 * SLI4 device.
da0436e9 10394 */
f5ca6f2e
JS
10395 if (pci_resource_start(pdev, PCI_64BIT_BAR0)) {
10396 phba->pci_bar0_map = pci_resource_start(pdev, PCI_64BIT_BAR0);
10397 bar0map_len = pci_resource_len(pdev, PCI_64BIT_BAR0);
2fcee4bf
JS
10398
10399 /*
10400 * Map SLI4 PCI Config Space Register base to a kernel virtual
10401 * addr
10402 */
10403 phba->sli4_hba.conf_regs_memmap_p =
10404 ioremap(phba->pci_bar0_map, bar0map_len);
10405 if (!phba->sli4_hba.conf_regs_memmap_p) {
10406 dev_printk(KERN_ERR, &pdev->dev,
10407 "ioremap failed for SLI4 PCI config "
10408 "registers.\n");
3a487ff7 10409 return -ENODEV;
2fcee4bf 10410 }
f5ca6f2e 10411 phba->pci_bar0_memmap_p = phba->sli4_hba.conf_regs_memmap_p;
2fcee4bf
JS
10412 /* Set up BAR0 PCI config space register memory map */
10413 lpfc_sli4_bar0_register_memmap(phba, if_type);
1dfb5a47
JS
10414 } else {
10415 phba->pci_bar0_map = pci_resource_start(pdev, 1);
10416 bar0map_len = pci_resource_len(pdev, 1);
27d6ac0a 10417 if (if_type >= LPFC_SLI_INTF_IF_TYPE_2) {
2fcee4bf
JS
10418 dev_printk(KERN_ERR, &pdev->dev,
10419 "FATAL - No BAR0 mapping for SLI4, if_type 2\n");
3a487ff7 10420 return -ENODEV;
2fcee4bf
JS
10421 }
10422 phba->sli4_hba.conf_regs_memmap_p =
da0436e9 10423 ioremap(phba->pci_bar0_map, bar0map_len);
2fcee4bf
JS
10424 if (!phba->sli4_hba.conf_regs_memmap_p) {
10425 dev_printk(KERN_ERR, &pdev->dev,
10426 "ioremap failed for SLI4 PCI config "
10427 "registers.\n");
3a487ff7 10428 return -ENODEV;
2fcee4bf
JS
10429 }
10430 lpfc_sli4_bar0_register_memmap(phba, if_type);
da0436e9
JS
10431 }
10432
e4b9794e
JS
10433 if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
10434 if (pci_resource_start(pdev, PCI_64BIT_BAR2)) {
10435 /*
10436 * Map SLI4 if type 0 HBA Control Register base to a
10437 * kernel virtual address and setup the registers.
10438 */
10439 phba->pci_bar1_map = pci_resource_start(pdev,
10440 PCI_64BIT_BAR2);
10441 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
10442 phba->sli4_hba.ctrl_regs_memmap_p =
10443 ioremap(phba->pci_bar1_map,
10444 bar1map_len);
10445 if (!phba->sli4_hba.ctrl_regs_memmap_p) {
10446 dev_err(&pdev->dev,
10447 "ioremap failed for SLI4 HBA "
10448 "control registers.\n");
10449 error = -ENOMEM;
10450 goto out_iounmap_conf;
10451 }
10452 phba->pci_bar2_memmap_p =
10453 phba->sli4_hba.ctrl_regs_memmap_p;
27d6ac0a 10454 lpfc_sli4_bar1_register_memmap(phba, if_type);
e4b9794e
JS
10455 } else {
10456 error = -ENOMEM;
2fcee4bf
JS
10457 goto out_iounmap_conf;
10458 }
da0436e9
JS
10459 }
10460
27d6ac0a
JS
10461 if ((if_type == LPFC_SLI_INTF_IF_TYPE_6) &&
10462 (pci_resource_start(pdev, PCI_64BIT_BAR2))) {
10463 /*
10464 * Map SLI4 if type 6 HBA Doorbell Register base to a kernel
10465 * virtual address and setup the registers.
10466 */
10467 phba->pci_bar1_map = pci_resource_start(pdev, PCI_64BIT_BAR2);
10468 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
10469 phba->sli4_hba.drbl_regs_memmap_p =
10470 ioremap(phba->pci_bar1_map, bar1map_len);
10471 if (!phba->sli4_hba.drbl_regs_memmap_p) {
10472 dev_err(&pdev->dev,
10473 "ioremap failed for SLI4 HBA doorbell registers.\n");
3a487ff7 10474 error = -ENOMEM;
27d6ac0a
JS
10475 goto out_iounmap_conf;
10476 }
10477 phba->pci_bar2_memmap_p = phba->sli4_hba.drbl_regs_memmap_p;
10478 lpfc_sli4_bar1_register_memmap(phba, if_type);
10479 }
10480
e4b9794e
JS
10481 if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
10482 if (pci_resource_start(pdev, PCI_64BIT_BAR4)) {
10483 /*
10484 * Map SLI4 if type 0 HBA Doorbell Register base to
10485 * a kernel virtual address and setup the registers.
10486 */
10487 phba->pci_bar2_map = pci_resource_start(pdev,
10488 PCI_64BIT_BAR4);
10489 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
10490 phba->sli4_hba.drbl_regs_memmap_p =
10491 ioremap(phba->pci_bar2_map,
10492 bar2map_len);
10493 if (!phba->sli4_hba.drbl_regs_memmap_p) {
10494 dev_err(&pdev->dev,
10495 "ioremap failed for SLI4 HBA"
10496 " doorbell registers.\n");
10497 error = -ENOMEM;
10498 goto out_iounmap_ctrl;
10499 }
10500 phba->pci_bar4_memmap_p =
10501 phba->sli4_hba.drbl_regs_memmap_p;
10502 error = lpfc_sli4_bar2_register_memmap(phba, LPFC_VF0);
10503 if (error)
10504 goto out_iounmap_all;
10505 } else {
10506 error = -ENOMEM;
2fcee4bf 10507 goto out_iounmap_all;
e4b9794e 10508 }
da0436e9
JS
10509 }
10510
1351e69f
JS
10511 if (if_type == LPFC_SLI_INTF_IF_TYPE_6 &&
10512 pci_resource_start(pdev, PCI_64BIT_BAR4)) {
10513 /*
10514 * Map SLI4 if type 6 HBA DPP Register base to a kernel
10515 * virtual address and setup the registers.
10516 */
10517 phba->pci_bar2_map = pci_resource_start(pdev, PCI_64BIT_BAR4);
10518 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
10519 phba->sli4_hba.dpp_regs_memmap_p =
10520 ioremap(phba->pci_bar2_map, bar2map_len);
10521 if (!phba->sli4_hba.dpp_regs_memmap_p) {
10522 dev_err(&pdev->dev,
10523 "ioremap failed for SLI4 HBA dpp registers.\n");
3a487ff7 10524 error = -ENOMEM;
1351e69f
JS
10525 goto out_iounmap_ctrl;
10526 }
10527 phba->pci_bar4_memmap_p = phba->sli4_hba.dpp_regs_memmap_p;
10528 }
10529
b71413dd 10530 /* Set up the EQ/CQ register handeling functions now */
27d6ac0a
JS
10531 switch (if_type) {
10532 case LPFC_SLI_INTF_IF_TYPE_0:
10533 case LPFC_SLI_INTF_IF_TYPE_2:
b71413dd 10534 phba->sli4_hba.sli4_eq_clr_intr = lpfc_sli4_eq_clr_intr;
32517fc0
JS
10535 phba->sli4_hba.sli4_write_eq_db = lpfc_sli4_write_eq_db;
10536 phba->sli4_hba.sli4_write_cq_db = lpfc_sli4_write_cq_db;
27d6ac0a
JS
10537 break;
10538 case LPFC_SLI_INTF_IF_TYPE_6:
10539 phba->sli4_hba.sli4_eq_clr_intr = lpfc_sli4_if6_eq_clr_intr;
32517fc0
JS
10540 phba->sli4_hba.sli4_write_eq_db = lpfc_sli4_if6_write_eq_db;
10541 phba->sli4_hba.sli4_write_cq_db = lpfc_sli4_if6_write_cq_db;
27d6ac0a
JS
10542 break;
10543 default:
10544 break;
b71413dd
JS
10545 }
10546
da0436e9
JS
10547 return 0;
10548
10549out_iounmap_all:
10550 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10551out_iounmap_ctrl:
10552 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
10553out_iounmap_conf:
10554 iounmap(phba->sli4_hba.conf_regs_memmap_p);
3a487ff7 10555
da0436e9
JS
10556 return error;
10557}
10558
10559/**
10560 * lpfc_sli4_pci_mem_unset - Unset SLI4 HBA PCI memory space.
10561 * @phba: pointer to lpfc hba data structure.
10562 *
10563 * This routine is invoked to unset the PCI device memory space for device
10564 * with SLI-4 interface spec.
10565 **/
10566static void
10567lpfc_sli4_pci_mem_unset(struct lpfc_hba *phba)
10568{
2e90f4b5
JS
10569 uint32_t if_type;
10570 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
da0436e9 10571
2e90f4b5
JS
10572 switch (if_type) {
10573 case LPFC_SLI_INTF_IF_TYPE_0:
10574 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10575 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
10576 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10577 break;
10578 case LPFC_SLI_INTF_IF_TYPE_2:
10579 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10580 break;
27d6ac0a
JS
10581 case LPFC_SLI_INTF_IF_TYPE_6:
10582 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10583 iounmap(phba->sli4_hba.conf_regs_memmap_p);
0b439194
JS
10584 if (phba->sli4_hba.dpp_regs_memmap_p)
10585 iounmap(phba->sli4_hba.dpp_regs_memmap_p);
27d6ac0a 10586 break;
2e90f4b5
JS
10587 case LPFC_SLI_INTF_IF_TYPE_1:
10588 default:
10589 dev_printk(KERN_ERR, &phba->pcidev->dev,
10590 "FATAL - unsupported SLI4 interface type - %d\n",
10591 if_type);
10592 break;
10593 }
da0436e9
JS
10594}
10595
10596/**
10597 * lpfc_sli_enable_msix - Enable MSI-X interrupt mode on SLI-3 device
10598 * @phba: pointer to lpfc hba data structure.
10599 *
10600 * This routine is invoked to enable the MSI-X interrupt vectors to device
45ffac19 10601 * with SLI-3 interface specs.
da0436e9
JS
10602 *
10603 * Return codes
af901ca1 10604 * 0 - successful
da0436e9
JS
10605 * other values - error
10606 **/
10607static int
10608lpfc_sli_enable_msix(struct lpfc_hba *phba)
10609{
45ffac19 10610 int rc;
da0436e9
JS
10611 LPFC_MBOXQ_t *pmb;
10612
10613 /* Set up MSI-X multi-message vectors */
45ffac19
CH
10614 rc = pci_alloc_irq_vectors(phba->pcidev,
10615 LPFC_MSIX_VECTORS, LPFC_MSIX_VECTORS, PCI_IRQ_MSIX);
10616 if (rc < 0) {
da0436e9
JS
10617 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10618 "0420 PCI enable MSI-X failed (%d)\n", rc);
029165ac 10619 goto vec_fail_out;
da0436e9 10620 }
45ffac19 10621
da0436e9
JS
10622 /*
10623 * Assign MSI-X vectors to interrupt handlers
10624 */
10625
10626 /* vector-0 is associated to slow-path handler */
45ffac19 10627 rc = request_irq(pci_irq_vector(phba->pcidev, 0),
ed243d37 10628 &lpfc_sli_sp_intr_handler, 0,
da0436e9
JS
10629 LPFC_SP_DRIVER_HANDLER_NAME, phba);
10630 if (rc) {
10631 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10632 "0421 MSI-X slow-path request_irq failed "
10633 "(%d)\n", rc);
10634 goto msi_fail_out;
10635 }
10636
10637 /* vector-1 is associated to fast-path handler */
45ffac19 10638 rc = request_irq(pci_irq_vector(phba->pcidev, 1),
ed243d37 10639 &lpfc_sli_fp_intr_handler, 0,
da0436e9
JS
10640 LPFC_FP_DRIVER_HANDLER_NAME, phba);
10641
10642 if (rc) {
10643 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10644 "0429 MSI-X fast-path request_irq failed "
10645 "(%d)\n", rc);
10646 goto irq_fail_out;
10647 }
10648
10649 /*
10650 * Configure HBA MSI-X attention conditions to messages
10651 */
10652 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
10653
10654 if (!pmb) {
10655 rc = -ENOMEM;
372c187b 10656 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
10657 "0474 Unable to allocate memory for issuing "
10658 "MBOX_CONFIG_MSI command\n");
10659 goto mem_fail_out;
10660 }
10661 rc = lpfc_config_msi(phba, pmb);
10662 if (rc)
10663 goto mbx_fail_out;
10664 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
10665 if (rc != MBX_SUCCESS) {
10666 lpfc_printf_log(phba, KERN_WARNING, LOG_MBOX,
10667 "0351 Config MSI mailbox command failed, "
10668 "mbxCmd x%x, mbxStatus x%x\n",
10669 pmb->u.mb.mbxCommand, pmb->u.mb.mbxStatus);
10670 goto mbx_fail_out;
10671 }
10672
10673 /* Free memory allocated for mailbox command */
10674 mempool_free(pmb, phba->mbox_mem_pool);
10675 return rc;
10676
10677mbx_fail_out:
10678 /* Free memory allocated for mailbox command */
10679 mempool_free(pmb, phba->mbox_mem_pool);
10680
10681mem_fail_out:
10682 /* free the irq already requested */
45ffac19 10683 free_irq(pci_irq_vector(phba->pcidev, 1), phba);
da0436e9
JS
10684
10685irq_fail_out:
10686 /* free the irq already requested */
45ffac19 10687 free_irq(pci_irq_vector(phba->pcidev, 0), phba);
da0436e9
JS
10688
10689msi_fail_out:
10690 /* Unconfigure MSI-X capability structure */
45ffac19 10691 pci_free_irq_vectors(phba->pcidev);
029165ac
AG
10692
10693vec_fail_out:
da0436e9
JS
10694 return rc;
10695}
10696
da0436e9
JS
10697/**
10698 * lpfc_sli_enable_msi - Enable MSI interrupt mode on SLI-3 device.
10699 * @phba: pointer to lpfc hba data structure.
10700 *
10701 * This routine is invoked to enable the MSI interrupt mode to device with
10702 * SLI-3 interface spec. The kernel function pci_enable_msi() is called to
10703 * enable the MSI vector. The device driver is responsible for calling the
10704 * request_irq() to register MSI vector with a interrupt the handler, which
10705 * is done in this function.
10706 *
10707 * Return codes
af901ca1 10708 * 0 - successful
da0436e9
JS
10709 * other values - error
10710 */
10711static int
10712lpfc_sli_enable_msi(struct lpfc_hba *phba)
10713{
10714 int rc;
10715
10716 rc = pci_enable_msi(phba->pcidev);
10717 if (!rc)
10718 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10719 "0462 PCI enable MSI mode success.\n");
10720 else {
10721 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10722 "0471 PCI enable MSI mode failed (%d)\n", rc);
10723 return rc;
10724 }
10725
10726 rc = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
ed243d37 10727 0, LPFC_DRIVER_NAME, phba);
da0436e9
JS
10728 if (rc) {
10729 pci_disable_msi(phba->pcidev);
10730 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10731 "0478 MSI request_irq failed (%d)\n", rc);
10732 }
10733 return rc;
10734}
10735
da0436e9
JS
10736/**
10737 * lpfc_sli_enable_intr - Enable device interrupt to SLI-3 device.
10738 * @phba: pointer to lpfc hba data structure.
fe614acd 10739 * @cfg_mode: Interrupt configuration mode (INTx, MSI or MSI-X).
da0436e9
JS
10740 *
10741 * This routine is invoked to enable device interrupt and associate driver's
10742 * interrupt handler(s) to interrupt vector(s) to device with SLI-3 interface
10743 * spec. Depends on the interrupt mode configured to the driver, the driver
10744 * will try to fallback from the configured interrupt mode to an interrupt
10745 * mode which is supported by the platform, kernel, and device in the order
10746 * of:
10747 * MSI-X -> MSI -> IRQ.
10748 *
10749 * Return codes
af901ca1 10750 * 0 - successful
da0436e9
JS
10751 * other values - error
10752 **/
10753static uint32_t
10754lpfc_sli_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
10755{
10756 uint32_t intr_mode = LPFC_INTR_ERROR;
10757 int retval;
10758
10759 if (cfg_mode == 2) {
10760 /* Need to issue conf_port mbox cmd before conf_msi mbox cmd */
10761 retval = lpfc_sli_config_port(phba, LPFC_SLI_REV3);
10762 if (!retval) {
10763 /* Now, try to enable MSI-X interrupt mode */
10764 retval = lpfc_sli_enable_msix(phba);
10765 if (!retval) {
10766 /* Indicate initialization to MSI-X mode */
10767 phba->intr_type = MSIX;
10768 intr_mode = 2;
10769 }
10770 }
10771 }
10772
10773 /* Fallback to MSI if MSI-X initialization failed */
10774 if (cfg_mode >= 1 && phba->intr_type == NONE) {
10775 retval = lpfc_sli_enable_msi(phba);
10776 if (!retval) {
10777 /* Indicate initialization to MSI mode */
10778 phba->intr_type = MSI;
10779 intr_mode = 1;
10780 }
10781 }
10782
10783 /* Fallback to INTx if both MSI-X/MSI initalization failed */
10784 if (phba->intr_type == NONE) {
10785 retval = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
10786 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
10787 if (!retval) {
10788 /* Indicate initialization to INTx mode */
10789 phba->intr_type = INTx;
10790 intr_mode = 0;
10791 }
10792 }
10793 return intr_mode;
10794}
10795
10796/**
10797 * lpfc_sli_disable_intr - Disable device interrupt to SLI-3 device.
10798 * @phba: pointer to lpfc hba data structure.
10799 *
10800 * This routine is invoked to disable device interrupt and disassociate the
10801 * driver's interrupt handler(s) from interrupt vector(s) to device with
10802 * SLI-3 interface spec. Depending on the interrupt mode, the driver will
10803 * release the interrupt vector(s) for the message signaled interrupt.
10804 **/
10805static void
10806lpfc_sli_disable_intr(struct lpfc_hba *phba)
10807{
45ffac19
CH
10808 int nr_irqs, i;
10809
da0436e9 10810 if (phba->intr_type == MSIX)
45ffac19
CH
10811 nr_irqs = LPFC_MSIX_VECTORS;
10812 else
10813 nr_irqs = 1;
10814
10815 for (i = 0; i < nr_irqs; i++)
10816 free_irq(pci_irq_vector(phba->pcidev, i), phba);
10817 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
10818
10819 /* Reset interrupt management states */
10820 phba->intr_type = NONE;
10821 phba->sli.slistat.sli_intr = 0;
da0436e9
JS
10822}
10823
6a828b0f 10824/**
657add4e 10825 * lpfc_find_cpu_handle - Find the CPU that corresponds to the specified Queue
6a828b0f
JS
10826 * @phba: pointer to lpfc hba data structure.
10827 * @id: EQ vector index or Hardware Queue index
10828 * @match: LPFC_FIND_BY_EQ = match by EQ
10829 * LPFC_FIND_BY_HDWQ = match by Hardware Queue
657add4e 10830 * Return the CPU that matches the selection criteria
6a828b0f
JS
10831 */
10832static uint16_t
10833lpfc_find_cpu_handle(struct lpfc_hba *phba, uint16_t id, int match)
10834{
10835 struct lpfc_vector_map_info *cpup;
10836 int cpu;
10837
657add4e 10838 /* Loop through all CPUs */
222e9239
JS
10839 for_each_present_cpu(cpu) {
10840 cpup = &phba->sli4_hba.cpu_map[cpu];
657add4e
JS
10841
10842 /* If we are matching by EQ, there may be multiple CPUs using
10843 * using the same vector, so select the one with
10844 * LPFC_CPU_FIRST_IRQ set.
10845 */
6a828b0f 10846 if ((match == LPFC_FIND_BY_EQ) &&
657add4e 10847 (cpup->flag & LPFC_CPU_FIRST_IRQ) &&
6a828b0f
JS
10848 (cpup->eq == id))
10849 return cpu;
657add4e
JS
10850
10851 /* If matching by HDWQ, select the first CPU that matches */
6a828b0f
JS
10852 if ((match == LPFC_FIND_BY_HDWQ) && (cpup->hdwq == id))
10853 return cpu;
6a828b0f
JS
10854 }
10855 return 0;
10856}
10857
6a828b0f
JS
10858#ifdef CONFIG_X86
10859/**
10860 * lpfc_find_hyper - Determine if the CPU map entry is hyper-threaded
10861 * @phba: pointer to lpfc hba data structure.
10862 * @cpu: CPU map index
10863 * @phys_id: CPU package physical id
10864 * @core_id: CPU core id
10865 */
10866static int
10867lpfc_find_hyper(struct lpfc_hba *phba, int cpu,
10868 uint16_t phys_id, uint16_t core_id)
10869{
10870 struct lpfc_vector_map_info *cpup;
10871 int idx;
10872
222e9239
JS
10873 for_each_present_cpu(idx) {
10874 cpup = &phba->sli4_hba.cpu_map[idx];
6a828b0f
JS
10875 /* Does the cpup match the one we are looking for */
10876 if ((cpup->phys_id == phys_id) &&
10877 (cpup->core_id == core_id) &&
222e9239 10878 (cpu != idx))
6a828b0f 10879 return 1;
6a828b0f
JS
10880 }
10881 return 0;
10882}
10883#endif
10884
dcaa2136
JS
10885/*
10886 * lpfc_assign_eq_map_info - Assigns eq for vector_map structure
10887 * @phba: pointer to lpfc hba data structure.
10888 * @eqidx: index for eq and irq vector
10889 * @flag: flags to set for vector_map structure
10890 * @cpu: cpu used to index vector_map structure
10891 *
10892 * The routine assigns eq info into vector_map structure
10893 */
10894static inline void
10895lpfc_assign_eq_map_info(struct lpfc_hba *phba, uint16_t eqidx, uint16_t flag,
10896 unsigned int cpu)
10897{
10898 struct lpfc_vector_map_info *cpup = &phba->sli4_hba.cpu_map[cpu];
10899 struct lpfc_hba_eq_hdl *eqhdl = lpfc_get_eq_hdl(eqidx);
10900
10901 cpup->eq = eqidx;
10902 cpup->flag |= flag;
10903
10904 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10905 "3336 Set Affinity: CPU %d irq %d eq %d flag x%x\n",
10906 cpu, eqhdl->irq, cpup->eq, cpup->flag);
10907}
10908
10909/**
10910 * lpfc_cpu_map_array_init - Initialize cpu_map structure
10911 * @phba: pointer to lpfc hba data structure.
10912 *
10913 * The routine initializes the cpu_map array structure
10914 */
10915static void
10916lpfc_cpu_map_array_init(struct lpfc_hba *phba)
10917{
10918 struct lpfc_vector_map_info *cpup;
10919 struct lpfc_eq_intr_info *eqi;
10920 int cpu;
10921
10922 for_each_possible_cpu(cpu) {
10923 cpup = &phba->sli4_hba.cpu_map[cpu];
10924 cpup->phys_id = LPFC_VECTOR_MAP_EMPTY;
10925 cpup->core_id = LPFC_VECTOR_MAP_EMPTY;
10926 cpup->hdwq = LPFC_VECTOR_MAP_EMPTY;
10927 cpup->eq = LPFC_VECTOR_MAP_EMPTY;
10928 cpup->flag = 0;
10929 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, cpu);
10930 INIT_LIST_HEAD(&eqi->list);
10931 eqi->icnt = 0;
10932 }
10933}
10934
10935/**
10936 * lpfc_hba_eq_hdl_array_init - Initialize hba_eq_hdl structure
10937 * @phba: pointer to lpfc hba data structure.
10938 *
10939 * The routine initializes the hba_eq_hdl array structure
10940 */
10941static void
10942lpfc_hba_eq_hdl_array_init(struct lpfc_hba *phba)
10943{
10944 struct lpfc_hba_eq_hdl *eqhdl;
10945 int i;
10946
10947 for (i = 0; i < phba->cfg_irq_chann; i++) {
10948 eqhdl = lpfc_get_eq_hdl(i);
10949 eqhdl->irq = LPFC_VECTOR_MAP_EMPTY;
10950 eqhdl->phba = phba;
10951 }
10952}
10953
7bb03bbf 10954/**
895427bd 10955 * lpfc_cpu_affinity_check - Check vector CPU affinity mappings
7bb03bbf 10956 * @phba: pointer to lpfc hba data structure.
895427bd
JS
10957 * @vectors: number of msix vectors allocated.
10958 *
10959 * The routine will figure out the CPU affinity assignment for every
6a828b0f 10960 * MSI-X vector allocated for the HBA.
895427bd
JS
10961 * In addition, the CPU to IO channel mapping will be calculated
10962 * and the phba->sli4_hba.cpu_map array will reflect this.
7bb03bbf 10963 */
895427bd
JS
10964static void
10965lpfc_cpu_affinity_check(struct lpfc_hba *phba, int vectors)
7bb03bbf 10966{
3ad348d9 10967 int i, cpu, idx, next_idx, new_cpu, start_cpu, first_cpu;
6a828b0f
JS
10968 int max_phys_id, min_phys_id;
10969 int max_core_id, min_core_id;
7bb03bbf 10970 struct lpfc_vector_map_info *cpup;
d9954a2d 10971 struct lpfc_vector_map_info *new_cpup;
7bb03bbf
JS
10972#ifdef CONFIG_X86
10973 struct cpuinfo_x86 *cpuinfo;
10974#endif
840eda96
JS
10975#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
10976 struct lpfc_hdwq_stat *c_stat;
10977#endif
7bb03bbf 10978
6a828b0f 10979 max_phys_id = 0;
d9954a2d 10980 min_phys_id = LPFC_VECTOR_MAP_EMPTY;
6a828b0f 10981 max_core_id = 0;
d9954a2d 10982 min_core_id = LPFC_VECTOR_MAP_EMPTY;
7bb03bbf
JS
10983
10984 /* Update CPU map with physical id and core id of each CPU */
222e9239
JS
10985 for_each_present_cpu(cpu) {
10986 cpup = &phba->sli4_hba.cpu_map[cpu];
7bb03bbf
JS
10987#ifdef CONFIG_X86
10988 cpuinfo = &cpu_data(cpu);
10989 cpup->phys_id = cpuinfo->phys_proc_id;
10990 cpup->core_id = cpuinfo->cpu_core_id;
d9954a2d
JS
10991 if (lpfc_find_hyper(phba, cpu, cpup->phys_id, cpup->core_id))
10992 cpup->flag |= LPFC_CPU_MAP_HYPER;
7bb03bbf
JS
10993#else
10994 /* No distinction between CPUs for other platforms */
10995 cpup->phys_id = 0;
6a828b0f 10996 cpup->core_id = cpu;
7bb03bbf 10997#endif
6a828b0f 10998
b3295c2a 10999 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3ad348d9
JS
11000 "3328 CPU %d physid %d coreid %d flag x%x\n",
11001 cpu, cpup->phys_id, cpup->core_id, cpup->flag);
6a828b0f
JS
11002
11003 if (cpup->phys_id > max_phys_id)
11004 max_phys_id = cpup->phys_id;
11005 if (cpup->phys_id < min_phys_id)
11006 min_phys_id = cpup->phys_id;
11007
11008 if (cpup->core_id > max_core_id)
11009 max_core_id = cpup->core_id;
11010 if (cpup->core_id < min_core_id)
11011 min_core_id = cpup->core_id;
7bb03bbf 11012 }
7bb03bbf 11013
d9954a2d
JS
11014 /* After looking at each irq vector assigned to this pcidev, its
11015 * possible to see that not ALL CPUs have been accounted for.
657add4e
JS
11016 * Next we will set any unassigned (unaffinitized) cpu map
11017 * entries to a IRQ on the same phys_id.
d9954a2d
JS
11018 */
11019 first_cpu = cpumask_first(cpu_present_mask);
11020 start_cpu = first_cpu;
11021
11022 for_each_present_cpu(cpu) {
11023 cpup = &phba->sli4_hba.cpu_map[cpu];
11024
11025 /* Is this CPU entry unassigned */
11026 if (cpup->eq == LPFC_VECTOR_MAP_EMPTY) {
11027 /* Mark CPU as IRQ not assigned by the kernel */
11028 cpup->flag |= LPFC_CPU_MAP_UNASSIGN;
11029
657add4e 11030 /* If so, find a new_cpup thats on the the SAME
d9954a2d
JS
11031 * phys_id as cpup. start_cpu will start where we
11032 * left off so all unassigned entries don't get assgined
11033 * the IRQ of the first entry.
11034 */
11035 new_cpu = start_cpu;
11036 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
11037 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
11038 if (!(new_cpup->flag & LPFC_CPU_MAP_UNASSIGN) &&
dcaa2136 11039 (new_cpup->eq != LPFC_VECTOR_MAP_EMPTY) &&
d9954a2d
JS
11040 (new_cpup->phys_id == cpup->phys_id))
11041 goto found_same;
11042 new_cpu = cpumask_next(
11043 new_cpu, cpu_present_mask);
11044 if (new_cpu == nr_cpumask_bits)
11045 new_cpu = first_cpu;
11046 }
11047 /* At this point, we leave the CPU as unassigned */
11048 continue;
11049found_same:
11050 /* We found a matching phys_id, so copy the IRQ info */
11051 cpup->eq = new_cpup->eq;
d9954a2d
JS
11052
11053 /* Bump start_cpu to the next slot to minmize the
11054 * chance of having multiple unassigned CPU entries
11055 * selecting the same IRQ.
11056 */
11057 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
11058 if (start_cpu == nr_cpumask_bits)
11059 start_cpu = first_cpu;
11060
657add4e 11061 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
d9954a2d 11062 "3337 Set Affinity: CPU %d "
dcaa2136 11063 "eq %d from peer cpu %d same "
d9954a2d 11064 "phys_id (%d)\n",
dcaa2136
JS
11065 cpu, cpup->eq, new_cpu,
11066 cpup->phys_id);
d9954a2d
JS
11067 }
11068 }
11069
11070 /* Set any unassigned cpu map entries to a IRQ on any phys_id */
11071 start_cpu = first_cpu;
11072
11073 for_each_present_cpu(cpu) {
11074 cpup = &phba->sli4_hba.cpu_map[cpu];
11075
11076 /* Is this entry unassigned */
11077 if (cpup->eq == LPFC_VECTOR_MAP_EMPTY) {
11078 /* Mark it as IRQ not assigned by the kernel */
11079 cpup->flag |= LPFC_CPU_MAP_UNASSIGN;
11080
657add4e 11081 /* If so, find a new_cpup thats on ANY phys_id
d9954a2d
JS
11082 * as the cpup. start_cpu will start where we
11083 * left off so all unassigned entries don't get
11084 * assigned the IRQ of the first entry.
11085 */
11086 new_cpu = start_cpu;
11087 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
11088 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
11089 if (!(new_cpup->flag & LPFC_CPU_MAP_UNASSIGN) &&
dcaa2136 11090 (new_cpup->eq != LPFC_VECTOR_MAP_EMPTY))
d9954a2d
JS
11091 goto found_any;
11092 new_cpu = cpumask_next(
11093 new_cpu, cpu_present_mask);
11094 if (new_cpu == nr_cpumask_bits)
11095 new_cpu = first_cpu;
11096 }
11097 /* We should never leave an entry unassigned */
11098 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11099 "3339 Set Affinity: CPU %d "
dcaa2136
JS
11100 "eq %d UNASSIGNED\n",
11101 cpup->hdwq, cpup->eq);
d9954a2d
JS
11102 continue;
11103found_any:
11104 /* We found an available entry, copy the IRQ info */
11105 cpup->eq = new_cpup->eq;
d9954a2d
JS
11106
11107 /* Bump start_cpu to the next slot to minmize the
11108 * chance of having multiple unassigned CPU entries
11109 * selecting the same IRQ.
11110 */
11111 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
11112 if (start_cpu == nr_cpumask_bits)
11113 start_cpu = first_cpu;
11114
657add4e 11115 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
d9954a2d 11116 "3338 Set Affinity: CPU %d "
dcaa2136
JS
11117 "eq %d from peer cpu %d (%d/%d)\n",
11118 cpu, cpup->eq, new_cpu,
d9954a2d
JS
11119 new_cpup->phys_id, new_cpup->core_id);
11120 }
11121 }
657add4e 11122
3ad348d9
JS
11123 /* Assign hdwq indices that are unique across all cpus in the map
11124 * that are also FIRST_CPUs.
11125 */
11126 idx = 0;
11127 for_each_present_cpu(cpu) {
11128 cpup = &phba->sli4_hba.cpu_map[cpu];
11129
11130 /* Only FIRST IRQs get a hdwq index assignment. */
11131 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
11132 continue;
11133
11134 /* 1 to 1, the first LPFC_CPU_FIRST_IRQ cpus to a unique hdwq */
11135 cpup->hdwq = idx;
11136 idx++;
bc2736e9 11137 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3ad348d9 11138 "3333 Set Affinity: CPU %d (phys %d core %d): "
dcaa2136 11139 "hdwq %d eq %d flg x%x\n",
3ad348d9 11140 cpu, cpup->phys_id, cpup->core_id,
dcaa2136 11141 cpup->hdwq, cpup->eq, cpup->flag);
3ad348d9 11142 }
bc227dde 11143 /* Associate a hdwq with each cpu_map entry
657add4e
JS
11144 * This will be 1 to 1 - hdwq to cpu, unless there are less
11145 * hardware queues then CPUs. For that case we will just round-robin
11146 * the available hardware queues as they get assigned to CPUs.
3ad348d9
JS
11147 * The next_idx is the idx from the FIRST_CPU loop above to account
11148 * for irq_chann < hdwq. The idx is used for round-robin assignments
11149 * and needs to start at 0.
657add4e 11150 */
3ad348d9 11151 next_idx = idx;
657add4e 11152 start_cpu = 0;
3ad348d9 11153 idx = 0;
657add4e
JS
11154 for_each_present_cpu(cpu) {
11155 cpup = &phba->sli4_hba.cpu_map[cpu];
657add4e 11156
3ad348d9
JS
11157 /* FIRST cpus are already mapped. */
11158 if (cpup->flag & LPFC_CPU_FIRST_IRQ)
11159 continue;
11160
11161 /* If the cfg_irq_chann < cfg_hdw_queue, set the hdwq
11162 * of the unassigned cpus to the next idx so that all
11163 * hdw queues are fully utilized.
11164 */
11165 if (next_idx < phba->cfg_hdw_queue) {
11166 cpup->hdwq = next_idx;
11167 next_idx++;
11168 continue;
11169 }
11170
11171 /* Not a First CPU and all hdw_queues are used. Reuse a
11172 * Hardware Queue for another CPU, so be smart about it
11173 * and pick one that has its IRQ/EQ mapped to the same phys_id
11174 * (CPU package) and core_id.
11175 */
11176 new_cpu = start_cpu;
11177 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
11178 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
11179 if (new_cpup->hdwq != LPFC_VECTOR_MAP_EMPTY &&
11180 new_cpup->phys_id == cpup->phys_id &&
11181 new_cpup->core_id == cpup->core_id) {
11182 goto found_hdwq;
657add4e 11183 }
3ad348d9
JS
11184 new_cpu = cpumask_next(new_cpu, cpu_present_mask);
11185 if (new_cpu == nr_cpumask_bits)
11186 new_cpu = first_cpu;
11187 }
657add4e 11188
3ad348d9
JS
11189 /* If we can't match both phys_id and core_id,
11190 * settle for just a phys_id match.
11191 */
11192 new_cpu = start_cpu;
11193 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
11194 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
11195 if (new_cpup->hdwq != LPFC_VECTOR_MAP_EMPTY &&
11196 new_cpup->phys_id == cpup->phys_id)
11197 goto found_hdwq;
11198
11199 new_cpu = cpumask_next(new_cpu, cpu_present_mask);
11200 if (new_cpu == nr_cpumask_bits)
11201 new_cpu = first_cpu;
657add4e 11202 }
3ad348d9
JS
11203
11204 /* Otherwise just round robin on cfg_hdw_queue */
11205 cpup->hdwq = idx % phba->cfg_hdw_queue;
11206 idx++;
11207 goto logit;
11208 found_hdwq:
11209 /* We found an available entry, copy the IRQ info */
11210 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
11211 if (start_cpu == nr_cpumask_bits)
11212 start_cpu = first_cpu;
11213 cpup->hdwq = new_cpup->hdwq;
11214 logit:
bc2736e9 11215 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
657add4e 11216 "3335 Set Affinity: CPU %d (phys %d core %d): "
dcaa2136 11217 "hdwq %d eq %d flg x%x\n",
657add4e 11218 cpu, cpup->phys_id, cpup->core_id,
dcaa2136 11219 cpup->hdwq, cpup->eq, cpup->flag);
657add4e
JS
11220 }
11221
bc227dde
JS
11222 /*
11223 * Initialize the cpu_map slots for not-present cpus in case
11224 * a cpu is hot-added. Perform a simple hdwq round robin assignment.
11225 */
11226 idx = 0;
11227 for_each_possible_cpu(cpu) {
11228 cpup = &phba->sli4_hba.cpu_map[cpu];
840eda96
JS
11229#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
11230 c_stat = per_cpu_ptr(phba->sli4_hba.c_stat, cpu);
11231 c_stat->hdwq_no = cpup->hdwq;
11232#endif
bc227dde
JS
11233 if (cpup->hdwq != LPFC_VECTOR_MAP_EMPTY)
11234 continue;
11235
11236 cpup->hdwq = idx++ % phba->cfg_hdw_queue;
840eda96
JS
11237#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
11238 c_stat->hdwq_no = cpup->hdwq;
11239#endif
bc227dde
JS
11240 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11241 "3340 Set Affinity: not present "
11242 "CPU %d hdwq %d\n",
11243 cpu, cpup->hdwq);
657add4e
JS
11244 }
11245
11246 /* The cpu_map array will be used later during initialization
11247 * when EQ / CQ / WQs are allocated and configured.
11248 */
b3295c2a 11249 return;
7bb03bbf 11250}
7bb03bbf 11251
93a4d6f4
JS
11252/**
11253 * lpfc_cpuhp_get_eq
11254 *
11255 * @phba: pointer to lpfc hba data structure.
11256 * @cpu: cpu going offline
fe614acd 11257 * @eqlist: eq list to append to
93a4d6f4 11258 */
a99c8074 11259static int
93a4d6f4
JS
11260lpfc_cpuhp_get_eq(struct lpfc_hba *phba, unsigned int cpu,
11261 struct list_head *eqlist)
11262{
93a4d6f4
JS
11263 const struct cpumask *maskp;
11264 struct lpfc_queue *eq;
a99c8074 11265 struct cpumask *tmp;
93a4d6f4
JS
11266 u16 idx;
11267
a99c8074
JS
11268 tmp = kzalloc(cpumask_size(), GFP_KERNEL);
11269 if (!tmp)
11270 return -ENOMEM;
11271
93a4d6f4
JS
11272 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
11273 maskp = pci_irq_get_affinity(phba->pcidev, idx);
11274 if (!maskp)
11275 continue;
11276 /*
11277 * if irq is not affinitized to the cpu going
11278 * then we don't need to poll the eq attached
11279 * to it.
11280 */
a99c8074 11281 if (!cpumask_and(tmp, maskp, cpumask_of(cpu)))
93a4d6f4
JS
11282 continue;
11283 /* get the cpus that are online and are affini-
11284 * tized to this irq vector. If the count is
11285 * more than 1 then cpuhp is not going to shut-
11286 * down this vector. Since this cpu has not
11287 * gone offline yet, we need >1.
11288 */
a99c8074
JS
11289 cpumask_and(tmp, maskp, cpu_online_mask);
11290 if (cpumask_weight(tmp) > 1)
93a4d6f4
JS
11291 continue;
11292
11293 /* Now that we have an irq to shutdown, get the eq
11294 * mapped to this irq. Note: multiple hdwq's in
11295 * the software can share an eq, but eventually
11296 * only eq will be mapped to this vector
11297 */
dcaa2136
JS
11298 eq = phba->sli4_hba.hba_eq_hdl[idx].eq;
11299 list_add(&eq->_poll_list, eqlist);
93a4d6f4 11300 }
a99c8074
JS
11301 kfree(tmp);
11302 return 0;
93a4d6f4
JS
11303}
11304
11305static void __lpfc_cpuhp_remove(struct lpfc_hba *phba)
11306{
11307 if (phba->sli_rev != LPFC_SLI_REV4)
11308 return;
11309
11310 cpuhp_state_remove_instance_nocalls(lpfc_cpuhp_state,
11311 &phba->cpuhp);
11312 /*
11313 * unregistering the instance doesn't stop the polling
11314 * timer. Wait for the poll timer to retire.
11315 */
11316 synchronize_rcu();
11317 del_timer_sync(&phba->cpuhp_poll_timer);
11318}
11319
11320static void lpfc_cpuhp_remove(struct lpfc_hba *phba)
11321{
11322 if (phba->pport->fc_flag & FC_OFFLINE_MODE)
11323 return;
11324
11325 __lpfc_cpuhp_remove(phba);
11326}
11327
11328static void lpfc_cpuhp_add(struct lpfc_hba *phba)
11329{
11330 if (phba->sli_rev != LPFC_SLI_REV4)
11331 return;
11332
11333 rcu_read_lock();
11334
f861f596 11335 if (!list_empty(&phba->poll_list))
93a4d6f4
JS
11336 mod_timer(&phba->cpuhp_poll_timer,
11337 jiffies + msecs_to_jiffies(LPFC_POLL_HB));
93a4d6f4
JS
11338
11339 rcu_read_unlock();
11340
11341 cpuhp_state_add_instance_nocalls(lpfc_cpuhp_state,
11342 &phba->cpuhp);
11343}
11344
11345static int __lpfc_cpuhp_checks(struct lpfc_hba *phba, int *retval)
11346{
11347 if (phba->pport->load_flag & FC_UNLOADING) {
11348 *retval = -EAGAIN;
11349 return true;
11350 }
11351
11352 if (phba->sli_rev != LPFC_SLI_REV4) {
11353 *retval = 0;
11354 return true;
11355 }
11356
11357 /* proceed with the hotplug */
11358 return false;
11359}
11360
dcaa2136
JS
11361/**
11362 * lpfc_irq_set_aff - set IRQ affinity
11363 * @eqhdl: EQ handle
11364 * @cpu: cpu to set affinity
11365 *
11366 **/
11367static inline void
11368lpfc_irq_set_aff(struct lpfc_hba_eq_hdl *eqhdl, unsigned int cpu)
11369{
11370 cpumask_clear(&eqhdl->aff_mask);
11371 cpumask_set_cpu(cpu, &eqhdl->aff_mask);
11372 irq_set_status_flags(eqhdl->irq, IRQ_NO_BALANCING);
11373 irq_set_affinity_hint(eqhdl->irq, &eqhdl->aff_mask);
11374}
11375
11376/**
11377 * lpfc_irq_clear_aff - clear IRQ affinity
11378 * @eqhdl: EQ handle
11379 *
11380 **/
11381static inline void
11382lpfc_irq_clear_aff(struct lpfc_hba_eq_hdl *eqhdl)
11383{
11384 cpumask_clear(&eqhdl->aff_mask);
11385 irq_clear_status_flags(eqhdl->irq, IRQ_NO_BALANCING);
dcaa2136
JS
11386}
11387
11388/**
11389 * lpfc_irq_rebalance - rebalances IRQ affinity according to cpuhp event
11390 * @phba: pointer to HBA context object.
11391 * @cpu: cpu going offline/online
11392 * @offline: true, cpu is going offline. false, cpu is coming online.
11393 *
11394 * If cpu is going offline, we'll try our best effort to find the next
3048e3e8
DK
11395 * online cpu on the phba's original_mask and migrate all offlining IRQ
11396 * affinities.
dcaa2136 11397 *
3048e3e8 11398 * If cpu is coming online, reaffinitize the IRQ back to the onlining cpu.
dcaa2136 11399 *
3048e3e8 11400 * Note: Call only if NUMA or NHT mode is enabled, otherwise rely on
dcaa2136
JS
11401 * PCI_IRQ_AFFINITY to auto-manage IRQ affinity.
11402 *
11403 **/
11404static void
11405lpfc_irq_rebalance(struct lpfc_hba *phba, unsigned int cpu, bool offline)
11406{
11407 struct lpfc_vector_map_info *cpup;
11408 struct cpumask *aff_mask;
11409 unsigned int cpu_select, cpu_next, idx;
3048e3e8 11410 const struct cpumask *orig_mask;
dcaa2136 11411
3048e3e8 11412 if (phba->irq_chann_mode == NORMAL_MODE)
dcaa2136
JS
11413 return;
11414
3048e3e8 11415 orig_mask = &phba->sli4_hba.irq_aff_mask;
dcaa2136 11416
3048e3e8 11417 if (!cpumask_test_cpu(cpu, orig_mask))
dcaa2136
JS
11418 return;
11419
11420 cpup = &phba->sli4_hba.cpu_map[cpu];
11421
11422 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
11423 return;
11424
11425 if (offline) {
3048e3e8
DK
11426 /* Find next online CPU on original mask */
11427 cpu_next = cpumask_next_wrap(cpu, orig_mask, cpu, true);
11428 cpu_select = lpfc_next_online_cpu(orig_mask, cpu_next);
dcaa2136
JS
11429
11430 /* Found a valid CPU */
11431 if ((cpu_select < nr_cpu_ids) && (cpu_select != cpu)) {
11432 /* Go through each eqhdl and ensure offlining
11433 * cpu aff_mask is migrated
11434 */
11435 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
11436 aff_mask = lpfc_get_aff_mask(idx);
11437
11438 /* Migrate affinity */
11439 if (cpumask_test_cpu(cpu, aff_mask))
11440 lpfc_irq_set_aff(lpfc_get_eq_hdl(idx),
11441 cpu_select);
11442 }
11443 } else {
11444 /* Rely on irqbalance if no online CPUs left on NUMA */
11445 for (idx = 0; idx < phba->cfg_irq_chann; idx++)
11446 lpfc_irq_clear_aff(lpfc_get_eq_hdl(idx));
11447 }
11448 } else {
11449 /* Migrate affinity back to this CPU */
11450 lpfc_irq_set_aff(lpfc_get_eq_hdl(cpup->eq), cpu);
11451 }
11452}
11453
93a4d6f4
JS
11454static int lpfc_cpu_offline(unsigned int cpu, struct hlist_node *node)
11455{
11456 struct lpfc_hba *phba = hlist_entry_safe(node, struct lpfc_hba, cpuhp);
11457 struct lpfc_queue *eq, *next;
11458 LIST_HEAD(eqlist);
11459 int retval;
11460
11461 if (!phba) {
11462 WARN_ONCE(!phba, "cpu: %u. phba:NULL", raw_smp_processor_id());
11463 return 0;
11464 }
11465
11466 if (__lpfc_cpuhp_checks(phba, &retval))
11467 return retval;
11468
dcaa2136
JS
11469 lpfc_irq_rebalance(phba, cpu, true);
11470
a99c8074
JS
11471 retval = lpfc_cpuhp_get_eq(phba, cpu, &eqlist);
11472 if (retval)
11473 return retval;
93a4d6f4
JS
11474
11475 /* start polling on these eq's */
11476 list_for_each_entry_safe(eq, next, &eqlist, _poll_list) {
11477 list_del_init(&eq->_poll_list);
11478 lpfc_sli4_start_polling(eq);
11479 }
11480
11481 return 0;
11482}
11483
11484static int lpfc_cpu_online(unsigned int cpu, struct hlist_node *node)
11485{
11486 struct lpfc_hba *phba = hlist_entry_safe(node, struct lpfc_hba, cpuhp);
11487 struct lpfc_queue *eq, *next;
11488 unsigned int n;
11489 int retval;
11490
11491 if (!phba) {
11492 WARN_ONCE(!phba, "cpu: %u. phba:NULL", raw_smp_processor_id());
11493 return 0;
11494 }
11495
11496 if (__lpfc_cpuhp_checks(phba, &retval))
11497 return retval;
11498
dcaa2136
JS
11499 lpfc_irq_rebalance(phba, cpu, false);
11500
93a4d6f4
JS
11501 list_for_each_entry_safe(eq, next, &phba->poll_list, _poll_list) {
11502 n = lpfc_find_cpu_handle(phba, eq->hdwq, LPFC_FIND_BY_HDWQ);
11503 if (n == cpu)
11504 lpfc_sli4_stop_polling(eq);
11505 }
11506
11507 return 0;
11508}
11509
da0436e9
JS
11510/**
11511 * lpfc_sli4_enable_msix - Enable MSI-X interrupt mode to SLI-4 device
11512 * @phba: pointer to lpfc hba data structure.
11513 *
11514 * This routine is invoked to enable the MSI-X interrupt vectors to device
dcaa2136
JS
11515 * with SLI-4 interface spec. It also allocates MSI-X vectors and maps them
11516 * to cpus on the system.
11517 *
11518 * When cfg_irq_numa is enabled, the adapter will only allocate vectors for
11519 * the number of cpus on the same numa node as this adapter. The vectors are
11520 * allocated without requesting OS affinity mapping. A vector will be
11521 * allocated and assigned to each online and offline cpu. If the cpu is
11522 * online, then affinity will be set to that cpu. If the cpu is offline, then
11523 * affinity will be set to the nearest peer cpu within the numa node that is
11524 * online. If there are no online cpus within the numa node, affinity is not
11525 * assigned and the OS may do as it pleases. Note: cpu vector affinity mapping
11526 * is consistent with the way cpu online/offline is handled when cfg_irq_numa is
11527 * configured.
11528 *
11529 * If numa mode is not enabled and there is more than 1 vector allocated, then
11530 * the driver relies on the managed irq interface where the OS assigns vector to
11531 * cpu affinity. The driver will then use that affinity mapping to setup its
11532 * cpu mapping table.
da0436e9
JS
11533 *
11534 * Return codes
af901ca1 11535 * 0 - successful
da0436e9
JS
11536 * other values - error
11537 **/
11538static int
11539lpfc_sli4_enable_msix(struct lpfc_hba *phba)
11540{
75baf696 11541 int vectors, rc, index;
b83d005e 11542 char *name;
3048e3e8 11543 const struct cpumask *aff_mask = NULL;
dcaa2136 11544 unsigned int cpu = 0, cpu_cnt = 0, cpu_select = nr_cpu_ids;
17105d95 11545 struct lpfc_vector_map_info *cpup;
dcaa2136
JS
11546 struct lpfc_hba_eq_hdl *eqhdl;
11547 const struct cpumask *maskp;
dcaa2136 11548 unsigned int flags = PCI_IRQ_MSIX;
da0436e9
JS
11549
11550 /* Set up MSI-X multi-message vectors */
6a828b0f 11551 vectors = phba->cfg_irq_chann;
45ffac19 11552
3048e3e8
DK
11553 if (phba->irq_chann_mode != NORMAL_MODE)
11554 aff_mask = &phba->sli4_hba.irq_aff_mask;
11555
11556 if (aff_mask) {
11557 cpu_cnt = cpumask_weight(aff_mask);
dcaa2136
JS
11558 vectors = min(phba->cfg_irq_chann, cpu_cnt);
11559
3048e3e8
DK
11560 /* cpu: iterates over aff_mask including offline or online
11561 * cpu_select: iterates over online aff_mask to set affinity
dcaa2136 11562 */
3048e3e8
DK
11563 cpu = cpumask_first(aff_mask);
11564 cpu_select = lpfc_next_online_cpu(aff_mask, cpu);
dcaa2136
JS
11565 } else {
11566 flags |= PCI_IRQ_AFFINITY;
11567 }
11568
11569 rc = pci_alloc_irq_vectors(phba->pcidev, 1, vectors, flags);
4f871e1b 11570 if (rc < 0) {
da0436e9
JS
11571 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11572 "0484 PCI enable MSI-X failed (%d)\n", rc);
029165ac 11573 goto vec_fail_out;
da0436e9 11574 }
4f871e1b 11575 vectors = rc;
75baf696 11576
7bb03bbf 11577 /* Assign MSI-X vectors to interrupt handlers */
67d12733 11578 for (index = 0; index < vectors; index++) {
dcaa2136
JS
11579 eqhdl = lpfc_get_eq_hdl(index);
11580 name = eqhdl->handler_name;
b83d005e
JS
11581 memset(name, 0, LPFC_SLI4_HANDLER_NAME_SZ);
11582 snprintf(name, LPFC_SLI4_HANDLER_NAME_SZ,
4305f183 11583 LPFC_DRIVER_HANDLER_NAME"%d", index);
da0436e9 11584
dcaa2136 11585 eqhdl->idx = index;
7370d10a
JS
11586 rc = request_irq(pci_irq_vector(phba->pcidev, index),
11587 &lpfc_sli4_hba_intr_handler, 0,
dcaa2136 11588 name, eqhdl);
da0436e9
JS
11589 if (rc) {
11590 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
11591 "0486 MSI-X fast-path (%d) "
11592 "request_irq failed (%d)\n", index, rc);
11593 goto cfg_fail_out;
11594 }
dcaa2136
JS
11595
11596 eqhdl->irq = pci_irq_vector(phba->pcidev, index);
11597
3048e3e8 11598 if (aff_mask) {
dcaa2136
JS
11599 /* If found a neighboring online cpu, set affinity */
11600 if (cpu_select < nr_cpu_ids)
11601 lpfc_irq_set_aff(eqhdl, cpu_select);
11602
11603 /* Assign EQ to cpu_map */
11604 lpfc_assign_eq_map_info(phba, index,
11605 LPFC_CPU_FIRST_IRQ,
11606 cpu);
11607
3048e3e8
DK
11608 /* Iterate to next offline or online cpu in aff_mask */
11609 cpu = cpumask_next(cpu, aff_mask);
dcaa2136 11610
3048e3e8
DK
11611 /* Find next online cpu in aff_mask to set affinity */
11612 cpu_select = lpfc_next_online_cpu(aff_mask, cpu);
dcaa2136
JS
11613 } else if (vectors == 1) {
11614 cpu = cpumask_first(cpu_present_mask);
11615 lpfc_assign_eq_map_info(phba, index, LPFC_CPU_FIRST_IRQ,
11616 cpu);
11617 } else {
11618 maskp = pci_irq_get_affinity(phba->pcidev, index);
11619
dcaa2136
JS
11620 /* Loop through all CPUs associated with vector index */
11621 for_each_cpu_and(cpu, maskp, cpu_present_mask) {
17105d95
DK
11622 cpup = &phba->sli4_hba.cpu_map[cpu];
11623
dcaa2136
JS
11624 /* If this is the first CPU thats assigned to
11625 * this vector, set LPFC_CPU_FIRST_IRQ.
17105d95
DK
11626 *
11627 * With certain platforms its possible that irq
11628 * vectors are affinitized to all the cpu's.
11629 * This can result in each cpu_map.eq to be set
11630 * to the last vector, resulting in overwrite
11631 * of all the previous cpu_map.eq. Ensure that
11632 * each vector receives a place in cpu_map.
11633 * Later call to lpfc_cpu_affinity_check will
11634 * ensure we are nicely balanced out.
dcaa2136 11635 */
17105d95
DK
11636 if (cpup->eq != LPFC_VECTOR_MAP_EMPTY)
11637 continue;
dcaa2136 11638 lpfc_assign_eq_map_info(phba, index,
17105d95 11639 LPFC_CPU_FIRST_IRQ,
dcaa2136 11640 cpu);
17105d95 11641 break;
dcaa2136
JS
11642 }
11643 }
da0436e9
JS
11644 }
11645
6a828b0f 11646 if (vectors != phba->cfg_irq_chann) {
372c187b 11647 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
82c3e9ba
JS
11648 "3238 Reducing IO channels to match number of "
11649 "MSI-X vectors, requested %d got %d\n",
6a828b0f
JS
11650 phba->cfg_irq_chann, vectors);
11651 if (phba->cfg_irq_chann > vectors)
11652 phba->cfg_irq_chann = vectors;
82c3e9ba 11653 }
7bb03bbf 11654
da0436e9
JS
11655 return rc;
11656
11657cfg_fail_out:
11658 /* free the irq already requested */
dcaa2136
JS
11659 for (--index; index >= 0; index--) {
11660 eqhdl = lpfc_get_eq_hdl(index);
11661 lpfc_irq_clear_aff(eqhdl);
11662 irq_set_affinity_hint(eqhdl->irq, NULL);
11663 free_irq(eqhdl->irq, eqhdl);
11664 }
da0436e9 11665
da0436e9 11666 /* Unconfigure MSI-X capability structure */
45ffac19 11667 pci_free_irq_vectors(phba->pcidev);
029165ac
AG
11668
11669vec_fail_out:
da0436e9
JS
11670 return rc;
11671}
11672
da0436e9
JS
11673/**
11674 * lpfc_sli4_enable_msi - Enable MSI interrupt mode to SLI-4 device
11675 * @phba: pointer to lpfc hba data structure.
11676 *
11677 * This routine is invoked to enable the MSI interrupt mode to device with
07b1b914
JS
11678 * SLI-4 interface spec. The kernel function pci_alloc_irq_vectors() is
11679 * called to enable the MSI vector. The device driver is responsible for
11680 * calling the request_irq() to register MSI vector with a interrupt the
11681 * handler, which is done in this function.
da0436e9
JS
11682 *
11683 * Return codes
af901ca1 11684 * 0 - successful
da0436e9
JS
11685 * other values - error
11686 **/
11687static int
11688lpfc_sli4_enable_msi(struct lpfc_hba *phba)
11689{
11690 int rc, index;
dcaa2136
JS
11691 unsigned int cpu;
11692 struct lpfc_hba_eq_hdl *eqhdl;
da0436e9 11693
07b1b914
JS
11694 rc = pci_alloc_irq_vectors(phba->pcidev, 1, 1,
11695 PCI_IRQ_MSI | PCI_IRQ_AFFINITY);
11696 if (rc > 0)
da0436e9
JS
11697 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11698 "0487 PCI enable MSI mode success.\n");
11699 else {
11700 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11701 "0488 PCI enable MSI mode failed (%d)\n", rc);
07b1b914 11702 return rc ? rc : -1;
da0436e9
JS
11703 }
11704
11705 rc = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
ed243d37 11706 0, LPFC_DRIVER_NAME, phba);
da0436e9 11707 if (rc) {
07b1b914 11708 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
11709 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
11710 "0490 MSI request_irq failed (%d)\n", rc);
75baf696 11711 return rc;
da0436e9
JS
11712 }
11713
dcaa2136
JS
11714 eqhdl = lpfc_get_eq_hdl(0);
11715 eqhdl->irq = pci_irq_vector(phba->pcidev, 0);
11716
11717 cpu = cpumask_first(cpu_present_mask);
11718 lpfc_assign_eq_map_info(phba, 0, LPFC_CPU_FIRST_IRQ, cpu);
11719
6a828b0f 11720 for (index = 0; index < phba->cfg_irq_chann; index++) {
dcaa2136
JS
11721 eqhdl = lpfc_get_eq_hdl(index);
11722 eqhdl->idx = index;
da0436e9
JS
11723 }
11724
75baf696 11725 return 0;
da0436e9
JS
11726}
11727
da0436e9
JS
11728/**
11729 * lpfc_sli4_enable_intr - Enable device interrupt to SLI-4 device
11730 * @phba: pointer to lpfc hba data structure.
fe614acd 11731 * @cfg_mode: Interrupt configuration mode (INTx, MSI or MSI-X).
da0436e9
JS
11732 *
11733 * This routine is invoked to enable device interrupt and associate driver's
11734 * interrupt handler(s) to interrupt vector(s) to device with SLI-4
11735 * interface spec. Depends on the interrupt mode configured to the driver,
11736 * the driver will try to fallback from the configured interrupt mode to an
11737 * interrupt mode which is supported by the platform, kernel, and device in
11738 * the order of:
11739 * MSI-X -> MSI -> IRQ.
11740 *
11741 * Return codes
af901ca1 11742 * 0 - successful
da0436e9
JS
11743 * other values - error
11744 **/
11745static uint32_t
11746lpfc_sli4_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
11747{
11748 uint32_t intr_mode = LPFC_INTR_ERROR;
895427bd 11749 int retval, idx;
da0436e9
JS
11750
11751 if (cfg_mode == 2) {
11752 /* Preparation before conf_msi mbox cmd */
11753 retval = 0;
11754 if (!retval) {
11755 /* Now, try to enable MSI-X interrupt mode */
11756 retval = lpfc_sli4_enable_msix(phba);
11757 if (!retval) {
11758 /* Indicate initialization to MSI-X mode */
11759 phba->intr_type = MSIX;
11760 intr_mode = 2;
11761 }
11762 }
11763 }
11764
11765 /* Fallback to MSI if MSI-X initialization failed */
11766 if (cfg_mode >= 1 && phba->intr_type == NONE) {
11767 retval = lpfc_sli4_enable_msi(phba);
11768 if (!retval) {
11769 /* Indicate initialization to MSI mode */
11770 phba->intr_type = MSI;
11771 intr_mode = 1;
11772 }
11773 }
11774
11775 /* Fallback to INTx if both MSI-X/MSI initalization failed */
11776 if (phba->intr_type == NONE) {
11777 retval = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
11778 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
11779 if (!retval) {
895427bd 11780 struct lpfc_hba_eq_hdl *eqhdl;
dcaa2136 11781 unsigned int cpu;
895427bd 11782
da0436e9
JS
11783 /* Indicate initialization to INTx mode */
11784 phba->intr_type = INTx;
11785 intr_mode = 0;
895427bd 11786
dcaa2136
JS
11787 eqhdl = lpfc_get_eq_hdl(0);
11788 eqhdl->irq = pci_irq_vector(phba->pcidev, 0);
11789
11790 cpu = cpumask_first(cpu_present_mask);
11791 lpfc_assign_eq_map_info(phba, 0, LPFC_CPU_FIRST_IRQ,
11792 cpu);
6a828b0f 11793 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
dcaa2136 11794 eqhdl = lpfc_get_eq_hdl(idx);
895427bd 11795 eqhdl->idx = idx;
1ba981fd 11796 }
da0436e9
JS
11797 }
11798 }
11799 return intr_mode;
11800}
11801
11802/**
11803 * lpfc_sli4_disable_intr - Disable device interrupt to SLI-4 device
11804 * @phba: pointer to lpfc hba data structure.
11805 *
11806 * This routine is invoked to disable device interrupt and disassociate
11807 * the driver's interrupt handler(s) from interrupt vector(s) to device
11808 * with SLI-4 interface spec. Depending on the interrupt mode, the driver
11809 * will release the interrupt vector(s) for the message signaled interrupt.
11810 **/
11811static void
11812lpfc_sli4_disable_intr(struct lpfc_hba *phba)
11813{
11814 /* Disable the currently initialized interrupt mode */
45ffac19
CH
11815 if (phba->intr_type == MSIX) {
11816 int index;
dcaa2136 11817 struct lpfc_hba_eq_hdl *eqhdl;
45ffac19
CH
11818
11819 /* Free up MSI-X multi-message vectors */
6a828b0f 11820 for (index = 0; index < phba->cfg_irq_chann; index++) {
dcaa2136
JS
11821 eqhdl = lpfc_get_eq_hdl(index);
11822 lpfc_irq_clear_aff(eqhdl);
11823 irq_set_affinity_hint(eqhdl->irq, NULL);
11824 free_irq(eqhdl->irq, eqhdl);
b3295c2a 11825 }
45ffac19 11826 } else {
da0436e9 11827 free_irq(phba->pcidev->irq, phba);
45ffac19
CH
11828 }
11829
11830 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
11831
11832 /* Reset interrupt management states */
11833 phba->intr_type = NONE;
11834 phba->sli.slistat.sli_intr = 0;
da0436e9
JS
11835}
11836
11837/**
11838 * lpfc_unset_hba - Unset SLI3 hba device initialization
11839 * @phba: pointer to lpfc hba data structure.
11840 *
11841 * This routine is invoked to unset the HBA device initialization steps to
11842 * a device with SLI-3 interface spec.
11843 **/
11844static void
11845lpfc_unset_hba(struct lpfc_hba *phba)
11846{
11847 struct lpfc_vport *vport = phba->pport;
11848 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
11849
11850 spin_lock_irq(shost->host_lock);
11851 vport->load_flag |= FC_UNLOADING;
11852 spin_unlock_irq(shost->host_lock);
11853
72859909
JS
11854 kfree(phba->vpi_bmask);
11855 kfree(phba->vpi_ids);
11856
da0436e9
JS
11857 lpfc_stop_hba_timers(phba);
11858
11859 phba->pport->work_port_events = 0;
11860
11861 lpfc_sli_hba_down(phba);
11862
11863 lpfc_sli_brdrestart(phba);
11864
11865 lpfc_sli_disable_intr(phba);
11866
11867 return;
11868}
11869
5af5eee7
JS
11870/**
11871 * lpfc_sli4_xri_exchange_busy_wait - Wait for device XRI exchange busy
11872 * @phba: Pointer to HBA context object.
11873 *
11874 * This function is called in the SLI4 code path to wait for completion
11875 * of device's XRIs exchange busy. It will check the XRI exchange busy
11876 * on outstanding FCP and ELS I/Os every 10ms for up to 10 seconds; after
11877 * that, it will check the XRI exchange busy on outstanding FCP and ELS
11878 * I/Os every 30 seconds, log error message, and wait forever. Only when
11879 * all XRI exchange busy complete, the driver unload shall proceed with
11880 * invoking the function reset ioctl mailbox command to the CNA and the
11881 * the rest of the driver unload resource release.
11882 **/
11883static void
11884lpfc_sli4_xri_exchange_busy_wait(struct lpfc_hba *phba)
11885{
5e5b511d 11886 struct lpfc_sli4_hdw_queue *qp;
c00f62e6 11887 int idx, ccnt;
5af5eee7 11888 int wait_time = 0;
5e5b511d 11889 int io_xri_cmpl = 1;
86c67379 11890 int nvmet_xri_cmpl = 1;
5af5eee7
JS
11891 int els_xri_cmpl = list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
11892
c3725bdc
JS
11893 /* Driver just aborted IOs during the hba_unset process. Pause
11894 * here to give the HBA time to complete the IO and get entries
11895 * into the abts lists.
11896 */
11897 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1 * 5);
11898
11899 /* Wait for NVME pending IO to flush back to transport. */
11900 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
11901 lpfc_nvme_wait_for_io_drain(phba);
11902
5e5b511d 11903 ccnt = 0;
5e5b511d
JS
11904 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
11905 qp = &phba->sli4_hba.hdwq[idx];
c00f62e6
JS
11906 io_xri_cmpl = list_empty(&qp->lpfc_abts_io_buf_list);
11907 if (!io_xri_cmpl) /* if list is NOT empty */
11908 ccnt++;
5e5b511d
JS
11909 }
11910 if (ccnt)
11911 io_xri_cmpl = 0;
5e5b511d 11912
86c67379 11913 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
86c67379
JS
11914 nvmet_xri_cmpl =
11915 list_empty(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
11916 }
895427bd 11917
c00f62e6 11918 while (!els_xri_cmpl || !io_xri_cmpl || !nvmet_xri_cmpl) {
5af5eee7 11919 if (wait_time > LPFC_XRI_EXCH_BUSY_WAIT_TMO) {
68c9b55d 11920 if (!nvmet_xri_cmpl)
372c187b 11921 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
68c9b55d
JS
11922 "6424 NVMET XRI exchange busy "
11923 "wait time: %d seconds.\n",
11924 wait_time/1000);
5e5b511d 11925 if (!io_xri_cmpl)
372c187b 11926 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
c00f62e6 11927 "6100 IO XRI exchange busy "
5af5eee7
JS
11928 "wait time: %d seconds.\n",
11929 wait_time/1000);
11930 if (!els_xri_cmpl)
372c187b 11931 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5af5eee7
JS
11932 "2878 ELS XRI exchange busy "
11933 "wait time: %d seconds.\n",
11934 wait_time/1000);
11935 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T2);
11936 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T2;
11937 } else {
11938 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1);
11939 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T1;
11940 }
5e5b511d
JS
11941
11942 ccnt = 0;
5e5b511d
JS
11943 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
11944 qp = &phba->sli4_hba.hdwq[idx];
c00f62e6
JS
11945 io_xri_cmpl = list_empty(
11946 &qp->lpfc_abts_io_buf_list);
11947 if (!io_xri_cmpl) /* if list is NOT empty */
11948 ccnt++;
5e5b511d
JS
11949 }
11950 if (ccnt)
11951 io_xri_cmpl = 0;
5e5b511d 11952
86c67379 11953 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
86c67379
JS
11954 nvmet_xri_cmpl = list_empty(
11955 &phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
11956 }
5af5eee7
JS
11957 els_xri_cmpl =
11958 list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
f358dd0c 11959
5af5eee7
JS
11960 }
11961}
11962
da0436e9
JS
11963/**
11964 * lpfc_sli4_hba_unset - Unset the fcoe hba
11965 * @phba: Pointer to HBA context object.
11966 *
11967 * This function is called in the SLI4 code path to reset the HBA's FCoE
11968 * function. The caller is not required to hold any lock. This routine
11969 * issues PCI function reset mailbox command to reset the FCoE function.
11970 * At the end of the function, it calls lpfc_hba_down_post function to
11971 * free any pending commands.
11972 **/
11973static void
11974lpfc_sli4_hba_unset(struct lpfc_hba *phba)
11975{
11976 int wait_cnt = 0;
11977 LPFC_MBOXQ_t *mboxq;
912e3acd 11978 struct pci_dev *pdev = phba->pcidev;
da0436e9
JS
11979
11980 lpfc_stop_hba_timers(phba);
cdb42bec
JS
11981 if (phba->pport)
11982 phba->sli4_hba.intr_enable = 0;
da0436e9
JS
11983
11984 /*
11985 * Gracefully wait out the potential current outstanding asynchronous
11986 * mailbox command.
11987 */
11988
11989 /* First, block any pending async mailbox command from posted */
11990 spin_lock_irq(&phba->hbalock);
11991 phba->sli.sli_flag |= LPFC_SLI_ASYNC_MBX_BLK;
11992 spin_unlock_irq(&phba->hbalock);
11993 /* Now, trying to wait it out if we can */
11994 while (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
11995 msleep(10);
11996 if (++wait_cnt > LPFC_ACTIVE_MBOX_WAIT_CNT)
11997 break;
11998 }
11999 /* Forcefully release the outstanding mailbox command if timed out */
12000 if (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
12001 spin_lock_irq(&phba->hbalock);
12002 mboxq = phba->sli.mbox_active;
12003 mboxq->u.mb.mbxStatus = MBX_NOT_FINISHED;
12004 __lpfc_mbox_cmpl_put(phba, mboxq);
12005 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
12006 phba->sli.mbox_active = NULL;
12007 spin_unlock_irq(&phba->hbalock);
12008 }
12009
5af5eee7
JS
12010 /* Abort all iocbs associated with the hba */
12011 lpfc_sli_hba_iocb_abort(phba);
12012
12013 /* Wait for completion of device XRI exchange busy */
12014 lpfc_sli4_xri_exchange_busy_wait(phba);
12015
93a4d6f4 12016 /* per-phba callback de-registration for hotplug event */
46da547e
SP
12017 if (phba->pport)
12018 lpfc_cpuhp_remove(phba);
93a4d6f4 12019
da0436e9
JS
12020 /* Disable PCI subsystem interrupt */
12021 lpfc_sli4_disable_intr(phba);
12022
912e3acd
JS
12023 /* Disable SR-IOV if enabled */
12024 if (phba->cfg_sriov_nr_virtfn)
12025 pci_disable_sriov(pdev);
12026
da0436e9
JS
12027 /* Stop kthread signal shall trigger work_done one more time */
12028 kthread_stop(phba->worker_thread);
12029
d2cc9bcd 12030 /* Disable FW logging to host memory */
1165a5c2 12031 lpfc_ras_stop_fwlog(phba);
d2cc9bcd 12032
d1f525aa
JS
12033 /* Unset the queues shared with the hardware then release all
12034 * allocated resources.
12035 */
12036 lpfc_sli4_queue_unset(phba);
12037 lpfc_sli4_queue_destroy(phba);
12038
3677a3a7
JS
12039 /* Reset SLI4 HBA FCoE function */
12040 lpfc_pci_function_reset(phba);
12041
1165a5c2
JS
12042 /* Free RAS DMA memory */
12043 if (phba->ras_fwlog.ras_enabled)
12044 lpfc_sli4_ras_dma_free(phba);
12045
da0436e9 12046 /* Stop the SLI4 device port */
1ffdd2c0
JS
12047 if (phba->pport)
12048 phba->pport->work_port_events = 0;
da0436e9
JS
12049}
12050
28baac74
JS
12051 /**
12052 * lpfc_pc_sli4_params_get - Get the SLI4_PARAMS port capabilities.
12053 * @phba: Pointer to HBA context object.
12054 * @mboxq: Pointer to the mailboxq memory for the mailbox command response.
12055 *
12056 * This function is called in the SLI4 code path to read the port's
12057 * sli4 capabilities.
12058 *
12059 * This function may be be called from any context that can block-wait
12060 * for the completion. The expectation is that this routine is called
12061 * typically from probe_one or from the online routine.
12062 **/
12063int
12064lpfc_pc_sli4_params_get(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
12065{
12066 int rc;
12067 struct lpfc_mqe *mqe;
12068 struct lpfc_pc_sli4_params *sli4_params;
12069 uint32_t mbox_tmo;
12070
12071 rc = 0;
12072 mqe = &mboxq->u.mqe;
12073
12074 /* Read the port's SLI4 Parameters port capabilities */
fedd3b7b 12075 lpfc_pc_sli4_params(mboxq);
28baac74
JS
12076 if (!phba->sli4_hba.intr_enable)
12077 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
12078 else {
a183a15f 12079 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
28baac74
JS
12080 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
12081 }
12082
12083 if (unlikely(rc))
12084 return 1;
12085
12086 sli4_params = &phba->sli4_hba.pc_sli4_params;
12087 sli4_params->if_type = bf_get(if_type, &mqe->un.sli4_params);
12088 sli4_params->sli_rev = bf_get(sli_rev, &mqe->un.sli4_params);
12089 sli4_params->sli_family = bf_get(sli_family, &mqe->un.sli4_params);
12090 sli4_params->featurelevel_1 = bf_get(featurelevel_1,
12091 &mqe->un.sli4_params);
12092 sli4_params->featurelevel_2 = bf_get(featurelevel_2,
12093 &mqe->un.sli4_params);
12094 sli4_params->proto_types = mqe->un.sli4_params.word3;
12095 sli4_params->sge_supp_len = mqe->un.sli4_params.sge_supp_len;
12096 sli4_params->if_page_sz = bf_get(if_page_sz, &mqe->un.sli4_params);
12097 sli4_params->rq_db_window = bf_get(rq_db_window, &mqe->un.sli4_params);
12098 sli4_params->loopbk_scope = bf_get(loopbk_scope, &mqe->un.sli4_params);
12099 sli4_params->eq_pages_max = bf_get(eq_pages, &mqe->un.sli4_params);
12100 sli4_params->eqe_size = bf_get(eqe_size, &mqe->un.sli4_params);
12101 sli4_params->cq_pages_max = bf_get(cq_pages, &mqe->un.sli4_params);
12102 sli4_params->cqe_size = bf_get(cqe_size, &mqe->un.sli4_params);
12103 sli4_params->mq_pages_max = bf_get(mq_pages, &mqe->un.sli4_params);
12104 sli4_params->mqe_size = bf_get(mqe_size, &mqe->un.sli4_params);
12105 sli4_params->mq_elem_cnt = bf_get(mq_elem_cnt, &mqe->un.sli4_params);
12106 sli4_params->wq_pages_max = bf_get(wq_pages, &mqe->un.sli4_params);
12107 sli4_params->wqe_size = bf_get(wqe_size, &mqe->un.sli4_params);
12108 sli4_params->rq_pages_max = bf_get(rq_pages, &mqe->un.sli4_params);
12109 sli4_params->rqe_size = bf_get(rqe_size, &mqe->un.sli4_params);
12110 sli4_params->hdr_pages_max = bf_get(hdr_pages, &mqe->un.sli4_params);
12111 sli4_params->hdr_size = bf_get(hdr_size, &mqe->un.sli4_params);
12112 sli4_params->hdr_pp_align = bf_get(hdr_pp_align, &mqe->un.sli4_params);
12113 sli4_params->sgl_pages_max = bf_get(sgl_pages, &mqe->un.sli4_params);
12114 sli4_params->sgl_pp_align = bf_get(sgl_pp_align, &mqe->un.sli4_params);
0558056c
JS
12115
12116 /* Make sure that sge_supp_len can be handled by the driver */
12117 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
12118 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
12119
28baac74
JS
12120 return rc;
12121}
12122
fedd3b7b
JS
12123/**
12124 * lpfc_get_sli4_parameters - Get the SLI4 Config PARAMETERS.
12125 * @phba: Pointer to HBA context object.
12126 * @mboxq: Pointer to the mailboxq memory for the mailbox command response.
12127 *
12128 * This function is called in the SLI4 code path to read the port's
12129 * sli4 capabilities.
12130 *
12131 * This function may be be called from any context that can block-wait
12132 * for the completion. The expectation is that this routine is called
12133 * typically from probe_one or from the online routine.
12134 **/
12135int
12136lpfc_get_sli4_parameters(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
12137{
12138 int rc;
12139 struct lpfc_mqe *mqe = &mboxq->u.mqe;
12140 struct lpfc_pc_sli4_params *sli4_params;
a183a15f 12141 uint32_t mbox_tmo;
fedd3b7b 12142 int length;
bf316c78 12143 bool exp_wqcq_pages = true;
fedd3b7b
JS
12144 struct lpfc_sli4_parameters *mbx_sli4_parameters;
12145
6d368e53
JS
12146 /*
12147 * By default, the driver assumes the SLI4 port requires RPI
12148 * header postings. The SLI4_PARAM response will correct this
12149 * assumption.
12150 */
12151 phba->sli4_hba.rpi_hdrs_in_use = 1;
12152
fedd3b7b
JS
12153 /* Read the port's SLI4 Config Parameters */
12154 length = (sizeof(struct lpfc_mbx_get_sli4_parameters) -
12155 sizeof(struct lpfc_sli4_cfg_mhdr));
12156 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
12157 LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS,
12158 length, LPFC_SLI4_MBX_EMBED);
12159 if (!phba->sli4_hba.intr_enable)
12160 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
a183a15f
JS
12161 else {
12162 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
12163 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
12164 }
fedd3b7b
JS
12165 if (unlikely(rc))
12166 return rc;
12167 sli4_params = &phba->sli4_hba.pc_sli4_params;
12168 mbx_sli4_parameters = &mqe->un.get_sli4_parameters.sli4_parameters;
12169 sli4_params->if_type = bf_get(cfg_if_type, mbx_sli4_parameters);
12170 sli4_params->sli_rev = bf_get(cfg_sli_rev, mbx_sli4_parameters);
12171 sli4_params->sli_family = bf_get(cfg_sli_family, mbx_sli4_parameters);
12172 sli4_params->featurelevel_1 = bf_get(cfg_sli_hint_1,
12173 mbx_sli4_parameters);
12174 sli4_params->featurelevel_2 = bf_get(cfg_sli_hint_2,
12175 mbx_sli4_parameters);
12176 if (bf_get(cfg_phwq, mbx_sli4_parameters))
12177 phba->sli3_options |= LPFC_SLI4_PHWQ_ENABLED;
12178 else
12179 phba->sli3_options &= ~LPFC_SLI4_PHWQ_ENABLED;
12180 sli4_params->sge_supp_len = mbx_sli4_parameters->sge_supp_len;
12181 sli4_params->loopbk_scope = bf_get(loopbk_scope, mbx_sli4_parameters);
1ba981fd 12182 sli4_params->oas_supported = bf_get(cfg_oas, mbx_sli4_parameters);
fedd3b7b
JS
12183 sli4_params->cqv = bf_get(cfg_cqv, mbx_sli4_parameters);
12184 sli4_params->mqv = bf_get(cfg_mqv, mbx_sli4_parameters);
12185 sli4_params->wqv = bf_get(cfg_wqv, mbx_sli4_parameters);
12186 sli4_params->rqv = bf_get(cfg_rqv, mbx_sli4_parameters);
7365f6fd
JS
12187 sli4_params->eqav = bf_get(cfg_eqav, mbx_sli4_parameters);
12188 sli4_params->cqav = bf_get(cfg_cqav, mbx_sli4_parameters);
0c651878 12189 sli4_params->wqsize = bf_get(cfg_wqsize, mbx_sli4_parameters);
66e9e6bf 12190 sli4_params->bv1s = bf_get(cfg_bv1s, mbx_sli4_parameters);
83c6cb1a 12191 sli4_params->pls = bf_get(cfg_pvl, mbx_sli4_parameters);
fedd3b7b
JS
12192 sli4_params->sgl_pages_max = bf_get(cfg_sgl_page_cnt,
12193 mbx_sli4_parameters);
895427bd 12194 sli4_params->wqpcnt = bf_get(cfg_wqpcnt, mbx_sli4_parameters);
fedd3b7b
JS
12195 sli4_params->sgl_pp_align = bf_get(cfg_sgl_pp_align,
12196 mbx_sli4_parameters);
6d368e53
JS
12197 phba->sli4_hba.extents_in_use = bf_get(cfg_ext, mbx_sli4_parameters);
12198 phba->sli4_hba.rpi_hdrs_in_use = bf_get(cfg_hdrr, mbx_sli4_parameters);
c15e0704 12199
d79c9e9d
JS
12200 /* Check for Extended Pre-Registered SGL support */
12201 phba->cfg_xpsgl = bf_get(cfg_xpsgl, mbx_sli4_parameters);
12202
c15e0704
JS
12203 /* Check for firmware nvme support */
12204 rc = (bf_get(cfg_nvme, mbx_sli4_parameters) &&
12205 bf_get(cfg_xib, mbx_sli4_parameters));
12206
12207 if (rc) {
12208 /* Save this to indicate the Firmware supports NVME */
12209 sli4_params->nvme = 1;
12210
12211 /* Firmware NVME support, check driver FC4 NVME support */
12212 if (phba->cfg_enable_fc4_type == LPFC_ENABLE_FCP) {
12213 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME,
12214 "6133 Disabling NVME support: "
12215 "FC4 type not supported: x%x\n",
12216 phba->cfg_enable_fc4_type);
12217 goto fcponly;
12218 }
12219 } else {
12220 /* No firmware NVME support, check driver FC4 NVME support */
12221 sli4_params->nvme = 0;
12222 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
12223 lpfc_printf_log(phba, KERN_ERR, LOG_INIT | LOG_NVME,
12224 "6101 Disabling NVME support: Not "
12225 "supported by firmware (%d %d) x%x\n",
12226 bf_get(cfg_nvme, mbx_sli4_parameters),
12227 bf_get(cfg_xib, mbx_sli4_parameters),
12228 phba->cfg_enable_fc4_type);
12229fcponly:
12230 phba->nvme_support = 0;
12231 phba->nvmet_support = 0;
12232 phba->cfg_nvmet_mrq = 0;
6a224b47 12233 phba->cfg_nvme_seg_cnt = 0;
c15e0704
JS
12234
12235 /* If no FC4 type support, move to just SCSI support */
12236 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
12237 return -ENODEV;
12238 phba->cfg_enable_fc4_type = LPFC_ENABLE_FCP;
12239 }
895427bd 12240 }
0558056c 12241
c26c265b 12242 /* If the NVME FC4 type is enabled, scale the sg_seg_cnt to
a5f7337f 12243 * accommodate 512K and 1M IOs in a single nvme buf.
c26c265b 12244 */
a5f7337f 12245 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
c26c265b 12246 phba->cfg_sg_seg_cnt = LPFC_MAX_NVME_SEG_CNT;
c26c265b 12247
414abe0a
JS
12248 /* Only embed PBDE for if_type 6, PBDE support requires xib be set */
12249 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) !=
12250 LPFC_SLI_INTF_IF_TYPE_6) || (!bf_get(cfg_xib, mbx_sli4_parameters)))
12251 phba->cfg_enable_pbde = 0;
0bc2b7c5 12252
20aefac3
JS
12253 /*
12254 * To support Suppress Response feature we must satisfy 3 conditions.
12255 * lpfc_suppress_rsp module parameter must be set (default).
12256 * In SLI4-Parameters Descriptor:
12257 * Extended Inline Buffers (XIB) must be supported.
12258 * Suppress Response IU Not Supported (SRIUNS) must NOT be supported
12259 * (double negative).
12260 */
12261 if (phba->cfg_suppress_rsp && bf_get(cfg_xib, mbx_sli4_parameters) &&
12262 !(bf_get(cfg_nosr, mbx_sli4_parameters)))
f358dd0c 12263 phba->sli.sli_flag |= LPFC_SLI_SUPPRESS_RSP;
20aefac3
JS
12264 else
12265 phba->cfg_suppress_rsp = 0;
f358dd0c 12266
0cf07f84
JS
12267 if (bf_get(cfg_eqdr, mbx_sli4_parameters))
12268 phba->sli.sli_flag |= LPFC_SLI_USE_EQDR;
12269
0558056c
JS
12270 /* Make sure that sge_supp_len can be handled by the driver */
12271 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
12272 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
12273
b5c53958 12274 /*
c176ffa0
JS
12275 * Check whether the adapter supports an embedded copy of the
12276 * FCP CMD IU within the WQE for FCP_Ixxx commands. In order
12277 * to use this option, 128-byte WQEs must be used.
b5c53958
JS
12278 */
12279 if (bf_get(cfg_ext_embed_cb, mbx_sli4_parameters))
12280 phba->fcp_embed_io = 1;
12281 else
12282 phba->fcp_embed_io = 0;
7bdedb34 12283
0bc2b7c5 12284 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME,
414abe0a 12285 "6422 XIB %d PBDE %d: FCP %d NVME %d %d %d\n",
0bc2b7c5 12286 bf_get(cfg_xib, mbx_sli4_parameters),
414abe0a
JS
12287 phba->cfg_enable_pbde,
12288 phba->fcp_embed_io, phba->nvme_support,
4e565cf0 12289 phba->cfg_nvme_embed_cmd, phba->cfg_suppress_rsp);
0bc2b7c5 12290
bf316c78
JS
12291 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
12292 LPFC_SLI_INTF_IF_TYPE_2) &&
12293 (bf_get(lpfc_sli_intf_sli_family, &phba->sli4_hba.sli_intf) ==
c221768b 12294 LPFC_SLI_INTF_FAMILY_LNCR_A0))
bf316c78
JS
12295 exp_wqcq_pages = false;
12296
c176ffa0
JS
12297 if ((bf_get(cfg_cqpsize, mbx_sli4_parameters) & LPFC_CQ_16K_PAGE_SZ) &&
12298 (bf_get(cfg_wqpsize, mbx_sli4_parameters) & LPFC_WQ_16K_PAGE_SZ) &&
bf316c78 12299 exp_wqcq_pages &&
c176ffa0
JS
12300 (sli4_params->wqsize & LPFC_WQ_SZ128_SUPPORT))
12301 phba->enab_exp_wqcq_pages = 1;
12302 else
12303 phba->enab_exp_wqcq_pages = 0;
7bdedb34
JS
12304 /*
12305 * Check if the SLI port supports MDS Diagnostics
12306 */
12307 if (bf_get(cfg_mds_diags, mbx_sli4_parameters))
12308 phba->mds_diags_support = 1;
12309 else
12310 phba->mds_diags_support = 0;
d2cc9bcd 12311
0d8af096
JS
12312 /*
12313 * Check if the SLI port supports NSLER
12314 */
12315 if (bf_get(cfg_nsler, mbx_sli4_parameters))
12316 phba->nsler = 1;
12317 else
12318 phba->nsler = 0;
12319
fedd3b7b
JS
12320 return 0;
12321}
12322
da0436e9
JS
12323/**
12324 * lpfc_pci_probe_one_s3 - PCI probe func to reg SLI-3 device to PCI subsystem.
12325 * @pdev: pointer to PCI device
12326 * @pid: pointer to PCI device identifier
12327 *
12328 * This routine is to be called to attach a device with SLI-3 interface spec
12329 * to the PCI subsystem. When an Emulex HBA with SLI-3 interface spec is
12330 * presented on PCI bus, the kernel PCI subsystem looks at PCI device-specific
12331 * information of the device and driver to see if the driver state that it can
12332 * support this kind of device. If the match is successful, the driver core
12333 * invokes this routine. If this routine determines it can claim the HBA, it
12334 * does all the initialization that it needs to do to handle the HBA properly.
12335 *
12336 * Return code
12337 * 0 - driver can claim the device
12338 * negative value - driver can not claim the device
12339 **/
6f039790 12340static int
da0436e9
JS
12341lpfc_pci_probe_one_s3(struct pci_dev *pdev, const struct pci_device_id *pid)
12342{
12343 struct lpfc_hba *phba;
12344 struct lpfc_vport *vport = NULL;
6669f9bb 12345 struct Scsi_Host *shost = NULL;
da0436e9
JS
12346 int error;
12347 uint32_t cfg_mode, intr_mode;
12348
12349 /* Allocate memory for HBA structure */
12350 phba = lpfc_hba_alloc(pdev);
12351 if (!phba)
12352 return -ENOMEM;
12353
12354 /* Perform generic PCI device enabling operation */
12355 error = lpfc_enable_pci_dev(phba);
079b5c91 12356 if (error)
da0436e9 12357 goto out_free_phba;
da0436e9
JS
12358
12359 /* Set up SLI API function jump table for PCI-device group-0 HBAs */
12360 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_LP);
12361 if (error)
12362 goto out_disable_pci_dev;
12363
12364 /* Set up SLI-3 specific device PCI memory space */
12365 error = lpfc_sli_pci_mem_setup(phba);
12366 if (error) {
12367 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12368 "1402 Failed to set up pci memory space.\n");
12369 goto out_disable_pci_dev;
12370 }
12371
da0436e9
JS
12372 /* Set up SLI-3 specific device driver resources */
12373 error = lpfc_sli_driver_resource_setup(phba);
12374 if (error) {
12375 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12376 "1404 Failed to set up driver resource.\n");
12377 goto out_unset_pci_mem_s3;
12378 }
12379
12380 /* Initialize and populate the iocb list per host */
d1f525aa 12381
da0436e9
JS
12382 error = lpfc_init_iocb_list(phba, LPFC_IOCB_LIST_CNT);
12383 if (error) {
12384 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12385 "1405 Failed to initialize iocb list.\n");
12386 goto out_unset_driver_resource_s3;
12387 }
12388
12389 /* Set up common device driver resources */
12390 error = lpfc_setup_driver_resource_phase2(phba);
12391 if (error) {
12392 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12393 "1406 Failed to set up driver resource.\n");
12394 goto out_free_iocb_list;
12395 }
12396
079b5c91
JS
12397 /* Get the default values for Model Name and Description */
12398 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
12399
da0436e9
JS
12400 /* Create SCSI host to the physical port */
12401 error = lpfc_create_shost(phba);
12402 if (error) {
12403 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12404 "1407 Failed to create scsi host.\n");
12405 goto out_unset_driver_resource;
12406 }
12407
12408 /* Configure sysfs attributes */
12409 vport = phba->pport;
12410 error = lpfc_alloc_sysfs_attr(vport);
12411 if (error) {
12412 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12413 "1476 Failed to allocate sysfs attr\n");
12414 goto out_destroy_shost;
12415 }
12416
6669f9bb 12417 shost = lpfc_shost_from_vport(vport); /* save shost for error cleanup */
da0436e9
JS
12418 /* Now, trying to enable interrupt and bring up the device */
12419 cfg_mode = phba->cfg_use_msi;
12420 while (true) {
12421 /* Put device to a known state before enabling interrupt */
12422 lpfc_stop_port(phba);
12423 /* Configure and enable interrupt */
12424 intr_mode = lpfc_sli_enable_intr(phba, cfg_mode);
12425 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 12426 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
12427 "0431 Failed to enable interrupt.\n");
12428 error = -ENODEV;
12429 goto out_free_sysfs_attr;
12430 }
12431 /* SLI-3 HBA setup */
12432 if (lpfc_sli_hba_setup(phba)) {
372c187b 12433 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
12434 "1477 Failed to set up hba\n");
12435 error = -ENODEV;
12436 goto out_remove_device;
12437 }
12438
12439 /* Wait 50ms for the interrupts of previous mailbox commands */
12440 msleep(50);
12441 /* Check active interrupts on message signaled interrupts */
12442 if (intr_mode == 0 ||
12443 phba->sli.slistat.sli_intr > LPFC_MSIX_VECTORS) {
12444 /* Log the current active interrupt mode */
12445 phba->intr_mode = intr_mode;
12446 lpfc_log_intr_mode(phba, intr_mode);
12447 break;
12448 } else {
12449 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12450 "0447 Configure interrupt mode (%d) "
12451 "failed active interrupt test.\n",
12452 intr_mode);
12453 /* Disable the current interrupt mode */
12454 lpfc_sli_disable_intr(phba);
12455 /* Try next level of interrupt mode */
12456 cfg_mode = --intr_mode;
12457 }
12458 }
12459
12460 /* Perform post initialization setup */
12461 lpfc_post_init_setup(phba);
12462
12463 /* Check if there are static vports to be created. */
12464 lpfc_create_static_vport(phba);
12465
12466 return 0;
12467
12468out_remove_device:
12469 lpfc_unset_hba(phba);
12470out_free_sysfs_attr:
12471 lpfc_free_sysfs_attr(vport);
12472out_destroy_shost:
12473 lpfc_destroy_shost(phba);
12474out_unset_driver_resource:
12475 lpfc_unset_driver_resource_phase2(phba);
12476out_free_iocb_list:
12477 lpfc_free_iocb_list(phba);
12478out_unset_driver_resource_s3:
12479 lpfc_sli_driver_resource_unset(phba);
12480out_unset_pci_mem_s3:
12481 lpfc_sli_pci_mem_unset(phba);
12482out_disable_pci_dev:
12483 lpfc_disable_pci_dev(phba);
6669f9bb
JS
12484 if (shost)
12485 scsi_host_put(shost);
da0436e9
JS
12486out_free_phba:
12487 lpfc_hba_free(phba);
12488 return error;
12489}
12490
12491/**
12492 * lpfc_pci_remove_one_s3 - PCI func to unreg SLI-3 device from PCI subsystem.
12493 * @pdev: pointer to PCI device
12494 *
12495 * This routine is to be called to disattach a device with SLI-3 interface
12496 * spec from PCI subsystem. When an Emulex HBA with SLI-3 interface spec is
12497 * removed from PCI bus, it performs all the necessary cleanup for the HBA
12498 * device to be removed from the PCI subsystem properly.
12499 **/
6f039790 12500static void
da0436e9
JS
12501lpfc_pci_remove_one_s3(struct pci_dev *pdev)
12502{
12503 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12504 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
12505 struct lpfc_vport **vports;
12506 struct lpfc_hba *phba = vport->phba;
12507 int i;
da0436e9
JS
12508
12509 spin_lock_irq(&phba->hbalock);
12510 vport->load_flag |= FC_UNLOADING;
12511 spin_unlock_irq(&phba->hbalock);
12512
12513 lpfc_free_sysfs_attr(vport);
12514
12515 /* Release all the vports against this physical port */
12516 vports = lpfc_create_vport_work_array(phba);
12517 if (vports != NULL)
587a37f6
JS
12518 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
12519 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
12520 continue;
da0436e9 12521 fc_vport_terminate(vports[i]->fc_vport);
587a37f6 12522 }
da0436e9
JS
12523 lpfc_destroy_vport_work_array(phba, vports);
12524
12525 /* Remove FC host and then SCSI host with the physical port */
12526 fc_remove_host(shost);
12527 scsi_remove_host(shost);
d613b6a7 12528
da0436e9
JS
12529 lpfc_cleanup(vport);
12530
12531 /*
12532 * Bring down the SLI Layer. This step disable all interrupts,
12533 * clears the rings, discards all mailbox commands, and resets
12534 * the HBA.
12535 */
12536
48e34d0f 12537 /* HBA interrupt will be disabled after this call */
da0436e9
JS
12538 lpfc_sli_hba_down(phba);
12539 /* Stop kthread signal shall trigger work_done one more time */
12540 kthread_stop(phba->worker_thread);
12541 /* Final cleanup of txcmplq and reset the HBA */
12542 lpfc_sli_brdrestart(phba);
12543
72859909
JS
12544 kfree(phba->vpi_bmask);
12545 kfree(phba->vpi_ids);
12546
da0436e9 12547 lpfc_stop_hba_timers(phba);
523128e5 12548 spin_lock_irq(&phba->port_list_lock);
da0436e9 12549 list_del_init(&vport->listentry);
523128e5 12550 spin_unlock_irq(&phba->port_list_lock);
da0436e9
JS
12551
12552 lpfc_debugfs_terminate(vport);
12553
912e3acd
JS
12554 /* Disable SR-IOV if enabled */
12555 if (phba->cfg_sriov_nr_virtfn)
12556 pci_disable_sriov(pdev);
12557
da0436e9
JS
12558 /* Disable interrupt */
12559 lpfc_sli_disable_intr(phba);
12560
da0436e9
JS
12561 scsi_host_put(shost);
12562
12563 /*
12564 * Call scsi_free before mem_free since scsi bufs are released to their
12565 * corresponding pools here.
12566 */
12567 lpfc_scsi_free(phba);
0794d601
JS
12568 lpfc_free_iocb_list(phba);
12569
da0436e9
JS
12570 lpfc_mem_free_all(phba);
12571
12572 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
12573 phba->hbqslimp.virt, phba->hbqslimp.phys);
12574
12575 /* Free resources associated with SLI2 interface */
12576 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
12577 phba->slim2p.virt, phba->slim2p.phys);
12578
12579 /* unmap adapter SLIM and Control Registers */
12580 iounmap(phba->ctrl_regs_memmap_p);
12581 iounmap(phba->slim_memmap_p);
12582
12583 lpfc_hba_free(phba);
12584
e0c0483c 12585 pci_release_mem_regions(pdev);
da0436e9
JS
12586 pci_disable_device(pdev);
12587}
12588
12589/**
12590 * lpfc_pci_suspend_one_s3 - PCI func to suspend SLI-3 device for power mgmnt
12591 * @pdev: pointer to PCI device
12592 * @msg: power management message
12593 *
12594 * This routine is to be called from the kernel's PCI subsystem to support
12595 * system Power Management (PM) to device with SLI-3 interface spec. When
12596 * PM invokes this method, it quiesces the device by stopping the driver's
12597 * worker thread for the device, turning off device's interrupt and DMA,
12598 * and bring the device offline. Note that as the driver implements the
12599 * minimum PM requirements to a power-aware driver's PM support for the
12600 * suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE, FREEZE)
12601 * to the suspend() method call will be treated as SUSPEND and the driver will
12602 * fully reinitialize its device during resume() method call, the driver will
12603 * set device to PCI_D3hot state in PCI config space instead of setting it
12604 * according to the @msg provided by the PM.
12605 *
12606 * Return code
12607 * 0 - driver suspended the device
12608 * Error otherwise
12609 **/
12610static int
12611lpfc_pci_suspend_one_s3(struct pci_dev *pdev, pm_message_t msg)
12612{
12613 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12614 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12615
12616 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12617 "0473 PCI device Power Management suspend.\n");
12618
12619 /* Bring down the device */
618a5230 12620 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
da0436e9
JS
12621 lpfc_offline(phba);
12622 kthread_stop(phba->worker_thread);
12623
12624 /* Disable interrupt from device */
12625 lpfc_sli_disable_intr(phba);
12626
12627 /* Save device state to PCI config space */
12628 pci_save_state(pdev);
12629 pci_set_power_state(pdev, PCI_D3hot);
12630
12631 return 0;
12632}
12633
12634/**
12635 * lpfc_pci_resume_one_s3 - PCI func to resume SLI-3 device for power mgmnt
12636 * @pdev: pointer to PCI device
12637 *
12638 * This routine is to be called from the kernel's PCI subsystem to support
12639 * system Power Management (PM) to device with SLI-3 interface spec. When PM
12640 * invokes this method, it restores the device's PCI config space state and
12641 * fully reinitializes the device and brings it online. Note that as the
12642 * driver implements the minimum PM requirements to a power-aware driver's
12643 * PM for suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE,
12644 * FREEZE) to the suspend() method call will be treated as SUSPEND and the
12645 * driver will fully reinitialize its device during resume() method call,
12646 * the device will be set to PCI_D0 directly in PCI config space before
12647 * restoring the state.
12648 *
12649 * Return code
12650 * 0 - driver suspended the device
12651 * Error otherwise
12652 **/
12653static int
12654lpfc_pci_resume_one_s3(struct pci_dev *pdev)
12655{
12656 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12657 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12658 uint32_t intr_mode;
12659 int error;
12660
12661 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12662 "0452 PCI device Power Management resume.\n");
12663
12664 /* Restore device state from PCI config space */
12665 pci_set_power_state(pdev, PCI_D0);
12666 pci_restore_state(pdev);
0d878419 12667
1dfb5a47
JS
12668 /*
12669 * As the new kernel behavior of pci_restore_state() API call clears
12670 * device saved_state flag, need to save the restored state again.
12671 */
12672 pci_save_state(pdev);
12673
da0436e9
JS
12674 if (pdev->is_busmaster)
12675 pci_set_master(pdev);
12676
12677 /* Startup the kernel thread for this host adapter. */
12678 phba->worker_thread = kthread_run(lpfc_do_work, phba,
12679 "lpfc_worker_%d", phba->brd_no);
12680 if (IS_ERR(phba->worker_thread)) {
12681 error = PTR_ERR(phba->worker_thread);
12682 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12683 "0434 PM resume failed to start worker "
12684 "thread: error=x%x.\n", error);
12685 return error;
12686 }
12687
12688 /* Configure and enable interrupt */
12689 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
12690 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 12691 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
12692 "0430 PM resume Failed to enable interrupt\n");
12693 return -EIO;
12694 } else
12695 phba->intr_mode = intr_mode;
12696
12697 /* Restart HBA and bring it online */
12698 lpfc_sli_brdrestart(phba);
12699 lpfc_online(phba);
12700
12701 /* Log the current active interrupt mode */
12702 lpfc_log_intr_mode(phba, phba->intr_mode);
12703
12704 return 0;
12705}
12706
891478a2
JS
12707/**
12708 * lpfc_sli_prep_dev_for_recover - Prepare SLI3 device for pci slot recover
12709 * @phba: pointer to lpfc hba data structure.
12710 *
12711 * This routine is called to prepare the SLI3 device for PCI slot recover. It
e2af0d2e 12712 * aborts all the outstanding SCSI I/Os to the pci device.
891478a2
JS
12713 **/
12714static void
12715lpfc_sli_prep_dev_for_recover(struct lpfc_hba *phba)
12716{
372c187b 12717 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
891478a2 12718 "2723 PCI channel I/O abort preparing for recovery\n");
e2af0d2e
JS
12719
12720 /*
12721 * There may be errored I/Os through HBA, abort all I/Os on txcmplq
12722 * and let the SCSI mid-layer to retry them to recover.
12723 */
db55fba8 12724 lpfc_sli_abort_fcp_rings(phba);
891478a2
JS
12725}
12726
0d878419
JS
12727/**
12728 * lpfc_sli_prep_dev_for_reset - Prepare SLI3 device for pci slot reset
12729 * @phba: pointer to lpfc hba data structure.
12730 *
12731 * This routine is called to prepare the SLI3 device for PCI slot reset. It
12732 * disables the device interrupt and pci device, and aborts the internal FCP
12733 * pending I/Os.
12734 **/
12735static void
12736lpfc_sli_prep_dev_for_reset(struct lpfc_hba *phba)
12737{
372c187b 12738 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
891478a2 12739 "2710 PCI channel disable preparing for reset\n");
e2af0d2e 12740
75baf696 12741 /* Block any management I/Os to the device */
618a5230 12742 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
75baf696 12743
e2af0d2e
JS
12744 /* Block all SCSI devices' I/Os on the host */
12745 lpfc_scsi_dev_block(phba);
12746
ea714f3d 12747 /* Flush all driver's outstanding SCSI I/Os as we are to reset */
c00f62e6 12748 lpfc_sli_flush_io_rings(phba);
ea714f3d 12749
e2af0d2e
JS
12750 /* stop all timers */
12751 lpfc_stop_hba_timers(phba);
12752
0d878419
JS
12753 /* Disable interrupt and pci device */
12754 lpfc_sli_disable_intr(phba);
12755 pci_disable_device(phba->pcidev);
0d878419
JS
12756}
12757
12758/**
12759 * lpfc_sli_prep_dev_for_perm_failure - Prepare SLI3 dev for pci slot disable
12760 * @phba: pointer to lpfc hba data structure.
12761 *
12762 * This routine is called to prepare the SLI3 device for PCI slot permanently
12763 * disabling. It blocks the SCSI transport layer traffic and flushes the FCP
12764 * pending I/Os.
12765 **/
12766static void
75baf696 12767lpfc_sli_prep_dev_for_perm_failure(struct lpfc_hba *phba)
0d878419 12768{
372c187b 12769 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
891478a2 12770 "2711 PCI channel permanent disable for failure\n");
e2af0d2e
JS
12771 /* Block all SCSI devices' I/Os on the host */
12772 lpfc_scsi_dev_block(phba);
12773
12774 /* stop all timers */
12775 lpfc_stop_hba_timers(phba);
12776
0d878419 12777 /* Clean up all driver's outstanding SCSI I/Os */
c00f62e6 12778 lpfc_sli_flush_io_rings(phba);
0d878419
JS
12779}
12780
da0436e9
JS
12781/**
12782 * lpfc_io_error_detected_s3 - Method for handling SLI-3 device PCI I/O error
12783 * @pdev: pointer to PCI device.
12784 * @state: the current PCI connection state.
12785 *
12786 * This routine is called from the PCI subsystem for I/O error handling to
12787 * device with SLI-3 interface spec. This function is called by the PCI
12788 * subsystem after a PCI bus error affecting this device has been detected.
12789 * When this function is invoked, it will need to stop all the I/Os and
12790 * interrupt(s) to the device. Once that is done, it will return
12791 * PCI_ERS_RESULT_NEED_RESET for the PCI subsystem to perform proper recovery
12792 * as desired.
12793 *
12794 * Return codes
0d878419 12795 * PCI_ERS_RESULT_CAN_RECOVER - can be recovered with reset_link
da0436e9
JS
12796 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
12797 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
12798 **/
12799static pci_ers_result_t
12800lpfc_io_error_detected_s3(struct pci_dev *pdev, pci_channel_state_t state)
12801{
12802 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12803 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
da0436e9 12804
0d878419
JS
12805 switch (state) {
12806 case pci_channel_io_normal:
891478a2
JS
12807 /* Non-fatal error, prepare for recovery */
12808 lpfc_sli_prep_dev_for_recover(phba);
0d878419
JS
12809 return PCI_ERS_RESULT_CAN_RECOVER;
12810 case pci_channel_io_frozen:
12811 /* Fatal error, prepare for slot reset */
12812 lpfc_sli_prep_dev_for_reset(phba);
12813 return PCI_ERS_RESULT_NEED_RESET;
12814 case pci_channel_io_perm_failure:
12815 /* Permanent failure, prepare for device down */
75baf696 12816 lpfc_sli_prep_dev_for_perm_failure(phba);
da0436e9 12817 return PCI_ERS_RESULT_DISCONNECT;
0d878419
JS
12818 default:
12819 /* Unknown state, prepare and request slot reset */
372c187b 12820 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0d878419
JS
12821 "0472 Unknown PCI error state: x%x\n", state);
12822 lpfc_sli_prep_dev_for_reset(phba);
12823 return PCI_ERS_RESULT_NEED_RESET;
da0436e9 12824 }
da0436e9
JS
12825}
12826
12827/**
12828 * lpfc_io_slot_reset_s3 - Method for restarting PCI SLI-3 device from scratch.
12829 * @pdev: pointer to PCI device.
12830 *
12831 * This routine is called from the PCI subsystem for error handling to
12832 * device with SLI-3 interface spec. This is called after PCI bus has been
12833 * reset to restart the PCI card from scratch, as if from a cold-boot.
12834 * During the PCI subsystem error recovery, after driver returns
12835 * PCI_ERS_RESULT_NEED_RESET, the PCI subsystem will perform proper error
12836 * recovery and then call this routine before calling the .resume method
12837 * to recover the device. This function will initialize the HBA device,
12838 * enable the interrupt, but it will just put the HBA to offline state
12839 * without passing any I/O traffic.
12840 *
12841 * Return codes
12842 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
12843 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
12844 */
12845static pci_ers_result_t
12846lpfc_io_slot_reset_s3(struct pci_dev *pdev)
12847{
12848 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12849 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12850 struct lpfc_sli *psli = &phba->sli;
12851 uint32_t intr_mode;
12852
12853 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
12854 if (pci_enable_device_mem(pdev)) {
12855 printk(KERN_ERR "lpfc: Cannot re-enable "
12856 "PCI device after reset.\n");
12857 return PCI_ERS_RESULT_DISCONNECT;
12858 }
12859
12860 pci_restore_state(pdev);
1dfb5a47
JS
12861
12862 /*
12863 * As the new kernel behavior of pci_restore_state() API call clears
12864 * device saved_state flag, need to save the restored state again.
12865 */
12866 pci_save_state(pdev);
12867
da0436e9
JS
12868 if (pdev->is_busmaster)
12869 pci_set_master(pdev);
12870
12871 spin_lock_irq(&phba->hbalock);
12872 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
12873 spin_unlock_irq(&phba->hbalock);
12874
12875 /* Configure and enable interrupt */
12876 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
12877 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 12878 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
12879 "0427 Cannot re-enable interrupt after "
12880 "slot reset.\n");
12881 return PCI_ERS_RESULT_DISCONNECT;
12882 } else
12883 phba->intr_mode = intr_mode;
12884
75baf696 12885 /* Take device offline, it will perform cleanup */
618a5230 12886 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
da0436e9
JS
12887 lpfc_offline(phba);
12888 lpfc_sli_brdrestart(phba);
12889
12890 /* Log the current active interrupt mode */
12891 lpfc_log_intr_mode(phba, phba->intr_mode);
12892
12893 return PCI_ERS_RESULT_RECOVERED;
12894}
12895
12896/**
12897 * lpfc_io_resume_s3 - Method for resuming PCI I/O operation on SLI-3 device.
12898 * @pdev: pointer to PCI device
12899 *
12900 * This routine is called from the PCI subsystem for error handling to device
12901 * with SLI-3 interface spec. It is called when kernel error recovery tells
12902 * the lpfc driver that it is ok to resume normal PCI operation after PCI bus
12903 * error recovery. After this call, traffic can start to flow from this device
12904 * again.
12905 */
12906static void
12907lpfc_io_resume_s3(struct pci_dev *pdev)
12908{
12909 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12910 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
3772a991 12911
e2af0d2e 12912 /* Bring device online, it will be no-op for non-fatal error resume */
da0436e9
JS
12913 lpfc_online(phba);
12914}
3772a991 12915
da0436e9
JS
12916/**
12917 * lpfc_sli4_get_els_iocb_cnt - Calculate the # of ELS IOCBs to reserve
12918 * @phba: pointer to lpfc hba data structure.
12919 *
12920 * returns the number of ELS/CT IOCBs to reserve
12921 **/
12922int
12923lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *phba)
12924{
12925 int max_xri = phba->sli4_hba.max_cfg_param.max_xri;
12926
f1126688
JS
12927 if (phba->sli_rev == LPFC_SLI_REV4) {
12928 if (max_xri <= 100)
6a9c52cf 12929 return 10;
f1126688 12930 else if (max_xri <= 256)
6a9c52cf 12931 return 25;
f1126688 12932 else if (max_xri <= 512)
6a9c52cf 12933 return 50;
f1126688 12934 else if (max_xri <= 1024)
6a9c52cf 12935 return 100;
8a9d2e80 12936 else if (max_xri <= 1536)
6a9c52cf 12937 return 150;
8a9d2e80
JS
12938 else if (max_xri <= 2048)
12939 return 200;
12940 else
12941 return 250;
f1126688
JS
12942 } else
12943 return 0;
3772a991
JS
12944}
12945
895427bd
JS
12946/**
12947 * lpfc_sli4_get_iocb_cnt - Calculate the # of total IOCBs to reserve
12948 * @phba: pointer to lpfc hba data structure.
12949 *
f358dd0c 12950 * returns the number of ELS/CT + NVMET IOCBs to reserve
895427bd
JS
12951 **/
12952int
12953lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba)
12954{
12955 int max_xri = lpfc_sli4_get_els_iocb_cnt(phba);
12956
f358dd0c
JS
12957 if (phba->nvmet_support)
12958 max_xri += LPFC_NVMET_BUF_POST;
895427bd
JS
12959 return max_xri;
12960}
12961
12962
0a5ce731 12963static int
1feb8204
JS
12964lpfc_log_write_firmware_error(struct lpfc_hba *phba, uint32_t offset,
12965 uint32_t magic_number, uint32_t ftype, uint32_t fid, uint32_t fsize,
12966 const struct firmware *fw)
12967{
0a5ce731
JS
12968 int rc;
12969
12970 /* Three cases: (1) FW was not supported on the detected adapter.
12971 * (2) FW update has been locked out administratively.
12972 * (3) Some other error during FW update.
12973 * In each case, an unmaskable message is written to the console
12974 * for admin diagnosis.
12975 */
12976 if (offset == ADD_STATUS_FW_NOT_SUPPORTED ||
a72d56b2 12977 (phba->pcidev->device == PCI_DEVICE_ID_LANCER_G6_FC &&
5792a0e8 12978 magic_number != MAGIC_NUMBER_G6) ||
a72d56b2 12979 (phba->pcidev->device == PCI_DEVICE_ID_LANCER_G7_FC &&
5792a0e8 12980 magic_number != MAGIC_NUMBER_G7)) {
372c187b 12981 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731
JS
12982 "3030 This firmware version is not supported on"
12983 " this HBA model. Device:%x Magic:%x Type:%x "
12984 "ID:%x Size %d %zd\n",
12985 phba->pcidev->device, magic_number, ftype, fid,
12986 fsize, fw->size);
12987 rc = -EINVAL;
12988 } else if (offset == ADD_STATUS_FW_DOWNLOAD_HW_DISABLED) {
372c187b 12989 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731
JS
12990 "3021 Firmware downloads have been prohibited "
12991 "by a system configuration setting on "
12992 "Device:%x Magic:%x Type:%x ID:%x Size %d "
12993 "%zd\n",
12994 phba->pcidev->device, magic_number, ftype, fid,
12995 fsize, fw->size);
12996 rc = -EACCES;
12997 } else {
372c187b 12998 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731
JS
12999 "3022 FW Download failed. Add Status x%x "
13000 "Device:%x Magic:%x Type:%x ID:%x Size %d "
13001 "%zd\n",
13002 offset, phba->pcidev->device, magic_number,
13003 ftype, fid, fsize, fw->size);
13004 rc = -EIO;
13005 }
13006 return rc;
1feb8204
JS
13007}
13008
52d52440
JS
13009/**
13010 * lpfc_write_firmware - attempt to write a firmware image to the port
52d52440 13011 * @fw: pointer to firmware image returned from request_firmware.
0a5ce731 13012 * @context: pointer to firmware image returned from request_firmware.
52d52440 13013 *
52d52440 13014 **/
ce396282
JS
13015static void
13016lpfc_write_firmware(const struct firmware *fw, void *context)
52d52440 13017{
ce396282 13018 struct lpfc_hba *phba = (struct lpfc_hba *)context;
6b5151fd 13019 char fwrev[FW_REV_STR_SIZE];
ce396282 13020 struct lpfc_grp_hdr *image;
52d52440
JS
13021 struct list_head dma_buffer_list;
13022 int i, rc = 0;
13023 struct lpfc_dmabuf *dmabuf, *next;
13024 uint32_t offset = 0, temp_offset = 0;
6b6ef5db 13025 uint32_t magic_number, ftype, fid, fsize;
52d52440 13026
c71ab861 13027 /* It can be null in no-wait mode, sanity check */
ce396282
JS
13028 if (!fw) {
13029 rc = -ENXIO;
13030 goto out;
13031 }
13032 image = (struct lpfc_grp_hdr *)fw->data;
13033
6b6ef5db
JS
13034 magic_number = be32_to_cpu(image->magic_number);
13035 ftype = bf_get_be32(lpfc_grp_hdr_file_type, image);
1feb8204 13036 fid = bf_get_be32(lpfc_grp_hdr_id, image);
6b6ef5db
JS
13037 fsize = be32_to_cpu(image->size);
13038
52d52440 13039 INIT_LIST_HEAD(&dma_buffer_list);
52d52440 13040 lpfc_decode_firmware_rev(phba, fwrev, 1);
88a2cfbb 13041 if (strncmp(fwrev, image->revision, strnlen(image->revision, 16))) {
372c187b 13042 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
ce396282 13043 "3023 Updating Firmware, Current Version:%s "
52d52440 13044 "New Version:%s\n",
88a2cfbb 13045 fwrev, image->revision);
52d52440
JS
13046 for (i = 0; i < LPFC_MBX_WR_CONFIG_MAX_BDE; i++) {
13047 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf),
13048 GFP_KERNEL);
13049 if (!dmabuf) {
13050 rc = -ENOMEM;
ce396282 13051 goto release_out;
52d52440
JS
13052 }
13053 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
13054 SLI4_PAGE_SIZE,
13055 &dmabuf->phys,
13056 GFP_KERNEL);
13057 if (!dmabuf->virt) {
13058 kfree(dmabuf);
13059 rc = -ENOMEM;
ce396282 13060 goto release_out;
52d52440
JS
13061 }
13062 list_add_tail(&dmabuf->list, &dma_buffer_list);
13063 }
13064 while (offset < fw->size) {
13065 temp_offset = offset;
13066 list_for_each_entry(dmabuf, &dma_buffer_list, list) {
079b5c91 13067 if (temp_offset + SLI4_PAGE_SIZE > fw->size) {
52d52440
JS
13068 memcpy(dmabuf->virt,
13069 fw->data + temp_offset,
079b5c91
JS
13070 fw->size - temp_offset);
13071 temp_offset = fw->size;
52d52440
JS
13072 break;
13073 }
52d52440
JS
13074 memcpy(dmabuf->virt, fw->data + temp_offset,
13075 SLI4_PAGE_SIZE);
88a2cfbb 13076 temp_offset += SLI4_PAGE_SIZE;
52d52440
JS
13077 }
13078 rc = lpfc_wr_object(phba, &dma_buffer_list,
13079 (fw->size - offset), &offset);
1feb8204 13080 if (rc) {
0a5ce731
JS
13081 rc = lpfc_log_write_firmware_error(phba, offset,
13082 magic_number,
13083 ftype,
13084 fid,
13085 fsize,
13086 fw);
ce396282 13087 goto release_out;
1feb8204 13088 }
52d52440
JS
13089 }
13090 rc = offset;
1feb8204 13091 } else
372c187b 13092 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1feb8204
JS
13093 "3029 Skipped Firmware update, Current "
13094 "Version:%s New Version:%s\n",
13095 fwrev, image->revision);
ce396282
JS
13096
13097release_out:
52d52440
JS
13098 list_for_each_entry_safe(dmabuf, next, &dma_buffer_list, list) {
13099 list_del(&dmabuf->list);
13100 dma_free_coherent(&phba->pcidev->dev, SLI4_PAGE_SIZE,
13101 dmabuf->virt, dmabuf->phys);
13102 kfree(dmabuf);
13103 }
ce396282
JS
13104 release_firmware(fw);
13105out:
0a5ce731 13106 if (rc < 0)
372c187b 13107 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731
JS
13108 "3062 Firmware update error, status %d.\n", rc);
13109 else
372c187b 13110 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731 13111 "3024 Firmware update success: size %d.\n", rc);
52d52440
JS
13112}
13113
c71ab861
JS
13114/**
13115 * lpfc_sli4_request_firmware_update - Request linux generic firmware upgrade
13116 * @phba: pointer to lpfc hba data structure.
fe614acd 13117 * @fw_upgrade: which firmware to update.
c71ab861
JS
13118 *
13119 * This routine is called to perform Linux generic firmware upgrade on device
13120 * that supports such feature.
13121 **/
13122int
13123lpfc_sli4_request_firmware_update(struct lpfc_hba *phba, uint8_t fw_upgrade)
13124{
13125 uint8_t file_name[ELX_MODEL_NAME_SIZE];
13126 int ret;
13127 const struct firmware *fw;
13128
13129 /* Only supported on SLI4 interface type 2 for now */
27d6ac0a 13130 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) <
c71ab861
JS
13131 LPFC_SLI_INTF_IF_TYPE_2)
13132 return -EPERM;
13133
13134 snprintf(file_name, ELX_MODEL_NAME_SIZE, "%s.grp", phba->ModelName);
13135
13136 if (fw_upgrade == INT_FW_UPGRADE) {
13137 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
13138 file_name, &phba->pcidev->dev,
13139 GFP_KERNEL, (void *)phba,
13140 lpfc_write_firmware);
13141 } else if (fw_upgrade == RUN_FW_UPGRADE) {
13142 ret = request_firmware(&fw, file_name, &phba->pcidev->dev);
13143 if (!ret)
13144 lpfc_write_firmware(fw, (void *)phba);
13145 } else {
13146 ret = -EINVAL;
13147 }
13148
13149 return ret;
13150}
13151
3772a991 13152/**
da0436e9 13153 * lpfc_pci_probe_one_s4 - PCI probe func to reg SLI-4 device to PCI subsys
3772a991
JS
13154 * @pdev: pointer to PCI device
13155 * @pid: pointer to PCI device identifier
13156 *
da0436e9
JS
13157 * This routine is called from the kernel's PCI subsystem to device with
13158 * SLI-4 interface spec. When an Emulex HBA with SLI-4 interface spec is
3772a991 13159 * presented on PCI bus, the kernel PCI subsystem looks at PCI device-specific
da0436e9
JS
13160 * information of the device and driver to see if the driver state that it
13161 * can support this kind of device. If the match is successful, the driver
13162 * core invokes this routine. If this routine determines it can claim the HBA,
13163 * it does all the initialization that it needs to do to handle the HBA
13164 * properly.
3772a991
JS
13165 *
13166 * Return code
13167 * 0 - driver can claim the device
13168 * negative value - driver can not claim the device
13169 **/
6f039790 13170static int
da0436e9 13171lpfc_pci_probe_one_s4(struct pci_dev *pdev, const struct pci_device_id *pid)
3772a991
JS
13172{
13173 struct lpfc_hba *phba;
13174 struct lpfc_vport *vport = NULL;
6669f9bb 13175 struct Scsi_Host *shost = NULL;
6c621a22 13176 int error;
3772a991
JS
13177 uint32_t cfg_mode, intr_mode;
13178
13179 /* Allocate memory for HBA structure */
13180 phba = lpfc_hba_alloc(pdev);
13181 if (!phba)
13182 return -ENOMEM;
13183
13184 /* Perform generic PCI device enabling operation */
13185 error = lpfc_enable_pci_dev(phba);
079b5c91 13186 if (error)
3772a991 13187 goto out_free_phba;
3772a991 13188
da0436e9
JS
13189 /* Set up SLI API function jump table for PCI-device group-1 HBAs */
13190 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_OC);
3772a991
JS
13191 if (error)
13192 goto out_disable_pci_dev;
13193
da0436e9
JS
13194 /* Set up SLI-4 specific device PCI memory space */
13195 error = lpfc_sli4_pci_mem_setup(phba);
3772a991
JS
13196 if (error) {
13197 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 13198 "1410 Failed to set up pci memory space.\n");
3772a991
JS
13199 goto out_disable_pci_dev;
13200 }
13201
da0436e9
JS
13202 /* Set up SLI-4 Specific device driver resources */
13203 error = lpfc_sli4_driver_resource_setup(phba);
3772a991
JS
13204 if (error) {
13205 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9
JS
13206 "1412 Failed to set up driver resource.\n");
13207 goto out_unset_pci_mem_s4;
3772a991
JS
13208 }
13209
19ca7609 13210 INIT_LIST_HEAD(&phba->active_rrq_list);
7d791df7 13211 INIT_LIST_HEAD(&phba->fcf.fcf_pri_list);
19ca7609 13212
3772a991
JS
13213 /* Set up common device driver resources */
13214 error = lpfc_setup_driver_resource_phase2(phba);
13215 if (error) {
13216 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 13217 "1414 Failed to set up driver resource.\n");
6c621a22 13218 goto out_unset_driver_resource_s4;
3772a991
JS
13219 }
13220
079b5c91
JS
13221 /* Get the default values for Model Name and Description */
13222 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
13223
3772a991 13224 /* Now, trying to enable interrupt and bring up the device */
5b75da2f 13225 cfg_mode = phba->cfg_use_msi;
5b75da2f 13226
7b15db32 13227 /* Put device to a known state before enabling interrupt */
cdb42bec 13228 phba->pport = NULL;
7b15db32 13229 lpfc_stop_port(phba);
895427bd 13230
dcaa2136
JS
13231 /* Init cpu_map array */
13232 lpfc_cpu_map_array_init(phba);
13233
13234 /* Init hba_eq_hdl array */
13235 lpfc_hba_eq_hdl_array_init(phba);
13236
7b15db32
JS
13237 /* Configure and enable interrupt */
13238 intr_mode = lpfc_sli4_enable_intr(phba, cfg_mode);
13239 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 13240 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
7b15db32
JS
13241 "0426 Failed to enable interrupt.\n");
13242 error = -ENODEV;
cdb42bec 13243 goto out_unset_driver_resource;
7b15db32
JS
13244 }
13245 /* Default to single EQ for non-MSI-X */
895427bd 13246 if (phba->intr_type != MSIX) {
6a828b0f 13247 phba->cfg_irq_chann = 1;
2d7dbc4c 13248 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
2d7dbc4c
JS
13249 if (phba->nvmet_support)
13250 phba->cfg_nvmet_mrq = 1;
13251 }
cdb42bec 13252 }
6a828b0f 13253 lpfc_cpu_affinity_check(phba, phba->cfg_irq_chann);
cdb42bec
JS
13254
13255 /* Create SCSI host to the physical port */
13256 error = lpfc_create_shost(phba);
13257 if (error) {
13258 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13259 "1415 Failed to create scsi host.\n");
13260 goto out_disable_intr;
13261 }
13262 vport = phba->pport;
13263 shost = lpfc_shost_from_vport(vport); /* save shost for error cleanup */
13264
13265 /* Configure sysfs attributes */
13266 error = lpfc_alloc_sysfs_attr(vport);
13267 if (error) {
13268 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13269 "1416 Failed to allocate sysfs attr\n");
13270 goto out_destroy_shost;
895427bd
JS
13271 }
13272
7b15db32
JS
13273 /* Set up SLI-4 HBA */
13274 if (lpfc_sli4_hba_setup(phba)) {
372c187b 13275 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
7b15db32
JS
13276 "1421 Failed to set up hba\n");
13277 error = -ENODEV;
cdb42bec 13278 goto out_free_sysfs_attr;
98c9ea5c 13279 }
858c9f6c 13280
7b15db32
JS
13281 /* Log the current active interrupt mode */
13282 phba->intr_mode = intr_mode;
13283 lpfc_log_intr_mode(phba, intr_mode);
13284
3772a991
JS
13285 /* Perform post initialization setup */
13286 lpfc_post_init_setup(phba);
dea3101e 13287
01649561
JS
13288 /* NVME support in FW earlier in the driver load corrects the
13289 * FC4 type making a check for nvme_support unnecessary.
13290 */
0794d601
JS
13291 if (phba->nvmet_support == 0) {
13292 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
13293 /* Create NVME binding with nvme_fc_transport. This
13294 * ensures the vport is initialized. If the localport
13295 * create fails, it should not unload the driver to
13296 * support field issues.
13297 */
13298 error = lpfc_nvme_create_localport(vport);
13299 if (error) {
372c187b 13300 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0794d601
JS
13301 "6004 NVME registration "
13302 "failed, error x%x\n",
13303 error);
13304 }
01649561
JS
13305 }
13306 }
895427bd 13307
c71ab861
JS
13308 /* check for firmware upgrade or downgrade */
13309 if (phba->cfg_request_firmware_upgrade)
db6f1c2f 13310 lpfc_sli4_request_firmware_update(phba, INT_FW_UPGRADE);
52d52440 13311
1c6834a7
JS
13312 /* Check if there are static vports to be created. */
13313 lpfc_create_static_vport(phba);
d2cc9bcd
JS
13314
13315 /* Enable RAS FW log support */
13316 lpfc_sli4_ras_setup(phba);
13317
93a4d6f4 13318 INIT_LIST_HEAD(&phba->poll_list);
f861f596 13319 timer_setup(&phba->cpuhp_poll_timer, lpfc_sli4_poll_hbtimer, 0);
93a4d6f4
JS
13320 cpuhp_state_add_instance_nocalls(lpfc_cpuhp_state, &phba->cpuhp);
13321
dea3101e 13322 return 0;
13323
5b75da2f
JS
13324out_free_sysfs_attr:
13325 lpfc_free_sysfs_attr(vport);
3772a991
JS
13326out_destroy_shost:
13327 lpfc_destroy_shost(phba);
cdb42bec
JS
13328out_disable_intr:
13329 lpfc_sli4_disable_intr(phba);
3772a991
JS
13330out_unset_driver_resource:
13331 lpfc_unset_driver_resource_phase2(phba);
da0436e9
JS
13332out_unset_driver_resource_s4:
13333 lpfc_sli4_driver_resource_unset(phba);
13334out_unset_pci_mem_s4:
13335 lpfc_sli4_pci_mem_unset(phba);
3772a991
JS
13336out_disable_pci_dev:
13337 lpfc_disable_pci_dev(phba);
6669f9bb
JS
13338 if (shost)
13339 scsi_host_put(shost);
2e0fef85 13340out_free_phba:
3772a991 13341 lpfc_hba_free(phba);
dea3101e 13342 return error;
13343}
13344
e59058c4 13345/**
da0436e9 13346 * lpfc_pci_remove_one_s4 - PCI func to unreg SLI-4 device from PCI subsystem
e59058c4
JS
13347 * @pdev: pointer to PCI device
13348 *
da0436e9
JS
13349 * This routine is called from the kernel's PCI subsystem to device with
13350 * SLI-4 interface spec. When an Emulex HBA with SLI-4 interface spec is
3772a991
JS
13351 * removed from PCI bus, it performs all the necessary cleanup for the HBA
13352 * device to be removed from the PCI subsystem properly.
e59058c4 13353 **/
6f039790 13354static void
da0436e9 13355lpfc_pci_remove_one_s4(struct pci_dev *pdev)
dea3101e 13356{
da0436e9 13357 struct Scsi_Host *shost = pci_get_drvdata(pdev);
2e0fef85 13358 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
eada272d 13359 struct lpfc_vport **vports;
da0436e9 13360 struct lpfc_hba *phba = vport->phba;
eada272d 13361 int i;
8a4df120 13362
da0436e9 13363 /* Mark the device unloading flag */
549e55cd 13364 spin_lock_irq(&phba->hbalock);
51ef4c26 13365 vport->load_flag |= FC_UNLOADING;
549e55cd 13366 spin_unlock_irq(&phba->hbalock);
2e0fef85 13367
da0436e9 13368 /* Free the HBA sysfs attributes */
858c9f6c
JS
13369 lpfc_free_sysfs_attr(vport);
13370
eada272d
JS
13371 /* Release all the vports against this physical port */
13372 vports = lpfc_create_vport_work_array(phba);
13373 if (vports != NULL)
587a37f6
JS
13374 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
13375 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
13376 continue;
eada272d 13377 fc_vport_terminate(vports[i]->fc_vport);
587a37f6 13378 }
eada272d
JS
13379 lpfc_destroy_vport_work_array(phba, vports);
13380
13381 /* Remove FC host and then SCSI host with the physical port */
858c9f6c
JS
13382 fc_remove_host(shost);
13383 scsi_remove_host(shost);
da0436e9 13384
d613b6a7
JS
13385 /* Perform ndlp cleanup on the physical port. The nvme and nvmet
13386 * localports are destroyed after to cleanup all transport memory.
895427bd 13387 */
87af33fe 13388 lpfc_cleanup(vport);
d613b6a7
JS
13389 lpfc_nvmet_destroy_targetport(phba);
13390 lpfc_nvme_destroy_localport(vport);
87af33fe 13391
c490850a
JS
13392 /* De-allocate multi-XRI pools */
13393 if (phba->cfg_xri_rebalancing)
13394 lpfc_destroy_multixri_pools(phba);
13395
281d6190
JS
13396 /*
13397 * Bring down the SLI Layer. This step disables all interrupts,
13398 * clears the rings, discards all mailbox commands, and resets
13399 * the HBA FCoE function.
13400 */
13401 lpfc_debugfs_terminate(vport);
a257bf90 13402
1901762f 13403 lpfc_stop_hba_timers(phba);
523128e5 13404 spin_lock_irq(&phba->port_list_lock);
858c9f6c 13405 list_del_init(&vport->listentry);
523128e5 13406 spin_unlock_irq(&phba->port_list_lock);
858c9f6c 13407
3677a3a7 13408 /* Perform scsi free before driver resource_unset since scsi
da0436e9 13409 * buffers are released to their corresponding pools here.
2e0fef85 13410 */
5e5b511d 13411 lpfc_io_free(phba);
01649561 13412 lpfc_free_iocb_list(phba);
5e5b511d 13413 lpfc_sli4_hba_unset(phba);
67d12733 13414
0cdb84ec 13415 lpfc_unset_driver_resource_phase2(phba);
da0436e9 13416 lpfc_sli4_driver_resource_unset(phba);
ed957684 13417
da0436e9
JS
13418 /* Unmap adapter Control and Doorbell registers */
13419 lpfc_sli4_pci_mem_unset(phba);
2e0fef85 13420
da0436e9
JS
13421 /* Release PCI resources and disable device's PCI function */
13422 scsi_host_put(shost);
13423 lpfc_disable_pci_dev(phba);
2e0fef85 13424
da0436e9 13425 /* Finally, free the driver's device data structure */
3772a991 13426 lpfc_hba_free(phba);
2e0fef85 13427
da0436e9 13428 return;
dea3101e 13429}
13430
3a55b532 13431/**
da0436e9 13432 * lpfc_pci_suspend_one_s4 - PCI func to suspend SLI-4 device for power mgmnt
3a55b532
JS
13433 * @pdev: pointer to PCI device
13434 * @msg: power management message
13435 *
da0436e9
JS
13436 * This routine is called from the kernel's PCI subsystem to support system
13437 * Power Management (PM) to device with SLI-4 interface spec. When PM invokes
13438 * this method, it quiesces the device by stopping the driver's worker
13439 * thread for the device, turning off device's interrupt and DMA, and bring
13440 * the device offline. Note that as the driver implements the minimum PM
13441 * requirements to a power-aware driver's PM support for suspend/resume -- all
13442 * the possible PM messages (SUSPEND, HIBERNATE, FREEZE) to the suspend()
13443 * method call will be treated as SUSPEND and the driver will fully
13444 * reinitialize its device during resume() method call, the driver will set
13445 * device to PCI_D3hot state in PCI config space instead of setting it
3772a991 13446 * according to the @msg provided by the PM.
3a55b532
JS
13447 *
13448 * Return code
3772a991
JS
13449 * 0 - driver suspended the device
13450 * Error otherwise
3a55b532
JS
13451 **/
13452static int
da0436e9 13453lpfc_pci_suspend_one_s4(struct pci_dev *pdev, pm_message_t msg)
3a55b532
JS
13454{
13455 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13456 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13457
13458 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
75baf696 13459 "2843 PCI device Power Management suspend.\n");
3a55b532
JS
13460
13461 /* Bring down the device */
618a5230 13462 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
3a55b532
JS
13463 lpfc_offline(phba);
13464 kthread_stop(phba->worker_thread);
13465
13466 /* Disable interrupt from device */
da0436e9 13467 lpfc_sli4_disable_intr(phba);
5350d872 13468 lpfc_sli4_queue_destroy(phba);
3a55b532
JS
13469
13470 /* Save device state to PCI config space */
13471 pci_save_state(pdev);
13472 pci_set_power_state(pdev, PCI_D3hot);
13473
13474 return 0;
13475}
13476
13477/**
da0436e9 13478 * lpfc_pci_resume_one_s4 - PCI func to resume SLI-4 device for power mgmnt
3a55b532
JS
13479 * @pdev: pointer to PCI device
13480 *
da0436e9
JS
13481 * This routine is called from the kernel's PCI subsystem to support system
13482 * Power Management (PM) to device with SLI-4 interface spac. When PM invokes
13483 * this method, it restores the device's PCI config space state and fully
13484 * reinitializes the device and brings it online. Note that as the driver
13485 * implements the minimum PM requirements to a power-aware driver's PM for
13486 * suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE, FREEZE)
13487 * to the suspend() method call will be treated as SUSPEND and the driver
13488 * will fully reinitialize its device during resume() method call, the device
13489 * will be set to PCI_D0 directly in PCI config space before restoring the
13490 * state.
3a55b532
JS
13491 *
13492 * Return code
3772a991
JS
13493 * 0 - driver suspended the device
13494 * Error otherwise
3a55b532
JS
13495 **/
13496static int
da0436e9 13497lpfc_pci_resume_one_s4(struct pci_dev *pdev)
3a55b532
JS
13498{
13499 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13500 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
5b75da2f 13501 uint32_t intr_mode;
3a55b532
JS
13502 int error;
13503
13504 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
da0436e9 13505 "0292 PCI device Power Management resume.\n");
3a55b532
JS
13506
13507 /* Restore device state from PCI config space */
13508 pci_set_power_state(pdev, PCI_D0);
13509 pci_restore_state(pdev);
1dfb5a47
JS
13510
13511 /*
13512 * As the new kernel behavior of pci_restore_state() API call clears
13513 * device saved_state flag, need to save the restored state again.
13514 */
13515 pci_save_state(pdev);
13516
3a55b532
JS
13517 if (pdev->is_busmaster)
13518 pci_set_master(pdev);
13519
da0436e9 13520 /* Startup the kernel thread for this host adapter. */
3a55b532
JS
13521 phba->worker_thread = kthread_run(lpfc_do_work, phba,
13522 "lpfc_worker_%d", phba->brd_no);
13523 if (IS_ERR(phba->worker_thread)) {
13524 error = PTR_ERR(phba->worker_thread);
13525 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 13526 "0293 PM resume failed to start worker "
3a55b532
JS
13527 "thread: error=x%x.\n", error);
13528 return error;
13529 }
13530
5b75da2f 13531 /* Configure and enable interrupt */
da0436e9 13532 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
5b75da2f 13533 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 13534 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 13535 "0294 PM resume Failed to enable interrupt\n");
5b75da2f
JS
13536 return -EIO;
13537 } else
13538 phba->intr_mode = intr_mode;
3a55b532
JS
13539
13540 /* Restart HBA and bring it online */
13541 lpfc_sli_brdrestart(phba);
13542 lpfc_online(phba);
13543
5b75da2f
JS
13544 /* Log the current active interrupt mode */
13545 lpfc_log_intr_mode(phba, phba->intr_mode);
13546
3a55b532
JS
13547 return 0;
13548}
13549
75baf696
JS
13550/**
13551 * lpfc_sli4_prep_dev_for_recover - Prepare SLI4 device for pci slot recover
13552 * @phba: pointer to lpfc hba data structure.
13553 *
13554 * This routine is called to prepare the SLI4 device for PCI slot recover. It
13555 * aborts all the outstanding SCSI I/Os to the pci device.
13556 **/
13557static void
13558lpfc_sli4_prep_dev_for_recover(struct lpfc_hba *phba)
13559{
372c187b 13560 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
13561 "2828 PCI channel I/O abort preparing for recovery\n");
13562 /*
13563 * There may be errored I/Os through HBA, abort all I/Os on txcmplq
13564 * and let the SCSI mid-layer to retry them to recover.
13565 */
db55fba8 13566 lpfc_sli_abort_fcp_rings(phba);
75baf696
JS
13567}
13568
13569/**
13570 * lpfc_sli4_prep_dev_for_reset - Prepare SLI4 device for pci slot reset
13571 * @phba: pointer to lpfc hba data structure.
13572 *
13573 * This routine is called to prepare the SLI4 device for PCI slot reset. It
13574 * disables the device interrupt and pci device, and aborts the internal FCP
13575 * pending I/Os.
13576 **/
13577static void
13578lpfc_sli4_prep_dev_for_reset(struct lpfc_hba *phba)
13579{
372c187b 13580 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
13581 "2826 PCI channel disable preparing for reset\n");
13582
13583 /* Block any management I/Os to the device */
618a5230 13584 lpfc_block_mgmt_io(phba, LPFC_MBX_NO_WAIT);
75baf696
JS
13585
13586 /* Block all SCSI devices' I/Os on the host */
13587 lpfc_scsi_dev_block(phba);
13588
c00f62e6
JS
13589 /* Flush all driver's outstanding I/Os as we are to reset */
13590 lpfc_sli_flush_io_rings(phba);
c3725bdc 13591
75baf696
JS
13592 /* stop all timers */
13593 lpfc_stop_hba_timers(phba);
13594
13595 /* Disable interrupt and pci device */
13596 lpfc_sli4_disable_intr(phba);
5350d872 13597 lpfc_sli4_queue_destroy(phba);
75baf696 13598 pci_disable_device(phba->pcidev);
75baf696
JS
13599}
13600
13601/**
13602 * lpfc_sli4_prep_dev_for_perm_failure - Prepare SLI4 dev for pci slot disable
13603 * @phba: pointer to lpfc hba data structure.
13604 *
13605 * This routine is called to prepare the SLI4 device for PCI slot permanently
13606 * disabling. It blocks the SCSI transport layer traffic and flushes the FCP
13607 * pending I/Os.
13608 **/
13609static void
13610lpfc_sli4_prep_dev_for_perm_failure(struct lpfc_hba *phba)
13611{
372c187b 13612 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
13613 "2827 PCI channel permanent disable for failure\n");
13614
13615 /* Block all SCSI devices' I/Os on the host */
13616 lpfc_scsi_dev_block(phba);
13617
13618 /* stop all timers */
13619 lpfc_stop_hba_timers(phba);
13620
c00f62e6
JS
13621 /* Clean up all driver's outstanding I/Os */
13622 lpfc_sli_flush_io_rings(phba);
75baf696
JS
13623}
13624
8d63f375 13625/**
da0436e9 13626 * lpfc_io_error_detected_s4 - Method for handling PCI I/O error to SLI-4 device
e59058c4
JS
13627 * @pdev: pointer to PCI device.
13628 * @state: the current PCI connection state.
8d63f375 13629 *
da0436e9
JS
13630 * This routine is called from the PCI subsystem for error handling to device
13631 * with SLI-4 interface spec. This function is called by the PCI subsystem
13632 * after a PCI bus error affecting this device has been detected. When this
13633 * function is invoked, it will need to stop all the I/Os and interrupt(s)
13634 * to the device. Once that is done, it will return PCI_ERS_RESULT_NEED_RESET
13635 * for the PCI subsystem to perform proper recovery as desired.
e59058c4
JS
13636 *
13637 * Return codes
3772a991
JS
13638 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
13639 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
e59058c4 13640 **/
3772a991 13641static pci_ers_result_t
da0436e9 13642lpfc_io_error_detected_s4(struct pci_dev *pdev, pci_channel_state_t state)
8d63f375 13643{
75baf696
JS
13644 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13645 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13646
13647 switch (state) {
13648 case pci_channel_io_normal:
13649 /* Non-fatal error, prepare for recovery */
13650 lpfc_sli4_prep_dev_for_recover(phba);
13651 return PCI_ERS_RESULT_CAN_RECOVER;
13652 case pci_channel_io_frozen:
13653 /* Fatal error, prepare for slot reset */
13654 lpfc_sli4_prep_dev_for_reset(phba);
13655 return PCI_ERS_RESULT_NEED_RESET;
13656 case pci_channel_io_perm_failure:
13657 /* Permanent failure, prepare for device down */
13658 lpfc_sli4_prep_dev_for_perm_failure(phba);
13659 return PCI_ERS_RESULT_DISCONNECT;
13660 default:
13661 /* Unknown state, prepare and request slot reset */
372c187b 13662 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
13663 "2825 Unknown PCI error state: x%x\n", state);
13664 lpfc_sli4_prep_dev_for_reset(phba);
13665 return PCI_ERS_RESULT_NEED_RESET;
13666 }
8d63f375
LV
13667}
13668
13669/**
da0436e9 13670 * lpfc_io_slot_reset_s4 - Method for restart PCI SLI-4 device from scratch
e59058c4
JS
13671 * @pdev: pointer to PCI device.
13672 *
da0436e9
JS
13673 * This routine is called from the PCI subsystem for error handling to device
13674 * with SLI-4 interface spec. It is called after PCI bus has been reset to
13675 * restart the PCI card from scratch, as if from a cold-boot. During the
13676 * PCI subsystem error recovery, after the driver returns
3772a991 13677 * PCI_ERS_RESULT_NEED_RESET, the PCI subsystem will perform proper error
da0436e9
JS
13678 * recovery and then call this routine before calling the .resume method to
13679 * recover the device. This function will initialize the HBA device, enable
13680 * the interrupt, but it will just put the HBA to offline state without
13681 * passing any I/O traffic.
8d63f375 13682 *
e59058c4 13683 * Return codes
3772a991
JS
13684 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
13685 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
8d63f375 13686 */
3772a991 13687static pci_ers_result_t
da0436e9 13688lpfc_io_slot_reset_s4(struct pci_dev *pdev)
8d63f375 13689{
75baf696
JS
13690 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13691 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13692 struct lpfc_sli *psli = &phba->sli;
13693 uint32_t intr_mode;
13694
13695 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
13696 if (pci_enable_device_mem(pdev)) {
13697 printk(KERN_ERR "lpfc: Cannot re-enable "
13698 "PCI device after reset.\n");
13699 return PCI_ERS_RESULT_DISCONNECT;
13700 }
13701
13702 pci_restore_state(pdev);
0a96e975
JS
13703
13704 /*
13705 * As the new kernel behavior of pci_restore_state() API call clears
13706 * device saved_state flag, need to save the restored state again.
13707 */
13708 pci_save_state(pdev);
13709
75baf696
JS
13710 if (pdev->is_busmaster)
13711 pci_set_master(pdev);
13712
13713 spin_lock_irq(&phba->hbalock);
13714 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
13715 spin_unlock_irq(&phba->hbalock);
13716
13717 /* Configure and enable interrupt */
13718 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
13719 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 13720 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
13721 "2824 Cannot re-enable interrupt after "
13722 "slot reset.\n");
13723 return PCI_ERS_RESULT_DISCONNECT;
13724 } else
13725 phba->intr_mode = intr_mode;
13726
13727 /* Log the current active interrupt mode */
13728 lpfc_log_intr_mode(phba, phba->intr_mode);
13729
8d63f375
LV
13730 return PCI_ERS_RESULT_RECOVERED;
13731}
13732
13733/**
da0436e9 13734 * lpfc_io_resume_s4 - Method for resuming PCI I/O operation to SLI-4 device
e59058c4 13735 * @pdev: pointer to PCI device
8d63f375 13736 *
3772a991 13737 * This routine is called from the PCI subsystem for error handling to device
da0436e9 13738 * with SLI-4 interface spec. It is called when kernel error recovery tells
3772a991
JS
13739 * the lpfc driver that it is ok to resume normal PCI operation after PCI bus
13740 * error recovery. After this call, traffic can start to flow from this device
13741 * again.
da0436e9 13742 **/
3772a991 13743static void
da0436e9 13744lpfc_io_resume_s4(struct pci_dev *pdev)
8d63f375 13745{
75baf696
JS
13746 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13747 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13748
13749 /*
13750 * In case of slot reset, as function reset is performed through
13751 * mailbox command which needs DMA to be enabled, this operation
13752 * has to be moved to the io resume phase. Taking device offline
13753 * will perform the necessary cleanup.
13754 */
13755 if (!(phba->sli.sli_flag & LPFC_SLI_ACTIVE)) {
13756 /* Perform device reset */
618a5230 13757 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
75baf696
JS
13758 lpfc_offline(phba);
13759 lpfc_sli_brdrestart(phba);
13760 /* Bring the device back online */
13761 lpfc_online(phba);
13762 }
8d63f375
LV
13763}
13764
3772a991
JS
13765/**
13766 * lpfc_pci_probe_one - lpfc PCI probe func to reg dev to PCI subsystem
13767 * @pdev: pointer to PCI device
13768 * @pid: pointer to PCI device identifier
13769 *
13770 * This routine is to be registered to the kernel's PCI subsystem. When an
13771 * Emulex HBA device is presented on PCI bus, the kernel PCI subsystem looks
13772 * at PCI device-specific information of the device and driver to see if the
13773 * driver state that it can support this kind of device. If the match is
13774 * successful, the driver core invokes this routine. This routine dispatches
13775 * the action to the proper SLI-3 or SLI-4 device probing routine, which will
13776 * do all the initialization that it needs to do to handle the HBA device
13777 * properly.
13778 *
13779 * Return code
13780 * 0 - driver can claim the device
13781 * negative value - driver can not claim the device
13782 **/
6f039790 13783static int
3772a991
JS
13784lpfc_pci_probe_one(struct pci_dev *pdev, const struct pci_device_id *pid)
13785{
13786 int rc;
8fa38513 13787 struct lpfc_sli_intf intf;
3772a991 13788
28baac74 13789 if (pci_read_config_dword(pdev, LPFC_SLI_INTF, &intf.word0))
3772a991
JS
13790 return -ENODEV;
13791
8fa38513 13792 if ((bf_get(lpfc_sli_intf_valid, &intf) == LPFC_SLI_INTF_VALID) &&
28baac74 13793 (bf_get(lpfc_sli_intf_slirev, &intf) == LPFC_SLI_INTF_REV_SLI4))
da0436e9 13794 rc = lpfc_pci_probe_one_s4(pdev, pid);
8fa38513 13795 else
3772a991 13796 rc = lpfc_pci_probe_one_s3(pdev, pid);
8fa38513 13797
3772a991
JS
13798 return rc;
13799}
13800
13801/**
13802 * lpfc_pci_remove_one - lpfc PCI func to unreg dev from PCI subsystem
13803 * @pdev: pointer to PCI device
13804 *
13805 * This routine is to be registered to the kernel's PCI subsystem. When an
13806 * Emulex HBA is removed from PCI bus, the driver core invokes this routine.
13807 * This routine dispatches the action to the proper SLI-3 or SLI-4 device
13808 * remove routine, which will perform all the necessary cleanup for the
13809 * device to be removed from the PCI subsystem properly.
13810 **/
6f039790 13811static void
3772a991
JS
13812lpfc_pci_remove_one(struct pci_dev *pdev)
13813{
13814 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13815 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13816
13817 switch (phba->pci_dev_grp) {
13818 case LPFC_PCI_DEV_LP:
13819 lpfc_pci_remove_one_s3(pdev);
13820 break;
da0436e9
JS
13821 case LPFC_PCI_DEV_OC:
13822 lpfc_pci_remove_one_s4(pdev);
13823 break;
3772a991 13824 default:
372c187b 13825 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
13826 "1424 Invalid PCI device group: 0x%x\n",
13827 phba->pci_dev_grp);
13828 break;
13829 }
13830 return;
13831}
13832
13833/**
13834 * lpfc_pci_suspend_one - lpfc PCI func to suspend dev for power management
13835 * @pdev: pointer to PCI device
13836 * @msg: power management message
13837 *
13838 * This routine is to be registered to the kernel's PCI subsystem to support
13839 * system Power Management (PM). When PM invokes this method, it dispatches
13840 * the action to the proper SLI-3 or SLI-4 device suspend routine, which will
13841 * suspend the device.
13842 *
13843 * Return code
13844 * 0 - driver suspended the device
13845 * Error otherwise
13846 **/
13847static int
13848lpfc_pci_suspend_one(struct pci_dev *pdev, pm_message_t msg)
13849{
13850 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13851 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13852 int rc = -ENODEV;
13853
13854 switch (phba->pci_dev_grp) {
13855 case LPFC_PCI_DEV_LP:
13856 rc = lpfc_pci_suspend_one_s3(pdev, msg);
13857 break;
da0436e9
JS
13858 case LPFC_PCI_DEV_OC:
13859 rc = lpfc_pci_suspend_one_s4(pdev, msg);
13860 break;
3772a991 13861 default:
372c187b 13862 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
13863 "1425 Invalid PCI device group: 0x%x\n",
13864 phba->pci_dev_grp);
13865 break;
13866 }
13867 return rc;
13868}
13869
13870/**
13871 * lpfc_pci_resume_one - lpfc PCI func to resume dev for power management
13872 * @pdev: pointer to PCI device
13873 *
13874 * This routine is to be registered to the kernel's PCI subsystem to support
13875 * system Power Management (PM). When PM invokes this method, it dispatches
13876 * the action to the proper SLI-3 or SLI-4 device resume routine, which will
13877 * resume the device.
13878 *
13879 * Return code
13880 * 0 - driver suspended the device
13881 * Error otherwise
13882 **/
13883static int
13884lpfc_pci_resume_one(struct pci_dev *pdev)
13885{
13886 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13887 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13888 int rc = -ENODEV;
13889
13890 switch (phba->pci_dev_grp) {
13891 case LPFC_PCI_DEV_LP:
13892 rc = lpfc_pci_resume_one_s3(pdev);
13893 break;
da0436e9
JS
13894 case LPFC_PCI_DEV_OC:
13895 rc = lpfc_pci_resume_one_s4(pdev);
13896 break;
3772a991 13897 default:
372c187b 13898 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
13899 "1426 Invalid PCI device group: 0x%x\n",
13900 phba->pci_dev_grp);
13901 break;
13902 }
13903 return rc;
13904}
13905
13906/**
13907 * lpfc_io_error_detected - lpfc method for handling PCI I/O error
13908 * @pdev: pointer to PCI device.
13909 * @state: the current PCI connection state.
13910 *
13911 * This routine is registered to the PCI subsystem for error handling. This
13912 * function is called by the PCI subsystem after a PCI bus error affecting
13913 * this device has been detected. When this routine is invoked, it dispatches
13914 * the action to the proper SLI-3 or SLI-4 device error detected handling
13915 * routine, which will perform the proper error detected operation.
13916 *
13917 * Return codes
13918 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
13919 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
13920 **/
13921static pci_ers_result_t
13922lpfc_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
13923{
13924 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13925 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13926 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
13927
13928 switch (phba->pci_dev_grp) {
13929 case LPFC_PCI_DEV_LP:
13930 rc = lpfc_io_error_detected_s3(pdev, state);
13931 break;
da0436e9
JS
13932 case LPFC_PCI_DEV_OC:
13933 rc = lpfc_io_error_detected_s4(pdev, state);
13934 break;
3772a991 13935 default:
372c187b 13936 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
13937 "1427 Invalid PCI device group: 0x%x\n",
13938 phba->pci_dev_grp);
13939 break;
13940 }
13941 return rc;
13942}
13943
13944/**
13945 * lpfc_io_slot_reset - lpfc method for restart PCI dev from scratch
13946 * @pdev: pointer to PCI device.
13947 *
13948 * This routine is registered to the PCI subsystem for error handling. This
13949 * function is called after PCI bus has been reset to restart the PCI card
13950 * from scratch, as if from a cold-boot. When this routine is invoked, it
13951 * dispatches the action to the proper SLI-3 or SLI-4 device reset handling
13952 * routine, which will perform the proper device reset.
13953 *
13954 * Return codes
13955 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
13956 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
13957 **/
13958static pci_ers_result_t
13959lpfc_io_slot_reset(struct pci_dev *pdev)
13960{
13961 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13962 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13963 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
13964
13965 switch (phba->pci_dev_grp) {
13966 case LPFC_PCI_DEV_LP:
13967 rc = lpfc_io_slot_reset_s3(pdev);
13968 break;
da0436e9
JS
13969 case LPFC_PCI_DEV_OC:
13970 rc = lpfc_io_slot_reset_s4(pdev);
13971 break;
3772a991 13972 default:
372c187b 13973 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
13974 "1428 Invalid PCI device group: 0x%x\n",
13975 phba->pci_dev_grp);
13976 break;
13977 }
13978 return rc;
13979}
13980
13981/**
13982 * lpfc_io_resume - lpfc method for resuming PCI I/O operation
13983 * @pdev: pointer to PCI device
13984 *
13985 * This routine is registered to the PCI subsystem for error handling. It
13986 * is called when kernel error recovery tells the lpfc driver that it is
13987 * OK to resume normal PCI operation after PCI bus error recovery. When
13988 * this routine is invoked, it dispatches the action to the proper SLI-3
13989 * or SLI-4 device io_resume routine, which will resume the device operation.
13990 **/
13991static void
13992lpfc_io_resume(struct pci_dev *pdev)
13993{
13994 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13995 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13996
13997 switch (phba->pci_dev_grp) {
13998 case LPFC_PCI_DEV_LP:
13999 lpfc_io_resume_s3(pdev);
14000 break;
da0436e9
JS
14001 case LPFC_PCI_DEV_OC:
14002 lpfc_io_resume_s4(pdev);
14003 break;
3772a991 14004 default:
372c187b 14005 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
14006 "1429 Invalid PCI device group: 0x%x\n",
14007 phba->pci_dev_grp);
14008 break;
14009 }
14010 return;
14011}
14012
1ba981fd
JS
14013/**
14014 * lpfc_sli4_oas_verify - Verify OAS is supported by this adapter
14015 * @phba: pointer to lpfc hba data structure.
14016 *
14017 * This routine checks to see if OAS is supported for this adapter. If
14018 * supported, the configure Flash Optimized Fabric flag is set. Otherwise,
14019 * the enable oas flag is cleared and the pool created for OAS device data
14020 * is destroyed.
14021 *
14022 **/
c7092975 14023static void
1ba981fd
JS
14024lpfc_sli4_oas_verify(struct lpfc_hba *phba)
14025{
14026
14027 if (!phba->cfg_EnableXLane)
14028 return;
14029
14030 if (phba->sli4_hba.pc_sli4_params.oas_supported) {
14031 phba->cfg_fof = 1;
14032 } else {
f38fa0bb 14033 phba->cfg_fof = 0;
c3e5aac3 14034 mempool_destroy(phba->device_data_mem_pool);
1ba981fd
JS
14035 phba->device_data_mem_pool = NULL;
14036 }
14037
14038 return;
14039}
14040
d2cc9bcd
JS
14041/**
14042 * lpfc_sli4_ras_init - Verify RAS-FW log is supported by this adapter
14043 * @phba: pointer to lpfc hba data structure.
14044 *
14045 * This routine checks to see if RAS is supported by the adapter. Check the
14046 * function through which RAS support enablement is to be done.
14047 **/
14048void
14049lpfc_sli4_ras_init(struct lpfc_hba *phba)
14050{
14051 switch (phba->pcidev->device) {
14052 case PCI_DEVICE_ID_LANCER_G6_FC:
14053 case PCI_DEVICE_ID_LANCER_G7_FC:
14054 phba->ras_fwlog.ras_hwsupport = true;
cb34990b
JS
14055 if (phba->cfg_ras_fwlog_func == PCI_FUNC(phba->pcidev->devfn) &&
14056 phba->cfg_ras_fwlog_buffsize)
d2cc9bcd
JS
14057 phba->ras_fwlog.ras_enabled = true;
14058 else
14059 phba->ras_fwlog.ras_enabled = false;
14060 break;
14061 default:
14062 phba->ras_fwlog.ras_hwsupport = false;
14063 }
14064}
14065
1ba981fd 14066
dea3101e 14067MODULE_DEVICE_TABLE(pci, lpfc_id_table);
14068
a55b2d21 14069static const struct pci_error_handlers lpfc_err_handler = {
8d63f375
LV
14070 .error_detected = lpfc_io_error_detected,
14071 .slot_reset = lpfc_io_slot_reset,
14072 .resume = lpfc_io_resume,
14073};
14074
dea3101e 14075static struct pci_driver lpfc_driver = {
14076 .name = LPFC_DRIVER_NAME,
14077 .id_table = lpfc_id_table,
14078 .probe = lpfc_pci_probe_one,
6f039790 14079 .remove = lpfc_pci_remove_one,
85e8a239 14080 .shutdown = lpfc_pci_remove_one,
3a55b532 14081 .suspend = lpfc_pci_suspend_one,
3772a991 14082 .resume = lpfc_pci_resume_one,
2e0fef85 14083 .err_handler = &lpfc_err_handler,
dea3101e 14084};
14085
3ef6d24c 14086static const struct file_operations lpfc_mgmt_fop = {
858feacd 14087 .owner = THIS_MODULE,
3ef6d24c
JS
14088};
14089
14090static struct miscdevice lpfc_mgmt_dev = {
14091 .minor = MISC_DYNAMIC_MINOR,
14092 .name = "lpfcmgmt",
14093 .fops = &lpfc_mgmt_fop,
14094};
14095
e59058c4 14096/**
3621a710 14097 * lpfc_init - lpfc module initialization routine
e59058c4
JS
14098 *
14099 * This routine is to be invoked when the lpfc module is loaded into the
14100 * kernel. The special kernel macro module_init() is used to indicate the
14101 * role of this routine to the kernel as lpfc module entry point.
14102 *
14103 * Return codes
14104 * 0 - successful
14105 * -ENOMEM - FC attach transport failed
14106 * all others - failed
14107 */
dea3101e 14108static int __init
14109lpfc_init(void)
14110{
14111 int error = 0;
14112
bc2736e9
AB
14113 pr_info(LPFC_MODULE_DESC "\n");
14114 pr_info(LPFC_COPYRIGHT "\n");
dea3101e 14115
3ef6d24c
JS
14116 error = misc_register(&lpfc_mgmt_dev);
14117 if (error)
14118 printk(KERN_ERR "Could not register lpfcmgmt device, "
14119 "misc_register returned with status %d", error);
14120
1eaff536 14121 error = -ENOMEM;
458c083e
JS
14122 lpfc_transport_functions.vport_create = lpfc_vport_create;
14123 lpfc_transport_functions.vport_delete = lpfc_vport_delete;
dea3101e 14124 lpfc_transport_template =
14125 fc_attach_transport(&lpfc_transport_functions);
7ee5d43e 14126 if (lpfc_transport_template == NULL)
1eaff536 14127 goto unregister;
458c083e
JS
14128 lpfc_vport_transport_template =
14129 fc_attach_transport(&lpfc_vport_transport_functions);
14130 if (lpfc_vport_transport_template == NULL) {
14131 fc_release_transport(lpfc_transport_template);
1eaff536 14132 goto unregister;
7ee5d43e 14133 }
5fd11085 14134 lpfc_nvme_cmd_template();
bd3061ba 14135 lpfc_nvmet_cmd_template();
7bb03bbf
JS
14136
14137 /* Initialize in case vector mapping is needed */
2ea259ee 14138 lpfc_present_cpu = num_present_cpus();
7bb03bbf 14139
93a4d6f4
JS
14140 error = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
14141 "lpfc/sli4:online",
14142 lpfc_cpu_online, lpfc_cpu_offline);
14143 if (error < 0)
14144 goto cpuhp_failure;
14145 lpfc_cpuhp_state = error;
14146
dea3101e 14147 error = pci_register_driver(&lpfc_driver);
93a4d6f4
JS
14148 if (error)
14149 goto unwind;
14150
14151 return error;
14152
14153unwind:
14154 cpuhp_remove_multi_state(lpfc_cpuhp_state);
14155cpuhp_failure:
14156 fc_release_transport(lpfc_transport_template);
14157 fc_release_transport(lpfc_vport_transport_template);
1eaff536
JX
14158unregister:
14159 misc_deregister(&lpfc_mgmt_dev);
dea3101e 14160
14161 return error;
14162}
14163
372c187b
DK
14164void lpfc_dmp_dbg(struct lpfc_hba *phba)
14165{
14166 unsigned int start_idx;
14167 unsigned int dbg_cnt;
14168 unsigned int temp_idx;
14169 int i;
14170 int j = 0;
14171 unsigned long rem_nsec;
14172
14173 if (phba->cfg_log_verbose)
14174 return;
14175
14176 if (atomic_cmpxchg(&phba->dbg_log_dmping, 0, 1) != 0)
14177 return;
14178
14179 start_idx = (unsigned int)atomic_read(&phba->dbg_log_idx) % DBG_LOG_SZ;
14180 dbg_cnt = (unsigned int)atomic_read(&phba->dbg_log_cnt);
14181 temp_idx = start_idx;
14182 if (dbg_cnt >= DBG_LOG_SZ) {
14183 dbg_cnt = DBG_LOG_SZ;
14184 temp_idx -= 1;
14185 } else {
14186 if ((start_idx + dbg_cnt) > (DBG_LOG_SZ - 1)) {
14187 temp_idx = (start_idx + dbg_cnt) % DBG_LOG_SZ;
14188 } else {
77dd7d7b 14189 if (start_idx < dbg_cnt)
372c187b 14190 start_idx = DBG_LOG_SZ - (dbg_cnt - start_idx);
77dd7d7b 14191 else
372c187b 14192 start_idx -= dbg_cnt;
372c187b
DK
14193 }
14194 }
14195 dev_info(&phba->pcidev->dev, "start %d end %d cnt %d\n",
14196 start_idx, temp_idx, dbg_cnt);
14197
14198 for (i = 0; i < dbg_cnt; i++) {
14199 if ((start_idx + i) < DBG_LOG_SZ)
77dd7d7b 14200 temp_idx = (start_idx + i) % DBG_LOG_SZ;
372c187b
DK
14201 else
14202 temp_idx = j++;
14203 rem_nsec = do_div(phba->dbg_log[temp_idx].t_ns, NSEC_PER_SEC);
14204 dev_info(&phba->pcidev->dev, "%d: [%5lu.%06lu] %s",
14205 temp_idx,
14206 (unsigned long)phba->dbg_log[temp_idx].t_ns,
14207 rem_nsec / 1000,
14208 phba->dbg_log[temp_idx].log);
14209 }
14210 atomic_set(&phba->dbg_log_cnt, 0);
14211 atomic_set(&phba->dbg_log_dmping, 0);
14212}
14213
7fa03c77 14214__printf(2, 3)
372c187b
DK
14215void lpfc_dbg_print(struct lpfc_hba *phba, const char *fmt, ...)
14216{
14217 unsigned int idx;
14218 va_list args;
14219 int dbg_dmping = atomic_read(&phba->dbg_log_dmping);
14220 struct va_format vaf;
14221
14222
14223 va_start(args, fmt);
14224 if (unlikely(dbg_dmping)) {
14225 vaf.fmt = fmt;
14226 vaf.va = &args;
14227 dev_info(&phba->pcidev->dev, "%pV", &vaf);
14228 va_end(args);
14229 return;
14230 }
14231 idx = (unsigned int)atomic_fetch_add(1, &phba->dbg_log_idx) %
14232 DBG_LOG_SZ;
14233
14234 atomic_inc(&phba->dbg_log_cnt);
14235
14236 vscnprintf(phba->dbg_log[idx].log,
14237 sizeof(phba->dbg_log[idx].log), fmt, args);
14238 va_end(args);
14239
14240 phba->dbg_log[idx].t_ns = local_clock();
14241}
14242
e59058c4 14243/**
3621a710 14244 * lpfc_exit - lpfc module removal routine
e59058c4
JS
14245 *
14246 * This routine is invoked when the lpfc module is removed from the kernel.
14247 * The special kernel macro module_exit() is used to indicate the role of
14248 * this routine to the kernel as lpfc module exit point.
14249 */
dea3101e 14250static void __exit
14251lpfc_exit(void)
14252{
3ef6d24c 14253 misc_deregister(&lpfc_mgmt_dev);
dea3101e 14254 pci_unregister_driver(&lpfc_driver);
93a4d6f4 14255 cpuhp_remove_multi_state(lpfc_cpuhp_state);
dea3101e 14256 fc_release_transport(lpfc_transport_template);
458c083e 14257 fc_release_transport(lpfc_vport_transport_template);
7973967f 14258 idr_destroy(&lpfc_hba_index);
dea3101e 14259}
14260
14261module_init(lpfc_init);
14262module_exit(lpfc_exit);
14263MODULE_LICENSE("GPL");
14264MODULE_DESCRIPTION(LPFC_MODULE_DESC);
d080abe0 14265MODULE_AUTHOR("Broadcom");
dea3101e 14266MODULE_VERSION("0:" LPFC_DRIVER_VERSION);