scsi: lpfc: Fix mailbox hang on adapter init
[linux-2.6-block.git] / drivers / scsi / lpfc / lpfc_init.c
CommitLineData
dea3101e 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
0d041215 4 * Copyright (C) 2017-2019 Broadcom. All Rights Reserved. The term *
3e21d1cb 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
50611577 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
c44ce173 7 * EMULEX and SLI are trademarks of Emulex. *
d080abe0 8 * www.broadcom.com *
c44ce173 9 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
dea3101e 10 * *
11 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC
12 * modify it under the terms of version 2 of the GNU General *
13 * Public License as published by the Free Software Foundation. *
14 * This program is distributed in the hope that it will be useful. *
15 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
16 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
18 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
19 * TO BE LEGALLY INVALID. See the GNU General Public License for *
20 * more details, a copy of which can be found in the file COPYING *
21 * included with this package. *
dea3101e 22 *******************************************************************/
23
dea3101e 24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/idr.h>
28#include <linux/interrupt.h>
acf3368f 29#include <linux/module.h>
dea3101e 30#include <linux/kthread.h>
31#include <linux/pci.h>
32#include <linux/spinlock.h>
92d7f7b0 33#include <linux/ctype.h>
0d878419 34#include <linux/aer.h>
5a0e3ad6 35#include <linux/slab.h>
52d52440 36#include <linux/firmware.h>
3ef6d24c 37#include <linux/miscdevice.h>
7bb03bbf 38#include <linux/percpu.h>
895427bd 39#include <linux/msi.h>
6a828b0f 40#include <linux/irq.h>
286871a6 41#include <linux/bitops.h>
dea3101e 42
91886523 43#include <scsi/scsi.h>
dea3101e 44#include <scsi/scsi_device.h>
45#include <scsi/scsi_host.h>
46#include <scsi/scsi_transport_fc.h>
86c67379
JS
47#include <scsi/scsi_tcq.h>
48#include <scsi/fc/fc_fs.h>
49
50#include <linux/nvme-fc-driver.h>
dea3101e 51
da0436e9 52#include "lpfc_hw4.h"
dea3101e 53#include "lpfc_hw.h"
54#include "lpfc_sli.h"
da0436e9 55#include "lpfc_sli4.h"
ea2151b4 56#include "lpfc_nl.h"
dea3101e 57#include "lpfc_disc.h"
dea3101e 58#include "lpfc.h"
895427bd
JS
59#include "lpfc_scsi.h"
60#include "lpfc_nvme.h"
86c67379 61#include "lpfc_nvmet.h"
dea3101e 62#include "lpfc_logmsg.h"
63#include "lpfc_crtn.h"
92d7f7b0 64#include "lpfc_vport.h"
dea3101e 65#include "lpfc_version.h"
12f44457 66#include "lpfc_ids.h"
dea3101e 67
81301a9b
JS
68char *_dump_buf_data;
69unsigned long _dump_buf_data_order;
70char *_dump_buf_dif;
71unsigned long _dump_buf_dif_order;
72spinlock_t _dump_buf_lock;
73
7bb03bbf 74/* Used when mapping IRQ vectors in a driver centric manner */
b246de17 75uint32_t lpfc_present_cpu;
7bb03bbf 76
dea3101e 77static void lpfc_get_hba_model_desc(struct lpfc_hba *, uint8_t *, uint8_t *);
78static int lpfc_post_rcv_buf(struct lpfc_hba *);
5350d872 79static int lpfc_sli4_queue_verify(struct lpfc_hba *);
da0436e9
JS
80static int lpfc_create_bootstrap_mbox(struct lpfc_hba *);
81static int lpfc_setup_endian_order(struct lpfc_hba *);
da0436e9 82static void lpfc_destroy_bootstrap_mbox(struct lpfc_hba *);
8a9d2e80 83static void lpfc_free_els_sgl_list(struct lpfc_hba *);
f358dd0c 84static void lpfc_free_nvmet_sgl_list(struct lpfc_hba *);
8a9d2e80 85static void lpfc_init_sgl_list(struct lpfc_hba *);
da0436e9
JS
86static int lpfc_init_active_sgl_array(struct lpfc_hba *);
87static void lpfc_free_active_sgl(struct lpfc_hba *);
88static int lpfc_hba_down_post_s3(struct lpfc_hba *phba);
89static int lpfc_hba_down_post_s4(struct lpfc_hba *phba);
90static int lpfc_sli4_cq_event_pool_create(struct lpfc_hba *);
91static void lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *);
92static void lpfc_sli4_cq_event_release_all(struct lpfc_hba *);
618a5230
JS
93static void lpfc_sli4_disable_intr(struct lpfc_hba *);
94static uint32_t lpfc_sli4_enable_intr(struct lpfc_hba *, uint32_t);
1ba981fd 95static void lpfc_sli4_oas_verify(struct lpfc_hba *phba);
6a828b0f
JS
96static uint16_t lpfc_find_eq_handle(struct lpfc_hba *, uint16_t);
97static uint16_t lpfc_find_cpu_handle(struct lpfc_hba *, uint16_t, int);
dea3101e 98
99static struct scsi_transport_template *lpfc_transport_template = NULL;
92d7f7b0 100static struct scsi_transport_template *lpfc_vport_transport_template = NULL;
dea3101e 101static DEFINE_IDR(lpfc_hba_index);
f358dd0c 102#define LPFC_NVMET_BUF_POST 254
dea3101e 103
e59058c4 104/**
3621a710 105 * lpfc_config_port_prep - Perform lpfc initialization prior to config port
e59058c4
JS
106 * @phba: pointer to lpfc hba data structure.
107 *
108 * This routine will do LPFC initialization prior to issuing the CONFIG_PORT
109 * mailbox command. It retrieves the revision information from the HBA and
110 * collects the Vital Product Data (VPD) about the HBA for preparing the
111 * configuration of the HBA.
112 *
113 * Return codes:
114 * 0 - success.
115 * -ERESTART - requests the SLI layer to reset the HBA and try again.
116 * Any other value - indicates an error.
117 **/
dea3101e 118int
2e0fef85 119lpfc_config_port_prep(struct lpfc_hba *phba)
dea3101e 120{
121 lpfc_vpd_t *vp = &phba->vpd;
122 int i = 0, rc;
123 LPFC_MBOXQ_t *pmb;
124 MAILBOX_t *mb;
125 char *lpfc_vpd_data = NULL;
126 uint16_t offset = 0;
127 static char licensed[56] =
128 "key unlock for use with gnu public licensed code only\0";
65a29c16 129 static int init_key = 1;
dea3101e 130
131 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
132 if (!pmb) {
2e0fef85 133 phba->link_state = LPFC_HBA_ERROR;
dea3101e 134 return -ENOMEM;
135 }
136
04c68496 137 mb = &pmb->u.mb;
2e0fef85 138 phba->link_state = LPFC_INIT_MBX_CMDS;
dea3101e 139
140 if (lpfc_is_LC_HBA(phba->pcidev->device)) {
65a29c16
JS
141 if (init_key) {
142 uint32_t *ptext = (uint32_t *) licensed;
dea3101e 143
65a29c16
JS
144 for (i = 0; i < 56; i += sizeof (uint32_t), ptext++)
145 *ptext = cpu_to_be32(*ptext);
146 init_key = 0;
147 }
dea3101e 148
149 lpfc_read_nv(phba, pmb);
150 memset((char*)mb->un.varRDnvp.rsvd3, 0,
151 sizeof (mb->un.varRDnvp.rsvd3));
152 memcpy((char*)mb->un.varRDnvp.rsvd3, licensed,
153 sizeof (licensed));
154
155 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
156
157 if (rc != MBX_SUCCESS) {
ed957684 158 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
e8b62011 159 "0324 Config Port initialization "
dea3101e 160 "error, mbxCmd x%x READ_NVPARM, "
161 "mbxStatus x%x\n",
dea3101e 162 mb->mbxCommand, mb->mbxStatus);
163 mempool_free(pmb, phba->mbox_mem_pool);
164 return -ERESTART;
165 }
166 memcpy(phba->wwnn, (char *)mb->un.varRDnvp.nodename,
2e0fef85
JS
167 sizeof(phba->wwnn));
168 memcpy(phba->wwpn, (char *)mb->un.varRDnvp.portname,
169 sizeof(phba->wwpn));
dea3101e 170 }
171
dfb75133
MW
172 /*
173 * Clear all option bits except LPFC_SLI3_BG_ENABLED,
174 * which was already set in lpfc_get_cfgparam()
175 */
176 phba->sli3_options &= (uint32_t)LPFC_SLI3_BG_ENABLED;
92d7f7b0 177
dea3101e 178 /* Setup and issue mailbox READ REV command */
179 lpfc_read_rev(phba, pmb);
180 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
181 if (rc != MBX_SUCCESS) {
ed957684 182 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e8b62011 183 "0439 Adapter failed to init, mbxCmd x%x "
dea3101e 184 "READ_REV, mbxStatus x%x\n",
dea3101e 185 mb->mbxCommand, mb->mbxStatus);
186 mempool_free( pmb, phba->mbox_mem_pool);
187 return -ERESTART;
188 }
189
92d7f7b0 190
1de933f3
JSEC
191 /*
192 * The value of rr must be 1 since the driver set the cv field to 1.
193 * This setting requires the FW to set all revision fields.
dea3101e 194 */
1de933f3 195 if (mb->un.varRdRev.rr == 0) {
dea3101e 196 vp->rev.rBit = 0;
1de933f3 197 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e8b62011
JS
198 "0440 Adapter failed to init, READ_REV has "
199 "missing revision information.\n");
dea3101e 200 mempool_free(pmb, phba->mbox_mem_pool);
201 return -ERESTART;
dea3101e 202 }
203
495a714c
JS
204 if (phba->sli_rev == 3 && !mb->un.varRdRev.v3rsp) {
205 mempool_free(pmb, phba->mbox_mem_pool);
ed957684 206 return -EINVAL;
495a714c 207 }
ed957684 208
dea3101e 209 /* Save information as VPD data */
1de933f3 210 vp->rev.rBit = 1;
92d7f7b0 211 memcpy(&vp->sli3Feat, &mb->un.varRdRev.sli3Feat, sizeof(uint32_t));
1de933f3
JSEC
212 vp->rev.sli1FwRev = mb->un.varRdRev.sli1FwRev;
213 memcpy(vp->rev.sli1FwName, (char*) mb->un.varRdRev.sli1FwName, 16);
214 vp->rev.sli2FwRev = mb->un.varRdRev.sli2FwRev;
215 memcpy(vp->rev.sli2FwName, (char *) mb->un.varRdRev.sli2FwName, 16);
dea3101e 216 vp->rev.biuRev = mb->un.varRdRev.biuRev;
217 vp->rev.smRev = mb->un.varRdRev.smRev;
218 vp->rev.smFwRev = mb->un.varRdRev.un.smFwRev;
219 vp->rev.endecRev = mb->un.varRdRev.endecRev;
220 vp->rev.fcphHigh = mb->un.varRdRev.fcphHigh;
221 vp->rev.fcphLow = mb->un.varRdRev.fcphLow;
222 vp->rev.feaLevelHigh = mb->un.varRdRev.feaLevelHigh;
223 vp->rev.feaLevelLow = mb->un.varRdRev.feaLevelLow;
224 vp->rev.postKernRev = mb->un.varRdRev.postKernRev;
225 vp->rev.opFwRev = mb->un.varRdRev.opFwRev;
226
92d7f7b0
JS
227 /* If the sli feature level is less then 9, we must
228 * tear down all RPIs and VPIs on link down if NPIV
229 * is enabled.
230 */
231 if (vp->rev.feaLevelHigh < 9)
232 phba->sli3_options |= LPFC_SLI3_VPORT_TEARDOWN;
233
dea3101e 234 if (lpfc_is_LC_HBA(phba->pcidev->device))
235 memcpy(phba->RandomData, (char *)&mb->un.varWords[24],
236 sizeof (phba->RandomData));
237
dea3101e 238 /* Get adapter VPD information */
dea3101e 239 lpfc_vpd_data = kmalloc(DMP_VPD_SIZE, GFP_KERNEL);
240 if (!lpfc_vpd_data)
d7c255b2 241 goto out_free_mbox;
dea3101e 242 do {
a0c87cbd 243 lpfc_dump_mem(phba, pmb, offset, DMP_REGION_VPD);
dea3101e 244 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
245
246 if (rc != MBX_SUCCESS) {
247 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011 248 "0441 VPD not present on adapter, "
dea3101e 249 "mbxCmd x%x DUMP VPD, mbxStatus x%x\n",
dea3101e 250 mb->mbxCommand, mb->mbxStatus);
74b72a59 251 mb->un.varDmp.word_cnt = 0;
dea3101e 252 }
04c68496
JS
253 /* dump mem may return a zero when finished or we got a
254 * mailbox error, either way we are done.
255 */
256 if (mb->un.varDmp.word_cnt == 0)
257 break;
74b72a59
JW
258 if (mb->un.varDmp.word_cnt > DMP_VPD_SIZE - offset)
259 mb->un.varDmp.word_cnt = DMP_VPD_SIZE - offset;
d7c255b2
JS
260 lpfc_sli_pcimem_bcopy(((uint8_t *)mb) + DMP_RSP_OFFSET,
261 lpfc_vpd_data + offset,
92d7f7b0 262 mb->un.varDmp.word_cnt);
dea3101e 263 offset += mb->un.varDmp.word_cnt;
74b72a59
JW
264 } while (mb->un.varDmp.word_cnt && offset < DMP_VPD_SIZE);
265 lpfc_parse_vpd(phba, lpfc_vpd_data, offset);
dea3101e 266
267 kfree(lpfc_vpd_data);
dea3101e 268out_free_mbox:
269 mempool_free(pmb, phba->mbox_mem_pool);
270 return 0;
271}
272
e59058c4 273/**
3621a710 274 * lpfc_config_async_cmpl - Completion handler for config async event mbox cmd
e59058c4
JS
275 * @phba: pointer to lpfc hba data structure.
276 * @pmboxq: pointer to the driver internal queue element for mailbox command.
277 *
278 * This is the completion handler for driver's configuring asynchronous event
279 * mailbox command to the device. If the mailbox command returns successfully,
280 * it will set internal async event support flag to 1; otherwise, it will
281 * set internal async event support flag to 0.
282 **/
57127f15
JS
283static void
284lpfc_config_async_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
285{
04c68496 286 if (pmboxq->u.mb.mbxStatus == MBX_SUCCESS)
57127f15
JS
287 phba->temp_sensor_support = 1;
288 else
289 phba->temp_sensor_support = 0;
290 mempool_free(pmboxq, phba->mbox_mem_pool);
291 return;
292}
293
97207482 294/**
3621a710 295 * lpfc_dump_wakeup_param_cmpl - dump memory mailbox command completion handler
97207482
JS
296 * @phba: pointer to lpfc hba data structure.
297 * @pmboxq: pointer to the driver internal queue element for mailbox command.
298 *
299 * This is the completion handler for dump mailbox command for getting
300 * wake up parameters. When this command complete, the response contain
301 * Option rom version of the HBA. This function translate the version number
302 * into a human readable string and store it in OptionROMVersion.
303 **/
304static void
305lpfc_dump_wakeup_param_cmpl(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmboxq)
306{
307 struct prog_id *prg;
308 uint32_t prog_id_word;
309 char dist = ' ';
310 /* character array used for decoding dist type. */
311 char dist_char[] = "nabx";
312
04c68496 313 if (pmboxq->u.mb.mbxStatus != MBX_SUCCESS) {
9f1e1b50 314 mempool_free(pmboxq, phba->mbox_mem_pool);
97207482 315 return;
9f1e1b50 316 }
97207482
JS
317
318 prg = (struct prog_id *) &prog_id_word;
319
320 /* word 7 contain option rom version */
04c68496 321 prog_id_word = pmboxq->u.mb.un.varWords[7];
97207482
JS
322
323 /* Decode the Option rom version word to a readable string */
324 if (prg->dist < 4)
325 dist = dist_char[prg->dist];
326
327 if ((prg->dist == 3) && (prg->num == 0))
a2fc4aef 328 snprintf(phba->OptionROMVersion, 32, "%d.%d%d",
97207482
JS
329 prg->ver, prg->rev, prg->lev);
330 else
a2fc4aef 331 snprintf(phba->OptionROMVersion, 32, "%d.%d%d%c%d",
97207482
JS
332 prg->ver, prg->rev, prg->lev,
333 dist, prg->num);
9f1e1b50 334 mempool_free(pmboxq, phba->mbox_mem_pool);
97207482
JS
335 return;
336}
337
0558056c
JS
338/**
339 * lpfc_update_vport_wwn - Updates the fc_nodename, fc_portname,
340 * cfg_soft_wwnn, cfg_soft_wwpn
341 * @vport: pointer to lpfc vport data structure.
342 *
343 *
344 * Return codes
345 * None.
346 **/
347void
348lpfc_update_vport_wwn(struct lpfc_vport *vport)
349{
aeb3c817
JS
350 uint8_t vvvl = vport->fc_sparam.cmn.valid_vendor_ver_level;
351 u32 *fawwpn_key = (u32 *)&vport->fc_sparam.un.vendorVersion[0];
352
0558056c
JS
353 /* If the soft name exists then update it using the service params */
354 if (vport->phba->cfg_soft_wwnn)
355 u64_to_wwn(vport->phba->cfg_soft_wwnn,
356 vport->fc_sparam.nodeName.u.wwn);
357 if (vport->phba->cfg_soft_wwpn)
358 u64_to_wwn(vport->phba->cfg_soft_wwpn,
359 vport->fc_sparam.portName.u.wwn);
360
361 /*
362 * If the name is empty or there exists a soft name
363 * then copy the service params name, otherwise use the fc name
364 */
365 if (vport->fc_nodename.u.wwn[0] == 0 || vport->phba->cfg_soft_wwnn)
366 memcpy(&vport->fc_nodename, &vport->fc_sparam.nodeName,
367 sizeof(struct lpfc_name));
368 else
369 memcpy(&vport->fc_sparam.nodeName, &vport->fc_nodename,
370 sizeof(struct lpfc_name));
371
aeb3c817
JS
372 /*
373 * If the port name has changed, then set the Param changes flag
374 * to unreg the login
375 */
376 if (vport->fc_portname.u.wwn[0] != 0 &&
377 memcmp(&vport->fc_portname, &vport->fc_sparam.portName,
378 sizeof(struct lpfc_name)))
379 vport->vport_flag |= FAWWPN_PARAM_CHG;
380
381 if (vport->fc_portname.u.wwn[0] == 0 ||
382 vport->phba->cfg_soft_wwpn ||
383 (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR) ||
384 vport->vport_flag & FAWWPN_SET) {
0558056c
JS
385 memcpy(&vport->fc_portname, &vport->fc_sparam.portName,
386 sizeof(struct lpfc_name));
aeb3c817
JS
387 vport->vport_flag &= ~FAWWPN_SET;
388 if (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR)
389 vport->vport_flag |= FAWWPN_SET;
390 }
0558056c
JS
391 else
392 memcpy(&vport->fc_sparam.portName, &vport->fc_portname,
393 sizeof(struct lpfc_name));
394}
395
e59058c4 396/**
3621a710 397 * lpfc_config_port_post - Perform lpfc initialization after config port
e59058c4
JS
398 * @phba: pointer to lpfc hba data structure.
399 *
400 * This routine will do LPFC initialization after the CONFIG_PORT mailbox
401 * command call. It performs all internal resource and state setups on the
402 * port: post IOCB buffers, enable appropriate host interrupt attentions,
403 * ELS ring timers, etc.
404 *
405 * Return codes
406 * 0 - success.
407 * Any other value - error.
408 **/
dea3101e 409int
2e0fef85 410lpfc_config_port_post(struct lpfc_hba *phba)
dea3101e 411{
2e0fef85 412 struct lpfc_vport *vport = phba->pport;
a257bf90 413 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
dea3101e 414 LPFC_MBOXQ_t *pmb;
415 MAILBOX_t *mb;
416 struct lpfc_dmabuf *mp;
417 struct lpfc_sli *psli = &phba->sli;
418 uint32_t status, timeout;
2e0fef85
JS
419 int i, j;
420 int rc;
dea3101e 421
7af67051
JS
422 spin_lock_irq(&phba->hbalock);
423 /*
424 * If the Config port completed correctly the HBA is not
425 * over heated any more.
426 */
427 if (phba->over_temp_state == HBA_OVER_TEMP)
428 phba->over_temp_state = HBA_NORMAL_TEMP;
429 spin_unlock_irq(&phba->hbalock);
430
dea3101e 431 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
432 if (!pmb) {
2e0fef85 433 phba->link_state = LPFC_HBA_ERROR;
dea3101e 434 return -ENOMEM;
435 }
04c68496 436 mb = &pmb->u.mb;
dea3101e 437
dea3101e 438 /* Get login parameters for NID. */
9f1177a3
JS
439 rc = lpfc_read_sparam(phba, pmb, 0);
440 if (rc) {
441 mempool_free(pmb, phba->mbox_mem_pool);
442 return -ENOMEM;
443 }
444
ed957684 445 pmb->vport = vport;
dea3101e 446 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
ed957684 447 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e8b62011 448 "0448 Adapter failed init, mbxCmd x%x "
dea3101e 449 "READ_SPARM mbxStatus x%x\n",
dea3101e 450 mb->mbxCommand, mb->mbxStatus);
2e0fef85 451 phba->link_state = LPFC_HBA_ERROR;
3e1f0718 452 mp = (struct lpfc_dmabuf *)pmb->ctx_buf;
9f1177a3 453 mempool_free(pmb, phba->mbox_mem_pool);
dea3101e 454 lpfc_mbuf_free(phba, mp->virt, mp->phys);
455 kfree(mp);
456 return -EIO;
457 }
458
3e1f0718 459 mp = (struct lpfc_dmabuf *)pmb->ctx_buf;
dea3101e 460
2e0fef85 461 memcpy(&vport->fc_sparam, mp->virt, sizeof (struct serv_parm));
dea3101e 462 lpfc_mbuf_free(phba, mp->virt, mp->phys);
463 kfree(mp);
3e1f0718 464 pmb->ctx_buf = NULL;
0558056c 465 lpfc_update_vport_wwn(vport);
a257bf90
JS
466
467 /* Update the fc_host data structures with new wwn. */
468 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
469 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
21e9a0a5 470 fc_host_max_npiv_vports(shost) = phba->max_vpi;
a257bf90 471
dea3101e 472 /* If no serial number in VPD data, use low 6 bytes of WWNN */
473 /* This should be consolidated into parse_vpd ? - mr */
474 if (phba->SerialNumber[0] == 0) {
475 uint8_t *outptr;
476
2e0fef85 477 outptr = &vport->fc_nodename.u.s.IEEE[0];
dea3101e 478 for (i = 0; i < 12; i++) {
479 status = *outptr++;
480 j = ((status & 0xf0) >> 4);
481 if (j <= 9)
482 phba->SerialNumber[i] =
483 (char)((uint8_t) 0x30 + (uint8_t) j);
484 else
485 phba->SerialNumber[i] =
486 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
487 i++;
488 j = (status & 0xf);
489 if (j <= 9)
490 phba->SerialNumber[i] =
491 (char)((uint8_t) 0x30 + (uint8_t) j);
492 else
493 phba->SerialNumber[i] =
494 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
495 }
496 }
497
dea3101e 498 lpfc_read_config(phba, pmb);
ed957684 499 pmb->vport = vport;
dea3101e 500 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
ed957684 501 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e8b62011 502 "0453 Adapter failed to init, mbxCmd x%x "
dea3101e 503 "READ_CONFIG, mbxStatus x%x\n",
dea3101e 504 mb->mbxCommand, mb->mbxStatus);
2e0fef85 505 phba->link_state = LPFC_HBA_ERROR;
dea3101e 506 mempool_free( pmb, phba->mbox_mem_pool);
507 return -EIO;
508 }
509
a0c87cbd
JS
510 /* Check if the port is disabled */
511 lpfc_sli_read_link_ste(phba);
512
dea3101e 513 /* Reset the DFT_HBA_Q_DEPTH to the max xri */
572709e2
JS
514 i = (mb->un.varRdConfig.max_xri + 1);
515 if (phba->cfg_hba_queue_depth > i) {
516 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
517 "3359 HBA queue depth changed from %d to %d\n",
518 phba->cfg_hba_queue_depth, i);
519 phba->cfg_hba_queue_depth = i;
520 }
521
522 /* Reset the DFT_LUN_Q_DEPTH to (max xri >> 3) */
523 i = (mb->un.varRdConfig.max_xri >> 3);
524 if (phba->pport->cfg_lun_queue_depth > i) {
525 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
526 "3360 LUN queue depth changed from %d to %d\n",
527 phba->pport->cfg_lun_queue_depth, i);
528 phba->pport->cfg_lun_queue_depth = i;
529 }
dea3101e 530
531 phba->lmt = mb->un.varRdConfig.lmt;
74b72a59
JW
532
533 /* Get the default values for Model Name and Description */
534 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
535
2e0fef85 536 phba->link_state = LPFC_LINK_DOWN;
dea3101e 537
0b727fea 538 /* Only process IOCBs on ELS ring till hba_state is READY */
895427bd
JS
539 if (psli->sli3_ring[LPFC_EXTRA_RING].sli.sli3.cmdringaddr)
540 psli->sli3_ring[LPFC_EXTRA_RING].flag |= LPFC_STOP_IOCB_EVENT;
541 if (psli->sli3_ring[LPFC_FCP_RING].sli.sli3.cmdringaddr)
542 psli->sli3_ring[LPFC_FCP_RING].flag |= LPFC_STOP_IOCB_EVENT;
dea3101e 543
544 /* Post receive buffers for desired rings */
ed957684
JS
545 if (phba->sli_rev != 3)
546 lpfc_post_rcv_buf(phba);
dea3101e 547
9399627f
JS
548 /*
549 * Configure HBA MSI-X attention conditions to messages if MSI-X mode
550 */
551 if (phba->intr_type == MSIX) {
552 rc = lpfc_config_msi(phba, pmb);
553 if (rc) {
554 mempool_free(pmb, phba->mbox_mem_pool);
555 return -EIO;
556 }
557 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
558 if (rc != MBX_SUCCESS) {
559 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
560 "0352 Config MSI mailbox command "
561 "failed, mbxCmd x%x, mbxStatus x%x\n",
04c68496
JS
562 pmb->u.mb.mbxCommand,
563 pmb->u.mb.mbxStatus);
9399627f
JS
564 mempool_free(pmb, phba->mbox_mem_pool);
565 return -EIO;
566 }
567 }
568
04c68496 569 spin_lock_irq(&phba->hbalock);
9399627f
JS
570 /* Initialize ERATT handling flag */
571 phba->hba_flag &= ~HBA_ERATT_HANDLED;
572
dea3101e 573 /* Enable appropriate host interrupts */
9940b97b
JS
574 if (lpfc_readl(phba->HCregaddr, &status)) {
575 spin_unlock_irq(&phba->hbalock);
576 return -EIO;
577 }
dea3101e 578 status |= HC_MBINT_ENA | HC_ERINT_ENA | HC_LAINT_ENA;
579 if (psli->num_rings > 0)
580 status |= HC_R0INT_ENA;
581 if (psli->num_rings > 1)
582 status |= HC_R1INT_ENA;
583 if (psli->num_rings > 2)
584 status |= HC_R2INT_ENA;
585 if (psli->num_rings > 3)
586 status |= HC_R3INT_ENA;
587
875fbdfe
JSEC
588 if ((phba->cfg_poll & ENABLE_FCP_RING_POLLING) &&
589 (phba->cfg_poll & DISABLE_FCP_RING_INT))
9399627f 590 status &= ~(HC_R0INT_ENA);
875fbdfe 591
dea3101e 592 writel(status, phba->HCregaddr);
593 readl(phba->HCregaddr); /* flush */
2e0fef85 594 spin_unlock_irq(&phba->hbalock);
dea3101e 595
9399627f
JS
596 /* Set up ring-0 (ELS) timer */
597 timeout = phba->fc_ratov * 2;
256ec0d0
JS
598 mod_timer(&vport->els_tmofunc,
599 jiffies + msecs_to_jiffies(1000 * timeout));
9399627f 600 /* Set up heart beat (HB) timer */
256ec0d0
JS
601 mod_timer(&phba->hb_tmofunc,
602 jiffies + msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
603 phba->hb_outstanding = 0;
604 phba->last_completion_time = jiffies;
9399627f 605 /* Set up error attention (ERATT) polling timer */
256ec0d0 606 mod_timer(&phba->eratt_poll,
65791f1f 607 jiffies + msecs_to_jiffies(1000 * phba->eratt_poll_interval));
dea3101e 608
a0c87cbd
JS
609 if (phba->hba_flag & LINK_DISABLED) {
610 lpfc_printf_log(phba,
611 KERN_ERR, LOG_INIT,
612 "2598 Adapter Link is disabled.\n");
613 lpfc_down_link(phba, pmb);
614 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
615 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
616 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
617 lpfc_printf_log(phba,
618 KERN_ERR, LOG_INIT,
619 "2599 Adapter failed to issue DOWN_LINK"
620 " mbox command rc 0x%x\n", rc);
621
622 mempool_free(pmb, phba->mbox_mem_pool);
623 return -EIO;
624 }
e40a02c1 625 } else if (phba->cfg_suppress_link_up == LPFC_INITIALIZE_LINK) {
026abb87
JS
626 mempool_free(pmb, phba->mbox_mem_pool);
627 rc = phba->lpfc_hba_init_link(phba, MBX_NOWAIT);
628 if (rc)
629 return rc;
dea3101e 630 }
631 /* MBOX buffer will be freed in mbox compl */
57127f15 632 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9f1177a3
JS
633 if (!pmb) {
634 phba->link_state = LPFC_HBA_ERROR;
635 return -ENOMEM;
636 }
637
57127f15
JS
638 lpfc_config_async(phba, pmb, LPFC_ELS_RING);
639 pmb->mbox_cmpl = lpfc_config_async_cmpl;
640 pmb->vport = phba->pport;
641 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
dea3101e 642
57127f15
JS
643 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
644 lpfc_printf_log(phba,
645 KERN_ERR,
646 LOG_INIT,
647 "0456 Adapter failed to issue "
e4e74273 648 "ASYNCEVT_ENABLE mbox status x%x\n",
57127f15
JS
649 rc);
650 mempool_free(pmb, phba->mbox_mem_pool);
651 }
97207482
JS
652
653 /* Get Option rom version */
654 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9f1177a3
JS
655 if (!pmb) {
656 phba->link_state = LPFC_HBA_ERROR;
657 return -ENOMEM;
658 }
659
97207482
JS
660 lpfc_dump_wakeup_param(phba, pmb);
661 pmb->mbox_cmpl = lpfc_dump_wakeup_param_cmpl;
662 pmb->vport = phba->pport;
663 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
664
665 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
666 lpfc_printf_log(phba, KERN_ERR, LOG_INIT, "0435 Adapter failed "
e4e74273 667 "to get Option ROM version status x%x\n", rc);
97207482
JS
668 mempool_free(pmb, phba->mbox_mem_pool);
669 }
670
d7c255b2 671 return 0;
ce8b3ce5
JS
672}
673
84d1b006
JS
674/**
675 * lpfc_hba_init_link - Initialize the FC link
676 * @phba: pointer to lpfc hba data structure.
6e7288d9 677 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
84d1b006
JS
678 *
679 * This routine will issue the INIT_LINK mailbox command call.
680 * It is available to other drivers through the lpfc_hba data
681 * structure for use as a delayed link up mechanism with the
682 * module parameter lpfc_suppress_link_up.
683 *
684 * Return code
685 * 0 - success
686 * Any other value - error
687 **/
e399b228 688static int
6e7288d9 689lpfc_hba_init_link(struct lpfc_hba *phba, uint32_t flag)
1b51197d
JS
690{
691 return lpfc_hba_init_link_fc_topology(phba, phba->cfg_topology, flag);
692}
693
694/**
695 * lpfc_hba_init_link_fc_topology - Initialize FC link with desired topology
696 * @phba: pointer to lpfc hba data structure.
697 * @fc_topology: desired fc topology.
698 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
699 *
700 * This routine will issue the INIT_LINK mailbox command call.
701 * It is available to other drivers through the lpfc_hba data
702 * structure for use as a delayed link up mechanism with the
703 * module parameter lpfc_suppress_link_up.
704 *
705 * Return code
706 * 0 - success
707 * Any other value - error
708 **/
709int
710lpfc_hba_init_link_fc_topology(struct lpfc_hba *phba, uint32_t fc_topology,
711 uint32_t flag)
84d1b006
JS
712{
713 struct lpfc_vport *vport = phba->pport;
714 LPFC_MBOXQ_t *pmb;
715 MAILBOX_t *mb;
716 int rc;
717
718 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
719 if (!pmb) {
720 phba->link_state = LPFC_HBA_ERROR;
721 return -ENOMEM;
722 }
723 mb = &pmb->u.mb;
724 pmb->vport = vport;
725
026abb87
JS
726 if ((phba->cfg_link_speed > LPFC_USER_LINK_SPEED_MAX) ||
727 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_1G) &&
728 !(phba->lmt & LMT_1Gb)) ||
729 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_2G) &&
730 !(phba->lmt & LMT_2Gb)) ||
731 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_4G) &&
732 !(phba->lmt & LMT_4Gb)) ||
733 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_8G) &&
734 !(phba->lmt & LMT_8Gb)) ||
735 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_10G) &&
736 !(phba->lmt & LMT_10Gb)) ||
737 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_16G) &&
d38dd52c
JS
738 !(phba->lmt & LMT_16Gb)) ||
739 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_32G) &&
fbd8a6ba
JS
740 !(phba->lmt & LMT_32Gb)) ||
741 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_64G) &&
742 !(phba->lmt & LMT_64Gb))) {
026abb87
JS
743 /* Reset link speed to auto */
744 lpfc_printf_log(phba, KERN_ERR, LOG_LINK_EVENT,
745 "1302 Invalid speed for this board:%d "
746 "Reset link speed to auto.\n",
747 phba->cfg_link_speed);
748 phba->cfg_link_speed = LPFC_USER_LINK_SPEED_AUTO;
749 }
1b51197d 750 lpfc_init_link(phba, pmb, fc_topology, phba->cfg_link_speed);
84d1b006 751 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
1b51197d
JS
752 if (phba->sli_rev < LPFC_SLI_REV4)
753 lpfc_set_loopback_flag(phba);
6e7288d9 754 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
76a95d75 755 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
84d1b006
JS
756 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
757 "0498 Adapter failed to init, mbxCmd x%x "
758 "INIT_LINK, mbxStatus x%x\n",
759 mb->mbxCommand, mb->mbxStatus);
76a95d75
JS
760 if (phba->sli_rev <= LPFC_SLI_REV3) {
761 /* Clear all interrupt enable conditions */
762 writel(0, phba->HCregaddr);
763 readl(phba->HCregaddr); /* flush */
764 /* Clear all pending interrupts */
765 writel(0xffffffff, phba->HAregaddr);
766 readl(phba->HAregaddr); /* flush */
767 }
84d1b006 768 phba->link_state = LPFC_HBA_ERROR;
6e7288d9 769 if (rc != MBX_BUSY || flag == MBX_POLL)
84d1b006
JS
770 mempool_free(pmb, phba->mbox_mem_pool);
771 return -EIO;
772 }
e40a02c1 773 phba->cfg_suppress_link_up = LPFC_INITIALIZE_LINK;
6e7288d9
JS
774 if (flag == MBX_POLL)
775 mempool_free(pmb, phba->mbox_mem_pool);
84d1b006
JS
776
777 return 0;
778}
779
780/**
781 * lpfc_hba_down_link - this routine downs the FC link
6e7288d9
JS
782 * @phba: pointer to lpfc hba data structure.
783 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
84d1b006
JS
784 *
785 * This routine will issue the DOWN_LINK mailbox command call.
786 * It is available to other drivers through the lpfc_hba data
787 * structure for use to stop the link.
788 *
789 * Return code
790 * 0 - success
791 * Any other value - error
792 **/
e399b228 793static int
6e7288d9 794lpfc_hba_down_link(struct lpfc_hba *phba, uint32_t flag)
84d1b006
JS
795{
796 LPFC_MBOXQ_t *pmb;
797 int rc;
798
799 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
800 if (!pmb) {
801 phba->link_state = LPFC_HBA_ERROR;
802 return -ENOMEM;
803 }
804
805 lpfc_printf_log(phba,
806 KERN_ERR, LOG_INIT,
807 "0491 Adapter Link is disabled.\n");
808 lpfc_down_link(phba, pmb);
809 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
6e7288d9 810 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
84d1b006
JS
811 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
812 lpfc_printf_log(phba,
813 KERN_ERR, LOG_INIT,
814 "2522 Adapter failed to issue DOWN_LINK"
815 " mbox command rc 0x%x\n", rc);
816
817 mempool_free(pmb, phba->mbox_mem_pool);
818 return -EIO;
819 }
6e7288d9
JS
820 if (flag == MBX_POLL)
821 mempool_free(pmb, phba->mbox_mem_pool);
822
84d1b006
JS
823 return 0;
824}
825
e59058c4 826/**
3621a710 827 * lpfc_hba_down_prep - Perform lpfc uninitialization prior to HBA reset
e59058c4
JS
828 * @phba: pointer to lpfc HBA data structure.
829 *
830 * This routine will do LPFC uninitialization before the HBA is reset when
831 * bringing down the SLI Layer.
832 *
833 * Return codes
834 * 0 - success.
835 * Any other value - error.
836 **/
dea3101e 837int
2e0fef85 838lpfc_hba_down_prep(struct lpfc_hba *phba)
dea3101e 839{
1b32f6aa
JS
840 struct lpfc_vport **vports;
841 int i;
3772a991
JS
842
843 if (phba->sli_rev <= LPFC_SLI_REV3) {
844 /* Disable interrupts */
845 writel(0, phba->HCregaddr);
846 readl(phba->HCregaddr); /* flush */
847 }
dea3101e 848
1b32f6aa
JS
849 if (phba->pport->load_flag & FC_UNLOADING)
850 lpfc_cleanup_discovery_resources(phba->pport);
851 else {
852 vports = lpfc_create_vport_work_array(phba);
853 if (vports != NULL)
3772a991
JS
854 for (i = 0; i <= phba->max_vports &&
855 vports[i] != NULL; i++)
1b32f6aa
JS
856 lpfc_cleanup_discovery_resources(vports[i]);
857 lpfc_destroy_vport_work_array(phba, vports);
7f5f3d0d
JS
858 }
859 return 0;
dea3101e 860}
861
68e814f5
JS
862/**
863 * lpfc_sli4_free_sp_events - Cleanup sp_queue_events to free
864 * rspiocb which got deferred
865 *
866 * @phba: pointer to lpfc HBA data structure.
867 *
868 * This routine will cleanup completed slow path events after HBA is reset
869 * when bringing down the SLI Layer.
870 *
871 *
872 * Return codes
873 * void.
874 **/
875static void
876lpfc_sli4_free_sp_events(struct lpfc_hba *phba)
877{
878 struct lpfc_iocbq *rspiocbq;
879 struct hbq_dmabuf *dmabuf;
880 struct lpfc_cq_event *cq_event;
881
882 spin_lock_irq(&phba->hbalock);
883 phba->hba_flag &= ~HBA_SP_QUEUE_EVT;
884 spin_unlock_irq(&phba->hbalock);
885
886 while (!list_empty(&phba->sli4_hba.sp_queue_event)) {
887 /* Get the response iocb from the head of work queue */
888 spin_lock_irq(&phba->hbalock);
889 list_remove_head(&phba->sli4_hba.sp_queue_event,
890 cq_event, struct lpfc_cq_event, list);
891 spin_unlock_irq(&phba->hbalock);
892
893 switch (bf_get(lpfc_wcqe_c_code, &cq_event->cqe.wcqe_cmpl)) {
894 case CQE_CODE_COMPL_WQE:
895 rspiocbq = container_of(cq_event, struct lpfc_iocbq,
896 cq_event);
897 lpfc_sli_release_iocbq(phba, rspiocbq);
898 break;
899 case CQE_CODE_RECEIVE:
900 case CQE_CODE_RECEIVE_V1:
901 dmabuf = container_of(cq_event, struct hbq_dmabuf,
902 cq_event);
903 lpfc_in_buf_free(phba, &dmabuf->dbuf);
904 }
905 }
906}
907
e59058c4 908/**
bcece5f5 909 * lpfc_hba_free_post_buf - Perform lpfc uninitialization after HBA reset
e59058c4
JS
910 * @phba: pointer to lpfc HBA data structure.
911 *
bcece5f5
JS
912 * This routine will cleanup posted ELS buffers after the HBA is reset
913 * when bringing down the SLI Layer.
914 *
e59058c4
JS
915 *
916 * Return codes
bcece5f5 917 * void.
e59058c4 918 **/
bcece5f5
JS
919static void
920lpfc_hba_free_post_buf(struct lpfc_hba *phba)
41415862
JW
921{
922 struct lpfc_sli *psli = &phba->sli;
923 struct lpfc_sli_ring *pring;
924 struct lpfc_dmabuf *mp, *next_mp;
07eab624
JS
925 LIST_HEAD(buflist);
926 int count;
41415862 927
92d7f7b0
JS
928 if (phba->sli3_options & LPFC_SLI3_HBQ_ENABLED)
929 lpfc_sli_hbqbuf_free_all(phba);
930 else {
931 /* Cleanup preposted buffers on the ELS ring */
895427bd 932 pring = &psli->sli3_ring[LPFC_ELS_RING];
07eab624
JS
933 spin_lock_irq(&phba->hbalock);
934 list_splice_init(&pring->postbufq, &buflist);
935 spin_unlock_irq(&phba->hbalock);
936
937 count = 0;
938 list_for_each_entry_safe(mp, next_mp, &buflist, list) {
92d7f7b0 939 list_del(&mp->list);
07eab624 940 count++;
92d7f7b0
JS
941 lpfc_mbuf_free(phba, mp->virt, mp->phys);
942 kfree(mp);
943 }
07eab624
JS
944
945 spin_lock_irq(&phba->hbalock);
946 pring->postbufq_cnt -= count;
bcece5f5 947 spin_unlock_irq(&phba->hbalock);
41415862 948 }
bcece5f5
JS
949}
950
951/**
952 * lpfc_hba_clean_txcmplq - Perform lpfc uninitialization after HBA reset
953 * @phba: pointer to lpfc HBA data structure.
954 *
955 * This routine will cleanup the txcmplq after the HBA is reset when bringing
956 * down the SLI Layer.
957 *
958 * Return codes
959 * void
960 **/
961static void
962lpfc_hba_clean_txcmplq(struct lpfc_hba *phba)
963{
964 struct lpfc_sli *psli = &phba->sli;
895427bd 965 struct lpfc_queue *qp = NULL;
bcece5f5
JS
966 struct lpfc_sli_ring *pring;
967 LIST_HEAD(completions);
968 int i;
c1dd9111 969 struct lpfc_iocbq *piocb, *next_iocb;
bcece5f5 970
895427bd
JS
971 if (phba->sli_rev != LPFC_SLI_REV4) {
972 for (i = 0; i < psli->num_rings; i++) {
973 pring = &psli->sli3_ring[i];
bcece5f5 974 spin_lock_irq(&phba->hbalock);
895427bd
JS
975 /* At this point in time the HBA is either reset or DOA
976 * Nothing should be on txcmplq as it will
977 * NEVER complete.
978 */
979 list_splice_init(&pring->txcmplq, &completions);
980 pring->txcmplq_cnt = 0;
bcece5f5 981 spin_unlock_irq(&phba->hbalock);
09372820 982
895427bd
JS
983 lpfc_sli_abort_iocb_ring(phba, pring);
984 }
a257bf90 985 /* Cancel all the IOCBs from the completions list */
895427bd
JS
986 lpfc_sli_cancel_iocbs(phba, &completions,
987 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
988 return;
989 }
990 list_for_each_entry(qp, &phba->sli4_hba.lpfc_wq_list, wq_list) {
991 pring = qp->pring;
992 if (!pring)
993 continue;
994 spin_lock_irq(&pring->ring_lock);
c1dd9111
JS
995 list_for_each_entry_safe(piocb, next_iocb,
996 &pring->txcmplq, list)
997 piocb->iocb_flag &= ~LPFC_IO_ON_TXCMPLQ;
895427bd
JS
998 list_splice_init(&pring->txcmplq, &completions);
999 pring->txcmplq_cnt = 0;
1000 spin_unlock_irq(&pring->ring_lock);
41415862
JW
1001 lpfc_sli_abort_iocb_ring(phba, pring);
1002 }
895427bd
JS
1003 /* Cancel all the IOCBs from the completions list */
1004 lpfc_sli_cancel_iocbs(phba, &completions,
1005 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
bcece5f5 1006}
41415862 1007
bcece5f5
JS
1008/**
1009 * lpfc_hba_down_post_s3 - Perform lpfc uninitialization after HBA reset
1010 int i;
1011 * @phba: pointer to lpfc HBA data structure.
1012 *
1013 * This routine will do uninitialization after the HBA is reset when bring
1014 * down the SLI Layer.
1015 *
1016 * Return codes
1017 * 0 - success.
1018 * Any other value - error.
1019 **/
1020static int
1021lpfc_hba_down_post_s3(struct lpfc_hba *phba)
1022{
1023 lpfc_hba_free_post_buf(phba);
1024 lpfc_hba_clean_txcmplq(phba);
41415862
JW
1025 return 0;
1026}
5af5eee7 1027
da0436e9
JS
1028/**
1029 * lpfc_hba_down_post_s4 - Perform lpfc uninitialization after HBA reset
1030 * @phba: pointer to lpfc HBA data structure.
1031 *
1032 * This routine will do uninitialization after the HBA is reset when bring
1033 * down the SLI Layer.
1034 *
1035 * Return codes
af901ca1 1036 * 0 - success.
da0436e9
JS
1037 * Any other value - error.
1038 **/
1039static int
1040lpfc_hba_down_post_s4(struct lpfc_hba *phba)
1041{
c490850a 1042 struct lpfc_io_buf *psb, *psb_next;
86c67379 1043 struct lpfc_nvmet_rcv_ctx *ctxp, *ctxp_next;
5e5b511d 1044 struct lpfc_sli4_hdw_queue *qp;
da0436e9 1045 LIST_HEAD(aborts);
895427bd 1046 LIST_HEAD(nvme_aborts);
86c67379 1047 LIST_HEAD(nvmet_aborts);
0f65ff68 1048 struct lpfc_sglq *sglq_entry = NULL;
5e5b511d 1049 int cnt, idx;
0f65ff68 1050
895427bd
JS
1051
1052 lpfc_sli_hbqbuf_free_all(phba);
bcece5f5
JS
1053 lpfc_hba_clean_txcmplq(phba);
1054
da0436e9
JS
1055 /* At this point in time the HBA is either reset or DOA. Either
1056 * way, nothing should be on lpfc_abts_els_sgl_list, it needs to be
895427bd 1057 * on the lpfc_els_sgl_list so that it can either be freed if the
da0436e9
JS
1058 * driver is unloading or reposted if the driver is restarting
1059 * the port.
1060 */
895427bd 1061 spin_lock_irq(&phba->hbalock); /* required for lpfc_els_sgl_list and */
da0436e9 1062 /* scsl_buf_list */
895427bd 1063 /* sgl_list_lock required because worker thread uses this
da0436e9
JS
1064 * list.
1065 */
895427bd 1066 spin_lock(&phba->sli4_hba.sgl_list_lock);
0f65ff68
JS
1067 list_for_each_entry(sglq_entry,
1068 &phba->sli4_hba.lpfc_abts_els_sgl_list, list)
1069 sglq_entry->state = SGL_FREED;
1070
da0436e9 1071 list_splice_init(&phba->sli4_hba.lpfc_abts_els_sgl_list,
895427bd
JS
1072 &phba->sli4_hba.lpfc_els_sgl_list);
1073
f358dd0c 1074
895427bd 1075 spin_unlock(&phba->sli4_hba.sgl_list_lock);
5e5b511d
JS
1076
1077 /* abts_xxxx_buf_list_lock required because worker thread uses this
da0436e9
JS
1078 * list.
1079 */
5e5b511d
JS
1080 cnt = 0;
1081 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
1082 qp = &phba->sli4_hba.hdwq[idx];
da0436e9 1083
5e5b511d
JS
1084 spin_lock(&qp->abts_scsi_buf_list_lock);
1085 list_splice_init(&qp->lpfc_abts_scsi_buf_list,
1086 &aborts);
68e814f5 1087
0794d601 1088 list_for_each_entry_safe(psb, psb_next, &aborts, list) {
86c67379
JS
1089 psb->pCmd = NULL;
1090 psb->status = IOSTAT_SUCCESS;
cf1a1d3e 1091 cnt++;
86c67379 1092 }
5e5b511d
JS
1093 spin_lock(&qp->io_buf_list_put_lock);
1094 list_splice_init(&aborts, &qp->lpfc_io_buf_list_put);
1095 qp->put_io_bufs += qp->abts_scsi_io_bufs;
1096 qp->abts_scsi_io_bufs = 0;
1097 spin_unlock(&qp->io_buf_list_put_lock);
1098 spin_unlock(&qp->abts_scsi_buf_list_lock);
86c67379 1099
5e5b511d
JS
1100 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
1101 spin_lock(&qp->abts_nvme_buf_list_lock);
1102 list_splice_init(&qp->lpfc_abts_nvme_buf_list,
1103 &nvme_aborts);
1104 list_for_each_entry_safe(psb, psb_next, &nvme_aborts,
1105 list) {
1106 psb->pCmd = NULL;
1107 psb->status = IOSTAT_SUCCESS;
1108 cnt++;
1109 }
1110 spin_lock(&qp->io_buf_list_put_lock);
1111 qp->put_io_bufs += qp->abts_nvme_io_bufs;
1112 qp->abts_nvme_io_bufs = 0;
1113 list_splice_init(&nvme_aborts,
1114 &qp->lpfc_io_buf_list_put);
1115 spin_unlock(&qp->io_buf_list_put_lock);
1116 spin_unlock(&qp->abts_nvme_buf_list_lock);
68e814f5 1117
86c67379 1118 }
5e5b511d 1119 }
731eedcb 1120 spin_unlock_irq(&phba->hbalock);
86c67379 1121
5e5b511d 1122 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
731eedcb 1123 spin_lock_irq(&phba->sli4_hba.abts_nvmet_buf_list_lock);
5e5b511d
JS
1124 list_splice_init(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list,
1125 &nvmet_aborts);
731eedcb 1126 spin_unlock_irq(&phba->sli4_hba.abts_nvmet_buf_list_lock);
86c67379
JS
1127 list_for_each_entry_safe(ctxp, ctxp_next, &nvmet_aborts, list) {
1128 ctxp->flag &= ~(LPFC_NVMET_XBUSY | LPFC_NVMET_ABORT_OP);
6c621a22 1129 lpfc_nvmet_ctxbuf_post(phba, ctxp->ctxbuf);
86c67379 1130 }
895427bd 1131 }
895427bd 1132
68e814f5 1133 lpfc_sli4_free_sp_events(phba);
5e5b511d 1134 return cnt;
da0436e9
JS
1135}
1136
1137/**
1138 * lpfc_hba_down_post - Wrapper func for hba down post routine
1139 * @phba: pointer to lpfc HBA data structure.
1140 *
1141 * This routine wraps the actual SLI3 or SLI4 routine for performing
1142 * uninitialization after the HBA is reset when bring down the SLI Layer.
1143 *
1144 * Return codes
af901ca1 1145 * 0 - success.
da0436e9
JS
1146 * Any other value - error.
1147 **/
1148int
1149lpfc_hba_down_post(struct lpfc_hba *phba)
1150{
1151 return (*phba->lpfc_hba_down_post)(phba);
1152}
41415862 1153
e59058c4 1154/**
3621a710 1155 * lpfc_hb_timeout - The HBA-timer timeout handler
e59058c4
JS
1156 * @ptr: unsigned long holds the pointer to lpfc hba data structure.
1157 *
1158 * This is the HBA-timer timeout handler registered to the lpfc driver. When
1159 * this timer fires, a HBA timeout event shall be posted to the lpfc driver
1160 * work-port-events bitmap and the worker thread is notified. This timeout
1161 * event will be used by the worker thread to invoke the actual timeout
1162 * handler routine, lpfc_hb_timeout_handler. Any periodical operations will
1163 * be performed in the timeout handler and the HBA timeout event bit shall
1164 * be cleared by the worker thread after it has taken the event bitmap out.
1165 **/
a6ababd2 1166static void
f22eb4d3 1167lpfc_hb_timeout(struct timer_list *t)
858c9f6c
JS
1168{
1169 struct lpfc_hba *phba;
5e9d9b82 1170 uint32_t tmo_posted;
858c9f6c
JS
1171 unsigned long iflag;
1172
f22eb4d3 1173 phba = from_timer(phba, t, hb_tmofunc);
9399627f
JS
1174
1175 /* Check for heart beat timeout conditions */
858c9f6c 1176 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
5e9d9b82
JS
1177 tmo_posted = phba->pport->work_port_events & WORKER_HB_TMO;
1178 if (!tmo_posted)
858c9f6c
JS
1179 phba->pport->work_port_events |= WORKER_HB_TMO;
1180 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
1181
9399627f 1182 /* Tell the worker thread there is work to do */
5e9d9b82
JS
1183 if (!tmo_posted)
1184 lpfc_worker_wake_up(phba);
858c9f6c
JS
1185 return;
1186}
1187
19ca7609
JS
1188/**
1189 * lpfc_rrq_timeout - The RRQ-timer timeout handler
1190 * @ptr: unsigned long holds the pointer to lpfc hba data structure.
1191 *
1192 * This is the RRQ-timer timeout handler registered to the lpfc driver. When
1193 * this timer fires, a RRQ timeout event shall be posted to the lpfc driver
1194 * work-port-events bitmap and the worker thread is notified. This timeout
1195 * event will be used by the worker thread to invoke the actual timeout
1196 * handler routine, lpfc_rrq_handler. Any periodical operations will
1197 * be performed in the timeout handler and the RRQ timeout event bit shall
1198 * be cleared by the worker thread after it has taken the event bitmap out.
1199 **/
1200static void
f22eb4d3 1201lpfc_rrq_timeout(struct timer_list *t)
19ca7609
JS
1202{
1203 struct lpfc_hba *phba;
19ca7609
JS
1204 unsigned long iflag;
1205
f22eb4d3 1206 phba = from_timer(phba, t, rrq_tmr);
19ca7609 1207 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
06918ac5
JS
1208 if (!(phba->pport->load_flag & FC_UNLOADING))
1209 phba->hba_flag |= HBA_RRQ_ACTIVE;
1210 else
1211 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
19ca7609 1212 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
06918ac5
JS
1213
1214 if (!(phba->pport->load_flag & FC_UNLOADING))
1215 lpfc_worker_wake_up(phba);
19ca7609
JS
1216}
1217
e59058c4 1218/**
3621a710 1219 * lpfc_hb_mbox_cmpl - The lpfc heart-beat mailbox command callback function
e59058c4
JS
1220 * @phba: pointer to lpfc hba data structure.
1221 * @pmboxq: pointer to the driver internal queue element for mailbox command.
1222 *
1223 * This is the callback function to the lpfc heart-beat mailbox command.
1224 * If configured, the lpfc driver issues the heart-beat mailbox command to
1225 * the HBA every LPFC_HB_MBOX_INTERVAL (current 5) seconds. At the time the
1226 * heart-beat mailbox command is issued, the driver shall set up heart-beat
1227 * timeout timer to LPFC_HB_MBOX_TIMEOUT (current 30) seconds and marks
1228 * heart-beat outstanding state. Once the mailbox command comes back and
1229 * no error conditions detected, the heart-beat mailbox command timer is
1230 * reset to LPFC_HB_MBOX_INTERVAL seconds and the heart-beat outstanding
1231 * state is cleared for the next heart-beat. If the timer expired with the
1232 * heart-beat outstanding state set, the driver will put the HBA offline.
1233 **/
858c9f6c
JS
1234static void
1235lpfc_hb_mbox_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
1236{
1237 unsigned long drvr_flag;
1238
1239 spin_lock_irqsave(&phba->hbalock, drvr_flag);
1240 phba->hb_outstanding = 0;
1241 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
1242
9399627f 1243 /* Check and reset heart-beat timer is necessary */
858c9f6c
JS
1244 mempool_free(pmboxq, phba->mbox_mem_pool);
1245 if (!(phba->pport->fc_flag & FC_OFFLINE_MODE) &&
1246 !(phba->link_state == LPFC_HBA_ERROR) &&
51ef4c26 1247 !(phba->pport->load_flag & FC_UNLOADING))
858c9f6c 1248 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1249 jiffies +
1250 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
1251 return;
1252}
1253
32517fc0
JS
1254static void
1255lpfc_hb_eq_delay_work(struct work_struct *work)
1256{
1257 struct lpfc_hba *phba = container_of(to_delayed_work(work),
1258 struct lpfc_hba, eq_delay_work);
1259 struct lpfc_eq_intr_info *eqi, *eqi_new;
1260 struct lpfc_queue *eq, *eq_next;
1261 unsigned char *eqcnt = NULL;
1262 uint32_t usdelay;
1263 int i;
1264
1265 if (!phba->cfg_auto_imax || phba->pport->load_flag & FC_UNLOADING)
1266 return;
1267
1268 if (phba->link_state == LPFC_HBA_ERROR ||
1269 phba->pport->fc_flag & FC_OFFLINE_MODE)
1270 goto requeue;
1271
1272 eqcnt = kcalloc(num_possible_cpus(), sizeof(unsigned char),
1273 GFP_KERNEL);
1274 if (!eqcnt)
1275 goto requeue;
1276
1277 for (i = 0; i < phba->cfg_irq_chann; i++) {
1278 eq = phba->sli4_hba.hdwq[i].hba_eq;
1279 if (eq && eqcnt[eq->last_cpu] < 2)
1280 eqcnt[eq->last_cpu]++;
1281 continue;
1282 }
1283
1284 for_each_present_cpu(i) {
1285 if (phba->cfg_irq_chann > 1 && eqcnt[i] < 2)
1286 continue;
1287
1288 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, i);
1289
1290 usdelay = (eqi->icnt / LPFC_IMAX_THRESHOLD) *
1291 LPFC_EQ_DELAY_STEP;
1292 if (usdelay > LPFC_MAX_AUTO_EQ_DELAY)
1293 usdelay = LPFC_MAX_AUTO_EQ_DELAY;
1294
1295 eqi->icnt = 0;
1296
1297 list_for_each_entry_safe(eq, eq_next, &eqi->list, cpu_list) {
1298 if (eq->last_cpu != i) {
1299 eqi_new = per_cpu_ptr(phba->sli4_hba.eq_info,
1300 eq->last_cpu);
1301 list_move_tail(&eq->cpu_list, &eqi_new->list);
1302 continue;
1303 }
1304 if (usdelay != eq->q_mode)
1305 lpfc_modify_hba_eq_delay(phba, eq->hdwq, 1,
1306 usdelay);
1307 }
1308 }
1309
1310 kfree(eqcnt);
1311
1312requeue:
1313 queue_delayed_work(phba->wq, &phba->eq_delay_work,
1314 msecs_to_jiffies(LPFC_EQ_DELAY_MSECS));
1315}
1316
c490850a
JS
1317/**
1318 * lpfc_hb_mxp_handler - Multi-XRI pools handler to adjust XRI distribution
1319 * @phba: pointer to lpfc hba data structure.
1320 *
1321 * For each heartbeat, this routine does some heuristic methods to adjust
1322 * XRI distribution. The goal is to fully utilize free XRIs.
1323 **/
1324static void lpfc_hb_mxp_handler(struct lpfc_hba *phba)
1325{
1326 u32 i;
1327 u32 hwq_count;
1328
1329 hwq_count = phba->cfg_hdw_queue;
1330 for (i = 0; i < hwq_count; i++) {
1331 /* Adjust XRIs in private pool */
1332 lpfc_adjust_pvt_pool_count(phba, i);
1333
1334 /* Adjust high watermark */
1335 lpfc_adjust_high_watermark(phba, i);
1336
1337#ifdef LPFC_MXP_STAT
1338 /* Snapshot pbl, pvt and busy count */
1339 lpfc_snapshot_mxp(phba, i);
1340#endif
1341 }
1342}
1343
e59058c4 1344/**
3621a710 1345 * lpfc_hb_timeout_handler - The HBA-timer timeout handler
e59058c4
JS
1346 * @phba: pointer to lpfc hba data structure.
1347 *
1348 * This is the actual HBA-timer timeout handler to be invoked by the worker
1349 * thread whenever the HBA timer fired and HBA-timeout event posted. This
1350 * handler performs any periodic operations needed for the device. If such
1351 * periodic event has already been attended to either in the interrupt handler
1352 * or by processing slow-ring or fast-ring events within the HBA-timer
1353 * timeout window (LPFC_HB_MBOX_INTERVAL), this handler just simply resets
1354 * the timer for the next timeout period. If lpfc heart-beat mailbox command
1355 * is configured and there is no heart-beat mailbox command outstanding, a
1356 * heart-beat mailbox is issued and timer set properly. Otherwise, if there
1357 * has been a heart-beat mailbox command outstanding, the HBA shall be put
1358 * to offline.
1359 **/
858c9f6c
JS
1360void
1361lpfc_hb_timeout_handler(struct lpfc_hba *phba)
1362{
45ed1190 1363 struct lpfc_vport **vports;
858c9f6c 1364 LPFC_MBOXQ_t *pmboxq;
0ff10d46 1365 struct lpfc_dmabuf *buf_ptr;
45ed1190 1366 int retval, i;
858c9f6c 1367 struct lpfc_sli *psli = &phba->sli;
0ff10d46 1368 LIST_HEAD(completions);
858c9f6c 1369
c490850a
JS
1370 if (phba->cfg_xri_rebalancing) {
1371 /* Multi-XRI pools handler */
1372 lpfc_hb_mxp_handler(phba);
1373 }
858c9f6c 1374
45ed1190
JS
1375 vports = lpfc_create_vport_work_array(phba);
1376 if (vports != NULL)
4258e98e 1377 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
45ed1190 1378 lpfc_rcv_seq_check_edtov(vports[i]);
4258e98e
JS
1379 lpfc_fdmi_num_disc_check(vports[i]);
1380 }
45ed1190
JS
1381 lpfc_destroy_vport_work_array(phba, vports);
1382
858c9f6c 1383 if ((phba->link_state == LPFC_HBA_ERROR) ||
51ef4c26 1384 (phba->pport->load_flag & FC_UNLOADING) ||
858c9f6c
JS
1385 (phba->pport->fc_flag & FC_OFFLINE_MODE))
1386 return;
1387
1388 spin_lock_irq(&phba->pport->work_port_lock);
858c9f6c 1389
256ec0d0
JS
1390 if (time_after(phba->last_completion_time +
1391 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL),
1392 jiffies)) {
858c9f6c
JS
1393 spin_unlock_irq(&phba->pport->work_port_lock);
1394 if (!phba->hb_outstanding)
1395 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1396 jiffies +
1397 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
1398 else
1399 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1400 jiffies +
1401 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
858c9f6c
JS
1402 return;
1403 }
1404 spin_unlock_irq(&phba->pport->work_port_lock);
1405
0ff10d46
JS
1406 if (phba->elsbuf_cnt &&
1407 (phba->elsbuf_cnt == phba->elsbuf_prev_cnt)) {
1408 spin_lock_irq(&phba->hbalock);
1409 list_splice_init(&phba->elsbuf, &completions);
1410 phba->elsbuf_cnt = 0;
1411 phba->elsbuf_prev_cnt = 0;
1412 spin_unlock_irq(&phba->hbalock);
1413
1414 while (!list_empty(&completions)) {
1415 list_remove_head(&completions, buf_ptr,
1416 struct lpfc_dmabuf, list);
1417 lpfc_mbuf_free(phba, buf_ptr->virt, buf_ptr->phys);
1418 kfree(buf_ptr);
1419 }
1420 }
1421 phba->elsbuf_prev_cnt = phba->elsbuf_cnt;
1422
858c9f6c 1423 /* If there is no heart beat outstanding, issue a heartbeat command */
13815c83
JS
1424 if (phba->cfg_enable_hba_heartbeat) {
1425 if (!phba->hb_outstanding) {
bc73905a
JS
1426 if ((!(psli->sli_flag & LPFC_SLI_MBOX_ACTIVE)) &&
1427 (list_empty(&psli->mboxq))) {
1428 pmboxq = mempool_alloc(phba->mbox_mem_pool,
1429 GFP_KERNEL);
1430 if (!pmboxq) {
1431 mod_timer(&phba->hb_tmofunc,
1432 jiffies +
256ec0d0
JS
1433 msecs_to_jiffies(1000 *
1434 LPFC_HB_MBOX_INTERVAL));
bc73905a
JS
1435 return;
1436 }
1437
1438 lpfc_heart_beat(phba, pmboxq);
1439 pmboxq->mbox_cmpl = lpfc_hb_mbox_cmpl;
1440 pmboxq->vport = phba->pport;
1441 retval = lpfc_sli_issue_mbox(phba, pmboxq,
1442 MBX_NOWAIT);
1443
1444 if (retval != MBX_BUSY &&
1445 retval != MBX_SUCCESS) {
1446 mempool_free(pmboxq,
1447 phba->mbox_mem_pool);
1448 mod_timer(&phba->hb_tmofunc,
1449 jiffies +
256ec0d0
JS
1450 msecs_to_jiffies(1000 *
1451 LPFC_HB_MBOX_INTERVAL));
bc73905a
JS
1452 return;
1453 }
1454 phba->skipped_hb = 0;
1455 phba->hb_outstanding = 1;
1456 } else if (time_before_eq(phba->last_completion_time,
1457 phba->skipped_hb)) {
1458 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
1459 "2857 Last completion time not "
1460 " updated in %d ms\n",
1461 jiffies_to_msecs(jiffies
1462 - phba->last_completion_time));
1463 } else
1464 phba->skipped_hb = jiffies;
1465
858c9f6c 1466 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1467 jiffies +
1468 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
858c9f6c 1469 return;
13815c83
JS
1470 } else {
1471 /*
1472 * If heart beat timeout called with hb_outstanding set
dcf2a4e0
JS
1473 * we need to give the hb mailbox cmd a chance to
1474 * complete or TMO.
13815c83 1475 */
dcf2a4e0
JS
1476 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1477 "0459 Adapter heartbeat still out"
1478 "standing:last compl time was %d ms.\n",
1479 jiffies_to_msecs(jiffies
1480 - phba->last_completion_time));
1481 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1482 jiffies +
1483 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
858c9f6c 1484 }
4258e98e
JS
1485 } else {
1486 mod_timer(&phba->hb_tmofunc,
1487 jiffies +
1488 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
1489 }
1490}
1491
e59058c4 1492/**
3621a710 1493 * lpfc_offline_eratt - Bring lpfc offline on hardware error attention
e59058c4
JS
1494 * @phba: pointer to lpfc hba data structure.
1495 *
1496 * This routine is called to bring the HBA offline when HBA hardware error
1497 * other than Port Error 6 has been detected.
1498 **/
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1499static void
1500lpfc_offline_eratt(struct lpfc_hba *phba)
1501{
1502 struct lpfc_sli *psli = &phba->sli;
1503
1504 spin_lock_irq(&phba->hbalock);
f4b4c68f 1505 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
09372820 1506 spin_unlock_irq(&phba->hbalock);
618a5230 1507 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
09372820
JS
1508
1509 lpfc_offline(phba);
1510 lpfc_reset_barrier(phba);
f4b4c68f 1511 spin_lock_irq(&phba->hbalock);
09372820 1512 lpfc_sli_brdreset(phba);
f4b4c68f 1513 spin_unlock_irq(&phba->hbalock);
09372820
JS
1514 lpfc_hba_down_post(phba);
1515 lpfc_sli_brdready(phba, HS_MBRDY);
1516 lpfc_unblock_mgmt_io(phba);
1517 phba->link_state = LPFC_HBA_ERROR;
1518 return;
1519}
1520
da0436e9
JS
1521/**
1522 * lpfc_sli4_offline_eratt - Bring lpfc offline on SLI4 hardware error attention
1523 * @phba: pointer to lpfc hba data structure.
1524 *
1525 * This routine is called to bring a SLI4 HBA offline when HBA hardware error
1526 * other than Port Error 6 has been detected.
1527 **/
a88dbb6a 1528void
da0436e9
JS
1529lpfc_sli4_offline_eratt(struct lpfc_hba *phba)
1530{
946727dc
JS
1531 spin_lock_irq(&phba->hbalock);
1532 phba->link_state = LPFC_HBA_ERROR;
1533 spin_unlock_irq(&phba->hbalock);
1534
618a5230 1535 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
da0436e9 1536 lpfc_offline(phba);
da0436e9 1537 lpfc_hba_down_post(phba);
da0436e9 1538 lpfc_unblock_mgmt_io(phba);
da0436e9
JS
1539}
1540
a257bf90
JS
1541/**
1542 * lpfc_handle_deferred_eratt - The HBA hardware deferred error handler
1543 * @phba: pointer to lpfc hba data structure.
1544 *
1545 * This routine is invoked to handle the deferred HBA hardware error
1546 * conditions. This type of error is indicated by HBA by setting ER1
1547 * and another ER bit in the host status register. The driver will
1548 * wait until the ER1 bit clears before handling the error condition.
1549 **/
1550static void
1551lpfc_handle_deferred_eratt(struct lpfc_hba *phba)
1552{
1553 uint32_t old_host_status = phba->work_hs;
a257bf90
JS
1554 struct lpfc_sli *psli = &phba->sli;
1555
f4b4c68f
JS
1556 /* If the pci channel is offline, ignore possible errors,
1557 * since we cannot communicate with the pci card anyway.
1558 */
1559 if (pci_channel_offline(phba->pcidev)) {
1560 spin_lock_irq(&phba->hbalock);
1561 phba->hba_flag &= ~DEFER_ERATT;
1562 spin_unlock_irq(&phba->hbalock);
1563 return;
1564 }
1565
a257bf90
JS
1566 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1567 "0479 Deferred Adapter Hardware Error "
1568 "Data: x%x x%x x%x\n",
1569 phba->work_hs,
1570 phba->work_status[0], phba->work_status[1]);
1571
1572 spin_lock_irq(&phba->hbalock);
f4b4c68f 1573 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
a257bf90
JS
1574 spin_unlock_irq(&phba->hbalock);
1575
1576
1577 /*
1578 * Firmware stops when it triggred erratt. That could cause the I/Os
1579 * dropped by the firmware. Error iocb (I/O) on txcmplq and let the
1580 * SCSI layer retry it after re-establishing link.
1581 */
db55fba8 1582 lpfc_sli_abort_fcp_rings(phba);
a257bf90
JS
1583
1584 /*
1585 * There was a firmware error. Take the hba offline and then
1586 * attempt to restart it.
1587 */
618a5230 1588 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
a257bf90
JS
1589 lpfc_offline(phba);
1590
1591 /* Wait for the ER1 bit to clear.*/
1592 while (phba->work_hs & HS_FFER1) {
1593 msleep(100);
9940b97b
JS
1594 if (lpfc_readl(phba->HSregaddr, &phba->work_hs)) {
1595 phba->work_hs = UNPLUG_ERR ;
1596 break;
1597 }
a257bf90
JS
1598 /* If driver is unloading let the worker thread continue */
1599 if (phba->pport->load_flag & FC_UNLOADING) {
1600 phba->work_hs = 0;
1601 break;
1602 }
1603 }
1604
1605 /*
1606 * This is to ptrotect against a race condition in which
1607 * first write to the host attention register clear the
1608 * host status register.
1609 */
1610 if ((!phba->work_hs) && (!(phba->pport->load_flag & FC_UNLOADING)))
1611 phba->work_hs = old_host_status & ~HS_FFER1;
1612
3772a991 1613 spin_lock_irq(&phba->hbalock);
a257bf90 1614 phba->hba_flag &= ~DEFER_ERATT;
3772a991 1615 spin_unlock_irq(&phba->hbalock);
a257bf90
JS
1616 phba->work_status[0] = readl(phba->MBslimaddr + 0xa8);
1617 phba->work_status[1] = readl(phba->MBslimaddr + 0xac);
1618}
1619
3772a991
JS
1620static void
1621lpfc_board_errevt_to_mgmt(struct lpfc_hba *phba)
1622{
1623 struct lpfc_board_event_header board_event;
1624 struct Scsi_Host *shost;
1625
1626 board_event.event_type = FC_REG_BOARD_EVENT;
1627 board_event.subcategory = LPFC_EVENT_PORTINTERR;
1628 shost = lpfc_shost_from_vport(phba->pport);
1629 fc_host_post_vendor_event(shost, fc_get_event_number(),
1630 sizeof(board_event),
1631 (char *) &board_event,
1632 LPFC_NL_VENDOR_ID);
1633}
1634
e59058c4 1635/**
3772a991 1636 * lpfc_handle_eratt_s3 - The SLI3 HBA hardware error handler
e59058c4
JS
1637 * @phba: pointer to lpfc hba data structure.
1638 *
1639 * This routine is invoked to handle the following HBA hardware error
1640 * conditions:
1641 * 1 - HBA error attention interrupt
1642 * 2 - DMA ring index out of range
1643 * 3 - Mailbox command came back as unknown
1644 **/
3772a991
JS
1645static void
1646lpfc_handle_eratt_s3(struct lpfc_hba *phba)
dea3101e 1647{
2e0fef85 1648 struct lpfc_vport *vport = phba->pport;
2e0fef85 1649 struct lpfc_sli *psli = &phba->sli;
d2873e4c 1650 uint32_t event_data;
57127f15
JS
1651 unsigned long temperature;
1652 struct temp_event temp_event_data;
92d7f7b0 1653 struct Scsi_Host *shost;
2e0fef85 1654
8d63f375 1655 /* If the pci channel is offline, ignore possible errors,
3772a991
JS
1656 * since we cannot communicate with the pci card anyway.
1657 */
1658 if (pci_channel_offline(phba->pcidev)) {
1659 spin_lock_irq(&phba->hbalock);
1660 phba->hba_flag &= ~DEFER_ERATT;
1661 spin_unlock_irq(&phba->hbalock);
8d63f375 1662 return;
3772a991
JS
1663 }
1664
13815c83
JS
1665 /* If resets are disabled then leave the HBA alone and return */
1666 if (!phba->cfg_enable_hba_reset)
1667 return;
dea3101e 1668
ea2151b4 1669 /* Send an internal error event to mgmt application */
3772a991 1670 lpfc_board_errevt_to_mgmt(phba);
ea2151b4 1671
a257bf90
JS
1672 if (phba->hba_flag & DEFER_ERATT)
1673 lpfc_handle_deferred_eratt(phba);
1674
dcf2a4e0
JS
1675 if ((phba->work_hs & HS_FFER6) || (phba->work_hs & HS_FFER8)) {
1676 if (phba->work_hs & HS_FFER6)
1677 /* Re-establishing Link */
1678 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1679 "1301 Re-establishing Link "
1680 "Data: x%x x%x x%x\n",
1681 phba->work_hs, phba->work_status[0],
1682 phba->work_status[1]);
1683 if (phba->work_hs & HS_FFER8)
1684 /* Device Zeroization */
1685 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1686 "2861 Host Authentication device "
1687 "zeroization Data:x%x x%x x%x\n",
1688 phba->work_hs, phba->work_status[0],
1689 phba->work_status[1]);
58da1ffb 1690
92d7f7b0 1691 spin_lock_irq(&phba->hbalock);
f4b4c68f 1692 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
92d7f7b0 1693 spin_unlock_irq(&phba->hbalock);
dea3101e 1694
1695 /*
1696 * Firmware stops when it triggled erratt with HS_FFER6.
1697 * That could cause the I/Os dropped by the firmware.
1698 * Error iocb (I/O) on txcmplq and let the SCSI layer
1699 * retry it after re-establishing link.
1700 */
db55fba8 1701 lpfc_sli_abort_fcp_rings(phba);
dea3101e 1702
dea3101e 1703 /*
1704 * There was a firmware error. Take the hba offline and then
1705 * attempt to restart it.
1706 */
618a5230 1707 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
dea3101e 1708 lpfc_offline(phba);
41415862 1709 lpfc_sli_brdrestart(phba);
dea3101e 1710 if (lpfc_online(phba) == 0) { /* Initialize the HBA */
46fa311e 1711 lpfc_unblock_mgmt_io(phba);
dea3101e 1712 return;
1713 }
46fa311e 1714 lpfc_unblock_mgmt_io(phba);
57127f15
JS
1715 } else if (phba->work_hs & HS_CRIT_TEMP) {
1716 temperature = readl(phba->MBslimaddr + TEMPERATURE_OFFSET);
1717 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1718 temp_event_data.event_code = LPFC_CRIT_TEMP;
1719 temp_event_data.data = (uint32_t)temperature;
1720
1721 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
d7c255b2 1722 "0406 Adapter maximum temperature exceeded "
57127f15
JS
1723 "(%ld), taking this port offline "
1724 "Data: x%x x%x x%x\n",
1725 temperature, phba->work_hs,
1726 phba->work_status[0], phba->work_status[1]);
1727
1728 shost = lpfc_shost_from_vport(phba->pport);
1729 fc_host_post_vendor_event(shost, fc_get_event_number(),
1730 sizeof(temp_event_data),
1731 (char *) &temp_event_data,
1732 SCSI_NL_VID_TYPE_PCI
1733 | PCI_VENDOR_ID_EMULEX);
1734
7af67051 1735 spin_lock_irq(&phba->hbalock);
7af67051
JS
1736 phba->over_temp_state = HBA_OVER_TEMP;
1737 spin_unlock_irq(&phba->hbalock);
09372820 1738 lpfc_offline_eratt(phba);
57127f15 1739
dea3101e 1740 } else {
1741 /* The if clause above forces this code path when the status
9399627f
JS
1742 * failure is a value other than FFER6. Do not call the offline
1743 * twice. This is the adapter hardware error path.
dea3101e 1744 */
1745 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e8b62011 1746 "0457 Adapter Hardware Error "
dea3101e 1747 "Data: x%x x%x x%x\n",
e8b62011 1748 phba->work_hs,
dea3101e 1749 phba->work_status[0], phba->work_status[1]);
1750
d2873e4c 1751 event_data = FC_REG_DUMP_EVENT;
92d7f7b0 1752 shost = lpfc_shost_from_vport(vport);
2e0fef85 1753 fc_host_post_vendor_event(shost, fc_get_event_number(),
d2873e4c
JS
1754 sizeof(event_data), (char *) &event_data,
1755 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
1756
09372820 1757 lpfc_offline_eratt(phba);
dea3101e 1758 }
9399627f 1759 return;
dea3101e 1760}
1761
618a5230
JS
1762/**
1763 * lpfc_sli4_port_sta_fn_reset - The SLI4 function reset due to port status reg
1764 * @phba: pointer to lpfc hba data structure.
1765 * @mbx_action: flag for mailbox shutdown action.
1766 *
1767 * This routine is invoked to perform an SLI4 port PCI function reset in
1768 * response to port status register polling attention. It waits for port
1769 * status register (ERR, RDY, RN) bits before proceeding with function reset.
1770 * During this process, interrupt vectors are freed and later requested
1771 * for handling possible port resource change.
1772 **/
1773static int
e10b2022
JS
1774lpfc_sli4_port_sta_fn_reset(struct lpfc_hba *phba, int mbx_action,
1775 bool en_rn_msg)
618a5230
JS
1776{
1777 int rc;
1778 uint32_t intr_mode;
1779
27d6ac0a 1780 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) >=
65791f1f
JS
1781 LPFC_SLI_INTF_IF_TYPE_2) {
1782 /*
1783 * On error status condition, driver need to wait for port
1784 * ready before performing reset.
1785 */
1786 rc = lpfc_sli4_pdev_status_reg_wait(phba);
0e916ee7 1787 if (rc)
65791f1f
JS
1788 return rc;
1789 }
0e916ee7 1790
65791f1f
JS
1791 /* need reset: attempt for port recovery */
1792 if (en_rn_msg)
1793 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1794 "2887 Reset Needed: Attempting Port "
1795 "Recovery...\n");
1796 lpfc_offline_prep(phba, mbx_action);
1797 lpfc_offline(phba);
1798 /* release interrupt for possible resource change */
1799 lpfc_sli4_disable_intr(phba);
5a9eeff5
JS
1800 rc = lpfc_sli_brdrestart(phba);
1801 if (rc) {
1802 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1803 "6309 Failed to restart board\n");
1804 return rc;
1805 }
65791f1f
JS
1806 /* request and enable interrupt */
1807 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
1808 if (intr_mode == LPFC_INTR_ERROR) {
1809 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1810 "3175 Failed to enable interrupt\n");
1811 return -EIO;
618a5230 1812 }
65791f1f
JS
1813 phba->intr_mode = intr_mode;
1814 rc = lpfc_online(phba);
1815 if (rc == 0)
1816 lpfc_unblock_mgmt_io(phba);
1817
618a5230
JS
1818 return rc;
1819}
1820
da0436e9
JS
1821/**
1822 * lpfc_handle_eratt_s4 - The SLI4 HBA hardware error handler
1823 * @phba: pointer to lpfc hba data structure.
1824 *
1825 * This routine is invoked to handle the SLI4 HBA hardware error attention
1826 * conditions.
1827 **/
1828static void
1829lpfc_handle_eratt_s4(struct lpfc_hba *phba)
1830{
1831 struct lpfc_vport *vport = phba->pport;
1832 uint32_t event_data;
1833 struct Scsi_Host *shost;
2fcee4bf 1834 uint32_t if_type;
2e90f4b5
JS
1835 struct lpfc_register portstat_reg = {0};
1836 uint32_t reg_err1, reg_err2;
1837 uint32_t uerrlo_reg, uemasklo_reg;
65791f1f 1838 uint32_t smphr_port_status = 0, pci_rd_rc1, pci_rd_rc2;
e10b2022 1839 bool en_rn_msg = true;
946727dc 1840 struct temp_event temp_event_data;
65791f1f
JS
1841 struct lpfc_register portsmphr_reg;
1842 int rc, i;
da0436e9
JS
1843
1844 /* If the pci channel is offline, ignore possible errors, since
1845 * we cannot communicate with the pci card anyway.
1846 */
32a93100
JS
1847 if (pci_channel_offline(phba->pcidev)) {
1848 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1849 "3166 pci channel is offline\n");
1850 lpfc_sli4_offline_eratt(phba);
da0436e9 1851 return;
32a93100 1852 }
da0436e9 1853
65791f1f 1854 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
2fcee4bf
JS
1855 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
1856 switch (if_type) {
1857 case LPFC_SLI_INTF_IF_TYPE_0:
2e90f4b5
JS
1858 pci_rd_rc1 = lpfc_readl(
1859 phba->sli4_hba.u.if_type0.UERRLOregaddr,
1860 &uerrlo_reg);
1861 pci_rd_rc2 = lpfc_readl(
1862 phba->sli4_hba.u.if_type0.UEMASKLOregaddr,
1863 &uemasklo_reg);
1864 /* consider PCI bus read error as pci_channel_offline */
1865 if (pci_rd_rc1 == -EIO && pci_rd_rc2 == -EIO)
1866 return;
65791f1f
JS
1867 if (!(phba->hba_flag & HBA_RECOVERABLE_UE)) {
1868 lpfc_sli4_offline_eratt(phba);
1869 return;
1870 }
1871 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1872 "7623 Checking UE recoverable");
1873
1874 for (i = 0; i < phba->sli4_hba.ue_to_sr / 1000; i++) {
1875 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
1876 &portsmphr_reg.word0))
1877 continue;
1878
1879 smphr_port_status = bf_get(lpfc_port_smphr_port_status,
1880 &portsmphr_reg);
1881 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
1882 LPFC_PORT_SEM_UE_RECOVERABLE)
1883 break;
1884 /*Sleep for 1Sec, before checking SEMAPHORE */
1885 msleep(1000);
1886 }
1887
1888 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1889 "4827 smphr_port_status x%x : Waited %dSec",
1890 smphr_port_status, i);
1891
1892 /* Recoverable UE, reset the HBA device */
1893 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
1894 LPFC_PORT_SEM_UE_RECOVERABLE) {
1895 for (i = 0; i < 20; i++) {
1896 msleep(1000);
1897 if (!lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
1898 &portsmphr_reg.word0) &&
1899 (LPFC_POST_STAGE_PORT_READY ==
1900 bf_get(lpfc_port_smphr_port_status,
1901 &portsmphr_reg))) {
1902 rc = lpfc_sli4_port_sta_fn_reset(phba,
1903 LPFC_MBX_NO_WAIT, en_rn_msg);
1904 if (rc == 0)
1905 return;
1906 lpfc_printf_log(phba,
1907 KERN_ERR, LOG_INIT,
1908 "4215 Failed to recover UE");
1909 break;
1910 }
1911 }
1912 }
1913 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1914 "7624 Firmware not ready: Failing UE recovery,"
1915 " waited %dSec", i);
2fcee4bf
JS
1916 lpfc_sli4_offline_eratt(phba);
1917 break;
946727dc 1918
2fcee4bf 1919 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 1920 case LPFC_SLI_INTF_IF_TYPE_6:
2e90f4b5
JS
1921 pci_rd_rc1 = lpfc_readl(
1922 phba->sli4_hba.u.if_type2.STATUSregaddr,
1923 &portstat_reg.word0);
1924 /* consider PCI bus read error as pci_channel_offline */
6b5151fd
JS
1925 if (pci_rd_rc1 == -EIO) {
1926 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1927 "3151 PCI bus read access failure: x%x\n",
1928 readl(phba->sli4_hba.u.if_type2.STATUSregaddr));
32a93100 1929 lpfc_sli4_offline_eratt(phba);
2e90f4b5 1930 return;
6b5151fd 1931 }
2e90f4b5
JS
1932 reg_err1 = readl(phba->sli4_hba.u.if_type2.ERR1regaddr);
1933 reg_err2 = readl(phba->sli4_hba.u.if_type2.ERR2regaddr);
2fcee4bf 1934 if (bf_get(lpfc_sliport_status_oti, &portstat_reg)) {
2fcee4bf
JS
1935 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1936 "2889 Port Overtemperature event, "
946727dc
JS
1937 "taking port offline Data: x%x x%x\n",
1938 reg_err1, reg_err2);
1939
310429ef 1940 phba->sfp_alarm |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
946727dc
JS
1941 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1942 temp_event_data.event_code = LPFC_CRIT_TEMP;
1943 temp_event_data.data = 0xFFFFFFFF;
1944
1945 shost = lpfc_shost_from_vport(phba->pport);
1946 fc_host_post_vendor_event(shost, fc_get_event_number(),
1947 sizeof(temp_event_data),
1948 (char *)&temp_event_data,
1949 SCSI_NL_VID_TYPE_PCI
1950 | PCI_VENDOR_ID_EMULEX);
1951
2fcee4bf
JS
1952 spin_lock_irq(&phba->hbalock);
1953 phba->over_temp_state = HBA_OVER_TEMP;
1954 spin_unlock_irq(&phba->hbalock);
1955 lpfc_sli4_offline_eratt(phba);
946727dc 1956 return;
2fcee4bf 1957 }
2e90f4b5 1958 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
e10b2022 1959 reg_err2 == SLIPORT_ERR2_REG_FW_RESTART) {
2e90f4b5 1960 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e10b2022
JS
1961 "3143 Port Down: Firmware Update "
1962 "Detected\n");
1963 en_rn_msg = false;
1964 } else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
2e90f4b5
JS
1965 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
1966 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1967 "3144 Port Down: Debug Dump\n");
1968 else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1969 reg_err2 == SLIPORT_ERR2_REG_FUNC_PROVISON)
1970 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1971 "3145 Port Down: Provisioning\n");
618a5230 1972
946727dc
JS
1973 /* If resets are disabled then leave the HBA alone and return */
1974 if (!phba->cfg_enable_hba_reset)
1975 return;
1976
618a5230 1977 /* Check port status register for function reset */
e10b2022
JS
1978 rc = lpfc_sli4_port_sta_fn_reset(phba, LPFC_MBX_NO_WAIT,
1979 en_rn_msg);
618a5230
JS
1980 if (rc == 0) {
1981 /* don't report event on forced debug dump */
1982 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1983 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
1984 return;
1985 else
1986 break;
2fcee4bf 1987 }
618a5230 1988 /* fall through for not able to recover */
6b5151fd
JS
1989 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1990 "3152 Unrecoverable error, bring the port "
1991 "offline\n");
2fcee4bf
JS
1992 lpfc_sli4_offline_eratt(phba);
1993 break;
1994 case LPFC_SLI_INTF_IF_TYPE_1:
1995 default:
1996 break;
1997 }
2e90f4b5
JS
1998 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1999 "3123 Report dump event to upper layer\n");
2000 /* Send an internal error event to mgmt application */
2001 lpfc_board_errevt_to_mgmt(phba);
2002
2003 event_data = FC_REG_DUMP_EVENT;
2004 shost = lpfc_shost_from_vport(vport);
2005 fc_host_post_vendor_event(shost, fc_get_event_number(),
2006 sizeof(event_data), (char *) &event_data,
2007 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
da0436e9
JS
2008}
2009
2010/**
2011 * lpfc_handle_eratt - Wrapper func for handling hba error attention
2012 * @phba: pointer to lpfc HBA data structure.
2013 *
2014 * This routine wraps the actual SLI3 or SLI4 hba error attention handling
2015 * routine from the API jump table function pointer from the lpfc_hba struct.
2016 *
2017 * Return codes
af901ca1 2018 * 0 - success.
da0436e9
JS
2019 * Any other value - error.
2020 **/
2021void
2022lpfc_handle_eratt(struct lpfc_hba *phba)
2023{
2024 (*phba->lpfc_handle_eratt)(phba);
2025}
2026
e59058c4 2027/**
3621a710 2028 * lpfc_handle_latt - The HBA link event handler
e59058c4
JS
2029 * @phba: pointer to lpfc hba data structure.
2030 *
2031 * This routine is invoked from the worker thread to handle a HBA host
895427bd 2032 * attention link event. SLI3 only.
e59058c4 2033 **/
dea3101e 2034void
2e0fef85 2035lpfc_handle_latt(struct lpfc_hba *phba)
dea3101e 2036{
2e0fef85
JS
2037 struct lpfc_vport *vport = phba->pport;
2038 struct lpfc_sli *psli = &phba->sli;
dea3101e 2039 LPFC_MBOXQ_t *pmb;
2040 volatile uint32_t control;
2041 struct lpfc_dmabuf *mp;
09372820 2042 int rc = 0;
dea3101e 2043
2044 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
09372820
JS
2045 if (!pmb) {
2046 rc = 1;
dea3101e 2047 goto lpfc_handle_latt_err_exit;
09372820 2048 }
dea3101e 2049
2050 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
09372820
JS
2051 if (!mp) {
2052 rc = 2;
dea3101e 2053 goto lpfc_handle_latt_free_pmb;
09372820 2054 }
dea3101e 2055
2056 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
09372820
JS
2057 if (!mp->virt) {
2058 rc = 3;
dea3101e 2059 goto lpfc_handle_latt_free_mp;
09372820 2060 }
dea3101e 2061
6281bfe0 2062 /* Cleanup any outstanding ELS commands */
549e55cd 2063 lpfc_els_flush_all_cmd(phba);
dea3101e 2064
2065 psli->slistat.link_event++;
76a95d75
JS
2066 lpfc_read_topology(phba, pmb, mp);
2067 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
2e0fef85 2068 pmb->vport = vport;
0d2b6b83 2069 /* Block ELS IOCBs until we have processed this mbox command */
895427bd 2070 phba->sli.sli3_ring[LPFC_ELS_RING].flag |= LPFC_STOP_IOCB_EVENT;
0b727fea 2071 rc = lpfc_sli_issue_mbox (phba, pmb, MBX_NOWAIT);
09372820
JS
2072 if (rc == MBX_NOT_FINISHED) {
2073 rc = 4;
14691150 2074 goto lpfc_handle_latt_free_mbuf;
09372820 2075 }
dea3101e 2076
2077 /* Clear Link Attention in HA REG */
2e0fef85 2078 spin_lock_irq(&phba->hbalock);
dea3101e 2079 writel(HA_LATT, phba->HAregaddr);
2080 readl(phba->HAregaddr); /* flush */
2e0fef85 2081 spin_unlock_irq(&phba->hbalock);
dea3101e 2082
2083 return;
2084
14691150 2085lpfc_handle_latt_free_mbuf:
895427bd 2086 phba->sli.sli3_ring[LPFC_ELS_RING].flag &= ~LPFC_STOP_IOCB_EVENT;
14691150 2087 lpfc_mbuf_free(phba, mp->virt, mp->phys);
dea3101e 2088lpfc_handle_latt_free_mp:
2089 kfree(mp);
2090lpfc_handle_latt_free_pmb:
1dcb58e5 2091 mempool_free(pmb, phba->mbox_mem_pool);
dea3101e 2092lpfc_handle_latt_err_exit:
2093 /* Enable Link attention interrupts */
2e0fef85 2094 spin_lock_irq(&phba->hbalock);
dea3101e 2095 psli->sli_flag |= LPFC_PROCESS_LA;
2096 control = readl(phba->HCregaddr);
2097 control |= HC_LAINT_ENA;
2098 writel(control, phba->HCregaddr);
2099 readl(phba->HCregaddr); /* flush */
2100
2101 /* Clear Link Attention in HA REG */
2102 writel(HA_LATT, phba->HAregaddr);
2103 readl(phba->HAregaddr); /* flush */
2e0fef85 2104 spin_unlock_irq(&phba->hbalock);
dea3101e 2105 lpfc_linkdown(phba);
2e0fef85 2106 phba->link_state = LPFC_HBA_ERROR;
dea3101e 2107
09372820
JS
2108 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
2109 "0300 LATT: Cannot issue READ_LA: Data:%d\n", rc);
dea3101e 2110
2111 return;
2112}
2113
e59058c4 2114/**
3621a710 2115 * lpfc_parse_vpd - Parse VPD (Vital Product Data)
e59058c4
JS
2116 * @phba: pointer to lpfc hba data structure.
2117 * @vpd: pointer to the vital product data.
2118 * @len: length of the vital product data in bytes.
2119 *
2120 * This routine parses the Vital Product Data (VPD). The VPD is treated as
2121 * an array of characters. In this routine, the ModelName, ProgramType, and
2122 * ModelDesc, etc. fields of the phba data structure will be populated.
2123 *
2124 * Return codes
2125 * 0 - pointer to the VPD passed in is NULL
2126 * 1 - success
2127 **/
3772a991 2128int
2e0fef85 2129lpfc_parse_vpd(struct lpfc_hba *phba, uint8_t *vpd, int len)
dea3101e 2130{
2131 uint8_t lenlo, lenhi;
07da60c1 2132 int Length;
dea3101e 2133 int i, j;
2134 int finished = 0;
2135 int index = 0;
2136
2137 if (!vpd)
2138 return 0;
2139
2140 /* Vital Product */
ed957684 2141 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011 2142 "0455 Vital Product Data: x%x x%x x%x x%x\n",
dea3101e 2143 (uint32_t) vpd[0], (uint32_t) vpd[1], (uint32_t) vpd[2],
2144 (uint32_t) vpd[3]);
74b72a59 2145 while (!finished && (index < (len - 4))) {
dea3101e 2146 switch (vpd[index]) {
2147 case 0x82:
74b72a59 2148 case 0x91:
dea3101e 2149 index += 1;
2150 lenlo = vpd[index];
2151 index += 1;
2152 lenhi = vpd[index];
2153 index += 1;
2154 i = ((((unsigned short)lenhi) << 8) + lenlo);
2155 index += i;
2156 break;
2157 case 0x90:
2158 index += 1;
2159 lenlo = vpd[index];
2160 index += 1;
2161 lenhi = vpd[index];
2162 index += 1;
2163 Length = ((((unsigned short)lenhi) << 8) + lenlo);
74b72a59
JW
2164 if (Length > len - index)
2165 Length = len - index;
dea3101e 2166 while (Length > 0) {
2167 /* Look for Serial Number */
2168 if ((vpd[index] == 'S') && (vpd[index+1] == 'N')) {
2169 index += 2;
2170 i = vpd[index];
2171 index += 1;
2172 j = 0;
2173 Length -= (3+i);
2174 while(i--) {
2175 phba->SerialNumber[j++] = vpd[index++];
2176 if (j == 31)
2177 break;
2178 }
2179 phba->SerialNumber[j] = 0;
2180 continue;
2181 }
2182 else if ((vpd[index] == 'V') && (vpd[index+1] == '1')) {
2183 phba->vpd_flag |= VPD_MODEL_DESC;
2184 index += 2;
2185 i = vpd[index];
2186 index += 1;
2187 j = 0;
2188 Length -= (3+i);
2189 while(i--) {
2190 phba->ModelDesc[j++] = vpd[index++];
2191 if (j == 255)
2192 break;
2193 }
2194 phba->ModelDesc[j] = 0;
2195 continue;
2196 }
2197 else if ((vpd[index] == 'V') && (vpd[index+1] == '2')) {
2198 phba->vpd_flag |= VPD_MODEL_NAME;
2199 index += 2;
2200 i = vpd[index];
2201 index += 1;
2202 j = 0;
2203 Length -= (3+i);
2204 while(i--) {
2205 phba->ModelName[j++] = vpd[index++];
2206 if (j == 79)
2207 break;
2208 }
2209 phba->ModelName[j] = 0;
2210 continue;
2211 }
2212 else if ((vpd[index] == 'V') && (vpd[index+1] == '3')) {
2213 phba->vpd_flag |= VPD_PROGRAM_TYPE;
2214 index += 2;
2215 i = vpd[index];
2216 index += 1;
2217 j = 0;
2218 Length -= (3+i);
2219 while(i--) {
2220 phba->ProgramType[j++] = vpd[index++];
2221 if (j == 255)
2222 break;
2223 }
2224 phba->ProgramType[j] = 0;
2225 continue;
2226 }
2227 else if ((vpd[index] == 'V') && (vpd[index+1] == '4')) {
2228 phba->vpd_flag |= VPD_PORT;
2229 index += 2;
2230 i = vpd[index];
2231 index += 1;
2232 j = 0;
2233 Length -= (3+i);
2234 while(i--) {
cd1c8301
JS
2235 if ((phba->sli_rev == LPFC_SLI_REV4) &&
2236 (phba->sli4_hba.pport_name_sta ==
2237 LPFC_SLI4_PPNAME_GET)) {
2238 j++;
2239 index++;
2240 } else
2241 phba->Port[j++] = vpd[index++];
2242 if (j == 19)
2243 break;
dea3101e 2244 }
cd1c8301
JS
2245 if ((phba->sli_rev != LPFC_SLI_REV4) ||
2246 (phba->sli4_hba.pport_name_sta ==
2247 LPFC_SLI4_PPNAME_NON))
2248 phba->Port[j] = 0;
dea3101e 2249 continue;
2250 }
2251 else {
2252 index += 2;
2253 i = vpd[index];
2254 index += 1;
2255 index += i;
2256 Length -= (3 + i);
2257 }
2258 }
2259 finished = 0;
2260 break;
2261 case 0x78:
2262 finished = 1;
2263 break;
2264 default:
2265 index ++;
2266 break;
2267 }
74b72a59 2268 }
dea3101e 2269
2270 return(1);
2271}
2272
e59058c4 2273/**
3621a710 2274 * lpfc_get_hba_model_desc - Retrieve HBA device model name and description
e59058c4
JS
2275 * @phba: pointer to lpfc hba data structure.
2276 * @mdp: pointer to the data structure to hold the derived model name.
2277 * @descp: pointer to the data structure to hold the derived description.
2278 *
2279 * This routine retrieves HBA's description based on its registered PCI device
2280 * ID. The @descp passed into this function points to an array of 256 chars. It
2281 * shall be returned with the model name, maximum speed, and the host bus type.
2282 * The @mdp passed into this function points to an array of 80 chars. When the
2283 * function returns, the @mdp will be filled with the model name.
2284 **/
dea3101e 2285static void
2e0fef85 2286lpfc_get_hba_model_desc(struct lpfc_hba *phba, uint8_t *mdp, uint8_t *descp)
dea3101e 2287{
2288 lpfc_vpd_t *vp;
fefcb2b6 2289 uint16_t dev_id = phba->pcidev->device;
74b72a59 2290 int max_speed;
84774a4d 2291 int GE = 0;
da0436e9 2292 int oneConnect = 0; /* default is not a oneConnect */
74b72a59 2293 struct {
a747c9ce
JS
2294 char *name;
2295 char *bus;
2296 char *function;
2297 } m = {"<Unknown>", "", ""};
74b72a59
JW
2298
2299 if (mdp && mdp[0] != '\0'
2300 && descp && descp[0] != '\0')
2301 return;
2302
fbd8a6ba
JS
2303 if (phba->lmt & LMT_64Gb)
2304 max_speed = 64;
2305 else if (phba->lmt & LMT_32Gb)
d38dd52c
JS
2306 max_speed = 32;
2307 else if (phba->lmt & LMT_16Gb)
c0c11512
JS
2308 max_speed = 16;
2309 else if (phba->lmt & LMT_10Gb)
74b72a59
JW
2310 max_speed = 10;
2311 else if (phba->lmt & LMT_8Gb)
2312 max_speed = 8;
2313 else if (phba->lmt & LMT_4Gb)
2314 max_speed = 4;
2315 else if (phba->lmt & LMT_2Gb)
2316 max_speed = 2;
4169d868 2317 else if (phba->lmt & LMT_1Gb)
74b72a59 2318 max_speed = 1;
4169d868
JS
2319 else
2320 max_speed = 0;
dea3101e 2321
2322 vp = &phba->vpd;
dea3101e 2323
e4adb204 2324 switch (dev_id) {
06325e74 2325 case PCI_DEVICE_ID_FIREFLY:
12222f4f
JS
2326 m = (typeof(m)){"LP6000", "PCI",
2327 "Obsolete, Unsupported Fibre Channel Adapter"};
06325e74 2328 break;
dea3101e 2329 case PCI_DEVICE_ID_SUPERFLY:
2330 if (vp->rev.biuRev >= 1 && vp->rev.biuRev <= 3)
12222f4f 2331 m = (typeof(m)){"LP7000", "PCI", ""};
dea3101e 2332 else
12222f4f
JS
2333 m = (typeof(m)){"LP7000E", "PCI", ""};
2334 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
dea3101e 2335 break;
2336 case PCI_DEVICE_ID_DRAGONFLY:
a747c9ce 2337 m = (typeof(m)){"LP8000", "PCI",
12222f4f 2338 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2339 break;
2340 case PCI_DEVICE_ID_CENTAUR:
2341 if (FC_JEDEC_ID(vp->rev.biuRev) == CENTAUR_2G_JEDEC_ID)
12222f4f 2342 m = (typeof(m)){"LP9002", "PCI", ""};
dea3101e 2343 else
12222f4f
JS
2344 m = (typeof(m)){"LP9000", "PCI", ""};
2345 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
dea3101e 2346 break;
2347 case PCI_DEVICE_ID_RFLY:
a747c9ce 2348 m = (typeof(m)){"LP952", "PCI",
12222f4f 2349 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2350 break;
2351 case PCI_DEVICE_ID_PEGASUS:
a747c9ce 2352 m = (typeof(m)){"LP9802", "PCI-X",
12222f4f 2353 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2354 break;
2355 case PCI_DEVICE_ID_THOR:
a747c9ce 2356 m = (typeof(m)){"LP10000", "PCI-X",
12222f4f 2357 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2358 break;
2359 case PCI_DEVICE_ID_VIPER:
a747c9ce 2360 m = (typeof(m)){"LPX1000", "PCI-X",
12222f4f 2361 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2362 break;
2363 case PCI_DEVICE_ID_PFLY:
a747c9ce 2364 m = (typeof(m)){"LP982", "PCI-X",
12222f4f 2365 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2366 break;
2367 case PCI_DEVICE_ID_TFLY:
a747c9ce 2368 m = (typeof(m)){"LP1050", "PCI-X",
12222f4f 2369 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2370 break;
2371 case PCI_DEVICE_ID_HELIOS:
a747c9ce 2372 m = (typeof(m)){"LP11000", "PCI-X2",
12222f4f 2373 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2374 break;
e4adb204 2375 case PCI_DEVICE_ID_HELIOS_SCSP:
a747c9ce 2376 m = (typeof(m)){"LP11000-SP", "PCI-X2",
12222f4f 2377 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2378 break;
2379 case PCI_DEVICE_ID_HELIOS_DCSP:
a747c9ce 2380 m = (typeof(m)){"LP11002-SP", "PCI-X2",
12222f4f 2381 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2382 break;
2383 case PCI_DEVICE_ID_NEPTUNE:
12222f4f
JS
2384 m = (typeof(m)){"LPe1000", "PCIe",
2385 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2386 break;
2387 case PCI_DEVICE_ID_NEPTUNE_SCSP:
12222f4f
JS
2388 m = (typeof(m)){"LPe1000-SP", "PCIe",
2389 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2390 break;
2391 case PCI_DEVICE_ID_NEPTUNE_DCSP:
12222f4f
JS
2392 m = (typeof(m)){"LPe1002-SP", "PCIe",
2393 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204 2394 break;
dea3101e 2395 case PCI_DEVICE_ID_BMID:
a747c9ce 2396 m = (typeof(m)){"LP1150", "PCI-X2", "Fibre Channel Adapter"};
dea3101e 2397 break;
2398 case PCI_DEVICE_ID_BSMB:
12222f4f
JS
2399 m = (typeof(m)){"LP111", "PCI-X2",
2400 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2401 break;
2402 case PCI_DEVICE_ID_ZEPHYR:
a747c9ce 2403 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
dea3101e 2404 break;
e4adb204 2405 case PCI_DEVICE_ID_ZEPHYR_SCSP:
a747c9ce 2406 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
e4adb204
JSEC
2407 break;
2408 case PCI_DEVICE_ID_ZEPHYR_DCSP:
a747c9ce 2409 m = (typeof(m)){"LP2105", "PCIe", "FCoE Adapter"};
a257bf90 2410 GE = 1;
e4adb204 2411 break;
dea3101e 2412 case PCI_DEVICE_ID_ZMID:
a747c9ce 2413 m = (typeof(m)){"LPe1150", "PCIe", "Fibre Channel Adapter"};
dea3101e 2414 break;
2415 case PCI_DEVICE_ID_ZSMB:
a747c9ce 2416 m = (typeof(m)){"LPe111", "PCIe", "Fibre Channel Adapter"};
dea3101e 2417 break;
2418 case PCI_DEVICE_ID_LP101:
12222f4f
JS
2419 m = (typeof(m)){"LP101", "PCI-X",
2420 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2421 break;
2422 case PCI_DEVICE_ID_LP10000S:
12222f4f
JS
2423 m = (typeof(m)){"LP10000-S", "PCI",
2424 "Obsolete, Unsupported Fibre Channel Adapter"};
06325e74 2425 break;
e4adb204 2426 case PCI_DEVICE_ID_LP11000S:
12222f4f
JS
2427 m = (typeof(m)){"LP11000-S", "PCI-X2",
2428 "Obsolete, Unsupported Fibre Channel Adapter"};
18a3b596 2429 break;
e4adb204 2430 case PCI_DEVICE_ID_LPE11000S:
12222f4f
JS
2431 m = (typeof(m)){"LPe11000-S", "PCIe",
2432 "Obsolete, Unsupported Fibre Channel Adapter"};
5cc36b3c 2433 break;
b87eab38 2434 case PCI_DEVICE_ID_SAT:
a747c9ce 2435 m = (typeof(m)){"LPe12000", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2436 break;
2437 case PCI_DEVICE_ID_SAT_MID:
a747c9ce 2438 m = (typeof(m)){"LPe1250", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2439 break;
2440 case PCI_DEVICE_ID_SAT_SMB:
a747c9ce 2441 m = (typeof(m)){"LPe121", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2442 break;
2443 case PCI_DEVICE_ID_SAT_DCSP:
a747c9ce 2444 m = (typeof(m)){"LPe12002-SP", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2445 break;
2446 case PCI_DEVICE_ID_SAT_SCSP:
a747c9ce 2447 m = (typeof(m)){"LPe12000-SP", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2448 break;
2449 case PCI_DEVICE_ID_SAT_S:
a747c9ce 2450 m = (typeof(m)){"LPe12000-S", "PCIe", "Fibre Channel Adapter"};
b87eab38 2451 break;
84774a4d 2452 case PCI_DEVICE_ID_HORNET:
12222f4f
JS
2453 m = (typeof(m)){"LP21000", "PCIe",
2454 "Obsolete, Unsupported FCoE Adapter"};
84774a4d
JS
2455 GE = 1;
2456 break;
2457 case PCI_DEVICE_ID_PROTEUS_VF:
a747c9ce 2458 m = (typeof(m)){"LPev12000", "PCIe IOV",
12222f4f 2459 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d
JS
2460 break;
2461 case PCI_DEVICE_ID_PROTEUS_PF:
a747c9ce 2462 m = (typeof(m)){"LPev12000", "PCIe IOV",
12222f4f 2463 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d
JS
2464 break;
2465 case PCI_DEVICE_ID_PROTEUS_S:
a747c9ce 2466 m = (typeof(m)){"LPemv12002-S", "PCIe IOV",
12222f4f 2467 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d 2468 break;
da0436e9
JS
2469 case PCI_DEVICE_ID_TIGERSHARK:
2470 oneConnect = 1;
a747c9ce 2471 m = (typeof(m)){"OCe10100", "PCIe", "FCoE"};
da0436e9 2472 break;
a747c9ce 2473 case PCI_DEVICE_ID_TOMCAT:
6669f9bb 2474 oneConnect = 1;
a747c9ce
JS
2475 m = (typeof(m)){"OCe11100", "PCIe", "FCoE"};
2476 break;
2477 case PCI_DEVICE_ID_FALCON:
2478 m = (typeof(m)){"LPSe12002-ML1-E", "PCIe",
2479 "EmulexSecure Fibre"};
6669f9bb 2480 break;
98fc5dd9
JS
2481 case PCI_DEVICE_ID_BALIUS:
2482 m = (typeof(m)){"LPVe12002", "PCIe Shared I/O",
12222f4f 2483 "Obsolete, Unsupported Fibre Channel Adapter"};
98fc5dd9 2484 break;
085c647c 2485 case PCI_DEVICE_ID_LANCER_FC:
c0c11512 2486 m = (typeof(m)){"LPe16000", "PCIe", "Fibre Channel Adapter"};
085c647c 2487 break;
12222f4f
JS
2488 case PCI_DEVICE_ID_LANCER_FC_VF:
2489 m = (typeof(m)){"LPe16000", "PCIe",
2490 "Obsolete, Unsupported Fibre Channel Adapter"};
2491 break;
085c647c
JS
2492 case PCI_DEVICE_ID_LANCER_FCOE:
2493 oneConnect = 1;
079b5c91 2494 m = (typeof(m)){"OCe15100", "PCIe", "FCoE"};
085c647c 2495 break;
12222f4f
JS
2496 case PCI_DEVICE_ID_LANCER_FCOE_VF:
2497 oneConnect = 1;
2498 m = (typeof(m)){"OCe15100", "PCIe",
2499 "Obsolete, Unsupported FCoE"};
2500 break;
d38dd52c
JS
2501 case PCI_DEVICE_ID_LANCER_G6_FC:
2502 m = (typeof(m)){"LPe32000", "PCIe", "Fibre Channel Adapter"};
2503 break;
c238b9b6
JS
2504 case PCI_DEVICE_ID_LANCER_G7_FC:
2505 m = (typeof(m)){"LPe36000", "PCIe", "Fibre Channel Adapter"};
2506 break;
f8cafd38
JS
2507 case PCI_DEVICE_ID_SKYHAWK:
2508 case PCI_DEVICE_ID_SKYHAWK_VF:
2509 oneConnect = 1;
2510 m = (typeof(m)){"OCe14000", "PCIe", "FCoE"};
2511 break;
5cc36b3c 2512 default:
a747c9ce 2513 m = (typeof(m)){"Unknown", "", ""};
e4adb204 2514 break;
dea3101e 2515 }
74b72a59
JW
2516
2517 if (mdp && mdp[0] == '\0')
2518 snprintf(mdp, 79,"%s", m.name);
c0c11512
JS
2519 /*
2520 * oneConnect hba requires special processing, they are all initiators
da0436e9
JS
2521 * and we put the port number on the end
2522 */
2523 if (descp && descp[0] == '\0') {
2524 if (oneConnect)
2525 snprintf(descp, 255,
4169d868 2526 "Emulex OneConnect %s, %s Initiator %s",
a747c9ce 2527 m.name, m.function,
da0436e9 2528 phba->Port);
4169d868
JS
2529 else if (max_speed == 0)
2530 snprintf(descp, 255,
290237d2 2531 "Emulex %s %s %s",
4169d868 2532 m.name, m.bus, m.function);
da0436e9
JS
2533 else
2534 snprintf(descp, 255,
2535 "Emulex %s %d%s %s %s",
a747c9ce
JS
2536 m.name, max_speed, (GE) ? "GE" : "Gb",
2537 m.bus, m.function);
da0436e9 2538 }
dea3101e 2539}
2540
e59058c4 2541/**
3621a710 2542 * lpfc_post_buffer - Post IOCB(s) with DMA buffer descriptor(s) to a IOCB ring
e59058c4
JS
2543 * @phba: pointer to lpfc hba data structure.
2544 * @pring: pointer to a IOCB ring.
2545 * @cnt: the number of IOCBs to be posted to the IOCB ring.
2546 *
2547 * This routine posts a given number of IOCBs with the associated DMA buffer
2548 * descriptors specified by the cnt argument to the given IOCB ring.
2549 *
2550 * Return codes
2551 * The number of IOCBs NOT able to be posted to the IOCB ring.
2552 **/
dea3101e 2553int
495a714c 2554lpfc_post_buffer(struct lpfc_hba *phba, struct lpfc_sli_ring *pring, int cnt)
dea3101e 2555{
2556 IOCB_t *icmd;
0bd4ca25 2557 struct lpfc_iocbq *iocb;
dea3101e 2558 struct lpfc_dmabuf *mp1, *mp2;
2559
2560 cnt += pring->missbufcnt;
2561
2562 /* While there are buffers to post */
2563 while (cnt > 0) {
2564 /* Allocate buffer for command iocb */
0bd4ca25 2565 iocb = lpfc_sli_get_iocbq(phba);
dea3101e 2566 if (iocb == NULL) {
2567 pring->missbufcnt = cnt;
2568 return cnt;
2569 }
dea3101e 2570 icmd = &iocb->iocb;
2571
2572 /* 2 buffers can be posted per command */
2573 /* Allocate buffer to post */
2574 mp1 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2575 if (mp1)
98c9ea5c
JS
2576 mp1->virt = lpfc_mbuf_alloc(phba, MEM_PRI, &mp1->phys);
2577 if (!mp1 || !mp1->virt) {
c9475cb0 2578 kfree(mp1);
604a3e30 2579 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2580 pring->missbufcnt = cnt;
2581 return cnt;
2582 }
2583
2584 INIT_LIST_HEAD(&mp1->list);
2585 /* Allocate buffer to post */
2586 if (cnt > 1) {
2587 mp2 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2588 if (mp2)
2589 mp2->virt = lpfc_mbuf_alloc(phba, MEM_PRI,
2590 &mp2->phys);
98c9ea5c 2591 if (!mp2 || !mp2->virt) {
c9475cb0 2592 kfree(mp2);
dea3101e 2593 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2594 kfree(mp1);
604a3e30 2595 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2596 pring->missbufcnt = cnt;
2597 return cnt;
2598 }
2599
2600 INIT_LIST_HEAD(&mp2->list);
2601 } else {
2602 mp2 = NULL;
2603 }
2604
2605 icmd->un.cont64[0].addrHigh = putPaddrHigh(mp1->phys);
2606 icmd->un.cont64[0].addrLow = putPaddrLow(mp1->phys);
2607 icmd->un.cont64[0].tus.f.bdeSize = FCELSSIZE;
2608 icmd->ulpBdeCount = 1;
2609 cnt--;
2610 if (mp2) {
2611 icmd->un.cont64[1].addrHigh = putPaddrHigh(mp2->phys);
2612 icmd->un.cont64[1].addrLow = putPaddrLow(mp2->phys);
2613 icmd->un.cont64[1].tus.f.bdeSize = FCELSSIZE;
2614 cnt--;
2615 icmd->ulpBdeCount = 2;
2616 }
2617
2618 icmd->ulpCommand = CMD_QUE_RING_BUF64_CN;
2619 icmd->ulpLe = 1;
2620
3772a991
JS
2621 if (lpfc_sli_issue_iocb(phba, pring->ringno, iocb, 0) ==
2622 IOCB_ERROR) {
dea3101e 2623 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2624 kfree(mp1);
2625 cnt++;
2626 if (mp2) {
2627 lpfc_mbuf_free(phba, mp2->virt, mp2->phys);
2628 kfree(mp2);
2629 cnt++;
2630 }
604a3e30 2631 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2632 pring->missbufcnt = cnt;
dea3101e 2633 return cnt;
2634 }
dea3101e 2635 lpfc_sli_ringpostbuf_put(phba, pring, mp1);
92d7f7b0 2636 if (mp2)
dea3101e 2637 lpfc_sli_ringpostbuf_put(phba, pring, mp2);
dea3101e 2638 }
2639 pring->missbufcnt = 0;
2640 return 0;
2641}
2642
e59058c4 2643/**
3621a710 2644 * lpfc_post_rcv_buf - Post the initial receive IOCB buffers to ELS ring
e59058c4
JS
2645 * @phba: pointer to lpfc hba data structure.
2646 *
2647 * This routine posts initial receive IOCB buffers to the ELS ring. The
2648 * current number of initial IOCB buffers specified by LPFC_BUF_RING0 is
895427bd 2649 * set to 64 IOCBs. SLI3 only.
e59058c4
JS
2650 *
2651 * Return codes
2652 * 0 - success (currently always success)
2653 **/
dea3101e 2654static int
2e0fef85 2655lpfc_post_rcv_buf(struct lpfc_hba *phba)
dea3101e 2656{
2657 struct lpfc_sli *psli = &phba->sli;
2658
2659 /* Ring 0, ELS / CT buffers */
895427bd 2660 lpfc_post_buffer(phba, &psli->sli3_ring[LPFC_ELS_RING], LPFC_BUF_RING0);
dea3101e 2661 /* Ring 2 - FCP no buffers needed */
2662
2663 return 0;
2664}
2665
2666#define S(N,V) (((V)<<(N))|((V)>>(32-(N))))
2667
e59058c4 2668/**
3621a710 2669 * lpfc_sha_init - Set up initial array of hash table entries
e59058c4
JS
2670 * @HashResultPointer: pointer to an array as hash table.
2671 *
2672 * This routine sets up the initial values to the array of hash table entries
2673 * for the LC HBAs.
2674 **/
dea3101e 2675static void
2676lpfc_sha_init(uint32_t * HashResultPointer)
2677{
2678 HashResultPointer[0] = 0x67452301;
2679 HashResultPointer[1] = 0xEFCDAB89;
2680 HashResultPointer[2] = 0x98BADCFE;
2681 HashResultPointer[3] = 0x10325476;
2682 HashResultPointer[4] = 0xC3D2E1F0;
2683}
2684
e59058c4 2685/**
3621a710 2686 * lpfc_sha_iterate - Iterate initial hash table with the working hash table
e59058c4
JS
2687 * @HashResultPointer: pointer to an initial/result hash table.
2688 * @HashWorkingPointer: pointer to an working hash table.
2689 *
2690 * This routine iterates an initial hash table pointed by @HashResultPointer
2691 * with the values from the working hash table pointeed by @HashWorkingPointer.
2692 * The results are putting back to the initial hash table, returned through
2693 * the @HashResultPointer as the result hash table.
2694 **/
dea3101e 2695static void
2696lpfc_sha_iterate(uint32_t * HashResultPointer, uint32_t * HashWorkingPointer)
2697{
2698 int t;
2699 uint32_t TEMP;
2700 uint32_t A, B, C, D, E;
2701 t = 16;
2702 do {
2703 HashWorkingPointer[t] =
2704 S(1,
2705 HashWorkingPointer[t - 3] ^ HashWorkingPointer[t -
2706 8] ^
2707 HashWorkingPointer[t - 14] ^ HashWorkingPointer[t - 16]);
2708 } while (++t <= 79);
2709 t = 0;
2710 A = HashResultPointer[0];
2711 B = HashResultPointer[1];
2712 C = HashResultPointer[2];
2713 D = HashResultPointer[3];
2714 E = HashResultPointer[4];
2715
2716 do {
2717 if (t < 20) {
2718 TEMP = ((B & C) | ((~B) & D)) + 0x5A827999;
2719 } else if (t < 40) {
2720 TEMP = (B ^ C ^ D) + 0x6ED9EBA1;
2721 } else if (t < 60) {
2722 TEMP = ((B & C) | (B & D) | (C & D)) + 0x8F1BBCDC;
2723 } else {
2724 TEMP = (B ^ C ^ D) + 0xCA62C1D6;
2725 }
2726 TEMP += S(5, A) + E + HashWorkingPointer[t];
2727 E = D;
2728 D = C;
2729 C = S(30, B);
2730 B = A;
2731 A = TEMP;
2732 } while (++t <= 79);
2733
2734 HashResultPointer[0] += A;
2735 HashResultPointer[1] += B;
2736 HashResultPointer[2] += C;
2737 HashResultPointer[3] += D;
2738 HashResultPointer[4] += E;
2739
2740}
2741
e59058c4 2742/**
3621a710 2743 * lpfc_challenge_key - Create challenge key based on WWPN of the HBA
e59058c4
JS
2744 * @RandomChallenge: pointer to the entry of host challenge random number array.
2745 * @HashWorking: pointer to the entry of the working hash array.
2746 *
2747 * This routine calculates the working hash array referred by @HashWorking
2748 * from the challenge random numbers associated with the host, referred by
2749 * @RandomChallenge. The result is put into the entry of the working hash
2750 * array and returned by reference through @HashWorking.
2751 **/
dea3101e 2752static void
2753lpfc_challenge_key(uint32_t * RandomChallenge, uint32_t * HashWorking)
2754{
2755 *HashWorking = (*RandomChallenge ^ *HashWorking);
2756}
2757
e59058c4 2758/**
3621a710 2759 * lpfc_hba_init - Perform special handling for LC HBA initialization
e59058c4
JS
2760 * @phba: pointer to lpfc hba data structure.
2761 * @hbainit: pointer to an array of unsigned 32-bit integers.
2762 *
2763 * This routine performs the special handling for LC HBA initialization.
2764 **/
dea3101e 2765void
2766lpfc_hba_init(struct lpfc_hba *phba, uint32_t *hbainit)
2767{
2768 int t;
2769 uint32_t *HashWorking;
2e0fef85 2770 uint32_t *pwwnn = (uint32_t *) phba->wwnn;
dea3101e 2771
bbfbbbc1 2772 HashWorking = kcalloc(80, sizeof(uint32_t), GFP_KERNEL);
dea3101e 2773 if (!HashWorking)
2774 return;
2775
dea3101e 2776 HashWorking[0] = HashWorking[78] = *pwwnn++;
2777 HashWorking[1] = HashWorking[79] = *pwwnn;
2778
2779 for (t = 0; t < 7; t++)
2780 lpfc_challenge_key(phba->RandomData + t, HashWorking + t);
2781
2782 lpfc_sha_init(hbainit);
2783 lpfc_sha_iterate(hbainit, HashWorking);
2784 kfree(HashWorking);
2785}
2786
e59058c4 2787/**
3621a710 2788 * lpfc_cleanup - Performs vport cleanups before deleting a vport
e59058c4
JS
2789 * @vport: pointer to a virtual N_Port data structure.
2790 *
2791 * This routine performs the necessary cleanups before deleting the @vport.
2792 * It invokes the discovery state machine to perform necessary state
2793 * transitions and to release the ndlps associated with the @vport. Note,
2794 * the physical port is treated as @vport 0.
2795 **/
87af33fe 2796void
2e0fef85 2797lpfc_cleanup(struct lpfc_vport *vport)
dea3101e 2798{
87af33fe 2799 struct lpfc_hba *phba = vport->phba;
dea3101e 2800 struct lpfc_nodelist *ndlp, *next_ndlp;
a8adb832 2801 int i = 0;
dea3101e 2802
87af33fe
JS
2803 if (phba->link_state > LPFC_LINK_DOWN)
2804 lpfc_port_link_failure(vport);
2805
2806 list_for_each_entry_safe(ndlp, next_ndlp, &vport->fc_nodes, nlp_listp) {
e47c9093
JS
2807 if (!NLP_CHK_NODE_ACT(ndlp)) {
2808 ndlp = lpfc_enable_node(vport, ndlp,
2809 NLP_STE_UNUSED_NODE);
2810 if (!ndlp)
2811 continue;
2812 spin_lock_irq(&phba->ndlp_lock);
2813 NLP_SET_FREE_REQ(ndlp);
2814 spin_unlock_irq(&phba->ndlp_lock);
2815 /* Trigger the release of the ndlp memory */
2816 lpfc_nlp_put(ndlp);
2817 continue;
2818 }
2819 spin_lock_irq(&phba->ndlp_lock);
2820 if (NLP_CHK_FREE_REQ(ndlp)) {
2821 /* The ndlp should not be in memory free mode already */
2822 spin_unlock_irq(&phba->ndlp_lock);
2823 continue;
2824 } else
2825 /* Indicate request for freeing ndlp memory */
2826 NLP_SET_FREE_REQ(ndlp);
2827 spin_unlock_irq(&phba->ndlp_lock);
2828
58da1ffb
JS
2829 if (vport->port_type != LPFC_PHYSICAL_PORT &&
2830 ndlp->nlp_DID == Fabric_DID) {
2831 /* Just free up ndlp with Fabric_DID for vports */
2832 lpfc_nlp_put(ndlp);
2833 continue;
2834 }
2835
eff4a01b
JS
2836 /* take care of nodes in unused state before the state
2837 * machine taking action.
2838 */
2839 if (ndlp->nlp_state == NLP_STE_UNUSED_NODE) {
2840 lpfc_nlp_put(ndlp);
2841 continue;
2842 }
2843
87af33fe
JS
2844 if (ndlp->nlp_type & NLP_FABRIC)
2845 lpfc_disc_state_machine(vport, ndlp, NULL,
2846 NLP_EVT_DEVICE_RECOVERY);
e47c9093 2847
87af33fe
JS
2848 lpfc_disc_state_machine(vport, ndlp, NULL,
2849 NLP_EVT_DEVICE_RM);
2850 }
2851
a8adb832
JS
2852 /* At this point, ALL ndlp's should be gone
2853 * because of the previous NLP_EVT_DEVICE_RM.
2854 * Lets wait for this to happen, if needed.
2855 */
87af33fe 2856 while (!list_empty(&vport->fc_nodes)) {
a8adb832 2857 if (i++ > 3000) {
87af33fe 2858 lpfc_printf_vlog(vport, KERN_ERR, LOG_DISCOVERY,
a8adb832 2859 "0233 Nodelist not empty\n");
e47c9093
JS
2860 list_for_each_entry_safe(ndlp, next_ndlp,
2861 &vport->fc_nodes, nlp_listp) {
2862 lpfc_printf_vlog(ndlp->vport, KERN_ERR,
2863 LOG_NODE,
d7c255b2 2864 "0282 did:x%x ndlp:x%p "
e47c9093
JS
2865 "usgmap:x%x refcnt:%d\n",
2866 ndlp->nlp_DID, (void *)ndlp,
2867 ndlp->nlp_usg_map,
2c935bc5 2868 kref_read(&ndlp->kref));
e47c9093 2869 }
a8adb832 2870 break;
87af33fe 2871 }
a8adb832
JS
2872
2873 /* Wait for any activity on ndlps to settle */
2874 msleep(10);
87af33fe 2875 }
1151e3ec 2876 lpfc_cleanup_vports_rrqs(vport, NULL);
dea3101e 2877}
2878
e59058c4 2879/**
3621a710 2880 * lpfc_stop_vport_timers - Stop all the timers associated with a vport
e59058c4
JS
2881 * @vport: pointer to a virtual N_Port data structure.
2882 *
2883 * This routine stops all the timers associated with a @vport. This function
2884 * is invoked before disabling or deleting a @vport. Note that the physical
2885 * port is treated as @vport 0.
2886 **/
92d7f7b0
JS
2887void
2888lpfc_stop_vport_timers(struct lpfc_vport *vport)
dea3101e 2889{
92d7f7b0 2890 del_timer_sync(&vport->els_tmofunc);
92494144 2891 del_timer_sync(&vport->delayed_disc_tmo);
92d7f7b0
JS
2892 lpfc_can_disctmo(vport);
2893 return;
dea3101e 2894}
2895
ecfd03c6
JS
2896/**
2897 * __lpfc_sli4_stop_fcf_redisc_wait_timer - Stop FCF rediscovery wait timer
2898 * @phba: pointer to lpfc hba data structure.
2899 *
2900 * This routine stops the SLI4 FCF rediscover wait timer if it's on. The
2901 * caller of this routine should already hold the host lock.
2902 **/
2903void
2904__lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2905{
5ac6b303
JS
2906 /* Clear pending FCF rediscovery wait flag */
2907 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
2908
ecfd03c6
JS
2909 /* Now, try to stop the timer */
2910 del_timer(&phba->fcf.redisc_wait);
2911}
2912
2913/**
2914 * lpfc_sli4_stop_fcf_redisc_wait_timer - Stop FCF rediscovery wait timer
2915 * @phba: pointer to lpfc hba data structure.
2916 *
2917 * This routine stops the SLI4 FCF rediscover wait timer if it's on. It
2918 * checks whether the FCF rediscovery wait timer is pending with the host
2919 * lock held before proceeding with disabling the timer and clearing the
2920 * wait timer pendig flag.
2921 **/
2922void
2923lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2924{
2925 spin_lock_irq(&phba->hbalock);
2926 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
2927 /* FCF rediscovery timer already fired or stopped */
2928 spin_unlock_irq(&phba->hbalock);
2929 return;
2930 }
2931 __lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
5ac6b303
JS
2932 /* Clear failover in progress flags */
2933 phba->fcf.fcf_flag &= ~(FCF_DEAD_DISC | FCF_ACVL_DISC);
ecfd03c6
JS
2934 spin_unlock_irq(&phba->hbalock);
2935}
2936
e59058c4 2937/**
3772a991 2938 * lpfc_stop_hba_timers - Stop all the timers associated with an HBA
e59058c4
JS
2939 * @phba: pointer to lpfc hba data structure.
2940 *
2941 * This routine stops all the timers associated with a HBA. This function is
2942 * invoked before either putting a HBA offline or unloading the driver.
2943 **/
3772a991
JS
2944void
2945lpfc_stop_hba_timers(struct lpfc_hba *phba)
dea3101e 2946{
cdb42bec
JS
2947 if (phba->pport)
2948 lpfc_stop_vport_timers(phba->pport);
32517fc0 2949 cancel_delayed_work_sync(&phba->eq_delay_work);
2e0fef85 2950 del_timer_sync(&phba->sli.mbox_tmo);
92d7f7b0 2951 del_timer_sync(&phba->fabric_block_timer);
9399627f 2952 del_timer_sync(&phba->eratt_poll);
3772a991 2953 del_timer_sync(&phba->hb_tmofunc);
1151e3ec
JS
2954 if (phba->sli_rev == LPFC_SLI_REV4) {
2955 del_timer_sync(&phba->rrq_tmr);
2956 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
2957 }
3772a991
JS
2958 phba->hb_outstanding = 0;
2959
2960 switch (phba->pci_dev_grp) {
2961 case LPFC_PCI_DEV_LP:
2962 /* Stop any LightPulse device specific driver timers */
2963 del_timer_sync(&phba->fcp_poll_timer);
2964 break;
2965 case LPFC_PCI_DEV_OC:
2966 /* Stop any OneConnect device sepcific driver timers */
ecfd03c6 2967 lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
3772a991
JS
2968 break;
2969 default:
2970 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
2971 "0297 Invalid device group (x%x)\n",
2972 phba->pci_dev_grp);
2973 break;
2974 }
2e0fef85 2975 return;
dea3101e 2976}
2977
e59058c4 2978/**
3621a710 2979 * lpfc_block_mgmt_io - Mark a HBA's management interface as blocked
e59058c4
JS
2980 * @phba: pointer to lpfc hba data structure.
2981 *
2982 * This routine marks a HBA's management interface as blocked. Once the HBA's
2983 * management interface is marked as blocked, all the user space access to
2984 * the HBA, whether they are from sysfs interface or libdfc interface will
2985 * all be blocked. The HBA is set to block the management interface when the
2986 * driver prepares the HBA interface for online or offline.
2987 **/
a6ababd2 2988static void
618a5230 2989lpfc_block_mgmt_io(struct lpfc_hba *phba, int mbx_action)
a6ababd2
AB
2990{
2991 unsigned long iflag;
6e7288d9
JS
2992 uint8_t actcmd = MBX_HEARTBEAT;
2993 unsigned long timeout;
2994
a6ababd2
AB
2995 spin_lock_irqsave(&phba->hbalock, iflag);
2996 phba->sli.sli_flag |= LPFC_BLOCK_MGMT_IO;
618a5230
JS
2997 spin_unlock_irqrestore(&phba->hbalock, iflag);
2998 if (mbx_action == LPFC_MBX_NO_WAIT)
2999 return;
3000 timeout = msecs_to_jiffies(LPFC_MBOX_TMO * 1000) + jiffies;
3001 spin_lock_irqsave(&phba->hbalock, iflag);
a183a15f 3002 if (phba->sli.mbox_active) {
6e7288d9 3003 actcmd = phba->sli.mbox_active->u.mb.mbxCommand;
a183a15f
JS
3004 /* Determine how long we might wait for the active mailbox
3005 * command to be gracefully completed by firmware.
3006 */
3007 timeout = msecs_to_jiffies(lpfc_mbox_tmo_val(phba,
3008 phba->sli.mbox_active) * 1000) + jiffies;
3009 }
a6ababd2 3010 spin_unlock_irqrestore(&phba->hbalock, iflag);
a183a15f 3011
6e7288d9
JS
3012 /* Wait for the outstnading mailbox command to complete */
3013 while (phba->sli.mbox_active) {
3014 /* Check active mailbox complete status every 2ms */
3015 msleep(2);
3016 if (time_after(jiffies, timeout)) {
3017 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3018 "2813 Mgmt IO is Blocked %x "
3019 "- mbox cmd %x still active\n",
3020 phba->sli.sli_flag, actcmd);
3021 break;
3022 }
3023 }
a6ababd2
AB
3024}
3025
6b5151fd
JS
3026/**
3027 * lpfc_sli4_node_prep - Assign RPIs for active nodes.
3028 * @phba: pointer to lpfc hba data structure.
3029 *
3030 * Allocate RPIs for all active remote nodes. This is needed whenever
3031 * an SLI4 adapter is reset and the driver is not unloading. Its purpose
3032 * is to fixup the temporary rpi assignments.
3033 **/
3034void
3035lpfc_sli4_node_prep(struct lpfc_hba *phba)
3036{
3037 struct lpfc_nodelist *ndlp, *next_ndlp;
3038 struct lpfc_vport **vports;
9d3d340d
JS
3039 int i, rpi;
3040 unsigned long flags;
6b5151fd
JS
3041
3042 if (phba->sli_rev != LPFC_SLI_REV4)
3043 return;
3044
3045 vports = lpfc_create_vport_work_array(phba);
9d3d340d
JS
3046 if (vports == NULL)
3047 return;
6b5151fd 3048
9d3d340d
JS
3049 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
3050 if (vports[i]->load_flag & FC_UNLOADING)
3051 continue;
3052
3053 list_for_each_entry_safe(ndlp, next_ndlp,
3054 &vports[i]->fc_nodes,
3055 nlp_listp) {
3056 if (!NLP_CHK_NODE_ACT(ndlp))
3057 continue;
3058 rpi = lpfc_sli4_alloc_rpi(phba);
3059 if (rpi == LPFC_RPI_ALLOC_ERROR) {
3060 spin_lock_irqsave(&phba->ndlp_lock, flags);
3061 NLP_CLR_NODE_ACT(ndlp);
3062 spin_unlock_irqrestore(&phba->ndlp_lock, flags);
3063 continue;
6b5151fd 3064 }
9d3d340d
JS
3065 ndlp->nlp_rpi = rpi;
3066 lpfc_printf_vlog(ndlp->vport, KERN_INFO, LOG_NODE,
3067 "0009 rpi:%x DID:%x "
3068 "flg:%x map:%x %p\n", ndlp->nlp_rpi,
3069 ndlp->nlp_DID, ndlp->nlp_flag,
3070 ndlp->nlp_usg_map, ndlp);
6b5151fd
JS
3071 }
3072 }
3073 lpfc_destroy_vport_work_array(phba, vports);
3074}
3075
c490850a
JS
3076/**
3077 * lpfc_create_expedite_pool - create expedite pool
3078 * @phba: pointer to lpfc hba data structure.
3079 *
3080 * This routine moves a batch of XRIs from lpfc_io_buf_list_put of HWQ 0
3081 * to expedite pool. Mark them as expedite.
3082 **/
3083void lpfc_create_expedite_pool(struct lpfc_hba *phba)
3084{
3085 struct lpfc_sli4_hdw_queue *qp;
3086 struct lpfc_io_buf *lpfc_ncmd;
3087 struct lpfc_io_buf *lpfc_ncmd_next;
3088 struct lpfc_epd_pool *epd_pool;
3089 unsigned long iflag;
3090
3091 epd_pool = &phba->epd_pool;
3092 qp = &phba->sli4_hba.hdwq[0];
3093
3094 spin_lock_init(&epd_pool->lock);
3095 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3096 spin_lock(&epd_pool->lock);
3097 INIT_LIST_HEAD(&epd_pool->list);
3098 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3099 &qp->lpfc_io_buf_list_put, list) {
3100 list_move_tail(&lpfc_ncmd->list, &epd_pool->list);
3101 lpfc_ncmd->expedite = true;
3102 qp->put_io_bufs--;
3103 epd_pool->count++;
3104 if (epd_pool->count >= XRI_BATCH)
3105 break;
3106 }
3107 spin_unlock(&epd_pool->lock);
3108 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3109}
3110
3111/**
3112 * lpfc_destroy_expedite_pool - destroy expedite pool
3113 * @phba: pointer to lpfc hba data structure.
3114 *
3115 * This routine returns XRIs from expedite pool to lpfc_io_buf_list_put
3116 * of HWQ 0. Clear the mark.
3117 **/
3118void lpfc_destroy_expedite_pool(struct lpfc_hba *phba)
3119{
3120 struct lpfc_sli4_hdw_queue *qp;
3121 struct lpfc_io_buf *lpfc_ncmd;
3122 struct lpfc_io_buf *lpfc_ncmd_next;
3123 struct lpfc_epd_pool *epd_pool;
3124 unsigned long iflag;
3125
3126 epd_pool = &phba->epd_pool;
3127 qp = &phba->sli4_hba.hdwq[0];
3128
3129 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3130 spin_lock(&epd_pool->lock);
3131 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3132 &epd_pool->list, list) {
3133 list_move_tail(&lpfc_ncmd->list,
3134 &qp->lpfc_io_buf_list_put);
3135 lpfc_ncmd->flags = false;
3136 qp->put_io_bufs++;
3137 epd_pool->count--;
3138 }
3139 spin_unlock(&epd_pool->lock);
3140 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3141}
3142
3143/**
3144 * lpfc_create_multixri_pools - create multi-XRI pools
3145 * @phba: pointer to lpfc hba data structure.
3146 *
3147 * This routine initialize public, private per HWQ. Then, move XRIs from
3148 * lpfc_io_buf_list_put to public pool. High and low watermark are also
3149 * Initialized.
3150 **/
3151void lpfc_create_multixri_pools(struct lpfc_hba *phba)
3152{
3153 u32 i, j;
3154 u32 hwq_count;
3155 u32 count_per_hwq;
3156 struct lpfc_io_buf *lpfc_ncmd;
3157 struct lpfc_io_buf *lpfc_ncmd_next;
3158 unsigned long iflag;
3159 struct lpfc_sli4_hdw_queue *qp;
3160 struct lpfc_multixri_pool *multixri_pool;
3161 struct lpfc_pbl_pool *pbl_pool;
3162 struct lpfc_pvt_pool *pvt_pool;
3163
3164 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3165 "1234 num_hdw_queue=%d num_present_cpu=%d common_xri_cnt=%d\n",
3166 phba->cfg_hdw_queue, phba->sli4_hba.num_present_cpu,
3167 phba->sli4_hba.io_xri_cnt);
3168
3169 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3170 lpfc_create_expedite_pool(phba);
3171
3172 hwq_count = phba->cfg_hdw_queue;
3173 count_per_hwq = phba->sli4_hba.io_xri_cnt / hwq_count;
3174
3175 for (i = 0; i < hwq_count; i++) {
3176 multixri_pool = kzalloc(sizeof(*multixri_pool), GFP_KERNEL);
3177
3178 if (!multixri_pool) {
3179 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3180 "1238 Failed to allocate memory for "
3181 "multixri_pool\n");
3182
3183 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3184 lpfc_destroy_expedite_pool(phba);
3185
3186 j = 0;
3187 while (j < i) {
3188 qp = &phba->sli4_hba.hdwq[j];
3189 kfree(qp->p_multixri_pool);
3190 j++;
3191 }
3192 phba->cfg_xri_rebalancing = 0;
3193 return;
3194 }
3195
3196 qp = &phba->sli4_hba.hdwq[i];
3197 qp->p_multixri_pool = multixri_pool;
3198
3199 multixri_pool->xri_limit = count_per_hwq;
3200 multixri_pool->rrb_next_hwqid = i;
3201
3202 /* Deal with public free xri pool */
3203 pbl_pool = &multixri_pool->pbl_pool;
3204 spin_lock_init(&pbl_pool->lock);
3205 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3206 spin_lock(&pbl_pool->lock);
3207 INIT_LIST_HEAD(&pbl_pool->list);
3208 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3209 &qp->lpfc_io_buf_list_put, list) {
3210 list_move_tail(&lpfc_ncmd->list, &pbl_pool->list);
3211 qp->put_io_bufs--;
3212 pbl_pool->count++;
3213 }
3214 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3215 "1235 Moved %d buffers from PUT list over to pbl_pool[%d]\n",
3216 pbl_pool->count, i);
3217 spin_unlock(&pbl_pool->lock);
3218 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3219
3220 /* Deal with private free xri pool */
3221 pvt_pool = &multixri_pool->pvt_pool;
3222 pvt_pool->high_watermark = multixri_pool->xri_limit / 2;
3223 pvt_pool->low_watermark = XRI_BATCH;
3224 spin_lock_init(&pvt_pool->lock);
3225 spin_lock_irqsave(&pvt_pool->lock, iflag);
3226 INIT_LIST_HEAD(&pvt_pool->list);
3227 pvt_pool->count = 0;
3228 spin_unlock_irqrestore(&pvt_pool->lock, iflag);
3229 }
3230}
3231
3232/**
3233 * lpfc_destroy_multixri_pools - destroy multi-XRI pools
3234 * @phba: pointer to lpfc hba data structure.
3235 *
3236 * This routine returns XRIs from public/private to lpfc_io_buf_list_put.
3237 **/
3238void lpfc_destroy_multixri_pools(struct lpfc_hba *phba)
3239{
3240 u32 i;
3241 u32 hwq_count;
3242 struct lpfc_io_buf *lpfc_ncmd;
3243 struct lpfc_io_buf *lpfc_ncmd_next;
3244 unsigned long iflag;
3245 struct lpfc_sli4_hdw_queue *qp;
3246 struct lpfc_multixri_pool *multixri_pool;
3247 struct lpfc_pbl_pool *pbl_pool;
3248 struct lpfc_pvt_pool *pvt_pool;
3249
3250 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3251 lpfc_destroy_expedite_pool(phba);
3252
3253 hwq_count = phba->cfg_hdw_queue;
3254
3255 for (i = 0; i < hwq_count; i++) {
3256 qp = &phba->sli4_hba.hdwq[i];
3257 multixri_pool = qp->p_multixri_pool;
3258 if (!multixri_pool)
3259 continue;
3260
3261 qp->p_multixri_pool = NULL;
3262
3263 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3264
3265 /* Deal with public free xri pool */
3266 pbl_pool = &multixri_pool->pbl_pool;
3267 spin_lock(&pbl_pool->lock);
3268
3269 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3270 "1236 Moving %d buffers from pbl_pool[%d] TO PUT list\n",
3271 pbl_pool->count, i);
3272
3273 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3274 &pbl_pool->list, list) {
3275 list_move_tail(&lpfc_ncmd->list,
3276 &qp->lpfc_io_buf_list_put);
3277 qp->put_io_bufs++;
3278 pbl_pool->count--;
3279 }
3280
3281 INIT_LIST_HEAD(&pbl_pool->list);
3282 pbl_pool->count = 0;
3283
3284 spin_unlock(&pbl_pool->lock);
3285
3286 /* Deal with private free xri pool */
3287 pvt_pool = &multixri_pool->pvt_pool;
3288 spin_lock(&pvt_pool->lock);
3289
3290 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3291 "1237 Moving %d buffers from pvt_pool[%d] TO PUT list\n",
3292 pvt_pool->count, i);
3293
3294 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3295 &pvt_pool->list, list) {
3296 list_move_tail(&lpfc_ncmd->list,
3297 &qp->lpfc_io_buf_list_put);
3298 qp->put_io_bufs++;
3299 pvt_pool->count--;
3300 }
3301
3302 INIT_LIST_HEAD(&pvt_pool->list);
3303 pvt_pool->count = 0;
3304
3305 spin_unlock(&pvt_pool->lock);
3306 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3307
3308 kfree(multixri_pool);
3309 }
3310}
3311
e59058c4 3312/**
3621a710 3313 * lpfc_online - Initialize and bring a HBA online
e59058c4
JS
3314 * @phba: pointer to lpfc hba data structure.
3315 *
3316 * This routine initializes the HBA and brings a HBA online. During this
3317 * process, the management interface is blocked to prevent user space access
3318 * to the HBA interfering with the driver initialization.
3319 *
3320 * Return codes
3321 * 0 - successful
3322 * 1 - failed
3323 **/
dea3101e 3324int
2e0fef85 3325lpfc_online(struct lpfc_hba *phba)
dea3101e 3326{
372bd282 3327 struct lpfc_vport *vport;
549e55cd 3328 struct lpfc_vport **vports;
a145fda3 3329 int i, error = 0;
16a3a208 3330 bool vpis_cleared = false;
2e0fef85 3331
dea3101e 3332 if (!phba)
3333 return 0;
372bd282 3334 vport = phba->pport;
dea3101e 3335
2e0fef85 3336 if (!(vport->fc_flag & FC_OFFLINE_MODE))
dea3101e 3337 return 0;
3338
ed957684 3339 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
e8b62011 3340 "0458 Bring Adapter online\n");
dea3101e 3341
618a5230 3342 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
46fa311e 3343
da0436e9
JS
3344 if (phba->sli_rev == LPFC_SLI_REV4) {
3345 if (lpfc_sli4_hba_setup(phba)) { /* Initialize SLI4 HBA */
3346 lpfc_unblock_mgmt_io(phba);
3347 return 1;
3348 }
16a3a208
JS
3349 spin_lock_irq(&phba->hbalock);
3350 if (!phba->sli4_hba.max_cfg_param.vpi_used)
3351 vpis_cleared = true;
3352 spin_unlock_irq(&phba->hbalock);
a145fda3
DK
3353
3354 /* Reestablish the local initiator port.
3355 * The offline process destroyed the previous lport.
3356 */
3357 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME &&
3358 !phba->nvmet_support) {
3359 error = lpfc_nvme_create_localport(phba->pport);
3360 if (error)
3361 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
3362 "6132 NVME restore reg failed "
3363 "on nvmei error x%x\n", error);
3364 }
da0436e9 3365 } else {
895427bd 3366 lpfc_sli_queue_init(phba);
da0436e9
JS
3367 if (lpfc_sli_hba_setup(phba)) { /* Initialize SLI2/SLI3 HBA */
3368 lpfc_unblock_mgmt_io(phba);
3369 return 1;
3370 }
46fa311e 3371 }
dea3101e 3372
549e55cd 3373 vports = lpfc_create_vport_work_array(phba);
aeb6641f 3374 if (vports != NULL) {
da0436e9 3375 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
549e55cd
JS
3376 struct Scsi_Host *shost;
3377 shost = lpfc_shost_from_vport(vports[i]);
3378 spin_lock_irq(shost->host_lock);
3379 vports[i]->fc_flag &= ~FC_OFFLINE_MODE;
3380 if (phba->sli3_options & LPFC_SLI3_NPIV_ENABLED)
3381 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
16a3a208 3382 if (phba->sli_rev == LPFC_SLI_REV4) {
1c6834a7 3383 vports[i]->fc_flag |= FC_VPORT_NEEDS_INIT_VPI;
16a3a208
JS
3384 if ((vpis_cleared) &&
3385 (vports[i]->port_type !=
3386 LPFC_PHYSICAL_PORT))
3387 vports[i]->vpi = 0;
3388 }
549e55cd
JS
3389 spin_unlock_irq(shost->host_lock);
3390 }
aeb6641f
AB
3391 }
3392 lpfc_destroy_vport_work_array(phba, vports);
dea3101e 3393
c490850a
JS
3394 if (phba->cfg_xri_rebalancing)
3395 lpfc_create_multixri_pools(phba);
3396
46fa311e 3397 lpfc_unblock_mgmt_io(phba);
dea3101e 3398 return 0;
3399}
3400
e59058c4 3401/**
3621a710 3402 * lpfc_unblock_mgmt_io - Mark a HBA's management interface to be not blocked
e59058c4
JS
3403 * @phba: pointer to lpfc hba data structure.
3404 *
3405 * This routine marks a HBA's management interface as not blocked. Once the
3406 * HBA's management interface is marked as not blocked, all the user space
3407 * access to the HBA, whether they are from sysfs interface or libdfc
3408 * interface will be allowed. The HBA is set to block the management interface
3409 * when the driver prepares the HBA interface for online or offline and then
3410 * set to unblock the management interface afterwards.
3411 **/
46fa311e
JS
3412void
3413lpfc_unblock_mgmt_io(struct lpfc_hba * phba)
3414{
3415 unsigned long iflag;
3416
2e0fef85
JS
3417 spin_lock_irqsave(&phba->hbalock, iflag);
3418 phba->sli.sli_flag &= ~LPFC_BLOCK_MGMT_IO;
3419 spin_unlock_irqrestore(&phba->hbalock, iflag);
46fa311e
JS
3420}
3421
e59058c4 3422/**
3621a710 3423 * lpfc_offline_prep - Prepare a HBA to be brought offline
e59058c4
JS
3424 * @phba: pointer to lpfc hba data structure.
3425 *
3426 * This routine is invoked to prepare a HBA to be brought offline. It performs
3427 * unregistration login to all the nodes on all vports and flushes the mailbox
3428 * queue to make it ready to be brought offline.
3429 **/
46fa311e 3430void
618a5230 3431lpfc_offline_prep(struct lpfc_hba *phba, int mbx_action)
46fa311e 3432{
2e0fef85 3433 struct lpfc_vport *vport = phba->pport;
46fa311e 3434 struct lpfc_nodelist *ndlp, *next_ndlp;
87af33fe 3435 struct lpfc_vport **vports;
72100cc4 3436 struct Scsi_Host *shost;
87af33fe 3437 int i;
dea3101e 3438
2e0fef85 3439 if (vport->fc_flag & FC_OFFLINE_MODE)
46fa311e 3440 return;
dea3101e 3441
618a5230 3442 lpfc_block_mgmt_io(phba, mbx_action);
dea3101e 3443
3444 lpfc_linkdown(phba);
3445
87af33fe
JS
3446 /* Issue an unreg_login to all nodes on all vports */
3447 vports = lpfc_create_vport_work_array(phba);
3448 if (vports != NULL) {
da0436e9 3449 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
a8adb832
JS
3450 if (vports[i]->load_flag & FC_UNLOADING)
3451 continue;
72100cc4
JS
3452 shost = lpfc_shost_from_vport(vports[i]);
3453 spin_lock_irq(shost->host_lock);
c868595d 3454 vports[i]->vpi_state &= ~LPFC_VPI_REGISTERED;
695a814e
JS
3455 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
3456 vports[i]->fc_flag &= ~FC_VFI_REGISTERED;
72100cc4 3457 spin_unlock_irq(shost->host_lock);
695a814e 3458
87af33fe
JS
3459 shost = lpfc_shost_from_vport(vports[i]);
3460 list_for_each_entry_safe(ndlp, next_ndlp,
3461 &vports[i]->fc_nodes,
3462 nlp_listp) {
e47c9093
JS
3463 if (!NLP_CHK_NODE_ACT(ndlp))
3464 continue;
87af33fe
JS
3465 if (ndlp->nlp_state == NLP_STE_UNUSED_NODE)
3466 continue;
3467 if (ndlp->nlp_type & NLP_FABRIC) {
3468 lpfc_disc_state_machine(vports[i], ndlp,
3469 NULL, NLP_EVT_DEVICE_RECOVERY);
3470 lpfc_disc_state_machine(vports[i], ndlp,
3471 NULL, NLP_EVT_DEVICE_RM);
3472 }
3473 spin_lock_irq(shost->host_lock);
3474 ndlp->nlp_flag &= ~NLP_NPR_ADISC;
401ee0c1 3475 spin_unlock_irq(shost->host_lock);
6b5151fd
JS
3476 /*
3477 * Whenever an SLI4 port goes offline, free the
401ee0c1
JS
3478 * RPI. Get a new RPI when the adapter port
3479 * comes back online.
6b5151fd 3480 */
be6bb941
JS
3481 if (phba->sli_rev == LPFC_SLI_REV4) {
3482 lpfc_printf_vlog(ndlp->vport,
3483 KERN_INFO, LOG_NODE,
3484 "0011 lpfc_offline: "
3485 "ndlp:x%p did %x "
3486 "usgmap:x%x rpi:%x\n",
3487 ndlp, ndlp->nlp_DID,
3488 ndlp->nlp_usg_map,
3489 ndlp->nlp_rpi);
3490
6b5151fd 3491 lpfc_sli4_free_rpi(phba, ndlp->nlp_rpi);
be6bb941 3492 }
87af33fe
JS
3493 lpfc_unreg_rpi(vports[i], ndlp);
3494 }
3495 }
3496 }
09372820 3497 lpfc_destroy_vport_work_array(phba, vports);
dea3101e 3498
618a5230 3499 lpfc_sli_mbox_sys_shutdown(phba, mbx_action);
f485c18d
DK
3500
3501 if (phba->wq)
3502 flush_workqueue(phba->wq);
46fa311e
JS
3503}
3504
e59058c4 3505/**
3621a710 3506 * lpfc_offline - Bring a HBA offline
e59058c4
JS
3507 * @phba: pointer to lpfc hba data structure.
3508 *
3509 * This routine actually brings a HBA offline. It stops all the timers
3510 * associated with the HBA, brings down the SLI layer, and eventually
3511 * marks the HBA as in offline state for the upper layer protocol.
3512 **/
46fa311e 3513void
2e0fef85 3514lpfc_offline(struct lpfc_hba *phba)
46fa311e 3515{
549e55cd
JS
3516 struct Scsi_Host *shost;
3517 struct lpfc_vport **vports;
3518 int i;
46fa311e 3519
549e55cd 3520 if (phba->pport->fc_flag & FC_OFFLINE_MODE)
46fa311e 3521 return;
688a8863 3522
da0436e9
JS
3523 /* stop port and all timers associated with this hba */
3524 lpfc_stop_port(phba);
4b40d02b
DK
3525
3526 /* Tear down the local and target port registrations. The
3527 * nvme transports need to cleanup.
3528 */
3529 lpfc_nvmet_destroy_targetport(phba);
3530 lpfc_nvme_destroy_localport(phba->pport);
3531
51ef4c26
JS
3532 vports = lpfc_create_vport_work_array(phba);
3533 if (vports != NULL)
da0436e9 3534 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
51ef4c26 3535 lpfc_stop_vport_timers(vports[i]);
09372820 3536 lpfc_destroy_vport_work_array(phba, vports);
92d7f7b0 3537 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
e8b62011 3538 "0460 Bring Adapter offline\n");
dea3101e 3539 /* Bring down the SLI Layer and cleanup. The HBA is offline
3540 now. */
3541 lpfc_sli_hba_down(phba);
92d7f7b0 3542 spin_lock_irq(&phba->hbalock);
7054a606 3543 phba->work_ha = 0;
92d7f7b0 3544 spin_unlock_irq(&phba->hbalock);
549e55cd
JS
3545 vports = lpfc_create_vport_work_array(phba);
3546 if (vports != NULL)
da0436e9 3547 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
549e55cd 3548 shost = lpfc_shost_from_vport(vports[i]);
549e55cd
JS
3549 spin_lock_irq(shost->host_lock);
3550 vports[i]->work_port_events = 0;
3551 vports[i]->fc_flag |= FC_OFFLINE_MODE;
3552 spin_unlock_irq(shost->host_lock);
3553 }
09372820 3554 lpfc_destroy_vport_work_array(phba, vports);
c490850a
JS
3555
3556 if (phba->cfg_xri_rebalancing)
3557 lpfc_destroy_multixri_pools(phba);
dea3101e 3558}
3559
e59058c4 3560/**
3621a710 3561 * lpfc_scsi_free - Free all the SCSI buffers and IOCBs from driver lists
e59058c4
JS
3562 * @phba: pointer to lpfc hba data structure.
3563 *
3564 * This routine is to free all the SCSI buffers and IOCBs from the driver
3565 * list back to kernel. It is called from lpfc_pci_remove_one to free
3566 * the internal resources before the device is removed from the system.
e59058c4 3567 **/
8a9d2e80 3568static void
2e0fef85 3569lpfc_scsi_free(struct lpfc_hba *phba)
dea3101e 3570{
c490850a 3571 struct lpfc_io_buf *sb, *sb_next;
dea3101e 3572
895427bd
JS
3573 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
3574 return;
3575
2e0fef85 3576 spin_lock_irq(&phba->hbalock);
a40fc5f0 3577
dea3101e 3578 /* Release all the lpfc_scsi_bufs maintained by this host. */
a40fc5f0
JS
3579
3580 spin_lock(&phba->scsi_buf_list_put_lock);
3581 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_put,
3582 list) {
dea3101e 3583 list_del(&sb->list);
771db5c0 3584 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
92d7f7b0 3585 sb->dma_handle);
dea3101e 3586 kfree(sb);
3587 phba->total_scsi_bufs--;
3588 }
a40fc5f0
JS
3589 spin_unlock(&phba->scsi_buf_list_put_lock);
3590
3591 spin_lock(&phba->scsi_buf_list_get_lock);
3592 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_get,
3593 list) {
dea3101e 3594 list_del(&sb->list);
771db5c0 3595 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
92d7f7b0 3596 sb->dma_handle);
dea3101e 3597 kfree(sb);
3598 phba->total_scsi_bufs--;
3599 }
a40fc5f0 3600 spin_unlock(&phba->scsi_buf_list_get_lock);
2e0fef85 3601 spin_unlock_irq(&phba->hbalock);
8a9d2e80 3602}
0794d601 3603
895427bd 3604/**
5e5b511d 3605 * lpfc_io_free - Free all the IO buffers and IOCBs from driver lists
895427bd
JS
3606 * @phba: pointer to lpfc hba data structure.
3607 *
0794d601 3608 * This routine is to free all the IO buffers and IOCBs from the driver
895427bd
JS
3609 * list back to kernel. It is called from lpfc_pci_remove_one to free
3610 * the internal resources before the device is removed from the system.
3611 **/
c490850a 3612void
5e5b511d 3613lpfc_io_free(struct lpfc_hba *phba)
895427bd 3614{
c490850a 3615 struct lpfc_io_buf *lpfc_ncmd, *lpfc_ncmd_next;
5e5b511d
JS
3616 struct lpfc_sli4_hdw_queue *qp;
3617 int idx;
895427bd 3618
5e5b511d
JS
3619 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3620 qp = &phba->sli4_hba.hdwq[idx];
3621 /* Release all the lpfc_nvme_bufs maintained by this host. */
3622 spin_lock(&qp->io_buf_list_put_lock);
3623 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3624 &qp->lpfc_io_buf_list_put,
3625 list) {
3626 list_del(&lpfc_ncmd->list);
3627 qp->put_io_bufs--;
3628 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3629 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
3630 kfree(lpfc_ncmd);
3631 qp->total_io_bufs--;
3632 }
3633 spin_unlock(&qp->io_buf_list_put_lock);
3634
3635 spin_lock(&qp->io_buf_list_get_lock);
3636 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3637 &qp->lpfc_io_buf_list_get,
3638 list) {
3639 list_del(&lpfc_ncmd->list);
3640 qp->get_io_bufs--;
3641 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3642 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
3643 kfree(lpfc_ncmd);
3644 qp->total_io_bufs--;
3645 }
3646 spin_unlock(&qp->io_buf_list_get_lock);
895427bd 3647 }
895427bd 3648}
0794d601 3649
8a9d2e80 3650/**
895427bd 3651 * lpfc_sli4_els_sgl_update - update ELS xri-sgl sizing and mapping
8a9d2e80
JS
3652 * @phba: pointer to lpfc hba data structure.
3653 *
3654 * This routine first calculates the sizes of the current els and allocated
3655 * scsi sgl lists, and then goes through all sgls to updates the physical
3656 * XRIs assigned due to port function reset. During port initialization, the
3657 * current els and allocated scsi sgl lists are 0s.
3658 *
3659 * Return codes
3660 * 0 - successful (for now, it always returns 0)
3661 **/
3662int
895427bd 3663lpfc_sli4_els_sgl_update(struct lpfc_hba *phba)
8a9d2e80
JS
3664{
3665 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
895427bd 3666 uint16_t i, lxri, xri_cnt, els_xri_cnt;
8a9d2e80 3667 LIST_HEAD(els_sgl_list);
8a9d2e80
JS
3668 int rc;
3669
3670 /*
3671 * update on pci function's els xri-sgl list
3672 */
3673 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
895427bd 3674
8a9d2e80
JS
3675 if (els_xri_cnt > phba->sli4_hba.els_xri_cnt) {
3676 /* els xri-sgl expanded */
3677 xri_cnt = els_xri_cnt - phba->sli4_hba.els_xri_cnt;
3678 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3679 "3157 ELS xri-sgl count increased from "
3680 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3681 els_xri_cnt);
3682 /* allocate the additional els sgls */
3683 for (i = 0; i < xri_cnt; i++) {
3684 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3685 GFP_KERNEL);
3686 if (sglq_entry == NULL) {
3687 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3688 "2562 Failure to allocate an "
3689 "ELS sgl entry:%d\n", i);
3690 rc = -ENOMEM;
3691 goto out_free_mem;
3692 }
3693 sglq_entry->buff_type = GEN_BUFF_TYPE;
3694 sglq_entry->virt = lpfc_mbuf_alloc(phba, 0,
3695 &sglq_entry->phys);
3696 if (sglq_entry->virt == NULL) {
3697 kfree(sglq_entry);
3698 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3699 "2563 Failure to allocate an "
3700 "ELS mbuf:%d\n", i);
3701 rc = -ENOMEM;
3702 goto out_free_mem;
3703 }
3704 sglq_entry->sgl = sglq_entry->virt;
3705 memset(sglq_entry->sgl, 0, LPFC_BPL_SIZE);
3706 sglq_entry->state = SGL_FREED;
3707 list_add_tail(&sglq_entry->list, &els_sgl_list);
3708 }
38c20673 3709 spin_lock_irq(&phba->hbalock);
895427bd
JS
3710 spin_lock(&phba->sli4_hba.sgl_list_lock);
3711 list_splice_init(&els_sgl_list,
3712 &phba->sli4_hba.lpfc_els_sgl_list);
3713 spin_unlock(&phba->sli4_hba.sgl_list_lock);
38c20673 3714 spin_unlock_irq(&phba->hbalock);
8a9d2e80
JS
3715 } else if (els_xri_cnt < phba->sli4_hba.els_xri_cnt) {
3716 /* els xri-sgl shrinked */
3717 xri_cnt = phba->sli4_hba.els_xri_cnt - els_xri_cnt;
3718 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3719 "3158 ELS xri-sgl count decreased from "
3720 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3721 els_xri_cnt);
3722 spin_lock_irq(&phba->hbalock);
895427bd
JS
3723 spin_lock(&phba->sli4_hba.sgl_list_lock);
3724 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list,
3725 &els_sgl_list);
8a9d2e80
JS
3726 /* release extra els sgls from list */
3727 for (i = 0; i < xri_cnt; i++) {
3728 list_remove_head(&els_sgl_list,
3729 sglq_entry, struct lpfc_sglq, list);
3730 if (sglq_entry) {
895427bd
JS
3731 __lpfc_mbuf_free(phba, sglq_entry->virt,
3732 sglq_entry->phys);
8a9d2e80
JS
3733 kfree(sglq_entry);
3734 }
3735 }
895427bd
JS
3736 list_splice_init(&els_sgl_list,
3737 &phba->sli4_hba.lpfc_els_sgl_list);
3738 spin_unlock(&phba->sli4_hba.sgl_list_lock);
8a9d2e80
JS
3739 spin_unlock_irq(&phba->hbalock);
3740 } else
3741 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3742 "3163 ELS xri-sgl count unchanged: %d\n",
3743 els_xri_cnt);
3744 phba->sli4_hba.els_xri_cnt = els_xri_cnt;
3745
3746 /* update xris to els sgls on the list */
3747 sglq_entry = NULL;
3748 sglq_entry_next = NULL;
3749 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
895427bd 3750 &phba->sli4_hba.lpfc_els_sgl_list, list) {
8a9d2e80
JS
3751 lxri = lpfc_sli4_next_xritag(phba);
3752 if (lxri == NO_XRI) {
3753 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3754 "2400 Failed to allocate xri for "
3755 "ELS sgl\n");
3756 rc = -ENOMEM;
3757 goto out_free_mem;
3758 }
3759 sglq_entry->sli4_lxritag = lxri;
3760 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3761 }
895427bd
JS
3762 return 0;
3763
3764out_free_mem:
3765 lpfc_free_els_sgl_list(phba);
3766 return rc;
3767}
3768
f358dd0c
JS
3769/**
3770 * lpfc_sli4_nvmet_sgl_update - update xri-sgl sizing and mapping
3771 * @phba: pointer to lpfc hba data structure.
3772 *
3773 * This routine first calculates the sizes of the current els and allocated
3774 * scsi sgl lists, and then goes through all sgls to updates the physical
3775 * XRIs assigned due to port function reset. During port initialization, the
3776 * current els and allocated scsi sgl lists are 0s.
3777 *
3778 * Return codes
3779 * 0 - successful (for now, it always returns 0)
3780 **/
3781int
3782lpfc_sli4_nvmet_sgl_update(struct lpfc_hba *phba)
3783{
3784 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
3785 uint16_t i, lxri, xri_cnt, els_xri_cnt;
6c621a22 3786 uint16_t nvmet_xri_cnt;
f358dd0c
JS
3787 LIST_HEAD(nvmet_sgl_list);
3788 int rc;
3789
3790 /*
3791 * update on pci function's nvmet xri-sgl list
3792 */
3793 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
61f3d4bf 3794
6c621a22
JS
3795 /* For NVMET, ALL remaining XRIs are dedicated for IO processing */
3796 nvmet_xri_cnt = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
f358dd0c
JS
3797 if (nvmet_xri_cnt > phba->sli4_hba.nvmet_xri_cnt) {
3798 /* els xri-sgl expanded */
3799 xri_cnt = nvmet_xri_cnt - phba->sli4_hba.nvmet_xri_cnt;
3800 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3801 "6302 NVMET xri-sgl cnt grew from %d to %d\n",
3802 phba->sli4_hba.nvmet_xri_cnt, nvmet_xri_cnt);
3803 /* allocate the additional nvmet sgls */
3804 for (i = 0; i < xri_cnt; i++) {
3805 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3806 GFP_KERNEL);
3807 if (sglq_entry == NULL) {
3808 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3809 "6303 Failure to allocate an "
3810 "NVMET sgl entry:%d\n", i);
3811 rc = -ENOMEM;
3812 goto out_free_mem;
3813 }
3814 sglq_entry->buff_type = NVMET_BUFF_TYPE;
3815 sglq_entry->virt = lpfc_nvmet_buf_alloc(phba, 0,
3816 &sglq_entry->phys);
3817 if (sglq_entry->virt == NULL) {
3818 kfree(sglq_entry);
3819 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3820 "6304 Failure to allocate an "
3821 "NVMET buf:%d\n", i);
3822 rc = -ENOMEM;
3823 goto out_free_mem;
3824 }
3825 sglq_entry->sgl = sglq_entry->virt;
3826 memset(sglq_entry->sgl, 0,
3827 phba->cfg_sg_dma_buf_size);
3828 sglq_entry->state = SGL_FREED;
3829 list_add_tail(&sglq_entry->list, &nvmet_sgl_list);
3830 }
3831 spin_lock_irq(&phba->hbalock);
3832 spin_lock(&phba->sli4_hba.sgl_list_lock);
3833 list_splice_init(&nvmet_sgl_list,
3834 &phba->sli4_hba.lpfc_nvmet_sgl_list);
3835 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3836 spin_unlock_irq(&phba->hbalock);
3837 } else if (nvmet_xri_cnt < phba->sli4_hba.nvmet_xri_cnt) {
3838 /* nvmet xri-sgl shrunk */
3839 xri_cnt = phba->sli4_hba.nvmet_xri_cnt - nvmet_xri_cnt;
3840 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3841 "6305 NVMET xri-sgl count decreased from "
3842 "%d to %d\n", phba->sli4_hba.nvmet_xri_cnt,
3843 nvmet_xri_cnt);
3844 spin_lock_irq(&phba->hbalock);
3845 spin_lock(&phba->sli4_hba.sgl_list_lock);
3846 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list,
3847 &nvmet_sgl_list);
3848 /* release extra nvmet sgls from list */
3849 for (i = 0; i < xri_cnt; i++) {
3850 list_remove_head(&nvmet_sgl_list,
3851 sglq_entry, struct lpfc_sglq, list);
3852 if (sglq_entry) {
3853 lpfc_nvmet_buf_free(phba, sglq_entry->virt,
3854 sglq_entry->phys);
3855 kfree(sglq_entry);
3856 }
3857 }
3858 list_splice_init(&nvmet_sgl_list,
3859 &phba->sli4_hba.lpfc_nvmet_sgl_list);
3860 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3861 spin_unlock_irq(&phba->hbalock);
3862 } else
3863 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3864 "6306 NVMET xri-sgl count unchanged: %d\n",
3865 nvmet_xri_cnt);
3866 phba->sli4_hba.nvmet_xri_cnt = nvmet_xri_cnt;
3867
3868 /* update xris to nvmet sgls on the list */
3869 sglq_entry = NULL;
3870 sglq_entry_next = NULL;
3871 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
3872 &phba->sli4_hba.lpfc_nvmet_sgl_list, list) {
3873 lxri = lpfc_sli4_next_xritag(phba);
3874 if (lxri == NO_XRI) {
3875 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3876 "6307 Failed to allocate xri for "
3877 "NVMET sgl\n");
3878 rc = -ENOMEM;
3879 goto out_free_mem;
3880 }
3881 sglq_entry->sli4_lxritag = lxri;
3882 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3883 }
3884 return 0;
3885
3886out_free_mem:
3887 lpfc_free_nvmet_sgl_list(phba);
3888 return rc;
3889}
3890
5e5b511d
JS
3891int
3892lpfc_io_buf_flush(struct lpfc_hba *phba, struct list_head *cbuf)
3893{
3894 LIST_HEAD(blist);
3895 struct lpfc_sli4_hdw_queue *qp;
c490850a
JS
3896 struct lpfc_io_buf *lpfc_cmd;
3897 struct lpfc_io_buf *iobufp, *prev_iobufp;
5e5b511d
JS
3898 int idx, cnt, xri, inserted;
3899
3900 cnt = 0;
3901 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3902 qp = &phba->sli4_hba.hdwq[idx];
3903 spin_lock_irq(&qp->io_buf_list_get_lock);
3904 spin_lock(&qp->io_buf_list_put_lock);
3905
3906 /* Take everything off the get and put lists */
3907 list_splice_init(&qp->lpfc_io_buf_list_get, &blist);
3908 list_splice(&qp->lpfc_io_buf_list_put, &blist);
3909 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_get);
3910 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_put);
3911 cnt += qp->get_io_bufs + qp->put_io_bufs;
3912 qp->get_io_bufs = 0;
3913 qp->put_io_bufs = 0;
3914 qp->total_io_bufs = 0;
3915 spin_unlock(&qp->io_buf_list_put_lock);
3916 spin_unlock_irq(&qp->io_buf_list_get_lock);
3917 }
3918
3919 /*
3920 * Take IO buffers off blist and put on cbuf sorted by XRI.
3921 * This is because POST_SGL takes a sequential range of XRIs
3922 * to post to the firmware.
3923 */
3924 for (idx = 0; idx < cnt; idx++) {
c490850a 3925 list_remove_head(&blist, lpfc_cmd, struct lpfc_io_buf, list);
5e5b511d
JS
3926 if (!lpfc_cmd)
3927 return cnt;
3928 if (idx == 0) {
3929 list_add_tail(&lpfc_cmd->list, cbuf);
3930 continue;
3931 }
3932 xri = lpfc_cmd->cur_iocbq.sli4_xritag;
3933 inserted = 0;
3934 prev_iobufp = NULL;
3935 list_for_each_entry(iobufp, cbuf, list) {
3936 if (xri < iobufp->cur_iocbq.sli4_xritag) {
3937 if (prev_iobufp)
3938 list_add(&lpfc_cmd->list,
3939 &prev_iobufp->list);
3940 else
3941 list_add(&lpfc_cmd->list, cbuf);
3942 inserted = 1;
3943 break;
3944 }
3945 prev_iobufp = iobufp;
3946 }
3947 if (!inserted)
3948 list_add_tail(&lpfc_cmd->list, cbuf);
3949 }
3950 return cnt;
3951}
3952
3953int
3954lpfc_io_buf_replenish(struct lpfc_hba *phba, struct list_head *cbuf)
3955{
3956 struct lpfc_sli4_hdw_queue *qp;
c490850a 3957 struct lpfc_io_buf *lpfc_cmd;
5e5b511d
JS
3958 int idx, cnt;
3959
3960 qp = phba->sli4_hba.hdwq;
3961 cnt = 0;
3962 while (!list_empty(cbuf)) {
3963 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3964 list_remove_head(cbuf, lpfc_cmd,
c490850a 3965 struct lpfc_io_buf, list);
5e5b511d
JS
3966 if (!lpfc_cmd)
3967 return cnt;
3968 cnt++;
3969 qp = &phba->sli4_hba.hdwq[idx];
1fbf9742
JS
3970 lpfc_cmd->hdwq_no = idx;
3971 lpfc_cmd->hdwq = qp;
5e5b511d
JS
3972 lpfc_cmd->cur_iocbq.wqe_cmpl = NULL;
3973 lpfc_cmd->cur_iocbq.iocb_cmpl = NULL;
3974 spin_lock(&qp->io_buf_list_put_lock);
3975 list_add_tail(&lpfc_cmd->list,
3976 &qp->lpfc_io_buf_list_put);
3977 qp->put_io_bufs++;
3978 qp->total_io_bufs++;
3979 spin_unlock(&qp->io_buf_list_put_lock);
3980 }
3981 }
3982 return cnt;
3983}
3984
895427bd 3985/**
5e5b511d 3986 * lpfc_sli4_io_sgl_update - update xri-sgl sizing and mapping
895427bd
JS
3987 * @phba: pointer to lpfc hba data structure.
3988 *
3989 * This routine first calculates the sizes of the current els and allocated
3990 * scsi sgl lists, and then goes through all sgls to updates the physical
3991 * XRIs assigned due to port function reset. During port initialization, the
3992 * current els and allocated scsi sgl lists are 0s.
3993 *
3994 * Return codes
3995 * 0 - successful (for now, it always returns 0)
3996 **/
3997int
5e5b511d 3998lpfc_sli4_io_sgl_update(struct lpfc_hba *phba)
895427bd 3999{
c490850a 4000 struct lpfc_io_buf *lpfc_ncmd = NULL, *lpfc_ncmd_next = NULL;
0794d601 4001 uint16_t i, lxri, els_xri_cnt;
5e5b511d
JS
4002 uint16_t io_xri_cnt, io_xri_max;
4003 LIST_HEAD(io_sgl_list);
0794d601 4004 int rc, cnt;
8a9d2e80 4005
895427bd 4006 /*
0794d601 4007 * update on pci function's allocated nvme xri-sgl list
895427bd 4008 */
8a9d2e80 4009
0794d601
JS
4010 /* maximum number of xris available for nvme buffers */
4011 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
5e5b511d
JS
4012 io_xri_max = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
4013 phba->sli4_hba.io_xri_max = io_xri_max;
895427bd 4014
e8c0a779 4015 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
0794d601
JS
4016 "6074 Current allocated XRI sgl count:%d, "
4017 "maximum XRI count:%d\n",
5e5b511d
JS
4018 phba->sli4_hba.io_xri_cnt,
4019 phba->sli4_hba.io_xri_max);
8a9d2e80 4020
5e5b511d 4021 cnt = lpfc_io_buf_flush(phba, &io_sgl_list);
8a9d2e80 4022
5e5b511d 4023 if (phba->sli4_hba.io_xri_cnt > phba->sli4_hba.io_xri_max) {
0794d601 4024 /* max nvme xri shrunk below the allocated nvme buffers */
5e5b511d
JS
4025 io_xri_cnt = phba->sli4_hba.io_xri_cnt -
4026 phba->sli4_hba.io_xri_max;
0794d601 4027 /* release the extra allocated nvme buffers */
5e5b511d
JS
4028 for (i = 0; i < io_xri_cnt; i++) {
4029 list_remove_head(&io_sgl_list, lpfc_ncmd,
c490850a 4030 struct lpfc_io_buf, list);
0794d601 4031 if (lpfc_ncmd) {
771db5c0 4032 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
0794d601
JS
4033 lpfc_ncmd->data,
4034 lpfc_ncmd->dma_handle);
4035 kfree(lpfc_ncmd);
a2fc4aef 4036 }
8a9d2e80 4037 }
5e5b511d 4038 phba->sli4_hba.io_xri_cnt -= io_xri_cnt;
8a9d2e80
JS
4039 }
4040
0794d601
JS
4041 /* update xris associated to remaining allocated nvme buffers */
4042 lpfc_ncmd = NULL;
4043 lpfc_ncmd_next = NULL;
5e5b511d 4044 phba->sli4_hba.io_xri_cnt = cnt;
0794d601 4045 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
5e5b511d 4046 &io_sgl_list, list) {
8a9d2e80
JS
4047 lxri = lpfc_sli4_next_xritag(phba);
4048 if (lxri == NO_XRI) {
4049 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
0794d601
JS
4050 "6075 Failed to allocate xri for "
4051 "nvme buffer\n");
8a9d2e80
JS
4052 rc = -ENOMEM;
4053 goto out_free_mem;
4054 }
0794d601
JS
4055 lpfc_ncmd->cur_iocbq.sli4_lxritag = lxri;
4056 lpfc_ncmd->cur_iocbq.sli4_xritag = phba->sli4_hba.xri_ids[lxri];
8a9d2e80 4057 }
5e5b511d 4058 cnt = lpfc_io_buf_replenish(phba, &io_sgl_list);
dea3101e 4059 return 0;
8a9d2e80
JS
4060
4061out_free_mem:
5e5b511d 4062 lpfc_io_free(phba);
8a9d2e80 4063 return rc;
dea3101e 4064}
4065
0794d601 4066/**
5e5b511d 4067 * lpfc_new_io_buf - IO buffer allocator for HBA with SLI4 IF spec
0794d601
JS
4068 * @vport: The virtual port for which this call being executed.
4069 * @num_to_allocate: The requested number of buffers to allocate.
4070 *
4071 * This routine allocates nvme buffers for device with SLI-4 interface spec,
4072 * the nvme buffer contains all the necessary information needed to initiate
4073 * an I/O. After allocating up to @num_to_allocate IO buffers and put
4074 * them on a list, it post them to the port by using SGL block post.
4075 *
4076 * Return codes:
5e5b511d 4077 * int - number of IO buffers that were allocated and posted.
0794d601
JS
4078 * 0 = failure, less than num_to_alloc is a partial failure.
4079 **/
4080int
5e5b511d 4081lpfc_new_io_buf(struct lpfc_hba *phba, int num_to_alloc)
0794d601 4082{
c490850a 4083 struct lpfc_io_buf *lpfc_ncmd;
0794d601
JS
4084 struct lpfc_iocbq *pwqeq;
4085 uint16_t iotag, lxri = 0;
4086 int bcnt, num_posted;
4087 LIST_HEAD(prep_nblist);
4088 LIST_HEAD(post_nblist);
4089 LIST_HEAD(nvme_nblist);
4090
4091 /* Sanity check to ensure our sizing is right for both SCSI and NVME */
c490850a 4092 if (sizeof(struct lpfc_io_buf) > LPFC_COMMON_IO_BUF_SZ) {
0794d601 4093 lpfc_printf_log(phba, KERN_ERR, LOG_FCP,
f996861b 4094 "6426 Common buffer size %zd exceeds %d\n",
c490850a
JS
4095 sizeof(struct lpfc_io_buf),
4096 LPFC_COMMON_IO_BUF_SZ);
0794d601
JS
4097 return 0;
4098 }
4099
5e5b511d 4100 phba->sli4_hba.io_xri_cnt = 0;
0794d601
JS
4101 for (bcnt = 0; bcnt < num_to_alloc; bcnt++) {
4102 lpfc_ncmd = kzalloc(LPFC_COMMON_IO_BUF_SZ, GFP_KERNEL);
4103 if (!lpfc_ncmd)
4104 break;
4105 /*
4106 * Get memory from the pci pool to map the virt space to
4107 * pci bus space for an I/O. The DMA buffer includes the
4108 * number of SGE's necessary to support the sg_tablesize.
4109 */
4110 lpfc_ncmd->data = dma_pool_alloc(phba->lpfc_sg_dma_buf_pool,
4111 GFP_KERNEL,
4112 &lpfc_ncmd->dma_handle);
4113 if (!lpfc_ncmd->data) {
4114 kfree(lpfc_ncmd);
4115 break;
4116 }
4117 memset(lpfc_ncmd->data, 0, phba->cfg_sg_dma_buf_size);
4118
4119 /*
4120 * 4K Page alignment is CRITICAL to BlockGuard, double check
4121 * to be sure.
4122 */
4123 if ((phba->sli3_options & LPFC_SLI3_BG_ENABLED) &&
4124 (((unsigned long)(lpfc_ncmd->data) &
4125 (unsigned long)(SLI4_PAGE_SIZE - 1)) != 0)) {
4126 lpfc_printf_log(phba, KERN_ERR, LOG_FCP,
4127 "3369 Memory alignment err: addr=%lx\n",
4128 (unsigned long)lpfc_ncmd->data);
4129 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4130 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
4131 kfree(lpfc_ncmd);
4132 break;
4133 }
4134
4135 lxri = lpfc_sli4_next_xritag(phba);
4136 if (lxri == NO_XRI) {
4137 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4138 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
4139 kfree(lpfc_ncmd);
4140 break;
4141 }
4142 pwqeq = &lpfc_ncmd->cur_iocbq;
4143
4144 /* Allocate iotag for lpfc_ncmd->cur_iocbq. */
4145 iotag = lpfc_sli_next_iotag(phba, pwqeq);
4146 if (iotag == 0) {
4147 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4148 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
4149 kfree(lpfc_ncmd);
4150 lpfc_printf_log(phba, KERN_ERR, LOG_NVME_IOERR,
4151 "6121 Failed to allocate IOTAG for"
4152 " XRI:0x%x\n", lxri);
4153 lpfc_sli4_free_xri(phba, lxri);
4154 break;
4155 }
4156 pwqeq->sli4_lxritag = lxri;
4157 pwqeq->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
4158 pwqeq->context1 = lpfc_ncmd;
4159
4160 /* Initialize local short-hand pointers. */
4161 lpfc_ncmd->dma_sgl = lpfc_ncmd->data;
4162 lpfc_ncmd->dma_phys_sgl = lpfc_ncmd->dma_handle;
4163 lpfc_ncmd->cur_iocbq.context1 = lpfc_ncmd;
c2017260 4164 spin_lock_init(&lpfc_ncmd->buf_lock);
0794d601
JS
4165
4166 /* add the nvme buffer to a post list */
4167 list_add_tail(&lpfc_ncmd->list, &post_nblist);
5e5b511d 4168 phba->sli4_hba.io_xri_cnt++;
0794d601
JS
4169 }
4170 lpfc_printf_log(phba, KERN_INFO, LOG_NVME,
4171 "6114 Allocate %d out of %d requested new NVME "
4172 "buffers\n", bcnt, num_to_alloc);
4173
4174 /* post the list of nvme buffer sgls to port if available */
4175 if (!list_empty(&post_nblist))
5e5b511d 4176 num_posted = lpfc_sli4_post_io_sgl_list(
0794d601
JS
4177 phba, &post_nblist, bcnt);
4178 else
4179 num_posted = 0;
4180
4181 return num_posted;
4182}
4183
96418b5e
JS
4184static uint64_t
4185lpfc_get_wwpn(struct lpfc_hba *phba)
4186{
4187 uint64_t wwn;
4188 int rc;
4189 LPFC_MBOXQ_t *mboxq;
4190 MAILBOX_t *mb;
4191
96418b5e
JS
4192 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
4193 GFP_KERNEL);
4194 if (!mboxq)
4195 return (uint64_t)-1;
4196
4197 /* First get WWN of HBA instance */
4198 lpfc_read_nv(phba, mboxq);
4199 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
4200 if (rc != MBX_SUCCESS) {
4201 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4202 "6019 Mailbox failed , mbxCmd x%x "
4203 "READ_NV, mbxStatus x%x\n",
4204 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
4205 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
4206 mempool_free(mboxq, phba->mbox_mem_pool);
4207 return (uint64_t) -1;
4208 }
4209 mb = &mboxq->u.mb;
4210 memcpy(&wwn, (char *)mb->un.varRDnvp.portname, sizeof(uint64_t));
4211 /* wwn is WWPN of HBA instance */
4212 mempool_free(mboxq, phba->mbox_mem_pool);
4213 if (phba->sli_rev == LPFC_SLI_REV4)
4214 return be64_to_cpu(wwn);
4215 else
286871a6 4216 return rol64(wwn, 32);
96418b5e
JS
4217}
4218
e59058c4 4219/**
3621a710 4220 * lpfc_create_port - Create an FC port
e59058c4
JS
4221 * @phba: pointer to lpfc hba data structure.
4222 * @instance: a unique integer ID to this FC port.
4223 * @dev: pointer to the device data structure.
4224 *
4225 * This routine creates a FC port for the upper layer protocol. The FC port
4226 * can be created on top of either a physical port or a virtual port provided
4227 * by the HBA. This routine also allocates a SCSI host data structure (shost)
4228 * and associates the FC port created before adding the shost into the SCSI
4229 * layer.
4230 *
4231 * Return codes
4232 * @vport - pointer to the virtual N_Port data structure.
4233 * NULL - port create failed.
4234 **/
2e0fef85 4235struct lpfc_vport *
3de2a653 4236lpfc_create_port(struct lpfc_hba *phba, int instance, struct device *dev)
47a8617c 4237{
2e0fef85 4238 struct lpfc_vport *vport;
895427bd 4239 struct Scsi_Host *shost = NULL;
2e0fef85 4240 int error = 0;
96418b5e
JS
4241 int i;
4242 uint64_t wwn;
4243 bool use_no_reset_hba = false;
56bc8028 4244 int rc;
96418b5e 4245
56bc8028
JS
4246 if (lpfc_no_hba_reset_cnt) {
4247 if (phba->sli_rev < LPFC_SLI_REV4 &&
4248 dev == &phba->pcidev->dev) {
4249 /* Reset the port first */
4250 lpfc_sli_brdrestart(phba);
4251 rc = lpfc_sli_chipset_init(phba);
4252 if (rc)
4253 return NULL;
4254 }
4255 wwn = lpfc_get_wwpn(phba);
4256 }
96418b5e
JS
4257
4258 for (i = 0; i < lpfc_no_hba_reset_cnt; i++) {
4259 if (wwn == lpfc_no_hba_reset[i]) {
4260 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4261 "6020 Setting use_no_reset port=%llx\n",
4262 wwn);
4263 use_no_reset_hba = true;
4264 break;
4265 }
4266 }
47a8617c 4267
895427bd
JS
4268 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
4269 if (dev != &phba->pcidev->dev) {
4270 shost = scsi_host_alloc(&lpfc_vport_template,
4271 sizeof(struct lpfc_vport));
4272 } else {
96418b5e 4273 if (!use_no_reset_hba)
895427bd
JS
4274 shost = scsi_host_alloc(&lpfc_template,
4275 sizeof(struct lpfc_vport));
4276 else
96418b5e 4277 shost = scsi_host_alloc(&lpfc_template_no_hr,
895427bd
JS
4278 sizeof(struct lpfc_vport));
4279 }
4280 } else if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
4281 shost = scsi_host_alloc(&lpfc_template_nvme,
ea4142f6
JS
4282 sizeof(struct lpfc_vport));
4283 }
2e0fef85
JS
4284 if (!shost)
4285 goto out;
47a8617c 4286
2e0fef85
JS
4287 vport = (struct lpfc_vport *) shost->hostdata;
4288 vport->phba = phba;
2e0fef85 4289 vport->load_flag |= FC_LOADING;
92d7f7b0 4290 vport->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
7f5f3d0d 4291 vport->fc_rscn_flush = 0;
3de2a653 4292 lpfc_get_vport_cfgparam(vport);
895427bd 4293
f6e84790
JS
4294 /* Adjust value in vport */
4295 vport->cfg_enable_fc4_type = phba->cfg_enable_fc4_type;
4296
2e0fef85
JS
4297 shost->unique_id = instance;
4298 shost->max_id = LPFC_MAX_TARGET;
3de2a653 4299 shost->max_lun = vport->cfg_max_luns;
2e0fef85
JS
4300 shost->this_id = -1;
4301 shost->max_cmd_len = 16;
6a828b0f 4302
da0436e9 4303 if (phba->sli_rev == LPFC_SLI_REV4) {
6a828b0f
JS
4304 if (phba->cfg_fcp_io_sched == LPFC_FCP_SCHED_BY_HDWQ)
4305 shost->nr_hw_queues = phba->cfg_hdw_queue;
4306 else
4307 shost->nr_hw_queues = phba->sli4_hba.num_present_cpu;
4308
28baac74 4309 shost->dma_boundary =
cb5172ea 4310 phba->sli4_hba.pc_sli4_params.sge_supp_len-1;
5b9e70b2 4311 shost->sg_tablesize = phba->cfg_scsi_seg_cnt;
ace44e48
JS
4312 } else
4313 /* SLI-3 has a limited number of hardware queues (3),
4314 * thus there is only one for FCP processing.
4315 */
4316 shost->nr_hw_queues = 1;
81301a9b 4317
47a8617c 4318 /*
2e0fef85
JS
4319 * Set initial can_queue value since 0 is no longer supported and
4320 * scsi_add_host will fail. This will be adjusted later based on the
4321 * max xri value determined in hba setup.
47a8617c 4322 */
2e0fef85 4323 shost->can_queue = phba->cfg_hba_queue_depth - 10;
3de2a653 4324 if (dev != &phba->pcidev->dev) {
92d7f7b0
JS
4325 shost->transportt = lpfc_vport_transport_template;
4326 vport->port_type = LPFC_NPIV_PORT;
4327 } else {
4328 shost->transportt = lpfc_transport_template;
4329 vport->port_type = LPFC_PHYSICAL_PORT;
4330 }
47a8617c 4331
2e0fef85
JS
4332 /* Initialize all internally managed lists. */
4333 INIT_LIST_HEAD(&vport->fc_nodes);
da0436e9 4334 INIT_LIST_HEAD(&vport->rcv_buffer_list);
2e0fef85 4335 spin_lock_init(&vport->work_port_lock);
47a8617c 4336
f22eb4d3 4337 timer_setup(&vport->fc_disctmo, lpfc_disc_timeout, 0);
47a8617c 4338
f22eb4d3 4339 timer_setup(&vport->els_tmofunc, lpfc_els_timeout, 0);
92494144 4340
f22eb4d3 4341 timer_setup(&vport->delayed_disc_tmo, lpfc_delayed_disc_tmo, 0);
92494144 4342
d139b9bd 4343 error = scsi_add_host_with_dma(shost, dev, &phba->pcidev->dev);
2e0fef85
JS
4344 if (error)
4345 goto out_put_shost;
47a8617c 4346
523128e5 4347 spin_lock_irq(&phba->port_list_lock);
2e0fef85 4348 list_add_tail(&vport->listentry, &phba->port_list);
523128e5 4349 spin_unlock_irq(&phba->port_list_lock);
2e0fef85 4350 return vport;
47a8617c 4351
2e0fef85
JS
4352out_put_shost:
4353 scsi_host_put(shost);
4354out:
4355 return NULL;
47a8617c
JS
4356}
4357
e59058c4 4358/**
3621a710 4359 * destroy_port - destroy an FC port
e59058c4
JS
4360 * @vport: pointer to an lpfc virtual N_Port data structure.
4361 *
4362 * This routine destroys a FC port from the upper layer protocol. All the
4363 * resources associated with the port are released.
4364 **/
2e0fef85
JS
4365void
4366destroy_port(struct lpfc_vport *vport)
47a8617c 4367{
92d7f7b0
JS
4368 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
4369 struct lpfc_hba *phba = vport->phba;
47a8617c 4370
858c9f6c 4371 lpfc_debugfs_terminate(vport);
92d7f7b0
JS
4372 fc_remove_host(shost);
4373 scsi_remove_host(shost);
47a8617c 4374
523128e5 4375 spin_lock_irq(&phba->port_list_lock);
92d7f7b0 4376 list_del_init(&vport->listentry);
523128e5 4377 spin_unlock_irq(&phba->port_list_lock);
47a8617c 4378
92d7f7b0 4379 lpfc_cleanup(vport);
47a8617c 4380 return;
47a8617c
JS
4381}
4382
e59058c4 4383/**
3621a710 4384 * lpfc_get_instance - Get a unique integer ID
e59058c4
JS
4385 *
4386 * This routine allocates a unique integer ID from lpfc_hba_index pool. It
4387 * uses the kernel idr facility to perform the task.
4388 *
4389 * Return codes:
4390 * instance - a unique integer ID allocated as the new instance.
4391 * -1 - lpfc get instance failed.
4392 **/
92d7f7b0
JS
4393int
4394lpfc_get_instance(void)
4395{
ab516036
TH
4396 int ret;
4397
4398 ret = idr_alloc(&lpfc_hba_index, NULL, 0, 0, GFP_KERNEL);
4399 return ret < 0 ? -1 : ret;
47a8617c
JS
4400}
4401
e59058c4 4402/**
3621a710 4403 * lpfc_scan_finished - method for SCSI layer to detect whether scan is done
e59058c4
JS
4404 * @shost: pointer to SCSI host data structure.
4405 * @time: elapsed time of the scan in jiffies.
4406 *
4407 * This routine is called by the SCSI layer with a SCSI host to determine
4408 * whether the scan host is finished.
4409 *
4410 * Note: there is no scan_start function as adapter initialization will have
4411 * asynchronously kicked off the link initialization.
4412 *
4413 * Return codes
4414 * 0 - SCSI host scan is not over yet.
4415 * 1 - SCSI host scan is over.
4416 **/
47a8617c
JS
4417int lpfc_scan_finished(struct Scsi_Host *shost, unsigned long time)
4418{
2e0fef85
JS
4419 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4420 struct lpfc_hba *phba = vport->phba;
858c9f6c 4421 int stat = 0;
47a8617c 4422
858c9f6c
JS
4423 spin_lock_irq(shost->host_lock);
4424
51ef4c26 4425 if (vport->load_flag & FC_UNLOADING) {
858c9f6c
JS
4426 stat = 1;
4427 goto finished;
4428 }
256ec0d0 4429 if (time >= msecs_to_jiffies(30 * 1000)) {
2e0fef85 4430 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011
JS
4431 "0461 Scanning longer than 30 "
4432 "seconds. Continuing initialization\n");
858c9f6c 4433 stat = 1;
47a8617c 4434 goto finished;
2e0fef85 4435 }
256ec0d0
JS
4436 if (time >= msecs_to_jiffies(15 * 1000) &&
4437 phba->link_state <= LPFC_LINK_DOWN) {
2e0fef85 4438 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011
JS
4439 "0465 Link down longer than 15 "
4440 "seconds. Continuing initialization\n");
858c9f6c 4441 stat = 1;
47a8617c 4442 goto finished;
2e0fef85 4443 }
47a8617c 4444
2e0fef85 4445 if (vport->port_state != LPFC_VPORT_READY)
858c9f6c 4446 goto finished;
2e0fef85 4447 if (vport->num_disc_nodes || vport->fc_prli_sent)
858c9f6c 4448 goto finished;
256ec0d0 4449 if (vport->fc_map_cnt == 0 && time < msecs_to_jiffies(2 * 1000))
858c9f6c 4450 goto finished;
2e0fef85 4451 if ((phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) != 0)
858c9f6c
JS
4452 goto finished;
4453
4454 stat = 1;
47a8617c
JS
4455
4456finished:
858c9f6c
JS
4457 spin_unlock_irq(shost->host_lock);
4458 return stat;
92d7f7b0 4459}
47a8617c 4460
cd71348a
JS
4461void lpfc_host_supported_speeds_set(struct Scsi_Host *shost)
4462{
4463 struct lpfc_vport *vport = (struct lpfc_vport *)shost->hostdata;
4464 struct lpfc_hba *phba = vport->phba;
4465
4466 fc_host_supported_speeds(shost) = 0;
1dc5ec24
JS
4467 if (phba->lmt & LMT_128Gb)
4468 fc_host_supported_speeds(shost) |= FC_PORTSPEED_128GBIT;
cd71348a
JS
4469 if (phba->lmt & LMT_64Gb)
4470 fc_host_supported_speeds(shost) |= FC_PORTSPEED_64GBIT;
4471 if (phba->lmt & LMT_32Gb)
4472 fc_host_supported_speeds(shost) |= FC_PORTSPEED_32GBIT;
4473 if (phba->lmt & LMT_16Gb)
4474 fc_host_supported_speeds(shost) |= FC_PORTSPEED_16GBIT;
4475 if (phba->lmt & LMT_10Gb)
4476 fc_host_supported_speeds(shost) |= FC_PORTSPEED_10GBIT;
4477 if (phba->lmt & LMT_8Gb)
4478 fc_host_supported_speeds(shost) |= FC_PORTSPEED_8GBIT;
4479 if (phba->lmt & LMT_4Gb)
4480 fc_host_supported_speeds(shost) |= FC_PORTSPEED_4GBIT;
4481 if (phba->lmt & LMT_2Gb)
4482 fc_host_supported_speeds(shost) |= FC_PORTSPEED_2GBIT;
4483 if (phba->lmt & LMT_1Gb)
4484 fc_host_supported_speeds(shost) |= FC_PORTSPEED_1GBIT;
4485}
4486
e59058c4 4487/**
3621a710 4488 * lpfc_host_attrib_init - Initialize SCSI host attributes on a FC port
e59058c4
JS
4489 * @shost: pointer to SCSI host data structure.
4490 *
4491 * This routine initializes a given SCSI host attributes on a FC port. The
4492 * SCSI host can be either on top of a physical port or a virtual port.
4493 **/
92d7f7b0
JS
4494void lpfc_host_attrib_init(struct Scsi_Host *shost)
4495{
4496 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4497 struct lpfc_hba *phba = vport->phba;
47a8617c 4498 /*
2e0fef85 4499 * Set fixed host attributes. Must done after lpfc_sli_hba_setup().
47a8617c
JS
4500 */
4501
2e0fef85
JS
4502 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
4503 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
47a8617c
JS
4504 fc_host_supported_classes(shost) = FC_COS_CLASS3;
4505
4506 memset(fc_host_supported_fc4s(shost), 0,
2e0fef85 4507 sizeof(fc_host_supported_fc4s(shost)));
47a8617c
JS
4508 fc_host_supported_fc4s(shost)[2] = 1;
4509 fc_host_supported_fc4s(shost)[7] = 1;
4510
92d7f7b0
JS
4511 lpfc_vport_symbolic_node_name(vport, fc_host_symbolic_name(shost),
4512 sizeof fc_host_symbolic_name(shost));
47a8617c 4513
cd71348a 4514 lpfc_host_supported_speeds_set(shost);
47a8617c
JS
4515
4516 fc_host_maxframe_size(shost) =
2e0fef85
JS
4517 (((uint32_t) vport->fc_sparam.cmn.bbRcvSizeMsb & 0x0F) << 8) |
4518 (uint32_t) vport->fc_sparam.cmn.bbRcvSizeLsb;
47a8617c 4519
0af5d708
MC
4520 fc_host_dev_loss_tmo(shost) = vport->cfg_devloss_tmo;
4521
47a8617c
JS
4522 /* This value is also unchanging */
4523 memset(fc_host_active_fc4s(shost), 0,
2e0fef85 4524 sizeof(fc_host_active_fc4s(shost)));
47a8617c
JS
4525 fc_host_active_fc4s(shost)[2] = 1;
4526 fc_host_active_fc4s(shost)[7] = 1;
4527
92d7f7b0 4528 fc_host_max_npiv_vports(shost) = phba->max_vpi;
47a8617c 4529 spin_lock_irq(shost->host_lock);
51ef4c26 4530 vport->load_flag &= ~FC_LOADING;
47a8617c 4531 spin_unlock_irq(shost->host_lock);
47a8617c 4532}
dea3101e 4533
e59058c4 4534/**
da0436e9 4535 * lpfc_stop_port_s3 - Stop SLI3 device port
e59058c4
JS
4536 * @phba: pointer to lpfc hba data structure.
4537 *
da0436e9
JS
4538 * This routine is invoked to stop an SLI3 device port, it stops the device
4539 * from generating interrupts and stops the device driver's timers for the
4540 * device.
e59058c4 4541 **/
da0436e9
JS
4542static void
4543lpfc_stop_port_s3(struct lpfc_hba *phba)
db2378e0 4544{
da0436e9
JS
4545 /* Clear all interrupt enable conditions */
4546 writel(0, phba->HCregaddr);
4547 readl(phba->HCregaddr); /* flush */
4548 /* Clear all pending interrupts */
4549 writel(0xffffffff, phba->HAregaddr);
4550 readl(phba->HAregaddr); /* flush */
db2378e0 4551
da0436e9
JS
4552 /* Reset some HBA SLI setup states */
4553 lpfc_stop_hba_timers(phba);
4554 phba->pport->work_port_events = 0;
4555}
db2378e0 4556
da0436e9
JS
4557/**
4558 * lpfc_stop_port_s4 - Stop SLI4 device port
4559 * @phba: pointer to lpfc hba data structure.
4560 *
4561 * This routine is invoked to stop an SLI4 device port, it stops the device
4562 * from generating interrupts and stops the device driver's timers for the
4563 * device.
4564 **/
4565static void
4566lpfc_stop_port_s4(struct lpfc_hba *phba)
4567{
4568 /* Reset some HBA SLI4 setup states */
4569 lpfc_stop_hba_timers(phba);
cdb42bec
JS
4570 if (phba->pport)
4571 phba->pport->work_port_events = 0;
da0436e9 4572 phba->sli4_hba.intr_enable = 0;
da0436e9 4573}
9399627f 4574
da0436e9
JS
4575/**
4576 * lpfc_stop_port - Wrapper function for stopping hba port
4577 * @phba: Pointer to HBA context object.
4578 *
4579 * This routine wraps the actual SLI3 or SLI4 hba stop port routine from
4580 * the API jump table function pointer from the lpfc_hba struct.
4581 **/
4582void
4583lpfc_stop_port(struct lpfc_hba *phba)
4584{
4585 phba->lpfc_stop_port(phba);
f485c18d
DK
4586
4587 if (phba->wq)
4588 flush_workqueue(phba->wq);
da0436e9 4589}
db2378e0 4590
ecfd03c6
JS
4591/**
4592 * lpfc_fcf_redisc_wait_start_timer - Start fcf rediscover wait timer
4593 * @phba: Pointer to hba for which this call is being executed.
4594 *
4595 * This routine starts the timer waiting for the FCF rediscovery to complete.
4596 **/
4597void
4598lpfc_fcf_redisc_wait_start_timer(struct lpfc_hba *phba)
4599{
4600 unsigned long fcf_redisc_wait_tmo =
4601 (jiffies + msecs_to_jiffies(LPFC_FCF_REDISCOVER_WAIT_TMO));
4602 /* Start fcf rediscovery wait period timer */
4603 mod_timer(&phba->fcf.redisc_wait, fcf_redisc_wait_tmo);
4604 spin_lock_irq(&phba->hbalock);
4605 /* Allow action to new fcf asynchronous event */
4606 phba->fcf.fcf_flag &= ~(FCF_AVAILABLE | FCF_SCAN_DONE);
4607 /* Mark the FCF rediscovery pending state */
4608 phba->fcf.fcf_flag |= FCF_REDISC_PEND;
4609 spin_unlock_irq(&phba->hbalock);
4610}
4611
4612/**
4613 * lpfc_sli4_fcf_redisc_wait_tmo - FCF table rediscover wait timeout
4614 * @ptr: Map to lpfc_hba data structure pointer.
4615 *
4616 * This routine is invoked when waiting for FCF table rediscover has been
4617 * timed out. If new FCF record(s) has (have) been discovered during the
4618 * wait period, a new FCF event shall be added to the FCOE async event
4619 * list, and then worker thread shall be waked up for processing from the
4620 * worker thread context.
4621 **/
e399b228 4622static void
f22eb4d3 4623lpfc_sli4_fcf_redisc_wait_tmo(struct timer_list *t)
ecfd03c6 4624{
f22eb4d3 4625 struct lpfc_hba *phba = from_timer(phba, t, fcf.redisc_wait);
ecfd03c6
JS
4626
4627 /* Don't send FCF rediscovery event if timer cancelled */
4628 spin_lock_irq(&phba->hbalock);
4629 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
4630 spin_unlock_irq(&phba->hbalock);
4631 return;
4632 }
4633 /* Clear FCF rediscovery timer pending flag */
4634 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
4635 /* FCF rediscovery event to worker thread */
4636 phba->fcf.fcf_flag |= FCF_REDISC_EVT;
4637 spin_unlock_irq(&phba->hbalock);
0c9ab6f5 4638 lpfc_printf_log(phba, KERN_INFO, LOG_FIP,
a93ff37a 4639 "2776 FCF rediscover quiescent timer expired\n");
ecfd03c6
JS
4640 /* wake up worker thread */
4641 lpfc_worker_wake_up(phba);
4642}
4643
e59058c4 4644/**
da0436e9 4645 * lpfc_sli4_parse_latt_fault - Parse sli4 link-attention link fault code
e59058c4 4646 * @phba: pointer to lpfc hba data structure.
da0436e9 4647 * @acqe_link: pointer to the async link completion queue entry.
e59058c4 4648 *
23288b78 4649 * This routine is to parse the SLI4 link-attention link fault code.
e59058c4 4650 **/
23288b78 4651static void
da0436e9
JS
4652lpfc_sli4_parse_latt_fault(struct lpfc_hba *phba,
4653 struct lpfc_acqe_link *acqe_link)
db2378e0 4654{
da0436e9
JS
4655 switch (bf_get(lpfc_acqe_link_fault, acqe_link)) {
4656 case LPFC_ASYNC_LINK_FAULT_NONE:
4657 case LPFC_ASYNC_LINK_FAULT_LOCAL:
4658 case LPFC_ASYNC_LINK_FAULT_REMOTE:
23288b78 4659 case LPFC_ASYNC_LINK_FAULT_LR_LRR:
da0436e9
JS
4660 break;
4661 default:
4662 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
23288b78 4663 "0398 Unknown link fault code: x%x\n",
da0436e9 4664 bf_get(lpfc_acqe_link_fault, acqe_link));
da0436e9
JS
4665 break;
4666 }
db2378e0
JS
4667}
4668
5b75da2f 4669/**
da0436e9 4670 * lpfc_sli4_parse_latt_type - Parse sli4 link attention type
5b75da2f 4671 * @phba: pointer to lpfc hba data structure.
da0436e9 4672 * @acqe_link: pointer to the async link completion queue entry.
5b75da2f 4673 *
da0436e9
JS
4674 * This routine is to parse the SLI4 link attention type and translate it
4675 * into the base driver's link attention type coding.
5b75da2f 4676 *
da0436e9
JS
4677 * Return: Link attention type in terms of base driver's coding.
4678 **/
4679static uint8_t
4680lpfc_sli4_parse_latt_type(struct lpfc_hba *phba,
4681 struct lpfc_acqe_link *acqe_link)
5b75da2f 4682{
da0436e9 4683 uint8_t att_type;
5b75da2f 4684
da0436e9
JS
4685 switch (bf_get(lpfc_acqe_link_status, acqe_link)) {
4686 case LPFC_ASYNC_LINK_STATUS_DOWN:
4687 case LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN:
76a95d75 4688 att_type = LPFC_ATT_LINK_DOWN;
da0436e9
JS
4689 break;
4690 case LPFC_ASYNC_LINK_STATUS_UP:
4691 /* Ignore physical link up events - wait for logical link up */
76a95d75 4692 att_type = LPFC_ATT_RESERVED;
da0436e9
JS
4693 break;
4694 case LPFC_ASYNC_LINK_STATUS_LOGICAL_UP:
76a95d75 4695 att_type = LPFC_ATT_LINK_UP;
da0436e9
JS
4696 break;
4697 default:
4698 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
4699 "0399 Invalid link attention type: x%x\n",
4700 bf_get(lpfc_acqe_link_status, acqe_link));
76a95d75 4701 att_type = LPFC_ATT_RESERVED;
da0436e9 4702 break;
5b75da2f 4703 }
da0436e9 4704 return att_type;
5b75da2f
JS
4705}
4706
8b68cd52
JS
4707/**
4708 * lpfc_sli_port_speed_get - Get sli3 link speed code to link speed
4709 * @phba: pointer to lpfc hba data structure.
4710 *
4711 * This routine is to get an SLI3 FC port's link speed in Mbps.
4712 *
4713 * Return: link speed in terms of Mbps.
4714 **/
4715uint32_t
4716lpfc_sli_port_speed_get(struct lpfc_hba *phba)
4717{
4718 uint32_t link_speed;
4719
4720 if (!lpfc_is_link_up(phba))
4721 return 0;
4722
a085e87c
JS
4723 if (phba->sli_rev <= LPFC_SLI_REV3) {
4724 switch (phba->fc_linkspeed) {
4725 case LPFC_LINK_SPEED_1GHZ:
4726 link_speed = 1000;
4727 break;
4728 case LPFC_LINK_SPEED_2GHZ:
4729 link_speed = 2000;
4730 break;
4731 case LPFC_LINK_SPEED_4GHZ:
4732 link_speed = 4000;
4733 break;
4734 case LPFC_LINK_SPEED_8GHZ:
4735 link_speed = 8000;
4736 break;
4737 case LPFC_LINK_SPEED_10GHZ:
4738 link_speed = 10000;
4739 break;
4740 case LPFC_LINK_SPEED_16GHZ:
4741 link_speed = 16000;
4742 break;
4743 default:
4744 link_speed = 0;
4745 }
4746 } else {
4747 if (phba->sli4_hba.link_state.logical_speed)
4748 link_speed =
4749 phba->sli4_hba.link_state.logical_speed;
4750 else
4751 link_speed = phba->sli4_hba.link_state.speed;
8b68cd52
JS
4752 }
4753 return link_speed;
4754}
4755
4756/**
4757 * lpfc_sli4_port_speed_parse - Parse async evt link speed code to link speed
4758 * @phba: pointer to lpfc hba data structure.
4759 * @evt_code: asynchronous event code.
4760 * @speed_code: asynchronous event link speed code.
4761 *
4762 * This routine is to parse the giving SLI4 async event link speed code into
4763 * value of Mbps for the link speed.
4764 *
4765 * Return: link speed in terms of Mbps.
4766 **/
4767static uint32_t
4768lpfc_sli4_port_speed_parse(struct lpfc_hba *phba, uint32_t evt_code,
4769 uint8_t speed_code)
4770{
4771 uint32_t port_speed;
4772
4773 switch (evt_code) {
4774 case LPFC_TRAILER_CODE_LINK:
4775 switch (speed_code) {
26d830ec 4776 case LPFC_ASYNC_LINK_SPEED_ZERO:
8b68cd52
JS
4777 port_speed = 0;
4778 break;
26d830ec 4779 case LPFC_ASYNC_LINK_SPEED_10MBPS:
8b68cd52
JS
4780 port_speed = 10;
4781 break;
26d830ec 4782 case LPFC_ASYNC_LINK_SPEED_100MBPS:
8b68cd52
JS
4783 port_speed = 100;
4784 break;
26d830ec 4785 case LPFC_ASYNC_LINK_SPEED_1GBPS:
8b68cd52
JS
4786 port_speed = 1000;
4787 break;
26d830ec 4788 case LPFC_ASYNC_LINK_SPEED_10GBPS:
8b68cd52
JS
4789 port_speed = 10000;
4790 break;
26d830ec
JS
4791 case LPFC_ASYNC_LINK_SPEED_20GBPS:
4792 port_speed = 20000;
4793 break;
4794 case LPFC_ASYNC_LINK_SPEED_25GBPS:
4795 port_speed = 25000;
4796 break;
4797 case LPFC_ASYNC_LINK_SPEED_40GBPS:
4798 port_speed = 40000;
4799 break;
8b68cd52
JS
4800 default:
4801 port_speed = 0;
4802 }
4803 break;
4804 case LPFC_TRAILER_CODE_FC:
4805 switch (speed_code) {
26d830ec 4806 case LPFC_FC_LA_SPEED_UNKNOWN:
8b68cd52
JS
4807 port_speed = 0;
4808 break;
26d830ec 4809 case LPFC_FC_LA_SPEED_1G:
8b68cd52
JS
4810 port_speed = 1000;
4811 break;
26d830ec 4812 case LPFC_FC_LA_SPEED_2G:
8b68cd52
JS
4813 port_speed = 2000;
4814 break;
26d830ec 4815 case LPFC_FC_LA_SPEED_4G:
8b68cd52
JS
4816 port_speed = 4000;
4817 break;
26d830ec 4818 case LPFC_FC_LA_SPEED_8G:
8b68cd52
JS
4819 port_speed = 8000;
4820 break;
26d830ec 4821 case LPFC_FC_LA_SPEED_10G:
8b68cd52
JS
4822 port_speed = 10000;
4823 break;
26d830ec 4824 case LPFC_FC_LA_SPEED_16G:
8b68cd52
JS
4825 port_speed = 16000;
4826 break;
d38dd52c
JS
4827 case LPFC_FC_LA_SPEED_32G:
4828 port_speed = 32000;
4829 break;
fbd8a6ba
JS
4830 case LPFC_FC_LA_SPEED_64G:
4831 port_speed = 64000;
4832 break;
1dc5ec24
JS
4833 case LPFC_FC_LA_SPEED_128G:
4834 port_speed = 128000;
4835 break;
8b68cd52
JS
4836 default:
4837 port_speed = 0;
4838 }
4839 break;
4840 default:
4841 port_speed = 0;
4842 }
4843 return port_speed;
4844}
4845
da0436e9 4846/**
70f3c073 4847 * lpfc_sli4_async_link_evt - Process the asynchronous FCoE link event
da0436e9
JS
4848 * @phba: pointer to lpfc hba data structure.
4849 * @acqe_link: pointer to the async link completion queue entry.
4850 *
70f3c073 4851 * This routine is to handle the SLI4 asynchronous FCoE link event.
da0436e9
JS
4852 **/
4853static void
4854lpfc_sli4_async_link_evt(struct lpfc_hba *phba,
4855 struct lpfc_acqe_link *acqe_link)
4856{
4857 struct lpfc_dmabuf *mp;
4858 LPFC_MBOXQ_t *pmb;
4859 MAILBOX_t *mb;
76a95d75 4860 struct lpfc_mbx_read_top *la;
da0436e9 4861 uint8_t att_type;
76a95d75 4862 int rc;
da0436e9
JS
4863
4864 att_type = lpfc_sli4_parse_latt_type(phba, acqe_link);
76a95d75 4865 if (att_type != LPFC_ATT_LINK_DOWN && att_type != LPFC_ATT_LINK_UP)
da0436e9 4866 return;
32b9793f 4867 phba->fcoe_eventtag = acqe_link->event_tag;
da0436e9
JS
4868 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
4869 if (!pmb) {
4870 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4871 "0395 The mboxq allocation failed\n");
4872 return;
4873 }
4874 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
4875 if (!mp) {
4876 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4877 "0396 The lpfc_dmabuf allocation failed\n");
4878 goto out_free_pmb;
4879 }
4880 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
4881 if (!mp->virt) {
4882 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4883 "0397 The mbuf allocation failed\n");
4884 goto out_free_dmabuf;
4885 }
4886
4887 /* Cleanup any outstanding ELS commands */
4888 lpfc_els_flush_all_cmd(phba);
4889
4890 /* Block ELS IOCBs until we have done process link event */
895427bd 4891 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
da0436e9
JS
4892
4893 /* Update link event statistics */
4894 phba->sli.slistat.link_event++;
4895
76a95d75
JS
4896 /* Create lpfc_handle_latt mailbox command from link ACQE */
4897 lpfc_read_topology(phba, pmb, mp);
4898 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
da0436e9
JS
4899 pmb->vport = phba->pport;
4900
da0436e9
JS
4901 /* Keep the link status for extra SLI4 state machine reference */
4902 phba->sli4_hba.link_state.speed =
8b68cd52
JS
4903 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_LINK,
4904 bf_get(lpfc_acqe_link_speed, acqe_link));
da0436e9
JS
4905 phba->sli4_hba.link_state.duplex =
4906 bf_get(lpfc_acqe_link_duplex, acqe_link);
4907 phba->sli4_hba.link_state.status =
4908 bf_get(lpfc_acqe_link_status, acqe_link);
70f3c073
JS
4909 phba->sli4_hba.link_state.type =
4910 bf_get(lpfc_acqe_link_type, acqe_link);
4911 phba->sli4_hba.link_state.number =
4912 bf_get(lpfc_acqe_link_number, acqe_link);
da0436e9
JS
4913 phba->sli4_hba.link_state.fault =
4914 bf_get(lpfc_acqe_link_fault, acqe_link);
65467b6b 4915 phba->sli4_hba.link_state.logical_speed =
8b68cd52
JS
4916 bf_get(lpfc_acqe_logical_link_speed, acqe_link) * 10;
4917
70f3c073 4918 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
c31098ce
JS
4919 "2900 Async FC/FCoE Link event - Speed:%dGBit "
4920 "duplex:x%x LA Type:x%x Port Type:%d Port Number:%d "
4921 "Logical speed:%dMbps Fault:%d\n",
70f3c073
JS
4922 phba->sli4_hba.link_state.speed,
4923 phba->sli4_hba.link_state.topology,
4924 phba->sli4_hba.link_state.status,
4925 phba->sli4_hba.link_state.type,
4926 phba->sli4_hba.link_state.number,
8b68cd52 4927 phba->sli4_hba.link_state.logical_speed,
70f3c073 4928 phba->sli4_hba.link_state.fault);
76a95d75
JS
4929 /*
4930 * For FC Mode: issue the READ_TOPOLOGY mailbox command to fetch
4931 * topology info. Note: Optional for non FC-AL ports.
4932 */
4933 if (!(phba->hba_flag & HBA_FCOE_MODE)) {
4934 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
4935 if (rc == MBX_NOT_FINISHED)
4936 goto out_free_dmabuf;
4937 return;
4938 }
4939 /*
4940 * For FCoE Mode: fill in all the topology information we need and call
4941 * the READ_TOPOLOGY completion routine to continue without actually
4942 * sending the READ_TOPOLOGY mailbox command to the port.
4943 */
23288b78 4944 /* Initialize completion status */
76a95d75 4945 mb = &pmb->u.mb;
23288b78
JS
4946 mb->mbxStatus = MBX_SUCCESS;
4947
4948 /* Parse port fault information field */
4949 lpfc_sli4_parse_latt_fault(phba, acqe_link);
76a95d75
JS
4950
4951 /* Parse and translate link attention fields */
4952 la = (struct lpfc_mbx_read_top *) &pmb->u.mb.un.varReadTop;
4953 la->eventTag = acqe_link->event_tag;
4954 bf_set(lpfc_mbx_read_top_att_type, la, att_type);
4955 bf_set(lpfc_mbx_read_top_link_spd, la,
a085e87c 4956 (bf_get(lpfc_acqe_link_speed, acqe_link)));
76a95d75
JS
4957
4958 /* Fake the the following irrelvant fields */
4959 bf_set(lpfc_mbx_read_top_topology, la, LPFC_TOPOLOGY_PT_PT);
4960 bf_set(lpfc_mbx_read_top_alpa_granted, la, 0);
4961 bf_set(lpfc_mbx_read_top_il, la, 0);
4962 bf_set(lpfc_mbx_read_top_pb, la, 0);
4963 bf_set(lpfc_mbx_read_top_fa, la, 0);
4964 bf_set(lpfc_mbx_read_top_mm, la, 0);
da0436e9
JS
4965
4966 /* Invoke the lpfc_handle_latt mailbox command callback function */
76a95d75 4967 lpfc_mbx_cmpl_read_topology(phba, pmb);
da0436e9 4968
5b75da2f 4969 return;
da0436e9
JS
4970
4971out_free_dmabuf:
4972 kfree(mp);
4973out_free_pmb:
4974 mempool_free(pmb, phba->mbox_mem_pool);
4975}
4976
1dc5ec24
JS
4977/**
4978 * lpfc_async_link_speed_to_read_top - Parse async evt link speed code to read
4979 * topology.
4980 * @phba: pointer to lpfc hba data structure.
4981 * @evt_code: asynchronous event code.
4982 * @speed_code: asynchronous event link speed code.
4983 *
4984 * This routine is to parse the giving SLI4 async event link speed code into
4985 * value of Read topology link speed.
4986 *
4987 * Return: link speed in terms of Read topology.
4988 **/
4989static uint8_t
4990lpfc_async_link_speed_to_read_top(struct lpfc_hba *phba, uint8_t speed_code)
4991{
4992 uint8_t port_speed;
4993
4994 switch (speed_code) {
4995 case LPFC_FC_LA_SPEED_1G:
4996 port_speed = LPFC_LINK_SPEED_1GHZ;
4997 break;
4998 case LPFC_FC_LA_SPEED_2G:
4999 port_speed = LPFC_LINK_SPEED_2GHZ;
5000 break;
5001 case LPFC_FC_LA_SPEED_4G:
5002 port_speed = LPFC_LINK_SPEED_4GHZ;
5003 break;
5004 case LPFC_FC_LA_SPEED_8G:
5005 port_speed = LPFC_LINK_SPEED_8GHZ;
5006 break;
5007 case LPFC_FC_LA_SPEED_16G:
5008 port_speed = LPFC_LINK_SPEED_16GHZ;
5009 break;
5010 case LPFC_FC_LA_SPEED_32G:
5011 port_speed = LPFC_LINK_SPEED_32GHZ;
5012 break;
5013 case LPFC_FC_LA_SPEED_64G:
5014 port_speed = LPFC_LINK_SPEED_64GHZ;
5015 break;
5016 case LPFC_FC_LA_SPEED_128G:
5017 port_speed = LPFC_LINK_SPEED_128GHZ;
5018 break;
5019 case LPFC_FC_LA_SPEED_256G:
5020 port_speed = LPFC_LINK_SPEED_256GHZ;
5021 break;
5022 default:
5023 port_speed = 0;
5024 break;
5025 }
5026
5027 return port_speed;
5028}
5029
5030#define trunk_link_status(__idx)\
5031 bf_get(lpfc_acqe_fc_la_trunk_config_port##__idx, acqe_fc) ?\
5032 ((phba->trunk_link.link##__idx.state == LPFC_LINK_UP) ?\
5033 "Link up" : "Link down") : "NA"
5034/* Did port __idx reported an error */
5035#define trunk_port_fault(__idx)\
5036 bf_get(lpfc_acqe_fc_la_trunk_config_port##__idx, acqe_fc) ?\
5037 (port_fault & (1 << __idx) ? "YES" : "NO") : "NA"
5038
5039static void
5040lpfc_update_trunk_link_status(struct lpfc_hba *phba,
5041 struct lpfc_acqe_fc_la *acqe_fc)
5042{
5043 uint8_t port_fault = bf_get(lpfc_acqe_fc_la_trunk_linkmask, acqe_fc);
5044 uint8_t err = bf_get(lpfc_acqe_fc_la_trunk_fault, acqe_fc);
5045
5046 phba->sli4_hba.link_state.speed =
5047 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
5048 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
5049
5050 phba->sli4_hba.link_state.logical_speed =
5051 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc);
5052 /* We got FC link speed, convert to fc_linkspeed (READ_TOPOLOGY) */
5053 phba->fc_linkspeed =
5054 lpfc_async_link_speed_to_read_top(
5055 phba,
5056 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
5057
5058 if (bf_get(lpfc_acqe_fc_la_trunk_config_port0, acqe_fc)) {
5059 phba->trunk_link.link0.state =
5060 bf_get(lpfc_acqe_fc_la_trunk_link_status_port0, acqe_fc)
5061 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5062 phba->trunk_link.link0.fault = port_fault & 0x1 ? err : 0;
1dc5ec24
JS
5063 }
5064 if (bf_get(lpfc_acqe_fc_la_trunk_config_port1, acqe_fc)) {
5065 phba->trunk_link.link1.state =
5066 bf_get(lpfc_acqe_fc_la_trunk_link_status_port1, acqe_fc)
5067 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5068 phba->trunk_link.link1.fault = port_fault & 0x2 ? err : 0;
1dc5ec24
JS
5069 }
5070 if (bf_get(lpfc_acqe_fc_la_trunk_config_port2, acqe_fc)) {
5071 phba->trunk_link.link2.state =
5072 bf_get(lpfc_acqe_fc_la_trunk_link_status_port2, acqe_fc)
5073 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5074 phba->trunk_link.link2.fault = port_fault & 0x4 ? err : 0;
1dc5ec24
JS
5075 }
5076 if (bf_get(lpfc_acqe_fc_la_trunk_config_port3, acqe_fc)) {
5077 phba->trunk_link.link3.state =
5078 bf_get(lpfc_acqe_fc_la_trunk_link_status_port3, acqe_fc)
5079 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5080 phba->trunk_link.link3.fault = port_fault & 0x8 ? err : 0;
1dc5ec24
JS
5081 }
5082
5083 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5084 "2910 Async FC Trunking Event - Speed:%d\n"
5085 "\tLogical speed:%d "
5086 "port0: %s port1: %s port2: %s port3: %s\n",
5087 phba->sli4_hba.link_state.speed,
5088 phba->sli4_hba.link_state.logical_speed,
5089 trunk_link_status(0), trunk_link_status(1),
5090 trunk_link_status(2), trunk_link_status(3));
5091
5092 if (port_fault)
5093 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5094 "3202 trunk error:0x%x (%s) seen on port0:%s "
5095 /*
5096 * SLI-4: We have only 0xA error codes
5097 * defined as of now. print an appropriate
5098 * message in case driver needs to be updated.
5099 */
5100 "port1:%s port2:%s port3:%s\n", err, err > 0xA ?
5101 "UNDEFINED. update driver." : trunk_errmsg[err],
5102 trunk_port_fault(0), trunk_port_fault(1),
5103 trunk_port_fault(2), trunk_port_fault(3));
5104}
5105
5106
70f3c073
JS
5107/**
5108 * lpfc_sli4_async_fc_evt - Process the asynchronous FC link event
5109 * @phba: pointer to lpfc hba data structure.
5110 * @acqe_fc: pointer to the async fc completion queue entry.
5111 *
5112 * This routine is to handle the SLI4 asynchronous FC event. It will simply log
5113 * that the event was received and then issue a read_topology mailbox command so
5114 * that the rest of the driver will treat it the same as SLI3.
5115 **/
5116static void
5117lpfc_sli4_async_fc_evt(struct lpfc_hba *phba, struct lpfc_acqe_fc_la *acqe_fc)
5118{
5119 struct lpfc_dmabuf *mp;
5120 LPFC_MBOXQ_t *pmb;
7bdedb34
JS
5121 MAILBOX_t *mb;
5122 struct lpfc_mbx_read_top *la;
70f3c073
JS
5123 int rc;
5124
5125 if (bf_get(lpfc_trailer_type, acqe_fc) !=
5126 LPFC_FC_LA_EVENT_TYPE_FC_LINK) {
5127 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5128 "2895 Non FC link Event detected.(%d)\n",
5129 bf_get(lpfc_trailer_type, acqe_fc));
5130 return;
5131 }
1dc5ec24
JS
5132
5133 if (bf_get(lpfc_acqe_fc_la_att_type, acqe_fc) ==
5134 LPFC_FC_LA_TYPE_TRUNKING_EVENT) {
5135 lpfc_update_trunk_link_status(phba, acqe_fc);
5136 return;
5137 }
5138
70f3c073
JS
5139 /* Keep the link status for extra SLI4 state machine reference */
5140 phba->sli4_hba.link_state.speed =
8b68cd52
JS
5141 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
5142 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
70f3c073
JS
5143 phba->sli4_hba.link_state.duplex = LPFC_ASYNC_LINK_DUPLEX_FULL;
5144 phba->sli4_hba.link_state.topology =
5145 bf_get(lpfc_acqe_fc_la_topology, acqe_fc);
5146 phba->sli4_hba.link_state.status =
5147 bf_get(lpfc_acqe_fc_la_att_type, acqe_fc);
5148 phba->sli4_hba.link_state.type =
5149 bf_get(lpfc_acqe_fc_la_port_type, acqe_fc);
5150 phba->sli4_hba.link_state.number =
5151 bf_get(lpfc_acqe_fc_la_port_number, acqe_fc);
5152 phba->sli4_hba.link_state.fault =
5153 bf_get(lpfc_acqe_link_fault, acqe_fc);
5154 phba->sli4_hba.link_state.logical_speed =
8b68cd52 5155 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
70f3c073
JS
5156 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5157 "2896 Async FC event - Speed:%dGBaud Topology:x%x "
5158 "LA Type:x%x Port Type:%d Port Number:%d Logical speed:"
5159 "%dMbps Fault:%d\n",
5160 phba->sli4_hba.link_state.speed,
5161 phba->sli4_hba.link_state.topology,
5162 phba->sli4_hba.link_state.status,
5163 phba->sli4_hba.link_state.type,
5164 phba->sli4_hba.link_state.number,
8b68cd52 5165 phba->sli4_hba.link_state.logical_speed,
70f3c073
JS
5166 phba->sli4_hba.link_state.fault);
5167 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
5168 if (!pmb) {
5169 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5170 "2897 The mboxq allocation failed\n");
5171 return;
5172 }
5173 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
5174 if (!mp) {
5175 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5176 "2898 The lpfc_dmabuf allocation failed\n");
5177 goto out_free_pmb;
5178 }
5179 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
5180 if (!mp->virt) {
5181 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5182 "2899 The mbuf allocation failed\n");
5183 goto out_free_dmabuf;
5184 }
5185
5186 /* Cleanup any outstanding ELS commands */
5187 lpfc_els_flush_all_cmd(phba);
5188
5189 /* Block ELS IOCBs until we have done process link event */
895427bd 5190 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
70f3c073
JS
5191
5192 /* Update link event statistics */
5193 phba->sli.slistat.link_event++;
5194
5195 /* Create lpfc_handle_latt mailbox command from link ACQE */
5196 lpfc_read_topology(phba, pmb, mp);
5197 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
5198 pmb->vport = phba->pport;
5199
7bdedb34 5200 if (phba->sli4_hba.link_state.status != LPFC_FC_LA_TYPE_LINK_UP) {
ae9e28f3
JS
5201 phba->link_flag &= ~(LS_MDS_LINK_DOWN | LS_MDS_LOOPBACK);
5202
5203 switch (phba->sli4_hba.link_state.status) {
5204 case LPFC_FC_LA_TYPE_MDS_LINK_DOWN:
5205 phba->link_flag |= LS_MDS_LINK_DOWN;
5206 break;
5207 case LPFC_FC_LA_TYPE_MDS_LOOPBACK:
5208 phba->link_flag |= LS_MDS_LOOPBACK;
5209 break;
5210 default:
5211 break;
5212 }
5213
23288b78 5214 /* Initialize completion status */
7bdedb34 5215 mb = &pmb->u.mb;
23288b78
JS
5216 mb->mbxStatus = MBX_SUCCESS;
5217
5218 /* Parse port fault information field */
5219 lpfc_sli4_parse_latt_fault(phba, (void *)acqe_fc);
7bdedb34
JS
5220
5221 /* Parse and translate link attention fields */
5222 la = (struct lpfc_mbx_read_top *)&pmb->u.mb.un.varReadTop;
5223 la->eventTag = acqe_fc->event_tag;
7bdedb34 5224
aeb3c817
JS
5225 if (phba->sli4_hba.link_state.status ==
5226 LPFC_FC_LA_TYPE_UNEXP_WWPN) {
5227 bf_set(lpfc_mbx_read_top_att_type, la,
5228 LPFC_FC_LA_TYPE_UNEXP_WWPN);
5229 } else {
5230 bf_set(lpfc_mbx_read_top_att_type, la,
5231 LPFC_FC_LA_TYPE_LINK_DOWN);
5232 }
7bdedb34
JS
5233 /* Invoke the mailbox command callback function */
5234 lpfc_mbx_cmpl_read_topology(phba, pmb);
5235
5236 return;
5237 }
5238
70f3c073
JS
5239 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
5240 if (rc == MBX_NOT_FINISHED)
5241 goto out_free_dmabuf;
5242 return;
5243
5244out_free_dmabuf:
5245 kfree(mp);
5246out_free_pmb:
5247 mempool_free(pmb, phba->mbox_mem_pool);
5248}
5249
5250/**
5251 * lpfc_sli4_async_sli_evt - Process the asynchronous SLI link event
5252 * @phba: pointer to lpfc hba data structure.
5253 * @acqe_fc: pointer to the async SLI completion queue entry.
5254 *
5255 * This routine is to handle the SLI4 asynchronous SLI events.
5256 **/
5257static void
5258lpfc_sli4_async_sli_evt(struct lpfc_hba *phba, struct lpfc_acqe_sli *acqe_sli)
5259{
4b8bae08 5260 char port_name;
8c1312e1 5261 char message[128];
4b8bae08 5262 uint8_t status;
946727dc 5263 uint8_t evt_type;
448193b5 5264 uint8_t operational = 0;
946727dc 5265 struct temp_event temp_event_data;
4b8bae08 5266 struct lpfc_acqe_misconfigured_event *misconfigured;
946727dc 5267 struct Scsi_Host *shost;
cd71348a
JS
5268 struct lpfc_vport **vports;
5269 int rc, i;
946727dc
JS
5270
5271 evt_type = bf_get(lpfc_trailer_type, acqe_sli);
4b8bae08 5272
448193b5
JS
5273 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5274 "2901 Async SLI event - Event Data1:x%08x Event Data2:"
5275 "x%08x SLI Event Type:%d\n",
5276 acqe_sli->event_data1, acqe_sli->event_data2,
5277 evt_type);
4b8bae08
JS
5278
5279 port_name = phba->Port[0];
5280 if (port_name == 0x00)
5281 port_name = '?'; /* get port name is empty */
5282
946727dc
JS
5283 switch (evt_type) {
5284 case LPFC_SLI_EVENT_TYPE_OVER_TEMP:
5285 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
5286 temp_event_data.event_code = LPFC_THRESHOLD_TEMP;
5287 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
5288
5289 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
5290 "3190 Over Temperature:%d Celsius- Port Name %c\n",
5291 acqe_sli->event_data1, port_name);
5292
310429ef 5293 phba->sfp_warning |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
946727dc
JS
5294 shost = lpfc_shost_from_vport(phba->pport);
5295 fc_host_post_vendor_event(shost, fc_get_event_number(),
5296 sizeof(temp_event_data),
5297 (char *)&temp_event_data,
5298 SCSI_NL_VID_TYPE_PCI
5299 | PCI_VENDOR_ID_EMULEX);
5300 break;
5301 case LPFC_SLI_EVENT_TYPE_NORM_TEMP:
5302 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
5303 temp_event_data.event_code = LPFC_NORMAL_TEMP;
5304 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
5305
5306 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5307 "3191 Normal Temperature:%d Celsius - Port Name %c\n",
5308 acqe_sli->event_data1, port_name);
5309
5310 shost = lpfc_shost_from_vport(phba->pport);
5311 fc_host_post_vendor_event(shost, fc_get_event_number(),
5312 sizeof(temp_event_data),
5313 (char *)&temp_event_data,
5314 SCSI_NL_VID_TYPE_PCI
5315 | PCI_VENDOR_ID_EMULEX);
5316 break;
5317 case LPFC_SLI_EVENT_TYPE_MISCONFIGURED:
5318 misconfigured = (struct lpfc_acqe_misconfigured_event *)
4b8bae08
JS
5319 &acqe_sli->event_data1;
5320
946727dc
JS
5321 /* fetch the status for this port */
5322 switch (phba->sli4_hba.lnk_info.lnk_no) {
5323 case LPFC_LINK_NUMBER_0:
448193b5
JS
5324 status = bf_get(lpfc_sli_misconfigured_port0_state,
5325 &misconfigured->theEvent);
5326 operational = bf_get(lpfc_sli_misconfigured_port0_op,
4b8bae08 5327 &misconfigured->theEvent);
946727dc
JS
5328 break;
5329 case LPFC_LINK_NUMBER_1:
448193b5
JS
5330 status = bf_get(lpfc_sli_misconfigured_port1_state,
5331 &misconfigured->theEvent);
5332 operational = bf_get(lpfc_sli_misconfigured_port1_op,
4b8bae08 5333 &misconfigured->theEvent);
946727dc
JS
5334 break;
5335 case LPFC_LINK_NUMBER_2:
448193b5
JS
5336 status = bf_get(lpfc_sli_misconfigured_port2_state,
5337 &misconfigured->theEvent);
5338 operational = bf_get(lpfc_sli_misconfigured_port2_op,
4b8bae08 5339 &misconfigured->theEvent);
946727dc
JS
5340 break;
5341 case LPFC_LINK_NUMBER_3:
448193b5
JS
5342 status = bf_get(lpfc_sli_misconfigured_port3_state,
5343 &misconfigured->theEvent);
5344 operational = bf_get(lpfc_sli_misconfigured_port3_op,
4b8bae08 5345 &misconfigured->theEvent);
946727dc
JS
5346 break;
5347 default:
448193b5
JS
5348 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5349 "3296 "
5350 "LPFC_SLI_EVENT_TYPE_MISCONFIGURED "
5351 "event: Invalid link %d",
5352 phba->sli4_hba.lnk_info.lnk_no);
5353 return;
946727dc 5354 }
4b8bae08 5355
448193b5
JS
5356 /* Skip if optic state unchanged */
5357 if (phba->sli4_hba.lnk_info.optic_state == status)
5358 return;
5359
946727dc
JS
5360 switch (status) {
5361 case LPFC_SLI_EVENT_STATUS_VALID:
448193b5
JS
5362 sprintf(message, "Physical Link is functional");
5363 break;
946727dc
JS
5364 case LPFC_SLI_EVENT_STATUS_NOT_PRESENT:
5365 sprintf(message, "Optics faulted/incorrectly "
5366 "installed/not installed - Reseat optics, "
5367 "if issue not resolved, replace.");
5368 break;
5369 case LPFC_SLI_EVENT_STATUS_WRONG_TYPE:
5370 sprintf(message,
5371 "Optics of two types installed - Remove one "
5372 "optic or install matching pair of optics.");
5373 break;
5374 case LPFC_SLI_EVENT_STATUS_UNSUPPORTED:
5375 sprintf(message, "Incompatible optics - Replace with "
292098be 5376 "compatible optics for card to function.");
946727dc 5377 break;
448193b5
JS
5378 case LPFC_SLI_EVENT_STATUS_UNQUALIFIED:
5379 sprintf(message, "Unqualified optics - Replace with "
5380 "Avago optics for Warranty and Technical "
5381 "Support - Link is%s operational",
2ea259ee 5382 (operational) ? " not" : "");
448193b5
JS
5383 break;
5384 case LPFC_SLI_EVENT_STATUS_UNCERTIFIED:
5385 sprintf(message, "Uncertified optics - Replace with "
5386 "Avago-certified optics to enable link "
5387 "operation - Link is%s operational",
2ea259ee 5388 (operational) ? " not" : "");
448193b5 5389 break;
946727dc
JS
5390 default:
5391 /* firmware is reporting a status we don't know about */
5392 sprintf(message, "Unknown event status x%02x", status);
5393 break;
5394 }
cd71348a
JS
5395
5396 /* Issue READ_CONFIG mbox command to refresh supported speeds */
5397 rc = lpfc_sli4_read_config(phba);
3952e91f 5398 if (rc) {
cd71348a
JS
5399 phba->lmt = 0;
5400 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5401 "3194 Unable to retrieve supported "
3952e91f 5402 "speeds, rc = 0x%x\n", rc);
cd71348a
JS
5403 }
5404 vports = lpfc_create_vport_work_array(phba);
5405 if (vports != NULL) {
5406 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
5407 i++) {
5408 shost = lpfc_shost_from_vport(vports[i]);
5409 lpfc_host_supported_speeds_set(shost);
5410 }
5411 }
5412 lpfc_destroy_vport_work_array(phba, vports);
5413
448193b5 5414 phba->sli4_hba.lnk_info.optic_state = status;
946727dc 5415 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
448193b5 5416 "3176 Port Name %c %s\n", port_name, message);
946727dc
JS
5417 break;
5418 case LPFC_SLI_EVENT_TYPE_REMOTE_DPORT:
5419 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5420 "3192 Remote DPort Test Initiated - "
5421 "Event Data1:x%08x Event Data2: x%08x\n",
5422 acqe_sli->event_data1, acqe_sli->event_data2);
4b8bae08
JS
5423 break;
5424 default:
946727dc
JS
5425 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5426 "3193 Async SLI event - Event Data1:x%08x Event Data2:"
5427 "x%08x SLI Event Type:%d\n",
5428 acqe_sli->event_data1, acqe_sli->event_data2,
5429 evt_type);
4b8bae08
JS
5430 break;
5431 }
70f3c073
JS
5432}
5433
fc2b989b
JS
5434/**
5435 * lpfc_sli4_perform_vport_cvl - Perform clear virtual link on a vport
5436 * @vport: pointer to vport data structure.
5437 *
5438 * This routine is to perform Clear Virtual Link (CVL) on a vport in
5439 * response to a CVL event.
5440 *
5441 * Return the pointer to the ndlp with the vport if successful, otherwise
5442 * return NULL.
5443 **/
5444static struct lpfc_nodelist *
5445lpfc_sli4_perform_vport_cvl(struct lpfc_vport *vport)
5446{
5447 struct lpfc_nodelist *ndlp;
5448 struct Scsi_Host *shost;
5449 struct lpfc_hba *phba;
5450
5451 if (!vport)
5452 return NULL;
fc2b989b
JS
5453 phba = vport->phba;
5454 if (!phba)
5455 return NULL;
78730cfe
JS
5456 ndlp = lpfc_findnode_did(vport, Fabric_DID);
5457 if (!ndlp) {
5458 /* Cannot find existing Fabric ndlp, so allocate a new one */
9d3d340d 5459 ndlp = lpfc_nlp_init(vport, Fabric_DID);
78730cfe
JS
5460 if (!ndlp)
5461 return 0;
78730cfe
JS
5462 /* Set the node type */
5463 ndlp->nlp_type |= NLP_FABRIC;
5464 /* Put ndlp onto node list */
5465 lpfc_enqueue_node(vport, ndlp);
5466 } else if (!NLP_CHK_NODE_ACT(ndlp)) {
5467 /* re-setup ndlp without removing from node list */
5468 ndlp = lpfc_enable_node(vport, ndlp, NLP_STE_UNUSED_NODE);
5469 if (!ndlp)
5470 return 0;
5471 }
63e801ce
JS
5472 if ((phba->pport->port_state < LPFC_FLOGI) &&
5473 (phba->pport->port_state != LPFC_VPORT_FAILED))
fc2b989b
JS
5474 return NULL;
5475 /* If virtual link is not yet instantiated ignore CVL */
63e801ce
JS
5476 if ((vport != phba->pport) && (vport->port_state < LPFC_FDISC)
5477 && (vport->port_state != LPFC_VPORT_FAILED))
fc2b989b
JS
5478 return NULL;
5479 shost = lpfc_shost_from_vport(vport);
5480 if (!shost)
5481 return NULL;
5482 lpfc_linkdown_port(vport);
5483 lpfc_cleanup_pending_mbox(vport);
5484 spin_lock_irq(shost->host_lock);
5485 vport->fc_flag |= FC_VPORT_CVL_RCVD;
5486 spin_unlock_irq(shost->host_lock);
5487
5488 return ndlp;
5489}
5490
5491/**
5492 * lpfc_sli4_perform_all_vport_cvl - Perform clear virtual link on all vports
5493 * @vport: pointer to lpfc hba data structure.
5494 *
5495 * This routine is to perform Clear Virtual Link (CVL) on all vports in
5496 * response to a FCF dead event.
5497 **/
5498static void
5499lpfc_sli4_perform_all_vport_cvl(struct lpfc_hba *phba)
5500{
5501 struct lpfc_vport **vports;
5502 int i;
5503
5504 vports = lpfc_create_vport_work_array(phba);
5505 if (vports)
5506 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
5507 lpfc_sli4_perform_vport_cvl(vports[i]);
5508 lpfc_destroy_vport_work_array(phba, vports);
5509}
5510
da0436e9 5511/**
76a95d75 5512 * lpfc_sli4_async_fip_evt - Process the asynchronous FCoE FIP event
da0436e9
JS
5513 * @phba: pointer to lpfc hba data structure.
5514 * @acqe_link: pointer to the async fcoe completion queue entry.
5515 *
5516 * This routine is to handle the SLI4 asynchronous fcoe event.
5517 **/
5518static void
76a95d75 5519lpfc_sli4_async_fip_evt(struct lpfc_hba *phba,
70f3c073 5520 struct lpfc_acqe_fip *acqe_fip)
da0436e9 5521{
70f3c073 5522 uint8_t event_type = bf_get(lpfc_trailer_type, acqe_fip);
da0436e9 5523 int rc;
6669f9bb
JS
5524 struct lpfc_vport *vport;
5525 struct lpfc_nodelist *ndlp;
5526 struct Scsi_Host *shost;
695a814e
JS
5527 int active_vlink_present;
5528 struct lpfc_vport **vports;
5529 int i;
da0436e9 5530
70f3c073
JS
5531 phba->fc_eventTag = acqe_fip->event_tag;
5532 phba->fcoe_eventtag = acqe_fip->event_tag;
da0436e9 5533 switch (event_type) {
70f3c073
JS
5534 case LPFC_FIP_EVENT_TYPE_NEW_FCF:
5535 case LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD:
5536 if (event_type == LPFC_FIP_EVENT_TYPE_NEW_FCF)
999d813f
JS
5537 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
5538 LOG_DISCOVERY,
a93ff37a
JS
5539 "2546 New FCF event, evt_tag:x%x, "
5540 "index:x%x\n",
70f3c073
JS
5541 acqe_fip->event_tag,
5542 acqe_fip->index);
999d813f
JS
5543 else
5544 lpfc_printf_log(phba, KERN_WARNING, LOG_FIP |
5545 LOG_DISCOVERY,
a93ff37a
JS
5546 "2788 FCF param modified event, "
5547 "evt_tag:x%x, index:x%x\n",
70f3c073
JS
5548 acqe_fip->event_tag,
5549 acqe_fip->index);
38b92ef8 5550 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
0c9ab6f5
JS
5551 /*
5552 * During period of FCF discovery, read the FCF
5553 * table record indexed by the event to update
a93ff37a 5554 * FCF roundrobin failover eligible FCF bmask.
0c9ab6f5
JS
5555 */
5556 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
5557 LOG_DISCOVERY,
a93ff37a
JS
5558 "2779 Read FCF (x%x) for updating "
5559 "roundrobin FCF failover bmask\n",
70f3c073
JS
5560 acqe_fip->index);
5561 rc = lpfc_sli4_read_fcf_rec(phba, acqe_fip->index);
0c9ab6f5 5562 }
38b92ef8
JS
5563
5564 /* If the FCF discovery is in progress, do nothing. */
3804dc84 5565 spin_lock_irq(&phba->hbalock);
a93ff37a 5566 if (phba->hba_flag & FCF_TS_INPROG) {
38b92ef8
JS
5567 spin_unlock_irq(&phba->hbalock);
5568 break;
5569 }
5570 /* If fast FCF failover rescan event is pending, do nothing */
036cad1f 5571 if (phba->fcf.fcf_flag & (FCF_REDISC_EVT | FCF_REDISC_PEND)) {
38b92ef8
JS
5572 spin_unlock_irq(&phba->hbalock);
5573 break;
5574 }
5575
c2b9712e
JS
5576 /* If the FCF has been in discovered state, do nothing. */
5577 if (phba->fcf.fcf_flag & FCF_SCAN_DONE) {
3804dc84
JS
5578 spin_unlock_irq(&phba->hbalock);
5579 break;
5580 }
5581 spin_unlock_irq(&phba->hbalock);
38b92ef8 5582
0c9ab6f5
JS
5583 /* Otherwise, scan the entire FCF table and re-discover SAN */
5584 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
a93ff37a
JS
5585 "2770 Start FCF table scan per async FCF "
5586 "event, evt_tag:x%x, index:x%x\n",
70f3c073 5587 acqe_fip->event_tag, acqe_fip->index);
0c9ab6f5
JS
5588 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba,
5589 LPFC_FCOE_FCF_GET_FIRST);
da0436e9 5590 if (rc)
0c9ab6f5
JS
5591 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
5592 "2547 Issue FCF scan read FCF mailbox "
a93ff37a 5593 "command failed (x%x)\n", rc);
da0436e9
JS
5594 break;
5595
70f3c073 5596 case LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL:
da0436e9 5597 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
e4e74273 5598 "2548 FCF Table full count 0x%x tag 0x%x\n",
70f3c073
JS
5599 bf_get(lpfc_acqe_fip_fcf_count, acqe_fip),
5600 acqe_fip->event_tag);
da0436e9
JS
5601 break;
5602
70f3c073 5603 case LPFC_FIP_EVENT_TYPE_FCF_DEAD:
80c17849 5604 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
0c9ab6f5 5605 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
a93ff37a 5606 "2549 FCF (x%x) disconnected from network, "
70f3c073 5607 "tag:x%x\n", acqe_fip->index, acqe_fip->event_tag);
38b92ef8
JS
5608 /*
5609 * If we are in the middle of FCF failover process, clear
5610 * the corresponding FCF bit in the roundrobin bitmap.
da0436e9 5611 */
fc2b989b 5612 spin_lock_irq(&phba->hbalock);
a1cadfef
JS
5613 if ((phba->fcf.fcf_flag & FCF_DISCOVERY) &&
5614 (phba->fcf.current_rec.fcf_indx != acqe_fip->index)) {
fc2b989b 5615 spin_unlock_irq(&phba->hbalock);
0c9ab6f5 5616 /* Update FLOGI FCF failover eligible FCF bmask */
70f3c073 5617 lpfc_sli4_fcf_rr_index_clear(phba, acqe_fip->index);
fc2b989b
JS
5618 break;
5619 }
38b92ef8
JS
5620 spin_unlock_irq(&phba->hbalock);
5621
5622 /* If the event is not for currently used fcf do nothing */
70f3c073 5623 if (phba->fcf.current_rec.fcf_indx != acqe_fip->index)
38b92ef8
JS
5624 break;
5625
5626 /*
5627 * Otherwise, request the port to rediscover the entire FCF
5628 * table for a fast recovery from case that the current FCF
5629 * is no longer valid as we are not in the middle of FCF
5630 * failover process already.
5631 */
c2b9712e
JS
5632 spin_lock_irq(&phba->hbalock);
5633 /* Mark the fast failover process in progress */
5634 phba->fcf.fcf_flag |= FCF_DEAD_DISC;
5635 spin_unlock_irq(&phba->hbalock);
5636
5637 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
5638 "2771 Start FCF fast failover process due to "
5639 "FCF DEAD event: evt_tag:x%x, fcf_index:x%x "
5640 "\n", acqe_fip->event_tag, acqe_fip->index);
5641 rc = lpfc_sli4_redisc_fcf_table(phba);
5642 if (rc) {
5643 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
5644 LOG_DISCOVERY,
7afc0ce9 5645 "2772 Issue FCF rediscover mailbox "
c2b9712e
JS
5646 "command failed, fail through to FCF "
5647 "dead event\n");
5648 spin_lock_irq(&phba->hbalock);
5649 phba->fcf.fcf_flag &= ~FCF_DEAD_DISC;
5650 spin_unlock_irq(&phba->hbalock);
5651 /*
5652 * Last resort will fail over by treating this
5653 * as a link down to FCF registration.
5654 */
5655 lpfc_sli4_fcf_dead_failthrough(phba);
5656 } else {
5657 /* Reset FCF roundrobin bmask for new discovery */
5658 lpfc_sli4_clear_fcf_rr_bmask(phba);
5659 /*
5660 * Handling fast FCF failover to a DEAD FCF event is
5661 * considered equalivant to receiving CVL to all vports.
5662 */
5663 lpfc_sli4_perform_all_vport_cvl(phba);
5664 }
da0436e9 5665 break;
70f3c073 5666 case LPFC_FIP_EVENT_TYPE_CVL:
80c17849 5667 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
0c9ab6f5 5668 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
6669f9bb 5669 "2718 Clear Virtual Link Received for VPI 0x%x"
70f3c073 5670 " tag 0x%x\n", acqe_fip->index, acqe_fip->event_tag);
6d368e53 5671
6669f9bb 5672 vport = lpfc_find_vport_by_vpid(phba,
5248a749 5673 acqe_fip->index);
fc2b989b 5674 ndlp = lpfc_sli4_perform_vport_cvl(vport);
6669f9bb
JS
5675 if (!ndlp)
5676 break;
695a814e
JS
5677 active_vlink_present = 0;
5678
5679 vports = lpfc_create_vport_work_array(phba);
5680 if (vports) {
5681 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
5682 i++) {
5683 if ((!(vports[i]->fc_flag &
5684 FC_VPORT_CVL_RCVD)) &&
5685 (vports[i]->port_state > LPFC_FDISC)) {
5686 active_vlink_present = 1;
5687 break;
5688 }
5689 }
5690 lpfc_destroy_vport_work_array(phba, vports);
5691 }
5692
cc82355a
JS
5693 /*
5694 * Don't re-instantiate if vport is marked for deletion.
5695 * If we are here first then vport_delete is going to wait
5696 * for discovery to complete.
5697 */
5698 if (!(vport->load_flag & FC_UNLOADING) &&
5699 active_vlink_present) {
695a814e
JS
5700 /*
5701 * If there are other active VLinks present,
5702 * re-instantiate the Vlink using FDISC.
5703 */
256ec0d0
JS
5704 mod_timer(&ndlp->nlp_delayfunc,
5705 jiffies + msecs_to_jiffies(1000));
fc2b989b 5706 shost = lpfc_shost_from_vport(vport);
6669f9bb
JS
5707 spin_lock_irq(shost->host_lock);
5708 ndlp->nlp_flag |= NLP_DELAY_TMO;
5709 spin_unlock_irq(shost->host_lock);
695a814e
JS
5710 ndlp->nlp_last_elscmd = ELS_CMD_FDISC;
5711 vport->port_state = LPFC_FDISC;
5712 } else {
ecfd03c6
JS
5713 /*
5714 * Otherwise, we request port to rediscover
5715 * the entire FCF table for a fast recovery
5716 * from possible case that the current FCF
0c9ab6f5
JS
5717 * is no longer valid if we are not already
5718 * in the FCF failover process.
ecfd03c6 5719 */
fc2b989b 5720 spin_lock_irq(&phba->hbalock);
0c9ab6f5 5721 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
fc2b989b
JS
5722 spin_unlock_irq(&phba->hbalock);
5723 break;
5724 }
5725 /* Mark the fast failover process in progress */
0c9ab6f5 5726 phba->fcf.fcf_flag |= FCF_ACVL_DISC;
fc2b989b 5727 spin_unlock_irq(&phba->hbalock);
0c9ab6f5
JS
5728 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
5729 LOG_DISCOVERY,
a93ff37a 5730 "2773 Start FCF failover per CVL, "
70f3c073 5731 "evt_tag:x%x\n", acqe_fip->event_tag);
ecfd03c6 5732 rc = lpfc_sli4_redisc_fcf_table(phba);
fc2b989b 5733 if (rc) {
0c9ab6f5
JS
5734 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
5735 LOG_DISCOVERY,
5736 "2774 Issue FCF rediscover "
7afc0ce9 5737 "mailbox command failed, "
0c9ab6f5 5738 "through to CVL event\n");
fc2b989b 5739 spin_lock_irq(&phba->hbalock);
0c9ab6f5 5740 phba->fcf.fcf_flag &= ~FCF_ACVL_DISC;
fc2b989b 5741 spin_unlock_irq(&phba->hbalock);
ecfd03c6
JS
5742 /*
5743 * Last resort will be re-try on the
5744 * the current registered FCF entry.
5745 */
5746 lpfc_retry_pport_discovery(phba);
38b92ef8
JS
5747 } else
5748 /*
5749 * Reset FCF roundrobin bmask for new
5750 * discovery.
5751 */
7d791df7 5752 lpfc_sli4_clear_fcf_rr_bmask(phba);
6669f9bb
JS
5753 }
5754 break;
da0436e9
JS
5755 default:
5756 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5757 "0288 Unknown FCoE event type 0x%x event tag "
70f3c073 5758 "0x%x\n", event_type, acqe_fip->event_tag);
da0436e9
JS
5759 break;
5760 }
5761}
5762
5763/**
5764 * lpfc_sli4_async_dcbx_evt - Process the asynchronous dcbx event
5765 * @phba: pointer to lpfc hba data structure.
5766 * @acqe_link: pointer to the async dcbx completion queue entry.
5767 *
5768 * This routine is to handle the SLI4 asynchronous dcbx event.
5769 **/
5770static void
5771lpfc_sli4_async_dcbx_evt(struct lpfc_hba *phba,
5772 struct lpfc_acqe_dcbx *acqe_dcbx)
5773{
4d9ab994 5774 phba->fc_eventTag = acqe_dcbx->event_tag;
da0436e9
JS
5775 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5776 "0290 The SLI4 DCBX asynchronous event is not "
5777 "handled yet\n");
5778}
5779
b19a061a
JS
5780/**
5781 * lpfc_sli4_async_grp5_evt - Process the asynchronous group5 event
5782 * @phba: pointer to lpfc hba data structure.
5783 * @acqe_link: pointer to the async grp5 completion queue entry.
5784 *
5785 * This routine is to handle the SLI4 asynchronous grp5 event. A grp5 event
5786 * is an asynchronous notified of a logical link speed change. The Port
5787 * reports the logical link speed in units of 10Mbps.
5788 **/
5789static void
5790lpfc_sli4_async_grp5_evt(struct lpfc_hba *phba,
5791 struct lpfc_acqe_grp5 *acqe_grp5)
5792{
5793 uint16_t prev_ll_spd;
5794
5795 phba->fc_eventTag = acqe_grp5->event_tag;
5796 phba->fcoe_eventtag = acqe_grp5->event_tag;
5797 prev_ll_spd = phba->sli4_hba.link_state.logical_speed;
5798 phba->sli4_hba.link_state.logical_speed =
8b68cd52 5799 (bf_get(lpfc_acqe_grp5_llink_spd, acqe_grp5)) * 10;
b19a061a
JS
5800 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5801 "2789 GRP5 Async Event: Updating logical link speed "
8b68cd52
JS
5802 "from %dMbps to %dMbps\n", prev_ll_spd,
5803 phba->sli4_hba.link_state.logical_speed);
b19a061a
JS
5804}
5805
da0436e9
JS
5806/**
5807 * lpfc_sli4_async_event_proc - Process all the pending asynchronous event
5808 * @phba: pointer to lpfc hba data structure.
5809 *
5810 * This routine is invoked by the worker thread to process all the pending
5811 * SLI4 asynchronous events.
5812 **/
5813void lpfc_sli4_async_event_proc(struct lpfc_hba *phba)
5814{
5815 struct lpfc_cq_event *cq_event;
5816
5817 /* First, declare the async event has been handled */
5818 spin_lock_irq(&phba->hbalock);
5819 phba->hba_flag &= ~ASYNC_EVENT;
5820 spin_unlock_irq(&phba->hbalock);
5821 /* Now, handle all the async events */
5822 while (!list_empty(&phba->sli4_hba.sp_asynce_work_queue)) {
5823 /* Get the first event from the head of the event queue */
5824 spin_lock_irq(&phba->hbalock);
5825 list_remove_head(&phba->sli4_hba.sp_asynce_work_queue,
5826 cq_event, struct lpfc_cq_event, list);
5827 spin_unlock_irq(&phba->hbalock);
5828 /* Process the asynchronous event */
5829 switch (bf_get(lpfc_trailer_code, &cq_event->cqe.mcqe_cmpl)) {
5830 case LPFC_TRAILER_CODE_LINK:
5831 lpfc_sli4_async_link_evt(phba,
5832 &cq_event->cqe.acqe_link);
5833 break;
5834 case LPFC_TRAILER_CODE_FCOE:
70f3c073 5835 lpfc_sli4_async_fip_evt(phba, &cq_event->cqe.acqe_fip);
da0436e9
JS
5836 break;
5837 case LPFC_TRAILER_CODE_DCBX:
5838 lpfc_sli4_async_dcbx_evt(phba,
5839 &cq_event->cqe.acqe_dcbx);
5840 break;
b19a061a
JS
5841 case LPFC_TRAILER_CODE_GRP5:
5842 lpfc_sli4_async_grp5_evt(phba,
5843 &cq_event->cqe.acqe_grp5);
5844 break;
70f3c073
JS
5845 case LPFC_TRAILER_CODE_FC:
5846 lpfc_sli4_async_fc_evt(phba, &cq_event->cqe.acqe_fc);
5847 break;
5848 case LPFC_TRAILER_CODE_SLI:
5849 lpfc_sli4_async_sli_evt(phba, &cq_event->cqe.acqe_sli);
5850 break;
da0436e9
JS
5851 default:
5852 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5853 "1804 Invalid asynchrous event code: "
5854 "x%x\n", bf_get(lpfc_trailer_code,
5855 &cq_event->cqe.mcqe_cmpl));
5856 break;
5857 }
5858 /* Free the completion event processed to the free pool */
5859 lpfc_sli4_cq_event_release(phba, cq_event);
5860 }
5861}
5862
ecfd03c6
JS
5863/**
5864 * lpfc_sli4_fcf_redisc_event_proc - Process fcf table rediscovery event
5865 * @phba: pointer to lpfc hba data structure.
5866 *
5867 * This routine is invoked by the worker thread to process FCF table
5868 * rediscovery pending completion event.
5869 **/
5870void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *phba)
5871{
5872 int rc;
5873
5874 spin_lock_irq(&phba->hbalock);
5875 /* Clear FCF rediscovery timeout event */
5876 phba->fcf.fcf_flag &= ~FCF_REDISC_EVT;
5877 /* Clear driver fast failover FCF record flag */
5878 phba->fcf.failover_rec.flag = 0;
5879 /* Set state for FCF fast failover */
5880 phba->fcf.fcf_flag |= FCF_REDISC_FOV;
5881 spin_unlock_irq(&phba->hbalock);
5882
5883 /* Scan FCF table from the first entry to re-discover SAN */
0c9ab6f5 5884 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
a93ff37a 5885 "2777 Start post-quiescent FCF table scan\n");
0c9ab6f5 5886 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba, LPFC_FCOE_FCF_GET_FIRST);
ecfd03c6 5887 if (rc)
0c9ab6f5
JS
5888 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
5889 "2747 Issue FCF scan read FCF mailbox "
5890 "command failed 0x%x\n", rc);
ecfd03c6
JS
5891}
5892
da0436e9
JS
5893/**
5894 * lpfc_api_table_setup - Set up per hba pci-device group func api jump table
5895 * @phba: pointer to lpfc hba data structure.
5896 * @dev_grp: The HBA PCI-Device group number.
5897 *
5898 * This routine is invoked to set up the per HBA PCI-Device group function
5899 * API jump table entries.
5900 *
5901 * Return: 0 if success, otherwise -ENODEV
5902 **/
5903int
5904lpfc_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
5905{
5906 int rc;
5907
5908 /* Set up lpfc PCI-device group */
5909 phba->pci_dev_grp = dev_grp;
5910
5911 /* The LPFC_PCI_DEV_OC uses SLI4 */
5912 if (dev_grp == LPFC_PCI_DEV_OC)
5913 phba->sli_rev = LPFC_SLI_REV4;
5914
5915 /* Set up device INIT API function jump table */
5916 rc = lpfc_init_api_table_setup(phba, dev_grp);
5917 if (rc)
5918 return -ENODEV;
5919 /* Set up SCSI API function jump table */
5920 rc = lpfc_scsi_api_table_setup(phba, dev_grp);
5921 if (rc)
5922 return -ENODEV;
5923 /* Set up SLI API function jump table */
5924 rc = lpfc_sli_api_table_setup(phba, dev_grp);
5925 if (rc)
5926 return -ENODEV;
5927 /* Set up MBOX API function jump table */
5928 rc = lpfc_mbox_api_table_setup(phba, dev_grp);
5929 if (rc)
5930 return -ENODEV;
5931
5932 return 0;
5b75da2f
JS
5933}
5934
5935/**
3621a710 5936 * lpfc_log_intr_mode - Log the active interrupt mode
5b75da2f
JS
5937 * @phba: pointer to lpfc hba data structure.
5938 * @intr_mode: active interrupt mode adopted.
5939 *
5940 * This routine it invoked to log the currently used active interrupt mode
5941 * to the device.
3772a991
JS
5942 **/
5943static void lpfc_log_intr_mode(struct lpfc_hba *phba, uint32_t intr_mode)
5b75da2f
JS
5944{
5945 switch (intr_mode) {
5946 case 0:
5947 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
5948 "0470 Enable INTx interrupt mode.\n");
5949 break;
5950 case 1:
5951 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
5952 "0481 Enabled MSI interrupt mode.\n");
5953 break;
5954 case 2:
5955 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
5956 "0480 Enabled MSI-X interrupt mode.\n");
5957 break;
5958 default:
5959 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5960 "0482 Illegal interrupt mode.\n");
5961 break;
5962 }
5963 return;
5964}
5965
5b75da2f 5966/**
3772a991 5967 * lpfc_enable_pci_dev - Enable a generic PCI device.
5b75da2f
JS
5968 * @phba: pointer to lpfc hba data structure.
5969 *
3772a991
JS
5970 * This routine is invoked to enable the PCI device that is common to all
5971 * PCI devices.
5b75da2f
JS
5972 *
5973 * Return codes
af901ca1 5974 * 0 - successful
3772a991 5975 * other values - error
5b75da2f 5976 **/
3772a991
JS
5977static int
5978lpfc_enable_pci_dev(struct lpfc_hba *phba)
5b75da2f 5979{
3772a991 5980 struct pci_dev *pdev;
5b75da2f 5981
3772a991
JS
5982 /* Obtain PCI device reference */
5983 if (!phba->pcidev)
5984 goto out_error;
5985 else
5986 pdev = phba->pcidev;
3772a991
JS
5987 /* Enable PCI device */
5988 if (pci_enable_device_mem(pdev))
5989 goto out_error;
5990 /* Request PCI resource for the device */
e0c0483c 5991 if (pci_request_mem_regions(pdev, LPFC_DRIVER_NAME))
3772a991
JS
5992 goto out_disable_device;
5993 /* Set up device as PCI master and save state for EEH */
5994 pci_set_master(pdev);
5995 pci_try_set_mwi(pdev);
5996 pci_save_state(pdev);
5b75da2f 5997
0558056c 5998 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
453193e0 5999 if (pci_is_pcie(pdev))
0558056c
JS
6000 pdev->needs_freset = 1;
6001
3772a991 6002 return 0;
5b75da2f 6003
3772a991
JS
6004out_disable_device:
6005 pci_disable_device(pdev);
6006out_error:
079b5c91 6007 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e0c0483c 6008 "1401 Failed to enable pci device\n");
3772a991 6009 return -ENODEV;
5b75da2f
JS
6010}
6011
6012/**
3772a991 6013 * lpfc_disable_pci_dev - Disable a generic PCI device.
5b75da2f
JS
6014 * @phba: pointer to lpfc hba data structure.
6015 *
3772a991
JS
6016 * This routine is invoked to disable the PCI device that is common to all
6017 * PCI devices.
5b75da2f
JS
6018 **/
6019static void
3772a991 6020lpfc_disable_pci_dev(struct lpfc_hba *phba)
5b75da2f 6021{
3772a991 6022 struct pci_dev *pdev;
5b75da2f 6023
3772a991
JS
6024 /* Obtain PCI device reference */
6025 if (!phba->pcidev)
6026 return;
6027 else
6028 pdev = phba->pcidev;
3772a991 6029 /* Release PCI resource and disable PCI device */
e0c0483c 6030 pci_release_mem_regions(pdev);
3772a991 6031 pci_disable_device(pdev);
5b75da2f
JS
6032
6033 return;
6034}
6035
e59058c4 6036/**
3772a991
JS
6037 * lpfc_reset_hba - Reset a hba
6038 * @phba: pointer to lpfc hba data structure.
e59058c4 6039 *
3772a991
JS
6040 * This routine is invoked to reset a hba device. It brings the HBA
6041 * offline, performs a board restart, and then brings the board back
6042 * online. The lpfc_offline calls lpfc_sli_hba_down which will clean up
6043 * on outstanding mailbox commands.
e59058c4 6044 **/
3772a991
JS
6045void
6046lpfc_reset_hba(struct lpfc_hba *phba)
dea3101e 6047{
3772a991
JS
6048 /* If resets are disabled then set error state and return. */
6049 if (!phba->cfg_enable_hba_reset) {
6050 phba->link_state = LPFC_HBA_ERROR;
6051 return;
6052 }
ee62021a
JS
6053 if (phba->sli.sli_flag & LPFC_SLI_ACTIVE)
6054 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
6055 else
6056 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
3772a991
JS
6057 lpfc_offline(phba);
6058 lpfc_sli_brdrestart(phba);
6059 lpfc_online(phba);
6060 lpfc_unblock_mgmt_io(phba);
6061}
dea3101e 6062
0a96e975
JS
6063/**
6064 * lpfc_sli_sriov_nr_virtfn_get - Get the number of sr-iov virtual functions
6065 * @phba: pointer to lpfc hba data structure.
6066 *
6067 * This function enables the PCI SR-IOV virtual functions to a physical
6068 * function. It invokes the PCI SR-IOV api with the @nr_vfn provided to
6069 * enable the number of virtual functions to the physical function. As
6070 * not all devices support SR-IOV, the return code from the pci_enable_sriov()
6071 * API call does not considered as an error condition for most of the device.
6072 **/
6073uint16_t
6074lpfc_sli_sriov_nr_virtfn_get(struct lpfc_hba *phba)
6075{
6076 struct pci_dev *pdev = phba->pcidev;
6077 uint16_t nr_virtfn;
6078 int pos;
6079
0a96e975
JS
6080 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6081 if (pos == 0)
6082 return 0;
6083
6084 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, &nr_virtfn);
6085 return nr_virtfn;
6086}
6087
912e3acd
JS
6088/**
6089 * lpfc_sli_probe_sriov_nr_virtfn - Enable a number of sr-iov virtual functions
6090 * @phba: pointer to lpfc hba data structure.
6091 * @nr_vfn: number of virtual functions to be enabled.
6092 *
6093 * This function enables the PCI SR-IOV virtual functions to a physical
6094 * function. It invokes the PCI SR-IOV api with the @nr_vfn provided to
6095 * enable the number of virtual functions to the physical function. As
6096 * not all devices support SR-IOV, the return code from the pci_enable_sriov()
6097 * API call does not considered as an error condition for most of the device.
6098 **/
6099int
6100lpfc_sli_probe_sriov_nr_virtfn(struct lpfc_hba *phba, int nr_vfn)
6101{
6102 struct pci_dev *pdev = phba->pcidev;
0a96e975 6103 uint16_t max_nr_vfn;
912e3acd
JS
6104 int rc;
6105
0a96e975
JS
6106 max_nr_vfn = lpfc_sli_sriov_nr_virtfn_get(phba);
6107 if (nr_vfn > max_nr_vfn) {
6108 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6109 "3057 Requested vfs (%d) greater than "
6110 "supported vfs (%d)", nr_vfn, max_nr_vfn);
6111 return -EINVAL;
6112 }
6113
912e3acd
JS
6114 rc = pci_enable_sriov(pdev, nr_vfn);
6115 if (rc) {
6116 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6117 "2806 Failed to enable sriov on this device "
6118 "with vfn number nr_vf:%d, rc:%d\n",
6119 nr_vfn, rc);
6120 } else
6121 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6122 "2807 Successful enable sriov on this device "
6123 "with vfn number nr_vf:%d\n", nr_vfn);
6124 return rc;
6125}
6126
3772a991 6127/**
895427bd 6128 * lpfc_setup_driver_resource_phase1 - Phase1 etup driver internal resources.
3772a991
JS
6129 * @phba: pointer to lpfc hba data structure.
6130 *
895427bd
JS
6131 * This routine is invoked to set up the driver internal resources before the
6132 * device specific resource setup to support the HBA device it attached to.
3772a991
JS
6133 *
6134 * Return codes
895427bd
JS
6135 * 0 - successful
6136 * other values - error
3772a991
JS
6137 **/
6138static int
895427bd 6139lpfc_setup_driver_resource_phase1(struct lpfc_hba *phba)
3772a991 6140{
895427bd 6141 struct lpfc_sli *psli = &phba->sli;
dea3101e 6142
2e0fef85 6143 /*
895427bd 6144 * Driver resources common to all SLI revisions
2e0fef85 6145 */
895427bd
JS
6146 atomic_set(&phba->fast_event_count, 0);
6147 spin_lock_init(&phba->hbalock);
dea3101e 6148
895427bd
JS
6149 /* Initialize ndlp management spinlock */
6150 spin_lock_init(&phba->ndlp_lock);
6151
523128e5
JS
6152 /* Initialize port_list spinlock */
6153 spin_lock_init(&phba->port_list_lock);
895427bd 6154 INIT_LIST_HEAD(&phba->port_list);
523128e5 6155
895427bd
JS
6156 INIT_LIST_HEAD(&phba->work_list);
6157 init_waitqueue_head(&phba->wait_4_mlo_m_q);
6158
6159 /* Initialize the wait queue head for the kernel thread */
6160 init_waitqueue_head(&phba->work_waitq);
6161
6162 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
f358dd0c 6163 "1403 Protocols supported %s %s %s\n",
895427bd
JS
6164 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) ?
6165 "SCSI" : " "),
6166 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) ?
f358dd0c
JS
6167 "NVME" : " "),
6168 (phba->nvmet_support ? "NVMET" : " "));
895427bd 6169
0794d601
JS
6170 /* Initialize the IO buffer list used by driver for SLI3 SCSI */
6171 spin_lock_init(&phba->scsi_buf_list_get_lock);
6172 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_get);
6173 spin_lock_init(&phba->scsi_buf_list_put_lock);
6174 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_put);
895427bd
JS
6175
6176 /* Initialize the fabric iocb list */
6177 INIT_LIST_HEAD(&phba->fabric_iocb_list);
6178
6179 /* Initialize list to save ELS buffers */
6180 INIT_LIST_HEAD(&phba->elsbuf);
6181
6182 /* Initialize FCF connection rec list */
6183 INIT_LIST_HEAD(&phba->fcf_conn_rec_list);
6184
6185 /* Initialize OAS configuration list */
6186 spin_lock_init(&phba->devicelock);
6187 INIT_LIST_HEAD(&phba->luns);
858c9f6c 6188
3772a991 6189 /* MBOX heartbeat timer */
f22eb4d3 6190 timer_setup(&psli->mbox_tmo, lpfc_mbox_timeout, 0);
3772a991 6191 /* Fabric block timer */
f22eb4d3 6192 timer_setup(&phba->fabric_block_timer, lpfc_fabric_block_timeout, 0);
3772a991 6193 /* EA polling mode timer */
f22eb4d3 6194 timer_setup(&phba->eratt_poll, lpfc_poll_eratt, 0);
895427bd 6195 /* Heartbeat timer */
f22eb4d3 6196 timer_setup(&phba->hb_tmofunc, lpfc_hb_timeout, 0);
895427bd 6197
32517fc0
JS
6198 INIT_DELAYED_WORK(&phba->eq_delay_work, lpfc_hb_eq_delay_work);
6199
895427bd
JS
6200 return 0;
6201}
6202
6203/**
6204 * lpfc_sli_driver_resource_setup - Setup driver internal resources for SLI3 dev
6205 * @phba: pointer to lpfc hba data structure.
6206 *
6207 * This routine is invoked to set up the driver internal resources specific to
6208 * support the SLI-3 HBA device it attached to.
6209 *
6210 * Return codes
6211 * 0 - successful
6212 * other values - error
6213 **/
6214static int
6215lpfc_sli_driver_resource_setup(struct lpfc_hba *phba)
6216{
0794d601 6217 int rc, entry_sz;
895427bd
JS
6218
6219 /*
6220 * Initialize timers used by driver
6221 */
6222
6223 /* FCP polling mode timer */
f22eb4d3 6224 timer_setup(&phba->fcp_poll_timer, lpfc_poll_timeout, 0);
dea3101e 6225
3772a991
JS
6226 /* Host attention work mask setup */
6227 phba->work_ha_mask = (HA_ERATT | HA_MBATT | HA_LATT);
6228 phba->work_ha_mask |= (HA_RXMASK << (LPFC_ELS_RING * 4));
dea3101e 6229
3772a991
JS
6230 /* Get all the module params for configuring this host */
6231 lpfc_get_cfgparam(phba);
895427bd
JS
6232 /* Set up phase-1 common device driver resources */
6233
6234 rc = lpfc_setup_driver_resource_phase1(phba);
6235 if (rc)
6236 return -ENODEV;
6237
49198b37
JS
6238 if (phba->pcidev->device == PCI_DEVICE_ID_HORNET) {
6239 phba->menlo_flag |= HBA_MENLO_SUPPORT;
6240 /* check for menlo minimum sg count */
6241 if (phba->cfg_sg_seg_cnt < LPFC_DEFAULT_MENLO_SG_SEG_CNT)
6242 phba->cfg_sg_seg_cnt = LPFC_DEFAULT_MENLO_SG_SEG_CNT;
6243 }
6244
895427bd 6245 if (!phba->sli.sli3_ring)
6396bb22
KC
6246 phba->sli.sli3_ring = kcalloc(LPFC_SLI3_MAX_RING,
6247 sizeof(struct lpfc_sli_ring),
6248 GFP_KERNEL);
895427bd 6249 if (!phba->sli.sli3_ring)
2a76a283
JS
6250 return -ENOMEM;
6251
dea3101e 6252 /*
96f7077f 6253 * Since lpfc_sg_seg_cnt is module parameter, the sg_dma_buf_size
3772a991 6254 * used to create the sg_dma_buf_pool must be dynamically calculated.
dea3101e 6255 */
3772a991 6256
96f7077f
JS
6257 /* Initialize the host templates the configured values. */
6258 lpfc_vport_template.sg_tablesize = phba->cfg_sg_seg_cnt;
96418b5e
JS
6259 lpfc_template_no_hr.sg_tablesize = phba->cfg_sg_seg_cnt;
6260 lpfc_template.sg_tablesize = phba->cfg_sg_seg_cnt;
96f7077f 6261
0794d601
JS
6262 if (phba->sli_rev == LPFC_SLI_REV4)
6263 entry_sz = sizeof(struct sli4_sge);
6264 else
6265 entry_sz = sizeof(struct ulp_bde64);
6266
96f7077f 6267 /* There are going to be 2 reserved BDEs: 1 FCP cmnd + 1 FCP rsp */
3772a991 6268 if (phba->cfg_enable_bg) {
96f7077f
JS
6269 /*
6270 * The scsi_buf for a T10-DIF I/O will hold the FCP cmnd,
6271 * the FCP rsp, and a BDE for each. Sice we have no control
6272 * over how many protection data segments the SCSI Layer
6273 * will hand us (ie: there could be one for every block
6274 * in the IO), we just allocate enough BDEs to accomidate
6275 * our max amount and we need to limit lpfc_sg_seg_cnt to
6276 * minimize the risk of running out.
6277 */
6278 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6279 sizeof(struct fcp_rsp) +
0794d601 6280 (LPFC_MAX_SG_SEG_CNT * entry_sz);
96f7077f
JS
6281
6282 if (phba->cfg_sg_seg_cnt > LPFC_MAX_SG_SEG_CNT_DIF)
6283 phba->cfg_sg_seg_cnt = LPFC_MAX_SG_SEG_CNT_DIF;
6284
6285 /* Total BDEs in BPL for scsi_sg_list and scsi_sg_prot_list */
6286 phba->cfg_total_seg_cnt = LPFC_MAX_SG_SEG_CNT;
6287 } else {
6288 /*
6289 * The scsi_buf for a regular I/O will hold the FCP cmnd,
6290 * the FCP rsp, a BDE for each, and a BDE for up to
6291 * cfg_sg_seg_cnt data segments.
6292 */
6293 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6294 sizeof(struct fcp_rsp) +
0794d601 6295 ((phba->cfg_sg_seg_cnt + 2) * entry_sz);
96f7077f
JS
6296
6297 /* Total BDEs in BPL for scsi_sg_list */
6298 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + 2;
901a920f 6299 }
dea3101e 6300
96f7077f
JS
6301 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
6302 "9088 sg_tablesize:%d dmabuf_size:%d total_bde:%d\n",
6303 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
6304 phba->cfg_total_seg_cnt);
dea3101e 6305
3772a991
JS
6306 phba->max_vpi = LPFC_MAX_VPI;
6307 /* This will be set to correct value after config_port mbox */
6308 phba->max_vports = 0;
dea3101e 6309
3772a991
JS
6310 /*
6311 * Initialize the SLI Layer to run with lpfc HBAs.
6312 */
6313 lpfc_sli_setup(phba);
895427bd 6314 lpfc_sli_queue_init(phba);
ed957684 6315
3772a991
JS
6316 /* Allocate device driver memory */
6317 if (lpfc_mem_alloc(phba, BPL_ALIGN_SZ))
6318 return -ENOMEM;
51ef4c26 6319
912e3acd
JS
6320 /*
6321 * Enable sr-iov virtual functions if supported and configured
6322 * through the module parameter.
6323 */
6324 if (phba->cfg_sriov_nr_virtfn > 0) {
6325 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
6326 phba->cfg_sriov_nr_virtfn);
6327 if (rc) {
6328 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6329 "2808 Requested number of SR-IOV "
6330 "virtual functions (%d) is not "
6331 "supported\n",
6332 phba->cfg_sriov_nr_virtfn);
6333 phba->cfg_sriov_nr_virtfn = 0;
6334 }
6335 }
6336
3772a991
JS
6337 return 0;
6338}
ed957684 6339
3772a991
JS
6340/**
6341 * lpfc_sli_driver_resource_unset - Unset drvr internal resources for SLI3 dev
6342 * @phba: pointer to lpfc hba data structure.
6343 *
6344 * This routine is invoked to unset the driver internal resources set up
6345 * specific for supporting the SLI-3 HBA device it attached to.
6346 **/
6347static void
6348lpfc_sli_driver_resource_unset(struct lpfc_hba *phba)
6349{
6350 /* Free device driver memory allocated */
6351 lpfc_mem_free_all(phba);
3163f725 6352
3772a991
JS
6353 return;
6354}
dea3101e 6355
3772a991 6356/**
da0436e9 6357 * lpfc_sli4_driver_resource_setup - Setup drvr internal resources for SLI4 dev
3772a991
JS
6358 * @phba: pointer to lpfc hba data structure.
6359 *
da0436e9
JS
6360 * This routine is invoked to set up the driver internal resources specific to
6361 * support the SLI-4 HBA device it attached to.
3772a991
JS
6362 *
6363 * Return codes
af901ca1 6364 * 0 - successful
da0436e9 6365 * other values - error
3772a991
JS
6366 **/
6367static int
da0436e9 6368lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba)
3772a991 6369{
28baac74 6370 LPFC_MBOXQ_t *mboxq;
f358dd0c 6371 MAILBOX_t *mb;
895427bd 6372 int rc, i, max_buf_size;
28baac74
JS
6373 uint8_t pn_page[LPFC_MAX_SUPPORTED_PAGES] = {0};
6374 struct lpfc_mqe *mqe;
09294d46 6375 int longs;
81e6a637 6376 int extra;
f358dd0c 6377 uint64_t wwn;
b92dc72d
JS
6378 u32 if_type;
6379 u32 if_fam;
da0436e9 6380
895427bd 6381 phba->sli4_hba.num_present_cpu = lpfc_present_cpu;
222e9239 6382 phba->sli4_hba.num_possible_cpu = num_possible_cpus();
895427bd
JS
6383 phba->sli4_hba.curr_disp_cpu = 0;
6384
716d3bc5
JS
6385 /* Get all the module params for configuring this host */
6386 lpfc_get_cfgparam(phba);
6387
895427bd
JS
6388 /* Set up phase-1 common device driver resources */
6389 rc = lpfc_setup_driver_resource_phase1(phba);
6390 if (rc)
6391 return -ENODEV;
6392
da0436e9
JS
6393 /* Before proceed, wait for POST done and device ready */
6394 rc = lpfc_sli4_post_status_check(phba);
6395 if (rc)
6396 return -ENODEV;
6397
3772a991 6398 /*
da0436e9 6399 * Initialize timers used by driver
3772a991 6400 */
3772a991 6401
f22eb4d3 6402 timer_setup(&phba->rrq_tmr, lpfc_rrq_timeout, 0);
3772a991 6403
ecfd03c6 6404 /* FCF rediscover timer */
f22eb4d3 6405 timer_setup(&phba->fcf.redisc_wait, lpfc_sli4_fcf_redisc_wait_tmo, 0);
ecfd03c6 6406
7ad20aa9
JS
6407 /*
6408 * Control structure for handling external multi-buffer mailbox
6409 * command pass-through.
6410 */
6411 memset((uint8_t *)&phba->mbox_ext_buf_ctx, 0,
6412 sizeof(struct lpfc_mbox_ext_buf_ctx));
6413 INIT_LIST_HEAD(&phba->mbox_ext_buf_ctx.ext_dmabuf_list);
6414
da0436e9 6415 phba->max_vpi = LPFC_MAX_VPI;
67d12733 6416
da0436e9
JS
6417 /* This will be set to correct value after the read_config mbox */
6418 phba->max_vports = 0;
3772a991 6419
da0436e9
JS
6420 /* Program the default value of vlan_id and fc_map */
6421 phba->valid_vlan = 0;
6422 phba->fc_map[0] = LPFC_FCOE_FCF_MAP0;
6423 phba->fc_map[1] = LPFC_FCOE_FCF_MAP1;
6424 phba->fc_map[2] = LPFC_FCOE_FCF_MAP2;
3772a991 6425
2a76a283
JS
6426 /*
6427 * For SLI4, instead of using ring 0 (LPFC_FCP_RING) for FCP commands
895427bd
JS
6428 * we will associate a new ring, for each EQ/CQ/WQ tuple.
6429 * The WQ create will allocate the ring.
2a76a283 6430 */
09294d46 6431
81e6a637
JS
6432 /*
6433 * 1 for cmd, 1 for rsp, NVME adds an extra one
6434 * for boundary conditions in its max_sgl_segment template.
6435 */
6436 extra = 2;
6437 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
6438 extra++;
6439
da0436e9 6440 /*
09294d46
JS
6441 * It doesn't matter what family our adapter is in, we are
6442 * limited to 2 Pages, 512 SGEs, for our SGL.
6443 * There are going to be 2 reserved SGEs: 1 FCP cmnd + 1 FCP rsp
6444 */
6445 max_buf_size = (2 * SLI4_PAGE_SIZE);
09294d46 6446
da0436e9 6447 /*
895427bd
JS
6448 * Since lpfc_sg_seg_cnt is module param, the sg_dma_buf_size
6449 * used to create the sg_dma_buf_pool must be calculated.
da0436e9 6450 */
f44ac12f 6451 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED) {
96f7077f 6452 /*
895427bd
JS
6453 * The scsi_buf for a T10-DIF I/O holds the FCP cmnd,
6454 * the FCP rsp, and a SGE. Sice we have no control
6455 * over how many protection segments the SCSI Layer
96f7077f 6456 * will hand us (ie: there could be one for every block
895427bd
JS
6457 * in the IO), just allocate enough SGEs to accomidate
6458 * our max amount and we need to limit lpfc_sg_seg_cnt
6459 * to minimize the risk of running out.
96f7077f
JS
6460 */
6461 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
895427bd 6462 sizeof(struct fcp_rsp) + max_buf_size;
96f7077f
JS
6463
6464 /* Total SGEs for scsi_sg_list and scsi_sg_prot_list */
6465 phba->cfg_total_seg_cnt = LPFC_MAX_SGL_SEG_CNT;
6466
5b9e70b2
JS
6467 /*
6468 * If supporting DIF, reduce the seg count for scsi to
6469 * allow room for the DIF sges.
6470 */
6471 if (phba->cfg_enable_bg &&
6472 phba->cfg_sg_seg_cnt > LPFC_MAX_BG_SLI4_SEG_CNT_DIF)
6473 phba->cfg_scsi_seg_cnt = LPFC_MAX_BG_SLI4_SEG_CNT_DIF;
6474 else
6475 phba->cfg_scsi_seg_cnt = phba->cfg_sg_seg_cnt;
6476
96f7077f
JS
6477 } else {
6478 /*
895427bd 6479 * The scsi_buf for a regular I/O holds the FCP cmnd,
96f7077f
JS
6480 * the FCP rsp, a SGE for each, and a SGE for up to
6481 * cfg_sg_seg_cnt data segments.
6482 */
6483 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
895427bd 6484 sizeof(struct fcp_rsp) +
81e6a637 6485 ((phba->cfg_sg_seg_cnt + extra) *
895427bd 6486 sizeof(struct sli4_sge));
96f7077f
JS
6487
6488 /* Total SGEs for scsi_sg_list */
81e6a637 6489 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + extra;
5b9e70b2 6490 phba->cfg_scsi_seg_cnt = phba->cfg_sg_seg_cnt;
895427bd 6491
96f7077f 6492 /*
81e6a637 6493 * NOTE: if (phba->cfg_sg_seg_cnt + extra) <= 256 we only
895427bd 6494 * need to post 1 page for the SGL.
96f7077f 6495 */
085c647c 6496 }
acd6859b 6497
5b9e70b2
JS
6498 /* Limit to LPFC_MAX_NVME_SEG_CNT for NVME. */
6499 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
6500 if (phba->cfg_sg_seg_cnt > LPFC_MAX_NVME_SEG_CNT) {
6501 lpfc_printf_log(phba, KERN_INFO, LOG_NVME | LOG_INIT,
6502 "6300 Reducing NVME sg segment "
6503 "cnt to %d\n",
6504 LPFC_MAX_NVME_SEG_CNT);
6505 phba->cfg_nvme_seg_cnt = LPFC_MAX_NVME_SEG_CNT;
6506 } else
6507 phba->cfg_nvme_seg_cnt = phba->cfg_sg_seg_cnt;
6508 }
6509
96f7077f 6510 /* Initialize the host templates with the updated values. */
5b9e70b2
JS
6511 lpfc_vport_template.sg_tablesize = phba->cfg_scsi_seg_cnt;
6512 lpfc_template.sg_tablesize = phba->cfg_scsi_seg_cnt;
6513 lpfc_template_no_hr.sg_tablesize = phba->cfg_scsi_seg_cnt;
96f7077f
JS
6514
6515 if (phba->cfg_sg_dma_buf_size <= LPFC_MIN_SG_SLI4_BUF_SZ)
6516 phba->cfg_sg_dma_buf_size = LPFC_MIN_SG_SLI4_BUF_SZ;
6517 else
6518 phba->cfg_sg_dma_buf_size =
6519 SLI4_PAGE_ALIGN(phba->cfg_sg_dma_buf_size);
6520
6521 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
5b9e70b2
JS
6522 "9087 sg_seg_cnt:%d dmabuf_size:%d "
6523 "total:%d scsi:%d nvme:%d\n",
96f7077f 6524 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
5b9e70b2
JS
6525 phba->cfg_total_seg_cnt, phba->cfg_scsi_seg_cnt,
6526 phba->cfg_nvme_seg_cnt);
3772a991 6527
da0436e9 6528 /* Initialize buffer queue management fields */
895427bd 6529 INIT_LIST_HEAD(&phba->hbqs[LPFC_ELS_HBQ].hbq_buffer_list);
da0436e9
JS
6530 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_sli4_rb_alloc;
6531 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_sli4_rb_free;
3772a991 6532
da0436e9
JS
6533 /*
6534 * Initialize the SLI Layer to run with lpfc SLI4 HBAs.
6535 */
895427bd
JS
6536 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
6537 /* Initialize the Abort scsi buffer list used by driver */
6538 spin_lock_init(&phba->sli4_hba.abts_scsi_buf_list_lock);
6539 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_scsi_buf_list);
6540 }
6541
6542 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
6543 /* Initialize the Abort nvme buffer list used by driver */
5e5b511d 6544 spin_lock_init(&phba->sli4_hba.abts_nvmet_buf_list_lock);
86c67379 6545 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
a8cf5dfe 6546 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_io_wait_list);
895427bd
JS
6547 }
6548
da0436e9 6549 /* This abort list used by worker thread */
895427bd 6550 spin_lock_init(&phba->sli4_hba.sgl_list_lock);
a8cf5dfe 6551 spin_lock_init(&phba->sli4_hba.nvmet_io_wait_lock);
3772a991 6552
da0436e9 6553 /*
6d368e53 6554 * Initialize driver internal slow-path work queues
da0436e9 6555 */
3772a991 6556
da0436e9
JS
6557 /* Driver internel slow-path CQ Event pool */
6558 INIT_LIST_HEAD(&phba->sli4_hba.sp_cqe_event_pool);
6559 /* Response IOCB work queue list */
45ed1190 6560 INIT_LIST_HEAD(&phba->sli4_hba.sp_queue_event);
da0436e9
JS
6561 /* Asynchronous event CQ Event work queue list */
6562 INIT_LIST_HEAD(&phba->sli4_hba.sp_asynce_work_queue);
6563 /* Fast-path XRI aborted CQ Event work queue list */
6564 INIT_LIST_HEAD(&phba->sli4_hba.sp_fcp_xri_aborted_work_queue);
6565 /* Slow-path XRI aborted CQ Event work queue list */
6566 INIT_LIST_HEAD(&phba->sli4_hba.sp_els_xri_aborted_work_queue);
6567 /* Receive queue CQ Event work queue list */
6568 INIT_LIST_HEAD(&phba->sli4_hba.sp_unsol_work_queue);
6569
6d368e53
JS
6570 /* Initialize extent block lists. */
6571 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_blk_list);
6572 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_xri_blk_list);
6573 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_vfi_blk_list);
6574 INIT_LIST_HEAD(&phba->lpfc_vpi_blk_list);
6575
d1f525aa
JS
6576 /* Initialize mboxq lists. If the early init routines fail
6577 * these lists need to be correctly initialized.
6578 */
6579 INIT_LIST_HEAD(&phba->sli.mboxq);
6580 INIT_LIST_HEAD(&phba->sli.mboxq_cmpl);
6581
448193b5
JS
6582 /* initialize optic_state to 0xFF */
6583 phba->sli4_hba.lnk_info.optic_state = 0xff;
6584
da0436e9
JS
6585 /* Allocate device driver memory */
6586 rc = lpfc_mem_alloc(phba, SGL_ALIGN_SZ);
6587 if (rc)
6588 return -ENOMEM;
6589
2fcee4bf 6590 /* IF Type 2 ports get initialized now. */
27d6ac0a 6591 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) >=
2fcee4bf
JS
6592 LPFC_SLI_INTF_IF_TYPE_2) {
6593 rc = lpfc_pci_function_reset(phba);
895427bd
JS
6594 if (unlikely(rc)) {
6595 rc = -ENODEV;
6596 goto out_free_mem;
6597 }
946727dc 6598 phba->temp_sensor_support = 1;
2fcee4bf
JS
6599 }
6600
da0436e9
JS
6601 /* Create the bootstrap mailbox command */
6602 rc = lpfc_create_bootstrap_mbox(phba);
6603 if (unlikely(rc))
6604 goto out_free_mem;
6605
6606 /* Set up the host's endian order with the device. */
6607 rc = lpfc_setup_endian_order(phba);
6608 if (unlikely(rc))
6609 goto out_free_bsmbx;
6610
6611 /* Set up the hba's configuration parameters. */
6612 rc = lpfc_sli4_read_config(phba);
cff261f6
JS
6613 if (unlikely(rc))
6614 goto out_free_bsmbx;
6615 rc = lpfc_mem_alloc_active_rrq_pool_s4(phba);
da0436e9
JS
6616 if (unlikely(rc))
6617 goto out_free_bsmbx;
6618
2fcee4bf
JS
6619 /* IF Type 0 ports get initialized now. */
6620 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
6621 LPFC_SLI_INTF_IF_TYPE_0) {
6622 rc = lpfc_pci_function_reset(phba);
6623 if (unlikely(rc))
6624 goto out_free_bsmbx;
6625 }
da0436e9 6626
cb5172ea
JS
6627 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
6628 GFP_KERNEL);
6629 if (!mboxq) {
6630 rc = -ENOMEM;
6631 goto out_free_bsmbx;
6632 }
6633
f358dd0c 6634 /* Check for NVMET being configured */
895427bd 6635 phba->nvmet_support = 0;
f358dd0c
JS
6636 if (lpfc_enable_nvmet_cnt) {
6637
6638 /* First get WWN of HBA instance */
6639 lpfc_read_nv(phba, mboxq);
6640 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
6641 if (rc != MBX_SUCCESS) {
6642 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
6643 "6016 Mailbox failed , mbxCmd x%x "
6644 "READ_NV, mbxStatus x%x\n",
6645 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
6646 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
d1f525aa 6647 mempool_free(mboxq, phba->mbox_mem_pool);
f358dd0c
JS
6648 rc = -EIO;
6649 goto out_free_bsmbx;
6650 }
6651 mb = &mboxq->u.mb;
6652 memcpy(&wwn, (char *)mb->un.varRDnvp.nodename,
6653 sizeof(uint64_t));
6654 wwn = cpu_to_be64(wwn);
6655 phba->sli4_hba.wwnn.u.name = wwn;
6656 memcpy(&wwn, (char *)mb->un.varRDnvp.portname,
6657 sizeof(uint64_t));
6658 /* wwn is WWPN of HBA instance */
6659 wwn = cpu_to_be64(wwn);
6660 phba->sli4_hba.wwpn.u.name = wwn;
6661
6662 /* Check to see if it matches any module parameter */
6663 for (i = 0; i < lpfc_enable_nvmet_cnt; i++) {
6664 if (wwn == lpfc_enable_nvmet[i]) {
7d708033 6665#if (IS_ENABLED(CONFIG_NVME_TARGET_FC))
3c603be9
JS
6666 if (lpfc_nvmet_mem_alloc(phba))
6667 break;
6668
6669 phba->nvmet_support = 1; /* a match */
6670
f358dd0c
JS
6671 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6672 "6017 NVME Target %016llx\n",
6673 wwn);
7d708033
JS
6674#else
6675 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6676 "6021 Can't enable NVME Target."
6677 " NVME_TARGET_FC infrastructure"
6678 " is not in kernel\n");
6679#endif
c490850a
JS
6680 /* Not supported for NVMET */
6681 phba->cfg_xri_rebalancing = 0;
3c603be9 6682 break;
f358dd0c
JS
6683 }
6684 }
6685 }
895427bd
JS
6686
6687 lpfc_nvme_mod_param_dep(phba);
6688
fedd3b7b 6689 /* Get the Supported Pages if PORT_CAPABILITIES is supported by port. */
cb5172ea
JS
6690 lpfc_supported_pages(mboxq);
6691 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
fedd3b7b
JS
6692 if (!rc) {
6693 mqe = &mboxq->u.mqe;
6694 memcpy(&pn_page[0], ((uint8_t *)&mqe->un.supp_pages.word3),
6695 LPFC_MAX_SUPPORTED_PAGES);
6696 for (i = 0; i < LPFC_MAX_SUPPORTED_PAGES; i++) {
6697 switch (pn_page[i]) {
6698 case LPFC_SLI4_PARAMETERS:
6699 phba->sli4_hba.pc_sli4_params.supported = 1;
6700 break;
6701 default:
6702 break;
6703 }
6704 }
6705 /* Read the port's SLI4 Parameters capabilities if supported. */
6706 if (phba->sli4_hba.pc_sli4_params.supported)
6707 rc = lpfc_pc_sli4_params_get(phba, mboxq);
6708 if (rc) {
6709 mempool_free(mboxq, phba->mbox_mem_pool);
6710 rc = -EIO;
6711 goto out_free_bsmbx;
cb5172ea
JS
6712 }
6713 }
65791f1f 6714
fedd3b7b
JS
6715 /*
6716 * Get sli4 parameters that override parameters from Port capabilities.
6d368e53
JS
6717 * If this call fails, it isn't critical unless the SLI4 parameters come
6718 * back in conflict.
fedd3b7b 6719 */
6d368e53
JS
6720 rc = lpfc_get_sli4_parameters(phba, mboxq);
6721 if (rc) {
b92dc72d
JS
6722 if_type = bf_get(lpfc_sli_intf_if_type,
6723 &phba->sli4_hba.sli_intf);
6724 if_fam = bf_get(lpfc_sli_intf_sli_family,
6725 &phba->sli4_hba.sli_intf);
6d368e53
JS
6726 if (phba->sli4_hba.extents_in_use &&
6727 phba->sli4_hba.rpi_hdrs_in_use) {
6728 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6729 "2999 Unsupported SLI4 Parameters "
6730 "Extents and RPI headers enabled.\n");
b92dc72d
JS
6731 if (if_type == LPFC_SLI_INTF_IF_TYPE_0 &&
6732 if_fam == LPFC_SLI_INTF_FAMILY_BE2) {
6733 mempool_free(mboxq, phba->mbox_mem_pool);
6734 rc = -EIO;
6735 goto out_free_bsmbx;
6736 }
6737 }
6738 if (!(if_type == LPFC_SLI_INTF_IF_TYPE_0 &&
6739 if_fam == LPFC_SLI_INTF_FAMILY_BE2)) {
6740 mempool_free(mboxq, phba->mbox_mem_pool);
6741 rc = -EIO;
6742 goto out_free_bsmbx;
6d368e53
JS
6743 }
6744 }
895427bd 6745
cb5172ea 6746 mempool_free(mboxq, phba->mbox_mem_pool);
1ba981fd
JS
6747
6748 /* Verify OAS is supported */
6749 lpfc_sli4_oas_verify(phba);
1ba981fd 6750
d2cc9bcd
JS
6751 /* Verify RAS support on adapter */
6752 lpfc_sli4_ras_init(phba);
6753
5350d872
JS
6754 /* Verify all the SLI4 queues */
6755 rc = lpfc_sli4_queue_verify(phba);
da0436e9
JS
6756 if (rc)
6757 goto out_free_bsmbx;
6758
6759 /* Create driver internal CQE event pool */
6760 rc = lpfc_sli4_cq_event_pool_create(phba);
6761 if (rc)
5350d872 6762 goto out_free_bsmbx;
da0436e9 6763
8a9d2e80
JS
6764 /* Initialize sgl lists per host */
6765 lpfc_init_sgl_list(phba);
6766
6767 /* Allocate and initialize active sgl array */
da0436e9
JS
6768 rc = lpfc_init_active_sgl_array(phba);
6769 if (rc) {
6770 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6771 "1430 Failed to initialize sgl list.\n");
8a9d2e80 6772 goto out_destroy_cq_event_pool;
da0436e9 6773 }
da0436e9
JS
6774 rc = lpfc_sli4_init_rpi_hdrs(phba);
6775 if (rc) {
6776 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6777 "1432 Failed to initialize rpi headers.\n");
6778 goto out_free_active_sgl;
6779 }
6780
a93ff37a 6781 /* Allocate eligible FCF bmask memory for FCF roundrobin failover */
0c9ab6f5 6782 longs = (LPFC_SLI4_FCF_TBL_INDX_MAX + BITS_PER_LONG - 1)/BITS_PER_LONG;
6396bb22 6783 phba->fcf.fcf_rr_bmask = kcalloc(longs, sizeof(unsigned long),
0c9ab6f5
JS
6784 GFP_KERNEL);
6785 if (!phba->fcf.fcf_rr_bmask) {
6786 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6787 "2759 Failed allocate memory for FCF round "
6788 "robin failover bmask\n");
0558056c 6789 rc = -ENOMEM;
0c9ab6f5
JS
6790 goto out_remove_rpi_hdrs;
6791 }
6792
6a828b0f 6793 phba->sli4_hba.hba_eq_hdl = kcalloc(phba->cfg_irq_chann,
cdb42bec
JS
6794 sizeof(struct lpfc_hba_eq_hdl),
6795 GFP_KERNEL);
895427bd 6796 if (!phba->sli4_hba.hba_eq_hdl) {
67d12733
JS
6797 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6798 "2572 Failed allocate memory for "
6799 "fast-path per-EQ handle array\n");
6800 rc = -ENOMEM;
6801 goto out_free_fcf_rr_bmask;
da0436e9
JS
6802 }
6803
222e9239 6804 phba->sli4_hba.cpu_map = kcalloc(phba->sli4_hba.num_possible_cpu,
895427bd
JS
6805 sizeof(struct lpfc_vector_map_info),
6806 GFP_KERNEL);
7bb03bbf
JS
6807 if (!phba->sli4_hba.cpu_map) {
6808 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6809 "3327 Failed allocate memory for msi-x "
6810 "interrupt vector mapping\n");
6811 rc = -ENOMEM;
895427bd 6812 goto out_free_hba_eq_hdl;
7bb03bbf 6813 }
b246de17 6814
32517fc0
JS
6815 phba->sli4_hba.eq_info = alloc_percpu(struct lpfc_eq_intr_info);
6816 if (!phba->sli4_hba.eq_info) {
6817 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6818 "3321 Failed allocation for per_cpu stats\n");
6819 rc = -ENOMEM;
6820 goto out_free_hba_cpu_map;
6821 }
912e3acd
JS
6822 /*
6823 * Enable sr-iov virtual functions if supported and configured
6824 * through the module parameter.
6825 */
6826 if (phba->cfg_sriov_nr_virtfn > 0) {
6827 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
6828 phba->cfg_sriov_nr_virtfn);
6829 if (rc) {
6830 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6831 "3020 Requested number of SR-IOV "
6832 "virtual functions (%d) is not "
6833 "supported\n",
6834 phba->cfg_sriov_nr_virtfn);
6835 phba->cfg_sriov_nr_virtfn = 0;
6836 }
6837 }
6838
5248a749 6839 return 0;
da0436e9 6840
32517fc0
JS
6841out_free_hba_cpu_map:
6842 kfree(phba->sli4_hba.cpu_map);
895427bd
JS
6843out_free_hba_eq_hdl:
6844 kfree(phba->sli4_hba.hba_eq_hdl);
0c9ab6f5
JS
6845out_free_fcf_rr_bmask:
6846 kfree(phba->fcf.fcf_rr_bmask);
da0436e9
JS
6847out_remove_rpi_hdrs:
6848 lpfc_sli4_remove_rpi_hdrs(phba);
6849out_free_active_sgl:
6850 lpfc_free_active_sgl(phba);
da0436e9
JS
6851out_destroy_cq_event_pool:
6852 lpfc_sli4_cq_event_pool_destroy(phba);
da0436e9
JS
6853out_free_bsmbx:
6854 lpfc_destroy_bootstrap_mbox(phba);
6855out_free_mem:
6856 lpfc_mem_free(phba);
6857 return rc;
6858}
6859
6860/**
6861 * lpfc_sli4_driver_resource_unset - Unset drvr internal resources for SLI4 dev
6862 * @phba: pointer to lpfc hba data structure.
6863 *
6864 * This routine is invoked to unset the driver internal resources set up
6865 * specific for supporting the SLI-4 HBA device it attached to.
6866 **/
6867static void
6868lpfc_sli4_driver_resource_unset(struct lpfc_hba *phba)
6869{
6870 struct lpfc_fcf_conn_entry *conn_entry, *next_conn_entry;
6871
32517fc0
JS
6872 free_percpu(phba->sli4_hba.eq_info);
6873
7bb03bbf
JS
6874 /* Free memory allocated for msi-x interrupt vector to CPU mapping */
6875 kfree(phba->sli4_hba.cpu_map);
222e9239 6876 phba->sli4_hba.num_possible_cpu = 0;
7bb03bbf 6877 phba->sli4_hba.num_present_cpu = 0;
76fd07a6 6878 phba->sli4_hba.curr_disp_cpu = 0;
7bb03bbf 6879
da0436e9 6880 /* Free memory allocated for fast-path work queue handles */
895427bd 6881 kfree(phba->sli4_hba.hba_eq_hdl);
da0436e9
JS
6882
6883 /* Free the allocated rpi headers. */
6884 lpfc_sli4_remove_rpi_hdrs(phba);
d11e31dd 6885 lpfc_sli4_remove_rpis(phba);
da0436e9 6886
0c9ab6f5
JS
6887 /* Free eligible FCF index bmask */
6888 kfree(phba->fcf.fcf_rr_bmask);
6889
da0436e9
JS
6890 /* Free the ELS sgl list */
6891 lpfc_free_active_sgl(phba);
8a9d2e80 6892 lpfc_free_els_sgl_list(phba);
f358dd0c 6893 lpfc_free_nvmet_sgl_list(phba);
da0436e9 6894
da0436e9
JS
6895 /* Free the completion queue EQ event pool */
6896 lpfc_sli4_cq_event_release_all(phba);
6897 lpfc_sli4_cq_event_pool_destroy(phba);
6898
6d368e53
JS
6899 /* Release resource identifiers. */
6900 lpfc_sli4_dealloc_resource_identifiers(phba);
6901
da0436e9
JS
6902 /* Free the bsmbx region. */
6903 lpfc_destroy_bootstrap_mbox(phba);
6904
6905 /* Free the SLI Layer memory with SLI4 HBAs */
6906 lpfc_mem_free_all(phba);
6907
6908 /* Free the current connect table */
6909 list_for_each_entry_safe(conn_entry, next_conn_entry,
4d9ab994
JS
6910 &phba->fcf_conn_rec_list, list) {
6911 list_del_init(&conn_entry->list);
da0436e9 6912 kfree(conn_entry);
4d9ab994 6913 }
da0436e9
JS
6914
6915 return;
6916}
6917
6918/**
25985edc 6919 * lpfc_init_api_table_setup - Set up init api function jump table
da0436e9
JS
6920 * @phba: The hba struct for which this call is being executed.
6921 * @dev_grp: The HBA PCI-Device group number.
6922 *
6923 * This routine sets up the device INIT interface API function jump table
6924 * in @phba struct.
6925 *
6926 * Returns: 0 - success, -ENODEV - failure.
6927 **/
6928int
6929lpfc_init_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
6930{
84d1b006
JS
6931 phba->lpfc_hba_init_link = lpfc_hba_init_link;
6932 phba->lpfc_hba_down_link = lpfc_hba_down_link;
7f86059a 6933 phba->lpfc_selective_reset = lpfc_selective_reset;
da0436e9
JS
6934 switch (dev_grp) {
6935 case LPFC_PCI_DEV_LP:
6936 phba->lpfc_hba_down_post = lpfc_hba_down_post_s3;
6937 phba->lpfc_handle_eratt = lpfc_handle_eratt_s3;
6938 phba->lpfc_stop_port = lpfc_stop_port_s3;
6939 break;
6940 case LPFC_PCI_DEV_OC:
6941 phba->lpfc_hba_down_post = lpfc_hba_down_post_s4;
6942 phba->lpfc_handle_eratt = lpfc_handle_eratt_s4;
6943 phba->lpfc_stop_port = lpfc_stop_port_s4;
6944 break;
6945 default:
6946 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6947 "1431 Invalid HBA PCI-device group: 0x%x\n",
6948 dev_grp);
6949 return -ENODEV;
6950 break;
6951 }
6952 return 0;
6953}
6954
da0436e9
JS
6955/**
6956 * lpfc_setup_driver_resource_phase2 - Phase2 setup driver internal resources.
6957 * @phba: pointer to lpfc hba data structure.
6958 *
6959 * This routine is invoked to set up the driver internal resources after the
6960 * device specific resource setup to support the HBA device it attached to.
6961 *
6962 * Return codes
af901ca1 6963 * 0 - successful
da0436e9
JS
6964 * other values - error
6965 **/
6966static int
6967lpfc_setup_driver_resource_phase2(struct lpfc_hba *phba)
6968{
6969 int error;
6970
6971 /* Startup the kernel thread for this host adapter. */
6972 phba->worker_thread = kthread_run(lpfc_do_work, phba,
6973 "lpfc_worker_%d", phba->brd_no);
6974 if (IS_ERR(phba->worker_thread)) {
6975 error = PTR_ERR(phba->worker_thread);
6976 return error;
3772a991
JS
6977 }
6978
0cdb84ec
JS
6979 /* The lpfc_wq workqueue for deferred irq use, is only used for SLI4 */
6980 if (phba->sli_rev == LPFC_SLI_REV4)
6981 phba->wq = alloc_workqueue("lpfc_wq", WQ_MEM_RECLAIM, 0);
6982 else
6983 phba->wq = NULL;
f485c18d 6984
3772a991
JS
6985 return 0;
6986}
6987
6988/**
6989 * lpfc_unset_driver_resource_phase2 - Phase2 unset driver internal resources.
6990 * @phba: pointer to lpfc hba data structure.
6991 *
6992 * This routine is invoked to unset the driver internal resources set up after
6993 * the device specific resource setup for supporting the HBA device it
6994 * attached to.
6995 **/
6996static void
6997lpfc_unset_driver_resource_phase2(struct lpfc_hba *phba)
6998{
f485c18d
DK
6999 if (phba->wq) {
7000 flush_workqueue(phba->wq);
7001 destroy_workqueue(phba->wq);
7002 phba->wq = NULL;
7003 }
7004
3772a991 7005 /* Stop kernel worker thread */
0cdb84ec
JS
7006 if (phba->worker_thread)
7007 kthread_stop(phba->worker_thread);
3772a991
JS
7008}
7009
7010/**
7011 * lpfc_free_iocb_list - Free iocb list.
7012 * @phba: pointer to lpfc hba data structure.
7013 *
7014 * This routine is invoked to free the driver's IOCB list and memory.
7015 **/
6c621a22 7016void
3772a991
JS
7017lpfc_free_iocb_list(struct lpfc_hba *phba)
7018{
7019 struct lpfc_iocbq *iocbq_entry = NULL, *iocbq_next = NULL;
7020
7021 spin_lock_irq(&phba->hbalock);
7022 list_for_each_entry_safe(iocbq_entry, iocbq_next,
7023 &phba->lpfc_iocb_list, list) {
7024 list_del(&iocbq_entry->list);
7025 kfree(iocbq_entry);
7026 phba->total_iocbq_bufs--;
98c9ea5c 7027 }
3772a991
JS
7028 spin_unlock_irq(&phba->hbalock);
7029
7030 return;
7031}
7032
7033/**
7034 * lpfc_init_iocb_list - Allocate and initialize iocb list.
7035 * @phba: pointer to lpfc hba data structure.
7036 *
7037 * This routine is invoked to allocate and initizlize the driver's IOCB
7038 * list and set up the IOCB tag array accordingly.
7039 *
7040 * Return codes
af901ca1 7041 * 0 - successful
3772a991
JS
7042 * other values - error
7043 **/
6c621a22 7044int
3772a991
JS
7045lpfc_init_iocb_list(struct lpfc_hba *phba, int iocb_count)
7046{
7047 struct lpfc_iocbq *iocbq_entry = NULL;
7048 uint16_t iotag;
7049 int i;
dea3101e 7050
7051 /* Initialize and populate the iocb list per host. */
7052 INIT_LIST_HEAD(&phba->lpfc_iocb_list);
3772a991 7053 for (i = 0; i < iocb_count; i++) {
dd00cc48 7054 iocbq_entry = kzalloc(sizeof(struct lpfc_iocbq), GFP_KERNEL);
dea3101e 7055 if (iocbq_entry == NULL) {
7056 printk(KERN_ERR "%s: only allocated %d iocbs of "
7057 "expected %d count. Unloading driver.\n",
cadbd4a5 7058 __func__, i, LPFC_IOCB_LIST_CNT);
dea3101e 7059 goto out_free_iocbq;
7060 }
7061
604a3e30
JB
7062 iotag = lpfc_sli_next_iotag(phba, iocbq_entry);
7063 if (iotag == 0) {
3772a991 7064 kfree(iocbq_entry);
604a3e30 7065 printk(KERN_ERR "%s: failed to allocate IOTAG. "
3772a991 7066 "Unloading driver.\n", __func__);
604a3e30
JB
7067 goto out_free_iocbq;
7068 }
6d368e53 7069 iocbq_entry->sli4_lxritag = NO_XRI;
3772a991 7070 iocbq_entry->sli4_xritag = NO_XRI;
2e0fef85
JS
7071
7072 spin_lock_irq(&phba->hbalock);
dea3101e 7073 list_add(&iocbq_entry->list, &phba->lpfc_iocb_list);
7074 phba->total_iocbq_bufs++;
2e0fef85 7075 spin_unlock_irq(&phba->hbalock);
dea3101e 7076 }
7077
3772a991 7078 return 0;
dea3101e 7079
3772a991
JS
7080out_free_iocbq:
7081 lpfc_free_iocb_list(phba);
dea3101e 7082
3772a991
JS
7083 return -ENOMEM;
7084}
5e9d9b82 7085
3772a991 7086/**
8a9d2e80 7087 * lpfc_free_sgl_list - Free a given sgl list.
da0436e9 7088 * @phba: pointer to lpfc hba data structure.
8a9d2e80 7089 * @sglq_list: pointer to the head of sgl list.
3772a991 7090 *
8a9d2e80 7091 * This routine is invoked to free a give sgl list and memory.
3772a991 7092 **/
8a9d2e80
JS
7093void
7094lpfc_free_sgl_list(struct lpfc_hba *phba, struct list_head *sglq_list)
3772a991 7095{
da0436e9 7096 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
8a9d2e80
JS
7097
7098 list_for_each_entry_safe(sglq_entry, sglq_next, sglq_list, list) {
7099 list_del(&sglq_entry->list);
7100 lpfc_mbuf_free(phba, sglq_entry->virt, sglq_entry->phys);
7101 kfree(sglq_entry);
7102 }
7103}
7104
7105/**
7106 * lpfc_free_els_sgl_list - Free els sgl list.
7107 * @phba: pointer to lpfc hba data structure.
7108 *
7109 * This routine is invoked to free the driver's els sgl list and memory.
7110 **/
7111static void
7112lpfc_free_els_sgl_list(struct lpfc_hba *phba)
7113{
da0436e9 7114 LIST_HEAD(sglq_list);
dea3101e 7115
8a9d2e80 7116 /* Retrieve all els sgls from driver list */
da0436e9 7117 spin_lock_irq(&phba->hbalock);
895427bd
JS
7118 spin_lock(&phba->sli4_hba.sgl_list_lock);
7119 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list, &sglq_list);
7120 spin_unlock(&phba->sli4_hba.sgl_list_lock);
da0436e9 7121 spin_unlock_irq(&phba->hbalock);
dea3101e 7122
8a9d2e80
JS
7123 /* Now free the sgl list */
7124 lpfc_free_sgl_list(phba, &sglq_list);
da0436e9 7125}
92d7f7b0 7126
f358dd0c
JS
7127/**
7128 * lpfc_free_nvmet_sgl_list - Free nvmet sgl list.
7129 * @phba: pointer to lpfc hba data structure.
7130 *
7131 * This routine is invoked to free the driver's nvmet sgl list and memory.
7132 **/
7133static void
7134lpfc_free_nvmet_sgl_list(struct lpfc_hba *phba)
7135{
7136 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
7137 LIST_HEAD(sglq_list);
7138
7139 /* Retrieve all nvmet sgls from driver list */
7140 spin_lock_irq(&phba->hbalock);
7141 spin_lock(&phba->sli4_hba.sgl_list_lock);
7142 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list, &sglq_list);
7143 spin_unlock(&phba->sli4_hba.sgl_list_lock);
7144 spin_unlock_irq(&phba->hbalock);
7145
7146 /* Now free the sgl list */
7147 list_for_each_entry_safe(sglq_entry, sglq_next, &sglq_list, list) {
7148 list_del(&sglq_entry->list);
7149 lpfc_nvmet_buf_free(phba, sglq_entry->virt, sglq_entry->phys);
7150 kfree(sglq_entry);
7151 }
4b40d02b
DK
7152
7153 /* Update the nvmet_xri_cnt to reflect no current sgls.
7154 * The next initialization cycle sets the count and allocates
7155 * the sgls over again.
7156 */
7157 phba->sli4_hba.nvmet_xri_cnt = 0;
f358dd0c
JS
7158}
7159
da0436e9
JS
7160/**
7161 * lpfc_init_active_sgl_array - Allocate the buf to track active ELS XRIs.
7162 * @phba: pointer to lpfc hba data structure.
7163 *
7164 * This routine is invoked to allocate the driver's active sgl memory.
7165 * This array will hold the sglq_entry's for active IOs.
7166 **/
7167static int
7168lpfc_init_active_sgl_array(struct lpfc_hba *phba)
7169{
7170 int size;
7171 size = sizeof(struct lpfc_sglq *);
7172 size *= phba->sli4_hba.max_cfg_param.max_xri;
7173
7174 phba->sli4_hba.lpfc_sglq_active_list =
7175 kzalloc(size, GFP_KERNEL);
7176 if (!phba->sli4_hba.lpfc_sglq_active_list)
7177 return -ENOMEM;
7178 return 0;
3772a991
JS
7179}
7180
7181/**
da0436e9 7182 * lpfc_free_active_sgl - Free the buf that tracks active ELS XRIs.
3772a991
JS
7183 * @phba: pointer to lpfc hba data structure.
7184 *
da0436e9
JS
7185 * This routine is invoked to walk through the array of active sglq entries
7186 * and free all of the resources.
7187 * This is just a place holder for now.
3772a991
JS
7188 **/
7189static void
da0436e9 7190lpfc_free_active_sgl(struct lpfc_hba *phba)
3772a991 7191{
da0436e9 7192 kfree(phba->sli4_hba.lpfc_sglq_active_list);
3772a991
JS
7193}
7194
7195/**
da0436e9 7196 * lpfc_init_sgl_list - Allocate and initialize sgl list.
3772a991
JS
7197 * @phba: pointer to lpfc hba data structure.
7198 *
da0436e9
JS
7199 * This routine is invoked to allocate and initizlize the driver's sgl
7200 * list and set up the sgl xritag tag array accordingly.
3772a991 7201 *
3772a991 7202 **/
8a9d2e80 7203static void
da0436e9 7204lpfc_init_sgl_list(struct lpfc_hba *phba)
3772a991 7205{
da0436e9 7206 /* Initialize and populate the sglq list per host/VF. */
895427bd 7207 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_els_sgl_list);
da0436e9 7208 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_els_sgl_list);
f358dd0c 7209 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_sgl_list);
86c67379 7210 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
da0436e9 7211
8a9d2e80
JS
7212 /* els xri-sgl book keeping */
7213 phba->sli4_hba.els_xri_cnt = 0;
0ff10d46 7214
895427bd 7215 /* nvme xri-buffer book keeping */
5e5b511d 7216 phba->sli4_hba.io_xri_cnt = 0;
da0436e9
JS
7217}
7218
7219/**
7220 * lpfc_sli4_init_rpi_hdrs - Post the rpi header memory region to the port
7221 * @phba: pointer to lpfc hba data structure.
7222 *
7223 * This routine is invoked to post rpi header templates to the
88a2cfbb 7224 * port for those SLI4 ports that do not support extents. This routine
da0436e9 7225 * posts a PAGE_SIZE memory region to the port to hold up to
88a2cfbb
JS
7226 * PAGE_SIZE modulo 64 rpi context headers. This is an initialization routine
7227 * and should be called only when interrupts are disabled.
da0436e9
JS
7228 *
7229 * Return codes
af901ca1 7230 * 0 - successful
88a2cfbb 7231 * -ERROR - otherwise.
da0436e9
JS
7232 **/
7233int
7234lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *phba)
7235{
7236 int rc = 0;
da0436e9
JS
7237 struct lpfc_rpi_hdr *rpi_hdr;
7238
7239 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_hdr_list);
ff78d8f9 7240 if (!phba->sli4_hba.rpi_hdrs_in_use)
6d368e53 7241 return rc;
6d368e53
JS
7242 if (phba->sli4_hba.extents_in_use)
7243 return -EIO;
da0436e9
JS
7244
7245 rpi_hdr = lpfc_sli4_create_rpi_hdr(phba);
7246 if (!rpi_hdr) {
7247 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX | LOG_SLI,
7248 "0391 Error during rpi post operation\n");
7249 lpfc_sli4_remove_rpis(phba);
7250 rc = -ENODEV;
7251 }
7252
7253 return rc;
7254}
7255
7256/**
7257 * lpfc_sli4_create_rpi_hdr - Allocate an rpi header memory region
7258 * @phba: pointer to lpfc hba data structure.
7259 *
7260 * This routine is invoked to allocate a single 4KB memory region to
7261 * support rpis and stores them in the phba. This single region
7262 * provides support for up to 64 rpis. The region is used globally
7263 * by the device.
7264 *
7265 * Returns:
7266 * A valid rpi hdr on success.
7267 * A NULL pointer on any failure.
7268 **/
7269struct lpfc_rpi_hdr *
7270lpfc_sli4_create_rpi_hdr(struct lpfc_hba *phba)
7271{
7272 uint16_t rpi_limit, curr_rpi_range;
7273 struct lpfc_dmabuf *dmabuf;
7274 struct lpfc_rpi_hdr *rpi_hdr;
7275
6d368e53
JS
7276 /*
7277 * If the SLI4 port supports extents, posting the rpi header isn't
7278 * required. Set the expected maximum count and let the actual value
7279 * get set when extents are fully allocated.
7280 */
7281 if (!phba->sli4_hba.rpi_hdrs_in_use)
7282 return NULL;
7283 if (phba->sli4_hba.extents_in_use)
7284 return NULL;
7285
7286 /* The limit on the logical index is just the max_rpi count. */
845d9e8d 7287 rpi_limit = phba->sli4_hba.max_cfg_param.max_rpi;
da0436e9
JS
7288
7289 spin_lock_irq(&phba->hbalock);
6d368e53
JS
7290 /*
7291 * Establish the starting RPI in this header block. The starting
7292 * rpi is normalized to a zero base because the physical rpi is
7293 * port based.
7294 */
97f2ecf1 7295 curr_rpi_range = phba->sli4_hba.next_rpi;
da0436e9
JS
7296 spin_unlock_irq(&phba->hbalock);
7297
845d9e8d
JS
7298 /* Reached full RPI range */
7299 if (curr_rpi_range == rpi_limit)
6d368e53 7300 return NULL;
845d9e8d 7301
da0436e9
JS
7302 /*
7303 * First allocate the protocol header region for the port. The
7304 * port expects a 4KB DMA-mapped memory region that is 4K aligned.
7305 */
7306 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
7307 if (!dmabuf)
7308 return NULL;
7309
750afb08
LC
7310 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
7311 LPFC_HDR_TEMPLATE_SIZE,
7312 &dmabuf->phys, GFP_KERNEL);
da0436e9
JS
7313 if (!dmabuf->virt) {
7314 rpi_hdr = NULL;
7315 goto err_free_dmabuf;
7316 }
7317
da0436e9
JS
7318 if (!IS_ALIGNED(dmabuf->phys, LPFC_HDR_TEMPLATE_SIZE)) {
7319 rpi_hdr = NULL;
7320 goto err_free_coherent;
7321 }
7322
7323 /* Save the rpi header data for cleanup later. */
7324 rpi_hdr = kzalloc(sizeof(struct lpfc_rpi_hdr), GFP_KERNEL);
7325 if (!rpi_hdr)
7326 goto err_free_coherent;
7327
7328 rpi_hdr->dmabuf = dmabuf;
7329 rpi_hdr->len = LPFC_HDR_TEMPLATE_SIZE;
7330 rpi_hdr->page_count = 1;
7331 spin_lock_irq(&phba->hbalock);
6d368e53
JS
7332
7333 /* The rpi_hdr stores the logical index only. */
7334 rpi_hdr->start_rpi = curr_rpi_range;
845d9e8d 7335 rpi_hdr->next_rpi = phba->sli4_hba.next_rpi + LPFC_RPI_HDR_COUNT;
da0436e9
JS
7336 list_add_tail(&rpi_hdr->list, &phba->sli4_hba.lpfc_rpi_hdr_list);
7337
da0436e9
JS
7338 spin_unlock_irq(&phba->hbalock);
7339 return rpi_hdr;
7340
7341 err_free_coherent:
7342 dma_free_coherent(&phba->pcidev->dev, LPFC_HDR_TEMPLATE_SIZE,
7343 dmabuf->virt, dmabuf->phys);
7344 err_free_dmabuf:
7345 kfree(dmabuf);
7346 return NULL;
7347}
7348
7349/**
7350 * lpfc_sli4_remove_rpi_hdrs - Remove all rpi header memory regions
7351 * @phba: pointer to lpfc hba data structure.
7352 *
7353 * This routine is invoked to remove all memory resources allocated
6d368e53
JS
7354 * to support rpis for SLI4 ports not supporting extents. This routine
7355 * presumes the caller has released all rpis consumed by fabric or port
7356 * logins and is prepared to have the header pages removed.
da0436e9
JS
7357 **/
7358void
7359lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *phba)
7360{
7361 struct lpfc_rpi_hdr *rpi_hdr, *next_rpi_hdr;
7362
6d368e53
JS
7363 if (!phba->sli4_hba.rpi_hdrs_in_use)
7364 goto exit;
7365
da0436e9
JS
7366 list_for_each_entry_safe(rpi_hdr, next_rpi_hdr,
7367 &phba->sli4_hba.lpfc_rpi_hdr_list, list) {
7368 list_del(&rpi_hdr->list);
7369 dma_free_coherent(&phba->pcidev->dev, rpi_hdr->len,
7370 rpi_hdr->dmabuf->virt, rpi_hdr->dmabuf->phys);
7371 kfree(rpi_hdr->dmabuf);
7372 kfree(rpi_hdr);
7373 }
6d368e53
JS
7374 exit:
7375 /* There are no rpis available to the port now. */
7376 phba->sli4_hba.next_rpi = 0;
da0436e9
JS
7377}
7378
7379/**
7380 * lpfc_hba_alloc - Allocate driver hba data structure for a device.
7381 * @pdev: pointer to pci device data structure.
7382 *
7383 * This routine is invoked to allocate the driver hba data structure for an
7384 * HBA device. If the allocation is successful, the phba reference to the
7385 * PCI device data structure is set.
7386 *
7387 * Return codes
af901ca1 7388 * pointer to @phba - successful
da0436e9
JS
7389 * NULL - error
7390 **/
7391static struct lpfc_hba *
7392lpfc_hba_alloc(struct pci_dev *pdev)
7393{
7394 struct lpfc_hba *phba;
7395
7396 /* Allocate memory for HBA structure */
7397 phba = kzalloc(sizeof(struct lpfc_hba), GFP_KERNEL);
7398 if (!phba) {
e34ccdfe 7399 dev_err(&pdev->dev, "failed to allocate hba struct\n");
da0436e9
JS
7400 return NULL;
7401 }
7402
7403 /* Set reference to PCI device in HBA structure */
7404 phba->pcidev = pdev;
7405
7406 /* Assign an unused board number */
7407 phba->brd_no = lpfc_get_instance();
7408 if (phba->brd_no < 0) {
7409 kfree(phba);
7410 return NULL;
7411 }
65791f1f 7412 phba->eratt_poll_interval = LPFC_ERATT_POLL_INTERVAL;
da0436e9 7413
4fede78f 7414 spin_lock_init(&phba->ct_ev_lock);
f1c3b0fc
JS
7415 INIT_LIST_HEAD(&phba->ct_ev_waiters);
7416
da0436e9
JS
7417 return phba;
7418}
7419
7420/**
7421 * lpfc_hba_free - Free driver hba data structure with a device.
7422 * @phba: pointer to lpfc hba data structure.
7423 *
7424 * This routine is invoked to free the driver hba data structure with an
7425 * HBA device.
7426 **/
7427static void
7428lpfc_hba_free(struct lpfc_hba *phba)
7429{
5e5b511d
JS
7430 if (phba->sli_rev == LPFC_SLI_REV4)
7431 kfree(phba->sli4_hba.hdwq);
7432
da0436e9
JS
7433 /* Release the driver assigned board number */
7434 idr_remove(&lpfc_hba_index, phba->brd_no);
7435
895427bd
JS
7436 /* Free memory allocated with sli3 rings */
7437 kfree(phba->sli.sli3_ring);
7438 phba->sli.sli3_ring = NULL;
2a76a283 7439
da0436e9
JS
7440 kfree(phba);
7441 return;
7442}
7443
7444/**
7445 * lpfc_create_shost - Create hba physical port with associated scsi host.
7446 * @phba: pointer to lpfc hba data structure.
7447 *
7448 * This routine is invoked to create HBA physical port and associate a SCSI
7449 * host with it.
7450 *
7451 * Return codes
af901ca1 7452 * 0 - successful
da0436e9
JS
7453 * other values - error
7454 **/
7455static int
7456lpfc_create_shost(struct lpfc_hba *phba)
7457{
7458 struct lpfc_vport *vport;
7459 struct Scsi_Host *shost;
7460
7461 /* Initialize HBA FC structure */
7462 phba->fc_edtov = FF_DEF_EDTOV;
7463 phba->fc_ratov = FF_DEF_RATOV;
7464 phba->fc_altov = FF_DEF_ALTOV;
7465 phba->fc_arbtov = FF_DEF_ARBTOV;
7466
d7c47992 7467 atomic_set(&phba->sdev_cnt, 0);
da0436e9
JS
7468 vport = lpfc_create_port(phba, phba->brd_no, &phba->pcidev->dev);
7469 if (!vport)
7470 return -ENODEV;
7471
7472 shost = lpfc_shost_from_vport(vport);
7473 phba->pport = vport;
2ea259ee 7474
f358dd0c
JS
7475 if (phba->nvmet_support) {
7476 /* Only 1 vport (pport) will support NVME target */
7477 if (phba->txrdy_payload_pool == NULL) {
771db5c0
RP
7478 phba->txrdy_payload_pool = dma_pool_create(
7479 "txrdy_pool", &phba->pcidev->dev,
f358dd0c
JS
7480 TXRDY_PAYLOAD_LEN, 16, 0);
7481 if (phba->txrdy_payload_pool) {
7482 phba->targetport = NULL;
7483 phba->cfg_enable_fc4_type = LPFC_ENABLE_NVME;
7484 lpfc_printf_log(phba, KERN_INFO,
7485 LOG_INIT | LOG_NVME_DISC,
7486 "6076 NVME Target Found\n");
7487 }
7488 }
7489 }
7490
da0436e9
JS
7491 lpfc_debugfs_initialize(vport);
7492 /* Put reference to SCSI host to driver's device private data */
7493 pci_set_drvdata(phba->pcidev, shost);
2e0fef85 7494
4258e98e
JS
7495 /*
7496 * At this point we are fully registered with PSA. In addition,
7497 * any initial discovery should be completed.
7498 */
7499 vport->load_flag |= FC_ALLOW_FDMI;
8663cbbe
JS
7500 if (phba->cfg_enable_SmartSAN ||
7501 (phba->cfg_fdmi_on == LPFC_FDMI_SUPPORT)) {
4258e98e
JS
7502
7503 /* Setup appropriate attribute masks */
7504 vport->fdmi_hba_mask = LPFC_FDMI2_HBA_ATTR;
8663cbbe 7505 if (phba->cfg_enable_SmartSAN)
4258e98e
JS
7506 vport->fdmi_port_mask = LPFC_FDMI2_SMART_ATTR;
7507 else
7508 vport->fdmi_port_mask = LPFC_FDMI2_PORT_ATTR;
7509 }
3772a991
JS
7510 return 0;
7511}
db2378e0 7512
3772a991
JS
7513/**
7514 * lpfc_destroy_shost - Destroy hba physical port with associated scsi host.
7515 * @phba: pointer to lpfc hba data structure.
7516 *
7517 * This routine is invoked to destroy HBA physical port and the associated
7518 * SCSI host.
7519 **/
7520static void
7521lpfc_destroy_shost(struct lpfc_hba *phba)
7522{
7523 struct lpfc_vport *vport = phba->pport;
7524
7525 /* Destroy physical port that associated with the SCSI host */
7526 destroy_port(vport);
7527
7528 return;
7529}
7530
7531/**
7532 * lpfc_setup_bg - Setup Block guard structures and debug areas.
7533 * @phba: pointer to lpfc hba data structure.
7534 * @shost: the shost to be used to detect Block guard settings.
7535 *
7536 * This routine sets up the local Block guard protocol settings for @shost.
7537 * This routine also allocates memory for debugging bg buffers.
7538 **/
7539static void
7540lpfc_setup_bg(struct lpfc_hba *phba, struct Scsi_Host *shost)
7541{
bbeb79b9
JS
7542 uint32_t old_mask;
7543 uint32_t old_guard;
7544
3772a991 7545 int pagecnt = 10;
b3b98b74 7546 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
3772a991
JS
7547 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7548 "1478 Registering BlockGuard with the "
7549 "SCSI layer\n");
bbeb79b9 7550
b3b98b74
JS
7551 old_mask = phba->cfg_prot_mask;
7552 old_guard = phba->cfg_prot_guard;
bbeb79b9
JS
7553
7554 /* Only allow supported values */
b3b98b74 7555 phba->cfg_prot_mask &= (SHOST_DIF_TYPE1_PROTECTION |
bbeb79b9
JS
7556 SHOST_DIX_TYPE0_PROTECTION |
7557 SHOST_DIX_TYPE1_PROTECTION);
b3b98b74
JS
7558 phba->cfg_prot_guard &= (SHOST_DIX_GUARD_IP |
7559 SHOST_DIX_GUARD_CRC);
bbeb79b9
JS
7560
7561 /* DIF Type 1 protection for profiles AST1/C1 is end to end */
b3b98b74
JS
7562 if (phba->cfg_prot_mask == SHOST_DIX_TYPE1_PROTECTION)
7563 phba->cfg_prot_mask |= SHOST_DIF_TYPE1_PROTECTION;
bbeb79b9 7564
b3b98b74
JS
7565 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
7566 if ((old_mask != phba->cfg_prot_mask) ||
7567 (old_guard != phba->cfg_prot_guard))
bbeb79b9
JS
7568 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7569 "1475 Registering BlockGuard with the "
7570 "SCSI layer: mask %d guard %d\n",
b3b98b74
JS
7571 phba->cfg_prot_mask,
7572 phba->cfg_prot_guard);
bbeb79b9 7573
b3b98b74
JS
7574 scsi_host_set_prot(shost, phba->cfg_prot_mask);
7575 scsi_host_set_guard(shost, phba->cfg_prot_guard);
bbeb79b9
JS
7576 } else
7577 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7578 "1479 Not Registering BlockGuard with the SCSI "
7579 "layer, Bad protection parameters: %d %d\n",
7580 old_mask, old_guard);
3772a991 7581 }
bbeb79b9 7582
3772a991
JS
7583 if (!_dump_buf_data) {
7584 while (pagecnt) {
7585 spin_lock_init(&_dump_buf_lock);
7586 _dump_buf_data =
7587 (char *) __get_free_pages(GFP_KERNEL, pagecnt);
7588 if (_dump_buf_data) {
6a9c52cf
JS
7589 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
7590 "9043 BLKGRD: allocated %d pages for "
3772a991
JS
7591 "_dump_buf_data at 0x%p\n",
7592 (1 << pagecnt), _dump_buf_data);
7593 _dump_buf_data_order = pagecnt;
7594 memset(_dump_buf_data, 0,
7595 ((1 << PAGE_SHIFT) << pagecnt));
7596 break;
7597 } else
7598 --pagecnt;
7599 }
7600 if (!_dump_buf_data_order)
6a9c52cf
JS
7601 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
7602 "9044 BLKGRD: ERROR unable to allocate "
3772a991
JS
7603 "memory for hexdump\n");
7604 } else
6a9c52cf
JS
7605 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
7606 "9045 BLKGRD: already allocated _dump_buf_data=0x%p"
3772a991
JS
7607 "\n", _dump_buf_data);
7608 if (!_dump_buf_dif) {
7609 while (pagecnt) {
7610 _dump_buf_dif =
7611 (char *) __get_free_pages(GFP_KERNEL, pagecnt);
7612 if (_dump_buf_dif) {
6a9c52cf
JS
7613 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
7614 "9046 BLKGRD: allocated %d pages for "
3772a991
JS
7615 "_dump_buf_dif at 0x%p\n",
7616 (1 << pagecnt), _dump_buf_dif);
7617 _dump_buf_dif_order = pagecnt;
7618 memset(_dump_buf_dif, 0,
7619 ((1 << PAGE_SHIFT) << pagecnt));
7620 break;
7621 } else
7622 --pagecnt;
7623 }
7624 if (!_dump_buf_dif_order)
6a9c52cf
JS
7625 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
7626 "9047 BLKGRD: ERROR unable to allocate "
3772a991
JS
7627 "memory for hexdump\n");
7628 } else
6a9c52cf
JS
7629 lpfc_printf_log(phba, KERN_ERR, LOG_BG,
7630 "9048 BLKGRD: already allocated _dump_buf_dif=0x%p\n",
3772a991
JS
7631 _dump_buf_dif);
7632}
7633
7634/**
7635 * lpfc_post_init_setup - Perform necessary device post initialization setup.
7636 * @phba: pointer to lpfc hba data structure.
7637 *
7638 * This routine is invoked to perform all the necessary post initialization
7639 * setup for the device.
7640 **/
7641static void
7642lpfc_post_init_setup(struct lpfc_hba *phba)
7643{
7644 struct Scsi_Host *shost;
7645 struct lpfc_adapter_event_header adapter_event;
7646
7647 /* Get the default values for Model Name and Description */
7648 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
7649
7650 /*
7651 * hba setup may have changed the hba_queue_depth so we need to
7652 * adjust the value of can_queue.
7653 */
7654 shost = pci_get_drvdata(phba->pcidev);
7655 shost->can_queue = phba->cfg_hba_queue_depth - 10;
7656 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED)
7657 lpfc_setup_bg(phba, shost);
7658
7659 lpfc_host_attrib_init(shost);
7660
7661 if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
7662 spin_lock_irq(shost->host_lock);
7663 lpfc_poll_start_timer(phba);
7664 spin_unlock_irq(shost->host_lock);
7665 }
7666
7667 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7668 "0428 Perform SCSI scan\n");
7669 /* Send board arrival event to upper layer */
7670 adapter_event.event_type = FC_REG_ADAPTER_EVENT;
7671 adapter_event.subcategory = LPFC_EVENT_ARRIVAL;
7672 fc_host_post_vendor_event(shost, fc_get_event_number(),
7673 sizeof(adapter_event),
7674 (char *) &adapter_event,
7675 LPFC_NL_VENDOR_ID);
7676 return;
7677}
7678
7679/**
7680 * lpfc_sli_pci_mem_setup - Setup SLI3 HBA PCI memory space.
7681 * @phba: pointer to lpfc hba data structure.
7682 *
7683 * This routine is invoked to set up the PCI device memory space for device
7684 * with SLI-3 interface spec.
7685 *
7686 * Return codes
af901ca1 7687 * 0 - successful
3772a991
JS
7688 * other values - error
7689 **/
7690static int
7691lpfc_sli_pci_mem_setup(struct lpfc_hba *phba)
7692{
f30e1bfd 7693 struct pci_dev *pdev = phba->pcidev;
3772a991
JS
7694 unsigned long bar0map_len, bar2map_len;
7695 int i, hbq_count;
7696 void *ptr;
56de8357 7697 int error;
3772a991 7698
f30e1bfd 7699 if (!pdev)
56de8357 7700 return -ENODEV;
3772a991
JS
7701
7702 /* Set the device DMA mask size */
56de8357
HR
7703 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7704 if (error)
7705 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7706 if (error)
f30e1bfd 7707 return error;
56de8357 7708 error = -ENODEV;
3772a991
JS
7709
7710 /* Get the bus address of Bar0 and Bar2 and the number of bytes
7711 * required by each mapping.
7712 */
7713 phba->pci_bar0_map = pci_resource_start(pdev, 0);
7714 bar0map_len = pci_resource_len(pdev, 0);
7715
7716 phba->pci_bar2_map = pci_resource_start(pdev, 2);
7717 bar2map_len = pci_resource_len(pdev, 2);
7718
7719 /* Map HBA SLIM to a kernel virtual address. */
7720 phba->slim_memmap_p = ioremap(phba->pci_bar0_map, bar0map_len);
7721 if (!phba->slim_memmap_p) {
7722 dev_printk(KERN_ERR, &pdev->dev,
7723 "ioremap failed for SLIM memory.\n");
7724 goto out;
7725 }
7726
7727 /* Map HBA Control Registers to a kernel virtual address. */
7728 phba->ctrl_regs_memmap_p = ioremap(phba->pci_bar2_map, bar2map_len);
7729 if (!phba->ctrl_regs_memmap_p) {
7730 dev_printk(KERN_ERR, &pdev->dev,
7731 "ioremap failed for HBA control registers.\n");
7732 goto out_iounmap_slim;
7733 }
7734
7735 /* Allocate memory for SLI-2 structures */
750afb08
LC
7736 phba->slim2p.virt = dma_alloc_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7737 &phba->slim2p.phys, GFP_KERNEL);
3772a991
JS
7738 if (!phba->slim2p.virt)
7739 goto out_iounmap;
7740
3772a991 7741 phba->mbox = phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, mbx);
7a470277
JS
7742 phba->mbox_ext = (phba->slim2p.virt +
7743 offsetof(struct lpfc_sli2_slim, mbx_ext_words));
3772a991
JS
7744 phba->pcb = (phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, pcb));
7745 phba->IOCBs = (phba->slim2p.virt +
7746 offsetof(struct lpfc_sli2_slim, IOCBs));
7747
7748 phba->hbqslimp.virt = dma_alloc_coherent(&pdev->dev,
7749 lpfc_sli_hbq_size(),
7750 &phba->hbqslimp.phys,
7751 GFP_KERNEL);
7752 if (!phba->hbqslimp.virt)
7753 goto out_free_slim;
7754
7755 hbq_count = lpfc_sli_hbq_count();
7756 ptr = phba->hbqslimp.virt;
7757 for (i = 0; i < hbq_count; ++i) {
7758 phba->hbqs[i].hbq_virt = ptr;
7759 INIT_LIST_HEAD(&phba->hbqs[i].hbq_buffer_list);
7760 ptr += (lpfc_hbq_defs[i]->entry_count *
7761 sizeof(struct lpfc_hbq_entry));
7762 }
7763 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_els_hbq_alloc;
7764 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_els_hbq_free;
7765
7766 memset(phba->hbqslimp.virt, 0, lpfc_sli_hbq_size());
7767
3772a991
JS
7768 phba->MBslimaddr = phba->slim_memmap_p;
7769 phba->HAregaddr = phba->ctrl_regs_memmap_p + HA_REG_OFFSET;
7770 phba->CAregaddr = phba->ctrl_regs_memmap_p + CA_REG_OFFSET;
7771 phba->HSregaddr = phba->ctrl_regs_memmap_p + HS_REG_OFFSET;
7772 phba->HCregaddr = phba->ctrl_regs_memmap_p + HC_REG_OFFSET;
7773
7774 return 0;
7775
7776out_free_slim:
7777 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7778 phba->slim2p.virt, phba->slim2p.phys);
7779out_iounmap:
7780 iounmap(phba->ctrl_regs_memmap_p);
7781out_iounmap_slim:
7782 iounmap(phba->slim_memmap_p);
7783out:
7784 return error;
7785}
7786
7787/**
7788 * lpfc_sli_pci_mem_unset - Unset SLI3 HBA PCI memory space.
7789 * @phba: pointer to lpfc hba data structure.
7790 *
7791 * This routine is invoked to unset the PCI device memory space for device
7792 * with SLI-3 interface spec.
7793 **/
7794static void
7795lpfc_sli_pci_mem_unset(struct lpfc_hba *phba)
7796{
7797 struct pci_dev *pdev;
7798
7799 /* Obtain PCI device reference */
7800 if (!phba->pcidev)
7801 return;
7802 else
7803 pdev = phba->pcidev;
7804
7805 /* Free coherent DMA memory allocated */
7806 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
7807 phba->hbqslimp.virt, phba->hbqslimp.phys);
7808 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7809 phba->slim2p.virt, phba->slim2p.phys);
7810
7811 /* I/O memory unmap */
7812 iounmap(phba->ctrl_regs_memmap_p);
7813 iounmap(phba->slim_memmap_p);
7814
7815 return;
7816}
7817
7818/**
da0436e9 7819 * lpfc_sli4_post_status_check - Wait for SLI4 POST done and check status
3772a991
JS
7820 * @phba: pointer to lpfc hba data structure.
7821 *
da0436e9
JS
7822 * This routine is invoked to wait for SLI4 device Power On Self Test (POST)
7823 * done and check status.
3772a991 7824 *
da0436e9 7825 * Return 0 if successful, otherwise -ENODEV.
3772a991 7826 **/
da0436e9
JS
7827int
7828lpfc_sli4_post_status_check(struct lpfc_hba *phba)
3772a991 7829{
2fcee4bf
JS
7830 struct lpfc_register portsmphr_reg, uerrlo_reg, uerrhi_reg;
7831 struct lpfc_register reg_data;
7832 int i, port_error = 0;
7833 uint32_t if_type;
3772a991 7834
9940b97b
JS
7835 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
7836 memset(&reg_data, 0, sizeof(reg_data));
2fcee4bf 7837 if (!phba->sli4_hba.PSMPHRregaddr)
da0436e9 7838 return -ENODEV;
3772a991 7839
da0436e9
JS
7840 /* Wait up to 30 seconds for the SLI Port POST done and ready */
7841 for (i = 0; i < 3000; i++) {
9940b97b
JS
7842 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
7843 &portsmphr_reg.word0) ||
7844 (bf_get(lpfc_port_smphr_perr, &portsmphr_reg))) {
2fcee4bf 7845 /* Port has a fatal POST error, break out */
da0436e9
JS
7846 port_error = -ENODEV;
7847 break;
7848 }
2fcee4bf
JS
7849 if (LPFC_POST_STAGE_PORT_READY ==
7850 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg))
da0436e9 7851 break;
da0436e9 7852 msleep(10);
3772a991
JS
7853 }
7854
2fcee4bf
JS
7855 /*
7856 * If there was a port error during POST, then don't proceed with
7857 * other register reads as the data may not be valid. Just exit.
7858 */
7859 if (port_error) {
da0436e9 7860 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
2fcee4bf
JS
7861 "1408 Port Failed POST - portsmphr=0x%x, "
7862 "perr=x%x, sfi=x%x, nip=x%x, ipc=x%x, scr1=x%x, "
7863 "scr2=x%x, hscratch=x%x, pstatus=x%x\n",
7864 portsmphr_reg.word0,
7865 bf_get(lpfc_port_smphr_perr, &portsmphr_reg),
7866 bf_get(lpfc_port_smphr_sfi, &portsmphr_reg),
7867 bf_get(lpfc_port_smphr_nip, &portsmphr_reg),
7868 bf_get(lpfc_port_smphr_ipc, &portsmphr_reg),
7869 bf_get(lpfc_port_smphr_scr1, &portsmphr_reg),
7870 bf_get(lpfc_port_smphr_scr2, &portsmphr_reg),
7871 bf_get(lpfc_port_smphr_host_scratch, &portsmphr_reg),
7872 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg));
7873 } else {
28baac74 7874 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
2fcee4bf
JS
7875 "2534 Device Info: SLIFamily=0x%x, "
7876 "SLIRev=0x%x, IFType=0x%x, SLIHint_1=0x%x, "
7877 "SLIHint_2=0x%x, FT=0x%x\n",
28baac74
JS
7878 bf_get(lpfc_sli_intf_sli_family,
7879 &phba->sli4_hba.sli_intf),
7880 bf_get(lpfc_sli_intf_slirev,
7881 &phba->sli4_hba.sli_intf),
085c647c
JS
7882 bf_get(lpfc_sli_intf_if_type,
7883 &phba->sli4_hba.sli_intf),
7884 bf_get(lpfc_sli_intf_sli_hint1,
28baac74 7885 &phba->sli4_hba.sli_intf),
085c647c
JS
7886 bf_get(lpfc_sli_intf_sli_hint2,
7887 &phba->sli4_hba.sli_intf),
7888 bf_get(lpfc_sli_intf_func_type,
28baac74 7889 &phba->sli4_hba.sli_intf));
2fcee4bf
JS
7890 /*
7891 * Check for other Port errors during the initialization
7892 * process. Fail the load if the port did not come up
7893 * correctly.
7894 */
7895 if_type = bf_get(lpfc_sli_intf_if_type,
7896 &phba->sli4_hba.sli_intf);
7897 switch (if_type) {
7898 case LPFC_SLI_INTF_IF_TYPE_0:
7899 phba->sli4_hba.ue_mask_lo =
7900 readl(phba->sli4_hba.u.if_type0.UEMASKLOregaddr);
7901 phba->sli4_hba.ue_mask_hi =
7902 readl(phba->sli4_hba.u.if_type0.UEMASKHIregaddr);
7903 uerrlo_reg.word0 =
7904 readl(phba->sli4_hba.u.if_type0.UERRLOregaddr);
7905 uerrhi_reg.word0 =
7906 readl(phba->sli4_hba.u.if_type0.UERRHIregaddr);
7907 if ((~phba->sli4_hba.ue_mask_lo & uerrlo_reg.word0) ||
7908 (~phba->sli4_hba.ue_mask_hi & uerrhi_reg.word0)) {
7909 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7910 "1422 Unrecoverable Error "
7911 "Detected during POST "
7912 "uerr_lo_reg=0x%x, "
7913 "uerr_hi_reg=0x%x, "
7914 "ue_mask_lo_reg=0x%x, "
7915 "ue_mask_hi_reg=0x%x\n",
7916 uerrlo_reg.word0,
7917 uerrhi_reg.word0,
7918 phba->sli4_hba.ue_mask_lo,
7919 phba->sli4_hba.ue_mask_hi);
7920 port_error = -ENODEV;
7921 }
7922 break;
7923 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 7924 case LPFC_SLI_INTF_IF_TYPE_6:
2fcee4bf 7925 /* Final checks. The port status should be clean. */
9940b97b
JS
7926 if (lpfc_readl(phba->sli4_hba.u.if_type2.STATUSregaddr,
7927 &reg_data.word0) ||
0558056c
JS
7928 (bf_get(lpfc_sliport_status_err, &reg_data) &&
7929 !bf_get(lpfc_sliport_status_rn, &reg_data))) {
2fcee4bf
JS
7930 phba->work_status[0] =
7931 readl(phba->sli4_hba.u.if_type2.
7932 ERR1regaddr);
7933 phba->work_status[1] =
7934 readl(phba->sli4_hba.u.if_type2.
7935 ERR2regaddr);
7936 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8fcb8acd
JS
7937 "2888 Unrecoverable port error "
7938 "following POST: port status reg "
7939 "0x%x, port_smphr reg 0x%x, "
2fcee4bf
JS
7940 "error 1=0x%x, error 2=0x%x\n",
7941 reg_data.word0,
7942 portsmphr_reg.word0,
7943 phba->work_status[0],
7944 phba->work_status[1]);
7945 port_error = -ENODEV;
7946 }
7947 break;
7948 case LPFC_SLI_INTF_IF_TYPE_1:
7949 default:
7950 break;
7951 }
28baac74 7952 }
da0436e9
JS
7953 return port_error;
7954}
3772a991 7955
da0436e9
JS
7956/**
7957 * lpfc_sli4_bar0_register_memmap - Set up SLI4 BAR0 register memory map.
7958 * @phba: pointer to lpfc hba data structure.
2fcee4bf 7959 * @if_type: The SLI4 interface type getting configured.
da0436e9
JS
7960 *
7961 * This routine is invoked to set up SLI4 BAR0 PCI config space register
7962 * memory map.
7963 **/
7964static void
2fcee4bf
JS
7965lpfc_sli4_bar0_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
7966{
7967 switch (if_type) {
7968 case LPFC_SLI_INTF_IF_TYPE_0:
7969 phba->sli4_hba.u.if_type0.UERRLOregaddr =
7970 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_LO;
7971 phba->sli4_hba.u.if_type0.UERRHIregaddr =
7972 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_HI;
7973 phba->sli4_hba.u.if_type0.UEMASKLOregaddr =
7974 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_LO;
7975 phba->sli4_hba.u.if_type0.UEMASKHIregaddr =
7976 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_HI;
7977 phba->sli4_hba.SLIINTFregaddr =
7978 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
7979 break;
7980 case LPFC_SLI_INTF_IF_TYPE_2:
0cf07f84
JS
7981 phba->sli4_hba.u.if_type2.EQDregaddr =
7982 phba->sli4_hba.conf_regs_memmap_p +
7983 LPFC_CTL_PORT_EQ_DELAY_OFFSET;
2fcee4bf 7984 phba->sli4_hba.u.if_type2.ERR1regaddr =
88a2cfbb
JS
7985 phba->sli4_hba.conf_regs_memmap_p +
7986 LPFC_CTL_PORT_ER1_OFFSET;
2fcee4bf 7987 phba->sli4_hba.u.if_type2.ERR2regaddr =
88a2cfbb
JS
7988 phba->sli4_hba.conf_regs_memmap_p +
7989 LPFC_CTL_PORT_ER2_OFFSET;
2fcee4bf 7990 phba->sli4_hba.u.if_type2.CTRLregaddr =
88a2cfbb
JS
7991 phba->sli4_hba.conf_regs_memmap_p +
7992 LPFC_CTL_PORT_CTL_OFFSET;
2fcee4bf 7993 phba->sli4_hba.u.if_type2.STATUSregaddr =
88a2cfbb
JS
7994 phba->sli4_hba.conf_regs_memmap_p +
7995 LPFC_CTL_PORT_STA_OFFSET;
2fcee4bf
JS
7996 phba->sli4_hba.SLIINTFregaddr =
7997 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
7998 phba->sli4_hba.PSMPHRregaddr =
88a2cfbb
JS
7999 phba->sli4_hba.conf_regs_memmap_p +
8000 LPFC_CTL_PORT_SEM_OFFSET;
2fcee4bf 8001 phba->sli4_hba.RQDBregaddr =
962bc51b
JS
8002 phba->sli4_hba.conf_regs_memmap_p +
8003 LPFC_ULP0_RQ_DOORBELL;
2fcee4bf 8004 phba->sli4_hba.WQDBregaddr =
962bc51b
JS
8005 phba->sli4_hba.conf_regs_memmap_p +
8006 LPFC_ULP0_WQ_DOORBELL;
9dd35425 8007 phba->sli4_hba.CQDBregaddr =
2fcee4bf 8008 phba->sli4_hba.conf_regs_memmap_p + LPFC_EQCQ_DOORBELL;
9dd35425 8009 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.CQDBregaddr;
2fcee4bf
JS
8010 phba->sli4_hba.MQDBregaddr =
8011 phba->sli4_hba.conf_regs_memmap_p + LPFC_MQ_DOORBELL;
8012 phba->sli4_hba.BMBXregaddr =
8013 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
8014 break;
27d6ac0a
JS
8015 case LPFC_SLI_INTF_IF_TYPE_6:
8016 phba->sli4_hba.u.if_type2.EQDregaddr =
8017 phba->sli4_hba.conf_regs_memmap_p +
8018 LPFC_CTL_PORT_EQ_DELAY_OFFSET;
8019 phba->sli4_hba.u.if_type2.ERR1regaddr =
8020 phba->sli4_hba.conf_regs_memmap_p +
8021 LPFC_CTL_PORT_ER1_OFFSET;
8022 phba->sli4_hba.u.if_type2.ERR2regaddr =
8023 phba->sli4_hba.conf_regs_memmap_p +
8024 LPFC_CTL_PORT_ER2_OFFSET;
8025 phba->sli4_hba.u.if_type2.CTRLregaddr =
8026 phba->sli4_hba.conf_regs_memmap_p +
8027 LPFC_CTL_PORT_CTL_OFFSET;
8028 phba->sli4_hba.u.if_type2.STATUSregaddr =
8029 phba->sli4_hba.conf_regs_memmap_p +
8030 LPFC_CTL_PORT_STA_OFFSET;
8031 phba->sli4_hba.PSMPHRregaddr =
8032 phba->sli4_hba.conf_regs_memmap_p +
8033 LPFC_CTL_PORT_SEM_OFFSET;
8034 phba->sli4_hba.BMBXregaddr =
8035 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
8036 break;
2fcee4bf
JS
8037 case LPFC_SLI_INTF_IF_TYPE_1:
8038 default:
8039 dev_printk(KERN_ERR, &phba->pcidev->dev,
8040 "FATAL - unsupported SLI4 interface type - %d\n",
8041 if_type);
8042 break;
8043 }
da0436e9 8044}
3772a991 8045
da0436e9
JS
8046/**
8047 * lpfc_sli4_bar1_register_memmap - Set up SLI4 BAR1 register memory map.
8048 * @phba: pointer to lpfc hba data structure.
8049 *
27d6ac0a 8050 * This routine is invoked to set up SLI4 BAR1 register memory map.
da0436e9
JS
8051 **/
8052static void
27d6ac0a 8053lpfc_sli4_bar1_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
da0436e9 8054{
27d6ac0a
JS
8055 switch (if_type) {
8056 case LPFC_SLI_INTF_IF_TYPE_0:
8057 phba->sli4_hba.PSMPHRregaddr =
8058 phba->sli4_hba.ctrl_regs_memmap_p +
8059 LPFC_SLIPORT_IF0_SMPHR;
8060 phba->sli4_hba.ISRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8061 LPFC_HST_ISR0;
8062 phba->sli4_hba.IMRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8063 LPFC_HST_IMR0;
8064 phba->sli4_hba.ISCRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8065 LPFC_HST_ISCR0;
8066 break;
8067 case LPFC_SLI_INTF_IF_TYPE_6:
8068 phba->sli4_hba.RQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8069 LPFC_IF6_RQ_DOORBELL;
8070 phba->sli4_hba.WQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8071 LPFC_IF6_WQ_DOORBELL;
8072 phba->sli4_hba.CQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8073 LPFC_IF6_CQ_DOORBELL;
8074 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8075 LPFC_IF6_EQ_DOORBELL;
8076 phba->sli4_hba.MQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8077 LPFC_IF6_MQ_DOORBELL;
8078 break;
8079 case LPFC_SLI_INTF_IF_TYPE_2:
8080 case LPFC_SLI_INTF_IF_TYPE_1:
8081 default:
8082 dev_err(&phba->pcidev->dev,
8083 "FATAL - unsupported SLI4 interface type - %d\n",
8084 if_type);
8085 break;
8086 }
3772a991
JS
8087}
8088
8089/**
da0436e9 8090 * lpfc_sli4_bar2_register_memmap - Set up SLI4 BAR2 register memory map.
3772a991 8091 * @phba: pointer to lpfc hba data structure.
da0436e9 8092 * @vf: virtual function number
3772a991 8093 *
da0436e9
JS
8094 * This routine is invoked to set up SLI4 BAR2 doorbell register memory map
8095 * based on the given viftual function number, @vf.
8096 *
8097 * Return 0 if successful, otherwise -ENODEV.
3772a991 8098 **/
da0436e9
JS
8099static int
8100lpfc_sli4_bar2_register_memmap(struct lpfc_hba *phba, uint32_t vf)
3772a991 8101{
da0436e9
JS
8102 if (vf > LPFC_VIR_FUNC_MAX)
8103 return -ENODEV;
3772a991 8104
da0436e9 8105 phba->sli4_hba.RQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
962bc51b
JS
8106 vf * LPFC_VFR_PAGE_SIZE +
8107 LPFC_ULP0_RQ_DOORBELL);
da0436e9 8108 phba->sli4_hba.WQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
962bc51b
JS
8109 vf * LPFC_VFR_PAGE_SIZE +
8110 LPFC_ULP0_WQ_DOORBELL);
9dd35425
JS
8111 phba->sli4_hba.CQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8112 vf * LPFC_VFR_PAGE_SIZE +
8113 LPFC_EQCQ_DOORBELL);
8114 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.CQDBregaddr;
da0436e9
JS
8115 phba->sli4_hba.MQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8116 vf * LPFC_VFR_PAGE_SIZE + LPFC_MQ_DOORBELL);
8117 phba->sli4_hba.BMBXregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8118 vf * LPFC_VFR_PAGE_SIZE + LPFC_BMBX);
8119 return 0;
3772a991
JS
8120}
8121
8122/**
da0436e9 8123 * lpfc_create_bootstrap_mbox - Create the bootstrap mailbox
3772a991
JS
8124 * @phba: pointer to lpfc hba data structure.
8125 *
da0436e9
JS
8126 * This routine is invoked to create the bootstrap mailbox
8127 * region consistent with the SLI-4 interface spec. This
8128 * routine allocates all memory necessary to communicate
8129 * mailbox commands to the port and sets up all alignment
8130 * needs. No locks are expected to be held when calling
8131 * this routine.
3772a991
JS
8132 *
8133 * Return codes
af901ca1 8134 * 0 - successful
d439d286 8135 * -ENOMEM - could not allocated memory.
da0436e9 8136 **/
3772a991 8137static int
da0436e9 8138lpfc_create_bootstrap_mbox(struct lpfc_hba *phba)
3772a991 8139{
da0436e9
JS
8140 uint32_t bmbx_size;
8141 struct lpfc_dmabuf *dmabuf;
8142 struct dma_address *dma_address;
8143 uint32_t pa_addr;
8144 uint64_t phys_addr;
8145
8146 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
8147 if (!dmabuf)
8148 return -ENOMEM;
3772a991 8149
da0436e9
JS
8150 /*
8151 * The bootstrap mailbox region is comprised of 2 parts
8152 * plus an alignment restriction of 16 bytes.
8153 */
8154 bmbx_size = sizeof(struct lpfc_bmbx_create) + (LPFC_ALIGN_16_BYTE - 1);
750afb08
LC
8155 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev, bmbx_size,
8156 &dmabuf->phys, GFP_KERNEL);
da0436e9
JS
8157 if (!dmabuf->virt) {
8158 kfree(dmabuf);
8159 return -ENOMEM;
3772a991
JS
8160 }
8161
da0436e9
JS
8162 /*
8163 * Initialize the bootstrap mailbox pointers now so that the register
8164 * operations are simple later. The mailbox dma address is required
8165 * to be 16-byte aligned. Also align the virtual memory as each
8166 * maibox is copied into the bmbx mailbox region before issuing the
8167 * command to the port.
8168 */
8169 phba->sli4_hba.bmbx.dmabuf = dmabuf;
8170 phba->sli4_hba.bmbx.bmbx_size = bmbx_size;
8171
8172 phba->sli4_hba.bmbx.avirt = PTR_ALIGN(dmabuf->virt,
8173 LPFC_ALIGN_16_BYTE);
8174 phba->sli4_hba.bmbx.aphys = ALIGN(dmabuf->phys,
8175 LPFC_ALIGN_16_BYTE);
8176
8177 /*
8178 * Set the high and low physical addresses now. The SLI4 alignment
8179 * requirement is 16 bytes and the mailbox is posted to the port
8180 * as two 30-bit addresses. The other data is a bit marking whether
8181 * the 30-bit address is the high or low address.
8182 * Upcast bmbx aphys to 64bits so shift instruction compiles
8183 * clean on 32 bit machines.
8184 */
8185 dma_address = &phba->sli4_hba.bmbx.dma_address;
8186 phys_addr = (uint64_t)phba->sli4_hba.bmbx.aphys;
8187 pa_addr = (uint32_t) ((phys_addr >> 34) & 0x3fffffff);
8188 dma_address->addr_hi = (uint32_t) ((pa_addr << 2) |
8189 LPFC_BMBX_BIT1_ADDR_HI);
8190
8191 pa_addr = (uint32_t) ((phba->sli4_hba.bmbx.aphys >> 4) & 0x3fffffff);
8192 dma_address->addr_lo = (uint32_t) ((pa_addr << 2) |
8193 LPFC_BMBX_BIT1_ADDR_LO);
8194 return 0;
3772a991
JS
8195}
8196
8197/**
da0436e9 8198 * lpfc_destroy_bootstrap_mbox - Destroy all bootstrap mailbox resources
3772a991
JS
8199 * @phba: pointer to lpfc hba data structure.
8200 *
da0436e9
JS
8201 * This routine is invoked to teardown the bootstrap mailbox
8202 * region and release all host resources. This routine requires
8203 * the caller to ensure all mailbox commands recovered, no
8204 * additional mailbox comands are sent, and interrupts are disabled
8205 * before calling this routine.
8206 *
8207 **/
3772a991 8208static void
da0436e9 8209lpfc_destroy_bootstrap_mbox(struct lpfc_hba *phba)
3772a991 8210{
da0436e9
JS
8211 dma_free_coherent(&phba->pcidev->dev,
8212 phba->sli4_hba.bmbx.bmbx_size,
8213 phba->sli4_hba.bmbx.dmabuf->virt,
8214 phba->sli4_hba.bmbx.dmabuf->phys);
8215
8216 kfree(phba->sli4_hba.bmbx.dmabuf);
8217 memset(&phba->sli4_hba.bmbx, 0, sizeof(struct lpfc_bmbx));
3772a991
JS
8218}
8219
8220/**
da0436e9 8221 * lpfc_sli4_read_config - Get the config parameters.
3772a991
JS
8222 * @phba: pointer to lpfc hba data structure.
8223 *
da0436e9
JS
8224 * This routine is invoked to read the configuration parameters from the HBA.
8225 * The configuration parameters are used to set the base and maximum values
8226 * for RPI's XRI's VPI's VFI's and FCFIs. These values also affect the resource
8227 * allocation for the port.
3772a991
JS
8228 *
8229 * Return codes
af901ca1 8230 * 0 - successful
25985edc 8231 * -ENOMEM - No available memory
d439d286 8232 * -EIO - The mailbox failed to complete successfully.
3772a991 8233 **/
ff78d8f9 8234int
da0436e9 8235lpfc_sli4_read_config(struct lpfc_hba *phba)
3772a991 8236{
da0436e9
JS
8237 LPFC_MBOXQ_t *pmb;
8238 struct lpfc_mbx_read_config *rd_config;
912e3acd
JS
8239 union lpfc_sli4_cfg_shdr *shdr;
8240 uint32_t shdr_status, shdr_add_status;
8241 struct lpfc_mbx_get_func_cfg *get_func_cfg;
8242 struct lpfc_rsrc_desc_fcfcoe *desc;
8aa134a8 8243 char *pdesc_0;
c691816e 8244 uint16_t forced_link_speed;
6a828b0f 8245 uint32_t if_type, qmin;
8aa134a8 8246 int length, i, rc = 0, rc2;
3772a991 8247
da0436e9
JS
8248 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
8249 if (!pmb) {
8250 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8251 "2011 Unable to allocate memory for issuing "
8252 "SLI_CONFIG_SPECIAL mailbox command\n");
8253 return -ENOMEM;
3772a991
JS
8254 }
8255
da0436e9 8256 lpfc_read_config(phba, pmb);
3772a991 8257
da0436e9
JS
8258 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
8259 if (rc != MBX_SUCCESS) {
8260 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8261 "2012 Mailbox failed , mbxCmd x%x "
8262 "READ_CONFIG, mbxStatus x%x\n",
8263 bf_get(lpfc_mqe_command, &pmb->u.mqe),
8264 bf_get(lpfc_mqe_status, &pmb->u.mqe));
8265 rc = -EIO;
8266 } else {
8267 rd_config = &pmb->u.mqe.un.rd_config;
ff78d8f9
JS
8268 if (bf_get(lpfc_mbx_rd_conf_lnk_ldv, rd_config)) {
8269 phba->sli4_hba.lnk_info.lnk_dv = LPFC_LNK_DAT_VAL;
8270 phba->sli4_hba.lnk_info.lnk_tp =
8271 bf_get(lpfc_mbx_rd_conf_lnk_type, rd_config);
8272 phba->sli4_hba.lnk_info.lnk_no =
8273 bf_get(lpfc_mbx_rd_conf_lnk_numb, rd_config);
8274 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8275 "3081 lnk_type:%d, lnk_numb:%d\n",
8276 phba->sli4_hba.lnk_info.lnk_tp,
8277 phba->sli4_hba.lnk_info.lnk_no);
8278 } else
8279 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
8280 "3082 Mailbox (x%x) returned ldv:x0\n",
8281 bf_get(lpfc_mqe_command, &pmb->u.mqe));
44fd7fe3
JS
8282 if (bf_get(lpfc_mbx_rd_conf_bbscn_def, rd_config)) {
8283 phba->bbcredit_support = 1;
8284 phba->sli4_hba.bbscn_params.word0 = rd_config->word8;
8285 }
8286
1dc5ec24
JS
8287 phba->sli4_hba.conf_trunk =
8288 bf_get(lpfc_mbx_rd_conf_trunk, rd_config);
6d368e53
JS
8289 phba->sli4_hba.extents_in_use =
8290 bf_get(lpfc_mbx_rd_conf_extnts_inuse, rd_config);
da0436e9
JS
8291 phba->sli4_hba.max_cfg_param.max_xri =
8292 bf_get(lpfc_mbx_rd_conf_xri_count, rd_config);
8293 phba->sli4_hba.max_cfg_param.xri_base =
8294 bf_get(lpfc_mbx_rd_conf_xri_base, rd_config);
8295 phba->sli4_hba.max_cfg_param.max_vpi =
8296 bf_get(lpfc_mbx_rd_conf_vpi_count, rd_config);
8b47ae69
JS
8297 /* Limit the max we support */
8298 if (phba->sli4_hba.max_cfg_param.max_vpi > LPFC_MAX_VPORTS)
8299 phba->sli4_hba.max_cfg_param.max_vpi = LPFC_MAX_VPORTS;
da0436e9
JS
8300 phba->sli4_hba.max_cfg_param.vpi_base =
8301 bf_get(lpfc_mbx_rd_conf_vpi_base, rd_config);
8302 phba->sli4_hba.max_cfg_param.max_rpi =
8303 bf_get(lpfc_mbx_rd_conf_rpi_count, rd_config);
8304 phba->sli4_hba.max_cfg_param.rpi_base =
8305 bf_get(lpfc_mbx_rd_conf_rpi_base, rd_config);
8306 phba->sli4_hba.max_cfg_param.max_vfi =
8307 bf_get(lpfc_mbx_rd_conf_vfi_count, rd_config);
8308 phba->sli4_hba.max_cfg_param.vfi_base =
8309 bf_get(lpfc_mbx_rd_conf_vfi_base, rd_config);
8310 phba->sli4_hba.max_cfg_param.max_fcfi =
8311 bf_get(lpfc_mbx_rd_conf_fcfi_count, rd_config);
da0436e9
JS
8312 phba->sli4_hba.max_cfg_param.max_eq =
8313 bf_get(lpfc_mbx_rd_conf_eq_count, rd_config);
8314 phba->sli4_hba.max_cfg_param.max_rq =
8315 bf_get(lpfc_mbx_rd_conf_rq_count, rd_config);
8316 phba->sli4_hba.max_cfg_param.max_wq =
8317 bf_get(lpfc_mbx_rd_conf_wq_count, rd_config);
8318 phba->sli4_hba.max_cfg_param.max_cq =
8319 bf_get(lpfc_mbx_rd_conf_cq_count, rd_config);
8320 phba->lmt = bf_get(lpfc_mbx_rd_conf_lmt, rd_config);
8321 phba->sli4_hba.next_xri = phba->sli4_hba.max_cfg_param.xri_base;
8322 phba->vpi_base = phba->sli4_hba.max_cfg_param.vpi_base;
8323 phba->vfi_base = phba->sli4_hba.max_cfg_param.vfi_base;
5ffc266e
JS
8324 phba->max_vpi = (phba->sli4_hba.max_cfg_param.max_vpi > 0) ?
8325 (phba->sli4_hba.max_cfg_param.max_vpi - 1) : 0;
da0436e9
JS
8326 phba->max_vports = phba->max_vpi;
8327 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
6d368e53
JS
8328 "2003 cfg params Extents? %d "
8329 "XRI(B:%d M:%d), "
da0436e9
JS
8330 "VPI(B:%d M:%d) "
8331 "VFI(B:%d M:%d) "
8332 "RPI(B:%d M:%d) "
2ea259ee 8333 "FCFI:%d EQ:%d CQ:%d WQ:%d RQ:%d\n",
6d368e53 8334 phba->sli4_hba.extents_in_use,
da0436e9
JS
8335 phba->sli4_hba.max_cfg_param.xri_base,
8336 phba->sli4_hba.max_cfg_param.max_xri,
8337 phba->sli4_hba.max_cfg_param.vpi_base,
8338 phba->sli4_hba.max_cfg_param.max_vpi,
8339 phba->sli4_hba.max_cfg_param.vfi_base,
8340 phba->sli4_hba.max_cfg_param.max_vfi,
8341 phba->sli4_hba.max_cfg_param.rpi_base,
8342 phba->sli4_hba.max_cfg_param.max_rpi,
2ea259ee
JS
8343 phba->sli4_hba.max_cfg_param.max_fcfi,
8344 phba->sli4_hba.max_cfg_param.max_eq,
8345 phba->sli4_hba.max_cfg_param.max_cq,
8346 phba->sli4_hba.max_cfg_param.max_wq,
8347 phba->sli4_hba.max_cfg_param.max_rq);
8348
d38f33b3 8349 /*
6a828b0f
JS
8350 * Calculate queue resources based on how
8351 * many WQ/CQ/EQs are available.
d38f33b3 8352 */
6a828b0f
JS
8353 qmin = phba->sli4_hba.max_cfg_param.max_wq;
8354 if (phba->sli4_hba.max_cfg_param.max_cq < qmin)
8355 qmin = phba->sli4_hba.max_cfg_param.max_cq;
8356 if (phba->sli4_hba.max_cfg_param.max_eq < qmin)
8357 qmin = phba->sli4_hba.max_cfg_param.max_eq;
8358 /*
8359 * Whats left after this can go toward NVME / FCP.
8360 * The minus 4 accounts for ELS, NVME LS, MBOX
8361 * plus one extra. When configured for
8362 * NVMET, FCP io channel WQs are not created.
8363 */
8364 qmin -= 4;
d38f33b3 8365
6a828b0f
JS
8366 /* If NVME is configured, double the number of CQ/WQs needed */
8367 if ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) &&
8368 !phba->nvmet_support)
8369 qmin /= 2;
8370
8371 /* Check to see if there is enough for NVME */
8372 if ((phba->cfg_irq_chann > qmin) ||
8373 (phba->cfg_hdw_queue > qmin)) {
8374 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8375 "2005 Reducing Queues: "
8376 "WQ %d CQ %d EQ %d: min %d: "
8377 "IRQ %d HDWQ %d\n",
d38f33b3
JS
8378 phba->sli4_hba.max_cfg_param.max_wq,
8379 phba->sli4_hba.max_cfg_param.max_cq,
6a828b0f
JS
8380 phba->sli4_hba.max_cfg_param.max_eq,
8381 qmin, phba->cfg_irq_chann,
cdb42bec 8382 phba->cfg_hdw_queue);
d38f33b3 8383
6a828b0f
JS
8384 if (phba->cfg_irq_chann > qmin)
8385 phba->cfg_irq_chann = qmin;
8386 if (phba->cfg_hdw_queue > qmin)
8387 phba->cfg_hdw_queue = qmin;
d38f33b3 8388 }
3772a991 8389 }
912e3acd
JS
8390
8391 if (rc)
8392 goto read_cfg_out;
da0436e9 8393
c691816e
JS
8394 /* Update link speed if forced link speed is supported */
8395 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
27d6ac0a 8396 if (if_type >= LPFC_SLI_INTF_IF_TYPE_2) {
c691816e
JS
8397 forced_link_speed =
8398 bf_get(lpfc_mbx_rd_conf_link_speed, rd_config);
8399 if (forced_link_speed) {
8400 phba->hba_flag |= HBA_FORCED_LINK_SPEED;
8401
8402 switch (forced_link_speed) {
8403 case LINK_SPEED_1G:
8404 phba->cfg_link_speed =
8405 LPFC_USER_LINK_SPEED_1G;
8406 break;
8407 case LINK_SPEED_2G:
8408 phba->cfg_link_speed =
8409 LPFC_USER_LINK_SPEED_2G;
8410 break;
8411 case LINK_SPEED_4G:
8412 phba->cfg_link_speed =
8413 LPFC_USER_LINK_SPEED_4G;
8414 break;
8415 case LINK_SPEED_8G:
8416 phba->cfg_link_speed =
8417 LPFC_USER_LINK_SPEED_8G;
8418 break;
8419 case LINK_SPEED_10G:
8420 phba->cfg_link_speed =
8421 LPFC_USER_LINK_SPEED_10G;
8422 break;
8423 case LINK_SPEED_16G:
8424 phba->cfg_link_speed =
8425 LPFC_USER_LINK_SPEED_16G;
8426 break;
8427 case LINK_SPEED_32G:
8428 phba->cfg_link_speed =
8429 LPFC_USER_LINK_SPEED_32G;
8430 break;
fbd8a6ba
JS
8431 case LINK_SPEED_64G:
8432 phba->cfg_link_speed =
8433 LPFC_USER_LINK_SPEED_64G;
8434 break;
c691816e
JS
8435 case 0xffff:
8436 phba->cfg_link_speed =
8437 LPFC_USER_LINK_SPEED_AUTO;
8438 break;
8439 default:
8440 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8441 "0047 Unrecognized link "
8442 "speed : %d\n",
8443 forced_link_speed);
8444 phba->cfg_link_speed =
8445 LPFC_USER_LINK_SPEED_AUTO;
8446 }
8447 }
8448 }
8449
da0436e9 8450 /* Reset the DFT_HBA_Q_DEPTH to the max xri */
572709e2
JS
8451 length = phba->sli4_hba.max_cfg_param.max_xri -
8452 lpfc_sli4_get_els_iocb_cnt(phba);
8453 if (phba->cfg_hba_queue_depth > length) {
8454 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
8455 "3361 HBA queue depth changed from %d to %d\n",
8456 phba->cfg_hba_queue_depth, length);
8457 phba->cfg_hba_queue_depth = length;
8458 }
912e3acd 8459
27d6ac0a 8460 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) <
912e3acd
JS
8461 LPFC_SLI_INTF_IF_TYPE_2)
8462 goto read_cfg_out;
8463
8464 /* get the pf# and vf# for SLI4 if_type 2 port */
8465 length = (sizeof(struct lpfc_mbx_get_func_cfg) -
8466 sizeof(struct lpfc_sli4_cfg_mhdr));
8467 lpfc_sli4_config(phba, pmb, LPFC_MBOX_SUBSYSTEM_COMMON,
8468 LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG,
8469 length, LPFC_SLI4_MBX_EMBED);
8470
8aa134a8 8471 rc2 = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
912e3acd
JS
8472 shdr = (union lpfc_sli4_cfg_shdr *)
8473 &pmb->u.mqe.un.sli4_config.header.cfg_shdr;
8474 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
8475 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
8aa134a8 8476 if (rc2 || shdr_status || shdr_add_status) {
912e3acd
JS
8477 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8478 "3026 Mailbox failed , mbxCmd x%x "
8479 "GET_FUNCTION_CONFIG, mbxStatus x%x\n",
8480 bf_get(lpfc_mqe_command, &pmb->u.mqe),
8481 bf_get(lpfc_mqe_status, &pmb->u.mqe));
912e3acd
JS
8482 goto read_cfg_out;
8483 }
8484
8485 /* search for fc_fcoe resrouce descriptor */
8486 get_func_cfg = &pmb->u.mqe.un.get_func_cfg;
912e3acd 8487
8aa134a8
JS
8488 pdesc_0 = (char *)&get_func_cfg->func_cfg.desc[0];
8489 desc = (struct lpfc_rsrc_desc_fcfcoe *)pdesc_0;
8490 length = bf_get(lpfc_rsrc_desc_fcfcoe_length, desc);
8491 if (length == LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD)
8492 length = LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH;
8493 else if (length != LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH)
8494 goto read_cfg_out;
8495
912e3acd 8496 for (i = 0; i < LPFC_RSRC_DESC_MAX_NUM; i++) {
8aa134a8 8497 desc = (struct lpfc_rsrc_desc_fcfcoe *)(pdesc_0 + length * i);
912e3acd 8498 if (LPFC_RSRC_DESC_TYPE_FCFCOE ==
8aa134a8 8499 bf_get(lpfc_rsrc_desc_fcfcoe_type, desc)) {
912e3acd
JS
8500 phba->sli4_hba.iov.pf_number =
8501 bf_get(lpfc_rsrc_desc_fcfcoe_pfnum, desc);
8502 phba->sli4_hba.iov.vf_number =
8503 bf_get(lpfc_rsrc_desc_fcfcoe_vfnum, desc);
8504 break;
8505 }
8506 }
8507
8508 if (i < LPFC_RSRC_DESC_MAX_NUM)
8509 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8510 "3027 GET_FUNCTION_CONFIG: pf_number:%d, "
8511 "vf_number:%d\n", phba->sli4_hba.iov.pf_number,
8512 phba->sli4_hba.iov.vf_number);
8aa134a8 8513 else
912e3acd
JS
8514 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8515 "3028 GET_FUNCTION_CONFIG: failed to find "
c4dba187 8516 "Resource Descriptor:x%x\n",
912e3acd 8517 LPFC_RSRC_DESC_TYPE_FCFCOE);
912e3acd
JS
8518
8519read_cfg_out:
8520 mempool_free(pmb, phba->mbox_mem_pool);
da0436e9 8521 return rc;
3772a991
JS
8522}
8523
8524/**
2fcee4bf 8525 * lpfc_setup_endian_order - Write endian order to an SLI4 if_type 0 port.
3772a991
JS
8526 * @phba: pointer to lpfc hba data structure.
8527 *
2fcee4bf
JS
8528 * This routine is invoked to setup the port-side endian order when
8529 * the port if_type is 0. This routine has no function for other
8530 * if_types.
da0436e9
JS
8531 *
8532 * Return codes
af901ca1 8533 * 0 - successful
25985edc 8534 * -ENOMEM - No available memory
d439d286 8535 * -EIO - The mailbox failed to complete successfully.
3772a991 8536 **/
da0436e9
JS
8537static int
8538lpfc_setup_endian_order(struct lpfc_hba *phba)
3772a991 8539{
da0436e9 8540 LPFC_MBOXQ_t *mboxq;
2fcee4bf 8541 uint32_t if_type, rc = 0;
da0436e9
JS
8542 uint32_t endian_mb_data[2] = {HOST_ENDIAN_LOW_WORD0,
8543 HOST_ENDIAN_HIGH_WORD1};
3772a991 8544
2fcee4bf
JS
8545 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
8546 switch (if_type) {
8547 case LPFC_SLI_INTF_IF_TYPE_0:
8548 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
8549 GFP_KERNEL);
8550 if (!mboxq) {
8551 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8552 "0492 Unable to allocate memory for "
8553 "issuing SLI_CONFIG_SPECIAL mailbox "
8554 "command\n");
8555 return -ENOMEM;
8556 }
3772a991 8557
2fcee4bf
JS
8558 /*
8559 * The SLI4_CONFIG_SPECIAL mailbox command requires the first
8560 * two words to contain special data values and no other data.
8561 */
8562 memset(mboxq, 0, sizeof(LPFC_MBOXQ_t));
8563 memcpy(&mboxq->u.mqe, &endian_mb_data, sizeof(endian_mb_data));
8564 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
8565 if (rc != MBX_SUCCESS) {
8566 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8567 "0493 SLI_CONFIG_SPECIAL mailbox "
8568 "failed with status x%x\n",
8569 rc);
8570 rc = -EIO;
8571 }
8572 mempool_free(mboxq, phba->mbox_mem_pool);
8573 break;
27d6ac0a 8574 case LPFC_SLI_INTF_IF_TYPE_6:
2fcee4bf
JS
8575 case LPFC_SLI_INTF_IF_TYPE_2:
8576 case LPFC_SLI_INTF_IF_TYPE_1:
8577 default:
8578 break;
da0436e9 8579 }
da0436e9 8580 return rc;
3772a991
JS
8581}
8582
8583/**
895427bd 8584 * lpfc_sli4_queue_verify - Verify and update EQ counts
3772a991
JS
8585 * @phba: pointer to lpfc hba data structure.
8586 *
895427bd
JS
8587 * This routine is invoked to check the user settable queue counts for EQs.
8588 * After this routine is called the counts will be set to valid values that
5350d872
JS
8589 * adhere to the constraints of the system's interrupt vectors and the port's
8590 * queue resources.
da0436e9
JS
8591 *
8592 * Return codes
af901ca1 8593 * 0 - successful
25985edc 8594 * -ENOMEM - No available memory
3772a991 8595 **/
da0436e9 8596static int
5350d872 8597lpfc_sli4_queue_verify(struct lpfc_hba *phba)
3772a991 8598{
da0436e9 8599 /*
67d12733 8600 * Sanity check for configured queue parameters against the run-time
da0436e9
JS
8601 * device parameters
8602 */
3772a991 8603
bcb24f65 8604 if (phba->nvmet_support) {
6a828b0f
JS
8605 if (phba->cfg_irq_chann < phba->cfg_nvmet_mrq)
8606 phba->cfg_nvmet_mrq = phba->cfg_irq_chann;
982ab128
JS
8607 if (phba->cfg_nvmet_mrq > LPFC_NVMET_MRQ_MAX)
8608 phba->cfg_nvmet_mrq = LPFC_NVMET_MRQ_MAX;
bcb24f65 8609 }
895427bd
JS
8610
8611 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6a828b0f
JS
8612 "2574 IO channels: hdwQ %d IRQ %d MRQ: %d\n",
8613 phba->cfg_hdw_queue, phba->cfg_irq_chann,
8614 phba->cfg_nvmet_mrq);
3772a991 8615
da0436e9
JS
8616 /* Get EQ depth from module parameter, fake the default for now */
8617 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
8618 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
3772a991 8619
5350d872
JS
8620 /* Get CQ depth from module parameter, fake the default for now */
8621 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
8622 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
895427bd
JS
8623 return 0;
8624}
8625
8626static int
8627lpfc_alloc_nvme_wq_cq(struct lpfc_hba *phba, int wqidx)
8628{
8629 struct lpfc_queue *qdesc;
5350d872 8630
a51e41b6 8631 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
81b96eda 8632 phba->sli4_hba.cq_esize,
a51e41b6 8633 LPFC_CQE_EXP_COUNT);
895427bd
JS
8634 if (!qdesc) {
8635 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8636 "0508 Failed allocate fast-path NVME CQ (%d)\n",
8637 wqidx);
8638 return 1;
8639 }
7365f6fd 8640 qdesc->qe_valid = 1;
5e5b511d 8641 qdesc->hdwq = wqidx;
6a828b0f 8642 qdesc->chann = lpfc_find_cpu_handle(phba, wqidx, LPFC_FIND_BY_HDWQ);
cdb42bec 8643 phba->sli4_hba.hdwq[wqidx].nvme_cq = qdesc;
895427bd 8644
a51e41b6
JS
8645 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
8646 LPFC_WQE128_SIZE, LPFC_WQE_EXP_COUNT);
895427bd
JS
8647 if (!qdesc) {
8648 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8649 "0509 Failed allocate fast-path NVME WQ (%d)\n",
8650 wqidx);
8651 return 1;
8652 }
5e5b511d 8653 qdesc->hdwq = wqidx;
6a828b0f 8654 qdesc->chann = wqidx;
cdb42bec 8655 phba->sli4_hba.hdwq[wqidx].nvme_wq = qdesc;
895427bd
JS
8656 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
8657 return 0;
8658}
8659
8660static int
8661lpfc_alloc_fcp_wq_cq(struct lpfc_hba *phba, int wqidx)
8662{
8663 struct lpfc_queue *qdesc;
c176ffa0 8664 uint32_t wqesize;
895427bd
JS
8665
8666 /* Create Fast Path FCP CQs */
c176ffa0 8667 if (phba->enab_exp_wqcq_pages)
a51e41b6
JS
8668 /* Increase the CQ size when WQEs contain an embedded cdb */
8669 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
8670 phba->sli4_hba.cq_esize,
8671 LPFC_CQE_EXP_COUNT);
8672
8673 else
8674 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8675 phba->sli4_hba.cq_esize,
8676 phba->sli4_hba.cq_ecount);
895427bd
JS
8677 if (!qdesc) {
8678 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8679 "0499 Failed allocate fast-path FCP CQ (%d)\n", wqidx);
8680 return 1;
8681 }
7365f6fd 8682 qdesc->qe_valid = 1;
5e5b511d 8683 qdesc->hdwq = wqidx;
6a828b0f 8684 qdesc->chann = lpfc_find_cpu_handle(phba, wqidx, LPFC_FIND_BY_HDWQ);
cdb42bec 8685 phba->sli4_hba.hdwq[wqidx].fcp_cq = qdesc;
895427bd
JS
8686
8687 /* Create Fast Path FCP WQs */
c176ffa0 8688 if (phba->enab_exp_wqcq_pages) {
a51e41b6 8689 /* Increase the WQ size when WQEs contain an embedded cdb */
c176ffa0
JS
8690 wqesize = (phba->fcp_embed_io) ?
8691 LPFC_WQE128_SIZE : phba->sli4_hba.wq_esize;
a51e41b6 8692 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
c176ffa0 8693 wqesize,
a51e41b6 8694 LPFC_WQE_EXP_COUNT);
c176ffa0 8695 } else
a51e41b6
JS
8696 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8697 phba->sli4_hba.wq_esize,
8698 phba->sli4_hba.wq_ecount);
c176ffa0 8699
895427bd
JS
8700 if (!qdesc) {
8701 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8702 "0503 Failed allocate fast-path FCP WQ (%d)\n",
8703 wqidx);
8704 return 1;
8705 }
5e5b511d 8706 qdesc->hdwq = wqidx;
6a828b0f 8707 qdesc->chann = wqidx;
cdb42bec 8708 phba->sli4_hba.hdwq[wqidx].fcp_wq = qdesc;
895427bd 8709 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
5350d872 8710 return 0;
5350d872
JS
8711}
8712
8713/**
8714 * lpfc_sli4_queue_create - Create all the SLI4 queues
8715 * @phba: pointer to lpfc hba data structure.
8716 *
8717 * This routine is invoked to allocate all the SLI4 queues for the FCoE HBA
8718 * operation. For each SLI4 queue type, the parameters such as queue entry
8719 * count (queue depth) shall be taken from the module parameter. For now,
8720 * we just use some constant number as place holder.
8721 *
8722 * Return codes
4907cb7b 8723 * 0 - successful
5350d872
JS
8724 * -ENOMEM - No availble memory
8725 * -EIO - The mailbox failed to complete successfully.
8726 **/
8727int
8728lpfc_sli4_queue_create(struct lpfc_hba *phba)
8729{
8730 struct lpfc_queue *qdesc;
6a828b0f 8731 int idx, eqidx;
5e5b511d 8732 struct lpfc_sli4_hdw_queue *qp;
32517fc0 8733 struct lpfc_eq_intr_info *eqi;
5350d872
JS
8734
8735 /*
67d12733 8736 * Create HBA Record arrays.
895427bd 8737 * Both NVME and FCP will share that same vectors / EQs
5350d872 8738 */
67d12733
JS
8739 phba->sli4_hba.mq_esize = LPFC_MQE_SIZE;
8740 phba->sli4_hba.mq_ecount = LPFC_MQE_DEF_COUNT;
8741 phba->sli4_hba.wq_esize = LPFC_WQE_SIZE;
8742 phba->sli4_hba.wq_ecount = LPFC_WQE_DEF_COUNT;
8743 phba->sli4_hba.rq_esize = LPFC_RQE_SIZE;
8744 phba->sli4_hba.rq_ecount = LPFC_RQE_DEF_COUNT;
895427bd
JS
8745 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
8746 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
8747 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
8748 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
67d12733 8749
cdb42bec 8750 if (!phba->sli4_hba.hdwq) {
5e5b511d
JS
8751 phba->sli4_hba.hdwq = kcalloc(
8752 phba->cfg_hdw_queue, sizeof(struct lpfc_sli4_hdw_queue),
8753 GFP_KERNEL);
8754 if (!phba->sli4_hba.hdwq) {
895427bd 8755 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5e5b511d
JS
8756 "6427 Failed allocate memory for "
8757 "fast-path Hardware Queue array\n");
895427bd
JS
8758 goto out_error;
8759 }
5e5b511d
JS
8760 /* Prepare hardware queues to take IO buffers */
8761 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
8762 qp = &phba->sli4_hba.hdwq[idx];
8763 spin_lock_init(&qp->io_buf_list_get_lock);
8764 spin_lock_init(&qp->io_buf_list_put_lock);
8765 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_get);
8766 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_put);
8767 qp->get_io_bufs = 0;
8768 qp->put_io_bufs = 0;
8769 qp->total_io_bufs = 0;
8770 spin_lock_init(&qp->abts_scsi_buf_list_lock);
8771 INIT_LIST_HEAD(&qp->lpfc_abts_scsi_buf_list);
8772 qp->abts_scsi_io_bufs = 0;
8773 spin_lock_init(&qp->abts_nvme_buf_list_lock);
8774 INIT_LIST_HEAD(&qp->lpfc_abts_nvme_buf_list);
8775 qp->abts_nvme_io_bufs = 0;
895427bd 8776 }
67d12733
JS
8777 }
8778
cdb42bec 8779 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
2d7dbc4c
JS
8780 if (phba->nvmet_support) {
8781 phba->sli4_hba.nvmet_cqset = kcalloc(
8782 phba->cfg_nvmet_mrq,
8783 sizeof(struct lpfc_queue *),
8784 GFP_KERNEL);
8785 if (!phba->sli4_hba.nvmet_cqset) {
8786 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8787 "3121 Fail allocate memory for "
8788 "fast-path CQ set array\n");
8789 goto out_error;
8790 }
8791 phba->sli4_hba.nvmet_mrq_hdr = kcalloc(
8792 phba->cfg_nvmet_mrq,
8793 sizeof(struct lpfc_queue *),
8794 GFP_KERNEL);
8795 if (!phba->sli4_hba.nvmet_mrq_hdr) {
8796 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8797 "3122 Fail allocate memory for "
8798 "fast-path RQ set hdr array\n");
8799 goto out_error;
8800 }
8801 phba->sli4_hba.nvmet_mrq_data = kcalloc(
8802 phba->cfg_nvmet_mrq,
8803 sizeof(struct lpfc_queue *),
8804 GFP_KERNEL);
8805 if (!phba->sli4_hba.nvmet_mrq_data) {
8806 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8807 "3124 Fail allocate memory for "
8808 "fast-path RQ set data array\n");
8809 goto out_error;
8810 }
8811 }
da0436e9 8812 }
67d12733 8813
895427bd 8814 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
67d12733 8815
895427bd 8816 /* Create HBA Event Queues (EQs) */
cdb42bec 8817 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
6a828b0f
JS
8818 /*
8819 * If there are more Hardware Queues than available
8820 * CQs, multiple Hardware Queues may share a common EQ.
8821 */
8822 if (idx >= phba->cfg_irq_chann) {
8823 /* Share an existing EQ */
8824 eqidx = lpfc_find_eq_handle(phba, idx);
8825 phba->sli4_hba.hdwq[idx].hba_eq =
8826 phba->sli4_hba.hdwq[eqidx].hba_eq;
8827 continue;
8828 }
8829 /* Create an EQ */
81b96eda
JS
8830 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8831 phba->sli4_hba.eq_esize,
da0436e9
JS
8832 phba->sli4_hba.eq_ecount);
8833 if (!qdesc) {
8834 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
67d12733
JS
8835 "0497 Failed allocate EQ (%d)\n", idx);
8836 goto out_error;
da0436e9 8837 }
7365f6fd 8838 qdesc->qe_valid = 1;
5e5b511d 8839 qdesc->hdwq = idx;
6a828b0f
JS
8840
8841 /* Save the CPU this EQ is affinitised to */
8842 eqidx = lpfc_find_eq_handle(phba, idx);
8843 qdesc->chann = lpfc_find_cpu_handle(phba, eqidx,
8844 LPFC_FIND_BY_EQ);
cdb42bec 8845 phba->sli4_hba.hdwq[idx].hba_eq = qdesc;
32517fc0
JS
8846 qdesc->last_cpu = qdesc->chann;
8847 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, qdesc->last_cpu);
8848 list_add(&qdesc->cpu_list, &eqi->list);
895427bd 8849 }
67d12733 8850
67d12733 8851
cdb42bec 8852 /* Allocate SCSI SLI4 CQ/WQs */
6a828b0f 8853 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
895427bd 8854 if (lpfc_alloc_fcp_wq_cq(phba, idx))
67d12733 8855 goto out_error;
6a828b0f 8856 }
da0436e9 8857
cdb42bec
JS
8858 /* Allocate NVME SLI4 CQ/WQs */
8859 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
6a828b0f 8860 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
cdb42bec
JS
8861 if (lpfc_alloc_nvme_wq_cq(phba, idx))
8862 goto out_error;
6a828b0f 8863 }
67d12733 8864
cdb42bec
JS
8865 if (phba->nvmet_support) {
8866 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
8867 qdesc = lpfc_sli4_queue_alloc(
8868 phba,
81b96eda
JS
8869 LPFC_DEFAULT_PAGE_SIZE,
8870 phba->sli4_hba.cq_esize,
8871 phba->sli4_hba.cq_ecount);
cdb42bec
JS
8872 if (!qdesc) {
8873 lpfc_printf_log(
8874 phba, KERN_ERR, LOG_INIT,
8875 "3142 Failed allocate NVME "
8876 "CQ Set (%d)\n", idx);
8877 goto out_error;
8878 }
8879 qdesc->qe_valid = 1;
5e5b511d 8880 qdesc->hdwq = idx;
6a828b0f 8881 qdesc->chann = idx;
cdb42bec 8882 phba->sli4_hba.nvmet_cqset[idx] = qdesc;
2d7dbc4c 8883 }
2d7dbc4c
JS
8884 }
8885 }
8886
da0436e9 8887 /*
67d12733 8888 * Create Slow Path Completion Queues (CQs)
da0436e9
JS
8889 */
8890
da0436e9 8891 /* Create slow-path Mailbox Command Complete Queue */
81b96eda
JS
8892 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8893 phba->sli4_hba.cq_esize,
da0436e9
JS
8894 phba->sli4_hba.cq_ecount);
8895 if (!qdesc) {
8896 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8897 "0500 Failed allocate slow-path mailbox CQ\n");
67d12733 8898 goto out_error;
da0436e9 8899 }
7365f6fd 8900 qdesc->qe_valid = 1;
da0436e9
JS
8901 phba->sli4_hba.mbx_cq = qdesc;
8902
8903 /* Create slow-path ELS Complete Queue */
81b96eda
JS
8904 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8905 phba->sli4_hba.cq_esize,
da0436e9
JS
8906 phba->sli4_hba.cq_ecount);
8907 if (!qdesc) {
8908 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8909 "0501 Failed allocate slow-path ELS CQ\n");
67d12733 8910 goto out_error;
da0436e9 8911 }
7365f6fd 8912 qdesc->qe_valid = 1;
6a828b0f 8913 qdesc->chann = 0;
da0436e9
JS
8914 phba->sli4_hba.els_cq = qdesc;
8915
da0436e9 8916
5350d872 8917 /*
67d12733 8918 * Create Slow Path Work Queues (WQs)
5350d872 8919 */
da0436e9
JS
8920
8921 /* Create Mailbox Command Queue */
da0436e9 8922
81b96eda
JS
8923 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8924 phba->sli4_hba.mq_esize,
da0436e9
JS
8925 phba->sli4_hba.mq_ecount);
8926 if (!qdesc) {
8927 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8928 "0505 Failed allocate slow-path MQ\n");
67d12733 8929 goto out_error;
da0436e9 8930 }
6a828b0f 8931 qdesc->chann = 0;
da0436e9
JS
8932 phba->sli4_hba.mbx_wq = qdesc;
8933
8934 /*
67d12733 8935 * Create ELS Work Queues
da0436e9 8936 */
da0436e9
JS
8937
8938 /* Create slow-path ELS Work Queue */
81b96eda
JS
8939 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8940 phba->sli4_hba.wq_esize,
da0436e9
JS
8941 phba->sli4_hba.wq_ecount);
8942 if (!qdesc) {
8943 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8944 "0504 Failed allocate slow-path ELS WQ\n");
67d12733 8945 goto out_error;
da0436e9 8946 }
6a828b0f 8947 qdesc->chann = 0;
da0436e9 8948 phba->sli4_hba.els_wq = qdesc;
895427bd
JS
8949 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
8950
8951 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
8952 /* Create NVME LS Complete Queue */
81b96eda
JS
8953 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8954 phba->sli4_hba.cq_esize,
895427bd
JS
8955 phba->sli4_hba.cq_ecount);
8956 if (!qdesc) {
8957 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8958 "6079 Failed allocate NVME LS CQ\n");
8959 goto out_error;
8960 }
6a828b0f 8961 qdesc->chann = 0;
7365f6fd 8962 qdesc->qe_valid = 1;
895427bd
JS
8963 phba->sli4_hba.nvmels_cq = qdesc;
8964
8965 /* Create NVME LS Work Queue */
81b96eda
JS
8966 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8967 phba->sli4_hba.wq_esize,
895427bd
JS
8968 phba->sli4_hba.wq_ecount);
8969 if (!qdesc) {
8970 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8971 "6080 Failed allocate NVME LS WQ\n");
8972 goto out_error;
8973 }
6a828b0f 8974 qdesc->chann = 0;
895427bd
JS
8975 phba->sli4_hba.nvmels_wq = qdesc;
8976 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
8977 }
da0436e9 8978
da0436e9
JS
8979 /*
8980 * Create Receive Queue (RQ)
8981 */
da0436e9
JS
8982
8983 /* Create Receive Queue for header */
81b96eda
JS
8984 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8985 phba->sli4_hba.rq_esize,
da0436e9
JS
8986 phba->sli4_hba.rq_ecount);
8987 if (!qdesc) {
8988 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8989 "0506 Failed allocate receive HRQ\n");
67d12733 8990 goto out_error;
da0436e9
JS
8991 }
8992 phba->sli4_hba.hdr_rq = qdesc;
8993
8994 /* Create Receive Queue for data */
81b96eda
JS
8995 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8996 phba->sli4_hba.rq_esize,
da0436e9
JS
8997 phba->sli4_hba.rq_ecount);
8998 if (!qdesc) {
8999 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9000 "0507 Failed allocate receive DRQ\n");
67d12733 9001 goto out_error;
da0436e9
JS
9002 }
9003 phba->sli4_hba.dat_rq = qdesc;
9004
cdb42bec
JS
9005 if ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) &&
9006 phba->nvmet_support) {
2d7dbc4c
JS
9007 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
9008 /* Create NVMET Receive Queue for header */
9009 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda 9010 LPFC_DEFAULT_PAGE_SIZE,
2d7dbc4c 9011 phba->sli4_hba.rq_esize,
61f3d4bf 9012 LPFC_NVMET_RQE_DEF_COUNT);
2d7dbc4c
JS
9013 if (!qdesc) {
9014 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9015 "3146 Failed allocate "
9016 "receive HRQ\n");
9017 goto out_error;
9018 }
5e5b511d 9019 qdesc->hdwq = idx;
2d7dbc4c
JS
9020 phba->sli4_hba.nvmet_mrq_hdr[idx] = qdesc;
9021
9022 /* Only needed for header of RQ pair */
9023 qdesc->rqbp = kzalloc(sizeof(struct lpfc_rqb),
9024 GFP_KERNEL);
9025 if (qdesc->rqbp == NULL) {
9026 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9027 "6131 Failed allocate "
9028 "Header RQBP\n");
9029 goto out_error;
9030 }
9031
4b40d02b
DK
9032 /* Put list in known state in case driver load fails. */
9033 INIT_LIST_HEAD(&qdesc->rqbp->rqb_buffer_list);
9034
2d7dbc4c
JS
9035 /* Create NVMET Receive Queue for data */
9036 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda 9037 LPFC_DEFAULT_PAGE_SIZE,
2d7dbc4c 9038 phba->sli4_hba.rq_esize,
61f3d4bf 9039 LPFC_NVMET_RQE_DEF_COUNT);
2d7dbc4c
JS
9040 if (!qdesc) {
9041 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9042 "3156 Failed allocate "
9043 "receive DRQ\n");
9044 goto out_error;
9045 }
5e5b511d 9046 qdesc->hdwq = idx;
2d7dbc4c
JS
9047 phba->sli4_hba.nvmet_mrq_data[idx] = qdesc;
9048 }
9049 }
9050
4c47efc1
JS
9051#if defined(BUILD_NVME)
9052 /* Clear NVME stats */
9053 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
9054 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9055 memset(&phba->sli4_hba.hdwq[idx].nvme_cstat, 0,
9056 sizeof(phba->sli4_hba.hdwq[idx].nvme_cstat));
9057 }
9058 }
9059#endif
9060
9061 /* Clear SCSI stats */
9062 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
9063 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9064 memset(&phba->sli4_hba.hdwq[idx].scsi_cstat, 0,
9065 sizeof(phba->sli4_hba.hdwq[idx].scsi_cstat));
9066 }
9067 }
9068
da0436e9
JS
9069 return 0;
9070
da0436e9 9071out_error:
67d12733 9072 lpfc_sli4_queue_destroy(phba);
da0436e9
JS
9073 return -ENOMEM;
9074}
9075
895427bd
JS
9076static inline void
9077__lpfc_sli4_release_queue(struct lpfc_queue **qp)
9078{
9079 if (*qp != NULL) {
9080 lpfc_sli4_queue_free(*qp);
9081 *qp = NULL;
9082 }
9083}
9084
9085static inline void
9086lpfc_sli4_release_queues(struct lpfc_queue ***qs, int max)
9087{
9088 int idx;
9089
9090 if (*qs == NULL)
9091 return;
9092
9093 for (idx = 0; idx < max; idx++)
9094 __lpfc_sli4_release_queue(&(*qs)[idx]);
9095
9096 kfree(*qs);
9097 *qs = NULL;
9098}
9099
9100static inline void
6a828b0f 9101lpfc_sli4_release_hdwq(struct lpfc_hba *phba)
895427bd 9102{
6a828b0f 9103 struct lpfc_sli4_hdw_queue *hdwq;
cdb42bec
JS
9104 uint32_t idx;
9105
6a828b0f
JS
9106 hdwq = phba->sli4_hba.hdwq;
9107 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9108 if (idx < phba->cfg_irq_chann)
9109 lpfc_sli4_queue_free(hdwq[idx].hba_eq);
9110 hdwq[idx].hba_eq = NULL;
9111
cdb42bec
JS
9112 lpfc_sli4_queue_free(hdwq[idx].fcp_cq);
9113 lpfc_sli4_queue_free(hdwq[idx].nvme_cq);
9114 lpfc_sli4_queue_free(hdwq[idx].fcp_wq);
9115 lpfc_sli4_queue_free(hdwq[idx].nvme_wq);
cdb42bec
JS
9116 hdwq[idx].fcp_cq = NULL;
9117 hdwq[idx].nvme_cq = NULL;
9118 hdwq[idx].fcp_wq = NULL;
9119 hdwq[idx].nvme_wq = NULL;
895427bd
JS
9120 }
9121}
9122
da0436e9
JS
9123/**
9124 * lpfc_sli4_queue_destroy - Destroy all the SLI4 queues
9125 * @phba: pointer to lpfc hba data structure.
9126 *
9127 * This routine is invoked to release all the SLI4 queues with the FCoE HBA
9128 * operation.
9129 *
9130 * Return codes
af901ca1 9131 * 0 - successful
25985edc 9132 * -ENOMEM - No available memory
d439d286 9133 * -EIO - The mailbox failed to complete successfully.
da0436e9 9134 **/
5350d872 9135void
da0436e9
JS
9136lpfc_sli4_queue_destroy(struct lpfc_hba *phba)
9137{
4645f7b5
JS
9138 /*
9139 * Set FREE_INIT before beginning to free the queues.
9140 * Wait until the users of queues to acknowledge to
9141 * release queues by clearing FREE_WAIT.
9142 */
9143 spin_lock_irq(&phba->hbalock);
9144 phba->sli.sli_flag |= LPFC_QUEUE_FREE_INIT;
9145 while (phba->sli.sli_flag & LPFC_QUEUE_FREE_WAIT) {
9146 spin_unlock_irq(&phba->hbalock);
9147 msleep(20);
9148 spin_lock_irq(&phba->hbalock);
9149 }
9150 spin_unlock_irq(&phba->hbalock);
9151
895427bd 9152 /* Release HBA eqs */
cdb42bec 9153 if (phba->sli4_hba.hdwq)
6a828b0f 9154 lpfc_sli4_release_hdwq(phba);
895427bd 9155
bcb24f65
JS
9156 if (phba->nvmet_support) {
9157 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_cqset,
9158 phba->cfg_nvmet_mrq);
2d7dbc4c 9159
bcb24f65
JS
9160 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_hdr,
9161 phba->cfg_nvmet_mrq);
9162 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_data,
9163 phba->cfg_nvmet_mrq);
9164 }
2d7dbc4c 9165
895427bd
JS
9166 /* Release mailbox command work queue */
9167 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_wq);
9168
9169 /* Release ELS work queue */
9170 __lpfc_sli4_release_queue(&phba->sli4_hba.els_wq);
9171
9172 /* Release ELS work queue */
9173 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_wq);
9174
9175 /* Release unsolicited receive queue */
9176 __lpfc_sli4_release_queue(&phba->sli4_hba.hdr_rq);
9177 __lpfc_sli4_release_queue(&phba->sli4_hba.dat_rq);
9178
9179 /* Release ELS complete queue */
9180 __lpfc_sli4_release_queue(&phba->sli4_hba.els_cq);
9181
9182 /* Release NVME LS complete queue */
9183 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_cq);
9184
9185 /* Release mailbox command complete queue */
9186 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_cq);
9187
9188 /* Everything on this list has been freed */
9189 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
4645f7b5
JS
9190
9191 /* Done with freeing the queues */
9192 spin_lock_irq(&phba->hbalock);
9193 phba->sli.sli_flag &= ~LPFC_QUEUE_FREE_INIT;
9194 spin_unlock_irq(&phba->hbalock);
895427bd
JS
9195}
9196
895427bd
JS
9197int
9198lpfc_free_rq_buffer(struct lpfc_hba *phba, struct lpfc_queue *rq)
9199{
9200 struct lpfc_rqb *rqbp;
9201 struct lpfc_dmabuf *h_buf;
9202 struct rqb_dmabuf *rqb_buffer;
9203
9204 rqbp = rq->rqbp;
9205 while (!list_empty(&rqbp->rqb_buffer_list)) {
9206 list_remove_head(&rqbp->rqb_buffer_list, h_buf,
9207 struct lpfc_dmabuf, list);
9208
9209 rqb_buffer = container_of(h_buf, struct rqb_dmabuf, hbuf);
9210 (rqbp->rqb_free_buffer)(phba, rqb_buffer);
9211 rqbp->buffer_count--;
67d12733 9212 }
895427bd
JS
9213 return 1;
9214}
67d12733 9215
895427bd
JS
9216static int
9217lpfc_create_wq_cq(struct lpfc_hba *phba, struct lpfc_queue *eq,
9218 struct lpfc_queue *cq, struct lpfc_queue *wq, uint16_t *cq_map,
9219 int qidx, uint32_t qtype)
9220{
9221 struct lpfc_sli_ring *pring;
9222 int rc;
9223
9224 if (!eq || !cq || !wq) {
9225 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9226 "6085 Fast-path %s (%d) not allocated\n",
9227 ((eq) ? ((cq) ? "WQ" : "CQ") : "EQ"), qidx);
9228 return -ENOMEM;
9229 }
9230
9231 /* create the Cq first */
9232 rc = lpfc_cq_create(phba, cq, eq,
9233 (qtype == LPFC_MBOX) ? LPFC_MCQ : LPFC_WCQ, qtype);
9234 if (rc) {
9235 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9236 "6086 Failed setup of CQ (%d), rc = 0x%x\n",
9237 qidx, (uint32_t)rc);
9238 return rc;
67d12733
JS
9239 }
9240
895427bd 9241 if (qtype != LPFC_MBOX) {
cdb42bec 9242 /* Setup cq_map for fast lookup */
895427bd
JS
9243 if (cq_map)
9244 *cq_map = cq->queue_id;
da0436e9 9245
895427bd
JS
9246 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9247 "6087 CQ setup: cq[%d]-id=%d, parent eq[%d]-id=%d\n",
9248 qidx, cq->queue_id, qidx, eq->queue_id);
da0436e9 9249
895427bd
JS
9250 /* create the wq */
9251 rc = lpfc_wq_create(phba, wq, cq, qtype);
9252 if (rc) {
9253 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9254 "6123 Fail setup fastpath WQ (%d), rc = 0x%x\n",
9255 qidx, (uint32_t)rc);
9256 /* no need to tear down cq - caller will do so */
9257 return rc;
9258 }
da0436e9 9259
895427bd
JS
9260 /* Bind this CQ/WQ to the NVME ring */
9261 pring = wq->pring;
9262 pring->sli.sli4.wqp = (void *)wq;
9263 cq->pring = pring;
da0436e9 9264
895427bd
JS
9265 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9266 "2593 WQ setup: wq[%d]-id=%d assoc=%d, cq[%d]-id=%d\n",
9267 qidx, wq->queue_id, wq->assoc_qid, qidx, cq->queue_id);
9268 } else {
9269 rc = lpfc_mq_create(phba, wq, cq, LPFC_MBOX);
9270 if (rc) {
9271 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9272 "0539 Failed setup of slow-path MQ: "
9273 "rc = 0x%x\n", rc);
9274 /* no need to tear down cq - caller will do so */
9275 return rc;
9276 }
da0436e9 9277
895427bd
JS
9278 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9279 "2589 MBX MQ setup: wq-id=%d, parent cq-id=%d\n",
9280 phba->sli4_hba.mbx_wq->queue_id,
9281 phba->sli4_hba.mbx_cq->queue_id);
67d12733 9282 }
da0436e9 9283
895427bd 9284 return 0;
da0436e9
JS
9285}
9286
6a828b0f
JS
9287/**
9288 * lpfc_setup_cq_lookup - Setup the CQ lookup table
9289 * @phba: pointer to lpfc hba data structure.
9290 *
9291 * This routine will populate the cq_lookup table by all
9292 * available CQ queue_id's.
9293 **/
9294void
9295lpfc_setup_cq_lookup(struct lpfc_hba *phba)
9296{
9297 struct lpfc_queue *eq, *childq;
9298 struct lpfc_sli4_hdw_queue *qp;
9299 int qidx;
9300
9301 qp = phba->sli4_hba.hdwq;
9302 memset(phba->sli4_hba.cq_lookup, 0,
9303 (sizeof(struct lpfc_queue *) * (phba->sli4_hba.cq_max + 1)));
9304 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
9305 eq = qp[qidx].hba_eq;
9306 if (!eq)
9307 continue;
9308 list_for_each_entry(childq, &eq->child_list, list) {
9309 if (childq->queue_id > phba->sli4_hba.cq_max)
9310 continue;
9311 if ((childq->subtype == LPFC_FCP) ||
9312 (childq->subtype == LPFC_NVME))
9313 phba->sli4_hba.cq_lookup[childq->queue_id] =
9314 childq;
9315 }
9316 }
9317}
9318
da0436e9
JS
9319/**
9320 * lpfc_sli4_queue_setup - Set up all the SLI4 queues
9321 * @phba: pointer to lpfc hba data structure.
9322 *
9323 * This routine is invoked to set up all the SLI4 queues for the FCoE HBA
9324 * operation.
9325 *
9326 * Return codes
af901ca1 9327 * 0 - successful
25985edc 9328 * -ENOMEM - No available memory
d439d286 9329 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
9330 **/
9331int
9332lpfc_sli4_queue_setup(struct lpfc_hba *phba)
9333{
962bc51b
JS
9334 uint32_t shdr_status, shdr_add_status;
9335 union lpfc_sli4_cfg_shdr *shdr;
cdb42bec 9336 struct lpfc_sli4_hdw_queue *qp;
962bc51b 9337 LPFC_MBOXQ_t *mboxq;
895427bd 9338 int qidx;
cb733e35 9339 uint32_t length, usdelay;
895427bd 9340 int rc = -ENOMEM;
962bc51b
JS
9341
9342 /* Check for dual-ULP support */
9343 mboxq = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9344 if (!mboxq) {
9345 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9346 "3249 Unable to allocate memory for "
9347 "QUERY_FW_CFG mailbox command\n");
9348 return -ENOMEM;
9349 }
9350 length = (sizeof(struct lpfc_mbx_query_fw_config) -
9351 sizeof(struct lpfc_sli4_cfg_mhdr));
9352 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
9353 LPFC_MBOX_OPCODE_QUERY_FW_CFG,
9354 length, LPFC_SLI4_MBX_EMBED);
9355
9356 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
9357
9358 shdr = (union lpfc_sli4_cfg_shdr *)
9359 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
9360 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
9361 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
9362 if (shdr_status || shdr_add_status || rc) {
9363 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9364 "3250 QUERY_FW_CFG mailbox failed with status "
9365 "x%x add_status x%x, mbx status x%x\n",
9366 shdr_status, shdr_add_status, rc);
9367 if (rc != MBX_TIMEOUT)
9368 mempool_free(mboxq, phba->mbox_mem_pool);
9369 rc = -ENXIO;
9370 goto out_error;
9371 }
9372
9373 phba->sli4_hba.fw_func_mode =
9374 mboxq->u.mqe.un.query_fw_cfg.rsp.function_mode;
9375 phba->sli4_hba.ulp0_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp0_mode;
9376 phba->sli4_hba.ulp1_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp1_mode;
8b017a30
JS
9377 phba->sli4_hba.physical_port =
9378 mboxq->u.mqe.un.query_fw_cfg.rsp.physical_port;
962bc51b
JS
9379 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9380 "3251 QUERY_FW_CFG: func_mode:x%x, ulp0_mode:x%x, "
9381 "ulp1_mode:x%x\n", phba->sli4_hba.fw_func_mode,
9382 phba->sli4_hba.ulp0_mode, phba->sli4_hba.ulp1_mode);
9383
9384 if (rc != MBX_TIMEOUT)
9385 mempool_free(mboxq, phba->mbox_mem_pool);
da0436e9
JS
9386
9387 /*
67d12733 9388 * Set up HBA Event Queues (EQs)
da0436e9 9389 */
cdb42bec 9390 qp = phba->sli4_hba.hdwq;
da0436e9 9391
67d12733 9392 /* Set up HBA event queue */
cdb42bec 9393 if (!qp) {
2e90f4b5
JS
9394 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9395 "3147 Fast-path EQs not allocated\n");
1b51197d 9396 rc = -ENOMEM;
67d12733 9397 goto out_error;
2e90f4b5 9398 }
6a828b0f 9399 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
cdb42bec 9400 if (!qp[qidx].hba_eq) {
da0436e9
JS
9401 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9402 "0522 Fast-path EQ (%d) not "
895427bd 9403 "allocated\n", qidx);
1b51197d 9404 rc = -ENOMEM;
895427bd 9405 goto out_destroy;
da0436e9 9406 }
cdb42bec
JS
9407 rc = lpfc_eq_create(phba, qp[qidx].hba_eq,
9408 phba->cfg_fcp_imax);
da0436e9
JS
9409 if (rc) {
9410 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9411 "0523 Failed setup of fast-path EQ "
895427bd 9412 "(%d), rc = 0x%x\n", qidx,
a2fc4aef 9413 (uint32_t)rc);
895427bd 9414 goto out_destroy;
da0436e9
JS
9415 }
9416 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
cdb42bec
JS
9417 "2584 HBA EQ setup: queue[%d]-id=%d\n", qidx,
9418 qp[qidx].hba_eq->queue_id);
67d12733
JS
9419 }
9420
cdb42bec
JS
9421 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
9422 for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {
895427bd 9423 rc = lpfc_create_wq_cq(phba,
cdb42bec
JS
9424 qp[qidx].hba_eq,
9425 qp[qidx].nvme_cq,
9426 qp[qidx].nvme_wq,
9427 &phba->sli4_hba.hdwq[qidx].nvme_cq_map,
895427bd
JS
9428 qidx, LPFC_NVME);
9429 if (rc) {
9430 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9431 "6123 Failed to setup fastpath "
9432 "NVME WQ/CQ (%d), rc = 0x%x\n",
9433 qidx, (uint32_t)rc);
9434 goto out_destroy;
9435 }
9436 }
67d12733
JS
9437 }
9438
cdb42bec
JS
9439 for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {
9440 rc = lpfc_create_wq_cq(phba,
9441 qp[qidx].hba_eq,
9442 qp[qidx].fcp_cq,
9443 qp[qidx].fcp_wq,
9444 &phba->sli4_hba.hdwq[qidx].fcp_cq_map,
9445 qidx, LPFC_FCP);
9446 if (rc) {
67d12733 9447 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
895427bd
JS
9448 "0535 Failed to setup fastpath "
9449 "FCP WQ/CQ (%d), rc = 0x%x\n",
9450 qidx, (uint32_t)rc);
cdb42bec 9451 goto out_destroy;
895427bd 9452 }
67d12733 9453 }
895427bd 9454
da0436e9 9455 /*
895427bd 9456 * Set up Slow Path Complete Queues (CQs)
da0436e9
JS
9457 */
9458
895427bd 9459 /* Set up slow-path MBOX CQ/MQ */
da0436e9 9460
895427bd 9461 if (!phba->sli4_hba.mbx_cq || !phba->sli4_hba.mbx_wq) {
da0436e9 9462 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
895427bd
JS
9463 "0528 %s not allocated\n",
9464 phba->sli4_hba.mbx_cq ?
d1f525aa 9465 "Mailbox WQ" : "Mailbox CQ");
1b51197d 9466 rc = -ENOMEM;
895427bd 9467 goto out_destroy;
da0436e9 9468 }
da0436e9 9469
cdb42bec 9470 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
d1f525aa
JS
9471 phba->sli4_hba.mbx_cq,
9472 phba->sli4_hba.mbx_wq,
9473 NULL, 0, LPFC_MBOX);
da0436e9
JS
9474 if (rc) {
9475 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
895427bd
JS
9476 "0529 Failed setup of mailbox WQ/CQ: rc = 0x%x\n",
9477 (uint32_t)rc);
9478 goto out_destroy;
da0436e9 9479 }
2d7dbc4c
JS
9480 if (phba->nvmet_support) {
9481 if (!phba->sli4_hba.nvmet_cqset) {
9482 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9483 "3165 Fast-path NVME CQ Set "
9484 "array not allocated\n");
9485 rc = -ENOMEM;
9486 goto out_destroy;
9487 }
9488 if (phba->cfg_nvmet_mrq > 1) {
9489 rc = lpfc_cq_create_set(phba,
9490 phba->sli4_hba.nvmet_cqset,
cdb42bec 9491 qp,
2d7dbc4c
JS
9492 LPFC_WCQ, LPFC_NVMET);
9493 if (rc) {
9494 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9495 "3164 Failed setup of NVME CQ "
9496 "Set, rc = 0x%x\n",
9497 (uint32_t)rc);
9498 goto out_destroy;
9499 }
9500 } else {
9501 /* Set up NVMET Receive Complete Queue */
9502 rc = lpfc_cq_create(phba, phba->sli4_hba.nvmet_cqset[0],
cdb42bec 9503 qp[0].hba_eq,
2d7dbc4c
JS
9504 LPFC_WCQ, LPFC_NVMET);
9505 if (rc) {
9506 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9507 "6089 Failed setup NVMET CQ: "
9508 "rc = 0x%x\n", (uint32_t)rc);
9509 goto out_destroy;
9510 }
81b96eda
JS
9511 phba->sli4_hba.nvmet_cqset[0]->chann = 0;
9512
2d7dbc4c
JS
9513 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9514 "6090 NVMET CQ setup: cq-id=%d, "
9515 "parent eq-id=%d\n",
9516 phba->sli4_hba.nvmet_cqset[0]->queue_id,
cdb42bec 9517 qp[0].hba_eq->queue_id);
2d7dbc4c
JS
9518 }
9519 }
da0436e9 9520
895427bd
JS
9521 /* Set up slow-path ELS WQ/CQ */
9522 if (!phba->sli4_hba.els_cq || !phba->sli4_hba.els_wq) {
da0436e9 9523 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
895427bd
JS
9524 "0530 ELS %s not allocated\n",
9525 phba->sli4_hba.els_cq ? "WQ" : "CQ");
1b51197d 9526 rc = -ENOMEM;
895427bd 9527 goto out_destroy;
da0436e9 9528 }
cdb42bec
JS
9529 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
9530 phba->sli4_hba.els_cq,
9531 phba->sli4_hba.els_wq,
9532 NULL, 0, LPFC_ELS);
da0436e9
JS
9533 if (rc) {
9534 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
cdb42bec
JS
9535 "0525 Failed setup of ELS WQ/CQ: rc = 0x%x\n",
9536 (uint32_t)rc);
895427bd 9537 goto out_destroy;
da0436e9
JS
9538 }
9539 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9540 "2590 ELS WQ setup: wq-id=%d, parent cq-id=%d\n",
9541 phba->sli4_hba.els_wq->queue_id,
9542 phba->sli4_hba.els_cq->queue_id);
9543
cdb42bec 9544 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
895427bd
JS
9545 /* Set up NVME LS Complete Queue */
9546 if (!phba->sli4_hba.nvmels_cq || !phba->sli4_hba.nvmels_wq) {
9547 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9548 "6091 LS %s not allocated\n",
9549 phba->sli4_hba.nvmels_cq ? "WQ" : "CQ");
9550 rc = -ENOMEM;
9551 goto out_destroy;
9552 }
cdb42bec
JS
9553 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
9554 phba->sli4_hba.nvmels_cq,
9555 phba->sli4_hba.nvmels_wq,
9556 NULL, 0, LPFC_NVME_LS);
895427bd
JS
9557 if (rc) {
9558 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
cdb42bec
JS
9559 "0526 Failed setup of NVVME LS WQ/CQ: "
9560 "rc = 0x%x\n", (uint32_t)rc);
895427bd
JS
9561 goto out_destroy;
9562 }
9563
9564 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9565 "6096 ELS WQ setup: wq-id=%d, "
9566 "parent cq-id=%d\n",
9567 phba->sli4_hba.nvmels_wq->queue_id,
9568 phba->sli4_hba.nvmels_cq->queue_id);
9569 }
9570
2d7dbc4c
JS
9571 /*
9572 * Create NVMET Receive Queue (RQ)
9573 */
9574 if (phba->nvmet_support) {
9575 if ((!phba->sli4_hba.nvmet_cqset) ||
9576 (!phba->sli4_hba.nvmet_mrq_hdr) ||
9577 (!phba->sli4_hba.nvmet_mrq_data)) {
9578 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9579 "6130 MRQ CQ Queues not "
9580 "allocated\n");
9581 rc = -ENOMEM;
9582 goto out_destroy;
9583 }
9584 if (phba->cfg_nvmet_mrq > 1) {
9585 rc = lpfc_mrq_create(phba,
9586 phba->sli4_hba.nvmet_mrq_hdr,
9587 phba->sli4_hba.nvmet_mrq_data,
9588 phba->sli4_hba.nvmet_cqset,
9589 LPFC_NVMET);
9590 if (rc) {
9591 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9592 "6098 Failed setup of NVMET "
9593 "MRQ: rc = 0x%x\n",
9594 (uint32_t)rc);
9595 goto out_destroy;
9596 }
9597
9598 } else {
9599 rc = lpfc_rq_create(phba,
9600 phba->sli4_hba.nvmet_mrq_hdr[0],
9601 phba->sli4_hba.nvmet_mrq_data[0],
9602 phba->sli4_hba.nvmet_cqset[0],
9603 LPFC_NVMET);
9604 if (rc) {
9605 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9606 "6057 Failed setup of NVMET "
9607 "Receive Queue: rc = 0x%x\n",
9608 (uint32_t)rc);
9609 goto out_destroy;
9610 }
9611
9612 lpfc_printf_log(
9613 phba, KERN_INFO, LOG_INIT,
9614 "6099 NVMET RQ setup: hdr-rq-id=%d, "
9615 "dat-rq-id=%d parent cq-id=%d\n",
9616 phba->sli4_hba.nvmet_mrq_hdr[0]->queue_id,
9617 phba->sli4_hba.nvmet_mrq_data[0]->queue_id,
9618 phba->sli4_hba.nvmet_cqset[0]->queue_id);
9619
9620 }
9621 }
9622
da0436e9
JS
9623 if (!phba->sli4_hba.hdr_rq || !phba->sli4_hba.dat_rq) {
9624 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9625 "0540 Receive Queue not allocated\n");
1b51197d 9626 rc = -ENOMEM;
895427bd 9627 goto out_destroy;
da0436e9 9628 }
73d91e50 9629
da0436e9 9630 rc = lpfc_rq_create(phba, phba->sli4_hba.hdr_rq, phba->sli4_hba.dat_rq,
4d9ab994 9631 phba->sli4_hba.els_cq, LPFC_USOL);
da0436e9
JS
9632 if (rc) {
9633 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9634 "0541 Failed setup of Receive Queue: "
a2fc4aef 9635 "rc = 0x%x\n", (uint32_t)rc);
895427bd 9636 goto out_destroy;
da0436e9 9637 }
73d91e50 9638
da0436e9
JS
9639 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9640 "2592 USL RQ setup: hdr-rq-id=%d, dat-rq-id=%d "
9641 "parent cq-id=%d\n",
9642 phba->sli4_hba.hdr_rq->queue_id,
9643 phba->sli4_hba.dat_rq->queue_id,
4d9ab994 9644 phba->sli4_hba.els_cq->queue_id);
1ba981fd 9645
cb733e35
JS
9646 if (phba->cfg_fcp_imax)
9647 usdelay = LPFC_SEC_TO_USEC / phba->cfg_fcp_imax;
9648 else
9649 usdelay = 0;
9650
6a828b0f 9651 for (qidx = 0; qidx < phba->cfg_irq_chann;
cdb42bec 9652 qidx += LPFC_MAX_EQ_DELAY_EQID_CNT)
0cf07f84 9653 lpfc_modify_hba_eq_delay(phba, qidx, LPFC_MAX_EQ_DELAY_EQID_CNT,
cb733e35 9654 usdelay);
43140ca6 9655
6a828b0f
JS
9656 if (phba->sli4_hba.cq_max) {
9657 kfree(phba->sli4_hba.cq_lookup);
9658 phba->sli4_hba.cq_lookup = kcalloc((phba->sli4_hba.cq_max + 1),
9659 sizeof(struct lpfc_queue *), GFP_KERNEL);
9660 if (!phba->sli4_hba.cq_lookup) {
1ba981fd 9661 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6a828b0f
JS
9662 "0549 Failed setup of CQ Lookup table: "
9663 "size 0x%x\n", phba->sli4_hba.cq_max);
fad28e3d 9664 rc = -ENOMEM;
895427bd 9665 goto out_destroy;
1ba981fd 9666 }
6a828b0f 9667 lpfc_setup_cq_lookup(phba);
1ba981fd 9668 }
da0436e9
JS
9669 return 0;
9670
895427bd
JS
9671out_destroy:
9672 lpfc_sli4_queue_unset(phba);
da0436e9
JS
9673out_error:
9674 return rc;
9675}
9676
9677/**
9678 * lpfc_sli4_queue_unset - Unset all the SLI4 queues
9679 * @phba: pointer to lpfc hba data structure.
9680 *
9681 * This routine is invoked to unset all the SLI4 queues with the FCoE HBA
9682 * operation.
9683 *
9684 * Return codes
af901ca1 9685 * 0 - successful
25985edc 9686 * -ENOMEM - No available memory
d439d286 9687 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
9688 **/
9689void
9690lpfc_sli4_queue_unset(struct lpfc_hba *phba)
9691{
cdb42bec 9692 struct lpfc_sli4_hdw_queue *qp;
895427bd 9693 int qidx;
da0436e9
JS
9694
9695 /* Unset mailbox command work queue */
895427bd
JS
9696 if (phba->sli4_hba.mbx_wq)
9697 lpfc_mq_destroy(phba, phba->sli4_hba.mbx_wq);
9698
9699 /* Unset NVME LS work queue */
9700 if (phba->sli4_hba.nvmels_wq)
9701 lpfc_wq_destroy(phba, phba->sli4_hba.nvmels_wq);
9702
da0436e9 9703 /* Unset ELS work queue */
019c0d66 9704 if (phba->sli4_hba.els_wq)
895427bd
JS
9705 lpfc_wq_destroy(phba, phba->sli4_hba.els_wq);
9706
da0436e9 9707 /* Unset unsolicited receive queue */
895427bd
JS
9708 if (phba->sli4_hba.hdr_rq)
9709 lpfc_rq_destroy(phba, phba->sli4_hba.hdr_rq,
9710 phba->sli4_hba.dat_rq);
9711
da0436e9 9712 /* Unset mailbox command complete queue */
895427bd
JS
9713 if (phba->sli4_hba.mbx_cq)
9714 lpfc_cq_destroy(phba, phba->sli4_hba.mbx_cq);
9715
da0436e9 9716 /* Unset ELS complete queue */
895427bd
JS
9717 if (phba->sli4_hba.els_cq)
9718 lpfc_cq_destroy(phba, phba->sli4_hba.els_cq);
9719
9720 /* Unset NVME LS complete queue */
9721 if (phba->sli4_hba.nvmels_cq)
9722 lpfc_cq_destroy(phba, phba->sli4_hba.nvmels_cq);
9723
bcb24f65
JS
9724 if (phba->nvmet_support) {
9725 /* Unset NVMET MRQ queue */
9726 if (phba->sli4_hba.nvmet_mrq_hdr) {
9727 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
9728 lpfc_rq_destroy(
9729 phba,
2d7dbc4c
JS
9730 phba->sli4_hba.nvmet_mrq_hdr[qidx],
9731 phba->sli4_hba.nvmet_mrq_data[qidx]);
bcb24f65 9732 }
2d7dbc4c 9733
bcb24f65
JS
9734 /* Unset NVMET CQ Set complete queue */
9735 if (phba->sli4_hba.nvmet_cqset) {
9736 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
9737 lpfc_cq_destroy(
9738 phba, phba->sli4_hba.nvmet_cqset[qidx]);
9739 }
2d7dbc4c
JS
9740 }
9741
cdb42bec
JS
9742 /* Unset fast-path SLI4 queues */
9743 if (phba->sli4_hba.hdwq) {
9744 for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {
9745 qp = &phba->sli4_hba.hdwq[qidx];
9746 lpfc_wq_destroy(phba, qp->fcp_wq);
9747 lpfc_wq_destroy(phba, qp->nvme_wq);
9748 lpfc_cq_destroy(phba, qp->fcp_cq);
9749 lpfc_cq_destroy(phba, qp->nvme_cq);
6a828b0f
JS
9750 if (qidx < phba->cfg_irq_chann)
9751 lpfc_eq_destroy(phba, qp->hba_eq);
cdb42bec
JS
9752 }
9753 }
895427bd 9754
6a828b0f
JS
9755 kfree(phba->sli4_hba.cq_lookup);
9756 phba->sli4_hba.cq_lookup = NULL;
9757 phba->sli4_hba.cq_max = 0;
da0436e9
JS
9758}
9759
9760/**
9761 * lpfc_sli4_cq_event_pool_create - Create completion-queue event free pool
9762 * @phba: pointer to lpfc hba data structure.
9763 *
9764 * This routine is invoked to allocate and set up a pool of completion queue
9765 * events. The body of the completion queue event is a completion queue entry
9766 * CQE. For now, this pool is used for the interrupt service routine to queue
9767 * the following HBA completion queue events for the worker thread to process:
9768 * - Mailbox asynchronous events
9769 * - Receive queue completion unsolicited events
9770 * Later, this can be used for all the slow-path events.
9771 *
9772 * Return codes
af901ca1 9773 * 0 - successful
25985edc 9774 * -ENOMEM - No available memory
da0436e9
JS
9775 **/
9776static int
9777lpfc_sli4_cq_event_pool_create(struct lpfc_hba *phba)
9778{
9779 struct lpfc_cq_event *cq_event;
9780 int i;
9781
9782 for (i = 0; i < (4 * phba->sli4_hba.cq_ecount); i++) {
9783 cq_event = kmalloc(sizeof(struct lpfc_cq_event), GFP_KERNEL);
9784 if (!cq_event)
9785 goto out_pool_create_fail;
9786 list_add_tail(&cq_event->list,
9787 &phba->sli4_hba.sp_cqe_event_pool);
9788 }
9789 return 0;
9790
9791out_pool_create_fail:
9792 lpfc_sli4_cq_event_pool_destroy(phba);
9793 return -ENOMEM;
9794}
9795
9796/**
9797 * lpfc_sli4_cq_event_pool_destroy - Free completion-queue event free pool
9798 * @phba: pointer to lpfc hba data structure.
9799 *
9800 * This routine is invoked to free the pool of completion queue events at
9801 * driver unload time. Note that, it is the responsibility of the driver
9802 * cleanup routine to free all the outstanding completion-queue events
9803 * allocated from this pool back into the pool before invoking this routine
9804 * to destroy the pool.
9805 **/
9806static void
9807lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *phba)
9808{
9809 struct lpfc_cq_event *cq_event, *next_cq_event;
9810
9811 list_for_each_entry_safe(cq_event, next_cq_event,
9812 &phba->sli4_hba.sp_cqe_event_pool, list) {
9813 list_del(&cq_event->list);
9814 kfree(cq_event);
9815 }
9816}
9817
9818/**
9819 * __lpfc_sli4_cq_event_alloc - Allocate a completion-queue event from free pool
9820 * @phba: pointer to lpfc hba data structure.
9821 *
9822 * This routine is the lock free version of the API invoked to allocate a
9823 * completion-queue event from the free pool.
9824 *
9825 * Return: Pointer to the newly allocated completion-queue event if successful
9826 * NULL otherwise.
9827 **/
9828struct lpfc_cq_event *
9829__lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
9830{
9831 struct lpfc_cq_event *cq_event = NULL;
9832
9833 list_remove_head(&phba->sli4_hba.sp_cqe_event_pool, cq_event,
9834 struct lpfc_cq_event, list);
9835 return cq_event;
9836}
9837
9838/**
9839 * lpfc_sli4_cq_event_alloc - Allocate a completion-queue event from free pool
9840 * @phba: pointer to lpfc hba data structure.
9841 *
9842 * This routine is the lock version of the API invoked to allocate a
9843 * completion-queue event from the free pool.
9844 *
9845 * Return: Pointer to the newly allocated completion-queue event if successful
9846 * NULL otherwise.
9847 **/
9848struct lpfc_cq_event *
9849lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
9850{
9851 struct lpfc_cq_event *cq_event;
9852 unsigned long iflags;
9853
9854 spin_lock_irqsave(&phba->hbalock, iflags);
9855 cq_event = __lpfc_sli4_cq_event_alloc(phba);
9856 spin_unlock_irqrestore(&phba->hbalock, iflags);
9857 return cq_event;
9858}
9859
9860/**
9861 * __lpfc_sli4_cq_event_release - Release a completion-queue event to free pool
9862 * @phba: pointer to lpfc hba data structure.
9863 * @cq_event: pointer to the completion queue event to be freed.
9864 *
9865 * This routine is the lock free version of the API invoked to release a
9866 * completion-queue event back into the free pool.
9867 **/
9868void
9869__lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
9870 struct lpfc_cq_event *cq_event)
9871{
9872 list_add_tail(&cq_event->list, &phba->sli4_hba.sp_cqe_event_pool);
9873}
9874
9875/**
9876 * lpfc_sli4_cq_event_release - Release a completion-queue event to free pool
9877 * @phba: pointer to lpfc hba data structure.
9878 * @cq_event: pointer to the completion queue event to be freed.
9879 *
9880 * This routine is the lock version of the API invoked to release a
9881 * completion-queue event back into the free pool.
9882 **/
9883void
9884lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
9885 struct lpfc_cq_event *cq_event)
9886{
9887 unsigned long iflags;
9888 spin_lock_irqsave(&phba->hbalock, iflags);
9889 __lpfc_sli4_cq_event_release(phba, cq_event);
9890 spin_unlock_irqrestore(&phba->hbalock, iflags);
9891}
9892
9893/**
9894 * lpfc_sli4_cq_event_release_all - Release all cq events to the free pool
9895 * @phba: pointer to lpfc hba data structure.
9896 *
9897 * This routine is to free all the pending completion-queue events to the
9898 * back into the free pool for device reset.
9899 **/
9900static void
9901lpfc_sli4_cq_event_release_all(struct lpfc_hba *phba)
9902{
9903 LIST_HEAD(cqelist);
9904 struct lpfc_cq_event *cqe;
9905 unsigned long iflags;
9906
9907 /* Retrieve all the pending WCQEs from pending WCQE lists */
9908 spin_lock_irqsave(&phba->hbalock, iflags);
9909 /* Pending FCP XRI abort events */
9910 list_splice_init(&phba->sli4_hba.sp_fcp_xri_aborted_work_queue,
9911 &cqelist);
9912 /* Pending ELS XRI abort events */
9913 list_splice_init(&phba->sli4_hba.sp_els_xri_aborted_work_queue,
9914 &cqelist);
9915 /* Pending asynnc events */
9916 list_splice_init(&phba->sli4_hba.sp_asynce_work_queue,
9917 &cqelist);
9918 spin_unlock_irqrestore(&phba->hbalock, iflags);
9919
9920 while (!list_empty(&cqelist)) {
9921 list_remove_head(&cqelist, cqe, struct lpfc_cq_event, list);
9922 lpfc_sli4_cq_event_release(phba, cqe);
9923 }
9924}
9925
9926/**
9927 * lpfc_pci_function_reset - Reset pci function.
9928 * @phba: pointer to lpfc hba data structure.
9929 *
9930 * This routine is invoked to request a PCI function reset. It will destroys
9931 * all resources assigned to the PCI function which originates this request.
9932 *
9933 * Return codes
af901ca1 9934 * 0 - successful
25985edc 9935 * -ENOMEM - No available memory
d439d286 9936 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
9937 **/
9938int
9939lpfc_pci_function_reset(struct lpfc_hba *phba)
9940{
9941 LPFC_MBOXQ_t *mboxq;
2fcee4bf 9942 uint32_t rc = 0, if_type;
da0436e9 9943 uint32_t shdr_status, shdr_add_status;
2f6fa2c9
JS
9944 uint32_t rdy_chk;
9945 uint32_t port_reset = 0;
da0436e9 9946 union lpfc_sli4_cfg_shdr *shdr;
2fcee4bf 9947 struct lpfc_register reg_data;
2b81f942 9948 uint16_t devid;
da0436e9 9949
2fcee4bf
JS
9950 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
9951 switch (if_type) {
9952 case LPFC_SLI_INTF_IF_TYPE_0:
9953 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
9954 GFP_KERNEL);
9955 if (!mboxq) {
9956 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9957 "0494 Unable to allocate memory for "
9958 "issuing SLI_FUNCTION_RESET mailbox "
9959 "command\n");
9960 return -ENOMEM;
9961 }
da0436e9 9962
2fcee4bf
JS
9963 /* Setup PCI function reset mailbox-ioctl command */
9964 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
9965 LPFC_MBOX_OPCODE_FUNCTION_RESET, 0,
9966 LPFC_SLI4_MBX_EMBED);
9967 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
9968 shdr = (union lpfc_sli4_cfg_shdr *)
9969 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
9970 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
9971 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status,
9972 &shdr->response);
9973 if (rc != MBX_TIMEOUT)
9974 mempool_free(mboxq, phba->mbox_mem_pool);
9975 if (shdr_status || shdr_add_status || rc) {
9976 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9977 "0495 SLI_FUNCTION_RESET mailbox "
9978 "failed with status x%x add_status x%x,"
9979 " mbx status x%x\n",
9980 shdr_status, shdr_add_status, rc);
9981 rc = -ENXIO;
9982 }
9983 break;
9984 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 9985 case LPFC_SLI_INTF_IF_TYPE_6:
2f6fa2c9
JS
9986wait:
9987 /*
9988 * Poll the Port Status Register and wait for RDY for
9989 * up to 30 seconds. If the port doesn't respond, treat
9990 * it as an error.
9991 */
77d093fb 9992 for (rdy_chk = 0; rdy_chk < 1500; rdy_chk++) {
2f6fa2c9
JS
9993 if (lpfc_readl(phba->sli4_hba.u.if_type2.
9994 STATUSregaddr, &reg_data.word0)) {
9995 rc = -ENODEV;
9996 goto out;
9997 }
9998 if (bf_get(lpfc_sliport_status_rdy, &reg_data))
9999 break;
10000 msleep(20);
10001 }
10002
10003 if (!bf_get(lpfc_sliport_status_rdy, &reg_data)) {
10004 phba->work_status[0] = readl(
10005 phba->sli4_hba.u.if_type2.ERR1regaddr);
10006 phba->work_status[1] = readl(
10007 phba->sli4_hba.u.if_type2.ERR2regaddr);
10008 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10009 "2890 Port not ready, port status reg "
10010 "0x%x error 1=0x%x, error 2=0x%x\n",
10011 reg_data.word0,
10012 phba->work_status[0],
10013 phba->work_status[1]);
10014 rc = -ENODEV;
10015 goto out;
10016 }
10017
10018 if (!port_reset) {
10019 /*
10020 * Reset the port now
10021 */
2fcee4bf
JS
10022 reg_data.word0 = 0;
10023 bf_set(lpfc_sliport_ctrl_end, &reg_data,
10024 LPFC_SLIPORT_LITTLE_ENDIAN);
10025 bf_set(lpfc_sliport_ctrl_ip, &reg_data,
10026 LPFC_SLIPORT_INIT_PORT);
10027 writel(reg_data.word0, phba->sli4_hba.u.if_type2.
10028 CTRLregaddr);
8fcb8acd 10029 /* flush */
2b81f942
JS
10030 pci_read_config_word(phba->pcidev,
10031 PCI_DEVICE_ID, &devid);
2fcee4bf 10032
2f6fa2c9
JS
10033 port_reset = 1;
10034 msleep(20);
10035 goto wait;
10036 } else if (bf_get(lpfc_sliport_status_rn, &reg_data)) {
10037 rc = -ENODEV;
10038 goto out;
2fcee4bf
JS
10039 }
10040 break;
2f6fa2c9 10041
2fcee4bf
JS
10042 case LPFC_SLI_INTF_IF_TYPE_1:
10043 default:
10044 break;
da0436e9 10045 }
2fcee4bf 10046
73d91e50 10047out:
2fcee4bf 10048 /* Catch the not-ready port failure after a port reset. */
2f6fa2c9 10049 if (rc) {
229adb0e
JS
10050 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10051 "3317 HBA not functional: IP Reset Failed "
2f6fa2c9 10052 "try: echo fw_reset > board_mode\n");
2fcee4bf 10053 rc = -ENODEV;
229adb0e 10054 }
2fcee4bf 10055
da0436e9
JS
10056 return rc;
10057}
10058
da0436e9
JS
10059/**
10060 * lpfc_sli4_pci_mem_setup - Setup SLI4 HBA PCI memory space.
10061 * @phba: pointer to lpfc hba data structure.
10062 *
10063 * This routine is invoked to set up the PCI device memory space for device
10064 * with SLI-4 interface spec.
10065 *
10066 * Return codes
af901ca1 10067 * 0 - successful
da0436e9
JS
10068 * other values - error
10069 **/
10070static int
10071lpfc_sli4_pci_mem_setup(struct lpfc_hba *phba)
10072{
f30e1bfd 10073 struct pci_dev *pdev = phba->pcidev;
da0436e9 10074 unsigned long bar0map_len, bar1map_len, bar2map_len;
3a487ff7 10075 int error;
2fcee4bf 10076 uint32_t if_type;
da0436e9 10077
f30e1bfd 10078 if (!pdev)
56de8357 10079 return -ENODEV;
da0436e9
JS
10080
10081 /* Set the device DMA mask size */
56de8357
HR
10082 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
10083 if (error)
10084 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10085 if (error)
f30e1bfd 10086 return error;
da0436e9 10087
2fcee4bf
JS
10088 /*
10089 * The BARs and register set definitions and offset locations are
10090 * dependent on the if_type.
10091 */
10092 if (pci_read_config_dword(pdev, LPFC_SLI_INTF,
10093 &phba->sli4_hba.sli_intf.word0)) {
3a487ff7 10094 return -ENODEV;
2fcee4bf
JS
10095 }
10096
10097 /* There is no SLI3 failback for SLI4 devices. */
10098 if (bf_get(lpfc_sli_intf_valid, &phba->sli4_hba.sli_intf) !=
10099 LPFC_SLI_INTF_VALID) {
10100 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10101 "2894 SLI_INTF reg contents invalid "
10102 "sli_intf reg 0x%x\n",
10103 phba->sli4_hba.sli_intf.word0);
3a487ff7 10104 return -ENODEV;
2fcee4bf
JS
10105 }
10106
10107 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
10108 /*
10109 * Get the bus address of SLI4 device Bar regions and the
10110 * number of bytes required by each mapping. The mapping of the
10111 * particular PCI BARs regions is dependent on the type of
10112 * SLI4 device.
da0436e9 10113 */
f5ca6f2e
JS
10114 if (pci_resource_start(pdev, PCI_64BIT_BAR0)) {
10115 phba->pci_bar0_map = pci_resource_start(pdev, PCI_64BIT_BAR0);
10116 bar0map_len = pci_resource_len(pdev, PCI_64BIT_BAR0);
2fcee4bf
JS
10117
10118 /*
10119 * Map SLI4 PCI Config Space Register base to a kernel virtual
10120 * addr
10121 */
10122 phba->sli4_hba.conf_regs_memmap_p =
10123 ioremap(phba->pci_bar0_map, bar0map_len);
10124 if (!phba->sli4_hba.conf_regs_memmap_p) {
10125 dev_printk(KERN_ERR, &pdev->dev,
10126 "ioremap failed for SLI4 PCI config "
10127 "registers.\n");
3a487ff7 10128 return -ENODEV;
2fcee4bf 10129 }
f5ca6f2e 10130 phba->pci_bar0_memmap_p = phba->sli4_hba.conf_regs_memmap_p;
2fcee4bf
JS
10131 /* Set up BAR0 PCI config space register memory map */
10132 lpfc_sli4_bar0_register_memmap(phba, if_type);
1dfb5a47
JS
10133 } else {
10134 phba->pci_bar0_map = pci_resource_start(pdev, 1);
10135 bar0map_len = pci_resource_len(pdev, 1);
27d6ac0a 10136 if (if_type >= LPFC_SLI_INTF_IF_TYPE_2) {
2fcee4bf
JS
10137 dev_printk(KERN_ERR, &pdev->dev,
10138 "FATAL - No BAR0 mapping for SLI4, if_type 2\n");
3a487ff7 10139 return -ENODEV;
2fcee4bf
JS
10140 }
10141 phba->sli4_hba.conf_regs_memmap_p =
da0436e9 10142 ioremap(phba->pci_bar0_map, bar0map_len);
2fcee4bf
JS
10143 if (!phba->sli4_hba.conf_regs_memmap_p) {
10144 dev_printk(KERN_ERR, &pdev->dev,
10145 "ioremap failed for SLI4 PCI config "
10146 "registers.\n");
3a487ff7 10147 return -ENODEV;
2fcee4bf
JS
10148 }
10149 lpfc_sli4_bar0_register_memmap(phba, if_type);
da0436e9
JS
10150 }
10151
e4b9794e
JS
10152 if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
10153 if (pci_resource_start(pdev, PCI_64BIT_BAR2)) {
10154 /*
10155 * Map SLI4 if type 0 HBA Control Register base to a
10156 * kernel virtual address and setup the registers.
10157 */
10158 phba->pci_bar1_map = pci_resource_start(pdev,
10159 PCI_64BIT_BAR2);
10160 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
10161 phba->sli4_hba.ctrl_regs_memmap_p =
10162 ioremap(phba->pci_bar1_map,
10163 bar1map_len);
10164 if (!phba->sli4_hba.ctrl_regs_memmap_p) {
10165 dev_err(&pdev->dev,
10166 "ioremap failed for SLI4 HBA "
10167 "control registers.\n");
10168 error = -ENOMEM;
10169 goto out_iounmap_conf;
10170 }
10171 phba->pci_bar2_memmap_p =
10172 phba->sli4_hba.ctrl_regs_memmap_p;
27d6ac0a 10173 lpfc_sli4_bar1_register_memmap(phba, if_type);
e4b9794e
JS
10174 } else {
10175 error = -ENOMEM;
2fcee4bf
JS
10176 goto out_iounmap_conf;
10177 }
da0436e9
JS
10178 }
10179
27d6ac0a
JS
10180 if ((if_type == LPFC_SLI_INTF_IF_TYPE_6) &&
10181 (pci_resource_start(pdev, PCI_64BIT_BAR2))) {
10182 /*
10183 * Map SLI4 if type 6 HBA Doorbell Register base to a kernel
10184 * virtual address and setup the registers.
10185 */
10186 phba->pci_bar1_map = pci_resource_start(pdev, PCI_64BIT_BAR2);
10187 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
10188 phba->sli4_hba.drbl_regs_memmap_p =
10189 ioremap(phba->pci_bar1_map, bar1map_len);
10190 if (!phba->sli4_hba.drbl_regs_memmap_p) {
10191 dev_err(&pdev->dev,
10192 "ioremap failed for SLI4 HBA doorbell registers.\n");
3a487ff7 10193 error = -ENOMEM;
27d6ac0a
JS
10194 goto out_iounmap_conf;
10195 }
10196 phba->pci_bar2_memmap_p = phba->sli4_hba.drbl_regs_memmap_p;
10197 lpfc_sli4_bar1_register_memmap(phba, if_type);
10198 }
10199
e4b9794e
JS
10200 if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
10201 if (pci_resource_start(pdev, PCI_64BIT_BAR4)) {
10202 /*
10203 * Map SLI4 if type 0 HBA Doorbell Register base to
10204 * a kernel virtual address and setup the registers.
10205 */
10206 phba->pci_bar2_map = pci_resource_start(pdev,
10207 PCI_64BIT_BAR4);
10208 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
10209 phba->sli4_hba.drbl_regs_memmap_p =
10210 ioremap(phba->pci_bar2_map,
10211 bar2map_len);
10212 if (!phba->sli4_hba.drbl_regs_memmap_p) {
10213 dev_err(&pdev->dev,
10214 "ioremap failed for SLI4 HBA"
10215 " doorbell registers.\n");
10216 error = -ENOMEM;
10217 goto out_iounmap_ctrl;
10218 }
10219 phba->pci_bar4_memmap_p =
10220 phba->sli4_hba.drbl_regs_memmap_p;
10221 error = lpfc_sli4_bar2_register_memmap(phba, LPFC_VF0);
10222 if (error)
10223 goto out_iounmap_all;
10224 } else {
10225 error = -ENOMEM;
2fcee4bf 10226 goto out_iounmap_all;
e4b9794e 10227 }
da0436e9
JS
10228 }
10229
1351e69f
JS
10230 if (if_type == LPFC_SLI_INTF_IF_TYPE_6 &&
10231 pci_resource_start(pdev, PCI_64BIT_BAR4)) {
10232 /*
10233 * Map SLI4 if type 6 HBA DPP Register base to a kernel
10234 * virtual address and setup the registers.
10235 */
10236 phba->pci_bar2_map = pci_resource_start(pdev, PCI_64BIT_BAR4);
10237 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
10238 phba->sli4_hba.dpp_regs_memmap_p =
10239 ioremap(phba->pci_bar2_map, bar2map_len);
10240 if (!phba->sli4_hba.dpp_regs_memmap_p) {
10241 dev_err(&pdev->dev,
10242 "ioremap failed for SLI4 HBA dpp registers.\n");
3a487ff7 10243 error = -ENOMEM;
1351e69f
JS
10244 goto out_iounmap_ctrl;
10245 }
10246 phba->pci_bar4_memmap_p = phba->sli4_hba.dpp_regs_memmap_p;
10247 }
10248
b71413dd 10249 /* Set up the EQ/CQ register handeling functions now */
27d6ac0a
JS
10250 switch (if_type) {
10251 case LPFC_SLI_INTF_IF_TYPE_0:
10252 case LPFC_SLI_INTF_IF_TYPE_2:
b71413dd 10253 phba->sli4_hba.sli4_eq_clr_intr = lpfc_sli4_eq_clr_intr;
32517fc0
JS
10254 phba->sli4_hba.sli4_write_eq_db = lpfc_sli4_write_eq_db;
10255 phba->sli4_hba.sli4_write_cq_db = lpfc_sli4_write_cq_db;
27d6ac0a
JS
10256 break;
10257 case LPFC_SLI_INTF_IF_TYPE_6:
10258 phba->sli4_hba.sli4_eq_clr_intr = lpfc_sli4_if6_eq_clr_intr;
32517fc0
JS
10259 phba->sli4_hba.sli4_write_eq_db = lpfc_sli4_if6_write_eq_db;
10260 phba->sli4_hba.sli4_write_cq_db = lpfc_sli4_if6_write_cq_db;
27d6ac0a
JS
10261 break;
10262 default:
10263 break;
b71413dd
JS
10264 }
10265
da0436e9
JS
10266 return 0;
10267
10268out_iounmap_all:
10269 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10270out_iounmap_ctrl:
10271 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
10272out_iounmap_conf:
10273 iounmap(phba->sli4_hba.conf_regs_memmap_p);
3a487ff7 10274
da0436e9
JS
10275 return error;
10276}
10277
10278/**
10279 * lpfc_sli4_pci_mem_unset - Unset SLI4 HBA PCI memory space.
10280 * @phba: pointer to lpfc hba data structure.
10281 *
10282 * This routine is invoked to unset the PCI device memory space for device
10283 * with SLI-4 interface spec.
10284 **/
10285static void
10286lpfc_sli4_pci_mem_unset(struct lpfc_hba *phba)
10287{
2e90f4b5
JS
10288 uint32_t if_type;
10289 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
da0436e9 10290
2e90f4b5
JS
10291 switch (if_type) {
10292 case LPFC_SLI_INTF_IF_TYPE_0:
10293 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10294 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
10295 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10296 break;
10297 case LPFC_SLI_INTF_IF_TYPE_2:
10298 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10299 break;
27d6ac0a
JS
10300 case LPFC_SLI_INTF_IF_TYPE_6:
10301 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10302 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10303 break;
2e90f4b5
JS
10304 case LPFC_SLI_INTF_IF_TYPE_1:
10305 default:
10306 dev_printk(KERN_ERR, &phba->pcidev->dev,
10307 "FATAL - unsupported SLI4 interface type - %d\n",
10308 if_type);
10309 break;
10310 }
da0436e9
JS
10311}
10312
10313/**
10314 * lpfc_sli_enable_msix - Enable MSI-X interrupt mode on SLI-3 device
10315 * @phba: pointer to lpfc hba data structure.
10316 *
10317 * This routine is invoked to enable the MSI-X interrupt vectors to device
45ffac19 10318 * with SLI-3 interface specs.
da0436e9
JS
10319 *
10320 * Return codes
af901ca1 10321 * 0 - successful
da0436e9
JS
10322 * other values - error
10323 **/
10324static int
10325lpfc_sli_enable_msix(struct lpfc_hba *phba)
10326{
45ffac19 10327 int rc;
da0436e9
JS
10328 LPFC_MBOXQ_t *pmb;
10329
10330 /* Set up MSI-X multi-message vectors */
45ffac19
CH
10331 rc = pci_alloc_irq_vectors(phba->pcidev,
10332 LPFC_MSIX_VECTORS, LPFC_MSIX_VECTORS, PCI_IRQ_MSIX);
10333 if (rc < 0) {
da0436e9
JS
10334 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10335 "0420 PCI enable MSI-X failed (%d)\n", rc);
029165ac 10336 goto vec_fail_out;
da0436e9 10337 }
45ffac19 10338
da0436e9
JS
10339 /*
10340 * Assign MSI-X vectors to interrupt handlers
10341 */
10342
10343 /* vector-0 is associated to slow-path handler */
45ffac19 10344 rc = request_irq(pci_irq_vector(phba->pcidev, 0),
ed243d37 10345 &lpfc_sli_sp_intr_handler, 0,
da0436e9
JS
10346 LPFC_SP_DRIVER_HANDLER_NAME, phba);
10347 if (rc) {
10348 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10349 "0421 MSI-X slow-path request_irq failed "
10350 "(%d)\n", rc);
10351 goto msi_fail_out;
10352 }
10353
10354 /* vector-1 is associated to fast-path handler */
45ffac19 10355 rc = request_irq(pci_irq_vector(phba->pcidev, 1),
ed243d37 10356 &lpfc_sli_fp_intr_handler, 0,
da0436e9
JS
10357 LPFC_FP_DRIVER_HANDLER_NAME, phba);
10358
10359 if (rc) {
10360 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10361 "0429 MSI-X fast-path request_irq failed "
10362 "(%d)\n", rc);
10363 goto irq_fail_out;
10364 }
10365
10366 /*
10367 * Configure HBA MSI-X attention conditions to messages
10368 */
10369 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
10370
10371 if (!pmb) {
10372 rc = -ENOMEM;
10373 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10374 "0474 Unable to allocate memory for issuing "
10375 "MBOX_CONFIG_MSI command\n");
10376 goto mem_fail_out;
10377 }
10378 rc = lpfc_config_msi(phba, pmb);
10379 if (rc)
10380 goto mbx_fail_out;
10381 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
10382 if (rc != MBX_SUCCESS) {
10383 lpfc_printf_log(phba, KERN_WARNING, LOG_MBOX,
10384 "0351 Config MSI mailbox command failed, "
10385 "mbxCmd x%x, mbxStatus x%x\n",
10386 pmb->u.mb.mbxCommand, pmb->u.mb.mbxStatus);
10387 goto mbx_fail_out;
10388 }
10389
10390 /* Free memory allocated for mailbox command */
10391 mempool_free(pmb, phba->mbox_mem_pool);
10392 return rc;
10393
10394mbx_fail_out:
10395 /* Free memory allocated for mailbox command */
10396 mempool_free(pmb, phba->mbox_mem_pool);
10397
10398mem_fail_out:
10399 /* free the irq already requested */
45ffac19 10400 free_irq(pci_irq_vector(phba->pcidev, 1), phba);
da0436e9
JS
10401
10402irq_fail_out:
10403 /* free the irq already requested */
45ffac19 10404 free_irq(pci_irq_vector(phba->pcidev, 0), phba);
da0436e9
JS
10405
10406msi_fail_out:
10407 /* Unconfigure MSI-X capability structure */
45ffac19 10408 pci_free_irq_vectors(phba->pcidev);
029165ac
AG
10409
10410vec_fail_out:
da0436e9
JS
10411 return rc;
10412}
10413
da0436e9
JS
10414/**
10415 * lpfc_sli_enable_msi - Enable MSI interrupt mode on SLI-3 device.
10416 * @phba: pointer to lpfc hba data structure.
10417 *
10418 * This routine is invoked to enable the MSI interrupt mode to device with
10419 * SLI-3 interface spec. The kernel function pci_enable_msi() is called to
10420 * enable the MSI vector. The device driver is responsible for calling the
10421 * request_irq() to register MSI vector with a interrupt the handler, which
10422 * is done in this function.
10423 *
10424 * Return codes
af901ca1 10425 * 0 - successful
da0436e9
JS
10426 * other values - error
10427 */
10428static int
10429lpfc_sli_enable_msi(struct lpfc_hba *phba)
10430{
10431 int rc;
10432
10433 rc = pci_enable_msi(phba->pcidev);
10434 if (!rc)
10435 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10436 "0462 PCI enable MSI mode success.\n");
10437 else {
10438 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10439 "0471 PCI enable MSI mode failed (%d)\n", rc);
10440 return rc;
10441 }
10442
10443 rc = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
ed243d37 10444 0, LPFC_DRIVER_NAME, phba);
da0436e9
JS
10445 if (rc) {
10446 pci_disable_msi(phba->pcidev);
10447 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10448 "0478 MSI request_irq failed (%d)\n", rc);
10449 }
10450 return rc;
10451}
10452
da0436e9
JS
10453/**
10454 * lpfc_sli_enable_intr - Enable device interrupt to SLI-3 device.
10455 * @phba: pointer to lpfc hba data structure.
10456 *
10457 * This routine is invoked to enable device interrupt and associate driver's
10458 * interrupt handler(s) to interrupt vector(s) to device with SLI-3 interface
10459 * spec. Depends on the interrupt mode configured to the driver, the driver
10460 * will try to fallback from the configured interrupt mode to an interrupt
10461 * mode which is supported by the platform, kernel, and device in the order
10462 * of:
10463 * MSI-X -> MSI -> IRQ.
10464 *
10465 * Return codes
af901ca1 10466 * 0 - successful
da0436e9
JS
10467 * other values - error
10468 **/
10469static uint32_t
10470lpfc_sli_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
10471{
10472 uint32_t intr_mode = LPFC_INTR_ERROR;
10473 int retval;
10474
10475 if (cfg_mode == 2) {
10476 /* Need to issue conf_port mbox cmd before conf_msi mbox cmd */
10477 retval = lpfc_sli_config_port(phba, LPFC_SLI_REV3);
10478 if (!retval) {
10479 /* Now, try to enable MSI-X interrupt mode */
10480 retval = lpfc_sli_enable_msix(phba);
10481 if (!retval) {
10482 /* Indicate initialization to MSI-X mode */
10483 phba->intr_type = MSIX;
10484 intr_mode = 2;
10485 }
10486 }
10487 }
10488
10489 /* Fallback to MSI if MSI-X initialization failed */
10490 if (cfg_mode >= 1 && phba->intr_type == NONE) {
10491 retval = lpfc_sli_enable_msi(phba);
10492 if (!retval) {
10493 /* Indicate initialization to MSI mode */
10494 phba->intr_type = MSI;
10495 intr_mode = 1;
10496 }
10497 }
10498
10499 /* Fallback to INTx if both MSI-X/MSI initalization failed */
10500 if (phba->intr_type == NONE) {
10501 retval = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
10502 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
10503 if (!retval) {
10504 /* Indicate initialization to INTx mode */
10505 phba->intr_type = INTx;
10506 intr_mode = 0;
10507 }
10508 }
10509 return intr_mode;
10510}
10511
10512/**
10513 * lpfc_sli_disable_intr - Disable device interrupt to SLI-3 device.
10514 * @phba: pointer to lpfc hba data structure.
10515 *
10516 * This routine is invoked to disable device interrupt and disassociate the
10517 * driver's interrupt handler(s) from interrupt vector(s) to device with
10518 * SLI-3 interface spec. Depending on the interrupt mode, the driver will
10519 * release the interrupt vector(s) for the message signaled interrupt.
10520 **/
10521static void
10522lpfc_sli_disable_intr(struct lpfc_hba *phba)
10523{
45ffac19
CH
10524 int nr_irqs, i;
10525
da0436e9 10526 if (phba->intr_type == MSIX)
45ffac19
CH
10527 nr_irqs = LPFC_MSIX_VECTORS;
10528 else
10529 nr_irqs = 1;
10530
10531 for (i = 0; i < nr_irqs; i++)
10532 free_irq(pci_irq_vector(phba->pcidev, i), phba);
10533 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
10534
10535 /* Reset interrupt management states */
10536 phba->intr_type = NONE;
10537 phba->sli.slistat.sli_intr = 0;
da0436e9
JS
10538}
10539
6a828b0f
JS
10540/**
10541 * lpfc_find_cpu_handle - Find the CPU that corresponds to the specified EQ
10542 * @phba: pointer to lpfc hba data structure.
10543 * @id: EQ vector index or Hardware Queue index
10544 * @match: LPFC_FIND_BY_EQ = match by EQ
10545 * LPFC_FIND_BY_HDWQ = match by Hardware Queue
10546 */
10547static uint16_t
10548lpfc_find_cpu_handle(struct lpfc_hba *phba, uint16_t id, int match)
10549{
10550 struct lpfc_vector_map_info *cpup;
10551 int cpu;
10552
10553 /* Find the desired phys_id for the specified EQ */
222e9239
JS
10554 for_each_present_cpu(cpu) {
10555 cpup = &phba->sli4_hba.cpu_map[cpu];
6a828b0f
JS
10556 if ((match == LPFC_FIND_BY_EQ) &&
10557 (cpup->irq != LPFC_VECTOR_MAP_EMPTY) &&
10558 (cpup->eq == id))
10559 return cpu;
10560 if ((match == LPFC_FIND_BY_HDWQ) && (cpup->hdwq == id))
10561 return cpu;
6a828b0f
JS
10562 }
10563 return 0;
10564}
10565
10566/**
10567 * lpfc_find_eq_handle - Find the EQ that corresponds to the specified
10568 * Hardware Queue
10569 * @phba: pointer to lpfc hba data structure.
10570 * @hdwq: Hardware Queue index
10571 */
10572static uint16_t
10573lpfc_find_eq_handle(struct lpfc_hba *phba, uint16_t hdwq)
10574{
10575 struct lpfc_vector_map_info *cpup;
10576 int cpu;
10577
10578 /* Find the desired phys_id for the specified EQ */
222e9239
JS
10579 for_each_present_cpu(cpu) {
10580 cpup = &phba->sli4_hba.cpu_map[cpu];
6a828b0f
JS
10581 if (cpup->hdwq == hdwq)
10582 return cpup->eq;
6a828b0f
JS
10583 }
10584 return 0;
10585}
10586
6a828b0f
JS
10587#ifdef CONFIG_X86
10588/**
10589 * lpfc_find_hyper - Determine if the CPU map entry is hyper-threaded
10590 * @phba: pointer to lpfc hba data structure.
10591 * @cpu: CPU map index
10592 * @phys_id: CPU package physical id
10593 * @core_id: CPU core id
10594 */
10595static int
10596lpfc_find_hyper(struct lpfc_hba *phba, int cpu,
10597 uint16_t phys_id, uint16_t core_id)
10598{
10599 struct lpfc_vector_map_info *cpup;
10600 int idx;
10601
222e9239
JS
10602 for_each_present_cpu(idx) {
10603 cpup = &phba->sli4_hba.cpu_map[idx];
6a828b0f
JS
10604 /* Does the cpup match the one we are looking for */
10605 if ((cpup->phys_id == phys_id) &&
10606 (cpup->core_id == core_id) &&
222e9239 10607 (cpu != idx))
6a828b0f 10608 return 1;
6a828b0f
JS
10609 }
10610 return 0;
10611}
10612#endif
10613
7bb03bbf 10614/**
895427bd 10615 * lpfc_cpu_affinity_check - Check vector CPU affinity mappings
7bb03bbf 10616 * @phba: pointer to lpfc hba data structure.
895427bd
JS
10617 * @vectors: number of msix vectors allocated.
10618 *
10619 * The routine will figure out the CPU affinity assignment for every
6a828b0f 10620 * MSI-X vector allocated for the HBA.
895427bd
JS
10621 * In addition, the CPU to IO channel mapping will be calculated
10622 * and the phba->sli4_hba.cpu_map array will reflect this.
7bb03bbf 10623 */
895427bd
JS
10624static void
10625lpfc_cpu_affinity_check(struct lpfc_hba *phba, int vectors)
7bb03bbf 10626{
59e54d9a 10627 int i, cpu, idx;
6a828b0f
JS
10628 int max_phys_id, min_phys_id;
10629 int max_core_id, min_core_id;
7bb03bbf 10630 struct lpfc_vector_map_info *cpup;
75508a8b 10631 const struct cpumask *maskp;
7bb03bbf
JS
10632#ifdef CONFIG_X86
10633 struct cpuinfo_x86 *cpuinfo;
10634#endif
7bb03bbf
JS
10635
10636 /* Init cpu_map array */
10637 memset(phba->sli4_hba.cpu_map, 0xff,
10638 (sizeof(struct lpfc_vector_map_info) *
222e9239 10639 phba->sli4_hba.num_possible_cpu));
7bb03bbf 10640
6a828b0f
JS
10641 max_phys_id = 0;
10642 min_phys_id = 0xffff;
10643 max_core_id = 0;
10644 min_core_id = 0xffff;
7bb03bbf
JS
10645
10646 /* Update CPU map with physical id and core id of each CPU */
222e9239
JS
10647 for_each_present_cpu(cpu) {
10648 cpup = &phba->sli4_hba.cpu_map[cpu];
7bb03bbf
JS
10649#ifdef CONFIG_X86
10650 cpuinfo = &cpu_data(cpu);
10651 cpup->phys_id = cpuinfo->phys_proc_id;
10652 cpup->core_id = cpuinfo->cpu_core_id;
6a828b0f
JS
10653 cpup->hyper = lpfc_find_hyper(phba, cpu,
10654 cpup->phys_id, cpup->core_id);
7bb03bbf
JS
10655#else
10656 /* No distinction between CPUs for other platforms */
10657 cpup->phys_id = 0;
6a828b0f
JS
10658 cpup->core_id = cpu;
10659 cpup->hyper = 0;
7bb03bbf 10660#endif
6a828b0f 10661
b3295c2a
JS
10662 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10663 "3328 CPU physid %d coreid %d\n",
10664 cpup->phys_id, cpup->core_id);
6a828b0f
JS
10665
10666 if (cpup->phys_id > max_phys_id)
10667 max_phys_id = cpup->phys_id;
10668 if (cpup->phys_id < min_phys_id)
10669 min_phys_id = cpup->phys_id;
10670
10671 if (cpup->core_id > max_core_id)
10672 max_core_id = cpup->core_id;
10673 if (cpup->core_id < min_core_id)
10674 min_core_id = cpup->core_id;
7bb03bbf 10675 }
7bb03bbf 10676
32517fc0
JS
10677 for_each_possible_cpu(i) {
10678 struct lpfc_eq_intr_info *eqi =
10679 per_cpu_ptr(phba->sli4_hba.eq_info, i);
10680
10681 INIT_LIST_HEAD(&eqi->list);
10682 eqi->icnt = 0;
10683 }
10684
75508a8b
JS
10685 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
10686 maskp = pci_irq_get_affinity(phba->pcidev, idx);
10687 if (!maskp)
10688 continue;
10689
10690 for_each_cpu_and(cpu, maskp, cpu_present_mask) {
10691 cpup = &phba->sli4_hba.cpu_map[cpu];
6a828b0f
JS
10692 cpup->eq = idx;
10693 cpup->hdwq = idx;
10694 cpup->irq = pci_irq_vector(phba->pcidev, idx);
10695
75508a8b 10696 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6a828b0f 10697 "3336 Set Affinity: CPU %d "
75508a8b
JS
10698 "hdwq %d irq %d\n",
10699 cpu, cpup->hdwq, cpup->irq);
6a828b0f 10700 }
b3295c2a
JS
10701 }
10702 return;
7bb03bbf 10703}
7bb03bbf 10704
da0436e9
JS
10705/**
10706 * lpfc_sli4_enable_msix - Enable MSI-X interrupt mode to SLI-4 device
10707 * @phba: pointer to lpfc hba data structure.
10708 *
10709 * This routine is invoked to enable the MSI-X interrupt vectors to device
45ffac19 10710 * with SLI-4 interface spec.
da0436e9
JS
10711 *
10712 * Return codes
af901ca1 10713 * 0 - successful
da0436e9
JS
10714 * other values - error
10715 **/
10716static int
10717lpfc_sli4_enable_msix(struct lpfc_hba *phba)
10718{
75baf696 10719 int vectors, rc, index;
b83d005e 10720 char *name;
da0436e9
JS
10721
10722 /* Set up MSI-X multi-message vectors */
6a828b0f 10723 vectors = phba->cfg_irq_chann;
45ffac19 10724
f358dd0c 10725 rc = pci_alloc_irq_vectors(phba->pcidev,
75508a8b 10726 1,
f358dd0c 10727 vectors, PCI_IRQ_MSIX | PCI_IRQ_AFFINITY);
4f871e1b 10728 if (rc < 0) {
da0436e9
JS
10729 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10730 "0484 PCI enable MSI-X failed (%d)\n", rc);
029165ac 10731 goto vec_fail_out;
da0436e9 10732 }
4f871e1b 10733 vectors = rc;
75baf696 10734
7bb03bbf 10735 /* Assign MSI-X vectors to interrupt handlers */
67d12733 10736 for (index = 0; index < vectors; index++) {
b83d005e
JS
10737 name = phba->sli4_hba.hba_eq_hdl[index].handler_name;
10738 memset(name, 0, LPFC_SLI4_HANDLER_NAME_SZ);
10739 snprintf(name, LPFC_SLI4_HANDLER_NAME_SZ,
4305f183 10740 LPFC_DRIVER_HANDLER_NAME"%d", index);
da0436e9 10741
895427bd
JS
10742 phba->sli4_hba.hba_eq_hdl[index].idx = index;
10743 phba->sli4_hba.hba_eq_hdl[index].phba = phba;
7370d10a
JS
10744 rc = request_irq(pci_irq_vector(phba->pcidev, index),
10745 &lpfc_sli4_hba_intr_handler, 0,
10746 name,
10747 &phba->sli4_hba.hba_eq_hdl[index]);
da0436e9
JS
10748 if (rc) {
10749 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10750 "0486 MSI-X fast-path (%d) "
10751 "request_irq failed (%d)\n", index, rc);
10752 goto cfg_fail_out;
10753 }
10754 }
10755
6a828b0f 10756 if (vectors != phba->cfg_irq_chann) {
82c3e9ba
JS
10757 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10758 "3238 Reducing IO channels to match number of "
10759 "MSI-X vectors, requested %d got %d\n",
6a828b0f
JS
10760 phba->cfg_irq_chann, vectors);
10761 if (phba->cfg_irq_chann > vectors)
10762 phba->cfg_irq_chann = vectors;
982ab128 10763 if (phba->nvmet_support && (phba->cfg_nvmet_mrq > vectors))
cdb42bec 10764 phba->cfg_nvmet_mrq = vectors;
82c3e9ba 10765 }
7bb03bbf 10766
da0436e9
JS
10767 return rc;
10768
10769cfg_fail_out:
10770 /* free the irq already requested */
895427bd
JS
10771 for (--index; index >= 0; index--)
10772 free_irq(pci_irq_vector(phba->pcidev, index),
10773 &phba->sli4_hba.hba_eq_hdl[index]);
da0436e9 10774
da0436e9 10775 /* Unconfigure MSI-X capability structure */
45ffac19 10776 pci_free_irq_vectors(phba->pcidev);
029165ac
AG
10777
10778vec_fail_out:
da0436e9
JS
10779 return rc;
10780}
10781
da0436e9
JS
10782/**
10783 * lpfc_sli4_enable_msi - Enable MSI interrupt mode to SLI-4 device
10784 * @phba: pointer to lpfc hba data structure.
10785 *
10786 * This routine is invoked to enable the MSI interrupt mode to device with
10787 * SLI-4 interface spec. The kernel function pci_enable_msi() is called
10788 * to enable the MSI vector. The device driver is responsible for calling
10789 * the request_irq() to register MSI vector with a interrupt the handler,
10790 * which is done in this function.
10791 *
10792 * Return codes
af901ca1 10793 * 0 - successful
da0436e9
JS
10794 * other values - error
10795 **/
10796static int
10797lpfc_sli4_enable_msi(struct lpfc_hba *phba)
10798{
10799 int rc, index;
10800
10801 rc = pci_enable_msi(phba->pcidev);
10802 if (!rc)
10803 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10804 "0487 PCI enable MSI mode success.\n");
10805 else {
10806 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10807 "0488 PCI enable MSI mode failed (%d)\n", rc);
10808 return rc;
10809 }
10810
10811 rc = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
ed243d37 10812 0, LPFC_DRIVER_NAME, phba);
da0436e9
JS
10813 if (rc) {
10814 pci_disable_msi(phba->pcidev);
10815 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10816 "0490 MSI request_irq failed (%d)\n", rc);
75baf696 10817 return rc;
da0436e9
JS
10818 }
10819
6a828b0f 10820 for (index = 0; index < phba->cfg_irq_chann; index++) {
895427bd
JS
10821 phba->sli4_hba.hba_eq_hdl[index].idx = index;
10822 phba->sli4_hba.hba_eq_hdl[index].phba = phba;
da0436e9
JS
10823 }
10824
75baf696 10825 return 0;
da0436e9
JS
10826}
10827
da0436e9
JS
10828/**
10829 * lpfc_sli4_enable_intr - Enable device interrupt to SLI-4 device
10830 * @phba: pointer to lpfc hba data structure.
10831 *
10832 * This routine is invoked to enable device interrupt and associate driver's
10833 * interrupt handler(s) to interrupt vector(s) to device with SLI-4
10834 * interface spec. Depends on the interrupt mode configured to the driver,
10835 * the driver will try to fallback from the configured interrupt mode to an
10836 * interrupt mode which is supported by the platform, kernel, and device in
10837 * the order of:
10838 * MSI-X -> MSI -> IRQ.
10839 *
10840 * Return codes
af901ca1 10841 * 0 - successful
da0436e9
JS
10842 * other values - error
10843 **/
10844static uint32_t
10845lpfc_sli4_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
10846{
10847 uint32_t intr_mode = LPFC_INTR_ERROR;
895427bd 10848 int retval, idx;
da0436e9
JS
10849
10850 if (cfg_mode == 2) {
10851 /* Preparation before conf_msi mbox cmd */
10852 retval = 0;
10853 if (!retval) {
10854 /* Now, try to enable MSI-X interrupt mode */
10855 retval = lpfc_sli4_enable_msix(phba);
10856 if (!retval) {
10857 /* Indicate initialization to MSI-X mode */
10858 phba->intr_type = MSIX;
10859 intr_mode = 2;
10860 }
10861 }
10862 }
10863
10864 /* Fallback to MSI if MSI-X initialization failed */
10865 if (cfg_mode >= 1 && phba->intr_type == NONE) {
10866 retval = lpfc_sli4_enable_msi(phba);
10867 if (!retval) {
10868 /* Indicate initialization to MSI mode */
10869 phba->intr_type = MSI;
10870 intr_mode = 1;
10871 }
10872 }
10873
10874 /* Fallback to INTx if both MSI-X/MSI initalization failed */
10875 if (phba->intr_type == NONE) {
10876 retval = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
10877 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
10878 if (!retval) {
895427bd
JS
10879 struct lpfc_hba_eq_hdl *eqhdl;
10880
da0436e9
JS
10881 /* Indicate initialization to INTx mode */
10882 phba->intr_type = INTx;
10883 intr_mode = 0;
895427bd 10884
6a828b0f 10885 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
895427bd
JS
10886 eqhdl = &phba->sli4_hba.hba_eq_hdl[idx];
10887 eqhdl->idx = idx;
10888 eqhdl->phba = phba;
1ba981fd 10889 }
da0436e9
JS
10890 }
10891 }
10892 return intr_mode;
10893}
10894
10895/**
10896 * lpfc_sli4_disable_intr - Disable device interrupt to SLI-4 device
10897 * @phba: pointer to lpfc hba data structure.
10898 *
10899 * This routine is invoked to disable device interrupt and disassociate
10900 * the driver's interrupt handler(s) from interrupt vector(s) to device
10901 * with SLI-4 interface spec. Depending on the interrupt mode, the driver
10902 * will release the interrupt vector(s) for the message signaled interrupt.
10903 **/
10904static void
10905lpfc_sli4_disable_intr(struct lpfc_hba *phba)
10906{
10907 /* Disable the currently initialized interrupt mode */
45ffac19
CH
10908 if (phba->intr_type == MSIX) {
10909 int index;
10910
10911 /* Free up MSI-X multi-message vectors */
6a828b0f 10912 for (index = 0; index < phba->cfg_irq_chann; index++) {
b3295c2a
JS
10913 irq_set_affinity_hint(
10914 pci_irq_vector(phba->pcidev, index),
10915 NULL);
895427bd
JS
10916 free_irq(pci_irq_vector(phba->pcidev, index),
10917 &phba->sli4_hba.hba_eq_hdl[index]);
b3295c2a 10918 }
45ffac19 10919 } else {
da0436e9 10920 free_irq(phba->pcidev->irq, phba);
45ffac19
CH
10921 }
10922
10923 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
10924
10925 /* Reset interrupt management states */
10926 phba->intr_type = NONE;
10927 phba->sli.slistat.sli_intr = 0;
da0436e9
JS
10928}
10929
10930/**
10931 * lpfc_unset_hba - Unset SLI3 hba device initialization
10932 * @phba: pointer to lpfc hba data structure.
10933 *
10934 * This routine is invoked to unset the HBA device initialization steps to
10935 * a device with SLI-3 interface spec.
10936 **/
10937static void
10938lpfc_unset_hba(struct lpfc_hba *phba)
10939{
10940 struct lpfc_vport *vport = phba->pport;
10941 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
10942
10943 spin_lock_irq(shost->host_lock);
10944 vport->load_flag |= FC_UNLOADING;
10945 spin_unlock_irq(shost->host_lock);
10946
72859909
JS
10947 kfree(phba->vpi_bmask);
10948 kfree(phba->vpi_ids);
10949
da0436e9
JS
10950 lpfc_stop_hba_timers(phba);
10951
10952 phba->pport->work_port_events = 0;
10953
10954 lpfc_sli_hba_down(phba);
10955
10956 lpfc_sli_brdrestart(phba);
10957
10958 lpfc_sli_disable_intr(phba);
10959
10960 return;
10961}
10962
5af5eee7
JS
10963/**
10964 * lpfc_sli4_xri_exchange_busy_wait - Wait for device XRI exchange busy
10965 * @phba: Pointer to HBA context object.
10966 *
10967 * This function is called in the SLI4 code path to wait for completion
10968 * of device's XRIs exchange busy. It will check the XRI exchange busy
10969 * on outstanding FCP and ELS I/Os every 10ms for up to 10 seconds; after
10970 * that, it will check the XRI exchange busy on outstanding FCP and ELS
10971 * I/Os every 30 seconds, log error message, and wait forever. Only when
10972 * all XRI exchange busy complete, the driver unload shall proceed with
10973 * invoking the function reset ioctl mailbox command to the CNA and the
10974 * the rest of the driver unload resource release.
10975 **/
10976static void
10977lpfc_sli4_xri_exchange_busy_wait(struct lpfc_hba *phba)
10978{
5e5b511d
JS
10979 struct lpfc_sli4_hdw_queue *qp;
10980 int idx, ccnt, fcnt;
5af5eee7 10981 int wait_time = 0;
5e5b511d 10982 int io_xri_cmpl = 1;
86c67379 10983 int nvmet_xri_cmpl = 1;
895427bd 10984 int fcp_xri_cmpl = 1;
5af5eee7
JS
10985 int els_xri_cmpl = list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
10986
c3725bdc
JS
10987 /* Driver just aborted IOs during the hba_unset process. Pause
10988 * here to give the HBA time to complete the IO and get entries
10989 * into the abts lists.
10990 */
10991 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1 * 5);
10992
10993 /* Wait for NVME pending IO to flush back to transport. */
10994 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
10995 lpfc_nvme_wait_for_io_drain(phba);
10996
5e5b511d
JS
10997 ccnt = 0;
10998 fcnt = 0;
10999 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
11000 qp = &phba->sli4_hba.hdwq[idx];
11001 fcp_xri_cmpl = list_empty(
11002 &qp->lpfc_abts_scsi_buf_list);
11003 if (!fcp_xri_cmpl) /* if list is NOT empty */
11004 fcnt++;
11005 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
11006 io_xri_cmpl = list_empty(
11007 &qp->lpfc_abts_nvme_buf_list);
11008 if (!io_xri_cmpl) /* if list is NOT empty */
11009 ccnt++;
11010 }
11011 }
11012 if (ccnt)
11013 io_xri_cmpl = 0;
11014 if (fcnt)
11015 fcp_xri_cmpl = 0;
11016
86c67379 11017 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
86c67379
JS
11018 nvmet_xri_cmpl =
11019 list_empty(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
11020 }
895427bd 11021
5e5b511d 11022 while (!fcp_xri_cmpl || !els_xri_cmpl || !io_xri_cmpl ||
f358dd0c 11023 !nvmet_xri_cmpl) {
5af5eee7 11024 if (wait_time > LPFC_XRI_EXCH_BUSY_WAIT_TMO) {
68c9b55d
JS
11025 if (!nvmet_xri_cmpl)
11026 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11027 "6424 NVMET XRI exchange busy "
11028 "wait time: %d seconds.\n",
11029 wait_time/1000);
5e5b511d 11030 if (!io_xri_cmpl)
895427bd
JS
11031 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11032 "6100 NVME XRI exchange busy "
11033 "wait time: %d seconds.\n",
11034 wait_time/1000);
5af5eee7
JS
11035 if (!fcp_xri_cmpl)
11036 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11037 "2877 FCP XRI exchange busy "
11038 "wait time: %d seconds.\n",
11039 wait_time/1000);
11040 if (!els_xri_cmpl)
11041 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11042 "2878 ELS XRI exchange busy "
11043 "wait time: %d seconds.\n",
11044 wait_time/1000);
11045 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T2);
11046 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T2;
11047 } else {
11048 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1);
11049 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T1;
11050 }
5e5b511d
JS
11051
11052 ccnt = 0;
11053 fcnt = 0;
11054 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
11055 qp = &phba->sli4_hba.hdwq[idx];
11056 fcp_xri_cmpl = list_empty(
11057 &qp->lpfc_abts_scsi_buf_list);
11058 if (!fcp_xri_cmpl) /* if list is NOT empty */
11059 fcnt++;
11060 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
11061 io_xri_cmpl = list_empty(
11062 &qp->lpfc_abts_nvme_buf_list);
11063 if (!io_xri_cmpl) /* if list is NOT empty */
11064 ccnt++;
11065 }
11066 }
11067 if (ccnt)
11068 io_xri_cmpl = 0;
11069 if (fcnt)
11070 fcp_xri_cmpl = 0;
11071
86c67379 11072 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
86c67379
JS
11073 nvmet_xri_cmpl = list_empty(
11074 &phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
11075 }
5af5eee7
JS
11076 els_xri_cmpl =
11077 list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
f358dd0c 11078
5af5eee7
JS
11079 }
11080}
11081
da0436e9
JS
11082/**
11083 * lpfc_sli4_hba_unset - Unset the fcoe hba
11084 * @phba: Pointer to HBA context object.
11085 *
11086 * This function is called in the SLI4 code path to reset the HBA's FCoE
11087 * function. The caller is not required to hold any lock. This routine
11088 * issues PCI function reset mailbox command to reset the FCoE function.
11089 * At the end of the function, it calls lpfc_hba_down_post function to
11090 * free any pending commands.
11091 **/
11092static void
11093lpfc_sli4_hba_unset(struct lpfc_hba *phba)
11094{
11095 int wait_cnt = 0;
11096 LPFC_MBOXQ_t *mboxq;
912e3acd 11097 struct pci_dev *pdev = phba->pcidev;
da0436e9
JS
11098
11099 lpfc_stop_hba_timers(phba);
cdb42bec
JS
11100 if (phba->pport)
11101 phba->sli4_hba.intr_enable = 0;
da0436e9
JS
11102
11103 /*
11104 * Gracefully wait out the potential current outstanding asynchronous
11105 * mailbox command.
11106 */
11107
11108 /* First, block any pending async mailbox command from posted */
11109 spin_lock_irq(&phba->hbalock);
11110 phba->sli.sli_flag |= LPFC_SLI_ASYNC_MBX_BLK;
11111 spin_unlock_irq(&phba->hbalock);
11112 /* Now, trying to wait it out if we can */
11113 while (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
11114 msleep(10);
11115 if (++wait_cnt > LPFC_ACTIVE_MBOX_WAIT_CNT)
11116 break;
11117 }
11118 /* Forcefully release the outstanding mailbox command if timed out */
11119 if (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
11120 spin_lock_irq(&phba->hbalock);
11121 mboxq = phba->sli.mbox_active;
11122 mboxq->u.mb.mbxStatus = MBX_NOT_FINISHED;
11123 __lpfc_mbox_cmpl_put(phba, mboxq);
11124 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
11125 phba->sli.mbox_active = NULL;
11126 spin_unlock_irq(&phba->hbalock);
11127 }
11128
5af5eee7
JS
11129 /* Abort all iocbs associated with the hba */
11130 lpfc_sli_hba_iocb_abort(phba);
11131
11132 /* Wait for completion of device XRI exchange busy */
11133 lpfc_sli4_xri_exchange_busy_wait(phba);
11134
da0436e9
JS
11135 /* Disable PCI subsystem interrupt */
11136 lpfc_sli4_disable_intr(phba);
11137
912e3acd
JS
11138 /* Disable SR-IOV if enabled */
11139 if (phba->cfg_sriov_nr_virtfn)
11140 pci_disable_sriov(pdev);
11141
da0436e9
JS
11142 /* Stop kthread signal shall trigger work_done one more time */
11143 kthread_stop(phba->worker_thread);
11144
d2cc9bcd 11145 /* Disable FW logging to host memory */
1165a5c2 11146 lpfc_ras_stop_fwlog(phba);
d2cc9bcd 11147
d1f525aa
JS
11148 /* Unset the queues shared with the hardware then release all
11149 * allocated resources.
11150 */
11151 lpfc_sli4_queue_unset(phba);
11152 lpfc_sli4_queue_destroy(phba);
11153
3677a3a7
JS
11154 /* Reset SLI4 HBA FCoE function */
11155 lpfc_pci_function_reset(phba);
11156
1165a5c2
JS
11157 /* Free RAS DMA memory */
11158 if (phba->ras_fwlog.ras_enabled)
11159 lpfc_sli4_ras_dma_free(phba);
11160
da0436e9 11161 /* Stop the SLI4 device port */
1ffdd2c0
JS
11162 if (phba->pport)
11163 phba->pport->work_port_events = 0;
da0436e9
JS
11164}
11165
28baac74
JS
11166 /**
11167 * lpfc_pc_sli4_params_get - Get the SLI4_PARAMS port capabilities.
11168 * @phba: Pointer to HBA context object.
11169 * @mboxq: Pointer to the mailboxq memory for the mailbox command response.
11170 *
11171 * This function is called in the SLI4 code path to read the port's
11172 * sli4 capabilities.
11173 *
11174 * This function may be be called from any context that can block-wait
11175 * for the completion. The expectation is that this routine is called
11176 * typically from probe_one or from the online routine.
11177 **/
11178int
11179lpfc_pc_sli4_params_get(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
11180{
11181 int rc;
11182 struct lpfc_mqe *mqe;
11183 struct lpfc_pc_sli4_params *sli4_params;
11184 uint32_t mbox_tmo;
11185
11186 rc = 0;
11187 mqe = &mboxq->u.mqe;
11188
11189 /* Read the port's SLI4 Parameters port capabilities */
fedd3b7b 11190 lpfc_pc_sli4_params(mboxq);
28baac74
JS
11191 if (!phba->sli4_hba.intr_enable)
11192 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
11193 else {
a183a15f 11194 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
28baac74
JS
11195 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
11196 }
11197
11198 if (unlikely(rc))
11199 return 1;
11200
11201 sli4_params = &phba->sli4_hba.pc_sli4_params;
11202 sli4_params->if_type = bf_get(if_type, &mqe->un.sli4_params);
11203 sli4_params->sli_rev = bf_get(sli_rev, &mqe->un.sli4_params);
11204 sli4_params->sli_family = bf_get(sli_family, &mqe->un.sli4_params);
11205 sli4_params->featurelevel_1 = bf_get(featurelevel_1,
11206 &mqe->un.sli4_params);
11207 sli4_params->featurelevel_2 = bf_get(featurelevel_2,
11208 &mqe->un.sli4_params);
11209 sli4_params->proto_types = mqe->un.sli4_params.word3;
11210 sli4_params->sge_supp_len = mqe->un.sli4_params.sge_supp_len;
11211 sli4_params->if_page_sz = bf_get(if_page_sz, &mqe->un.sli4_params);
11212 sli4_params->rq_db_window = bf_get(rq_db_window, &mqe->un.sli4_params);
11213 sli4_params->loopbk_scope = bf_get(loopbk_scope, &mqe->un.sli4_params);
11214 sli4_params->eq_pages_max = bf_get(eq_pages, &mqe->un.sli4_params);
11215 sli4_params->eqe_size = bf_get(eqe_size, &mqe->un.sli4_params);
11216 sli4_params->cq_pages_max = bf_get(cq_pages, &mqe->un.sli4_params);
11217 sli4_params->cqe_size = bf_get(cqe_size, &mqe->un.sli4_params);
11218 sli4_params->mq_pages_max = bf_get(mq_pages, &mqe->un.sli4_params);
11219 sli4_params->mqe_size = bf_get(mqe_size, &mqe->un.sli4_params);
11220 sli4_params->mq_elem_cnt = bf_get(mq_elem_cnt, &mqe->un.sli4_params);
11221 sli4_params->wq_pages_max = bf_get(wq_pages, &mqe->un.sli4_params);
11222 sli4_params->wqe_size = bf_get(wqe_size, &mqe->un.sli4_params);
11223 sli4_params->rq_pages_max = bf_get(rq_pages, &mqe->un.sli4_params);
11224 sli4_params->rqe_size = bf_get(rqe_size, &mqe->un.sli4_params);
11225 sli4_params->hdr_pages_max = bf_get(hdr_pages, &mqe->un.sli4_params);
11226 sli4_params->hdr_size = bf_get(hdr_size, &mqe->un.sli4_params);
11227 sli4_params->hdr_pp_align = bf_get(hdr_pp_align, &mqe->un.sli4_params);
11228 sli4_params->sgl_pages_max = bf_get(sgl_pages, &mqe->un.sli4_params);
11229 sli4_params->sgl_pp_align = bf_get(sgl_pp_align, &mqe->un.sli4_params);
0558056c
JS
11230
11231 /* Make sure that sge_supp_len can be handled by the driver */
11232 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
11233 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
11234
28baac74
JS
11235 return rc;
11236}
11237
fedd3b7b
JS
11238/**
11239 * lpfc_get_sli4_parameters - Get the SLI4 Config PARAMETERS.
11240 * @phba: Pointer to HBA context object.
11241 * @mboxq: Pointer to the mailboxq memory for the mailbox command response.
11242 *
11243 * This function is called in the SLI4 code path to read the port's
11244 * sli4 capabilities.
11245 *
11246 * This function may be be called from any context that can block-wait
11247 * for the completion. The expectation is that this routine is called
11248 * typically from probe_one or from the online routine.
11249 **/
11250int
11251lpfc_get_sli4_parameters(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
11252{
11253 int rc;
11254 struct lpfc_mqe *mqe = &mboxq->u.mqe;
11255 struct lpfc_pc_sli4_params *sli4_params;
a183a15f 11256 uint32_t mbox_tmo;
fedd3b7b 11257 int length;
bf316c78 11258 bool exp_wqcq_pages = true;
fedd3b7b
JS
11259 struct lpfc_sli4_parameters *mbx_sli4_parameters;
11260
6d368e53
JS
11261 /*
11262 * By default, the driver assumes the SLI4 port requires RPI
11263 * header postings. The SLI4_PARAM response will correct this
11264 * assumption.
11265 */
11266 phba->sli4_hba.rpi_hdrs_in_use = 1;
11267
fedd3b7b
JS
11268 /* Read the port's SLI4 Config Parameters */
11269 length = (sizeof(struct lpfc_mbx_get_sli4_parameters) -
11270 sizeof(struct lpfc_sli4_cfg_mhdr));
11271 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
11272 LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS,
11273 length, LPFC_SLI4_MBX_EMBED);
11274 if (!phba->sli4_hba.intr_enable)
11275 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
a183a15f
JS
11276 else {
11277 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
11278 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
11279 }
fedd3b7b
JS
11280 if (unlikely(rc))
11281 return rc;
11282 sli4_params = &phba->sli4_hba.pc_sli4_params;
11283 mbx_sli4_parameters = &mqe->un.get_sli4_parameters.sli4_parameters;
11284 sli4_params->if_type = bf_get(cfg_if_type, mbx_sli4_parameters);
11285 sli4_params->sli_rev = bf_get(cfg_sli_rev, mbx_sli4_parameters);
11286 sli4_params->sli_family = bf_get(cfg_sli_family, mbx_sli4_parameters);
11287 sli4_params->featurelevel_1 = bf_get(cfg_sli_hint_1,
11288 mbx_sli4_parameters);
11289 sli4_params->featurelevel_2 = bf_get(cfg_sli_hint_2,
11290 mbx_sli4_parameters);
11291 if (bf_get(cfg_phwq, mbx_sli4_parameters))
11292 phba->sli3_options |= LPFC_SLI4_PHWQ_ENABLED;
11293 else
11294 phba->sli3_options &= ~LPFC_SLI4_PHWQ_ENABLED;
11295 sli4_params->sge_supp_len = mbx_sli4_parameters->sge_supp_len;
11296 sli4_params->loopbk_scope = bf_get(loopbk_scope, mbx_sli4_parameters);
1ba981fd 11297 sli4_params->oas_supported = bf_get(cfg_oas, mbx_sli4_parameters);
fedd3b7b
JS
11298 sli4_params->cqv = bf_get(cfg_cqv, mbx_sli4_parameters);
11299 sli4_params->mqv = bf_get(cfg_mqv, mbx_sli4_parameters);
11300 sli4_params->wqv = bf_get(cfg_wqv, mbx_sli4_parameters);
11301 sli4_params->rqv = bf_get(cfg_rqv, mbx_sli4_parameters);
7365f6fd
JS
11302 sli4_params->eqav = bf_get(cfg_eqav, mbx_sli4_parameters);
11303 sli4_params->cqav = bf_get(cfg_cqav, mbx_sli4_parameters);
0c651878 11304 sli4_params->wqsize = bf_get(cfg_wqsize, mbx_sli4_parameters);
66e9e6bf 11305 sli4_params->bv1s = bf_get(cfg_bv1s, mbx_sli4_parameters);
fedd3b7b
JS
11306 sli4_params->sgl_pages_max = bf_get(cfg_sgl_page_cnt,
11307 mbx_sli4_parameters);
895427bd 11308 sli4_params->wqpcnt = bf_get(cfg_wqpcnt, mbx_sli4_parameters);
fedd3b7b
JS
11309 sli4_params->sgl_pp_align = bf_get(cfg_sgl_pp_align,
11310 mbx_sli4_parameters);
6d368e53
JS
11311 phba->sli4_hba.extents_in_use = bf_get(cfg_ext, mbx_sli4_parameters);
11312 phba->sli4_hba.rpi_hdrs_in_use = bf_get(cfg_hdrr, mbx_sli4_parameters);
895427bd
JS
11313 phba->nvme_support = (bf_get(cfg_nvme, mbx_sli4_parameters) &&
11314 bf_get(cfg_xib, mbx_sli4_parameters));
11315
11316 if ((phba->cfg_enable_fc4_type == LPFC_ENABLE_FCP) ||
11317 !phba->nvme_support) {
11318 phba->nvme_support = 0;
11319 phba->nvmet_support = 0;
982ab128 11320 phba->cfg_nvmet_mrq = 0;
895427bd
JS
11321 lpfc_printf_log(phba, KERN_ERR, LOG_INIT | LOG_NVME,
11322 "6101 Disabling NVME support: "
11323 "Not supported by firmware: %d %d\n",
11324 bf_get(cfg_nvme, mbx_sli4_parameters),
11325 bf_get(cfg_xib, mbx_sli4_parameters));
11326
11327 /* If firmware doesn't support NVME, just use SCSI support */
11328 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
11329 return -ENODEV;
11330 phba->cfg_enable_fc4_type = LPFC_ENABLE_FCP;
11331 }
0558056c 11332
414abe0a
JS
11333 /* Only embed PBDE for if_type 6, PBDE support requires xib be set */
11334 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) !=
11335 LPFC_SLI_INTF_IF_TYPE_6) || (!bf_get(cfg_xib, mbx_sli4_parameters)))
11336 phba->cfg_enable_pbde = 0;
0bc2b7c5 11337
20aefac3
JS
11338 /*
11339 * To support Suppress Response feature we must satisfy 3 conditions.
11340 * lpfc_suppress_rsp module parameter must be set (default).
11341 * In SLI4-Parameters Descriptor:
11342 * Extended Inline Buffers (XIB) must be supported.
11343 * Suppress Response IU Not Supported (SRIUNS) must NOT be supported
11344 * (double negative).
11345 */
11346 if (phba->cfg_suppress_rsp && bf_get(cfg_xib, mbx_sli4_parameters) &&
11347 !(bf_get(cfg_nosr, mbx_sli4_parameters)))
f358dd0c 11348 phba->sli.sli_flag |= LPFC_SLI_SUPPRESS_RSP;
20aefac3
JS
11349 else
11350 phba->cfg_suppress_rsp = 0;
f358dd0c 11351
0cf07f84
JS
11352 if (bf_get(cfg_eqdr, mbx_sli4_parameters))
11353 phba->sli.sli_flag |= LPFC_SLI_USE_EQDR;
11354
0558056c
JS
11355 /* Make sure that sge_supp_len can be handled by the driver */
11356 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
11357 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
11358
b5c53958 11359 /*
c176ffa0
JS
11360 * Check whether the adapter supports an embedded copy of the
11361 * FCP CMD IU within the WQE for FCP_Ixxx commands. In order
11362 * to use this option, 128-byte WQEs must be used.
b5c53958
JS
11363 */
11364 if (bf_get(cfg_ext_embed_cb, mbx_sli4_parameters))
11365 phba->fcp_embed_io = 1;
11366 else
11367 phba->fcp_embed_io = 0;
7bdedb34 11368
0bc2b7c5 11369 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME,
414abe0a 11370 "6422 XIB %d PBDE %d: FCP %d NVME %d %d %d\n",
0bc2b7c5 11371 bf_get(cfg_xib, mbx_sli4_parameters),
414abe0a
JS
11372 phba->cfg_enable_pbde,
11373 phba->fcp_embed_io, phba->nvme_support,
4e565cf0 11374 phba->cfg_nvme_embed_cmd, phba->cfg_suppress_rsp);
0bc2b7c5 11375
bf316c78
JS
11376 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
11377 LPFC_SLI_INTF_IF_TYPE_2) &&
11378 (bf_get(lpfc_sli_intf_sli_family, &phba->sli4_hba.sli_intf) ==
c221768b 11379 LPFC_SLI_INTF_FAMILY_LNCR_A0))
bf316c78
JS
11380 exp_wqcq_pages = false;
11381
c176ffa0
JS
11382 if ((bf_get(cfg_cqpsize, mbx_sli4_parameters) & LPFC_CQ_16K_PAGE_SZ) &&
11383 (bf_get(cfg_wqpsize, mbx_sli4_parameters) & LPFC_WQ_16K_PAGE_SZ) &&
bf316c78 11384 exp_wqcq_pages &&
c176ffa0
JS
11385 (sli4_params->wqsize & LPFC_WQ_SZ128_SUPPORT))
11386 phba->enab_exp_wqcq_pages = 1;
11387 else
11388 phba->enab_exp_wqcq_pages = 0;
7bdedb34
JS
11389 /*
11390 * Check if the SLI port supports MDS Diagnostics
11391 */
11392 if (bf_get(cfg_mds_diags, mbx_sli4_parameters))
11393 phba->mds_diags_support = 1;
11394 else
11395 phba->mds_diags_support = 0;
d2cc9bcd 11396
fedd3b7b
JS
11397 return 0;
11398}
11399
da0436e9
JS
11400/**
11401 * lpfc_pci_probe_one_s3 - PCI probe func to reg SLI-3 device to PCI subsystem.
11402 * @pdev: pointer to PCI device
11403 * @pid: pointer to PCI device identifier
11404 *
11405 * This routine is to be called to attach a device with SLI-3 interface spec
11406 * to the PCI subsystem. When an Emulex HBA with SLI-3 interface spec is
11407 * presented on PCI bus, the kernel PCI subsystem looks at PCI device-specific
11408 * information of the device and driver to see if the driver state that it can
11409 * support this kind of device. If the match is successful, the driver core
11410 * invokes this routine. If this routine determines it can claim the HBA, it
11411 * does all the initialization that it needs to do to handle the HBA properly.
11412 *
11413 * Return code
11414 * 0 - driver can claim the device
11415 * negative value - driver can not claim the device
11416 **/
6f039790 11417static int
da0436e9
JS
11418lpfc_pci_probe_one_s3(struct pci_dev *pdev, const struct pci_device_id *pid)
11419{
11420 struct lpfc_hba *phba;
11421 struct lpfc_vport *vport = NULL;
6669f9bb 11422 struct Scsi_Host *shost = NULL;
da0436e9
JS
11423 int error;
11424 uint32_t cfg_mode, intr_mode;
11425
11426 /* Allocate memory for HBA structure */
11427 phba = lpfc_hba_alloc(pdev);
11428 if (!phba)
11429 return -ENOMEM;
11430
11431 /* Perform generic PCI device enabling operation */
11432 error = lpfc_enable_pci_dev(phba);
079b5c91 11433 if (error)
da0436e9 11434 goto out_free_phba;
da0436e9
JS
11435
11436 /* Set up SLI API function jump table for PCI-device group-0 HBAs */
11437 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_LP);
11438 if (error)
11439 goto out_disable_pci_dev;
11440
11441 /* Set up SLI-3 specific device PCI memory space */
11442 error = lpfc_sli_pci_mem_setup(phba);
11443 if (error) {
11444 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11445 "1402 Failed to set up pci memory space.\n");
11446 goto out_disable_pci_dev;
11447 }
11448
da0436e9
JS
11449 /* Set up SLI-3 specific device driver resources */
11450 error = lpfc_sli_driver_resource_setup(phba);
11451 if (error) {
11452 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11453 "1404 Failed to set up driver resource.\n");
11454 goto out_unset_pci_mem_s3;
11455 }
11456
11457 /* Initialize and populate the iocb list per host */
d1f525aa 11458
da0436e9
JS
11459 error = lpfc_init_iocb_list(phba, LPFC_IOCB_LIST_CNT);
11460 if (error) {
11461 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11462 "1405 Failed to initialize iocb list.\n");
11463 goto out_unset_driver_resource_s3;
11464 }
11465
11466 /* Set up common device driver resources */
11467 error = lpfc_setup_driver_resource_phase2(phba);
11468 if (error) {
11469 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11470 "1406 Failed to set up driver resource.\n");
11471 goto out_free_iocb_list;
11472 }
11473
079b5c91
JS
11474 /* Get the default values for Model Name and Description */
11475 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
11476
da0436e9
JS
11477 /* Create SCSI host to the physical port */
11478 error = lpfc_create_shost(phba);
11479 if (error) {
11480 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11481 "1407 Failed to create scsi host.\n");
11482 goto out_unset_driver_resource;
11483 }
11484
11485 /* Configure sysfs attributes */
11486 vport = phba->pport;
11487 error = lpfc_alloc_sysfs_attr(vport);
11488 if (error) {
11489 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11490 "1476 Failed to allocate sysfs attr\n");
11491 goto out_destroy_shost;
11492 }
11493
6669f9bb 11494 shost = lpfc_shost_from_vport(vport); /* save shost for error cleanup */
da0436e9
JS
11495 /* Now, trying to enable interrupt and bring up the device */
11496 cfg_mode = phba->cfg_use_msi;
11497 while (true) {
11498 /* Put device to a known state before enabling interrupt */
11499 lpfc_stop_port(phba);
11500 /* Configure and enable interrupt */
11501 intr_mode = lpfc_sli_enable_intr(phba, cfg_mode);
11502 if (intr_mode == LPFC_INTR_ERROR) {
11503 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11504 "0431 Failed to enable interrupt.\n");
11505 error = -ENODEV;
11506 goto out_free_sysfs_attr;
11507 }
11508 /* SLI-3 HBA setup */
11509 if (lpfc_sli_hba_setup(phba)) {
11510 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11511 "1477 Failed to set up hba\n");
11512 error = -ENODEV;
11513 goto out_remove_device;
11514 }
11515
11516 /* Wait 50ms for the interrupts of previous mailbox commands */
11517 msleep(50);
11518 /* Check active interrupts on message signaled interrupts */
11519 if (intr_mode == 0 ||
11520 phba->sli.slistat.sli_intr > LPFC_MSIX_VECTORS) {
11521 /* Log the current active interrupt mode */
11522 phba->intr_mode = intr_mode;
11523 lpfc_log_intr_mode(phba, intr_mode);
11524 break;
11525 } else {
11526 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11527 "0447 Configure interrupt mode (%d) "
11528 "failed active interrupt test.\n",
11529 intr_mode);
11530 /* Disable the current interrupt mode */
11531 lpfc_sli_disable_intr(phba);
11532 /* Try next level of interrupt mode */
11533 cfg_mode = --intr_mode;
11534 }
11535 }
11536
11537 /* Perform post initialization setup */
11538 lpfc_post_init_setup(phba);
11539
11540 /* Check if there are static vports to be created. */
11541 lpfc_create_static_vport(phba);
11542
11543 return 0;
11544
11545out_remove_device:
11546 lpfc_unset_hba(phba);
11547out_free_sysfs_attr:
11548 lpfc_free_sysfs_attr(vport);
11549out_destroy_shost:
11550 lpfc_destroy_shost(phba);
11551out_unset_driver_resource:
11552 lpfc_unset_driver_resource_phase2(phba);
11553out_free_iocb_list:
11554 lpfc_free_iocb_list(phba);
11555out_unset_driver_resource_s3:
11556 lpfc_sli_driver_resource_unset(phba);
11557out_unset_pci_mem_s3:
11558 lpfc_sli_pci_mem_unset(phba);
11559out_disable_pci_dev:
11560 lpfc_disable_pci_dev(phba);
6669f9bb
JS
11561 if (shost)
11562 scsi_host_put(shost);
da0436e9
JS
11563out_free_phba:
11564 lpfc_hba_free(phba);
11565 return error;
11566}
11567
11568/**
11569 * lpfc_pci_remove_one_s3 - PCI func to unreg SLI-3 device from PCI subsystem.
11570 * @pdev: pointer to PCI device
11571 *
11572 * This routine is to be called to disattach a device with SLI-3 interface
11573 * spec from PCI subsystem. When an Emulex HBA with SLI-3 interface spec is
11574 * removed from PCI bus, it performs all the necessary cleanup for the HBA
11575 * device to be removed from the PCI subsystem properly.
11576 **/
6f039790 11577static void
da0436e9
JS
11578lpfc_pci_remove_one_s3(struct pci_dev *pdev)
11579{
11580 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11581 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
11582 struct lpfc_vport **vports;
11583 struct lpfc_hba *phba = vport->phba;
11584 int i;
da0436e9
JS
11585
11586 spin_lock_irq(&phba->hbalock);
11587 vport->load_flag |= FC_UNLOADING;
11588 spin_unlock_irq(&phba->hbalock);
11589
11590 lpfc_free_sysfs_attr(vport);
11591
11592 /* Release all the vports against this physical port */
11593 vports = lpfc_create_vport_work_array(phba);
11594 if (vports != NULL)
587a37f6
JS
11595 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
11596 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
11597 continue;
da0436e9 11598 fc_vport_terminate(vports[i]->fc_vport);
587a37f6 11599 }
da0436e9
JS
11600 lpfc_destroy_vport_work_array(phba, vports);
11601
11602 /* Remove FC host and then SCSI host with the physical port */
11603 fc_remove_host(shost);
11604 scsi_remove_host(shost);
d613b6a7 11605
da0436e9
JS
11606 lpfc_cleanup(vport);
11607
11608 /*
11609 * Bring down the SLI Layer. This step disable all interrupts,
11610 * clears the rings, discards all mailbox commands, and resets
11611 * the HBA.
11612 */
11613
48e34d0f 11614 /* HBA interrupt will be disabled after this call */
da0436e9
JS
11615 lpfc_sli_hba_down(phba);
11616 /* Stop kthread signal shall trigger work_done one more time */
11617 kthread_stop(phba->worker_thread);
11618 /* Final cleanup of txcmplq and reset the HBA */
11619 lpfc_sli_brdrestart(phba);
11620
72859909
JS
11621 kfree(phba->vpi_bmask);
11622 kfree(phba->vpi_ids);
11623
da0436e9 11624 lpfc_stop_hba_timers(phba);
523128e5 11625 spin_lock_irq(&phba->port_list_lock);
da0436e9 11626 list_del_init(&vport->listentry);
523128e5 11627 spin_unlock_irq(&phba->port_list_lock);
da0436e9
JS
11628
11629 lpfc_debugfs_terminate(vport);
11630
912e3acd
JS
11631 /* Disable SR-IOV if enabled */
11632 if (phba->cfg_sriov_nr_virtfn)
11633 pci_disable_sriov(pdev);
11634
da0436e9
JS
11635 /* Disable interrupt */
11636 lpfc_sli_disable_intr(phba);
11637
da0436e9
JS
11638 scsi_host_put(shost);
11639
11640 /*
11641 * Call scsi_free before mem_free since scsi bufs are released to their
11642 * corresponding pools here.
11643 */
11644 lpfc_scsi_free(phba);
0794d601
JS
11645 lpfc_free_iocb_list(phba);
11646
da0436e9
JS
11647 lpfc_mem_free_all(phba);
11648
11649 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
11650 phba->hbqslimp.virt, phba->hbqslimp.phys);
11651
11652 /* Free resources associated with SLI2 interface */
11653 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
11654 phba->slim2p.virt, phba->slim2p.phys);
11655
11656 /* unmap adapter SLIM and Control Registers */
11657 iounmap(phba->ctrl_regs_memmap_p);
11658 iounmap(phba->slim_memmap_p);
11659
11660 lpfc_hba_free(phba);
11661
e0c0483c 11662 pci_release_mem_regions(pdev);
da0436e9
JS
11663 pci_disable_device(pdev);
11664}
11665
11666/**
11667 * lpfc_pci_suspend_one_s3 - PCI func to suspend SLI-3 device for power mgmnt
11668 * @pdev: pointer to PCI device
11669 * @msg: power management message
11670 *
11671 * This routine is to be called from the kernel's PCI subsystem to support
11672 * system Power Management (PM) to device with SLI-3 interface spec. When
11673 * PM invokes this method, it quiesces the device by stopping the driver's
11674 * worker thread for the device, turning off device's interrupt and DMA,
11675 * and bring the device offline. Note that as the driver implements the
11676 * minimum PM requirements to a power-aware driver's PM support for the
11677 * suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE, FREEZE)
11678 * to the suspend() method call will be treated as SUSPEND and the driver will
11679 * fully reinitialize its device during resume() method call, the driver will
11680 * set device to PCI_D3hot state in PCI config space instead of setting it
11681 * according to the @msg provided by the PM.
11682 *
11683 * Return code
11684 * 0 - driver suspended the device
11685 * Error otherwise
11686 **/
11687static int
11688lpfc_pci_suspend_one_s3(struct pci_dev *pdev, pm_message_t msg)
11689{
11690 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11691 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11692
11693 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11694 "0473 PCI device Power Management suspend.\n");
11695
11696 /* Bring down the device */
618a5230 11697 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
da0436e9
JS
11698 lpfc_offline(phba);
11699 kthread_stop(phba->worker_thread);
11700
11701 /* Disable interrupt from device */
11702 lpfc_sli_disable_intr(phba);
11703
11704 /* Save device state to PCI config space */
11705 pci_save_state(pdev);
11706 pci_set_power_state(pdev, PCI_D3hot);
11707
11708 return 0;
11709}
11710
11711/**
11712 * lpfc_pci_resume_one_s3 - PCI func to resume SLI-3 device for power mgmnt
11713 * @pdev: pointer to PCI device
11714 *
11715 * This routine is to be called from the kernel's PCI subsystem to support
11716 * system Power Management (PM) to device with SLI-3 interface spec. When PM
11717 * invokes this method, it restores the device's PCI config space state and
11718 * fully reinitializes the device and brings it online. Note that as the
11719 * driver implements the minimum PM requirements to a power-aware driver's
11720 * PM for suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE,
11721 * FREEZE) to the suspend() method call will be treated as SUSPEND and the
11722 * driver will fully reinitialize its device during resume() method call,
11723 * the device will be set to PCI_D0 directly in PCI config space before
11724 * restoring the state.
11725 *
11726 * Return code
11727 * 0 - driver suspended the device
11728 * Error otherwise
11729 **/
11730static int
11731lpfc_pci_resume_one_s3(struct pci_dev *pdev)
11732{
11733 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11734 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11735 uint32_t intr_mode;
11736 int error;
11737
11738 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11739 "0452 PCI device Power Management resume.\n");
11740
11741 /* Restore device state from PCI config space */
11742 pci_set_power_state(pdev, PCI_D0);
11743 pci_restore_state(pdev);
0d878419 11744
1dfb5a47
JS
11745 /*
11746 * As the new kernel behavior of pci_restore_state() API call clears
11747 * device saved_state flag, need to save the restored state again.
11748 */
11749 pci_save_state(pdev);
11750
da0436e9
JS
11751 if (pdev->is_busmaster)
11752 pci_set_master(pdev);
11753
11754 /* Startup the kernel thread for this host adapter. */
11755 phba->worker_thread = kthread_run(lpfc_do_work, phba,
11756 "lpfc_worker_%d", phba->brd_no);
11757 if (IS_ERR(phba->worker_thread)) {
11758 error = PTR_ERR(phba->worker_thread);
11759 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11760 "0434 PM resume failed to start worker "
11761 "thread: error=x%x.\n", error);
11762 return error;
11763 }
11764
11765 /* Configure and enable interrupt */
11766 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
11767 if (intr_mode == LPFC_INTR_ERROR) {
11768 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11769 "0430 PM resume Failed to enable interrupt\n");
11770 return -EIO;
11771 } else
11772 phba->intr_mode = intr_mode;
11773
11774 /* Restart HBA and bring it online */
11775 lpfc_sli_brdrestart(phba);
11776 lpfc_online(phba);
11777
11778 /* Log the current active interrupt mode */
11779 lpfc_log_intr_mode(phba, phba->intr_mode);
11780
11781 return 0;
11782}
11783
891478a2
JS
11784/**
11785 * lpfc_sli_prep_dev_for_recover - Prepare SLI3 device for pci slot recover
11786 * @phba: pointer to lpfc hba data structure.
11787 *
11788 * This routine is called to prepare the SLI3 device for PCI slot recover. It
e2af0d2e 11789 * aborts all the outstanding SCSI I/Os to the pci device.
891478a2
JS
11790 **/
11791static void
11792lpfc_sli_prep_dev_for_recover(struct lpfc_hba *phba)
11793{
11794 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11795 "2723 PCI channel I/O abort preparing for recovery\n");
e2af0d2e
JS
11796
11797 /*
11798 * There may be errored I/Os through HBA, abort all I/Os on txcmplq
11799 * and let the SCSI mid-layer to retry them to recover.
11800 */
db55fba8 11801 lpfc_sli_abort_fcp_rings(phba);
891478a2
JS
11802}
11803
0d878419
JS
11804/**
11805 * lpfc_sli_prep_dev_for_reset - Prepare SLI3 device for pci slot reset
11806 * @phba: pointer to lpfc hba data structure.
11807 *
11808 * This routine is called to prepare the SLI3 device for PCI slot reset. It
11809 * disables the device interrupt and pci device, and aborts the internal FCP
11810 * pending I/Os.
11811 **/
11812static void
11813lpfc_sli_prep_dev_for_reset(struct lpfc_hba *phba)
11814{
0d878419 11815 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
891478a2 11816 "2710 PCI channel disable preparing for reset\n");
e2af0d2e 11817
75baf696 11818 /* Block any management I/Os to the device */
618a5230 11819 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
75baf696 11820
e2af0d2e
JS
11821 /* Block all SCSI devices' I/Os on the host */
11822 lpfc_scsi_dev_block(phba);
11823
ea714f3d
JS
11824 /* Flush all driver's outstanding SCSI I/Os as we are to reset */
11825 lpfc_sli_flush_fcp_rings(phba);
11826
e2af0d2e
JS
11827 /* stop all timers */
11828 lpfc_stop_hba_timers(phba);
11829
0d878419
JS
11830 /* Disable interrupt and pci device */
11831 lpfc_sli_disable_intr(phba);
11832 pci_disable_device(phba->pcidev);
0d878419
JS
11833}
11834
11835/**
11836 * lpfc_sli_prep_dev_for_perm_failure - Prepare SLI3 dev for pci slot disable
11837 * @phba: pointer to lpfc hba data structure.
11838 *
11839 * This routine is called to prepare the SLI3 device for PCI slot permanently
11840 * disabling. It blocks the SCSI transport layer traffic and flushes the FCP
11841 * pending I/Os.
11842 **/
11843static void
75baf696 11844lpfc_sli_prep_dev_for_perm_failure(struct lpfc_hba *phba)
0d878419
JS
11845{
11846 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
891478a2 11847 "2711 PCI channel permanent disable for failure\n");
e2af0d2e
JS
11848 /* Block all SCSI devices' I/Os on the host */
11849 lpfc_scsi_dev_block(phba);
11850
11851 /* stop all timers */
11852 lpfc_stop_hba_timers(phba);
11853
0d878419
JS
11854 /* Clean up all driver's outstanding SCSI I/Os */
11855 lpfc_sli_flush_fcp_rings(phba);
11856}
11857
da0436e9
JS
11858/**
11859 * lpfc_io_error_detected_s3 - Method for handling SLI-3 device PCI I/O error
11860 * @pdev: pointer to PCI device.
11861 * @state: the current PCI connection state.
11862 *
11863 * This routine is called from the PCI subsystem for I/O error handling to
11864 * device with SLI-3 interface spec. This function is called by the PCI
11865 * subsystem after a PCI bus error affecting this device has been detected.
11866 * When this function is invoked, it will need to stop all the I/Os and
11867 * interrupt(s) to the device. Once that is done, it will return
11868 * PCI_ERS_RESULT_NEED_RESET for the PCI subsystem to perform proper recovery
11869 * as desired.
11870 *
11871 * Return codes
0d878419 11872 * PCI_ERS_RESULT_CAN_RECOVER - can be recovered with reset_link
da0436e9
JS
11873 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
11874 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
11875 **/
11876static pci_ers_result_t
11877lpfc_io_error_detected_s3(struct pci_dev *pdev, pci_channel_state_t state)
11878{
11879 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11880 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
da0436e9 11881
0d878419
JS
11882 switch (state) {
11883 case pci_channel_io_normal:
891478a2
JS
11884 /* Non-fatal error, prepare for recovery */
11885 lpfc_sli_prep_dev_for_recover(phba);
0d878419
JS
11886 return PCI_ERS_RESULT_CAN_RECOVER;
11887 case pci_channel_io_frozen:
11888 /* Fatal error, prepare for slot reset */
11889 lpfc_sli_prep_dev_for_reset(phba);
11890 return PCI_ERS_RESULT_NEED_RESET;
11891 case pci_channel_io_perm_failure:
11892 /* Permanent failure, prepare for device down */
75baf696 11893 lpfc_sli_prep_dev_for_perm_failure(phba);
da0436e9 11894 return PCI_ERS_RESULT_DISCONNECT;
0d878419
JS
11895 default:
11896 /* Unknown state, prepare and request slot reset */
11897 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11898 "0472 Unknown PCI error state: x%x\n", state);
11899 lpfc_sli_prep_dev_for_reset(phba);
11900 return PCI_ERS_RESULT_NEED_RESET;
da0436e9 11901 }
da0436e9
JS
11902}
11903
11904/**
11905 * lpfc_io_slot_reset_s3 - Method for restarting PCI SLI-3 device from scratch.
11906 * @pdev: pointer to PCI device.
11907 *
11908 * This routine is called from the PCI subsystem for error handling to
11909 * device with SLI-3 interface spec. This is called after PCI bus has been
11910 * reset to restart the PCI card from scratch, as if from a cold-boot.
11911 * During the PCI subsystem error recovery, after driver returns
11912 * PCI_ERS_RESULT_NEED_RESET, the PCI subsystem will perform proper error
11913 * recovery and then call this routine before calling the .resume method
11914 * to recover the device. This function will initialize the HBA device,
11915 * enable the interrupt, but it will just put the HBA to offline state
11916 * without passing any I/O traffic.
11917 *
11918 * Return codes
11919 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
11920 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
11921 */
11922static pci_ers_result_t
11923lpfc_io_slot_reset_s3(struct pci_dev *pdev)
11924{
11925 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11926 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11927 struct lpfc_sli *psli = &phba->sli;
11928 uint32_t intr_mode;
11929
11930 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
11931 if (pci_enable_device_mem(pdev)) {
11932 printk(KERN_ERR "lpfc: Cannot re-enable "
11933 "PCI device after reset.\n");
11934 return PCI_ERS_RESULT_DISCONNECT;
11935 }
11936
11937 pci_restore_state(pdev);
1dfb5a47
JS
11938
11939 /*
11940 * As the new kernel behavior of pci_restore_state() API call clears
11941 * device saved_state flag, need to save the restored state again.
11942 */
11943 pci_save_state(pdev);
11944
da0436e9
JS
11945 if (pdev->is_busmaster)
11946 pci_set_master(pdev);
11947
11948 spin_lock_irq(&phba->hbalock);
11949 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
11950 spin_unlock_irq(&phba->hbalock);
11951
11952 /* Configure and enable interrupt */
11953 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
11954 if (intr_mode == LPFC_INTR_ERROR) {
11955 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11956 "0427 Cannot re-enable interrupt after "
11957 "slot reset.\n");
11958 return PCI_ERS_RESULT_DISCONNECT;
11959 } else
11960 phba->intr_mode = intr_mode;
11961
75baf696 11962 /* Take device offline, it will perform cleanup */
618a5230 11963 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
da0436e9
JS
11964 lpfc_offline(phba);
11965 lpfc_sli_brdrestart(phba);
11966
11967 /* Log the current active interrupt mode */
11968 lpfc_log_intr_mode(phba, phba->intr_mode);
11969
11970 return PCI_ERS_RESULT_RECOVERED;
11971}
11972
11973/**
11974 * lpfc_io_resume_s3 - Method for resuming PCI I/O operation on SLI-3 device.
11975 * @pdev: pointer to PCI device
11976 *
11977 * This routine is called from the PCI subsystem for error handling to device
11978 * with SLI-3 interface spec. It is called when kernel error recovery tells
11979 * the lpfc driver that it is ok to resume normal PCI operation after PCI bus
11980 * error recovery. After this call, traffic can start to flow from this device
11981 * again.
11982 */
11983static void
11984lpfc_io_resume_s3(struct pci_dev *pdev)
11985{
11986 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11987 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
3772a991 11988
e2af0d2e 11989 /* Bring device online, it will be no-op for non-fatal error resume */
da0436e9
JS
11990 lpfc_online(phba);
11991}
3772a991 11992
da0436e9
JS
11993/**
11994 * lpfc_sli4_get_els_iocb_cnt - Calculate the # of ELS IOCBs to reserve
11995 * @phba: pointer to lpfc hba data structure.
11996 *
11997 * returns the number of ELS/CT IOCBs to reserve
11998 **/
11999int
12000lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *phba)
12001{
12002 int max_xri = phba->sli4_hba.max_cfg_param.max_xri;
12003
f1126688
JS
12004 if (phba->sli_rev == LPFC_SLI_REV4) {
12005 if (max_xri <= 100)
6a9c52cf 12006 return 10;
f1126688 12007 else if (max_xri <= 256)
6a9c52cf 12008 return 25;
f1126688 12009 else if (max_xri <= 512)
6a9c52cf 12010 return 50;
f1126688 12011 else if (max_xri <= 1024)
6a9c52cf 12012 return 100;
8a9d2e80 12013 else if (max_xri <= 1536)
6a9c52cf 12014 return 150;
8a9d2e80
JS
12015 else if (max_xri <= 2048)
12016 return 200;
12017 else
12018 return 250;
f1126688
JS
12019 } else
12020 return 0;
3772a991
JS
12021}
12022
895427bd
JS
12023/**
12024 * lpfc_sli4_get_iocb_cnt - Calculate the # of total IOCBs to reserve
12025 * @phba: pointer to lpfc hba data structure.
12026 *
f358dd0c 12027 * returns the number of ELS/CT + NVMET IOCBs to reserve
895427bd
JS
12028 **/
12029int
12030lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba)
12031{
12032 int max_xri = lpfc_sli4_get_els_iocb_cnt(phba);
12033
f358dd0c
JS
12034 if (phba->nvmet_support)
12035 max_xri += LPFC_NVMET_BUF_POST;
895427bd
JS
12036 return max_xri;
12037}
12038
12039
1feb8204
JS
12040static void
12041lpfc_log_write_firmware_error(struct lpfc_hba *phba, uint32_t offset,
12042 uint32_t magic_number, uint32_t ftype, uint32_t fid, uint32_t fsize,
12043 const struct firmware *fw)
12044{
a72d56b2
JS
12045 if ((offset == ADD_STATUS_FW_NOT_SUPPORTED) ||
12046 (phba->pcidev->device == PCI_DEVICE_ID_LANCER_G6_FC &&
12047 magic_number != MAGIC_NUMER_G6) ||
12048 (phba->pcidev->device == PCI_DEVICE_ID_LANCER_G7_FC &&
12049 magic_number != MAGIC_NUMER_G7))
1feb8204
JS
12050 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12051 "3030 This firmware version is not supported on "
12052 "this HBA model. Device:%x Magic:%x Type:%x "
12053 "ID:%x Size %d %zd\n",
12054 phba->pcidev->device, magic_number, ftype, fid,
12055 fsize, fw->size);
12056 else
12057 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12058 "3022 FW Download failed. Device:%x Magic:%x Type:%x "
12059 "ID:%x Size %d %zd\n",
12060 phba->pcidev->device, magic_number, ftype, fid,
12061 fsize, fw->size);
12062}
12063
12064
52d52440
JS
12065/**
12066 * lpfc_write_firmware - attempt to write a firmware image to the port
52d52440 12067 * @fw: pointer to firmware image returned from request_firmware.
ce396282 12068 * @phba: pointer to lpfc hba data structure.
52d52440 12069 *
52d52440 12070 **/
ce396282
JS
12071static void
12072lpfc_write_firmware(const struct firmware *fw, void *context)
52d52440 12073{
ce396282 12074 struct lpfc_hba *phba = (struct lpfc_hba *)context;
6b5151fd 12075 char fwrev[FW_REV_STR_SIZE];
ce396282 12076 struct lpfc_grp_hdr *image;
52d52440
JS
12077 struct list_head dma_buffer_list;
12078 int i, rc = 0;
12079 struct lpfc_dmabuf *dmabuf, *next;
12080 uint32_t offset = 0, temp_offset = 0;
6b6ef5db 12081 uint32_t magic_number, ftype, fid, fsize;
52d52440 12082
c71ab861 12083 /* It can be null in no-wait mode, sanity check */
ce396282
JS
12084 if (!fw) {
12085 rc = -ENXIO;
12086 goto out;
12087 }
12088 image = (struct lpfc_grp_hdr *)fw->data;
12089
6b6ef5db
JS
12090 magic_number = be32_to_cpu(image->magic_number);
12091 ftype = bf_get_be32(lpfc_grp_hdr_file_type, image);
1feb8204 12092 fid = bf_get_be32(lpfc_grp_hdr_id, image);
6b6ef5db
JS
12093 fsize = be32_to_cpu(image->size);
12094
52d52440 12095 INIT_LIST_HEAD(&dma_buffer_list);
52d52440 12096 lpfc_decode_firmware_rev(phba, fwrev, 1);
88a2cfbb 12097 if (strncmp(fwrev, image->revision, strnlen(image->revision, 16))) {
52d52440 12098 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
ce396282 12099 "3023 Updating Firmware, Current Version:%s "
52d52440 12100 "New Version:%s\n",
88a2cfbb 12101 fwrev, image->revision);
52d52440
JS
12102 for (i = 0; i < LPFC_MBX_WR_CONFIG_MAX_BDE; i++) {
12103 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf),
12104 GFP_KERNEL);
12105 if (!dmabuf) {
12106 rc = -ENOMEM;
ce396282 12107 goto release_out;
52d52440
JS
12108 }
12109 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
12110 SLI4_PAGE_SIZE,
12111 &dmabuf->phys,
12112 GFP_KERNEL);
12113 if (!dmabuf->virt) {
12114 kfree(dmabuf);
12115 rc = -ENOMEM;
ce396282 12116 goto release_out;
52d52440
JS
12117 }
12118 list_add_tail(&dmabuf->list, &dma_buffer_list);
12119 }
12120 while (offset < fw->size) {
12121 temp_offset = offset;
12122 list_for_each_entry(dmabuf, &dma_buffer_list, list) {
079b5c91 12123 if (temp_offset + SLI4_PAGE_SIZE > fw->size) {
52d52440
JS
12124 memcpy(dmabuf->virt,
12125 fw->data + temp_offset,
079b5c91
JS
12126 fw->size - temp_offset);
12127 temp_offset = fw->size;
52d52440
JS
12128 break;
12129 }
52d52440
JS
12130 memcpy(dmabuf->virt, fw->data + temp_offset,
12131 SLI4_PAGE_SIZE);
88a2cfbb 12132 temp_offset += SLI4_PAGE_SIZE;
52d52440
JS
12133 }
12134 rc = lpfc_wr_object(phba, &dma_buffer_list,
12135 (fw->size - offset), &offset);
1feb8204
JS
12136 if (rc) {
12137 lpfc_log_write_firmware_error(phba, offset,
12138 magic_number, ftype, fid, fsize, fw);
ce396282 12139 goto release_out;
1feb8204 12140 }
52d52440
JS
12141 }
12142 rc = offset;
1feb8204
JS
12143 } else
12144 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12145 "3029 Skipped Firmware update, Current "
12146 "Version:%s New Version:%s\n",
12147 fwrev, image->revision);
ce396282
JS
12148
12149release_out:
52d52440
JS
12150 list_for_each_entry_safe(dmabuf, next, &dma_buffer_list, list) {
12151 list_del(&dmabuf->list);
12152 dma_free_coherent(&phba->pcidev->dev, SLI4_PAGE_SIZE,
12153 dmabuf->virt, dmabuf->phys);
12154 kfree(dmabuf);
12155 }
ce396282
JS
12156 release_firmware(fw);
12157out:
12158 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
c71ab861 12159 "3024 Firmware update done: %d.\n", rc);
ce396282 12160 return;
52d52440
JS
12161}
12162
c71ab861
JS
12163/**
12164 * lpfc_sli4_request_firmware_update - Request linux generic firmware upgrade
12165 * @phba: pointer to lpfc hba data structure.
12166 *
12167 * This routine is called to perform Linux generic firmware upgrade on device
12168 * that supports such feature.
12169 **/
12170int
12171lpfc_sli4_request_firmware_update(struct lpfc_hba *phba, uint8_t fw_upgrade)
12172{
12173 uint8_t file_name[ELX_MODEL_NAME_SIZE];
12174 int ret;
12175 const struct firmware *fw;
12176
12177 /* Only supported on SLI4 interface type 2 for now */
27d6ac0a 12178 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) <
c71ab861
JS
12179 LPFC_SLI_INTF_IF_TYPE_2)
12180 return -EPERM;
12181
12182 snprintf(file_name, ELX_MODEL_NAME_SIZE, "%s.grp", phba->ModelName);
12183
12184 if (fw_upgrade == INT_FW_UPGRADE) {
12185 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
12186 file_name, &phba->pcidev->dev,
12187 GFP_KERNEL, (void *)phba,
12188 lpfc_write_firmware);
12189 } else if (fw_upgrade == RUN_FW_UPGRADE) {
12190 ret = request_firmware(&fw, file_name, &phba->pcidev->dev);
12191 if (!ret)
12192 lpfc_write_firmware(fw, (void *)phba);
12193 } else {
12194 ret = -EINVAL;
12195 }
12196
12197 return ret;
12198}
12199
3772a991 12200/**
da0436e9 12201 * lpfc_pci_probe_one_s4 - PCI probe func to reg SLI-4 device to PCI subsys
3772a991
JS
12202 * @pdev: pointer to PCI device
12203 * @pid: pointer to PCI device identifier
12204 *
da0436e9
JS
12205 * This routine is called from the kernel's PCI subsystem to device with
12206 * SLI-4 interface spec. When an Emulex HBA with SLI-4 interface spec is
3772a991 12207 * presented on PCI bus, the kernel PCI subsystem looks at PCI device-specific
da0436e9
JS
12208 * information of the device and driver to see if the driver state that it
12209 * can support this kind of device. If the match is successful, the driver
12210 * core invokes this routine. If this routine determines it can claim the HBA,
12211 * it does all the initialization that it needs to do to handle the HBA
12212 * properly.
3772a991
JS
12213 *
12214 * Return code
12215 * 0 - driver can claim the device
12216 * negative value - driver can not claim the device
12217 **/
6f039790 12218static int
da0436e9 12219lpfc_pci_probe_one_s4(struct pci_dev *pdev, const struct pci_device_id *pid)
3772a991
JS
12220{
12221 struct lpfc_hba *phba;
12222 struct lpfc_vport *vport = NULL;
6669f9bb 12223 struct Scsi_Host *shost = NULL;
6c621a22 12224 int error;
3772a991
JS
12225 uint32_t cfg_mode, intr_mode;
12226
12227 /* Allocate memory for HBA structure */
12228 phba = lpfc_hba_alloc(pdev);
12229 if (!phba)
12230 return -ENOMEM;
12231
12232 /* Perform generic PCI device enabling operation */
12233 error = lpfc_enable_pci_dev(phba);
079b5c91 12234 if (error)
3772a991 12235 goto out_free_phba;
3772a991 12236
da0436e9
JS
12237 /* Set up SLI API function jump table for PCI-device group-1 HBAs */
12238 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_OC);
3772a991
JS
12239 if (error)
12240 goto out_disable_pci_dev;
12241
da0436e9
JS
12242 /* Set up SLI-4 specific device PCI memory space */
12243 error = lpfc_sli4_pci_mem_setup(phba);
3772a991
JS
12244 if (error) {
12245 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 12246 "1410 Failed to set up pci memory space.\n");
3772a991
JS
12247 goto out_disable_pci_dev;
12248 }
12249
da0436e9
JS
12250 /* Set up SLI-4 Specific device driver resources */
12251 error = lpfc_sli4_driver_resource_setup(phba);
3772a991
JS
12252 if (error) {
12253 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9
JS
12254 "1412 Failed to set up driver resource.\n");
12255 goto out_unset_pci_mem_s4;
3772a991
JS
12256 }
12257
19ca7609 12258 INIT_LIST_HEAD(&phba->active_rrq_list);
7d791df7 12259 INIT_LIST_HEAD(&phba->fcf.fcf_pri_list);
19ca7609 12260
3772a991
JS
12261 /* Set up common device driver resources */
12262 error = lpfc_setup_driver_resource_phase2(phba);
12263 if (error) {
12264 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 12265 "1414 Failed to set up driver resource.\n");
6c621a22 12266 goto out_unset_driver_resource_s4;
3772a991
JS
12267 }
12268
079b5c91
JS
12269 /* Get the default values for Model Name and Description */
12270 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
12271
3772a991 12272 /* Now, trying to enable interrupt and bring up the device */
5b75da2f 12273 cfg_mode = phba->cfg_use_msi;
5b75da2f 12274
7b15db32 12275 /* Put device to a known state before enabling interrupt */
cdb42bec 12276 phba->pport = NULL;
7b15db32 12277 lpfc_stop_port(phba);
895427bd 12278
7b15db32
JS
12279 /* Configure and enable interrupt */
12280 intr_mode = lpfc_sli4_enable_intr(phba, cfg_mode);
12281 if (intr_mode == LPFC_INTR_ERROR) {
12282 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12283 "0426 Failed to enable interrupt.\n");
12284 error = -ENODEV;
cdb42bec 12285 goto out_unset_driver_resource;
7b15db32
JS
12286 }
12287 /* Default to single EQ for non-MSI-X */
895427bd 12288 if (phba->intr_type != MSIX) {
6a828b0f 12289 phba->cfg_irq_chann = 1;
2d7dbc4c 12290 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
2d7dbc4c
JS
12291 if (phba->nvmet_support)
12292 phba->cfg_nvmet_mrq = 1;
12293 }
cdb42bec 12294 }
6a828b0f 12295 lpfc_cpu_affinity_check(phba, phba->cfg_irq_chann);
cdb42bec
JS
12296
12297 /* Create SCSI host to the physical port */
12298 error = lpfc_create_shost(phba);
12299 if (error) {
12300 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12301 "1415 Failed to create scsi host.\n");
12302 goto out_disable_intr;
12303 }
12304 vport = phba->pport;
12305 shost = lpfc_shost_from_vport(vport); /* save shost for error cleanup */
12306
12307 /* Configure sysfs attributes */
12308 error = lpfc_alloc_sysfs_attr(vport);
12309 if (error) {
12310 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12311 "1416 Failed to allocate sysfs attr\n");
12312 goto out_destroy_shost;
895427bd
JS
12313 }
12314
7b15db32
JS
12315 /* Set up SLI-4 HBA */
12316 if (lpfc_sli4_hba_setup(phba)) {
12317 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12318 "1421 Failed to set up hba\n");
12319 error = -ENODEV;
cdb42bec 12320 goto out_free_sysfs_attr;
98c9ea5c 12321 }
858c9f6c 12322
7b15db32
JS
12323 /* Log the current active interrupt mode */
12324 phba->intr_mode = intr_mode;
12325 lpfc_log_intr_mode(phba, intr_mode);
12326
3772a991
JS
12327 /* Perform post initialization setup */
12328 lpfc_post_init_setup(phba);
dea3101e 12329
01649561
JS
12330 /* NVME support in FW earlier in the driver load corrects the
12331 * FC4 type making a check for nvme_support unnecessary.
12332 */
0794d601
JS
12333 if (phba->nvmet_support == 0) {
12334 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
12335 /* Create NVME binding with nvme_fc_transport. This
12336 * ensures the vport is initialized. If the localport
12337 * create fails, it should not unload the driver to
12338 * support field issues.
12339 */
12340 error = lpfc_nvme_create_localport(vport);
12341 if (error) {
12342 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12343 "6004 NVME registration "
12344 "failed, error x%x\n",
12345 error);
12346 }
01649561
JS
12347 }
12348 }
895427bd 12349
c71ab861
JS
12350 /* check for firmware upgrade or downgrade */
12351 if (phba->cfg_request_firmware_upgrade)
db6f1c2f 12352 lpfc_sli4_request_firmware_update(phba, INT_FW_UPGRADE);
52d52440 12353
1c6834a7
JS
12354 /* Check if there are static vports to be created. */
12355 lpfc_create_static_vport(phba);
d2cc9bcd
JS
12356
12357 /* Enable RAS FW log support */
12358 lpfc_sli4_ras_setup(phba);
12359
dea3101e 12360 return 0;
12361
5b75da2f
JS
12362out_free_sysfs_attr:
12363 lpfc_free_sysfs_attr(vport);
3772a991
JS
12364out_destroy_shost:
12365 lpfc_destroy_shost(phba);
cdb42bec
JS
12366out_disable_intr:
12367 lpfc_sli4_disable_intr(phba);
3772a991
JS
12368out_unset_driver_resource:
12369 lpfc_unset_driver_resource_phase2(phba);
da0436e9
JS
12370out_unset_driver_resource_s4:
12371 lpfc_sli4_driver_resource_unset(phba);
12372out_unset_pci_mem_s4:
12373 lpfc_sli4_pci_mem_unset(phba);
3772a991
JS
12374out_disable_pci_dev:
12375 lpfc_disable_pci_dev(phba);
6669f9bb
JS
12376 if (shost)
12377 scsi_host_put(shost);
2e0fef85 12378out_free_phba:
3772a991 12379 lpfc_hba_free(phba);
dea3101e 12380 return error;
12381}
12382
e59058c4 12383/**
da0436e9 12384 * lpfc_pci_remove_one_s4 - PCI func to unreg SLI-4 device from PCI subsystem
e59058c4
JS
12385 * @pdev: pointer to PCI device
12386 *
da0436e9
JS
12387 * This routine is called from the kernel's PCI subsystem to device with
12388 * SLI-4 interface spec. When an Emulex HBA with SLI-4 interface spec is
3772a991
JS
12389 * removed from PCI bus, it performs all the necessary cleanup for the HBA
12390 * device to be removed from the PCI subsystem properly.
e59058c4 12391 **/
6f039790 12392static void
da0436e9 12393lpfc_pci_remove_one_s4(struct pci_dev *pdev)
dea3101e 12394{
da0436e9 12395 struct Scsi_Host *shost = pci_get_drvdata(pdev);
2e0fef85 12396 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
eada272d 12397 struct lpfc_vport **vports;
da0436e9 12398 struct lpfc_hba *phba = vport->phba;
eada272d 12399 int i;
8a4df120 12400
da0436e9 12401 /* Mark the device unloading flag */
549e55cd 12402 spin_lock_irq(&phba->hbalock);
51ef4c26 12403 vport->load_flag |= FC_UNLOADING;
549e55cd 12404 spin_unlock_irq(&phba->hbalock);
2e0fef85 12405
da0436e9 12406 /* Free the HBA sysfs attributes */
858c9f6c
JS
12407 lpfc_free_sysfs_attr(vport);
12408
eada272d
JS
12409 /* Release all the vports against this physical port */
12410 vports = lpfc_create_vport_work_array(phba);
12411 if (vports != NULL)
587a37f6
JS
12412 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
12413 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
12414 continue;
eada272d 12415 fc_vport_terminate(vports[i]->fc_vport);
587a37f6 12416 }
eada272d
JS
12417 lpfc_destroy_vport_work_array(phba, vports);
12418
12419 /* Remove FC host and then SCSI host with the physical port */
858c9f6c
JS
12420 fc_remove_host(shost);
12421 scsi_remove_host(shost);
da0436e9 12422
d613b6a7
JS
12423 /* Perform ndlp cleanup on the physical port. The nvme and nvmet
12424 * localports are destroyed after to cleanup all transport memory.
895427bd 12425 */
87af33fe 12426 lpfc_cleanup(vport);
d613b6a7
JS
12427 lpfc_nvmet_destroy_targetport(phba);
12428 lpfc_nvme_destroy_localport(vport);
87af33fe 12429
c490850a
JS
12430 /* De-allocate multi-XRI pools */
12431 if (phba->cfg_xri_rebalancing)
12432 lpfc_destroy_multixri_pools(phba);
12433
281d6190
JS
12434 /*
12435 * Bring down the SLI Layer. This step disables all interrupts,
12436 * clears the rings, discards all mailbox commands, and resets
12437 * the HBA FCoE function.
12438 */
12439 lpfc_debugfs_terminate(vport);
a257bf90 12440
1901762f 12441 lpfc_stop_hba_timers(phba);
523128e5 12442 spin_lock_irq(&phba->port_list_lock);
858c9f6c 12443 list_del_init(&vport->listentry);
523128e5 12444 spin_unlock_irq(&phba->port_list_lock);
858c9f6c 12445
3677a3a7 12446 /* Perform scsi free before driver resource_unset since scsi
da0436e9 12447 * buffers are released to their corresponding pools here.
2e0fef85 12448 */
5e5b511d 12449 lpfc_io_free(phba);
01649561 12450 lpfc_free_iocb_list(phba);
5e5b511d 12451 lpfc_sli4_hba_unset(phba);
67d12733 12452
0cdb84ec 12453 lpfc_unset_driver_resource_phase2(phba);
da0436e9 12454 lpfc_sli4_driver_resource_unset(phba);
ed957684 12455
da0436e9
JS
12456 /* Unmap adapter Control and Doorbell registers */
12457 lpfc_sli4_pci_mem_unset(phba);
2e0fef85 12458
da0436e9
JS
12459 /* Release PCI resources and disable device's PCI function */
12460 scsi_host_put(shost);
12461 lpfc_disable_pci_dev(phba);
2e0fef85 12462
da0436e9 12463 /* Finally, free the driver's device data structure */
3772a991 12464 lpfc_hba_free(phba);
2e0fef85 12465
da0436e9 12466 return;
dea3101e 12467}
12468
3a55b532 12469/**
da0436e9 12470 * lpfc_pci_suspend_one_s4 - PCI func to suspend SLI-4 device for power mgmnt
3a55b532
JS
12471 * @pdev: pointer to PCI device
12472 * @msg: power management message
12473 *
da0436e9
JS
12474 * This routine is called from the kernel's PCI subsystem to support system
12475 * Power Management (PM) to device with SLI-4 interface spec. When PM invokes
12476 * this method, it quiesces the device by stopping the driver's worker
12477 * thread for the device, turning off device's interrupt and DMA, and bring
12478 * the device offline. Note that as the driver implements the minimum PM
12479 * requirements to a power-aware driver's PM support for suspend/resume -- all
12480 * the possible PM messages (SUSPEND, HIBERNATE, FREEZE) to the suspend()
12481 * method call will be treated as SUSPEND and the driver will fully
12482 * reinitialize its device during resume() method call, the driver will set
12483 * device to PCI_D3hot state in PCI config space instead of setting it
3772a991 12484 * according to the @msg provided by the PM.
3a55b532
JS
12485 *
12486 * Return code
3772a991
JS
12487 * 0 - driver suspended the device
12488 * Error otherwise
3a55b532
JS
12489 **/
12490static int
da0436e9 12491lpfc_pci_suspend_one_s4(struct pci_dev *pdev, pm_message_t msg)
3a55b532
JS
12492{
12493 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12494 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12495
12496 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
75baf696 12497 "2843 PCI device Power Management suspend.\n");
3a55b532
JS
12498
12499 /* Bring down the device */
618a5230 12500 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
3a55b532
JS
12501 lpfc_offline(phba);
12502 kthread_stop(phba->worker_thread);
12503
12504 /* Disable interrupt from device */
da0436e9 12505 lpfc_sli4_disable_intr(phba);
5350d872 12506 lpfc_sli4_queue_destroy(phba);
3a55b532
JS
12507
12508 /* Save device state to PCI config space */
12509 pci_save_state(pdev);
12510 pci_set_power_state(pdev, PCI_D3hot);
12511
12512 return 0;
12513}
12514
12515/**
da0436e9 12516 * lpfc_pci_resume_one_s4 - PCI func to resume SLI-4 device for power mgmnt
3a55b532
JS
12517 * @pdev: pointer to PCI device
12518 *
da0436e9
JS
12519 * This routine is called from the kernel's PCI subsystem to support system
12520 * Power Management (PM) to device with SLI-4 interface spac. When PM invokes
12521 * this method, it restores the device's PCI config space state and fully
12522 * reinitializes the device and brings it online. Note that as the driver
12523 * implements the minimum PM requirements to a power-aware driver's PM for
12524 * suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE, FREEZE)
12525 * to the suspend() method call will be treated as SUSPEND and the driver
12526 * will fully reinitialize its device during resume() method call, the device
12527 * will be set to PCI_D0 directly in PCI config space before restoring the
12528 * state.
3a55b532
JS
12529 *
12530 * Return code
3772a991
JS
12531 * 0 - driver suspended the device
12532 * Error otherwise
3a55b532
JS
12533 **/
12534static int
da0436e9 12535lpfc_pci_resume_one_s4(struct pci_dev *pdev)
3a55b532
JS
12536{
12537 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12538 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
5b75da2f 12539 uint32_t intr_mode;
3a55b532
JS
12540 int error;
12541
12542 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
da0436e9 12543 "0292 PCI device Power Management resume.\n");
3a55b532
JS
12544
12545 /* Restore device state from PCI config space */
12546 pci_set_power_state(pdev, PCI_D0);
12547 pci_restore_state(pdev);
1dfb5a47
JS
12548
12549 /*
12550 * As the new kernel behavior of pci_restore_state() API call clears
12551 * device saved_state flag, need to save the restored state again.
12552 */
12553 pci_save_state(pdev);
12554
3a55b532
JS
12555 if (pdev->is_busmaster)
12556 pci_set_master(pdev);
12557
da0436e9 12558 /* Startup the kernel thread for this host adapter. */
3a55b532
JS
12559 phba->worker_thread = kthread_run(lpfc_do_work, phba,
12560 "lpfc_worker_%d", phba->brd_no);
12561 if (IS_ERR(phba->worker_thread)) {
12562 error = PTR_ERR(phba->worker_thread);
12563 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 12564 "0293 PM resume failed to start worker "
3a55b532
JS
12565 "thread: error=x%x.\n", error);
12566 return error;
12567 }
12568
5b75da2f 12569 /* Configure and enable interrupt */
da0436e9 12570 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
5b75da2f 12571 if (intr_mode == LPFC_INTR_ERROR) {
3a55b532 12572 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 12573 "0294 PM resume Failed to enable interrupt\n");
5b75da2f
JS
12574 return -EIO;
12575 } else
12576 phba->intr_mode = intr_mode;
3a55b532
JS
12577
12578 /* Restart HBA and bring it online */
12579 lpfc_sli_brdrestart(phba);
12580 lpfc_online(phba);
12581
5b75da2f
JS
12582 /* Log the current active interrupt mode */
12583 lpfc_log_intr_mode(phba, phba->intr_mode);
12584
3a55b532
JS
12585 return 0;
12586}
12587
75baf696
JS
12588/**
12589 * lpfc_sli4_prep_dev_for_recover - Prepare SLI4 device for pci slot recover
12590 * @phba: pointer to lpfc hba data structure.
12591 *
12592 * This routine is called to prepare the SLI4 device for PCI slot recover. It
12593 * aborts all the outstanding SCSI I/Os to the pci device.
12594 **/
12595static void
12596lpfc_sli4_prep_dev_for_recover(struct lpfc_hba *phba)
12597{
75baf696
JS
12598 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12599 "2828 PCI channel I/O abort preparing for recovery\n");
12600 /*
12601 * There may be errored I/Os through HBA, abort all I/Os on txcmplq
12602 * and let the SCSI mid-layer to retry them to recover.
12603 */
db55fba8 12604 lpfc_sli_abort_fcp_rings(phba);
75baf696
JS
12605}
12606
12607/**
12608 * lpfc_sli4_prep_dev_for_reset - Prepare SLI4 device for pci slot reset
12609 * @phba: pointer to lpfc hba data structure.
12610 *
12611 * This routine is called to prepare the SLI4 device for PCI slot reset. It
12612 * disables the device interrupt and pci device, and aborts the internal FCP
12613 * pending I/Os.
12614 **/
12615static void
12616lpfc_sli4_prep_dev_for_reset(struct lpfc_hba *phba)
12617{
12618 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12619 "2826 PCI channel disable preparing for reset\n");
12620
12621 /* Block any management I/Os to the device */
618a5230 12622 lpfc_block_mgmt_io(phba, LPFC_MBX_NO_WAIT);
75baf696
JS
12623
12624 /* Block all SCSI devices' I/Os on the host */
12625 lpfc_scsi_dev_block(phba);
12626
ea714f3d
JS
12627 /* Flush all driver's outstanding SCSI I/Os as we are to reset */
12628 lpfc_sli_flush_fcp_rings(phba);
12629
c3725bdc
JS
12630 /* Flush the outstanding NVME IOs if fc4 type enabled. */
12631 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
12632 lpfc_sli_flush_nvme_rings(phba);
12633
75baf696
JS
12634 /* stop all timers */
12635 lpfc_stop_hba_timers(phba);
12636
12637 /* Disable interrupt and pci device */
12638 lpfc_sli4_disable_intr(phba);
5350d872 12639 lpfc_sli4_queue_destroy(phba);
75baf696 12640 pci_disable_device(phba->pcidev);
75baf696
JS
12641}
12642
12643/**
12644 * lpfc_sli4_prep_dev_for_perm_failure - Prepare SLI4 dev for pci slot disable
12645 * @phba: pointer to lpfc hba data structure.
12646 *
12647 * This routine is called to prepare the SLI4 device for PCI slot permanently
12648 * disabling. It blocks the SCSI transport layer traffic and flushes the FCP
12649 * pending I/Os.
12650 **/
12651static void
12652lpfc_sli4_prep_dev_for_perm_failure(struct lpfc_hba *phba)
12653{
12654 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12655 "2827 PCI channel permanent disable for failure\n");
12656
12657 /* Block all SCSI devices' I/Os on the host */
12658 lpfc_scsi_dev_block(phba);
12659
12660 /* stop all timers */
12661 lpfc_stop_hba_timers(phba);
12662
12663 /* Clean up all driver's outstanding SCSI I/Os */
12664 lpfc_sli_flush_fcp_rings(phba);
c3725bdc
JS
12665
12666 /* Flush the outstanding NVME IOs if fc4 type enabled. */
12667 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
12668 lpfc_sli_flush_nvme_rings(phba);
75baf696
JS
12669}
12670
8d63f375 12671/**
da0436e9 12672 * lpfc_io_error_detected_s4 - Method for handling PCI I/O error to SLI-4 device
e59058c4
JS
12673 * @pdev: pointer to PCI device.
12674 * @state: the current PCI connection state.
8d63f375 12675 *
da0436e9
JS
12676 * This routine is called from the PCI subsystem for error handling to device
12677 * with SLI-4 interface spec. This function is called by the PCI subsystem
12678 * after a PCI bus error affecting this device has been detected. When this
12679 * function is invoked, it will need to stop all the I/Os and interrupt(s)
12680 * to the device. Once that is done, it will return PCI_ERS_RESULT_NEED_RESET
12681 * for the PCI subsystem to perform proper recovery as desired.
e59058c4
JS
12682 *
12683 * Return codes
3772a991
JS
12684 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
12685 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
e59058c4 12686 **/
3772a991 12687static pci_ers_result_t
da0436e9 12688lpfc_io_error_detected_s4(struct pci_dev *pdev, pci_channel_state_t state)
8d63f375 12689{
75baf696
JS
12690 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12691 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12692
12693 switch (state) {
12694 case pci_channel_io_normal:
12695 /* Non-fatal error, prepare for recovery */
12696 lpfc_sli4_prep_dev_for_recover(phba);
12697 return PCI_ERS_RESULT_CAN_RECOVER;
12698 case pci_channel_io_frozen:
12699 /* Fatal error, prepare for slot reset */
12700 lpfc_sli4_prep_dev_for_reset(phba);
12701 return PCI_ERS_RESULT_NEED_RESET;
12702 case pci_channel_io_perm_failure:
12703 /* Permanent failure, prepare for device down */
12704 lpfc_sli4_prep_dev_for_perm_failure(phba);
12705 return PCI_ERS_RESULT_DISCONNECT;
12706 default:
12707 /* Unknown state, prepare and request slot reset */
12708 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12709 "2825 Unknown PCI error state: x%x\n", state);
12710 lpfc_sli4_prep_dev_for_reset(phba);
12711 return PCI_ERS_RESULT_NEED_RESET;
12712 }
8d63f375
LV
12713}
12714
12715/**
da0436e9 12716 * lpfc_io_slot_reset_s4 - Method for restart PCI SLI-4 device from scratch
e59058c4
JS
12717 * @pdev: pointer to PCI device.
12718 *
da0436e9
JS
12719 * This routine is called from the PCI subsystem for error handling to device
12720 * with SLI-4 interface spec. It is called after PCI bus has been reset to
12721 * restart the PCI card from scratch, as if from a cold-boot. During the
12722 * PCI subsystem error recovery, after the driver returns
3772a991 12723 * PCI_ERS_RESULT_NEED_RESET, the PCI subsystem will perform proper error
da0436e9
JS
12724 * recovery and then call this routine before calling the .resume method to
12725 * recover the device. This function will initialize the HBA device, enable
12726 * the interrupt, but it will just put the HBA to offline state without
12727 * passing any I/O traffic.
8d63f375 12728 *
e59058c4 12729 * Return codes
3772a991
JS
12730 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
12731 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
8d63f375 12732 */
3772a991 12733static pci_ers_result_t
da0436e9 12734lpfc_io_slot_reset_s4(struct pci_dev *pdev)
8d63f375 12735{
75baf696
JS
12736 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12737 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12738 struct lpfc_sli *psli = &phba->sli;
12739 uint32_t intr_mode;
12740
12741 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
12742 if (pci_enable_device_mem(pdev)) {
12743 printk(KERN_ERR "lpfc: Cannot re-enable "
12744 "PCI device after reset.\n");
12745 return PCI_ERS_RESULT_DISCONNECT;
12746 }
12747
12748 pci_restore_state(pdev);
0a96e975
JS
12749
12750 /*
12751 * As the new kernel behavior of pci_restore_state() API call clears
12752 * device saved_state flag, need to save the restored state again.
12753 */
12754 pci_save_state(pdev);
12755
75baf696
JS
12756 if (pdev->is_busmaster)
12757 pci_set_master(pdev);
12758
12759 spin_lock_irq(&phba->hbalock);
12760 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
12761 spin_unlock_irq(&phba->hbalock);
12762
12763 /* Configure and enable interrupt */
12764 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
12765 if (intr_mode == LPFC_INTR_ERROR) {
12766 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12767 "2824 Cannot re-enable interrupt after "
12768 "slot reset.\n");
12769 return PCI_ERS_RESULT_DISCONNECT;
12770 } else
12771 phba->intr_mode = intr_mode;
12772
12773 /* Log the current active interrupt mode */
12774 lpfc_log_intr_mode(phba, phba->intr_mode);
12775
8d63f375
LV
12776 return PCI_ERS_RESULT_RECOVERED;
12777}
12778
12779/**
da0436e9 12780 * lpfc_io_resume_s4 - Method for resuming PCI I/O operation to SLI-4 device
e59058c4 12781 * @pdev: pointer to PCI device
8d63f375 12782 *
3772a991 12783 * This routine is called from the PCI subsystem for error handling to device
da0436e9 12784 * with SLI-4 interface spec. It is called when kernel error recovery tells
3772a991
JS
12785 * the lpfc driver that it is ok to resume normal PCI operation after PCI bus
12786 * error recovery. After this call, traffic can start to flow from this device
12787 * again.
da0436e9 12788 **/
3772a991 12789static void
da0436e9 12790lpfc_io_resume_s4(struct pci_dev *pdev)
8d63f375 12791{
75baf696
JS
12792 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12793 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12794
12795 /*
12796 * In case of slot reset, as function reset is performed through
12797 * mailbox command which needs DMA to be enabled, this operation
12798 * has to be moved to the io resume phase. Taking device offline
12799 * will perform the necessary cleanup.
12800 */
12801 if (!(phba->sli.sli_flag & LPFC_SLI_ACTIVE)) {
12802 /* Perform device reset */
618a5230 12803 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
75baf696
JS
12804 lpfc_offline(phba);
12805 lpfc_sli_brdrestart(phba);
12806 /* Bring the device back online */
12807 lpfc_online(phba);
12808 }
8d63f375
LV
12809}
12810
3772a991
JS
12811/**
12812 * lpfc_pci_probe_one - lpfc PCI probe func to reg dev to PCI subsystem
12813 * @pdev: pointer to PCI device
12814 * @pid: pointer to PCI device identifier
12815 *
12816 * This routine is to be registered to the kernel's PCI subsystem. When an
12817 * Emulex HBA device is presented on PCI bus, the kernel PCI subsystem looks
12818 * at PCI device-specific information of the device and driver to see if the
12819 * driver state that it can support this kind of device. If the match is
12820 * successful, the driver core invokes this routine. This routine dispatches
12821 * the action to the proper SLI-3 or SLI-4 device probing routine, which will
12822 * do all the initialization that it needs to do to handle the HBA device
12823 * properly.
12824 *
12825 * Return code
12826 * 0 - driver can claim the device
12827 * negative value - driver can not claim the device
12828 **/
6f039790 12829static int
3772a991
JS
12830lpfc_pci_probe_one(struct pci_dev *pdev, const struct pci_device_id *pid)
12831{
12832 int rc;
8fa38513 12833 struct lpfc_sli_intf intf;
3772a991 12834
28baac74 12835 if (pci_read_config_dword(pdev, LPFC_SLI_INTF, &intf.word0))
3772a991
JS
12836 return -ENODEV;
12837
8fa38513 12838 if ((bf_get(lpfc_sli_intf_valid, &intf) == LPFC_SLI_INTF_VALID) &&
28baac74 12839 (bf_get(lpfc_sli_intf_slirev, &intf) == LPFC_SLI_INTF_REV_SLI4))
da0436e9 12840 rc = lpfc_pci_probe_one_s4(pdev, pid);
8fa38513 12841 else
3772a991 12842 rc = lpfc_pci_probe_one_s3(pdev, pid);
8fa38513 12843
3772a991
JS
12844 return rc;
12845}
12846
12847/**
12848 * lpfc_pci_remove_one - lpfc PCI func to unreg dev from PCI subsystem
12849 * @pdev: pointer to PCI device
12850 *
12851 * This routine is to be registered to the kernel's PCI subsystem. When an
12852 * Emulex HBA is removed from PCI bus, the driver core invokes this routine.
12853 * This routine dispatches the action to the proper SLI-3 or SLI-4 device
12854 * remove routine, which will perform all the necessary cleanup for the
12855 * device to be removed from the PCI subsystem properly.
12856 **/
6f039790 12857static void
3772a991
JS
12858lpfc_pci_remove_one(struct pci_dev *pdev)
12859{
12860 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12861 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12862
12863 switch (phba->pci_dev_grp) {
12864 case LPFC_PCI_DEV_LP:
12865 lpfc_pci_remove_one_s3(pdev);
12866 break;
da0436e9
JS
12867 case LPFC_PCI_DEV_OC:
12868 lpfc_pci_remove_one_s4(pdev);
12869 break;
3772a991
JS
12870 default:
12871 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12872 "1424 Invalid PCI device group: 0x%x\n",
12873 phba->pci_dev_grp);
12874 break;
12875 }
12876 return;
12877}
12878
12879/**
12880 * lpfc_pci_suspend_one - lpfc PCI func to suspend dev for power management
12881 * @pdev: pointer to PCI device
12882 * @msg: power management message
12883 *
12884 * This routine is to be registered to the kernel's PCI subsystem to support
12885 * system Power Management (PM). When PM invokes this method, it dispatches
12886 * the action to the proper SLI-3 or SLI-4 device suspend routine, which will
12887 * suspend the device.
12888 *
12889 * Return code
12890 * 0 - driver suspended the device
12891 * Error otherwise
12892 **/
12893static int
12894lpfc_pci_suspend_one(struct pci_dev *pdev, pm_message_t msg)
12895{
12896 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12897 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12898 int rc = -ENODEV;
12899
12900 switch (phba->pci_dev_grp) {
12901 case LPFC_PCI_DEV_LP:
12902 rc = lpfc_pci_suspend_one_s3(pdev, msg);
12903 break;
da0436e9
JS
12904 case LPFC_PCI_DEV_OC:
12905 rc = lpfc_pci_suspend_one_s4(pdev, msg);
12906 break;
3772a991
JS
12907 default:
12908 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12909 "1425 Invalid PCI device group: 0x%x\n",
12910 phba->pci_dev_grp);
12911 break;
12912 }
12913 return rc;
12914}
12915
12916/**
12917 * lpfc_pci_resume_one - lpfc PCI func to resume dev for power management
12918 * @pdev: pointer to PCI device
12919 *
12920 * This routine is to be registered to the kernel's PCI subsystem to support
12921 * system Power Management (PM). When PM invokes this method, it dispatches
12922 * the action to the proper SLI-3 or SLI-4 device resume routine, which will
12923 * resume the device.
12924 *
12925 * Return code
12926 * 0 - driver suspended the device
12927 * Error otherwise
12928 **/
12929static int
12930lpfc_pci_resume_one(struct pci_dev *pdev)
12931{
12932 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12933 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12934 int rc = -ENODEV;
12935
12936 switch (phba->pci_dev_grp) {
12937 case LPFC_PCI_DEV_LP:
12938 rc = lpfc_pci_resume_one_s3(pdev);
12939 break;
da0436e9
JS
12940 case LPFC_PCI_DEV_OC:
12941 rc = lpfc_pci_resume_one_s4(pdev);
12942 break;
3772a991
JS
12943 default:
12944 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12945 "1426 Invalid PCI device group: 0x%x\n",
12946 phba->pci_dev_grp);
12947 break;
12948 }
12949 return rc;
12950}
12951
12952/**
12953 * lpfc_io_error_detected - lpfc method for handling PCI I/O error
12954 * @pdev: pointer to PCI device.
12955 * @state: the current PCI connection state.
12956 *
12957 * This routine is registered to the PCI subsystem for error handling. This
12958 * function is called by the PCI subsystem after a PCI bus error affecting
12959 * this device has been detected. When this routine is invoked, it dispatches
12960 * the action to the proper SLI-3 or SLI-4 device error detected handling
12961 * routine, which will perform the proper error detected operation.
12962 *
12963 * Return codes
12964 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
12965 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
12966 **/
12967static pci_ers_result_t
12968lpfc_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
12969{
12970 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12971 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12972 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
12973
12974 switch (phba->pci_dev_grp) {
12975 case LPFC_PCI_DEV_LP:
12976 rc = lpfc_io_error_detected_s3(pdev, state);
12977 break;
da0436e9
JS
12978 case LPFC_PCI_DEV_OC:
12979 rc = lpfc_io_error_detected_s4(pdev, state);
12980 break;
3772a991
JS
12981 default:
12982 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12983 "1427 Invalid PCI device group: 0x%x\n",
12984 phba->pci_dev_grp);
12985 break;
12986 }
12987 return rc;
12988}
12989
12990/**
12991 * lpfc_io_slot_reset - lpfc method for restart PCI dev from scratch
12992 * @pdev: pointer to PCI device.
12993 *
12994 * This routine is registered to the PCI subsystem for error handling. This
12995 * function is called after PCI bus has been reset to restart the PCI card
12996 * from scratch, as if from a cold-boot. When this routine is invoked, it
12997 * dispatches the action to the proper SLI-3 or SLI-4 device reset handling
12998 * routine, which will perform the proper device reset.
12999 *
13000 * Return codes
13001 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
13002 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
13003 **/
13004static pci_ers_result_t
13005lpfc_io_slot_reset(struct pci_dev *pdev)
13006{
13007 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13008 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13009 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
13010
13011 switch (phba->pci_dev_grp) {
13012 case LPFC_PCI_DEV_LP:
13013 rc = lpfc_io_slot_reset_s3(pdev);
13014 break;
da0436e9
JS
13015 case LPFC_PCI_DEV_OC:
13016 rc = lpfc_io_slot_reset_s4(pdev);
13017 break;
3772a991
JS
13018 default:
13019 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13020 "1428 Invalid PCI device group: 0x%x\n",
13021 phba->pci_dev_grp);
13022 break;
13023 }
13024 return rc;
13025}
13026
13027/**
13028 * lpfc_io_resume - lpfc method for resuming PCI I/O operation
13029 * @pdev: pointer to PCI device
13030 *
13031 * This routine is registered to the PCI subsystem for error handling. It
13032 * is called when kernel error recovery tells the lpfc driver that it is
13033 * OK to resume normal PCI operation after PCI bus error recovery. When
13034 * this routine is invoked, it dispatches the action to the proper SLI-3
13035 * or SLI-4 device io_resume routine, which will resume the device operation.
13036 **/
13037static void
13038lpfc_io_resume(struct pci_dev *pdev)
13039{
13040 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13041 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13042
13043 switch (phba->pci_dev_grp) {
13044 case LPFC_PCI_DEV_LP:
13045 lpfc_io_resume_s3(pdev);
13046 break;
da0436e9
JS
13047 case LPFC_PCI_DEV_OC:
13048 lpfc_io_resume_s4(pdev);
13049 break;
3772a991
JS
13050 default:
13051 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13052 "1429 Invalid PCI device group: 0x%x\n",
13053 phba->pci_dev_grp);
13054 break;
13055 }
13056 return;
13057}
13058
1ba981fd
JS
13059/**
13060 * lpfc_sli4_oas_verify - Verify OAS is supported by this adapter
13061 * @phba: pointer to lpfc hba data structure.
13062 *
13063 * This routine checks to see if OAS is supported for this adapter. If
13064 * supported, the configure Flash Optimized Fabric flag is set. Otherwise,
13065 * the enable oas flag is cleared and the pool created for OAS device data
13066 * is destroyed.
13067 *
13068 **/
13069void
13070lpfc_sli4_oas_verify(struct lpfc_hba *phba)
13071{
13072
13073 if (!phba->cfg_EnableXLane)
13074 return;
13075
13076 if (phba->sli4_hba.pc_sli4_params.oas_supported) {
13077 phba->cfg_fof = 1;
13078 } else {
f38fa0bb 13079 phba->cfg_fof = 0;
1ba981fd
JS
13080 if (phba->device_data_mem_pool)
13081 mempool_destroy(phba->device_data_mem_pool);
13082 phba->device_data_mem_pool = NULL;
13083 }
13084
13085 return;
13086}
13087
d2cc9bcd
JS
13088/**
13089 * lpfc_sli4_ras_init - Verify RAS-FW log is supported by this adapter
13090 * @phba: pointer to lpfc hba data structure.
13091 *
13092 * This routine checks to see if RAS is supported by the adapter. Check the
13093 * function through which RAS support enablement is to be done.
13094 **/
13095void
13096lpfc_sli4_ras_init(struct lpfc_hba *phba)
13097{
13098 switch (phba->pcidev->device) {
13099 case PCI_DEVICE_ID_LANCER_G6_FC:
13100 case PCI_DEVICE_ID_LANCER_G7_FC:
13101 phba->ras_fwlog.ras_hwsupport = true;
cb34990b
JS
13102 if (phba->cfg_ras_fwlog_func == PCI_FUNC(phba->pcidev->devfn) &&
13103 phba->cfg_ras_fwlog_buffsize)
d2cc9bcd
JS
13104 phba->ras_fwlog.ras_enabled = true;
13105 else
13106 phba->ras_fwlog.ras_enabled = false;
13107 break;
13108 default:
13109 phba->ras_fwlog.ras_hwsupport = false;
13110 }
13111}
13112
1ba981fd 13113
dea3101e 13114MODULE_DEVICE_TABLE(pci, lpfc_id_table);
13115
a55b2d21 13116static const struct pci_error_handlers lpfc_err_handler = {
8d63f375
LV
13117 .error_detected = lpfc_io_error_detected,
13118 .slot_reset = lpfc_io_slot_reset,
13119 .resume = lpfc_io_resume,
13120};
13121
dea3101e 13122static struct pci_driver lpfc_driver = {
13123 .name = LPFC_DRIVER_NAME,
13124 .id_table = lpfc_id_table,
13125 .probe = lpfc_pci_probe_one,
6f039790 13126 .remove = lpfc_pci_remove_one,
85e8a239 13127 .shutdown = lpfc_pci_remove_one,
3a55b532 13128 .suspend = lpfc_pci_suspend_one,
3772a991 13129 .resume = lpfc_pci_resume_one,
2e0fef85 13130 .err_handler = &lpfc_err_handler,
dea3101e 13131};
13132
3ef6d24c 13133static const struct file_operations lpfc_mgmt_fop = {
858feacd 13134 .owner = THIS_MODULE,
3ef6d24c
JS
13135};
13136
13137static struct miscdevice lpfc_mgmt_dev = {
13138 .minor = MISC_DYNAMIC_MINOR,
13139 .name = "lpfcmgmt",
13140 .fops = &lpfc_mgmt_fop,
13141};
13142
e59058c4 13143/**
3621a710 13144 * lpfc_init - lpfc module initialization routine
e59058c4
JS
13145 *
13146 * This routine is to be invoked when the lpfc module is loaded into the
13147 * kernel. The special kernel macro module_init() is used to indicate the
13148 * role of this routine to the kernel as lpfc module entry point.
13149 *
13150 * Return codes
13151 * 0 - successful
13152 * -ENOMEM - FC attach transport failed
13153 * all others - failed
13154 */
dea3101e 13155static int __init
13156lpfc_init(void)
13157{
13158 int error = 0;
13159
13160 printk(LPFC_MODULE_DESC "\n");
c44ce173 13161 printk(LPFC_COPYRIGHT "\n");
dea3101e 13162
3ef6d24c
JS
13163 error = misc_register(&lpfc_mgmt_dev);
13164 if (error)
13165 printk(KERN_ERR "Could not register lpfcmgmt device, "
13166 "misc_register returned with status %d", error);
13167
458c083e
JS
13168 lpfc_transport_functions.vport_create = lpfc_vport_create;
13169 lpfc_transport_functions.vport_delete = lpfc_vport_delete;
dea3101e 13170 lpfc_transport_template =
13171 fc_attach_transport(&lpfc_transport_functions);
7ee5d43e 13172 if (lpfc_transport_template == NULL)
dea3101e 13173 return -ENOMEM;
458c083e
JS
13174 lpfc_vport_transport_template =
13175 fc_attach_transport(&lpfc_vport_transport_functions);
13176 if (lpfc_vport_transport_template == NULL) {
13177 fc_release_transport(lpfc_transport_template);
13178 return -ENOMEM;
7ee5d43e 13179 }
5fd11085 13180 lpfc_nvme_cmd_template();
bd3061ba 13181 lpfc_nvmet_cmd_template();
7bb03bbf
JS
13182
13183 /* Initialize in case vector mapping is needed */
2ea259ee 13184 lpfc_present_cpu = num_present_cpus();
7bb03bbf 13185
dea3101e 13186 error = pci_register_driver(&lpfc_driver);
92d7f7b0 13187 if (error) {
dea3101e 13188 fc_release_transport(lpfc_transport_template);
458c083e 13189 fc_release_transport(lpfc_vport_transport_template);
92d7f7b0 13190 }
dea3101e 13191
13192 return error;
13193}
13194
e59058c4 13195/**
3621a710 13196 * lpfc_exit - lpfc module removal routine
e59058c4
JS
13197 *
13198 * This routine is invoked when the lpfc module is removed from the kernel.
13199 * The special kernel macro module_exit() is used to indicate the role of
13200 * this routine to the kernel as lpfc module exit point.
13201 */
dea3101e 13202static void __exit
13203lpfc_exit(void)
13204{
3ef6d24c 13205 misc_deregister(&lpfc_mgmt_dev);
dea3101e 13206 pci_unregister_driver(&lpfc_driver);
13207 fc_release_transport(lpfc_transport_template);
458c083e 13208 fc_release_transport(lpfc_vport_transport_template);
81301a9b 13209 if (_dump_buf_data) {
6a9c52cf
JS
13210 printk(KERN_ERR "9062 BLKGRD: freeing %lu pages for "
13211 "_dump_buf_data at 0x%p\n",
81301a9b
JS
13212 (1L << _dump_buf_data_order), _dump_buf_data);
13213 free_pages((unsigned long)_dump_buf_data, _dump_buf_data_order);
13214 }
13215
13216 if (_dump_buf_dif) {
6a9c52cf
JS
13217 printk(KERN_ERR "9049 BLKGRD: freeing %lu pages for "
13218 "_dump_buf_dif at 0x%p\n",
81301a9b
JS
13219 (1L << _dump_buf_dif_order), _dump_buf_dif);
13220 free_pages((unsigned long)_dump_buf_dif, _dump_buf_dif_order);
13221 }
7973967f 13222 idr_destroy(&lpfc_hba_index);
dea3101e 13223}
13224
13225module_init(lpfc_init);
13226module_exit(lpfc_exit);
13227MODULE_LICENSE("GPL");
13228MODULE_DESCRIPTION(LPFC_MODULE_DESC);
d080abe0 13229MODULE_AUTHOR("Broadcom");
dea3101e 13230MODULE_VERSION("0:" LPFC_DRIVER_VERSION);