scsi: lpfc: Fix field overload in lpfc_iocbq data structure
[linux-2.6-block.git] / drivers / scsi / lpfc / lpfc_init.c
CommitLineData
dea3101e 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
f45775bf 4 * Copyright (C) 2017-2022 Broadcom. All Rights Reserved. The term *
3e21d1cb 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
50611577 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
c44ce173 7 * EMULEX and SLI are trademarks of Emulex. *
d080abe0 8 * www.broadcom.com *
c44ce173 9 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
dea3101e 10 * *
11 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC
12 * modify it under the terms of version 2 of the GNU General *
13 * Public License as published by the Free Software Foundation. *
14 * This program is distributed in the hope that it will be useful. *
15 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
16 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
18 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
19 * TO BE LEGALLY INVALID. See the GNU General Public License for *
20 * more details, a copy of which can be found in the file COPYING *
21 * included with this package. *
dea3101e 22 *******************************************************************/
23
dea3101e 24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/idr.h>
28#include <linux/interrupt.h>
acf3368f 29#include <linux/module.h>
dea3101e 30#include <linux/kthread.h>
31#include <linux/pci.h>
32#include <linux/spinlock.h>
92d7f7b0 33#include <linux/ctype.h>
0d878419 34#include <linux/aer.h>
5a0e3ad6 35#include <linux/slab.h>
52d52440 36#include <linux/firmware.h>
3ef6d24c 37#include <linux/miscdevice.h>
7bb03bbf 38#include <linux/percpu.h>
895427bd 39#include <linux/msi.h>
6a828b0f 40#include <linux/irq.h>
286871a6 41#include <linux/bitops.h>
31f06d2e 42#include <linux/crash_dump.h>
dcaa2136 43#include <linux/cpu.h>
93a4d6f4 44#include <linux/cpuhotplug.h>
dea3101e 45
91886523 46#include <scsi/scsi.h>
dea3101e 47#include <scsi/scsi_device.h>
48#include <scsi/scsi_host.h>
49#include <scsi/scsi_transport_fc.h>
86c67379
JS
50#include <scsi/scsi_tcq.h>
51#include <scsi/fc/fc_fs.h>
52
da0436e9 53#include "lpfc_hw4.h"
dea3101e 54#include "lpfc_hw.h"
55#include "lpfc_sli.h"
da0436e9 56#include "lpfc_sli4.h"
ea2151b4 57#include "lpfc_nl.h"
dea3101e 58#include "lpfc_disc.h"
dea3101e 59#include "lpfc.h"
895427bd
JS
60#include "lpfc_scsi.h"
61#include "lpfc_nvme.h"
dea3101e 62#include "lpfc_logmsg.h"
63#include "lpfc_crtn.h"
92d7f7b0 64#include "lpfc_vport.h"
dea3101e 65#include "lpfc_version.h"
12f44457 66#include "lpfc_ids.h"
dea3101e 67
93a4d6f4 68static enum cpuhp_state lpfc_cpuhp_state;
7bb03bbf 69/* Used when mapping IRQ vectors in a driver centric manner */
d7b761b0 70static uint32_t lpfc_present_cpu;
a5b141a8 71static bool lpfc_pldv_detect;
7bb03bbf 72
93a4d6f4
JS
73static void __lpfc_cpuhp_remove(struct lpfc_hba *phba);
74static void lpfc_cpuhp_remove(struct lpfc_hba *phba);
75static void lpfc_cpuhp_add(struct lpfc_hba *phba);
dea3101e 76static void lpfc_get_hba_model_desc(struct lpfc_hba *, uint8_t *, uint8_t *);
77static int lpfc_post_rcv_buf(struct lpfc_hba *);
5350d872 78static int lpfc_sli4_queue_verify(struct lpfc_hba *);
da0436e9
JS
79static int lpfc_create_bootstrap_mbox(struct lpfc_hba *);
80static int lpfc_setup_endian_order(struct lpfc_hba *);
da0436e9 81static void lpfc_destroy_bootstrap_mbox(struct lpfc_hba *);
8a9d2e80 82static void lpfc_free_els_sgl_list(struct lpfc_hba *);
f358dd0c 83static void lpfc_free_nvmet_sgl_list(struct lpfc_hba *);
8a9d2e80 84static void lpfc_init_sgl_list(struct lpfc_hba *);
da0436e9
JS
85static int lpfc_init_active_sgl_array(struct lpfc_hba *);
86static void lpfc_free_active_sgl(struct lpfc_hba *);
87static int lpfc_hba_down_post_s3(struct lpfc_hba *phba);
88static int lpfc_hba_down_post_s4(struct lpfc_hba *phba);
89static int lpfc_sli4_cq_event_pool_create(struct lpfc_hba *);
90static void lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *);
91static void lpfc_sli4_cq_event_release_all(struct lpfc_hba *);
618a5230
JS
92static void lpfc_sli4_disable_intr(struct lpfc_hba *);
93static uint32_t lpfc_sli4_enable_intr(struct lpfc_hba *, uint32_t);
1ba981fd 94static void lpfc_sli4_oas_verify(struct lpfc_hba *phba);
6a828b0f 95static uint16_t lpfc_find_cpu_handle(struct lpfc_hba *, uint16_t, int);
aa6ff309 96static void lpfc_setup_bg(struct lpfc_hba *, struct Scsi_Host *);
02243836 97static int lpfc_sli4_cgn_parm_chg_evt(struct lpfc_hba *);
a4691038 98static void lpfc_sli4_prep_dev_for_reset(struct lpfc_hba *phba);
dea3101e 99
100static struct scsi_transport_template *lpfc_transport_template = NULL;
92d7f7b0 101static struct scsi_transport_template *lpfc_vport_transport_template = NULL;
dea3101e 102static DEFINE_IDR(lpfc_hba_index);
f358dd0c 103#define LPFC_NVMET_BUF_POST 254
5e633302 104static int lpfc_vmid_res_alloc(struct lpfc_hba *phba, struct lpfc_vport *vport);
dea3101e 105
e59058c4 106/**
3621a710 107 * lpfc_config_port_prep - Perform lpfc initialization prior to config port
e59058c4
JS
108 * @phba: pointer to lpfc hba data structure.
109 *
110 * This routine will do LPFC initialization prior to issuing the CONFIG_PORT
111 * mailbox command. It retrieves the revision information from the HBA and
112 * collects the Vital Product Data (VPD) about the HBA for preparing the
113 * configuration of the HBA.
114 *
115 * Return codes:
116 * 0 - success.
117 * -ERESTART - requests the SLI layer to reset the HBA and try again.
118 * Any other value - indicates an error.
119 **/
dea3101e 120int
2e0fef85 121lpfc_config_port_prep(struct lpfc_hba *phba)
dea3101e 122{
123 lpfc_vpd_t *vp = &phba->vpd;
124 int i = 0, rc;
125 LPFC_MBOXQ_t *pmb;
126 MAILBOX_t *mb;
127 char *lpfc_vpd_data = NULL;
128 uint16_t offset = 0;
129 static char licensed[56] =
130 "key unlock for use with gnu public licensed code only\0";
65a29c16 131 static int init_key = 1;
dea3101e 132
133 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
134 if (!pmb) {
2e0fef85 135 phba->link_state = LPFC_HBA_ERROR;
dea3101e 136 return -ENOMEM;
137 }
138
04c68496 139 mb = &pmb->u.mb;
2e0fef85 140 phba->link_state = LPFC_INIT_MBX_CMDS;
dea3101e 141
142 if (lpfc_is_LC_HBA(phba->pcidev->device)) {
65a29c16
JS
143 if (init_key) {
144 uint32_t *ptext = (uint32_t *) licensed;
dea3101e 145
65a29c16
JS
146 for (i = 0; i < 56; i += sizeof (uint32_t), ptext++)
147 *ptext = cpu_to_be32(*ptext);
148 init_key = 0;
149 }
dea3101e 150
151 lpfc_read_nv(phba, pmb);
152 memset((char*)mb->un.varRDnvp.rsvd3, 0,
153 sizeof (mb->un.varRDnvp.rsvd3));
154 memcpy((char*)mb->un.varRDnvp.rsvd3, licensed,
155 sizeof (licensed));
156
157 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
158
159 if (rc != MBX_SUCCESS) {
372c187b 160 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 161 "0324 Config Port initialization "
dea3101e 162 "error, mbxCmd x%x READ_NVPARM, "
163 "mbxStatus x%x\n",
dea3101e 164 mb->mbxCommand, mb->mbxStatus);
165 mempool_free(pmb, phba->mbox_mem_pool);
166 return -ERESTART;
167 }
168 memcpy(phba->wwnn, (char *)mb->un.varRDnvp.nodename,
2e0fef85
JS
169 sizeof(phba->wwnn));
170 memcpy(phba->wwpn, (char *)mb->un.varRDnvp.portname,
171 sizeof(phba->wwpn));
dea3101e 172 }
173
dfb75133
MW
174 /*
175 * Clear all option bits except LPFC_SLI3_BG_ENABLED,
176 * which was already set in lpfc_get_cfgparam()
177 */
178 phba->sli3_options &= (uint32_t)LPFC_SLI3_BG_ENABLED;
92d7f7b0 179
dea3101e 180 /* Setup and issue mailbox READ REV command */
181 lpfc_read_rev(phba, pmb);
182 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
183 if (rc != MBX_SUCCESS) {
372c187b 184 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 185 "0439 Adapter failed to init, mbxCmd x%x "
dea3101e 186 "READ_REV, mbxStatus x%x\n",
dea3101e 187 mb->mbxCommand, mb->mbxStatus);
188 mempool_free( pmb, phba->mbox_mem_pool);
189 return -ERESTART;
190 }
191
92d7f7b0 192
1de933f3
JSEC
193 /*
194 * The value of rr must be 1 since the driver set the cv field to 1.
195 * This setting requires the FW to set all revision fields.
dea3101e 196 */
1de933f3 197 if (mb->un.varRdRev.rr == 0) {
dea3101e 198 vp->rev.rBit = 0;
372c187b 199 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011
JS
200 "0440 Adapter failed to init, READ_REV has "
201 "missing revision information.\n");
dea3101e 202 mempool_free(pmb, phba->mbox_mem_pool);
203 return -ERESTART;
dea3101e 204 }
205
495a714c
JS
206 if (phba->sli_rev == 3 && !mb->un.varRdRev.v3rsp) {
207 mempool_free(pmb, phba->mbox_mem_pool);
ed957684 208 return -EINVAL;
495a714c 209 }
ed957684 210
dea3101e 211 /* Save information as VPD data */
1de933f3 212 vp->rev.rBit = 1;
92d7f7b0 213 memcpy(&vp->sli3Feat, &mb->un.varRdRev.sli3Feat, sizeof(uint32_t));
1de933f3
JSEC
214 vp->rev.sli1FwRev = mb->un.varRdRev.sli1FwRev;
215 memcpy(vp->rev.sli1FwName, (char*) mb->un.varRdRev.sli1FwName, 16);
216 vp->rev.sli2FwRev = mb->un.varRdRev.sli2FwRev;
217 memcpy(vp->rev.sli2FwName, (char *) mb->un.varRdRev.sli2FwName, 16);
dea3101e 218 vp->rev.biuRev = mb->un.varRdRev.biuRev;
219 vp->rev.smRev = mb->un.varRdRev.smRev;
220 vp->rev.smFwRev = mb->un.varRdRev.un.smFwRev;
221 vp->rev.endecRev = mb->un.varRdRev.endecRev;
222 vp->rev.fcphHigh = mb->un.varRdRev.fcphHigh;
223 vp->rev.fcphLow = mb->un.varRdRev.fcphLow;
224 vp->rev.feaLevelHigh = mb->un.varRdRev.feaLevelHigh;
225 vp->rev.feaLevelLow = mb->un.varRdRev.feaLevelLow;
226 vp->rev.postKernRev = mb->un.varRdRev.postKernRev;
227 vp->rev.opFwRev = mb->un.varRdRev.opFwRev;
228
92d7f7b0
JS
229 /* If the sli feature level is less then 9, we must
230 * tear down all RPIs and VPIs on link down if NPIV
231 * is enabled.
232 */
233 if (vp->rev.feaLevelHigh < 9)
234 phba->sli3_options |= LPFC_SLI3_VPORT_TEARDOWN;
235
dea3101e 236 if (lpfc_is_LC_HBA(phba->pcidev->device))
237 memcpy(phba->RandomData, (char *)&mb->un.varWords[24],
238 sizeof (phba->RandomData));
239
dea3101e 240 /* Get adapter VPD information */
dea3101e 241 lpfc_vpd_data = kmalloc(DMP_VPD_SIZE, GFP_KERNEL);
242 if (!lpfc_vpd_data)
d7c255b2 243 goto out_free_mbox;
dea3101e 244 do {
a0c87cbd 245 lpfc_dump_mem(phba, pmb, offset, DMP_REGION_VPD);
dea3101e 246 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
247
248 if (rc != MBX_SUCCESS) {
249 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011 250 "0441 VPD not present on adapter, "
dea3101e 251 "mbxCmd x%x DUMP VPD, mbxStatus x%x\n",
dea3101e 252 mb->mbxCommand, mb->mbxStatus);
74b72a59 253 mb->un.varDmp.word_cnt = 0;
dea3101e 254 }
04c68496
JS
255 /* dump mem may return a zero when finished or we got a
256 * mailbox error, either way we are done.
257 */
258 if (mb->un.varDmp.word_cnt == 0)
259 break;
d91e3abb 260
e4ec1022
JS
261 if (mb->un.varDmp.word_cnt > DMP_VPD_SIZE - offset)
262 mb->un.varDmp.word_cnt = DMP_VPD_SIZE - offset;
d7c255b2 263 lpfc_sli_pcimem_bcopy(((uint8_t *)mb) + DMP_RSP_OFFSET,
e4ec1022
JS
264 lpfc_vpd_data + offset,
265 mb->un.varDmp.word_cnt);
266 offset += mb->un.varDmp.word_cnt;
267 } while (mb->un.varDmp.word_cnt && offset < DMP_VPD_SIZE);
d91e3abb 268
74b72a59 269 lpfc_parse_vpd(phba, lpfc_vpd_data, offset);
dea3101e 270
271 kfree(lpfc_vpd_data);
dea3101e 272out_free_mbox:
273 mempool_free(pmb, phba->mbox_mem_pool);
274 return 0;
275}
276
e59058c4 277/**
3621a710 278 * lpfc_config_async_cmpl - Completion handler for config async event mbox cmd
e59058c4
JS
279 * @phba: pointer to lpfc hba data structure.
280 * @pmboxq: pointer to the driver internal queue element for mailbox command.
281 *
282 * This is the completion handler for driver's configuring asynchronous event
283 * mailbox command to the device. If the mailbox command returns successfully,
284 * it will set internal async event support flag to 1; otherwise, it will
285 * set internal async event support flag to 0.
286 **/
57127f15
JS
287static void
288lpfc_config_async_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
289{
04c68496 290 if (pmboxq->u.mb.mbxStatus == MBX_SUCCESS)
57127f15
JS
291 phba->temp_sensor_support = 1;
292 else
293 phba->temp_sensor_support = 0;
294 mempool_free(pmboxq, phba->mbox_mem_pool);
295 return;
296}
297
97207482 298/**
3621a710 299 * lpfc_dump_wakeup_param_cmpl - dump memory mailbox command completion handler
97207482
JS
300 * @phba: pointer to lpfc hba data structure.
301 * @pmboxq: pointer to the driver internal queue element for mailbox command.
302 *
303 * This is the completion handler for dump mailbox command for getting
304 * wake up parameters. When this command complete, the response contain
305 * Option rom version of the HBA. This function translate the version number
306 * into a human readable string and store it in OptionROMVersion.
307 **/
308static void
309lpfc_dump_wakeup_param_cmpl(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmboxq)
310{
311 struct prog_id *prg;
312 uint32_t prog_id_word;
313 char dist = ' ';
314 /* character array used for decoding dist type. */
315 char dist_char[] = "nabx";
316
04c68496 317 if (pmboxq->u.mb.mbxStatus != MBX_SUCCESS) {
9f1e1b50 318 mempool_free(pmboxq, phba->mbox_mem_pool);
97207482 319 return;
9f1e1b50 320 }
97207482
JS
321
322 prg = (struct prog_id *) &prog_id_word;
323
324 /* word 7 contain option rom version */
04c68496 325 prog_id_word = pmboxq->u.mb.un.varWords[7];
97207482
JS
326
327 /* Decode the Option rom version word to a readable string */
328 if (prg->dist < 4)
329 dist = dist_char[prg->dist];
330
331 if ((prg->dist == 3) && (prg->num == 0))
a2fc4aef 332 snprintf(phba->OptionROMVersion, 32, "%d.%d%d",
97207482
JS
333 prg->ver, prg->rev, prg->lev);
334 else
a2fc4aef 335 snprintf(phba->OptionROMVersion, 32, "%d.%d%d%c%d",
97207482
JS
336 prg->ver, prg->rev, prg->lev,
337 dist, prg->num);
9f1e1b50 338 mempool_free(pmboxq, phba->mbox_mem_pool);
97207482
JS
339 return;
340}
341
0558056c
JS
342/**
343 * lpfc_update_vport_wwn - Updates the fc_nodename, fc_portname,
0558056c
JS
344 * @vport: pointer to lpfc vport data structure.
345 *
346 *
347 * Return codes
348 * None.
349 **/
350void
351lpfc_update_vport_wwn(struct lpfc_vport *vport)
352{
aeb3c817
JS
353 uint8_t vvvl = vport->fc_sparam.cmn.valid_vendor_ver_level;
354 u32 *fawwpn_key = (u32 *)&vport->fc_sparam.un.vendorVersion[0];
355
0558056c
JS
356 /*
357 * If the name is empty or there exists a soft name
358 * then copy the service params name, otherwise use the fc name
359 */
2ea3a393 360 if (vport->fc_nodename.u.wwn[0] == 0)
0558056c
JS
361 memcpy(&vport->fc_nodename, &vport->fc_sparam.nodeName,
362 sizeof(struct lpfc_name));
363 else
364 memcpy(&vport->fc_sparam.nodeName, &vport->fc_nodename,
365 sizeof(struct lpfc_name));
366
aeb3c817
JS
367 /*
368 * If the port name has changed, then set the Param changes flag
369 * to unreg the login
370 */
371 if (vport->fc_portname.u.wwn[0] != 0 &&
372 memcmp(&vport->fc_portname, &vport->fc_sparam.portName,
373 sizeof(struct lpfc_name)))
374 vport->vport_flag |= FAWWPN_PARAM_CHG;
375
376 if (vport->fc_portname.u.wwn[0] == 0 ||
aeb3c817
JS
377 (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR) ||
378 vport->vport_flag & FAWWPN_SET) {
0558056c
JS
379 memcpy(&vport->fc_portname, &vport->fc_sparam.portName,
380 sizeof(struct lpfc_name));
aeb3c817
JS
381 vport->vport_flag &= ~FAWWPN_SET;
382 if (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR)
383 vport->vport_flag |= FAWWPN_SET;
384 }
0558056c
JS
385 else
386 memcpy(&vport->fc_sparam.portName, &vport->fc_portname,
387 sizeof(struct lpfc_name));
388}
389
e59058c4 390/**
3621a710 391 * lpfc_config_port_post - Perform lpfc initialization after config port
e59058c4
JS
392 * @phba: pointer to lpfc hba data structure.
393 *
394 * This routine will do LPFC initialization after the CONFIG_PORT mailbox
395 * command call. It performs all internal resource and state setups on the
396 * port: post IOCB buffers, enable appropriate host interrupt attentions,
397 * ELS ring timers, etc.
398 *
399 * Return codes
400 * 0 - success.
401 * Any other value - error.
402 **/
dea3101e 403int
2e0fef85 404lpfc_config_port_post(struct lpfc_hba *phba)
dea3101e 405{
2e0fef85 406 struct lpfc_vport *vport = phba->pport;
a257bf90 407 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
dea3101e 408 LPFC_MBOXQ_t *pmb;
409 MAILBOX_t *mb;
410 struct lpfc_dmabuf *mp;
411 struct lpfc_sli *psli = &phba->sli;
412 uint32_t status, timeout;
2e0fef85
JS
413 int i, j;
414 int rc;
dea3101e 415
7af67051
JS
416 spin_lock_irq(&phba->hbalock);
417 /*
418 * If the Config port completed correctly the HBA is not
419 * over heated any more.
420 */
421 if (phba->over_temp_state == HBA_OVER_TEMP)
422 phba->over_temp_state = HBA_NORMAL_TEMP;
423 spin_unlock_irq(&phba->hbalock);
424
dea3101e 425 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
426 if (!pmb) {
2e0fef85 427 phba->link_state = LPFC_HBA_ERROR;
dea3101e 428 return -ENOMEM;
429 }
04c68496 430 mb = &pmb->u.mb;
dea3101e 431
dea3101e 432 /* Get login parameters for NID. */
9f1177a3
JS
433 rc = lpfc_read_sparam(phba, pmb, 0);
434 if (rc) {
435 mempool_free(pmb, phba->mbox_mem_pool);
436 return -ENOMEM;
437 }
438
ed957684 439 pmb->vport = vport;
dea3101e 440 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
372c187b 441 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 442 "0448 Adapter failed init, mbxCmd x%x "
dea3101e 443 "READ_SPARM mbxStatus x%x\n",
dea3101e 444 mb->mbxCommand, mb->mbxStatus);
2e0fef85 445 phba->link_state = LPFC_HBA_ERROR;
3e1f0718 446 mp = (struct lpfc_dmabuf *)pmb->ctx_buf;
9f1177a3 447 mempool_free(pmb, phba->mbox_mem_pool);
dea3101e 448 lpfc_mbuf_free(phba, mp->virt, mp->phys);
449 kfree(mp);
450 return -EIO;
451 }
452
3e1f0718 453 mp = (struct lpfc_dmabuf *)pmb->ctx_buf;
dea3101e 454
2e0fef85 455 memcpy(&vport->fc_sparam, mp->virt, sizeof (struct serv_parm));
dea3101e 456 lpfc_mbuf_free(phba, mp->virt, mp->phys);
457 kfree(mp);
3e1f0718 458 pmb->ctx_buf = NULL;
0558056c 459 lpfc_update_vport_wwn(vport);
a257bf90
JS
460
461 /* Update the fc_host data structures with new wwn. */
462 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
463 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
21e9a0a5 464 fc_host_max_npiv_vports(shost) = phba->max_vpi;
a257bf90 465
dea3101e 466 /* If no serial number in VPD data, use low 6 bytes of WWNN */
467 /* This should be consolidated into parse_vpd ? - mr */
468 if (phba->SerialNumber[0] == 0) {
469 uint8_t *outptr;
470
2e0fef85 471 outptr = &vport->fc_nodename.u.s.IEEE[0];
dea3101e 472 for (i = 0; i < 12; i++) {
473 status = *outptr++;
474 j = ((status & 0xf0) >> 4);
475 if (j <= 9)
476 phba->SerialNumber[i] =
477 (char)((uint8_t) 0x30 + (uint8_t) j);
478 else
479 phba->SerialNumber[i] =
480 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
481 i++;
482 j = (status & 0xf);
483 if (j <= 9)
484 phba->SerialNumber[i] =
485 (char)((uint8_t) 0x30 + (uint8_t) j);
486 else
487 phba->SerialNumber[i] =
488 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
489 }
490 }
491
dea3101e 492 lpfc_read_config(phba, pmb);
ed957684 493 pmb->vport = vport;
dea3101e 494 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
372c187b 495 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 496 "0453 Adapter failed to init, mbxCmd x%x "
dea3101e 497 "READ_CONFIG, mbxStatus x%x\n",
dea3101e 498 mb->mbxCommand, mb->mbxStatus);
2e0fef85 499 phba->link_state = LPFC_HBA_ERROR;
dea3101e 500 mempool_free( pmb, phba->mbox_mem_pool);
501 return -EIO;
502 }
503
a0c87cbd
JS
504 /* Check if the port is disabled */
505 lpfc_sli_read_link_ste(phba);
506
dea3101e 507 /* Reset the DFT_HBA_Q_DEPTH to the max xri */
f6770e7d 508 if (phba->cfg_hba_queue_depth > mb->un.varRdConfig.max_xri) {
572709e2
JS
509 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
510 "3359 HBA queue depth changed from %d to %d\n",
f6770e7d
JS
511 phba->cfg_hba_queue_depth,
512 mb->un.varRdConfig.max_xri);
513 phba->cfg_hba_queue_depth = mb->un.varRdConfig.max_xri;
572709e2 514 }
dea3101e 515
516 phba->lmt = mb->un.varRdConfig.lmt;
74b72a59
JW
517
518 /* Get the default values for Model Name and Description */
519 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
520
2e0fef85 521 phba->link_state = LPFC_LINK_DOWN;
dea3101e 522
0b727fea 523 /* Only process IOCBs on ELS ring till hba_state is READY */
895427bd
JS
524 if (psli->sli3_ring[LPFC_EXTRA_RING].sli.sli3.cmdringaddr)
525 psli->sli3_ring[LPFC_EXTRA_RING].flag |= LPFC_STOP_IOCB_EVENT;
526 if (psli->sli3_ring[LPFC_FCP_RING].sli.sli3.cmdringaddr)
527 psli->sli3_ring[LPFC_FCP_RING].flag |= LPFC_STOP_IOCB_EVENT;
dea3101e 528
529 /* Post receive buffers for desired rings */
ed957684
JS
530 if (phba->sli_rev != 3)
531 lpfc_post_rcv_buf(phba);
dea3101e 532
9399627f
JS
533 /*
534 * Configure HBA MSI-X attention conditions to messages if MSI-X mode
535 */
536 if (phba->intr_type == MSIX) {
537 rc = lpfc_config_msi(phba, pmb);
538 if (rc) {
539 mempool_free(pmb, phba->mbox_mem_pool);
540 return -EIO;
541 }
542 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
543 if (rc != MBX_SUCCESS) {
372c187b 544 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
9399627f
JS
545 "0352 Config MSI mailbox command "
546 "failed, mbxCmd x%x, mbxStatus x%x\n",
04c68496
JS
547 pmb->u.mb.mbxCommand,
548 pmb->u.mb.mbxStatus);
9399627f
JS
549 mempool_free(pmb, phba->mbox_mem_pool);
550 return -EIO;
551 }
552 }
553
04c68496 554 spin_lock_irq(&phba->hbalock);
9399627f
JS
555 /* Initialize ERATT handling flag */
556 phba->hba_flag &= ~HBA_ERATT_HANDLED;
557
dea3101e 558 /* Enable appropriate host interrupts */
9940b97b
JS
559 if (lpfc_readl(phba->HCregaddr, &status)) {
560 spin_unlock_irq(&phba->hbalock);
561 return -EIO;
562 }
dea3101e 563 status |= HC_MBINT_ENA | HC_ERINT_ENA | HC_LAINT_ENA;
564 if (psli->num_rings > 0)
565 status |= HC_R0INT_ENA;
566 if (psli->num_rings > 1)
567 status |= HC_R1INT_ENA;
568 if (psli->num_rings > 2)
569 status |= HC_R2INT_ENA;
570 if (psli->num_rings > 3)
571 status |= HC_R3INT_ENA;
572
875fbdfe
JSEC
573 if ((phba->cfg_poll & ENABLE_FCP_RING_POLLING) &&
574 (phba->cfg_poll & DISABLE_FCP_RING_INT))
9399627f 575 status &= ~(HC_R0INT_ENA);
875fbdfe 576
dea3101e 577 writel(status, phba->HCregaddr);
578 readl(phba->HCregaddr); /* flush */
2e0fef85 579 spin_unlock_irq(&phba->hbalock);
dea3101e 580
9399627f
JS
581 /* Set up ring-0 (ELS) timer */
582 timeout = phba->fc_ratov * 2;
256ec0d0
JS
583 mod_timer(&vport->els_tmofunc,
584 jiffies + msecs_to_jiffies(1000 * timeout));
9399627f 585 /* Set up heart beat (HB) timer */
256ec0d0
JS
586 mod_timer(&phba->hb_tmofunc,
587 jiffies + msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
a22d73b6 588 phba->hba_flag &= ~(HBA_HBEAT_INP | HBA_HBEAT_TMO);
858c9f6c 589 phba->last_completion_time = jiffies;
9399627f 590 /* Set up error attention (ERATT) polling timer */
256ec0d0 591 mod_timer(&phba->eratt_poll,
65791f1f 592 jiffies + msecs_to_jiffies(1000 * phba->eratt_poll_interval));
dea3101e 593
a0c87cbd 594 if (phba->hba_flag & LINK_DISABLED) {
372c187b
DK
595 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
596 "2598 Adapter Link is disabled.\n");
a0c87cbd
JS
597 lpfc_down_link(phba, pmb);
598 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
599 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
600 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
372c187b
DK
601 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
602 "2599 Adapter failed to issue DOWN_LINK"
603 " mbox command rc 0x%x\n", rc);
a0c87cbd
JS
604
605 mempool_free(pmb, phba->mbox_mem_pool);
606 return -EIO;
607 }
e40a02c1 608 } else if (phba->cfg_suppress_link_up == LPFC_INITIALIZE_LINK) {
026abb87
JS
609 mempool_free(pmb, phba->mbox_mem_pool);
610 rc = phba->lpfc_hba_init_link(phba, MBX_NOWAIT);
611 if (rc)
612 return rc;
dea3101e 613 }
614 /* MBOX buffer will be freed in mbox compl */
57127f15 615 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9f1177a3
JS
616 if (!pmb) {
617 phba->link_state = LPFC_HBA_ERROR;
618 return -ENOMEM;
619 }
620
57127f15
JS
621 lpfc_config_async(phba, pmb, LPFC_ELS_RING);
622 pmb->mbox_cmpl = lpfc_config_async_cmpl;
623 pmb->vport = phba->pport;
624 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
dea3101e 625
57127f15 626 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
372c187b 627 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
57127f15 628 "0456 Adapter failed to issue "
e4e74273 629 "ASYNCEVT_ENABLE mbox status x%x\n",
57127f15
JS
630 rc);
631 mempool_free(pmb, phba->mbox_mem_pool);
632 }
97207482
JS
633
634 /* Get Option rom version */
635 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9f1177a3
JS
636 if (!pmb) {
637 phba->link_state = LPFC_HBA_ERROR;
638 return -ENOMEM;
639 }
640
97207482
JS
641 lpfc_dump_wakeup_param(phba, pmb);
642 pmb->mbox_cmpl = lpfc_dump_wakeup_param_cmpl;
643 pmb->vport = phba->pport;
644 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
645
646 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
372c187b
DK
647 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
648 "0435 Adapter failed "
e4e74273 649 "to get Option ROM version status x%x\n", rc);
97207482
JS
650 mempool_free(pmb, phba->mbox_mem_pool);
651 }
652
d7c255b2 653 return 0;
ce8b3ce5
JS
654}
655
7a1dda94
JS
656/**
657 * lpfc_sli4_refresh_params - update driver copy of params.
658 * @phba: Pointer to HBA context object.
659 *
660 * This is called to refresh driver copy of dynamic fields from the
661 * common_get_sli4_parameters descriptor.
662 **/
663int
664lpfc_sli4_refresh_params(struct lpfc_hba *phba)
665{
666 LPFC_MBOXQ_t *mboxq;
667 struct lpfc_mqe *mqe;
668 struct lpfc_sli4_parameters *mbx_sli4_parameters;
669 int length, rc;
670
671 mboxq = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
672 if (!mboxq)
673 return -ENOMEM;
674
675 mqe = &mboxq->u.mqe;
676 /* Read the port's SLI4 Config Parameters */
677 length = (sizeof(struct lpfc_mbx_get_sli4_parameters) -
678 sizeof(struct lpfc_sli4_cfg_mhdr));
679 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
680 LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS,
681 length, LPFC_SLI4_MBX_EMBED);
682
683 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
684 if (unlikely(rc)) {
685 mempool_free(mboxq, phba->mbox_mem_pool);
686 return rc;
687 }
688 mbx_sli4_parameters = &mqe->un.get_sli4_parameters.sli4_parameters;
39a1a86b
JS
689
690 /* Are we forcing MI off via module parameter? */
691 if (phba->cfg_enable_mi)
692 phba->sli4_hba.pc_sli4_params.mi_ver =
7a1dda94 693 bf_get(cfg_mi_ver, mbx_sli4_parameters);
39a1a86b
JS
694 else
695 phba->sli4_hba.pc_sli4_params.mi_ver = 0;
696
7a1dda94
JS
697 phba->sli4_hba.pc_sli4_params.cmf =
698 bf_get(cfg_cmf, mbx_sli4_parameters);
699 phba->sli4_hba.pc_sli4_params.pls =
700 bf_get(cfg_pvl, mbx_sli4_parameters);
701
702 mempool_free(mboxq, phba->mbox_mem_pool);
703 return rc;
704}
705
84d1b006
JS
706/**
707 * lpfc_hba_init_link - Initialize the FC link
708 * @phba: pointer to lpfc hba data structure.
6e7288d9 709 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
84d1b006
JS
710 *
711 * This routine will issue the INIT_LINK mailbox command call.
712 * It is available to other drivers through the lpfc_hba data
713 * structure for use as a delayed link up mechanism with the
714 * module parameter lpfc_suppress_link_up.
715 *
716 * Return code
717 * 0 - success
718 * Any other value - error
719 **/
e399b228 720static int
6e7288d9 721lpfc_hba_init_link(struct lpfc_hba *phba, uint32_t flag)
1b51197d
JS
722{
723 return lpfc_hba_init_link_fc_topology(phba, phba->cfg_topology, flag);
724}
725
726/**
727 * lpfc_hba_init_link_fc_topology - Initialize FC link with desired topology
728 * @phba: pointer to lpfc hba data structure.
729 * @fc_topology: desired fc topology.
730 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
731 *
732 * This routine will issue the INIT_LINK mailbox command call.
733 * It is available to other drivers through the lpfc_hba data
734 * structure for use as a delayed link up mechanism with the
735 * module parameter lpfc_suppress_link_up.
736 *
737 * Return code
738 * 0 - success
739 * Any other value - error
740 **/
741int
742lpfc_hba_init_link_fc_topology(struct lpfc_hba *phba, uint32_t fc_topology,
743 uint32_t flag)
84d1b006
JS
744{
745 struct lpfc_vport *vport = phba->pport;
746 LPFC_MBOXQ_t *pmb;
747 MAILBOX_t *mb;
748 int rc;
749
750 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
751 if (!pmb) {
752 phba->link_state = LPFC_HBA_ERROR;
753 return -ENOMEM;
754 }
755 mb = &pmb->u.mb;
756 pmb->vport = vport;
757
026abb87
JS
758 if ((phba->cfg_link_speed > LPFC_USER_LINK_SPEED_MAX) ||
759 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_1G) &&
760 !(phba->lmt & LMT_1Gb)) ||
761 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_2G) &&
762 !(phba->lmt & LMT_2Gb)) ||
763 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_4G) &&
764 !(phba->lmt & LMT_4Gb)) ||
765 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_8G) &&
766 !(phba->lmt & LMT_8Gb)) ||
767 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_10G) &&
768 !(phba->lmt & LMT_10Gb)) ||
769 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_16G) &&
d38dd52c
JS
770 !(phba->lmt & LMT_16Gb)) ||
771 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_32G) &&
fbd8a6ba
JS
772 !(phba->lmt & LMT_32Gb)) ||
773 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_64G) &&
774 !(phba->lmt & LMT_64Gb))) {
026abb87 775 /* Reset link speed to auto */
372c187b
DK
776 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
777 "1302 Invalid speed for this board:%d "
778 "Reset link speed to auto.\n",
779 phba->cfg_link_speed);
026abb87
JS
780 phba->cfg_link_speed = LPFC_USER_LINK_SPEED_AUTO;
781 }
1b51197d 782 lpfc_init_link(phba, pmb, fc_topology, phba->cfg_link_speed);
84d1b006 783 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
1b51197d
JS
784 if (phba->sli_rev < LPFC_SLI_REV4)
785 lpfc_set_loopback_flag(phba);
6e7288d9 786 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
76a95d75 787 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
372c187b
DK
788 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
789 "0498 Adapter failed to init, mbxCmd x%x "
790 "INIT_LINK, mbxStatus x%x\n",
791 mb->mbxCommand, mb->mbxStatus);
76a95d75
JS
792 if (phba->sli_rev <= LPFC_SLI_REV3) {
793 /* Clear all interrupt enable conditions */
794 writel(0, phba->HCregaddr);
795 readl(phba->HCregaddr); /* flush */
796 /* Clear all pending interrupts */
797 writel(0xffffffff, phba->HAregaddr);
798 readl(phba->HAregaddr); /* flush */
799 }
84d1b006 800 phba->link_state = LPFC_HBA_ERROR;
6e7288d9 801 if (rc != MBX_BUSY || flag == MBX_POLL)
84d1b006
JS
802 mempool_free(pmb, phba->mbox_mem_pool);
803 return -EIO;
804 }
e40a02c1 805 phba->cfg_suppress_link_up = LPFC_INITIALIZE_LINK;
6e7288d9
JS
806 if (flag == MBX_POLL)
807 mempool_free(pmb, phba->mbox_mem_pool);
84d1b006
JS
808
809 return 0;
810}
811
812/**
813 * lpfc_hba_down_link - this routine downs the FC link
6e7288d9
JS
814 * @phba: pointer to lpfc hba data structure.
815 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
84d1b006
JS
816 *
817 * This routine will issue the DOWN_LINK mailbox command call.
818 * It is available to other drivers through the lpfc_hba data
819 * structure for use to stop the link.
820 *
821 * Return code
822 * 0 - success
823 * Any other value - error
824 **/
e399b228 825static int
6e7288d9 826lpfc_hba_down_link(struct lpfc_hba *phba, uint32_t flag)
84d1b006
JS
827{
828 LPFC_MBOXQ_t *pmb;
829 int rc;
830
831 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
832 if (!pmb) {
833 phba->link_state = LPFC_HBA_ERROR;
834 return -ENOMEM;
835 }
836
372c187b
DK
837 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
838 "0491 Adapter Link is disabled.\n");
84d1b006
JS
839 lpfc_down_link(phba, pmb);
840 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
6e7288d9 841 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
84d1b006 842 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
372c187b
DK
843 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
844 "2522 Adapter failed to issue DOWN_LINK"
845 " mbox command rc 0x%x\n", rc);
84d1b006
JS
846
847 mempool_free(pmb, phba->mbox_mem_pool);
848 return -EIO;
849 }
6e7288d9
JS
850 if (flag == MBX_POLL)
851 mempool_free(pmb, phba->mbox_mem_pool);
852
84d1b006
JS
853 return 0;
854}
855
e59058c4 856/**
3621a710 857 * lpfc_hba_down_prep - Perform lpfc uninitialization prior to HBA reset
e59058c4
JS
858 * @phba: pointer to lpfc HBA data structure.
859 *
860 * This routine will do LPFC uninitialization before the HBA is reset when
861 * bringing down the SLI Layer.
862 *
863 * Return codes
864 * 0 - success.
865 * Any other value - error.
866 **/
dea3101e 867int
2e0fef85 868lpfc_hba_down_prep(struct lpfc_hba *phba)
dea3101e 869{
1b32f6aa
JS
870 struct lpfc_vport **vports;
871 int i;
3772a991
JS
872
873 if (phba->sli_rev <= LPFC_SLI_REV3) {
874 /* Disable interrupts */
875 writel(0, phba->HCregaddr);
876 readl(phba->HCregaddr); /* flush */
877 }
dea3101e 878
1b32f6aa
JS
879 if (phba->pport->load_flag & FC_UNLOADING)
880 lpfc_cleanup_discovery_resources(phba->pport);
881 else {
882 vports = lpfc_create_vport_work_array(phba);
883 if (vports != NULL)
3772a991
JS
884 for (i = 0; i <= phba->max_vports &&
885 vports[i] != NULL; i++)
1b32f6aa
JS
886 lpfc_cleanup_discovery_resources(vports[i]);
887 lpfc_destroy_vport_work_array(phba, vports);
7f5f3d0d
JS
888 }
889 return 0;
dea3101e 890}
891
68e814f5
JS
892/**
893 * lpfc_sli4_free_sp_events - Cleanup sp_queue_events to free
894 * rspiocb which got deferred
895 *
896 * @phba: pointer to lpfc HBA data structure.
897 *
898 * This routine will cleanup completed slow path events after HBA is reset
899 * when bringing down the SLI Layer.
900 *
901 *
902 * Return codes
903 * void.
904 **/
905static void
906lpfc_sli4_free_sp_events(struct lpfc_hba *phba)
907{
908 struct lpfc_iocbq *rspiocbq;
909 struct hbq_dmabuf *dmabuf;
910 struct lpfc_cq_event *cq_event;
911
912 spin_lock_irq(&phba->hbalock);
913 phba->hba_flag &= ~HBA_SP_QUEUE_EVT;
914 spin_unlock_irq(&phba->hbalock);
915
916 while (!list_empty(&phba->sli4_hba.sp_queue_event)) {
917 /* Get the response iocb from the head of work queue */
918 spin_lock_irq(&phba->hbalock);
919 list_remove_head(&phba->sli4_hba.sp_queue_event,
920 cq_event, struct lpfc_cq_event, list);
921 spin_unlock_irq(&phba->hbalock);
922
923 switch (bf_get(lpfc_wcqe_c_code, &cq_event->cqe.wcqe_cmpl)) {
924 case CQE_CODE_COMPL_WQE:
925 rspiocbq = container_of(cq_event, struct lpfc_iocbq,
926 cq_event);
927 lpfc_sli_release_iocbq(phba, rspiocbq);
928 break;
929 case CQE_CODE_RECEIVE:
930 case CQE_CODE_RECEIVE_V1:
931 dmabuf = container_of(cq_event, struct hbq_dmabuf,
932 cq_event);
933 lpfc_in_buf_free(phba, &dmabuf->dbuf);
934 }
935 }
936}
937
e59058c4 938/**
bcece5f5 939 * lpfc_hba_free_post_buf - Perform lpfc uninitialization after HBA reset
e59058c4
JS
940 * @phba: pointer to lpfc HBA data structure.
941 *
bcece5f5
JS
942 * This routine will cleanup posted ELS buffers after the HBA is reset
943 * when bringing down the SLI Layer.
944 *
e59058c4
JS
945 *
946 * Return codes
bcece5f5 947 * void.
e59058c4 948 **/
bcece5f5
JS
949static void
950lpfc_hba_free_post_buf(struct lpfc_hba *phba)
41415862
JW
951{
952 struct lpfc_sli *psli = &phba->sli;
953 struct lpfc_sli_ring *pring;
954 struct lpfc_dmabuf *mp, *next_mp;
07eab624
JS
955 LIST_HEAD(buflist);
956 int count;
41415862 957
92d7f7b0
JS
958 if (phba->sli3_options & LPFC_SLI3_HBQ_ENABLED)
959 lpfc_sli_hbqbuf_free_all(phba);
960 else {
961 /* Cleanup preposted buffers on the ELS ring */
895427bd 962 pring = &psli->sli3_ring[LPFC_ELS_RING];
07eab624
JS
963 spin_lock_irq(&phba->hbalock);
964 list_splice_init(&pring->postbufq, &buflist);
965 spin_unlock_irq(&phba->hbalock);
966
967 count = 0;
968 list_for_each_entry_safe(mp, next_mp, &buflist, list) {
92d7f7b0 969 list_del(&mp->list);
07eab624 970 count++;
92d7f7b0
JS
971 lpfc_mbuf_free(phba, mp->virt, mp->phys);
972 kfree(mp);
973 }
07eab624
JS
974
975 spin_lock_irq(&phba->hbalock);
976 pring->postbufq_cnt -= count;
bcece5f5 977 spin_unlock_irq(&phba->hbalock);
41415862 978 }
bcece5f5
JS
979}
980
981/**
982 * lpfc_hba_clean_txcmplq - Perform lpfc uninitialization after HBA reset
983 * @phba: pointer to lpfc HBA data structure.
984 *
985 * This routine will cleanup the txcmplq after the HBA is reset when bringing
986 * down the SLI Layer.
987 *
988 * Return codes
989 * void
990 **/
991static void
992lpfc_hba_clean_txcmplq(struct lpfc_hba *phba)
993{
994 struct lpfc_sli *psli = &phba->sli;
895427bd 995 struct lpfc_queue *qp = NULL;
bcece5f5
JS
996 struct lpfc_sli_ring *pring;
997 LIST_HEAD(completions);
998 int i;
c1dd9111 999 struct lpfc_iocbq *piocb, *next_iocb;
bcece5f5 1000
895427bd
JS
1001 if (phba->sli_rev != LPFC_SLI_REV4) {
1002 for (i = 0; i < psli->num_rings; i++) {
1003 pring = &psli->sli3_ring[i];
bcece5f5 1004 spin_lock_irq(&phba->hbalock);
895427bd
JS
1005 /* At this point in time the HBA is either reset or DOA
1006 * Nothing should be on txcmplq as it will
1007 * NEVER complete.
1008 */
1009 list_splice_init(&pring->txcmplq, &completions);
1010 pring->txcmplq_cnt = 0;
bcece5f5 1011 spin_unlock_irq(&phba->hbalock);
09372820 1012
895427bd
JS
1013 lpfc_sli_abort_iocb_ring(phba, pring);
1014 }
a257bf90 1015 /* Cancel all the IOCBs from the completions list */
895427bd
JS
1016 lpfc_sli_cancel_iocbs(phba, &completions,
1017 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
1018 return;
1019 }
1020 list_for_each_entry(qp, &phba->sli4_hba.lpfc_wq_list, wq_list) {
1021 pring = qp->pring;
1022 if (!pring)
1023 continue;
1024 spin_lock_irq(&pring->ring_lock);
c1dd9111
JS
1025 list_for_each_entry_safe(piocb, next_iocb,
1026 &pring->txcmplq, list)
a680a929 1027 piocb->cmd_flag &= ~LPFC_IO_ON_TXCMPLQ;
895427bd
JS
1028 list_splice_init(&pring->txcmplq, &completions);
1029 pring->txcmplq_cnt = 0;
1030 spin_unlock_irq(&pring->ring_lock);
41415862
JW
1031 lpfc_sli_abort_iocb_ring(phba, pring);
1032 }
895427bd
JS
1033 /* Cancel all the IOCBs from the completions list */
1034 lpfc_sli_cancel_iocbs(phba, &completions,
1035 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
bcece5f5 1036}
41415862 1037
bcece5f5
JS
1038/**
1039 * lpfc_hba_down_post_s3 - Perform lpfc uninitialization after HBA reset
bcece5f5
JS
1040 * @phba: pointer to lpfc HBA data structure.
1041 *
1042 * This routine will do uninitialization after the HBA is reset when bring
1043 * down the SLI Layer.
1044 *
1045 * Return codes
1046 * 0 - success.
1047 * Any other value - error.
1048 **/
1049static int
1050lpfc_hba_down_post_s3(struct lpfc_hba *phba)
1051{
1052 lpfc_hba_free_post_buf(phba);
1053 lpfc_hba_clean_txcmplq(phba);
41415862
JW
1054 return 0;
1055}
5af5eee7 1056
da0436e9
JS
1057/**
1058 * lpfc_hba_down_post_s4 - Perform lpfc uninitialization after HBA reset
1059 * @phba: pointer to lpfc HBA data structure.
1060 *
1061 * This routine will do uninitialization after the HBA is reset when bring
1062 * down the SLI Layer.
1063 *
1064 * Return codes
af901ca1 1065 * 0 - success.
da0436e9
JS
1066 * Any other value - error.
1067 **/
1068static int
1069lpfc_hba_down_post_s4(struct lpfc_hba *phba)
1070{
c490850a 1071 struct lpfc_io_buf *psb, *psb_next;
7cacae2a 1072 struct lpfc_async_xchg_ctx *ctxp, *ctxp_next;
5e5b511d 1073 struct lpfc_sli4_hdw_queue *qp;
da0436e9 1074 LIST_HEAD(aborts);
895427bd 1075 LIST_HEAD(nvme_aborts);
86c67379 1076 LIST_HEAD(nvmet_aborts);
0f65ff68 1077 struct lpfc_sglq *sglq_entry = NULL;
5e5b511d 1078 int cnt, idx;
0f65ff68 1079
895427bd
JS
1080
1081 lpfc_sli_hbqbuf_free_all(phba);
bcece5f5
JS
1082 lpfc_hba_clean_txcmplq(phba);
1083
da0436e9
JS
1084 /* At this point in time the HBA is either reset or DOA. Either
1085 * way, nothing should be on lpfc_abts_els_sgl_list, it needs to be
895427bd 1086 * on the lpfc_els_sgl_list so that it can either be freed if the
da0436e9
JS
1087 * driver is unloading or reposted if the driver is restarting
1088 * the port.
1089 */
a789241e 1090
895427bd 1091 /* sgl_list_lock required because worker thread uses this
da0436e9
JS
1092 * list.
1093 */
a789241e 1094 spin_lock_irq(&phba->sli4_hba.sgl_list_lock);
0f65ff68
JS
1095 list_for_each_entry(sglq_entry,
1096 &phba->sli4_hba.lpfc_abts_els_sgl_list, list)
1097 sglq_entry->state = SGL_FREED;
1098
da0436e9 1099 list_splice_init(&phba->sli4_hba.lpfc_abts_els_sgl_list,
895427bd
JS
1100 &phba->sli4_hba.lpfc_els_sgl_list);
1101
f358dd0c 1102
a789241e 1103 spin_unlock_irq(&phba->sli4_hba.sgl_list_lock);
5e5b511d
JS
1104
1105 /* abts_xxxx_buf_list_lock required because worker thread uses this
da0436e9
JS
1106 * list.
1107 */
a789241e 1108 spin_lock_irq(&phba->hbalock);
5e5b511d
JS
1109 cnt = 0;
1110 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
1111 qp = &phba->sli4_hba.hdwq[idx];
da0436e9 1112
c00f62e6
JS
1113 spin_lock(&qp->abts_io_buf_list_lock);
1114 list_splice_init(&qp->lpfc_abts_io_buf_list,
5e5b511d 1115 &aborts);
68e814f5 1116
0794d601 1117 list_for_each_entry_safe(psb, psb_next, &aborts, list) {
86c67379
JS
1118 psb->pCmd = NULL;
1119 psb->status = IOSTAT_SUCCESS;
cf1a1d3e 1120 cnt++;
86c67379 1121 }
5e5b511d
JS
1122 spin_lock(&qp->io_buf_list_put_lock);
1123 list_splice_init(&aborts, &qp->lpfc_io_buf_list_put);
1124 qp->put_io_bufs += qp->abts_scsi_io_bufs;
c00f62e6 1125 qp->put_io_bufs += qp->abts_nvme_io_bufs;
5e5b511d 1126 qp->abts_scsi_io_bufs = 0;
c00f62e6 1127 qp->abts_nvme_io_bufs = 0;
5e5b511d 1128 spin_unlock(&qp->io_buf_list_put_lock);
c00f62e6 1129 spin_unlock(&qp->abts_io_buf_list_lock);
5e5b511d 1130 }
731eedcb 1131 spin_unlock_irq(&phba->hbalock);
86c67379 1132
5e5b511d 1133 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
731eedcb 1134 spin_lock_irq(&phba->sli4_hba.abts_nvmet_buf_list_lock);
5e5b511d
JS
1135 list_splice_init(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list,
1136 &nvmet_aborts);
731eedcb 1137 spin_unlock_irq(&phba->sli4_hba.abts_nvmet_buf_list_lock);
86c67379 1138 list_for_each_entry_safe(ctxp, ctxp_next, &nvmet_aborts, list) {
7b7f551b 1139 ctxp->flag &= ~(LPFC_NVME_XBUSY | LPFC_NVME_ABORT_OP);
6c621a22 1140 lpfc_nvmet_ctxbuf_post(phba, ctxp->ctxbuf);
86c67379 1141 }
895427bd 1142 }
895427bd 1143
68e814f5 1144 lpfc_sli4_free_sp_events(phba);
5e5b511d 1145 return cnt;
da0436e9
JS
1146}
1147
1148/**
1149 * lpfc_hba_down_post - Wrapper func for hba down post routine
1150 * @phba: pointer to lpfc HBA data structure.
1151 *
1152 * This routine wraps the actual SLI3 or SLI4 routine for performing
1153 * uninitialization after the HBA is reset when bring down the SLI Layer.
1154 *
1155 * Return codes
af901ca1 1156 * 0 - success.
da0436e9
JS
1157 * Any other value - error.
1158 **/
1159int
1160lpfc_hba_down_post(struct lpfc_hba *phba)
1161{
1162 return (*phba->lpfc_hba_down_post)(phba);
1163}
41415862 1164
e59058c4 1165/**
3621a710 1166 * lpfc_hb_timeout - The HBA-timer timeout handler
fe614acd 1167 * @t: timer context used to obtain the pointer to lpfc hba data structure.
e59058c4
JS
1168 *
1169 * This is the HBA-timer timeout handler registered to the lpfc driver. When
1170 * this timer fires, a HBA timeout event shall be posted to the lpfc driver
1171 * work-port-events bitmap and the worker thread is notified. This timeout
1172 * event will be used by the worker thread to invoke the actual timeout
1173 * handler routine, lpfc_hb_timeout_handler. Any periodical operations will
1174 * be performed in the timeout handler and the HBA timeout event bit shall
1175 * be cleared by the worker thread after it has taken the event bitmap out.
1176 **/
a6ababd2 1177static void
f22eb4d3 1178lpfc_hb_timeout(struct timer_list *t)
858c9f6c
JS
1179{
1180 struct lpfc_hba *phba;
5e9d9b82 1181 uint32_t tmo_posted;
858c9f6c
JS
1182 unsigned long iflag;
1183
f22eb4d3 1184 phba = from_timer(phba, t, hb_tmofunc);
9399627f
JS
1185
1186 /* Check for heart beat timeout conditions */
858c9f6c 1187 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
5e9d9b82
JS
1188 tmo_posted = phba->pport->work_port_events & WORKER_HB_TMO;
1189 if (!tmo_posted)
858c9f6c
JS
1190 phba->pport->work_port_events |= WORKER_HB_TMO;
1191 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
1192
9399627f 1193 /* Tell the worker thread there is work to do */
5e9d9b82
JS
1194 if (!tmo_posted)
1195 lpfc_worker_wake_up(phba);
858c9f6c
JS
1196 return;
1197}
1198
19ca7609
JS
1199/**
1200 * lpfc_rrq_timeout - The RRQ-timer timeout handler
fe614acd 1201 * @t: timer context used to obtain the pointer to lpfc hba data structure.
19ca7609
JS
1202 *
1203 * This is the RRQ-timer timeout handler registered to the lpfc driver. When
1204 * this timer fires, a RRQ timeout event shall be posted to the lpfc driver
1205 * work-port-events bitmap and the worker thread is notified. This timeout
1206 * event will be used by the worker thread to invoke the actual timeout
1207 * handler routine, lpfc_rrq_handler. Any periodical operations will
1208 * be performed in the timeout handler and the RRQ timeout event bit shall
1209 * be cleared by the worker thread after it has taken the event bitmap out.
1210 **/
1211static void
f22eb4d3 1212lpfc_rrq_timeout(struct timer_list *t)
19ca7609
JS
1213{
1214 struct lpfc_hba *phba;
19ca7609
JS
1215 unsigned long iflag;
1216
f22eb4d3 1217 phba = from_timer(phba, t, rrq_tmr);
19ca7609 1218 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
06918ac5
JS
1219 if (!(phba->pport->load_flag & FC_UNLOADING))
1220 phba->hba_flag |= HBA_RRQ_ACTIVE;
1221 else
1222 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
19ca7609 1223 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
06918ac5
JS
1224
1225 if (!(phba->pport->load_flag & FC_UNLOADING))
1226 lpfc_worker_wake_up(phba);
19ca7609
JS
1227}
1228
e59058c4 1229/**
3621a710 1230 * lpfc_hb_mbox_cmpl - The lpfc heart-beat mailbox command callback function
e59058c4
JS
1231 * @phba: pointer to lpfc hba data structure.
1232 * @pmboxq: pointer to the driver internal queue element for mailbox command.
1233 *
1234 * This is the callback function to the lpfc heart-beat mailbox command.
1235 * If configured, the lpfc driver issues the heart-beat mailbox command to
1236 * the HBA every LPFC_HB_MBOX_INTERVAL (current 5) seconds. At the time the
1237 * heart-beat mailbox command is issued, the driver shall set up heart-beat
1238 * timeout timer to LPFC_HB_MBOX_TIMEOUT (current 30) seconds and marks
1239 * heart-beat outstanding state. Once the mailbox command comes back and
1240 * no error conditions detected, the heart-beat mailbox command timer is
1241 * reset to LPFC_HB_MBOX_INTERVAL seconds and the heart-beat outstanding
1242 * state is cleared for the next heart-beat. If the timer expired with the
1243 * heart-beat outstanding state set, the driver will put the HBA offline.
1244 **/
858c9f6c
JS
1245static void
1246lpfc_hb_mbox_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
1247{
1248 unsigned long drvr_flag;
1249
1250 spin_lock_irqsave(&phba->hbalock, drvr_flag);
a22d73b6 1251 phba->hba_flag &= ~(HBA_HBEAT_INP | HBA_HBEAT_TMO);
858c9f6c
JS
1252 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
1253
a22d73b6 1254 /* Check and reset heart-beat timer if necessary */
858c9f6c
JS
1255 mempool_free(pmboxq, phba->mbox_mem_pool);
1256 if (!(phba->pport->fc_flag & FC_OFFLINE_MODE) &&
1257 !(phba->link_state == LPFC_HBA_ERROR) &&
51ef4c26 1258 !(phba->pport->load_flag & FC_UNLOADING))
858c9f6c 1259 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1260 jiffies +
1261 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
1262 return;
1263}
1264
fe614acd 1265/*
317aeb83
DK
1266 * lpfc_idle_stat_delay_work - idle_stat tracking
1267 *
1268 * This routine tracks per-cq idle_stat and determines polling decisions.
1269 *
1270 * Return codes:
1271 * None
1272 **/
1273static void
1274lpfc_idle_stat_delay_work(struct work_struct *work)
1275{
1276 struct lpfc_hba *phba = container_of(to_delayed_work(work),
1277 struct lpfc_hba,
1278 idle_stat_delay_work);
1279 struct lpfc_queue *cq;
1280 struct lpfc_sli4_hdw_queue *hdwq;
1281 struct lpfc_idle_stat *idle_stat;
1282 u32 i, idle_percent;
1283 u64 wall, wall_idle, diff_wall, diff_idle, busy_time;
1284
1285 if (phba->pport->load_flag & FC_UNLOADING)
1286 return;
1287
1288 if (phba->link_state == LPFC_HBA_ERROR ||
9064aeb2
JS
1289 phba->pport->fc_flag & FC_OFFLINE_MODE ||
1290 phba->cmf_active_mode != LPFC_CFG_OFF)
317aeb83
DK
1291 goto requeue;
1292
1293 for_each_present_cpu(i) {
1294 hdwq = &phba->sli4_hba.hdwq[phba->sli4_hba.cpu_map[i].hdwq];
1295 cq = hdwq->io_cq;
1296
1297 /* Skip if we've already handled this cq's primary CPU */
1298 if (cq->chann != i)
1299 continue;
1300
1301 idle_stat = &phba->sli4_hba.idle_stat[i];
1302
1303 /* get_cpu_idle_time returns values as running counters. Thus,
1304 * to know the amount for this period, the prior counter values
1305 * need to be subtracted from the current counter values.
1306 * From there, the idle time stat can be calculated as a
1307 * percentage of 100 - the sum of the other consumption times.
1308 */
1309 wall_idle = get_cpu_idle_time(i, &wall, 1);
1310 diff_idle = wall_idle - idle_stat->prev_idle;
1311 diff_wall = wall - idle_stat->prev_wall;
1312
1313 if (diff_wall <= diff_idle)
1314 busy_time = 0;
1315 else
1316 busy_time = diff_wall - diff_idle;
1317
1318 idle_percent = div64_u64(100 * busy_time, diff_wall);
1319 idle_percent = 100 - idle_percent;
1320
1321 if (idle_percent < 15)
1322 cq->poll_mode = LPFC_QUEUE_WORK;
1323 else
1324 cq->poll_mode = LPFC_IRQ_POLL;
1325
1326 idle_stat->prev_idle = wall_idle;
1327 idle_stat->prev_wall = wall;
1328 }
1329
1330requeue:
1331 schedule_delayed_work(&phba->idle_stat_delay_work,
1332 msecs_to_jiffies(LPFC_IDLE_STAT_DELAY));
1333}
1334
32517fc0
JS
1335static void
1336lpfc_hb_eq_delay_work(struct work_struct *work)
1337{
1338 struct lpfc_hba *phba = container_of(to_delayed_work(work),
1339 struct lpfc_hba, eq_delay_work);
1340 struct lpfc_eq_intr_info *eqi, *eqi_new;
1341 struct lpfc_queue *eq, *eq_next;
8156d378 1342 unsigned char *ena_delay = NULL;
32517fc0
JS
1343 uint32_t usdelay;
1344 int i;
1345
1346 if (!phba->cfg_auto_imax || phba->pport->load_flag & FC_UNLOADING)
1347 return;
1348
1349 if (phba->link_state == LPFC_HBA_ERROR ||
1350 phba->pport->fc_flag & FC_OFFLINE_MODE)
1351 goto requeue;
1352
8156d378
JS
1353 ena_delay = kcalloc(phba->sli4_hba.num_possible_cpu, sizeof(*ena_delay),
1354 GFP_KERNEL);
1355 if (!ena_delay)
32517fc0
JS
1356 goto requeue;
1357
8156d378
JS
1358 for (i = 0; i < phba->cfg_irq_chann; i++) {
1359 /* Get the EQ corresponding to the IRQ vector */
1360 eq = phba->sli4_hba.hba_eq_hdl[i].eq;
1361 if (!eq)
1362 continue;
1363 if (eq->q_mode || eq->q_flag & HBA_EQ_DELAY_CHK) {
1364 eq->q_flag &= ~HBA_EQ_DELAY_CHK;
1365 ena_delay[eq->last_cpu] = 1;
8d34a59c 1366 }
8156d378 1367 }
32517fc0
JS
1368
1369 for_each_present_cpu(i) {
32517fc0 1370 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, i);
8156d378
JS
1371 if (ena_delay[i]) {
1372 usdelay = (eqi->icnt >> 10) * LPFC_EQ_DELAY_STEP;
1373 if (usdelay > LPFC_MAX_AUTO_EQ_DELAY)
1374 usdelay = LPFC_MAX_AUTO_EQ_DELAY;
1375 } else {
1376 usdelay = 0;
8d34a59c 1377 }
32517fc0 1378
32517fc0
JS
1379 eqi->icnt = 0;
1380
1381 list_for_each_entry_safe(eq, eq_next, &eqi->list, cpu_list) {
8156d378 1382 if (unlikely(eq->last_cpu != i)) {
32517fc0
JS
1383 eqi_new = per_cpu_ptr(phba->sli4_hba.eq_info,
1384 eq->last_cpu);
1385 list_move_tail(&eq->cpu_list, &eqi_new->list);
1386 continue;
1387 }
1388 if (usdelay != eq->q_mode)
1389 lpfc_modify_hba_eq_delay(phba, eq->hdwq, 1,
1390 usdelay);
1391 }
1392 }
1393
8156d378 1394 kfree(ena_delay);
32517fc0
JS
1395
1396requeue:
1397 queue_delayed_work(phba->wq, &phba->eq_delay_work,
1398 msecs_to_jiffies(LPFC_EQ_DELAY_MSECS));
1399}
1400
c490850a
JS
1401/**
1402 * lpfc_hb_mxp_handler - Multi-XRI pools handler to adjust XRI distribution
1403 * @phba: pointer to lpfc hba data structure.
1404 *
1405 * For each heartbeat, this routine does some heuristic methods to adjust
1406 * XRI distribution. The goal is to fully utilize free XRIs.
1407 **/
1408static void lpfc_hb_mxp_handler(struct lpfc_hba *phba)
1409{
1410 u32 i;
1411 u32 hwq_count;
1412
1413 hwq_count = phba->cfg_hdw_queue;
1414 for (i = 0; i < hwq_count; i++) {
1415 /* Adjust XRIs in private pool */
1416 lpfc_adjust_pvt_pool_count(phba, i);
1417
1418 /* Adjust high watermark */
1419 lpfc_adjust_high_watermark(phba, i);
1420
1421#ifdef LPFC_MXP_STAT
1422 /* Snapshot pbl, pvt and busy count */
1423 lpfc_snapshot_mxp(phba, i);
1424#endif
1425 }
1426}
1427
a22d73b6
JS
1428/**
1429 * lpfc_issue_hb_mbox - Issues heart-beat mailbox command
1430 * @phba: pointer to lpfc hba data structure.
1431 *
1432 * If a HB mbox is not already in progrees, this routine will allocate
1433 * a LPFC_MBOXQ_t, populate it with a MBX_HEARTBEAT (0x31) command,
1434 * and issue it. The HBA_HBEAT_INP flag means the command is in progress.
1435 **/
1436int
1437lpfc_issue_hb_mbox(struct lpfc_hba *phba)
1438{
1439 LPFC_MBOXQ_t *pmboxq;
1440 int retval;
1441
1442 /* Is a Heartbeat mbox already in progress */
1443 if (phba->hba_flag & HBA_HBEAT_INP)
1444 return 0;
1445
1446 pmboxq = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
1447 if (!pmboxq)
1448 return -ENOMEM;
1449
1450 lpfc_heart_beat(phba, pmboxq);
1451 pmboxq->mbox_cmpl = lpfc_hb_mbox_cmpl;
1452 pmboxq->vport = phba->pport;
1453 retval = lpfc_sli_issue_mbox(phba, pmboxq, MBX_NOWAIT);
1454
1455 if (retval != MBX_BUSY && retval != MBX_SUCCESS) {
1456 mempool_free(pmboxq, phba->mbox_mem_pool);
1457 return -ENXIO;
1458 }
1459 phba->hba_flag |= HBA_HBEAT_INP;
1460
1461 return 0;
1462}
1463
1464/**
1465 * lpfc_issue_hb_tmo - Signals heartbeat timer to issue mbox command
1466 * @phba: pointer to lpfc hba data structure.
1467 *
1468 * The heartbeat timer (every 5 sec) will fire. If the HBA_HBEAT_TMO
1469 * flag is set, it will force a MBX_HEARTBEAT mbox command, regardless
1470 * of the value of lpfc_enable_hba_heartbeat.
1471 * If lpfc_enable_hba_heartbeat is set, the timeout routine will always
1472 * try to issue a MBX_HEARTBEAT mbox command.
1473 **/
1474void
1475lpfc_issue_hb_tmo(struct lpfc_hba *phba)
1476{
1477 if (phba->cfg_enable_hba_heartbeat)
1478 return;
1479 phba->hba_flag |= HBA_HBEAT_TMO;
1480}
1481
e59058c4 1482/**
3621a710 1483 * lpfc_hb_timeout_handler - The HBA-timer timeout handler
e59058c4
JS
1484 * @phba: pointer to lpfc hba data structure.
1485 *
1486 * This is the actual HBA-timer timeout handler to be invoked by the worker
1487 * thread whenever the HBA timer fired and HBA-timeout event posted. This
1488 * handler performs any periodic operations needed for the device. If such
1489 * periodic event has already been attended to either in the interrupt handler
1490 * or by processing slow-ring or fast-ring events within the HBA-timer
1491 * timeout window (LPFC_HB_MBOX_INTERVAL), this handler just simply resets
1492 * the timer for the next timeout period. If lpfc heart-beat mailbox command
1493 * is configured and there is no heart-beat mailbox command outstanding, a
1494 * heart-beat mailbox is issued and timer set properly. Otherwise, if there
1495 * has been a heart-beat mailbox command outstanding, the HBA shall be put
1496 * to offline.
1497 **/
858c9f6c
JS
1498void
1499lpfc_hb_timeout_handler(struct lpfc_hba *phba)
1500{
45ed1190 1501 struct lpfc_vport **vports;
0ff10d46 1502 struct lpfc_dmabuf *buf_ptr;
a22d73b6
JS
1503 int retval = 0;
1504 int i, tmo;
858c9f6c 1505 struct lpfc_sli *psli = &phba->sli;
0ff10d46 1506 LIST_HEAD(completions);
858c9f6c 1507
c490850a
JS
1508 if (phba->cfg_xri_rebalancing) {
1509 /* Multi-XRI pools handler */
1510 lpfc_hb_mxp_handler(phba);
1511 }
858c9f6c 1512
45ed1190
JS
1513 vports = lpfc_create_vport_work_array(phba);
1514 if (vports != NULL)
4258e98e 1515 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
45ed1190 1516 lpfc_rcv_seq_check_edtov(vports[i]);
e3ba04c9 1517 lpfc_fdmi_change_check(vports[i]);
4258e98e 1518 }
45ed1190
JS
1519 lpfc_destroy_vport_work_array(phba, vports);
1520
858c9f6c 1521 if ((phba->link_state == LPFC_HBA_ERROR) ||
51ef4c26 1522 (phba->pport->load_flag & FC_UNLOADING) ||
858c9f6c
JS
1523 (phba->pport->fc_flag & FC_OFFLINE_MODE))
1524 return;
1525
0ff10d46
JS
1526 if (phba->elsbuf_cnt &&
1527 (phba->elsbuf_cnt == phba->elsbuf_prev_cnt)) {
1528 spin_lock_irq(&phba->hbalock);
1529 list_splice_init(&phba->elsbuf, &completions);
1530 phba->elsbuf_cnt = 0;
1531 phba->elsbuf_prev_cnt = 0;
1532 spin_unlock_irq(&phba->hbalock);
1533
1534 while (!list_empty(&completions)) {
1535 list_remove_head(&completions, buf_ptr,
1536 struct lpfc_dmabuf, list);
1537 lpfc_mbuf_free(phba, buf_ptr->virt, buf_ptr->phys);
1538 kfree(buf_ptr);
1539 }
1540 }
1541 phba->elsbuf_prev_cnt = phba->elsbuf_cnt;
1542
858c9f6c 1543 /* If there is no heart beat outstanding, issue a heartbeat command */
13815c83 1544 if (phba->cfg_enable_hba_heartbeat) {
a22d73b6
JS
1545 /* If IOs are completing, no need to issue a MBX_HEARTBEAT */
1546 spin_lock_irq(&phba->pport->work_port_lock);
1547 if (time_after(phba->last_completion_time +
1548 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL),
1549 jiffies)) {
1550 spin_unlock_irq(&phba->pport->work_port_lock);
1551 if (phba->hba_flag & HBA_HBEAT_INP)
1552 tmo = (1000 * LPFC_HB_MBOX_TIMEOUT);
1553 else
1554 tmo = (1000 * LPFC_HB_MBOX_INTERVAL);
1555 goto out;
1556 }
1557 spin_unlock_irq(&phba->pport->work_port_lock);
1558
1559 /* Check if a MBX_HEARTBEAT is already in progress */
1560 if (phba->hba_flag & HBA_HBEAT_INP) {
1561 /*
1562 * If heart beat timeout called with HBA_HBEAT_INP set
1563 * we need to give the hb mailbox cmd a chance to
1564 * complete or TMO.
1565 */
1566 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1567 "0459 Adapter heartbeat still outstanding: "
1568 "last compl time was %d ms.\n",
1569 jiffies_to_msecs(jiffies
1570 - phba->last_completion_time));
1571 tmo = (1000 * LPFC_HB_MBOX_TIMEOUT);
1572 } else {
bc73905a
JS
1573 if ((!(psli->sli_flag & LPFC_SLI_MBOX_ACTIVE)) &&
1574 (list_empty(&psli->mboxq))) {
bc73905a 1575
a22d73b6
JS
1576 retval = lpfc_issue_hb_mbox(phba);
1577 if (retval) {
1578 tmo = (1000 * LPFC_HB_MBOX_INTERVAL);
1579 goto out;
bc73905a
JS
1580 }
1581 phba->skipped_hb = 0;
bc73905a
JS
1582 } else if (time_before_eq(phba->last_completion_time,
1583 phba->skipped_hb)) {
1584 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
1585 "2857 Last completion time not "
1586 " updated in %d ms\n",
1587 jiffies_to_msecs(jiffies
1588 - phba->last_completion_time));
1589 } else
1590 phba->skipped_hb = jiffies;
1591
a22d73b6
JS
1592 tmo = (1000 * LPFC_HB_MBOX_TIMEOUT);
1593 goto out;
858c9f6c 1594 }
4258e98e 1595 } else {
a22d73b6
JS
1596 /* Check to see if we want to force a MBX_HEARTBEAT */
1597 if (phba->hba_flag & HBA_HBEAT_TMO) {
1598 retval = lpfc_issue_hb_mbox(phba);
1599 if (retval)
1600 tmo = (1000 * LPFC_HB_MBOX_INTERVAL);
1601 else
1602 tmo = (1000 * LPFC_HB_MBOX_TIMEOUT);
1603 goto out;
1604 }
1605 tmo = (1000 * LPFC_HB_MBOX_INTERVAL);
858c9f6c 1606 }
a22d73b6
JS
1607out:
1608 mod_timer(&phba->hb_tmofunc, jiffies + msecs_to_jiffies(tmo));
858c9f6c
JS
1609}
1610
e59058c4 1611/**
3621a710 1612 * lpfc_offline_eratt - Bring lpfc offline on hardware error attention
e59058c4
JS
1613 * @phba: pointer to lpfc hba data structure.
1614 *
1615 * This routine is called to bring the HBA offline when HBA hardware error
1616 * other than Port Error 6 has been detected.
1617 **/
09372820
JS
1618static void
1619lpfc_offline_eratt(struct lpfc_hba *phba)
1620{
1621 struct lpfc_sli *psli = &phba->sli;
1622
1623 spin_lock_irq(&phba->hbalock);
f4b4c68f 1624 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
09372820 1625 spin_unlock_irq(&phba->hbalock);
618a5230 1626 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
09372820
JS
1627
1628 lpfc_offline(phba);
1629 lpfc_reset_barrier(phba);
f4b4c68f 1630 spin_lock_irq(&phba->hbalock);
09372820 1631 lpfc_sli_brdreset(phba);
f4b4c68f 1632 spin_unlock_irq(&phba->hbalock);
09372820
JS
1633 lpfc_hba_down_post(phba);
1634 lpfc_sli_brdready(phba, HS_MBRDY);
1635 lpfc_unblock_mgmt_io(phba);
1636 phba->link_state = LPFC_HBA_ERROR;
1637 return;
1638}
1639
da0436e9
JS
1640/**
1641 * lpfc_sli4_offline_eratt - Bring lpfc offline on SLI4 hardware error attention
1642 * @phba: pointer to lpfc hba data structure.
1643 *
1644 * This routine is called to bring a SLI4 HBA offline when HBA hardware error
1645 * other than Port Error 6 has been detected.
1646 **/
a88dbb6a 1647void
da0436e9
JS
1648lpfc_sli4_offline_eratt(struct lpfc_hba *phba)
1649{
946727dc 1650 spin_lock_irq(&phba->hbalock);
25ac2c97 1651 if (phba->link_state == LPFC_HBA_ERROR &&
35ed9613 1652 test_bit(HBA_PCI_ERR, &phba->bit_flags)) {
25ac2c97
JS
1653 spin_unlock_irq(&phba->hbalock);
1654 return;
1655 }
946727dc
JS
1656 phba->link_state = LPFC_HBA_ERROR;
1657 spin_unlock_irq(&phba->hbalock);
1658
618a5230 1659 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
c00f62e6 1660 lpfc_sli_flush_io_rings(phba);
da0436e9 1661 lpfc_offline(phba);
da0436e9 1662 lpfc_hba_down_post(phba);
da0436e9 1663 lpfc_unblock_mgmt_io(phba);
da0436e9
JS
1664}
1665
a257bf90
JS
1666/**
1667 * lpfc_handle_deferred_eratt - The HBA hardware deferred error handler
1668 * @phba: pointer to lpfc hba data structure.
1669 *
1670 * This routine is invoked to handle the deferred HBA hardware error
1671 * conditions. This type of error is indicated by HBA by setting ER1
1672 * and another ER bit in the host status register. The driver will
1673 * wait until the ER1 bit clears before handling the error condition.
1674 **/
1675static void
1676lpfc_handle_deferred_eratt(struct lpfc_hba *phba)
1677{
1678 uint32_t old_host_status = phba->work_hs;
a257bf90
JS
1679 struct lpfc_sli *psli = &phba->sli;
1680
f4b4c68f
JS
1681 /* If the pci channel is offline, ignore possible errors,
1682 * since we cannot communicate with the pci card anyway.
1683 */
1684 if (pci_channel_offline(phba->pcidev)) {
1685 spin_lock_irq(&phba->hbalock);
1686 phba->hba_flag &= ~DEFER_ERATT;
1687 spin_unlock_irq(&phba->hbalock);
1688 return;
1689 }
1690
372c187b
DK
1691 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1692 "0479 Deferred Adapter Hardware Error "
1693 "Data: x%x x%x x%x\n",
1694 phba->work_hs, phba->work_status[0],
1695 phba->work_status[1]);
a257bf90
JS
1696
1697 spin_lock_irq(&phba->hbalock);
f4b4c68f 1698 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
a257bf90
JS
1699 spin_unlock_irq(&phba->hbalock);
1700
1701
1702 /*
1703 * Firmware stops when it triggred erratt. That could cause the I/Os
1704 * dropped by the firmware. Error iocb (I/O) on txcmplq and let the
1705 * SCSI layer retry it after re-establishing link.
1706 */
db55fba8 1707 lpfc_sli_abort_fcp_rings(phba);
a257bf90
JS
1708
1709 /*
1710 * There was a firmware error. Take the hba offline and then
1711 * attempt to restart it.
1712 */
618a5230 1713 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
a257bf90
JS
1714 lpfc_offline(phba);
1715
1716 /* Wait for the ER1 bit to clear.*/
1717 while (phba->work_hs & HS_FFER1) {
1718 msleep(100);
9940b97b
JS
1719 if (lpfc_readl(phba->HSregaddr, &phba->work_hs)) {
1720 phba->work_hs = UNPLUG_ERR ;
1721 break;
1722 }
a257bf90
JS
1723 /* If driver is unloading let the worker thread continue */
1724 if (phba->pport->load_flag & FC_UNLOADING) {
1725 phba->work_hs = 0;
1726 break;
1727 }
1728 }
1729
1730 /*
1731 * This is to ptrotect against a race condition in which
1732 * first write to the host attention register clear the
1733 * host status register.
1734 */
1735 if ((!phba->work_hs) && (!(phba->pport->load_flag & FC_UNLOADING)))
1736 phba->work_hs = old_host_status & ~HS_FFER1;
1737
3772a991 1738 spin_lock_irq(&phba->hbalock);
a257bf90 1739 phba->hba_flag &= ~DEFER_ERATT;
3772a991 1740 spin_unlock_irq(&phba->hbalock);
a257bf90
JS
1741 phba->work_status[0] = readl(phba->MBslimaddr + 0xa8);
1742 phba->work_status[1] = readl(phba->MBslimaddr + 0xac);
1743}
1744
3772a991
JS
1745static void
1746lpfc_board_errevt_to_mgmt(struct lpfc_hba *phba)
1747{
1748 struct lpfc_board_event_header board_event;
1749 struct Scsi_Host *shost;
1750
1751 board_event.event_type = FC_REG_BOARD_EVENT;
1752 board_event.subcategory = LPFC_EVENT_PORTINTERR;
1753 shost = lpfc_shost_from_vport(phba->pport);
1754 fc_host_post_vendor_event(shost, fc_get_event_number(),
1755 sizeof(board_event),
1756 (char *) &board_event,
1757 LPFC_NL_VENDOR_ID);
1758}
1759
e59058c4 1760/**
3772a991 1761 * lpfc_handle_eratt_s3 - The SLI3 HBA hardware error handler
e59058c4
JS
1762 * @phba: pointer to lpfc hba data structure.
1763 *
1764 * This routine is invoked to handle the following HBA hardware error
1765 * conditions:
1766 * 1 - HBA error attention interrupt
1767 * 2 - DMA ring index out of range
1768 * 3 - Mailbox command came back as unknown
1769 **/
3772a991
JS
1770static void
1771lpfc_handle_eratt_s3(struct lpfc_hba *phba)
dea3101e 1772{
2e0fef85 1773 struct lpfc_vport *vport = phba->pport;
2e0fef85 1774 struct lpfc_sli *psli = &phba->sli;
d2873e4c 1775 uint32_t event_data;
57127f15
JS
1776 unsigned long temperature;
1777 struct temp_event temp_event_data;
92d7f7b0 1778 struct Scsi_Host *shost;
2e0fef85 1779
8d63f375 1780 /* If the pci channel is offline, ignore possible errors,
3772a991
JS
1781 * since we cannot communicate with the pci card anyway.
1782 */
1783 if (pci_channel_offline(phba->pcidev)) {
1784 spin_lock_irq(&phba->hbalock);
1785 phba->hba_flag &= ~DEFER_ERATT;
1786 spin_unlock_irq(&phba->hbalock);
8d63f375 1787 return;
3772a991
JS
1788 }
1789
13815c83
JS
1790 /* If resets are disabled then leave the HBA alone and return */
1791 if (!phba->cfg_enable_hba_reset)
1792 return;
dea3101e 1793
ea2151b4 1794 /* Send an internal error event to mgmt application */
3772a991 1795 lpfc_board_errevt_to_mgmt(phba);
ea2151b4 1796
a257bf90
JS
1797 if (phba->hba_flag & DEFER_ERATT)
1798 lpfc_handle_deferred_eratt(phba);
1799
dcf2a4e0
JS
1800 if ((phba->work_hs & HS_FFER6) || (phba->work_hs & HS_FFER8)) {
1801 if (phba->work_hs & HS_FFER6)
1802 /* Re-establishing Link */
1803 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1804 "1301 Re-establishing Link "
1805 "Data: x%x x%x x%x\n",
1806 phba->work_hs, phba->work_status[0],
1807 phba->work_status[1]);
1808 if (phba->work_hs & HS_FFER8)
1809 /* Device Zeroization */
1810 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1811 "2861 Host Authentication device "
1812 "zeroization Data:x%x x%x x%x\n",
1813 phba->work_hs, phba->work_status[0],
1814 phba->work_status[1]);
58da1ffb 1815
92d7f7b0 1816 spin_lock_irq(&phba->hbalock);
f4b4c68f 1817 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
92d7f7b0 1818 spin_unlock_irq(&phba->hbalock);
dea3101e 1819
1820 /*
1821 * Firmware stops when it triggled erratt with HS_FFER6.
1822 * That could cause the I/Os dropped by the firmware.
1823 * Error iocb (I/O) on txcmplq and let the SCSI layer
1824 * retry it after re-establishing link.
1825 */
db55fba8 1826 lpfc_sli_abort_fcp_rings(phba);
dea3101e 1827
dea3101e 1828 /*
1829 * There was a firmware error. Take the hba offline and then
1830 * attempt to restart it.
1831 */
618a5230 1832 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
dea3101e 1833 lpfc_offline(phba);
41415862 1834 lpfc_sli_brdrestart(phba);
dea3101e 1835 if (lpfc_online(phba) == 0) { /* Initialize the HBA */
46fa311e 1836 lpfc_unblock_mgmt_io(phba);
dea3101e 1837 return;
1838 }
46fa311e 1839 lpfc_unblock_mgmt_io(phba);
57127f15
JS
1840 } else if (phba->work_hs & HS_CRIT_TEMP) {
1841 temperature = readl(phba->MBslimaddr + TEMPERATURE_OFFSET);
1842 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1843 temp_event_data.event_code = LPFC_CRIT_TEMP;
1844 temp_event_data.data = (uint32_t)temperature;
1845
372c187b 1846 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
d7c255b2 1847 "0406 Adapter maximum temperature exceeded "
57127f15
JS
1848 "(%ld), taking this port offline "
1849 "Data: x%x x%x x%x\n",
1850 temperature, phba->work_hs,
1851 phba->work_status[0], phba->work_status[1]);
1852
1853 shost = lpfc_shost_from_vport(phba->pport);
1854 fc_host_post_vendor_event(shost, fc_get_event_number(),
1855 sizeof(temp_event_data),
1856 (char *) &temp_event_data,
1857 SCSI_NL_VID_TYPE_PCI
1858 | PCI_VENDOR_ID_EMULEX);
1859
7af67051 1860 spin_lock_irq(&phba->hbalock);
7af67051
JS
1861 phba->over_temp_state = HBA_OVER_TEMP;
1862 spin_unlock_irq(&phba->hbalock);
09372820 1863 lpfc_offline_eratt(phba);
57127f15 1864
dea3101e 1865 } else {
1866 /* The if clause above forces this code path when the status
9399627f
JS
1867 * failure is a value other than FFER6. Do not call the offline
1868 * twice. This is the adapter hardware error path.
dea3101e 1869 */
372c187b 1870 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 1871 "0457 Adapter Hardware Error "
dea3101e 1872 "Data: x%x x%x x%x\n",
e8b62011 1873 phba->work_hs,
dea3101e 1874 phba->work_status[0], phba->work_status[1]);
1875
d2873e4c 1876 event_data = FC_REG_DUMP_EVENT;
92d7f7b0 1877 shost = lpfc_shost_from_vport(vport);
2e0fef85 1878 fc_host_post_vendor_event(shost, fc_get_event_number(),
d2873e4c
JS
1879 sizeof(event_data), (char *) &event_data,
1880 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
1881
09372820 1882 lpfc_offline_eratt(phba);
dea3101e 1883 }
9399627f 1884 return;
dea3101e 1885}
1886
618a5230
JS
1887/**
1888 * lpfc_sli4_port_sta_fn_reset - The SLI4 function reset due to port status reg
1889 * @phba: pointer to lpfc hba data structure.
1890 * @mbx_action: flag for mailbox shutdown action.
fe614acd 1891 * @en_rn_msg: send reset/port recovery message.
618a5230
JS
1892 * This routine is invoked to perform an SLI4 port PCI function reset in
1893 * response to port status register polling attention. It waits for port
1894 * status register (ERR, RDY, RN) bits before proceeding with function reset.
1895 * During this process, interrupt vectors are freed and later requested
1896 * for handling possible port resource change.
1897 **/
1898static int
e10b2022
JS
1899lpfc_sli4_port_sta_fn_reset(struct lpfc_hba *phba, int mbx_action,
1900 bool en_rn_msg)
618a5230
JS
1901{
1902 int rc;
1903 uint32_t intr_mode;
a9978e39 1904 LPFC_MBOXQ_t *mboxq;
618a5230 1905
27d6ac0a 1906 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) >=
65791f1f
JS
1907 LPFC_SLI_INTF_IF_TYPE_2) {
1908 /*
1909 * On error status condition, driver need to wait for port
1910 * ready before performing reset.
1911 */
1912 rc = lpfc_sli4_pdev_status_reg_wait(phba);
0e916ee7 1913 if (rc)
65791f1f
JS
1914 return rc;
1915 }
0e916ee7 1916
65791f1f
JS
1917 /* need reset: attempt for port recovery */
1918 if (en_rn_msg)
0b3ad32e 1919 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
65791f1f
JS
1920 "2887 Reset Needed: Attempting Port "
1921 "Recovery...\n");
3ba6216a
JS
1922
1923 /* If we are no wait, the HBA has been reset and is not
a9978e39
JS
1924 * functional, thus we should clear
1925 * (LPFC_SLI_ACTIVE | LPFC_SLI_MBOX_ACTIVE) flags.
3ba6216a
JS
1926 */
1927 if (mbx_action == LPFC_MBX_NO_WAIT) {
1928 spin_lock_irq(&phba->hbalock);
1929 phba->sli.sli_flag &= ~LPFC_SLI_ACTIVE;
a9978e39
JS
1930 if (phba->sli.mbox_active) {
1931 mboxq = phba->sli.mbox_active;
1932 mboxq->u.mb.mbxStatus = MBX_NOT_FINISHED;
1933 __lpfc_mbox_cmpl_put(phba, mboxq);
1934 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
1935 phba->sli.mbox_active = NULL;
1936 }
3ba6216a
JS
1937 spin_unlock_irq(&phba->hbalock);
1938 }
1939
65791f1f 1940 lpfc_offline_prep(phba, mbx_action);
c00f62e6 1941 lpfc_sli_flush_io_rings(phba);
65791f1f
JS
1942 lpfc_offline(phba);
1943 /* release interrupt for possible resource change */
1944 lpfc_sli4_disable_intr(phba);
5a9eeff5
JS
1945 rc = lpfc_sli_brdrestart(phba);
1946 if (rc) {
372c187b 1947 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5a9eeff5
JS
1948 "6309 Failed to restart board\n");
1949 return rc;
1950 }
65791f1f
JS
1951 /* request and enable interrupt */
1952 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
1953 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 1954 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
1955 "3175 Failed to enable interrupt\n");
1956 return -EIO;
618a5230 1957 }
65791f1f
JS
1958 phba->intr_mode = intr_mode;
1959 rc = lpfc_online(phba);
1960 if (rc == 0)
1961 lpfc_unblock_mgmt_io(phba);
1962
618a5230
JS
1963 return rc;
1964}
1965
da0436e9
JS
1966/**
1967 * lpfc_handle_eratt_s4 - The SLI4 HBA hardware error handler
1968 * @phba: pointer to lpfc hba data structure.
1969 *
1970 * This routine is invoked to handle the SLI4 HBA hardware error attention
1971 * conditions.
1972 **/
1973static void
1974lpfc_handle_eratt_s4(struct lpfc_hba *phba)
1975{
1976 struct lpfc_vport *vport = phba->pport;
1977 uint32_t event_data;
1978 struct Scsi_Host *shost;
2fcee4bf 1979 uint32_t if_type;
2e90f4b5
JS
1980 struct lpfc_register portstat_reg = {0};
1981 uint32_t reg_err1, reg_err2;
1982 uint32_t uerrlo_reg, uemasklo_reg;
65791f1f 1983 uint32_t smphr_port_status = 0, pci_rd_rc1, pci_rd_rc2;
e10b2022 1984 bool en_rn_msg = true;
946727dc 1985 struct temp_event temp_event_data;
65791f1f
JS
1986 struct lpfc_register portsmphr_reg;
1987 int rc, i;
da0436e9
JS
1988
1989 /* If the pci channel is offline, ignore possible errors, since
1990 * we cannot communicate with the pci card anyway.
1991 */
32a93100 1992 if (pci_channel_offline(phba->pcidev)) {
372c187b 1993 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
32a93100 1994 "3166 pci channel is offline\n");
a4691038 1995 lpfc_sli_flush_io_rings(phba);
da0436e9 1996 return;
32a93100 1997 }
da0436e9 1998
65791f1f 1999 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
2fcee4bf
JS
2000 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
2001 switch (if_type) {
2002 case LPFC_SLI_INTF_IF_TYPE_0:
2e90f4b5
JS
2003 pci_rd_rc1 = lpfc_readl(
2004 phba->sli4_hba.u.if_type0.UERRLOregaddr,
2005 &uerrlo_reg);
2006 pci_rd_rc2 = lpfc_readl(
2007 phba->sli4_hba.u.if_type0.UEMASKLOregaddr,
2008 &uemasklo_reg);
2009 /* consider PCI bus read error as pci_channel_offline */
2010 if (pci_rd_rc1 == -EIO && pci_rd_rc2 == -EIO)
2011 return;
65791f1f
JS
2012 if (!(phba->hba_flag & HBA_RECOVERABLE_UE)) {
2013 lpfc_sli4_offline_eratt(phba);
2014 return;
2015 }
372c187b 2016 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
2017 "7623 Checking UE recoverable");
2018
2019 for (i = 0; i < phba->sli4_hba.ue_to_sr / 1000; i++) {
2020 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
2021 &portsmphr_reg.word0))
2022 continue;
2023
2024 smphr_port_status = bf_get(lpfc_port_smphr_port_status,
2025 &portsmphr_reg);
2026 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
2027 LPFC_PORT_SEM_UE_RECOVERABLE)
2028 break;
2029 /*Sleep for 1Sec, before checking SEMAPHORE */
2030 msleep(1000);
2031 }
2032
372c187b 2033 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
2034 "4827 smphr_port_status x%x : Waited %dSec",
2035 smphr_port_status, i);
2036
2037 /* Recoverable UE, reset the HBA device */
2038 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
2039 LPFC_PORT_SEM_UE_RECOVERABLE) {
2040 for (i = 0; i < 20; i++) {
2041 msleep(1000);
2042 if (!lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
2043 &portsmphr_reg.word0) &&
2044 (LPFC_POST_STAGE_PORT_READY ==
2045 bf_get(lpfc_port_smphr_port_status,
2046 &portsmphr_reg))) {
2047 rc = lpfc_sli4_port_sta_fn_reset(phba,
2048 LPFC_MBX_NO_WAIT, en_rn_msg);
2049 if (rc == 0)
2050 return;
372c187b
DK
2051 lpfc_printf_log(phba, KERN_ERR,
2052 LOG_TRACE_EVENT,
65791f1f
JS
2053 "4215 Failed to recover UE");
2054 break;
2055 }
2056 }
2057 }
372c187b 2058 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
2059 "7624 Firmware not ready: Failing UE recovery,"
2060 " waited %dSec", i);
8c24a4f6 2061 phba->link_state = LPFC_HBA_ERROR;
2fcee4bf 2062 break;
946727dc 2063
2fcee4bf 2064 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 2065 case LPFC_SLI_INTF_IF_TYPE_6:
2e90f4b5
JS
2066 pci_rd_rc1 = lpfc_readl(
2067 phba->sli4_hba.u.if_type2.STATUSregaddr,
2068 &portstat_reg.word0);
2069 /* consider PCI bus read error as pci_channel_offline */
6b5151fd 2070 if (pci_rd_rc1 == -EIO) {
372c187b 2071 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
6b5151fd
JS
2072 "3151 PCI bus read access failure: x%x\n",
2073 readl(phba->sli4_hba.u.if_type2.STATUSregaddr));
32a93100 2074 lpfc_sli4_offline_eratt(phba);
2e90f4b5 2075 return;
6b5151fd 2076 }
2e90f4b5
JS
2077 reg_err1 = readl(phba->sli4_hba.u.if_type2.ERR1regaddr);
2078 reg_err2 = readl(phba->sli4_hba.u.if_type2.ERR2regaddr);
2fcee4bf 2079 if (bf_get(lpfc_sliport_status_oti, &portstat_reg)) {
372c187b
DK
2080 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2081 "2889 Port Overtemperature event, "
2082 "taking port offline Data: x%x x%x\n",
2083 reg_err1, reg_err2);
946727dc 2084
310429ef 2085 phba->sfp_alarm |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
946727dc
JS
2086 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
2087 temp_event_data.event_code = LPFC_CRIT_TEMP;
2088 temp_event_data.data = 0xFFFFFFFF;
2089
2090 shost = lpfc_shost_from_vport(phba->pport);
2091 fc_host_post_vendor_event(shost, fc_get_event_number(),
2092 sizeof(temp_event_data),
2093 (char *)&temp_event_data,
2094 SCSI_NL_VID_TYPE_PCI
2095 | PCI_VENDOR_ID_EMULEX);
2096
2fcee4bf
JS
2097 spin_lock_irq(&phba->hbalock);
2098 phba->over_temp_state = HBA_OVER_TEMP;
2099 spin_unlock_irq(&phba->hbalock);
2100 lpfc_sli4_offline_eratt(phba);
946727dc 2101 return;
2fcee4bf 2102 }
2e90f4b5 2103 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
e10b2022 2104 reg_err2 == SLIPORT_ERR2_REG_FW_RESTART) {
5852ed2a 2105 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
e10b2022
JS
2106 "3143 Port Down: Firmware Update "
2107 "Detected\n");
2108 en_rn_msg = false;
2109 } else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
2e90f4b5 2110 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
372c187b 2111 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2e90f4b5
JS
2112 "3144 Port Down: Debug Dump\n");
2113 else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
2114 reg_err2 == SLIPORT_ERR2_REG_FUNC_PROVISON)
372c187b 2115 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2e90f4b5 2116 "3145 Port Down: Provisioning\n");
618a5230 2117
946727dc
JS
2118 /* If resets are disabled then leave the HBA alone and return */
2119 if (!phba->cfg_enable_hba_reset)
2120 return;
2121
618a5230 2122 /* Check port status register for function reset */
e10b2022
JS
2123 rc = lpfc_sli4_port_sta_fn_reset(phba, LPFC_MBX_NO_WAIT,
2124 en_rn_msg);
618a5230
JS
2125 if (rc == 0) {
2126 /* don't report event on forced debug dump */
2127 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
2128 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
2129 return;
2130 else
2131 break;
2fcee4bf 2132 }
618a5230 2133 /* fall through for not able to recover */
372c187b 2134 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
8c24a4f6
JS
2135 "3152 Unrecoverable error\n");
2136 phba->link_state = LPFC_HBA_ERROR;
2fcee4bf
JS
2137 break;
2138 case LPFC_SLI_INTF_IF_TYPE_1:
2139 default:
2140 break;
2141 }
2e90f4b5
JS
2142 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
2143 "3123 Report dump event to upper layer\n");
2144 /* Send an internal error event to mgmt application */
2145 lpfc_board_errevt_to_mgmt(phba);
2146
2147 event_data = FC_REG_DUMP_EVENT;
2148 shost = lpfc_shost_from_vport(vport);
2149 fc_host_post_vendor_event(shost, fc_get_event_number(),
2150 sizeof(event_data), (char *) &event_data,
2151 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
da0436e9
JS
2152}
2153
2154/**
2155 * lpfc_handle_eratt - Wrapper func for handling hba error attention
2156 * @phba: pointer to lpfc HBA data structure.
2157 *
2158 * This routine wraps the actual SLI3 or SLI4 hba error attention handling
2159 * routine from the API jump table function pointer from the lpfc_hba struct.
2160 *
2161 * Return codes
af901ca1 2162 * 0 - success.
da0436e9
JS
2163 * Any other value - error.
2164 **/
2165void
2166lpfc_handle_eratt(struct lpfc_hba *phba)
2167{
2168 (*phba->lpfc_handle_eratt)(phba);
2169}
2170
e59058c4 2171/**
3621a710 2172 * lpfc_handle_latt - The HBA link event handler
e59058c4
JS
2173 * @phba: pointer to lpfc hba data structure.
2174 *
2175 * This routine is invoked from the worker thread to handle a HBA host
895427bd 2176 * attention link event. SLI3 only.
e59058c4 2177 **/
dea3101e 2178void
2e0fef85 2179lpfc_handle_latt(struct lpfc_hba *phba)
dea3101e 2180{
2e0fef85
JS
2181 struct lpfc_vport *vport = phba->pport;
2182 struct lpfc_sli *psli = &phba->sli;
dea3101e 2183 LPFC_MBOXQ_t *pmb;
2184 volatile uint32_t control;
2185 struct lpfc_dmabuf *mp;
09372820 2186 int rc = 0;
dea3101e 2187
2188 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
09372820
JS
2189 if (!pmb) {
2190 rc = 1;
dea3101e 2191 goto lpfc_handle_latt_err_exit;
09372820 2192 }
dea3101e 2193
2194 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
09372820
JS
2195 if (!mp) {
2196 rc = 2;
dea3101e 2197 goto lpfc_handle_latt_free_pmb;
09372820 2198 }
dea3101e 2199
2200 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
09372820
JS
2201 if (!mp->virt) {
2202 rc = 3;
dea3101e 2203 goto lpfc_handle_latt_free_mp;
09372820 2204 }
dea3101e 2205
6281bfe0 2206 /* Cleanup any outstanding ELS commands */
549e55cd 2207 lpfc_els_flush_all_cmd(phba);
dea3101e 2208
2209 psli->slistat.link_event++;
76a95d75
JS
2210 lpfc_read_topology(phba, pmb, mp);
2211 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
2e0fef85 2212 pmb->vport = vport;
0d2b6b83 2213 /* Block ELS IOCBs until we have processed this mbox command */
895427bd 2214 phba->sli.sli3_ring[LPFC_ELS_RING].flag |= LPFC_STOP_IOCB_EVENT;
0b727fea 2215 rc = lpfc_sli_issue_mbox (phba, pmb, MBX_NOWAIT);
09372820
JS
2216 if (rc == MBX_NOT_FINISHED) {
2217 rc = 4;
14691150 2218 goto lpfc_handle_latt_free_mbuf;
09372820 2219 }
dea3101e 2220
2221 /* Clear Link Attention in HA REG */
2e0fef85 2222 spin_lock_irq(&phba->hbalock);
dea3101e 2223 writel(HA_LATT, phba->HAregaddr);
2224 readl(phba->HAregaddr); /* flush */
2e0fef85 2225 spin_unlock_irq(&phba->hbalock);
dea3101e 2226
2227 return;
2228
14691150 2229lpfc_handle_latt_free_mbuf:
895427bd 2230 phba->sli.sli3_ring[LPFC_ELS_RING].flag &= ~LPFC_STOP_IOCB_EVENT;
14691150 2231 lpfc_mbuf_free(phba, mp->virt, mp->phys);
dea3101e 2232lpfc_handle_latt_free_mp:
2233 kfree(mp);
2234lpfc_handle_latt_free_pmb:
1dcb58e5 2235 mempool_free(pmb, phba->mbox_mem_pool);
dea3101e 2236lpfc_handle_latt_err_exit:
2237 /* Enable Link attention interrupts */
2e0fef85 2238 spin_lock_irq(&phba->hbalock);
dea3101e 2239 psli->sli_flag |= LPFC_PROCESS_LA;
2240 control = readl(phba->HCregaddr);
2241 control |= HC_LAINT_ENA;
2242 writel(control, phba->HCregaddr);
2243 readl(phba->HCregaddr); /* flush */
2244
2245 /* Clear Link Attention in HA REG */
2246 writel(HA_LATT, phba->HAregaddr);
2247 readl(phba->HAregaddr); /* flush */
2e0fef85 2248 spin_unlock_irq(&phba->hbalock);
dea3101e 2249 lpfc_linkdown(phba);
2e0fef85 2250 phba->link_state = LPFC_HBA_ERROR;
dea3101e 2251
372c187b
DK
2252 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2253 "0300 LATT: Cannot issue READ_LA: Data:%d\n", rc);
dea3101e 2254
2255 return;
2256}
2257
e59058c4 2258/**
3621a710 2259 * lpfc_parse_vpd - Parse VPD (Vital Product Data)
e59058c4
JS
2260 * @phba: pointer to lpfc hba data structure.
2261 * @vpd: pointer to the vital product data.
2262 * @len: length of the vital product data in bytes.
2263 *
2264 * This routine parses the Vital Product Data (VPD). The VPD is treated as
2265 * an array of characters. In this routine, the ModelName, ProgramType, and
2266 * ModelDesc, etc. fields of the phba data structure will be populated.
2267 *
2268 * Return codes
2269 * 0 - pointer to the VPD passed in is NULL
2270 * 1 - success
2271 **/
3772a991 2272int
2e0fef85 2273lpfc_parse_vpd(struct lpfc_hba *phba, uint8_t *vpd, int len)
dea3101e 2274{
2275 uint8_t lenlo, lenhi;
07da60c1 2276 int Length;
dea3101e 2277 int i, j;
2278 int finished = 0;
2279 int index = 0;
2280
2281 if (!vpd)
2282 return 0;
2283
2284 /* Vital Product */
ed957684 2285 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011 2286 "0455 Vital Product Data: x%x x%x x%x x%x\n",
dea3101e 2287 (uint32_t) vpd[0], (uint32_t) vpd[1], (uint32_t) vpd[2],
2288 (uint32_t) vpd[3]);
74b72a59 2289 while (!finished && (index < (len - 4))) {
dea3101e 2290 switch (vpd[index]) {
2291 case 0x82:
74b72a59 2292 case 0x91:
dea3101e 2293 index += 1;
2294 lenlo = vpd[index];
2295 index += 1;
2296 lenhi = vpd[index];
2297 index += 1;
2298 i = ((((unsigned short)lenhi) << 8) + lenlo);
2299 index += i;
2300 break;
2301 case 0x90:
2302 index += 1;
2303 lenlo = vpd[index];
2304 index += 1;
2305 lenhi = vpd[index];
2306 index += 1;
2307 Length = ((((unsigned short)lenhi) << 8) + lenlo);
74b72a59
JW
2308 if (Length > len - index)
2309 Length = len - index;
dea3101e 2310 while (Length > 0) {
2311 /* Look for Serial Number */
2312 if ((vpd[index] == 'S') && (vpd[index+1] == 'N')) {
2313 index += 2;
2314 i = vpd[index];
2315 index += 1;
2316 j = 0;
2317 Length -= (3+i);
2318 while(i--) {
2319 phba->SerialNumber[j++] = vpd[index++];
2320 if (j == 31)
2321 break;
2322 }
2323 phba->SerialNumber[j] = 0;
2324 continue;
2325 }
2326 else if ((vpd[index] == 'V') && (vpd[index+1] == '1')) {
2327 phba->vpd_flag |= VPD_MODEL_DESC;
2328 index += 2;
2329 i = vpd[index];
2330 index += 1;
2331 j = 0;
2332 Length -= (3+i);
2333 while(i--) {
2334 phba->ModelDesc[j++] = vpd[index++];
2335 if (j == 255)
2336 break;
2337 }
2338 phba->ModelDesc[j] = 0;
2339 continue;
2340 }
2341 else if ((vpd[index] == 'V') && (vpd[index+1] == '2')) {
2342 phba->vpd_flag |= VPD_MODEL_NAME;
2343 index += 2;
2344 i = vpd[index];
2345 index += 1;
2346 j = 0;
2347 Length -= (3+i);
2348 while(i--) {
2349 phba->ModelName[j++] = vpd[index++];
2350 if (j == 79)
2351 break;
2352 }
2353 phba->ModelName[j] = 0;
2354 continue;
2355 }
2356 else if ((vpd[index] == 'V') && (vpd[index+1] == '3')) {
2357 phba->vpd_flag |= VPD_PROGRAM_TYPE;
2358 index += 2;
2359 i = vpd[index];
2360 index += 1;
2361 j = 0;
2362 Length -= (3+i);
2363 while(i--) {
2364 phba->ProgramType[j++] = vpd[index++];
2365 if (j == 255)
2366 break;
2367 }
2368 phba->ProgramType[j] = 0;
2369 continue;
2370 }
2371 else if ((vpd[index] == 'V') && (vpd[index+1] == '4')) {
2372 phba->vpd_flag |= VPD_PORT;
2373 index += 2;
2374 i = vpd[index];
2375 index += 1;
2376 j = 0;
2377 Length -= (3+i);
2378 while(i--) {
cd1c8301
JS
2379 if ((phba->sli_rev == LPFC_SLI_REV4) &&
2380 (phba->sli4_hba.pport_name_sta ==
2381 LPFC_SLI4_PPNAME_GET)) {
2382 j++;
2383 index++;
2384 } else
2385 phba->Port[j++] = vpd[index++];
2386 if (j == 19)
2387 break;
dea3101e 2388 }
cd1c8301
JS
2389 if ((phba->sli_rev != LPFC_SLI_REV4) ||
2390 (phba->sli4_hba.pport_name_sta ==
2391 LPFC_SLI4_PPNAME_NON))
2392 phba->Port[j] = 0;
dea3101e 2393 continue;
2394 }
2395 else {
2396 index += 2;
2397 i = vpd[index];
2398 index += 1;
2399 index += i;
2400 Length -= (3 + i);
2401 }
2402 }
2403 finished = 0;
2404 break;
2405 case 0x78:
2406 finished = 1;
2407 break;
2408 default:
2409 index ++;
2410 break;
2411 }
74b72a59 2412 }
dea3101e 2413
2414 return(1);
2415}
2416
e59058c4 2417/**
3621a710 2418 * lpfc_get_hba_model_desc - Retrieve HBA device model name and description
e59058c4
JS
2419 * @phba: pointer to lpfc hba data structure.
2420 * @mdp: pointer to the data structure to hold the derived model name.
2421 * @descp: pointer to the data structure to hold the derived description.
2422 *
2423 * This routine retrieves HBA's description based on its registered PCI device
2424 * ID. The @descp passed into this function points to an array of 256 chars. It
2425 * shall be returned with the model name, maximum speed, and the host bus type.
2426 * The @mdp passed into this function points to an array of 80 chars. When the
2427 * function returns, the @mdp will be filled with the model name.
2428 **/
dea3101e 2429static void
2e0fef85 2430lpfc_get_hba_model_desc(struct lpfc_hba *phba, uint8_t *mdp, uint8_t *descp)
dea3101e 2431{
2432 lpfc_vpd_t *vp;
fefcb2b6 2433 uint16_t dev_id = phba->pcidev->device;
74b72a59 2434 int max_speed;
84774a4d 2435 int GE = 0;
da0436e9 2436 int oneConnect = 0; /* default is not a oneConnect */
74b72a59 2437 struct {
a747c9ce
JS
2438 char *name;
2439 char *bus;
2440 char *function;
2441 } m = {"<Unknown>", "", ""};
74b72a59
JW
2442
2443 if (mdp && mdp[0] != '\0'
2444 && descp && descp[0] != '\0')
2445 return;
2446
fbd8a6ba
JS
2447 if (phba->lmt & LMT_64Gb)
2448 max_speed = 64;
2449 else if (phba->lmt & LMT_32Gb)
d38dd52c
JS
2450 max_speed = 32;
2451 else if (phba->lmt & LMT_16Gb)
c0c11512
JS
2452 max_speed = 16;
2453 else if (phba->lmt & LMT_10Gb)
74b72a59
JW
2454 max_speed = 10;
2455 else if (phba->lmt & LMT_8Gb)
2456 max_speed = 8;
2457 else if (phba->lmt & LMT_4Gb)
2458 max_speed = 4;
2459 else if (phba->lmt & LMT_2Gb)
2460 max_speed = 2;
4169d868 2461 else if (phba->lmt & LMT_1Gb)
74b72a59 2462 max_speed = 1;
4169d868
JS
2463 else
2464 max_speed = 0;
dea3101e 2465
2466 vp = &phba->vpd;
dea3101e 2467
e4adb204 2468 switch (dev_id) {
06325e74 2469 case PCI_DEVICE_ID_FIREFLY:
12222f4f
JS
2470 m = (typeof(m)){"LP6000", "PCI",
2471 "Obsolete, Unsupported Fibre Channel Adapter"};
06325e74 2472 break;
dea3101e 2473 case PCI_DEVICE_ID_SUPERFLY:
2474 if (vp->rev.biuRev >= 1 && vp->rev.biuRev <= 3)
12222f4f 2475 m = (typeof(m)){"LP7000", "PCI", ""};
dea3101e 2476 else
12222f4f
JS
2477 m = (typeof(m)){"LP7000E", "PCI", ""};
2478 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
dea3101e 2479 break;
2480 case PCI_DEVICE_ID_DRAGONFLY:
a747c9ce 2481 m = (typeof(m)){"LP8000", "PCI",
12222f4f 2482 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2483 break;
2484 case PCI_DEVICE_ID_CENTAUR:
2485 if (FC_JEDEC_ID(vp->rev.biuRev) == CENTAUR_2G_JEDEC_ID)
12222f4f 2486 m = (typeof(m)){"LP9002", "PCI", ""};
dea3101e 2487 else
12222f4f
JS
2488 m = (typeof(m)){"LP9000", "PCI", ""};
2489 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
dea3101e 2490 break;
2491 case PCI_DEVICE_ID_RFLY:
a747c9ce 2492 m = (typeof(m)){"LP952", "PCI",
12222f4f 2493 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2494 break;
2495 case PCI_DEVICE_ID_PEGASUS:
a747c9ce 2496 m = (typeof(m)){"LP9802", "PCI-X",
12222f4f 2497 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2498 break;
2499 case PCI_DEVICE_ID_THOR:
a747c9ce 2500 m = (typeof(m)){"LP10000", "PCI-X",
12222f4f 2501 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2502 break;
2503 case PCI_DEVICE_ID_VIPER:
a747c9ce 2504 m = (typeof(m)){"LPX1000", "PCI-X",
12222f4f 2505 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2506 break;
2507 case PCI_DEVICE_ID_PFLY:
a747c9ce 2508 m = (typeof(m)){"LP982", "PCI-X",
12222f4f 2509 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2510 break;
2511 case PCI_DEVICE_ID_TFLY:
a747c9ce 2512 m = (typeof(m)){"LP1050", "PCI-X",
12222f4f 2513 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2514 break;
2515 case PCI_DEVICE_ID_HELIOS:
a747c9ce 2516 m = (typeof(m)){"LP11000", "PCI-X2",
12222f4f 2517 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2518 break;
e4adb204 2519 case PCI_DEVICE_ID_HELIOS_SCSP:
a747c9ce 2520 m = (typeof(m)){"LP11000-SP", "PCI-X2",
12222f4f 2521 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2522 break;
2523 case PCI_DEVICE_ID_HELIOS_DCSP:
a747c9ce 2524 m = (typeof(m)){"LP11002-SP", "PCI-X2",
12222f4f 2525 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2526 break;
2527 case PCI_DEVICE_ID_NEPTUNE:
12222f4f
JS
2528 m = (typeof(m)){"LPe1000", "PCIe",
2529 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2530 break;
2531 case PCI_DEVICE_ID_NEPTUNE_SCSP:
12222f4f
JS
2532 m = (typeof(m)){"LPe1000-SP", "PCIe",
2533 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2534 break;
2535 case PCI_DEVICE_ID_NEPTUNE_DCSP:
12222f4f
JS
2536 m = (typeof(m)){"LPe1002-SP", "PCIe",
2537 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204 2538 break;
dea3101e 2539 case PCI_DEVICE_ID_BMID:
a747c9ce 2540 m = (typeof(m)){"LP1150", "PCI-X2", "Fibre Channel Adapter"};
dea3101e 2541 break;
2542 case PCI_DEVICE_ID_BSMB:
12222f4f
JS
2543 m = (typeof(m)){"LP111", "PCI-X2",
2544 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2545 break;
2546 case PCI_DEVICE_ID_ZEPHYR:
a747c9ce 2547 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
dea3101e 2548 break;
e4adb204 2549 case PCI_DEVICE_ID_ZEPHYR_SCSP:
a747c9ce 2550 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
e4adb204
JSEC
2551 break;
2552 case PCI_DEVICE_ID_ZEPHYR_DCSP:
a747c9ce 2553 m = (typeof(m)){"LP2105", "PCIe", "FCoE Adapter"};
a257bf90 2554 GE = 1;
e4adb204 2555 break;
dea3101e 2556 case PCI_DEVICE_ID_ZMID:
a747c9ce 2557 m = (typeof(m)){"LPe1150", "PCIe", "Fibre Channel Adapter"};
dea3101e 2558 break;
2559 case PCI_DEVICE_ID_ZSMB:
a747c9ce 2560 m = (typeof(m)){"LPe111", "PCIe", "Fibre Channel Adapter"};
dea3101e 2561 break;
2562 case PCI_DEVICE_ID_LP101:
12222f4f
JS
2563 m = (typeof(m)){"LP101", "PCI-X",
2564 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2565 break;
2566 case PCI_DEVICE_ID_LP10000S:
12222f4f
JS
2567 m = (typeof(m)){"LP10000-S", "PCI",
2568 "Obsolete, Unsupported Fibre Channel Adapter"};
06325e74 2569 break;
e4adb204 2570 case PCI_DEVICE_ID_LP11000S:
12222f4f
JS
2571 m = (typeof(m)){"LP11000-S", "PCI-X2",
2572 "Obsolete, Unsupported Fibre Channel Adapter"};
18a3b596 2573 break;
e4adb204 2574 case PCI_DEVICE_ID_LPE11000S:
12222f4f
JS
2575 m = (typeof(m)){"LPe11000-S", "PCIe",
2576 "Obsolete, Unsupported Fibre Channel Adapter"};
5cc36b3c 2577 break;
b87eab38 2578 case PCI_DEVICE_ID_SAT:
a747c9ce 2579 m = (typeof(m)){"LPe12000", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2580 break;
2581 case PCI_DEVICE_ID_SAT_MID:
a747c9ce 2582 m = (typeof(m)){"LPe1250", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2583 break;
2584 case PCI_DEVICE_ID_SAT_SMB:
a747c9ce 2585 m = (typeof(m)){"LPe121", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2586 break;
2587 case PCI_DEVICE_ID_SAT_DCSP:
a747c9ce 2588 m = (typeof(m)){"LPe12002-SP", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2589 break;
2590 case PCI_DEVICE_ID_SAT_SCSP:
a747c9ce 2591 m = (typeof(m)){"LPe12000-SP", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2592 break;
2593 case PCI_DEVICE_ID_SAT_S:
a747c9ce 2594 m = (typeof(m)){"LPe12000-S", "PCIe", "Fibre Channel Adapter"};
b87eab38 2595 break;
84774a4d 2596 case PCI_DEVICE_ID_HORNET:
12222f4f
JS
2597 m = (typeof(m)){"LP21000", "PCIe",
2598 "Obsolete, Unsupported FCoE Adapter"};
84774a4d
JS
2599 GE = 1;
2600 break;
2601 case PCI_DEVICE_ID_PROTEUS_VF:
a747c9ce 2602 m = (typeof(m)){"LPev12000", "PCIe IOV",
12222f4f 2603 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d
JS
2604 break;
2605 case PCI_DEVICE_ID_PROTEUS_PF:
a747c9ce 2606 m = (typeof(m)){"LPev12000", "PCIe IOV",
12222f4f 2607 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d
JS
2608 break;
2609 case PCI_DEVICE_ID_PROTEUS_S:
a747c9ce 2610 m = (typeof(m)){"LPemv12002-S", "PCIe IOV",
12222f4f 2611 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d 2612 break;
da0436e9
JS
2613 case PCI_DEVICE_ID_TIGERSHARK:
2614 oneConnect = 1;
a747c9ce 2615 m = (typeof(m)){"OCe10100", "PCIe", "FCoE"};
da0436e9 2616 break;
a747c9ce 2617 case PCI_DEVICE_ID_TOMCAT:
6669f9bb 2618 oneConnect = 1;
a747c9ce
JS
2619 m = (typeof(m)){"OCe11100", "PCIe", "FCoE"};
2620 break;
2621 case PCI_DEVICE_ID_FALCON:
2622 m = (typeof(m)){"LPSe12002-ML1-E", "PCIe",
2623 "EmulexSecure Fibre"};
6669f9bb 2624 break;
98fc5dd9
JS
2625 case PCI_DEVICE_ID_BALIUS:
2626 m = (typeof(m)){"LPVe12002", "PCIe Shared I/O",
12222f4f 2627 "Obsolete, Unsupported Fibre Channel Adapter"};
98fc5dd9 2628 break;
085c647c 2629 case PCI_DEVICE_ID_LANCER_FC:
c0c11512 2630 m = (typeof(m)){"LPe16000", "PCIe", "Fibre Channel Adapter"};
085c647c 2631 break;
12222f4f
JS
2632 case PCI_DEVICE_ID_LANCER_FC_VF:
2633 m = (typeof(m)){"LPe16000", "PCIe",
2634 "Obsolete, Unsupported Fibre Channel Adapter"};
2635 break;
085c647c
JS
2636 case PCI_DEVICE_ID_LANCER_FCOE:
2637 oneConnect = 1;
079b5c91 2638 m = (typeof(m)){"OCe15100", "PCIe", "FCoE"};
085c647c 2639 break;
12222f4f
JS
2640 case PCI_DEVICE_ID_LANCER_FCOE_VF:
2641 oneConnect = 1;
2642 m = (typeof(m)){"OCe15100", "PCIe",
2643 "Obsolete, Unsupported FCoE"};
2644 break;
d38dd52c
JS
2645 case PCI_DEVICE_ID_LANCER_G6_FC:
2646 m = (typeof(m)){"LPe32000", "PCIe", "Fibre Channel Adapter"};
2647 break;
c238b9b6
JS
2648 case PCI_DEVICE_ID_LANCER_G7_FC:
2649 m = (typeof(m)){"LPe36000", "PCIe", "Fibre Channel Adapter"};
2650 break;
f449a3d7
JS
2651 case PCI_DEVICE_ID_LANCER_G7P_FC:
2652 m = (typeof(m)){"LPe38000", "PCIe", "Fibre Channel Adapter"};
2653 break;
f8cafd38
JS
2654 case PCI_DEVICE_ID_SKYHAWK:
2655 case PCI_DEVICE_ID_SKYHAWK_VF:
2656 oneConnect = 1;
2657 m = (typeof(m)){"OCe14000", "PCIe", "FCoE"};
2658 break;
5cc36b3c 2659 default:
a747c9ce 2660 m = (typeof(m)){"Unknown", "", ""};
e4adb204 2661 break;
dea3101e 2662 }
74b72a59
JW
2663
2664 if (mdp && mdp[0] == '\0')
2665 snprintf(mdp, 79,"%s", m.name);
c0c11512
JS
2666 /*
2667 * oneConnect hba requires special processing, they are all initiators
da0436e9
JS
2668 * and we put the port number on the end
2669 */
2670 if (descp && descp[0] == '\0') {
2671 if (oneConnect)
2672 snprintf(descp, 255,
4169d868 2673 "Emulex OneConnect %s, %s Initiator %s",
a747c9ce 2674 m.name, m.function,
da0436e9 2675 phba->Port);
4169d868
JS
2676 else if (max_speed == 0)
2677 snprintf(descp, 255,
290237d2 2678 "Emulex %s %s %s",
4169d868 2679 m.name, m.bus, m.function);
da0436e9
JS
2680 else
2681 snprintf(descp, 255,
2682 "Emulex %s %d%s %s %s",
a747c9ce
JS
2683 m.name, max_speed, (GE) ? "GE" : "Gb",
2684 m.bus, m.function);
da0436e9 2685 }
dea3101e 2686}
2687
e59058c4 2688/**
a680a929 2689 * lpfc_sli3_post_buffer - Post IOCB(s) with DMA buffer descriptor(s) to a IOCB ring
e59058c4
JS
2690 * @phba: pointer to lpfc hba data structure.
2691 * @pring: pointer to a IOCB ring.
2692 * @cnt: the number of IOCBs to be posted to the IOCB ring.
2693 *
2694 * This routine posts a given number of IOCBs with the associated DMA buffer
2695 * descriptors specified by the cnt argument to the given IOCB ring.
2696 *
2697 * Return codes
2698 * The number of IOCBs NOT able to be posted to the IOCB ring.
2699 **/
dea3101e 2700int
a680a929 2701lpfc_sli3_post_buffer(struct lpfc_hba *phba, struct lpfc_sli_ring *pring, int cnt)
dea3101e 2702{
2703 IOCB_t *icmd;
0bd4ca25 2704 struct lpfc_iocbq *iocb;
dea3101e 2705 struct lpfc_dmabuf *mp1, *mp2;
2706
2707 cnt += pring->missbufcnt;
2708
2709 /* While there are buffers to post */
2710 while (cnt > 0) {
2711 /* Allocate buffer for command iocb */
0bd4ca25 2712 iocb = lpfc_sli_get_iocbq(phba);
dea3101e 2713 if (iocb == NULL) {
2714 pring->missbufcnt = cnt;
2715 return cnt;
2716 }
dea3101e 2717 icmd = &iocb->iocb;
2718
2719 /* 2 buffers can be posted per command */
2720 /* Allocate buffer to post */
2721 mp1 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2722 if (mp1)
98c9ea5c
JS
2723 mp1->virt = lpfc_mbuf_alloc(phba, MEM_PRI, &mp1->phys);
2724 if (!mp1 || !mp1->virt) {
c9475cb0 2725 kfree(mp1);
604a3e30 2726 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2727 pring->missbufcnt = cnt;
2728 return cnt;
2729 }
2730
2731 INIT_LIST_HEAD(&mp1->list);
2732 /* Allocate buffer to post */
2733 if (cnt > 1) {
2734 mp2 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2735 if (mp2)
2736 mp2->virt = lpfc_mbuf_alloc(phba, MEM_PRI,
2737 &mp2->phys);
98c9ea5c 2738 if (!mp2 || !mp2->virt) {
c9475cb0 2739 kfree(mp2);
dea3101e 2740 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2741 kfree(mp1);
604a3e30 2742 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2743 pring->missbufcnt = cnt;
2744 return cnt;
2745 }
2746
2747 INIT_LIST_HEAD(&mp2->list);
2748 } else {
2749 mp2 = NULL;
2750 }
2751
2752 icmd->un.cont64[0].addrHigh = putPaddrHigh(mp1->phys);
2753 icmd->un.cont64[0].addrLow = putPaddrLow(mp1->phys);
2754 icmd->un.cont64[0].tus.f.bdeSize = FCELSSIZE;
2755 icmd->ulpBdeCount = 1;
2756 cnt--;
2757 if (mp2) {
2758 icmd->un.cont64[1].addrHigh = putPaddrHigh(mp2->phys);
2759 icmd->un.cont64[1].addrLow = putPaddrLow(mp2->phys);
2760 icmd->un.cont64[1].tus.f.bdeSize = FCELSSIZE;
2761 cnt--;
2762 icmd->ulpBdeCount = 2;
2763 }
2764
2765 icmd->ulpCommand = CMD_QUE_RING_BUF64_CN;
2766 icmd->ulpLe = 1;
2767
3772a991
JS
2768 if (lpfc_sli_issue_iocb(phba, pring->ringno, iocb, 0) ==
2769 IOCB_ERROR) {
dea3101e 2770 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2771 kfree(mp1);
2772 cnt++;
2773 if (mp2) {
2774 lpfc_mbuf_free(phba, mp2->virt, mp2->phys);
2775 kfree(mp2);
2776 cnt++;
2777 }
604a3e30 2778 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2779 pring->missbufcnt = cnt;
dea3101e 2780 return cnt;
2781 }
dea3101e 2782 lpfc_sli_ringpostbuf_put(phba, pring, mp1);
92d7f7b0 2783 if (mp2)
dea3101e 2784 lpfc_sli_ringpostbuf_put(phba, pring, mp2);
dea3101e 2785 }
2786 pring->missbufcnt = 0;
2787 return 0;
2788}
2789
e59058c4 2790/**
3621a710 2791 * lpfc_post_rcv_buf - Post the initial receive IOCB buffers to ELS ring
e59058c4
JS
2792 * @phba: pointer to lpfc hba data structure.
2793 *
2794 * This routine posts initial receive IOCB buffers to the ELS ring. The
2795 * current number of initial IOCB buffers specified by LPFC_BUF_RING0 is
895427bd 2796 * set to 64 IOCBs. SLI3 only.
e59058c4
JS
2797 *
2798 * Return codes
2799 * 0 - success (currently always success)
2800 **/
dea3101e 2801static int
2e0fef85 2802lpfc_post_rcv_buf(struct lpfc_hba *phba)
dea3101e 2803{
2804 struct lpfc_sli *psli = &phba->sli;
2805
2806 /* Ring 0, ELS / CT buffers */
a680a929 2807 lpfc_sli3_post_buffer(phba, &psli->sli3_ring[LPFC_ELS_RING], LPFC_BUF_RING0);
dea3101e 2808 /* Ring 2 - FCP no buffers needed */
2809
2810 return 0;
2811}
2812
2813#define S(N,V) (((V)<<(N))|((V)>>(32-(N))))
2814
e59058c4 2815/**
3621a710 2816 * lpfc_sha_init - Set up initial array of hash table entries
e59058c4
JS
2817 * @HashResultPointer: pointer to an array as hash table.
2818 *
2819 * This routine sets up the initial values to the array of hash table entries
2820 * for the LC HBAs.
2821 **/
dea3101e 2822static void
2823lpfc_sha_init(uint32_t * HashResultPointer)
2824{
2825 HashResultPointer[0] = 0x67452301;
2826 HashResultPointer[1] = 0xEFCDAB89;
2827 HashResultPointer[2] = 0x98BADCFE;
2828 HashResultPointer[3] = 0x10325476;
2829 HashResultPointer[4] = 0xC3D2E1F0;
2830}
2831
e59058c4 2832/**
3621a710 2833 * lpfc_sha_iterate - Iterate initial hash table with the working hash table
e59058c4
JS
2834 * @HashResultPointer: pointer to an initial/result hash table.
2835 * @HashWorkingPointer: pointer to an working hash table.
2836 *
2837 * This routine iterates an initial hash table pointed by @HashResultPointer
2838 * with the values from the working hash table pointeed by @HashWorkingPointer.
2839 * The results are putting back to the initial hash table, returned through
2840 * the @HashResultPointer as the result hash table.
2841 **/
dea3101e 2842static void
2843lpfc_sha_iterate(uint32_t * HashResultPointer, uint32_t * HashWorkingPointer)
2844{
2845 int t;
2846 uint32_t TEMP;
2847 uint32_t A, B, C, D, E;
2848 t = 16;
2849 do {
2850 HashWorkingPointer[t] =
2851 S(1,
2852 HashWorkingPointer[t - 3] ^ HashWorkingPointer[t -
2853 8] ^
2854 HashWorkingPointer[t - 14] ^ HashWorkingPointer[t - 16]);
2855 } while (++t <= 79);
2856 t = 0;
2857 A = HashResultPointer[0];
2858 B = HashResultPointer[1];
2859 C = HashResultPointer[2];
2860 D = HashResultPointer[3];
2861 E = HashResultPointer[4];
2862
2863 do {
2864 if (t < 20) {
2865 TEMP = ((B & C) | ((~B) & D)) + 0x5A827999;
2866 } else if (t < 40) {
2867 TEMP = (B ^ C ^ D) + 0x6ED9EBA1;
2868 } else if (t < 60) {
2869 TEMP = ((B & C) | (B & D) | (C & D)) + 0x8F1BBCDC;
2870 } else {
2871 TEMP = (B ^ C ^ D) + 0xCA62C1D6;
2872 }
2873 TEMP += S(5, A) + E + HashWorkingPointer[t];
2874 E = D;
2875 D = C;
2876 C = S(30, B);
2877 B = A;
2878 A = TEMP;
2879 } while (++t <= 79);
2880
2881 HashResultPointer[0] += A;
2882 HashResultPointer[1] += B;
2883 HashResultPointer[2] += C;
2884 HashResultPointer[3] += D;
2885 HashResultPointer[4] += E;
2886
2887}
2888
e59058c4 2889/**
3621a710 2890 * lpfc_challenge_key - Create challenge key based on WWPN of the HBA
e59058c4
JS
2891 * @RandomChallenge: pointer to the entry of host challenge random number array.
2892 * @HashWorking: pointer to the entry of the working hash array.
2893 *
2894 * This routine calculates the working hash array referred by @HashWorking
2895 * from the challenge random numbers associated with the host, referred by
2896 * @RandomChallenge. The result is put into the entry of the working hash
2897 * array and returned by reference through @HashWorking.
2898 **/
dea3101e 2899static void
2900lpfc_challenge_key(uint32_t * RandomChallenge, uint32_t * HashWorking)
2901{
2902 *HashWorking = (*RandomChallenge ^ *HashWorking);
2903}
2904
e59058c4 2905/**
3621a710 2906 * lpfc_hba_init - Perform special handling for LC HBA initialization
e59058c4
JS
2907 * @phba: pointer to lpfc hba data structure.
2908 * @hbainit: pointer to an array of unsigned 32-bit integers.
2909 *
2910 * This routine performs the special handling for LC HBA initialization.
2911 **/
dea3101e 2912void
2913lpfc_hba_init(struct lpfc_hba *phba, uint32_t *hbainit)
2914{
2915 int t;
2916 uint32_t *HashWorking;
2e0fef85 2917 uint32_t *pwwnn = (uint32_t *) phba->wwnn;
dea3101e 2918
bbfbbbc1 2919 HashWorking = kcalloc(80, sizeof(uint32_t), GFP_KERNEL);
dea3101e 2920 if (!HashWorking)
2921 return;
2922
dea3101e 2923 HashWorking[0] = HashWorking[78] = *pwwnn++;
2924 HashWorking[1] = HashWorking[79] = *pwwnn;
2925
2926 for (t = 0; t < 7; t++)
2927 lpfc_challenge_key(phba->RandomData + t, HashWorking + t);
2928
2929 lpfc_sha_init(hbainit);
2930 lpfc_sha_iterate(hbainit, HashWorking);
2931 kfree(HashWorking);
2932}
2933
e59058c4 2934/**
3621a710 2935 * lpfc_cleanup - Performs vport cleanups before deleting a vport
e59058c4
JS
2936 * @vport: pointer to a virtual N_Port data structure.
2937 *
2938 * This routine performs the necessary cleanups before deleting the @vport.
2939 * It invokes the discovery state machine to perform necessary state
2940 * transitions and to release the ndlps associated with the @vport. Note,
2941 * the physical port is treated as @vport 0.
2942 **/
87af33fe 2943void
2e0fef85 2944lpfc_cleanup(struct lpfc_vport *vport)
dea3101e 2945{
87af33fe 2946 struct lpfc_hba *phba = vport->phba;
dea3101e 2947 struct lpfc_nodelist *ndlp, *next_ndlp;
a8adb832 2948 int i = 0;
dea3101e 2949
87af33fe
JS
2950 if (phba->link_state > LPFC_LINK_DOWN)
2951 lpfc_port_link_failure(vport);
2952
5e633302
GS
2953 /* Clean up VMID resources */
2954 if (lpfc_is_vmid_enabled(phba))
2955 lpfc_vmid_vport_cleanup(vport);
2956
87af33fe 2957 list_for_each_entry_safe(ndlp, next_ndlp, &vport->fc_nodes, nlp_listp) {
58da1ffb
JS
2958 if (vport->port_type != LPFC_PHYSICAL_PORT &&
2959 ndlp->nlp_DID == Fabric_DID) {
2960 /* Just free up ndlp with Fabric_DID for vports */
2961 lpfc_nlp_put(ndlp);
2962 continue;
2963 }
2964
a70e63ee
JS
2965 if (ndlp->nlp_DID == Fabric_Cntl_DID &&
2966 ndlp->nlp_state == NLP_STE_UNUSED_NODE) {
eff4a01b
JS
2967 lpfc_nlp_put(ndlp);
2968 continue;
2969 }
2970
e9b11083
JS
2971 /* Fabric Ports not in UNMAPPED state are cleaned up in the
2972 * DEVICE_RM event.
2973 */
2974 if (ndlp->nlp_type & NLP_FABRIC &&
2975 ndlp->nlp_state == NLP_STE_UNMAPPED_NODE)
87af33fe
JS
2976 lpfc_disc_state_machine(vport, ndlp, NULL,
2977 NLP_EVT_DEVICE_RECOVERY);
e47c9093 2978
e9b11083
JS
2979 if (!(ndlp->fc4_xpt_flags & (NVME_XPT_REGD|SCSI_XPT_REGD)))
2980 lpfc_disc_state_machine(vport, ndlp, NULL,
2981 NLP_EVT_DEVICE_RM);
87af33fe
JS
2982 }
2983
a4691038
JS
2984 /* This is a special case flush to return all
2985 * IOs before entering this loop. There are
2986 * two points in the code where a flush is
2987 * avoided if the FC_UNLOADING flag is set.
2988 * one is in the multipool destroy,
2989 * (this prevents a crash) and the other is
2990 * in the nvme abort handler, ( also prevents
2991 * a crash). Both of these exceptions are
2992 * cases where the slot is still accessible.
2993 * The flush here is only when the pci slot
2994 * is offline.
2995 */
2996 if (vport->load_flag & FC_UNLOADING &&
2997 pci_channel_offline(phba->pcidev))
2998 lpfc_sli_flush_io_rings(vport->phba);
2999
a8adb832
JS
3000 /* At this point, ALL ndlp's should be gone
3001 * because of the previous NLP_EVT_DEVICE_RM.
3002 * Lets wait for this to happen, if needed.
3003 */
87af33fe 3004 while (!list_empty(&vport->fc_nodes)) {
a8adb832 3005 if (i++ > 3000) {
372c187b
DK
3006 lpfc_printf_vlog(vport, KERN_ERR,
3007 LOG_TRACE_EVENT,
a8adb832 3008 "0233 Nodelist not empty\n");
e47c9093
JS
3009 list_for_each_entry_safe(ndlp, next_ndlp,
3010 &vport->fc_nodes, nlp_listp) {
3011 lpfc_printf_vlog(ndlp->vport, KERN_ERR,
a4691038 3012 LOG_DISCOVERY,
e9b11083
JS
3013 "0282 did:x%x ndlp:x%px "
3014 "refcnt:%d xflags x%x nflag x%x\n",
3015 ndlp->nlp_DID, (void *)ndlp,
3016 kref_read(&ndlp->kref),
3017 ndlp->fc4_xpt_flags,
3018 ndlp->nlp_flag);
e47c9093 3019 }
a8adb832 3020 break;
87af33fe 3021 }
a8adb832
JS
3022
3023 /* Wait for any activity on ndlps to settle */
3024 msleep(10);
87af33fe 3025 }
1151e3ec 3026 lpfc_cleanup_vports_rrqs(vport, NULL);
dea3101e 3027}
3028
e59058c4 3029/**
3621a710 3030 * lpfc_stop_vport_timers - Stop all the timers associated with a vport
e59058c4
JS
3031 * @vport: pointer to a virtual N_Port data structure.
3032 *
3033 * This routine stops all the timers associated with a @vport. This function
3034 * is invoked before disabling or deleting a @vport. Note that the physical
3035 * port is treated as @vport 0.
3036 **/
92d7f7b0
JS
3037void
3038lpfc_stop_vport_timers(struct lpfc_vport *vport)
dea3101e 3039{
92d7f7b0 3040 del_timer_sync(&vport->els_tmofunc);
92494144 3041 del_timer_sync(&vport->delayed_disc_tmo);
92d7f7b0
JS
3042 lpfc_can_disctmo(vport);
3043 return;
dea3101e 3044}
3045
ecfd03c6
JS
3046/**
3047 * __lpfc_sli4_stop_fcf_redisc_wait_timer - Stop FCF rediscovery wait timer
3048 * @phba: pointer to lpfc hba data structure.
3049 *
3050 * This routine stops the SLI4 FCF rediscover wait timer if it's on. The
3051 * caller of this routine should already hold the host lock.
3052 **/
3053void
3054__lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
3055{
5ac6b303
JS
3056 /* Clear pending FCF rediscovery wait flag */
3057 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
3058
ecfd03c6
JS
3059 /* Now, try to stop the timer */
3060 del_timer(&phba->fcf.redisc_wait);
3061}
3062
3063/**
3064 * lpfc_sli4_stop_fcf_redisc_wait_timer - Stop FCF rediscovery wait timer
3065 * @phba: pointer to lpfc hba data structure.
3066 *
3067 * This routine stops the SLI4 FCF rediscover wait timer if it's on. It
3068 * checks whether the FCF rediscovery wait timer is pending with the host
3069 * lock held before proceeding with disabling the timer and clearing the
3070 * wait timer pendig flag.
3071 **/
3072void
3073lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
3074{
3075 spin_lock_irq(&phba->hbalock);
3076 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
3077 /* FCF rediscovery timer already fired or stopped */
3078 spin_unlock_irq(&phba->hbalock);
3079 return;
3080 }
3081 __lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
5ac6b303
JS
3082 /* Clear failover in progress flags */
3083 phba->fcf.fcf_flag &= ~(FCF_DEAD_DISC | FCF_ACVL_DISC);
ecfd03c6
JS
3084 spin_unlock_irq(&phba->hbalock);
3085}
3086
02243836
JS
3087/**
3088 * lpfc_cmf_stop - Stop CMF processing
3089 * @phba: pointer to lpfc hba data structure.
3090 *
3091 * This is called when the link goes down or if CMF mode is turned OFF.
3092 * It is also called when going offline or unloaded just before the
3093 * congestion info buffer is unregistered.
3094 **/
3095void
3096lpfc_cmf_stop(struct lpfc_hba *phba)
3097{
3098 int cpu;
3099 struct lpfc_cgn_stat *cgs;
3100
3101 /* We only do something if CMF is enabled */
3102 if (!phba->sli4_hba.pc_sli4_params.cmf)
3103 return;
3104
3105 lpfc_printf_log(phba, KERN_INFO, LOG_CGN_MGMT,
3106 "6221 Stop CMF / Cancel Timer\n");
3107
3108 /* Cancel the CMF timer */
3109 hrtimer_cancel(&phba->cmf_timer);
3110
3111 /* Zero CMF counters */
3112 atomic_set(&phba->cmf_busy, 0);
3113 for_each_present_cpu(cpu) {
3114 cgs = per_cpu_ptr(phba->cmf_stat, cpu);
3115 atomic64_set(&cgs->total_bytes, 0);
3116 atomic64_set(&cgs->rcv_bytes, 0);
3117 atomic_set(&cgs->rx_io_cnt, 0);
3118 atomic64_set(&cgs->rx_latency, 0);
3119 }
3120 atomic_set(&phba->cmf_bw_wait, 0);
3121
3122 /* Resume any blocked IO - Queue unblock on workqueue */
3123 queue_work(phba->wq, &phba->unblock_request_work);
3124}
3125
3126static inline uint64_t
3127lpfc_get_max_line_rate(struct lpfc_hba *phba)
3128{
3129 uint64_t rate = lpfc_sli_port_speed_get(phba);
3130
3131 return ((((unsigned long)rate) * 1024 * 1024) / 10);
3132}
3133
3134void
3135lpfc_cmf_signal_init(struct lpfc_hba *phba)
3136{
3137 lpfc_printf_log(phba, KERN_INFO, LOG_CGN_MGMT,
3138 "6223 Signal CMF init\n");
3139
3140 /* Use the new fc_linkspeed to recalculate */
3141 phba->cmf_interval_rate = LPFC_CMF_INTERVAL;
3142 phba->cmf_max_line_rate = lpfc_get_max_line_rate(phba);
3143 phba->cmf_link_byte_count = div_u64(phba->cmf_max_line_rate *
3144 phba->cmf_interval_rate, 1000);
3145 phba->cmf_max_bytes_per_interval = phba->cmf_link_byte_count;
3146
3147 /* This is a signal to firmware to sync up CMF BW with link speed */
3148 lpfc_issue_cmf_sync_wqe(phba, 0, 0);
3149}
3150
3151/**
3152 * lpfc_cmf_start - Start CMF processing
3153 * @phba: pointer to lpfc hba data structure.
3154 *
3155 * This is called when the link comes up or if CMF mode is turned OFF
3156 * to Monitor or Managed.
3157 **/
3158void
3159lpfc_cmf_start(struct lpfc_hba *phba)
3160{
3161 struct lpfc_cgn_stat *cgs;
3162 int cpu;
3163
3164 /* We only do something if CMF is enabled */
3165 if (!phba->sli4_hba.pc_sli4_params.cmf ||
3166 phba->cmf_active_mode == LPFC_CFG_OFF)
3167 return;
3168
3169 /* Reinitialize congestion buffer info */
3170 lpfc_init_congestion_buf(phba);
3171
3172 atomic_set(&phba->cgn_fabric_warn_cnt, 0);
3173 atomic_set(&phba->cgn_fabric_alarm_cnt, 0);
3174 atomic_set(&phba->cgn_sync_alarm_cnt, 0);
3175 atomic_set(&phba->cgn_sync_warn_cnt, 0);
3176
3177 atomic_set(&phba->cmf_busy, 0);
3178 for_each_present_cpu(cpu) {
3179 cgs = per_cpu_ptr(phba->cmf_stat, cpu);
3180 atomic64_set(&cgs->total_bytes, 0);
3181 atomic64_set(&cgs->rcv_bytes, 0);
3182 atomic_set(&cgs->rx_io_cnt, 0);
3183 atomic64_set(&cgs->rx_latency, 0);
3184 }
3185 phba->cmf_latency.tv_sec = 0;
3186 phba->cmf_latency.tv_nsec = 0;
3187
3188 lpfc_cmf_signal_init(phba);
3189
3190 lpfc_printf_log(phba, KERN_INFO, LOG_CGN_MGMT,
3191 "6222 Start CMF / Timer\n");
3192
3193 phba->cmf_timer_cnt = 0;
3194 hrtimer_start(&phba->cmf_timer,
3195 ktime_set(0, LPFC_CMF_INTERVAL * 1000000),
3196 HRTIMER_MODE_REL);
3197 /* Setup for latency check in IO cmpl routines */
3198 ktime_get_real_ts64(&phba->cmf_latency);
3199
3200 atomic_set(&phba->cmf_bw_wait, 0);
3201 atomic_set(&phba->cmf_stop_io, 0);
3202}
3203
e59058c4 3204/**
3772a991 3205 * lpfc_stop_hba_timers - Stop all the timers associated with an HBA
e59058c4
JS
3206 * @phba: pointer to lpfc hba data structure.
3207 *
3208 * This routine stops all the timers associated with a HBA. This function is
3209 * invoked before either putting a HBA offline or unloading the driver.
3210 **/
3772a991
JS
3211void
3212lpfc_stop_hba_timers(struct lpfc_hba *phba)
dea3101e 3213{
cdb42bec
JS
3214 if (phba->pport)
3215 lpfc_stop_vport_timers(phba->pport);
32517fc0 3216 cancel_delayed_work_sync(&phba->eq_delay_work);
317aeb83 3217 cancel_delayed_work_sync(&phba->idle_stat_delay_work);
2e0fef85 3218 del_timer_sync(&phba->sli.mbox_tmo);
92d7f7b0 3219 del_timer_sync(&phba->fabric_block_timer);
9399627f 3220 del_timer_sync(&phba->eratt_poll);
3772a991 3221 del_timer_sync(&phba->hb_tmofunc);
1151e3ec
JS
3222 if (phba->sli_rev == LPFC_SLI_REV4) {
3223 del_timer_sync(&phba->rrq_tmr);
3224 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
3225 }
a22d73b6 3226 phba->hba_flag &= ~(HBA_HBEAT_INP | HBA_HBEAT_TMO);
3772a991
JS
3227
3228 switch (phba->pci_dev_grp) {
3229 case LPFC_PCI_DEV_LP:
3230 /* Stop any LightPulse device specific driver timers */
3231 del_timer_sync(&phba->fcp_poll_timer);
3232 break;
3233 case LPFC_PCI_DEV_OC:
cc0e5f1c 3234 /* Stop any OneConnect device specific driver timers */
ecfd03c6 3235 lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
3772a991
JS
3236 break;
3237 default:
372c187b 3238 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
3239 "0297 Invalid device group (x%x)\n",
3240 phba->pci_dev_grp);
3241 break;
3242 }
2e0fef85 3243 return;
dea3101e 3244}
3245
e59058c4 3246/**
3621a710 3247 * lpfc_block_mgmt_io - Mark a HBA's management interface as blocked
e59058c4 3248 * @phba: pointer to lpfc hba data structure.
fe614acd 3249 * @mbx_action: flag for mailbox no wait action.
e59058c4
JS
3250 *
3251 * This routine marks a HBA's management interface as blocked. Once the HBA's
3252 * management interface is marked as blocked, all the user space access to
3253 * the HBA, whether they are from sysfs interface or libdfc interface will
3254 * all be blocked. The HBA is set to block the management interface when the
3255 * driver prepares the HBA interface for online or offline.
3256 **/
a6ababd2 3257static void
618a5230 3258lpfc_block_mgmt_io(struct lpfc_hba *phba, int mbx_action)
a6ababd2
AB
3259{
3260 unsigned long iflag;
6e7288d9
JS
3261 uint8_t actcmd = MBX_HEARTBEAT;
3262 unsigned long timeout;
3263
a6ababd2
AB
3264 spin_lock_irqsave(&phba->hbalock, iflag);
3265 phba->sli.sli_flag |= LPFC_BLOCK_MGMT_IO;
618a5230
JS
3266 spin_unlock_irqrestore(&phba->hbalock, iflag);
3267 if (mbx_action == LPFC_MBX_NO_WAIT)
3268 return;
3269 timeout = msecs_to_jiffies(LPFC_MBOX_TMO * 1000) + jiffies;
3270 spin_lock_irqsave(&phba->hbalock, iflag);
a183a15f 3271 if (phba->sli.mbox_active) {
6e7288d9 3272 actcmd = phba->sli.mbox_active->u.mb.mbxCommand;
a183a15f
JS
3273 /* Determine how long we might wait for the active mailbox
3274 * command to be gracefully completed by firmware.
3275 */
3276 timeout = msecs_to_jiffies(lpfc_mbox_tmo_val(phba,
3277 phba->sli.mbox_active) * 1000) + jiffies;
3278 }
a6ababd2 3279 spin_unlock_irqrestore(&phba->hbalock, iflag);
a183a15f 3280
6e7288d9
JS
3281 /* Wait for the outstnading mailbox command to complete */
3282 while (phba->sli.mbox_active) {
3283 /* Check active mailbox complete status every 2ms */
3284 msleep(2);
3285 if (time_after(jiffies, timeout)) {
372c187b
DK
3286 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3287 "2813 Mgmt IO is Blocked %x "
3288 "- mbox cmd %x still active\n",
3289 phba->sli.sli_flag, actcmd);
6e7288d9
JS
3290 break;
3291 }
3292 }
a6ababd2
AB
3293}
3294
6b5151fd
JS
3295/**
3296 * lpfc_sli4_node_prep - Assign RPIs for active nodes.
3297 * @phba: pointer to lpfc hba data structure.
3298 *
3299 * Allocate RPIs for all active remote nodes. This is needed whenever
3300 * an SLI4 adapter is reset and the driver is not unloading. Its purpose
3301 * is to fixup the temporary rpi assignments.
3302 **/
3303void
3304lpfc_sli4_node_prep(struct lpfc_hba *phba)
3305{
3306 struct lpfc_nodelist *ndlp, *next_ndlp;
3307 struct lpfc_vport **vports;
9d3d340d 3308 int i, rpi;
6b5151fd
JS
3309
3310 if (phba->sli_rev != LPFC_SLI_REV4)
3311 return;
3312
3313 vports = lpfc_create_vport_work_array(phba);
9d3d340d
JS
3314 if (vports == NULL)
3315 return;
6b5151fd 3316
9d3d340d
JS
3317 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
3318 if (vports[i]->load_flag & FC_UNLOADING)
3319 continue;
3320
3321 list_for_each_entry_safe(ndlp, next_ndlp,
3322 &vports[i]->fc_nodes,
3323 nlp_listp) {
9d3d340d
JS
3324 rpi = lpfc_sli4_alloc_rpi(phba);
3325 if (rpi == LPFC_RPI_ALLOC_ERROR) {
307e3380 3326 /* TODO print log? */
9d3d340d 3327 continue;
6b5151fd 3328 }
9d3d340d 3329 ndlp->nlp_rpi = rpi;
0f154226
JS
3330 lpfc_printf_vlog(ndlp->vport, KERN_INFO,
3331 LOG_NODE | LOG_DISCOVERY,
3332 "0009 Assign RPI x%x to ndlp x%px "
307e3380 3333 "DID:x%06x flg:x%x\n",
0f154226 3334 ndlp->nlp_rpi, ndlp, ndlp->nlp_DID,
307e3380 3335 ndlp->nlp_flag);
6b5151fd
JS
3336 }
3337 }
3338 lpfc_destroy_vport_work_array(phba, vports);
3339}
3340
c490850a
JS
3341/**
3342 * lpfc_create_expedite_pool - create expedite pool
3343 * @phba: pointer to lpfc hba data structure.
3344 *
3345 * This routine moves a batch of XRIs from lpfc_io_buf_list_put of HWQ 0
3346 * to expedite pool. Mark them as expedite.
3347 **/
3999df75 3348static void lpfc_create_expedite_pool(struct lpfc_hba *phba)
c490850a
JS
3349{
3350 struct lpfc_sli4_hdw_queue *qp;
3351 struct lpfc_io_buf *lpfc_ncmd;
3352 struct lpfc_io_buf *lpfc_ncmd_next;
3353 struct lpfc_epd_pool *epd_pool;
3354 unsigned long iflag;
3355
3356 epd_pool = &phba->epd_pool;
3357 qp = &phba->sli4_hba.hdwq[0];
3358
3359 spin_lock_init(&epd_pool->lock);
3360 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3361 spin_lock(&epd_pool->lock);
3362 INIT_LIST_HEAD(&epd_pool->list);
3363 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3364 &qp->lpfc_io_buf_list_put, list) {
3365 list_move_tail(&lpfc_ncmd->list, &epd_pool->list);
3366 lpfc_ncmd->expedite = true;
3367 qp->put_io_bufs--;
3368 epd_pool->count++;
3369 if (epd_pool->count >= XRI_BATCH)
3370 break;
3371 }
3372 spin_unlock(&epd_pool->lock);
3373 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3374}
3375
3376/**
3377 * lpfc_destroy_expedite_pool - destroy expedite pool
3378 * @phba: pointer to lpfc hba data structure.
3379 *
3380 * This routine returns XRIs from expedite pool to lpfc_io_buf_list_put
3381 * of HWQ 0. Clear the mark.
3382 **/
3999df75 3383static void lpfc_destroy_expedite_pool(struct lpfc_hba *phba)
c490850a
JS
3384{
3385 struct lpfc_sli4_hdw_queue *qp;
3386 struct lpfc_io_buf *lpfc_ncmd;
3387 struct lpfc_io_buf *lpfc_ncmd_next;
3388 struct lpfc_epd_pool *epd_pool;
3389 unsigned long iflag;
3390
3391 epd_pool = &phba->epd_pool;
3392 qp = &phba->sli4_hba.hdwq[0];
3393
3394 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3395 spin_lock(&epd_pool->lock);
3396 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3397 &epd_pool->list, list) {
3398 list_move_tail(&lpfc_ncmd->list,
3399 &qp->lpfc_io_buf_list_put);
3400 lpfc_ncmd->flags = false;
3401 qp->put_io_bufs++;
3402 epd_pool->count--;
3403 }
3404 spin_unlock(&epd_pool->lock);
3405 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3406}
3407
3408/**
3409 * lpfc_create_multixri_pools - create multi-XRI pools
3410 * @phba: pointer to lpfc hba data structure.
3411 *
3412 * This routine initialize public, private per HWQ. Then, move XRIs from
3413 * lpfc_io_buf_list_put to public pool. High and low watermark are also
3414 * Initialized.
3415 **/
3416void lpfc_create_multixri_pools(struct lpfc_hba *phba)
3417{
3418 u32 i, j;
3419 u32 hwq_count;
3420 u32 count_per_hwq;
3421 struct lpfc_io_buf *lpfc_ncmd;
3422 struct lpfc_io_buf *lpfc_ncmd_next;
3423 unsigned long iflag;
3424 struct lpfc_sli4_hdw_queue *qp;
3425 struct lpfc_multixri_pool *multixri_pool;
3426 struct lpfc_pbl_pool *pbl_pool;
3427 struct lpfc_pvt_pool *pvt_pool;
3428
3429 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3430 "1234 num_hdw_queue=%d num_present_cpu=%d common_xri_cnt=%d\n",
3431 phba->cfg_hdw_queue, phba->sli4_hba.num_present_cpu,
3432 phba->sli4_hba.io_xri_cnt);
3433
3434 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3435 lpfc_create_expedite_pool(phba);
3436
3437 hwq_count = phba->cfg_hdw_queue;
3438 count_per_hwq = phba->sli4_hba.io_xri_cnt / hwq_count;
3439
3440 for (i = 0; i < hwq_count; i++) {
3441 multixri_pool = kzalloc(sizeof(*multixri_pool), GFP_KERNEL);
3442
3443 if (!multixri_pool) {
3444 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3445 "1238 Failed to allocate memory for "
3446 "multixri_pool\n");
3447
3448 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3449 lpfc_destroy_expedite_pool(phba);
3450
3451 j = 0;
3452 while (j < i) {
3453 qp = &phba->sli4_hba.hdwq[j];
3454 kfree(qp->p_multixri_pool);
3455 j++;
3456 }
3457 phba->cfg_xri_rebalancing = 0;
3458 return;
3459 }
3460
3461 qp = &phba->sli4_hba.hdwq[i];
3462 qp->p_multixri_pool = multixri_pool;
3463
3464 multixri_pool->xri_limit = count_per_hwq;
3465 multixri_pool->rrb_next_hwqid = i;
3466
3467 /* Deal with public free xri pool */
3468 pbl_pool = &multixri_pool->pbl_pool;
3469 spin_lock_init(&pbl_pool->lock);
3470 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3471 spin_lock(&pbl_pool->lock);
3472 INIT_LIST_HEAD(&pbl_pool->list);
3473 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3474 &qp->lpfc_io_buf_list_put, list) {
3475 list_move_tail(&lpfc_ncmd->list, &pbl_pool->list);
3476 qp->put_io_bufs--;
3477 pbl_pool->count++;
3478 }
3479 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3480 "1235 Moved %d buffers from PUT list over to pbl_pool[%d]\n",
3481 pbl_pool->count, i);
3482 spin_unlock(&pbl_pool->lock);
3483 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3484
3485 /* Deal with private free xri pool */
3486 pvt_pool = &multixri_pool->pvt_pool;
3487 pvt_pool->high_watermark = multixri_pool->xri_limit / 2;
3488 pvt_pool->low_watermark = XRI_BATCH;
3489 spin_lock_init(&pvt_pool->lock);
3490 spin_lock_irqsave(&pvt_pool->lock, iflag);
3491 INIT_LIST_HEAD(&pvt_pool->list);
3492 pvt_pool->count = 0;
3493 spin_unlock_irqrestore(&pvt_pool->lock, iflag);
3494 }
3495}
3496
3497/**
3498 * lpfc_destroy_multixri_pools - destroy multi-XRI pools
3499 * @phba: pointer to lpfc hba data structure.
3500 *
3501 * This routine returns XRIs from public/private to lpfc_io_buf_list_put.
3502 **/
3999df75 3503static void lpfc_destroy_multixri_pools(struct lpfc_hba *phba)
c490850a
JS
3504{
3505 u32 i;
3506 u32 hwq_count;
3507 struct lpfc_io_buf *lpfc_ncmd;
3508 struct lpfc_io_buf *lpfc_ncmd_next;
3509 unsigned long iflag;
3510 struct lpfc_sli4_hdw_queue *qp;
3511 struct lpfc_multixri_pool *multixri_pool;
3512 struct lpfc_pbl_pool *pbl_pool;
3513 struct lpfc_pvt_pool *pvt_pool;
3514
3515 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3516 lpfc_destroy_expedite_pool(phba);
3517
c00f62e6
JS
3518 if (!(phba->pport->load_flag & FC_UNLOADING))
3519 lpfc_sli_flush_io_rings(phba);
c66a9197 3520
c490850a
JS
3521 hwq_count = phba->cfg_hdw_queue;
3522
3523 for (i = 0; i < hwq_count; i++) {
3524 qp = &phba->sli4_hba.hdwq[i];
3525 multixri_pool = qp->p_multixri_pool;
3526 if (!multixri_pool)
3527 continue;
3528
3529 qp->p_multixri_pool = NULL;
3530
3531 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3532
3533 /* Deal with public free xri pool */
3534 pbl_pool = &multixri_pool->pbl_pool;
3535 spin_lock(&pbl_pool->lock);
3536
3537 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3538 "1236 Moving %d buffers from pbl_pool[%d] TO PUT list\n",
3539 pbl_pool->count, i);
3540
3541 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3542 &pbl_pool->list, list) {
3543 list_move_tail(&lpfc_ncmd->list,
3544 &qp->lpfc_io_buf_list_put);
3545 qp->put_io_bufs++;
3546 pbl_pool->count--;
3547 }
3548
3549 INIT_LIST_HEAD(&pbl_pool->list);
3550 pbl_pool->count = 0;
3551
3552 spin_unlock(&pbl_pool->lock);
3553
3554 /* Deal with private free xri pool */
3555 pvt_pool = &multixri_pool->pvt_pool;
3556 spin_lock(&pvt_pool->lock);
3557
3558 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3559 "1237 Moving %d buffers from pvt_pool[%d] TO PUT list\n",
3560 pvt_pool->count, i);
3561
3562 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3563 &pvt_pool->list, list) {
3564 list_move_tail(&lpfc_ncmd->list,
3565 &qp->lpfc_io_buf_list_put);
3566 qp->put_io_bufs++;
3567 pvt_pool->count--;
3568 }
3569
3570 INIT_LIST_HEAD(&pvt_pool->list);
3571 pvt_pool->count = 0;
3572
3573 spin_unlock(&pvt_pool->lock);
3574 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3575
3576 kfree(multixri_pool);
3577 }
3578}
3579
e59058c4 3580/**
3621a710 3581 * lpfc_online - Initialize and bring a HBA online
e59058c4
JS
3582 * @phba: pointer to lpfc hba data structure.
3583 *
3584 * This routine initializes the HBA and brings a HBA online. During this
3585 * process, the management interface is blocked to prevent user space access
3586 * to the HBA interfering with the driver initialization.
3587 *
3588 * Return codes
3589 * 0 - successful
3590 * 1 - failed
3591 **/
dea3101e 3592int
2e0fef85 3593lpfc_online(struct lpfc_hba *phba)
dea3101e 3594{
372bd282 3595 struct lpfc_vport *vport;
549e55cd 3596 struct lpfc_vport **vports;
a145fda3 3597 int i, error = 0;
16a3a208 3598 bool vpis_cleared = false;
2e0fef85 3599
dea3101e 3600 if (!phba)
3601 return 0;
372bd282 3602 vport = phba->pport;
dea3101e 3603
2e0fef85 3604 if (!(vport->fc_flag & FC_OFFLINE_MODE))
dea3101e 3605 return 0;
3606
ed957684 3607 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
e8b62011 3608 "0458 Bring Adapter online\n");
dea3101e 3609
618a5230 3610 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
46fa311e 3611
da0436e9
JS
3612 if (phba->sli_rev == LPFC_SLI_REV4) {
3613 if (lpfc_sli4_hba_setup(phba)) { /* Initialize SLI4 HBA */
3614 lpfc_unblock_mgmt_io(phba);
3615 return 1;
3616 }
16a3a208
JS
3617 spin_lock_irq(&phba->hbalock);
3618 if (!phba->sli4_hba.max_cfg_param.vpi_used)
3619 vpis_cleared = true;
3620 spin_unlock_irq(&phba->hbalock);
a145fda3
DK
3621
3622 /* Reestablish the local initiator port.
3623 * The offline process destroyed the previous lport.
3624 */
3625 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME &&
3626 !phba->nvmet_support) {
3627 error = lpfc_nvme_create_localport(phba->pport);
3628 if (error)
372c187b 3629 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
a145fda3
DK
3630 "6132 NVME restore reg failed "
3631 "on nvmei error x%x\n", error);
3632 }
da0436e9 3633 } else {
895427bd 3634 lpfc_sli_queue_init(phba);
da0436e9
JS
3635 if (lpfc_sli_hba_setup(phba)) { /* Initialize SLI2/SLI3 HBA */
3636 lpfc_unblock_mgmt_io(phba);
3637 return 1;
3638 }
46fa311e 3639 }
dea3101e 3640
549e55cd 3641 vports = lpfc_create_vport_work_array(phba);
aeb6641f 3642 if (vports != NULL) {
da0436e9 3643 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
549e55cd
JS
3644 struct Scsi_Host *shost;
3645 shost = lpfc_shost_from_vport(vports[i]);
3646 spin_lock_irq(shost->host_lock);
3647 vports[i]->fc_flag &= ~FC_OFFLINE_MODE;
3648 if (phba->sli3_options & LPFC_SLI3_NPIV_ENABLED)
3649 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
16a3a208 3650 if (phba->sli_rev == LPFC_SLI_REV4) {
1c6834a7 3651 vports[i]->fc_flag |= FC_VPORT_NEEDS_INIT_VPI;
16a3a208
JS
3652 if ((vpis_cleared) &&
3653 (vports[i]->port_type !=
3654 LPFC_PHYSICAL_PORT))
3655 vports[i]->vpi = 0;
3656 }
549e55cd
JS
3657 spin_unlock_irq(shost->host_lock);
3658 }
aeb6641f
AB
3659 }
3660 lpfc_destroy_vport_work_array(phba, vports);
dea3101e 3661
c490850a
JS
3662 if (phba->cfg_xri_rebalancing)
3663 lpfc_create_multixri_pools(phba);
3664
93a4d6f4
JS
3665 lpfc_cpuhp_add(phba);
3666
46fa311e 3667 lpfc_unblock_mgmt_io(phba);
dea3101e 3668 return 0;
3669}
3670
e59058c4 3671/**
3621a710 3672 * lpfc_unblock_mgmt_io - Mark a HBA's management interface to be not blocked
e59058c4
JS
3673 * @phba: pointer to lpfc hba data structure.
3674 *
3675 * This routine marks a HBA's management interface as not blocked. Once the
3676 * HBA's management interface is marked as not blocked, all the user space
3677 * access to the HBA, whether they are from sysfs interface or libdfc
3678 * interface will be allowed. The HBA is set to block the management interface
3679 * when the driver prepares the HBA interface for online or offline and then
3680 * set to unblock the management interface afterwards.
3681 **/
46fa311e
JS
3682void
3683lpfc_unblock_mgmt_io(struct lpfc_hba * phba)
3684{
3685 unsigned long iflag;
3686
2e0fef85
JS
3687 spin_lock_irqsave(&phba->hbalock, iflag);
3688 phba->sli.sli_flag &= ~LPFC_BLOCK_MGMT_IO;
3689 spin_unlock_irqrestore(&phba->hbalock, iflag);
46fa311e
JS
3690}
3691
e59058c4 3692/**
3621a710 3693 * lpfc_offline_prep - Prepare a HBA to be brought offline
e59058c4 3694 * @phba: pointer to lpfc hba data structure.
fe614acd 3695 * @mbx_action: flag for mailbox shutdown action.
e59058c4
JS
3696 *
3697 * This routine is invoked to prepare a HBA to be brought offline. It performs
3698 * unregistration login to all the nodes on all vports and flushes the mailbox
3699 * queue to make it ready to be brought offline.
3700 **/
46fa311e 3701void
618a5230 3702lpfc_offline_prep(struct lpfc_hba *phba, int mbx_action)
46fa311e 3703{
2e0fef85 3704 struct lpfc_vport *vport = phba->pport;
46fa311e 3705 struct lpfc_nodelist *ndlp, *next_ndlp;
87af33fe 3706 struct lpfc_vport **vports;
72100cc4 3707 struct Scsi_Host *shost;
87af33fe 3708 int i;
35ed9613
JS
3709 int offline;
3710 bool hba_pci_err;
dea3101e 3711
2e0fef85 3712 if (vport->fc_flag & FC_OFFLINE_MODE)
46fa311e 3713 return;
dea3101e 3714
618a5230 3715 lpfc_block_mgmt_io(phba, mbx_action);
dea3101e 3716
3717 lpfc_linkdown(phba);
3718
25ac2c97 3719 offline = pci_channel_offline(phba->pcidev);
35ed9613 3720 hba_pci_err = test_bit(HBA_PCI_ERR, &phba->bit_flags);
25ac2c97 3721
87af33fe
JS
3722 /* Issue an unreg_login to all nodes on all vports */
3723 vports = lpfc_create_vport_work_array(phba);
3724 if (vports != NULL) {
da0436e9 3725 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
a8adb832
JS
3726 if (vports[i]->load_flag & FC_UNLOADING)
3727 continue;
72100cc4
JS
3728 shost = lpfc_shost_from_vport(vports[i]);
3729 spin_lock_irq(shost->host_lock);
c868595d 3730 vports[i]->vpi_state &= ~LPFC_VPI_REGISTERED;
695a814e
JS
3731 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
3732 vports[i]->fc_flag &= ~FC_VFI_REGISTERED;
72100cc4 3733 spin_unlock_irq(shost->host_lock);
695a814e 3734
87af33fe
JS
3735 shost = lpfc_shost_from_vport(vports[i]);
3736 list_for_each_entry_safe(ndlp, next_ndlp,
3737 &vports[i]->fc_nodes,
3738 nlp_listp) {
0f154226 3739
c6adba15 3740 spin_lock_irq(&ndlp->lock);
87af33fe 3741 ndlp->nlp_flag &= ~NLP_NPR_ADISC;
c6adba15 3742 spin_unlock_irq(&ndlp->lock);
affbe244 3743
35ed9613 3744 if (offline || hba_pci_err) {
25ac2c97
JS
3745 spin_lock_irq(&ndlp->lock);
3746 ndlp->nlp_flag &= ~(NLP_UNREG_INP |
3747 NLP_RPI_REGISTERED);
3748 spin_unlock_irq(&ndlp->lock);
35ed9613
JS
3749 if (phba->sli_rev == LPFC_SLI_REV4)
3750 lpfc_sli_rpi_release(vports[i],
3751 ndlp);
25ac2c97
JS
3752 } else {
3753 lpfc_unreg_rpi(vports[i], ndlp);
3754 }
6b5151fd
JS
3755 /*
3756 * Whenever an SLI4 port goes offline, free the
401ee0c1
JS
3757 * RPI. Get a new RPI when the adapter port
3758 * comes back online.
6b5151fd 3759 */
be6bb941 3760 if (phba->sli_rev == LPFC_SLI_REV4) {
e9b11083 3761 lpfc_printf_vlog(vports[i], KERN_INFO,
0f154226
JS
3762 LOG_NODE | LOG_DISCOVERY,
3763 "0011 Free RPI x%x on "
f1156125 3764 "ndlp: x%px did x%x\n",
0f154226 3765 ndlp->nlp_rpi, ndlp,
307e3380 3766 ndlp->nlp_DID);
6b5151fd 3767 lpfc_sli4_free_rpi(phba, ndlp->nlp_rpi);
0f154226 3768 ndlp->nlp_rpi = LPFC_RPI_ALLOC_ERROR;
be6bb941 3769 }
307e3380
JS
3770
3771 if (ndlp->nlp_type & NLP_FABRIC) {
3772 lpfc_disc_state_machine(vports[i], ndlp,
3773 NULL, NLP_EVT_DEVICE_RECOVERY);
e9b11083 3774
af984c87 3775 /* Don't remove the node unless the node
e9b11083 3776 * has been unregistered with the
af984c87
JS
3777 * transport, and we're not in recovery
3778 * before dev_loss_tmo triggered.
3779 * Otherwise, let dev_loss take care of
3780 * the node.
e9b11083 3781 */
af984c87
JS
3782 if (!(ndlp->save_flags &
3783 NLP_IN_RECOV_POST_DEV_LOSS) &&
3784 !(ndlp->fc4_xpt_flags &
e9b11083
JS
3785 (NVME_XPT_REGD | SCSI_XPT_REGD)))
3786 lpfc_disc_state_machine
3787 (vports[i], ndlp,
3788 NULL,
3789 NLP_EVT_DEVICE_RM);
307e3380 3790 }
87af33fe
JS
3791 }
3792 }
3793 }
09372820 3794 lpfc_destroy_vport_work_array(phba, vports);
dea3101e 3795
618a5230 3796 lpfc_sli_mbox_sys_shutdown(phba, mbx_action);
f485c18d
DK
3797
3798 if (phba->wq)
3799 flush_workqueue(phba->wq);
46fa311e
JS
3800}
3801
e59058c4 3802/**
3621a710 3803 * lpfc_offline - Bring a HBA offline
e59058c4
JS
3804 * @phba: pointer to lpfc hba data structure.
3805 *
3806 * This routine actually brings a HBA offline. It stops all the timers
3807 * associated with the HBA, brings down the SLI layer, and eventually
3808 * marks the HBA as in offline state for the upper layer protocol.
3809 **/
46fa311e 3810void
2e0fef85 3811lpfc_offline(struct lpfc_hba *phba)
46fa311e 3812{
549e55cd
JS
3813 struct Scsi_Host *shost;
3814 struct lpfc_vport **vports;
3815 int i;
46fa311e 3816
549e55cd 3817 if (phba->pport->fc_flag & FC_OFFLINE_MODE)
46fa311e 3818 return;
688a8863 3819
da0436e9
JS
3820 /* stop port and all timers associated with this hba */
3821 lpfc_stop_port(phba);
4b40d02b
DK
3822
3823 /* Tear down the local and target port registrations. The
3824 * nvme transports need to cleanup.
3825 */
3826 lpfc_nvmet_destroy_targetport(phba);
3827 lpfc_nvme_destroy_localport(phba->pport);
3828
51ef4c26
JS
3829 vports = lpfc_create_vport_work_array(phba);
3830 if (vports != NULL)
da0436e9 3831 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
51ef4c26 3832 lpfc_stop_vport_timers(vports[i]);
09372820 3833 lpfc_destroy_vport_work_array(phba, vports);
92d7f7b0 3834 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
e8b62011 3835 "0460 Bring Adapter offline\n");
dea3101e 3836 /* Bring down the SLI Layer and cleanup. The HBA is offline
3837 now. */
3838 lpfc_sli_hba_down(phba);
92d7f7b0 3839 spin_lock_irq(&phba->hbalock);
7054a606 3840 phba->work_ha = 0;
92d7f7b0 3841 spin_unlock_irq(&phba->hbalock);
549e55cd
JS
3842 vports = lpfc_create_vport_work_array(phba);
3843 if (vports != NULL)
da0436e9 3844 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
549e55cd 3845 shost = lpfc_shost_from_vport(vports[i]);
549e55cd
JS
3846 spin_lock_irq(shost->host_lock);
3847 vports[i]->work_port_events = 0;
3848 vports[i]->fc_flag |= FC_OFFLINE_MODE;
3849 spin_unlock_irq(shost->host_lock);
3850 }
09372820 3851 lpfc_destroy_vport_work_array(phba, vports);
f0871ab6
JS
3852 /* If OFFLINE flag is clear (i.e. unloading), cpuhp removal is handled
3853 * in hba_unset
3854 */
3855 if (phba->pport->fc_flag & FC_OFFLINE_MODE)
3856 __lpfc_cpuhp_remove(phba);
c490850a
JS
3857
3858 if (phba->cfg_xri_rebalancing)
3859 lpfc_destroy_multixri_pools(phba);
dea3101e 3860}
3861
e59058c4 3862/**
3621a710 3863 * lpfc_scsi_free - Free all the SCSI buffers and IOCBs from driver lists
e59058c4
JS
3864 * @phba: pointer to lpfc hba data structure.
3865 *
3866 * This routine is to free all the SCSI buffers and IOCBs from the driver
3867 * list back to kernel. It is called from lpfc_pci_remove_one to free
3868 * the internal resources before the device is removed from the system.
e59058c4 3869 **/
8a9d2e80 3870static void
2e0fef85 3871lpfc_scsi_free(struct lpfc_hba *phba)
dea3101e 3872{
c490850a 3873 struct lpfc_io_buf *sb, *sb_next;
dea3101e 3874
895427bd
JS
3875 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
3876 return;
3877
2e0fef85 3878 spin_lock_irq(&phba->hbalock);
a40fc5f0 3879
dea3101e 3880 /* Release all the lpfc_scsi_bufs maintained by this host. */
a40fc5f0
JS
3881
3882 spin_lock(&phba->scsi_buf_list_put_lock);
3883 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_put,
3884 list) {
dea3101e 3885 list_del(&sb->list);
771db5c0 3886 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
92d7f7b0 3887 sb->dma_handle);
dea3101e 3888 kfree(sb);
3889 phba->total_scsi_bufs--;
3890 }
a40fc5f0
JS
3891 spin_unlock(&phba->scsi_buf_list_put_lock);
3892
3893 spin_lock(&phba->scsi_buf_list_get_lock);
3894 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_get,
3895 list) {
dea3101e 3896 list_del(&sb->list);
771db5c0 3897 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
92d7f7b0 3898 sb->dma_handle);
dea3101e 3899 kfree(sb);
3900 phba->total_scsi_bufs--;
3901 }
a40fc5f0 3902 spin_unlock(&phba->scsi_buf_list_get_lock);
2e0fef85 3903 spin_unlock_irq(&phba->hbalock);
8a9d2e80 3904}
0794d601 3905
895427bd 3906/**
5e5b511d 3907 * lpfc_io_free - Free all the IO buffers and IOCBs from driver lists
895427bd
JS
3908 * @phba: pointer to lpfc hba data structure.
3909 *
0794d601 3910 * This routine is to free all the IO buffers and IOCBs from the driver
895427bd
JS
3911 * list back to kernel. It is called from lpfc_pci_remove_one to free
3912 * the internal resources before the device is removed from the system.
3913 **/
c490850a 3914void
5e5b511d 3915lpfc_io_free(struct lpfc_hba *phba)
895427bd 3916{
c490850a 3917 struct lpfc_io_buf *lpfc_ncmd, *lpfc_ncmd_next;
5e5b511d
JS
3918 struct lpfc_sli4_hdw_queue *qp;
3919 int idx;
895427bd 3920
5e5b511d
JS
3921 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3922 qp = &phba->sli4_hba.hdwq[idx];
3923 /* Release all the lpfc_nvme_bufs maintained by this host. */
3924 spin_lock(&qp->io_buf_list_put_lock);
3925 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3926 &qp->lpfc_io_buf_list_put,
3927 list) {
3928 list_del(&lpfc_ncmd->list);
3929 qp->put_io_bufs--;
3930 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3931 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
d79c9e9d
JS
3932 if (phba->cfg_xpsgl && !phba->nvmet_support)
3933 lpfc_put_sgl_per_hdwq(phba, lpfc_ncmd);
3934 lpfc_put_cmd_rsp_buf_per_hdwq(phba, lpfc_ncmd);
5e5b511d
JS
3935 kfree(lpfc_ncmd);
3936 qp->total_io_bufs--;
3937 }
3938 spin_unlock(&qp->io_buf_list_put_lock);
3939
3940 spin_lock(&qp->io_buf_list_get_lock);
3941 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3942 &qp->lpfc_io_buf_list_get,
3943 list) {
3944 list_del(&lpfc_ncmd->list);
3945 qp->get_io_bufs--;
3946 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3947 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
d79c9e9d
JS
3948 if (phba->cfg_xpsgl && !phba->nvmet_support)
3949 lpfc_put_sgl_per_hdwq(phba, lpfc_ncmd);
3950 lpfc_put_cmd_rsp_buf_per_hdwq(phba, lpfc_ncmd);
5e5b511d
JS
3951 kfree(lpfc_ncmd);
3952 qp->total_io_bufs--;
3953 }
3954 spin_unlock(&qp->io_buf_list_get_lock);
895427bd 3955 }
895427bd 3956}
0794d601 3957
8a9d2e80 3958/**
895427bd 3959 * lpfc_sli4_els_sgl_update - update ELS xri-sgl sizing and mapping
8a9d2e80
JS
3960 * @phba: pointer to lpfc hba data structure.
3961 *
3962 * This routine first calculates the sizes of the current els and allocated
3963 * scsi sgl lists, and then goes through all sgls to updates the physical
3964 * XRIs assigned due to port function reset. During port initialization, the
3965 * current els and allocated scsi sgl lists are 0s.
3966 *
3967 * Return codes
3968 * 0 - successful (for now, it always returns 0)
3969 **/
3970int
895427bd 3971lpfc_sli4_els_sgl_update(struct lpfc_hba *phba)
8a9d2e80
JS
3972{
3973 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
895427bd 3974 uint16_t i, lxri, xri_cnt, els_xri_cnt;
8a9d2e80 3975 LIST_HEAD(els_sgl_list);
8a9d2e80
JS
3976 int rc;
3977
3978 /*
3979 * update on pci function's els xri-sgl list
3980 */
3981 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
895427bd 3982
8a9d2e80
JS
3983 if (els_xri_cnt > phba->sli4_hba.els_xri_cnt) {
3984 /* els xri-sgl expanded */
3985 xri_cnt = els_xri_cnt - phba->sli4_hba.els_xri_cnt;
3986 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3987 "3157 ELS xri-sgl count increased from "
3988 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3989 els_xri_cnt);
3990 /* allocate the additional els sgls */
3991 for (i = 0; i < xri_cnt; i++) {
3992 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3993 GFP_KERNEL);
3994 if (sglq_entry == NULL) {
372c187b
DK
3995 lpfc_printf_log(phba, KERN_ERR,
3996 LOG_TRACE_EVENT,
8a9d2e80
JS
3997 "2562 Failure to allocate an "
3998 "ELS sgl entry:%d\n", i);
3999 rc = -ENOMEM;
4000 goto out_free_mem;
4001 }
4002 sglq_entry->buff_type = GEN_BUFF_TYPE;
4003 sglq_entry->virt = lpfc_mbuf_alloc(phba, 0,
4004 &sglq_entry->phys);
4005 if (sglq_entry->virt == NULL) {
4006 kfree(sglq_entry);
372c187b
DK
4007 lpfc_printf_log(phba, KERN_ERR,
4008 LOG_TRACE_EVENT,
8a9d2e80
JS
4009 "2563 Failure to allocate an "
4010 "ELS mbuf:%d\n", i);
4011 rc = -ENOMEM;
4012 goto out_free_mem;
4013 }
4014 sglq_entry->sgl = sglq_entry->virt;
4015 memset(sglq_entry->sgl, 0, LPFC_BPL_SIZE);
4016 sglq_entry->state = SGL_FREED;
4017 list_add_tail(&sglq_entry->list, &els_sgl_list);
4018 }
a789241e 4019 spin_lock_irq(&phba->sli4_hba.sgl_list_lock);
895427bd
JS
4020 list_splice_init(&els_sgl_list,
4021 &phba->sli4_hba.lpfc_els_sgl_list);
a789241e 4022 spin_unlock_irq(&phba->sli4_hba.sgl_list_lock);
8a9d2e80
JS
4023 } else if (els_xri_cnt < phba->sli4_hba.els_xri_cnt) {
4024 /* els xri-sgl shrinked */
4025 xri_cnt = phba->sli4_hba.els_xri_cnt - els_xri_cnt;
4026 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4027 "3158 ELS xri-sgl count decreased from "
4028 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
4029 els_xri_cnt);
a789241e 4030 spin_lock_irq(&phba->sli4_hba.sgl_list_lock);
895427bd
JS
4031 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list,
4032 &els_sgl_list);
8a9d2e80
JS
4033 /* release extra els sgls from list */
4034 for (i = 0; i < xri_cnt; i++) {
4035 list_remove_head(&els_sgl_list,
4036 sglq_entry, struct lpfc_sglq, list);
4037 if (sglq_entry) {
895427bd
JS
4038 __lpfc_mbuf_free(phba, sglq_entry->virt,
4039 sglq_entry->phys);
8a9d2e80
JS
4040 kfree(sglq_entry);
4041 }
4042 }
895427bd
JS
4043 list_splice_init(&els_sgl_list,
4044 &phba->sli4_hba.lpfc_els_sgl_list);
a789241e 4045 spin_unlock_irq(&phba->sli4_hba.sgl_list_lock);
8a9d2e80
JS
4046 } else
4047 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4048 "3163 ELS xri-sgl count unchanged: %d\n",
4049 els_xri_cnt);
4050 phba->sli4_hba.els_xri_cnt = els_xri_cnt;
4051
4052 /* update xris to els sgls on the list */
4053 sglq_entry = NULL;
4054 sglq_entry_next = NULL;
4055 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
895427bd 4056 &phba->sli4_hba.lpfc_els_sgl_list, list) {
8a9d2e80
JS
4057 lxri = lpfc_sli4_next_xritag(phba);
4058 if (lxri == NO_XRI) {
372c187b
DK
4059 lpfc_printf_log(phba, KERN_ERR,
4060 LOG_TRACE_EVENT,
8a9d2e80
JS
4061 "2400 Failed to allocate xri for "
4062 "ELS sgl\n");
4063 rc = -ENOMEM;
4064 goto out_free_mem;
4065 }
4066 sglq_entry->sli4_lxritag = lxri;
4067 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
4068 }
895427bd
JS
4069 return 0;
4070
4071out_free_mem:
4072 lpfc_free_els_sgl_list(phba);
4073 return rc;
4074}
4075
f358dd0c
JS
4076/**
4077 * lpfc_sli4_nvmet_sgl_update - update xri-sgl sizing and mapping
4078 * @phba: pointer to lpfc hba data structure.
4079 *
4080 * This routine first calculates the sizes of the current els and allocated
4081 * scsi sgl lists, and then goes through all sgls to updates the physical
4082 * XRIs assigned due to port function reset. During port initialization, the
4083 * current els and allocated scsi sgl lists are 0s.
4084 *
4085 * Return codes
4086 * 0 - successful (for now, it always returns 0)
4087 **/
4088int
4089lpfc_sli4_nvmet_sgl_update(struct lpfc_hba *phba)
4090{
4091 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
4092 uint16_t i, lxri, xri_cnt, els_xri_cnt;
6c621a22 4093 uint16_t nvmet_xri_cnt;
f358dd0c
JS
4094 LIST_HEAD(nvmet_sgl_list);
4095 int rc;
4096
4097 /*
4098 * update on pci function's nvmet xri-sgl list
4099 */
4100 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
61f3d4bf 4101
6c621a22
JS
4102 /* For NVMET, ALL remaining XRIs are dedicated for IO processing */
4103 nvmet_xri_cnt = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
f358dd0c
JS
4104 if (nvmet_xri_cnt > phba->sli4_hba.nvmet_xri_cnt) {
4105 /* els xri-sgl expanded */
4106 xri_cnt = nvmet_xri_cnt - phba->sli4_hba.nvmet_xri_cnt;
4107 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4108 "6302 NVMET xri-sgl cnt grew from %d to %d\n",
4109 phba->sli4_hba.nvmet_xri_cnt, nvmet_xri_cnt);
4110 /* allocate the additional nvmet sgls */
4111 for (i = 0; i < xri_cnt; i++) {
4112 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
4113 GFP_KERNEL);
4114 if (sglq_entry == NULL) {
372c187b
DK
4115 lpfc_printf_log(phba, KERN_ERR,
4116 LOG_TRACE_EVENT,
f358dd0c
JS
4117 "6303 Failure to allocate an "
4118 "NVMET sgl entry:%d\n", i);
4119 rc = -ENOMEM;
4120 goto out_free_mem;
4121 }
4122 sglq_entry->buff_type = NVMET_BUFF_TYPE;
4123 sglq_entry->virt = lpfc_nvmet_buf_alloc(phba, 0,
4124 &sglq_entry->phys);
4125 if (sglq_entry->virt == NULL) {
4126 kfree(sglq_entry);
372c187b
DK
4127 lpfc_printf_log(phba, KERN_ERR,
4128 LOG_TRACE_EVENT,
f358dd0c
JS
4129 "6304 Failure to allocate an "
4130 "NVMET buf:%d\n", i);
4131 rc = -ENOMEM;
4132 goto out_free_mem;
4133 }
4134 sglq_entry->sgl = sglq_entry->virt;
4135 memset(sglq_entry->sgl, 0,
4136 phba->cfg_sg_dma_buf_size);
4137 sglq_entry->state = SGL_FREED;
4138 list_add_tail(&sglq_entry->list, &nvmet_sgl_list);
4139 }
4140 spin_lock_irq(&phba->hbalock);
4141 spin_lock(&phba->sli4_hba.sgl_list_lock);
4142 list_splice_init(&nvmet_sgl_list,
4143 &phba->sli4_hba.lpfc_nvmet_sgl_list);
4144 spin_unlock(&phba->sli4_hba.sgl_list_lock);
4145 spin_unlock_irq(&phba->hbalock);
4146 } else if (nvmet_xri_cnt < phba->sli4_hba.nvmet_xri_cnt) {
4147 /* nvmet xri-sgl shrunk */
4148 xri_cnt = phba->sli4_hba.nvmet_xri_cnt - nvmet_xri_cnt;
4149 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4150 "6305 NVMET xri-sgl count decreased from "
4151 "%d to %d\n", phba->sli4_hba.nvmet_xri_cnt,
4152 nvmet_xri_cnt);
4153 spin_lock_irq(&phba->hbalock);
4154 spin_lock(&phba->sli4_hba.sgl_list_lock);
4155 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list,
4156 &nvmet_sgl_list);
4157 /* release extra nvmet sgls from list */
4158 for (i = 0; i < xri_cnt; i++) {
4159 list_remove_head(&nvmet_sgl_list,
4160 sglq_entry, struct lpfc_sglq, list);
4161 if (sglq_entry) {
4162 lpfc_nvmet_buf_free(phba, sglq_entry->virt,
4163 sglq_entry->phys);
4164 kfree(sglq_entry);
4165 }
4166 }
4167 list_splice_init(&nvmet_sgl_list,
4168 &phba->sli4_hba.lpfc_nvmet_sgl_list);
4169 spin_unlock(&phba->sli4_hba.sgl_list_lock);
4170 spin_unlock_irq(&phba->hbalock);
4171 } else
4172 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
4173 "6306 NVMET xri-sgl count unchanged: %d\n",
4174 nvmet_xri_cnt);
4175 phba->sli4_hba.nvmet_xri_cnt = nvmet_xri_cnt;
4176
4177 /* update xris to nvmet sgls on the list */
4178 sglq_entry = NULL;
4179 sglq_entry_next = NULL;
4180 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
4181 &phba->sli4_hba.lpfc_nvmet_sgl_list, list) {
4182 lxri = lpfc_sli4_next_xritag(phba);
4183 if (lxri == NO_XRI) {
372c187b
DK
4184 lpfc_printf_log(phba, KERN_ERR,
4185 LOG_TRACE_EVENT,
f358dd0c
JS
4186 "6307 Failed to allocate xri for "
4187 "NVMET sgl\n");
4188 rc = -ENOMEM;
4189 goto out_free_mem;
4190 }
4191 sglq_entry->sli4_lxritag = lxri;
4192 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
4193 }
4194 return 0;
4195
4196out_free_mem:
4197 lpfc_free_nvmet_sgl_list(phba);
4198 return rc;
4199}
4200
5e5b511d
JS
4201int
4202lpfc_io_buf_flush(struct lpfc_hba *phba, struct list_head *cbuf)
4203{
4204 LIST_HEAD(blist);
4205 struct lpfc_sli4_hdw_queue *qp;
c490850a
JS
4206 struct lpfc_io_buf *lpfc_cmd;
4207 struct lpfc_io_buf *iobufp, *prev_iobufp;
5e5b511d
JS
4208 int idx, cnt, xri, inserted;
4209
4210 cnt = 0;
4211 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
4212 qp = &phba->sli4_hba.hdwq[idx];
4213 spin_lock_irq(&qp->io_buf_list_get_lock);
4214 spin_lock(&qp->io_buf_list_put_lock);
4215
4216 /* Take everything off the get and put lists */
4217 list_splice_init(&qp->lpfc_io_buf_list_get, &blist);
4218 list_splice(&qp->lpfc_io_buf_list_put, &blist);
4219 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_get);
4220 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_put);
4221 cnt += qp->get_io_bufs + qp->put_io_bufs;
4222 qp->get_io_bufs = 0;
4223 qp->put_io_bufs = 0;
4224 qp->total_io_bufs = 0;
4225 spin_unlock(&qp->io_buf_list_put_lock);
4226 spin_unlock_irq(&qp->io_buf_list_get_lock);
4227 }
4228
4229 /*
4230 * Take IO buffers off blist and put on cbuf sorted by XRI.
4231 * This is because POST_SGL takes a sequential range of XRIs
4232 * to post to the firmware.
4233 */
4234 for (idx = 0; idx < cnt; idx++) {
c490850a 4235 list_remove_head(&blist, lpfc_cmd, struct lpfc_io_buf, list);
5e5b511d
JS
4236 if (!lpfc_cmd)
4237 return cnt;
4238 if (idx == 0) {
4239 list_add_tail(&lpfc_cmd->list, cbuf);
4240 continue;
4241 }
4242 xri = lpfc_cmd->cur_iocbq.sli4_xritag;
4243 inserted = 0;
4244 prev_iobufp = NULL;
4245 list_for_each_entry(iobufp, cbuf, list) {
4246 if (xri < iobufp->cur_iocbq.sli4_xritag) {
4247 if (prev_iobufp)
4248 list_add(&lpfc_cmd->list,
4249 &prev_iobufp->list);
4250 else
4251 list_add(&lpfc_cmd->list, cbuf);
4252 inserted = 1;
4253 break;
4254 }
4255 prev_iobufp = iobufp;
4256 }
4257 if (!inserted)
4258 list_add_tail(&lpfc_cmd->list, cbuf);
4259 }
4260 return cnt;
4261}
4262
4263int
4264lpfc_io_buf_replenish(struct lpfc_hba *phba, struct list_head *cbuf)
4265{
4266 struct lpfc_sli4_hdw_queue *qp;
c490850a 4267 struct lpfc_io_buf *lpfc_cmd;
5e5b511d
JS
4268 int idx, cnt;
4269
4270 qp = phba->sli4_hba.hdwq;
4271 cnt = 0;
4272 while (!list_empty(cbuf)) {
4273 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
4274 list_remove_head(cbuf, lpfc_cmd,
c490850a 4275 struct lpfc_io_buf, list);
5e5b511d
JS
4276 if (!lpfc_cmd)
4277 return cnt;
4278 cnt++;
4279 qp = &phba->sli4_hba.hdwq[idx];
1fbf9742
JS
4280 lpfc_cmd->hdwq_no = idx;
4281 lpfc_cmd->hdwq = qp;
a680a929 4282 lpfc_cmd->cur_iocbq.cmd_cmpl = NULL;
5e5b511d
JS
4283 spin_lock(&qp->io_buf_list_put_lock);
4284 list_add_tail(&lpfc_cmd->list,
4285 &qp->lpfc_io_buf_list_put);
4286 qp->put_io_bufs++;
4287 qp->total_io_bufs++;
4288 spin_unlock(&qp->io_buf_list_put_lock);
4289 }
4290 }
4291 return cnt;
4292}
4293
895427bd 4294/**
5e5b511d 4295 * lpfc_sli4_io_sgl_update - update xri-sgl sizing and mapping
895427bd
JS
4296 * @phba: pointer to lpfc hba data structure.
4297 *
4298 * This routine first calculates the sizes of the current els and allocated
4299 * scsi sgl lists, and then goes through all sgls to updates the physical
4300 * XRIs assigned due to port function reset. During port initialization, the
4301 * current els and allocated scsi sgl lists are 0s.
4302 *
4303 * Return codes
4304 * 0 - successful (for now, it always returns 0)
4305 **/
4306int
5e5b511d 4307lpfc_sli4_io_sgl_update(struct lpfc_hba *phba)
895427bd 4308{
c490850a 4309 struct lpfc_io_buf *lpfc_ncmd = NULL, *lpfc_ncmd_next = NULL;
0794d601 4310 uint16_t i, lxri, els_xri_cnt;
5e5b511d
JS
4311 uint16_t io_xri_cnt, io_xri_max;
4312 LIST_HEAD(io_sgl_list);
0794d601 4313 int rc, cnt;
8a9d2e80 4314
895427bd 4315 /*
0794d601 4316 * update on pci function's allocated nvme xri-sgl list
895427bd 4317 */
8a9d2e80 4318
0794d601
JS
4319 /* maximum number of xris available for nvme buffers */
4320 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
5e5b511d
JS
4321 io_xri_max = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
4322 phba->sli4_hba.io_xri_max = io_xri_max;
895427bd 4323
e8c0a779 4324 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
0794d601 4325 "6074 Current allocated XRI sgl count:%d, "
d51cf5bd 4326 "maximum XRI count:%d els_xri_cnt:%d\n\n",
5e5b511d 4327 phba->sli4_hba.io_xri_cnt,
d51cf5bd
JS
4328 phba->sli4_hba.io_xri_max,
4329 els_xri_cnt);
8a9d2e80 4330
5e5b511d 4331 cnt = lpfc_io_buf_flush(phba, &io_sgl_list);
8a9d2e80 4332
5e5b511d 4333 if (phba->sli4_hba.io_xri_cnt > phba->sli4_hba.io_xri_max) {
0794d601 4334 /* max nvme xri shrunk below the allocated nvme buffers */
5e5b511d
JS
4335 io_xri_cnt = phba->sli4_hba.io_xri_cnt -
4336 phba->sli4_hba.io_xri_max;
0794d601 4337 /* release the extra allocated nvme buffers */
5e5b511d
JS
4338 for (i = 0; i < io_xri_cnt; i++) {
4339 list_remove_head(&io_sgl_list, lpfc_ncmd,
c490850a 4340 struct lpfc_io_buf, list);
0794d601 4341 if (lpfc_ncmd) {
771db5c0 4342 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
0794d601
JS
4343 lpfc_ncmd->data,
4344 lpfc_ncmd->dma_handle);
4345 kfree(lpfc_ncmd);
a2fc4aef 4346 }
8a9d2e80 4347 }
5e5b511d 4348 phba->sli4_hba.io_xri_cnt -= io_xri_cnt;
8a9d2e80
JS
4349 }
4350
0794d601
JS
4351 /* update xris associated to remaining allocated nvme buffers */
4352 lpfc_ncmd = NULL;
4353 lpfc_ncmd_next = NULL;
5e5b511d 4354 phba->sli4_hba.io_xri_cnt = cnt;
0794d601 4355 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
5e5b511d 4356 &io_sgl_list, list) {
8a9d2e80
JS
4357 lxri = lpfc_sli4_next_xritag(phba);
4358 if (lxri == NO_XRI) {
372c187b
DK
4359 lpfc_printf_log(phba, KERN_ERR,
4360 LOG_TRACE_EVENT,
0794d601
JS
4361 "6075 Failed to allocate xri for "
4362 "nvme buffer\n");
8a9d2e80
JS
4363 rc = -ENOMEM;
4364 goto out_free_mem;
4365 }
0794d601
JS
4366 lpfc_ncmd->cur_iocbq.sli4_lxritag = lxri;
4367 lpfc_ncmd->cur_iocbq.sli4_xritag = phba->sli4_hba.xri_ids[lxri];
8a9d2e80 4368 }
5e5b511d 4369 cnt = lpfc_io_buf_replenish(phba, &io_sgl_list);
dea3101e 4370 return 0;
8a9d2e80
JS
4371
4372out_free_mem:
5e5b511d 4373 lpfc_io_free(phba);
8a9d2e80 4374 return rc;
dea3101e 4375}
4376
0794d601 4377/**
5e5b511d 4378 * lpfc_new_io_buf - IO buffer allocator for HBA with SLI4 IF spec
fe614acd
LJ
4379 * @phba: Pointer to lpfc hba data structure.
4380 * @num_to_alloc: The requested number of buffers to allocate.
0794d601
JS
4381 *
4382 * This routine allocates nvme buffers for device with SLI-4 interface spec,
4383 * the nvme buffer contains all the necessary information needed to initiate
4384 * an I/O. After allocating up to @num_to_allocate IO buffers and put
4385 * them on a list, it post them to the port by using SGL block post.
4386 *
4387 * Return codes:
5e5b511d 4388 * int - number of IO buffers that were allocated and posted.
0794d601
JS
4389 * 0 = failure, less than num_to_alloc is a partial failure.
4390 **/
4391int
5e5b511d 4392lpfc_new_io_buf(struct lpfc_hba *phba, int num_to_alloc)
0794d601 4393{
c490850a 4394 struct lpfc_io_buf *lpfc_ncmd;
0794d601
JS
4395 struct lpfc_iocbq *pwqeq;
4396 uint16_t iotag, lxri = 0;
4397 int bcnt, num_posted;
4398 LIST_HEAD(prep_nblist);
4399 LIST_HEAD(post_nblist);
4400 LIST_HEAD(nvme_nblist);
4401
5e5b511d 4402 phba->sli4_hba.io_xri_cnt = 0;
0794d601 4403 for (bcnt = 0; bcnt < num_to_alloc; bcnt++) {
7f9989ba 4404 lpfc_ncmd = kzalloc(sizeof(*lpfc_ncmd), GFP_KERNEL);
0794d601
JS
4405 if (!lpfc_ncmd)
4406 break;
4407 /*
4408 * Get memory from the pci pool to map the virt space to
4409 * pci bus space for an I/O. The DMA buffer includes the
4410 * number of SGE's necessary to support the sg_tablesize.
4411 */
a5c990ee
TM
4412 lpfc_ncmd->data = dma_pool_zalloc(phba->lpfc_sg_dma_buf_pool,
4413 GFP_KERNEL,
4414 &lpfc_ncmd->dma_handle);
0794d601
JS
4415 if (!lpfc_ncmd->data) {
4416 kfree(lpfc_ncmd);
4417 break;
4418 }
0794d601 4419
d79c9e9d
JS
4420 if (phba->cfg_xpsgl && !phba->nvmet_support) {
4421 INIT_LIST_HEAD(&lpfc_ncmd->dma_sgl_xtra_list);
4422 } else {
4423 /*
4424 * 4K Page alignment is CRITICAL to BlockGuard, double
4425 * check to be sure.
4426 */
4427 if ((phba->sli3_options & LPFC_SLI3_BG_ENABLED) &&
4428 (((unsigned long)(lpfc_ncmd->data) &
4429 (unsigned long)(SLI4_PAGE_SIZE - 1)) != 0)) {
372c187b
DK
4430 lpfc_printf_log(phba, KERN_ERR,
4431 LOG_TRACE_EVENT,
d79c9e9d
JS
4432 "3369 Memory alignment err: "
4433 "addr=%lx\n",
4434 (unsigned long)lpfc_ncmd->data);
4435 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4436 lpfc_ncmd->data,
4437 lpfc_ncmd->dma_handle);
4438 kfree(lpfc_ncmd);
4439 break;
4440 }
0794d601
JS
4441 }
4442
d79c9e9d
JS
4443 INIT_LIST_HEAD(&lpfc_ncmd->dma_cmd_rsp_list);
4444
0794d601
JS
4445 lxri = lpfc_sli4_next_xritag(phba);
4446 if (lxri == NO_XRI) {
4447 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4448 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
4449 kfree(lpfc_ncmd);
4450 break;
4451 }
4452 pwqeq = &lpfc_ncmd->cur_iocbq;
4453
4454 /* Allocate iotag for lpfc_ncmd->cur_iocbq. */
4455 iotag = lpfc_sli_next_iotag(phba, pwqeq);
4456 if (iotag == 0) {
4457 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4458 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
4459 kfree(lpfc_ncmd);
372c187b 4460 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0794d601
JS
4461 "6121 Failed to allocate IOTAG for"
4462 " XRI:0x%x\n", lxri);
4463 lpfc_sli4_free_xri(phba, lxri);
4464 break;
4465 }
4466 pwqeq->sli4_lxritag = lxri;
4467 pwqeq->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
0794d601
JS
4468
4469 /* Initialize local short-hand pointers. */
4470 lpfc_ncmd->dma_sgl = lpfc_ncmd->data;
4471 lpfc_ncmd->dma_phys_sgl = lpfc_ncmd->dma_handle;
d51cf5bd 4472 lpfc_ncmd->cur_iocbq.io_buf = lpfc_ncmd;
c2017260 4473 spin_lock_init(&lpfc_ncmd->buf_lock);
0794d601
JS
4474
4475 /* add the nvme buffer to a post list */
4476 list_add_tail(&lpfc_ncmd->list, &post_nblist);
5e5b511d 4477 phba->sli4_hba.io_xri_cnt++;
0794d601
JS
4478 }
4479 lpfc_printf_log(phba, KERN_INFO, LOG_NVME,
4480 "6114 Allocate %d out of %d requested new NVME "
d51cf5bd
JS
4481 "buffers of size x%zu bytes\n", bcnt, num_to_alloc,
4482 sizeof(*lpfc_ncmd));
4483
0794d601
JS
4484
4485 /* post the list of nvme buffer sgls to port if available */
4486 if (!list_empty(&post_nblist))
5e5b511d 4487 num_posted = lpfc_sli4_post_io_sgl_list(
0794d601
JS
4488 phba, &post_nblist, bcnt);
4489 else
4490 num_posted = 0;
4491
4492 return num_posted;
4493}
4494
96418b5e
JS
4495static uint64_t
4496lpfc_get_wwpn(struct lpfc_hba *phba)
4497{
4498 uint64_t wwn;
4499 int rc;
4500 LPFC_MBOXQ_t *mboxq;
4501 MAILBOX_t *mb;
4502
96418b5e
JS
4503 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
4504 GFP_KERNEL);
4505 if (!mboxq)
4506 return (uint64_t)-1;
4507
4508 /* First get WWN of HBA instance */
4509 lpfc_read_nv(phba, mboxq);
4510 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
4511 if (rc != MBX_SUCCESS) {
372c187b 4512 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
96418b5e
JS
4513 "6019 Mailbox failed , mbxCmd x%x "
4514 "READ_NV, mbxStatus x%x\n",
4515 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
4516 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
4517 mempool_free(mboxq, phba->mbox_mem_pool);
4518 return (uint64_t) -1;
4519 }
4520 mb = &mboxq->u.mb;
4521 memcpy(&wwn, (char *)mb->un.varRDnvp.portname, sizeof(uint64_t));
4522 /* wwn is WWPN of HBA instance */
4523 mempool_free(mboxq, phba->mbox_mem_pool);
4524 if (phba->sli_rev == LPFC_SLI_REV4)
4525 return be64_to_cpu(wwn);
4526 else
286871a6 4527 return rol64(wwn, 32);
96418b5e
JS
4528}
4529
5e633302
GS
4530/**
4531 * lpfc_vmid_res_alloc - Allocates resources for VMID
4532 * @phba: pointer to lpfc hba data structure.
4533 * @vport: pointer to vport data structure
4534 *
4535 * This routine allocated the resources needed for the VMID.
4536 *
4537 * Return codes
4538 * 0 on Success
4539 * Non-0 on Failure
4540 */
4541static int
4542lpfc_vmid_res_alloc(struct lpfc_hba *phba, struct lpfc_vport *vport)
4543{
4544 /* VMID feature is supported only on SLI4 */
4545 if (phba->sli_rev == LPFC_SLI_REV3) {
4546 phba->cfg_vmid_app_header = 0;
4547 phba->cfg_vmid_priority_tagging = 0;
4548 }
4549
4550 if (lpfc_is_vmid_enabled(phba)) {
4551 vport->vmid =
4552 kcalloc(phba->cfg_max_vmid, sizeof(struct lpfc_vmid),
4553 GFP_KERNEL);
4554 if (!vport->vmid)
4555 return -ENOMEM;
4556
4557 rwlock_init(&vport->vmid_lock);
4558
4559 /* Set the VMID parameters for the vport */
4560 vport->vmid_priority_tagging = phba->cfg_vmid_priority_tagging;
4561 vport->vmid_inactivity_timeout =
4562 phba->cfg_vmid_inactivity_timeout;
4563 vport->max_vmid = phba->cfg_max_vmid;
4564 vport->cur_vmid_cnt = 0;
4565
4566 vport->vmid_priority_range = bitmap_zalloc
4567 (LPFC_VMID_MAX_PRIORITY_RANGE, GFP_KERNEL);
4568
4569 if (!vport->vmid_priority_range) {
4570 kfree(vport->vmid);
4571 return -ENOMEM;
4572 }
4573
4574 hash_init(vport->hash_table);
4575 }
4576 return 0;
4577}
4578
e59058c4 4579/**
3621a710 4580 * lpfc_create_port - Create an FC port
e59058c4
JS
4581 * @phba: pointer to lpfc hba data structure.
4582 * @instance: a unique integer ID to this FC port.
4583 * @dev: pointer to the device data structure.
4584 *
4585 * This routine creates a FC port for the upper layer protocol. The FC port
4586 * can be created on top of either a physical port or a virtual port provided
4587 * by the HBA. This routine also allocates a SCSI host data structure (shost)
4588 * and associates the FC port created before adding the shost into the SCSI
4589 * layer.
4590 *
4591 * Return codes
4592 * @vport - pointer to the virtual N_Port data structure.
4593 * NULL - port create failed.
4594 **/
2e0fef85 4595struct lpfc_vport *
3de2a653 4596lpfc_create_port(struct lpfc_hba *phba, int instance, struct device *dev)
47a8617c 4597{
2e0fef85 4598 struct lpfc_vport *vport;
895427bd 4599 struct Scsi_Host *shost = NULL;
c90b4480 4600 struct scsi_host_template *template;
2e0fef85 4601 int error = 0;
96418b5e
JS
4602 int i;
4603 uint64_t wwn;
4604 bool use_no_reset_hba = false;
56bc8028 4605 int rc;
96418b5e 4606
56bc8028
JS
4607 if (lpfc_no_hba_reset_cnt) {
4608 if (phba->sli_rev < LPFC_SLI_REV4 &&
4609 dev == &phba->pcidev->dev) {
4610 /* Reset the port first */
4611 lpfc_sli_brdrestart(phba);
4612 rc = lpfc_sli_chipset_init(phba);
4613 if (rc)
4614 return NULL;
4615 }
4616 wwn = lpfc_get_wwpn(phba);
4617 }
96418b5e
JS
4618
4619 for (i = 0; i < lpfc_no_hba_reset_cnt; i++) {
4620 if (wwn == lpfc_no_hba_reset[i]) {
372c187b
DK
4621 lpfc_printf_log(phba, KERN_ERR,
4622 LOG_TRACE_EVENT,
96418b5e
JS
4623 "6020 Setting use_no_reset port=%llx\n",
4624 wwn);
4625 use_no_reset_hba = true;
4626 break;
4627 }
4628 }
47a8617c 4629
c90b4480
JS
4630 /* Seed template for SCSI host registration */
4631 if (dev == &phba->pcidev->dev) {
4632 template = &phba->port_template;
4633
4634 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
4635 /* Seed physical port template */
4636 memcpy(template, &lpfc_template, sizeof(*template));
4637
7c30bb62 4638 if (use_no_reset_hba)
c90b4480 4639 /* template is for a no reset SCSI Host */
c90b4480 4640 template->eh_host_reset_handler = NULL;
c90b4480
JS
4641
4642 /* Template for all vports this physical port creates */
4643 memcpy(&phba->vport_template, &lpfc_template,
4644 sizeof(*template));
08adfa75 4645 phba->vport_template.shost_groups = lpfc_vport_groups;
c90b4480
JS
4646 phba->vport_template.eh_bus_reset_handler = NULL;
4647 phba->vport_template.eh_host_reset_handler = NULL;
4648 phba->vport_template.vendor_id = 0;
4649
4650 /* Initialize the host templates with updated value */
4651 if (phba->sli_rev == LPFC_SLI_REV4) {
4652 template->sg_tablesize = phba->cfg_scsi_seg_cnt;
4653 phba->vport_template.sg_tablesize =
4654 phba->cfg_scsi_seg_cnt;
4655 } else {
4656 template->sg_tablesize = phba->cfg_sg_seg_cnt;
4657 phba->vport_template.sg_tablesize =
4658 phba->cfg_sg_seg_cnt;
4659 }
4660
895427bd 4661 } else {
c90b4480
JS
4662 /* NVMET is for physical port only */
4663 memcpy(template, &lpfc_template_nvme,
4664 sizeof(*template));
895427bd 4665 }
c90b4480
JS
4666 } else {
4667 template = &phba->vport_template;
ea4142f6 4668 }
c90b4480
JS
4669
4670 shost = scsi_host_alloc(template, sizeof(struct lpfc_vport));
2e0fef85
JS
4671 if (!shost)
4672 goto out;
47a8617c 4673
2e0fef85
JS
4674 vport = (struct lpfc_vport *) shost->hostdata;
4675 vport->phba = phba;
2e0fef85 4676 vport->load_flag |= FC_LOADING;
92d7f7b0 4677 vport->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
7f5f3d0d 4678 vport->fc_rscn_flush = 0;
3de2a653 4679 lpfc_get_vport_cfgparam(vport);
895427bd 4680
f6e84790
JS
4681 /* Adjust value in vport */
4682 vport->cfg_enable_fc4_type = phba->cfg_enable_fc4_type;
4683
2e0fef85
JS
4684 shost->unique_id = instance;
4685 shost->max_id = LPFC_MAX_TARGET;
3de2a653 4686 shost->max_lun = vport->cfg_max_luns;
2e0fef85
JS
4687 shost->this_id = -1;
4688 shost->max_cmd_len = 16;
6a828b0f 4689
da0436e9 4690 if (phba->sli_rev == LPFC_SLI_REV4) {
77ffd346
JS
4691 if (!phba->cfg_fcp_mq_threshold ||
4692 phba->cfg_fcp_mq_threshold > phba->cfg_hdw_queue)
4693 phba->cfg_fcp_mq_threshold = phba->cfg_hdw_queue;
4694
4695 shost->nr_hw_queues = min_t(int, 2 * num_possible_nodes(),
4696 phba->cfg_fcp_mq_threshold);
6a828b0f 4697
28baac74 4698 shost->dma_boundary =
cb5172ea 4699 phba->sli4_hba.pc_sli4_params.sge_supp_len-1;
d79c9e9d
JS
4700
4701 if (phba->cfg_xpsgl && !phba->nvmet_support)
4702 shost->sg_tablesize = LPFC_MAX_SG_TABLESIZE;
4703 else
4704 shost->sg_tablesize = phba->cfg_scsi_seg_cnt;
ace44e48
JS
4705 } else
4706 /* SLI-3 has a limited number of hardware queues (3),
4707 * thus there is only one for FCP processing.
4708 */
4709 shost->nr_hw_queues = 1;
81301a9b 4710
47a8617c 4711 /*
2e0fef85
JS
4712 * Set initial can_queue value since 0 is no longer supported and
4713 * scsi_add_host will fail. This will be adjusted later based on the
4714 * max xri value determined in hba setup.
47a8617c 4715 */
2e0fef85 4716 shost->can_queue = phba->cfg_hba_queue_depth - 10;
3de2a653 4717 if (dev != &phba->pcidev->dev) {
92d7f7b0
JS
4718 shost->transportt = lpfc_vport_transport_template;
4719 vport->port_type = LPFC_NPIV_PORT;
4720 } else {
4721 shost->transportt = lpfc_transport_template;
4722 vport->port_type = LPFC_PHYSICAL_PORT;
4723 }
47a8617c 4724
c90b4480
JS
4725 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
4726 "9081 CreatePort TMPLATE type %x TBLsize %d "
4727 "SEGcnt %d/%d\n",
4728 vport->port_type, shost->sg_tablesize,
4729 phba->cfg_scsi_seg_cnt, phba->cfg_sg_seg_cnt);
4730
5e633302
GS
4731 /* Allocate the resources for VMID */
4732 rc = lpfc_vmid_res_alloc(phba, vport);
4733
4734 if (rc)
4735 goto out;
4736
2e0fef85
JS
4737 /* Initialize all internally managed lists. */
4738 INIT_LIST_HEAD(&vport->fc_nodes);
da0436e9 4739 INIT_LIST_HEAD(&vport->rcv_buffer_list);
2e0fef85 4740 spin_lock_init(&vport->work_port_lock);
47a8617c 4741
f22eb4d3 4742 timer_setup(&vport->fc_disctmo, lpfc_disc_timeout, 0);
47a8617c 4743
f22eb4d3 4744 timer_setup(&vport->els_tmofunc, lpfc_els_timeout, 0);
92494144 4745
f22eb4d3 4746 timer_setup(&vport->delayed_disc_tmo, lpfc_delayed_disc_tmo, 0);
92494144 4747
aa6ff309
JS
4748 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED)
4749 lpfc_setup_bg(phba, shost);
4750
d139b9bd 4751 error = scsi_add_host_with_dma(shost, dev, &phba->pcidev->dev);
2e0fef85
JS
4752 if (error)
4753 goto out_put_shost;
47a8617c 4754
523128e5 4755 spin_lock_irq(&phba->port_list_lock);
2e0fef85 4756 list_add_tail(&vport->listentry, &phba->port_list);
523128e5 4757 spin_unlock_irq(&phba->port_list_lock);
2e0fef85 4758 return vport;
47a8617c 4759
2e0fef85 4760out_put_shost:
5e633302
GS
4761 kfree(vport->vmid);
4762 bitmap_free(vport->vmid_priority_range);
2e0fef85
JS
4763 scsi_host_put(shost);
4764out:
4765 return NULL;
47a8617c
JS
4766}
4767
e59058c4 4768/**
3621a710 4769 * destroy_port - destroy an FC port
e59058c4
JS
4770 * @vport: pointer to an lpfc virtual N_Port data structure.
4771 *
4772 * This routine destroys a FC port from the upper layer protocol. All the
4773 * resources associated with the port are released.
4774 **/
2e0fef85
JS
4775void
4776destroy_port(struct lpfc_vport *vport)
47a8617c 4777{
92d7f7b0
JS
4778 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
4779 struct lpfc_hba *phba = vport->phba;
47a8617c 4780
858c9f6c 4781 lpfc_debugfs_terminate(vport);
92d7f7b0
JS
4782 fc_remove_host(shost);
4783 scsi_remove_host(shost);
47a8617c 4784
523128e5 4785 spin_lock_irq(&phba->port_list_lock);
92d7f7b0 4786 list_del_init(&vport->listentry);
523128e5 4787 spin_unlock_irq(&phba->port_list_lock);
47a8617c 4788
92d7f7b0 4789 lpfc_cleanup(vport);
47a8617c 4790 return;
47a8617c
JS
4791}
4792
e59058c4 4793/**
3621a710 4794 * lpfc_get_instance - Get a unique integer ID
e59058c4
JS
4795 *
4796 * This routine allocates a unique integer ID from lpfc_hba_index pool. It
4797 * uses the kernel idr facility to perform the task.
4798 *
4799 * Return codes:
4800 * instance - a unique integer ID allocated as the new instance.
4801 * -1 - lpfc get instance failed.
4802 **/
92d7f7b0
JS
4803int
4804lpfc_get_instance(void)
4805{
ab516036
TH
4806 int ret;
4807
4808 ret = idr_alloc(&lpfc_hba_index, NULL, 0, 0, GFP_KERNEL);
4809 return ret < 0 ? -1 : ret;
47a8617c
JS
4810}
4811
e59058c4 4812/**
3621a710 4813 * lpfc_scan_finished - method for SCSI layer to detect whether scan is done
e59058c4
JS
4814 * @shost: pointer to SCSI host data structure.
4815 * @time: elapsed time of the scan in jiffies.
4816 *
4817 * This routine is called by the SCSI layer with a SCSI host to determine
4818 * whether the scan host is finished.
4819 *
4820 * Note: there is no scan_start function as adapter initialization will have
4821 * asynchronously kicked off the link initialization.
4822 *
4823 * Return codes
4824 * 0 - SCSI host scan is not over yet.
4825 * 1 - SCSI host scan is over.
4826 **/
47a8617c
JS
4827int lpfc_scan_finished(struct Scsi_Host *shost, unsigned long time)
4828{
2e0fef85
JS
4829 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4830 struct lpfc_hba *phba = vport->phba;
858c9f6c 4831 int stat = 0;
47a8617c 4832
858c9f6c
JS
4833 spin_lock_irq(shost->host_lock);
4834
51ef4c26 4835 if (vport->load_flag & FC_UNLOADING) {
858c9f6c
JS
4836 stat = 1;
4837 goto finished;
4838 }
256ec0d0 4839 if (time >= msecs_to_jiffies(30 * 1000)) {
2e0fef85 4840 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011
JS
4841 "0461 Scanning longer than 30 "
4842 "seconds. Continuing initialization\n");
858c9f6c 4843 stat = 1;
47a8617c 4844 goto finished;
2e0fef85 4845 }
256ec0d0
JS
4846 if (time >= msecs_to_jiffies(15 * 1000) &&
4847 phba->link_state <= LPFC_LINK_DOWN) {
2e0fef85 4848 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011
JS
4849 "0465 Link down longer than 15 "
4850 "seconds. Continuing initialization\n");
858c9f6c 4851 stat = 1;
47a8617c 4852 goto finished;
2e0fef85 4853 }
47a8617c 4854
2e0fef85 4855 if (vport->port_state != LPFC_VPORT_READY)
858c9f6c 4856 goto finished;
2e0fef85 4857 if (vport->num_disc_nodes || vport->fc_prli_sent)
858c9f6c 4858 goto finished;
256ec0d0 4859 if (vport->fc_map_cnt == 0 && time < msecs_to_jiffies(2 * 1000))
858c9f6c 4860 goto finished;
2e0fef85 4861 if ((phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) != 0)
858c9f6c
JS
4862 goto finished;
4863
4864 stat = 1;
47a8617c
JS
4865
4866finished:
858c9f6c
JS
4867 spin_unlock_irq(shost->host_lock);
4868 return stat;
92d7f7b0 4869}
47a8617c 4870
3999df75 4871static void lpfc_host_supported_speeds_set(struct Scsi_Host *shost)
cd71348a
JS
4872{
4873 struct lpfc_vport *vport = (struct lpfc_vport *)shost->hostdata;
4874 struct lpfc_hba *phba = vport->phba;
4875
4876 fc_host_supported_speeds(shost) = 0;
a1e4d3d8
DK
4877 /*
4878 * Avoid reporting supported link speed for FCoE as it can't be
4879 * controlled via FCoE.
4880 */
4881 if (phba->hba_flag & HBA_FCOE_MODE)
4882 return;
4883
bfc47785
JS
4884 if (phba->lmt & LMT_256Gb)
4885 fc_host_supported_speeds(shost) |= FC_PORTSPEED_256GBIT;
1dc5ec24
JS
4886 if (phba->lmt & LMT_128Gb)
4887 fc_host_supported_speeds(shost) |= FC_PORTSPEED_128GBIT;
cd71348a
JS
4888 if (phba->lmt & LMT_64Gb)
4889 fc_host_supported_speeds(shost) |= FC_PORTSPEED_64GBIT;
4890 if (phba->lmt & LMT_32Gb)
4891 fc_host_supported_speeds(shost) |= FC_PORTSPEED_32GBIT;
4892 if (phba->lmt & LMT_16Gb)
4893 fc_host_supported_speeds(shost) |= FC_PORTSPEED_16GBIT;
4894 if (phba->lmt & LMT_10Gb)
4895 fc_host_supported_speeds(shost) |= FC_PORTSPEED_10GBIT;
4896 if (phba->lmt & LMT_8Gb)
4897 fc_host_supported_speeds(shost) |= FC_PORTSPEED_8GBIT;
4898 if (phba->lmt & LMT_4Gb)
4899 fc_host_supported_speeds(shost) |= FC_PORTSPEED_4GBIT;
4900 if (phba->lmt & LMT_2Gb)
4901 fc_host_supported_speeds(shost) |= FC_PORTSPEED_2GBIT;
4902 if (phba->lmt & LMT_1Gb)
4903 fc_host_supported_speeds(shost) |= FC_PORTSPEED_1GBIT;
4904}
4905
e59058c4 4906/**
3621a710 4907 * lpfc_host_attrib_init - Initialize SCSI host attributes on a FC port
e59058c4
JS
4908 * @shost: pointer to SCSI host data structure.
4909 *
4910 * This routine initializes a given SCSI host attributes on a FC port. The
4911 * SCSI host can be either on top of a physical port or a virtual port.
4912 **/
92d7f7b0
JS
4913void lpfc_host_attrib_init(struct Scsi_Host *shost)
4914{
4915 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4916 struct lpfc_hba *phba = vport->phba;
47a8617c 4917 /*
2e0fef85 4918 * Set fixed host attributes. Must done after lpfc_sli_hba_setup().
47a8617c
JS
4919 */
4920
2e0fef85
JS
4921 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
4922 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
47a8617c
JS
4923 fc_host_supported_classes(shost) = FC_COS_CLASS3;
4924
4925 memset(fc_host_supported_fc4s(shost), 0,
2e0fef85 4926 sizeof(fc_host_supported_fc4s(shost)));
47a8617c
JS
4927 fc_host_supported_fc4s(shost)[2] = 1;
4928 fc_host_supported_fc4s(shost)[7] = 1;
4929
92d7f7b0
JS
4930 lpfc_vport_symbolic_node_name(vport, fc_host_symbolic_name(shost),
4931 sizeof fc_host_symbolic_name(shost));
47a8617c 4932
cd71348a 4933 lpfc_host_supported_speeds_set(shost);
47a8617c
JS
4934
4935 fc_host_maxframe_size(shost) =
2e0fef85
JS
4936 (((uint32_t) vport->fc_sparam.cmn.bbRcvSizeMsb & 0x0F) << 8) |
4937 (uint32_t) vport->fc_sparam.cmn.bbRcvSizeLsb;
47a8617c 4938
0af5d708
MC
4939 fc_host_dev_loss_tmo(shost) = vport->cfg_devloss_tmo;
4940
47a8617c
JS
4941 /* This value is also unchanging */
4942 memset(fc_host_active_fc4s(shost), 0,
2e0fef85 4943 sizeof(fc_host_active_fc4s(shost)));
47a8617c
JS
4944 fc_host_active_fc4s(shost)[2] = 1;
4945 fc_host_active_fc4s(shost)[7] = 1;
4946
92d7f7b0 4947 fc_host_max_npiv_vports(shost) = phba->max_vpi;
47a8617c 4948 spin_lock_irq(shost->host_lock);
51ef4c26 4949 vport->load_flag &= ~FC_LOADING;
47a8617c 4950 spin_unlock_irq(shost->host_lock);
47a8617c 4951}
dea3101e 4952
e59058c4 4953/**
da0436e9 4954 * lpfc_stop_port_s3 - Stop SLI3 device port
e59058c4
JS
4955 * @phba: pointer to lpfc hba data structure.
4956 *
da0436e9
JS
4957 * This routine is invoked to stop an SLI3 device port, it stops the device
4958 * from generating interrupts and stops the device driver's timers for the
4959 * device.
e59058c4 4960 **/
da0436e9
JS
4961static void
4962lpfc_stop_port_s3(struct lpfc_hba *phba)
db2378e0 4963{
da0436e9
JS
4964 /* Clear all interrupt enable conditions */
4965 writel(0, phba->HCregaddr);
4966 readl(phba->HCregaddr); /* flush */
4967 /* Clear all pending interrupts */
4968 writel(0xffffffff, phba->HAregaddr);
4969 readl(phba->HAregaddr); /* flush */
db2378e0 4970
da0436e9
JS
4971 /* Reset some HBA SLI setup states */
4972 lpfc_stop_hba_timers(phba);
4973 phba->pport->work_port_events = 0;
4974}
db2378e0 4975
da0436e9
JS
4976/**
4977 * lpfc_stop_port_s4 - Stop SLI4 device port
4978 * @phba: pointer to lpfc hba data structure.
4979 *
4980 * This routine is invoked to stop an SLI4 device port, it stops the device
4981 * from generating interrupts and stops the device driver's timers for the
4982 * device.
4983 **/
4984static void
4985lpfc_stop_port_s4(struct lpfc_hba *phba)
4986{
4987 /* Reset some HBA SLI4 setup states */
4988 lpfc_stop_hba_timers(phba);
cdb42bec
JS
4989 if (phba->pport)
4990 phba->pport->work_port_events = 0;
da0436e9 4991 phba->sli4_hba.intr_enable = 0;
da0436e9 4992}
9399627f 4993
da0436e9
JS
4994/**
4995 * lpfc_stop_port - Wrapper function for stopping hba port
4996 * @phba: Pointer to HBA context object.
4997 *
4998 * This routine wraps the actual SLI3 or SLI4 hba stop port routine from
4999 * the API jump table function pointer from the lpfc_hba struct.
5000 **/
5001void
5002lpfc_stop_port(struct lpfc_hba *phba)
5003{
5004 phba->lpfc_stop_port(phba);
f485c18d
DK
5005
5006 if (phba->wq)
5007 flush_workqueue(phba->wq);
da0436e9 5008}
db2378e0 5009
ecfd03c6
JS
5010/**
5011 * lpfc_fcf_redisc_wait_start_timer - Start fcf rediscover wait timer
5012 * @phba: Pointer to hba for which this call is being executed.
5013 *
5014 * This routine starts the timer waiting for the FCF rediscovery to complete.
5015 **/
5016void
5017lpfc_fcf_redisc_wait_start_timer(struct lpfc_hba *phba)
5018{
5019 unsigned long fcf_redisc_wait_tmo =
5020 (jiffies + msecs_to_jiffies(LPFC_FCF_REDISCOVER_WAIT_TMO));
5021 /* Start fcf rediscovery wait period timer */
5022 mod_timer(&phba->fcf.redisc_wait, fcf_redisc_wait_tmo);
5023 spin_lock_irq(&phba->hbalock);
5024 /* Allow action to new fcf asynchronous event */
5025 phba->fcf.fcf_flag &= ~(FCF_AVAILABLE | FCF_SCAN_DONE);
5026 /* Mark the FCF rediscovery pending state */
5027 phba->fcf.fcf_flag |= FCF_REDISC_PEND;
5028 spin_unlock_irq(&phba->hbalock);
5029}
5030
5031/**
5032 * lpfc_sli4_fcf_redisc_wait_tmo - FCF table rediscover wait timeout
fe614acd 5033 * @t: Timer context used to obtain the pointer to lpfc hba data structure.
ecfd03c6
JS
5034 *
5035 * This routine is invoked when waiting for FCF table rediscover has been
5036 * timed out. If new FCF record(s) has (have) been discovered during the
5037 * wait period, a new FCF event shall be added to the FCOE async event
5038 * list, and then worker thread shall be waked up for processing from the
5039 * worker thread context.
5040 **/
e399b228 5041static void
f22eb4d3 5042lpfc_sli4_fcf_redisc_wait_tmo(struct timer_list *t)
ecfd03c6 5043{
f22eb4d3 5044 struct lpfc_hba *phba = from_timer(phba, t, fcf.redisc_wait);
ecfd03c6
JS
5045
5046 /* Don't send FCF rediscovery event if timer cancelled */
5047 spin_lock_irq(&phba->hbalock);
5048 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
5049 spin_unlock_irq(&phba->hbalock);
5050 return;
5051 }
5052 /* Clear FCF rediscovery timer pending flag */
5053 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
5054 /* FCF rediscovery event to worker thread */
5055 phba->fcf.fcf_flag |= FCF_REDISC_EVT;
5056 spin_unlock_irq(&phba->hbalock);
0c9ab6f5 5057 lpfc_printf_log(phba, KERN_INFO, LOG_FIP,
a93ff37a 5058 "2776 FCF rediscover quiescent timer expired\n");
ecfd03c6
JS
5059 /* wake up worker thread */
5060 lpfc_worker_wake_up(phba);
5061}
5062
20397179
GS
5063/**
5064 * lpfc_vmid_poll - VMID timeout detection
50baa159 5065 * @t: Timer context used to obtain the pointer to lpfc hba data structure.
20397179
GS
5066 *
5067 * This routine is invoked when there is no I/O on by a VM for the specified
5068 * amount of time. When this situation is detected, the VMID has to be
5069 * deregistered from the switch and all the local resources freed. The VMID
5070 * will be reassigned to the VM once the I/O begins.
5071 **/
5072static void
5073lpfc_vmid_poll(struct timer_list *t)
5074{
5075 struct lpfc_hba *phba = from_timer(phba, t, inactive_vmid_poll);
5076 u32 wake_up = 0;
5077
5078 /* check if there is a need to issue QFPA */
5079 if (phba->pport->vmid_priority_tagging) {
5080 wake_up = 1;
5081 phba->pport->work_port_events |= WORKER_CHECK_VMID_ISSUE_QFPA;
5082 }
5083
5084 /* Is the vmid inactivity timer enabled */
5085 if (phba->pport->vmid_inactivity_timeout ||
5086 phba->pport->load_flag & FC_DEREGISTER_ALL_APP_ID) {
5087 wake_up = 1;
5088 phba->pport->work_port_events |= WORKER_CHECK_INACTIVE_VMID;
5089 }
5090
5091 if (wake_up)
5092 lpfc_worker_wake_up(phba);
5093
5094 /* restart the timer for the next iteration */
5095 mod_timer(&phba->inactive_vmid_poll, jiffies + msecs_to_jiffies(1000 *
5096 LPFC_VMID_TIMER));
5097}
5098
e59058c4 5099/**
da0436e9 5100 * lpfc_sli4_parse_latt_fault - Parse sli4 link-attention link fault code
e59058c4 5101 * @phba: pointer to lpfc hba data structure.
da0436e9 5102 * @acqe_link: pointer to the async link completion queue entry.
e59058c4 5103 *
23288b78 5104 * This routine is to parse the SLI4 link-attention link fault code.
e59058c4 5105 **/
23288b78 5106static void
da0436e9
JS
5107lpfc_sli4_parse_latt_fault(struct lpfc_hba *phba,
5108 struct lpfc_acqe_link *acqe_link)
db2378e0 5109{
da0436e9
JS
5110 switch (bf_get(lpfc_acqe_link_fault, acqe_link)) {
5111 case LPFC_ASYNC_LINK_FAULT_NONE:
5112 case LPFC_ASYNC_LINK_FAULT_LOCAL:
5113 case LPFC_ASYNC_LINK_FAULT_REMOTE:
23288b78 5114 case LPFC_ASYNC_LINK_FAULT_LR_LRR:
da0436e9
JS
5115 break;
5116 default:
372c187b 5117 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
23288b78 5118 "0398 Unknown link fault code: x%x\n",
da0436e9 5119 bf_get(lpfc_acqe_link_fault, acqe_link));
da0436e9
JS
5120 break;
5121 }
db2378e0
JS
5122}
5123
5b75da2f 5124/**
da0436e9 5125 * lpfc_sli4_parse_latt_type - Parse sli4 link attention type
5b75da2f 5126 * @phba: pointer to lpfc hba data structure.
da0436e9 5127 * @acqe_link: pointer to the async link completion queue entry.
5b75da2f 5128 *
da0436e9
JS
5129 * This routine is to parse the SLI4 link attention type and translate it
5130 * into the base driver's link attention type coding.
5b75da2f 5131 *
da0436e9
JS
5132 * Return: Link attention type in terms of base driver's coding.
5133 **/
5134static uint8_t
5135lpfc_sli4_parse_latt_type(struct lpfc_hba *phba,
5136 struct lpfc_acqe_link *acqe_link)
5b75da2f 5137{
da0436e9 5138 uint8_t att_type;
5b75da2f 5139
da0436e9
JS
5140 switch (bf_get(lpfc_acqe_link_status, acqe_link)) {
5141 case LPFC_ASYNC_LINK_STATUS_DOWN:
5142 case LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN:
76a95d75 5143 att_type = LPFC_ATT_LINK_DOWN;
da0436e9
JS
5144 break;
5145 case LPFC_ASYNC_LINK_STATUS_UP:
5146 /* Ignore physical link up events - wait for logical link up */
76a95d75 5147 att_type = LPFC_ATT_RESERVED;
da0436e9
JS
5148 break;
5149 case LPFC_ASYNC_LINK_STATUS_LOGICAL_UP:
76a95d75 5150 att_type = LPFC_ATT_LINK_UP;
da0436e9
JS
5151 break;
5152 default:
372c187b 5153 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
5154 "0399 Invalid link attention type: x%x\n",
5155 bf_get(lpfc_acqe_link_status, acqe_link));
76a95d75 5156 att_type = LPFC_ATT_RESERVED;
da0436e9 5157 break;
5b75da2f 5158 }
da0436e9 5159 return att_type;
5b75da2f
JS
5160}
5161
8b68cd52
JS
5162/**
5163 * lpfc_sli_port_speed_get - Get sli3 link speed code to link speed
5164 * @phba: pointer to lpfc hba data structure.
5165 *
5166 * This routine is to get an SLI3 FC port's link speed in Mbps.
5167 *
5168 * Return: link speed in terms of Mbps.
5169 **/
5170uint32_t
5171lpfc_sli_port_speed_get(struct lpfc_hba *phba)
5172{
5173 uint32_t link_speed;
5174
5175 if (!lpfc_is_link_up(phba))
5176 return 0;
5177
a085e87c
JS
5178 if (phba->sli_rev <= LPFC_SLI_REV3) {
5179 switch (phba->fc_linkspeed) {
5180 case LPFC_LINK_SPEED_1GHZ:
5181 link_speed = 1000;
5182 break;
5183 case LPFC_LINK_SPEED_2GHZ:
5184 link_speed = 2000;
5185 break;
5186 case LPFC_LINK_SPEED_4GHZ:
5187 link_speed = 4000;
5188 break;
5189 case LPFC_LINK_SPEED_8GHZ:
5190 link_speed = 8000;
5191 break;
5192 case LPFC_LINK_SPEED_10GHZ:
5193 link_speed = 10000;
5194 break;
5195 case LPFC_LINK_SPEED_16GHZ:
5196 link_speed = 16000;
5197 break;
5198 default:
5199 link_speed = 0;
5200 }
5201 } else {
5202 if (phba->sli4_hba.link_state.logical_speed)
5203 link_speed =
5204 phba->sli4_hba.link_state.logical_speed;
5205 else
5206 link_speed = phba->sli4_hba.link_state.speed;
8b68cd52
JS
5207 }
5208 return link_speed;
5209}
5210
5211/**
5212 * lpfc_sli4_port_speed_parse - Parse async evt link speed code to link speed
5213 * @phba: pointer to lpfc hba data structure.
5214 * @evt_code: asynchronous event code.
5215 * @speed_code: asynchronous event link speed code.
5216 *
5217 * This routine is to parse the giving SLI4 async event link speed code into
5218 * value of Mbps for the link speed.
5219 *
5220 * Return: link speed in terms of Mbps.
5221 **/
5222static uint32_t
5223lpfc_sli4_port_speed_parse(struct lpfc_hba *phba, uint32_t evt_code,
5224 uint8_t speed_code)
5225{
5226 uint32_t port_speed;
5227
5228 switch (evt_code) {
5229 case LPFC_TRAILER_CODE_LINK:
5230 switch (speed_code) {
26d830ec 5231 case LPFC_ASYNC_LINK_SPEED_ZERO:
8b68cd52
JS
5232 port_speed = 0;
5233 break;
26d830ec 5234 case LPFC_ASYNC_LINK_SPEED_10MBPS:
8b68cd52
JS
5235 port_speed = 10;
5236 break;
26d830ec 5237 case LPFC_ASYNC_LINK_SPEED_100MBPS:
8b68cd52
JS
5238 port_speed = 100;
5239 break;
26d830ec 5240 case LPFC_ASYNC_LINK_SPEED_1GBPS:
8b68cd52
JS
5241 port_speed = 1000;
5242 break;
26d830ec 5243 case LPFC_ASYNC_LINK_SPEED_10GBPS:
8b68cd52
JS
5244 port_speed = 10000;
5245 break;
26d830ec
JS
5246 case LPFC_ASYNC_LINK_SPEED_20GBPS:
5247 port_speed = 20000;
5248 break;
5249 case LPFC_ASYNC_LINK_SPEED_25GBPS:
5250 port_speed = 25000;
5251 break;
5252 case LPFC_ASYNC_LINK_SPEED_40GBPS:
5253 port_speed = 40000;
5254 break;
a1e4d3d8
DK
5255 case LPFC_ASYNC_LINK_SPEED_100GBPS:
5256 port_speed = 100000;
5257 break;
8b68cd52
JS
5258 default:
5259 port_speed = 0;
5260 }
5261 break;
5262 case LPFC_TRAILER_CODE_FC:
5263 switch (speed_code) {
26d830ec 5264 case LPFC_FC_LA_SPEED_UNKNOWN:
8b68cd52
JS
5265 port_speed = 0;
5266 break;
26d830ec 5267 case LPFC_FC_LA_SPEED_1G:
8b68cd52
JS
5268 port_speed = 1000;
5269 break;
26d830ec 5270 case LPFC_FC_LA_SPEED_2G:
8b68cd52
JS
5271 port_speed = 2000;
5272 break;
26d830ec 5273 case LPFC_FC_LA_SPEED_4G:
8b68cd52
JS
5274 port_speed = 4000;
5275 break;
26d830ec 5276 case LPFC_FC_LA_SPEED_8G:
8b68cd52
JS
5277 port_speed = 8000;
5278 break;
26d830ec 5279 case LPFC_FC_LA_SPEED_10G:
8b68cd52
JS
5280 port_speed = 10000;
5281 break;
26d830ec 5282 case LPFC_FC_LA_SPEED_16G:
8b68cd52
JS
5283 port_speed = 16000;
5284 break;
d38dd52c
JS
5285 case LPFC_FC_LA_SPEED_32G:
5286 port_speed = 32000;
5287 break;
fbd8a6ba
JS
5288 case LPFC_FC_LA_SPEED_64G:
5289 port_speed = 64000;
5290 break;
1dc5ec24
JS
5291 case LPFC_FC_LA_SPEED_128G:
5292 port_speed = 128000;
5293 break;
bfc47785
JS
5294 case LPFC_FC_LA_SPEED_256G:
5295 port_speed = 256000;
5296 break;
8b68cd52
JS
5297 default:
5298 port_speed = 0;
5299 }
5300 break;
5301 default:
5302 port_speed = 0;
5303 }
5304 return port_speed;
5305}
5306
da0436e9 5307/**
70f3c073 5308 * lpfc_sli4_async_link_evt - Process the asynchronous FCoE link event
da0436e9
JS
5309 * @phba: pointer to lpfc hba data structure.
5310 * @acqe_link: pointer to the async link completion queue entry.
5311 *
70f3c073 5312 * This routine is to handle the SLI4 asynchronous FCoE link event.
da0436e9
JS
5313 **/
5314static void
5315lpfc_sli4_async_link_evt(struct lpfc_hba *phba,
5316 struct lpfc_acqe_link *acqe_link)
5317{
5318 struct lpfc_dmabuf *mp;
5319 LPFC_MBOXQ_t *pmb;
5320 MAILBOX_t *mb;
76a95d75 5321 struct lpfc_mbx_read_top *la;
da0436e9 5322 uint8_t att_type;
76a95d75 5323 int rc;
da0436e9
JS
5324
5325 att_type = lpfc_sli4_parse_latt_type(phba, acqe_link);
76a95d75 5326 if (att_type != LPFC_ATT_LINK_DOWN && att_type != LPFC_ATT_LINK_UP)
da0436e9 5327 return;
32b9793f 5328 phba->fcoe_eventtag = acqe_link->event_tag;
da0436e9
JS
5329 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
5330 if (!pmb) {
372c187b 5331 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
5332 "0395 The mboxq allocation failed\n");
5333 return;
5334 }
5335 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
5336 if (!mp) {
372c187b 5337 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
5338 "0396 The lpfc_dmabuf allocation failed\n");
5339 goto out_free_pmb;
5340 }
5341 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
5342 if (!mp->virt) {
372c187b 5343 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
5344 "0397 The mbuf allocation failed\n");
5345 goto out_free_dmabuf;
5346 }
5347
5348 /* Cleanup any outstanding ELS commands */
5349 lpfc_els_flush_all_cmd(phba);
5350
5351 /* Block ELS IOCBs until we have done process link event */
895427bd 5352 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
da0436e9
JS
5353
5354 /* Update link event statistics */
5355 phba->sli.slistat.link_event++;
5356
76a95d75
JS
5357 /* Create lpfc_handle_latt mailbox command from link ACQE */
5358 lpfc_read_topology(phba, pmb, mp);
5359 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
da0436e9
JS
5360 pmb->vport = phba->pport;
5361
da0436e9
JS
5362 /* Keep the link status for extra SLI4 state machine reference */
5363 phba->sli4_hba.link_state.speed =
8b68cd52
JS
5364 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_LINK,
5365 bf_get(lpfc_acqe_link_speed, acqe_link));
da0436e9
JS
5366 phba->sli4_hba.link_state.duplex =
5367 bf_get(lpfc_acqe_link_duplex, acqe_link);
5368 phba->sli4_hba.link_state.status =
5369 bf_get(lpfc_acqe_link_status, acqe_link);
70f3c073
JS
5370 phba->sli4_hba.link_state.type =
5371 bf_get(lpfc_acqe_link_type, acqe_link);
5372 phba->sli4_hba.link_state.number =
5373 bf_get(lpfc_acqe_link_number, acqe_link);
da0436e9
JS
5374 phba->sli4_hba.link_state.fault =
5375 bf_get(lpfc_acqe_link_fault, acqe_link);
65467b6b 5376 phba->sli4_hba.link_state.logical_speed =
8b68cd52
JS
5377 bf_get(lpfc_acqe_logical_link_speed, acqe_link) * 10;
5378
70f3c073 5379 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
c31098ce
JS
5380 "2900 Async FC/FCoE Link event - Speed:%dGBit "
5381 "duplex:x%x LA Type:x%x Port Type:%d Port Number:%d "
5382 "Logical speed:%dMbps Fault:%d\n",
70f3c073
JS
5383 phba->sli4_hba.link_state.speed,
5384 phba->sli4_hba.link_state.topology,
5385 phba->sli4_hba.link_state.status,
5386 phba->sli4_hba.link_state.type,
5387 phba->sli4_hba.link_state.number,
8b68cd52 5388 phba->sli4_hba.link_state.logical_speed,
70f3c073 5389 phba->sli4_hba.link_state.fault);
76a95d75
JS
5390 /*
5391 * For FC Mode: issue the READ_TOPOLOGY mailbox command to fetch
5392 * topology info. Note: Optional for non FC-AL ports.
5393 */
5394 if (!(phba->hba_flag & HBA_FCOE_MODE)) {
5395 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
f0d39196
JS
5396 if (rc == MBX_NOT_FINISHED) {
5397 lpfc_mbuf_free(phba, mp->virt, mp->phys);
76a95d75 5398 goto out_free_dmabuf;
f0d39196 5399 }
76a95d75
JS
5400 return;
5401 }
5402 /*
5403 * For FCoE Mode: fill in all the topology information we need and call
5404 * the READ_TOPOLOGY completion routine to continue without actually
5405 * sending the READ_TOPOLOGY mailbox command to the port.
5406 */
23288b78 5407 /* Initialize completion status */
76a95d75 5408 mb = &pmb->u.mb;
23288b78
JS
5409 mb->mbxStatus = MBX_SUCCESS;
5410
5411 /* Parse port fault information field */
5412 lpfc_sli4_parse_latt_fault(phba, acqe_link);
76a95d75
JS
5413
5414 /* Parse and translate link attention fields */
5415 la = (struct lpfc_mbx_read_top *) &pmb->u.mb.un.varReadTop;
5416 la->eventTag = acqe_link->event_tag;
5417 bf_set(lpfc_mbx_read_top_att_type, la, att_type);
5418 bf_set(lpfc_mbx_read_top_link_spd, la,
a085e87c 5419 (bf_get(lpfc_acqe_link_speed, acqe_link)));
76a95d75
JS
5420
5421 /* Fake the the following irrelvant fields */
5422 bf_set(lpfc_mbx_read_top_topology, la, LPFC_TOPOLOGY_PT_PT);
5423 bf_set(lpfc_mbx_read_top_alpa_granted, la, 0);
5424 bf_set(lpfc_mbx_read_top_il, la, 0);
5425 bf_set(lpfc_mbx_read_top_pb, la, 0);
5426 bf_set(lpfc_mbx_read_top_fa, la, 0);
5427 bf_set(lpfc_mbx_read_top_mm, la, 0);
da0436e9
JS
5428
5429 /* Invoke the lpfc_handle_latt mailbox command callback function */
76a95d75 5430 lpfc_mbx_cmpl_read_topology(phba, pmb);
da0436e9 5431
5b75da2f 5432 return;
da0436e9
JS
5433
5434out_free_dmabuf:
5435 kfree(mp);
5436out_free_pmb:
5437 mempool_free(pmb, phba->mbox_mem_pool);
5438}
5439
1dc5ec24
JS
5440/**
5441 * lpfc_async_link_speed_to_read_top - Parse async evt link speed code to read
5442 * topology.
5443 * @phba: pointer to lpfc hba data structure.
1dc5ec24
JS
5444 * @speed_code: asynchronous event link speed code.
5445 *
5446 * This routine is to parse the giving SLI4 async event link speed code into
5447 * value of Read topology link speed.
5448 *
5449 * Return: link speed in terms of Read topology.
5450 **/
5451static uint8_t
5452lpfc_async_link_speed_to_read_top(struct lpfc_hba *phba, uint8_t speed_code)
5453{
5454 uint8_t port_speed;
5455
5456 switch (speed_code) {
5457 case LPFC_FC_LA_SPEED_1G:
5458 port_speed = LPFC_LINK_SPEED_1GHZ;
5459 break;
5460 case LPFC_FC_LA_SPEED_2G:
5461 port_speed = LPFC_LINK_SPEED_2GHZ;
5462 break;
5463 case LPFC_FC_LA_SPEED_4G:
5464 port_speed = LPFC_LINK_SPEED_4GHZ;
5465 break;
5466 case LPFC_FC_LA_SPEED_8G:
5467 port_speed = LPFC_LINK_SPEED_8GHZ;
5468 break;
5469 case LPFC_FC_LA_SPEED_16G:
5470 port_speed = LPFC_LINK_SPEED_16GHZ;
5471 break;
5472 case LPFC_FC_LA_SPEED_32G:
5473 port_speed = LPFC_LINK_SPEED_32GHZ;
5474 break;
5475 case LPFC_FC_LA_SPEED_64G:
5476 port_speed = LPFC_LINK_SPEED_64GHZ;
5477 break;
5478 case LPFC_FC_LA_SPEED_128G:
5479 port_speed = LPFC_LINK_SPEED_128GHZ;
5480 break;
5481 case LPFC_FC_LA_SPEED_256G:
5482 port_speed = LPFC_LINK_SPEED_256GHZ;
5483 break;
5484 default:
5485 port_speed = 0;
5486 break;
5487 }
5488
5489 return port_speed;
5490}
5491
74a7baa2
JS
5492void
5493lpfc_cgn_dump_rxmonitor(struct lpfc_hba *phba)
5494{
5495 struct rxtable_entry *entry;
5496 int cnt = 0, head, tail, last, start;
5497
5498 head = atomic_read(&phba->rxtable_idx_head);
5499 tail = atomic_read(&phba->rxtable_idx_tail);
5500 if (!phba->rxtable || head == tail) {
5501 lpfc_printf_log(phba, KERN_ERR, LOG_CGN_MGMT,
5502 "4411 Rxtable is empty\n");
5503 return;
5504 }
5505 last = tail;
5506 start = head;
5507
5508 /* Display the last LPFC_MAX_RXMONITOR_DUMP entries from the rxtable */
5509 while (start != last) {
5510 if (start)
5511 start--;
5512 else
5513 start = LPFC_MAX_RXMONITOR_ENTRY - 1;
5514 entry = &phba->rxtable[start];
5515 lpfc_printf_log(phba, KERN_INFO, LOG_CGN_MGMT,
5516 "4410 %02d: MBPI %lld Xmit %lld Cmpl %lld "
5517 "Lat %lld ASz %lld Info %02d BWUtil %d "
5518 "Int %d slot %d\n",
5519 cnt, entry->max_bytes_per_interval,
5520 entry->total_bytes, entry->rcv_bytes,
5521 entry->avg_io_latency, entry->avg_io_size,
5522 entry->cmf_info, entry->timer_utilization,
5523 entry->timer_interval, start);
5524 cnt++;
5525 if (cnt >= LPFC_MAX_RXMONITOR_DUMP)
5526 return;
5527 }
5528}
5529
7481811c
JS
5530/**
5531 * lpfc_cgn_update_stat - Save data into congestion stats buffer
5532 * @phba: pointer to lpfc hba data structure.
5533 * @dtag: FPIN descriptor received
5534 *
5535 * Increment the FPIN received counter/time when it happens.
5536 */
5537void
5538lpfc_cgn_update_stat(struct lpfc_hba *phba, uint32_t dtag)
5539{
5540 struct lpfc_cgn_info *cp;
5541 struct tm broken;
5542 struct timespec64 cur_time;
5543 u32 cnt;
5295d19d 5544 u32 value;
7481811c
JS
5545
5546 /* Make sure we have a congestion info buffer */
5547 if (!phba->cgn_i)
5548 return;
5549 cp = (struct lpfc_cgn_info *)phba->cgn_i->virt;
5550 ktime_get_real_ts64(&cur_time);
5551 time64_to_tm(cur_time.tv_sec, 0, &broken);
5552
5553 /* Update congestion statistics */
5554 switch (dtag) {
5555 case ELS_DTAG_LNK_INTEGRITY:
5556 cnt = le32_to_cpu(cp->link_integ_notification);
5557 cnt++;
5558 cp->link_integ_notification = cpu_to_le32(cnt);
5559
5560 cp->cgn_stat_lnk_month = broken.tm_mon + 1;
5561 cp->cgn_stat_lnk_day = broken.tm_mday;
5562 cp->cgn_stat_lnk_year = broken.tm_year - 100;
5563 cp->cgn_stat_lnk_hour = broken.tm_hour;
5564 cp->cgn_stat_lnk_min = broken.tm_min;
5565 cp->cgn_stat_lnk_sec = broken.tm_sec;
5566 break;
5567 case ELS_DTAG_DELIVERY:
5568 cnt = le32_to_cpu(cp->delivery_notification);
5569 cnt++;
5570 cp->delivery_notification = cpu_to_le32(cnt);
5571
5572 cp->cgn_stat_del_month = broken.tm_mon + 1;
5573 cp->cgn_stat_del_day = broken.tm_mday;
5574 cp->cgn_stat_del_year = broken.tm_year - 100;
5575 cp->cgn_stat_del_hour = broken.tm_hour;
5576 cp->cgn_stat_del_min = broken.tm_min;
5577 cp->cgn_stat_del_sec = broken.tm_sec;
5578 break;
5579 case ELS_DTAG_PEER_CONGEST:
5580 cnt = le32_to_cpu(cp->cgn_peer_notification);
5581 cnt++;
5582 cp->cgn_peer_notification = cpu_to_le32(cnt);
5583
5584 cp->cgn_stat_peer_month = broken.tm_mon + 1;
5585 cp->cgn_stat_peer_day = broken.tm_mday;
5586 cp->cgn_stat_peer_year = broken.tm_year - 100;
5587 cp->cgn_stat_peer_hour = broken.tm_hour;
5588 cp->cgn_stat_peer_min = broken.tm_min;
5589 cp->cgn_stat_peer_sec = broken.tm_sec;
5590 break;
5591 case ELS_DTAG_CONGESTION:
5592 cnt = le32_to_cpu(cp->cgn_notification);
5593 cnt++;
5594 cp->cgn_notification = cpu_to_le32(cnt);
5595
5596 cp->cgn_stat_cgn_month = broken.tm_mon + 1;
5597 cp->cgn_stat_cgn_day = broken.tm_mday;
5598 cp->cgn_stat_cgn_year = broken.tm_year - 100;
5599 cp->cgn_stat_cgn_hour = broken.tm_hour;
5600 cp->cgn_stat_cgn_min = broken.tm_min;
5601 cp->cgn_stat_cgn_sec = broken.tm_sec;
5602 }
5603 if (phba->cgn_fpin_frequency &&
5604 phba->cgn_fpin_frequency != LPFC_FPIN_INIT_FREQ) {
5605 value = LPFC_CGN_TIMER_TO_MIN / phba->cgn_fpin_frequency;
59936430 5606 cp->cgn_stat_npm = value;
7481811c
JS
5607 }
5608 value = lpfc_cgn_calc_crc32(cp, LPFC_CGN_INFO_SZ,
5609 LPFC_CGN_CRC32_SEED);
5610 cp->cgn_info_crc = cpu_to_le32(value);
5611}
5612
5613/**
5614 * lpfc_cgn_save_evt_cnt - Save data into registered congestion buffer
5615 * @phba: pointer to lpfc hba data structure.
5616 *
5617 * Save the congestion event data every minute.
5618 * On the hour collapse all the minute data into hour data. Every day
5619 * collapse all the hour data into daily data. Separate driver
5620 * and fabrc congestion event counters that will be saved out
5621 * to the registered congestion buffer every minute.
5622 */
5623static void
5624lpfc_cgn_save_evt_cnt(struct lpfc_hba *phba)
5625{
5626 struct lpfc_cgn_info *cp;
5627 struct tm broken;
5628 struct timespec64 cur_time;
5629 uint32_t i, index;
5630 uint16_t value, mvalue;
5631 uint64_t bps;
5632 uint32_t mbps;
5633 uint32_t dvalue, wvalue, lvalue, avalue;
5634 uint64_t latsum;
59936430
JS
5635 __le16 *ptr;
5636 __le32 *lptr;
5637 __le16 *mptr;
7481811c
JS
5638
5639 /* Make sure we have a congestion info buffer */
5640 if (!phba->cgn_i)
5641 return;
5642 cp = (struct lpfc_cgn_info *)phba->cgn_i->virt;
5643
5644 if (time_before(jiffies, phba->cgn_evt_timestamp))
5645 return;
5646 phba->cgn_evt_timestamp = jiffies +
5647 msecs_to_jiffies(LPFC_CGN_TIMER_TO_MIN);
5648 phba->cgn_evt_minute++;
5649
5650 /* We should get to this point in the routine on 1 minute intervals */
5651
5652 ktime_get_real_ts64(&cur_time);
5653 time64_to_tm(cur_time.tv_sec, 0, &broken);
5654
5655 if (phba->cgn_fpin_frequency &&
5656 phba->cgn_fpin_frequency != LPFC_FPIN_INIT_FREQ) {
5657 value = LPFC_CGN_TIMER_TO_MIN / phba->cgn_fpin_frequency;
59936430 5658 cp->cgn_stat_npm = value;
7481811c
JS
5659 }
5660
5661 /* Read and clear the latency counters for this minute */
5662 lvalue = atomic_read(&phba->cgn_latency_evt_cnt);
5663 latsum = atomic64_read(&phba->cgn_latency_evt);
5664 atomic_set(&phba->cgn_latency_evt_cnt, 0);
5665 atomic64_set(&phba->cgn_latency_evt, 0);
5666
5667 /* We need to store MB/sec bandwidth in the congestion information.
5668 * block_cnt is count of 512 byte blocks for the entire minute,
5669 * bps will get bytes per sec before finally converting to MB/sec.
5670 */
5671 bps = div_u64(phba->rx_block_cnt, LPFC_SEC_MIN) * 512;
5672 phba->rx_block_cnt = 0;
5673 mvalue = bps / (1024 * 1024); /* convert to MB/sec */
5674
5675 /* Every minute */
5676 /* cgn parameters */
5677 cp->cgn_info_mode = phba->cgn_p.cgn_param_mode;
5678 cp->cgn_info_level0 = phba->cgn_p.cgn_param_level0;
5679 cp->cgn_info_level1 = phba->cgn_p.cgn_param_level1;
5680 cp->cgn_info_level2 = phba->cgn_p.cgn_param_level2;
5681
5682 /* Fill in default LUN qdepth */
5683 value = (uint16_t)(phba->pport->cfg_lun_queue_depth);
5684 cp->cgn_lunq = cpu_to_le16(value);
5685
5686 /* Record congestion buffer info - every minute
5687 * cgn_driver_evt_cnt (Driver events)
5688 * cgn_fabric_warn_cnt (Congestion Warnings)
5689 * cgn_latency_evt_cnt / cgn_latency_evt (IO Latency)
5690 * cgn_fabric_alarm_cnt (Congestion Alarms)
5691 */
5692 index = ++cp->cgn_index_minute;
5693 if (cp->cgn_index_minute == LPFC_MIN_HOUR) {
5694 cp->cgn_index_minute = 0;
5695 index = 0;
5696 }
5697
5698 /* Get the number of driver events in this sample and reset counter */
5699 dvalue = atomic_read(&phba->cgn_driver_evt_cnt);
5700 atomic_set(&phba->cgn_driver_evt_cnt, 0);
5701
5702 /* Get the number of warning events - FPIN and Signal for this minute */
5703 wvalue = 0;
5704 if ((phba->cgn_reg_fpin & LPFC_CGN_FPIN_WARN) ||
5705 phba->cgn_reg_signal == EDC_CG_SIG_WARN_ONLY ||
5706 phba->cgn_reg_signal == EDC_CG_SIG_WARN_ALARM)
5707 wvalue = atomic_read(&phba->cgn_fabric_warn_cnt);
5708 atomic_set(&phba->cgn_fabric_warn_cnt, 0);
5709
5710 /* Get the number of alarm events - FPIN and Signal for this minute */
5711 avalue = 0;
5712 if ((phba->cgn_reg_fpin & LPFC_CGN_FPIN_ALARM) ||
5713 phba->cgn_reg_signal == EDC_CG_SIG_WARN_ALARM)
5714 avalue = atomic_read(&phba->cgn_fabric_alarm_cnt);
5715 atomic_set(&phba->cgn_fabric_alarm_cnt, 0);
5716
5717 /* Collect the driver, warning, alarm and latency counts for this
5718 * minute into the driver congestion buffer.
5719 */
5720 ptr = &cp->cgn_drvr_min[index];
5721 value = (uint16_t)dvalue;
5722 *ptr = cpu_to_le16(value);
5723
5724 ptr = &cp->cgn_warn_min[index];
5725 value = (uint16_t)wvalue;
5726 *ptr = cpu_to_le16(value);
5727
5728 ptr = &cp->cgn_alarm_min[index];
5729 value = (uint16_t)avalue;
5730 *ptr = cpu_to_le16(value);
5731
5732 lptr = &cp->cgn_latency_min[index];
5733 if (lvalue) {
5734 lvalue = (uint32_t)div_u64(latsum, lvalue);
5735 *lptr = cpu_to_le32(lvalue);
5736 } else {
5737 *lptr = 0;
5738 }
5739
5740 /* Collect the bandwidth value into the driver's congesion buffer. */
5741 mptr = &cp->cgn_bw_min[index];
5742 *mptr = cpu_to_le16(mvalue);
5743
5744 lpfc_printf_log(phba, KERN_INFO, LOG_CGN_MGMT,
5745 "2418 Congestion Info - minute (%d): %d %d %d %d %d\n",
5746 index, dvalue, wvalue, *lptr, mvalue, avalue);
5747
5748 /* Every hour */
5749 if ((phba->cgn_evt_minute % LPFC_MIN_HOUR) == 0) {
5750 /* Record congestion buffer info - every hour
5751 * Collapse all minutes into an hour
5752 */
5753 index = ++cp->cgn_index_hour;
5754 if (cp->cgn_index_hour == LPFC_HOUR_DAY) {
5755 cp->cgn_index_hour = 0;
5756 index = 0;
5757 }
5758
5759 dvalue = 0;
5760 wvalue = 0;
5761 lvalue = 0;
5762 avalue = 0;
5763 mvalue = 0;
5764 mbps = 0;
5765 for (i = 0; i < LPFC_MIN_HOUR; i++) {
5766 dvalue += le16_to_cpu(cp->cgn_drvr_min[i]);
5767 wvalue += le16_to_cpu(cp->cgn_warn_min[i]);
5768 lvalue += le32_to_cpu(cp->cgn_latency_min[i]);
5769 mbps += le16_to_cpu(cp->cgn_bw_min[i]);
5770 avalue += le16_to_cpu(cp->cgn_alarm_min[i]);
5771 }
5772 if (lvalue) /* Avg of latency averages */
5773 lvalue /= LPFC_MIN_HOUR;
5774 if (mbps) /* Avg of Bandwidth averages */
5775 mvalue = mbps / LPFC_MIN_HOUR;
5776
5777 lptr = &cp->cgn_drvr_hr[index];
5778 *lptr = cpu_to_le32(dvalue);
5779 lptr = &cp->cgn_warn_hr[index];
5780 *lptr = cpu_to_le32(wvalue);
5781 lptr = &cp->cgn_latency_hr[index];
5782 *lptr = cpu_to_le32(lvalue);
5783 mptr = &cp->cgn_bw_hr[index];
5784 *mptr = cpu_to_le16(mvalue);
5785 lptr = &cp->cgn_alarm_hr[index];
5786 *lptr = cpu_to_le32(avalue);
5787
5788 lpfc_printf_log(phba, KERN_INFO, LOG_CGN_MGMT,
5789 "2419 Congestion Info - hour "
5790 "(%d): %d %d %d %d %d\n",
5791 index, dvalue, wvalue, lvalue, mvalue, avalue);
5792 }
5793
5794 /* Every day */
5795 if ((phba->cgn_evt_minute % LPFC_MIN_DAY) == 0) {
5796 /* Record congestion buffer info - every hour
5797 * Collapse all hours into a day. Rotate days
5798 * after LPFC_MAX_CGN_DAYS.
5799 */
5800 index = ++cp->cgn_index_day;
5801 if (cp->cgn_index_day == LPFC_MAX_CGN_DAYS) {
5802 cp->cgn_index_day = 0;
5803 index = 0;
5804 }
5805
5806 /* Anytime we overwrite daily index 0, after we wrap,
5807 * we will be overwriting the oldest day, so we must
5808 * update the congestion data start time for that day.
5809 * That start time should have previously been saved after
5810 * we wrote the last days worth of data.
5811 */
5812 if ((phba->hba_flag & HBA_CGN_DAY_WRAP) && index == 0) {
5813 time64_to_tm(phba->cgn_daily_ts.tv_sec, 0, &broken);
5814
5815 cp->cgn_info_month = broken.tm_mon + 1;
5816 cp->cgn_info_day = broken.tm_mday;
5817 cp->cgn_info_year = broken.tm_year - 100;
5818 cp->cgn_info_hour = broken.tm_hour;
5819 cp->cgn_info_minute = broken.tm_min;
5820 cp->cgn_info_second = broken.tm_sec;
5821
5822 lpfc_printf_log
5823 (phba, KERN_INFO, LOG_CGN_MGMT,
5824 "2646 CGNInfo idx0 Start Time: "
5825 "%d/%d/%d %d:%d:%d\n",
5826 cp->cgn_info_day, cp->cgn_info_month,
5827 cp->cgn_info_year, cp->cgn_info_hour,
5828 cp->cgn_info_minute, cp->cgn_info_second);
5829 }
5830
5831 dvalue = 0;
5832 wvalue = 0;
5833 lvalue = 0;
5834 mvalue = 0;
5835 mbps = 0;
5836 avalue = 0;
5837 for (i = 0; i < LPFC_HOUR_DAY; i++) {
5838 dvalue += le32_to_cpu(cp->cgn_drvr_hr[i]);
5839 wvalue += le32_to_cpu(cp->cgn_warn_hr[i]);
5840 lvalue += le32_to_cpu(cp->cgn_latency_hr[i]);
59936430 5841 mbps += le16_to_cpu(cp->cgn_bw_hr[i]);
7481811c
JS
5842 avalue += le32_to_cpu(cp->cgn_alarm_hr[i]);
5843 }
5844 if (lvalue) /* Avg of latency averages */
5845 lvalue /= LPFC_HOUR_DAY;
5846 if (mbps) /* Avg of Bandwidth averages */
5847 mvalue = mbps / LPFC_HOUR_DAY;
5848
5849 lptr = &cp->cgn_drvr_day[index];
5850 *lptr = cpu_to_le32(dvalue);
5851 lptr = &cp->cgn_warn_day[index];
5852 *lptr = cpu_to_le32(wvalue);
5853 lptr = &cp->cgn_latency_day[index];
5854 *lptr = cpu_to_le32(lvalue);
5855 mptr = &cp->cgn_bw_day[index];
5856 *mptr = cpu_to_le16(mvalue);
5857 lptr = &cp->cgn_alarm_day[index];
5858 *lptr = cpu_to_le32(avalue);
5859
5860 lpfc_printf_log(phba, KERN_INFO, LOG_CGN_MGMT,
5861 "2420 Congestion Info - daily (%d): "
5862 "%d %d %d %d %d\n",
5863 index, dvalue, wvalue, lvalue, mvalue, avalue);
5864
5865 /* We just wrote LPFC_MAX_CGN_DAYS of data,
5866 * so we are wrapped on any data after this.
5867 * Save this as the start time for the next day.
5868 */
5869 if (index == (LPFC_MAX_CGN_DAYS - 1)) {
5870 phba->hba_flag |= HBA_CGN_DAY_WRAP;
5871 ktime_get_real_ts64(&phba->cgn_daily_ts);
5872 }
5873 }
5874
5875 /* Use the frequency found in the last rcv'ed FPIN */
5876 value = phba->cgn_fpin_frequency;
5877 if (phba->cgn_reg_fpin & LPFC_CGN_FPIN_WARN)
5878 cp->cgn_warn_freq = cpu_to_le16(value);
5879 if (phba->cgn_reg_fpin & LPFC_CGN_FPIN_ALARM)
5880 cp->cgn_alarm_freq = cpu_to_le16(value);
5881
5882 /* Frequency (in ms) Signal Warning/Signal Congestion Notifications
5883 * are received by the HBA
5884 */
5885 value = phba->cgn_sig_freq;
5886
5887 if (phba->cgn_reg_signal == EDC_CG_SIG_WARN_ONLY ||
5888 phba->cgn_reg_signal == EDC_CG_SIG_WARN_ALARM)
5889 cp->cgn_warn_freq = cpu_to_le16(value);
5890 if (phba->cgn_reg_signal == EDC_CG_SIG_WARN_ALARM)
5891 cp->cgn_alarm_freq = cpu_to_le16(value);
5892
5893 lvalue = lpfc_cgn_calc_crc32(cp, LPFC_CGN_INFO_SZ,
5894 LPFC_CGN_CRC32_SEED);
5895 cp->cgn_info_crc = cpu_to_le32(lvalue);
5896}
5897
02243836
JS
5898/**
5899 * lpfc_calc_cmf_latency - latency from start of rxate timer interval
5900 * @phba: The Hba for which this call is being executed.
5901 *
5902 * The routine calculates the latency from the beginning of the CMF timer
5903 * interval to the current point in time. It is called from IO completion
5904 * when we exceed our Bandwidth limitation for the time interval.
5905 */
5906uint32_t
5907lpfc_calc_cmf_latency(struct lpfc_hba *phba)
5908{
5909 struct timespec64 cmpl_time;
5910 uint32_t msec = 0;
5911
5912 ktime_get_real_ts64(&cmpl_time);
5913
5914 /* This routine works on a ms granularity so sec and usec are
5915 * converted accordingly.
5916 */
5917 if (cmpl_time.tv_sec == phba->cmf_latency.tv_sec) {
5918 msec = (cmpl_time.tv_nsec - phba->cmf_latency.tv_nsec) /
5919 NSEC_PER_MSEC;
5920 } else {
5921 if (cmpl_time.tv_nsec >= phba->cmf_latency.tv_nsec) {
5922 msec = (cmpl_time.tv_sec -
5923 phba->cmf_latency.tv_sec) * MSEC_PER_SEC;
5924 msec += ((cmpl_time.tv_nsec -
5925 phba->cmf_latency.tv_nsec) / NSEC_PER_MSEC);
5926 } else {
5927 msec = (cmpl_time.tv_sec - phba->cmf_latency.tv_sec -
5928 1) * MSEC_PER_SEC;
5929 msec += (((NSEC_PER_SEC - phba->cmf_latency.tv_nsec) +
5930 cmpl_time.tv_nsec) / NSEC_PER_MSEC);
5931 }
5932 }
5933 return msec;
5934}
5935
5936/**
5937 * lpfc_cmf_timer - This is the timer function for one congestion
5938 * rate interval.
5939 * @timer: Pointer to the high resolution timer that expired
5940 */
5941static enum hrtimer_restart
5942lpfc_cmf_timer(struct hrtimer *timer)
5943{
5944 struct lpfc_hba *phba = container_of(timer, struct lpfc_hba,
5945 cmf_timer);
17b27ac5 5946 struct rxtable_entry *entry;
02243836 5947 uint32_t io_cnt;
17b27ac5
JS
5948 uint32_t head, tail;
5949 uint32_t busy, max_read;
a6269f83 5950 uint64_t total, rcv, lat, mbpi, extra, cnt;
02243836 5951 int timer_interval = LPFC_CMF_INTERVAL;
17b27ac5 5952 uint32_t ms;
02243836
JS
5953 struct lpfc_cgn_stat *cgs;
5954 int cpu;
5955
5956 /* Only restart the timer if congestion mgmt is on */
5957 if (phba->cmf_active_mode == LPFC_CFG_OFF ||
5958 !phba->cmf_latency.tv_sec) {
5959 lpfc_printf_log(phba, KERN_INFO, LOG_CGN_MGMT,
5960 "6224 CMF timer exit: %d %lld\n",
5961 phba->cmf_active_mode,
5962 (uint64_t)phba->cmf_latency.tv_sec);
5963 return HRTIMER_NORESTART;
5964 }
5965
5966 /* If pport is not ready yet, just exit and wait for
5967 * the next timer cycle to hit.
5968 */
5969 if (!phba->pport)
5970 goto skip;
5971
5972 /* Do not block SCSI IO while in the timer routine since
5973 * total_bytes will be cleared
5974 */
5975 atomic_set(&phba->cmf_stop_io, 1);
5976
17b27ac5
JS
5977 /* First we need to calculate the actual ms between
5978 * the last timer interrupt and this one. We ask for
5979 * LPFC_CMF_INTERVAL, however the actual time may
5980 * vary depending on system overhead.
5981 */
5982 ms = lpfc_calc_cmf_latency(phba);
5983
5984
02243836
JS
5985 /* Immediately after we calculate the time since the last
5986 * timer interrupt, set the start time for the next
5987 * interrupt
5988 */
5989 ktime_get_real_ts64(&phba->cmf_latency);
5990
5991 phba->cmf_link_byte_count =
5992 div_u64(phba->cmf_max_line_rate * LPFC_CMF_INTERVAL, 1000);
5993
5994 /* Collect all the stats from the prior timer interval */
5995 total = 0;
5996 io_cnt = 0;
5997 lat = 0;
5998 rcv = 0;
5999 for_each_present_cpu(cpu) {
6000 cgs = per_cpu_ptr(phba->cmf_stat, cpu);
6001 total += atomic64_xchg(&cgs->total_bytes, 0);
6002 io_cnt += atomic_xchg(&cgs->rx_io_cnt, 0);
6003 lat += atomic64_xchg(&cgs->rx_latency, 0);
6004 rcv += atomic64_xchg(&cgs->rcv_bytes, 0);
6005 }
6006
6007 /* Before we issue another CMF_SYNC_WQE, retrieve the BW
6008 * returned from the last CMF_SYNC_WQE issued, from
6009 * cmf_last_sync_bw. This will be the target BW for
6010 * this next timer interval.
6011 */
6012 if (phba->cmf_active_mode == LPFC_CFG_MANAGED &&
6013 phba->link_state != LPFC_LINK_DOWN &&
6014 phba->hba_flag & HBA_SETUP) {
6015 mbpi = phba->cmf_last_sync_bw;
6016 phba->cmf_last_sync_bw = 0;
d5ac69b3
JS
6017 extra = 0;
6018
6019 /* Calculate any extra bytes needed to account for the
6020 * timer accuracy. If we are less than LPFC_CMF_INTERVAL
a6269f83
JS
6021 * calculate the adjustment needed for total to reflect
6022 * a full LPFC_CMF_INTERVAL.
d5ac69b3 6023 */
a6269f83
JS
6024 if (ms && ms < LPFC_CMF_INTERVAL) {
6025 cnt = div_u64(total, ms); /* bytes per ms */
6026 cnt *= LPFC_CMF_INTERVAL; /* what total should be */
05116ef9
JS
6027
6028 /* If the timeout is scheduled to be shorter,
6029 * this value may skew the data, so cap it at mbpi.
6030 */
6031 if ((phba->hba_flag & HBA_SHORT_CMF) && cnt > mbpi)
a6269f83 6032 cnt = mbpi;
05116ef9 6033
a6269f83
JS
6034 extra = cnt - total;
6035 }
d5ac69b3 6036 lpfc_issue_cmf_sync_wqe(phba, LPFC_CMF_INTERVAL, total + extra);
02243836
JS
6037 } else {
6038 /* For Monitor mode or link down we want mbpi
6039 * to be the full link speed
6040 */
6041 mbpi = phba->cmf_link_byte_count;
a6269f83 6042 extra = 0;
02243836
JS
6043 }
6044 phba->cmf_timer_cnt++;
6045
6046 if (io_cnt) {
6047 /* Update congestion info buffer latency in us */
6048 atomic_add(io_cnt, &phba->cgn_latency_evt_cnt);
6049 atomic64_add(lat, &phba->cgn_latency_evt);
6050 }
17b27ac5
JS
6051 busy = atomic_xchg(&phba->cmf_busy, 0);
6052 max_read = atomic_xchg(&phba->rx_max_read_cnt, 0);
02243836
JS
6053
6054 /* Calculate MBPI for the next timer interval */
6055 if (mbpi) {
6056 if (mbpi > phba->cmf_link_byte_count ||
6057 phba->cmf_active_mode == LPFC_CFG_MONITOR)
6058 mbpi = phba->cmf_link_byte_count;
6059
6060 /* Change max_bytes_per_interval to what the prior
6061 * CMF_SYNC_WQE cmpl indicated.
6062 */
6063 if (mbpi != phba->cmf_max_bytes_per_interval)
6064 phba->cmf_max_bytes_per_interval = mbpi;
6065 }
6066
17b27ac5
JS
6067 /* Save rxmonitor information for debug */
6068 if (phba->rxtable) {
6069 head = atomic_xchg(&phba->rxtable_idx_head,
6070 LPFC_RXMONITOR_TABLE_IN_USE);
6071 entry = &phba->rxtable[head];
6072 entry->total_bytes = total;
a6269f83 6073 entry->cmf_bytes = total + extra;
17b27ac5
JS
6074 entry->rcv_bytes = rcv;
6075 entry->cmf_busy = busy;
6076 entry->cmf_info = phba->cmf_active_info;
6077 if (io_cnt) {
6078 entry->avg_io_latency = div_u64(lat, io_cnt);
6079 entry->avg_io_size = div_u64(rcv, io_cnt);
6080 } else {
6081 entry->avg_io_latency = 0;
6082 entry->avg_io_size = 0;
6083 }
6084 entry->max_read_cnt = max_read;
6085 entry->io_cnt = io_cnt;
6086 entry->max_bytes_per_interval = mbpi;
6087 if (phba->cmf_active_mode == LPFC_CFG_MANAGED)
6088 entry->timer_utilization = phba->cmf_last_ts;
6089 else
6090 entry->timer_utilization = ms;
6091 entry->timer_interval = ms;
6092 phba->cmf_last_ts = 0;
6093
6094 /* Increment rxtable index */
6095 head = (head + 1) % LPFC_MAX_RXMONITOR_ENTRY;
6096 tail = atomic_read(&phba->rxtable_idx_tail);
6097 if (head == tail) {
6098 tail = (tail + 1) % LPFC_MAX_RXMONITOR_ENTRY;
6099 atomic_set(&phba->rxtable_idx_tail, tail);
6100 }
6101 atomic_set(&phba->rxtable_idx_head, head);
6102 }
6103
02243836
JS
6104 if (phba->cmf_active_mode == LPFC_CFG_MONITOR) {
6105 /* If Monitor mode, check if we are oversubscribed
6106 * against the full line rate.
6107 */
6108 if (mbpi && total > mbpi)
6109 atomic_inc(&phba->cgn_driver_evt_cnt);
6110 }
6111 phba->rx_block_cnt += div_u64(rcv, 512); /* save 512 byte block cnt */
6112
7481811c
JS
6113 /* Each minute save Fabric and Driver congestion information */
6114 lpfc_cgn_save_evt_cnt(phba);
6115
05116ef9
JS
6116 phba->hba_flag &= ~HBA_SHORT_CMF;
6117
7481811c
JS
6118 /* Since we need to call lpfc_cgn_save_evt_cnt every minute, on the
6119 * minute, adjust our next timer interval, if needed, to ensure a
6120 * 1 minute granularity when we get the next timer interrupt.
6121 */
6122 if (time_after(jiffies + msecs_to_jiffies(LPFC_CMF_INTERVAL),
6123 phba->cgn_evt_timestamp)) {
6124 timer_interval = jiffies_to_msecs(phba->cgn_evt_timestamp -
6125 jiffies);
6126 if (timer_interval <= 0)
6127 timer_interval = LPFC_CMF_INTERVAL;
05116ef9
JS
6128 else
6129 phba->hba_flag |= HBA_SHORT_CMF;
7481811c
JS
6130
6131 /* If we adjust timer_interval, max_bytes_per_interval
6132 * needs to be adjusted as well.
6133 */
6134 phba->cmf_link_byte_count = div_u64(phba->cmf_max_line_rate *
6135 timer_interval, 1000);
6136 if (phba->cmf_active_mode == LPFC_CFG_MONITOR)
6137 phba->cmf_max_bytes_per_interval =
6138 phba->cmf_link_byte_count;
6139 }
6140
02243836
JS
6141 /* Since total_bytes has already been zero'ed, its okay to unblock
6142 * after max_bytes_per_interval is setup.
6143 */
6144 if (atomic_xchg(&phba->cmf_bw_wait, 0))
6145 queue_work(phba->wq, &phba->unblock_request_work);
6146
6147 /* SCSI IO is now unblocked */
6148 atomic_set(&phba->cmf_stop_io, 0);
6149
6150skip:
6151 hrtimer_forward_now(timer,
6152 ktime_set(0, timer_interval * NSEC_PER_MSEC));
6153 return HRTIMER_RESTART;
6154}
6155
1dc5ec24
JS
6156#define trunk_link_status(__idx)\
6157 bf_get(lpfc_acqe_fc_la_trunk_config_port##__idx, acqe_fc) ?\
6158 ((phba->trunk_link.link##__idx.state == LPFC_LINK_UP) ?\
6159 "Link up" : "Link down") : "NA"
6160/* Did port __idx reported an error */
6161#define trunk_port_fault(__idx)\
6162 bf_get(lpfc_acqe_fc_la_trunk_config_port##__idx, acqe_fc) ?\
6163 (port_fault & (1 << __idx) ? "YES" : "NO") : "NA"
6164
6165static void
6166lpfc_update_trunk_link_status(struct lpfc_hba *phba,
6167 struct lpfc_acqe_fc_la *acqe_fc)
6168{
6169 uint8_t port_fault = bf_get(lpfc_acqe_fc_la_trunk_linkmask, acqe_fc);
6170 uint8_t err = bf_get(lpfc_acqe_fc_la_trunk_fault, acqe_fc);
6171
6172 phba->sli4_hba.link_state.speed =
6173 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
6174 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
6175
6176 phba->sli4_hba.link_state.logical_speed =
b8e6f136 6177 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
1dc5ec24
JS
6178 /* We got FC link speed, convert to fc_linkspeed (READ_TOPOLOGY) */
6179 phba->fc_linkspeed =
6180 lpfc_async_link_speed_to_read_top(
6181 phba,
6182 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
6183
6184 if (bf_get(lpfc_acqe_fc_la_trunk_config_port0, acqe_fc)) {
6185 phba->trunk_link.link0.state =
6186 bf_get(lpfc_acqe_fc_la_trunk_link_status_port0, acqe_fc)
6187 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 6188 phba->trunk_link.link0.fault = port_fault & 0x1 ? err : 0;
1dc5ec24
JS
6189 }
6190 if (bf_get(lpfc_acqe_fc_la_trunk_config_port1, acqe_fc)) {
6191 phba->trunk_link.link1.state =
6192 bf_get(lpfc_acqe_fc_la_trunk_link_status_port1, acqe_fc)
6193 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 6194 phba->trunk_link.link1.fault = port_fault & 0x2 ? err : 0;
1dc5ec24
JS
6195 }
6196 if (bf_get(lpfc_acqe_fc_la_trunk_config_port2, acqe_fc)) {
6197 phba->trunk_link.link2.state =
6198 bf_get(lpfc_acqe_fc_la_trunk_link_status_port2, acqe_fc)
6199 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 6200 phba->trunk_link.link2.fault = port_fault & 0x4 ? err : 0;
1dc5ec24
JS
6201 }
6202 if (bf_get(lpfc_acqe_fc_la_trunk_config_port3, acqe_fc)) {
6203 phba->trunk_link.link3.state =
6204 bf_get(lpfc_acqe_fc_la_trunk_link_status_port3, acqe_fc)
6205 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 6206 phba->trunk_link.link3.fault = port_fault & 0x8 ? err : 0;
1dc5ec24
JS
6207 }
6208
372c187b 6209 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1dc5ec24
JS
6210 "2910 Async FC Trunking Event - Speed:%d\n"
6211 "\tLogical speed:%d "
6212 "port0: %s port1: %s port2: %s port3: %s\n",
6213 phba->sli4_hba.link_state.speed,
6214 phba->sli4_hba.link_state.logical_speed,
6215 trunk_link_status(0), trunk_link_status(1),
6216 trunk_link_status(2), trunk_link_status(3));
6217
02243836
JS
6218 if (phba->cmf_active_mode != LPFC_CFG_OFF)
6219 lpfc_cmf_signal_init(phba);
6220
1dc5ec24 6221 if (port_fault)
372c187b 6222 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1dc5ec24
JS
6223 "3202 trunk error:0x%x (%s) seen on port0:%s "
6224 /*
6225 * SLI-4: We have only 0xA error codes
6226 * defined as of now. print an appropriate
6227 * message in case driver needs to be updated.
6228 */
6229 "port1:%s port2:%s port3:%s\n", err, err > 0xA ?
6230 "UNDEFINED. update driver." : trunk_errmsg[err],
6231 trunk_port_fault(0), trunk_port_fault(1),
6232 trunk_port_fault(2), trunk_port_fault(3));
6233}
6234
6235
70f3c073
JS
6236/**
6237 * lpfc_sli4_async_fc_evt - Process the asynchronous FC link event
6238 * @phba: pointer to lpfc hba data structure.
6239 * @acqe_fc: pointer to the async fc completion queue entry.
6240 *
6241 * This routine is to handle the SLI4 asynchronous FC event. It will simply log
6242 * that the event was received and then issue a read_topology mailbox command so
6243 * that the rest of the driver will treat it the same as SLI3.
6244 **/
6245static void
6246lpfc_sli4_async_fc_evt(struct lpfc_hba *phba, struct lpfc_acqe_fc_la *acqe_fc)
6247{
6248 struct lpfc_dmabuf *mp;
6249 LPFC_MBOXQ_t *pmb;
7bdedb34
JS
6250 MAILBOX_t *mb;
6251 struct lpfc_mbx_read_top *la;
70f3c073
JS
6252 int rc;
6253
6254 if (bf_get(lpfc_trailer_type, acqe_fc) !=
6255 LPFC_FC_LA_EVENT_TYPE_FC_LINK) {
372c187b 6256 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
70f3c073
JS
6257 "2895 Non FC link Event detected.(%d)\n",
6258 bf_get(lpfc_trailer_type, acqe_fc));
6259 return;
6260 }
1dc5ec24
JS
6261
6262 if (bf_get(lpfc_acqe_fc_la_att_type, acqe_fc) ==
6263 LPFC_FC_LA_TYPE_TRUNKING_EVENT) {
6264 lpfc_update_trunk_link_status(phba, acqe_fc);
6265 return;
6266 }
6267
70f3c073
JS
6268 /* Keep the link status for extra SLI4 state machine reference */
6269 phba->sli4_hba.link_state.speed =
8b68cd52
JS
6270 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
6271 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
70f3c073
JS
6272 phba->sli4_hba.link_state.duplex = LPFC_ASYNC_LINK_DUPLEX_FULL;
6273 phba->sli4_hba.link_state.topology =
6274 bf_get(lpfc_acqe_fc_la_topology, acqe_fc);
6275 phba->sli4_hba.link_state.status =
6276 bf_get(lpfc_acqe_fc_la_att_type, acqe_fc);
6277 phba->sli4_hba.link_state.type =
6278 bf_get(lpfc_acqe_fc_la_port_type, acqe_fc);
6279 phba->sli4_hba.link_state.number =
6280 bf_get(lpfc_acqe_fc_la_port_number, acqe_fc);
6281 phba->sli4_hba.link_state.fault =
6282 bf_get(lpfc_acqe_link_fault, acqe_fc);
b8e6f136
JS
6283
6284 if (bf_get(lpfc_acqe_fc_la_att_type, acqe_fc) ==
6285 LPFC_FC_LA_TYPE_LINK_DOWN)
6286 phba->sli4_hba.link_state.logical_speed = 0;
6287 else if (!phba->sli4_hba.conf_trunk)
6288 phba->sli4_hba.link_state.logical_speed =
8b68cd52 6289 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
b8e6f136 6290
70f3c073
JS
6291 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
6292 "2896 Async FC event - Speed:%dGBaud Topology:x%x "
6293 "LA Type:x%x Port Type:%d Port Number:%d Logical speed:"
6294 "%dMbps Fault:%d\n",
6295 phba->sli4_hba.link_state.speed,
6296 phba->sli4_hba.link_state.topology,
6297 phba->sli4_hba.link_state.status,
6298 phba->sli4_hba.link_state.type,
6299 phba->sli4_hba.link_state.number,
8b68cd52 6300 phba->sli4_hba.link_state.logical_speed,
70f3c073
JS
6301 phba->sli4_hba.link_state.fault);
6302 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
6303 if (!pmb) {
372c187b 6304 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
70f3c073
JS
6305 "2897 The mboxq allocation failed\n");
6306 return;
6307 }
6308 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
6309 if (!mp) {
372c187b 6310 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
70f3c073
JS
6311 "2898 The lpfc_dmabuf allocation failed\n");
6312 goto out_free_pmb;
6313 }
6314 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
6315 if (!mp->virt) {
372c187b 6316 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
70f3c073
JS
6317 "2899 The mbuf allocation failed\n");
6318 goto out_free_dmabuf;
6319 }
6320
6321 /* Cleanup any outstanding ELS commands */
6322 lpfc_els_flush_all_cmd(phba);
6323
6324 /* Block ELS IOCBs until we have done process link event */
895427bd 6325 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
70f3c073
JS
6326
6327 /* Update link event statistics */
6328 phba->sli.slistat.link_event++;
6329
6330 /* Create lpfc_handle_latt mailbox command from link ACQE */
6331 lpfc_read_topology(phba, pmb, mp);
6332 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
6333 pmb->vport = phba->pport;
6334
7bdedb34 6335 if (phba->sli4_hba.link_state.status != LPFC_FC_LA_TYPE_LINK_UP) {
ae9e28f3
JS
6336 phba->link_flag &= ~(LS_MDS_LINK_DOWN | LS_MDS_LOOPBACK);
6337
6338 switch (phba->sli4_hba.link_state.status) {
6339 case LPFC_FC_LA_TYPE_MDS_LINK_DOWN:
6340 phba->link_flag |= LS_MDS_LINK_DOWN;
6341 break;
6342 case LPFC_FC_LA_TYPE_MDS_LOOPBACK:
6343 phba->link_flag |= LS_MDS_LOOPBACK;
6344 break;
6345 default:
6346 break;
6347 }
6348
23288b78 6349 /* Initialize completion status */
7bdedb34 6350 mb = &pmb->u.mb;
23288b78
JS
6351 mb->mbxStatus = MBX_SUCCESS;
6352
6353 /* Parse port fault information field */
6354 lpfc_sli4_parse_latt_fault(phba, (void *)acqe_fc);
7bdedb34
JS
6355
6356 /* Parse and translate link attention fields */
6357 la = (struct lpfc_mbx_read_top *)&pmb->u.mb.un.varReadTop;
6358 la->eventTag = acqe_fc->event_tag;
7bdedb34 6359
aeb3c817
JS
6360 if (phba->sli4_hba.link_state.status ==
6361 LPFC_FC_LA_TYPE_UNEXP_WWPN) {
6362 bf_set(lpfc_mbx_read_top_att_type, la,
6363 LPFC_FC_LA_TYPE_UNEXP_WWPN);
6364 } else {
6365 bf_set(lpfc_mbx_read_top_att_type, la,
6366 LPFC_FC_LA_TYPE_LINK_DOWN);
6367 }
7bdedb34
JS
6368 /* Invoke the mailbox command callback function */
6369 lpfc_mbx_cmpl_read_topology(phba, pmb);
6370
6371 return;
6372 }
6373
70f3c073 6374 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
f0d39196
JS
6375 if (rc == MBX_NOT_FINISHED) {
6376 lpfc_mbuf_free(phba, mp->virt, mp->phys);
70f3c073 6377 goto out_free_dmabuf;
f0d39196 6378 }
70f3c073
JS
6379 return;
6380
6381out_free_dmabuf:
6382 kfree(mp);
6383out_free_pmb:
6384 mempool_free(pmb, phba->mbox_mem_pool);
6385}
6386
6387/**
6388 * lpfc_sli4_async_sli_evt - Process the asynchronous SLI link event
6389 * @phba: pointer to lpfc hba data structure.
fe614acd 6390 * @acqe_sli: pointer to the async SLI completion queue entry.
70f3c073
JS
6391 *
6392 * This routine is to handle the SLI4 asynchronous SLI events.
6393 **/
6394static void
6395lpfc_sli4_async_sli_evt(struct lpfc_hba *phba, struct lpfc_acqe_sli *acqe_sli)
6396{
4b8bae08 6397 char port_name;
8c1312e1 6398 char message[128];
4b8bae08 6399 uint8_t status;
946727dc 6400 uint8_t evt_type;
448193b5 6401 uint8_t operational = 0;
946727dc 6402 struct temp_event temp_event_data;
4b8bae08 6403 struct lpfc_acqe_misconfigured_event *misconfigured;
9064aeb2 6404 struct lpfc_acqe_cgn_signal *cgn_signal;
946727dc 6405 struct Scsi_Host *shost;
cd71348a 6406 struct lpfc_vport **vports;
9064aeb2 6407 int rc, i, cnt;
946727dc
JS
6408
6409 evt_type = bf_get(lpfc_trailer_type, acqe_sli);
4b8bae08 6410
448193b5 6411 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
d11ed16d
JS
6412 "2901 Async SLI event - Type:%d, Event Data: x%08x "
6413 "x%08x x%08x x%08x\n", evt_type,
448193b5 6414 acqe_sli->event_data1, acqe_sli->event_data2,
d11ed16d 6415 acqe_sli->reserved, acqe_sli->trailer);
4b8bae08
JS
6416
6417 port_name = phba->Port[0];
6418 if (port_name == 0x00)
6419 port_name = '?'; /* get port name is empty */
6420
946727dc
JS
6421 switch (evt_type) {
6422 case LPFC_SLI_EVENT_TYPE_OVER_TEMP:
6423 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
6424 temp_event_data.event_code = LPFC_THRESHOLD_TEMP;
6425 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
6426
6427 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
6428 "3190 Over Temperature:%d Celsius- Port Name %c\n",
6429 acqe_sli->event_data1, port_name);
6430
310429ef 6431 phba->sfp_warning |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
946727dc
JS
6432 shost = lpfc_shost_from_vport(phba->pport);
6433 fc_host_post_vendor_event(shost, fc_get_event_number(),
6434 sizeof(temp_event_data),
6435 (char *)&temp_event_data,
6436 SCSI_NL_VID_TYPE_PCI
6437 | PCI_VENDOR_ID_EMULEX);
6438 break;
6439 case LPFC_SLI_EVENT_TYPE_NORM_TEMP:
6440 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
6441 temp_event_data.event_code = LPFC_NORMAL_TEMP;
6442 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
6443
6444 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
6445 "3191 Normal Temperature:%d Celsius - Port Name %c\n",
6446 acqe_sli->event_data1, port_name);
6447
6448 shost = lpfc_shost_from_vport(phba->pport);
6449 fc_host_post_vendor_event(shost, fc_get_event_number(),
6450 sizeof(temp_event_data),
6451 (char *)&temp_event_data,
6452 SCSI_NL_VID_TYPE_PCI
6453 | PCI_VENDOR_ID_EMULEX);
6454 break;
6455 case LPFC_SLI_EVENT_TYPE_MISCONFIGURED:
6456 misconfigured = (struct lpfc_acqe_misconfigured_event *)
4b8bae08
JS
6457 &acqe_sli->event_data1;
6458
946727dc
JS
6459 /* fetch the status for this port */
6460 switch (phba->sli4_hba.lnk_info.lnk_no) {
6461 case LPFC_LINK_NUMBER_0:
448193b5
JS
6462 status = bf_get(lpfc_sli_misconfigured_port0_state,
6463 &misconfigured->theEvent);
6464 operational = bf_get(lpfc_sli_misconfigured_port0_op,
4b8bae08 6465 &misconfigured->theEvent);
946727dc
JS
6466 break;
6467 case LPFC_LINK_NUMBER_1:
448193b5
JS
6468 status = bf_get(lpfc_sli_misconfigured_port1_state,
6469 &misconfigured->theEvent);
6470 operational = bf_get(lpfc_sli_misconfigured_port1_op,
4b8bae08 6471 &misconfigured->theEvent);
946727dc
JS
6472 break;
6473 case LPFC_LINK_NUMBER_2:
448193b5
JS
6474 status = bf_get(lpfc_sli_misconfigured_port2_state,
6475 &misconfigured->theEvent);
6476 operational = bf_get(lpfc_sli_misconfigured_port2_op,
4b8bae08 6477 &misconfigured->theEvent);
946727dc
JS
6478 break;
6479 case LPFC_LINK_NUMBER_3:
448193b5
JS
6480 status = bf_get(lpfc_sli_misconfigured_port3_state,
6481 &misconfigured->theEvent);
6482 operational = bf_get(lpfc_sli_misconfigured_port3_op,
4b8bae08 6483 &misconfigured->theEvent);
946727dc
JS
6484 break;
6485 default:
372c187b 6486 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
448193b5
JS
6487 "3296 "
6488 "LPFC_SLI_EVENT_TYPE_MISCONFIGURED "
6489 "event: Invalid link %d",
6490 phba->sli4_hba.lnk_info.lnk_no);
6491 return;
946727dc 6492 }
4b8bae08 6493
448193b5
JS
6494 /* Skip if optic state unchanged */
6495 if (phba->sli4_hba.lnk_info.optic_state == status)
6496 return;
6497
946727dc
JS
6498 switch (status) {
6499 case LPFC_SLI_EVENT_STATUS_VALID:
448193b5
JS
6500 sprintf(message, "Physical Link is functional");
6501 break;
946727dc
JS
6502 case LPFC_SLI_EVENT_STATUS_NOT_PRESENT:
6503 sprintf(message, "Optics faulted/incorrectly "
6504 "installed/not installed - Reseat optics, "
6505 "if issue not resolved, replace.");
6506 break;
6507 case LPFC_SLI_EVENT_STATUS_WRONG_TYPE:
6508 sprintf(message,
6509 "Optics of two types installed - Remove one "
6510 "optic or install matching pair of optics.");
6511 break;
6512 case LPFC_SLI_EVENT_STATUS_UNSUPPORTED:
6513 sprintf(message, "Incompatible optics - Replace with "
292098be 6514 "compatible optics for card to function.");
946727dc 6515 break;
448193b5
JS
6516 case LPFC_SLI_EVENT_STATUS_UNQUALIFIED:
6517 sprintf(message, "Unqualified optics - Replace with "
6518 "Avago optics for Warranty and Technical "
6519 "Support - Link is%s operational",
2ea259ee 6520 (operational) ? " not" : "");
448193b5
JS
6521 break;
6522 case LPFC_SLI_EVENT_STATUS_UNCERTIFIED:
6523 sprintf(message, "Uncertified optics - Replace with "
6524 "Avago-certified optics to enable link "
6525 "operation - Link is%s operational",
2ea259ee 6526 (operational) ? " not" : "");
448193b5 6527 break;
946727dc
JS
6528 default:
6529 /* firmware is reporting a status we don't know about */
6530 sprintf(message, "Unknown event status x%02x", status);
6531 break;
6532 }
cd71348a
JS
6533
6534 /* Issue READ_CONFIG mbox command to refresh supported speeds */
6535 rc = lpfc_sli4_read_config(phba);
3952e91f 6536 if (rc) {
cd71348a 6537 phba->lmt = 0;
372c187b
DK
6538 lpfc_printf_log(phba, KERN_ERR,
6539 LOG_TRACE_EVENT,
cd71348a 6540 "3194 Unable to retrieve supported "
3952e91f 6541 "speeds, rc = 0x%x\n", rc);
cd71348a 6542 }
7a1dda94
JS
6543 rc = lpfc_sli4_refresh_params(phba);
6544 if (rc) {
6545 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
6546 "3174 Unable to update pls support, "
6547 "rc x%x\n", rc);
6548 }
cd71348a
JS
6549 vports = lpfc_create_vport_work_array(phba);
6550 if (vports != NULL) {
6551 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
6552 i++) {
6553 shost = lpfc_shost_from_vport(vports[i]);
6554 lpfc_host_supported_speeds_set(shost);
6555 }
6556 }
6557 lpfc_destroy_vport_work_array(phba, vports);
6558
448193b5 6559 phba->sli4_hba.lnk_info.optic_state = status;
946727dc 6560 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
448193b5 6561 "3176 Port Name %c %s\n", port_name, message);
946727dc
JS
6562 break;
6563 case LPFC_SLI_EVENT_TYPE_REMOTE_DPORT:
6564 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
6565 "3192 Remote DPort Test Initiated - "
6566 "Event Data1:x%08x Event Data2: x%08x\n",
6567 acqe_sli->event_data1, acqe_sli->event_data2);
4b8bae08 6568 break;
02243836
JS
6569 case LPFC_SLI_EVENT_TYPE_PORT_PARAMS_CHG:
6570 /* Call FW to obtain active parms */
6571 lpfc_sli4_cgn_parm_chg_evt(phba);
6572 break;
e7d85952
JS
6573 case LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN:
6574 /* Misconfigured WWN. Reports that the SLI Port is configured
6575 * to use FA-WWN, but the attached device doesn’t support it.
6576 * No driver action is required.
6577 * Event Data1 - N.A, Event Data2 - N.A
6578 */
6579 lpfc_log_msg(phba, KERN_WARNING, LOG_SLI,
6580 "2699 Misconfigured FA-WWN - Attached device does "
6581 "not support FA-WWN\n");
6582 break;
d11ed16d
JS
6583 case LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE:
6584 /* EEPROM failure. No driver action is required */
6585 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
6586 "2518 EEPROM failure - "
6587 "Event Data1: x%08x Event Data2: x%08x\n",
6588 acqe_sli->event_data1, acqe_sli->event_data2);
6589 break;
9064aeb2
JS
6590 case LPFC_SLI_EVENT_TYPE_CGN_SIGNAL:
6591 if (phba->cmf_active_mode == LPFC_CFG_OFF)
6592 break;
6593 cgn_signal = (struct lpfc_acqe_cgn_signal *)
6594 &acqe_sli->event_data1;
6595 phba->cgn_acqe_cnt++;
6596
6597 cnt = bf_get(lpfc_warn_acqe, cgn_signal);
6598 atomic64_add(cnt, &phba->cgn_acqe_stat.warn);
6599 atomic64_add(cgn_signal->alarm_cnt, &phba->cgn_acqe_stat.alarm);
6600
6601 /* no threshold for CMF, even 1 signal will trigger an event */
6602
6603 /* Alarm overrides warning, so check that first */
6604 if (cgn_signal->alarm_cnt) {
6605 if (phba->cgn_reg_signal == EDC_CG_SIG_WARN_ALARM) {
6606 /* Keep track of alarm cnt for cgn_info */
6607 atomic_add(cgn_signal->alarm_cnt,
6608 &phba->cgn_fabric_alarm_cnt);
6609 /* Keep track of alarm cnt for CMF_SYNC_WQE */
6610 atomic_add(cgn_signal->alarm_cnt,
6611 &phba->cgn_sync_alarm_cnt);
6612 }
6613 } else if (cnt) {
6614 /* signal action needs to be taken */
6615 if (phba->cgn_reg_signal == EDC_CG_SIG_WARN_ONLY ||
6616 phba->cgn_reg_signal == EDC_CG_SIG_WARN_ALARM) {
6617 /* Keep track of warning cnt for cgn_info */
6618 atomic_add(cnt, &phba->cgn_fabric_warn_cnt);
6619 /* Keep track of warning cnt for CMF_SYNC_WQE */
6620 atomic_add(cnt, &phba->cgn_sync_warn_cnt);
6621 }
6622 }
6623 break;
4b8bae08 6624 default:
946727dc 6625 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
d11ed16d 6626 "3193 Unrecognized SLI event, type: 0x%x",
946727dc 6627 evt_type);
4b8bae08
JS
6628 break;
6629 }
70f3c073
JS
6630}
6631
fc2b989b
JS
6632/**
6633 * lpfc_sli4_perform_vport_cvl - Perform clear virtual link on a vport
6634 * @vport: pointer to vport data structure.
6635 *
6636 * This routine is to perform Clear Virtual Link (CVL) on a vport in
6637 * response to a CVL event.
6638 *
6639 * Return the pointer to the ndlp with the vport if successful, otherwise
6640 * return NULL.
6641 **/
6642static struct lpfc_nodelist *
6643lpfc_sli4_perform_vport_cvl(struct lpfc_vport *vport)
6644{
6645 struct lpfc_nodelist *ndlp;
6646 struct Scsi_Host *shost;
6647 struct lpfc_hba *phba;
6648
6649 if (!vport)
6650 return NULL;
fc2b989b
JS
6651 phba = vport->phba;
6652 if (!phba)
6653 return NULL;
78730cfe
JS
6654 ndlp = lpfc_findnode_did(vport, Fabric_DID);
6655 if (!ndlp) {
6656 /* Cannot find existing Fabric ndlp, so allocate a new one */
9d3d340d 6657 ndlp = lpfc_nlp_init(vport, Fabric_DID);
78730cfe 6658 if (!ndlp)
5860d9fb 6659 return NULL;
78730cfe
JS
6660 /* Set the node type */
6661 ndlp->nlp_type |= NLP_FABRIC;
6662 /* Put ndlp onto node list */
6663 lpfc_enqueue_node(vport, ndlp);
78730cfe 6664 }
63e801ce
JS
6665 if ((phba->pport->port_state < LPFC_FLOGI) &&
6666 (phba->pport->port_state != LPFC_VPORT_FAILED))
fc2b989b
JS
6667 return NULL;
6668 /* If virtual link is not yet instantiated ignore CVL */
63e801ce
JS
6669 if ((vport != phba->pport) && (vport->port_state < LPFC_FDISC)
6670 && (vport->port_state != LPFC_VPORT_FAILED))
fc2b989b
JS
6671 return NULL;
6672 shost = lpfc_shost_from_vport(vport);
6673 if (!shost)
6674 return NULL;
6675 lpfc_linkdown_port(vport);
6676 lpfc_cleanup_pending_mbox(vport);
6677 spin_lock_irq(shost->host_lock);
6678 vport->fc_flag |= FC_VPORT_CVL_RCVD;
6679 spin_unlock_irq(shost->host_lock);
6680
6681 return ndlp;
6682}
6683
6684/**
6685 * lpfc_sli4_perform_all_vport_cvl - Perform clear virtual link on all vports
fe614acd 6686 * @phba: pointer to lpfc hba data structure.
fc2b989b
JS
6687 *
6688 * This routine is to perform Clear Virtual Link (CVL) on all vports in
6689 * response to a FCF dead event.
6690 **/
6691static void
6692lpfc_sli4_perform_all_vport_cvl(struct lpfc_hba *phba)
6693{
6694 struct lpfc_vport **vports;
6695 int i;
6696
6697 vports = lpfc_create_vport_work_array(phba);
6698 if (vports)
6699 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
6700 lpfc_sli4_perform_vport_cvl(vports[i]);
6701 lpfc_destroy_vport_work_array(phba, vports);
6702}
6703
da0436e9 6704/**
76a95d75 6705 * lpfc_sli4_async_fip_evt - Process the asynchronous FCoE FIP event
da0436e9 6706 * @phba: pointer to lpfc hba data structure.
fe614acd 6707 * @acqe_fip: pointer to the async fcoe completion queue entry.
da0436e9
JS
6708 *
6709 * This routine is to handle the SLI4 asynchronous fcoe event.
6710 **/
6711static void
76a95d75 6712lpfc_sli4_async_fip_evt(struct lpfc_hba *phba,
70f3c073 6713 struct lpfc_acqe_fip *acqe_fip)
da0436e9 6714{
70f3c073 6715 uint8_t event_type = bf_get(lpfc_trailer_type, acqe_fip);
da0436e9 6716 int rc;
6669f9bb
JS
6717 struct lpfc_vport *vport;
6718 struct lpfc_nodelist *ndlp;
695a814e
JS
6719 int active_vlink_present;
6720 struct lpfc_vport **vports;
6721 int i;
da0436e9 6722
70f3c073
JS
6723 phba->fc_eventTag = acqe_fip->event_tag;
6724 phba->fcoe_eventtag = acqe_fip->event_tag;
da0436e9 6725 switch (event_type) {
70f3c073
JS
6726 case LPFC_FIP_EVENT_TYPE_NEW_FCF:
6727 case LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD:
6728 if (event_type == LPFC_FIP_EVENT_TYPE_NEW_FCF)
372c187b 6729 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
a93ff37a
JS
6730 "2546 New FCF event, evt_tag:x%x, "
6731 "index:x%x\n",
70f3c073
JS
6732 acqe_fip->event_tag,
6733 acqe_fip->index);
999d813f
JS
6734 else
6735 lpfc_printf_log(phba, KERN_WARNING, LOG_FIP |
6736 LOG_DISCOVERY,
a93ff37a
JS
6737 "2788 FCF param modified event, "
6738 "evt_tag:x%x, index:x%x\n",
70f3c073
JS
6739 acqe_fip->event_tag,
6740 acqe_fip->index);
38b92ef8 6741 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
0c9ab6f5
JS
6742 /*
6743 * During period of FCF discovery, read the FCF
6744 * table record indexed by the event to update
a93ff37a 6745 * FCF roundrobin failover eligible FCF bmask.
0c9ab6f5
JS
6746 */
6747 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
6748 LOG_DISCOVERY,
a93ff37a
JS
6749 "2779 Read FCF (x%x) for updating "
6750 "roundrobin FCF failover bmask\n",
70f3c073
JS
6751 acqe_fip->index);
6752 rc = lpfc_sli4_read_fcf_rec(phba, acqe_fip->index);
0c9ab6f5 6753 }
38b92ef8
JS
6754
6755 /* If the FCF discovery is in progress, do nothing. */
3804dc84 6756 spin_lock_irq(&phba->hbalock);
a93ff37a 6757 if (phba->hba_flag & FCF_TS_INPROG) {
38b92ef8
JS
6758 spin_unlock_irq(&phba->hbalock);
6759 break;
6760 }
6761 /* If fast FCF failover rescan event is pending, do nothing */
036cad1f 6762 if (phba->fcf.fcf_flag & (FCF_REDISC_EVT | FCF_REDISC_PEND)) {
38b92ef8
JS
6763 spin_unlock_irq(&phba->hbalock);
6764 break;
6765 }
6766
c2b9712e
JS
6767 /* If the FCF has been in discovered state, do nothing. */
6768 if (phba->fcf.fcf_flag & FCF_SCAN_DONE) {
3804dc84
JS
6769 spin_unlock_irq(&phba->hbalock);
6770 break;
6771 }
6772 spin_unlock_irq(&phba->hbalock);
38b92ef8 6773
0c9ab6f5
JS
6774 /* Otherwise, scan the entire FCF table and re-discover SAN */
6775 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
a93ff37a
JS
6776 "2770 Start FCF table scan per async FCF "
6777 "event, evt_tag:x%x, index:x%x\n",
70f3c073 6778 acqe_fip->event_tag, acqe_fip->index);
0c9ab6f5
JS
6779 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba,
6780 LPFC_FCOE_FCF_GET_FIRST);
da0436e9 6781 if (rc)
372c187b 6782 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0c9ab6f5 6783 "2547 Issue FCF scan read FCF mailbox "
a93ff37a 6784 "command failed (x%x)\n", rc);
da0436e9
JS
6785 break;
6786
70f3c073 6787 case LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL:
372c187b
DK
6788 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
6789 "2548 FCF Table full count 0x%x tag 0x%x\n",
6790 bf_get(lpfc_acqe_fip_fcf_count, acqe_fip),
6791 acqe_fip->event_tag);
da0436e9
JS
6792 break;
6793
70f3c073 6794 case LPFC_FIP_EVENT_TYPE_FCF_DEAD:
80c17849 6795 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
372c187b
DK
6796 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
6797 "2549 FCF (x%x) disconnected from network, "
6798 "tag:x%x\n", acqe_fip->index,
6799 acqe_fip->event_tag);
38b92ef8
JS
6800 /*
6801 * If we are in the middle of FCF failover process, clear
6802 * the corresponding FCF bit in the roundrobin bitmap.
da0436e9 6803 */
fc2b989b 6804 spin_lock_irq(&phba->hbalock);
a1cadfef
JS
6805 if ((phba->fcf.fcf_flag & FCF_DISCOVERY) &&
6806 (phba->fcf.current_rec.fcf_indx != acqe_fip->index)) {
fc2b989b 6807 spin_unlock_irq(&phba->hbalock);
0c9ab6f5 6808 /* Update FLOGI FCF failover eligible FCF bmask */
70f3c073 6809 lpfc_sli4_fcf_rr_index_clear(phba, acqe_fip->index);
fc2b989b
JS
6810 break;
6811 }
38b92ef8
JS
6812 spin_unlock_irq(&phba->hbalock);
6813
6814 /* If the event is not for currently used fcf do nothing */
70f3c073 6815 if (phba->fcf.current_rec.fcf_indx != acqe_fip->index)
38b92ef8
JS
6816 break;
6817
6818 /*
6819 * Otherwise, request the port to rediscover the entire FCF
6820 * table for a fast recovery from case that the current FCF
6821 * is no longer valid as we are not in the middle of FCF
6822 * failover process already.
6823 */
c2b9712e
JS
6824 spin_lock_irq(&phba->hbalock);
6825 /* Mark the fast failover process in progress */
6826 phba->fcf.fcf_flag |= FCF_DEAD_DISC;
6827 spin_unlock_irq(&phba->hbalock);
6828
6829 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
6830 "2771 Start FCF fast failover process due to "
6831 "FCF DEAD event: evt_tag:x%x, fcf_index:x%x "
6832 "\n", acqe_fip->event_tag, acqe_fip->index);
6833 rc = lpfc_sli4_redisc_fcf_table(phba);
6834 if (rc) {
6835 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
372c187b 6836 LOG_TRACE_EVENT,
7afc0ce9 6837 "2772 Issue FCF rediscover mailbox "
c2b9712e
JS
6838 "command failed, fail through to FCF "
6839 "dead event\n");
6840 spin_lock_irq(&phba->hbalock);
6841 phba->fcf.fcf_flag &= ~FCF_DEAD_DISC;
6842 spin_unlock_irq(&phba->hbalock);
6843 /*
6844 * Last resort will fail over by treating this
6845 * as a link down to FCF registration.
6846 */
6847 lpfc_sli4_fcf_dead_failthrough(phba);
6848 } else {
6849 /* Reset FCF roundrobin bmask for new discovery */
6850 lpfc_sli4_clear_fcf_rr_bmask(phba);
6851 /*
6852 * Handling fast FCF failover to a DEAD FCF event is
6853 * considered equalivant to receiving CVL to all vports.
6854 */
6855 lpfc_sli4_perform_all_vport_cvl(phba);
6856 }
da0436e9 6857 break;
70f3c073 6858 case LPFC_FIP_EVENT_TYPE_CVL:
80c17849 6859 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
372c187b
DK
6860 lpfc_printf_log(phba, KERN_ERR,
6861 LOG_TRACE_EVENT,
6669f9bb 6862 "2718 Clear Virtual Link Received for VPI 0x%x"
70f3c073 6863 " tag 0x%x\n", acqe_fip->index, acqe_fip->event_tag);
6d368e53 6864
6669f9bb 6865 vport = lpfc_find_vport_by_vpid(phba,
5248a749 6866 acqe_fip->index);
fc2b989b 6867 ndlp = lpfc_sli4_perform_vport_cvl(vport);
6669f9bb
JS
6868 if (!ndlp)
6869 break;
695a814e
JS
6870 active_vlink_present = 0;
6871
6872 vports = lpfc_create_vport_work_array(phba);
6873 if (vports) {
6874 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
6875 i++) {
6876 if ((!(vports[i]->fc_flag &
6877 FC_VPORT_CVL_RCVD)) &&
6878 (vports[i]->port_state > LPFC_FDISC)) {
6879 active_vlink_present = 1;
6880 break;
6881 }
6882 }
6883 lpfc_destroy_vport_work_array(phba, vports);
6884 }
6885
cc82355a
JS
6886 /*
6887 * Don't re-instantiate if vport is marked for deletion.
6888 * If we are here first then vport_delete is going to wait
6889 * for discovery to complete.
6890 */
6891 if (!(vport->load_flag & FC_UNLOADING) &&
6892 active_vlink_present) {
695a814e
JS
6893 /*
6894 * If there are other active VLinks present,
6895 * re-instantiate the Vlink using FDISC.
6896 */
256ec0d0
JS
6897 mod_timer(&ndlp->nlp_delayfunc,
6898 jiffies + msecs_to_jiffies(1000));
c6adba15 6899 spin_lock_irq(&ndlp->lock);
6669f9bb 6900 ndlp->nlp_flag |= NLP_DELAY_TMO;
c6adba15 6901 spin_unlock_irq(&ndlp->lock);
695a814e
JS
6902 ndlp->nlp_last_elscmd = ELS_CMD_FDISC;
6903 vport->port_state = LPFC_FDISC;
6904 } else {
ecfd03c6
JS
6905 /*
6906 * Otherwise, we request port to rediscover
6907 * the entire FCF table for a fast recovery
6908 * from possible case that the current FCF
0c9ab6f5
JS
6909 * is no longer valid if we are not already
6910 * in the FCF failover process.
ecfd03c6 6911 */
fc2b989b 6912 spin_lock_irq(&phba->hbalock);
0c9ab6f5 6913 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
fc2b989b
JS
6914 spin_unlock_irq(&phba->hbalock);
6915 break;
6916 }
6917 /* Mark the fast failover process in progress */
0c9ab6f5 6918 phba->fcf.fcf_flag |= FCF_ACVL_DISC;
fc2b989b 6919 spin_unlock_irq(&phba->hbalock);
0c9ab6f5
JS
6920 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
6921 LOG_DISCOVERY,
a93ff37a 6922 "2773 Start FCF failover per CVL, "
70f3c073 6923 "evt_tag:x%x\n", acqe_fip->event_tag);
ecfd03c6 6924 rc = lpfc_sli4_redisc_fcf_table(phba);
fc2b989b 6925 if (rc) {
0c9ab6f5 6926 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
372c187b 6927 LOG_TRACE_EVENT,
0c9ab6f5 6928 "2774 Issue FCF rediscover "
7afc0ce9 6929 "mailbox command failed, "
0c9ab6f5 6930 "through to CVL event\n");
fc2b989b 6931 spin_lock_irq(&phba->hbalock);
0c9ab6f5 6932 phba->fcf.fcf_flag &= ~FCF_ACVL_DISC;
fc2b989b 6933 spin_unlock_irq(&phba->hbalock);
ecfd03c6
JS
6934 /*
6935 * Last resort will be re-try on the
6936 * the current registered FCF entry.
6937 */
6938 lpfc_retry_pport_discovery(phba);
38b92ef8
JS
6939 } else
6940 /*
6941 * Reset FCF roundrobin bmask for new
6942 * discovery.
6943 */
7d791df7 6944 lpfc_sli4_clear_fcf_rr_bmask(phba);
6669f9bb
JS
6945 }
6946 break;
da0436e9 6947 default:
372c187b
DK
6948 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
6949 "0288 Unknown FCoE event type 0x%x event tag "
6950 "0x%x\n", event_type, acqe_fip->event_tag);
da0436e9
JS
6951 break;
6952 }
6953}
6954
6955/**
6956 * lpfc_sli4_async_dcbx_evt - Process the asynchronous dcbx event
6957 * @phba: pointer to lpfc hba data structure.
fe614acd 6958 * @acqe_dcbx: pointer to the async dcbx completion queue entry.
da0436e9
JS
6959 *
6960 * This routine is to handle the SLI4 asynchronous dcbx event.
6961 **/
6962static void
6963lpfc_sli4_async_dcbx_evt(struct lpfc_hba *phba,
6964 struct lpfc_acqe_dcbx *acqe_dcbx)
6965{
4d9ab994 6966 phba->fc_eventTag = acqe_dcbx->event_tag;
372c187b 6967 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
6968 "0290 The SLI4 DCBX asynchronous event is not "
6969 "handled yet\n");
6970}
6971
b19a061a
JS
6972/**
6973 * lpfc_sli4_async_grp5_evt - Process the asynchronous group5 event
6974 * @phba: pointer to lpfc hba data structure.
fe614acd 6975 * @acqe_grp5: pointer to the async grp5 completion queue entry.
b19a061a
JS
6976 *
6977 * This routine is to handle the SLI4 asynchronous grp5 event. A grp5 event
6978 * is an asynchronous notified of a logical link speed change. The Port
6979 * reports the logical link speed in units of 10Mbps.
6980 **/
6981static void
6982lpfc_sli4_async_grp5_evt(struct lpfc_hba *phba,
6983 struct lpfc_acqe_grp5 *acqe_grp5)
6984{
6985 uint16_t prev_ll_spd;
6986
6987 phba->fc_eventTag = acqe_grp5->event_tag;
6988 phba->fcoe_eventtag = acqe_grp5->event_tag;
6989 prev_ll_spd = phba->sli4_hba.link_state.logical_speed;
6990 phba->sli4_hba.link_state.logical_speed =
8b68cd52 6991 (bf_get(lpfc_acqe_grp5_llink_spd, acqe_grp5)) * 10;
b19a061a
JS
6992 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
6993 "2789 GRP5 Async Event: Updating logical link speed "
8b68cd52
JS
6994 "from %dMbps to %dMbps\n", prev_ll_spd,
6995 phba->sli4_hba.link_state.logical_speed);
b19a061a
JS
6996}
6997
02243836
JS
6998/**
6999 * lpfc_sli4_async_cmstat_evt - Process the asynchronous cmstat event
7000 * @phba: pointer to lpfc hba data structure.
7001 *
7002 * This routine is to handle the SLI4 asynchronous cmstat event. A cmstat event
7003 * is an asynchronous notification of a request to reset CM stats.
7004 **/
7005static void
7006lpfc_sli4_async_cmstat_evt(struct lpfc_hba *phba)
7007{
7008 if (!phba->cgn_i)
7009 return;
7010 lpfc_init_congestion_stat(phba);
7011}
7012
72df8a45
JS
7013/**
7014 * lpfc_cgn_params_val - Validate FW congestion parameters.
7015 * @phba: pointer to lpfc hba data structure.
7016 * @p_cfg_param: pointer to FW provided congestion parameters.
7017 *
7018 * This routine validates the congestion parameters passed
7019 * by the FW to the driver via an ACQE event.
7020 **/
7021static void
7022lpfc_cgn_params_val(struct lpfc_hba *phba, struct lpfc_cgn_param *p_cfg_param)
7023{
7024 spin_lock_irq(&phba->hbalock);
7025
7026 if (!lpfc_rangecheck(p_cfg_param->cgn_param_mode, LPFC_CFG_OFF,
7027 LPFC_CFG_MONITOR)) {
7028 lpfc_printf_log(phba, KERN_ERR, LOG_CGN_MGMT,
7029 "6225 CMF mode param out of range: %d\n",
7030 p_cfg_param->cgn_param_mode);
7031 p_cfg_param->cgn_param_mode = LPFC_CFG_OFF;
7032 }
7033
7034 spin_unlock_irq(&phba->hbalock);
7035}
7036
7037/**
7038 * lpfc_cgn_params_parse - Process a FW cong parm change event
7039 * @phba: pointer to lpfc hba data structure.
7040 * @p_cgn_param: pointer to a data buffer with the FW cong params.
7041 * @len: the size of pdata in bytes.
7042 *
7043 * This routine validates the congestion management buffer signature
7044 * from the FW, validates the contents and makes corrections for
7045 * valid, in-range values. If the signature magic is correct and
7046 * after parameter validation, the contents are copied to the driver's
7047 * @phba structure. If the magic is incorrect, an error message is
7048 * logged.
7049 **/
7050static void
7051lpfc_cgn_params_parse(struct lpfc_hba *phba,
7052 struct lpfc_cgn_param *p_cgn_param, uint32_t len)
7053{
7481811c
JS
7054 struct lpfc_cgn_info *cp;
7055 uint32_t crc, oldmode;
72df8a45
JS
7056
7057 /* Make sure the FW has encoded the correct magic number to
7058 * validate the congestion parameter in FW memory.
7059 */
7060 if (p_cgn_param->cgn_param_magic == LPFC_CFG_PARAM_MAGIC_NUM) {
7061 lpfc_printf_log(phba, KERN_INFO, LOG_CGN_MGMT | LOG_INIT,
7062 "4668 FW cgn parm buffer data: "
7063 "magic 0x%x version %d mode %d "
7064 "level0 %d level1 %d "
7065 "level2 %d byte13 %d "
7066 "byte14 %d byte15 %d "
7067 "byte11 %d byte12 %d activeMode %d\n",
7068 p_cgn_param->cgn_param_magic,
7069 p_cgn_param->cgn_param_version,
7070 p_cgn_param->cgn_param_mode,
7071 p_cgn_param->cgn_param_level0,
7072 p_cgn_param->cgn_param_level1,
7073 p_cgn_param->cgn_param_level2,
7074 p_cgn_param->byte13,
7075 p_cgn_param->byte14,
7076 p_cgn_param->byte15,
7077 p_cgn_param->byte11,
7078 p_cgn_param->byte12,
7079 phba->cmf_active_mode);
7080
7081 oldmode = phba->cmf_active_mode;
7082
7083 /* Any parameters out of range are corrected to defaults
7084 * by this routine. No need to fail.
7085 */
7086 lpfc_cgn_params_val(phba, p_cgn_param);
7087
7088 /* Parameters are verified, move them into driver storage */
7089 spin_lock_irq(&phba->hbalock);
7090 memcpy(&phba->cgn_p, p_cgn_param,
7091 sizeof(struct lpfc_cgn_param));
7092
7481811c
JS
7093 /* Update parameters in congestion info buffer now */
7094 if (phba->cgn_i) {
7095 cp = (struct lpfc_cgn_info *)phba->cgn_i->virt;
7096 cp->cgn_info_mode = phba->cgn_p.cgn_param_mode;
7097 cp->cgn_info_level0 = phba->cgn_p.cgn_param_level0;
7098 cp->cgn_info_level1 = phba->cgn_p.cgn_param_level1;
7099 cp->cgn_info_level2 = phba->cgn_p.cgn_param_level2;
7100 crc = lpfc_cgn_calc_crc32(cp, LPFC_CGN_INFO_SZ,
7101 LPFC_CGN_CRC32_SEED);
7102 cp->cgn_info_crc = cpu_to_le32(crc);
7103 }
72df8a45
JS
7104 spin_unlock_irq(&phba->hbalock);
7105
7106 phba->cmf_active_mode = phba->cgn_p.cgn_param_mode;
7107
7108 switch (oldmode) {
7109 case LPFC_CFG_OFF:
7110 if (phba->cgn_p.cgn_param_mode != LPFC_CFG_OFF) {
7111 /* Turning CMF on */
02243836 7112 lpfc_cmf_start(phba);
72df8a45
JS
7113
7114 if (phba->link_state >= LPFC_LINK_UP) {
7115 phba->cgn_reg_fpin =
7116 phba->cgn_init_reg_fpin;
7117 phba->cgn_reg_signal =
7118 phba->cgn_init_reg_signal;
7119 lpfc_issue_els_edc(phba->pport, 0);
7120 }
7121 }
7122 break;
7123 case LPFC_CFG_MANAGED:
7124 switch (phba->cgn_p.cgn_param_mode) {
7125 case LPFC_CFG_OFF:
7126 /* Turning CMF off */
02243836 7127 lpfc_cmf_stop(phba);
72df8a45
JS
7128 if (phba->link_state >= LPFC_LINK_UP)
7129 lpfc_issue_els_edc(phba->pport, 0);
7130 break;
7131 case LPFC_CFG_MONITOR:
7132 lpfc_printf_log(phba, KERN_INFO, LOG_CGN_MGMT,
7133 "4661 Switch from MANAGED to "
7134 "`MONITOR mode\n");
02243836
JS
7135 phba->cmf_max_bytes_per_interval =
7136 phba->cmf_link_byte_count;
7137
7138 /* Resume blocked IO - unblock on workqueue */
7139 queue_work(phba->wq,
7140 &phba->unblock_request_work);
72df8a45
JS
7141 break;
7142 }
7143 break;
7144 case LPFC_CFG_MONITOR:
7145 switch (phba->cgn_p.cgn_param_mode) {
7146 case LPFC_CFG_OFF:
7147 /* Turning CMF off */
02243836 7148 lpfc_cmf_stop(phba);
72df8a45
JS
7149 if (phba->link_state >= LPFC_LINK_UP)
7150 lpfc_issue_els_edc(phba->pport, 0);
7151 break;
7152 case LPFC_CFG_MANAGED:
7153 lpfc_printf_log(phba, KERN_INFO, LOG_CGN_MGMT,
7154 "4662 Switch from MONITOR to "
7155 "MANAGED mode\n");
02243836 7156 lpfc_cmf_signal_init(phba);
72df8a45
JS
7157 break;
7158 }
7159 break;
7160 }
7161 } else {
7162 lpfc_printf_log(phba, KERN_ERR, LOG_CGN_MGMT | LOG_INIT,
7163 "4669 FW cgn parm buf wrong magic 0x%x "
7164 "version %d\n", p_cgn_param->cgn_param_magic,
7165 p_cgn_param->cgn_param_version);
7166 }
7167}
7168
7169/**
7170 * lpfc_sli4_cgn_params_read - Read and Validate FW congestion parameters.
7171 * @phba: pointer to lpfc hba data structure.
7172 *
7173 * This routine issues a read_object mailbox command to
7174 * get the congestion management parameters from the FW
7175 * parses it and updates the driver maintained values.
7176 *
7177 * Returns
7178 * 0 if the object was empty
7179 * -Eval if an error was encountered
7180 * Count if bytes were read from object
7181 **/
7182int
7183lpfc_sli4_cgn_params_read(struct lpfc_hba *phba)
7184{
7185 int ret = 0;
7186 struct lpfc_cgn_param *p_cgn_param = NULL;
7187 u32 *pdata = NULL;
7188 u32 len = 0;
7189
7190 /* Find out if the FW has a new set of congestion parameters. */
7191 len = sizeof(struct lpfc_cgn_param);
7192 pdata = kzalloc(len, GFP_KERNEL);
7193 ret = lpfc_read_object(phba, (char *)LPFC_PORT_CFG_NAME,
7194 pdata, len);
7195
7196 /* 0 means no data. A negative means error. A positive means
7197 * bytes were copied.
7198 */
7199 if (!ret) {
7200 lpfc_printf_log(phba, KERN_ERR, LOG_CGN_MGMT | LOG_INIT,
7201 "4670 CGN RD OBJ returns no data\n");
7202 goto rd_obj_err;
7203 } else if (ret < 0) {
7204 /* Some error. Just exit and return it to the caller.*/
7205 goto rd_obj_err;
7206 }
7207
7208 lpfc_printf_log(phba, KERN_INFO, LOG_CGN_MGMT | LOG_INIT,
7209 "6234 READ CGN PARAMS Successful %d\n", len);
7210
7211 /* Parse data pointer over len and update the phba congestion
7212 * parameters with values passed back. The receive rate values
7213 * may have been altered in FW, but take no action here.
7214 */
7215 p_cgn_param = (struct lpfc_cgn_param *)pdata;
7216 lpfc_cgn_params_parse(phba, p_cgn_param, len);
7217
7218 rd_obj_err:
7219 kfree(pdata);
7220 return ret;
7221}
7222
02243836
JS
7223/**
7224 * lpfc_sli4_cgn_parm_chg_evt - Process a FW congestion param change event
7225 * @phba: pointer to lpfc hba data structure.
7226 *
7227 * The FW generated Async ACQE SLI event calls this routine when
7228 * the event type is an SLI Internal Port Event and the Event Code
7229 * indicates a change to the FW maintained congestion parameters.
7230 *
7231 * This routine executes a Read_Object mailbox call to obtain the
7232 * current congestion parameters maintained in FW and corrects
7233 * the driver's active congestion parameters.
7234 *
7235 * The acqe event is not passed because there is no further data
7236 * required.
7237 *
7238 * Returns nonzero error if event processing encountered an error.
7239 * Zero otherwise for success.
7240 **/
7241static int
7242lpfc_sli4_cgn_parm_chg_evt(struct lpfc_hba *phba)
7243{
7244 int ret = 0;
7245
7246 if (!phba->sli4_hba.pc_sli4_params.cmf) {
7247 lpfc_printf_log(phba, KERN_ERR, LOG_CGN_MGMT | LOG_INIT,
7248 "4664 Cgn Evt when E2E off. Drop event\n");
7249 return -EACCES;
7250 }
7251
7252 /* If the event is claiming an empty object, it's ok. A write
7253 * could have cleared it. Only error is a negative return
7254 * status.
7255 */
7256 ret = lpfc_sli4_cgn_params_read(phba);
7257 if (ret < 0) {
7258 lpfc_printf_log(phba, KERN_ERR, LOG_CGN_MGMT | LOG_INIT,
7259 "4667 Error reading Cgn Params (%d)\n",
7260 ret);
7261 } else if (!ret) {
7262 lpfc_printf_log(phba, KERN_ERR, LOG_CGN_MGMT | LOG_INIT,
7263 "4673 CGN Event empty object.\n");
7264 }
7265 return ret;
7266}
7267
da0436e9
JS
7268/**
7269 * lpfc_sli4_async_event_proc - Process all the pending asynchronous event
7270 * @phba: pointer to lpfc hba data structure.
7271 *
7272 * This routine is invoked by the worker thread to process all the pending
7273 * SLI4 asynchronous events.
7274 **/
7275void lpfc_sli4_async_event_proc(struct lpfc_hba *phba)
7276{
7277 struct lpfc_cq_event *cq_event;
e7dab164 7278 unsigned long iflags;
da0436e9
JS
7279
7280 /* First, declare the async event has been handled */
e7dab164 7281 spin_lock_irqsave(&phba->hbalock, iflags);
da0436e9 7282 phba->hba_flag &= ~ASYNC_EVENT;
e7dab164
JS
7283 spin_unlock_irqrestore(&phba->hbalock, iflags);
7284
da0436e9 7285 /* Now, handle all the async events */
e7dab164 7286 spin_lock_irqsave(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9 7287 while (!list_empty(&phba->sli4_hba.sp_asynce_work_queue)) {
da0436e9
JS
7288 list_remove_head(&phba->sli4_hba.sp_asynce_work_queue,
7289 cq_event, struct lpfc_cq_event, list);
e7dab164
JS
7290 spin_unlock_irqrestore(&phba->sli4_hba.asynce_list_lock,
7291 iflags);
7292
da0436e9
JS
7293 /* Process the asynchronous event */
7294 switch (bf_get(lpfc_trailer_code, &cq_event->cqe.mcqe_cmpl)) {
7295 case LPFC_TRAILER_CODE_LINK:
7296 lpfc_sli4_async_link_evt(phba,
7297 &cq_event->cqe.acqe_link);
7298 break;
7299 case LPFC_TRAILER_CODE_FCOE:
70f3c073 7300 lpfc_sli4_async_fip_evt(phba, &cq_event->cqe.acqe_fip);
da0436e9
JS
7301 break;
7302 case LPFC_TRAILER_CODE_DCBX:
7303 lpfc_sli4_async_dcbx_evt(phba,
7304 &cq_event->cqe.acqe_dcbx);
7305 break;
b19a061a
JS
7306 case LPFC_TRAILER_CODE_GRP5:
7307 lpfc_sli4_async_grp5_evt(phba,
7308 &cq_event->cqe.acqe_grp5);
7309 break;
70f3c073
JS
7310 case LPFC_TRAILER_CODE_FC:
7311 lpfc_sli4_async_fc_evt(phba, &cq_event->cqe.acqe_fc);
7312 break;
7313 case LPFC_TRAILER_CODE_SLI:
7314 lpfc_sli4_async_sli_evt(phba, &cq_event->cqe.acqe_sli);
7315 break;
02243836
JS
7316 case LPFC_TRAILER_CODE_CMSTAT:
7317 lpfc_sli4_async_cmstat_evt(phba);
7318 break;
da0436e9 7319 default:
372c187b
DK
7320 lpfc_printf_log(phba, KERN_ERR,
7321 LOG_TRACE_EVENT,
291c2548 7322 "1804 Invalid asynchronous event code: "
da0436e9
JS
7323 "x%x\n", bf_get(lpfc_trailer_code,
7324 &cq_event->cqe.mcqe_cmpl));
7325 break;
7326 }
e7dab164 7327
da0436e9
JS
7328 /* Free the completion event processed to the free pool */
7329 lpfc_sli4_cq_event_release(phba, cq_event);
e7dab164 7330 spin_lock_irqsave(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9 7331 }
e7dab164 7332 spin_unlock_irqrestore(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9
JS
7333}
7334
ecfd03c6
JS
7335/**
7336 * lpfc_sli4_fcf_redisc_event_proc - Process fcf table rediscovery event
7337 * @phba: pointer to lpfc hba data structure.
7338 *
7339 * This routine is invoked by the worker thread to process FCF table
7340 * rediscovery pending completion event.
7341 **/
7342void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *phba)
7343{
7344 int rc;
7345
7346 spin_lock_irq(&phba->hbalock);
7347 /* Clear FCF rediscovery timeout event */
7348 phba->fcf.fcf_flag &= ~FCF_REDISC_EVT;
7349 /* Clear driver fast failover FCF record flag */
7350 phba->fcf.failover_rec.flag = 0;
7351 /* Set state for FCF fast failover */
7352 phba->fcf.fcf_flag |= FCF_REDISC_FOV;
7353 spin_unlock_irq(&phba->hbalock);
7354
7355 /* Scan FCF table from the first entry to re-discover SAN */
0c9ab6f5 7356 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
a93ff37a 7357 "2777 Start post-quiescent FCF table scan\n");
0c9ab6f5 7358 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba, LPFC_FCOE_FCF_GET_FIRST);
ecfd03c6 7359 if (rc)
372c187b 7360 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0c9ab6f5
JS
7361 "2747 Issue FCF scan read FCF mailbox "
7362 "command failed 0x%x\n", rc);
ecfd03c6
JS
7363}
7364
da0436e9
JS
7365/**
7366 * lpfc_api_table_setup - Set up per hba pci-device group func api jump table
7367 * @phba: pointer to lpfc hba data structure.
7368 * @dev_grp: The HBA PCI-Device group number.
7369 *
7370 * This routine is invoked to set up the per HBA PCI-Device group function
7371 * API jump table entries.
7372 *
7373 * Return: 0 if success, otherwise -ENODEV
7374 **/
7375int
7376lpfc_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
7377{
7378 int rc;
7379
7380 /* Set up lpfc PCI-device group */
7381 phba->pci_dev_grp = dev_grp;
7382
7383 /* The LPFC_PCI_DEV_OC uses SLI4 */
7384 if (dev_grp == LPFC_PCI_DEV_OC)
7385 phba->sli_rev = LPFC_SLI_REV4;
7386
7387 /* Set up device INIT API function jump table */
7388 rc = lpfc_init_api_table_setup(phba, dev_grp);
7389 if (rc)
7390 return -ENODEV;
7391 /* Set up SCSI API function jump table */
7392 rc = lpfc_scsi_api_table_setup(phba, dev_grp);
7393 if (rc)
7394 return -ENODEV;
7395 /* Set up SLI API function jump table */
7396 rc = lpfc_sli_api_table_setup(phba, dev_grp);
7397 if (rc)
7398 return -ENODEV;
7399 /* Set up MBOX API function jump table */
7400 rc = lpfc_mbox_api_table_setup(phba, dev_grp);
7401 if (rc)
7402 return -ENODEV;
7403
7404 return 0;
5b75da2f
JS
7405}
7406
7407/**
3621a710 7408 * lpfc_log_intr_mode - Log the active interrupt mode
5b75da2f
JS
7409 * @phba: pointer to lpfc hba data structure.
7410 * @intr_mode: active interrupt mode adopted.
7411 *
7412 * This routine it invoked to log the currently used active interrupt mode
7413 * to the device.
3772a991
JS
7414 **/
7415static void lpfc_log_intr_mode(struct lpfc_hba *phba, uint32_t intr_mode)
5b75da2f
JS
7416{
7417 switch (intr_mode) {
7418 case 0:
7419 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7420 "0470 Enable INTx interrupt mode.\n");
7421 break;
7422 case 1:
7423 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7424 "0481 Enabled MSI interrupt mode.\n");
7425 break;
7426 case 2:
7427 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7428 "0480 Enabled MSI-X interrupt mode.\n");
7429 break;
7430 default:
372c187b 7431 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5b75da2f
JS
7432 "0482 Illegal interrupt mode.\n");
7433 break;
7434 }
7435 return;
7436}
7437
5b75da2f 7438/**
3772a991 7439 * lpfc_enable_pci_dev - Enable a generic PCI device.
5b75da2f
JS
7440 * @phba: pointer to lpfc hba data structure.
7441 *
3772a991
JS
7442 * This routine is invoked to enable the PCI device that is common to all
7443 * PCI devices.
5b75da2f
JS
7444 *
7445 * Return codes
af901ca1 7446 * 0 - successful
3772a991 7447 * other values - error
5b75da2f 7448 **/
3772a991
JS
7449static int
7450lpfc_enable_pci_dev(struct lpfc_hba *phba)
5b75da2f 7451{
3772a991 7452 struct pci_dev *pdev;
5b75da2f 7453
3772a991
JS
7454 /* Obtain PCI device reference */
7455 if (!phba->pcidev)
7456 goto out_error;
7457 else
7458 pdev = phba->pcidev;
3772a991
JS
7459 /* Enable PCI device */
7460 if (pci_enable_device_mem(pdev))
7461 goto out_error;
7462 /* Request PCI resource for the device */
e0c0483c 7463 if (pci_request_mem_regions(pdev, LPFC_DRIVER_NAME))
3772a991
JS
7464 goto out_disable_device;
7465 /* Set up device as PCI master and save state for EEH */
7466 pci_set_master(pdev);
7467 pci_try_set_mwi(pdev);
7468 pci_save_state(pdev);
5b75da2f 7469
0558056c 7470 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
453193e0 7471 if (pci_is_pcie(pdev))
0558056c
JS
7472 pdev->needs_freset = 1;
7473
3772a991 7474 return 0;
5b75da2f 7475
3772a991
JS
7476out_disable_device:
7477 pci_disable_device(pdev);
7478out_error:
a516074c 7479 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e0c0483c 7480 "1401 Failed to enable pci device\n");
3772a991 7481 return -ENODEV;
5b75da2f
JS
7482}
7483
7484/**
3772a991 7485 * lpfc_disable_pci_dev - Disable a generic PCI device.
5b75da2f
JS
7486 * @phba: pointer to lpfc hba data structure.
7487 *
3772a991
JS
7488 * This routine is invoked to disable the PCI device that is common to all
7489 * PCI devices.
5b75da2f
JS
7490 **/
7491static void
3772a991 7492lpfc_disable_pci_dev(struct lpfc_hba *phba)
5b75da2f 7493{
3772a991 7494 struct pci_dev *pdev;
5b75da2f 7495
3772a991
JS
7496 /* Obtain PCI device reference */
7497 if (!phba->pcidev)
7498 return;
7499 else
7500 pdev = phba->pcidev;
3772a991 7501 /* Release PCI resource and disable PCI device */
e0c0483c 7502 pci_release_mem_regions(pdev);
3772a991 7503 pci_disable_device(pdev);
5b75da2f
JS
7504
7505 return;
7506}
7507
e59058c4 7508/**
3772a991
JS
7509 * lpfc_reset_hba - Reset a hba
7510 * @phba: pointer to lpfc hba data structure.
e59058c4 7511 *
3772a991
JS
7512 * This routine is invoked to reset a hba device. It brings the HBA
7513 * offline, performs a board restart, and then brings the board back
7514 * online. The lpfc_offline calls lpfc_sli_hba_down which will clean up
7515 * on outstanding mailbox commands.
e59058c4 7516 **/
3772a991
JS
7517void
7518lpfc_reset_hba(struct lpfc_hba *phba)
dea3101e 7519{
3772a991
JS
7520 /* If resets are disabled then set error state and return. */
7521 if (!phba->cfg_enable_hba_reset) {
7522 phba->link_state = LPFC_HBA_ERROR;
7523 return;
7524 }
9ec58ec7
JS
7525
7526 /* If not LPFC_SLI_ACTIVE, force all IO to be flushed */
7527 if (phba->sli.sli_flag & LPFC_SLI_ACTIVE) {
ee62021a 7528 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
9ec58ec7 7529 } else {
ee62021a 7530 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
9ec58ec7
JS
7531 lpfc_sli_flush_io_rings(phba);
7532 }
3772a991
JS
7533 lpfc_offline(phba);
7534 lpfc_sli_brdrestart(phba);
7535 lpfc_online(phba);
7536 lpfc_unblock_mgmt_io(phba);
7537}
dea3101e 7538
0a96e975
JS
7539/**
7540 * lpfc_sli_sriov_nr_virtfn_get - Get the number of sr-iov virtual functions
7541 * @phba: pointer to lpfc hba data structure.
7542 *
7543 * This function enables the PCI SR-IOV virtual functions to a physical
7544 * function. It invokes the PCI SR-IOV api with the @nr_vfn provided to
7545 * enable the number of virtual functions to the physical function. As
7546 * not all devices support SR-IOV, the return code from the pci_enable_sriov()
7547 * API call does not considered as an error condition for most of the device.
7548 **/
7549uint16_t
7550lpfc_sli_sriov_nr_virtfn_get(struct lpfc_hba *phba)
7551{
7552 struct pci_dev *pdev = phba->pcidev;
7553 uint16_t nr_virtfn;
7554 int pos;
7555
0a96e975
JS
7556 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
7557 if (pos == 0)
7558 return 0;
7559
7560 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, &nr_virtfn);
7561 return nr_virtfn;
7562}
7563
912e3acd
JS
7564/**
7565 * lpfc_sli_probe_sriov_nr_virtfn - Enable a number of sr-iov virtual functions
7566 * @phba: pointer to lpfc hba data structure.
7567 * @nr_vfn: number of virtual functions to be enabled.
7568 *
7569 * This function enables the PCI SR-IOV virtual functions to a physical
7570 * function. It invokes the PCI SR-IOV api with the @nr_vfn provided to
7571 * enable the number of virtual functions to the physical function. As
7572 * not all devices support SR-IOV, the return code from the pci_enable_sriov()
7573 * API call does not considered as an error condition for most of the device.
7574 **/
7575int
7576lpfc_sli_probe_sriov_nr_virtfn(struct lpfc_hba *phba, int nr_vfn)
7577{
7578 struct pci_dev *pdev = phba->pcidev;
0a96e975 7579 uint16_t max_nr_vfn;
912e3acd
JS
7580 int rc;
7581
0a96e975
JS
7582 max_nr_vfn = lpfc_sli_sriov_nr_virtfn_get(phba);
7583 if (nr_vfn > max_nr_vfn) {
372c187b 7584 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a96e975
JS
7585 "3057 Requested vfs (%d) greater than "
7586 "supported vfs (%d)", nr_vfn, max_nr_vfn);
7587 return -EINVAL;
7588 }
7589
912e3acd
JS
7590 rc = pci_enable_sriov(pdev, nr_vfn);
7591 if (rc) {
7592 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
7593 "2806 Failed to enable sriov on this device "
7594 "with vfn number nr_vf:%d, rc:%d\n",
7595 nr_vfn, rc);
7596 } else
7597 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
7598 "2807 Successful enable sriov on this device "
7599 "with vfn number nr_vf:%d\n", nr_vfn);
7600 return rc;
7601}
7602
02243836
JS
7603static void
7604lpfc_unblock_requests_work(struct work_struct *work)
7605{
7606 struct lpfc_hba *phba = container_of(work, struct lpfc_hba,
7607 unblock_request_work);
7608
7609 lpfc_unblock_requests(phba);
7610}
7611
3772a991 7612/**
895427bd 7613 * lpfc_setup_driver_resource_phase1 - Phase1 etup driver internal resources.
3772a991
JS
7614 * @phba: pointer to lpfc hba data structure.
7615 *
895427bd
JS
7616 * This routine is invoked to set up the driver internal resources before the
7617 * device specific resource setup to support the HBA device it attached to.
3772a991
JS
7618 *
7619 * Return codes
895427bd
JS
7620 * 0 - successful
7621 * other values - error
3772a991
JS
7622 **/
7623static int
895427bd 7624lpfc_setup_driver_resource_phase1(struct lpfc_hba *phba)
3772a991 7625{
895427bd 7626 struct lpfc_sli *psli = &phba->sli;
dea3101e 7627
2e0fef85 7628 /*
895427bd 7629 * Driver resources common to all SLI revisions
2e0fef85 7630 */
895427bd 7631 atomic_set(&phba->fast_event_count, 0);
372c187b
DK
7632 atomic_set(&phba->dbg_log_idx, 0);
7633 atomic_set(&phba->dbg_log_cnt, 0);
7634 atomic_set(&phba->dbg_log_dmping, 0);
895427bd 7635 spin_lock_init(&phba->hbalock);
dea3101e 7636
523128e5
JS
7637 /* Initialize port_list spinlock */
7638 spin_lock_init(&phba->port_list_lock);
895427bd 7639 INIT_LIST_HEAD(&phba->port_list);
523128e5 7640
895427bd
JS
7641 INIT_LIST_HEAD(&phba->work_list);
7642 init_waitqueue_head(&phba->wait_4_mlo_m_q);
7643
7644 /* Initialize the wait queue head for the kernel thread */
7645 init_waitqueue_head(&phba->work_waitq);
7646
7647 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
f358dd0c 7648 "1403 Protocols supported %s %s %s\n",
895427bd
JS
7649 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) ?
7650 "SCSI" : " "),
7651 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) ?
f358dd0c
JS
7652 "NVME" : " "),
7653 (phba->nvmet_support ? "NVMET" : " "));
895427bd 7654
0794d601
JS
7655 /* Initialize the IO buffer list used by driver for SLI3 SCSI */
7656 spin_lock_init(&phba->scsi_buf_list_get_lock);
7657 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_get);
7658 spin_lock_init(&phba->scsi_buf_list_put_lock);
7659 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_put);
895427bd
JS
7660
7661 /* Initialize the fabric iocb list */
7662 INIT_LIST_HEAD(&phba->fabric_iocb_list);
7663
7664 /* Initialize list to save ELS buffers */
7665 INIT_LIST_HEAD(&phba->elsbuf);
7666
7667 /* Initialize FCF connection rec list */
7668 INIT_LIST_HEAD(&phba->fcf_conn_rec_list);
7669
7670 /* Initialize OAS configuration list */
7671 spin_lock_init(&phba->devicelock);
7672 INIT_LIST_HEAD(&phba->luns);
858c9f6c 7673
3772a991 7674 /* MBOX heartbeat timer */
f22eb4d3 7675 timer_setup(&psli->mbox_tmo, lpfc_mbox_timeout, 0);
3772a991 7676 /* Fabric block timer */
f22eb4d3 7677 timer_setup(&phba->fabric_block_timer, lpfc_fabric_block_timeout, 0);
3772a991 7678 /* EA polling mode timer */
f22eb4d3 7679 timer_setup(&phba->eratt_poll, lpfc_poll_eratt, 0);
895427bd 7680 /* Heartbeat timer */
f22eb4d3 7681 timer_setup(&phba->hb_tmofunc, lpfc_hb_timeout, 0);
895427bd 7682
32517fc0
JS
7683 INIT_DELAYED_WORK(&phba->eq_delay_work, lpfc_hb_eq_delay_work);
7684
317aeb83
DK
7685 INIT_DELAYED_WORK(&phba->idle_stat_delay_work,
7686 lpfc_idle_stat_delay_work);
02243836 7687 INIT_WORK(&phba->unblock_request_work, lpfc_unblock_requests_work);
895427bd
JS
7688 return 0;
7689}
7690
7691/**
7692 * lpfc_sli_driver_resource_setup - Setup driver internal resources for SLI3 dev
7693 * @phba: pointer to lpfc hba data structure.
7694 *
7695 * This routine is invoked to set up the driver internal resources specific to
7696 * support the SLI-3 HBA device it attached to.
7697 *
7698 * Return codes
7699 * 0 - successful
7700 * other values - error
7701 **/
7702static int
7703lpfc_sli_driver_resource_setup(struct lpfc_hba *phba)
7704{
0794d601 7705 int rc, entry_sz;
895427bd
JS
7706
7707 /*
7708 * Initialize timers used by driver
7709 */
7710
7711 /* FCP polling mode timer */
f22eb4d3 7712 timer_setup(&phba->fcp_poll_timer, lpfc_poll_timeout, 0);
dea3101e 7713
3772a991
JS
7714 /* Host attention work mask setup */
7715 phba->work_ha_mask = (HA_ERATT | HA_MBATT | HA_LATT);
7716 phba->work_ha_mask |= (HA_RXMASK << (LPFC_ELS_RING * 4));
dea3101e 7717
3772a991
JS
7718 /* Get all the module params for configuring this host */
7719 lpfc_get_cfgparam(phba);
895427bd
JS
7720 /* Set up phase-1 common device driver resources */
7721
7722 rc = lpfc_setup_driver_resource_phase1(phba);
7723 if (rc)
7724 return -ENODEV;
7725
49198b37
JS
7726 if (phba->pcidev->device == PCI_DEVICE_ID_HORNET) {
7727 phba->menlo_flag |= HBA_MENLO_SUPPORT;
7728 /* check for menlo minimum sg count */
7729 if (phba->cfg_sg_seg_cnt < LPFC_DEFAULT_MENLO_SG_SEG_CNT)
7730 phba->cfg_sg_seg_cnt = LPFC_DEFAULT_MENLO_SG_SEG_CNT;
7731 }
7732
895427bd 7733 if (!phba->sli.sli3_ring)
6396bb22
KC
7734 phba->sli.sli3_ring = kcalloc(LPFC_SLI3_MAX_RING,
7735 sizeof(struct lpfc_sli_ring),
7736 GFP_KERNEL);
895427bd 7737 if (!phba->sli.sli3_ring)
2a76a283
JS
7738 return -ENOMEM;
7739
dea3101e 7740 /*
96f7077f 7741 * Since lpfc_sg_seg_cnt is module parameter, the sg_dma_buf_size
3772a991 7742 * used to create the sg_dma_buf_pool must be dynamically calculated.
dea3101e 7743 */
3772a991 7744
0794d601
JS
7745 if (phba->sli_rev == LPFC_SLI_REV4)
7746 entry_sz = sizeof(struct sli4_sge);
7747 else
7748 entry_sz = sizeof(struct ulp_bde64);
7749
96f7077f 7750 /* There are going to be 2 reserved BDEs: 1 FCP cmnd + 1 FCP rsp */
3772a991 7751 if (phba->cfg_enable_bg) {
96f7077f
JS
7752 /*
7753 * The scsi_buf for a T10-DIF I/O will hold the FCP cmnd,
7754 * the FCP rsp, and a BDE for each. Sice we have no control
7755 * over how many protection data segments the SCSI Layer
7756 * will hand us (ie: there could be one for every block
7757 * in the IO), we just allocate enough BDEs to accomidate
7758 * our max amount and we need to limit lpfc_sg_seg_cnt to
7759 * minimize the risk of running out.
7760 */
7761 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
7762 sizeof(struct fcp_rsp) +
0794d601 7763 (LPFC_MAX_SG_SEG_CNT * entry_sz);
96f7077f
JS
7764
7765 if (phba->cfg_sg_seg_cnt > LPFC_MAX_SG_SEG_CNT_DIF)
7766 phba->cfg_sg_seg_cnt = LPFC_MAX_SG_SEG_CNT_DIF;
7767
7768 /* Total BDEs in BPL for scsi_sg_list and scsi_sg_prot_list */
7769 phba->cfg_total_seg_cnt = LPFC_MAX_SG_SEG_CNT;
7770 } else {
7771 /*
7772 * The scsi_buf for a regular I/O will hold the FCP cmnd,
7773 * the FCP rsp, a BDE for each, and a BDE for up to
7774 * cfg_sg_seg_cnt data segments.
7775 */
7776 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
7777 sizeof(struct fcp_rsp) +
0794d601 7778 ((phba->cfg_sg_seg_cnt + 2) * entry_sz);
96f7077f
JS
7779
7780 /* Total BDEs in BPL for scsi_sg_list */
7781 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + 2;
901a920f 7782 }
dea3101e 7783
96f7077f 7784 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
c90b4480 7785 "9088 INIT sg_tablesize:%d dmabuf_size:%d total_bde:%d\n",
96f7077f
JS
7786 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
7787 phba->cfg_total_seg_cnt);
dea3101e 7788
3772a991
JS
7789 phba->max_vpi = LPFC_MAX_VPI;
7790 /* This will be set to correct value after config_port mbox */
7791 phba->max_vports = 0;
dea3101e 7792
3772a991
JS
7793 /*
7794 * Initialize the SLI Layer to run with lpfc HBAs.
7795 */
7796 lpfc_sli_setup(phba);
895427bd 7797 lpfc_sli_queue_init(phba);
ed957684 7798
3772a991
JS
7799 /* Allocate device driver memory */
7800 if (lpfc_mem_alloc(phba, BPL_ALIGN_SZ))
7801 return -ENOMEM;
51ef4c26 7802
d79c9e9d
JS
7803 phba->lpfc_sg_dma_buf_pool =
7804 dma_pool_create("lpfc_sg_dma_buf_pool",
7805 &phba->pcidev->dev, phba->cfg_sg_dma_buf_size,
7806 BPL_ALIGN_SZ, 0);
7807
7808 if (!phba->lpfc_sg_dma_buf_pool)
7809 goto fail_free_mem;
7810
7811 phba->lpfc_cmd_rsp_buf_pool =
7812 dma_pool_create("lpfc_cmd_rsp_buf_pool",
7813 &phba->pcidev->dev,
7814 sizeof(struct fcp_cmnd) +
7815 sizeof(struct fcp_rsp),
7816 BPL_ALIGN_SZ, 0);
7817
7818 if (!phba->lpfc_cmd_rsp_buf_pool)
7819 goto fail_free_dma_buf_pool;
7820
912e3acd
JS
7821 /*
7822 * Enable sr-iov virtual functions if supported and configured
7823 * through the module parameter.
7824 */
7825 if (phba->cfg_sriov_nr_virtfn > 0) {
7826 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
7827 phba->cfg_sriov_nr_virtfn);
7828 if (rc) {
7829 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
7830 "2808 Requested number of SR-IOV "
7831 "virtual functions (%d) is not "
7832 "supported\n",
7833 phba->cfg_sriov_nr_virtfn);
7834 phba->cfg_sriov_nr_virtfn = 0;
7835 }
7836 }
7837
3772a991 7838 return 0;
d79c9e9d
JS
7839
7840fail_free_dma_buf_pool:
7841 dma_pool_destroy(phba->lpfc_sg_dma_buf_pool);
7842 phba->lpfc_sg_dma_buf_pool = NULL;
7843fail_free_mem:
7844 lpfc_mem_free(phba);
7845 return -ENOMEM;
3772a991 7846}
ed957684 7847
3772a991
JS
7848/**
7849 * lpfc_sli_driver_resource_unset - Unset drvr internal resources for SLI3 dev
7850 * @phba: pointer to lpfc hba data structure.
7851 *
7852 * This routine is invoked to unset the driver internal resources set up
7853 * specific for supporting the SLI-3 HBA device it attached to.
7854 **/
7855static void
7856lpfc_sli_driver_resource_unset(struct lpfc_hba *phba)
7857{
7858 /* Free device driver memory allocated */
7859 lpfc_mem_free_all(phba);
3163f725 7860
3772a991
JS
7861 return;
7862}
dea3101e 7863
3772a991 7864/**
da0436e9 7865 * lpfc_sli4_driver_resource_setup - Setup drvr internal resources for SLI4 dev
3772a991
JS
7866 * @phba: pointer to lpfc hba data structure.
7867 *
da0436e9
JS
7868 * This routine is invoked to set up the driver internal resources specific to
7869 * support the SLI-4 HBA device it attached to.
3772a991
JS
7870 *
7871 * Return codes
af901ca1 7872 * 0 - successful
da0436e9 7873 * other values - error
3772a991
JS
7874 **/
7875static int
da0436e9 7876lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba)
3772a991 7877{
28baac74 7878 LPFC_MBOXQ_t *mboxq;
f358dd0c 7879 MAILBOX_t *mb;
895427bd 7880 int rc, i, max_buf_size;
09294d46 7881 int longs;
81e6a637 7882 int extra;
f358dd0c 7883 uint64_t wwn;
b92dc72d
JS
7884 u32 if_type;
7885 u32 if_fam;
da0436e9 7886
895427bd 7887 phba->sli4_hba.num_present_cpu = lpfc_present_cpu;
eede4970 7888 phba->sli4_hba.num_possible_cpu = cpumask_last(cpu_possible_mask) + 1;
895427bd
JS
7889 phba->sli4_hba.curr_disp_cpu = 0;
7890
716d3bc5
JS
7891 /* Get all the module params for configuring this host */
7892 lpfc_get_cfgparam(phba);
7893
895427bd
JS
7894 /* Set up phase-1 common device driver resources */
7895 rc = lpfc_setup_driver_resource_phase1(phba);
7896 if (rc)
7897 return -ENODEV;
7898
da0436e9
JS
7899 /* Before proceed, wait for POST done and device ready */
7900 rc = lpfc_sli4_post_status_check(phba);
7901 if (rc)
7902 return -ENODEV;
7903
3cee98db
JS
7904 /* Allocate all driver workqueues here */
7905
7906 /* The lpfc_wq workqueue for deferred irq use */
7907 phba->wq = alloc_workqueue("lpfc_wq", WQ_MEM_RECLAIM, 0);
7908
3772a991 7909 /*
da0436e9 7910 * Initialize timers used by driver
3772a991 7911 */
3772a991 7912
f22eb4d3 7913 timer_setup(&phba->rrq_tmr, lpfc_rrq_timeout, 0);
3772a991 7914
ecfd03c6 7915 /* FCF rediscover timer */
f22eb4d3 7916 timer_setup(&phba->fcf.redisc_wait, lpfc_sli4_fcf_redisc_wait_tmo, 0);
ecfd03c6 7917
02243836
JS
7918 /* CMF congestion timer */
7919 hrtimer_init(&phba->cmf_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
7920 phba->cmf_timer.function = lpfc_cmf_timer;
7921
7ad20aa9
JS
7922 /*
7923 * Control structure for handling external multi-buffer mailbox
7924 * command pass-through.
7925 */
7926 memset((uint8_t *)&phba->mbox_ext_buf_ctx, 0,
7927 sizeof(struct lpfc_mbox_ext_buf_ctx));
7928 INIT_LIST_HEAD(&phba->mbox_ext_buf_ctx.ext_dmabuf_list);
7929
da0436e9 7930 phba->max_vpi = LPFC_MAX_VPI;
67d12733 7931
da0436e9
JS
7932 /* This will be set to correct value after the read_config mbox */
7933 phba->max_vports = 0;
3772a991 7934
da0436e9
JS
7935 /* Program the default value of vlan_id and fc_map */
7936 phba->valid_vlan = 0;
7937 phba->fc_map[0] = LPFC_FCOE_FCF_MAP0;
7938 phba->fc_map[1] = LPFC_FCOE_FCF_MAP1;
7939 phba->fc_map[2] = LPFC_FCOE_FCF_MAP2;
3772a991 7940
2a76a283
JS
7941 /*
7942 * For SLI4, instead of using ring 0 (LPFC_FCP_RING) for FCP commands
895427bd
JS
7943 * we will associate a new ring, for each EQ/CQ/WQ tuple.
7944 * The WQ create will allocate the ring.
2a76a283 7945 */
09294d46 7946
da0436e9 7947 /* Initialize buffer queue management fields */
895427bd 7948 INIT_LIST_HEAD(&phba->hbqs[LPFC_ELS_HBQ].hbq_buffer_list);
da0436e9
JS
7949 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_sli4_rb_alloc;
7950 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_sli4_rb_free;
3772a991 7951
20397179
GS
7952 /* for VMID idle timeout if VMID is enabled */
7953 if (lpfc_is_vmid_enabled(phba))
7954 timer_setup(&phba->inactive_vmid_poll, lpfc_vmid_poll, 0);
7955
da0436e9
JS
7956 /*
7957 * Initialize the SLI Layer to run with lpfc SLI4 HBAs.
7958 */
c00f62e6
JS
7959 /* Initialize the Abort buffer list used by driver */
7960 spin_lock_init(&phba->sli4_hba.abts_io_buf_list_lock);
7961 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_io_buf_list);
895427bd
JS
7962
7963 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
7964 /* Initialize the Abort nvme buffer list used by driver */
5e5b511d 7965 spin_lock_init(&phba->sli4_hba.abts_nvmet_buf_list_lock);
86c67379 7966 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
a8cf5dfe 7967 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_io_wait_list);
79d8c4ce
JS
7968 spin_lock_init(&phba->sli4_hba.t_active_list_lock);
7969 INIT_LIST_HEAD(&phba->sli4_hba.t_active_ctx_list);
895427bd
JS
7970 }
7971
da0436e9 7972 /* This abort list used by worker thread */
895427bd 7973 spin_lock_init(&phba->sli4_hba.sgl_list_lock);
a8cf5dfe 7974 spin_lock_init(&phba->sli4_hba.nvmet_io_wait_lock);
e7dab164
JS
7975 spin_lock_init(&phba->sli4_hba.asynce_list_lock);
7976 spin_lock_init(&phba->sli4_hba.els_xri_abrt_list_lock);
3772a991 7977
da0436e9 7978 /*
6d368e53 7979 * Initialize driver internal slow-path work queues
da0436e9 7980 */
3772a991 7981
da0436e9
JS
7982 /* Driver internel slow-path CQ Event pool */
7983 INIT_LIST_HEAD(&phba->sli4_hba.sp_cqe_event_pool);
7984 /* Response IOCB work queue list */
45ed1190 7985 INIT_LIST_HEAD(&phba->sli4_hba.sp_queue_event);
da0436e9
JS
7986 /* Asynchronous event CQ Event work queue list */
7987 INIT_LIST_HEAD(&phba->sli4_hba.sp_asynce_work_queue);
da0436e9
JS
7988 /* Slow-path XRI aborted CQ Event work queue list */
7989 INIT_LIST_HEAD(&phba->sli4_hba.sp_els_xri_aborted_work_queue);
7990 /* Receive queue CQ Event work queue list */
7991 INIT_LIST_HEAD(&phba->sli4_hba.sp_unsol_work_queue);
7992
6d368e53
JS
7993 /* Initialize extent block lists. */
7994 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_blk_list);
7995 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_xri_blk_list);
7996 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_vfi_blk_list);
7997 INIT_LIST_HEAD(&phba->lpfc_vpi_blk_list);
7998
d1f525aa
JS
7999 /* Initialize mboxq lists. If the early init routines fail
8000 * these lists need to be correctly initialized.
8001 */
8002 INIT_LIST_HEAD(&phba->sli.mboxq);
8003 INIT_LIST_HEAD(&phba->sli.mboxq_cmpl);
8004
448193b5
JS
8005 /* initialize optic_state to 0xFF */
8006 phba->sli4_hba.lnk_info.optic_state = 0xff;
8007
da0436e9
JS
8008 /* Allocate device driver memory */
8009 rc = lpfc_mem_alloc(phba, SGL_ALIGN_SZ);
8010 if (rc)
8011 return -ENOMEM;
8012
2fcee4bf 8013 /* IF Type 2 ports get initialized now. */
27d6ac0a 8014 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) >=
2fcee4bf
JS
8015 LPFC_SLI_INTF_IF_TYPE_2) {
8016 rc = lpfc_pci_function_reset(phba);
895427bd
JS
8017 if (unlikely(rc)) {
8018 rc = -ENODEV;
8019 goto out_free_mem;
8020 }
946727dc 8021 phba->temp_sensor_support = 1;
2fcee4bf
JS
8022 }
8023
da0436e9
JS
8024 /* Create the bootstrap mailbox command */
8025 rc = lpfc_create_bootstrap_mbox(phba);
8026 if (unlikely(rc))
8027 goto out_free_mem;
8028
8029 /* Set up the host's endian order with the device. */
8030 rc = lpfc_setup_endian_order(phba);
8031 if (unlikely(rc))
8032 goto out_free_bsmbx;
8033
8034 /* Set up the hba's configuration parameters. */
8035 rc = lpfc_sli4_read_config(phba);
cff261f6
JS
8036 if (unlikely(rc))
8037 goto out_free_bsmbx;
8038 rc = lpfc_mem_alloc_active_rrq_pool_s4(phba);
da0436e9
JS
8039 if (unlikely(rc))
8040 goto out_free_bsmbx;
8041
2fcee4bf
JS
8042 /* IF Type 0 ports get initialized now. */
8043 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
8044 LPFC_SLI_INTF_IF_TYPE_0) {
8045 rc = lpfc_pci_function_reset(phba);
8046 if (unlikely(rc))
8047 goto out_free_bsmbx;
8048 }
da0436e9 8049
cb5172ea
JS
8050 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
8051 GFP_KERNEL);
8052 if (!mboxq) {
8053 rc = -ENOMEM;
8054 goto out_free_bsmbx;
8055 }
8056
f358dd0c 8057 /* Check for NVMET being configured */
895427bd 8058 phba->nvmet_support = 0;
f358dd0c
JS
8059 if (lpfc_enable_nvmet_cnt) {
8060
8061 /* First get WWN of HBA instance */
8062 lpfc_read_nv(phba, mboxq);
8063 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
8064 if (rc != MBX_SUCCESS) {
372c187b
DK
8065 lpfc_printf_log(phba, KERN_ERR,
8066 LOG_TRACE_EVENT,
f358dd0c
JS
8067 "6016 Mailbox failed , mbxCmd x%x "
8068 "READ_NV, mbxStatus x%x\n",
8069 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
8070 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
d1f525aa 8071 mempool_free(mboxq, phba->mbox_mem_pool);
f358dd0c
JS
8072 rc = -EIO;
8073 goto out_free_bsmbx;
8074 }
8075 mb = &mboxq->u.mb;
8076 memcpy(&wwn, (char *)mb->un.varRDnvp.nodename,
8077 sizeof(uint64_t));
8078 wwn = cpu_to_be64(wwn);
8079 phba->sli4_hba.wwnn.u.name = wwn;
8080 memcpy(&wwn, (char *)mb->un.varRDnvp.portname,
8081 sizeof(uint64_t));
8082 /* wwn is WWPN of HBA instance */
8083 wwn = cpu_to_be64(wwn);
8084 phba->sli4_hba.wwpn.u.name = wwn;
8085
8086 /* Check to see if it matches any module parameter */
8087 for (i = 0; i < lpfc_enable_nvmet_cnt; i++) {
8088 if (wwn == lpfc_enable_nvmet[i]) {
7d708033 8089#if (IS_ENABLED(CONFIG_NVME_TARGET_FC))
3c603be9
JS
8090 if (lpfc_nvmet_mem_alloc(phba))
8091 break;
8092
8093 phba->nvmet_support = 1; /* a match */
8094
372c187b
DK
8095 lpfc_printf_log(phba, KERN_ERR,
8096 LOG_TRACE_EVENT,
f358dd0c
JS
8097 "6017 NVME Target %016llx\n",
8098 wwn);
7d708033 8099#else
372c187b
DK
8100 lpfc_printf_log(phba, KERN_ERR,
8101 LOG_TRACE_EVENT,
7d708033
JS
8102 "6021 Can't enable NVME Target."
8103 " NVME_TARGET_FC infrastructure"
8104 " is not in kernel\n");
8105#endif
c490850a
JS
8106 /* Not supported for NVMET */
8107 phba->cfg_xri_rebalancing = 0;
3048e3e8
DK
8108 if (phba->irq_chann_mode == NHT_MODE) {
8109 phba->cfg_irq_chann =
8110 phba->sli4_hba.num_present_cpu;
8111 phba->cfg_hdw_queue =
8112 phba->sli4_hba.num_present_cpu;
8113 phba->irq_chann_mode = NORMAL_MODE;
8114 }
3c603be9 8115 break;
f358dd0c
JS
8116 }
8117 }
8118 }
895427bd
JS
8119
8120 lpfc_nvme_mod_param_dep(phba);
8121
fedd3b7b
JS
8122 /*
8123 * Get sli4 parameters that override parameters from Port capabilities.
6d368e53
JS
8124 * If this call fails, it isn't critical unless the SLI4 parameters come
8125 * back in conflict.
fedd3b7b 8126 */
6d368e53
JS
8127 rc = lpfc_get_sli4_parameters(phba, mboxq);
8128 if (rc) {
b92dc72d
JS
8129 if_type = bf_get(lpfc_sli_intf_if_type,
8130 &phba->sli4_hba.sli_intf);
8131 if_fam = bf_get(lpfc_sli_intf_sli_family,
8132 &phba->sli4_hba.sli_intf);
6d368e53
JS
8133 if (phba->sli4_hba.extents_in_use &&
8134 phba->sli4_hba.rpi_hdrs_in_use) {
372c187b
DK
8135 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
8136 "2999 Unsupported SLI4 Parameters "
8137 "Extents and RPI headers enabled.\n");
b92dc72d
JS
8138 if (if_type == LPFC_SLI_INTF_IF_TYPE_0 &&
8139 if_fam == LPFC_SLI_INTF_FAMILY_BE2) {
8140 mempool_free(mboxq, phba->mbox_mem_pool);
8141 rc = -EIO;
8142 goto out_free_bsmbx;
8143 }
8144 }
8145 if (!(if_type == LPFC_SLI_INTF_IF_TYPE_0 &&
8146 if_fam == LPFC_SLI_INTF_FAMILY_BE2)) {
8147 mempool_free(mboxq, phba->mbox_mem_pool);
8148 rc = -EIO;
8149 goto out_free_bsmbx;
6d368e53
JS
8150 }
8151 }
895427bd 8152
d79c9e9d
JS
8153 /*
8154 * 1 for cmd, 1 for rsp, NVME adds an extra one
8155 * for boundary conditions in its max_sgl_segment template.
8156 */
8157 extra = 2;
8158 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
8159 extra++;
8160
8161 /*
8162 * It doesn't matter what family our adapter is in, we are
8163 * limited to 2 Pages, 512 SGEs, for our SGL.
8164 * There are going to be 2 reserved SGEs: 1 FCP cmnd + 1 FCP rsp
8165 */
8166 max_buf_size = (2 * SLI4_PAGE_SIZE);
8167
8168 /*
8169 * Since lpfc_sg_seg_cnt is module param, the sg_dma_buf_size
8170 * used to create the sg_dma_buf_pool must be calculated.
8171 */
8172 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED) {
8173 /* Both cfg_enable_bg and cfg_external_dif code paths */
8174
8175 /*
8176 * The scsi_buf for a T10-DIF I/O holds the FCP cmnd,
8177 * the FCP rsp, and a SGE. Sice we have no control
8178 * over how many protection segments the SCSI Layer
8179 * will hand us (ie: there could be one for every block
8180 * in the IO), just allocate enough SGEs to accomidate
8181 * our max amount and we need to limit lpfc_sg_seg_cnt
8182 * to minimize the risk of running out.
8183 */
8184 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
8185 sizeof(struct fcp_rsp) + max_buf_size;
8186
8187 /* Total SGEs for scsi_sg_list and scsi_sg_prot_list */
8188 phba->cfg_total_seg_cnt = LPFC_MAX_SGL_SEG_CNT;
8189
8190 /*
8191 * If supporting DIF, reduce the seg count for scsi to
8192 * allow room for the DIF sges.
8193 */
8194 if (phba->cfg_enable_bg &&
8195 phba->cfg_sg_seg_cnt > LPFC_MAX_BG_SLI4_SEG_CNT_DIF)
8196 phba->cfg_scsi_seg_cnt = LPFC_MAX_BG_SLI4_SEG_CNT_DIF;
8197 else
8198 phba->cfg_scsi_seg_cnt = phba->cfg_sg_seg_cnt;
8199
8200 } else {
8201 /*
8202 * The scsi_buf for a regular I/O holds the FCP cmnd,
8203 * the FCP rsp, a SGE for each, and a SGE for up to
8204 * cfg_sg_seg_cnt data segments.
8205 */
8206 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
8207 sizeof(struct fcp_rsp) +
8208 ((phba->cfg_sg_seg_cnt + extra) *
8209 sizeof(struct sli4_sge));
8210
8211 /* Total SGEs for scsi_sg_list */
8212 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + extra;
8213 phba->cfg_scsi_seg_cnt = phba->cfg_sg_seg_cnt;
8214
8215 /*
8216 * NOTE: if (phba->cfg_sg_seg_cnt + extra) <= 256 we only
8217 * need to post 1 page for the SGL.
8218 */
8219 }
8220
8221 if (phba->cfg_xpsgl && !phba->nvmet_support)
8222 phba->cfg_sg_dma_buf_size = LPFC_DEFAULT_XPSGL_SIZE;
8223 else if (phba->cfg_sg_dma_buf_size <= LPFC_MIN_SG_SLI4_BUF_SZ)
8224 phba->cfg_sg_dma_buf_size = LPFC_MIN_SG_SLI4_BUF_SZ;
8225 else
8226 phba->cfg_sg_dma_buf_size =
8227 SLI4_PAGE_ALIGN(phba->cfg_sg_dma_buf_size);
8228
8229 phba->border_sge_num = phba->cfg_sg_dma_buf_size /
8230 sizeof(struct sli4_sge);
8231
8232 /* Limit to LPFC_MAX_NVME_SEG_CNT for NVME. */
8233 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
8234 if (phba->cfg_sg_seg_cnt > LPFC_MAX_NVME_SEG_CNT) {
8235 lpfc_printf_log(phba, KERN_INFO, LOG_NVME | LOG_INIT,
8236 "6300 Reducing NVME sg segment "
8237 "cnt to %d\n",
8238 LPFC_MAX_NVME_SEG_CNT);
8239 phba->cfg_nvme_seg_cnt = LPFC_MAX_NVME_SEG_CNT;
8240 } else
8241 phba->cfg_nvme_seg_cnt = phba->cfg_sg_seg_cnt;
8242 }
8243
d79c9e9d
JS
8244 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
8245 "9087 sg_seg_cnt:%d dmabuf_size:%d "
8246 "total:%d scsi:%d nvme:%d\n",
8247 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
8248 phba->cfg_total_seg_cnt, phba->cfg_scsi_seg_cnt,
8249 phba->cfg_nvme_seg_cnt);
8250
8251 if (phba->cfg_sg_dma_buf_size < SLI4_PAGE_SIZE)
8252 i = phba->cfg_sg_dma_buf_size;
8253 else
8254 i = SLI4_PAGE_SIZE;
8255
8256 phba->lpfc_sg_dma_buf_pool =
8257 dma_pool_create("lpfc_sg_dma_buf_pool",
8258 &phba->pcidev->dev,
8259 phba->cfg_sg_dma_buf_size,
8260 i, 0);
8261 if (!phba->lpfc_sg_dma_buf_pool)
8262 goto out_free_bsmbx;
8263
8264 phba->lpfc_cmd_rsp_buf_pool =
8265 dma_pool_create("lpfc_cmd_rsp_buf_pool",
8266 &phba->pcidev->dev,
8267 sizeof(struct fcp_cmnd) +
8268 sizeof(struct fcp_rsp),
8269 i, 0);
8270 if (!phba->lpfc_cmd_rsp_buf_pool)
8271 goto out_free_sg_dma_buf;
8272
cb5172ea 8273 mempool_free(mboxq, phba->mbox_mem_pool);
1ba981fd
JS
8274
8275 /* Verify OAS is supported */
8276 lpfc_sli4_oas_verify(phba);
1ba981fd 8277
d2cc9bcd
JS
8278 /* Verify RAS support on adapter */
8279 lpfc_sli4_ras_init(phba);
8280
5350d872
JS
8281 /* Verify all the SLI4 queues */
8282 rc = lpfc_sli4_queue_verify(phba);
da0436e9 8283 if (rc)
d79c9e9d 8284 goto out_free_cmd_rsp_buf;
da0436e9
JS
8285
8286 /* Create driver internal CQE event pool */
8287 rc = lpfc_sli4_cq_event_pool_create(phba);
8288 if (rc)
d79c9e9d 8289 goto out_free_cmd_rsp_buf;
da0436e9 8290
8a9d2e80
JS
8291 /* Initialize sgl lists per host */
8292 lpfc_init_sgl_list(phba);
8293
8294 /* Allocate and initialize active sgl array */
da0436e9
JS
8295 rc = lpfc_init_active_sgl_array(phba);
8296 if (rc) {
372c187b 8297 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 8298 "1430 Failed to initialize sgl list.\n");
8a9d2e80 8299 goto out_destroy_cq_event_pool;
da0436e9 8300 }
da0436e9
JS
8301 rc = lpfc_sli4_init_rpi_hdrs(phba);
8302 if (rc) {
372c187b 8303 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
8304 "1432 Failed to initialize rpi headers.\n");
8305 goto out_free_active_sgl;
8306 }
8307
a93ff37a 8308 /* Allocate eligible FCF bmask memory for FCF roundrobin failover */
0c9ab6f5 8309 longs = (LPFC_SLI4_FCF_TBL_INDX_MAX + BITS_PER_LONG - 1)/BITS_PER_LONG;
6396bb22 8310 phba->fcf.fcf_rr_bmask = kcalloc(longs, sizeof(unsigned long),
0c9ab6f5
JS
8311 GFP_KERNEL);
8312 if (!phba->fcf.fcf_rr_bmask) {
372c187b 8313 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0c9ab6f5
JS
8314 "2759 Failed allocate memory for FCF round "
8315 "robin failover bmask\n");
0558056c 8316 rc = -ENOMEM;
0c9ab6f5
JS
8317 goto out_remove_rpi_hdrs;
8318 }
8319
6a828b0f 8320 phba->sli4_hba.hba_eq_hdl = kcalloc(phba->cfg_irq_chann,
cdb42bec
JS
8321 sizeof(struct lpfc_hba_eq_hdl),
8322 GFP_KERNEL);
895427bd 8323 if (!phba->sli4_hba.hba_eq_hdl) {
372c187b 8324 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
67d12733
JS
8325 "2572 Failed allocate memory for "
8326 "fast-path per-EQ handle array\n");
8327 rc = -ENOMEM;
8328 goto out_free_fcf_rr_bmask;
da0436e9
JS
8329 }
8330
222e9239 8331 phba->sli4_hba.cpu_map = kcalloc(phba->sli4_hba.num_possible_cpu,
895427bd
JS
8332 sizeof(struct lpfc_vector_map_info),
8333 GFP_KERNEL);
7bb03bbf 8334 if (!phba->sli4_hba.cpu_map) {
372c187b 8335 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
7bb03bbf
JS
8336 "3327 Failed allocate memory for msi-x "
8337 "interrupt vector mapping\n");
8338 rc = -ENOMEM;
895427bd 8339 goto out_free_hba_eq_hdl;
7bb03bbf 8340 }
b246de17 8341
32517fc0
JS
8342 phba->sli4_hba.eq_info = alloc_percpu(struct lpfc_eq_intr_info);
8343 if (!phba->sli4_hba.eq_info) {
372c187b 8344 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
32517fc0
JS
8345 "3321 Failed allocation for per_cpu stats\n");
8346 rc = -ENOMEM;
8347 goto out_free_hba_cpu_map;
8348 }
840eda96 8349
317aeb83
DK
8350 phba->sli4_hba.idle_stat = kcalloc(phba->sli4_hba.num_possible_cpu,
8351 sizeof(*phba->sli4_hba.idle_stat),
8352 GFP_KERNEL);
8353 if (!phba->sli4_hba.idle_stat) {
372c187b 8354 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
317aeb83
DK
8355 "3390 Failed allocation for idle_stat\n");
8356 rc = -ENOMEM;
8357 goto out_free_hba_eq_info;
8358 }
8359
840eda96
JS
8360#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
8361 phba->sli4_hba.c_stat = alloc_percpu(struct lpfc_hdwq_stat);
8362 if (!phba->sli4_hba.c_stat) {
372c187b 8363 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
840eda96
JS
8364 "3332 Failed allocating per cpu hdwq stats\n");
8365 rc = -ENOMEM;
317aeb83 8366 goto out_free_hba_idle_stat;
840eda96
JS
8367 }
8368#endif
8369
02243836
JS
8370 phba->cmf_stat = alloc_percpu(struct lpfc_cgn_stat);
8371 if (!phba->cmf_stat) {
8372 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
8373 "3331 Failed allocating per cpu cgn stats\n");
8374 rc = -ENOMEM;
8375 goto out_free_hba_hdwq_info;
8376 }
8377
912e3acd
JS
8378 /*
8379 * Enable sr-iov virtual functions if supported and configured
8380 * through the module parameter.
8381 */
8382 if (phba->cfg_sriov_nr_virtfn > 0) {
8383 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
8384 phba->cfg_sriov_nr_virtfn);
8385 if (rc) {
8386 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
8387 "3020 Requested number of SR-IOV "
8388 "virtual functions (%d) is not "
8389 "supported\n",
8390 phba->cfg_sriov_nr_virtfn);
8391 phba->cfg_sriov_nr_virtfn = 0;
8392 }
8393 }
8394
5248a749 8395 return 0;
da0436e9 8396
02243836 8397out_free_hba_hdwq_info:
840eda96 8398#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
37e38409 8399 free_percpu(phba->sli4_hba.c_stat);
317aeb83 8400out_free_hba_idle_stat:
317aeb83 8401#endif
37e38409 8402 kfree(phba->sli4_hba.idle_stat);
840eda96
JS
8403out_free_hba_eq_info:
8404 free_percpu(phba->sli4_hba.eq_info);
32517fc0
JS
8405out_free_hba_cpu_map:
8406 kfree(phba->sli4_hba.cpu_map);
895427bd
JS
8407out_free_hba_eq_hdl:
8408 kfree(phba->sli4_hba.hba_eq_hdl);
0c9ab6f5
JS
8409out_free_fcf_rr_bmask:
8410 kfree(phba->fcf.fcf_rr_bmask);
da0436e9
JS
8411out_remove_rpi_hdrs:
8412 lpfc_sli4_remove_rpi_hdrs(phba);
8413out_free_active_sgl:
8414 lpfc_free_active_sgl(phba);
da0436e9
JS
8415out_destroy_cq_event_pool:
8416 lpfc_sli4_cq_event_pool_destroy(phba);
d79c9e9d
JS
8417out_free_cmd_rsp_buf:
8418 dma_pool_destroy(phba->lpfc_cmd_rsp_buf_pool);
8419 phba->lpfc_cmd_rsp_buf_pool = NULL;
8420out_free_sg_dma_buf:
8421 dma_pool_destroy(phba->lpfc_sg_dma_buf_pool);
8422 phba->lpfc_sg_dma_buf_pool = NULL;
da0436e9
JS
8423out_free_bsmbx:
8424 lpfc_destroy_bootstrap_mbox(phba);
8425out_free_mem:
8426 lpfc_mem_free(phba);
8427 return rc;
8428}
8429
8430/**
8431 * lpfc_sli4_driver_resource_unset - Unset drvr internal resources for SLI4 dev
8432 * @phba: pointer to lpfc hba data structure.
8433 *
8434 * This routine is invoked to unset the driver internal resources set up
8435 * specific for supporting the SLI-4 HBA device it attached to.
8436 **/
8437static void
8438lpfc_sli4_driver_resource_unset(struct lpfc_hba *phba)
8439{
8440 struct lpfc_fcf_conn_entry *conn_entry, *next_conn_entry;
8441
32517fc0 8442 free_percpu(phba->sli4_hba.eq_info);
840eda96
JS
8443#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
8444 free_percpu(phba->sli4_hba.c_stat);
8445#endif
02243836 8446 free_percpu(phba->cmf_stat);
317aeb83 8447 kfree(phba->sli4_hba.idle_stat);
32517fc0 8448
7bb03bbf
JS
8449 /* Free memory allocated for msi-x interrupt vector to CPU mapping */
8450 kfree(phba->sli4_hba.cpu_map);
222e9239 8451 phba->sli4_hba.num_possible_cpu = 0;
7bb03bbf 8452 phba->sli4_hba.num_present_cpu = 0;
76fd07a6 8453 phba->sli4_hba.curr_disp_cpu = 0;
3048e3e8 8454 cpumask_clear(&phba->sli4_hba.irq_aff_mask);
7bb03bbf 8455
da0436e9 8456 /* Free memory allocated for fast-path work queue handles */
895427bd 8457 kfree(phba->sli4_hba.hba_eq_hdl);
da0436e9
JS
8458
8459 /* Free the allocated rpi headers. */
8460 lpfc_sli4_remove_rpi_hdrs(phba);
d11e31dd 8461 lpfc_sli4_remove_rpis(phba);
da0436e9 8462
0c9ab6f5
JS
8463 /* Free eligible FCF index bmask */
8464 kfree(phba->fcf.fcf_rr_bmask);
8465
da0436e9
JS
8466 /* Free the ELS sgl list */
8467 lpfc_free_active_sgl(phba);
8a9d2e80 8468 lpfc_free_els_sgl_list(phba);
f358dd0c 8469 lpfc_free_nvmet_sgl_list(phba);
da0436e9 8470
da0436e9
JS
8471 /* Free the completion queue EQ event pool */
8472 lpfc_sli4_cq_event_release_all(phba);
8473 lpfc_sli4_cq_event_pool_destroy(phba);
8474
6d368e53
JS
8475 /* Release resource identifiers. */
8476 lpfc_sli4_dealloc_resource_identifiers(phba);
8477
da0436e9
JS
8478 /* Free the bsmbx region. */
8479 lpfc_destroy_bootstrap_mbox(phba);
8480
8481 /* Free the SLI Layer memory with SLI4 HBAs */
8482 lpfc_mem_free_all(phba);
8483
8484 /* Free the current connect table */
8485 list_for_each_entry_safe(conn_entry, next_conn_entry,
4d9ab994
JS
8486 &phba->fcf_conn_rec_list, list) {
8487 list_del_init(&conn_entry->list);
da0436e9 8488 kfree(conn_entry);
4d9ab994 8489 }
da0436e9
JS
8490
8491 return;
8492}
8493
8494/**
25985edc 8495 * lpfc_init_api_table_setup - Set up init api function jump table
da0436e9
JS
8496 * @phba: The hba struct for which this call is being executed.
8497 * @dev_grp: The HBA PCI-Device group number.
8498 *
8499 * This routine sets up the device INIT interface API function jump table
8500 * in @phba struct.
8501 *
8502 * Returns: 0 - success, -ENODEV - failure.
8503 **/
8504int
8505lpfc_init_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
8506{
84d1b006
JS
8507 phba->lpfc_hba_init_link = lpfc_hba_init_link;
8508 phba->lpfc_hba_down_link = lpfc_hba_down_link;
7f86059a 8509 phba->lpfc_selective_reset = lpfc_selective_reset;
da0436e9
JS
8510 switch (dev_grp) {
8511 case LPFC_PCI_DEV_LP:
8512 phba->lpfc_hba_down_post = lpfc_hba_down_post_s3;
8513 phba->lpfc_handle_eratt = lpfc_handle_eratt_s3;
8514 phba->lpfc_stop_port = lpfc_stop_port_s3;
8515 break;
8516 case LPFC_PCI_DEV_OC:
8517 phba->lpfc_hba_down_post = lpfc_hba_down_post_s4;
8518 phba->lpfc_handle_eratt = lpfc_handle_eratt_s4;
8519 phba->lpfc_stop_port = lpfc_stop_port_s4;
8520 break;
8521 default:
a516074c 8522 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9
JS
8523 "1431 Invalid HBA PCI-device group: 0x%x\n",
8524 dev_grp);
8525 return -ENODEV;
da0436e9
JS
8526 }
8527 return 0;
8528}
8529
da0436e9
JS
8530/**
8531 * lpfc_setup_driver_resource_phase2 - Phase2 setup driver internal resources.
8532 * @phba: pointer to lpfc hba data structure.
8533 *
8534 * This routine is invoked to set up the driver internal resources after the
8535 * device specific resource setup to support the HBA device it attached to.
8536 *
8537 * Return codes
af901ca1 8538 * 0 - successful
da0436e9
JS
8539 * other values - error
8540 **/
8541static int
8542lpfc_setup_driver_resource_phase2(struct lpfc_hba *phba)
8543{
8544 int error;
8545
8546 /* Startup the kernel thread for this host adapter. */
8547 phba->worker_thread = kthread_run(lpfc_do_work, phba,
8548 "lpfc_worker_%d", phba->brd_no);
8549 if (IS_ERR(phba->worker_thread)) {
8550 error = PTR_ERR(phba->worker_thread);
8551 return error;
3772a991
JS
8552 }
8553
8554 return 0;
8555}
8556
8557/**
8558 * lpfc_unset_driver_resource_phase2 - Phase2 unset driver internal resources.
8559 * @phba: pointer to lpfc hba data structure.
8560 *
8561 * This routine is invoked to unset the driver internal resources set up after
8562 * the device specific resource setup for supporting the HBA device it
8563 * attached to.
8564 **/
8565static void
8566lpfc_unset_driver_resource_phase2(struct lpfc_hba *phba)
8567{
f485c18d 8568 if (phba->wq) {
f485c18d
DK
8569 destroy_workqueue(phba->wq);
8570 phba->wq = NULL;
8571 }
8572
3772a991 8573 /* Stop kernel worker thread */
0cdb84ec
JS
8574 if (phba->worker_thread)
8575 kthread_stop(phba->worker_thread);
3772a991
JS
8576}
8577
8578/**
8579 * lpfc_free_iocb_list - Free iocb list.
8580 * @phba: pointer to lpfc hba data structure.
8581 *
8582 * This routine is invoked to free the driver's IOCB list and memory.
8583 **/
6c621a22 8584void
3772a991
JS
8585lpfc_free_iocb_list(struct lpfc_hba *phba)
8586{
8587 struct lpfc_iocbq *iocbq_entry = NULL, *iocbq_next = NULL;
8588
8589 spin_lock_irq(&phba->hbalock);
8590 list_for_each_entry_safe(iocbq_entry, iocbq_next,
8591 &phba->lpfc_iocb_list, list) {
8592 list_del(&iocbq_entry->list);
8593 kfree(iocbq_entry);
8594 phba->total_iocbq_bufs--;
98c9ea5c 8595 }
3772a991
JS
8596 spin_unlock_irq(&phba->hbalock);
8597
8598 return;
8599}
8600
8601/**
8602 * lpfc_init_iocb_list - Allocate and initialize iocb list.
8603 * @phba: pointer to lpfc hba data structure.
fe614acd 8604 * @iocb_count: number of requested iocbs
3772a991
JS
8605 *
8606 * This routine is invoked to allocate and initizlize the driver's IOCB
8607 * list and set up the IOCB tag array accordingly.
8608 *
8609 * Return codes
af901ca1 8610 * 0 - successful
3772a991
JS
8611 * other values - error
8612 **/
6c621a22 8613int
3772a991
JS
8614lpfc_init_iocb_list(struct lpfc_hba *phba, int iocb_count)
8615{
8616 struct lpfc_iocbq *iocbq_entry = NULL;
8617 uint16_t iotag;
8618 int i;
dea3101e 8619
8620 /* Initialize and populate the iocb list per host. */
8621 INIT_LIST_HEAD(&phba->lpfc_iocb_list);
3772a991 8622 for (i = 0; i < iocb_count; i++) {
dd00cc48 8623 iocbq_entry = kzalloc(sizeof(struct lpfc_iocbq), GFP_KERNEL);
dea3101e 8624 if (iocbq_entry == NULL) {
8625 printk(KERN_ERR "%s: only allocated %d iocbs of "
8626 "expected %d count. Unloading driver.\n",
a5f7337f 8627 __func__, i, iocb_count);
dea3101e 8628 goto out_free_iocbq;
8629 }
8630
604a3e30
JB
8631 iotag = lpfc_sli_next_iotag(phba, iocbq_entry);
8632 if (iotag == 0) {
3772a991 8633 kfree(iocbq_entry);
604a3e30 8634 printk(KERN_ERR "%s: failed to allocate IOTAG. "
3772a991 8635 "Unloading driver.\n", __func__);
604a3e30
JB
8636 goto out_free_iocbq;
8637 }
6d368e53 8638 iocbq_entry->sli4_lxritag = NO_XRI;
3772a991 8639 iocbq_entry->sli4_xritag = NO_XRI;
2e0fef85
JS
8640
8641 spin_lock_irq(&phba->hbalock);
dea3101e 8642 list_add(&iocbq_entry->list, &phba->lpfc_iocb_list);
8643 phba->total_iocbq_bufs++;
2e0fef85 8644 spin_unlock_irq(&phba->hbalock);
dea3101e 8645 }
8646
3772a991 8647 return 0;
dea3101e 8648
3772a991
JS
8649out_free_iocbq:
8650 lpfc_free_iocb_list(phba);
dea3101e 8651
3772a991
JS
8652 return -ENOMEM;
8653}
5e9d9b82 8654
3772a991 8655/**
8a9d2e80 8656 * lpfc_free_sgl_list - Free a given sgl list.
da0436e9 8657 * @phba: pointer to lpfc hba data structure.
8a9d2e80 8658 * @sglq_list: pointer to the head of sgl list.
3772a991 8659 *
8a9d2e80 8660 * This routine is invoked to free a give sgl list and memory.
3772a991 8661 **/
8a9d2e80
JS
8662void
8663lpfc_free_sgl_list(struct lpfc_hba *phba, struct list_head *sglq_list)
3772a991 8664{
da0436e9 8665 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
8a9d2e80
JS
8666
8667 list_for_each_entry_safe(sglq_entry, sglq_next, sglq_list, list) {
8668 list_del(&sglq_entry->list);
8669 lpfc_mbuf_free(phba, sglq_entry->virt, sglq_entry->phys);
8670 kfree(sglq_entry);
8671 }
8672}
8673
8674/**
8675 * lpfc_free_els_sgl_list - Free els sgl list.
8676 * @phba: pointer to lpfc hba data structure.
8677 *
8678 * This routine is invoked to free the driver's els sgl list and memory.
8679 **/
8680static void
8681lpfc_free_els_sgl_list(struct lpfc_hba *phba)
8682{
da0436e9 8683 LIST_HEAD(sglq_list);
dea3101e 8684
8a9d2e80 8685 /* Retrieve all els sgls from driver list */
a789241e 8686 spin_lock_irq(&phba->sli4_hba.sgl_list_lock);
895427bd 8687 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list, &sglq_list);
a789241e 8688 spin_unlock_irq(&phba->sli4_hba.sgl_list_lock);
dea3101e 8689
8a9d2e80
JS
8690 /* Now free the sgl list */
8691 lpfc_free_sgl_list(phba, &sglq_list);
da0436e9 8692}
92d7f7b0 8693
f358dd0c
JS
8694/**
8695 * lpfc_free_nvmet_sgl_list - Free nvmet sgl list.
8696 * @phba: pointer to lpfc hba data structure.
8697 *
8698 * This routine is invoked to free the driver's nvmet sgl list and memory.
8699 **/
8700static void
8701lpfc_free_nvmet_sgl_list(struct lpfc_hba *phba)
8702{
8703 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
8704 LIST_HEAD(sglq_list);
8705
8706 /* Retrieve all nvmet sgls from driver list */
8707 spin_lock_irq(&phba->hbalock);
8708 spin_lock(&phba->sli4_hba.sgl_list_lock);
8709 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list, &sglq_list);
8710 spin_unlock(&phba->sli4_hba.sgl_list_lock);
8711 spin_unlock_irq(&phba->hbalock);
8712
8713 /* Now free the sgl list */
8714 list_for_each_entry_safe(sglq_entry, sglq_next, &sglq_list, list) {
8715 list_del(&sglq_entry->list);
8716 lpfc_nvmet_buf_free(phba, sglq_entry->virt, sglq_entry->phys);
8717 kfree(sglq_entry);
8718 }
4b40d02b
DK
8719
8720 /* Update the nvmet_xri_cnt to reflect no current sgls.
8721 * The next initialization cycle sets the count and allocates
8722 * the sgls over again.
8723 */
8724 phba->sli4_hba.nvmet_xri_cnt = 0;
f358dd0c
JS
8725}
8726
da0436e9
JS
8727/**
8728 * lpfc_init_active_sgl_array - Allocate the buf to track active ELS XRIs.
8729 * @phba: pointer to lpfc hba data structure.
8730 *
8731 * This routine is invoked to allocate the driver's active sgl memory.
8732 * This array will hold the sglq_entry's for active IOs.
8733 **/
8734static int
8735lpfc_init_active_sgl_array(struct lpfc_hba *phba)
8736{
8737 int size;
8738 size = sizeof(struct lpfc_sglq *);
8739 size *= phba->sli4_hba.max_cfg_param.max_xri;
8740
8741 phba->sli4_hba.lpfc_sglq_active_list =
8742 kzalloc(size, GFP_KERNEL);
8743 if (!phba->sli4_hba.lpfc_sglq_active_list)
8744 return -ENOMEM;
8745 return 0;
3772a991
JS
8746}
8747
8748/**
da0436e9 8749 * lpfc_free_active_sgl - Free the buf that tracks active ELS XRIs.
3772a991
JS
8750 * @phba: pointer to lpfc hba data structure.
8751 *
da0436e9
JS
8752 * This routine is invoked to walk through the array of active sglq entries
8753 * and free all of the resources.
8754 * This is just a place holder for now.
3772a991
JS
8755 **/
8756static void
da0436e9 8757lpfc_free_active_sgl(struct lpfc_hba *phba)
3772a991 8758{
da0436e9 8759 kfree(phba->sli4_hba.lpfc_sglq_active_list);
3772a991
JS
8760}
8761
8762/**
da0436e9 8763 * lpfc_init_sgl_list - Allocate and initialize sgl list.
3772a991
JS
8764 * @phba: pointer to lpfc hba data structure.
8765 *
da0436e9
JS
8766 * This routine is invoked to allocate and initizlize the driver's sgl
8767 * list and set up the sgl xritag tag array accordingly.
3772a991 8768 *
3772a991 8769 **/
8a9d2e80 8770static void
da0436e9 8771lpfc_init_sgl_list(struct lpfc_hba *phba)
3772a991 8772{
da0436e9 8773 /* Initialize and populate the sglq list per host/VF. */
895427bd 8774 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_els_sgl_list);
da0436e9 8775 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_els_sgl_list);
f358dd0c 8776 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_sgl_list);
86c67379 8777 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
da0436e9 8778
8a9d2e80
JS
8779 /* els xri-sgl book keeping */
8780 phba->sli4_hba.els_xri_cnt = 0;
0ff10d46 8781
895427bd 8782 /* nvme xri-buffer book keeping */
5e5b511d 8783 phba->sli4_hba.io_xri_cnt = 0;
da0436e9
JS
8784}
8785
8786/**
8787 * lpfc_sli4_init_rpi_hdrs - Post the rpi header memory region to the port
8788 * @phba: pointer to lpfc hba data structure.
8789 *
8790 * This routine is invoked to post rpi header templates to the
88a2cfbb 8791 * port for those SLI4 ports that do not support extents. This routine
da0436e9 8792 * posts a PAGE_SIZE memory region to the port to hold up to
88a2cfbb
JS
8793 * PAGE_SIZE modulo 64 rpi context headers. This is an initialization routine
8794 * and should be called only when interrupts are disabled.
da0436e9
JS
8795 *
8796 * Return codes
af901ca1 8797 * 0 - successful
88a2cfbb 8798 * -ERROR - otherwise.
da0436e9
JS
8799 **/
8800int
8801lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *phba)
8802{
8803 int rc = 0;
da0436e9
JS
8804 struct lpfc_rpi_hdr *rpi_hdr;
8805
8806 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_hdr_list);
ff78d8f9 8807 if (!phba->sli4_hba.rpi_hdrs_in_use)
6d368e53 8808 return rc;
6d368e53
JS
8809 if (phba->sli4_hba.extents_in_use)
8810 return -EIO;
da0436e9
JS
8811
8812 rpi_hdr = lpfc_sli4_create_rpi_hdr(phba);
8813 if (!rpi_hdr) {
372c187b 8814 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
8815 "0391 Error during rpi post operation\n");
8816 lpfc_sli4_remove_rpis(phba);
8817 rc = -ENODEV;
8818 }
8819
8820 return rc;
8821}
8822
8823/**
8824 * lpfc_sli4_create_rpi_hdr - Allocate an rpi header memory region
8825 * @phba: pointer to lpfc hba data structure.
8826 *
8827 * This routine is invoked to allocate a single 4KB memory region to
8828 * support rpis and stores them in the phba. This single region
8829 * provides support for up to 64 rpis. The region is used globally
8830 * by the device.
8831 *
8832 * Returns:
8833 * A valid rpi hdr on success.
8834 * A NULL pointer on any failure.
8835 **/
8836struct lpfc_rpi_hdr *
8837lpfc_sli4_create_rpi_hdr(struct lpfc_hba *phba)
8838{
8839 uint16_t rpi_limit, curr_rpi_range;
8840 struct lpfc_dmabuf *dmabuf;
8841 struct lpfc_rpi_hdr *rpi_hdr;
8842
6d368e53
JS
8843 /*
8844 * If the SLI4 port supports extents, posting the rpi header isn't
8845 * required. Set the expected maximum count and let the actual value
8846 * get set when extents are fully allocated.
8847 */
8848 if (!phba->sli4_hba.rpi_hdrs_in_use)
8849 return NULL;
8850 if (phba->sli4_hba.extents_in_use)
8851 return NULL;
8852
8853 /* The limit on the logical index is just the max_rpi count. */
845d9e8d 8854 rpi_limit = phba->sli4_hba.max_cfg_param.max_rpi;
da0436e9
JS
8855
8856 spin_lock_irq(&phba->hbalock);
6d368e53
JS
8857 /*
8858 * Establish the starting RPI in this header block. The starting
8859 * rpi is normalized to a zero base because the physical rpi is
8860 * port based.
8861 */
97f2ecf1 8862 curr_rpi_range = phba->sli4_hba.next_rpi;
da0436e9
JS
8863 spin_unlock_irq(&phba->hbalock);
8864
845d9e8d
JS
8865 /* Reached full RPI range */
8866 if (curr_rpi_range == rpi_limit)
6d368e53 8867 return NULL;
845d9e8d 8868
da0436e9
JS
8869 /*
8870 * First allocate the protocol header region for the port. The
8871 * port expects a 4KB DMA-mapped memory region that is 4K aligned.
8872 */
8873 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
8874 if (!dmabuf)
8875 return NULL;
8876
750afb08
LC
8877 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
8878 LPFC_HDR_TEMPLATE_SIZE,
8879 &dmabuf->phys, GFP_KERNEL);
da0436e9
JS
8880 if (!dmabuf->virt) {
8881 rpi_hdr = NULL;
8882 goto err_free_dmabuf;
8883 }
8884
da0436e9
JS
8885 if (!IS_ALIGNED(dmabuf->phys, LPFC_HDR_TEMPLATE_SIZE)) {
8886 rpi_hdr = NULL;
8887 goto err_free_coherent;
8888 }
8889
8890 /* Save the rpi header data for cleanup later. */
8891 rpi_hdr = kzalloc(sizeof(struct lpfc_rpi_hdr), GFP_KERNEL);
8892 if (!rpi_hdr)
8893 goto err_free_coherent;
8894
8895 rpi_hdr->dmabuf = dmabuf;
8896 rpi_hdr->len = LPFC_HDR_TEMPLATE_SIZE;
8897 rpi_hdr->page_count = 1;
8898 spin_lock_irq(&phba->hbalock);
6d368e53
JS
8899
8900 /* The rpi_hdr stores the logical index only. */
8901 rpi_hdr->start_rpi = curr_rpi_range;
845d9e8d 8902 rpi_hdr->next_rpi = phba->sli4_hba.next_rpi + LPFC_RPI_HDR_COUNT;
da0436e9
JS
8903 list_add_tail(&rpi_hdr->list, &phba->sli4_hba.lpfc_rpi_hdr_list);
8904
da0436e9
JS
8905 spin_unlock_irq(&phba->hbalock);
8906 return rpi_hdr;
8907
8908 err_free_coherent:
8909 dma_free_coherent(&phba->pcidev->dev, LPFC_HDR_TEMPLATE_SIZE,
8910 dmabuf->virt, dmabuf->phys);
8911 err_free_dmabuf:
8912 kfree(dmabuf);
8913 return NULL;
8914}
8915
8916/**
8917 * lpfc_sli4_remove_rpi_hdrs - Remove all rpi header memory regions
8918 * @phba: pointer to lpfc hba data structure.
8919 *
8920 * This routine is invoked to remove all memory resources allocated
6d368e53
JS
8921 * to support rpis for SLI4 ports not supporting extents. This routine
8922 * presumes the caller has released all rpis consumed by fabric or port
8923 * logins and is prepared to have the header pages removed.
da0436e9
JS
8924 **/
8925void
8926lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *phba)
8927{
8928 struct lpfc_rpi_hdr *rpi_hdr, *next_rpi_hdr;
8929
6d368e53
JS
8930 if (!phba->sli4_hba.rpi_hdrs_in_use)
8931 goto exit;
8932
da0436e9
JS
8933 list_for_each_entry_safe(rpi_hdr, next_rpi_hdr,
8934 &phba->sli4_hba.lpfc_rpi_hdr_list, list) {
8935 list_del(&rpi_hdr->list);
8936 dma_free_coherent(&phba->pcidev->dev, rpi_hdr->len,
8937 rpi_hdr->dmabuf->virt, rpi_hdr->dmabuf->phys);
8938 kfree(rpi_hdr->dmabuf);
8939 kfree(rpi_hdr);
8940 }
6d368e53
JS
8941 exit:
8942 /* There are no rpis available to the port now. */
8943 phba->sli4_hba.next_rpi = 0;
da0436e9
JS
8944}
8945
8946/**
8947 * lpfc_hba_alloc - Allocate driver hba data structure for a device.
8948 * @pdev: pointer to pci device data structure.
8949 *
8950 * This routine is invoked to allocate the driver hba data structure for an
8951 * HBA device. If the allocation is successful, the phba reference to the
8952 * PCI device data structure is set.
8953 *
8954 * Return codes
af901ca1 8955 * pointer to @phba - successful
da0436e9
JS
8956 * NULL - error
8957 **/
8958static struct lpfc_hba *
8959lpfc_hba_alloc(struct pci_dev *pdev)
8960{
8961 struct lpfc_hba *phba;
8962
8963 /* Allocate memory for HBA structure */
8964 phba = kzalloc(sizeof(struct lpfc_hba), GFP_KERNEL);
8965 if (!phba) {
e34ccdfe 8966 dev_err(&pdev->dev, "failed to allocate hba struct\n");
da0436e9
JS
8967 return NULL;
8968 }
8969
8970 /* Set reference to PCI device in HBA structure */
8971 phba->pcidev = pdev;
8972
8973 /* Assign an unused board number */
8974 phba->brd_no = lpfc_get_instance();
8975 if (phba->brd_no < 0) {
8976 kfree(phba);
8977 return NULL;
8978 }
65791f1f 8979 phba->eratt_poll_interval = LPFC_ERATT_POLL_INTERVAL;
da0436e9 8980
4fede78f 8981 spin_lock_init(&phba->ct_ev_lock);
f1c3b0fc
JS
8982 INIT_LIST_HEAD(&phba->ct_ev_waiters);
8983
da0436e9
JS
8984 return phba;
8985}
8986
8987/**
8988 * lpfc_hba_free - Free driver hba data structure with a device.
8989 * @phba: pointer to lpfc hba data structure.
8990 *
8991 * This routine is invoked to free the driver hba data structure with an
8992 * HBA device.
8993 **/
8994static void
8995lpfc_hba_free(struct lpfc_hba *phba)
8996{
5e5b511d
JS
8997 if (phba->sli_rev == LPFC_SLI_REV4)
8998 kfree(phba->sli4_hba.hdwq);
8999
da0436e9
JS
9000 /* Release the driver assigned board number */
9001 idr_remove(&lpfc_hba_index, phba->brd_no);
9002
895427bd
JS
9003 /* Free memory allocated with sli3 rings */
9004 kfree(phba->sli.sli3_ring);
9005 phba->sli.sli3_ring = NULL;
2a76a283 9006
da0436e9
JS
9007 kfree(phba);
9008 return;
9009}
9010
9011/**
9012 * lpfc_create_shost - Create hba physical port with associated scsi host.
9013 * @phba: pointer to lpfc hba data structure.
9014 *
9015 * This routine is invoked to create HBA physical port and associate a SCSI
9016 * host with it.
9017 *
9018 * Return codes
af901ca1 9019 * 0 - successful
da0436e9
JS
9020 * other values - error
9021 **/
9022static int
9023lpfc_create_shost(struct lpfc_hba *phba)
9024{
9025 struct lpfc_vport *vport;
9026 struct Scsi_Host *shost;
9027
9028 /* Initialize HBA FC structure */
9029 phba->fc_edtov = FF_DEF_EDTOV;
9030 phba->fc_ratov = FF_DEF_RATOV;
9031 phba->fc_altov = FF_DEF_ALTOV;
9032 phba->fc_arbtov = FF_DEF_ARBTOV;
9033
d7c47992 9034 atomic_set(&phba->sdev_cnt, 0);
da0436e9
JS
9035 vport = lpfc_create_port(phba, phba->brd_no, &phba->pcidev->dev);
9036 if (!vport)
9037 return -ENODEV;
9038
9039 shost = lpfc_shost_from_vport(vport);
9040 phba->pport = vport;
2ea259ee 9041
f358dd0c
JS
9042 if (phba->nvmet_support) {
9043 /* Only 1 vport (pport) will support NVME target */
ea85a20c
JS
9044 phba->targetport = NULL;
9045 phba->cfg_enable_fc4_type = LPFC_ENABLE_NVME;
9046 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME_DISC,
9047 "6076 NVME Target Found\n");
f358dd0c
JS
9048 }
9049
da0436e9
JS
9050 lpfc_debugfs_initialize(vport);
9051 /* Put reference to SCSI host to driver's device private data */
9052 pci_set_drvdata(phba->pcidev, shost);
2e0fef85 9053
4258e98e
JS
9054 /*
9055 * At this point we are fully registered with PSA. In addition,
9056 * any initial discovery should be completed.
9057 */
9058 vport->load_flag |= FC_ALLOW_FDMI;
8663cbbe
JS
9059 if (phba->cfg_enable_SmartSAN ||
9060 (phba->cfg_fdmi_on == LPFC_FDMI_SUPPORT)) {
4258e98e
JS
9061
9062 /* Setup appropriate attribute masks */
9063 vport->fdmi_hba_mask = LPFC_FDMI2_HBA_ATTR;
8663cbbe 9064 if (phba->cfg_enable_SmartSAN)
4258e98e
JS
9065 vport->fdmi_port_mask = LPFC_FDMI2_SMART_ATTR;
9066 else
9067 vport->fdmi_port_mask = LPFC_FDMI2_PORT_ATTR;
9068 }
3772a991
JS
9069 return 0;
9070}
db2378e0 9071
3772a991
JS
9072/**
9073 * lpfc_destroy_shost - Destroy hba physical port with associated scsi host.
9074 * @phba: pointer to lpfc hba data structure.
9075 *
9076 * This routine is invoked to destroy HBA physical port and the associated
9077 * SCSI host.
9078 **/
9079static void
9080lpfc_destroy_shost(struct lpfc_hba *phba)
9081{
9082 struct lpfc_vport *vport = phba->pport;
9083
9084 /* Destroy physical port that associated with the SCSI host */
9085 destroy_port(vport);
9086
9087 return;
9088}
9089
9090/**
9091 * lpfc_setup_bg - Setup Block guard structures and debug areas.
9092 * @phba: pointer to lpfc hba data structure.
9093 * @shost: the shost to be used to detect Block guard settings.
9094 *
9095 * This routine sets up the local Block guard protocol settings for @shost.
9096 * This routine also allocates memory for debugging bg buffers.
9097 **/
9098static void
9099lpfc_setup_bg(struct lpfc_hba *phba, struct Scsi_Host *shost)
9100{
bbeb79b9
JS
9101 uint32_t old_mask;
9102 uint32_t old_guard;
9103
b3b98b74 9104 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
3772a991
JS
9105 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9106 "1478 Registering BlockGuard with the "
9107 "SCSI layer\n");
bbeb79b9 9108
b3b98b74
JS
9109 old_mask = phba->cfg_prot_mask;
9110 old_guard = phba->cfg_prot_guard;
bbeb79b9
JS
9111
9112 /* Only allow supported values */
b3b98b74 9113 phba->cfg_prot_mask &= (SHOST_DIF_TYPE1_PROTECTION |
bbeb79b9
JS
9114 SHOST_DIX_TYPE0_PROTECTION |
9115 SHOST_DIX_TYPE1_PROTECTION);
b3b98b74
JS
9116 phba->cfg_prot_guard &= (SHOST_DIX_GUARD_IP |
9117 SHOST_DIX_GUARD_CRC);
bbeb79b9
JS
9118
9119 /* DIF Type 1 protection for profiles AST1/C1 is end to end */
b3b98b74
JS
9120 if (phba->cfg_prot_mask == SHOST_DIX_TYPE1_PROTECTION)
9121 phba->cfg_prot_mask |= SHOST_DIF_TYPE1_PROTECTION;
bbeb79b9 9122
b3b98b74
JS
9123 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
9124 if ((old_mask != phba->cfg_prot_mask) ||
9125 (old_guard != phba->cfg_prot_guard))
372c187b 9126 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
bbeb79b9
JS
9127 "1475 Registering BlockGuard with the "
9128 "SCSI layer: mask %d guard %d\n",
b3b98b74
JS
9129 phba->cfg_prot_mask,
9130 phba->cfg_prot_guard);
bbeb79b9 9131
b3b98b74
JS
9132 scsi_host_set_prot(shost, phba->cfg_prot_mask);
9133 scsi_host_set_guard(shost, phba->cfg_prot_guard);
bbeb79b9 9134 } else
372c187b 9135 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
bbeb79b9
JS
9136 "1479 Not Registering BlockGuard with the SCSI "
9137 "layer, Bad protection parameters: %d %d\n",
9138 old_mask, old_guard);
3772a991 9139 }
3772a991
JS
9140}
9141
9142/**
9143 * lpfc_post_init_setup - Perform necessary device post initialization setup.
9144 * @phba: pointer to lpfc hba data structure.
9145 *
9146 * This routine is invoked to perform all the necessary post initialization
9147 * setup for the device.
9148 **/
9149static void
9150lpfc_post_init_setup(struct lpfc_hba *phba)
9151{
9152 struct Scsi_Host *shost;
9153 struct lpfc_adapter_event_header adapter_event;
9154
9155 /* Get the default values for Model Name and Description */
9156 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
9157
9158 /*
9159 * hba setup may have changed the hba_queue_depth so we need to
9160 * adjust the value of can_queue.
9161 */
9162 shost = pci_get_drvdata(phba->pcidev);
9163 shost->can_queue = phba->cfg_hba_queue_depth - 10;
3772a991
JS
9164
9165 lpfc_host_attrib_init(shost);
9166
9167 if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
9168 spin_lock_irq(shost->host_lock);
9169 lpfc_poll_start_timer(phba);
9170 spin_unlock_irq(shost->host_lock);
9171 }
9172
9173 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9174 "0428 Perform SCSI scan\n");
9175 /* Send board arrival event to upper layer */
9176 adapter_event.event_type = FC_REG_ADAPTER_EVENT;
9177 adapter_event.subcategory = LPFC_EVENT_ARRIVAL;
9178 fc_host_post_vendor_event(shost, fc_get_event_number(),
9179 sizeof(adapter_event),
9180 (char *) &adapter_event,
9181 LPFC_NL_VENDOR_ID);
9182 return;
9183}
9184
9185/**
9186 * lpfc_sli_pci_mem_setup - Setup SLI3 HBA PCI memory space.
9187 * @phba: pointer to lpfc hba data structure.
9188 *
9189 * This routine is invoked to set up the PCI device memory space for device
9190 * with SLI-3 interface spec.
9191 *
9192 * Return codes
af901ca1 9193 * 0 - successful
3772a991
JS
9194 * other values - error
9195 **/
9196static int
9197lpfc_sli_pci_mem_setup(struct lpfc_hba *phba)
9198{
f30e1bfd 9199 struct pci_dev *pdev = phba->pcidev;
3772a991
JS
9200 unsigned long bar0map_len, bar2map_len;
9201 int i, hbq_count;
9202 void *ptr;
56de8357 9203 int error;
3772a991 9204
f30e1bfd 9205 if (!pdev)
56de8357 9206 return -ENODEV;
3772a991
JS
9207
9208 /* Set the device DMA mask size */
56de8357
HR
9209 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9210 if (error)
9211 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9212 if (error)
f30e1bfd 9213 return error;
56de8357 9214 error = -ENODEV;
3772a991
JS
9215
9216 /* Get the bus address of Bar0 and Bar2 and the number of bytes
9217 * required by each mapping.
9218 */
9219 phba->pci_bar0_map = pci_resource_start(pdev, 0);
9220 bar0map_len = pci_resource_len(pdev, 0);
9221
9222 phba->pci_bar2_map = pci_resource_start(pdev, 2);
9223 bar2map_len = pci_resource_len(pdev, 2);
9224
9225 /* Map HBA SLIM to a kernel virtual address. */
9226 phba->slim_memmap_p = ioremap(phba->pci_bar0_map, bar0map_len);
9227 if (!phba->slim_memmap_p) {
9228 dev_printk(KERN_ERR, &pdev->dev,
9229 "ioremap failed for SLIM memory.\n");
9230 goto out;
9231 }
9232
9233 /* Map HBA Control Registers to a kernel virtual address. */
9234 phba->ctrl_regs_memmap_p = ioremap(phba->pci_bar2_map, bar2map_len);
9235 if (!phba->ctrl_regs_memmap_p) {
9236 dev_printk(KERN_ERR, &pdev->dev,
9237 "ioremap failed for HBA control registers.\n");
9238 goto out_iounmap_slim;
9239 }
9240
9241 /* Allocate memory for SLI-2 structures */
750afb08
LC
9242 phba->slim2p.virt = dma_alloc_coherent(&pdev->dev, SLI2_SLIM_SIZE,
9243 &phba->slim2p.phys, GFP_KERNEL);
3772a991
JS
9244 if (!phba->slim2p.virt)
9245 goto out_iounmap;
9246
3772a991 9247 phba->mbox = phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, mbx);
7a470277
JS
9248 phba->mbox_ext = (phba->slim2p.virt +
9249 offsetof(struct lpfc_sli2_slim, mbx_ext_words));
3772a991
JS
9250 phba->pcb = (phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, pcb));
9251 phba->IOCBs = (phba->slim2p.virt +
9252 offsetof(struct lpfc_sli2_slim, IOCBs));
9253
9254 phba->hbqslimp.virt = dma_alloc_coherent(&pdev->dev,
9255 lpfc_sli_hbq_size(),
9256 &phba->hbqslimp.phys,
9257 GFP_KERNEL);
9258 if (!phba->hbqslimp.virt)
9259 goto out_free_slim;
9260
9261 hbq_count = lpfc_sli_hbq_count();
9262 ptr = phba->hbqslimp.virt;
9263 for (i = 0; i < hbq_count; ++i) {
9264 phba->hbqs[i].hbq_virt = ptr;
9265 INIT_LIST_HEAD(&phba->hbqs[i].hbq_buffer_list);
9266 ptr += (lpfc_hbq_defs[i]->entry_count *
9267 sizeof(struct lpfc_hbq_entry));
9268 }
9269 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_els_hbq_alloc;
9270 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_els_hbq_free;
9271
9272 memset(phba->hbqslimp.virt, 0, lpfc_sli_hbq_size());
9273
3772a991
JS
9274 phba->MBslimaddr = phba->slim_memmap_p;
9275 phba->HAregaddr = phba->ctrl_regs_memmap_p + HA_REG_OFFSET;
9276 phba->CAregaddr = phba->ctrl_regs_memmap_p + CA_REG_OFFSET;
9277 phba->HSregaddr = phba->ctrl_regs_memmap_p + HS_REG_OFFSET;
9278 phba->HCregaddr = phba->ctrl_regs_memmap_p + HC_REG_OFFSET;
9279
9280 return 0;
9281
9282out_free_slim:
9283 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
9284 phba->slim2p.virt, phba->slim2p.phys);
9285out_iounmap:
9286 iounmap(phba->ctrl_regs_memmap_p);
9287out_iounmap_slim:
9288 iounmap(phba->slim_memmap_p);
9289out:
9290 return error;
9291}
9292
9293/**
9294 * lpfc_sli_pci_mem_unset - Unset SLI3 HBA PCI memory space.
9295 * @phba: pointer to lpfc hba data structure.
9296 *
9297 * This routine is invoked to unset the PCI device memory space for device
9298 * with SLI-3 interface spec.
9299 **/
9300static void
9301lpfc_sli_pci_mem_unset(struct lpfc_hba *phba)
9302{
9303 struct pci_dev *pdev;
9304
9305 /* Obtain PCI device reference */
9306 if (!phba->pcidev)
9307 return;
9308 else
9309 pdev = phba->pcidev;
9310
9311 /* Free coherent DMA memory allocated */
9312 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
9313 phba->hbqslimp.virt, phba->hbqslimp.phys);
9314 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
9315 phba->slim2p.virt, phba->slim2p.phys);
9316
9317 /* I/O memory unmap */
9318 iounmap(phba->ctrl_regs_memmap_p);
9319 iounmap(phba->slim_memmap_p);
9320
9321 return;
9322}
9323
9324/**
da0436e9 9325 * lpfc_sli4_post_status_check - Wait for SLI4 POST done and check status
3772a991
JS
9326 * @phba: pointer to lpfc hba data structure.
9327 *
da0436e9
JS
9328 * This routine is invoked to wait for SLI4 device Power On Self Test (POST)
9329 * done and check status.
3772a991 9330 *
da0436e9 9331 * Return 0 if successful, otherwise -ENODEV.
3772a991 9332 **/
da0436e9
JS
9333int
9334lpfc_sli4_post_status_check(struct lpfc_hba *phba)
3772a991 9335{
2fcee4bf
JS
9336 struct lpfc_register portsmphr_reg, uerrlo_reg, uerrhi_reg;
9337 struct lpfc_register reg_data;
9338 int i, port_error = 0;
9339 uint32_t if_type;
3772a991 9340
9940b97b
JS
9341 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
9342 memset(&reg_data, 0, sizeof(reg_data));
2fcee4bf 9343 if (!phba->sli4_hba.PSMPHRregaddr)
da0436e9 9344 return -ENODEV;
3772a991 9345
da0436e9
JS
9346 /* Wait up to 30 seconds for the SLI Port POST done and ready */
9347 for (i = 0; i < 3000; i++) {
9940b97b
JS
9348 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
9349 &portsmphr_reg.word0) ||
9350 (bf_get(lpfc_port_smphr_perr, &portsmphr_reg))) {
2fcee4bf 9351 /* Port has a fatal POST error, break out */
da0436e9
JS
9352 port_error = -ENODEV;
9353 break;
9354 }
2fcee4bf
JS
9355 if (LPFC_POST_STAGE_PORT_READY ==
9356 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg))
da0436e9 9357 break;
da0436e9 9358 msleep(10);
3772a991
JS
9359 }
9360
2fcee4bf
JS
9361 /*
9362 * If there was a port error during POST, then don't proceed with
9363 * other register reads as the data may not be valid. Just exit.
9364 */
9365 if (port_error) {
372c187b 9366 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
9367 "1408 Port Failed POST - portsmphr=0x%x, "
9368 "perr=x%x, sfi=x%x, nip=x%x, ipc=x%x, scr1=x%x, "
9369 "scr2=x%x, hscratch=x%x, pstatus=x%x\n",
9370 portsmphr_reg.word0,
9371 bf_get(lpfc_port_smphr_perr, &portsmphr_reg),
9372 bf_get(lpfc_port_smphr_sfi, &portsmphr_reg),
9373 bf_get(lpfc_port_smphr_nip, &portsmphr_reg),
9374 bf_get(lpfc_port_smphr_ipc, &portsmphr_reg),
9375 bf_get(lpfc_port_smphr_scr1, &portsmphr_reg),
9376 bf_get(lpfc_port_smphr_scr2, &portsmphr_reg),
9377 bf_get(lpfc_port_smphr_host_scratch, &portsmphr_reg),
9378 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg));
9379 } else {
28baac74 9380 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
2fcee4bf
JS
9381 "2534 Device Info: SLIFamily=0x%x, "
9382 "SLIRev=0x%x, IFType=0x%x, SLIHint_1=0x%x, "
9383 "SLIHint_2=0x%x, FT=0x%x\n",
28baac74
JS
9384 bf_get(lpfc_sli_intf_sli_family,
9385 &phba->sli4_hba.sli_intf),
9386 bf_get(lpfc_sli_intf_slirev,
9387 &phba->sli4_hba.sli_intf),
085c647c
JS
9388 bf_get(lpfc_sli_intf_if_type,
9389 &phba->sli4_hba.sli_intf),
9390 bf_get(lpfc_sli_intf_sli_hint1,
28baac74 9391 &phba->sli4_hba.sli_intf),
085c647c
JS
9392 bf_get(lpfc_sli_intf_sli_hint2,
9393 &phba->sli4_hba.sli_intf),
9394 bf_get(lpfc_sli_intf_func_type,
28baac74 9395 &phba->sli4_hba.sli_intf));
2fcee4bf
JS
9396 /*
9397 * Check for other Port errors during the initialization
9398 * process. Fail the load if the port did not come up
9399 * correctly.
9400 */
9401 if_type = bf_get(lpfc_sli_intf_if_type,
9402 &phba->sli4_hba.sli_intf);
9403 switch (if_type) {
9404 case LPFC_SLI_INTF_IF_TYPE_0:
9405 phba->sli4_hba.ue_mask_lo =
9406 readl(phba->sli4_hba.u.if_type0.UEMASKLOregaddr);
9407 phba->sli4_hba.ue_mask_hi =
9408 readl(phba->sli4_hba.u.if_type0.UEMASKHIregaddr);
9409 uerrlo_reg.word0 =
9410 readl(phba->sli4_hba.u.if_type0.UERRLOregaddr);
9411 uerrhi_reg.word0 =
9412 readl(phba->sli4_hba.u.if_type0.UERRHIregaddr);
9413 if ((~phba->sli4_hba.ue_mask_lo & uerrlo_reg.word0) ||
9414 (~phba->sli4_hba.ue_mask_hi & uerrhi_reg.word0)) {
372c187b
DK
9415 lpfc_printf_log(phba, KERN_ERR,
9416 LOG_TRACE_EVENT,
2fcee4bf
JS
9417 "1422 Unrecoverable Error "
9418 "Detected during POST "
9419 "uerr_lo_reg=0x%x, "
9420 "uerr_hi_reg=0x%x, "
9421 "ue_mask_lo_reg=0x%x, "
9422 "ue_mask_hi_reg=0x%x\n",
9423 uerrlo_reg.word0,
9424 uerrhi_reg.word0,
9425 phba->sli4_hba.ue_mask_lo,
9426 phba->sli4_hba.ue_mask_hi);
9427 port_error = -ENODEV;
9428 }
9429 break;
9430 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 9431 case LPFC_SLI_INTF_IF_TYPE_6:
2fcee4bf 9432 /* Final checks. The port status should be clean. */
9940b97b
JS
9433 if (lpfc_readl(phba->sli4_hba.u.if_type2.STATUSregaddr,
9434 &reg_data.word0) ||
0558056c
JS
9435 (bf_get(lpfc_sliport_status_err, &reg_data) &&
9436 !bf_get(lpfc_sliport_status_rn, &reg_data))) {
2fcee4bf
JS
9437 phba->work_status[0] =
9438 readl(phba->sli4_hba.u.if_type2.
9439 ERR1regaddr);
9440 phba->work_status[1] =
9441 readl(phba->sli4_hba.u.if_type2.
9442 ERR2regaddr);
372c187b 9443 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
8fcb8acd
JS
9444 "2888 Unrecoverable port error "
9445 "following POST: port status reg "
9446 "0x%x, port_smphr reg 0x%x, "
2fcee4bf
JS
9447 "error 1=0x%x, error 2=0x%x\n",
9448 reg_data.word0,
9449 portsmphr_reg.word0,
9450 phba->work_status[0],
9451 phba->work_status[1]);
9452 port_error = -ENODEV;
a5b141a8 9453 break;
2fcee4bf 9454 }
a5b141a8
JS
9455
9456 if (lpfc_pldv_detect &&
9457 bf_get(lpfc_sli_intf_sli_family,
9458 &phba->sli4_hba.sli_intf) ==
9459 LPFC_SLI_INTF_FAMILY_G6)
9460 pci_write_config_byte(phba->pcidev,
9461 LPFC_SLI_INTF, CFG_PLD);
2fcee4bf
JS
9462 break;
9463 case LPFC_SLI_INTF_IF_TYPE_1:
9464 default:
9465 break;
9466 }
28baac74 9467 }
da0436e9
JS
9468 return port_error;
9469}
3772a991 9470
da0436e9
JS
9471/**
9472 * lpfc_sli4_bar0_register_memmap - Set up SLI4 BAR0 register memory map.
9473 * @phba: pointer to lpfc hba data structure.
2fcee4bf 9474 * @if_type: The SLI4 interface type getting configured.
da0436e9
JS
9475 *
9476 * This routine is invoked to set up SLI4 BAR0 PCI config space register
9477 * memory map.
9478 **/
9479static void
2fcee4bf
JS
9480lpfc_sli4_bar0_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
9481{
9482 switch (if_type) {
9483 case LPFC_SLI_INTF_IF_TYPE_0:
9484 phba->sli4_hba.u.if_type0.UERRLOregaddr =
9485 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_LO;
9486 phba->sli4_hba.u.if_type0.UERRHIregaddr =
9487 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_HI;
9488 phba->sli4_hba.u.if_type0.UEMASKLOregaddr =
9489 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_LO;
9490 phba->sli4_hba.u.if_type0.UEMASKHIregaddr =
9491 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_HI;
9492 phba->sli4_hba.SLIINTFregaddr =
9493 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
9494 break;
9495 case LPFC_SLI_INTF_IF_TYPE_2:
0cf07f84
JS
9496 phba->sli4_hba.u.if_type2.EQDregaddr =
9497 phba->sli4_hba.conf_regs_memmap_p +
9498 LPFC_CTL_PORT_EQ_DELAY_OFFSET;
2fcee4bf 9499 phba->sli4_hba.u.if_type2.ERR1regaddr =
88a2cfbb
JS
9500 phba->sli4_hba.conf_regs_memmap_p +
9501 LPFC_CTL_PORT_ER1_OFFSET;
2fcee4bf 9502 phba->sli4_hba.u.if_type2.ERR2regaddr =
88a2cfbb
JS
9503 phba->sli4_hba.conf_regs_memmap_p +
9504 LPFC_CTL_PORT_ER2_OFFSET;
2fcee4bf 9505 phba->sli4_hba.u.if_type2.CTRLregaddr =
88a2cfbb
JS
9506 phba->sli4_hba.conf_regs_memmap_p +
9507 LPFC_CTL_PORT_CTL_OFFSET;
2fcee4bf 9508 phba->sli4_hba.u.if_type2.STATUSregaddr =
88a2cfbb
JS
9509 phba->sli4_hba.conf_regs_memmap_p +
9510 LPFC_CTL_PORT_STA_OFFSET;
2fcee4bf
JS
9511 phba->sli4_hba.SLIINTFregaddr =
9512 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
9513 phba->sli4_hba.PSMPHRregaddr =
88a2cfbb
JS
9514 phba->sli4_hba.conf_regs_memmap_p +
9515 LPFC_CTL_PORT_SEM_OFFSET;
2fcee4bf 9516 phba->sli4_hba.RQDBregaddr =
962bc51b
JS
9517 phba->sli4_hba.conf_regs_memmap_p +
9518 LPFC_ULP0_RQ_DOORBELL;
2fcee4bf 9519 phba->sli4_hba.WQDBregaddr =
962bc51b
JS
9520 phba->sli4_hba.conf_regs_memmap_p +
9521 LPFC_ULP0_WQ_DOORBELL;
9dd35425 9522 phba->sli4_hba.CQDBregaddr =
2fcee4bf 9523 phba->sli4_hba.conf_regs_memmap_p + LPFC_EQCQ_DOORBELL;
9dd35425 9524 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.CQDBregaddr;
2fcee4bf
JS
9525 phba->sli4_hba.MQDBregaddr =
9526 phba->sli4_hba.conf_regs_memmap_p + LPFC_MQ_DOORBELL;
9527 phba->sli4_hba.BMBXregaddr =
9528 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
9529 break;
27d6ac0a
JS
9530 case LPFC_SLI_INTF_IF_TYPE_6:
9531 phba->sli4_hba.u.if_type2.EQDregaddr =
9532 phba->sli4_hba.conf_regs_memmap_p +
9533 LPFC_CTL_PORT_EQ_DELAY_OFFSET;
9534 phba->sli4_hba.u.if_type2.ERR1regaddr =
9535 phba->sli4_hba.conf_regs_memmap_p +
9536 LPFC_CTL_PORT_ER1_OFFSET;
9537 phba->sli4_hba.u.if_type2.ERR2regaddr =
9538 phba->sli4_hba.conf_regs_memmap_p +
9539 LPFC_CTL_PORT_ER2_OFFSET;
9540 phba->sli4_hba.u.if_type2.CTRLregaddr =
9541 phba->sli4_hba.conf_regs_memmap_p +
9542 LPFC_CTL_PORT_CTL_OFFSET;
9543 phba->sli4_hba.u.if_type2.STATUSregaddr =
9544 phba->sli4_hba.conf_regs_memmap_p +
9545 LPFC_CTL_PORT_STA_OFFSET;
9546 phba->sli4_hba.PSMPHRregaddr =
9547 phba->sli4_hba.conf_regs_memmap_p +
9548 LPFC_CTL_PORT_SEM_OFFSET;
9549 phba->sli4_hba.BMBXregaddr =
9550 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
9551 break;
2fcee4bf
JS
9552 case LPFC_SLI_INTF_IF_TYPE_1:
9553 default:
9554 dev_printk(KERN_ERR, &phba->pcidev->dev,
9555 "FATAL - unsupported SLI4 interface type - %d\n",
9556 if_type);
9557 break;
9558 }
da0436e9 9559}
3772a991 9560
da0436e9
JS
9561/**
9562 * lpfc_sli4_bar1_register_memmap - Set up SLI4 BAR1 register memory map.
9563 * @phba: pointer to lpfc hba data structure.
fe614acd 9564 * @if_type: sli if type to operate on.
da0436e9 9565 *
27d6ac0a 9566 * This routine is invoked to set up SLI4 BAR1 register memory map.
da0436e9
JS
9567 **/
9568static void
27d6ac0a 9569lpfc_sli4_bar1_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
da0436e9 9570{
27d6ac0a
JS
9571 switch (if_type) {
9572 case LPFC_SLI_INTF_IF_TYPE_0:
9573 phba->sli4_hba.PSMPHRregaddr =
9574 phba->sli4_hba.ctrl_regs_memmap_p +
9575 LPFC_SLIPORT_IF0_SMPHR;
9576 phba->sli4_hba.ISRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
9577 LPFC_HST_ISR0;
9578 phba->sli4_hba.IMRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
9579 LPFC_HST_IMR0;
9580 phba->sli4_hba.ISCRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
9581 LPFC_HST_ISCR0;
9582 break;
9583 case LPFC_SLI_INTF_IF_TYPE_6:
9584 phba->sli4_hba.RQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
9585 LPFC_IF6_RQ_DOORBELL;
9586 phba->sli4_hba.WQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
9587 LPFC_IF6_WQ_DOORBELL;
9588 phba->sli4_hba.CQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
9589 LPFC_IF6_CQ_DOORBELL;
9590 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
9591 LPFC_IF6_EQ_DOORBELL;
9592 phba->sli4_hba.MQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
9593 LPFC_IF6_MQ_DOORBELL;
9594 break;
9595 case LPFC_SLI_INTF_IF_TYPE_2:
9596 case LPFC_SLI_INTF_IF_TYPE_1:
9597 default:
9598 dev_err(&phba->pcidev->dev,
9599 "FATAL - unsupported SLI4 interface type - %d\n",
9600 if_type);
9601 break;
9602 }
3772a991
JS
9603}
9604
9605/**
da0436e9 9606 * lpfc_sli4_bar2_register_memmap - Set up SLI4 BAR2 register memory map.
3772a991 9607 * @phba: pointer to lpfc hba data structure.
da0436e9 9608 * @vf: virtual function number
3772a991 9609 *
da0436e9
JS
9610 * This routine is invoked to set up SLI4 BAR2 doorbell register memory map
9611 * based on the given viftual function number, @vf.
9612 *
9613 * Return 0 if successful, otherwise -ENODEV.
3772a991 9614 **/
da0436e9
JS
9615static int
9616lpfc_sli4_bar2_register_memmap(struct lpfc_hba *phba, uint32_t vf)
3772a991 9617{
da0436e9
JS
9618 if (vf > LPFC_VIR_FUNC_MAX)
9619 return -ENODEV;
3772a991 9620
da0436e9 9621 phba->sli4_hba.RQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
962bc51b
JS
9622 vf * LPFC_VFR_PAGE_SIZE +
9623 LPFC_ULP0_RQ_DOORBELL);
da0436e9 9624 phba->sli4_hba.WQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
962bc51b
JS
9625 vf * LPFC_VFR_PAGE_SIZE +
9626 LPFC_ULP0_WQ_DOORBELL);
9dd35425
JS
9627 phba->sli4_hba.CQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
9628 vf * LPFC_VFR_PAGE_SIZE +
9629 LPFC_EQCQ_DOORBELL);
9630 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.CQDBregaddr;
da0436e9
JS
9631 phba->sli4_hba.MQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
9632 vf * LPFC_VFR_PAGE_SIZE + LPFC_MQ_DOORBELL);
9633 phba->sli4_hba.BMBXregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
9634 vf * LPFC_VFR_PAGE_SIZE + LPFC_BMBX);
9635 return 0;
3772a991
JS
9636}
9637
9638/**
da0436e9 9639 * lpfc_create_bootstrap_mbox - Create the bootstrap mailbox
3772a991
JS
9640 * @phba: pointer to lpfc hba data structure.
9641 *
da0436e9
JS
9642 * This routine is invoked to create the bootstrap mailbox
9643 * region consistent with the SLI-4 interface spec. This
9644 * routine allocates all memory necessary to communicate
9645 * mailbox commands to the port and sets up all alignment
9646 * needs. No locks are expected to be held when calling
9647 * this routine.
3772a991
JS
9648 *
9649 * Return codes
af901ca1 9650 * 0 - successful
d439d286 9651 * -ENOMEM - could not allocated memory.
da0436e9 9652 **/
3772a991 9653static int
da0436e9 9654lpfc_create_bootstrap_mbox(struct lpfc_hba *phba)
3772a991 9655{
da0436e9
JS
9656 uint32_t bmbx_size;
9657 struct lpfc_dmabuf *dmabuf;
9658 struct dma_address *dma_address;
9659 uint32_t pa_addr;
9660 uint64_t phys_addr;
9661
9662 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
9663 if (!dmabuf)
9664 return -ENOMEM;
3772a991 9665
da0436e9
JS
9666 /*
9667 * The bootstrap mailbox region is comprised of 2 parts
9668 * plus an alignment restriction of 16 bytes.
9669 */
9670 bmbx_size = sizeof(struct lpfc_bmbx_create) + (LPFC_ALIGN_16_BYTE - 1);
750afb08
LC
9671 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev, bmbx_size,
9672 &dmabuf->phys, GFP_KERNEL);
da0436e9
JS
9673 if (!dmabuf->virt) {
9674 kfree(dmabuf);
9675 return -ENOMEM;
3772a991
JS
9676 }
9677
da0436e9
JS
9678 /*
9679 * Initialize the bootstrap mailbox pointers now so that the register
9680 * operations are simple later. The mailbox dma address is required
9681 * to be 16-byte aligned. Also align the virtual memory as each
9682 * maibox is copied into the bmbx mailbox region before issuing the
9683 * command to the port.
9684 */
9685 phba->sli4_hba.bmbx.dmabuf = dmabuf;
9686 phba->sli4_hba.bmbx.bmbx_size = bmbx_size;
9687
9688 phba->sli4_hba.bmbx.avirt = PTR_ALIGN(dmabuf->virt,
9689 LPFC_ALIGN_16_BYTE);
9690 phba->sli4_hba.bmbx.aphys = ALIGN(dmabuf->phys,
9691 LPFC_ALIGN_16_BYTE);
9692
9693 /*
9694 * Set the high and low physical addresses now. The SLI4 alignment
9695 * requirement is 16 bytes and the mailbox is posted to the port
9696 * as two 30-bit addresses. The other data is a bit marking whether
9697 * the 30-bit address is the high or low address.
9698 * Upcast bmbx aphys to 64bits so shift instruction compiles
9699 * clean on 32 bit machines.
9700 */
9701 dma_address = &phba->sli4_hba.bmbx.dma_address;
9702 phys_addr = (uint64_t)phba->sli4_hba.bmbx.aphys;
9703 pa_addr = (uint32_t) ((phys_addr >> 34) & 0x3fffffff);
9704 dma_address->addr_hi = (uint32_t) ((pa_addr << 2) |
9705 LPFC_BMBX_BIT1_ADDR_HI);
9706
9707 pa_addr = (uint32_t) ((phba->sli4_hba.bmbx.aphys >> 4) & 0x3fffffff);
9708 dma_address->addr_lo = (uint32_t) ((pa_addr << 2) |
9709 LPFC_BMBX_BIT1_ADDR_LO);
9710 return 0;
3772a991
JS
9711}
9712
9713/**
da0436e9 9714 * lpfc_destroy_bootstrap_mbox - Destroy all bootstrap mailbox resources
3772a991
JS
9715 * @phba: pointer to lpfc hba data structure.
9716 *
da0436e9
JS
9717 * This routine is invoked to teardown the bootstrap mailbox
9718 * region and release all host resources. This routine requires
9719 * the caller to ensure all mailbox commands recovered, no
9720 * additional mailbox comands are sent, and interrupts are disabled
9721 * before calling this routine.
9722 *
9723 **/
3772a991 9724static void
da0436e9 9725lpfc_destroy_bootstrap_mbox(struct lpfc_hba *phba)
3772a991 9726{
da0436e9
JS
9727 dma_free_coherent(&phba->pcidev->dev,
9728 phba->sli4_hba.bmbx.bmbx_size,
9729 phba->sli4_hba.bmbx.dmabuf->virt,
9730 phba->sli4_hba.bmbx.dmabuf->phys);
9731
9732 kfree(phba->sli4_hba.bmbx.dmabuf);
9733 memset(&phba->sli4_hba.bmbx, 0, sizeof(struct lpfc_bmbx));
3772a991
JS
9734}
9735
83c6cb1a
JS
9736static const char * const lpfc_topo_to_str[] = {
9737 "Loop then P2P",
9738 "Loopback",
9739 "P2P Only",
9740 "Unsupported",
9741 "Loop Only",
9742 "Unsupported",
9743 "P2P then Loop",
9744};
9745
fe614acd
LJ
9746#define LINK_FLAGS_DEF 0x0
9747#define LINK_FLAGS_P2P 0x1
9748#define LINK_FLAGS_LOOP 0x2
83c6cb1a
JS
9749/**
9750 * lpfc_map_topology - Map the topology read from READ_CONFIG
9751 * @phba: pointer to lpfc hba data structure.
fe614acd 9752 * @rd_config: pointer to read config data
83c6cb1a
JS
9753 *
9754 * This routine is invoked to map the topology values as read
9755 * from the read config mailbox command. If the persistent
9756 * topology feature is supported, the firmware will provide the
9757 * saved topology information to be used in INIT_LINK
83c6cb1a 9758 **/
83c6cb1a
JS
9759static void
9760lpfc_map_topology(struct lpfc_hba *phba, struct lpfc_mbx_read_config *rd_config)
9761{
9762 u8 ptv, tf, pt;
9763
9764 ptv = bf_get(lpfc_mbx_rd_conf_ptv, rd_config);
9765 tf = bf_get(lpfc_mbx_rd_conf_tf, rd_config);
9766 pt = bf_get(lpfc_mbx_rd_conf_pt, rd_config);
9767
9768 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
9769 "2027 Read Config Data : ptv:0x%x, tf:0x%x pt:0x%x",
9770 ptv, tf, pt);
9771 if (!ptv) {
9772 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
9773 "2019 FW does not support persistent topology "
9774 "Using driver parameter defined value [%s]",
9775 lpfc_topo_to_str[phba->cfg_topology]);
9776 return;
9777 }
9778 /* FW supports persistent topology - override module parameter value */
9779 phba->hba_flag |= HBA_PERSISTENT_TOPO;
f6c5e6c4
JS
9780
9781 /* if ASIC_GEN_NUM >= 0xC) */
9782 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
9783 LPFC_SLI_INTF_IF_TYPE_6) ||
9784 (bf_get(lpfc_sli_intf_sli_family, &phba->sli4_hba.sli_intf) ==
9785 LPFC_SLI_INTF_FAMILY_G6)) {
83c6cb1a
JS
9786 if (!tf) {
9787 phba->cfg_topology = ((pt == LINK_FLAGS_LOOP)
9788 ? FLAGS_TOPOLOGY_MODE_LOOP
9789 : FLAGS_TOPOLOGY_MODE_PT_PT);
9790 } else {
9791 phba->hba_flag &= ~HBA_PERSISTENT_TOPO;
9792 }
f6c5e6c4 9793 } else { /* G5 */
83c6cb1a
JS
9794 if (tf) {
9795 /* If topology failover set - pt is '0' or '1' */
9796 phba->cfg_topology = (pt ? FLAGS_TOPOLOGY_MODE_PT_LOOP :
9797 FLAGS_TOPOLOGY_MODE_LOOP_PT);
9798 } else {
9799 phba->cfg_topology = ((pt == LINK_FLAGS_P2P)
9800 ? FLAGS_TOPOLOGY_MODE_PT_PT
9801 : FLAGS_TOPOLOGY_MODE_LOOP);
9802 }
83c6cb1a
JS
9803 }
9804 if (phba->hba_flag & HBA_PERSISTENT_TOPO) {
9805 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
9806 "2020 Using persistent topology value [%s]",
9807 lpfc_topo_to_str[phba->cfg_topology]);
9808 } else {
9809 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
9810 "2021 Invalid topology values from FW "
9811 "Using driver parameter defined value [%s]",
9812 lpfc_topo_to_str[phba->cfg_topology]);
9813 }
9814}
9815
3772a991 9816/**
da0436e9 9817 * lpfc_sli4_read_config - Get the config parameters.
3772a991
JS
9818 * @phba: pointer to lpfc hba data structure.
9819 *
da0436e9
JS
9820 * This routine is invoked to read the configuration parameters from the HBA.
9821 * The configuration parameters are used to set the base and maximum values
9822 * for RPI's XRI's VPI's VFI's and FCFIs. These values also affect the resource
9823 * allocation for the port.
3772a991
JS
9824 *
9825 * Return codes
af901ca1 9826 * 0 - successful
25985edc 9827 * -ENOMEM - No available memory
d439d286 9828 * -EIO - The mailbox failed to complete successfully.
3772a991 9829 **/
ff78d8f9 9830int
da0436e9 9831lpfc_sli4_read_config(struct lpfc_hba *phba)
3772a991 9832{
da0436e9
JS
9833 LPFC_MBOXQ_t *pmb;
9834 struct lpfc_mbx_read_config *rd_config;
912e3acd
JS
9835 union lpfc_sli4_cfg_shdr *shdr;
9836 uint32_t shdr_status, shdr_add_status;
9837 struct lpfc_mbx_get_func_cfg *get_func_cfg;
9838 struct lpfc_rsrc_desc_fcfcoe *desc;
8aa134a8 9839 char *pdesc_0;
c691816e 9840 uint16_t forced_link_speed;
6a828b0f 9841 uint32_t if_type, qmin;
8aa134a8 9842 int length, i, rc = 0, rc2;
3772a991 9843
da0436e9
JS
9844 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9845 if (!pmb) {
372c187b 9846 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
9847 "2011 Unable to allocate memory for issuing "
9848 "SLI_CONFIG_SPECIAL mailbox command\n");
9849 return -ENOMEM;
3772a991
JS
9850 }
9851
da0436e9 9852 lpfc_read_config(phba, pmb);
3772a991 9853
da0436e9
JS
9854 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
9855 if (rc != MBX_SUCCESS) {
372c187b
DK
9856 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
9857 "2012 Mailbox failed , mbxCmd x%x "
9858 "READ_CONFIG, mbxStatus x%x\n",
9859 bf_get(lpfc_mqe_command, &pmb->u.mqe),
9860 bf_get(lpfc_mqe_status, &pmb->u.mqe));
da0436e9
JS
9861 rc = -EIO;
9862 } else {
9863 rd_config = &pmb->u.mqe.un.rd_config;
ff78d8f9
JS
9864 if (bf_get(lpfc_mbx_rd_conf_lnk_ldv, rd_config)) {
9865 phba->sli4_hba.lnk_info.lnk_dv = LPFC_LNK_DAT_VAL;
9866 phba->sli4_hba.lnk_info.lnk_tp =
9867 bf_get(lpfc_mbx_rd_conf_lnk_type, rd_config);
9868 phba->sli4_hba.lnk_info.lnk_no =
9869 bf_get(lpfc_mbx_rd_conf_lnk_numb, rd_config);
9870 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
9871 "3081 lnk_type:%d, lnk_numb:%d\n",
9872 phba->sli4_hba.lnk_info.lnk_tp,
9873 phba->sli4_hba.lnk_info.lnk_no);
9874 } else
9875 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
9876 "3082 Mailbox (x%x) returned ldv:x0\n",
9877 bf_get(lpfc_mqe_command, &pmb->u.mqe));
44fd7fe3
JS
9878 if (bf_get(lpfc_mbx_rd_conf_bbscn_def, rd_config)) {
9879 phba->bbcredit_support = 1;
9880 phba->sli4_hba.bbscn_params.word0 = rd_config->word8;
9881 }
9882
1dc5ec24
JS
9883 phba->sli4_hba.conf_trunk =
9884 bf_get(lpfc_mbx_rd_conf_trunk, rd_config);
6d368e53
JS
9885 phba->sli4_hba.extents_in_use =
9886 bf_get(lpfc_mbx_rd_conf_extnts_inuse, rd_config);
da0436e9
JS
9887 phba->sli4_hba.max_cfg_param.max_xri =
9888 bf_get(lpfc_mbx_rd_conf_xri_count, rd_config);
31f06d2e
JS
9889 /* Reduce resource usage in kdump environment */
9890 if (is_kdump_kernel() &&
9891 phba->sli4_hba.max_cfg_param.max_xri > 512)
9892 phba->sli4_hba.max_cfg_param.max_xri = 512;
da0436e9
JS
9893 phba->sli4_hba.max_cfg_param.xri_base =
9894 bf_get(lpfc_mbx_rd_conf_xri_base, rd_config);
9895 phba->sli4_hba.max_cfg_param.max_vpi =
9896 bf_get(lpfc_mbx_rd_conf_vpi_count, rd_config);
8b47ae69
JS
9897 /* Limit the max we support */
9898 if (phba->sli4_hba.max_cfg_param.max_vpi > LPFC_MAX_VPORTS)
9899 phba->sli4_hba.max_cfg_param.max_vpi = LPFC_MAX_VPORTS;
da0436e9
JS
9900 phba->sli4_hba.max_cfg_param.vpi_base =
9901 bf_get(lpfc_mbx_rd_conf_vpi_base, rd_config);
9902 phba->sli4_hba.max_cfg_param.max_rpi =
9903 bf_get(lpfc_mbx_rd_conf_rpi_count, rd_config);
9904 phba->sli4_hba.max_cfg_param.rpi_base =
9905 bf_get(lpfc_mbx_rd_conf_rpi_base, rd_config);
9906 phba->sli4_hba.max_cfg_param.max_vfi =
9907 bf_get(lpfc_mbx_rd_conf_vfi_count, rd_config);
9908 phba->sli4_hba.max_cfg_param.vfi_base =
9909 bf_get(lpfc_mbx_rd_conf_vfi_base, rd_config);
9910 phba->sli4_hba.max_cfg_param.max_fcfi =
9911 bf_get(lpfc_mbx_rd_conf_fcfi_count, rd_config);
da0436e9
JS
9912 phba->sli4_hba.max_cfg_param.max_eq =
9913 bf_get(lpfc_mbx_rd_conf_eq_count, rd_config);
9914 phba->sli4_hba.max_cfg_param.max_rq =
9915 bf_get(lpfc_mbx_rd_conf_rq_count, rd_config);
9916 phba->sli4_hba.max_cfg_param.max_wq =
9917 bf_get(lpfc_mbx_rd_conf_wq_count, rd_config);
9918 phba->sli4_hba.max_cfg_param.max_cq =
9919 bf_get(lpfc_mbx_rd_conf_cq_count, rd_config);
9920 phba->lmt = bf_get(lpfc_mbx_rd_conf_lmt, rd_config);
9921 phba->sli4_hba.next_xri = phba->sli4_hba.max_cfg_param.xri_base;
9922 phba->vpi_base = phba->sli4_hba.max_cfg_param.vpi_base;
9923 phba->vfi_base = phba->sli4_hba.max_cfg_param.vfi_base;
5ffc266e
JS
9924 phba->max_vpi = (phba->sli4_hba.max_cfg_param.max_vpi > 0) ?
9925 (phba->sli4_hba.max_cfg_param.max_vpi - 1) : 0;
da0436e9 9926 phba->max_vports = phba->max_vpi;
9064aeb2
JS
9927
9928 /* Next decide on FPIN or Signal E2E CGN support
9929 * For congestion alarms and warnings valid combination are:
9930 * 1. FPIN alarms / FPIN warnings
9931 * 2. Signal alarms / Signal warnings
9932 * 3. FPIN alarms / Signal warnings
9933 * 4. Signal alarms / FPIN warnings
9934 *
9935 * Initialize the adapter frequency to 100 mSecs
9936 */
9937 phba->cgn_reg_fpin = LPFC_CGN_FPIN_BOTH;
9938 phba->cgn_reg_signal = EDC_CG_SIG_NOTSUPPORTED;
9939 phba->cgn_sig_freq = lpfc_fabric_cgn_frequency;
9940
9941 if (lpfc_use_cgn_signal) {
9942 if (bf_get(lpfc_mbx_rd_conf_wcs, rd_config)) {
9943 phba->cgn_reg_signal = EDC_CG_SIG_WARN_ONLY;
9944 phba->cgn_reg_fpin &= ~LPFC_CGN_FPIN_WARN;
9945 }
9946 if (bf_get(lpfc_mbx_rd_conf_acs, rd_config)) {
9947 /* MUST support both alarm and warning
9948 * because EDC does not support alarm alone.
9949 */
9950 if (phba->cgn_reg_signal !=
9951 EDC_CG_SIG_WARN_ONLY) {
9952 /* Must support both or none */
9953 phba->cgn_reg_fpin = LPFC_CGN_FPIN_BOTH;
9954 phba->cgn_reg_signal =
9955 EDC_CG_SIG_NOTSUPPORTED;
9956 } else {
9957 phba->cgn_reg_signal =
9958 EDC_CG_SIG_WARN_ALARM;
9959 phba->cgn_reg_fpin =
9960 LPFC_CGN_FPIN_NONE;
9961 }
9962 }
9963 }
9964
9965 /* Set the congestion initial signal and fpin values. */
9966 phba->cgn_init_reg_fpin = phba->cgn_reg_fpin;
9967 phba->cgn_init_reg_signal = phba->cgn_reg_signal;
9968
9969 lpfc_printf_log(phba, KERN_INFO, LOG_CGN_MGMT,
9970 "6446 READ_CONFIG reg_sig x%x reg_fpin:x%x\n",
9971 phba->cgn_reg_signal, phba->cgn_reg_fpin);
9972
83c6cb1a 9973 lpfc_map_topology(phba, rd_config);
da0436e9 9974 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
6d368e53
JS
9975 "2003 cfg params Extents? %d "
9976 "XRI(B:%d M:%d), "
da0436e9
JS
9977 "VPI(B:%d M:%d) "
9978 "VFI(B:%d M:%d) "
9979 "RPI(B:%d M:%d) "
a1e4d3d8 9980 "FCFI:%d EQ:%d CQ:%d WQ:%d RQ:%d lmt:x%x\n",
6d368e53 9981 phba->sli4_hba.extents_in_use,
da0436e9
JS
9982 phba->sli4_hba.max_cfg_param.xri_base,
9983 phba->sli4_hba.max_cfg_param.max_xri,
9984 phba->sli4_hba.max_cfg_param.vpi_base,
9985 phba->sli4_hba.max_cfg_param.max_vpi,
9986 phba->sli4_hba.max_cfg_param.vfi_base,
9987 phba->sli4_hba.max_cfg_param.max_vfi,
9988 phba->sli4_hba.max_cfg_param.rpi_base,
9989 phba->sli4_hba.max_cfg_param.max_rpi,
2ea259ee
JS
9990 phba->sli4_hba.max_cfg_param.max_fcfi,
9991 phba->sli4_hba.max_cfg_param.max_eq,
9992 phba->sli4_hba.max_cfg_param.max_cq,
9993 phba->sli4_hba.max_cfg_param.max_wq,
a1e4d3d8
DK
9994 phba->sli4_hba.max_cfg_param.max_rq,
9995 phba->lmt);
2ea259ee 9996
d38f33b3 9997 /*
6a828b0f
JS
9998 * Calculate queue resources based on how
9999 * many WQ/CQ/EQs are available.
d38f33b3 10000 */
6a828b0f
JS
10001 qmin = phba->sli4_hba.max_cfg_param.max_wq;
10002 if (phba->sli4_hba.max_cfg_param.max_cq < qmin)
10003 qmin = phba->sli4_hba.max_cfg_param.max_cq;
10004 if (phba->sli4_hba.max_cfg_param.max_eq < qmin)
10005 qmin = phba->sli4_hba.max_cfg_param.max_eq;
10006 /*
10007 * Whats left after this can go toward NVME / FCP.
10008 * The minus 4 accounts for ELS, NVME LS, MBOX
10009 * plus one extra. When configured for
10010 * NVMET, FCP io channel WQs are not created.
10011 */
10012 qmin -= 4;
d38f33b3 10013
6a828b0f
JS
10014 /* Check to see if there is enough for NVME */
10015 if ((phba->cfg_irq_chann > qmin) ||
10016 (phba->cfg_hdw_queue > qmin)) {
372c187b 10017 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
9e3e365a
DK
10018 "2005 Reducing Queues - "
10019 "FW resource limitation: "
6a828b0f
JS
10020 "WQ %d CQ %d EQ %d: min %d: "
10021 "IRQ %d HDWQ %d\n",
d38f33b3
JS
10022 phba->sli4_hba.max_cfg_param.max_wq,
10023 phba->sli4_hba.max_cfg_param.max_cq,
6a828b0f
JS
10024 phba->sli4_hba.max_cfg_param.max_eq,
10025 qmin, phba->cfg_irq_chann,
cdb42bec 10026 phba->cfg_hdw_queue);
d38f33b3 10027
6a828b0f
JS
10028 if (phba->cfg_irq_chann > qmin)
10029 phba->cfg_irq_chann = qmin;
10030 if (phba->cfg_hdw_queue > qmin)
10031 phba->cfg_hdw_queue = qmin;
d38f33b3 10032 }
3772a991 10033 }
912e3acd
JS
10034
10035 if (rc)
10036 goto read_cfg_out;
da0436e9 10037
c691816e
JS
10038 /* Update link speed if forced link speed is supported */
10039 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
27d6ac0a 10040 if (if_type >= LPFC_SLI_INTF_IF_TYPE_2) {
c691816e
JS
10041 forced_link_speed =
10042 bf_get(lpfc_mbx_rd_conf_link_speed, rd_config);
10043 if (forced_link_speed) {
10044 phba->hba_flag |= HBA_FORCED_LINK_SPEED;
10045
10046 switch (forced_link_speed) {
10047 case LINK_SPEED_1G:
10048 phba->cfg_link_speed =
10049 LPFC_USER_LINK_SPEED_1G;
10050 break;
10051 case LINK_SPEED_2G:
10052 phba->cfg_link_speed =
10053 LPFC_USER_LINK_SPEED_2G;
10054 break;
10055 case LINK_SPEED_4G:
10056 phba->cfg_link_speed =
10057 LPFC_USER_LINK_SPEED_4G;
10058 break;
10059 case LINK_SPEED_8G:
10060 phba->cfg_link_speed =
10061 LPFC_USER_LINK_SPEED_8G;
10062 break;
10063 case LINK_SPEED_10G:
10064 phba->cfg_link_speed =
10065 LPFC_USER_LINK_SPEED_10G;
10066 break;
10067 case LINK_SPEED_16G:
10068 phba->cfg_link_speed =
10069 LPFC_USER_LINK_SPEED_16G;
10070 break;
10071 case LINK_SPEED_32G:
10072 phba->cfg_link_speed =
10073 LPFC_USER_LINK_SPEED_32G;
10074 break;
fbd8a6ba
JS
10075 case LINK_SPEED_64G:
10076 phba->cfg_link_speed =
10077 LPFC_USER_LINK_SPEED_64G;
10078 break;
c691816e
JS
10079 case 0xffff:
10080 phba->cfg_link_speed =
10081 LPFC_USER_LINK_SPEED_AUTO;
10082 break;
10083 default:
372c187b
DK
10084 lpfc_printf_log(phba, KERN_ERR,
10085 LOG_TRACE_EVENT,
c691816e
JS
10086 "0047 Unrecognized link "
10087 "speed : %d\n",
10088 forced_link_speed);
10089 phba->cfg_link_speed =
10090 LPFC_USER_LINK_SPEED_AUTO;
10091 }
10092 }
10093 }
10094
da0436e9 10095 /* Reset the DFT_HBA_Q_DEPTH to the max xri */
572709e2
JS
10096 length = phba->sli4_hba.max_cfg_param.max_xri -
10097 lpfc_sli4_get_els_iocb_cnt(phba);
10098 if (phba->cfg_hba_queue_depth > length) {
10099 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10100 "3361 HBA queue depth changed from %d to %d\n",
10101 phba->cfg_hba_queue_depth, length);
10102 phba->cfg_hba_queue_depth = length;
10103 }
912e3acd 10104
27d6ac0a 10105 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) <
912e3acd
JS
10106 LPFC_SLI_INTF_IF_TYPE_2)
10107 goto read_cfg_out;
10108
10109 /* get the pf# and vf# for SLI4 if_type 2 port */
10110 length = (sizeof(struct lpfc_mbx_get_func_cfg) -
10111 sizeof(struct lpfc_sli4_cfg_mhdr));
10112 lpfc_sli4_config(phba, pmb, LPFC_MBOX_SUBSYSTEM_COMMON,
10113 LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG,
10114 length, LPFC_SLI4_MBX_EMBED);
10115
8aa134a8 10116 rc2 = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
912e3acd
JS
10117 shdr = (union lpfc_sli4_cfg_shdr *)
10118 &pmb->u.mqe.un.sli4_config.header.cfg_shdr;
10119 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
10120 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
8aa134a8 10121 if (rc2 || shdr_status || shdr_add_status) {
372c187b 10122 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
912e3acd
JS
10123 "3026 Mailbox failed , mbxCmd x%x "
10124 "GET_FUNCTION_CONFIG, mbxStatus x%x\n",
10125 bf_get(lpfc_mqe_command, &pmb->u.mqe),
10126 bf_get(lpfc_mqe_status, &pmb->u.mqe));
912e3acd
JS
10127 goto read_cfg_out;
10128 }
10129
10130 /* search for fc_fcoe resrouce descriptor */
10131 get_func_cfg = &pmb->u.mqe.un.get_func_cfg;
912e3acd 10132
8aa134a8
JS
10133 pdesc_0 = (char *)&get_func_cfg->func_cfg.desc[0];
10134 desc = (struct lpfc_rsrc_desc_fcfcoe *)pdesc_0;
10135 length = bf_get(lpfc_rsrc_desc_fcfcoe_length, desc);
10136 if (length == LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD)
10137 length = LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH;
10138 else if (length != LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH)
10139 goto read_cfg_out;
10140
912e3acd 10141 for (i = 0; i < LPFC_RSRC_DESC_MAX_NUM; i++) {
8aa134a8 10142 desc = (struct lpfc_rsrc_desc_fcfcoe *)(pdesc_0 + length * i);
912e3acd 10143 if (LPFC_RSRC_DESC_TYPE_FCFCOE ==
8aa134a8 10144 bf_get(lpfc_rsrc_desc_fcfcoe_type, desc)) {
912e3acd
JS
10145 phba->sli4_hba.iov.pf_number =
10146 bf_get(lpfc_rsrc_desc_fcfcoe_pfnum, desc);
10147 phba->sli4_hba.iov.vf_number =
10148 bf_get(lpfc_rsrc_desc_fcfcoe_vfnum, desc);
10149 break;
10150 }
10151 }
10152
10153 if (i < LPFC_RSRC_DESC_MAX_NUM)
10154 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
10155 "3027 GET_FUNCTION_CONFIG: pf_number:%d, "
10156 "vf_number:%d\n", phba->sli4_hba.iov.pf_number,
10157 phba->sli4_hba.iov.vf_number);
8aa134a8 10158 else
372c187b 10159 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
912e3acd 10160 "3028 GET_FUNCTION_CONFIG: failed to find "
c4dba187 10161 "Resource Descriptor:x%x\n",
912e3acd 10162 LPFC_RSRC_DESC_TYPE_FCFCOE);
912e3acd
JS
10163
10164read_cfg_out:
10165 mempool_free(pmb, phba->mbox_mem_pool);
da0436e9 10166 return rc;
3772a991
JS
10167}
10168
10169/**
2fcee4bf 10170 * lpfc_setup_endian_order - Write endian order to an SLI4 if_type 0 port.
3772a991
JS
10171 * @phba: pointer to lpfc hba data structure.
10172 *
2fcee4bf
JS
10173 * This routine is invoked to setup the port-side endian order when
10174 * the port if_type is 0. This routine has no function for other
10175 * if_types.
da0436e9
JS
10176 *
10177 * Return codes
af901ca1 10178 * 0 - successful
25985edc 10179 * -ENOMEM - No available memory
d439d286 10180 * -EIO - The mailbox failed to complete successfully.
3772a991 10181 **/
da0436e9
JS
10182static int
10183lpfc_setup_endian_order(struct lpfc_hba *phba)
3772a991 10184{
da0436e9 10185 LPFC_MBOXQ_t *mboxq;
2fcee4bf 10186 uint32_t if_type, rc = 0;
da0436e9
JS
10187 uint32_t endian_mb_data[2] = {HOST_ENDIAN_LOW_WORD0,
10188 HOST_ENDIAN_HIGH_WORD1};
3772a991 10189
2fcee4bf
JS
10190 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
10191 switch (if_type) {
10192 case LPFC_SLI_INTF_IF_TYPE_0:
10193 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
10194 GFP_KERNEL);
10195 if (!mboxq) {
372c187b 10196 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
10197 "0492 Unable to allocate memory for "
10198 "issuing SLI_CONFIG_SPECIAL mailbox "
10199 "command\n");
10200 return -ENOMEM;
10201 }
3772a991 10202
2fcee4bf
JS
10203 /*
10204 * The SLI4_CONFIG_SPECIAL mailbox command requires the first
10205 * two words to contain special data values and no other data.
10206 */
10207 memset(mboxq, 0, sizeof(LPFC_MBOXQ_t));
10208 memcpy(&mboxq->u.mqe, &endian_mb_data, sizeof(endian_mb_data));
10209 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
10210 if (rc != MBX_SUCCESS) {
372c187b 10211 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
10212 "0493 SLI_CONFIG_SPECIAL mailbox "
10213 "failed with status x%x\n",
10214 rc);
10215 rc = -EIO;
10216 }
10217 mempool_free(mboxq, phba->mbox_mem_pool);
10218 break;
27d6ac0a 10219 case LPFC_SLI_INTF_IF_TYPE_6:
2fcee4bf
JS
10220 case LPFC_SLI_INTF_IF_TYPE_2:
10221 case LPFC_SLI_INTF_IF_TYPE_1:
10222 default:
10223 break;
da0436e9 10224 }
da0436e9 10225 return rc;
3772a991
JS
10226}
10227
10228/**
895427bd 10229 * lpfc_sli4_queue_verify - Verify and update EQ counts
3772a991
JS
10230 * @phba: pointer to lpfc hba data structure.
10231 *
895427bd
JS
10232 * This routine is invoked to check the user settable queue counts for EQs.
10233 * After this routine is called the counts will be set to valid values that
5350d872
JS
10234 * adhere to the constraints of the system's interrupt vectors and the port's
10235 * queue resources.
da0436e9
JS
10236 *
10237 * Return codes
af901ca1 10238 * 0 - successful
25985edc 10239 * -ENOMEM - No available memory
3772a991 10240 **/
da0436e9 10241static int
5350d872 10242lpfc_sli4_queue_verify(struct lpfc_hba *phba)
3772a991 10243{
da0436e9 10244 /*
67d12733 10245 * Sanity check for configured queue parameters against the run-time
da0436e9
JS
10246 * device parameters
10247 */
3772a991 10248
bcb24f65 10249 if (phba->nvmet_support) {
97a9ed3b
JS
10250 if (phba->cfg_hdw_queue < phba->cfg_nvmet_mrq)
10251 phba->cfg_nvmet_mrq = phba->cfg_hdw_queue;
982ab128
JS
10252 if (phba->cfg_nvmet_mrq > LPFC_NVMET_MRQ_MAX)
10253 phba->cfg_nvmet_mrq = LPFC_NVMET_MRQ_MAX;
bcb24f65 10254 }
895427bd
JS
10255
10256 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6a828b0f
JS
10257 "2574 IO channels: hdwQ %d IRQ %d MRQ: %d\n",
10258 phba->cfg_hdw_queue, phba->cfg_irq_chann,
10259 phba->cfg_nvmet_mrq);
3772a991 10260
da0436e9
JS
10261 /* Get EQ depth from module parameter, fake the default for now */
10262 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
10263 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
3772a991 10264
5350d872
JS
10265 /* Get CQ depth from module parameter, fake the default for now */
10266 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
10267 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
895427bd
JS
10268 return 0;
10269}
10270
10271static int
c00f62e6 10272lpfc_alloc_io_wq_cq(struct lpfc_hba *phba, int idx)
895427bd
JS
10273{
10274 struct lpfc_queue *qdesc;
c00f62e6 10275 u32 wqesize;
c1a21ebc 10276 int cpu;
895427bd 10277
c00f62e6
JS
10278 cpu = lpfc_find_cpu_handle(phba, idx, LPFC_FIND_BY_HDWQ);
10279 /* Create Fast Path IO CQs */
c176ffa0 10280 if (phba->enab_exp_wqcq_pages)
a51e41b6
JS
10281 /* Increase the CQ size when WQEs contain an embedded cdb */
10282 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
10283 phba->sli4_hba.cq_esize,
c1a21ebc 10284 LPFC_CQE_EXP_COUNT, cpu);
a51e41b6
JS
10285
10286 else
10287 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
10288 phba->sli4_hba.cq_esize,
c1a21ebc 10289 phba->sli4_hba.cq_ecount, cpu);
895427bd 10290 if (!qdesc) {
372c187b
DK
10291 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
10292 "0499 Failed allocate fast-path IO CQ (%d)\n",
10293 idx);
895427bd
JS
10294 return 1;
10295 }
7365f6fd 10296 qdesc->qe_valid = 1;
c00f62e6 10297 qdesc->hdwq = idx;
c1a21ebc 10298 qdesc->chann = cpu;
c00f62e6 10299 phba->sli4_hba.hdwq[idx].io_cq = qdesc;
895427bd 10300
c00f62e6 10301 /* Create Fast Path IO WQs */
c176ffa0 10302 if (phba->enab_exp_wqcq_pages) {
a51e41b6 10303 /* Increase the WQ size when WQEs contain an embedded cdb */
c176ffa0
JS
10304 wqesize = (phba->fcp_embed_io) ?
10305 LPFC_WQE128_SIZE : phba->sli4_hba.wq_esize;
a51e41b6 10306 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
c176ffa0 10307 wqesize,
c1a21ebc 10308 LPFC_WQE_EXP_COUNT, cpu);
c176ffa0 10309 } else
a51e41b6
JS
10310 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
10311 phba->sli4_hba.wq_esize,
c1a21ebc 10312 phba->sli4_hba.wq_ecount, cpu);
c176ffa0 10313
895427bd 10314 if (!qdesc) {
372c187b 10315 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
c00f62e6
JS
10316 "0503 Failed allocate fast-path IO WQ (%d)\n",
10317 idx);
895427bd
JS
10318 return 1;
10319 }
c00f62e6
JS
10320 qdesc->hdwq = idx;
10321 qdesc->chann = cpu;
10322 phba->sli4_hba.hdwq[idx].io_wq = qdesc;
895427bd 10323 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
5350d872 10324 return 0;
5350d872
JS
10325}
10326
10327/**
10328 * lpfc_sli4_queue_create - Create all the SLI4 queues
10329 * @phba: pointer to lpfc hba data structure.
10330 *
10331 * This routine is invoked to allocate all the SLI4 queues for the FCoE HBA
10332 * operation. For each SLI4 queue type, the parameters such as queue entry
10333 * count (queue depth) shall be taken from the module parameter. For now,
10334 * we just use some constant number as place holder.
10335 *
10336 * Return codes
4907cb7b 10337 * 0 - successful
5350d872
JS
10338 * -ENOMEM - No availble memory
10339 * -EIO - The mailbox failed to complete successfully.
10340 **/
10341int
10342lpfc_sli4_queue_create(struct lpfc_hba *phba)
10343{
10344 struct lpfc_queue *qdesc;
657add4e 10345 int idx, cpu, eqcpu;
5e5b511d 10346 struct lpfc_sli4_hdw_queue *qp;
657add4e
JS
10347 struct lpfc_vector_map_info *cpup;
10348 struct lpfc_vector_map_info *eqcpup;
32517fc0 10349 struct lpfc_eq_intr_info *eqi;
5350d872
JS
10350
10351 /*
67d12733 10352 * Create HBA Record arrays.
895427bd 10353 * Both NVME and FCP will share that same vectors / EQs
5350d872 10354 */
67d12733
JS
10355 phba->sli4_hba.mq_esize = LPFC_MQE_SIZE;
10356 phba->sli4_hba.mq_ecount = LPFC_MQE_DEF_COUNT;
10357 phba->sli4_hba.wq_esize = LPFC_WQE_SIZE;
10358 phba->sli4_hba.wq_ecount = LPFC_WQE_DEF_COUNT;
10359 phba->sli4_hba.rq_esize = LPFC_RQE_SIZE;
10360 phba->sli4_hba.rq_ecount = LPFC_RQE_DEF_COUNT;
895427bd
JS
10361 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
10362 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
10363 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
10364 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
67d12733 10365
cdb42bec 10366 if (!phba->sli4_hba.hdwq) {
5e5b511d
JS
10367 phba->sli4_hba.hdwq = kcalloc(
10368 phba->cfg_hdw_queue, sizeof(struct lpfc_sli4_hdw_queue),
10369 GFP_KERNEL);
10370 if (!phba->sli4_hba.hdwq) {
372c187b 10371 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5e5b511d
JS
10372 "6427 Failed allocate memory for "
10373 "fast-path Hardware Queue array\n");
895427bd
JS
10374 goto out_error;
10375 }
5e5b511d
JS
10376 /* Prepare hardware queues to take IO buffers */
10377 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
10378 qp = &phba->sli4_hba.hdwq[idx];
10379 spin_lock_init(&qp->io_buf_list_get_lock);
10380 spin_lock_init(&qp->io_buf_list_put_lock);
10381 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_get);
10382 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_put);
10383 qp->get_io_bufs = 0;
10384 qp->put_io_bufs = 0;
10385 qp->total_io_bufs = 0;
c00f62e6
JS
10386 spin_lock_init(&qp->abts_io_buf_list_lock);
10387 INIT_LIST_HEAD(&qp->lpfc_abts_io_buf_list);
5e5b511d 10388 qp->abts_scsi_io_bufs = 0;
5e5b511d 10389 qp->abts_nvme_io_bufs = 0;
d79c9e9d
JS
10390 INIT_LIST_HEAD(&qp->sgl_list);
10391 INIT_LIST_HEAD(&qp->cmd_rsp_buf_list);
10392 spin_lock_init(&qp->hdwq_lock);
895427bd 10393 }
67d12733
JS
10394 }
10395
cdb42bec 10396 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
2d7dbc4c
JS
10397 if (phba->nvmet_support) {
10398 phba->sli4_hba.nvmet_cqset = kcalloc(
10399 phba->cfg_nvmet_mrq,
10400 sizeof(struct lpfc_queue *),
10401 GFP_KERNEL);
10402 if (!phba->sli4_hba.nvmet_cqset) {
372c187b 10403 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
10404 "3121 Fail allocate memory for "
10405 "fast-path CQ set array\n");
10406 goto out_error;
10407 }
10408 phba->sli4_hba.nvmet_mrq_hdr = kcalloc(
10409 phba->cfg_nvmet_mrq,
10410 sizeof(struct lpfc_queue *),
10411 GFP_KERNEL);
10412 if (!phba->sli4_hba.nvmet_mrq_hdr) {
372c187b 10413 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
10414 "3122 Fail allocate memory for "
10415 "fast-path RQ set hdr array\n");
10416 goto out_error;
10417 }
10418 phba->sli4_hba.nvmet_mrq_data = kcalloc(
10419 phba->cfg_nvmet_mrq,
10420 sizeof(struct lpfc_queue *),
10421 GFP_KERNEL);
10422 if (!phba->sli4_hba.nvmet_mrq_data) {
372c187b 10423 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
10424 "3124 Fail allocate memory for "
10425 "fast-path RQ set data array\n");
10426 goto out_error;
10427 }
10428 }
da0436e9 10429 }
67d12733 10430
895427bd 10431 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
67d12733 10432
895427bd 10433 /* Create HBA Event Queues (EQs) */
657add4e
JS
10434 for_each_present_cpu(cpu) {
10435 /* We only want to create 1 EQ per vector, even though
10436 * multiple CPUs might be using that vector. so only
10437 * selects the CPUs that are LPFC_CPU_FIRST_IRQ.
6a828b0f 10438 */
657add4e
JS
10439 cpup = &phba->sli4_hba.cpu_map[cpu];
10440 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
6a828b0f 10441 continue;
657add4e
JS
10442
10443 /* Get a ptr to the Hardware Queue associated with this CPU */
10444 qp = &phba->sli4_hba.hdwq[cpup->hdwq];
10445
10446 /* Allocate an EQ */
81b96eda
JS
10447 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
10448 phba->sli4_hba.eq_esize,
c1a21ebc 10449 phba->sli4_hba.eq_ecount, cpu);
da0436e9 10450 if (!qdesc) {
372c187b 10451 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
657add4e
JS
10452 "0497 Failed allocate EQ (%d)\n",
10453 cpup->hdwq);
67d12733 10454 goto out_error;
da0436e9 10455 }
7365f6fd 10456 qdesc->qe_valid = 1;
657add4e 10457 qdesc->hdwq = cpup->hdwq;
3ad348d9 10458 qdesc->chann = cpu; /* First CPU this EQ is affinitized to */
32517fc0 10459 qdesc->last_cpu = qdesc->chann;
657add4e
JS
10460
10461 /* Save the allocated EQ in the Hardware Queue */
10462 qp->hba_eq = qdesc;
10463
32517fc0
JS
10464 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, qdesc->last_cpu);
10465 list_add(&qdesc->cpu_list, &eqi->list);
895427bd 10466 }
67d12733 10467
657add4e
JS
10468 /* Now we need to populate the other Hardware Queues, that share
10469 * an IRQ vector, with the associated EQ ptr.
10470 */
10471 for_each_present_cpu(cpu) {
10472 cpup = &phba->sli4_hba.cpu_map[cpu];
10473
10474 /* Check for EQ already allocated in previous loop */
10475 if (cpup->flag & LPFC_CPU_FIRST_IRQ)
10476 continue;
10477
10478 /* Check for multiple CPUs per hdwq */
10479 qp = &phba->sli4_hba.hdwq[cpup->hdwq];
10480 if (qp->hba_eq)
10481 continue;
10482
10483 /* We need to share an EQ for this hdwq */
10484 eqcpu = lpfc_find_cpu_handle(phba, cpup->eq, LPFC_FIND_BY_EQ);
10485 eqcpup = &phba->sli4_hba.cpu_map[eqcpu];
10486 qp->hba_eq = phba->sli4_hba.hdwq[eqcpup->hdwq].hba_eq;
10487 }
67d12733 10488
c00f62e6 10489 /* Allocate IO Path SLI4 CQ/WQs */
6a828b0f 10490 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
c00f62e6 10491 if (lpfc_alloc_io_wq_cq(phba, idx))
67d12733 10492 goto out_error;
6a828b0f 10493 }
da0436e9 10494
c00f62e6
JS
10495 if (phba->nvmet_support) {
10496 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
10497 cpu = lpfc_find_cpu_handle(phba, idx,
10498 LPFC_FIND_BY_HDWQ);
10499 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda
JS
10500 LPFC_DEFAULT_PAGE_SIZE,
10501 phba->sli4_hba.cq_esize,
c1a21ebc
JS
10502 phba->sli4_hba.cq_ecount,
10503 cpu);
c00f62e6 10504 if (!qdesc) {
372c187b 10505 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
cdb42bec
JS
10506 "3142 Failed allocate NVME "
10507 "CQ Set (%d)\n", idx);
c00f62e6 10508 goto out_error;
2d7dbc4c 10509 }
c00f62e6
JS
10510 qdesc->qe_valid = 1;
10511 qdesc->hdwq = idx;
10512 qdesc->chann = cpu;
10513 phba->sli4_hba.nvmet_cqset[idx] = qdesc;
2d7dbc4c
JS
10514 }
10515 }
10516
da0436e9 10517 /*
67d12733 10518 * Create Slow Path Completion Queues (CQs)
da0436e9
JS
10519 */
10520
c1a21ebc 10521 cpu = lpfc_find_cpu_handle(phba, 0, LPFC_FIND_BY_EQ);
da0436e9 10522 /* Create slow-path Mailbox Command Complete Queue */
81b96eda
JS
10523 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
10524 phba->sli4_hba.cq_esize,
c1a21ebc 10525 phba->sli4_hba.cq_ecount, cpu);
da0436e9 10526 if (!qdesc) {
372c187b 10527 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 10528 "0500 Failed allocate slow-path mailbox CQ\n");
67d12733 10529 goto out_error;
da0436e9 10530 }
7365f6fd 10531 qdesc->qe_valid = 1;
da0436e9
JS
10532 phba->sli4_hba.mbx_cq = qdesc;
10533
10534 /* Create slow-path ELS Complete Queue */
81b96eda
JS
10535 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
10536 phba->sli4_hba.cq_esize,
c1a21ebc 10537 phba->sli4_hba.cq_ecount, cpu);
da0436e9 10538 if (!qdesc) {
372c187b 10539 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 10540 "0501 Failed allocate slow-path ELS CQ\n");
67d12733 10541 goto out_error;
da0436e9 10542 }
7365f6fd 10543 qdesc->qe_valid = 1;
c00f62e6 10544 qdesc->chann = cpu;
da0436e9
JS
10545 phba->sli4_hba.els_cq = qdesc;
10546
da0436e9 10547
5350d872 10548 /*
67d12733 10549 * Create Slow Path Work Queues (WQs)
5350d872 10550 */
da0436e9
JS
10551
10552 /* Create Mailbox Command Queue */
da0436e9 10553
81b96eda
JS
10554 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
10555 phba->sli4_hba.mq_esize,
c1a21ebc 10556 phba->sli4_hba.mq_ecount, cpu);
da0436e9 10557 if (!qdesc) {
372c187b 10558 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 10559 "0505 Failed allocate slow-path MQ\n");
67d12733 10560 goto out_error;
da0436e9 10561 }
c00f62e6 10562 qdesc->chann = cpu;
da0436e9
JS
10563 phba->sli4_hba.mbx_wq = qdesc;
10564
10565 /*
67d12733 10566 * Create ELS Work Queues
da0436e9 10567 */
da0436e9
JS
10568
10569 /* Create slow-path ELS Work Queue */
81b96eda
JS
10570 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
10571 phba->sli4_hba.wq_esize,
c1a21ebc 10572 phba->sli4_hba.wq_ecount, cpu);
da0436e9 10573 if (!qdesc) {
372c187b 10574 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 10575 "0504 Failed allocate slow-path ELS WQ\n");
67d12733 10576 goto out_error;
da0436e9 10577 }
c00f62e6 10578 qdesc->chann = cpu;
da0436e9 10579 phba->sli4_hba.els_wq = qdesc;
895427bd
JS
10580 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
10581
10582 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
10583 /* Create NVME LS Complete Queue */
81b96eda
JS
10584 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
10585 phba->sli4_hba.cq_esize,
c1a21ebc 10586 phba->sli4_hba.cq_ecount, cpu);
895427bd 10587 if (!qdesc) {
372c187b 10588 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
10589 "6079 Failed allocate NVME LS CQ\n");
10590 goto out_error;
10591 }
c00f62e6 10592 qdesc->chann = cpu;
7365f6fd 10593 qdesc->qe_valid = 1;
895427bd
JS
10594 phba->sli4_hba.nvmels_cq = qdesc;
10595
10596 /* Create NVME LS Work Queue */
81b96eda
JS
10597 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
10598 phba->sli4_hba.wq_esize,
c1a21ebc 10599 phba->sli4_hba.wq_ecount, cpu);
895427bd 10600 if (!qdesc) {
372c187b 10601 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
10602 "6080 Failed allocate NVME LS WQ\n");
10603 goto out_error;
10604 }
c00f62e6 10605 qdesc->chann = cpu;
895427bd
JS
10606 phba->sli4_hba.nvmels_wq = qdesc;
10607 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
10608 }
da0436e9 10609
da0436e9
JS
10610 /*
10611 * Create Receive Queue (RQ)
10612 */
da0436e9
JS
10613
10614 /* Create Receive Queue for header */
81b96eda
JS
10615 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
10616 phba->sli4_hba.rq_esize,
c1a21ebc 10617 phba->sli4_hba.rq_ecount, cpu);
da0436e9 10618 if (!qdesc) {
372c187b 10619 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 10620 "0506 Failed allocate receive HRQ\n");
67d12733 10621 goto out_error;
da0436e9
JS
10622 }
10623 phba->sli4_hba.hdr_rq = qdesc;
10624
10625 /* Create Receive Queue for data */
81b96eda
JS
10626 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
10627 phba->sli4_hba.rq_esize,
c1a21ebc 10628 phba->sli4_hba.rq_ecount, cpu);
da0436e9 10629 if (!qdesc) {
372c187b 10630 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 10631 "0507 Failed allocate receive DRQ\n");
67d12733 10632 goto out_error;
da0436e9
JS
10633 }
10634 phba->sli4_hba.dat_rq = qdesc;
10635
cdb42bec
JS
10636 if ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) &&
10637 phba->nvmet_support) {
2d7dbc4c 10638 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
c1a21ebc
JS
10639 cpu = lpfc_find_cpu_handle(phba, idx,
10640 LPFC_FIND_BY_HDWQ);
2d7dbc4c
JS
10641 /* Create NVMET Receive Queue for header */
10642 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda 10643 LPFC_DEFAULT_PAGE_SIZE,
2d7dbc4c 10644 phba->sli4_hba.rq_esize,
c1a21ebc
JS
10645 LPFC_NVMET_RQE_DEF_COUNT,
10646 cpu);
2d7dbc4c 10647 if (!qdesc) {
372c187b 10648 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
10649 "3146 Failed allocate "
10650 "receive HRQ\n");
10651 goto out_error;
10652 }
5e5b511d 10653 qdesc->hdwq = idx;
2d7dbc4c
JS
10654 phba->sli4_hba.nvmet_mrq_hdr[idx] = qdesc;
10655
10656 /* Only needed for header of RQ pair */
c1a21ebc
JS
10657 qdesc->rqbp = kzalloc_node(sizeof(*qdesc->rqbp),
10658 GFP_KERNEL,
10659 cpu_to_node(cpu));
2d7dbc4c 10660 if (qdesc->rqbp == NULL) {
372c187b 10661 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
10662 "6131 Failed allocate "
10663 "Header RQBP\n");
10664 goto out_error;
10665 }
10666
4b40d02b
DK
10667 /* Put list in known state in case driver load fails. */
10668 INIT_LIST_HEAD(&qdesc->rqbp->rqb_buffer_list);
10669
2d7dbc4c
JS
10670 /* Create NVMET Receive Queue for data */
10671 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda 10672 LPFC_DEFAULT_PAGE_SIZE,
2d7dbc4c 10673 phba->sli4_hba.rq_esize,
c1a21ebc
JS
10674 LPFC_NVMET_RQE_DEF_COUNT,
10675 cpu);
2d7dbc4c 10676 if (!qdesc) {
372c187b 10677 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
10678 "3156 Failed allocate "
10679 "receive DRQ\n");
10680 goto out_error;
10681 }
5e5b511d 10682 qdesc->hdwq = idx;
2d7dbc4c
JS
10683 phba->sli4_hba.nvmet_mrq_data[idx] = qdesc;
10684 }
10685 }
10686
4c47efc1
JS
10687 /* Clear NVME stats */
10688 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
10689 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
10690 memset(&phba->sli4_hba.hdwq[idx].nvme_cstat, 0,
10691 sizeof(phba->sli4_hba.hdwq[idx].nvme_cstat));
10692 }
10693 }
4c47efc1
JS
10694
10695 /* Clear SCSI stats */
10696 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
10697 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
10698 memset(&phba->sli4_hba.hdwq[idx].scsi_cstat, 0,
10699 sizeof(phba->sli4_hba.hdwq[idx].scsi_cstat));
10700 }
10701 }
10702
da0436e9
JS
10703 return 0;
10704
da0436e9 10705out_error:
67d12733 10706 lpfc_sli4_queue_destroy(phba);
da0436e9
JS
10707 return -ENOMEM;
10708}
10709
895427bd
JS
10710static inline void
10711__lpfc_sli4_release_queue(struct lpfc_queue **qp)
10712{
10713 if (*qp != NULL) {
10714 lpfc_sli4_queue_free(*qp);
10715 *qp = NULL;
10716 }
10717}
10718
10719static inline void
10720lpfc_sli4_release_queues(struct lpfc_queue ***qs, int max)
10721{
10722 int idx;
10723
10724 if (*qs == NULL)
10725 return;
10726
10727 for (idx = 0; idx < max; idx++)
10728 __lpfc_sli4_release_queue(&(*qs)[idx]);
10729
10730 kfree(*qs);
10731 *qs = NULL;
10732}
10733
10734static inline void
6a828b0f 10735lpfc_sli4_release_hdwq(struct lpfc_hba *phba)
895427bd 10736{
6a828b0f 10737 struct lpfc_sli4_hdw_queue *hdwq;
657add4e 10738 struct lpfc_queue *eq;
cdb42bec
JS
10739 uint32_t idx;
10740
6a828b0f 10741 hdwq = phba->sli4_hba.hdwq;
6a828b0f 10742
657add4e
JS
10743 /* Loop thru all Hardware Queues */
10744 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
10745 /* Free the CQ/WQ corresponding to the Hardware Queue */
c00f62e6
JS
10746 lpfc_sli4_queue_free(hdwq[idx].io_cq);
10747 lpfc_sli4_queue_free(hdwq[idx].io_wq);
821bc882 10748 hdwq[idx].hba_eq = NULL;
c00f62e6
JS
10749 hdwq[idx].io_cq = NULL;
10750 hdwq[idx].io_wq = NULL;
d79c9e9d
JS
10751 if (phba->cfg_xpsgl && !phba->nvmet_support)
10752 lpfc_free_sgl_per_hdwq(phba, &hdwq[idx]);
10753 lpfc_free_cmd_rsp_buf_per_hdwq(phba, &hdwq[idx]);
895427bd 10754 }
657add4e
JS
10755 /* Loop thru all IRQ vectors */
10756 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
10757 /* Free the EQ corresponding to the IRQ vector */
10758 eq = phba->sli4_hba.hba_eq_hdl[idx].eq;
10759 lpfc_sli4_queue_free(eq);
10760 phba->sli4_hba.hba_eq_hdl[idx].eq = NULL;
10761 }
895427bd
JS
10762}
10763
da0436e9
JS
10764/**
10765 * lpfc_sli4_queue_destroy - Destroy all the SLI4 queues
10766 * @phba: pointer to lpfc hba data structure.
10767 *
10768 * This routine is invoked to release all the SLI4 queues with the FCoE HBA
10769 * operation.
10770 *
10771 * Return codes
af901ca1 10772 * 0 - successful
25985edc 10773 * -ENOMEM - No available memory
d439d286 10774 * -EIO - The mailbox failed to complete successfully.
da0436e9 10775 **/
5350d872 10776void
da0436e9
JS
10777lpfc_sli4_queue_destroy(struct lpfc_hba *phba)
10778{
4645f7b5
JS
10779 /*
10780 * Set FREE_INIT before beginning to free the queues.
10781 * Wait until the users of queues to acknowledge to
10782 * release queues by clearing FREE_WAIT.
10783 */
10784 spin_lock_irq(&phba->hbalock);
10785 phba->sli.sli_flag |= LPFC_QUEUE_FREE_INIT;
10786 while (phba->sli.sli_flag & LPFC_QUEUE_FREE_WAIT) {
10787 spin_unlock_irq(&phba->hbalock);
10788 msleep(20);
10789 spin_lock_irq(&phba->hbalock);
10790 }
10791 spin_unlock_irq(&phba->hbalock);
10792
93a4d6f4
JS
10793 lpfc_sli4_cleanup_poll_list(phba);
10794
895427bd 10795 /* Release HBA eqs */
cdb42bec 10796 if (phba->sli4_hba.hdwq)
6a828b0f 10797 lpfc_sli4_release_hdwq(phba);
895427bd 10798
bcb24f65
JS
10799 if (phba->nvmet_support) {
10800 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_cqset,
10801 phba->cfg_nvmet_mrq);
2d7dbc4c 10802
bcb24f65
JS
10803 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_hdr,
10804 phba->cfg_nvmet_mrq);
10805 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_data,
10806 phba->cfg_nvmet_mrq);
10807 }
2d7dbc4c 10808
895427bd
JS
10809 /* Release mailbox command work queue */
10810 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_wq);
10811
10812 /* Release ELS work queue */
10813 __lpfc_sli4_release_queue(&phba->sli4_hba.els_wq);
10814
10815 /* Release ELS work queue */
10816 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_wq);
10817
10818 /* Release unsolicited receive queue */
10819 __lpfc_sli4_release_queue(&phba->sli4_hba.hdr_rq);
10820 __lpfc_sli4_release_queue(&phba->sli4_hba.dat_rq);
10821
10822 /* Release ELS complete queue */
10823 __lpfc_sli4_release_queue(&phba->sli4_hba.els_cq);
10824
10825 /* Release NVME LS complete queue */
10826 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_cq);
10827
10828 /* Release mailbox command complete queue */
10829 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_cq);
10830
10831 /* Everything on this list has been freed */
10832 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
4645f7b5
JS
10833
10834 /* Done with freeing the queues */
10835 spin_lock_irq(&phba->hbalock);
10836 phba->sli.sli_flag &= ~LPFC_QUEUE_FREE_INIT;
10837 spin_unlock_irq(&phba->hbalock);
895427bd
JS
10838}
10839
895427bd
JS
10840int
10841lpfc_free_rq_buffer(struct lpfc_hba *phba, struct lpfc_queue *rq)
10842{
10843 struct lpfc_rqb *rqbp;
10844 struct lpfc_dmabuf *h_buf;
10845 struct rqb_dmabuf *rqb_buffer;
10846
10847 rqbp = rq->rqbp;
10848 while (!list_empty(&rqbp->rqb_buffer_list)) {
10849 list_remove_head(&rqbp->rqb_buffer_list, h_buf,
10850 struct lpfc_dmabuf, list);
10851
10852 rqb_buffer = container_of(h_buf, struct rqb_dmabuf, hbuf);
10853 (rqbp->rqb_free_buffer)(phba, rqb_buffer);
10854 rqbp->buffer_count--;
67d12733 10855 }
895427bd
JS
10856 return 1;
10857}
67d12733 10858
895427bd
JS
10859static int
10860lpfc_create_wq_cq(struct lpfc_hba *phba, struct lpfc_queue *eq,
10861 struct lpfc_queue *cq, struct lpfc_queue *wq, uint16_t *cq_map,
10862 int qidx, uint32_t qtype)
10863{
10864 struct lpfc_sli_ring *pring;
10865 int rc;
10866
10867 if (!eq || !cq || !wq) {
372c187b 10868 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
10869 "6085 Fast-path %s (%d) not allocated\n",
10870 ((eq) ? ((cq) ? "WQ" : "CQ") : "EQ"), qidx);
10871 return -ENOMEM;
10872 }
10873
10874 /* create the Cq first */
10875 rc = lpfc_cq_create(phba, cq, eq,
10876 (qtype == LPFC_MBOX) ? LPFC_MCQ : LPFC_WCQ, qtype);
10877 if (rc) {
372c187b
DK
10878 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
10879 "6086 Failed setup of CQ (%d), rc = 0x%x\n",
10880 qidx, (uint32_t)rc);
895427bd 10881 return rc;
67d12733
JS
10882 }
10883
895427bd 10884 if (qtype != LPFC_MBOX) {
cdb42bec 10885 /* Setup cq_map for fast lookup */
895427bd
JS
10886 if (cq_map)
10887 *cq_map = cq->queue_id;
da0436e9 10888
895427bd
JS
10889 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10890 "6087 CQ setup: cq[%d]-id=%d, parent eq[%d]-id=%d\n",
10891 qidx, cq->queue_id, qidx, eq->queue_id);
da0436e9 10892
895427bd
JS
10893 /* create the wq */
10894 rc = lpfc_wq_create(phba, wq, cq, qtype);
10895 if (rc) {
372c187b 10896 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
c835c085 10897 "4618 Fail setup fastpath WQ (%d), rc = 0x%x\n",
895427bd
JS
10898 qidx, (uint32_t)rc);
10899 /* no need to tear down cq - caller will do so */
10900 return rc;
10901 }
da0436e9 10902
895427bd
JS
10903 /* Bind this CQ/WQ to the NVME ring */
10904 pring = wq->pring;
10905 pring->sli.sli4.wqp = (void *)wq;
10906 cq->pring = pring;
da0436e9 10907
895427bd
JS
10908 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10909 "2593 WQ setup: wq[%d]-id=%d assoc=%d, cq[%d]-id=%d\n",
10910 qidx, wq->queue_id, wq->assoc_qid, qidx, cq->queue_id);
10911 } else {
10912 rc = lpfc_mq_create(phba, wq, cq, LPFC_MBOX);
10913 if (rc) {
372c187b
DK
10914 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
10915 "0539 Failed setup of slow-path MQ: "
10916 "rc = 0x%x\n", rc);
895427bd
JS
10917 /* no need to tear down cq - caller will do so */
10918 return rc;
10919 }
da0436e9 10920
895427bd
JS
10921 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10922 "2589 MBX MQ setup: wq-id=%d, parent cq-id=%d\n",
10923 phba->sli4_hba.mbx_wq->queue_id,
10924 phba->sli4_hba.mbx_cq->queue_id);
67d12733 10925 }
da0436e9 10926
895427bd 10927 return 0;
da0436e9
JS
10928}
10929
6a828b0f
JS
10930/**
10931 * lpfc_setup_cq_lookup - Setup the CQ lookup table
10932 * @phba: pointer to lpfc hba data structure.
10933 *
10934 * This routine will populate the cq_lookup table by all
10935 * available CQ queue_id's.
10936 **/
3999df75 10937static void
6a828b0f
JS
10938lpfc_setup_cq_lookup(struct lpfc_hba *phba)
10939{
10940 struct lpfc_queue *eq, *childq;
6a828b0f
JS
10941 int qidx;
10942
6a828b0f
JS
10943 memset(phba->sli4_hba.cq_lookup, 0,
10944 (sizeof(struct lpfc_queue *) * (phba->sli4_hba.cq_max + 1)));
657add4e 10945 /* Loop thru all IRQ vectors */
6a828b0f 10946 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
657add4e
JS
10947 /* Get the EQ corresponding to the IRQ vector */
10948 eq = phba->sli4_hba.hba_eq_hdl[qidx].eq;
6a828b0f
JS
10949 if (!eq)
10950 continue;
657add4e 10951 /* Loop through all CQs associated with that EQ */
6a828b0f
JS
10952 list_for_each_entry(childq, &eq->child_list, list) {
10953 if (childq->queue_id > phba->sli4_hba.cq_max)
10954 continue;
c00f62e6 10955 if (childq->subtype == LPFC_IO)
6a828b0f
JS
10956 phba->sli4_hba.cq_lookup[childq->queue_id] =
10957 childq;
10958 }
10959 }
10960}
10961
da0436e9
JS
10962/**
10963 * lpfc_sli4_queue_setup - Set up all the SLI4 queues
10964 * @phba: pointer to lpfc hba data structure.
10965 *
10966 * This routine is invoked to set up all the SLI4 queues for the FCoE HBA
10967 * operation.
10968 *
10969 * Return codes
af901ca1 10970 * 0 - successful
25985edc 10971 * -ENOMEM - No available memory
d439d286 10972 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
10973 **/
10974int
10975lpfc_sli4_queue_setup(struct lpfc_hba *phba)
10976{
962bc51b
JS
10977 uint32_t shdr_status, shdr_add_status;
10978 union lpfc_sli4_cfg_shdr *shdr;
657add4e 10979 struct lpfc_vector_map_info *cpup;
cdb42bec 10980 struct lpfc_sli4_hdw_queue *qp;
962bc51b 10981 LPFC_MBOXQ_t *mboxq;
657add4e 10982 int qidx, cpu;
cb733e35 10983 uint32_t length, usdelay;
895427bd 10984 int rc = -ENOMEM;
962bc51b
JS
10985
10986 /* Check for dual-ULP support */
10987 mboxq = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
10988 if (!mboxq) {
372c187b 10989 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
962bc51b
JS
10990 "3249 Unable to allocate memory for "
10991 "QUERY_FW_CFG mailbox command\n");
10992 return -ENOMEM;
10993 }
10994 length = (sizeof(struct lpfc_mbx_query_fw_config) -
10995 sizeof(struct lpfc_sli4_cfg_mhdr));
10996 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
10997 LPFC_MBOX_OPCODE_QUERY_FW_CFG,
10998 length, LPFC_SLI4_MBX_EMBED);
10999
11000 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
11001
11002 shdr = (union lpfc_sli4_cfg_shdr *)
11003 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
11004 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
11005 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
11006 if (shdr_status || shdr_add_status || rc) {
372c187b 11007 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
962bc51b
JS
11008 "3250 QUERY_FW_CFG mailbox failed with status "
11009 "x%x add_status x%x, mbx status x%x\n",
11010 shdr_status, shdr_add_status, rc);
304ee432 11011 mempool_free(mboxq, phba->mbox_mem_pool);
962bc51b
JS
11012 rc = -ENXIO;
11013 goto out_error;
11014 }
11015
11016 phba->sli4_hba.fw_func_mode =
11017 mboxq->u.mqe.un.query_fw_cfg.rsp.function_mode;
11018 phba->sli4_hba.ulp0_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp0_mode;
11019 phba->sli4_hba.ulp1_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp1_mode;
8b017a30
JS
11020 phba->sli4_hba.physical_port =
11021 mboxq->u.mqe.un.query_fw_cfg.rsp.physical_port;
962bc51b
JS
11022 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11023 "3251 QUERY_FW_CFG: func_mode:x%x, ulp0_mode:x%x, "
11024 "ulp1_mode:x%x\n", phba->sli4_hba.fw_func_mode,
11025 phba->sli4_hba.ulp0_mode, phba->sli4_hba.ulp1_mode);
11026
304ee432 11027 mempool_free(mboxq, phba->mbox_mem_pool);
da0436e9
JS
11028
11029 /*
67d12733 11030 * Set up HBA Event Queues (EQs)
da0436e9 11031 */
cdb42bec 11032 qp = phba->sli4_hba.hdwq;
da0436e9 11033
67d12733 11034 /* Set up HBA event queue */
cdb42bec 11035 if (!qp) {
372c187b 11036 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2e90f4b5 11037 "3147 Fast-path EQs not allocated\n");
1b51197d 11038 rc = -ENOMEM;
67d12733 11039 goto out_error;
2e90f4b5 11040 }
657add4e
JS
11041
11042 /* Loop thru all IRQ vectors */
6a828b0f 11043 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
657add4e
JS
11044 /* Create HBA Event Queues (EQs) in order */
11045 for_each_present_cpu(cpu) {
11046 cpup = &phba->sli4_hba.cpu_map[cpu];
11047
11048 /* Look for the CPU thats using that vector with
11049 * LPFC_CPU_FIRST_IRQ set.
11050 */
11051 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
11052 continue;
11053 if (qidx != cpup->eq)
11054 continue;
11055
11056 /* Create an EQ for that vector */
11057 rc = lpfc_eq_create(phba, qp[cpup->hdwq].hba_eq,
11058 phba->cfg_fcp_imax);
11059 if (rc) {
372c187b 11060 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
657add4e
JS
11061 "0523 Failed setup of fast-path"
11062 " EQ (%d), rc = 0x%x\n",
11063 cpup->eq, (uint32_t)rc);
11064 goto out_destroy;
11065 }
11066
11067 /* Save the EQ for that vector in the hba_eq_hdl */
11068 phba->sli4_hba.hba_eq_hdl[cpup->eq].eq =
11069 qp[cpup->hdwq].hba_eq;
11070
11071 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11072 "2584 HBA EQ setup: queue[%d]-id=%d\n",
11073 cpup->eq,
11074 qp[cpup->hdwq].hba_eq->queue_id);
da0436e9 11075 }
67d12733
JS
11076 }
11077
657add4e 11078 /* Loop thru all Hardware Queues */
cdb42bec 11079 for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {
657add4e
JS
11080 cpu = lpfc_find_cpu_handle(phba, qidx, LPFC_FIND_BY_HDWQ);
11081 cpup = &phba->sli4_hba.cpu_map[cpu];
11082
11083 /* Create the CQ/WQ corresponding to the Hardware Queue */
cdb42bec 11084 rc = lpfc_create_wq_cq(phba,
657add4e 11085 phba->sli4_hba.hdwq[cpup->hdwq].hba_eq,
c00f62e6
JS
11086 qp[qidx].io_cq,
11087 qp[qidx].io_wq,
11088 &phba->sli4_hba.hdwq[qidx].io_cq_map,
11089 qidx,
11090 LPFC_IO);
cdb42bec 11091 if (rc) {
372c187b 11092 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd 11093 "0535 Failed to setup fastpath "
c00f62e6 11094 "IO WQ/CQ (%d), rc = 0x%x\n",
895427bd 11095 qidx, (uint32_t)rc);
cdb42bec 11096 goto out_destroy;
895427bd 11097 }
67d12733 11098 }
895427bd 11099
da0436e9 11100 /*
895427bd 11101 * Set up Slow Path Complete Queues (CQs)
da0436e9
JS
11102 */
11103
895427bd 11104 /* Set up slow-path MBOX CQ/MQ */
da0436e9 11105
895427bd 11106 if (!phba->sli4_hba.mbx_cq || !phba->sli4_hba.mbx_wq) {
372c187b 11107 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
11108 "0528 %s not allocated\n",
11109 phba->sli4_hba.mbx_cq ?
d1f525aa 11110 "Mailbox WQ" : "Mailbox CQ");
1b51197d 11111 rc = -ENOMEM;
895427bd 11112 goto out_destroy;
da0436e9 11113 }
da0436e9 11114
cdb42bec 11115 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
d1f525aa
JS
11116 phba->sli4_hba.mbx_cq,
11117 phba->sli4_hba.mbx_wq,
11118 NULL, 0, LPFC_MBOX);
da0436e9 11119 if (rc) {
372c187b 11120 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
11121 "0529 Failed setup of mailbox WQ/CQ: rc = 0x%x\n",
11122 (uint32_t)rc);
11123 goto out_destroy;
da0436e9 11124 }
2d7dbc4c
JS
11125 if (phba->nvmet_support) {
11126 if (!phba->sli4_hba.nvmet_cqset) {
372c187b 11127 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
11128 "3165 Fast-path NVME CQ Set "
11129 "array not allocated\n");
11130 rc = -ENOMEM;
11131 goto out_destroy;
11132 }
11133 if (phba->cfg_nvmet_mrq > 1) {
11134 rc = lpfc_cq_create_set(phba,
11135 phba->sli4_hba.nvmet_cqset,
cdb42bec 11136 qp,
2d7dbc4c
JS
11137 LPFC_WCQ, LPFC_NVMET);
11138 if (rc) {
372c187b 11139 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
11140 "3164 Failed setup of NVME CQ "
11141 "Set, rc = 0x%x\n",
11142 (uint32_t)rc);
11143 goto out_destroy;
11144 }
11145 } else {
11146 /* Set up NVMET Receive Complete Queue */
11147 rc = lpfc_cq_create(phba, phba->sli4_hba.nvmet_cqset[0],
cdb42bec 11148 qp[0].hba_eq,
2d7dbc4c
JS
11149 LPFC_WCQ, LPFC_NVMET);
11150 if (rc) {
372c187b 11151 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
11152 "6089 Failed setup NVMET CQ: "
11153 "rc = 0x%x\n", (uint32_t)rc);
11154 goto out_destroy;
11155 }
81b96eda
JS
11156 phba->sli4_hba.nvmet_cqset[0]->chann = 0;
11157
2d7dbc4c
JS
11158 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11159 "6090 NVMET CQ setup: cq-id=%d, "
11160 "parent eq-id=%d\n",
11161 phba->sli4_hba.nvmet_cqset[0]->queue_id,
cdb42bec 11162 qp[0].hba_eq->queue_id);
2d7dbc4c
JS
11163 }
11164 }
da0436e9 11165
895427bd
JS
11166 /* Set up slow-path ELS WQ/CQ */
11167 if (!phba->sli4_hba.els_cq || !phba->sli4_hba.els_wq) {
372c187b 11168 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
11169 "0530 ELS %s not allocated\n",
11170 phba->sli4_hba.els_cq ? "WQ" : "CQ");
1b51197d 11171 rc = -ENOMEM;
895427bd 11172 goto out_destroy;
da0436e9 11173 }
cdb42bec
JS
11174 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
11175 phba->sli4_hba.els_cq,
11176 phba->sli4_hba.els_wq,
11177 NULL, 0, LPFC_ELS);
da0436e9 11178 if (rc) {
372c187b 11179 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
cdb42bec
JS
11180 "0525 Failed setup of ELS WQ/CQ: rc = 0x%x\n",
11181 (uint32_t)rc);
895427bd 11182 goto out_destroy;
da0436e9
JS
11183 }
11184 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11185 "2590 ELS WQ setup: wq-id=%d, parent cq-id=%d\n",
11186 phba->sli4_hba.els_wq->queue_id,
11187 phba->sli4_hba.els_cq->queue_id);
11188
cdb42bec 11189 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
895427bd
JS
11190 /* Set up NVME LS Complete Queue */
11191 if (!phba->sli4_hba.nvmels_cq || !phba->sli4_hba.nvmels_wq) {
372c187b 11192 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
11193 "6091 LS %s not allocated\n",
11194 phba->sli4_hba.nvmels_cq ? "WQ" : "CQ");
11195 rc = -ENOMEM;
11196 goto out_destroy;
11197 }
cdb42bec
JS
11198 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
11199 phba->sli4_hba.nvmels_cq,
11200 phba->sli4_hba.nvmels_wq,
11201 NULL, 0, LPFC_NVME_LS);
895427bd 11202 if (rc) {
372c187b 11203 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
cdb42bec
JS
11204 "0526 Failed setup of NVVME LS WQ/CQ: "
11205 "rc = 0x%x\n", (uint32_t)rc);
895427bd
JS
11206 goto out_destroy;
11207 }
11208
11209 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11210 "6096 ELS WQ setup: wq-id=%d, "
11211 "parent cq-id=%d\n",
11212 phba->sli4_hba.nvmels_wq->queue_id,
11213 phba->sli4_hba.nvmels_cq->queue_id);
11214 }
11215
2d7dbc4c
JS
11216 /*
11217 * Create NVMET Receive Queue (RQ)
11218 */
11219 if (phba->nvmet_support) {
11220 if ((!phba->sli4_hba.nvmet_cqset) ||
11221 (!phba->sli4_hba.nvmet_mrq_hdr) ||
11222 (!phba->sli4_hba.nvmet_mrq_data)) {
372c187b 11223 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
11224 "6130 MRQ CQ Queues not "
11225 "allocated\n");
11226 rc = -ENOMEM;
11227 goto out_destroy;
11228 }
11229 if (phba->cfg_nvmet_mrq > 1) {
11230 rc = lpfc_mrq_create(phba,
11231 phba->sli4_hba.nvmet_mrq_hdr,
11232 phba->sli4_hba.nvmet_mrq_data,
11233 phba->sli4_hba.nvmet_cqset,
11234 LPFC_NVMET);
11235 if (rc) {
372c187b 11236 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
11237 "6098 Failed setup of NVMET "
11238 "MRQ: rc = 0x%x\n",
11239 (uint32_t)rc);
11240 goto out_destroy;
11241 }
11242
11243 } else {
11244 rc = lpfc_rq_create(phba,
11245 phba->sli4_hba.nvmet_mrq_hdr[0],
11246 phba->sli4_hba.nvmet_mrq_data[0],
11247 phba->sli4_hba.nvmet_cqset[0],
11248 LPFC_NVMET);
11249 if (rc) {
372c187b 11250 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
11251 "6057 Failed setup of NVMET "
11252 "Receive Queue: rc = 0x%x\n",
11253 (uint32_t)rc);
11254 goto out_destroy;
11255 }
11256
11257 lpfc_printf_log(
11258 phba, KERN_INFO, LOG_INIT,
11259 "6099 NVMET RQ setup: hdr-rq-id=%d, "
11260 "dat-rq-id=%d parent cq-id=%d\n",
11261 phba->sli4_hba.nvmet_mrq_hdr[0]->queue_id,
11262 phba->sli4_hba.nvmet_mrq_data[0]->queue_id,
11263 phba->sli4_hba.nvmet_cqset[0]->queue_id);
11264
11265 }
11266 }
11267
da0436e9 11268 if (!phba->sli4_hba.hdr_rq || !phba->sli4_hba.dat_rq) {
372c187b 11269 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 11270 "0540 Receive Queue not allocated\n");
1b51197d 11271 rc = -ENOMEM;
895427bd 11272 goto out_destroy;
da0436e9 11273 }
73d91e50 11274
da0436e9 11275 rc = lpfc_rq_create(phba, phba->sli4_hba.hdr_rq, phba->sli4_hba.dat_rq,
4d9ab994 11276 phba->sli4_hba.els_cq, LPFC_USOL);
da0436e9 11277 if (rc) {
372c187b 11278 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 11279 "0541 Failed setup of Receive Queue: "
a2fc4aef 11280 "rc = 0x%x\n", (uint32_t)rc);
895427bd 11281 goto out_destroy;
da0436e9 11282 }
73d91e50 11283
da0436e9
JS
11284 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11285 "2592 USL RQ setup: hdr-rq-id=%d, dat-rq-id=%d "
11286 "parent cq-id=%d\n",
11287 phba->sli4_hba.hdr_rq->queue_id,
11288 phba->sli4_hba.dat_rq->queue_id,
4d9ab994 11289 phba->sli4_hba.els_cq->queue_id);
1ba981fd 11290
cb733e35
JS
11291 if (phba->cfg_fcp_imax)
11292 usdelay = LPFC_SEC_TO_USEC / phba->cfg_fcp_imax;
11293 else
11294 usdelay = 0;
11295
6a828b0f 11296 for (qidx = 0; qidx < phba->cfg_irq_chann;
cdb42bec 11297 qidx += LPFC_MAX_EQ_DELAY_EQID_CNT)
0cf07f84 11298 lpfc_modify_hba_eq_delay(phba, qidx, LPFC_MAX_EQ_DELAY_EQID_CNT,
cb733e35 11299 usdelay);
43140ca6 11300
6a828b0f
JS
11301 if (phba->sli4_hba.cq_max) {
11302 kfree(phba->sli4_hba.cq_lookup);
11303 phba->sli4_hba.cq_lookup = kcalloc((phba->sli4_hba.cq_max + 1),
11304 sizeof(struct lpfc_queue *), GFP_KERNEL);
11305 if (!phba->sli4_hba.cq_lookup) {
372c187b 11306 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
6a828b0f
JS
11307 "0549 Failed setup of CQ Lookup table: "
11308 "size 0x%x\n", phba->sli4_hba.cq_max);
fad28e3d 11309 rc = -ENOMEM;
895427bd 11310 goto out_destroy;
1ba981fd 11311 }
6a828b0f 11312 lpfc_setup_cq_lookup(phba);
1ba981fd 11313 }
da0436e9
JS
11314 return 0;
11315
895427bd
JS
11316out_destroy:
11317 lpfc_sli4_queue_unset(phba);
da0436e9
JS
11318out_error:
11319 return rc;
11320}
11321
11322/**
11323 * lpfc_sli4_queue_unset - Unset all the SLI4 queues
11324 * @phba: pointer to lpfc hba data structure.
11325 *
11326 * This routine is invoked to unset all the SLI4 queues with the FCoE HBA
11327 * operation.
11328 *
11329 * Return codes
af901ca1 11330 * 0 - successful
25985edc 11331 * -ENOMEM - No available memory
d439d286 11332 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
11333 **/
11334void
11335lpfc_sli4_queue_unset(struct lpfc_hba *phba)
11336{
cdb42bec 11337 struct lpfc_sli4_hdw_queue *qp;
657add4e 11338 struct lpfc_queue *eq;
895427bd 11339 int qidx;
da0436e9
JS
11340
11341 /* Unset mailbox command work queue */
895427bd
JS
11342 if (phba->sli4_hba.mbx_wq)
11343 lpfc_mq_destroy(phba, phba->sli4_hba.mbx_wq);
11344
11345 /* Unset NVME LS work queue */
11346 if (phba->sli4_hba.nvmels_wq)
11347 lpfc_wq_destroy(phba, phba->sli4_hba.nvmels_wq);
11348
da0436e9 11349 /* Unset ELS work queue */
019c0d66 11350 if (phba->sli4_hba.els_wq)
895427bd
JS
11351 lpfc_wq_destroy(phba, phba->sli4_hba.els_wq);
11352
da0436e9 11353 /* Unset unsolicited receive queue */
895427bd
JS
11354 if (phba->sli4_hba.hdr_rq)
11355 lpfc_rq_destroy(phba, phba->sli4_hba.hdr_rq,
11356 phba->sli4_hba.dat_rq);
11357
da0436e9 11358 /* Unset mailbox command complete queue */
895427bd
JS
11359 if (phba->sli4_hba.mbx_cq)
11360 lpfc_cq_destroy(phba, phba->sli4_hba.mbx_cq);
11361
da0436e9 11362 /* Unset ELS complete queue */
895427bd
JS
11363 if (phba->sli4_hba.els_cq)
11364 lpfc_cq_destroy(phba, phba->sli4_hba.els_cq);
11365
11366 /* Unset NVME LS complete queue */
11367 if (phba->sli4_hba.nvmels_cq)
11368 lpfc_cq_destroy(phba, phba->sli4_hba.nvmels_cq);
11369
bcb24f65
JS
11370 if (phba->nvmet_support) {
11371 /* Unset NVMET MRQ queue */
11372 if (phba->sli4_hba.nvmet_mrq_hdr) {
11373 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
11374 lpfc_rq_destroy(
11375 phba,
2d7dbc4c
JS
11376 phba->sli4_hba.nvmet_mrq_hdr[qidx],
11377 phba->sli4_hba.nvmet_mrq_data[qidx]);
bcb24f65 11378 }
2d7dbc4c 11379
bcb24f65
JS
11380 /* Unset NVMET CQ Set complete queue */
11381 if (phba->sli4_hba.nvmet_cqset) {
11382 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
11383 lpfc_cq_destroy(
11384 phba, phba->sli4_hba.nvmet_cqset[qidx]);
11385 }
2d7dbc4c
JS
11386 }
11387
cdb42bec
JS
11388 /* Unset fast-path SLI4 queues */
11389 if (phba->sli4_hba.hdwq) {
657add4e 11390 /* Loop thru all Hardware Queues */
cdb42bec 11391 for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {
657add4e 11392 /* Destroy the CQ/WQ corresponding to Hardware Queue */
cdb42bec 11393 qp = &phba->sli4_hba.hdwq[qidx];
c00f62e6
JS
11394 lpfc_wq_destroy(phba, qp->io_wq);
11395 lpfc_cq_destroy(phba, qp->io_cq);
657add4e
JS
11396 }
11397 /* Loop thru all IRQ vectors */
11398 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
11399 /* Destroy the EQ corresponding to the IRQ vector */
11400 eq = phba->sli4_hba.hba_eq_hdl[qidx].eq;
11401 lpfc_eq_destroy(phba, eq);
cdb42bec
JS
11402 }
11403 }
895427bd 11404
6a828b0f
JS
11405 kfree(phba->sli4_hba.cq_lookup);
11406 phba->sli4_hba.cq_lookup = NULL;
11407 phba->sli4_hba.cq_max = 0;
da0436e9
JS
11408}
11409
11410/**
11411 * lpfc_sli4_cq_event_pool_create - Create completion-queue event free pool
11412 * @phba: pointer to lpfc hba data structure.
11413 *
11414 * This routine is invoked to allocate and set up a pool of completion queue
11415 * events. The body of the completion queue event is a completion queue entry
11416 * CQE. For now, this pool is used for the interrupt service routine to queue
11417 * the following HBA completion queue events for the worker thread to process:
11418 * - Mailbox asynchronous events
11419 * - Receive queue completion unsolicited events
11420 * Later, this can be used for all the slow-path events.
11421 *
11422 * Return codes
af901ca1 11423 * 0 - successful
25985edc 11424 * -ENOMEM - No available memory
da0436e9
JS
11425 **/
11426static int
11427lpfc_sli4_cq_event_pool_create(struct lpfc_hba *phba)
11428{
11429 struct lpfc_cq_event *cq_event;
11430 int i;
11431
11432 for (i = 0; i < (4 * phba->sli4_hba.cq_ecount); i++) {
11433 cq_event = kmalloc(sizeof(struct lpfc_cq_event), GFP_KERNEL);
11434 if (!cq_event)
11435 goto out_pool_create_fail;
11436 list_add_tail(&cq_event->list,
11437 &phba->sli4_hba.sp_cqe_event_pool);
11438 }
11439 return 0;
11440
11441out_pool_create_fail:
11442 lpfc_sli4_cq_event_pool_destroy(phba);
11443 return -ENOMEM;
11444}
11445
11446/**
11447 * lpfc_sli4_cq_event_pool_destroy - Free completion-queue event free pool
11448 * @phba: pointer to lpfc hba data structure.
11449 *
11450 * This routine is invoked to free the pool of completion queue events at
11451 * driver unload time. Note that, it is the responsibility of the driver
11452 * cleanup routine to free all the outstanding completion-queue events
11453 * allocated from this pool back into the pool before invoking this routine
11454 * to destroy the pool.
11455 **/
11456static void
11457lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *phba)
11458{
11459 struct lpfc_cq_event *cq_event, *next_cq_event;
11460
11461 list_for_each_entry_safe(cq_event, next_cq_event,
11462 &phba->sli4_hba.sp_cqe_event_pool, list) {
11463 list_del(&cq_event->list);
11464 kfree(cq_event);
11465 }
11466}
11467
11468/**
11469 * __lpfc_sli4_cq_event_alloc - Allocate a completion-queue event from free pool
11470 * @phba: pointer to lpfc hba data structure.
11471 *
11472 * This routine is the lock free version of the API invoked to allocate a
11473 * completion-queue event from the free pool.
11474 *
11475 * Return: Pointer to the newly allocated completion-queue event if successful
11476 * NULL otherwise.
11477 **/
11478struct lpfc_cq_event *
11479__lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
11480{
11481 struct lpfc_cq_event *cq_event = NULL;
11482
11483 list_remove_head(&phba->sli4_hba.sp_cqe_event_pool, cq_event,
11484 struct lpfc_cq_event, list);
11485 return cq_event;
11486}
11487
11488/**
11489 * lpfc_sli4_cq_event_alloc - Allocate a completion-queue event from free pool
11490 * @phba: pointer to lpfc hba data structure.
11491 *
11492 * This routine is the lock version of the API invoked to allocate a
11493 * completion-queue event from the free pool.
11494 *
11495 * Return: Pointer to the newly allocated completion-queue event if successful
11496 * NULL otherwise.
11497 **/
11498struct lpfc_cq_event *
11499lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
11500{
11501 struct lpfc_cq_event *cq_event;
11502 unsigned long iflags;
11503
11504 spin_lock_irqsave(&phba->hbalock, iflags);
11505 cq_event = __lpfc_sli4_cq_event_alloc(phba);
11506 spin_unlock_irqrestore(&phba->hbalock, iflags);
11507 return cq_event;
11508}
11509
11510/**
11511 * __lpfc_sli4_cq_event_release - Release a completion-queue event to free pool
11512 * @phba: pointer to lpfc hba data structure.
11513 * @cq_event: pointer to the completion queue event to be freed.
11514 *
11515 * This routine is the lock free version of the API invoked to release a
11516 * completion-queue event back into the free pool.
11517 **/
11518void
11519__lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
11520 struct lpfc_cq_event *cq_event)
11521{
11522 list_add_tail(&cq_event->list, &phba->sli4_hba.sp_cqe_event_pool);
11523}
11524
11525/**
11526 * lpfc_sli4_cq_event_release - Release a completion-queue event to free pool
11527 * @phba: pointer to lpfc hba data structure.
11528 * @cq_event: pointer to the completion queue event to be freed.
11529 *
11530 * This routine is the lock version of the API invoked to release a
11531 * completion-queue event back into the free pool.
11532 **/
11533void
11534lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
11535 struct lpfc_cq_event *cq_event)
11536{
11537 unsigned long iflags;
11538 spin_lock_irqsave(&phba->hbalock, iflags);
11539 __lpfc_sli4_cq_event_release(phba, cq_event);
11540 spin_unlock_irqrestore(&phba->hbalock, iflags);
11541}
11542
11543/**
11544 * lpfc_sli4_cq_event_release_all - Release all cq events to the free pool
11545 * @phba: pointer to lpfc hba data structure.
11546 *
11547 * This routine is to free all the pending completion-queue events to the
11548 * back into the free pool for device reset.
11549 **/
11550static void
11551lpfc_sli4_cq_event_release_all(struct lpfc_hba *phba)
11552{
e7dab164
JS
11553 LIST_HEAD(cq_event_list);
11554 struct lpfc_cq_event *cq_event;
da0436e9
JS
11555 unsigned long iflags;
11556
11557 /* Retrieve all the pending WCQEs from pending WCQE lists */
e7dab164 11558
da0436e9 11559 /* Pending ELS XRI abort events */
e7dab164 11560 spin_lock_irqsave(&phba->sli4_hba.els_xri_abrt_list_lock, iflags);
da0436e9 11561 list_splice_init(&phba->sli4_hba.sp_els_xri_aborted_work_queue,
e7dab164
JS
11562 &cq_event_list);
11563 spin_unlock_irqrestore(&phba->sli4_hba.els_xri_abrt_list_lock, iflags);
11564
da0436e9 11565 /* Pending asynnc events */
e7dab164 11566 spin_lock_irqsave(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9 11567 list_splice_init(&phba->sli4_hba.sp_asynce_work_queue,
e7dab164
JS
11568 &cq_event_list);
11569 spin_unlock_irqrestore(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9 11570
e7dab164
JS
11571 while (!list_empty(&cq_event_list)) {
11572 list_remove_head(&cq_event_list, cq_event,
11573 struct lpfc_cq_event, list);
11574 lpfc_sli4_cq_event_release(phba, cq_event);
da0436e9
JS
11575 }
11576}
11577
11578/**
11579 * lpfc_pci_function_reset - Reset pci function.
11580 * @phba: pointer to lpfc hba data structure.
11581 *
11582 * This routine is invoked to request a PCI function reset. It will destroys
11583 * all resources assigned to the PCI function which originates this request.
11584 *
11585 * Return codes
af901ca1 11586 * 0 - successful
25985edc 11587 * -ENOMEM - No available memory
d439d286 11588 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
11589 **/
11590int
11591lpfc_pci_function_reset(struct lpfc_hba *phba)
11592{
11593 LPFC_MBOXQ_t *mboxq;
2fcee4bf 11594 uint32_t rc = 0, if_type;
da0436e9 11595 uint32_t shdr_status, shdr_add_status;
2f6fa2c9
JS
11596 uint32_t rdy_chk;
11597 uint32_t port_reset = 0;
da0436e9 11598 union lpfc_sli4_cfg_shdr *shdr;
2fcee4bf 11599 struct lpfc_register reg_data;
2b81f942 11600 uint16_t devid;
da0436e9 11601
2fcee4bf
JS
11602 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
11603 switch (if_type) {
11604 case LPFC_SLI_INTF_IF_TYPE_0:
11605 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
11606 GFP_KERNEL);
11607 if (!mboxq) {
372c187b 11608 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
11609 "0494 Unable to allocate memory for "
11610 "issuing SLI_FUNCTION_RESET mailbox "
11611 "command\n");
11612 return -ENOMEM;
11613 }
da0436e9 11614
2fcee4bf
JS
11615 /* Setup PCI function reset mailbox-ioctl command */
11616 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
11617 LPFC_MBOX_OPCODE_FUNCTION_RESET, 0,
11618 LPFC_SLI4_MBX_EMBED);
11619 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
11620 shdr = (union lpfc_sli4_cfg_shdr *)
11621 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
11622 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
11623 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status,
11624 &shdr->response);
304ee432 11625 mempool_free(mboxq, phba->mbox_mem_pool);
2fcee4bf 11626 if (shdr_status || shdr_add_status || rc) {
372c187b 11627 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
11628 "0495 SLI_FUNCTION_RESET mailbox "
11629 "failed with status x%x add_status x%x,"
11630 " mbx status x%x\n",
11631 shdr_status, shdr_add_status, rc);
11632 rc = -ENXIO;
11633 }
11634 break;
11635 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 11636 case LPFC_SLI_INTF_IF_TYPE_6:
2f6fa2c9
JS
11637wait:
11638 /*
11639 * Poll the Port Status Register and wait for RDY for
11640 * up to 30 seconds. If the port doesn't respond, treat
11641 * it as an error.
11642 */
77d093fb 11643 for (rdy_chk = 0; rdy_chk < 1500; rdy_chk++) {
2f6fa2c9
JS
11644 if (lpfc_readl(phba->sli4_hba.u.if_type2.
11645 STATUSregaddr, &reg_data.word0)) {
11646 rc = -ENODEV;
11647 goto out;
11648 }
11649 if (bf_get(lpfc_sliport_status_rdy, &reg_data))
11650 break;
11651 msleep(20);
11652 }
11653
11654 if (!bf_get(lpfc_sliport_status_rdy, &reg_data)) {
11655 phba->work_status[0] = readl(
11656 phba->sli4_hba.u.if_type2.ERR1regaddr);
11657 phba->work_status[1] = readl(
11658 phba->sli4_hba.u.if_type2.ERR2regaddr);
372c187b 11659 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2f6fa2c9
JS
11660 "2890 Port not ready, port status reg "
11661 "0x%x error 1=0x%x, error 2=0x%x\n",
11662 reg_data.word0,
11663 phba->work_status[0],
11664 phba->work_status[1]);
11665 rc = -ENODEV;
11666 goto out;
11667 }
11668
a5b141a8
JS
11669 if (bf_get(lpfc_sliport_status_pldv, &reg_data))
11670 lpfc_pldv_detect = true;
11671
2f6fa2c9
JS
11672 if (!port_reset) {
11673 /*
11674 * Reset the port now
11675 */
2fcee4bf
JS
11676 reg_data.word0 = 0;
11677 bf_set(lpfc_sliport_ctrl_end, &reg_data,
11678 LPFC_SLIPORT_LITTLE_ENDIAN);
11679 bf_set(lpfc_sliport_ctrl_ip, &reg_data,
11680 LPFC_SLIPORT_INIT_PORT);
11681 writel(reg_data.word0, phba->sli4_hba.u.if_type2.
11682 CTRLregaddr);
8fcb8acd 11683 /* flush */
2b81f942
JS
11684 pci_read_config_word(phba->pcidev,
11685 PCI_DEVICE_ID, &devid);
2fcee4bf 11686
2f6fa2c9
JS
11687 port_reset = 1;
11688 msleep(20);
11689 goto wait;
11690 } else if (bf_get(lpfc_sliport_status_rn, &reg_data)) {
11691 rc = -ENODEV;
11692 goto out;
2fcee4bf
JS
11693 }
11694 break;
2f6fa2c9 11695
2fcee4bf
JS
11696 case LPFC_SLI_INTF_IF_TYPE_1:
11697 default:
11698 break;
da0436e9 11699 }
2fcee4bf 11700
73d91e50 11701out:
2fcee4bf 11702 /* Catch the not-ready port failure after a port reset. */
2f6fa2c9 11703 if (rc) {
372c187b 11704 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
229adb0e 11705 "3317 HBA not functional: IP Reset Failed "
2f6fa2c9 11706 "try: echo fw_reset > board_mode\n");
2fcee4bf 11707 rc = -ENODEV;
229adb0e 11708 }
2fcee4bf 11709
da0436e9
JS
11710 return rc;
11711}
11712
da0436e9
JS
11713/**
11714 * lpfc_sli4_pci_mem_setup - Setup SLI4 HBA PCI memory space.
11715 * @phba: pointer to lpfc hba data structure.
11716 *
11717 * This routine is invoked to set up the PCI device memory space for device
11718 * with SLI-4 interface spec.
11719 *
11720 * Return codes
af901ca1 11721 * 0 - successful
da0436e9
JS
11722 * other values - error
11723 **/
11724static int
11725lpfc_sli4_pci_mem_setup(struct lpfc_hba *phba)
11726{
f30e1bfd 11727 struct pci_dev *pdev = phba->pcidev;
da0436e9 11728 unsigned long bar0map_len, bar1map_len, bar2map_len;
3a487ff7 11729 int error;
2fcee4bf 11730 uint32_t if_type;
da0436e9 11731
f30e1bfd 11732 if (!pdev)
56de8357 11733 return -ENODEV;
da0436e9
JS
11734
11735 /* Set the device DMA mask size */
56de8357
HR
11736 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
11737 if (error)
11738 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
11739 if (error)
f30e1bfd 11740 return error;
da0436e9 11741
2fcee4bf
JS
11742 /*
11743 * The BARs and register set definitions and offset locations are
11744 * dependent on the if_type.
11745 */
11746 if (pci_read_config_dword(pdev, LPFC_SLI_INTF,
11747 &phba->sli4_hba.sli_intf.word0)) {
3a487ff7 11748 return -ENODEV;
2fcee4bf
JS
11749 }
11750
11751 /* There is no SLI3 failback for SLI4 devices. */
11752 if (bf_get(lpfc_sli_intf_valid, &phba->sli4_hba.sli_intf) !=
11753 LPFC_SLI_INTF_VALID) {
a516074c 11754 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
2fcee4bf
JS
11755 "2894 SLI_INTF reg contents invalid "
11756 "sli_intf reg 0x%x\n",
11757 phba->sli4_hba.sli_intf.word0);
3a487ff7 11758 return -ENODEV;
2fcee4bf
JS
11759 }
11760
11761 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
11762 /*
11763 * Get the bus address of SLI4 device Bar regions and the
11764 * number of bytes required by each mapping. The mapping of the
11765 * particular PCI BARs regions is dependent on the type of
11766 * SLI4 device.
da0436e9 11767 */
f5ca6f2e
JS
11768 if (pci_resource_start(pdev, PCI_64BIT_BAR0)) {
11769 phba->pci_bar0_map = pci_resource_start(pdev, PCI_64BIT_BAR0);
11770 bar0map_len = pci_resource_len(pdev, PCI_64BIT_BAR0);
2fcee4bf
JS
11771
11772 /*
11773 * Map SLI4 PCI Config Space Register base to a kernel virtual
11774 * addr
11775 */
11776 phba->sli4_hba.conf_regs_memmap_p =
11777 ioremap(phba->pci_bar0_map, bar0map_len);
11778 if (!phba->sli4_hba.conf_regs_memmap_p) {
11779 dev_printk(KERN_ERR, &pdev->dev,
11780 "ioremap failed for SLI4 PCI config "
11781 "registers.\n");
3a487ff7 11782 return -ENODEV;
2fcee4bf 11783 }
f5ca6f2e 11784 phba->pci_bar0_memmap_p = phba->sli4_hba.conf_regs_memmap_p;
2fcee4bf
JS
11785 /* Set up BAR0 PCI config space register memory map */
11786 lpfc_sli4_bar0_register_memmap(phba, if_type);
1dfb5a47
JS
11787 } else {
11788 phba->pci_bar0_map = pci_resource_start(pdev, 1);
11789 bar0map_len = pci_resource_len(pdev, 1);
27d6ac0a 11790 if (if_type >= LPFC_SLI_INTF_IF_TYPE_2) {
2fcee4bf
JS
11791 dev_printk(KERN_ERR, &pdev->dev,
11792 "FATAL - No BAR0 mapping for SLI4, if_type 2\n");
3a487ff7 11793 return -ENODEV;
2fcee4bf
JS
11794 }
11795 phba->sli4_hba.conf_regs_memmap_p =
da0436e9 11796 ioremap(phba->pci_bar0_map, bar0map_len);
2fcee4bf
JS
11797 if (!phba->sli4_hba.conf_regs_memmap_p) {
11798 dev_printk(KERN_ERR, &pdev->dev,
11799 "ioremap failed for SLI4 PCI config "
11800 "registers.\n");
3a487ff7 11801 return -ENODEV;
2fcee4bf
JS
11802 }
11803 lpfc_sli4_bar0_register_memmap(phba, if_type);
da0436e9
JS
11804 }
11805
e4b9794e
JS
11806 if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
11807 if (pci_resource_start(pdev, PCI_64BIT_BAR2)) {
11808 /*
11809 * Map SLI4 if type 0 HBA Control Register base to a
11810 * kernel virtual address and setup the registers.
11811 */
11812 phba->pci_bar1_map = pci_resource_start(pdev,
11813 PCI_64BIT_BAR2);
11814 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
11815 phba->sli4_hba.ctrl_regs_memmap_p =
11816 ioremap(phba->pci_bar1_map,
11817 bar1map_len);
11818 if (!phba->sli4_hba.ctrl_regs_memmap_p) {
11819 dev_err(&pdev->dev,
11820 "ioremap failed for SLI4 HBA "
11821 "control registers.\n");
11822 error = -ENOMEM;
11823 goto out_iounmap_conf;
11824 }
11825 phba->pci_bar2_memmap_p =
11826 phba->sli4_hba.ctrl_regs_memmap_p;
27d6ac0a 11827 lpfc_sli4_bar1_register_memmap(phba, if_type);
e4b9794e
JS
11828 } else {
11829 error = -ENOMEM;
2fcee4bf
JS
11830 goto out_iounmap_conf;
11831 }
da0436e9
JS
11832 }
11833
27d6ac0a
JS
11834 if ((if_type == LPFC_SLI_INTF_IF_TYPE_6) &&
11835 (pci_resource_start(pdev, PCI_64BIT_BAR2))) {
11836 /*
11837 * Map SLI4 if type 6 HBA Doorbell Register base to a kernel
11838 * virtual address and setup the registers.
11839 */
11840 phba->pci_bar1_map = pci_resource_start(pdev, PCI_64BIT_BAR2);
11841 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
11842 phba->sli4_hba.drbl_regs_memmap_p =
11843 ioremap(phba->pci_bar1_map, bar1map_len);
11844 if (!phba->sli4_hba.drbl_regs_memmap_p) {
11845 dev_err(&pdev->dev,
11846 "ioremap failed for SLI4 HBA doorbell registers.\n");
3a487ff7 11847 error = -ENOMEM;
27d6ac0a
JS
11848 goto out_iounmap_conf;
11849 }
11850 phba->pci_bar2_memmap_p = phba->sli4_hba.drbl_regs_memmap_p;
11851 lpfc_sli4_bar1_register_memmap(phba, if_type);
11852 }
11853
e4b9794e
JS
11854 if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
11855 if (pci_resource_start(pdev, PCI_64BIT_BAR4)) {
11856 /*
11857 * Map SLI4 if type 0 HBA Doorbell Register base to
11858 * a kernel virtual address and setup the registers.
11859 */
11860 phba->pci_bar2_map = pci_resource_start(pdev,
11861 PCI_64BIT_BAR4);
11862 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
11863 phba->sli4_hba.drbl_regs_memmap_p =
11864 ioremap(phba->pci_bar2_map,
11865 bar2map_len);
11866 if (!phba->sli4_hba.drbl_regs_memmap_p) {
11867 dev_err(&pdev->dev,
11868 "ioremap failed for SLI4 HBA"
11869 " doorbell registers.\n");
11870 error = -ENOMEM;
11871 goto out_iounmap_ctrl;
11872 }
11873 phba->pci_bar4_memmap_p =
11874 phba->sli4_hba.drbl_regs_memmap_p;
11875 error = lpfc_sli4_bar2_register_memmap(phba, LPFC_VF0);
11876 if (error)
11877 goto out_iounmap_all;
11878 } else {
11879 error = -ENOMEM;
2fcee4bf 11880 goto out_iounmap_all;
e4b9794e 11881 }
da0436e9
JS
11882 }
11883
1351e69f
JS
11884 if (if_type == LPFC_SLI_INTF_IF_TYPE_6 &&
11885 pci_resource_start(pdev, PCI_64BIT_BAR4)) {
11886 /*
11887 * Map SLI4 if type 6 HBA DPP Register base to a kernel
11888 * virtual address and setup the registers.
11889 */
11890 phba->pci_bar2_map = pci_resource_start(pdev, PCI_64BIT_BAR4);
11891 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
11892 phba->sli4_hba.dpp_regs_memmap_p =
11893 ioremap(phba->pci_bar2_map, bar2map_len);
11894 if (!phba->sli4_hba.dpp_regs_memmap_p) {
11895 dev_err(&pdev->dev,
11896 "ioremap failed for SLI4 HBA dpp registers.\n");
3a487ff7 11897 error = -ENOMEM;
1351e69f
JS
11898 goto out_iounmap_ctrl;
11899 }
11900 phba->pci_bar4_memmap_p = phba->sli4_hba.dpp_regs_memmap_p;
11901 }
11902
b71413dd 11903 /* Set up the EQ/CQ register handeling functions now */
27d6ac0a
JS
11904 switch (if_type) {
11905 case LPFC_SLI_INTF_IF_TYPE_0:
11906 case LPFC_SLI_INTF_IF_TYPE_2:
b71413dd 11907 phba->sli4_hba.sli4_eq_clr_intr = lpfc_sli4_eq_clr_intr;
32517fc0
JS
11908 phba->sli4_hba.sli4_write_eq_db = lpfc_sli4_write_eq_db;
11909 phba->sli4_hba.sli4_write_cq_db = lpfc_sli4_write_cq_db;
27d6ac0a
JS
11910 break;
11911 case LPFC_SLI_INTF_IF_TYPE_6:
11912 phba->sli4_hba.sli4_eq_clr_intr = lpfc_sli4_if6_eq_clr_intr;
32517fc0
JS
11913 phba->sli4_hba.sli4_write_eq_db = lpfc_sli4_if6_write_eq_db;
11914 phba->sli4_hba.sli4_write_cq_db = lpfc_sli4_if6_write_cq_db;
27d6ac0a
JS
11915 break;
11916 default:
11917 break;
b71413dd
JS
11918 }
11919
da0436e9
JS
11920 return 0;
11921
11922out_iounmap_all:
11923 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
11924out_iounmap_ctrl:
11925 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
11926out_iounmap_conf:
11927 iounmap(phba->sli4_hba.conf_regs_memmap_p);
3a487ff7 11928
da0436e9
JS
11929 return error;
11930}
11931
11932/**
11933 * lpfc_sli4_pci_mem_unset - Unset SLI4 HBA PCI memory space.
11934 * @phba: pointer to lpfc hba data structure.
11935 *
11936 * This routine is invoked to unset the PCI device memory space for device
11937 * with SLI-4 interface spec.
11938 **/
11939static void
11940lpfc_sli4_pci_mem_unset(struct lpfc_hba *phba)
11941{
2e90f4b5
JS
11942 uint32_t if_type;
11943 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
da0436e9 11944
2e90f4b5
JS
11945 switch (if_type) {
11946 case LPFC_SLI_INTF_IF_TYPE_0:
11947 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
11948 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
11949 iounmap(phba->sli4_hba.conf_regs_memmap_p);
11950 break;
11951 case LPFC_SLI_INTF_IF_TYPE_2:
11952 iounmap(phba->sli4_hba.conf_regs_memmap_p);
11953 break;
27d6ac0a
JS
11954 case LPFC_SLI_INTF_IF_TYPE_6:
11955 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
11956 iounmap(phba->sli4_hba.conf_regs_memmap_p);
0b439194
JS
11957 if (phba->sli4_hba.dpp_regs_memmap_p)
11958 iounmap(phba->sli4_hba.dpp_regs_memmap_p);
27d6ac0a 11959 break;
2e90f4b5
JS
11960 case LPFC_SLI_INTF_IF_TYPE_1:
11961 default:
11962 dev_printk(KERN_ERR, &phba->pcidev->dev,
11963 "FATAL - unsupported SLI4 interface type - %d\n",
11964 if_type);
11965 break;
11966 }
da0436e9
JS
11967}
11968
11969/**
11970 * lpfc_sli_enable_msix - Enable MSI-X interrupt mode on SLI-3 device
11971 * @phba: pointer to lpfc hba data structure.
11972 *
11973 * This routine is invoked to enable the MSI-X interrupt vectors to device
45ffac19 11974 * with SLI-3 interface specs.
da0436e9
JS
11975 *
11976 * Return codes
af901ca1 11977 * 0 - successful
da0436e9
JS
11978 * other values - error
11979 **/
11980static int
11981lpfc_sli_enable_msix(struct lpfc_hba *phba)
11982{
45ffac19 11983 int rc;
da0436e9
JS
11984 LPFC_MBOXQ_t *pmb;
11985
11986 /* Set up MSI-X multi-message vectors */
45ffac19
CH
11987 rc = pci_alloc_irq_vectors(phba->pcidev,
11988 LPFC_MSIX_VECTORS, LPFC_MSIX_VECTORS, PCI_IRQ_MSIX);
11989 if (rc < 0) {
da0436e9
JS
11990 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11991 "0420 PCI enable MSI-X failed (%d)\n", rc);
029165ac 11992 goto vec_fail_out;
da0436e9 11993 }
45ffac19 11994
da0436e9
JS
11995 /*
11996 * Assign MSI-X vectors to interrupt handlers
11997 */
11998
11999 /* vector-0 is associated to slow-path handler */
45ffac19 12000 rc = request_irq(pci_irq_vector(phba->pcidev, 0),
ed243d37 12001 &lpfc_sli_sp_intr_handler, 0,
da0436e9
JS
12002 LPFC_SP_DRIVER_HANDLER_NAME, phba);
12003 if (rc) {
12004 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
12005 "0421 MSI-X slow-path request_irq failed "
12006 "(%d)\n", rc);
12007 goto msi_fail_out;
12008 }
12009
12010 /* vector-1 is associated to fast-path handler */
45ffac19 12011 rc = request_irq(pci_irq_vector(phba->pcidev, 1),
ed243d37 12012 &lpfc_sli_fp_intr_handler, 0,
da0436e9
JS
12013 LPFC_FP_DRIVER_HANDLER_NAME, phba);
12014
12015 if (rc) {
12016 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
12017 "0429 MSI-X fast-path request_irq failed "
12018 "(%d)\n", rc);
12019 goto irq_fail_out;
12020 }
12021
12022 /*
12023 * Configure HBA MSI-X attention conditions to messages
12024 */
12025 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
12026
12027 if (!pmb) {
12028 rc = -ENOMEM;
372c187b 12029 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
12030 "0474 Unable to allocate memory for issuing "
12031 "MBOX_CONFIG_MSI command\n");
12032 goto mem_fail_out;
12033 }
12034 rc = lpfc_config_msi(phba, pmb);
12035 if (rc)
12036 goto mbx_fail_out;
12037 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
12038 if (rc != MBX_SUCCESS) {
12039 lpfc_printf_log(phba, KERN_WARNING, LOG_MBOX,
12040 "0351 Config MSI mailbox command failed, "
12041 "mbxCmd x%x, mbxStatus x%x\n",
12042 pmb->u.mb.mbxCommand, pmb->u.mb.mbxStatus);
12043 goto mbx_fail_out;
12044 }
12045
12046 /* Free memory allocated for mailbox command */
12047 mempool_free(pmb, phba->mbox_mem_pool);
12048 return rc;
12049
12050mbx_fail_out:
12051 /* Free memory allocated for mailbox command */
12052 mempool_free(pmb, phba->mbox_mem_pool);
12053
12054mem_fail_out:
12055 /* free the irq already requested */
45ffac19 12056 free_irq(pci_irq_vector(phba->pcidev, 1), phba);
da0436e9
JS
12057
12058irq_fail_out:
12059 /* free the irq already requested */
45ffac19 12060 free_irq(pci_irq_vector(phba->pcidev, 0), phba);
da0436e9
JS
12061
12062msi_fail_out:
12063 /* Unconfigure MSI-X capability structure */
45ffac19 12064 pci_free_irq_vectors(phba->pcidev);
029165ac
AG
12065
12066vec_fail_out:
da0436e9
JS
12067 return rc;
12068}
12069
da0436e9
JS
12070/**
12071 * lpfc_sli_enable_msi - Enable MSI interrupt mode on SLI-3 device.
12072 * @phba: pointer to lpfc hba data structure.
12073 *
12074 * This routine is invoked to enable the MSI interrupt mode to device with
12075 * SLI-3 interface spec. The kernel function pci_enable_msi() is called to
12076 * enable the MSI vector. The device driver is responsible for calling the
12077 * request_irq() to register MSI vector with a interrupt the handler, which
12078 * is done in this function.
12079 *
12080 * Return codes
af901ca1 12081 * 0 - successful
da0436e9
JS
12082 * other values - error
12083 */
12084static int
12085lpfc_sli_enable_msi(struct lpfc_hba *phba)
12086{
12087 int rc;
12088
12089 rc = pci_enable_msi(phba->pcidev);
12090 if (!rc)
12091 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12092 "0462 PCI enable MSI mode success.\n");
12093 else {
12094 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12095 "0471 PCI enable MSI mode failed (%d)\n", rc);
12096 return rc;
12097 }
12098
12099 rc = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
ed243d37 12100 0, LPFC_DRIVER_NAME, phba);
da0436e9
JS
12101 if (rc) {
12102 pci_disable_msi(phba->pcidev);
12103 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
12104 "0478 MSI request_irq failed (%d)\n", rc);
12105 }
12106 return rc;
12107}
12108
da0436e9
JS
12109/**
12110 * lpfc_sli_enable_intr - Enable device interrupt to SLI-3 device.
12111 * @phba: pointer to lpfc hba data structure.
fe614acd 12112 * @cfg_mode: Interrupt configuration mode (INTx, MSI or MSI-X).
da0436e9
JS
12113 *
12114 * This routine is invoked to enable device interrupt and associate driver's
12115 * interrupt handler(s) to interrupt vector(s) to device with SLI-3 interface
12116 * spec. Depends on the interrupt mode configured to the driver, the driver
12117 * will try to fallback from the configured interrupt mode to an interrupt
12118 * mode which is supported by the platform, kernel, and device in the order
12119 * of:
12120 * MSI-X -> MSI -> IRQ.
12121 *
12122 * Return codes
af901ca1 12123 * 0 - successful
da0436e9
JS
12124 * other values - error
12125 **/
12126static uint32_t
12127lpfc_sli_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
12128{
12129 uint32_t intr_mode = LPFC_INTR_ERROR;
12130 int retval;
12131
d2f2547e
JS
12132 /* Need to issue conf_port mbox cmd before conf_msi mbox cmd */
12133 retval = lpfc_sli_config_port(phba, LPFC_SLI_REV3);
12134 if (retval)
12135 return intr_mode;
12136 phba->hba_flag &= ~HBA_NEEDS_CFG_PORT;
12137
da0436e9 12138 if (cfg_mode == 2) {
d2f2547e
JS
12139 /* Now, try to enable MSI-X interrupt mode */
12140 retval = lpfc_sli_enable_msix(phba);
da0436e9 12141 if (!retval) {
d2f2547e
JS
12142 /* Indicate initialization to MSI-X mode */
12143 phba->intr_type = MSIX;
12144 intr_mode = 2;
da0436e9
JS
12145 }
12146 }
12147
12148 /* Fallback to MSI if MSI-X initialization failed */
12149 if (cfg_mode >= 1 && phba->intr_type == NONE) {
12150 retval = lpfc_sli_enable_msi(phba);
12151 if (!retval) {
12152 /* Indicate initialization to MSI mode */
12153 phba->intr_type = MSI;
12154 intr_mode = 1;
12155 }
12156 }
12157
12158 /* Fallback to INTx if both MSI-X/MSI initalization failed */
12159 if (phba->intr_type == NONE) {
12160 retval = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
12161 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
12162 if (!retval) {
12163 /* Indicate initialization to INTx mode */
12164 phba->intr_type = INTx;
12165 intr_mode = 0;
12166 }
12167 }
12168 return intr_mode;
12169}
12170
12171/**
12172 * lpfc_sli_disable_intr - Disable device interrupt to SLI-3 device.
12173 * @phba: pointer to lpfc hba data structure.
12174 *
12175 * This routine is invoked to disable device interrupt and disassociate the
12176 * driver's interrupt handler(s) from interrupt vector(s) to device with
12177 * SLI-3 interface spec. Depending on the interrupt mode, the driver will
12178 * release the interrupt vector(s) for the message signaled interrupt.
12179 **/
12180static void
12181lpfc_sli_disable_intr(struct lpfc_hba *phba)
12182{
45ffac19
CH
12183 int nr_irqs, i;
12184
da0436e9 12185 if (phba->intr_type == MSIX)
45ffac19
CH
12186 nr_irqs = LPFC_MSIX_VECTORS;
12187 else
12188 nr_irqs = 1;
12189
12190 for (i = 0; i < nr_irqs; i++)
12191 free_irq(pci_irq_vector(phba->pcidev, i), phba);
12192 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
12193
12194 /* Reset interrupt management states */
12195 phba->intr_type = NONE;
12196 phba->sli.slistat.sli_intr = 0;
da0436e9
JS
12197}
12198
6a828b0f 12199/**
657add4e 12200 * lpfc_find_cpu_handle - Find the CPU that corresponds to the specified Queue
6a828b0f
JS
12201 * @phba: pointer to lpfc hba data structure.
12202 * @id: EQ vector index or Hardware Queue index
12203 * @match: LPFC_FIND_BY_EQ = match by EQ
12204 * LPFC_FIND_BY_HDWQ = match by Hardware Queue
657add4e 12205 * Return the CPU that matches the selection criteria
6a828b0f
JS
12206 */
12207static uint16_t
12208lpfc_find_cpu_handle(struct lpfc_hba *phba, uint16_t id, int match)
12209{
12210 struct lpfc_vector_map_info *cpup;
12211 int cpu;
12212
657add4e 12213 /* Loop through all CPUs */
222e9239
JS
12214 for_each_present_cpu(cpu) {
12215 cpup = &phba->sli4_hba.cpu_map[cpu];
657add4e
JS
12216
12217 /* If we are matching by EQ, there may be multiple CPUs using
12218 * using the same vector, so select the one with
12219 * LPFC_CPU_FIRST_IRQ set.
12220 */
6a828b0f 12221 if ((match == LPFC_FIND_BY_EQ) &&
657add4e 12222 (cpup->flag & LPFC_CPU_FIRST_IRQ) &&
6a828b0f
JS
12223 (cpup->eq == id))
12224 return cpu;
657add4e
JS
12225
12226 /* If matching by HDWQ, select the first CPU that matches */
6a828b0f
JS
12227 if ((match == LPFC_FIND_BY_HDWQ) && (cpup->hdwq == id))
12228 return cpu;
6a828b0f
JS
12229 }
12230 return 0;
12231}
12232
6a828b0f
JS
12233#ifdef CONFIG_X86
12234/**
12235 * lpfc_find_hyper - Determine if the CPU map entry is hyper-threaded
12236 * @phba: pointer to lpfc hba data structure.
12237 * @cpu: CPU map index
12238 * @phys_id: CPU package physical id
12239 * @core_id: CPU core id
12240 */
12241static int
12242lpfc_find_hyper(struct lpfc_hba *phba, int cpu,
12243 uint16_t phys_id, uint16_t core_id)
12244{
12245 struct lpfc_vector_map_info *cpup;
12246 int idx;
12247
222e9239
JS
12248 for_each_present_cpu(idx) {
12249 cpup = &phba->sli4_hba.cpu_map[idx];
6a828b0f
JS
12250 /* Does the cpup match the one we are looking for */
12251 if ((cpup->phys_id == phys_id) &&
12252 (cpup->core_id == core_id) &&
222e9239 12253 (cpu != idx))
6a828b0f 12254 return 1;
6a828b0f
JS
12255 }
12256 return 0;
12257}
12258#endif
12259
dcaa2136
JS
12260/*
12261 * lpfc_assign_eq_map_info - Assigns eq for vector_map structure
12262 * @phba: pointer to lpfc hba data structure.
12263 * @eqidx: index for eq and irq vector
12264 * @flag: flags to set for vector_map structure
12265 * @cpu: cpu used to index vector_map structure
12266 *
12267 * The routine assigns eq info into vector_map structure
12268 */
12269static inline void
12270lpfc_assign_eq_map_info(struct lpfc_hba *phba, uint16_t eqidx, uint16_t flag,
12271 unsigned int cpu)
12272{
12273 struct lpfc_vector_map_info *cpup = &phba->sli4_hba.cpu_map[cpu];
12274 struct lpfc_hba_eq_hdl *eqhdl = lpfc_get_eq_hdl(eqidx);
12275
12276 cpup->eq = eqidx;
12277 cpup->flag |= flag;
12278
12279 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12280 "3336 Set Affinity: CPU %d irq %d eq %d flag x%x\n",
12281 cpu, eqhdl->irq, cpup->eq, cpup->flag);
12282}
12283
12284/**
12285 * lpfc_cpu_map_array_init - Initialize cpu_map structure
12286 * @phba: pointer to lpfc hba data structure.
12287 *
12288 * The routine initializes the cpu_map array structure
12289 */
12290static void
12291lpfc_cpu_map_array_init(struct lpfc_hba *phba)
12292{
12293 struct lpfc_vector_map_info *cpup;
12294 struct lpfc_eq_intr_info *eqi;
12295 int cpu;
12296
12297 for_each_possible_cpu(cpu) {
12298 cpup = &phba->sli4_hba.cpu_map[cpu];
12299 cpup->phys_id = LPFC_VECTOR_MAP_EMPTY;
12300 cpup->core_id = LPFC_VECTOR_MAP_EMPTY;
12301 cpup->hdwq = LPFC_VECTOR_MAP_EMPTY;
12302 cpup->eq = LPFC_VECTOR_MAP_EMPTY;
12303 cpup->flag = 0;
12304 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, cpu);
12305 INIT_LIST_HEAD(&eqi->list);
12306 eqi->icnt = 0;
12307 }
12308}
12309
12310/**
12311 * lpfc_hba_eq_hdl_array_init - Initialize hba_eq_hdl structure
12312 * @phba: pointer to lpfc hba data structure.
12313 *
12314 * The routine initializes the hba_eq_hdl array structure
12315 */
12316static void
12317lpfc_hba_eq_hdl_array_init(struct lpfc_hba *phba)
12318{
12319 struct lpfc_hba_eq_hdl *eqhdl;
12320 int i;
12321
12322 for (i = 0; i < phba->cfg_irq_chann; i++) {
12323 eqhdl = lpfc_get_eq_hdl(i);
12324 eqhdl->irq = LPFC_VECTOR_MAP_EMPTY;
12325 eqhdl->phba = phba;
12326 }
12327}
12328
7bb03bbf 12329/**
895427bd 12330 * lpfc_cpu_affinity_check - Check vector CPU affinity mappings
7bb03bbf 12331 * @phba: pointer to lpfc hba data structure.
895427bd
JS
12332 * @vectors: number of msix vectors allocated.
12333 *
12334 * The routine will figure out the CPU affinity assignment for every
6a828b0f 12335 * MSI-X vector allocated for the HBA.
895427bd
JS
12336 * In addition, the CPU to IO channel mapping will be calculated
12337 * and the phba->sli4_hba.cpu_map array will reflect this.
7bb03bbf 12338 */
895427bd
JS
12339static void
12340lpfc_cpu_affinity_check(struct lpfc_hba *phba, int vectors)
7bb03bbf 12341{
3ad348d9 12342 int i, cpu, idx, next_idx, new_cpu, start_cpu, first_cpu;
6a828b0f
JS
12343 int max_phys_id, min_phys_id;
12344 int max_core_id, min_core_id;
7bb03bbf 12345 struct lpfc_vector_map_info *cpup;
d9954a2d 12346 struct lpfc_vector_map_info *new_cpup;
7bb03bbf
JS
12347#ifdef CONFIG_X86
12348 struct cpuinfo_x86 *cpuinfo;
12349#endif
840eda96
JS
12350#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
12351 struct lpfc_hdwq_stat *c_stat;
12352#endif
7bb03bbf 12353
6a828b0f 12354 max_phys_id = 0;
d9954a2d 12355 min_phys_id = LPFC_VECTOR_MAP_EMPTY;
6a828b0f 12356 max_core_id = 0;
d9954a2d 12357 min_core_id = LPFC_VECTOR_MAP_EMPTY;
7bb03bbf
JS
12358
12359 /* Update CPU map with physical id and core id of each CPU */
222e9239
JS
12360 for_each_present_cpu(cpu) {
12361 cpup = &phba->sli4_hba.cpu_map[cpu];
7bb03bbf
JS
12362#ifdef CONFIG_X86
12363 cpuinfo = &cpu_data(cpu);
12364 cpup->phys_id = cpuinfo->phys_proc_id;
12365 cpup->core_id = cpuinfo->cpu_core_id;
d9954a2d
JS
12366 if (lpfc_find_hyper(phba, cpu, cpup->phys_id, cpup->core_id))
12367 cpup->flag |= LPFC_CPU_MAP_HYPER;
7bb03bbf
JS
12368#else
12369 /* No distinction between CPUs for other platforms */
12370 cpup->phys_id = 0;
6a828b0f 12371 cpup->core_id = cpu;
7bb03bbf 12372#endif
6a828b0f 12373
b3295c2a 12374 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3ad348d9
JS
12375 "3328 CPU %d physid %d coreid %d flag x%x\n",
12376 cpu, cpup->phys_id, cpup->core_id, cpup->flag);
6a828b0f
JS
12377
12378 if (cpup->phys_id > max_phys_id)
12379 max_phys_id = cpup->phys_id;
12380 if (cpup->phys_id < min_phys_id)
12381 min_phys_id = cpup->phys_id;
12382
12383 if (cpup->core_id > max_core_id)
12384 max_core_id = cpup->core_id;
12385 if (cpup->core_id < min_core_id)
12386 min_core_id = cpup->core_id;
7bb03bbf 12387 }
7bb03bbf 12388
d9954a2d
JS
12389 /* After looking at each irq vector assigned to this pcidev, its
12390 * possible to see that not ALL CPUs have been accounted for.
657add4e
JS
12391 * Next we will set any unassigned (unaffinitized) cpu map
12392 * entries to a IRQ on the same phys_id.
d9954a2d
JS
12393 */
12394 first_cpu = cpumask_first(cpu_present_mask);
12395 start_cpu = first_cpu;
12396
12397 for_each_present_cpu(cpu) {
12398 cpup = &phba->sli4_hba.cpu_map[cpu];
12399
12400 /* Is this CPU entry unassigned */
12401 if (cpup->eq == LPFC_VECTOR_MAP_EMPTY) {
12402 /* Mark CPU as IRQ not assigned by the kernel */
12403 cpup->flag |= LPFC_CPU_MAP_UNASSIGN;
12404
657add4e 12405 /* If so, find a new_cpup thats on the the SAME
d9954a2d
JS
12406 * phys_id as cpup. start_cpu will start where we
12407 * left off so all unassigned entries don't get assgined
12408 * the IRQ of the first entry.
12409 */
12410 new_cpu = start_cpu;
12411 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
12412 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
12413 if (!(new_cpup->flag & LPFC_CPU_MAP_UNASSIGN) &&
dcaa2136 12414 (new_cpup->eq != LPFC_VECTOR_MAP_EMPTY) &&
d9954a2d
JS
12415 (new_cpup->phys_id == cpup->phys_id))
12416 goto found_same;
12417 new_cpu = cpumask_next(
12418 new_cpu, cpu_present_mask);
12419 if (new_cpu == nr_cpumask_bits)
12420 new_cpu = first_cpu;
12421 }
12422 /* At this point, we leave the CPU as unassigned */
12423 continue;
12424found_same:
12425 /* We found a matching phys_id, so copy the IRQ info */
12426 cpup->eq = new_cpup->eq;
d9954a2d
JS
12427
12428 /* Bump start_cpu to the next slot to minmize the
12429 * chance of having multiple unassigned CPU entries
12430 * selecting the same IRQ.
12431 */
12432 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
12433 if (start_cpu == nr_cpumask_bits)
12434 start_cpu = first_cpu;
12435
657add4e 12436 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
d9954a2d 12437 "3337 Set Affinity: CPU %d "
dcaa2136 12438 "eq %d from peer cpu %d same "
d9954a2d 12439 "phys_id (%d)\n",
dcaa2136
JS
12440 cpu, cpup->eq, new_cpu,
12441 cpup->phys_id);
d9954a2d
JS
12442 }
12443 }
12444
12445 /* Set any unassigned cpu map entries to a IRQ on any phys_id */
12446 start_cpu = first_cpu;
12447
12448 for_each_present_cpu(cpu) {
12449 cpup = &phba->sli4_hba.cpu_map[cpu];
12450
12451 /* Is this entry unassigned */
12452 if (cpup->eq == LPFC_VECTOR_MAP_EMPTY) {
12453 /* Mark it as IRQ not assigned by the kernel */
12454 cpup->flag |= LPFC_CPU_MAP_UNASSIGN;
12455
657add4e 12456 /* If so, find a new_cpup thats on ANY phys_id
d9954a2d
JS
12457 * as the cpup. start_cpu will start where we
12458 * left off so all unassigned entries don't get
12459 * assigned the IRQ of the first entry.
12460 */
12461 new_cpu = start_cpu;
12462 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
12463 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
12464 if (!(new_cpup->flag & LPFC_CPU_MAP_UNASSIGN) &&
dcaa2136 12465 (new_cpup->eq != LPFC_VECTOR_MAP_EMPTY))
d9954a2d
JS
12466 goto found_any;
12467 new_cpu = cpumask_next(
12468 new_cpu, cpu_present_mask);
12469 if (new_cpu == nr_cpumask_bits)
12470 new_cpu = first_cpu;
12471 }
12472 /* We should never leave an entry unassigned */
12473 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12474 "3339 Set Affinity: CPU %d "
dcaa2136
JS
12475 "eq %d UNASSIGNED\n",
12476 cpup->hdwq, cpup->eq);
d9954a2d
JS
12477 continue;
12478found_any:
12479 /* We found an available entry, copy the IRQ info */
12480 cpup->eq = new_cpup->eq;
d9954a2d
JS
12481
12482 /* Bump start_cpu to the next slot to minmize the
12483 * chance of having multiple unassigned CPU entries
12484 * selecting the same IRQ.
12485 */
12486 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
12487 if (start_cpu == nr_cpumask_bits)
12488 start_cpu = first_cpu;
12489
657add4e 12490 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
d9954a2d 12491 "3338 Set Affinity: CPU %d "
dcaa2136
JS
12492 "eq %d from peer cpu %d (%d/%d)\n",
12493 cpu, cpup->eq, new_cpu,
d9954a2d
JS
12494 new_cpup->phys_id, new_cpup->core_id);
12495 }
12496 }
657add4e 12497
3ad348d9
JS
12498 /* Assign hdwq indices that are unique across all cpus in the map
12499 * that are also FIRST_CPUs.
12500 */
12501 idx = 0;
12502 for_each_present_cpu(cpu) {
12503 cpup = &phba->sli4_hba.cpu_map[cpu];
12504
12505 /* Only FIRST IRQs get a hdwq index assignment. */
12506 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
12507 continue;
12508
12509 /* 1 to 1, the first LPFC_CPU_FIRST_IRQ cpus to a unique hdwq */
12510 cpup->hdwq = idx;
12511 idx++;
bc2736e9 12512 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3ad348d9 12513 "3333 Set Affinity: CPU %d (phys %d core %d): "
dcaa2136 12514 "hdwq %d eq %d flg x%x\n",
3ad348d9 12515 cpu, cpup->phys_id, cpup->core_id,
dcaa2136 12516 cpup->hdwq, cpup->eq, cpup->flag);
3ad348d9 12517 }
bc227dde 12518 /* Associate a hdwq with each cpu_map entry
657add4e
JS
12519 * This will be 1 to 1 - hdwq to cpu, unless there are less
12520 * hardware queues then CPUs. For that case we will just round-robin
12521 * the available hardware queues as they get assigned to CPUs.
3ad348d9
JS
12522 * The next_idx is the idx from the FIRST_CPU loop above to account
12523 * for irq_chann < hdwq. The idx is used for round-robin assignments
12524 * and needs to start at 0.
657add4e 12525 */
3ad348d9 12526 next_idx = idx;
657add4e 12527 start_cpu = 0;
3ad348d9 12528 idx = 0;
657add4e
JS
12529 for_each_present_cpu(cpu) {
12530 cpup = &phba->sli4_hba.cpu_map[cpu];
657add4e 12531
3ad348d9
JS
12532 /* FIRST cpus are already mapped. */
12533 if (cpup->flag & LPFC_CPU_FIRST_IRQ)
12534 continue;
12535
12536 /* If the cfg_irq_chann < cfg_hdw_queue, set the hdwq
12537 * of the unassigned cpus to the next idx so that all
12538 * hdw queues are fully utilized.
12539 */
12540 if (next_idx < phba->cfg_hdw_queue) {
12541 cpup->hdwq = next_idx;
12542 next_idx++;
12543 continue;
12544 }
12545
12546 /* Not a First CPU and all hdw_queues are used. Reuse a
12547 * Hardware Queue for another CPU, so be smart about it
12548 * and pick one that has its IRQ/EQ mapped to the same phys_id
12549 * (CPU package) and core_id.
12550 */
12551 new_cpu = start_cpu;
12552 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
12553 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
12554 if (new_cpup->hdwq != LPFC_VECTOR_MAP_EMPTY &&
12555 new_cpup->phys_id == cpup->phys_id &&
12556 new_cpup->core_id == cpup->core_id) {
12557 goto found_hdwq;
657add4e 12558 }
3ad348d9
JS
12559 new_cpu = cpumask_next(new_cpu, cpu_present_mask);
12560 if (new_cpu == nr_cpumask_bits)
12561 new_cpu = first_cpu;
12562 }
657add4e 12563
3ad348d9
JS
12564 /* If we can't match both phys_id and core_id,
12565 * settle for just a phys_id match.
12566 */
12567 new_cpu = start_cpu;
12568 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
12569 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
12570 if (new_cpup->hdwq != LPFC_VECTOR_MAP_EMPTY &&
12571 new_cpup->phys_id == cpup->phys_id)
12572 goto found_hdwq;
12573
12574 new_cpu = cpumask_next(new_cpu, cpu_present_mask);
12575 if (new_cpu == nr_cpumask_bits)
12576 new_cpu = first_cpu;
657add4e 12577 }
3ad348d9
JS
12578
12579 /* Otherwise just round robin on cfg_hdw_queue */
12580 cpup->hdwq = idx % phba->cfg_hdw_queue;
12581 idx++;
12582 goto logit;
12583 found_hdwq:
12584 /* We found an available entry, copy the IRQ info */
12585 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
12586 if (start_cpu == nr_cpumask_bits)
12587 start_cpu = first_cpu;
12588 cpup->hdwq = new_cpup->hdwq;
12589 logit:
bc2736e9 12590 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
657add4e 12591 "3335 Set Affinity: CPU %d (phys %d core %d): "
dcaa2136 12592 "hdwq %d eq %d flg x%x\n",
657add4e 12593 cpu, cpup->phys_id, cpup->core_id,
dcaa2136 12594 cpup->hdwq, cpup->eq, cpup->flag);
657add4e
JS
12595 }
12596
bc227dde
JS
12597 /*
12598 * Initialize the cpu_map slots for not-present cpus in case
12599 * a cpu is hot-added. Perform a simple hdwq round robin assignment.
12600 */
12601 idx = 0;
12602 for_each_possible_cpu(cpu) {
12603 cpup = &phba->sli4_hba.cpu_map[cpu];
840eda96
JS
12604#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
12605 c_stat = per_cpu_ptr(phba->sli4_hba.c_stat, cpu);
12606 c_stat->hdwq_no = cpup->hdwq;
12607#endif
bc227dde
JS
12608 if (cpup->hdwq != LPFC_VECTOR_MAP_EMPTY)
12609 continue;
12610
12611 cpup->hdwq = idx++ % phba->cfg_hdw_queue;
840eda96
JS
12612#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
12613 c_stat->hdwq_no = cpup->hdwq;
12614#endif
bc227dde
JS
12615 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12616 "3340 Set Affinity: not present "
12617 "CPU %d hdwq %d\n",
12618 cpu, cpup->hdwq);
657add4e
JS
12619 }
12620
12621 /* The cpu_map array will be used later during initialization
12622 * when EQ / CQ / WQs are allocated and configured.
12623 */
b3295c2a 12624 return;
7bb03bbf 12625}
7bb03bbf 12626
93a4d6f4
JS
12627/**
12628 * lpfc_cpuhp_get_eq
12629 *
12630 * @phba: pointer to lpfc hba data structure.
12631 * @cpu: cpu going offline
fe614acd 12632 * @eqlist: eq list to append to
93a4d6f4 12633 */
a99c8074 12634static int
93a4d6f4
JS
12635lpfc_cpuhp_get_eq(struct lpfc_hba *phba, unsigned int cpu,
12636 struct list_head *eqlist)
12637{
93a4d6f4
JS
12638 const struct cpumask *maskp;
12639 struct lpfc_queue *eq;
a99c8074 12640 struct cpumask *tmp;
93a4d6f4
JS
12641 u16 idx;
12642
a99c8074
JS
12643 tmp = kzalloc(cpumask_size(), GFP_KERNEL);
12644 if (!tmp)
12645 return -ENOMEM;
12646
93a4d6f4
JS
12647 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
12648 maskp = pci_irq_get_affinity(phba->pcidev, idx);
12649 if (!maskp)
12650 continue;
12651 /*
12652 * if irq is not affinitized to the cpu going
12653 * then we don't need to poll the eq attached
12654 * to it.
12655 */
a99c8074 12656 if (!cpumask_and(tmp, maskp, cpumask_of(cpu)))
93a4d6f4
JS
12657 continue;
12658 /* get the cpus that are online and are affini-
12659 * tized to this irq vector. If the count is
12660 * more than 1 then cpuhp is not going to shut-
12661 * down this vector. Since this cpu has not
12662 * gone offline yet, we need >1.
12663 */
a99c8074
JS
12664 cpumask_and(tmp, maskp, cpu_online_mask);
12665 if (cpumask_weight(tmp) > 1)
93a4d6f4
JS
12666 continue;
12667
12668 /* Now that we have an irq to shutdown, get the eq
12669 * mapped to this irq. Note: multiple hdwq's in
12670 * the software can share an eq, but eventually
12671 * only eq will be mapped to this vector
12672 */
dcaa2136
JS
12673 eq = phba->sli4_hba.hba_eq_hdl[idx].eq;
12674 list_add(&eq->_poll_list, eqlist);
93a4d6f4 12675 }
a99c8074
JS
12676 kfree(tmp);
12677 return 0;
93a4d6f4
JS
12678}
12679
12680static void __lpfc_cpuhp_remove(struct lpfc_hba *phba)
12681{
12682 if (phba->sli_rev != LPFC_SLI_REV4)
12683 return;
12684
12685 cpuhp_state_remove_instance_nocalls(lpfc_cpuhp_state,
12686 &phba->cpuhp);
12687 /*
12688 * unregistering the instance doesn't stop the polling
12689 * timer. Wait for the poll timer to retire.
12690 */
12691 synchronize_rcu();
12692 del_timer_sync(&phba->cpuhp_poll_timer);
12693}
12694
12695static void lpfc_cpuhp_remove(struct lpfc_hba *phba)
12696{
12697 if (phba->pport->fc_flag & FC_OFFLINE_MODE)
12698 return;
12699
12700 __lpfc_cpuhp_remove(phba);
12701}
12702
12703static void lpfc_cpuhp_add(struct lpfc_hba *phba)
12704{
12705 if (phba->sli_rev != LPFC_SLI_REV4)
12706 return;
12707
12708 rcu_read_lock();
12709
f861f596 12710 if (!list_empty(&phba->poll_list))
93a4d6f4
JS
12711 mod_timer(&phba->cpuhp_poll_timer,
12712 jiffies + msecs_to_jiffies(LPFC_POLL_HB));
93a4d6f4
JS
12713
12714 rcu_read_unlock();
12715
12716 cpuhp_state_add_instance_nocalls(lpfc_cpuhp_state,
12717 &phba->cpuhp);
12718}
12719
12720static int __lpfc_cpuhp_checks(struct lpfc_hba *phba, int *retval)
12721{
12722 if (phba->pport->load_flag & FC_UNLOADING) {
12723 *retval = -EAGAIN;
12724 return true;
12725 }
12726
12727 if (phba->sli_rev != LPFC_SLI_REV4) {
12728 *retval = 0;
12729 return true;
12730 }
12731
12732 /* proceed with the hotplug */
12733 return false;
12734}
12735
dcaa2136
JS
12736/**
12737 * lpfc_irq_set_aff - set IRQ affinity
12738 * @eqhdl: EQ handle
12739 * @cpu: cpu to set affinity
12740 *
12741 **/
12742static inline void
12743lpfc_irq_set_aff(struct lpfc_hba_eq_hdl *eqhdl, unsigned int cpu)
12744{
12745 cpumask_clear(&eqhdl->aff_mask);
12746 cpumask_set_cpu(cpu, &eqhdl->aff_mask);
12747 irq_set_status_flags(eqhdl->irq, IRQ_NO_BALANCING);
ce5a58a9 12748 irq_set_affinity(eqhdl->irq, &eqhdl->aff_mask);
dcaa2136
JS
12749}
12750
12751/**
12752 * lpfc_irq_clear_aff - clear IRQ affinity
12753 * @eqhdl: EQ handle
12754 *
12755 **/
12756static inline void
12757lpfc_irq_clear_aff(struct lpfc_hba_eq_hdl *eqhdl)
12758{
12759 cpumask_clear(&eqhdl->aff_mask);
12760 irq_clear_status_flags(eqhdl->irq, IRQ_NO_BALANCING);
dcaa2136
JS
12761}
12762
12763/**
12764 * lpfc_irq_rebalance - rebalances IRQ affinity according to cpuhp event
12765 * @phba: pointer to HBA context object.
12766 * @cpu: cpu going offline/online
12767 * @offline: true, cpu is going offline. false, cpu is coming online.
12768 *
12769 * If cpu is going offline, we'll try our best effort to find the next
3048e3e8
DK
12770 * online cpu on the phba's original_mask and migrate all offlining IRQ
12771 * affinities.
dcaa2136 12772 *
3048e3e8 12773 * If cpu is coming online, reaffinitize the IRQ back to the onlining cpu.
dcaa2136 12774 *
3048e3e8 12775 * Note: Call only if NUMA or NHT mode is enabled, otherwise rely on
dcaa2136
JS
12776 * PCI_IRQ_AFFINITY to auto-manage IRQ affinity.
12777 *
12778 **/
12779static void
12780lpfc_irq_rebalance(struct lpfc_hba *phba, unsigned int cpu, bool offline)
12781{
12782 struct lpfc_vector_map_info *cpup;
12783 struct cpumask *aff_mask;
12784 unsigned int cpu_select, cpu_next, idx;
3048e3e8 12785 const struct cpumask *orig_mask;
dcaa2136 12786
3048e3e8 12787 if (phba->irq_chann_mode == NORMAL_MODE)
dcaa2136
JS
12788 return;
12789
3048e3e8 12790 orig_mask = &phba->sli4_hba.irq_aff_mask;
dcaa2136 12791
3048e3e8 12792 if (!cpumask_test_cpu(cpu, orig_mask))
dcaa2136
JS
12793 return;
12794
12795 cpup = &phba->sli4_hba.cpu_map[cpu];
12796
12797 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
12798 return;
12799
12800 if (offline) {
3048e3e8
DK
12801 /* Find next online CPU on original mask */
12802 cpu_next = cpumask_next_wrap(cpu, orig_mask, cpu, true);
12803 cpu_select = lpfc_next_online_cpu(orig_mask, cpu_next);
dcaa2136
JS
12804
12805 /* Found a valid CPU */
12806 if ((cpu_select < nr_cpu_ids) && (cpu_select != cpu)) {
12807 /* Go through each eqhdl and ensure offlining
12808 * cpu aff_mask is migrated
12809 */
12810 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
12811 aff_mask = lpfc_get_aff_mask(idx);
12812
12813 /* Migrate affinity */
12814 if (cpumask_test_cpu(cpu, aff_mask))
12815 lpfc_irq_set_aff(lpfc_get_eq_hdl(idx),
12816 cpu_select);
12817 }
12818 } else {
12819 /* Rely on irqbalance if no online CPUs left on NUMA */
12820 for (idx = 0; idx < phba->cfg_irq_chann; idx++)
12821 lpfc_irq_clear_aff(lpfc_get_eq_hdl(idx));
12822 }
12823 } else {
12824 /* Migrate affinity back to this CPU */
12825 lpfc_irq_set_aff(lpfc_get_eq_hdl(cpup->eq), cpu);
12826 }
12827}
12828
93a4d6f4
JS
12829static int lpfc_cpu_offline(unsigned int cpu, struct hlist_node *node)
12830{
12831 struct lpfc_hba *phba = hlist_entry_safe(node, struct lpfc_hba, cpuhp);
12832 struct lpfc_queue *eq, *next;
12833 LIST_HEAD(eqlist);
12834 int retval;
12835
12836 if (!phba) {
12837 WARN_ONCE(!phba, "cpu: %u. phba:NULL", raw_smp_processor_id());
12838 return 0;
12839 }
12840
12841 if (__lpfc_cpuhp_checks(phba, &retval))
12842 return retval;
12843
dcaa2136
JS
12844 lpfc_irq_rebalance(phba, cpu, true);
12845
a99c8074
JS
12846 retval = lpfc_cpuhp_get_eq(phba, cpu, &eqlist);
12847 if (retval)
12848 return retval;
93a4d6f4
JS
12849
12850 /* start polling on these eq's */
12851 list_for_each_entry_safe(eq, next, &eqlist, _poll_list) {
12852 list_del_init(&eq->_poll_list);
12853 lpfc_sli4_start_polling(eq);
12854 }
12855
12856 return 0;
12857}
12858
12859static int lpfc_cpu_online(unsigned int cpu, struct hlist_node *node)
12860{
12861 struct lpfc_hba *phba = hlist_entry_safe(node, struct lpfc_hba, cpuhp);
12862 struct lpfc_queue *eq, *next;
12863 unsigned int n;
12864 int retval;
12865
12866 if (!phba) {
12867 WARN_ONCE(!phba, "cpu: %u. phba:NULL", raw_smp_processor_id());
12868 return 0;
12869 }
12870
12871 if (__lpfc_cpuhp_checks(phba, &retval))
12872 return retval;
12873
dcaa2136
JS
12874 lpfc_irq_rebalance(phba, cpu, false);
12875
93a4d6f4
JS
12876 list_for_each_entry_safe(eq, next, &phba->poll_list, _poll_list) {
12877 n = lpfc_find_cpu_handle(phba, eq->hdwq, LPFC_FIND_BY_HDWQ);
12878 if (n == cpu)
12879 lpfc_sli4_stop_polling(eq);
12880 }
12881
12882 return 0;
12883}
12884
da0436e9
JS
12885/**
12886 * lpfc_sli4_enable_msix - Enable MSI-X interrupt mode to SLI-4 device
12887 * @phba: pointer to lpfc hba data structure.
12888 *
12889 * This routine is invoked to enable the MSI-X interrupt vectors to device
dcaa2136
JS
12890 * with SLI-4 interface spec. It also allocates MSI-X vectors and maps them
12891 * to cpus on the system.
12892 *
12893 * When cfg_irq_numa is enabled, the adapter will only allocate vectors for
12894 * the number of cpus on the same numa node as this adapter. The vectors are
12895 * allocated without requesting OS affinity mapping. A vector will be
12896 * allocated and assigned to each online and offline cpu. If the cpu is
12897 * online, then affinity will be set to that cpu. If the cpu is offline, then
12898 * affinity will be set to the nearest peer cpu within the numa node that is
12899 * online. If there are no online cpus within the numa node, affinity is not
12900 * assigned and the OS may do as it pleases. Note: cpu vector affinity mapping
12901 * is consistent with the way cpu online/offline is handled when cfg_irq_numa is
12902 * configured.
12903 *
12904 * If numa mode is not enabled and there is more than 1 vector allocated, then
12905 * the driver relies on the managed irq interface where the OS assigns vector to
12906 * cpu affinity. The driver will then use that affinity mapping to setup its
12907 * cpu mapping table.
da0436e9
JS
12908 *
12909 * Return codes
af901ca1 12910 * 0 - successful
da0436e9
JS
12911 * other values - error
12912 **/
12913static int
12914lpfc_sli4_enable_msix(struct lpfc_hba *phba)
12915{
75baf696 12916 int vectors, rc, index;
b83d005e 12917 char *name;
3048e3e8 12918 const struct cpumask *aff_mask = NULL;
dcaa2136 12919 unsigned int cpu = 0, cpu_cnt = 0, cpu_select = nr_cpu_ids;
17105d95 12920 struct lpfc_vector_map_info *cpup;
dcaa2136
JS
12921 struct lpfc_hba_eq_hdl *eqhdl;
12922 const struct cpumask *maskp;
dcaa2136 12923 unsigned int flags = PCI_IRQ_MSIX;
da0436e9
JS
12924
12925 /* Set up MSI-X multi-message vectors */
6a828b0f 12926 vectors = phba->cfg_irq_chann;
45ffac19 12927
3048e3e8
DK
12928 if (phba->irq_chann_mode != NORMAL_MODE)
12929 aff_mask = &phba->sli4_hba.irq_aff_mask;
12930
12931 if (aff_mask) {
12932 cpu_cnt = cpumask_weight(aff_mask);
dcaa2136
JS
12933 vectors = min(phba->cfg_irq_chann, cpu_cnt);
12934
3048e3e8
DK
12935 /* cpu: iterates over aff_mask including offline or online
12936 * cpu_select: iterates over online aff_mask to set affinity
dcaa2136 12937 */
3048e3e8
DK
12938 cpu = cpumask_first(aff_mask);
12939 cpu_select = lpfc_next_online_cpu(aff_mask, cpu);
dcaa2136
JS
12940 } else {
12941 flags |= PCI_IRQ_AFFINITY;
12942 }
12943
12944 rc = pci_alloc_irq_vectors(phba->pcidev, 1, vectors, flags);
4f871e1b 12945 if (rc < 0) {
da0436e9
JS
12946 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12947 "0484 PCI enable MSI-X failed (%d)\n", rc);
029165ac 12948 goto vec_fail_out;
da0436e9 12949 }
4f871e1b 12950 vectors = rc;
75baf696 12951
7bb03bbf 12952 /* Assign MSI-X vectors to interrupt handlers */
67d12733 12953 for (index = 0; index < vectors; index++) {
dcaa2136
JS
12954 eqhdl = lpfc_get_eq_hdl(index);
12955 name = eqhdl->handler_name;
b83d005e
JS
12956 memset(name, 0, LPFC_SLI4_HANDLER_NAME_SZ);
12957 snprintf(name, LPFC_SLI4_HANDLER_NAME_SZ,
4305f183 12958 LPFC_DRIVER_HANDLER_NAME"%d", index);
da0436e9 12959
dcaa2136 12960 eqhdl->idx = index;
7370d10a
JS
12961 rc = request_irq(pci_irq_vector(phba->pcidev, index),
12962 &lpfc_sli4_hba_intr_handler, 0,
dcaa2136 12963 name, eqhdl);
da0436e9
JS
12964 if (rc) {
12965 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
12966 "0486 MSI-X fast-path (%d) "
12967 "request_irq failed (%d)\n", index, rc);
12968 goto cfg_fail_out;
12969 }
dcaa2136
JS
12970
12971 eqhdl->irq = pci_irq_vector(phba->pcidev, index);
12972
3048e3e8 12973 if (aff_mask) {
dcaa2136
JS
12974 /* If found a neighboring online cpu, set affinity */
12975 if (cpu_select < nr_cpu_ids)
12976 lpfc_irq_set_aff(eqhdl, cpu_select);
12977
12978 /* Assign EQ to cpu_map */
12979 lpfc_assign_eq_map_info(phba, index,
12980 LPFC_CPU_FIRST_IRQ,
12981 cpu);
12982
3048e3e8
DK
12983 /* Iterate to next offline or online cpu in aff_mask */
12984 cpu = cpumask_next(cpu, aff_mask);
dcaa2136 12985
3048e3e8
DK
12986 /* Find next online cpu in aff_mask to set affinity */
12987 cpu_select = lpfc_next_online_cpu(aff_mask, cpu);
dcaa2136
JS
12988 } else if (vectors == 1) {
12989 cpu = cpumask_first(cpu_present_mask);
12990 lpfc_assign_eq_map_info(phba, index, LPFC_CPU_FIRST_IRQ,
12991 cpu);
12992 } else {
12993 maskp = pci_irq_get_affinity(phba->pcidev, index);
12994
dcaa2136
JS
12995 /* Loop through all CPUs associated with vector index */
12996 for_each_cpu_and(cpu, maskp, cpu_present_mask) {
17105d95
DK
12997 cpup = &phba->sli4_hba.cpu_map[cpu];
12998
dcaa2136
JS
12999 /* If this is the first CPU thats assigned to
13000 * this vector, set LPFC_CPU_FIRST_IRQ.
17105d95
DK
13001 *
13002 * With certain platforms its possible that irq
13003 * vectors are affinitized to all the cpu's.
13004 * This can result in each cpu_map.eq to be set
13005 * to the last vector, resulting in overwrite
13006 * of all the previous cpu_map.eq. Ensure that
13007 * each vector receives a place in cpu_map.
13008 * Later call to lpfc_cpu_affinity_check will
13009 * ensure we are nicely balanced out.
dcaa2136 13010 */
17105d95
DK
13011 if (cpup->eq != LPFC_VECTOR_MAP_EMPTY)
13012 continue;
dcaa2136 13013 lpfc_assign_eq_map_info(phba, index,
17105d95 13014 LPFC_CPU_FIRST_IRQ,
dcaa2136 13015 cpu);
17105d95 13016 break;
dcaa2136
JS
13017 }
13018 }
da0436e9
JS
13019 }
13020
6a828b0f 13021 if (vectors != phba->cfg_irq_chann) {
372c187b 13022 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
82c3e9ba
JS
13023 "3238 Reducing IO channels to match number of "
13024 "MSI-X vectors, requested %d got %d\n",
6a828b0f
JS
13025 phba->cfg_irq_chann, vectors);
13026 if (phba->cfg_irq_chann > vectors)
13027 phba->cfg_irq_chann = vectors;
82c3e9ba 13028 }
7bb03bbf 13029
da0436e9
JS
13030 return rc;
13031
13032cfg_fail_out:
13033 /* free the irq already requested */
dcaa2136
JS
13034 for (--index; index >= 0; index--) {
13035 eqhdl = lpfc_get_eq_hdl(index);
13036 lpfc_irq_clear_aff(eqhdl);
dcaa2136
JS
13037 free_irq(eqhdl->irq, eqhdl);
13038 }
da0436e9 13039
da0436e9 13040 /* Unconfigure MSI-X capability structure */
45ffac19 13041 pci_free_irq_vectors(phba->pcidev);
029165ac
AG
13042
13043vec_fail_out:
da0436e9
JS
13044 return rc;
13045}
13046
da0436e9
JS
13047/**
13048 * lpfc_sli4_enable_msi - Enable MSI interrupt mode to SLI-4 device
13049 * @phba: pointer to lpfc hba data structure.
13050 *
13051 * This routine is invoked to enable the MSI interrupt mode to device with
07b1b914
JS
13052 * SLI-4 interface spec. The kernel function pci_alloc_irq_vectors() is
13053 * called to enable the MSI vector. The device driver is responsible for
13054 * calling the request_irq() to register MSI vector with a interrupt the
13055 * handler, which is done in this function.
da0436e9
JS
13056 *
13057 * Return codes
af901ca1 13058 * 0 - successful
da0436e9
JS
13059 * other values - error
13060 **/
13061static int
13062lpfc_sli4_enable_msi(struct lpfc_hba *phba)
13063{
13064 int rc, index;
dcaa2136
JS
13065 unsigned int cpu;
13066 struct lpfc_hba_eq_hdl *eqhdl;
da0436e9 13067
07b1b914
JS
13068 rc = pci_alloc_irq_vectors(phba->pcidev, 1, 1,
13069 PCI_IRQ_MSI | PCI_IRQ_AFFINITY);
13070 if (rc > 0)
da0436e9
JS
13071 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
13072 "0487 PCI enable MSI mode success.\n");
13073 else {
13074 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
13075 "0488 PCI enable MSI mode failed (%d)\n", rc);
07b1b914 13076 return rc ? rc : -1;
da0436e9
JS
13077 }
13078
13079 rc = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
ed243d37 13080 0, LPFC_DRIVER_NAME, phba);
da0436e9 13081 if (rc) {
07b1b914 13082 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
13083 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
13084 "0490 MSI request_irq failed (%d)\n", rc);
75baf696 13085 return rc;
da0436e9
JS
13086 }
13087
dcaa2136
JS
13088 eqhdl = lpfc_get_eq_hdl(0);
13089 eqhdl->irq = pci_irq_vector(phba->pcidev, 0);
13090
13091 cpu = cpumask_first(cpu_present_mask);
13092 lpfc_assign_eq_map_info(phba, 0, LPFC_CPU_FIRST_IRQ, cpu);
13093
6a828b0f 13094 for (index = 0; index < phba->cfg_irq_chann; index++) {
dcaa2136
JS
13095 eqhdl = lpfc_get_eq_hdl(index);
13096 eqhdl->idx = index;
da0436e9
JS
13097 }
13098
75baf696 13099 return 0;
da0436e9
JS
13100}
13101
da0436e9
JS
13102/**
13103 * lpfc_sli4_enable_intr - Enable device interrupt to SLI-4 device
13104 * @phba: pointer to lpfc hba data structure.
fe614acd 13105 * @cfg_mode: Interrupt configuration mode (INTx, MSI or MSI-X).
da0436e9
JS
13106 *
13107 * This routine is invoked to enable device interrupt and associate driver's
13108 * interrupt handler(s) to interrupt vector(s) to device with SLI-4
13109 * interface spec. Depends on the interrupt mode configured to the driver,
13110 * the driver will try to fallback from the configured interrupt mode to an
13111 * interrupt mode which is supported by the platform, kernel, and device in
13112 * the order of:
13113 * MSI-X -> MSI -> IRQ.
13114 *
13115 * Return codes
af901ca1 13116 * 0 - successful
da0436e9
JS
13117 * other values - error
13118 **/
13119static uint32_t
13120lpfc_sli4_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
13121{
13122 uint32_t intr_mode = LPFC_INTR_ERROR;
895427bd 13123 int retval, idx;
da0436e9
JS
13124
13125 if (cfg_mode == 2) {
13126 /* Preparation before conf_msi mbox cmd */
13127 retval = 0;
13128 if (!retval) {
13129 /* Now, try to enable MSI-X interrupt mode */
13130 retval = lpfc_sli4_enable_msix(phba);
13131 if (!retval) {
13132 /* Indicate initialization to MSI-X mode */
13133 phba->intr_type = MSIX;
13134 intr_mode = 2;
13135 }
13136 }
13137 }
13138
13139 /* Fallback to MSI if MSI-X initialization failed */
13140 if (cfg_mode >= 1 && phba->intr_type == NONE) {
13141 retval = lpfc_sli4_enable_msi(phba);
13142 if (!retval) {
13143 /* Indicate initialization to MSI mode */
13144 phba->intr_type = MSI;
13145 intr_mode = 1;
13146 }
13147 }
13148
13149 /* Fallback to INTx if both MSI-X/MSI initalization failed */
13150 if (phba->intr_type == NONE) {
13151 retval = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
13152 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
13153 if (!retval) {
895427bd 13154 struct lpfc_hba_eq_hdl *eqhdl;
dcaa2136 13155 unsigned int cpu;
895427bd 13156
da0436e9
JS
13157 /* Indicate initialization to INTx mode */
13158 phba->intr_type = INTx;
13159 intr_mode = 0;
895427bd 13160
dcaa2136
JS
13161 eqhdl = lpfc_get_eq_hdl(0);
13162 eqhdl->irq = pci_irq_vector(phba->pcidev, 0);
13163
13164 cpu = cpumask_first(cpu_present_mask);
13165 lpfc_assign_eq_map_info(phba, 0, LPFC_CPU_FIRST_IRQ,
13166 cpu);
6a828b0f 13167 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
dcaa2136 13168 eqhdl = lpfc_get_eq_hdl(idx);
895427bd 13169 eqhdl->idx = idx;
1ba981fd 13170 }
da0436e9
JS
13171 }
13172 }
13173 return intr_mode;
13174}
13175
13176/**
13177 * lpfc_sli4_disable_intr - Disable device interrupt to SLI-4 device
13178 * @phba: pointer to lpfc hba data structure.
13179 *
13180 * This routine is invoked to disable device interrupt and disassociate
13181 * the driver's interrupt handler(s) from interrupt vector(s) to device
13182 * with SLI-4 interface spec. Depending on the interrupt mode, the driver
13183 * will release the interrupt vector(s) for the message signaled interrupt.
13184 **/
13185static void
13186lpfc_sli4_disable_intr(struct lpfc_hba *phba)
13187{
13188 /* Disable the currently initialized interrupt mode */
45ffac19
CH
13189 if (phba->intr_type == MSIX) {
13190 int index;
dcaa2136 13191 struct lpfc_hba_eq_hdl *eqhdl;
45ffac19
CH
13192
13193 /* Free up MSI-X multi-message vectors */
6a828b0f 13194 for (index = 0; index < phba->cfg_irq_chann; index++) {
dcaa2136
JS
13195 eqhdl = lpfc_get_eq_hdl(index);
13196 lpfc_irq_clear_aff(eqhdl);
dcaa2136 13197 free_irq(eqhdl->irq, eqhdl);
b3295c2a 13198 }
45ffac19 13199 } else {
da0436e9 13200 free_irq(phba->pcidev->irq, phba);
45ffac19
CH
13201 }
13202
13203 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
13204
13205 /* Reset interrupt management states */
13206 phba->intr_type = NONE;
13207 phba->sli.slistat.sli_intr = 0;
da0436e9
JS
13208}
13209
13210/**
13211 * lpfc_unset_hba - Unset SLI3 hba device initialization
13212 * @phba: pointer to lpfc hba data structure.
13213 *
13214 * This routine is invoked to unset the HBA device initialization steps to
13215 * a device with SLI-3 interface spec.
13216 **/
13217static void
13218lpfc_unset_hba(struct lpfc_hba *phba)
13219{
13220 struct lpfc_vport *vport = phba->pport;
13221 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
13222
13223 spin_lock_irq(shost->host_lock);
13224 vport->load_flag |= FC_UNLOADING;
13225 spin_unlock_irq(shost->host_lock);
13226
72859909
JS
13227 kfree(phba->vpi_bmask);
13228 kfree(phba->vpi_ids);
13229
da0436e9
JS
13230 lpfc_stop_hba_timers(phba);
13231
13232 phba->pport->work_port_events = 0;
13233
13234 lpfc_sli_hba_down(phba);
13235
13236 lpfc_sli_brdrestart(phba);
13237
13238 lpfc_sli_disable_intr(phba);
13239
13240 return;
13241}
13242
5af5eee7
JS
13243/**
13244 * lpfc_sli4_xri_exchange_busy_wait - Wait for device XRI exchange busy
13245 * @phba: Pointer to HBA context object.
13246 *
13247 * This function is called in the SLI4 code path to wait for completion
13248 * of device's XRIs exchange busy. It will check the XRI exchange busy
13249 * on outstanding FCP and ELS I/Os every 10ms for up to 10 seconds; after
13250 * that, it will check the XRI exchange busy on outstanding FCP and ELS
13251 * I/Os every 30 seconds, log error message, and wait forever. Only when
13252 * all XRI exchange busy complete, the driver unload shall proceed with
13253 * invoking the function reset ioctl mailbox command to the CNA and the
13254 * the rest of the driver unload resource release.
13255 **/
13256static void
13257lpfc_sli4_xri_exchange_busy_wait(struct lpfc_hba *phba)
13258{
5e5b511d 13259 struct lpfc_sli4_hdw_queue *qp;
c00f62e6 13260 int idx, ccnt;
5af5eee7 13261 int wait_time = 0;
5e5b511d 13262 int io_xri_cmpl = 1;
86c67379 13263 int nvmet_xri_cmpl = 1;
5af5eee7
JS
13264 int els_xri_cmpl = list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
13265
c3725bdc
JS
13266 /* Driver just aborted IOs during the hba_unset process. Pause
13267 * here to give the HBA time to complete the IO and get entries
13268 * into the abts lists.
13269 */
13270 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1 * 5);
13271
13272 /* Wait for NVME pending IO to flush back to transport. */
13273 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
13274 lpfc_nvme_wait_for_io_drain(phba);
13275
5e5b511d 13276 ccnt = 0;
5e5b511d
JS
13277 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
13278 qp = &phba->sli4_hba.hdwq[idx];
c00f62e6
JS
13279 io_xri_cmpl = list_empty(&qp->lpfc_abts_io_buf_list);
13280 if (!io_xri_cmpl) /* if list is NOT empty */
13281 ccnt++;
5e5b511d
JS
13282 }
13283 if (ccnt)
13284 io_xri_cmpl = 0;
5e5b511d 13285
86c67379 13286 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
86c67379
JS
13287 nvmet_xri_cmpl =
13288 list_empty(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
13289 }
895427bd 13290
c00f62e6 13291 while (!els_xri_cmpl || !io_xri_cmpl || !nvmet_xri_cmpl) {
5af5eee7 13292 if (wait_time > LPFC_XRI_EXCH_BUSY_WAIT_TMO) {
68c9b55d 13293 if (!nvmet_xri_cmpl)
372c187b 13294 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
68c9b55d
JS
13295 "6424 NVMET XRI exchange busy "
13296 "wait time: %d seconds.\n",
13297 wait_time/1000);
5e5b511d 13298 if (!io_xri_cmpl)
372c187b 13299 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
c00f62e6 13300 "6100 IO XRI exchange busy "
5af5eee7
JS
13301 "wait time: %d seconds.\n",
13302 wait_time/1000);
13303 if (!els_xri_cmpl)
372c187b 13304 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5af5eee7
JS
13305 "2878 ELS XRI exchange busy "
13306 "wait time: %d seconds.\n",
13307 wait_time/1000);
13308 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T2);
13309 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T2;
13310 } else {
13311 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1);
13312 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T1;
13313 }
5e5b511d
JS
13314
13315 ccnt = 0;
5e5b511d
JS
13316 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
13317 qp = &phba->sli4_hba.hdwq[idx];
c00f62e6
JS
13318 io_xri_cmpl = list_empty(
13319 &qp->lpfc_abts_io_buf_list);
13320 if (!io_xri_cmpl) /* if list is NOT empty */
13321 ccnt++;
5e5b511d
JS
13322 }
13323 if (ccnt)
13324 io_xri_cmpl = 0;
5e5b511d 13325
86c67379 13326 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
86c67379
JS
13327 nvmet_xri_cmpl = list_empty(
13328 &phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
13329 }
5af5eee7
JS
13330 els_xri_cmpl =
13331 list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
f358dd0c 13332
5af5eee7
JS
13333 }
13334}
13335
da0436e9
JS
13336/**
13337 * lpfc_sli4_hba_unset - Unset the fcoe hba
13338 * @phba: Pointer to HBA context object.
13339 *
13340 * This function is called in the SLI4 code path to reset the HBA's FCoE
13341 * function. The caller is not required to hold any lock. This routine
13342 * issues PCI function reset mailbox command to reset the FCoE function.
13343 * At the end of the function, it calls lpfc_hba_down_post function to
13344 * free any pending commands.
13345 **/
13346static void
13347lpfc_sli4_hba_unset(struct lpfc_hba *phba)
13348{
13349 int wait_cnt = 0;
13350 LPFC_MBOXQ_t *mboxq;
912e3acd 13351 struct pci_dev *pdev = phba->pcidev;
da0436e9
JS
13352
13353 lpfc_stop_hba_timers(phba);
02243836
JS
13354 hrtimer_cancel(&phba->cmf_timer);
13355
cdb42bec
JS
13356 if (phba->pport)
13357 phba->sli4_hba.intr_enable = 0;
da0436e9
JS
13358
13359 /*
13360 * Gracefully wait out the potential current outstanding asynchronous
13361 * mailbox command.
13362 */
13363
13364 /* First, block any pending async mailbox command from posted */
13365 spin_lock_irq(&phba->hbalock);
13366 phba->sli.sli_flag |= LPFC_SLI_ASYNC_MBX_BLK;
13367 spin_unlock_irq(&phba->hbalock);
13368 /* Now, trying to wait it out if we can */
13369 while (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
13370 msleep(10);
13371 if (++wait_cnt > LPFC_ACTIVE_MBOX_WAIT_CNT)
13372 break;
13373 }
13374 /* Forcefully release the outstanding mailbox command if timed out */
13375 if (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
13376 spin_lock_irq(&phba->hbalock);
13377 mboxq = phba->sli.mbox_active;
13378 mboxq->u.mb.mbxStatus = MBX_NOT_FINISHED;
13379 __lpfc_mbox_cmpl_put(phba, mboxq);
13380 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
13381 phba->sli.mbox_active = NULL;
13382 spin_unlock_irq(&phba->hbalock);
13383 }
13384
5af5eee7
JS
13385 /* Abort all iocbs associated with the hba */
13386 lpfc_sli_hba_iocb_abort(phba);
13387
a4691038
JS
13388 if (!pci_channel_offline(phba->pcidev))
13389 /* Wait for completion of device XRI exchange busy */
13390 lpfc_sli4_xri_exchange_busy_wait(phba);
5af5eee7 13391
93a4d6f4 13392 /* per-phba callback de-registration for hotplug event */
46da547e
SP
13393 if (phba->pport)
13394 lpfc_cpuhp_remove(phba);
93a4d6f4 13395
da0436e9
JS
13396 /* Disable PCI subsystem interrupt */
13397 lpfc_sli4_disable_intr(phba);
13398
912e3acd
JS
13399 /* Disable SR-IOV if enabled */
13400 if (phba->cfg_sriov_nr_virtfn)
13401 pci_disable_sriov(pdev);
13402
da0436e9
JS
13403 /* Stop kthread signal shall trigger work_done one more time */
13404 kthread_stop(phba->worker_thread);
13405
d2cc9bcd 13406 /* Disable FW logging to host memory */
1165a5c2 13407 lpfc_ras_stop_fwlog(phba);
d2cc9bcd 13408
3677a3a7
JS
13409 /* Reset SLI4 HBA FCoE function */
13410 lpfc_pci_function_reset(phba);
13411
35ed9613
JS
13412 /* release all queue allocated resources. */
13413 lpfc_sli4_queue_destroy(phba);
13414
1165a5c2
JS
13415 /* Free RAS DMA memory */
13416 if (phba->ras_fwlog.ras_enabled)
13417 lpfc_sli4_ras_dma_free(phba);
13418
da0436e9 13419 /* Stop the SLI4 device port */
1ffdd2c0
JS
13420 if (phba->pport)
13421 phba->pport->work_port_events = 0;
da0436e9
JS
13422}
13423
7481811c
JS
13424static uint32_t
13425lpfc_cgn_crc32(uint32_t crc, u8 byte)
13426{
13427 uint32_t msb = 0;
13428 uint32_t bit;
13429
13430 for (bit = 0; bit < 8; bit++) {
13431 msb = (crc >> 31) & 1;
13432 crc <<= 1;
13433
13434 if (msb ^ (byte & 1)) {
13435 crc ^= LPFC_CGN_CRC32_MAGIC_NUMBER;
13436 crc |= 1;
13437 }
13438 byte >>= 1;
13439 }
13440 return crc;
13441}
13442
13443static uint32_t
13444lpfc_cgn_reverse_bits(uint32_t wd)
13445{
13446 uint32_t result = 0;
13447 uint32_t i;
13448
13449 for (i = 0; i < 32; i++) {
13450 result <<= 1;
13451 result |= (1 & (wd >> i));
13452 }
13453 return result;
13454}
13455
13456/*
13457 * The routine corresponds with the algorithm the HBA firmware
13458 * uses to validate the data integrity.
13459 */
13460uint32_t
13461lpfc_cgn_calc_crc32(void *ptr, uint32_t byteLen, uint32_t crc)
13462{
13463 uint32_t i;
13464 uint32_t result;
13465 uint8_t *data = (uint8_t *)ptr;
13466
13467 for (i = 0; i < byteLen; ++i)
13468 crc = lpfc_cgn_crc32(crc, data[i]);
13469
13470 result = ~lpfc_cgn_reverse_bits(crc);
13471 return result;
13472}
13473
8c42a65c
JS
13474void
13475lpfc_init_congestion_buf(struct lpfc_hba *phba)
13476{
7481811c
JS
13477 struct lpfc_cgn_info *cp;
13478 struct timespec64 cmpl_time;
13479 struct tm broken;
13480 uint16_t size;
13481 uint32_t crc;
13482
8c42a65c
JS
13483 lpfc_printf_log(phba, KERN_INFO, LOG_CGN_MGMT,
13484 "6235 INIT Congestion Buffer %p\n", phba->cgn_i);
13485
13486 if (!phba->cgn_i)
13487 return;
7481811c 13488 cp = (struct lpfc_cgn_info *)phba->cgn_i->virt;
8c42a65c
JS
13489
13490 atomic_set(&phba->cgn_fabric_warn_cnt, 0);
13491 atomic_set(&phba->cgn_fabric_alarm_cnt, 0);
13492 atomic_set(&phba->cgn_sync_alarm_cnt, 0);
13493 atomic_set(&phba->cgn_sync_warn_cnt, 0);
13494
8c42a65c
JS
13495 atomic_set(&phba->cgn_driver_evt_cnt, 0);
13496 atomic_set(&phba->cgn_latency_evt_cnt, 0);
13497 atomic64_set(&phba->cgn_latency_evt, 0);
13498 phba->cgn_evt_minute = 0;
7481811c
JS
13499 phba->hba_flag &= ~HBA_CGN_DAY_WRAP;
13500
532adda9 13501 memset(cp, 0xff, offsetof(struct lpfc_cgn_info, cgn_stat));
7481811c
JS
13502 cp->cgn_info_size = cpu_to_le16(LPFC_CGN_INFO_SZ);
13503 cp->cgn_info_version = LPFC_CGN_INFO_V3;
13504
13505 /* cgn parameters */
13506 cp->cgn_info_mode = phba->cgn_p.cgn_param_mode;
13507 cp->cgn_info_level0 = phba->cgn_p.cgn_param_level0;
13508 cp->cgn_info_level1 = phba->cgn_p.cgn_param_level1;
13509 cp->cgn_info_level2 = phba->cgn_p.cgn_param_level2;
13510
13511 ktime_get_real_ts64(&cmpl_time);
13512 time64_to_tm(cmpl_time.tv_sec, 0, &broken);
13513
13514 cp->cgn_info_month = broken.tm_mon + 1;
13515 cp->cgn_info_day = broken.tm_mday;
13516 cp->cgn_info_year = broken.tm_year - 100; /* relative to 2000 */
13517 cp->cgn_info_hour = broken.tm_hour;
13518 cp->cgn_info_minute = broken.tm_min;
13519 cp->cgn_info_second = broken.tm_sec;
13520
13521 lpfc_printf_log(phba, KERN_INFO, LOG_CGN_MGMT | LOG_INIT,
13522 "2643 CGNInfo Init: Start Time "
13523 "%d/%d/%d %d:%d:%d\n",
13524 cp->cgn_info_day, cp->cgn_info_month,
13525 cp->cgn_info_year, cp->cgn_info_hour,
13526 cp->cgn_info_minute, cp->cgn_info_second);
13527
13528 /* Fill in default LUN qdepth */
13529 if (phba->pport) {
13530 size = (uint16_t)(phba->pport->cfg_lun_queue_depth);
13531 cp->cgn_lunq = cpu_to_le16(size);
13532 }
13533
13534 /* last used Index initialized to 0xff already */
13535
59936430
JS
13536 cp->cgn_warn_freq = cpu_to_le16(LPFC_FPIN_INIT_FREQ);
13537 cp->cgn_alarm_freq = cpu_to_le16(LPFC_FPIN_INIT_FREQ);
7481811c
JS
13538 crc = lpfc_cgn_calc_crc32(cp, LPFC_CGN_INFO_SZ, LPFC_CGN_CRC32_SEED);
13539 cp->cgn_info_crc = cpu_to_le32(crc);
8c42a65c
JS
13540
13541 phba->cgn_evt_timestamp = jiffies +
13542 msecs_to_jiffies(LPFC_CGN_TIMER_TO_MIN);
13543}
13544
13545void
13546lpfc_init_congestion_stat(struct lpfc_hba *phba)
13547{
7481811c
JS
13548 struct lpfc_cgn_info *cp;
13549 struct timespec64 cmpl_time;
13550 struct tm broken;
13551 uint32_t crc;
13552
8c42a65c
JS
13553 lpfc_printf_log(phba, KERN_INFO, LOG_CGN_MGMT,
13554 "6236 INIT Congestion Stat %p\n", phba->cgn_i);
13555
13556 if (!phba->cgn_i)
13557 return;
7481811c
JS
13558
13559 cp = (struct lpfc_cgn_info *)phba->cgn_i->virt;
532adda9 13560 memset(&cp->cgn_stat, 0, sizeof(cp->cgn_stat));
7481811c
JS
13561
13562 ktime_get_real_ts64(&cmpl_time);
13563 time64_to_tm(cmpl_time.tv_sec, 0, &broken);
13564
13565 cp->cgn_stat_month = broken.tm_mon + 1;
13566 cp->cgn_stat_day = broken.tm_mday;
13567 cp->cgn_stat_year = broken.tm_year - 100; /* relative to 2000 */
13568 cp->cgn_stat_hour = broken.tm_hour;
13569 cp->cgn_stat_minute = broken.tm_min;
13570
13571 lpfc_printf_log(phba, KERN_INFO, LOG_CGN_MGMT | LOG_INIT,
13572 "2647 CGNstat Init: Start Time "
13573 "%d/%d/%d %d:%d\n",
13574 cp->cgn_stat_day, cp->cgn_stat_month,
13575 cp->cgn_stat_year, cp->cgn_stat_hour,
13576 cp->cgn_stat_minute);
13577
13578 crc = lpfc_cgn_calc_crc32(cp, LPFC_CGN_INFO_SZ, LPFC_CGN_CRC32_SEED);
13579 cp->cgn_info_crc = cpu_to_le32(crc);
8c42a65c
JS
13580}
13581
13582/**
13583 * __lpfc_reg_congestion_buf - register congestion info buffer with HBA
13584 * @phba: Pointer to hba context object.
13585 * @reg: flag to determine register or unregister.
13586 */
13587static int
13588__lpfc_reg_congestion_buf(struct lpfc_hba *phba, int reg)
13589{
13590 struct lpfc_mbx_reg_congestion_buf *reg_congestion_buf;
13591 union lpfc_sli4_cfg_shdr *shdr;
13592 uint32_t shdr_status, shdr_add_status;
13593 LPFC_MBOXQ_t *mboxq;
13594 int length, rc;
13595
13596 if (!phba->cgn_i)
13597 return -ENXIO;
13598
13599 mboxq = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
13600 if (!mboxq) {
13601 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
13602 "2641 REG_CONGESTION_BUF mbox allocation fail: "
13603 "HBA state x%x reg %d\n",
13604 phba->pport->port_state, reg);
13605 return -ENOMEM;
13606 }
13607
13608 length = (sizeof(struct lpfc_mbx_reg_congestion_buf) -
13609 sizeof(struct lpfc_sli4_cfg_mhdr));
13610 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
13611 LPFC_MBOX_OPCODE_REG_CONGESTION_BUF, length,
13612 LPFC_SLI4_MBX_EMBED);
13613 reg_congestion_buf = &mboxq->u.mqe.un.reg_congestion_buf;
13614 bf_set(lpfc_mbx_reg_cgn_buf_type, reg_congestion_buf, 1);
13615 if (reg > 0)
13616 bf_set(lpfc_mbx_reg_cgn_buf_cnt, reg_congestion_buf, 1);
13617 else
13618 bf_set(lpfc_mbx_reg_cgn_buf_cnt, reg_congestion_buf, 0);
13619 reg_congestion_buf->length = sizeof(struct lpfc_cgn_info);
13620 reg_congestion_buf->addr_lo =
13621 putPaddrLow(phba->cgn_i->phys);
13622 reg_congestion_buf->addr_hi =
13623 putPaddrHigh(phba->cgn_i->phys);
13624
13625 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
13626 shdr = (union lpfc_sli4_cfg_shdr *)
13627 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
13628 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
13629 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status,
13630 &shdr->response);
13631 mempool_free(mboxq, phba->mbox_mem_pool);
13632 if (shdr_status || shdr_add_status || rc) {
13633 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13634 "2642 REG_CONGESTION_BUF mailbox "
13635 "failed with status x%x add_status x%x,"
13636 " mbx status x%x reg %d\n",
13637 shdr_status, shdr_add_status, rc, reg);
13638 return -ENXIO;
13639 }
13640 return 0;
13641}
13642
02243836 13643int
8c42a65c
JS
13644lpfc_unreg_congestion_buf(struct lpfc_hba *phba)
13645{
02243836 13646 lpfc_cmf_stop(phba);
8c42a65c
JS
13647 return __lpfc_reg_congestion_buf(phba, 0);
13648}
13649
13650int
13651lpfc_reg_congestion_buf(struct lpfc_hba *phba)
13652{
13653 return __lpfc_reg_congestion_buf(phba, 1);
13654}
13655
fedd3b7b
JS
13656/**
13657 * lpfc_get_sli4_parameters - Get the SLI4 Config PARAMETERS.
13658 * @phba: Pointer to HBA context object.
13659 * @mboxq: Pointer to the mailboxq memory for the mailbox command response.
13660 *
13661 * This function is called in the SLI4 code path to read the port's
13662 * sli4 capabilities.
13663 *
13664 * This function may be be called from any context that can block-wait
13665 * for the completion. The expectation is that this routine is called
13666 * typically from probe_one or from the online routine.
13667 **/
13668int
13669lpfc_get_sli4_parameters(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
13670{
13671 int rc;
13672 struct lpfc_mqe *mqe = &mboxq->u.mqe;
13673 struct lpfc_pc_sli4_params *sli4_params;
a183a15f 13674 uint32_t mbox_tmo;
fedd3b7b 13675 int length;
bf316c78 13676 bool exp_wqcq_pages = true;
fedd3b7b
JS
13677 struct lpfc_sli4_parameters *mbx_sli4_parameters;
13678
6d368e53
JS
13679 /*
13680 * By default, the driver assumes the SLI4 port requires RPI
13681 * header postings. The SLI4_PARAM response will correct this
13682 * assumption.
13683 */
13684 phba->sli4_hba.rpi_hdrs_in_use = 1;
13685
fedd3b7b
JS
13686 /* Read the port's SLI4 Config Parameters */
13687 length = (sizeof(struct lpfc_mbx_get_sli4_parameters) -
13688 sizeof(struct lpfc_sli4_cfg_mhdr));
13689 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
13690 LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS,
13691 length, LPFC_SLI4_MBX_EMBED);
13692 if (!phba->sli4_hba.intr_enable)
13693 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
a183a15f
JS
13694 else {
13695 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
13696 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
13697 }
fedd3b7b
JS
13698 if (unlikely(rc))
13699 return rc;
13700 sli4_params = &phba->sli4_hba.pc_sli4_params;
13701 mbx_sli4_parameters = &mqe->un.get_sli4_parameters.sli4_parameters;
13702 sli4_params->if_type = bf_get(cfg_if_type, mbx_sli4_parameters);
13703 sli4_params->sli_rev = bf_get(cfg_sli_rev, mbx_sli4_parameters);
13704 sli4_params->sli_family = bf_get(cfg_sli_family, mbx_sli4_parameters);
13705 sli4_params->featurelevel_1 = bf_get(cfg_sli_hint_1,
13706 mbx_sli4_parameters);
13707 sli4_params->featurelevel_2 = bf_get(cfg_sli_hint_2,
13708 mbx_sli4_parameters);
13709 if (bf_get(cfg_phwq, mbx_sli4_parameters))
13710 phba->sli3_options |= LPFC_SLI4_PHWQ_ENABLED;
13711 else
13712 phba->sli3_options &= ~LPFC_SLI4_PHWQ_ENABLED;
13713 sli4_params->sge_supp_len = mbx_sli4_parameters->sge_supp_len;
b62232ba
JS
13714 sli4_params->loopbk_scope = bf_get(cfg_loopbk_scope,
13715 mbx_sli4_parameters);
1ba981fd 13716 sli4_params->oas_supported = bf_get(cfg_oas, mbx_sli4_parameters);
fedd3b7b
JS
13717 sli4_params->cqv = bf_get(cfg_cqv, mbx_sli4_parameters);
13718 sli4_params->mqv = bf_get(cfg_mqv, mbx_sli4_parameters);
13719 sli4_params->wqv = bf_get(cfg_wqv, mbx_sli4_parameters);
13720 sli4_params->rqv = bf_get(cfg_rqv, mbx_sli4_parameters);
7365f6fd
JS
13721 sli4_params->eqav = bf_get(cfg_eqav, mbx_sli4_parameters);
13722 sli4_params->cqav = bf_get(cfg_cqav, mbx_sli4_parameters);
0c651878 13723 sli4_params->wqsize = bf_get(cfg_wqsize, mbx_sli4_parameters);
66e9e6bf 13724 sli4_params->bv1s = bf_get(cfg_bv1s, mbx_sli4_parameters);
83c6cb1a 13725 sli4_params->pls = bf_get(cfg_pvl, mbx_sli4_parameters);
fedd3b7b
JS
13726 sli4_params->sgl_pages_max = bf_get(cfg_sgl_page_cnt,
13727 mbx_sli4_parameters);
895427bd 13728 sli4_params->wqpcnt = bf_get(cfg_wqpcnt, mbx_sli4_parameters);
fedd3b7b
JS
13729 sli4_params->sgl_pp_align = bf_get(cfg_sgl_pp_align,
13730 mbx_sli4_parameters);
6d368e53
JS
13731 phba->sli4_hba.extents_in_use = bf_get(cfg_ext, mbx_sli4_parameters);
13732 phba->sli4_hba.rpi_hdrs_in_use = bf_get(cfg_hdrr, mbx_sli4_parameters);
c15e0704 13733
d79c9e9d
JS
13734 /* Check for Extended Pre-Registered SGL support */
13735 phba->cfg_xpsgl = bf_get(cfg_xpsgl, mbx_sli4_parameters);
13736
c15e0704
JS
13737 /* Check for firmware nvme support */
13738 rc = (bf_get(cfg_nvme, mbx_sli4_parameters) &&
13739 bf_get(cfg_xib, mbx_sli4_parameters));
13740
13741 if (rc) {
13742 /* Save this to indicate the Firmware supports NVME */
13743 sli4_params->nvme = 1;
13744
13745 /* Firmware NVME support, check driver FC4 NVME support */
13746 if (phba->cfg_enable_fc4_type == LPFC_ENABLE_FCP) {
13747 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME,
13748 "6133 Disabling NVME support: "
13749 "FC4 type not supported: x%x\n",
13750 phba->cfg_enable_fc4_type);
13751 goto fcponly;
13752 }
13753 } else {
13754 /* No firmware NVME support, check driver FC4 NVME support */
13755 sli4_params->nvme = 0;
13756 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
13757 lpfc_printf_log(phba, KERN_ERR, LOG_INIT | LOG_NVME,
13758 "6101 Disabling NVME support: Not "
13759 "supported by firmware (%d %d) x%x\n",
13760 bf_get(cfg_nvme, mbx_sli4_parameters),
13761 bf_get(cfg_xib, mbx_sli4_parameters),
13762 phba->cfg_enable_fc4_type);
13763fcponly:
c15e0704
JS
13764 phba->nvmet_support = 0;
13765 phba->cfg_nvmet_mrq = 0;
6a224b47 13766 phba->cfg_nvme_seg_cnt = 0;
c15e0704
JS
13767
13768 /* If no FC4 type support, move to just SCSI support */
13769 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
13770 return -ENODEV;
13771 phba->cfg_enable_fc4_type = LPFC_ENABLE_FCP;
13772 }
895427bd 13773 }
0558056c 13774
c26c265b 13775 /* If the NVME FC4 type is enabled, scale the sg_seg_cnt to
a5f7337f 13776 * accommodate 512K and 1M IOs in a single nvme buf.
c26c265b 13777 */
a5f7337f 13778 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
c26c265b 13779 phba->cfg_sg_seg_cnt = LPFC_MAX_NVME_SEG_CNT;
c26c265b 13780
137ddf03
JS
13781 /* Enable embedded Payload BDE if support is indicated */
13782 if (bf_get(cfg_pbde, mbx_sli4_parameters))
13783 phba->cfg_enable_pbde = 1;
13784 else
414abe0a 13785 phba->cfg_enable_pbde = 0;
0bc2b7c5 13786
20aefac3
JS
13787 /*
13788 * To support Suppress Response feature we must satisfy 3 conditions.
13789 * lpfc_suppress_rsp module parameter must be set (default).
13790 * In SLI4-Parameters Descriptor:
13791 * Extended Inline Buffers (XIB) must be supported.
13792 * Suppress Response IU Not Supported (SRIUNS) must NOT be supported
13793 * (double negative).
13794 */
13795 if (phba->cfg_suppress_rsp && bf_get(cfg_xib, mbx_sli4_parameters) &&
13796 !(bf_get(cfg_nosr, mbx_sli4_parameters)))
f358dd0c 13797 phba->sli.sli_flag |= LPFC_SLI_SUPPRESS_RSP;
20aefac3
JS
13798 else
13799 phba->cfg_suppress_rsp = 0;
f358dd0c 13800
0cf07f84
JS
13801 if (bf_get(cfg_eqdr, mbx_sli4_parameters))
13802 phba->sli.sli_flag |= LPFC_SLI_USE_EQDR;
13803
0558056c
JS
13804 /* Make sure that sge_supp_len can be handled by the driver */
13805 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
13806 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
13807
b5c53958 13808 /*
c176ffa0
JS
13809 * Check whether the adapter supports an embedded copy of the
13810 * FCP CMD IU within the WQE for FCP_Ixxx commands. In order
13811 * to use this option, 128-byte WQEs must be used.
b5c53958
JS
13812 */
13813 if (bf_get(cfg_ext_embed_cb, mbx_sli4_parameters))
13814 phba->fcp_embed_io = 1;
13815 else
13816 phba->fcp_embed_io = 0;
7bdedb34 13817
0bc2b7c5 13818 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME,
414abe0a 13819 "6422 XIB %d PBDE %d: FCP %d NVME %d %d %d\n",
0bc2b7c5 13820 bf_get(cfg_xib, mbx_sli4_parameters),
414abe0a 13821 phba->cfg_enable_pbde,
ae463b60 13822 phba->fcp_embed_io, sli4_params->nvme,
4e565cf0 13823 phba->cfg_nvme_embed_cmd, phba->cfg_suppress_rsp);
0bc2b7c5 13824
bf316c78
JS
13825 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
13826 LPFC_SLI_INTF_IF_TYPE_2) &&
13827 (bf_get(lpfc_sli_intf_sli_family, &phba->sli4_hba.sli_intf) ==
c221768b 13828 LPFC_SLI_INTF_FAMILY_LNCR_A0))
bf316c78
JS
13829 exp_wqcq_pages = false;
13830
c176ffa0
JS
13831 if ((bf_get(cfg_cqpsize, mbx_sli4_parameters) & LPFC_CQ_16K_PAGE_SZ) &&
13832 (bf_get(cfg_wqpsize, mbx_sli4_parameters) & LPFC_WQ_16K_PAGE_SZ) &&
bf316c78 13833 exp_wqcq_pages &&
c176ffa0
JS
13834 (sli4_params->wqsize & LPFC_WQ_SZ128_SUPPORT))
13835 phba->enab_exp_wqcq_pages = 1;
13836 else
13837 phba->enab_exp_wqcq_pages = 0;
7bdedb34
JS
13838 /*
13839 * Check if the SLI port supports MDS Diagnostics
13840 */
13841 if (bf_get(cfg_mds_diags, mbx_sli4_parameters))
13842 phba->mds_diags_support = 1;
13843 else
13844 phba->mds_diags_support = 0;
d2cc9bcd 13845
0d8af096
JS
13846 /*
13847 * Check if the SLI port supports NSLER
13848 */
13849 if (bf_get(cfg_nsler, mbx_sli4_parameters))
13850 phba->nsler = 1;
13851 else
13852 phba->nsler = 0;
13853
fedd3b7b
JS
13854 return 0;
13855}
13856
da0436e9
JS
13857/**
13858 * lpfc_pci_probe_one_s3 - PCI probe func to reg SLI-3 device to PCI subsystem.
13859 * @pdev: pointer to PCI device
13860 * @pid: pointer to PCI device identifier
13861 *
13862 * This routine is to be called to attach a device with SLI-3 interface spec
13863 * to the PCI subsystem. When an Emulex HBA with SLI-3 interface spec is
13864 * presented on PCI bus, the kernel PCI subsystem looks at PCI device-specific
13865 * information of the device and driver to see if the driver state that it can
13866 * support this kind of device. If the match is successful, the driver core
13867 * invokes this routine. If this routine determines it can claim the HBA, it
13868 * does all the initialization that it needs to do to handle the HBA properly.
13869 *
13870 * Return code
13871 * 0 - driver can claim the device
13872 * negative value - driver can not claim the device
13873 **/
6f039790 13874static int
da0436e9
JS
13875lpfc_pci_probe_one_s3(struct pci_dev *pdev, const struct pci_device_id *pid)
13876{
13877 struct lpfc_hba *phba;
13878 struct lpfc_vport *vport = NULL;
6669f9bb 13879 struct Scsi_Host *shost = NULL;
da0436e9
JS
13880 int error;
13881 uint32_t cfg_mode, intr_mode;
13882
13883 /* Allocate memory for HBA structure */
13884 phba = lpfc_hba_alloc(pdev);
13885 if (!phba)
13886 return -ENOMEM;
13887
13888 /* Perform generic PCI device enabling operation */
13889 error = lpfc_enable_pci_dev(phba);
079b5c91 13890 if (error)
da0436e9 13891 goto out_free_phba;
da0436e9
JS
13892
13893 /* Set up SLI API function jump table for PCI-device group-0 HBAs */
13894 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_LP);
13895 if (error)
13896 goto out_disable_pci_dev;
13897
13898 /* Set up SLI-3 specific device PCI memory space */
13899 error = lpfc_sli_pci_mem_setup(phba);
13900 if (error) {
13901 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13902 "1402 Failed to set up pci memory space.\n");
13903 goto out_disable_pci_dev;
13904 }
13905
da0436e9
JS
13906 /* Set up SLI-3 specific device driver resources */
13907 error = lpfc_sli_driver_resource_setup(phba);
13908 if (error) {
13909 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13910 "1404 Failed to set up driver resource.\n");
13911 goto out_unset_pci_mem_s3;
13912 }
13913
13914 /* Initialize and populate the iocb list per host */
d1f525aa 13915
da0436e9
JS
13916 error = lpfc_init_iocb_list(phba, LPFC_IOCB_LIST_CNT);
13917 if (error) {
13918 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13919 "1405 Failed to initialize iocb list.\n");
13920 goto out_unset_driver_resource_s3;
13921 }
13922
13923 /* Set up common device driver resources */
13924 error = lpfc_setup_driver_resource_phase2(phba);
13925 if (error) {
13926 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13927 "1406 Failed to set up driver resource.\n");
13928 goto out_free_iocb_list;
13929 }
13930
079b5c91
JS
13931 /* Get the default values for Model Name and Description */
13932 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
13933
da0436e9
JS
13934 /* Create SCSI host to the physical port */
13935 error = lpfc_create_shost(phba);
13936 if (error) {
13937 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13938 "1407 Failed to create scsi host.\n");
13939 goto out_unset_driver_resource;
13940 }
13941
13942 /* Configure sysfs attributes */
13943 vport = phba->pport;
13944 error = lpfc_alloc_sysfs_attr(vport);
13945 if (error) {
13946 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13947 "1476 Failed to allocate sysfs attr\n");
13948 goto out_destroy_shost;
13949 }
13950
6669f9bb 13951 shost = lpfc_shost_from_vport(vport); /* save shost for error cleanup */
da0436e9
JS
13952 /* Now, trying to enable interrupt and bring up the device */
13953 cfg_mode = phba->cfg_use_msi;
13954 while (true) {
13955 /* Put device to a known state before enabling interrupt */
13956 lpfc_stop_port(phba);
13957 /* Configure and enable interrupt */
13958 intr_mode = lpfc_sli_enable_intr(phba, cfg_mode);
13959 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 13960 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
13961 "0431 Failed to enable interrupt.\n");
13962 error = -ENODEV;
13963 goto out_free_sysfs_attr;
13964 }
13965 /* SLI-3 HBA setup */
13966 if (lpfc_sli_hba_setup(phba)) {
372c187b 13967 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
13968 "1477 Failed to set up hba\n");
13969 error = -ENODEV;
13970 goto out_remove_device;
13971 }
13972
13973 /* Wait 50ms for the interrupts of previous mailbox commands */
13974 msleep(50);
13975 /* Check active interrupts on message signaled interrupts */
13976 if (intr_mode == 0 ||
13977 phba->sli.slistat.sli_intr > LPFC_MSIX_VECTORS) {
13978 /* Log the current active interrupt mode */
13979 phba->intr_mode = intr_mode;
13980 lpfc_log_intr_mode(phba, intr_mode);
13981 break;
13982 } else {
13983 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
13984 "0447 Configure interrupt mode (%d) "
13985 "failed active interrupt test.\n",
13986 intr_mode);
13987 /* Disable the current interrupt mode */
13988 lpfc_sli_disable_intr(phba);
13989 /* Try next level of interrupt mode */
13990 cfg_mode = --intr_mode;
13991 }
13992 }
13993
13994 /* Perform post initialization setup */
13995 lpfc_post_init_setup(phba);
13996
13997 /* Check if there are static vports to be created. */
13998 lpfc_create_static_vport(phba);
13999
14000 return 0;
14001
14002out_remove_device:
14003 lpfc_unset_hba(phba);
14004out_free_sysfs_attr:
14005 lpfc_free_sysfs_attr(vport);
14006out_destroy_shost:
14007 lpfc_destroy_shost(phba);
14008out_unset_driver_resource:
14009 lpfc_unset_driver_resource_phase2(phba);
14010out_free_iocb_list:
14011 lpfc_free_iocb_list(phba);
14012out_unset_driver_resource_s3:
14013 lpfc_sli_driver_resource_unset(phba);
14014out_unset_pci_mem_s3:
14015 lpfc_sli_pci_mem_unset(phba);
14016out_disable_pci_dev:
14017 lpfc_disable_pci_dev(phba);
6669f9bb
JS
14018 if (shost)
14019 scsi_host_put(shost);
da0436e9
JS
14020out_free_phba:
14021 lpfc_hba_free(phba);
14022 return error;
14023}
14024
14025/**
14026 * lpfc_pci_remove_one_s3 - PCI func to unreg SLI-3 device from PCI subsystem.
14027 * @pdev: pointer to PCI device
14028 *
14029 * This routine is to be called to disattach a device with SLI-3 interface
14030 * spec from PCI subsystem. When an Emulex HBA with SLI-3 interface spec is
14031 * removed from PCI bus, it performs all the necessary cleanup for the HBA
14032 * device to be removed from the PCI subsystem properly.
14033 **/
6f039790 14034static void
da0436e9
JS
14035lpfc_pci_remove_one_s3(struct pci_dev *pdev)
14036{
14037 struct Scsi_Host *shost = pci_get_drvdata(pdev);
14038 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
14039 struct lpfc_vport **vports;
14040 struct lpfc_hba *phba = vport->phba;
14041 int i;
da0436e9
JS
14042
14043 spin_lock_irq(&phba->hbalock);
14044 vport->load_flag |= FC_UNLOADING;
14045 spin_unlock_irq(&phba->hbalock);
14046
14047 lpfc_free_sysfs_attr(vport);
14048
14049 /* Release all the vports against this physical port */
14050 vports = lpfc_create_vport_work_array(phba);
14051 if (vports != NULL)
587a37f6
JS
14052 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
14053 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
14054 continue;
da0436e9 14055 fc_vport_terminate(vports[i]->fc_vport);
587a37f6 14056 }
da0436e9
JS
14057 lpfc_destroy_vport_work_array(phba, vports);
14058
95f0ef8a 14059 /* Remove FC host with the physical port */
da0436e9 14060 fc_remove_host(shost);
e9b11083 14061 scsi_remove_host(shost);
d613b6a7 14062
95f0ef8a 14063 /* Clean up all nodes, mailboxes and IOs. */
da0436e9
JS
14064 lpfc_cleanup(vport);
14065
14066 /*
14067 * Bring down the SLI Layer. This step disable all interrupts,
14068 * clears the rings, discards all mailbox commands, and resets
14069 * the HBA.
14070 */
14071
48e34d0f 14072 /* HBA interrupt will be disabled after this call */
da0436e9
JS
14073 lpfc_sli_hba_down(phba);
14074 /* Stop kthread signal shall trigger work_done one more time */
14075 kthread_stop(phba->worker_thread);
14076 /* Final cleanup of txcmplq and reset the HBA */
14077 lpfc_sli_brdrestart(phba);
14078
72859909
JS
14079 kfree(phba->vpi_bmask);
14080 kfree(phba->vpi_ids);
14081
da0436e9 14082 lpfc_stop_hba_timers(phba);
523128e5 14083 spin_lock_irq(&phba->port_list_lock);
da0436e9 14084 list_del_init(&vport->listentry);
523128e5 14085 spin_unlock_irq(&phba->port_list_lock);
da0436e9
JS
14086
14087 lpfc_debugfs_terminate(vport);
14088
912e3acd
JS
14089 /* Disable SR-IOV if enabled */
14090 if (phba->cfg_sriov_nr_virtfn)
14091 pci_disable_sriov(pdev);
14092
da0436e9
JS
14093 /* Disable interrupt */
14094 lpfc_sli_disable_intr(phba);
14095
da0436e9
JS
14096 scsi_host_put(shost);
14097
14098 /*
14099 * Call scsi_free before mem_free since scsi bufs are released to their
14100 * corresponding pools here.
14101 */
14102 lpfc_scsi_free(phba);
0794d601
JS
14103 lpfc_free_iocb_list(phba);
14104
da0436e9
JS
14105 lpfc_mem_free_all(phba);
14106
14107 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
14108 phba->hbqslimp.virt, phba->hbqslimp.phys);
14109
14110 /* Free resources associated with SLI2 interface */
14111 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
14112 phba->slim2p.virt, phba->slim2p.phys);
14113
14114 /* unmap adapter SLIM and Control Registers */
14115 iounmap(phba->ctrl_regs_memmap_p);
14116 iounmap(phba->slim_memmap_p);
14117
14118 lpfc_hba_free(phba);
14119
e0c0483c 14120 pci_release_mem_regions(pdev);
da0436e9
JS
14121 pci_disable_device(pdev);
14122}
14123
14124/**
14125 * lpfc_pci_suspend_one_s3 - PCI func to suspend SLI-3 device for power mgmnt
ef6fa16b 14126 * @dev_d: pointer to device
da0436e9
JS
14127 *
14128 * This routine is to be called from the kernel's PCI subsystem to support
14129 * system Power Management (PM) to device with SLI-3 interface spec. When
14130 * PM invokes this method, it quiesces the device by stopping the driver's
14131 * worker thread for the device, turning off device's interrupt and DMA,
14132 * and bring the device offline. Note that as the driver implements the
14133 * minimum PM requirements to a power-aware driver's PM support for the
14134 * suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE, FREEZE)
14135 * to the suspend() method call will be treated as SUSPEND and the driver will
14136 * fully reinitialize its device during resume() method call, the driver will
14137 * set device to PCI_D3hot state in PCI config space instead of setting it
14138 * according to the @msg provided by the PM.
14139 *
14140 * Return code
14141 * 0 - driver suspended the device
14142 * Error otherwise
14143 **/
ef6fa16b
VG
14144static int __maybe_unused
14145lpfc_pci_suspend_one_s3(struct device *dev_d)
da0436e9 14146{
ef6fa16b 14147 struct Scsi_Host *shost = dev_get_drvdata(dev_d);
da0436e9
JS
14148 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
14149
14150 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
14151 "0473 PCI device Power Management suspend.\n");
14152
14153 /* Bring down the device */
618a5230 14154 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
da0436e9
JS
14155 lpfc_offline(phba);
14156 kthread_stop(phba->worker_thread);
14157
14158 /* Disable interrupt from device */
14159 lpfc_sli_disable_intr(phba);
14160
da0436e9
JS
14161 return 0;
14162}
14163
14164/**
14165 * lpfc_pci_resume_one_s3 - PCI func to resume SLI-3 device for power mgmnt
ef6fa16b 14166 * @dev_d: pointer to device
da0436e9
JS
14167 *
14168 * This routine is to be called from the kernel's PCI subsystem to support
14169 * system Power Management (PM) to device with SLI-3 interface spec. When PM
14170 * invokes this method, it restores the device's PCI config space state and
14171 * fully reinitializes the device and brings it online. Note that as the
14172 * driver implements the minimum PM requirements to a power-aware driver's
14173 * PM for suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE,
14174 * FREEZE) to the suspend() method call will be treated as SUSPEND and the
14175 * driver will fully reinitialize its device during resume() method call,
14176 * the device will be set to PCI_D0 directly in PCI config space before
14177 * restoring the state.
14178 *
14179 * Return code
14180 * 0 - driver suspended the device
14181 * Error otherwise
14182 **/
ef6fa16b
VG
14183static int __maybe_unused
14184lpfc_pci_resume_one_s3(struct device *dev_d)
da0436e9 14185{
ef6fa16b 14186 struct Scsi_Host *shost = dev_get_drvdata(dev_d);
da0436e9
JS
14187 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
14188 uint32_t intr_mode;
14189 int error;
14190
14191 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
14192 "0452 PCI device Power Management resume.\n");
14193
da0436e9
JS
14194 /* Startup the kernel thread for this host adapter. */
14195 phba->worker_thread = kthread_run(lpfc_do_work, phba,
14196 "lpfc_worker_%d", phba->brd_no);
14197 if (IS_ERR(phba->worker_thread)) {
14198 error = PTR_ERR(phba->worker_thread);
14199 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
14200 "0434 PM resume failed to start worker "
14201 "thread: error=x%x.\n", error);
14202 return error;
14203 }
14204
25ac2c97
JS
14205 /* Init cpu_map array */
14206 lpfc_cpu_map_array_init(phba);
14207 /* Init hba_eq_hdl array */
14208 lpfc_hba_eq_hdl_array_init(phba);
da0436e9
JS
14209 /* Configure and enable interrupt */
14210 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
14211 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 14212 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
14213 "0430 PM resume Failed to enable interrupt\n");
14214 return -EIO;
14215 } else
14216 phba->intr_mode = intr_mode;
14217
14218 /* Restart HBA and bring it online */
14219 lpfc_sli_brdrestart(phba);
14220 lpfc_online(phba);
14221
14222 /* Log the current active interrupt mode */
14223 lpfc_log_intr_mode(phba, phba->intr_mode);
14224
14225 return 0;
14226}
14227
891478a2
JS
14228/**
14229 * lpfc_sli_prep_dev_for_recover - Prepare SLI3 device for pci slot recover
14230 * @phba: pointer to lpfc hba data structure.
14231 *
14232 * This routine is called to prepare the SLI3 device for PCI slot recover. It
e2af0d2e 14233 * aborts all the outstanding SCSI I/Os to the pci device.
891478a2
JS
14234 **/
14235static void
14236lpfc_sli_prep_dev_for_recover(struct lpfc_hba *phba)
14237{
372c187b 14238 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
891478a2 14239 "2723 PCI channel I/O abort preparing for recovery\n");
e2af0d2e
JS
14240
14241 /*
14242 * There may be errored I/Os through HBA, abort all I/Os on txcmplq
14243 * and let the SCSI mid-layer to retry them to recover.
14244 */
db55fba8 14245 lpfc_sli_abort_fcp_rings(phba);
891478a2
JS
14246}
14247
0d878419
JS
14248/**
14249 * lpfc_sli_prep_dev_for_reset - Prepare SLI3 device for pci slot reset
14250 * @phba: pointer to lpfc hba data structure.
14251 *
14252 * This routine is called to prepare the SLI3 device for PCI slot reset. It
14253 * disables the device interrupt and pci device, and aborts the internal FCP
14254 * pending I/Os.
14255 **/
14256static void
14257lpfc_sli_prep_dev_for_reset(struct lpfc_hba *phba)
14258{
372c187b 14259 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
891478a2 14260 "2710 PCI channel disable preparing for reset\n");
e2af0d2e 14261
75baf696 14262 /* Block any management I/Os to the device */
618a5230 14263 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
75baf696 14264
e2af0d2e
JS
14265 /* Block all SCSI devices' I/Os on the host */
14266 lpfc_scsi_dev_block(phba);
14267
ea714f3d 14268 /* Flush all driver's outstanding SCSI I/Os as we are to reset */
c00f62e6 14269 lpfc_sli_flush_io_rings(phba);
ea714f3d 14270
e2af0d2e
JS
14271 /* stop all timers */
14272 lpfc_stop_hba_timers(phba);
14273
0d878419
JS
14274 /* Disable interrupt and pci device */
14275 lpfc_sli_disable_intr(phba);
14276 pci_disable_device(phba->pcidev);
0d878419
JS
14277}
14278
14279/**
14280 * lpfc_sli_prep_dev_for_perm_failure - Prepare SLI3 dev for pci slot disable
14281 * @phba: pointer to lpfc hba data structure.
14282 *
14283 * This routine is called to prepare the SLI3 device for PCI slot permanently
14284 * disabling. It blocks the SCSI transport layer traffic and flushes the FCP
14285 * pending I/Os.
14286 **/
14287static void
75baf696 14288lpfc_sli_prep_dev_for_perm_failure(struct lpfc_hba *phba)
0d878419 14289{
372c187b 14290 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
891478a2 14291 "2711 PCI channel permanent disable for failure\n");
e2af0d2e
JS
14292 /* Block all SCSI devices' I/Os on the host */
14293 lpfc_scsi_dev_block(phba);
a4691038 14294 lpfc_sli4_prep_dev_for_reset(phba);
e2af0d2e
JS
14295
14296 /* stop all timers */
14297 lpfc_stop_hba_timers(phba);
14298
0d878419 14299 /* Clean up all driver's outstanding SCSI I/Os */
c00f62e6 14300 lpfc_sli_flush_io_rings(phba);
0d878419
JS
14301}
14302
da0436e9
JS
14303/**
14304 * lpfc_io_error_detected_s3 - Method for handling SLI-3 device PCI I/O error
14305 * @pdev: pointer to PCI device.
14306 * @state: the current PCI connection state.
14307 *
14308 * This routine is called from the PCI subsystem for I/O error handling to
14309 * device with SLI-3 interface spec. This function is called by the PCI
14310 * subsystem after a PCI bus error affecting this device has been detected.
14311 * When this function is invoked, it will need to stop all the I/Os and
14312 * interrupt(s) to the device. Once that is done, it will return
14313 * PCI_ERS_RESULT_NEED_RESET for the PCI subsystem to perform proper recovery
14314 * as desired.
14315 *
14316 * Return codes
0d878419 14317 * PCI_ERS_RESULT_CAN_RECOVER - can be recovered with reset_link
da0436e9
JS
14318 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
14319 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
14320 **/
14321static pci_ers_result_t
14322lpfc_io_error_detected_s3(struct pci_dev *pdev, pci_channel_state_t state)
14323{
14324 struct Scsi_Host *shost = pci_get_drvdata(pdev);
14325 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
da0436e9 14326
0d878419
JS
14327 switch (state) {
14328 case pci_channel_io_normal:
891478a2
JS
14329 /* Non-fatal error, prepare for recovery */
14330 lpfc_sli_prep_dev_for_recover(phba);
0d878419
JS
14331 return PCI_ERS_RESULT_CAN_RECOVER;
14332 case pci_channel_io_frozen:
14333 /* Fatal error, prepare for slot reset */
14334 lpfc_sli_prep_dev_for_reset(phba);
14335 return PCI_ERS_RESULT_NEED_RESET;
14336 case pci_channel_io_perm_failure:
14337 /* Permanent failure, prepare for device down */
75baf696 14338 lpfc_sli_prep_dev_for_perm_failure(phba);
da0436e9 14339 return PCI_ERS_RESULT_DISCONNECT;
0d878419
JS
14340 default:
14341 /* Unknown state, prepare and request slot reset */
372c187b 14342 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0d878419
JS
14343 "0472 Unknown PCI error state: x%x\n", state);
14344 lpfc_sli_prep_dev_for_reset(phba);
14345 return PCI_ERS_RESULT_NEED_RESET;
da0436e9 14346 }
da0436e9
JS
14347}
14348
14349/**
14350 * lpfc_io_slot_reset_s3 - Method for restarting PCI SLI-3 device from scratch.
14351 * @pdev: pointer to PCI device.
14352 *
14353 * This routine is called from the PCI subsystem for error handling to
14354 * device with SLI-3 interface spec. This is called after PCI bus has been
14355 * reset to restart the PCI card from scratch, as if from a cold-boot.
14356 * During the PCI subsystem error recovery, after driver returns
14357 * PCI_ERS_RESULT_NEED_RESET, the PCI subsystem will perform proper error
14358 * recovery and then call this routine before calling the .resume method
14359 * to recover the device. This function will initialize the HBA device,
14360 * enable the interrupt, but it will just put the HBA to offline state
14361 * without passing any I/O traffic.
14362 *
14363 * Return codes
14364 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
14365 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
14366 */
14367static pci_ers_result_t
14368lpfc_io_slot_reset_s3(struct pci_dev *pdev)
14369{
14370 struct Scsi_Host *shost = pci_get_drvdata(pdev);
14371 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
14372 struct lpfc_sli *psli = &phba->sli;
14373 uint32_t intr_mode;
14374
14375 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
14376 if (pci_enable_device_mem(pdev)) {
14377 printk(KERN_ERR "lpfc: Cannot re-enable "
14378 "PCI device after reset.\n");
14379 return PCI_ERS_RESULT_DISCONNECT;
14380 }
14381
14382 pci_restore_state(pdev);
1dfb5a47
JS
14383
14384 /*
14385 * As the new kernel behavior of pci_restore_state() API call clears
14386 * device saved_state flag, need to save the restored state again.
14387 */
14388 pci_save_state(pdev);
14389
da0436e9
JS
14390 if (pdev->is_busmaster)
14391 pci_set_master(pdev);
14392
14393 spin_lock_irq(&phba->hbalock);
14394 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
14395 spin_unlock_irq(&phba->hbalock);
14396
14397 /* Configure and enable interrupt */
14398 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
14399 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 14400 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
14401 "0427 Cannot re-enable interrupt after "
14402 "slot reset.\n");
14403 return PCI_ERS_RESULT_DISCONNECT;
14404 } else
14405 phba->intr_mode = intr_mode;
14406
75baf696 14407 /* Take device offline, it will perform cleanup */
618a5230 14408 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
da0436e9
JS
14409 lpfc_offline(phba);
14410 lpfc_sli_brdrestart(phba);
14411
14412 /* Log the current active interrupt mode */
14413 lpfc_log_intr_mode(phba, phba->intr_mode);
14414
14415 return PCI_ERS_RESULT_RECOVERED;
14416}
14417
14418/**
14419 * lpfc_io_resume_s3 - Method for resuming PCI I/O operation on SLI-3 device.
14420 * @pdev: pointer to PCI device
14421 *
14422 * This routine is called from the PCI subsystem for error handling to device
14423 * with SLI-3 interface spec. It is called when kernel error recovery tells
14424 * the lpfc driver that it is ok to resume normal PCI operation after PCI bus
14425 * error recovery. After this call, traffic can start to flow from this device
14426 * again.
14427 */
14428static void
14429lpfc_io_resume_s3(struct pci_dev *pdev)
14430{
14431 struct Scsi_Host *shost = pci_get_drvdata(pdev);
14432 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
3772a991 14433
e2af0d2e 14434 /* Bring device online, it will be no-op for non-fatal error resume */
da0436e9
JS
14435 lpfc_online(phba);
14436}
3772a991 14437
da0436e9
JS
14438/**
14439 * lpfc_sli4_get_els_iocb_cnt - Calculate the # of ELS IOCBs to reserve
14440 * @phba: pointer to lpfc hba data structure.
14441 *
14442 * returns the number of ELS/CT IOCBs to reserve
14443 **/
14444int
14445lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *phba)
14446{
14447 int max_xri = phba->sli4_hba.max_cfg_param.max_xri;
14448
f1126688
JS
14449 if (phba->sli_rev == LPFC_SLI_REV4) {
14450 if (max_xri <= 100)
6a9c52cf 14451 return 10;
f1126688 14452 else if (max_xri <= 256)
6a9c52cf 14453 return 25;
f1126688 14454 else if (max_xri <= 512)
6a9c52cf 14455 return 50;
f1126688 14456 else if (max_xri <= 1024)
6a9c52cf 14457 return 100;
8a9d2e80 14458 else if (max_xri <= 1536)
6a9c52cf 14459 return 150;
8a9d2e80
JS
14460 else if (max_xri <= 2048)
14461 return 200;
14462 else
14463 return 250;
f1126688
JS
14464 } else
14465 return 0;
3772a991
JS
14466}
14467
895427bd
JS
14468/**
14469 * lpfc_sli4_get_iocb_cnt - Calculate the # of total IOCBs to reserve
14470 * @phba: pointer to lpfc hba data structure.
14471 *
f358dd0c 14472 * returns the number of ELS/CT + NVMET IOCBs to reserve
895427bd
JS
14473 **/
14474int
14475lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba)
14476{
14477 int max_xri = lpfc_sli4_get_els_iocb_cnt(phba);
14478
f358dd0c
JS
14479 if (phba->nvmet_support)
14480 max_xri += LPFC_NVMET_BUF_POST;
895427bd
JS
14481 return max_xri;
14482}
14483
14484
0a5ce731 14485static int
1feb8204
JS
14486lpfc_log_write_firmware_error(struct lpfc_hba *phba, uint32_t offset,
14487 uint32_t magic_number, uint32_t ftype, uint32_t fid, uint32_t fsize,
14488 const struct firmware *fw)
14489{
0a5ce731 14490 int rc;
f6c5e6c4 14491 u8 sli_family;
0a5ce731 14492
f6c5e6c4 14493 sli_family = bf_get(lpfc_sli_intf_sli_family, &phba->sli4_hba.sli_intf);
0a5ce731
JS
14494 /* Three cases: (1) FW was not supported on the detected adapter.
14495 * (2) FW update has been locked out administratively.
14496 * (3) Some other error during FW update.
14497 * In each case, an unmaskable message is written to the console
14498 * for admin diagnosis.
14499 */
14500 if (offset == ADD_STATUS_FW_NOT_SUPPORTED ||
f6c5e6c4 14501 (sli_family == LPFC_SLI_INTF_FAMILY_G6 &&
5792a0e8 14502 magic_number != MAGIC_NUMBER_G6) ||
f6c5e6c4
JS
14503 (sli_family == LPFC_SLI_INTF_FAMILY_G7 &&
14504 magic_number != MAGIC_NUMBER_G7) ||
14505 (sli_family == LPFC_SLI_INTF_FAMILY_G7P &&
14506 magic_number != MAGIC_NUMBER_G7P)) {
372c187b 14507 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731
JS
14508 "3030 This firmware version is not supported on"
14509 " this HBA model. Device:%x Magic:%x Type:%x "
14510 "ID:%x Size %d %zd\n",
14511 phba->pcidev->device, magic_number, ftype, fid,
14512 fsize, fw->size);
14513 rc = -EINVAL;
14514 } else if (offset == ADD_STATUS_FW_DOWNLOAD_HW_DISABLED) {
372c187b 14515 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731
JS
14516 "3021 Firmware downloads have been prohibited "
14517 "by a system configuration setting on "
14518 "Device:%x Magic:%x Type:%x ID:%x Size %d "
14519 "%zd\n",
14520 phba->pcidev->device, magic_number, ftype, fid,
14521 fsize, fw->size);
14522 rc = -EACCES;
14523 } else {
372c187b 14524 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731
JS
14525 "3022 FW Download failed. Add Status x%x "
14526 "Device:%x Magic:%x Type:%x ID:%x Size %d "
14527 "%zd\n",
14528 offset, phba->pcidev->device, magic_number,
14529 ftype, fid, fsize, fw->size);
14530 rc = -EIO;
14531 }
14532 return rc;
1feb8204
JS
14533}
14534
52d52440
JS
14535/**
14536 * lpfc_write_firmware - attempt to write a firmware image to the port
52d52440 14537 * @fw: pointer to firmware image returned from request_firmware.
0a5ce731 14538 * @context: pointer to firmware image returned from request_firmware.
52d52440 14539 *
52d52440 14540 **/
ce396282
JS
14541static void
14542lpfc_write_firmware(const struct firmware *fw, void *context)
52d52440 14543{
ce396282 14544 struct lpfc_hba *phba = (struct lpfc_hba *)context;
6b5151fd 14545 char fwrev[FW_REV_STR_SIZE];
ce396282 14546 struct lpfc_grp_hdr *image;
52d52440
JS
14547 struct list_head dma_buffer_list;
14548 int i, rc = 0;
14549 struct lpfc_dmabuf *dmabuf, *next;
14550 uint32_t offset = 0, temp_offset = 0;
6b6ef5db 14551 uint32_t magic_number, ftype, fid, fsize;
52d52440 14552
c71ab861 14553 /* It can be null in no-wait mode, sanity check */
ce396282
JS
14554 if (!fw) {
14555 rc = -ENXIO;
14556 goto out;
14557 }
14558 image = (struct lpfc_grp_hdr *)fw->data;
14559
6b6ef5db
JS
14560 magic_number = be32_to_cpu(image->magic_number);
14561 ftype = bf_get_be32(lpfc_grp_hdr_file_type, image);
1feb8204 14562 fid = bf_get_be32(lpfc_grp_hdr_id, image);
6b6ef5db
JS
14563 fsize = be32_to_cpu(image->size);
14564
52d52440 14565 INIT_LIST_HEAD(&dma_buffer_list);
52d52440 14566 lpfc_decode_firmware_rev(phba, fwrev, 1);
88a2cfbb 14567 if (strncmp(fwrev, image->revision, strnlen(image->revision, 16))) {
372c187b 14568 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
ce396282 14569 "3023 Updating Firmware, Current Version:%s "
52d52440 14570 "New Version:%s\n",
88a2cfbb 14571 fwrev, image->revision);
52d52440
JS
14572 for (i = 0; i < LPFC_MBX_WR_CONFIG_MAX_BDE; i++) {
14573 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf),
14574 GFP_KERNEL);
14575 if (!dmabuf) {
14576 rc = -ENOMEM;
ce396282 14577 goto release_out;
52d52440
JS
14578 }
14579 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
14580 SLI4_PAGE_SIZE,
14581 &dmabuf->phys,
14582 GFP_KERNEL);
14583 if (!dmabuf->virt) {
14584 kfree(dmabuf);
14585 rc = -ENOMEM;
ce396282 14586 goto release_out;
52d52440
JS
14587 }
14588 list_add_tail(&dmabuf->list, &dma_buffer_list);
14589 }
14590 while (offset < fw->size) {
14591 temp_offset = offset;
14592 list_for_each_entry(dmabuf, &dma_buffer_list, list) {
079b5c91 14593 if (temp_offset + SLI4_PAGE_SIZE > fw->size) {
52d52440
JS
14594 memcpy(dmabuf->virt,
14595 fw->data + temp_offset,
079b5c91
JS
14596 fw->size - temp_offset);
14597 temp_offset = fw->size;
52d52440
JS
14598 break;
14599 }
52d52440
JS
14600 memcpy(dmabuf->virt, fw->data + temp_offset,
14601 SLI4_PAGE_SIZE);
88a2cfbb 14602 temp_offset += SLI4_PAGE_SIZE;
52d52440
JS
14603 }
14604 rc = lpfc_wr_object(phba, &dma_buffer_list,
14605 (fw->size - offset), &offset);
1feb8204 14606 if (rc) {
0a5ce731
JS
14607 rc = lpfc_log_write_firmware_error(phba, offset,
14608 magic_number,
14609 ftype,
14610 fid,
14611 fsize,
14612 fw);
ce396282 14613 goto release_out;
1feb8204 14614 }
52d52440
JS
14615 }
14616 rc = offset;
1feb8204 14617 } else
372c187b 14618 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1feb8204
JS
14619 "3029 Skipped Firmware update, Current "
14620 "Version:%s New Version:%s\n",
14621 fwrev, image->revision);
ce396282
JS
14622
14623release_out:
52d52440
JS
14624 list_for_each_entry_safe(dmabuf, next, &dma_buffer_list, list) {
14625 list_del(&dmabuf->list);
14626 dma_free_coherent(&phba->pcidev->dev, SLI4_PAGE_SIZE,
14627 dmabuf->virt, dmabuf->phys);
14628 kfree(dmabuf);
14629 }
ce396282
JS
14630 release_firmware(fw);
14631out:
0a5ce731 14632 if (rc < 0)
372c187b 14633 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731
JS
14634 "3062 Firmware update error, status %d.\n", rc);
14635 else
372c187b 14636 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731 14637 "3024 Firmware update success: size %d.\n", rc);
52d52440
JS
14638}
14639
c71ab861
JS
14640/**
14641 * lpfc_sli4_request_firmware_update - Request linux generic firmware upgrade
14642 * @phba: pointer to lpfc hba data structure.
fe614acd 14643 * @fw_upgrade: which firmware to update.
c71ab861
JS
14644 *
14645 * This routine is called to perform Linux generic firmware upgrade on device
14646 * that supports such feature.
14647 **/
14648int
14649lpfc_sli4_request_firmware_update(struct lpfc_hba *phba, uint8_t fw_upgrade)
14650{
14651 uint8_t file_name[ELX_MODEL_NAME_SIZE];
14652 int ret;
14653 const struct firmware *fw;
14654
14655 /* Only supported on SLI4 interface type 2 for now */
27d6ac0a 14656 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) <
c71ab861
JS
14657 LPFC_SLI_INTF_IF_TYPE_2)
14658 return -EPERM;
14659
14660 snprintf(file_name, ELX_MODEL_NAME_SIZE, "%s.grp", phba->ModelName);
14661
14662 if (fw_upgrade == INT_FW_UPGRADE) {
0733d839 14663 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
c71ab861
JS
14664 file_name, &phba->pcidev->dev,
14665 GFP_KERNEL, (void *)phba,
14666 lpfc_write_firmware);
14667 } else if (fw_upgrade == RUN_FW_UPGRADE) {
14668 ret = request_firmware(&fw, file_name, &phba->pcidev->dev);
14669 if (!ret)
14670 lpfc_write_firmware(fw, (void *)phba);
14671 } else {
14672 ret = -EINVAL;
14673 }
14674
14675 return ret;
14676}
14677
3772a991 14678/**
da0436e9 14679 * lpfc_pci_probe_one_s4 - PCI probe func to reg SLI-4 device to PCI subsys
3772a991
JS
14680 * @pdev: pointer to PCI device
14681 * @pid: pointer to PCI device identifier
14682 *
da0436e9
JS
14683 * This routine is called from the kernel's PCI subsystem to device with
14684 * SLI-4 interface spec. When an Emulex HBA with SLI-4 interface spec is
3772a991 14685 * presented on PCI bus, the kernel PCI subsystem looks at PCI device-specific
da0436e9
JS
14686 * information of the device and driver to see if the driver state that it
14687 * can support this kind of device. If the match is successful, the driver
14688 * core invokes this routine. If this routine determines it can claim the HBA,
14689 * it does all the initialization that it needs to do to handle the HBA
14690 * properly.
3772a991
JS
14691 *
14692 * Return code
14693 * 0 - driver can claim the device
14694 * negative value - driver can not claim the device
14695 **/
6f039790 14696static int
da0436e9 14697lpfc_pci_probe_one_s4(struct pci_dev *pdev, const struct pci_device_id *pid)
3772a991
JS
14698{
14699 struct lpfc_hba *phba;
14700 struct lpfc_vport *vport = NULL;
6669f9bb 14701 struct Scsi_Host *shost = NULL;
6c621a22 14702 int error;
3772a991
JS
14703 uint32_t cfg_mode, intr_mode;
14704
14705 /* Allocate memory for HBA structure */
14706 phba = lpfc_hba_alloc(pdev);
14707 if (!phba)
14708 return -ENOMEM;
14709
9977d880
EM
14710 INIT_LIST_HEAD(&phba->poll_list);
14711
3772a991
JS
14712 /* Perform generic PCI device enabling operation */
14713 error = lpfc_enable_pci_dev(phba);
079b5c91 14714 if (error)
3772a991 14715 goto out_free_phba;
3772a991 14716
da0436e9
JS
14717 /* Set up SLI API function jump table for PCI-device group-1 HBAs */
14718 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_OC);
3772a991
JS
14719 if (error)
14720 goto out_disable_pci_dev;
14721
da0436e9
JS
14722 /* Set up SLI-4 specific device PCI memory space */
14723 error = lpfc_sli4_pci_mem_setup(phba);
3772a991
JS
14724 if (error) {
14725 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 14726 "1410 Failed to set up pci memory space.\n");
3772a991
JS
14727 goto out_disable_pci_dev;
14728 }
14729
da0436e9
JS
14730 /* Set up SLI-4 Specific device driver resources */
14731 error = lpfc_sli4_driver_resource_setup(phba);
3772a991
JS
14732 if (error) {
14733 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9
JS
14734 "1412 Failed to set up driver resource.\n");
14735 goto out_unset_pci_mem_s4;
3772a991
JS
14736 }
14737
19ca7609 14738 INIT_LIST_HEAD(&phba->active_rrq_list);
7d791df7 14739 INIT_LIST_HEAD(&phba->fcf.fcf_pri_list);
19ca7609 14740
3772a991
JS
14741 /* Set up common device driver resources */
14742 error = lpfc_setup_driver_resource_phase2(phba);
14743 if (error) {
14744 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 14745 "1414 Failed to set up driver resource.\n");
6c621a22 14746 goto out_unset_driver_resource_s4;
3772a991
JS
14747 }
14748
079b5c91
JS
14749 /* Get the default values for Model Name and Description */
14750 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
14751
3772a991 14752 /* Now, trying to enable interrupt and bring up the device */
5b75da2f 14753 cfg_mode = phba->cfg_use_msi;
5b75da2f 14754
7b15db32 14755 /* Put device to a known state before enabling interrupt */
cdb42bec 14756 phba->pport = NULL;
7b15db32 14757 lpfc_stop_port(phba);
895427bd 14758
dcaa2136
JS
14759 /* Init cpu_map array */
14760 lpfc_cpu_map_array_init(phba);
14761
14762 /* Init hba_eq_hdl array */
14763 lpfc_hba_eq_hdl_array_init(phba);
14764
7b15db32
JS
14765 /* Configure and enable interrupt */
14766 intr_mode = lpfc_sli4_enable_intr(phba, cfg_mode);
14767 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 14768 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
7b15db32
JS
14769 "0426 Failed to enable interrupt.\n");
14770 error = -ENODEV;
cdb42bec 14771 goto out_unset_driver_resource;
7b15db32
JS
14772 }
14773 /* Default to single EQ for non-MSI-X */
895427bd 14774 if (phba->intr_type != MSIX) {
6a828b0f 14775 phba->cfg_irq_chann = 1;
2d7dbc4c 14776 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
2d7dbc4c
JS
14777 if (phba->nvmet_support)
14778 phba->cfg_nvmet_mrq = 1;
14779 }
cdb42bec 14780 }
6a828b0f 14781 lpfc_cpu_affinity_check(phba, phba->cfg_irq_chann);
cdb42bec
JS
14782
14783 /* Create SCSI host to the physical port */
14784 error = lpfc_create_shost(phba);
14785 if (error) {
14786 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
14787 "1415 Failed to create scsi host.\n");
14788 goto out_disable_intr;
14789 }
14790 vport = phba->pport;
14791 shost = lpfc_shost_from_vport(vport); /* save shost for error cleanup */
14792
14793 /* Configure sysfs attributes */
14794 error = lpfc_alloc_sysfs_attr(vport);
14795 if (error) {
14796 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
14797 "1416 Failed to allocate sysfs attr\n");
14798 goto out_destroy_shost;
895427bd
JS
14799 }
14800
7b15db32
JS
14801 /* Set up SLI-4 HBA */
14802 if (lpfc_sli4_hba_setup(phba)) {
372c187b 14803 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
7b15db32
JS
14804 "1421 Failed to set up hba\n");
14805 error = -ENODEV;
cdb42bec 14806 goto out_free_sysfs_attr;
98c9ea5c 14807 }
858c9f6c 14808
7b15db32
JS
14809 /* Log the current active interrupt mode */
14810 phba->intr_mode = intr_mode;
14811 lpfc_log_intr_mode(phba, intr_mode);
14812
3772a991
JS
14813 /* Perform post initialization setup */
14814 lpfc_post_init_setup(phba);
dea3101e 14815
01649561
JS
14816 /* NVME support in FW earlier in the driver load corrects the
14817 * FC4 type making a check for nvme_support unnecessary.
14818 */
0794d601
JS
14819 if (phba->nvmet_support == 0) {
14820 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
14821 /* Create NVME binding with nvme_fc_transport. This
14822 * ensures the vport is initialized. If the localport
14823 * create fails, it should not unload the driver to
14824 * support field issues.
14825 */
14826 error = lpfc_nvme_create_localport(vport);
14827 if (error) {
372c187b 14828 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0794d601
JS
14829 "6004 NVME registration "
14830 "failed, error x%x\n",
14831 error);
14832 }
01649561
JS
14833 }
14834 }
895427bd 14835
c71ab861
JS
14836 /* check for firmware upgrade or downgrade */
14837 if (phba->cfg_request_firmware_upgrade)
db6f1c2f 14838 lpfc_sli4_request_firmware_update(phba, INT_FW_UPGRADE);
52d52440 14839
1c6834a7
JS
14840 /* Check if there are static vports to be created. */
14841 lpfc_create_static_vport(phba);
d2cc9bcd 14842
f861f596 14843 timer_setup(&phba->cpuhp_poll_timer, lpfc_sli4_poll_hbtimer, 0);
93a4d6f4
JS
14844 cpuhp_state_add_instance_nocalls(lpfc_cpuhp_state, &phba->cpuhp);
14845
dea3101e 14846 return 0;
14847
5b75da2f
JS
14848out_free_sysfs_attr:
14849 lpfc_free_sysfs_attr(vport);
3772a991
JS
14850out_destroy_shost:
14851 lpfc_destroy_shost(phba);
cdb42bec
JS
14852out_disable_intr:
14853 lpfc_sli4_disable_intr(phba);
3772a991
JS
14854out_unset_driver_resource:
14855 lpfc_unset_driver_resource_phase2(phba);
da0436e9
JS
14856out_unset_driver_resource_s4:
14857 lpfc_sli4_driver_resource_unset(phba);
14858out_unset_pci_mem_s4:
14859 lpfc_sli4_pci_mem_unset(phba);
3772a991
JS
14860out_disable_pci_dev:
14861 lpfc_disable_pci_dev(phba);
6669f9bb
JS
14862 if (shost)
14863 scsi_host_put(shost);
2e0fef85 14864out_free_phba:
3772a991 14865 lpfc_hba_free(phba);
dea3101e 14866 return error;
14867}
14868
e59058c4 14869/**
da0436e9 14870 * lpfc_pci_remove_one_s4 - PCI func to unreg SLI-4 device from PCI subsystem
e59058c4
JS
14871 * @pdev: pointer to PCI device
14872 *
da0436e9
JS
14873 * This routine is called from the kernel's PCI subsystem to device with
14874 * SLI-4 interface spec. When an Emulex HBA with SLI-4 interface spec is
3772a991
JS
14875 * removed from PCI bus, it performs all the necessary cleanup for the HBA
14876 * device to be removed from the PCI subsystem properly.
e59058c4 14877 **/
6f039790 14878static void
da0436e9 14879lpfc_pci_remove_one_s4(struct pci_dev *pdev)
dea3101e 14880{
da0436e9 14881 struct Scsi_Host *shost = pci_get_drvdata(pdev);
2e0fef85 14882 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
eada272d 14883 struct lpfc_vport **vports;
da0436e9 14884 struct lpfc_hba *phba = vport->phba;
eada272d 14885 int i;
8a4df120 14886
da0436e9 14887 /* Mark the device unloading flag */
549e55cd 14888 spin_lock_irq(&phba->hbalock);
51ef4c26 14889 vport->load_flag |= FC_UNLOADING;
549e55cd 14890 spin_unlock_irq(&phba->hbalock);
02243836
JS
14891 if (phba->cgn_i)
14892 lpfc_unreg_congestion_buf(phba);
2e0fef85 14893
858c9f6c
JS
14894 lpfc_free_sysfs_attr(vport);
14895
eada272d
JS
14896 /* Release all the vports against this physical port */
14897 vports = lpfc_create_vport_work_array(phba);
14898 if (vports != NULL)
587a37f6
JS
14899 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
14900 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
14901 continue;
eada272d 14902 fc_vport_terminate(vports[i]->fc_vport);
587a37f6 14903 }
eada272d
JS
14904 lpfc_destroy_vport_work_array(phba, vports);
14905
95f0ef8a 14906 /* Remove FC host with the physical port */
858c9f6c 14907 fc_remove_host(shost);
e9b11083 14908 scsi_remove_host(shost);
da0436e9 14909
d613b6a7
JS
14910 /* Perform ndlp cleanup on the physical port. The nvme and nvmet
14911 * localports are destroyed after to cleanup all transport memory.
895427bd 14912 */
87af33fe 14913 lpfc_cleanup(vport);
d613b6a7
JS
14914 lpfc_nvmet_destroy_targetport(phba);
14915 lpfc_nvme_destroy_localport(vport);
87af33fe 14916
c490850a
JS
14917 /* De-allocate multi-XRI pools */
14918 if (phba->cfg_xri_rebalancing)
14919 lpfc_destroy_multixri_pools(phba);
14920
281d6190
JS
14921 /*
14922 * Bring down the SLI Layer. This step disables all interrupts,
14923 * clears the rings, discards all mailbox commands, and resets
14924 * the HBA FCoE function.
14925 */
14926 lpfc_debugfs_terminate(vport);
a257bf90 14927
1901762f 14928 lpfc_stop_hba_timers(phba);
523128e5 14929 spin_lock_irq(&phba->port_list_lock);
858c9f6c 14930 list_del_init(&vport->listentry);
523128e5 14931 spin_unlock_irq(&phba->port_list_lock);
858c9f6c 14932
3677a3a7 14933 /* Perform scsi free before driver resource_unset since scsi
da0436e9 14934 * buffers are released to their corresponding pools here.
2e0fef85 14935 */
5e5b511d 14936 lpfc_io_free(phba);
01649561 14937 lpfc_free_iocb_list(phba);
5e5b511d 14938 lpfc_sli4_hba_unset(phba);
67d12733 14939
0cdb84ec 14940 lpfc_unset_driver_resource_phase2(phba);
da0436e9 14941 lpfc_sli4_driver_resource_unset(phba);
ed957684 14942
da0436e9
JS
14943 /* Unmap adapter Control and Doorbell registers */
14944 lpfc_sli4_pci_mem_unset(phba);
2e0fef85 14945
da0436e9
JS
14946 /* Release PCI resources and disable device's PCI function */
14947 scsi_host_put(shost);
14948 lpfc_disable_pci_dev(phba);
2e0fef85 14949
da0436e9 14950 /* Finally, free the driver's device data structure */
3772a991 14951 lpfc_hba_free(phba);
2e0fef85 14952
da0436e9 14953 return;
dea3101e 14954}
14955
3a55b532 14956/**
da0436e9 14957 * lpfc_pci_suspend_one_s4 - PCI func to suspend SLI-4 device for power mgmnt
ef6fa16b 14958 * @dev_d: pointer to device
3a55b532 14959 *
da0436e9
JS
14960 * This routine is called from the kernel's PCI subsystem to support system
14961 * Power Management (PM) to device with SLI-4 interface spec. When PM invokes
14962 * this method, it quiesces the device by stopping the driver's worker
14963 * thread for the device, turning off device's interrupt and DMA, and bring
14964 * the device offline. Note that as the driver implements the minimum PM
14965 * requirements to a power-aware driver's PM support for suspend/resume -- all
14966 * the possible PM messages (SUSPEND, HIBERNATE, FREEZE) to the suspend()
14967 * method call will be treated as SUSPEND and the driver will fully
14968 * reinitialize its device during resume() method call, the driver will set
14969 * device to PCI_D3hot state in PCI config space instead of setting it
3772a991 14970 * according to the @msg provided by the PM.
3a55b532
JS
14971 *
14972 * Return code
3772a991
JS
14973 * 0 - driver suspended the device
14974 * Error otherwise
3a55b532 14975 **/
ef6fa16b
VG
14976static int __maybe_unused
14977lpfc_pci_suspend_one_s4(struct device *dev_d)
3a55b532 14978{
ef6fa16b 14979 struct Scsi_Host *shost = dev_get_drvdata(dev_d);
3a55b532
JS
14980 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
14981
14982 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
75baf696 14983 "2843 PCI device Power Management suspend.\n");
3a55b532
JS
14984
14985 /* Bring down the device */
618a5230 14986 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
3a55b532
JS
14987 lpfc_offline(phba);
14988 kthread_stop(phba->worker_thread);
14989
14990 /* Disable interrupt from device */
da0436e9 14991 lpfc_sli4_disable_intr(phba);
5350d872 14992 lpfc_sli4_queue_destroy(phba);
3a55b532 14993
3a55b532
JS
14994 return 0;
14995}
14996
14997/**
da0436e9 14998 * lpfc_pci_resume_one_s4 - PCI func to resume SLI-4 device for power mgmnt
ef6fa16b 14999 * @dev_d: pointer to device
3a55b532 15000 *
da0436e9
JS
15001 * This routine is called from the kernel's PCI subsystem to support system
15002 * Power Management (PM) to device with SLI-4 interface spac. When PM invokes
15003 * this method, it restores the device's PCI config space state and fully
15004 * reinitializes the device and brings it online. Note that as the driver
15005 * implements the minimum PM requirements to a power-aware driver's PM for
15006 * suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE, FREEZE)
15007 * to the suspend() method call will be treated as SUSPEND and the driver
15008 * will fully reinitialize its device during resume() method call, the device
15009 * will be set to PCI_D0 directly in PCI config space before restoring the
15010 * state.
3a55b532
JS
15011 *
15012 * Return code
3772a991
JS
15013 * 0 - driver suspended the device
15014 * Error otherwise
3a55b532 15015 **/
ef6fa16b
VG
15016static int __maybe_unused
15017lpfc_pci_resume_one_s4(struct device *dev_d)
3a55b532 15018{
ef6fa16b 15019 struct Scsi_Host *shost = dev_get_drvdata(dev_d);
3a55b532 15020 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
5b75da2f 15021 uint32_t intr_mode;
3a55b532
JS
15022 int error;
15023
15024 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
da0436e9 15025 "0292 PCI device Power Management resume.\n");
3a55b532 15026
da0436e9 15027 /* Startup the kernel thread for this host adapter. */
3a55b532
JS
15028 phba->worker_thread = kthread_run(lpfc_do_work, phba,
15029 "lpfc_worker_%d", phba->brd_no);
15030 if (IS_ERR(phba->worker_thread)) {
15031 error = PTR_ERR(phba->worker_thread);
15032 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 15033 "0293 PM resume failed to start worker "
3a55b532
JS
15034 "thread: error=x%x.\n", error);
15035 return error;
15036 }
15037
5b75da2f 15038 /* Configure and enable interrupt */
da0436e9 15039 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
5b75da2f 15040 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 15041 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 15042 "0294 PM resume Failed to enable interrupt\n");
5b75da2f
JS
15043 return -EIO;
15044 } else
15045 phba->intr_mode = intr_mode;
3a55b532
JS
15046
15047 /* Restart HBA and bring it online */
15048 lpfc_sli_brdrestart(phba);
15049 lpfc_online(phba);
15050
5b75da2f
JS
15051 /* Log the current active interrupt mode */
15052 lpfc_log_intr_mode(phba, phba->intr_mode);
15053
3a55b532
JS
15054 return 0;
15055}
15056
75baf696
JS
15057/**
15058 * lpfc_sli4_prep_dev_for_recover - Prepare SLI4 device for pci slot recover
15059 * @phba: pointer to lpfc hba data structure.
15060 *
15061 * This routine is called to prepare the SLI4 device for PCI slot recover. It
15062 * aborts all the outstanding SCSI I/Os to the pci device.
15063 **/
15064static void
15065lpfc_sli4_prep_dev_for_recover(struct lpfc_hba *phba)
15066{
372c187b 15067 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
15068 "2828 PCI channel I/O abort preparing for recovery\n");
15069 /*
15070 * There may be errored I/Os through HBA, abort all I/Os on txcmplq
15071 * and let the SCSI mid-layer to retry them to recover.
15072 */
db55fba8 15073 lpfc_sli_abort_fcp_rings(phba);
75baf696
JS
15074}
15075
15076/**
15077 * lpfc_sli4_prep_dev_for_reset - Prepare SLI4 device for pci slot reset
15078 * @phba: pointer to lpfc hba data structure.
15079 *
15080 * This routine is called to prepare the SLI4 device for PCI slot reset. It
15081 * disables the device interrupt and pci device, and aborts the internal FCP
15082 * pending I/Os.
15083 **/
15084static void
15085lpfc_sli4_prep_dev_for_reset(struct lpfc_hba *phba)
15086{
35ed9613
JS
15087 int offline = pci_channel_offline(phba->pcidev);
15088
15089 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
15090 "2826 PCI channel disable preparing for reset offline"
15091 " %d\n", offline);
75baf696
JS
15092
15093 /* Block any management I/Os to the device */
618a5230 15094 lpfc_block_mgmt_io(phba, LPFC_MBX_NO_WAIT);
75baf696 15095
75baf696 15096
35ed9613
JS
15097 /* HBA_PCI_ERR was set in io_error_detect */
15098 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
c00f62e6
JS
15099 /* Flush all driver's outstanding I/Os as we are to reset */
15100 lpfc_sli_flush_io_rings(phba);
35ed9613 15101 lpfc_offline(phba);
c3725bdc 15102
75baf696
JS
15103 /* stop all timers */
15104 lpfc_stop_hba_timers(phba);
15105
35ed9613 15106 lpfc_sli4_queue_destroy(phba);
75baf696
JS
15107 /* Disable interrupt and pci device */
15108 lpfc_sli4_disable_intr(phba);
15109 pci_disable_device(phba->pcidev);
75baf696
JS
15110}
15111
15112/**
15113 * lpfc_sli4_prep_dev_for_perm_failure - Prepare SLI4 dev for pci slot disable
15114 * @phba: pointer to lpfc hba data structure.
15115 *
15116 * This routine is called to prepare the SLI4 device for PCI slot permanently
15117 * disabling. It blocks the SCSI transport layer traffic and flushes the FCP
15118 * pending I/Os.
15119 **/
15120static void
15121lpfc_sli4_prep_dev_for_perm_failure(struct lpfc_hba *phba)
15122{
372c187b 15123 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
15124 "2827 PCI channel permanent disable for failure\n");
15125
15126 /* Block all SCSI devices' I/Os on the host */
15127 lpfc_scsi_dev_block(phba);
15128
15129 /* stop all timers */
15130 lpfc_stop_hba_timers(phba);
15131
c00f62e6
JS
15132 /* Clean up all driver's outstanding I/Os */
15133 lpfc_sli_flush_io_rings(phba);
75baf696
JS
15134}
15135
8d63f375 15136/**
da0436e9 15137 * lpfc_io_error_detected_s4 - Method for handling PCI I/O error to SLI-4 device
e59058c4
JS
15138 * @pdev: pointer to PCI device.
15139 * @state: the current PCI connection state.
8d63f375 15140 *
da0436e9
JS
15141 * This routine is called from the PCI subsystem for error handling to device
15142 * with SLI-4 interface spec. This function is called by the PCI subsystem
15143 * after a PCI bus error affecting this device has been detected. When this
15144 * function is invoked, it will need to stop all the I/Os and interrupt(s)
15145 * to the device. Once that is done, it will return PCI_ERS_RESULT_NEED_RESET
15146 * for the PCI subsystem to perform proper recovery as desired.
e59058c4
JS
15147 *
15148 * Return codes
3772a991
JS
15149 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
15150 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
e59058c4 15151 **/
3772a991 15152static pci_ers_result_t
da0436e9 15153lpfc_io_error_detected_s4(struct pci_dev *pdev, pci_channel_state_t state)
8d63f375 15154{
75baf696
JS
15155 struct Scsi_Host *shost = pci_get_drvdata(pdev);
15156 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
35ed9613 15157 bool hba_pci_err;
75baf696
JS
15158
15159 switch (state) {
15160 case pci_channel_io_normal:
15161 /* Non-fatal error, prepare for recovery */
15162 lpfc_sli4_prep_dev_for_recover(phba);
15163 return PCI_ERS_RESULT_CAN_RECOVER;
15164 case pci_channel_io_frozen:
35ed9613 15165 hba_pci_err = test_and_set_bit(HBA_PCI_ERR, &phba->bit_flags);
75baf696 15166 /* Fatal error, prepare for slot reset */
35ed9613
JS
15167 if (!hba_pci_err)
15168 lpfc_sli4_prep_dev_for_reset(phba);
15169 else
15170 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
15171 "2832 Already handling PCI error "
15172 "state: x%x\n", state);
75baf696
JS
15173 return PCI_ERS_RESULT_NEED_RESET;
15174 case pci_channel_io_perm_failure:
35ed9613 15175 set_bit(HBA_PCI_ERR, &phba->bit_flags);
75baf696
JS
15176 /* Permanent failure, prepare for device down */
15177 lpfc_sli4_prep_dev_for_perm_failure(phba);
15178 return PCI_ERS_RESULT_DISCONNECT;
15179 default:
35ed9613
JS
15180 hba_pci_err = test_and_set_bit(HBA_PCI_ERR, &phba->bit_flags);
15181 if (!hba_pci_err)
15182 lpfc_sli4_prep_dev_for_reset(phba);
75baf696 15183 /* Unknown state, prepare and request slot reset */
372c187b 15184 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
15185 "2825 Unknown PCI error state: x%x\n", state);
15186 lpfc_sli4_prep_dev_for_reset(phba);
15187 return PCI_ERS_RESULT_NEED_RESET;
15188 }
8d63f375
LV
15189}
15190
15191/**
da0436e9 15192 * lpfc_io_slot_reset_s4 - Method for restart PCI SLI-4 device from scratch
e59058c4
JS
15193 * @pdev: pointer to PCI device.
15194 *
da0436e9
JS
15195 * This routine is called from the PCI subsystem for error handling to device
15196 * with SLI-4 interface spec. It is called after PCI bus has been reset to
15197 * restart the PCI card from scratch, as if from a cold-boot. During the
15198 * PCI subsystem error recovery, after the driver returns
3772a991 15199 * PCI_ERS_RESULT_NEED_RESET, the PCI subsystem will perform proper error
da0436e9
JS
15200 * recovery and then call this routine before calling the .resume method to
15201 * recover the device. This function will initialize the HBA device, enable
15202 * the interrupt, but it will just put the HBA to offline state without
15203 * passing any I/O traffic.
8d63f375 15204 *
e59058c4 15205 * Return codes
3772a991
JS
15206 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
15207 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
8d63f375 15208 */
3772a991 15209static pci_ers_result_t
da0436e9 15210lpfc_io_slot_reset_s4(struct pci_dev *pdev)
8d63f375 15211{
75baf696
JS
15212 struct Scsi_Host *shost = pci_get_drvdata(pdev);
15213 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
15214 struct lpfc_sli *psli = &phba->sli;
15215 uint32_t intr_mode;
35ed9613 15216 bool hba_pci_err;
75baf696
JS
15217
15218 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
15219 if (pci_enable_device_mem(pdev)) {
15220 printk(KERN_ERR "lpfc: Cannot re-enable "
35ed9613 15221 "PCI device after reset.\n");
75baf696
JS
15222 return PCI_ERS_RESULT_DISCONNECT;
15223 }
15224
15225 pci_restore_state(pdev);
0a96e975 15226
35ed9613
JS
15227 hba_pci_err = test_and_clear_bit(HBA_PCI_ERR, &phba->bit_flags);
15228 if (!hba_pci_err)
15229 dev_info(&pdev->dev,
15230 "hba_pci_err was not set, recovering slot reset.\n");
0a96e975
JS
15231 /*
15232 * As the new kernel behavior of pci_restore_state() API call clears
15233 * device saved_state flag, need to save the restored state again.
15234 */
15235 pci_save_state(pdev);
15236
75baf696
JS
15237 if (pdev->is_busmaster)
15238 pci_set_master(pdev);
15239
15240 spin_lock_irq(&phba->hbalock);
15241 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
15242 spin_unlock_irq(&phba->hbalock);
15243
df010119
JS
15244 /* Init cpu_map array */
15245 lpfc_cpu_map_array_init(phba);
75baf696
JS
15246 /* Configure and enable interrupt */
15247 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
15248 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 15249 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
15250 "2824 Cannot re-enable interrupt after "
15251 "slot reset.\n");
15252 return PCI_ERS_RESULT_DISCONNECT;
15253 } else
15254 phba->intr_mode = intr_mode;
25ac2c97 15255 lpfc_cpu_affinity_check(phba, phba->cfg_irq_chann);
75baf696
JS
15256
15257 /* Log the current active interrupt mode */
15258 lpfc_log_intr_mode(phba, phba->intr_mode);
15259
8d63f375
LV
15260 return PCI_ERS_RESULT_RECOVERED;
15261}
15262
15263/**
da0436e9 15264 * lpfc_io_resume_s4 - Method for resuming PCI I/O operation to SLI-4 device
e59058c4 15265 * @pdev: pointer to PCI device
8d63f375 15266 *
3772a991 15267 * This routine is called from the PCI subsystem for error handling to device
da0436e9 15268 * with SLI-4 interface spec. It is called when kernel error recovery tells
3772a991
JS
15269 * the lpfc driver that it is ok to resume normal PCI operation after PCI bus
15270 * error recovery. After this call, traffic can start to flow from this device
15271 * again.
da0436e9 15272 **/
3772a991 15273static void
da0436e9 15274lpfc_io_resume_s4(struct pci_dev *pdev)
8d63f375 15275{
75baf696
JS
15276 struct Scsi_Host *shost = pci_get_drvdata(pdev);
15277 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
15278
15279 /*
15280 * In case of slot reset, as function reset is performed through
15281 * mailbox command which needs DMA to be enabled, this operation
15282 * has to be moved to the io resume phase. Taking device offline
15283 * will perform the necessary cleanup.
15284 */
15285 if (!(phba->sli.sli_flag & LPFC_SLI_ACTIVE)) {
15286 /* Perform device reset */
75baf696
JS
15287 lpfc_sli_brdrestart(phba);
15288 /* Bring the device back online */
15289 lpfc_online(phba);
15290 }
8d63f375
LV
15291}
15292
3772a991
JS
15293/**
15294 * lpfc_pci_probe_one - lpfc PCI probe func to reg dev to PCI subsystem
15295 * @pdev: pointer to PCI device
15296 * @pid: pointer to PCI device identifier
15297 *
15298 * This routine is to be registered to the kernel's PCI subsystem. When an
15299 * Emulex HBA device is presented on PCI bus, the kernel PCI subsystem looks
15300 * at PCI device-specific information of the device and driver to see if the
15301 * driver state that it can support this kind of device. If the match is
15302 * successful, the driver core invokes this routine. This routine dispatches
15303 * the action to the proper SLI-3 or SLI-4 device probing routine, which will
15304 * do all the initialization that it needs to do to handle the HBA device
15305 * properly.
15306 *
15307 * Return code
15308 * 0 - driver can claim the device
15309 * negative value - driver can not claim the device
15310 **/
6f039790 15311static int
3772a991
JS
15312lpfc_pci_probe_one(struct pci_dev *pdev, const struct pci_device_id *pid)
15313{
15314 int rc;
8fa38513 15315 struct lpfc_sli_intf intf;
3772a991 15316
28baac74 15317 if (pci_read_config_dword(pdev, LPFC_SLI_INTF, &intf.word0))
3772a991
JS
15318 return -ENODEV;
15319
8fa38513 15320 if ((bf_get(lpfc_sli_intf_valid, &intf) == LPFC_SLI_INTF_VALID) &&
28baac74 15321 (bf_get(lpfc_sli_intf_slirev, &intf) == LPFC_SLI_INTF_REV_SLI4))
da0436e9 15322 rc = lpfc_pci_probe_one_s4(pdev, pid);
8fa38513 15323 else
3772a991 15324 rc = lpfc_pci_probe_one_s3(pdev, pid);
8fa38513 15325
3772a991
JS
15326 return rc;
15327}
15328
15329/**
15330 * lpfc_pci_remove_one - lpfc PCI func to unreg dev from PCI subsystem
15331 * @pdev: pointer to PCI device
15332 *
15333 * This routine is to be registered to the kernel's PCI subsystem. When an
15334 * Emulex HBA is removed from PCI bus, the driver core invokes this routine.
15335 * This routine dispatches the action to the proper SLI-3 or SLI-4 device
15336 * remove routine, which will perform all the necessary cleanup for the
15337 * device to be removed from the PCI subsystem properly.
15338 **/
6f039790 15339static void
3772a991
JS
15340lpfc_pci_remove_one(struct pci_dev *pdev)
15341{
15342 struct Scsi_Host *shost = pci_get_drvdata(pdev);
15343 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
15344
15345 switch (phba->pci_dev_grp) {
15346 case LPFC_PCI_DEV_LP:
15347 lpfc_pci_remove_one_s3(pdev);
15348 break;
da0436e9
JS
15349 case LPFC_PCI_DEV_OC:
15350 lpfc_pci_remove_one_s4(pdev);
15351 break;
3772a991 15352 default:
372c187b 15353 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
15354 "1424 Invalid PCI device group: 0x%x\n",
15355 phba->pci_dev_grp);
15356 break;
15357 }
15358 return;
15359}
15360
15361/**
15362 * lpfc_pci_suspend_one - lpfc PCI func to suspend dev for power management
ef6fa16b 15363 * @dev: pointer to device
3772a991
JS
15364 *
15365 * This routine is to be registered to the kernel's PCI subsystem to support
15366 * system Power Management (PM). When PM invokes this method, it dispatches
15367 * the action to the proper SLI-3 or SLI-4 device suspend routine, which will
15368 * suspend the device.
15369 *
15370 * Return code
15371 * 0 - driver suspended the device
15372 * Error otherwise
15373 **/
ef6fa16b
VG
15374static int __maybe_unused
15375lpfc_pci_suspend_one(struct device *dev)
3772a991 15376{
ef6fa16b 15377 struct Scsi_Host *shost = dev_get_drvdata(dev);
3772a991
JS
15378 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
15379 int rc = -ENODEV;
15380
15381 switch (phba->pci_dev_grp) {
15382 case LPFC_PCI_DEV_LP:
ef6fa16b 15383 rc = lpfc_pci_suspend_one_s3(dev);
3772a991 15384 break;
da0436e9 15385 case LPFC_PCI_DEV_OC:
ef6fa16b 15386 rc = lpfc_pci_suspend_one_s4(dev);
da0436e9 15387 break;
3772a991 15388 default:
372c187b 15389 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
15390 "1425 Invalid PCI device group: 0x%x\n",
15391 phba->pci_dev_grp);
15392 break;
15393 }
15394 return rc;
15395}
15396
15397/**
15398 * lpfc_pci_resume_one - lpfc PCI func to resume dev for power management
ef6fa16b 15399 * @dev: pointer to device
3772a991
JS
15400 *
15401 * This routine is to be registered to the kernel's PCI subsystem to support
15402 * system Power Management (PM). When PM invokes this method, it dispatches
15403 * the action to the proper SLI-3 or SLI-4 device resume routine, which will
15404 * resume the device.
15405 *
15406 * Return code
15407 * 0 - driver suspended the device
15408 * Error otherwise
15409 **/
ef6fa16b
VG
15410static int __maybe_unused
15411lpfc_pci_resume_one(struct device *dev)
3772a991 15412{
ef6fa16b 15413 struct Scsi_Host *shost = dev_get_drvdata(dev);
3772a991
JS
15414 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
15415 int rc = -ENODEV;
15416
15417 switch (phba->pci_dev_grp) {
15418 case LPFC_PCI_DEV_LP:
ef6fa16b 15419 rc = lpfc_pci_resume_one_s3(dev);
3772a991 15420 break;
da0436e9 15421 case LPFC_PCI_DEV_OC:
ef6fa16b 15422 rc = lpfc_pci_resume_one_s4(dev);
da0436e9 15423 break;
3772a991 15424 default:
372c187b 15425 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
15426 "1426 Invalid PCI device group: 0x%x\n",
15427 phba->pci_dev_grp);
15428 break;
15429 }
15430 return rc;
15431}
15432
15433/**
15434 * lpfc_io_error_detected - lpfc method for handling PCI I/O error
15435 * @pdev: pointer to PCI device.
15436 * @state: the current PCI connection state.
15437 *
15438 * This routine is registered to the PCI subsystem for error handling. This
15439 * function is called by the PCI subsystem after a PCI bus error affecting
15440 * this device has been detected. When this routine is invoked, it dispatches
15441 * the action to the proper SLI-3 or SLI-4 device error detected handling
15442 * routine, which will perform the proper error detected operation.
15443 *
15444 * Return codes
15445 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
15446 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
15447 **/
15448static pci_ers_result_t
15449lpfc_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
15450{
15451 struct Scsi_Host *shost = pci_get_drvdata(pdev);
15452 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
15453 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
15454
25ac2c97
JS
15455 if (phba->link_state == LPFC_HBA_ERROR &&
15456 phba->hba_flag & HBA_IOQ_FLUSH)
15457 return PCI_ERS_RESULT_NEED_RESET;
15458
3772a991
JS
15459 switch (phba->pci_dev_grp) {
15460 case LPFC_PCI_DEV_LP:
15461 rc = lpfc_io_error_detected_s3(pdev, state);
15462 break;
da0436e9
JS
15463 case LPFC_PCI_DEV_OC:
15464 rc = lpfc_io_error_detected_s4(pdev, state);
15465 break;
3772a991 15466 default:
372c187b 15467 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
15468 "1427 Invalid PCI device group: 0x%x\n",
15469 phba->pci_dev_grp);
15470 break;
15471 }
15472 return rc;
15473}
15474
15475/**
15476 * lpfc_io_slot_reset - lpfc method for restart PCI dev from scratch
15477 * @pdev: pointer to PCI device.
15478 *
15479 * This routine is registered to the PCI subsystem for error handling. This
15480 * function is called after PCI bus has been reset to restart the PCI card
15481 * from scratch, as if from a cold-boot. When this routine is invoked, it
15482 * dispatches the action to the proper SLI-3 or SLI-4 device reset handling
15483 * routine, which will perform the proper device reset.
15484 *
15485 * Return codes
15486 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
15487 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
15488 **/
15489static pci_ers_result_t
15490lpfc_io_slot_reset(struct pci_dev *pdev)
15491{
15492 struct Scsi_Host *shost = pci_get_drvdata(pdev);
15493 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
15494 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
15495
15496 switch (phba->pci_dev_grp) {
15497 case LPFC_PCI_DEV_LP:
15498 rc = lpfc_io_slot_reset_s3(pdev);
15499 break;
da0436e9
JS
15500 case LPFC_PCI_DEV_OC:
15501 rc = lpfc_io_slot_reset_s4(pdev);
15502 break;
3772a991 15503 default:
372c187b 15504 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
15505 "1428 Invalid PCI device group: 0x%x\n",
15506 phba->pci_dev_grp);
15507 break;
15508 }
15509 return rc;
15510}
15511
15512/**
15513 * lpfc_io_resume - lpfc method for resuming PCI I/O operation
15514 * @pdev: pointer to PCI device
15515 *
15516 * This routine is registered to the PCI subsystem for error handling. It
15517 * is called when kernel error recovery tells the lpfc driver that it is
15518 * OK to resume normal PCI operation after PCI bus error recovery. When
15519 * this routine is invoked, it dispatches the action to the proper SLI-3
15520 * or SLI-4 device io_resume routine, which will resume the device operation.
15521 **/
15522static void
15523lpfc_io_resume(struct pci_dev *pdev)
15524{
15525 struct Scsi_Host *shost = pci_get_drvdata(pdev);
15526 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
15527
15528 switch (phba->pci_dev_grp) {
15529 case LPFC_PCI_DEV_LP:
15530 lpfc_io_resume_s3(pdev);
15531 break;
da0436e9
JS
15532 case LPFC_PCI_DEV_OC:
15533 lpfc_io_resume_s4(pdev);
15534 break;
3772a991 15535 default:
372c187b 15536 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
15537 "1429 Invalid PCI device group: 0x%x\n",
15538 phba->pci_dev_grp);
15539 break;
15540 }
15541 return;
15542}
15543
1ba981fd
JS
15544/**
15545 * lpfc_sli4_oas_verify - Verify OAS is supported by this adapter
15546 * @phba: pointer to lpfc hba data structure.
15547 *
15548 * This routine checks to see if OAS is supported for this adapter. If
15549 * supported, the configure Flash Optimized Fabric flag is set. Otherwise,
15550 * the enable oas flag is cleared and the pool created for OAS device data
15551 * is destroyed.
15552 *
15553 **/
c7092975 15554static void
1ba981fd
JS
15555lpfc_sli4_oas_verify(struct lpfc_hba *phba)
15556{
15557
15558 if (!phba->cfg_EnableXLane)
15559 return;
15560
15561 if (phba->sli4_hba.pc_sli4_params.oas_supported) {
15562 phba->cfg_fof = 1;
15563 } else {
f38fa0bb 15564 phba->cfg_fof = 0;
c3e5aac3 15565 mempool_destroy(phba->device_data_mem_pool);
1ba981fd
JS
15566 phba->device_data_mem_pool = NULL;
15567 }
15568
15569 return;
15570}
15571
d2cc9bcd
JS
15572/**
15573 * lpfc_sli4_ras_init - Verify RAS-FW log is supported by this adapter
15574 * @phba: pointer to lpfc hba data structure.
15575 *
15576 * This routine checks to see if RAS is supported by the adapter. Check the
15577 * function through which RAS support enablement is to be done.
15578 **/
15579void
15580lpfc_sli4_ras_init(struct lpfc_hba *phba)
15581{
f6c5e6c4
JS
15582 /* if ASIC_GEN_NUM >= 0xC) */
15583 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
15584 LPFC_SLI_INTF_IF_TYPE_6) ||
15585 (bf_get(lpfc_sli_intf_sli_family, &phba->sli4_hba.sli_intf) ==
15586 LPFC_SLI_INTF_FAMILY_G6)) {
d2cc9bcd 15587 phba->ras_fwlog.ras_hwsupport = true;
cb34990b
JS
15588 if (phba->cfg_ras_fwlog_func == PCI_FUNC(phba->pcidev->devfn) &&
15589 phba->cfg_ras_fwlog_buffsize)
d2cc9bcd
JS
15590 phba->ras_fwlog.ras_enabled = true;
15591 else
15592 phba->ras_fwlog.ras_enabled = false;
f6c5e6c4 15593 } else {
d2cc9bcd
JS
15594 phba->ras_fwlog.ras_hwsupport = false;
15595 }
15596}
15597
1ba981fd 15598
dea3101e 15599MODULE_DEVICE_TABLE(pci, lpfc_id_table);
15600
a55b2d21 15601static const struct pci_error_handlers lpfc_err_handler = {
8d63f375
LV
15602 .error_detected = lpfc_io_error_detected,
15603 .slot_reset = lpfc_io_slot_reset,
15604 .resume = lpfc_io_resume,
15605};
15606
ef6fa16b
VG
15607static SIMPLE_DEV_PM_OPS(lpfc_pci_pm_ops_one,
15608 lpfc_pci_suspend_one,
15609 lpfc_pci_resume_one);
15610
dea3101e 15611static struct pci_driver lpfc_driver = {
15612 .name = LPFC_DRIVER_NAME,
15613 .id_table = lpfc_id_table,
15614 .probe = lpfc_pci_probe_one,
6f039790 15615 .remove = lpfc_pci_remove_one,
85e8a239 15616 .shutdown = lpfc_pci_remove_one,
ef6fa16b 15617 .driver.pm = &lpfc_pci_pm_ops_one,
2e0fef85 15618 .err_handler = &lpfc_err_handler,
dea3101e 15619};
15620
3ef6d24c 15621static const struct file_operations lpfc_mgmt_fop = {
858feacd 15622 .owner = THIS_MODULE,
3ef6d24c
JS
15623};
15624
15625static struct miscdevice lpfc_mgmt_dev = {
15626 .minor = MISC_DYNAMIC_MINOR,
15627 .name = "lpfcmgmt",
15628 .fops = &lpfc_mgmt_fop,
15629};
15630
e59058c4 15631/**
3621a710 15632 * lpfc_init - lpfc module initialization routine
e59058c4
JS
15633 *
15634 * This routine is to be invoked when the lpfc module is loaded into the
15635 * kernel. The special kernel macro module_init() is used to indicate the
15636 * role of this routine to the kernel as lpfc module entry point.
15637 *
15638 * Return codes
15639 * 0 - successful
15640 * -ENOMEM - FC attach transport failed
15641 * all others - failed
15642 */
dea3101e 15643static int __init
15644lpfc_init(void)
15645{
15646 int error = 0;
15647
bc2736e9
AB
15648 pr_info(LPFC_MODULE_DESC "\n");
15649 pr_info(LPFC_COPYRIGHT "\n");
dea3101e 15650
3ef6d24c
JS
15651 error = misc_register(&lpfc_mgmt_dev);
15652 if (error)
15653 printk(KERN_ERR "Could not register lpfcmgmt device, "
15654 "misc_register returned with status %d", error);
15655
1eaff536 15656 error = -ENOMEM;
458c083e
JS
15657 lpfc_transport_functions.vport_create = lpfc_vport_create;
15658 lpfc_transport_functions.vport_delete = lpfc_vport_delete;
dea3101e 15659 lpfc_transport_template =
15660 fc_attach_transport(&lpfc_transport_functions);
7ee5d43e 15661 if (lpfc_transport_template == NULL)
1eaff536 15662 goto unregister;
458c083e
JS
15663 lpfc_vport_transport_template =
15664 fc_attach_transport(&lpfc_vport_transport_functions);
15665 if (lpfc_vport_transport_template == NULL) {
15666 fc_release_transport(lpfc_transport_template);
1eaff536 15667 goto unregister;
7ee5d43e 15668 }
840a4701 15669 lpfc_wqe_cmd_template();
bd3061ba 15670 lpfc_nvmet_cmd_template();
7bb03bbf
JS
15671
15672 /* Initialize in case vector mapping is needed */
2ea259ee 15673 lpfc_present_cpu = num_present_cpus();
7bb03bbf 15674
a5b141a8
JS
15675 lpfc_pldv_detect = false;
15676
93a4d6f4
JS
15677 error = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
15678 "lpfc/sli4:online",
15679 lpfc_cpu_online, lpfc_cpu_offline);
15680 if (error < 0)
15681 goto cpuhp_failure;
15682 lpfc_cpuhp_state = error;
15683
dea3101e 15684 error = pci_register_driver(&lpfc_driver);
93a4d6f4
JS
15685 if (error)
15686 goto unwind;
15687
15688 return error;
15689
15690unwind:
15691 cpuhp_remove_multi_state(lpfc_cpuhp_state);
15692cpuhp_failure:
15693 fc_release_transport(lpfc_transport_template);
15694 fc_release_transport(lpfc_vport_transport_template);
1eaff536
JX
15695unregister:
15696 misc_deregister(&lpfc_mgmt_dev);
dea3101e 15697
15698 return error;
15699}
15700
372c187b
DK
15701void lpfc_dmp_dbg(struct lpfc_hba *phba)
15702{
15703 unsigned int start_idx;
15704 unsigned int dbg_cnt;
15705 unsigned int temp_idx;
15706 int i;
15707 int j = 0;
e294647b 15708 unsigned long rem_nsec;
0b3ad32e 15709
372c187b
DK
15710 if (atomic_cmpxchg(&phba->dbg_log_dmping, 0, 1) != 0)
15711 return;
15712
15713 start_idx = (unsigned int)atomic_read(&phba->dbg_log_idx) % DBG_LOG_SZ;
15714 dbg_cnt = (unsigned int)atomic_read(&phba->dbg_log_cnt);
0b3ad32e
JS
15715 if (!dbg_cnt)
15716 goto out;
372c187b
DK
15717 temp_idx = start_idx;
15718 if (dbg_cnt >= DBG_LOG_SZ) {
15719 dbg_cnt = DBG_LOG_SZ;
15720 temp_idx -= 1;
15721 } else {
15722 if ((start_idx + dbg_cnt) > (DBG_LOG_SZ - 1)) {
15723 temp_idx = (start_idx + dbg_cnt) % DBG_LOG_SZ;
15724 } else {
77dd7d7b 15725 if (start_idx < dbg_cnt)
372c187b 15726 start_idx = DBG_LOG_SZ - (dbg_cnt - start_idx);
77dd7d7b 15727 else
372c187b 15728 start_idx -= dbg_cnt;
372c187b
DK
15729 }
15730 }
15731 dev_info(&phba->pcidev->dev, "start %d end %d cnt %d\n",
15732 start_idx, temp_idx, dbg_cnt);
15733
15734 for (i = 0; i < dbg_cnt; i++) {
15735 if ((start_idx + i) < DBG_LOG_SZ)
77dd7d7b 15736 temp_idx = (start_idx + i) % DBG_LOG_SZ;
372c187b
DK
15737 else
15738 temp_idx = j++;
15739 rem_nsec = do_div(phba->dbg_log[temp_idx].t_ns, NSEC_PER_SEC);
15740 dev_info(&phba->pcidev->dev, "%d: [%5lu.%06lu] %s",
15741 temp_idx,
15742 (unsigned long)phba->dbg_log[temp_idx].t_ns,
15743 rem_nsec / 1000,
15744 phba->dbg_log[temp_idx].log);
15745 }
0b3ad32e 15746out:
372c187b
DK
15747 atomic_set(&phba->dbg_log_cnt, 0);
15748 atomic_set(&phba->dbg_log_dmping, 0);
15749}
15750
7fa03c77 15751__printf(2, 3)
372c187b
DK
15752void lpfc_dbg_print(struct lpfc_hba *phba, const char *fmt, ...)
15753{
15754 unsigned int idx;
15755 va_list args;
15756 int dbg_dmping = atomic_read(&phba->dbg_log_dmping);
15757 struct va_format vaf;
15758
15759
15760 va_start(args, fmt);
15761 if (unlikely(dbg_dmping)) {
15762 vaf.fmt = fmt;
15763 vaf.va = &args;
15764 dev_info(&phba->pcidev->dev, "%pV", &vaf);
15765 va_end(args);
15766 return;
15767 }
15768 idx = (unsigned int)atomic_fetch_add(1, &phba->dbg_log_idx) %
15769 DBG_LOG_SZ;
15770
15771 atomic_inc(&phba->dbg_log_cnt);
15772
15773 vscnprintf(phba->dbg_log[idx].log,
15774 sizeof(phba->dbg_log[idx].log), fmt, args);
15775 va_end(args);
15776
15777 phba->dbg_log[idx].t_ns = local_clock();
15778}
15779
e59058c4 15780/**
3621a710 15781 * lpfc_exit - lpfc module removal routine
e59058c4
JS
15782 *
15783 * This routine is invoked when the lpfc module is removed from the kernel.
15784 * The special kernel macro module_exit() is used to indicate the role of
15785 * this routine to the kernel as lpfc module exit point.
15786 */
dea3101e 15787static void __exit
15788lpfc_exit(void)
15789{
3ef6d24c 15790 misc_deregister(&lpfc_mgmt_dev);
dea3101e 15791 pci_unregister_driver(&lpfc_driver);
93a4d6f4 15792 cpuhp_remove_multi_state(lpfc_cpuhp_state);
dea3101e 15793 fc_release_transport(lpfc_transport_template);
458c083e 15794 fc_release_transport(lpfc_vport_transport_template);
7973967f 15795 idr_destroy(&lpfc_hba_index);
dea3101e 15796}
15797
15798module_init(lpfc_init);
15799module_exit(lpfc_exit);
15800MODULE_LICENSE("GPL");
15801MODULE_DESCRIPTION(LPFC_MODULE_DESC);
d080abe0 15802MODULE_AUTHOR("Broadcom");
dea3101e 15803MODULE_VERSION("0:" LPFC_DRIVER_VERSION);