scsi: lpfc: Implement health checking when aborting I/O
[linux-2.6-block.git] / drivers / scsi / lpfc / lpfc_init.c
CommitLineData
dea3101e 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
145e5a8a 4 * Copyright (C) 2017-2020 Broadcom. All Rights Reserved. The term *
3e21d1cb 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
50611577 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
c44ce173 7 * EMULEX and SLI are trademarks of Emulex. *
d080abe0 8 * www.broadcom.com *
c44ce173 9 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
dea3101e 10 * *
11 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC
12 * modify it under the terms of version 2 of the GNU General *
13 * Public License as published by the Free Software Foundation. *
14 * This program is distributed in the hope that it will be useful. *
15 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
16 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
18 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
19 * TO BE LEGALLY INVALID. See the GNU General Public License for *
20 * more details, a copy of which can be found in the file COPYING *
21 * included with this package. *
dea3101e 22 *******************************************************************/
23
dea3101e 24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/idr.h>
28#include <linux/interrupt.h>
acf3368f 29#include <linux/module.h>
dea3101e 30#include <linux/kthread.h>
31#include <linux/pci.h>
32#include <linux/spinlock.h>
92d7f7b0 33#include <linux/ctype.h>
0d878419 34#include <linux/aer.h>
5a0e3ad6 35#include <linux/slab.h>
52d52440 36#include <linux/firmware.h>
3ef6d24c 37#include <linux/miscdevice.h>
7bb03bbf 38#include <linux/percpu.h>
895427bd 39#include <linux/msi.h>
6a828b0f 40#include <linux/irq.h>
286871a6 41#include <linux/bitops.h>
31f06d2e 42#include <linux/crash_dump.h>
dcaa2136 43#include <linux/cpu.h>
93a4d6f4 44#include <linux/cpuhotplug.h>
dea3101e 45
91886523 46#include <scsi/scsi.h>
dea3101e 47#include <scsi/scsi_device.h>
48#include <scsi/scsi_host.h>
49#include <scsi/scsi_transport_fc.h>
86c67379
JS
50#include <scsi/scsi_tcq.h>
51#include <scsi/fc/fc_fs.h>
52
da0436e9 53#include "lpfc_hw4.h"
dea3101e 54#include "lpfc_hw.h"
55#include "lpfc_sli.h"
da0436e9 56#include "lpfc_sli4.h"
ea2151b4 57#include "lpfc_nl.h"
dea3101e 58#include "lpfc_disc.h"
dea3101e 59#include "lpfc.h"
895427bd
JS
60#include "lpfc_scsi.h"
61#include "lpfc_nvme.h"
dea3101e 62#include "lpfc_logmsg.h"
63#include "lpfc_crtn.h"
92d7f7b0 64#include "lpfc_vport.h"
dea3101e 65#include "lpfc_version.h"
12f44457 66#include "lpfc_ids.h"
dea3101e 67
93a4d6f4 68static enum cpuhp_state lpfc_cpuhp_state;
7bb03bbf 69/* Used when mapping IRQ vectors in a driver centric manner */
d7b761b0 70static uint32_t lpfc_present_cpu;
7bb03bbf 71
93a4d6f4
JS
72static void __lpfc_cpuhp_remove(struct lpfc_hba *phba);
73static void lpfc_cpuhp_remove(struct lpfc_hba *phba);
74static void lpfc_cpuhp_add(struct lpfc_hba *phba);
dea3101e 75static void lpfc_get_hba_model_desc(struct lpfc_hba *, uint8_t *, uint8_t *);
76static int lpfc_post_rcv_buf(struct lpfc_hba *);
5350d872 77static int lpfc_sli4_queue_verify(struct lpfc_hba *);
da0436e9
JS
78static int lpfc_create_bootstrap_mbox(struct lpfc_hba *);
79static int lpfc_setup_endian_order(struct lpfc_hba *);
da0436e9 80static void lpfc_destroy_bootstrap_mbox(struct lpfc_hba *);
8a9d2e80 81static void lpfc_free_els_sgl_list(struct lpfc_hba *);
f358dd0c 82static void lpfc_free_nvmet_sgl_list(struct lpfc_hba *);
8a9d2e80 83static void lpfc_init_sgl_list(struct lpfc_hba *);
da0436e9
JS
84static int lpfc_init_active_sgl_array(struct lpfc_hba *);
85static void lpfc_free_active_sgl(struct lpfc_hba *);
86static int lpfc_hba_down_post_s3(struct lpfc_hba *phba);
87static int lpfc_hba_down_post_s4(struct lpfc_hba *phba);
88static int lpfc_sli4_cq_event_pool_create(struct lpfc_hba *);
89static void lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *);
90static void lpfc_sli4_cq_event_release_all(struct lpfc_hba *);
618a5230
JS
91static void lpfc_sli4_disable_intr(struct lpfc_hba *);
92static uint32_t lpfc_sli4_enable_intr(struct lpfc_hba *, uint32_t);
1ba981fd 93static void lpfc_sli4_oas_verify(struct lpfc_hba *phba);
6a828b0f 94static uint16_t lpfc_find_cpu_handle(struct lpfc_hba *, uint16_t, int);
aa6ff309 95static void lpfc_setup_bg(struct lpfc_hba *, struct Scsi_Host *);
dea3101e 96
97static struct scsi_transport_template *lpfc_transport_template = NULL;
92d7f7b0 98static struct scsi_transport_template *lpfc_vport_transport_template = NULL;
dea3101e 99static DEFINE_IDR(lpfc_hba_index);
f358dd0c 100#define LPFC_NVMET_BUF_POST 254
dea3101e 101
e59058c4 102/**
3621a710 103 * lpfc_config_port_prep - Perform lpfc initialization prior to config port
e59058c4
JS
104 * @phba: pointer to lpfc hba data structure.
105 *
106 * This routine will do LPFC initialization prior to issuing the CONFIG_PORT
107 * mailbox command. It retrieves the revision information from the HBA and
108 * collects the Vital Product Data (VPD) about the HBA for preparing the
109 * configuration of the HBA.
110 *
111 * Return codes:
112 * 0 - success.
113 * -ERESTART - requests the SLI layer to reset the HBA and try again.
114 * Any other value - indicates an error.
115 **/
dea3101e 116int
2e0fef85 117lpfc_config_port_prep(struct lpfc_hba *phba)
dea3101e 118{
119 lpfc_vpd_t *vp = &phba->vpd;
120 int i = 0, rc;
121 LPFC_MBOXQ_t *pmb;
122 MAILBOX_t *mb;
123 char *lpfc_vpd_data = NULL;
124 uint16_t offset = 0;
125 static char licensed[56] =
126 "key unlock for use with gnu public licensed code only\0";
65a29c16 127 static int init_key = 1;
dea3101e 128
129 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
130 if (!pmb) {
2e0fef85 131 phba->link_state = LPFC_HBA_ERROR;
dea3101e 132 return -ENOMEM;
133 }
134
04c68496 135 mb = &pmb->u.mb;
2e0fef85 136 phba->link_state = LPFC_INIT_MBX_CMDS;
dea3101e 137
138 if (lpfc_is_LC_HBA(phba->pcidev->device)) {
65a29c16
JS
139 if (init_key) {
140 uint32_t *ptext = (uint32_t *) licensed;
dea3101e 141
65a29c16
JS
142 for (i = 0; i < 56; i += sizeof (uint32_t), ptext++)
143 *ptext = cpu_to_be32(*ptext);
144 init_key = 0;
145 }
dea3101e 146
147 lpfc_read_nv(phba, pmb);
148 memset((char*)mb->un.varRDnvp.rsvd3, 0,
149 sizeof (mb->un.varRDnvp.rsvd3));
150 memcpy((char*)mb->un.varRDnvp.rsvd3, licensed,
151 sizeof (licensed));
152
153 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
154
155 if (rc != MBX_SUCCESS) {
372c187b 156 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 157 "0324 Config Port initialization "
dea3101e 158 "error, mbxCmd x%x READ_NVPARM, "
159 "mbxStatus x%x\n",
dea3101e 160 mb->mbxCommand, mb->mbxStatus);
161 mempool_free(pmb, phba->mbox_mem_pool);
162 return -ERESTART;
163 }
164 memcpy(phba->wwnn, (char *)mb->un.varRDnvp.nodename,
2e0fef85
JS
165 sizeof(phba->wwnn));
166 memcpy(phba->wwpn, (char *)mb->un.varRDnvp.portname,
167 sizeof(phba->wwpn));
dea3101e 168 }
169
dfb75133
MW
170 /*
171 * Clear all option bits except LPFC_SLI3_BG_ENABLED,
172 * which was already set in lpfc_get_cfgparam()
173 */
174 phba->sli3_options &= (uint32_t)LPFC_SLI3_BG_ENABLED;
92d7f7b0 175
dea3101e 176 /* Setup and issue mailbox READ REV command */
177 lpfc_read_rev(phba, pmb);
178 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
179 if (rc != MBX_SUCCESS) {
372c187b 180 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 181 "0439 Adapter failed to init, mbxCmd x%x "
dea3101e 182 "READ_REV, mbxStatus x%x\n",
dea3101e 183 mb->mbxCommand, mb->mbxStatus);
184 mempool_free( pmb, phba->mbox_mem_pool);
185 return -ERESTART;
186 }
187
92d7f7b0 188
1de933f3
JSEC
189 /*
190 * The value of rr must be 1 since the driver set the cv field to 1.
191 * This setting requires the FW to set all revision fields.
dea3101e 192 */
1de933f3 193 if (mb->un.varRdRev.rr == 0) {
dea3101e 194 vp->rev.rBit = 0;
372c187b 195 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011
JS
196 "0440 Adapter failed to init, READ_REV has "
197 "missing revision information.\n");
dea3101e 198 mempool_free(pmb, phba->mbox_mem_pool);
199 return -ERESTART;
dea3101e 200 }
201
495a714c
JS
202 if (phba->sli_rev == 3 && !mb->un.varRdRev.v3rsp) {
203 mempool_free(pmb, phba->mbox_mem_pool);
ed957684 204 return -EINVAL;
495a714c 205 }
ed957684 206
dea3101e 207 /* Save information as VPD data */
1de933f3 208 vp->rev.rBit = 1;
92d7f7b0 209 memcpy(&vp->sli3Feat, &mb->un.varRdRev.sli3Feat, sizeof(uint32_t));
1de933f3
JSEC
210 vp->rev.sli1FwRev = mb->un.varRdRev.sli1FwRev;
211 memcpy(vp->rev.sli1FwName, (char*) mb->un.varRdRev.sli1FwName, 16);
212 vp->rev.sli2FwRev = mb->un.varRdRev.sli2FwRev;
213 memcpy(vp->rev.sli2FwName, (char *) mb->un.varRdRev.sli2FwName, 16);
dea3101e 214 vp->rev.biuRev = mb->un.varRdRev.biuRev;
215 vp->rev.smRev = mb->un.varRdRev.smRev;
216 vp->rev.smFwRev = mb->un.varRdRev.un.smFwRev;
217 vp->rev.endecRev = mb->un.varRdRev.endecRev;
218 vp->rev.fcphHigh = mb->un.varRdRev.fcphHigh;
219 vp->rev.fcphLow = mb->un.varRdRev.fcphLow;
220 vp->rev.feaLevelHigh = mb->un.varRdRev.feaLevelHigh;
221 vp->rev.feaLevelLow = mb->un.varRdRev.feaLevelLow;
222 vp->rev.postKernRev = mb->un.varRdRev.postKernRev;
223 vp->rev.opFwRev = mb->un.varRdRev.opFwRev;
224
92d7f7b0
JS
225 /* If the sli feature level is less then 9, we must
226 * tear down all RPIs and VPIs on link down if NPIV
227 * is enabled.
228 */
229 if (vp->rev.feaLevelHigh < 9)
230 phba->sli3_options |= LPFC_SLI3_VPORT_TEARDOWN;
231
dea3101e 232 if (lpfc_is_LC_HBA(phba->pcidev->device))
233 memcpy(phba->RandomData, (char *)&mb->un.varWords[24],
234 sizeof (phba->RandomData));
235
dea3101e 236 /* Get adapter VPD information */
dea3101e 237 lpfc_vpd_data = kmalloc(DMP_VPD_SIZE, GFP_KERNEL);
238 if (!lpfc_vpd_data)
d7c255b2 239 goto out_free_mbox;
dea3101e 240 do {
a0c87cbd 241 lpfc_dump_mem(phba, pmb, offset, DMP_REGION_VPD);
dea3101e 242 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
243
244 if (rc != MBX_SUCCESS) {
245 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011 246 "0441 VPD not present on adapter, "
dea3101e 247 "mbxCmd x%x DUMP VPD, mbxStatus x%x\n",
dea3101e 248 mb->mbxCommand, mb->mbxStatus);
74b72a59 249 mb->un.varDmp.word_cnt = 0;
dea3101e 250 }
04c68496
JS
251 /* dump mem may return a zero when finished or we got a
252 * mailbox error, either way we are done.
253 */
254 if (mb->un.varDmp.word_cnt == 0)
255 break;
d91e3abb
DK
256
257 i = mb->un.varDmp.word_cnt * sizeof(uint32_t);
258 if (offset + i > DMP_VPD_SIZE)
259 i = DMP_VPD_SIZE - offset;
d7c255b2 260 lpfc_sli_pcimem_bcopy(((uint8_t *)mb) + DMP_RSP_OFFSET,
d91e3abb
DK
261 lpfc_vpd_data + offset, i);
262 offset += i;
263 } while (offset < DMP_VPD_SIZE);
264
74b72a59 265 lpfc_parse_vpd(phba, lpfc_vpd_data, offset);
dea3101e 266
267 kfree(lpfc_vpd_data);
dea3101e 268out_free_mbox:
269 mempool_free(pmb, phba->mbox_mem_pool);
270 return 0;
271}
272
e59058c4 273/**
3621a710 274 * lpfc_config_async_cmpl - Completion handler for config async event mbox cmd
e59058c4
JS
275 * @phba: pointer to lpfc hba data structure.
276 * @pmboxq: pointer to the driver internal queue element for mailbox command.
277 *
278 * This is the completion handler for driver's configuring asynchronous event
279 * mailbox command to the device. If the mailbox command returns successfully,
280 * it will set internal async event support flag to 1; otherwise, it will
281 * set internal async event support flag to 0.
282 **/
57127f15
JS
283static void
284lpfc_config_async_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
285{
04c68496 286 if (pmboxq->u.mb.mbxStatus == MBX_SUCCESS)
57127f15
JS
287 phba->temp_sensor_support = 1;
288 else
289 phba->temp_sensor_support = 0;
290 mempool_free(pmboxq, phba->mbox_mem_pool);
291 return;
292}
293
97207482 294/**
3621a710 295 * lpfc_dump_wakeup_param_cmpl - dump memory mailbox command completion handler
97207482
JS
296 * @phba: pointer to lpfc hba data structure.
297 * @pmboxq: pointer to the driver internal queue element for mailbox command.
298 *
299 * This is the completion handler for dump mailbox command for getting
300 * wake up parameters. When this command complete, the response contain
301 * Option rom version of the HBA. This function translate the version number
302 * into a human readable string and store it in OptionROMVersion.
303 **/
304static void
305lpfc_dump_wakeup_param_cmpl(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmboxq)
306{
307 struct prog_id *prg;
308 uint32_t prog_id_word;
309 char dist = ' ';
310 /* character array used for decoding dist type. */
311 char dist_char[] = "nabx";
312
04c68496 313 if (pmboxq->u.mb.mbxStatus != MBX_SUCCESS) {
9f1e1b50 314 mempool_free(pmboxq, phba->mbox_mem_pool);
97207482 315 return;
9f1e1b50 316 }
97207482
JS
317
318 prg = (struct prog_id *) &prog_id_word;
319
320 /* word 7 contain option rom version */
04c68496 321 prog_id_word = pmboxq->u.mb.un.varWords[7];
97207482
JS
322
323 /* Decode the Option rom version word to a readable string */
324 if (prg->dist < 4)
325 dist = dist_char[prg->dist];
326
327 if ((prg->dist == 3) && (prg->num == 0))
a2fc4aef 328 snprintf(phba->OptionROMVersion, 32, "%d.%d%d",
97207482
JS
329 prg->ver, prg->rev, prg->lev);
330 else
a2fc4aef 331 snprintf(phba->OptionROMVersion, 32, "%d.%d%d%c%d",
97207482
JS
332 prg->ver, prg->rev, prg->lev,
333 dist, prg->num);
9f1e1b50 334 mempool_free(pmboxq, phba->mbox_mem_pool);
97207482
JS
335 return;
336}
337
0558056c
JS
338/**
339 * lpfc_update_vport_wwn - Updates the fc_nodename, fc_portname,
340 * cfg_soft_wwnn, cfg_soft_wwpn
341 * @vport: pointer to lpfc vport data structure.
342 *
343 *
344 * Return codes
345 * None.
346 **/
347void
348lpfc_update_vport_wwn(struct lpfc_vport *vport)
349{
aeb3c817
JS
350 uint8_t vvvl = vport->fc_sparam.cmn.valid_vendor_ver_level;
351 u32 *fawwpn_key = (u32 *)&vport->fc_sparam.un.vendorVersion[0];
352
0558056c
JS
353 /* If the soft name exists then update it using the service params */
354 if (vport->phba->cfg_soft_wwnn)
355 u64_to_wwn(vport->phba->cfg_soft_wwnn,
356 vport->fc_sparam.nodeName.u.wwn);
357 if (vport->phba->cfg_soft_wwpn)
358 u64_to_wwn(vport->phba->cfg_soft_wwpn,
359 vport->fc_sparam.portName.u.wwn);
360
361 /*
362 * If the name is empty or there exists a soft name
363 * then copy the service params name, otherwise use the fc name
364 */
365 if (vport->fc_nodename.u.wwn[0] == 0 || vport->phba->cfg_soft_wwnn)
366 memcpy(&vport->fc_nodename, &vport->fc_sparam.nodeName,
367 sizeof(struct lpfc_name));
368 else
369 memcpy(&vport->fc_sparam.nodeName, &vport->fc_nodename,
370 sizeof(struct lpfc_name));
371
aeb3c817
JS
372 /*
373 * If the port name has changed, then set the Param changes flag
374 * to unreg the login
375 */
376 if (vport->fc_portname.u.wwn[0] != 0 &&
377 memcmp(&vport->fc_portname, &vport->fc_sparam.portName,
378 sizeof(struct lpfc_name)))
379 vport->vport_flag |= FAWWPN_PARAM_CHG;
380
381 if (vport->fc_portname.u.wwn[0] == 0 ||
382 vport->phba->cfg_soft_wwpn ||
383 (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR) ||
384 vport->vport_flag & FAWWPN_SET) {
0558056c
JS
385 memcpy(&vport->fc_portname, &vport->fc_sparam.portName,
386 sizeof(struct lpfc_name));
aeb3c817
JS
387 vport->vport_flag &= ~FAWWPN_SET;
388 if (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR)
389 vport->vport_flag |= FAWWPN_SET;
390 }
0558056c
JS
391 else
392 memcpy(&vport->fc_sparam.portName, &vport->fc_portname,
393 sizeof(struct lpfc_name));
394}
395
e59058c4 396/**
3621a710 397 * lpfc_config_port_post - Perform lpfc initialization after config port
e59058c4
JS
398 * @phba: pointer to lpfc hba data structure.
399 *
400 * This routine will do LPFC initialization after the CONFIG_PORT mailbox
401 * command call. It performs all internal resource and state setups on the
402 * port: post IOCB buffers, enable appropriate host interrupt attentions,
403 * ELS ring timers, etc.
404 *
405 * Return codes
406 * 0 - success.
407 * Any other value - error.
408 **/
dea3101e 409int
2e0fef85 410lpfc_config_port_post(struct lpfc_hba *phba)
dea3101e 411{
2e0fef85 412 struct lpfc_vport *vport = phba->pport;
a257bf90 413 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
dea3101e 414 LPFC_MBOXQ_t *pmb;
415 MAILBOX_t *mb;
416 struct lpfc_dmabuf *mp;
417 struct lpfc_sli *psli = &phba->sli;
418 uint32_t status, timeout;
2e0fef85
JS
419 int i, j;
420 int rc;
dea3101e 421
7af67051
JS
422 spin_lock_irq(&phba->hbalock);
423 /*
424 * If the Config port completed correctly the HBA is not
425 * over heated any more.
426 */
427 if (phba->over_temp_state == HBA_OVER_TEMP)
428 phba->over_temp_state = HBA_NORMAL_TEMP;
429 spin_unlock_irq(&phba->hbalock);
430
dea3101e 431 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
432 if (!pmb) {
2e0fef85 433 phba->link_state = LPFC_HBA_ERROR;
dea3101e 434 return -ENOMEM;
435 }
04c68496 436 mb = &pmb->u.mb;
dea3101e 437
dea3101e 438 /* Get login parameters for NID. */
9f1177a3
JS
439 rc = lpfc_read_sparam(phba, pmb, 0);
440 if (rc) {
441 mempool_free(pmb, phba->mbox_mem_pool);
442 return -ENOMEM;
443 }
444
ed957684 445 pmb->vport = vport;
dea3101e 446 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
372c187b 447 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 448 "0448 Adapter failed init, mbxCmd x%x "
dea3101e 449 "READ_SPARM mbxStatus x%x\n",
dea3101e 450 mb->mbxCommand, mb->mbxStatus);
2e0fef85 451 phba->link_state = LPFC_HBA_ERROR;
3e1f0718 452 mp = (struct lpfc_dmabuf *)pmb->ctx_buf;
9f1177a3 453 mempool_free(pmb, phba->mbox_mem_pool);
dea3101e 454 lpfc_mbuf_free(phba, mp->virt, mp->phys);
455 kfree(mp);
456 return -EIO;
457 }
458
3e1f0718 459 mp = (struct lpfc_dmabuf *)pmb->ctx_buf;
dea3101e 460
2e0fef85 461 memcpy(&vport->fc_sparam, mp->virt, sizeof (struct serv_parm));
dea3101e 462 lpfc_mbuf_free(phba, mp->virt, mp->phys);
463 kfree(mp);
3e1f0718 464 pmb->ctx_buf = NULL;
0558056c 465 lpfc_update_vport_wwn(vport);
a257bf90
JS
466
467 /* Update the fc_host data structures with new wwn. */
468 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
469 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
21e9a0a5 470 fc_host_max_npiv_vports(shost) = phba->max_vpi;
a257bf90 471
dea3101e 472 /* If no serial number in VPD data, use low 6 bytes of WWNN */
473 /* This should be consolidated into parse_vpd ? - mr */
474 if (phba->SerialNumber[0] == 0) {
475 uint8_t *outptr;
476
2e0fef85 477 outptr = &vport->fc_nodename.u.s.IEEE[0];
dea3101e 478 for (i = 0; i < 12; i++) {
479 status = *outptr++;
480 j = ((status & 0xf0) >> 4);
481 if (j <= 9)
482 phba->SerialNumber[i] =
483 (char)((uint8_t) 0x30 + (uint8_t) j);
484 else
485 phba->SerialNumber[i] =
486 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
487 i++;
488 j = (status & 0xf);
489 if (j <= 9)
490 phba->SerialNumber[i] =
491 (char)((uint8_t) 0x30 + (uint8_t) j);
492 else
493 phba->SerialNumber[i] =
494 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
495 }
496 }
497
dea3101e 498 lpfc_read_config(phba, pmb);
ed957684 499 pmb->vport = vport;
dea3101e 500 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
372c187b 501 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 502 "0453 Adapter failed to init, mbxCmd x%x "
dea3101e 503 "READ_CONFIG, mbxStatus x%x\n",
dea3101e 504 mb->mbxCommand, mb->mbxStatus);
2e0fef85 505 phba->link_state = LPFC_HBA_ERROR;
dea3101e 506 mempool_free( pmb, phba->mbox_mem_pool);
507 return -EIO;
508 }
509
a0c87cbd
JS
510 /* Check if the port is disabled */
511 lpfc_sli_read_link_ste(phba);
512
dea3101e 513 /* Reset the DFT_HBA_Q_DEPTH to the max xri */
f6770e7d 514 if (phba->cfg_hba_queue_depth > mb->un.varRdConfig.max_xri) {
572709e2
JS
515 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
516 "3359 HBA queue depth changed from %d to %d\n",
f6770e7d
JS
517 phba->cfg_hba_queue_depth,
518 mb->un.varRdConfig.max_xri);
519 phba->cfg_hba_queue_depth = mb->un.varRdConfig.max_xri;
572709e2 520 }
dea3101e 521
522 phba->lmt = mb->un.varRdConfig.lmt;
74b72a59
JW
523
524 /* Get the default values for Model Name and Description */
525 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
526
2e0fef85 527 phba->link_state = LPFC_LINK_DOWN;
dea3101e 528
0b727fea 529 /* Only process IOCBs on ELS ring till hba_state is READY */
895427bd
JS
530 if (psli->sli3_ring[LPFC_EXTRA_RING].sli.sli3.cmdringaddr)
531 psli->sli3_ring[LPFC_EXTRA_RING].flag |= LPFC_STOP_IOCB_EVENT;
532 if (psli->sli3_ring[LPFC_FCP_RING].sli.sli3.cmdringaddr)
533 psli->sli3_ring[LPFC_FCP_RING].flag |= LPFC_STOP_IOCB_EVENT;
dea3101e 534
535 /* Post receive buffers for desired rings */
ed957684
JS
536 if (phba->sli_rev != 3)
537 lpfc_post_rcv_buf(phba);
dea3101e 538
9399627f
JS
539 /*
540 * Configure HBA MSI-X attention conditions to messages if MSI-X mode
541 */
542 if (phba->intr_type == MSIX) {
543 rc = lpfc_config_msi(phba, pmb);
544 if (rc) {
545 mempool_free(pmb, phba->mbox_mem_pool);
546 return -EIO;
547 }
548 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
549 if (rc != MBX_SUCCESS) {
372c187b 550 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
9399627f
JS
551 "0352 Config MSI mailbox command "
552 "failed, mbxCmd x%x, mbxStatus x%x\n",
04c68496
JS
553 pmb->u.mb.mbxCommand,
554 pmb->u.mb.mbxStatus);
9399627f
JS
555 mempool_free(pmb, phba->mbox_mem_pool);
556 return -EIO;
557 }
558 }
559
04c68496 560 spin_lock_irq(&phba->hbalock);
9399627f
JS
561 /* Initialize ERATT handling flag */
562 phba->hba_flag &= ~HBA_ERATT_HANDLED;
563
dea3101e 564 /* Enable appropriate host interrupts */
9940b97b
JS
565 if (lpfc_readl(phba->HCregaddr, &status)) {
566 spin_unlock_irq(&phba->hbalock);
567 return -EIO;
568 }
dea3101e 569 status |= HC_MBINT_ENA | HC_ERINT_ENA | HC_LAINT_ENA;
570 if (psli->num_rings > 0)
571 status |= HC_R0INT_ENA;
572 if (psli->num_rings > 1)
573 status |= HC_R1INT_ENA;
574 if (psli->num_rings > 2)
575 status |= HC_R2INT_ENA;
576 if (psli->num_rings > 3)
577 status |= HC_R3INT_ENA;
578
875fbdfe
JSEC
579 if ((phba->cfg_poll & ENABLE_FCP_RING_POLLING) &&
580 (phba->cfg_poll & DISABLE_FCP_RING_INT))
9399627f 581 status &= ~(HC_R0INT_ENA);
875fbdfe 582
dea3101e 583 writel(status, phba->HCregaddr);
584 readl(phba->HCregaddr); /* flush */
2e0fef85 585 spin_unlock_irq(&phba->hbalock);
dea3101e 586
9399627f
JS
587 /* Set up ring-0 (ELS) timer */
588 timeout = phba->fc_ratov * 2;
256ec0d0
JS
589 mod_timer(&vport->els_tmofunc,
590 jiffies + msecs_to_jiffies(1000 * timeout));
9399627f 591 /* Set up heart beat (HB) timer */
256ec0d0
JS
592 mod_timer(&phba->hb_tmofunc,
593 jiffies + msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
a22d73b6 594 phba->hba_flag &= ~(HBA_HBEAT_INP | HBA_HBEAT_TMO);
858c9f6c 595 phba->last_completion_time = jiffies;
9399627f 596 /* Set up error attention (ERATT) polling timer */
256ec0d0 597 mod_timer(&phba->eratt_poll,
65791f1f 598 jiffies + msecs_to_jiffies(1000 * phba->eratt_poll_interval));
dea3101e 599
a0c87cbd 600 if (phba->hba_flag & LINK_DISABLED) {
372c187b
DK
601 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
602 "2598 Adapter Link is disabled.\n");
a0c87cbd
JS
603 lpfc_down_link(phba, pmb);
604 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
605 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
606 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
372c187b
DK
607 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
608 "2599 Adapter failed to issue DOWN_LINK"
609 " mbox command rc 0x%x\n", rc);
a0c87cbd
JS
610
611 mempool_free(pmb, phba->mbox_mem_pool);
612 return -EIO;
613 }
e40a02c1 614 } else if (phba->cfg_suppress_link_up == LPFC_INITIALIZE_LINK) {
026abb87
JS
615 mempool_free(pmb, phba->mbox_mem_pool);
616 rc = phba->lpfc_hba_init_link(phba, MBX_NOWAIT);
617 if (rc)
618 return rc;
dea3101e 619 }
620 /* MBOX buffer will be freed in mbox compl */
57127f15 621 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9f1177a3
JS
622 if (!pmb) {
623 phba->link_state = LPFC_HBA_ERROR;
624 return -ENOMEM;
625 }
626
57127f15
JS
627 lpfc_config_async(phba, pmb, LPFC_ELS_RING);
628 pmb->mbox_cmpl = lpfc_config_async_cmpl;
629 pmb->vport = phba->pport;
630 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
dea3101e 631
57127f15 632 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
372c187b 633 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
57127f15 634 "0456 Adapter failed to issue "
e4e74273 635 "ASYNCEVT_ENABLE mbox status x%x\n",
57127f15
JS
636 rc);
637 mempool_free(pmb, phba->mbox_mem_pool);
638 }
97207482
JS
639
640 /* Get Option rom version */
641 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9f1177a3
JS
642 if (!pmb) {
643 phba->link_state = LPFC_HBA_ERROR;
644 return -ENOMEM;
645 }
646
97207482
JS
647 lpfc_dump_wakeup_param(phba, pmb);
648 pmb->mbox_cmpl = lpfc_dump_wakeup_param_cmpl;
649 pmb->vport = phba->pport;
650 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
651
652 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
372c187b
DK
653 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
654 "0435 Adapter failed "
e4e74273 655 "to get Option ROM version status x%x\n", rc);
97207482
JS
656 mempool_free(pmb, phba->mbox_mem_pool);
657 }
658
d7c255b2 659 return 0;
ce8b3ce5
JS
660}
661
84d1b006
JS
662/**
663 * lpfc_hba_init_link - Initialize the FC link
664 * @phba: pointer to lpfc hba data structure.
6e7288d9 665 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
84d1b006
JS
666 *
667 * This routine will issue the INIT_LINK mailbox command call.
668 * It is available to other drivers through the lpfc_hba data
669 * structure for use as a delayed link up mechanism with the
670 * module parameter lpfc_suppress_link_up.
671 *
672 * Return code
673 * 0 - success
674 * Any other value - error
675 **/
e399b228 676static int
6e7288d9 677lpfc_hba_init_link(struct lpfc_hba *phba, uint32_t flag)
1b51197d
JS
678{
679 return lpfc_hba_init_link_fc_topology(phba, phba->cfg_topology, flag);
680}
681
682/**
683 * lpfc_hba_init_link_fc_topology - Initialize FC link with desired topology
684 * @phba: pointer to lpfc hba data structure.
685 * @fc_topology: desired fc topology.
686 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
687 *
688 * This routine will issue the INIT_LINK mailbox command call.
689 * It is available to other drivers through the lpfc_hba data
690 * structure for use as a delayed link up mechanism with the
691 * module parameter lpfc_suppress_link_up.
692 *
693 * Return code
694 * 0 - success
695 * Any other value - error
696 **/
697int
698lpfc_hba_init_link_fc_topology(struct lpfc_hba *phba, uint32_t fc_topology,
699 uint32_t flag)
84d1b006
JS
700{
701 struct lpfc_vport *vport = phba->pport;
702 LPFC_MBOXQ_t *pmb;
703 MAILBOX_t *mb;
704 int rc;
705
706 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
707 if (!pmb) {
708 phba->link_state = LPFC_HBA_ERROR;
709 return -ENOMEM;
710 }
711 mb = &pmb->u.mb;
712 pmb->vport = vport;
713
026abb87
JS
714 if ((phba->cfg_link_speed > LPFC_USER_LINK_SPEED_MAX) ||
715 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_1G) &&
716 !(phba->lmt & LMT_1Gb)) ||
717 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_2G) &&
718 !(phba->lmt & LMT_2Gb)) ||
719 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_4G) &&
720 !(phba->lmt & LMT_4Gb)) ||
721 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_8G) &&
722 !(phba->lmt & LMT_8Gb)) ||
723 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_10G) &&
724 !(phba->lmt & LMT_10Gb)) ||
725 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_16G) &&
d38dd52c
JS
726 !(phba->lmt & LMT_16Gb)) ||
727 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_32G) &&
fbd8a6ba
JS
728 !(phba->lmt & LMT_32Gb)) ||
729 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_64G) &&
730 !(phba->lmt & LMT_64Gb))) {
026abb87 731 /* Reset link speed to auto */
372c187b
DK
732 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
733 "1302 Invalid speed for this board:%d "
734 "Reset link speed to auto.\n",
735 phba->cfg_link_speed);
026abb87
JS
736 phba->cfg_link_speed = LPFC_USER_LINK_SPEED_AUTO;
737 }
1b51197d 738 lpfc_init_link(phba, pmb, fc_topology, phba->cfg_link_speed);
84d1b006 739 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
1b51197d
JS
740 if (phba->sli_rev < LPFC_SLI_REV4)
741 lpfc_set_loopback_flag(phba);
6e7288d9 742 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
76a95d75 743 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
372c187b
DK
744 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
745 "0498 Adapter failed to init, mbxCmd x%x "
746 "INIT_LINK, mbxStatus x%x\n",
747 mb->mbxCommand, mb->mbxStatus);
76a95d75
JS
748 if (phba->sli_rev <= LPFC_SLI_REV3) {
749 /* Clear all interrupt enable conditions */
750 writel(0, phba->HCregaddr);
751 readl(phba->HCregaddr); /* flush */
752 /* Clear all pending interrupts */
753 writel(0xffffffff, phba->HAregaddr);
754 readl(phba->HAregaddr); /* flush */
755 }
84d1b006 756 phba->link_state = LPFC_HBA_ERROR;
6e7288d9 757 if (rc != MBX_BUSY || flag == MBX_POLL)
84d1b006
JS
758 mempool_free(pmb, phba->mbox_mem_pool);
759 return -EIO;
760 }
e40a02c1 761 phba->cfg_suppress_link_up = LPFC_INITIALIZE_LINK;
6e7288d9
JS
762 if (flag == MBX_POLL)
763 mempool_free(pmb, phba->mbox_mem_pool);
84d1b006
JS
764
765 return 0;
766}
767
768/**
769 * lpfc_hba_down_link - this routine downs the FC link
6e7288d9
JS
770 * @phba: pointer to lpfc hba data structure.
771 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
84d1b006
JS
772 *
773 * This routine will issue the DOWN_LINK mailbox command call.
774 * It is available to other drivers through the lpfc_hba data
775 * structure for use to stop the link.
776 *
777 * Return code
778 * 0 - success
779 * Any other value - error
780 **/
e399b228 781static int
6e7288d9 782lpfc_hba_down_link(struct lpfc_hba *phba, uint32_t flag)
84d1b006
JS
783{
784 LPFC_MBOXQ_t *pmb;
785 int rc;
786
787 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
788 if (!pmb) {
789 phba->link_state = LPFC_HBA_ERROR;
790 return -ENOMEM;
791 }
792
372c187b
DK
793 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
794 "0491 Adapter Link is disabled.\n");
84d1b006
JS
795 lpfc_down_link(phba, pmb);
796 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
6e7288d9 797 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
84d1b006 798 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
372c187b
DK
799 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
800 "2522 Adapter failed to issue DOWN_LINK"
801 " mbox command rc 0x%x\n", rc);
84d1b006
JS
802
803 mempool_free(pmb, phba->mbox_mem_pool);
804 return -EIO;
805 }
6e7288d9
JS
806 if (flag == MBX_POLL)
807 mempool_free(pmb, phba->mbox_mem_pool);
808
84d1b006
JS
809 return 0;
810}
811
e59058c4 812/**
3621a710 813 * lpfc_hba_down_prep - Perform lpfc uninitialization prior to HBA reset
e59058c4
JS
814 * @phba: pointer to lpfc HBA data structure.
815 *
816 * This routine will do LPFC uninitialization before the HBA is reset when
817 * bringing down the SLI Layer.
818 *
819 * Return codes
820 * 0 - success.
821 * Any other value - error.
822 **/
dea3101e 823int
2e0fef85 824lpfc_hba_down_prep(struct lpfc_hba *phba)
dea3101e 825{
1b32f6aa
JS
826 struct lpfc_vport **vports;
827 int i;
3772a991
JS
828
829 if (phba->sli_rev <= LPFC_SLI_REV3) {
830 /* Disable interrupts */
831 writel(0, phba->HCregaddr);
832 readl(phba->HCregaddr); /* flush */
833 }
dea3101e 834
1b32f6aa
JS
835 if (phba->pport->load_flag & FC_UNLOADING)
836 lpfc_cleanup_discovery_resources(phba->pport);
837 else {
838 vports = lpfc_create_vport_work_array(phba);
839 if (vports != NULL)
3772a991
JS
840 for (i = 0; i <= phba->max_vports &&
841 vports[i] != NULL; i++)
1b32f6aa
JS
842 lpfc_cleanup_discovery_resources(vports[i]);
843 lpfc_destroy_vport_work_array(phba, vports);
7f5f3d0d
JS
844 }
845 return 0;
dea3101e 846}
847
68e814f5
JS
848/**
849 * lpfc_sli4_free_sp_events - Cleanup sp_queue_events to free
850 * rspiocb which got deferred
851 *
852 * @phba: pointer to lpfc HBA data structure.
853 *
854 * This routine will cleanup completed slow path events after HBA is reset
855 * when bringing down the SLI Layer.
856 *
857 *
858 * Return codes
859 * void.
860 **/
861static void
862lpfc_sli4_free_sp_events(struct lpfc_hba *phba)
863{
864 struct lpfc_iocbq *rspiocbq;
865 struct hbq_dmabuf *dmabuf;
866 struct lpfc_cq_event *cq_event;
867
868 spin_lock_irq(&phba->hbalock);
869 phba->hba_flag &= ~HBA_SP_QUEUE_EVT;
870 spin_unlock_irq(&phba->hbalock);
871
872 while (!list_empty(&phba->sli4_hba.sp_queue_event)) {
873 /* Get the response iocb from the head of work queue */
874 spin_lock_irq(&phba->hbalock);
875 list_remove_head(&phba->sli4_hba.sp_queue_event,
876 cq_event, struct lpfc_cq_event, list);
877 spin_unlock_irq(&phba->hbalock);
878
879 switch (bf_get(lpfc_wcqe_c_code, &cq_event->cqe.wcqe_cmpl)) {
880 case CQE_CODE_COMPL_WQE:
881 rspiocbq = container_of(cq_event, struct lpfc_iocbq,
882 cq_event);
883 lpfc_sli_release_iocbq(phba, rspiocbq);
884 break;
885 case CQE_CODE_RECEIVE:
886 case CQE_CODE_RECEIVE_V1:
887 dmabuf = container_of(cq_event, struct hbq_dmabuf,
888 cq_event);
889 lpfc_in_buf_free(phba, &dmabuf->dbuf);
890 }
891 }
892}
893
e59058c4 894/**
bcece5f5 895 * lpfc_hba_free_post_buf - Perform lpfc uninitialization after HBA reset
e59058c4
JS
896 * @phba: pointer to lpfc HBA data structure.
897 *
bcece5f5
JS
898 * This routine will cleanup posted ELS buffers after the HBA is reset
899 * when bringing down the SLI Layer.
900 *
e59058c4
JS
901 *
902 * Return codes
bcece5f5 903 * void.
e59058c4 904 **/
bcece5f5
JS
905static void
906lpfc_hba_free_post_buf(struct lpfc_hba *phba)
41415862
JW
907{
908 struct lpfc_sli *psli = &phba->sli;
909 struct lpfc_sli_ring *pring;
910 struct lpfc_dmabuf *mp, *next_mp;
07eab624
JS
911 LIST_HEAD(buflist);
912 int count;
41415862 913
92d7f7b0
JS
914 if (phba->sli3_options & LPFC_SLI3_HBQ_ENABLED)
915 lpfc_sli_hbqbuf_free_all(phba);
916 else {
917 /* Cleanup preposted buffers on the ELS ring */
895427bd 918 pring = &psli->sli3_ring[LPFC_ELS_RING];
07eab624
JS
919 spin_lock_irq(&phba->hbalock);
920 list_splice_init(&pring->postbufq, &buflist);
921 spin_unlock_irq(&phba->hbalock);
922
923 count = 0;
924 list_for_each_entry_safe(mp, next_mp, &buflist, list) {
92d7f7b0 925 list_del(&mp->list);
07eab624 926 count++;
92d7f7b0
JS
927 lpfc_mbuf_free(phba, mp->virt, mp->phys);
928 kfree(mp);
929 }
07eab624
JS
930
931 spin_lock_irq(&phba->hbalock);
932 pring->postbufq_cnt -= count;
bcece5f5 933 spin_unlock_irq(&phba->hbalock);
41415862 934 }
bcece5f5
JS
935}
936
937/**
938 * lpfc_hba_clean_txcmplq - Perform lpfc uninitialization after HBA reset
939 * @phba: pointer to lpfc HBA data structure.
940 *
941 * This routine will cleanup the txcmplq after the HBA is reset when bringing
942 * down the SLI Layer.
943 *
944 * Return codes
945 * void
946 **/
947static void
948lpfc_hba_clean_txcmplq(struct lpfc_hba *phba)
949{
950 struct lpfc_sli *psli = &phba->sli;
895427bd 951 struct lpfc_queue *qp = NULL;
bcece5f5
JS
952 struct lpfc_sli_ring *pring;
953 LIST_HEAD(completions);
954 int i;
c1dd9111 955 struct lpfc_iocbq *piocb, *next_iocb;
bcece5f5 956
895427bd
JS
957 if (phba->sli_rev != LPFC_SLI_REV4) {
958 for (i = 0; i < psli->num_rings; i++) {
959 pring = &psli->sli3_ring[i];
bcece5f5 960 spin_lock_irq(&phba->hbalock);
895427bd
JS
961 /* At this point in time the HBA is either reset or DOA
962 * Nothing should be on txcmplq as it will
963 * NEVER complete.
964 */
965 list_splice_init(&pring->txcmplq, &completions);
966 pring->txcmplq_cnt = 0;
bcece5f5 967 spin_unlock_irq(&phba->hbalock);
09372820 968
895427bd
JS
969 lpfc_sli_abort_iocb_ring(phba, pring);
970 }
a257bf90 971 /* Cancel all the IOCBs from the completions list */
895427bd
JS
972 lpfc_sli_cancel_iocbs(phba, &completions,
973 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
974 return;
975 }
976 list_for_each_entry(qp, &phba->sli4_hba.lpfc_wq_list, wq_list) {
977 pring = qp->pring;
978 if (!pring)
979 continue;
980 spin_lock_irq(&pring->ring_lock);
c1dd9111
JS
981 list_for_each_entry_safe(piocb, next_iocb,
982 &pring->txcmplq, list)
983 piocb->iocb_flag &= ~LPFC_IO_ON_TXCMPLQ;
895427bd
JS
984 list_splice_init(&pring->txcmplq, &completions);
985 pring->txcmplq_cnt = 0;
986 spin_unlock_irq(&pring->ring_lock);
41415862
JW
987 lpfc_sli_abort_iocb_ring(phba, pring);
988 }
895427bd
JS
989 /* Cancel all the IOCBs from the completions list */
990 lpfc_sli_cancel_iocbs(phba, &completions,
991 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
bcece5f5 992}
41415862 993
bcece5f5
JS
994/**
995 * lpfc_hba_down_post_s3 - Perform lpfc uninitialization after HBA reset
bcece5f5
JS
996 * @phba: pointer to lpfc HBA data structure.
997 *
998 * This routine will do uninitialization after the HBA is reset when bring
999 * down the SLI Layer.
1000 *
1001 * Return codes
1002 * 0 - success.
1003 * Any other value - error.
1004 **/
1005static int
1006lpfc_hba_down_post_s3(struct lpfc_hba *phba)
1007{
1008 lpfc_hba_free_post_buf(phba);
1009 lpfc_hba_clean_txcmplq(phba);
41415862
JW
1010 return 0;
1011}
5af5eee7 1012
da0436e9
JS
1013/**
1014 * lpfc_hba_down_post_s4 - Perform lpfc uninitialization after HBA reset
1015 * @phba: pointer to lpfc HBA data structure.
1016 *
1017 * This routine will do uninitialization after the HBA is reset when bring
1018 * down the SLI Layer.
1019 *
1020 * Return codes
af901ca1 1021 * 0 - success.
da0436e9
JS
1022 * Any other value - error.
1023 **/
1024static int
1025lpfc_hba_down_post_s4(struct lpfc_hba *phba)
1026{
c490850a 1027 struct lpfc_io_buf *psb, *psb_next;
7cacae2a 1028 struct lpfc_async_xchg_ctx *ctxp, *ctxp_next;
5e5b511d 1029 struct lpfc_sli4_hdw_queue *qp;
da0436e9 1030 LIST_HEAD(aborts);
895427bd 1031 LIST_HEAD(nvme_aborts);
86c67379 1032 LIST_HEAD(nvmet_aborts);
0f65ff68 1033 struct lpfc_sglq *sglq_entry = NULL;
5e5b511d 1034 int cnt, idx;
0f65ff68 1035
895427bd
JS
1036
1037 lpfc_sli_hbqbuf_free_all(phba);
bcece5f5
JS
1038 lpfc_hba_clean_txcmplq(phba);
1039
da0436e9
JS
1040 /* At this point in time the HBA is either reset or DOA. Either
1041 * way, nothing should be on lpfc_abts_els_sgl_list, it needs to be
895427bd 1042 * on the lpfc_els_sgl_list so that it can either be freed if the
da0436e9
JS
1043 * driver is unloading or reposted if the driver is restarting
1044 * the port.
1045 */
895427bd 1046 spin_lock_irq(&phba->hbalock); /* required for lpfc_els_sgl_list and */
da0436e9 1047 /* scsl_buf_list */
895427bd 1048 /* sgl_list_lock required because worker thread uses this
da0436e9
JS
1049 * list.
1050 */
895427bd 1051 spin_lock(&phba->sli4_hba.sgl_list_lock);
0f65ff68
JS
1052 list_for_each_entry(sglq_entry,
1053 &phba->sli4_hba.lpfc_abts_els_sgl_list, list)
1054 sglq_entry->state = SGL_FREED;
1055
da0436e9 1056 list_splice_init(&phba->sli4_hba.lpfc_abts_els_sgl_list,
895427bd
JS
1057 &phba->sli4_hba.lpfc_els_sgl_list);
1058
f358dd0c 1059
895427bd 1060 spin_unlock(&phba->sli4_hba.sgl_list_lock);
5e5b511d
JS
1061
1062 /* abts_xxxx_buf_list_lock required because worker thread uses this
da0436e9
JS
1063 * list.
1064 */
5e5b511d
JS
1065 cnt = 0;
1066 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
1067 qp = &phba->sli4_hba.hdwq[idx];
da0436e9 1068
c00f62e6
JS
1069 spin_lock(&qp->abts_io_buf_list_lock);
1070 list_splice_init(&qp->lpfc_abts_io_buf_list,
5e5b511d 1071 &aborts);
68e814f5 1072
0794d601 1073 list_for_each_entry_safe(psb, psb_next, &aborts, list) {
86c67379
JS
1074 psb->pCmd = NULL;
1075 psb->status = IOSTAT_SUCCESS;
cf1a1d3e 1076 cnt++;
86c67379 1077 }
5e5b511d
JS
1078 spin_lock(&qp->io_buf_list_put_lock);
1079 list_splice_init(&aborts, &qp->lpfc_io_buf_list_put);
1080 qp->put_io_bufs += qp->abts_scsi_io_bufs;
c00f62e6 1081 qp->put_io_bufs += qp->abts_nvme_io_bufs;
5e5b511d 1082 qp->abts_scsi_io_bufs = 0;
c00f62e6 1083 qp->abts_nvme_io_bufs = 0;
5e5b511d 1084 spin_unlock(&qp->io_buf_list_put_lock);
c00f62e6 1085 spin_unlock(&qp->abts_io_buf_list_lock);
5e5b511d 1086 }
731eedcb 1087 spin_unlock_irq(&phba->hbalock);
86c67379 1088
5e5b511d 1089 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
731eedcb 1090 spin_lock_irq(&phba->sli4_hba.abts_nvmet_buf_list_lock);
5e5b511d
JS
1091 list_splice_init(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list,
1092 &nvmet_aborts);
731eedcb 1093 spin_unlock_irq(&phba->sli4_hba.abts_nvmet_buf_list_lock);
86c67379 1094 list_for_each_entry_safe(ctxp, ctxp_next, &nvmet_aborts, list) {
7b7f551b 1095 ctxp->flag &= ~(LPFC_NVME_XBUSY | LPFC_NVME_ABORT_OP);
6c621a22 1096 lpfc_nvmet_ctxbuf_post(phba, ctxp->ctxbuf);
86c67379 1097 }
895427bd 1098 }
895427bd 1099
68e814f5 1100 lpfc_sli4_free_sp_events(phba);
5e5b511d 1101 return cnt;
da0436e9
JS
1102}
1103
1104/**
1105 * lpfc_hba_down_post - Wrapper func for hba down post routine
1106 * @phba: pointer to lpfc HBA data structure.
1107 *
1108 * This routine wraps the actual SLI3 or SLI4 routine for performing
1109 * uninitialization after the HBA is reset when bring down the SLI Layer.
1110 *
1111 * Return codes
af901ca1 1112 * 0 - success.
da0436e9
JS
1113 * Any other value - error.
1114 **/
1115int
1116lpfc_hba_down_post(struct lpfc_hba *phba)
1117{
1118 return (*phba->lpfc_hba_down_post)(phba);
1119}
41415862 1120
e59058c4 1121/**
3621a710 1122 * lpfc_hb_timeout - The HBA-timer timeout handler
fe614acd 1123 * @t: timer context used to obtain the pointer to lpfc hba data structure.
e59058c4
JS
1124 *
1125 * This is the HBA-timer timeout handler registered to the lpfc driver. When
1126 * this timer fires, a HBA timeout event shall be posted to the lpfc driver
1127 * work-port-events bitmap and the worker thread is notified. This timeout
1128 * event will be used by the worker thread to invoke the actual timeout
1129 * handler routine, lpfc_hb_timeout_handler. Any periodical operations will
1130 * be performed in the timeout handler and the HBA timeout event bit shall
1131 * be cleared by the worker thread after it has taken the event bitmap out.
1132 **/
a6ababd2 1133static void
f22eb4d3 1134lpfc_hb_timeout(struct timer_list *t)
858c9f6c
JS
1135{
1136 struct lpfc_hba *phba;
5e9d9b82 1137 uint32_t tmo_posted;
858c9f6c
JS
1138 unsigned long iflag;
1139
f22eb4d3 1140 phba = from_timer(phba, t, hb_tmofunc);
9399627f
JS
1141
1142 /* Check for heart beat timeout conditions */
858c9f6c 1143 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
5e9d9b82
JS
1144 tmo_posted = phba->pport->work_port_events & WORKER_HB_TMO;
1145 if (!tmo_posted)
858c9f6c
JS
1146 phba->pport->work_port_events |= WORKER_HB_TMO;
1147 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
1148
9399627f 1149 /* Tell the worker thread there is work to do */
5e9d9b82
JS
1150 if (!tmo_posted)
1151 lpfc_worker_wake_up(phba);
858c9f6c
JS
1152 return;
1153}
1154
19ca7609
JS
1155/**
1156 * lpfc_rrq_timeout - The RRQ-timer timeout handler
fe614acd 1157 * @t: timer context used to obtain the pointer to lpfc hba data structure.
19ca7609
JS
1158 *
1159 * This is the RRQ-timer timeout handler registered to the lpfc driver. When
1160 * this timer fires, a RRQ timeout event shall be posted to the lpfc driver
1161 * work-port-events bitmap and the worker thread is notified. This timeout
1162 * event will be used by the worker thread to invoke the actual timeout
1163 * handler routine, lpfc_rrq_handler. Any periodical operations will
1164 * be performed in the timeout handler and the RRQ timeout event bit shall
1165 * be cleared by the worker thread after it has taken the event bitmap out.
1166 **/
1167static void
f22eb4d3 1168lpfc_rrq_timeout(struct timer_list *t)
19ca7609
JS
1169{
1170 struct lpfc_hba *phba;
19ca7609
JS
1171 unsigned long iflag;
1172
f22eb4d3 1173 phba = from_timer(phba, t, rrq_tmr);
19ca7609 1174 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
06918ac5
JS
1175 if (!(phba->pport->load_flag & FC_UNLOADING))
1176 phba->hba_flag |= HBA_RRQ_ACTIVE;
1177 else
1178 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
19ca7609 1179 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
06918ac5
JS
1180
1181 if (!(phba->pport->load_flag & FC_UNLOADING))
1182 lpfc_worker_wake_up(phba);
19ca7609
JS
1183}
1184
e59058c4 1185/**
3621a710 1186 * lpfc_hb_mbox_cmpl - The lpfc heart-beat mailbox command callback function
e59058c4
JS
1187 * @phba: pointer to lpfc hba data structure.
1188 * @pmboxq: pointer to the driver internal queue element for mailbox command.
1189 *
1190 * This is the callback function to the lpfc heart-beat mailbox command.
1191 * If configured, the lpfc driver issues the heart-beat mailbox command to
1192 * the HBA every LPFC_HB_MBOX_INTERVAL (current 5) seconds. At the time the
1193 * heart-beat mailbox command is issued, the driver shall set up heart-beat
1194 * timeout timer to LPFC_HB_MBOX_TIMEOUT (current 30) seconds and marks
1195 * heart-beat outstanding state. Once the mailbox command comes back and
1196 * no error conditions detected, the heart-beat mailbox command timer is
1197 * reset to LPFC_HB_MBOX_INTERVAL seconds and the heart-beat outstanding
1198 * state is cleared for the next heart-beat. If the timer expired with the
1199 * heart-beat outstanding state set, the driver will put the HBA offline.
1200 **/
858c9f6c
JS
1201static void
1202lpfc_hb_mbox_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
1203{
1204 unsigned long drvr_flag;
1205
1206 spin_lock_irqsave(&phba->hbalock, drvr_flag);
a22d73b6 1207 phba->hba_flag &= ~(HBA_HBEAT_INP | HBA_HBEAT_TMO);
858c9f6c
JS
1208 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
1209
a22d73b6 1210 /* Check and reset heart-beat timer if necessary */
858c9f6c
JS
1211 mempool_free(pmboxq, phba->mbox_mem_pool);
1212 if (!(phba->pport->fc_flag & FC_OFFLINE_MODE) &&
1213 !(phba->link_state == LPFC_HBA_ERROR) &&
51ef4c26 1214 !(phba->pport->load_flag & FC_UNLOADING))
858c9f6c 1215 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1216 jiffies +
1217 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
1218 return;
1219}
1220
fe614acd 1221/*
317aeb83
DK
1222 * lpfc_idle_stat_delay_work - idle_stat tracking
1223 *
1224 * This routine tracks per-cq idle_stat and determines polling decisions.
1225 *
1226 * Return codes:
1227 * None
1228 **/
1229static void
1230lpfc_idle_stat_delay_work(struct work_struct *work)
1231{
1232 struct lpfc_hba *phba = container_of(to_delayed_work(work),
1233 struct lpfc_hba,
1234 idle_stat_delay_work);
1235 struct lpfc_queue *cq;
1236 struct lpfc_sli4_hdw_queue *hdwq;
1237 struct lpfc_idle_stat *idle_stat;
1238 u32 i, idle_percent;
1239 u64 wall, wall_idle, diff_wall, diff_idle, busy_time;
1240
1241 if (phba->pport->load_flag & FC_UNLOADING)
1242 return;
1243
1244 if (phba->link_state == LPFC_HBA_ERROR ||
1245 phba->pport->fc_flag & FC_OFFLINE_MODE)
1246 goto requeue;
1247
1248 for_each_present_cpu(i) {
1249 hdwq = &phba->sli4_hba.hdwq[phba->sli4_hba.cpu_map[i].hdwq];
1250 cq = hdwq->io_cq;
1251
1252 /* Skip if we've already handled this cq's primary CPU */
1253 if (cq->chann != i)
1254 continue;
1255
1256 idle_stat = &phba->sli4_hba.idle_stat[i];
1257
1258 /* get_cpu_idle_time returns values as running counters. Thus,
1259 * to know the amount for this period, the prior counter values
1260 * need to be subtracted from the current counter values.
1261 * From there, the idle time stat can be calculated as a
1262 * percentage of 100 - the sum of the other consumption times.
1263 */
1264 wall_idle = get_cpu_idle_time(i, &wall, 1);
1265 diff_idle = wall_idle - idle_stat->prev_idle;
1266 diff_wall = wall - idle_stat->prev_wall;
1267
1268 if (diff_wall <= diff_idle)
1269 busy_time = 0;
1270 else
1271 busy_time = diff_wall - diff_idle;
1272
1273 idle_percent = div64_u64(100 * busy_time, diff_wall);
1274 idle_percent = 100 - idle_percent;
1275
1276 if (idle_percent < 15)
1277 cq->poll_mode = LPFC_QUEUE_WORK;
1278 else
1279 cq->poll_mode = LPFC_IRQ_POLL;
1280
1281 idle_stat->prev_idle = wall_idle;
1282 idle_stat->prev_wall = wall;
1283 }
1284
1285requeue:
1286 schedule_delayed_work(&phba->idle_stat_delay_work,
1287 msecs_to_jiffies(LPFC_IDLE_STAT_DELAY));
1288}
1289
32517fc0
JS
1290static void
1291lpfc_hb_eq_delay_work(struct work_struct *work)
1292{
1293 struct lpfc_hba *phba = container_of(to_delayed_work(work),
1294 struct lpfc_hba, eq_delay_work);
1295 struct lpfc_eq_intr_info *eqi, *eqi_new;
1296 struct lpfc_queue *eq, *eq_next;
8156d378 1297 unsigned char *ena_delay = NULL;
32517fc0
JS
1298 uint32_t usdelay;
1299 int i;
1300
1301 if (!phba->cfg_auto_imax || phba->pport->load_flag & FC_UNLOADING)
1302 return;
1303
1304 if (phba->link_state == LPFC_HBA_ERROR ||
1305 phba->pport->fc_flag & FC_OFFLINE_MODE)
1306 goto requeue;
1307
8156d378
JS
1308 ena_delay = kcalloc(phba->sli4_hba.num_possible_cpu, sizeof(*ena_delay),
1309 GFP_KERNEL);
1310 if (!ena_delay)
32517fc0
JS
1311 goto requeue;
1312
8156d378
JS
1313 for (i = 0; i < phba->cfg_irq_chann; i++) {
1314 /* Get the EQ corresponding to the IRQ vector */
1315 eq = phba->sli4_hba.hba_eq_hdl[i].eq;
1316 if (!eq)
1317 continue;
1318 if (eq->q_mode || eq->q_flag & HBA_EQ_DELAY_CHK) {
1319 eq->q_flag &= ~HBA_EQ_DELAY_CHK;
1320 ena_delay[eq->last_cpu] = 1;
8d34a59c 1321 }
8156d378 1322 }
32517fc0
JS
1323
1324 for_each_present_cpu(i) {
32517fc0 1325 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, i);
8156d378
JS
1326 if (ena_delay[i]) {
1327 usdelay = (eqi->icnt >> 10) * LPFC_EQ_DELAY_STEP;
1328 if (usdelay > LPFC_MAX_AUTO_EQ_DELAY)
1329 usdelay = LPFC_MAX_AUTO_EQ_DELAY;
1330 } else {
1331 usdelay = 0;
8d34a59c 1332 }
32517fc0 1333
32517fc0
JS
1334 eqi->icnt = 0;
1335
1336 list_for_each_entry_safe(eq, eq_next, &eqi->list, cpu_list) {
8156d378 1337 if (unlikely(eq->last_cpu != i)) {
32517fc0
JS
1338 eqi_new = per_cpu_ptr(phba->sli4_hba.eq_info,
1339 eq->last_cpu);
1340 list_move_tail(&eq->cpu_list, &eqi_new->list);
1341 continue;
1342 }
1343 if (usdelay != eq->q_mode)
1344 lpfc_modify_hba_eq_delay(phba, eq->hdwq, 1,
1345 usdelay);
1346 }
1347 }
1348
8156d378 1349 kfree(ena_delay);
32517fc0
JS
1350
1351requeue:
1352 queue_delayed_work(phba->wq, &phba->eq_delay_work,
1353 msecs_to_jiffies(LPFC_EQ_DELAY_MSECS));
1354}
1355
c490850a
JS
1356/**
1357 * lpfc_hb_mxp_handler - Multi-XRI pools handler to adjust XRI distribution
1358 * @phba: pointer to lpfc hba data structure.
1359 *
1360 * For each heartbeat, this routine does some heuristic methods to adjust
1361 * XRI distribution. The goal is to fully utilize free XRIs.
1362 **/
1363static void lpfc_hb_mxp_handler(struct lpfc_hba *phba)
1364{
1365 u32 i;
1366 u32 hwq_count;
1367
1368 hwq_count = phba->cfg_hdw_queue;
1369 for (i = 0; i < hwq_count; i++) {
1370 /* Adjust XRIs in private pool */
1371 lpfc_adjust_pvt_pool_count(phba, i);
1372
1373 /* Adjust high watermark */
1374 lpfc_adjust_high_watermark(phba, i);
1375
1376#ifdef LPFC_MXP_STAT
1377 /* Snapshot pbl, pvt and busy count */
1378 lpfc_snapshot_mxp(phba, i);
1379#endif
1380 }
1381}
1382
a22d73b6
JS
1383/**
1384 * lpfc_issue_hb_mbox - Issues heart-beat mailbox command
1385 * @phba: pointer to lpfc hba data structure.
1386 *
1387 * If a HB mbox is not already in progrees, this routine will allocate
1388 * a LPFC_MBOXQ_t, populate it with a MBX_HEARTBEAT (0x31) command,
1389 * and issue it. The HBA_HBEAT_INP flag means the command is in progress.
1390 **/
1391int
1392lpfc_issue_hb_mbox(struct lpfc_hba *phba)
1393{
1394 LPFC_MBOXQ_t *pmboxq;
1395 int retval;
1396
1397 /* Is a Heartbeat mbox already in progress */
1398 if (phba->hba_flag & HBA_HBEAT_INP)
1399 return 0;
1400
1401 pmboxq = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
1402 if (!pmboxq)
1403 return -ENOMEM;
1404
1405 lpfc_heart_beat(phba, pmboxq);
1406 pmboxq->mbox_cmpl = lpfc_hb_mbox_cmpl;
1407 pmboxq->vport = phba->pport;
1408 retval = lpfc_sli_issue_mbox(phba, pmboxq, MBX_NOWAIT);
1409
1410 if (retval != MBX_BUSY && retval != MBX_SUCCESS) {
1411 mempool_free(pmboxq, phba->mbox_mem_pool);
1412 return -ENXIO;
1413 }
1414 phba->hba_flag |= HBA_HBEAT_INP;
1415
1416 return 0;
1417}
1418
1419/**
1420 * lpfc_issue_hb_tmo - Signals heartbeat timer to issue mbox command
1421 * @phba: pointer to lpfc hba data structure.
1422 *
1423 * The heartbeat timer (every 5 sec) will fire. If the HBA_HBEAT_TMO
1424 * flag is set, it will force a MBX_HEARTBEAT mbox command, regardless
1425 * of the value of lpfc_enable_hba_heartbeat.
1426 * If lpfc_enable_hba_heartbeat is set, the timeout routine will always
1427 * try to issue a MBX_HEARTBEAT mbox command.
1428 **/
1429void
1430lpfc_issue_hb_tmo(struct lpfc_hba *phba)
1431{
1432 if (phba->cfg_enable_hba_heartbeat)
1433 return;
1434 phba->hba_flag |= HBA_HBEAT_TMO;
1435}
1436
e59058c4 1437/**
3621a710 1438 * lpfc_hb_timeout_handler - The HBA-timer timeout handler
e59058c4
JS
1439 * @phba: pointer to lpfc hba data structure.
1440 *
1441 * This is the actual HBA-timer timeout handler to be invoked by the worker
1442 * thread whenever the HBA timer fired and HBA-timeout event posted. This
1443 * handler performs any periodic operations needed for the device. If such
1444 * periodic event has already been attended to either in the interrupt handler
1445 * or by processing slow-ring or fast-ring events within the HBA-timer
1446 * timeout window (LPFC_HB_MBOX_INTERVAL), this handler just simply resets
1447 * the timer for the next timeout period. If lpfc heart-beat mailbox command
1448 * is configured and there is no heart-beat mailbox command outstanding, a
1449 * heart-beat mailbox is issued and timer set properly. Otherwise, if there
1450 * has been a heart-beat mailbox command outstanding, the HBA shall be put
1451 * to offline.
1452 **/
858c9f6c
JS
1453void
1454lpfc_hb_timeout_handler(struct lpfc_hba *phba)
1455{
45ed1190 1456 struct lpfc_vport **vports;
0ff10d46 1457 struct lpfc_dmabuf *buf_ptr;
a22d73b6
JS
1458 int retval = 0;
1459 int i, tmo;
858c9f6c 1460 struct lpfc_sli *psli = &phba->sli;
0ff10d46 1461 LIST_HEAD(completions);
858c9f6c 1462
c490850a
JS
1463 if (phba->cfg_xri_rebalancing) {
1464 /* Multi-XRI pools handler */
1465 lpfc_hb_mxp_handler(phba);
1466 }
858c9f6c 1467
45ed1190
JS
1468 vports = lpfc_create_vport_work_array(phba);
1469 if (vports != NULL)
4258e98e 1470 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
45ed1190 1471 lpfc_rcv_seq_check_edtov(vports[i]);
e3ba04c9 1472 lpfc_fdmi_change_check(vports[i]);
4258e98e 1473 }
45ed1190
JS
1474 lpfc_destroy_vport_work_array(phba, vports);
1475
858c9f6c 1476 if ((phba->link_state == LPFC_HBA_ERROR) ||
51ef4c26 1477 (phba->pport->load_flag & FC_UNLOADING) ||
858c9f6c
JS
1478 (phba->pport->fc_flag & FC_OFFLINE_MODE))
1479 return;
1480
0ff10d46
JS
1481 if (phba->elsbuf_cnt &&
1482 (phba->elsbuf_cnt == phba->elsbuf_prev_cnt)) {
1483 spin_lock_irq(&phba->hbalock);
1484 list_splice_init(&phba->elsbuf, &completions);
1485 phba->elsbuf_cnt = 0;
1486 phba->elsbuf_prev_cnt = 0;
1487 spin_unlock_irq(&phba->hbalock);
1488
1489 while (!list_empty(&completions)) {
1490 list_remove_head(&completions, buf_ptr,
1491 struct lpfc_dmabuf, list);
1492 lpfc_mbuf_free(phba, buf_ptr->virt, buf_ptr->phys);
1493 kfree(buf_ptr);
1494 }
1495 }
1496 phba->elsbuf_prev_cnt = phba->elsbuf_cnt;
1497
858c9f6c 1498 /* If there is no heart beat outstanding, issue a heartbeat command */
13815c83 1499 if (phba->cfg_enable_hba_heartbeat) {
a22d73b6
JS
1500 /* If IOs are completing, no need to issue a MBX_HEARTBEAT */
1501 spin_lock_irq(&phba->pport->work_port_lock);
1502 if (time_after(phba->last_completion_time +
1503 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL),
1504 jiffies)) {
1505 spin_unlock_irq(&phba->pport->work_port_lock);
1506 if (phba->hba_flag & HBA_HBEAT_INP)
1507 tmo = (1000 * LPFC_HB_MBOX_TIMEOUT);
1508 else
1509 tmo = (1000 * LPFC_HB_MBOX_INTERVAL);
1510 goto out;
1511 }
1512 spin_unlock_irq(&phba->pport->work_port_lock);
1513
1514 /* Check if a MBX_HEARTBEAT is already in progress */
1515 if (phba->hba_flag & HBA_HBEAT_INP) {
1516 /*
1517 * If heart beat timeout called with HBA_HBEAT_INP set
1518 * we need to give the hb mailbox cmd a chance to
1519 * complete or TMO.
1520 */
1521 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1522 "0459 Adapter heartbeat still outstanding: "
1523 "last compl time was %d ms.\n",
1524 jiffies_to_msecs(jiffies
1525 - phba->last_completion_time));
1526 tmo = (1000 * LPFC_HB_MBOX_TIMEOUT);
1527 } else {
bc73905a
JS
1528 if ((!(psli->sli_flag & LPFC_SLI_MBOX_ACTIVE)) &&
1529 (list_empty(&psli->mboxq))) {
bc73905a 1530
a22d73b6
JS
1531 retval = lpfc_issue_hb_mbox(phba);
1532 if (retval) {
1533 tmo = (1000 * LPFC_HB_MBOX_INTERVAL);
1534 goto out;
bc73905a
JS
1535 }
1536 phba->skipped_hb = 0;
bc73905a
JS
1537 } else if (time_before_eq(phba->last_completion_time,
1538 phba->skipped_hb)) {
1539 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
1540 "2857 Last completion time not "
1541 " updated in %d ms\n",
1542 jiffies_to_msecs(jiffies
1543 - phba->last_completion_time));
1544 } else
1545 phba->skipped_hb = jiffies;
1546
a22d73b6
JS
1547 tmo = (1000 * LPFC_HB_MBOX_TIMEOUT);
1548 goto out;
858c9f6c 1549 }
4258e98e 1550 } else {
a22d73b6
JS
1551 /* Check to see if we want to force a MBX_HEARTBEAT */
1552 if (phba->hba_flag & HBA_HBEAT_TMO) {
1553 retval = lpfc_issue_hb_mbox(phba);
1554 if (retval)
1555 tmo = (1000 * LPFC_HB_MBOX_INTERVAL);
1556 else
1557 tmo = (1000 * LPFC_HB_MBOX_TIMEOUT);
1558 goto out;
1559 }
1560 tmo = (1000 * LPFC_HB_MBOX_INTERVAL);
858c9f6c 1561 }
a22d73b6
JS
1562out:
1563 mod_timer(&phba->hb_tmofunc, jiffies + msecs_to_jiffies(tmo));
858c9f6c
JS
1564}
1565
e59058c4 1566/**
3621a710 1567 * lpfc_offline_eratt - Bring lpfc offline on hardware error attention
e59058c4
JS
1568 * @phba: pointer to lpfc hba data structure.
1569 *
1570 * This routine is called to bring the HBA offline when HBA hardware error
1571 * other than Port Error 6 has been detected.
1572 **/
09372820
JS
1573static void
1574lpfc_offline_eratt(struct lpfc_hba *phba)
1575{
1576 struct lpfc_sli *psli = &phba->sli;
1577
1578 spin_lock_irq(&phba->hbalock);
f4b4c68f 1579 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
09372820 1580 spin_unlock_irq(&phba->hbalock);
618a5230 1581 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
09372820
JS
1582
1583 lpfc_offline(phba);
1584 lpfc_reset_barrier(phba);
f4b4c68f 1585 spin_lock_irq(&phba->hbalock);
09372820 1586 lpfc_sli_brdreset(phba);
f4b4c68f 1587 spin_unlock_irq(&phba->hbalock);
09372820
JS
1588 lpfc_hba_down_post(phba);
1589 lpfc_sli_brdready(phba, HS_MBRDY);
1590 lpfc_unblock_mgmt_io(phba);
1591 phba->link_state = LPFC_HBA_ERROR;
1592 return;
1593}
1594
da0436e9
JS
1595/**
1596 * lpfc_sli4_offline_eratt - Bring lpfc offline on SLI4 hardware error attention
1597 * @phba: pointer to lpfc hba data structure.
1598 *
1599 * This routine is called to bring a SLI4 HBA offline when HBA hardware error
1600 * other than Port Error 6 has been detected.
1601 **/
a88dbb6a 1602void
da0436e9
JS
1603lpfc_sli4_offline_eratt(struct lpfc_hba *phba)
1604{
946727dc
JS
1605 spin_lock_irq(&phba->hbalock);
1606 phba->link_state = LPFC_HBA_ERROR;
1607 spin_unlock_irq(&phba->hbalock);
1608
618a5230 1609 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
c00f62e6 1610 lpfc_sli_flush_io_rings(phba);
da0436e9 1611 lpfc_offline(phba);
da0436e9 1612 lpfc_hba_down_post(phba);
da0436e9 1613 lpfc_unblock_mgmt_io(phba);
da0436e9
JS
1614}
1615
a257bf90
JS
1616/**
1617 * lpfc_handle_deferred_eratt - The HBA hardware deferred error handler
1618 * @phba: pointer to lpfc hba data structure.
1619 *
1620 * This routine is invoked to handle the deferred HBA hardware error
1621 * conditions. This type of error is indicated by HBA by setting ER1
1622 * and another ER bit in the host status register. The driver will
1623 * wait until the ER1 bit clears before handling the error condition.
1624 **/
1625static void
1626lpfc_handle_deferred_eratt(struct lpfc_hba *phba)
1627{
1628 uint32_t old_host_status = phba->work_hs;
a257bf90
JS
1629 struct lpfc_sli *psli = &phba->sli;
1630
f4b4c68f
JS
1631 /* If the pci channel is offline, ignore possible errors,
1632 * since we cannot communicate with the pci card anyway.
1633 */
1634 if (pci_channel_offline(phba->pcidev)) {
1635 spin_lock_irq(&phba->hbalock);
1636 phba->hba_flag &= ~DEFER_ERATT;
1637 spin_unlock_irq(&phba->hbalock);
1638 return;
1639 }
1640
372c187b
DK
1641 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1642 "0479 Deferred Adapter Hardware Error "
1643 "Data: x%x x%x x%x\n",
1644 phba->work_hs, phba->work_status[0],
1645 phba->work_status[1]);
a257bf90
JS
1646
1647 spin_lock_irq(&phba->hbalock);
f4b4c68f 1648 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
a257bf90
JS
1649 spin_unlock_irq(&phba->hbalock);
1650
1651
1652 /*
1653 * Firmware stops when it triggred erratt. That could cause the I/Os
1654 * dropped by the firmware. Error iocb (I/O) on txcmplq and let the
1655 * SCSI layer retry it after re-establishing link.
1656 */
db55fba8 1657 lpfc_sli_abort_fcp_rings(phba);
a257bf90
JS
1658
1659 /*
1660 * There was a firmware error. Take the hba offline and then
1661 * attempt to restart it.
1662 */
618a5230 1663 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
a257bf90
JS
1664 lpfc_offline(phba);
1665
1666 /* Wait for the ER1 bit to clear.*/
1667 while (phba->work_hs & HS_FFER1) {
1668 msleep(100);
9940b97b
JS
1669 if (lpfc_readl(phba->HSregaddr, &phba->work_hs)) {
1670 phba->work_hs = UNPLUG_ERR ;
1671 break;
1672 }
a257bf90
JS
1673 /* If driver is unloading let the worker thread continue */
1674 if (phba->pport->load_flag & FC_UNLOADING) {
1675 phba->work_hs = 0;
1676 break;
1677 }
1678 }
1679
1680 /*
1681 * This is to ptrotect against a race condition in which
1682 * first write to the host attention register clear the
1683 * host status register.
1684 */
1685 if ((!phba->work_hs) && (!(phba->pport->load_flag & FC_UNLOADING)))
1686 phba->work_hs = old_host_status & ~HS_FFER1;
1687
3772a991 1688 spin_lock_irq(&phba->hbalock);
a257bf90 1689 phba->hba_flag &= ~DEFER_ERATT;
3772a991 1690 spin_unlock_irq(&phba->hbalock);
a257bf90
JS
1691 phba->work_status[0] = readl(phba->MBslimaddr + 0xa8);
1692 phba->work_status[1] = readl(phba->MBslimaddr + 0xac);
1693}
1694
3772a991
JS
1695static void
1696lpfc_board_errevt_to_mgmt(struct lpfc_hba *phba)
1697{
1698 struct lpfc_board_event_header board_event;
1699 struct Scsi_Host *shost;
1700
1701 board_event.event_type = FC_REG_BOARD_EVENT;
1702 board_event.subcategory = LPFC_EVENT_PORTINTERR;
1703 shost = lpfc_shost_from_vport(phba->pport);
1704 fc_host_post_vendor_event(shost, fc_get_event_number(),
1705 sizeof(board_event),
1706 (char *) &board_event,
1707 LPFC_NL_VENDOR_ID);
1708}
1709
e59058c4 1710/**
3772a991 1711 * lpfc_handle_eratt_s3 - The SLI3 HBA hardware error handler
e59058c4
JS
1712 * @phba: pointer to lpfc hba data structure.
1713 *
1714 * This routine is invoked to handle the following HBA hardware error
1715 * conditions:
1716 * 1 - HBA error attention interrupt
1717 * 2 - DMA ring index out of range
1718 * 3 - Mailbox command came back as unknown
1719 **/
3772a991
JS
1720static void
1721lpfc_handle_eratt_s3(struct lpfc_hba *phba)
dea3101e 1722{
2e0fef85 1723 struct lpfc_vport *vport = phba->pport;
2e0fef85 1724 struct lpfc_sli *psli = &phba->sli;
d2873e4c 1725 uint32_t event_data;
57127f15
JS
1726 unsigned long temperature;
1727 struct temp_event temp_event_data;
92d7f7b0 1728 struct Scsi_Host *shost;
2e0fef85 1729
8d63f375 1730 /* If the pci channel is offline, ignore possible errors,
3772a991
JS
1731 * since we cannot communicate with the pci card anyway.
1732 */
1733 if (pci_channel_offline(phba->pcidev)) {
1734 spin_lock_irq(&phba->hbalock);
1735 phba->hba_flag &= ~DEFER_ERATT;
1736 spin_unlock_irq(&phba->hbalock);
8d63f375 1737 return;
3772a991
JS
1738 }
1739
13815c83
JS
1740 /* If resets are disabled then leave the HBA alone and return */
1741 if (!phba->cfg_enable_hba_reset)
1742 return;
dea3101e 1743
ea2151b4 1744 /* Send an internal error event to mgmt application */
3772a991 1745 lpfc_board_errevt_to_mgmt(phba);
ea2151b4 1746
a257bf90
JS
1747 if (phba->hba_flag & DEFER_ERATT)
1748 lpfc_handle_deferred_eratt(phba);
1749
dcf2a4e0
JS
1750 if ((phba->work_hs & HS_FFER6) || (phba->work_hs & HS_FFER8)) {
1751 if (phba->work_hs & HS_FFER6)
1752 /* Re-establishing Link */
1753 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1754 "1301 Re-establishing Link "
1755 "Data: x%x x%x x%x\n",
1756 phba->work_hs, phba->work_status[0],
1757 phba->work_status[1]);
1758 if (phba->work_hs & HS_FFER8)
1759 /* Device Zeroization */
1760 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1761 "2861 Host Authentication device "
1762 "zeroization Data:x%x x%x x%x\n",
1763 phba->work_hs, phba->work_status[0],
1764 phba->work_status[1]);
58da1ffb 1765
92d7f7b0 1766 spin_lock_irq(&phba->hbalock);
f4b4c68f 1767 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
92d7f7b0 1768 spin_unlock_irq(&phba->hbalock);
dea3101e 1769
1770 /*
1771 * Firmware stops when it triggled erratt with HS_FFER6.
1772 * That could cause the I/Os dropped by the firmware.
1773 * Error iocb (I/O) on txcmplq and let the SCSI layer
1774 * retry it after re-establishing link.
1775 */
db55fba8 1776 lpfc_sli_abort_fcp_rings(phba);
dea3101e 1777
dea3101e 1778 /*
1779 * There was a firmware error. Take the hba offline and then
1780 * attempt to restart it.
1781 */
618a5230 1782 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
dea3101e 1783 lpfc_offline(phba);
41415862 1784 lpfc_sli_brdrestart(phba);
dea3101e 1785 if (lpfc_online(phba) == 0) { /* Initialize the HBA */
46fa311e 1786 lpfc_unblock_mgmt_io(phba);
dea3101e 1787 return;
1788 }
46fa311e 1789 lpfc_unblock_mgmt_io(phba);
57127f15
JS
1790 } else if (phba->work_hs & HS_CRIT_TEMP) {
1791 temperature = readl(phba->MBslimaddr + TEMPERATURE_OFFSET);
1792 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1793 temp_event_data.event_code = LPFC_CRIT_TEMP;
1794 temp_event_data.data = (uint32_t)temperature;
1795
372c187b 1796 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
d7c255b2 1797 "0406 Adapter maximum temperature exceeded "
57127f15
JS
1798 "(%ld), taking this port offline "
1799 "Data: x%x x%x x%x\n",
1800 temperature, phba->work_hs,
1801 phba->work_status[0], phba->work_status[1]);
1802
1803 shost = lpfc_shost_from_vport(phba->pport);
1804 fc_host_post_vendor_event(shost, fc_get_event_number(),
1805 sizeof(temp_event_data),
1806 (char *) &temp_event_data,
1807 SCSI_NL_VID_TYPE_PCI
1808 | PCI_VENDOR_ID_EMULEX);
1809
7af67051 1810 spin_lock_irq(&phba->hbalock);
7af67051
JS
1811 phba->over_temp_state = HBA_OVER_TEMP;
1812 spin_unlock_irq(&phba->hbalock);
09372820 1813 lpfc_offline_eratt(phba);
57127f15 1814
dea3101e 1815 } else {
1816 /* The if clause above forces this code path when the status
9399627f
JS
1817 * failure is a value other than FFER6. Do not call the offline
1818 * twice. This is the adapter hardware error path.
dea3101e 1819 */
372c187b 1820 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 1821 "0457 Adapter Hardware Error "
dea3101e 1822 "Data: x%x x%x x%x\n",
e8b62011 1823 phba->work_hs,
dea3101e 1824 phba->work_status[0], phba->work_status[1]);
1825
d2873e4c 1826 event_data = FC_REG_DUMP_EVENT;
92d7f7b0 1827 shost = lpfc_shost_from_vport(vport);
2e0fef85 1828 fc_host_post_vendor_event(shost, fc_get_event_number(),
d2873e4c
JS
1829 sizeof(event_data), (char *) &event_data,
1830 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
1831
09372820 1832 lpfc_offline_eratt(phba);
dea3101e 1833 }
9399627f 1834 return;
dea3101e 1835}
1836
618a5230
JS
1837/**
1838 * lpfc_sli4_port_sta_fn_reset - The SLI4 function reset due to port status reg
1839 * @phba: pointer to lpfc hba data structure.
1840 * @mbx_action: flag for mailbox shutdown action.
fe614acd 1841 * @en_rn_msg: send reset/port recovery message.
618a5230
JS
1842 * This routine is invoked to perform an SLI4 port PCI function reset in
1843 * response to port status register polling attention. It waits for port
1844 * status register (ERR, RDY, RN) bits before proceeding with function reset.
1845 * During this process, interrupt vectors are freed and later requested
1846 * for handling possible port resource change.
1847 **/
1848static int
e10b2022
JS
1849lpfc_sli4_port_sta_fn_reset(struct lpfc_hba *phba, int mbx_action,
1850 bool en_rn_msg)
618a5230
JS
1851{
1852 int rc;
1853 uint32_t intr_mode;
1854
27d6ac0a 1855 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) >=
65791f1f
JS
1856 LPFC_SLI_INTF_IF_TYPE_2) {
1857 /*
1858 * On error status condition, driver need to wait for port
1859 * ready before performing reset.
1860 */
1861 rc = lpfc_sli4_pdev_status_reg_wait(phba);
0e916ee7 1862 if (rc)
65791f1f
JS
1863 return rc;
1864 }
0e916ee7 1865
65791f1f
JS
1866 /* need reset: attempt for port recovery */
1867 if (en_rn_msg)
372c187b 1868 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
1869 "2887 Reset Needed: Attempting Port "
1870 "Recovery...\n");
3ba6216a
JS
1871
1872 /* If we are no wait, the HBA has been reset and is not
1873 * functional, thus we should clear LPFC_SLI_ACTIVE flag.
1874 */
1875 if (mbx_action == LPFC_MBX_NO_WAIT) {
1876 spin_lock_irq(&phba->hbalock);
1877 phba->sli.sli_flag &= ~LPFC_SLI_ACTIVE;
1878 spin_unlock_irq(&phba->hbalock);
1879 }
1880
65791f1f 1881 lpfc_offline_prep(phba, mbx_action);
c00f62e6 1882 lpfc_sli_flush_io_rings(phba);
65791f1f
JS
1883 lpfc_offline(phba);
1884 /* release interrupt for possible resource change */
1885 lpfc_sli4_disable_intr(phba);
5a9eeff5
JS
1886 rc = lpfc_sli_brdrestart(phba);
1887 if (rc) {
372c187b 1888 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5a9eeff5
JS
1889 "6309 Failed to restart board\n");
1890 return rc;
1891 }
65791f1f
JS
1892 /* request and enable interrupt */
1893 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
1894 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 1895 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
1896 "3175 Failed to enable interrupt\n");
1897 return -EIO;
618a5230 1898 }
65791f1f
JS
1899 phba->intr_mode = intr_mode;
1900 rc = lpfc_online(phba);
1901 if (rc == 0)
1902 lpfc_unblock_mgmt_io(phba);
1903
618a5230
JS
1904 return rc;
1905}
1906
da0436e9
JS
1907/**
1908 * lpfc_handle_eratt_s4 - The SLI4 HBA hardware error handler
1909 * @phba: pointer to lpfc hba data structure.
1910 *
1911 * This routine is invoked to handle the SLI4 HBA hardware error attention
1912 * conditions.
1913 **/
1914static void
1915lpfc_handle_eratt_s4(struct lpfc_hba *phba)
1916{
1917 struct lpfc_vport *vport = phba->pport;
1918 uint32_t event_data;
1919 struct Scsi_Host *shost;
2fcee4bf 1920 uint32_t if_type;
2e90f4b5
JS
1921 struct lpfc_register portstat_reg = {0};
1922 uint32_t reg_err1, reg_err2;
1923 uint32_t uerrlo_reg, uemasklo_reg;
65791f1f 1924 uint32_t smphr_port_status = 0, pci_rd_rc1, pci_rd_rc2;
e10b2022 1925 bool en_rn_msg = true;
946727dc 1926 struct temp_event temp_event_data;
65791f1f
JS
1927 struct lpfc_register portsmphr_reg;
1928 int rc, i;
da0436e9
JS
1929
1930 /* If the pci channel is offline, ignore possible errors, since
1931 * we cannot communicate with the pci card anyway.
1932 */
32a93100 1933 if (pci_channel_offline(phba->pcidev)) {
372c187b 1934 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
32a93100
JS
1935 "3166 pci channel is offline\n");
1936 lpfc_sli4_offline_eratt(phba);
da0436e9 1937 return;
32a93100 1938 }
da0436e9 1939
65791f1f 1940 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
2fcee4bf
JS
1941 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
1942 switch (if_type) {
1943 case LPFC_SLI_INTF_IF_TYPE_0:
2e90f4b5
JS
1944 pci_rd_rc1 = lpfc_readl(
1945 phba->sli4_hba.u.if_type0.UERRLOregaddr,
1946 &uerrlo_reg);
1947 pci_rd_rc2 = lpfc_readl(
1948 phba->sli4_hba.u.if_type0.UEMASKLOregaddr,
1949 &uemasklo_reg);
1950 /* consider PCI bus read error as pci_channel_offline */
1951 if (pci_rd_rc1 == -EIO && pci_rd_rc2 == -EIO)
1952 return;
65791f1f
JS
1953 if (!(phba->hba_flag & HBA_RECOVERABLE_UE)) {
1954 lpfc_sli4_offline_eratt(phba);
1955 return;
1956 }
372c187b 1957 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
1958 "7623 Checking UE recoverable");
1959
1960 for (i = 0; i < phba->sli4_hba.ue_to_sr / 1000; i++) {
1961 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
1962 &portsmphr_reg.word0))
1963 continue;
1964
1965 smphr_port_status = bf_get(lpfc_port_smphr_port_status,
1966 &portsmphr_reg);
1967 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
1968 LPFC_PORT_SEM_UE_RECOVERABLE)
1969 break;
1970 /*Sleep for 1Sec, before checking SEMAPHORE */
1971 msleep(1000);
1972 }
1973
372c187b 1974 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
1975 "4827 smphr_port_status x%x : Waited %dSec",
1976 smphr_port_status, i);
1977
1978 /* Recoverable UE, reset the HBA device */
1979 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
1980 LPFC_PORT_SEM_UE_RECOVERABLE) {
1981 for (i = 0; i < 20; i++) {
1982 msleep(1000);
1983 if (!lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
1984 &portsmphr_reg.word0) &&
1985 (LPFC_POST_STAGE_PORT_READY ==
1986 bf_get(lpfc_port_smphr_port_status,
1987 &portsmphr_reg))) {
1988 rc = lpfc_sli4_port_sta_fn_reset(phba,
1989 LPFC_MBX_NO_WAIT, en_rn_msg);
1990 if (rc == 0)
1991 return;
372c187b
DK
1992 lpfc_printf_log(phba, KERN_ERR,
1993 LOG_TRACE_EVENT,
65791f1f
JS
1994 "4215 Failed to recover UE");
1995 break;
1996 }
1997 }
1998 }
372c187b 1999 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
2000 "7624 Firmware not ready: Failing UE recovery,"
2001 " waited %dSec", i);
8c24a4f6 2002 phba->link_state = LPFC_HBA_ERROR;
2fcee4bf 2003 break;
946727dc 2004
2fcee4bf 2005 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 2006 case LPFC_SLI_INTF_IF_TYPE_6:
2e90f4b5
JS
2007 pci_rd_rc1 = lpfc_readl(
2008 phba->sli4_hba.u.if_type2.STATUSregaddr,
2009 &portstat_reg.word0);
2010 /* consider PCI bus read error as pci_channel_offline */
6b5151fd 2011 if (pci_rd_rc1 == -EIO) {
372c187b 2012 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
6b5151fd
JS
2013 "3151 PCI bus read access failure: x%x\n",
2014 readl(phba->sli4_hba.u.if_type2.STATUSregaddr));
32a93100 2015 lpfc_sli4_offline_eratt(phba);
2e90f4b5 2016 return;
6b5151fd 2017 }
2e90f4b5
JS
2018 reg_err1 = readl(phba->sli4_hba.u.if_type2.ERR1regaddr);
2019 reg_err2 = readl(phba->sli4_hba.u.if_type2.ERR2regaddr);
2fcee4bf 2020 if (bf_get(lpfc_sliport_status_oti, &portstat_reg)) {
372c187b
DK
2021 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2022 "2889 Port Overtemperature event, "
2023 "taking port offline Data: x%x x%x\n",
2024 reg_err1, reg_err2);
946727dc 2025
310429ef 2026 phba->sfp_alarm |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
946727dc
JS
2027 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
2028 temp_event_data.event_code = LPFC_CRIT_TEMP;
2029 temp_event_data.data = 0xFFFFFFFF;
2030
2031 shost = lpfc_shost_from_vport(phba->pport);
2032 fc_host_post_vendor_event(shost, fc_get_event_number(),
2033 sizeof(temp_event_data),
2034 (char *)&temp_event_data,
2035 SCSI_NL_VID_TYPE_PCI
2036 | PCI_VENDOR_ID_EMULEX);
2037
2fcee4bf
JS
2038 spin_lock_irq(&phba->hbalock);
2039 phba->over_temp_state = HBA_OVER_TEMP;
2040 spin_unlock_irq(&phba->hbalock);
2041 lpfc_sli4_offline_eratt(phba);
946727dc 2042 return;
2fcee4bf 2043 }
2e90f4b5 2044 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
e10b2022 2045 reg_err2 == SLIPORT_ERR2_REG_FW_RESTART) {
372c187b 2046 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e10b2022
JS
2047 "3143 Port Down: Firmware Update "
2048 "Detected\n");
2049 en_rn_msg = false;
2050 } else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
2e90f4b5 2051 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
372c187b 2052 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2e90f4b5
JS
2053 "3144 Port Down: Debug Dump\n");
2054 else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
2055 reg_err2 == SLIPORT_ERR2_REG_FUNC_PROVISON)
372c187b 2056 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2e90f4b5 2057 "3145 Port Down: Provisioning\n");
618a5230 2058
946727dc
JS
2059 /* If resets are disabled then leave the HBA alone and return */
2060 if (!phba->cfg_enable_hba_reset)
2061 return;
2062
618a5230 2063 /* Check port status register for function reset */
e10b2022
JS
2064 rc = lpfc_sli4_port_sta_fn_reset(phba, LPFC_MBX_NO_WAIT,
2065 en_rn_msg);
618a5230
JS
2066 if (rc == 0) {
2067 /* don't report event on forced debug dump */
2068 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
2069 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
2070 return;
2071 else
2072 break;
2fcee4bf 2073 }
618a5230 2074 /* fall through for not able to recover */
372c187b 2075 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
8c24a4f6
JS
2076 "3152 Unrecoverable error\n");
2077 phba->link_state = LPFC_HBA_ERROR;
2fcee4bf
JS
2078 break;
2079 case LPFC_SLI_INTF_IF_TYPE_1:
2080 default:
2081 break;
2082 }
2e90f4b5
JS
2083 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
2084 "3123 Report dump event to upper layer\n");
2085 /* Send an internal error event to mgmt application */
2086 lpfc_board_errevt_to_mgmt(phba);
2087
2088 event_data = FC_REG_DUMP_EVENT;
2089 shost = lpfc_shost_from_vport(vport);
2090 fc_host_post_vendor_event(shost, fc_get_event_number(),
2091 sizeof(event_data), (char *) &event_data,
2092 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
da0436e9
JS
2093}
2094
2095/**
2096 * lpfc_handle_eratt - Wrapper func for handling hba error attention
2097 * @phba: pointer to lpfc HBA data structure.
2098 *
2099 * This routine wraps the actual SLI3 or SLI4 hba error attention handling
2100 * routine from the API jump table function pointer from the lpfc_hba struct.
2101 *
2102 * Return codes
af901ca1 2103 * 0 - success.
da0436e9
JS
2104 * Any other value - error.
2105 **/
2106void
2107lpfc_handle_eratt(struct lpfc_hba *phba)
2108{
2109 (*phba->lpfc_handle_eratt)(phba);
2110}
2111
e59058c4 2112/**
3621a710 2113 * lpfc_handle_latt - The HBA link event handler
e59058c4
JS
2114 * @phba: pointer to lpfc hba data structure.
2115 *
2116 * This routine is invoked from the worker thread to handle a HBA host
895427bd 2117 * attention link event. SLI3 only.
e59058c4 2118 **/
dea3101e 2119void
2e0fef85 2120lpfc_handle_latt(struct lpfc_hba *phba)
dea3101e 2121{
2e0fef85
JS
2122 struct lpfc_vport *vport = phba->pport;
2123 struct lpfc_sli *psli = &phba->sli;
dea3101e 2124 LPFC_MBOXQ_t *pmb;
2125 volatile uint32_t control;
2126 struct lpfc_dmabuf *mp;
09372820 2127 int rc = 0;
dea3101e 2128
2129 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
09372820
JS
2130 if (!pmb) {
2131 rc = 1;
dea3101e 2132 goto lpfc_handle_latt_err_exit;
09372820 2133 }
dea3101e 2134
2135 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
09372820
JS
2136 if (!mp) {
2137 rc = 2;
dea3101e 2138 goto lpfc_handle_latt_free_pmb;
09372820 2139 }
dea3101e 2140
2141 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
09372820
JS
2142 if (!mp->virt) {
2143 rc = 3;
dea3101e 2144 goto lpfc_handle_latt_free_mp;
09372820 2145 }
dea3101e 2146
6281bfe0 2147 /* Cleanup any outstanding ELS commands */
549e55cd 2148 lpfc_els_flush_all_cmd(phba);
dea3101e 2149
2150 psli->slistat.link_event++;
76a95d75
JS
2151 lpfc_read_topology(phba, pmb, mp);
2152 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
2e0fef85 2153 pmb->vport = vport;
0d2b6b83 2154 /* Block ELS IOCBs until we have processed this mbox command */
895427bd 2155 phba->sli.sli3_ring[LPFC_ELS_RING].flag |= LPFC_STOP_IOCB_EVENT;
0b727fea 2156 rc = lpfc_sli_issue_mbox (phba, pmb, MBX_NOWAIT);
09372820
JS
2157 if (rc == MBX_NOT_FINISHED) {
2158 rc = 4;
14691150 2159 goto lpfc_handle_latt_free_mbuf;
09372820 2160 }
dea3101e 2161
2162 /* Clear Link Attention in HA REG */
2e0fef85 2163 spin_lock_irq(&phba->hbalock);
dea3101e 2164 writel(HA_LATT, phba->HAregaddr);
2165 readl(phba->HAregaddr); /* flush */
2e0fef85 2166 spin_unlock_irq(&phba->hbalock);
dea3101e 2167
2168 return;
2169
14691150 2170lpfc_handle_latt_free_mbuf:
895427bd 2171 phba->sli.sli3_ring[LPFC_ELS_RING].flag &= ~LPFC_STOP_IOCB_EVENT;
14691150 2172 lpfc_mbuf_free(phba, mp->virt, mp->phys);
dea3101e 2173lpfc_handle_latt_free_mp:
2174 kfree(mp);
2175lpfc_handle_latt_free_pmb:
1dcb58e5 2176 mempool_free(pmb, phba->mbox_mem_pool);
dea3101e 2177lpfc_handle_latt_err_exit:
2178 /* Enable Link attention interrupts */
2e0fef85 2179 spin_lock_irq(&phba->hbalock);
dea3101e 2180 psli->sli_flag |= LPFC_PROCESS_LA;
2181 control = readl(phba->HCregaddr);
2182 control |= HC_LAINT_ENA;
2183 writel(control, phba->HCregaddr);
2184 readl(phba->HCregaddr); /* flush */
2185
2186 /* Clear Link Attention in HA REG */
2187 writel(HA_LATT, phba->HAregaddr);
2188 readl(phba->HAregaddr); /* flush */
2e0fef85 2189 spin_unlock_irq(&phba->hbalock);
dea3101e 2190 lpfc_linkdown(phba);
2e0fef85 2191 phba->link_state = LPFC_HBA_ERROR;
dea3101e 2192
372c187b
DK
2193 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2194 "0300 LATT: Cannot issue READ_LA: Data:%d\n", rc);
dea3101e 2195
2196 return;
2197}
2198
e59058c4 2199/**
3621a710 2200 * lpfc_parse_vpd - Parse VPD (Vital Product Data)
e59058c4
JS
2201 * @phba: pointer to lpfc hba data structure.
2202 * @vpd: pointer to the vital product data.
2203 * @len: length of the vital product data in bytes.
2204 *
2205 * This routine parses the Vital Product Data (VPD). The VPD is treated as
2206 * an array of characters. In this routine, the ModelName, ProgramType, and
2207 * ModelDesc, etc. fields of the phba data structure will be populated.
2208 *
2209 * Return codes
2210 * 0 - pointer to the VPD passed in is NULL
2211 * 1 - success
2212 **/
3772a991 2213int
2e0fef85 2214lpfc_parse_vpd(struct lpfc_hba *phba, uint8_t *vpd, int len)
dea3101e 2215{
2216 uint8_t lenlo, lenhi;
07da60c1 2217 int Length;
dea3101e 2218 int i, j;
2219 int finished = 0;
2220 int index = 0;
2221
2222 if (!vpd)
2223 return 0;
2224
2225 /* Vital Product */
ed957684 2226 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011 2227 "0455 Vital Product Data: x%x x%x x%x x%x\n",
dea3101e 2228 (uint32_t) vpd[0], (uint32_t) vpd[1], (uint32_t) vpd[2],
2229 (uint32_t) vpd[3]);
74b72a59 2230 while (!finished && (index < (len - 4))) {
dea3101e 2231 switch (vpd[index]) {
2232 case 0x82:
74b72a59 2233 case 0x91:
dea3101e 2234 index += 1;
2235 lenlo = vpd[index];
2236 index += 1;
2237 lenhi = vpd[index];
2238 index += 1;
2239 i = ((((unsigned short)lenhi) << 8) + lenlo);
2240 index += i;
2241 break;
2242 case 0x90:
2243 index += 1;
2244 lenlo = vpd[index];
2245 index += 1;
2246 lenhi = vpd[index];
2247 index += 1;
2248 Length = ((((unsigned short)lenhi) << 8) + lenlo);
74b72a59
JW
2249 if (Length > len - index)
2250 Length = len - index;
dea3101e 2251 while (Length > 0) {
2252 /* Look for Serial Number */
2253 if ((vpd[index] == 'S') && (vpd[index+1] == 'N')) {
2254 index += 2;
2255 i = vpd[index];
2256 index += 1;
2257 j = 0;
2258 Length -= (3+i);
2259 while(i--) {
2260 phba->SerialNumber[j++] = vpd[index++];
2261 if (j == 31)
2262 break;
2263 }
2264 phba->SerialNumber[j] = 0;
2265 continue;
2266 }
2267 else if ((vpd[index] == 'V') && (vpd[index+1] == '1')) {
2268 phba->vpd_flag |= VPD_MODEL_DESC;
2269 index += 2;
2270 i = vpd[index];
2271 index += 1;
2272 j = 0;
2273 Length -= (3+i);
2274 while(i--) {
2275 phba->ModelDesc[j++] = vpd[index++];
2276 if (j == 255)
2277 break;
2278 }
2279 phba->ModelDesc[j] = 0;
2280 continue;
2281 }
2282 else if ((vpd[index] == 'V') && (vpd[index+1] == '2')) {
2283 phba->vpd_flag |= VPD_MODEL_NAME;
2284 index += 2;
2285 i = vpd[index];
2286 index += 1;
2287 j = 0;
2288 Length -= (3+i);
2289 while(i--) {
2290 phba->ModelName[j++] = vpd[index++];
2291 if (j == 79)
2292 break;
2293 }
2294 phba->ModelName[j] = 0;
2295 continue;
2296 }
2297 else if ((vpd[index] == 'V') && (vpd[index+1] == '3')) {
2298 phba->vpd_flag |= VPD_PROGRAM_TYPE;
2299 index += 2;
2300 i = vpd[index];
2301 index += 1;
2302 j = 0;
2303 Length -= (3+i);
2304 while(i--) {
2305 phba->ProgramType[j++] = vpd[index++];
2306 if (j == 255)
2307 break;
2308 }
2309 phba->ProgramType[j] = 0;
2310 continue;
2311 }
2312 else if ((vpd[index] == 'V') && (vpd[index+1] == '4')) {
2313 phba->vpd_flag |= VPD_PORT;
2314 index += 2;
2315 i = vpd[index];
2316 index += 1;
2317 j = 0;
2318 Length -= (3+i);
2319 while(i--) {
cd1c8301
JS
2320 if ((phba->sli_rev == LPFC_SLI_REV4) &&
2321 (phba->sli4_hba.pport_name_sta ==
2322 LPFC_SLI4_PPNAME_GET)) {
2323 j++;
2324 index++;
2325 } else
2326 phba->Port[j++] = vpd[index++];
2327 if (j == 19)
2328 break;
dea3101e 2329 }
cd1c8301
JS
2330 if ((phba->sli_rev != LPFC_SLI_REV4) ||
2331 (phba->sli4_hba.pport_name_sta ==
2332 LPFC_SLI4_PPNAME_NON))
2333 phba->Port[j] = 0;
dea3101e 2334 continue;
2335 }
2336 else {
2337 index += 2;
2338 i = vpd[index];
2339 index += 1;
2340 index += i;
2341 Length -= (3 + i);
2342 }
2343 }
2344 finished = 0;
2345 break;
2346 case 0x78:
2347 finished = 1;
2348 break;
2349 default:
2350 index ++;
2351 break;
2352 }
74b72a59 2353 }
dea3101e 2354
2355 return(1);
2356}
2357
e59058c4 2358/**
3621a710 2359 * lpfc_get_hba_model_desc - Retrieve HBA device model name and description
e59058c4
JS
2360 * @phba: pointer to lpfc hba data structure.
2361 * @mdp: pointer to the data structure to hold the derived model name.
2362 * @descp: pointer to the data structure to hold the derived description.
2363 *
2364 * This routine retrieves HBA's description based on its registered PCI device
2365 * ID. The @descp passed into this function points to an array of 256 chars. It
2366 * shall be returned with the model name, maximum speed, and the host bus type.
2367 * The @mdp passed into this function points to an array of 80 chars. When the
2368 * function returns, the @mdp will be filled with the model name.
2369 **/
dea3101e 2370static void
2e0fef85 2371lpfc_get_hba_model_desc(struct lpfc_hba *phba, uint8_t *mdp, uint8_t *descp)
dea3101e 2372{
2373 lpfc_vpd_t *vp;
fefcb2b6 2374 uint16_t dev_id = phba->pcidev->device;
74b72a59 2375 int max_speed;
84774a4d 2376 int GE = 0;
da0436e9 2377 int oneConnect = 0; /* default is not a oneConnect */
74b72a59 2378 struct {
a747c9ce
JS
2379 char *name;
2380 char *bus;
2381 char *function;
2382 } m = {"<Unknown>", "", ""};
74b72a59
JW
2383
2384 if (mdp && mdp[0] != '\0'
2385 && descp && descp[0] != '\0')
2386 return;
2387
fbd8a6ba
JS
2388 if (phba->lmt & LMT_64Gb)
2389 max_speed = 64;
2390 else if (phba->lmt & LMT_32Gb)
d38dd52c
JS
2391 max_speed = 32;
2392 else if (phba->lmt & LMT_16Gb)
c0c11512
JS
2393 max_speed = 16;
2394 else if (phba->lmt & LMT_10Gb)
74b72a59
JW
2395 max_speed = 10;
2396 else if (phba->lmt & LMT_8Gb)
2397 max_speed = 8;
2398 else if (phba->lmt & LMT_4Gb)
2399 max_speed = 4;
2400 else if (phba->lmt & LMT_2Gb)
2401 max_speed = 2;
4169d868 2402 else if (phba->lmt & LMT_1Gb)
74b72a59 2403 max_speed = 1;
4169d868
JS
2404 else
2405 max_speed = 0;
dea3101e 2406
2407 vp = &phba->vpd;
dea3101e 2408
e4adb204 2409 switch (dev_id) {
06325e74 2410 case PCI_DEVICE_ID_FIREFLY:
12222f4f
JS
2411 m = (typeof(m)){"LP6000", "PCI",
2412 "Obsolete, Unsupported Fibre Channel Adapter"};
06325e74 2413 break;
dea3101e 2414 case PCI_DEVICE_ID_SUPERFLY:
2415 if (vp->rev.biuRev >= 1 && vp->rev.biuRev <= 3)
12222f4f 2416 m = (typeof(m)){"LP7000", "PCI", ""};
dea3101e 2417 else
12222f4f
JS
2418 m = (typeof(m)){"LP7000E", "PCI", ""};
2419 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
dea3101e 2420 break;
2421 case PCI_DEVICE_ID_DRAGONFLY:
a747c9ce 2422 m = (typeof(m)){"LP8000", "PCI",
12222f4f 2423 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2424 break;
2425 case PCI_DEVICE_ID_CENTAUR:
2426 if (FC_JEDEC_ID(vp->rev.biuRev) == CENTAUR_2G_JEDEC_ID)
12222f4f 2427 m = (typeof(m)){"LP9002", "PCI", ""};
dea3101e 2428 else
12222f4f
JS
2429 m = (typeof(m)){"LP9000", "PCI", ""};
2430 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
dea3101e 2431 break;
2432 case PCI_DEVICE_ID_RFLY:
a747c9ce 2433 m = (typeof(m)){"LP952", "PCI",
12222f4f 2434 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2435 break;
2436 case PCI_DEVICE_ID_PEGASUS:
a747c9ce 2437 m = (typeof(m)){"LP9802", "PCI-X",
12222f4f 2438 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2439 break;
2440 case PCI_DEVICE_ID_THOR:
a747c9ce 2441 m = (typeof(m)){"LP10000", "PCI-X",
12222f4f 2442 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2443 break;
2444 case PCI_DEVICE_ID_VIPER:
a747c9ce 2445 m = (typeof(m)){"LPX1000", "PCI-X",
12222f4f 2446 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2447 break;
2448 case PCI_DEVICE_ID_PFLY:
a747c9ce 2449 m = (typeof(m)){"LP982", "PCI-X",
12222f4f 2450 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2451 break;
2452 case PCI_DEVICE_ID_TFLY:
a747c9ce 2453 m = (typeof(m)){"LP1050", "PCI-X",
12222f4f 2454 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2455 break;
2456 case PCI_DEVICE_ID_HELIOS:
a747c9ce 2457 m = (typeof(m)){"LP11000", "PCI-X2",
12222f4f 2458 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2459 break;
e4adb204 2460 case PCI_DEVICE_ID_HELIOS_SCSP:
a747c9ce 2461 m = (typeof(m)){"LP11000-SP", "PCI-X2",
12222f4f 2462 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2463 break;
2464 case PCI_DEVICE_ID_HELIOS_DCSP:
a747c9ce 2465 m = (typeof(m)){"LP11002-SP", "PCI-X2",
12222f4f 2466 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2467 break;
2468 case PCI_DEVICE_ID_NEPTUNE:
12222f4f
JS
2469 m = (typeof(m)){"LPe1000", "PCIe",
2470 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2471 break;
2472 case PCI_DEVICE_ID_NEPTUNE_SCSP:
12222f4f
JS
2473 m = (typeof(m)){"LPe1000-SP", "PCIe",
2474 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2475 break;
2476 case PCI_DEVICE_ID_NEPTUNE_DCSP:
12222f4f
JS
2477 m = (typeof(m)){"LPe1002-SP", "PCIe",
2478 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204 2479 break;
dea3101e 2480 case PCI_DEVICE_ID_BMID:
a747c9ce 2481 m = (typeof(m)){"LP1150", "PCI-X2", "Fibre Channel Adapter"};
dea3101e 2482 break;
2483 case PCI_DEVICE_ID_BSMB:
12222f4f
JS
2484 m = (typeof(m)){"LP111", "PCI-X2",
2485 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2486 break;
2487 case PCI_DEVICE_ID_ZEPHYR:
a747c9ce 2488 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
dea3101e 2489 break;
e4adb204 2490 case PCI_DEVICE_ID_ZEPHYR_SCSP:
a747c9ce 2491 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
e4adb204
JSEC
2492 break;
2493 case PCI_DEVICE_ID_ZEPHYR_DCSP:
a747c9ce 2494 m = (typeof(m)){"LP2105", "PCIe", "FCoE Adapter"};
a257bf90 2495 GE = 1;
e4adb204 2496 break;
dea3101e 2497 case PCI_DEVICE_ID_ZMID:
a747c9ce 2498 m = (typeof(m)){"LPe1150", "PCIe", "Fibre Channel Adapter"};
dea3101e 2499 break;
2500 case PCI_DEVICE_ID_ZSMB:
a747c9ce 2501 m = (typeof(m)){"LPe111", "PCIe", "Fibre Channel Adapter"};
dea3101e 2502 break;
2503 case PCI_DEVICE_ID_LP101:
12222f4f
JS
2504 m = (typeof(m)){"LP101", "PCI-X",
2505 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2506 break;
2507 case PCI_DEVICE_ID_LP10000S:
12222f4f
JS
2508 m = (typeof(m)){"LP10000-S", "PCI",
2509 "Obsolete, Unsupported Fibre Channel Adapter"};
06325e74 2510 break;
e4adb204 2511 case PCI_DEVICE_ID_LP11000S:
12222f4f
JS
2512 m = (typeof(m)){"LP11000-S", "PCI-X2",
2513 "Obsolete, Unsupported Fibre Channel Adapter"};
18a3b596 2514 break;
e4adb204 2515 case PCI_DEVICE_ID_LPE11000S:
12222f4f
JS
2516 m = (typeof(m)){"LPe11000-S", "PCIe",
2517 "Obsolete, Unsupported Fibre Channel Adapter"};
5cc36b3c 2518 break;
b87eab38 2519 case PCI_DEVICE_ID_SAT:
a747c9ce 2520 m = (typeof(m)){"LPe12000", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2521 break;
2522 case PCI_DEVICE_ID_SAT_MID:
a747c9ce 2523 m = (typeof(m)){"LPe1250", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2524 break;
2525 case PCI_DEVICE_ID_SAT_SMB:
a747c9ce 2526 m = (typeof(m)){"LPe121", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2527 break;
2528 case PCI_DEVICE_ID_SAT_DCSP:
a747c9ce 2529 m = (typeof(m)){"LPe12002-SP", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2530 break;
2531 case PCI_DEVICE_ID_SAT_SCSP:
a747c9ce 2532 m = (typeof(m)){"LPe12000-SP", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2533 break;
2534 case PCI_DEVICE_ID_SAT_S:
a747c9ce 2535 m = (typeof(m)){"LPe12000-S", "PCIe", "Fibre Channel Adapter"};
b87eab38 2536 break;
84774a4d 2537 case PCI_DEVICE_ID_HORNET:
12222f4f
JS
2538 m = (typeof(m)){"LP21000", "PCIe",
2539 "Obsolete, Unsupported FCoE Adapter"};
84774a4d
JS
2540 GE = 1;
2541 break;
2542 case PCI_DEVICE_ID_PROTEUS_VF:
a747c9ce 2543 m = (typeof(m)){"LPev12000", "PCIe IOV",
12222f4f 2544 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d
JS
2545 break;
2546 case PCI_DEVICE_ID_PROTEUS_PF:
a747c9ce 2547 m = (typeof(m)){"LPev12000", "PCIe IOV",
12222f4f 2548 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d
JS
2549 break;
2550 case PCI_DEVICE_ID_PROTEUS_S:
a747c9ce 2551 m = (typeof(m)){"LPemv12002-S", "PCIe IOV",
12222f4f 2552 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d 2553 break;
da0436e9
JS
2554 case PCI_DEVICE_ID_TIGERSHARK:
2555 oneConnect = 1;
a747c9ce 2556 m = (typeof(m)){"OCe10100", "PCIe", "FCoE"};
da0436e9 2557 break;
a747c9ce 2558 case PCI_DEVICE_ID_TOMCAT:
6669f9bb 2559 oneConnect = 1;
a747c9ce
JS
2560 m = (typeof(m)){"OCe11100", "PCIe", "FCoE"};
2561 break;
2562 case PCI_DEVICE_ID_FALCON:
2563 m = (typeof(m)){"LPSe12002-ML1-E", "PCIe",
2564 "EmulexSecure Fibre"};
6669f9bb 2565 break;
98fc5dd9
JS
2566 case PCI_DEVICE_ID_BALIUS:
2567 m = (typeof(m)){"LPVe12002", "PCIe Shared I/O",
12222f4f 2568 "Obsolete, Unsupported Fibre Channel Adapter"};
98fc5dd9 2569 break;
085c647c 2570 case PCI_DEVICE_ID_LANCER_FC:
c0c11512 2571 m = (typeof(m)){"LPe16000", "PCIe", "Fibre Channel Adapter"};
085c647c 2572 break;
12222f4f
JS
2573 case PCI_DEVICE_ID_LANCER_FC_VF:
2574 m = (typeof(m)){"LPe16000", "PCIe",
2575 "Obsolete, Unsupported Fibre Channel Adapter"};
2576 break;
085c647c
JS
2577 case PCI_DEVICE_ID_LANCER_FCOE:
2578 oneConnect = 1;
079b5c91 2579 m = (typeof(m)){"OCe15100", "PCIe", "FCoE"};
085c647c 2580 break;
12222f4f
JS
2581 case PCI_DEVICE_ID_LANCER_FCOE_VF:
2582 oneConnect = 1;
2583 m = (typeof(m)){"OCe15100", "PCIe",
2584 "Obsolete, Unsupported FCoE"};
2585 break;
d38dd52c
JS
2586 case PCI_DEVICE_ID_LANCER_G6_FC:
2587 m = (typeof(m)){"LPe32000", "PCIe", "Fibre Channel Adapter"};
2588 break;
c238b9b6
JS
2589 case PCI_DEVICE_ID_LANCER_G7_FC:
2590 m = (typeof(m)){"LPe36000", "PCIe", "Fibre Channel Adapter"};
2591 break;
f8cafd38
JS
2592 case PCI_DEVICE_ID_SKYHAWK:
2593 case PCI_DEVICE_ID_SKYHAWK_VF:
2594 oneConnect = 1;
2595 m = (typeof(m)){"OCe14000", "PCIe", "FCoE"};
2596 break;
5cc36b3c 2597 default:
a747c9ce 2598 m = (typeof(m)){"Unknown", "", ""};
e4adb204 2599 break;
dea3101e 2600 }
74b72a59
JW
2601
2602 if (mdp && mdp[0] == '\0')
2603 snprintf(mdp, 79,"%s", m.name);
c0c11512
JS
2604 /*
2605 * oneConnect hba requires special processing, they are all initiators
da0436e9
JS
2606 * and we put the port number on the end
2607 */
2608 if (descp && descp[0] == '\0') {
2609 if (oneConnect)
2610 snprintf(descp, 255,
4169d868 2611 "Emulex OneConnect %s, %s Initiator %s",
a747c9ce 2612 m.name, m.function,
da0436e9 2613 phba->Port);
4169d868
JS
2614 else if (max_speed == 0)
2615 snprintf(descp, 255,
290237d2 2616 "Emulex %s %s %s",
4169d868 2617 m.name, m.bus, m.function);
da0436e9
JS
2618 else
2619 snprintf(descp, 255,
2620 "Emulex %s %d%s %s %s",
a747c9ce
JS
2621 m.name, max_speed, (GE) ? "GE" : "Gb",
2622 m.bus, m.function);
da0436e9 2623 }
dea3101e 2624}
2625
e59058c4 2626/**
3621a710 2627 * lpfc_post_buffer - Post IOCB(s) with DMA buffer descriptor(s) to a IOCB ring
e59058c4
JS
2628 * @phba: pointer to lpfc hba data structure.
2629 * @pring: pointer to a IOCB ring.
2630 * @cnt: the number of IOCBs to be posted to the IOCB ring.
2631 *
2632 * This routine posts a given number of IOCBs with the associated DMA buffer
2633 * descriptors specified by the cnt argument to the given IOCB ring.
2634 *
2635 * Return codes
2636 * The number of IOCBs NOT able to be posted to the IOCB ring.
2637 **/
dea3101e 2638int
495a714c 2639lpfc_post_buffer(struct lpfc_hba *phba, struct lpfc_sli_ring *pring, int cnt)
dea3101e 2640{
2641 IOCB_t *icmd;
0bd4ca25 2642 struct lpfc_iocbq *iocb;
dea3101e 2643 struct lpfc_dmabuf *mp1, *mp2;
2644
2645 cnt += pring->missbufcnt;
2646
2647 /* While there are buffers to post */
2648 while (cnt > 0) {
2649 /* Allocate buffer for command iocb */
0bd4ca25 2650 iocb = lpfc_sli_get_iocbq(phba);
dea3101e 2651 if (iocb == NULL) {
2652 pring->missbufcnt = cnt;
2653 return cnt;
2654 }
dea3101e 2655 icmd = &iocb->iocb;
2656
2657 /* 2 buffers can be posted per command */
2658 /* Allocate buffer to post */
2659 mp1 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2660 if (mp1)
98c9ea5c
JS
2661 mp1->virt = lpfc_mbuf_alloc(phba, MEM_PRI, &mp1->phys);
2662 if (!mp1 || !mp1->virt) {
c9475cb0 2663 kfree(mp1);
604a3e30 2664 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2665 pring->missbufcnt = cnt;
2666 return cnt;
2667 }
2668
2669 INIT_LIST_HEAD(&mp1->list);
2670 /* Allocate buffer to post */
2671 if (cnt > 1) {
2672 mp2 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2673 if (mp2)
2674 mp2->virt = lpfc_mbuf_alloc(phba, MEM_PRI,
2675 &mp2->phys);
98c9ea5c 2676 if (!mp2 || !mp2->virt) {
c9475cb0 2677 kfree(mp2);
dea3101e 2678 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2679 kfree(mp1);
604a3e30 2680 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2681 pring->missbufcnt = cnt;
2682 return cnt;
2683 }
2684
2685 INIT_LIST_HEAD(&mp2->list);
2686 } else {
2687 mp2 = NULL;
2688 }
2689
2690 icmd->un.cont64[0].addrHigh = putPaddrHigh(mp1->phys);
2691 icmd->un.cont64[0].addrLow = putPaddrLow(mp1->phys);
2692 icmd->un.cont64[0].tus.f.bdeSize = FCELSSIZE;
2693 icmd->ulpBdeCount = 1;
2694 cnt--;
2695 if (mp2) {
2696 icmd->un.cont64[1].addrHigh = putPaddrHigh(mp2->phys);
2697 icmd->un.cont64[1].addrLow = putPaddrLow(mp2->phys);
2698 icmd->un.cont64[1].tus.f.bdeSize = FCELSSIZE;
2699 cnt--;
2700 icmd->ulpBdeCount = 2;
2701 }
2702
2703 icmd->ulpCommand = CMD_QUE_RING_BUF64_CN;
2704 icmd->ulpLe = 1;
2705
3772a991
JS
2706 if (lpfc_sli_issue_iocb(phba, pring->ringno, iocb, 0) ==
2707 IOCB_ERROR) {
dea3101e 2708 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2709 kfree(mp1);
2710 cnt++;
2711 if (mp2) {
2712 lpfc_mbuf_free(phba, mp2->virt, mp2->phys);
2713 kfree(mp2);
2714 cnt++;
2715 }
604a3e30 2716 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2717 pring->missbufcnt = cnt;
dea3101e 2718 return cnt;
2719 }
dea3101e 2720 lpfc_sli_ringpostbuf_put(phba, pring, mp1);
92d7f7b0 2721 if (mp2)
dea3101e 2722 lpfc_sli_ringpostbuf_put(phba, pring, mp2);
dea3101e 2723 }
2724 pring->missbufcnt = 0;
2725 return 0;
2726}
2727
e59058c4 2728/**
3621a710 2729 * lpfc_post_rcv_buf - Post the initial receive IOCB buffers to ELS ring
e59058c4
JS
2730 * @phba: pointer to lpfc hba data structure.
2731 *
2732 * This routine posts initial receive IOCB buffers to the ELS ring. The
2733 * current number of initial IOCB buffers specified by LPFC_BUF_RING0 is
895427bd 2734 * set to 64 IOCBs. SLI3 only.
e59058c4
JS
2735 *
2736 * Return codes
2737 * 0 - success (currently always success)
2738 **/
dea3101e 2739static int
2e0fef85 2740lpfc_post_rcv_buf(struct lpfc_hba *phba)
dea3101e 2741{
2742 struct lpfc_sli *psli = &phba->sli;
2743
2744 /* Ring 0, ELS / CT buffers */
895427bd 2745 lpfc_post_buffer(phba, &psli->sli3_ring[LPFC_ELS_RING], LPFC_BUF_RING0);
dea3101e 2746 /* Ring 2 - FCP no buffers needed */
2747
2748 return 0;
2749}
2750
2751#define S(N,V) (((V)<<(N))|((V)>>(32-(N))))
2752
e59058c4 2753/**
3621a710 2754 * lpfc_sha_init - Set up initial array of hash table entries
e59058c4
JS
2755 * @HashResultPointer: pointer to an array as hash table.
2756 *
2757 * This routine sets up the initial values to the array of hash table entries
2758 * for the LC HBAs.
2759 **/
dea3101e 2760static void
2761lpfc_sha_init(uint32_t * HashResultPointer)
2762{
2763 HashResultPointer[0] = 0x67452301;
2764 HashResultPointer[1] = 0xEFCDAB89;
2765 HashResultPointer[2] = 0x98BADCFE;
2766 HashResultPointer[3] = 0x10325476;
2767 HashResultPointer[4] = 0xC3D2E1F0;
2768}
2769
e59058c4 2770/**
3621a710 2771 * lpfc_sha_iterate - Iterate initial hash table with the working hash table
e59058c4
JS
2772 * @HashResultPointer: pointer to an initial/result hash table.
2773 * @HashWorkingPointer: pointer to an working hash table.
2774 *
2775 * This routine iterates an initial hash table pointed by @HashResultPointer
2776 * with the values from the working hash table pointeed by @HashWorkingPointer.
2777 * The results are putting back to the initial hash table, returned through
2778 * the @HashResultPointer as the result hash table.
2779 **/
dea3101e 2780static void
2781lpfc_sha_iterate(uint32_t * HashResultPointer, uint32_t * HashWorkingPointer)
2782{
2783 int t;
2784 uint32_t TEMP;
2785 uint32_t A, B, C, D, E;
2786 t = 16;
2787 do {
2788 HashWorkingPointer[t] =
2789 S(1,
2790 HashWorkingPointer[t - 3] ^ HashWorkingPointer[t -
2791 8] ^
2792 HashWorkingPointer[t - 14] ^ HashWorkingPointer[t - 16]);
2793 } while (++t <= 79);
2794 t = 0;
2795 A = HashResultPointer[0];
2796 B = HashResultPointer[1];
2797 C = HashResultPointer[2];
2798 D = HashResultPointer[3];
2799 E = HashResultPointer[4];
2800
2801 do {
2802 if (t < 20) {
2803 TEMP = ((B & C) | ((~B) & D)) + 0x5A827999;
2804 } else if (t < 40) {
2805 TEMP = (B ^ C ^ D) + 0x6ED9EBA1;
2806 } else if (t < 60) {
2807 TEMP = ((B & C) | (B & D) | (C & D)) + 0x8F1BBCDC;
2808 } else {
2809 TEMP = (B ^ C ^ D) + 0xCA62C1D6;
2810 }
2811 TEMP += S(5, A) + E + HashWorkingPointer[t];
2812 E = D;
2813 D = C;
2814 C = S(30, B);
2815 B = A;
2816 A = TEMP;
2817 } while (++t <= 79);
2818
2819 HashResultPointer[0] += A;
2820 HashResultPointer[1] += B;
2821 HashResultPointer[2] += C;
2822 HashResultPointer[3] += D;
2823 HashResultPointer[4] += E;
2824
2825}
2826
e59058c4 2827/**
3621a710 2828 * lpfc_challenge_key - Create challenge key based on WWPN of the HBA
e59058c4
JS
2829 * @RandomChallenge: pointer to the entry of host challenge random number array.
2830 * @HashWorking: pointer to the entry of the working hash array.
2831 *
2832 * This routine calculates the working hash array referred by @HashWorking
2833 * from the challenge random numbers associated with the host, referred by
2834 * @RandomChallenge. The result is put into the entry of the working hash
2835 * array and returned by reference through @HashWorking.
2836 **/
dea3101e 2837static void
2838lpfc_challenge_key(uint32_t * RandomChallenge, uint32_t * HashWorking)
2839{
2840 *HashWorking = (*RandomChallenge ^ *HashWorking);
2841}
2842
e59058c4 2843/**
3621a710 2844 * lpfc_hba_init - Perform special handling for LC HBA initialization
e59058c4
JS
2845 * @phba: pointer to lpfc hba data structure.
2846 * @hbainit: pointer to an array of unsigned 32-bit integers.
2847 *
2848 * This routine performs the special handling for LC HBA initialization.
2849 **/
dea3101e 2850void
2851lpfc_hba_init(struct lpfc_hba *phba, uint32_t *hbainit)
2852{
2853 int t;
2854 uint32_t *HashWorking;
2e0fef85 2855 uint32_t *pwwnn = (uint32_t *) phba->wwnn;
dea3101e 2856
bbfbbbc1 2857 HashWorking = kcalloc(80, sizeof(uint32_t), GFP_KERNEL);
dea3101e 2858 if (!HashWorking)
2859 return;
2860
dea3101e 2861 HashWorking[0] = HashWorking[78] = *pwwnn++;
2862 HashWorking[1] = HashWorking[79] = *pwwnn;
2863
2864 for (t = 0; t < 7; t++)
2865 lpfc_challenge_key(phba->RandomData + t, HashWorking + t);
2866
2867 lpfc_sha_init(hbainit);
2868 lpfc_sha_iterate(hbainit, HashWorking);
2869 kfree(HashWorking);
2870}
2871
e59058c4 2872/**
3621a710 2873 * lpfc_cleanup - Performs vport cleanups before deleting a vport
e59058c4
JS
2874 * @vport: pointer to a virtual N_Port data structure.
2875 *
2876 * This routine performs the necessary cleanups before deleting the @vport.
2877 * It invokes the discovery state machine to perform necessary state
2878 * transitions and to release the ndlps associated with the @vport. Note,
2879 * the physical port is treated as @vport 0.
2880 **/
87af33fe 2881void
2e0fef85 2882lpfc_cleanup(struct lpfc_vport *vport)
dea3101e 2883{
87af33fe 2884 struct lpfc_hba *phba = vport->phba;
dea3101e 2885 struct lpfc_nodelist *ndlp, *next_ndlp;
a8adb832 2886 int i = 0;
dea3101e 2887
87af33fe
JS
2888 if (phba->link_state > LPFC_LINK_DOWN)
2889 lpfc_port_link_failure(vport);
2890
2891 list_for_each_entry_safe(ndlp, next_ndlp, &vport->fc_nodes, nlp_listp) {
58da1ffb
JS
2892 if (vport->port_type != LPFC_PHYSICAL_PORT &&
2893 ndlp->nlp_DID == Fabric_DID) {
2894 /* Just free up ndlp with Fabric_DID for vports */
2895 lpfc_nlp_put(ndlp);
2896 continue;
2897 }
2898
a70e63ee
JS
2899 if (ndlp->nlp_DID == Fabric_Cntl_DID &&
2900 ndlp->nlp_state == NLP_STE_UNUSED_NODE) {
eff4a01b
JS
2901 lpfc_nlp_put(ndlp);
2902 continue;
2903 }
2904
e9b11083
JS
2905 /* Fabric Ports not in UNMAPPED state are cleaned up in the
2906 * DEVICE_RM event.
2907 */
2908 if (ndlp->nlp_type & NLP_FABRIC &&
2909 ndlp->nlp_state == NLP_STE_UNMAPPED_NODE)
87af33fe
JS
2910 lpfc_disc_state_machine(vport, ndlp, NULL,
2911 NLP_EVT_DEVICE_RECOVERY);
e47c9093 2912
e9b11083
JS
2913 if (!(ndlp->fc4_xpt_flags & (NVME_XPT_REGD|SCSI_XPT_REGD)))
2914 lpfc_disc_state_machine(vport, ndlp, NULL,
2915 NLP_EVT_DEVICE_RM);
87af33fe
JS
2916 }
2917
a8adb832
JS
2918 /* At this point, ALL ndlp's should be gone
2919 * because of the previous NLP_EVT_DEVICE_RM.
2920 * Lets wait for this to happen, if needed.
2921 */
87af33fe 2922 while (!list_empty(&vport->fc_nodes)) {
a8adb832 2923 if (i++ > 3000) {
372c187b
DK
2924 lpfc_printf_vlog(vport, KERN_ERR,
2925 LOG_TRACE_EVENT,
a8adb832 2926 "0233 Nodelist not empty\n");
e47c9093
JS
2927 list_for_each_entry_safe(ndlp, next_ndlp,
2928 &vport->fc_nodes, nlp_listp) {
2929 lpfc_printf_vlog(ndlp->vport, KERN_ERR,
e9b11083
JS
2930 LOG_TRACE_EVENT,
2931 "0282 did:x%x ndlp:x%px "
2932 "refcnt:%d xflags x%x nflag x%x\n",
2933 ndlp->nlp_DID, (void *)ndlp,
2934 kref_read(&ndlp->kref),
2935 ndlp->fc4_xpt_flags,
2936 ndlp->nlp_flag);
e47c9093 2937 }
a8adb832 2938 break;
87af33fe 2939 }
a8adb832
JS
2940
2941 /* Wait for any activity on ndlps to settle */
2942 msleep(10);
87af33fe 2943 }
1151e3ec 2944 lpfc_cleanup_vports_rrqs(vport, NULL);
dea3101e 2945}
2946
e59058c4 2947/**
3621a710 2948 * lpfc_stop_vport_timers - Stop all the timers associated with a vport
e59058c4
JS
2949 * @vport: pointer to a virtual N_Port data structure.
2950 *
2951 * This routine stops all the timers associated with a @vport. This function
2952 * is invoked before disabling or deleting a @vport. Note that the physical
2953 * port is treated as @vport 0.
2954 **/
92d7f7b0
JS
2955void
2956lpfc_stop_vport_timers(struct lpfc_vport *vport)
dea3101e 2957{
92d7f7b0 2958 del_timer_sync(&vport->els_tmofunc);
92494144 2959 del_timer_sync(&vport->delayed_disc_tmo);
92d7f7b0
JS
2960 lpfc_can_disctmo(vport);
2961 return;
dea3101e 2962}
2963
ecfd03c6
JS
2964/**
2965 * __lpfc_sli4_stop_fcf_redisc_wait_timer - Stop FCF rediscovery wait timer
2966 * @phba: pointer to lpfc hba data structure.
2967 *
2968 * This routine stops the SLI4 FCF rediscover wait timer if it's on. The
2969 * caller of this routine should already hold the host lock.
2970 **/
2971void
2972__lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2973{
5ac6b303
JS
2974 /* Clear pending FCF rediscovery wait flag */
2975 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
2976
ecfd03c6
JS
2977 /* Now, try to stop the timer */
2978 del_timer(&phba->fcf.redisc_wait);
2979}
2980
2981/**
2982 * lpfc_sli4_stop_fcf_redisc_wait_timer - Stop FCF rediscovery wait timer
2983 * @phba: pointer to lpfc hba data structure.
2984 *
2985 * This routine stops the SLI4 FCF rediscover wait timer if it's on. It
2986 * checks whether the FCF rediscovery wait timer is pending with the host
2987 * lock held before proceeding with disabling the timer and clearing the
2988 * wait timer pendig flag.
2989 **/
2990void
2991lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2992{
2993 spin_lock_irq(&phba->hbalock);
2994 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
2995 /* FCF rediscovery timer already fired or stopped */
2996 spin_unlock_irq(&phba->hbalock);
2997 return;
2998 }
2999 __lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
5ac6b303
JS
3000 /* Clear failover in progress flags */
3001 phba->fcf.fcf_flag &= ~(FCF_DEAD_DISC | FCF_ACVL_DISC);
ecfd03c6
JS
3002 spin_unlock_irq(&phba->hbalock);
3003}
3004
e59058c4 3005/**
3772a991 3006 * lpfc_stop_hba_timers - Stop all the timers associated with an HBA
e59058c4
JS
3007 * @phba: pointer to lpfc hba data structure.
3008 *
3009 * This routine stops all the timers associated with a HBA. This function is
3010 * invoked before either putting a HBA offline or unloading the driver.
3011 **/
3772a991
JS
3012void
3013lpfc_stop_hba_timers(struct lpfc_hba *phba)
dea3101e 3014{
cdb42bec
JS
3015 if (phba->pport)
3016 lpfc_stop_vport_timers(phba->pport);
32517fc0 3017 cancel_delayed_work_sync(&phba->eq_delay_work);
317aeb83 3018 cancel_delayed_work_sync(&phba->idle_stat_delay_work);
2e0fef85 3019 del_timer_sync(&phba->sli.mbox_tmo);
92d7f7b0 3020 del_timer_sync(&phba->fabric_block_timer);
9399627f 3021 del_timer_sync(&phba->eratt_poll);
3772a991 3022 del_timer_sync(&phba->hb_tmofunc);
1151e3ec
JS
3023 if (phba->sli_rev == LPFC_SLI_REV4) {
3024 del_timer_sync(&phba->rrq_tmr);
3025 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
3026 }
a22d73b6 3027 phba->hba_flag &= ~(HBA_HBEAT_INP | HBA_HBEAT_TMO);
3772a991
JS
3028
3029 switch (phba->pci_dev_grp) {
3030 case LPFC_PCI_DEV_LP:
3031 /* Stop any LightPulse device specific driver timers */
3032 del_timer_sync(&phba->fcp_poll_timer);
3033 break;
3034 case LPFC_PCI_DEV_OC:
cc0e5f1c 3035 /* Stop any OneConnect device specific driver timers */
ecfd03c6 3036 lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
3772a991
JS
3037 break;
3038 default:
372c187b 3039 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
3040 "0297 Invalid device group (x%x)\n",
3041 phba->pci_dev_grp);
3042 break;
3043 }
2e0fef85 3044 return;
dea3101e 3045}
3046
e59058c4 3047/**
3621a710 3048 * lpfc_block_mgmt_io - Mark a HBA's management interface as blocked
e59058c4 3049 * @phba: pointer to lpfc hba data structure.
fe614acd 3050 * @mbx_action: flag for mailbox no wait action.
e59058c4
JS
3051 *
3052 * This routine marks a HBA's management interface as blocked. Once the HBA's
3053 * management interface is marked as blocked, all the user space access to
3054 * the HBA, whether they are from sysfs interface or libdfc interface will
3055 * all be blocked. The HBA is set to block the management interface when the
3056 * driver prepares the HBA interface for online or offline.
3057 **/
a6ababd2 3058static void
618a5230 3059lpfc_block_mgmt_io(struct lpfc_hba *phba, int mbx_action)
a6ababd2
AB
3060{
3061 unsigned long iflag;
6e7288d9
JS
3062 uint8_t actcmd = MBX_HEARTBEAT;
3063 unsigned long timeout;
3064
a6ababd2
AB
3065 spin_lock_irqsave(&phba->hbalock, iflag);
3066 phba->sli.sli_flag |= LPFC_BLOCK_MGMT_IO;
618a5230
JS
3067 spin_unlock_irqrestore(&phba->hbalock, iflag);
3068 if (mbx_action == LPFC_MBX_NO_WAIT)
3069 return;
3070 timeout = msecs_to_jiffies(LPFC_MBOX_TMO * 1000) + jiffies;
3071 spin_lock_irqsave(&phba->hbalock, iflag);
a183a15f 3072 if (phba->sli.mbox_active) {
6e7288d9 3073 actcmd = phba->sli.mbox_active->u.mb.mbxCommand;
a183a15f
JS
3074 /* Determine how long we might wait for the active mailbox
3075 * command to be gracefully completed by firmware.
3076 */
3077 timeout = msecs_to_jiffies(lpfc_mbox_tmo_val(phba,
3078 phba->sli.mbox_active) * 1000) + jiffies;
3079 }
a6ababd2 3080 spin_unlock_irqrestore(&phba->hbalock, iflag);
a183a15f 3081
6e7288d9
JS
3082 /* Wait for the outstnading mailbox command to complete */
3083 while (phba->sli.mbox_active) {
3084 /* Check active mailbox complete status every 2ms */
3085 msleep(2);
3086 if (time_after(jiffies, timeout)) {
372c187b
DK
3087 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3088 "2813 Mgmt IO is Blocked %x "
3089 "- mbox cmd %x still active\n",
3090 phba->sli.sli_flag, actcmd);
6e7288d9
JS
3091 break;
3092 }
3093 }
a6ababd2
AB
3094}
3095
6b5151fd
JS
3096/**
3097 * lpfc_sli4_node_prep - Assign RPIs for active nodes.
3098 * @phba: pointer to lpfc hba data structure.
3099 *
3100 * Allocate RPIs for all active remote nodes. This is needed whenever
3101 * an SLI4 adapter is reset and the driver is not unloading. Its purpose
3102 * is to fixup the temporary rpi assignments.
3103 **/
3104void
3105lpfc_sli4_node_prep(struct lpfc_hba *phba)
3106{
3107 struct lpfc_nodelist *ndlp, *next_ndlp;
3108 struct lpfc_vport **vports;
9d3d340d 3109 int i, rpi;
6b5151fd
JS
3110
3111 if (phba->sli_rev != LPFC_SLI_REV4)
3112 return;
3113
3114 vports = lpfc_create_vport_work_array(phba);
9d3d340d
JS
3115 if (vports == NULL)
3116 return;
6b5151fd 3117
9d3d340d
JS
3118 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
3119 if (vports[i]->load_flag & FC_UNLOADING)
3120 continue;
3121
3122 list_for_each_entry_safe(ndlp, next_ndlp,
3123 &vports[i]->fc_nodes,
3124 nlp_listp) {
9d3d340d
JS
3125 rpi = lpfc_sli4_alloc_rpi(phba);
3126 if (rpi == LPFC_RPI_ALLOC_ERROR) {
307e3380 3127 /* TODO print log? */
9d3d340d 3128 continue;
6b5151fd 3129 }
9d3d340d 3130 ndlp->nlp_rpi = rpi;
0f154226
JS
3131 lpfc_printf_vlog(ndlp->vport, KERN_INFO,
3132 LOG_NODE | LOG_DISCOVERY,
3133 "0009 Assign RPI x%x to ndlp x%px "
307e3380 3134 "DID:x%06x flg:x%x\n",
0f154226 3135 ndlp->nlp_rpi, ndlp, ndlp->nlp_DID,
307e3380 3136 ndlp->nlp_flag);
6b5151fd
JS
3137 }
3138 }
3139 lpfc_destroy_vport_work_array(phba, vports);
3140}
3141
c490850a
JS
3142/**
3143 * lpfc_create_expedite_pool - create expedite pool
3144 * @phba: pointer to lpfc hba data structure.
3145 *
3146 * This routine moves a batch of XRIs from lpfc_io_buf_list_put of HWQ 0
3147 * to expedite pool. Mark them as expedite.
3148 **/
3999df75 3149static void lpfc_create_expedite_pool(struct lpfc_hba *phba)
c490850a
JS
3150{
3151 struct lpfc_sli4_hdw_queue *qp;
3152 struct lpfc_io_buf *lpfc_ncmd;
3153 struct lpfc_io_buf *lpfc_ncmd_next;
3154 struct lpfc_epd_pool *epd_pool;
3155 unsigned long iflag;
3156
3157 epd_pool = &phba->epd_pool;
3158 qp = &phba->sli4_hba.hdwq[0];
3159
3160 spin_lock_init(&epd_pool->lock);
3161 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3162 spin_lock(&epd_pool->lock);
3163 INIT_LIST_HEAD(&epd_pool->list);
3164 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3165 &qp->lpfc_io_buf_list_put, list) {
3166 list_move_tail(&lpfc_ncmd->list, &epd_pool->list);
3167 lpfc_ncmd->expedite = true;
3168 qp->put_io_bufs--;
3169 epd_pool->count++;
3170 if (epd_pool->count >= XRI_BATCH)
3171 break;
3172 }
3173 spin_unlock(&epd_pool->lock);
3174 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3175}
3176
3177/**
3178 * lpfc_destroy_expedite_pool - destroy expedite pool
3179 * @phba: pointer to lpfc hba data structure.
3180 *
3181 * This routine returns XRIs from expedite pool to lpfc_io_buf_list_put
3182 * of HWQ 0. Clear the mark.
3183 **/
3999df75 3184static void lpfc_destroy_expedite_pool(struct lpfc_hba *phba)
c490850a
JS
3185{
3186 struct lpfc_sli4_hdw_queue *qp;
3187 struct lpfc_io_buf *lpfc_ncmd;
3188 struct lpfc_io_buf *lpfc_ncmd_next;
3189 struct lpfc_epd_pool *epd_pool;
3190 unsigned long iflag;
3191
3192 epd_pool = &phba->epd_pool;
3193 qp = &phba->sli4_hba.hdwq[0];
3194
3195 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3196 spin_lock(&epd_pool->lock);
3197 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3198 &epd_pool->list, list) {
3199 list_move_tail(&lpfc_ncmd->list,
3200 &qp->lpfc_io_buf_list_put);
3201 lpfc_ncmd->flags = false;
3202 qp->put_io_bufs++;
3203 epd_pool->count--;
3204 }
3205 spin_unlock(&epd_pool->lock);
3206 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3207}
3208
3209/**
3210 * lpfc_create_multixri_pools - create multi-XRI pools
3211 * @phba: pointer to lpfc hba data structure.
3212 *
3213 * This routine initialize public, private per HWQ. Then, move XRIs from
3214 * lpfc_io_buf_list_put to public pool. High and low watermark are also
3215 * Initialized.
3216 **/
3217void lpfc_create_multixri_pools(struct lpfc_hba *phba)
3218{
3219 u32 i, j;
3220 u32 hwq_count;
3221 u32 count_per_hwq;
3222 struct lpfc_io_buf *lpfc_ncmd;
3223 struct lpfc_io_buf *lpfc_ncmd_next;
3224 unsigned long iflag;
3225 struct lpfc_sli4_hdw_queue *qp;
3226 struct lpfc_multixri_pool *multixri_pool;
3227 struct lpfc_pbl_pool *pbl_pool;
3228 struct lpfc_pvt_pool *pvt_pool;
3229
3230 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3231 "1234 num_hdw_queue=%d num_present_cpu=%d common_xri_cnt=%d\n",
3232 phba->cfg_hdw_queue, phba->sli4_hba.num_present_cpu,
3233 phba->sli4_hba.io_xri_cnt);
3234
3235 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3236 lpfc_create_expedite_pool(phba);
3237
3238 hwq_count = phba->cfg_hdw_queue;
3239 count_per_hwq = phba->sli4_hba.io_xri_cnt / hwq_count;
3240
3241 for (i = 0; i < hwq_count; i++) {
3242 multixri_pool = kzalloc(sizeof(*multixri_pool), GFP_KERNEL);
3243
3244 if (!multixri_pool) {
3245 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3246 "1238 Failed to allocate memory for "
3247 "multixri_pool\n");
3248
3249 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3250 lpfc_destroy_expedite_pool(phba);
3251
3252 j = 0;
3253 while (j < i) {
3254 qp = &phba->sli4_hba.hdwq[j];
3255 kfree(qp->p_multixri_pool);
3256 j++;
3257 }
3258 phba->cfg_xri_rebalancing = 0;
3259 return;
3260 }
3261
3262 qp = &phba->sli4_hba.hdwq[i];
3263 qp->p_multixri_pool = multixri_pool;
3264
3265 multixri_pool->xri_limit = count_per_hwq;
3266 multixri_pool->rrb_next_hwqid = i;
3267
3268 /* Deal with public free xri pool */
3269 pbl_pool = &multixri_pool->pbl_pool;
3270 spin_lock_init(&pbl_pool->lock);
3271 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3272 spin_lock(&pbl_pool->lock);
3273 INIT_LIST_HEAD(&pbl_pool->list);
3274 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3275 &qp->lpfc_io_buf_list_put, list) {
3276 list_move_tail(&lpfc_ncmd->list, &pbl_pool->list);
3277 qp->put_io_bufs--;
3278 pbl_pool->count++;
3279 }
3280 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3281 "1235 Moved %d buffers from PUT list over to pbl_pool[%d]\n",
3282 pbl_pool->count, i);
3283 spin_unlock(&pbl_pool->lock);
3284 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3285
3286 /* Deal with private free xri pool */
3287 pvt_pool = &multixri_pool->pvt_pool;
3288 pvt_pool->high_watermark = multixri_pool->xri_limit / 2;
3289 pvt_pool->low_watermark = XRI_BATCH;
3290 spin_lock_init(&pvt_pool->lock);
3291 spin_lock_irqsave(&pvt_pool->lock, iflag);
3292 INIT_LIST_HEAD(&pvt_pool->list);
3293 pvt_pool->count = 0;
3294 spin_unlock_irqrestore(&pvt_pool->lock, iflag);
3295 }
3296}
3297
3298/**
3299 * lpfc_destroy_multixri_pools - destroy multi-XRI pools
3300 * @phba: pointer to lpfc hba data structure.
3301 *
3302 * This routine returns XRIs from public/private to lpfc_io_buf_list_put.
3303 **/
3999df75 3304static void lpfc_destroy_multixri_pools(struct lpfc_hba *phba)
c490850a
JS
3305{
3306 u32 i;
3307 u32 hwq_count;
3308 struct lpfc_io_buf *lpfc_ncmd;
3309 struct lpfc_io_buf *lpfc_ncmd_next;
3310 unsigned long iflag;
3311 struct lpfc_sli4_hdw_queue *qp;
3312 struct lpfc_multixri_pool *multixri_pool;
3313 struct lpfc_pbl_pool *pbl_pool;
3314 struct lpfc_pvt_pool *pvt_pool;
3315
3316 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3317 lpfc_destroy_expedite_pool(phba);
3318
c00f62e6
JS
3319 if (!(phba->pport->load_flag & FC_UNLOADING))
3320 lpfc_sli_flush_io_rings(phba);
c66a9197 3321
c490850a
JS
3322 hwq_count = phba->cfg_hdw_queue;
3323
3324 for (i = 0; i < hwq_count; i++) {
3325 qp = &phba->sli4_hba.hdwq[i];
3326 multixri_pool = qp->p_multixri_pool;
3327 if (!multixri_pool)
3328 continue;
3329
3330 qp->p_multixri_pool = NULL;
3331
3332 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3333
3334 /* Deal with public free xri pool */
3335 pbl_pool = &multixri_pool->pbl_pool;
3336 spin_lock(&pbl_pool->lock);
3337
3338 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3339 "1236 Moving %d buffers from pbl_pool[%d] TO PUT list\n",
3340 pbl_pool->count, i);
3341
3342 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3343 &pbl_pool->list, list) {
3344 list_move_tail(&lpfc_ncmd->list,
3345 &qp->lpfc_io_buf_list_put);
3346 qp->put_io_bufs++;
3347 pbl_pool->count--;
3348 }
3349
3350 INIT_LIST_HEAD(&pbl_pool->list);
3351 pbl_pool->count = 0;
3352
3353 spin_unlock(&pbl_pool->lock);
3354
3355 /* Deal with private free xri pool */
3356 pvt_pool = &multixri_pool->pvt_pool;
3357 spin_lock(&pvt_pool->lock);
3358
3359 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3360 "1237 Moving %d buffers from pvt_pool[%d] TO PUT list\n",
3361 pvt_pool->count, i);
3362
3363 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3364 &pvt_pool->list, list) {
3365 list_move_tail(&lpfc_ncmd->list,
3366 &qp->lpfc_io_buf_list_put);
3367 qp->put_io_bufs++;
3368 pvt_pool->count--;
3369 }
3370
3371 INIT_LIST_HEAD(&pvt_pool->list);
3372 pvt_pool->count = 0;
3373
3374 spin_unlock(&pvt_pool->lock);
3375 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3376
3377 kfree(multixri_pool);
3378 }
3379}
3380
e59058c4 3381/**
3621a710 3382 * lpfc_online - Initialize and bring a HBA online
e59058c4
JS
3383 * @phba: pointer to lpfc hba data structure.
3384 *
3385 * This routine initializes the HBA and brings a HBA online. During this
3386 * process, the management interface is blocked to prevent user space access
3387 * to the HBA interfering with the driver initialization.
3388 *
3389 * Return codes
3390 * 0 - successful
3391 * 1 - failed
3392 **/
dea3101e 3393int
2e0fef85 3394lpfc_online(struct lpfc_hba *phba)
dea3101e 3395{
372bd282 3396 struct lpfc_vport *vport;
549e55cd 3397 struct lpfc_vport **vports;
a145fda3 3398 int i, error = 0;
16a3a208 3399 bool vpis_cleared = false;
2e0fef85 3400
dea3101e 3401 if (!phba)
3402 return 0;
372bd282 3403 vport = phba->pport;
dea3101e 3404
2e0fef85 3405 if (!(vport->fc_flag & FC_OFFLINE_MODE))
dea3101e 3406 return 0;
3407
ed957684 3408 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
e8b62011 3409 "0458 Bring Adapter online\n");
dea3101e 3410
618a5230 3411 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
46fa311e 3412
da0436e9
JS
3413 if (phba->sli_rev == LPFC_SLI_REV4) {
3414 if (lpfc_sli4_hba_setup(phba)) { /* Initialize SLI4 HBA */
3415 lpfc_unblock_mgmt_io(phba);
3416 return 1;
3417 }
16a3a208
JS
3418 spin_lock_irq(&phba->hbalock);
3419 if (!phba->sli4_hba.max_cfg_param.vpi_used)
3420 vpis_cleared = true;
3421 spin_unlock_irq(&phba->hbalock);
a145fda3
DK
3422
3423 /* Reestablish the local initiator port.
3424 * The offline process destroyed the previous lport.
3425 */
3426 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME &&
3427 !phba->nvmet_support) {
3428 error = lpfc_nvme_create_localport(phba->pport);
3429 if (error)
372c187b 3430 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
a145fda3
DK
3431 "6132 NVME restore reg failed "
3432 "on nvmei error x%x\n", error);
3433 }
da0436e9 3434 } else {
895427bd 3435 lpfc_sli_queue_init(phba);
da0436e9
JS
3436 if (lpfc_sli_hba_setup(phba)) { /* Initialize SLI2/SLI3 HBA */
3437 lpfc_unblock_mgmt_io(phba);
3438 return 1;
3439 }
46fa311e 3440 }
dea3101e 3441
549e55cd 3442 vports = lpfc_create_vport_work_array(phba);
aeb6641f 3443 if (vports != NULL) {
da0436e9 3444 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
549e55cd
JS
3445 struct Scsi_Host *shost;
3446 shost = lpfc_shost_from_vport(vports[i]);
3447 spin_lock_irq(shost->host_lock);
3448 vports[i]->fc_flag &= ~FC_OFFLINE_MODE;
3449 if (phba->sli3_options & LPFC_SLI3_NPIV_ENABLED)
3450 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
16a3a208 3451 if (phba->sli_rev == LPFC_SLI_REV4) {
1c6834a7 3452 vports[i]->fc_flag |= FC_VPORT_NEEDS_INIT_VPI;
16a3a208
JS
3453 if ((vpis_cleared) &&
3454 (vports[i]->port_type !=
3455 LPFC_PHYSICAL_PORT))
3456 vports[i]->vpi = 0;
3457 }
549e55cd
JS
3458 spin_unlock_irq(shost->host_lock);
3459 }
aeb6641f
AB
3460 }
3461 lpfc_destroy_vport_work_array(phba, vports);
dea3101e 3462
c490850a
JS
3463 if (phba->cfg_xri_rebalancing)
3464 lpfc_create_multixri_pools(phba);
3465
93a4d6f4
JS
3466 lpfc_cpuhp_add(phba);
3467
46fa311e 3468 lpfc_unblock_mgmt_io(phba);
dea3101e 3469 return 0;
3470}
3471
e59058c4 3472/**
3621a710 3473 * lpfc_unblock_mgmt_io - Mark a HBA's management interface to be not blocked
e59058c4
JS
3474 * @phba: pointer to lpfc hba data structure.
3475 *
3476 * This routine marks a HBA's management interface as not blocked. Once the
3477 * HBA's management interface is marked as not blocked, all the user space
3478 * access to the HBA, whether they are from sysfs interface or libdfc
3479 * interface will be allowed. The HBA is set to block the management interface
3480 * when the driver prepares the HBA interface for online or offline and then
3481 * set to unblock the management interface afterwards.
3482 **/
46fa311e
JS
3483void
3484lpfc_unblock_mgmt_io(struct lpfc_hba * phba)
3485{
3486 unsigned long iflag;
3487
2e0fef85
JS
3488 spin_lock_irqsave(&phba->hbalock, iflag);
3489 phba->sli.sli_flag &= ~LPFC_BLOCK_MGMT_IO;
3490 spin_unlock_irqrestore(&phba->hbalock, iflag);
46fa311e
JS
3491}
3492
e59058c4 3493/**
3621a710 3494 * lpfc_offline_prep - Prepare a HBA to be brought offline
e59058c4 3495 * @phba: pointer to lpfc hba data structure.
fe614acd 3496 * @mbx_action: flag for mailbox shutdown action.
e59058c4
JS
3497 *
3498 * This routine is invoked to prepare a HBA to be brought offline. It performs
3499 * unregistration login to all the nodes on all vports and flushes the mailbox
3500 * queue to make it ready to be brought offline.
3501 **/
46fa311e 3502void
618a5230 3503lpfc_offline_prep(struct lpfc_hba *phba, int mbx_action)
46fa311e 3504{
2e0fef85 3505 struct lpfc_vport *vport = phba->pport;
46fa311e 3506 struct lpfc_nodelist *ndlp, *next_ndlp;
87af33fe 3507 struct lpfc_vport **vports;
72100cc4 3508 struct Scsi_Host *shost;
87af33fe 3509 int i;
dea3101e 3510
2e0fef85 3511 if (vport->fc_flag & FC_OFFLINE_MODE)
46fa311e 3512 return;
dea3101e 3513
618a5230 3514 lpfc_block_mgmt_io(phba, mbx_action);
dea3101e 3515
3516 lpfc_linkdown(phba);
3517
87af33fe
JS
3518 /* Issue an unreg_login to all nodes on all vports */
3519 vports = lpfc_create_vport_work_array(phba);
3520 if (vports != NULL) {
da0436e9 3521 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
a8adb832
JS
3522 if (vports[i]->load_flag & FC_UNLOADING)
3523 continue;
72100cc4
JS
3524 shost = lpfc_shost_from_vport(vports[i]);
3525 spin_lock_irq(shost->host_lock);
c868595d 3526 vports[i]->vpi_state &= ~LPFC_VPI_REGISTERED;
695a814e
JS
3527 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
3528 vports[i]->fc_flag &= ~FC_VFI_REGISTERED;
72100cc4 3529 spin_unlock_irq(shost->host_lock);
695a814e 3530
87af33fe
JS
3531 shost = lpfc_shost_from_vport(vports[i]);
3532 list_for_each_entry_safe(ndlp, next_ndlp,
3533 &vports[i]->fc_nodes,
3534 nlp_listp) {
307e3380 3535 if (ndlp->nlp_state == NLP_STE_UNUSED_NODE) {
0f154226
JS
3536 /* Driver must assume RPI is invalid for
3537 * any unused or inactive node.
3538 */
3539 ndlp->nlp_rpi = LPFC_RPI_ALLOC_ERROR;
87af33fe 3540 continue;
0f154226
JS
3541 }
3542
c6adba15 3543 spin_lock_irq(&ndlp->lock);
87af33fe 3544 ndlp->nlp_flag &= ~NLP_NPR_ADISC;
c6adba15 3545 spin_unlock_irq(&ndlp->lock);
6b5151fd
JS
3546 /*
3547 * Whenever an SLI4 port goes offline, free the
401ee0c1
JS
3548 * RPI. Get a new RPI when the adapter port
3549 * comes back online.
6b5151fd 3550 */
be6bb941 3551 if (phba->sli_rev == LPFC_SLI_REV4) {
e9b11083 3552 lpfc_printf_vlog(vports[i], KERN_INFO,
0f154226
JS
3553 LOG_NODE | LOG_DISCOVERY,
3554 "0011 Free RPI x%x on "
e9b11083 3555 "ndlp: %p did x%x\n",
0f154226 3556 ndlp->nlp_rpi, ndlp,
307e3380 3557 ndlp->nlp_DID);
6b5151fd 3558 lpfc_sli4_free_rpi(phba, ndlp->nlp_rpi);
0f154226 3559 ndlp->nlp_rpi = LPFC_RPI_ALLOC_ERROR;
be6bb941 3560 }
87af33fe 3561 lpfc_unreg_rpi(vports[i], ndlp);
307e3380
JS
3562
3563 if (ndlp->nlp_type & NLP_FABRIC) {
3564 lpfc_disc_state_machine(vports[i], ndlp,
3565 NULL, NLP_EVT_DEVICE_RECOVERY);
e9b11083
JS
3566
3567 /* Don't remove the node unless the
3568 * has been unregistered with the
3569 * transport. If so, let dev_loss
3570 * take care of the node.
3571 */
3572 if (!(ndlp->fc4_xpt_flags &
3573 (NVME_XPT_REGD | SCSI_XPT_REGD)))
3574 lpfc_disc_state_machine
3575 (vports[i], ndlp,
3576 NULL,
3577 NLP_EVT_DEVICE_RM);
307e3380 3578 }
87af33fe
JS
3579 }
3580 }
3581 }
09372820 3582 lpfc_destroy_vport_work_array(phba, vports);
dea3101e 3583
618a5230 3584 lpfc_sli_mbox_sys_shutdown(phba, mbx_action);
f485c18d
DK
3585
3586 if (phba->wq)
3587 flush_workqueue(phba->wq);
46fa311e
JS
3588}
3589
e59058c4 3590/**
3621a710 3591 * lpfc_offline - Bring a HBA offline
e59058c4
JS
3592 * @phba: pointer to lpfc hba data structure.
3593 *
3594 * This routine actually brings a HBA offline. It stops all the timers
3595 * associated with the HBA, brings down the SLI layer, and eventually
3596 * marks the HBA as in offline state for the upper layer protocol.
3597 **/
46fa311e 3598void
2e0fef85 3599lpfc_offline(struct lpfc_hba *phba)
46fa311e 3600{
549e55cd
JS
3601 struct Scsi_Host *shost;
3602 struct lpfc_vport **vports;
3603 int i;
46fa311e 3604
549e55cd 3605 if (phba->pport->fc_flag & FC_OFFLINE_MODE)
46fa311e 3606 return;
688a8863 3607
da0436e9
JS
3608 /* stop port and all timers associated with this hba */
3609 lpfc_stop_port(phba);
4b40d02b
DK
3610
3611 /* Tear down the local and target port registrations. The
3612 * nvme transports need to cleanup.
3613 */
3614 lpfc_nvmet_destroy_targetport(phba);
3615 lpfc_nvme_destroy_localport(phba->pport);
3616
51ef4c26
JS
3617 vports = lpfc_create_vport_work_array(phba);
3618 if (vports != NULL)
da0436e9 3619 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
51ef4c26 3620 lpfc_stop_vport_timers(vports[i]);
09372820 3621 lpfc_destroy_vport_work_array(phba, vports);
92d7f7b0 3622 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
e8b62011 3623 "0460 Bring Adapter offline\n");
dea3101e 3624 /* Bring down the SLI Layer and cleanup. The HBA is offline
3625 now. */
3626 lpfc_sli_hba_down(phba);
92d7f7b0 3627 spin_lock_irq(&phba->hbalock);
7054a606 3628 phba->work_ha = 0;
92d7f7b0 3629 spin_unlock_irq(&phba->hbalock);
549e55cd
JS
3630 vports = lpfc_create_vport_work_array(phba);
3631 if (vports != NULL)
da0436e9 3632 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
549e55cd 3633 shost = lpfc_shost_from_vport(vports[i]);
549e55cd
JS
3634 spin_lock_irq(shost->host_lock);
3635 vports[i]->work_port_events = 0;
3636 vports[i]->fc_flag |= FC_OFFLINE_MODE;
3637 spin_unlock_irq(shost->host_lock);
3638 }
09372820 3639 lpfc_destroy_vport_work_array(phba, vports);
f0871ab6
JS
3640 /* If OFFLINE flag is clear (i.e. unloading), cpuhp removal is handled
3641 * in hba_unset
3642 */
3643 if (phba->pport->fc_flag & FC_OFFLINE_MODE)
3644 __lpfc_cpuhp_remove(phba);
c490850a
JS
3645
3646 if (phba->cfg_xri_rebalancing)
3647 lpfc_destroy_multixri_pools(phba);
dea3101e 3648}
3649
e59058c4 3650/**
3621a710 3651 * lpfc_scsi_free - Free all the SCSI buffers and IOCBs from driver lists
e59058c4
JS
3652 * @phba: pointer to lpfc hba data structure.
3653 *
3654 * This routine is to free all the SCSI buffers and IOCBs from the driver
3655 * list back to kernel. It is called from lpfc_pci_remove_one to free
3656 * the internal resources before the device is removed from the system.
e59058c4 3657 **/
8a9d2e80 3658static void
2e0fef85 3659lpfc_scsi_free(struct lpfc_hba *phba)
dea3101e 3660{
c490850a 3661 struct lpfc_io_buf *sb, *sb_next;
dea3101e 3662
895427bd
JS
3663 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
3664 return;
3665
2e0fef85 3666 spin_lock_irq(&phba->hbalock);
a40fc5f0 3667
dea3101e 3668 /* Release all the lpfc_scsi_bufs maintained by this host. */
a40fc5f0
JS
3669
3670 spin_lock(&phba->scsi_buf_list_put_lock);
3671 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_put,
3672 list) {
dea3101e 3673 list_del(&sb->list);
771db5c0 3674 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
92d7f7b0 3675 sb->dma_handle);
dea3101e 3676 kfree(sb);
3677 phba->total_scsi_bufs--;
3678 }
a40fc5f0
JS
3679 spin_unlock(&phba->scsi_buf_list_put_lock);
3680
3681 spin_lock(&phba->scsi_buf_list_get_lock);
3682 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_get,
3683 list) {
dea3101e 3684 list_del(&sb->list);
771db5c0 3685 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
92d7f7b0 3686 sb->dma_handle);
dea3101e 3687 kfree(sb);
3688 phba->total_scsi_bufs--;
3689 }
a40fc5f0 3690 spin_unlock(&phba->scsi_buf_list_get_lock);
2e0fef85 3691 spin_unlock_irq(&phba->hbalock);
8a9d2e80 3692}
0794d601 3693
895427bd 3694/**
5e5b511d 3695 * lpfc_io_free - Free all the IO buffers and IOCBs from driver lists
895427bd
JS
3696 * @phba: pointer to lpfc hba data structure.
3697 *
0794d601 3698 * This routine is to free all the IO buffers and IOCBs from the driver
895427bd
JS
3699 * list back to kernel. It is called from lpfc_pci_remove_one to free
3700 * the internal resources before the device is removed from the system.
3701 **/
c490850a 3702void
5e5b511d 3703lpfc_io_free(struct lpfc_hba *phba)
895427bd 3704{
c490850a 3705 struct lpfc_io_buf *lpfc_ncmd, *lpfc_ncmd_next;
5e5b511d
JS
3706 struct lpfc_sli4_hdw_queue *qp;
3707 int idx;
895427bd 3708
5e5b511d
JS
3709 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3710 qp = &phba->sli4_hba.hdwq[idx];
3711 /* Release all the lpfc_nvme_bufs maintained by this host. */
3712 spin_lock(&qp->io_buf_list_put_lock);
3713 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3714 &qp->lpfc_io_buf_list_put,
3715 list) {
3716 list_del(&lpfc_ncmd->list);
3717 qp->put_io_bufs--;
3718 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3719 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
d79c9e9d
JS
3720 if (phba->cfg_xpsgl && !phba->nvmet_support)
3721 lpfc_put_sgl_per_hdwq(phba, lpfc_ncmd);
3722 lpfc_put_cmd_rsp_buf_per_hdwq(phba, lpfc_ncmd);
5e5b511d
JS
3723 kfree(lpfc_ncmd);
3724 qp->total_io_bufs--;
3725 }
3726 spin_unlock(&qp->io_buf_list_put_lock);
3727
3728 spin_lock(&qp->io_buf_list_get_lock);
3729 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3730 &qp->lpfc_io_buf_list_get,
3731 list) {
3732 list_del(&lpfc_ncmd->list);
3733 qp->get_io_bufs--;
3734 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3735 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
d79c9e9d
JS
3736 if (phba->cfg_xpsgl && !phba->nvmet_support)
3737 lpfc_put_sgl_per_hdwq(phba, lpfc_ncmd);
3738 lpfc_put_cmd_rsp_buf_per_hdwq(phba, lpfc_ncmd);
5e5b511d
JS
3739 kfree(lpfc_ncmd);
3740 qp->total_io_bufs--;
3741 }
3742 spin_unlock(&qp->io_buf_list_get_lock);
895427bd 3743 }
895427bd 3744}
0794d601 3745
8a9d2e80 3746/**
895427bd 3747 * lpfc_sli4_els_sgl_update - update ELS xri-sgl sizing and mapping
8a9d2e80
JS
3748 * @phba: pointer to lpfc hba data structure.
3749 *
3750 * This routine first calculates the sizes of the current els and allocated
3751 * scsi sgl lists, and then goes through all sgls to updates the physical
3752 * XRIs assigned due to port function reset. During port initialization, the
3753 * current els and allocated scsi sgl lists are 0s.
3754 *
3755 * Return codes
3756 * 0 - successful (for now, it always returns 0)
3757 **/
3758int
895427bd 3759lpfc_sli4_els_sgl_update(struct lpfc_hba *phba)
8a9d2e80
JS
3760{
3761 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
895427bd 3762 uint16_t i, lxri, xri_cnt, els_xri_cnt;
8a9d2e80 3763 LIST_HEAD(els_sgl_list);
8a9d2e80
JS
3764 int rc;
3765
3766 /*
3767 * update on pci function's els xri-sgl list
3768 */
3769 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
895427bd 3770
8a9d2e80
JS
3771 if (els_xri_cnt > phba->sli4_hba.els_xri_cnt) {
3772 /* els xri-sgl expanded */
3773 xri_cnt = els_xri_cnt - phba->sli4_hba.els_xri_cnt;
3774 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3775 "3157 ELS xri-sgl count increased from "
3776 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3777 els_xri_cnt);
3778 /* allocate the additional els sgls */
3779 for (i = 0; i < xri_cnt; i++) {
3780 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3781 GFP_KERNEL);
3782 if (sglq_entry == NULL) {
372c187b
DK
3783 lpfc_printf_log(phba, KERN_ERR,
3784 LOG_TRACE_EVENT,
8a9d2e80
JS
3785 "2562 Failure to allocate an "
3786 "ELS sgl entry:%d\n", i);
3787 rc = -ENOMEM;
3788 goto out_free_mem;
3789 }
3790 sglq_entry->buff_type = GEN_BUFF_TYPE;
3791 sglq_entry->virt = lpfc_mbuf_alloc(phba, 0,
3792 &sglq_entry->phys);
3793 if (sglq_entry->virt == NULL) {
3794 kfree(sglq_entry);
372c187b
DK
3795 lpfc_printf_log(phba, KERN_ERR,
3796 LOG_TRACE_EVENT,
8a9d2e80
JS
3797 "2563 Failure to allocate an "
3798 "ELS mbuf:%d\n", i);
3799 rc = -ENOMEM;
3800 goto out_free_mem;
3801 }
3802 sglq_entry->sgl = sglq_entry->virt;
3803 memset(sglq_entry->sgl, 0, LPFC_BPL_SIZE);
3804 sglq_entry->state = SGL_FREED;
3805 list_add_tail(&sglq_entry->list, &els_sgl_list);
3806 }
38c20673 3807 spin_lock_irq(&phba->hbalock);
895427bd
JS
3808 spin_lock(&phba->sli4_hba.sgl_list_lock);
3809 list_splice_init(&els_sgl_list,
3810 &phba->sli4_hba.lpfc_els_sgl_list);
3811 spin_unlock(&phba->sli4_hba.sgl_list_lock);
38c20673 3812 spin_unlock_irq(&phba->hbalock);
8a9d2e80
JS
3813 } else if (els_xri_cnt < phba->sli4_hba.els_xri_cnt) {
3814 /* els xri-sgl shrinked */
3815 xri_cnt = phba->sli4_hba.els_xri_cnt - els_xri_cnt;
3816 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3817 "3158 ELS xri-sgl count decreased from "
3818 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3819 els_xri_cnt);
3820 spin_lock_irq(&phba->hbalock);
895427bd
JS
3821 spin_lock(&phba->sli4_hba.sgl_list_lock);
3822 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list,
3823 &els_sgl_list);
8a9d2e80
JS
3824 /* release extra els sgls from list */
3825 for (i = 0; i < xri_cnt; i++) {
3826 list_remove_head(&els_sgl_list,
3827 sglq_entry, struct lpfc_sglq, list);
3828 if (sglq_entry) {
895427bd
JS
3829 __lpfc_mbuf_free(phba, sglq_entry->virt,
3830 sglq_entry->phys);
8a9d2e80
JS
3831 kfree(sglq_entry);
3832 }
3833 }
895427bd
JS
3834 list_splice_init(&els_sgl_list,
3835 &phba->sli4_hba.lpfc_els_sgl_list);
3836 spin_unlock(&phba->sli4_hba.sgl_list_lock);
8a9d2e80
JS
3837 spin_unlock_irq(&phba->hbalock);
3838 } else
3839 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3840 "3163 ELS xri-sgl count unchanged: %d\n",
3841 els_xri_cnt);
3842 phba->sli4_hba.els_xri_cnt = els_xri_cnt;
3843
3844 /* update xris to els sgls on the list */
3845 sglq_entry = NULL;
3846 sglq_entry_next = NULL;
3847 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
895427bd 3848 &phba->sli4_hba.lpfc_els_sgl_list, list) {
8a9d2e80
JS
3849 lxri = lpfc_sli4_next_xritag(phba);
3850 if (lxri == NO_XRI) {
372c187b
DK
3851 lpfc_printf_log(phba, KERN_ERR,
3852 LOG_TRACE_EVENT,
8a9d2e80
JS
3853 "2400 Failed to allocate xri for "
3854 "ELS sgl\n");
3855 rc = -ENOMEM;
3856 goto out_free_mem;
3857 }
3858 sglq_entry->sli4_lxritag = lxri;
3859 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3860 }
895427bd
JS
3861 return 0;
3862
3863out_free_mem:
3864 lpfc_free_els_sgl_list(phba);
3865 return rc;
3866}
3867
f358dd0c
JS
3868/**
3869 * lpfc_sli4_nvmet_sgl_update - update xri-sgl sizing and mapping
3870 * @phba: pointer to lpfc hba data structure.
3871 *
3872 * This routine first calculates the sizes of the current els and allocated
3873 * scsi sgl lists, and then goes through all sgls to updates the physical
3874 * XRIs assigned due to port function reset. During port initialization, the
3875 * current els and allocated scsi sgl lists are 0s.
3876 *
3877 * Return codes
3878 * 0 - successful (for now, it always returns 0)
3879 **/
3880int
3881lpfc_sli4_nvmet_sgl_update(struct lpfc_hba *phba)
3882{
3883 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
3884 uint16_t i, lxri, xri_cnt, els_xri_cnt;
6c621a22 3885 uint16_t nvmet_xri_cnt;
f358dd0c
JS
3886 LIST_HEAD(nvmet_sgl_list);
3887 int rc;
3888
3889 /*
3890 * update on pci function's nvmet xri-sgl list
3891 */
3892 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
61f3d4bf 3893
6c621a22
JS
3894 /* For NVMET, ALL remaining XRIs are dedicated for IO processing */
3895 nvmet_xri_cnt = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
f358dd0c
JS
3896 if (nvmet_xri_cnt > phba->sli4_hba.nvmet_xri_cnt) {
3897 /* els xri-sgl expanded */
3898 xri_cnt = nvmet_xri_cnt - phba->sli4_hba.nvmet_xri_cnt;
3899 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3900 "6302 NVMET xri-sgl cnt grew from %d to %d\n",
3901 phba->sli4_hba.nvmet_xri_cnt, nvmet_xri_cnt);
3902 /* allocate the additional nvmet sgls */
3903 for (i = 0; i < xri_cnt; i++) {
3904 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3905 GFP_KERNEL);
3906 if (sglq_entry == NULL) {
372c187b
DK
3907 lpfc_printf_log(phba, KERN_ERR,
3908 LOG_TRACE_EVENT,
f358dd0c
JS
3909 "6303 Failure to allocate an "
3910 "NVMET sgl entry:%d\n", i);
3911 rc = -ENOMEM;
3912 goto out_free_mem;
3913 }
3914 sglq_entry->buff_type = NVMET_BUFF_TYPE;
3915 sglq_entry->virt = lpfc_nvmet_buf_alloc(phba, 0,
3916 &sglq_entry->phys);
3917 if (sglq_entry->virt == NULL) {
3918 kfree(sglq_entry);
372c187b
DK
3919 lpfc_printf_log(phba, KERN_ERR,
3920 LOG_TRACE_EVENT,
f358dd0c
JS
3921 "6304 Failure to allocate an "
3922 "NVMET buf:%d\n", i);
3923 rc = -ENOMEM;
3924 goto out_free_mem;
3925 }
3926 sglq_entry->sgl = sglq_entry->virt;
3927 memset(sglq_entry->sgl, 0,
3928 phba->cfg_sg_dma_buf_size);
3929 sglq_entry->state = SGL_FREED;
3930 list_add_tail(&sglq_entry->list, &nvmet_sgl_list);
3931 }
3932 spin_lock_irq(&phba->hbalock);
3933 spin_lock(&phba->sli4_hba.sgl_list_lock);
3934 list_splice_init(&nvmet_sgl_list,
3935 &phba->sli4_hba.lpfc_nvmet_sgl_list);
3936 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3937 spin_unlock_irq(&phba->hbalock);
3938 } else if (nvmet_xri_cnt < phba->sli4_hba.nvmet_xri_cnt) {
3939 /* nvmet xri-sgl shrunk */
3940 xri_cnt = phba->sli4_hba.nvmet_xri_cnt - nvmet_xri_cnt;
3941 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3942 "6305 NVMET xri-sgl count decreased from "
3943 "%d to %d\n", phba->sli4_hba.nvmet_xri_cnt,
3944 nvmet_xri_cnt);
3945 spin_lock_irq(&phba->hbalock);
3946 spin_lock(&phba->sli4_hba.sgl_list_lock);
3947 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list,
3948 &nvmet_sgl_list);
3949 /* release extra nvmet sgls from list */
3950 for (i = 0; i < xri_cnt; i++) {
3951 list_remove_head(&nvmet_sgl_list,
3952 sglq_entry, struct lpfc_sglq, list);
3953 if (sglq_entry) {
3954 lpfc_nvmet_buf_free(phba, sglq_entry->virt,
3955 sglq_entry->phys);
3956 kfree(sglq_entry);
3957 }
3958 }
3959 list_splice_init(&nvmet_sgl_list,
3960 &phba->sli4_hba.lpfc_nvmet_sgl_list);
3961 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3962 spin_unlock_irq(&phba->hbalock);
3963 } else
3964 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3965 "6306 NVMET xri-sgl count unchanged: %d\n",
3966 nvmet_xri_cnt);
3967 phba->sli4_hba.nvmet_xri_cnt = nvmet_xri_cnt;
3968
3969 /* update xris to nvmet sgls on the list */
3970 sglq_entry = NULL;
3971 sglq_entry_next = NULL;
3972 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
3973 &phba->sli4_hba.lpfc_nvmet_sgl_list, list) {
3974 lxri = lpfc_sli4_next_xritag(phba);
3975 if (lxri == NO_XRI) {
372c187b
DK
3976 lpfc_printf_log(phba, KERN_ERR,
3977 LOG_TRACE_EVENT,
f358dd0c
JS
3978 "6307 Failed to allocate xri for "
3979 "NVMET sgl\n");
3980 rc = -ENOMEM;
3981 goto out_free_mem;
3982 }
3983 sglq_entry->sli4_lxritag = lxri;
3984 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3985 }
3986 return 0;
3987
3988out_free_mem:
3989 lpfc_free_nvmet_sgl_list(phba);
3990 return rc;
3991}
3992
5e5b511d
JS
3993int
3994lpfc_io_buf_flush(struct lpfc_hba *phba, struct list_head *cbuf)
3995{
3996 LIST_HEAD(blist);
3997 struct lpfc_sli4_hdw_queue *qp;
c490850a
JS
3998 struct lpfc_io_buf *lpfc_cmd;
3999 struct lpfc_io_buf *iobufp, *prev_iobufp;
5e5b511d
JS
4000 int idx, cnt, xri, inserted;
4001
4002 cnt = 0;
4003 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
4004 qp = &phba->sli4_hba.hdwq[idx];
4005 spin_lock_irq(&qp->io_buf_list_get_lock);
4006 spin_lock(&qp->io_buf_list_put_lock);
4007
4008 /* Take everything off the get and put lists */
4009 list_splice_init(&qp->lpfc_io_buf_list_get, &blist);
4010 list_splice(&qp->lpfc_io_buf_list_put, &blist);
4011 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_get);
4012 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_put);
4013 cnt += qp->get_io_bufs + qp->put_io_bufs;
4014 qp->get_io_bufs = 0;
4015 qp->put_io_bufs = 0;
4016 qp->total_io_bufs = 0;
4017 spin_unlock(&qp->io_buf_list_put_lock);
4018 spin_unlock_irq(&qp->io_buf_list_get_lock);
4019 }
4020
4021 /*
4022 * Take IO buffers off blist and put on cbuf sorted by XRI.
4023 * This is because POST_SGL takes a sequential range of XRIs
4024 * to post to the firmware.
4025 */
4026 for (idx = 0; idx < cnt; idx++) {
c490850a 4027 list_remove_head(&blist, lpfc_cmd, struct lpfc_io_buf, list);
5e5b511d
JS
4028 if (!lpfc_cmd)
4029 return cnt;
4030 if (idx == 0) {
4031 list_add_tail(&lpfc_cmd->list, cbuf);
4032 continue;
4033 }
4034 xri = lpfc_cmd->cur_iocbq.sli4_xritag;
4035 inserted = 0;
4036 prev_iobufp = NULL;
4037 list_for_each_entry(iobufp, cbuf, list) {
4038 if (xri < iobufp->cur_iocbq.sli4_xritag) {
4039 if (prev_iobufp)
4040 list_add(&lpfc_cmd->list,
4041 &prev_iobufp->list);
4042 else
4043 list_add(&lpfc_cmd->list, cbuf);
4044 inserted = 1;
4045 break;
4046 }
4047 prev_iobufp = iobufp;
4048 }
4049 if (!inserted)
4050 list_add_tail(&lpfc_cmd->list, cbuf);
4051 }
4052 return cnt;
4053}
4054
4055int
4056lpfc_io_buf_replenish(struct lpfc_hba *phba, struct list_head *cbuf)
4057{
4058 struct lpfc_sli4_hdw_queue *qp;
c490850a 4059 struct lpfc_io_buf *lpfc_cmd;
5e5b511d
JS
4060 int idx, cnt;
4061
4062 qp = phba->sli4_hba.hdwq;
4063 cnt = 0;
4064 while (!list_empty(cbuf)) {
4065 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
4066 list_remove_head(cbuf, lpfc_cmd,
c490850a 4067 struct lpfc_io_buf, list);
5e5b511d
JS
4068 if (!lpfc_cmd)
4069 return cnt;
4070 cnt++;
4071 qp = &phba->sli4_hba.hdwq[idx];
1fbf9742
JS
4072 lpfc_cmd->hdwq_no = idx;
4073 lpfc_cmd->hdwq = qp;
5e5b511d
JS
4074 lpfc_cmd->cur_iocbq.wqe_cmpl = NULL;
4075 lpfc_cmd->cur_iocbq.iocb_cmpl = NULL;
4076 spin_lock(&qp->io_buf_list_put_lock);
4077 list_add_tail(&lpfc_cmd->list,
4078 &qp->lpfc_io_buf_list_put);
4079 qp->put_io_bufs++;
4080 qp->total_io_bufs++;
4081 spin_unlock(&qp->io_buf_list_put_lock);
4082 }
4083 }
4084 return cnt;
4085}
4086
895427bd 4087/**
5e5b511d 4088 * lpfc_sli4_io_sgl_update - update xri-sgl sizing and mapping
895427bd
JS
4089 * @phba: pointer to lpfc hba data structure.
4090 *
4091 * This routine first calculates the sizes of the current els and allocated
4092 * scsi sgl lists, and then goes through all sgls to updates the physical
4093 * XRIs assigned due to port function reset. During port initialization, the
4094 * current els and allocated scsi sgl lists are 0s.
4095 *
4096 * Return codes
4097 * 0 - successful (for now, it always returns 0)
4098 **/
4099int
5e5b511d 4100lpfc_sli4_io_sgl_update(struct lpfc_hba *phba)
895427bd 4101{
c490850a 4102 struct lpfc_io_buf *lpfc_ncmd = NULL, *lpfc_ncmd_next = NULL;
0794d601 4103 uint16_t i, lxri, els_xri_cnt;
5e5b511d
JS
4104 uint16_t io_xri_cnt, io_xri_max;
4105 LIST_HEAD(io_sgl_list);
0794d601 4106 int rc, cnt;
8a9d2e80 4107
895427bd 4108 /*
0794d601 4109 * update on pci function's allocated nvme xri-sgl list
895427bd 4110 */
8a9d2e80 4111
0794d601
JS
4112 /* maximum number of xris available for nvme buffers */
4113 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
5e5b511d
JS
4114 io_xri_max = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
4115 phba->sli4_hba.io_xri_max = io_xri_max;
895427bd 4116
e8c0a779 4117 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
0794d601
JS
4118 "6074 Current allocated XRI sgl count:%d, "
4119 "maximum XRI count:%d\n",
5e5b511d
JS
4120 phba->sli4_hba.io_xri_cnt,
4121 phba->sli4_hba.io_xri_max);
8a9d2e80 4122
5e5b511d 4123 cnt = lpfc_io_buf_flush(phba, &io_sgl_list);
8a9d2e80 4124
5e5b511d 4125 if (phba->sli4_hba.io_xri_cnt > phba->sli4_hba.io_xri_max) {
0794d601 4126 /* max nvme xri shrunk below the allocated nvme buffers */
5e5b511d
JS
4127 io_xri_cnt = phba->sli4_hba.io_xri_cnt -
4128 phba->sli4_hba.io_xri_max;
0794d601 4129 /* release the extra allocated nvme buffers */
5e5b511d
JS
4130 for (i = 0; i < io_xri_cnt; i++) {
4131 list_remove_head(&io_sgl_list, lpfc_ncmd,
c490850a 4132 struct lpfc_io_buf, list);
0794d601 4133 if (lpfc_ncmd) {
771db5c0 4134 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
0794d601
JS
4135 lpfc_ncmd->data,
4136 lpfc_ncmd->dma_handle);
4137 kfree(lpfc_ncmd);
a2fc4aef 4138 }
8a9d2e80 4139 }
5e5b511d 4140 phba->sli4_hba.io_xri_cnt -= io_xri_cnt;
8a9d2e80
JS
4141 }
4142
0794d601
JS
4143 /* update xris associated to remaining allocated nvme buffers */
4144 lpfc_ncmd = NULL;
4145 lpfc_ncmd_next = NULL;
5e5b511d 4146 phba->sli4_hba.io_xri_cnt = cnt;
0794d601 4147 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
5e5b511d 4148 &io_sgl_list, list) {
8a9d2e80
JS
4149 lxri = lpfc_sli4_next_xritag(phba);
4150 if (lxri == NO_XRI) {
372c187b
DK
4151 lpfc_printf_log(phba, KERN_ERR,
4152 LOG_TRACE_EVENT,
0794d601
JS
4153 "6075 Failed to allocate xri for "
4154 "nvme buffer\n");
8a9d2e80
JS
4155 rc = -ENOMEM;
4156 goto out_free_mem;
4157 }
0794d601
JS
4158 lpfc_ncmd->cur_iocbq.sli4_lxritag = lxri;
4159 lpfc_ncmd->cur_iocbq.sli4_xritag = phba->sli4_hba.xri_ids[lxri];
8a9d2e80 4160 }
5e5b511d 4161 cnt = lpfc_io_buf_replenish(phba, &io_sgl_list);
dea3101e 4162 return 0;
8a9d2e80
JS
4163
4164out_free_mem:
5e5b511d 4165 lpfc_io_free(phba);
8a9d2e80 4166 return rc;
dea3101e 4167}
4168
0794d601 4169/**
5e5b511d 4170 * lpfc_new_io_buf - IO buffer allocator for HBA with SLI4 IF spec
fe614acd
LJ
4171 * @phba: Pointer to lpfc hba data structure.
4172 * @num_to_alloc: The requested number of buffers to allocate.
0794d601
JS
4173 *
4174 * This routine allocates nvme buffers for device with SLI-4 interface spec,
4175 * the nvme buffer contains all the necessary information needed to initiate
4176 * an I/O. After allocating up to @num_to_allocate IO buffers and put
4177 * them on a list, it post them to the port by using SGL block post.
4178 *
4179 * Return codes:
5e5b511d 4180 * int - number of IO buffers that were allocated and posted.
0794d601
JS
4181 * 0 = failure, less than num_to_alloc is a partial failure.
4182 **/
4183int
5e5b511d 4184lpfc_new_io_buf(struct lpfc_hba *phba, int num_to_alloc)
0794d601 4185{
c490850a 4186 struct lpfc_io_buf *lpfc_ncmd;
0794d601
JS
4187 struct lpfc_iocbq *pwqeq;
4188 uint16_t iotag, lxri = 0;
4189 int bcnt, num_posted;
4190 LIST_HEAD(prep_nblist);
4191 LIST_HEAD(post_nblist);
4192 LIST_HEAD(nvme_nblist);
4193
5e5b511d 4194 phba->sli4_hba.io_xri_cnt = 0;
0794d601 4195 for (bcnt = 0; bcnt < num_to_alloc; bcnt++) {
7f9989ba 4196 lpfc_ncmd = kzalloc(sizeof(*lpfc_ncmd), GFP_KERNEL);
0794d601
JS
4197 if (!lpfc_ncmd)
4198 break;
4199 /*
4200 * Get memory from the pci pool to map the virt space to
4201 * pci bus space for an I/O. The DMA buffer includes the
4202 * number of SGE's necessary to support the sg_tablesize.
4203 */
a5c990ee
TM
4204 lpfc_ncmd->data = dma_pool_zalloc(phba->lpfc_sg_dma_buf_pool,
4205 GFP_KERNEL,
4206 &lpfc_ncmd->dma_handle);
0794d601
JS
4207 if (!lpfc_ncmd->data) {
4208 kfree(lpfc_ncmd);
4209 break;
4210 }
0794d601 4211
d79c9e9d
JS
4212 if (phba->cfg_xpsgl && !phba->nvmet_support) {
4213 INIT_LIST_HEAD(&lpfc_ncmd->dma_sgl_xtra_list);
4214 } else {
4215 /*
4216 * 4K Page alignment is CRITICAL to BlockGuard, double
4217 * check to be sure.
4218 */
4219 if ((phba->sli3_options & LPFC_SLI3_BG_ENABLED) &&
4220 (((unsigned long)(lpfc_ncmd->data) &
4221 (unsigned long)(SLI4_PAGE_SIZE - 1)) != 0)) {
372c187b
DK
4222 lpfc_printf_log(phba, KERN_ERR,
4223 LOG_TRACE_EVENT,
d79c9e9d
JS
4224 "3369 Memory alignment err: "
4225 "addr=%lx\n",
4226 (unsigned long)lpfc_ncmd->data);
4227 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4228 lpfc_ncmd->data,
4229 lpfc_ncmd->dma_handle);
4230 kfree(lpfc_ncmd);
4231 break;
4232 }
0794d601
JS
4233 }
4234
d79c9e9d
JS
4235 INIT_LIST_HEAD(&lpfc_ncmd->dma_cmd_rsp_list);
4236
0794d601
JS
4237 lxri = lpfc_sli4_next_xritag(phba);
4238 if (lxri == NO_XRI) {
4239 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4240 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
4241 kfree(lpfc_ncmd);
4242 break;
4243 }
4244 pwqeq = &lpfc_ncmd->cur_iocbq;
4245
4246 /* Allocate iotag for lpfc_ncmd->cur_iocbq. */
4247 iotag = lpfc_sli_next_iotag(phba, pwqeq);
4248 if (iotag == 0) {
4249 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4250 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
4251 kfree(lpfc_ncmd);
372c187b 4252 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0794d601
JS
4253 "6121 Failed to allocate IOTAG for"
4254 " XRI:0x%x\n", lxri);
4255 lpfc_sli4_free_xri(phba, lxri);
4256 break;
4257 }
4258 pwqeq->sli4_lxritag = lxri;
4259 pwqeq->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
4260 pwqeq->context1 = lpfc_ncmd;
4261
4262 /* Initialize local short-hand pointers. */
4263 lpfc_ncmd->dma_sgl = lpfc_ncmd->data;
4264 lpfc_ncmd->dma_phys_sgl = lpfc_ncmd->dma_handle;
4265 lpfc_ncmd->cur_iocbq.context1 = lpfc_ncmd;
c2017260 4266 spin_lock_init(&lpfc_ncmd->buf_lock);
0794d601
JS
4267
4268 /* add the nvme buffer to a post list */
4269 list_add_tail(&lpfc_ncmd->list, &post_nblist);
5e5b511d 4270 phba->sli4_hba.io_xri_cnt++;
0794d601
JS
4271 }
4272 lpfc_printf_log(phba, KERN_INFO, LOG_NVME,
4273 "6114 Allocate %d out of %d requested new NVME "
4274 "buffers\n", bcnt, num_to_alloc);
4275
4276 /* post the list of nvme buffer sgls to port if available */
4277 if (!list_empty(&post_nblist))
5e5b511d 4278 num_posted = lpfc_sli4_post_io_sgl_list(
0794d601
JS
4279 phba, &post_nblist, bcnt);
4280 else
4281 num_posted = 0;
4282
4283 return num_posted;
4284}
4285
96418b5e
JS
4286static uint64_t
4287lpfc_get_wwpn(struct lpfc_hba *phba)
4288{
4289 uint64_t wwn;
4290 int rc;
4291 LPFC_MBOXQ_t *mboxq;
4292 MAILBOX_t *mb;
4293
96418b5e
JS
4294 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
4295 GFP_KERNEL);
4296 if (!mboxq)
4297 return (uint64_t)-1;
4298
4299 /* First get WWN of HBA instance */
4300 lpfc_read_nv(phba, mboxq);
4301 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
4302 if (rc != MBX_SUCCESS) {
372c187b 4303 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
96418b5e
JS
4304 "6019 Mailbox failed , mbxCmd x%x "
4305 "READ_NV, mbxStatus x%x\n",
4306 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
4307 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
4308 mempool_free(mboxq, phba->mbox_mem_pool);
4309 return (uint64_t) -1;
4310 }
4311 mb = &mboxq->u.mb;
4312 memcpy(&wwn, (char *)mb->un.varRDnvp.portname, sizeof(uint64_t));
4313 /* wwn is WWPN of HBA instance */
4314 mempool_free(mboxq, phba->mbox_mem_pool);
4315 if (phba->sli_rev == LPFC_SLI_REV4)
4316 return be64_to_cpu(wwn);
4317 else
286871a6 4318 return rol64(wwn, 32);
96418b5e
JS
4319}
4320
e59058c4 4321/**
3621a710 4322 * lpfc_create_port - Create an FC port
e59058c4
JS
4323 * @phba: pointer to lpfc hba data structure.
4324 * @instance: a unique integer ID to this FC port.
4325 * @dev: pointer to the device data structure.
4326 *
4327 * This routine creates a FC port for the upper layer protocol. The FC port
4328 * can be created on top of either a physical port or a virtual port provided
4329 * by the HBA. This routine also allocates a SCSI host data structure (shost)
4330 * and associates the FC port created before adding the shost into the SCSI
4331 * layer.
4332 *
4333 * Return codes
4334 * @vport - pointer to the virtual N_Port data structure.
4335 * NULL - port create failed.
4336 **/
2e0fef85 4337struct lpfc_vport *
3de2a653 4338lpfc_create_port(struct lpfc_hba *phba, int instance, struct device *dev)
47a8617c 4339{
2e0fef85 4340 struct lpfc_vport *vport;
895427bd 4341 struct Scsi_Host *shost = NULL;
c90b4480 4342 struct scsi_host_template *template;
2e0fef85 4343 int error = 0;
96418b5e
JS
4344 int i;
4345 uint64_t wwn;
4346 bool use_no_reset_hba = false;
56bc8028 4347 int rc;
96418b5e 4348
56bc8028
JS
4349 if (lpfc_no_hba_reset_cnt) {
4350 if (phba->sli_rev < LPFC_SLI_REV4 &&
4351 dev == &phba->pcidev->dev) {
4352 /* Reset the port first */
4353 lpfc_sli_brdrestart(phba);
4354 rc = lpfc_sli_chipset_init(phba);
4355 if (rc)
4356 return NULL;
4357 }
4358 wwn = lpfc_get_wwpn(phba);
4359 }
96418b5e
JS
4360
4361 for (i = 0; i < lpfc_no_hba_reset_cnt; i++) {
4362 if (wwn == lpfc_no_hba_reset[i]) {
372c187b
DK
4363 lpfc_printf_log(phba, KERN_ERR,
4364 LOG_TRACE_EVENT,
96418b5e
JS
4365 "6020 Setting use_no_reset port=%llx\n",
4366 wwn);
4367 use_no_reset_hba = true;
4368 break;
4369 }
4370 }
47a8617c 4371
c90b4480
JS
4372 /* Seed template for SCSI host registration */
4373 if (dev == &phba->pcidev->dev) {
4374 template = &phba->port_template;
4375
4376 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
4377 /* Seed physical port template */
4378 memcpy(template, &lpfc_template, sizeof(*template));
4379
7c30bb62 4380 if (use_no_reset_hba)
c90b4480 4381 /* template is for a no reset SCSI Host */
c90b4480 4382 template->eh_host_reset_handler = NULL;
c90b4480
JS
4383
4384 /* Template for all vports this physical port creates */
4385 memcpy(&phba->vport_template, &lpfc_template,
4386 sizeof(*template));
c90b4480
JS
4387 phba->vport_template.shost_attrs = lpfc_vport_attrs;
4388 phba->vport_template.eh_bus_reset_handler = NULL;
4389 phba->vport_template.eh_host_reset_handler = NULL;
4390 phba->vport_template.vendor_id = 0;
4391
4392 /* Initialize the host templates with updated value */
4393 if (phba->sli_rev == LPFC_SLI_REV4) {
4394 template->sg_tablesize = phba->cfg_scsi_seg_cnt;
4395 phba->vport_template.sg_tablesize =
4396 phba->cfg_scsi_seg_cnt;
4397 } else {
4398 template->sg_tablesize = phba->cfg_sg_seg_cnt;
4399 phba->vport_template.sg_tablesize =
4400 phba->cfg_sg_seg_cnt;
4401 }
4402
895427bd 4403 } else {
c90b4480
JS
4404 /* NVMET is for physical port only */
4405 memcpy(template, &lpfc_template_nvme,
4406 sizeof(*template));
895427bd 4407 }
c90b4480
JS
4408 } else {
4409 template = &phba->vport_template;
ea4142f6 4410 }
c90b4480
JS
4411
4412 shost = scsi_host_alloc(template, sizeof(struct lpfc_vport));
2e0fef85
JS
4413 if (!shost)
4414 goto out;
47a8617c 4415
2e0fef85
JS
4416 vport = (struct lpfc_vport *) shost->hostdata;
4417 vport->phba = phba;
2e0fef85 4418 vport->load_flag |= FC_LOADING;
92d7f7b0 4419 vport->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
7f5f3d0d 4420 vport->fc_rscn_flush = 0;
3de2a653 4421 lpfc_get_vport_cfgparam(vport);
895427bd 4422
f6e84790
JS
4423 /* Adjust value in vport */
4424 vport->cfg_enable_fc4_type = phba->cfg_enable_fc4_type;
4425
2e0fef85
JS
4426 shost->unique_id = instance;
4427 shost->max_id = LPFC_MAX_TARGET;
3de2a653 4428 shost->max_lun = vport->cfg_max_luns;
2e0fef85
JS
4429 shost->this_id = -1;
4430 shost->max_cmd_len = 16;
6a828b0f 4431
da0436e9 4432 if (phba->sli_rev == LPFC_SLI_REV4) {
77ffd346
JS
4433 if (!phba->cfg_fcp_mq_threshold ||
4434 phba->cfg_fcp_mq_threshold > phba->cfg_hdw_queue)
4435 phba->cfg_fcp_mq_threshold = phba->cfg_hdw_queue;
4436
4437 shost->nr_hw_queues = min_t(int, 2 * num_possible_nodes(),
4438 phba->cfg_fcp_mq_threshold);
6a828b0f 4439
28baac74 4440 shost->dma_boundary =
cb5172ea 4441 phba->sli4_hba.pc_sli4_params.sge_supp_len-1;
d79c9e9d
JS
4442
4443 if (phba->cfg_xpsgl && !phba->nvmet_support)
4444 shost->sg_tablesize = LPFC_MAX_SG_TABLESIZE;
4445 else
4446 shost->sg_tablesize = phba->cfg_scsi_seg_cnt;
ace44e48
JS
4447 } else
4448 /* SLI-3 has a limited number of hardware queues (3),
4449 * thus there is only one for FCP processing.
4450 */
4451 shost->nr_hw_queues = 1;
81301a9b 4452
47a8617c 4453 /*
2e0fef85
JS
4454 * Set initial can_queue value since 0 is no longer supported and
4455 * scsi_add_host will fail. This will be adjusted later based on the
4456 * max xri value determined in hba setup.
47a8617c 4457 */
2e0fef85 4458 shost->can_queue = phba->cfg_hba_queue_depth - 10;
3de2a653 4459 if (dev != &phba->pcidev->dev) {
92d7f7b0
JS
4460 shost->transportt = lpfc_vport_transport_template;
4461 vport->port_type = LPFC_NPIV_PORT;
4462 } else {
4463 shost->transportt = lpfc_transport_template;
4464 vport->port_type = LPFC_PHYSICAL_PORT;
4465 }
47a8617c 4466
c90b4480
JS
4467 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
4468 "9081 CreatePort TMPLATE type %x TBLsize %d "
4469 "SEGcnt %d/%d\n",
4470 vport->port_type, shost->sg_tablesize,
4471 phba->cfg_scsi_seg_cnt, phba->cfg_sg_seg_cnt);
4472
2e0fef85
JS
4473 /* Initialize all internally managed lists. */
4474 INIT_LIST_HEAD(&vport->fc_nodes);
da0436e9 4475 INIT_LIST_HEAD(&vport->rcv_buffer_list);
2e0fef85 4476 spin_lock_init(&vport->work_port_lock);
47a8617c 4477
f22eb4d3 4478 timer_setup(&vport->fc_disctmo, lpfc_disc_timeout, 0);
47a8617c 4479
f22eb4d3 4480 timer_setup(&vport->els_tmofunc, lpfc_els_timeout, 0);
92494144 4481
f22eb4d3 4482 timer_setup(&vport->delayed_disc_tmo, lpfc_delayed_disc_tmo, 0);
92494144 4483
aa6ff309
JS
4484 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED)
4485 lpfc_setup_bg(phba, shost);
4486
d139b9bd 4487 error = scsi_add_host_with_dma(shost, dev, &phba->pcidev->dev);
2e0fef85
JS
4488 if (error)
4489 goto out_put_shost;
47a8617c 4490
523128e5 4491 spin_lock_irq(&phba->port_list_lock);
2e0fef85 4492 list_add_tail(&vport->listentry, &phba->port_list);
523128e5 4493 spin_unlock_irq(&phba->port_list_lock);
2e0fef85 4494 return vport;
47a8617c 4495
2e0fef85
JS
4496out_put_shost:
4497 scsi_host_put(shost);
4498out:
4499 return NULL;
47a8617c
JS
4500}
4501
e59058c4 4502/**
3621a710 4503 * destroy_port - destroy an FC port
e59058c4
JS
4504 * @vport: pointer to an lpfc virtual N_Port data structure.
4505 *
4506 * This routine destroys a FC port from the upper layer protocol. All the
4507 * resources associated with the port are released.
4508 **/
2e0fef85
JS
4509void
4510destroy_port(struct lpfc_vport *vport)
47a8617c 4511{
92d7f7b0
JS
4512 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
4513 struct lpfc_hba *phba = vport->phba;
47a8617c 4514
858c9f6c 4515 lpfc_debugfs_terminate(vport);
92d7f7b0
JS
4516 fc_remove_host(shost);
4517 scsi_remove_host(shost);
47a8617c 4518
523128e5 4519 spin_lock_irq(&phba->port_list_lock);
92d7f7b0 4520 list_del_init(&vport->listentry);
523128e5 4521 spin_unlock_irq(&phba->port_list_lock);
47a8617c 4522
92d7f7b0 4523 lpfc_cleanup(vport);
47a8617c 4524 return;
47a8617c
JS
4525}
4526
e59058c4 4527/**
3621a710 4528 * lpfc_get_instance - Get a unique integer ID
e59058c4
JS
4529 *
4530 * This routine allocates a unique integer ID from lpfc_hba_index pool. It
4531 * uses the kernel idr facility to perform the task.
4532 *
4533 * Return codes:
4534 * instance - a unique integer ID allocated as the new instance.
4535 * -1 - lpfc get instance failed.
4536 **/
92d7f7b0
JS
4537int
4538lpfc_get_instance(void)
4539{
ab516036
TH
4540 int ret;
4541
4542 ret = idr_alloc(&lpfc_hba_index, NULL, 0, 0, GFP_KERNEL);
4543 return ret < 0 ? -1 : ret;
47a8617c
JS
4544}
4545
e59058c4 4546/**
3621a710 4547 * lpfc_scan_finished - method for SCSI layer to detect whether scan is done
e59058c4
JS
4548 * @shost: pointer to SCSI host data structure.
4549 * @time: elapsed time of the scan in jiffies.
4550 *
4551 * This routine is called by the SCSI layer with a SCSI host to determine
4552 * whether the scan host is finished.
4553 *
4554 * Note: there is no scan_start function as adapter initialization will have
4555 * asynchronously kicked off the link initialization.
4556 *
4557 * Return codes
4558 * 0 - SCSI host scan is not over yet.
4559 * 1 - SCSI host scan is over.
4560 **/
47a8617c
JS
4561int lpfc_scan_finished(struct Scsi_Host *shost, unsigned long time)
4562{
2e0fef85
JS
4563 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4564 struct lpfc_hba *phba = vport->phba;
858c9f6c 4565 int stat = 0;
47a8617c 4566
858c9f6c
JS
4567 spin_lock_irq(shost->host_lock);
4568
51ef4c26 4569 if (vport->load_flag & FC_UNLOADING) {
858c9f6c
JS
4570 stat = 1;
4571 goto finished;
4572 }
256ec0d0 4573 if (time >= msecs_to_jiffies(30 * 1000)) {
2e0fef85 4574 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011
JS
4575 "0461 Scanning longer than 30 "
4576 "seconds. Continuing initialization\n");
858c9f6c 4577 stat = 1;
47a8617c 4578 goto finished;
2e0fef85 4579 }
256ec0d0
JS
4580 if (time >= msecs_to_jiffies(15 * 1000) &&
4581 phba->link_state <= LPFC_LINK_DOWN) {
2e0fef85 4582 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011
JS
4583 "0465 Link down longer than 15 "
4584 "seconds. Continuing initialization\n");
858c9f6c 4585 stat = 1;
47a8617c 4586 goto finished;
2e0fef85 4587 }
47a8617c 4588
2e0fef85 4589 if (vport->port_state != LPFC_VPORT_READY)
858c9f6c 4590 goto finished;
2e0fef85 4591 if (vport->num_disc_nodes || vport->fc_prli_sent)
858c9f6c 4592 goto finished;
256ec0d0 4593 if (vport->fc_map_cnt == 0 && time < msecs_to_jiffies(2 * 1000))
858c9f6c 4594 goto finished;
2e0fef85 4595 if ((phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) != 0)
858c9f6c
JS
4596 goto finished;
4597
4598 stat = 1;
47a8617c
JS
4599
4600finished:
858c9f6c
JS
4601 spin_unlock_irq(shost->host_lock);
4602 return stat;
92d7f7b0 4603}
47a8617c 4604
3999df75 4605static void lpfc_host_supported_speeds_set(struct Scsi_Host *shost)
cd71348a
JS
4606{
4607 struct lpfc_vport *vport = (struct lpfc_vport *)shost->hostdata;
4608 struct lpfc_hba *phba = vport->phba;
4609
4610 fc_host_supported_speeds(shost) = 0;
a1e4d3d8
DK
4611 /*
4612 * Avoid reporting supported link speed for FCoE as it can't be
4613 * controlled via FCoE.
4614 */
4615 if (phba->hba_flag & HBA_FCOE_MODE)
4616 return;
4617
1dc5ec24
JS
4618 if (phba->lmt & LMT_128Gb)
4619 fc_host_supported_speeds(shost) |= FC_PORTSPEED_128GBIT;
cd71348a
JS
4620 if (phba->lmt & LMT_64Gb)
4621 fc_host_supported_speeds(shost) |= FC_PORTSPEED_64GBIT;
4622 if (phba->lmt & LMT_32Gb)
4623 fc_host_supported_speeds(shost) |= FC_PORTSPEED_32GBIT;
4624 if (phba->lmt & LMT_16Gb)
4625 fc_host_supported_speeds(shost) |= FC_PORTSPEED_16GBIT;
4626 if (phba->lmt & LMT_10Gb)
4627 fc_host_supported_speeds(shost) |= FC_PORTSPEED_10GBIT;
4628 if (phba->lmt & LMT_8Gb)
4629 fc_host_supported_speeds(shost) |= FC_PORTSPEED_8GBIT;
4630 if (phba->lmt & LMT_4Gb)
4631 fc_host_supported_speeds(shost) |= FC_PORTSPEED_4GBIT;
4632 if (phba->lmt & LMT_2Gb)
4633 fc_host_supported_speeds(shost) |= FC_PORTSPEED_2GBIT;
4634 if (phba->lmt & LMT_1Gb)
4635 fc_host_supported_speeds(shost) |= FC_PORTSPEED_1GBIT;
4636}
4637
e59058c4 4638/**
3621a710 4639 * lpfc_host_attrib_init - Initialize SCSI host attributes on a FC port
e59058c4
JS
4640 * @shost: pointer to SCSI host data structure.
4641 *
4642 * This routine initializes a given SCSI host attributes on a FC port. The
4643 * SCSI host can be either on top of a physical port or a virtual port.
4644 **/
92d7f7b0
JS
4645void lpfc_host_attrib_init(struct Scsi_Host *shost)
4646{
4647 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4648 struct lpfc_hba *phba = vport->phba;
47a8617c 4649 /*
2e0fef85 4650 * Set fixed host attributes. Must done after lpfc_sli_hba_setup().
47a8617c
JS
4651 */
4652
2e0fef85
JS
4653 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
4654 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
47a8617c
JS
4655 fc_host_supported_classes(shost) = FC_COS_CLASS3;
4656
4657 memset(fc_host_supported_fc4s(shost), 0,
2e0fef85 4658 sizeof(fc_host_supported_fc4s(shost)));
47a8617c
JS
4659 fc_host_supported_fc4s(shost)[2] = 1;
4660 fc_host_supported_fc4s(shost)[7] = 1;
4661
92d7f7b0
JS
4662 lpfc_vport_symbolic_node_name(vport, fc_host_symbolic_name(shost),
4663 sizeof fc_host_symbolic_name(shost));
47a8617c 4664
cd71348a 4665 lpfc_host_supported_speeds_set(shost);
47a8617c
JS
4666
4667 fc_host_maxframe_size(shost) =
2e0fef85
JS
4668 (((uint32_t) vport->fc_sparam.cmn.bbRcvSizeMsb & 0x0F) << 8) |
4669 (uint32_t) vport->fc_sparam.cmn.bbRcvSizeLsb;
47a8617c 4670
0af5d708
MC
4671 fc_host_dev_loss_tmo(shost) = vport->cfg_devloss_tmo;
4672
47a8617c
JS
4673 /* This value is also unchanging */
4674 memset(fc_host_active_fc4s(shost), 0,
2e0fef85 4675 sizeof(fc_host_active_fc4s(shost)));
47a8617c
JS
4676 fc_host_active_fc4s(shost)[2] = 1;
4677 fc_host_active_fc4s(shost)[7] = 1;
4678
92d7f7b0 4679 fc_host_max_npiv_vports(shost) = phba->max_vpi;
47a8617c 4680 spin_lock_irq(shost->host_lock);
51ef4c26 4681 vport->load_flag &= ~FC_LOADING;
47a8617c 4682 spin_unlock_irq(shost->host_lock);
47a8617c 4683}
dea3101e 4684
e59058c4 4685/**
da0436e9 4686 * lpfc_stop_port_s3 - Stop SLI3 device port
e59058c4
JS
4687 * @phba: pointer to lpfc hba data structure.
4688 *
da0436e9
JS
4689 * This routine is invoked to stop an SLI3 device port, it stops the device
4690 * from generating interrupts and stops the device driver's timers for the
4691 * device.
e59058c4 4692 **/
da0436e9
JS
4693static void
4694lpfc_stop_port_s3(struct lpfc_hba *phba)
db2378e0 4695{
da0436e9
JS
4696 /* Clear all interrupt enable conditions */
4697 writel(0, phba->HCregaddr);
4698 readl(phba->HCregaddr); /* flush */
4699 /* Clear all pending interrupts */
4700 writel(0xffffffff, phba->HAregaddr);
4701 readl(phba->HAregaddr); /* flush */
db2378e0 4702
da0436e9
JS
4703 /* Reset some HBA SLI setup states */
4704 lpfc_stop_hba_timers(phba);
4705 phba->pport->work_port_events = 0;
4706}
db2378e0 4707
da0436e9
JS
4708/**
4709 * lpfc_stop_port_s4 - Stop SLI4 device port
4710 * @phba: pointer to lpfc hba data structure.
4711 *
4712 * This routine is invoked to stop an SLI4 device port, it stops the device
4713 * from generating interrupts and stops the device driver's timers for the
4714 * device.
4715 **/
4716static void
4717lpfc_stop_port_s4(struct lpfc_hba *phba)
4718{
4719 /* Reset some HBA SLI4 setup states */
4720 lpfc_stop_hba_timers(phba);
cdb42bec
JS
4721 if (phba->pport)
4722 phba->pport->work_port_events = 0;
da0436e9 4723 phba->sli4_hba.intr_enable = 0;
da0436e9 4724}
9399627f 4725
da0436e9
JS
4726/**
4727 * lpfc_stop_port - Wrapper function for stopping hba port
4728 * @phba: Pointer to HBA context object.
4729 *
4730 * This routine wraps the actual SLI3 or SLI4 hba stop port routine from
4731 * the API jump table function pointer from the lpfc_hba struct.
4732 **/
4733void
4734lpfc_stop_port(struct lpfc_hba *phba)
4735{
4736 phba->lpfc_stop_port(phba);
f485c18d
DK
4737
4738 if (phba->wq)
4739 flush_workqueue(phba->wq);
da0436e9 4740}
db2378e0 4741
ecfd03c6
JS
4742/**
4743 * lpfc_fcf_redisc_wait_start_timer - Start fcf rediscover wait timer
4744 * @phba: Pointer to hba for which this call is being executed.
4745 *
4746 * This routine starts the timer waiting for the FCF rediscovery to complete.
4747 **/
4748void
4749lpfc_fcf_redisc_wait_start_timer(struct lpfc_hba *phba)
4750{
4751 unsigned long fcf_redisc_wait_tmo =
4752 (jiffies + msecs_to_jiffies(LPFC_FCF_REDISCOVER_WAIT_TMO));
4753 /* Start fcf rediscovery wait period timer */
4754 mod_timer(&phba->fcf.redisc_wait, fcf_redisc_wait_tmo);
4755 spin_lock_irq(&phba->hbalock);
4756 /* Allow action to new fcf asynchronous event */
4757 phba->fcf.fcf_flag &= ~(FCF_AVAILABLE | FCF_SCAN_DONE);
4758 /* Mark the FCF rediscovery pending state */
4759 phba->fcf.fcf_flag |= FCF_REDISC_PEND;
4760 spin_unlock_irq(&phba->hbalock);
4761}
4762
4763/**
4764 * lpfc_sli4_fcf_redisc_wait_tmo - FCF table rediscover wait timeout
fe614acd 4765 * @t: Timer context used to obtain the pointer to lpfc hba data structure.
ecfd03c6
JS
4766 *
4767 * This routine is invoked when waiting for FCF table rediscover has been
4768 * timed out. If new FCF record(s) has (have) been discovered during the
4769 * wait period, a new FCF event shall be added to the FCOE async event
4770 * list, and then worker thread shall be waked up for processing from the
4771 * worker thread context.
4772 **/
e399b228 4773static void
f22eb4d3 4774lpfc_sli4_fcf_redisc_wait_tmo(struct timer_list *t)
ecfd03c6 4775{
f22eb4d3 4776 struct lpfc_hba *phba = from_timer(phba, t, fcf.redisc_wait);
ecfd03c6
JS
4777
4778 /* Don't send FCF rediscovery event if timer cancelled */
4779 spin_lock_irq(&phba->hbalock);
4780 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
4781 spin_unlock_irq(&phba->hbalock);
4782 return;
4783 }
4784 /* Clear FCF rediscovery timer pending flag */
4785 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
4786 /* FCF rediscovery event to worker thread */
4787 phba->fcf.fcf_flag |= FCF_REDISC_EVT;
4788 spin_unlock_irq(&phba->hbalock);
0c9ab6f5 4789 lpfc_printf_log(phba, KERN_INFO, LOG_FIP,
a93ff37a 4790 "2776 FCF rediscover quiescent timer expired\n");
ecfd03c6
JS
4791 /* wake up worker thread */
4792 lpfc_worker_wake_up(phba);
4793}
4794
e59058c4 4795/**
da0436e9 4796 * lpfc_sli4_parse_latt_fault - Parse sli4 link-attention link fault code
e59058c4 4797 * @phba: pointer to lpfc hba data structure.
da0436e9 4798 * @acqe_link: pointer to the async link completion queue entry.
e59058c4 4799 *
23288b78 4800 * This routine is to parse the SLI4 link-attention link fault code.
e59058c4 4801 **/
23288b78 4802static void
da0436e9
JS
4803lpfc_sli4_parse_latt_fault(struct lpfc_hba *phba,
4804 struct lpfc_acqe_link *acqe_link)
db2378e0 4805{
da0436e9
JS
4806 switch (bf_get(lpfc_acqe_link_fault, acqe_link)) {
4807 case LPFC_ASYNC_LINK_FAULT_NONE:
4808 case LPFC_ASYNC_LINK_FAULT_LOCAL:
4809 case LPFC_ASYNC_LINK_FAULT_REMOTE:
23288b78 4810 case LPFC_ASYNC_LINK_FAULT_LR_LRR:
da0436e9
JS
4811 break;
4812 default:
372c187b 4813 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
23288b78 4814 "0398 Unknown link fault code: x%x\n",
da0436e9 4815 bf_get(lpfc_acqe_link_fault, acqe_link));
da0436e9
JS
4816 break;
4817 }
db2378e0
JS
4818}
4819
5b75da2f 4820/**
da0436e9 4821 * lpfc_sli4_parse_latt_type - Parse sli4 link attention type
5b75da2f 4822 * @phba: pointer to lpfc hba data structure.
da0436e9 4823 * @acqe_link: pointer to the async link completion queue entry.
5b75da2f 4824 *
da0436e9
JS
4825 * This routine is to parse the SLI4 link attention type and translate it
4826 * into the base driver's link attention type coding.
5b75da2f 4827 *
da0436e9
JS
4828 * Return: Link attention type in terms of base driver's coding.
4829 **/
4830static uint8_t
4831lpfc_sli4_parse_latt_type(struct lpfc_hba *phba,
4832 struct lpfc_acqe_link *acqe_link)
5b75da2f 4833{
da0436e9 4834 uint8_t att_type;
5b75da2f 4835
da0436e9
JS
4836 switch (bf_get(lpfc_acqe_link_status, acqe_link)) {
4837 case LPFC_ASYNC_LINK_STATUS_DOWN:
4838 case LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN:
76a95d75 4839 att_type = LPFC_ATT_LINK_DOWN;
da0436e9
JS
4840 break;
4841 case LPFC_ASYNC_LINK_STATUS_UP:
4842 /* Ignore physical link up events - wait for logical link up */
76a95d75 4843 att_type = LPFC_ATT_RESERVED;
da0436e9
JS
4844 break;
4845 case LPFC_ASYNC_LINK_STATUS_LOGICAL_UP:
76a95d75 4846 att_type = LPFC_ATT_LINK_UP;
da0436e9
JS
4847 break;
4848 default:
372c187b 4849 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
4850 "0399 Invalid link attention type: x%x\n",
4851 bf_get(lpfc_acqe_link_status, acqe_link));
76a95d75 4852 att_type = LPFC_ATT_RESERVED;
da0436e9 4853 break;
5b75da2f 4854 }
da0436e9 4855 return att_type;
5b75da2f
JS
4856}
4857
8b68cd52
JS
4858/**
4859 * lpfc_sli_port_speed_get - Get sli3 link speed code to link speed
4860 * @phba: pointer to lpfc hba data structure.
4861 *
4862 * This routine is to get an SLI3 FC port's link speed in Mbps.
4863 *
4864 * Return: link speed in terms of Mbps.
4865 **/
4866uint32_t
4867lpfc_sli_port_speed_get(struct lpfc_hba *phba)
4868{
4869 uint32_t link_speed;
4870
4871 if (!lpfc_is_link_up(phba))
4872 return 0;
4873
a085e87c
JS
4874 if (phba->sli_rev <= LPFC_SLI_REV3) {
4875 switch (phba->fc_linkspeed) {
4876 case LPFC_LINK_SPEED_1GHZ:
4877 link_speed = 1000;
4878 break;
4879 case LPFC_LINK_SPEED_2GHZ:
4880 link_speed = 2000;
4881 break;
4882 case LPFC_LINK_SPEED_4GHZ:
4883 link_speed = 4000;
4884 break;
4885 case LPFC_LINK_SPEED_8GHZ:
4886 link_speed = 8000;
4887 break;
4888 case LPFC_LINK_SPEED_10GHZ:
4889 link_speed = 10000;
4890 break;
4891 case LPFC_LINK_SPEED_16GHZ:
4892 link_speed = 16000;
4893 break;
4894 default:
4895 link_speed = 0;
4896 }
4897 } else {
4898 if (phba->sli4_hba.link_state.logical_speed)
4899 link_speed =
4900 phba->sli4_hba.link_state.logical_speed;
4901 else
4902 link_speed = phba->sli4_hba.link_state.speed;
8b68cd52
JS
4903 }
4904 return link_speed;
4905}
4906
4907/**
4908 * lpfc_sli4_port_speed_parse - Parse async evt link speed code to link speed
4909 * @phba: pointer to lpfc hba data structure.
4910 * @evt_code: asynchronous event code.
4911 * @speed_code: asynchronous event link speed code.
4912 *
4913 * This routine is to parse the giving SLI4 async event link speed code into
4914 * value of Mbps for the link speed.
4915 *
4916 * Return: link speed in terms of Mbps.
4917 **/
4918static uint32_t
4919lpfc_sli4_port_speed_parse(struct lpfc_hba *phba, uint32_t evt_code,
4920 uint8_t speed_code)
4921{
4922 uint32_t port_speed;
4923
4924 switch (evt_code) {
4925 case LPFC_TRAILER_CODE_LINK:
4926 switch (speed_code) {
26d830ec 4927 case LPFC_ASYNC_LINK_SPEED_ZERO:
8b68cd52
JS
4928 port_speed = 0;
4929 break;
26d830ec 4930 case LPFC_ASYNC_LINK_SPEED_10MBPS:
8b68cd52
JS
4931 port_speed = 10;
4932 break;
26d830ec 4933 case LPFC_ASYNC_LINK_SPEED_100MBPS:
8b68cd52
JS
4934 port_speed = 100;
4935 break;
26d830ec 4936 case LPFC_ASYNC_LINK_SPEED_1GBPS:
8b68cd52
JS
4937 port_speed = 1000;
4938 break;
26d830ec 4939 case LPFC_ASYNC_LINK_SPEED_10GBPS:
8b68cd52
JS
4940 port_speed = 10000;
4941 break;
26d830ec
JS
4942 case LPFC_ASYNC_LINK_SPEED_20GBPS:
4943 port_speed = 20000;
4944 break;
4945 case LPFC_ASYNC_LINK_SPEED_25GBPS:
4946 port_speed = 25000;
4947 break;
4948 case LPFC_ASYNC_LINK_SPEED_40GBPS:
4949 port_speed = 40000;
4950 break;
a1e4d3d8
DK
4951 case LPFC_ASYNC_LINK_SPEED_100GBPS:
4952 port_speed = 100000;
4953 break;
8b68cd52
JS
4954 default:
4955 port_speed = 0;
4956 }
4957 break;
4958 case LPFC_TRAILER_CODE_FC:
4959 switch (speed_code) {
26d830ec 4960 case LPFC_FC_LA_SPEED_UNKNOWN:
8b68cd52
JS
4961 port_speed = 0;
4962 break;
26d830ec 4963 case LPFC_FC_LA_SPEED_1G:
8b68cd52
JS
4964 port_speed = 1000;
4965 break;
26d830ec 4966 case LPFC_FC_LA_SPEED_2G:
8b68cd52
JS
4967 port_speed = 2000;
4968 break;
26d830ec 4969 case LPFC_FC_LA_SPEED_4G:
8b68cd52
JS
4970 port_speed = 4000;
4971 break;
26d830ec 4972 case LPFC_FC_LA_SPEED_8G:
8b68cd52
JS
4973 port_speed = 8000;
4974 break;
26d830ec 4975 case LPFC_FC_LA_SPEED_10G:
8b68cd52
JS
4976 port_speed = 10000;
4977 break;
26d830ec 4978 case LPFC_FC_LA_SPEED_16G:
8b68cd52
JS
4979 port_speed = 16000;
4980 break;
d38dd52c
JS
4981 case LPFC_FC_LA_SPEED_32G:
4982 port_speed = 32000;
4983 break;
fbd8a6ba
JS
4984 case LPFC_FC_LA_SPEED_64G:
4985 port_speed = 64000;
4986 break;
1dc5ec24
JS
4987 case LPFC_FC_LA_SPEED_128G:
4988 port_speed = 128000;
4989 break;
8b68cd52
JS
4990 default:
4991 port_speed = 0;
4992 }
4993 break;
4994 default:
4995 port_speed = 0;
4996 }
4997 return port_speed;
4998}
4999
da0436e9 5000/**
70f3c073 5001 * lpfc_sli4_async_link_evt - Process the asynchronous FCoE link event
da0436e9
JS
5002 * @phba: pointer to lpfc hba data structure.
5003 * @acqe_link: pointer to the async link completion queue entry.
5004 *
70f3c073 5005 * This routine is to handle the SLI4 asynchronous FCoE link event.
da0436e9
JS
5006 **/
5007static void
5008lpfc_sli4_async_link_evt(struct lpfc_hba *phba,
5009 struct lpfc_acqe_link *acqe_link)
5010{
5011 struct lpfc_dmabuf *mp;
5012 LPFC_MBOXQ_t *pmb;
5013 MAILBOX_t *mb;
76a95d75 5014 struct lpfc_mbx_read_top *la;
da0436e9 5015 uint8_t att_type;
76a95d75 5016 int rc;
da0436e9
JS
5017
5018 att_type = lpfc_sli4_parse_latt_type(phba, acqe_link);
76a95d75 5019 if (att_type != LPFC_ATT_LINK_DOWN && att_type != LPFC_ATT_LINK_UP)
da0436e9 5020 return;
32b9793f 5021 phba->fcoe_eventtag = acqe_link->event_tag;
da0436e9
JS
5022 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
5023 if (!pmb) {
372c187b 5024 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
5025 "0395 The mboxq allocation failed\n");
5026 return;
5027 }
5028 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
5029 if (!mp) {
372c187b 5030 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
5031 "0396 The lpfc_dmabuf allocation failed\n");
5032 goto out_free_pmb;
5033 }
5034 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
5035 if (!mp->virt) {
372c187b 5036 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
5037 "0397 The mbuf allocation failed\n");
5038 goto out_free_dmabuf;
5039 }
5040
5041 /* Cleanup any outstanding ELS commands */
5042 lpfc_els_flush_all_cmd(phba);
5043
5044 /* Block ELS IOCBs until we have done process link event */
895427bd 5045 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
da0436e9
JS
5046
5047 /* Update link event statistics */
5048 phba->sli.slistat.link_event++;
5049
76a95d75
JS
5050 /* Create lpfc_handle_latt mailbox command from link ACQE */
5051 lpfc_read_topology(phba, pmb, mp);
5052 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
da0436e9
JS
5053 pmb->vport = phba->pport;
5054
da0436e9
JS
5055 /* Keep the link status for extra SLI4 state machine reference */
5056 phba->sli4_hba.link_state.speed =
8b68cd52
JS
5057 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_LINK,
5058 bf_get(lpfc_acqe_link_speed, acqe_link));
da0436e9
JS
5059 phba->sli4_hba.link_state.duplex =
5060 bf_get(lpfc_acqe_link_duplex, acqe_link);
5061 phba->sli4_hba.link_state.status =
5062 bf_get(lpfc_acqe_link_status, acqe_link);
70f3c073
JS
5063 phba->sli4_hba.link_state.type =
5064 bf_get(lpfc_acqe_link_type, acqe_link);
5065 phba->sli4_hba.link_state.number =
5066 bf_get(lpfc_acqe_link_number, acqe_link);
da0436e9
JS
5067 phba->sli4_hba.link_state.fault =
5068 bf_get(lpfc_acqe_link_fault, acqe_link);
65467b6b 5069 phba->sli4_hba.link_state.logical_speed =
8b68cd52
JS
5070 bf_get(lpfc_acqe_logical_link_speed, acqe_link) * 10;
5071
70f3c073 5072 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
c31098ce
JS
5073 "2900 Async FC/FCoE Link event - Speed:%dGBit "
5074 "duplex:x%x LA Type:x%x Port Type:%d Port Number:%d "
5075 "Logical speed:%dMbps Fault:%d\n",
70f3c073
JS
5076 phba->sli4_hba.link_state.speed,
5077 phba->sli4_hba.link_state.topology,
5078 phba->sli4_hba.link_state.status,
5079 phba->sli4_hba.link_state.type,
5080 phba->sli4_hba.link_state.number,
8b68cd52 5081 phba->sli4_hba.link_state.logical_speed,
70f3c073 5082 phba->sli4_hba.link_state.fault);
76a95d75
JS
5083 /*
5084 * For FC Mode: issue the READ_TOPOLOGY mailbox command to fetch
5085 * topology info. Note: Optional for non FC-AL ports.
5086 */
5087 if (!(phba->hba_flag & HBA_FCOE_MODE)) {
5088 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
5089 if (rc == MBX_NOT_FINISHED)
5090 goto out_free_dmabuf;
5091 return;
5092 }
5093 /*
5094 * For FCoE Mode: fill in all the topology information we need and call
5095 * the READ_TOPOLOGY completion routine to continue without actually
5096 * sending the READ_TOPOLOGY mailbox command to the port.
5097 */
23288b78 5098 /* Initialize completion status */
76a95d75 5099 mb = &pmb->u.mb;
23288b78
JS
5100 mb->mbxStatus = MBX_SUCCESS;
5101
5102 /* Parse port fault information field */
5103 lpfc_sli4_parse_latt_fault(phba, acqe_link);
76a95d75
JS
5104
5105 /* Parse and translate link attention fields */
5106 la = (struct lpfc_mbx_read_top *) &pmb->u.mb.un.varReadTop;
5107 la->eventTag = acqe_link->event_tag;
5108 bf_set(lpfc_mbx_read_top_att_type, la, att_type);
5109 bf_set(lpfc_mbx_read_top_link_spd, la,
a085e87c 5110 (bf_get(lpfc_acqe_link_speed, acqe_link)));
76a95d75
JS
5111
5112 /* Fake the the following irrelvant fields */
5113 bf_set(lpfc_mbx_read_top_topology, la, LPFC_TOPOLOGY_PT_PT);
5114 bf_set(lpfc_mbx_read_top_alpa_granted, la, 0);
5115 bf_set(lpfc_mbx_read_top_il, la, 0);
5116 bf_set(lpfc_mbx_read_top_pb, la, 0);
5117 bf_set(lpfc_mbx_read_top_fa, la, 0);
5118 bf_set(lpfc_mbx_read_top_mm, la, 0);
da0436e9
JS
5119
5120 /* Invoke the lpfc_handle_latt mailbox command callback function */
76a95d75 5121 lpfc_mbx_cmpl_read_topology(phba, pmb);
da0436e9 5122
5b75da2f 5123 return;
da0436e9
JS
5124
5125out_free_dmabuf:
5126 kfree(mp);
5127out_free_pmb:
5128 mempool_free(pmb, phba->mbox_mem_pool);
5129}
5130
1dc5ec24
JS
5131/**
5132 * lpfc_async_link_speed_to_read_top - Parse async evt link speed code to read
5133 * topology.
5134 * @phba: pointer to lpfc hba data structure.
1dc5ec24
JS
5135 * @speed_code: asynchronous event link speed code.
5136 *
5137 * This routine is to parse the giving SLI4 async event link speed code into
5138 * value of Read topology link speed.
5139 *
5140 * Return: link speed in terms of Read topology.
5141 **/
5142static uint8_t
5143lpfc_async_link_speed_to_read_top(struct lpfc_hba *phba, uint8_t speed_code)
5144{
5145 uint8_t port_speed;
5146
5147 switch (speed_code) {
5148 case LPFC_FC_LA_SPEED_1G:
5149 port_speed = LPFC_LINK_SPEED_1GHZ;
5150 break;
5151 case LPFC_FC_LA_SPEED_2G:
5152 port_speed = LPFC_LINK_SPEED_2GHZ;
5153 break;
5154 case LPFC_FC_LA_SPEED_4G:
5155 port_speed = LPFC_LINK_SPEED_4GHZ;
5156 break;
5157 case LPFC_FC_LA_SPEED_8G:
5158 port_speed = LPFC_LINK_SPEED_8GHZ;
5159 break;
5160 case LPFC_FC_LA_SPEED_16G:
5161 port_speed = LPFC_LINK_SPEED_16GHZ;
5162 break;
5163 case LPFC_FC_LA_SPEED_32G:
5164 port_speed = LPFC_LINK_SPEED_32GHZ;
5165 break;
5166 case LPFC_FC_LA_SPEED_64G:
5167 port_speed = LPFC_LINK_SPEED_64GHZ;
5168 break;
5169 case LPFC_FC_LA_SPEED_128G:
5170 port_speed = LPFC_LINK_SPEED_128GHZ;
5171 break;
5172 case LPFC_FC_LA_SPEED_256G:
5173 port_speed = LPFC_LINK_SPEED_256GHZ;
5174 break;
5175 default:
5176 port_speed = 0;
5177 break;
5178 }
5179
5180 return port_speed;
5181}
5182
5183#define trunk_link_status(__idx)\
5184 bf_get(lpfc_acqe_fc_la_trunk_config_port##__idx, acqe_fc) ?\
5185 ((phba->trunk_link.link##__idx.state == LPFC_LINK_UP) ?\
5186 "Link up" : "Link down") : "NA"
5187/* Did port __idx reported an error */
5188#define trunk_port_fault(__idx)\
5189 bf_get(lpfc_acqe_fc_la_trunk_config_port##__idx, acqe_fc) ?\
5190 (port_fault & (1 << __idx) ? "YES" : "NO") : "NA"
5191
5192static void
5193lpfc_update_trunk_link_status(struct lpfc_hba *phba,
5194 struct lpfc_acqe_fc_la *acqe_fc)
5195{
5196 uint8_t port_fault = bf_get(lpfc_acqe_fc_la_trunk_linkmask, acqe_fc);
5197 uint8_t err = bf_get(lpfc_acqe_fc_la_trunk_fault, acqe_fc);
5198
5199 phba->sli4_hba.link_state.speed =
5200 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
5201 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
5202
5203 phba->sli4_hba.link_state.logical_speed =
b8e6f136 5204 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
1dc5ec24
JS
5205 /* We got FC link speed, convert to fc_linkspeed (READ_TOPOLOGY) */
5206 phba->fc_linkspeed =
5207 lpfc_async_link_speed_to_read_top(
5208 phba,
5209 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
5210
5211 if (bf_get(lpfc_acqe_fc_la_trunk_config_port0, acqe_fc)) {
5212 phba->trunk_link.link0.state =
5213 bf_get(lpfc_acqe_fc_la_trunk_link_status_port0, acqe_fc)
5214 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5215 phba->trunk_link.link0.fault = port_fault & 0x1 ? err : 0;
1dc5ec24
JS
5216 }
5217 if (bf_get(lpfc_acqe_fc_la_trunk_config_port1, acqe_fc)) {
5218 phba->trunk_link.link1.state =
5219 bf_get(lpfc_acqe_fc_la_trunk_link_status_port1, acqe_fc)
5220 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5221 phba->trunk_link.link1.fault = port_fault & 0x2 ? err : 0;
1dc5ec24
JS
5222 }
5223 if (bf_get(lpfc_acqe_fc_la_trunk_config_port2, acqe_fc)) {
5224 phba->trunk_link.link2.state =
5225 bf_get(lpfc_acqe_fc_la_trunk_link_status_port2, acqe_fc)
5226 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5227 phba->trunk_link.link2.fault = port_fault & 0x4 ? err : 0;
1dc5ec24
JS
5228 }
5229 if (bf_get(lpfc_acqe_fc_la_trunk_config_port3, acqe_fc)) {
5230 phba->trunk_link.link3.state =
5231 bf_get(lpfc_acqe_fc_la_trunk_link_status_port3, acqe_fc)
5232 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5233 phba->trunk_link.link3.fault = port_fault & 0x8 ? err : 0;
1dc5ec24
JS
5234 }
5235
372c187b 5236 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1dc5ec24
JS
5237 "2910 Async FC Trunking Event - Speed:%d\n"
5238 "\tLogical speed:%d "
5239 "port0: %s port1: %s port2: %s port3: %s\n",
5240 phba->sli4_hba.link_state.speed,
5241 phba->sli4_hba.link_state.logical_speed,
5242 trunk_link_status(0), trunk_link_status(1),
5243 trunk_link_status(2), trunk_link_status(3));
5244
5245 if (port_fault)
372c187b 5246 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1dc5ec24
JS
5247 "3202 trunk error:0x%x (%s) seen on port0:%s "
5248 /*
5249 * SLI-4: We have only 0xA error codes
5250 * defined as of now. print an appropriate
5251 * message in case driver needs to be updated.
5252 */
5253 "port1:%s port2:%s port3:%s\n", err, err > 0xA ?
5254 "UNDEFINED. update driver." : trunk_errmsg[err],
5255 trunk_port_fault(0), trunk_port_fault(1),
5256 trunk_port_fault(2), trunk_port_fault(3));
5257}
5258
5259
70f3c073
JS
5260/**
5261 * lpfc_sli4_async_fc_evt - Process the asynchronous FC link event
5262 * @phba: pointer to lpfc hba data structure.
5263 * @acqe_fc: pointer to the async fc completion queue entry.
5264 *
5265 * This routine is to handle the SLI4 asynchronous FC event. It will simply log
5266 * that the event was received and then issue a read_topology mailbox command so
5267 * that the rest of the driver will treat it the same as SLI3.
5268 **/
5269static void
5270lpfc_sli4_async_fc_evt(struct lpfc_hba *phba, struct lpfc_acqe_fc_la *acqe_fc)
5271{
5272 struct lpfc_dmabuf *mp;
5273 LPFC_MBOXQ_t *pmb;
7bdedb34
JS
5274 MAILBOX_t *mb;
5275 struct lpfc_mbx_read_top *la;
70f3c073
JS
5276 int rc;
5277
5278 if (bf_get(lpfc_trailer_type, acqe_fc) !=
5279 LPFC_FC_LA_EVENT_TYPE_FC_LINK) {
372c187b 5280 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
70f3c073
JS
5281 "2895 Non FC link Event detected.(%d)\n",
5282 bf_get(lpfc_trailer_type, acqe_fc));
5283 return;
5284 }
1dc5ec24
JS
5285
5286 if (bf_get(lpfc_acqe_fc_la_att_type, acqe_fc) ==
5287 LPFC_FC_LA_TYPE_TRUNKING_EVENT) {
5288 lpfc_update_trunk_link_status(phba, acqe_fc);
5289 return;
5290 }
5291
70f3c073
JS
5292 /* Keep the link status for extra SLI4 state machine reference */
5293 phba->sli4_hba.link_state.speed =
8b68cd52
JS
5294 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
5295 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
70f3c073
JS
5296 phba->sli4_hba.link_state.duplex = LPFC_ASYNC_LINK_DUPLEX_FULL;
5297 phba->sli4_hba.link_state.topology =
5298 bf_get(lpfc_acqe_fc_la_topology, acqe_fc);
5299 phba->sli4_hba.link_state.status =
5300 bf_get(lpfc_acqe_fc_la_att_type, acqe_fc);
5301 phba->sli4_hba.link_state.type =
5302 bf_get(lpfc_acqe_fc_la_port_type, acqe_fc);
5303 phba->sli4_hba.link_state.number =
5304 bf_get(lpfc_acqe_fc_la_port_number, acqe_fc);
5305 phba->sli4_hba.link_state.fault =
5306 bf_get(lpfc_acqe_link_fault, acqe_fc);
b8e6f136
JS
5307
5308 if (bf_get(lpfc_acqe_fc_la_att_type, acqe_fc) ==
5309 LPFC_FC_LA_TYPE_LINK_DOWN)
5310 phba->sli4_hba.link_state.logical_speed = 0;
5311 else if (!phba->sli4_hba.conf_trunk)
5312 phba->sli4_hba.link_state.logical_speed =
8b68cd52 5313 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
b8e6f136 5314
70f3c073
JS
5315 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5316 "2896 Async FC event - Speed:%dGBaud Topology:x%x "
5317 "LA Type:x%x Port Type:%d Port Number:%d Logical speed:"
5318 "%dMbps Fault:%d\n",
5319 phba->sli4_hba.link_state.speed,
5320 phba->sli4_hba.link_state.topology,
5321 phba->sli4_hba.link_state.status,
5322 phba->sli4_hba.link_state.type,
5323 phba->sli4_hba.link_state.number,
8b68cd52 5324 phba->sli4_hba.link_state.logical_speed,
70f3c073
JS
5325 phba->sli4_hba.link_state.fault);
5326 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
5327 if (!pmb) {
372c187b 5328 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
70f3c073
JS
5329 "2897 The mboxq allocation failed\n");
5330 return;
5331 }
5332 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
5333 if (!mp) {
372c187b 5334 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
70f3c073
JS
5335 "2898 The lpfc_dmabuf allocation failed\n");
5336 goto out_free_pmb;
5337 }
5338 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
5339 if (!mp->virt) {
372c187b 5340 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
70f3c073
JS
5341 "2899 The mbuf allocation failed\n");
5342 goto out_free_dmabuf;
5343 }
5344
5345 /* Cleanup any outstanding ELS commands */
5346 lpfc_els_flush_all_cmd(phba);
5347
5348 /* Block ELS IOCBs until we have done process link event */
895427bd 5349 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
70f3c073
JS
5350
5351 /* Update link event statistics */
5352 phba->sli.slistat.link_event++;
5353
5354 /* Create lpfc_handle_latt mailbox command from link ACQE */
5355 lpfc_read_topology(phba, pmb, mp);
5356 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
5357 pmb->vport = phba->pport;
5358
7bdedb34 5359 if (phba->sli4_hba.link_state.status != LPFC_FC_LA_TYPE_LINK_UP) {
ae9e28f3
JS
5360 phba->link_flag &= ~(LS_MDS_LINK_DOWN | LS_MDS_LOOPBACK);
5361
5362 switch (phba->sli4_hba.link_state.status) {
5363 case LPFC_FC_LA_TYPE_MDS_LINK_DOWN:
5364 phba->link_flag |= LS_MDS_LINK_DOWN;
5365 break;
5366 case LPFC_FC_LA_TYPE_MDS_LOOPBACK:
5367 phba->link_flag |= LS_MDS_LOOPBACK;
5368 break;
5369 default:
5370 break;
5371 }
5372
23288b78 5373 /* Initialize completion status */
7bdedb34 5374 mb = &pmb->u.mb;
23288b78
JS
5375 mb->mbxStatus = MBX_SUCCESS;
5376
5377 /* Parse port fault information field */
5378 lpfc_sli4_parse_latt_fault(phba, (void *)acqe_fc);
7bdedb34
JS
5379
5380 /* Parse and translate link attention fields */
5381 la = (struct lpfc_mbx_read_top *)&pmb->u.mb.un.varReadTop;
5382 la->eventTag = acqe_fc->event_tag;
7bdedb34 5383
aeb3c817
JS
5384 if (phba->sli4_hba.link_state.status ==
5385 LPFC_FC_LA_TYPE_UNEXP_WWPN) {
5386 bf_set(lpfc_mbx_read_top_att_type, la,
5387 LPFC_FC_LA_TYPE_UNEXP_WWPN);
5388 } else {
5389 bf_set(lpfc_mbx_read_top_att_type, la,
5390 LPFC_FC_LA_TYPE_LINK_DOWN);
5391 }
7bdedb34
JS
5392 /* Invoke the mailbox command callback function */
5393 lpfc_mbx_cmpl_read_topology(phba, pmb);
5394
5395 return;
5396 }
5397
70f3c073
JS
5398 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
5399 if (rc == MBX_NOT_FINISHED)
5400 goto out_free_dmabuf;
5401 return;
5402
5403out_free_dmabuf:
5404 kfree(mp);
5405out_free_pmb:
5406 mempool_free(pmb, phba->mbox_mem_pool);
5407}
5408
5409/**
5410 * lpfc_sli4_async_sli_evt - Process the asynchronous SLI link event
5411 * @phba: pointer to lpfc hba data structure.
fe614acd 5412 * @acqe_sli: pointer to the async SLI completion queue entry.
70f3c073
JS
5413 *
5414 * This routine is to handle the SLI4 asynchronous SLI events.
5415 **/
5416static void
5417lpfc_sli4_async_sli_evt(struct lpfc_hba *phba, struct lpfc_acqe_sli *acqe_sli)
5418{
4b8bae08 5419 char port_name;
8c1312e1 5420 char message[128];
4b8bae08 5421 uint8_t status;
946727dc 5422 uint8_t evt_type;
448193b5 5423 uint8_t operational = 0;
946727dc 5424 struct temp_event temp_event_data;
4b8bae08 5425 struct lpfc_acqe_misconfigured_event *misconfigured;
946727dc 5426 struct Scsi_Host *shost;
cd71348a
JS
5427 struct lpfc_vport **vports;
5428 int rc, i;
946727dc
JS
5429
5430 evt_type = bf_get(lpfc_trailer_type, acqe_sli);
4b8bae08 5431
448193b5 5432 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
d11ed16d
JS
5433 "2901 Async SLI event - Type:%d, Event Data: x%08x "
5434 "x%08x x%08x x%08x\n", evt_type,
448193b5 5435 acqe_sli->event_data1, acqe_sli->event_data2,
d11ed16d 5436 acqe_sli->reserved, acqe_sli->trailer);
4b8bae08
JS
5437
5438 port_name = phba->Port[0];
5439 if (port_name == 0x00)
5440 port_name = '?'; /* get port name is empty */
5441
946727dc
JS
5442 switch (evt_type) {
5443 case LPFC_SLI_EVENT_TYPE_OVER_TEMP:
5444 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
5445 temp_event_data.event_code = LPFC_THRESHOLD_TEMP;
5446 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
5447
5448 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
5449 "3190 Over Temperature:%d Celsius- Port Name %c\n",
5450 acqe_sli->event_data1, port_name);
5451
310429ef 5452 phba->sfp_warning |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
946727dc
JS
5453 shost = lpfc_shost_from_vport(phba->pport);
5454 fc_host_post_vendor_event(shost, fc_get_event_number(),
5455 sizeof(temp_event_data),
5456 (char *)&temp_event_data,
5457 SCSI_NL_VID_TYPE_PCI
5458 | PCI_VENDOR_ID_EMULEX);
5459 break;
5460 case LPFC_SLI_EVENT_TYPE_NORM_TEMP:
5461 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
5462 temp_event_data.event_code = LPFC_NORMAL_TEMP;
5463 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
5464
5465 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5466 "3191 Normal Temperature:%d Celsius - Port Name %c\n",
5467 acqe_sli->event_data1, port_name);
5468
5469 shost = lpfc_shost_from_vport(phba->pport);
5470 fc_host_post_vendor_event(shost, fc_get_event_number(),
5471 sizeof(temp_event_data),
5472 (char *)&temp_event_data,
5473 SCSI_NL_VID_TYPE_PCI
5474 | PCI_VENDOR_ID_EMULEX);
5475 break;
5476 case LPFC_SLI_EVENT_TYPE_MISCONFIGURED:
5477 misconfigured = (struct lpfc_acqe_misconfigured_event *)
4b8bae08
JS
5478 &acqe_sli->event_data1;
5479
946727dc
JS
5480 /* fetch the status for this port */
5481 switch (phba->sli4_hba.lnk_info.lnk_no) {
5482 case LPFC_LINK_NUMBER_0:
448193b5
JS
5483 status = bf_get(lpfc_sli_misconfigured_port0_state,
5484 &misconfigured->theEvent);
5485 operational = bf_get(lpfc_sli_misconfigured_port0_op,
4b8bae08 5486 &misconfigured->theEvent);
946727dc
JS
5487 break;
5488 case LPFC_LINK_NUMBER_1:
448193b5
JS
5489 status = bf_get(lpfc_sli_misconfigured_port1_state,
5490 &misconfigured->theEvent);
5491 operational = bf_get(lpfc_sli_misconfigured_port1_op,
4b8bae08 5492 &misconfigured->theEvent);
946727dc
JS
5493 break;
5494 case LPFC_LINK_NUMBER_2:
448193b5
JS
5495 status = bf_get(lpfc_sli_misconfigured_port2_state,
5496 &misconfigured->theEvent);
5497 operational = bf_get(lpfc_sli_misconfigured_port2_op,
4b8bae08 5498 &misconfigured->theEvent);
946727dc
JS
5499 break;
5500 case LPFC_LINK_NUMBER_3:
448193b5
JS
5501 status = bf_get(lpfc_sli_misconfigured_port3_state,
5502 &misconfigured->theEvent);
5503 operational = bf_get(lpfc_sli_misconfigured_port3_op,
4b8bae08 5504 &misconfigured->theEvent);
946727dc
JS
5505 break;
5506 default:
372c187b 5507 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
448193b5
JS
5508 "3296 "
5509 "LPFC_SLI_EVENT_TYPE_MISCONFIGURED "
5510 "event: Invalid link %d",
5511 phba->sli4_hba.lnk_info.lnk_no);
5512 return;
946727dc 5513 }
4b8bae08 5514
448193b5
JS
5515 /* Skip if optic state unchanged */
5516 if (phba->sli4_hba.lnk_info.optic_state == status)
5517 return;
5518
946727dc
JS
5519 switch (status) {
5520 case LPFC_SLI_EVENT_STATUS_VALID:
448193b5
JS
5521 sprintf(message, "Physical Link is functional");
5522 break;
946727dc
JS
5523 case LPFC_SLI_EVENT_STATUS_NOT_PRESENT:
5524 sprintf(message, "Optics faulted/incorrectly "
5525 "installed/not installed - Reseat optics, "
5526 "if issue not resolved, replace.");
5527 break;
5528 case LPFC_SLI_EVENT_STATUS_WRONG_TYPE:
5529 sprintf(message,
5530 "Optics of two types installed - Remove one "
5531 "optic or install matching pair of optics.");
5532 break;
5533 case LPFC_SLI_EVENT_STATUS_UNSUPPORTED:
5534 sprintf(message, "Incompatible optics - Replace with "
292098be 5535 "compatible optics for card to function.");
946727dc 5536 break;
448193b5
JS
5537 case LPFC_SLI_EVENT_STATUS_UNQUALIFIED:
5538 sprintf(message, "Unqualified optics - Replace with "
5539 "Avago optics for Warranty and Technical "
5540 "Support - Link is%s operational",
2ea259ee 5541 (operational) ? " not" : "");
448193b5
JS
5542 break;
5543 case LPFC_SLI_EVENT_STATUS_UNCERTIFIED:
5544 sprintf(message, "Uncertified optics - Replace with "
5545 "Avago-certified optics to enable link "
5546 "operation - Link is%s operational",
2ea259ee 5547 (operational) ? " not" : "");
448193b5 5548 break;
946727dc
JS
5549 default:
5550 /* firmware is reporting a status we don't know about */
5551 sprintf(message, "Unknown event status x%02x", status);
5552 break;
5553 }
cd71348a
JS
5554
5555 /* Issue READ_CONFIG mbox command to refresh supported speeds */
5556 rc = lpfc_sli4_read_config(phba);
3952e91f 5557 if (rc) {
cd71348a 5558 phba->lmt = 0;
372c187b
DK
5559 lpfc_printf_log(phba, KERN_ERR,
5560 LOG_TRACE_EVENT,
cd71348a 5561 "3194 Unable to retrieve supported "
3952e91f 5562 "speeds, rc = 0x%x\n", rc);
cd71348a
JS
5563 }
5564 vports = lpfc_create_vport_work_array(phba);
5565 if (vports != NULL) {
5566 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
5567 i++) {
5568 shost = lpfc_shost_from_vport(vports[i]);
5569 lpfc_host_supported_speeds_set(shost);
5570 }
5571 }
5572 lpfc_destroy_vport_work_array(phba, vports);
5573
448193b5 5574 phba->sli4_hba.lnk_info.optic_state = status;
946727dc 5575 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
448193b5 5576 "3176 Port Name %c %s\n", port_name, message);
946727dc
JS
5577 break;
5578 case LPFC_SLI_EVENT_TYPE_REMOTE_DPORT:
5579 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5580 "3192 Remote DPort Test Initiated - "
5581 "Event Data1:x%08x Event Data2: x%08x\n",
5582 acqe_sli->event_data1, acqe_sli->event_data2);
4b8bae08 5583 break;
e7d85952
JS
5584 case LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN:
5585 /* Misconfigured WWN. Reports that the SLI Port is configured
5586 * to use FA-WWN, but the attached device doesn’t support it.
5587 * No driver action is required.
5588 * Event Data1 - N.A, Event Data2 - N.A
5589 */
5590 lpfc_log_msg(phba, KERN_WARNING, LOG_SLI,
5591 "2699 Misconfigured FA-WWN - Attached device does "
5592 "not support FA-WWN\n");
5593 break;
d11ed16d
JS
5594 case LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE:
5595 /* EEPROM failure. No driver action is required */
5596 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
5597 "2518 EEPROM failure - "
5598 "Event Data1: x%08x Event Data2: x%08x\n",
5599 acqe_sli->event_data1, acqe_sli->event_data2);
5600 break;
4b8bae08 5601 default:
946727dc 5602 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
d11ed16d 5603 "3193 Unrecognized SLI event, type: 0x%x",
946727dc 5604 evt_type);
4b8bae08
JS
5605 break;
5606 }
70f3c073
JS
5607}
5608
fc2b989b
JS
5609/**
5610 * lpfc_sli4_perform_vport_cvl - Perform clear virtual link on a vport
5611 * @vport: pointer to vport data structure.
5612 *
5613 * This routine is to perform Clear Virtual Link (CVL) on a vport in
5614 * response to a CVL event.
5615 *
5616 * Return the pointer to the ndlp with the vport if successful, otherwise
5617 * return NULL.
5618 **/
5619static struct lpfc_nodelist *
5620lpfc_sli4_perform_vport_cvl(struct lpfc_vport *vport)
5621{
5622 struct lpfc_nodelist *ndlp;
5623 struct Scsi_Host *shost;
5624 struct lpfc_hba *phba;
5625
5626 if (!vport)
5627 return NULL;
fc2b989b
JS
5628 phba = vport->phba;
5629 if (!phba)
5630 return NULL;
78730cfe
JS
5631 ndlp = lpfc_findnode_did(vport, Fabric_DID);
5632 if (!ndlp) {
5633 /* Cannot find existing Fabric ndlp, so allocate a new one */
9d3d340d 5634 ndlp = lpfc_nlp_init(vport, Fabric_DID);
78730cfe
JS
5635 if (!ndlp)
5636 return 0;
78730cfe
JS
5637 /* Set the node type */
5638 ndlp->nlp_type |= NLP_FABRIC;
5639 /* Put ndlp onto node list */
5640 lpfc_enqueue_node(vport, ndlp);
78730cfe 5641 }
63e801ce
JS
5642 if ((phba->pport->port_state < LPFC_FLOGI) &&
5643 (phba->pport->port_state != LPFC_VPORT_FAILED))
fc2b989b
JS
5644 return NULL;
5645 /* If virtual link is not yet instantiated ignore CVL */
63e801ce
JS
5646 if ((vport != phba->pport) && (vport->port_state < LPFC_FDISC)
5647 && (vport->port_state != LPFC_VPORT_FAILED))
fc2b989b
JS
5648 return NULL;
5649 shost = lpfc_shost_from_vport(vport);
5650 if (!shost)
5651 return NULL;
5652 lpfc_linkdown_port(vport);
5653 lpfc_cleanup_pending_mbox(vport);
5654 spin_lock_irq(shost->host_lock);
5655 vport->fc_flag |= FC_VPORT_CVL_RCVD;
5656 spin_unlock_irq(shost->host_lock);
5657
5658 return ndlp;
5659}
5660
5661/**
5662 * lpfc_sli4_perform_all_vport_cvl - Perform clear virtual link on all vports
fe614acd 5663 * @phba: pointer to lpfc hba data structure.
fc2b989b
JS
5664 *
5665 * This routine is to perform Clear Virtual Link (CVL) on all vports in
5666 * response to a FCF dead event.
5667 **/
5668static void
5669lpfc_sli4_perform_all_vport_cvl(struct lpfc_hba *phba)
5670{
5671 struct lpfc_vport **vports;
5672 int i;
5673
5674 vports = lpfc_create_vport_work_array(phba);
5675 if (vports)
5676 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
5677 lpfc_sli4_perform_vport_cvl(vports[i]);
5678 lpfc_destroy_vport_work_array(phba, vports);
5679}
5680
da0436e9 5681/**
76a95d75 5682 * lpfc_sli4_async_fip_evt - Process the asynchronous FCoE FIP event
da0436e9 5683 * @phba: pointer to lpfc hba data structure.
fe614acd 5684 * @acqe_fip: pointer to the async fcoe completion queue entry.
da0436e9
JS
5685 *
5686 * This routine is to handle the SLI4 asynchronous fcoe event.
5687 **/
5688static void
76a95d75 5689lpfc_sli4_async_fip_evt(struct lpfc_hba *phba,
70f3c073 5690 struct lpfc_acqe_fip *acqe_fip)
da0436e9 5691{
70f3c073 5692 uint8_t event_type = bf_get(lpfc_trailer_type, acqe_fip);
da0436e9 5693 int rc;
6669f9bb
JS
5694 struct lpfc_vport *vport;
5695 struct lpfc_nodelist *ndlp;
695a814e
JS
5696 int active_vlink_present;
5697 struct lpfc_vport **vports;
5698 int i;
da0436e9 5699
70f3c073
JS
5700 phba->fc_eventTag = acqe_fip->event_tag;
5701 phba->fcoe_eventtag = acqe_fip->event_tag;
da0436e9 5702 switch (event_type) {
70f3c073
JS
5703 case LPFC_FIP_EVENT_TYPE_NEW_FCF:
5704 case LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD:
5705 if (event_type == LPFC_FIP_EVENT_TYPE_NEW_FCF)
372c187b 5706 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
a93ff37a
JS
5707 "2546 New FCF event, evt_tag:x%x, "
5708 "index:x%x\n",
70f3c073
JS
5709 acqe_fip->event_tag,
5710 acqe_fip->index);
999d813f
JS
5711 else
5712 lpfc_printf_log(phba, KERN_WARNING, LOG_FIP |
5713 LOG_DISCOVERY,
a93ff37a
JS
5714 "2788 FCF param modified event, "
5715 "evt_tag:x%x, index:x%x\n",
70f3c073
JS
5716 acqe_fip->event_tag,
5717 acqe_fip->index);
38b92ef8 5718 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
0c9ab6f5
JS
5719 /*
5720 * During period of FCF discovery, read the FCF
5721 * table record indexed by the event to update
a93ff37a 5722 * FCF roundrobin failover eligible FCF bmask.
0c9ab6f5
JS
5723 */
5724 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
5725 LOG_DISCOVERY,
a93ff37a
JS
5726 "2779 Read FCF (x%x) for updating "
5727 "roundrobin FCF failover bmask\n",
70f3c073
JS
5728 acqe_fip->index);
5729 rc = lpfc_sli4_read_fcf_rec(phba, acqe_fip->index);
0c9ab6f5 5730 }
38b92ef8
JS
5731
5732 /* If the FCF discovery is in progress, do nothing. */
3804dc84 5733 spin_lock_irq(&phba->hbalock);
a93ff37a 5734 if (phba->hba_flag & FCF_TS_INPROG) {
38b92ef8
JS
5735 spin_unlock_irq(&phba->hbalock);
5736 break;
5737 }
5738 /* If fast FCF failover rescan event is pending, do nothing */
036cad1f 5739 if (phba->fcf.fcf_flag & (FCF_REDISC_EVT | FCF_REDISC_PEND)) {
38b92ef8
JS
5740 spin_unlock_irq(&phba->hbalock);
5741 break;
5742 }
5743
c2b9712e
JS
5744 /* If the FCF has been in discovered state, do nothing. */
5745 if (phba->fcf.fcf_flag & FCF_SCAN_DONE) {
3804dc84
JS
5746 spin_unlock_irq(&phba->hbalock);
5747 break;
5748 }
5749 spin_unlock_irq(&phba->hbalock);
38b92ef8 5750
0c9ab6f5
JS
5751 /* Otherwise, scan the entire FCF table and re-discover SAN */
5752 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
a93ff37a
JS
5753 "2770 Start FCF table scan per async FCF "
5754 "event, evt_tag:x%x, index:x%x\n",
70f3c073 5755 acqe_fip->event_tag, acqe_fip->index);
0c9ab6f5
JS
5756 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba,
5757 LPFC_FCOE_FCF_GET_FIRST);
da0436e9 5758 if (rc)
372c187b 5759 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0c9ab6f5 5760 "2547 Issue FCF scan read FCF mailbox "
a93ff37a 5761 "command failed (x%x)\n", rc);
da0436e9
JS
5762 break;
5763
70f3c073 5764 case LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL:
372c187b
DK
5765 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5766 "2548 FCF Table full count 0x%x tag 0x%x\n",
5767 bf_get(lpfc_acqe_fip_fcf_count, acqe_fip),
5768 acqe_fip->event_tag);
da0436e9
JS
5769 break;
5770
70f3c073 5771 case LPFC_FIP_EVENT_TYPE_FCF_DEAD:
80c17849 5772 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
372c187b
DK
5773 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5774 "2549 FCF (x%x) disconnected from network, "
5775 "tag:x%x\n", acqe_fip->index,
5776 acqe_fip->event_tag);
38b92ef8
JS
5777 /*
5778 * If we are in the middle of FCF failover process, clear
5779 * the corresponding FCF bit in the roundrobin bitmap.
da0436e9 5780 */
fc2b989b 5781 spin_lock_irq(&phba->hbalock);
a1cadfef
JS
5782 if ((phba->fcf.fcf_flag & FCF_DISCOVERY) &&
5783 (phba->fcf.current_rec.fcf_indx != acqe_fip->index)) {
fc2b989b 5784 spin_unlock_irq(&phba->hbalock);
0c9ab6f5 5785 /* Update FLOGI FCF failover eligible FCF bmask */
70f3c073 5786 lpfc_sli4_fcf_rr_index_clear(phba, acqe_fip->index);
fc2b989b
JS
5787 break;
5788 }
38b92ef8
JS
5789 spin_unlock_irq(&phba->hbalock);
5790
5791 /* If the event is not for currently used fcf do nothing */
70f3c073 5792 if (phba->fcf.current_rec.fcf_indx != acqe_fip->index)
38b92ef8
JS
5793 break;
5794
5795 /*
5796 * Otherwise, request the port to rediscover the entire FCF
5797 * table for a fast recovery from case that the current FCF
5798 * is no longer valid as we are not in the middle of FCF
5799 * failover process already.
5800 */
c2b9712e
JS
5801 spin_lock_irq(&phba->hbalock);
5802 /* Mark the fast failover process in progress */
5803 phba->fcf.fcf_flag |= FCF_DEAD_DISC;
5804 spin_unlock_irq(&phba->hbalock);
5805
5806 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
5807 "2771 Start FCF fast failover process due to "
5808 "FCF DEAD event: evt_tag:x%x, fcf_index:x%x "
5809 "\n", acqe_fip->event_tag, acqe_fip->index);
5810 rc = lpfc_sli4_redisc_fcf_table(phba);
5811 if (rc) {
5812 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
372c187b 5813 LOG_TRACE_EVENT,
7afc0ce9 5814 "2772 Issue FCF rediscover mailbox "
c2b9712e
JS
5815 "command failed, fail through to FCF "
5816 "dead event\n");
5817 spin_lock_irq(&phba->hbalock);
5818 phba->fcf.fcf_flag &= ~FCF_DEAD_DISC;
5819 spin_unlock_irq(&phba->hbalock);
5820 /*
5821 * Last resort will fail over by treating this
5822 * as a link down to FCF registration.
5823 */
5824 lpfc_sli4_fcf_dead_failthrough(phba);
5825 } else {
5826 /* Reset FCF roundrobin bmask for new discovery */
5827 lpfc_sli4_clear_fcf_rr_bmask(phba);
5828 /*
5829 * Handling fast FCF failover to a DEAD FCF event is
5830 * considered equalivant to receiving CVL to all vports.
5831 */
5832 lpfc_sli4_perform_all_vport_cvl(phba);
5833 }
da0436e9 5834 break;
70f3c073 5835 case LPFC_FIP_EVENT_TYPE_CVL:
80c17849 5836 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
372c187b
DK
5837 lpfc_printf_log(phba, KERN_ERR,
5838 LOG_TRACE_EVENT,
6669f9bb 5839 "2718 Clear Virtual Link Received for VPI 0x%x"
70f3c073 5840 " tag 0x%x\n", acqe_fip->index, acqe_fip->event_tag);
6d368e53 5841
6669f9bb 5842 vport = lpfc_find_vport_by_vpid(phba,
5248a749 5843 acqe_fip->index);
fc2b989b 5844 ndlp = lpfc_sli4_perform_vport_cvl(vport);
6669f9bb
JS
5845 if (!ndlp)
5846 break;
695a814e
JS
5847 active_vlink_present = 0;
5848
5849 vports = lpfc_create_vport_work_array(phba);
5850 if (vports) {
5851 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
5852 i++) {
5853 if ((!(vports[i]->fc_flag &
5854 FC_VPORT_CVL_RCVD)) &&
5855 (vports[i]->port_state > LPFC_FDISC)) {
5856 active_vlink_present = 1;
5857 break;
5858 }
5859 }
5860 lpfc_destroy_vport_work_array(phba, vports);
5861 }
5862
cc82355a
JS
5863 /*
5864 * Don't re-instantiate if vport is marked for deletion.
5865 * If we are here first then vport_delete is going to wait
5866 * for discovery to complete.
5867 */
5868 if (!(vport->load_flag & FC_UNLOADING) &&
5869 active_vlink_present) {
695a814e
JS
5870 /*
5871 * If there are other active VLinks present,
5872 * re-instantiate the Vlink using FDISC.
5873 */
256ec0d0
JS
5874 mod_timer(&ndlp->nlp_delayfunc,
5875 jiffies + msecs_to_jiffies(1000));
c6adba15 5876 spin_lock_irq(&ndlp->lock);
6669f9bb 5877 ndlp->nlp_flag |= NLP_DELAY_TMO;
c6adba15 5878 spin_unlock_irq(&ndlp->lock);
695a814e
JS
5879 ndlp->nlp_last_elscmd = ELS_CMD_FDISC;
5880 vport->port_state = LPFC_FDISC;
5881 } else {
ecfd03c6
JS
5882 /*
5883 * Otherwise, we request port to rediscover
5884 * the entire FCF table for a fast recovery
5885 * from possible case that the current FCF
0c9ab6f5
JS
5886 * is no longer valid if we are not already
5887 * in the FCF failover process.
ecfd03c6 5888 */
fc2b989b 5889 spin_lock_irq(&phba->hbalock);
0c9ab6f5 5890 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
fc2b989b
JS
5891 spin_unlock_irq(&phba->hbalock);
5892 break;
5893 }
5894 /* Mark the fast failover process in progress */
0c9ab6f5 5895 phba->fcf.fcf_flag |= FCF_ACVL_DISC;
fc2b989b 5896 spin_unlock_irq(&phba->hbalock);
0c9ab6f5
JS
5897 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
5898 LOG_DISCOVERY,
a93ff37a 5899 "2773 Start FCF failover per CVL, "
70f3c073 5900 "evt_tag:x%x\n", acqe_fip->event_tag);
ecfd03c6 5901 rc = lpfc_sli4_redisc_fcf_table(phba);
fc2b989b 5902 if (rc) {
0c9ab6f5 5903 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
372c187b 5904 LOG_TRACE_EVENT,
0c9ab6f5 5905 "2774 Issue FCF rediscover "
7afc0ce9 5906 "mailbox command failed, "
0c9ab6f5 5907 "through to CVL event\n");
fc2b989b 5908 spin_lock_irq(&phba->hbalock);
0c9ab6f5 5909 phba->fcf.fcf_flag &= ~FCF_ACVL_DISC;
fc2b989b 5910 spin_unlock_irq(&phba->hbalock);
ecfd03c6
JS
5911 /*
5912 * Last resort will be re-try on the
5913 * the current registered FCF entry.
5914 */
5915 lpfc_retry_pport_discovery(phba);
38b92ef8
JS
5916 } else
5917 /*
5918 * Reset FCF roundrobin bmask for new
5919 * discovery.
5920 */
7d791df7 5921 lpfc_sli4_clear_fcf_rr_bmask(phba);
6669f9bb
JS
5922 }
5923 break;
da0436e9 5924 default:
372c187b
DK
5925 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5926 "0288 Unknown FCoE event type 0x%x event tag "
5927 "0x%x\n", event_type, acqe_fip->event_tag);
da0436e9
JS
5928 break;
5929 }
5930}
5931
5932/**
5933 * lpfc_sli4_async_dcbx_evt - Process the asynchronous dcbx event
5934 * @phba: pointer to lpfc hba data structure.
fe614acd 5935 * @acqe_dcbx: pointer to the async dcbx completion queue entry.
da0436e9
JS
5936 *
5937 * This routine is to handle the SLI4 asynchronous dcbx event.
5938 **/
5939static void
5940lpfc_sli4_async_dcbx_evt(struct lpfc_hba *phba,
5941 struct lpfc_acqe_dcbx *acqe_dcbx)
5942{
4d9ab994 5943 phba->fc_eventTag = acqe_dcbx->event_tag;
372c187b 5944 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
5945 "0290 The SLI4 DCBX asynchronous event is not "
5946 "handled yet\n");
5947}
5948
b19a061a
JS
5949/**
5950 * lpfc_sli4_async_grp5_evt - Process the asynchronous group5 event
5951 * @phba: pointer to lpfc hba data structure.
fe614acd 5952 * @acqe_grp5: pointer to the async grp5 completion queue entry.
b19a061a
JS
5953 *
5954 * This routine is to handle the SLI4 asynchronous grp5 event. A grp5 event
5955 * is an asynchronous notified of a logical link speed change. The Port
5956 * reports the logical link speed in units of 10Mbps.
5957 **/
5958static void
5959lpfc_sli4_async_grp5_evt(struct lpfc_hba *phba,
5960 struct lpfc_acqe_grp5 *acqe_grp5)
5961{
5962 uint16_t prev_ll_spd;
5963
5964 phba->fc_eventTag = acqe_grp5->event_tag;
5965 phba->fcoe_eventtag = acqe_grp5->event_tag;
5966 prev_ll_spd = phba->sli4_hba.link_state.logical_speed;
5967 phba->sli4_hba.link_state.logical_speed =
8b68cd52 5968 (bf_get(lpfc_acqe_grp5_llink_spd, acqe_grp5)) * 10;
b19a061a
JS
5969 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5970 "2789 GRP5 Async Event: Updating logical link speed "
8b68cd52
JS
5971 "from %dMbps to %dMbps\n", prev_ll_spd,
5972 phba->sli4_hba.link_state.logical_speed);
b19a061a
JS
5973}
5974
da0436e9
JS
5975/**
5976 * lpfc_sli4_async_event_proc - Process all the pending asynchronous event
5977 * @phba: pointer to lpfc hba data structure.
5978 *
5979 * This routine is invoked by the worker thread to process all the pending
5980 * SLI4 asynchronous events.
5981 **/
5982void lpfc_sli4_async_event_proc(struct lpfc_hba *phba)
5983{
5984 struct lpfc_cq_event *cq_event;
e7dab164 5985 unsigned long iflags;
da0436e9
JS
5986
5987 /* First, declare the async event has been handled */
e7dab164 5988 spin_lock_irqsave(&phba->hbalock, iflags);
da0436e9 5989 phba->hba_flag &= ~ASYNC_EVENT;
e7dab164
JS
5990 spin_unlock_irqrestore(&phba->hbalock, iflags);
5991
da0436e9 5992 /* Now, handle all the async events */
e7dab164 5993 spin_lock_irqsave(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9 5994 while (!list_empty(&phba->sli4_hba.sp_asynce_work_queue)) {
da0436e9
JS
5995 list_remove_head(&phba->sli4_hba.sp_asynce_work_queue,
5996 cq_event, struct lpfc_cq_event, list);
e7dab164
JS
5997 spin_unlock_irqrestore(&phba->sli4_hba.asynce_list_lock,
5998 iflags);
5999
da0436e9
JS
6000 /* Process the asynchronous event */
6001 switch (bf_get(lpfc_trailer_code, &cq_event->cqe.mcqe_cmpl)) {
6002 case LPFC_TRAILER_CODE_LINK:
6003 lpfc_sli4_async_link_evt(phba,
6004 &cq_event->cqe.acqe_link);
6005 break;
6006 case LPFC_TRAILER_CODE_FCOE:
70f3c073 6007 lpfc_sli4_async_fip_evt(phba, &cq_event->cqe.acqe_fip);
da0436e9
JS
6008 break;
6009 case LPFC_TRAILER_CODE_DCBX:
6010 lpfc_sli4_async_dcbx_evt(phba,
6011 &cq_event->cqe.acqe_dcbx);
6012 break;
b19a061a
JS
6013 case LPFC_TRAILER_CODE_GRP5:
6014 lpfc_sli4_async_grp5_evt(phba,
6015 &cq_event->cqe.acqe_grp5);
6016 break;
70f3c073
JS
6017 case LPFC_TRAILER_CODE_FC:
6018 lpfc_sli4_async_fc_evt(phba, &cq_event->cqe.acqe_fc);
6019 break;
6020 case LPFC_TRAILER_CODE_SLI:
6021 lpfc_sli4_async_sli_evt(phba, &cq_event->cqe.acqe_sli);
6022 break;
da0436e9 6023 default:
372c187b
DK
6024 lpfc_printf_log(phba, KERN_ERR,
6025 LOG_TRACE_EVENT,
291c2548 6026 "1804 Invalid asynchronous event code: "
da0436e9
JS
6027 "x%x\n", bf_get(lpfc_trailer_code,
6028 &cq_event->cqe.mcqe_cmpl));
6029 break;
6030 }
e7dab164 6031
da0436e9
JS
6032 /* Free the completion event processed to the free pool */
6033 lpfc_sli4_cq_event_release(phba, cq_event);
e7dab164 6034 spin_lock_irqsave(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9 6035 }
e7dab164 6036 spin_unlock_irqrestore(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9
JS
6037}
6038
ecfd03c6
JS
6039/**
6040 * lpfc_sli4_fcf_redisc_event_proc - Process fcf table rediscovery event
6041 * @phba: pointer to lpfc hba data structure.
6042 *
6043 * This routine is invoked by the worker thread to process FCF table
6044 * rediscovery pending completion event.
6045 **/
6046void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *phba)
6047{
6048 int rc;
6049
6050 spin_lock_irq(&phba->hbalock);
6051 /* Clear FCF rediscovery timeout event */
6052 phba->fcf.fcf_flag &= ~FCF_REDISC_EVT;
6053 /* Clear driver fast failover FCF record flag */
6054 phba->fcf.failover_rec.flag = 0;
6055 /* Set state for FCF fast failover */
6056 phba->fcf.fcf_flag |= FCF_REDISC_FOV;
6057 spin_unlock_irq(&phba->hbalock);
6058
6059 /* Scan FCF table from the first entry to re-discover SAN */
0c9ab6f5 6060 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
a93ff37a 6061 "2777 Start post-quiescent FCF table scan\n");
0c9ab6f5 6062 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba, LPFC_FCOE_FCF_GET_FIRST);
ecfd03c6 6063 if (rc)
372c187b 6064 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0c9ab6f5
JS
6065 "2747 Issue FCF scan read FCF mailbox "
6066 "command failed 0x%x\n", rc);
ecfd03c6
JS
6067}
6068
da0436e9
JS
6069/**
6070 * lpfc_api_table_setup - Set up per hba pci-device group func api jump table
6071 * @phba: pointer to lpfc hba data structure.
6072 * @dev_grp: The HBA PCI-Device group number.
6073 *
6074 * This routine is invoked to set up the per HBA PCI-Device group function
6075 * API jump table entries.
6076 *
6077 * Return: 0 if success, otherwise -ENODEV
6078 **/
6079int
6080lpfc_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
6081{
6082 int rc;
6083
6084 /* Set up lpfc PCI-device group */
6085 phba->pci_dev_grp = dev_grp;
6086
6087 /* The LPFC_PCI_DEV_OC uses SLI4 */
6088 if (dev_grp == LPFC_PCI_DEV_OC)
6089 phba->sli_rev = LPFC_SLI_REV4;
6090
6091 /* Set up device INIT API function jump table */
6092 rc = lpfc_init_api_table_setup(phba, dev_grp);
6093 if (rc)
6094 return -ENODEV;
6095 /* Set up SCSI API function jump table */
6096 rc = lpfc_scsi_api_table_setup(phba, dev_grp);
6097 if (rc)
6098 return -ENODEV;
6099 /* Set up SLI API function jump table */
6100 rc = lpfc_sli_api_table_setup(phba, dev_grp);
6101 if (rc)
6102 return -ENODEV;
6103 /* Set up MBOX API function jump table */
6104 rc = lpfc_mbox_api_table_setup(phba, dev_grp);
6105 if (rc)
6106 return -ENODEV;
6107
6108 return 0;
5b75da2f
JS
6109}
6110
6111/**
3621a710 6112 * lpfc_log_intr_mode - Log the active interrupt mode
5b75da2f
JS
6113 * @phba: pointer to lpfc hba data structure.
6114 * @intr_mode: active interrupt mode adopted.
6115 *
6116 * This routine it invoked to log the currently used active interrupt mode
6117 * to the device.
3772a991
JS
6118 **/
6119static void lpfc_log_intr_mode(struct lpfc_hba *phba, uint32_t intr_mode)
5b75da2f
JS
6120{
6121 switch (intr_mode) {
6122 case 0:
6123 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
6124 "0470 Enable INTx interrupt mode.\n");
6125 break;
6126 case 1:
6127 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
6128 "0481 Enabled MSI interrupt mode.\n");
6129 break;
6130 case 2:
6131 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
6132 "0480 Enabled MSI-X interrupt mode.\n");
6133 break;
6134 default:
372c187b 6135 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5b75da2f
JS
6136 "0482 Illegal interrupt mode.\n");
6137 break;
6138 }
6139 return;
6140}
6141
5b75da2f 6142/**
3772a991 6143 * lpfc_enable_pci_dev - Enable a generic PCI device.
5b75da2f
JS
6144 * @phba: pointer to lpfc hba data structure.
6145 *
3772a991
JS
6146 * This routine is invoked to enable the PCI device that is common to all
6147 * PCI devices.
5b75da2f
JS
6148 *
6149 * Return codes
af901ca1 6150 * 0 - successful
3772a991 6151 * other values - error
5b75da2f 6152 **/
3772a991
JS
6153static int
6154lpfc_enable_pci_dev(struct lpfc_hba *phba)
5b75da2f 6155{
3772a991 6156 struct pci_dev *pdev;
5b75da2f 6157
3772a991
JS
6158 /* Obtain PCI device reference */
6159 if (!phba->pcidev)
6160 goto out_error;
6161 else
6162 pdev = phba->pcidev;
3772a991
JS
6163 /* Enable PCI device */
6164 if (pci_enable_device_mem(pdev))
6165 goto out_error;
6166 /* Request PCI resource for the device */
e0c0483c 6167 if (pci_request_mem_regions(pdev, LPFC_DRIVER_NAME))
3772a991
JS
6168 goto out_disable_device;
6169 /* Set up device as PCI master and save state for EEH */
6170 pci_set_master(pdev);
6171 pci_try_set_mwi(pdev);
6172 pci_save_state(pdev);
5b75da2f 6173
0558056c 6174 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
453193e0 6175 if (pci_is_pcie(pdev))
0558056c
JS
6176 pdev->needs_freset = 1;
6177
3772a991 6178 return 0;
5b75da2f 6179
3772a991
JS
6180out_disable_device:
6181 pci_disable_device(pdev);
6182out_error:
372c187b 6183 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e0c0483c 6184 "1401 Failed to enable pci device\n");
3772a991 6185 return -ENODEV;
5b75da2f
JS
6186}
6187
6188/**
3772a991 6189 * lpfc_disable_pci_dev - Disable a generic PCI device.
5b75da2f
JS
6190 * @phba: pointer to lpfc hba data structure.
6191 *
3772a991
JS
6192 * This routine is invoked to disable the PCI device that is common to all
6193 * PCI devices.
5b75da2f
JS
6194 **/
6195static void
3772a991 6196lpfc_disable_pci_dev(struct lpfc_hba *phba)
5b75da2f 6197{
3772a991 6198 struct pci_dev *pdev;
5b75da2f 6199
3772a991
JS
6200 /* Obtain PCI device reference */
6201 if (!phba->pcidev)
6202 return;
6203 else
6204 pdev = phba->pcidev;
3772a991 6205 /* Release PCI resource and disable PCI device */
e0c0483c 6206 pci_release_mem_regions(pdev);
3772a991 6207 pci_disable_device(pdev);
5b75da2f
JS
6208
6209 return;
6210}
6211
e59058c4 6212/**
3772a991
JS
6213 * lpfc_reset_hba - Reset a hba
6214 * @phba: pointer to lpfc hba data structure.
e59058c4 6215 *
3772a991
JS
6216 * This routine is invoked to reset a hba device. It brings the HBA
6217 * offline, performs a board restart, and then brings the board back
6218 * online. The lpfc_offline calls lpfc_sli_hba_down which will clean up
6219 * on outstanding mailbox commands.
e59058c4 6220 **/
3772a991
JS
6221void
6222lpfc_reset_hba(struct lpfc_hba *phba)
dea3101e 6223{
3772a991
JS
6224 /* If resets are disabled then set error state and return. */
6225 if (!phba->cfg_enable_hba_reset) {
6226 phba->link_state = LPFC_HBA_ERROR;
6227 return;
6228 }
9ec58ec7
JS
6229
6230 /* If not LPFC_SLI_ACTIVE, force all IO to be flushed */
6231 if (phba->sli.sli_flag & LPFC_SLI_ACTIVE) {
ee62021a 6232 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
9ec58ec7 6233 } else {
ee62021a 6234 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
9ec58ec7
JS
6235 lpfc_sli_flush_io_rings(phba);
6236 }
3772a991
JS
6237 lpfc_offline(phba);
6238 lpfc_sli_brdrestart(phba);
6239 lpfc_online(phba);
6240 lpfc_unblock_mgmt_io(phba);
6241}
dea3101e 6242
0a96e975
JS
6243/**
6244 * lpfc_sli_sriov_nr_virtfn_get - Get the number of sr-iov virtual functions
6245 * @phba: pointer to lpfc hba data structure.
6246 *
6247 * This function enables the PCI SR-IOV virtual functions to a physical
6248 * function. It invokes the PCI SR-IOV api with the @nr_vfn provided to
6249 * enable the number of virtual functions to the physical function. As
6250 * not all devices support SR-IOV, the return code from the pci_enable_sriov()
6251 * API call does not considered as an error condition for most of the device.
6252 **/
6253uint16_t
6254lpfc_sli_sriov_nr_virtfn_get(struct lpfc_hba *phba)
6255{
6256 struct pci_dev *pdev = phba->pcidev;
6257 uint16_t nr_virtfn;
6258 int pos;
6259
0a96e975
JS
6260 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6261 if (pos == 0)
6262 return 0;
6263
6264 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, &nr_virtfn);
6265 return nr_virtfn;
6266}
6267
912e3acd
JS
6268/**
6269 * lpfc_sli_probe_sriov_nr_virtfn - Enable a number of sr-iov virtual functions
6270 * @phba: pointer to lpfc hba data structure.
6271 * @nr_vfn: number of virtual functions to be enabled.
6272 *
6273 * This function enables the PCI SR-IOV virtual functions to a physical
6274 * function. It invokes the PCI SR-IOV api with the @nr_vfn provided to
6275 * enable the number of virtual functions to the physical function. As
6276 * not all devices support SR-IOV, the return code from the pci_enable_sriov()
6277 * API call does not considered as an error condition for most of the device.
6278 **/
6279int
6280lpfc_sli_probe_sriov_nr_virtfn(struct lpfc_hba *phba, int nr_vfn)
6281{
6282 struct pci_dev *pdev = phba->pcidev;
0a96e975 6283 uint16_t max_nr_vfn;
912e3acd
JS
6284 int rc;
6285
0a96e975
JS
6286 max_nr_vfn = lpfc_sli_sriov_nr_virtfn_get(phba);
6287 if (nr_vfn > max_nr_vfn) {
372c187b 6288 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a96e975
JS
6289 "3057 Requested vfs (%d) greater than "
6290 "supported vfs (%d)", nr_vfn, max_nr_vfn);
6291 return -EINVAL;
6292 }
6293
912e3acd
JS
6294 rc = pci_enable_sriov(pdev, nr_vfn);
6295 if (rc) {
6296 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6297 "2806 Failed to enable sriov on this device "
6298 "with vfn number nr_vf:%d, rc:%d\n",
6299 nr_vfn, rc);
6300 } else
6301 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6302 "2807 Successful enable sriov on this device "
6303 "with vfn number nr_vf:%d\n", nr_vfn);
6304 return rc;
6305}
6306
3772a991 6307/**
895427bd 6308 * lpfc_setup_driver_resource_phase1 - Phase1 etup driver internal resources.
3772a991
JS
6309 * @phba: pointer to lpfc hba data structure.
6310 *
895427bd
JS
6311 * This routine is invoked to set up the driver internal resources before the
6312 * device specific resource setup to support the HBA device it attached to.
3772a991
JS
6313 *
6314 * Return codes
895427bd
JS
6315 * 0 - successful
6316 * other values - error
3772a991
JS
6317 **/
6318static int
895427bd 6319lpfc_setup_driver_resource_phase1(struct lpfc_hba *phba)
3772a991 6320{
895427bd 6321 struct lpfc_sli *psli = &phba->sli;
dea3101e 6322
2e0fef85 6323 /*
895427bd 6324 * Driver resources common to all SLI revisions
2e0fef85 6325 */
895427bd 6326 atomic_set(&phba->fast_event_count, 0);
372c187b
DK
6327 atomic_set(&phba->dbg_log_idx, 0);
6328 atomic_set(&phba->dbg_log_cnt, 0);
6329 atomic_set(&phba->dbg_log_dmping, 0);
895427bd 6330 spin_lock_init(&phba->hbalock);
dea3101e 6331
523128e5
JS
6332 /* Initialize port_list spinlock */
6333 spin_lock_init(&phba->port_list_lock);
895427bd 6334 INIT_LIST_HEAD(&phba->port_list);
523128e5 6335
895427bd
JS
6336 INIT_LIST_HEAD(&phba->work_list);
6337 init_waitqueue_head(&phba->wait_4_mlo_m_q);
6338
6339 /* Initialize the wait queue head for the kernel thread */
6340 init_waitqueue_head(&phba->work_waitq);
6341
6342 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
f358dd0c 6343 "1403 Protocols supported %s %s %s\n",
895427bd
JS
6344 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) ?
6345 "SCSI" : " "),
6346 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) ?
f358dd0c
JS
6347 "NVME" : " "),
6348 (phba->nvmet_support ? "NVMET" : " "));
895427bd 6349
0794d601
JS
6350 /* Initialize the IO buffer list used by driver for SLI3 SCSI */
6351 spin_lock_init(&phba->scsi_buf_list_get_lock);
6352 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_get);
6353 spin_lock_init(&phba->scsi_buf_list_put_lock);
6354 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_put);
895427bd
JS
6355
6356 /* Initialize the fabric iocb list */
6357 INIT_LIST_HEAD(&phba->fabric_iocb_list);
6358
6359 /* Initialize list to save ELS buffers */
6360 INIT_LIST_HEAD(&phba->elsbuf);
6361
6362 /* Initialize FCF connection rec list */
6363 INIT_LIST_HEAD(&phba->fcf_conn_rec_list);
6364
6365 /* Initialize OAS configuration list */
6366 spin_lock_init(&phba->devicelock);
6367 INIT_LIST_HEAD(&phba->luns);
858c9f6c 6368
3772a991 6369 /* MBOX heartbeat timer */
f22eb4d3 6370 timer_setup(&psli->mbox_tmo, lpfc_mbox_timeout, 0);
3772a991 6371 /* Fabric block timer */
f22eb4d3 6372 timer_setup(&phba->fabric_block_timer, lpfc_fabric_block_timeout, 0);
3772a991 6373 /* EA polling mode timer */
f22eb4d3 6374 timer_setup(&phba->eratt_poll, lpfc_poll_eratt, 0);
895427bd 6375 /* Heartbeat timer */
f22eb4d3 6376 timer_setup(&phba->hb_tmofunc, lpfc_hb_timeout, 0);
895427bd 6377
32517fc0
JS
6378 INIT_DELAYED_WORK(&phba->eq_delay_work, lpfc_hb_eq_delay_work);
6379
317aeb83
DK
6380 INIT_DELAYED_WORK(&phba->idle_stat_delay_work,
6381 lpfc_idle_stat_delay_work);
6382
895427bd
JS
6383 return 0;
6384}
6385
6386/**
6387 * lpfc_sli_driver_resource_setup - Setup driver internal resources for SLI3 dev
6388 * @phba: pointer to lpfc hba data structure.
6389 *
6390 * This routine is invoked to set up the driver internal resources specific to
6391 * support the SLI-3 HBA device it attached to.
6392 *
6393 * Return codes
6394 * 0 - successful
6395 * other values - error
6396 **/
6397static int
6398lpfc_sli_driver_resource_setup(struct lpfc_hba *phba)
6399{
0794d601 6400 int rc, entry_sz;
895427bd
JS
6401
6402 /*
6403 * Initialize timers used by driver
6404 */
6405
6406 /* FCP polling mode timer */
f22eb4d3 6407 timer_setup(&phba->fcp_poll_timer, lpfc_poll_timeout, 0);
dea3101e 6408
3772a991
JS
6409 /* Host attention work mask setup */
6410 phba->work_ha_mask = (HA_ERATT | HA_MBATT | HA_LATT);
6411 phba->work_ha_mask |= (HA_RXMASK << (LPFC_ELS_RING * 4));
dea3101e 6412
3772a991
JS
6413 /* Get all the module params for configuring this host */
6414 lpfc_get_cfgparam(phba);
895427bd
JS
6415 /* Set up phase-1 common device driver resources */
6416
6417 rc = lpfc_setup_driver_resource_phase1(phba);
6418 if (rc)
6419 return -ENODEV;
6420
49198b37
JS
6421 if (phba->pcidev->device == PCI_DEVICE_ID_HORNET) {
6422 phba->menlo_flag |= HBA_MENLO_SUPPORT;
6423 /* check for menlo minimum sg count */
6424 if (phba->cfg_sg_seg_cnt < LPFC_DEFAULT_MENLO_SG_SEG_CNT)
6425 phba->cfg_sg_seg_cnt = LPFC_DEFAULT_MENLO_SG_SEG_CNT;
6426 }
6427
895427bd 6428 if (!phba->sli.sli3_ring)
6396bb22
KC
6429 phba->sli.sli3_ring = kcalloc(LPFC_SLI3_MAX_RING,
6430 sizeof(struct lpfc_sli_ring),
6431 GFP_KERNEL);
895427bd 6432 if (!phba->sli.sli3_ring)
2a76a283
JS
6433 return -ENOMEM;
6434
dea3101e 6435 /*
96f7077f 6436 * Since lpfc_sg_seg_cnt is module parameter, the sg_dma_buf_size
3772a991 6437 * used to create the sg_dma_buf_pool must be dynamically calculated.
dea3101e 6438 */
3772a991 6439
0794d601
JS
6440 if (phba->sli_rev == LPFC_SLI_REV4)
6441 entry_sz = sizeof(struct sli4_sge);
6442 else
6443 entry_sz = sizeof(struct ulp_bde64);
6444
96f7077f 6445 /* There are going to be 2 reserved BDEs: 1 FCP cmnd + 1 FCP rsp */
3772a991 6446 if (phba->cfg_enable_bg) {
96f7077f
JS
6447 /*
6448 * The scsi_buf for a T10-DIF I/O will hold the FCP cmnd,
6449 * the FCP rsp, and a BDE for each. Sice we have no control
6450 * over how many protection data segments the SCSI Layer
6451 * will hand us (ie: there could be one for every block
6452 * in the IO), we just allocate enough BDEs to accomidate
6453 * our max amount and we need to limit lpfc_sg_seg_cnt to
6454 * minimize the risk of running out.
6455 */
6456 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6457 sizeof(struct fcp_rsp) +
0794d601 6458 (LPFC_MAX_SG_SEG_CNT * entry_sz);
96f7077f
JS
6459
6460 if (phba->cfg_sg_seg_cnt > LPFC_MAX_SG_SEG_CNT_DIF)
6461 phba->cfg_sg_seg_cnt = LPFC_MAX_SG_SEG_CNT_DIF;
6462
6463 /* Total BDEs in BPL for scsi_sg_list and scsi_sg_prot_list */
6464 phba->cfg_total_seg_cnt = LPFC_MAX_SG_SEG_CNT;
6465 } else {
6466 /*
6467 * The scsi_buf for a regular I/O will hold the FCP cmnd,
6468 * the FCP rsp, a BDE for each, and a BDE for up to
6469 * cfg_sg_seg_cnt data segments.
6470 */
6471 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6472 sizeof(struct fcp_rsp) +
0794d601 6473 ((phba->cfg_sg_seg_cnt + 2) * entry_sz);
96f7077f
JS
6474
6475 /* Total BDEs in BPL for scsi_sg_list */
6476 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + 2;
901a920f 6477 }
dea3101e 6478
96f7077f 6479 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
c90b4480 6480 "9088 INIT sg_tablesize:%d dmabuf_size:%d total_bde:%d\n",
96f7077f
JS
6481 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
6482 phba->cfg_total_seg_cnt);
dea3101e 6483
3772a991
JS
6484 phba->max_vpi = LPFC_MAX_VPI;
6485 /* This will be set to correct value after config_port mbox */
6486 phba->max_vports = 0;
dea3101e 6487
3772a991
JS
6488 /*
6489 * Initialize the SLI Layer to run with lpfc HBAs.
6490 */
6491 lpfc_sli_setup(phba);
895427bd 6492 lpfc_sli_queue_init(phba);
ed957684 6493
3772a991
JS
6494 /* Allocate device driver memory */
6495 if (lpfc_mem_alloc(phba, BPL_ALIGN_SZ))
6496 return -ENOMEM;
51ef4c26 6497
d79c9e9d
JS
6498 phba->lpfc_sg_dma_buf_pool =
6499 dma_pool_create("lpfc_sg_dma_buf_pool",
6500 &phba->pcidev->dev, phba->cfg_sg_dma_buf_size,
6501 BPL_ALIGN_SZ, 0);
6502
6503 if (!phba->lpfc_sg_dma_buf_pool)
6504 goto fail_free_mem;
6505
6506 phba->lpfc_cmd_rsp_buf_pool =
6507 dma_pool_create("lpfc_cmd_rsp_buf_pool",
6508 &phba->pcidev->dev,
6509 sizeof(struct fcp_cmnd) +
6510 sizeof(struct fcp_rsp),
6511 BPL_ALIGN_SZ, 0);
6512
6513 if (!phba->lpfc_cmd_rsp_buf_pool)
6514 goto fail_free_dma_buf_pool;
6515
912e3acd
JS
6516 /*
6517 * Enable sr-iov virtual functions if supported and configured
6518 * through the module parameter.
6519 */
6520 if (phba->cfg_sriov_nr_virtfn > 0) {
6521 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
6522 phba->cfg_sriov_nr_virtfn);
6523 if (rc) {
6524 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6525 "2808 Requested number of SR-IOV "
6526 "virtual functions (%d) is not "
6527 "supported\n",
6528 phba->cfg_sriov_nr_virtfn);
6529 phba->cfg_sriov_nr_virtfn = 0;
6530 }
6531 }
6532
3772a991 6533 return 0;
d79c9e9d
JS
6534
6535fail_free_dma_buf_pool:
6536 dma_pool_destroy(phba->lpfc_sg_dma_buf_pool);
6537 phba->lpfc_sg_dma_buf_pool = NULL;
6538fail_free_mem:
6539 lpfc_mem_free(phba);
6540 return -ENOMEM;
3772a991 6541}
ed957684 6542
3772a991
JS
6543/**
6544 * lpfc_sli_driver_resource_unset - Unset drvr internal resources for SLI3 dev
6545 * @phba: pointer to lpfc hba data structure.
6546 *
6547 * This routine is invoked to unset the driver internal resources set up
6548 * specific for supporting the SLI-3 HBA device it attached to.
6549 **/
6550static void
6551lpfc_sli_driver_resource_unset(struct lpfc_hba *phba)
6552{
6553 /* Free device driver memory allocated */
6554 lpfc_mem_free_all(phba);
3163f725 6555
3772a991
JS
6556 return;
6557}
dea3101e 6558
3772a991 6559/**
da0436e9 6560 * lpfc_sli4_driver_resource_setup - Setup drvr internal resources for SLI4 dev
3772a991
JS
6561 * @phba: pointer to lpfc hba data structure.
6562 *
da0436e9
JS
6563 * This routine is invoked to set up the driver internal resources specific to
6564 * support the SLI-4 HBA device it attached to.
3772a991
JS
6565 *
6566 * Return codes
af901ca1 6567 * 0 - successful
da0436e9 6568 * other values - error
3772a991
JS
6569 **/
6570static int
da0436e9 6571lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba)
3772a991 6572{
28baac74 6573 LPFC_MBOXQ_t *mboxq;
f358dd0c 6574 MAILBOX_t *mb;
895427bd 6575 int rc, i, max_buf_size;
28baac74
JS
6576 uint8_t pn_page[LPFC_MAX_SUPPORTED_PAGES] = {0};
6577 struct lpfc_mqe *mqe;
09294d46 6578 int longs;
81e6a637 6579 int extra;
f358dd0c 6580 uint64_t wwn;
b92dc72d
JS
6581 u32 if_type;
6582 u32 if_fam;
da0436e9 6583
895427bd 6584 phba->sli4_hba.num_present_cpu = lpfc_present_cpu;
eede4970 6585 phba->sli4_hba.num_possible_cpu = cpumask_last(cpu_possible_mask) + 1;
895427bd
JS
6586 phba->sli4_hba.curr_disp_cpu = 0;
6587
716d3bc5
JS
6588 /* Get all the module params for configuring this host */
6589 lpfc_get_cfgparam(phba);
6590
895427bd
JS
6591 /* Set up phase-1 common device driver resources */
6592 rc = lpfc_setup_driver_resource_phase1(phba);
6593 if (rc)
6594 return -ENODEV;
6595
da0436e9
JS
6596 /* Before proceed, wait for POST done and device ready */
6597 rc = lpfc_sli4_post_status_check(phba);
6598 if (rc)
6599 return -ENODEV;
6600
3cee98db
JS
6601 /* Allocate all driver workqueues here */
6602
6603 /* The lpfc_wq workqueue for deferred irq use */
6604 phba->wq = alloc_workqueue("lpfc_wq", WQ_MEM_RECLAIM, 0);
6605
3772a991 6606 /*
da0436e9 6607 * Initialize timers used by driver
3772a991 6608 */
3772a991 6609
f22eb4d3 6610 timer_setup(&phba->rrq_tmr, lpfc_rrq_timeout, 0);
3772a991 6611
ecfd03c6 6612 /* FCF rediscover timer */
f22eb4d3 6613 timer_setup(&phba->fcf.redisc_wait, lpfc_sli4_fcf_redisc_wait_tmo, 0);
ecfd03c6 6614
7ad20aa9
JS
6615 /*
6616 * Control structure for handling external multi-buffer mailbox
6617 * command pass-through.
6618 */
6619 memset((uint8_t *)&phba->mbox_ext_buf_ctx, 0,
6620 sizeof(struct lpfc_mbox_ext_buf_ctx));
6621 INIT_LIST_HEAD(&phba->mbox_ext_buf_ctx.ext_dmabuf_list);
6622
da0436e9 6623 phba->max_vpi = LPFC_MAX_VPI;
67d12733 6624
da0436e9
JS
6625 /* This will be set to correct value after the read_config mbox */
6626 phba->max_vports = 0;
3772a991 6627
da0436e9
JS
6628 /* Program the default value of vlan_id and fc_map */
6629 phba->valid_vlan = 0;
6630 phba->fc_map[0] = LPFC_FCOE_FCF_MAP0;
6631 phba->fc_map[1] = LPFC_FCOE_FCF_MAP1;
6632 phba->fc_map[2] = LPFC_FCOE_FCF_MAP2;
3772a991 6633
2a76a283
JS
6634 /*
6635 * For SLI4, instead of using ring 0 (LPFC_FCP_RING) for FCP commands
895427bd
JS
6636 * we will associate a new ring, for each EQ/CQ/WQ tuple.
6637 * The WQ create will allocate the ring.
2a76a283 6638 */
09294d46 6639
da0436e9 6640 /* Initialize buffer queue management fields */
895427bd 6641 INIT_LIST_HEAD(&phba->hbqs[LPFC_ELS_HBQ].hbq_buffer_list);
da0436e9
JS
6642 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_sli4_rb_alloc;
6643 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_sli4_rb_free;
3772a991 6644
da0436e9
JS
6645 /*
6646 * Initialize the SLI Layer to run with lpfc SLI4 HBAs.
6647 */
c00f62e6
JS
6648 /* Initialize the Abort buffer list used by driver */
6649 spin_lock_init(&phba->sli4_hba.abts_io_buf_list_lock);
6650 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_io_buf_list);
895427bd
JS
6651
6652 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
6653 /* Initialize the Abort nvme buffer list used by driver */
5e5b511d 6654 spin_lock_init(&phba->sli4_hba.abts_nvmet_buf_list_lock);
86c67379 6655 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
a8cf5dfe 6656 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_io_wait_list);
79d8c4ce
JS
6657 spin_lock_init(&phba->sli4_hba.t_active_list_lock);
6658 INIT_LIST_HEAD(&phba->sli4_hba.t_active_ctx_list);
895427bd
JS
6659 }
6660
da0436e9 6661 /* This abort list used by worker thread */
895427bd 6662 spin_lock_init(&phba->sli4_hba.sgl_list_lock);
a8cf5dfe 6663 spin_lock_init(&phba->sli4_hba.nvmet_io_wait_lock);
e7dab164
JS
6664 spin_lock_init(&phba->sli4_hba.asynce_list_lock);
6665 spin_lock_init(&phba->sli4_hba.els_xri_abrt_list_lock);
3772a991 6666
da0436e9 6667 /*
6d368e53 6668 * Initialize driver internal slow-path work queues
da0436e9 6669 */
3772a991 6670
da0436e9
JS
6671 /* Driver internel slow-path CQ Event pool */
6672 INIT_LIST_HEAD(&phba->sli4_hba.sp_cqe_event_pool);
6673 /* Response IOCB work queue list */
45ed1190 6674 INIT_LIST_HEAD(&phba->sli4_hba.sp_queue_event);
da0436e9
JS
6675 /* Asynchronous event CQ Event work queue list */
6676 INIT_LIST_HEAD(&phba->sli4_hba.sp_asynce_work_queue);
da0436e9
JS
6677 /* Slow-path XRI aborted CQ Event work queue list */
6678 INIT_LIST_HEAD(&phba->sli4_hba.sp_els_xri_aborted_work_queue);
6679 /* Receive queue CQ Event work queue list */
6680 INIT_LIST_HEAD(&phba->sli4_hba.sp_unsol_work_queue);
6681
6d368e53
JS
6682 /* Initialize extent block lists. */
6683 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_blk_list);
6684 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_xri_blk_list);
6685 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_vfi_blk_list);
6686 INIT_LIST_HEAD(&phba->lpfc_vpi_blk_list);
6687
d1f525aa
JS
6688 /* Initialize mboxq lists. If the early init routines fail
6689 * these lists need to be correctly initialized.
6690 */
6691 INIT_LIST_HEAD(&phba->sli.mboxq);
6692 INIT_LIST_HEAD(&phba->sli.mboxq_cmpl);
6693
448193b5
JS
6694 /* initialize optic_state to 0xFF */
6695 phba->sli4_hba.lnk_info.optic_state = 0xff;
6696
da0436e9
JS
6697 /* Allocate device driver memory */
6698 rc = lpfc_mem_alloc(phba, SGL_ALIGN_SZ);
6699 if (rc)
6700 return -ENOMEM;
6701
2fcee4bf 6702 /* IF Type 2 ports get initialized now. */
27d6ac0a 6703 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) >=
2fcee4bf
JS
6704 LPFC_SLI_INTF_IF_TYPE_2) {
6705 rc = lpfc_pci_function_reset(phba);
895427bd
JS
6706 if (unlikely(rc)) {
6707 rc = -ENODEV;
6708 goto out_free_mem;
6709 }
946727dc 6710 phba->temp_sensor_support = 1;
2fcee4bf
JS
6711 }
6712
da0436e9
JS
6713 /* Create the bootstrap mailbox command */
6714 rc = lpfc_create_bootstrap_mbox(phba);
6715 if (unlikely(rc))
6716 goto out_free_mem;
6717
6718 /* Set up the host's endian order with the device. */
6719 rc = lpfc_setup_endian_order(phba);
6720 if (unlikely(rc))
6721 goto out_free_bsmbx;
6722
6723 /* Set up the hba's configuration parameters. */
6724 rc = lpfc_sli4_read_config(phba);
cff261f6
JS
6725 if (unlikely(rc))
6726 goto out_free_bsmbx;
6727 rc = lpfc_mem_alloc_active_rrq_pool_s4(phba);
da0436e9
JS
6728 if (unlikely(rc))
6729 goto out_free_bsmbx;
6730
2fcee4bf
JS
6731 /* IF Type 0 ports get initialized now. */
6732 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
6733 LPFC_SLI_INTF_IF_TYPE_0) {
6734 rc = lpfc_pci_function_reset(phba);
6735 if (unlikely(rc))
6736 goto out_free_bsmbx;
6737 }
da0436e9 6738
cb5172ea
JS
6739 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
6740 GFP_KERNEL);
6741 if (!mboxq) {
6742 rc = -ENOMEM;
6743 goto out_free_bsmbx;
6744 }
6745
f358dd0c 6746 /* Check for NVMET being configured */
895427bd 6747 phba->nvmet_support = 0;
f358dd0c
JS
6748 if (lpfc_enable_nvmet_cnt) {
6749
6750 /* First get WWN of HBA instance */
6751 lpfc_read_nv(phba, mboxq);
6752 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
6753 if (rc != MBX_SUCCESS) {
372c187b
DK
6754 lpfc_printf_log(phba, KERN_ERR,
6755 LOG_TRACE_EVENT,
f358dd0c
JS
6756 "6016 Mailbox failed , mbxCmd x%x "
6757 "READ_NV, mbxStatus x%x\n",
6758 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
6759 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
d1f525aa 6760 mempool_free(mboxq, phba->mbox_mem_pool);
f358dd0c
JS
6761 rc = -EIO;
6762 goto out_free_bsmbx;
6763 }
6764 mb = &mboxq->u.mb;
6765 memcpy(&wwn, (char *)mb->un.varRDnvp.nodename,
6766 sizeof(uint64_t));
6767 wwn = cpu_to_be64(wwn);
6768 phba->sli4_hba.wwnn.u.name = wwn;
6769 memcpy(&wwn, (char *)mb->un.varRDnvp.portname,
6770 sizeof(uint64_t));
6771 /* wwn is WWPN of HBA instance */
6772 wwn = cpu_to_be64(wwn);
6773 phba->sli4_hba.wwpn.u.name = wwn;
6774
6775 /* Check to see if it matches any module parameter */
6776 for (i = 0; i < lpfc_enable_nvmet_cnt; i++) {
6777 if (wwn == lpfc_enable_nvmet[i]) {
7d708033 6778#if (IS_ENABLED(CONFIG_NVME_TARGET_FC))
3c603be9
JS
6779 if (lpfc_nvmet_mem_alloc(phba))
6780 break;
6781
6782 phba->nvmet_support = 1; /* a match */
6783
372c187b
DK
6784 lpfc_printf_log(phba, KERN_ERR,
6785 LOG_TRACE_EVENT,
f358dd0c
JS
6786 "6017 NVME Target %016llx\n",
6787 wwn);
7d708033 6788#else
372c187b
DK
6789 lpfc_printf_log(phba, KERN_ERR,
6790 LOG_TRACE_EVENT,
7d708033
JS
6791 "6021 Can't enable NVME Target."
6792 " NVME_TARGET_FC infrastructure"
6793 " is not in kernel\n");
6794#endif
c490850a
JS
6795 /* Not supported for NVMET */
6796 phba->cfg_xri_rebalancing = 0;
3048e3e8
DK
6797 if (phba->irq_chann_mode == NHT_MODE) {
6798 phba->cfg_irq_chann =
6799 phba->sli4_hba.num_present_cpu;
6800 phba->cfg_hdw_queue =
6801 phba->sli4_hba.num_present_cpu;
6802 phba->irq_chann_mode = NORMAL_MODE;
6803 }
3c603be9 6804 break;
f358dd0c
JS
6805 }
6806 }
6807 }
895427bd
JS
6808
6809 lpfc_nvme_mod_param_dep(phba);
6810
fedd3b7b 6811 /* Get the Supported Pages if PORT_CAPABILITIES is supported by port. */
cb5172ea
JS
6812 lpfc_supported_pages(mboxq);
6813 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
fedd3b7b
JS
6814 if (!rc) {
6815 mqe = &mboxq->u.mqe;
6816 memcpy(&pn_page[0], ((uint8_t *)&mqe->un.supp_pages.word3),
6817 LPFC_MAX_SUPPORTED_PAGES);
6818 for (i = 0; i < LPFC_MAX_SUPPORTED_PAGES; i++) {
6819 switch (pn_page[i]) {
6820 case LPFC_SLI4_PARAMETERS:
6821 phba->sli4_hba.pc_sli4_params.supported = 1;
6822 break;
6823 default:
6824 break;
6825 }
6826 }
6827 /* Read the port's SLI4 Parameters capabilities if supported. */
6828 if (phba->sli4_hba.pc_sli4_params.supported)
6829 rc = lpfc_pc_sli4_params_get(phba, mboxq);
6830 if (rc) {
6831 mempool_free(mboxq, phba->mbox_mem_pool);
6832 rc = -EIO;
6833 goto out_free_bsmbx;
cb5172ea
JS
6834 }
6835 }
65791f1f 6836
fedd3b7b
JS
6837 /*
6838 * Get sli4 parameters that override parameters from Port capabilities.
6d368e53
JS
6839 * If this call fails, it isn't critical unless the SLI4 parameters come
6840 * back in conflict.
fedd3b7b 6841 */
6d368e53
JS
6842 rc = lpfc_get_sli4_parameters(phba, mboxq);
6843 if (rc) {
b92dc72d
JS
6844 if_type = bf_get(lpfc_sli_intf_if_type,
6845 &phba->sli4_hba.sli_intf);
6846 if_fam = bf_get(lpfc_sli_intf_sli_family,
6847 &phba->sli4_hba.sli_intf);
6d368e53
JS
6848 if (phba->sli4_hba.extents_in_use &&
6849 phba->sli4_hba.rpi_hdrs_in_use) {
372c187b
DK
6850 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
6851 "2999 Unsupported SLI4 Parameters "
6852 "Extents and RPI headers enabled.\n");
b92dc72d
JS
6853 if (if_type == LPFC_SLI_INTF_IF_TYPE_0 &&
6854 if_fam == LPFC_SLI_INTF_FAMILY_BE2) {
6855 mempool_free(mboxq, phba->mbox_mem_pool);
6856 rc = -EIO;
6857 goto out_free_bsmbx;
6858 }
6859 }
6860 if (!(if_type == LPFC_SLI_INTF_IF_TYPE_0 &&
6861 if_fam == LPFC_SLI_INTF_FAMILY_BE2)) {
6862 mempool_free(mboxq, phba->mbox_mem_pool);
6863 rc = -EIO;
6864 goto out_free_bsmbx;
6d368e53
JS
6865 }
6866 }
895427bd 6867
d79c9e9d
JS
6868 /*
6869 * 1 for cmd, 1 for rsp, NVME adds an extra one
6870 * for boundary conditions in its max_sgl_segment template.
6871 */
6872 extra = 2;
6873 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
6874 extra++;
6875
6876 /*
6877 * It doesn't matter what family our adapter is in, we are
6878 * limited to 2 Pages, 512 SGEs, for our SGL.
6879 * There are going to be 2 reserved SGEs: 1 FCP cmnd + 1 FCP rsp
6880 */
6881 max_buf_size = (2 * SLI4_PAGE_SIZE);
6882
6883 /*
6884 * Since lpfc_sg_seg_cnt is module param, the sg_dma_buf_size
6885 * used to create the sg_dma_buf_pool must be calculated.
6886 */
6887 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED) {
6888 /* Both cfg_enable_bg and cfg_external_dif code paths */
6889
6890 /*
6891 * The scsi_buf for a T10-DIF I/O holds the FCP cmnd,
6892 * the FCP rsp, and a SGE. Sice we have no control
6893 * over how many protection segments the SCSI Layer
6894 * will hand us (ie: there could be one for every block
6895 * in the IO), just allocate enough SGEs to accomidate
6896 * our max amount and we need to limit lpfc_sg_seg_cnt
6897 * to minimize the risk of running out.
6898 */
6899 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6900 sizeof(struct fcp_rsp) + max_buf_size;
6901
6902 /* Total SGEs for scsi_sg_list and scsi_sg_prot_list */
6903 phba->cfg_total_seg_cnt = LPFC_MAX_SGL_SEG_CNT;
6904
6905 /*
6906 * If supporting DIF, reduce the seg count for scsi to
6907 * allow room for the DIF sges.
6908 */
6909 if (phba->cfg_enable_bg &&
6910 phba->cfg_sg_seg_cnt > LPFC_MAX_BG_SLI4_SEG_CNT_DIF)
6911 phba->cfg_scsi_seg_cnt = LPFC_MAX_BG_SLI4_SEG_CNT_DIF;
6912 else
6913 phba->cfg_scsi_seg_cnt = phba->cfg_sg_seg_cnt;
6914
6915 } else {
6916 /*
6917 * The scsi_buf for a regular I/O holds the FCP cmnd,
6918 * the FCP rsp, a SGE for each, and a SGE for up to
6919 * cfg_sg_seg_cnt data segments.
6920 */
6921 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6922 sizeof(struct fcp_rsp) +
6923 ((phba->cfg_sg_seg_cnt + extra) *
6924 sizeof(struct sli4_sge));
6925
6926 /* Total SGEs for scsi_sg_list */
6927 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + extra;
6928 phba->cfg_scsi_seg_cnt = phba->cfg_sg_seg_cnt;
6929
6930 /*
6931 * NOTE: if (phba->cfg_sg_seg_cnt + extra) <= 256 we only
6932 * need to post 1 page for the SGL.
6933 */
6934 }
6935
6936 if (phba->cfg_xpsgl && !phba->nvmet_support)
6937 phba->cfg_sg_dma_buf_size = LPFC_DEFAULT_XPSGL_SIZE;
6938 else if (phba->cfg_sg_dma_buf_size <= LPFC_MIN_SG_SLI4_BUF_SZ)
6939 phba->cfg_sg_dma_buf_size = LPFC_MIN_SG_SLI4_BUF_SZ;
6940 else
6941 phba->cfg_sg_dma_buf_size =
6942 SLI4_PAGE_ALIGN(phba->cfg_sg_dma_buf_size);
6943
6944 phba->border_sge_num = phba->cfg_sg_dma_buf_size /
6945 sizeof(struct sli4_sge);
6946
6947 /* Limit to LPFC_MAX_NVME_SEG_CNT for NVME. */
6948 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
6949 if (phba->cfg_sg_seg_cnt > LPFC_MAX_NVME_SEG_CNT) {
6950 lpfc_printf_log(phba, KERN_INFO, LOG_NVME | LOG_INIT,
6951 "6300 Reducing NVME sg segment "
6952 "cnt to %d\n",
6953 LPFC_MAX_NVME_SEG_CNT);
6954 phba->cfg_nvme_seg_cnt = LPFC_MAX_NVME_SEG_CNT;
6955 } else
6956 phba->cfg_nvme_seg_cnt = phba->cfg_sg_seg_cnt;
6957 }
6958
d79c9e9d
JS
6959 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
6960 "9087 sg_seg_cnt:%d dmabuf_size:%d "
6961 "total:%d scsi:%d nvme:%d\n",
6962 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
6963 phba->cfg_total_seg_cnt, phba->cfg_scsi_seg_cnt,
6964 phba->cfg_nvme_seg_cnt);
6965
6966 if (phba->cfg_sg_dma_buf_size < SLI4_PAGE_SIZE)
6967 i = phba->cfg_sg_dma_buf_size;
6968 else
6969 i = SLI4_PAGE_SIZE;
6970
6971 phba->lpfc_sg_dma_buf_pool =
6972 dma_pool_create("lpfc_sg_dma_buf_pool",
6973 &phba->pcidev->dev,
6974 phba->cfg_sg_dma_buf_size,
6975 i, 0);
6976 if (!phba->lpfc_sg_dma_buf_pool)
6977 goto out_free_bsmbx;
6978
6979 phba->lpfc_cmd_rsp_buf_pool =
6980 dma_pool_create("lpfc_cmd_rsp_buf_pool",
6981 &phba->pcidev->dev,
6982 sizeof(struct fcp_cmnd) +
6983 sizeof(struct fcp_rsp),
6984 i, 0);
6985 if (!phba->lpfc_cmd_rsp_buf_pool)
6986 goto out_free_sg_dma_buf;
6987
cb5172ea 6988 mempool_free(mboxq, phba->mbox_mem_pool);
1ba981fd
JS
6989
6990 /* Verify OAS is supported */
6991 lpfc_sli4_oas_verify(phba);
1ba981fd 6992
d2cc9bcd
JS
6993 /* Verify RAS support on adapter */
6994 lpfc_sli4_ras_init(phba);
6995
5350d872
JS
6996 /* Verify all the SLI4 queues */
6997 rc = lpfc_sli4_queue_verify(phba);
da0436e9 6998 if (rc)
d79c9e9d 6999 goto out_free_cmd_rsp_buf;
da0436e9
JS
7000
7001 /* Create driver internal CQE event pool */
7002 rc = lpfc_sli4_cq_event_pool_create(phba);
7003 if (rc)
d79c9e9d 7004 goto out_free_cmd_rsp_buf;
da0436e9 7005
8a9d2e80
JS
7006 /* Initialize sgl lists per host */
7007 lpfc_init_sgl_list(phba);
7008
7009 /* Allocate and initialize active sgl array */
da0436e9
JS
7010 rc = lpfc_init_active_sgl_array(phba);
7011 if (rc) {
372c187b 7012 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 7013 "1430 Failed to initialize sgl list.\n");
8a9d2e80 7014 goto out_destroy_cq_event_pool;
da0436e9 7015 }
da0436e9
JS
7016 rc = lpfc_sli4_init_rpi_hdrs(phba);
7017 if (rc) {
372c187b 7018 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
7019 "1432 Failed to initialize rpi headers.\n");
7020 goto out_free_active_sgl;
7021 }
7022
a93ff37a 7023 /* Allocate eligible FCF bmask memory for FCF roundrobin failover */
0c9ab6f5 7024 longs = (LPFC_SLI4_FCF_TBL_INDX_MAX + BITS_PER_LONG - 1)/BITS_PER_LONG;
6396bb22 7025 phba->fcf.fcf_rr_bmask = kcalloc(longs, sizeof(unsigned long),
0c9ab6f5
JS
7026 GFP_KERNEL);
7027 if (!phba->fcf.fcf_rr_bmask) {
372c187b 7028 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0c9ab6f5
JS
7029 "2759 Failed allocate memory for FCF round "
7030 "robin failover bmask\n");
0558056c 7031 rc = -ENOMEM;
0c9ab6f5
JS
7032 goto out_remove_rpi_hdrs;
7033 }
7034
6a828b0f 7035 phba->sli4_hba.hba_eq_hdl = kcalloc(phba->cfg_irq_chann,
cdb42bec
JS
7036 sizeof(struct lpfc_hba_eq_hdl),
7037 GFP_KERNEL);
895427bd 7038 if (!phba->sli4_hba.hba_eq_hdl) {
372c187b 7039 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
67d12733
JS
7040 "2572 Failed allocate memory for "
7041 "fast-path per-EQ handle array\n");
7042 rc = -ENOMEM;
7043 goto out_free_fcf_rr_bmask;
da0436e9
JS
7044 }
7045
222e9239 7046 phba->sli4_hba.cpu_map = kcalloc(phba->sli4_hba.num_possible_cpu,
895427bd
JS
7047 sizeof(struct lpfc_vector_map_info),
7048 GFP_KERNEL);
7bb03bbf 7049 if (!phba->sli4_hba.cpu_map) {
372c187b 7050 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
7bb03bbf
JS
7051 "3327 Failed allocate memory for msi-x "
7052 "interrupt vector mapping\n");
7053 rc = -ENOMEM;
895427bd 7054 goto out_free_hba_eq_hdl;
7bb03bbf 7055 }
b246de17 7056
32517fc0
JS
7057 phba->sli4_hba.eq_info = alloc_percpu(struct lpfc_eq_intr_info);
7058 if (!phba->sli4_hba.eq_info) {
372c187b 7059 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
32517fc0
JS
7060 "3321 Failed allocation for per_cpu stats\n");
7061 rc = -ENOMEM;
7062 goto out_free_hba_cpu_map;
7063 }
840eda96 7064
317aeb83
DK
7065 phba->sli4_hba.idle_stat = kcalloc(phba->sli4_hba.num_possible_cpu,
7066 sizeof(*phba->sli4_hba.idle_stat),
7067 GFP_KERNEL);
7068 if (!phba->sli4_hba.idle_stat) {
372c187b 7069 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
317aeb83
DK
7070 "3390 Failed allocation for idle_stat\n");
7071 rc = -ENOMEM;
7072 goto out_free_hba_eq_info;
7073 }
7074
840eda96
JS
7075#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
7076 phba->sli4_hba.c_stat = alloc_percpu(struct lpfc_hdwq_stat);
7077 if (!phba->sli4_hba.c_stat) {
372c187b 7078 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
840eda96
JS
7079 "3332 Failed allocating per cpu hdwq stats\n");
7080 rc = -ENOMEM;
317aeb83 7081 goto out_free_hba_idle_stat;
840eda96
JS
7082 }
7083#endif
7084
912e3acd
JS
7085 /*
7086 * Enable sr-iov virtual functions if supported and configured
7087 * through the module parameter.
7088 */
7089 if (phba->cfg_sriov_nr_virtfn > 0) {
7090 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
7091 phba->cfg_sriov_nr_virtfn);
7092 if (rc) {
7093 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
7094 "3020 Requested number of SR-IOV "
7095 "virtual functions (%d) is not "
7096 "supported\n",
7097 phba->cfg_sriov_nr_virtfn);
7098 phba->cfg_sriov_nr_virtfn = 0;
7099 }
7100 }
7101
5248a749 7102 return 0;
da0436e9 7103
840eda96 7104#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
317aeb83
DK
7105out_free_hba_idle_stat:
7106 kfree(phba->sli4_hba.idle_stat);
7107#endif
840eda96
JS
7108out_free_hba_eq_info:
7109 free_percpu(phba->sli4_hba.eq_info);
32517fc0
JS
7110out_free_hba_cpu_map:
7111 kfree(phba->sli4_hba.cpu_map);
895427bd
JS
7112out_free_hba_eq_hdl:
7113 kfree(phba->sli4_hba.hba_eq_hdl);
0c9ab6f5
JS
7114out_free_fcf_rr_bmask:
7115 kfree(phba->fcf.fcf_rr_bmask);
da0436e9
JS
7116out_remove_rpi_hdrs:
7117 lpfc_sli4_remove_rpi_hdrs(phba);
7118out_free_active_sgl:
7119 lpfc_free_active_sgl(phba);
da0436e9
JS
7120out_destroy_cq_event_pool:
7121 lpfc_sli4_cq_event_pool_destroy(phba);
d79c9e9d
JS
7122out_free_cmd_rsp_buf:
7123 dma_pool_destroy(phba->lpfc_cmd_rsp_buf_pool);
7124 phba->lpfc_cmd_rsp_buf_pool = NULL;
7125out_free_sg_dma_buf:
7126 dma_pool_destroy(phba->lpfc_sg_dma_buf_pool);
7127 phba->lpfc_sg_dma_buf_pool = NULL;
da0436e9
JS
7128out_free_bsmbx:
7129 lpfc_destroy_bootstrap_mbox(phba);
7130out_free_mem:
7131 lpfc_mem_free(phba);
7132 return rc;
7133}
7134
7135/**
7136 * lpfc_sli4_driver_resource_unset - Unset drvr internal resources for SLI4 dev
7137 * @phba: pointer to lpfc hba data structure.
7138 *
7139 * This routine is invoked to unset the driver internal resources set up
7140 * specific for supporting the SLI-4 HBA device it attached to.
7141 **/
7142static void
7143lpfc_sli4_driver_resource_unset(struct lpfc_hba *phba)
7144{
7145 struct lpfc_fcf_conn_entry *conn_entry, *next_conn_entry;
7146
32517fc0 7147 free_percpu(phba->sli4_hba.eq_info);
840eda96
JS
7148#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
7149 free_percpu(phba->sli4_hba.c_stat);
7150#endif
317aeb83 7151 kfree(phba->sli4_hba.idle_stat);
32517fc0 7152
7bb03bbf
JS
7153 /* Free memory allocated for msi-x interrupt vector to CPU mapping */
7154 kfree(phba->sli4_hba.cpu_map);
222e9239 7155 phba->sli4_hba.num_possible_cpu = 0;
7bb03bbf 7156 phba->sli4_hba.num_present_cpu = 0;
76fd07a6 7157 phba->sli4_hba.curr_disp_cpu = 0;
3048e3e8 7158 cpumask_clear(&phba->sli4_hba.irq_aff_mask);
7bb03bbf 7159
da0436e9 7160 /* Free memory allocated for fast-path work queue handles */
895427bd 7161 kfree(phba->sli4_hba.hba_eq_hdl);
da0436e9
JS
7162
7163 /* Free the allocated rpi headers. */
7164 lpfc_sli4_remove_rpi_hdrs(phba);
d11e31dd 7165 lpfc_sli4_remove_rpis(phba);
da0436e9 7166
0c9ab6f5
JS
7167 /* Free eligible FCF index bmask */
7168 kfree(phba->fcf.fcf_rr_bmask);
7169
da0436e9
JS
7170 /* Free the ELS sgl list */
7171 lpfc_free_active_sgl(phba);
8a9d2e80 7172 lpfc_free_els_sgl_list(phba);
f358dd0c 7173 lpfc_free_nvmet_sgl_list(phba);
da0436e9 7174
da0436e9
JS
7175 /* Free the completion queue EQ event pool */
7176 lpfc_sli4_cq_event_release_all(phba);
7177 lpfc_sli4_cq_event_pool_destroy(phba);
7178
6d368e53
JS
7179 /* Release resource identifiers. */
7180 lpfc_sli4_dealloc_resource_identifiers(phba);
7181
da0436e9
JS
7182 /* Free the bsmbx region. */
7183 lpfc_destroy_bootstrap_mbox(phba);
7184
7185 /* Free the SLI Layer memory with SLI4 HBAs */
7186 lpfc_mem_free_all(phba);
7187
7188 /* Free the current connect table */
7189 list_for_each_entry_safe(conn_entry, next_conn_entry,
4d9ab994
JS
7190 &phba->fcf_conn_rec_list, list) {
7191 list_del_init(&conn_entry->list);
da0436e9 7192 kfree(conn_entry);
4d9ab994 7193 }
da0436e9
JS
7194
7195 return;
7196}
7197
7198/**
25985edc 7199 * lpfc_init_api_table_setup - Set up init api function jump table
da0436e9
JS
7200 * @phba: The hba struct for which this call is being executed.
7201 * @dev_grp: The HBA PCI-Device group number.
7202 *
7203 * This routine sets up the device INIT interface API function jump table
7204 * in @phba struct.
7205 *
7206 * Returns: 0 - success, -ENODEV - failure.
7207 **/
7208int
7209lpfc_init_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
7210{
84d1b006
JS
7211 phba->lpfc_hba_init_link = lpfc_hba_init_link;
7212 phba->lpfc_hba_down_link = lpfc_hba_down_link;
7f86059a 7213 phba->lpfc_selective_reset = lpfc_selective_reset;
da0436e9
JS
7214 switch (dev_grp) {
7215 case LPFC_PCI_DEV_LP:
7216 phba->lpfc_hba_down_post = lpfc_hba_down_post_s3;
7217 phba->lpfc_handle_eratt = lpfc_handle_eratt_s3;
7218 phba->lpfc_stop_port = lpfc_stop_port_s3;
7219 break;
7220 case LPFC_PCI_DEV_OC:
7221 phba->lpfc_hba_down_post = lpfc_hba_down_post_s4;
7222 phba->lpfc_handle_eratt = lpfc_handle_eratt_s4;
7223 phba->lpfc_stop_port = lpfc_stop_port_s4;
7224 break;
7225 default:
372c187b 7226 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
7227 "1431 Invalid HBA PCI-device group: 0x%x\n",
7228 dev_grp);
7229 return -ENODEV;
da0436e9
JS
7230 }
7231 return 0;
7232}
7233
da0436e9
JS
7234/**
7235 * lpfc_setup_driver_resource_phase2 - Phase2 setup driver internal resources.
7236 * @phba: pointer to lpfc hba data structure.
7237 *
7238 * This routine is invoked to set up the driver internal resources after the
7239 * device specific resource setup to support the HBA device it attached to.
7240 *
7241 * Return codes
af901ca1 7242 * 0 - successful
da0436e9
JS
7243 * other values - error
7244 **/
7245static int
7246lpfc_setup_driver_resource_phase2(struct lpfc_hba *phba)
7247{
7248 int error;
7249
7250 /* Startup the kernel thread for this host adapter. */
7251 phba->worker_thread = kthread_run(lpfc_do_work, phba,
7252 "lpfc_worker_%d", phba->brd_no);
7253 if (IS_ERR(phba->worker_thread)) {
7254 error = PTR_ERR(phba->worker_thread);
7255 return error;
3772a991
JS
7256 }
7257
7258 return 0;
7259}
7260
7261/**
7262 * lpfc_unset_driver_resource_phase2 - Phase2 unset driver internal resources.
7263 * @phba: pointer to lpfc hba data structure.
7264 *
7265 * This routine is invoked to unset the driver internal resources set up after
7266 * the device specific resource setup for supporting the HBA device it
7267 * attached to.
7268 **/
7269static void
7270lpfc_unset_driver_resource_phase2(struct lpfc_hba *phba)
7271{
f485c18d
DK
7272 if (phba->wq) {
7273 flush_workqueue(phba->wq);
7274 destroy_workqueue(phba->wq);
7275 phba->wq = NULL;
7276 }
7277
3772a991 7278 /* Stop kernel worker thread */
0cdb84ec
JS
7279 if (phba->worker_thread)
7280 kthread_stop(phba->worker_thread);
3772a991
JS
7281}
7282
7283/**
7284 * lpfc_free_iocb_list - Free iocb list.
7285 * @phba: pointer to lpfc hba data structure.
7286 *
7287 * This routine is invoked to free the driver's IOCB list and memory.
7288 **/
6c621a22 7289void
3772a991
JS
7290lpfc_free_iocb_list(struct lpfc_hba *phba)
7291{
7292 struct lpfc_iocbq *iocbq_entry = NULL, *iocbq_next = NULL;
7293
7294 spin_lock_irq(&phba->hbalock);
7295 list_for_each_entry_safe(iocbq_entry, iocbq_next,
7296 &phba->lpfc_iocb_list, list) {
7297 list_del(&iocbq_entry->list);
7298 kfree(iocbq_entry);
7299 phba->total_iocbq_bufs--;
98c9ea5c 7300 }
3772a991
JS
7301 spin_unlock_irq(&phba->hbalock);
7302
7303 return;
7304}
7305
7306/**
7307 * lpfc_init_iocb_list - Allocate and initialize iocb list.
7308 * @phba: pointer to lpfc hba data structure.
fe614acd 7309 * @iocb_count: number of requested iocbs
3772a991
JS
7310 *
7311 * This routine is invoked to allocate and initizlize the driver's IOCB
7312 * list and set up the IOCB tag array accordingly.
7313 *
7314 * Return codes
af901ca1 7315 * 0 - successful
3772a991
JS
7316 * other values - error
7317 **/
6c621a22 7318int
3772a991
JS
7319lpfc_init_iocb_list(struct lpfc_hba *phba, int iocb_count)
7320{
7321 struct lpfc_iocbq *iocbq_entry = NULL;
7322 uint16_t iotag;
7323 int i;
dea3101e 7324
7325 /* Initialize and populate the iocb list per host. */
7326 INIT_LIST_HEAD(&phba->lpfc_iocb_list);
3772a991 7327 for (i = 0; i < iocb_count; i++) {
dd00cc48 7328 iocbq_entry = kzalloc(sizeof(struct lpfc_iocbq), GFP_KERNEL);
dea3101e 7329 if (iocbq_entry == NULL) {
7330 printk(KERN_ERR "%s: only allocated %d iocbs of "
7331 "expected %d count. Unloading driver.\n",
a5f7337f 7332 __func__, i, iocb_count);
dea3101e 7333 goto out_free_iocbq;
7334 }
7335
604a3e30
JB
7336 iotag = lpfc_sli_next_iotag(phba, iocbq_entry);
7337 if (iotag == 0) {
3772a991 7338 kfree(iocbq_entry);
604a3e30 7339 printk(KERN_ERR "%s: failed to allocate IOTAG. "
3772a991 7340 "Unloading driver.\n", __func__);
604a3e30
JB
7341 goto out_free_iocbq;
7342 }
6d368e53 7343 iocbq_entry->sli4_lxritag = NO_XRI;
3772a991 7344 iocbq_entry->sli4_xritag = NO_XRI;
2e0fef85
JS
7345
7346 spin_lock_irq(&phba->hbalock);
dea3101e 7347 list_add(&iocbq_entry->list, &phba->lpfc_iocb_list);
7348 phba->total_iocbq_bufs++;
2e0fef85 7349 spin_unlock_irq(&phba->hbalock);
dea3101e 7350 }
7351
3772a991 7352 return 0;
dea3101e 7353
3772a991
JS
7354out_free_iocbq:
7355 lpfc_free_iocb_list(phba);
dea3101e 7356
3772a991
JS
7357 return -ENOMEM;
7358}
5e9d9b82 7359
3772a991 7360/**
8a9d2e80 7361 * lpfc_free_sgl_list - Free a given sgl list.
da0436e9 7362 * @phba: pointer to lpfc hba data structure.
8a9d2e80 7363 * @sglq_list: pointer to the head of sgl list.
3772a991 7364 *
8a9d2e80 7365 * This routine is invoked to free a give sgl list and memory.
3772a991 7366 **/
8a9d2e80
JS
7367void
7368lpfc_free_sgl_list(struct lpfc_hba *phba, struct list_head *sglq_list)
3772a991 7369{
da0436e9 7370 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
8a9d2e80
JS
7371
7372 list_for_each_entry_safe(sglq_entry, sglq_next, sglq_list, list) {
7373 list_del(&sglq_entry->list);
7374 lpfc_mbuf_free(phba, sglq_entry->virt, sglq_entry->phys);
7375 kfree(sglq_entry);
7376 }
7377}
7378
7379/**
7380 * lpfc_free_els_sgl_list - Free els sgl list.
7381 * @phba: pointer to lpfc hba data structure.
7382 *
7383 * This routine is invoked to free the driver's els sgl list and memory.
7384 **/
7385static void
7386lpfc_free_els_sgl_list(struct lpfc_hba *phba)
7387{
da0436e9 7388 LIST_HEAD(sglq_list);
dea3101e 7389
8a9d2e80 7390 /* Retrieve all els sgls from driver list */
da0436e9 7391 spin_lock_irq(&phba->hbalock);
895427bd
JS
7392 spin_lock(&phba->sli4_hba.sgl_list_lock);
7393 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list, &sglq_list);
7394 spin_unlock(&phba->sli4_hba.sgl_list_lock);
da0436e9 7395 spin_unlock_irq(&phba->hbalock);
dea3101e 7396
8a9d2e80
JS
7397 /* Now free the sgl list */
7398 lpfc_free_sgl_list(phba, &sglq_list);
da0436e9 7399}
92d7f7b0 7400
f358dd0c
JS
7401/**
7402 * lpfc_free_nvmet_sgl_list - Free nvmet sgl list.
7403 * @phba: pointer to lpfc hba data structure.
7404 *
7405 * This routine is invoked to free the driver's nvmet sgl list and memory.
7406 **/
7407static void
7408lpfc_free_nvmet_sgl_list(struct lpfc_hba *phba)
7409{
7410 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
7411 LIST_HEAD(sglq_list);
7412
7413 /* Retrieve all nvmet sgls from driver list */
7414 spin_lock_irq(&phba->hbalock);
7415 spin_lock(&phba->sli4_hba.sgl_list_lock);
7416 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list, &sglq_list);
7417 spin_unlock(&phba->sli4_hba.sgl_list_lock);
7418 spin_unlock_irq(&phba->hbalock);
7419
7420 /* Now free the sgl list */
7421 list_for_each_entry_safe(sglq_entry, sglq_next, &sglq_list, list) {
7422 list_del(&sglq_entry->list);
7423 lpfc_nvmet_buf_free(phba, sglq_entry->virt, sglq_entry->phys);
7424 kfree(sglq_entry);
7425 }
4b40d02b
DK
7426
7427 /* Update the nvmet_xri_cnt to reflect no current sgls.
7428 * The next initialization cycle sets the count and allocates
7429 * the sgls over again.
7430 */
7431 phba->sli4_hba.nvmet_xri_cnt = 0;
f358dd0c
JS
7432}
7433
da0436e9
JS
7434/**
7435 * lpfc_init_active_sgl_array - Allocate the buf to track active ELS XRIs.
7436 * @phba: pointer to lpfc hba data structure.
7437 *
7438 * This routine is invoked to allocate the driver's active sgl memory.
7439 * This array will hold the sglq_entry's for active IOs.
7440 **/
7441static int
7442lpfc_init_active_sgl_array(struct lpfc_hba *phba)
7443{
7444 int size;
7445 size = sizeof(struct lpfc_sglq *);
7446 size *= phba->sli4_hba.max_cfg_param.max_xri;
7447
7448 phba->sli4_hba.lpfc_sglq_active_list =
7449 kzalloc(size, GFP_KERNEL);
7450 if (!phba->sli4_hba.lpfc_sglq_active_list)
7451 return -ENOMEM;
7452 return 0;
3772a991
JS
7453}
7454
7455/**
da0436e9 7456 * lpfc_free_active_sgl - Free the buf that tracks active ELS XRIs.
3772a991
JS
7457 * @phba: pointer to lpfc hba data structure.
7458 *
da0436e9
JS
7459 * This routine is invoked to walk through the array of active sglq entries
7460 * and free all of the resources.
7461 * This is just a place holder for now.
3772a991
JS
7462 **/
7463static void
da0436e9 7464lpfc_free_active_sgl(struct lpfc_hba *phba)
3772a991 7465{
da0436e9 7466 kfree(phba->sli4_hba.lpfc_sglq_active_list);
3772a991
JS
7467}
7468
7469/**
da0436e9 7470 * lpfc_init_sgl_list - Allocate and initialize sgl list.
3772a991
JS
7471 * @phba: pointer to lpfc hba data structure.
7472 *
da0436e9
JS
7473 * This routine is invoked to allocate and initizlize the driver's sgl
7474 * list and set up the sgl xritag tag array accordingly.
3772a991 7475 *
3772a991 7476 **/
8a9d2e80 7477static void
da0436e9 7478lpfc_init_sgl_list(struct lpfc_hba *phba)
3772a991 7479{
da0436e9 7480 /* Initialize and populate the sglq list per host/VF. */
895427bd 7481 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_els_sgl_list);
da0436e9 7482 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_els_sgl_list);
f358dd0c 7483 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_sgl_list);
86c67379 7484 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
da0436e9 7485
8a9d2e80
JS
7486 /* els xri-sgl book keeping */
7487 phba->sli4_hba.els_xri_cnt = 0;
0ff10d46 7488
895427bd 7489 /* nvme xri-buffer book keeping */
5e5b511d 7490 phba->sli4_hba.io_xri_cnt = 0;
da0436e9
JS
7491}
7492
7493/**
7494 * lpfc_sli4_init_rpi_hdrs - Post the rpi header memory region to the port
7495 * @phba: pointer to lpfc hba data structure.
7496 *
7497 * This routine is invoked to post rpi header templates to the
88a2cfbb 7498 * port for those SLI4 ports that do not support extents. This routine
da0436e9 7499 * posts a PAGE_SIZE memory region to the port to hold up to
88a2cfbb
JS
7500 * PAGE_SIZE modulo 64 rpi context headers. This is an initialization routine
7501 * and should be called only when interrupts are disabled.
da0436e9
JS
7502 *
7503 * Return codes
af901ca1 7504 * 0 - successful
88a2cfbb 7505 * -ERROR - otherwise.
da0436e9
JS
7506 **/
7507int
7508lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *phba)
7509{
7510 int rc = 0;
da0436e9
JS
7511 struct lpfc_rpi_hdr *rpi_hdr;
7512
7513 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_hdr_list);
ff78d8f9 7514 if (!phba->sli4_hba.rpi_hdrs_in_use)
6d368e53 7515 return rc;
6d368e53
JS
7516 if (phba->sli4_hba.extents_in_use)
7517 return -EIO;
da0436e9
JS
7518
7519 rpi_hdr = lpfc_sli4_create_rpi_hdr(phba);
7520 if (!rpi_hdr) {
372c187b 7521 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
7522 "0391 Error during rpi post operation\n");
7523 lpfc_sli4_remove_rpis(phba);
7524 rc = -ENODEV;
7525 }
7526
7527 return rc;
7528}
7529
7530/**
7531 * lpfc_sli4_create_rpi_hdr - Allocate an rpi header memory region
7532 * @phba: pointer to lpfc hba data structure.
7533 *
7534 * This routine is invoked to allocate a single 4KB memory region to
7535 * support rpis and stores them in the phba. This single region
7536 * provides support for up to 64 rpis. The region is used globally
7537 * by the device.
7538 *
7539 * Returns:
7540 * A valid rpi hdr on success.
7541 * A NULL pointer on any failure.
7542 **/
7543struct lpfc_rpi_hdr *
7544lpfc_sli4_create_rpi_hdr(struct lpfc_hba *phba)
7545{
7546 uint16_t rpi_limit, curr_rpi_range;
7547 struct lpfc_dmabuf *dmabuf;
7548 struct lpfc_rpi_hdr *rpi_hdr;
7549
6d368e53
JS
7550 /*
7551 * If the SLI4 port supports extents, posting the rpi header isn't
7552 * required. Set the expected maximum count and let the actual value
7553 * get set when extents are fully allocated.
7554 */
7555 if (!phba->sli4_hba.rpi_hdrs_in_use)
7556 return NULL;
7557 if (phba->sli4_hba.extents_in_use)
7558 return NULL;
7559
7560 /* The limit on the logical index is just the max_rpi count. */
845d9e8d 7561 rpi_limit = phba->sli4_hba.max_cfg_param.max_rpi;
da0436e9
JS
7562
7563 spin_lock_irq(&phba->hbalock);
6d368e53
JS
7564 /*
7565 * Establish the starting RPI in this header block. The starting
7566 * rpi is normalized to a zero base because the physical rpi is
7567 * port based.
7568 */
97f2ecf1 7569 curr_rpi_range = phba->sli4_hba.next_rpi;
da0436e9
JS
7570 spin_unlock_irq(&phba->hbalock);
7571
845d9e8d
JS
7572 /* Reached full RPI range */
7573 if (curr_rpi_range == rpi_limit)
6d368e53 7574 return NULL;
845d9e8d 7575
da0436e9
JS
7576 /*
7577 * First allocate the protocol header region for the port. The
7578 * port expects a 4KB DMA-mapped memory region that is 4K aligned.
7579 */
7580 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
7581 if (!dmabuf)
7582 return NULL;
7583
750afb08
LC
7584 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
7585 LPFC_HDR_TEMPLATE_SIZE,
7586 &dmabuf->phys, GFP_KERNEL);
da0436e9
JS
7587 if (!dmabuf->virt) {
7588 rpi_hdr = NULL;
7589 goto err_free_dmabuf;
7590 }
7591
da0436e9
JS
7592 if (!IS_ALIGNED(dmabuf->phys, LPFC_HDR_TEMPLATE_SIZE)) {
7593 rpi_hdr = NULL;
7594 goto err_free_coherent;
7595 }
7596
7597 /* Save the rpi header data for cleanup later. */
7598 rpi_hdr = kzalloc(sizeof(struct lpfc_rpi_hdr), GFP_KERNEL);
7599 if (!rpi_hdr)
7600 goto err_free_coherent;
7601
7602 rpi_hdr->dmabuf = dmabuf;
7603 rpi_hdr->len = LPFC_HDR_TEMPLATE_SIZE;
7604 rpi_hdr->page_count = 1;
7605 spin_lock_irq(&phba->hbalock);
6d368e53
JS
7606
7607 /* The rpi_hdr stores the logical index only. */
7608 rpi_hdr->start_rpi = curr_rpi_range;
845d9e8d 7609 rpi_hdr->next_rpi = phba->sli4_hba.next_rpi + LPFC_RPI_HDR_COUNT;
da0436e9
JS
7610 list_add_tail(&rpi_hdr->list, &phba->sli4_hba.lpfc_rpi_hdr_list);
7611
da0436e9
JS
7612 spin_unlock_irq(&phba->hbalock);
7613 return rpi_hdr;
7614
7615 err_free_coherent:
7616 dma_free_coherent(&phba->pcidev->dev, LPFC_HDR_TEMPLATE_SIZE,
7617 dmabuf->virt, dmabuf->phys);
7618 err_free_dmabuf:
7619 kfree(dmabuf);
7620 return NULL;
7621}
7622
7623/**
7624 * lpfc_sli4_remove_rpi_hdrs - Remove all rpi header memory regions
7625 * @phba: pointer to lpfc hba data structure.
7626 *
7627 * This routine is invoked to remove all memory resources allocated
6d368e53
JS
7628 * to support rpis for SLI4 ports not supporting extents. This routine
7629 * presumes the caller has released all rpis consumed by fabric or port
7630 * logins and is prepared to have the header pages removed.
da0436e9
JS
7631 **/
7632void
7633lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *phba)
7634{
7635 struct lpfc_rpi_hdr *rpi_hdr, *next_rpi_hdr;
7636
6d368e53
JS
7637 if (!phba->sli4_hba.rpi_hdrs_in_use)
7638 goto exit;
7639
da0436e9
JS
7640 list_for_each_entry_safe(rpi_hdr, next_rpi_hdr,
7641 &phba->sli4_hba.lpfc_rpi_hdr_list, list) {
7642 list_del(&rpi_hdr->list);
7643 dma_free_coherent(&phba->pcidev->dev, rpi_hdr->len,
7644 rpi_hdr->dmabuf->virt, rpi_hdr->dmabuf->phys);
7645 kfree(rpi_hdr->dmabuf);
7646 kfree(rpi_hdr);
7647 }
6d368e53
JS
7648 exit:
7649 /* There are no rpis available to the port now. */
7650 phba->sli4_hba.next_rpi = 0;
da0436e9
JS
7651}
7652
7653/**
7654 * lpfc_hba_alloc - Allocate driver hba data structure for a device.
7655 * @pdev: pointer to pci device data structure.
7656 *
7657 * This routine is invoked to allocate the driver hba data structure for an
7658 * HBA device. If the allocation is successful, the phba reference to the
7659 * PCI device data structure is set.
7660 *
7661 * Return codes
af901ca1 7662 * pointer to @phba - successful
da0436e9
JS
7663 * NULL - error
7664 **/
7665static struct lpfc_hba *
7666lpfc_hba_alloc(struct pci_dev *pdev)
7667{
7668 struct lpfc_hba *phba;
7669
7670 /* Allocate memory for HBA structure */
7671 phba = kzalloc(sizeof(struct lpfc_hba), GFP_KERNEL);
7672 if (!phba) {
e34ccdfe 7673 dev_err(&pdev->dev, "failed to allocate hba struct\n");
da0436e9
JS
7674 return NULL;
7675 }
7676
7677 /* Set reference to PCI device in HBA structure */
7678 phba->pcidev = pdev;
7679
7680 /* Assign an unused board number */
7681 phba->brd_no = lpfc_get_instance();
7682 if (phba->brd_no < 0) {
7683 kfree(phba);
7684 return NULL;
7685 }
65791f1f 7686 phba->eratt_poll_interval = LPFC_ERATT_POLL_INTERVAL;
da0436e9 7687
4fede78f 7688 spin_lock_init(&phba->ct_ev_lock);
f1c3b0fc
JS
7689 INIT_LIST_HEAD(&phba->ct_ev_waiters);
7690
da0436e9
JS
7691 return phba;
7692}
7693
7694/**
7695 * lpfc_hba_free - Free driver hba data structure with a device.
7696 * @phba: pointer to lpfc hba data structure.
7697 *
7698 * This routine is invoked to free the driver hba data structure with an
7699 * HBA device.
7700 **/
7701static void
7702lpfc_hba_free(struct lpfc_hba *phba)
7703{
5e5b511d
JS
7704 if (phba->sli_rev == LPFC_SLI_REV4)
7705 kfree(phba->sli4_hba.hdwq);
7706
da0436e9
JS
7707 /* Release the driver assigned board number */
7708 idr_remove(&lpfc_hba_index, phba->brd_no);
7709
895427bd
JS
7710 /* Free memory allocated with sli3 rings */
7711 kfree(phba->sli.sli3_ring);
7712 phba->sli.sli3_ring = NULL;
2a76a283 7713
da0436e9
JS
7714 kfree(phba);
7715 return;
7716}
7717
7718/**
7719 * lpfc_create_shost - Create hba physical port with associated scsi host.
7720 * @phba: pointer to lpfc hba data structure.
7721 *
7722 * This routine is invoked to create HBA physical port and associate a SCSI
7723 * host with it.
7724 *
7725 * Return codes
af901ca1 7726 * 0 - successful
da0436e9
JS
7727 * other values - error
7728 **/
7729static int
7730lpfc_create_shost(struct lpfc_hba *phba)
7731{
7732 struct lpfc_vport *vport;
7733 struct Scsi_Host *shost;
7734
7735 /* Initialize HBA FC structure */
7736 phba->fc_edtov = FF_DEF_EDTOV;
7737 phba->fc_ratov = FF_DEF_RATOV;
7738 phba->fc_altov = FF_DEF_ALTOV;
7739 phba->fc_arbtov = FF_DEF_ARBTOV;
7740
d7c47992 7741 atomic_set(&phba->sdev_cnt, 0);
da0436e9
JS
7742 vport = lpfc_create_port(phba, phba->brd_no, &phba->pcidev->dev);
7743 if (!vport)
7744 return -ENODEV;
7745
7746 shost = lpfc_shost_from_vport(vport);
7747 phba->pport = vport;
2ea259ee 7748
f358dd0c
JS
7749 if (phba->nvmet_support) {
7750 /* Only 1 vport (pport) will support NVME target */
ea85a20c
JS
7751 phba->targetport = NULL;
7752 phba->cfg_enable_fc4_type = LPFC_ENABLE_NVME;
7753 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME_DISC,
7754 "6076 NVME Target Found\n");
f358dd0c
JS
7755 }
7756
da0436e9
JS
7757 lpfc_debugfs_initialize(vport);
7758 /* Put reference to SCSI host to driver's device private data */
7759 pci_set_drvdata(phba->pcidev, shost);
2e0fef85 7760
4258e98e
JS
7761 /*
7762 * At this point we are fully registered with PSA. In addition,
7763 * any initial discovery should be completed.
7764 */
7765 vport->load_flag |= FC_ALLOW_FDMI;
8663cbbe
JS
7766 if (phba->cfg_enable_SmartSAN ||
7767 (phba->cfg_fdmi_on == LPFC_FDMI_SUPPORT)) {
4258e98e
JS
7768
7769 /* Setup appropriate attribute masks */
7770 vport->fdmi_hba_mask = LPFC_FDMI2_HBA_ATTR;
8663cbbe 7771 if (phba->cfg_enable_SmartSAN)
4258e98e
JS
7772 vport->fdmi_port_mask = LPFC_FDMI2_SMART_ATTR;
7773 else
7774 vport->fdmi_port_mask = LPFC_FDMI2_PORT_ATTR;
7775 }
3772a991
JS
7776 return 0;
7777}
db2378e0 7778
3772a991
JS
7779/**
7780 * lpfc_destroy_shost - Destroy hba physical port with associated scsi host.
7781 * @phba: pointer to lpfc hba data structure.
7782 *
7783 * This routine is invoked to destroy HBA physical port and the associated
7784 * SCSI host.
7785 **/
7786static void
7787lpfc_destroy_shost(struct lpfc_hba *phba)
7788{
7789 struct lpfc_vport *vport = phba->pport;
7790
7791 /* Destroy physical port that associated with the SCSI host */
7792 destroy_port(vport);
7793
7794 return;
7795}
7796
7797/**
7798 * lpfc_setup_bg - Setup Block guard structures and debug areas.
7799 * @phba: pointer to lpfc hba data structure.
7800 * @shost: the shost to be used to detect Block guard settings.
7801 *
7802 * This routine sets up the local Block guard protocol settings for @shost.
7803 * This routine also allocates memory for debugging bg buffers.
7804 **/
7805static void
7806lpfc_setup_bg(struct lpfc_hba *phba, struct Scsi_Host *shost)
7807{
bbeb79b9
JS
7808 uint32_t old_mask;
7809 uint32_t old_guard;
7810
b3b98b74 7811 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
3772a991
JS
7812 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7813 "1478 Registering BlockGuard with the "
7814 "SCSI layer\n");
bbeb79b9 7815
b3b98b74
JS
7816 old_mask = phba->cfg_prot_mask;
7817 old_guard = phba->cfg_prot_guard;
bbeb79b9
JS
7818
7819 /* Only allow supported values */
b3b98b74 7820 phba->cfg_prot_mask &= (SHOST_DIF_TYPE1_PROTECTION |
bbeb79b9
JS
7821 SHOST_DIX_TYPE0_PROTECTION |
7822 SHOST_DIX_TYPE1_PROTECTION);
b3b98b74
JS
7823 phba->cfg_prot_guard &= (SHOST_DIX_GUARD_IP |
7824 SHOST_DIX_GUARD_CRC);
bbeb79b9
JS
7825
7826 /* DIF Type 1 protection for profiles AST1/C1 is end to end */
b3b98b74
JS
7827 if (phba->cfg_prot_mask == SHOST_DIX_TYPE1_PROTECTION)
7828 phba->cfg_prot_mask |= SHOST_DIF_TYPE1_PROTECTION;
bbeb79b9 7829
b3b98b74
JS
7830 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
7831 if ((old_mask != phba->cfg_prot_mask) ||
7832 (old_guard != phba->cfg_prot_guard))
372c187b 7833 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
bbeb79b9
JS
7834 "1475 Registering BlockGuard with the "
7835 "SCSI layer: mask %d guard %d\n",
b3b98b74
JS
7836 phba->cfg_prot_mask,
7837 phba->cfg_prot_guard);
bbeb79b9 7838
b3b98b74
JS
7839 scsi_host_set_prot(shost, phba->cfg_prot_mask);
7840 scsi_host_set_guard(shost, phba->cfg_prot_guard);
bbeb79b9 7841 } else
372c187b 7842 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
bbeb79b9
JS
7843 "1479 Not Registering BlockGuard with the SCSI "
7844 "layer, Bad protection parameters: %d %d\n",
7845 old_mask, old_guard);
3772a991 7846 }
3772a991
JS
7847}
7848
7849/**
7850 * lpfc_post_init_setup - Perform necessary device post initialization setup.
7851 * @phba: pointer to lpfc hba data structure.
7852 *
7853 * This routine is invoked to perform all the necessary post initialization
7854 * setup for the device.
7855 **/
7856static void
7857lpfc_post_init_setup(struct lpfc_hba *phba)
7858{
7859 struct Scsi_Host *shost;
7860 struct lpfc_adapter_event_header adapter_event;
7861
7862 /* Get the default values for Model Name and Description */
7863 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
7864
7865 /*
7866 * hba setup may have changed the hba_queue_depth so we need to
7867 * adjust the value of can_queue.
7868 */
7869 shost = pci_get_drvdata(phba->pcidev);
7870 shost->can_queue = phba->cfg_hba_queue_depth - 10;
3772a991
JS
7871
7872 lpfc_host_attrib_init(shost);
7873
7874 if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
7875 spin_lock_irq(shost->host_lock);
7876 lpfc_poll_start_timer(phba);
7877 spin_unlock_irq(shost->host_lock);
7878 }
7879
7880 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7881 "0428 Perform SCSI scan\n");
7882 /* Send board arrival event to upper layer */
7883 adapter_event.event_type = FC_REG_ADAPTER_EVENT;
7884 adapter_event.subcategory = LPFC_EVENT_ARRIVAL;
7885 fc_host_post_vendor_event(shost, fc_get_event_number(),
7886 sizeof(adapter_event),
7887 (char *) &adapter_event,
7888 LPFC_NL_VENDOR_ID);
7889 return;
7890}
7891
7892/**
7893 * lpfc_sli_pci_mem_setup - Setup SLI3 HBA PCI memory space.
7894 * @phba: pointer to lpfc hba data structure.
7895 *
7896 * This routine is invoked to set up the PCI device memory space for device
7897 * with SLI-3 interface spec.
7898 *
7899 * Return codes
af901ca1 7900 * 0 - successful
3772a991
JS
7901 * other values - error
7902 **/
7903static int
7904lpfc_sli_pci_mem_setup(struct lpfc_hba *phba)
7905{
f30e1bfd 7906 struct pci_dev *pdev = phba->pcidev;
3772a991
JS
7907 unsigned long bar0map_len, bar2map_len;
7908 int i, hbq_count;
7909 void *ptr;
56de8357 7910 int error;
3772a991 7911
f30e1bfd 7912 if (!pdev)
56de8357 7913 return -ENODEV;
3772a991
JS
7914
7915 /* Set the device DMA mask size */
56de8357
HR
7916 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7917 if (error)
7918 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7919 if (error)
f30e1bfd 7920 return error;
56de8357 7921 error = -ENODEV;
3772a991
JS
7922
7923 /* Get the bus address of Bar0 and Bar2 and the number of bytes
7924 * required by each mapping.
7925 */
7926 phba->pci_bar0_map = pci_resource_start(pdev, 0);
7927 bar0map_len = pci_resource_len(pdev, 0);
7928
7929 phba->pci_bar2_map = pci_resource_start(pdev, 2);
7930 bar2map_len = pci_resource_len(pdev, 2);
7931
7932 /* Map HBA SLIM to a kernel virtual address. */
7933 phba->slim_memmap_p = ioremap(phba->pci_bar0_map, bar0map_len);
7934 if (!phba->slim_memmap_p) {
7935 dev_printk(KERN_ERR, &pdev->dev,
7936 "ioremap failed for SLIM memory.\n");
7937 goto out;
7938 }
7939
7940 /* Map HBA Control Registers to a kernel virtual address. */
7941 phba->ctrl_regs_memmap_p = ioremap(phba->pci_bar2_map, bar2map_len);
7942 if (!phba->ctrl_regs_memmap_p) {
7943 dev_printk(KERN_ERR, &pdev->dev,
7944 "ioremap failed for HBA control registers.\n");
7945 goto out_iounmap_slim;
7946 }
7947
7948 /* Allocate memory for SLI-2 structures */
750afb08
LC
7949 phba->slim2p.virt = dma_alloc_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7950 &phba->slim2p.phys, GFP_KERNEL);
3772a991
JS
7951 if (!phba->slim2p.virt)
7952 goto out_iounmap;
7953
3772a991 7954 phba->mbox = phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, mbx);
7a470277
JS
7955 phba->mbox_ext = (phba->slim2p.virt +
7956 offsetof(struct lpfc_sli2_slim, mbx_ext_words));
3772a991
JS
7957 phba->pcb = (phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, pcb));
7958 phba->IOCBs = (phba->slim2p.virt +
7959 offsetof(struct lpfc_sli2_slim, IOCBs));
7960
7961 phba->hbqslimp.virt = dma_alloc_coherent(&pdev->dev,
7962 lpfc_sli_hbq_size(),
7963 &phba->hbqslimp.phys,
7964 GFP_KERNEL);
7965 if (!phba->hbqslimp.virt)
7966 goto out_free_slim;
7967
7968 hbq_count = lpfc_sli_hbq_count();
7969 ptr = phba->hbqslimp.virt;
7970 for (i = 0; i < hbq_count; ++i) {
7971 phba->hbqs[i].hbq_virt = ptr;
7972 INIT_LIST_HEAD(&phba->hbqs[i].hbq_buffer_list);
7973 ptr += (lpfc_hbq_defs[i]->entry_count *
7974 sizeof(struct lpfc_hbq_entry));
7975 }
7976 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_els_hbq_alloc;
7977 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_els_hbq_free;
7978
7979 memset(phba->hbqslimp.virt, 0, lpfc_sli_hbq_size());
7980
3772a991
JS
7981 phba->MBslimaddr = phba->slim_memmap_p;
7982 phba->HAregaddr = phba->ctrl_regs_memmap_p + HA_REG_OFFSET;
7983 phba->CAregaddr = phba->ctrl_regs_memmap_p + CA_REG_OFFSET;
7984 phba->HSregaddr = phba->ctrl_regs_memmap_p + HS_REG_OFFSET;
7985 phba->HCregaddr = phba->ctrl_regs_memmap_p + HC_REG_OFFSET;
7986
7987 return 0;
7988
7989out_free_slim:
7990 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7991 phba->slim2p.virt, phba->slim2p.phys);
7992out_iounmap:
7993 iounmap(phba->ctrl_regs_memmap_p);
7994out_iounmap_slim:
7995 iounmap(phba->slim_memmap_p);
7996out:
7997 return error;
7998}
7999
8000/**
8001 * lpfc_sli_pci_mem_unset - Unset SLI3 HBA PCI memory space.
8002 * @phba: pointer to lpfc hba data structure.
8003 *
8004 * This routine is invoked to unset the PCI device memory space for device
8005 * with SLI-3 interface spec.
8006 **/
8007static void
8008lpfc_sli_pci_mem_unset(struct lpfc_hba *phba)
8009{
8010 struct pci_dev *pdev;
8011
8012 /* Obtain PCI device reference */
8013 if (!phba->pcidev)
8014 return;
8015 else
8016 pdev = phba->pcidev;
8017
8018 /* Free coherent DMA memory allocated */
8019 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
8020 phba->hbqslimp.virt, phba->hbqslimp.phys);
8021 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
8022 phba->slim2p.virt, phba->slim2p.phys);
8023
8024 /* I/O memory unmap */
8025 iounmap(phba->ctrl_regs_memmap_p);
8026 iounmap(phba->slim_memmap_p);
8027
8028 return;
8029}
8030
8031/**
da0436e9 8032 * lpfc_sli4_post_status_check - Wait for SLI4 POST done and check status
3772a991
JS
8033 * @phba: pointer to lpfc hba data structure.
8034 *
da0436e9
JS
8035 * This routine is invoked to wait for SLI4 device Power On Self Test (POST)
8036 * done and check status.
3772a991 8037 *
da0436e9 8038 * Return 0 if successful, otherwise -ENODEV.
3772a991 8039 **/
da0436e9
JS
8040int
8041lpfc_sli4_post_status_check(struct lpfc_hba *phba)
3772a991 8042{
2fcee4bf
JS
8043 struct lpfc_register portsmphr_reg, uerrlo_reg, uerrhi_reg;
8044 struct lpfc_register reg_data;
8045 int i, port_error = 0;
8046 uint32_t if_type;
3772a991 8047
9940b97b
JS
8048 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
8049 memset(&reg_data, 0, sizeof(reg_data));
2fcee4bf 8050 if (!phba->sli4_hba.PSMPHRregaddr)
da0436e9 8051 return -ENODEV;
3772a991 8052
da0436e9
JS
8053 /* Wait up to 30 seconds for the SLI Port POST done and ready */
8054 for (i = 0; i < 3000; i++) {
9940b97b
JS
8055 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
8056 &portsmphr_reg.word0) ||
8057 (bf_get(lpfc_port_smphr_perr, &portsmphr_reg))) {
2fcee4bf 8058 /* Port has a fatal POST error, break out */
da0436e9
JS
8059 port_error = -ENODEV;
8060 break;
8061 }
2fcee4bf
JS
8062 if (LPFC_POST_STAGE_PORT_READY ==
8063 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg))
da0436e9 8064 break;
da0436e9 8065 msleep(10);
3772a991
JS
8066 }
8067
2fcee4bf
JS
8068 /*
8069 * If there was a port error during POST, then don't proceed with
8070 * other register reads as the data may not be valid. Just exit.
8071 */
8072 if (port_error) {
372c187b 8073 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
8074 "1408 Port Failed POST - portsmphr=0x%x, "
8075 "perr=x%x, sfi=x%x, nip=x%x, ipc=x%x, scr1=x%x, "
8076 "scr2=x%x, hscratch=x%x, pstatus=x%x\n",
8077 portsmphr_reg.word0,
8078 bf_get(lpfc_port_smphr_perr, &portsmphr_reg),
8079 bf_get(lpfc_port_smphr_sfi, &portsmphr_reg),
8080 bf_get(lpfc_port_smphr_nip, &portsmphr_reg),
8081 bf_get(lpfc_port_smphr_ipc, &portsmphr_reg),
8082 bf_get(lpfc_port_smphr_scr1, &portsmphr_reg),
8083 bf_get(lpfc_port_smphr_scr2, &portsmphr_reg),
8084 bf_get(lpfc_port_smphr_host_scratch, &portsmphr_reg),
8085 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg));
8086 } else {
28baac74 8087 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
2fcee4bf
JS
8088 "2534 Device Info: SLIFamily=0x%x, "
8089 "SLIRev=0x%x, IFType=0x%x, SLIHint_1=0x%x, "
8090 "SLIHint_2=0x%x, FT=0x%x\n",
28baac74
JS
8091 bf_get(lpfc_sli_intf_sli_family,
8092 &phba->sli4_hba.sli_intf),
8093 bf_get(lpfc_sli_intf_slirev,
8094 &phba->sli4_hba.sli_intf),
085c647c
JS
8095 bf_get(lpfc_sli_intf_if_type,
8096 &phba->sli4_hba.sli_intf),
8097 bf_get(lpfc_sli_intf_sli_hint1,
28baac74 8098 &phba->sli4_hba.sli_intf),
085c647c
JS
8099 bf_get(lpfc_sli_intf_sli_hint2,
8100 &phba->sli4_hba.sli_intf),
8101 bf_get(lpfc_sli_intf_func_type,
28baac74 8102 &phba->sli4_hba.sli_intf));
2fcee4bf
JS
8103 /*
8104 * Check for other Port errors during the initialization
8105 * process. Fail the load if the port did not come up
8106 * correctly.
8107 */
8108 if_type = bf_get(lpfc_sli_intf_if_type,
8109 &phba->sli4_hba.sli_intf);
8110 switch (if_type) {
8111 case LPFC_SLI_INTF_IF_TYPE_0:
8112 phba->sli4_hba.ue_mask_lo =
8113 readl(phba->sli4_hba.u.if_type0.UEMASKLOregaddr);
8114 phba->sli4_hba.ue_mask_hi =
8115 readl(phba->sli4_hba.u.if_type0.UEMASKHIregaddr);
8116 uerrlo_reg.word0 =
8117 readl(phba->sli4_hba.u.if_type0.UERRLOregaddr);
8118 uerrhi_reg.word0 =
8119 readl(phba->sli4_hba.u.if_type0.UERRHIregaddr);
8120 if ((~phba->sli4_hba.ue_mask_lo & uerrlo_reg.word0) ||
8121 (~phba->sli4_hba.ue_mask_hi & uerrhi_reg.word0)) {
372c187b
DK
8122 lpfc_printf_log(phba, KERN_ERR,
8123 LOG_TRACE_EVENT,
2fcee4bf
JS
8124 "1422 Unrecoverable Error "
8125 "Detected during POST "
8126 "uerr_lo_reg=0x%x, "
8127 "uerr_hi_reg=0x%x, "
8128 "ue_mask_lo_reg=0x%x, "
8129 "ue_mask_hi_reg=0x%x\n",
8130 uerrlo_reg.word0,
8131 uerrhi_reg.word0,
8132 phba->sli4_hba.ue_mask_lo,
8133 phba->sli4_hba.ue_mask_hi);
8134 port_error = -ENODEV;
8135 }
8136 break;
8137 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 8138 case LPFC_SLI_INTF_IF_TYPE_6:
2fcee4bf 8139 /* Final checks. The port status should be clean. */
9940b97b
JS
8140 if (lpfc_readl(phba->sli4_hba.u.if_type2.STATUSregaddr,
8141 &reg_data.word0) ||
0558056c
JS
8142 (bf_get(lpfc_sliport_status_err, &reg_data) &&
8143 !bf_get(lpfc_sliport_status_rn, &reg_data))) {
2fcee4bf
JS
8144 phba->work_status[0] =
8145 readl(phba->sli4_hba.u.if_type2.
8146 ERR1regaddr);
8147 phba->work_status[1] =
8148 readl(phba->sli4_hba.u.if_type2.
8149 ERR2regaddr);
372c187b 8150 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
8fcb8acd
JS
8151 "2888 Unrecoverable port error "
8152 "following POST: port status reg "
8153 "0x%x, port_smphr reg 0x%x, "
2fcee4bf
JS
8154 "error 1=0x%x, error 2=0x%x\n",
8155 reg_data.word0,
8156 portsmphr_reg.word0,
8157 phba->work_status[0],
8158 phba->work_status[1]);
8159 port_error = -ENODEV;
8160 }
8161 break;
8162 case LPFC_SLI_INTF_IF_TYPE_1:
8163 default:
8164 break;
8165 }
28baac74 8166 }
da0436e9
JS
8167 return port_error;
8168}
3772a991 8169
da0436e9
JS
8170/**
8171 * lpfc_sli4_bar0_register_memmap - Set up SLI4 BAR0 register memory map.
8172 * @phba: pointer to lpfc hba data structure.
2fcee4bf 8173 * @if_type: The SLI4 interface type getting configured.
da0436e9
JS
8174 *
8175 * This routine is invoked to set up SLI4 BAR0 PCI config space register
8176 * memory map.
8177 **/
8178static void
2fcee4bf
JS
8179lpfc_sli4_bar0_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
8180{
8181 switch (if_type) {
8182 case LPFC_SLI_INTF_IF_TYPE_0:
8183 phba->sli4_hba.u.if_type0.UERRLOregaddr =
8184 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_LO;
8185 phba->sli4_hba.u.if_type0.UERRHIregaddr =
8186 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_HI;
8187 phba->sli4_hba.u.if_type0.UEMASKLOregaddr =
8188 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_LO;
8189 phba->sli4_hba.u.if_type0.UEMASKHIregaddr =
8190 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_HI;
8191 phba->sli4_hba.SLIINTFregaddr =
8192 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
8193 break;
8194 case LPFC_SLI_INTF_IF_TYPE_2:
0cf07f84
JS
8195 phba->sli4_hba.u.if_type2.EQDregaddr =
8196 phba->sli4_hba.conf_regs_memmap_p +
8197 LPFC_CTL_PORT_EQ_DELAY_OFFSET;
2fcee4bf 8198 phba->sli4_hba.u.if_type2.ERR1regaddr =
88a2cfbb
JS
8199 phba->sli4_hba.conf_regs_memmap_p +
8200 LPFC_CTL_PORT_ER1_OFFSET;
2fcee4bf 8201 phba->sli4_hba.u.if_type2.ERR2regaddr =
88a2cfbb
JS
8202 phba->sli4_hba.conf_regs_memmap_p +
8203 LPFC_CTL_PORT_ER2_OFFSET;
2fcee4bf 8204 phba->sli4_hba.u.if_type2.CTRLregaddr =
88a2cfbb
JS
8205 phba->sli4_hba.conf_regs_memmap_p +
8206 LPFC_CTL_PORT_CTL_OFFSET;
2fcee4bf 8207 phba->sli4_hba.u.if_type2.STATUSregaddr =
88a2cfbb
JS
8208 phba->sli4_hba.conf_regs_memmap_p +
8209 LPFC_CTL_PORT_STA_OFFSET;
2fcee4bf
JS
8210 phba->sli4_hba.SLIINTFregaddr =
8211 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
8212 phba->sli4_hba.PSMPHRregaddr =
88a2cfbb
JS
8213 phba->sli4_hba.conf_regs_memmap_p +
8214 LPFC_CTL_PORT_SEM_OFFSET;
2fcee4bf 8215 phba->sli4_hba.RQDBregaddr =
962bc51b
JS
8216 phba->sli4_hba.conf_regs_memmap_p +
8217 LPFC_ULP0_RQ_DOORBELL;
2fcee4bf 8218 phba->sli4_hba.WQDBregaddr =
962bc51b
JS
8219 phba->sli4_hba.conf_regs_memmap_p +
8220 LPFC_ULP0_WQ_DOORBELL;
9dd35425 8221 phba->sli4_hba.CQDBregaddr =
2fcee4bf 8222 phba->sli4_hba.conf_regs_memmap_p + LPFC_EQCQ_DOORBELL;
9dd35425 8223 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.CQDBregaddr;
2fcee4bf
JS
8224 phba->sli4_hba.MQDBregaddr =
8225 phba->sli4_hba.conf_regs_memmap_p + LPFC_MQ_DOORBELL;
8226 phba->sli4_hba.BMBXregaddr =
8227 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
8228 break;
27d6ac0a
JS
8229 case LPFC_SLI_INTF_IF_TYPE_6:
8230 phba->sli4_hba.u.if_type2.EQDregaddr =
8231 phba->sli4_hba.conf_regs_memmap_p +
8232 LPFC_CTL_PORT_EQ_DELAY_OFFSET;
8233 phba->sli4_hba.u.if_type2.ERR1regaddr =
8234 phba->sli4_hba.conf_regs_memmap_p +
8235 LPFC_CTL_PORT_ER1_OFFSET;
8236 phba->sli4_hba.u.if_type2.ERR2regaddr =
8237 phba->sli4_hba.conf_regs_memmap_p +
8238 LPFC_CTL_PORT_ER2_OFFSET;
8239 phba->sli4_hba.u.if_type2.CTRLregaddr =
8240 phba->sli4_hba.conf_regs_memmap_p +
8241 LPFC_CTL_PORT_CTL_OFFSET;
8242 phba->sli4_hba.u.if_type2.STATUSregaddr =
8243 phba->sli4_hba.conf_regs_memmap_p +
8244 LPFC_CTL_PORT_STA_OFFSET;
8245 phba->sli4_hba.PSMPHRregaddr =
8246 phba->sli4_hba.conf_regs_memmap_p +
8247 LPFC_CTL_PORT_SEM_OFFSET;
8248 phba->sli4_hba.BMBXregaddr =
8249 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
8250 break;
2fcee4bf
JS
8251 case LPFC_SLI_INTF_IF_TYPE_1:
8252 default:
8253 dev_printk(KERN_ERR, &phba->pcidev->dev,
8254 "FATAL - unsupported SLI4 interface type - %d\n",
8255 if_type);
8256 break;
8257 }
da0436e9 8258}
3772a991 8259
da0436e9
JS
8260/**
8261 * lpfc_sli4_bar1_register_memmap - Set up SLI4 BAR1 register memory map.
8262 * @phba: pointer to lpfc hba data structure.
fe614acd 8263 * @if_type: sli if type to operate on.
da0436e9 8264 *
27d6ac0a 8265 * This routine is invoked to set up SLI4 BAR1 register memory map.
da0436e9
JS
8266 **/
8267static void
27d6ac0a 8268lpfc_sli4_bar1_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
da0436e9 8269{
27d6ac0a
JS
8270 switch (if_type) {
8271 case LPFC_SLI_INTF_IF_TYPE_0:
8272 phba->sli4_hba.PSMPHRregaddr =
8273 phba->sli4_hba.ctrl_regs_memmap_p +
8274 LPFC_SLIPORT_IF0_SMPHR;
8275 phba->sli4_hba.ISRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8276 LPFC_HST_ISR0;
8277 phba->sli4_hba.IMRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8278 LPFC_HST_IMR0;
8279 phba->sli4_hba.ISCRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8280 LPFC_HST_ISCR0;
8281 break;
8282 case LPFC_SLI_INTF_IF_TYPE_6:
8283 phba->sli4_hba.RQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8284 LPFC_IF6_RQ_DOORBELL;
8285 phba->sli4_hba.WQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8286 LPFC_IF6_WQ_DOORBELL;
8287 phba->sli4_hba.CQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8288 LPFC_IF6_CQ_DOORBELL;
8289 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8290 LPFC_IF6_EQ_DOORBELL;
8291 phba->sli4_hba.MQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8292 LPFC_IF6_MQ_DOORBELL;
8293 break;
8294 case LPFC_SLI_INTF_IF_TYPE_2:
8295 case LPFC_SLI_INTF_IF_TYPE_1:
8296 default:
8297 dev_err(&phba->pcidev->dev,
8298 "FATAL - unsupported SLI4 interface type - %d\n",
8299 if_type);
8300 break;
8301 }
3772a991
JS
8302}
8303
8304/**
da0436e9 8305 * lpfc_sli4_bar2_register_memmap - Set up SLI4 BAR2 register memory map.
3772a991 8306 * @phba: pointer to lpfc hba data structure.
da0436e9 8307 * @vf: virtual function number
3772a991 8308 *
da0436e9
JS
8309 * This routine is invoked to set up SLI4 BAR2 doorbell register memory map
8310 * based on the given viftual function number, @vf.
8311 *
8312 * Return 0 if successful, otherwise -ENODEV.
3772a991 8313 **/
da0436e9
JS
8314static int
8315lpfc_sli4_bar2_register_memmap(struct lpfc_hba *phba, uint32_t vf)
3772a991 8316{
da0436e9
JS
8317 if (vf > LPFC_VIR_FUNC_MAX)
8318 return -ENODEV;
3772a991 8319
da0436e9 8320 phba->sli4_hba.RQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
962bc51b
JS
8321 vf * LPFC_VFR_PAGE_SIZE +
8322 LPFC_ULP0_RQ_DOORBELL);
da0436e9 8323 phba->sli4_hba.WQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
962bc51b
JS
8324 vf * LPFC_VFR_PAGE_SIZE +
8325 LPFC_ULP0_WQ_DOORBELL);
9dd35425
JS
8326 phba->sli4_hba.CQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8327 vf * LPFC_VFR_PAGE_SIZE +
8328 LPFC_EQCQ_DOORBELL);
8329 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.CQDBregaddr;
da0436e9
JS
8330 phba->sli4_hba.MQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8331 vf * LPFC_VFR_PAGE_SIZE + LPFC_MQ_DOORBELL);
8332 phba->sli4_hba.BMBXregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8333 vf * LPFC_VFR_PAGE_SIZE + LPFC_BMBX);
8334 return 0;
3772a991
JS
8335}
8336
8337/**
da0436e9 8338 * lpfc_create_bootstrap_mbox - Create the bootstrap mailbox
3772a991
JS
8339 * @phba: pointer to lpfc hba data structure.
8340 *
da0436e9
JS
8341 * This routine is invoked to create the bootstrap mailbox
8342 * region consistent with the SLI-4 interface spec. This
8343 * routine allocates all memory necessary to communicate
8344 * mailbox commands to the port and sets up all alignment
8345 * needs. No locks are expected to be held when calling
8346 * this routine.
3772a991
JS
8347 *
8348 * Return codes
af901ca1 8349 * 0 - successful
d439d286 8350 * -ENOMEM - could not allocated memory.
da0436e9 8351 **/
3772a991 8352static int
da0436e9 8353lpfc_create_bootstrap_mbox(struct lpfc_hba *phba)
3772a991 8354{
da0436e9
JS
8355 uint32_t bmbx_size;
8356 struct lpfc_dmabuf *dmabuf;
8357 struct dma_address *dma_address;
8358 uint32_t pa_addr;
8359 uint64_t phys_addr;
8360
8361 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
8362 if (!dmabuf)
8363 return -ENOMEM;
3772a991 8364
da0436e9
JS
8365 /*
8366 * The bootstrap mailbox region is comprised of 2 parts
8367 * plus an alignment restriction of 16 bytes.
8368 */
8369 bmbx_size = sizeof(struct lpfc_bmbx_create) + (LPFC_ALIGN_16_BYTE - 1);
750afb08
LC
8370 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev, bmbx_size,
8371 &dmabuf->phys, GFP_KERNEL);
da0436e9
JS
8372 if (!dmabuf->virt) {
8373 kfree(dmabuf);
8374 return -ENOMEM;
3772a991
JS
8375 }
8376
da0436e9
JS
8377 /*
8378 * Initialize the bootstrap mailbox pointers now so that the register
8379 * operations are simple later. The mailbox dma address is required
8380 * to be 16-byte aligned. Also align the virtual memory as each
8381 * maibox is copied into the bmbx mailbox region before issuing the
8382 * command to the port.
8383 */
8384 phba->sli4_hba.bmbx.dmabuf = dmabuf;
8385 phba->sli4_hba.bmbx.bmbx_size = bmbx_size;
8386
8387 phba->sli4_hba.bmbx.avirt = PTR_ALIGN(dmabuf->virt,
8388 LPFC_ALIGN_16_BYTE);
8389 phba->sli4_hba.bmbx.aphys = ALIGN(dmabuf->phys,
8390 LPFC_ALIGN_16_BYTE);
8391
8392 /*
8393 * Set the high and low physical addresses now. The SLI4 alignment
8394 * requirement is 16 bytes and the mailbox is posted to the port
8395 * as two 30-bit addresses. The other data is a bit marking whether
8396 * the 30-bit address is the high or low address.
8397 * Upcast bmbx aphys to 64bits so shift instruction compiles
8398 * clean on 32 bit machines.
8399 */
8400 dma_address = &phba->sli4_hba.bmbx.dma_address;
8401 phys_addr = (uint64_t)phba->sli4_hba.bmbx.aphys;
8402 pa_addr = (uint32_t) ((phys_addr >> 34) & 0x3fffffff);
8403 dma_address->addr_hi = (uint32_t) ((pa_addr << 2) |
8404 LPFC_BMBX_BIT1_ADDR_HI);
8405
8406 pa_addr = (uint32_t) ((phba->sli4_hba.bmbx.aphys >> 4) & 0x3fffffff);
8407 dma_address->addr_lo = (uint32_t) ((pa_addr << 2) |
8408 LPFC_BMBX_BIT1_ADDR_LO);
8409 return 0;
3772a991
JS
8410}
8411
8412/**
da0436e9 8413 * lpfc_destroy_bootstrap_mbox - Destroy all bootstrap mailbox resources
3772a991
JS
8414 * @phba: pointer to lpfc hba data structure.
8415 *
da0436e9
JS
8416 * This routine is invoked to teardown the bootstrap mailbox
8417 * region and release all host resources. This routine requires
8418 * the caller to ensure all mailbox commands recovered, no
8419 * additional mailbox comands are sent, and interrupts are disabled
8420 * before calling this routine.
8421 *
8422 **/
3772a991 8423static void
da0436e9 8424lpfc_destroy_bootstrap_mbox(struct lpfc_hba *phba)
3772a991 8425{
da0436e9
JS
8426 dma_free_coherent(&phba->pcidev->dev,
8427 phba->sli4_hba.bmbx.bmbx_size,
8428 phba->sli4_hba.bmbx.dmabuf->virt,
8429 phba->sli4_hba.bmbx.dmabuf->phys);
8430
8431 kfree(phba->sli4_hba.bmbx.dmabuf);
8432 memset(&phba->sli4_hba.bmbx, 0, sizeof(struct lpfc_bmbx));
3772a991
JS
8433}
8434
83c6cb1a
JS
8435static const char * const lpfc_topo_to_str[] = {
8436 "Loop then P2P",
8437 "Loopback",
8438 "P2P Only",
8439 "Unsupported",
8440 "Loop Only",
8441 "Unsupported",
8442 "P2P then Loop",
8443};
8444
fe614acd
LJ
8445#define LINK_FLAGS_DEF 0x0
8446#define LINK_FLAGS_P2P 0x1
8447#define LINK_FLAGS_LOOP 0x2
83c6cb1a
JS
8448/**
8449 * lpfc_map_topology - Map the topology read from READ_CONFIG
8450 * @phba: pointer to lpfc hba data structure.
fe614acd 8451 * @rd_config: pointer to read config data
83c6cb1a
JS
8452 *
8453 * This routine is invoked to map the topology values as read
8454 * from the read config mailbox command. If the persistent
8455 * topology feature is supported, the firmware will provide the
8456 * saved topology information to be used in INIT_LINK
83c6cb1a 8457 **/
83c6cb1a
JS
8458static void
8459lpfc_map_topology(struct lpfc_hba *phba, struct lpfc_mbx_read_config *rd_config)
8460{
8461 u8 ptv, tf, pt;
8462
8463 ptv = bf_get(lpfc_mbx_rd_conf_ptv, rd_config);
8464 tf = bf_get(lpfc_mbx_rd_conf_tf, rd_config);
8465 pt = bf_get(lpfc_mbx_rd_conf_pt, rd_config);
8466
8467 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8468 "2027 Read Config Data : ptv:0x%x, tf:0x%x pt:0x%x",
8469 ptv, tf, pt);
8470 if (!ptv) {
8471 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
8472 "2019 FW does not support persistent topology "
8473 "Using driver parameter defined value [%s]",
8474 lpfc_topo_to_str[phba->cfg_topology]);
8475 return;
8476 }
8477 /* FW supports persistent topology - override module parameter value */
8478 phba->hba_flag |= HBA_PERSISTENT_TOPO;
8479 switch (phba->pcidev->device) {
8480 case PCI_DEVICE_ID_LANCER_G7_FC:
83c6cb1a
JS
8481 case PCI_DEVICE_ID_LANCER_G6_FC:
8482 if (!tf) {
8483 phba->cfg_topology = ((pt == LINK_FLAGS_LOOP)
8484 ? FLAGS_TOPOLOGY_MODE_LOOP
8485 : FLAGS_TOPOLOGY_MODE_PT_PT);
8486 } else {
8487 phba->hba_flag &= ~HBA_PERSISTENT_TOPO;
8488 }
8489 break;
8490 default: /* G5 */
8491 if (tf) {
8492 /* If topology failover set - pt is '0' or '1' */
8493 phba->cfg_topology = (pt ? FLAGS_TOPOLOGY_MODE_PT_LOOP :
8494 FLAGS_TOPOLOGY_MODE_LOOP_PT);
8495 } else {
8496 phba->cfg_topology = ((pt == LINK_FLAGS_P2P)
8497 ? FLAGS_TOPOLOGY_MODE_PT_PT
8498 : FLAGS_TOPOLOGY_MODE_LOOP);
8499 }
8500 break;
8501 }
8502 if (phba->hba_flag & HBA_PERSISTENT_TOPO) {
8503 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8504 "2020 Using persistent topology value [%s]",
8505 lpfc_topo_to_str[phba->cfg_topology]);
8506 } else {
8507 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
8508 "2021 Invalid topology values from FW "
8509 "Using driver parameter defined value [%s]",
8510 lpfc_topo_to_str[phba->cfg_topology]);
8511 }
8512}
8513
3772a991 8514/**
da0436e9 8515 * lpfc_sli4_read_config - Get the config parameters.
3772a991
JS
8516 * @phba: pointer to lpfc hba data structure.
8517 *
da0436e9
JS
8518 * This routine is invoked to read the configuration parameters from the HBA.
8519 * The configuration parameters are used to set the base and maximum values
8520 * for RPI's XRI's VPI's VFI's and FCFIs. These values also affect the resource
8521 * allocation for the port.
3772a991
JS
8522 *
8523 * Return codes
af901ca1 8524 * 0 - successful
25985edc 8525 * -ENOMEM - No available memory
d439d286 8526 * -EIO - The mailbox failed to complete successfully.
3772a991 8527 **/
ff78d8f9 8528int
da0436e9 8529lpfc_sli4_read_config(struct lpfc_hba *phba)
3772a991 8530{
da0436e9
JS
8531 LPFC_MBOXQ_t *pmb;
8532 struct lpfc_mbx_read_config *rd_config;
912e3acd
JS
8533 union lpfc_sli4_cfg_shdr *shdr;
8534 uint32_t shdr_status, shdr_add_status;
8535 struct lpfc_mbx_get_func_cfg *get_func_cfg;
8536 struct lpfc_rsrc_desc_fcfcoe *desc;
8aa134a8 8537 char *pdesc_0;
c691816e 8538 uint16_t forced_link_speed;
6a828b0f 8539 uint32_t if_type, qmin;
8aa134a8 8540 int length, i, rc = 0, rc2;
3772a991 8541
da0436e9
JS
8542 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
8543 if (!pmb) {
372c187b 8544 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
8545 "2011 Unable to allocate memory for issuing "
8546 "SLI_CONFIG_SPECIAL mailbox command\n");
8547 return -ENOMEM;
3772a991
JS
8548 }
8549
da0436e9 8550 lpfc_read_config(phba, pmb);
3772a991 8551
da0436e9
JS
8552 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
8553 if (rc != MBX_SUCCESS) {
372c187b
DK
8554 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
8555 "2012 Mailbox failed , mbxCmd x%x "
8556 "READ_CONFIG, mbxStatus x%x\n",
8557 bf_get(lpfc_mqe_command, &pmb->u.mqe),
8558 bf_get(lpfc_mqe_status, &pmb->u.mqe));
da0436e9
JS
8559 rc = -EIO;
8560 } else {
8561 rd_config = &pmb->u.mqe.un.rd_config;
ff78d8f9
JS
8562 if (bf_get(lpfc_mbx_rd_conf_lnk_ldv, rd_config)) {
8563 phba->sli4_hba.lnk_info.lnk_dv = LPFC_LNK_DAT_VAL;
8564 phba->sli4_hba.lnk_info.lnk_tp =
8565 bf_get(lpfc_mbx_rd_conf_lnk_type, rd_config);
8566 phba->sli4_hba.lnk_info.lnk_no =
8567 bf_get(lpfc_mbx_rd_conf_lnk_numb, rd_config);
8568 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8569 "3081 lnk_type:%d, lnk_numb:%d\n",
8570 phba->sli4_hba.lnk_info.lnk_tp,
8571 phba->sli4_hba.lnk_info.lnk_no);
8572 } else
8573 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
8574 "3082 Mailbox (x%x) returned ldv:x0\n",
8575 bf_get(lpfc_mqe_command, &pmb->u.mqe));
44fd7fe3
JS
8576 if (bf_get(lpfc_mbx_rd_conf_bbscn_def, rd_config)) {
8577 phba->bbcredit_support = 1;
8578 phba->sli4_hba.bbscn_params.word0 = rd_config->word8;
8579 }
8580
1dc5ec24
JS
8581 phba->sli4_hba.conf_trunk =
8582 bf_get(lpfc_mbx_rd_conf_trunk, rd_config);
6d368e53
JS
8583 phba->sli4_hba.extents_in_use =
8584 bf_get(lpfc_mbx_rd_conf_extnts_inuse, rd_config);
da0436e9
JS
8585 phba->sli4_hba.max_cfg_param.max_xri =
8586 bf_get(lpfc_mbx_rd_conf_xri_count, rd_config);
31f06d2e
JS
8587 /* Reduce resource usage in kdump environment */
8588 if (is_kdump_kernel() &&
8589 phba->sli4_hba.max_cfg_param.max_xri > 512)
8590 phba->sli4_hba.max_cfg_param.max_xri = 512;
da0436e9
JS
8591 phba->sli4_hba.max_cfg_param.xri_base =
8592 bf_get(lpfc_mbx_rd_conf_xri_base, rd_config);
8593 phba->sli4_hba.max_cfg_param.max_vpi =
8594 bf_get(lpfc_mbx_rd_conf_vpi_count, rd_config);
8b47ae69
JS
8595 /* Limit the max we support */
8596 if (phba->sli4_hba.max_cfg_param.max_vpi > LPFC_MAX_VPORTS)
8597 phba->sli4_hba.max_cfg_param.max_vpi = LPFC_MAX_VPORTS;
da0436e9
JS
8598 phba->sli4_hba.max_cfg_param.vpi_base =
8599 bf_get(lpfc_mbx_rd_conf_vpi_base, rd_config);
8600 phba->sli4_hba.max_cfg_param.max_rpi =
8601 bf_get(lpfc_mbx_rd_conf_rpi_count, rd_config);
8602 phba->sli4_hba.max_cfg_param.rpi_base =
8603 bf_get(lpfc_mbx_rd_conf_rpi_base, rd_config);
8604 phba->sli4_hba.max_cfg_param.max_vfi =
8605 bf_get(lpfc_mbx_rd_conf_vfi_count, rd_config);
8606 phba->sli4_hba.max_cfg_param.vfi_base =
8607 bf_get(lpfc_mbx_rd_conf_vfi_base, rd_config);
8608 phba->sli4_hba.max_cfg_param.max_fcfi =
8609 bf_get(lpfc_mbx_rd_conf_fcfi_count, rd_config);
da0436e9
JS
8610 phba->sli4_hba.max_cfg_param.max_eq =
8611 bf_get(lpfc_mbx_rd_conf_eq_count, rd_config);
8612 phba->sli4_hba.max_cfg_param.max_rq =
8613 bf_get(lpfc_mbx_rd_conf_rq_count, rd_config);
8614 phba->sli4_hba.max_cfg_param.max_wq =
8615 bf_get(lpfc_mbx_rd_conf_wq_count, rd_config);
8616 phba->sli4_hba.max_cfg_param.max_cq =
8617 bf_get(lpfc_mbx_rd_conf_cq_count, rd_config);
8618 phba->lmt = bf_get(lpfc_mbx_rd_conf_lmt, rd_config);
8619 phba->sli4_hba.next_xri = phba->sli4_hba.max_cfg_param.xri_base;
8620 phba->vpi_base = phba->sli4_hba.max_cfg_param.vpi_base;
8621 phba->vfi_base = phba->sli4_hba.max_cfg_param.vfi_base;
5ffc266e
JS
8622 phba->max_vpi = (phba->sli4_hba.max_cfg_param.max_vpi > 0) ?
8623 (phba->sli4_hba.max_cfg_param.max_vpi - 1) : 0;
da0436e9 8624 phba->max_vports = phba->max_vpi;
83c6cb1a 8625 lpfc_map_topology(phba, rd_config);
da0436e9 8626 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
6d368e53
JS
8627 "2003 cfg params Extents? %d "
8628 "XRI(B:%d M:%d), "
da0436e9
JS
8629 "VPI(B:%d M:%d) "
8630 "VFI(B:%d M:%d) "
8631 "RPI(B:%d M:%d) "
a1e4d3d8 8632 "FCFI:%d EQ:%d CQ:%d WQ:%d RQ:%d lmt:x%x\n",
6d368e53 8633 phba->sli4_hba.extents_in_use,
da0436e9
JS
8634 phba->sli4_hba.max_cfg_param.xri_base,
8635 phba->sli4_hba.max_cfg_param.max_xri,
8636 phba->sli4_hba.max_cfg_param.vpi_base,
8637 phba->sli4_hba.max_cfg_param.max_vpi,
8638 phba->sli4_hba.max_cfg_param.vfi_base,
8639 phba->sli4_hba.max_cfg_param.max_vfi,
8640 phba->sli4_hba.max_cfg_param.rpi_base,
8641 phba->sli4_hba.max_cfg_param.max_rpi,
2ea259ee
JS
8642 phba->sli4_hba.max_cfg_param.max_fcfi,
8643 phba->sli4_hba.max_cfg_param.max_eq,
8644 phba->sli4_hba.max_cfg_param.max_cq,
8645 phba->sli4_hba.max_cfg_param.max_wq,
a1e4d3d8
DK
8646 phba->sli4_hba.max_cfg_param.max_rq,
8647 phba->lmt);
2ea259ee 8648
d38f33b3 8649 /*
6a828b0f
JS
8650 * Calculate queue resources based on how
8651 * many WQ/CQ/EQs are available.
d38f33b3 8652 */
6a828b0f
JS
8653 qmin = phba->sli4_hba.max_cfg_param.max_wq;
8654 if (phba->sli4_hba.max_cfg_param.max_cq < qmin)
8655 qmin = phba->sli4_hba.max_cfg_param.max_cq;
8656 if (phba->sli4_hba.max_cfg_param.max_eq < qmin)
8657 qmin = phba->sli4_hba.max_cfg_param.max_eq;
8658 /*
8659 * Whats left after this can go toward NVME / FCP.
8660 * The minus 4 accounts for ELS, NVME LS, MBOX
8661 * plus one extra. When configured for
8662 * NVMET, FCP io channel WQs are not created.
8663 */
8664 qmin -= 4;
d38f33b3 8665
6a828b0f
JS
8666 /* Check to see if there is enough for NVME */
8667 if ((phba->cfg_irq_chann > qmin) ||
8668 (phba->cfg_hdw_queue > qmin)) {
372c187b 8669 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
9e3e365a
DK
8670 "2005 Reducing Queues - "
8671 "FW resource limitation: "
6a828b0f
JS
8672 "WQ %d CQ %d EQ %d: min %d: "
8673 "IRQ %d HDWQ %d\n",
d38f33b3
JS
8674 phba->sli4_hba.max_cfg_param.max_wq,
8675 phba->sli4_hba.max_cfg_param.max_cq,
6a828b0f
JS
8676 phba->sli4_hba.max_cfg_param.max_eq,
8677 qmin, phba->cfg_irq_chann,
cdb42bec 8678 phba->cfg_hdw_queue);
d38f33b3 8679
6a828b0f
JS
8680 if (phba->cfg_irq_chann > qmin)
8681 phba->cfg_irq_chann = qmin;
8682 if (phba->cfg_hdw_queue > qmin)
8683 phba->cfg_hdw_queue = qmin;
d38f33b3 8684 }
3772a991 8685 }
912e3acd
JS
8686
8687 if (rc)
8688 goto read_cfg_out;
da0436e9 8689
c691816e
JS
8690 /* Update link speed if forced link speed is supported */
8691 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
27d6ac0a 8692 if (if_type >= LPFC_SLI_INTF_IF_TYPE_2) {
c691816e
JS
8693 forced_link_speed =
8694 bf_get(lpfc_mbx_rd_conf_link_speed, rd_config);
8695 if (forced_link_speed) {
8696 phba->hba_flag |= HBA_FORCED_LINK_SPEED;
8697
8698 switch (forced_link_speed) {
8699 case LINK_SPEED_1G:
8700 phba->cfg_link_speed =
8701 LPFC_USER_LINK_SPEED_1G;
8702 break;
8703 case LINK_SPEED_2G:
8704 phba->cfg_link_speed =
8705 LPFC_USER_LINK_SPEED_2G;
8706 break;
8707 case LINK_SPEED_4G:
8708 phba->cfg_link_speed =
8709 LPFC_USER_LINK_SPEED_4G;
8710 break;
8711 case LINK_SPEED_8G:
8712 phba->cfg_link_speed =
8713 LPFC_USER_LINK_SPEED_8G;
8714 break;
8715 case LINK_SPEED_10G:
8716 phba->cfg_link_speed =
8717 LPFC_USER_LINK_SPEED_10G;
8718 break;
8719 case LINK_SPEED_16G:
8720 phba->cfg_link_speed =
8721 LPFC_USER_LINK_SPEED_16G;
8722 break;
8723 case LINK_SPEED_32G:
8724 phba->cfg_link_speed =
8725 LPFC_USER_LINK_SPEED_32G;
8726 break;
fbd8a6ba
JS
8727 case LINK_SPEED_64G:
8728 phba->cfg_link_speed =
8729 LPFC_USER_LINK_SPEED_64G;
8730 break;
c691816e
JS
8731 case 0xffff:
8732 phba->cfg_link_speed =
8733 LPFC_USER_LINK_SPEED_AUTO;
8734 break;
8735 default:
372c187b
DK
8736 lpfc_printf_log(phba, KERN_ERR,
8737 LOG_TRACE_EVENT,
c691816e
JS
8738 "0047 Unrecognized link "
8739 "speed : %d\n",
8740 forced_link_speed);
8741 phba->cfg_link_speed =
8742 LPFC_USER_LINK_SPEED_AUTO;
8743 }
8744 }
8745 }
8746
da0436e9 8747 /* Reset the DFT_HBA_Q_DEPTH to the max xri */
572709e2
JS
8748 length = phba->sli4_hba.max_cfg_param.max_xri -
8749 lpfc_sli4_get_els_iocb_cnt(phba);
8750 if (phba->cfg_hba_queue_depth > length) {
8751 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
8752 "3361 HBA queue depth changed from %d to %d\n",
8753 phba->cfg_hba_queue_depth, length);
8754 phba->cfg_hba_queue_depth = length;
8755 }
912e3acd 8756
27d6ac0a 8757 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) <
912e3acd
JS
8758 LPFC_SLI_INTF_IF_TYPE_2)
8759 goto read_cfg_out;
8760
8761 /* get the pf# and vf# for SLI4 if_type 2 port */
8762 length = (sizeof(struct lpfc_mbx_get_func_cfg) -
8763 sizeof(struct lpfc_sli4_cfg_mhdr));
8764 lpfc_sli4_config(phba, pmb, LPFC_MBOX_SUBSYSTEM_COMMON,
8765 LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG,
8766 length, LPFC_SLI4_MBX_EMBED);
8767
8aa134a8 8768 rc2 = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
912e3acd
JS
8769 shdr = (union lpfc_sli4_cfg_shdr *)
8770 &pmb->u.mqe.un.sli4_config.header.cfg_shdr;
8771 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
8772 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
8aa134a8 8773 if (rc2 || shdr_status || shdr_add_status) {
372c187b 8774 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
912e3acd
JS
8775 "3026 Mailbox failed , mbxCmd x%x "
8776 "GET_FUNCTION_CONFIG, mbxStatus x%x\n",
8777 bf_get(lpfc_mqe_command, &pmb->u.mqe),
8778 bf_get(lpfc_mqe_status, &pmb->u.mqe));
912e3acd
JS
8779 goto read_cfg_out;
8780 }
8781
8782 /* search for fc_fcoe resrouce descriptor */
8783 get_func_cfg = &pmb->u.mqe.un.get_func_cfg;
912e3acd 8784
8aa134a8
JS
8785 pdesc_0 = (char *)&get_func_cfg->func_cfg.desc[0];
8786 desc = (struct lpfc_rsrc_desc_fcfcoe *)pdesc_0;
8787 length = bf_get(lpfc_rsrc_desc_fcfcoe_length, desc);
8788 if (length == LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD)
8789 length = LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH;
8790 else if (length != LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH)
8791 goto read_cfg_out;
8792
912e3acd 8793 for (i = 0; i < LPFC_RSRC_DESC_MAX_NUM; i++) {
8aa134a8 8794 desc = (struct lpfc_rsrc_desc_fcfcoe *)(pdesc_0 + length * i);
912e3acd 8795 if (LPFC_RSRC_DESC_TYPE_FCFCOE ==
8aa134a8 8796 bf_get(lpfc_rsrc_desc_fcfcoe_type, desc)) {
912e3acd
JS
8797 phba->sli4_hba.iov.pf_number =
8798 bf_get(lpfc_rsrc_desc_fcfcoe_pfnum, desc);
8799 phba->sli4_hba.iov.vf_number =
8800 bf_get(lpfc_rsrc_desc_fcfcoe_vfnum, desc);
8801 break;
8802 }
8803 }
8804
8805 if (i < LPFC_RSRC_DESC_MAX_NUM)
8806 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8807 "3027 GET_FUNCTION_CONFIG: pf_number:%d, "
8808 "vf_number:%d\n", phba->sli4_hba.iov.pf_number,
8809 phba->sli4_hba.iov.vf_number);
8aa134a8 8810 else
372c187b 8811 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
912e3acd 8812 "3028 GET_FUNCTION_CONFIG: failed to find "
c4dba187 8813 "Resource Descriptor:x%x\n",
912e3acd 8814 LPFC_RSRC_DESC_TYPE_FCFCOE);
912e3acd
JS
8815
8816read_cfg_out:
8817 mempool_free(pmb, phba->mbox_mem_pool);
da0436e9 8818 return rc;
3772a991
JS
8819}
8820
8821/**
2fcee4bf 8822 * lpfc_setup_endian_order - Write endian order to an SLI4 if_type 0 port.
3772a991
JS
8823 * @phba: pointer to lpfc hba data structure.
8824 *
2fcee4bf
JS
8825 * This routine is invoked to setup the port-side endian order when
8826 * the port if_type is 0. This routine has no function for other
8827 * if_types.
da0436e9
JS
8828 *
8829 * Return codes
af901ca1 8830 * 0 - successful
25985edc 8831 * -ENOMEM - No available memory
d439d286 8832 * -EIO - The mailbox failed to complete successfully.
3772a991 8833 **/
da0436e9
JS
8834static int
8835lpfc_setup_endian_order(struct lpfc_hba *phba)
3772a991 8836{
da0436e9 8837 LPFC_MBOXQ_t *mboxq;
2fcee4bf 8838 uint32_t if_type, rc = 0;
da0436e9
JS
8839 uint32_t endian_mb_data[2] = {HOST_ENDIAN_LOW_WORD0,
8840 HOST_ENDIAN_HIGH_WORD1};
3772a991 8841
2fcee4bf
JS
8842 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
8843 switch (if_type) {
8844 case LPFC_SLI_INTF_IF_TYPE_0:
8845 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
8846 GFP_KERNEL);
8847 if (!mboxq) {
372c187b 8848 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
8849 "0492 Unable to allocate memory for "
8850 "issuing SLI_CONFIG_SPECIAL mailbox "
8851 "command\n");
8852 return -ENOMEM;
8853 }
3772a991 8854
2fcee4bf
JS
8855 /*
8856 * The SLI4_CONFIG_SPECIAL mailbox command requires the first
8857 * two words to contain special data values and no other data.
8858 */
8859 memset(mboxq, 0, sizeof(LPFC_MBOXQ_t));
8860 memcpy(&mboxq->u.mqe, &endian_mb_data, sizeof(endian_mb_data));
8861 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
8862 if (rc != MBX_SUCCESS) {
372c187b 8863 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
8864 "0493 SLI_CONFIG_SPECIAL mailbox "
8865 "failed with status x%x\n",
8866 rc);
8867 rc = -EIO;
8868 }
8869 mempool_free(mboxq, phba->mbox_mem_pool);
8870 break;
27d6ac0a 8871 case LPFC_SLI_INTF_IF_TYPE_6:
2fcee4bf
JS
8872 case LPFC_SLI_INTF_IF_TYPE_2:
8873 case LPFC_SLI_INTF_IF_TYPE_1:
8874 default:
8875 break;
da0436e9 8876 }
da0436e9 8877 return rc;
3772a991
JS
8878}
8879
8880/**
895427bd 8881 * lpfc_sli4_queue_verify - Verify and update EQ counts
3772a991
JS
8882 * @phba: pointer to lpfc hba data structure.
8883 *
895427bd
JS
8884 * This routine is invoked to check the user settable queue counts for EQs.
8885 * After this routine is called the counts will be set to valid values that
5350d872
JS
8886 * adhere to the constraints of the system's interrupt vectors and the port's
8887 * queue resources.
da0436e9
JS
8888 *
8889 * Return codes
af901ca1 8890 * 0 - successful
25985edc 8891 * -ENOMEM - No available memory
3772a991 8892 **/
da0436e9 8893static int
5350d872 8894lpfc_sli4_queue_verify(struct lpfc_hba *phba)
3772a991 8895{
da0436e9 8896 /*
67d12733 8897 * Sanity check for configured queue parameters against the run-time
da0436e9
JS
8898 * device parameters
8899 */
3772a991 8900
bcb24f65 8901 if (phba->nvmet_support) {
97a9ed3b
JS
8902 if (phba->cfg_hdw_queue < phba->cfg_nvmet_mrq)
8903 phba->cfg_nvmet_mrq = phba->cfg_hdw_queue;
982ab128
JS
8904 if (phba->cfg_nvmet_mrq > LPFC_NVMET_MRQ_MAX)
8905 phba->cfg_nvmet_mrq = LPFC_NVMET_MRQ_MAX;
bcb24f65 8906 }
895427bd
JS
8907
8908 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6a828b0f
JS
8909 "2574 IO channels: hdwQ %d IRQ %d MRQ: %d\n",
8910 phba->cfg_hdw_queue, phba->cfg_irq_chann,
8911 phba->cfg_nvmet_mrq);
3772a991 8912
da0436e9
JS
8913 /* Get EQ depth from module parameter, fake the default for now */
8914 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
8915 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
3772a991 8916
5350d872
JS
8917 /* Get CQ depth from module parameter, fake the default for now */
8918 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
8919 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
895427bd
JS
8920 return 0;
8921}
8922
8923static int
c00f62e6 8924lpfc_alloc_io_wq_cq(struct lpfc_hba *phba, int idx)
895427bd
JS
8925{
8926 struct lpfc_queue *qdesc;
c00f62e6 8927 u32 wqesize;
c1a21ebc 8928 int cpu;
895427bd 8929
c00f62e6
JS
8930 cpu = lpfc_find_cpu_handle(phba, idx, LPFC_FIND_BY_HDWQ);
8931 /* Create Fast Path IO CQs */
c176ffa0 8932 if (phba->enab_exp_wqcq_pages)
a51e41b6
JS
8933 /* Increase the CQ size when WQEs contain an embedded cdb */
8934 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
8935 phba->sli4_hba.cq_esize,
c1a21ebc 8936 LPFC_CQE_EXP_COUNT, cpu);
a51e41b6
JS
8937
8938 else
8939 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8940 phba->sli4_hba.cq_esize,
c1a21ebc 8941 phba->sli4_hba.cq_ecount, cpu);
895427bd 8942 if (!qdesc) {
372c187b
DK
8943 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
8944 "0499 Failed allocate fast-path IO CQ (%d)\n",
8945 idx);
895427bd
JS
8946 return 1;
8947 }
7365f6fd 8948 qdesc->qe_valid = 1;
c00f62e6 8949 qdesc->hdwq = idx;
c1a21ebc 8950 qdesc->chann = cpu;
c00f62e6 8951 phba->sli4_hba.hdwq[idx].io_cq = qdesc;
895427bd 8952
c00f62e6 8953 /* Create Fast Path IO WQs */
c176ffa0 8954 if (phba->enab_exp_wqcq_pages) {
a51e41b6 8955 /* Increase the WQ size when WQEs contain an embedded cdb */
c176ffa0
JS
8956 wqesize = (phba->fcp_embed_io) ?
8957 LPFC_WQE128_SIZE : phba->sli4_hba.wq_esize;
a51e41b6 8958 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
c176ffa0 8959 wqesize,
c1a21ebc 8960 LPFC_WQE_EXP_COUNT, cpu);
c176ffa0 8961 } else
a51e41b6
JS
8962 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8963 phba->sli4_hba.wq_esize,
c1a21ebc 8964 phba->sli4_hba.wq_ecount, cpu);
c176ffa0 8965
895427bd 8966 if (!qdesc) {
372c187b 8967 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
c00f62e6
JS
8968 "0503 Failed allocate fast-path IO WQ (%d)\n",
8969 idx);
895427bd
JS
8970 return 1;
8971 }
c00f62e6
JS
8972 qdesc->hdwq = idx;
8973 qdesc->chann = cpu;
8974 phba->sli4_hba.hdwq[idx].io_wq = qdesc;
895427bd 8975 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
5350d872 8976 return 0;
5350d872
JS
8977}
8978
8979/**
8980 * lpfc_sli4_queue_create - Create all the SLI4 queues
8981 * @phba: pointer to lpfc hba data structure.
8982 *
8983 * This routine is invoked to allocate all the SLI4 queues for the FCoE HBA
8984 * operation. For each SLI4 queue type, the parameters such as queue entry
8985 * count (queue depth) shall be taken from the module parameter. For now,
8986 * we just use some constant number as place holder.
8987 *
8988 * Return codes
4907cb7b 8989 * 0 - successful
5350d872
JS
8990 * -ENOMEM - No availble memory
8991 * -EIO - The mailbox failed to complete successfully.
8992 **/
8993int
8994lpfc_sli4_queue_create(struct lpfc_hba *phba)
8995{
8996 struct lpfc_queue *qdesc;
657add4e 8997 int idx, cpu, eqcpu;
5e5b511d 8998 struct lpfc_sli4_hdw_queue *qp;
657add4e
JS
8999 struct lpfc_vector_map_info *cpup;
9000 struct lpfc_vector_map_info *eqcpup;
32517fc0 9001 struct lpfc_eq_intr_info *eqi;
5350d872
JS
9002
9003 /*
67d12733 9004 * Create HBA Record arrays.
895427bd 9005 * Both NVME and FCP will share that same vectors / EQs
5350d872 9006 */
67d12733
JS
9007 phba->sli4_hba.mq_esize = LPFC_MQE_SIZE;
9008 phba->sli4_hba.mq_ecount = LPFC_MQE_DEF_COUNT;
9009 phba->sli4_hba.wq_esize = LPFC_WQE_SIZE;
9010 phba->sli4_hba.wq_ecount = LPFC_WQE_DEF_COUNT;
9011 phba->sli4_hba.rq_esize = LPFC_RQE_SIZE;
9012 phba->sli4_hba.rq_ecount = LPFC_RQE_DEF_COUNT;
895427bd
JS
9013 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
9014 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
9015 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
9016 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
67d12733 9017
cdb42bec 9018 if (!phba->sli4_hba.hdwq) {
5e5b511d
JS
9019 phba->sli4_hba.hdwq = kcalloc(
9020 phba->cfg_hdw_queue, sizeof(struct lpfc_sli4_hdw_queue),
9021 GFP_KERNEL);
9022 if (!phba->sli4_hba.hdwq) {
372c187b 9023 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5e5b511d
JS
9024 "6427 Failed allocate memory for "
9025 "fast-path Hardware Queue array\n");
895427bd
JS
9026 goto out_error;
9027 }
5e5b511d
JS
9028 /* Prepare hardware queues to take IO buffers */
9029 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9030 qp = &phba->sli4_hba.hdwq[idx];
9031 spin_lock_init(&qp->io_buf_list_get_lock);
9032 spin_lock_init(&qp->io_buf_list_put_lock);
9033 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_get);
9034 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_put);
9035 qp->get_io_bufs = 0;
9036 qp->put_io_bufs = 0;
9037 qp->total_io_bufs = 0;
c00f62e6
JS
9038 spin_lock_init(&qp->abts_io_buf_list_lock);
9039 INIT_LIST_HEAD(&qp->lpfc_abts_io_buf_list);
5e5b511d 9040 qp->abts_scsi_io_bufs = 0;
5e5b511d 9041 qp->abts_nvme_io_bufs = 0;
d79c9e9d
JS
9042 INIT_LIST_HEAD(&qp->sgl_list);
9043 INIT_LIST_HEAD(&qp->cmd_rsp_buf_list);
9044 spin_lock_init(&qp->hdwq_lock);
895427bd 9045 }
67d12733
JS
9046 }
9047
cdb42bec 9048 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
2d7dbc4c
JS
9049 if (phba->nvmet_support) {
9050 phba->sli4_hba.nvmet_cqset = kcalloc(
9051 phba->cfg_nvmet_mrq,
9052 sizeof(struct lpfc_queue *),
9053 GFP_KERNEL);
9054 if (!phba->sli4_hba.nvmet_cqset) {
372c187b 9055 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9056 "3121 Fail allocate memory for "
9057 "fast-path CQ set array\n");
9058 goto out_error;
9059 }
9060 phba->sli4_hba.nvmet_mrq_hdr = kcalloc(
9061 phba->cfg_nvmet_mrq,
9062 sizeof(struct lpfc_queue *),
9063 GFP_KERNEL);
9064 if (!phba->sli4_hba.nvmet_mrq_hdr) {
372c187b 9065 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9066 "3122 Fail allocate memory for "
9067 "fast-path RQ set hdr array\n");
9068 goto out_error;
9069 }
9070 phba->sli4_hba.nvmet_mrq_data = kcalloc(
9071 phba->cfg_nvmet_mrq,
9072 sizeof(struct lpfc_queue *),
9073 GFP_KERNEL);
9074 if (!phba->sli4_hba.nvmet_mrq_data) {
372c187b 9075 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9076 "3124 Fail allocate memory for "
9077 "fast-path RQ set data array\n");
9078 goto out_error;
9079 }
9080 }
da0436e9 9081 }
67d12733 9082
895427bd 9083 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
67d12733 9084
895427bd 9085 /* Create HBA Event Queues (EQs) */
657add4e
JS
9086 for_each_present_cpu(cpu) {
9087 /* We only want to create 1 EQ per vector, even though
9088 * multiple CPUs might be using that vector. so only
9089 * selects the CPUs that are LPFC_CPU_FIRST_IRQ.
6a828b0f 9090 */
657add4e
JS
9091 cpup = &phba->sli4_hba.cpu_map[cpu];
9092 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
6a828b0f 9093 continue;
657add4e
JS
9094
9095 /* Get a ptr to the Hardware Queue associated with this CPU */
9096 qp = &phba->sli4_hba.hdwq[cpup->hdwq];
9097
9098 /* Allocate an EQ */
81b96eda
JS
9099 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9100 phba->sli4_hba.eq_esize,
c1a21ebc 9101 phba->sli4_hba.eq_ecount, cpu);
da0436e9 9102 if (!qdesc) {
372c187b 9103 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
657add4e
JS
9104 "0497 Failed allocate EQ (%d)\n",
9105 cpup->hdwq);
67d12733 9106 goto out_error;
da0436e9 9107 }
7365f6fd 9108 qdesc->qe_valid = 1;
657add4e 9109 qdesc->hdwq = cpup->hdwq;
3ad348d9 9110 qdesc->chann = cpu; /* First CPU this EQ is affinitized to */
32517fc0 9111 qdesc->last_cpu = qdesc->chann;
657add4e
JS
9112
9113 /* Save the allocated EQ in the Hardware Queue */
9114 qp->hba_eq = qdesc;
9115
32517fc0
JS
9116 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, qdesc->last_cpu);
9117 list_add(&qdesc->cpu_list, &eqi->list);
895427bd 9118 }
67d12733 9119
657add4e
JS
9120 /* Now we need to populate the other Hardware Queues, that share
9121 * an IRQ vector, with the associated EQ ptr.
9122 */
9123 for_each_present_cpu(cpu) {
9124 cpup = &phba->sli4_hba.cpu_map[cpu];
9125
9126 /* Check for EQ already allocated in previous loop */
9127 if (cpup->flag & LPFC_CPU_FIRST_IRQ)
9128 continue;
9129
9130 /* Check for multiple CPUs per hdwq */
9131 qp = &phba->sli4_hba.hdwq[cpup->hdwq];
9132 if (qp->hba_eq)
9133 continue;
9134
9135 /* We need to share an EQ for this hdwq */
9136 eqcpu = lpfc_find_cpu_handle(phba, cpup->eq, LPFC_FIND_BY_EQ);
9137 eqcpup = &phba->sli4_hba.cpu_map[eqcpu];
9138 qp->hba_eq = phba->sli4_hba.hdwq[eqcpup->hdwq].hba_eq;
9139 }
67d12733 9140
c00f62e6 9141 /* Allocate IO Path SLI4 CQ/WQs */
6a828b0f 9142 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
c00f62e6 9143 if (lpfc_alloc_io_wq_cq(phba, idx))
67d12733 9144 goto out_error;
6a828b0f 9145 }
da0436e9 9146
c00f62e6
JS
9147 if (phba->nvmet_support) {
9148 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
9149 cpu = lpfc_find_cpu_handle(phba, idx,
9150 LPFC_FIND_BY_HDWQ);
9151 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda
JS
9152 LPFC_DEFAULT_PAGE_SIZE,
9153 phba->sli4_hba.cq_esize,
c1a21ebc
JS
9154 phba->sli4_hba.cq_ecount,
9155 cpu);
c00f62e6 9156 if (!qdesc) {
372c187b 9157 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
cdb42bec
JS
9158 "3142 Failed allocate NVME "
9159 "CQ Set (%d)\n", idx);
c00f62e6 9160 goto out_error;
2d7dbc4c 9161 }
c00f62e6
JS
9162 qdesc->qe_valid = 1;
9163 qdesc->hdwq = idx;
9164 qdesc->chann = cpu;
9165 phba->sli4_hba.nvmet_cqset[idx] = qdesc;
2d7dbc4c
JS
9166 }
9167 }
9168
da0436e9 9169 /*
67d12733 9170 * Create Slow Path Completion Queues (CQs)
da0436e9
JS
9171 */
9172
c1a21ebc 9173 cpu = lpfc_find_cpu_handle(phba, 0, LPFC_FIND_BY_EQ);
da0436e9 9174 /* Create slow-path Mailbox Command Complete Queue */
81b96eda
JS
9175 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9176 phba->sli4_hba.cq_esize,
c1a21ebc 9177 phba->sli4_hba.cq_ecount, cpu);
da0436e9 9178 if (!qdesc) {
372c187b 9179 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9180 "0500 Failed allocate slow-path mailbox CQ\n");
67d12733 9181 goto out_error;
da0436e9 9182 }
7365f6fd 9183 qdesc->qe_valid = 1;
da0436e9
JS
9184 phba->sli4_hba.mbx_cq = qdesc;
9185
9186 /* Create slow-path ELS Complete Queue */
81b96eda
JS
9187 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9188 phba->sli4_hba.cq_esize,
c1a21ebc 9189 phba->sli4_hba.cq_ecount, cpu);
da0436e9 9190 if (!qdesc) {
372c187b 9191 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9192 "0501 Failed allocate slow-path ELS CQ\n");
67d12733 9193 goto out_error;
da0436e9 9194 }
7365f6fd 9195 qdesc->qe_valid = 1;
c00f62e6 9196 qdesc->chann = cpu;
da0436e9
JS
9197 phba->sli4_hba.els_cq = qdesc;
9198
da0436e9 9199
5350d872 9200 /*
67d12733 9201 * Create Slow Path Work Queues (WQs)
5350d872 9202 */
da0436e9
JS
9203
9204 /* Create Mailbox Command Queue */
da0436e9 9205
81b96eda
JS
9206 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9207 phba->sli4_hba.mq_esize,
c1a21ebc 9208 phba->sli4_hba.mq_ecount, cpu);
da0436e9 9209 if (!qdesc) {
372c187b 9210 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9211 "0505 Failed allocate slow-path MQ\n");
67d12733 9212 goto out_error;
da0436e9 9213 }
c00f62e6 9214 qdesc->chann = cpu;
da0436e9
JS
9215 phba->sli4_hba.mbx_wq = qdesc;
9216
9217 /*
67d12733 9218 * Create ELS Work Queues
da0436e9 9219 */
da0436e9
JS
9220
9221 /* Create slow-path ELS Work Queue */
81b96eda
JS
9222 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9223 phba->sli4_hba.wq_esize,
c1a21ebc 9224 phba->sli4_hba.wq_ecount, cpu);
da0436e9 9225 if (!qdesc) {
372c187b 9226 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9227 "0504 Failed allocate slow-path ELS WQ\n");
67d12733 9228 goto out_error;
da0436e9 9229 }
c00f62e6 9230 qdesc->chann = cpu;
da0436e9 9231 phba->sli4_hba.els_wq = qdesc;
895427bd
JS
9232 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
9233
9234 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
9235 /* Create NVME LS Complete Queue */
81b96eda
JS
9236 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9237 phba->sli4_hba.cq_esize,
c1a21ebc 9238 phba->sli4_hba.cq_ecount, cpu);
895427bd 9239 if (!qdesc) {
372c187b 9240 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9241 "6079 Failed allocate NVME LS CQ\n");
9242 goto out_error;
9243 }
c00f62e6 9244 qdesc->chann = cpu;
7365f6fd 9245 qdesc->qe_valid = 1;
895427bd
JS
9246 phba->sli4_hba.nvmels_cq = qdesc;
9247
9248 /* Create NVME LS Work Queue */
81b96eda
JS
9249 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9250 phba->sli4_hba.wq_esize,
c1a21ebc 9251 phba->sli4_hba.wq_ecount, cpu);
895427bd 9252 if (!qdesc) {
372c187b 9253 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9254 "6080 Failed allocate NVME LS WQ\n");
9255 goto out_error;
9256 }
c00f62e6 9257 qdesc->chann = cpu;
895427bd
JS
9258 phba->sli4_hba.nvmels_wq = qdesc;
9259 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
9260 }
da0436e9 9261
da0436e9
JS
9262 /*
9263 * Create Receive Queue (RQ)
9264 */
da0436e9
JS
9265
9266 /* Create Receive Queue for header */
81b96eda
JS
9267 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9268 phba->sli4_hba.rq_esize,
c1a21ebc 9269 phba->sli4_hba.rq_ecount, cpu);
da0436e9 9270 if (!qdesc) {
372c187b 9271 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9272 "0506 Failed allocate receive HRQ\n");
67d12733 9273 goto out_error;
da0436e9
JS
9274 }
9275 phba->sli4_hba.hdr_rq = qdesc;
9276
9277 /* Create Receive Queue for data */
81b96eda
JS
9278 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9279 phba->sli4_hba.rq_esize,
c1a21ebc 9280 phba->sli4_hba.rq_ecount, cpu);
da0436e9 9281 if (!qdesc) {
372c187b 9282 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9283 "0507 Failed allocate receive DRQ\n");
67d12733 9284 goto out_error;
da0436e9
JS
9285 }
9286 phba->sli4_hba.dat_rq = qdesc;
9287
cdb42bec
JS
9288 if ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) &&
9289 phba->nvmet_support) {
2d7dbc4c 9290 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
c1a21ebc
JS
9291 cpu = lpfc_find_cpu_handle(phba, idx,
9292 LPFC_FIND_BY_HDWQ);
2d7dbc4c
JS
9293 /* Create NVMET Receive Queue for header */
9294 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda 9295 LPFC_DEFAULT_PAGE_SIZE,
2d7dbc4c 9296 phba->sli4_hba.rq_esize,
c1a21ebc
JS
9297 LPFC_NVMET_RQE_DEF_COUNT,
9298 cpu);
2d7dbc4c 9299 if (!qdesc) {
372c187b 9300 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9301 "3146 Failed allocate "
9302 "receive HRQ\n");
9303 goto out_error;
9304 }
5e5b511d 9305 qdesc->hdwq = idx;
2d7dbc4c
JS
9306 phba->sli4_hba.nvmet_mrq_hdr[idx] = qdesc;
9307
9308 /* Only needed for header of RQ pair */
c1a21ebc
JS
9309 qdesc->rqbp = kzalloc_node(sizeof(*qdesc->rqbp),
9310 GFP_KERNEL,
9311 cpu_to_node(cpu));
2d7dbc4c 9312 if (qdesc->rqbp == NULL) {
372c187b 9313 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9314 "6131 Failed allocate "
9315 "Header RQBP\n");
9316 goto out_error;
9317 }
9318
4b40d02b
DK
9319 /* Put list in known state in case driver load fails. */
9320 INIT_LIST_HEAD(&qdesc->rqbp->rqb_buffer_list);
9321
2d7dbc4c
JS
9322 /* Create NVMET Receive Queue for data */
9323 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda 9324 LPFC_DEFAULT_PAGE_SIZE,
2d7dbc4c 9325 phba->sli4_hba.rq_esize,
c1a21ebc
JS
9326 LPFC_NVMET_RQE_DEF_COUNT,
9327 cpu);
2d7dbc4c 9328 if (!qdesc) {
372c187b 9329 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9330 "3156 Failed allocate "
9331 "receive DRQ\n");
9332 goto out_error;
9333 }
5e5b511d 9334 qdesc->hdwq = idx;
2d7dbc4c
JS
9335 phba->sli4_hba.nvmet_mrq_data[idx] = qdesc;
9336 }
9337 }
9338
4c47efc1
JS
9339 /* Clear NVME stats */
9340 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
9341 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9342 memset(&phba->sli4_hba.hdwq[idx].nvme_cstat, 0,
9343 sizeof(phba->sli4_hba.hdwq[idx].nvme_cstat));
9344 }
9345 }
4c47efc1
JS
9346
9347 /* Clear SCSI stats */
9348 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
9349 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9350 memset(&phba->sli4_hba.hdwq[idx].scsi_cstat, 0,
9351 sizeof(phba->sli4_hba.hdwq[idx].scsi_cstat));
9352 }
9353 }
9354
da0436e9
JS
9355 return 0;
9356
da0436e9 9357out_error:
67d12733 9358 lpfc_sli4_queue_destroy(phba);
da0436e9
JS
9359 return -ENOMEM;
9360}
9361
895427bd
JS
9362static inline void
9363__lpfc_sli4_release_queue(struct lpfc_queue **qp)
9364{
9365 if (*qp != NULL) {
9366 lpfc_sli4_queue_free(*qp);
9367 *qp = NULL;
9368 }
9369}
9370
9371static inline void
9372lpfc_sli4_release_queues(struct lpfc_queue ***qs, int max)
9373{
9374 int idx;
9375
9376 if (*qs == NULL)
9377 return;
9378
9379 for (idx = 0; idx < max; idx++)
9380 __lpfc_sli4_release_queue(&(*qs)[idx]);
9381
9382 kfree(*qs);
9383 *qs = NULL;
9384}
9385
9386static inline void
6a828b0f 9387lpfc_sli4_release_hdwq(struct lpfc_hba *phba)
895427bd 9388{
6a828b0f 9389 struct lpfc_sli4_hdw_queue *hdwq;
657add4e 9390 struct lpfc_queue *eq;
cdb42bec
JS
9391 uint32_t idx;
9392
6a828b0f 9393 hdwq = phba->sli4_hba.hdwq;
6a828b0f 9394
657add4e
JS
9395 /* Loop thru all Hardware Queues */
9396 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9397 /* Free the CQ/WQ corresponding to the Hardware Queue */
c00f62e6
JS
9398 lpfc_sli4_queue_free(hdwq[idx].io_cq);
9399 lpfc_sli4_queue_free(hdwq[idx].io_wq);
821bc882 9400 hdwq[idx].hba_eq = NULL;
c00f62e6
JS
9401 hdwq[idx].io_cq = NULL;
9402 hdwq[idx].io_wq = NULL;
d79c9e9d
JS
9403 if (phba->cfg_xpsgl && !phba->nvmet_support)
9404 lpfc_free_sgl_per_hdwq(phba, &hdwq[idx]);
9405 lpfc_free_cmd_rsp_buf_per_hdwq(phba, &hdwq[idx]);
895427bd 9406 }
657add4e
JS
9407 /* Loop thru all IRQ vectors */
9408 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
9409 /* Free the EQ corresponding to the IRQ vector */
9410 eq = phba->sli4_hba.hba_eq_hdl[idx].eq;
9411 lpfc_sli4_queue_free(eq);
9412 phba->sli4_hba.hba_eq_hdl[idx].eq = NULL;
9413 }
895427bd
JS
9414}
9415
da0436e9
JS
9416/**
9417 * lpfc_sli4_queue_destroy - Destroy all the SLI4 queues
9418 * @phba: pointer to lpfc hba data structure.
9419 *
9420 * This routine is invoked to release all the SLI4 queues with the FCoE HBA
9421 * operation.
9422 *
9423 * Return codes
af901ca1 9424 * 0 - successful
25985edc 9425 * -ENOMEM - No available memory
d439d286 9426 * -EIO - The mailbox failed to complete successfully.
da0436e9 9427 **/
5350d872 9428void
da0436e9
JS
9429lpfc_sli4_queue_destroy(struct lpfc_hba *phba)
9430{
4645f7b5
JS
9431 /*
9432 * Set FREE_INIT before beginning to free the queues.
9433 * Wait until the users of queues to acknowledge to
9434 * release queues by clearing FREE_WAIT.
9435 */
9436 spin_lock_irq(&phba->hbalock);
9437 phba->sli.sli_flag |= LPFC_QUEUE_FREE_INIT;
9438 while (phba->sli.sli_flag & LPFC_QUEUE_FREE_WAIT) {
9439 spin_unlock_irq(&phba->hbalock);
9440 msleep(20);
9441 spin_lock_irq(&phba->hbalock);
9442 }
9443 spin_unlock_irq(&phba->hbalock);
9444
93a4d6f4
JS
9445 lpfc_sli4_cleanup_poll_list(phba);
9446
895427bd 9447 /* Release HBA eqs */
cdb42bec 9448 if (phba->sli4_hba.hdwq)
6a828b0f 9449 lpfc_sli4_release_hdwq(phba);
895427bd 9450
bcb24f65
JS
9451 if (phba->nvmet_support) {
9452 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_cqset,
9453 phba->cfg_nvmet_mrq);
2d7dbc4c 9454
bcb24f65
JS
9455 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_hdr,
9456 phba->cfg_nvmet_mrq);
9457 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_data,
9458 phba->cfg_nvmet_mrq);
9459 }
2d7dbc4c 9460
895427bd
JS
9461 /* Release mailbox command work queue */
9462 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_wq);
9463
9464 /* Release ELS work queue */
9465 __lpfc_sli4_release_queue(&phba->sli4_hba.els_wq);
9466
9467 /* Release ELS work queue */
9468 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_wq);
9469
9470 /* Release unsolicited receive queue */
9471 __lpfc_sli4_release_queue(&phba->sli4_hba.hdr_rq);
9472 __lpfc_sli4_release_queue(&phba->sli4_hba.dat_rq);
9473
9474 /* Release ELS complete queue */
9475 __lpfc_sli4_release_queue(&phba->sli4_hba.els_cq);
9476
9477 /* Release NVME LS complete queue */
9478 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_cq);
9479
9480 /* Release mailbox command complete queue */
9481 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_cq);
9482
9483 /* Everything on this list has been freed */
9484 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
4645f7b5
JS
9485
9486 /* Done with freeing the queues */
9487 spin_lock_irq(&phba->hbalock);
9488 phba->sli.sli_flag &= ~LPFC_QUEUE_FREE_INIT;
9489 spin_unlock_irq(&phba->hbalock);
895427bd
JS
9490}
9491
895427bd
JS
9492int
9493lpfc_free_rq_buffer(struct lpfc_hba *phba, struct lpfc_queue *rq)
9494{
9495 struct lpfc_rqb *rqbp;
9496 struct lpfc_dmabuf *h_buf;
9497 struct rqb_dmabuf *rqb_buffer;
9498
9499 rqbp = rq->rqbp;
9500 while (!list_empty(&rqbp->rqb_buffer_list)) {
9501 list_remove_head(&rqbp->rqb_buffer_list, h_buf,
9502 struct lpfc_dmabuf, list);
9503
9504 rqb_buffer = container_of(h_buf, struct rqb_dmabuf, hbuf);
9505 (rqbp->rqb_free_buffer)(phba, rqb_buffer);
9506 rqbp->buffer_count--;
67d12733 9507 }
895427bd
JS
9508 return 1;
9509}
67d12733 9510
895427bd
JS
9511static int
9512lpfc_create_wq_cq(struct lpfc_hba *phba, struct lpfc_queue *eq,
9513 struct lpfc_queue *cq, struct lpfc_queue *wq, uint16_t *cq_map,
9514 int qidx, uint32_t qtype)
9515{
9516 struct lpfc_sli_ring *pring;
9517 int rc;
9518
9519 if (!eq || !cq || !wq) {
372c187b 9520 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9521 "6085 Fast-path %s (%d) not allocated\n",
9522 ((eq) ? ((cq) ? "WQ" : "CQ") : "EQ"), qidx);
9523 return -ENOMEM;
9524 }
9525
9526 /* create the Cq first */
9527 rc = lpfc_cq_create(phba, cq, eq,
9528 (qtype == LPFC_MBOX) ? LPFC_MCQ : LPFC_WCQ, qtype);
9529 if (rc) {
372c187b
DK
9530 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
9531 "6086 Failed setup of CQ (%d), rc = 0x%x\n",
9532 qidx, (uint32_t)rc);
895427bd 9533 return rc;
67d12733
JS
9534 }
9535
895427bd 9536 if (qtype != LPFC_MBOX) {
cdb42bec 9537 /* Setup cq_map for fast lookup */
895427bd
JS
9538 if (cq_map)
9539 *cq_map = cq->queue_id;
da0436e9 9540
895427bd
JS
9541 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9542 "6087 CQ setup: cq[%d]-id=%d, parent eq[%d]-id=%d\n",
9543 qidx, cq->queue_id, qidx, eq->queue_id);
da0436e9 9544
895427bd
JS
9545 /* create the wq */
9546 rc = lpfc_wq_create(phba, wq, cq, qtype);
9547 if (rc) {
372c187b 9548 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
c835c085 9549 "4618 Fail setup fastpath WQ (%d), rc = 0x%x\n",
895427bd
JS
9550 qidx, (uint32_t)rc);
9551 /* no need to tear down cq - caller will do so */
9552 return rc;
9553 }
da0436e9 9554
895427bd
JS
9555 /* Bind this CQ/WQ to the NVME ring */
9556 pring = wq->pring;
9557 pring->sli.sli4.wqp = (void *)wq;
9558 cq->pring = pring;
da0436e9 9559
895427bd
JS
9560 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9561 "2593 WQ setup: wq[%d]-id=%d assoc=%d, cq[%d]-id=%d\n",
9562 qidx, wq->queue_id, wq->assoc_qid, qidx, cq->queue_id);
9563 } else {
9564 rc = lpfc_mq_create(phba, wq, cq, LPFC_MBOX);
9565 if (rc) {
372c187b
DK
9566 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
9567 "0539 Failed setup of slow-path MQ: "
9568 "rc = 0x%x\n", rc);
895427bd
JS
9569 /* no need to tear down cq - caller will do so */
9570 return rc;
9571 }
da0436e9 9572
895427bd
JS
9573 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9574 "2589 MBX MQ setup: wq-id=%d, parent cq-id=%d\n",
9575 phba->sli4_hba.mbx_wq->queue_id,
9576 phba->sli4_hba.mbx_cq->queue_id);
67d12733 9577 }
da0436e9 9578
895427bd 9579 return 0;
da0436e9
JS
9580}
9581
6a828b0f
JS
9582/**
9583 * lpfc_setup_cq_lookup - Setup the CQ lookup table
9584 * @phba: pointer to lpfc hba data structure.
9585 *
9586 * This routine will populate the cq_lookup table by all
9587 * available CQ queue_id's.
9588 **/
3999df75 9589static void
6a828b0f
JS
9590lpfc_setup_cq_lookup(struct lpfc_hba *phba)
9591{
9592 struct lpfc_queue *eq, *childq;
6a828b0f
JS
9593 int qidx;
9594
6a828b0f
JS
9595 memset(phba->sli4_hba.cq_lookup, 0,
9596 (sizeof(struct lpfc_queue *) * (phba->sli4_hba.cq_max + 1)));
657add4e 9597 /* Loop thru all IRQ vectors */
6a828b0f 9598 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
657add4e
JS
9599 /* Get the EQ corresponding to the IRQ vector */
9600 eq = phba->sli4_hba.hba_eq_hdl[qidx].eq;
6a828b0f
JS
9601 if (!eq)
9602 continue;
657add4e 9603 /* Loop through all CQs associated with that EQ */
6a828b0f
JS
9604 list_for_each_entry(childq, &eq->child_list, list) {
9605 if (childq->queue_id > phba->sli4_hba.cq_max)
9606 continue;
c00f62e6 9607 if (childq->subtype == LPFC_IO)
6a828b0f
JS
9608 phba->sli4_hba.cq_lookup[childq->queue_id] =
9609 childq;
9610 }
9611 }
9612}
9613
da0436e9
JS
9614/**
9615 * lpfc_sli4_queue_setup - Set up all the SLI4 queues
9616 * @phba: pointer to lpfc hba data structure.
9617 *
9618 * This routine is invoked to set up all the SLI4 queues for the FCoE HBA
9619 * operation.
9620 *
9621 * Return codes
af901ca1 9622 * 0 - successful
25985edc 9623 * -ENOMEM - No available memory
d439d286 9624 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
9625 **/
9626int
9627lpfc_sli4_queue_setup(struct lpfc_hba *phba)
9628{
962bc51b
JS
9629 uint32_t shdr_status, shdr_add_status;
9630 union lpfc_sli4_cfg_shdr *shdr;
657add4e 9631 struct lpfc_vector_map_info *cpup;
cdb42bec 9632 struct lpfc_sli4_hdw_queue *qp;
962bc51b 9633 LPFC_MBOXQ_t *mboxq;
657add4e 9634 int qidx, cpu;
cb733e35 9635 uint32_t length, usdelay;
895427bd 9636 int rc = -ENOMEM;
962bc51b
JS
9637
9638 /* Check for dual-ULP support */
9639 mboxq = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9640 if (!mboxq) {
372c187b 9641 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
962bc51b
JS
9642 "3249 Unable to allocate memory for "
9643 "QUERY_FW_CFG mailbox command\n");
9644 return -ENOMEM;
9645 }
9646 length = (sizeof(struct lpfc_mbx_query_fw_config) -
9647 sizeof(struct lpfc_sli4_cfg_mhdr));
9648 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
9649 LPFC_MBOX_OPCODE_QUERY_FW_CFG,
9650 length, LPFC_SLI4_MBX_EMBED);
9651
9652 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
9653
9654 shdr = (union lpfc_sli4_cfg_shdr *)
9655 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
9656 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
9657 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
9658 if (shdr_status || shdr_add_status || rc) {
372c187b 9659 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
962bc51b
JS
9660 "3250 QUERY_FW_CFG mailbox failed with status "
9661 "x%x add_status x%x, mbx status x%x\n",
9662 shdr_status, shdr_add_status, rc);
9663 if (rc != MBX_TIMEOUT)
9664 mempool_free(mboxq, phba->mbox_mem_pool);
9665 rc = -ENXIO;
9666 goto out_error;
9667 }
9668
9669 phba->sli4_hba.fw_func_mode =
9670 mboxq->u.mqe.un.query_fw_cfg.rsp.function_mode;
9671 phba->sli4_hba.ulp0_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp0_mode;
9672 phba->sli4_hba.ulp1_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp1_mode;
8b017a30
JS
9673 phba->sli4_hba.physical_port =
9674 mboxq->u.mqe.un.query_fw_cfg.rsp.physical_port;
962bc51b
JS
9675 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9676 "3251 QUERY_FW_CFG: func_mode:x%x, ulp0_mode:x%x, "
9677 "ulp1_mode:x%x\n", phba->sli4_hba.fw_func_mode,
9678 phba->sli4_hba.ulp0_mode, phba->sli4_hba.ulp1_mode);
9679
9680 if (rc != MBX_TIMEOUT)
9681 mempool_free(mboxq, phba->mbox_mem_pool);
da0436e9
JS
9682
9683 /*
67d12733 9684 * Set up HBA Event Queues (EQs)
da0436e9 9685 */
cdb42bec 9686 qp = phba->sli4_hba.hdwq;
da0436e9 9687
67d12733 9688 /* Set up HBA event queue */
cdb42bec 9689 if (!qp) {
372c187b 9690 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2e90f4b5 9691 "3147 Fast-path EQs not allocated\n");
1b51197d 9692 rc = -ENOMEM;
67d12733 9693 goto out_error;
2e90f4b5 9694 }
657add4e
JS
9695
9696 /* Loop thru all IRQ vectors */
6a828b0f 9697 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
657add4e
JS
9698 /* Create HBA Event Queues (EQs) in order */
9699 for_each_present_cpu(cpu) {
9700 cpup = &phba->sli4_hba.cpu_map[cpu];
9701
9702 /* Look for the CPU thats using that vector with
9703 * LPFC_CPU_FIRST_IRQ set.
9704 */
9705 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
9706 continue;
9707 if (qidx != cpup->eq)
9708 continue;
9709
9710 /* Create an EQ for that vector */
9711 rc = lpfc_eq_create(phba, qp[cpup->hdwq].hba_eq,
9712 phba->cfg_fcp_imax);
9713 if (rc) {
372c187b 9714 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
657add4e
JS
9715 "0523 Failed setup of fast-path"
9716 " EQ (%d), rc = 0x%x\n",
9717 cpup->eq, (uint32_t)rc);
9718 goto out_destroy;
9719 }
9720
9721 /* Save the EQ for that vector in the hba_eq_hdl */
9722 phba->sli4_hba.hba_eq_hdl[cpup->eq].eq =
9723 qp[cpup->hdwq].hba_eq;
9724
9725 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9726 "2584 HBA EQ setup: queue[%d]-id=%d\n",
9727 cpup->eq,
9728 qp[cpup->hdwq].hba_eq->queue_id);
da0436e9 9729 }
67d12733
JS
9730 }
9731
657add4e 9732 /* Loop thru all Hardware Queues */
cdb42bec 9733 for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {
657add4e
JS
9734 cpu = lpfc_find_cpu_handle(phba, qidx, LPFC_FIND_BY_HDWQ);
9735 cpup = &phba->sli4_hba.cpu_map[cpu];
9736
9737 /* Create the CQ/WQ corresponding to the Hardware Queue */
cdb42bec 9738 rc = lpfc_create_wq_cq(phba,
657add4e 9739 phba->sli4_hba.hdwq[cpup->hdwq].hba_eq,
c00f62e6
JS
9740 qp[qidx].io_cq,
9741 qp[qidx].io_wq,
9742 &phba->sli4_hba.hdwq[qidx].io_cq_map,
9743 qidx,
9744 LPFC_IO);
cdb42bec 9745 if (rc) {
372c187b 9746 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd 9747 "0535 Failed to setup fastpath "
c00f62e6 9748 "IO WQ/CQ (%d), rc = 0x%x\n",
895427bd 9749 qidx, (uint32_t)rc);
cdb42bec 9750 goto out_destroy;
895427bd 9751 }
67d12733 9752 }
895427bd 9753
da0436e9 9754 /*
895427bd 9755 * Set up Slow Path Complete Queues (CQs)
da0436e9
JS
9756 */
9757
895427bd 9758 /* Set up slow-path MBOX CQ/MQ */
da0436e9 9759
895427bd 9760 if (!phba->sli4_hba.mbx_cq || !phba->sli4_hba.mbx_wq) {
372c187b 9761 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9762 "0528 %s not allocated\n",
9763 phba->sli4_hba.mbx_cq ?
d1f525aa 9764 "Mailbox WQ" : "Mailbox CQ");
1b51197d 9765 rc = -ENOMEM;
895427bd 9766 goto out_destroy;
da0436e9 9767 }
da0436e9 9768
cdb42bec 9769 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
d1f525aa
JS
9770 phba->sli4_hba.mbx_cq,
9771 phba->sli4_hba.mbx_wq,
9772 NULL, 0, LPFC_MBOX);
da0436e9 9773 if (rc) {
372c187b 9774 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9775 "0529 Failed setup of mailbox WQ/CQ: rc = 0x%x\n",
9776 (uint32_t)rc);
9777 goto out_destroy;
da0436e9 9778 }
2d7dbc4c
JS
9779 if (phba->nvmet_support) {
9780 if (!phba->sli4_hba.nvmet_cqset) {
372c187b 9781 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9782 "3165 Fast-path NVME CQ Set "
9783 "array not allocated\n");
9784 rc = -ENOMEM;
9785 goto out_destroy;
9786 }
9787 if (phba->cfg_nvmet_mrq > 1) {
9788 rc = lpfc_cq_create_set(phba,
9789 phba->sli4_hba.nvmet_cqset,
cdb42bec 9790 qp,
2d7dbc4c
JS
9791 LPFC_WCQ, LPFC_NVMET);
9792 if (rc) {
372c187b 9793 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9794 "3164 Failed setup of NVME CQ "
9795 "Set, rc = 0x%x\n",
9796 (uint32_t)rc);
9797 goto out_destroy;
9798 }
9799 } else {
9800 /* Set up NVMET Receive Complete Queue */
9801 rc = lpfc_cq_create(phba, phba->sli4_hba.nvmet_cqset[0],
cdb42bec 9802 qp[0].hba_eq,
2d7dbc4c
JS
9803 LPFC_WCQ, LPFC_NVMET);
9804 if (rc) {
372c187b 9805 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9806 "6089 Failed setup NVMET CQ: "
9807 "rc = 0x%x\n", (uint32_t)rc);
9808 goto out_destroy;
9809 }
81b96eda
JS
9810 phba->sli4_hba.nvmet_cqset[0]->chann = 0;
9811
2d7dbc4c
JS
9812 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9813 "6090 NVMET CQ setup: cq-id=%d, "
9814 "parent eq-id=%d\n",
9815 phba->sli4_hba.nvmet_cqset[0]->queue_id,
cdb42bec 9816 qp[0].hba_eq->queue_id);
2d7dbc4c
JS
9817 }
9818 }
da0436e9 9819
895427bd
JS
9820 /* Set up slow-path ELS WQ/CQ */
9821 if (!phba->sli4_hba.els_cq || !phba->sli4_hba.els_wq) {
372c187b 9822 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9823 "0530 ELS %s not allocated\n",
9824 phba->sli4_hba.els_cq ? "WQ" : "CQ");
1b51197d 9825 rc = -ENOMEM;
895427bd 9826 goto out_destroy;
da0436e9 9827 }
cdb42bec
JS
9828 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
9829 phba->sli4_hba.els_cq,
9830 phba->sli4_hba.els_wq,
9831 NULL, 0, LPFC_ELS);
da0436e9 9832 if (rc) {
372c187b 9833 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
cdb42bec
JS
9834 "0525 Failed setup of ELS WQ/CQ: rc = 0x%x\n",
9835 (uint32_t)rc);
895427bd 9836 goto out_destroy;
da0436e9
JS
9837 }
9838 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9839 "2590 ELS WQ setup: wq-id=%d, parent cq-id=%d\n",
9840 phba->sli4_hba.els_wq->queue_id,
9841 phba->sli4_hba.els_cq->queue_id);
9842
cdb42bec 9843 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
895427bd
JS
9844 /* Set up NVME LS Complete Queue */
9845 if (!phba->sli4_hba.nvmels_cq || !phba->sli4_hba.nvmels_wq) {
372c187b 9846 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9847 "6091 LS %s not allocated\n",
9848 phba->sli4_hba.nvmels_cq ? "WQ" : "CQ");
9849 rc = -ENOMEM;
9850 goto out_destroy;
9851 }
cdb42bec
JS
9852 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
9853 phba->sli4_hba.nvmels_cq,
9854 phba->sli4_hba.nvmels_wq,
9855 NULL, 0, LPFC_NVME_LS);
895427bd 9856 if (rc) {
372c187b 9857 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
cdb42bec
JS
9858 "0526 Failed setup of NVVME LS WQ/CQ: "
9859 "rc = 0x%x\n", (uint32_t)rc);
895427bd
JS
9860 goto out_destroy;
9861 }
9862
9863 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9864 "6096 ELS WQ setup: wq-id=%d, "
9865 "parent cq-id=%d\n",
9866 phba->sli4_hba.nvmels_wq->queue_id,
9867 phba->sli4_hba.nvmels_cq->queue_id);
9868 }
9869
2d7dbc4c
JS
9870 /*
9871 * Create NVMET Receive Queue (RQ)
9872 */
9873 if (phba->nvmet_support) {
9874 if ((!phba->sli4_hba.nvmet_cqset) ||
9875 (!phba->sli4_hba.nvmet_mrq_hdr) ||
9876 (!phba->sli4_hba.nvmet_mrq_data)) {
372c187b 9877 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9878 "6130 MRQ CQ Queues not "
9879 "allocated\n");
9880 rc = -ENOMEM;
9881 goto out_destroy;
9882 }
9883 if (phba->cfg_nvmet_mrq > 1) {
9884 rc = lpfc_mrq_create(phba,
9885 phba->sli4_hba.nvmet_mrq_hdr,
9886 phba->sli4_hba.nvmet_mrq_data,
9887 phba->sli4_hba.nvmet_cqset,
9888 LPFC_NVMET);
9889 if (rc) {
372c187b 9890 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9891 "6098 Failed setup of NVMET "
9892 "MRQ: rc = 0x%x\n",
9893 (uint32_t)rc);
9894 goto out_destroy;
9895 }
9896
9897 } else {
9898 rc = lpfc_rq_create(phba,
9899 phba->sli4_hba.nvmet_mrq_hdr[0],
9900 phba->sli4_hba.nvmet_mrq_data[0],
9901 phba->sli4_hba.nvmet_cqset[0],
9902 LPFC_NVMET);
9903 if (rc) {
372c187b 9904 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9905 "6057 Failed setup of NVMET "
9906 "Receive Queue: rc = 0x%x\n",
9907 (uint32_t)rc);
9908 goto out_destroy;
9909 }
9910
9911 lpfc_printf_log(
9912 phba, KERN_INFO, LOG_INIT,
9913 "6099 NVMET RQ setup: hdr-rq-id=%d, "
9914 "dat-rq-id=%d parent cq-id=%d\n",
9915 phba->sli4_hba.nvmet_mrq_hdr[0]->queue_id,
9916 phba->sli4_hba.nvmet_mrq_data[0]->queue_id,
9917 phba->sli4_hba.nvmet_cqset[0]->queue_id);
9918
9919 }
9920 }
9921
da0436e9 9922 if (!phba->sli4_hba.hdr_rq || !phba->sli4_hba.dat_rq) {
372c187b 9923 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9924 "0540 Receive Queue not allocated\n");
1b51197d 9925 rc = -ENOMEM;
895427bd 9926 goto out_destroy;
da0436e9 9927 }
73d91e50 9928
da0436e9 9929 rc = lpfc_rq_create(phba, phba->sli4_hba.hdr_rq, phba->sli4_hba.dat_rq,
4d9ab994 9930 phba->sli4_hba.els_cq, LPFC_USOL);
da0436e9 9931 if (rc) {
372c187b 9932 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9933 "0541 Failed setup of Receive Queue: "
a2fc4aef 9934 "rc = 0x%x\n", (uint32_t)rc);
895427bd 9935 goto out_destroy;
da0436e9 9936 }
73d91e50 9937
da0436e9
JS
9938 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9939 "2592 USL RQ setup: hdr-rq-id=%d, dat-rq-id=%d "
9940 "parent cq-id=%d\n",
9941 phba->sli4_hba.hdr_rq->queue_id,
9942 phba->sli4_hba.dat_rq->queue_id,
4d9ab994 9943 phba->sli4_hba.els_cq->queue_id);
1ba981fd 9944
cb733e35
JS
9945 if (phba->cfg_fcp_imax)
9946 usdelay = LPFC_SEC_TO_USEC / phba->cfg_fcp_imax;
9947 else
9948 usdelay = 0;
9949
6a828b0f 9950 for (qidx = 0; qidx < phba->cfg_irq_chann;
cdb42bec 9951 qidx += LPFC_MAX_EQ_DELAY_EQID_CNT)
0cf07f84 9952 lpfc_modify_hba_eq_delay(phba, qidx, LPFC_MAX_EQ_DELAY_EQID_CNT,
cb733e35 9953 usdelay);
43140ca6 9954
6a828b0f
JS
9955 if (phba->sli4_hba.cq_max) {
9956 kfree(phba->sli4_hba.cq_lookup);
9957 phba->sli4_hba.cq_lookup = kcalloc((phba->sli4_hba.cq_max + 1),
9958 sizeof(struct lpfc_queue *), GFP_KERNEL);
9959 if (!phba->sli4_hba.cq_lookup) {
372c187b 9960 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
6a828b0f
JS
9961 "0549 Failed setup of CQ Lookup table: "
9962 "size 0x%x\n", phba->sli4_hba.cq_max);
fad28e3d 9963 rc = -ENOMEM;
895427bd 9964 goto out_destroy;
1ba981fd 9965 }
6a828b0f 9966 lpfc_setup_cq_lookup(phba);
1ba981fd 9967 }
da0436e9
JS
9968 return 0;
9969
895427bd
JS
9970out_destroy:
9971 lpfc_sli4_queue_unset(phba);
da0436e9
JS
9972out_error:
9973 return rc;
9974}
9975
9976/**
9977 * lpfc_sli4_queue_unset - Unset all the SLI4 queues
9978 * @phba: pointer to lpfc hba data structure.
9979 *
9980 * This routine is invoked to unset all the SLI4 queues with the FCoE HBA
9981 * operation.
9982 *
9983 * Return codes
af901ca1 9984 * 0 - successful
25985edc 9985 * -ENOMEM - No available memory
d439d286 9986 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
9987 **/
9988void
9989lpfc_sli4_queue_unset(struct lpfc_hba *phba)
9990{
cdb42bec 9991 struct lpfc_sli4_hdw_queue *qp;
657add4e 9992 struct lpfc_queue *eq;
895427bd 9993 int qidx;
da0436e9
JS
9994
9995 /* Unset mailbox command work queue */
895427bd
JS
9996 if (phba->sli4_hba.mbx_wq)
9997 lpfc_mq_destroy(phba, phba->sli4_hba.mbx_wq);
9998
9999 /* Unset NVME LS work queue */
10000 if (phba->sli4_hba.nvmels_wq)
10001 lpfc_wq_destroy(phba, phba->sli4_hba.nvmels_wq);
10002
da0436e9 10003 /* Unset ELS work queue */
019c0d66 10004 if (phba->sli4_hba.els_wq)
895427bd
JS
10005 lpfc_wq_destroy(phba, phba->sli4_hba.els_wq);
10006
da0436e9 10007 /* Unset unsolicited receive queue */
895427bd
JS
10008 if (phba->sli4_hba.hdr_rq)
10009 lpfc_rq_destroy(phba, phba->sli4_hba.hdr_rq,
10010 phba->sli4_hba.dat_rq);
10011
da0436e9 10012 /* Unset mailbox command complete queue */
895427bd
JS
10013 if (phba->sli4_hba.mbx_cq)
10014 lpfc_cq_destroy(phba, phba->sli4_hba.mbx_cq);
10015
da0436e9 10016 /* Unset ELS complete queue */
895427bd
JS
10017 if (phba->sli4_hba.els_cq)
10018 lpfc_cq_destroy(phba, phba->sli4_hba.els_cq);
10019
10020 /* Unset NVME LS complete queue */
10021 if (phba->sli4_hba.nvmels_cq)
10022 lpfc_cq_destroy(phba, phba->sli4_hba.nvmels_cq);
10023
bcb24f65
JS
10024 if (phba->nvmet_support) {
10025 /* Unset NVMET MRQ queue */
10026 if (phba->sli4_hba.nvmet_mrq_hdr) {
10027 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
10028 lpfc_rq_destroy(
10029 phba,
2d7dbc4c
JS
10030 phba->sli4_hba.nvmet_mrq_hdr[qidx],
10031 phba->sli4_hba.nvmet_mrq_data[qidx]);
bcb24f65 10032 }
2d7dbc4c 10033
bcb24f65
JS
10034 /* Unset NVMET CQ Set complete queue */
10035 if (phba->sli4_hba.nvmet_cqset) {
10036 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
10037 lpfc_cq_destroy(
10038 phba, phba->sli4_hba.nvmet_cqset[qidx]);
10039 }
2d7dbc4c
JS
10040 }
10041
cdb42bec
JS
10042 /* Unset fast-path SLI4 queues */
10043 if (phba->sli4_hba.hdwq) {
657add4e 10044 /* Loop thru all Hardware Queues */
cdb42bec 10045 for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {
657add4e 10046 /* Destroy the CQ/WQ corresponding to Hardware Queue */
cdb42bec 10047 qp = &phba->sli4_hba.hdwq[qidx];
c00f62e6
JS
10048 lpfc_wq_destroy(phba, qp->io_wq);
10049 lpfc_cq_destroy(phba, qp->io_cq);
657add4e
JS
10050 }
10051 /* Loop thru all IRQ vectors */
10052 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
10053 /* Destroy the EQ corresponding to the IRQ vector */
10054 eq = phba->sli4_hba.hba_eq_hdl[qidx].eq;
10055 lpfc_eq_destroy(phba, eq);
cdb42bec
JS
10056 }
10057 }
895427bd 10058
6a828b0f
JS
10059 kfree(phba->sli4_hba.cq_lookup);
10060 phba->sli4_hba.cq_lookup = NULL;
10061 phba->sli4_hba.cq_max = 0;
da0436e9
JS
10062}
10063
10064/**
10065 * lpfc_sli4_cq_event_pool_create - Create completion-queue event free pool
10066 * @phba: pointer to lpfc hba data structure.
10067 *
10068 * This routine is invoked to allocate and set up a pool of completion queue
10069 * events. The body of the completion queue event is a completion queue entry
10070 * CQE. For now, this pool is used for the interrupt service routine to queue
10071 * the following HBA completion queue events for the worker thread to process:
10072 * - Mailbox asynchronous events
10073 * - Receive queue completion unsolicited events
10074 * Later, this can be used for all the slow-path events.
10075 *
10076 * Return codes
af901ca1 10077 * 0 - successful
25985edc 10078 * -ENOMEM - No available memory
da0436e9
JS
10079 **/
10080static int
10081lpfc_sli4_cq_event_pool_create(struct lpfc_hba *phba)
10082{
10083 struct lpfc_cq_event *cq_event;
10084 int i;
10085
10086 for (i = 0; i < (4 * phba->sli4_hba.cq_ecount); i++) {
10087 cq_event = kmalloc(sizeof(struct lpfc_cq_event), GFP_KERNEL);
10088 if (!cq_event)
10089 goto out_pool_create_fail;
10090 list_add_tail(&cq_event->list,
10091 &phba->sli4_hba.sp_cqe_event_pool);
10092 }
10093 return 0;
10094
10095out_pool_create_fail:
10096 lpfc_sli4_cq_event_pool_destroy(phba);
10097 return -ENOMEM;
10098}
10099
10100/**
10101 * lpfc_sli4_cq_event_pool_destroy - Free completion-queue event free pool
10102 * @phba: pointer to lpfc hba data structure.
10103 *
10104 * This routine is invoked to free the pool of completion queue events at
10105 * driver unload time. Note that, it is the responsibility of the driver
10106 * cleanup routine to free all the outstanding completion-queue events
10107 * allocated from this pool back into the pool before invoking this routine
10108 * to destroy the pool.
10109 **/
10110static void
10111lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *phba)
10112{
10113 struct lpfc_cq_event *cq_event, *next_cq_event;
10114
10115 list_for_each_entry_safe(cq_event, next_cq_event,
10116 &phba->sli4_hba.sp_cqe_event_pool, list) {
10117 list_del(&cq_event->list);
10118 kfree(cq_event);
10119 }
10120}
10121
10122/**
10123 * __lpfc_sli4_cq_event_alloc - Allocate a completion-queue event from free pool
10124 * @phba: pointer to lpfc hba data structure.
10125 *
10126 * This routine is the lock free version of the API invoked to allocate a
10127 * completion-queue event from the free pool.
10128 *
10129 * Return: Pointer to the newly allocated completion-queue event if successful
10130 * NULL otherwise.
10131 **/
10132struct lpfc_cq_event *
10133__lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
10134{
10135 struct lpfc_cq_event *cq_event = NULL;
10136
10137 list_remove_head(&phba->sli4_hba.sp_cqe_event_pool, cq_event,
10138 struct lpfc_cq_event, list);
10139 return cq_event;
10140}
10141
10142/**
10143 * lpfc_sli4_cq_event_alloc - Allocate a completion-queue event from free pool
10144 * @phba: pointer to lpfc hba data structure.
10145 *
10146 * This routine is the lock version of the API invoked to allocate a
10147 * completion-queue event from the free pool.
10148 *
10149 * Return: Pointer to the newly allocated completion-queue event if successful
10150 * NULL otherwise.
10151 **/
10152struct lpfc_cq_event *
10153lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
10154{
10155 struct lpfc_cq_event *cq_event;
10156 unsigned long iflags;
10157
10158 spin_lock_irqsave(&phba->hbalock, iflags);
10159 cq_event = __lpfc_sli4_cq_event_alloc(phba);
10160 spin_unlock_irqrestore(&phba->hbalock, iflags);
10161 return cq_event;
10162}
10163
10164/**
10165 * __lpfc_sli4_cq_event_release - Release a completion-queue event to free pool
10166 * @phba: pointer to lpfc hba data structure.
10167 * @cq_event: pointer to the completion queue event to be freed.
10168 *
10169 * This routine is the lock free version of the API invoked to release a
10170 * completion-queue event back into the free pool.
10171 **/
10172void
10173__lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
10174 struct lpfc_cq_event *cq_event)
10175{
10176 list_add_tail(&cq_event->list, &phba->sli4_hba.sp_cqe_event_pool);
10177}
10178
10179/**
10180 * lpfc_sli4_cq_event_release - Release a completion-queue event to free pool
10181 * @phba: pointer to lpfc hba data structure.
10182 * @cq_event: pointer to the completion queue event to be freed.
10183 *
10184 * This routine is the lock version of the API invoked to release a
10185 * completion-queue event back into the free pool.
10186 **/
10187void
10188lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
10189 struct lpfc_cq_event *cq_event)
10190{
10191 unsigned long iflags;
10192 spin_lock_irqsave(&phba->hbalock, iflags);
10193 __lpfc_sli4_cq_event_release(phba, cq_event);
10194 spin_unlock_irqrestore(&phba->hbalock, iflags);
10195}
10196
10197/**
10198 * lpfc_sli4_cq_event_release_all - Release all cq events to the free pool
10199 * @phba: pointer to lpfc hba data structure.
10200 *
10201 * This routine is to free all the pending completion-queue events to the
10202 * back into the free pool for device reset.
10203 **/
10204static void
10205lpfc_sli4_cq_event_release_all(struct lpfc_hba *phba)
10206{
e7dab164
JS
10207 LIST_HEAD(cq_event_list);
10208 struct lpfc_cq_event *cq_event;
da0436e9
JS
10209 unsigned long iflags;
10210
10211 /* Retrieve all the pending WCQEs from pending WCQE lists */
e7dab164 10212
da0436e9 10213 /* Pending ELS XRI abort events */
e7dab164 10214 spin_lock_irqsave(&phba->sli4_hba.els_xri_abrt_list_lock, iflags);
da0436e9 10215 list_splice_init(&phba->sli4_hba.sp_els_xri_aborted_work_queue,
e7dab164
JS
10216 &cq_event_list);
10217 spin_unlock_irqrestore(&phba->sli4_hba.els_xri_abrt_list_lock, iflags);
10218
da0436e9 10219 /* Pending asynnc events */
e7dab164 10220 spin_lock_irqsave(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9 10221 list_splice_init(&phba->sli4_hba.sp_asynce_work_queue,
e7dab164
JS
10222 &cq_event_list);
10223 spin_unlock_irqrestore(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9 10224
e7dab164
JS
10225 while (!list_empty(&cq_event_list)) {
10226 list_remove_head(&cq_event_list, cq_event,
10227 struct lpfc_cq_event, list);
10228 lpfc_sli4_cq_event_release(phba, cq_event);
da0436e9
JS
10229 }
10230}
10231
10232/**
10233 * lpfc_pci_function_reset - Reset pci function.
10234 * @phba: pointer to lpfc hba data structure.
10235 *
10236 * This routine is invoked to request a PCI function reset. It will destroys
10237 * all resources assigned to the PCI function which originates this request.
10238 *
10239 * Return codes
af901ca1 10240 * 0 - successful
25985edc 10241 * -ENOMEM - No available memory
d439d286 10242 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
10243 **/
10244int
10245lpfc_pci_function_reset(struct lpfc_hba *phba)
10246{
10247 LPFC_MBOXQ_t *mboxq;
2fcee4bf 10248 uint32_t rc = 0, if_type;
da0436e9 10249 uint32_t shdr_status, shdr_add_status;
2f6fa2c9
JS
10250 uint32_t rdy_chk;
10251 uint32_t port_reset = 0;
da0436e9 10252 union lpfc_sli4_cfg_shdr *shdr;
2fcee4bf 10253 struct lpfc_register reg_data;
2b81f942 10254 uint16_t devid;
da0436e9 10255
2fcee4bf
JS
10256 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
10257 switch (if_type) {
10258 case LPFC_SLI_INTF_IF_TYPE_0:
10259 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
10260 GFP_KERNEL);
10261 if (!mboxq) {
372c187b 10262 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
10263 "0494 Unable to allocate memory for "
10264 "issuing SLI_FUNCTION_RESET mailbox "
10265 "command\n");
10266 return -ENOMEM;
10267 }
da0436e9 10268
2fcee4bf
JS
10269 /* Setup PCI function reset mailbox-ioctl command */
10270 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
10271 LPFC_MBOX_OPCODE_FUNCTION_RESET, 0,
10272 LPFC_SLI4_MBX_EMBED);
10273 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
10274 shdr = (union lpfc_sli4_cfg_shdr *)
10275 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
10276 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
10277 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status,
10278 &shdr->response);
10279 if (rc != MBX_TIMEOUT)
10280 mempool_free(mboxq, phba->mbox_mem_pool);
10281 if (shdr_status || shdr_add_status || rc) {
372c187b 10282 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
10283 "0495 SLI_FUNCTION_RESET mailbox "
10284 "failed with status x%x add_status x%x,"
10285 " mbx status x%x\n",
10286 shdr_status, shdr_add_status, rc);
10287 rc = -ENXIO;
10288 }
10289 break;
10290 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 10291 case LPFC_SLI_INTF_IF_TYPE_6:
2f6fa2c9
JS
10292wait:
10293 /*
10294 * Poll the Port Status Register and wait for RDY for
10295 * up to 30 seconds. If the port doesn't respond, treat
10296 * it as an error.
10297 */
77d093fb 10298 for (rdy_chk = 0; rdy_chk < 1500; rdy_chk++) {
2f6fa2c9
JS
10299 if (lpfc_readl(phba->sli4_hba.u.if_type2.
10300 STATUSregaddr, &reg_data.word0)) {
10301 rc = -ENODEV;
10302 goto out;
10303 }
10304 if (bf_get(lpfc_sliport_status_rdy, &reg_data))
10305 break;
10306 msleep(20);
10307 }
10308
10309 if (!bf_get(lpfc_sliport_status_rdy, &reg_data)) {
10310 phba->work_status[0] = readl(
10311 phba->sli4_hba.u.if_type2.ERR1regaddr);
10312 phba->work_status[1] = readl(
10313 phba->sli4_hba.u.if_type2.ERR2regaddr);
372c187b 10314 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2f6fa2c9
JS
10315 "2890 Port not ready, port status reg "
10316 "0x%x error 1=0x%x, error 2=0x%x\n",
10317 reg_data.word0,
10318 phba->work_status[0],
10319 phba->work_status[1]);
10320 rc = -ENODEV;
10321 goto out;
10322 }
10323
10324 if (!port_reset) {
10325 /*
10326 * Reset the port now
10327 */
2fcee4bf
JS
10328 reg_data.word0 = 0;
10329 bf_set(lpfc_sliport_ctrl_end, &reg_data,
10330 LPFC_SLIPORT_LITTLE_ENDIAN);
10331 bf_set(lpfc_sliport_ctrl_ip, &reg_data,
10332 LPFC_SLIPORT_INIT_PORT);
10333 writel(reg_data.word0, phba->sli4_hba.u.if_type2.
10334 CTRLregaddr);
8fcb8acd 10335 /* flush */
2b81f942
JS
10336 pci_read_config_word(phba->pcidev,
10337 PCI_DEVICE_ID, &devid);
2fcee4bf 10338
2f6fa2c9
JS
10339 port_reset = 1;
10340 msleep(20);
10341 goto wait;
10342 } else if (bf_get(lpfc_sliport_status_rn, &reg_data)) {
10343 rc = -ENODEV;
10344 goto out;
2fcee4bf
JS
10345 }
10346 break;
2f6fa2c9 10347
2fcee4bf
JS
10348 case LPFC_SLI_INTF_IF_TYPE_1:
10349 default:
10350 break;
da0436e9 10351 }
2fcee4bf 10352
73d91e50 10353out:
2fcee4bf 10354 /* Catch the not-ready port failure after a port reset. */
2f6fa2c9 10355 if (rc) {
372c187b 10356 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
229adb0e 10357 "3317 HBA not functional: IP Reset Failed "
2f6fa2c9 10358 "try: echo fw_reset > board_mode\n");
2fcee4bf 10359 rc = -ENODEV;
229adb0e 10360 }
2fcee4bf 10361
da0436e9
JS
10362 return rc;
10363}
10364
da0436e9
JS
10365/**
10366 * lpfc_sli4_pci_mem_setup - Setup SLI4 HBA PCI memory space.
10367 * @phba: pointer to lpfc hba data structure.
10368 *
10369 * This routine is invoked to set up the PCI device memory space for device
10370 * with SLI-4 interface spec.
10371 *
10372 * Return codes
af901ca1 10373 * 0 - successful
da0436e9
JS
10374 * other values - error
10375 **/
10376static int
10377lpfc_sli4_pci_mem_setup(struct lpfc_hba *phba)
10378{
f30e1bfd 10379 struct pci_dev *pdev = phba->pcidev;
da0436e9 10380 unsigned long bar0map_len, bar1map_len, bar2map_len;
3a487ff7 10381 int error;
2fcee4bf 10382 uint32_t if_type;
da0436e9 10383
f30e1bfd 10384 if (!pdev)
56de8357 10385 return -ENODEV;
da0436e9
JS
10386
10387 /* Set the device DMA mask size */
56de8357
HR
10388 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
10389 if (error)
10390 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10391 if (error)
f30e1bfd 10392 return error;
da0436e9 10393
2fcee4bf
JS
10394 /*
10395 * The BARs and register set definitions and offset locations are
10396 * dependent on the if_type.
10397 */
10398 if (pci_read_config_dword(pdev, LPFC_SLI_INTF,
10399 &phba->sli4_hba.sli_intf.word0)) {
3a487ff7 10400 return -ENODEV;
2fcee4bf
JS
10401 }
10402
10403 /* There is no SLI3 failback for SLI4 devices. */
10404 if (bf_get(lpfc_sli_intf_valid, &phba->sli4_hba.sli_intf) !=
10405 LPFC_SLI_INTF_VALID) {
372c187b 10406 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
10407 "2894 SLI_INTF reg contents invalid "
10408 "sli_intf reg 0x%x\n",
10409 phba->sli4_hba.sli_intf.word0);
3a487ff7 10410 return -ENODEV;
2fcee4bf
JS
10411 }
10412
10413 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
10414 /*
10415 * Get the bus address of SLI4 device Bar regions and the
10416 * number of bytes required by each mapping. The mapping of the
10417 * particular PCI BARs regions is dependent on the type of
10418 * SLI4 device.
da0436e9 10419 */
f5ca6f2e
JS
10420 if (pci_resource_start(pdev, PCI_64BIT_BAR0)) {
10421 phba->pci_bar0_map = pci_resource_start(pdev, PCI_64BIT_BAR0);
10422 bar0map_len = pci_resource_len(pdev, PCI_64BIT_BAR0);
2fcee4bf
JS
10423
10424 /*
10425 * Map SLI4 PCI Config Space Register base to a kernel virtual
10426 * addr
10427 */
10428 phba->sli4_hba.conf_regs_memmap_p =
10429 ioremap(phba->pci_bar0_map, bar0map_len);
10430 if (!phba->sli4_hba.conf_regs_memmap_p) {
10431 dev_printk(KERN_ERR, &pdev->dev,
10432 "ioremap failed for SLI4 PCI config "
10433 "registers.\n");
3a487ff7 10434 return -ENODEV;
2fcee4bf 10435 }
f5ca6f2e 10436 phba->pci_bar0_memmap_p = phba->sli4_hba.conf_regs_memmap_p;
2fcee4bf
JS
10437 /* Set up BAR0 PCI config space register memory map */
10438 lpfc_sli4_bar0_register_memmap(phba, if_type);
1dfb5a47
JS
10439 } else {
10440 phba->pci_bar0_map = pci_resource_start(pdev, 1);
10441 bar0map_len = pci_resource_len(pdev, 1);
27d6ac0a 10442 if (if_type >= LPFC_SLI_INTF_IF_TYPE_2) {
2fcee4bf
JS
10443 dev_printk(KERN_ERR, &pdev->dev,
10444 "FATAL - No BAR0 mapping for SLI4, if_type 2\n");
3a487ff7 10445 return -ENODEV;
2fcee4bf
JS
10446 }
10447 phba->sli4_hba.conf_regs_memmap_p =
da0436e9 10448 ioremap(phba->pci_bar0_map, bar0map_len);
2fcee4bf
JS
10449 if (!phba->sli4_hba.conf_regs_memmap_p) {
10450 dev_printk(KERN_ERR, &pdev->dev,
10451 "ioremap failed for SLI4 PCI config "
10452 "registers.\n");
3a487ff7 10453 return -ENODEV;
2fcee4bf
JS
10454 }
10455 lpfc_sli4_bar0_register_memmap(phba, if_type);
da0436e9
JS
10456 }
10457
e4b9794e
JS
10458 if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
10459 if (pci_resource_start(pdev, PCI_64BIT_BAR2)) {
10460 /*
10461 * Map SLI4 if type 0 HBA Control Register base to a
10462 * kernel virtual address and setup the registers.
10463 */
10464 phba->pci_bar1_map = pci_resource_start(pdev,
10465 PCI_64BIT_BAR2);
10466 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
10467 phba->sli4_hba.ctrl_regs_memmap_p =
10468 ioremap(phba->pci_bar1_map,
10469 bar1map_len);
10470 if (!phba->sli4_hba.ctrl_regs_memmap_p) {
10471 dev_err(&pdev->dev,
10472 "ioremap failed for SLI4 HBA "
10473 "control registers.\n");
10474 error = -ENOMEM;
10475 goto out_iounmap_conf;
10476 }
10477 phba->pci_bar2_memmap_p =
10478 phba->sli4_hba.ctrl_regs_memmap_p;
27d6ac0a 10479 lpfc_sli4_bar1_register_memmap(phba, if_type);
e4b9794e
JS
10480 } else {
10481 error = -ENOMEM;
2fcee4bf
JS
10482 goto out_iounmap_conf;
10483 }
da0436e9
JS
10484 }
10485
27d6ac0a
JS
10486 if ((if_type == LPFC_SLI_INTF_IF_TYPE_6) &&
10487 (pci_resource_start(pdev, PCI_64BIT_BAR2))) {
10488 /*
10489 * Map SLI4 if type 6 HBA Doorbell Register base to a kernel
10490 * virtual address and setup the registers.
10491 */
10492 phba->pci_bar1_map = pci_resource_start(pdev, PCI_64BIT_BAR2);
10493 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
10494 phba->sli4_hba.drbl_regs_memmap_p =
10495 ioremap(phba->pci_bar1_map, bar1map_len);
10496 if (!phba->sli4_hba.drbl_regs_memmap_p) {
10497 dev_err(&pdev->dev,
10498 "ioremap failed for SLI4 HBA doorbell registers.\n");
3a487ff7 10499 error = -ENOMEM;
27d6ac0a
JS
10500 goto out_iounmap_conf;
10501 }
10502 phba->pci_bar2_memmap_p = phba->sli4_hba.drbl_regs_memmap_p;
10503 lpfc_sli4_bar1_register_memmap(phba, if_type);
10504 }
10505
e4b9794e
JS
10506 if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
10507 if (pci_resource_start(pdev, PCI_64BIT_BAR4)) {
10508 /*
10509 * Map SLI4 if type 0 HBA Doorbell Register base to
10510 * a kernel virtual address and setup the registers.
10511 */
10512 phba->pci_bar2_map = pci_resource_start(pdev,
10513 PCI_64BIT_BAR4);
10514 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
10515 phba->sli4_hba.drbl_regs_memmap_p =
10516 ioremap(phba->pci_bar2_map,
10517 bar2map_len);
10518 if (!phba->sli4_hba.drbl_regs_memmap_p) {
10519 dev_err(&pdev->dev,
10520 "ioremap failed for SLI4 HBA"
10521 " doorbell registers.\n");
10522 error = -ENOMEM;
10523 goto out_iounmap_ctrl;
10524 }
10525 phba->pci_bar4_memmap_p =
10526 phba->sli4_hba.drbl_regs_memmap_p;
10527 error = lpfc_sli4_bar2_register_memmap(phba, LPFC_VF0);
10528 if (error)
10529 goto out_iounmap_all;
10530 } else {
10531 error = -ENOMEM;
2fcee4bf 10532 goto out_iounmap_all;
e4b9794e 10533 }
da0436e9
JS
10534 }
10535
1351e69f
JS
10536 if (if_type == LPFC_SLI_INTF_IF_TYPE_6 &&
10537 pci_resource_start(pdev, PCI_64BIT_BAR4)) {
10538 /*
10539 * Map SLI4 if type 6 HBA DPP Register base to a kernel
10540 * virtual address and setup the registers.
10541 */
10542 phba->pci_bar2_map = pci_resource_start(pdev, PCI_64BIT_BAR4);
10543 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
10544 phba->sli4_hba.dpp_regs_memmap_p =
10545 ioremap(phba->pci_bar2_map, bar2map_len);
10546 if (!phba->sli4_hba.dpp_regs_memmap_p) {
10547 dev_err(&pdev->dev,
10548 "ioremap failed for SLI4 HBA dpp registers.\n");
3a487ff7 10549 error = -ENOMEM;
1351e69f
JS
10550 goto out_iounmap_ctrl;
10551 }
10552 phba->pci_bar4_memmap_p = phba->sli4_hba.dpp_regs_memmap_p;
10553 }
10554
b71413dd 10555 /* Set up the EQ/CQ register handeling functions now */
27d6ac0a
JS
10556 switch (if_type) {
10557 case LPFC_SLI_INTF_IF_TYPE_0:
10558 case LPFC_SLI_INTF_IF_TYPE_2:
b71413dd 10559 phba->sli4_hba.sli4_eq_clr_intr = lpfc_sli4_eq_clr_intr;
32517fc0
JS
10560 phba->sli4_hba.sli4_write_eq_db = lpfc_sli4_write_eq_db;
10561 phba->sli4_hba.sli4_write_cq_db = lpfc_sli4_write_cq_db;
27d6ac0a
JS
10562 break;
10563 case LPFC_SLI_INTF_IF_TYPE_6:
10564 phba->sli4_hba.sli4_eq_clr_intr = lpfc_sli4_if6_eq_clr_intr;
32517fc0
JS
10565 phba->sli4_hba.sli4_write_eq_db = lpfc_sli4_if6_write_eq_db;
10566 phba->sli4_hba.sli4_write_cq_db = lpfc_sli4_if6_write_cq_db;
27d6ac0a
JS
10567 break;
10568 default:
10569 break;
b71413dd
JS
10570 }
10571
da0436e9
JS
10572 return 0;
10573
10574out_iounmap_all:
10575 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10576out_iounmap_ctrl:
10577 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
10578out_iounmap_conf:
10579 iounmap(phba->sli4_hba.conf_regs_memmap_p);
3a487ff7 10580
da0436e9
JS
10581 return error;
10582}
10583
10584/**
10585 * lpfc_sli4_pci_mem_unset - Unset SLI4 HBA PCI memory space.
10586 * @phba: pointer to lpfc hba data structure.
10587 *
10588 * This routine is invoked to unset the PCI device memory space for device
10589 * with SLI-4 interface spec.
10590 **/
10591static void
10592lpfc_sli4_pci_mem_unset(struct lpfc_hba *phba)
10593{
2e90f4b5
JS
10594 uint32_t if_type;
10595 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
da0436e9 10596
2e90f4b5
JS
10597 switch (if_type) {
10598 case LPFC_SLI_INTF_IF_TYPE_0:
10599 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10600 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
10601 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10602 break;
10603 case LPFC_SLI_INTF_IF_TYPE_2:
10604 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10605 break;
27d6ac0a
JS
10606 case LPFC_SLI_INTF_IF_TYPE_6:
10607 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10608 iounmap(phba->sli4_hba.conf_regs_memmap_p);
0b439194
JS
10609 if (phba->sli4_hba.dpp_regs_memmap_p)
10610 iounmap(phba->sli4_hba.dpp_regs_memmap_p);
27d6ac0a 10611 break;
2e90f4b5
JS
10612 case LPFC_SLI_INTF_IF_TYPE_1:
10613 default:
10614 dev_printk(KERN_ERR, &phba->pcidev->dev,
10615 "FATAL - unsupported SLI4 interface type - %d\n",
10616 if_type);
10617 break;
10618 }
da0436e9
JS
10619}
10620
10621/**
10622 * lpfc_sli_enable_msix - Enable MSI-X interrupt mode on SLI-3 device
10623 * @phba: pointer to lpfc hba data structure.
10624 *
10625 * This routine is invoked to enable the MSI-X interrupt vectors to device
45ffac19 10626 * with SLI-3 interface specs.
da0436e9
JS
10627 *
10628 * Return codes
af901ca1 10629 * 0 - successful
da0436e9
JS
10630 * other values - error
10631 **/
10632static int
10633lpfc_sli_enable_msix(struct lpfc_hba *phba)
10634{
45ffac19 10635 int rc;
da0436e9
JS
10636 LPFC_MBOXQ_t *pmb;
10637
10638 /* Set up MSI-X multi-message vectors */
45ffac19
CH
10639 rc = pci_alloc_irq_vectors(phba->pcidev,
10640 LPFC_MSIX_VECTORS, LPFC_MSIX_VECTORS, PCI_IRQ_MSIX);
10641 if (rc < 0) {
da0436e9
JS
10642 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10643 "0420 PCI enable MSI-X failed (%d)\n", rc);
029165ac 10644 goto vec_fail_out;
da0436e9 10645 }
45ffac19 10646
da0436e9
JS
10647 /*
10648 * Assign MSI-X vectors to interrupt handlers
10649 */
10650
10651 /* vector-0 is associated to slow-path handler */
45ffac19 10652 rc = request_irq(pci_irq_vector(phba->pcidev, 0),
ed243d37 10653 &lpfc_sli_sp_intr_handler, 0,
da0436e9
JS
10654 LPFC_SP_DRIVER_HANDLER_NAME, phba);
10655 if (rc) {
10656 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10657 "0421 MSI-X slow-path request_irq failed "
10658 "(%d)\n", rc);
10659 goto msi_fail_out;
10660 }
10661
10662 /* vector-1 is associated to fast-path handler */
45ffac19 10663 rc = request_irq(pci_irq_vector(phba->pcidev, 1),
ed243d37 10664 &lpfc_sli_fp_intr_handler, 0,
da0436e9
JS
10665 LPFC_FP_DRIVER_HANDLER_NAME, phba);
10666
10667 if (rc) {
10668 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10669 "0429 MSI-X fast-path request_irq failed "
10670 "(%d)\n", rc);
10671 goto irq_fail_out;
10672 }
10673
10674 /*
10675 * Configure HBA MSI-X attention conditions to messages
10676 */
10677 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
10678
10679 if (!pmb) {
10680 rc = -ENOMEM;
372c187b 10681 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
10682 "0474 Unable to allocate memory for issuing "
10683 "MBOX_CONFIG_MSI command\n");
10684 goto mem_fail_out;
10685 }
10686 rc = lpfc_config_msi(phba, pmb);
10687 if (rc)
10688 goto mbx_fail_out;
10689 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
10690 if (rc != MBX_SUCCESS) {
10691 lpfc_printf_log(phba, KERN_WARNING, LOG_MBOX,
10692 "0351 Config MSI mailbox command failed, "
10693 "mbxCmd x%x, mbxStatus x%x\n",
10694 pmb->u.mb.mbxCommand, pmb->u.mb.mbxStatus);
10695 goto mbx_fail_out;
10696 }
10697
10698 /* Free memory allocated for mailbox command */
10699 mempool_free(pmb, phba->mbox_mem_pool);
10700 return rc;
10701
10702mbx_fail_out:
10703 /* Free memory allocated for mailbox command */
10704 mempool_free(pmb, phba->mbox_mem_pool);
10705
10706mem_fail_out:
10707 /* free the irq already requested */
45ffac19 10708 free_irq(pci_irq_vector(phba->pcidev, 1), phba);
da0436e9
JS
10709
10710irq_fail_out:
10711 /* free the irq already requested */
45ffac19 10712 free_irq(pci_irq_vector(phba->pcidev, 0), phba);
da0436e9
JS
10713
10714msi_fail_out:
10715 /* Unconfigure MSI-X capability structure */
45ffac19 10716 pci_free_irq_vectors(phba->pcidev);
029165ac
AG
10717
10718vec_fail_out:
da0436e9
JS
10719 return rc;
10720}
10721
da0436e9
JS
10722/**
10723 * lpfc_sli_enable_msi - Enable MSI interrupt mode on SLI-3 device.
10724 * @phba: pointer to lpfc hba data structure.
10725 *
10726 * This routine is invoked to enable the MSI interrupt mode to device with
10727 * SLI-3 interface spec. The kernel function pci_enable_msi() is called to
10728 * enable the MSI vector. The device driver is responsible for calling the
10729 * request_irq() to register MSI vector with a interrupt the handler, which
10730 * is done in this function.
10731 *
10732 * Return codes
af901ca1 10733 * 0 - successful
da0436e9
JS
10734 * other values - error
10735 */
10736static int
10737lpfc_sli_enable_msi(struct lpfc_hba *phba)
10738{
10739 int rc;
10740
10741 rc = pci_enable_msi(phba->pcidev);
10742 if (!rc)
10743 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10744 "0462 PCI enable MSI mode success.\n");
10745 else {
10746 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10747 "0471 PCI enable MSI mode failed (%d)\n", rc);
10748 return rc;
10749 }
10750
10751 rc = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
ed243d37 10752 0, LPFC_DRIVER_NAME, phba);
da0436e9
JS
10753 if (rc) {
10754 pci_disable_msi(phba->pcidev);
10755 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10756 "0478 MSI request_irq failed (%d)\n", rc);
10757 }
10758 return rc;
10759}
10760
da0436e9
JS
10761/**
10762 * lpfc_sli_enable_intr - Enable device interrupt to SLI-3 device.
10763 * @phba: pointer to lpfc hba data structure.
fe614acd 10764 * @cfg_mode: Interrupt configuration mode (INTx, MSI or MSI-X).
da0436e9
JS
10765 *
10766 * This routine is invoked to enable device interrupt and associate driver's
10767 * interrupt handler(s) to interrupt vector(s) to device with SLI-3 interface
10768 * spec. Depends on the interrupt mode configured to the driver, the driver
10769 * will try to fallback from the configured interrupt mode to an interrupt
10770 * mode which is supported by the platform, kernel, and device in the order
10771 * of:
10772 * MSI-X -> MSI -> IRQ.
10773 *
10774 * Return codes
af901ca1 10775 * 0 - successful
da0436e9
JS
10776 * other values - error
10777 **/
10778static uint32_t
10779lpfc_sli_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
10780{
10781 uint32_t intr_mode = LPFC_INTR_ERROR;
10782 int retval;
10783
d2f2547e
JS
10784 /* Need to issue conf_port mbox cmd before conf_msi mbox cmd */
10785 retval = lpfc_sli_config_port(phba, LPFC_SLI_REV3);
10786 if (retval)
10787 return intr_mode;
10788 phba->hba_flag &= ~HBA_NEEDS_CFG_PORT;
10789
da0436e9 10790 if (cfg_mode == 2) {
d2f2547e
JS
10791 /* Now, try to enable MSI-X interrupt mode */
10792 retval = lpfc_sli_enable_msix(phba);
da0436e9 10793 if (!retval) {
d2f2547e
JS
10794 /* Indicate initialization to MSI-X mode */
10795 phba->intr_type = MSIX;
10796 intr_mode = 2;
da0436e9
JS
10797 }
10798 }
10799
10800 /* Fallback to MSI if MSI-X initialization failed */
10801 if (cfg_mode >= 1 && phba->intr_type == NONE) {
10802 retval = lpfc_sli_enable_msi(phba);
10803 if (!retval) {
10804 /* Indicate initialization to MSI mode */
10805 phba->intr_type = MSI;
10806 intr_mode = 1;
10807 }
10808 }
10809
10810 /* Fallback to INTx if both MSI-X/MSI initalization failed */
10811 if (phba->intr_type == NONE) {
10812 retval = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
10813 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
10814 if (!retval) {
10815 /* Indicate initialization to INTx mode */
10816 phba->intr_type = INTx;
10817 intr_mode = 0;
10818 }
10819 }
10820 return intr_mode;
10821}
10822
10823/**
10824 * lpfc_sli_disable_intr - Disable device interrupt to SLI-3 device.
10825 * @phba: pointer to lpfc hba data structure.
10826 *
10827 * This routine is invoked to disable device interrupt and disassociate the
10828 * driver's interrupt handler(s) from interrupt vector(s) to device with
10829 * SLI-3 interface spec. Depending on the interrupt mode, the driver will
10830 * release the interrupt vector(s) for the message signaled interrupt.
10831 **/
10832static void
10833lpfc_sli_disable_intr(struct lpfc_hba *phba)
10834{
45ffac19
CH
10835 int nr_irqs, i;
10836
da0436e9 10837 if (phba->intr_type == MSIX)
45ffac19
CH
10838 nr_irqs = LPFC_MSIX_VECTORS;
10839 else
10840 nr_irqs = 1;
10841
10842 for (i = 0; i < nr_irqs; i++)
10843 free_irq(pci_irq_vector(phba->pcidev, i), phba);
10844 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
10845
10846 /* Reset interrupt management states */
10847 phba->intr_type = NONE;
10848 phba->sli.slistat.sli_intr = 0;
da0436e9
JS
10849}
10850
6a828b0f 10851/**
657add4e 10852 * lpfc_find_cpu_handle - Find the CPU that corresponds to the specified Queue
6a828b0f
JS
10853 * @phba: pointer to lpfc hba data structure.
10854 * @id: EQ vector index or Hardware Queue index
10855 * @match: LPFC_FIND_BY_EQ = match by EQ
10856 * LPFC_FIND_BY_HDWQ = match by Hardware Queue
657add4e 10857 * Return the CPU that matches the selection criteria
6a828b0f
JS
10858 */
10859static uint16_t
10860lpfc_find_cpu_handle(struct lpfc_hba *phba, uint16_t id, int match)
10861{
10862 struct lpfc_vector_map_info *cpup;
10863 int cpu;
10864
657add4e 10865 /* Loop through all CPUs */
222e9239
JS
10866 for_each_present_cpu(cpu) {
10867 cpup = &phba->sli4_hba.cpu_map[cpu];
657add4e
JS
10868
10869 /* If we are matching by EQ, there may be multiple CPUs using
10870 * using the same vector, so select the one with
10871 * LPFC_CPU_FIRST_IRQ set.
10872 */
6a828b0f 10873 if ((match == LPFC_FIND_BY_EQ) &&
657add4e 10874 (cpup->flag & LPFC_CPU_FIRST_IRQ) &&
6a828b0f
JS
10875 (cpup->eq == id))
10876 return cpu;
657add4e
JS
10877
10878 /* If matching by HDWQ, select the first CPU that matches */
6a828b0f
JS
10879 if ((match == LPFC_FIND_BY_HDWQ) && (cpup->hdwq == id))
10880 return cpu;
6a828b0f
JS
10881 }
10882 return 0;
10883}
10884
6a828b0f
JS
10885#ifdef CONFIG_X86
10886/**
10887 * lpfc_find_hyper - Determine if the CPU map entry is hyper-threaded
10888 * @phba: pointer to lpfc hba data structure.
10889 * @cpu: CPU map index
10890 * @phys_id: CPU package physical id
10891 * @core_id: CPU core id
10892 */
10893static int
10894lpfc_find_hyper(struct lpfc_hba *phba, int cpu,
10895 uint16_t phys_id, uint16_t core_id)
10896{
10897 struct lpfc_vector_map_info *cpup;
10898 int idx;
10899
222e9239
JS
10900 for_each_present_cpu(idx) {
10901 cpup = &phba->sli4_hba.cpu_map[idx];
6a828b0f
JS
10902 /* Does the cpup match the one we are looking for */
10903 if ((cpup->phys_id == phys_id) &&
10904 (cpup->core_id == core_id) &&
222e9239 10905 (cpu != idx))
6a828b0f 10906 return 1;
6a828b0f
JS
10907 }
10908 return 0;
10909}
10910#endif
10911
dcaa2136
JS
10912/*
10913 * lpfc_assign_eq_map_info - Assigns eq for vector_map structure
10914 * @phba: pointer to lpfc hba data structure.
10915 * @eqidx: index for eq and irq vector
10916 * @flag: flags to set for vector_map structure
10917 * @cpu: cpu used to index vector_map structure
10918 *
10919 * The routine assigns eq info into vector_map structure
10920 */
10921static inline void
10922lpfc_assign_eq_map_info(struct lpfc_hba *phba, uint16_t eqidx, uint16_t flag,
10923 unsigned int cpu)
10924{
10925 struct lpfc_vector_map_info *cpup = &phba->sli4_hba.cpu_map[cpu];
10926 struct lpfc_hba_eq_hdl *eqhdl = lpfc_get_eq_hdl(eqidx);
10927
10928 cpup->eq = eqidx;
10929 cpup->flag |= flag;
10930
10931 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10932 "3336 Set Affinity: CPU %d irq %d eq %d flag x%x\n",
10933 cpu, eqhdl->irq, cpup->eq, cpup->flag);
10934}
10935
10936/**
10937 * lpfc_cpu_map_array_init - Initialize cpu_map structure
10938 * @phba: pointer to lpfc hba data structure.
10939 *
10940 * The routine initializes the cpu_map array structure
10941 */
10942static void
10943lpfc_cpu_map_array_init(struct lpfc_hba *phba)
10944{
10945 struct lpfc_vector_map_info *cpup;
10946 struct lpfc_eq_intr_info *eqi;
10947 int cpu;
10948
10949 for_each_possible_cpu(cpu) {
10950 cpup = &phba->sli4_hba.cpu_map[cpu];
10951 cpup->phys_id = LPFC_VECTOR_MAP_EMPTY;
10952 cpup->core_id = LPFC_VECTOR_MAP_EMPTY;
10953 cpup->hdwq = LPFC_VECTOR_MAP_EMPTY;
10954 cpup->eq = LPFC_VECTOR_MAP_EMPTY;
10955 cpup->flag = 0;
10956 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, cpu);
10957 INIT_LIST_HEAD(&eqi->list);
10958 eqi->icnt = 0;
10959 }
10960}
10961
10962/**
10963 * lpfc_hba_eq_hdl_array_init - Initialize hba_eq_hdl structure
10964 * @phba: pointer to lpfc hba data structure.
10965 *
10966 * The routine initializes the hba_eq_hdl array structure
10967 */
10968static void
10969lpfc_hba_eq_hdl_array_init(struct lpfc_hba *phba)
10970{
10971 struct lpfc_hba_eq_hdl *eqhdl;
10972 int i;
10973
10974 for (i = 0; i < phba->cfg_irq_chann; i++) {
10975 eqhdl = lpfc_get_eq_hdl(i);
10976 eqhdl->irq = LPFC_VECTOR_MAP_EMPTY;
10977 eqhdl->phba = phba;
10978 }
10979}
10980
7bb03bbf 10981/**
895427bd 10982 * lpfc_cpu_affinity_check - Check vector CPU affinity mappings
7bb03bbf 10983 * @phba: pointer to lpfc hba data structure.
895427bd
JS
10984 * @vectors: number of msix vectors allocated.
10985 *
10986 * The routine will figure out the CPU affinity assignment for every
6a828b0f 10987 * MSI-X vector allocated for the HBA.
895427bd
JS
10988 * In addition, the CPU to IO channel mapping will be calculated
10989 * and the phba->sli4_hba.cpu_map array will reflect this.
7bb03bbf 10990 */
895427bd
JS
10991static void
10992lpfc_cpu_affinity_check(struct lpfc_hba *phba, int vectors)
7bb03bbf 10993{
3ad348d9 10994 int i, cpu, idx, next_idx, new_cpu, start_cpu, first_cpu;
6a828b0f
JS
10995 int max_phys_id, min_phys_id;
10996 int max_core_id, min_core_id;
7bb03bbf 10997 struct lpfc_vector_map_info *cpup;
d9954a2d 10998 struct lpfc_vector_map_info *new_cpup;
7bb03bbf
JS
10999#ifdef CONFIG_X86
11000 struct cpuinfo_x86 *cpuinfo;
11001#endif
840eda96
JS
11002#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
11003 struct lpfc_hdwq_stat *c_stat;
11004#endif
7bb03bbf 11005
6a828b0f 11006 max_phys_id = 0;
d9954a2d 11007 min_phys_id = LPFC_VECTOR_MAP_EMPTY;
6a828b0f 11008 max_core_id = 0;
d9954a2d 11009 min_core_id = LPFC_VECTOR_MAP_EMPTY;
7bb03bbf
JS
11010
11011 /* Update CPU map with physical id and core id of each CPU */
222e9239
JS
11012 for_each_present_cpu(cpu) {
11013 cpup = &phba->sli4_hba.cpu_map[cpu];
7bb03bbf
JS
11014#ifdef CONFIG_X86
11015 cpuinfo = &cpu_data(cpu);
11016 cpup->phys_id = cpuinfo->phys_proc_id;
11017 cpup->core_id = cpuinfo->cpu_core_id;
d9954a2d
JS
11018 if (lpfc_find_hyper(phba, cpu, cpup->phys_id, cpup->core_id))
11019 cpup->flag |= LPFC_CPU_MAP_HYPER;
7bb03bbf
JS
11020#else
11021 /* No distinction between CPUs for other platforms */
11022 cpup->phys_id = 0;
6a828b0f 11023 cpup->core_id = cpu;
7bb03bbf 11024#endif
6a828b0f 11025
b3295c2a 11026 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3ad348d9
JS
11027 "3328 CPU %d physid %d coreid %d flag x%x\n",
11028 cpu, cpup->phys_id, cpup->core_id, cpup->flag);
6a828b0f
JS
11029
11030 if (cpup->phys_id > max_phys_id)
11031 max_phys_id = cpup->phys_id;
11032 if (cpup->phys_id < min_phys_id)
11033 min_phys_id = cpup->phys_id;
11034
11035 if (cpup->core_id > max_core_id)
11036 max_core_id = cpup->core_id;
11037 if (cpup->core_id < min_core_id)
11038 min_core_id = cpup->core_id;
7bb03bbf 11039 }
7bb03bbf 11040
d9954a2d
JS
11041 /* After looking at each irq vector assigned to this pcidev, its
11042 * possible to see that not ALL CPUs have been accounted for.
657add4e
JS
11043 * Next we will set any unassigned (unaffinitized) cpu map
11044 * entries to a IRQ on the same phys_id.
d9954a2d
JS
11045 */
11046 first_cpu = cpumask_first(cpu_present_mask);
11047 start_cpu = first_cpu;
11048
11049 for_each_present_cpu(cpu) {
11050 cpup = &phba->sli4_hba.cpu_map[cpu];
11051
11052 /* Is this CPU entry unassigned */
11053 if (cpup->eq == LPFC_VECTOR_MAP_EMPTY) {
11054 /* Mark CPU as IRQ not assigned by the kernel */
11055 cpup->flag |= LPFC_CPU_MAP_UNASSIGN;
11056
657add4e 11057 /* If so, find a new_cpup thats on the the SAME
d9954a2d
JS
11058 * phys_id as cpup. start_cpu will start where we
11059 * left off so all unassigned entries don't get assgined
11060 * the IRQ of the first entry.
11061 */
11062 new_cpu = start_cpu;
11063 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
11064 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
11065 if (!(new_cpup->flag & LPFC_CPU_MAP_UNASSIGN) &&
dcaa2136 11066 (new_cpup->eq != LPFC_VECTOR_MAP_EMPTY) &&
d9954a2d
JS
11067 (new_cpup->phys_id == cpup->phys_id))
11068 goto found_same;
11069 new_cpu = cpumask_next(
11070 new_cpu, cpu_present_mask);
11071 if (new_cpu == nr_cpumask_bits)
11072 new_cpu = first_cpu;
11073 }
11074 /* At this point, we leave the CPU as unassigned */
11075 continue;
11076found_same:
11077 /* We found a matching phys_id, so copy the IRQ info */
11078 cpup->eq = new_cpup->eq;
d9954a2d
JS
11079
11080 /* Bump start_cpu to the next slot to minmize the
11081 * chance of having multiple unassigned CPU entries
11082 * selecting the same IRQ.
11083 */
11084 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
11085 if (start_cpu == nr_cpumask_bits)
11086 start_cpu = first_cpu;
11087
657add4e 11088 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
d9954a2d 11089 "3337 Set Affinity: CPU %d "
dcaa2136 11090 "eq %d from peer cpu %d same "
d9954a2d 11091 "phys_id (%d)\n",
dcaa2136
JS
11092 cpu, cpup->eq, new_cpu,
11093 cpup->phys_id);
d9954a2d
JS
11094 }
11095 }
11096
11097 /* Set any unassigned cpu map entries to a IRQ on any phys_id */
11098 start_cpu = first_cpu;
11099
11100 for_each_present_cpu(cpu) {
11101 cpup = &phba->sli4_hba.cpu_map[cpu];
11102
11103 /* Is this entry unassigned */
11104 if (cpup->eq == LPFC_VECTOR_MAP_EMPTY) {
11105 /* Mark it as IRQ not assigned by the kernel */
11106 cpup->flag |= LPFC_CPU_MAP_UNASSIGN;
11107
657add4e 11108 /* If so, find a new_cpup thats on ANY phys_id
d9954a2d
JS
11109 * as the cpup. start_cpu will start where we
11110 * left off so all unassigned entries don't get
11111 * assigned the IRQ of the first entry.
11112 */
11113 new_cpu = start_cpu;
11114 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
11115 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
11116 if (!(new_cpup->flag & LPFC_CPU_MAP_UNASSIGN) &&
dcaa2136 11117 (new_cpup->eq != LPFC_VECTOR_MAP_EMPTY))
d9954a2d
JS
11118 goto found_any;
11119 new_cpu = cpumask_next(
11120 new_cpu, cpu_present_mask);
11121 if (new_cpu == nr_cpumask_bits)
11122 new_cpu = first_cpu;
11123 }
11124 /* We should never leave an entry unassigned */
11125 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11126 "3339 Set Affinity: CPU %d "
dcaa2136
JS
11127 "eq %d UNASSIGNED\n",
11128 cpup->hdwq, cpup->eq);
d9954a2d
JS
11129 continue;
11130found_any:
11131 /* We found an available entry, copy the IRQ info */
11132 cpup->eq = new_cpup->eq;
d9954a2d
JS
11133
11134 /* Bump start_cpu to the next slot to minmize the
11135 * chance of having multiple unassigned CPU entries
11136 * selecting the same IRQ.
11137 */
11138 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
11139 if (start_cpu == nr_cpumask_bits)
11140 start_cpu = first_cpu;
11141
657add4e 11142 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
d9954a2d 11143 "3338 Set Affinity: CPU %d "
dcaa2136
JS
11144 "eq %d from peer cpu %d (%d/%d)\n",
11145 cpu, cpup->eq, new_cpu,
d9954a2d
JS
11146 new_cpup->phys_id, new_cpup->core_id);
11147 }
11148 }
657add4e 11149
3ad348d9
JS
11150 /* Assign hdwq indices that are unique across all cpus in the map
11151 * that are also FIRST_CPUs.
11152 */
11153 idx = 0;
11154 for_each_present_cpu(cpu) {
11155 cpup = &phba->sli4_hba.cpu_map[cpu];
11156
11157 /* Only FIRST IRQs get a hdwq index assignment. */
11158 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
11159 continue;
11160
11161 /* 1 to 1, the first LPFC_CPU_FIRST_IRQ cpus to a unique hdwq */
11162 cpup->hdwq = idx;
11163 idx++;
bc2736e9 11164 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3ad348d9 11165 "3333 Set Affinity: CPU %d (phys %d core %d): "
dcaa2136 11166 "hdwq %d eq %d flg x%x\n",
3ad348d9 11167 cpu, cpup->phys_id, cpup->core_id,
dcaa2136 11168 cpup->hdwq, cpup->eq, cpup->flag);
3ad348d9 11169 }
bc227dde 11170 /* Associate a hdwq with each cpu_map entry
657add4e
JS
11171 * This will be 1 to 1 - hdwq to cpu, unless there are less
11172 * hardware queues then CPUs. For that case we will just round-robin
11173 * the available hardware queues as they get assigned to CPUs.
3ad348d9
JS
11174 * The next_idx is the idx from the FIRST_CPU loop above to account
11175 * for irq_chann < hdwq. The idx is used for round-robin assignments
11176 * and needs to start at 0.
657add4e 11177 */
3ad348d9 11178 next_idx = idx;
657add4e 11179 start_cpu = 0;
3ad348d9 11180 idx = 0;
657add4e
JS
11181 for_each_present_cpu(cpu) {
11182 cpup = &phba->sli4_hba.cpu_map[cpu];
657add4e 11183
3ad348d9
JS
11184 /* FIRST cpus are already mapped. */
11185 if (cpup->flag & LPFC_CPU_FIRST_IRQ)
11186 continue;
11187
11188 /* If the cfg_irq_chann < cfg_hdw_queue, set the hdwq
11189 * of the unassigned cpus to the next idx so that all
11190 * hdw queues are fully utilized.
11191 */
11192 if (next_idx < phba->cfg_hdw_queue) {
11193 cpup->hdwq = next_idx;
11194 next_idx++;
11195 continue;
11196 }
11197
11198 /* Not a First CPU and all hdw_queues are used. Reuse a
11199 * Hardware Queue for another CPU, so be smart about it
11200 * and pick one that has its IRQ/EQ mapped to the same phys_id
11201 * (CPU package) and core_id.
11202 */
11203 new_cpu = start_cpu;
11204 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
11205 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
11206 if (new_cpup->hdwq != LPFC_VECTOR_MAP_EMPTY &&
11207 new_cpup->phys_id == cpup->phys_id &&
11208 new_cpup->core_id == cpup->core_id) {
11209 goto found_hdwq;
657add4e 11210 }
3ad348d9
JS
11211 new_cpu = cpumask_next(new_cpu, cpu_present_mask);
11212 if (new_cpu == nr_cpumask_bits)
11213 new_cpu = first_cpu;
11214 }
657add4e 11215
3ad348d9
JS
11216 /* If we can't match both phys_id and core_id,
11217 * settle for just a phys_id match.
11218 */
11219 new_cpu = start_cpu;
11220 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
11221 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
11222 if (new_cpup->hdwq != LPFC_VECTOR_MAP_EMPTY &&
11223 new_cpup->phys_id == cpup->phys_id)
11224 goto found_hdwq;
11225
11226 new_cpu = cpumask_next(new_cpu, cpu_present_mask);
11227 if (new_cpu == nr_cpumask_bits)
11228 new_cpu = first_cpu;
657add4e 11229 }
3ad348d9
JS
11230
11231 /* Otherwise just round robin on cfg_hdw_queue */
11232 cpup->hdwq = idx % phba->cfg_hdw_queue;
11233 idx++;
11234 goto logit;
11235 found_hdwq:
11236 /* We found an available entry, copy the IRQ info */
11237 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
11238 if (start_cpu == nr_cpumask_bits)
11239 start_cpu = first_cpu;
11240 cpup->hdwq = new_cpup->hdwq;
11241 logit:
bc2736e9 11242 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
657add4e 11243 "3335 Set Affinity: CPU %d (phys %d core %d): "
dcaa2136 11244 "hdwq %d eq %d flg x%x\n",
657add4e 11245 cpu, cpup->phys_id, cpup->core_id,
dcaa2136 11246 cpup->hdwq, cpup->eq, cpup->flag);
657add4e
JS
11247 }
11248
bc227dde
JS
11249 /*
11250 * Initialize the cpu_map slots for not-present cpus in case
11251 * a cpu is hot-added. Perform a simple hdwq round robin assignment.
11252 */
11253 idx = 0;
11254 for_each_possible_cpu(cpu) {
11255 cpup = &phba->sli4_hba.cpu_map[cpu];
840eda96
JS
11256#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
11257 c_stat = per_cpu_ptr(phba->sli4_hba.c_stat, cpu);
11258 c_stat->hdwq_no = cpup->hdwq;
11259#endif
bc227dde
JS
11260 if (cpup->hdwq != LPFC_VECTOR_MAP_EMPTY)
11261 continue;
11262
11263 cpup->hdwq = idx++ % phba->cfg_hdw_queue;
840eda96
JS
11264#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
11265 c_stat->hdwq_no = cpup->hdwq;
11266#endif
bc227dde
JS
11267 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11268 "3340 Set Affinity: not present "
11269 "CPU %d hdwq %d\n",
11270 cpu, cpup->hdwq);
657add4e
JS
11271 }
11272
11273 /* The cpu_map array will be used later during initialization
11274 * when EQ / CQ / WQs are allocated and configured.
11275 */
b3295c2a 11276 return;
7bb03bbf 11277}
7bb03bbf 11278
93a4d6f4
JS
11279/**
11280 * lpfc_cpuhp_get_eq
11281 *
11282 * @phba: pointer to lpfc hba data structure.
11283 * @cpu: cpu going offline
fe614acd 11284 * @eqlist: eq list to append to
93a4d6f4 11285 */
a99c8074 11286static int
93a4d6f4
JS
11287lpfc_cpuhp_get_eq(struct lpfc_hba *phba, unsigned int cpu,
11288 struct list_head *eqlist)
11289{
93a4d6f4
JS
11290 const struct cpumask *maskp;
11291 struct lpfc_queue *eq;
a99c8074 11292 struct cpumask *tmp;
93a4d6f4
JS
11293 u16 idx;
11294
a99c8074
JS
11295 tmp = kzalloc(cpumask_size(), GFP_KERNEL);
11296 if (!tmp)
11297 return -ENOMEM;
11298
93a4d6f4
JS
11299 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
11300 maskp = pci_irq_get_affinity(phba->pcidev, idx);
11301 if (!maskp)
11302 continue;
11303 /*
11304 * if irq is not affinitized to the cpu going
11305 * then we don't need to poll the eq attached
11306 * to it.
11307 */
a99c8074 11308 if (!cpumask_and(tmp, maskp, cpumask_of(cpu)))
93a4d6f4
JS
11309 continue;
11310 /* get the cpus that are online and are affini-
11311 * tized to this irq vector. If the count is
11312 * more than 1 then cpuhp is not going to shut-
11313 * down this vector. Since this cpu has not
11314 * gone offline yet, we need >1.
11315 */
a99c8074
JS
11316 cpumask_and(tmp, maskp, cpu_online_mask);
11317 if (cpumask_weight(tmp) > 1)
93a4d6f4
JS
11318 continue;
11319
11320 /* Now that we have an irq to shutdown, get the eq
11321 * mapped to this irq. Note: multiple hdwq's in
11322 * the software can share an eq, but eventually
11323 * only eq will be mapped to this vector
11324 */
dcaa2136
JS
11325 eq = phba->sli4_hba.hba_eq_hdl[idx].eq;
11326 list_add(&eq->_poll_list, eqlist);
93a4d6f4 11327 }
a99c8074
JS
11328 kfree(tmp);
11329 return 0;
93a4d6f4
JS
11330}
11331
11332static void __lpfc_cpuhp_remove(struct lpfc_hba *phba)
11333{
11334 if (phba->sli_rev != LPFC_SLI_REV4)
11335 return;
11336
11337 cpuhp_state_remove_instance_nocalls(lpfc_cpuhp_state,
11338 &phba->cpuhp);
11339 /*
11340 * unregistering the instance doesn't stop the polling
11341 * timer. Wait for the poll timer to retire.
11342 */
11343 synchronize_rcu();
11344 del_timer_sync(&phba->cpuhp_poll_timer);
11345}
11346
11347static void lpfc_cpuhp_remove(struct lpfc_hba *phba)
11348{
11349 if (phba->pport->fc_flag & FC_OFFLINE_MODE)
11350 return;
11351
11352 __lpfc_cpuhp_remove(phba);
11353}
11354
11355static void lpfc_cpuhp_add(struct lpfc_hba *phba)
11356{
11357 if (phba->sli_rev != LPFC_SLI_REV4)
11358 return;
11359
11360 rcu_read_lock();
11361
f861f596 11362 if (!list_empty(&phba->poll_list))
93a4d6f4
JS
11363 mod_timer(&phba->cpuhp_poll_timer,
11364 jiffies + msecs_to_jiffies(LPFC_POLL_HB));
93a4d6f4
JS
11365
11366 rcu_read_unlock();
11367
11368 cpuhp_state_add_instance_nocalls(lpfc_cpuhp_state,
11369 &phba->cpuhp);
11370}
11371
11372static int __lpfc_cpuhp_checks(struct lpfc_hba *phba, int *retval)
11373{
11374 if (phba->pport->load_flag & FC_UNLOADING) {
11375 *retval = -EAGAIN;
11376 return true;
11377 }
11378
11379 if (phba->sli_rev != LPFC_SLI_REV4) {
11380 *retval = 0;
11381 return true;
11382 }
11383
11384 /* proceed with the hotplug */
11385 return false;
11386}
11387
dcaa2136
JS
11388/**
11389 * lpfc_irq_set_aff - set IRQ affinity
11390 * @eqhdl: EQ handle
11391 * @cpu: cpu to set affinity
11392 *
11393 **/
11394static inline void
11395lpfc_irq_set_aff(struct lpfc_hba_eq_hdl *eqhdl, unsigned int cpu)
11396{
11397 cpumask_clear(&eqhdl->aff_mask);
11398 cpumask_set_cpu(cpu, &eqhdl->aff_mask);
11399 irq_set_status_flags(eqhdl->irq, IRQ_NO_BALANCING);
11400 irq_set_affinity_hint(eqhdl->irq, &eqhdl->aff_mask);
11401}
11402
11403/**
11404 * lpfc_irq_clear_aff - clear IRQ affinity
11405 * @eqhdl: EQ handle
11406 *
11407 **/
11408static inline void
11409lpfc_irq_clear_aff(struct lpfc_hba_eq_hdl *eqhdl)
11410{
11411 cpumask_clear(&eqhdl->aff_mask);
11412 irq_clear_status_flags(eqhdl->irq, IRQ_NO_BALANCING);
dcaa2136
JS
11413}
11414
11415/**
11416 * lpfc_irq_rebalance - rebalances IRQ affinity according to cpuhp event
11417 * @phba: pointer to HBA context object.
11418 * @cpu: cpu going offline/online
11419 * @offline: true, cpu is going offline. false, cpu is coming online.
11420 *
11421 * If cpu is going offline, we'll try our best effort to find the next
3048e3e8
DK
11422 * online cpu on the phba's original_mask and migrate all offlining IRQ
11423 * affinities.
dcaa2136 11424 *
3048e3e8 11425 * If cpu is coming online, reaffinitize the IRQ back to the onlining cpu.
dcaa2136 11426 *
3048e3e8 11427 * Note: Call only if NUMA or NHT mode is enabled, otherwise rely on
dcaa2136
JS
11428 * PCI_IRQ_AFFINITY to auto-manage IRQ affinity.
11429 *
11430 **/
11431static void
11432lpfc_irq_rebalance(struct lpfc_hba *phba, unsigned int cpu, bool offline)
11433{
11434 struct lpfc_vector_map_info *cpup;
11435 struct cpumask *aff_mask;
11436 unsigned int cpu_select, cpu_next, idx;
3048e3e8 11437 const struct cpumask *orig_mask;
dcaa2136 11438
3048e3e8 11439 if (phba->irq_chann_mode == NORMAL_MODE)
dcaa2136
JS
11440 return;
11441
3048e3e8 11442 orig_mask = &phba->sli4_hba.irq_aff_mask;
dcaa2136 11443
3048e3e8 11444 if (!cpumask_test_cpu(cpu, orig_mask))
dcaa2136
JS
11445 return;
11446
11447 cpup = &phba->sli4_hba.cpu_map[cpu];
11448
11449 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
11450 return;
11451
11452 if (offline) {
3048e3e8
DK
11453 /* Find next online CPU on original mask */
11454 cpu_next = cpumask_next_wrap(cpu, orig_mask, cpu, true);
11455 cpu_select = lpfc_next_online_cpu(orig_mask, cpu_next);
dcaa2136
JS
11456
11457 /* Found a valid CPU */
11458 if ((cpu_select < nr_cpu_ids) && (cpu_select != cpu)) {
11459 /* Go through each eqhdl and ensure offlining
11460 * cpu aff_mask is migrated
11461 */
11462 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
11463 aff_mask = lpfc_get_aff_mask(idx);
11464
11465 /* Migrate affinity */
11466 if (cpumask_test_cpu(cpu, aff_mask))
11467 lpfc_irq_set_aff(lpfc_get_eq_hdl(idx),
11468 cpu_select);
11469 }
11470 } else {
11471 /* Rely on irqbalance if no online CPUs left on NUMA */
11472 for (idx = 0; idx < phba->cfg_irq_chann; idx++)
11473 lpfc_irq_clear_aff(lpfc_get_eq_hdl(idx));
11474 }
11475 } else {
11476 /* Migrate affinity back to this CPU */
11477 lpfc_irq_set_aff(lpfc_get_eq_hdl(cpup->eq), cpu);
11478 }
11479}
11480
93a4d6f4
JS
11481static int lpfc_cpu_offline(unsigned int cpu, struct hlist_node *node)
11482{
11483 struct lpfc_hba *phba = hlist_entry_safe(node, struct lpfc_hba, cpuhp);
11484 struct lpfc_queue *eq, *next;
11485 LIST_HEAD(eqlist);
11486 int retval;
11487
11488 if (!phba) {
11489 WARN_ONCE(!phba, "cpu: %u. phba:NULL", raw_smp_processor_id());
11490 return 0;
11491 }
11492
11493 if (__lpfc_cpuhp_checks(phba, &retval))
11494 return retval;
11495
dcaa2136
JS
11496 lpfc_irq_rebalance(phba, cpu, true);
11497
a99c8074
JS
11498 retval = lpfc_cpuhp_get_eq(phba, cpu, &eqlist);
11499 if (retval)
11500 return retval;
93a4d6f4
JS
11501
11502 /* start polling on these eq's */
11503 list_for_each_entry_safe(eq, next, &eqlist, _poll_list) {
11504 list_del_init(&eq->_poll_list);
11505 lpfc_sli4_start_polling(eq);
11506 }
11507
11508 return 0;
11509}
11510
11511static int lpfc_cpu_online(unsigned int cpu, struct hlist_node *node)
11512{
11513 struct lpfc_hba *phba = hlist_entry_safe(node, struct lpfc_hba, cpuhp);
11514 struct lpfc_queue *eq, *next;
11515 unsigned int n;
11516 int retval;
11517
11518 if (!phba) {
11519 WARN_ONCE(!phba, "cpu: %u. phba:NULL", raw_smp_processor_id());
11520 return 0;
11521 }
11522
11523 if (__lpfc_cpuhp_checks(phba, &retval))
11524 return retval;
11525
dcaa2136
JS
11526 lpfc_irq_rebalance(phba, cpu, false);
11527
93a4d6f4
JS
11528 list_for_each_entry_safe(eq, next, &phba->poll_list, _poll_list) {
11529 n = lpfc_find_cpu_handle(phba, eq->hdwq, LPFC_FIND_BY_HDWQ);
11530 if (n == cpu)
11531 lpfc_sli4_stop_polling(eq);
11532 }
11533
11534 return 0;
11535}
11536
da0436e9
JS
11537/**
11538 * lpfc_sli4_enable_msix - Enable MSI-X interrupt mode to SLI-4 device
11539 * @phba: pointer to lpfc hba data structure.
11540 *
11541 * This routine is invoked to enable the MSI-X interrupt vectors to device
dcaa2136
JS
11542 * with SLI-4 interface spec. It also allocates MSI-X vectors and maps them
11543 * to cpus on the system.
11544 *
11545 * When cfg_irq_numa is enabled, the adapter will only allocate vectors for
11546 * the number of cpus on the same numa node as this adapter. The vectors are
11547 * allocated without requesting OS affinity mapping. A vector will be
11548 * allocated and assigned to each online and offline cpu. If the cpu is
11549 * online, then affinity will be set to that cpu. If the cpu is offline, then
11550 * affinity will be set to the nearest peer cpu within the numa node that is
11551 * online. If there are no online cpus within the numa node, affinity is not
11552 * assigned and the OS may do as it pleases. Note: cpu vector affinity mapping
11553 * is consistent with the way cpu online/offline is handled when cfg_irq_numa is
11554 * configured.
11555 *
11556 * If numa mode is not enabled and there is more than 1 vector allocated, then
11557 * the driver relies on the managed irq interface where the OS assigns vector to
11558 * cpu affinity. The driver will then use that affinity mapping to setup its
11559 * cpu mapping table.
da0436e9
JS
11560 *
11561 * Return codes
af901ca1 11562 * 0 - successful
da0436e9
JS
11563 * other values - error
11564 **/
11565static int
11566lpfc_sli4_enable_msix(struct lpfc_hba *phba)
11567{
75baf696 11568 int vectors, rc, index;
b83d005e 11569 char *name;
3048e3e8 11570 const struct cpumask *aff_mask = NULL;
dcaa2136 11571 unsigned int cpu = 0, cpu_cnt = 0, cpu_select = nr_cpu_ids;
17105d95 11572 struct lpfc_vector_map_info *cpup;
dcaa2136
JS
11573 struct lpfc_hba_eq_hdl *eqhdl;
11574 const struct cpumask *maskp;
dcaa2136 11575 unsigned int flags = PCI_IRQ_MSIX;
da0436e9
JS
11576
11577 /* Set up MSI-X multi-message vectors */
6a828b0f 11578 vectors = phba->cfg_irq_chann;
45ffac19 11579
3048e3e8
DK
11580 if (phba->irq_chann_mode != NORMAL_MODE)
11581 aff_mask = &phba->sli4_hba.irq_aff_mask;
11582
11583 if (aff_mask) {
11584 cpu_cnt = cpumask_weight(aff_mask);
dcaa2136
JS
11585 vectors = min(phba->cfg_irq_chann, cpu_cnt);
11586
3048e3e8
DK
11587 /* cpu: iterates over aff_mask including offline or online
11588 * cpu_select: iterates over online aff_mask to set affinity
dcaa2136 11589 */
3048e3e8
DK
11590 cpu = cpumask_first(aff_mask);
11591 cpu_select = lpfc_next_online_cpu(aff_mask, cpu);
dcaa2136
JS
11592 } else {
11593 flags |= PCI_IRQ_AFFINITY;
11594 }
11595
11596 rc = pci_alloc_irq_vectors(phba->pcidev, 1, vectors, flags);
4f871e1b 11597 if (rc < 0) {
da0436e9
JS
11598 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11599 "0484 PCI enable MSI-X failed (%d)\n", rc);
029165ac 11600 goto vec_fail_out;
da0436e9 11601 }
4f871e1b 11602 vectors = rc;
75baf696 11603
7bb03bbf 11604 /* Assign MSI-X vectors to interrupt handlers */
67d12733 11605 for (index = 0; index < vectors; index++) {
dcaa2136
JS
11606 eqhdl = lpfc_get_eq_hdl(index);
11607 name = eqhdl->handler_name;
b83d005e
JS
11608 memset(name, 0, LPFC_SLI4_HANDLER_NAME_SZ);
11609 snprintf(name, LPFC_SLI4_HANDLER_NAME_SZ,
4305f183 11610 LPFC_DRIVER_HANDLER_NAME"%d", index);
da0436e9 11611
dcaa2136 11612 eqhdl->idx = index;
7370d10a
JS
11613 rc = request_irq(pci_irq_vector(phba->pcidev, index),
11614 &lpfc_sli4_hba_intr_handler, 0,
dcaa2136 11615 name, eqhdl);
da0436e9
JS
11616 if (rc) {
11617 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
11618 "0486 MSI-X fast-path (%d) "
11619 "request_irq failed (%d)\n", index, rc);
11620 goto cfg_fail_out;
11621 }
dcaa2136
JS
11622
11623 eqhdl->irq = pci_irq_vector(phba->pcidev, index);
11624
3048e3e8 11625 if (aff_mask) {
dcaa2136
JS
11626 /* If found a neighboring online cpu, set affinity */
11627 if (cpu_select < nr_cpu_ids)
11628 lpfc_irq_set_aff(eqhdl, cpu_select);
11629
11630 /* Assign EQ to cpu_map */
11631 lpfc_assign_eq_map_info(phba, index,
11632 LPFC_CPU_FIRST_IRQ,
11633 cpu);
11634
3048e3e8
DK
11635 /* Iterate to next offline or online cpu in aff_mask */
11636 cpu = cpumask_next(cpu, aff_mask);
dcaa2136 11637
3048e3e8
DK
11638 /* Find next online cpu in aff_mask to set affinity */
11639 cpu_select = lpfc_next_online_cpu(aff_mask, cpu);
dcaa2136
JS
11640 } else if (vectors == 1) {
11641 cpu = cpumask_first(cpu_present_mask);
11642 lpfc_assign_eq_map_info(phba, index, LPFC_CPU_FIRST_IRQ,
11643 cpu);
11644 } else {
11645 maskp = pci_irq_get_affinity(phba->pcidev, index);
11646
dcaa2136
JS
11647 /* Loop through all CPUs associated with vector index */
11648 for_each_cpu_and(cpu, maskp, cpu_present_mask) {
17105d95
DK
11649 cpup = &phba->sli4_hba.cpu_map[cpu];
11650
dcaa2136
JS
11651 /* If this is the first CPU thats assigned to
11652 * this vector, set LPFC_CPU_FIRST_IRQ.
17105d95
DK
11653 *
11654 * With certain platforms its possible that irq
11655 * vectors are affinitized to all the cpu's.
11656 * This can result in each cpu_map.eq to be set
11657 * to the last vector, resulting in overwrite
11658 * of all the previous cpu_map.eq. Ensure that
11659 * each vector receives a place in cpu_map.
11660 * Later call to lpfc_cpu_affinity_check will
11661 * ensure we are nicely balanced out.
dcaa2136 11662 */
17105d95
DK
11663 if (cpup->eq != LPFC_VECTOR_MAP_EMPTY)
11664 continue;
dcaa2136 11665 lpfc_assign_eq_map_info(phba, index,
17105d95 11666 LPFC_CPU_FIRST_IRQ,
dcaa2136 11667 cpu);
17105d95 11668 break;
dcaa2136
JS
11669 }
11670 }
da0436e9
JS
11671 }
11672
6a828b0f 11673 if (vectors != phba->cfg_irq_chann) {
372c187b 11674 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
82c3e9ba
JS
11675 "3238 Reducing IO channels to match number of "
11676 "MSI-X vectors, requested %d got %d\n",
6a828b0f
JS
11677 phba->cfg_irq_chann, vectors);
11678 if (phba->cfg_irq_chann > vectors)
11679 phba->cfg_irq_chann = vectors;
82c3e9ba 11680 }
7bb03bbf 11681
da0436e9
JS
11682 return rc;
11683
11684cfg_fail_out:
11685 /* free the irq already requested */
dcaa2136
JS
11686 for (--index; index >= 0; index--) {
11687 eqhdl = lpfc_get_eq_hdl(index);
11688 lpfc_irq_clear_aff(eqhdl);
11689 irq_set_affinity_hint(eqhdl->irq, NULL);
11690 free_irq(eqhdl->irq, eqhdl);
11691 }
da0436e9 11692
da0436e9 11693 /* Unconfigure MSI-X capability structure */
45ffac19 11694 pci_free_irq_vectors(phba->pcidev);
029165ac
AG
11695
11696vec_fail_out:
da0436e9
JS
11697 return rc;
11698}
11699
da0436e9
JS
11700/**
11701 * lpfc_sli4_enable_msi - Enable MSI interrupt mode to SLI-4 device
11702 * @phba: pointer to lpfc hba data structure.
11703 *
11704 * This routine is invoked to enable the MSI interrupt mode to device with
07b1b914
JS
11705 * SLI-4 interface spec. The kernel function pci_alloc_irq_vectors() is
11706 * called to enable the MSI vector. The device driver is responsible for
11707 * calling the request_irq() to register MSI vector with a interrupt the
11708 * handler, which is done in this function.
da0436e9
JS
11709 *
11710 * Return codes
af901ca1 11711 * 0 - successful
da0436e9
JS
11712 * other values - error
11713 **/
11714static int
11715lpfc_sli4_enable_msi(struct lpfc_hba *phba)
11716{
11717 int rc, index;
dcaa2136
JS
11718 unsigned int cpu;
11719 struct lpfc_hba_eq_hdl *eqhdl;
da0436e9 11720
07b1b914
JS
11721 rc = pci_alloc_irq_vectors(phba->pcidev, 1, 1,
11722 PCI_IRQ_MSI | PCI_IRQ_AFFINITY);
11723 if (rc > 0)
da0436e9
JS
11724 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11725 "0487 PCI enable MSI mode success.\n");
11726 else {
11727 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11728 "0488 PCI enable MSI mode failed (%d)\n", rc);
07b1b914 11729 return rc ? rc : -1;
da0436e9
JS
11730 }
11731
11732 rc = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
ed243d37 11733 0, LPFC_DRIVER_NAME, phba);
da0436e9 11734 if (rc) {
07b1b914 11735 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
11736 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
11737 "0490 MSI request_irq failed (%d)\n", rc);
75baf696 11738 return rc;
da0436e9
JS
11739 }
11740
dcaa2136
JS
11741 eqhdl = lpfc_get_eq_hdl(0);
11742 eqhdl->irq = pci_irq_vector(phba->pcidev, 0);
11743
11744 cpu = cpumask_first(cpu_present_mask);
11745 lpfc_assign_eq_map_info(phba, 0, LPFC_CPU_FIRST_IRQ, cpu);
11746
6a828b0f 11747 for (index = 0; index < phba->cfg_irq_chann; index++) {
dcaa2136
JS
11748 eqhdl = lpfc_get_eq_hdl(index);
11749 eqhdl->idx = index;
da0436e9
JS
11750 }
11751
75baf696 11752 return 0;
da0436e9
JS
11753}
11754
da0436e9
JS
11755/**
11756 * lpfc_sli4_enable_intr - Enable device interrupt to SLI-4 device
11757 * @phba: pointer to lpfc hba data structure.
fe614acd 11758 * @cfg_mode: Interrupt configuration mode (INTx, MSI or MSI-X).
da0436e9
JS
11759 *
11760 * This routine is invoked to enable device interrupt and associate driver's
11761 * interrupt handler(s) to interrupt vector(s) to device with SLI-4
11762 * interface spec. Depends on the interrupt mode configured to the driver,
11763 * the driver will try to fallback from the configured interrupt mode to an
11764 * interrupt mode which is supported by the platform, kernel, and device in
11765 * the order of:
11766 * MSI-X -> MSI -> IRQ.
11767 *
11768 * Return codes
af901ca1 11769 * 0 - successful
da0436e9
JS
11770 * other values - error
11771 **/
11772static uint32_t
11773lpfc_sli4_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
11774{
11775 uint32_t intr_mode = LPFC_INTR_ERROR;
895427bd 11776 int retval, idx;
da0436e9
JS
11777
11778 if (cfg_mode == 2) {
11779 /* Preparation before conf_msi mbox cmd */
11780 retval = 0;
11781 if (!retval) {
11782 /* Now, try to enable MSI-X interrupt mode */
11783 retval = lpfc_sli4_enable_msix(phba);
11784 if (!retval) {
11785 /* Indicate initialization to MSI-X mode */
11786 phba->intr_type = MSIX;
11787 intr_mode = 2;
11788 }
11789 }
11790 }
11791
11792 /* Fallback to MSI if MSI-X initialization failed */
11793 if (cfg_mode >= 1 && phba->intr_type == NONE) {
11794 retval = lpfc_sli4_enable_msi(phba);
11795 if (!retval) {
11796 /* Indicate initialization to MSI mode */
11797 phba->intr_type = MSI;
11798 intr_mode = 1;
11799 }
11800 }
11801
11802 /* Fallback to INTx if both MSI-X/MSI initalization failed */
11803 if (phba->intr_type == NONE) {
11804 retval = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
11805 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
11806 if (!retval) {
895427bd 11807 struct lpfc_hba_eq_hdl *eqhdl;
dcaa2136 11808 unsigned int cpu;
895427bd 11809
da0436e9
JS
11810 /* Indicate initialization to INTx mode */
11811 phba->intr_type = INTx;
11812 intr_mode = 0;
895427bd 11813
dcaa2136
JS
11814 eqhdl = lpfc_get_eq_hdl(0);
11815 eqhdl->irq = pci_irq_vector(phba->pcidev, 0);
11816
11817 cpu = cpumask_first(cpu_present_mask);
11818 lpfc_assign_eq_map_info(phba, 0, LPFC_CPU_FIRST_IRQ,
11819 cpu);
6a828b0f 11820 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
dcaa2136 11821 eqhdl = lpfc_get_eq_hdl(idx);
895427bd 11822 eqhdl->idx = idx;
1ba981fd 11823 }
da0436e9
JS
11824 }
11825 }
11826 return intr_mode;
11827}
11828
11829/**
11830 * lpfc_sli4_disable_intr - Disable device interrupt to SLI-4 device
11831 * @phba: pointer to lpfc hba data structure.
11832 *
11833 * This routine is invoked to disable device interrupt and disassociate
11834 * the driver's interrupt handler(s) from interrupt vector(s) to device
11835 * with SLI-4 interface spec. Depending on the interrupt mode, the driver
11836 * will release the interrupt vector(s) for the message signaled interrupt.
11837 **/
11838static void
11839lpfc_sli4_disable_intr(struct lpfc_hba *phba)
11840{
11841 /* Disable the currently initialized interrupt mode */
45ffac19
CH
11842 if (phba->intr_type == MSIX) {
11843 int index;
dcaa2136 11844 struct lpfc_hba_eq_hdl *eqhdl;
45ffac19
CH
11845
11846 /* Free up MSI-X multi-message vectors */
6a828b0f 11847 for (index = 0; index < phba->cfg_irq_chann; index++) {
dcaa2136
JS
11848 eqhdl = lpfc_get_eq_hdl(index);
11849 lpfc_irq_clear_aff(eqhdl);
11850 irq_set_affinity_hint(eqhdl->irq, NULL);
11851 free_irq(eqhdl->irq, eqhdl);
b3295c2a 11852 }
45ffac19 11853 } else {
da0436e9 11854 free_irq(phba->pcidev->irq, phba);
45ffac19
CH
11855 }
11856
11857 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
11858
11859 /* Reset interrupt management states */
11860 phba->intr_type = NONE;
11861 phba->sli.slistat.sli_intr = 0;
da0436e9
JS
11862}
11863
11864/**
11865 * lpfc_unset_hba - Unset SLI3 hba device initialization
11866 * @phba: pointer to lpfc hba data structure.
11867 *
11868 * This routine is invoked to unset the HBA device initialization steps to
11869 * a device with SLI-3 interface spec.
11870 **/
11871static void
11872lpfc_unset_hba(struct lpfc_hba *phba)
11873{
11874 struct lpfc_vport *vport = phba->pport;
11875 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
11876
11877 spin_lock_irq(shost->host_lock);
11878 vport->load_flag |= FC_UNLOADING;
11879 spin_unlock_irq(shost->host_lock);
11880
72859909
JS
11881 kfree(phba->vpi_bmask);
11882 kfree(phba->vpi_ids);
11883
da0436e9
JS
11884 lpfc_stop_hba_timers(phba);
11885
11886 phba->pport->work_port_events = 0;
11887
11888 lpfc_sli_hba_down(phba);
11889
11890 lpfc_sli_brdrestart(phba);
11891
11892 lpfc_sli_disable_intr(phba);
11893
11894 return;
11895}
11896
5af5eee7
JS
11897/**
11898 * lpfc_sli4_xri_exchange_busy_wait - Wait for device XRI exchange busy
11899 * @phba: Pointer to HBA context object.
11900 *
11901 * This function is called in the SLI4 code path to wait for completion
11902 * of device's XRIs exchange busy. It will check the XRI exchange busy
11903 * on outstanding FCP and ELS I/Os every 10ms for up to 10 seconds; after
11904 * that, it will check the XRI exchange busy on outstanding FCP and ELS
11905 * I/Os every 30 seconds, log error message, and wait forever. Only when
11906 * all XRI exchange busy complete, the driver unload shall proceed with
11907 * invoking the function reset ioctl mailbox command to the CNA and the
11908 * the rest of the driver unload resource release.
11909 **/
11910static void
11911lpfc_sli4_xri_exchange_busy_wait(struct lpfc_hba *phba)
11912{
5e5b511d 11913 struct lpfc_sli4_hdw_queue *qp;
c00f62e6 11914 int idx, ccnt;
5af5eee7 11915 int wait_time = 0;
5e5b511d 11916 int io_xri_cmpl = 1;
86c67379 11917 int nvmet_xri_cmpl = 1;
5af5eee7
JS
11918 int els_xri_cmpl = list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
11919
c3725bdc
JS
11920 /* Driver just aborted IOs during the hba_unset process. Pause
11921 * here to give the HBA time to complete the IO and get entries
11922 * into the abts lists.
11923 */
11924 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1 * 5);
11925
11926 /* Wait for NVME pending IO to flush back to transport. */
11927 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
11928 lpfc_nvme_wait_for_io_drain(phba);
11929
5e5b511d 11930 ccnt = 0;
5e5b511d
JS
11931 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
11932 qp = &phba->sli4_hba.hdwq[idx];
c00f62e6
JS
11933 io_xri_cmpl = list_empty(&qp->lpfc_abts_io_buf_list);
11934 if (!io_xri_cmpl) /* if list is NOT empty */
11935 ccnt++;
5e5b511d
JS
11936 }
11937 if (ccnt)
11938 io_xri_cmpl = 0;
5e5b511d 11939
86c67379 11940 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
86c67379
JS
11941 nvmet_xri_cmpl =
11942 list_empty(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
11943 }
895427bd 11944
c00f62e6 11945 while (!els_xri_cmpl || !io_xri_cmpl || !nvmet_xri_cmpl) {
5af5eee7 11946 if (wait_time > LPFC_XRI_EXCH_BUSY_WAIT_TMO) {
68c9b55d 11947 if (!nvmet_xri_cmpl)
372c187b 11948 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
68c9b55d
JS
11949 "6424 NVMET XRI exchange busy "
11950 "wait time: %d seconds.\n",
11951 wait_time/1000);
5e5b511d 11952 if (!io_xri_cmpl)
372c187b 11953 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
c00f62e6 11954 "6100 IO XRI exchange busy "
5af5eee7
JS
11955 "wait time: %d seconds.\n",
11956 wait_time/1000);
11957 if (!els_xri_cmpl)
372c187b 11958 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5af5eee7
JS
11959 "2878 ELS XRI exchange busy "
11960 "wait time: %d seconds.\n",
11961 wait_time/1000);
11962 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T2);
11963 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T2;
11964 } else {
11965 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1);
11966 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T1;
11967 }
5e5b511d
JS
11968
11969 ccnt = 0;
5e5b511d
JS
11970 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
11971 qp = &phba->sli4_hba.hdwq[idx];
c00f62e6
JS
11972 io_xri_cmpl = list_empty(
11973 &qp->lpfc_abts_io_buf_list);
11974 if (!io_xri_cmpl) /* if list is NOT empty */
11975 ccnt++;
5e5b511d
JS
11976 }
11977 if (ccnt)
11978 io_xri_cmpl = 0;
5e5b511d 11979
86c67379 11980 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
86c67379
JS
11981 nvmet_xri_cmpl = list_empty(
11982 &phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
11983 }
5af5eee7
JS
11984 els_xri_cmpl =
11985 list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
f358dd0c 11986
5af5eee7
JS
11987 }
11988}
11989
da0436e9
JS
11990/**
11991 * lpfc_sli4_hba_unset - Unset the fcoe hba
11992 * @phba: Pointer to HBA context object.
11993 *
11994 * This function is called in the SLI4 code path to reset the HBA's FCoE
11995 * function. The caller is not required to hold any lock. This routine
11996 * issues PCI function reset mailbox command to reset the FCoE function.
11997 * At the end of the function, it calls lpfc_hba_down_post function to
11998 * free any pending commands.
11999 **/
12000static void
12001lpfc_sli4_hba_unset(struct lpfc_hba *phba)
12002{
12003 int wait_cnt = 0;
12004 LPFC_MBOXQ_t *mboxq;
912e3acd 12005 struct pci_dev *pdev = phba->pcidev;
da0436e9
JS
12006
12007 lpfc_stop_hba_timers(phba);
cdb42bec
JS
12008 if (phba->pport)
12009 phba->sli4_hba.intr_enable = 0;
da0436e9
JS
12010
12011 /*
12012 * Gracefully wait out the potential current outstanding asynchronous
12013 * mailbox command.
12014 */
12015
12016 /* First, block any pending async mailbox command from posted */
12017 spin_lock_irq(&phba->hbalock);
12018 phba->sli.sli_flag |= LPFC_SLI_ASYNC_MBX_BLK;
12019 spin_unlock_irq(&phba->hbalock);
12020 /* Now, trying to wait it out if we can */
12021 while (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
12022 msleep(10);
12023 if (++wait_cnt > LPFC_ACTIVE_MBOX_WAIT_CNT)
12024 break;
12025 }
12026 /* Forcefully release the outstanding mailbox command if timed out */
12027 if (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
12028 spin_lock_irq(&phba->hbalock);
12029 mboxq = phba->sli.mbox_active;
12030 mboxq->u.mb.mbxStatus = MBX_NOT_FINISHED;
12031 __lpfc_mbox_cmpl_put(phba, mboxq);
12032 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
12033 phba->sli.mbox_active = NULL;
12034 spin_unlock_irq(&phba->hbalock);
12035 }
12036
5af5eee7
JS
12037 /* Abort all iocbs associated with the hba */
12038 lpfc_sli_hba_iocb_abort(phba);
12039
12040 /* Wait for completion of device XRI exchange busy */
12041 lpfc_sli4_xri_exchange_busy_wait(phba);
12042
93a4d6f4 12043 /* per-phba callback de-registration for hotplug event */
46da547e
SP
12044 if (phba->pport)
12045 lpfc_cpuhp_remove(phba);
93a4d6f4 12046
da0436e9
JS
12047 /* Disable PCI subsystem interrupt */
12048 lpfc_sli4_disable_intr(phba);
12049
912e3acd
JS
12050 /* Disable SR-IOV if enabled */
12051 if (phba->cfg_sriov_nr_virtfn)
12052 pci_disable_sriov(pdev);
12053
da0436e9
JS
12054 /* Stop kthread signal shall trigger work_done one more time */
12055 kthread_stop(phba->worker_thread);
12056
d2cc9bcd 12057 /* Disable FW logging to host memory */
1165a5c2 12058 lpfc_ras_stop_fwlog(phba);
d2cc9bcd 12059
d1f525aa
JS
12060 /* Unset the queues shared with the hardware then release all
12061 * allocated resources.
12062 */
12063 lpfc_sli4_queue_unset(phba);
12064 lpfc_sli4_queue_destroy(phba);
12065
3677a3a7
JS
12066 /* Reset SLI4 HBA FCoE function */
12067 lpfc_pci_function_reset(phba);
12068
1165a5c2
JS
12069 /* Free RAS DMA memory */
12070 if (phba->ras_fwlog.ras_enabled)
12071 lpfc_sli4_ras_dma_free(phba);
12072
da0436e9 12073 /* Stop the SLI4 device port */
1ffdd2c0
JS
12074 if (phba->pport)
12075 phba->pport->work_port_events = 0;
da0436e9
JS
12076}
12077
28baac74
JS
12078 /**
12079 * lpfc_pc_sli4_params_get - Get the SLI4_PARAMS port capabilities.
12080 * @phba: Pointer to HBA context object.
12081 * @mboxq: Pointer to the mailboxq memory for the mailbox command response.
12082 *
12083 * This function is called in the SLI4 code path to read the port's
12084 * sli4 capabilities.
12085 *
12086 * This function may be be called from any context that can block-wait
12087 * for the completion. The expectation is that this routine is called
12088 * typically from probe_one or from the online routine.
12089 **/
12090int
12091lpfc_pc_sli4_params_get(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
12092{
12093 int rc;
12094 struct lpfc_mqe *mqe;
12095 struct lpfc_pc_sli4_params *sli4_params;
12096 uint32_t mbox_tmo;
12097
12098 rc = 0;
12099 mqe = &mboxq->u.mqe;
12100
12101 /* Read the port's SLI4 Parameters port capabilities */
fedd3b7b 12102 lpfc_pc_sli4_params(mboxq);
28baac74
JS
12103 if (!phba->sli4_hba.intr_enable)
12104 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
12105 else {
a183a15f 12106 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
28baac74
JS
12107 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
12108 }
12109
12110 if (unlikely(rc))
12111 return 1;
12112
12113 sli4_params = &phba->sli4_hba.pc_sli4_params;
12114 sli4_params->if_type = bf_get(if_type, &mqe->un.sli4_params);
12115 sli4_params->sli_rev = bf_get(sli_rev, &mqe->un.sli4_params);
12116 sli4_params->sli_family = bf_get(sli_family, &mqe->un.sli4_params);
12117 sli4_params->featurelevel_1 = bf_get(featurelevel_1,
12118 &mqe->un.sli4_params);
12119 sli4_params->featurelevel_2 = bf_get(featurelevel_2,
12120 &mqe->un.sli4_params);
12121 sli4_params->proto_types = mqe->un.sli4_params.word3;
12122 sli4_params->sge_supp_len = mqe->un.sli4_params.sge_supp_len;
12123 sli4_params->if_page_sz = bf_get(if_page_sz, &mqe->un.sli4_params);
12124 sli4_params->rq_db_window = bf_get(rq_db_window, &mqe->un.sli4_params);
12125 sli4_params->loopbk_scope = bf_get(loopbk_scope, &mqe->un.sli4_params);
12126 sli4_params->eq_pages_max = bf_get(eq_pages, &mqe->un.sli4_params);
12127 sli4_params->eqe_size = bf_get(eqe_size, &mqe->un.sli4_params);
12128 sli4_params->cq_pages_max = bf_get(cq_pages, &mqe->un.sli4_params);
12129 sli4_params->cqe_size = bf_get(cqe_size, &mqe->un.sli4_params);
12130 sli4_params->mq_pages_max = bf_get(mq_pages, &mqe->un.sli4_params);
12131 sli4_params->mqe_size = bf_get(mqe_size, &mqe->un.sli4_params);
12132 sli4_params->mq_elem_cnt = bf_get(mq_elem_cnt, &mqe->un.sli4_params);
12133 sli4_params->wq_pages_max = bf_get(wq_pages, &mqe->un.sli4_params);
12134 sli4_params->wqe_size = bf_get(wqe_size, &mqe->un.sli4_params);
12135 sli4_params->rq_pages_max = bf_get(rq_pages, &mqe->un.sli4_params);
12136 sli4_params->rqe_size = bf_get(rqe_size, &mqe->un.sli4_params);
12137 sli4_params->hdr_pages_max = bf_get(hdr_pages, &mqe->un.sli4_params);
12138 sli4_params->hdr_size = bf_get(hdr_size, &mqe->un.sli4_params);
12139 sli4_params->hdr_pp_align = bf_get(hdr_pp_align, &mqe->un.sli4_params);
12140 sli4_params->sgl_pages_max = bf_get(sgl_pages, &mqe->un.sli4_params);
12141 sli4_params->sgl_pp_align = bf_get(sgl_pp_align, &mqe->un.sli4_params);
0558056c
JS
12142
12143 /* Make sure that sge_supp_len can be handled by the driver */
12144 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
12145 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
12146
28baac74
JS
12147 return rc;
12148}
12149
fedd3b7b
JS
12150/**
12151 * lpfc_get_sli4_parameters - Get the SLI4 Config PARAMETERS.
12152 * @phba: Pointer to HBA context object.
12153 * @mboxq: Pointer to the mailboxq memory for the mailbox command response.
12154 *
12155 * This function is called in the SLI4 code path to read the port's
12156 * sli4 capabilities.
12157 *
12158 * This function may be be called from any context that can block-wait
12159 * for the completion. The expectation is that this routine is called
12160 * typically from probe_one or from the online routine.
12161 **/
12162int
12163lpfc_get_sli4_parameters(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
12164{
12165 int rc;
12166 struct lpfc_mqe *mqe = &mboxq->u.mqe;
12167 struct lpfc_pc_sli4_params *sli4_params;
a183a15f 12168 uint32_t mbox_tmo;
fedd3b7b 12169 int length;
bf316c78 12170 bool exp_wqcq_pages = true;
fedd3b7b
JS
12171 struct lpfc_sli4_parameters *mbx_sli4_parameters;
12172
6d368e53
JS
12173 /*
12174 * By default, the driver assumes the SLI4 port requires RPI
12175 * header postings. The SLI4_PARAM response will correct this
12176 * assumption.
12177 */
12178 phba->sli4_hba.rpi_hdrs_in_use = 1;
12179
fedd3b7b
JS
12180 /* Read the port's SLI4 Config Parameters */
12181 length = (sizeof(struct lpfc_mbx_get_sli4_parameters) -
12182 sizeof(struct lpfc_sli4_cfg_mhdr));
12183 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
12184 LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS,
12185 length, LPFC_SLI4_MBX_EMBED);
12186 if (!phba->sli4_hba.intr_enable)
12187 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
a183a15f
JS
12188 else {
12189 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
12190 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
12191 }
fedd3b7b
JS
12192 if (unlikely(rc))
12193 return rc;
12194 sli4_params = &phba->sli4_hba.pc_sli4_params;
12195 mbx_sli4_parameters = &mqe->un.get_sli4_parameters.sli4_parameters;
12196 sli4_params->if_type = bf_get(cfg_if_type, mbx_sli4_parameters);
12197 sli4_params->sli_rev = bf_get(cfg_sli_rev, mbx_sli4_parameters);
12198 sli4_params->sli_family = bf_get(cfg_sli_family, mbx_sli4_parameters);
12199 sli4_params->featurelevel_1 = bf_get(cfg_sli_hint_1,
12200 mbx_sli4_parameters);
12201 sli4_params->featurelevel_2 = bf_get(cfg_sli_hint_2,
12202 mbx_sli4_parameters);
12203 if (bf_get(cfg_phwq, mbx_sli4_parameters))
12204 phba->sli3_options |= LPFC_SLI4_PHWQ_ENABLED;
12205 else
12206 phba->sli3_options &= ~LPFC_SLI4_PHWQ_ENABLED;
12207 sli4_params->sge_supp_len = mbx_sli4_parameters->sge_supp_len;
12208 sli4_params->loopbk_scope = bf_get(loopbk_scope, mbx_sli4_parameters);
1ba981fd 12209 sli4_params->oas_supported = bf_get(cfg_oas, mbx_sli4_parameters);
fedd3b7b
JS
12210 sli4_params->cqv = bf_get(cfg_cqv, mbx_sli4_parameters);
12211 sli4_params->mqv = bf_get(cfg_mqv, mbx_sli4_parameters);
12212 sli4_params->wqv = bf_get(cfg_wqv, mbx_sli4_parameters);
12213 sli4_params->rqv = bf_get(cfg_rqv, mbx_sli4_parameters);
7365f6fd
JS
12214 sli4_params->eqav = bf_get(cfg_eqav, mbx_sli4_parameters);
12215 sli4_params->cqav = bf_get(cfg_cqav, mbx_sli4_parameters);
0c651878 12216 sli4_params->wqsize = bf_get(cfg_wqsize, mbx_sli4_parameters);
66e9e6bf 12217 sli4_params->bv1s = bf_get(cfg_bv1s, mbx_sli4_parameters);
83c6cb1a 12218 sli4_params->pls = bf_get(cfg_pvl, mbx_sli4_parameters);
fedd3b7b
JS
12219 sli4_params->sgl_pages_max = bf_get(cfg_sgl_page_cnt,
12220 mbx_sli4_parameters);
895427bd 12221 sli4_params->wqpcnt = bf_get(cfg_wqpcnt, mbx_sli4_parameters);
fedd3b7b
JS
12222 sli4_params->sgl_pp_align = bf_get(cfg_sgl_pp_align,
12223 mbx_sli4_parameters);
6d368e53
JS
12224 phba->sli4_hba.extents_in_use = bf_get(cfg_ext, mbx_sli4_parameters);
12225 phba->sli4_hba.rpi_hdrs_in_use = bf_get(cfg_hdrr, mbx_sli4_parameters);
c15e0704 12226
d79c9e9d
JS
12227 /* Check for Extended Pre-Registered SGL support */
12228 phba->cfg_xpsgl = bf_get(cfg_xpsgl, mbx_sli4_parameters);
12229
c15e0704
JS
12230 /* Check for firmware nvme support */
12231 rc = (bf_get(cfg_nvme, mbx_sli4_parameters) &&
12232 bf_get(cfg_xib, mbx_sli4_parameters));
12233
12234 if (rc) {
12235 /* Save this to indicate the Firmware supports NVME */
12236 sli4_params->nvme = 1;
12237
12238 /* Firmware NVME support, check driver FC4 NVME support */
12239 if (phba->cfg_enable_fc4_type == LPFC_ENABLE_FCP) {
12240 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME,
12241 "6133 Disabling NVME support: "
12242 "FC4 type not supported: x%x\n",
12243 phba->cfg_enable_fc4_type);
12244 goto fcponly;
12245 }
12246 } else {
12247 /* No firmware NVME support, check driver FC4 NVME support */
12248 sli4_params->nvme = 0;
12249 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
12250 lpfc_printf_log(phba, KERN_ERR, LOG_INIT | LOG_NVME,
12251 "6101 Disabling NVME support: Not "
12252 "supported by firmware (%d %d) x%x\n",
12253 bf_get(cfg_nvme, mbx_sli4_parameters),
12254 bf_get(cfg_xib, mbx_sli4_parameters),
12255 phba->cfg_enable_fc4_type);
12256fcponly:
12257 phba->nvme_support = 0;
12258 phba->nvmet_support = 0;
12259 phba->cfg_nvmet_mrq = 0;
6a224b47 12260 phba->cfg_nvme_seg_cnt = 0;
c15e0704
JS
12261
12262 /* If no FC4 type support, move to just SCSI support */
12263 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
12264 return -ENODEV;
12265 phba->cfg_enable_fc4_type = LPFC_ENABLE_FCP;
12266 }
895427bd 12267 }
0558056c 12268
c26c265b 12269 /* If the NVME FC4 type is enabled, scale the sg_seg_cnt to
a5f7337f 12270 * accommodate 512K and 1M IOs in a single nvme buf.
c26c265b 12271 */
a5f7337f 12272 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
c26c265b 12273 phba->cfg_sg_seg_cnt = LPFC_MAX_NVME_SEG_CNT;
c26c265b 12274
414abe0a
JS
12275 /* Only embed PBDE for if_type 6, PBDE support requires xib be set */
12276 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) !=
12277 LPFC_SLI_INTF_IF_TYPE_6) || (!bf_get(cfg_xib, mbx_sli4_parameters)))
12278 phba->cfg_enable_pbde = 0;
0bc2b7c5 12279
20aefac3
JS
12280 /*
12281 * To support Suppress Response feature we must satisfy 3 conditions.
12282 * lpfc_suppress_rsp module parameter must be set (default).
12283 * In SLI4-Parameters Descriptor:
12284 * Extended Inline Buffers (XIB) must be supported.
12285 * Suppress Response IU Not Supported (SRIUNS) must NOT be supported
12286 * (double negative).
12287 */
12288 if (phba->cfg_suppress_rsp && bf_get(cfg_xib, mbx_sli4_parameters) &&
12289 !(bf_get(cfg_nosr, mbx_sli4_parameters)))
f358dd0c 12290 phba->sli.sli_flag |= LPFC_SLI_SUPPRESS_RSP;
20aefac3
JS
12291 else
12292 phba->cfg_suppress_rsp = 0;
f358dd0c 12293
0cf07f84
JS
12294 if (bf_get(cfg_eqdr, mbx_sli4_parameters))
12295 phba->sli.sli_flag |= LPFC_SLI_USE_EQDR;
12296
0558056c
JS
12297 /* Make sure that sge_supp_len can be handled by the driver */
12298 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
12299 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
12300
b5c53958 12301 /*
c176ffa0
JS
12302 * Check whether the adapter supports an embedded copy of the
12303 * FCP CMD IU within the WQE for FCP_Ixxx commands. In order
12304 * to use this option, 128-byte WQEs must be used.
b5c53958
JS
12305 */
12306 if (bf_get(cfg_ext_embed_cb, mbx_sli4_parameters))
12307 phba->fcp_embed_io = 1;
12308 else
12309 phba->fcp_embed_io = 0;
7bdedb34 12310
0bc2b7c5 12311 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME,
414abe0a 12312 "6422 XIB %d PBDE %d: FCP %d NVME %d %d %d\n",
0bc2b7c5 12313 bf_get(cfg_xib, mbx_sli4_parameters),
414abe0a
JS
12314 phba->cfg_enable_pbde,
12315 phba->fcp_embed_io, phba->nvme_support,
4e565cf0 12316 phba->cfg_nvme_embed_cmd, phba->cfg_suppress_rsp);
0bc2b7c5 12317
bf316c78
JS
12318 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
12319 LPFC_SLI_INTF_IF_TYPE_2) &&
12320 (bf_get(lpfc_sli_intf_sli_family, &phba->sli4_hba.sli_intf) ==
c221768b 12321 LPFC_SLI_INTF_FAMILY_LNCR_A0))
bf316c78
JS
12322 exp_wqcq_pages = false;
12323
c176ffa0
JS
12324 if ((bf_get(cfg_cqpsize, mbx_sli4_parameters) & LPFC_CQ_16K_PAGE_SZ) &&
12325 (bf_get(cfg_wqpsize, mbx_sli4_parameters) & LPFC_WQ_16K_PAGE_SZ) &&
bf316c78 12326 exp_wqcq_pages &&
c176ffa0
JS
12327 (sli4_params->wqsize & LPFC_WQ_SZ128_SUPPORT))
12328 phba->enab_exp_wqcq_pages = 1;
12329 else
12330 phba->enab_exp_wqcq_pages = 0;
7bdedb34
JS
12331 /*
12332 * Check if the SLI port supports MDS Diagnostics
12333 */
12334 if (bf_get(cfg_mds_diags, mbx_sli4_parameters))
12335 phba->mds_diags_support = 1;
12336 else
12337 phba->mds_diags_support = 0;
d2cc9bcd 12338
0d8af096
JS
12339 /*
12340 * Check if the SLI port supports NSLER
12341 */
12342 if (bf_get(cfg_nsler, mbx_sli4_parameters))
12343 phba->nsler = 1;
12344 else
12345 phba->nsler = 0;
12346
8aaa7bcf
JS
12347 /* Save PB info for use during HBA setup */
12348 sli4_params->mi_ver = bf_get(cfg_mi_ver, mbx_sli4_parameters);
12349 sli4_params->mib_bde_cnt = bf_get(cfg_mib_bde_cnt, mbx_sli4_parameters);
12350 sli4_params->mib_size = mbx_sli4_parameters->mib_size;
12351 sli4_params->mi_value = LPFC_DFLT_MIB_VAL;
12352
12353 /* Next we check for Vendor MIB support */
12354 if (sli4_params->mi_ver && phba->cfg_enable_mi)
12355 phba->cfg_fdmi_on = LPFC_FDMI_SUPPORT;
12356
12357 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12358 "6461 MIB attr %d enable %d FDMI %d buf %d:%d\n",
12359 sli4_params->mi_ver, phba->cfg_enable_mi,
12360 sli4_params->mi_value, sli4_params->mib_bde_cnt,
12361 sli4_params->mib_size);
fedd3b7b
JS
12362 return 0;
12363}
12364
da0436e9
JS
12365/**
12366 * lpfc_pci_probe_one_s3 - PCI probe func to reg SLI-3 device to PCI subsystem.
12367 * @pdev: pointer to PCI device
12368 * @pid: pointer to PCI device identifier
12369 *
12370 * This routine is to be called to attach a device with SLI-3 interface spec
12371 * to the PCI subsystem. When an Emulex HBA with SLI-3 interface spec is
12372 * presented on PCI bus, the kernel PCI subsystem looks at PCI device-specific
12373 * information of the device and driver to see if the driver state that it can
12374 * support this kind of device. If the match is successful, the driver core
12375 * invokes this routine. If this routine determines it can claim the HBA, it
12376 * does all the initialization that it needs to do to handle the HBA properly.
12377 *
12378 * Return code
12379 * 0 - driver can claim the device
12380 * negative value - driver can not claim the device
12381 **/
6f039790 12382static int
da0436e9
JS
12383lpfc_pci_probe_one_s3(struct pci_dev *pdev, const struct pci_device_id *pid)
12384{
12385 struct lpfc_hba *phba;
12386 struct lpfc_vport *vport = NULL;
6669f9bb 12387 struct Scsi_Host *shost = NULL;
da0436e9
JS
12388 int error;
12389 uint32_t cfg_mode, intr_mode;
12390
12391 /* Allocate memory for HBA structure */
12392 phba = lpfc_hba_alloc(pdev);
12393 if (!phba)
12394 return -ENOMEM;
12395
12396 /* Perform generic PCI device enabling operation */
12397 error = lpfc_enable_pci_dev(phba);
079b5c91 12398 if (error)
da0436e9 12399 goto out_free_phba;
da0436e9
JS
12400
12401 /* Set up SLI API function jump table for PCI-device group-0 HBAs */
12402 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_LP);
12403 if (error)
12404 goto out_disable_pci_dev;
12405
12406 /* Set up SLI-3 specific device PCI memory space */
12407 error = lpfc_sli_pci_mem_setup(phba);
12408 if (error) {
12409 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12410 "1402 Failed to set up pci memory space.\n");
12411 goto out_disable_pci_dev;
12412 }
12413
da0436e9
JS
12414 /* Set up SLI-3 specific device driver resources */
12415 error = lpfc_sli_driver_resource_setup(phba);
12416 if (error) {
12417 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12418 "1404 Failed to set up driver resource.\n");
12419 goto out_unset_pci_mem_s3;
12420 }
12421
12422 /* Initialize and populate the iocb list per host */
d1f525aa 12423
da0436e9
JS
12424 error = lpfc_init_iocb_list(phba, LPFC_IOCB_LIST_CNT);
12425 if (error) {
12426 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12427 "1405 Failed to initialize iocb list.\n");
12428 goto out_unset_driver_resource_s3;
12429 }
12430
12431 /* Set up common device driver resources */
12432 error = lpfc_setup_driver_resource_phase2(phba);
12433 if (error) {
12434 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12435 "1406 Failed to set up driver resource.\n");
12436 goto out_free_iocb_list;
12437 }
12438
079b5c91
JS
12439 /* Get the default values for Model Name and Description */
12440 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
12441
da0436e9
JS
12442 /* Create SCSI host to the physical port */
12443 error = lpfc_create_shost(phba);
12444 if (error) {
12445 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12446 "1407 Failed to create scsi host.\n");
12447 goto out_unset_driver_resource;
12448 }
12449
12450 /* Configure sysfs attributes */
12451 vport = phba->pport;
12452 error = lpfc_alloc_sysfs_attr(vport);
12453 if (error) {
12454 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12455 "1476 Failed to allocate sysfs attr\n");
12456 goto out_destroy_shost;
12457 }
12458
6669f9bb 12459 shost = lpfc_shost_from_vport(vport); /* save shost for error cleanup */
da0436e9
JS
12460 /* Now, trying to enable interrupt and bring up the device */
12461 cfg_mode = phba->cfg_use_msi;
12462 while (true) {
12463 /* Put device to a known state before enabling interrupt */
12464 lpfc_stop_port(phba);
12465 /* Configure and enable interrupt */
12466 intr_mode = lpfc_sli_enable_intr(phba, cfg_mode);
12467 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 12468 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
12469 "0431 Failed to enable interrupt.\n");
12470 error = -ENODEV;
12471 goto out_free_sysfs_attr;
12472 }
12473 /* SLI-3 HBA setup */
12474 if (lpfc_sli_hba_setup(phba)) {
372c187b 12475 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
12476 "1477 Failed to set up hba\n");
12477 error = -ENODEV;
12478 goto out_remove_device;
12479 }
12480
12481 /* Wait 50ms for the interrupts of previous mailbox commands */
12482 msleep(50);
12483 /* Check active interrupts on message signaled interrupts */
12484 if (intr_mode == 0 ||
12485 phba->sli.slistat.sli_intr > LPFC_MSIX_VECTORS) {
12486 /* Log the current active interrupt mode */
12487 phba->intr_mode = intr_mode;
12488 lpfc_log_intr_mode(phba, intr_mode);
12489 break;
12490 } else {
12491 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12492 "0447 Configure interrupt mode (%d) "
12493 "failed active interrupt test.\n",
12494 intr_mode);
12495 /* Disable the current interrupt mode */
12496 lpfc_sli_disable_intr(phba);
12497 /* Try next level of interrupt mode */
12498 cfg_mode = --intr_mode;
12499 }
12500 }
12501
12502 /* Perform post initialization setup */
12503 lpfc_post_init_setup(phba);
12504
12505 /* Check if there are static vports to be created. */
12506 lpfc_create_static_vport(phba);
12507
12508 return 0;
12509
12510out_remove_device:
12511 lpfc_unset_hba(phba);
12512out_free_sysfs_attr:
12513 lpfc_free_sysfs_attr(vport);
12514out_destroy_shost:
12515 lpfc_destroy_shost(phba);
12516out_unset_driver_resource:
12517 lpfc_unset_driver_resource_phase2(phba);
12518out_free_iocb_list:
12519 lpfc_free_iocb_list(phba);
12520out_unset_driver_resource_s3:
12521 lpfc_sli_driver_resource_unset(phba);
12522out_unset_pci_mem_s3:
12523 lpfc_sli_pci_mem_unset(phba);
12524out_disable_pci_dev:
12525 lpfc_disable_pci_dev(phba);
6669f9bb
JS
12526 if (shost)
12527 scsi_host_put(shost);
da0436e9
JS
12528out_free_phba:
12529 lpfc_hba_free(phba);
12530 return error;
12531}
12532
12533/**
12534 * lpfc_pci_remove_one_s3 - PCI func to unreg SLI-3 device from PCI subsystem.
12535 * @pdev: pointer to PCI device
12536 *
12537 * This routine is to be called to disattach a device with SLI-3 interface
12538 * spec from PCI subsystem. When an Emulex HBA with SLI-3 interface spec is
12539 * removed from PCI bus, it performs all the necessary cleanup for the HBA
12540 * device to be removed from the PCI subsystem properly.
12541 **/
6f039790 12542static void
da0436e9
JS
12543lpfc_pci_remove_one_s3(struct pci_dev *pdev)
12544{
12545 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12546 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
12547 struct lpfc_vport **vports;
12548 struct lpfc_hba *phba = vport->phba;
12549 int i;
da0436e9
JS
12550
12551 spin_lock_irq(&phba->hbalock);
12552 vport->load_flag |= FC_UNLOADING;
12553 spin_unlock_irq(&phba->hbalock);
12554
12555 lpfc_free_sysfs_attr(vport);
12556
12557 /* Release all the vports against this physical port */
12558 vports = lpfc_create_vport_work_array(phba);
12559 if (vports != NULL)
587a37f6
JS
12560 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
12561 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
12562 continue;
da0436e9 12563 fc_vport_terminate(vports[i]->fc_vport);
587a37f6 12564 }
da0436e9
JS
12565 lpfc_destroy_vport_work_array(phba, vports);
12566
95f0ef8a 12567 /* Remove FC host with the physical port */
da0436e9 12568 fc_remove_host(shost);
e9b11083 12569 scsi_remove_host(shost);
d613b6a7 12570
95f0ef8a 12571 /* Clean up all nodes, mailboxes and IOs. */
da0436e9
JS
12572 lpfc_cleanup(vport);
12573
12574 /*
12575 * Bring down the SLI Layer. This step disable all interrupts,
12576 * clears the rings, discards all mailbox commands, and resets
12577 * the HBA.
12578 */
12579
48e34d0f 12580 /* HBA interrupt will be disabled after this call */
da0436e9
JS
12581 lpfc_sli_hba_down(phba);
12582 /* Stop kthread signal shall trigger work_done one more time */
12583 kthread_stop(phba->worker_thread);
12584 /* Final cleanup of txcmplq and reset the HBA */
12585 lpfc_sli_brdrestart(phba);
12586
72859909
JS
12587 kfree(phba->vpi_bmask);
12588 kfree(phba->vpi_ids);
12589
da0436e9 12590 lpfc_stop_hba_timers(phba);
523128e5 12591 spin_lock_irq(&phba->port_list_lock);
da0436e9 12592 list_del_init(&vport->listentry);
523128e5 12593 spin_unlock_irq(&phba->port_list_lock);
da0436e9
JS
12594
12595 lpfc_debugfs_terminate(vport);
12596
912e3acd
JS
12597 /* Disable SR-IOV if enabled */
12598 if (phba->cfg_sriov_nr_virtfn)
12599 pci_disable_sriov(pdev);
12600
da0436e9
JS
12601 /* Disable interrupt */
12602 lpfc_sli_disable_intr(phba);
12603
da0436e9
JS
12604 scsi_host_put(shost);
12605
12606 /*
12607 * Call scsi_free before mem_free since scsi bufs are released to their
12608 * corresponding pools here.
12609 */
12610 lpfc_scsi_free(phba);
0794d601
JS
12611 lpfc_free_iocb_list(phba);
12612
da0436e9
JS
12613 lpfc_mem_free_all(phba);
12614
12615 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
12616 phba->hbqslimp.virt, phba->hbqslimp.phys);
12617
12618 /* Free resources associated with SLI2 interface */
12619 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
12620 phba->slim2p.virt, phba->slim2p.phys);
12621
12622 /* unmap adapter SLIM and Control Registers */
12623 iounmap(phba->ctrl_regs_memmap_p);
12624 iounmap(phba->slim_memmap_p);
12625
12626 lpfc_hba_free(phba);
12627
e0c0483c 12628 pci_release_mem_regions(pdev);
da0436e9
JS
12629 pci_disable_device(pdev);
12630}
12631
12632/**
12633 * lpfc_pci_suspend_one_s3 - PCI func to suspend SLI-3 device for power mgmnt
ef6fa16b 12634 * @dev_d: pointer to device
da0436e9
JS
12635 *
12636 * This routine is to be called from the kernel's PCI subsystem to support
12637 * system Power Management (PM) to device with SLI-3 interface spec. When
12638 * PM invokes this method, it quiesces the device by stopping the driver's
12639 * worker thread for the device, turning off device's interrupt and DMA,
12640 * and bring the device offline. Note that as the driver implements the
12641 * minimum PM requirements to a power-aware driver's PM support for the
12642 * suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE, FREEZE)
12643 * to the suspend() method call will be treated as SUSPEND and the driver will
12644 * fully reinitialize its device during resume() method call, the driver will
12645 * set device to PCI_D3hot state in PCI config space instead of setting it
12646 * according to the @msg provided by the PM.
12647 *
12648 * Return code
12649 * 0 - driver suspended the device
12650 * Error otherwise
12651 **/
ef6fa16b
VG
12652static int __maybe_unused
12653lpfc_pci_suspend_one_s3(struct device *dev_d)
da0436e9 12654{
ef6fa16b 12655 struct Scsi_Host *shost = dev_get_drvdata(dev_d);
da0436e9
JS
12656 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12657
12658 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12659 "0473 PCI device Power Management suspend.\n");
12660
12661 /* Bring down the device */
618a5230 12662 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
da0436e9
JS
12663 lpfc_offline(phba);
12664 kthread_stop(phba->worker_thread);
12665
12666 /* Disable interrupt from device */
12667 lpfc_sli_disable_intr(phba);
12668
da0436e9
JS
12669 return 0;
12670}
12671
12672/**
12673 * lpfc_pci_resume_one_s3 - PCI func to resume SLI-3 device for power mgmnt
ef6fa16b 12674 * @dev_d: pointer to device
da0436e9
JS
12675 *
12676 * This routine is to be called from the kernel's PCI subsystem to support
12677 * system Power Management (PM) to device with SLI-3 interface spec. When PM
12678 * invokes this method, it restores the device's PCI config space state and
12679 * fully reinitializes the device and brings it online. Note that as the
12680 * driver implements the minimum PM requirements to a power-aware driver's
12681 * PM for suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE,
12682 * FREEZE) to the suspend() method call will be treated as SUSPEND and the
12683 * driver will fully reinitialize its device during resume() method call,
12684 * the device will be set to PCI_D0 directly in PCI config space before
12685 * restoring the state.
12686 *
12687 * Return code
12688 * 0 - driver suspended the device
12689 * Error otherwise
12690 **/
ef6fa16b
VG
12691static int __maybe_unused
12692lpfc_pci_resume_one_s3(struct device *dev_d)
da0436e9 12693{
ef6fa16b 12694 struct Scsi_Host *shost = dev_get_drvdata(dev_d);
da0436e9
JS
12695 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12696 uint32_t intr_mode;
12697 int error;
12698
12699 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12700 "0452 PCI device Power Management resume.\n");
12701
da0436e9
JS
12702 /* Startup the kernel thread for this host adapter. */
12703 phba->worker_thread = kthread_run(lpfc_do_work, phba,
12704 "lpfc_worker_%d", phba->brd_no);
12705 if (IS_ERR(phba->worker_thread)) {
12706 error = PTR_ERR(phba->worker_thread);
12707 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12708 "0434 PM resume failed to start worker "
12709 "thread: error=x%x.\n", error);
12710 return error;
12711 }
12712
12713 /* Configure and enable interrupt */
12714 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
12715 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 12716 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
12717 "0430 PM resume Failed to enable interrupt\n");
12718 return -EIO;
12719 } else
12720 phba->intr_mode = intr_mode;
12721
12722 /* Restart HBA and bring it online */
12723 lpfc_sli_brdrestart(phba);
12724 lpfc_online(phba);
12725
12726 /* Log the current active interrupt mode */
12727 lpfc_log_intr_mode(phba, phba->intr_mode);
12728
12729 return 0;
12730}
12731
891478a2
JS
12732/**
12733 * lpfc_sli_prep_dev_for_recover - Prepare SLI3 device for pci slot recover
12734 * @phba: pointer to lpfc hba data structure.
12735 *
12736 * This routine is called to prepare the SLI3 device for PCI slot recover. It
e2af0d2e 12737 * aborts all the outstanding SCSI I/Os to the pci device.
891478a2
JS
12738 **/
12739static void
12740lpfc_sli_prep_dev_for_recover(struct lpfc_hba *phba)
12741{
372c187b 12742 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
891478a2 12743 "2723 PCI channel I/O abort preparing for recovery\n");
e2af0d2e
JS
12744
12745 /*
12746 * There may be errored I/Os through HBA, abort all I/Os on txcmplq
12747 * and let the SCSI mid-layer to retry them to recover.
12748 */
db55fba8 12749 lpfc_sli_abort_fcp_rings(phba);
891478a2
JS
12750}
12751
0d878419
JS
12752/**
12753 * lpfc_sli_prep_dev_for_reset - Prepare SLI3 device for pci slot reset
12754 * @phba: pointer to lpfc hba data structure.
12755 *
12756 * This routine is called to prepare the SLI3 device for PCI slot reset. It
12757 * disables the device interrupt and pci device, and aborts the internal FCP
12758 * pending I/Os.
12759 **/
12760static void
12761lpfc_sli_prep_dev_for_reset(struct lpfc_hba *phba)
12762{
372c187b 12763 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
891478a2 12764 "2710 PCI channel disable preparing for reset\n");
e2af0d2e 12765
75baf696 12766 /* Block any management I/Os to the device */
618a5230 12767 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
75baf696 12768
e2af0d2e
JS
12769 /* Block all SCSI devices' I/Os on the host */
12770 lpfc_scsi_dev_block(phba);
12771
ea714f3d 12772 /* Flush all driver's outstanding SCSI I/Os as we are to reset */
c00f62e6 12773 lpfc_sli_flush_io_rings(phba);
ea714f3d 12774
e2af0d2e
JS
12775 /* stop all timers */
12776 lpfc_stop_hba_timers(phba);
12777
0d878419
JS
12778 /* Disable interrupt and pci device */
12779 lpfc_sli_disable_intr(phba);
12780 pci_disable_device(phba->pcidev);
0d878419
JS
12781}
12782
12783/**
12784 * lpfc_sli_prep_dev_for_perm_failure - Prepare SLI3 dev for pci slot disable
12785 * @phba: pointer to lpfc hba data structure.
12786 *
12787 * This routine is called to prepare the SLI3 device for PCI slot permanently
12788 * disabling. It blocks the SCSI transport layer traffic and flushes the FCP
12789 * pending I/Os.
12790 **/
12791static void
75baf696 12792lpfc_sli_prep_dev_for_perm_failure(struct lpfc_hba *phba)
0d878419 12793{
372c187b 12794 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
891478a2 12795 "2711 PCI channel permanent disable for failure\n");
e2af0d2e
JS
12796 /* Block all SCSI devices' I/Os on the host */
12797 lpfc_scsi_dev_block(phba);
12798
12799 /* stop all timers */
12800 lpfc_stop_hba_timers(phba);
12801
0d878419 12802 /* Clean up all driver's outstanding SCSI I/Os */
c00f62e6 12803 lpfc_sli_flush_io_rings(phba);
0d878419
JS
12804}
12805
da0436e9
JS
12806/**
12807 * lpfc_io_error_detected_s3 - Method for handling SLI-3 device PCI I/O error
12808 * @pdev: pointer to PCI device.
12809 * @state: the current PCI connection state.
12810 *
12811 * This routine is called from the PCI subsystem for I/O error handling to
12812 * device with SLI-3 interface spec. This function is called by the PCI
12813 * subsystem after a PCI bus error affecting this device has been detected.
12814 * When this function is invoked, it will need to stop all the I/Os and
12815 * interrupt(s) to the device. Once that is done, it will return
12816 * PCI_ERS_RESULT_NEED_RESET for the PCI subsystem to perform proper recovery
12817 * as desired.
12818 *
12819 * Return codes
0d878419 12820 * PCI_ERS_RESULT_CAN_RECOVER - can be recovered with reset_link
da0436e9
JS
12821 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
12822 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
12823 **/
12824static pci_ers_result_t
12825lpfc_io_error_detected_s3(struct pci_dev *pdev, pci_channel_state_t state)
12826{
12827 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12828 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
da0436e9 12829
0d878419
JS
12830 switch (state) {
12831 case pci_channel_io_normal:
891478a2
JS
12832 /* Non-fatal error, prepare for recovery */
12833 lpfc_sli_prep_dev_for_recover(phba);
0d878419
JS
12834 return PCI_ERS_RESULT_CAN_RECOVER;
12835 case pci_channel_io_frozen:
12836 /* Fatal error, prepare for slot reset */
12837 lpfc_sli_prep_dev_for_reset(phba);
12838 return PCI_ERS_RESULT_NEED_RESET;
12839 case pci_channel_io_perm_failure:
12840 /* Permanent failure, prepare for device down */
75baf696 12841 lpfc_sli_prep_dev_for_perm_failure(phba);
da0436e9 12842 return PCI_ERS_RESULT_DISCONNECT;
0d878419
JS
12843 default:
12844 /* Unknown state, prepare and request slot reset */
372c187b 12845 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0d878419
JS
12846 "0472 Unknown PCI error state: x%x\n", state);
12847 lpfc_sli_prep_dev_for_reset(phba);
12848 return PCI_ERS_RESULT_NEED_RESET;
da0436e9 12849 }
da0436e9
JS
12850}
12851
12852/**
12853 * lpfc_io_slot_reset_s3 - Method for restarting PCI SLI-3 device from scratch.
12854 * @pdev: pointer to PCI device.
12855 *
12856 * This routine is called from the PCI subsystem for error handling to
12857 * device with SLI-3 interface spec. This is called after PCI bus has been
12858 * reset to restart the PCI card from scratch, as if from a cold-boot.
12859 * During the PCI subsystem error recovery, after driver returns
12860 * PCI_ERS_RESULT_NEED_RESET, the PCI subsystem will perform proper error
12861 * recovery and then call this routine before calling the .resume method
12862 * to recover the device. This function will initialize the HBA device,
12863 * enable the interrupt, but it will just put the HBA to offline state
12864 * without passing any I/O traffic.
12865 *
12866 * Return codes
12867 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
12868 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
12869 */
12870static pci_ers_result_t
12871lpfc_io_slot_reset_s3(struct pci_dev *pdev)
12872{
12873 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12874 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12875 struct lpfc_sli *psli = &phba->sli;
12876 uint32_t intr_mode;
12877
12878 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
12879 if (pci_enable_device_mem(pdev)) {
12880 printk(KERN_ERR "lpfc: Cannot re-enable "
12881 "PCI device after reset.\n");
12882 return PCI_ERS_RESULT_DISCONNECT;
12883 }
12884
12885 pci_restore_state(pdev);
1dfb5a47
JS
12886
12887 /*
12888 * As the new kernel behavior of pci_restore_state() API call clears
12889 * device saved_state flag, need to save the restored state again.
12890 */
12891 pci_save_state(pdev);
12892
da0436e9
JS
12893 if (pdev->is_busmaster)
12894 pci_set_master(pdev);
12895
12896 spin_lock_irq(&phba->hbalock);
12897 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
12898 spin_unlock_irq(&phba->hbalock);
12899
12900 /* Configure and enable interrupt */
12901 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
12902 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 12903 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
12904 "0427 Cannot re-enable interrupt after "
12905 "slot reset.\n");
12906 return PCI_ERS_RESULT_DISCONNECT;
12907 } else
12908 phba->intr_mode = intr_mode;
12909
75baf696 12910 /* Take device offline, it will perform cleanup */
618a5230 12911 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
da0436e9
JS
12912 lpfc_offline(phba);
12913 lpfc_sli_brdrestart(phba);
12914
12915 /* Log the current active interrupt mode */
12916 lpfc_log_intr_mode(phba, phba->intr_mode);
12917
12918 return PCI_ERS_RESULT_RECOVERED;
12919}
12920
12921/**
12922 * lpfc_io_resume_s3 - Method for resuming PCI I/O operation on SLI-3 device.
12923 * @pdev: pointer to PCI device
12924 *
12925 * This routine is called from the PCI subsystem for error handling to device
12926 * with SLI-3 interface spec. It is called when kernel error recovery tells
12927 * the lpfc driver that it is ok to resume normal PCI operation after PCI bus
12928 * error recovery. After this call, traffic can start to flow from this device
12929 * again.
12930 */
12931static void
12932lpfc_io_resume_s3(struct pci_dev *pdev)
12933{
12934 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12935 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
3772a991 12936
e2af0d2e 12937 /* Bring device online, it will be no-op for non-fatal error resume */
da0436e9
JS
12938 lpfc_online(phba);
12939}
3772a991 12940
da0436e9
JS
12941/**
12942 * lpfc_sli4_get_els_iocb_cnt - Calculate the # of ELS IOCBs to reserve
12943 * @phba: pointer to lpfc hba data structure.
12944 *
12945 * returns the number of ELS/CT IOCBs to reserve
12946 **/
12947int
12948lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *phba)
12949{
12950 int max_xri = phba->sli4_hba.max_cfg_param.max_xri;
12951
f1126688
JS
12952 if (phba->sli_rev == LPFC_SLI_REV4) {
12953 if (max_xri <= 100)
6a9c52cf 12954 return 10;
f1126688 12955 else if (max_xri <= 256)
6a9c52cf 12956 return 25;
f1126688 12957 else if (max_xri <= 512)
6a9c52cf 12958 return 50;
f1126688 12959 else if (max_xri <= 1024)
6a9c52cf 12960 return 100;
8a9d2e80 12961 else if (max_xri <= 1536)
6a9c52cf 12962 return 150;
8a9d2e80
JS
12963 else if (max_xri <= 2048)
12964 return 200;
12965 else
12966 return 250;
f1126688
JS
12967 } else
12968 return 0;
3772a991
JS
12969}
12970
895427bd
JS
12971/**
12972 * lpfc_sli4_get_iocb_cnt - Calculate the # of total IOCBs to reserve
12973 * @phba: pointer to lpfc hba data structure.
12974 *
f358dd0c 12975 * returns the number of ELS/CT + NVMET IOCBs to reserve
895427bd
JS
12976 **/
12977int
12978lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba)
12979{
12980 int max_xri = lpfc_sli4_get_els_iocb_cnt(phba);
12981
f358dd0c
JS
12982 if (phba->nvmet_support)
12983 max_xri += LPFC_NVMET_BUF_POST;
895427bd
JS
12984 return max_xri;
12985}
12986
12987
0a5ce731 12988static int
1feb8204
JS
12989lpfc_log_write_firmware_error(struct lpfc_hba *phba, uint32_t offset,
12990 uint32_t magic_number, uint32_t ftype, uint32_t fid, uint32_t fsize,
12991 const struct firmware *fw)
12992{
0a5ce731
JS
12993 int rc;
12994
12995 /* Three cases: (1) FW was not supported on the detected adapter.
12996 * (2) FW update has been locked out administratively.
12997 * (3) Some other error during FW update.
12998 * In each case, an unmaskable message is written to the console
12999 * for admin diagnosis.
13000 */
13001 if (offset == ADD_STATUS_FW_NOT_SUPPORTED ||
a72d56b2 13002 (phba->pcidev->device == PCI_DEVICE_ID_LANCER_G6_FC &&
5792a0e8 13003 magic_number != MAGIC_NUMBER_G6) ||
a72d56b2 13004 (phba->pcidev->device == PCI_DEVICE_ID_LANCER_G7_FC &&
5792a0e8 13005 magic_number != MAGIC_NUMBER_G7)) {
372c187b 13006 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731
JS
13007 "3030 This firmware version is not supported on"
13008 " this HBA model. Device:%x Magic:%x Type:%x "
13009 "ID:%x Size %d %zd\n",
13010 phba->pcidev->device, magic_number, ftype, fid,
13011 fsize, fw->size);
13012 rc = -EINVAL;
13013 } else if (offset == ADD_STATUS_FW_DOWNLOAD_HW_DISABLED) {
372c187b 13014 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731
JS
13015 "3021 Firmware downloads have been prohibited "
13016 "by a system configuration setting on "
13017 "Device:%x Magic:%x Type:%x ID:%x Size %d "
13018 "%zd\n",
13019 phba->pcidev->device, magic_number, ftype, fid,
13020 fsize, fw->size);
13021 rc = -EACCES;
13022 } else {
372c187b 13023 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731
JS
13024 "3022 FW Download failed. Add Status x%x "
13025 "Device:%x Magic:%x Type:%x ID:%x Size %d "
13026 "%zd\n",
13027 offset, phba->pcidev->device, magic_number,
13028 ftype, fid, fsize, fw->size);
13029 rc = -EIO;
13030 }
13031 return rc;
1feb8204
JS
13032}
13033
52d52440
JS
13034/**
13035 * lpfc_write_firmware - attempt to write a firmware image to the port
52d52440 13036 * @fw: pointer to firmware image returned from request_firmware.
0a5ce731 13037 * @context: pointer to firmware image returned from request_firmware.
52d52440 13038 *
52d52440 13039 **/
ce396282
JS
13040static void
13041lpfc_write_firmware(const struct firmware *fw, void *context)
52d52440 13042{
ce396282 13043 struct lpfc_hba *phba = (struct lpfc_hba *)context;
6b5151fd 13044 char fwrev[FW_REV_STR_SIZE];
ce396282 13045 struct lpfc_grp_hdr *image;
52d52440
JS
13046 struct list_head dma_buffer_list;
13047 int i, rc = 0;
13048 struct lpfc_dmabuf *dmabuf, *next;
13049 uint32_t offset = 0, temp_offset = 0;
6b6ef5db 13050 uint32_t magic_number, ftype, fid, fsize;
52d52440 13051
c71ab861 13052 /* It can be null in no-wait mode, sanity check */
ce396282
JS
13053 if (!fw) {
13054 rc = -ENXIO;
13055 goto out;
13056 }
13057 image = (struct lpfc_grp_hdr *)fw->data;
13058
6b6ef5db
JS
13059 magic_number = be32_to_cpu(image->magic_number);
13060 ftype = bf_get_be32(lpfc_grp_hdr_file_type, image);
1feb8204 13061 fid = bf_get_be32(lpfc_grp_hdr_id, image);
6b6ef5db
JS
13062 fsize = be32_to_cpu(image->size);
13063
52d52440 13064 INIT_LIST_HEAD(&dma_buffer_list);
52d52440 13065 lpfc_decode_firmware_rev(phba, fwrev, 1);
88a2cfbb 13066 if (strncmp(fwrev, image->revision, strnlen(image->revision, 16))) {
372c187b 13067 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
ce396282 13068 "3023 Updating Firmware, Current Version:%s "
52d52440 13069 "New Version:%s\n",
88a2cfbb 13070 fwrev, image->revision);
52d52440
JS
13071 for (i = 0; i < LPFC_MBX_WR_CONFIG_MAX_BDE; i++) {
13072 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf),
13073 GFP_KERNEL);
13074 if (!dmabuf) {
13075 rc = -ENOMEM;
ce396282 13076 goto release_out;
52d52440
JS
13077 }
13078 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
13079 SLI4_PAGE_SIZE,
13080 &dmabuf->phys,
13081 GFP_KERNEL);
13082 if (!dmabuf->virt) {
13083 kfree(dmabuf);
13084 rc = -ENOMEM;
ce396282 13085 goto release_out;
52d52440
JS
13086 }
13087 list_add_tail(&dmabuf->list, &dma_buffer_list);
13088 }
13089 while (offset < fw->size) {
13090 temp_offset = offset;
13091 list_for_each_entry(dmabuf, &dma_buffer_list, list) {
079b5c91 13092 if (temp_offset + SLI4_PAGE_SIZE > fw->size) {
52d52440
JS
13093 memcpy(dmabuf->virt,
13094 fw->data + temp_offset,
079b5c91
JS
13095 fw->size - temp_offset);
13096 temp_offset = fw->size;
52d52440
JS
13097 break;
13098 }
52d52440
JS
13099 memcpy(dmabuf->virt, fw->data + temp_offset,
13100 SLI4_PAGE_SIZE);
88a2cfbb 13101 temp_offset += SLI4_PAGE_SIZE;
52d52440
JS
13102 }
13103 rc = lpfc_wr_object(phba, &dma_buffer_list,
13104 (fw->size - offset), &offset);
1feb8204 13105 if (rc) {
0a5ce731
JS
13106 rc = lpfc_log_write_firmware_error(phba, offset,
13107 magic_number,
13108 ftype,
13109 fid,
13110 fsize,
13111 fw);
ce396282 13112 goto release_out;
1feb8204 13113 }
52d52440
JS
13114 }
13115 rc = offset;
1feb8204 13116 } else
372c187b 13117 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1feb8204
JS
13118 "3029 Skipped Firmware update, Current "
13119 "Version:%s New Version:%s\n",
13120 fwrev, image->revision);
ce396282
JS
13121
13122release_out:
52d52440
JS
13123 list_for_each_entry_safe(dmabuf, next, &dma_buffer_list, list) {
13124 list_del(&dmabuf->list);
13125 dma_free_coherent(&phba->pcidev->dev, SLI4_PAGE_SIZE,
13126 dmabuf->virt, dmabuf->phys);
13127 kfree(dmabuf);
13128 }
ce396282
JS
13129 release_firmware(fw);
13130out:
0a5ce731 13131 if (rc < 0)
372c187b 13132 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731
JS
13133 "3062 Firmware update error, status %d.\n", rc);
13134 else
372c187b 13135 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731 13136 "3024 Firmware update success: size %d.\n", rc);
52d52440
JS
13137}
13138
c71ab861
JS
13139/**
13140 * lpfc_sli4_request_firmware_update - Request linux generic firmware upgrade
13141 * @phba: pointer to lpfc hba data structure.
fe614acd 13142 * @fw_upgrade: which firmware to update.
c71ab861
JS
13143 *
13144 * This routine is called to perform Linux generic firmware upgrade on device
13145 * that supports such feature.
13146 **/
13147int
13148lpfc_sli4_request_firmware_update(struct lpfc_hba *phba, uint8_t fw_upgrade)
13149{
13150 uint8_t file_name[ELX_MODEL_NAME_SIZE];
13151 int ret;
13152 const struct firmware *fw;
13153
13154 /* Only supported on SLI4 interface type 2 for now */
27d6ac0a 13155 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) <
c71ab861
JS
13156 LPFC_SLI_INTF_IF_TYPE_2)
13157 return -EPERM;
13158
13159 snprintf(file_name, ELX_MODEL_NAME_SIZE, "%s.grp", phba->ModelName);
13160
13161 if (fw_upgrade == INT_FW_UPGRADE) {
13162 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
13163 file_name, &phba->pcidev->dev,
13164 GFP_KERNEL, (void *)phba,
13165 lpfc_write_firmware);
13166 } else if (fw_upgrade == RUN_FW_UPGRADE) {
13167 ret = request_firmware(&fw, file_name, &phba->pcidev->dev);
13168 if (!ret)
13169 lpfc_write_firmware(fw, (void *)phba);
13170 } else {
13171 ret = -EINVAL;
13172 }
13173
13174 return ret;
13175}
13176
3772a991 13177/**
da0436e9 13178 * lpfc_pci_probe_one_s4 - PCI probe func to reg SLI-4 device to PCI subsys
3772a991
JS
13179 * @pdev: pointer to PCI device
13180 * @pid: pointer to PCI device identifier
13181 *
da0436e9
JS
13182 * This routine is called from the kernel's PCI subsystem to device with
13183 * SLI-4 interface spec. When an Emulex HBA with SLI-4 interface spec is
3772a991 13184 * presented on PCI bus, the kernel PCI subsystem looks at PCI device-specific
da0436e9
JS
13185 * information of the device and driver to see if the driver state that it
13186 * can support this kind of device. If the match is successful, the driver
13187 * core invokes this routine. If this routine determines it can claim the HBA,
13188 * it does all the initialization that it needs to do to handle the HBA
13189 * properly.
3772a991
JS
13190 *
13191 * Return code
13192 * 0 - driver can claim the device
13193 * negative value - driver can not claim the device
13194 **/
6f039790 13195static int
da0436e9 13196lpfc_pci_probe_one_s4(struct pci_dev *pdev, const struct pci_device_id *pid)
3772a991
JS
13197{
13198 struct lpfc_hba *phba;
13199 struct lpfc_vport *vport = NULL;
6669f9bb 13200 struct Scsi_Host *shost = NULL;
6c621a22 13201 int error;
3772a991
JS
13202 uint32_t cfg_mode, intr_mode;
13203
13204 /* Allocate memory for HBA structure */
13205 phba = lpfc_hba_alloc(pdev);
13206 if (!phba)
13207 return -ENOMEM;
13208
13209 /* Perform generic PCI device enabling operation */
13210 error = lpfc_enable_pci_dev(phba);
079b5c91 13211 if (error)
3772a991 13212 goto out_free_phba;
3772a991 13213
da0436e9
JS
13214 /* Set up SLI API function jump table for PCI-device group-1 HBAs */
13215 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_OC);
3772a991
JS
13216 if (error)
13217 goto out_disable_pci_dev;
13218
da0436e9
JS
13219 /* Set up SLI-4 specific device PCI memory space */
13220 error = lpfc_sli4_pci_mem_setup(phba);
3772a991
JS
13221 if (error) {
13222 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 13223 "1410 Failed to set up pci memory space.\n");
3772a991
JS
13224 goto out_disable_pci_dev;
13225 }
13226
da0436e9
JS
13227 /* Set up SLI-4 Specific device driver resources */
13228 error = lpfc_sli4_driver_resource_setup(phba);
3772a991
JS
13229 if (error) {
13230 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9
JS
13231 "1412 Failed to set up driver resource.\n");
13232 goto out_unset_pci_mem_s4;
3772a991
JS
13233 }
13234
19ca7609 13235 INIT_LIST_HEAD(&phba->active_rrq_list);
7d791df7 13236 INIT_LIST_HEAD(&phba->fcf.fcf_pri_list);
19ca7609 13237
3772a991
JS
13238 /* Set up common device driver resources */
13239 error = lpfc_setup_driver_resource_phase2(phba);
13240 if (error) {
13241 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 13242 "1414 Failed to set up driver resource.\n");
6c621a22 13243 goto out_unset_driver_resource_s4;
3772a991
JS
13244 }
13245
079b5c91
JS
13246 /* Get the default values for Model Name and Description */
13247 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
13248
3772a991 13249 /* Now, trying to enable interrupt and bring up the device */
5b75da2f 13250 cfg_mode = phba->cfg_use_msi;
5b75da2f 13251
7b15db32 13252 /* Put device to a known state before enabling interrupt */
cdb42bec 13253 phba->pport = NULL;
7b15db32 13254 lpfc_stop_port(phba);
895427bd 13255
dcaa2136
JS
13256 /* Init cpu_map array */
13257 lpfc_cpu_map_array_init(phba);
13258
13259 /* Init hba_eq_hdl array */
13260 lpfc_hba_eq_hdl_array_init(phba);
13261
7b15db32
JS
13262 /* Configure and enable interrupt */
13263 intr_mode = lpfc_sli4_enable_intr(phba, cfg_mode);
13264 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 13265 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
7b15db32
JS
13266 "0426 Failed to enable interrupt.\n");
13267 error = -ENODEV;
cdb42bec 13268 goto out_unset_driver_resource;
7b15db32
JS
13269 }
13270 /* Default to single EQ for non-MSI-X */
895427bd 13271 if (phba->intr_type != MSIX) {
6a828b0f 13272 phba->cfg_irq_chann = 1;
2d7dbc4c 13273 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
2d7dbc4c
JS
13274 if (phba->nvmet_support)
13275 phba->cfg_nvmet_mrq = 1;
13276 }
cdb42bec 13277 }
6a828b0f 13278 lpfc_cpu_affinity_check(phba, phba->cfg_irq_chann);
cdb42bec
JS
13279
13280 /* Create SCSI host to the physical port */
13281 error = lpfc_create_shost(phba);
13282 if (error) {
13283 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13284 "1415 Failed to create scsi host.\n");
13285 goto out_disable_intr;
13286 }
13287 vport = phba->pport;
13288 shost = lpfc_shost_from_vport(vport); /* save shost for error cleanup */
13289
13290 /* Configure sysfs attributes */
13291 error = lpfc_alloc_sysfs_attr(vport);
13292 if (error) {
13293 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13294 "1416 Failed to allocate sysfs attr\n");
13295 goto out_destroy_shost;
895427bd
JS
13296 }
13297
7b15db32
JS
13298 /* Set up SLI-4 HBA */
13299 if (lpfc_sli4_hba_setup(phba)) {
372c187b 13300 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
7b15db32
JS
13301 "1421 Failed to set up hba\n");
13302 error = -ENODEV;
cdb42bec 13303 goto out_free_sysfs_attr;
98c9ea5c 13304 }
858c9f6c 13305
7b15db32
JS
13306 /* Log the current active interrupt mode */
13307 phba->intr_mode = intr_mode;
13308 lpfc_log_intr_mode(phba, intr_mode);
13309
3772a991
JS
13310 /* Perform post initialization setup */
13311 lpfc_post_init_setup(phba);
dea3101e 13312
01649561
JS
13313 /* NVME support in FW earlier in the driver load corrects the
13314 * FC4 type making a check for nvme_support unnecessary.
13315 */
0794d601
JS
13316 if (phba->nvmet_support == 0) {
13317 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
13318 /* Create NVME binding with nvme_fc_transport. This
13319 * ensures the vport is initialized. If the localport
13320 * create fails, it should not unload the driver to
13321 * support field issues.
13322 */
13323 error = lpfc_nvme_create_localport(vport);
13324 if (error) {
372c187b 13325 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0794d601
JS
13326 "6004 NVME registration "
13327 "failed, error x%x\n",
13328 error);
13329 }
01649561
JS
13330 }
13331 }
895427bd 13332
c71ab861
JS
13333 /* check for firmware upgrade or downgrade */
13334 if (phba->cfg_request_firmware_upgrade)
db6f1c2f 13335 lpfc_sli4_request_firmware_update(phba, INT_FW_UPGRADE);
52d52440 13336
1c6834a7
JS
13337 /* Check if there are static vports to be created. */
13338 lpfc_create_static_vport(phba);
d2cc9bcd
JS
13339
13340 /* Enable RAS FW log support */
13341 lpfc_sli4_ras_setup(phba);
13342
93a4d6f4 13343 INIT_LIST_HEAD(&phba->poll_list);
f861f596 13344 timer_setup(&phba->cpuhp_poll_timer, lpfc_sli4_poll_hbtimer, 0);
93a4d6f4
JS
13345 cpuhp_state_add_instance_nocalls(lpfc_cpuhp_state, &phba->cpuhp);
13346
dea3101e 13347 return 0;
13348
5b75da2f
JS
13349out_free_sysfs_attr:
13350 lpfc_free_sysfs_attr(vport);
3772a991
JS
13351out_destroy_shost:
13352 lpfc_destroy_shost(phba);
cdb42bec
JS
13353out_disable_intr:
13354 lpfc_sli4_disable_intr(phba);
3772a991
JS
13355out_unset_driver_resource:
13356 lpfc_unset_driver_resource_phase2(phba);
da0436e9
JS
13357out_unset_driver_resource_s4:
13358 lpfc_sli4_driver_resource_unset(phba);
13359out_unset_pci_mem_s4:
13360 lpfc_sli4_pci_mem_unset(phba);
3772a991
JS
13361out_disable_pci_dev:
13362 lpfc_disable_pci_dev(phba);
6669f9bb
JS
13363 if (shost)
13364 scsi_host_put(shost);
2e0fef85 13365out_free_phba:
3772a991 13366 lpfc_hba_free(phba);
dea3101e 13367 return error;
13368}
13369
e59058c4 13370/**
da0436e9 13371 * lpfc_pci_remove_one_s4 - PCI func to unreg SLI-4 device from PCI subsystem
e59058c4
JS
13372 * @pdev: pointer to PCI device
13373 *
da0436e9
JS
13374 * This routine is called from the kernel's PCI subsystem to device with
13375 * SLI-4 interface spec. When an Emulex HBA with SLI-4 interface spec is
3772a991
JS
13376 * removed from PCI bus, it performs all the necessary cleanup for the HBA
13377 * device to be removed from the PCI subsystem properly.
e59058c4 13378 **/
6f039790 13379static void
da0436e9 13380lpfc_pci_remove_one_s4(struct pci_dev *pdev)
dea3101e 13381{
da0436e9 13382 struct Scsi_Host *shost = pci_get_drvdata(pdev);
2e0fef85 13383 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
eada272d 13384 struct lpfc_vport **vports;
da0436e9 13385 struct lpfc_hba *phba = vport->phba;
eada272d 13386 int i;
8a4df120 13387
da0436e9 13388 /* Mark the device unloading flag */
549e55cd 13389 spin_lock_irq(&phba->hbalock);
51ef4c26 13390 vport->load_flag |= FC_UNLOADING;
549e55cd 13391 spin_unlock_irq(&phba->hbalock);
2e0fef85 13392
858c9f6c
JS
13393 lpfc_free_sysfs_attr(vport);
13394
eada272d
JS
13395 /* Release all the vports against this physical port */
13396 vports = lpfc_create_vport_work_array(phba);
13397 if (vports != NULL)
587a37f6
JS
13398 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
13399 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
13400 continue;
eada272d 13401 fc_vport_terminate(vports[i]->fc_vport);
587a37f6 13402 }
eada272d
JS
13403 lpfc_destroy_vport_work_array(phba, vports);
13404
95f0ef8a 13405 /* Remove FC host with the physical port */
858c9f6c 13406 fc_remove_host(shost);
e9b11083 13407 scsi_remove_host(shost);
da0436e9 13408
d613b6a7
JS
13409 /* Perform ndlp cleanup on the physical port. The nvme and nvmet
13410 * localports are destroyed after to cleanup all transport memory.
895427bd 13411 */
87af33fe 13412 lpfc_cleanup(vport);
d613b6a7
JS
13413 lpfc_nvmet_destroy_targetport(phba);
13414 lpfc_nvme_destroy_localport(vport);
87af33fe 13415
c490850a
JS
13416 /* De-allocate multi-XRI pools */
13417 if (phba->cfg_xri_rebalancing)
13418 lpfc_destroy_multixri_pools(phba);
13419
281d6190
JS
13420 /*
13421 * Bring down the SLI Layer. This step disables all interrupts,
13422 * clears the rings, discards all mailbox commands, and resets
13423 * the HBA FCoE function.
13424 */
13425 lpfc_debugfs_terminate(vport);
a257bf90 13426
1901762f 13427 lpfc_stop_hba_timers(phba);
523128e5 13428 spin_lock_irq(&phba->port_list_lock);
858c9f6c 13429 list_del_init(&vport->listentry);
523128e5 13430 spin_unlock_irq(&phba->port_list_lock);
858c9f6c 13431
3677a3a7 13432 /* Perform scsi free before driver resource_unset since scsi
da0436e9 13433 * buffers are released to their corresponding pools here.
2e0fef85 13434 */
5e5b511d 13435 lpfc_io_free(phba);
01649561 13436 lpfc_free_iocb_list(phba);
5e5b511d 13437 lpfc_sli4_hba_unset(phba);
67d12733 13438
0cdb84ec 13439 lpfc_unset_driver_resource_phase2(phba);
da0436e9 13440 lpfc_sli4_driver_resource_unset(phba);
ed957684 13441
da0436e9
JS
13442 /* Unmap adapter Control and Doorbell registers */
13443 lpfc_sli4_pci_mem_unset(phba);
2e0fef85 13444
da0436e9
JS
13445 /* Release PCI resources and disable device's PCI function */
13446 scsi_host_put(shost);
13447 lpfc_disable_pci_dev(phba);
2e0fef85 13448
da0436e9 13449 /* Finally, free the driver's device data structure */
3772a991 13450 lpfc_hba_free(phba);
2e0fef85 13451
da0436e9 13452 return;
dea3101e 13453}
13454
3a55b532 13455/**
da0436e9 13456 * lpfc_pci_suspend_one_s4 - PCI func to suspend SLI-4 device for power mgmnt
ef6fa16b 13457 * @dev_d: pointer to device
3a55b532 13458 *
da0436e9
JS
13459 * This routine is called from the kernel's PCI subsystem to support system
13460 * Power Management (PM) to device with SLI-4 interface spec. When PM invokes
13461 * this method, it quiesces the device by stopping the driver's worker
13462 * thread for the device, turning off device's interrupt and DMA, and bring
13463 * the device offline. Note that as the driver implements the minimum PM
13464 * requirements to a power-aware driver's PM support for suspend/resume -- all
13465 * the possible PM messages (SUSPEND, HIBERNATE, FREEZE) to the suspend()
13466 * method call will be treated as SUSPEND and the driver will fully
13467 * reinitialize its device during resume() method call, the driver will set
13468 * device to PCI_D3hot state in PCI config space instead of setting it
3772a991 13469 * according to the @msg provided by the PM.
3a55b532
JS
13470 *
13471 * Return code
3772a991
JS
13472 * 0 - driver suspended the device
13473 * Error otherwise
3a55b532 13474 **/
ef6fa16b
VG
13475static int __maybe_unused
13476lpfc_pci_suspend_one_s4(struct device *dev_d)
3a55b532 13477{
ef6fa16b 13478 struct Scsi_Host *shost = dev_get_drvdata(dev_d);
3a55b532
JS
13479 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13480
13481 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
75baf696 13482 "2843 PCI device Power Management suspend.\n");
3a55b532
JS
13483
13484 /* Bring down the device */
618a5230 13485 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
3a55b532
JS
13486 lpfc_offline(phba);
13487 kthread_stop(phba->worker_thread);
13488
13489 /* Disable interrupt from device */
da0436e9 13490 lpfc_sli4_disable_intr(phba);
5350d872 13491 lpfc_sli4_queue_destroy(phba);
3a55b532 13492
3a55b532
JS
13493 return 0;
13494}
13495
13496/**
da0436e9 13497 * lpfc_pci_resume_one_s4 - PCI func to resume SLI-4 device for power mgmnt
ef6fa16b 13498 * @dev_d: pointer to device
3a55b532 13499 *
da0436e9
JS
13500 * This routine is called from the kernel's PCI subsystem to support system
13501 * Power Management (PM) to device with SLI-4 interface spac. When PM invokes
13502 * this method, it restores the device's PCI config space state and fully
13503 * reinitializes the device and brings it online. Note that as the driver
13504 * implements the minimum PM requirements to a power-aware driver's PM for
13505 * suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE, FREEZE)
13506 * to the suspend() method call will be treated as SUSPEND and the driver
13507 * will fully reinitialize its device during resume() method call, the device
13508 * will be set to PCI_D0 directly in PCI config space before restoring the
13509 * state.
3a55b532
JS
13510 *
13511 * Return code
3772a991
JS
13512 * 0 - driver suspended the device
13513 * Error otherwise
3a55b532 13514 **/
ef6fa16b
VG
13515static int __maybe_unused
13516lpfc_pci_resume_one_s4(struct device *dev_d)
3a55b532 13517{
ef6fa16b 13518 struct Scsi_Host *shost = dev_get_drvdata(dev_d);
3a55b532 13519 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
5b75da2f 13520 uint32_t intr_mode;
3a55b532
JS
13521 int error;
13522
13523 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
da0436e9 13524 "0292 PCI device Power Management resume.\n");
3a55b532 13525
da0436e9 13526 /* Startup the kernel thread for this host adapter. */
3a55b532
JS
13527 phba->worker_thread = kthread_run(lpfc_do_work, phba,
13528 "lpfc_worker_%d", phba->brd_no);
13529 if (IS_ERR(phba->worker_thread)) {
13530 error = PTR_ERR(phba->worker_thread);
13531 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 13532 "0293 PM resume failed to start worker "
3a55b532
JS
13533 "thread: error=x%x.\n", error);
13534 return error;
13535 }
13536
5b75da2f 13537 /* Configure and enable interrupt */
da0436e9 13538 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
5b75da2f 13539 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 13540 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 13541 "0294 PM resume Failed to enable interrupt\n");
5b75da2f
JS
13542 return -EIO;
13543 } else
13544 phba->intr_mode = intr_mode;
3a55b532
JS
13545
13546 /* Restart HBA and bring it online */
13547 lpfc_sli_brdrestart(phba);
13548 lpfc_online(phba);
13549
5b75da2f
JS
13550 /* Log the current active interrupt mode */
13551 lpfc_log_intr_mode(phba, phba->intr_mode);
13552
3a55b532
JS
13553 return 0;
13554}
13555
75baf696
JS
13556/**
13557 * lpfc_sli4_prep_dev_for_recover - Prepare SLI4 device for pci slot recover
13558 * @phba: pointer to lpfc hba data structure.
13559 *
13560 * This routine is called to prepare the SLI4 device for PCI slot recover. It
13561 * aborts all the outstanding SCSI I/Os to the pci device.
13562 **/
13563static void
13564lpfc_sli4_prep_dev_for_recover(struct lpfc_hba *phba)
13565{
372c187b 13566 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
13567 "2828 PCI channel I/O abort preparing for recovery\n");
13568 /*
13569 * There may be errored I/Os through HBA, abort all I/Os on txcmplq
13570 * and let the SCSI mid-layer to retry them to recover.
13571 */
db55fba8 13572 lpfc_sli_abort_fcp_rings(phba);
75baf696
JS
13573}
13574
13575/**
13576 * lpfc_sli4_prep_dev_for_reset - Prepare SLI4 device for pci slot reset
13577 * @phba: pointer to lpfc hba data structure.
13578 *
13579 * This routine is called to prepare the SLI4 device for PCI slot reset. It
13580 * disables the device interrupt and pci device, and aborts the internal FCP
13581 * pending I/Os.
13582 **/
13583static void
13584lpfc_sli4_prep_dev_for_reset(struct lpfc_hba *phba)
13585{
372c187b 13586 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
13587 "2826 PCI channel disable preparing for reset\n");
13588
13589 /* Block any management I/Os to the device */
618a5230 13590 lpfc_block_mgmt_io(phba, LPFC_MBX_NO_WAIT);
75baf696
JS
13591
13592 /* Block all SCSI devices' I/Os on the host */
13593 lpfc_scsi_dev_block(phba);
13594
c00f62e6
JS
13595 /* Flush all driver's outstanding I/Os as we are to reset */
13596 lpfc_sli_flush_io_rings(phba);
c3725bdc 13597
75baf696
JS
13598 /* stop all timers */
13599 lpfc_stop_hba_timers(phba);
13600
13601 /* Disable interrupt and pci device */
13602 lpfc_sli4_disable_intr(phba);
5350d872 13603 lpfc_sli4_queue_destroy(phba);
75baf696 13604 pci_disable_device(phba->pcidev);
75baf696
JS
13605}
13606
13607/**
13608 * lpfc_sli4_prep_dev_for_perm_failure - Prepare SLI4 dev for pci slot disable
13609 * @phba: pointer to lpfc hba data structure.
13610 *
13611 * This routine is called to prepare the SLI4 device for PCI slot permanently
13612 * disabling. It blocks the SCSI transport layer traffic and flushes the FCP
13613 * pending I/Os.
13614 **/
13615static void
13616lpfc_sli4_prep_dev_for_perm_failure(struct lpfc_hba *phba)
13617{
372c187b 13618 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
13619 "2827 PCI channel permanent disable for failure\n");
13620
13621 /* Block all SCSI devices' I/Os on the host */
13622 lpfc_scsi_dev_block(phba);
13623
13624 /* stop all timers */
13625 lpfc_stop_hba_timers(phba);
13626
c00f62e6
JS
13627 /* Clean up all driver's outstanding I/Os */
13628 lpfc_sli_flush_io_rings(phba);
75baf696
JS
13629}
13630
8d63f375 13631/**
da0436e9 13632 * lpfc_io_error_detected_s4 - Method for handling PCI I/O error to SLI-4 device
e59058c4
JS
13633 * @pdev: pointer to PCI device.
13634 * @state: the current PCI connection state.
8d63f375 13635 *
da0436e9
JS
13636 * This routine is called from the PCI subsystem for error handling to device
13637 * with SLI-4 interface spec. This function is called by the PCI subsystem
13638 * after a PCI bus error affecting this device has been detected. When this
13639 * function is invoked, it will need to stop all the I/Os and interrupt(s)
13640 * to the device. Once that is done, it will return PCI_ERS_RESULT_NEED_RESET
13641 * for the PCI subsystem to perform proper recovery as desired.
e59058c4
JS
13642 *
13643 * Return codes
3772a991
JS
13644 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
13645 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
e59058c4 13646 **/
3772a991 13647static pci_ers_result_t
da0436e9 13648lpfc_io_error_detected_s4(struct pci_dev *pdev, pci_channel_state_t state)
8d63f375 13649{
75baf696
JS
13650 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13651 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13652
13653 switch (state) {
13654 case pci_channel_io_normal:
13655 /* Non-fatal error, prepare for recovery */
13656 lpfc_sli4_prep_dev_for_recover(phba);
13657 return PCI_ERS_RESULT_CAN_RECOVER;
13658 case pci_channel_io_frozen:
13659 /* Fatal error, prepare for slot reset */
13660 lpfc_sli4_prep_dev_for_reset(phba);
13661 return PCI_ERS_RESULT_NEED_RESET;
13662 case pci_channel_io_perm_failure:
13663 /* Permanent failure, prepare for device down */
13664 lpfc_sli4_prep_dev_for_perm_failure(phba);
13665 return PCI_ERS_RESULT_DISCONNECT;
13666 default:
13667 /* Unknown state, prepare and request slot reset */
372c187b 13668 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
13669 "2825 Unknown PCI error state: x%x\n", state);
13670 lpfc_sli4_prep_dev_for_reset(phba);
13671 return PCI_ERS_RESULT_NEED_RESET;
13672 }
8d63f375
LV
13673}
13674
13675/**
da0436e9 13676 * lpfc_io_slot_reset_s4 - Method for restart PCI SLI-4 device from scratch
e59058c4
JS
13677 * @pdev: pointer to PCI device.
13678 *
da0436e9
JS
13679 * This routine is called from the PCI subsystem for error handling to device
13680 * with SLI-4 interface spec. It is called after PCI bus has been reset to
13681 * restart the PCI card from scratch, as if from a cold-boot. During the
13682 * PCI subsystem error recovery, after the driver returns
3772a991 13683 * PCI_ERS_RESULT_NEED_RESET, the PCI subsystem will perform proper error
da0436e9
JS
13684 * recovery and then call this routine before calling the .resume method to
13685 * recover the device. This function will initialize the HBA device, enable
13686 * the interrupt, but it will just put the HBA to offline state without
13687 * passing any I/O traffic.
8d63f375 13688 *
e59058c4 13689 * Return codes
3772a991
JS
13690 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
13691 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
8d63f375 13692 */
3772a991 13693static pci_ers_result_t
da0436e9 13694lpfc_io_slot_reset_s4(struct pci_dev *pdev)
8d63f375 13695{
75baf696
JS
13696 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13697 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13698 struct lpfc_sli *psli = &phba->sli;
13699 uint32_t intr_mode;
13700
13701 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
13702 if (pci_enable_device_mem(pdev)) {
13703 printk(KERN_ERR "lpfc: Cannot re-enable "
13704 "PCI device after reset.\n");
13705 return PCI_ERS_RESULT_DISCONNECT;
13706 }
13707
13708 pci_restore_state(pdev);
0a96e975
JS
13709
13710 /*
13711 * As the new kernel behavior of pci_restore_state() API call clears
13712 * device saved_state flag, need to save the restored state again.
13713 */
13714 pci_save_state(pdev);
13715
75baf696
JS
13716 if (pdev->is_busmaster)
13717 pci_set_master(pdev);
13718
13719 spin_lock_irq(&phba->hbalock);
13720 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
13721 spin_unlock_irq(&phba->hbalock);
13722
13723 /* Configure and enable interrupt */
13724 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
13725 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 13726 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
13727 "2824 Cannot re-enable interrupt after "
13728 "slot reset.\n");
13729 return PCI_ERS_RESULT_DISCONNECT;
13730 } else
13731 phba->intr_mode = intr_mode;
13732
13733 /* Log the current active interrupt mode */
13734 lpfc_log_intr_mode(phba, phba->intr_mode);
13735
8d63f375
LV
13736 return PCI_ERS_RESULT_RECOVERED;
13737}
13738
13739/**
da0436e9 13740 * lpfc_io_resume_s4 - Method for resuming PCI I/O operation to SLI-4 device
e59058c4 13741 * @pdev: pointer to PCI device
8d63f375 13742 *
3772a991 13743 * This routine is called from the PCI subsystem for error handling to device
da0436e9 13744 * with SLI-4 interface spec. It is called when kernel error recovery tells
3772a991
JS
13745 * the lpfc driver that it is ok to resume normal PCI operation after PCI bus
13746 * error recovery. After this call, traffic can start to flow from this device
13747 * again.
da0436e9 13748 **/
3772a991 13749static void
da0436e9 13750lpfc_io_resume_s4(struct pci_dev *pdev)
8d63f375 13751{
75baf696
JS
13752 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13753 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13754
13755 /*
13756 * In case of slot reset, as function reset is performed through
13757 * mailbox command which needs DMA to be enabled, this operation
13758 * has to be moved to the io resume phase. Taking device offline
13759 * will perform the necessary cleanup.
13760 */
13761 if (!(phba->sli.sli_flag & LPFC_SLI_ACTIVE)) {
13762 /* Perform device reset */
618a5230 13763 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
75baf696
JS
13764 lpfc_offline(phba);
13765 lpfc_sli_brdrestart(phba);
13766 /* Bring the device back online */
13767 lpfc_online(phba);
13768 }
8d63f375
LV
13769}
13770
3772a991
JS
13771/**
13772 * lpfc_pci_probe_one - lpfc PCI probe func to reg dev to PCI subsystem
13773 * @pdev: pointer to PCI device
13774 * @pid: pointer to PCI device identifier
13775 *
13776 * This routine is to be registered to the kernel's PCI subsystem. When an
13777 * Emulex HBA device is presented on PCI bus, the kernel PCI subsystem looks
13778 * at PCI device-specific information of the device and driver to see if the
13779 * driver state that it can support this kind of device. If the match is
13780 * successful, the driver core invokes this routine. This routine dispatches
13781 * the action to the proper SLI-3 or SLI-4 device probing routine, which will
13782 * do all the initialization that it needs to do to handle the HBA device
13783 * properly.
13784 *
13785 * Return code
13786 * 0 - driver can claim the device
13787 * negative value - driver can not claim the device
13788 **/
6f039790 13789static int
3772a991
JS
13790lpfc_pci_probe_one(struct pci_dev *pdev, const struct pci_device_id *pid)
13791{
13792 int rc;
8fa38513 13793 struct lpfc_sli_intf intf;
3772a991 13794
28baac74 13795 if (pci_read_config_dword(pdev, LPFC_SLI_INTF, &intf.word0))
3772a991
JS
13796 return -ENODEV;
13797
8fa38513 13798 if ((bf_get(lpfc_sli_intf_valid, &intf) == LPFC_SLI_INTF_VALID) &&
28baac74 13799 (bf_get(lpfc_sli_intf_slirev, &intf) == LPFC_SLI_INTF_REV_SLI4))
da0436e9 13800 rc = lpfc_pci_probe_one_s4(pdev, pid);
8fa38513 13801 else
3772a991 13802 rc = lpfc_pci_probe_one_s3(pdev, pid);
8fa38513 13803
3772a991
JS
13804 return rc;
13805}
13806
13807/**
13808 * lpfc_pci_remove_one - lpfc PCI func to unreg dev from PCI subsystem
13809 * @pdev: pointer to PCI device
13810 *
13811 * This routine is to be registered to the kernel's PCI subsystem. When an
13812 * Emulex HBA is removed from PCI bus, the driver core invokes this routine.
13813 * This routine dispatches the action to the proper SLI-3 or SLI-4 device
13814 * remove routine, which will perform all the necessary cleanup for the
13815 * device to be removed from the PCI subsystem properly.
13816 **/
6f039790 13817static void
3772a991
JS
13818lpfc_pci_remove_one(struct pci_dev *pdev)
13819{
13820 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13821 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13822
13823 switch (phba->pci_dev_grp) {
13824 case LPFC_PCI_DEV_LP:
13825 lpfc_pci_remove_one_s3(pdev);
13826 break;
da0436e9
JS
13827 case LPFC_PCI_DEV_OC:
13828 lpfc_pci_remove_one_s4(pdev);
13829 break;
3772a991 13830 default:
372c187b 13831 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
13832 "1424 Invalid PCI device group: 0x%x\n",
13833 phba->pci_dev_grp);
13834 break;
13835 }
13836 return;
13837}
13838
13839/**
13840 * lpfc_pci_suspend_one - lpfc PCI func to suspend dev for power management
ef6fa16b 13841 * @dev: pointer to device
3772a991
JS
13842 *
13843 * This routine is to be registered to the kernel's PCI subsystem to support
13844 * system Power Management (PM). When PM invokes this method, it dispatches
13845 * the action to the proper SLI-3 or SLI-4 device suspend routine, which will
13846 * suspend the device.
13847 *
13848 * Return code
13849 * 0 - driver suspended the device
13850 * Error otherwise
13851 **/
ef6fa16b
VG
13852static int __maybe_unused
13853lpfc_pci_suspend_one(struct device *dev)
3772a991 13854{
ef6fa16b 13855 struct Scsi_Host *shost = dev_get_drvdata(dev);
3772a991
JS
13856 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13857 int rc = -ENODEV;
13858
13859 switch (phba->pci_dev_grp) {
13860 case LPFC_PCI_DEV_LP:
ef6fa16b 13861 rc = lpfc_pci_suspend_one_s3(dev);
3772a991 13862 break;
da0436e9 13863 case LPFC_PCI_DEV_OC:
ef6fa16b 13864 rc = lpfc_pci_suspend_one_s4(dev);
da0436e9 13865 break;
3772a991 13866 default:
372c187b 13867 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
13868 "1425 Invalid PCI device group: 0x%x\n",
13869 phba->pci_dev_grp);
13870 break;
13871 }
13872 return rc;
13873}
13874
13875/**
13876 * lpfc_pci_resume_one - lpfc PCI func to resume dev for power management
ef6fa16b 13877 * @dev: pointer to device
3772a991
JS
13878 *
13879 * This routine is to be registered to the kernel's PCI subsystem to support
13880 * system Power Management (PM). When PM invokes this method, it dispatches
13881 * the action to the proper SLI-3 or SLI-4 device resume routine, which will
13882 * resume the device.
13883 *
13884 * Return code
13885 * 0 - driver suspended the device
13886 * Error otherwise
13887 **/
ef6fa16b
VG
13888static int __maybe_unused
13889lpfc_pci_resume_one(struct device *dev)
3772a991 13890{
ef6fa16b 13891 struct Scsi_Host *shost = dev_get_drvdata(dev);
3772a991
JS
13892 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13893 int rc = -ENODEV;
13894
13895 switch (phba->pci_dev_grp) {
13896 case LPFC_PCI_DEV_LP:
ef6fa16b 13897 rc = lpfc_pci_resume_one_s3(dev);
3772a991 13898 break;
da0436e9 13899 case LPFC_PCI_DEV_OC:
ef6fa16b 13900 rc = lpfc_pci_resume_one_s4(dev);
da0436e9 13901 break;
3772a991 13902 default:
372c187b 13903 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
13904 "1426 Invalid PCI device group: 0x%x\n",
13905 phba->pci_dev_grp);
13906 break;
13907 }
13908 return rc;
13909}
13910
13911/**
13912 * lpfc_io_error_detected - lpfc method for handling PCI I/O error
13913 * @pdev: pointer to PCI device.
13914 * @state: the current PCI connection state.
13915 *
13916 * This routine is registered to the PCI subsystem for error handling. This
13917 * function is called by the PCI subsystem after a PCI bus error affecting
13918 * this device has been detected. When this routine is invoked, it dispatches
13919 * the action to the proper SLI-3 or SLI-4 device error detected handling
13920 * routine, which will perform the proper error detected operation.
13921 *
13922 * Return codes
13923 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
13924 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
13925 **/
13926static pci_ers_result_t
13927lpfc_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
13928{
13929 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13930 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13931 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
13932
13933 switch (phba->pci_dev_grp) {
13934 case LPFC_PCI_DEV_LP:
13935 rc = lpfc_io_error_detected_s3(pdev, state);
13936 break;
da0436e9
JS
13937 case LPFC_PCI_DEV_OC:
13938 rc = lpfc_io_error_detected_s4(pdev, state);
13939 break;
3772a991 13940 default:
372c187b 13941 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
13942 "1427 Invalid PCI device group: 0x%x\n",
13943 phba->pci_dev_grp);
13944 break;
13945 }
13946 return rc;
13947}
13948
13949/**
13950 * lpfc_io_slot_reset - lpfc method for restart PCI dev from scratch
13951 * @pdev: pointer to PCI device.
13952 *
13953 * This routine is registered to the PCI subsystem for error handling. This
13954 * function is called after PCI bus has been reset to restart the PCI card
13955 * from scratch, as if from a cold-boot. When this routine is invoked, it
13956 * dispatches the action to the proper SLI-3 or SLI-4 device reset handling
13957 * routine, which will perform the proper device reset.
13958 *
13959 * Return codes
13960 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
13961 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
13962 **/
13963static pci_ers_result_t
13964lpfc_io_slot_reset(struct pci_dev *pdev)
13965{
13966 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13967 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13968 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
13969
13970 switch (phba->pci_dev_grp) {
13971 case LPFC_PCI_DEV_LP:
13972 rc = lpfc_io_slot_reset_s3(pdev);
13973 break;
da0436e9
JS
13974 case LPFC_PCI_DEV_OC:
13975 rc = lpfc_io_slot_reset_s4(pdev);
13976 break;
3772a991 13977 default:
372c187b 13978 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
13979 "1428 Invalid PCI device group: 0x%x\n",
13980 phba->pci_dev_grp);
13981 break;
13982 }
13983 return rc;
13984}
13985
13986/**
13987 * lpfc_io_resume - lpfc method for resuming PCI I/O operation
13988 * @pdev: pointer to PCI device
13989 *
13990 * This routine is registered to the PCI subsystem for error handling. It
13991 * is called when kernel error recovery tells the lpfc driver that it is
13992 * OK to resume normal PCI operation after PCI bus error recovery. When
13993 * this routine is invoked, it dispatches the action to the proper SLI-3
13994 * or SLI-4 device io_resume routine, which will resume the device operation.
13995 **/
13996static void
13997lpfc_io_resume(struct pci_dev *pdev)
13998{
13999 struct Scsi_Host *shost = pci_get_drvdata(pdev);
14000 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
14001
14002 switch (phba->pci_dev_grp) {
14003 case LPFC_PCI_DEV_LP:
14004 lpfc_io_resume_s3(pdev);
14005 break;
da0436e9
JS
14006 case LPFC_PCI_DEV_OC:
14007 lpfc_io_resume_s4(pdev);
14008 break;
3772a991 14009 default:
372c187b 14010 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
14011 "1429 Invalid PCI device group: 0x%x\n",
14012 phba->pci_dev_grp);
14013 break;
14014 }
14015 return;
14016}
14017
1ba981fd
JS
14018/**
14019 * lpfc_sli4_oas_verify - Verify OAS is supported by this adapter
14020 * @phba: pointer to lpfc hba data structure.
14021 *
14022 * This routine checks to see if OAS is supported for this adapter. If
14023 * supported, the configure Flash Optimized Fabric flag is set. Otherwise,
14024 * the enable oas flag is cleared and the pool created for OAS device data
14025 * is destroyed.
14026 *
14027 **/
c7092975 14028static void
1ba981fd
JS
14029lpfc_sli4_oas_verify(struct lpfc_hba *phba)
14030{
14031
14032 if (!phba->cfg_EnableXLane)
14033 return;
14034
14035 if (phba->sli4_hba.pc_sli4_params.oas_supported) {
14036 phba->cfg_fof = 1;
14037 } else {
f38fa0bb 14038 phba->cfg_fof = 0;
c3e5aac3 14039 mempool_destroy(phba->device_data_mem_pool);
1ba981fd
JS
14040 phba->device_data_mem_pool = NULL;
14041 }
14042
14043 return;
14044}
14045
d2cc9bcd
JS
14046/**
14047 * lpfc_sli4_ras_init - Verify RAS-FW log is supported by this adapter
14048 * @phba: pointer to lpfc hba data structure.
14049 *
14050 * This routine checks to see if RAS is supported by the adapter. Check the
14051 * function through which RAS support enablement is to be done.
14052 **/
14053void
14054lpfc_sli4_ras_init(struct lpfc_hba *phba)
14055{
14056 switch (phba->pcidev->device) {
14057 case PCI_DEVICE_ID_LANCER_G6_FC:
14058 case PCI_DEVICE_ID_LANCER_G7_FC:
14059 phba->ras_fwlog.ras_hwsupport = true;
cb34990b
JS
14060 if (phba->cfg_ras_fwlog_func == PCI_FUNC(phba->pcidev->devfn) &&
14061 phba->cfg_ras_fwlog_buffsize)
d2cc9bcd
JS
14062 phba->ras_fwlog.ras_enabled = true;
14063 else
14064 phba->ras_fwlog.ras_enabled = false;
14065 break;
14066 default:
14067 phba->ras_fwlog.ras_hwsupport = false;
14068 }
14069}
14070
1ba981fd 14071
dea3101e 14072MODULE_DEVICE_TABLE(pci, lpfc_id_table);
14073
a55b2d21 14074static const struct pci_error_handlers lpfc_err_handler = {
8d63f375
LV
14075 .error_detected = lpfc_io_error_detected,
14076 .slot_reset = lpfc_io_slot_reset,
14077 .resume = lpfc_io_resume,
14078};
14079
ef6fa16b
VG
14080static SIMPLE_DEV_PM_OPS(lpfc_pci_pm_ops_one,
14081 lpfc_pci_suspend_one,
14082 lpfc_pci_resume_one);
14083
dea3101e 14084static struct pci_driver lpfc_driver = {
14085 .name = LPFC_DRIVER_NAME,
14086 .id_table = lpfc_id_table,
14087 .probe = lpfc_pci_probe_one,
6f039790 14088 .remove = lpfc_pci_remove_one,
85e8a239 14089 .shutdown = lpfc_pci_remove_one,
ef6fa16b 14090 .driver.pm = &lpfc_pci_pm_ops_one,
2e0fef85 14091 .err_handler = &lpfc_err_handler,
dea3101e 14092};
14093
3ef6d24c 14094static const struct file_operations lpfc_mgmt_fop = {
858feacd 14095 .owner = THIS_MODULE,
3ef6d24c
JS
14096};
14097
14098static struct miscdevice lpfc_mgmt_dev = {
14099 .minor = MISC_DYNAMIC_MINOR,
14100 .name = "lpfcmgmt",
14101 .fops = &lpfc_mgmt_fop,
14102};
14103
e59058c4 14104/**
3621a710 14105 * lpfc_init - lpfc module initialization routine
e59058c4
JS
14106 *
14107 * This routine is to be invoked when the lpfc module is loaded into the
14108 * kernel. The special kernel macro module_init() is used to indicate the
14109 * role of this routine to the kernel as lpfc module entry point.
14110 *
14111 * Return codes
14112 * 0 - successful
14113 * -ENOMEM - FC attach transport failed
14114 * all others - failed
14115 */
dea3101e 14116static int __init
14117lpfc_init(void)
14118{
14119 int error = 0;
14120
bc2736e9
AB
14121 pr_info(LPFC_MODULE_DESC "\n");
14122 pr_info(LPFC_COPYRIGHT "\n");
dea3101e 14123
3ef6d24c
JS
14124 error = misc_register(&lpfc_mgmt_dev);
14125 if (error)
14126 printk(KERN_ERR "Could not register lpfcmgmt device, "
14127 "misc_register returned with status %d", error);
14128
1eaff536 14129 error = -ENOMEM;
458c083e
JS
14130 lpfc_transport_functions.vport_create = lpfc_vport_create;
14131 lpfc_transport_functions.vport_delete = lpfc_vport_delete;
dea3101e 14132 lpfc_transport_template =
14133 fc_attach_transport(&lpfc_transport_functions);
7ee5d43e 14134 if (lpfc_transport_template == NULL)
1eaff536 14135 goto unregister;
458c083e
JS
14136 lpfc_vport_transport_template =
14137 fc_attach_transport(&lpfc_vport_transport_functions);
14138 if (lpfc_vport_transport_template == NULL) {
14139 fc_release_transport(lpfc_transport_template);
1eaff536 14140 goto unregister;
7ee5d43e 14141 }
840a4701 14142 lpfc_wqe_cmd_template();
bd3061ba 14143 lpfc_nvmet_cmd_template();
7bb03bbf
JS
14144
14145 /* Initialize in case vector mapping is needed */
2ea259ee 14146 lpfc_present_cpu = num_present_cpus();
7bb03bbf 14147
93a4d6f4
JS
14148 error = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
14149 "lpfc/sli4:online",
14150 lpfc_cpu_online, lpfc_cpu_offline);
14151 if (error < 0)
14152 goto cpuhp_failure;
14153 lpfc_cpuhp_state = error;
14154
dea3101e 14155 error = pci_register_driver(&lpfc_driver);
93a4d6f4
JS
14156 if (error)
14157 goto unwind;
14158
14159 return error;
14160
14161unwind:
14162 cpuhp_remove_multi_state(lpfc_cpuhp_state);
14163cpuhp_failure:
14164 fc_release_transport(lpfc_transport_template);
14165 fc_release_transport(lpfc_vport_transport_template);
1eaff536
JX
14166unregister:
14167 misc_deregister(&lpfc_mgmt_dev);
dea3101e 14168
14169 return error;
14170}
14171
372c187b
DK
14172void lpfc_dmp_dbg(struct lpfc_hba *phba)
14173{
14174 unsigned int start_idx;
14175 unsigned int dbg_cnt;
14176 unsigned int temp_idx;
14177 int i;
14178 int j = 0;
14179 unsigned long rem_nsec;
14180
14181 if (phba->cfg_log_verbose)
14182 return;
14183
14184 if (atomic_cmpxchg(&phba->dbg_log_dmping, 0, 1) != 0)
14185 return;
14186
14187 start_idx = (unsigned int)atomic_read(&phba->dbg_log_idx) % DBG_LOG_SZ;
14188 dbg_cnt = (unsigned int)atomic_read(&phba->dbg_log_cnt);
14189 temp_idx = start_idx;
14190 if (dbg_cnt >= DBG_LOG_SZ) {
14191 dbg_cnt = DBG_LOG_SZ;
14192 temp_idx -= 1;
14193 } else {
14194 if ((start_idx + dbg_cnt) > (DBG_LOG_SZ - 1)) {
14195 temp_idx = (start_idx + dbg_cnt) % DBG_LOG_SZ;
14196 } else {
77dd7d7b 14197 if (start_idx < dbg_cnt)
372c187b 14198 start_idx = DBG_LOG_SZ - (dbg_cnt - start_idx);
77dd7d7b 14199 else
372c187b 14200 start_idx -= dbg_cnt;
372c187b
DK
14201 }
14202 }
14203 dev_info(&phba->pcidev->dev, "start %d end %d cnt %d\n",
14204 start_idx, temp_idx, dbg_cnt);
14205
14206 for (i = 0; i < dbg_cnt; i++) {
14207 if ((start_idx + i) < DBG_LOG_SZ)
77dd7d7b 14208 temp_idx = (start_idx + i) % DBG_LOG_SZ;
372c187b
DK
14209 else
14210 temp_idx = j++;
14211 rem_nsec = do_div(phba->dbg_log[temp_idx].t_ns, NSEC_PER_SEC);
14212 dev_info(&phba->pcidev->dev, "%d: [%5lu.%06lu] %s",
14213 temp_idx,
14214 (unsigned long)phba->dbg_log[temp_idx].t_ns,
14215 rem_nsec / 1000,
14216 phba->dbg_log[temp_idx].log);
14217 }
14218 atomic_set(&phba->dbg_log_cnt, 0);
14219 atomic_set(&phba->dbg_log_dmping, 0);
14220}
14221
7fa03c77 14222__printf(2, 3)
372c187b
DK
14223void lpfc_dbg_print(struct lpfc_hba *phba, const char *fmt, ...)
14224{
14225 unsigned int idx;
14226 va_list args;
14227 int dbg_dmping = atomic_read(&phba->dbg_log_dmping);
14228 struct va_format vaf;
14229
14230
14231 va_start(args, fmt);
14232 if (unlikely(dbg_dmping)) {
14233 vaf.fmt = fmt;
14234 vaf.va = &args;
14235 dev_info(&phba->pcidev->dev, "%pV", &vaf);
14236 va_end(args);
14237 return;
14238 }
14239 idx = (unsigned int)atomic_fetch_add(1, &phba->dbg_log_idx) %
14240 DBG_LOG_SZ;
14241
14242 atomic_inc(&phba->dbg_log_cnt);
14243
14244 vscnprintf(phba->dbg_log[idx].log,
14245 sizeof(phba->dbg_log[idx].log), fmt, args);
14246 va_end(args);
14247
14248 phba->dbg_log[idx].t_ns = local_clock();
14249}
14250
e59058c4 14251/**
3621a710 14252 * lpfc_exit - lpfc module removal routine
e59058c4
JS
14253 *
14254 * This routine is invoked when the lpfc module is removed from the kernel.
14255 * The special kernel macro module_exit() is used to indicate the role of
14256 * this routine to the kernel as lpfc module exit point.
14257 */
dea3101e 14258static void __exit
14259lpfc_exit(void)
14260{
3ef6d24c 14261 misc_deregister(&lpfc_mgmt_dev);
dea3101e 14262 pci_unregister_driver(&lpfc_driver);
93a4d6f4 14263 cpuhp_remove_multi_state(lpfc_cpuhp_state);
dea3101e 14264 fc_release_transport(lpfc_transport_template);
458c083e 14265 fc_release_transport(lpfc_vport_transport_template);
7973967f 14266 idr_destroy(&lpfc_hba_index);
dea3101e 14267}
14268
14269module_init(lpfc_init);
14270module_exit(lpfc_exit);
14271MODULE_LICENSE("GPL");
14272MODULE_DESCRIPTION(LPFC_MODULE_DESC);
d080abe0 14273MODULE_AUTHOR("Broadcom");
dea3101e 14274MODULE_VERSION("0:" LPFC_DRIVER_VERSION);