scsi: be2iscsi: Mark beiscsi_attrs with static keyword
[linux-2.6-block.git] / drivers / scsi / lpfc / lpfc_init.c
CommitLineData
dea3101e 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
145e5a8a 4 * Copyright (C) 2017-2020 Broadcom. All Rights Reserved. The term *
3e21d1cb 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
50611577 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
c44ce173 7 * EMULEX and SLI are trademarks of Emulex. *
d080abe0 8 * www.broadcom.com *
c44ce173 9 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
dea3101e 10 * *
11 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC
12 * modify it under the terms of version 2 of the GNU General *
13 * Public License as published by the Free Software Foundation. *
14 * This program is distributed in the hope that it will be useful. *
15 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
16 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
18 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
19 * TO BE LEGALLY INVALID. See the GNU General Public License for *
20 * more details, a copy of which can be found in the file COPYING *
21 * included with this package. *
dea3101e 22 *******************************************************************/
23
dea3101e 24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/idr.h>
28#include <linux/interrupt.h>
acf3368f 29#include <linux/module.h>
dea3101e 30#include <linux/kthread.h>
31#include <linux/pci.h>
32#include <linux/spinlock.h>
92d7f7b0 33#include <linux/ctype.h>
0d878419 34#include <linux/aer.h>
5a0e3ad6 35#include <linux/slab.h>
52d52440 36#include <linux/firmware.h>
3ef6d24c 37#include <linux/miscdevice.h>
7bb03bbf 38#include <linux/percpu.h>
895427bd 39#include <linux/msi.h>
6a828b0f 40#include <linux/irq.h>
286871a6 41#include <linux/bitops.h>
31f06d2e 42#include <linux/crash_dump.h>
dcaa2136 43#include <linux/cpu.h>
93a4d6f4 44#include <linux/cpuhotplug.h>
dea3101e 45
91886523 46#include <scsi/scsi.h>
dea3101e 47#include <scsi/scsi_device.h>
48#include <scsi/scsi_host.h>
49#include <scsi/scsi_transport_fc.h>
86c67379
JS
50#include <scsi/scsi_tcq.h>
51#include <scsi/fc/fc_fs.h>
52
da0436e9 53#include "lpfc_hw4.h"
dea3101e 54#include "lpfc_hw.h"
55#include "lpfc_sli.h"
da0436e9 56#include "lpfc_sli4.h"
ea2151b4 57#include "lpfc_nl.h"
dea3101e 58#include "lpfc_disc.h"
dea3101e 59#include "lpfc.h"
895427bd
JS
60#include "lpfc_scsi.h"
61#include "lpfc_nvme.h"
dea3101e 62#include "lpfc_logmsg.h"
63#include "lpfc_crtn.h"
92d7f7b0 64#include "lpfc_vport.h"
dea3101e 65#include "lpfc_version.h"
12f44457 66#include "lpfc_ids.h"
dea3101e 67
93a4d6f4 68static enum cpuhp_state lpfc_cpuhp_state;
7bb03bbf 69/* Used when mapping IRQ vectors in a driver centric manner */
d7b761b0 70static uint32_t lpfc_present_cpu;
7bb03bbf 71
93a4d6f4
JS
72static void __lpfc_cpuhp_remove(struct lpfc_hba *phba);
73static void lpfc_cpuhp_remove(struct lpfc_hba *phba);
74static void lpfc_cpuhp_add(struct lpfc_hba *phba);
dea3101e 75static void lpfc_get_hba_model_desc(struct lpfc_hba *, uint8_t *, uint8_t *);
76static int lpfc_post_rcv_buf(struct lpfc_hba *);
5350d872 77static int lpfc_sli4_queue_verify(struct lpfc_hba *);
da0436e9
JS
78static int lpfc_create_bootstrap_mbox(struct lpfc_hba *);
79static int lpfc_setup_endian_order(struct lpfc_hba *);
da0436e9 80static void lpfc_destroy_bootstrap_mbox(struct lpfc_hba *);
8a9d2e80 81static void lpfc_free_els_sgl_list(struct lpfc_hba *);
f358dd0c 82static void lpfc_free_nvmet_sgl_list(struct lpfc_hba *);
8a9d2e80 83static void lpfc_init_sgl_list(struct lpfc_hba *);
da0436e9
JS
84static int lpfc_init_active_sgl_array(struct lpfc_hba *);
85static void lpfc_free_active_sgl(struct lpfc_hba *);
86static int lpfc_hba_down_post_s3(struct lpfc_hba *phba);
87static int lpfc_hba_down_post_s4(struct lpfc_hba *phba);
88static int lpfc_sli4_cq_event_pool_create(struct lpfc_hba *);
89static void lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *);
90static void lpfc_sli4_cq_event_release_all(struct lpfc_hba *);
618a5230
JS
91static void lpfc_sli4_disable_intr(struct lpfc_hba *);
92static uint32_t lpfc_sli4_enable_intr(struct lpfc_hba *, uint32_t);
1ba981fd 93static void lpfc_sli4_oas_verify(struct lpfc_hba *phba);
6a828b0f 94static uint16_t lpfc_find_cpu_handle(struct lpfc_hba *, uint16_t, int);
aa6ff309 95static void lpfc_setup_bg(struct lpfc_hba *, struct Scsi_Host *);
dea3101e 96
97static struct scsi_transport_template *lpfc_transport_template = NULL;
92d7f7b0 98static struct scsi_transport_template *lpfc_vport_transport_template = NULL;
dea3101e 99static DEFINE_IDR(lpfc_hba_index);
f358dd0c 100#define LPFC_NVMET_BUF_POST 254
dea3101e 101
e59058c4 102/**
3621a710 103 * lpfc_config_port_prep - Perform lpfc initialization prior to config port
e59058c4
JS
104 * @phba: pointer to lpfc hba data structure.
105 *
106 * This routine will do LPFC initialization prior to issuing the CONFIG_PORT
107 * mailbox command. It retrieves the revision information from the HBA and
108 * collects the Vital Product Data (VPD) about the HBA for preparing the
109 * configuration of the HBA.
110 *
111 * Return codes:
112 * 0 - success.
113 * -ERESTART - requests the SLI layer to reset the HBA and try again.
114 * Any other value - indicates an error.
115 **/
dea3101e 116int
2e0fef85 117lpfc_config_port_prep(struct lpfc_hba *phba)
dea3101e 118{
119 lpfc_vpd_t *vp = &phba->vpd;
120 int i = 0, rc;
121 LPFC_MBOXQ_t *pmb;
122 MAILBOX_t *mb;
123 char *lpfc_vpd_data = NULL;
124 uint16_t offset = 0;
125 static char licensed[56] =
126 "key unlock for use with gnu public licensed code only\0";
65a29c16 127 static int init_key = 1;
dea3101e 128
129 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
130 if (!pmb) {
2e0fef85 131 phba->link_state = LPFC_HBA_ERROR;
dea3101e 132 return -ENOMEM;
133 }
134
04c68496 135 mb = &pmb->u.mb;
2e0fef85 136 phba->link_state = LPFC_INIT_MBX_CMDS;
dea3101e 137
138 if (lpfc_is_LC_HBA(phba->pcidev->device)) {
65a29c16
JS
139 if (init_key) {
140 uint32_t *ptext = (uint32_t *) licensed;
dea3101e 141
65a29c16
JS
142 for (i = 0; i < 56; i += sizeof (uint32_t), ptext++)
143 *ptext = cpu_to_be32(*ptext);
144 init_key = 0;
145 }
dea3101e 146
147 lpfc_read_nv(phba, pmb);
148 memset((char*)mb->un.varRDnvp.rsvd3, 0,
149 sizeof (mb->un.varRDnvp.rsvd3));
150 memcpy((char*)mb->un.varRDnvp.rsvd3, licensed,
151 sizeof (licensed));
152
153 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
154
155 if (rc != MBX_SUCCESS) {
372c187b 156 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 157 "0324 Config Port initialization "
dea3101e 158 "error, mbxCmd x%x READ_NVPARM, "
159 "mbxStatus x%x\n",
dea3101e 160 mb->mbxCommand, mb->mbxStatus);
161 mempool_free(pmb, phba->mbox_mem_pool);
162 return -ERESTART;
163 }
164 memcpy(phba->wwnn, (char *)mb->un.varRDnvp.nodename,
2e0fef85
JS
165 sizeof(phba->wwnn));
166 memcpy(phba->wwpn, (char *)mb->un.varRDnvp.portname,
167 sizeof(phba->wwpn));
dea3101e 168 }
169
dfb75133
MW
170 /*
171 * Clear all option bits except LPFC_SLI3_BG_ENABLED,
172 * which was already set in lpfc_get_cfgparam()
173 */
174 phba->sli3_options &= (uint32_t)LPFC_SLI3_BG_ENABLED;
92d7f7b0 175
dea3101e 176 /* Setup and issue mailbox READ REV command */
177 lpfc_read_rev(phba, pmb);
178 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
179 if (rc != MBX_SUCCESS) {
372c187b 180 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 181 "0439 Adapter failed to init, mbxCmd x%x "
dea3101e 182 "READ_REV, mbxStatus x%x\n",
dea3101e 183 mb->mbxCommand, mb->mbxStatus);
184 mempool_free( pmb, phba->mbox_mem_pool);
185 return -ERESTART;
186 }
187
92d7f7b0 188
1de933f3
JSEC
189 /*
190 * The value of rr must be 1 since the driver set the cv field to 1.
191 * This setting requires the FW to set all revision fields.
dea3101e 192 */
1de933f3 193 if (mb->un.varRdRev.rr == 0) {
dea3101e 194 vp->rev.rBit = 0;
372c187b 195 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011
JS
196 "0440 Adapter failed to init, READ_REV has "
197 "missing revision information.\n");
dea3101e 198 mempool_free(pmb, phba->mbox_mem_pool);
199 return -ERESTART;
dea3101e 200 }
201
495a714c
JS
202 if (phba->sli_rev == 3 && !mb->un.varRdRev.v3rsp) {
203 mempool_free(pmb, phba->mbox_mem_pool);
ed957684 204 return -EINVAL;
495a714c 205 }
ed957684 206
dea3101e 207 /* Save information as VPD data */
1de933f3 208 vp->rev.rBit = 1;
92d7f7b0 209 memcpy(&vp->sli3Feat, &mb->un.varRdRev.sli3Feat, sizeof(uint32_t));
1de933f3
JSEC
210 vp->rev.sli1FwRev = mb->un.varRdRev.sli1FwRev;
211 memcpy(vp->rev.sli1FwName, (char*) mb->un.varRdRev.sli1FwName, 16);
212 vp->rev.sli2FwRev = mb->un.varRdRev.sli2FwRev;
213 memcpy(vp->rev.sli2FwName, (char *) mb->un.varRdRev.sli2FwName, 16);
dea3101e 214 vp->rev.biuRev = mb->un.varRdRev.biuRev;
215 vp->rev.smRev = mb->un.varRdRev.smRev;
216 vp->rev.smFwRev = mb->un.varRdRev.un.smFwRev;
217 vp->rev.endecRev = mb->un.varRdRev.endecRev;
218 vp->rev.fcphHigh = mb->un.varRdRev.fcphHigh;
219 vp->rev.fcphLow = mb->un.varRdRev.fcphLow;
220 vp->rev.feaLevelHigh = mb->un.varRdRev.feaLevelHigh;
221 vp->rev.feaLevelLow = mb->un.varRdRev.feaLevelLow;
222 vp->rev.postKernRev = mb->un.varRdRev.postKernRev;
223 vp->rev.opFwRev = mb->un.varRdRev.opFwRev;
224
92d7f7b0
JS
225 /* If the sli feature level is less then 9, we must
226 * tear down all RPIs and VPIs on link down if NPIV
227 * is enabled.
228 */
229 if (vp->rev.feaLevelHigh < 9)
230 phba->sli3_options |= LPFC_SLI3_VPORT_TEARDOWN;
231
dea3101e 232 if (lpfc_is_LC_HBA(phba->pcidev->device))
233 memcpy(phba->RandomData, (char *)&mb->un.varWords[24],
234 sizeof (phba->RandomData));
235
dea3101e 236 /* Get adapter VPD information */
dea3101e 237 lpfc_vpd_data = kmalloc(DMP_VPD_SIZE, GFP_KERNEL);
238 if (!lpfc_vpd_data)
d7c255b2 239 goto out_free_mbox;
dea3101e 240 do {
a0c87cbd 241 lpfc_dump_mem(phba, pmb, offset, DMP_REGION_VPD);
dea3101e 242 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
243
244 if (rc != MBX_SUCCESS) {
245 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011 246 "0441 VPD not present on adapter, "
dea3101e 247 "mbxCmd x%x DUMP VPD, mbxStatus x%x\n",
dea3101e 248 mb->mbxCommand, mb->mbxStatus);
74b72a59 249 mb->un.varDmp.word_cnt = 0;
dea3101e 250 }
04c68496
JS
251 /* dump mem may return a zero when finished or we got a
252 * mailbox error, either way we are done.
253 */
254 if (mb->un.varDmp.word_cnt == 0)
255 break;
d91e3abb
DK
256
257 i = mb->un.varDmp.word_cnt * sizeof(uint32_t);
258 if (offset + i > DMP_VPD_SIZE)
259 i = DMP_VPD_SIZE - offset;
d7c255b2 260 lpfc_sli_pcimem_bcopy(((uint8_t *)mb) + DMP_RSP_OFFSET,
d91e3abb
DK
261 lpfc_vpd_data + offset, i);
262 offset += i;
263 } while (offset < DMP_VPD_SIZE);
264
74b72a59 265 lpfc_parse_vpd(phba, lpfc_vpd_data, offset);
dea3101e 266
267 kfree(lpfc_vpd_data);
dea3101e 268out_free_mbox:
269 mempool_free(pmb, phba->mbox_mem_pool);
270 return 0;
271}
272
e59058c4 273/**
3621a710 274 * lpfc_config_async_cmpl - Completion handler for config async event mbox cmd
e59058c4
JS
275 * @phba: pointer to lpfc hba data structure.
276 * @pmboxq: pointer to the driver internal queue element for mailbox command.
277 *
278 * This is the completion handler for driver's configuring asynchronous event
279 * mailbox command to the device. If the mailbox command returns successfully,
280 * it will set internal async event support flag to 1; otherwise, it will
281 * set internal async event support flag to 0.
282 **/
57127f15
JS
283static void
284lpfc_config_async_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
285{
04c68496 286 if (pmboxq->u.mb.mbxStatus == MBX_SUCCESS)
57127f15
JS
287 phba->temp_sensor_support = 1;
288 else
289 phba->temp_sensor_support = 0;
290 mempool_free(pmboxq, phba->mbox_mem_pool);
291 return;
292}
293
97207482 294/**
3621a710 295 * lpfc_dump_wakeup_param_cmpl - dump memory mailbox command completion handler
97207482
JS
296 * @phba: pointer to lpfc hba data structure.
297 * @pmboxq: pointer to the driver internal queue element for mailbox command.
298 *
299 * This is the completion handler for dump mailbox command for getting
300 * wake up parameters. When this command complete, the response contain
301 * Option rom version of the HBA. This function translate the version number
302 * into a human readable string and store it in OptionROMVersion.
303 **/
304static void
305lpfc_dump_wakeup_param_cmpl(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmboxq)
306{
307 struct prog_id *prg;
308 uint32_t prog_id_word;
309 char dist = ' ';
310 /* character array used for decoding dist type. */
311 char dist_char[] = "nabx";
312
04c68496 313 if (pmboxq->u.mb.mbxStatus != MBX_SUCCESS) {
9f1e1b50 314 mempool_free(pmboxq, phba->mbox_mem_pool);
97207482 315 return;
9f1e1b50 316 }
97207482
JS
317
318 prg = (struct prog_id *) &prog_id_word;
319
320 /* word 7 contain option rom version */
04c68496 321 prog_id_word = pmboxq->u.mb.un.varWords[7];
97207482
JS
322
323 /* Decode the Option rom version word to a readable string */
324 if (prg->dist < 4)
325 dist = dist_char[prg->dist];
326
327 if ((prg->dist == 3) && (prg->num == 0))
a2fc4aef 328 snprintf(phba->OptionROMVersion, 32, "%d.%d%d",
97207482
JS
329 prg->ver, prg->rev, prg->lev);
330 else
a2fc4aef 331 snprintf(phba->OptionROMVersion, 32, "%d.%d%d%c%d",
97207482
JS
332 prg->ver, prg->rev, prg->lev,
333 dist, prg->num);
9f1e1b50 334 mempool_free(pmboxq, phba->mbox_mem_pool);
97207482
JS
335 return;
336}
337
0558056c
JS
338/**
339 * lpfc_update_vport_wwn - Updates the fc_nodename, fc_portname,
340 * cfg_soft_wwnn, cfg_soft_wwpn
341 * @vport: pointer to lpfc vport data structure.
342 *
343 *
344 * Return codes
345 * None.
346 **/
347void
348lpfc_update_vport_wwn(struct lpfc_vport *vport)
349{
aeb3c817
JS
350 uint8_t vvvl = vport->fc_sparam.cmn.valid_vendor_ver_level;
351 u32 *fawwpn_key = (u32 *)&vport->fc_sparam.un.vendorVersion[0];
352
0558056c
JS
353 /* If the soft name exists then update it using the service params */
354 if (vport->phba->cfg_soft_wwnn)
355 u64_to_wwn(vport->phba->cfg_soft_wwnn,
356 vport->fc_sparam.nodeName.u.wwn);
357 if (vport->phba->cfg_soft_wwpn)
358 u64_to_wwn(vport->phba->cfg_soft_wwpn,
359 vport->fc_sparam.portName.u.wwn);
360
361 /*
362 * If the name is empty or there exists a soft name
363 * then copy the service params name, otherwise use the fc name
364 */
365 if (vport->fc_nodename.u.wwn[0] == 0 || vport->phba->cfg_soft_wwnn)
366 memcpy(&vport->fc_nodename, &vport->fc_sparam.nodeName,
367 sizeof(struct lpfc_name));
368 else
369 memcpy(&vport->fc_sparam.nodeName, &vport->fc_nodename,
370 sizeof(struct lpfc_name));
371
aeb3c817
JS
372 /*
373 * If the port name has changed, then set the Param changes flag
374 * to unreg the login
375 */
376 if (vport->fc_portname.u.wwn[0] != 0 &&
377 memcmp(&vport->fc_portname, &vport->fc_sparam.portName,
378 sizeof(struct lpfc_name)))
379 vport->vport_flag |= FAWWPN_PARAM_CHG;
380
381 if (vport->fc_portname.u.wwn[0] == 0 ||
382 vport->phba->cfg_soft_wwpn ||
383 (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR) ||
384 vport->vport_flag & FAWWPN_SET) {
0558056c
JS
385 memcpy(&vport->fc_portname, &vport->fc_sparam.portName,
386 sizeof(struct lpfc_name));
aeb3c817
JS
387 vport->vport_flag &= ~FAWWPN_SET;
388 if (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR)
389 vport->vport_flag |= FAWWPN_SET;
390 }
0558056c
JS
391 else
392 memcpy(&vport->fc_sparam.portName, &vport->fc_portname,
393 sizeof(struct lpfc_name));
394}
395
e59058c4 396/**
3621a710 397 * lpfc_config_port_post - Perform lpfc initialization after config port
e59058c4
JS
398 * @phba: pointer to lpfc hba data structure.
399 *
400 * This routine will do LPFC initialization after the CONFIG_PORT mailbox
401 * command call. It performs all internal resource and state setups on the
402 * port: post IOCB buffers, enable appropriate host interrupt attentions,
403 * ELS ring timers, etc.
404 *
405 * Return codes
406 * 0 - success.
407 * Any other value - error.
408 **/
dea3101e 409int
2e0fef85 410lpfc_config_port_post(struct lpfc_hba *phba)
dea3101e 411{
2e0fef85 412 struct lpfc_vport *vport = phba->pport;
a257bf90 413 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
dea3101e 414 LPFC_MBOXQ_t *pmb;
415 MAILBOX_t *mb;
416 struct lpfc_dmabuf *mp;
417 struct lpfc_sli *psli = &phba->sli;
418 uint32_t status, timeout;
2e0fef85
JS
419 int i, j;
420 int rc;
dea3101e 421
7af67051
JS
422 spin_lock_irq(&phba->hbalock);
423 /*
424 * If the Config port completed correctly the HBA is not
425 * over heated any more.
426 */
427 if (phba->over_temp_state == HBA_OVER_TEMP)
428 phba->over_temp_state = HBA_NORMAL_TEMP;
429 spin_unlock_irq(&phba->hbalock);
430
dea3101e 431 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
432 if (!pmb) {
2e0fef85 433 phba->link_state = LPFC_HBA_ERROR;
dea3101e 434 return -ENOMEM;
435 }
04c68496 436 mb = &pmb->u.mb;
dea3101e 437
dea3101e 438 /* Get login parameters for NID. */
9f1177a3
JS
439 rc = lpfc_read_sparam(phba, pmb, 0);
440 if (rc) {
441 mempool_free(pmb, phba->mbox_mem_pool);
442 return -ENOMEM;
443 }
444
ed957684 445 pmb->vport = vport;
dea3101e 446 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
372c187b 447 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 448 "0448 Adapter failed init, mbxCmd x%x "
dea3101e 449 "READ_SPARM mbxStatus x%x\n",
dea3101e 450 mb->mbxCommand, mb->mbxStatus);
2e0fef85 451 phba->link_state = LPFC_HBA_ERROR;
3e1f0718 452 mp = (struct lpfc_dmabuf *)pmb->ctx_buf;
9f1177a3 453 mempool_free(pmb, phba->mbox_mem_pool);
dea3101e 454 lpfc_mbuf_free(phba, mp->virt, mp->phys);
455 kfree(mp);
456 return -EIO;
457 }
458
3e1f0718 459 mp = (struct lpfc_dmabuf *)pmb->ctx_buf;
dea3101e 460
2e0fef85 461 memcpy(&vport->fc_sparam, mp->virt, sizeof (struct serv_parm));
dea3101e 462 lpfc_mbuf_free(phba, mp->virt, mp->phys);
463 kfree(mp);
3e1f0718 464 pmb->ctx_buf = NULL;
0558056c 465 lpfc_update_vport_wwn(vport);
a257bf90
JS
466
467 /* Update the fc_host data structures with new wwn. */
468 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
469 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
21e9a0a5 470 fc_host_max_npiv_vports(shost) = phba->max_vpi;
a257bf90 471
dea3101e 472 /* If no serial number in VPD data, use low 6 bytes of WWNN */
473 /* This should be consolidated into parse_vpd ? - mr */
474 if (phba->SerialNumber[0] == 0) {
475 uint8_t *outptr;
476
2e0fef85 477 outptr = &vport->fc_nodename.u.s.IEEE[0];
dea3101e 478 for (i = 0; i < 12; i++) {
479 status = *outptr++;
480 j = ((status & 0xf0) >> 4);
481 if (j <= 9)
482 phba->SerialNumber[i] =
483 (char)((uint8_t) 0x30 + (uint8_t) j);
484 else
485 phba->SerialNumber[i] =
486 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
487 i++;
488 j = (status & 0xf);
489 if (j <= 9)
490 phba->SerialNumber[i] =
491 (char)((uint8_t) 0x30 + (uint8_t) j);
492 else
493 phba->SerialNumber[i] =
494 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
495 }
496 }
497
dea3101e 498 lpfc_read_config(phba, pmb);
ed957684 499 pmb->vport = vport;
dea3101e 500 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
372c187b 501 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 502 "0453 Adapter failed to init, mbxCmd x%x "
dea3101e 503 "READ_CONFIG, mbxStatus x%x\n",
dea3101e 504 mb->mbxCommand, mb->mbxStatus);
2e0fef85 505 phba->link_state = LPFC_HBA_ERROR;
dea3101e 506 mempool_free( pmb, phba->mbox_mem_pool);
507 return -EIO;
508 }
509
a0c87cbd
JS
510 /* Check if the port is disabled */
511 lpfc_sli_read_link_ste(phba);
512
dea3101e 513 /* Reset the DFT_HBA_Q_DEPTH to the max xri */
f6770e7d 514 if (phba->cfg_hba_queue_depth > mb->un.varRdConfig.max_xri) {
572709e2
JS
515 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
516 "3359 HBA queue depth changed from %d to %d\n",
f6770e7d
JS
517 phba->cfg_hba_queue_depth,
518 mb->un.varRdConfig.max_xri);
519 phba->cfg_hba_queue_depth = mb->un.varRdConfig.max_xri;
572709e2 520 }
dea3101e 521
522 phba->lmt = mb->un.varRdConfig.lmt;
74b72a59
JW
523
524 /* Get the default values for Model Name and Description */
525 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
526
2e0fef85 527 phba->link_state = LPFC_LINK_DOWN;
dea3101e 528
0b727fea 529 /* Only process IOCBs on ELS ring till hba_state is READY */
895427bd
JS
530 if (psli->sli3_ring[LPFC_EXTRA_RING].sli.sli3.cmdringaddr)
531 psli->sli3_ring[LPFC_EXTRA_RING].flag |= LPFC_STOP_IOCB_EVENT;
532 if (psli->sli3_ring[LPFC_FCP_RING].sli.sli3.cmdringaddr)
533 psli->sli3_ring[LPFC_FCP_RING].flag |= LPFC_STOP_IOCB_EVENT;
dea3101e 534
535 /* Post receive buffers for desired rings */
ed957684
JS
536 if (phba->sli_rev != 3)
537 lpfc_post_rcv_buf(phba);
dea3101e 538
9399627f
JS
539 /*
540 * Configure HBA MSI-X attention conditions to messages if MSI-X mode
541 */
542 if (phba->intr_type == MSIX) {
543 rc = lpfc_config_msi(phba, pmb);
544 if (rc) {
545 mempool_free(pmb, phba->mbox_mem_pool);
546 return -EIO;
547 }
548 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
549 if (rc != MBX_SUCCESS) {
372c187b 550 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
9399627f
JS
551 "0352 Config MSI mailbox command "
552 "failed, mbxCmd x%x, mbxStatus x%x\n",
04c68496
JS
553 pmb->u.mb.mbxCommand,
554 pmb->u.mb.mbxStatus);
9399627f
JS
555 mempool_free(pmb, phba->mbox_mem_pool);
556 return -EIO;
557 }
558 }
559
04c68496 560 spin_lock_irq(&phba->hbalock);
9399627f
JS
561 /* Initialize ERATT handling flag */
562 phba->hba_flag &= ~HBA_ERATT_HANDLED;
563
dea3101e 564 /* Enable appropriate host interrupts */
9940b97b
JS
565 if (lpfc_readl(phba->HCregaddr, &status)) {
566 spin_unlock_irq(&phba->hbalock);
567 return -EIO;
568 }
dea3101e 569 status |= HC_MBINT_ENA | HC_ERINT_ENA | HC_LAINT_ENA;
570 if (psli->num_rings > 0)
571 status |= HC_R0INT_ENA;
572 if (psli->num_rings > 1)
573 status |= HC_R1INT_ENA;
574 if (psli->num_rings > 2)
575 status |= HC_R2INT_ENA;
576 if (psli->num_rings > 3)
577 status |= HC_R3INT_ENA;
578
875fbdfe
JSEC
579 if ((phba->cfg_poll & ENABLE_FCP_RING_POLLING) &&
580 (phba->cfg_poll & DISABLE_FCP_RING_INT))
9399627f 581 status &= ~(HC_R0INT_ENA);
875fbdfe 582
dea3101e 583 writel(status, phba->HCregaddr);
584 readl(phba->HCregaddr); /* flush */
2e0fef85 585 spin_unlock_irq(&phba->hbalock);
dea3101e 586
9399627f
JS
587 /* Set up ring-0 (ELS) timer */
588 timeout = phba->fc_ratov * 2;
256ec0d0
JS
589 mod_timer(&vport->els_tmofunc,
590 jiffies + msecs_to_jiffies(1000 * timeout));
9399627f 591 /* Set up heart beat (HB) timer */
256ec0d0
JS
592 mod_timer(&phba->hb_tmofunc,
593 jiffies + msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
594 phba->hb_outstanding = 0;
595 phba->last_completion_time = jiffies;
9399627f 596 /* Set up error attention (ERATT) polling timer */
256ec0d0 597 mod_timer(&phba->eratt_poll,
65791f1f 598 jiffies + msecs_to_jiffies(1000 * phba->eratt_poll_interval));
dea3101e 599
a0c87cbd 600 if (phba->hba_flag & LINK_DISABLED) {
372c187b
DK
601 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
602 "2598 Adapter Link is disabled.\n");
a0c87cbd
JS
603 lpfc_down_link(phba, pmb);
604 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
605 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
606 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
372c187b
DK
607 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
608 "2599 Adapter failed to issue DOWN_LINK"
609 " mbox command rc 0x%x\n", rc);
a0c87cbd
JS
610
611 mempool_free(pmb, phba->mbox_mem_pool);
612 return -EIO;
613 }
e40a02c1 614 } else if (phba->cfg_suppress_link_up == LPFC_INITIALIZE_LINK) {
026abb87
JS
615 mempool_free(pmb, phba->mbox_mem_pool);
616 rc = phba->lpfc_hba_init_link(phba, MBX_NOWAIT);
617 if (rc)
618 return rc;
dea3101e 619 }
620 /* MBOX buffer will be freed in mbox compl */
57127f15 621 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9f1177a3
JS
622 if (!pmb) {
623 phba->link_state = LPFC_HBA_ERROR;
624 return -ENOMEM;
625 }
626
57127f15
JS
627 lpfc_config_async(phba, pmb, LPFC_ELS_RING);
628 pmb->mbox_cmpl = lpfc_config_async_cmpl;
629 pmb->vport = phba->pport;
630 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
dea3101e 631
57127f15 632 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
372c187b 633 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
57127f15 634 "0456 Adapter failed to issue "
e4e74273 635 "ASYNCEVT_ENABLE mbox status x%x\n",
57127f15
JS
636 rc);
637 mempool_free(pmb, phba->mbox_mem_pool);
638 }
97207482
JS
639
640 /* Get Option rom version */
641 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9f1177a3
JS
642 if (!pmb) {
643 phba->link_state = LPFC_HBA_ERROR;
644 return -ENOMEM;
645 }
646
97207482
JS
647 lpfc_dump_wakeup_param(phba, pmb);
648 pmb->mbox_cmpl = lpfc_dump_wakeup_param_cmpl;
649 pmb->vport = phba->pport;
650 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
651
652 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
372c187b
DK
653 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
654 "0435 Adapter failed "
e4e74273 655 "to get Option ROM version status x%x\n", rc);
97207482
JS
656 mempool_free(pmb, phba->mbox_mem_pool);
657 }
658
d7c255b2 659 return 0;
ce8b3ce5
JS
660}
661
84d1b006
JS
662/**
663 * lpfc_hba_init_link - Initialize the FC link
664 * @phba: pointer to lpfc hba data structure.
6e7288d9 665 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
84d1b006
JS
666 *
667 * This routine will issue the INIT_LINK mailbox command call.
668 * It is available to other drivers through the lpfc_hba data
669 * structure for use as a delayed link up mechanism with the
670 * module parameter lpfc_suppress_link_up.
671 *
672 * Return code
673 * 0 - success
674 * Any other value - error
675 **/
e399b228 676static int
6e7288d9 677lpfc_hba_init_link(struct lpfc_hba *phba, uint32_t flag)
1b51197d
JS
678{
679 return lpfc_hba_init_link_fc_topology(phba, phba->cfg_topology, flag);
680}
681
682/**
683 * lpfc_hba_init_link_fc_topology - Initialize FC link with desired topology
684 * @phba: pointer to lpfc hba data structure.
685 * @fc_topology: desired fc topology.
686 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
687 *
688 * This routine will issue the INIT_LINK mailbox command call.
689 * It is available to other drivers through the lpfc_hba data
690 * structure for use as a delayed link up mechanism with the
691 * module parameter lpfc_suppress_link_up.
692 *
693 * Return code
694 * 0 - success
695 * Any other value - error
696 **/
697int
698lpfc_hba_init_link_fc_topology(struct lpfc_hba *phba, uint32_t fc_topology,
699 uint32_t flag)
84d1b006
JS
700{
701 struct lpfc_vport *vport = phba->pport;
702 LPFC_MBOXQ_t *pmb;
703 MAILBOX_t *mb;
704 int rc;
705
706 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
707 if (!pmb) {
708 phba->link_state = LPFC_HBA_ERROR;
709 return -ENOMEM;
710 }
711 mb = &pmb->u.mb;
712 pmb->vport = vport;
713
026abb87
JS
714 if ((phba->cfg_link_speed > LPFC_USER_LINK_SPEED_MAX) ||
715 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_1G) &&
716 !(phba->lmt & LMT_1Gb)) ||
717 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_2G) &&
718 !(phba->lmt & LMT_2Gb)) ||
719 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_4G) &&
720 !(phba->lmt & LMT_4Gb)) ||
721 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_8G) &&
722 !(phba->lmt & LMT_8Gb)) ||
723 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_10G) &&
724 !(phba->lmt & LMT_10Gb)) ||
725 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_16G) &&
d38dd52c
JS
726 !(phba->lmt & LMT_16Gb)) ||
727 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_32G) &&
fbd8a6ba
JS
728 !(phba->lmt & LMT_32Gb)) ||
729 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_64G) &&
730 !(phba->lmt & LMT_64Gb))) {
026abb87 731 /* Reset link speed to auto */
372c187b
DK
732 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
733 "1302 Invalid speed for this board:%d "
734 "Reset link speed to auto.\n",
735 phba->cfg_link_speed);
026abb87
JS
736 phba->cfg_link_speed = LPFC_USER_LINK_SPEED_AUTO;
737 }
1b51197d 738 lpfc_init_link(phba, pmb, fc_topology, phba->cfg_link_speed);
84d1b006 739 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
1b51197d
JS
740 if (phba->sli_rev < LPFC_SLI_REV4)
741 lpfc_set_loopback_flag(phba);
6e7288d9 742 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
76a95d75 743 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
372c187b
DK
744 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
745 "0498 Adapter failed to init, mbxCmd x%x "
746 "INIT_LINK, mbxStatus x%x\n",
747 mb->mbxCommand, mb->mbxStatus);
76a95d75
JS
748 if (phba->sli_rev <= LPFC_SLI_REV3) {
749 /* Clear all interrupt enable conditions */
750 writel(0, phba->HCregaddr);
751 readl(phba->HCregaddr); /* flush */
752 /* Clear all pending interrupts */
753 writel(0xffffffff, phba->HAregaddr);
754 readl(phba->HAregaddr); /* flush */
755 }
84d1b006 756 phba->link_state = LPFC_HBA_ERROR;
6e7288d9 757 if (rc != MBX_BUSY || flag == MBX_POLL)
84d1b006
JS
758 mempool_free(pmb, phba->mbox_mem_pool);
759 return -EIO;
760 }
e40a02c1 761 phba->cfg_suppress_link_up = LPFC_INITIALIZE_LINK;
6e7288d9
JS
762 if (flag == MBX_POLL)
763 mempool_free(pmb, phba->mbox_mem_pool);
84d1b006
JS
764
765 return 0;
766}
767
768/**
769 * lpfc_hba_down_link - this routine downs the FC link
6e7288d9
JS
770 * @phba: pointer to lpfc hba data structure.
771 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
84d1b006
JS
772 *
773 * This routine will issue the DOWN_LINK mailbox command call.
774 * It is available to other drivers through the lpfc_hba data
775 * structure for use to stop the link.
776 *
777 * Return code
778 * 0 - success
779 * Any other value - error
780 **/
e399b228 781static int
6e7288d9 782lpfc_hba_down_link(struct lpfc_hba *phba, uint32_t flag)
84d1b006
JS
783{
784 LPFC_MBOXQ_t *pmb;
785 int rc;
786
787 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
788 if (!pmb) {
789 phba->link_state = LPFC_HBA_ERROR;
790 return -ENOMEM;
791 }
792
372c187b
DK
793 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
794 "0491 Adapter Link is disabled.\n");
84d1b006
JS
795 lpfc_down_link(phba, pmb);
796 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
6e7288d9 797 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
84d1b006 798 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
372c187b
DK
799 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
800 "2522 Adapter failed to issue DOWN_LINK"
801 " mbox command rc 0x%x\n", rc);
84d1b006
JS
802
803 mempool_free(pmb, phba->mbox_mem_pool);
804 return -EIO;
805 }
6e7288d9
JS
806 if (flag == MBX_POLL)
807 mempool_free(pmb, phba->mbox_mem_pool);
808
84d1b006
JS
809 return 0;
810}
811
e59058c4 812/**
3621a710 813 * lpfc_hba_down_prep - Perform lpfc uninitialization prior to HBA reset
e59058c4
JS
814 * @phba: pointer to lpfc HBA data structure.
815 *
816 * This routine will do LPFC uninitialization before the HBA is reset when
817 * bringing down the SLI Layer.
818 *
819 * Return codes
820 * 0 - success.
821 * Any other value - error.
822 **/
dea3101e 823int
2e0fef85 824lpfc_hba_down_prep(struct lpfc_hba *phba)
dea3101e 825{
1b32f6aa
JS
826 struct lpfc_vport **vports;
827 int i;
3772a991
JS
828
829 if (phba->sli_rev <= LPFC_SLI_REV3) {
830 /* Disable interrupts */
831 writel(0, phba->HCregaddr);
832 readl(phba->HCregaddr); /* flush */
833 }
dea3101e 834
1b32f6aa
JS
835 if (phba->pport->load_flag & FC_UNLOADING)
836 lpfc_cleanup_discovery_resources(phba->pport);
837 else {
838 vports = lpfc_create_vport_work_array(phba);
839 if (vports != NULL)
3772a991
JS
840 for (i = 0; i <= phba->max_vports &&
841 vports[i] != NULL; i++)
1b32f6aa
JS
842 lpfc_cleanup_discovery_resources(vports[i]);
843 lpfc_destroy_vport_work_array(phba, vports);
7f5f3d0d
JS
844 }
845 return 0;
dea3101e 846}
847
68e814f5
JS
848/**
849 * lpfc_sli4_free_sp_events - Cleanup sp_queue_events to free
850 * rspiocb which got deferred
851 *
852 * @phba: pointer to lpfc HBA data structure.
853 *
854 * This routine will cleanup completed slow path events after HBA is reset
855 * when bringing down the SLI Layer.
856 *
857 *
858 * Return codes
859 * void.
860 **/
861static void
862lpfc_sli4_free_sp_events(struct lpfc_hba *phba)
863{
864 struct lpfc_iocbq *rspiocbq;
865 struct hbq_dmabuf *dmabuf;
866 struct lpfc_cq_event *cq_event;
867
868 spin_lock_irq(&phba->hbalock);
869 phba->hba_flag &= ~HBA_SP_QUEUE_EVT;
870 spin_unlock_irq(&phba->hbalock);
871
872 while (!list_empty(&phba->sli4_hba.sp_queue_event)) {
873 /* Get the response iocb from the head of work queue */
874 spin_lock_irq(&phba->hbalock);
875 list_remove_head(&phba->sli4_hba.sp_queue_event,
876 cq_event, struct lpfc_cq_event, list);
877 spin_unlock_irq(&phba->hbalock);
878
879 switch (bf_get(lpfc_wcqe_c_code, &cq_event->cqe.wcqe_cmpl)) {
880 case CQE_CODE_COMPL_WQE:
881 rspiocbq = container_of(cq_event, struct lpfc_iocbq,
882 cq_event);
883 lpfc_sli_release_iocbq(phba, rspiocbq);
884 break;
885 case CQE_CODE_RECEIVE:
886 case CQE_CODE_RECEIVE_V1:
887 dmabuf = container_of(cq_event, struct hbq_dmabuf,
888 cq_event);
889 lpfc_in_buf_free(phba, &dmabuf->dbuf);
890 }
891 }
892}
893
e59058c4 894/**
bcece5f5 895 * lpfc_hba_free_post_buf - Perform lpfc uninitialization after HBA reset
e59058c4
JS
896 * @phba: pointer to lpfc HBA data structure.
897 *
bcece5f5
JS
898 * This routine will cleanup posted ELS buffers after the HBA is reset
899 * when bringing down the SLI Layer.
900 *
e59058c4
JS
901 *
902 * Return codes
bcece5f5 903 * void.
e59058c4 904 **/
bcece5f5
JS
905static void
906lpfc_hba_free_post_buf(struct lpfc_hba *phba)
41415862
JW
907{
908 struct lpfc_sli *psli = &phba->sli;
909 struct lpfc_sli_ring *pring;
910 struct lpfc_dmabuf *mp, *next_mp;
07eab624
JS
911 LIST_HEAD(buflist);
912 int count;
41415862 913
92d7f7b0
JS
914 if (phba->sli3_options & LPFC_SLI3_HBQ_ENABLED)
915 lpfc_sli_hbqbuf_free_all(phba);
916 else {
917 /* Cleanup preposted buffers on the ELS ring */
895427bd 918 pring = &psli->sli3_ring[LPFC_ELS_RING];
07eab624
JS
919 spin_lock_irq(&phba->hbalock);
920 list_splice_init(&pring->postbufq, &buflist);
921 spin_unlock_irq(&phba->hbalock);
922
923 count = 0;
924 list_for_each_entry_safe(mp, next_mp, &buflist, list) {
92d7f7b0 925 list_del(&mp->list);
07eab624 926 count++;
92d7f7b0
JS
927 lpfc_mbuf_free(phba, mp->virt, mp->phys);
928 kfree(mp);
929 }
07eab624
JS
930
931 spin_lock_irq(&phba->hbalock);
932 pring->postbufq_cnt -= count;
bcece5f5 933 spin_unlock_irq(&phba->hbalock);
41415862 934 }
bcece5f5
JS
935}
936
937/**
938 * lpfc_hba_clean_txcmplq - Perform lpfc uninitialization after HBA reset
939 * @phba: pointer to lpfc HBA data structure.
940 *
941 * This routine will cleanup the txcmplq after the HBA is reset when bringing
942 * down the SLI Layer.
943 *
944 * Return codes
945 * void
946 **/
947static void
948lpfc_hba_clean_txcmplq(struct lpfc_hba *phba)
949{
950 struct lpfc_sli *psli = &phba->sli;
895427bd 951 struct lpfc_queue *qp = NULL;
bcece5f5
JS
952 struct lpfc_sli_ring *pring;
953 LIST_HEAD(completions);
954 int i;
c1dd9111 955 struct lpfc_iocbq *piocb, *next_iocb;
bcece5f5 956
895427bd
JS
957 if (phba->sli_rev != LPFC_SLI_REV4) {
958 for (i = 0; i < psli->num_rings; i++) {
959 pring = &psli->sli3_ring[i];
bcece5f5 960 spin_lock_irq(&phba->hbalock);
895427bd
JS
961 /* At this point in time the HBA is either reset or DOA
962 * Nothing should be on txcmplq as it will
963 * NEVER complete.
964 */
965 list_splice_init(&pring->txcmplq, &completions);
966 pring->txcmplq_cnt = 0;
bcece5f5 967 spin_unlock_irq(&phba->hbalock);
09372820 968
895427bd
JS
969 lpfc_sli_abort_iocb_ring(phba, pring);
970 }
a257bf90 971 /* Cancel all the IOCBs from the completions list */
895427bd
JS
972 lpfc_sli_cancel_iocbs(phba, &completions,
973 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
974 return;
975 }
976 list_for_each_entry(qp, &phba->sli4_hba.lpfc_wq_list, wq_list) {
977 pring = qp->pring;
978 if (!pring)
979 continue;
980 spin_lock_irq(&pring->ring_lock);
c1dd9111
JS
981 list_for_each_entry_safe(piocb, next_iocb,
982 &pring->txcmplq, list)
983 piocb->iocb_flag &= ~LPFC_IO_ON_TXCMPLQ;
895427bd
JS
984 list_splice_init(&pring->txcmplq, &completions);
985 pring->txcmplq_cnt = 0;
986 spin_unlock_irq(&pring->ring_lock);
41415862
JW
987 lpfc_sli_abort_iocb_ring(phba, pring);
988 }
895427bd
JS
989 /* Cancel all the IOCBs from the completions list */
990 lpfc_sli_cancel_iocbs(phba, &completions,
991 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
bcece5f5 992}
41415862 993
bcece5f5
JS
994/**
995 * lpfc_hba_down_post_s3 - Perform lpfc uninitialization after HBA reset
bcece5f5
JS
996 * @phba: pointer to lpfc HBA data structure.
997 *
998 * This routine will do uninitialization after the HBA is reset when bring
999 * down the SLI Layer.
1000 *
1001 * Return codes
1002 * 0 - success.
1003 * Any other value - error.
1004 **/
1005static int
1006lpfc_hba_down_post_s3(struct lpfc_hba *phba)
1007{
1008 lpfc_hba_free_post_buf(phba);
1009 lpfc_hba_clean_txcmplq(phba);
41415862
JW
1010 return 0;
1011}
5af5eee7 1012
da0436e9
JS
1013/**
1014 * lpfc_hba_down_post_s4 - Perform lpfc uninitialization after HBA reset
1015 * @phba: pointer to lpfc HBA data structure.
1016 *
1017 * This routine will do uninitialization after the HBA is reset when bring
1018 * down the SLI Layer.
1019 *
1020 * Return codes
af901ca1 1021 * 0 - success.
da0436e9
JS
1022 * Any other value - error.
1023 **/
1024static int
1025lpfc_hba_down_post_s4(struct lpfc_hba *phba)
1026{
c490850a 1027 struct lpfc_io_buf *psb, *psb_next;
7cacae2a 1028 struct lpfc_async_xchg_ctx *ctxp, *ctxp_next;
5e5b511d 1029 struct lpfc_sli4_hdw_queue *qp;
da0436e9 1030 LIST_HEAD(aborts);
895427bd 1031 LIST_HEAD(nvme_aborts);
86c67379 1032 LIST_HEAD(nvmet_aborts);
0f65ff68 1033 struct lpfc_sglq *sglq_entry = NULL;
5e5b511d 1034 int cnt, idx;
0f65ff68 1035
895427bd
JS
1036
1037 lpfc_sli_hbqbuf_free_all(phba);
bcece5f5
JS
1038 lpfc_hba_clean_txcmplq(phba);
1039
da0436e9
JS
1040 /* At this point in time the HBA is either reset or DOA. Either
1041 * way, nothing should be on lpfc_abts_els_sgl_list, it needs to be
895427bd 1042 * on the lpfc_els_sgl_list so that it can either be freed if the
da0436e9
JS
1043 * driver is unloading or reposted if the driver is restarting
1044 * the port.
1045 */
895427bd 1046 spin_lock_irq(&phba->hbalock); /* required for lpfc_els_sgl_list and */
da0436e9 1047 /* scsl_buf_list */
895427bd 1048 /* sgl_list_lock required because worker thread uses this
da0436e9
JS
1049 * list.
1050 */
895427bd 1051 spin_lock(&phba->sli4_hba.sgl_list_lock);
0f65ff68
JS
1052 list_for_each_entry(sglq_entry,
1053 &phba->sli4_hba.lpfc_abts_els_sgl_list, list)
1054 sglq_entry->state = SGL_FREED;
1055
da0436e9 1056 list_splice_init(&phba->sli4_hba.lpfc_abts_els_sgl_list,
895427bd
JS
1057 &phba->sli4_hba.lpfc_els_sgl_list);
1058
f358dd0c 1059
895427bd 1060 spin_unlock(&phba->sli4_hba.sgl_list_lock);
5e5b511d
JS
1061
1062 /* abts_xxxx_buf_list_lock required because worker thread uses this
da0436e9
JS
1063 * list.
1064 */
5e5b511d
JS
1065 cnt = 0;
1066 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
1067 qp = &phba->sli4_hba.hdwq[idx];
da0436e9 1068
c00f62e6
JS
1069 spin_lock(&qp->abts_io_buf_list_lock);
1070 list_splice_init(&qp->lpfc_abts_io_buf_list,
5e5b511d 1071 &aborts);
68e814f5 1072
0794d601 1073 list_for_each_entry_safe(psb, psb_next, &aborts, list) {
86c67379
JS
1074 psb->pCmd = NULL;
1075 psb->status = IOSTAT_SUCCESS;
cf1a1d3e 1076 cnt++;
86c67379 1077 }
5e5b511d
JS
1078 spin_lock(&qp->io_buf_list_put_lock);
1079 list_splice_init(&aborts, &qp->lpfc_io_buf_list_put);
1080 qp->put_io_bufs += qp->abts_scsi_io_bufs;
c00f62e6 1081 qp->put_io_bufs += qp->abts_nvme_io_bufs;
5e5b511d 1082 qp->abts_scsi_io_bufs = 0;
c00f62e6 1083 qp->abts_nvme_io_bufs = 0;
5e5b511d 1084 spin_unlock(&qp->io_buf_list_put_lock);
c00f62e6 1085 spin_unlock(&qp->abts_io_buf_list_lock);
5e5b511d 1086 }
731eedcb 1087 spin_unlock_irq(&phba->hbalock);
86c67379 1088
5e5b511d 1089 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
731eedcb 1090 spin_lock_irq(&phba->sli4_hba.abts_nvmet_buf_list_lock);
5e5b511d
JS
1091 list_splice_init(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list,
1092 &nvmet_aborts);
731eedcb 1093 spin_unlock_irq(&phba->sli4_hba.abts_nvmet_buf_list_lock);
86c67379 1094 list_for_each_entry_safe(ctxp, ctxp_next, &nvmet_aborts, list) {
7b7f551b 1095 ctxp->flag &= ~(LPFC_NVME_XBUSY | LPFC_NVME_ABORT_OP);
6c621a22 1096 lpfc_nvmet_ctxbuf_post(phba, ctxp->ctxbuf);
86c67379 1097 }
895427bd 1098 }
895427bd 1099
68e814f5 1100 lpfc_sli4_free_sp_events(phba);
5e5b511d 1101 return cnt;
da0436e9
JS
1102}
1103
1104/**
1105 * lpfc_hba_down_post - Wrapper func for hba down post routine
1106 * @phba: pointer to lpfc HBA data structure.
1107 *
1108 * This routine wraps the actual SLI3 or SLI4 routine for performing
1109 * uninitialization after the HBA is reset when bring down the SLI Layer.
1110 *
1111 * Return codes
af901ca1 1112 * 0 - success.
da0436e9
JS
1113 * Any other value - error.
1114 **/
1115int
1116lpfc_hba_down_post(struct lpfc_hba *phba)
1117{
1118 return (*phba->lpfc_hba_down_post)(phba);
1119}
41415862 1120
e59058c4 1121/**
3621a710 1122 * lpfc_hb_timeout - The HBA-timer timeout handler
fe614acd 1123 * @t: timer context used to obtain the pointer to lpfc hba data structure.
e59058c4
JS
1124 *
1125 * This is the HBA-timer timeout handler registered to the lpfc driver. When
1126 * this timer fires, a HBA timeout event shall be posted to the lpfc driver
1127 * work-port-events bitmap and the worker thread is notified. This timeout
1128 * event will be used by the worker thread to invoke the actual timeout
1129 * handler routine, lpfc_hb_timeout_handler. Any periodical operations will
1130 * be performed in the timeout handler and the HBA timeout event bit shall
1131 * be cleared by the worker thread after it has taken the event bitmap out.
1132 **/
a6ababd2 1133static void
f22eb4d3 1134lpfc_hb_timeout(struct timer_list *t)
858c9f6c
JS
1135{
1136 struct lpfc_hba *phba;
5e9d9b82 1137 uint32_t tmo_posted;
858c9f6c
JS
1138 unsigned long iflag;
1139
f22eb4d3 1140 phba = from_timer(phba, t, hb_tmofunc);
9399627f
JS
1141
1142 /* Check for heart beat timeout conditions */
858c9f6c 1143 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
5e9d9b82
JS
1144 tmo_posted = phba->pport->work_port_events & WORKER_HB_TMO;
1145 if (!tmo_posted)
858c9f6c
JS
1146 phba->pport->work_port_events |= WORKER_HB_TMO;
1147 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
1148
9399627f 1149 /* Tell the worker thread there is work to do */
5e9d9b82
JS
1150 if (!tmo_posted)
1151 lpfc_worker_wake_up(phba);
858c9f6c
JS
1152 return;
1153}
1154
19ca7609
JS
1155/**
1156 * lpfc_rrq_timeout - The RRQ-timer timeout handler
fe614acd 1157 * @t: timer context used to obtain the pointer to lpfc hba data structure.
19ca7609
JS
1158 *
1159 * This is the RRQ-timer timeout handler registered to the lpfc driver. When
1160 * this timer fires, a RRQ timeout event shall be posted to the lpfc driver
1161 * work-port-events bitmap and the worker thread is notified. This timeout
1162 * event will be used by the worker thread to invoke the actual timeout
1163 * handler routine, lpfc_rrq_handler. Any periodical operations will
1164 * be performed in the timeout handler and the RRQ timeout event bit shall
1165 * be cleared by the worker thread after it has taken the event bitmap out.
1166 **/
1167static void
f22eb4d3 1168lpfc_rrq_timeout(struct timer_list *t)
19ca7609
JS
1169{
1170 struct lpfc_hba *phba;
19ca7609
JS
1171 unsigned long iflag;
1172
f22eb4d3 1173 phba = from_timer(phba, t, rrq_tmr);
19ca7609 1174 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
06918ac5
JS
1175 if (!(phba->pport->load_flag & FC_UNLOADING))
1176 phba->hba_flag |= HBA_RRQ_ACTIVE;
1177 else
1178 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
19ca7609 1179 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
06918ac5
JS
1180
1181 if (!(phba->pport->load_flag & FC_UNLOADING))
1182 lpfc_worker_wake_up(phba);
19ca7609
JS
1183}
1184
e59058c4 1185/**
3621a710 1186 * lpfc_hb_mbox_cmpl - The lpfc heart-beat mailbox command callback function
e59058c4
JS
1187 * @phba: pointer to lpfc hba data structure.
1188 * @pmboxq: pointer to the driver internal queue element for mailbox command.
1189 *
1190 * This is the callback function to the lpfc heart-beat mailbox command.
1191 * If configured, the lpfc driver issues the heart-beat mailbox command to
1192 * the HBA every LPFC_HB_MBOX_INTERVAL (current 5) seconds. At the time the
1193 * heart-beat mailbox command is issued, the driver shall set up heart-beat
1194 * timeout timer to LPFC_HB_MBOX_TIMEOUT (current 30) seconds and marks
1195 * heart-beat outstanding state. Once the mailbox command comes back and
1196 * no error conditions detected, the heart-beat mailbox command timer is
1197 * reset to LPFC_HB_MBOX_INTERVAL seconds and the heart-beat outstanding
1198 * state is cleared for the next heart-beat. If the timer expired with the
1199 * heart-beat outstanding state set, the driver will put the HBA offline.
1200 **/
858c9f6c
JS
1201static void
1202lpfc_hb_mbox_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
1203{
1204 unsigned long drvr_flag;
1205
1206 spin_lock_irqsave(&phba->hbalock, drvr_flag);
1207 phba->hb_outstanding = 0;
1208 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
1209
9399627f 1210 /* Check and reset heart-beat timer is necessary */
858c9f6c
JS
1211 mempool_free(pmboxq, phba->mbox_mem_pool);
1212 if (!(phba->pport->fc_flag & FC_OFFLINE_MODE) &&
1213 !(phba->link_state == LPFC_HBA_ERROR) &&
51ef4c26 1214 !(phba->pport->load_flag & FC_UNLOADING))
858c9f6c 1215 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1216 jiffies +
1217 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
1218 return;
1219}
1220
fe614acd 1221/*
317aeb83
DK
1222 * lpfc_idle_stat_delay_work - idle_stat tracking
1223 *
1224 * This routine tracks per-cq idle_stat and determines polling decisions.
1225 *
1226 * Return codes:
1227 * None
1228 **/
1229static void
1230lpfc_idle_stat_delay_work(struct work_struct *work)
1231{
1232 struct lpfc_hba *phba = container_of(to_delayed_work(work),
1233 struct lpfc_hba,
1234 idle_stat_delay_work);
1235 struct lpfc_queue *cq;
1236 struct lpfc_sli4_hdw_queue *hdwq;
1237 struct lpfc_idle_stat *idle_stat;
1238 u32 i, idle_percent;
1239 u64 wall, wall_idle, diff_wall, diff_idle, busy_time;
1240
1241 if (phba->pport->load_flag & FC_UNLOADING)
1242 return;
1243
1244 if (phba->link_state == LPFC_HBA_ERROR ||
1245 phba->pport->fc_flag & FC_OFFLINE_MODE)
1246 goto requeue;
1247
1248 for_each_present_cpu(i) {
1249 hdwq = &phba->sli4_hba.hdwq[phba->sli4_hba.cpu_map[i].hdwq];
1250 cq = hdwq->io_cq;
1251
1252 /* Skip if we've already handled this cq's primary CPU */
1253 if (cq->chann != i)
1254 continue;
1255
1256 idle_stat = &phba->sli4_hba.idle_stat[i];
1257
1258 /* get_cpu_idle_time returns values as running counters. Thus,
1259 * to know the amount for this period, the prior counter values
1260 * need to be subtracted from the current counter values.
1261 * From there, the idle time stat can be calculated as a
1262 * percentage of 100 - the sum of the other consumption times.
1263 */
1264 wall_idle = get_cpu_idle_time(i, &wall, 1);
1265 diff_idle = wall_idle - idle_stat->prev_idle;
1266 diff_wall = wall - idle_stat->prev_wall;
1267
1268 if (diff_wall <= diff_idle)
1269 busy_time = 0;
1270 else
1271 busy_time = diff_wall - diff_idle;
1272
1273 idle_percent = div64_u64(100 * busy_time, diff_wall);
1274 idle_percent = 100 - idle_percent;
1275
1276 if (idle_percent < 15)
1277 cq->poll_mode = LPFC_QUEUE_WORK;
1278 else
1279 cq->poll_mode = LPFC_IRQ_POLL;
1280
1281 idle_stat->prev_idle = wall_idle;
1282 idle_stat->prev_wall = wall;
1283 }
1284
1285requeue:
1286 schedule_delayed_work(&phba->idle_stat_delay_work,
1287 msecs_to_jiffies(LPFC_IDLE_STAT_DELAY));
1288}
1289
32517fc0
JS
1290static void
1291lpfc_hb_eq_delay_work(struct work_struct *work)
1292{
1293 struct lpfc_hba *phba = container_of(to_delayed_work(work),
1294 struct lpfc_hba, eq_delay_work);
1295 struct lpfc_eq_intr_info *eqi, *eqi_new;
1296 struct lpfc_queue *eq, *eq_next;
8156d378 1297 unsigned char *ena_delay = NULL;
32517fc0
JS
1298 uint32_t usdelay;
1299 int i;
1300
1301 if (!phba->cfg_auto_imax || phba->pport->load_flag & FC_UNLOADING)
1302 return;
1303
1304 if (phba->link_state == LPFC_HBA_ERROR ||
1305 phba->pport->fc_flag & FC_OFFLINE_MODE)
1306 goto requeue;
1307
8156d378
JS
1308 ena_delay = kcalloc(phba->sli4_hba.num_possible_cpu, sizeof(*ena_delay),
1309 GFP_KERNEL);
1310 if (!ena_delay)
32517fc0
JS
1311 goto requeue;
1312
8156d378
JS
1313 for (i = 0; i < phba->cfg_irq_chann; i++) {
1314 /* Get the EQ corresponding to the IRQ vector */
1315 eq = phba->sli4_hba.hba_eq_hdl[i].eq;
1316 if (!eq)
1317 continue;
1318 if (eq->q_mode || eq->q_flag & HBA_EQ_DELAY_CHK) {
1319 eq->q_flag &= ~HBA_EQ_DELAY_CHK;
1320 ena_delay[eq->last_cpu] = 1;
8d34a59c 1321 }
8156d378 1322 }
32517fc0
JS
1323
1324 for_each_present_cpu(i) {
32517fc0 1325 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, i);
8156d378
JS
1326 if (ena_delay[i]) {
1327 usdelay = (eqi->icnt >> 10) * LPFC_EQ_DELAY_STEP;
1328 if (usdelay > LPFC_MAX_AUTO_EQ_DELAY)
1329 usdelay = LPFC_MAX_AUTO_EQ_DELAY;
1330 } else {
1331 usdelay = 0;
8d34a59c 1332 }
32517fc0 1333
32517fc0
JS
1334 eqi->icnt = 0;
1335
1336 list_for_each_entry_safe(eq, eq_next, &eqi->list, cpu_list) {
8156d378 1337 if (unlikely(eq->last_cpu != i)) {
32517fc0
JS
1338 eqi_new = per_cpu_ptr(phba->sli4_hba.eq_info,
1339 eq->last_cpu);
1340 list_move_tail(&eq->cpu_list, &eqi_new->list);
1341 continue;
1342 }
1343 if (usdelay != eq->q_mode)
1344 lpfc_modify_hba_eq_delay(phba, eq->hdwq, 1,
1345 usdelay);
1346 }
1347 }
1348
8156d378 1349 kfree(ena_delay);
32517fc0
JS
1350
1351requeue:
1352 queue_delayed_work(phba->wq, &phba->eq_delay_work,
1353 msecs_to_jiffies(LPFC_EQ_DELAY_MSECS));
1354}
1355
c490850a
JS
1356/**
1357 * lpfc_hb_mxp_handler - Multi-XRI pools handler to adjust XRI distribution
1358 * @phba: pointer to lpfc hba data structure.
1359 *
1360 * For each heartbeat, this routine does some heuristic methods to adjust
1361 * XRI distribution. The goal is to fully utilize free XRIs.
1362 **/
1363static void lpfc_hb_mxp_handler(struct lpfc_hba *phba)
1364{
1365 u32 i;
1366 u32 hwq_count;
1367
1368 hwq_count = phba->cfg_hdw_queue;
1369 for (i = 0; i < hwq_count; i++) {
1370 /* Adjust XRIs in private pool */
1371 lpfc_adjust_pvt_pool_count(phba, i);
1372
1373 /* Adjust high watermark */
1374 lpfc_adjust_high_watermark(phba, i);
1375
1376#ifdef LPFC_MXP_STAT
1377 /* Snapshot pbl, pvt and busy count */
1378 lpfc_snapshot_mxp(phba, i);
1379#endif
1380 }
1381}
1382
e59058c4 1383/**
3621a710 1384 * lpfc_hb_timeout_handler - The HBA-timer timeout handler
e59058c4
JS
1385 * @phba: pointer to lpfc hba data structure.
1386 *
1387 * This is the actual HBA-timer timeout handler to be invoked by the worker
1388 * thread whenever the HBA timer fired and HBA-timeout event posted. This
1389 * handler performs any periodic operations needed for the device. If such
1390 * periodic event has already been attended to either in the interrupt handler
1391 * or by processing slow-ring or fast-ring events within the HBA-timer
1392 * timeout window (LPFC_HB_MBOX_INTERVAL), this handler just simply resets
1393 * the timer for the next timeout period. If lpfc heart-beat mailbox command
1394 * is configured and there is no heart-beat mailbox command outstanding, a
1395 * heart-beat mailbox is issued and timer set properly. Otherwise, if there
1396 * has been a heart-beat mailbox command outstanding, the HBA shall be put
1397 * to offline.
1398 **/
858c9f6c
JS
1399void
1400lpfc_hb_timeout_handler(struct lpfc_hba *phba)
1401{
45ed1190 1402 struct lpfc_vport **vports;
858c9f6c 1403 LPFC_MBOXQ_t *pmboxq;
0ff10d46 1404 struct lpfc_dmabuf *buf_ptr;
45ed1190 1405 int retval, i;
858c9f6c 1406 struct lpfc_sli *psli = &phba->sli;
0ff10d46 1407 LIST_HEAD(completions);
858c9f6c 1408
c490850a
JS
1409 if (phba->cfg_xri_rebalancing) {
1410 /* Multi-XRI pools handler */
1411 lpfc_hb_mxp_handler(phba);
1412 }
858c9f6c 1413
45ed1190
JS
1414 vports = lpfc_create_vport_work_array(phba);
1415 if (vports != NULL)
4258e98e 1416 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
45ed1190 1417 lpfc_rcv_seq_check_edtov(vports[i]);
e3ba04c9 1418 lpfc_fdmi_change_check(vports[i]);
4258e98e 1419 }
45ed1190
JS
1420 lpfc_destroy_vport_work_array(phba, vports);
1421
858c9f6c 1422 if ((phba->link_state == LPFC_HBA_ERROR) ||
51ef4c26 1423 (phba->pport->load_flag & FC_UNLOADING) ||
858c9f6c
JS
1424 (phba->pport->fc_flag & FC_OFFLINE_MODE))
1425 return;
1426
1427 spin_lock_irq(&phba->pport->work_port_lock);
858c9f6c 1428
256ec0d0
JS
1429 if (time_after(phba->last_completion_time +
1430 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL),
1431 jiffies)) {
858c9f6c
JS
1432 spin_unlock_irq(&phba->pport->work_port_lock);
1433 if (!phba->hb_outstanding)
1434 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1435 jiffies +
1436 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
1437 else
1438 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1439 jiffies +
1440 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
858c9f6c
JS
1441 return;
1442 }
1443 spin_unlock_irq(&phba->pport->work_port_lock);
1444
0ff10d46
JS
1445 if (phba->elsbuf_cnt &&
1446 (phba->elsbuf_cnt == phba->elsbuf_prev_cnt)) {
1447 spin_lock_irq(&phba->hbalock);
1448 list_splice_init(&phba->elsbuf, &completions);
1449 phba->elsbuf_cnt = 0;
1450 phba->elsbuf_prev_cnt = 0;
1451 spin_unlock_irq(&phba->hbalock);
1452
1453 while (!list_empty(&completions)) {
1454 list_remove_head(&completions, buf_ptr,
1455 struct lpfc_dmabuf, list);
1456 lpfc_mbuf_free(phba, buf_ptr->virt, buf_ptr->phys);
1457 kfree(buf_ptr);
1458 }
1459 }
1460 phba->elsbuf_prev_cnt = phba->elsbuf_cnt;
1461
858c9f6c 1462 /* If there is no heart beat outstanding, issue a heartbeat command */
13815c83
JS
1463 if (phba->cfg_enable_hba_heartbeat) {
1464 if (!phba->hb_outstanding) {
bc73905a
JS
1465 if ((!(psli->sli_flag & LPFC_SLI_MBOX_ACTIVE)) &&
1466 (list_empty(&psli->mboxq))) {
1467 pmboxq = mempool_alloc(phba->mbox_mem_pool,
1468 GFP_KERNEL);
1469 if (!pmboxq) {
1470 mod_timer(&phba->hb_tmofunc,
1471 jiffies +
256ec0d0
JS
1472 msecs_to_jiffies(1000 *
1473 LPFC_HB_MBOX_INTERVAL));
bc73905a
JS
1474 return;
1475 }
1476
1477 lpfc_heart_beat(phba, pmboxq);
1478 pmboxq->mbox_cmpl = lpfc_hb_mbox_cmpl;
1479 pmboxq->vport = phba->pport;
1480 retval = lpfc_sli_issue_mbox(phba, pmboxq,
1481 MBX_NOWAIT);
1482
1483 if (retval != MBX_BUSY &&
1484 retval != MBX_SUCCESS) {
1485 mempool_free(pmboxq,
1486 phba->mbox_mem_pool);
1487 mod_timer(&phba->hb_tmofunc,
1488 jiffies +
256ec0d0
JS
1489 msecs_to_jiffies(1000 *
1490 LPFC_HB_MBOX_INTERVAL));
bc73905a
JS
1491 return;
1492 }
1493 phba->skipped_hb = 0;
1494 phba->hb_outstanding = 1;
1495 } else if (time_before_eq(phba->last_completion_time,
1496 phba->skipped_hb)) {
1497 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
1498 "2857 Last completion time not "
1499 " updated in %d ms\n",
1500 jiffies_to_msecs(jiffies
1501 - phba->last_completion_time));
1502 } else
1503 phba->skipped_hb = jiffies;
1504
858c9f6c 1505 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1506 jiffies +
1507 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
858c9f6c 1508 return;
13815c83
JS
1509 } else {
1510 /*
1511 * If heart beat timeout called with hb_outstanding set
dcf2a4e0
JS
1512 * we need to give the hb mailbox cmd a chance to
1513 * complete or TMO.
13815c83 1514 */
dcf2a4e0
JS
1515 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1516 "0459 Adapter heartbeat still out"
1517 "standing:last compl time was %d ms.\n",
1518 jiffies_to_msecs(jiffies
1519 - phba->last_completion_time));
1520 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1521 jiffies +
1522 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
858c9f6c 1523 }
4258e98e
JS
1524 } else {
1525 mod_timer(&phba->hb_tmofunc,
1526 jiffies +
1527 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
1528 }
1529}
1530
e59058c4 1531/**
3621a710 1532 * lpfc_offline_eratt - Bring lpfc offline on hardware error attention
e59058c4
JS
1533 * @phba: pointer to lpfc hba data structure.
1534 *
1535 * This routine is called to bring the HBA offline when HBA hardware error
1536 * other than Port Error 6 has been detected.
1537 **/
09372820
JS
1538static void
1539lpfc_offline_eratt(struct lpfc_hba *phba)
1540{
1541 struct lpfc_sli *psli = &phba->sli;
1542
1543 spin_lock_irq(&phba->hbalock);
f4b4c68f 1544 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
09372820 1545 spin_unlock_irq(&phba->hbalock);
618a5230 1546 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
09372820
JS
1547
1548 lpfc_offline(phba);
1549 lpfc_reset_barrier(phba);
f4b4c68f 1550 spin_lock_irq(&phba->hbalock);
09372820 1551 lpfc_sli_brdreset(phba);
f4b4c68f 1552 spin_unlock_irq(&phba->hbalock);
09372820
JS
1553 lpfc_hba_down_post(phba);
1554 lpfc_sli_brdready(phba, HS_MBRDY);
1555 lpfc_unblock_mgmt_io(phba);
1556 phba->link_state = LPFC_HBA_ERROR;
1557 return;
1558}
1559
da0436e9
JS
1560/**
1561 * lpfc_sli4_offline_eratt - Bring lpfc offline on SLI4 hardware error attention
1562 * @phba: pointer to lpfc hba data structure.
1563 *
1564 * This routine is called to bring a SLI4 HBA offline when HBA hardware error
1565 * other than Port Error 6 has been detected.
1566 **/
a88dbb6a 1567void
da0436e9
JS
1568lpfc_sli4_offline_eratt(struct lpfc_hba *phba)
1569{
946727dc
JS
1570 spin_lock_irq(&phba->hbalock);
1571 phba->link_state = LPFC_HBA_ERROR;
1572 spin_unlock_irq(&phba->hbalock);
1573
618a5230 1574 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
c00f62e6 1575 lpfc_sli_flush_io_rings(phba);
da0436e9 1576 lpfc_offline(phba);
da0436e9 1577 lpfc_hba_down_post(phba);
da0436e9 1578 lpfc_unblock_mgmt_io(phba);
da0436e9
JS
1579}
1580
a257bf90
JS
1581/**
1582 * lpfc_handle_deferred_eratt - The HBA hardware deferred error handler
1583 * @phba: pointer to lpfc hba data structure.
1584 *
1585 * This routine is invoked to handle the deferred HBA hardware error
1586 * conditions. This type of error is indicated by HBA by setting ER1
1587 * and another ER bit in the host status register. The driver will
1588 * wait until the ER1 bit clears before handling the error condition.
1589 **/
1590static void
1591lpfc_handle_deferred_eratt(struct lpfc_hba *phba)
1592{
1593 uint32_t old_host_status = phba->work_hs;
a257bf90
JS
1594 struct lpfc_sli *psli = &phba->sli;
1595
f4b4c68f
JS
1596 /* If the pci channel is offline, ignore possible errors,
1597 * since we cannot communicate with the pci card anyway.
1598 */
1599 if (pci_channel_offline(phba->pcidev)) {
1600 spin_lock_irq(&phba->hbalock);
1601 phba->hba_flag &= ~DEFER_ERATT;
1602 spin_unlock_irq(&phba->hbalock);
1603 return;
1604 }
1605
372c187b
DK
1606 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1607 "0479 Deferred Adapter Hardware Error "
1608 "Data: x%x x%x x%x\n",
1609 phba->work_hs, phba->work_status[0],
1610 phba->work_status[1]);
a257bf90
JS
1611
1612 spin_lock_irq(&phba->hbalock);
f4b4c68f 1613 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
a257bf90
JS
1614 spin_unlock_irq(&phba->hbalock);
1615
1616
1617 /*
1618 * Firmware stops when it triggred erratt. That could cause the I/Os
1619 * dropped by the firmware. Error iocb (I/O) on txcmplq and let the
1620 * SCSI layer retry it after re-establishing link.
1621 */
db55fba8 1622 lpfc_sli_abort_fcp_rings(phba);
a257bf90
JS
1623
1624 /*
1625 * There was a firmware error. Take the hba offline and then
1626 * attempt to restart it.
1627 */
618a5230 1628 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
a257bf90
JS
1629 lpfc_offline(phba);
1630
1631 /* Wait for the ER1 bit to clear.*/
1632 while (phba->work_hs & HS_FFER1) {
1633 msleep(100);
9940b97b
JS
1634 if (lpfc_readl(phba->HSregaddr, &phba->work_hs)) {
1635 phba->work_hs = UNPLUG_ERR ;
1636 break;
1637 }
a257bf90
JS
1638 /* If driver is unloading let the worker thread continue */
1639 if (phba->pport->load_flag & FC_UNLOADING) {
1640 phba->work_hs = 0;
1641 break;
1642 }
1643 }
1644
1645 /*
1646 * This is to ptrotect against a race condition in which
1647 * first write to the host attention register clear the
1648 * host status register.
1649 */
1650 if ((!phba->work_hs) && (!(phba->pport->load_flag & FC_UNLOADING)))
1651 phba->work_hs = old_host_status & ~HS_FFER1;
1652
3772a991 1653 spin_lock_irq(&phba->hbalock);
a257bf90 1654 phba->hba_flag &= ~DEFER_ERATT;
3772a991 1655 spin_unlock_irq(&phba->hbalock);
a257bf90
JS
1656 phba->work_status[0] = readl(phba->MBslimaddr + 0xa8);
1657 phba->work_status[1] = readl(phba->MBslimaddr + 0xac);
1658}
1659
3772a991
JS
1660static void
1661lpfc_board_errevt_to_mgmt(struct lpfc_hba *phba)
1662{
1663 struct lpfc_board_event_header board_event;
1664 struct Scsi_Host *shost;
1665
1666 board_event.event_type = FC_REG_BOARD_EVENT;
1667 board_event.subcategory = LPFC_EVENT_PORTINTERR;
1668 shost = lpfc_shost_from_vport(phba->pport);
1669 fc_host_post_vendor_event(shost, fc_get_event_number(),
1670 sizeof(board_event),
1671 (char *) &board_event,
1672 LPFC_NL_VENDOR_ID);
1673}
1674
e59058c4 1675/**
3772a991 1676 * lpfc_handle_eratt_s3 - The SLI3 HBA hardware error handler
e59058c4
JS
1677 * @phba: pointer to lpfc hba data structure.
1678 *
1679 * This routine is invoked to handle the following HBA hardware error
1680 * conditions:
1681 * 1 - HBA error attention interrupt
1682 * 2 - DMA ring index out of range
1683 * 3 - Mailbox command came back as unknown
1684 **/
3772a991
JS
1685static void
1686lpfc_handle_eratt_s3(struct lpfc_hba *phba)
dea3101e 1687{
2e0fef85 1688 struct lpfc_vport *vport = phba->pport;
2e0fef85 1689 struct lpfc_sli *psli = &phba->sli;
d2873e4c 1690 uint32_t event_data;
57127f15
JS
1691 unsigned long temperature;
1692 struct temp_event temp_event_data;
92d7f7b0 1693 struct Scsi_Host *shost;
2e0fef85 1694
8d63f375 1695 /* If the pci channel is offline, ignore possible errors,
3772a991
JS
1696 * since we cannot communicate with the pci card anyway.
1697 */
1698 if (pci_channel_offline(phba->pcidev)) {
1699 spin_lock_irq(&phba->hbalock);
1700 phba->hba_flag &= ~DEFER_ERATT;
1701 spin_unlock_irq(&phba->hbalock);
8d63f375 1702 return;
3772a991
JS
1703 }
1704
13815c83
JS
1705 /* If resets are disabled then leave the HBA alone and return */
1706 if (!phba->cfg_enable_hba_reset)
1707 return;
dea3101e 1708
ea2151b4 1709 /* Send an internal error event to mgmt application */
3772a991 1710 lpfc_board_errevt_to_mgmt(phba);
ea2151b4 1711
a257bf90
JS
1712 if (phba->hba_flag & DEFER_ERATT)
1713 lpfc_handle_deferred_eratt(phba);
1714
dcf2a4e0
JS
1715 if ((phba->work_hs & HS_FFER6) || (phba->work_hs & HS_FFER8)) {
1716 if (phba->work_hs & HS_FFER6)
1717 /* Re-establishing Link */
1718 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1719 "1301 Re-establishing Link "
1720 "Data: x%x x%x x%x\n",
1721 phba->work_hs, phba->work_status[0],
1722 phba->work_status[1]);
1723 if (phba->work_hs & HS_FFER8)
1724 /* Device Zeroization */
1725 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1726 "2861 Host Authentication device "
1727 "zeroization Data:x%x x%x x%x\n",
1728 phba->work_hs, phba->work_status[0],
1729 phba->work_status[1]);
58da1ffb 1730
92d7f7b0 1731 spin_lock_irq(&phba->hbalock);
f4b4c68f 1732 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
92d7f7b0 1733 spin_unlock_irq(&phba->hbalock);
dea3101e 1734
1735 /*
1736 * Firmware stops when it triggled erratt with HS_FFER6.
1737 * That could cause the I/Os dropped by the firmware.
1738 * Error iocb (I/O) on txcmplq and let the SCSI layer
1739 * retry it after re-establishing link.
1740 */
db55fba8 1741 lpfc_sli_abort_fcp_rings(phba);
dea3101e 1742
dea3101e 1743 /*
1744 * There was a firmware error. Take the hba offline and then
1745 * attempt to restart it.
1746 */
618a5230 1747 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
dea3101e 1748 lpfc_offline(phba);
41415862 1749 lpfc_sli_brdrestart(phba);
dea3101e 1750 if (lpfc_online(phba) == 0) { /* Initialize the HBA */
46fa311e 1751 lpfc_unblock_mgmt_io(phba);
dea3101e 1752 return;
1753 }
46fa311e 1754 lpfc_unblock_mgmt_io(phba);
57127f15
JS
1755 } else if (phba->work_hs & HS_CRIT_TEMP) {
1756 temperature = readl(phba->MBslimaddr + TEMPERATURE_OFFSET);
1757 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1758 temp_event_data.event_code = LPFC_CRIT_TEMP;
1759 temp_event_data.data = (uint32_t)temperature;
1760
372c187b 1761 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
d7c255b2 1762 "0406 Adapter maximum temperature exceeded "
57127f15
JS
1763 "(%ld), taking this port offline "
1764 "Data: x%x x%x x%x\n",
1765 temperature, phba->work_hs,
1766 phba->work_status[0], phba->work_status[1]);
1767
1768 shost = lpfc_shost_from_vport(phba->pport);
1769 fc_host_post_vendor_event(shost, fc_get_event_number(),
1770 sizeof(temp_event_data),
1771 (char *) &temp_event_data,
1772 SCSI_NL_VID_TYPE_PCI
1773 | PCI_VENDOR_ID_EMULEX);
1774
7af67051 1775 spin_lock_irq(&phba->hbalock);
7af67051
JS
1776 phba->over_temp_state = HBA_OVER_TEMP;
1777 spin_unlock_irq(&phba->hbalock);
09372820 1778 lpfc_offline_eratt(phba);
57127f15 1779
dea3101e 1780 } else {
1781 /* The if clause above forces this code path when the status
9399627f
JS
1782 * failure is a value other than FFER6. Do not call the offline
1783 * twice. This is the adapter hardware error path.
dea3101e 1784 */
372c187b 1785 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e8b62011 1786 "0457 Adapter Hardware Error "
dea3101e 1787 "Data: x%x x%x x%x\n",
e8b62011 1788 phba->work_hs,
dea3101e 1789 phba->work_status[0], phba->work_status[1]);
1790
d2873e4c 1791 event_data = FC_REG_DUMP_EVENT;
92d7f7b0 1792 shost = lpfc_shost_from_vport(vport);
2e0fef85 1793 fc_host_post_vendor_event(shost, fc_get_event_number(),
d2873e4c
JS
1794 sizeof(event_data), (char *) &event_data,
1795 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
1796
09372820 1797 lpfc_offline_eratt(phba);
dea3101e 1798 }
9399627f 1799 return;
dea3101e 1800}
1801
618a5230
JS
1802/**
1803 * lpfc_sli4_port_sta_fn_reset - The SLI4 function reset due to port status reg
1804 * @phba: pointer to lpfc hba data structure.
1805 * @mbx_action: flag for mailbox shutdown action.
fe614acd 1806 * @en_rn_msg: send reset/port recovery message.
618a5230
JS
1807 * This routine is invoked to perform an SLI4 port PCI function reset in
1808 * response to port status register polling attention. It waits for port
1809 * status register (ERR, RDY, RN) bits before proceeding with function reset.
1810 * During this process, interrupt vectors are freed and later requested
1811 * for handling possible port resource change.
1812 **/
1813static int
e10b2022
JS
1814lpfc_sli4_port_sta_fn_reset(struct lpfc_hba *phba, int mbx_action,
1815 bool en_rn_msg)
618a5230
JS
1816{
1817 int rc;
1818 uint32_t intr_mode;
1819
27d6ac0a 1820 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) >=
65791f1f
JS
1821 LPFC_SLI_INTF_IF_TYPE_2) {
1822 /*
1823 * On error status condition, driver need to wait for port
1824 * ready before performing reset.
1825 */
1826 rc = lpfc_sli4_pdev_status_reg_wait(phba);
0e916ee7 1827 if (rc)
65791f1f
JS
1828 return rc;
1829 }
0e916ee7 1830
65791f1f
JS
1831 /* need reset: attempt for port recovery */
1832 if (en_rn_msg)
372c187b 1833 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
1834 "2887 Reset Needed: Attempting Port "
1835 "Recovery...\n");
1836 lpfc_offline_prep(phba, mbx_action);
c00f62e6 1837 lpfc_sli_flush_io_rings(phba);
65791f1f
JS
1838 lpfc_offline(phba);
1839 /* release interrupt for possible resource change */
1840 lpfc_sli4_disable_intr(phba);
5a9eeff5
JS
1841 rc = lpfc_sli_brdrestart(phba);
1842 if (rc) {
372c187b 1843 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5a9eeff5
JS
1844 "6309 Failed to restart board\n");
1845 return rc;
1846 }
65791f1f
JS
1847 /* request and enable interrupt */
1848 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
1849 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 1850 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
1851 "3175 Failed to enable interrupt\n");
1852 return -EIO;
618a5230 1853 }
65791f1f
JS
1854 phba->intr_mode = intr_mode;
1855 rc = lpfc_online(phba);
1856 if (rc == 0)
1857 lpfc_unblock_mgmt_io(phba);
1858
618a5230
JS
1859 return rc;
1860}
1861
da0436e9
JS
1862/**
1863 * lpfc_handle_eratt_s4 - The SLI4 HBA hardware error handler
1864 * @phba: pointer to lpfc hba data structure.
1865 *
1866 * This routine is invoked to handle the SLI4 HBA hardware error attention
1867 * conditions.
1868 **/
1869static void
1870lpfc_handle_eratt_s4(struct lpfc_hba *phba)
1871{
1872 struct lpfc_vport *vport = phba->pport;
1873 uint32_t event_data;
1874 struct Scsi_Host *shost;
2fcee4bf 1875 uint32_t if_type;
2e90f4b5
JS
1876 struct lpfc_register portstat_reg = {0};
1877 uint32_t reg_err1, reg_err2;
1878 uint32_t uerrlo_reg, uemasklo_reg;
65791f1f 1879 uint32_t smphr_port_status = 0, pci_rd_rc1, pci_rd_rc2;
e10b2022 1880 bool en_rn_msg = true;
946727dc 1881 struct temp_event temp_event_data;
65791f1f
JS
1882 struct lpfc_register portsmphr_reg;
1883 int rc, i;
da0436e9
JS
1884
1885 /* If the pci channel is offline, ignore possible errors, since
1886 * we cannot communicate with the pci card anyway.
1887 */
32a93100 1888 if (pci_channel_offline(phba->pcidev)) {
372c187b 1889 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
32a93100
JS
1890 "3166 pci channel is offline\n");
1891 lpfc_sli4_offline_eratt(phba);
da0436e9 1892 return;
32a93100 1893 }
da0436e9 1894
65791f1f 1895 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
2fcee4bf
JS
1896 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
1897 switch (if_type) {
1898 case LPFC_SLI_INTF_IF_TYPE_0:
2e90f4b5
JS
1899 pci_rd_rc1 = lpfc_readl(
1900 phba->sli4_hba.u.if_type0.UERRLOregaddr,
1901 &uerrlo_reg);
1902 pci_rd_rc2 = lpfc_readl(
1903 phba->sli4_hba.u.if_type0.UEMASKLOregaddr,
1904 &uemasklo_reg);
1905 /* consider PCI bus read error as pci_channel_offline */
1906 if (pci_rd_rc1 == -EIO && pci_rd_rc2 == -EIO)
1907 return;
65791f1f
JS
1908 if (!(phba->hba_flag & HBA_RECOVERABLE_UE)) {
1909 lpfc_sli4_offline_eratt(phba);
1910 return;
1911 }
372c187b 1912 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
1913 "7623 Checking UE recoverable");
1914
1915 for (i = 0; i < phba->sli4_hba.ue_to_sr / 1000; i++) {
1916 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
1917 &portsmphr_reg.word0))
1918 continue;
1919
1920 smphr_port_status = bf_get(lpfc_port_smphr_port_status,
1921 &portsmphr_reg);
1922 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
1923 LPFC_PORT_SEM_UE_RECOVERABLE)
1924 break;
1925 /*Sleep for 1Sec, before checking SEMAPHORE */
1926 msleep(1000);
1927 }
1928
372c187b 1929 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
1930 "4827 smphr_port_status x%x : Waited %dSec",
1931 smphr_port_status, i);
1932
1933 /* Recoverable UE, reset the HBA device */
1934 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
1935 LPFC_PORT_SEM_UE_RECOVERABLE) {
1936 for (i = 0; i < 20; i++) {
1937 msleep(1000);
1938 if (!lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
1939 &portsmphr_reg.word0) &&
1940 (LPFC_POST_STAGE_PORT_READY ==
1941 bf_get(lpfc_port_smphr_port_status,
1942 &portsmphr_reg))) {
1943 rc = lpfc_sli4_port_sta_fn_reset(phba,
1944 LPFC_MBX_NO_WAIT, en_rn_msg);
1945 if (rc == 0)
1946 return;
372c187b
DK
1947 lpfc_printf_log(phba, KERN_ERR,
1948 LOG_TRACE_EVENT,
65791f1f
JS
1949 "4215 Failed to recover UE");
1950 break;
1951 }
1952 }
1953 }
372c187b 1954 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
65791f1f
JS
1955 "7624 Firmware not ready: Failing UE recovery,"
1956 " waited %dSec", i);
8c24a4f6 1957 phba->link_state = LPFC_HBA_ERROR;
2fcee4bf 1958 break;
946727dc 1959
2fcee4bf 1960 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 1961 case LPFC_SLI_INTF_IF_TYPE_6:
2e90f4b5
JS
1962 pci_rd_rc1 = lpfc_readl(
1963 phba->sli4_hba.u.if_type2.STATUSregaddr,
1964 &portstat_reg.word0);
1965 /* consider PCI bus read error as pci_channel_offline */
6b5151fd 1966 if (pci_rd_rc1 == -EIO) {
372c187b 1967 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
6b5151fd
JS
1968 "3151 PCI bus read access failure: x%x\n",
1969 readl(phba->sli4_hba.u.if_type2.STATUSregaddr));
32a93100 1970 lpfc_sli4_offline_eratt(phba);
2e90f4b5 1971 return;
6b5151fd 1972 }
2e90f4b5
JS
1973 reg_err1 = readl(phba->sli4_hba.u.if_type2.ERR1regaddr);
1974 reg_err2 = readl(phba->sli4_hba.u.if_type2.ERR2regaddr);
2fcee4bf 1975 if (bf_get(lpfc_sliport_status_oti, &portstat_reg)) {
372c187b
DK
1976 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1977 "2889 Port Overtemperature event, "
1978 "taking port offline Data: x%x x%x\n",
1979 reg_err1, reg_err2);
946727dc 1980
310429ef 1981 phba->sfp_alarm |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
946727dc
JS
1982 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1983 temp_event_data.event_code = LPFC_CRIT_TEMP;
1984 temp_event_data.data = 0xFFFFFFFF;
1985
1986 shost = lpfc_shost_from_vport(phba->pport);
1987 fc_host_post_vendor_event(shost, fc_get_event_number(),
1988 sizeof(temp_event_data),
1989 (char *)&temp_event_data,
1990 SCSI_NL_VID_TYPE_PCI
1991 | PCI_VENDOR_ID_EMULEX);
1992
2fcee4bf
JS
1993 spin_lock_irq(&phba->hbalock);
1994 phba->over_temp_state = HBA_OVER_TEMP;
1995 spin_unlock_irq(&phba->hbalock);
1996 lpfc_sli4_offline_eratt(phba);
946727dc 1997 return;
2fcee4bf 1998 }
2e90f4b5 1999 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
e10b2022 2000 reg_err2 == SLIPORT_ERR2_REG_FW_RESTART) {
372c187b 2001 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e10b2022
JS
2002 "3143 Port Down: Firmware Update "
2003 "Detected\n");
2004 en_rn_msg = false;
2005 } else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
2e90f4b5 2006 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
372c187b 2007 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2e90f4b5
JS
2008 "3144 Port Down: Debug Dump\n");
2009 else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
2010 reg_err2 == SLIPORT_ERR2_REG_FUNC_PROVISON)
372c187b 2011 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2e90f4b5 2012 "3145 Port Down: Provisioning\n");
618a5230 2013
946727dc
JS
2014 /* If resets are disabled then leave the HBA alone and return */
2015 if (!phba->cfg_enable_hba_reset)
2016 return;
2017
618a5230 2018 /* Check port status register for function reset */
e10b2022
JS
2019 rc = lpfc_sli4_port_sta_fn_reset(phba, LPFC_MBX_NO_WAIT,
2020 en_rn_msg);
618a5230
JS
2021 if (rc == 0) {
2022 /* don't report event on forced debug dump */
2023 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
2024 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
2025 return;
2026 else
2027 break;
2fcee4bf 2028 }
618a5230 2029 /* fall through for not able to recover */
372c187b 2030 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
8c24a4f6
JS
2031 "3152 Unrecoverable error\n");
2032 phba->link_state = LPFC_HBA_ERROR;
2fcee4bf
JS
2033 break;
2034 case LPFC_SLI_INTF_IF_TYPE_1:
2035 default:
2036 break;
2037 }
2e90f4b5
JS
2038 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
2039 "3123 Report dump event to upper layer\n");
2040 /* Send an internal error event to mgmt application */
2041 lpfc_board_errevt_to_mgmt(phba);
2042
2043 event_data = FC_REG_DUMP_EVENT;
2044 shost = lpfc_shost_from_vport(vport);
2045 fc_host_post_vendor_event(shost, fc_get_event_number(),
2046 sizeof(event_data), (char *) &event_data,
2047 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
da0436e9
JS
2048}
2049
2050/**
2051 * lpfc_handle_eratt - Wrapper func for handling hba error attention
2052 * @phba: pointer to lpfc HBA data structure.
2053 *
2054 * This routine wraps the actual SLI3 or SLI4 hba error attention handling
2055 * routine from the API jump table function pointer from the lpfc_hba struct.
2056 *
2057 * Return codes
af901ca1 2058 * 0 - success.
da0436e9
JS
2059 * Any other value - error.
2060 **/
2061void
2062lpfc_handle_eratt(struct lpfc_hba *phba)
2063{
2064 (*phba->lpfc_handle_eratt)(phba);
2065}
2066
e59058c4 2067/**
3621a710 2068 * lpfc_handle_latt - The HBA link event handler
e59058c4
JS
2069 * @phba: pointer to lpfc hba data structure.
2070 *
2071 * This routine is invoked from the worker thread to handle a HBA host
895427bd 2072 * attention link event. SLI3 only.
e59058c4 2073 **/
dea3101e 2074void
2e0fef85 2075lpfc_handle_latt(struct lpfc_hba *phba)
dea3101e 2076{
2e0fef85
JS
2077 struct lpfc_vport *vport = phba->pport;
2078 struct lpfc_sli *psli = &phba->sli;
dea3101e 2079 LPFC_MBOXQ_t *pmb;
2080 volatile uint32_t control;
2081 struct lpfc_dmabuf *mp;
09372820 2082 int rc = 0;
dea3101e 2083
2084 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
09372820
JS
2085 if (!pmb) {
2086 rc = 1;
dea3101e 2087 goto lpfc_handle_latt_err_exit;
09372820 2088 }
dea3101e 2089
2090 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
09372820
JS
2091 if (!mp) {
2092 rc = 2;
dea3101e 2093 goto lpfc_handle_latt_free_pmb;
09372820 2094 }
dea3101e 2095
2096 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
09372820
JS
2097 if (!mp->virt) {
2098 rc = 3;
dea3101e 2099 goto lpfc_handle_latt_free_mp;
09372820 2100 }
dea3101e 2101
6281bfe0 2102 /* Cleanup any outstanding ELS commands */
549e55cd 2103 lpfc_els_flush_all_cmd(phba);
dea3101e 2104
2105 psli->slistat.link_event++;
76a95d75
JS
2106 lpfc_read_topology(phba, pmb, mp);
2107 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
2e0fef85 2108 pmb->vport = vport;
0d2b6b83 2109 /* Block ELS IOCBs until we have processed this mbox command */
895427bd 2110 phba->sli.sli3_ring[LPFC_ELS_RING].flag |= LPFC_STOP_IOCB_EVENT;
0b727fea 2111 rc = lpfc_sli_issue_mbox (phba, pmb, MBX_NOWAIT);
09372820
JS
2112 if (rc == MBX_NOT_FINISHED) {
2113 rc = 4;
14691150 2114 goto lpfc_handle_latt_free_mbuf;
09372820 2115 }
dea3101e 2116
2117 /* Clear Link Attention in HA REG */
2e0fef85 2118 spin_lock_irq(&phba->hbalock);
dea3101e 2119 writel(HA_LATT, phba->HAregaddr);
2120 readl(phba->HAregaddr); /* flush */
2e0fef85 2121 spin_unlock_irq(&phba->hbalock);
dea3101e 2122
2123 return;
2124
14691150 2125lpfc_handle_latt_free_mbuf:
895427bd 2126 phba->sli.sli3_ring[LPFC_ELS_RING].flag &= ~LPFC_STOP_IOCB_EVENT;
14691150 2127 lpfc_mbuf_free(phba, mp->virt, mp->phys);
dea3101e 2128lpfc_handle_latt_free_mp:
2129 kfree(mp);
2130lpfc_handle_latt_free_pmb:
1dcb58e5 2131 mempool_free(pmb, phba->mbox_mem_pool);
dea3101e 2132lpfc_handle_latt_err_exit:
2133 /* Enable Link attention interrupts */
2e0fef85 2134 spin_lock_irq(&phba->hbalock);
dea3101e 2135 psli->sli_flag |= LPFC_PROCESS_LA;
2136 control = readl(phba->HCregaddr);
2137 control |= HC_LAINT_ENA;
2138 writel(control, phba->HCregaddr);
2139 readl(phba->HCregaddr); /* flush */
2140
2141 /* Clear Link Attention in HA REG */
2142 writel(HA_LATT, phba->HAregaddr);
2143 readl(phba->HAregaddr); /* flush */
2e0fef85 2144 spin_unlock_irq(&phba->hbalock);
dea3101e 2145 lpfc_linkdown(phba);
2e0fef85 2146 phba->link_state = LPFC_HBA_ERROR;
dea3101e 2147
372c187b
DK
2148 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2149 "0300 LATT: Cannot issue READ_LA: Data:%d\n", rc);
dea3101e 2150
2151 return;
2152}
2153
e59058c4 2154/**
3621a710 2155 * lpfc_parse_vpd - Parse VPD (Vital Product Data)
e59058c4
JS
2156 * @phba: pointer to lpfc hba data structure.
2157 * @vpd: pointer to the vital product data.
2158 * @len: length of the vital product data in bytes.
2159 *
2160 * This routine parses the Vital Product Data (VPD). The VPD is treated as
2161 * an array of characters. In this routine, the ModelName, ProgramType, and
2162 * ModelDesc, etc. fields of the phba data structure will be populated.
2163 *
2164 * Return codes
2165 * 0 - pointer to the VPD passed in is NULL
2166 * 1 - success
2167 **/
3772a991 2168int
2e0fef85 2169lpfc_parse_vpd(struct lpfc_hba *phba, uint8_t *vpd, int len)
dea3101e 2170{
2171 uint8_t lenlo, lenhi;
07da60c1 2172 int Length;
dea3101e 2173 int i, j;
2174 int finished = 0;
2175 int index = 0;
2176
2177 if (!vpd)
2178 return 0;
2179
2180 /* Vital Product */
ed957684 2181 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011 2182 "0455 Vital Product Data: x%x x%x x%x x%x\n",
dea3101e 2183 (uint32_t) vpd[0], (uint32_t) vpd[1], (uint32_t) vpd[2],
2184 (uint32_t) vpd[3]);
74b72a59 2185 while (!finished && (index < (len - 4))) {
dea3101e 2186 switch (vpd[index]) {
2187 case 0x82:
74b72a59 2188 case 0x91:
dea3101e 2189 index += 1;
2190 lenlo = vpd[index];
2191 index += 1;
2192 lenhi = vpd[index];
2193 index += 1;
2194 i = ((((unsigned short)lenhi) << 8) + lenlo);
2195 index += i;
2196 break;
2197 case 0x90:
2198 index += 1;
2199 lenlo = vpd[index];
2200 index += 1;
2201 lenhi = vpd[index];
2202 index += 1;
2203 Length = ((((unsigned short)lenhi) << 8) + lenlo);
74b72a59
JW
2204 if (Length > len - index)
2205 Length = len - index;
dea3101e 2206 while (Length > 0) {
2207 /* Look for Serial Number */
2208 if ((vpd[index] == 'S') && (vpd[index+1] == 'N')) {
2209 index += 2;
2210 i = vpd[index];
2211 index += 1;
2212 j = 0;
2213 Length -= (3+i);
2214 while(i--) {
2215 phba->SerialNumber[j++] = vpd[index++];
2216 if (j == 31)
2217 break;
2218 }
2219 phba->SerialNumber[j] = 0;
2220 continue;
2221 }
2222 else if ((vpd[index] == 'V') && (vpd[index+1] == '1')) {
2223 phba->vpd_flag |= VPD_MODEL_DESC;
2224 index += 2;
2225 i = vpd[index];
2226 index += 1;
2227 j = 0;
2228 Length -= (3+i);
2229 while(i--) {
2230 phba->ModelDesc[j++] = vpd[index++];
2231 if (j == 255)
2232 break;
2233 }
2234 phba->ModelDesc[j] = 0;
2235 continue;
2236 }
2237 else if ((vpd[index] == 'V') && (vpd[index+1] == '2')) {
2238 phba->vpd_flag |= VPD_MODEL_NAME;
2239 index += 2;
2240 i = vpd[index];
2241 index += 1;
2242 j = 0;
2243 Length -= (3+i);
2244 while(i--) {
2245 phba->ModelName[j++] = vpd[index++];
2246 if (j == 79)
2247 break;
2248 }
2249 phba->ModelName[j] = 0;
2250 continue;
2251 }
2252 else if ((vpd[index] == 'V') && (vpd[index+1] == '3')) {
2253 phba->vpd_flag |= VPD_PROGRAM_TYPE;
2254 index += 2;
2255 i = vpd[index];
2256 index += 1;
2257 j = 0;
2258 Length -= (3+i);
2259 while(i--) {
2260 phba->ProgramType[j++] = vpd[index++];
2261 if (j == 255)
2262 break;
2263 }
2264 phba->ProgramType[j] = 0;
2265 continue;
2266 }
2267 else if ((vpd[index] == 'V') && (vpd[index+1] == '4')) {
2268 phba->vpd_flag |= VPD_PORT;
2269 index += 2;
2270 i = vpd[index];
2271 index += 1;
2272 j = 0;
2273 Length -= (3+i);
2274 while(i--) {
cd1c8301
JS
2275 if ((phba->sli_rev == LPFC_SLI_REV4) &&
2276 (phba->sli4_hba.pport_name_sta ==
2277 LPFC_SLI4_PPNAME_GET)) {
2278 j++;
2279 index++;
2280 } else
2281 phba->Port[j++] = vpd[index++];
2282 if (j == 19)
2283 break;
dea3101e 2284 }
cd1c8301
JS
2285 if ((phba->sli_rev != LPFC_SLI_REV4) ||
2286 (phba->sli4_hba.pport_name_sta ==
2287 LPFC_SLI4_PPNAME_NON))
2288 phba->Port[j] = 0;
dea3101e 2289 continue;
2290 }
2291 else {
2292 index += 2;
2293 i = vpd[index];
2294 index += 1;
2295 index += i;
2296 Length -= (3 + i);
2297 }
2298 }
2299 finished = 0;
2300 break;
2301 case 0x78:
2302 finished = 1;
2303 break;
2304 default:
2305 index ++;
2306 break;
2307 }
74b72a59 2308 }
dea3101e 2309
2310 return(1);
2311}
2312
e59058c4 2313/**
3621a710 2314 * lpfc_get_hba_model_desc - Retrieve HBA device model name and description
e59058c4
JS
2315 * @phba: pointer to lpfc hba data structure.
2316 * @mdp: pointer to the data structure to hold the derived model name.
2317 * @descp: pointer to the data structure to hold the derived description.
2318 *
2319 * This routine retrieves HBA's description based on its registered PCI device
2320 * ID. The @descp passed into this function points to an array of 256 chars. It
2321 * shall be returned with the model name, maximum speed, and the host bus type.
2322 * The @mdp passed into this function points to an array of 80 chars. When the
2323 * function returns, the @mdp will be filled with the model name.
2324 **/
dea3101e 2325static void
2e0fef85 2326lpfc_get_hba_model_desc(struct lpfc_hba *phba, uint8_t *mdp, uint8_t *descp)
dea3101e 2327{
2328 lpfc_vpd_t *vp;
fefcb2b6 2329 uint16_t dev_id = phba->pcidev->device;
74b72a59 2330 int max_speed;
84774a4d 2331 int GE = 0;
da0436e9 2332 int oneConnect = 0; /* default is not a oneConnect */
74b72a59 2333 struct {
a747c9ce
JS
2334 char *name;
2335 char *bus;
2336 char *function;
2337 } m = {"<Unknown>", "", ""};
74b72a59
JW
2338
2339 if (mdp && mdp[0] != '\0'
2340 && descp && descp[0] != '\0')
2341 return;
2342
fbd8a6ba
JS
2343 if (phba->lmt & LMT_64Gb)
2344 max_speed = 64;
2345 else if (phba->lmt & LMT_32Gb)
d38dd52c
JS
2346 max_speed = 32;
2347 else if (phba->lmt & LMT_16Gb)
c0c11512
JS
2348 max_speed = 16;
2349 else if (phba->lmt & LMT_10Gb)
74b72a59
JW
2350 max_speed = 10;
2351 else if (phba->lmt & LMT_8Gb)
2352 max_speed = 8;
2353 else if (phba->lmt & LMT_4Gb)
2354 max_speed = 4;
2355 else if (phba->lmt & LMT_2Gb)
2356 max_speed = 2;
4169d868 2357 else if (phba->lmt & LMT_1Gb)
74b72a59 2358 max_speed = 1;
4169d868
JS
2359 else
2360 max_speed = 0;
dea3101e 2361
2362 vp = &phba->vpd;
dea3101e 2363
e4adb204 2364 switch (dev_id) {
06325e74 2365 case PCI_DEVICE_ID_FIREFLY:
12222f4f
JS
2366 m = (typeof(m)){"LP6000", "PCI",
2367 "Obsolete, Unsupported Fibre Channel Adapter"};
06325e74 2368 break;
dea3101e 2369 case PCI_DEVICE_ID_SUPERFLY:
2370 if (vp->rev.biuRev >= 1 && vp->rev.biuRev <= 3)
12222f4f 2371 m = (typeof(m)){"LP7000", "PCI", ""};
dea3101e 2372 else
12222f4f
JS
2373 m = (typeof(m)){"LP7000E", "PCI", ""};
2374 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
dea3101e 2375 break;
2376 case PCI_DEVICE_ID_DRAGONFLY:
a747c9ce 2377 m = (typeof(m)){"LP8000", "PCI",
12222f4f 2378 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2379 break;
2380 case PCI_DEVICE_ID_CENTAUR:
2381 if (FC_JEDEC_ID(vp->rev.biuRev) == CENTAUR_2G_JEDEC_ID)
12222f4f 2382 m = (typeof(m)){"LP9002", "PCI", ""};
dea3101e 2383 else
12222f4f
JS
2384 m = (typeof(m)){"LP9000", "PCI", ""};
2385 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
dea3101e 2386 break;
2387 case PCI_DEVICE_ID_RFLY:
a747c9ce 2388 m = (typeof(m)){"LP952", "PCI",
12222f4f 2389 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2390 break;
2391 case PCI_DEVICE_ID_PEGASUS:
a747c9ce 2392 m = (typeof(m)){"LP9802", "PCI-X",
12222f4f 2393 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2394 break;
2395 case PCI_DEVICE_ID_THOR:
a747c9ce 2396 m = (typeof(m)){"LP10000", "PCI-X",
12222f4f 2397 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2398 break;
2399 case PCI_DEVICE_ID_VIPER:
a747c9ce 2400 m = (typeof(m)){"LPX1000", "PCI-X",
12222f4f 2401 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2402 break;
2403 case PCI_DEVICE_ID_PFLY:
a747c9ce 2404 m = (typeof(m)){"LP982", "PCI-X",
12222f4f 2405 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2406 break;
2407 case PCI_DEVICE_ID_TFLY:
a747c9ce 2408 m = (typeof(m)){"LP1050", "PCI-X",
12222f4f 2409 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2410 break;
2411 case PCI_DEVICE_ID_HELIOS:
a747c9ce 2412 m = (typeof(m)){"LP11000", "PCI-X2",
12222f4f 2413 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2414 break;
e4adb204 2415 case PCI_DEVICE_ID_HELIOS_SCSP:
a747c9ce 2416 m = (typeof(m)){"LP11000-SP", "PCI-X2",
12222f4f 2417 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2418 break;
2419 case PCI_DEVICE_ID_HELIOS_DCSP:
a747c9ce 2420 m = (typeof(m)){"LP11002-SP", "PCI-X2",
12222f4f 2421 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2422 break;
2423 case PCI_DEVICE_ID_NEPTUNE:
12222f4f
JS
2424 m = (typeof(m)){"LPe1000", "PCIe",
2425 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2426 break;
2427 case PCI_DEVICE_ID_NEPTUNE_SCSP:
12222f4f
JS
2428 m = (typeof(m)){"LPe1000-SP", "PCIe",
2429 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2430 break;
2431 case PCI_DEVICE_ID_NEPTUNE_DCSP:
12222f4f
JS
2432 m = (typeof(m)){"LPe1002-SP", "PCIe",
2433 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204 2434 break;
dea3101e 2435 case PCI_DEVICE_ID_BMID:
a747c9ce 2436 m = (typeof(m)){"LP1150", "PCI-X2", "Fibre Channel Adapter"};
dea3101e 2437 break;
2438 case PCI_DEVICE_ID_BSMB:
12222f4f
JS
2439 m = (typeof(m)){"LP111", "PCI-X2",
2440 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2441 break;
2442 case PCI_DEVICE_ID_ZEPHYR:
a747c9ce 2443 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
dea3101e 2444 break;
e4adb204 2445 case PCI_DEVICE_ID_ZEPHYR_SCSP:
a747c9ce 2446 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
e4adb204
JSEC
2447 break;
2448 case PCI_DEVICE_ID_ZEPHYR_DCSP:
a747c9ce 2449 m = (typeof(m)){"LP2105", "PCIe", "FCoE Adapter"};
a257bf90 2450 GE = 1;
e4adb204 2451 break;
dea3101e 2452 case PCI_DEVICE_ID_ZMID:
a747c9ce 2453 m = (typeof(m)){"LPe1150", "PCIe", "Fibre Channel Adapter"};
dea3101e 2454 break;
2455 case PCI_DEVICE_ID_ZSMB:
a747c9ce 2456 m = (typeof(m)){"LPe111", "PCIe", "Fibre Channel Adapter"};
dea3101e 2457 break;
2458 case PCI_DEVICE_ID_LP101:
12222f4f
JS
2459 m = (typeof(m)){"LP101", "PCI-X",
2460 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2461 break;
2462 case PCI_DEVICE_ID_LP10000S:
12222f4f
JS
2463 m = (typeof(m)){"LP10000-S", "PCI",
2464 "Obsolete, Unsupported Fibre Channel Adapter"};
06325e74 2465 break;
e4adb204 2466 case PCI_DEVICE_ID_LP11000S:
12222f4f
JS
2467 m = (typeof(m)){"LP11000-S", "PCI-X2",
2468 "Obsolete, Unsupported Fibre Channel Adapter"};
18a3b596 2469 break;
e4adb204 2470 case PCI_DEVICE_ID_LPE11000S:
12222f4f
JS
2471 m = (typeof(m)){"LPe11000-S", "PCIe",
2472 "Obsolete, Unsupported Fibre Channel Adapter"};
5cc36b3c 2473 break;
b87eab38 2474 case PCI_DEVICE_ID_SAT:
a747c9ce 2475 m = (typeof(m)){"LPe12000", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2476 break;
2477 case PCI_DEVICE_ID_SAT_MID:
a747c9ce 2478 m = (typeof(m)){"LPe1250", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2479 break;
2480 case PCI_DEVICE_ID_SAT_SMB:
a747c9ce 2481 m = (typeof(m)){"LPe121", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2482 break;
2483 case PCI_DEVICE_ID_SAT_DCSP:
a747c9ce 2484 m = (typeof(m)){"LPe12002-SP", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2485 break;
2486 case PCI_DEVICE_ID_SAT_SCSP:
a747c9ce 2487 m = (typeof(m)){"LPe12000-SP", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2488 break;
2489 case PCI_DEVICE_ID_SAT_S:
a747c9ce 2490 m = (typeof(m)){"LPe12000-S", "PCIe", "Fibre Channel Adapter"};
b87eab38 2491 break;
84774a4d 2492 case PCI_DEVICE_ID_HORNET:
12222f4f
JS
2493 m = (typeof(m)){"LP21000", "PCIe",
2494 "Obsolete, Unsupported FCoE Adapter"};
84774a4d
JS
2495 GE = 1;
2496 break;
2497 case PCI_DEVICE_ID_PROTEUS_VF:
a747c9ce 2498 m = (typeof(m)){"LPev12000", "PCIe IOV",
12222f4f 2499 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d
JS
2500 break;
2501 case PCI_DEVICE_ID_PROTEUS_PF:
a747c9ce 2502 m = (typeof(m)){"LPev12000", "PCIe IOV",
12222f4f 2503 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d
JS
2504 break;
2505 case PCI_DEVICE_ID_PROTEUS_S:
a747c9ce 2506 m = (typeof(m)){"LPemv12002-S", "PCIe IOV",
12222f4f 2507 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d 2508 break;
da0436e9
JS
2509 case PCI_DEVICE_ID_TIGERSHARK:
2510 oneConnect = 1;
a747c9ce 2511 m = (typeof(m)){"OCe10100", "PCIe", "FCoE"};
da0436e9 2512 break;
a747c9ce 2513 case PCI_DEVICE_ID_TOMCAT:
6669f9bb 2514 oneConnect = 1;
a747c9ce
JS
2515 m = (typeof(m)){"OCe11100", "PCIe", "FCoE"};
2516 break;
2517 case PCI_DEVICE_ID_FALCON:
2518 m = (typeof(m)){"LPSe12002-ML1-E", "PCIe",
2519 "EmulexSecure Fibre"};
6669f9bb 2520 break;
98fc5dd9
JS
2521 case PCI_DEVICE_ID_BALIUS:
2522 m = (typeof(m)){"LPVe12002", "PCIe Shared I/O",
12222f4f 2523 "Obsolete, Unsupported Fibre Channel Adapter"};
98fc5dd9 2524 break;
085c647c 2525 case PCI_DEVICE_ID_LANCER_FC:
c0c11512 2526 m = (typeof(m)){"LPe16000", "PCIe", "Fibre Channel Adapter"};
085c647c 2527 break;
12222f4f
JS
2528 case PCI_DEVICE_ID_LANCER_FC_VF:
2529 m = (typeof(m)){"LPe16000", "PCIe",
2530 "Obsolete, Unsupported Fibre Channel Adapter"};
2531 break;
085c647c
JS
2532 case PCI_DEVICE_ID_LANCER_FCOE:
2533 oneConnect = 1;
079b5c91 2534 m = (typeof(m)){"OCe15100", "PCIe", "FCoE"};
085c647c 2535 break;
12222f4f
JS
2536 case PCI_DEVICE_ID_LANCER_FCOE_VF:
2537 oneConnect = 1;
2538 m = (typeof(m)){"OCe15100", "PCIe",
2539 "Obsolete, Unsupported FCoE"};
2540 break;
d38dd52c
JS
2541 case PCI_DEVICE_ID_LANCER_G6_FC:
2542 m = (typeof(m)){"LPe32000", "PCIe", "Fibre Channel Adapter"};
2543 break;
c238b9b6
JS
2544 case PCI_DEVICE_ID_LANCER_G7_FC:
2545 m = (typeof(m)){"LPe36000", "PCIe", "Fibre Channel Adapter"};
2546 break;
f8cafd38
JS
2547 case PCI_DEVICE_ID_SKYHAWK:
2548 case PCI_DEVICE_ID_SKYHAWK_VF:
2549 oneConnect = 1;
2550 m = (typeof(m)){"OCe14000", "PCIe", "FCoE"};
2551 break;
5cc36b3c 2552 default:
a747c9ce 2553 m = (typeof(m)){"Unknown", "", ""};
e4adb204 2554 break;
dea3101e 2555 }
74b72a59
JW
2556
2557 if (mdp && mdp[0] == '\0')
2558 snprintf(mdp, 79,"%s", m.name);
c0c11512
JS
2559 /*
2560 * oneConnect hba requires special processing, they are all initiators
da0436e9
JS
2561 * and we put the port number on the end
2562 */
2563 if (descp && descp[0] == '\0') {
2564 if (oneConnect)
2565 snprintf(descp, 255,
4169d868 2566 "Emulex OneConnect %s, %s Initiator %s",
a747c9ce 2567 m.name, m.function,
da0436e9 2568 phba->Port);
4169d868
JS
2569 else if (max_speed == 0)
2570 snprintf(descp, 255,
290237d2 2571 "Emulex %s %s %s",
4169d868 2572 m.name, m.bus, m.function);
da0436e9
JS
2573 else
2574 snprintf(descp, 255,
2575 "Emulex %s %d%s %s %s",
a747c9ce
JS
2576 m.name, max_speed, (GE) ? "GE" : "Gb",
2577 m.bus, m.function);
da0436e9 2578 }
dea3101e 2579}
2580
e59058c4 2581/**
3621a710 2582 * lpfc_post_buffer - Post IOCB(s) with DMA buffer descriptor(s) to a IOCB ring
e59058c4
JS
2583 * @phba: pointer to lpfc hba data structure.
2584 * @pring: pointer to a IOCB ring.
2585 * @cnt: the number of IOCBs to be posted to the IOCB ring.
2586 *
2587 * This routine posts a given number of IOCBs with the associated DMA buffer
2588 * descriptors specified by the cnt argument to the given IOCB ring.
2589 *
2590 * Return codes
2591 * The number of IOCBs NOT able to be posted to the IOCB ring.
2592 **/
dea3101e 2593int
495a714c 2594lpfc_post_buffer(struct lpfc_hba *phba, struct lpfc_sli_ring *pring, int cnt)
dea3101e 2595{
2596 IOCB_t *icmd;
0bd4ca25 2597 struct lpfc_iocbq *iocb;
dea3101e 2598 struct lpfc_dmabuf *mp1, *mp2;
2599
2600 cnt += pring->missbufcnt;
2601
2602 /* While there are buffers to post */
2603 while (cnt > 0) {
2604 /* Allocate buffer for command iocb */
0bd4ca25 2605 iocb = lpfc_sli_get_iocbq(phba);
dea3101e 2606 if (iocb == NULL) {
2607 pring->missbufcnt = cnt;
2608 return cnt;
2609 }
dea3101e 2610 icmd = &iocb->iocb;
2611
2612 /* 2 buffers can be posted per command */
2613 /* Allocate buffer to post */
2614 mp1 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2615 if (mp1)
98c9ea5c
JS
2616 mp1->virt = lpfc_mbuf_alloc(phba, MEM_PRI, &mp1->phys);
2617 if (!mp1 || !mp1->virt) {
c9475cb0 2618 kfree(mp1);
604a3e30 2619 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2620 pring->missbufcnt = cnt;
2621 return cnt;
2622 }
2623
2624 INIT_LIST_HEAD(&mp1->list);
2625 /* Allocate buffer to post */
2626 if (cnt > 1) {
2627 mp2 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2628 if (mp2)
2629 mp2->virt = lpfc_mbuf_alloc(phba, MEM_PRI,
2630 &mp2->phys);
98c9ea5c 2631 if (!mp2 || !mp2->virt) {
c9475cb0 2632 kfree(mp2);
dea3101e 2633 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2634 kfree(mp1);
604a3e30 2635 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2636 pring->missbufcnt = cnt;
2637 return cnt;
2638 }
2639
2640 INIT_LIST_HEAD(&mp2->list);
2641 } else {
2642 mp2 = NULL;
2643 }
2644
2645 icmd->un.cont64[0].addrHigh = putPaddrHigh(mp1->phys);
2646 icmd->un.cont64[0].addrLow = putPaddrLow(mp1->phys);
2647 icmd->un.cont64[0].tus.f.bdeSize = FCELSSIZE;
2648 icmd->ulpBdeCount = 1;
2649 cnt--;
2650 if (mp2) {
2651 icmd->un.cont64[1].addrHigh = putPaddrHigh(mp2->phys);
2652 icmd->un.cont64[1].addrLow = putPaddrLow(mp2->phys);
2653 icmd->un.cont64[1].tus.f.bdeSize = FCELSSIZE;
2654 cnt--;
2655 icmd->ulpBdeCount = 2;
2656 }
2657
2658 icmd->ulpCommand = CMD_QUE_RING_BUF64_CN;
2659 icmd->ulpLe = 1;
2660
3772a991
JS
2661 if (lpfc_sli_issue_iocb(phba, pring->ringno, iocb, 0) ==
2662 IOCB_ERROR) {
dea3101e 2663 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2664 kfree(mp1);
2665 cnt++;
2666 if (mp2) {
2667 lpfc_mbuf_free(phba, mp2->virt, mp2->phys);
2668 kfree(mp2);
2669 cnt++;
2670 }
604a3e30 2671 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2672 pring->missbufcnt = cnt;
dea3101e 2673 return cnt;
2674 }
dea3101e 2675 lpfc_sli_ringpostbuf_put(phba, pring, mp1);
92d7f7b0 2676 if (mp2)
dea3101e 2677 lpfc_sli_ringpostbuf_put(phba, pring, mp2);
dea3101e 2678 }
2679 pring->missbufcnt = 0;
2680 return 0;
2681}
2682
e59058c4 2683/**
3621a710 2684 * lpfc_post_rcv_buf - Post the initial receive IOCB buffers to ELS ring
e59058c4
JS
2685 * @phba: pointer to lpfc hba data structure.
2686 *
2687 * This routine posts initial receive IOCB buffers to the ELS ring. The
2688 * current number of initial IOCB buffers specified by LPFC_BUF_RING0 is
895427bd 2689 * set to 64 IOCBs. SLI3 only.
e59058c4
JS
2690 *
2691 * Return codes
2692 * 0 - success (currently always success)
2693 **/
dea3101e 2694static int
2e0fef85 2695lpfc_post_rcv_buf(struct lpfc_hba *phba)
dea3101e 2696{
2697 struct lpfc_sli *psli = &phba->sli;
2698
2699 /* Ring 0, ELS / CT buffers */
895427bd 2700 lpfc_post_buffer(phba, &psli->sli3_ring[LPFC_ELS_RING], LPFC_BUF_RING0);
dea3101e 2701 /* Ring 2 - FCP no buffers needed */
2702
2703 return 0;
2704}
2705
2706#define S(N,V) (((V)<<(N))|((V)>>(32-(N))))
2707
e59058c4 2708/**
3621a710 2709 * lpfc_sha_init - Set up initial array of hash table entries
e59058c4
JS
2710 * @HashResultPointer: pointer to an array as hash table.
2711 *
2712 * This routine sets up the initial values to the array of hash table entries
2713 * for the LC HBAs.
2714 **/
dea3101e 2715static void
2716lpfc_sha_init(uint32_t * HashResultPointer)
2717{
2718 HashResultPointer[0] = 0x67452301;
2719 HashResultPointer[1] = 0xEFCDAB89;
2720 HashResultPointer[2] = 0x98BADCFE;
2721 HashResultPointer[3] = 0x10325476;
2722 HashResultPointer[4] = 0xC3D2E1F0;
2723}
2724
e59058c4 2725/**
3621a710 2726 * lpfc_sha_iterate - Iterate initial hash table with the working hash table
e59058c4
JS
2727 * @HashResultPointer: pointer to an initial/result hash table.
2728 * @HashWorkingPointer: pointer to an working hash table.
2729 *
2730 * This routine iterates an initial hash table pointed by @HashResultPointer
2731 * with the values from the working hash table pointeed by @HashWorkingPointer.
2732 * The results are putting back to the initial hash table, returned through
2733 * the @HashResultPointer as the result hash table.
2734 **/
dea3101e 2735static void
2736lpfc_sha_iterate(uint32_t * HashResultPointer, uint32_t * HashWorkingPointer)
2737{
2738 int t;
2739 uint32_t TEMP;
2740 uint32_t A, B, C, D, E;
2741 t = 16;
2742 do {
2743 HashWorkingPointer[t] =
2744 S(1,
2745 HashWorkingPointer[t - 3] ^ HashWorkingPointer[t -
2746 8] ^
2747 HashWorkingPointer[t - 14] ^ HashWorkingPointer[t - 16]);
2748 } while (++t <= 79);
2749 t = 0;
2750 A = HashResultPointer[0];
2751 B = HashResultPointer[1];
2752 C = HashResultPointer[2];
2753 D = HashResultPointer[3];
2754 E = HashResultPointer[4];
2755
2756 do {
2757 if (t < 20) {
2758 TEMP = ((B & C) | ((~B) & D)) + 0x5A827999;
2759 } else if (t < 40) {
2760 TEMP = (B ^ C ^ D) + 0x6ED9EBA1;
2761 } else if (t < 60) {
2762 TEMP = ((B & C) | (B & D) | (C & D)) + 0x8F1BBCDC;
2763 } else {
2764 TEMP = (B ^ C ^ D) + 0xCA62C1D6;
2765 }
2766 TEMP += S(5, A) + E + HashWorkingPointer[t];
2767 E = D;
2768 D = C;
2769 C = S(30, B);
2770 B = A;
2771 A = TEMP;
2772 } while (++t <= 79);
2773
2774 HashResultPointer[0] += A;
2775 HashResultPointer[1] += B;
2776 HashResultPointer[2] += C;
2777 HashResultPointer[3] += D;
2778 HashResultPointer[4] += E;
2779
2780}
2781
e59058c4 2782/**
3621a710 2783 * lpfc_challenge_key - Create challenge key based on WWPN of the HBA
e59058c4
JS
2784 * @RandomChallenge: pointer to the entry of host challenge random number array.
2785 * @HashWorking: pointer to the entry of the working hash array.
2786 *
2787 * This routine calculates the working hash array referred by @HashWorking
2788 * from the challenge random numbers associated with the host, referred by
2789 * @RandomChallenge. The result is put into the entry of the working hash
2790 * array and returned by reference through @HashWorking.
2791 **/
dea3101e 2792static void
2793lpfc_challenge_key(uint32_t * RandomChallenge, uint32_t * HashWorking)
2794{
2795 *HashWorking = (*RandomChallenge ^ *HashWorking);
2796}
2797
e59058c4 2798/**
3621a710 2799 * lpfc_hba_init - Perform special handling for LC HBA initialization
e59058c4
JS
2800 * @phba: pointer to lpfc hba data structure.
2801 * @hbainit: pointer to an array of unsigned 32-bit integers.
2802 *
2803 * This routine performs the special handling for LC HBA initialization.
2804 **/
dea3101e 2805void
2806lpfc_hba_init(struct lpfc_hba *phba, uint32_t *hbainit)
2807{
2808 int t;
2809 uint32_t *HashWorking;
2e0fef85 2810 uint32_t *pwwnn = (uint32_t *) phba->wwnn;
dea3101e 2811
bbfbbbc1 2812 HashWorking = kcalloc(80, sizeof(uint32_t), GFP_KERNEL);
dea3101e 2813 if (!HashWorking)
2814 return;
2815
dea3101e 2816 HashWorking[0] = HashWorking[78] = *pwwnn++;
2817 HashWorking[1] = HashWorking[79] = *pwwnn;
2818
2819 for (t = 0; t < 7; t++)
2820 lpfc_challenge_key(phba->RandomData + t, HashWorking + t);
2821
2822 lpfc_sha_init(hbainit);
2823 lpfc_sha_iterate(hbainit, HashWorking);
2824 kfree(HashWorking);
2825}
2826
e59058c4 2827/**
3621a710 2828 * lpfc_cleanup - Performs vport cleanups before deleting a vport
e59058c4
JS
2829 * @vport: pointer to a virtual N_Port data structure.
2830 *
2831 * This routine performs the necessary cleanups before deleting the @vport.
2832 * It invokes the discovery state machine to perform necessary state
2833 * transitions and to release the ndlps associated with the @vport. Note,
2834 * the physical port is treated as @vport 0.
2835 **/
87af33fe 2836void
2e0fef85 2837lpfc_cleanup(struct lpfc_vport *vport)
dea3101e 2838{
87af33fe 2839 struct lpfc_hba *phba = vport->phba;
dea3101e 2840 struct lpfc_nodelist *ndlp, *next_ndlp;
a8adb832 2841 int i = 0;
dea3101e 2842
87af33fe
JS
2843 if (phba->link_state > LPFC_LINK_DOWN)
2844 lpfc_port_link_failure(vport);
2845
2846 list_for_each_entry_safe(ndlp, next_ndlp, &vport->fc_nodes, nlp_listp) {
e47c9093
JS
2847 if (!NLP_CHK_NODE_ACT(ndlp)) {
2848 ndlp = lpfc_enable_node(vport, ndlp,
2849 NLP_STE_UNUSED_NODE);
2850 if (!ndlp)
2851 continue;
2852 spin_lock_irq(&phba->ndlp_lock);
2853 NLP_SET_FREE_REQ(ndlp);
2854 spin_unlock_irq(&phba->ndlp_lock);
2855 /* Trigger the release of the ndlp memory */
2856 lpfc_nlp_put(ndlp);
2857 continue;
2858 }
2859 spin_lock_irq(&phba->ndlp_lock);
2860 if (NLP_CHK_FREE_REQ(ndlp)) {
2861 /* The ndlp should not be in memory free mode already */
2862 spin_unlock_irq(&phba->ndlp_lock);
2863 continue;
2864 } else
2865 /* Indicate request for freeing ndlp memory */
2866 NLP_SET_FREE_REQ(ndlp);
2867 spin_unlock_irq(&phba->ndlp_lock);
2868
58da1ffb
JS
2869 if (vport->port_type != LPFC_PHYSICAL_PORT &&
2870 ndlp->nlp_DID == Fabric_DID) {
2871 /* Just free up ndlp with Fabric_DID for vports */
2872 lpfc_nlp_put(ndlp);
2873 continue;
2874 }
2875
eff4a01b
JS
2876 /* take care of nodes in unused state before the state
2877 * machine taking action.
2878 */
2879 if (ndlp->nlp_state == NLP_STE_UNUSED_NODE) {
2880 lpfc_nlp_put(ndlp);
2881 continue;
2882 }
2883
87af33fe
JS
2884 if (ndlp->nlp_type & NLP_FABRIC)
2885 lpfc_disc_state_machine(vport, ndlp, NULL,
2886 NLP_EVT_DEVICE_RECOVERY);
e47c9093 2887
87af33fe
JS
2888 lpfc_disc_state_machine(vport, ndlp, NULL,
2889 NLP_EVT_DEVICE_RM);
2890 }
2891
a8adb832
JS
2892 /* At this point, ALL ndlp's should be gone
2893 * because of the previous NLP_EVT_DEVICE_RM.
2894 * Lets wait for this to happen, if needed.
2895 */
87af33fe 2896 while (!list_empty(&vport->fc_nodes)) {
a8adb832 2897 if (i++ > 3000) {
372c187b
DK
2898 lpfc_printf_vlog(vport, KERN_ERR,
2899 LOG_TRACE_EVENT,
a8adb832 2900 "0233 Nodelist not empty\n");
e47c9093
JS
2901 list_for_each_entry_safe(ndlp, next_ndlp,
2902 &vport->fc_nodes, nlp_listp) {
2903 lpfc_printf_vlog(ndlp->vport, KERN_ERR,
372c187b 2904 LOG_TRACE_EVENT,
32350664 2905 "0282 did:x%x ndlp:x%px "
e47c9093
JS
2906 "usgmap:x%x refcnt:%d\n",
2907 ndlp->nlp_DID, (void *)ndlp,
2908 ndlp->nlp_usg_map,
2c935bc5 2909 kref_read(&ndlp->kref));
e47c9093 2910 }
a8adb832 2911 break;
87af33fe 2912 }
a8adb832
JS
2913
2914 /* Wait for any activity on ndlps to settle */
2915 msleep(10);
87af33fe 2916 }
1151e3ec 2917 lpfc_cleanup_vports_rrqs(vport, NULL);
dea3101e 2918}
2919
e59058c4 2920/**
3621a710 2921 * lpfc_stop_vport_timers - Stop all the timers associated with a vport
e59058c4
JS
2922 * @vport: pointer to a virtual N_Port data structure.
2923 *
2924 * This routine stops all the timers associated with a @vport. This function
2925 * is invoked before disabling or deleting a @vport. Note that the physical
2926 * port is treated as @vport 0.
2927 **/
92d7f7b0
JS
2928void
2929lpfc_stop_vport_timers(struct lpfc_vport *vport)
dea3101e 2930{
92d7f7b0 2931 del_timer_sync(&vport->els_tmofunc);
92494144 2932 del_timer_sync(&vport->delayed_disc_tmo);
92d7f7b0
JS
2933 lpfc_can_disctmo(vport);
2934 return;
dea3101e 2935}
2936
ecfd03c6
JS
2937/**
2938 * __lpfc_sli4_stop_fcf_redisc_wait_timer - Stop FCF rediscovery wait timer
2939 * @phba: pointer to lpfc hba data structure.
2940 *
2941 * This routine stops the SLI4 FCF rediscover wait timer if it's on. The
2942 * caller of this routine should already hold the host lock.
2943 **/
2944void
2945__lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2946{
5ac6b303
JS
2947 /* Clear pending FCF rediscovery wait flag */
2948 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
2949
ecfd03c6
JS
2950 /* Now, try to stop the timer */
2951 del_timer(&phba->fcf.redisc_wait);
2952}
2953
2954/**
2955 * lpfc_sli4_stop_fcf_redisc_wait_timer - Stop FCF rediscovery wait timer
2956 * @phba: pointer to lpfc hba data structure.
2957 *
2958 * This routine stops the SLI4 FCF rediscover wait timer if it's on. It
2959 * checks whether the FCF rediscovery wait timer is pending with the host
2960 * lock held before proceeding with disabling the timer and clearing the
2961 * wait timer pendig flag.
2962 **/
2963void
2964lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2965{
2966 spin_lock_irq(&phba->hbalock);
2967 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
2968 /* FCF rediscovery timer already fired or stopped */
2969 spin_unlock_irq(&phba->hbalock);
2970 return;
2971 }
2972 __lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
5ac6b303
JS
2973 /* Clear failover in progress flags */
2974 phba->fcf.fcf_flag &= ~(FCF_DEAD_DISC | FCF_ACVL_DISC);
ecfd03c6
JS
2975 spin_unlock_irq(&phba->hbalock);
2976}
2977
e59058c4 2978/**
3772a991 2979 * lpfc_stop_hba_timers - Stop all the timers associated with an HBA
e59058c4
JS
2980 * @phba: pointer to lpfc hba data structure.
2981 *
2982 * This routine stops all the timers associated with a HBA. This function is
2983 * invoked before either putting a HBA offline or unloading the driver.
2984 **/
3772a991
JS
2985void
2986lpfc_stop_hba_timers(struct lpfc_hba *phba)
dea3101e 2987{
cdb42bec
JS
2988 if (phba->pport)
2989 lpfc_stop_vport_timers(phba->pport);
32517fc0 2990 cancel_delayed_work_sync(&phba->eq_delay_work);
317aeb83 2991 cancel_delayed_work_sync(&phba->idle_stat_delay_work);
2e0fef85 2992 del_timer_sync(&phba->sli.mbox_tmo);
92d7f7b0 2993 del_timer_sync(&phba->fabric_block_timer);
9399627f 2994 del_timer_sync(&phba->eratt_poll);
3772a991 2995 del_timer_sync(&phba->hb_tmofunc);
1151e3ec
JS
2996 if (phba->sli_rev == LPFC_SLI_REV4) {
2997 del_timer_sync(&phba->rrq_tmr);
2998 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
2999 }
3772a991
JS
3000 phba->hb_outstanding = 0;
3001
3002 switch (phba->pci_dev_grp) {
3003 case LPFC_PCI_DEV_LP:
3004 /* Stop any LightPulse device specific driver timers */
3005 del_timer_sync(&phba->fcp_poll_timer);
3006 break;
3007 case LPFC_PCI_DEV_OC:
cc0e5f1c 3008 /* Stop any OneConnect device specific driver timers */
ecfd03c6 3009 lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
3772a991
JS
3010 break;
3011 default:
372c187b 3012 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
3013 "0297 Invalid device group (x%x)\n",
3014 phba->pci_dev_grp);
3015 break;
3016 }
2e0fef85 3017 return;
dea3101e 3018}
3019
e59058c4 3020/**
3621a710 3021 * lpfc_block_mgmt_io - Mark a HBA's management interface as blocked
e59058c4 3022 * @phba: pointer to lpfc hba data structure.
fe614acd 3023 * @mbx_action: flag for mailbox no wait action.
e59058c4
JS
3024 *
3025 * This routine marks a HBA's management interface as blocked. Once the HBA's
3026 * management interface is marked as blocked, all the user space access to
3027 * the HBA, whether they are from sysfs interface or libdfc interface will
3028 * all be blocked. The HBA is set to block the management interface when the
3029 * driver prepares the HBA interface for online or offline.
3030 **/
a6ababd2 3031static void
618a5230 3032lpfc_block_mgmt_io(struct lpfc_hba *phba, int mbx_action)
a6ababd2
AB
3033{
3034 unsigned long iflag;
6e7288d9
JS
3035 uint8_t actcmd = MBX_HEARTBEAT;
3036 unsigned long timeout;
3037
a6ababd2
AB
3038 spin_lock_irqsave(&phba->hbalock, iflag);
3039 phba->sli.sli_flag |= LPFC_BLOCK_MGMT_IO;
618a5230
JS
3040 spin_unlock_irqrestore(&phba->hbalock, iflag);
3041 if (mbx_action == LPFC_MBX_NO_WAIT)
3042 return;
3043 timeout = msecs_to_jiffies(LPFC_MBOX_TMO * 1000) + jiffies;
3044 spin_lock_irqsave(&phba->hbalock, iflag);
a183a15f 3045 if (phba->sli.mbox_active) {
6e7288d9 3046 actcmd = phba->sli.mbox_active->u.mb.mbxCommand;
a183a15f
JS
3047 /* Determine how long we might wait for the active mailbox
3048 * command to be gracefully completed by firmware.
3049 */
3050 timeout = msecs_to_jiffies(lpfc_mbox_tmo_val(phba,
3051 phba->sli.mbox_active) * 1000) + jiffies;
3052 }
a6ababd2 3053 spin_unlock_irqrestore(&phba->hbalock, iflag);
a183a15f 3054
6e7288d9
JS
3055 /* Wait for the outstnading mailbox command to complete */
3056 while (phba->sli.mbox_active) {
3057 /* Check active mailbox complete status every 2ms */
3058 msleep(2);
3059 if (time_after(jiffies, timeout)) {
372c187b
DK
3060 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3061 "2813 Mgmt IO is Blocked %x "
3062 "- mbox cmd %x still active\n",
3063 phba->sli.sli_flag, actcmd);
6e7288d9
JS
3064 break;
3065 }
3066 }
a6ababd2
AB
3067}
3068
6b5151fd
JS
3069/**
3070 * lpfc_sli4_node_prep - Assign RPIs for active nodes.
3071 * @phba: pointer to lpfc hba data structure.
3072 *
3073 * Allocate RPIs for all active remote nodes. This is needed whenever
3074 * an SLI4 adapter is reset and the driver is not unloading. Its purpose
3075 * is to fixup the temporary rpi assignments.
3076 **/
3077void
3078lpfc_sli4_node_prep(struct lpfc_hba *phba)
3079{
3080 struct lpfc_nodelist *ndlp, *next_ndlp;
3081 struct lpfc_vport **vports;
9d3d340d
JS
3082 int i, rpi;
3083 unsigned long flags;
6b5151fd
JS
3084
3085 if (phba->sli_rev != LPFC_SLI_REV4)
3086 return;
3087
3088 vports = lpfc_create_vport_work_array(phba);
9d3d340d
JS
3089 if (vports == NULL)
3090 return;
6b5151fd 3091
9d3d340d
JS
3092 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
3093 if (vports[i]->load_flag & FC_UNLOADING)
3094 continue;
3095
3096 list_for_each_entry_safe(ndlp, next_ndlp,
3097 &vports[i]->fc_nodes,
3098 nlp_listp) {
3099 if (!NLP_CHK_NODE_ACT(ndlp))
3100 continue;
3101 rpi = lpfc_sli4_alloc_rpi(phba);
3102 if (rpi == LPFC_RPI_ALLOC_ERROR) {
3103 spin_lock_irqsave(&phba->ndlp_lock, flags);
3104 NLP_CLR_NODE_ACT(ndlp);
3105 spin_unlock_irqrestore(&phba->ndlp_lock, flags);
3106 continue;
6b5151fd 3107 }
9d3d340d 3108 ndlp->nlp_rpi = rpi;
0f154226
JS
3109 lpfc_printf_vlog(ndlp->vport, KERN_INFO,
3110 LOG_NODE | LOG_DISCOVERY,
3111 "0009 Assign RPI x%x to ndlp x%px "
3112 "DID:x%06x flg:x%x map:x%x\n",
3113 ndlp->nlp_rpi, ndlp, ndlp->nlp_DID,
3114 ndlp->nlp_flag, ndlp->nlp_usg_map);
6b5151fd
JS
3115 }
3116 }
3117 lpfc_destroy_vport_work_array(phba, vports);
3118}
3119
c490850a
JS
3120/**
3121 * lpfc_create_expedite_pool - create expedite pool
3122 * @phba: pointer to lpfc hba data structure.
3123 *
3124 * This routine moves a batch of XRIs from lpfc_io_buf_list_put of HWQ 0
3125 * to expedite pool. Mark them as expedite.
3126 **/
3999df75 3127static void lpfc_create_expedite_pool(struct lpfc_hba *phba)
c490850a
JS
3128{
3129 struct lpfc_sli4_hdw_queue *qp;
3130 struct lpfc_io_buf *lpfc_ncmd;
3131 struct lpfc_io_buf *lpfc_ncmd_next;
3132 struct lpfc_epd_pool *epd_pool;
3133 unsigned long iflag;
3134
3135 epd_pool = &phba->epd_pool;
3136 qp = &phba->sli4_hba.hdwq[0];
3137
3138 spin_lock_init(&epd_pool->lock);
3139 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3140 spin_lock(&epd_pool->lock);
3141 INIT_LIST_HEAD(&epd_pool->list);
3142 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3143 &qp->lpfc_io_buf_list_put, list) {
3144 list_move_tail(&lpfc_ncmd->list, &epd_pool->list);
3145 lpfc_ncmd->expedite = true;
3146 qp->put_io_bufs--;
3147 epd_pool->count++;
3148 if (epd_pool->count >= XRI_BATCH)
3149 break;
3150 }
3151 spin_unlock(&epd_pool->lock);
3152 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3153}
3154
3155/**
3156 * lpfc_destroy_expedite_pool - destroy expedite pool
3157 * @phba: pointer to lpfc hba data structure.
3158 *
3159 * This routine returns XRIs from expedite pool to lpfc_io_buf_list_put
3160 * of HWQ 0. Clear the mark.
3161 **/
3999df75 3162static void lpfc_destroy_expedite_pool(struct lpfc_hba *phba)
c490850a
JS
3163{
3164 struct lpfc_sli4_hdw_queue *qp;
3165 struct lpfc_io_buf *lpfc_ncmd;
3166 struct lpfc_io_buf *lpfc_ncmd_next;
3167 struct lpfc_epd_pool *epd_pool;
3168 unsigned long iflag;
3169
3170 epd_pool = &phba->epd_pool;
3171 qp = &phba->sli4_hba.hdwq[0];
3172
3173 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3174 spin_lock(&epd_pool->lock);
3175 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3176 &epd_pool->list, list) {
3177 list_move_tail(&lpfc_ncmd->list,
3178 &qp->lpfc_io_buf_list_put);
3179 lpfc_ncmd->flags = false;
3180 qp->put_io_bufs++;
3181 epd_pool->count--;
3182 }
3183 spin_unlock(&epd_pool->lock);
3184 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3185}
3186
3187/**
3188 * lpfc_create_multixri_pools - create multi-XRI pools
3189 * @phba: pointer to lpfc hba data structure.
3190 *
3191 * This routine initialize public, private per HWQ. Then, move XRIs from
3192 * lpfc_io_buf_list_put to public pool. High and low watermark are also
3193 * Initialized.
3194 **/
3195void lpfc_create_multixri_pools(struct lpfc_hba *phba)
3196{
3197 u32 i, j;
3198 u32 hwq_count;
3199 u32 count_per_hwq;
3200 struct lpfc_io_buf *lpfc_ncmd;
3201 struct lpfc_io_buf *lpfc_ncmd_next;
3202 unsigned long iflag;
3203 struct lpfc_sli4_hdw_queue *qp;
3204 struct lpfc_multixri_pool *multixri_pool;
3205 struct lpfc_pbl_pool *pbl_pool;
3206 struct lpfc_pvt_pool *pvt_pool;
3207
3208 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3209 "1234 num_hdw_queue=%d num_present_cpu=%d common_xri_cnt=%d\n",
3210 phba->cfg_hdw_queue, phba->sli4_hba.num_present_cpu,
3211 phba->sli4_hba.io_xri_cnt);
3212
3213 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3214 lpfc_create_expedite_pool(phba);
3215
3216 hwq_count = phba->cfg_hdw_queue;
3217 count_per_hwq = phba->sli4_hba.io_xri_cnt / hwq_count;
3218
3219 for (i = 0; i < hwq_count; i++) {
3220 multixri_pool = kzalloc(sizeof(*multixri_pool), GFP_KERNEL);
3221
3222 if (!multixri_pool) {
3223 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3224 "1238 Failed to allocate memory for "
3225 "multixri_pool\n");
3226
3227 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3228 lpfc_destroy_expedite_pool(phba);
3229
3230 j = 0;
3231 while (j < i) {
3232 qp = &phba->sli4_hba.hdwq[j];
3233 kfree(qp->p_multixri_pool);
3234 j++;
3235 }
3236 phba->cfg_xri_rebalancing = 0;
3237 return;
3238 }
3239
3240 qp = &phba->sli4_hba.hdwq[i];
3241 qp->p_multixri_pool = multixri_pool;
3242
3243 multixri_pool->xri_limit = count_per_hwq;
3244 multixri_pool->rrb_next_hwqid = i;
3245
3246 /* Deal with public free xri pool */
3247 pbl_pool = &multixri_pool->pbl_pool;
3248 spin_lock_init(&pbl_pool->lock);
3249 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3250 spin_lock(&pbl_pool->lock);
3251 INIT_LIST_HEAD(&pbl_pool->list);
3252 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3253 &qp->lpfc_io_buf_list_put, list) {
3254 list_move_tail(&lpfc_ncmd->list, &pbl_pool->list);
3255 qp->put_io_bufs--;
3256 pbl_pool->count++;
3257 }
3258 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3259 "1235 Moved %d buffers from PUT list over to pbl_pool[%d]\n",
3260 pbl_pool->count, i);
3261 spin_unlock(&pbl_pool->lock);
3262 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3263
3264 /* Deal with private free xri pool */
3265 pvt_pool = &multixri_pool->pvt_pool;
3266 pvt_pool->high_watermark = multixri_pool->xri_limit / 2;
3267 pvt_pool->low_watermark = XRI_BATCH;
3268 spin_lock_init(&pvt_pool->lock);
3269 spin_lock_irqsave(&pvt_pool->lock, iflag);
3270 INIT_LIST_HEAD(&pvt_pool->list);
3271 pvt_pool->count = 0;
3272 spin_unlock_irqrestore(&pvt_pool->lock, iflag);
3273 }
3274}
3275
3276/**
3277 * lpfc_destroy_multixri_pools - destroy multi-XRI pools
3278 * @phba: pointer to lpfc hba data structure.
3279 *
3280 * This routine returns XRIs from public/private to lpfc_io_buf_list_put.
3281 **/
3999df75 3282static void lpfc_destroy_multixri_pools(struct lpfc_hba *phba)
c490850a
JS
3283{
3284 u32 i;
3285 u32 hwq_count;
3286 struct lpfc_io_buf *lpfc_ncmd;
3287 struct lpfc_io_buf *lpfc_ncmd_next;
3288 unsigned long iflag;
3289 struct lpfc_sli4_hdw_queue *qp;
3290 struct lpfc_multixri_pool *multixri_pool;
3291 struct lpfc_pbl_pool *pbl_pool;
3292 struct lpfc_pvt_pool *pvt_pool;
3293
3294 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3295 lpfc_destroy_expedite_pool(phba);
3296
c00f62e6
JS
3297 if (!(phba->pport->load_flag & FC_UNLOADING))
3298 lpfc_sli_flush_io_rings(phba);
c66a9197 3299
c490850a
JS
3300 hwq_count = phba->cfg_hdw_queue;
3301
3302 for (i = 0; i < hwq_count; i++) {
3303 qp = &phba->sli4_hba.hdwq[i];
3304 multixri_pool = qp->p_multixri_pool;
3305 if (!multixri_pool)
3306 continue;
3307
3308 qp->p_multixri_pool = NULL;
3309
3310 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3311
3312 /* Deal with public free xri pool */
3313 pbl_pool = &multixri_pool->pbl_pool;
3314 spin_lock(&pbl_pool->lock);
3315
3316 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3317 "1236 Moving %d buffers from pbl_pool[%d] TO PUT list\n",
3318 pbl_pool->count, i);
3319
3320 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3321 &pbl_pool->list, list) {
3322 list_move_tail(&lpfc_ncmd->list,
3323 &qp->lpfc_io_buf_list_put);
3324 qp->put_io_bufs++;
3325 pbl_pool->count--;
3326 }
3327
3328 INIT_LIST_HEAD(&pbl_pool->list);
3329 pbl_pool->count = 0;
3330
3331 spin_unlock(&pbl_pool->lock);
3332
3333 /* Deal with private free xri pool */
3334 pvt_pool = &multixri_pool->pvt_pool;
3335 spin_lock(&pvt_pool->lock);
3336
3337 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3338 "1237 Moving %d buffers from pvt_pool[%d] TO PUT list\n",
3339 pvt_pool->count, i);
3340
3341 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3342 &pvt_pool->list, list) {
3343 list_move_tail(&lpfc_ncmd->list,
3344 &qp->lpfc_io_buf_list_put);
3345 qp->put_io_bufs++;
3346 pvt_pool->count--;
3347 }
3348
3349 INIT_LIST_HEAD(&pvt_pool->list);
3350 pvt_pool->count = 0;
3351
3352 spin_unlock(&pvt_pool->lock);
3353 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3354
3355 kfree(multixri_pool);
3356 }
3357}
3358
e59058c4 3359/**
3621a710 3360 * lpfc_online - Initialize and bring a HBA online
e59058c4
JS
3361 * @phba: pointer to lpfc hba data structure.
3362 *
3363 * This routine initializes the HBA and brings a HBA online. During this
3364 * process, the management interface is blocked to prevent user space access
3365 * to the HBA interfering with the driver initialization.
3366 *
3367 * Return codes
3368 * 0 - successful
3369 * 1 - failed
3370 **/
dea3101e 3371int
2e0fef85 3372lpfc_online(struct lpfc_hba *phba)
dea3101e 3373{
372bd282 3374 struct lpfc_vport *vport;
549e55cd 3375 struct lpfc_vport **vports;
a145fda3 3376 int i, error = 0;
16a3a208 3377 bool vpis_cleared = false;
2e0fef85 3378
dea3101e 3379 if (!phba)
3380 return 0;
372bd282 3381 vport = phba->pport;
dea3101e 3382
2e0fef85 3383 if (!(vport->fc_flag & FC_OFFLINE_MODE))
dea3101e 3384 return 0;
3385
ed957684 3386 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
e8b62011 3387 "0458 Bring Adapter online\n");
dea3101e 3388
618a5230 3389 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
46fa311e 3390
da0436e9
JS
3391 if (phba->sli_rev == LPFC_SLI_REV4) {
3392 if (lpfc_sli4_hba_setup(phba)) { /* Initialize SLI4 HBA */
3393 lpfc_unblock_mgmt_io(phba);
3394 return 1;
3395 }
16a3a208
JS
3396 spin_lock_irq(&phba->hbalock);
3397 if (!phba->sli4_hba.max_cfg_param.vpi_used)
3398 vpis_cleared = true;
3399 spin_unlock_irq(&phba->hbalock);
a145fda3
DK
3400
3401 /* Reestablish the local initiator port.
3402 * The offline process destroyed the previous lport.
3403 */
3404 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME &&
3405 !phba->nvmet_support) {
3406 error = lpfc_nvme_create_localport(phba->pport);
3407 if (error)
372c187b 3408 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
a145fda3
DK
3409 "6132 NVME restore reg failed "
3410 "on nvmei error x%x\n", error);
3411 }
da0436e9 3412 } else {
895427bd 3413 lpfc_sli_queue_init(phba);
da0436e9
JS
3414 if (lpfc_sli_hba_setup(phba)) { /* Initialize SLI2/SLI3 HBA */
3415 lpfc_unblock_mgmt_io(phba);
3416 return 1;
3417 }
46fa311e 3418 }
dea3101e 3419
549e55cd 3420 vports = lpfc_create_vport_work_array(phba);
aeb6641f 3421 if (vports != NULL) {
da0436e9 3422 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
549e55cd
JS
3423 struct Scsi_Host *shost;
3424 shost = lpfc_shost_from_vport(vports[i]);
3425 spin_lock_irq(shost->host_lock);
3426 vports[i]->fc_flag &= ~FC_OFFLINE_MODE;
3427 if (phba->sli3_options & LPFC_SLI3_NPIV_ENABLED)
3428 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
16a3a208 3429 if (phba->sli_rev == LPFC_SLI_REV4) {
1c6834a7 3430 vports[i]->fc_flag |= FC_VPORT_NEEDS_INIT_VPI;
16a3a208
JS
3431 if ((vpis_cleared) &&
3432 (vports[i]->port_type !=
3433 LPFC_PHYSICAL_PORT))
3434 vports[i]->vpi = 0;
3435 }
549e55cd
JS
3436 spin_unlock_irq(shost->host_lock);
3437 }
aeb6641f
AB
3438 }
3439 lpfc_destroy_vport_work_array(phba, vports);
dea3101e 3440
c490850a
JS
3441 if (phba->cfg_xri_rebalancing)
3442 lpfc_create_multixri_pools(phba);
3443
93a4d6f4
JS
3444 lpfc_cpuhp_add(phba);
3445
46fa311e 3446 lpfc_unblock_mgmt_io(phba);
dea3101e 3447 return 0;
3448}
3449
e59058c4 3450/**
3621a710 3451 * lpfc_unblock_mgmt_io - Mark a HBA's management interface to be not blocked
e59058c4
JS
3452 * @phba: pointer to lpfc hba data structure.
3453 *
3454 * This routine marks a HBA's management interface as not blocked. Once the
3455 * HBA's management interface is marked as not blocked, all the user space
3456 * access to the HBA, whether they are from sysfs interface or libdfc
3457 * interface will be allowed. The HBA is set to block the management interface
3458 * when the driver prepares the HBA interface for online or offline and then
3459 * set to unblock the management interface afterwards.
3460 **/
46fa311e
JS
3461void
3462lpfc_unblock_mgmt_io(struct lpfc_hba * phba)
3463{
3464 unsigned long iflag;
3465
2e0fef85
JS
3466 spin_lock_irqsave(&phba->hbalock, iflag);
3467 phba->sli.sli_flag &= ~LPFC_BLOCK_MGMT_IO;
3468 spin_unlock_irqrestore(&phba->hbalock, iflag);
46fa311e
JS
3469}
3470
e59058c4 3471/**
3621a710 3472 * lpfc_offline_prep - Prepare a HBA to be brought offline
e59058c4 3473 * @phba: pointer to lpfc hba data structure.
fe614acd 3474 * @mbx_action: flag for mailbox shutdown action.
e59058c4
JS
3475 *
3476 * This routine is invoked to prepare a HBA to be brought offline. It performs
3477 * unregistration login to all the nodes on all vports and flushes the mailbox
3478 * queue to make it ready to be brought offline.
3479 **/
46fa311e 3480void
618a5230 3481lpfc_offline_prep(struct lpfc_hba *phba, int mbx_action)
46fa311e 3482{
2e0fef85 3483 struct lpfc_vport *vport = phba->pport;
46fa311e 3484 struct lpfc_nodelist *ndlp, *next_ndlp;
87af33fe 3485 struct lpfc_vport **vports;
72100cc4 3486 struct Scsi_Host *shost;
87af33fe 3487 int i;
dea3101e 3488
2e0fef85 3489 if (vport->fc_flag & FC_OFFLINE_MODE)
46fa311e 3490 return;
dea3101e 3491
618a5230 3492 lpfc_block_mgmt_io(phba, mbx_action);
dea3101e 3493
3494 lpfc_linkdown(phba);
3495
87af33fe
JS
3496 /* Issue an unreg_login to all nodes on all vports */
3497 vports = lpfc_create_vport_work_array(phba);
3498 if (vports != NULL) {
da0436e9 3499 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
a8adb832
JS
3500 if (vports[i]->load_flag & FC_UNLOADING)
3501 continue;
72100cc4
JS
3502 shost = lpfc_shost_from_vport(vports[i]);
3503 spin_lock_irq(shost->host_lock);
c868595d 3504 vports[i]->vpi_state &= ~LPFC_VPI_REGISTERED;
695a814e
JS
3505 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
3506 vports[i]->fc_flag &= ~FC_VFI_REGISTERED;
72100cc4 3507 spin_unlock_irq(shost->host_lock);
695a814e 3508
87af33fe
JS
3509 shost = lpfc_shost_from_vport(vports[i]);
3510 list_for_each_entry_safe(ndlp, next_ndlp,
3511 &vports[i]->fc_nodes,
3512 nlp_listp) {
0f154226
JS
3513 if ((!NLP_CHK_NODE_ACT(ndlp)) ||
3514 ndlp->nlp_state == NLP_STE_UNUSED_NODE) {
3515 /* Driver must assume RPI is invalid for
3516 * any unused or inactive node.
3517 */
3518 ndlp->nlp_rpi = LPFC_RPI_ALLOC_ERROR;
87af33fe 3519 continue;
0f154226
JS
3520 }
3521
87af33fe
JS
3522 if (ndlp->nlp_type & NLP_FABRIC) {
3523 lpfc_disc_state_machine(vports[i], ndlp,
3524 NULL, NLP_EVT_DEVICE_RECOVERY);
3525 lpfc_disc_state_machine(vports[i], ndlp,
3526 NULL, NLP_EVT_DEVICE_RM);
3527 }
3528 spin_lock_irq(shost->host_lock);
3529 ndlp->nlp_flag &= ~NLP_NPR_ADISC;
401ee0c1 3530 spin_unlock_irq(shost->host_lock);
6b5151fd
JS
3531 /*
3532 * Whenever an SLI4 port goes offline, free the
401ee0c1
JS
3533 * RPI. Get a new RPI when the adapter port
3534 * comes back online.
6b5151fd 3535 */
be6bb941 3536 if (phba->sli_rev == LPFC_SLI_REV4) {
0f154226
JS
3537 lpfc_printf_vlog(ndlp->vport, KERN_INFO,
3538 LOG_NODE | LOG_DISCOVERY,
3539 "0011 Free RPI x%x on "
3540 "ndlp:x%px did x%x "
3541 "usgmap:x%x\n",
3542 ndlp->nlp_rpi, ndlp,
3543 ndlp->nlp_DID,
3544 ndlp->nlp_usg_map);
6b5151fd 3545 lpfc_sli4_free_rpi(phba, ndlp->nlp_rpi);
0f154226 3546 ndlp->nlp_rpi = LPFC_RPI_ALLOC_ERROR;
be6bb941 3547 }
87af33fe
JS
3548 lpfc_unreg_rpi(vports[i], ndlp);
3549 }
3550 }
3551 }
09372820 3552 lpfc_destroy_vport_work_array(phba, vports);
dea3101e 3553
618a5230 3554 lpfc_sli_mbox_sys_shutdown(phba, mbx_action);
f485c18d
DK
3555
3556 if (phba->wq)
3557 flush_workqueue(phba->wq);
46fa311e
JS
3558}
3559
e59058c4 3560/**
3621a710 3561 * lpfc_offline - Bring a HBA offline
e59058c4
JS
3562 * @phba: pointer to lpfc hba data structure.
3563 *
3564 * This routine actually brings a HBA offline. It stops all the timers
3565 * associated with the HBA, brings down the SLI layer, and eventually
3566 * marks the HBA as in offline state for the upper layer protocol.
3567 **/
46fa311e 3568void
2e0fef85 3569lpfc_offline(struct lpfc_hba *phba)
46fa311e 3570{
549e55cd
JS
3571 struct Scsi_Host *shost;
3572 struct lpfc_vport **vports;
3573 int i;
46fa311e 3574
549e55cd 3575 if (phba->pport->fc_flag & FC_OFFLINE_MODE)
46fa311e 3576 return;
688a8863 3577
da0436e9
JS
3578 /* stop port and all timers associated with this hba */
3579 lpfc_stop_port(phba);
4b40d02b
DK
3580
3581 /* Tear down the local and target port registrations. The
3582 * nvme transports need to cleanup.
3583 */
3584 lpfc_nvmet_destroy_targetport(phba);
3585 lpfc_nvme_destroy_localport(phba->pport);
3586
51ef4c26
JS
3587 vports = lpfc_create_vport_work_array(phba);
3588 if (vports != NULL)
da0436e9 3589 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
51ef4c26 3590 lpfc_stop_vport_timers(vports[i]);
09372820 3591 lpfc_destroy_vport_work_array(phba, vports);
92d7f7b0 3592 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
e8b62011 3593 "0460 Bring Adapter offline\n");
dea3101e 3594 /* Bring down the SLI Layer and cleanup. The HBA is offline
3595 now. */
3596 lpfc_sli_hba_down(phba);
92d7f7b0 3597 spin_lock_irq(&phba->hbalock);
7054a606 3598 phba->work_ha = 0;
92d7f7b0 3599 spin_unlock_irq(&phba->hbalock);
549e55cd
JS
3600 vports = lpfc_create_vport_work_array(phba);
3601 if (vports != NULL)
da0436e9 3602 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
549e55cd 3603 shost = lpfc_shost_from_vport(vports[i]);
549e55cd
JS
3604 spin_lock_irq(shost->host_lock);
3605 vports[i]->work_port_events = 0;
3606 vports[i]->fc_flag |= FC_OFFLINE_MODE;
3607 spin_unlock_irq(shost->host_lock);
3608 }
09372820 3609 lpfc_destroy_vport_work_array(phba, vports);
93a4d6f4 3610 __lpfc_cpuhp_remove(phba);
c490850a
JS
3611
3612 if (phba->cfg_xri_rebalancing)
3613 lpfc_destroy_multixri_pools(phba);
dea3101e 3614}
3615
e59058c4 3616/**
3621a710 3617 * lpfc_scsi_free - Free all the SCSI buffers and IOCBs from driver lists
e59058c4
JS
3618 * @phba: pointer to lpfc hba data structure.
3619 *
3620 * This routine is to free all the SCSI buffers and IOCBs from the driver
3621 * list back to kernel. It is called from lpfc_pci_remove_one to free
3622 * the internal resources before the device is removed from the system.
e59058c4 3623 **/
8a9d2e80 3624static void
2e0fef85 3625lpfc_scsi_free(struct lpfc_hba *phba)
dea3101e 3626{
c490850a 3627 struct lpfc_io_buf *sb, *sb_next;
dea3101e 3628
895427bd
JS
3629 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
3630 return;
3631
2e0fef85 3632 spin_lock_irq(&phba->hbalock);
a40fc5f0 3633
dea3101e 3634 /* Release all the lpfc_scsi_bufs maintained by this host. */
a40fc5f0
JS
3635
3636 spin_lock(&phba->scsi_buf_list_put_lock);
3637 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_put,
3638 list) {
dea3101e 3639 list_del(&sb->list);
771db5c0 3640 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
92d7f7b0 3641 sb->dma_handle);
dea3101e 3642 kfree(sb);
3643 phba->total_scsi_bufs--;
3644 }
a40fc5f0
JS
3645 spin_unlock(&phba->scsi_buf_list_put_lock);
3646
3647 spin_lock(&phba->scsi_buf_list_get_lock);
3648 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_get,
3649 list) {
dea3101e 3650 list_del(&sb->list);
771db5c0 3651 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
92d7f7b0 3652 sb->dma_handle);
dea3101e 3653 kfree(sb);
3654 phba->total_scsi_bufs--;
3655 }
a40fc5f0 3656 spin_unlock(&phba->scsi_buf_list_get_lock);
2e0fef85 3657 spin_unlock_irq(&phba->hbalock);
8a9d2e80 3658}
0794d601 3659
895427bd 3660/**
5e5b511d 3661 * lpfc_io_free - Free all the IO buffers and IOCBs from driver lists
895427bd
JS
3662 * @phba: pointer to lpfc hba data structure.
3663 *
0794d601 3664 * This routine is to free all the IO buffers and IOCBs from the driver
895427bd
JS
3665 * list back to kernel. It is called from lpfc_pci_remove_one to free
3666 * the internal resources before the device is removed from the system.
3667 **/
c490850a 3668void
5e5b511d 3669lpfc_io_free(struct lpfc_hba *phba)
895427bd 3670{
c490850a 3671 struct lpfc_io_buf *lpfc_ncmd, *lpfc_ncmd_next;
5e5b511d
JS
3672 struct lpfc_sli4_hdw_queue *qp;
3673 int idx;
895427bd 3674
5e5b511d
JS
3675 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3676 qp = &phba->sli4_hba.hdwq[idx];
3677 /* Release all the lpfc_nvme_bufs maintained by this host. */
3678 spin_lock(&qp->io_buf_list_put_lock);
3679 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3680 &qp->lpfc_io_buf_list_put,
3681 list) {
3682 list_del(&lpfc_ncmd->list);
3683 qp->put_io_bufs--;
3684 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3685 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
d79c9e9d
JS
3686 if (phba->cfg_xpsgl && !phba->nvmet_support)
3687 lpfc_put_sgl_per_hdwq(phba, lpfc_ncmd);
3688 lpfc_put_cmd_rsp_buf_per_hdwq(phba, lpfc_ncmd);
5e5b511d
JS
3689 kfree(lpfc_ncmd);
3690 qp->total_io_bufs--;
3691 }
3692 spin_unlock(&qp->io_buf_list_put_lock);
3693
3694 spin_lock(&qp->io_buf_list_get_lock);
3695 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3696 &qp->lpfc_io_buf_list_get,
3697 list) {
3698 list_del(&lpfc_ncmd->list);
3699 qp->get_io_bufs--;
3700 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3701 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
d79c9e9d
JS
3702 if (phba->cfg_xpsgl && !phba->nvmet_support)
3703 lpfc_put_sgl_per_hdwq(phba, lpfc_ncmd);
3704 lpfc_put_cmd_rsp_buf_per_hdwq(phba, lpfc_ncmd);
5e5b511d
JS
3705 kfree(lpfc_ncmd);
3706 qp->total_io_bufs--;
3707 }
3708 spin_unlock(&qp->io_buf_list_get_lock);
895427bd 3709 }
895427bd 3710}
0794d601 3711
8a9d2e80 3712/**
895427bd 3713 * lpfc_sli4_els_sgl_update - update ELS xri-sgl sizing and mapping
8a9d2e80
JS
3714 * @phba: pointer to lpfc hba data structure.
3715 *
3716 * This routine first calculates the sizes of the current els and allocated
3717 * scsi sgl lists, and then goes through all sgls to updates the physical
3718 * XRIs assigned due to port function reset. During port initialization, the
3719 * current els and allocated scsi sgl lists are 0s.
3720 *
3721 * Return codes
3722 * 0 - successful (for now, it always returns 0)
3723 **/
3724int
895427bd 3725lpfc_sli4_els_sgl_update(struct lpfc_hba *phba)
8a9d2e80
JS
3726{
3727 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
895427bd 3728 uint16_t i, lxri, xri_cnt, els_xri_cnt;
8a9d2e80 3729 LIST_HEAD(els_sgl_list);
8a9d2e80
JS
3730 int rc;
3731
3732 /*
3733 * update on pci function's els xri-sgl list
3734 */
3735 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
895427bd 3736
8a9d2e80
JS
3737 if (els_xri_cnt > phba->sli4_hba.els_xri_cnt) {
3738 /* els xri-sgl expanded */
3739 xri_cnt = els_xri_cnt - phba->sli4_hba.els_xri_cnt;
3740 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3741 "3157 ELS xri-sgl count increased from "
3742 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3743 els_xri_cnt);
3744 /* allocate the additional els sgls */
3745 for (i = 0; i < xri_cnt; i++) {
3746 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3747 GFP_KERNEL);
3748 if (sglq_entry == NULL) {
372c187b
DK
3749 lpfc_printf_log(phba, KERN_ERR,
3750 LOG_TRACE_EVENT,
8a9d2e80
JS
3751 "2562 Failure to allocate an "
3752 "ELS sgl entry:%d\n", i);
3753 rc = -ENOMEM;
3754 goto out_free_mem;
3755 }
3756 sglq_entry->buff_type = GEN_BUFF_TYPE;
3757 sglq_entry->virt = lpfc_mbuf_alloc(phba, 0,
3758 &sglq_entry->phys);
3759 if (sglq_entry->virt == NULL) {
3760 kfree(sglq_entry);
372c187b
DK
3761 lpfc_printf_log(phba, KERN_ERR,
3762 LOG_TRACE_EVENT,
8a9d2e80
JS
3763 "2563 Failure to allocate an "
3764 "ELS mbuf:%d\n", i);
3765 rc = -ENOMEM;
3766 goto out_free_mem;
3767 }
3768 sglq_entry->sgl = sglq_entry->virt;
3769 memset(sglq_entry->sgl, 0, LPFC_BPL_SIZE);
3770 sglq_entry->state = SGL_FREED;
3771 list_add_tail(&sglq_entry->list, &els_sgl_list);
3772 }
38c20673 3773 spin_lock_irq(&phba->hbalock);
895427bd
JS
3774 spin_lock(&phba->sli4_hba.sgl_list_lock);
3775 list_splice_init(&els_sgl_list,
3776 &phba->sli4_hba.lpfc_els_sgl_list);
3777 spin_unlock(&phba->sli4_hba.sgl_list_lock);
38c20673 3778 spin_unlock_irq(&phba->hbalock);
8a9d2e80
JS
3779 } else if (els_xri_cnt < phba->sli4_hba.els_xri_cnt) {
3780 /* els xri-sgl shrinked */
3781 xri_cnt = phba->sli4_hba.els_xri_cnt - els_xri_cnt;
3782 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3783 "3158 ELS xri-sgl count decreased from "
3784 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3785 els_xri_cnt);
3786 spin_lock_irq(&phba->hbalock);
895427bd
JS
3787 spin_lock(&phba->sli4_hba.sgl_list_lock);
3788 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list,
3789 &els_sgl_list);
8a9d2e80
JS
3790 /* release extra els sgls from list */
3791 for (i = 0; i < xri_cnt; i++) {
3792 list_remove_head(&els_sgl_list,
3793 sglq_entry, struct lpfc_sglq, list);
3794 if (sglq_entry) {
895427bd
JS
3795 __lpfc_mbuf_free(phba, sglq_entry->virt,
3796 sglq_entry->phys);
8a9d2e80
JS
3797 kfree(sglq_entry);
3798 }
3799 }
895427bd
JS
3800 list_splice_init(&els_sgl_list,
3801 &phba->sli4_hba.lpfc_els_sgl_list);
3802 spin_unlock(&phba->sli4_hba.sgl_list_lock);
8a9d2e80
JS
3803 spin_unlock_irq(&phba->hbalock);
3804 } else
3805 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3806 "3163 ELS xri-sgl count unchanged: %d\n",
3807 els_xri_cnt);
3808 phba->sli4_hba.els_xri_cnt = els_xri_cnt;
3809
3810 /* update xris to els sgls on the list */
3811 sglq_entry = NULL;
3812 sglq_entry_next = NULL;
3813 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
895427bd 3814 &phba->sli4_hba.lpfc_els_sgl_list, list) {
8a9d2e80
JS
3815 lxri = lpfc_sli4_next_xritag(phba);
3816 if (lxri == NO_XRI) {
372c187b
DK
3817 lpfc_printf_log(phba, KERN_ERR,
3818 LOG_TRACE_EVENT,
8a9d2e80
JS
3819 "2400 Failed to allocate xri for "
3820 "ELS sgl\n");
3821 rc = -ENOMEM;
3822 goto out_free_mem;
3823 }
3824 sglq_entry->sli4_lxritag = lxri;
3825 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3826 }
895427bd
JS
3827 return 0;
3828
3829out_free_mem:
3830 lpfc_free_els_sgl_list(phba);
3831 return rc;
3832}
3833
f358dd0c
JS
3834/**
3835 * lpfc_sli4_nvmet_sgl_update - update xri-sgl sizing and mapping
3836 * @phba: pointer to lpfc hba data structure.
3837 *
3838 * This routine first calculates the sizes of the current els and allocated
3839 * scsi sgl lists, and then goes through all sgls to updates the physical
3840 * XRIs assigned due to port function reset. During port initialization, the
3841 * current els and allocated scsi sgl lists are 0s.
3842 *
3843 * Return codes
3844 * 0 - successful (for now, it always returns 0)
3845 **/
3846int
3847lpfc_sli4_nvmet_sgl_update(struct lpfc_hba *phba)
3848{
3849 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
3850 uint16_t i, lxri, xri_cnt, els_xri_cnt;
6c621a22 3851 uint16_t nvmet_xri_cnt;
f358dd0c
JS
3852 LIST_HEAD(nvmet_sgl_list);
3853 int rc;
3854
3855 /*
3856 * update on pci function's nvmet xri-sgl list
3857 */
3858 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
61f3d4bf 3859
6c621a22
JS
3860 /* For NVMET, ALL remaining XRIs are dedicated for IO processing */
3861 nvmet_xri_cnt = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
f358dd0c
JS
3862 if (nvmet_xri_cnt > phba->sli4_hba.nvmet_xri_cnt) {
3863 /* els xri-sgl expanded */
3864 xri_cnt = nvmet_xri_cnt - phba->sli4_hba.nvmet_xri_cnt;
3865 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3866 "6302 NVMET xri-sgl cnt grew from %d to %d\n",
3867 phba->sli4_hba.nvmet_xri_cnt, nvmet_xri_cnt);
3868 /* allocate the additional nvmet sgls */
3869 for (i = 0; i < xri_cnt; i++) {
3870 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3871 GFP_KERNEL);
3872 if (sglq_entry == NULL) {
372c187b
DK
3873 lpfc_printf_log(phba, KERN_ERR,
3874 LOG_TRACE_EVENT,
f358dd0c
JS
3875 "6303 Failure to allocate an "
3876 "NVMET sgl entry:%d\n", i);
3877 rc = -ENOMEM;
3878 goto out_free_mem;
3879 }
3880 sglq_entry->buff_type = NVMET_BUFF_TYPE;
3881 sglq_entry->virt = lpfc_nvmet_buf_alloc(phba, 0,
3882 &sglq_entry->phys);
3883 if (sglq_entry->virt == NULL) {
3884 kfree(sglq_entry);
372c187b
DK
3885 lpfc_printf_log(phba, KERN_ERR,
3886 LOG_TRACE_EVENT,
f358dd0c
JS
3887 "6304 Failure to allocate an "
3888 "NVMET buf:%d\n", i);
3889 rc = -ENOMEM;
3890 goto out_free_mem;
3891 }
3892 sglq_entry->sgl = sglq_entry->virt;
3893 memset(sglq_entry->sgl, 0,
3894 phba->cfg_sg_dma_buf_size);
3895 sglq_entry->state = SGL_FREED;
3896 list_add_tail(&sglq_entry->list, &nvmet_sgl_list);
3897 }
3898 spin_lock_irq(&phba->hbalock);
3899 spin_lock(&phba->sli4_hba.sgl_list_lock);
3900 list_splice_init(&nvmet_sgl_list,
3901 &phba->sli4_hba.lpfc_nvmet_sgl_list);
3902 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3903 spin_unlock_irq(&phba->hbalock);
3904 } else if (nvmet_xri_cnt < phba->sli4_hba.nvmet_xri_cnt) {
3905 /* nvmet xri-sgl shrunk */
3906 xri_cnt = phba->sli4_hba.nvmet_xri_cnt - nvmet_xri_cnt;
3907 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3908 "6305 NVMET xri-sgl count decreased from "
3909 "%d to %d\n", phba->sli4_hba.nvmet_xri_cnt,
3910 nvmet_xri_cnt);
3911 spin_lock_irq(&phba->hbalock);
3912 spin_lock(&phba->sli4_hba.sgl_list_lock);
3913 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list,
3914 &nvmet_sgl_list);
3915 /* release extra nvmet sgls from list */
3916 for (i = 0; i < xri_cnt; i++) {
3917 list_remove_head(&nvmet_sgl_list,
3918 sglq_entry, struct lpfc_sglq, list);
3919 if (sglq_entry) {
3920 lpfc_nvmet_buf_free(phba, sglq_entry->virt,
3921 sglq_entry->phys);
3922 kfree(sglq_entry);
3923 }
3924 }
3925 list_splice_init(&nvmet_sgl_list,
3926 &phba->sli4_hba.lpfc_nvmet_sgl_list);
3927 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3928 spin_unlock_irq(&phba->hbalock);
3929 } else
3930 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3931 "6306 NVMET xri-sgl count unchanged: %d\n",
3932 nvmet_xri_cnt);
3933 phba->sli4_hba.nvmet_xri_cnt = nvmet_xri_cnt;
3934
3935 /* update xris to nvmet sgls on the list */
3936 sglq_entry = NULL;
3937 sglq_entry_next = NULL;
3938 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
3939 &phba->sli4_hba.lpfc_nvmet_sgl_list, list) {
3940 lxri = lpfc_sli4_next_xritag(phba);
3941 if (lxri == NO_XRI) {
372c187b
DK
3942 lpfc_printf_log(phba, KERN_ERR,
3943 LOG_TRACE_EVENT,
f358dd0c
JS
3944 "6307 Failed to allocate xri for "
3945 "NVMET sgl\n");
3946 rc = -ENOMEM;
3947 goto out_free_mem;
3948 }
3949 sglq_entry->sli4_lxritag = lxri;
3950 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3951 }
3952 return 0;
3953
3954out_free_mem:
3955 lpfc_free_nvmet_sgl_list(phba);
3956 return rc;
3957}
3958
5e5b511d
JS
3959int
3960lpfc_io_buf_flush(struct lpfc_hba *phba, struct list_head *cbuf)
3961{
3962 LIST_HEAD(blist);
3963 struct lpfc_sli4_hdw_queue *qp;
c490850a
JS
3964 struct lpfc_io_buf *lpfc_cmd;
3965 struct lpfc_io_buf *iobufp, *prev_iobufp;
5e5b511d
JS
3966 int idx, cnt, xri, inserted;
3967
3968 cnt = 0;
3969 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3970 qp = &phba->sli4_hba.hdwq[idx];
3971 spin_lock_irq(&qp->io_buf_list_get_lock);
3972 spin_lock(&qp->io_buf_list_put_lock);
3973
3974 /* Take everything off the get and put lists */
3975 list_splice_init(&qp->lpfc_io_buf_list_get, &blist);
3976 list_splice(&qp->lpfc_io_buf_list_put, &blist);
3977 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_get);
3978 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_put);
3979 cnt += qp->get_io_bufs + qp->put_io_bufs;
3980 qp->get_io_bufs = 0;
3981 qp->put_io_bufs = 0;
3982 qp->total_io_bufs = 0;
3983 spin_unlock(&qp->io_buf_list_put_lock);
3984 spin_unlock_irq(&qp->io_buf_list_get_lock);
3985 }
3986
3987 /*
3988 * Take IO buffers off blist and put on cbuf sorted by XRI.
3989 * This is because POST_SGL takes a sequential range of XRIs
3990 * to post to the firmware.
3991 */
3992 for (idx = 0; idx < cnt; idx++) {
c490850a 3993 list_remove_head(&blist, lpfc_cmd, struct lpfc_io_buf, list);
5e5b511d
JS
3994 if (!lpfc_cmd)
3995 return cnt;
3996 if (idx == 0) {
3997 list_add_tail(&lpfc_cmd->list, cbuf);
3998 continue;
3999 }
4000 xri = lpfc_cmd->cur_iocbq.sli4_xritag;
4001 inserted = 0;
4002 prev_iobufp = NULL;
4003 list_for_each_entry(iobufp, cbuf, list) {
4004 if (xri < iobufp->cur_iocbq.sli4_xritag) {
4005 if (prev_iobufp)
4006 list_add(&lpfc_cmd->list,
4007 &prev_iobufp->list);
4008 else
4009 list_add(&lpfc_cmd->list, cbuf);
4010 inserted = 1;
4011 break;
4012 }
4013 prev_iobufp = iobufp;
4014 }
4015 if (!inserted)
4016 list_add_tail(&lpfc_cmd->list, cbuf);
4017 }
4018 return cnt;
4019}
4020
4021int
4022lpfc_io_buf_replenish(struct lpfc_hba *phba, struct list_head *cbuf)
4023{
4024 struct lpfc_sli4_hdw_queue *qp;
c490850a 4025 struct lpfc_io_buf *lpfc_cmd;
5e5b511d
JS
4026 int idx, cnt;
4027
4028 qp = phba->sli4_hba.hdwq;
4029 cnt = 0;
4030 while (!list_empty(cbuf)) {
4031 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
4032 list_remove_head(cbuf, lpfc_cmd,
c490850a 4033 struct lpfc_io_buf, list);
5e5b511d
JS
4034 if (!lpfc_cmd)
4035 return cnt;
4036 cnt++;
4037 qp = &phba->sli4_hba.hdwq[idx];
1fbf9742
JS
4038 lpfc_cmd->hdwq_no = idx;
4039 lpfc_cmd->hdwq = qp;
5e5b511d
JS
4040 lpfc_cmd->cur_iocbq.wqe_cmpl = NULL;
4041 lpfc_cmd->cur_iocbq.iocb_cmpl = NULL;
4042 spin_lock(&qp->io_buf_list_put_lock);
4043 list_add_tail(&lpfc_cmd->list,
4044 &qp->lpfc_io_buf_list_put);
4045 qp->put_io_bufs++;
4046 qp->total_io_bufs++;
4047 spin_unlock(&qp->io_buf_list_put_lock);
4048 }
4049 }
4050 return cnt;
4051}
4052
895427bd 4053/**
5e5b511d 4054 * lpfc_sli4_io_sgl_update - update xri-sgl sizing and mapping
895427bd
JS
4055 * @phba: pointer to lpfc hba data structure.
4056 *
4057 * This routine first calculates the sizes of the current els and allocated
4058 * scsi sgl lists, and then goes through all sgls to updates the physical
4059 * XRIs assigned due to port function reset. During port initialization, the
4060 * current els and allocated scsi sgl lists are 0s.
4061 *
4062 * Return codes
4063 * 0 - successful (for now, it always returns 0)
4064 **/
4065int
5e5b511d 4066lpfc_sli4_io_sgl_update(struct lpfc_hba *phba)
895427bd 4067{
c490850a 4068 struct lpfc_io_buf *lpfc_ncmd = NULL, *lpfc_ncmd_next = NULL;
0794d601 4069 uint16_t i, lxri, els_xri_cnt;
5e5b511d
JS
4070 uint16_t io_xri_cnt, io_xri_max;
4071 LIST_HEAD(io_sgl_list);
0794d601 4072 int rc, cnt;
8a9d2e80 4073
895427bd 4074 /*
0794d601 4075 * update on pci function's allocated nvme xri-sgl list
895427bd 4076 */
8a9d2e80 4077
0794d601
JS
4078 /* maximum number of xris available for nvme buffers */
4079 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
5e5b511d
JS
4080 io_xri_max = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
4081 phba->sli4_hba.io_xri_max = io_xri_max;
895427bd 4082
e8c0a779 4083 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
0794d601
JS
4084 "6074 Current allocated XRI sgl count:%d, "
4085 "maximum XRI count:%d\n",
5e5b511d
JS
4086 phba->sli4_hba.io_xri_cnt,
4087 phba->sli4_hba.io_xri_max);
8a9d2e80 4088
5e5b511d 4089 cnt = lpfc_io_buf_flush(phba, &io_sgl_list);
8a9d2e80 4090
5e5b511d 4091 if (phba->sli4_hba.io_xri_cnt > phba->sli4_hba.io_xri_max) {
0794d601 4092 /* max nvme xri shrunk below the allocated nvme buffers */
5e5b511d
JS
4093 io_xri_cnt = phba->sli4_hba.io_xri_cnt -
4094 phba->sli4_hba.io_xri_max;
0794d601 4095 /* release the extra allocated nvme buffers */
5e5b511d
JS
4096 for (i = 0; i < io_xri_cnt; i++) {
4097 list_remove_head(&io_sgl_list, lpfc_ncmd,
c490850a 4098 struct lpfc_io_buf, list);
0794d601 4099 if (lpfc_ncmd) {
771db5c0 4100 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
0794d601
JS
4101 lpfc_ncmd->data,
4102 lpfc_ncmd->dma_handle);
4103 kfree(lpfc_ncmd);
a2fc4aef 4104 }
8a9d2e80 4105 }
5e5b511d 4106 phba->sli4_hba.io_xri_cnt -= io_xri_cnt;
8a9d2e80
JS
4107 }
4108
0794d601
JS
4109 /* update xris associated to remaining allocated nvme buffers */
4110 lpfc_ncmd = NULL;
4111 lpfc_ncmd_next = NULL;
5e5b511d 4112 phba->sli4_hba.io_xri_cnt = cnt;
0794d601 4113 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
5e5b511d 4114 &io_sgl_list, list) {
8a9d2e80
JS
4115 lxri = lpfc_sli4_next_xritag(phba);
4116 if (lxri == NO_XRI) {
372c187b
DK
4117 lpfc_printf_log(phba, KERN_ERR,
4118 LOG_TRACE_EVENT,
0794d601
JS
4119 "6075 Failed to allocate xri for "
4120 "nvme buffer\n");
8a9d2e80
JS
4121 rc = -ENOMEM;
4122 goto out_free_mem;
4123 }
0794d601
JS
4124 lpfc_ncmd->cur_iocbq.sli4_lxritag = lxri;
4125 lpfc_ncmd->cur_iocbq.sli4_xritag = phba->sli4_hba.xri_ids[lxri];
8a9d2e80 4126 }
5e5b511d 4127 cnt = lpfc_io_buf_replenish(phba, &io_sgl_list);
dea3101e 4128 return 0;
8a9d2e80
JS
4129
4130out_free_mem:
5e5b511d 4131 lpfc_io_free(phba);
8a9d2e80 4132 return rc;
dea3101e 4133}
4134
0794d601 4135/**
5e5b511d 4136 * lpfc_new_io_buf - IO buffer allocator for HBA with SLI4 IF spec
fe614acd
LJ
4137 * @phba: Pointer to lpfc hba data structure.
4138 * @num_to_alloc: The requested number of buffers to allocate.
0794d601
JS
4139 *
4140 * This routine allocates nvme buffers for device with SLI-4 interface spec,
4141 * the nvme buffer contains all the necessary information needed to initiate
4142 * an I/O. After allocating up to @num_to_allocate IO buffers and put
4143 * them on a list, it post them to the port by using SGL block post.
4144 *
4145 * Return codes:
5e5b511d 4146 * int - number of IO buffers that were allocated and posted.
0794d601
JS
4147 * 0 = failure, less than num_to_alloc is a partial failure.
4148 **/
4149int
5e5b511d 4150lpfc_new_io_buf(struct lpfc_hba *phba, int num_to_alloc)
0794d601 4151{
c490850a 4152 struct lpfc_io_buf *lpfc_ncmd;
0794d601
JS
4153 struct lpfc_iocbq *pwqeq;
4154 uint16_t iotag, lxri = 0;
4155 int bcnt, num_posted;
4156 LIST_HEAD(prep_nblist);
4157 LIST_HEAD(post_nblist);
4158 LIST_HEAD(nvme_nblist);
4159
5e5b511d 4160 phba->sli4_hba.io_xri_cnt = 0;
0794d601 4161 for (bcnt = 0; bcnt < num_to_alloc; bcnt++) {
7f9989ba 4162 lpfc_ncmd = kzalloc(sizeof(*lpfc_ncmd), GFP_KERNEL);
0794d601
JS
4163 if (!lpfc_ncmd)
4164 break;
4165 /*
4166 * Get memory from the pci pool to map the virt space to
4167 * pci bus space for an I/O. The DMA buffer includes the
4168 * number of SGE's necessary to support the sg_tablesize.
4169 */
a5c990ee
TM
4170 lpfc_ncmd->data = dma_pool_zalloc(phba->lpfc_sg_dma_buf_pool,
4171 GFP_KERNEL,
4172 &lpfc_ncmd->dma_handle);
0794d601
JS
4173 if (!lpfc_ncmd->data) {
4174 kfree(lpfc_ncmd);
4175 break;
4176 }
0794d601 4177
d79c9e9d
JS
4178 if (phba->cfg_xpsgl && !phba->nvmet_support) {
4179 INIT_LIST_HEAD(&lpfc_ncmd->dma_sgl_xtra_list);
4180 } else {
4181 /*
4182 * 4K Page alignment is CRITICAL to BlockGuard, double
4183 * check to be sure.
4184 */
4185 if ((phba->sli3_options & LPFC_SLI3_BG_ENABLED) &&
4186 (((unsigned long)(lpfc_ncmd->data) &
4187 (unsigned long)(SLI4_PAGE_SIZE - 1)) != 0)) {
372c187b
DK
4188 lpfc_printf_log(phba, KERN_ERR,
4189 LOG_TRACE_EVENT,
d79c9e9d
JS
4190 "3369 Memory alignment err: "
4191 "addr=%lx\n",
4192 (unsigned long)lpfc_ncmd->data);
4193 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4194 lpfc_ncmd->data,
4195 lpfc_ncmd->dma_handle);
4196 kfree(lpfc_ncmd);
4197 break;
4198 }
0794d601
JS
4199 }
4200
d79c9e9d
JS
4201 INIT_LIST_HEAD(&lpfc_ncmd->dma_cmd_rsp_list);
4202
0794d601
JS
4203 lxri = lpfc_sli4_next_xritag(phba);
4204 if (lxri == NO_XRI) {
4205 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4206 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
4207 kfree(lpfc_ncmd);
4208 break;
4209 }
4210 pwqeq = &lpfc_ncmd->cur_iocbq;
4211
4212 /* Allocate iotag for lpfc_ncmd->cur_iocbq. */
4213 iotag = lpfc_sli_next_iotag(phba, pwqeq);
4214 if (iotag == 0) {
4215 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4216 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
4217 kfree(lpfc_ncmd);
372c187b 4218 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0794d601
JS
4219 "6121 Failed to allocate IOTAG for"
4220 " XRI:0x%x\n", lxri);
4221 lpfc_sli4_free_xri(phba, lxri);
4222 break;
4223 }
4224 pwqeq->sli4_lxritag = lxri;
4225 pwqeq->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
4226 pwqeq->context1 = lpfc_ncmd;
4227
4228 /* Initialize local short-hand pointers. */
4229 lpfc_ncmd->dma_sgl = lpfc_ncmd->data;
4230 lpfc_ncmd->dma_phys_sgl = lpfc_ncmd->dma_handle;
4231 lpfc_ncmd->cur_iocbq.context1 = lpfc_ncmd;
c2017260 4232 spin_lock_init(&lpfc_ncmd->buf_lock);
0794d601
JS
4233
4234 /* add the nvme buffer to a post list */
4235 list_add_tail(&lpfc_ncmd->list, &post_nblist);
5e5b511d 4236 phba->sli4_hba.io_xri_cnt++;
0794d601
JS
4237 }
4238 lpfc_printf_log(phba, KERN_INFO, LOG_NVME,
4239 "6114 Allocate %d out of %d requested new NVME "
4240 "buffers\n", bcnt, num_to_alloc);
4241
4242 /* post the list of nvme buffer sgls to port if available */
4243 if (!list_empty(&post_nblist))
5e5b511d 4244 num_posted = lpfc_sli4_post_io_sgl_list(
0794d601
JS
4245 phba, &post_nblist, bcnt);
4246 else
4247 num_posted = 0;
4248
4249 return num_posted;
4250}
4251
96418b5e
JS
4252static uint64_t
4253lpfc_get_wwpn(struct lpfc_hba *phba)
4254{
4255 uint64_t wwn;
4256 int rc;
4257 LPFC_MBOXQ_t *mboxq;
4258 MAILBOX_t *mb;
4259
96418b5e
JS
4260 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
4261 GFP_KERNEL);
4262 if (!mboxq)
4263 return (uint64_t)-1;
4264
4265 /* First get WWN of HBA instance */
4266 lpfc_read_nv(phba, mboxq);
4267 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
4268 if (rc != MBX_SUCCESS) {
372c187b 4269 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
96418b5e
JS
4270 "6019 Mailbox failed , mbxCmd x%x "
4271 "READ_NV, mbxStatus x%x\n",
4272 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
4273 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
4274 mempool_free(mboxq, phba->mbox_mem_pool);
4275 return (uint64_t) -1;
4276 }
4277 mb = &mboxq->u.mb;
4278 memcpy(&wwn, (char *)mb->un.varRDnvp.portname, sizeof(uint64_t));
4279 /* wwn is WWPN of HBA instance */
4280 mempool_free(mboxq, phba->mbox_mem_pool);
4281 if (phba->sli_rev == LPFC_SLI_REV4)
4282 return be64_to_cpu(wwn);
4283 else
286871a6 4284 return rol64(wwn, 32);
96418b5e
JS
4285}
4286
e59058c4 4287/**
3621a710 4288 * lpfc_create_port - Create an FC port
e59058c4
JS
4289 * @phba: pointer to lpfc hba data structure.
4290 * @instance: a unique integer ID to this FC port.
4291 * @dev: pointer to the device data structure.
4292 *
4293 * This routine creates a FC port for the upper layer protocol. The FC port
4294 * can be created on top of either a physical port or a virtual port provided
4295 * by the HBA. This routine also allocates a SCSI host data structure (shost)
4296 * and associates the FC port created before adding the shost into the SCSI
4297 * layer.
4298 *
4299 * Return codes
4300 * @vport - pointer to the virtual N_Port data structure.
4301 * NULL - port create failed.
4302 **/
2e0fef85 4303struct lpfc_vport *
3de2a653 4304lpfc_create_port(struct lpfc_hba *phba, int instance, struct device *dev)
47a8617c 4305{
2e0fef85 4306 struct lpfc_vport *vport;
895427bd 4307 struct Scsi_Host *shost = NULL;
c90b4480 4308 struct scsi_host_template *template;
2e0fef85 4309 int error = 0;
96418b5e
JS
4310 int i;
4311 uint64_t wwn;
4312 bool use_no_reset_hba = false;
56bc8028 4313 int rc;
96418b5e 4314
56bc8028
JS
4315 if (lpfc_no_hba_reset_cnt) {
4316 if (phba->sli_rev < LPFC_SLI_REV4 &&
4317 dev == &phba->pcidev->dev) {
4318 /* Reset the port first */
4319 lpfc_sli_brdrestart(phba);
4320 rc = lpfc_sli_chipset_init(phba);
4321 if (rc)
4322 return NULL;
4323 }
4324 wwn = lpfc_get_wwpn(phba);
4325 }
96418b5e
JS
4326
4327 for (i = 0; i < lpfc_no_hba_reset_cnt; i++) {
4328 if (wwn == lpfc_no_hba_reset[i]) {
372c187b
DK
4329 lpfc_printf_log(phba, KERN_ERR,
4330 LOG_TRACE_EVENT,
96418b5e
JS
4331 "6020 Setting use_no_reset port=%llx\n",
4332 wwn);
4333 use_no_reset_hba = true;
4334 break;
4335 }
4336 }
47a8617c 4337
c90b4480
JS
4338 /* Seed template for SCSI host registration */
4339 if (dev == &phba->pcidev->dev) {
4340 template = &phba->port_template;
4341
4342 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
4343 /* Seed physical port template */
4344 memcpy(template, &lpfc_template, sizeof(*template));
4345
7c30bb62 4346 if (use_no_reset_hba)
c90b4480 4347 /* template is for a no reset SCSI Host */
c90b4480 4348 template->eh_host_reset_handler = NULL;
c90b4480
JS
4349
4350 /* Template for all vports this physical port creates */
4351 memcpy(&phba->vport_template, &lpfc_template,
4352 sizeof(*template));
c90b4480
JS
4353 phba->vport_template.shost_attrs = lpfc_vport_attrs;
4354 phba->vport_template.eh_bus_reset_handler = NULL;
4355 phba->vport_template.eh_host_reset_handler = NULL;
4356 phba->vport_template.vendor_id = 0;
4357
4358 /* Initialize the host templates with updated value */
4359 if (phba->sli_rev == LPFC_SLI_REV4) {
4360 template->sg_tablesize = phba->cfg_scsi_seg_cnt;
4361 phba->vport_template.sg_tablesize =
4362 phba->cfg_scsi_seg_cnt;
4363 } else {
4364 template->sg_tablesize = phba->cfg_sg_seg_cnt;
4365 phba->vport_template.sg_tablesize =
4366 phba->cfg_sg_seg_cnt;
4367 }
4368
895427bd 4369 } else {
c90b4480
JS
4370 /* NVMET is for physical port only */
4371 memcpy(template, &lpfc_template_nvme,
4372 sizeof(*template));
895427bd 4373 }
c90b4480
JS
4374 } else {
4375 template = &phba->vport_template;
ea4142f6 4376 }
c90b4480
JS
4377
4378 shost = scsi_host_alloc(template, sizeof(struct lpfc_vport));
2e0fef85
JS
4379 if (!shost)
4380 goto out;
47a8617c 4381
2e0fef85
JS
4382 vport = (struct lpfc_vport *) shost->hostdata;
4383 vport->phba = phba;
2e0fef85 4384 vport->load_flag |= FC_LOADING;
92d7f7b0 4385 vport->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
7f5f3d0d 4386 vport->fc_rscn_flush = 0;
3de2a653 4387 lpfc_get_vport_cfgparam(vport);
895427bd 4388
f6e84790
JS
4389 /* Adjust value in vport */
4390 vport->cfg_enable_fc4_type = phba->cfg_enable_fc4_type;
4391
2e0fef85
JS
4392 shost->unique_id = instance;
4393 shost->max_id = LPFC_MAX_TARGET;
3de2a653 4394 shost->max_lun = vport->cfg_max_luns;
2e0fef85
JS
4395 shost->this_id = -1;
4396 shost->max_cmd_len = 16;
6a828b0f 4397
da0436e9 4398 if (phba->sli_rev == LPFC_SLI_REV4) {
77ffd346
JS
4399 if (!phba->cfg_fcp_mq_threshold ||
4400 phba->cfg_fcp_mq_threshold > phba->cfg_hdw_queue)
4401 phba->cfg_fcp_mq_threshold = phba->cfg_hdw_queue;
4402
4403 shost->nr_hw_queues = min_t(int, 2 * num_possible_nodes(),
4404 phba->cfg_fcp_mq_threshold);
6a828b0f 4405
28baac74 4406 shost->dma_boundary =
cb5172ea 4407 phba->sli4_hba.pc_sli4_params.sge_supp_len-1;
d79c9e9d
JS
4408
4409 if (phba->cfg_xpsgl && !phba->nvmet_support)
4410 shost->sg_tablesize = LPFC_MAX_SG_TABLESIZE;
4411 else
4412 shost->sg_tablesize = phba->cfg_scsi_seg_cnt;
ace44e48
JS
4413 } else
4414 /* SLI-3 has a limited number of hardware queues (3),
4415 * thus there is only one for FCP processing.
4416 */
4417 shost->nr_hw_queues = 1;
81301a9b 4418
47a8617c 4419 /*
2e0fef85
JS
4420 * Set initial can_queue value since 0 is no longer supported and
4421 * scsi_add_host will fail. This will be adjusted later based on the
4422 * max xri value determined in hba setup.
47a8617c 4423 */
2e0fef85 4424 shost->can_queue = phba->cfg_hba_queue_depth - 10;
3de2a653 4425 if (dev != &phba->pcidev->dev) {
92d7f7b0
JS
4426 shost->transportt = lpfc_vport_transport_template;
4427 vport->port_type = LPFC_NPIV_PORT;
4428 } else {
4429 shost->transportt = lpfc_transport_template;
4430 vport->port_type = LPFC_PHYSICAL_PORT;
4431 }
47a8617c 4432
c90b4480
JS
4433 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
4434 "9081 CreatePort TMPLATE type %x TBLsize %d "
4435 "SEGcnt %d/%d\n",
4436 vport->port_type, shost->sg_tablesize,
4437 phba->cfg_scsi_seg_cnt, phba->cfg_sg_seg_cnt);
4438
2e0fef85
JS
4439 /* Initialize all internally managed lists. */
4440 INIT_LIST_HEAD(&vport->fc_nodes);
da0436e9 4441 INIT_LIST_HEAD(&vport->rcv_buffer_list);
2e0fef85 4442 spin_lock_init(&vport->work_port_lock);
47a8617c 4443
f22eb4d3 4444 timer_setup(&vport->fc_disctmo, lpfc_disc_timeout, 0);
47a8617c 4445
f22eb4d3 4446 timer_setup(&vport->els_tmofunc, lpfc_els_timeout, 0);
92494144 4447
f22eb4d3 4448 timer_setup(&vport->delayed_disc_tmo, lpfc_delayed_disc_tmo, 0);
92494144 4449
aa6ff309
JS
4450 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED)
4451 lpfc_setup_bg(phba, shost);
4452
d139b9bd 4453 error = scsi_add_host_with_dma(shost, dev, &phba->pcidev->dev);
2e0fef85
JS
4454 if (error)
4455 goto out_put_shost;
47a8617c 4456
523128e5 4457 spin_lock_irq(&phba->port_list_lock);
2e0fef85 4458 list_add_tail(&vport->listentry, &phba->port_list);
523128e5 4459 spin_unlock_irq(&phba->port_list_lock);
2e0fef85 4460 return vport;
47a8617c 4461
2e0fef85
JS
4462out_put_shost:
4463 scsi_host_put(shost);
4464out:
4465 return NULL;
47a8617c
JS
4466}
4467
e59058c4 4468/**
3621a710 4469 * destroy_port - destroy an FC port
e59058c4
JS
4470 * @vport: pointer to an lpfc virtual N_Port data structure.
4471 *
4472 * This routine destroys a FC port from the upper layer protocol. All the
4473 * resources associated with the port are released.
4474 **/
2e0fef85
JS
4475void
4476destroy_port(struct lpfc_vport *vport)
47a8617c 4477{
92d7f7b0
JS
4478 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
4479 struct lpfc_hba *phba = vport->phba;
47a8617c 4480
858c9f6c 4481 lpfc_debugfs_terminate(vport);
92d7f7b0
JS
4482 fc_remove_host(shost);
4483 scsi_remove_host(shost);
47a8617c 4484
523128e5 4485 spin_lock_irq(&phba->port_list_lock);
92d7f7b0 4486 list_del_init(&vport->listentry);
523128e5 4487 spin_unlock_irq(&phba->port_list_lock);
47a8617c 4488
92d7f7b0 4489 lpfc_cleanup(vport);
47a8617c 4490 return;
47a8617c
JS
4491}
4492
e59058c4 4493/**
3621a710 4494 * lpfc_get_instance - Get a unique integer ID
e59058c4
JS
4495 *
4496 * This routine allocates a unique integer ID from lpfc_hba_index pool. It
4497 * uses the kernel idr facility to perform the task.
4498 *
4499 * Return codes:
4500 * instance - a unique integer ID allocated as the new instance.
4501 * -1 - lpfc get instance failed.
4502 **/
92d7f7b0
JS
4503int
4504lpfc_get_instance(void)
4505{
ab516036
TH
4506 int ret;
4507
4508 ret = idr_alloc(&lpfc_hba_index, NULL, 0, 0, GFP_KERNEL);
4509 return ret < 0 ? -1 : ret;
47a8617c
JS
4510}
4511
e59058c4 4512/**
3621a710 4513 * lpfc_scan_finished - method for SCSI layer to detect whether scan is done
e59058c4
JS
4514 * @shost: pointer to SCSI host data structure.
4515 * @time: elapsed time of the scan in jiffies.
4516 *
4517 * This routine is called by the SCSI layer with a SCSI host to determine
4518 * whether the scan host is finished.
4519 *
4520 * Note: there is no scan_start function as adapter initialization will have
4521 * asynchronously kicked off the link initialization.
4522 *
4523 * Return codes
4524 * 0 - SCSI host scan is not over yet.
4525 * 1 - SCSI host scan is over.
4526 **/
47a8617c
JS
4527int lpfc_scan_finished(struct Scsi_Host *shost, unsigned long time)
4528{
2e0fef85
JS
4529 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4530 struct lpfc_hba *phba = vport->phba;
858c9f6c 4531 int stat = 0;
47a8617c 4532
858c9f6c
JS
4533 spin_lock_irq(shost->host_lock);
4534
51ef4c26 4535 if (vport->load_flag & FC_UNLOADING) {
858c9f6c
JS
4536 stat = 1;
4537 goto finished;
4538 }
256ec0d0 4539 if (time >= msecs_to_jiffies(30 * 1000)) {
2e0fef85 4540 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011
JS
4541 "0461 Scanning longer than 30 "
4542 "seconds. Continuing initialization\n");
858c9f6c 4543 stat = 1;
47a8617c 4544 goto finished;
2e0fef85 4545 }
256ec0d0
JS
4546 if (time >= msecs_to_jiffies(15 * 1000) &&
4547 phba->link_state <= LPFC_LINK_DOWN) {
2e0fef85 4548 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011
JS
4549 "0465 Link down longer than 15 "
4550 "seconds. Continuing initialization\n");
858c9f6c 4551 stat = 1;
47a8617c 4552 goto finished;
2e0fef85 4553 }
47a8617c 4554
2e0fef85 4555 if (vport->port_state != LPFC_VPORT_READY)
858c9f6c 4556 goto finished;
2e0fef85 4557 if (vport->num_disc_nodes || vport->fc_prli_sent)
858c9f6c 4558 goto finished;
256ec0d0 4559 if (vport->fc_map_cnt == 0 && time < msecs_to_jiffies(2 * 1000))
858c9f6c 4560 goto finished;
2e0fef85 4561 if ((phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) != 0)
858c9f6c
JS
4562 goto finished;
4563
4564 stat = 1;
47a8617c
JS
4565
4566finished:
858c9f6c
JS
4567 spin_unlock_irq(shost->host_lock);
4568 return stat;
92d7f7b0 4569}
47a8617c 4570
3999df75 4571static void lpfc_host_supported_speeds_set(struct Scsi_Host *shost)
cd71348a
JS
4572{
4573 struct lpfc_vport *vport = (struct lpfc_vport *)shost->hostdata;
4574 struct lpfc_hba *phba = vport->phba;
4575
4576 fc_host_supported_speeds(shost) = 0;
a1e4d3d8
DK
4577 /*
4578 * Avoid reporting supported link speed for FCoE as it can't be
4579 * controlled via FCoE.
4580 */
4581 if (phba->hba_flag & HBA_FCOE_MODE)
4582 return;
4583
1dc5ec24
JS
4584 if (phba->lmt & LMT_128Gb)
4585 fc_host_supported_speeds(shost) |= FC_PORTSPEED_128GBIT;
cd71348a
JS
4586 if (phba->lmt & LMT_64Gb)
4587 fc_host_supported_speeds(shost) |= FC_PORTSPEED_64GBIT;
4588 if (phba->lmt & LMT_32Gb)
4589 fc_host_supported_speeds(shost) |= FC_PORTSPEED_32GBIT;
4590 if (phba->lmt & LMT_16Gb)
4591 fc_host_supported_speeds(shost) |= FC_PORTSPEED_16GBIT;
4592 if (phba->lmt & LMT_10Gb)
4593 fc_host_supported_speeds(shost) |= FC_PORTSPEED_10GBIT;
4594 if (phba->lmt & LMT_8Gb)
4595 fc_host_supported_speeds(shost) |= FC_PORTSPEED_8GBIT;
4596 if (phba->lmt & LMT_4Gb)
4597 fc_host_supported_speeds(shost) |= FC_PORTSPEED_4GBIT;
4598 if (phba->lmt & LMT_2Gb)
4599 fc_host_supported_speeds(shost) |= FC_PORTSPEED_2GBIT;
4600 if (phba->lmt & LMT_1Gb)
4601 fc_host_supported_speeds(shost) |= FC_PORTSPEED_1GBIT;
4602}
4603
e59058c4 4604/**
3621a710 4605 * lpfc_host_attrib_init - Initialize SCSI host attributes on a FC port
e59058c4
JS
4606 * @shost: pointer to SCSI host data structure.
4607 *
4608 * This routine initializes a given SCSI host attributes on a FC port. The
4609 * SCSI host can be either on top of a physical port or a virtual port.
4610 **/
92d7f7b0
JS
4611void lpfc_host_attrib_init(struct Scsi_Host *shost)
4612{
4613 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4614 struct lpfc_hba *phba = vport->phba;
47a8617c 4615 /*
2e0fef85 4616 * Set fixed host attributes. Must done after lpfc_sli_hba_setup().
47a8617c
JS
4617 */
4618
2e0fef85
JS
4619 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
4620 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
47a8617c
JS
4621 fc_host_supported_classes(shost) = FC_COS_CLASS3;
4622
4623 memset(fc_host_supported_fc4s(shost), 0,
2e0fef85 4624 sizeof(fc_host_supported_fc4s(shost)));
47a8617c
JS
4625 fc_host_supported_fc4s(shost)[2] = 1;
4626 fc_host_supported_fc4s(shost)[7] = 1;
4627
92d7f7b0
JS
4628 lpfc_vport_symbolic_node_name(vport, fc_host_symbolic_name(shost),
4629 sizeof fc_host_symbolic_name(shost));
47a8617c 4630
cd71348a 4631 lpfc_host_supported_speeds_set(shost);
47a8617c
JS
4632
4633 fc_host_maxframe_size(shost) =
2e0fef85
JS
4634 (((uint32_t) vport->fc_sparam.cmn.bbRcvSizeMsb & 0x0F) << 8) |
4635 (uint32_t) vport->fc_sparam.cmn.bbRcvSizeLsb;
47a8617c 4636
0af5d708
MC
4637 fc_host_dev_loss_tmo(shost) = vport->cfg_devloss_tmo;
4638
47a8617c
JS
4639 /* This value is also unchanging */
4640 memset(fc_host_active_fc4s(shost), 0,
2e0fef85 4641 sizeof(fc_host_active_fc4s(shost)));
47a8617c
JS
4642 fc_host_active_fc4s(shost)[2] = 1;
4643 fc_host_active_fc4s(shost)[7] = 1;
4644
92d7f7b0 4645 fc_host_max_npiv_vports(shost) = phba->max_vpi;
47a8617c 4646 spin_lock_irq(shost->host_lock);
51ef4c26 4647 vport->load_flag &= ~FC_LOADING;
47a8617c 4648 spin_unlock_irq(shost->host_lock);
47a8617c 4649}
dea3101e 4650
e59058c4 4651/**
da0436e9 4652 * lpfc_stop_port_s3 - Stop SLI3 device port
e59058c4
JS
4653 * @phba: pointer to lpfc hba data structure.
4654 *
da0436e9
JS
4655 * This routine is invoked to stop an SLI3 device port, it stops the device
4656 * from generating interrupts and stops the device driver's timers for the
4657 * device.
e59058c4 4658 **/
da0436e9
JS
4659static void
4660lpfc_stop_port_s3(struct lpfc_hba *phba)
db2378e0 4661{
da0436e9
JS
4662 /* Clear all interrupt enable conditions */
4663 writel(0, phba->HCregaddr);
4664 readl(phba->HCregaddr); /* flush */
4665 /* Clear all pending interrupts */
4666 writel(0xffffffff, phba->HAregaddr);
4667 readl(phba->HAregaddr); /* flush */
db2378e0 4668
da0436e9
JS
4669 /* Reset some HBA SLI setup states */
4670 lpfc_stop_hba_timers(phba);
4671 phba->pport->work_port_events = 0;
4672}
db2378e0 4673
da0436e9
JS
4674/**
4675 * lpfc_stop_port_s4 - Stop SLI4 device port
4676 * @phba: pointer to lpfc hba data structure.
4677 *
4678 * This routine is invoked to stop an SLI4 device port, it stops the device
4679 * from generating interrupts and stops the device driver's timers for the
4680 * device.
4681 **/
4682static void
4683lpfc_stop_port_s4(struct lpfc_hba *phba)
4684{
4685 /* Reset some HBA SLI4 setup states */
4686 lpfc_stop_hba_timers(phba);
cdb42bec
JS
4687 if (phba->pport)
4688 phba->pport->work_port_events = 0;
da0436e9 4689 phba->sli4_hba.intr_enable = 0;
da0436e9 4690}
9399627f 4691
da0436e9
JS
4692/**
4693 * lpfc_stop_port - Wrapper function for stopping hba port
4694 * @phba: Pointer to HBA context object.
4695 *
4696 * This routine wraps the actual SLI3 or SLI4 hba stop port routine from
4697 * the API jump table function pointer from the lpfc_hba struct.
4698 **/
4699void
4700lpfc_stop_port(struct lpfc_hba *phba)
4701{
4702 phba->lpfc_stop_port(phba);
f485c18d
DK
4703
4704 if (phba->wq)
4705 flush_workqueue(phba->wq);
da0436e9 4706}
db2378e0 4707
ecfd03c6
JS
4708/**
4709 * lpfc_fcf_redisc_wait_start_timer - Start fcf rediscover wait timer
4710 * @phba: Pointer to hba for which this call is being executed.
4711 *
4712 * This routine starts the timer waiting for the FCF rediscovery to complete.
4713 **/
4714void
4715lpfc_fcf_redisc_wait_start_timer(struct lpfc_hba *phba)
4716{
4717 unsigned long fcf_redisc_wait_tmo =
4718 (jiffies + msecs_to_jiffies(LPFC_FCF_REDISCOVER_WAIT_TMO));
4719 /* Start fcf rediscovery wait period timer */
4720 mod_timer(&phba->fcf.redisc_wait, fcf_redisc_wait_tmo);
4721 spin_lock_irq(&phba->hbalock);
4722 /* Allow action to new fcf asynchronous event */
4723 phba->fcf.fcf_flag &= ~(FCF_AVAILABLE | FCF_SCAN_DONE);
4724 /* Mark the FCF rediscovery pending state */
4725 phba->fcf.fcf_flag |= FCF_REDISC_PEND;
4726 spin_unlock_irq(&phba->hbalock);
4727}
4728
4729/**
4730 * lpfc_sli4_fcf_redisc_wait_tmo - FCF table rediscover wait timeout
fe614acd 4731 * @t: Timer context used to obtain the pointer to lpfc hba data structure.
ecfd03c6
JS
4732 *
4733 * This routine is invoked when waiting for FCF table rediscover has been
4734 * timed out. If new FCF record(s) has (have) been discovered during the
4735 * wait period, a new FCF event shall be added to the FCOE async event
4736 * list, and then worker thread shall be waked up for processing from the
4737 * worker thread context.
4738 **/
e399b228 4739static void
f22eb4d3 4740lpfc_sli4_fcf_redisc_wait_tmo(struct timer_list *t)
ecfd03c6 4741{
f22eb4d3 4742 struct lpfc_hba *phba = from_timer(phba, t, fcf.redisc_wait);
ecfd03c6
JS
4743
4744 /* Don't send FCF rediscovery event if timer cancelled */
4745 spin_lock_irq(&phba->hbalock);
4746 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
4747 spin_unlock_irq(&phba->hbalock);
4748 return;
4749 }
4750 /* Clear FCF rediscovery timer pending flag */
4751 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
4752 /* FCF rediscovery event to worker thread */
4753 phba->fcf.fcf_flag |= FCF_REDISC_EVT;
4754 spin_unlock_irq(&phba->hbalock);
0c9ab6f5 4755 lpfc_printf_log(phba, KERN_INFO, LOG_FIP,
a93ff37a 4756 "2776 FCF rediscover quiescent timer expired\n");
ecfd03c6
JS
4757 /* wake up worker thread */
4758 lpfc_worker_wake_up(phba);
4759}
4760
e59058c4 4761/**
da0436e9 4762 * lpfc_sli4_parse_latt_fault - Parse sli4 link-attention link fault code
e59058c4 4763 * @phba: pointer to lpfc hba data structure.
da0436e9 4764 * @acqe_link: pointer to the async link completion queue entry.
e59058c4 4765 *
23288b78 4766 * This routine is to parse the SLI4 link-attention link fault code.
e59058c4 4767 **/
23288b78 4768static void
da0436e9
JS
4769lpfc_sli4_parse_latt_fault(struct lpfc_hba *phba,
4770 struct lpfc_acqe_link *acqe_link)
db2378e0 4771{
da0436e9
JS
4772 switch (bf_get(lpfc_acqe_link_fault, acqe_link)) {
4773 case LPFC_ASYNC_LINK_FAULT_NONE:
4774 case LPFC_ASYNC_LINK_FAULT_LOCAL:
4775 case LPFC_ASYNC_LINK_FAULT_REMOTE:
23288b78 4776 case LPFC_ASYNC_LINK_FAULT_LR_LRR:
da0436e9
JS
4777 break;
4778 default:
372c187b 4779 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
23288b78 4780 "0398 Unknown link fault code: x%x\n",
da0436e9 4781 bf_get(lpfc_acqe_link_fault, acqe_link));
da0436e9
JS
4782 break;
4783 }
db2378e0
JS
4784}
4785
5b75da2f 4786/**
da0436e9 4787 * lpfc_sli4_parse_latt_type - Parse sli4 link attention type
5b75da2f 4788 * @phba: pointer to lpfc hba data structure.
da0436e9 4789 * @acqe_link: pointer to the async link completion queue entry.
5b75da2f 4790 *
da0436e9
JS
4791 * This routine is to parse the SLI4 link attention type and translate it
4792 * into the base driver's link attention type coding.
5b75da2f 4793 *
da0436e9
JS
4794 * Return: Link attention type in terms of base driver's coding.
4795 **/
4796static uint8_t
4797lpfc_sli4_parse_latt_type(struct lpfc_hba *phba,
4798 struct lpfc_acqe_link *acqe_link)
5b75da2f 4799{
da0436e9 4800 uint8_t att_type;
5b75da2f 4801
da0436e9
JS
4802 switch (bf_get(lpfc_acqe_link_status, acqe_link)) {
4803 case LPFC_ASYNC_LINK_STATUS_DOWN:
4804 case LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN:
76a95d75 4805 att_type = LPFC_ATT_LINK_DOWN;
da0436e9
JS
4806 break;
4807 case LPFC_ASYNC_LINK_STATUS_UP:
4808 /* Ignore physical link up events - wait for logical link up */
76a95d75 4809 att_type = LPFC_ATT_RESERVED;
da0436e9
JS
4810 break;
4811 case LPFC_ASYNC_LINK_STATUS_LOGICAL_UP:
76a95d75 4812 att_type = LPFC_ATT_LINK_UP;
da0436e9
JS
4813 break;
4814 default:
372c187b 4815 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
4816 "0399 Invalid link attention type: x%x\n",
4817 bf_get(lpfc_acqe_link_status, acqe_link));
76a95d75 4818 att_type = LPFC_ATT_RESERVED;
da0436e9 4819 break;
5b75da2f 4820 }
da0436e9 4821 return att_type;
5b75da2f
JS
4822}
4823
8b68cd52
JS
4824/**
4825 * lpfc_sli_port_speed_get - Get sli3 link speed code to link speed
4826 * @phba: pointer to lpfc hba data structure.
4827 *
4828 * This routine is to get an SLI3 FC port's link speed in Mbps.
4829 *
4830 * Return: link speed in terms of Mbps.
4831 **/
4832uint32_t
4833lpfc_sli_port_speed_get(struct lpfc_hba *phba)
4834{
4835 uint32_t link_speed;
4836
4837 if (!lpfc_is_link_up(phba))
4838 return 0;
4839
a085e87c
JS
4840 if (phba->sli_rev <= LPFC_SLI_REV3) {
4841 switch (phba->fc_linkspeed) {
4842 case LPFC_LINK_SPEED_1GHZ:
4843 link_speed = 1000;
4844 break;
4845 case LPFC_LINK_SPEED_2GHZ:
4846 link_speed = 2000;
4847 break;
4848 case LPFC_LINK_SPEED_4GHZ:
4849 link_speed = 4000;
4850 break;
4851 case LPFC_LINK_SPEED_8GHZ:
4852 link_speed = 8000;
4853 break;
4854 case LPFC_LINK_SPEED_10GHZ:
4855 link_speed = 10000;
4856 break;
4857 case LPFC_LINK_SPEED_16GHZ:
4858 link_speed = 16000;
4859 break;
4860 default:
4861 link_speed = 0;
4862 }
4863 } else {
4864 if (phba->sli4_hba.link_state.logical_speed)
4865 link_speed =
4866 phba->sli4_hba.link_state.logical_speed;
4867 else
4868 link_speed = phba->sli4_hba.link_state.speed;
8b68cd52
JS
4869 }
4870 return link_speed;
4871}
4872
4873/**
4874 * lpfc_sli4_port_speed_parse - Parse async evt link speed code to link speed
4875 * @phba: pointer to lpfc hba data structure.
4876 * @evt_code: asynchronous event code.
4877 * @speed_code: asynchronous event link speed code.
4878 *
4879 * This routine is to parse the giving SLI4 async event link speed code into
4880 * value of Mbps for the link speed.
4881 *
4882 * Return: link speed in terms of Mbps.
4883 **/
4884static uint32_t
4885lpfc_sli4_port_speed_parse(struct lpfc_hba *phba, uint32_t evt_code,
4886 uint8_t speed_code)
4887{
4888 uint32_t port_speed;
4889
4890 switch (evt_code) {
4891 case LPFC_TRAILER_CODE_LINK:
4892 switch (speed_code) {
26d830ec 4893 case LPFC_ASYNC_LINK_SPEED_ZERO:
8b68cd52
JS
4894 port_speed = 0;
4895 break;
26d830ec 4896 case LPFC_ASYNC_LINK_SPEED_10MBPS:
8b68cd52
JS
4897 port_speed = 10;
4898 break;
26d830ec 4899 case LPFC_ASYNC_LINK_SPEED_100MBPS:
8b68cd52
JS
4900 port_speed = 100;
4901 break;
26d830ec 4902 case LPFC_ASYNC_LINK_SPEED_1GBPS:
8b68cd52
JS
4903 port_speed = 1000;
4904 break;
26d830ec 4905 case LPFC_ASYNC_LINK_SPEED_10GBPS:
8b68cd52
JS
4906 port_speed = 10000;
4907 break;
26d830ec
JS
4908 case LPFC_ASYNC_LINK_SPEED_20GBPS:
4909 port_speed = 20000;
4910 break;
4911 case LPFC_ASYNC_LINK_SPEED_25GBPS:
4912 port_speed = 25000;
4913 break;
4914 case LPFC_ASYNC_LINK_SPEED_40GBPS:
4915 port_speed = 40000;
4916 break;
a1e4d3d8
DK
4917 case LPFC_ASYNC_LINK_SPEED_100GBPS:
4918 port_speed = 100000;
4919 break;
8b68cd52
JS
4920 default:
4921 port_speed = 0;
4922 }
4923 break;
4924 case LPFC_TRAILER_CODE_FC:
4925 switch (speed_code) {
26d830ec 4926 case LPFC_FC_LA_SPEED_UNKNOWN:
8b68cd52
JS
4927 port_speed = 0;
4928 break;
26d830ec 4929 case LPFC_FC_LA_SPEED_1G:
8b68cd52
JS
4930 port_speed = 1000;
4931 break;
26d830ec 4932 case LPFC_FC_LA_SPEED_2G:
8b68cd52
JS
4933 port_speed = 2000;
4934 break;
26d830ec 4935 case LPFC_FC_LA_SPEED_4G:
8b68cd52
JS
4936 port_speed = 4000;
4937 break;
26d830ec 4938 case LPFC_FC_LA_SPEED_8G:
8b68cd52
JS
4939 port_speed = 8000;
4940 break;
26d830ec 4941 case LPFC_FC_LA_SPEED_10G:
8b68cd52
JS
4942 port_speed = 10000;
4943 break;
26d830ec 4944 case LPFC_FC_LA_SPEED_16G:
8b68cd52
JS
4945 port_speed = 16000;
4946 break;
d38dd52c
JS
4947 case LPFC_FC_LA_SPEED_32G:
4948 port_speed = 32000;
4949 break;
fbd8a6ba
JS
4950 case LPFC_FC_LA_SPEED_64G:
4951 port_speed = 64000;
4952 break;
1dc5ec24
JS
4953 case LPFC_FC_LA_SPEED_128G:
4954 port_speed = 128000;
4955 break;
8b68cd52
JS
4956 default:
4957 port_speed = 0;
4958 }
4959 break;
4960 default:
4961 port_speed = 0;
4962 }
4963 return port_speed;
4964}
4965
da0436e9 4966/**
70f3c073 4967 * lpfc_sli4_async_link_evt - Process the asynchronous FCoE link event
da0436e9
JS
4968 * @phba: pointer to lpfc hba data structure.
4969 * @acqe_link: pointer to the async link completion queue entry.
4970 *
70f3c073 4971 * This routine is to handle the SLI4 asynchronous FCoE link event.
da0436e9
JS
4972 **/
4973static void
4974lpfc_sli4_async_link_evt(struct lpfc_hba *phba,
4975 struct lpfc_acqe_link *acqe_link)
4976{
4977 struct lpfc_dmabuf *mp;
4978 LPFC_MBOXQ_t *pmb;
4979 MAILBOX_t *mb;
76a95d75 4980 struct lpfc_mbx_read_top *la;
da0436e9 4981 uint8_t att_type;
76a95d75 4982 int rc;
da0436e9
JS
4983
4984 att_type = lpfc_sli4_parse_latt_type(phba, acqe_link);
76a95d75 4985 if (att_type != LPFC_ATT_LINK_DOWN && att_type != LPFC_ATT_LINK_UP)
da0436e9 4986 return;
32b9793f 4987 phba->fcoe_eventtag = acqe_link->event_tag;
da0436e9
JS
4988 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
4989 if (!pmb) {
372c187b 4990 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
4991 "0395 The mboxq allocation failed\n");
4992 return;
4993 }
4994 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
4995 if (!mp) {
372c187b 4996 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
4997 "0396 The lpfc_dmabuf allocation failed\n");
4998 goto out_free_pmb;
4999 }
5000 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
5001 if (!mp->virt) {
372c187b 5002 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
5003 "0397 The mbuf allocation failed\n");
5004 goto out_free_dmabuf;
5005 }
5006
5007 /* Cleanup any outstanding ELS commands */
5008 lpfc_els_flush_all_cmd(phba);
5009
5010 /* Block ELS IOCBs until we have done process link event */
895427bd 5011 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
da0436e9
JS
5012
5013 /* Update link event statistics */
5014 phba->sli.slistat.link_event++;
5015
76a95d75
JS
5016 /* Create lpfc_handle_latt mailbox command from link ACQE */
5017 lpfc_read_topology(phba, pmb, mp);
5018 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
da0436e9
JS
5019 pmb->vport = phba->pport;
5020
da0436e9
JS
5021 /* Keep the link status for extra SLI4 state machine reference */
5022 phba->sli4_hba.link_state.speed =
8b68cd52
JS
5023 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_LINK,
5024 bf_get(lpfc_acqe_link_speed, acqe_link));
da0436e9
JS
5025 phba->sli4_hba.link_state.duplex =
5026 bf_get(lpfc_acqe_link_duplex, acqe_link);
5027 phba->sli4_hba.link_state.status =
5028 bf_get(lpfc_acqe_link_status, acqe_link);
70f3c073
JS
5029 phba->sli4_hba.link_state.type =
5030 bf_get(lpfc_acqe_link_type, acqe_link);
5031 phba->sli4_hba.link_state.number =
5032 bf_get(lpfc_acqe_link_number, acqe_link);
da0436e9
JS
5033 phba->sli4_hba.link_state.fault =
5034 bf_get(lpfc_acqe_link_fault, acqe_link);
65467b6b 5035 phba->sli4_hba.link_state.logical_speed =
8b68cd52
JS
5036 bf_get(lpfc_acqe_logical_link_speed, acqe_link) * 10;
5037
70f3c073 5038 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
c31098ce
JS
5039 "2900 Async FC/FCoE Link event - Speed:%dGBit "
5040 "duplex:x%x LA Type:x%x Port Type:%d Port Number:%d "
5041 "Logical speed:%dMbps Fault:%d\n",
70f3c073
JS
5042 phba->sli4_hba.link_state.speed,
5043 phba->sli4_hba.link_state.topology,
5044 phba->sli4_hba.link_state.status,
5045 phba->sli4_hba.link_state.type,
5046 phba->sli4_hba.link_state.number,
8b68cd52 5047 phba->sli4_hba.link_state.logical_speed,
70f3c073 5048 phba->sli4_hba.link_state.fault);
76a95d75
JS
5049 /*
5050 * For FC Mode: issue the READ_TOPOLOGY mailbox command to fetch
5051 * topology info. Note: Optional for non FC-AL ports.
5052 */
5053 if (!(phba->hba_flag & HBA_FCOE_MODE)) {
5054 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
5055 if (rc == MBX_NOT_FINISHED)
5056 goto out_free_dmabuf;
5057 return;
5058 }
5059 /*
5060 * For FCoE Mode: fill in all the topology information we need and call
5061 * the READ_TOPOLOGY completion routine to continue without actually
5062 * sending the READ_TOPOLOGY mailbox command to the port.
5063 */
23288b78 5064 /* Initialize completion status */
76a95d75 5065 mb = &pmb->u.mb;
23288b78
JS
5066 mb->mbxStatus = MBX_SUCCESS;
5067
5068 /* Parse port fault information field */
5069 lpfc_sli4_parse_latt_fault(phba, acqe_link);
76a95d75
JS
5070
5071 /* Parse and translate link attention fields */
5072 la = (struct lpfc_mbx_read_top *) &pmb->u.mb.un.varReadTop;
5073 la->eventTag = acqe_link->event_tag;
5074 bf_set(lpfc_mbx_read_top_att_type, la, att_type);
5075 bf_set(lpfc_mbx_read_top_link_spd, la,
a085e87c 5076 (bf_get(lpfc_acqe_link_speed, acqe_link)));
76a95d75
JS
5077
5078 /* Fake the the following irrelvant fields */
5079 bf_set(lpfc_mbx_read_top_topology, la, LPFC_TOPOLOGY_PT_PT);
5080 bf_set(lpfc_mbx_read_top_alpa_granted, la, 0);
5081 bf_set(lpfc_mbx_read_top_il, la, 0);
5082 bf_set(lpfc_mbx_read_top_pb, la, 0);
5083 bf_set(lpfc_mbx_read_top_fa, la, 0);
5084 bf_set(lpfc_mbx_read_top_mm, la, 0);
da0436e9
JS
5085
5086 /* Invoke the lpfc_handle_latt mailbox command callback function */
76a95d75 5087 lpfc_mbx_cmpl_read_topology(phba, pmb);
da0436e9 5088
5b75da2f 5089 return;
da0436e9
JS
5090
5091out_free_dmabuf:
5092 kfree(mp);
5093out_free_pmb:
5094 mempool_free(pmb, phba->mbox_mem_pool);
5095}
5096
1dc5ec24
JS
5097/**
5098 * lpfc_async_link_speed_to_read_top - Parse async evt link speed code to read
5099 * topology.
5100 * @phba: pointer to lpfc hba data structure.
1dc5ec24
JS
5101 * @speed_code: asynchronous event link speed code.
5102 *
5103 * This routine is to parse the giving SLI4 async event link speed code into
5104 * value of Read topology link speed.
5105 *
5106 * Return: link speed in terms of Read topology.
5107 **/
5108static uint8_t
5109lpfc_async_link_speed_to_read_top(struct lpfc_hba *phba, uint8_t speed_code)
5110{
5111 uint8_t port_speed;
5112
5113 switch (speed_code) {
5114 case LPFC_FC_LA_SPEED_1G:
5115 port_speed = LPFC_LINK_SPEED_1GHZ;
5116 break;
5117 case LPFC_FC_LA_SPEED_2G:
5118 port_speed = LPFC_LINK_SPEED_2GHZ;
5119 break;
5120 case LPFC_FC_LA_SPEED_4G:
5121 port_speed = LPFC_LINK_SPEED_4GHZ;
5122 break;
5123 case LPFC_FC_LA_SPEED_8G:
5124 port_speed = LPFC_LINK_SPEED_8GHZ;
5125 break;
5126 case LPFC_FC_LA_SPEED_16G:
5127 port_speed = LPFC_LINK_SPEED_16GHZ;
5128 break;
5129 case LPFC_FC_LA_SPEED_32G:
5130 port_speed = LPFC_LINK_SPEED_32GHZ;
5131 break;
5132 case LPFC_FC_LA_SPEED_64G:
5133 port_speed = LPFC_LINK_SPEED_64GHZ;
5134 break;
5135 case LPFC_FC_LA_SPEED_128G:
5136 port_speed = LPFC_LINK_SPEED_128GHZ;
5137 break;
5138 case LPFC_FC_LA_SPEED_256G:
5139 port_speed = LPFC_LINK_SPEED_256GHZ;
5140 break;
5141 default:
5142 port_speed = 0;
5143 break;
5144 }
5145
5146 return port_speed;
5147}
5148
5149#define trunk_link_status(__idx)\
5150 bf_get(lpfc_acqe_fc_la_trunk_config_port##__idx, acqe_fc) ?\
5151 ((phba->trunk_link.link##__idx.state == LPFC_LINK_UP) ?\
5152 "Link up" : "Link down") : "NA"
5153/* Did port __idx reported an error */
5154#define trunk_port_fault(__idx)\
5155 bf_get(lpfc_acqe_fc_la_trunk_config_port##__idx, acqe_fc) ?\
5156 (port_fault & (1 << __idx) ? "YES" : "NO") : "NA"
5157
5158static void
5159lpfc_update_trunk_link_status(struct lpfc_hba *phba,
5160 struct lpfc_acqe_fc_la *acqe_fc)
5161{
5162 uint8_t port_fault = bf_get(lpfc_acqe_fc_la_trunk_linkmask, acqe_fc);
5163 uint8_t err = bf_get(lpfc_acqe_fc_la_trunk_fault, acqe_fc);
5164
5165 phba->sli4_hba.link_state.speed =
5166 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
5167 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
5168
5169 phba->sli4_hba.link_state.logical_speed =
b8e6f136 5170 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
1dc5ec24
JS
5171 /* We got FC link speed, convert to fc_linkspeed (READ_TOPOLOGY) */
5172 phba->fc_linkspeed =
5173 lpfc_async_link_speed_to_read_top(
5174 phba,
5175 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
5176
5177 if (bf_get(lpfc_acqe_fc_la_trunk_config_port0, acqe_fc)) {
5178 phba->trunk_link.link0.state =
5179 bf_get(lpfc_acqe_fc_la_trunk_link_status_port0, acqe_fc)
5180 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5181 phba->trunk_link.link0.fault = port_fault & 0x1 ? err : 0;
1dc5ec24
JS
5182 }
5183 if (bf_get(lpfc_acqe_fc_la_trunk_config_port1, acqe_fc)) {
5184 phba->trunk_link.link1.state =
5185 bf_get(lpfc_acqe_fc_la_trunk_link_status_port1, acqe_fc)
5186 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5187 phba->trunk_link.link1.fault = port_fault & 0x2 ? err : 0;
1dc5ec24
JS
5188 }
5189 if (bf_get(lpfc_acqe_fc_la_trunk_config_port2, acqe_fc)) {
5190 phba->trunk_link.link2.state =
5191 bf_get(lpfc_acqe_fc_la_trunk_link_status_port2, acqe_fc)
5192 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5193 phba->trunk_link.link2.fault = port_fault & 0x4 ? err : 0;
1dc5ec24
JS
5194 }
5195 if (bf_get(lpfc_acqe_fc_la_trunk_config_port3, acqe_fc)) {
5196 phba->trunk_link.link3.state =
5197 bf_get(lpfc_acqe_fc_la_trunk_link_status_port3, acqe_fc)
5198 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5199 phba->trunk_link.link3.fault = port_fault & 0x8 ? err : 0;
1dc5ec24
JS
5200 }
5201
372c187b 5202 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1dc5ec24
JS
5203 "2910 Async FC Trunking Event - Speed:%d\n"
5204 "\tLogical speed:%d "
5205 "port0: %s port1: %s port2: %s port3: %s\n",
5206 phba->sli4_hba.link_state.speed,
5207 phba->sli4_hba.link_state.logical_speed,
5208 trunk_link_status(0), trunk_link_status(1),
5209 trunk_link_status(2), trunk_link_status(3));
5210
5211 if (port_fault)
372c187b 5212 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1dc5ec24
JS
5213 "3202 trunk error:0x%x (%s) seen on port0:%s "
5214 /*
5215 * SLI-4: We have only 0xA error codes
5216 * defined as of now. print an appropriate
5217 * message in case driver needs to be updated.
5218 */
5219 "port1:%s port2:%s port3:%s\n", err, err > 0xA ?
5220 "UNDEFINED. update driver." : trunk_errmsg[err],
5221 trunk_port_fault(0), trunk_port_fault(1),
5222 trunk_port_fault(2), trunk_port_fault(3));
5223}
5224
5225
70f3c073
JS
5226/**
5227 * lpfc_sli4_async_fc_evt - Process the asynchronous FC link event
5228 * @phba: pointer to lpfc hba data structure.
5229 * @acqe_fc: pointer to the async fc completion queue entry.
5230 *
5231 * This routine is to handle the SLI4 asynchronous FC event. It will simply log
5232 * that the event was received and then issue a read_topology mailbox command so
5233 * that the rest of the driver will treat it the same as SLI3.
5234 **/
5235static void
5236lpfc_sli4_async_fc_evt(struct lpfc_hba *phba, struct lpfc_acqe_fc_la *acqe_fc)
5237{
5238 struct lpfc_dmabuf *mp;
5239 LPFC_MBOXQ_t *pmb;
7bdedb34
JS
5240 MAILBOX_t *mb;
5241 struct lpfc_mbx_read_top *la;
70f3c073
JS
5242 int rc;
5243
5244 if (bf_get(lpfc_trailer_type, acqe_fc) !=
5245 LPFC_FC_LA_EVENT_TYPE_FC_LINK) {
372c187b 5246 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
70f3c073
JS
5247 "2895 Non FC link Event detected.(%d)\n",
5248 bf_get(lpfc_trailer_type, acqe_fc));
5249 return;
5250 }
1dc5ec24
JS
5251
5252 if (bf_get(lpfc_acqe_fc_la_att_type, acqe_fc) ==
5253 LPFC_FC_LA_TYPE_TRUNKING_EVENT) {
5254 lpfc_update_trunk_link_status(phba, acqe_fc);
5255 return;
5256 }
5257
70f3c073
JS
5258 /* Keep the link status for extra SLI4 state machine reference */
5259 phba->sli4_hba.link_state.speed =
8b68cd52
JS
5260 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
5261 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
70f3c073
JS
5262 phba->sli4_hba.link_state.duplex = LPFC_ASYNC_LINK_DUPLEX_FULL;
5263 phba->sli4_hba.link_state.topology =
5264 bf_get(lpfc_acqe_fc_la_topology, acqe_fc);
5265 phba->sli4_hba.link_state.status =
5266 bf_get(lpfc_acqe_fc_la_att_type, acqe_fc);
5267 phba->sli4_hba.link_state.type =
5268 bf_get(lpfc_acqe_fc_la_port_type, acqe_fc);
5269 phba->sli4_hba.link_state.number =
5270 bf_get(lpfc_acqe_fc_la_port_number, acqe_fc);
5271 phba->sli4_hba.link_state.fault =
5272 bf_get(lpfc_acqe_link_fault, acqe_fc);
b8e6f136
JS
5273
5274 if (bf_get(lpfc_acqe_fc_la_att_type, acqe_fc) ==
5275 LPFC_FC_LA_TYPE_LINK_DOWN)
5276 phba->sli4_hba.link_state.logical_speed = 0;
5277 else if (!phba->sli4_hba.conf_trunk)
5278 phba->sli4_hba.link_state.logical_speed =
8b68cd52 5279 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
b8e6f136 5280
70f3c073
JS
5281 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5282 "2896 Async FC event - Speed:%dGBaud Topology:x%x "
5283 "LA Type:x%x Port Type:%d Port Number:%d Logical speed:"
5284 "%dMbps Fault:%d\n",
5285 phba->sli4_hba.link_state.speed,
5286 phba->sli4_hba.link_state.topology,
5287 phba->sli4_hba.link_state.status,
5288 phba->sli4_hba.link_state.type,
5289 phba->sli4_hba.link_state.number,
8b68cd52 5290 phba->sli4_hba.link_state.logical_speed,
70f3c073
JS
5291 phba->sli4_hba.link_state.fault);
5292 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
5293 if (!pmb) {
372c187b 5294 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
70f3c073
JS
5295 "2897 The mboxq allocation failed\n");
5296 return;
5297 }
5298 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
5299 if (!mp) {
372c187b 5300 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
70f3c073
JS
5301 "2898 The lpfc_dmabuf allocation failed\n");
5302 goto out_free_pmb;
5303 }
5304 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
5305 if (!mp->virt) {
372c187b 5306 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
70f3c073
JS
5307 "2899 The mbuf allocation failed\n");
5308 goto out_free_dmabuf;
5309 }
5310
5311 /* Cleanup any outstanding ELS commands */
5312 lpfc_els_flush_all_cmd(phba);
5313
5314 /* Block ELS IOCBs until we have done process link event */
895427bd 5315 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
70f3c073
JS
5316
5317 /* Update link event statistics */
5318 phba->sli.slistat.link_event++;
5319
5320 /* Create lpfc_handle_latt mailbox command from link ACQE */
5321 lpfc_read_topology(phba, pmb, mp);
5322 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
5323 pmb->vport = phba->pport;
5324
7bdedb34 5325 if (phba->sli4_hba.link_state.status != LPFC_FC_LA_TYPE_LINK_UP) {
ae9e28f3
JS
5326 phba->link_flag &= ~(LS_MDS_LINK_DOWN | LS_MDS_LOOPBACK);
5327
5328 switch (phba->sli4_hba.link_state.status) {
5329 case LPFC_FC_LA_TYPE_MDS_LINK_DOWN:
5330 phba->link_flag |= LS_MDS_LINK_DOWN;
5331 break;
5332 case LPFC_FC_LA_TYPE_MDS_LOOPBACK:
5333 phba->link_flag |= LS_MDS_LOOPBACK;
5334 break;
5335 default:
5336 break;
5337 }
5338
23288b78 5339 /* Initialize completion status */
7bdedb34 5340 mb = &pmb->u.mb;
23288b78
JS
5341 mb->mbxStatus = MBX_SUCCESS;
5342
5343 /* Parse port fault information field */
5344 lpfc_sli4_parse_latt_fault(phba, (void *)acqe_fc);
7bdedb34
JS
5345
5346 /* Parse and translate link attention fields */
5347 la = (struct lpfc_mbx_read_top *)&pmb->u.mb.un.varReadTop;
5348 la->eventTag = acqe_fc->event_tag;
7bdedb34 5349
aeb3c817
JS
5350 if (phba->sli4_hba.link_state.status ==
5351 LPFC_FC_LA_TYPE_UNEXP_WWPN) {
5352 bf_set(lpfc_mbx_read_top_att_type, la,
5353 LPFC_FC_LA_TYPE_UNEXP_WWPN);
5354 } else {
5355 bf_set(lpfc_mbx_read_top_att_type, la,
5356 LPFC_FC_LA_TYPE_LINK_DOWN);
5357 }
7bdedb34
JS
5358 /* Invoke the mailbox command callback function */
5359 lpfc_mbx_cmpl_read_topology(phba, pmb);
5360
5361 return;
5362 }
5363
70f3c073
JS
5364 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
5365 if (rc == MBX_NOT_FINISHED)
5366 goto out_free_dmabuf;
5367 return;
5368
5369out_free_dmabuf:
5370 kfree(mp);
5371out_free_pmb:
5372 mempool_free(pmb, phba->mbox_mem_pool);
5373}
5374
5375/**
5376 * lpfc_sli4_async_sli_evt - Process the asynchronous SLI link event
5377 * @phba: pointer to lpfc hba data structure.
fe614acd 5378 * @acqe_sli: pointer to the async SLI completion queue entry.
70f3c073
JS
5379 *
5380 * This routine is to handle the SLI4 asynchronous SLI events.
5381 **/
5382static void
5383lpfc_sli4_async_sli_evt(struct lpfc_hba *phba, struct lpfc_acqe_sli *acqe_sli)
5384{
4b8bae08 5385 char port_name;
8c1312e1 5386 char message[128];
4b8bae08 5387 uint8_t status;
946727dc 5388 uint8_t evt_type;
448193b5 5389 uint8_t operational = 0;
946727dc 5390 struct temp_event temp_event_data;
4b8bae08 5391 struct lpfc_acqe_misconfigured_event *misconfigured;
946727dc 5392 struct Scsi_Host *shost;
cd71348a
JS
5393 struct lpfc_vport **vports;
5394 int rc, i;
946727dc
JS
5395
5396 evt_type = bf_get(lpfc_trailer_type, acqe_sli);
4b8bae08 5397
448193b5 5398 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
d11ed16d
JS
5399 "2901 Async SLI event - Type:%d, Event Data: x%08x "
5400 "x%08x x%08x x%08x\n", evt_type,
448193b5 5401 acqe_sli->event_data1, acqe_sli->event_data2,
d11ed16d 5402 acqe_sli->reserved, acqe_sli->trailer);
4b8bae08
JS
5403
5404 port_name = phba->Port[0];
5405 if (port_name == 0x00)
5406 port_name = '?'; /* get port name is empty */
5407
946727dc
JS
5408 switch (evt_type) {
5409 case LPFC_SLI_EVENT_TYPE_OVER_TEMP:
5410 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
5411 temp_event_data.event_code = LPFC_THRESHOLD_TEMP;
5412 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
5413
5414 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
5415 "3190 Over Temperature:%d Celsius- Port Name %c\n",
5416 acqe_sli->event_data1, port_name);
5417
310429ef 5418 phba->sfp_warning |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
946727dc
JS
5419 shost = lpfc_shost_from_vport(phba->pport);
5420 fc_host_post_vendor_event(shost, fc_get_event_number(),
5421 sizeof(temp_event_data),
5422 (char *)&temp_event_data,
5423 SCSI_NL_VID_TYPE_PCI
5424 | PCI_VENDOR_ID_EMULEX);
5425 break;
5426 case LPFC_SLI_EVENT_TYPE_NORM_TEMP:
5427 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
5428 temp_event_data.event_code = LPFC_NORMAL_TEMP;
5429 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
5430
5431 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5432 "3191 Normal Temperature:%d Celsius - Port Name %c\n",
5433 acqe_sli->event_data1, port_name);
5434
5435 shost = lpfc_shost_from_vport(phba->pport);
5436 fc_host_post_vendor_event(shost, fc_get_event_number(),
5437 sizeof(temp_event_data),
5438 (char *)&temp_event_data,
5439 SCSI_NL_VID_TYPE_PCI
5440 | PCI_VENDOR_ID_EMULEX);
5441 break;
5442 case LPFC_SLI_EVENT_TYPE_MISCONFIGURED:
5443 misconfigured = (struct lpfc_acqe_misconfigured_event *)
4b8bae08
JS
5444 &acqe_sli->event_data1;
5445
946727dc
JS
5446 /* fetch the status for this port */
5447 switch (phba->sli4_hba.lnk_info.lnk_no) {
5448 case LPFC_LINK_NUMBER_0:
448193b5
JS
5449 status = bf_get(lpfc_sli_misconfigured_port0_state,
5450 &misconfigured->theEvent);
5451 operational = bf_get(lpfc_sli_misconfigured_port0_op,
4b8bae08 5452 &misconfigured->theEvent);
946727dc
JS
5453 break;
5454 case LPFC_LINK_NUMBER_1:
448193b5
JS
5455 status = bf_get(lpfc_sli_misconfigured_port1_state,
5456 &misconfigured->theEvent);
5457 operational = bf_get(lpfc_sli_misconfigured_port1_op,
4b8bae08 5458 &misconfigured->theEvent);
946727dc
JS
5459 break;
5460 case LPFC_LINK_NUMBER_2:
448193b5
JS
5461 status = bf_get(lpfc_sli_misconfigured_port2_state,
5462 &misconfigured->theEvent);
5463 operational = bf_get(lpfc_sli_misconfigured_port2_op,
4b8bae08 5464 &misconfigured->theEvent);
946727dc
JS
5465 break;
5466 case LPFC_LINK_NUMBER_3:
448193b5
JS
5467 status = bf_get(lpfc_sli_misconfigured_port3_state,
5468 &misconfigured->theEvent);
5469 operational = bf_get(lpfc_sli_misconfigured_port3_op,
4b8bae08 5470 &misconfigured->theEvent);
946727dc
JS
5471 break;
5472 default:
372c187b 5473 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
448193b5
JS
5474 "3296 "
5475 "LPFC_SLI_EVENT_TYPE_MISCONFIGURED "
5476 "event: Invalid link %d",
5477 phba->sli4_hba.lnk_info.lnk_no);
5478 return;
946727dc 5479 }
4b8bae08 5480
448193b5
JS
5481 /* Skip if optic state unchanged */
5482 if (phba->sli4_hba.lnk_info.optic_state == status)
5483 return;
5484
946727dc
JS
5485 switch (status) {
5486 case LPFC_SLI_EVENT_STATUS_VALID:
448193b5
JS
5487 sprintf(message, "Physical Link is functional");
5488 break;
946727dc
JS
5489 case LPFC_SLI_EVENT_STATUS_NOT_PRESENT:
5490 sprintf(message, "Optics faulted/incorrectly "
5491 "installed/not installed - Reseat optics, "
5492 "if issue not resolved, replace.");
5493 break;
5494 case LPFC_SLI_EVENT_STATUS_WRONG_TYPE:
5495 sprintf(message,
5496 "Optics of two types installed - Remove one "
5497 "optic or install matching pair of optics.");
5498 break;
5499 case LPFC_SLI_EVENT_STATUS_UNSUPPORTED:
5500 sprintf(message, "Incompatible optics - Replace with "
292098be 5501 "compatible optics for card to function.");
946727dc 5502 break;
448193b5
JS
5503 case LPFC_SLI_EVENT_STATUS_UNQUALIFIED:
5504 sprintf(message, "Unqualified optics - Replace with "
5505 "Avago optics for Warranty and Technical "
5506 "Support - Link is%s operational",
2ea259ee 5507 (operational) ? " not" : "");
448193b5
JS
5508 break;
5509 case LPFC_SLI_EVENT_STATUS_UNCERTIFIED:
5510 sprintf(message, "Uncertified optics - Replace with "
5511 "Avago-certified optics to enable link "
5512 "operation - Link is%s operational",
2ea259ee 5513 (operational) ? " not" : "");
448193b5 5514 break;
946727dc
JS
5515 default:
5516 /* firmware is reporting a status we don't know about */
5517 sprintf(message, "Unknown event status x%02x", status);
5518 break;
5519 }
cd71348a
JS
5520
5521 /* Issue READ_CONFIG mbox command to refresh supported speeds */
5522 rc = lpfc_sli4_read_config(phba);
3952e91f 5523 if (rc) {
cd71348a 5524 phba->lmt = 0;
372c187b
DK
5525 lpfc_printf_log(phba, KERN_ERR,
5526 LOG_TRACE_EVENT,
cd71348a 5527 "3194 Unable to retrieve supported "
3952e91f 5528 "speeds, rc = 0x%x\n", rc);
cd71348a
JS
5529 }
5530 vports = lpfc_create_vport_work_array(phba);
5531 if (vports != NULL) {
5532 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
5533 i++) {
5534 shost = lpfc_shost_from_vport(vports[i]);
5535 lpfc_host_supported_speeds_set(shost);
5536 }
5537 }
5538 lpfc_destroy_vport_work_array(phba, vports);
5539
448193b5 5540 phba->sli4_hba.lnk_info.optic_state = status;
946727dc 5541 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
448193b5 5542 "3176 Port Name %c %s\n", port_name, message);
946727dc
JS
5543 break;
5544 case LPFC_SLI_EVENT_TYPE_REMOTE_DPORT:
5545 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5546 "3192 Remote DPort Test Initiated - "
5547 "Event Data1:x%08x Event Data2: x%08x\n",
5548 acqe_sli->event_data1, acqe_sli->event_data2);
4b8bae08 5549 break;
e7d85952
JS
5550 case LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN:
5551 /* Misconfigured WWN. Reports that the SLI Port is configured
5552 * to use FA-WWN, but the attached device doesn’t support it.
5553 * No driver action is required.
5554 * Event Data1 - N.A, Event Data2 - N.A
5555 */
5556 lpfc_log_msg(phba, KERN_WARNING, LOG_SLI,
5557 "2699 Misconfigured FA-WWN - Attached device does "
5558 "not support FA-WWN\n");
5559 break;
d11ed16d
JS
5560 case LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE:
5561 /* EEPROM failure. No driver action is required */
5562 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
5563 "2518 EEPROM failure - "
5564 "Event Data1: x%08x Event Data2: x%08x\n",
5565 acqe_sli->event_data1, acqe_sli->event_data2);
5566 break;
4b8bae08 5567 default:
946727dc 5568 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
d11ed16d 5569 "3193 Unrecognized SLI event, type: 0x%x",
946727dc 5570 evt_type);
4b8bae08
JS
5571 break;
5572 }
70f3c073
JS
5573}
5574
fc2b989b
JS
5575/**
5576 * lpfc_sli4_perform_vport_cvl - Perform clear virtual link on a vport
5577 * @vport: pointer to vport data structure.
5578 *
5579 * This routine is to perform Clear Virtual Link (CVL) on a vport in
5580 * response to a CVL event.
5581 *
5582 * Return the pointer to the ndlp with the vport if successful, otherwise
5583 * return NULL.
5584 **/
5585static struct lpfc_nodelist *
5586lpfc_sli4_perform_vport_cvl(struct lpfc_vport *vport)
5587{
5588 struct lpfc_nodelist *ndlp;
5589 struct Scsi_Host *shost;
5590 struct lpfc_hba *phba;
5591
5592 if (!vport)
5593 return NULL;
fc2b989b
JS
5594 phba = vport->phba;
5595 if (!phba)
5596 return NULL;
78730cfe
JS
5597 ndlp = lpfc_findnode_did(vport, Fabric_DID);
5598 if (!ndlp) {
5599 /* Cannot find existing Fabric ndlp, so allocate a new one */
9d3d340d 5600 ndlp = lpfc_nlp_init(vport, Fabric_DID);
78730cfe
JS
5601 if (!ndlp)
5602 return 0;
78730cfe
JS
5603 /* Set the node type */
5604 ndlp->nlp_type |= NLP_FABRIC;
5605 /* Put ndlp onto node list */
5606 lpfc_enqueue_node(vport, ndlp);
5607 } else if (!NLP_CHK_NODE_ACT(ndlp)) {
5608 /* re-setup ndlp without removing from node list */
5609 ndlp = lpfc_enable_node(vport, ndlp, NLP_STE_UNUSED_NODE);
5610 if (!ndlp)
5611 return 0;
5612 }
63e801ce
JS
5613 if ((phba->pport->port_state < LPFC_FLOGI) &&
5614 (phba->pport->port_state != LPFC_VPORT_FAILED))
fc2b989b
JS
5615 return NULL;
5616 /* If virtual link is not yet instantiated ignore CVL */
63e801ce
JS
5617 if ((vport != phba->pport) && (vport->port_state < LPFC_FDISC)
5618 && (vport->port_state != LPFC_VPORT_FAILED))
fc2b989b
JS
5619 return NULL;
5620 shost = lpfc_shost_from_vport(vport);
5621 if (!shost)
5622 return NULL;
5623 lpfc_linkdown_port(vport);
5624 lpfc_cleanup_pending_mbox(vport);
5625 spin_lock_irq(shost->host_lock);
5626 vport->fc_flag |= FC_VPORT_CVL_RCVD;
5627 spin_unlock_irq(shost->host_lock);
5628
5629 return ndlp;
5630}
5631
5632/**
5633 * lpfc_sli4_perform_all_vport_cvl - Perform clear virtual link on all vports
fe614acd 5634 * @phba: pointer to lpfc hba data structure.
fc2b989b
JS
5635 *
5636 * This routine is to perform Clear Virtual Link (CVL) on all vports in
5637 * response to a FCF dead event.
5638 **/
5639static void
5640lpfc_sli4_perform_all_vport_cvl(struct lpfc_hba *phba)
5641{
5642 struct lpfc_vport **vports;
5643 int i;
5644
5645 vports = lpfc_create_vport_work_array(phba);
5646 if (vports)
5647 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
5648 lpfc_sli4_perform_vport_cvl(vports[i]);
5649 lpfc_destroy_vport_work_array(phba, vports);
5650}
5651
da0436e9 5652/**
76a95d75 5653 * lpfc_sli4_async_fip_evt - Process the asynchronous FCoE FIP event
da0436e9 5654 * @phba: pointer to lpfc hba data structure.
fe614acd 5655 * @acqe_fip: pointer to the async fcoe completion queue entry.
da0436e9
JS
5656 *
5657 * This routine is to handle the SLI4 asynchronous fcoe event.
5658 **/
5659static void
76a95d75 5660lpfc_sli4_async_fip_evt(struct lpfc_hba *phba,
70f3c073 5661 struct lpfc_acqe_fip *acqe_fip)
da0436e9 5662{
70f3c073 5663 uint8_t event_type = bf_get(lpfc_trailer_type, acqe_fip);
da0436e9 5664 int rc;
6669f9bb
JS
5665 struct lpfc_vport *vport;
5666 struct lpfc_nodelist *ndlp;
5667 struct Scsi_Host *shost;
695a814e
JS
5668 int active_vlink_present;
5669 struct lpfc_vport **vports;
5670 int i;
da0436e9 5671
70f3c073
JS
5672 phba->fc_eventTag = acqe_fip->event_tag;
5673 phba->fcoe_eventtag = acqe_fip->event_tag;
da0436e9 5674 switch (event_type) {
70f3c073
JS
5675 case LPFC_FIP_EVENT_TYPE_NEW_FCF:
5676 case LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD:
5677 if (event_type == LPFC_FIP_EVENT_TYPE_NEW_FCF)
372c187b 5678 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
a93ff37a
JS
5679 "2546 New FCF event, evt_tag:x%x, "
5680 "index:x%x\n",
70f3c073
JS
5681 acqe_fip->event_tag,
5682 acqe_fip->index);
999d813f
JS
5683 else
5684 lpfc_printf_log(phba, KERN_WARNING, LOG_FIP |
5685 LOG_DISCOVERY,
a93ff37a
JS
5686 "2788 FCF param modified event, "
5687 "evt_tag:x%x, index:x%x\n",
70f3c073
JS
5688 acqe_fip->event_tag,
5689 acqe_fip->index);
38b92ef8 5690 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
0c9ab6f5
JS
5691 /*
5692 * During period of FCF discovery, read the FCF
5693 * table record indexed by the event to update
a93ff37a 5694 * FCF roundrobin failover eligible FCF bmask.
0c9ab6f5
JS
5695 */
5696 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
5697 LOG_DISCOVERY,
a93ff37a
JS
5698 "2779 Read FCF (x%x) for updating "
5699 "roundrobin FCF failover bmask\n",
70f3c073
JS
5700 acqe_fip->index);
5701 rc = lpfc_sli4_read_fcf_rec(phba, acqe_fip->index);
0c9ab6f5 5702 }
38b92ef8
JS
5703
5704 /* If the FCF discovery is in progress, do nothing. */
3804dc84 5705 spin_lock_irq(&phba->hbalock);
a93ff37a 5706 if (phba->hba_flag & FCF_TS_INPROG) {
38b92ef8
JS
5707 spin_unlock_irq(&phba->hbalock);
5708 break;
5709 }
5710 /* If fast FCF failover rescan event is pending, do nothing */
036cad1f 5711 if (phba->fcf.fcf_flag & (FCF_REDISC_EVT | FCF_REDISC_PEND)) {
38b92ef8
JS
5712 spin_unlock_irq(&phba->hbalock);
5713 break;
5714 }
5715
c2b9712e
JS
5716 /* If the FCF has been in discovered state, do nothing. */
5717 if (phba->fcf.fcf_flag & FCF_SCAN_DONE) {
3804dc84
JS
5718 spin_unlock_irq(&phba->hbalock);
5719 break;
5720 }
5721 spin_unlock_irq(&phba->hbalock);
38b92ef8 5722
0c9ab6f5
JS
5723 /* Otherwise, scan the entire FCF table and re-discover SAN */
5724 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
a93ff37a
JS
5725 "2770 Start FCF table scan per async FCF "
5726 "event, evt_tag:x%x, index:x%x\n",
70f3c073 5727 acqe_fip->event_tag, acqe_fip->index);
0c9ab6f5
JS
5728 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba,
5729 LPFC_FCOE_FCF_GET_FIRST);
da0436e9 5730 if (rc)
372c187b 5731 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0c9ab6f5 5732 "2547 Issue FCF scan read FCF mailbox "
a93ff37a 5733 "command failed (x%x)\n", rc);
da0436e9
JS
5734 break;
5735
70f3c073 5736 case LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL:
372c187b
DK
5737 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5738 "2548 FCF Table full count 0x%x tag 0x%x\n",
5739 bf_get(lpfc_acqe_fip_fcf_count, acqe_fip),
5740 acqe_fip->event_tag);
da0436e9
JS
5741 break;
5742
70f3c073 5743 case LPFC_FIP_EVENT_TYPE_FCF_DEAD:
80c17849 5744 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
372c187b
DK
5745 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5746 "2549 FCF (x%x) disconnected from network, "
5747 "tag:x%x\n", acqe_fip->index,
5748 acqe_fip->event_tag);
38b92ef8
JS
5749 /*
5750 * If we are in the middle of FCF failover process, clear
5751 * the corresponding FCF bit in the roundrobin bitmap.
da0436e9 5752 */
fc2b989b 5753 spin_lock_irq(&phba->hbalock);
a1cadfef
JS
5754 if ((phba->fcf.fcf_flag & FCF_DISCOVERY) &&
5755 (phba->fcf.current_rec.fcf_indx != acqe_fip->index)) {
fc2b989b 5756 spin_unlock_irq(&phba->hbalock);
0c9ab6f5 5757 /* Update FLOGI FCF failover eligible FCF bmask */
70f3c073 5758 lpfc_sli4_fcf_rr_index_clear(phba, acqe_fip->index);
fc2b989b
JS
5759 break;
5760 }
38b92ef8
JS
5761 spin_unlock_irq(&phba->hbalock);
5762
5763 /* If the event is not for currently used fcf do nothing */
70f3c073 5764 if (phba->fcf.current_rec.fcf_indx != acqe_fip->index)
38b92ef8
JS
5765 break;
5766
5767 /*
5768 * Otherwise, request the port to rediscover the entire FCF
5769 * table for a fast recovery from case that the current FCF
5770 * is no longer valid as we are not in the middle of FCF
5771 * failover process already.
5772 */
c2b9712e
JS
5773 spin_lock_irq(&phba->hbalock);
5774 /* Mark the fast failover process in progress */
5775 phba->fcf.fcf_flag |= FCF_DEAD_DISC;
5776 spin_unlock_irq(&phba->hbalock);
5777
5778 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
5779 "2771 Start FCF fast failover process due to "
5780 "FCF DEAD event: evt_tag:x%x, fcf_index:x%x "
5781 "\n", acqe_fip->event_tag, acqe_fip->index);
5782 rc = lpfc_sli4_redisc_fcf_table(phba);
5783 if (rc) {
5784 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
372c187b 5785 LOG_TRACE_EVENT,
7afc0ce9 5786 "2772 Issue FCF rediscover mailbox "
c2b9712e
JS
5787 "command failed, fail through to FCF "
5788 "dead event\n");
5789 spin_lock_irq(&phba->hbalock);
5790 phba->fcf.fcf_flag &= ~FCF_DEAD_DISC;
5791 spin_unlock_irq(&phba->hbalock);
5792 /*
5793 * Last resort will fail over by treating this
5794 * as a link down to FCF registration.
5795 */
5796 lpfc_sli4_fcf_dead_failthrough(phba);
5797 } else {
5798 /* Reset FCF roundrobin bmask for new discovery */
5799 lpfc_sli4_clear_fcf_rr_bmask(phba);
5800 /*
5801 * Handling fast FCF failover to a DEAD FCF event is
5802 * considered equalivant to receiving CVL to all vports.
5803 */
5804 lpfc_sli4_perform_all_vport_cvl(phba);
5805 }
da0436e9 5806 break;
70f3c073 5807 case LPFC_FIP_EVENT_TYPE_CVL:
80c17849 5808 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
372c187b
DK
5809 lpfc_printf_log(phba, KERN_ERR,
5810 LOG_TRACE_EVENT,
6669f9bb 5811 "2718 Clear Virtual Link Received for VPI 0x%x"
70f3c073 5812 " tag 0x%x\n", acqe_fip->index, acqe_fip->event_tag);
6d368e53 5813
6669f9bb 5814 vport = lpfc_find_vport_by_vpid(phba,
5248a749 5815 acqe_fip->index);
fc2b989b 5816 ndlp = lpfc_sli4_perform_vport_cvl(vport);
6669f9bb
JS
5817 if (!ndlp)
5818 break;
695a814e
JS
5819 active_vlink_present = 0;
5820
5821 vports = lpfc_create_vport_work_array(phba);
5822 if (vports) {
5823 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
5824 i++) {
5825 if ((!(vports[i]->fc_flag &
5826 FC_VPORT_CVL_RCVD)) &&
5827 (vports[i]->port_state > LPFC_FDISC)) {
5828 active_vlink_present = 1;
5829 break;
5830 }
5831 }
5832 lpfc_destroy_vport_work_array(phba, vports);
5833 }
5834
cc82355a
JS
5835 /*
5836 * Don't re-instantiate if vport is marked for deletion.
5837 * If we are here first then vport_delete is going to wait
5838 * for discovery to complete.
5839 */
5840 if (!(vport->load_flag & FC_UNLOADING) &&
5841 active_vlink_present) {
695a814e
JS
5842 /*
5843 * If there are other active VLinks present,
5844 * re-instantiate the Vlink using FDISC.
5845 */
256ec0d0
JS
5846 mod_timer(&ndlp->nlp_delayfunc,
5847 jiffies + msecs_to_jiffies(1000));
fc2b989b 5848 shost = lpfc_shost_from_vport(vport);
6669f9bb
JS
5849 spin_lock_irq(shost->host_lock);
5850 ndlp->nlp_flag |= NLP_DELAY_TMO;
5851 spin_unlock_irq(shost->host_lock);
695a814e
JS
5852 ndlp->nlp_last_elscmd = ELS_CMD_FDISC;
5853 vport->port_state = LPFC_FDISC;
5854 } else {
ecfd03c6
JS
5855 /*
5856 * Otherwise, we request port to rediscover
5857 * the entire FCF table for a fast recovery
5858 * from possible case that the current FCF
0c9ab6f5
JS
5859 * is no longer valid if we are not already
5860 * in the FCF failover process.
ecfd03c6 5861 */
fc2b989b 5862 spin_lock_irq(&phba->hbalock);
0c9ab6f5 5863 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
fc2b989b
JS
5864 spin_unlock_irq(&phba->hbalock);
5865 break;
5866 }
5867 /* Mark the fast failover process in progress */
0c9ab6f5 5868 phba->fcf.fcf_flag |= FCF_ACVL_DISC;
fc2b989b 5869 spin_unlock_irq(&phba->hbalock);
0c9ab6f5
JS
5870 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
5871 LOG_DISCOVERY,
a93ff37a 5872 "2773 Start FCF failover per CVL, "
70f3c073 5873 "evt_tag:x%x\n", acqe_fip->event_tag);
ecfd03c6 5874 rc = lpfc_sli4_redisc_fcf_table(phba);
fc2b989b 5875 if (rc) {
0c9ab6f5 5876 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
372c187b 5877 LOG_TRACE_EVENT,
0c9ab6f5 5878 "2774 Issue FCF rediscover "
7afc0ce9 5879 "mailbox command failed, "
0c9ab6f5 5880 "through to CVL event\n");
fc2b989b 5881 spin_lock_irq(&phba->hbalock);
0c9ab6f5 5882 phba->fcf.fcf_flag &= ~FCF_ACVL_DISC;
fc2b989b 5883 spin_unlock_irq(&phba->hbalock);
ecfd03c6
JS
5884 /*
5885 * Last resort will be re-try on the
5886 * the current registered FCF entry.
5887 */
5888 lpfc_retry_pport_discovery(phba);
38b92ef8
JS
5889 } else
5890 /*
5891 * Reset FCF roundrobin bmask for new
5892 * discovery.
5893 */
7d791df7 5894 lpfc_sli4_clear_fcf_rr_bmask(phba);
6669f9bb
JS
5895 }
5896 break;
da0436e9 5897 default:
372c187b
DK
5898 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5899 "0288 Unknown FCoE event type 0x%x event tag "
5900 "0x%x\n", event_type, acqe_fip->event_tag);
da0436e9
JS
5901 break;
5902 }
5903}
5904
5905/**
5906 * lpfc_sli4_async_dcbx_evt - Process the asynchronous dcbx event
5907 * @phba: pointer to lpfc hba data structure.
fe614acd 5908 * @acqe_dcbx: pointer to the async dcbx completion queue entry.
da0436e9
JS
5909 *
5910 * This routine is to handle the SLI4 asynchronous dcbx event.
5911 **/
5912static void
5913lpfc_sli4_async_dcbx_evt(struct lpfc_hba *phba,
5914 struct lpfc_acqe_dcbx *acqe_dcbx)
5915{
4d9ab994 5916 phba->fc_eventTag = acqe_dcbx->event_tag;
372c187b 5917 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
5918 "0290 The SLI4 DCBX asynchronous event is not "
5919 "handled yet\n");
5920}
5921
b19a061a
JS
5922/**
5923 * lpfc_sli4_async_grp5_evt - Process the asynchronous group5 event
5924 * @phba: pointer to lpfc hba data structure.
fe614acd 5925 * @acqe_grp5: pointer to the async grp5 completion queue entry.
b19a061a
JS
5926 *
5927 * This routine is to handle the SLI4 asynchronous grp5 event. A grp5 event
5928 * is an asynchronous notified of a logical link speed change. The Port
5929 * reports the logical link speed in units of 10Mbps.
5930 **/
5931static void
5932lpfc_sli4_async_grp5_evt(struct lpfc_hba *phba,
5933 struct lpfc_acqe_grp5 *acqe_grp5)
5934{
5935 uint16_t prev_ll_spd;
5936
5937 phba->fc_eventTag = acqe_grp5->event_tag;
5938 phba->fcoe_eventtag = acqe_grp5->event_tag;
5939 prev_ll_spd = phba->sli4_hba.link_state.logical_speed;
5940 phba->sli4_hba.link_state.logical_speed =
8b68cd52 5941 (bf_get(lpfc_acqe_grp5_llink_spd, acqe_grp5)) * 10;
b19a061a
JS
5942 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5943 "2789 GRP5 Async Event: Updating logical link speed "
8b68cd52
JS
5944 "from %dMbps to %dMbps\n", prev_ll_spd,
5945 phba->sli4_hba.link_state.logical_speed);
b19a061a
JS
5946}
5947
da0436e9
JS
5948/**
5949 * lpfc_sli4_async_event_proc - Process all the pending asynchronous event
5950 * @phba: pointer to lpfc hba data structure.
5951 *
5952 * This routine is invoked by the worker thread to process all the pending
5953 * SLI4 asynchronous events.
5954 **/
5955void lpfc_sli4_async_event_proc(struct lpfc_hba *phba)
5956{
5957 struct lpfc_cq_event *cq_event;
e7dab164 5958 unsigned long iflags;
da0436e9
JS
5959
5960 /* First, declare the async event has been handled */
e7dab164 5961 spin_lock_irqsave(&phba->hbalock, iflags);
da0436e9 5962 phba->hba_flag &= ~ASYNC_EVENT;
e7dab164
JS
5963 spin_unlock_irqrestore(&phba->hbalock, iflags);
5964
da0436e9 5965 /* Now, handle all the async events */
e7dab164 5966 spin_lock_irqsave(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9 5967 while (!list_empty(&phba->sli4_hba.sp_asynce_work_queue)) {
da0436e9
JS
5968 list_remove_head(&phba->sli4_hba.sp_asynce_work_queue,
5969 cq_event, struct lpfc_cq_event, list);
e7dab164
JS
5970 spin_unlock_irqrestore(&phba->sli4_hba.asynce_list_lock,
5971 iflags);
5972
da0436e9
JS
5973 /* Process the asynchronous event */
5974 switch (bf_get(lpfc_trailer_code, &cq_event->cqe.mcqe_cmpl)) {
5975 case LPFC_TRAILER_CODE_LINK:
5976 lpfc_sli4_async_link_evt(phba,
5977 &cq_event->cqe.acqe_link);
5978 break;
5979 case LPFC_TRAILER_CODE_FCOE:
70f3c073 5980 lpfc_sli4_async_fip_evt(phba, &cq_event->cqe.acqe_fip);
da0436e9
JS
5981 break;
5982 case LPFC_TRAILER_CODE_DCBX:
5983 lpfc_sli4_async_dcbx_evt(phba,
5984 &cq_event->cqe.acqe_dcbx);
5985 break;
b19a061a
JS
5986 case LPFC_TRAILER_CODE_GRP5:
5987 lpfc_sli4_async_grp5_evt(phba,
5988 &cq_event->cqe.acqe_grp5);
5989 break;
70f3c073
JS
5990 case LPFC_TRAILER_CODE_FC:
5991 lpfc_sli4_async_fc_evt(phba, &cq_event->cqe.acqe_fc);
5992 break;
5993 case LPFC_TRAILER_CODE_SLI:
5994 lpfc_sli4_async_sli_evt(phba, &cq_event->cqe.acqe_sli);
5995 break;
da0436e9 5996 default:
372c187b
DK
5997 lpfc_printf_log(phba, KERN_ERR,
5998 LOG_TRACE_EVENT,
291c2548 5999 "1804 Invalid asynchronous event code: "
da0436e9
JS
6000 "x%x\n", bf_get(lpfc_trailer_code,
6001 &cq_event->cqe.mcqe_cmpl));
6002 break;
6003 }
e7dab164 6004
da0436e9
JS
6005 /* Free the completion event processed to the free pool */
6006 lpfc_sli4_cq_event_release(phba, cq_event);
e7dab164 6007 spin_lock_irqsave(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9 6008 }
e7dab164 6009 spin_unlock_irqrestore(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9
JS
6010}
6011
ecfd03c6
JS
6012/**
6013 * lpfc_sli4_fcf_redisc_event_proc - Process fcf table rediscovery event
6014 * @phba: pointer to lpfc hba data structure.
6015 *
6016 * This routine is invoked by the worker thread to process FCF table
6017 * rediscovery pending completion event.
6018 **/
6019void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *phba)
6020{
6021 int rc;
6022
6023 spin_lock_irq(&phba->hbalock);
6024 /* Clear FCF rediscovery timeout event */
6025 phba->fcf.fcf_flag &= ~FCF_REDISC_EVT;
6026 /* Clear driver fast failover FCF record flag */
6027 phba->fcf.failover_rec.flag = 0;
6028 /* Set state for FCF fast failover */
6029 phba->fcf.fcf_flag |= FCF_REDISC_FOV;
6030 spin_unlock_irq(&phba->hbalock);
6031
6032 /* Scan FCF table from the first entry to re-discover SAN */
0c9ab6f5 6033 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
a93ff37a 6034 "2777 Start post-quiescent FCF table scan\n");
0c9ab6f5 6035 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba, LPFC_FCOE_FCF_GET_FIRST);
ecfd03c6 6036 if (rc)
372c187b 6037 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0c9ab6f5
JS
6038 "2747 Issue FCF scan read FCF mailbox "
6039 "command failed 0x%x\n", rc);
ecfd03c6
JS
6040}
6041
da0436e9
JS
6042/**
6043 * lpfc_api_table_setup - Set up per hba pci-device group func api jump table
6044 * @phba: pointer to lpfc hba data structure.
6045 * @dev_grp: The HBA PCI-Device group number.
6046 *
6047 * This routine is invoked to set up the per HBA PCI-Device group function
6048 * API jump table entries.
6049 *
6050 * Return: 0 if success, otherwise -ENODEV
6051 **/
6052int
6053lpfc_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
6054{
6055 int rc;
6056
6057 /* Set up lpfc PCI-device group */
6058 phba->pci_dev_grp = dev_grp;
6059
6060 /* The LPFC_PCI_DEV_OC uses SLI4 */
6061 if (dev_grp == LPFC_PCI_DEV_OC)
6062 phba->sli_rev = LPFC_SLI_REV4;
6063
6064 /* Set up device INIT API function jump table */
6065 rc = lpfc_init_api_table_setup(phba, dev_grp);
6066 if (rc)
6067 return -ENODEV;
6068 /* Set up SCSI API function jump table */
6069 rc = lpfc_scsi_api_table_setup(phba, dev_grp);
6070 if (rc)
6071 return -ENODEV;
6072 /* Set up SLI API function jump table */
6073 rc = lpfc_sli_api_table_setup(phba, dev_grp);
6074 if (rc)
6075 return -ENODEV;
6076 /* Set up MBOX API function jump table */
6077 rc = lpfc_mbox_api_table_setup(phba, dev_grp);
6078 if (rc)
6079 return -ENODEV;
6080
6081 return 0;
5b75da2f
JS
6082}
6083
6084/**
3621a710 6085 * lpfc_log_intr_mode - Log the active interrupt mode
5b75da2f
JS
6086 * @phba: pointer to lpfc hba data structure.
6087 * @intr_mode: active interrupt mode adopted.
6088 *
6089 * This routine it invoked to log the currently used active interrupt mode
6090 * to the device.
3772a991
JS
6091 **/
6092static void lpfc_log_intr_mode(struct lpfc_hba *phba, uint32_t intr_mode)
5b75da2f
JS
6093{
6094 switch (intr_mode) {
6095 case 0:
6096 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
6097 "0470 Enable INTx interrupt mode.\n");
6098 break;
6099 case 1:
6100 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
6101 "0481 Enabled MSI interrupt mode.\n");
6102 break;
6103 case 2:
6104 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
6105 "0480 Enabled MSI-X interrupt mode.\n");
6106 break;
6107 default:
372c187b 6108 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5b75da2f
JS
6109 "0482 Illegal interrupt mode.\n");
6110 break;
6111 }
6112 return;
6113}
6114
5b75da2f 6115/**
3772a991 6116 * lpfc_enable_pci_dev - Enable a generic PCI device.
5b75da2f
JS
6117 * @phba: pointer to lpfc hba data structure.
6118 *
3772a991
JS
6119 * This routine is invoked to enable the PCI device that is common to all
6120 * PCI devices.
5b75da2f
JS
6121 *
6122 * Return codes
af901ca1 6123 * 0 - successful
3772a991 6124 * other values - error
5b75da2f 6125 **/
3772a991
JS
6126static int
6127lpfc_enable_pci_dev(struct lpfc_hba *phba)
5b75da2f 6128{
3772a991 6129 struct pci_dev *pdev;
5b75da2f 6130
3772a991
JS
6131 /* Obtain PCI device reference */
6132 if (!phba->pcidev)
6133 goto out_error;
6134 else
6135 pdev = phba->pcidev;
3772a991
JS
6136 /* Enable PCI device */
6137 if (pci_enable_device_mem(pdev))
6138 goto out_error;
6139 /* Request PCI resource for the device */
e0c0483c 6140 if (pci_request_mem_regions(pdev, LPFC_DRIVER_NAME))
3772a991
JS
6141 goto out_disable_device;
6142 /* Set up device as PCI master and save state for EEH */
6143 pci_set_master(pdev);
6144 pci_try_set_mwi(pdev);
6145 pci_save_state(pdev);
5b75da2f 6146
0558056c 6147 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
453193e0 6148 if (pci_is_pcie(pdev))
0558056c
JS
6149 pdev->needs_freset = 1;
6150
3772a991 6151 return 0;
5b75da2f 6152
3772a991
JS
6153out_disable_device:
6154 pci_disable_device(pdev);
6155out_error:
372c187b 6156 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
e0c0483c 6157 "1401 Failed to enable pci device\n");
3772a991 6158 return -ENODEV;
5b75da2f
JS
6159}
6160
6161/**
3772a991 6162 * lpfc_disable_pci_dev - Disable a generic PCI device.
5b75da2f
JS
6163 * @phba: pointer to lpfc hba data structure.
6164 *
3772a991
JS
6165 * This routine is invoked to disable the PCI device that is common to all
6166 * PCI devices.
5b75da2f
JS
6167 **/
6168static void
3772a991 6169lpfc_disable_pci_dev(struct lpfc_hba *phba)
5b75da2f 6170{
3772a991 6171 struct pci_dev *pdev;
5b75da2f 6172
3772a991
JS
6173 /* Obtain PCI device reference */
6174 if (!phba->pcidev)
6175 return;
6176 else
6177 pdev = phba->pcidev;
3772a991 6178 /* Release PCI resource and disable PCI device */
e0c0483c 6179 pci_release_mem_regions(pdev);
3772a991 6180 pci_disable_device(pdev);
5b75da2f
JS
6181
6182 return;
6183}
6184
e59058c4 6185/**
3772a991
JS
6186 * lpfc_reset_hba - Reset a hba
6187 * @phba: pointer to lpfc hba data structure.
e59058c4 6188 *
3772a991
JS
6189 * This routine is invoked to reset a hba device. It brings the HBA
6190 * offline, performs a board restart, and then brings the board back
6191 * online. The lpfc_offline calls lpfc_sli_hba_down which will clean up
6192 * on outstanding mailbox commands.
e59058c4 6193 **/
3772a991
JS
6194void
6195lpfc_reset_hba(struct lpfc_hba *phba)
dea3101e 6196{
3772a991
JS
6197 /* If resets are disabled then set error state and return. */
6198 if (!phba->cfg_enable_hba_reset) {
6199 phba->link_state = LPFC_HBA_ERROR;
6200 return;
6201 }
ee62021a
JS
6202 if (phba->sli.sli_flag & LPFC_SLI_ACTIVE)
6203 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
6204 else
6205 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
3772a991
JS
6206 lpfc_offline(phba);
6207 lpfc_sli_brdrestart(phba);
6208 lpfc_online(phba);
6209 lpfc_unblock_mgmt_io(phba);
6210}
dea3101e 6211
0a96e975
JS
6212/**
6213 * lpfc_sli_sriov_nr_virtfn_get - Get the number of sr-iov virtual functions
6214 * @phba: pointer to lpfc hba data structure.
6215 *
6216 * This function enables the PCI SR-IOV virtual functions to a physical
6217 * function. It invokes the PCI SR-IOV api with the @nr_vfn provided to
6218 * enable the number of virtual functions to the physical function. As
6219 * not all devices support SR-IOV, the return code from the pci_enable_sriov()
6220 * API call does not considered as an error condition for most of the device.
6221 **/
6222uint16_t
6223lpfc_sli_sriov_nr_virtfn_get(struct lpfc_hba *phba)
6224{
6225 struct pci_dev *pdev = phba->pcidev;
6226 uint16_t nr_virtfn;
6227 int pos;
6228
0a96e975
JS
6229 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6230 if (pos == 0)
6231 return 0;
6232
6233 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, &nr_virtfn);
6234 return nr_virtfn;
6235}
6236
912e3acd
JS
6237/**
6238 * lpfc_sli_probe_sriov_nr_virtfn - Enable a number of sr-iov virtual functions
6239 * @phba: pointer to lpfc hba data structure.
6240 * @nr_vfn: number of virtual functions to be enabled.
6241 *
6242 * This function enables the PCI SR-IOV virtual functions to a physical
6243 * function. It invokes the PCI SR-IOV api with the @nr_vfn provided to
6244 * enable the number of virtual functions to the physical function. As
6245 * not all devices support SR-IOV, the return code from the pci_enable_sriov()
6246 * API call does not considered as an error condition for most of the device.
6247 **/
6248int
6249lpfc_sli_probe_sriov_nr_virtfn(struct lpfc_hba *phba, int nr_vfn)
6250{
6251 struct pci_dev *pdev = phba->pcidev;
0a96e975 6252 uint16_t max_nr_vfn;
912e3acd
JS
6253 int rc;
6254
0a96e975
JS
6255 max_nr_vfn = lpfc_sli_sriov_nr_virtfn_get(phba);
6256 if (nr_vfn > max_nr_vfn) {
372c187b 6257 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a96e975
JS
6258 "3057 Requested vfs (%d) greater than "
6259 "supported vfs (%d)", nr_vfn, max_nr_vfn);
6260 return -EINVAL;
6261 }
6262
912e3acd
JS
6263 rc = pci_enable_sriov(pdev, nr_vfn);
6264 if (rc) {
6265 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6266 "2806 Failed to enable sriov on this device "
6267 "with vfn number nr_vf:%d, rc:%d\n",
6268 nr_vfn, rc);
6269 } else
6270 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6271 "2807 Successful enable sriov on this device "
6272 "with vfn number nr_vf:%d\n", nr_vfn);
6273 return rc;
6274}
6275
3772a991 6276/**
895427bd 6277 * lpfc_setup_driver_resource_phase1 - Phase1 etup driver internal resources.
3772a991
JS
6278 * @phba: pointer to lpfc hba data structure.
6279 *
895427bd
JS
6280 * This routine is invoked to set up the driver internal resources before the
6281 * device specific resource setup to support the HBA device it attached to.
3772a991
JS
6282 *
6283 * Return codes
895427bd
JS
6284 * 0 - successful
6285 * other values - error
3772a991
JS
6286 **/
6287static int
895427bd 6288lpfc_setup_driver_resource_phase1(struct lpfc_hba *phba)
3772a991 6289{
895427bd 6290 struct lpfc_sli *psli = &phba->sli;
dea3101e 6291
2e0fef85 6292 /*
895427bd 6293 * Driver resources common to all SLI revisions
2e0fef85 6294 */
895427bd 6295 atomic_set(&phba->fast_event_count, 0);
372c187b
DK
6296 atomic_set(&phba->dbg_log_idx, 0);
6297 atomic_set(&phba->dbg_log_cnt, 0);
6298 atomic_set(&phba->dbg_log_dmping, 0);
895427bd 6299 spin_lock_init(&phba->hbalock);
dea3101e 6300
895427bd
JS
6301 /* Initialize ndlp management spinlock */
6302 spin_lock_init(&phba->ndlp_lock);
6303
523128e5
JS
6304 /* Initialize port_list spinlock */
6305 spin_lock_init(&phba->port_list_lock);
895427bd 6306 INIT_LIST_HEAD(&phba->port_list);
523128e5 6307
895427bd
JS
6308 INIT_LIST_HEAD(&phba->work_list);
6309 init_waitqueue_head(&phba->wait_4_mlo_m_q);
6310
6311 /* Initialize the wait queue head for the kernel thread */
6312 init_waitqueue_head(&phba->work_waitq);
6313
6314 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
f358dd0c 6315 "1403 Protocols supported %s %s %s\n",
895427bd
JS
6316 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) ?
6317 "SCSI" : " "),
6318 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) ?
f358dd0c
JS
6319 "NVME" : " "),
6320 (phba->nvmet_support ? "NVMET" : " "));
895427bd 6321
0794d601
JS
6322 /* Initialize the IO buffer list used by driver for SLI3 SCSI */
6323 spin_lock_init(&phba->scsi_buf_list_get_lock);
6324 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_get);
6325 spin_lock_init(&phba->scsi_buf_list_put_lock);
6326 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_put);
895427bd
JS
6327
6328 /* Initialize the fabric iocb list */
6329 INIT_LIST_HEAD(&phba->fabric_iocb_list);
6330
6331 /* Initialize list to save ELS buffers */
6332 INIT_LIST_HEAD(&phba->elsbuf);
6333
6334 /* Initialize FCF connection rec list */
6335 INIT_LIST_HEAD(&phba->fcf_conn_rec_list);
6336
6337 /* Initialize OAS configuration list */
6338 spin_lock_init(&phba->devicelock);
6339 INIT_LIST_HEAD(&phba->luns);
858c9f6c 6340
3772a991 6341 /* MBOX heartbeat timer */
f22eb4d3 6342 timer_setup(&psli->mbox_tmo, lpfc_mbox_timeout, 0);
3772a991 6343 /* Fabric block timer */
f22eb4d3 6344 timer_setup(&phba->fabric_block_timer, lpfc_fabric_block_timeout, 0);
3772a991 6345 /* EA polling mode timer */
f22eb4d3 6346 timer_setup(&phba->eratt_poll, lpfc_poll_eratt, 0);
895427bd 6347 /* Heartbeat timer */
f22eb4d3 6348 timer_setup(&phba->hb_tmofunc, lpfc_hb_timeout, 0);
895427bd 6349
32517fc0
JS
6350 INIT_DELAYED_WORK(&phba->eq_delay_work, lpfc_hb_eq_delay_work);
6351
317aeb83
DK
6352 INIT_DELAYED_WORK(&phba->idle_stat_delay_work,
6353 lpfc_idle_stat_delay_work);
6354
895427bd
JS
6355 return 0;
6356}
6357
6358/**
6359 * lpfc_sli_driver_resource_setup - Setup driver internal resources for SLI3 dev
6360 * @phba: pointer to lpfc hba data structure.
6361 *
6362 * This routine is invoked to set up the driver internal resources specific to
6363 * support the SLI-3 HBA device it attached to.
6364 *
6365 * Return codes
6366 * 0 - successful
6367 * other values - error
6368 **/
6369static int
6370lpfc_sli_driver_resource_setup(struct lpfc_hba *phba)
6371{
0794d601 6372 int rc, entry_sz;
895427bd
JS
6373
6374 /*
6375 * Initialize timers used by driver
6376 */
6377
6378 /* FCP polling mode timer */
f22eb4d3 6379 timer_setup(&phba->fcp_poll_timer, lpfc_poll_timeout, 0);
dea3101e 6380
3772a991
JS
6381 /* Host attention work mask setup */
6382 phba->work_ha_mask = (HA_ERATT | HA_MBATT | HA_LATT);
6383 phba->work_ha_mask |= (HA_RXMASK << (LPFC_ELS_RING * 4));
dea3101e 6384
3772a991
JS
6385 /* Get all the module params for configuring this host */
6386 lpfc_get_cfgparam(phba);
895427bd
JS
6387 /* Set up phase-1 common device driver resources */
6388
6389 rc = lpfc_setup_driver_resource_phase1(phba);
6390 if (rc)
6391 return -ENODEV;
6392
49198b37
JS
6393 if (phba->pcidev->device == PCI_DEVICE_ID_HORNET) {
6394 phba->menlo_flag |= HBA_MENLO_SUPPORT;
6395 /* check for menlo minimum sg count */
6396 if (phba->cfg_sg_seg_cnt < LPFC_DEFAULT_MENLO_SG_SEG_CNT)
6397 phba->cfg_sg_seg_cnt = LPFC_DEFAULT_MENLO_SG_SEG_CNT;
6398 }
6399
895427bd 6400 if (!phba->sli.sli3_ring)
6396bb22
KC
6401 phba->sli.sli3_ring = kcalloc(LPFC_SLI3_MAX_RING,
6402 sizeof(struct lpfc_sli_ring),
6403 GFP_KERNEL);
895427bd 6404 if (!phba->sli.sli3_ring)
2a76a283
JS
6405 return -ENOMEM;
6406
dea3101e 6407 /*
96f7077f 6408 * Since lpfc_sg_seg_cnt is module parameter, the sg_dma_buf_size
3772a991 6409 * used to create the sg_dma_buf_pool must be dynamically calculated.
dea3101e 6410 */
3772a991 6411
0794d601
JS
6412 if (phba->sli_rev == LPFC_SLI_REV4)
6413 entry_sz = sizeof(struct sli4_sge);
6414 else
6415 entry_sz = sizeof(struct ulp_bde64);
6416
96f7077f 6417 /* There are going to be 2 reserved BDEs: 1 FCP cmnd + 1 FCP rsp */
3772a991 6418 if (phba->cfg_enable_bg) {
96f7077f
JS
6419 /*
6420 * The scsi_buf for a T10-DIF I/O will hold the FCP cmnd,
6421 * the FCP rsp, and a BDE for each. Sice we have no control
6422 * over how many protection data segments the SCSI Layer
6423 * will hand us (ie: there could be one for every block
6424 * in the IO), we just allocate enough BDEs to accomidate
6425 * our max amount and we need to limit lpfc_sg_seg_cnt to
6426 * minimize the risk of running out.
6427 */
6428 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6429 sizeof(struct fcp_rsp) +
0794d601 6430 (LPFC_MAX_SG_SEG_CNT * entry_sz);
96f7077f
JS
6431
6432 if (phba->cfg_sg_seg_cnt > LPFC_MAX_SG_SEG_CNT_DIF)
6433 phba->cfg_sg_seg_cnt = LPFC_MAX_SG_SEG_CNT_DIF;
6434
6435 /* Total BDEs in BPL for scsi_sg_list and scsi_sg_prot_list */
6436 phba->cfg_total_seg_cnt = LPFC_MAX_SG_SEG_CNT;
6437 } else {
6438 /*
6439 * The scsi_buf for a regular I/O will hold the FCP cmnd,
6440 * the FCP rsp, a BDE for each, and a BDE for up to
6441 * cfg_sg_seg_cnt data segments.
6442 */
6443 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6444 sizeof(struct fcp_rsp) +
0794d601 6445 ((phba->cfg_sg_seg_cnt + 2) * entry_sz);
96f7077f
JS
6446
6447 /* Total BDEs in BPL for scsi_sg_list */
6448 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + 2;
901a920f 6449 }
dea3101e 6450
96f7077f 6451 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
c90b4480 6452 "9088 INIT sg_tablesize:%d dmabuf_size:%d total_bde:%d\n",
96f7077f
JS
6453 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
6454 phba->cfg_total_seg_cnt);
dea3101e 6455
3772a991
JS
6456 phba->max_vpi = LPFC_MAX_VPI;
6457 /* This will be set to correct value after config_port mbox */
6458 phba->max_vports = 0;
dea3101e 6459
3772a991
JS
6460 /*
6461 * Initialize the SLI Layer to run with lpfc HBAs.
6462 */
6463 lpfc_sli_setup(phba);
895427bd 6464 lpfc_sli_queue_init(phba);
ed957684 6465
3772a991
JS
6466 /* Allocate device driver memory */
6467 if (lpfc_mem_alloc(phba, BPL_ALIGN_SZ))
6468 return -ENOMEM;
51ef4c26 6469
d79c9e9d
JS
6470 phba->lpfc_sg_dma_buf_pool =
6471 dma_pool_create("lpfc_sg_dma_buf_pool",
6472 &phba->pcidev->dev, phba->cfg_sg_dma_buf_size,
6473 BPL_ALIGN_SZ, 0);
6474
6475 if (!phba->lpfc_sg_dma_buf_pool)
6476 goto fail_free_mem;
6477
6478 phba->lpfc_cmd_rsp_buf_pool =
6479 dma_pool_create("lpfc_cmd_rsp_buf_pool",
6480 &phba->pcidev->dev,
6481 sizeof(struct fcp_cmnd) +
6482 sizeof(struct fcp_rsp),
6483 BPL_ALIGN_SZ, 0);
6484
6485 if (!phba->lpfc_cmd_rsp_buf_pool)
6486 goto fail_free_dma_buf_pool;
6487
912e3acd
JS
6488 /*
6489 * Enable sr-iov virtual functions if supported and configured
6490 * through the module parameter.
6491 */
6492 if (phba->cfg_sriov_nr_virtfn > 0) {
6493 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
6494 phba->cfg_sriov_nr_virtfn);
6495 if (rc) {
6496 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6497 "2808 Requested number of SR-IOV "
6498 "virtual functions (%d) is not "
6499 "supported\n",
6500 phba->cfg_sriov_nr_virtfn);
6501 phba->cfg_sriov_nr_virtfn = 0;
6502 }
6503 }
6504
3772a991 6505 return 0;
d79c9e9d
JS
6506
6507fail_free_dma_buf_pool:
6508 dma_pool_destroy(phba->lpfc_sg_dma_buf_pool);
6509 phba->lpfc_sg_dma_buf_pool = NULL;
6510fail_free_mem:
6511 lpfc_mem_free(phba);
6512 return -ENOMEM;
3772a991 6513}
ed957684 6514
3772a991
JS
6515/**
6516 * lpfc_sli_driver_resource_unset - Unset drvr internal resources for SLI3 dev
6517 * @phba: pointer to lpfc hba data structure.
6518 *
6519 * This routine is invoked to unset the driver internal resources set up
6520 * specific for supporting the SLI-3 HBA device it attached to.
6521 **/
6522static void
6523lpfc_sli_driver_resource_unset(struct lpfc_hba *phba)
6524{
6525 /* Free device driver memory allocated */
6526 lpfc_mem_free_all(phba);
3163f725 6527
3772a991
JS
6528 return;
6529}
dea3101e 6530
3772a991 6531/**
da0436e9 6532 * lpfc_sli4_driver_resource_setup - Setup drvr internal resources for SLI4 dev
3772a991
JS
6533 * @phba: pointer to lpfc hba data structure.
6534 *
da0436e9
JS
6535 * This routine is invoked to set up the driver internal resources specific to
6536 * support the SLI-4 HBA device it attached to.
3772a991
JS
6537 *
6538 * Return codes
af901ca1 6539 * 0 - successful
da0436e9 6540 * other values - error
3772a991
JS
6541 **/
6542static int
da0436e9 6543lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba)
3772a991 6544{
28baac74 6545 LPFC_MBOXQ_t *mboxq;
f358dd0c 6546 MAILBOX_t *mb;
895427bd 6547 int rc, i, max_buf_size;
28baac74
JS
6548 uint8_t pn_page[LPFC_MAX_SUPPORTED_PAGES] = {0};
6549 struct lpfc_mqe *mqe;
09294d46 6550 int longs;
81e6a637 6551 int extra;
f358dd0c 6552 uint64_t wwn;
b92dc72d
JS
6553 u32 if_type;
6554 u32 if_fam;
da0436e9 6555
895427bd 6556 phba->sli4_hba.num_present_cpu = lpfc_present_cpu;
eede4970 6557 phba->sli4_hba.num_possible_cpu = cpumask_last(cpu_possible_mask) + 1;
895427bd
JS
6558 phba->sli4_hba.curr_disp_cpu = 0;
6559
716d3bc5
JS
6560 /* Get all the module params for configuring this host */
6561 lpfc_get_cfgparam(phba);
6562
895427bd
JS
6563 /* Set up phase-1 common device driver resources */
6564 rc = lpfc_setup_driver_resource_phase1(phba);
6565 if (rc)
6566 return -ENODEV;
6567
da0436e9
JS
6568 /* Before proceed, wait for POST done and device ready */
6569 rc = lpfc_sli4_post_status_check(phba);
6570 if (rc)
6571 return -ENODEV;
6572
3cee98db
JS
6573 /* Allocate all driver workqueues here */
6574
6575 /* The lpfc_wq workqueue for deferred irq use */
6576 phba->wq = alloc_workqueue("lpfc_wq", WQ_MEM_RECLAIM, 0);
6577
3772a991 6578 /*
da0436e9 6579 * Initialize timers used by driver
3772a991 6580 */
3772a991 6581
f22eb4d3 6582 timer_setup(&phba->rrq_tmr, lpfc_rrq_timeout, 0);
3772a991 6583
ecfd03c6 6584 /* FCF rediscover timer */
f22eb4d3 6585 timer_setup(&phba->fcf.redisc_wait, lpfc_sli4_fcf_redisc_wait_tmo, 0);
ecfd03c6 6586
7ad20aa9
JS
6587 /*
6588 * Control structure for handling external multi-buffer mailbox
6589 * command pass-through.
6590 */
6591 memset((uint8_t *)&phba->mbox_ext_buf_ctx, 0,
6592 sizeof(struct lpfc_mbox_ext_buf_ctx));
6593 INIT_LIST_HEAD(&phba->mbox_ext_buf_ctx.ext_dmabuf_list);
6594
da0436e9 6595 phba->max_vpi = LPFC_MAX_VPI;
67d12733 6596
da0436e9
JS
6597 /* This will be set to correct value after the read_config mbox */
6598 phba->max_vports = 0;
3772a991 6599
da0436e9
JS
6600 /* Program the default value of vlan_id and fc_map */
6601 phba->valid_vlan = 0;
6602 phba->fc_map[0] = LPFC_FCOE_FCF_MAP0;
6603 phba->fc_map[1] = LPFC_FCOE_FCF_MAP1;
6604 phba->fc_map[2] = LPFC_FCOE_FCF_MAP2;
3772a991 6605
2a76a283
JS
6606 /*
6607 * For SLI4, instead of using ring 0 (LPFC_FCP_RING) for FCP commands
895427bd
JS
6608 * we will associate a new ring, for each EQ/CQ/WQ tuple.
6609 * The WQ create will allocate the ring.
2a76a283 6610 */
09294d46 6611
da0436e9 6612 /* Initialize buffer queue management fields */
895427bd 6613 INIT_LIST_HEAD(&phba->hbqs[LPFC_ELS_HBQ].hbq_buffer_list);
da0436e9
JS
6614 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_sli4_rb_alloc;
6615 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_sli4_rb_free;
3772a991 6616
da0436e9
JS
6617 /*
6618 * Initialize the SLI Layer to run with lpfc SLI4 HBAs.
6619 */
c00f62e6
JS
6620 /* Initialize the Abort buffer list used by driver */
6621 spin_lock_init(&phba->sli4_hba.abts_io_buf_list_lock);
6622 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_io_buf_list);
895427bd
JS
6623
6624 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
6625 /* Initialize the Abort nvme buffer list used by driver */
5e5b511d 6626 spin_lock_init(&phba->sli4_hba.abts_nvmet_buf_list_lock);
86c67379 6627 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
a8cf5dfe 6628 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_io_wait_list);
79d8c4ce
JS
6629 spin_lock_init(&phba->sli4_hba.t_active_list_lock);
6630 INIT_LIST_HEAD(&phba->sli4_hba.t_active_ctx_list);
895427bd
JS
6631 }
6632
da0436e9 6633 /* This abort list used by worker thread */
895427bd 6634 spin_lock_init(&phba->sli4_hba.sgl_list_lock);
a8cf5dfe 6635 spin_lock_init(&phba->sli4_hba.nvmet_io_wait_lock);
e7dab164
JS
6636 spin_lock_init(&phba->sli4_hba.asynce_list_lock);
6637 spin_lock_init(&phba->sli4_hba.els_xri_abrt_list_lock);
3772a991 6638
da0436e9 6639 /*
6d368e53 6640 * Initialize driver internal slow-path work queues
da0436e9 6641 */
3772a991 6642
da0436e9
JS
6643 /* Driver internel slow-path CQ Event pool */
6644 INIT_LIST_HEAD(&phba->sli4_hba.sp_cqe_event_pool);
6645 /* Response IOCB work queue list */
45ed1190 6646 INIT_LIST_HEAD(&phba->sli4_hba.sp_queue_event);
da0436e9
JS
6647 /* Asynchronous event CQ Event work queue list */
6648 INIT_LIST_HEAD(&phba->sli4_hba.sp_asynce_work_queue);
da0436e9
JS
6649 /* Slow-path XRI aborted CQ Event work queue list */
6650 INIT_LIST_HEAD(&phba->sli4_hba.sp_els_xri_aborted_work_queue);
6651 /* Receive queue CQ Event work queue list */
6652 INIT_LIST_HEAD(&phba->sli4_hba.sp_unsol_work_queue);
6653
6d368e53
JS
6654 /* Initialize extent block lists. */
6655 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_blk_list);
6656 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_xri_blk_list);
6657 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_vfi_blk_list);
6658 INIT_LIST_HEAD(&phba->lpfc_vpi_blk_list);
6659
d1f525aa
JS
6660 /* Initialize mboxq lists. If the early init routines fail
6661 * these lists need to be correctly initialized.
6662 */
6663 INIT_LIST_HEAD(&phba->sli.mboxq);
6664 INIT_LIST_HEAD(&phba->sli.mboxq_cmpl);
6665
448193b5
JS
6666 /* initialize optic_state to 0xFF */
6667 phba->sli4_hba.lnk_info.optic_state = 0xff;
6668
da0436e9
JS
6669 /* Allocate device driver memory */
6670 rc = lpfc_mem_alloc(phba, SGL_ALIGN_SZ);
6671 if (rc)
6672 return -ENOMEM;
6673
2fcee4bf 6674 /* IF Type 2 ports get initialized now. */
27d6ac0a 6675 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) >=
2fcee4bf
JS
6676 LPFC_SLI_INTF_IF_TYPE_2) {
6677 rc = lpfc_pci_function_reset(phba);
895427bd
JS
6678 if (unlikely(rc)) {
6679 rc = -ENODEV;
6680 goto out_free_mem;
6681 }
946727dc 6682 phba->temp_sensor_support = 1;
2fcee4bf
JS
6683 }
6684
da0436e9
JS
6685 /* Create the bootstrap mailbox command */
6686 rc = lpfc_create_bootstrap_mbox(phba);
6687 if (unlikely(rc))
6688 goto out_free_mem;
6689
6690 /* Set up the host's endian order with the device. */
6691 rc = lpfc_setup_endian_order(phba);
6692 if (unlikely(rc))
6693 goto out_free_bsmbx;
6694
6695 /* Set up the hba's configuration parameters. */
6696 rc = lpfc_sli4_read_config(phba);
cff261f6
JS
6697 if (unlikely(rc))
6698 goto out_free_bsmbx;
6699 rc = lpfc_mem_alloc_active_rrq_pool_s4(phba);
da0436e9
JS
6700 if (unlikely(rc))
6701 goto out_free_bsmbx;
6702
2fcee4bf
JS
6703 /* IF Type 0 ports get initialized now. */
6704 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
6705 LPFC_SLI_INTF_IF_TYPE_0) {
6706 rc = lpfc_pci_function_reset(phba);
6707 if (unlikely(rc))
6708 goto out_free_bsmbx;
6709 }
da0436e9 6710
cb5172ea
JS
6711 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
6712 GFP_KERNEL);
6713 if (!mboxq) {
6714 rc = -ENOMEM;
6715 goto out_free_bsmbx;
6716 }
6717
f358dd0c 6718 /* Check for NVMET being configured */
895427bd 6719 phba->nvmet_support = 0;
f358dd0c
JS
6720 if (lpfc_enable_nvmet_cnt) {
6721
6722 /* First get WWN of HBA instance */
6723 lpfc_read_nv(phba, mboxq);
6724 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
6725 if (rc != MBX_SUCCESS) {
372c187b
DK
6726 lpfc_printf_log(phba, KERN_ERR,
6727 LOG_TRACE_EVENT,
f358dd0c
JS
6728 "6016 Mailbox failed , mbxCmd x%x "
6729 "READ_NV, mbxStatus x%x\n",
6730 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
6731 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
d1f525aa 6732 mempool_free(mboxq, phba->mbox_mem_pool);
f358dd0c
JS
6733 rc = -EIO;
6734 goto out_free_bsmbx;
6735 }
6736 mb = &mboxq->u.mb;
6737 memcpy(&wwn, (char *)mb->un.varRDnvp.nodename,
6738 sizeof(uint64_t));
6739 wwn = cpu_to_be64(wwn);
6740 phba->sli4_hba.wwnn.u.name = wwn;
6741 memcpy(&wwn, (char *)mb->un.varRDnvp.portname,
6742 sizeof(uint64_t));
6743 /* wwn is WWPN of HBA instance */
6744 wwn = cpu_to_be64(wwn);
6745 phba->sli4_hba.wwpn.u.name = wwn;
6746
6747 /* Check to see if it matches any module parameter */
6748 for (i = 0; i < lpfc_enable_nvmet_cnt; i++) {
6749 if (wwn == lpfc_enable_nvmet[i]) {
7d708033 6750#if (IS_ENABLED(CONFIG_NVME_TARGET_FC))
3c603be9
JS
6751 if (lpfc_nvmet_mem_alloc(phba))
6752 break;
6753
6754 phba->nvmet_support = 1; /* a match */
6755
372c187b
DK
6756 lpfc_printf_log(phba, KERN_ERR,
6757 LOG_TRACE_EVENT,
f358dd0c
JS
6758 "6017 NVME Target %016llx\n",
6759 wwn);
7d708033 6760#else
372c187b
DK
6761 lpfc_printf_log(phba, KERN_ERR,
6762 LOG_TRACE_EVENT,
7d708033
JS
6763 "6021 Can't enable NVME Target."
6764 " NVME_TARGET_FC infrastructure"
6765 " is not in kernel\n");
6766#endif
c490850a
JS
6767 /* Not supported for NVMET */
6768 phba->cfg_xri_rebalancing = 0;
3048e3e8
DK
6769 if (phba->irq_chann_mode == NHT_MODE) {
6770 phba->cfg_irq_chann =
6771 phba->sli4_hba.num_present_cpu;
6772 phba->cfg_hdw_queue =
6773 phba->sli4_hba.num_present_cpu;
6774 phba->irq_chann_mode = NORMAL_MODE;
6775 }
3c603be9 6776 break;
f358dd0c
JS
6777 }
6778 }
6779 }
895427bd
JS
6780
6781 lpfc_nvme_mod_param_dep(phba);
6782
fedd3b7b 6783 /* Get the Supported Pages if PORT_CAPABILITIES is supported by port. */
cb5172ea
JS
6784 lpfc_supported_pages(mboxq);
6785 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
fedd3b7b
JS
6786 if (!rc) {
6787 mqe = &mboxq->u.mqe;
6788 memcpy(&pn_page[0], ((uint8_t *)&mqe->un.supp_pages.word3),
6789 LPFC_MAX_SUPPORTED_PAGES);
6790 for (i = 0; i < LPFC_MAX_SUPPORTED_PAGES; i++) {
6791 switch (pn_page[i]) {
6792 case LPFC_SLI4_PARAMETERS:
6793 phba->sli4_hba.pc_sli4_params.supported = 1;
6794 break;
6795 default:
6796 break;
6797 }
6798 }
6799 /* Read the port's SLI4 Parameters capabilities if supported. */
6800 if (phba->sli4_hba.pc_sli4_params.supported)
6801 rc = lpfc_pc_sli4_params_get(phba, mboxq);
6802 if (rc) {
6803 mempool_free(mboxq, phba->mbox_mem_pool);
6804 rc = -EIO;
6805 goto out_free_bsmbx;
cb5172ea
JS
6806 }
6807 }
65791f1f 6808
fedd3b7b
JS
6809 /*
6810 * Get sli4 parameters that override parameters from Port capabilities.
6d368e53
JS
6811 * If this call fails, it isn't critical unless the SLI4 parameters come
6812 * back in conflict.
fedd3b7b 6813 */
6d368e53
JS
6814 rc = lpfc_get_sli4_parameters(phba, mboxq);
6815 if (rc) {
b92dc72d
JS
6816 if_type = bf_get(lpfc_sli_intf_if_type,
6817 &phba->sli4_hba.sli_intf);
6818 if_fam = bf_get(lpfc_sli_intf_sli_family,
6819 &phba->sli4_hba.sli_intf);
6d368e53
JS
6820 if (phba->sli4_hba.extents_in_use &&
6821 phba->sli4_hba.rpi_hdrs_in_use) {
372c187b
DK
6822 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
6823 "2999 Unsupported SLI4 Parameters "
6824 "Extents and RPI headers enabled.\n");
b92dc72d
JS
6825 if (if_type == LPFC_SLI_INTF_IF_TYPE_0 &&
6826 if_fam == LPFC_SLI_INTF_FAMILY_BE2) {
6827 mempool_free(mboxq, phba->mbox_mem_pool);
6828 rc = -EIO;
6829 goto out_free_bsmbx;
6830 }
6831 }
6832 if (!(if_type == LPFC_SLI_INTF_IF_TYPE_0 &&
6833 if_fam == LPFC_SLI_INTF_FAMILY_BE2)) {
6834 mempool_free(mboxq, phba->mbox_mem_pool);
6835 rc = -EIO;
6836 goto out_free_bsmbx;
6d368e53
JS
6837 }
6838 }
895427bd 6839
d79c9e9d
JS
6840 /*
6841 * 1 for cmd, 1 for rsp, NVME adds an extra one
6842 * for boundary conditions in its max_sgl_segment template.
6843 */
6844 extra = 2;
6845 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
6846 extra++;
6847
6848 /*
6849 * It doesn't matter what family our adapter is in, we are
6850 * limited to 2 Pages, 512 SGEs, for our SGL.
6851 * There are going to be 2 reserved SGEs: 1 FCP cmnd + 1 FCP rsp
6852 */
6853 max_buf_size = (2 * SLI4_PAGE_SIZE);
6854
6855 /*
6856 * Since lpfc_sg_seg_cnt is module param, the sg_dma_buf_size
6857 * used to create the sg_dma_buf_pool must be calculated.
6858 */
6859 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED) {
6860 /* Both cfg_enable_bg and cfg_external_dif code paths */
6861
6862 /*
6863 * The scsi_buf for a T10-DIF I/O holds the FCP cmnd,
6864 * the FCP rsp, and a SGE. Sice we have no control
6865 * over how many protection segments the SCSI Layer
6866 * will hand us (ie: there could be one for every block
6867 * in the IO), just allocate enough SGEs to accomidate
6868 * our max amount and we need to limit lpfc_sg_seg_cnt
6869 * to minimize the risk of running out.
6870 */
6871 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6872 sizeof(struct fcp_rsp) + max_buf_size;
6873
6874 /* Total SGEs for scsi_sg_list and scsi_sg_prot_list */
6875 phba->cfg_total_seg_cnt = LPFC_MAX_SGL_SEG_CNT;
6876
6877 /*
6878 * If supporting DIF, reduce the seg count for scsi to
6879 * allow room for the DIF sges.
6880 */
6881 if (phba->cfg_enable_bg &&
6882 phba->cfg_sg_seg_cnt > LPFC_MAX_BG_SLI4_SEG_CNT_DIF)
6883 phba->cfg_scsi_seg_cnt = LPFC_MAX_BG_SLI4_SEG_CNT_DIF;
6884 else
6885 phba->cfg_scsi_seg_cnt = phba->cfg_sg_seg_cnt;
6886
6887 } else {
6888 /*
6889 * The scsi_buf for a regular I/O holds the FCP cmnd,
6890 * the FCP rsp, a SGE for each, and a SGE for up to
6891 * cfg_sg_seg_cnt data segments.
6892 */
6893 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6894 sizeof(struct fcp_rsp) +
6895 ((phba->cfg_sg_seg_cnt + extra) *
6896 sizeof(struct sli4_sge));
6897
6898 /* Total SGEs for scsi_sg_list */
6899 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + extra;
6900 phba->cfg_scsi_seg_cnt = phba->cfg_sg_seg_cnt;
6901
6902 /*
6903 * NOTE: if (phba->cfg_sg_seg_cnt + extra) <= 256 we only
6904 * need to post 1 page for the SGL.
6905 */
6906 }
6907
6908 if (phba->cfg_xpsgl && !phba->nvmet_support)
6909 phba->cfg_sg_dma_buf_size = LPFC_DEFAULT_XPSGL_SIZE;
6910 else if (phba->cfg_sg_dma_buf_size <= LPFC_MIN_SG_SLI4_BUF_SZ)
6911 phba->cfg_sg_dma_buf_size = LPFC_MIN_SG_SLI4_BUF_SZ;
6912 else
6913 phba->cfg_sg_dma_buf_size =
6914 SLI4_PAGE_ALIGN(phba->cfg_sg_dma_buf_size);
6915
6916 phba->border_sge_num = phba->cfg_sg_dma_buf_size /
6917 sizeof(struct sli4_sge);
6918
6919 /* Limit to LPFC_MAX_NVME_SEG_CNT for NVME. */
6920 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
6921 if (phba->cfg_sg_seg_cnt > LPFC_MAX_NVME_SEG_CNT) {
6922 lpfc_printf_log(phba, KERN_INFO, LOG_NVME | LOG_INIT,
6923 "6300 Reducing NVME sg segment "
6924 "cnt to %d\n",
6925 LPFC_MAX_NVME_SEG_CNT);
6926 phba->cfg_nvme_seg_cnt = LPFC_MAX_NVME_SEG_CNT;
6927 } else
6928 phba->cfg_nvme_seg_cnt = phba->cfg_sg_seg_cnt;
6929 }
6930
d79c9e9d
JS
6931 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
6932 "9087 sg_seg_cnt:%d dmabuf_size:%d "
6933 "total:%d scsi:%d nvme:%d\n",
6934 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
6935 phba->cfg_total_seg_cnt, phba->cfg_scsi_seg_cnt,
6936 phba->cfg_nvme_seg_cnt);
6937
6938 if (phba->cfg_sg_dma_buf_size < SLI4_PAGE_SIZE)
6939 i = phba->cfg_sg_dma_buf_size;
6940 else
6941 i = SLI4_PAGE_SIZE;
6942
6943 phba->lpfc_sg_dma_buf_pool =
6944 dma_pool_create("lpfc_sg_dma_buf_pool",
6945 &phba->pcidev->dev,
6946 phba->cfg_sg_dma_buf_size,
6947 i, 0);
6948 if (!phba->lpfc_sg_dma_buf_pool)
6949 goto out_free_bsmbx;
6950
6951 phba->lpfc_cmd_rsp_buf_pool =
6952 dma_pool_create("lpfc_cmd_rsp_buf_pool",
6953 &phba->pcidev->dev,
6954 sizeof(struct fcp_cmnd) +
6955 sizeof(struct fcp_rsp),
6956 i, 0);
6957 if (!phba->lpfc_cmd_rsp_buf_pool)
6958 goto out_free_sg_dma_buf;
6959
cb5172ea 6960 mempool_free(mboxq, phba->mbox_mem_pool);
1ba981fd
JS
6961
6962 /* Verify OAS is supported */
6963 lpfc_sli4_oas_verify(phba);
1ba981fd 6964
d2cc9bcd
JS
6965 /* Verify RAS support on adapter */
6966 lpfc_sli4_ras_init(phba);
6967
5350d872
JS
6968 /* Verify all the SLI4 queues */
6969 rc = lpfc_sli4_queue_verify(phba);
da0436e9 6970 if (rc)
d79c9e9d 6971 goto out_free_cmd_rsp_buf;
da0436e9
JS
6972
6973 /* Create driver internal CQE event pool */
6974 rc = lpfc_sli4_cq_event_pool_create(phba);
6975 if (rc)
d79c9e9d 6976 goto out_free_cmd_rsp_buf;
da0436e9 6977
8a9d2e80
JS
6978 /* Initialize sgl lists per host */
6979 lpfc_init_sgl_list(phba);
6980
6981 /* Allocate and initialize active sgl array */
da0436e9
JS
6982 rc = lpfc_init_active_sgl_array(phba);
6983 if (rc) {
372c187b 6984 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 6985 "1430 Failed to initialize sgl list.\n");
8a9d2e80 6986 goto out_destroy_cq_event_pool;
da0436e9 6987 }
da0436e9
JS
6988 rc = lpfc_sli4_init_rpi_hdrs(phba);
6989 if (rc) {
372c187b 6990 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
6991 "1432 Failed to initialize rpi headers.\n");
6992 goto out_free_active_sgl;
6993 }
6994
a93ff37a 6995 /* Allocate eligible FCF bmask memory for FCF roundrobin failover */
0c9ab6f5 6996 longs = (LPFC_SLI4_FCF_TBL_INDX_MAX + BITS_PER_LONG - 1)/BITS_PER_LONG;
6396bb22 6997 phba->fcf.fcf_rr_bmask = kcalloc(longs, sizeof(unsigned long),
0c9ab6f5
JS
6998 GFP_KERNEL);
6999 if (!phba->fcf.fcf_rr_bmask) {
372c187b 7000 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0c9ab6f5
JS
7001 "2759 Failed allocate memory for FCF round "
7002 "robin failover bmask\n");
0558056c 7003 rc = -ENOMEM;
0c9ab6f5
JS
7004 goto out_remove_rpi_hdrs;
7005 }
7006
6a828b0f 7007 phba->sli4_hba.hba_eq_hdl = kcalloc(phba->cfg_irq_chann,
cdb42bec
JS
7008 sizeof(struct lpfc_hba_eq_hdl),
7009 GFP_KERNEL);
895427bd 7010 if (!phba->sli4_hba.hba_eq_hdl) {
372c187b 7011 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
67d12733
JS
7012 "2572 Failed allocate memory for "
7013 "fast-path per-EQ handle array\n");
7014 rc = -ENOMEM;
7015 goto out_free_fcf_rr_bmask;
da0436e9
JS
7016 }
7017
222e9239 7018 phba->sli4_hba.cpu_map = kcalloc(phba->sli4_hba.num_possible_cpu,
895427bd
JS
7019 sizeof(struct lpfc_vector_map_info),
7020 GFP_KERNEL);
7bb03bbf 7021 if (!phba->sli4_hba.cpu_map) {
372c187b 7022 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
7bb03bbf
JS
7023 "3327 Failed allocate memory for msi-x "
7024 "interrupt vector mapping\n");
7025 rc = -ENOMEM;
895427bd 7026 goto out_free_hba_eq_hdl;
7bb03bbf 7027 }
b246de17 7028
32517fc0
JS
7029 phba->sli4_hba.eq_info = alloc_percpu(struct lpfc_eq_intr_info);
7030 if (!phba->sli4_hba.eq_info) {
372c187b 7031 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
32517fc0
JS
7032 "3321 Failed allocation for per_cpu stats\n");
7033 rc = -ENOMEM;
7034 goto out_free_hba_cpu_map;
7035 }
840eda96 7036
317aeb83
DK
7037 phba->sli4_hba.idle_stat = kcalloc(phba->sli4_hba.num_possible_cpu,
7038 sizeof(*phba->sli4_hba.idle_stat),
7039 GFP_KERNEL);
7040 if (!phba->sli4_hba.idle_stat) {
372c187b 7041 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
317aeb83
DK
7042 "3390 Failed allocation for idle_stat\n");
7043 rc = -ENOMEM;
7044 goto out_free_hba_eq_info;
7045 }
7046
840eda96
JS
7047#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
7048 phba->sli4_hba.c_stat = alloc_percpu(struct lpfc_hdwq_stat);
7049 if (!phba->sli4_hba.c_stat) {
372c187b 7050 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
840eda96
JS
7051 "3332 Failed allocating per cpu hdwq stats\n");
7052 rc = -ENOMEM;
317aeb83 7053 goto out_free_hba_idle_stat;
840eda96
JS
7054 }
7055#endif
7056
912e3acd
JS
7057 /*
7058 * Enable sr-iov virtual functions if supported and configured
7059 * through the module parameter.
7060 */
7061 if (phba->cfg_sriov_nr_virtfn > 0) {
7062 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
7063 phba->cfg_sriov_nr_virtfn);
7064 if (rc) {
7065 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
7066 "3020 Requested number of SR-IOV "
7067 "virtual functions (%d) is not "
7068 "supported\n",
7069 phba->cfg_sriov_nr_virtfn);
7070 phba->cfg_sriov_nr_virtfn = 0;
7071 }
7072 }
7073
5248a749 7074 return 0;
da0436e9 7075
840eda96 7076#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
317aeb83
DK
7077out_free_hba_idle_stat:
7078 kfree(phba->sli4_hba.idle_stat);
7079#endif
840eda96
JS
7080out_free_hba_eq_info:
7081 free_percpu(phba->sli4_hba.eq_info);
32517fc0
JS
7082out_free_hba_cpu_map:
7083 kfree(phba->sli4_hba.cpu_map);
895427bd
JS
7084out_free_hba_eq_hdl:
7085 kfree(phba->sli4_hba.hba_eq_hdl);
0c9ab6f5
JS
7086out_free_fcf_rr_bmask:
7087 kfree(phba->fcf.fcf_rr_bmask);
da0436e9
JS
7088out_remove_rpi_hdrs:
7089 lpfc_sli4_remove_rpi_hdrs(phba);
7090out_free_active_sgl:
7091 lpfc_free_active_sgl(phba);
da0436e9
JS
7092out_destroy_cq_event_pool:
7093 lpfc_sli4_cq_event_pool_destroy(phba);
d79c9e9d
JS
7094out_free_cmd_rsp_buf:
7095 dma_pool_destroy(phba->lpfc_cmd_rsp_buf_pool);
7096 phba->lpfc_cmd_rsp_buf_pool = NULL;
7097out_free_sg_dma_buf:
7098 dma_pool_destroy(phba->lpfc_sg_dma_buf_pool);
7099 phba->lpfc_sg_dma_buf_pool = NULL;
da0436e9
JS
7100out_free_bsmbx:
7101 lpfc_destroy_bootstrap_mbox(phba);
7102out_free_mem:
7103 lpfc_mem_free(phba);
7104 return rc;
7105}
7106
7107/**
7108 * lpfc_sli4_driver_resource_unset - Unset drvr internal resources for SLI4 dev
7109 * @phba: pointer to lpfc hba data structure.
7110 *
7111 * This routine is invoked to unset the driver internal resources set up
7112 * specific for supporting the SLI-4 HBA device it attached to.
7113 **/
7114static void
7115lpfc_sli4_driver_resource_unset(struct lpfc_hba *phba)
7116{
7117 struct lpfc_fcf_conn_entry *conn_entry, *next_conn_entry;
7118
32517fc0 7119 free_percpu(phba->sli4_hba.eq_info);
840eda96
JS
7120#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
7121 free_percpu(phba->sli4_hba.c_stat);
7122#endif
317aeb83 7123 kfree(phba->sli4_hba.idle_stat);
32517fc0 7124
7bb03bbf
JS
7125 /* Free memory allocated for msi-x interrupt vector to CPU mapping */
7126 kfree(phba->sli4_hba.cpu_map);
222e9239 7127 phba->sli4_hba.num_possible_cpu = 0;
7bb03bbf 7128 phba->sli4_hba.num_present_cpu = 0;
76fd07a6 7129 phba->sli4_hba.curr_disp_cpu = 0;
3048e3e8 7130 cpumask_clear(&phba->sli4_hba.irq_aff_mask);
7bb03bbf 7131
da0436e9 7132 /* Free memory allocated for fast-path work queue handles */
895427bd 7133 kfree(phba->sli4_hba.hba_eq_hdl);
da0436e9
JS
7134
7135 /* Free the allocated rpi headers. */
7136 lpfc_sli4_remove_rpi_hdrs(phba);
d11e31dd 7137 lpfc_sli4_remove_rpis(phba);
da0436e9 7138
0c9ab6f5
JS
7139 /* Free eligible FCF index bmask */
7140 kfree(phba->fcf.fcf_rr_bmask);
7141
da0436e9
JS
7142 /* Free the ELS sgl list */
7143 lpfc_free_active_sgl(phba);
8a9d2e80 7144 lpfc_free_els_sgl_list(phba);
f358dd0c 7145 lpfc_free_nvmet_sgl_list(phba);
da0436e9 7146
da0436e9
JS
7147 /* Free the completion queue EQ event pool */
7148 lpfc_sli4_cq_event_release_all(phba);
7149 lpfc_sli4_cq_event_pool_destroy(phba);
7150
6d368e53
JS
7151 /* Release resource identifiers. */
7152 lpfc_sli4_dealloc_resource_identifiers(phba);
7153
da0436e9
JS
7154 /* Free the bsmbx region. */
7155 lpfc_destroy_bootstrap_mbox(phba);
7156
7157 /* Free the SLI Layer memory with SLI4 HBAs */
7158 lpfc_mem_free_all(phba);
7159
7160 /* Free the current connect table */
7161 list_for_each_entry_safe(conn_entry, next_conn_entry,
4d9ab994
JS
7162 &phba->fcf_conn_rec_list, list) {
7163 list_del_init(&conn_entry->list);
da0436e9 7164 kfree(conn_entry);
4d9ab994 7165 }
da0436e9
JS
7166
7167 return;
7168}
7169
7170/**
25985edc 7171 * lpfc_init_api_table_setup - Set up init api function jump table
da0436e9
JS
7172 * @phba: The hba struct for which this call is being executed.
7173 * @dev_grp: The HBA PCI-Device group number.
7174 *
7175 * This routine sets up the device INIT interface API function jump table
7176 * in @phba struct.
7177 *
7178 * Returns: 0 - success, -ENODEV - failure.
7179 **/
7180int
7181lpfc_init_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
7182{
84d1b006
JS
7183 phba->lpfc_hba_init_link = lpfc_hba_init_link;
7184 phba->lpfc_hba_down_link = lpfc_hba_down_link;
7f86059a 7185 phba->lpfc_selective_reset = lpfc_selective_reset;
da0436e9
JS
7186 switch (dev_grp) {
7187 case LPFC_PCI_DEV_LP:
7188 phba->lpfc_hba_down_post = lpfc_hba_down_post_s3;
7189 phba->lpfc_handle_eratt = lpfc_handle_eratt_s3;
7190 phba->lpfc_stop_port = lpfc_stop_port_s3;
7191 break;
7192 case LPFC_PCI_DEV_OC:
7193 phba->lpfc_hba_down_post = lpfc_hba_down_post_s4;
7194 phba->lpfc_handle_eratt = lpfc_handle_eratt_s4;
7195 phba->lpfc_stop_port = lpfc_stop_port_s4;
7196 break;
7197 default:
372c187b 7198 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
7199 "1431 Invalid HBA PCI-device group: 0x%x\n",
7200 dev_grp);
7201 return -ENODEV;
da0436e9
JS
7202 }
7203 return 0;
7204}
7205
da0436e9
JS
7206/**
7207 * lpfc_setup_driver_resource_phase2 - Phase2 setup driver internal resources.
7208 * @phba: pointer to lpfc hba data structure.
7209 *
7210 * This routine is invoked to set up the driver internal resources after the
7211 * device specific resource setup to support the HBA device it attached to.
7212 *
7213 * Return codes
af901ca1 7214 * 0 - successful
da0436e9
JS
7215 * other values - error
7216 **/
7217static int
7218lpfc_setup_driver_resource_phase2(struct lpfc_hba *phba)
7219{
7220 int error;
7221
7222 /* Startup the kernel thread for this host adapter. */
7223 phba->worker_thread = kthread_run(lpfc_do_work, phba,
7224 "lpfc_worker_%d", phba->brd_no);
7225 if (IS_ERR(phba->worker_thread)) {
7226 error = PTR_ERR(phba->worker_thread);
7227 return error;
3772a991
JS
7228 }
7229
7230 return 0;
7231}
7232
7233/**
7234 * lpfc_unset_driver_resource_phase2 - Phase2 unset driver internal resources.
7235 * @phba: pointer to lpfc hba data structure.
7236 *
7237 * This routine is invoked to unset the driver internal resources set up after
7238 * the device specific resource setup for supporting the HBA device it
7239 * attached to.
7240 **/
7241static void
7242lpfc_unset_driver_resource_phase2(struct lpfc_hba *phba)
7243{
f485c18d
DK
7244 if (phba->wq) {
7245 flush_workqueue(phba->wq);
7246 destroy_workqueue(phba->wq);
7247 phba->wq = NULL;
7248 }
7249
3772a991 7250 /* Stop kernel worker thread */
0cdb84ec
JS
7251 if (phba->worker_thread)
7252 kthread_stop(phba->worker_thread);
3772a991
JS
7253}
7254
7255/**
7256 * lpfc_free_iocb_list - Free iocb list.
7257 * @phba: pointer to lpfc hba data structure.
7258 *
7259 * This routine is invoked to free the driver's IOCB list and memory.
7260 **/
6c621a22 7261void
3772a991
JS
7262lpfc_free_iocb_list(struct lpfc_hba *phba)
7263{
7264 struct lpfc_iocbq *iocbq_entry = NULL, *iocbq_next = NULL;
7265
7266 spin_lock_irq(&phba->hbalock);
7267 list_for_each_entry_safe(iocbq_entry, iocbq_next,
7268 &phba->lpfc_iocb_list, list) {
7269 list_del(&iocbq_entry->list);
7270 kfree(iocbq_entry);
7271 phba->total_iocbq_bufs--;
98c9ea5c 7272 }
3772a991
JS
7273 spin_unlock_irq(&phba->hbalock);
7274
7275 return;
7276}
7277
7278/**
7279 * lpfc_init_iocb_list - Allocate and initialize iocb list.
7280 * @phba: pointer to lpfc hba data structure.
fe614acd 7281 * @iocb_count: number of requested iocbs
3772a991
JS
7282 *
7283 * This routine is invoked to allocate and initizlize the driver's IOCB
7284 * list and set up the IOCB tag array accordingly.
7285 *
7286 * Return codes
af901ca1 7287 * 0 - successful
3772a991
JS
7288 * other values - error
7289 **/
6c621a22 7290int
3772a991
JS
7291lpfc_init_iocb_list(struct lpfc_hba *phba, int iocb_count)
7292{
7293 struct lpfc_iocbq *iocbq_entry = NULL;
7294 uint16_t iotag;
7295 int i;
dea3101e 7296
7297 /* Initialize and populate the iocb list per host. */
7298 INIT_LIST_HEAD(&phba->lpfc_iocb_list);
3772a991 7299 for (i = 0; i < iocb_count; i++) {
dd00cc48 7300 iocbq_entry = kzalloc(sizeof(struct lpfc_iocbq), GFP_KERNEL);
dea3101e 7301 if (iocbq_entry == NULL) {
7302 printk(KERN_ERR "%s: only allocated %d iocbs of "
7303 "expected %d count. Unloading driver.\n",
a5f7337f 7304 __func__, i, iocb_count);
dea3101e 7305 goto out_free_iocbq;
7306 }
7307
604a3e30
JB
7308 iotag = lpfc_sli_next_iotag(phba, iocbq_entry);
7309 if (iotag == 0) {
3772a991 7310 kfree(iocbq_entry);
604a3e30 7311 printk(KERN_ERR "%s: failed to allocate IOTAG. "
3772a991 7312 "Unloading driver.\n", __func__);
604a3e30
JB
7313 goto out_free_iocbq;
7314 }
6d368e53 7315 iocbq_entry->sli4_lxritag = NO_XRI;
3772a991 7316 iocbq_entry->sli4_xritag = NO_XRI;
2e0fef85
JS
7317
7318 spin_lock_irq(&phba->hbalock);
dea3101e 7319 list_add(&iocbq_entry->list, &phba->lpfc_iocb_list);
7320 phba->total_iocbq_bufs++;
2e0fef85 7321 spin_unlock_irq(&phba->hbalock);
dea3101e 7322 }
7323
3772a991 7324 return 0;
dea3101e 7325
3772a991
JS
7326out_free_iocbq:
7327 lpfc_free_iocb_list(phba);
dea3101e 7328
3772a991
JS
7329 return -ENOMEM;
7330}
5e9d9b82 7331
3772a991 7332/**
8a9d2e80 7333 * lpfc_free_sgl_list - Free a given sgl list.
da0436e9 7334 * @phba: pointer to lpfc hba data structure.
8a9d2e80 7335 * @sglq_list: pointer to the head of sgl list.
3772a991 7336 *
8a9d2e80 7337 * This routine is invoked to free a give sgl list and memory.
3772a991 7338 **/
8a9d2e80
JS
7339void
7340lpfc_free_sgl_list(struct lpfc_hba *phba, struct list_head *sglq_list)
3772a991 7341{
da0436e9 7342 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
8a9d2e80
JS
7343
7344 list_for_each_entry_safe(sglq_entry, sglq_next, sglq_list, list) {
7345 list_del(&sglq_entry->list);
7346 lpfc_mbuf_free(phba, sglq_entry->virt, sglq_entry->phys);
7347 kfree(sglq_entry);
7348 }
7349}
7350
7351/**
7352 * lpfc_free_els_sgl_list - Free els sgl list.
7353 * @phba: pointer to lpfc hba data structure.
7354 *
7355 * This routine is invoked to free the driver's els sgl list and memory.
7356 **/
7357static void
7358lpfc_free_els_sgl_list(struct lpfc_hba *phba)
7359{
da0436e9 7360 LIST_HEAD(sglq_list);
dea3101e 7361
8a9d2e80 7362 /* Retrieve all els sgls from driver list */
da0436e9 7363 spin_lock_irq(&phba->hbalock);
895427bd
JS
7364 spin_lock(&phba->sli4_hba.sgl_list_lock);
7365 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list, &sglq_list);
7366 spin_unlock(&phba->sli4_hba.sgl_list_lock);
da0436e9 7367 spin_unlock_irq(&phba->hbalock);
dea3101e 7368
8a9d2e80
JS
7369 /* Now free the sgl list */
7370 lpfc_free_sgl_list(phba, &sglq_list);
da0436e9 7371}
92d7f7b0 7372
f358dd0c
JS
7373/**
7374 * lpfc_free_nvmet_sgl_list - Free nvmet sgl list.
7375 * @phba: pointer to lpfc hba data structure.
7376 *
7377 * This routine is invoked to free the driver's nvmet sgl list and memory.
7378 **/
7379static void
7380lpfc_free_nvmet_sgl_list(struct lpfc_hba *phba)
7381{
7382 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
7383 LIST_HEAD(sglq_list);
7384
7385 /* Retrieve all nvmet sgls from driver list */
7386 spin_lock_irq(&phba->hbalock);
7387 spin_lock(&phba->sli4_hba.sgl_list_lock);
7388 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list, &sglq_list);
7389 spin_unlock(&phba->sli4_hba.sgl_list_lock);
7390 spin_unlock_irq(&phba->hbalock);
7391
7392 /* Now free the sgl list */
7393 list_for_each_entry_safe(sglq_entry, sglq_next, &sglq_list, list) {
7394 list_del(&sglq_entry->list);
7395 lpfc_nvmet_buf_free(phba, sglq_entry->virt, sglq_entry->phys);
7396 kfree(sglq_entry);
7397 }
4b40d02b
DK
7398
7399 /* Update the nvmet_xri_cnt to reflect no current sgls.
7400 * The next initialization cycle sets the count and allocates
7401 * the sgls over again.
7402 */
7403 phba->sli4_hba.nvmet_xri_cnt = 0;
f358dd0c
JS
7404}
7405
da0436e9
JS
7406/**
7407 * lpfc_init_active_sgl_array - Allocate the buf to track active ELS XRIs.
7408 * @phba: pointer to lpfc hba data structure.
7409 *
7410 * This routine is invoked to allocate the driver's active sgl memory.
7411 * This array will hold the sglq_entry's for active IOs.
7412 **/
7413static int
7414lpfc_init_active_sgl_array(struct lpfc_hba *phba)
7415{
7416 int size;
7417 size = sizeof(struct lpfc_sglq *);
7418 size *= phba->sli4_hba.max_cfg_param.max_xri;
7419
7420 phba->sli4_hba.lpfc_sglq_active_list =
7421 kzalloc(size, GFP_KERNEL);
7422 if (!phba->sli4_hba.lpfc_sglq_active_list)
7423 return -ENOMEM;
7424 return 0;
3772a991
JS
7425}
7426
7427/**
da0436e9 7428 * lpfc_free_active_sgl - Free the buf that tracks active ELS XRIs.
3772a991
JS
7429 * @phba: pointer to lpfc hba data structure.
7430 *
da0436e9
JS
7431 * This routine is invoked to walk through the array of active sglq entries
7432 * and free all of the resources.
7433 * This is just a place holder for now.
3772a991
JS
7434 **/
7435static void
da0436e9 7436lpfc_free_active_sgl(struct lpfc_hba *phba)
3772a991 7437{
da0436e9 7438 kfree(phba->sli4_hba.lpfc_sglq_active_list);
3772a991
JS
7439}
7440
7441/**
da0436e9 7442 * lpfc_init_sgl_list - Allocate and initialize sgl list.
3772a991
JS
7443 * @phba: pointer to lpfc hba data structure.
7444 *
da0436e9
JS
7445 * This routine is invoked to allocate and initizlize the driver's sgl
7446 * list and set up the sgl xritag tag array accordingly.
3772a991 7447 *
3772a991 7448 **/
8a9d2e80 7449static void
da0436e9 7450lpfc_init_sgl_list(struct lpfc_hba *phba)
3772a991 7451{
da0436e9 7452 /* Initialize and populate the sglq list per host/VF. */
895427bd 7453 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_els_sgl_list);
da0436e9 7454 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_els_sgl_list);
f358dd0c 7455 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_sgl_list);
86c67379 7456 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
da0436e9 7457
8a9d2e80
JS
7458 /* els xri-sgl book keeping */
7459 phba->sli4_hba.els_xri_cnt = 0;
0ff10d46 7460
895427bd 7461 /* nvme xri-buffer book keeping */
5e5b511d 7462 phba->sli4_hba.io_xri_cnt = 0;
da0436e9
JS
7463}
7464
7465/**
7466 * lpfc_sli4_init_rpi_hdrs - Post the rpi header memory region to the port
7467 * @phba: pointer to lpfc hba data structure.
7468 *
7469 * This routine is invoked to post rpi header templates to the
88a2cfbb 7470 * port for those SLI4 ports that do not support extents. This routine
da0436e9 7471 * posts a PAGE_SIZE memory region to the port to hold up to
88a2cfbb
JS
7472 * PAGE_SIZE modulo 64 rpi context headers. This is an initialization routine
7473 * and should be called only when interrupts are disabled.
da0436e9
JS
7474 *
7475 * Return codes
af901ca1 7476 * 0 - successful
88a2cfbb 7477 * -ERROR - otherwise.
da0436e9
JS
7478 **/
7479int
7480lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *phba)
7481{
7482 int rc = 0;
da0436e9
JS
7483 struct lpfc_rpi_hdr *rpi_hdr;
7484
7485 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_hdr_list);
ff78d8f9 7486 if (!phba->sli4_hba.rpi_hdrs_in_use)
6d368e53 7487 return rc;
6d368e53
JS
7488 if (phba->sli4_hba.extents_in_use)
7489 return -EIO;
da0436e9
JS
7490
7491 rpi_hdr = lpfc_sli4_create_rpi_hdr(phba);
7492 if (!rpi_hdr) {
372c187b 7493 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
7494 "0391 Error during rpi post operation\n");
7495 lpfc_sli4_remove_rpis(phba);
7496 rc = -ENODEV;
7497 }
7498
7499 return rc;
7500}
7501
7502/**
7503 * lpfc_sli4_create_rpi_hdr - Allocate an rpi header memory region
7504 * @phba: pointer to lpfc hba data structure.
7505 *
7506 * This routine is invoked to allocate a single 4KB memory region to
7507 * support rpis and stores them in the phba. This single region
7508 * provides support for up to 64 rpis. The region is used globally
7509 * by the device.
7510 *
7511 * Returns:
7512 * A valid rpi hdr on success.
7513 * A NULL pointer on any failure.
7514 **/
7515struct lpfc_rpi_hdr *
7516lpfc_sli4_create_rpi_hdr(struct lpfc_hba *phba)
7517{
7518 uint16_t rpi_limit, curr_rpi_range;
7519 struct lpfc_dmabuf *dmabuf;
7520 struct lpfc_rpi_hdr *rpi_hdr;
7521
6d368e53
JS
7522 /*
7523 * If the SLI4 port supports extents, posting the rpi header isn't
7524 * required. Set the expected maximum count and let the actual value
7525 * get set when extents are fully allocated.
7526 */
7527 if (!phba->sli4_hba.rpi_hdrs_in_use)
7528 return NULL;
7529 if (phba->sli4_hba.extents_in_use)
7530 return NULL;
7531
7532 /* The limit on the logical index is just the max_rpi count. */
845d9e8d 7533 rpi_limit = phba->sli4_hba.max_cfg_param.max_rpi;
da0436e9
JS
7534
7535 spin_lock_irq(&phba->hbalock);
6d368e53
JS
7536 /*
7537 * Establish the starting RPI in this header block. The starting
7538 * rpi is normalized to a zero base because the physical rpi is
7539 * port based.
7540 */
97f2ecf1 7541 curr_rpi_range = phba->sli4_hba.next_rpi;
da0436e9
JS
7542 spin_unlock_irq(&phba->hbalock);
7543
845d9e8d
JS
7544 /* Reached full RPI range */
7545 if (curr_rpi_range == rpi_limit)
6d368e53 7546 return NULL;
845d9e8d 7547
da0436e9
JS
7548 /*
7549 * First allocate the protocol header region for the port. The
7550 * port expects a 4KB DMA-mapped memory region that is 4K aligned.
7551 */
7552 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
7553 if (!dmabuf)
7554 return NULL;
7555
750afb08
LC
7556 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
7557 LPFC_HDR_TEMPLATE_SIZE,
7558 &dmabuf->phys, GFP_KERNEL);
da0436e9
JS
7559 if (!dmabuf->virt) {
7560 rpi_hdr = NULL;
7561 goto err_free_dmabuf;
7562 }
7563
da0436e9
JS
7564 if (!IS_ALIGNED(dmabuf->phys, LPFC_HDR_TEMPLATE_SIZE)) {
7565 rpi_hdr = NULL;
7566 goto err_free_coherent;
7567 }
7568
7569 /* Save the rpi header data for cleanup later. */
7570 rpi_hdr = kzalloc(sizeof(struct lpfc_rpi_hdr), GFP_KERNEL);
7571 if (!rpi_hdr)
7572 goto err_free_coherent;
7573
7574 rpi_hdr->dmabuf = dmabuf;
7575 rpi_hdr->len = LPFC_HDR_TEMPLATE_SIZE;
7576 rpi_hdr->page_count = 1;
7577 spin_lock_irq(&phba->hbalock);
6d368e53
JS
7578
7579 /* The rpi_hdr stores the logical index only. */
7580 rpi_hdr->start_rpi = curr_rpi_range;
845d9e8d 7581 rpi_hdr->next_rpi = phba->sli4_hba.next_rpi + LPFC_RPI_HDR_COUNT;
da0436e9
JS
7582 list_add_tail(&rpi_hdr->list, &phba->sli4_hba.lpfc_rpi_hdr_list);
7583
da0436e9
JS
7584 spin_unlock_irq(&phba->hbalock);
7585 return rpi_hdr;
7586
7587 err_free_coherent:
7588 dma_free_coherent(&phba->pcidev->dev, LPFC_HDR_TEMPLATE_SIZE,
7589 dmabuf->virt, dmabuf->phys);
7590 err_free_dmabuf:
7591 kfree(dmabuf);
7592 return NULL;
7593}
7594
7595/**
7596 * lpfc_sli4_remove_rpi_hdrs - Remove all rpi header memory regions
7597 * @phba: pointer to lpfc hba data structure.
7598 *
7599 * This routine is invoked to remove all memory resources allocated
6d368e53
JS
7600 * to support rpis for SLI4 ports not supporting extents. This routine
7601 * presumes the caller has released all rpis consumed by fabric or port
7602 * logins and is prepared to have the header pages removed.
da0436e9
JS
7603 **/
7604void
7605lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *phba)
7606{
7607 struct lpfc_rpi_hdr *rpi_hdr, *next_rpi_hdr;
7608
6d368e53
JS
7609 if (!phba->sli4_hba.rpi_hdrs_in_use)
7610 goto exit;
7611
da0436e9
JS
7612 list_for_each_entry_safe(rpi_hdr, next_rpi_hdr,
7613 &phba->sli4_hba.lpfc_rpi_hdr_list, list) {
7614 list_del(&rpi_hdr->list);
7615 dma_free_coherent(&phba->pcidev->dev, rpi_hdr->len,
7616 rpi_hdr->dmabuf->virt, rpi_hdr->dmabuf->phys);
7617 kfree(rpi_hdr->dmabuf);
7618 kfree(rpi_hdr);
7619 }
6d368e53
JS
7620 exit:
7621 /* There are no rpis available to the port now. */
7622 phba->sli4_hba.next_rpi = 0;
da0436e9
JS
7623}
7624
7625/**
7626 * lpfc_hba_alloc - Allocate driver hba data structure for a device.
7627 * @pdev: pointer to pci device data structure.
7628 *
7629 * This routine is invoked to allocate the driver hba data structure for an
7630 * HBA device. If the allocation is successful, the phba reference to the
7631 * PCI device data structure is set.
7632 *
7633 * Return codes
af901ca1 7634 * pointer to @phba - successful
da0436e9
JS
7635 * NULL - error
7636 **/
7637static struct lpfc_hba *
7638lpfc_hba_alloc(struct pci_dev *pdev)
7639{
7640 struct lpfc_hba *phba;
7641
7642 /* Allocate memory for HBA structure */
7643 phba = kzalloc(sizeof(struct lpfc_hba), GFP_KERNEL);
7644 if (!phba) {
e34ccdfe 7645 dev_err(&pdev->dev, "failed to allocate hba struct\n");
da0436e9
JS
7646 return NULL;
7647 }
7648
7649 /* Set reference to PCI device in HBA structure */
7650 phba->pcidev = pdev;
7651
7652 /* Assign an unused board number */
7653 phba->brd_no = lpfc_get_instance();
7654 if (phba->brd_no < 0) {
7655 kfree(phba);
7656 return NULL;
7657 }
65791f1f 7658 phba->eratt_poll_interval = LPFC_ERATT_POLL_INTERVAL;
da0436e9 7659
4fede78f 7660 spin_lock_init(&phba->ct_ev_lock);
f1c3b0fc
JS
7661 INIT_LIST_HEAD(&phba->ct_ev_waiters);
7662
da0436e9
JS
7663 return phba;
7664}
7665
7666/**
7667 * lpfc_hba_free - Free driver hba data structure with a device.
7668 * @phba: pointer to lpfc hba data structure.
7669 *
7670 * This routine is invoked to free the driver hba data structure with an
7671 * HBA device.
7672 **/
7673static void
7674lpfc_hba_free(struct lpfc_hba *phba)
7675{
5e5b511d
JS
7676 if (phba->sli_rev == LPFC_SLI_REV4)
7677 kfree(phba->sli4_hba.hdwq);
7678
da0436e9
JS
7679 /* Release the driver assigned board number */
7680 idr_remove(&lpfc_hba_index, phba->brd_no);
7681
895427bd
JS
7682 /* Free memory allocated with sli3 rings */
7683 kfree(phba->sli.sli3_ring);
7684 phba->sli.sli3_ring = NULL;
2a76a283 7685
da0436e9
JS
7686 kfree(phba);
7687 return;
7688}
7689
7690/**
7691 * lpfc_create_shost - Create hba physical port with associated scsi host.
7692 * @phba: pointer to lpfc hba data structure.
7693 *
7694 * This routine is invoked to create HBA physical port and associate a SCSI
7695 * host with it.
7696 *
7697 * Return codes
af901ca1 7698 * 0 - successful
da0436e9
JS
7699 * other values - error
7700 **/
7701static int
7702lpfc_create_shost(struct lpfc_hba *phba)
7703{
7704 struct lpfc_vport *vport;
7705 struct Scsi_Host *shost;
7706
7707 /* Initialize HBA FC structure */
7708 phba->fc_edtov = FF_DEF_EDTOV;
7709 phba->fc_ratov = FF_DEF_RATOV;
7710 phba->fc_altov = FF_DEF_ALTOV;
7711 phba->fc_arbtov = FF_DEF_ARBTOV;
7712
d7c47992 7713 atomic_set(&phba->sdev_cnt, 0);
da0436e9
JS
7714 vport = lpfc_create_port(phba, phba->brd_no, &phba->pcidev->dev);
7715 if (!vport)
7716 return -ENODEV;
7717
7718 shost = lpfc_shost_from_vport(vport);
7719 phba->pport = vport;
2ea259ee 7720
f358dd0c
JS
7721 if (phba->nvmet_support) {
7722 /* Only 1 vport (pport) will support NVME target */
ea85a20c
JS
7723 phba->targetport = NULL;
7724 phba->cfg_enable_fc4_type = LPFC_ENABLE_NVME;
7725 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME_DISC,
7726 "6076 NVME Target Found\n");
f358dd0c
JS
7727 }
7728
da0436e9
JS
7729 lpfc_debugfs_initialize(vport);
7730 /* Put reference to SCSI host to driver's device private data */
7731 pci_set_drvdata(phba->pcidev, shost);
2e0fef85 7732
4258e98e
JS
7733 /*
7734 * At this point we are fully registered with PSA. In addition,
7735 * any initial discovery should be completed.
7736 */
7737 vport->load_flag |= FC_ALLOW_FDMI;
8663cbbe
JS
7738 if (phba->cfg_enable_SmartSAN ||
7739 (phba->cfg_fdmi_on == LPFC_FDMI_SUPPORT)) {
4258e98e
JS
7740
7741 /* Setup appropriate attribute masks */
7742 vport->fdmi_hba_mask = LPFC_FDMI2_HBA_ATTR;
8663cbbe 7743 if (phba->cfg_enable_SmartSAN)
4258e98e
JS
7744 vport->fdmi_port_mask = LPFC_FDMI2_SMART_ATTR;
7745 else
7746 vport->fdmi_port_mask = LPFC_FDMI2_PORT_ATTR;
7747 }
3772a991
JS
7748 return 0;
7749}
db2378e0 7750
3772a991
JS
7751/**
7752 * lpfc_destroy_shost - Destroy hba physical port with associated scsi host.
7753 * @phba: pointer to lpfc hba data structure.
7754 *
7755 * This routine is invoked to destroy HBA physical port and the associated
7756 * SCSI host.
7757 **/
7758static void
7759lpfc_destroy_shost(struct lpfc_hba *phba)
7760{
7761 struct lpfc_vport *vport = phba->pport;
7762
7763 /* Destroy physical port that associated with the SCSI host */
7764 destroy_port(vport);
7765
7766 return;
7767}
7768
7769/**
7770 * lpfc_setup_bg - Setup Block guard structures and debug areas.
7771 * @phba: pointer to lpfc hba data structure.
7772 * @shost: the shost to be used to detect Block guard settings.
7773 *
7774 * This routine sets up the local Block guard protocol settings for @shost.
7775 * This routine also allocates memory for debugging bg buffers.
7776 **/
7777static void
7778lpfc_setup_bg(struct lpfc_hba *phba, struct Scsi_Host *shost)
7779{
bbeb79b9
JS
7780 uint32_t old_mask;
7781 uint32_t old_guard;
7782
b3b98b74 7783 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
3772a991
JS
7784 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7785 "1478 Registering BlockGuard with the "
7786 "SCSI layer\n");
bbeb79b9 7787
b3b98b74
JS
7788 old_mask = phba->cfg_prot_mask;
7789 old_guard = phba->cfg_prot_guard;
bbeb79b9
JS
7790
7791 /* Only allow supported values */
b3b98b74 7792 phba->cfg_prot_mask &= (SHOST_DIF_TYPE1_PROTECTION |
bbeb79b9
JS
7793 SHOST_DIX_TYPE0_PROTECTION |
7794 SHOST_DIX_TYPE1_PROTECTION);
b3b98b74
JS
7795 phba->cfg_prot_guard &= (SHOST_DIX_GUARD_IP |
7796 SHOST_DIX_GUARD_CRC);
bbeb79b9
JS
7797
7798 /* DIF Type 1 protection for profiles AST1/C1 is end to end */
b3b98b74
JS
7799 if (phba->cfg_prot_mask == SHOST_DIX_TYPE1_PROTECTION)
7800 phba->cfg_prot_mask |= SHOST_DIF_TYPE1_PROTECTION;
bbeb79b9 7801
b3b98b74
JS
7802 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
7803 if ((old_mask != phba->cfg_prot_mask) ||
7804 (old_guard != phba->cfg_prot_guard))
372c187b 7805 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
bbeb79b9
JS
7806 "1475 Registering BlockGuard with the "
7807 "SCSI layer: mask %d guard %d\n",
b3b98b74
JS
7808 phba->cfg_prot_mask,
7809 phba->cfg_prot_guard);
bbeb79b9 7810
b3b98b74
JS
7811 scsi_host_set_prot(shost, phba->cfg_prot_mask);
7812 scsi_host_set_guard(shost, phba->cfg_prot_guard);
bbeb79b9 7813 } else
372c187b 7814 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
bbeb79b9
JS
7815 "1479 Not Registering BlockGuard with the SCSI "
7816 "layer, Bad protection parameters: %d %d\n",
7817 old_mask, old_guard);
3772a991 7818 }
3772a991
JS
7819}
7820
7821/**
7822 * lpfc_post_init_setup - Perform necessary device post initialization setup.
7823 * @phba: pointer to lpfc hba data structure.
7824 *
7825 * This routine is invoked to perform all the necessary post initialization
7826 * setup for the device.
7827 **/
7828static void
7829lpfc_post_init_setup(struct lpfc_hba *phba)
7830{
7831 struct Scsi_Host *shost;
7832 struct lpfc_adapter_event_header adapter_event;
7833
7834 /* Get the default values for Model Name and Description */
7835 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
7836
7837 /*
7838 * hba setup may have changed the hba_queue_depth so we need to
7839 * adjust the value of can_queue.
7840 */
7841 shost = pci_get_drvdata(phba->pcidev);
7842 shost->can_queue = phba->cfg_hba_queue_depth - 10;
3772a991
JS
7843
7844 lpfc_host_attrib_init(shost);
7845
7846 if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
7847 spin_lock_irq(shost->host_lock);
7848 lpfc_poll_start_timer(phba);
7849 spin_unlock_irq(shost->host_lock);
7850 }
7851
7852 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7853 "0428 Perform SCSI scan\n");
7854 /* Send board arrival event to upper layer */
7855 adapter_event.event_type = FC_REG_ADAPTER_EVENT;
7856 adapter_event.subcategory = LPFC_EVENT_ARRIVAL;
7857 fc_host_post_vendor_event(shost, fc_get_event_number(),
7858 sizeof(adapter_event),
7859 (char *) &adapter_event,
7860 LPFC_NL_VENDOR_ID);
7861 return;
7862}
7863
7864/**
7865 * lpfc_sli_pci_mem_setup - Setup SLI3 HBA PCI memory space.
7866 * @phba: pointer to lpfc hba data structure.
7867 *
7868 * This routine is invoked to set up the PCI device memory space for device
7869 * with SLI-3 interface spec.
7870 *
7871 * Return codes
af901ca1 7872 * 0 - successful
3772a991
JS
7873 * other values - error
7874 **/
7875static int
7876lpfc_sli_pci_mem_setup(struct lpfc_hba *phba)
7877{
f30e1bfd 7878 struct pci_dev *pdev = phba->pcidev;
3772a991
JS
7879 unsigned long bar0map_len, bar2map_len;
7880 int i, hbq_count;
7881 void *ptr;
56de8357 7882 int error;
3772a991 7883
f30e1bfd 7884 if (!pdev)
56de8357 7885 return -ENODEV;
3772a991
JS
7886
7887 /* Set the device DMA mask size */
56de8357
HR
7888 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7889 if (error)
7890 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7891 if (error)
f30e1bfd 7892 return error;
56de8357 7893 error = -ENODEV;
3772a991
JS
7894
7895 /* Get the bus address of Bar0 and Bar2 and the number of bytes
7896 * required by each mapping.
7897 */
7898 phba->pci_bar0_map = pci_resource_start(pdev, 0);
7899 bar0map_len = pci_resource_len(pdev, 0);
7900
7901 phba->pci_bar2_map = pci_resource_start(pdev, 2);
7902 bar2map_len = pci_resource_len(pdev, 2);
7903
7904 /* Map HBA SLIM to a kernel virtual address. */
7905 phba->slim_memmap_p = ioremap(phba->pci_bar0_map, bar0map_len);
7906 if (!phba->slim_memmap_p) {
7907 dev_printk(KERN_ERR, &pdev->dev,
7908 "ioremap failed for SLIM memory.\n");
7909 goto out;
7910 }
7911
7912 /* Map HBA Control Registers to a kernel virtual address. */
7913 phba->ctrl_regs_memmap_p = ioremap(phba->pci_bar2_map, bar2map_len);
7914 if (!phba->ctrl_regs_memmap_p) {
7915 dev_printk(KERN_ERR, &pdev->dev,
7916 "ioremap failed for HBA control registers.\n");
7917 goto out_iounmap_slim;
7918 }
7919
7920 /* Allocate memory for SLI-2 structures */
750afb08
LC
7921 phba->slim2p.virt = dma_alloc_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7922 &phba->slim2p.phys, GFP_KERNEL);
3772a991
JS
7923 if (!phba->slim2p.virt)
7924 goto out_iounmap;
7925
3772a991 7926 phba->mbox = phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, mbx);
7a470277
JS
7927 phba->mbox_ext = (phba->slim2p.virt +
7928 offsetof(struct lpfc_sli2_slim, mbx_ext_words));
3772a991
JS
7929 phba->pcb = (phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, pcb));
7930 phba->IOCBs = (phba->slim2p.virt +
7931 offsetof(struct lpfc_sli2_slim, IOCBs));
7932
7933 phba->hbqslimp.virt = dma_alloc_coherent(&pdev->dev,
7934 lpfc_sli_hbq_size(),
7935 &phba->hbqslimp.phys,
7936 GFP_KERNEL);
7937 if (!phba->hbqslimp.virt)
7938 goto out_free_slim;
7939
7940 hbq_count = lpfc_sli_hbq_count();
7941 ptr = phba->hbqslimp.virt;
7942 for (i = 0; i < hbq_count; ++i) {
7943 phba->hbqs[i].hbq_virt = ptr;
7944 INIT_LIST_HEAD(&phba->hbqs[i].hbq_buffer_list);
7945 ptr += (lpfc_hbq_defs[i]->entry_count *
7946 sizeof(struct lpfc_hbq_entry));
7947 }
7948 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_els_hbq_alloc;
7949 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_els_hbq_free;
7950
7951 memset(phba->hbqslimp.virt, 0, lpfc_sli_hbq_size());
7952
3772a991
JS
7953 phba->MBslimaddr = phba->slim_memmap_p;
7954 phba->HAregaddr = phba->ctrl_regs_memmap_p + HA_REG_OFFSET;
7955 phba->CAregaddr = phba->ctrl_regs_memmap_p + CA_REG_OFFSET;
7956 phba->HSregaddr = phba->ctrl_regs_memmap_p + HS_REG_OFFSET;
7957 phba->HCregaddr = phba->ctrl_regs_memmap_p + HC_REG_OFFSET;
7958
7959 return 0;
7960
7961out_free_slim:
7962 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7963 phba->slim2p.virt, phba->slim2p.phys);
7964out_iounmap:
7965 iounmap(phba->ctrl_regs_memmap_p);
7966out_iounmap_slim:
7967 iounmap(phba->slim_memmap_p);
7968out:
7969 return error;
7970}
7971
7972/**
7973 * lpfc_sli_pci_mem_unset - Unset SLI3 HBA PCI memory space.
7974 * @phba: pointer to lpfc hba data structure.
7975 *
7976 * This routine is invoked to unset the PCI device memory space for device
7977 * with SLI-3 interface spec.
7978 **/
7979static void
7980lpfc_sli_pci_mem_unset(struct lpfc_hba *phba)
7981{
7982 struct pci_dev *pdev;
7983
7984 /* Obtain PCI device reference */
7985 if (!phba->pcidev)
7986 return;
7987 else
7988 pdev = phba->pcidev;
7989
7990 /* Free coherent DMA memory allocated */
7991 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
7992 phba->hbqslimp.virt, phba->hbqslimp.phys);
7993 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7994 phba->slim2p.virt, phba->slim2p.phys);
7995
7996 /* I/O memory unmap */
7997 iounmap(phba->ctrl_regs_memmap_p);
7998 iounmap(phba->slim_memmap_p);
7999
8000 return;
8001}
8002
8003/**
da0436e9 8004 * lpfc_sli4_post_status_check - Wait for SLI4 POST done and check status
3772a991
JS
8005 * @phba: pointer to lpfc hba data structure.
8006 *
da0436e9
JS
8007 * This routine is invoked to wait for SLI4 device Power On Self Test (POST)
8008 * done and check status.
3772a991 8009 *
da0436e9 8010 * Return 0 if successful, otherwise -ENODEV.
3772a991 8011 **/
da0436e9
JS
8012int
8013lpfc_sli4_post_status_check(struct lpfc_hba *phba)
3772a991 8014{
2fcee4bf
JS
8015 struct lpfc_register portsmphr_reg, uerrlo_reg, uerrhi_reg;
8016 struct lpfc_register reg_data;
8017 int i, port_error = 0;
8018 uint32_t if_type;
3772a991 8019
9940b97b
JS
8020 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
8021 memset(&reg_data, 0, sizeof(reg_data));
2fcee4bf 8022 if (!phba->sli4_hba.PSMPHRregaddr)
da0436e9 8023 return -ENODEV;
3772a991 8024
da0436e9
JS
8025 /* Wait up to 30 seconds for the SLI Port POST done and ready */
8026 for (i = 0; i < 3000; i++) {
9940b97b
JS
8027 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
8028 &portsmphr_reg.word0) ||
8029 (bf_get(lpfc_port_smphr_perr, &portsmphr_reg))) {
2fcee4bf 8030 /* Port has a fatal POST error, break out */
da0436e9
JS
8031 port_error = -ENODEV;
8032 break;
8033 }
2fcee4bf
JS
8034 if (LPFC_POST_STAGE_PORT_READY ==
8035 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg))
da0436e9 8036 break;
da0436e9 8037 msleep(10);
3772a991
JS
8038 }
8039
2fcee4bf
JS
8040 /*
8041 * If there was a port error during POST, then don't proceed with
8042 * other register reads as the data may not be valid. Just exit.
8043 */
8044 if (port_error) {
372c187b 8045 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
8046 "1408 Port Failed POST - portsmphr=0x%x, "
8047 "perr=x%x, sfi=x%x, nip=x%x, ipc=x%x, scr1=x%x, "
8048 "scr2=x%x, hscratch=x%x, pstatus=x%x\n",
8049 portsmphr_reg.word0,
8050 bf_get(lpfc_port_smphr_perr, &portsmphr_reg),
8051 bf_get(lpfc_port_smphr_sfi, &portsmphr_reg),
8052 bf_get(lpfc_port_smphr_nip, &portsmphr_reg),
8053 bf_get(lpfc_port_smphr_ipc, &portsmphr_reg),
8054 bf_get(lpfc_port_smphr_scr1, &portsmphr_reg),
8055 bf_get(lpfc_port_smphr_scr2, &portsmphr_reg),
8056 bf_get(lpfc_port_smphr_host_scratch, &portsmphr_reg),
8057 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg));
8058 } else {
28baac74 8059 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
2fcee4bf
JS
8060 "2534 Device Info: SLIFamily=0x%x, "
8061 "SLIRev=0x%x, IFType=0x%x, SLIHint_1=0x%x, "
8062 "SLIHint_2=0x%x, FT=0x%x\n",
28baac74
JS
8063 bf_get(lpfc_sli_intf_sli_family,
8064 &phba->sli4_hba.sli_intf),
8065 bf_get(lpfc_sli_intf_slirev,
8066 &phba->sli4_hba.sli_intf),
085c647c
JS
8067 bf_get(lpfc_sli_intf_if_type,
8068 &phba->sli4_hba.sli_intf),
8069 bf_get(lpfc_sli_intf_sli_hint1,
28baac74 8070 &phba->sli4_hba.sli_intf),
085c647c
JS
8071 bf_get(lpfc_sli_intf_sli_hint2,
8072 &phba->sli4_hba.sli_intf),
8073 bf_get(lpfc_sli_intf_func_type,
28baac74 8074 &phba->sli4_hba.sli_intf));
2fcee4bf
JS
8075 /*
8076 * Check for other Port errors during the initialization
8077 * process. Fail the load if the port did not come up
8078 * correctly.
8079 */
8080 if_type = bf_get(lpfc_sli_intf_if_type,
8081 &phba->sli4_hba.sli_intf);
8082 switch (if_type) {
8083 case LPFC_SLI_INTF_IF_TYPE_0:
8084 phba->sli4_hba.ue_mask_lo =
8085 readl(phba->sli4_hba.u.if_type0.UEMASKLOregaddr);
8086 phba->sli4_hba.ue_mask_hi =
8087 readl(phba->sli4_hba.u.if_type0.UEMASKHIregaddr);
8088 uerrlo_reg.word0 =
8089 readl(phba->sli4_hba.u.if_type0.UERRLOregaddr);
8090 uerrhi_reg.word0 =
8091 readl(phba->sli4_hba.u.if_type0.UERRHIregaddr);
8092 if ((~phba->sli4_hba.ue_mask_lo & uerrlo_reg.word0) ||
8093 (~phba->sli4_hba.ue_mask_hi & uerrhi_reg.word0)) {
372c187b
DK
8094 lpfc_printf_log(phba, KERN_ERR,
8095 LOG_TRACE_EVENT,
2fcee4bf
JS
8096 "1422 Unrecoverable Error "
8097 "Detected during POST "
8098 "uerr_lo_reg=0x%x, "
8099 "uerr_hi_reg=0x%x, "
8100 "ue_mask_lo_reg=0x%x, "
8101 "ue_mask_hi_reg=0x%x\n",
8102 uerrlo_reg.word0,
8103 uerrhi_reg.word0,
8104 phba->sli4_hba.ue_mask_lo,
8105 phba->sli4_hba.ue_mask_hi);
8106 port_error = -ENODEV;
8107 }
8108 break;
8109 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 8110 case LPFC_SLI_INTF_IF_TYPE_6:
2fcee4bf 8111 /* Final checks. The port status should be clean. */
9940b97b
JS
8112 if (lpfc_readl(phba->sli4_hba.u.if_type2.STATUSregaddr,
8113 &reg_data.word0) ||
0558056c
JS
8114 (bf_get(lpfc_sliport_status_err, &reg_data) &&
8115 !bf_get(lpfc_sliport_status_rn, &reg_data))) {
2fcee4bf
JS
8116 phba->work_status[0] =
8117 readl(phba->sli4_hba.u.if_type2.
8118 ERR1regaddr);
8119 phba->work_status[1] =
8120 readl(phba->sli4_hba.u.if_type2.
8121 ERR2regaddr);
372c187b 8122 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
8fcb8acd
JS
8123 "2888 Unrecoverable port error "
8124 "following POST: port status reg "
8125 "0x%x, port_smphr reg 0x%x, "
2fcee4bf
JS
8126 "error 1=0x%x, error 2=0x%x\n",
8127 reg_data.word0,
8128 portsmphr_reg.word0,
8129 phba->work_status[0],
8130 phba->work_status[1]);
8131 port_error = -ENODEV;
8132 }
8133 break;
8134 case LPFC_SLI_INTF_IF_TYPE_1:
8135 default:
8136 break;
8137 }
28baac74 8138 }
da0436e9
JS
8139 return port_error;
8140}
3772a991 8141
da0436e9
JS
8142/**
8143 * lpfc_sli4_bar0_register_memmap - Set up SLI4 BAR0 register memory map.
8144 * @phba: pointer to lpfc hba data structure.
2fcee4bf 8145 * @if_type: The SLI4 interface type getting configured.
da0436e9
JS
8146 *
8147 * This routine is invoked to set up SLI4 BAR0 PCI config space register
8148 * memory map.
8149 **/
8150static void
2fcee4bf
JS
8151lpfc_sli4_bar0_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
8152{
8153 switch (if_type) {
8154 case LPFC_SLI_INTF_IF_TYPE_0:
8155 phba->sli4_hba.u.if_type0.UERRLOregaddr =
8156 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_LO;
8157 phba->sli4_hba.u.if_type0.UERRHIregaddr =
8158 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_HI;
8159 phba->sli4_hba.u.if_type0.UEMASKLOregaddr =
8160 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_LO;
8161 phba->sli4_hba.u.if_type0.UEMASKHIregaddr =
8162 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_HI;
8163 phba->sli4_hba.SLIINTFregaddr =
8164 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
8165 break;
8166 case LPFC_SLI_INTF_IF_TYPE_2:
0cf07f84
JS
8167 phba->sli4_hba.u.if_type2.EQDregaddr =
8168 phba->sli4_hba.conf_regs_memmap_p +
8169 LPFC_CTL_PORT_EQ_DELAY_OFFSET;
2fcee4bf 8170 phba->sli4_hba.u.if_type2.ERR1regaddr =
88a2cfbb
JS
8171 phba->sli4_hba.conf_regs_memmap_p +
8172 LPFC_CTL_PORT_ER1_OFFSET;
2fcee4bf 8173 phba->sli4_hba.u.if_type2.ERR2regaddr =
88a2cfbb
JS
8174 phba->sli4_hba.conf_regs_memmap_p +
8175 LPFC_CTL_PORT_ER2_OFFSET;
2fcee4bf 8176 phba->sli4_hba.u.if_type2.CTRLregaddr =
88a2cfbb
JS
8177 phba->sli4_hba.conf_regs_memmap_p +
8178 LPFC_CTL_PORT_CTL_OFFSET;
2fcee4bf 8179 phba->sli4_hba.u.if_type2.STATUSregaddr =
88a2cfbb
JS
8180 phba->sli4_hba.conf_regs_memmap_p +
8181 LPFC_CTL_PORT_STA_OFFSET;
2fcee4bf
JS
8182 phba->sli4_hba.SLIINTFregaddr =
8183 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
8184 phba->sli4_hba.PSMPHRregaddr =
88a2cfbb
JS
8185 phba->sli4_hba.conf_regs_memmap_p +
8186 LPFC_CTL_PORT_SEM_OFFSET;
2fcee4bf 8187 phba->sli4_hba.RQDBregaddr =
962bc51b
JS
8188 phba->sli4_hba.conf_regs_memmap_p +
8189 LPFC_ULP0_RQ_DOORBELL;
2fcee4bf 8190 phba->sli4_hba.WQDBregaddr =
962bc51b
JS
8191 phba->sli4_hba.conf_regs_memmap_p +
8192 LPFC_ULP0_WQ_DOORBELL;
9dd35425 8193 phba->sli4_hba.CQDBregaddr =
2fcee4bf 8194 phba->sli4_hba.conf_regs_memmap_p + LPFC_EQCQ_DOORBELL;
9dd35425 8195 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.CQDBregaddr;
2fcee4bf
JS
8196 phba->sli4_hba.MQDBregaddr =
8197 phba->sli4_hba.conf_regs_memmap_p + LPFC_MQ_DOORBELL;
8198 phba->sli4_hba.BMBXregaddr =
8199 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
8200 break;
27d6ac0a
JS
8201 case LPFC_SLI_INTF_IF_TYPE_6:
8202 phba->sli4_hba.u.if_type2.EQDregaddr =
8203 phba->sli4_hba.conf_regs_memmap_p +
8204 LPFC_CTL_PORT_EQ_DELAY_OFFSET;
8205 phba->sli4_hba.u.if_type2.ERR1regaddr =
8206 phba->sli4_hba.conf_regs_memmap_p +
8207 LPFC_CTL_PORT_ER1_OFFSET;
8208 phba->sli4_hba.u.if_type2.ERR2regaddr =
8209 phba->sli4_hba.conf_regs_memmap_p +
8210 LPFC_CTL_PORT_ER2_OFFSET;
8211 phba->sli4_hba.u.if_type2.CTRLregaddr =
8212 phba->sli4_hba.conf_regs_memmap_p +
8213 LPFC_CTL_PORT_CTL_OFFSET;
8214 phba->sli4_hba.u.if_type2.STATUSregaddr =
8215 phba->sli4_hba.conf_regs_memmap_p +
8216 LPFC_CTL_PORT_STA_OFFSET;
8217 phba->sli4_hba.PSMPHRregaddr =
8218 phba->sli4_hba.conf_regs_memmap_p +
8219 LPFC_CTL_PORT_SEM_OFFSET;
8220 phba->sli4_hba.BMBXregaddr =
8221 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
8222 break;
2fcee4bf
JS
8223 case LPFC_SLI_INTF_IF_TYPE_1:
8224 default:
8225 dev_printk(KERN_ERR, &phba->pcidev->dev,
8226 "FATAL - unsupported SLI4 interface type - %d\n",
8227 if_type);
8228 break;
8229 }
da0436e9 8230}
3772a991 8231
da0436e9
JS
8232/**
8233 * lpfc_sli4_bar1_register_memmap - Set up SLI4 BAR1 register memory map.
8234 * @phba: pointer to lpfc hba data structure.
fe614acd 8235 * @if_type: sli if type to operate on.
da0436e9 8236 *
27d6ac0a 8237 * This routine is invoked to set up SLI4 BAR1 register memory map.
da0436e9
JS
8238 **/
8239static void
27d6ac0a 8240lpfc_sli4_bar1_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
da0436e9 8241{
27d6ac0a
JS
8242 switch (if_type) {
8243 case LPFC_SLI_INTF_IF_TYPE_0:
8244 phba->sli4_hba.PSMPHRregaddr =
8245 phba->sli4_hba.ctrl_regs_memmap_p +
8246 LPFC_SLIPORT_IF0_SMPHR;
8247 phba->sli4_hba.ISRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8248 LPFC_HST_ISR0;
8249 phba->sli4_hba.IMRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8250 LPFC_HST_IMR0;
8251 phba->sli4_hba.ISCRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8252 LPFC_HST_ISCR0;
8253 break;
8254 case LPFC_SLI_INTF_IF_TYPE_6:
8255 phba->sli4_hba.RQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8256 LPFC_IF6_RQ_DOORBELL;
8257 phba->sli4_hba.WQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8258 LPFC_IF6_WQ_DOORBELL;
8259 phba->sli4_hba.CQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8260 LPFC_IF6_CQ_DOORBELL;
8261 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8262 LPFC_IF6_EQ_DOORBELL;
8263 phba->sli4_hba.MQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8264 LPFC_IF6_MQ_DOORBELL;
8265 break;
8266 case LPFC_SLI_INTF_IF_TYPE_2:
8267 case LPFC_SLI_INTF_IF_TYPE_1:
8268 default:
8269 dev_err(&phba->pcidev->dev,
8270 "FATAL - unsupported SLI4 interface type - %d\n",
8271 if_type);
8272 break;
8273 }
3772a991
JS
8274}
8275
8276/**
da0436e9 8277 * lpfc_sli4_bar2_register_memmap - Set up SLI4 BAR2 register memory map.
3772a991 8278 * @phba: pointer to lpfc hba data structure.
da0436e9 8279 * @vf: virtual function number
3772a991 8280 *
da0436e9
JS
8281 * This routine is invoked to set up SLI4 BAR2 doorbell register memory map
8282 * based on the given viftual function number, @vf.
8283 *
8284 * Return 0 if successful, otherwise -ENODEV.
3772a991 8285 **/
da0436e9
JS
8286static int
8287lpfc_sli4_bar2_register_memmap(struct lpfc_hba *phba, uint32_t vf)
3772a991 8288{
da0436e9
JS
8289 if (vf > LPFC_VIR_FUNC_MAX)
8290 return -ENODEV;
3772a991 8291
da0436e9 8292 phba->sli4_hba.RQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
962bc51b
JS
8293 vf * LPFC_VFR_PAGE_SIZE +
8294 LPFC_ULP0_RQ_DOORBELL);
da0436e9 8295 phba->sli4_hba.WQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
962bc51b
JS
8296 vf * LPFC_VFR_PAGE_SIZE +
8297 LPFC_ULP0_WQ_DOORBELL);
9dd35425
JS
8298 phba->sli4_hba.CQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8299 vf * LPFC_VFR_PAGE_SIZE +
8300 LPFC_EQCQ_DOORBELL);
8301 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.CQDBregaddr;
da0436e9
JS
8302 phba->sli4_hba.MQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8303 vf * LPFC_VFR_PAGE_SIZE + LPFC_MQ_DOORBELL);
8304 phba->sli4_hba.BMBXregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8305 vf * LPFC_VFR_PAGE_SIZE + LPFC_BMBX);
8306 return 0;
3772a991
JS
8307}
8308
8309/**
da0436e9 8310 * lpfc_create_bootstrap_mbox - Create the bootstrap mailbox
3772a991
JS
8311 * @phba: pointer to lpfc hba data structure.
8312 *
da0436e9
JS
8313 * This routine is invoked to create the bootstrap mailbox
8314 * region consistent with the SLI-4 interface spec. This
8315 * routine allocates all memory necessary to communicate
8316 * mailbox commands to the port and sets up all alignment
8317 * needs. No locks are expected to be held when calling
8318 * this routine.
3772a991
JS
8319 *
8320 * Return codes
af901ca1 8321 * 0 - successful
d439d286 8322 * -ENOMEM - could not allocated memory.
da0436e9 8323 **/
3772a991 8324static int
da0436e9 8325lpfc_create_bootstrap_mbox(struct lpfc_hba *phba)
3772a991 8326{
da0436e9
JS
8327 uint32_t bmbx_size;
8328 struct lpfc_dmabuf *dmabuf;
8329 struct dma_address *dma_address;
8330 uint32_t pa_addr;
8331 uint64_t phys_addr;
8332
8333 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
8334 if (!dmabuf)
8335 return -ENOMEM;
3772a991 8336
da0436e9
JS
8337 /*
8338 * The bootstrap mailbox region is comprised of 2 parts
8339 * plus an alignment restriction of 16 bytes.
8340 */
8341 bmbx_size = sizeof(struct lpfc_bmbx_create) + (LPFC_ALIGN_16_BYTE - 1);
750afb08
LC
8342 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev, bmbx_size,
8343 &dmabuf->phys, GFP_KERNEL);
da0436e9
JS
8344 if (!dmabuf->virt) {
8345 kfree(dmabuf);
8346 return -ENOMEM;
3772a991
JS
8347 }
8348
da0436e9
JS
8349 /*
8350 * Initialize the bootstrap mailbox pointers now so that the register
8351 * operations are simple later. The mailbox dma address is required
8352 * to be 16-byte aligned. Also align the virtual memory as each
8353 * maibox is copied into the bmbx mailbox region before issuing the
8354 * command to the port.
8355 */
8356 phba->sli4_hba.bmbx.dmabuf = dmabuf;
8357 phba->sli4_hba.bmbx.bmbx_size = bmbx_size;
8358
8359 phba->sli4_hba.bmbx.avirt = PTR_ALIGN(dmabuf->virt,
8360 LPFC_ALIGN_16_BYTE);
8361 phba->sli4_hba.bmbx.aphys = ALIGN(dmabuf->phys,
8362 LPFC_ALIGN_16_BYTE);
8363
8364 /*
8365 * Set the high and low physical addresses now. The SLI4 alignment
8366 * requirement is 16 bytes and the mailbox is posted to the port
8367 * as two 30-bit addresses. The other data is a bit marking whether
8368 * the 30-bit address is the high or low address.
8369 * Upcast bmbx aphys to 64bits so shift instruction compiles
8370 * clean on 32 bit machines.
8371 */
8372 dma_address = &phba->sli4_hba.bmbx.dma_address;
8373 phys_addr = (uint64_t)phba->sli4_hba.bmbx.aphys;
8374 pa_addr = (uint32_t) ((phys_addr >> 34) & 0x3fffffff);
8375 dma_address->addr_hi = (uint32_t) ((pa_addr << 2) |
8376 LPFC_BMBX_BIT1_ADDR_HI);
8377
8378 pa_addr = (uint32_t) ((phba->sli4_hba.bmbx.aphys >> 4) & 0x3fffffff);
8379 dma_address->addr_lo = (uint32_t) ((pa_addr << 2) |
8380 LPFC_BMBX_BIT1_ADDR_LO);
8381 return 0;
3772a991
JS
8382}
8383
8384/**
da0436e9 8385 * lpfc_destroy_bootstrap_mbox - Destroy all bootstrap mailbox resources
3772a991
JS
8386 * @phba: pointer to lpfc hba data structure.
8387 *
da0436e9
JS
8388 * This routine is invoked to teardown the bootstrap mailbox
8389 * region and release all host resources. This routine requires
8390 * the caller to ensure all mailbox commands recovered, no
8391 * additional mailbox comands are sent, and interrupts are disabled
8392 * before calling this routine.
8393 *
8394 **/
3772a991 8395static void
da0436e9 8396lpfc_destroy_bootstrap_mbox(struct lpfc_hba *phba)
3772a991 8397{
da0436e9
JS
8398 dma_free_coherent(&phba->pcidev->dev,
8399 phba->sli4_hba.bmbx.bmbx_size,
8400 phba->sli4_hba.bmbx.dmabuf->virt,
8401 phba->sli4_hba.bmbx.dmabuf->phys);
8402
8403 kfree(phba->sli4_hba.bmbx.dmabuf);
8404 memset(&phba->sli4_hba.bmbx, 0, sizeof(struct lpfc_bmbx));
3772a991
JS
8405}
8406
83c6cb1a
JS
8407static const char * const lpfc_topo_to_str[] = {
8408 "Loop then P2P",
8409 "Loopback",
8410 "P2P Only",
8411 "Unsupported",
8412 "Loop Only",
8413 "Unsupported",
8414 "P2P then Loop",
8415};
8416
fe614acd
LJ
8417#define LINK_FLAGS_DEF 0x0
8418#define LINK_FLAGS_P2P 0x1
8419#define LINK_FLAGS_LOOP 0x2
83c6cb1a
JS
8420/**
8421 * lpfc_map_topology - Map the topology read from READ_CONFIG
8422 * @phba: pointer to lpfc hba data structure.
fe614acd 8423 * @rd_config: pointer to read config data
83c6cb1a
JS
8424 *
8425 * This routine is invoked to map the topology values as read
8426 * from the read config mailbox command. If the persistent
8427 * topology feature is supported, the firmware will provide the
8428 * saved topology information to be used in INIT_LINK
83c6cb1a 8429 **/
83c6cb1a
JS
8430static void
8431lpfc_map_topology(struct lpfc_hba *phba, struct lpfc_mbx_read_config *rd_config)
8432{
8433 u8 ptv, tf, pt;
8434
8435 ptv = bf_get(lpfc_mbx_rd_conf_ptv, rd_config);
8436 tf = bf_get(lpfc_mbx_rd_conf_tf, rd_config);
8437 pt = bf_get(lpfc_mbx_rd_conf_pt, rd_config);
8438
8439 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8440 "2027 Read Config Data : ptv:0x%x, tf:0x%x pt:0x%x",
8441 ptv, tf, pt);
8442 if (!ptv) {
8443 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
8444 "2019 FW does not support persistent topology "
8445 "Using driver parameter defined value [%s]",
8446 lpfc_topo_to_str[phba->cfg_topology]);
8447 return;
8448 }
8449 /* FW supports persistent topology - override module parameter value */
8450 phba->hba_flag |= HBA_PERSISTENT_TOPO;
8451 switch (phba->pcidev->device) {
8452 case PCI_DEVICE_ID_LANCER_G7_FC:
83c6cb1a
JS
8453 case PCI_DEVICE_ID_LANCER_G6_FC:
8454 if (!tf) {
8455 phba->cfg_topology = ((pt == LINK_FLAGS_LOOP)
8456 ? FLAGS_TOPOLOGY_MODE_LOOP
8457 : FLAGS_TOPOLOGY_MODE_PT_PT);
8458 } else {
8459 phba->hba_flag &= ~HBA_PERSISTENT_TOPO;
8460 }
8461 break;
8462 default: /* G5 */
8463 if (tf) {
8464 /* If topology failover set - pt is '0' or '1' */
8465 phba->cfg_topology = (pt ? FLAGS_TOPOLOGY_MODE_PT_LOOP :
8466 FLAGS_TOPOLOGY_MODE_LOOP_PT);
8467 } else {
8468 phba->cfg_topology = ((pt == LINK_FLAGS_P2P)
8469 ? FLAGS_TOPOLOGY_MODE_PT_PT
8470 : FLAGS_TOPOLOGY_MODE_LOOP);
8471 }
8472 break;
8473 }
8474 if (phba->hba_flag & HBA_PERSISTENT_TOPO) {
8475 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8476 "2020 Using persistent topology value [%s]",
8477 lpfc_topo_to_str[phba->cfg_topology]);
8478 } else {
8479 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
8480 "2021 Invalid topology values from FW "
8481 "Using driver parameter defined value [%s]",
8482 lpfc_topo_to_str[phba->cfg_topology]);
8483 }
8484}
8485
3772a991 8486/**
da0436e9 8487 * lpfc_sli4_read_config - Get the config parameters.
3772a991
JS
8488 * @phba: pointer to lpfc hba data structure.
8489 *
da0436e9
JS
8490 * This routine is invoked to read the configuration parameters from the HBA.
8491 * The configuration parameters are used to set the base and maximum values
8492 * for RPI's XRI's VPI's VFI's and FCFIs. These values also affect the resource
8493 * allocation for the port.
3772a991
JS
8494 *
8495 * Return codes
af901ca1 8496 * 0 - successful
25985edc 8497 * -ENOMEM - No available memory
d439d286 8498 * -EIO - The mailbox failed to complete successfully.
3772a991 8499 **/
ff78d8f9 8500int
da0436e9 8501lpfc_sli4_read_config(struct lpfc_hba *phba)
3772a991 8502{
da0436e9
JS
8503 LPFC_MBOXQ_t *pmb;
8504 struct lpfc_mbx_read_config *rd_config;
912e3acd
JS
8505 union lpfc_sli4_cfg_shdr *shdr;
8506 uint32_t shdr_status, shdr_add_status;
8507 struct lpfc_mbx_get_func_cfg *get_func_cfg;
8508 struct lpfc_rsrc_desc_fcfcoe *desc;
8aa134a8 8509 char *pdesc_0;
c691816e 8510 uint16_t forced_link_speed;
6a828b0f 8511 uint32_t if_type, qmin;
8aa134a8 8512 int length, i, rc = 0, rc2;
3772a991 8513
da0436e9
JS
8514 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
8515 if (!pmb) {
372c187b 8516 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
8517 "2011 Unable to allocate memory for issuing "
8518 "SLI_CONFIG_SPECIAL mailbox command\n");
8519 return -ENOMEM;
3772a991
JS
8520 }
8521
da0436e9 8522 lpfc_read_config(phba, pmb);
3772a991 8523
da0436e9
JS
8524 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
8525 if (rc != MBX_SUCCESS) {
372c187b
DK
8526 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
8527 "2012 Mailbox failed , mbxCmd x%x "
8528 "READ_CONFIG, mbxStatus x%x\n",
8529 bf_get(lpfc_mqe_command, &pmb->u.mqe),
8530 bf_get(lpfc_mqe_status, &pmb->u.mqe));
da0436e9
JS
8531 rc = -EIO;
8532 } else {
8533 rd_config = &pmb->u.mqe.un.rd_config;
ff78d8f9
JS
8534 if (bf_get(lpfc_mbx_rd_conf_lnk_ldv, rd_config)) {
8535 phba->sli4_hba.lnk_info.lnk_dv = LPFC_LNK_DAT_VAL;
8536 phba->sli4_hba.lnk_info.lnk_tp =
8537 bf_get(lpfc_mbx_rd_conf_lnk_type, rd_config);
8538 phba->sli4_hba.lnk_info.lnk_no =
8539 bf_get(lpfc_mbx_rd_conf_lnk_numb, rd_config);
8540 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8541 "3081 lnk_type:%d, lnk_numb:%d\n",
8542 phba->sli4_hba.lnk_info.lnk_tp,
8543 phba->sli4_hba.lnk_info.lnk_no);
8544 } else
8545 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
8546 "3082 Mailbox (x%x) returned ldv:x0\n",
8547 bf_get(lpfc_mqe_command, &pmb->u.mqe));
44fd7fe3
JS
8548 if (bf_get(lpfc_mbx_rd_conf_bbscn_def, rd_config)) {
8549 phba->bbcredit_support = 1;
8550 phba->sli4_hba.bbscn_params.word0 = rd_config->word8;
8551 }
8552
1dc5ec24
JS
8553 phba->sli4_hba.conf_trunk =
8554 bf_get(lpfc_mbx_rd_conf_trunk, rd_config);
6d368e53
JS
8555 phba->sli4_hba.extents_in_use =
8556 bf_get(lpfc_mbx_rd_conf_extnts_inuse, rd_config);
da0436e9
JS
8557 phba->sli4_hba.max_cfg_param.max_xri =
8558 bf_get(lpfc_mbx_rd_conf_xri_count, rd_config);
31f06d2e
JS
8559 /* Reduce resource usage in kdump environment */
8560 if (is_kdump_kernel() &&
8561 phba->sli4_hba.max_cfg_param.max_xri > 512)
8562 phba->sli4_hba.max_cfg_param.max_xri = 512;
da0436e9
JS
8563 phba->sli4_hba.max_cfg_param.xri_base =
8564 bf_get(lpfc_mbx_rd_conf_xri_base, rd_config);
8565 phba->sli4_hba.max_cfg_param.max_vpi =
8566 bf_get(lpfc_mbx_rd_conf_vpi_count, rd_config);
8b47ae69
JS
8567 /* Limit the max we support */
8568 if (phba->sli4_hba.max_cfg_param.max_vpi > LPFC_MAX_VPORTS)
8569 phba->sli4_hba.max_cfg_param.max_vpi = LPFC_MAX_VPORTS;
da0436e9
JS
8570 phba->sli4_hba.max_cfg_param.vpi_base =
8571 bf_get(lpfc_mbx_rd_conf_vpi_base, rd_config);
8572 phba->sli4_hba.max_cfg_param.max_rpi =
8573 bf_get(lpfc_mbx_rd_conf_rpi_count, rd_config);
8574 phba->sli4_hba.max_cfg_param.rpi_base =
8575 bf_get(lpfc_mbx_rd_conf_rpi_base, rd_config);
8576 phba->sli4_hba.max_cfg_param.max_vfi =
8577 bf_get(lpfc_mbx_rd_conf_vfi_count, rd_config);
8578 phba->sli4_hba.max_cfg_param.vfi_base =
8579 bf_get(lpfc_mbx_rd_conf_vfi_base, rd_config);
8580 phba->sli4_hba.max_cfg_param.max_fcfi =
8581 bf_get(lpfc_mbx_rd_conf_fcfi_count, rd_config);
da0436e9
JS
8582 phba->sli4_hba.max_cfg_param.max_eq =
8583 bf_get(lpfc_mbx_rd_conf_eq_count, rd_config);
8584 phba->sli4_hba.max_cfg_param.max_rq =
8585 bf_get(lpfc_mbx_rd_conf_rq_count, rd_config);
8586 phba->sli4_hba.max_cfg_param.max_wq =
8587 bf_get(lpfc_mbx_rd_conf_wq_count, rd_config);
8588 phba->sli4_hba.max_cfg_param.max_cq =
8589 bf_get(lpfc_mbx_rd_conf_cq_count, rd_config);
8590 phba->lmt = bf_get(lpfc_mbx_rd_conf_lmt, rd_config);
8591 phba->sli4_hba.next_xri = phba->sli4_hba.max_cfg_param.xri_base;
8592 phba->vpi_base = phba->sli4_hba.max_cfg_param.vpi_base;
8593 phba->vfi_base = phba->sli4_hba.max_cfg_param.vfi_base;
5ffc266e
JS
8594 phba->max_vpi = (phba->sli4_hba.max_cfg_param.max_vpi > 0) ?
8595 (phba->sli4_hba.max_cfg_param.max_vpi - 1) : 0;
da0436e9 8596 phba->max_vports = phba->max_vpi;
83c6cb1a 8597 lpfc_map_topology(phba, rd_config);
da0436e9 8598 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
6d368e53
JS
8599 "2003 cfg params Extents? %d "
8600 "XRI(B:%d M:%d), "
da0436e9
JS
8601 "VPI(B:%d M:%d) "
8602 "VFI(B:%d M:%d) "
8603 "RPI(B:%d M:%d) "
a1e4d3d8 8604 "FCFI:%d EQ:%d CQ:%d WQ:%d RQ:%d lmt:x%x\n",
6d368e53 8605 phba->sli4_hba.extents_in_use,
da0436e9
JS
8606 phba->sli4_hba.max_cfg_param.xri_base,
8607 phba->sli4_hba.max_cfg_param.max_xri,
8608 phba->sli4_hba.max_cfg_param.vpi_base,
8609 phba->sli4_hba.max_cfg_param.max_vpi,
8610 phba->sli4_hba.max_cfg_param.vfi_base,
8611 phba->sli4_hba.max_cfg_param.max_vfi,
8612 phba->sli4_hba.max_cfg_param.rpi_base,
8613 phba->sli4_hba.max_cfg_param.max_rpi,
2ea259ee
JS
8614 phba->sli4_hba.max_cfg_param.max_fcfi,
8615 phba->sli4_hba.max_cfg_param.max_eq,
8616 phba->sli4_hba.max_cfg_param.max_cq,
8617 phba->sli4_hba.max_cfg_param.max_wq,
a1e4d3d8
DK
8618 phba->sli4_hba.max_cfg_param.max_rq,
8619 phba->lmt);
2ea259ee 8620
d38f33b3 8621 /*
6a828b0f
JS
8622 * Calculate queue resources based on how
8623 * many WQ/CQ/EQs are available.
d38f33b3 8624 */
6a828b0f
JS
8625 qmin = phba->sli4_hba.max_cfg_param.max_wq;
8626 if (phba->sli4_hba.max_cfg_param.max_cq < qmin)
8627 qmin = phba->sli4_hba.max_cfg_param.max_cq;
8628 if (phba->sli4_hba.max_cfg_param.max_eq < qmin)
8629 qmin = phba->sli4_hba.max_cfg_param.max_eq;
8630 /*
8631 * Whats left after this can go toward NVME / FCP.
8632 * The minus 4 accounts for ELS, NVME LS, MBOX
8633 * plus one extra. When configured for
8634 * NVMET, FCP io channel WQs are not created.
8635 */
8636 qmin -= 4;
d38f33b3 8637
6a828b0f
JS
8638 /* Check to see if there is enough for NVME */
8639 if ((phba->cfg_irq_chann > qmin) ||
8640 (phba->cfg_hdw_queue > qmin)) {
372c187b 8641 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
9e3e365a
DK
8642 "2005 Reducing Queues - "
8643 "FW resource limitation: "
6a828b0f
JS
8644 "WQ %d CQ %d EQ %d: min %d: "
8645 "IRQ %d HDWQ %d\n",
d38f33b3
JS
8646 phba->sli4_hba.max_cfg_param.max_wq,
8647 phba->sli4_hba.max_cfg_param.max_cq,
6a828b0f
JS
8648 phba->sli4_hba.max_cfg_param.max_eq,
8649 qmin, phba->cfg_irq_chann,
cdb42bec 8650 phba->cfg_hdw_queue);
d38f33b3 8651
6a828b0f
JS
8652 if (phba->cfg_irq_chann > qmin)
8653 phba->cfg_irq_chann = qmin;
8654 if (phba->cfg_hdw_queue > qmin)
8655 phba->cfg_hdw_queue = qmin;
d38f33b3 8656 }
3772a991 8657 }
912e3acd
JS
8658
8659 if (rc)
8660 goto read_cfg_out;
da0436e9 8661
c691816e
JS
8662 /* Update link speed if forced link speed is supported */
8663 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
27d6ac0a 8664 if (if_type >= LPFC_SLI_INTF_IF_TYPE_2) {
c691816e
JS
8665 forced_link_speed =
8666 bf_get(lpfc_mbx_rd_conf_link_speed, rd_config);
8667 if (forced_link_speed) {
8668 phba->hba_flag |= HBA_FORCED_LINK_SPEED;
8669
8670 switch (forced_link_speed) {
8671 case LINK_SPEED_1G:
8672 phba->cfg_link_speed =
8673 LPFC_USER_LINK_SPEED_1G;
8674 break;
8675 case LINK_SPEED_2G:
8676 phba->cfg_link_speed =
8677 LPFC_USER_LINK_SPEED_2G;
8678 break;
8679 case LINK_SPEED_4G:
8680 phba->cfg_link_speed =
8681 LPFC_USER_LINK_SPEED_4G;
8682 break;
8683 case LINK_SPEED_8G:
8684 phba->cfg_link_speed =
8685 LPFC_USER_LINK_SPEED_8G;
8686 break;
8687 case LINK_SPEED_10G:
8688 phba->cfg_link_speed =
8689 LPFC_USER_LINK_SPEED_10G;
8690 break;
8691 case LINK_SPEED_16G:
8692 phba->cfg_link_speed =
8693 LPFC_USER_LINK_SPEED_16G;
8694 break;
8695 case LINK_SPEED_32G:
8696 phba->cfg_link_speed =
8697 LPFC_USER_LINK_SPEED_32G;
8698 break;
fbd8a6ba
JS
8699 case LINK_SPEED_64G:
8700 phba->cfg_link_speed =
8701 LPFC_USER_LINK_SPEED_64G;
8702 break;
c691816e
JS
8703 case 0xffff:
8704 phba->cfg_link_speed =
8705 LPFC_USER_LINK_SPEED_AUTO;
8706 break;
8707 default:
372c187b
DK
8708 lpfc_printf_log(phba, KERN_ERR,
8709 LOG_TRACE_EVENT,
c691816e
JS
8710 "0047 Unrecognized link "
8711 "speed : %d\n",
8712 forced_link_speed);
8713 phba->cfg_link_speed =
8714 LPFC_USER_LINK_SPEED_AUTO;
8715 }
8716 }
8717 }
8718
da0436e9 8719 /* Reset the DFT_HBA_Q_DEPTH to the max xri */
572709e2
JS
8720 length = phba->sli4_hba.max_cfg_param.max_xri -
8721 lpfc_sli4_get_els_iocb_cnt(phba);
8722 if (phba->cfg_hba_queue_depth > length) {
8723 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
8724 "3361 HBA queue depth changed from %d to %d\n",
8725 phba->cfg_hba_queue_depth, length);
8726 phba->cfg_hba_queue_depth = length;
8727 }
912e3acd 8728
27d6ac0a 8729 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) <
912e3acd
JS
8730 LPFC_SLI_INTF_IF_TYPE_2)
8731 goto read_cfg_out;
8732
8733 /* get the pf# and vf# for SLI4 if_type 2 port */
8734 length = (sizeof(struct lpfc_mbx_get_func_cfg) -
8735 sizeof(struct lpfc_sli4_cfg_mhdr));
8736 lpfc_sli4_config(phba, pmb, LPFC_MBOX_SUBSYSTEM_COMMON,
8737 LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG,
8738 length, LPFC_SLI4_MBX_EMBED);
8739
8aa134a8 8740 rc2 = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
912e3acd
JS
8741 shdr = (union lpfc_sli4_cfg_shdr *)
8742 &pmb->u.mqe.un.sli4_config.header.cfg_shdr;
8743 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
8744 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
8aa134a8 8745 if (rc2 || shdr_status || shdr_add_status) {
372c187b 8746 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
912e3acd
JS
8747 "3026 Mailbox failed , mbxCmd x%x "
8748 "GET_FUNCTION_CONFIG, mbxStatus x%x\n",
8749 bf_get(lpfc_mqe_command, &pmb->u.mqe),
8750 bf_get(lpfc_mqe_status, &pmb->u.mqe));
912e3acd
JS
8751 goto read_cfg_out;
8752 }
8753
8754 /* search for fc_fcoe resrouce descriptor */
8755 get_func_cfg = &pmb->u.mqe.un.get_func_cfg;
912e3acd 8756
8aa134a8
JS
8757 pdesc_0 = (char *)&get_func_cfg->func_cfg.desc[0];
8758 desc = (struct lpfc_rsrc_desc_fcfcoe *)pdesc_0;
8759 length = bf_get(lpfc_rsrc_desc_fcfcoe_length, desc);
8760 if (length == LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD)
8761 length = LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH;
8762 else if (length != LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH)
8763 goto read_cfg_out;
8764
912e3acd 8765 for (i = 0; i < LPFC_RSRC_DESC_MAX_NUM; i++) {
8aa134a8 8766 desc = (struct lpfc_rsrc_desc_fcfcoe *)(pdesc_0 + length * i);
912e3acd 8767 if (LPFC_RSRC_DESC_TYPE_FCFCOE ==
8aa134a8 8768 bf_get(lpfc_rsrc_desc_fcfcoe_type, desc)) {
912e3acd
JS
8769 phba->sli4_hba.iov.pf_number =
8770 bf_get(lpfc_rsrc_desc_fcfcoe_pfnum, desc);
8771 phba->sli4_hba.iov.vf_number =
8772 bf_get(lpfc_rsrc_desc_fcfcoe_vfnum, desc);
8773 break;
8774 }
8775 }
8776
8777 if (i < LPFC_RSRC_DESC_MAX_NUM)
8778 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8779 "3027 GET_FUNCTION_CONFIG: pf_number:%d, "
8780 "vf_number:%d\n", phba->sli4_hba.iov.pf_number,
8781 phba->sli4_hba.iov.vf_number);
8aa134a8 8782 else
372c187b 8783 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
912e3acd 8784 "3028 GET_FUNCTION_CONFIG: failed to find "
c4dba187 8785 "Resource Descriptor:x%x\n",
912e3acd 8786 LPFC_RSRC_DESC_TYPE_FCFCOE);
912e3acd
JS
8787
8788read_cfg_out:
8789 mempool_free(pmb, phba->mbox_mem_pool);
da0436e9 8790 return rc;
3772a991
JS
8791}
8792
8793/**
2fcee4bf 8794 * lpfc_setup_endian_order - Write endian order to an SLI4 if_type 0 port.
3772a991
JS
8795 * @phba: pointer to lpfc hba data structure.
8796 *
2fcee4bf
JS
8797 * This routine is invoked to setup the port-side endian order when
8798 * the port if_type is 0. This routine has no function for other
8799 * if_types.
da0436e9
JS
8800 *
8801 * Return codes
af901ca1 8802 * 0 - successful
25985edc 8803 * -ENOMEM - No available memory
d439d286 8804 * -EIO - The mailbox failed to complete successfully.
3772a991 8805 **/
da0436e9
JS
8806static int
8807lpfc_setup_endian_order(struct lpfc_hba *phba)
3772a991 8808{
da0436e9 8809 LPFC_MBOXQ_t *mboxq;
2fcee4bf 8810 uint32_t if_type, rc = 0;
da0436e9
JS
8811 uint32_t endian_mb_data[2] = {HOST_ENDIAN_LOW_WORD0,
8812 HOST_ENDIAN_HIGH_WORD1};
3772a991 8813
2fcee4bf
JS
8814 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
8815 switch (if_type) {
8816 case LPFC_SLI_INTF_IF_TYPE_0:
8817 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
8818 GFP_KERNEL);
8819 if (!mboxq) {
372c187b 8820 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
8821 "0492 Unable to allocate memory for "
8822 "issuing SLI_CONFIG_SPECIAL mailbox "
8823 "command\n");
8824 return -ENOMEM;
8825 }
3772a991 8826
2fcee4bf
JS
8827 /*
8828 * The SLI4_CONFIG_SPECIAL mailbox command requires the first
8829 * two words to contain special data values and no other data.
8830 */
8831 memset(mboxq, 0, sizeof(LPFC_MBOXQ_t));
8832 memcpy(&mboxq->u.mqe, &endian_mb_data, sizeof(endian_mb_data));
8833 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
8834 if (rc != MBX_SUCCESS) {
372c187b 8835 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
8836 "0493 SLI_CONFIG_SPECIAL mailbox "
8837 "failed with status x%x\n",
8838 rc);
8839 rc = -EIO;
8840 }
8841 mempool_free(mboxq, phba->mbox_mem_pool);
8842 break;
27d6ac0a 8843 case LPFC_SLI_INTF_IF_TYPE_6:
2fcee4bf
JS
8844 case LPFC_SLI_INTF_IF_TYPE_2:
8845 case LPFC_SLI_INTF_IF_TYPE_1:
8846 default:
8847 break;
da0436e9 8848 }
da0436e9 8849 return rc;
3772a991
JS
8850}
8851
8852/**
895427bd 8853 * lpfc_sli4_queue_verify - Verify and update EQ counts
3772a991
JS
8854 * @phba: pointer to lpfc hba data structure.
8855 *
895427bd
JS
8856 * This routine is invoked to check the user settable queue counts for EQs.
8857 * After this routine is called the counts will be set to valid values that
5350d872
JS
8858 * adhere to the constraints of the system's interrupt vectors and the port's
8859 * queue resources.
da0436e9
JS
8860 *
8861 * Return codes
af901ca1 8862 * 0 - successful
25985edc 8863 * -ENOMEM - No available memory
3772a991 8864 **/
da0436e9 8865static int
5350d872 8866lpfc_sli4_queue_verify(struct lpfc_hba *phba)
3772a991 8867{
da0436e9 8868 /*
67d12733 8869 * Sanity check for configured queue parameters against the run-time
da0436e9
JS
8870 * device parameters
8871 */
3772a991 8872
bcb24f65 8873 if (phba->nvmet_support) {
97a9ed3b
JS
8874 if (phba->cfg_hdw_queue < phba->cfg_nvmet_mrq)
8875 phba->cfg_nvmet_mrq = phba->cfg_hdw_queue;
982ab128
JS
8876 if (phba->cfg_nvmet_mrq > LPFC_NVMET_MRQ_MAX)
8877 phba->cfg_nvmet_mrq = LPFC_NVMET_MRQ_MAX;
bcb24f65 8878 }
895427bd
JS
8879
8880 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6a828b0f
JS
8881 "2574 IO channels: hdwQ %d IRQ %d MRQ: %d\n",
8882 phba->cfg_hdw_queue, phba->cfg_irq_chann,
8883 phba->cfg_nvmet_mrq);
3772a991 8884
da0436e9
JS
8885 /* Get EQ depth from module parameter, fake the default for now */
8886 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
8887 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
3772a991 8888
5350d872
JS
8889 /* Get CQ depth from module parameter, fake the default for now */
8890 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
8891 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
895427bd
JS
8892 return 0;
8893}
8894
8895static int
c00f62e6 8896lpfc_alloc_io_wq_cq(struct lpfc_hba *phba, int idx)
895427bd
JS
8897{
8898 struct lpfc_queue *qdesc;
c00f62e6 8899 u32 wqesize;
c1a21ebc 8900 int cpu;
895427bd 8901
c00f62e6
JS
8902 cpu = lpfc_find_cpu_handle(phba, idx, LPFC_FIND_BY_HDWQ);
8903 /* Create Fast Path IO CQs */
c176ffa0 8904 if (phba->enab_exp_wqcq_pages)
a51e41b6
JS
8905 /* Increase the CQ size when WQEs contain an embedded cdb */
8906 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
8907 phba->sli4_hba.cq_esize,
c1a21ebc 8908 LPFC_CQE_EXP_COUNT, cpu);
a51e41b6
JS
8909
8910 else
8911 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8912 phba->sli4_hba.cq_esize,
c1a21ebc 8913 phba->sli4_hba.cq_ecount, cpu);
895427bd 8914 if (!qdesc) {
372c187b
DK
8915 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
8916 "0499 Failed allocate fast-path IO CQ (%d)\n",
8917 idx);
895427bd
JS
8918 return 1;
8919 }
7365f6fd 8920 qdesc->qe_valid = 1;
c00f62e6 8921 qdesc->hdwq = idx;
c1a21ebc 8922 qdesc->chann = cpu;
c00f62e6 8923 phba->sli4_hba.hdwq[idx].io_cq = qdesc;
895427bd 8924
c00f62e6 8925 /* Create Fast Path IO WQs */
c176ffa0 8926 if (phba->enab_exp_wqcq_pages) {
a51e41b6 8927 /* Increase the WQ size when WQEs contain an embedded cdb */
c176ffa0
JS
8928 wqesize = (phba->fcp_embed_io) ?
8929 LPFC_WQE128_SIZE : phba->sli4_hba.wq_esize;
a51e41b6 8930 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
c176ffa0 8931 wqesize,
c1a21ebc 8932 LPFC_WQE_EXP_COUNT, cpu);
c176ffa0 8933 } else
a51e41b6
JS
8934 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8935 phba->sli4_hba.wq_esize,
c1a21ebc 8936 phba->sli4_hba.wq_ecount, cpu);
c176ffa0 8937
895427bd 8938 if (!qdesc) {
372c187b 8939 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
c00f62e6
JS
8940 "0503 Failed allocate fast-path IO WQ (%d)\n",
8941 idx);
895427bd
JS
8942 return 1;
8943 }
c00f62e6
JS
8944 qdesc->hdwq = idx;
8945 qdesc->chann = cpu;
8946 phba->sli4_hba.hdwq[idx].io_wq = qdesc;
895427bd 8947 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
5350d872 8948 return 0;
5350d872
JS
8949}
8950
8951/**
8952 * lpfc_sli4_queue_create - Create all the SLI4 queues
8953 * @phba: pointer to lpfc hba data structure.
8954 *
8955 * This routine is invoked to allocate all the SLI4 queues for the FCoE HBA
8956 * operation. For each SLI4 queue type, the parameters such as queue entry
8957 * count (queue depth) shall be taken from the module parameter. For now,
8958 * we just use some constant number as place holder.
8959 *
8960 * Return codes
4907cb7b 8961 * 0 - successful
5350d872
JS
8962 * -ENOMEM - No availble memory
8963 * -EIO - The mailbox failed to complete successfully.
8964 **/
8965int
8966lpfc_sli4_queue_create(struct lpfc_hba *phba)
8967{
8968 struct lpfc_queue *qdesc;
657add4e 8969 int idx, cpu, eqcpu;
5e5b511d 8970 struct lpfc_sli4_hdw_queue *qp;
657add4e
JS
8971 struct lpfc_vector_map_info *cpup;
8972 struct lpfc_vector_map_info *eqcpup;
32517fc0 8973 struct lpfc_eq_intr_info *eqi;
5350d872
JS
8974
8975 /*
67d12733 8976 * Create HBA Record arrays.
895427bd 8977 * Both NVME and FCP will share that same vectors / EQs
5350d872 8978 */
67d12733
JS
8979 phba->sli4_hba.mq_esize = LPFC_MQE_SIZE;
8980 phba->sli4_hba.mq_ecount = LPFC_MQE_DEF_COUNT;
8981 phba->sli4_hba.wq_esize = LPFC_WQE_SIZE;
8982 phba->sli4_hba.wq_ecount = LPFC_WQE_DEF_COUNT;
8983 phba->sli4_hba.rq_esize = LPFC_RQE_SIZE;
8984 phba->sli4_hba.rq_ecount = LPFC_RQE_DEF_COUNT;
895427bd
JS
8985 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
8986 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
8987 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
8988 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
67d12733 8989
cdb42bec 8990 if (!phba->sli4_hba.hdwq) {
5e5b511d
JS
8991 phba->sli4_hba.hdwq = kcalloc(
8992 phba->cfg_hdw_queue, sizeof(struct lpfc_sli4_hdw_queue),
8993 GFP_KERNEL);
8994 if (!phba->sli4_hba.hdwq) {
372c187b 8995 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5e5b511d
JS
8996 "6427 Failed allocate memory for "
8997 "fast-path Hardware Queue array\n");
895427bd
JS
8998 goto out_error;
8999 }
5e5b511d
JS
9000 /* Prepare hardware queues to take IO buffers */
9001 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9002 qp = &phba->sli4_hba.hdwq[idx];
9003 spin_lock_init(&qp->io_buf_list_get_lock);
9004 spin_lock_init(&qp->io_buf_list_put_lock);
9005 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_get);
9006 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_put);
9007 qp->get_io_bufs = 0;
9008 qp->put_io_bufs = 0;
9009 qp->total_io_bufs = 0;
c00f62e6
JS
9010 spin_lock_init(&qp->abts_io_buf_list_lock);
9011 INIT_LIST_HEAD(&qp->lpfc_abts_io_buf_list);
5e5b511d 9012 qp->abts_scsi_io_bufs = 0;
5e5b511d 9013 qp->abts_nvme_io_bufs = 0;
d79c9e9d
JS
9014 INIT_LIST_HEAD(&qp->sgl_list);
9015 INIT_LIST_HEAD(&qp->cmd_rsp_buf_list);
9016 spin_lock_init(&qp->hdwq_lock);
895427bd 9017 }
67d12733
JS
9018 }
9019
cdb42bec 9020 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
2d7dbc4c
JS
9021 if (phba->nvmet_support) {
9022 phba->sli4_hba.nvmet_cqset = kcalloc(
9023 phba->cfg_nvmet_mrq,
9024 sizeof(struct lpfc_queue *),
9025 GFP_KERNEL);
9026 if (!phba->sli4_hba.nvmet_cqset) {
372c187b 9027 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9028 "3121 Fail allocate memory for "
9029 "fast-path CQ set array\n");
9030 goto out_error;
9031 }
9032 phba->sli4_hba.nvmet_mrq_hdr = kcalloc(
9033 phba->cfg_nvmet_mrq,
9034 sizeof(struct lpfc_queue *),
9035 GFP_KERNEL);
9036 if (!phba->sli4_hba.nvmet_mrq_hdr) {
372c187b 9037 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9038 "3122 Fail allocate memory for "
9039 "fast-path RQ set hdr array\n");
9040 goto out_error;
9041 }
9042 phba->sli4_hba.nvmet_mrq_data = kcalloc(
9043 phba->cfg_nvmet_mrq,
9044 sizeof(struct lpfc_queue *),
9045 GFP_KERNEL);
9046 if (!phba->sli4_hba.nvmet_mrq_data) {
372c187b 9047 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9048 "3124 Fail allocate memory for "
9049 "fast-path RQ set data array\n");
9050 goto out_error;
9051 }
9052 }
da0436e9 9053 }
67d12733 9054
895427bd 9055 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
67d12733 9056
895427bd 9057 /* Create HBA Event Queues (EQs) */
657add4e
JS
9058 for_each_present_cpu(cpu) {
9059 /* We only want to create 1 EQ per vector, even though
9060 * multiple CPUs might be using that vector. so only
9061 * selects the CPUs that are LPFC_CPU_FIRST_IRQ.
6a828b0f 9062 */
657add4e
JS
9063 cpup = &phba->sli4_hba.cpu_map[cpu];
9064 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
6a828b0f 9065 continue;
657add4e
JS
9066
9067 /* Get a ptr to the Hardware Queue associated with this CPU */
9068 qp = &phba->sli4_hba.hdwq[cpup->hdwq];
9069
9070 /* Allocate an EQ */
81b96eda
JS
9071 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9072 phba->sli4_hba.eq_esize,
c1a21ebc 9073 phba->sli4_hba.eq_ecount, cpu);
da0436e9 9074 if (!qdesc) {
372c187b 9075 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
657add4e
JS
9076 "0497 Failed allocate EQ (%d)\n",
9077 cpup->hdwq);
67d12733 9078 goto out_error;
da0436e9 9079 }
7365f6fd 9080 qdesc->qe_valid = 1;
657add4e 9081 qdesc->hdwq = cpup->hdwq;
3ad348d9 9082 qdesc->chann = cpu; /* First CPU this EQ is affinitized to */
32517fc0 9083 qdesc->last_cpu = qdesc->chann;
657add4e
JS
9084
9085 /* Save the allocated EQ in the Hardware Queue */
9086 qp->hba_eq = qdesc;
9087
32517fc0
JS
9088 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, qdesc->last_cpu);
9089 list_add(&qdesc->cpu_list, &eqi->list);
895427bd 9090 }
67d12733 9091
657add4e
JS
9092 /* Now we need to populate the other Hardware Queues, that share
9093 * an IRQ vector, with the associated EQ ptr.
9094 */
9095 for_each_present_cpu(cpu) {
9096 cpup = &phba->sli4_hba.cpu_map[cpu];
9097
9098 /* Check for EQ already allocated in previous loop */
9099 if (cpup->flag & LPFC_CPU_FIRST_IRQ)
9100 continue;
9101
9102 /* Check for multiple CPUs per hdwq */
9103 qp = &phba->sli4_hba.hdwq[cpup->hdwq];
9104 if (qp->hba_eq)
9105 continue;
9106
9107 /* We need to share an EQ for this hdwq */
9108 eqcpu = lpfc_find_cpu_handle(phba, cpup->eq, LPFC_FIND_BY_EQ);
9109 eqcpup = &phba->sli4_hba.cpu_map[eqcpu];
9110 qp->hba_eq = phba->sli4_hba.hdwq[eqcpup->hdwq].hba_eq;
9111 }
67d12733 9112
c00f62e6 9113 /* Allocate IO Path SLI4 CQ/WQs */
6a828b0f 9114 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
c00f62e6 9115 if (lpfc_alloc_io_wq_cq(phba, idx))
67d12733 9116 goto out_error;
6a828b0f 9117 }
da0436e9 9118
c00f62e6
JS
9119 if (phba->nvmet_support) {
9120 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
9121 cpu = lpfc_find_cpu_handle(phba, idx,
9122 LPFC_FIND_BY_HDWQ);
9123 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda
JS
9124 LPFC_DEFAULT_PAGE_SIZE,
9125 phba->sli4_hba.cq_esize,
c1a21ebc
JS
9126 phba->sli4_hba.cq_ecount,
9127 cpu);
c00f62e6 9128 if (!qdesc) {
372c187b 9129 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
cdb42bec
JS
9130 "3142 Failed allocate NVME "
9131 "CQ Set (%d)\n", idx);
c00f62e6 9132 goto out_error;
2d7dbc4c 9133 }
c00f62e6
JS
9134 qdesc->qe_valid = 1;
9135 qdesc->hdwq = idx;
9136 qdesc->chann = cpu;
9137 phba->sli4_hba.nvmet_cqset[idx] = qdesc;
2d7dbc4c
JS
9138 }
9139 }
9140
da0436e9 9141 /*
67d12733 9142 * Create Slow Path Completion Queues (CQs)
da0436e9
JS
9143 */
9144
c1a21ebc 9145 cpu = lpfc_find_cpu_handle(phba, 0, LPFC_FIND_BY_EQ);
da0436e9 9146 /* Create slow-path Mailbox Command Complete Queue */
81b96eda
JS
9147 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9148 phba->sli4_hba.cq_esize,
c1a21ebc 9149 phba->sli4_hba.cq_ecount, cpu);
da0436e9 9150 if (!qdesc) {
372c187b 9151 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9152 "0500 Failed allocate slow-path mailbox CQ\n");
67d12733 9153 goto out_error;
da0436e9 9154 }
7365f6fd 9155 qdesc->qe_valid = 1;
da0436e9
JS
9156 phba->sli4_hba.mbx_cq = qdesc;
9157
9158 /* Create slow-path ELS Complete Queue */
81b96eda
JS
9159 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9160 phba->sli4_hba.cq_esize,
c1a21ebc 9161 phba->sli4_hba.cq_ecount, cpu);
da0436e9 9162 if (!qdesc) {
372c187b 9163 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9164 "0501 Failed allocate slow-path ELS CQ\n");
67d12733 9165 goto out_error;
da0436e9 9166 }
7365f6fd 9167 qdesc->qe_valid = 1;
c00f62e6 9168 qdesc->chann = cpu;
da0436e9
JS
9169 phba->sli4_hba.els_cq = qdesc;
9170
da0436e9 9171
5350d872 9172 /*
67d12733 9173 * Create Slow Path Work Queues (WQs)
5350d872 9174 */
da0436e9
JS
9175
9176 /* Create Mailbox Command Queue */
da0436e9 9177
81b96eda
JS
9178 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9179 phba->sli4_hba.mq_esize,
c1a21ebc 9180 phba->sli4_hba.mq_ecount, cpu);
da0436e9 9181 if (!qdesc) {
372c187b 9182 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9183 "0505 Failed allocate slow-path MQ\n");
67d12733 9184 goto out_error;
da0436e9 9185 }
c00f62e6 9186 qdesc->chann = cpu;
da0436e9
JS
9187 phba->sli4_hba.mbx_wq = qdesc;
9188
9189 /*
67d12733 9190 * Create ELS Work Queues
da0436e9 9191 */
da0436e9
JS
9192
9193 /* Create slow-path ELS Work Queue */
81b96eda
JS
9194 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9195 phba->sli4_hba.wq_esize,
c1a21ebc 9196 phba->sli4_hba.wq_ecount, cpu);
da0436e9 9197 if (!qdesc) {
372c187b 9198 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9199 "0504 Failed allocate slow-path ELS WQ\n");
67d12733 9200 goto out_error;
da0436e9 9201 }
c00f62e6 9202 qdesc->chann = cpu;
da0436e9 9203 phba->sli4_hba.els_wq = qdesc;
895427bd
JS
9204 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
9205
9206 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
9207 /* Create NVME LS Complete Queue */
81b96eda
JS
9208 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9209 phba->sli4_hba.cq_esize,
c1a21ebc 9210 phba->sli4_hba.cq_ecount, cpu);
895427bd 9211 if (!qdesc) {
372c187b 9212 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9213 "6079 Failed allocate NVME LS CQ\n");
9214 goto out_error;
9215 }
c00f62e6 9216 qdesc->chann = cpu;
7365f6fd 9217 qdesc->qe_valid = 1;
895427bd
JS
9218 phba->sli4_hba.nvmels_cq = qdesc;
9219
9220 /* Create NVME LS Work Queue */
81b96eda
JS
9221 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9222 phba->sli4_hba.wq_esize,
c1a21ebc 9223 phba->sli4_hba.wq_ecount, cpu);
895427bd 9224 if (!qdesc) {
372c187b 9225 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9226 "6080 Failed allocate NVME LS WQ\n");
9227 goto out_error;
9228 }
c00f62e6 9229 qdesc->chann = cpu;
895427bd
JS
9230 phba->sli4_hba.nvmels_wq = qdesc;
9231 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
9232 }
da0436e9 9233
da0436e9
JS
9234 /*
9235 * Create Receive Queue (RQ)
9236 */
da0436e9
JS
9237
9238 /* Create Receive Queue for header */
81b96eda
JS
9239 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9240 phba->sli4_hba.rq_esize,
c1a21ebc 9241 phba->sli4_hba.rq_ecount, cpu);
da0436e9 9242 if (!qdesc) {
372c187b 9243 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9244 "0506 Failed allocate receive HRQ\n");
67d12733 9245 goto out_error;
da0436e9
JS
9246 }
9247 phba->sli4_hba.hdr_rq = qdesc;
9248
9249 /* Create Receive Queue for data */
81b96eda
JS
9250 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9251 phba->sli4_hba.rq_esize,
c1a21ebc 9252 phba->sli4_hba.rq_ecount, cpu);
da0436e9 9253 if (!qdesc) {
372c187b 9254 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9255 "0507 Failed allocate receive DRQ\n");
67d12733 9256 goto out_error;
da0436e9
JS
9257 }
9258 phba->sli4_hba.dat_rq = qdesc;
9259
cdb42bec
JS
9260 if ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) &&
9261 phba->nvmet_support) {
2d7dbc4c 9262 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
c1a21ebc
JS
9263 cpu = lpfc_find_cpu_handle(phba, idx,
9264 LPFC_FIND_BY_HDWQ);
2d7dbc4c
JS
9265 /* Create NVMET Receive Queue for header */
9266 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda 9267 LPFC_DEFAULT_PAGE_SIZE,
2d7dbc4c 9268 phba->sli4_hba.rq_esize,
c1a21ebc
JS
9269 LPFC_NVMET_RQE_DEF_COUNT,
9270 cpu);
2d7dbc4c 9271 if (!qdesc) {
372c187b 9272 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9273 "3146 Failed allocate "
9274 "receive HRQ\n");
9275 goto out_error;
9276 }
5e5b511d 9277 qdesc->hdwq = idx;
2d7dbc4c
JS
9278 phba->sli4_hba.nvmet_mrq_hdr[idx] = qdesc;
9279
9280 /* Only needed for header of RQ pair */
c1a21ebc
JS
9281 qdesc->rqbp = kzalloc_node(sizeof(*qdesc->rqbp),
9282 GFP_KERNEL,
9283 cpu_to_node(cpu));
2d7dbc4c 9284 if (qdesc->rqbp == NULL) {
372c187b 9285 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9286 "6131 Failed allocate "
9287 "Header RQBP\n");
9288 goto out_error;
9289 }
9290
4b40d02b
DK
9291 /* Put list in known state in case driver load fails. */
9292 INIT_LIST_HEAD(&qdesc->rqbp->rqb_buffer_list);
9293
2d7dbc4c
JS
9294 /* Create NVMET Receive Queue for data */
9295 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda 9296 LPFC_DEFAULT_PAGE_SIZE,
2d7dbc4c 9297 phba->sli4_hba.rq_esize,
c1a21ebc
JS
9298 LPFC_NVMET_RQE_DEF_COUNT,
9299 cpu);
2d7dbc4c 9300 if (!qdesc) {
372c187b 9301 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9302 "3156 Failed allocate "
9303 "receive DRQ\n");
9304 goto out_error;
9305 }
5e5b511d 9306 qdesc->hdwq = idx;
2d7dbc4c
JS
9307 phba->sli4_hba.nvmet_mrq_data[idx] = qdesc;
9308 }
9309 }
9310
4c47efc1
JS
9311 /* Clear NVME stats */
9312 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
9313 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9314 memset(&phba->sli4_hba.hdwq[idx].nvme_cstat, 0,
9315 sizeof(phba->sli4_hba.hdwq[idx].nvme_cstat));
9316 }
9317 }
4c47efc1
JS
9318
9319 /* Clear SCSI stats */
9320 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
9321 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9322 memset(&phba->sli4_hba.hdwq[idx].scsi_cstat, 0,
9323 sizeof(phba->sli4_hba.hdwq[idx].scsi_cstat));
9324 }
9325 }
9326
da0436e9
JS
9327 return 0;
9328
da0436e9 9329out_error:
67d12733 9330 lpfc_sli4_queue_destroy(phba);
da0436e9
JS
9331 return -ENOMEM;
9332}
9333
895427bd
JS
9334static inline void
9335__lpfc_sli4_release_queue(struct lpfc_queue **qp)
9336{
9337 if (*qp != NULL) {
9338 lpfc_sli4_queue_free(*qp);
9339 *qp = NULL;
9340 }
9341}
9342
9343static inline void
9344lpfc_sli4_release_queues(struct lpfc_queue ***qs, int max)
9345{
9346 int idx;
9347
9348 if (*qs == NULL)
9349 return;
9350
9351 for (idx = 0; idx < max; idx++)
9352 __lpfc_sli4_release_queue(&(*qs)[idx]);
9353
9354 kfree(*qs);
9355 *qs = NULL;
9356}
9357
9358static inline void
6a828b0f 9359lpfc_sli4_release_hdwq(struct lpfc_hba *phba)
895427bd 9360{
6a828b0f 9361 struct lpfc_sli4_hdw_queue *hdwq;
657add4e 9362 struct lpfc_queue *eq;
cdb42bec
JS
9363 uint32_t idx;
9364
6a828b0f 9365 hdwq = phba->sli4_hba.hdwq;
6a828b0f 9366
657add4e
JS
9367 /* Loop thru all Hardware Queues */
9368 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9369 /* Free the CQ/WQ corresponding to the Hardware Queue */
c00f62e6
JS
9370 lpfc_sli4_queue_free(hdwq[idx].io_cq);
9371 lpfc_sli4_queue_free(hdwq[idx].io_wq);
821bc882 9372 hdwq[idx].hba_eq = NULL;
c00f62e6
JS
9373 hdwq[idx].io_cq = NULL;
9374 hdwq[idx].io_wq = NULL;
d79c9e9d
JS
9375 if (phba->cfg_xpsgl && !phba->nvmet_support)
9376 lpfc_free_sgl_per_hdwq(phba, &hdwq[idx]);
9377 lpfc_free_cmd_rsp_buf_per_hdwq(phba, &hdwq[idx]);
895427bd 9378 }
657add4e
JS
9379 /* Loop thru all IRQ vectors */
9380 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
9381 /* Free the EQ corresponding to the IRQ vector */
9382 eq = phba->sli4_hba.hba_eq_hdl[idx].eq;
9383 lpfc_sli4_queue_free(eq);
9384 phba->sli4_hba.hba_eq_hdl[idx].eq = NULL;
9385 }
895427bd
JS
9386}
9387
da0436e9
JS
9388/**
9389 * lpfc_sli4_queue_destroy - Destroy all the SLI4 queues
9390 * @phba: pointer to lpfc hba data structure.
9391 *
9392 * This routine is invoked to release all the SLI4 queues with the FCoE HBA
9393 * operation.
9394 *
9395 * Return codes
af901ca1 9396 * 0 - successful
25985edc 9397 * -ENOMEM - No available memory
d439d286 9398 * -EIO - The mailbox failed to complete successfully.
da0436e9 9399 **/
5350d872 9400void
da0436e9
JS
9401lpfc_sli4_queue_destroy(struct lpfc_hba *phba)
9402{
4645f7b5
JS
9403 /*
9404 * Set FREE_INIT before beginning to free the queues.
9405 * Wait until the users of queues to acknowledge to
9406 * release queues by clearing FREE_WAIT.
9407 */
9408 spin_lock_irq(&phba->hbalock);
9409 phba->sli.sli_flag |= LPFC_QUEUE_FREE_INIT;
9410 while (phba->sli.sli_flag & LPFC_QUEUE_FREE_WAIT) {
9411 spin_unlock_irq(&phba->hbalock);
9412 msleep(20);
9413 spin_lock_irq(&phba->hbalock);
9414 }
9415 spin_unlock_irq(&phba->hbalock);
9416
93a4d6f4
JS
9417 lpfc_sli4_cleanup_poll_list(phba);
9418
895427bd 9419 /* Release HBA eqs */
cdb42bec 9420 if (phba->sli4_hba.hdwq)
6a828b0f 9421 lpfc_sli4_release_hdwq(phba);
895427bd 9422
bcb24f65
JS
9423 if (phba->nvmet_support) {
9424 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_cqset,
9425 phba->cfg_nvmet_mrq);
2d7dbc4c 9426
bcb24f65
JS
9427 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_hdr,
9428 phba->cfg_nvmet_mrq);
9429 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_data,
9430 phba->cfg_nvmet_mrq);
9431 }
2d7dbc4c 9432
895427bd
JS
9433 /* Release mailbox command work queue */
9434 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_wq);
9435
9436 /* Release ELS work queue */
9437 __lpfc_sli4_release_queue(&phba->sli4_hba.els_wq);
9438
9439 /* Release ELS work queue */
9440 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_wq);
9441
9442 /* Release unsolicited receive queue */
9443 __lpfc_sli4_release_queue(&phba->sli4_hba.hdr_rq);
9444 __lpfc_sli4_release_queue(&phba->sli4_hba.dat_rq);
9445
9446 /* Release ELS complete queue */
9447 __lpfc_sli4_release_queue(&phba->sli4_hba.els_cq);
9448
9449 /* Release NVME LS complete queue */
9450 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_cq);
9451
9452 /* Release mailbox command complete queue */
9453 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_cq);
9454
9455 /* Everything on this list has been freed */
9456 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
4645f7b5
JS
9457
9458 /* Done with freeing the queues */
9459 spin_lock_irq(&phba->hbalock);
9460 phba->sli.sli_flag &= ~LPFC_QUEUE_FREE_INIT;
9461 spin_unlock_irq(&phba->hbalock);
895427bd
JS
9462}
9463
895427bd
JS
9464int
9465lpfc_free_rq_buffer(struct lpfc_hba *phba, struct lpfc_queue *rq)
9466{
9467 struct lpfc_rqb *rqbp;
9468 struct lpfc_dmabuf *h_buf;
9469 struct rqb_dmabuf *rqb_buffer;
9470
9471 rqbp = rq->rqbp;
9472 while (!list_empty(&rqbp->rqb_buffer_list)) {
9473 list_remove_head(&rqbp->rqb_buffer_list, h_buf,
9474 struct lpfc_dmabuf, list);
9475
9476 rqb_buffer = container_of(h_buf, struct rqb_dmabuf, hbuf);
9477 (rqbp->rqb_free_buffer)(phba, rqb_buffer);
9478 rqbp->buffer_count--;
67d12733 9479 }
895427bd
JS
9480 return 1;
9481}
67d12733 9482
895427bd
JS
9483static int
9484lpfc_create_wq_cq(struct lpfc_hba *phba, struct lpfc_queue *eq,
9485 struct lpfc_queue *cq, struct lpfc_queue *wq, uint16_t *cq_map,
9486 int qidx, uint32_t qtype)
9487{
9488 struct lpfc_sli_ring *pring;
9489 int rc;
9490
9491 if (!eq || !cq || !wq) {
372c187b 9492 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9493 "6085 Fast-path %s (%d) not allocated\n",
9494 ((eq) ? ((cq) ? "WQ" : "CQ") : "EQ"), qidx);
9495 return -ENOMEM;
9496 }
9497
9498 /* create the Cq first */
9499 rc = lpfc_cq_create(phba, cq, eq,
9500 (qtype == LPFC_MBOX) ? LPFC_MCQ : LPFC_WCQ, qtype);
9501 if (rc) {
372c187b
DK
9502 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
9503 "6086 Failed setup of CQ (%d), rc = 0x%x\n",
9504 qidx, (uint32_t)rc);
895427bd 9505 return rc;
67d12733
JS
9506 }
9507
895427bd 9508 if (qtype != LPFC_MBOX) {
cdb42bec 9509 /* Setup cq_map for fast lookup */
895427bd
JS
9510 if (cq_map)
9511 *cq_map = cq->queue_id;
da0436e9 9512
895427bd
JS
9513 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9514 "6087 CQ setup: cq[%d]-id=%d, parent eq[%d]-id=%d\n",
9515 qidx, cq->queue_id, qidx, eq->queue_id);
da0436e9 9516
895427bd
JS
9517 /* create the wq */
9518 rc = lpfc_wq_create(phba, wq, cq, qtype);
9519 if (rc) {
372c187b 9520 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
c835c085 9521 "4618 Fail setup fastpath WQ (%d), rc = 0x%x\n",
895427bd
JS
9522 qidx, (uint32_t)rc);
9523 /* no need to tear down cq - caller will do so */
9524 return rc;
9525 }
da0436e9 9526
895427bd
JS
9527 /* Bind this CQ/WQ to the NVME ring */
9528 pring = wq->pring;
9529 pring->sli.sli4.wqp = (void *)wq;
9530 cq->pring = pring;
da0436e9 9531
895427bd
JS
9532 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9533 "2593 WQ setup: wq[%d]-id=%d assoc=%d, cq[%d]-id=%d\n",
9534 qidx, wq->queue_id, wq->assoc_qid, qidx, cq->queue_id);
9535 } else {
9536 rc = lpfc_mq_create(phba, wq, cq, LPFC_MBOX);
9537 if (rc) {
372c187b
DK
9538 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
9539 "0539 Failed setup of slow-path MQ: "
9540 "rc = 0x%x\n", rc);
895427bd
JS
9541 /* no need to tear down cq - caller will do so */
9542 return rc;
9543 }
da0436e9 9544
895427bd
JS
9545 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9546 "2589 MBX MQ setup: wq-id=%d, parent cq-id=%d\n",
9547 phba->sli4_hba.mbx_wq->queue_id,
9548 phba->sli4_hba.mbx_cq->queue_id);
67d12733 9549 }
da0436e9 9550
895427bd 9551 return 0;
da0436e9
JS
9552}
9553
6a828b0f
JS
9554/**
9555 * lpfc_setup_cq_lookup - Setup the CQ lookup table
9556 * @phba: pointer to lpfc hba data structure.
9557 *
9558 * This routine will populate the cq_lookup table by all
9559 * available CQ queue_id's.
9560 **/
3999df75 9561static void
6a828b0f
JS
9562lpfc_setup_cq_lookup(struct lpfc_hba *phba)
9563{
9564 struct lpfc_queue *eq, *childq;
6a828b0f
JS
9565 int qidx;
9566
6a828b0f
JS
9567 memset(phba->sli4_hba.cq_lookup, 0,
9568 (sizeof(struct lpfc_queue *) * (phba->sli4_hba.cq_max + 1)));
657add4e 9569 /* Loop thru all IRQ vectors */
6a828b0f 9570 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
657add4e
JS
9571 /* Get the EQ corresponding to the IRQ vector */
9572 eq = phba->sli4_hba.hba_eq_hdl[qidx].eq;
6a828b0f
JS
9573 if (!eq)
9574 continue;
657add4e 9575 /* Loop through all CQs associated with that EQ */
6a828b0f
JS
9576 list_for_each_entry(childq, &eq->child_list, list) {
9577 if (childq->queue_id > phba->sli4_hba.cq_max)
9578 continue;
c00f62e6 9579 if (childq->subtype == LPFC_IO)
6a828b0f
JS
9580 phba->sli4_hba.cq_lookup[childq->queue_id] =
9581 childq;
9582 }
9583 }
9584}
9585
da0436e9
JS
9586/**
9587 * lpfc_sli4_queue_setup - Set up all the SLI4 queues
9588 * @phba: pointer to lpfc hba data structure.
9589 *
9590 * This routine is invoked to set up all the SLI4 queues for the FCoE HBA
9591 * operation.
9592 *
9593 * Return codes
af901ca1 9594 * 0 - successful
25985edc 9595 * -ENOMEM - No available memory
d439d286 9596 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
9597 **/
9598int
9599lpfc_sli4_queue_setup(struct lpfc_hba *phba)
9600{
962bc51b
JS
9601 uint32_t shdr_status, shdr_add_status;
9602 union lpfc_sli4_cfg_shdr *shdr;
657add4e 9603 struct lpfc_vector_map_info *cpup;
cdb42bec 9604 struct lpfc_sli4_hdw_queue *qp;
962bc51b 9605 LPFC_MBOXQ_t *mboxq;
657add4e 9606 int qidx, cpu;
cb733e35 9607 uint32_t length, usdelay;
895427bd 9608 int rc = -ENOMEM;
962bc51b
JS
9609
9610 /* Check for dual-ULP support */
9611 mboxq = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9612 if (!mboxq) {
372c187b 9613 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
962bc51b
JS
9614 "3249 Unable to allocate memory for "
9615 "QUERY_FW_CFG mailbox command\n");
9616 return -ENOMEM;
9617 }
9618 length = (sizeof(struct lpfc_mbx_query_fw_config) -
9619 sizeof(struct lpfc_sli4_cfg_mhdr));
9620 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
9621 LPFC_MBOX_OPCODE_QUERY_FW_CFG,
9622 length, LPFC_SLI4_MBX_EMBED);
9623
9624 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
9625
9626 shdr = (union lpfc_sli4_cfg_shdr *)
9627 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
9628 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
9629 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
9630 if (shdr_status || shdr_add_status || rc) {
372c187b 9631 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
962bc51b
JS
9632 "3250 QUERY_FW_CFG mailbox failed with status "
9633 "x%x add_status x%x, mbx status x%x\n",
9634 shdr_status, shdr_add_status, rc);
9635 if (rc != MBX_TIMEOUT)
9636 mempool_free(mboxq, phba->mbox_mem_pool);
9637 rc = -ENXIO;
9638 goto out_error;
9639 }
9640
9641 phba->sli4_hba.fw_func_mode =
9642 mboxq->u.mqe.un.query_fw_cfg.rsp.function_mode;
9643 phba->sli4_hba.ulp0_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp0_mode;
9644 phba->sli4_hba.ulp1_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp1_mode;
8b017a30
JS
9645 phba->sli4_hba.physical_port =
9646 mboxq->u.mqe.un.query_fw_cfg.rsp.physical_port;
962bc51b
JS
9647 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9648 "3251 QUERY_FW_CFG: func_mode:x%x, ulp0_mode:x%x, "
9649 "ulp1_mode:x%x\n", phba->sli4_hba.fw_func_mode,
9650 phba->sli4_hba.ulp0_mode, phba->sli4_hba.ulp1_mode);
9651
9652 if (rc != MBX_TIMEOUT)
9653 mempool_free(mboxq, phba->mbox_mem_pool);
da0436e9
JS
9654
9655 /*
67d12733 9656 * Set up HBA Event Queues (EQs)
da0436e9 9657 */
cdb42bec 9658 qp = phba->sli4_hba.hdwq;
da0436e9 9659
67d12733 9660 /* Set up HBA event queue */
cdb42bec 9661 if (!qp) {
372c187b 9662 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2e90f4b5 9663 "3147 Fast-path EQs not allocated\n");
1b51197d 9664 rc = -ENOMEM;
67d12733 9665 goto out_error;
2e90f4b5 9666 }
657add4e
JS
9667
9668 /* Loop thru all IRQ vectors */
6a828b0f 9669 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
657add4e
JS
9670 /* Create HBA Event Queues (EQs) in order */
9671 for_each_present_cpu(cpu) {
9672 cpup = &phba->sli4_hba.cpu_map[cpu];
9673
9674 /* Look for the CPU thats using that vector with
9675 * LPFC_CPU_FIRST_IRQ set.
9676 */
9677 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
9678 continue;
9679 if (qidx != cpup->eq)
9680 continue;
9681
9682 /* Create an EQ for that vector */
9683 rc = lpfc_eq_create(phba, qp[cpup->hdwq].hba_eq,
9684 phba->cfg_fcp_imax);
9685 if (rc) {
372c187b 9686 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
657add4e
JS
9687 "0523 Failed setup of fast-path"
9688 " EQ (%d), rc = 0x%x\n",
9689 cpup->eq, (uint32_t)rc);
9690 goto out_destroy;
9691 }
9692
9693 /* Save the EQ for that vector in the hba_eq_hdl */
9694 phba->sli4_hba.hba_eq_hdl[cpup->eq].eq =
9695 qp[cpup->hdwq].hba_eq;
9696
9697 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9698 "2584 HBA EQ setup: queue[%d]-id=%d\n",
9699 cpup->eq,
9700 qp[cpup->hdwq].hba_eq->queue_id);
da0436e9 9701 }
67d12733
JS
9702 }
9703
657add4e 9704 /* Loop thru all Hardware Queues */
cdb42bec 9705 for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {
657add4e
JS
9706 cpu = lpfc_find_cpu_handle(phba, qidx, LPFC_FIND_BY_HDWQ);
9707 cpup = &phba->sli4_hba.cpu_map[cpu];
9708
9709 /* Create the CQ/WQ corresponding to the Hardware Queue */
cdb42bec 9710 rc = lpfc_create_wq_cq(phba,
657add4e 9711 phba->sli4_hba.hdwq[cpup->hdwq].hba_eq,
c00f62e6
JS
9712 qp[qidx].io_cq,
9713 qp[qidx].io_wq,
9714 &phba->sli4_hba.hdwq[qidx].io_cq_map,
9715 qidx,
9716 LPFC_IO);
cdb42bec 9717 if (rc) {
372c187b 9718 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd 9719 "0535 Failed to setup fastpath "
c00f62e6 9720 "IO WQ/CQ (%d), rc = 0x%x\n",
895427bd 9721 qidx, (uint32_t)rc);
cdb42bec 9722 goto out_destroy;
895427bd 9723 }
67d12733 9724 }
895427bd 9725
da0436e9 9726 /*
895427bd 9727 * Set up Slow Path Complete Queues (CQs)
da0436e9
JS
9728 */
9729
895427bd 9730 /* Set up slow-path MBOX CQ/MQ */
da0436e9 9731
895427bd 9732 if (!phba->sli4_hba.mbx_cq || !phba->sli4_hba.mbx_wq) {
372c187b 9733 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9734 "0528 %s not allocated\n",
9735 phba->sli4_hba.mbx_cq ?
d1f525aa 9736 "Mailbox WQ" : "Mailbox CQ");
1b51197d 9737 rc = -ENOMEM;
895427bd 9738 goto out_destroy;
da0436e9 9739 }
da0436e9 9740
cdb42bec 9741 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
d1f525aa
JS
9742 phba->sli4_hba.mbx_cq,
9743 phba->sli4_hba.mbx_wq,
9744 NULL, 0, LPFC_MBOX);
da0436e9 9745 if (rc) {
372c187b 9746 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9747 "0529 Failed setup of mailbox WQ/CQ: rc = 0x%x\n",
9748 (uint32_t)rc);
9749 goto out_destroy;
da0436e9 9750 }
2d7dbc4c
JS
9751 if (phba->nvmet_support) {
9752 if (!phba->sli4_hba.nvmet_cqset) {
372c187b 9753 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9754 "3165 Fast-path NVME CQ Set "
9755 "array not allocated\n");
9756 rc = -ENOMEM;
9757 goto out_destroy;
9758 }
9759 if (phba->cfg_nvmet_mrq > 1) {
9760 rc = lpfc_cq_create_set(phba,
9761 phba->sli4_hba.nvmet_cqset,
cdb42bec 9762 qp,
2d7dbc4c
JS
9763 LPFC_WCQ, LPFC_NVMET);
9764 if (rc) {
372c187b 9765 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9766 "3164 Failed setup of NVME CQ "
9767 "Set, rc = 0x%x\n",
9768 (uint32_t)rc);
9769 goto out_destroy;
9770 }
9771 } else {
9772 /* Set up NVMET Receive Complete Queue */
9773 rc = lpfc_cq_create(phba, phba->sli4_hba.nvmet_cqset[0],
cdb42bec 9774 qp[0].hba_eq,
2d7dbc4c
JS
9775 LPFC_WCQ, LPFC_NVMET);
9776 if (rc) {
372c187b 9777 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9778 "6089 Failed setup NVMET CQ: "
9779 "rc = 0x%x\n", (uint32_t)rc);
9780 goto out_destroy;
9781 }
81b96eda
JS
9782 phba->sli4_hba.nvmet_cqset[0]->chann = 0;
9783
2d7dbc4c
JS
9784 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9785 "6090 NVMET CQ setup: cq-id=%d, "
9786 "parent eq-id=%d\n",
9787 phba->sli4_hba.nvmet_cqset[0]->queue_id,
cdb42bec 9788 qp[0].hba_eq->queue_id);
2d7dbc4c
JS
9789 }
9790 }
da0436e9 9791
895427bd
JS
9792 /* Set up slow-path ELS WQ/CQ */
9793 if (!phba->sli4_hba.els_cq || !phba->sli4_hba.els_wq) {
372c187b 9794 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9795 "0530 ELS %s not allocated\n",
9796 phba->sli4_hba.els_cq ? "WQ" : "CQ");
1b51197d 9797 rc = -ENOMEM;
895427bd 9798 goto out_destroy;
da0436e9 9799 }
cdb42bec
JS
9800 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
9801 phba->sli4_hba.els_cq,
9802 phba->sli4_hba.els_wq,
9803 NULL, 0, LPFC_ELS);
da0436e9 9804 if (rc) {
372c187b 9805 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
cdb42bec
JS
9806 "0525 Failed setup of ELS WQ/CQ: rc = 0x%x\n",
9807 (uint32_t)rc);
895427bd 9808 goto out_destroy;
da0436e9
JS
9809 }
9810 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9811 "2590 ELS WQ setup: wq-id=%d, parent cq-id=%d\n",
9812 phba->sli4_hba.els_wq->queue_id,
9813 phba->sli4_hba.els_cq->queue_id);
9814
cdb42bec 9815 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
895427bd
JS
9816 /* Set up NVME LS Complete Queue */
9817 if (!phba->sli4_hba.nvmels_cq || !phba->sli4_hba.nvmels_wq) {
372c187b 9818 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
895427bd
JS
9819 "6091 LS %s not allocated\n",
9820 phba->sli4_hba.nvmels_cq ? "WQ" : "CQ");
9821 rc = -ENOMEM;
9822 goto out_destroy;
9823 }
cdb42bec
JS
9824 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
9825 phba->sli4_hba.nvmels_cq,
9826 phba->sli4_hba.nvmels_wq,
9827 NULL, 0, LPFC_NVME_LS);
895427bd 9828 if (rc) {
372c187b 9829 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
cdb42bec
JS
9830 "0526 Failed setup of NVVME LS WQ/CQ: "
9831 "rc = 0x%x\n", (uint32_t)rc);
895427bd
JS
9832 goto out_destroy;
9833 }
9834
9835 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9836 "6096 ELS WQ setup: wq-id=%d, "
9837 "parent cq-id=%d\n",
9838 phba->sli4_hba.nvmels_wq->queue_id,
9839 phba->sli4_hba.nvmels_cq->queue_id);
9840 }
9841
2d7dbc4c
JS
9842 /*
9843 * Create NVMET Receive Queue (RQ)
9844 */
9845 if (phba->nvmet_support) {
9846 if ((!phba->sli4_hba.nvmet_cqset) ||
9847 (!phba->sli4_hba.nvmet_mrq_hdr) ||
9848 (!phba->sli4_hba.nvmet_mrq_data)) {
372c187b 9849 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9850 "6130 MRQ CQ Queues not "
9851 "allocated\n");
9852 rc = -ENOMEM;
9853 goto out_destroy;
9854 }
9855 if (phba->cfg_nvmet_mrq > 1) {
9856 rc = lpfc_mrq_create(phba,
9857 phba->sli4_hba.nvmet_mrq_hdr,
9858 phba->sli4_hba.nvmet_mrq_data,
9859 phba->sli4_hba.nvmet_cqset,
9860 LPFC_NVMET);
9861 if (rc) {
372c187b 9862 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9863 "6098 Failed setup of NVMET "
9864 "MRQ: rc = 0x%x\n",
9865 (uint32_t)rc);
9866 goto out_destroy;
9867 }
9868
9869 } else {
9870 rc = lpfc_rq_create(phba,
9871 phba->sli4_hba.nvmet_mrq_hdr[0],
9872 phba->sli4_hba.nvmet_mrq_data[0],
9873 phba->sli4_hba.nvmet_cqset[0],
9874 LPFC_NVMET);
9875 if (rc) {
372c187b 9876 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2d7dbc4c
JS
9877 "6057 Failed setup of NVMET "
9878 "Receive Queue: rc = 0x%x\n",
9879 (uint32_t)rc);
9880 goto out_destroy;
9881 }
9882
9883 lpfc_printf_log(
9884 phba, KERN_INFO, LOG_INIT,
9885 "6099 NVMET RQ setup: hdr-rq-id=%d, "
9886 "dat-rq-id=%d parent cq-id=%d\n",
9887 phba->sli4_hba.nvmet_mrq_hdr[0]->queue_id,
9888 phba->sli4_hba.nvmet_mrq_data[0]->queue_id,
9889 phba->sli4_hba.nvmet_cqset[0]->queue_id);
9890
9891 }
9892 }
9893
da0436e9 9894 if (!phba->sli4_hba.hdr_rq || !phba->sli4_hba.dat_rq) {
372c187b 9895 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9896 "0540 Receive Queue not allocated\n");
1b51197d 9897 rc = -ENOMEM;
895427bd 9898 goto out_destroy;
da0436e9 9899 }
73d91e50 9900
da0436e9 9901 rc = lpfc_rq_create(phba, phba->sli4_hba.hdr_rq, phba->sli4_hba.dat_rq,
4d9ab994 9902 phba->sli4_hba.els_cq, LPFC_USOL);
da0436e9 9903 if (rc) {
372c187b 9904 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 9905 "0541 Failed setup of Receive Queue: "
a2fc4aef 9906 "rc = 0x%x\n", (uint32_t)rc);
895427bd 9907 goto out_destroy;
da0436e9 9908 }
73d91e50 9909
da0436e9
JS
9910 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9911 "2592 USL RQ setup: hdr-rq-id=%d, dat-rq-id=%d "
9912 "parent cq-id=%d\n",
9913 phba->sli4_hba.hdr_rq->queue_id,
9914 phba->sli4_hba.dat_rq->queue_id,
4d9ab994 9915 phba->sli4_hba.els_cq->queue_id);
1ba981fd 9916
cb733e35
JS
9917 if (phba->cfg_fcp_imax)
9918 usdelay = LPFC_SEC_TO_USEC / phba->cfg_fcp_imax;
9919 else
9920 usdelay = 0;
9921
6a828b0f 9922 for (qidx = 0; qidx < phba->cfg_irq_chann;
cdb42bec 9923 qidx += LPFC_MAX_EQ_DELAY_EQID_CNT)
0cf07f84 9924 lpfc_modify_hba_eq_delay(phba, qidx, LPFC_MAX_EQ_DELAY_EQID_CNT,
cb733e35 9925 usdelay);
43140ca6 9926
6a828b0f
JS
9927 if (phba->sli4_hba.cq_max) {
9928 kfree(phba->sli4_hba.cq_lookup);
9929 phba->sli4_hba.cq_lookup = kcalloc((phba->sli4_hba.cq_max + 1),
9930 sizeof(struct lpfc_queue *), GFP_KERNEL);
9931 if (!phba->sli4_hba.cq_lookup) {
372c187b 9932 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
6a828b0f
JS
9933 "0549 Failed setup of CQ Lookup table: "
9934 "size 0x%x\n", phba->sli4_hba.cq_max);
fad28e3d 9935 rc = -ENOMEM;
895427bd 9936 goto out_destroy;
1ba981fd 9937 }
6a828b0f 9938 lpfc_setup_cq_lookup(phba);
1ba981fd 9939 }
da0436e9
JS
9940 return 0;
9941
895427bd
JS
9942out_destroy:
9943 lpfc_sli4_queue_unset(phba);
da0436e9
JS
9944out_error:
9945 return rc;
9946}
9947
9948/**
9949 * lpfc_sli4_queue_unset - Unset all the SLI4 queues
9950 * @phba: pointer to lpfc hba data structure.
9951 *
9952 * This routine is invoked to unset all the SLI4 queues with the FCoE HBA
9953 * operation.
9954 *
9955 * Return codes
af901ca1 9956 * 0 - successful
25985edc 9957 * -ENOMEM - No available memory
d439d286 9958 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
9959 **/
9960void
9961lpfc_sli4_queue_unset(struct lpfc_hba *phba)
9962{
cdb42bec 9963 struct lpfc_sli4_hdw_queue *qp;
657add4e 9964 struct lpfc_queue *eq;
895427bd 9965 int qidx;
da0436e9
JS
9966
9967 /* Unset mailbox command work queue */
895427bd
JS
9968 if (phba->sli4_hba.mbx_wq)
9969 lpfc_mq_destroy(phba, phba->sli4_hba.mbx_wq);
9970
9971 /* Unset NVME LS work queue */
9972 if (phba->sli4_hba.nvmels_wq)
9973 lpfc_wq_destroy(phba, phba->sli4_hba.nvmels_wq);
9974
da0436e9 9975 /* Unset ELS work queue */
019c0d66 9976 if (phba->sli4_hba.els_wq)
895427bd
JS
9977 lpfc_wq_destroy(phba, phba->sli4_hba.els_wq);
9978
da0436e9 9979 /* Unset unsolicited receive queue */
895427bd
JS
9980 if (phba->sli4_hba.hdr_rq)
9981 lpfc_rq_destroy(phba, phba->sli4_hba.hdr_rq,
9982 phba->sli4_hba.dat_rq);
9983
da0436e9 9984 /* Unset mailbox command complete queue */
895427bd
JS
9985 if (phba->sli4_hba.mbx_cq)
9986 lpfc_cq_destroy(phba, phba->sli4_hba.mbx_cq);
9987
da0436e9 9988 /* Unset ELS complete queue */
895427bd
JS
9989 if (phba->sli4_hba.els_cq)
9990 lpfc_cq_destroy(phba, phba->sli4_hba.els_cq);
9991
9992 /* Unset NVME LS complete queue */
9993 if (phba->sli4_hba.nvmels_cq)
9994 lpfc_cq_destroy(phba, phba->sli4_hba.nvmels_cq);
9995
bcb24f65
JS
9996 if (phba->nvmet_support) {
9997 /* Unset NVMET MRQ queue */
9998 if (phba->sli4_hba.nvmet_mrq_hdr) {
9999 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
10000 lpfc_rq_destroy(
10001 phba,
2d7dbc4c
JS
10002 phba->sli4_hba.nvmet_mrq_hdr[qidx],
10003 phba->sli4_hba.nvmet_mrq_data[qidx]);
bcb24f65 10004 }
2d7dbc4c 10005
bcb24f65
JS
10006 /* Unset NVMET CQ Set complete queue */
10007 if (phba->sli4_hba.nvmet_cqset) {
10008 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
10009 lpfc_cq_destroy(
10010 phba, phba->sli4_hba.nvmet_cqset[qidx]);
10011 }
2d7dbc4c
JS
10012 }
10013
cdb42bec
JS
10014 /* Unset fast-path SLI4 queues */
10015 if (phba->sli4_hba.hdwq) {
657add4e 10016 /* Loop thru all Hardware Queues */
cdb42bec 10017 for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {
657add4e 10018 /* Destroy the CQ/WQ corresponding to Hardware Queue */
cdb42bec 10019 qp = &phba->sli4_hba.hdwq[qidx];
c00f62e6
JS
10020 lpfc_wq_destroy(phba, qp->io_wq);
10021 lpfc_cq_destroy(phba, qp->io_cq);
657add4e
JS
10022 }
10023 /* Loop thru all IRQ vectors */
10024 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
10025 /* Destroy the EQ corresponding to the IRQ vector */
10026 eq = phba->sli4_hba.hba_eq_hdl[qidx].eq;
10027 lpfc_eq_destroy(phba, eq);
cdb42bec
JS
10028 }
10029 }
895427bd 10030
6a828b0f
JS
10031 kfree(phba->sli4_hba.cq_lookup);
10032 phba->sli4_hba.cq_lookup = NULL;
10033 phba->sli4_hba.cq_max = 0;
da0436e9
JS
10034}
10035
10036/**
10037 * lpfc_sli4_cq_event_pool_create - Create completion-queue event free pool
10038 * @phba: pointer to lpfc hba data structure.
10039 *
10040 * This routine is invoked to allocate and set up a pool of completion queue
10041 * events. The body of the completion queue event is a completion queue entry
10042 * CQE. For now, this pool is used for the interrupt service routine to queue
10043 * the following HBA completion queue events for the worker thread to process:
10044 * - Mailbox asynchronous events
10045 * - Receive queue completion unsolicited events
10046 * Later, this can be used for all the slow-path events.
10047 *
10048 * Return codes
af901ca1 10049 * 0 - successful
25985edc 10050 * -ENOMEM - No available memory
da0436e9
JS
10051 **/
10052static int
10053lpfc_sli4_cq_event_pool_create(struct lpfc_hba *phba)
10054{
10055 struct lpfc_cq_event *cq_event;
10056 int i;
10057
10058 for (i = 0; i < (4 * phba->sli4_hba.cq_ecount); i++) {
10059 cq_event = kmalloc(sizeof(struct lpfc_cq_event), GFP_KERNEL);
10060 if (!cq_event)
10061 goto out_pool_create_fail;
10062 list_add_tail(&cq_event->list,
10063 &phba->sli4_hba.sp_cqe_event_pool);
10064 }
10065 return 0;
10066
10067out_pool_create_fail:
10068 lpfc_sli4_cq_event_pool_destroy(phba);
10069 return -ENOMEM;
10070}
10071
10072/**
10073 * lpfc_sli4_cq_event_pool_destroy - Free completion-queue event free pool
10074 * @phba: pointer to lpfc hba data structure.
10075 *
10076 * This routine is invoked to free the pool of completion queue events at
10077 * driver unload time. Note that, it is the responsibility of the driver
10078 * cleanup routine to free all the outstanding completion-queue events
10079 * allocated from this pool back into the pool before invoking this routine
10080 * to destroy the pool.
10081 **/
10082static void
10083lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *phba)
10084{
10085 struct lpfc_cq_event *cq_event, *next_cq_event;
10086
10087 list_for_each_entry_safe(cq_event, next_cq_event,
10088 &phba->sli4_hba.sp_cqe_event_pool, list) {
10089 list_del(&cq_event->list);
10090 kfree(cq_event);
10091 }
10092}
10093
10094/**
10095 * __lpfc_sli4_cq_event_alloc - Allocate a completion-queue event from free pool
10096 * @phba: pointer to lpfc hba data structure.
10097 *
10098 * This routine is the lock free version of the API invoked to allocate a
10099 * completion-queue event from the free pool.
10100 *
10101 * Return: Pointer to the newly allocated completion-queue event if successful
10102 * NULL otherwise.
10103 **/
10104struct lpfc_cq_event *
10105__lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
10106{
10107 struct lpfc_cq_event *cq_event = NULL;
10108
10109 list_remove_head(&phba->sli4_hba.sp_cqe_event_pool, cq_event,
10110 struct lpfc_cq_event, list);
10111 return cq_event;
10112}
10113
10114/**
10115 * lpfc_sli4_cq_event_alloc - Allocate a completion-queue event from free pool
10116 * @phba: pointer to lpfc hba data structure.
10117 *
10118 * This routine is the lock version of the API invoked to allocate a
10119 * completion-queue event from the free pool.
10120 *
10121 * Return: Pointer to the newly allocated completion-queue event if successful
10122 * NULL otherwise.
10123 **/
10124struct lpfc_cq_event *
10125lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
10126{
10127 struct lpfc_cq_event *cq_event;
10128 unsigned long iflags;
10129
10130 spin_lock_irqsave(&phba->hbalock, iflags);
10131 cq_event = __lpfc_sli4_cq_event_alloc(phba);
10132 spin_unlock_irqrestore(&phba->hbalock, iflags);
10133 return cq_event;
10134}
10135
10136/**
10137 * __lpfc_sli4_cq_event_release - Release a completion-queue event to free pool
10138 * @phba: pointer to lpfc hba data structure.
10139 * @cq_event: pointer to the completion queue event to be freed.
10140 *
10141 * This routine is the lock free version of the API invoked to release a
10142 * completion-queue event back into the free pool.
10143 **/
10144void
10145__lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
10146 struct lpfc_cq_event *cq_event)
10147{
10148 list_add_tail(&cq_event->list, &phba->sli4_hba.sp_cqe_event_pool);
10149}
10150
10151/**
10152 * lpfc_sli4_cq_event_release - Release a completion-queue event to free pool
10153 * @phba: pointer to lpfc hba data structure.
10154 * @cq_event: pointer to the completion queue event to be freed.
10155 *
10156 * This routine is the lock version of the API invoked to release a
10157 * completion-queue event back into the free pool.
10158 **/
10159void
10160lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
10161 struct lpfc_cq_event *cq_event)
10162{
10163 unsigned long iflags;
10164 spin_lock_irqsave(&phba->hbalock, iflags);
10165 __lpfc_sli4_cq_event_release(phba, cq_event);
10166 spin_unlock_irqrestore(&phba->hbalock, iflags);
10167}
10168
10169/**
10170 * lpfc_sli4_cq_event_release_all - Release all cq events to the free pool
10171 * @phba: pointer to lpfc hba data structure.
10172 *
10173 * This routine is to free all the pending completion-queue events to the
10174 * back into the free pool for device reset.
10175 **/
10176static void
10177lpfc_sli4_cq_event_release_all(struct lpfc_hba *phba)
10178{
e7dab164
JS
10179 LIST_HEAD(cq_event_list);
10180 struct lpfc_cq_event *cq_event;
da0436e9
JS
10181 unsigned long iflags;
10182
10183 /* Retrieve all the pending WCQEs from pending WCQE lists */
e7dab164 10184
da0436e9 10185 /* Pending ELS XRI abort events */
e7dab164 10186 spin_lock_irqsave(&phba->sli4_hba.els_xri_abrt_list_lock, iflags);
da0436e9 10187 list_splice_init(&phba->sli4_hba.sp_els_xri_aborted_work_queue,
e7dab164
JS
10188 &cq_event_list);
10189 spin_unlock_irqrestore(&phba->sli4_hba.els_xri_abrt_list_lock, iflags);
10190
da0436e9 10191 /* Pending asynnc events */
e7dab164 10192 spin_lock_irqsave(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9 10193 list_splice_init(&phba->sli4_hba.sp_asynce_work_queue,
e7dab164
JS
10194 &cq_event_list);
10195 spin_unlock_irqrestore(&phba->sli4_hba.asynce_list_lock, iflags);
da0436e9 10196
e7dab164
JS
10197 while (!list_empty(&cq_event_list)) {
10198 list_remove_head(&cq_event_list, cq_event,
10199 struct lpfc_cq_event, list);
10200 lpfc_sli4_cq_event_release(phba, cq_event);
da0436e9
JS
10201 }
10202}
10203
10204/**
10205 * lpfc_pci_function_reset - Reset pci function.
10206 * @phba: pointer to lpfc hba data structure.
10207 *
10208 * This routine is invoked to request a PCI function reset. It will destroys
10209 * all resources assigned to the PCI function which originates this request.
10210 *
10211 * Return codes
af901ca1 10212 * 0 - successful
25985edc 10213 * -ENOMEM - No available memory
d439d286 10214 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
10215 **/
10216int
10217lpfc_pci_function_reset(struct lpfc_hba *phba)
10218{
10219 LPFC_MBOXQ_t *mboxq;
2fcee4bf 10220 uint32_t rc = 0, if_type;
da0436e9 10221 uint32_t shdr_status, shdr_add_status;
2f6fa2c9
JS
10222 uint32_t rdy_chk;
10223 uint32_t port_reset = 0;
da0436e9 10224 union lpfc_sli4_cfg_shdr *shdr;
2fcee4bf 10225 struct lpfc_register reg_data;
2b81f942 10226 uint16_t devid;
da0436e9 10227
2fcee4bf
JS
10228 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
10229 switch (if_type) {
10230 case LPFC_SLI_INTF_IF_TYPE_0:
10231 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
10232 GFP_KERNEL);
10233 if (!mboxq) {
372c187b 10234 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
10235 "0494 Unable to allocate memory for "
10236 "issuing SLI_FUNCTION_RESET mailbox "
10237 "command\n");
10238 return -ENOMEM;
10239 }
da0436e9 10240
2fcee4bf
JS
10241 /* Setup PCI function reset mailbox-ioctl command */
10242 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
10243 LPFC_MBOX_OPCODE_FUNCTION_RESET, 0,
10244 LPFC_SLI4_MBX_EMBED);
10245 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
10246 shdr = (union lpfc_sli4_cfg_shdr *)
10247 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
10248 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
10249 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status,
10250 &shdr->response);
10251 if (rc != MBX_TIMEOUT)
10252 mempool_free(mboxq, phba->mbox_mem_pool);
10253 if (shdr_status || shdr_add_status || rc) {
372c187b 10254 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
10255 "0495 SLI_FUNCTION_RESET mailbox "
10256 "failed with status x%x add_status x%x,"
10257 " mbx status x%x\n",
10258 shdr_status, shdr_add_status, rc);
10259 rc = -ENXIO;
10260 }
10261 break;
10262 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 10263 case LPFC_SLI_INTF_IF_TYPE_6:
2f6fa2c9
JS
10264wait:
10265 /*
10266 * Poll the Port Status Register and wait for RDY for
10267 * up to 30 seconds. If the port doesn't respond, treat
10268 * it as an error.
10269 */
77d093fb 10270 for (rdy_chk = 0; rdy_chk < 1500; rdy_chk++) {
2f6fa2c9
JS
10271 if (lpfc_readl(phba->sli4_hba.u.if_type2.
10272 STATUSregaddr, &reg_data.word0)) {
10273 rc = -ENODEV;
10274 goto out;
10275 }
10276 if (bf_get(lpfc_sliport_status_rdy, &reg_data))
10277 break;
10278 msleep(20);
10279 }
10280
10281 if (!bf_get(lpfc_sliport_status_rdy, &reg_data)) {
10282 phba->work_status[0] = readl(
10283 phba->sli4_hba.u.if_type2.ERR1regaddr);
10284 phba->work_status[1] = readl(
10285 phba->sli4_hba.u.if_type2.ERR2regaddr);
372c187b 10286 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2f6fa2c9
JS
10287 "2890 Port not ready, port status reg "
10288 "0x%x error 1=0x%x, error 2=0x%x\n",
10289 reg_data.word0,
10290 phba->work_status[0],
10291 phba->work_status[1]);
10292 rc = -ENODEV;
10293 goto out;
10294 }
10295
10296 if (!port_reset) {
10297 /*
10298 * Reset the port now
10299 */
2fcee4bf
JS
10300 reg_data.word0 = 0;
10301 bf_set(lpfc_sliport_ctrl_end, &reg_data,
10302 LPFC_SLIPORT_LITTLE_ENDIAN);
10303 bf_set(lpfc_sliport_ctrl_ip, &reg_data,
10304 LPFC_SLIPORT_INIT_PORT);
10305 writel(reg_data.word0, phba->sli4_hba.u.if_type2.
10306 CTRLregaddr);
8fcb8acd 10307 /* flush */
2b81f942
JS
10308 pci_read_config_word(phba->pcidev,
10309 PCI_DEVICE_ID, &devid);
2fcee4bf 10310
2f6fa2c9
JS
10311 port_reset = 1;
10312 msleep(20);
10313 goto wait;
10314 } else if (bf_get(lpfc_sliport_status_rn, &reg_data)) {
10315 rc = -ENODEV;
10316 goto out;
2fcee4bf
JS
10317 }
10318 break;
2f6fa2c9 10319
2fcee4bf
JS
10320 case LPFC_SLI_INTF_IF_TYPE_1:
10321 default:
10322 break;
da0436e9 10323 }
2fcee4bf 10324
73d91e50 10325out:
2fcee4bf 10326 /* Catch the not-ready port failure after a port reset. */
2f6fa2c9 10327 if (rc) {
372c187b 10328 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
229adb0e 10329 "3317 HBA not functional: IP Reset Failed "
2f6fa2c9 10330 "try: echo fw_reset > board_mode\n");
2fcee4bf 10331 rc = -ENODEV;
229adb0e 10332 }
2fcee4bf 10333
da0436e9
JS
10334 return rc;
10335}
10336
da0436e9
JS
10337/**
10338 * lpfc_sli4_pci_mem_setup - Setup SLI4 HBA PCI memory space.
10339 * @phba: pointer to lpfc hba data structure.
10340 *
10341 * This routine is invoked to set up the PCI device memory space for device
10342 * with SLI-4 interface spec.
10343 *
10344 * Return codes
af901ca1 10345 * 0 - successful
da0436e9
JS
10346 * other values - error
10347 **/
10348static int
10349lpfc_sli4_pci_mem_setup(struct lpfc_hba *phba)
10350{
f30e1bfd 10351 struct pci_dev *pdev = phba->pcidev;
da0436e9 10352 unsigned long bar0map_len, bar1map_len, bar2map_len;
3a487ff7 10353 int error;
2fcee4bf 10354 uint32_t if_type;
da0436e9 10355
f30e1bfd 10356 if (!pdev)
56de8357 10357 return -ENODEV;
da0436e9
JS
10358
10359 /* Set the device DMA mask size */
56de8357
HR
10360 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
10361 if (error)
10362 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10363 if (error)
f30e1bfd 10364 return error;
da0436e9 10365
2fcee4bf
JS
10366 /*
10367 * The BARs and register set definitions and offset locations are
10368 * dependent on the if_type.
10369 */
10370 if (pci_read_config_dword(pdev, LPFC_SLI_INTF,
10371 &phba->sli4_hba.sli_intf.word0)) {
3a487ff7 10372 return -ENODEV;
2fcee4bf
JS
10373 }
10374
10375 /* There is no SLI3 failback for SLI4 devices. */
10376 if (bf_get(lpfc_sli_intf_valid, &phba->sli4_hba.sli_intf) !=
10377 LPFC_SLI_INTF_VALID) {
372c187b 10378 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
2fcee4bf
JS
10379 "2894 SLI_INTF reg contents invalid "
10380 "sli_intf reg 0x%x\n",
10381 phba->sli4_hba.sli_intf.word0);
3a487ff7 10382 return -ENODEV;
2fcee4bf
JS
10383 }
10384
10385 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
10386 /*
10387 * Get the bus address of SLI4 device Bar regions and the
10388 * number of bytes required by each mapping. The mapping of the
10389 * particular PCI BARs regions is dependent on the type of
10390 * SLI4 device.
da0436e9 10391 */
f5ca6f2e
JS
10392 if (pci_resource_start(pdev, PCI_64BIT_BAR0)) {
10393 phba->pci_bar0_map = pci_resource_start(pdev, PCI_64BIT_BAR0);
10394 bar0map_len = pci_resource_len(pdev, PCI_64BIT_BAR0);
2fcee4bf
JS
10395
10396 /*
10397 * Map SLI4 PCI Config Space Register base to a kernel virtual
10398 * addr
10399 */
10400 phba->sli4_hba.conf_regs_memmap_p =
10401 ioremap(phba->pci_bar0_map, bar0map_len);
10402 if (!phba->sli4_hba.conf_regs_memmap_p) {
10403 dev_printk(KERN_ERR, &pdev->dev,
10404 "ioremap failed for SLI4 PCI config "
10405 "registers.\n");
3a487ff7 10406 return -ENODEV;
2fcee4bf 10407 }
f5ca6f2e 10408 phba->pci_bar0_memmap_p = phba->sli4_hba.conf_regs_memmap_p;
2fcee4bf
JS
10409 /* Set up BAR0 PCI config space register memory map */
10410 lpfc_sli4_bar0_register_memmap(phba, if_type);
1dfb5a47
JS
10411 } else {
10412 phba->pci_bar0_map = pci_resource_start(pdev, 1);
10413 bar0map_len = pci_resource_len(pdev, 1);
27d6ac0a 10414 if (if_type >= LPFC_SLI_INTF_IF_TYPE_2) {
2fcee4bf
JS
10415 dev_printk(KERN_ERR, &pdev->dev,
10416 "FATAL - No BAR0 mapping for SLI4, if_type 2\n");
3a487ff7 10417 return -ENODEV;
2fcee4bf
JS
10418 }
10419 phba->sli4_hba.conf_regs_memmap_p =
da0436e9 10420 ioremap(phba->pci_bar0_map, bar0map_len);
2fcee4bf
JS
10421 if (!phba->sli4_hba.conf_regs_memmap_p) {
10422 dev_printk(KERN_ERR, &pdev->dev,
10423 "ioremap failed for SLI4 PCI config "
10424 "registers.\n");
3a487ff7 10425 return -ENODEV;
2fcee4bf
JS
10426 }
10427 lpfc_sli4_bar0_register_memmap(phba, if_type);
da0436e9
JS
10428 }
10429
e4b9794e
JS
10430 if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
10431 if (pci_resource_start(pdev, PCI_64BIT_BAR2)) {
10432 /*
10433 * Map SLI4 if type 0 HBA Control Register base to a
10434 * kernel virtual address and setup the registers.
10435 */
10436 phba->pci_bar1_map = pci_resource_start(pdev,
10437 PCI_64BIT_BAR2);
10438 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
10439 phba->sli4_hba.ctrl_regs_memmap_p =
10440 ioremap(phba->pci_bar1_map,
10441 bar1map_len);
10442 if (!phba->sli4_hba.ctrl_regs_memmap_p) {
10443 dev_err(&pdev->dev,
10444 "ioremap failed for SLI4 HBA "
10445 "control registers.\n");
10446 error = -ENOMEM;
10447 goto out_iounmap_conf;
10448 }
10449 phba->pci_bar2_memmap_p =
10450 phba->sli4_hba.ctrl_regs_memmap_p;
27d6ac0a 10451 lpfc_sli4_bar1_register_memmap(phba, if_type);
e4b9794e
JS
10452 } else {
10453 error = -ENOMEM;
2fcee4bf
JS
10454 goto out_iounmap_conf;
10455 }
da0436e9
JS
10456 }
10457
27d6ac0a
JS
10458 if ((if_type == LPFC_SLI_INTF_IF_TYPE_6) &&
10459 (pci_resource_start(pdev, PCI_64BIT_BAR2))) {
10460 /*
10461 * Map SLI4 if type 6 HBA Doorbell Register base to a kernel
10462 * virtual address and setup the registers.
10463 */
10464 phba->pci_bar1_map = pci_resource_start(pdev, PCI_64BIT_BAR2);
10465 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
10466 phba->sli4_hba.drbl_regs_memmap_p =
10467 ioremap(phba->pci_bar1_map, bar1map_len);
10468 if (!phba->sli4_hba.drbl_regs_memmap_p) {
10469 dev_err(&pdev->dev,
10470 "ioremap failed for SLI4 HBA doorbell registers.\n");
3a487ff7 10471 error = -ENOMEM;
27d6ac0a
JS
10472 goto out_iounmap_conf;
10473 }
10474 phba->pci_bar2_memmap_p = phba->sli4_hba.drbl_regs_memmap_p;
10475 lpfc_sli4_bar1_register_memmap(phba, if_type);
10476 }
10477
e4b9794e
JS
10478 if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
10479 if (pci_resource_start(pdev, PCI_64BIT_BAR4)) {
10480 /*
10481 * Map SLI4 if type 0 HBA Doorbell Register base to
10482 * a kernel virtual address and setup the registers.
10483 */
10484 phba->pci_bar2_map = pci_resource_start(pdev,
10485 PCI_64BIT_BAR4);
10486 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
10487 phba->sli4_hba.drbl_regs_memmap_p =
10488 ioremap(phba->pci_bar2_map,
10489 bar2map_len);
10490 if (!phba->sli4_hba.drbl_regs_memmap_p) {
10491 dev_err(&pdev->dev,
10492 "ioremap failed for SLI4 HBA"
10493 " doorbell registers.\n");
10494 error = -ENOMEM;
10495 goto out_iounmap_ctrl;
10496 }
10497 phba->pci_bar4_memmap_p =
10498 phba->sli4_hba.drbl_regs_memmap_p;
10499 error = lpfc_sli4_bar2_register_memmap(phba, LPFC_VF0);
10500 if (error)
10501 goto out_iounmap_all;
10502 } else {
10503 error = -ENOMEM;
2fcee4bf 10504 goto out_iounmap_all;
e4b9794e 10505 }
da0436e9
JS
10506 }
10507
1351e69f
JS
10508 if (if_type == LPFC_SLI_INTF_IF_TYPE_6 &&
10509 pci_resource_start(pdev, PCI_64BIT_BAR4)) {
10510 /*
10511 * Map SLI4 if type 6 HBA DPP Register base to a kernel
10512 * virtual address and setup the registers.
10513 */
10514 phba->pci_bar2_map = pci_resource_start(pdev, PCI_64BIT_BAR4);
10515 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
10516 phba->sli4_hba.dpp_regs_memmap_p =
10517 ioremap(phba->pci_bar2_map, bar2map_len);
10518 if (!phba->sli4_hba.dpp_regs_memmap_p) {
10519 dev_err(&pdev->dev,
10520 "ioremap failed for SLI4 HBA dpp registers.\n");
3a487ff7 10521 error = -ENOMEM;
1351e69f
JS
10522 goto out_iounmap_ctrl;
10523 }
10524 phba->pci_bar4_memmap_p = phba->sli4_hba.dpp_regs_memmap_p;
10525 }
10526
b71413dd 10527 /* Set up the EQ/CQ register handeling functions now */
27d6ac0a
JS
10528 switch (if_type) {
10529 case LPFC_SLI_INTF_IF_TYPE_0:
10530 case LPFC_SLI_INTF_IF_TYPE_2:
b71413dd 10531 phba->sli4_hba.sli4_eq_clr_intr = lpfc_sli4_eq_clr_intr;
32517fc0
JS
10532 phba->sli4_hba.sli4_write_eq_db = lpfc_sli4_write_eq_db;
10533 phba->sli4_hba.sli4_write_cq_db = lpfc_sli4_write_cq_db;
27d6ac0a
JS
10534 break;
10535 case LPFC_SLI_INTF_IF_TYPE_6:
10536 phba->sli4_hba.sli4_eq_clr_intr = lpfc_sli4_if6_eq_clr_intr;
32517fc0
JS
10537 phba->sli4_hba.sli4_write_eq_db = lpfc_sli4_if6_write_eq_db;
10538 phba->sli4_hba.sli4_write_cq_db = lpfc_sli4_if6_write_cq_db;
27d6ac0a
JS
10539 break;
10540 default:
10541 break;
b71413dd
JS
10542 }
10543
da0436e9
JS
10544 return 0;
10545
10546out_iounmap_all:
10547 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10548out_iounmap_ctrl:
10549 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
10550out_iounmap_conf:
10551 iounmap(phba->sli4_hba.conf_regs_memmap_p);
3a487ff7 10552
da0436e9
JS
10553 return error;
10554}
10555
10556/**
10557 * lpfc_sli4_pci_mem_unset - Unset SLI4 HBA PCI memory space.
10558 * @phba: pointer to lpfc hba data structure.
10559 *
10560 * This routine is invoked to unset the PCI device memory space for device
10561 * with SLI-4 interface spec.
10562 **/
10563static void
10564lpfc_sli4_pci_mem_unset(struct lpfc_hba *phba)
10565{
2e90f4b5
JS
10566 uint32_t if_type;
10567 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
da0436e9 10568
2e90f4b5
JS
10569 switch (if_type) {
10570 case LPFC_SLI_INTF_IF_TYPE_0:
10571 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10572 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
10573 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10574 break;
10575 case LPFC_SLI_INTF_IF_TYPE_2:
10576 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10577 break;
27d6ac0a
JS
10578 case LPFC_SLI_INTF_IF_TYPE_6:
10579 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10580 iounmap(phba->sli4_hba.conf_regs_memmap_p);
0b439194
JS
10581 if (phba->sli4_hba.dpp_regs_memmap_p)
10582 iounmap(phba->sli4_hba.dpp_regs_memmap_p);
27d6ac0a 10583 break;
2e90f4b5
JS
10584 case LPFC_SLI_INTF_IF_TYPE_1:
10585 default:
10586 dev_printk(KERN_ERR, &phba->pcidev->dev,
10587 "FATAL - unsupported SLI4 interface type - %d\n",
10588 if_type);
10589 break;
10590 }
da0436e9
JS
10591}
10592
10593/**
10594 * lpfc_sli_enable_msix - Enable MSI-X interrupt mode on SLI-3 device
10595 * @phba: pointer to lpfc hba data structure.
10596 *
10597 * This routine is invoked to enable the MSI-X interrupt vectors to device
45ffac19 10598 * with SLI-3 interface specs.
da0436e9
JS
10599 *
10600 * Return codes
af901ca1 10601 * 0 - successful
da0436e9
JS
10602 * other values - error
10603 **/
10604static int
10605lpfc_sli_enable_msix(struct lpfc_hba *phba)
10606{
45ffac19 10607 int rc;
da0436e9
JS
10608 LPFC_MBOXQ_t *pmb;
10609
10610 /* Set up MSI-X multi-message vectors */
45ffac19
CH
10611 rc = pci_alloc_irq_vectors(phba->pcidev,
10612 LPFC_MSIX_VECTORS, LPFC_MSIX_VECTORS, PCI_IRQ_MSIX);
10613 if (rc < 0) {
da0436e9
JS
10614 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10615 "0420 PCI enable MSI-X failed (%d)\n", rc);
029165ac 10616 goto vec_fail_out;
da0436e9 10617 }
45ffac19 10618
da0436e9
JS
10619 /*
10620 * Assign MSI-X vectors to interrupt handlers
10621 */
10622
10623 /* vector-0 is associated to slow-path handler */
45ffac19 10624 rc = request_irq(pci_irq_vector(phba->pcidev, 0),
ed243d37 10625 &lpfc_sli_sp_intr_handler, 0,
da0436e9
JS
10626 LPFC_SP_DRIVER_HANDLER_NAME, phba);
10627 if (rc) {
10628 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10629 "0421 MSI-X slow-path request_irq failed "
10630 "(%d)\n", rc);
10631 goto msi_fail_out;
10632 }
10633
10634 /* vector-1 is associated to fast-path handler */
45ffac19 10635 rc = request_irq(pci_irq_vector(phba->pcidev, 1),
ed243d37 10636 &lpfc_sli_fp_intr_handler, 0,
da0436e9
JS
10637 LPFC_FP_DRIVER_HANDLER_NAME, phba);
10638
10639 if (rc) {
10640 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10641 "0429 MSI-X fast-path request_irq failed "
10642 "(%d)\n", rc);
10643 goto irq_fail_out;
10644 }
10645
10646 /*
10647 * Configure HBA MSI-X attention conditions to messages
10648 */
10649 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
10650
10651 if (!pmb) {
10652 rc = -ENOMEM;
372c187b 10653 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
10654 "0474 Unable to allocate memory for issuing "
10655 "MBOX_CONFIG_MSI command\n");
10656 goto mem_fail_out;
10657 }
10658 rc = lpfc_config_msi(phba, pmb);
10659 if (rc)
10660 goto mbx_fail_out;
10661 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
10662 if (rc != MBX_SUCCESS) {
10663 lpfc_printf_log(phba, KERN_WARNING, LOG_MBOX,
10664 "0351 Config MSI mailbox command failed, "
10665 "mbxCmd x%x, mbxStatus x%x\n",
10666 pmb->u.mb.mbxCommand, pmb->u.mb.mbxStatus);
10667 goto mbx_fail_out;
10668 }
10669
10670 /* Free memory allocated for mailbox command */
10671 mempool_free(pmb, phba->mbox_mem_pool);
10672 return rc;
10673
10674mbx_fail_out:
10675 /* Free memory allocated for mailbox command */
10676 mempool_free(pmb, phba->mbox_mem_pool);
10677
10678mem_fail_out:
10679 /* free the irq already requested */
45ffac19 10680 free_irq(pci_irq_vector(phba->pcidev, 1), phba);
da0436e9
JS
10681
10682irq_fail_out:
10683 /* free the irq already requested */
45ffac19 10684 free_irq(pci_irq_vector(phba->pcidev, 0), phba);
da0436e9
JS
10685
10686msi_fail_out:
10687 /* Unconfigure MSI-X capability structure */
45ffac19 10688 pci_free_irq_vectors(phba->pcidev);
029165ac
AG
10689
10690vec_fail_out:
da0436e9
JS
10691 return rc;
10692}
10693
da0436e9
JS
10694/**
10695 * lpfc_sli_enable_msi - Enable MSI interrupt mode on SLI-3 device.
10696 * @phba: pointer to lpfc hba data structure.
10697 *
10698 * This routine is invoked to enable the MSI interrupt mode to device with
10699 * SLI-3 interface spec. The kernel function pci_enable_msi() is called to
10700 * enable the MSI vector. The device driver is responsible for calling the
10701 * request_irq() to register MSI vector with a interrupt the handler, which
10702 * is done in this function.
10703 *
10704 * Return codes
af901ca1 10705 * 0 - successful
da0436e9
JS
10706 * other values - error
10707 */
10708static int
10709lpfc_sli_enable_msi(struct lpfc_hba *phba)
10710{
10711 int rc;
10712
10713 rc = pci_enable_msi(phba->pcidev);
10714 if (!rc)
10715 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10716 "0462 PCI enable MSI mode success.\n");
10717 else {
10718 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10719 "0471 PCI enable MSI mode failed (%d)\n", rc);
10720 return rc;
10721 }
10722
10723 rc = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
ed243d37 10724 0, LPFC_DRIVER_NAME, phba);
da0436e9
JS
10725 if (rc) {
10726 pci_disable_msi(phba->pcidev);
10727 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10728 "0478 MSI request_irq failed (%d)\n", rc);
10729 }
10730 return rc;
10731}
10732
da0436e9
JS
10733/**
10734 * lpfc_sli_enable_intr - Enable device interrupt to SLI-3 device.
10735 * @phba: pointer to lpfc hba data structure.
fe614acd 10736 * @cfg_mode: Interrupt configuration mode (INTx, MSI or MSI-X).
da0436e9
JS
10737 *
10738 * This routine is invoked to enable device interrupt and associate driver's
10739 * interrupt handler(s) to interrupt vector(s) to device with SLI-3 interface
10740 * spec. Depends on the interrupt mode configured to the driver, the driver
10741 * will try to fallback from the configured interrupt mode to an interrupt
10742 * mode which is supported by the platform, kernel, and device in the order
10743 * of:
10744 * MSI-X -> MSI -> IRQ.
10745 *
10746 * Return codes
af901ca1 10747 * 0 - successful
da0436e9
JS
10748 * other values - error
10749 **/
10750static uint32_t
10751lpfc_sli_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
10752{
10753 uint32_t intr_mode = LPFC_INTR_ERROR;
10754 int retval;
10755
10756 if (cfg_mode == 2) {
10757 /* Need to issue conf_port mbox cmd before conf_msi mbox cmd */
10758 retval = lpfc_sli_config_port(phba, LPFC_SLI_REV3);
10759 if (!retval) {
10760 /* Now, try to enable MSI-X interrupt mode */
10761 retval = lpfc_sli_enable_msix(phba);
10762 if (!retval) {
10763 /* Indicate initialization to MSI-X mode */
10764 phba->intr_type = MSIX;
10765 intr_mode = 2;
10766 }
10767 }
10768 }
10769
10770 /* Fallback to MSI if MSI-X initialization failed */
10771 if (cfg_mode >= 1 && phba->intr_type == NONE) {
10772 retval = lpfc_sli_enable_msi(phba);
10773 if (!retval) {
10774 /* Indicate initialization to MSI mode */
10775 phba->intr_type = MSI;
10776 intr_mode = 1;
10777 }
10778 }
10779
10780 /* Fallback to INTx if both MSI-X/MSI initalization failed */
10781 if (phba->intr_type == NONE) {
10782 retval = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
10783 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
10784 if (!retval) {
10785 /* Indicate initialization to INTx mode */
10786 phba->intr_type = INTx;
10787 intr_mode = 0;
10788 }
10789 }
10790 return intr_mode;
10791}
10792
10793/**
10794 * lpfc_sli_disable_intr - Disable device interrupt to SLI-3 device.
10795 * @phba: pointer to lpfc hba data structure.
10796 *
10797 * This routine is invoked to disable device interrupt and disassociate the
10798 * driver's interrupt handler(s) from interrupt vector(s) to device with
10799 * SLI-3 interface spec. Depending on the interrupt mode, the driver will
10800 * release the interrupt vector(s) for the message signaled interrupt.
10801 **/
10802static void
10803lpfc_sli_disable_intr(struct lpfc_hba *phba)
10804{
45ffac19
CH
10805 int nr_irqs, i;
10806
da0436e9 10807 if (phba->intr_type == MSIX)
45ffac19
CH
10808 nr_irqs = LPFC_MSIX_VECTORS;
10809 else
10810 nr_irqs = 1;
10811
10812 for (i = 0; i < nr_irqs; i++)
10813 free_irq(pci_irq_vector(phba->pcidev, i), phba);
10814 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
10815
10816 /* Reset interrupt management states */
10817 phba->intr_type = NONE;
10818 phba->sli.slistat.sli_intr = 0;
da0436e9
JS
10819}
10820
6a828b0f 10821/**
657add4e 10822 * lpfc_find_cpu_handle - Find the CPU that corresponds to the specified Queue
6a828b0f
JS
10823 * @phba: pointer to lpfc hba data structure.
10824 * @id: EQ vector index or Hardware Queue index
10825 * @match: LPFC_FIND_BY_EQ = match by EQ
10826 * LPFC_FIND_BY_HDWQ = match by Hardware Queue
657add4e 10827 * Return the CPU that matches the selection criteria
6a828b0f
JS
10828 */
10829static uint16_t
10830lpfc_find_cpu_handle(struct lpfc_hba *phba, uint16_t id, int match)
10831{
10832 struct lpfc_vector_map_info *cpup;
10833 int cpu;
10834
657add4e 10835 /* Loop through all CPUs */
222e9239
JS
10836 for_each_present_cpu(cpu) {
10837 cpup = &phba->sli4_hba.cpu_map[cpu];
657add4e
JS
10838
10839 /* If we are matching by EQ, there may be multiple CPUs using
10840 * using the same vector, so select the one with
10841 * LPFC_CPU_FIRST_IRQ set.
10842 */
6a828b0f 10843 if ((match == LPFC_FIND_BY_EQ) &&
657add4e 10844 (cpup->flag & LPFC_CPU_FIRST_IRQ) &&
6a828b0f
JS
10845 (cpup->eq == id))
10846 return cpu;
657add4e
JS
10847
10848 /* If matching by HDWQ, select the first CPU that matches */
6a828b0f
JS
10849 if ((match == LPFC_FIND_BY_HDWQ) && (cpup->hdwq == id))
10850 return cpu;
6a828b0f
JS
10851 }
10852 return 0;
10853}
10854
6a828b0f
JS
10855#ifdef CONFIG_X86
10856/**
10857 * lpfc_find_hyper - Determine if the CPU map entry is hyper-threaded
10858 * @phba: pointer to lpfc hba data structure.
10859 * @cpu: CPU map index
10860 * @phys_id: CPU package physical id
10861 * @core_id: CPU core id
10862 */
10863static int
10864lpfc_find_hyper(struct lpfc_hba *phba, int cpu,
10865 uint16_t phys_id, uint16_t core_id)
10866{
10867 struct lpfc_vector_map_info *cpup;
10868 int idx;
10869
222e9239
JS
10870 for_each_present_cpu(idx) {
10871 cpup = &phba->sli4_hba.cpu_map[idx];
6a828b0f
JS
10872 /* Does the cpup match the one we are looking for */
10873 if ((cpup->phys_id == phys_id) &&
10874 (cpup->core_id == core_id) &&
222e9239 10875 (cpu != idx))
6a828b0f 10876 return 1;
6a828b0f
JS
10877 }
10878 return 0;
10879}
10880#endif
10881
dcaa2136
JS
10882/*
10883 * lpfc_assign_eq_map_info - Assigns eq for vector_map structure
10884 * @phba: pointer to lpfc hba data structure.
10885 * @eqidx: index for eq and irq vector
10886 * @flag: flags to set for vector_map structure
10887 * @cpu: cpu used to index vector_map structure
10888 *
10889 * The routine assigns eq info into vector_map structure
10890 */
10891static inline void
10892lpfc_assign_eq_map_info(struct lpfc_hba *phba, uint16_t eqidx, uint16_t flag,
10893 unsigned int cpu)
10894{
10895 struct lpfc_vector_map_info *cpup = &phba->sli4_hba.cpu_map[cpu];
10896 struct lpfc_hba_eq_hdl *eqhdl = lpfc_get_eq_hdl(eqidx);
10897
10898 cpup->eq = eqidx;
10899 cpup->flag |= flag;
10900
10901 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10902 "3336 Set Affinity: CPU %d irq %d eq %d flag x%x\n",
10903 cpu, eqhdl->irq, cpup->eq, cpup->flag);
10904}
10905
10906/**
10907 * lpfc_cpu_map_array_init - Initialize cpu_map structure
10908 * @phba: pointer to lpfc hba data structure.
10909 *
10910 * The routine initializes the cpu_map array structure
10911 */
10912static void
10913lpfc_cpu_map_array_init(struct lpfc_hba *phba)
10914{
10915 struct lpfc_vector_map_info *cpup;
10916 struct lpfc_eq_intr_info *eqi;
10917 int cpu;
10918
10919 for_each_possible_cpu(cpu) {
10920 cpup = &phba->sli4_hba.cpu_map[cpu];
10921 cpup->phys_id = LPFC_VECTOR_MAP_EMPTY;
10922 cpup->core_id = LPFC_VECTOR_MAP_EMPTY;
10923 cpup->hdwq = LPFC_VECTOR_MAP_EMPTY;
10924 cpup->eq = LPFC_VECTOR_MAP_EMPTY;
10925 cpup->flag = 0;
10926 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, cpu);
10927 INIT_LIST_HEAD(&eqi->list);
10928 eqi->icnt = 0;
10929 }
10930}
10931
10932/**
10933 * lpfc_hba_eq_hdl_array_init - Initialize hba_eq_hdl structure
10934 * @phba: pointer to lpfc hba data structure.
10935 *
10936 * The routine initializes the hba_eq_hdl array structure
10937 */
10938static void
10939lpfc_hba_eq_hdl_array_init(struct lpfc_hba *phba)
10940{
10941 struct lpfc_hba_eq_hdl *eqhdl;
10942 int i;
10943
10944 for (i = 0; i < phba->cfg_irq_chann; i++) {
10945 eqhdl = lpfc_get_eq_hdl(i);
10946 eqhdl->irq = LPFC_VECTOR_MAP_EMPTY;
10947 eqhdl->phba = phba;
10948 }
10949}
10950
7bb03bbf 10951/**
895427bd 10952 * lpfc_cpu_affinity_check - Check vector CPU affinity mappings
7bb03bbf 10953 * @phba: pointer to lpfc hba data structure.
895427bd
JS
10954 * @vectors: number of msix vectors allocated.
10955 *
10956 * The routine will figure out the CPU affinity assignment for every
6a828b0f 10957 * MSI-X vector allocated for the HBA.
895427bd
JS
10958 * In addition, the CPU to IO channel mapping will be calculated
10959 * and the phba->sli4_hba.cpu_map array will reflect this.
7bb03bbf 10960 */
895427bd
JS
10961static void
10962lpfc_cpu_affinity_check(struct lpfc_hba *phba, int vectors)
7bb03bbf 10963{
3ad348d9 10964 int i, cpu, idx, next_idx, new_cpu, start_cpu, first_cpu;
6a828b0f
JS
10965 int max_phys_id, min_phys_id;
10966 int max_core_id, min_core_id;
7bb03bbf 10967 struct lpfc_vector_map_info *cpup;
d9954a2d 10968 struct lpfc_vector_map_info *new_cpup;
7bb03bbf
JS
10969#ifdef CONFIG_X86
10970 struct cpuinfo_x86 *cpuinfo;
10971#endif
840eda96
JS
10972#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
10973 struct lpfc_hdwq_stat *c_stat;
10974#endif
7bb03bbf 10975
6a828b0f 10976 max_phys_id = 0;
d9954a2d 10977 min_phys_id = LPFC_VECTOR_MAP_EMPTY;
6a828b0f 10978 max_core_id = 0;
d9954a2d 10979 min_core_id = LPFC_VECTOR_MAP_EMPTY;
7bb03bbf
JS
10980
10981 /* Update CPU map with physical id and core id of each CPU */
222e9239
JS
10982 for_each_present_cpu(cpu) {
10983 cpup = &phba->sli4_hba.cpu_map[cpu];
7bb03bbf
JS
10984#ifdef CONFIG_X86
10985 cpuinfo = &cpu_data(cpu);
10986 cpup->phys_id = cpuinfo->phys_proc_id;
10987 cpup->core_id = cpuinfo->cpu_core_id;
d9954a2d
JS
10988 if (lpfc_find_hyper(phba, cpu, cpup->phys_id, cpup->core_id))
10989 cpup->flag |= LPFC_CPU_MAP_HYPER;
7bb03bbf
JS
10990#else
10991 /* No distinction between CPUs for other platforms */
10992 cpup->phys_id = 0;
6a828b0f 10993 cpup->core_id = cpu;
7bb03bbf 10994#endif
6a828b0f 10995
b3295c2a 10996 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3ad348d9
JS
10997 "3328 CPU %d physid %d coreid %d flag x%x\n",
10998 cpu, cpup->phys_id, cpup->core_id, cpup->flag);
6a828b0f
JS
10999
11000 if (cpup->phys_id > max_phys_id)
11001 max_phys_id = cpup->phys_id;
11002 if (cpup->phys_id < min_phys_id)
11003 min_phys_id = cpup->phys_id;
11004
11005 if (cpup->core_id > max_core_id)
11006 max_core_id = cpup->core_id;
11007 if (cpup->core_id < min_core_id)
11008 min_core_id = cpup->core_id;
7bb03bbf 11009 }
7bb03bbf 11010
d9954a2d
JS
11011 /* After looking at each irq vector assigned to this pcidev, its
11012 * possible to see that not ALL CPUs have been accounted for.
657add4e
JS
11013 * Next we will set any unassigned (unaffinitized) cpu map
11014 * entries to a IRQ on the same phys_id.
d9954a2d
JS
11015 */
11016 first_cpu = cpumask_first(cpu_present_mask);
11017 start_cpu = first_cpu;
11018
11019 for_each_present_cpu(cpu) {
11020 cpup = &phba->sli4_hba.cpu_map[cpu];
11021
11022 /* Is this CPU entry unassigned */
11023 if (cpup->eq == LPFC_VECTOR_MAP_EMPTY) {
11024 /* Mark CPU as IRQ not assigned by the kernel */
11025 cpup->flag |= LPFC_CPU_MAP_UNASSIGN;
11026
657add4e 11027 /* If so, find a new_cpup thats on the the SAME
d9954a2d
JS
11028 * phys_id as cpup. start_cpu will start where we
11029 * left off so all unassigned entries don't get assgined
11030 * the IRQ of the first entry.
11031 */
11032 new_cpu = start_cpu;
11033 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
11034 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
11035 if (!(new_cpup->flag & LPFC_CPU_MAP_UNASSIGN) &&
dcaa2136 11036 (new_cpup->eq != LPFC_VECTOR_MAP_EMPTY) &&
d9954a2d
JS
11037 (new_cpup->phys_id == cpup->phys_id))
11038 goto found_same;
11039 new_cpu = cpumask_next(
11040 new_cpu, cpu_present_mask);
11041 if (new_cpu == nr_cpumask_bits)
11042 new_cpu = first_cpu;
11043 }
11044 /* At this point, we leave the CPU as unassigned */
11045 continue;
11046found_same:
11047 /* We found a matching phys_id, so copy the IRQ info */
11048 cpup->eq = new_cpup->eq;
d9954a2d
JS
11049
11050 /* Bump start_cpu to the next slot to minmize the
11051 * chance of having multiple unassigned CPU entries
11052 * selecting the same IRQ.
11053 */
11054 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
11055 if (start_cpu == nr_cpumask_bits)
11056 start_cpu = first_cpu;
11057
657add4e 11058 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
d9954a2d 11059 "3337 Set Affinity: CPU %d "
dcaa2136 11060 "eq %d from peer cpu %d same "
d9954a2d 11061 "phys_id (%d)\n",
dcaa2136
JS
11062 cpu, cpup->eq, new_cpu,
11063 cpup->phys_id);
d9954a2d
JS
11064 }
11065 }
11066
11067 /* Set any unassigned cpu map entries to a IRQ on any phys_id */
11068 start_cpu = first_cpu;
11069
11070 for_each_present_cpu(cpu) {
11071 cpup = &phba->sli4_hba.cpu_map[cpu];
11072
11073 /* Is this entry unassigned */
11074 if (cpup->eq == LPFC_VECTOR_MAP_EMPTY) {
11075 /* Mark it as IRQ not assigned by the kernel */
11076 cpup->flag |= LPFC_CPU_MAP_UNASSIGN;
11077
657add4e 11078 /* If so, find a new_cpup thats on ANY phys_id
d9954a2d
JS
11079 * as the cpup. start_cpu will start where we
11080 * left off so all unassigned entries don't get
11081 * assigned the IRQ of the first entry.
11082 */
11083 new_cpu = start_cpu;
11084 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
11085 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
11086 if (!(new_cpup->flag & LPFC_CPU_MAP_UNASSIGN) &&
dcaa2136 11087 (new_cpup->eq != LPFC_VECTOR_MAP_EMPTY))
d9954a2d
JS
11088 goto found_any;
11089 new_cpu = cpumask_next(
11090 new_cpu, cpu_present_mask);
11091 if (new_cpu == nr_cpumask_bits)
11092 new_cpu = first_cpu;
11093 }
11094 /* We should never leave an entry unassigned */
11095 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11096 "3339 Set Affinity: CPU %d "
dcaa2136
JS
11097 "eq %d UNASSIGNED\n",
11098 cpup->hdwq, cpup->eq);
d9954a2d
JS
11099 continue;
11100found_any:
11101 /* We found an available entry, copy the IRQ info */
11102 cpup->eq = new_cpup->eq;
d9954a2d
JS
11103
11104 /* Bump start_cpu to the next slot to minmize the
11105 * chance of having multiple unassigned CPU entries
11106 * selecting the same IRQ.
11107 */
11108 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
11109 if (start_cpu == nr_cpumask_bits)
11110 start_cpu = first_cpu;
11111
657add4e 11112 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
d9954a2d 11113 "3338 Set Affinity: CPU %d "
dcaa2136
JS
11114 "eq %d from peer cpu %d (%d/%d)\n",
11115 cpu, cpup->eq, new_cpu,
d9954a2d
JS
11116 new_cpup->phys_id, new_cpup->core_id);
11117 }
11118 }
657add4e 11119
3ad348d9
JS
11120 /* Assign hdwq indices that are unique across all cpus in the map
11121 * that are also FIRST_CPUs.
11122 */
11123 idx = 0;
11124 for_each_present_cpu(cpu) {
11125 cpup = &phba->sli4_hba.cpu_map[cpu];
11126
11127 /* Only FIRST IRQs get a hdwq index assignment. */
11128 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
11129 continue;
11130
11131 /* 1 to 1, the first LPFC_CPU_FIRST_IRQ cpus to a unique hdwq */
11132 cpup->hdwq = idx;
11133 idx++;
bc2736e9 11134 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3ad348d9 11135 "3333 Set Affinity: CPU %d (phys %d core %d): "
dcaa2136 11136 "hdwq %d eq %d flg x%x\n",
3ad348d9 11137 cpu, cpup->phys_id, cpup->core_id,
dcaa2136 11138 cpup->hdwq, cpup->eq, cpup->flag);
3ad348d9 11139 }
bc227dde 11140 /* Associate a hdwq with each cpu_map entry
657add4e
JS
11141 * This will be 1 to 1 - hdwq to cpu, unless there are less
11142 * hardware queues then CPUs. For that case we will just round-robin
11143 * the available hardware queues as they get assigned to CPUs.
3ad348d9
JS
11144 * The next_idx is the idx from the FIRST_CPU loop above to account
11145 * for irq_chann < hdwq. The idx is used for round-robin assignments
11146 * and needs to start at 0.
657add4e 11147 */
3ad348d9 11148 next_idx = idx;
657add4e 11149 start_cpu = 0;
3ad348d9 11150 idx = 0;
657add4e
JS
11151 for_each_present_cpu(cpu) {
11152 cpup = &phba->sli4_hba.cpu_map[cpu];
657add4e 11153
3ad348d9
JS
11154 /* FIRST cpus are already mapped. */
11155 if (cpup->flag & LPFC_CPU_FIRST_IRQ)
11156 continue;
11157
11158 /* If the cfg_irq_chann < cfg_hdw_queue, set the hdwq
11159 * of the unassigned cpus to the next idx so that all
11160 * hdw queues are fully utilized.
11161 */
11162 if (next_idx < phba->cfg_hdw_queue) {
11163 cpup->hdwq = next_idx;
11164 next_idx++;
11165 continue;
11166 }
11167
11168 /* Not a First CPU and all hdw_queues are used. Reuse a
11169 * Hardware Queue for another CPU, so be smart about it
11170 * and pick one that has its IRQ/EQ mapped to the same phys_id
11171 * (CPU package) and core_id.
11172 */
11173 new_cpu = start_cpu;
11174 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
11175 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
11176 if (new_cpup->hdwq != LPFC_VECTOR_MAP_EMPTY &&
11177 new_cpup->phys_id == cpup->phys_id &&
11178 new_cpup->core_id == cpup->core_id) {
11179 goto found_hdwq;
657add4e 11180 }
3ad348d9
JS
11181 new_cpu = cpumask_next(new_cpu, cpu_present_mask);
11182 if (new_cpu == nr_cpumask_bits)
11183 new_cpu = first_cpu;
11184 }
657add4e 11185
3ad348d9
JS
11186 /* If we can't match both phys_id and core_id,
11187 * settle for just a phys_id match.
11188 */
11189 new_cpu = start_cpu;
11190 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
11191 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
11192 if (new_cpup->hdwq != LPFC_VECTOR_MAP_EMPTY &&
11193 new_cpup->phys_id == cpup->phys_id)
11194 goto found_hdwq;
11195
11196 new_cpu = cpumask_next(new_cpu, cpu_present_mask);
11197 if (new_cpu == nr_cpumask_bits)
11198 new_cpu = first_cpu;
657add4e 11199 }
3ad348d9
JS
11200
11201 /* Otherwise just round robin on cfg_hdw_queue */
11202 cpup->hdwq = idx % phba->cfg_hdw_queue;
11203 idx++;
11204 goto logit;
11205 found_hdwq:
11206 /* We found an available entry, copy the IRQ info */
11207 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
11208 if (start_cpu == nr_cpumask_bits)
11209 start_cpu = first_cpu;
11210 cpup->hdwq = new_cpup->hdwq;
11211 logit:
bc2736e9 11212 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
657add4e 11213 "3335 Set Affinity: CPU %d (phys %d core %d): "
dcaa2136 11214 "hdwq %d eq %d flg x%x\n",
657add4e 11215 cpu, cpup->phys_id, cpup->core_id,
dcaa2136 11216 cpup->hdwq, cpup->eq, cpup->flag);
657add4e
JS
11217 }
11218
bc227dde
JS
11219 /*
11220 * Initialize the cpu_map slots for not-present cpus in case
11221 * a cpu is hot-added. Perform a simple hdwq round robin assignment.
11222 */
11223 idx = 0;
11224 for_each_possible_cpu(cpu) {
11225 cpup = &phba->sli4_hba.cpu_map[cpu];
840eda96
JS
11226#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
11227 c_stat = per_cpu_ptr(phba->sli4_hba.c_stat, cpu);
11228 c_stat->hdwq_no = cpup->hdwq;
11229#endif
bc227dde
JS
11230 if (cpup->hdwq != LPFC_VECTOR_MAP_EMPTY)
11231 continue;
11232
11233 cpup->hdwq = idx++ % phba->cfg_hdw_queue;
840eda96
JS
11234#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
11235 c_stat->hdwq_no = cpup->hdwq;
11236#endif
bc227dde
JS
11237 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11238 "3340 Set Affinity: not present "
11239 "CPU %d hdwq %d\n",
11240 cpu, cpup->hdwq);
657add4e
JS
11241 }
11242
11243 /* The cpu_map array will be used later during initialization
11244 * when EQ / CQ / WQs are allocated and configured.
11245 */
b3295c2a 11246 return;
7bb03bbf 11247}
7bb03bbf 11248
93a4d6f4
JS
11249/**
11250 * lpfc_cpuhp_get_eq
11251 *
11252 * @phba: pointer to lpfc hba data structure.
11253 * @cpu: cpu going offline
fe614acd 11254 * @eqlist: eq list to append to
93a4d6f4 11255 */
a99c8074 11256static int
93a4d6f4
JS
11257lpfc_cpuhp_get_eq(struct lpfc_hba *phba, unsigned int cpu,
11258 struct list_head *eqlist)
11259{
93a4d6f4
JS
11260 const struct cpumask *maskp;
11261 struct lpfc_queue *eq;
a99c8074 11262 struct cpumask *tmp;
93a4d6f4
JS
11263 u16 idx;
11264
a99c8074
JS
11265 tmp = kzalloc(cpumask_size(), GFP_KERNEL);
11266 if (!tmp)
11267 return -ENOMEM;
11268
93a4d6f4
JS
11269 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
11270 maskp = pci_irq_get_affinity(phba->pcidev, idx);
11271 if (!maskp)
11272 continue;
11273 /*
11274 * if irq is not affinitized to the cpu going
11275 * then we don't need to poll the eq attached
11276 * to it.
11277 */
a99c8074 11278 if (!cpumask_and(tmp, maskp, cpumask_of(cpu)))
93a4d6f4
JS
11279 continue;
11280 /* get the cpus that are online and are affini-
11281 * tized to this irq vector. If the count is
11282 * more than 1 then cpuhp is not going to shut-
11283 * down this vector. Since this cpu has not
11284 * gone offline yet, we need >1.
11285 */
a99c8074
JS
11286 cpumask_and(tmp, maskp, cpu_online_mask);
11287 if (cpumask_weight(tmp) > 1)
93a4d6f4
JS
11288 continue;
11289
11290 /* Now that we have an irq to shutdown, get the eq
11291 * mapped to this irq. Note: multiple hdwq's in
11292 * the software can share an eq, but eventually
11293 * only eq will be mapped to this vector
11294 */
dcaa2136
JS
11295 eq = phba->sli4_hba.hba_eq_hdl[idx].eq;
11296 list_add(&eq->_poll_list, eqlist);
93a4d6f4 11297 }
a99c8074
JS
11298 kfree(tmp);
11299 return 0;
93a4d6f4
JS
11300}
11301
11302static void __lpfc_cpuhp_remove(struct lpfc_hba *phba)
11303{
11304 if (phba->sli_rev != LPFC_SLI_REV4)
11305 return;
11306
11307 cpuhp_state_remove_instance_nocalls(lpfc_cpuhp_state,
11308 &phba->cpuhp);
11309 /*
11310 * unregistering the instance doesn't stop the polling
11311 * timer. Wait for the poll timer to retire.
11312 */
11313 synchronize_rcu();
11314 del_timer_sync(&phba->cpuhp_poll_timer);
11315}
11316
11317static void lpfc_cpuhp_remove(struct lpfc_hba *phba)
11318{
11319 if (phba->pport->fc_flag & FC_OFFLINE_MODE)
11320 return;
11321
11322 __lpfc_cpuhp_remove(phba);
11323}
11324
11325static void lpfc_cpuhp_add(struct lpfc_hba *phba)
11326{
11327 if (phba->sli_rev != LPFC_SLI_REV4)
11328 return;
11329
11330 rcu_read_lock();
11331
f861f596 11332 if (!list_empty(&phba->poll_list))
93a4d6f4
JS
11333 mod_timer(&phba->cpuhp_poll_timer,
11334 jiffies + msecs_to_jiffies(LPFC_POLL_HB));
93a4d6f4
JS
11335
11336 rcu_read_unlock();
11337
11338 cpuhp_state_add_instance_nocalls(lpfc_cpuhp_state,
11339 &phba->cpuhp);
11340}
11341
11342static int __lpfc_cpuhp_checks(struct lpfc_hba *phba, int *retval)
11343{
11344 if (phba->pport->load_flag & FC_UNLOADING) {
11345 *retval = -EAGAIN;
11346 return true;
11347 }
11348
11349 if (phba->sli_rev != LPFC_SLI_REV4) {
11350 *retval = 0;
11351 return true;
11352 }
11353
11354 /* proceed with the hotplug */
11355 return false;
11356}
11357
dcaa2136
JS
11358/**
11359 * lpfc_irq_set_aff - set IRQ affinity
11360 * @eqhdl: EQ handle
11361 * @cpu: cpu to set affinity
11362 *
11363 **/
11364static inline void
11365lpfc_irq_set_aff(struct lpfc_hba_eq_hdl *eqhdl, unsigned int cpu)
11366{
11367 cpumask_clear(&eqhdl->aff_mask);
11368 cpumask_set_cpu(cpu, &eqhdl->aff_mask);
11369 irq_set_status_flags(eqhdl->irq, IRQ_NO_BALANCING);
11370 irq_set_affinity_hint(eqhdl->irq, &eqhdl->aff_mask);
11371}
11372
11373/**
11374 * lpfc_irq_clear_aff - clear IRQ affinity
11375 * @eqhdl: EQ handle
11376 *
11377 **/
11378static inline void
11379lpfc_irq_clear_aff(struct lpfc_hba_eq_hdl *eqhdl)
11380{
11381 cpumask_clear(&eqhdl->aff_mask);
11382 irq_clear_status_flags(eqhdl->irq, IRQ_NO_BALANCING);
dcaa2136
JS
11383}
11384
11385/**
11386 * lpfc_irq_rebalance - rebalances IRQ affinity according to cpuhp event
11387 * @phba: pointer to HBA context object.
11388 * @cpu: cpu going offline/online
11389 * @offline: true, cpu is going offline. false, cpu is coming online.
11390 *
11391 * If cpu is going offline, we'll try our best effort to find the next
3048e3e8
DK
11392 * online cpu on the phba's original_mask and migrate all offlining IRQ
11393 * affinities.
dcaa2136 11394 *
3048e3e8 11395 * If cpu is coming online, reaffinitize the IRQ back to the onlining cpu.
dcaa2136 11396 *
3048e3e8 11397 * Note: Call only if NUMA or NHT mode is enabled, otherwise rely on
dcaa2136
JS
11398 * PCI_IRQ_AFFINITY to auto-manage IRQ affinity.
11399 *
11400 **/
11401static void
11402lpfc_irq_rebalance(struct lpfc_hba *phba, unsigned int cpu, bool offline)
11403{
11404 struct lpfc_vector_map_info *cpup;
11405 struct cpumask *aff_mask;
11406 unsigned int cpu_select, cpu_next, idx;
3048e3e8 11407 const struct cpumask *orig_mask;
dcaa2136 11408
3048e3e8 11409 if (phba->irq_chann_mode == NORMAL_MODE)
dcaa2136
JS
11410 return;
11411
3048e3e8 11412 orig_mask = &phba->sli4_hba.irq_aff_mask;
dcaa2136 11413
3048e3e8 11414 if (!cpumask_test_cpu(cpu, orig_mask))
dcaa2136
JS
11415 return;
11416
11417 cpup = &phba->sli4_hba.cpu_map[cpu];
11418
11419 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
11420 return;
11421
11422 if (offline) {
3048e3e8
DK
11423 /* Find next online CPU on original mask */
11424 cpu_next = cpumask_next_wrap(cpu, orig_mask, cpu, true);
11425 cpu_select = lpfc_next_online_cpu(orig_mask, cpu_next);
dcaa2136
JS
11426
11427 /* Found a valid CPU */
11428 if ((cpu_select < nr_cpu_ids) && (cpu_select != cpu)) {
11429 /* Go through each eqhdl and ensure offlining
11430 * cpu aff_mask is migrated
11431 */
11432 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
11433 aff_mask = lpfc_get_aff_mask(idx);
11434
11435 /* Migrate affinity */
11436 if (cpumask_test_cpu(cpu, aff_mask))
11437 lpfc_irq_set_aff(lpfc_get_eq_hdl(idx),
11438 cpu_select);
11439 }
11440 } else {
11441 /* Rely on irqbalance if no online CPUs left on NUMA */
11442 for (idx = 0; idx < phba->cfg_irq_chann; idx++)
11443 lpfc_irq_clear_aff(lpfc_get_eq_hdl(idx));
11444 }
11445 } else {
11446 /* Migrate affinity back to this CPU */
11447 lpfc_irq_set_aff(lpfc_get_eq_hdl(cpup->eq), cpu);
11448 }
11449}
11450
93a4d6f4
JS
11451static int lpfc_cpu_offline(unsigned int cpu, struct hlist_node *node)
11452{
11453 struct lpfc_hba *phba = hlist_entry_safe(node, struct lpfc_hba, cpuhp);
11454 struct lpfc_queue *eq, *next;
11455 LIST_HEAD(eqlist);
11456 int retval;
11457
11458 if (!phba) {
11459 WARN_ONCE(!phba, "cpu: %u. phba:NULL", raw_smp_processor_id());
11460 return 0;
11461 }
11462
11463 if (__lpfc_cpuhp_checks(phba, &retval))
11464 return retval;
11465
dcaa2136
JS
11466 lpfc_irq_rebalance(phba, cpu, true);
11467
a99c8074
JS
11468 retval = lpfc_cpuhp_get_eq(phba, cpu, &eqlist);
11469 if (retval)
11470 return retval;
93a4d6f4
JS
11471
11472 /* start polling on these eq's */
11473 list_for_each_entry_safe(eq, next, &eqlist, _poll_list) {
11474 list_del_init(&eq->_poll_list);
11475 lpfc_sli4_start_polling(eq);
11476 }
11477
11478 return 0;
11479}
11480
11481static int lpfc_cpu_online(unsigned int cpu, struct hlist_node *node)
11482{
11483 struct lpfc_hba *phba = hlist_entry_safe(node, struct lpfc_hba, cpuhp);
11484 struct lpfc_queue *eq, *next;
11485 unsigned int n;
11486 int retval;
11487
11488 if (!phba) {
11489 WARN_ONCE(!phba, "cpu: %u. phba:NULL", raw_smp_processor_id());
11490 return 0;
11491 }
11492
11493 if (__lpfc_cpuhp_checks(phba, &retval))
11494 return retval;
11495
dcaa2136
JS
11496 lpfc_irq_rebalance(phba, cpu, false);
11497
93a4d6f4
JS
11498 list_for_each_entry_safe(eq, next, &phba->poll_list, _poll_list) {
11499 n = lpfc_find_cpu_handle(phba, eq->hdwq, LPFC_FIND_BY_HDWQ);
11500 if (n == cpu)
11501 lpfc_sli4_stop_polling(eq);
11502 }
11503
11504 return 0;
11505}
11506
da0436e9
JS
11507/**
11508 * lpfc_sli4_enable_msix - Enable MSI-X interrupt mode to SLI-4 device
11509 * @phba: pointer to lpfc hba data structure.
11510 *
11511 * This routine is invoked to enable the MSI-X interrupt vectors to device
dcaa2136
JS
11512 * with SLI-4 interface spec. It also allocates MSI-X vectors and maps them
11513 * to cpus on the system.
11514 *
11515 * When cfg_irq_numa is enabled, the adapter will only allocate vectors for
11516 * the number of cpus on the same numa node as this adapter. The vectors are
11517 * allocated without requesting OS affinity mapping. A vector will be
11518 * allocated and assigned to each online and offline cpu. If the cpu is
11519 * online, then affinity will be set to that cpu. If the cpu is offline, then
11520 * affinity will be set to the nearest peer cpu within the numa node that is
11521 * online. If there are no online cpus within the numa node, affinity is not
11522 * assigned and the OS may do as it pleases. Note: cpu vector affinity mapping
11523 * is consistent with the way cpu online/offline is handled when cfg_irq_numa is
11524 * configured.
11525 *
11526 * If numa mode is not enabled and there is more than 1 vector allocated, then
11527 * the driver relies on the managed irq interface where the OS assigns vector to
11528 * cpu affinity. The driver will then use that affinity mapping to setup its
11529 * cpu mapping table.
da0436e9
JS
11530 *
11531 * Return codes
af901ca1 11532 * 0 - successful
da0436e9
JS
11533 * other values - error
11534 **/
11535static int
11536lpfc_sli4_enable_msix(struct lpfc_hba *phba)
11537{
75baf696 11538 int vectors, rc, index;
b83d005e 11539 char *name;
3048e3e8 11540 const struct cpumask *aff_mask = NULL;
dcaa2136 11541 unsigned int cpu = 0, cpu_cnt = 0, cpu_select = nr_cpu_ids;
17105d95 11542 struct lpfc_vector_map_info *cpup;
dcaa2136
JS
11543 struct lpfc_hba_eq_hdl *eqhdl;
11544 const struct cpumask *maskp;
dcaa2136 11545 unsigned int flags = PCI_IRQ_MSIX;
da0436e9
JS
11546
11547 /* Set up MSI-X multi-message vectors */
6a828b0f 11548 vectors = phba->cfg_irq_chann;
45ffac19 11549
3048e3e8
DK
11550 if (phba->irq_chann_mode != NORMAL_MODE)
11551 aff_mask = &phba->sli4_hba.irq_aff_mask;
11552
11553 if (aff_mask) {
11554 cpu_cnt = cpumask_weight(aff_mask);
dcaa2136
JS
11555 vectors = min(phba->cfg_irq_chann, cpu_cnt);
11556
3048e3e8
DK
11557 /* cpu: iterates over aff_mask including offline or online
11558 * cpu_select: iterates over online aff_mask to set affinity
dcaa2136 11559 */
3048e3e8
DK
11560 cpu = cpumask_first(aff_mask);
11561 cpu_select = lpfc_next_online_cpu(aff_mask, cpu);
dcaa2136
JS
11562 } else {
11563 flags |= PCI_IRQ_AFFINITY;
11564 }
11565
11566 rc = pci_alloc_irq_vectors(phba->pcidev, 1, vectors, flags);
4f871e1b 11567 if (rc < 0) {
da0436e9
JS
11568 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11569 "0484 PCI enable MSI-X failed (%d)\n", rc);
029165ac 11570 goto vec_fail_out;
da0436e9 11571 }
4f871e1b 11572 vectors = rc;
75baf696 11573
7bb03bbf 11574 /* Assign MSI-X vectors to interrupt handlers */
67d12733 11575 for (index = 0; index < vectors; index++) {
dcaa2136
JS
11576 eqhdl = lpfc_get_eq_hdl(index);
11577 name = eqhdl->handler_name;
b83d005e
JS
11578 memset(name, 0, LPFC_SLI4_HANDLER_NAME_SZ);
11579 snprintf(name, LPFC_SLI4_HANDLER_NAME_SZ,
4305f183 11580 LPFC_DRIVER_HANDLER_NAME"%d", index);
da0436e9 11581
dcaa2136 11582 eqhdl->idx = index;
7370d10a
JS
11583 rc = request_irq(pci_irq_vector(phba->pcidev, index),
11584 &lpfc_sli4_hba_intr_handler, 0,
dcaa2136 11585 name, eqhdl);
da0436e9
JS
11586 if (rc) {
11587 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
11588 "0486 MSI-X fast-path (%d) "
11589 "request_irq failed (%d)\n", index, rc);
11590 goto cfg_fail_out;
11591 }
dcaa2136
JS
11592
11593 eqhdl->irq = pci_irq_vector(phba->pcidev, index);
11594
3048e3e8 11595 if (aff_mask) {
dcaa2136
JS
11596 /* If found a neighboring online cpu, set affinity */
11597 if (cpu_select < nr_cpu_ids)
11598 lpfc_irq_set_aff(eqhdl, cpu_select);
11599
11600 /* Assign EQ to cpu_map */
11601 lpfc_assign_eq_map_info(phba, index,
11602 LPFC_CPU_FIRST_IRQ,
11603 cpu);
11604
3048e3e8
DK
11605 /* Iterate to next offline or online cpu in aff_mask */
11606 cpu = cpumask_next(cpu, aff_mask);
dcaa2136 11607
3048e3e8
DK
11608 /* Find next online cpu in aff_mask to set affinity */
11609 cpu_select = lpfc_next_online_cpu(aff_mask, cpu);
dcaa2136
JS
11610 } else if (vectors == 1) {
11611 cpu = cpumask_first(cpu_present_mask);
11612 lpfc_assign_eq_map_info(phba, index, LPFC_CPU_FIRST_IRQ,
11613 cpu);
11614 } else {
11615 maskp = pci_irq_get_affinity(phba->pcidev, index);
11616
dcaa2136
JS
11617 /* Loop through all CPUs associated with vector index */
11618 for_each_cpu_and(cpu, maskp, cpu_present_mask) {
17105d95
DK
11619 cpup = &phba->sli4_hba.cpu_map[cpu];
11620
dcaa2136
JS
11621 /* If this is the first CPU thats assigned to
11622 * this vector, set LPFC_CPU_FIRST_IRQ.
17105d95
DK
11623 *
11624 * With certain platforms its possible that irq
11625 * vectors are affinitized to all the cpu's.
11626 * This can result in each cpu_map.eq to be set
11627 * to the last vector, resulting in overwrite
11628 * of all the previous cpu_map.eq. Ensure that
11629 * each vector receives a place in cpu_map.
11630 * Later call to lpfc_cpu_affinity_check will
11631 * ensure we are nicely balanced out.
dcaa2136 11632 */
17105d95
DK
11633 if (cpup->eq != LPFC_VECTOR_MAP_EMPTY)
11634 continue;
dcaa2136 11635 lpfc_assign_eq_map_info(phba, index,
17105d95 11636 LPFC_CPU_FIRST_IRQ,
dcaa2136 11637 cpu);
17105d95 11638 break;
dcaa2136
JS
11639 }
11640 }
da0436e9
JS
11641 }
11642
6a828b0f 11643 if (vectors != phba->cfg_irq_chann) {
372c187b 11644 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
82c3e9ba
JS
11645 "3238 Reducing IO channels to match number of "
11646 "MSI-X vectors, requested %d got %d\n",
6a828b0f
JS
11647 phba->cfg_irq_chann, vectors);
11648 if (phba->cfg_irq_chann > vectors)
11649 phba->cfg_irq_chann = vectors;
82c3e9ba 11650 }
7bb03bbf 11651
da0436e9
JS
11652 return rc;
11653
11654cfg_fail_out:
11655 /* free the irq already requested */
dcaa2136
JS
11656 for (--index; index >= 0; index--) {
11657 eqhdl = lpfc_get_eq_hdl(index);
11658 lpfc_irq_clear_aff(eqhdl);
11659 irq_set_affinity_hint(eqhdl->irq, NULL);
11660 free_irq(eqhdl->irq, eqhdl);
11661 }
da0436e9 11662
da0436e9 11663 /* Unconfigure MSI-X capability structure */
45ffac19 11664 pci_free_irq_vectors(phba->pcidev);
029165ac
AG
11665
11666vec_fail_out:
da0436e9
JS
11667 return rc;
11668}
11669
da0436e9
JS
11670/**
11671 * lpfc_sli4_enable_msi - Enable MSI interrupt mode to SLI-4 device
11672 * @phba: pointer to lpfc hba data structure.
11673 *
11674 * This routine is invoked to enable the MSI interrupt mode to device with
07b1b914
JS
11675 * SLI-4 interface spec. The kernel function pci_alloc_irq_vectors() is
11676 * called to enable the MSI vector. The device driver is responsible for
11677 * calling the request_irq() to register MSI vector with a interrupt the
11678 * handler, which is done in this function.
da0436e9
JS
11679 *
11680 * Return codes
af901ca1 11681 * 0 - successful
da0436e9
JS
11682 * other values - error
11683 **/
11684static int
11685lpfc_sli4_enable_msi(struct lpfc_hba *phba)
11686{
11687 int rc, index;
dcaa2136
JS
11688 unsigned int cpu;
11689 struct lpfc_hba_eq_hdl *eqhdl;
da0436e9 11690
07b1b914
JS
11691 rc = pci_alloc_irq_vectors(phba->pcidev, 1, 1,
11692 PCI_IRQ_MSI | PCI_IRQ_AFFINITY);
11693 if (rc > 0)
da0436e9
JS
11694 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11695 "0487 PCI enable MSI mode success.\n");
11696 else {
11697 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11698 "0488 PCI enable MSI mode failed (%d)\n", rc);
07b1b914 11699 return rc ? rc : -1;
da0436e9
JS
11700 }
11701
11702 rc = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
ed243d37 11703 0, LPFC_DRIVER_NAME, phba);
da0436e9 11704 if (rc) {
07b1b914 11705 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
11706 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
11707 "0490 MSI request_irq failed (%d)\n", rc);
75baf696 11708 return rc;
da0436e9
JS
11709 }
11710
dcaa2136
JS
11711 eqhdl = lpfc_get_eq_hdl(0);
11712 eqhdl->irq = pci_irq_vector(phba->pcidev, 0);
11713
11714 cpu = cpumask_first(cpu_present_mask);
11715 lpfc_assign_eq_map_info(phba, 0, LPFC_CPU_FIRST_IRQ, cpu);
11716
6a828b0f 11717 for (index = 0; index < phba->cfg_irq_chann; index++) {
dcaa2136
JS
11718 eqhdl = lpfc_get_eq_hdl(index);
11719 eqhdl->idx = index;
da0436e9
JS
11720 }
11721
75baf696 11722 return 0;
da0436e9
JS
11723}
11724
da0436e9
JS
11725/**
11726 * lpfc_sli4_enable_intr - Enable device interrupt to SLI-4 device
11727 * @phba: pointer to lpfc hba data structure.
fe614acd 11728 * @cfg_mode: Interrupt configuration mode (INTx, MSI or MSI-X).
da0436e9
JS
11729 *
11730 * This routine is invoked to enable device interrupt and associate driver's
11731 * interrupt handler(s) to interrupt vector(s) to device with SLI-4
11732 * interface spec. Depends on the interrupt mode configured to the driver,
11733 * the driver will try to fallback from the configured interrupt mode to an
11734 * interrupt mode which is supported by the platform, kernel, and device in
11735 * the order of:
11736 * MSI-X -> MSI -> IRQ.
11737 *
11738 * Return codes
af901ca1 11739 * 0 - successful
da0436e9
JS
11740 * other values - error
11741 **/
11742static uint32_t
11743lpfc_sli4_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
11744{
11745 uint32_t intr_mode = LPFC_INTR_ERROR;
895427bd 11746 int retval, idx;
da0436e9
JS
11747
11748 if (cfg_mode == 2) {
11749 /* Preparation before conf_msi mbox cmd */
11750 retval = 0;
11751 if (!retval) {
11752 /* Now, try to enable MSI-X interrupt mode */
11753 retval = lpfc_sli4_enable_msix(phba);
11754 if (!retval) {
11755 /* Indicate initialization to MSI-X mode */
11756 phba->intr_type = MSIX;
11757 intr_mode = 2;
11758 }
11759 }
11760 }
11761
11762 /* Fallback to MSI if MSI-X initialization failed */
11763 if (cfg_mode >= 1 && phba->intr_type == NONE) {
11764 retval = lpfc_sli4_enable_msi(phba);
11765 if (!retval) {
11766 /* Indicate initialization to MSI mode */
11767 phba->intr_type = MSI;
11768 intr_mode = 1;
11769 }
11770 }
11771
11772 /* Fallback to INTx if both MSI-X/MSI initalization failed */
11773 if (phba->intr_type == NONE) {
11774 retval = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
11775 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
11776 if (!retval) {
895427bd 11777 struct lpfc_hba_eq_hdl *eqhdl;
dcaa2136 11778 unsigned int cpu;
895427bd 11779
da0436e9
JS
11780 /* Indicate initialization to INTx mode */
11781 phba->intr_type = INTx;
11782 intr_mode = 0;
895427bd 11783
dcaa2136
JS
11784 eqhdl = lpfc_get_eq_hdl(0);
11785 eqhdl->irq = pci_irq_vector(phba->pcidev, 0);
11786
11787 cpu = cpumask_first(cpu_present_mask);
11788 lpfc_assign_eq_map_info(phba, 0, LPFC_CPU_FIRST_IRQ,
11789 cpu);
6a828b0f 11790 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
dcaa2136 11791 eqhdl = lpfc_get_eq_hdl(idx);
895427bd 11792 eqhdl->idx = idx;
1ba981fd 11793 }
da0436e9
JS
11794 }
11795 }
11796 return intr_mode;
11797}
11798
11799/**
11800 * lpfc_sli4_disable_intr - Disable device interrupt to SLI-4 device
11801 * @phba: pointer to lpfc hba data structure.
11802 *
11803 * This routine is invoked to disable device interrupt and disassociate
11804 * the driver's interrupt handler(s) from interrupt vector(s) to device
11805 * with SLI-4 interface spec. Depending on the interrupt mode, the driver
11806 * will release the interrupt vector(s) for the message signaled interrupt.
11807 **/
11808static void
11809lpfc_sli4_disable_intr(struct lpfc_hba *phba)
11810{
11811 /* Disable the currently initialized interrupt mode */
45ffac19
CH
11812 if (phba->intr_type == MSIX) {
11813 int index;
dcaa2136 11814 struct lpfc_hba_eq_hdl *eqhdl;
45ffac19
CH
11815
11816 /* Free up MSI-X multi-message vectors */
6a828b0f 11817 for (index = 0; index < phba->cfg_irq_chann; index++) {
dcaa2136
JS
11818 eqhdl = lpfc_get_eq_hdl(index);
11819 lpfc_irq_clear_aff(eqhdl);
11820 irq_set_affinity_hint(eqhdl->irq, NULL);
11821 free_irq(eqhdl->irq, eqhdl);
b3295c2a 11822 }
45ffac19 11823 } else {
da0436e9 11824 free_irq(phba->pcidev->irq, phba);
45ffac19
CH
11825 }
11826
11827 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
11828
11829 /* Reset interrupt management states */
11830 phba->intr_type = NONE;
11831 phba->sli.slistat.sli_intr = 0;
da0436e9
JS
11832}
11833
11834/**
11835 * lpfc_unset_hba - Unset SLI3 hba device initialization
11836 * @phba: pointer to lpfc hba data structure.
11837 *
11838 * This routine is invoked to unset the HBA device initialization steps to
11839 * a device with SLI-3 interface spec.
11840 **/
11841static void
11842lpfc_unset_hba(struct lpfc_hba *phba)
11843{
11844 struct lpfc_vport *vport = phba->pport;
11845 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
11846
11847 spin_lock_irq(shost->host_lock);
11848 vport->load_flag |= FC_UNLOADING;
11849 spin_unlock_irq(shost->host_lock);
11850
72859909
JS
11851 kfree(phba->vpi_bmask);
11852 kfree(phba->vpi_ids);
11853
da0436e9
JS
11854 lpfc_stop_hba_timers(phba);
11855
11856 phba->pport->work_port_events = 0;
11857
11858 lpfc_sli_hba_down(phba);
11859
11860 lpfc_sli_brdrestart(phba);
11861
11862 lpfc_sli_disable_intr(phba);
11863
11864 return;
11865}
11866
5af5eee7
JS
11867/**
11868 * lpfc_sli4_xri_exchange_busy_wait - Wait for device XRI exchange busy
11869 * @phba: Pointer to HBA context object.
11870 *
11871 * This function is called in the SLI4 code path to wait for completion
11872 * of device's XRIs exchange busy. It will check the XRI exchange busy
11873 * on outstanding FCP and ELS I/Os every 10ms for up to 10 seconds; after
11874 * that, it will check the XRI exchange busy on outstanding FCP and ELS
11875 * I/Os every 30 seconds, log error message, and wait forever. Only when
11876 * all XRI exchange busy complete, the driver unload shall proceed with
11877 * invoking the function reset ioctl mailbox command to the CNA and the
11878 * the rest of the driver unload resource release.
11879 **/
11880static void
11881lpfc_sli4_xri_exchange_busy_wait(struct lpfc_hba *phba)
11882{
5e5b511d 11883 struct lpfc_sli4_hdw_queue *qp;
c00f62e6 11884 int idx, ccnt;
5af5eee7 11885 int wait_time = 0;
5e5b511d 11886 int io_xri_cmpl = 1;
86c67379 11887 int nvmet_xri_cmpl = 1;
5af5eee7
JS
11888 int els_xri_cmpl = list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
11889
c3725bdc
JS
11890 /* Driver just aborted IOs during the hba_unset process. Pause
11891 * here to give the HBA time to complete the IO and get entries
11892 * into the abts lists.
11893 */
11894 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1 * 5);
11895
11896 /* Wait for NVME pending IO to flush back to transport. */
11897 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
11898 lpfc_nvme_wait_for_io_drain(phba);
11899
5e5b511d 11900 ccnt = 0;
5e5b511d
JS
11901 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
11902 qp = &phba->sli4_hba.hdwq[idx];
c00f62e6
JS
11903 io_xri_cmpl = list_empty(&qp->lpfc_abts_io_buf_list);
11904 if (!io_xri_cmpl) /* if list is NOT empty */
11905 ccnt++;
5e5b511d
JS
11906 }
11907 if (ccnt)
11908 io_xri_cmpl = 0;
5e5b511d 11909
86c67379 11910 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
86c67379
JS
11911 nvmet_xri_cmpl =
11912 list_empty(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
11913 }
895427bd 11914
c00f62e6 11915 while (!els_xri_cmpl || !io_xri_cmpl || !nvmet_xri_cmpl) {
5af5eee7 11916 if (wait_time > LPFC_XRI_EXCH_BUSY_WAIT_TMO) {
68c9b55d 11917 if (!nvmet_xri_cmpl)
372c187b 11918 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
68c9b55d
JS
11919 "6424 NVMET XRI exchange busy "
11920 "wait time: %d seconds.\n",
11921 wait_time/1000);
5e5b511d 11922 if (!io_xri_cmpl)
372c187b 11923 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
c00f62e6 11924 "6100 IO XRI exchange busy "
5af5eee7
JS
11925 "wait time: %d seconds.\n",
11926 wait_time/1000);
11927 if (!els_xri_cmpl)
372c187b 11928 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
5af5eee7
JS
11929 "2878 ELS XRI exchange busy "
11930 "wait time: %d seconds.\n",
11931 wait_time/1000);
11932 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T2);
11933 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T2;
11934 } else {
11935 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1);
11936 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T1;
11937 }
5e5b511d
JS
11938
11939 ccnt = 0;
5e5b511d
JS
11940 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
11941 qp = &phba->sli4_hba.hdwq[idx];
c00f62e6
JS
11942 io_xri_cmpl = list_empty(
11943 &qp->lpfc_abts_io_buf_list);
11944 if (!io_xri_cmpl) /* if list is NOT empty */
11945 ccnt++;
5e5b511d
JS
11946 }
11947 if (ccnt)
11948 io_xri_cmpl = 0;
5e5b511d 11949
86c67379 11950 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
86c67379
JS
11951 nvmet_xri_cmpl = list_empty(
11952 &phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
11953 }
5af5eee7
JS
11954 els_xri_cmpl =
11955 list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
f358dd0c 11956
5af5eee7
JS
11957 }
11958}
11959
da0436e9
JS
11960/**
11961 * lpfc_sli4_hba_unset - Unset the fcoe hba
11962 * @phba: Pointer to HBA context object.
11963 *
11964 * This function is called in the SLI4 code path to reset the HBA's FCoE
11965 * function. The caller is not required to hold any lock. This routine
11966 * issues PCI function reset mailbox command to reset the FCoE function.
11967 * At the end of the function, it calls lpfc_hba_down_post function to
11968 * free any pending commands.
11969 **/
11970static void
11971lpfc_sli4_hba_unset(struct lpfc_hba *phba)
11972{
11973 int wait_cnt = 0;
11974 LPFC_MBOXQ_t *mboxq;
912e3acd 11975 struct pci_dev *pdev = phba->pcidev;
da0436e9
JS
11976
11977 lpfc_stop_hba_timers(phba);
cdb42bec
JS
11978 if (phba->pport)
11979 phba->sli4_hba.intr_enable = 0;
da0436e9
JS
11980
11981 /*
11982 * Gracefully wait out the potential current outstanding asynchronous
11983 * mailbox command.
11984 */
11985
11986 /* First, block any pending async mailbox command from posted */
11987 spin_lock_irq(&phba->hbalock);
11988 phba->sli.sli_flag |= LPFC_SLI_ASYNC_MBX_BLK;
11989 spin_unlock_irq(&phba->hbalock);
11990 /* Now, trying to wait it out if we can */
11991 while (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
11992 msleep(10);
11993 if (++wait_cnt > LPFC_ACTIVE_MBOX_WAIT_CNT)
11994 break;
11995 }
11996 /* Forcefully release the outstanding mailbox command if timed out */
11997 if (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
11998 spin_lock_irq(&phba->hbalock);
11999 mboxq = phba->sli.mbox_active;
12000 mboxq->u.mb.mbxStatus = MBX_NOT_FINISHED;
12001 __lpfc_mbox_cmpl_put(phba, mboxq);
12002 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
12003 phba->sli.mbox_active = NULL;
12004 spin_unlock_irq(&phba->hbalock);
12005 }
12006
5af5eee7
JS
12007 /* Abort all iocbs associated with the hba */
12008 lpfc_sli_hba_iocb_abort(phba);
12009
12010 /* Wait for completion of device XRI exchange busy */
12011 lpfc_sli4_xri_exchange_busy_wait(phba);
12012
93a4d6f4 12013 /* per-phba callback de-registration for hotplug event */
46da547e
SP
12014 if (phba->pport)
12015 lpfc_cpuhp_remove(phba);
93a4d6f4 12016
da0436e9
JS
12017 /* Disable PCI subsystem interrupt */
12018 lpfc_sli4_disable_intr(phba);
12019
912e3acd
JS
12020 /* Disable SR-IOV if enabled */
12021 if (phba->cfg_sriov_nr_virtfn)
12022 pci_disable_sriov(pdev);
12023
da0436e9
JS
12024 /* Stop kthread signal shall trigger work_done one more time */
12025 kthread_stop(phba->worker_thread);
12026
d2cc9bcd 12027 /* Disable FW logging to host memory */
1165a5c2 12028 lpfc_ras_stop_fwlog(phba);
d2cc9bcd 12029
d1f525aa
JS
12030 /* Unset the queues shared with the hardware then release all
12031 * allocated resources.
12032 */
12033 lpfc_sli4_queue_unset(phba);
12034 lpfc_sli4_queue_destroy(phba);
12035
3677a3a7
JS
12036 /* Reset SLI4 HBA FCoE function */
12037 lpfc_pci_function_reset(phba);
12038
1165a5c2
JS
12039 /* Free RAS DMA memory */
12040 if (phba->ras_fwlog.ras_enabled)
12041 lpfc_sli4_ras_dma_free(phba);
12042
da0436e9 12043 /* Stop the SLI4 device port */
1ffdd2c0
JS
12044 if (phba->pport)
12045 phba->pport->work_port_events = 0;
da0436e9
JS
12046}
12047
28baac74
JS
12048 /**
12049 * lpfc_pc_sli4_params_get - Get the SLI4_PARAMS port capabilities.
12050 * @phba: Pointer to HBA context object.
12051 * @mboxq: Pointer to the mailboxq memory for the mailbox command response.
12052 *
12053 * This function is called in the SLI4 code path to read the port's
12054 * sli4 capabilities.
12055 *
12056 * This function may be be called from any context that can block-wait
12057 * for the completion. The expectation is that this routine is called
12058 * typically from probe_one or from the online routine.
12059 **/
12060int
12061lpfc_pc_sli4_params_get(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
12062{
12063 int rc;
12064 struct lpfc_mqe *mqe;
12065 struct lpfc_pc_sli4_params *sli4_params;
12066 uint32_t mbox_tmo;
12067
12068 rc = 0;
12069 mqe = &mboxq->u.mqe;
12070
12071 /* Read the port's SLI4 Parameters port capabilities */
fedd3b7b 12072 lpfc_pc_sli4_params(mboxq);
28baac74
JS
12073 if (!phba->sli4_hba.intr_enable)
12074 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
12075 else {
a183a15f 12076 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
28baac74
JS
12077 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
12078 }
12079
12080 if (unlikely(rc))
12081 return 1;
12082
12083 sli4_params = &phba->sli4_hba.pc_sli4_params;
12084 sli4_params->if_type = bf_get(if_type, &mqe->un.sli4_params);
12085 sli4_params->sli_rev = bf_get(sli_rev, &mqe->un.sli4_params);
12086 sli4_params->sli_family = bf_get(sli_family, &mqe->un.sli4_params);
12087 sli4_params->featurelevel_1 = bf_get(featurelevel_1,
12088 &mqe->un.sli4_params);
12089 sli4_params->featurelevel_2 = bf_get(featurelevel_2,
12090 &mqe->un.sli4_params);
12091 sli4_params->proto_types = mqe->un.sli4_params.word3;
12092 sli4_params->sge_supp_len = mqe->un.sli4_params.sge_supp_len;
12093 sli4_params->if_page_sz = bf_get(if_page_sz, &mqe->un.sli4_params);
12094 sli4_params->rq_db_window = bf_get(rq_db_window, &mqe->un.sli4_params);
12095 sli4_params->loopbk_scope = bf_get(loopbk_scope, &mqe->un.sli4_params);
12096 sli4_params->eq_pages_max = bf_get(eq_pages, &mqe->un.sli4_params);
12097 sli4_params->eqe_size = bf_get(eqe_size, &mqe->un.sli4_params);
12098 sli4_params->cq_pages_max = bf_get(cq_pages, &mqe->un.sli4_params);
12099 sli4_params->cqe_size = bf_get(cqe_size, &mqe->un.sli4_params);
12100 sli4_params->mq_pages_max = bf_get(mq_pages, &mqe->un.sli4_params);
12101 sli4_params->mqe_size = bf_get(mqe_size, &mqe->un.sli4_params);
12102 sli4_params->mq_elem_cnt = bf_get(mq_elem_cnt, &mqe->un.sli4_params);
12103 sli4_params->wq_pages_max = bf_get(wq_pages, &mqe->un.sli4_params);
12104 sli4_params->wqe_size = bf_get(wqe_size, &mqe->un.sli4_params);
12105 sli4_params->rq_pages_max = bf_get(rq_pages, &mqe->un.sli4_params);
12106 sli4_params->rqe_size = bf_get(rqe_size, &mqe->un.sli4_params);
12107 sli4_params->hdr_pages_max = bf_get(hdr_pages, &mqe->un.sli4_params);
12108 sli4_params->hdr_size = bf_get(hdr_size, &mqe->un.sli4_params);
12109 sli4_params->hdr_pp_align = bf_get(hdr_pp_align, &mqe->un.sli4_params);
12110 sli4_params->sgl_pages_max = bf_get(sgl_pages, &mqe->un.sli4_params);
12111 sli4_params->sgl_pp_align = bf_get(sgl_pp_align, &mqe->un.sli4_params);
0558056c
JS
12112
12113 /* Make sure that sge_supp_len can be handled by the driver */
12114 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
12115 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
12116
28baac74
JS
12117 return rc;
12118}
12119
fedd3b7b
JS
12120/**
12121 * lpfc_get_sli4_parameters - Get the SLI4 Config PARAMETERS.
12122 * @phba: Pointer to HBA context object.
12123 * @mboxq: Pointer to the mailboxq memory for the mailbox command response.
12124 *
12125 * This function is called in the SLI4 code path to read the port's
12126 * sli4 capabilities.
12127 *
12128 * This function may be be called from any context that can block-wait
12129 * for the completion. The expectation is that this routine is called
12130 * typically from probe_one or from the online routine.
12131 **/
12132int
12133lpfc_get_sli4_parameters(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
12134{
12135 int rc;
12136 struct lpfc_mqe *mqe = &mboxq->u.mqe;
12137 struct lpfc_pc_sli4_params *sli4_params;
a183a15f 12138 uint32_t mbox_tmo;
fedd3b7b 12139 int length;
bf316c78 12140 bool exp_wqcq_pages = true;
fedd3b7b
JS
12141 struct lpfc_sli4_parameters *mbx_sli4_parameters;
12142
6d368e53
JS
12143 /*
12144 * By default, the driver assumes the SLI4 port requires RPI
12145 * header postings. The SLI4_PARAM response will correct this
12146 * assumption.
12147 */
12148 phba->sli4_hba.rpi_hdrs_in_use = 1;
12149
fedd3b7b
JS
12150 /* Read the port's SLI4 Config Parameters */
12151 length = (sizeof(struct lpfc_mbx_get_sli4_parameters) -
12152 sizeof(struct lpfc_sli4_cfg_mhdr));
12153 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
12154 LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS,
12155 length, LPFC_SLI4_MBX_EMBED);
12156 if (!phba->sli4_hba.intr_enable)
12157 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
a183a15f
JS
12158 else {
12159 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
12160 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
12161 }
fedd3b7b
JS
12162 if (unlikely(rc))
12163 return rc;
12164 sli4_params = &phba->sli4_hba.pc_sli4_params;
12165 mbx_sli4_parameters = &mqe->un.get_sli4_parameters.sli4_parameters;
12166 sli4_params->if_type = bf_get(cfg_if_type, mbx_sli4_parameters);
12167 sli4_params->sli_rev = bf_get(cfg_sli_rev, mbx_sli4_parameters);
12168 sli4_params->sli_family = bf_get(cfg_sli_family, mbx_sli4_parameters);
12169 sli4_params->featurelevel_1 = bf_get(cfg_sli_hint_1,
12170 mbx_sli4_parameters);
12171 sli4_params->featurelevel_2 = bf_get(cfg_sli_hint_2,
12172 mbx_sli4_parameters);
12173 if (bf_get(cfg_phwq, mbx_sli4_parameters))
12174 phba->sli3_options |= LPFC_SLI4_PHWQ_ENABLED;
12175 else
12176 phba->sli3_options &= ~LPFC_SLI4_PHWQ_ENABLED;
12177 sli4_params->sge_supp_len = mbx_sli4_parameters->sge_supp_len;
12178 sli4_params->loopbk_scope = bf_get(loopbk_scope, mbx_sli4_parameters);
1ba981fd 12179 sli4_params->oas_supported = bf_get(cfg_oas, mbx_sli4_parameters);
fedd3b7b
JS
12180 sli4_params->cqv = bf_get(cfg_cqv, mbx_sli4_parameters);
12181 sli4_params->mqv = bf_get(cfg_mqv, mbx_sli4_parameters);
12182 sli4_params->wqv = bf_get(cfg_wqv, mbx_sli4_parameters);
12183 sli4_params->rqv = bf_get(cfg_rqv, mbx_sli4_parameters);
7365f6fd
JS
12184 sli4_params->eqav = bf_get(cfg_eqav, mbx_sli4_parameters);
12185 sli4_params->cqav = bf_get(cfg_cqav, mbx_sli4_parameters);
0c651878 12186 sli4_params->wqsize = bf_get(cfg_wqsize, mbx_sli4_parameters);
66e9e6bf 12187 sli4_params->bv1s = bf_get(cfg_bv1s, mbx_sli4_parameters);
83c6cb1a 12188 sli4_params->pls = bf_get(cfg_pvl, mbx_sli4_parameters);
fedd3b7b
JS
12189 sli4_params->sgl_pages_max = bf_get(cfg_sgl_page_cnt,
12190 mbx_sli4_parameters);
895427bd 12191 sli4_params->wqpcnt = bf_get(cfg_wqpcnt, mbx_sli4_parameters);
fedd3b7b
JS
12192 sli4_params->sgl_pp_align = bf_get(cfg_sgl_pp_align,
12193 mbx_sli4_parameters);
6d368e53
JS
12194 phba->sli4_hba.extents_in_use = bf_get(cfg_ext, mbx_sli4_parameters);
12195 phba->sli4_hba.rpi_hdrs_in_use = bf_get(cfg_hdrr, mbx_sli4_parameters);
c15e0704 12196
d79c9e9d
JS
12197 /* Check for Extended Pre-Registered SGL support */
12198 phba->cfg_xpsgl = bf_get(cfg_xpsgl, mbx_sli4_parameters);
12199
c15e0704
JS
12200 /* Check for firmware nvme support */
12201 rc = (bf_get(cfg_nvme, mbx_sli4_parameters) &&
12202 bf_get(cfg_xib, mbx_sli4_parameters));
12203
12204 if (rc) {
12205 /* Save this to indicate the Firmware supports NVME */
12206 sli4_params->nvme = 1;
12207
12208 /* Firmware NVME support, check driver FC4 NVME support */
12209 if (phba->cfg_enable_fc4_type == LPFC_ENABLE_FCP) {
12210 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME,
12211 "6133 Disabling NVME support: "
12212 "FC4 type not supported: x%x\n",
12213 phba->cfg_enable_fc4_type);
12214 goto fcponly;
12215 }
12216 } else {
12217 /* No firmware NVME support, check driver FC4 NVME support */
12218 sli4_params->nvme = 0;
12219 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
12220 lpfc_printf_log(phba, KERN_ERR, LOG_INIT | LOG_NVME,
12221 "6101 Disabling NVME support: Not "
12222 "supported by firmware (%d %d) x%x\n",
12223 bf_get(cfg_nvme, mbx_sli4_parameters),
12224 bf_get(cfg_xib, mbx_sli4_parameters),
12225 phba->cfg_enable_fc4_type);
12226fcponly:
12227 phba->nvme_support = 0;
12228 phba->nvmet_support = 0;
12229 phba->cfg_nvmet_mrq = 0;
6a224b47 12230 phba->cfg_nvme_seg_cnt = 0;
c15e0704
JS
12231
12232 /* If no FC4 type support, move to just SCSI support */
12233 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
12234 return -ENODEV;
12235 phba->cfg_enable_fc4_type = LPFC_ENABLE_FCP;
12236 }
895427bd 12237 }
0558056c 12238
c26c265b 12239 /* If the NVME FC4 type is enabled, scale the sg_seg_cnt to
a5f7337f 12240 * accommodate 512K and 1M IOs in a single nvme buf.
c26c265b 12241 */
a5f7337f 12242 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
c26c265b 12243 phba->cfg_sg_seg_cnt = LPFC_MAX_NVME_SEG_CNT;
c26c265b 12244
414abe0a
JS
12245 /* Only embed PBDE for if_type 6, PBDE support requires xib be set */
12246 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) !=
12247 LPFC_SLI_INTF_IF_TYPE_6) || (!bf_get(cfg_xib, mbx_sli4_parameters)))
12248 phba->cfg_enable_pbde = 0;
0bc2b7c5 12249
20aefac3
JS
12250 /*
12251 * To support Suppress Response feature we must satisfy 3 conditions.
12252 * lpfc_suppress_rsp module parameter must be set (default).
12253 * In SLI4-Parameters Descriptor:
12254 * Extended Inline Buffers (XIB) must be supported.
12255 * Suppress Response IU Not Supported (SRIUNS) must NOT be supported
12256 * (double negative).
12257 */
12258 if (phba->cfg_suppress_rsp && bf_get(cfg_xib, mbx_sli4_parameters) &&
12259 !(bf_get(cfg_nosr, mbx_sli4_parameters)))
f358dd0c 12260 phba->sli.sli_flag |= LPFC_SLI_SUPPRESS_RSP;
20aefac3
JS
12261 else
12262 phba->cfg_suppress_rsp = 0;
f358dd0c 12263
0cf07f84
JS
12264 if (bf_get(cfg_eqdr, mbx_sli4_parameters))
12265 phba->sli.sli_flag |= LPFC_SLI_USE_EQDR;
12266
0558056c
JS
12267 /* Make sure that sge_supp_len can be handled by the driver */
12268 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
12269 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
12270
b5c53958 12271 /*
c176ffa0
JS
12272 * Check whether the adapter supports an embedded copy of the
12273 * FCP CMD IU within the WQE for FCP_Ixxx commands. In order
12274 * to use this option, 128-byte WQEs must be used.
b5c53958
JS
12275 */
12276 if (bf_get(cfg_ext_embed_cb, mbx_sli4_parameters))
12277 phba->fcp_embed_io = 1;
12278 else
12279 phba->fcp_embed_io = 0;
7bdedb34 12280
0bc2b7c5 12281 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME,
414abe0a 12282 "6422 XIB %d PBDE %d: FCP %d NVME %d %d %d\n",
0bc2b7c5 12283 bf_get(cfg_xib, mbx_sli4_parameters),
414abe0a
JS
12284 phba->cfg_enable_pbde,
12285 phba->fcp_embed_io, phba->nvme_support,
4e565cf0 12286 phba->cfg_nvme_embed_cmd, phba->cfg_suppress_rsp);
0bc2b7c5 12287
bf316c78
JS
12288 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
12289 LPFC_SLI_INTF_IF_TYPE_2) &&
12290 (bf_get(lpfc_sli_intf_sli_family, &phba->sli4_hba.sli_intf) ==
c221768b 12291 LPFC_SLI_INTF_FAMILY_LNCR_A0))
bf316c78
JS
12292 exp_wqcq_pages = false;
12293
c176ffa0
JS
12294 if ((bf_get(cfg_cqpsize, mbx_sli4_parameters) & LPFC_CQ_16K_PAGE_SZ) &&
12295 (bf_get(cfg_wqpsize, mbx_sli4_parameters) & LPFC_WQ_16K_PAGE_SZ) &&
bf316c78 12296 exp_wqcq_pages &&
c176ffa0
JS
12297 (sli4_params->wqsize & LPFC_WQ_SZ128_SUPPORT))
12298 phba->enab_exp_wqcq_pages = 1;
12299 else
12300 phba->enab_exp_wqcq_pages = 0;
7bdedb34
JS
12301 /*
12302 * Check if the SLI port supports MDS Diagnostics
12303 */
12304 if (bf_get(cfg_mds_diags, mbx_sli4_parameters))
12305 phba->mds_diags_support = 1;
12306 else
12307 phba->mds_diags_support = 0;
d2cc9bcd 12308
0d8af096
JS
12309 /*
12310 * Check if the SLI port supports NSLER
12311 */
12312 if (bf_get(cfg_nsler, mbx_sli4_parameters))
12313 phba->nsler = 1;
12314 else
12315 phba->nsler = 0;
12316
8aaa7bcf
JS
12317 /* Save PB info for use during HBA setup */
12318 sli4_params->mi_ver = bf_get(cfg_mi_ver, mbx_sli4_parameters);
12319 sli4_params->mib_bde_cnt = bf_get(cfg_mib_bde_cnt, mbx_sli4_parameters);
12320 sli4_params->mib_size = mbx_sli4_parameters->mib_size;
12321 sli4_params->mi_value = LPFC_DFLT_MIB_VAL;
12322
12323 /* Next we check for Vendor MIB support */
12324 if (sli4_params->mi_ver && phba->cfg_enable_mi)
12325 phba->cfg_fdmi_on = LPFC_FDMI_SUPPORT;
12326
12327 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12328 "6461 MIB attr %d enable %d FDMI %d buf %d:%d\n",
12329 sli4_params->mi_ver, phba->cfg_enable_mi,
12330 sli4_params->mi_value, sli4_params->mib_bde_cnt,
12331 sli4_params->mib_size);
fedd3b7b
JS
12332 return 0;
12333}
12334
da0436e9
JS
12335/**
12336 * lpfc_pci_probe_one_s3 - PCI probe func to reg SLI-3 device to PCI subsystem.
12337 * @pdev: pointer to PCI device
12338 * @pid: pointer to PCI device identifier
12339 *
12340 * This routine is to be called to attach a device with SLI-3 interface spec
12341 * to the PCI subsystem. When an Emulex HBA with SLI-3 interface spec is
12342 * presented on PCI bus, the kernel PCI subsystem looks at PCI device-specific
12343 * information of the device and driver to see if the driver state that it can
12344 * support this kind of device. If the match is successful, the driver core
12345 * invokes this routine. If this routine determines it can claim the HBA, it
12346 * does all the initialization that it needs to do to handle the HBA properly.
12347 *
12348 * Return code
12349 * 0 - driver can claim the device
12350 * negative value - driver can not claim the device
12351 **/
6f039790 12352static int
da0436e9
JS
12353lpfc_pci_probe_one_s3(struct pci_dev *pdev, const struct pci_device_id *pid)
12354{
12355 struct lpfc_hba *phba;
12356 struct lpfc_vport *vport = NULL;
6669f9bb 12357 struct Scsi_Host *shost = NULL;
da0436e9
JS
12358 int error;
12359 uint32_t cfg_mode, intr_mode;
12360
12361 /* Allocate memory for HBA structure */
12362 phba = lpfc_hba_alloc(pdev);
12363 if (!phba)
12364 return -ENOMEM;
12365
12366 /* Perform generic PCI device enabling operation */
12367 error = lpfc_enable_pci_dev(phba);
079b5c91 12368 if (error)
da0436e9 12369 goto out_free_phba;
da0436e9
JS
12370
12371 /* Set up SLI API function jump table for PCI-device group-0 HBAs */
12372 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_LP);
12373 if (error)
12374 goto out_disable_pci_dev;
12375
12376 /* Set up SLI-3 specific device PCI memory space */
12377 error = lpfc_sli_pci_mem_setup(phba);
12378 if (error) {
12379 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12380 "1402 Failed to set up pci memory space.\n");
12381 goto out_disable_pci_dev;
12382 }
12383
da0436e9
JS
12384 /* Set up SLI-3 specific device driver resources */
12385 error = lpfc_sli_driver_resource_setup(phba);
12386 if (error) {
12387 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12388 "1404 Failed to set up driver resource.\n");
12389 goto out_unset_pci_mem_s3;
12390 }
12391
12392 /* Initialize and populate the iocb list per host */
d1f525aa 12393
da0436e9
JS
12394 error = lpfc_init_iocb_list(phba, LPFC_IOCB_LIST_CNT);
12395 if (error) {
12396 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12397 "1405 Failed to initialize iocb list.\n");
12398 goto out_unset_driver_resource_s3;
12399 }
12400
12401 /* Set up common device driver resources */
12402 error = lpfc_setup_driver_resource_phase2(phba);
12403 if (error) {
12404 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12405 "1406 Failed to set up driver resource.\n");
12406 goto out_free_iocb_list;
12407 }
12408
079b5c91
JS
12409 /* Get the default values for Model Name and Description */
12410 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
12411
da0436e9
JS
12412 /* Create SCSI host to the physical port */
12413 error = lpfc_create_shost(phba);
12414 if (error) {
12415 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12416 "1407 Failed to create scsi host.\n");
12417 goto out_unset_driver_resource;
12418 }
12419
12420 /* Configure sysfs attributes */
12421 vport = phba->pport;
12422 error = lpfc_alloc_sysfs_attr(vport);
12423 if (error) {
12424 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12425 "1476 Failed to allocate sysfs attr\n");
12426 goto out_destroy_shost;
12427 }
12428
6669f9bb 12429 shost = lpfc_shost_from_vport(vport); /* save shost for error cleanup */
da0436e9
JS
12430 /* Now, trying to enable interrupt and bring up the device */
12431 cfg_mode = phba->cfg_use_msi;
12432 while (true) {
12433 /* Put device to a known state before enabling interrupt */
12434 lpfc_stop_port(phba);
12435 /* Configure and enable interrupt */
12436 intr_mode = lpfc_sli_enable_intr(phba, cfg_mode);
12437 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 12438 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
12439 "0431 Failed to enable interrupt.\n");
12440 error = -ENODEV;
12441 goto out_free_sysfs_attr;
12442 }
12443 /* SLI-3 HBA setup */
12444 if (lpfc_sli_hba_setup(phba)) {
372c187b 12445 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
12446 "1477 Failed to set up hba\n");
12447 error = -ENODEV;
12448 goto out_remove_device;
12449 }
12450
12451 /* Wait 50ms for the interrupts of previous mailbox commands */
12452 msleep(50);
12453 /* Check active interrupts on message signaled interrupts */
12454 if (intr_mode == 0 ||
12455 phba->sli.slistat.sli_intr > LPFC_MSIX_VECTORS) {
12456 /* Log the current active interrupt mode */
12457 phba->intr_mode = intr_mode;
12458 lpfc_log_intr_mode(phba, intr_mode);
12459 break;
12460 } else {
12461 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12462 "0447 Configure interrupt mode (%d) "
12463 "failed active interrupt test.\n",
12464 intr_mode);
12465 /* Disable the current interrupt mode */
12466 lpfc_sli_disable_intr(phba);
12467 /* Try next level of interrupt mode */
12468 cfg_mode = --intr_mode;
12469 }
12470 }
12471
12472 /* Perform post initialization setup */
12473 lpfc_post_init_setup(phba);
12474
12475 /* Check if there are static vports to be created. */
12476 lpfc_create_static_vport(phba);
12477
12478 return 0;
12479
12480out_remove_device:
12481 lpfc_unset_hba(phba);
12482out_free_sysfs_attr:
12483 lpfc_free_sysfs_attr(vport);
12484out_destroy_shost:
12485 lpfc_destroy_shost(phba);
12486out_unset_driver_resource:
12487 lpfc_unset_driver_resource_phase2(phba);
12488out_free_iocb_list:
12489 lpfc_free_iocb_list(phba);
12490out_unset_driver_resource_s3:
12491 lpfc_sli_driver_resource_unset(phba);
12492out_unset_pci_mem_s3:
12493 lpfc_sli_pci_mem_unset(phba);
12494out_disable_pci_dev:
12495 lpfc_disable_pci_dev(phba);
6669f9bb
JS
12496 if (shost)
12497 scsi_host_put(shost);
da0436e9
JS
12498out_free_phba:
12499 lpfc_hba_free(phba);
12500 return error;
12501}
12502
12503/**
12504 * lpfc_pci_remove_one_s3 - PCI func to unreg SLI-3 device from PCI subsystem.
12505 * @pdev: pointer to PCI device
12506 *
12507 * This routine is to be called to disattach a device with SLI-3 interface
12508 * spec from PCI subsystem. When an Emulex HBA with SLI-3 interface spec is
12509 * removed from PCI bus, it performs all the necessary cleanup for the HBA
12510 * device to be removed from the PCI subsystem properly.
12511 **/
6f039790 12512static void
da0436e9
JS
12513lpfc_pci_remove_one_s3(struct pci_dev *pdev)
12514{
12515 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12516 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
12517 struct lpfc_vport **vports;
12518 struct lpfc_hba *phba = vport->phba;
12519 int i;
da0436e9
JS
12520
12521 spin_lock_irq(&phba->hbalock);
12522 vport->load_flag |= FC_UNLOADING;
12523 spin_unlock_irq(&phba->hbalock);
12524
12525 lpfc_free_sysfs_attr(vport);
12526
12527 /* Release all the vports against this physical port */
12528 vports = lpfc_create_vport_work_array(phba);
12529 if (vports != NULL)
587a37f6
JS
12530 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
12531 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
12532 continue;
da0436e9 12533 fc_vport_terminate(vports[i]->fc_vport);
587a37f6 12534 }
da0436e9
JS
12535 lpfc_destroy_vport_work_array(phba, vports);
12536
12537 /* Remove FC host and then SCSI host with the physical port */
12538 fc_remove_host(shost);
12539 scsi_remove_host(shost);
d613b6a7 12540
da0436e9
JS
12541 lpfc_cleanup(vport);
12542
12543 /*
12544 * Bring down the SLI Layer. This step disable all interrupts,
12545 * clears the rings, discards all mailbox commands, and resets
12546 * the HBA.
12547 */
12548
48e34d0f 12549 /* HBA interrupt will be disabled after this call */
da0436e9
JS
12550 lpfc_sli_hba_down(phba);
12551 /* Stop kthread signal shall trigger work_done one more time */
12552 kthread_stop(phba->worker_thread);
12553 /* Final cleanup of txcmplq and reset the HBA */
12554 lpfc_sli_brdrestart(phba);
12555
72859909
JS
12556 kfree(phba->vpi_bmask);
12557 kfree(phba->vpi_ids);
12558
da0436e9 12559 lpfc_stop_hba_timers(phba);
523128e5 12560 spin_lock_irq(&phba->port_list_lock);
da0436e9 12561 list_del_init(&vport->listentry);
523128e5 12562 spin_unlock_irq(&phba->port_list_lock);
da0436e9
JS
12563
12564 lpfc_debugfs_terminate(vport);
12565
912e3acd
JS
12566 /* Disable SR-IOV if enabled */
12567 if (phba->cfg_sriov_nr_virtfn)
12568 pci_disable_sriov(pdev);
12569
da0436e9
JS
12570 /* Disable interrupt */
12571 lpfc_sli_disable_intr(phba);
12572
da0436e9
JS
12573 scsi_host_put(shost);
12574
12575 /*
12576 * Call scsi_free before mem_free since scsi bufs are released to their
12577 * corresponding pools here.
12578 */
12579 lpfc_scsi_free(phba);
0794d601
JS
12580 lpfc_free_iocb_list(phba);
12581
da0436e9
JS
12582 lpfc_mem_free_all(phba);
12583
12584 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
12585 phba->hbqslimp.virt, phba->hbqslimp.phys);
12586
12587 /* Free resources associated with SLI2 interface */
12588 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
12589 phba->slim2p.virt, phba->slim2p.phys);
12590
12591 /* unmap adapter SLIM and Control Registers */
12592 iounmap(phba->ctrl_regs_memmap_p);
12593 iounmap(phba->slim_memmap_p);
12594
12595 lpfc_hba_free(phba);
12596
e0c0483c 12597 pci_release_mem_regions(pdev);
da0436e9
JS
12598 pci_disable_device(pdev);
12599}
12600
12601/**
12602 * lpfc_pci_suspend_one_s3 - PCI func to suspend SLI-3 device for power mgmnt
12603 * @pdev: pointer to PCI device
12604 * @msg: power management message
12605 *
12606 * This routine is to be called from the kernel's PCI subsystem to support
12607 * system Power Management (PM) to device with SLI-3 interface spec. When
12608 * PM invokes this method, it quiesces the device by stopping the driver's
12609 * worker thread for the device, turning off device's interrupt and DMA,
12610 * and bring the device offline. Note that as the driver implements the
12611 * minimum PM requirements to a power-aware driver's PM support for the
12612 * suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE, FREEZE)
12613 * to the suspend() method call will be treated as SUSPEND and the driver will
12614 * fully reinitialize its device during resume() method call, the driver will
12615 * set device to PCI_D3hot state in PCI config space instead of setting it
12616 * according to the @msg provided by the PM.
12617 *
12618 * Return code
12619 * 0 - driver suspended the device
12620 * Error otherwise
12621 **/
12622static int
12623lpfc_pci_suspend_one_s3(struct pci_dev *pdev, pm_message_t msg)
12624{
12625 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12626 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12627
12628 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12629 "0473 PCI device Power Management suspend.\n");
12630
12631 /* Bring down the device */
618a5230 12632 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
da0436e9
JS
12633 lpfc_offline(phba);
12634 kthread_stop(phba->worker_thread);
12635
12636 /* Disable interrupt from device */
12637 lpfc_sli_disable_intr(phba);
12638
12639 /* Save device state to PCI config space */
12640 pci_save_state(pdev);
12641 pci_set_power_state(pdev, PCI_D3hot);
12642
12643 return 0;
12644}
12645
12646/**
12647 * lpfc_pci_resume_one_s3 - PCI func to resume SLI-3 device for power mgmnt
12648 * @pdev: pointer to PCI device
12649 *
12650 * This routine is to be called from the kernel's PCI subsystem to support
12651 * system Power Management (PM) to device with SLI-3 interface spec. When PM
12652 * invokes this method, it restores the device's PCI config space state and
12653 * fully reinitializes the device and brings it online. Note that as the
12654 * driver implements the minimum PM requirements to a power-aware driver's
12655 * PM for suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE,
12656 * FREEZE) to the suspend() method call will be treated as SUSPEND and the
12657 * driver will fully reinitialize its device during resume() method call,
12658 * the device will be set to PCI_D0 directly in PCI config space before
12659 * restoring the state.
12660 *
12661 * Return code
12662 * 0 - driver suspended the device
12663 * Error otherwise
12664 **/
12665static int
12666lpfc_pci_resume_one_s3(struct pci_dev *pdev)
12667{
12668 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12669 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12670 uint32_t intr_mode;
12671 int error;
12672
12673 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12674 "0452 PCI device Power Management resume.\n");
12675
12676 /* Restore device state from PCI config space */
12677 pci_set_power_state(pdev, PCI_D0);
12678 pci_restore_state(pdev);
0d878419 12679
1dfb5a47
JS
12680 /*
12681 * As the new kernel behavior of pci_restore_state() API call clears
12682 * device saved_state flag, need to save the restored state again.
12683 */
12684 pci_save_state(pdev);
12685
da0436e9
JS
12686 if (pdev->is_busmaster)
12687 pci_set_master(pdev);
12688
12689 /* Startup the kernel thread for this host adapter. */
12690 phba->worker_thread = kthread_run(lpfc_do_work, phba,
12691 "lpfc_worker_%d", phba->brd_no);
12692 if (IS_ERR(phba->worker_thread)) {
12693 error = PTR_ERR(phba->worker_thread);
12694 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12695 "0434 PM resume failed to start worker "
12696 "thread: error=x%x.\n", error);
12697 return error;
12698 }
12699
12700 /* Configure and enable interrupt */
12701 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
12702 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 12703 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
12704 "0430 PM resume Failed to enable interrupt\n");
12705 return -EIO;
12706 } else
12707 phba->intr_mode = intr_mode;
12708
12709 /* Restart HBA and bring it online */
12710 lpfc_sli_brdrestart(phba);
12711 lpfc_online(phba);
12712
12713 /* Log the current active interrupt mode */
12714 lpfc_log_intr_mode(phba, phba->intr_mode);
12715
12716 return 0;
12717}
12718
891478a2
JS
12719/**
12720 * lpfc_sli_prep_dev_for_recover - Prepare SLI3 device for pci slot recover
12721 * @phba: pointer to lpfc hba data structure.
12722 *
12723 * This routine is called to prepare the SLI3 device for PCI slot recover. It
e2af0d2e 12724 * aborts all the outstanding SCSI I/Os to the pci device.
891478a2
JS
12725 **/
12726static void
12727lpfc_sli_prep_dev_for_recover(struct lpfc_hba *phba)
12728{
372c187b 12729 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
891478a2 12730 "2723 PCI channel I/O abort preparing for recovery\n");
e2af0d2e
JS
12731
12732 /*
12733 * There may be errored I/Os through HBA, abort all I/Os on txcmplq
12734 * and let the SCSI mid-layer to retry them to recover.
12735 */
db55fba8 12736 lpfc_sli_abort_fcp_rings(phba);
891478a2
JS
12737}
12738
0d878419
JS
12739/**
12740 * lpfc_sli_prep_dev_for_reset - Prepare SLI3 device for pci slot reset
12741 * @phba: pointer to lpfc hba data structure.
12742 *
12743 * This routine is called to prepare the SLI3 device for PCI slot reset. It
12744 * disables the device interrupt and pci device, and aborts the internal FCP
12745 * pending I/Os.
12746 **/
12747static void
12748lpfc_sli_prep_dev_for_reset(struct lpfc_hba *phba)
12749{
372c187b 12750 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
891478a2 12751 "2710 PCI channel disable preparing for reset\n");
e2af0d2e 12752
75baf696 12753 /* Block any management I/Os to the device */
618a5230 12754 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
75baf696 12755
e2af0d2e
JS
12756 /* Block all SCSI devices' I/Os on the host */
12757 lpfc_scsi_dev_block(phba);
12758
ea714f3d 12759 /* Flush all driver's outstanding SCSI I/Os as we are to reset */
c00f62e6 12760 lpfc_sli_flush_io_rings(phba);
ea714f3d 12761
e2af0d2e
JS
12762 /* stop all timers */
12763 lpfc_stop_hba_timers(phba);
12764
0d878419
JS
12765 /* Disable interrupt and pci device */
12766 lpfc_sli_disable_intr(phba);
12767 pci_disable_device(phba->pcidev);
0d878419
JS
12768}
12769
12770/**
12771 * lpfc_sli_prep_dev_for_perm_failure - Prepare SLI3 dev for pci slot disable
12772 * @phba: pointer to lpfc hba data structure.
12773 *
12774 * This routine is called to prepare the SLI3 device for PCI slot permanently
12775 * disabling. It blocks the SCSI transport layer traffic and flushes the FCP
12776 * pending I/Os.
12777 **/
12778static void
75baf696 12779lpfc_sli_prep_dev_for_perm_failure(struct lpfc_hba *phba)
0d878419 12780{
372c187b 12781 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
891478a2 12782 "2711 PCI channel permanent disable for failure\n");
e2af0d2e
JS
12783 /* Block all SCSI devices' I/Os on the host */
12784 lpfc_scsi_dev_block(phba);
12785
12786 /* stop all timers */
12787 lpfc_stop_hba_timers(phba);
12788
0d878419 12789 /* Clean up all driver's outstanding SCSI I/Os */
c00f62e6 12790 lpfc_sli_flush_io_rings(phba);
0d878419
JS
12791}
12792
da0436e9
JS
12793/**
12794 * lpfc_io_error_detected_s3 - Method for handling SLI-3 device PCI I/O error
12795 * @pdev: pointer to PCI device.
12796 * @state: the current PCI connection state.
12797 *
12798 * This routine is called from the PCI subsystem for I/O error handling to
12799 * device with SLI-3 interface spec. This function is called by the PCI
12800 * subsystem after a PCI bus error affecting this device has been detected.
12801 * When this function is invoked, it will need to stop all the I/Os and
12802 * interrupt(s) to the device. Once that is done, it will return
12803 * PCI_ERS_RESULT_NEED_RESET for the PCI subsystem to perform proper recovery
12804 * as desired.
12805 *
12806 * Return codes
0d878419 12807 * PCI_ERS_RESULT_CAN_RECOVER - can be recovered with reset_link
da0436e9
JS
12808 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
12809 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
12810 **/
12811static pci_ers_result_t
12812lpfc_io_error_detected_s3(struct pci_dev *pdev, pci_channel_state_t state)
12813{
12814 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12815 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
da0436e9 12816
0d878419
JS
12817 switch (state) {
12818 case pci_channel_io_normal:
891478a2
JS
12819 /* Non-fatal error, prepare for recovery */
12820 lpfc_sli_prep_dev_for_recover(phba);
0d878419
JS
12821 return PCI_ERS_RESULT_CAN_RECOVER;
12822 case pci_channel_io_frozen:
12823 /* Fatal error, prepare for slot reset */
12824 lpfc_sli_prep_dev_for_reset(phba);
12825 return PCI_ERS_RESULT_NEED_RESET;
12826 case pci_channel_io_perm_failure:
12827 /* Permanent failure, prepare for device down */
75baf696 12828 lpfc_sli_prep_dev_for_perm_failure(phba);
da0436e9 12829 return PCI_ERS_RESULT_DISCONNECT;
0d878419
JS
12830 default:
12831 /* Unknown state, prepare and request slot reset */
372c187b 12832 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0d878419
JS
12833 "0472 Unknown PCI error state: x%x\n", state);
12834 lpfc_sli_prep_dev_for_reset(phba);
12835 return PCI_ERS_RESULT_NEED_RESET;
da0436e9 12836 }
da0436e9
JS
12837}
12838
12839/**
12840 * lpfc_io_slot_reset_s3 - Method for restarting PCI SLI-3 device from scratch.
12841 * @pdev: pointer to PCI device.
12842 *
12843 * This routine is called from the PCI subsystem for error handling to
12844 * device with SLI-3 interface spec. This is called after PCI bus has been
12845 * reset to restart the PCI card from scratch, as if from a cold-boot.
12846 * During the PCI subsystem error recovery, after driver returns
12847 * PCI_ERS_RESULT_NEED_RESET, the PCI subsystem will perform proper error
12848 * recovery and then call this routine before calling the .resume method
12849 * to recover the device. This function will initialize the HBA device,
12850 * enable the interrupt, but it will just put the HBA to offline state
12851 * without passing any I/O traffic.
12852 *
12853 * Return codes
12854 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
12855 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
12856 */
12857static pci_ers_result_t
12858lpfc_io_slot_reset_s3(struct pci_dev *pdev)
12859{
12860 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12861 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12862 struct lpfc_sli *psli = &phba->sli;
12863 uint32_t intr_mode;
12864
12865 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
12866 if (pci_enable_device_mem(pdev)) {
12867 printk(KERN_ERR "lpfc: Cannot re-enable "
12868 "PCI device after reset.\n");
12869 return PCI_ERS_RESULT_DISCONNECT;
12870 }
12871
12872 pci_restore_state(pdev);
1dfb5a47
JS
12873
12874 /*
12875 * As the new kernel behavior of pci_restore_state() API call clears
12876 * device saved_state flag, need to save the restored state again.
12877 */
12878 pci_save_state(pdev);
12879
da0436e9
JS
12880 if (pdev->is_busmaster)
12881 pci_set_master(pdev);
12882
12883 spin_lock_irq(&phba->hbalock);
12884 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
12885 spin_unlock_irq(&phba->hbalock);
12886
12887 /* Configure and enable interrupt */
12888 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
12889 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 12890 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9
JS
12891 "0427 Cannot re-enable interrupt after "
12892 "slot reset.\n");
12893 return PCI_ERS_RESULT_DISCONNECT;
12894 } else
12895 phba->intr_mode = intr_mode;
12896
75baf696 12897 /* Take device offline, it will perform cleanup */
618a5230 12898 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
da0436e9
JS
12899 lpfc_offline(phba);
12900 lpfc_sli_brdrestart(phba);
12901
12902 /* Log the current active interrupt mode */
12903 lpfc_log_intr_mode(phba, phba->intr_mode);
12904
12905 return PCI_ERS_RESULT_RECOVERED;
12906}
12907
12908/**
12909 * lpfc_io_resume_s3 - Method for resuming PCI I/O operation on SLI-3 device.
12910 * @pdev: pointer to PCI device
12911 *
12912 * This routine is called from the PCI subsystem for error handling to device
12913 * with SLI-3 interface spec. It is called when kernel error recovery tells
12914 * the lpfc driver that it is ok to resume normal PCI operation after PCI bus
12915 * error recovery. After this call, traffic can start to flow from this device
12916 * again.
12917 */
12918static void
12919lpfc_io_resume_s3(struct pci_dev *pdev)
12920{
12921 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12922 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
3772a991 12923
e2af0d2e 12924 /* Bring device online, it will be no-op for non-fatal error resume */
da0436e9
JS
12925 lpfc_online(phba);
12926}
3772a991 12927
da0436e9
JS
12928/**
12929 * lpfc_sli4_get_els_iocb_cnt - Calculate the # of ELS IOCBs to reserve
12930 * @phba: pointer to lpfc hba data structure.
12931 *
12932 * returns the number of ELS/CT IOCBs to reserve
12933 **/
12934int
12935lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *phba)
12936{
12937 int max_xri = phba->sli4_hba.max_cfg_param.max_xri;
12938
f1126688
JS
12939 if (phba->sli_rev == LPFC_SLI_REV4) {
12940 if (max_xri <= 100)
6a9c52cf 12941 return 10;
f1126688 12942 else if (max_xri <= 256)
6a9c52cf 12943 return 25;
f1126688 12944 else if (max_xri <= 512)
6a9c52cf 12945 return 50;
f1126688 12946 else if (max_xri <= 1024)
6a9c52cf 12947 return 100;
8a9d2e80 12948 else if (max_xri <= 1536)
6a9c52cf 12949 return 150;
8a9d2e80
JS
12950 else if (max_xri <= 2048)
12951 return 200;
12952 else
12953 return 250;
f1126688
JS
12954 } else
12955 return 0;
3772a991
JS
12956}
12957
895427bd
JS
12958/**
12959 * lpfc_sli4_get_iocb_cnt - Calculate the # of total IOCBs to reserve
12960 * @phba: pointer to lpfc hba data structure.
12961 *
f358dd0c 12962 * returns the number of ELS/CT + NVMET IOCBs to reserve
895427bd
JS
12963 **/
12964int
12965lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba)
12966{
12967 int max_xri = lpfc_sli4_get_els_iocb_cnt(phba);
12968
f358dd0c
JS
12969 if (phba->nvmet_support)
12970 max_xri += LPFC_NVMET_BUF_POST;
895427bd
JS
12971 return max_xri;
12972}
12973
12974
0a5ce731 12975static int
1feb8204
JS
12976lpfc_log_write_firmware_error(struct lpfc_hba *phba, uint32_t offset,
12977 uint32_t magic_number, uint32_t ftype, uint32_t fid, uint32_t fsize,
12978 const struct firmware *fw)
12979{
0a5ce731
JS
12980 int rc;
12981
12982 /* Three cases: (1) FW was not supported on the detected adapter.
12983 * (2) FW update has been locked out administratively.
12984 * (3) Some other error during FW update.
12985 * In each case, an unmaskable message is written to the console
12986 * for admin diagnosis.
12987 */
12988 if (offset == ADD_STATUS_FW_NOT_SUPPORTED ||
a72d56b2 12989 (phba->pcidev->device == PCI_DEVICE_ID_LANCER_G6_FC &&
5792a0e8 12990 magic_number != MAGIC_NUMBER_G6) ||
a72d56b2 12991 (phba->pcidev->device == PCI_DEVICE_ID_LANCER_G7_FC &&
5792a0e8 12992 magic_number != MAGIC_NUMBER_G7)) {
372c187b 12993 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731
JS
12994 "3030 This firmware version is not supported on"
12995 " this HBA model. Device:%x Magic:%x Type:%x "
12996 "ID:%x Size %d %zd\n",
12997 phba->pcidev->device, magic_number, ftype, fid,
12998 fsize, fw->size);
12999 rc = -EINVAL;
13000 } else if (offset == ADD_STATUS_FW_DOWNLOAD_HW_DISABLED) {
372c187b 13001 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731
JS
13002 "3021 Firmware downloads have been prohibited "
13003 "by a system configuration setting on "
13004 "Device:%x Magic:%x Type:%x ID:%x Size %d "
13005 "%zd\n",
13006 phba->pcidev->device, magic_number, ftype, fid,
13007 fsize, fw->size);
13008 rc = -EACCES;
13009 } else {
372c187b 13010 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731
JS
13011 "3022 FW Download failed. Add Status x%x "
13012 "Device:%x Magic:%x Type:%x ID:%x Size %d "
13013 "%zd\n",
13014 offset, phba->pcidev->device, magic_number,
13015 ftype, fid, fsize, fw->size);
13016 rc = -EIO;
13017 }
13018 return rc;
1feb8204
JS
13019}
13020
52d52440
JS
13021/**
13022 * lpfc_write_firmware - attempt to write a firmware image to the port
52d52440 13023 * @fw: pointer to firmware image returned from request_firmware.
0a5ce731 13024 * @context: pointer to firmware image returned from request_firmware.
52d52440 13025 *
52d52440 13026 **/
ce396282
JS
13027static void
13028lpfc_write_firmware(const struct firmware *fw, void *context)
52d52440 13029{
ce396282 13030 struct lpfc_hba *phba = (struct lpfc_hba *)context;
6b5151fd 13031 char fwrev[FW_REV_STR_SIZE];
ce396282 13032 struct lpfc_grp_hdr *image;
52d52440
JS
13033 struct list_head dma_buffer_list;
13034 int i, rc = 0;
13035 struct lpfc_dmabuf *dmabuf, *next;
13036 uint32_t offset = 0, temp_offset = 0;
6b6ef5db 13037 uint32_t magic_number, ftype, fid, fsize;
52d52440 13038
c71ab861 13039 /* It can be null in no-wait mode, sanity check */
ce396282
JS
13040 if (!fw) {
13041 rc = -ENXIO;
13042 goto out;
13043 }
13044 image = (struct lpfc_grp_hdr *)fw->data;
13045
6b6ef5db
JS
13046 magic_number = be32_to_cpu(image->magic_number);
13047 ftype = bf_get_be32(lpfc_grp_hdr_file_type, image);
1feb8204 13048 fid = bf_get_be32(lpfc_grp_hdr_id, image);
6b6ef5db
JS
13049 fsize = be32_to_cpu(image->size);
13050
52d52440 13051 INIT_LIST_HEAD(&dma_buffer_list);
52d52440 13052 lpfc_decode_firmware_rev(phba, fwrev, 1);
88a2cfbb 13053 if (strncmp(fwrev, image->revision, strnlen(image->revision, 16))) {
372c187b 13054 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
ce396282 13055 "3023 Updating Firmware, Current Version:%s "
52d52440 13056 "New Version:%s\n",
88a2cfbb 13057 fwrev, image->revision);
52d52440
JS
13058 for (i = 0; i < LPFC_MBX_WR_CONFIG_MAX_BDE; i++) {
13059 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf),
13060 GFP_KERNEL);
13061 if (!dmabuf) {
13062 rc = -ENOMEM;
ce396282 13063 goto release_out;
52d52440
JS
13064 }
13065 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
13066 SLI4_PAGE_SIZE,
13067 &dmabuf->phys,
13068 GFP_KERNEL);
13069 if (!dmabuf->virt) {
13070 kfree(dmabuf);
13071 rc = -ENOMEM;
ce396282 13072 goto release_out;
52d52440
JS
13073 }
13074 list_add_tail(&dmabuf->list, &dma_buffer_list);
13075 }
13076 while (offset < fw->size) {
13077 temp_offset = offset;
13078 list_for_each_entry(dmabuf, &dma_buffer_list, list) {
079b5c91 13079 if (temp_offset + SLI4_PAGE_SIZE > fw->size) {
52d52440
JS
13080 memcpy(dmabuf->virt,
13081 fw->data + temp_offset,
079b5c91
JS
13082 fw->size - temp_offset);
13083 temp_offset = fw->size;
52d52440
JS
13084 break;
13085 }
52d52440
JS
13086 memcpy(dmabuf->virt, fw->data + temp_offset,
13087 SLI4_PAGE_SIZE);
88a2cfbb 13088 temp_offset += SLI4_PAGE_SIZE;
52d52440
JS
13089 }
13090 rc = lpfc_wr_object(phba, &dma_buffer_list,
13091 (fw->size - offset), &offset);
1feb8204 13092 if (rc) {
0a5ce731
JS
13093 rc = lpfc_log_write_firmware_error(phba, offset,
13094 magic_number,
13095 ftype,
13096 fid,
13097 fsize,
13098 fw);
ce396282 13099 goto release_out;
1feb8204 13100 }
52d52440
JS
13101 }
13102 rc = offset;
1feb8204 13103 } else
372c187b 13104 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
1feb8204
JS
13105 "3029 Skipped Firmware update, Current "
13106 "Version:%s New Version:%s\n",
13107 fwrev, image->revision);
ce396282
JS
13108
13109release_out:
52d52440
JS
13110 list_for_each_entry_safe(dmabuf, next, &dma_buffer_list, list) {
13111 list_del(&dmabuf->list);
13112 dma_free_coherent(&phba->pcidev->dev, SLI4_PAGE_SIZE,
13113 dmabuf->virt, dmabuf->phys);
13114 kfree(dmabuf);
13115 }
ce396282
JS
13116 release_firmware(fw);
13117out:
0a5ce731 13118 if (rc < 0)
372c187b 13119 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731
JS
13120 "3062 Firmware update error, status %d.\n", rc);
13121 else
372c187b 13122 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0a5ce731 13123 "3024 Firmware update success: size %d.\n", rc);
52d52440
JS
13124}
13125
c71ab861
JS
13126/**
13127 * lpfc_sli4_request_firmware_update - Request linux generic firmware upgrade
13128 * @phba: pointer to lpfc hba data structure.
fe614acd 13129 * @fw_upgrade: which firmware to update.
c71ab861
JS
13130 *
13131 * This routine is called to perform Linux generic firmware upgrade on device
13132 * that supports such feature.
13133 **/
13134int
13135lpfc_sli4_request_firmware_update(struct lpfc_hba *phba, uint8_t fw_upgrade)
13136{
13137 uint8_t file_name[ELX_MODEL_NAME_SIZE];
13138 int ret;
13139 const struct firmware *fw;
13140
13141 /* Only supported on SLI4 interface type 2 for now */
27d6ac0a 13142 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) <
c71ab861
JS
13143 LPFC_SLI_INTF_IF_TYPE_2)
13144 return -EPERM;
13145
13146 snprintf(file_name, ELX_MODEL_NAME_SIZE, "%s.grp", phba->ModelName);
13147
13148 if (fw_upgrade == INT_FW_UPGRADE) {
13149 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
13150 file_name, &phba->pcidev->dev,
13151 GFP_KERNEL, (void *)phba,
13152 lpfc_write_firmware);
13153 } else if (fw_upgrade == RUN_FW_UPGRADE) {
13154 ret = request_firmware(&fw, file_name, &phba->pcidev->dev);
13155 if (!ret)
13156 lpfc_write_firmware(fw, (void *)phba);
13157 } else {
13158 ret = -EINVAL;
13159 }
13160
13161 return ret;
13162}
13163
3772a991 13164/**
da0436e9 13165 * lpfc_pci_probe_one_s4 - PCI probe func to reg SLI-4 device to PCI subsys
3772a991
JS
13166 * @pdev: pointer to PCI device
13167 * @pid: pointer to PCI device identifier
13168 *
da0436e9
JS
13169 * This routine is called from the kernel's PCI subsystem to device with
13170 * SLI-4 interface spec. When an Emulex HBA with SLI-4 interface spec is
3772a991 13171 * presented on PCI bus, the kernel PCI subsystem looks at PCI device-specific
da0436e9
JS
13172 * information of the device and driver to see if the driver state that it
13173 * can support this kind of device. If the match is successful, the driver
13174 * core invokes this routine. If this routine determines it can claim the HBA,
13175 * it does all the initialization that it needs to do to handle the HBA
13176 * properly.
3772a991
JS
13177 *
13178 * Return code
13179 * 0 - driver can claim the device
13180 * negative value - driver can not claim the device
13181 **/
6f039790 13182static int
da0436e9 13183lpfc_pci_probe_one_s4(struct pci_dev *pdev, const struct pci_device_id *pid)
3772a991
JS
13184{
13185 struct lpfc_hba *phba;
13186 struct lpfc_vport *vport = NULL;
6669f9bb 13187 struct Scsi_Host *shost = NULL;
6c621a22 13188 int error;
3772a991
JS
13189 uint32_t cfg_mode, intr_mode;
13190
13191 /* Allocate memory for HBA structure */
13192 phba = lpfc_hba_alloc(pdev);
13193 if (!phba)
13194 return -ENOMEM;
13195
13196 /* Perform generic PCI device enabling operation */
13197 error = lpfc_enable_pci_dev(phba);
079b5c91 13198 if (error)
3772a991 13199 goto out_free_phba;
3772a991 13200
da0436e9
JS
13201 /* Set up SLI API function jump table for PCI-device group-1 HBAs */
13202 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_OC);
3772a991
JS
13203 if (error)
13204 goto out_disable_pci_dev;
13205
da0436e9
JS
13206 /* Set up SLI-4 specific device PCI memory space */
13207 error = lpfc_sli4_pci_mem_setup(phba);
3772a991
JS
13208 if (error) {
13209 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 13210 "1410 Failed to set up pci memory space.\n");
3772a991
JS
13211 goto out_disable_pci_dev;
13212 }
13213
da0436e9
JS
13214 /* Set up SLI-4 Specific device driver resources */
13215 error = lpfc_sli4_driver_resource_setup(phba);
3772a991
JS
13216 if (error) {
13217 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9
JS
13218 "1412 Failed to set up driver resource.\n");
13219 goto out_unset_pci_mem_s4;
3772a991
JS
13220 }
13221
19ca7609 13222 INIT_LIST_HEAD(&phba->active_rrq_list);
7d791df7 13223 INIT_LIST_HEAD(&phba->fcf.fcf_pri_list);
19ca7609 13224
3772a991
JS
13225 /* Set up common device driver resources */
13226 error = lpfc_setup_driver_resource_phase2(phba);
13227 if (error) {
13228 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 13229 "1414 Failed to set up driver resource.\n");
6c621a22 13230 goto out_unset_driver_resource_s4;
3772a991
JS
13231 }
13232
079b5c91
JS
13233 /* Get the default values for Model Name and Description */
13234 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
13235
3772a991 13236 /* Now, trying to enable interrupt and bring up the device */
5b75da2f 13237 cfg_mode = phba->cfg_use_msi;
5b75da2f 13238
7b15db32 13239 /* Put device to a known state before enabling interrupt */
cdb42bec 13240 phba->pport = NULL;
7b15db32 13241 lpfc_stop_port(phba);
895427bd 13242
dcaa2136
JS
13243 /* Init cpu_map array */
13244 lpfc_cpu_map_array_init(phba);
13245
13246 /* Init hba_eq_hdl array */
13247 lpfc_hba_eq_hdl_array_init(phba);
13248
7b15db32
JS
13249 /* Configure and enable interrupt */
13250 intr_mode = lpfc_sli4_enable_intr(phba, cfg_mode);
13251 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 13252 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
7b15db32
JS
13253 "0426 Failed to enable interrupt.\n");
13254 error = -ENODEV;
cdb42bec 13255 goto out_unset_driver_resource;
7b15db32
JS
13256 }
13257 /* Default to single EQ for non-MSI-X */
895427bd 13258 if (phba->intr_type != MSIX) {
6a828b0f 13259 phba->cfg_irq_chann = 1;
2d7dbc4c 13260 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
2d7dbc4c
JS
13261 if (phba->nvmet_support)
13262 phba->cfg_nvmet_mrq = 1;
13263 }
cdb42bec 13264 }
6a828b0f 13265 lpfc_cpu_affinity_check(phba, phba->cfg_irq_chann);
cdb42bec
JS
13266
13267 /* Create SCSI host to the physical port */
13268 error = lpfc_create_shost(phba);
13269 if (error) {
13270 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13271 "1415 Failed to create scsi host.\n");
13272 goto out_disable_intr;
13273 }
13274 vport = phba->pport;
13275 shost = lpfc_shost_from_vport(vport); /* save shost for error cleanup */
13276
13277 /* Configure sysfs attributes */
13278 error = lpfc_alloc_sysfs_attr(vport);
13279 if (error) {
13280 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13281 "1416 Failed to allocate sysfs attr\n");
13282 goto out_destroy_shost;
895427bd
JS
13283 }
13284
7b15db32
JS
13285 /* Set up SLI-4 HBA */
13286 if (lpfc_sli4_hba_setup(phba)) {
372c187b 13287 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
7b15db32
JS
13288 "1421 Failed to set up hba\n");
13289 error = -ENODEV;
cdb42bec 13290 goto out_free_sysfs_attr;
98c9ea5c 13291 }
858c9f6c 13292
7b15db32
JS
13293 /* Log the current active interrupt mode */
13294 phba->intr_mode = intr_mode;
13295 lpfc_log_intr_mode(phba, intr_mode);
13296
3772a991
JS
13297 /* Perform post initialization setup */
13298 lpfc_post_init_setup(phba);
dea3101e 13299
01649561
JS
13300 /* NVME support in FW earlier in the driver load corrects the
13301 * FC4 type making a check for nvme_support unnecessary.
13302 */
0794d601
JS
13303 if (phba->nvmet_support == 0) {
13304 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
13305 /* Create NVME binding with nvme_fc_transport. This
13306 * ensures the vport is initialized. If the localport
13307 * create fails, it should not unload the driver to
13308 * support field issues.
13309 */
13310 error = lpfc_nvme_create_localport(vport);
13311 if (error) {
372c187b 13312 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
0794d601
JS
13313 "6004 NVME registration "
13314 "failed, error x%x\n",
13315 error);
13316 }
01649561
JS
13317 }
13318 }
895427bd 13319
c71ab861
JS
13320 /* check for firmware upgrade or downgrade */
13321 if (phba->cfg_request_firmware_upgrade)
db6f1c2f 13322 lpfc_sli4_request_firmware_update(phba, INT_FW_UPGRADE);
52d52440 13323
1c6834a7
JS
13324 /* Check if there are static vports to be created. */
13325 lpfc_create_static_vport(phba);
d2cc9bcd
JS
13326
13327 /* Enable RAS FW log support */
13328 lpfc_sli4_ras_setup(phba);
13329
93a4d6f4 13330 INIT_LIST_HEAD(&phba->poll_list);
f861f596 13331 timer_setup(&phba->cpuhp_poll_timer, lpfc_sli4_poll_hbtimer, 0);
93a4d6f4
JS
13332 cpuhp_state_add_instance_nocalls(lpfc_cpuhp_state, &phba->cpuhp);
13333
dea3101e 13334 return 0;
13335
5b75da2f
JS
13336out_free_sysfs_attr:
13337 lpfc_free_sysfs_attr(vport);
3772a991
JS
13338out_destroy_shost:
13339 lpfc_destroy_shost(phba);
cdb42bec
JS
13340out_disable_intr:
13341 lpfc_sli4_disable_intr(phba);
3772a991
JS
13342out_unset_driver_resource:
13343 lpfc_unset_driver_resource_phase2(phba);
da0436e9
JS
13344out_unset_driver_resource_s4:
13345 lpfc_sli4_driver_resource_unset(phba);
13346out_unset_pci_mem_s4:
13347 lpfc_sli4_pci_mem_unset(phba);
3772a991
JS
13348out_disable_pci_dev:
13349 lpfc_disable_pci_dev(phba);
6669f9bb
JS
13350 if (shost)
13351 scsi_host_put(shost);
2e0fef85 13352out_free_phba:
3772a991 13353 lpfc_hba_free(phba);
dea3101e 13354 return error;
13355}
13356
e59058c4 13357/**
da0436e9 13358 * lpfc_pci_remove_one_s4 - PCI func to unreg SLI-4 device from PCI subsystem
e59058c4
JS
13359 * @pdev: pointer to PCI device
13360 *
da0436e9
JS
13361 * This routine is called from the kernel's PCI subsystem to device with
13362 * SLI-4 interface spec. When an Emulex HBA with SLI-4 interface spec is
3772a991
JS
13363 * removed from PCI bus, it performs all the necessary cleanup for the HBA
13364 * device to be removed from the PCI subsystem properly.
e59058c4 13365 **/
6f039790 13366static void
da0436e9 13367lpfc_pci_remove_one_s4(struct pci_dev *pdev)
dea3101e 13368{
da0436e9 13369 struct Scsi_Host *shost = pci_get_drvdata(pdev);
2e0fef85 13370 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
eada272d 13371 struct lpfc_vport **vports;
da0436e9 13372 struct lpfc_hba *phba = vport->phba;
eada272d 13373 int i;
8a4df120 13374
da0436e9 13375 /* Mark the device unloading flag */
549e55cd 13376 spin_lock_irq(&phba->hbalock);
51ef4c26 13377 vport->load_flag |= FC_UNLOADING;
549e55cd 13378 spin_unlock_irq(&phba->hbalock);
2e0fef85 13379
da0436e9 13380 /* Free the HBA sysfs attributes */
858c9f6c
JS
13381 lpfc_free_sysfs_attr(vport);
13382
eada272d
JS
13383 /* Release all the vports against this physical port */
13384 vports = lpfc_create_vport_work_array(phba);
13385 if (vports != NULL)
587a37f6
JS
13386 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
13387 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
13388 continue;
eada272d 13389 fc_vport_terminate(vports[i]->fc_vport);
587a37f6 13390 }
eada272d
JS
13391 lpfc_destroy_vport_work_array(phba, vports);
13392
13393 /* Remove FC host and then SCSI host with the physical port */
858c9f6c
JS
13394 fc_remove_host(shost);
13395 scsi_remove_host(shost);
da0436e9 13396
d613b6a7
JS
13397 /* Perform ndlp cleanup on the physical port. The nvme and nvmet
13398 * localports are destroyed after to cleanup all transport memory.
895427bd 13399 */
87af33fe 13400 lpfc_cleanup(vport);
d613b6a7
JS
13401 lpfc_nvmet_destroy_targetport(phba);
13402 lpfc_nvme_destroy_localport(vport);
87af33fe 13403
c490850a
JS
13404 /* De-allocate multi-XRI pools */
13405 if (phba->cfg_xri_rebalancing)
13406 lpfc_destroy_multixri_pools(phba);
13407
281d6190
JS
13408 /*
13409 * Bring down the SLI Layer. This step disables all interrupts,
13410 * clears the rings, discards all mailbox commands, and resets
13411 * the HBA FCoE function.
13412 */
13413 lpfc_debugfs_terminate(vport);
a257bf90 13414
1901762f 13415 lpfc_stop_hba_timers(phba);
523128e5 13416 spin_lock_irq(&phba->port_list_lock);
858c9f6c 13417 list_del_init(&vport->listentry);
523128e5 13418 spin_unlock_irq(&phba->port_list_lock);
858c9f6c 13419
3677a3a7 13420 /* Perform scsi free before driver resource_unset since scsi
da0436e9 13421 * buffers are released to their corresponding pools here.
2e0fef85 13422 */
5e5b511d 13423 lpfc_io_free(phba);
01649561 13424 lpfc_free_iocb_list(phba);
5e5b511d 13425 lpfc_sli4_hba_unset(phba);
67d12733 13426
0cdb84ec 13427 lpfc_unset_driver_resource_phase2(phba);
da0436e9 13428 lpfc_sli4_driver_resource_unset(phba);
ed957684 13429
da0436e9
JS
13430 /* Unmap adapter Control and Doorbell registers */
13431 lpfc_sli4_pci_mem_unset(phba);
2e0fef85 13432
da0436e9
JS
13433 /* Release PCI resources and disable device's PCI function */
13434 scsi_host_put(shost);
13435 lpfc_disable_pci_dev(phba);
2e0fef85 13436
da0436e9 13437 /* Finally, free the driver's device data structure */
3772a991 13438 lpfc_hba_free(phba);
2e0fef85 13439
da0436e9 13440 return;
dea3101e 13441}
13442
3a55b532 13443/**
da0436e9 13444 * lpfc_pci_suspend_one_s4 - PCI func to suspend SLI-4 device for power mgmnt
3a55b532
JS
13445 * @pdev: pointer to PCI device
13446 * @msg: power management message
13447 *
da0436e9
JS
13448 * This routine is called from the kernel's PCI subsystem to support system
13449 * Power Management (PM) to device with SLI-4 interface spec. When PM invokes
13450 * this method, it quiesces the device by stopping the driver's worker
13451 * thread for the device, turning off device's interrupt and DMA, and bring
13452 * the device offline. Note that as the driver implements the minimum PM
13453 * requirements to a power-aware driver's PM support for suspend/resume -- all
13454 * the possible PM messages (SUSPEND, HIBERNATE, FREEZE) to the suspend()
13455 * method call will be treated as SUSPEND and the driver will fully
13456 * reinitialize its device during resume() method call, the driver will set
13457 * device to PCI_D3hot state in PCI config space instead of setting it
3772a991 13458 * according to the @msg provided by the PM.
3a55b532
JS
13459 *
13460 * Return code
3772a991
JS
13461 * 0 - driver suspended the device
13462 * Error otherwise
3a55b532
JS
13463 **/
13464static int
da0436e9 13465lpfc_pci_suspend_one_s4(struct pci_dev *pdev, pm_message_t msg)
3a55b532
JS
13466{
13467 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13468 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13469
13470 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
75baf696 13471 "2843 PCI device Power Management suspend.\n");
3a55b532
JS
13472
13473 /* Bring down the device */
618a5230 13474 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
3a55b532
JS
13475 lpfc_offline(phba);
13476 kthread_stop(phba->worker_thread);
13477
13478 /* Disable interrupt from device */
da0436e9 13479 lpfc_sli4_disable_intr(phba);
5350d872 13480 lpfc_sli4_queue_destroy(phba);
3a55b532
JS
13481
13482 /* Save device state to PCI config space */
13483 pci_save_state(pdev);
13484 pci_set_power_state(pdev, PCI_D3hot);
13485
13486 return 0;
13487}
13488
13489/**
da0436e9 13490 * lpfc_pci_resume_one_s4 - PCI func to resume SLI-4 device for power mgmnt
3a55b532
JS
13491 * @pdev: pointer to PCI device
13492 *
da0436e9
JS
13493 * This routine is called from the kernel's PCI subsystem to support system
13494 * Power Management (PM) to device with SLI-4 interface spac. When PM invokes
13495 * this method, it restores the device's PCI config space state and fully
13496 * reinitializes the device and brings it online. Note that as the driver
13497 * implements the minimum PM requirements to a power-aware driver's PM for
13498 * suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE, FREEZE)
13499 * to the suspend() method call will be treated as SUSPEND and the driver
13500 * will fully reinitialize its device during resume() method call, the device
13501 * will be set to PCI_D0 directly in PCI config space before restoring the
13502 * state.
3a55b532
JS
13503 *
13504 * Return code
3772a991
JS
13505 * 0 - driver suspended the device
13506 * Error otherwise
3a55b532
JS
13507 **/
13508static int
da0436e9 13509lpfc_pci_resume_one_s4(struct pci_dev *pdev)
3a55b532
JS
13510{
13511 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13512 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
5b75da2f 13513 uint32_t intr_mode;
3a55b532
JS
13514 int error;
13515
13516 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
da0436e9 13517 "0292 PCI device Power Management resume.\n");
3a55b532
JS
13518
13519 /* Restore device state from PCI config space */
13520 pci_set_power_state(pdev, PCI_D0);
13521 pci_restore_state(pdev);
1dfb5a47
JS
13522
13523 /*
13524 * As the new kernel behavior of pci_restore_state() API call clears
13525 * device saved_state flag, need to save the restored state again.
13526 */
13527 pci_save_state(pdev);
13528
3a55b532
JS
13529 if (pdev->is_busmaster)
13530 pci_set_master(pdev);
13531
da0436e9 13532 /* Startup the kernel thread for this host adapter. */
3a55b532
JS
13533 phba->worker_thread = kthread_run(lpfc_do_work, phba,
13534 "lpfc_worker_%d", phba->brd_no);
13535 if (IS_ERR(phba->worker_thread)) {
13536 error = PTR_ERR(phba->worker_thread);
13537 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 13538 "0293 PM resume failed to start worker "
3a55b532
JS
13539 "thread: error=x%x.\n", error);
13540 return error;
13541 }
13542
5b75da2f 13543 /* Configure and enable interrupt */
da0436e9 13544 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
5b75da2f 13545 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 13546 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
da0436e9 13547 "0294 PM resume Failed to enable interrupt\n");
5b75da2f
JS
13548 return -EIO;
13549 } else
13550 phba->intr_mode = intr_mode;
3a55b532
JS
13551
13552 /* Restart HBA and bring it online */
13553 lpfc_sli_brdrestart(phba);
13554 lpfc_online(phba);
13555
5b75da2f
JS
13556 /* Log the current active interrupt mode */
13557 lpfc_log_intr_mode(phba, phba->intr_mode);
13558
3a55b532
JS
13559 return 0;
13560}
13561
75baf696
JS
13562/**
13563 * lpfc_sli4_prep_dev_for_recover - Prepare SLI4 device for pci slot recover
13564 * @phba: pointer to lpfc hba data structure.
13565 *
13566 * This routine is called to prepare the SLI4 device for PCI slot recover. It
13567 * aborts all the outstanding SCSI I/Os to the pci device.
13568 **/
13569static void
13570lpfc_sli4_prep_dev_for_recover(struct lpfc_hba *phba)
13571{
372c187b 13572 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
13573 "2828 PCI channel I/O abort preparing for recovery\n");
13574 /*
13575 * There may be errored I/Os through HBA, abort all I/Os on txcmplq
13576 * and let the SCSI mid-layer to retry them to recover.
13577 */
db55fba8 13578 lpfc_sli_abort_fcp_rings(phba);
75baf696
JS
13579}
13580
13581/**
13582 * lpfc_sli4_prep_dev_for_reset - Prepare SLI4 device for pci slot reset
13583 * @phba: pointer to lpfc hba data structure.
13584 *
13585 * This routine is called to prepare the SLI4 device for PCI slot reset. It
13586 * disables the device interrupt and pci device, and aborts the internal FCP
13587 * pending I/Os.
13588 **/
13589static void
13590lpfc_sli4_prep_dev_for_reset(struct lpfc_hba *phba)
13591{
372c187b 13592 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
13593 "2826 PCI channel disable preparing for reset\n");
13594
13595 /* Block any management I/Os to the device */
618a5230 13596 lpfc_block_mgmt_io(phba, LPFC_MBX_NO_WAIT);
75baf696
JS
13597
13598 /* Block all SCSI devices' I/Os on the host */
13599 lpfc_scsi_dev_block(phba);
13600
c00f62e6
JS
13601 /* Flush all driver's outstanding I/Os as we are to reset */
13602 lpfc_sli_flush_io_rings(phba);
c3725bdc 13603
75baf696
JS
13604 /* stop all timers */
13605 lpfc_stop_hba_timers(phba);
13606
13607 /* Disable interrupt and pci device */
13608 lpfc_sli4_disable_intr(phba);
5350d872 13609 lpfc_sli4_queue_destroy(phba);
75baf696 13610 pci_disable_device(phba->pcidev);
75baf696
JS
13611}
13612
13613/**
13614 * lpfc_sli4_prep_dev_for_perm_failure - Prepare SLI4 dev for pci slot disable
13615 * @phba: pointer to lpfc hba data structure.
13616 *
13617 * This routine is called to prepare the SLI4 device for PCI slot permanently
13618 * disabling. It blocks the SCSI transport layer traffic and flushes the FCP
13619 * pending I/Os.
13620 **/
13621static void
13622lpfc_sli4_prep_dev_for_perm_failure(struct lpfc_hba *phba)
13623{
372c187b 13624 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
13625 "2827 PCI channel permanent disable for failure\n");
13626
13627 /* Block all SCSI devices' I/Os on the host */
13628 lpfc_scsi_dev_block(phba);
13629
13630 /* stop all timers */
13631 lpfc_stop_hba_timers(phba);
13632
c00f62e6
JS
13633 /* Clean up all driver's outstanding I/Os */
13634 lpfc_sli_flush_io_rings(phba);
75baf696
JS
13635}
13636
8d63f375 13637/**
da0436e9 13638 * lpfc_io_error_detected_s4 - Method for handling PCI I/O error to SLI-4 device
e59058c4
JS
13639 * @pdev: pointer to PCI device.
13640 * @state: the current PCI connection state.
8d63f375 13641 *
da0436e9
JS
13642 * This routine is called from the PCI subsystem for error handling to device
13643 * with SLI-4 interface spec. This function is called by the PCI subsystem
13644 * after a PCI bus error affecting this device has been detected. When this
13645 * function is invoked, it will need to stop all the I/Os and interrupt(s)
13646 * to the device. Once that is done, it will return PCI_ERS_RESULT_NEED_RESET
13647 * for the PCI subsystem to perform proper recovery as desired.
e59058c4
JS
13648 *
13649 * Return codes
3772a991
JS
13650 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
13651 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
e59058c4 13652 **/
3772a991 13653static pci_ers_result_t
da0436e9 13654lpfc_io_error_detected_s4(struct pci_dev *pdev, pci_channel_state_t state)
8d63f375 13655{
75baf696
JS
13656 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13657 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13658
13659 switch (state) {
13660 case pci_channel_io_normal:
13661 /* Non-fatal error, prepare for recovery */
13662 lpfc_sli4_prep_dev_for_recover(phba);
13663 return PCI_ERS_RESULT_CAN_RECOVER;
13664 case pci_channel_io_frozen:
13665 /* Fatal error, prepare for slot reset */
13666 lpfc_sli4_prep_dev_for_reset(phba);
13667 return PCI_ERS_RESULT_NEED_RESET;
13668 case pci_channel_io_perm_failure:
13669 /* Permanent failure, prepare for device down */
13670 lpfc_sli4_prep_dev_for_perm_failure(phba);
13671 return PCI_ERS_RESULT_DISCONNECT;
13672 default:
13673 /* Unknown state, prepare and request slot reset */
372c187b 13674 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
13675 "2825 Unknown PCI error state: x%x\n", state);
13676 lpfc_sli4_prep_dev_for_reset(phba);
13677 return PCI_ERS_RESULT_NEED_RESET;
13678 }
8d63f375
LV
13679}
13680
13681/**
da0436e9 13682 * lpfc_io_slot_reset_s4 - Method for restart PCI SLI-4 device from scratch
e59058c4
JS
13683 * @pdev: pointer to PCI device.
13684 *
da0436e9
JS
13685 * This routine is called from the PCI subsystem for error handling to device
13686 * with SLI-4 interface spec. It is called after PCI bus has been reset to
13687 * restart the PCI card from scratch, as if from a cold-boot. During the
13688 * PCI subsystem error recovery, after the driver returns
3772a991 13689 * PCI_ERS_RESULT_NEED_RESET, the PCI subsystem will perform proper error
da0436e9
JS
13690 * recovery and then call this routine before calling the .resume method to
13691 * recover the device. This function will initialize the HBA device, enable
13692 * the interrupt, but it will just put the HBA to offline state without
13693 * passing any I/O traffic.
8d63f375 13694 *
e59058c4 13695 * Return codes
3772a991
JS
13696 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
13697 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
8d63f375 13698 */
3772a991 13699static pci_ers_result_t
da0436e9 13700lpfc_io_slot_reset_s4(struct pci_dev *pdev)
8d63f375 13701{
75baf696
JS
13702 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13703 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13704 struct lpfc_sli *psli = &phba->sli;
13705 uint32_t intr_mode;
13706
13707 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
13708 if (pci_enable_device_mem(pdev)) {
13709 printk(KERN_ERR "lpfc: Cannot re-enable "
13710 "PCI device after reset.\n");
13711 return PCI_ERS_RESULT_DISCONNECT;
13712 }
13713
13714 pci_restore_state(pdev);
0a96e975
JS
13715
13716 /*
13717 * As the new kernel behavior of pci_restore_state() API call clears
13718 * device saved_state flag, need to save the restored state again.
13719 */
13720 pci_save_state(pdev);
13721
75baf696
JS
13722 if (pdev->is_busmaster)
13723 pci_set_master(pdev);
13724
13725 spin_lock_irq(&phba->hbalock);
13726 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
13727 spin_unlock_irq(&phba->hbalock);
13728
13729 /* Configure and enable interrupt */
13730 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
13731 if (intr_mode == LPFC_INTR_ERROR) {
372c187b 13732 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
75baf696
JS
13733 "2824 Cannot re-enable interrupt after "
13734 "slot reset.\n");
13735 return PCI_ERS_RESULT_DISCONNECT;
13736 } else
13737 phba->intr_mode = intr_mode;
13738
13739 /* Log the current active interrupt mode */
13740 lpfc_log_intr_mode(phba, phba->intr_mode);
13741
8d63f375
LV
13742 return PCI_ERS_RESULT_RECOVERED;
13743}
13744
13745/**
da0436e9 13746 * lpfc_io_resume_s4 - Method for resuming PCI I/O operation to SLI-4 device
e59058c4 13747 * @pdev: pointer to PCI device
8d63f375 13748 *
3772a991 13749 * This routine is called from the PCI subsystem for error handling to device
da0436e9 13750 * with SLI-4 interface spec. It is called when kernel error recovery tells
3772a991
JS
13751 * the lpfc driver that it is ok to resume normal PCI operation after PCI bus
13752 * error recovery. After this call, traffic can start to flow from this device
13753 * again.
da0436e9 13754 **/
3772a991 13755static void
da0436e9 13756lpfc_io_resume_s4(struct pci_dev *pdev)
8d63f375 13757{
75baf696
JS
13758 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13759 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13760
13761 /*
13762 * In case of slot reset, as function reset is performed through
13763 * mailbox command which needs DMA to be enabled, this operation
13764 * has to be moved to the io resume phase. Taking device offline
13765 * will perform the necessary cleanup.
13766 */
13767 if (!(phba->sli.sli_flag & LPFC_SLI_ACTIVE)) {
13768 /* Perform device reset */
618a5230 13769 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
75baf696
JS
13770 lpfc_offline(phba);
13771 lpfc_sli_brdrestart(phba);
13772 /* Bring the device back online */
13773 lpfc_online(phba);
13774 }
8d63f375
LV
13775}
13776
3772a991
JS
13777/**
13778 * lpfc_pci_probe_one - lpfc PCI probe func to reg dev to PCI subsystem
13779 * @pdev: pointer to PCI device
13780 * @pid: pointer to PCI device identifier
13781 *
13782 * This routine is to be registered to the kernel's PCI subsystem. When an
13783 * Emulex HBA device is presented on PCI bus, the kernel PCI subsystem looks
13784 * at PCI device-specific information of the device and driver to see if the
13785 * driver state that it can support this kind of device. If the match is
13786 * successful, the driver core invokes this routine. This routine dispatches
13787 * the action to the proper SLI-3 or SLI-4 device probing routine, which will
13788 * do all the initialization that it needs to do to handle the HBA device
13789 * properly.
13790 *
13791 * Return code
13792 * 0 - driver can claim the device
13793 * negative value - driver can not claim the device
13794 **/
6f039790 13795static int
3772a991
JS
13796lpfc_pci_probe_one(struct pci_dev *pdev, const struct pci_device_id *pid)
13797{
13798 int rc;
8fa38513 13799 struct lpfc_sli_intf intf;
3772a991 13800
28baac74 13801 if (pci_read_config_dword(pdev, LPFC_SLI_INTF, &intf.word0))
3772a991
JS
13802 return -ENODEV;
13803
8fa38513 13804 if ((bf_get(lpfc_sli_intf_valid, &intf) == LPFC_SLI_INTF_VALID) &&
28baac74 13805 (bf_get(lpfc_sli_intf_slirev, &intf) == LPFC_SLI_INTF_REV_SLI4))
da0436e9 13806 rc = lpfc_pci_probe_one_s4(pdev, pid);
8fa38513 13807 else
3772a991 13808 rc = lpfc_pci_probe_one_s3(pdev, pid);
8fa38513 13809
3772a991
JS
13810 return rc;
13811}
13812
13813/**
13814 * lpfc_pci_remove_one - lpfc PCI func to unreg dev from PCI subsystem
13815 * @pdev: pointer to PCI device
13816 *
13817 * This routine is to be registered to the kernel's PCI subsystem. When an
13818 * Emulex HBA is removed from PCI bus, the driver core invokes this routine.
13819 * This routine dispatches the action to the proper SLI-3 or SLI-4 device
13820 * remove routine, which will perform all the necessary cleanup for the
13821 * device to be removed from the PCI subsystem properly.
13822 **/
6f039790 13823static void
3772a991
JS
13824lpfc_pci_remove_one(struct pci_dev *pdev)
13825{
13826 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13827 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13828
13829 switch (phba->pci_dev_grp) {
13830 case LPFC_PCI_DEV_LP:
13831 lpfc_pci_remove_one_s3(pdev);
13832 break;
da0436e9
JS
13833 case LPFC_PCI_DEV_OC:
13834 lpfc_pci_remove_one_s4(pdev);
13835 break;
3772a991 13836 default:
372c187b 13837 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
13838 "1424 Invalid PCI device group: 0x%x\n",
13839 phba->pci_dev_grp);
13840 break;
13841 }
13842 return;
13843}
13844
13845/**
13846 * lpfc_pci_suspend_one - lpfc PCI func to suspend dev for power management
13847 * @pdev: pointer to PCI device
13848 * @msg: power management message
13849 *
13850 * This routine is to be registered to the kernel's PCI subsystem to support
13851 * system Power Management (PM). When PM invokes this method, it dispatches
13852 * the action to the proper SLI-3 or SLI-4 device suspend routine, which will
13853 * suspend the device.
13854 *
13855 * Return code
13856 * 0 - driver suspended the device
13857 * Error otherwise
13858 **/
13859static int
13860lpfc_pci_suspend_one(struct pci_dev *pdev, pm_message_t msg)
13861{
13862 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13863 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13864 int rc = -ENODEV;
13865
13866 switch (phba->pci_dev_grp) {
13867 case LPFC_PCI_DEV_LP:
13868 rc = lpfc_pci_suspend_one_s3(pdev, msg);
13869 break;
da0436e9
JS
13870 case LPFC_PCI_DEV_OC:
13871 rc = lpfc_pci_suspend_one_s4(pdev, msg);
13872 break;
3772a991 13873 default:
372c187b 13874 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
13875 "1425 Invalid PCI device group: 0x%x\n",
13876 phba->pci_dev_grp);
13877 break;
13878 }
13879 return rc;
13880}
13881
13882/**
13883 * lpfc_pci_resume_one - lpfc PCI func to resume dev for power management
13884 * @pdev: pointer to PCI device
13885 *
13886 * This routine is to be registered to the kernel's PCI subsystem to support
13887 * system Power Management (PM). When PM invokes this method, it dispatches
13888 * the action to the proper SLI-3 or SLI-4 device resume routine, which will
13889 * resume the device.
13890 *
13891 * Return code
13892 * 0 - driver suspended the device
13893 * Error otherwise
13894 **/
13895static int
13896lpfc_pci_resume_one(struct pci_dev *pdev)
13897{
13898 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13899 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13900 int rc = -ENODEV;
13901
13902 switch (phba->pci_dev_grp) {
13903 case LPFC_PCI_DEV_LP:
13904 rc = lpfc_pci_resume_one_s3(pdev);
13905 break;
da0436e9
JS
13906 case LPFC_PCI_DEV_OC:
13907 rc = lpfc_pci_resume_one_s4(pdev);
13908 break;
3772a991 13909 default:
372c187b 13910 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
13911 "1426 Invalid PCI device group: 0x%x\n",
13912 phba->pci_dev_grp);
13913 break;
13914 }
13915 return rc;
13916}
13917
13918/**
13919 * lpfc_io_error_detected - lpfc method for handling PCI I/O error
13920 * @pdev: pointer to PCI device.
13921 * @state: the current PCI connection state.
13922 *
13923 * This routine is registered to the PCI subsystem for error handling. This
13924 * function is called by the PCI subsystem after a PCI bus error affecting
13925 * this device has been detected. When this routine is invoked, it dispatches
13926 * the action to the proper SLI-3 or SLI-4 device error detected handling
13927 * routine, which will perform the proper error detected operation.
13928 *
13929 * Return codes
13930 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
13931 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
13932 **/
13933static pci_ers_result_t
13934lpfc_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
13935{
13936 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13937 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13938 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
13939
13940 switch (phba->pci_dev_grp) {
13941 case LPFC_PCI_DEV_LP:
13942 rc = lpfc_io_error_detected_s3(pdev, state);
13943 break;
da0436e9
JS
13944 case LPFC_PCI_DEV_OC:
13945 rc = lpfc_io_error_detected_s4(pdev, state);
13946 break;
3772a991 13947 default:
372c187b 13948 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
13949 "1427 Invalid PCI device group: 0x%x\n",
13950 phba->pci_dev_grp);
13951 break;
13952 }
13953 return rc;
13954}
13955
13956/**
13957 * lpfc_io_slot_reset - lpfc method for restart PCI dev from scratch
13958 * @pdev: pointer to PCI device.
13959 *
13960 * This routine is registered to the PCI subsystem for error handling. This
13961 * function is called after PCI bus has been reset to restart the PCI card
13962 * from scratch, as if from a cold-boot. When this routine is invoked, it
13963 * dispatches the action to the proper SLI-3 or SLI-4 device reset handling
13964 * routine, which will perform the proper device reset.
13965 *
13966 * Return codes
13967 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
13968 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
13969 **/
13970static pci_ers_result_t
13971lpfc_io_slot_reset(struct pci_dev *pdev)
13972{
13973 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13974 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13975 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
13976
13977 switch (phba->pci_dev_grp) {
13978 case LPFC_PCI_DEV_LP:
13979 rc = lpfc_io_slot_reset_s3(pdev);
13980 break;
da0436e9
JS
13981 case LPFC_PCI_DEV_OC:
13982 rc = lpfc_io_slot_reset_s4(pdev);
13983 break;
3772a991 13984 default:
372c187b 13985 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
13986 "1428 Invalid PCI device group: 0x%x\n",
13987 phba->pci_dev_grp);
13988 break;
13989 }
13990 return rc;
13991}
13992
13993/**
13994 * lpfc_io_resume - lpfc method for resuming PCI I/O operation
13995 * @pdev: pointer to PCI device
13996 *
13997 * This routine is registered to the PCI subsystem for error handling. It
13998 * is called when kernel error recovery tells the lpfc driver that it is
13999 * OK to resume normal PCI operation after PCI bus error recovery. When
14000 * this routine is invoked, it dispatches the action to the proper SLI-3
14001 * or SLI-4 device io_resume routine, which will resume the device operation.
14002 **/
14003static void
14004lpfc_io_resume(struct pci_dev *pdev)
14005{
14006 struct Scsi_Host *shost = pci_get_drvdata(pdev);
14007 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
14008
14009 switch (phba->pci_dev_grp) {
14010 case LPFC_PCI_DEV_LP:
14011 lpfc_io_resume_s3(pdev);
14012 break;
da0436e9
JS
14013 case LPFC_PCI_DEV_OC:
14014 lpfc_io_resume_s4(pdev);
14015 break;
3772a991 14016 default:
372c187b 14017 lpfc_printf_log(phba, KERN_ERR, LOG_TRACE_EVENT,
3772a991
JS
14018 "1429 Invalid PCI device group: 0x%x\n",
14019 phba->pci_dev_grp);
14020 break;
14021 }
14022 return;
14023}
14024
1ba981fd
JS
14025/**
14026 * lpfc_sli4_oas_verify - Verify OAS is supported by this adapter
14027 * @phba: pointer to lpfc hba data structure.
14028 *
14029 * This routine checks to see if OAS is supported for this adapter. If
14030 * supported, the configure Flash Optimized Fabric flag is set. Otherwise,
14031 * the enable oas flag is cleared and the pool created for OAS device data
14032 * is destroyed.
14033 *
14034 **/
c7092975 14035static void
1ba981fd
JS
14036lpfc_sli4_oas_verify(struct lpfc_hba *phba)
14037{
14038
14039 if (!phba->cfg_EnableXLane)
14040 return;
14041
14042 if (phba->sli4_hba.pc_sli4_params.oas_supported) {
14043 phba->cfg_fof = 1;
14044 } else {
f38fa0bb 14045 phba->cfg_fof = 0;
c3e5aac3 14046 mempool_destroy(phba->device_data_mem_pool);
1ba981fd
JS
14047 phba->device_data_mem_pool = NULL;
14048 }
14049
14050 return;
14051}
14052
d2cc9bcd
JS
14053/**
14054 * lpfc_sli4_ras_init - Verify RAS-FW log is supported by this adapter
14055 * @phba: pointer to lpfc hba data structure.
14056 *
14057 * This routine checks to see if RAS is supported by the adapter. Check the
14058 * function through which RAS support enablement is to be done.
14059 **/
14060void
14061lpfc_sli4_ras_init(struct lpfc_hba *phba)
14062{
14063 switch (phba->pcidev->device) {
14064 case PCI_DEVICE_ID_LANCER_G6_FC:
14065 case PCI_DEVICE_ID_LANCER_G7_FC:
14066 phba->ras_fwlog.ras_hwsupport = true;
cb34990b
JS
14067 if (phba->cfg_ras_fwlog_func == PCI_FUNC(phba->pcidev->devfn) &&
14068 phba->cfg_ras_fwlog_buffsize)
d2cc9bcd
JS
14069 phba->ras_fwlog.ras_enabled = true;
14070 else
14071 phba->ras_fwlog.ras_enabled = false;
14072 break;
14073 default:
14074 phba->ras_fwlog.ras_hwsupport = false;
14075 }
14076}
14077
1ba981fd 14078
dea3101e 14079MODULE_DEVICE_TABLE(pci, lpfc_id_table);
14080
a55b2d21 14081static const struct pci_error_handlers lpfc_err_handler = {
8d63f375
LV
14082 .error_detected = lpfc_io_error_detected,
14083 .slot_reset = lpfc_io_slot_reset,
14084 .resume = lpfc_io_resume,
14085};
14086
dea3101e 14087static struct pci_driver lpfc_driver = {
14088 .name = LPFC_DRIVER_NAME,
14089 .id_table = lpfc_id_table,
14090 .probe = lpfc_pci_probe_one,
6f039790 14091 .remove = lpfc_pci_remove_one,
85e8a239 14092 .shutdown = lpfc_pci_remove_one,
3a55b532 14093 .suspend = lpfc_pci_suspend_one,
3772a991 14094 .resume = lpfc_pci_resume_one,
2e0fef85 14095 .err_handler = &lpfc_err_handler,
dea3101e 14096};
14097
3ef6d24c 14098static const struct file_operations lpfc_mgmt_fop = {
858feacd 14099 .owner = THIS_MODULE,
3ef6d24c
JS
14100};
14101
14102static struct miscdevice lpfc_mgmt_dev = {
14103 .minor = MISC_DYNAMIC_MINOR,
14104 .name = "lpfcmgmt",
14105 .fops = &lpfc_mgmt_fop,
14106};
14107
e59058c4 14108/**
3621a710 14109 * lpfc_init - lpfc module initialization routine
e59058c4
JS
14110 *
14111 * This routine is to be invoked when the lpfc module is loaded into the
14112 * kernel. The special kernel macro module_init() is used to indicate the
14113 * role of this routine to the kernel as lpfc module entry point.
14114 *
14115 * Return codes
14116 * 0 - successful
14117 * -ENOMEM - FC attach transport failed
14118 * all others - failed
14119 */
dea3101e 14120static int __init
14121lpfc_init(void)
14122{
14123 int error = 0;
14124
bc2736e9
AB
14125 pr_info(LPFC_MODULE_DESC "\n");
14126 pr_info(LPFC_COPYRIGHT "\n");
dea3101e 14127
3ef6d24c
JS
14128 error = misc_register(&lpfc_mgmt_dev);
14129 if (error)
14130 printk(KERN_ERR "Could not register lpfcmgmt device, "
14131 "misc_register returned with status %d", error);
14132
1eaff536 14133 error = -ENOMEM;
458c083e
JS
14134 lpfc_transport_functions.vport_create = lpfc_vport_create;
14135 lpfc_transport_functions.vport_delete = lpfc_vport_delete;
dea3101e 14136 lpfc_transport_template =
14137 fc_attach_transport(&lpfc_transport_functions);
7ee5d43e 14138 if (lpfc_transport_template == NULL)
1eaff536 14139 goto unregister;
458c083e
JS
14140 lpfc_vport_transport_template =
14141 fc_attach_transport(&lpfc_vport_transport_functions);
14142 if (lpfc_vport_transport_template == NULL) {
14143 fc_release_transport(lpfc_transport_template);
1eaff536 14144 goto unregister;
7ee5d43e 14145 }
5fd11085 14146 lpfc_nvme_cmd_template();
bd3061ba 14147 lpfc_nvmet_cmd_template();
7bb03bbf
JS
14148
14149 /* Initialize in case vector mapping is needed */
2ea259ee 14150 lpfc_present_cpu = num_present_cpus();
7bb03bbf 14151
93a4d6f4
JS
14152 error = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
14153 "lpfc/sli4:online",
14154 lpfc_cpu_online, lpfc_cpu_offline);
14155 if (error < 0)
14156 goto cpuhp_failure;
14157 lpfc_cpuhp_state = error;
14158
dea3101e 14159 error = pci_register_driver(&lpfc_driver);
93a4d6f4
JS
14160 if (error)
14161 goto unwind;
14162
14163 return error;
14164
14165unwind:
14166 cpuhp_remove_multi_state(lpfc_cpuhp_state);
14167cpuhp_failure:
14168 fc_release_transport(lpfc_transport_template);
14169 fc_release_transport(lpfc_vport_transport_template);
1eaff536
JX
14170unregister:
14171 misc_deregister(&lpfc_mgmt_dev);
dea3101e 14172
14173 return error;
14174}
14175
372c187b
DK
14176void lpfc_dmp_dbg(struct lpfc_hba *phba)
14177{
14178 unsigned int start_idx;
14179 unsigned int dbg_cnt;
14180 unsigned int temp_idx;
14181 int i;
14182 int j = 0;
14183 unsigned long rem_nsec;
14184
14185 if (phba->cfg_log_verbose)
14186 return;
14187
14188 if (atomic_cmpxchg(&phba->dbg_log_dmping, 0, 1) != 0)
14189 return;
14190
14191 start_idx = (unsigned int)atomic_read(&phba->dbg_log_idx) % DBG_LOG_SZ;
14192 dbg_cnt = (unsigned int)atomic_read(&phba->dbg_log_cnt);
14193 temp_idx = start_idx;
14194 if (dbg_cnt >= DBG_LOG_SZ) {
14195 dbg_cnt = DBG_LOG_SZ;
14196 temp_idx -= 1;
14197 } else {
14198 if ((start_idx + dbg_cnt) > (DBG_LOG_SZ - 1)) {
14199 temp_idx = (start_idx + dbg_cnt) % DBG_LOG_SZ;
14200 } else {
77dd7d7b 14201 if (start_idx < dbg_cnt)
372c187b 14202 start_idx = DBG_LOG_SZ - (dbg_cnt - start_idx);
77dd7d7b 14203 else
372c187b 14204 start_idx -= dbg_cnt;
372c187b
DK
14205 }
14206 }
14207 dev_info(&phba->pcidev->dev, "start %d end %d cnt %d\n",
14208 start_idx, temp_idx, dbg_cnt);
14209
14210 for (i = 0; i < dbg_cnt; i++) {
14211 if ((start_idx + i) < DBG_LOG_SZ)
77dd7d7b 14212 temp_idx = (start_idx + i) % DBG_LOG_SZ;
372c187b
DK
14213 else
14214 temp_idx = j++;
14215 rem_nsec = do_div(phba->dbg_log[temp_idx].t_ns, NSEC_PER_SEC);
14216 dev_info(&phba->pcidev->dev, "%d: [%5lu.%06lu] %s",
14217 temp_idx,
14218 (unsigned long)phba->dbg_log[temp_idx].t_ns,
14219 rem_nsec / 1000,
14220 phba->dbg_log[temp_idx].log);
14221 }
14222 atomic_set(&phba->dbg_log_cnt, 0);
14223 atomic_set(&phba->dbg_log_dmping, 0);
14224}
14225
7fa03c77 14226__printf(2, 3)
372c187b
DK
14227void lpfc_dbg_print(struct lpfc_hba *phba, const char *fmt, ...)
14228{
14229 unsigned int idx;
14230 va_list args;
14231 int dbg_dmping = atomic_read(&phba->dbg_log_dmping);
14232 struct va_format vaf;
14233
14234
14235 va_start(args, fmt);
14236 if (unlikely(dbg_dmping)) {
14237 vaf.fmt = fmt;
14238 vaf.va = &args;
14239 dev_info(&phba->pcidev->dev, "%pV", &vaf);
14240 va_end(args);
14241 return;
14242 }
14243 idx = (unsigned int)atomic_fetch_add(1, &phba->dbg_log_idx) %
14244 DBG_LOG_SZ;
14245
14246 atomic_inc(&phba->dbg_log_cnt);
14247
14248 vscnprintf(phba->dbg_log[idx].log,
14249 sizeof(phba->dbg_log[idx].log), fmt, args);
14250 va_end(args);
14251
14252 phba->dbg_log[idx].t_ns = local_clock();
14253}
14254
e59058c4 14255/**
3621a710 14256 * lpfc_exit - lpfc module removal routine
e59058c4
JS
14257 *
14258 * This routine is invoked when the lpfc module is removed from the kernel.
14259 * The special kernel macro module_exit() is used to indicate the role of
14260 * this routine to the kernel as lpfc module exit point.
14261 */
dea3101e 14262static void __exit
14263lpfc_exit(void)
14264{
3ef6d24c 14265 misc_deregister(&lpfc_mgmt_dev);
dea3101e 14266 pci_unregister_driver(&lpfc_driver);
93a4d6f4 14267 cpuhp_remove_multi_state(lpfc_cpuhp_state);
dea3101e 14268 fc_release_transport(lpfc_transport_template);
458c083e 14269 fc_release_transport(lpfc_vport_transport_template);
7973967f 14270 idr_destroy(&lpfc_hba_index);
dea3101e 14271}
14272
14273module_init(lpfc_init);
14274module_exit(lpfc_exit);
14275MODULE_LICENSE("GPL");
14276MODULE_DESCRIPTION(LPFC_MODULE_DESC);
d080abe0 14277MODULE_AUTHOR("Broadcom");
dea3101e 14278MODULE_VERSION("0:" LPFC_DRIVER_VERSION);